Compal LA-e811p Schematic

A

Aditya11ttt.com

1 1

2 2

B

C

D

E

Kabylake-U M/B Schematics Document

Intel ULV Processor with DDR4 SODIMMx2

Date : 2016/05/11

3 3

Project :

4 4

A

B

Version : 0.2

(PV phase)

Diner_Crepe1.1(15")

BDL50 : LA-D707P

(Modifie d Source :LA-D7 04PR2 0_2016 -04-20)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTYOF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTYOF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANYTHIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANYTHIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/29 2011/06/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet

D

Date : Sheet

Compal Electronics, Inc.

Cover Page

Document Number Re v

Cover Page

LA-D707P

1 60Wednesday, May 11, 2016

o f

E

o f

v0.2

A

Aditya11ttt.com

B

C

D

E

Compal Confidential

Model Name : File Name :

1 1

2 2

3 3

Diner_Crepe1.1(15")

LA-D707P

VRAM gDDR3 x4pcs

25 6Mb x 16 ( 4Gb ) 51 2Mb x 16 ( 8Gb )

eDP/LVDS

CONN

FHD

CRT CONN

HDMI CONN

P. 4 0 ~42

JL V D S 1

P. 2 0

P. 2 2

JH D M I 1

P. 2 1

1Ch 64bits 1.5V

R16M-M1-70 D3(R7) R16M-M1-30 D3(R5)

eDP to LVDS Transmitter

RTD2132N

CRT

NGFF WLAN+BT

(Key E)

DP to VGA Transmitter

RTD2168

HDMI

LAN

RT L8 111 HS H (G iga ) RT L8 166 EH( 10/ 10 0 )

JW L AN 1

LVDS @

eDP@

P. 3 2

AMD

P. 3 6 ~40

U T 1

P. 1 9

U 4 1 0 4JC R T 1

P. 2 2

UL 1

P. 2 3

PCIe 1.0:2.5Gb/s PCIe 2.0:5Gb/s

U 6 6 6

PCIex4

Port #1~#4

PCIe 2.0:5Gb/s PCIe 3.0:8Gb/s

eDP

x1Lane

2.7Gb/s

eDPx2Lane

2.7Gb/s

DDI

x2Lane

DDI

x4Lane

297MHz

Port #5

PCIex1

PCIe Gen1:2.5Gb/s PCIe Gen2:5Gb/s

Port #6

PCIex1

SMbus

Port 2

Port 1

1MHz

Kabylake-U

Skylake-U

1356P BGA

KBL-U 15W 2+2

SKL-U 15W 2+2

U C 1

GEN1 1.5Gb/s GEN2 3Gb/s GEN3 6Gb/s

Dual Channel

DDR4 2133MHz 1.2V

SATA 3.0

USB3.0

5Gb/s

USB2.0 480Mb/s

Interleaved

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

DDR4-SO-DIMM X 2

2.5" SATA HDD

ODD

USB3.0 port

(onboard-1)

USB2.0 port

(onboard-2)

USB2.0 Port

(sub board)

Bluetooth

Camera

Touch Screen

Card reader RTS5141

(sub board)

J H D D

P. 3 0

JO D D

P. 3 0

JU S B 1

P. 3 1

JU S B 2

P. 3 1

JI O 1

P. 3 3

JW L AN 1

P. 3 2

JL V D S 1

P. 2 0

JL V D S 1

P. 2 0

JI O 1

P. 3 3

P. 1 7 ~18

Port 1

U K 1

P. 2 6

TPM

P. 2 8

*default FWTPM

U 4

U C 2

P. 0 7

LPC 33MHz

SPI 50MHz

U A 1

24MHz

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/29 2011/06/29

HDA Aduio codec ALC3227

Compal Secret Data

Deciphered Date

P. 2 4

D

JS P K 1

Internal SPK

Combo Jack

J H P

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet

Compal Electronics, Inc.

Document Number Re v

LA-D707P

Block Diagrams

E

v0.2

2 60Wednesday, May 11, 2016

v0.2

of

FAN

JK B 1

P. 2 7

J T P 1

PS2 HDA

EC ENE

KB 9 0 22Q D

P. 2 7

P. 3 4

JP W R

P. 3 3

U C 3

P. 1 0NC T 7 7 1 8 W

SL B 966 5 T T2. 0

SPI ROM 8MBytes

B

Int.KBD

TouchPad

Lid switch

(sub board)

4 4

A

Thermal sensor

A

Stuf f

Aditya11ttt.com

Power rail

+RTCVCC

VIN

BATT+

B+

+VL

+3VL

+5VALW

+3VALW

+3VALW_EC

1 1

+3V_PCH

+1.2V_VDDQ

+5VS

+3VS

+1.5VS

+1.05VS

+0.6V_0.6VS

+VCC_CORE

Control (EC)

X

EC_ON

PCH_PWR_EN

SYSON

SUSP#

X

Source (CPU)

X

PM_SLP_S5#/PM_SLP_S4#

PM_SLP_S3#

VR12.5_VR_ON

BOM Structure Table (1/2)

C_SMB_DA1

A

Un-Stuf f

+3VS

R=1K

+3VS

R=499

+3VS

R=1K

+3VS

R=1K

+3VL_EC

R=2.2K

+3VS

2N7002

Touch Screen

QKKS@

UC1

ES_QKKS

S IC A32 FJ8067702739720 QKKS G0 2.4G

QS_i3@

UC1

i3_7100U_QS_QLDP

SA0000A3810 S IC A32 FJ8067702739738 QLDP H0 2.4G

R30@

U666

R16M-M1-30 FCBGA

SA000087T90 S IC A32 216-0867-071 R16M-M1-30 FCBGA

+3VS

2N7002

+3VS

2N7002

+3VS

R=2.2K

EC_SMB_CK2 EC_SMB_DA2

R=100

SA00009PJ10

+3VS

R=10K

+3VALW

R=2.2K

DGPU_PEX _RST#

2N7002

Thermal Sensor :NCT7718W_MSOP8

BAT

Charger

Funct i on

DGPU SKU

UMA SKU

SPI_IO3(MOW36)

Crystal (DIS) Crystal XTAL@

Green CLK(UMA)

Green CLK(DIS)

2 2

UCPU1

3 3

CPU

UK1:+3VALW_EC

4 4

(+3VL)

R7 R8

R9 W2

W3 V3

U6 U7

U9 U8

79 80

PX@

UMA@

ES@

XTALPX@

GCLK@

GCLKPX@

TPM@TPM

SMBCLK SMBDATA

SML0CLK SML0DATA

SML1CLK SML1DATA

I2C_0_SCL

I2C_0_SDA

I2C_1_SCL

I2C_1_SDA

EC_SMB_CK2 EC_SMB_DA2

EC

EC_SMB_CK1

77

E

78

B

QKJW@

UC1

ES_QKJW

S IC A32 FJ8067702739718 QKJW G0 2.6G

QS_i5@

UC1

i5_7200U_QLDM

SA0000A3710 S IC A32 FJ8067702739739 QLDM H0 2.5G

R70@

U666

R16M-M1-70 FCBGA

SA000098V10 S IC A32 216-0864-032 R16M-M1-70 FCBGA

PCH_SMBCLK PCH_SMBDATA

TP_SMBCLK TP_SMBDAT

+3VGS_AON

R=2.2K

I2CS_SCL

I2CS_SDA

Address : 0x4C

B

SOC SMBUS Address Table

SOC_SMBUS Net Name

SMBCLK SMBDATA

SML0CLK SML0DATA

SML1CLK SML1DATA

SA00009UR00

i7_7500U_QLDN

SA0000A3420 S IC A32 FJ8067702739740 QLDN H0 2.7G

SO-DIMM B

Touch Pad

dGPU

Power Rail

+3VS

SKLPV2@

UC1

SA000092P60

SKY_i7_6500U_SR2EZ

S IC FJ8066201930408 SR2EZ D1 2.5G BGA

QS_i7@

UC1

C

(TBC)

Device

DIMM1

Address (7 bit)

TBC

Touch PAD TBC T BC TBC

ME FW

EC

DGPU

0x48/0x49

TBC

Address (8bit) Write Read

0xA2

TBC

0x90/0x92

TBC

TBC T BC

TBCTBC

D

EC SMBUS Address Table

EC_SMBUS Port

SMBUS Port 1

SMBUS Port 2

PCH TBC T BC TBC

DAX

KBL

Part Number = DA6001LS000 PCB 1RU LA-D707P REV0 M/B 6

ROYALTY HDMI W/LOGO45@

Part Number Description

HDMI W/Logo:RO0000002HM

RO0000002HM

RO0000003HM

R30R1@

U666

R16M-M1-30 FCBGA

SA000087TC0 S IC A32 216-0867-071 R16M-M1-30 FCBGA

R30R3@

U666

R16M-M1-30 FCBGA

SA000087TB0 S IC A32 216-0867-071 R16M-M1-30 FCBGA

i3R1@

UC1

SA000092N70

ES_QKKS

S IC A32 FJ8067702739720 QKKS G0 2.4G

i3R3@

UC1

SA000092N80

ES_QKKS

S IC A32 FJ8067702739720 QKKS G0 2.4G

ZZZ

HY2@

MIC2@

2G HYNIX

2G MICRON

X7667032L01

X7667032L02

ZZZ

R3MIC2@

R3HY2@

2G MICRON

2G HYNIX

X7667032L24

X7667032L23

DAX

SKL

Part Number = DAZ1O200301 PCB BDL50 LA-D704P LS-C701P/C703P 02

SKL@

R70R1@

U666

R16M-M1-70 FCBGA

SA000098V30 S IC A32 216-0864-032 R16M-M1-70 FCBGA

R70R3@

U666

R16M-M1-70 FCBGA

SA000098V40 S IC A32 216-0864-032 R16M-M1-70 FCBGA

i5R1@

UC1

SA000092O70

ES_QKKS

S IC A32 FJ8067702739720 QKKS G0 2.4G

i5R3@

UC1

SA000092O80

ES_QKKS

S IC A32 FJ8067702739720 QKKS G0 2.4G

ZZZ

SAM2@

2G SAMSUNG

X7667032L05

ZZZ

R3SAM2@

2G SAMSUNG

X7667032L25

ZZZ

HY4@

4G Hynix

X7667032L03

ZZZ

R3HY4@

4G Hynix

X7667032L21

ZZZ

MIC4@

4G Micron

X7667032L04

ZZZ

R3MIC4@

4G Micron

X7667032L22

Power State

STATE

S0 (Full ON)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Sof t OFF)

i7R1@

UC1

SA000092P60

ES_QKKS

S IC A32 FJ8067702739720 QKKS G0 2.4G

i7R3@

UC1

SA000092P70

ES_QKKS

S IC A32 FJ8067702739720 QKKS G0 2.4G

SIGNAL

<PCI-E,SATA,USB3.0/CLK>

Lane#

Load BOM Opt i on Tabl e

BOM Number Load BOM Opt i on

4519YN32L01(UMA)

4519YN32L02(DIS)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/29 2011/06/29

Compal Secret Data

Deciphered Date

D

E

(TBC)

Power Rail Device Address (7 bit)

+3VL_EC

+3VS

BAT

CHGR

dGPU

Thermal

Sensor

0x16

0x12

TBC

0x4C

PCH TBC

SLP_S4#

SLP_S3#

HIGH HIGH HIGH

HIGH

LOW

LOWLOW

LOW LOW LOW

+VALW

SLP_S5#

ON ON ON ON

HIGH

ONONON

HIGH

ON

+V

OFF

+VS Clock

OFF

<USB2.0 port>

USB2.0 port

1 2

USB 2.0 OFF BOARD

3 4 5 6 7 8 9 10

PCI-E

SATA

1 2 3 4 5

1

6

2

7

3 4

8 9

5

10

6

11

7

12 ODD

8

13

9

14

10

15

11

16

12

0 1

1*

2

TOUCH SCREEN

USB3.0

1 2 3 4 5 6

DESTINATION

UMA

USB 2.0/3.0 USB 2.0/3.0 USB 2.0/3.0

WLAN WLAN

Camera Camera

CR CR

USB 2.0/3.0

USB 2.0 OFF BOARD

TOUCH SCREEN

DESTINATION

UMA

U

SB3.0

USB3.0 USB3.0

USB3.0(Charger) USB3.0(Charger)

USB3.0(IO Board)USB3.0(IO Board)

X X X X

LAN LAN

WLAN WLAN

2.5"HDD 2.5"HDD ODD

Card reader(PCI-E)

X X

Title

Size

Document Number Re v

Custom

Date: Sheet

Dis

USB3.0

GPU(DIS only) GPU(DIS only) GPU(DIS only) GPU(DIS only)

Card reader(PCI-E)

Compal Electronics, Inc.

Notes List

LA-D707P

E

Dis

CLK

X X X X

CLK0

CLK1 CLK2

X X

CLK3 X X

X X X

of

3 60Wednesday, May 11, 2016

v0.2

[Diner-PWR Sequence_SKL-U22_DDR3L_Volume_NON CS]

Aditya11ttt.com

5

4

3

2

1

G3->S0 S0->S3

+3VL_RTC

SOC_RTCRST#

+19VB

+3VLP/+5VLP

D D

EC_ON

+5VALW/+3VALW/+ 3VALW_DSW

PM_BATLOW#

PCH_PWR_EN (SLP_SUS#)

+3V_PRIM

+1.8V_PRIM

EXT_PWR_GATE#

+1.0V_MPHYPLL

+1.0V_PRIM_CORE

+1.0V_PRIM

SUSACK#

PCH_DPWROK

EC_RSMRST#

C C

AC_PRESENT

ON/OFF

PBTN_OUT#

PM_SLP_S5#

ESPI_RST#

PM_SLP_S4#

SYSON

+1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC

PM_SLP_S3#

SUSP#

+1.0VS_VCCSTG

+1.0VS_VCCIO

B B

+5VS/+3VS/+1. 5VS/+1.05VS

EC_VCCST_PG

VR_ON

SM_PG_CTRL

+0.675VS_VTT

+VCC_SA

+VCC_CORE

+VCC_GT

VR_PWRGD

PCH_PWROK

H_CPUPWRGD

SYS_PWROK

A A

SUS_STAT#

SOC_PLTRST#

tPCH01_Min : 9 ms

tPCH06_Min : 200 us

tPCH04_Min : 9 ms

Pull-up to DSW well if not implemented.

If EXT_PWR_GATE# Toffmin is too small, Pwr gate may choose to completely ignore it

tPCH34_Max : 20 ms

tPCH02_Min : 10 ms

tPCH03_Min : 10 ms

tPLT02_Min : 0 ms Max : 90 ms

Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

tPCH18_Min : 90 us

tCPU04 Min : 100 ns

tCPU10 Min : 1 ms

T4 = Min : 20ms Max : 30ms(EC Control)

tCPU19 Max : 100 ns

tCPU18 Max : 35 us

tCPU09 Min : 1 ms

tCPU16 Min : 0 ns

/DS3

->S0

DS3S0/

S0->S5

+3VL_RTC

SOC_RTCRST#

+19VB

+3VLP/+5VLP

EC_ON

+5VALW/+3VALW/+ 3VALW_DSW

PM_BATLOW#

PCH_PWR_EN (SLP_SUS#)

+3V_PRIM

+1.8V_PRIM

EXT_PWR_GATE#

+1.0V_MPHYPLL

+1.0V_PRIM_CORE

+1.0V_PRIM

SUSACK#

PCH_DPWROK

EC_RSMRST#

AC_PRESENT

ON/OFF

PBTN_OUT#

PM_SLP_S5#

ESPI_RST#

PM_SLP_S4#

SYSON

+1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC

PM_SLP_S3#

SUSP#

+1.0VS_VCCSTG

+1.0VS_VCCIO

+5VS/+3VS/+1. 5VS/+1.05VS

EC_VCCST_PG

VR_ON

SM_PG_CTRL

+0.675VS_VTT

+VCC_SA

+VCC_CORE

+VCC_GT

VR_PWRGD

PCH_PWROK

H_CPUPWRGD

SYS_PWROK

SUS_STAT#

SOC_PLTRST#

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Document Number Rev

Custom

Date: Sheet

LA-D707P

HW Reserve

1

4 60Wednesday, May 11, 2016

v0.2

of

A

Aditya11ttt.com

B

C

D

E

UC1A

AT16 AU16

D63 A54 C65 C63 A65

C55 D55 B54 C56

A6

A7 BA5 AY5

H66 H65

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKL-U_BGA1356

UC1D

CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#

CPU MISC

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

SKL-U_BGA1356

SKL-U

4 OF 20

PCH_DPB_N2<21>

PCH_DPB_P2<21>

SOC_DP1_CTRL_DATA(Internal Pull Down):

<HDMI>

Display Port B Detected

1 1

0 = Port B is not detected.

1 = Port B is detected.

PCH_DPB_N1<21>

PCH_DPB_P1<21>

PCH_DPB_N0<21>

PCH_DPB_P0<21>

PCH_DPB_N3<21>

PCH_DPB_P3<21>

PCH_DPC_N0<22>

PCH_DPC_P0<22>

PCH_DPC_N1<22>

PCH_DPC_P1<22>

SOC_DP2_CTRL_DATA(Internal Pull Down):

Display Port C Detected

0 = Port C is not detected.

1 = Port C is detected.

HDMI DDC (Port B)

PCH_DDPB_CLK<21> PCH_DDPB_DAT<21>

+3VS

<DB> DP port C enable

+1.0V_VCCST

H_THERMTRIP#

1 2

RC2 1K_0402_5%

2 2

COMPENSATION PU FOR eDP

+1.0VS_VCCIO

EDP_COMP

1 2

RC1

CAD note: Trace width=20 mils,Spacing=25mil,Max length=100mils

24.9_0402_1%

PROCHOT#<26>

+1.0VS_VCCIO

12

RC3 1K_0402_5%

RC4 499_0402_1%

12

DS11 CK0402101V05_0402-2

ESD@

SCV00001K00

T248 TP@

12 12 12 12

H_PECI<26>

T25 TP@

T270 TP@ T271 TP@ T250 TP@ T249 TP@

T30 TP@

T40 TP@

1 2

RC5 49.9_0402_1% RC6 49.9_0402_1% RC7 49.9_0402_1% RC8 49.9_0402_1%

PCH_DDPB_CLK PCH_DDPB_DAT

1 2

RC200 2.2K_0402_5%@

1 2

RC199 2.2K_0402_5%

CRT@

EDP_COMP

H_PECI

H_PROCHOT#_R H_THERMTRIP# SOC_OCC#

XDP_BPM#0 XDP_BPM#1

SOC_GPIOE3

SOC_GPIOB4

CPU_POPIRCOMP PCH_OPIRCOMP EDRAM_OPIO_RCOMP EOPIO_RCOMP

SKL-U

DDI

DISPLAY SIDEBANDS

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

1 OF 20

Rev_0.5 3

JTAGX

EDP

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

Rev_0.5 3

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

CPU_XDP_TCK0 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST#

PCH_JTAG_TCK1 SOC_XDP_TDI

SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST# CPU_XDP_TCK0

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52

G50 F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

DDI2_AUX_DN DDI2_AUX_DP

PCH_DDPB_HPD DDI2_HPD NMI_DBG#_CPU EC_SCI# EDP_HPD

ENBKL

ENVDD_CPU

T259TP@ T260TP@ T261TP@ T262TP@ T263TP@

T264TP@ T265TP@ T266TP@ T267TP@ T268TP@ T269TP@

EDP_CPU_LANE_N0_C <19> EDP_CPU_LANE_P0_C <19> EDP_CPU_LANE_N1_C <19> EDP_CPU_LANE_P1_C <19>

EDP_CPU_AUX#_C <19> EDP_CPU_AUX_C <19>

T228TP@

DDI2_AUX_DN <22> DDI2_AUX_DP <22>

PCH_DDPB_HPD <21> DDI2_HPD <22> NMI_DBG#_CPU <10,26> EC_SCI# <10,26> EDP_HPD <19>

ENBKL <26> BKL_PWM_CPU <20> ENVDD_CPU <20>

1 2

RC123 100K_0402_5%@

1 2

RC124 100K_0402_5%

<eDP >

From HDMI From eDP to CRT

From eDP

ENVDD_CPU

ENBKL

<DB> Check

XDP CONN

3 3

+1.0VS_VCCIO

RC11 51_0402_5%@

RC13 51_0402_5%@

RC15 51 +-1% 0402 SD000008H80

RC364 51_0402_5%@

+1.0V_PRIM

RC14 51_0402_5%@

RC31 1K_0402_5%@

4 4

RC365 51_0402_1%@

RC35 51_0402_1% SD000008H80

RC37 51_0402_5%@

RC366 0_0402_5%@

12

1 2

12

1 2

A

SOC_XDP_TMS

SOC_XDP_TDI

SOC_XDP_TDO

CPU_XDP_TCK0

XDP_PREQ#

XDP_ITP_PMODE

SOC_XDP_TRST#

CPU_XDP_TCK0

PCH_JTAG_TCK1

CFG3

XDP_PREQ# <11>

XDP_ITP_PMODE <16>

CFG3 <16>

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet

Compal Electronics, Inc.

SKL-U(1/12)DDI,MSIC,XDP,EDP

Document Number Re v

LA-D707P

E

5 60Wednesday, May 11, 2016

v0.2

o f

5

Aditya11ttt.com

Interleaved Memory

4

3

2

1

Interleaved Memory

D D

UC1B

DDR_A_D[0..15]<17>

DDR_A_D[16..31]<17>

C C

DDR_A_D[32..47]<17>

DDR_A_D[48..63]<17>

B B

A A

DDR_A_D0

AL71

DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

SB00000QJ00,S TR DRC5115E0L NPN SOT323-3

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKL-U_BGA1356

12

RC905

100K_0402_5%

@

12

RC906

100K_0402_5%

DDR_PG_CTRL SM_PG_CTRL

@

DDR CH - A

2 OF 20

+1.2V_VDDQ

12

RC904 100K_0402_5%

@

2

13

@

UC9

SB000008E10

MMBT3904WH NPN SOT323-3

<Cocoa_1020> PDG#543016, ODT: CPU side no connect, DRAM side connect to VDDQ(Memory down); FET+R(SO-DIMM)

SKL-U

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

DDR_A_CLK#0

AU53

DDR_A_CLK0

AT53

DDR_A_CLK#1

AU55

DDR_A_CLK1

AT55

DDR_A_CKE0

BA56

DDR_A_CKE1

BB56 AW56 AY56

DDR_A_CS#0

AU45

DDR_A_CS#1

AU43

DDR_A_ODT0

AT45

DDR_A_ODT1

AT43

DDR_A_MA5

BA51

DDR_A_MA9

BB54

DDR_A_MA6

BA52

DDR_A_MA8

AY52

DDR_A_MA7

AW52

DDR_A_BG0

AY55

DDR_A_MA12

AW54

DDR_A_MA11

BA54

DDR_A_ACT#

BA55

DDR_A_BG1

AY54

DDR_A_MA13

AU46

DDR_A_MA15_CAS#

AU48

DDR_A_MA14_WE#

AT46

DDR_A_MA16_RAS#

AU50

DDR_A_BA0

AU52

DDR_A_MA2

AY51

DDR_A_BA1

AT48

DDR_A_MA10

AT50

DDR_A_MA1

BB50

DDR_A_MA0

AY50

DDR_A_MA3

BA50

DDR_A_MA4

BB52

DDR_A_DQS#0

AM70

DDR_A_DQS0

AM69

DDR_A_DQS#1

AT69

DDR_A_DQS1

AT70

DDR_A_DQS#2

BA64

DDR_A_DQS2

AY64

DDR_A_DQS#3

AY60

DDR_A_DQS3

BA60

DDR_A_DQS#4

BA38

DDR_A_DQS4

AY38

DDR_A_DQS#5

AY34

DDR_A_DQS5

BA34

DDR_A_DQS#6

BA30

DDR_A_DQS6

AY30

DDR_A_DQS#7

AY26

DDR_A_DQS7

BA26

DDR_A_ALERT#

AW50

DDR_A_PAR

AT52

+0.6V_VREFCA

AY67 AY68

+0.6V_B_VREFDQ

BA67

DDR_PG_CTRL

AW67

For VTT power control

DDR_PG_CTRL

DDR_A_CLK#0 <17> DDR_A_CLK0 <17> DDR_A_CLK#1 <17> DDR_A_CLK1 <17>

DDR_A_CKE0 <17>

DDR_A_CKE1 <17>

T14TP@ T15TP@

DDR_A_CS#0 <17>

DDR_A_CS#1 <17>

DDR_A_ODT0 <17>

DDR_A_ODT1 <17> DDR_B_ODT0 <18>

DDR_A_MA5 <17>

DDR_A_MA9 <17>

DDR_A_MA6 <17>

DDR_A_MA8 <17>

DDR_A_MA7 <17>

DDR_A_BG0 <17>

DDR_A_MA12 <17>

DDR_A_MA11 <17>

DDR_A_ACT# <17>

DDR_A_BG1 <17>

DDR_A_MA13 <17>

DDR_A_MA15_CAS# <17>

DDR_A_MA14_WE# <17>

DDR_A_MA16_RAS# <17>

DDR_A_BA0 <17>

DDR_A_MA2 <17>

DDR_A_BA1 <17>

DDR_A_MA10 <17>

DDR_A_MA1 <17>

DDR_A_MA0 <17>

DDR_A_MA3 <17>

DDR_A_MA4 <17>

DDR_A_DQS#0 <17>

DDR_A_DQS0 <17>

DDR_A_DQS#1 <17>

DDR_A_DQS1 <17>

DDR_A_DQS#2 <17>

DDR_A_DQS2 <17>

DDR_A_DQS#3 <17>

DDR_A_DQS3 <17>

DDR_A_DQS#4 <17>

DDR_A_DQS4 <17>

DDR_A_DQS#5 <17>

DDR_A_DQS5 <17>

DDR_A_DQS#6 <17>

DDR_A_DQS6 <17>

DDR_A_DQS#7 <17>

DDR_A_DQS7 <17>

DDR_A_ALERT# <17>

DDR_A_PAR <17>

+0.6V_VREFCA

+0.6V_B_VREFDQ

+1.2V_VDDQ

12

NC1VCC

A

GND

CC570.1U_0201_10V6K

5

4

Y

UC7

2

3

SN74AUP1G07DCKR_SC70-5

SA00007UR00

+3VS

12

RC394 100K_0402_5%

DDR_B_D[0..15]<18>

DDR_B_D[16..31]<18>

DDR_B_D[32..47]<18>

DDR_B_D[48..63]<18>

SM_PG_CTRL <49>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

UC1C

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKL-U_BGA1356

+1.2V_VDDQ

12

DDR_DRAMRST# DDR_DRAMRST#_R

SKL-U

DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR CH - B

3 OF 20

RC32 470_0402_5%

1 2

RC33 0_0402_5%

Rev_0.5 3Rev_0.5 3

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]

1

CC155

0.1U_0201_10V6K

@ESD@

2

DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

DDR_DRAMRST#_R <17,18>

9/8 Modify base on ESD Request

PLACE NEAR TO SoC

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32 AR25 AR27 AR22 AR21

AN43 AP43 AT13 AR18 AT18 AU18

DDR_B_CLK#0 DDR_B_CLK#1 DDR_B_CLK0 DDR_B_CLK1

DDR_B_CKE0 DDR_B_CKE1

DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0 DDR_B_ODT1

DDR_B_MA5 DDR_B_MA9 DDR_B_MA6 DDR_B_MA8 DDR_B_MA7 DDR_B_BG0 DDR_B_MA12 DDR_B_MA11 DDR_B_ACT# DDR_B_BG1

DDR_B_MA13 DDR_B_MA15_CAS# DDR_B_MA14_WE# DDR_B_MA16_RAS# DDR_B_BA0 DDR_B_MA2 DDR_B_BA1 DDR_B_MA10 DDR_B_MA1 DDR_B_MA0 DDR_B_MA3 DDR_B_MA4

DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7

DDR_B_ALERT# DDR_B_PAR DDR_DRAMRST# SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

DDR_B_CLK#0 <18> DDR_B_CLK#1 <18> DDR_B_CLK0 <18> DDR_B_CLK1 <18>

DDR_B_CKE0 <18>

DDR_B_CKE1 <18>

T17TP@ T18TP@

DDR_B_CS#0 <18>

DDR_B_CS#1 <18>

DDR_B_ODT1 <18>

DDR_B_MA5 <18>

DDR_B_MA9 <18>

DDR_B_MA6 <18>

DDR_B_MA8 <18>

DDR_B_MA7 <18>

DDR_B_BG0 <18>

DDR_B_MA12 <18>

DDR_B_MA11 <18>

DDR_B_ACT# <18>

DDR_B_BG1 <18>

DDR_B_MA13 <18>

DDR_B_MA15_CAS# <18>

DDR_B_MA14_WE# <18>

DDR_B_MA16_RAS# <18>

DDR_B_BA0 <18>

DDR_B_MA2 <18>

DDR_B_BA1 <18>

DDR_B_MA10 <18>

DDR_B_MA1 <18>

DDR_B_MA0 <18>

DDR_B_MA3 <18>

DDR_B_MA4 <18>

DDR_B_DQS#0 <18>

DDR_B_DQS0 <18>

DDR_B_DQS#1 <18>

DDR_B_DQS1 <18>

DDR_B_DQS#2 <18>

DDR_B_DQS2 <18>

DDR_B_DQS#3 <18>

DDR_B_DQS3 <18>

DDR_B_DQS#4 <18>

DDR_B_DQS4 <18>

DDR_B_DQS#5 <18>

DDR_B_DQS5 <18>

DDR_B_DQS#6 <18>

DDR_B_DQS6 <18>

DDR_B_DQS#7 <18>

DDR_B_DQS7 <18>

DDR_B_ALERT# <18>

DDR_B_PAR <18>

1 2

RC38 121_0402_1%

1 2

RC39 80.6_0402_1%

1 2

RC40 100_0402_1%

DDR_PG_CTRL

@ESD@

1 2

CC70 100P_0402_50V8J

From ESD Team Request

8/10 Modify for DDR4

9/8 Modify

8/10 Modify for DDR4

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date: Sheet

2

Date: Sheet

SKL-U(2/12)DDRIII

Document Number Re v

LA-D707P

Wednesday, May 11, 2016

1

60

of

6

of

6

of

6

v0.2

5

Aditya11ttt.com

PCH_SPI_CLK PCH_SPI_SO PCH_SPI_SI PCH_SPI_SIO2 PCH_SPI_SIO3 PCH_SPI_CS0#

D D

12/11_Delete TP

To TPM

C C

B B

A A

PCH_SPI_CS0#_R PCH_SPI_CS0#_R PCH_SPI_SO_R PCH_SPI_SO_R

PCH_SPI_SI_R PCH_SPI_SI_R EC_SPI_SI

SPI ROM ( 8MByte Only)

PCH_SPI_CS0#_R

PCH_SPI_WP#

EON SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P MXIC SA00006N100 S IC FL 64M MX25L6473EM2I-10G SOP 8P WINBOND SA000039A30 S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM Micron SA00005L100 S IC FL 64M N25Q064A13ESEC0F SO8W 8P

1 8 2 7 3 6 4 5

15_0804_8P4R_5%

1 8 2 7 3 6 4 5

15_0804_8P4R_5%

RC388 15_0402_5%

UC2

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

W25Q64FVSSIQ_SO8

PCB Footprint = ACES_91960-0084L_8P-T

Use socket footprint

RC368

15_0402_5%

12

EMI@

EC_KBRST#<26>

SERIRQ<26,28>

Source Fromto SPI ROM UC2

RPH11

EC_SPI_CS0# PCH_SPI_CS0# EC_SPI_SO PCH_SPI_SO

RPH12

PCH_SPI_SIO3PCH_SPI_HOLD# PCH_SPI_SI

PCH_SPI_SIO2PCH_SPI_WP#

12

+3V_SPI

8

VCC

PCH_SPI_HOLD#PCH_SPI_SO_R

7

/HOLD(IO3)

PCH_SPI_CLK_RPCH_SPI_CLK

CC9 10P_0402_50V8J

@EMI@

PCH_SPI_CLK_R

6

CLK

PCH_SPI_SI_R

5

DI(IO0)

SA000039A30

SPI ROM: Main:SA000039A30, S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM 2nd :SA00007LA10, S IC FL 64M GD25B64CSIGR SOP 8P SPI ROM 3rd :SA000099300, S IC FL 64M N25Q064A13ESEDFF SO8W 8P SPI

1 2

EC_KBRST#

SERIRQ

LPC Mode

EC_SPI_CS0# <26>

EC_SPI_SO <26>

EC_SPI_SI <26>

CC8

1 2

0.1U_0402_16V7K

PCH_SPI_CLK_R <26>

AV2

AW3

AV3

AW2

AU4 AU3 AU2 AU1

AW13

AY11

M2 M3

J4 V1 V2 M1

G3 G2 G1

4

UC1E

SPI - FLASH

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

C LINK

CL_CLK CL_DATA CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

SKL-U_BGA1356

QC1A

6 1

SMBCLK

2N7002DWH_SOT363-6

SB00000I700

SMBDATA

2N7002DWH_SOT363-6

SML1CLK

SML1DATA

SMBCLK

2N7002DWH_SOT363-6

SMBDATA

6 1

QC2A

SB00000I700

2

SKL-U

LPC

5 OF 20

+3VS +3VS

2

QC1B

2N7002DWH_SOT363-6

5

3 4

SB00000I700

2

3 4

QC2B

2N7002DWH_SOT363-6

SB00000I700

<DB> PWR Rail

SB00000I700

61

QC7A

5

QC7B

SB00000I700

2N7002DWH_SOT363-6

SMBUS, SMLINK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

RC215

RC216

10K_0402_5%

+3VS

5

10K_0402_5%

34

10K_0402_5%

1 2

<Cocoa_1020> add level shift

EC_SMB_CK2 <10,19,22,26,37>

EC_SMB_DA2 <10,19,22,26,37>

+3VALW+3V_PRIM

RC81

RC82 10K_0402_5%

1 2

3

Rev_0.5 3

R7

SMBCLK

R8

SMBDATA

R10

SMBALERT#

R9

SML0CLK

W2

SML0DATA

W1

SML0ALERT#

W3

SML1CLK

V3

SML1DATA

GPP_B23

AM7

LPC_AD0

AY13

LPC_AD1

BA13

LPC_AD2

BB13

LPC_AD3

AY12

LPC_FRAME#

BA12

SUS_STAT#

BA11

CLK_PCI0

AW9

CLK_PCI1

AY9

PM_CLKRUN#

AW11

<SI>un-mount RC53 11/28 CPU side delete EC_PCIE_WAKE#

PCH_SMBCLK <17,18,19,22>

PCH_SMBDATA <17,18,19,22>

TP_SMBCLK <27>

TP_SMBDATA <27>

T239TP@

1 2

SML1ALERT#

RC902

@

0_0201_5%

T234TP@

LPC_AD0 <26,28> LPC_AD1 <26,28> LPC_AD2 <26,28> LPC_AD3 <26,28> LPC_FRAME# <26,28>

T242TP@

1 2

RC387 22_0402_5%

1 2

RC53 22_0402_5%TPM@

PM_CLKRUN# <26>

2

SML0ALERT# (Internal Pull Down): eSPI or LPC 0 = LPC is selected for EC --> For KB9022/9032 Use 1 = eSPI is selected for EC --> For KB9032 Only.

SMB

(Link to XDP, DDR, TP)

SML1

(Link to EC,DGPU, LAN, Thermal Sensor)

CLK_PCI_LPC <26> CLK_PCI_TPM <28>

To EC

SML0ALERT#

SML1ALERT#

SML0ALERT#

SMBALERT#

EC_KBRST#

12

RC218 1K_0402_1%

RC903

@

150K_0402_1%

RC360 10K_0402_5%@

RPC19 10K_0804_8P4R_5%

11/28_Follow Intel check list, add PU res

11/28_Change PWR rail from +3VS to +3V_PRIM

+3V_PRIM

SML0CLK

SML0DATA

SML1CLK SML1DATA SMBDATA SMBCLK

PCH_SPI_SIO2

PCH_SPI_SIO3

PCH_SPI_CS0#_R

PCH_SPI_SIO3

From WW36 MOW for SKL-U ES sample

PM_CLKRUN#

SERIRQ

Follow 543016_SKL_U_Y_PDG_0_9

1 2

RC49 499_0402_1%

1 2

RC50 499_0402_1%

RPC7

1 8 2 7 3 6 4 5

1K_0804_8P4R_5%

1 2

RC390 1K_0402_1%@

1 2

RC391 1K_0402_1%

@

1 2

RC357 1K_0402_5%

1 2

RC51 1K_0402_1%ES@

1 2

RC107 8.2K_0402_5%

1 2

RC122 8.2K_0402_5%

+3V_SPI

+3VS_PGPPA

1

12

18 27 36 45

+3V_PRIM

+3VS

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2014/12/11 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(3/12)SPI,ESPI,SMB,LPC

Size

Document Number Re v

Custom

LA-D707P

Date : Sheet

2

Date : Sheet

1

7 60Wednesday, May 11, 2016

v0.2

o f

5

Aditya11ttt.com

4

3

2

1

UC1G

D D

HDA_SDIN0<24>

T35 TP@

T38 TP@ T39 TP@

HDA_SPKR<10,24>

C C

HDA_SYNC HDA_BIT_CLK HDA_SDOUT

HDA_SDIN0

HDA_RST#

SOC_GPIOF1 SOC_GPIOF0

HDA_SPKR

BA22 AY22 BB22 BA21 AY21

AW22

AY20

AW20

AK7 AK6 AK9

AK10

AW5

J5

H5 D7

D8 C8

AUDIO

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKL-U_BGA1356

SKL-U

7 OF 20

Rev_0. 53

SDIO/SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

VRAMCLK_SEL

PROJECT_ID

SD_RCOMP

RC76 200_0402_1%

SOC_GPIOF17

T235 TP@

+3V_PRIM

12

RC127 10K_0402_5%

PX@

12

RC128

10K_0402_5%

UMA@

12

PROJECT_ID

VRAM Clock

VRAMCLK_SEL

UMA

0

+3V_PRIM

X76@

RC900 10K_0402_5%

1 2

X76@

RC901 10K_0402_5%

1 2

DIS

1

1000M Hz900MH z

1

HDA for AUDIO

RPC9

1 8

@EMI@

2 7 3 6 4 5

HDA_SYNC_AUDIO<24> HDA_RST_AUDIO#<24> HDA_SDOUT_AUDIO<24>

HDA_BITCLK_AUDIO<24>

CC143 22P_0402_50V8J

EMI request

B B

A A

HDA_SYNC HDA_RST# HDA_SDOUT

33_0804_8P4R_5%

HDA_BIT_CLK

RC383 33_0402_5%

12

EMI@

A36 B36 C38 D38 C36 D36 A38 B38

C31 D31 C33 D33 A31 B31 A33 B33

A29 B29 C28 D28 A27 B27 C27 D27

UC1I

CSI-2

CSI2_DN0 CSI2_DP0 CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3

CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7

CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11

SKL-U_BGA1356

+3V_HDA

ME_FLASH_EN<26>

1 2

SKL_ULT

@

1K_0402_1%

9 OF 20

RC380

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

1 2

RC367 0_0402_5%

G

D

@

Rev_0. 53

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

S

HDA_SDOUT

QC380 MESS138W-G_SOT323-3

C37 D37 C32 D32 C29 D29 B26 A26

CSI2_COMP

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

EMMC_RCOMP

AT1

123

EMMC_RCOMP

HDA_SDOUT: ME Flash Descriptor Security Override Low : Disabled(Default) High : Enabled

T63 TP@

12

RC80 100_0402_1%

RC89 200_0402_1%

5

Security Classification

2014/05/19 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2014/05/19 2015/12/31

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(4/12)HDA,EMMC,SDIO,CSI2

Size

Document Number Re v

Custom

LA-D707P

Wednesday, May 11, 2016

Date : Sheet

2

Date : Sheet

1

o f

8

o f

8

o f

8

v0.2

60

PCH PLTRST Buf f er

+RTCVCC

Aditya11ttt.com

RC91 20K_0402_5%

CC10 1U_0402_6.3V6K

CLRP1 SHORT PADS

RC93 20K_0402_5%

CC11 1U_0402_6.3V6K

CLRP2 SHORT PADS

D D

+3V_PRIM

C C

B B

A A

RC94 1M_0402_5%

PCH_RTCRST#

PCH_SRTCRST#

+3VS

RC165 10K_0402_5%

RC105 10K_0402_5%

RC109 10K_0402_5%

+3VALW_DSW

10K_0804_8P4R_5%

CLRP3 SHORT PADS

RC100 1K_0402_5%

RC101 100K_0402_5%

+3VALW_DSW

+3V_PRIM

+3VALW_DSW

RC111 100K_0402_5%

From EC(open-drain)

EC_VCCST_PG_R<26,35>

5

1 2

12

@

R10880_0402_5%

12

@

R10890_0402_5%

1 2

RPC10

18 27 36 45

10K_0804_8P4R_5%

1 2

@

RPC11

18 27 36 45

12

1 2

@

12

1 2

RC103 8.2K_0402_5%

1 2

RC104 1K_0402_5%

1 2

RC106 10K_0402_5%

@

1 2

RC115 10K_0402_5%

@

PCH_SRTCRST#

CLR ME

PCH_RTCRST#

CLR CMOS

SM_INTRUDER#

CLR_CMOS# <26>

12

Clear CMOS close to RAM door

@

JCMOS1

0_0603_5%

CLKREQ_PCIE#4

CLKREQ_PCIE#5

LAN_CLKREQ# MINI1_CLKREQ# CR_CLKREQ#

VGA_CLKREQ#

PCH_PWROK LAN_WAKE# PCH_RSMRST# SYS_RESET#

SYS_RESET#

SUSCLK

PCH_DPWROK

From 545659_SKL_PCH_U_Y_EDS_R0_7

<DB> unpop, PD at GPU side

PM_BATLOW#

WAKE#

AC_PRESENT_R

<DB> RC106 unpop , follow module design

SOC_VRALERT#

12

PBTN_OUT#

+1.0V_VCCST

12

RC113 1K_0402_5%

1 2

RC116 60.4_0402_1%

<Cocoa_1 027> check un-use GPIO for termination guidance

DS12

PCH_PWROK

12

CK0402101V05_0402-2

ESD@ SCV00001K00

Only For Power Sequence Debug

ESD@

DS13

SCV00001K00

1 2

CK0402101V05_0402-2

DS14

1 2

CK0402101V05_0402-2

DS15

1 2

CK0402101V05_0402-2

EC_VCCST_PG

5

SUSACK#<26>

H_CPUPWRGD

@ESD@ SCV00001K00

SUSACK#

@ESD@ SCV00001K00

SYS_PWROK

4

CLK_PEG_VGA#<36>

GPU

CLK_PEG_VGA<36>

VGA_CLKREQ#<37>

CLK_PCIE_LAN#<23>

LAN

CLK_PCIE_LAN<23>

LAN_CLKREQ#<23>

WLAN

CLK_PCIE_WLAN#<32> CLK_PCIE_WLAN<32>

MINI1_CLKREQ#<32>

CardRea der

T95 TP@

RC102 1K_0402_5%@

12

RC110 0_0402_5%

<DB> add ESD protection

4

PCH_RSMRST#<26>

1 2

SYS_PWROK<26>

PCH_PWROK<26>

PCH_SUSWARN#<26>

WAKE#<32>

3

UC1J

CLK_PEG_VGA# CLK_PEG_VGA VGA_CLKREQ#

CLK_PCIE_LAN# CLK_PCIE_LAN LAN_CLKREQ#

CLK_PCIE_WLAN# CLK_PCIE_WLAN MINI1_CLKREQ#

CR_CLKREQ#

CLKREQ_PCIE#4

CLKREQ_PCIE#5

RC99 0_0402_5%

PLT_RST#_PCH

SN74AHC1G08DCKR_SC70-5

PLT_RST#_PCH

T296 TP@

SYS_RESET# PCH_RSMRST#

H_CPUPWRGD EC_VCCST_PG

SYS_PWROK PCH_PWROK PCH_DPWROK_R

PCH_SUSWARN# SUSACK#_R

WAKE# LAN_WAKE#

T94 TP@

PCH_RSMRST# PCH_PWROK

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKL-U_BGA1356

<DB> Romove PLT_RST# buf f er

1 2

+3VS

CC145

@

1 2

@

5

UC8

0.1U_0402_16V7K

1

P

IN1

4

O

2

IN2

G

3

UC1K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKL-U_BGA1356

DC3

SCS00003500

CH751H-40PT_SOD323-2

21

2 1

DC4

SCS00003500

CH751H-40PT_SOD323-2

PCH_DPWROK<26>

3

2

SKL_ULT

CLOCK SIGNALS

10 OF 20

PLT_RST#PLT_RST#

SYSTEM POWER MANAGEMENT

RC112 0_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PLT_RST# <23,26,28,32,36>

SKL-U

GPP_B11/EXT_PWR_GATE#

11 OF 20

11/28 add RSMRST protect circuit

SPOK <48>

12

2014/05/19 2015/12/31

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

SRTCRST#

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B2/VRALERT#

PCH_DPWROK_R

Rev_0.5 3

F43 E43

BA17

SUSCLK

PCH_XTAL24_IN

E37

PCH_XTAL24_OUT

E35

XCLK_BIASREF

E42

PCH_RTCX1

AM18

RTCX1 RTCX2

RTCRST#

Rev_0.5 3

SLP_LAN#

Compal Secret Data

PCH_RTCX2

AM20

PCH_SRTCRST#

AN18

PCH_RTCRST#

AM16

PCH_XTAL24_IN

PCH_XTAL24_OUT PCH_RTCX1

PM_SLP_S0#

AT11

PM_SLP_S3#

AP15

PM_SLP_S4#

BA16

PM_SLP_S5#

AY16

PM_SLP_SUS#

AN15

SLP_LAN#

AW15

SLP_WLAN#

BB17

PM_SLP_A#

AN16

PBTN_OUT#

BA15

AC_PRESENT_R

AY15

PM_BATLOW#

AU13

EC_PCIE_WAKE#

AU11

SM_INTRUDER#

AP16

EXT_PWR_GATE#

AM10

SOC_VRALERT#

AM11

Deciphered Date

2

SUSCLK <32>

1 2

RC96 2.7K_0402_1%

1 2

RC92 1M_0402_5%

YC1

SJ10000IZ00

24MHZ 12PF 20PPM X3G024000DC1H

3

CC12

22P_0402_50V8J

GND

4

<Coc oa_1 020 > 32M use these part (SJ10000NM00, SJ10000MH00) just can meet <50k ohm spec 24M: SJ10000DI00, SJ10000CS00

PM_SLP_SUS# <13,26>

T87TP@ T88TP@

RC108 0_0402_5%

PBTN_OUT# <26>

EC_PCIE_WAKE# <26,32>

T298TP@

1

+1.0V_CLK5_F24NS

XCLK_BIASREF

@

1 2

RC97 60.4_0402_1%

<DB> stuf f f or c annonl ake 60oh m 1 %

<SI> change to SJ10000Q300 , CL=9p

PCH_RTCX2

1 2

RC98 10M_0402_5%

YC2

32.768KHZ 9PF 10PPM 9H03200055

1

GND

2

12

22P_0402_50V8J

PM_SLP_S3# <12,26,35> PM_SLP_S4# <12,26,35,49> PM_SLP_S5# <26>

Title

Size

Custom

Date: Sheet

CC15

CC13

T254TP@ T255TP@ T256TP@ T257TP@ T258TP@

ACIN <26,37>

Compal Electronics, Inc.

SKL-U(5/12)CLK,GPIO

Document Number Re v

LA-D707P

1 2

SJ10000Q800

6.8P_0402_50V8J

1

2

<PV> change CC15,CC16 to 6.8p <MV> change CC15,CC16 to 8.2p

9 60Wednesday, May 11, 2016

1

9 60Wednesday, May 11, 2016

CC16

6.8P_0402_50V8J

1

2

v0.2

of

5

Aditya11ttt.com

4

3

2

1

@

1 2

@

1 2

@

1 2

SKL-U

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

6 OF 20

HDA_SPKR

GSPI0_MOSI

GSPI1_MOSI

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A12/BM_BUSY#/ISH_GP6

HDA_SPKR <8,24>

Rev_0.5 3

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

P2 P3 P4 P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

DGPU_PWR_EN

AC1

DGPU_HOLD_RST#

AC2 AC3 AB4

AY8 BA8 BB7

ODD_PWR

BA7

ODD_DA#

AY7 AW7

SOC_GPIOA12

AP13

TS_GPIO_CPU <20>

12/11_Delete TP

DGPU_PWR_EN <26,38,55,56> DGPU_HOLD_RST# <36>

GPU_PGD <56>

ODD_PWR <30>

ODD_DA# <30>

T122 TP@

+3VS

1 2

RC45 33K_0402_5%

1105_Modify schematic

<Cocoa_1 027> Follow #544669 GPIO I/O setting

CPU THERMAL SENSOR

+3VS

0.1U_0402_16V7K CC127

1

2

CC14

1 2

2200P_0402_50V7K

Thermal sensor: Main:SA000067P00, S IC NCT7718W MSOP 8P THEMAL SENSOR(Nuvoton) 2nd : SA00007WP00, S IC F75397M MSOP 8P THEMAL SENSOR(Fintek) 3rd : SA007810140, S IC G781P8F MSOP 8P TEMP. SENSOR(GMT)

Thermal sensor SMBus address -->100-1_100xb : 0x4C (x=0)Write Address(0x98h) (x=1)Read Address(0x99h)

UC3

1

H_THERMDA

H_THERMDC

CPU_THERM#

VDD

2

D+

3

D-

THERM#4GND

NCT7718W_MSOP8

SA000067P00

SCLK

SDATA

ALERT#

8

7

6

5

NMI_DBG#_CPU<5,26>

EC_SCI#<5,26>

<Cocoa_1127> remove EC_LID_OUT# function

<Cocoa_1 020> Follow BDW

EC_SMB_CK2

EC_SMB_DA2

THERMAL_ALERT#

EC_SMB_CK2 <7,19,22,26,37>

EC_SMB_DA2 <7,19,22,26,37>

DGPU_PWR_EN

EC_SCI# ODD_PWR ODD_DA#

RC44 10K_0402_5%

SOC_GPIOB21

WL_OFF# NMI_DBG#_CPU

RC382 10K_0402_5%

12

<DB >

1 2

@

RPC14

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

RPC12

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

+3VS

UC1F

AN8 AP7

GSPI0_MOSI

D D

C C

<DB> add TP by BIOS

T129TP@ T128TP@

WL_OFF#<32>

T133TP@ T132TP@

12

R5194

@

0_0402_5%

SOC_GPIOB21 GSPI1_MOSI

UART_0_CRXD_DTXD UART_0_CTXD_DRXD

WL_OFF#

UART_2_CRXD_DTXD UART_2_CTXD_DRXD

UART_2_CTXD_DRXD

UART_2_CRXD_DTXD

AM5

AH10

AH11 AH12

AF11 AF12

AP8 AR7

AN7 AP5 AN5

AB1 AB2

W4

AB3

AD1 AD2 AD3 AD4

U7 U6

U8 U9

AH9

Functional Strap Definitions

SPKR (Internal Pull Down):

TOP Swap Override

0 = Disable TOP Swap mode.---> AAX05 Use

1 = Enable TOP Swap Mode.

GSPI0_MOSI (Internal Pull Down):

No Reboot

LPSS ISH

GPP_B15/GSPI0_CS# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL

SKL-U_BGA1356

Strap Pin

+3VS

RC117 100K_0402_5%

RC118 4.7K_0402_5%

RC201 150K_0402_1%

<Cocoa_1 020> 1K ohm for 400kH z speed/ 0.5k ohm for 1MHz speed

+3VS

+3V_PRIM

+3VS

0 = Disable No Reboot mode. --> AAX05 Use

1 = Enable No Reboot Mode. (PCH will disable the TCO Timer system re boot feature). This function is useful when running ITP/XDP.

B B

GSPI1_MOSI (Internal Pull Down):

<DB> Delete Win7 debug port

Boot BIOS Strap Bit

0 = SPI Mode --> AAX05 Use

1 = LPC Mode

A A

Security Classification

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(6/12)GPIO

Size

Document Number Re v

Custom

LA-D707P

Date: Sheet

2

Date: Sheet

1

10 60Wednesday, May 11, 2016

v0.2

of

5

Aditya11ttt.com

4

3

2

1

UC1H

<DB> Change to 0.22uF for Gen3

PEG_PRX_C_DTX_N0<36> PEG_PRX_C_DTX_P0<36> PEG_PTX_C_DRX_N0<36>

D D

PEG

LAN

WLAN

HDD

C C

ODD

B B

A A

PEG_PTX_C_DRX_P0<36>

PEG_PRX_C_DTX_N1<36> PEG_PRX_C_DTX_P1<36> PEG_PTX_C_DRX_N1<36> PEG_PTX_C_DRX_P1<36>

PEG_PRX_C_DTX_N2<36> PEG_PRX_C_DTX_P2<36> PEG_PTX_C_DRX_N2<36> PEG_PTX_C_DRX_P2<36>

PEG_PRX_C_DTX_N3<36> PEG_PRX_C_DTX_P3<36> PEG_PTX_C_DRX_N3<36> PEG_PTX_C_DRX_P3<36>

PCIE_PRX_DTX_N5<23>

PCIE_PRX_DTX_P5<23> PCIE_PTX_C_DRX_N5<23> PCIE_PTX_C_DRX_P5<23>

PCIE_PRX_DTX_N6<32>

PCIE_PRX_DTX_P6<32> PCIE_PTX_C_DRX_N6<32> PCIE_PTX_C_DRX_P6<32>

SATA_PRX_DTX_N0<30>

SATA_PRX_DTX_P0<30>

SATA_PTX_DRX_N0<30>

SATA_PTX_DRX_P0<30>

SATA_PRX_DTX_N1<30>

SATA_PRX_DTX_P1<30>

SATA_PTX_DRX_N1<30>

SATA_PTX_DRX_P1<30>

CC119 0.22U 6.3V K X5R 0402 PX@ CC146 0.22U 6.3V K X5R 0402 PX@

CC128 0.22U 6.3V K X5R 0402 PX@ CC93 0.22U 6.3V K X5R 0402 PX@

CC124 0.22U 6.3V K X5R 0402 PX@ CC92 0.22U 6.3V K X5R 0402 PX@

CC129 0.22U 6.3V K X5R 0402 PX@ CC118 0.22U 6.3V K X5R 0402 PX@

12

CC18 0.1U_0402_16V7K

12

CC17 0.1U_0402_16V7K

12

CC20 0.1U_0402_16V7K

12

CC19 0.1U_0402_16V7K

1 2

RC120 100_0402_1%

T291 TP@

XDP_PREQ#<5>

T154 TP@

XDP_PRDY#

XDP_PREQ#

SOC_GPIOA7

PEG_PRX_C_DTX_N0 PEG_PRX_C_DTX_P0

PEG_PTX_DRX_N0

12

PEG_PTX_DRX_P0

12

PEG_PRX_C_DTX_N1 PEG_PRX_C_DTX_P1

PEG_PTX_DRX_N1

12

PEG_PTX_DRX_P1

12

PEG_PRX_C_DTX_N2 PEG_PRX_C_DTX_P2

PEG_PTX_DRX_N2

12

PEG_PTX_DRX_P2

12

PEG_PRX_C_DTX_N3 PEG_PRX_C_DTX_P3

PEG_PTX_DRX_N3

12

PEG_PTX_DRX_P3

12

PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5

PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6

PCIE_RCOMPN PCIE_RCOMPP

When PCIE8/SATA1A is used as SATA Port 1 (ODD), then PCIE11/SATA1B (M.2 SSD) cannot be used as SATA Port 1.

5

4

PCIE/U SB3/SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL-U_BGA1356

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

3

SKL-U

8 OF 20

GPI O

USB_ OC0#

USB_ OC1#

USB_ OC2#

USB_ OC3#

DEVSLP 0

DEVSLP 1

DEVSLP 2

SATA _GP0

SATA _GP1

SATA _GP2

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

DEVICE CONTROL

USB2 Port 1 and Port 2

USB2 Port 3

NA

NGFF SSD KEY B

NA

ODD_ PLU G#

Compal Secret Data

Deciphered Date

Rev_0. 53

USB3_1_RXN USB3_1_RXP USB3_1_TXN

USB3_1_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN

USB3_4_TXP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6 AG3 AG4

A9 C9 D9 B9

J1 J2 J3

H2 H3 G4

H1

2

USB2_COMP USB2_ID USB2_VBUSSENSE

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

DEVSLP0 DEVSLP1 DEVSLP2

SATA_GP0 ODD_PLUG# SATA_GP2

SATA_LED#

USB3_RX1_N <31> USB3_RX1_P <31>

USB3_TX1_N <31> USB3_TX1_P <31>

USB20_N1 <31> USB20_P1 <31>

USB20_N2 <31> USB20_P2 <31>

USB20_N3 <33> USB20_P3 <33>

USB20_N4 <32> USB20_P4 <32>

USB20_N5 <20> USB20_P5 <20>

USB20_N6 <20> USB20_P6 <20>

USB20_N7 <33> USB20_P7 <33>

1 2

RC119 113_0402_1%

USB2.0/USB3.0

USB2.0

USB2.0 ( on small board )

WLAN

Camera

Touch Screen

Card Reader

<SI> follow EDS to add 1K ohm PD

USB2_ID

T243 TP@

<DB> PU

T241 TP@

ODD_PLUG# <30>

SATA_LED# <33>

DEVSLP1 SOC_GPIOA7

SATA_LED# SATA_GP0 SATA_GP2 ODD_PLUG#

USB_OC1# USB_OC3# USB_OC0# USB_OC2#

USB2_VBUSSENSE

RC362 10K_0402_5% RC361 10K_0402_5%

1128_Add pull high resistor

Compal Electronics, Inc.

Title

SKL-U(7/12)PCIE,USB,SATA

Size

Document Number Re v

Custom

LA-D707P

Date : Sheet

1 2

RC20 0_0402_5%

1 2

RC21 0_0402_5%

1 2 1 2

RPC13

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

RPC20

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

1

11 60Wednesday, May 11, 2016

+3VS

+3V_PRIM

o f

v0.2

5

Aditya11ttt.com

4

3

2

1

+1.0V_PRIM TO +1.0V_VCCSTU

+1.2V_VDDQ

1211_Delete jump RC147

D D

1 2

SYSON<26,35,49>

PM_SLP_S4#<9,26,35,49>

SUSP#<13,26,35,49>

PM_SLP_S3#<9,26,35>

C C

1210_Delete jump RC146

RC142 0_0402_5%

1 2

RC144 0_0402_5%@

1 2

RC168 0_0402_5%

1 2

RC194 0_0402_5%@

1

2

0.1U_0402_25V6

@

CC151

+5VALW

1

2

+1.8V_PRIM

1

@

2

CC98

CC99

1U_0402_6.3V6K

CC97

1

@

2

EN_1.0V_VCCSTU

EN_1.8VS

+1.0VS_VCCIO

R5188 0_0603_5%@

I (Max) : 0.04 A(+1.0V_VCCSTU) RON(Max) : 25 mohm V drop : 0.001 V

UC5

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

EM5209VF_DFN14_2X3

SA00007PM00

I (Max) : 0.536 A(+1.8VS) RON(Max) : 25 mohm V drop : 0.013 V

VOUT1 VOUT1

CT1

GND

CT2

VOUT2 VOUT2

GPAD

14 13

12

CC95

11

10P_0402_50V8J

10

CC94

@

9

1000P_0402_50V7K

8

15

0.1U_0402_25V6

1 2

@ESD@

CC156

+1.0V_VCCSTU+1.0V_PRIM

1

2

+1.8VS

1

CC100

0.1U_0402_25V6

2

<DB> Delete RC145

0.1U_0402_25V6

CC96

+1.2V_VDDQC

+1.0V_VCCST

+1.0VS_VCCIO

+1.2V_VCCSFR_OC

+1.0V_VCCSFR

<Cocoa_1113> Per 543977_SKL_PDDG_Rev0_91, change CC95 value from 1000pf to 10pf for meet <= 65us timing for +1.0V_VCCSTU power rail.

+1.0V_VCCSTU +1.0V_VCCST

1 2

RC140 0_0402_5%

AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51

AM40

A18

A22

AL23

K20 K21

UC1N

VDDQ_AU23 VDDQ_AU28 VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51

VDDQC

VCCST

VCCSTG_A22

VCCPLL_OC

VCCPLL_K20 VCCPLL_K21

SKL-U_BGA1356

+1.0V_PRIM TO +1.0VS_VCCSTG / +1.0VS_VCCIO

+5VALW

+1.0V_PRIM

0.1U_0402_25V6

CC88

1

2

@

B B

EC_S0IX_EN<26>

For Verify S0IX

+1.0VS_VCCIO

SUSP#

<Cocoa_1027> connect to EC, check /w EC

10U_0402_6.3V6M

1

CC27

2

1 2

RC186 0_0402_5%

1 2

RC187 0_0402_5%

10U_0402_6.3V6M

CC28

@

1U_0201_6.3V6K

1

CC29

2

1U_0402_6.3V6K

Imax : 2.77 A

CC117

1

2

1U_0201_6.3V6K

1

CC30

CC31

2

I (Max) : 3 A(+1.0VS_VCCIO) RON(Max) : 6.2 mohm V drop : 0.019 V

UC6

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

Part Number = SA00007XR00

PSC SideBSC Side

1U_0402_6.3V6K

1U_0201_6.3V6K

1

CC32

2

1U_0402_6.3V6K

1

CC33

2

VOUT

GND

CC34

6

5

1U_0402_6.3V6K

1

CC35

2

<PV> change short pad

+1.0VS_VCCSTG_IO

RC189

1 2

Imax : 3 A

<DB> change +1.35V_VDDQ

RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev0_53

+1.2V_VDDQ

1U_0402_6.3V6K

1

CC36

CC47 Follow 543016_SKL_U_Y_PDG_0_9

2

+1.0VS_VCCIO

0_0805_5%

RC208

1 2

near pin A22

@

1 2

CC89 0.1U_0402_25V6

1 2

CC90 0.1U_0402_25V6

+1.2V_VDDQC

0_0603_5%

BSC Side

1U_0402_6.3V6K

1

CC47

2

1 2

RC143 0_0402_5%

<DB> change +1.35V_VDDQ

+1.2V_VDDQ

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

1

CC37

CC38

2

CPU POWER 3 OF 4

14 OF 20

PSC Side

1U_0402_6.3V6K

1

2

+1.0V_VCCSFR

1U_0402_6.3V6K

1

2

10U_0603_6.3V6M

1

CC39

2

SKL-U

VSSSA_SENSE VCCSA_SENSE

CC48

Rev_0. 53

VCCIO_SENSE

VSSIO_SENSE

RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev1.0

CC55

10U_0603_6.3V6M

1

CC40

2

+1.0VS_VCCIO

AK28

VCCIO

AK30

VCCIO

AL30

VCCIO

AL42

VCCIO

AM28

VCCIO

AM30

VCCIO

AM42

VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

+VCC_SA

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE VCCSA_SENSE

<DB> change +1.35V_VDDQ

BSC SidePSC Side

10U_0603_6.3V6M

1U_0402_6.3V6K

10U_0603_6.3V6M

1

CC42

CC41

2

1U_0201_6.3V6K

1

CC43

2

T124 TP@ T125 TP@

VSSSA_SENSE <52> VCCSA_SENSE <52>

+1.0VS_VCCIO

1U_0402_6.3V6K

1

CC44

2

BSC SidePSC Side

1U_0402_6.3V6K

1

CC56

2

1U_0402_6.3V6K

1

CC46

CC45

2

A A

Security Classification

5

Security Classification

2014/12/11 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2014/12/11 2015/12/31

3

Compal Secret Data

Deciphered Date

+1.35V_VDDQ_CPU : 10UF/6.3V/0603 *6 1UF/6.3V/0402 * 4

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet

2

Date : Sheet

Compal Electronics, Inc.

SKL-U(8/12)Power

Document Number Re v

LA-D707P

v0.2

o f

12 60Wednesday, May 11, 2016

o f

12 60Wednesday, May 11, 2016

o f

12 60Wednesday, May 11, 2016

1

5

Aditya11ttt.com

+1.0V_PRIM

1 2

RC148 0_0603_5%

D D

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC152 0_0603_5%

1 2

RC190 0_0603_5%

C C

Imax : 2.57A

near pin AF18, AF19,V20 ,V21

+1.0V_APLL

22U_0603_6.3V6M

CC142

1

@

2

+1.0V_CLK5_F24NS

22U_0603_6.3V6M

CC135

1

@

2

+1.0V_CLK4_F100OC

22U_0603_6.3V6M

CC136

1

@

2

+1.0V_PRIM

+3V_PRIM

1 2

CC134

CC130

1U_0402_6.3V6K

1

CC67

@

2

CC137

1U_0402_6.3V6K

1

CC76

2

RC150 0_0402_5%

1U_0402_6.3V6K

1

CC72

2

+3V_PRIM

1 2

RC197 0_0402_5%

1 2

RC154 0_0402_5%

1 2

RC161 0_0402_5%

1 2

RC163 0_0402_5%

<Diner-DB> change to +3V_PRIM

+1.0V_MPHYAON

1 2

RC175 0_0402_5%

B B

1 2

RC169 0_0603_5%

@

1 2

RC162 0_0402_5%

1

2

+1.0V_CLK6_24TBT

1U_0402_6.3V6K

1

CC86

@

2

+1.0V_DTS

1U_0402_6.3V6K

CC87

22U_0603_6.3V6M

1U_0402_6.3V6K

CC75

@

CC139

CC138

1

@

2

1 2

RC172 0_0402_5%

1 2

RC167 0_0402_5%

1 2

RC171 0_0402_5%

Follow 543016_SKL_U_Y_PDG_0_9

+1.0V_PRIM +3V_PRIM +1.8V_PRIM

22U_0603_6.3V6M

A A

22U_0603_6.3V6M

CC112

CC111

1

@

2

22U_0603_6.3V6M

CC114

CC113

1

@

2

22U_0603_6.3V6M

CC115

CC116

1

@

2

5

+3VS

1 2

RC178 0_0402_5%

+3VALW

1 2

RC173 0_0603_5%

Follow 543016_SKL_U_Y_PDG_0_9

4

+3V_HDA

+3V_PGPPA

+3V_SPI

+3V_PGPPB

1U_0402_6.3V6K

1

2

+3V_PGPPC

1U_0402_6.3V6K

1

2

+3V_1.8V_PGPPD

1U_0402_6.3V6K

1

@

2

+3V_PGPPE

1U_0402_6.3V6K

1

2

+3V_PRIM_RTC

1U_0402_6.3V6K

1

2

4

1

CC63 1U_0201_6.3V6K

2

CC102

CC73

1 2

RC206 0_0402_5%@

CC103

CC74

1

CC77

2

+3VS_PGPPA

+3VALW_DSW

+1.8V_PRIM

near p in K15, L15

near pin N18

near pin AF20, AF21,T19, T20

near pin N15, N16, N17,P15, P16

3

+1.0V_PRIM

1

2

+1.0V_PRIM

+1.0V_APLL

+1.0V_PRIM

+3VALW_DSW

+3V_HDA

+3V_SPI

+1.0V_PRIM

+3V_PRIM

+1.0V_PRIM

CC147

@

CC80

22U_0603_6.3V6M

CC148

1

2

@

+1.0V_PRIM

22U_0603_6.3V6M

CC81

1

2

1U_0402_6.3V6K

CC61

1

2

1U_0402_6.3V6K

CC68

1

2

1U_0201_6.3V6K

1

CC141

2

22U_0603_6.3V6M

CC82

1

2

@

+1.0VO_DSW

1U_0402_6.3V6K

1

+1.0V_MPHYAON

CC85

2

<DB>Check Power Rail

Per 543016_SKL_U_Y_PDG_0_9

VCCRTC does not exceed 3.2 V From PDG

22U_0603_6.3V6M

1

@

2

1U_0402_6.3V6K

1

2

Power Rail Volt age

+CHG RTC

BAT5 4C(V F)

+3VL _RT C

3.38 3V(M AX)

240 mV

3.14 3V

Result : Pass

+1.0V_PRIM

1U_0201_6.3V6K

CC91

2

UC1O

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

SKL-U_BGA1356

1U_0201_6.3V6K

CC7

SKL-U

CPU POWER 4 OF 4

15 OF 20

RTC Battery

CC7 Close UC1.AK19.

+RTCVCC

15mils

1

2

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE VCCPGPPF VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

MAX. 8000mil

+RTCBATT_R

DC1

2

1

3

BAV70W 3P C/C_SOT-323

SC600000B00

Rev_0.5 3

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19

T1

AA1

AK17

AK19 BB14

BB10

CC71 0.1U_0402_10V7K

A14

K19

L21

N20

L19

A10

PRIMCORE_VID0

AN11

PRIMCORE_VID1

AN13

<DB> RTC BAT Conn

JRTC1

2

LOTES_AAA-BAT-054-K01

SP07000H700

1K_0402_5%

RC19

15mils15mils

12

+3VL

1

1209

_follow G group GPIO

powe rail to +3V_PRIM

+3V_PGPPA +3V_PGPPB +3V_PGPPC +3V_1.8V_PGPPD +3V_PGPPE +1.8V_PRIM +3V_PRIM

+3V_PRIM

+1.0V_DTS

+1.8V_PRIM

+3V_PRIM_RTC

+RTCVCC

1 2

+1.0V_CLK6_24TBT

+1.0V_APLL

+1.0V_CLK4_F100OC

+1.0V_CLK5_F24NS

+1.0V_CLK6_24TBT

T130 TP@ T131 TP@

-

CONN@

+RTCBATT

+

For SD CARD

20mils

1

+RTCBATT

+3VALW TO +3V_PRIM

0.1U_0201_10V6K

0_0805_5%

+3V_PRIM

13 60Wednesday, May 11, 2016

0.1U_0402_25V6

CC51

1

2

v0.2

of

I (Max) : 0.46 A(+3V_PRIM) RDS(Typ) : 65 mohm

+3VALW+5VALW

V drop : 0.03 V

1U_0402_6.3V6K

@

1

For DS3

0.1U_0201_10V6K

CC78

1 2

PCH_PWR_EN<26,35,51>

PM_SLP_SUS#<9,26>

SUSP#<12,26,35,49>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

RC191 0_0402_5%

1 2

RC174 0_0402_5%@

1 2

RC392

Compal Secret Data

2014/12/11 2015/12/31

Compal Secret Data

2

0_0402_5%

Deciphered Date

2

CC52

+1.2V_VDDQ

1U_0402_6.3V6K

CC150

CC50

1

2

EN_3V_PRIM

1

2

UC4

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

EM5209VF_DFN14_2X3

SA00007PM00

1 2

RC141 0_0402_5%@

+3VALW

1 2

RC393

For NON-DS3

+3V_PRIMJP

1 2

@

RC159

CC53

CC149

@

1 2

For DS3

+1.2V_VCCSFR_OC

CC49

1

2

1

14

VOUT1

13

VOUT1

12

CT1

1000P_0402_50V7K

11

GND

10

CT2

1000P_0402_50V7K

9

VOUT2

8

VOUT2

15

GPAD

Compal Electronics, Inc.

Title

SKL-U(9/12)Power

Size

Document Number Re v

Custom

LA-D707P

Date: Sheet

5

Aditya11ttt.com

4

3

2

1

UC1L

A30

VCC_A30

A34

VCC_A34

D D

T123 TP@

T121 TP@

For CPU2+3e SKU

C C

SVID ALERT

B B

A39

A44 AK33 AK35 AK37 AK38 AK40

AL33 AL37

AL40 AM32 AM33 AM35 AM37 AM38

G30

K32

AK32

AB62

P62 V62

H63

G61

AC63 AE63

AE62

AG62

AL63

AJ62

+1.0V_VCCST

12

RC179 56_0402_5%

VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RSVD_K32

RSVD_AK32

VCCOPC_AB62 VCCOPC_P62 VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE VSSOPC_SENSE

VCCEOPIO VCCEOPIO

VCCEOPIO_SENSE VSSEOPIO_SENSE

SKL-U_BGA1356

Place the PU resistors close to CPU

SKL-U

CPU POWER 1 OF 4

12 OF 20

Rev_0. 53

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VCC_SENSE VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

B63 A63 D64

G20

SOC_SVID_ALERT# SOC_SVID_CLK SOC_SVID_DAT

Trace Length < 25 mils

VCCSENSE <52>

VSSSENSE <52>

SOC_SVID_CLK <52>

+1.0VS_VCCIO

VCCGT_SENSE<52> VSSGT_SENSE<52>

Trace Length < 25 mils

VCCGT_SENSE VSSGT_SENSE

+VCC_GT +VCC_GT+VCC_CORE +VCC_CORE

AA63 AA64 AA66 AA67 AA69 AA70

AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71

M62

A48 A53 A58 A62 A66

K48 K50 K52 K53 K55 K56 K58 K60 L62 L63 L64 L65 L66 L67 L68 L69 L70 L71

N63 N64 N66 N67 N69

J43 J45 J46 J48 J50 J52 J53 J55 J56 J58 J60

J70 J69

UC1M

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT_SENSE VSSGT_SENSE

SKL-U_BGA1356

CPU POWER 2 OF 4

SKL-U

13 OF 20

Rev_0. 53

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70 VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56

VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63

VCCGTX_BB57

VCCGTX_BB66

VCCGTX_SENSE

VSSGTX_SENSE

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

VCCGTX_SENSE

AK62

VSSGTX_SENSE

AL61

For CPU2+3e SKU

T155 TP@ T219 TP@

SOC_SVID_ALERT#

SVID DATA

A A

SOC_SVID_DAT

1 2

RC180 220_0402_5%

5

+1.0V_VCCST

12

RC181 100_0402_1%

SOC_SVID_ALERT#_R <52>

Place the PU resistors close to CPU

SOC_SVID_DAT <52>

4

(To VR)

Security Classification

2014/05/19 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet

SKL-U(10/12)Power,SVID

Document Number Re v

LA-D707P

14 60Wednesday, May 11, 2016

1

v0.2

o f

5

Aditya11ttt.com

4

3

2

1

D D

A5 A67 A70 AA2 AA4

AA65 AA68 AB15 AB16 AB18 AB21

AB8

AD13 AD16 AD19 AD20 AD21 AD62

AD8

AE64 AE65 AE66 AE67

C C

B B

AE68 AE69

AF1

AF10 AF15 AF17

AF2 AF4

AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71

AH13

AH6 AH63 AH64 AH67 AJ15 AJ18 AJ20

AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69

AK8

AL2 AL28 AL32 AL35 AL38

AL4 AL45 AL48 AL52 AL55 AL58 AL64

AJ4

UC1P

GND 1 OF 3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-U_BGA1356

SKL-U

Rev_0. 53 Rev_0. 53

AL65

VSS

AL66

VSS

AM13

VSS

AM21

VSS

AM25

VSS

AM27

VSS

AM43

VSS

AM45

VSS

AM46

VSS

AM55

VSS

AM60

VSS

AM61

VSS

AM68

VSS

AM71

VSS

AM8

VSS

AN20

VSS

AN23

VSS

AN28

VSS

AN30

VSS

AN32

VSS

AN33

VSS

AN35

VSS

AN37

VSS

AN38

VSS

AN40

VSS

AN42

VSS

AN58

VSS

AN63

VSS

AP10

VSS

AP18

VSS

AP20

VSS

AP23

VSS

AP28

VSS

AP32

VSS

AP35

VSS

AP38

VSS

AP42

VSS

AP58

VSS

AP63

VSS

AP68

VSS

AP70

VSS

AR11

VSS

AR15

VSS

AR16

VSS

AR20

VSS

AR23

VSS

AR28

VSS

AR35

VSS

AR42

VSS

AR43

VSS

AR45

VSS

AR46

VSS

AR48

VSS

AR5

VSS

AR50

VSS

AR52

VSS

AR53

VSS

AR55

VSS

AR58

VSS

AR63

VSS

AR8

VSS

AT2

VSS

AT20

VSS

AT23

VSS

AT28

VSS

AT35

VSS

AT4

VSS

AT42

VSS

AT56

VSS

AT58

VSS

16 OF 20

AT63 AT68

AT71 AU10 AU15 AU20 AU32 AU38

AV1 AV68 AV69 AV70 AV71 AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57

AW6 AW60 AW62 AW64 AW66

AW8 AY66

B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71

BA1 BA10 BA14 BA18

BA2 BA23 BA28 BA32 BA36

F68

BA45

UC1Q

GND 2 OF 3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-U_BGA1356

SKL-U

17 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

G10 G22 G43 G45 G48

G52 G55 G58

G60 G63 G66 H15 H18 H71

K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71

F8

G5

G6

J11 J13 J25 J28 J32 J35 J38 J42

J8

L11 L16 L17

UC1R

GND 3 OF 3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-U_BGA1356

SKL-U

18 OF 20

Rev_0. 53

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

A A

Security Classification

5

Security Classification

2014/05/19 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2014/05/19 2015/12/31

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet

2

Date : Sheet

SKL-U(11/12)GND

Document Number Re v

LA-D707P

1

o f

15 60Wednesday, May 11, 2016

o f

15 60Wednesday, May 11, 2016

o f

15 60Wednesday, May 11, 2016

v0.2

5

Aditya11ttt.com

D D

T272 TP@ T273 TP@ T274 TP@

CFG3<5>

T275 TP@ T276 TP@ T277 TP@ T278 TP@ T279 TP@ T281 TP@ T280 TP@ T283 TP@ T282 TP@ T284 TP@ T285 TP@

T286 TP@ T287 TP@

T288 TP@

C C

XDP_ITP_PMODE<5>

B B

T289 TP@

T192 TP@

T194 TP@ T196 TP@

T198 TP@ T200 TP@

T205 TP@ T206 TP@

T209 TP@

T211 TP@

T213 TP@ T300 TP@

T217 TP@ T218 TP@

T220 TP@ T222 TP@

T224 TP@ T226 TP@

CFG_RCOMP

XDP_ITP_PMODE

CFG4

E68 B67 D65 D67 E70 C68 D68 C67

G69

G68 H70 G71 H69 G70

E63

E66

E60

AY2 AY1

K46 K45

AL25 AL27

C71 B70

A52

BA70 BA68

G65

E61

F71

F70

F63

F66

E8

D1 D3

F60

J71 J68

F65

F61

4

UC1S

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2 RSVD_AY1

RSVD_D1 RSVD_D3

RSVD_K46 RSVD_K45

RSVD_AL25 RSVD_AL27

RSVD_C71 RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70 RSVD_TP_BA68

RSVD_J71 RSVD_J68

VSS_F65 VSS_G65

RSVD_F61 RSVD_E61

SKL-U_BGA1356

RESERVED SIGNALS-1

SKL-U

19 OF 20

Rev_0. 53

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4 RSVD_C4

RSVD_A69 RSVD_B69

RSVD_AY3

RSVD_D71 RSVD_C70

RSVD_C54 RSVD_D54

VSS_AY71

ZVM#

RSVD_TP_AW71 RSVD_TP_AW70

MSM#

PROC_SELECT#

3

TP5 TP6

TP4

TP1 TP2

BB68 BB69

AK13 AK12

BB2 BA3

AU5 AT5

D5 D4 B2 C2

B3 A3

AW1

E1 E2

BA4 BB4

A4 C4

BB5

A69 B69

AY3

D71 C70

C54 D54

AY4 BB3

AY71 AR56

AW71 AW70

AP56 C64

PM_ZVM#

PM_MSM# SKL_CNL#

T156 TP@ T157 TP@

T158 TP@ T159 TP@

T162 TP@ T163 TP@

T166 TP@ T167 TP@

T170 TP@ T252 TP@

T174 TP@

T179 TP@ T183 TP@

T195 TP@ T197 TP@

T201 TP@ T203 TP@

1 2

RC182 0_0402_5%

T207 TP@ T208 TP@

T210 TP@ T301 TP@

1 2

RC183 0_0402_5%

T225 TP@

T333 TP@ T223 TP@

T230 TP@

1 2

@

RC184 100K_0402_5%

+1.0V_VCCST

Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0

2

AW69 AW68

AU56

AW48

C7 U12 U11 H11

For 2+3e Solution PM_ZVM# PM_MSM#

UC1T

RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48 RSVD_C7 RSVD_U12 RSVD_U11 RSVD_H11

SKL-U_BGA1356

SPARE

SKL-U

20 OF 20

Rev_0. 53

RSVD_F6

RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12 RSVD_F52

F6 E3 C11 B11 A11 D12 C12 F52

1

T227 TP@

CFG_RCOMP

CFG4

A A

1 2

RC185 49.9_0402_1%

1 2

RC193 1K_0402_1%

Display Port Presence Strap

CFG4

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2014/05/19 2015/12/31

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet

2

Date : Sheet

SKL-U(12/12)RSVD

Document Number Re v

LA-D707P

1

o f

16 60Wednesday, May 11, 2016

o f

16 60Wednesday, May 11, 2016

o f

16 60Wednesday, May 11, 2016

v0.2

5

Aditya11ttt.com

4

3

2

1

CHANNEL-A

REVERSE TYPE

Interleaved Memory

TOP: JDIMM1 CONN Non-ECC DIMM

D D

12

@

12

RD1 0_0402_5%

RD3 0_0402_5%

12

@

12

RD4 0_0402_5%

SA1_CHA_DIM1SA0_CHA_DIM1

RD5 0_0402_5%

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL A :

RITE ADDRESS: 0XA0

W READ ADDRESS: 0XA1 SA0 = 0; SA1 = 0; SA2 = 0. DDR4 POR OPERATING SPEED: 1867 MT/S

C C

STRETCH GOAL IS 2133 MT/S

Layout Note: Place near JDIMM1.257,259

+2.5V +0.6V_0.6VS

10U_0603_6.3V6M

1

CD3

2

Layout Note: PLACE THE CAP near JDIMM1. 164

B B

+0.6V_DDR_VREFCA

2

CD11

0.1U_0402_10V6K

1

0uF*2

1uF*2

1U_0402_6.3V6K

1

CD6

2

2.2uF*1

0.1uF*1

2

CD12

2.2U_0402_6.3V6M

1

0.1U_0402_25V6

1

@ESD@

CC159

2

1U_0402_6.3V6K

1

CD4

CD5

2

+3VS+3VS+3VS

12

RD2

@

0_0402_5%

SA2_CHA_DIM1

12

RD6 0_0402_5%

Layout Note: Place near JDIMM1.258

10uF*2 1uF*1

1U_0402_6.3V6K

10U_0603_6.3V6M

1

CD7

2

CD9

CD8

2

1 2

RD32 0_0402_5%

+1.2V_VDDQ

8/2 6

+3V_PRIM_DA

0.1U_0402_10V6K

2.2U_0402_6.3V6M

+0.6V_DDR_VREFCA

2

CD1

CD2

1

PLACE NEAR TO PIN

+3V_PRIM_DA+3V_PRIM

Part Number:LTCX0069GA0 Part Value:S SOCKET FOX AS0A827-H2RB-7H 260P DDR4

DDR_A_D[0..15]<6>

DDR_A_D[16..31]<6>

DDR_A_D[32..47]<6>

DDR_A_D[48..63]<6>

JDIMM1B

STD

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND

FOX_AS0A827-H2RB-7H

CONN@

VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19

VPP1 VPP2

GND

141 142 147 148 153 154 159 160 163

258

VTT

257 259

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

261

+1.2V_VDDQ

+0.6V_0.6VS

+2.5V

+1.2V_VDDQ

DDR_DRAMRST#_R

9/8 Modify

RD7 240_0402_1%

+1.2V_VDDQ

2

CD10

0.1U_0402_10V6K

@ESD@

1

12

DDR_DRAMRST#_R<6,18>

PLACE NEAR TO SODIMM

+1.2V_VDDQ

(5.2 mm)

DDR_A_CLK0<6> DDR_A_CLK#0<6> DDR_A_CLK1<6> DDR_A_CLK#1<6>

DDR_A_CKE0<6> DDR_A_CKE1<6>

DDR_A_CS#0<6> DDR_A_CS#1<6>

DDR_A_ODT0<6> DDR_A_ODT1<6>

DDR_A_BG0<6> DDR_A_BG1<6> DDR_A_BA0<6> DDR_A_BA1<6>

DDR_A_MA0<6> DDR_A_MA1<6> DDR_A_MA2<6> DDR_A_MA3<6> DDR_A_MA4<6> DDR_A_MA5<6> DDR_A_MA6<6> DDR_A_MA7<6> DDR_A_MA8<6> DDR_A_MA9<6> DDR_A_MA10<6> DDR_A_MA11<6> DDR_A_MA12<6> DDR_A_MA13<6> DDR_A_MA14_WE#<6> DDR_A_MA15_CAS#<6> DDR_A_MA16_RAS#<6>

DDR_A_ACT#<6>

DDR_A_PAR<6> DDR_A_ALERT#<6>

PCH_SMBDATA<7,18,19,22> PCH_SMBCLK<7,18,19,22>

For ECC DIMM

9/8 Modify base on ESD Request

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1

DDR_A_CKE0 DDR_A_CKE1

DDR_A_CS#0 DDR_A_CS#1

DDR_A_ODT0 DDR_A_ODT1

DDR_A_BG0 DDR_A_BG1 DDR_A_BA0 DDR_A_BA1

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14_WE# DDR_A_MA15_CAS# DDR_A_MA16_RAS#

DDR_A_ACT#

DDR_A_PAR DDR_A_ALERT# DIMM1_CHA_EVENT# DDR_DRAMRST#_R

PCH_SMBDATA PCH_SMBCLK

SA2_CHA_DIM1 SA1_CHA_DIM1 SA0_CHA_DIM1

JDIMM1A

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

FOX_AS0A827-H2RB-7H

CONN@

STD

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQS0(T)

DQS0#(C)

DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

DQS1(T)

DQS1#(C)

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

DQS2(T)

DQS2#(C)

DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS3(T)

DQS3#(C)

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

DQS4(T)

DQS4#(C)

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

DQS5(T)

DQS5#(C)

DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55

DQS6(T)

DQS6#(C)

DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS7(T)

DQS7#(C)

8 7 20 21 4 3 16 17 13 11

28 29 41 42 24 25 38 37 34 32

50 49 62 63 46 45 58 59 55 53

70 71 83 84 66 67 79 80 76 74

174 173 187 186 170 169 183 182 179 177

195 194 207 208 191 190 203 204 200 198

216 215 228 229 211 212 224 225 221 219

237 236 249 250 232 233 245 246 242 240

DDR_A_D0 DDR_A_D4 DDR_A_D3 DDR_A_D7 DDR_A_D1 DDR_A_D5 DDR_A_D2 DDR_A_D6 DDR_A_DQS0 DDR_A_DQS#0

DDR_A_D8 DDR_A_D12 DDR_A_D14 DDR_A_D10 DDR_A_D9 DDR_A_D13 DDR_A_D11 DDR_A_D15 DDR_A_DQS1 DDR_A_DQS#1

DDR_A_D21 DDR_A_D17 DDR_A_D23 DDR_A_D18 DDR_A_D16 DDR_A_D20 DDR_A_D19 DDR_A_D22 DDR_A_DQS2 DDR_A_DQS#2

DDR_A_D25 DDR_A_D28 DDR_A_D30 DDR_A_D31 DDR_A_D24 DDR_A_D29 DDR_A_D27 DDR_A_D26 DDR_A_DQS3 DDR_A_DQS#3

DDR_A_D32 DDR_A_D37 DDR_A_D34 DDR_A_D39 DDR_A_D36 DDR_A_D33 DDR_A_D35 DDR_A_D38 DDR_A_DQS4 DDR_A_DQS#4

DDR_A_D44 DDR_A_D45 DDR_A_D42 DDR_A_D43 DDR_A_D41 DDR_A_D40 DDR_A_D46 DDR_A_D47 DDR_A_DQS5 DDR_A_DQS#5

DDR_A_D53 DDR_A_D48 DDR_A_D54 DDR_A_D50 DDR_A_D52 DDR_A_D49 DDR_A_D55 DDR_A_D51 DDR_A_DQS6 DDR_A_DQS#6

DDR_A_D60 DDR_A_D57 DDR_A_D59 DDR_A_D62 DDR_A_D56 DDR_A_D61 DDR_A_D58 DDR_A_D63 DDR_A_DQS7 DDR_A_DQS#7

DDR_A_DQS0 <6>

DDR_A_DQS#0 <6>

DDR_A_DQS1 <6>

DDR_A_DQS#1 <6>

DDR_A_DQS2 <6>

DDR_A_DQS#2 <6>

DDR_A_DQS3 <6>

DDR_A_DQS#3 <6>

DDR_A_DQS4 <6>

DDR_A_DQS#4 <6>

DDR_A_DQS5 <6>

DDR_A_DQS#5 <6>

DDR_A_DQS6 <6>

DDR_A_DQS#6 <6>

DDR_A_DQS7 <6>

DDR_A_DQS#7 <6>

1 2

RD9

2_0402_1%

2

CPU Side

+0.6V_VREFCA

VREF traces should be at least 20 mils wide with 20 mils spacing to other

1

sign als

CD15

0.022U_0402_25V7K

2

RD11

24.9_0402_1%

1 2

Compal Electronics, Inc.

Title

Size

Date: Sheet

Compal Electronics, Inc.

P18-DDRIV_CHA: DIMM0

Document Number Re v

LA-D707P

1

17 60Wednesday, May 11, 2016

v0.2

of

DIMM Side

+0.6V_DDR_VREFCA

Layout Note: Place near JDIMM1

10uF*6 1uF*8 330uF*1

10U_0603_6.3V6M

CD93

1

A A

1

2

10U_0603_6.3V6M

CD16

1

2

10U_0603_6.3V6M

CD18

CD17

1

2

10U_0603_6.3V6M

CD19

1

2

10U_0603_6.3V6M

CD21

CD20

CD22

1

2

@

+1.2V_VDDQ+1.2V_VDDQ

10U_0603_6.3V6M

1U_0402_6.3V6K

CD95

CD23

1

2

1U_0402_6.3V6K

1

CD96

2

1U_0402_6.3V6K

1

CD24

2

1U_0402_6.3V6K

1

CD25

CD26

CD27

2

1U_0402_6.3V6K

1

CD28

2

1U_0402_6.3V6K

1

CD31

CD30

CD29

2

1

2

1U_0402_6.3V6K

CD94

+1.2V_VDDQ

C174

330U_2.5V_M

1

+

Part Number = SF000006S00

2

5

4

2

@

CD13

0.1U_0402_10V6K

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

RD8 1K_0402_1%

1 2

RD10 1K_0402_1%

1 2

2015/08/03 2015/12/31

2

CD14

0.1U_0402_10V6K

1

Compal Secret Data

Deciphered Date

5

Aditya11ttt.com

4

3

2

1

(5.2 mm)

DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1

DDR_B_CKE0 DDR_B_CKE1

DDR_B_CS#0 DDR_B_CS#1

DDR_B_ODT0 DDR_B_ODT1

DDR_B_BG0 DDR_B_BG1 DDR_B_BA0 DDR_B_BA1

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14_WE# DDR_B_MA15_CAS# DDR_B_MA16_RAS#

DDR_B_ACT#

DDR_B_PAR DDR_B_ALERT#

PCH_SMBDATA PCH_SMBCLK

SA2_CHB_DIM2 SA1_CHB_DIM2 SA0_CHB_DIM2

1

CD82

0.022U_0402_25V7K

2

RD29

24.9_0402_1%

1 2

JDIMM2A

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

FOX_AS0A827-H2SB-7H

CONN@

CPU Side

+0.6V_B_VREFDQ

VREF traces should be at least 20 mils wide with 20 mils spacing to other sign als

STD

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQS0(T)

DQS0#(C)

DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

DQS1(T)

DQS1#(C)

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

DQS2(T)

DQS2#(C)

DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS3(T)

DQS3#(C)

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

DQS4(T)

DQS4#(C)

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

DQS5(T)

DQS5#(C)

DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55

DQS6(T)

DQS6#(C)

DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS7(T)

DQS7#(C)

DDR_B_D15

8

DDR_B_D10

7

DDR_B_D11

20

DDR_B_D12

21

DDR_B_D14

4

DDR_B_D9

3

DDR_B_D8

16

DDR_B_D13

17

DDR_B_DQS1

13

DDR_B_DQS#1

11

DDR_B_D0

28

DDR_B_D5

29

DDR_B_D7

41

DDR_B_D6

42

DDR_B_D4

24

DDR_B_D1

25

DDR_B_D3

38

DDR_B_D2

37

DDR_B_DQS0

34

DDR_B_DQS#0

32

DDR_B_D20

50

DDR_B_D17

49

DDR_B_D19

62

DDR_B_D22

63

DDR_B_D21

46

DDR_B_D16

45

DDR_B_D18

58

DDR_B_D23

59

DDR_B_DQS2

55

DDR_B_DQS#2

53

DDR_B_D25

70

DDR_B_D24

71

DDR_B_D31

83

DDR_B_D27

84

DDR_B_D28

66

DDR_B_D29

67

DDR_B_D30

79

DDR_B_D26

80

DDR_B_DQS3

76

DDR_B_DQS#3

74

DDR_B_D37

174

DDR_B_D33

173

DDR_B_D35

187

DDR_B_D38

186

DDR_B_D32

170

DDR_B_D36

169

DDR_B_D34

183

DDR_B_D39

182

DDR_B_DQS4

179

DDR_B_DQS#4

177

DDR_B_D44

195

DDR_B_D45

194

DDR_B_D42

207

DDR_B_D47

208

DDR_B_D40

191

DDR_B_D41

190

DDR_B_D43

203

DDR_B_D46

204

DDR_B_DQS5

200

DDR_B_DQS#5

198

DDR_B_D48

216

DDR_B_D53

215

DDR_B_D54

228

DDR_B_D51

229

DDR_B_D52

211

DDR_B_D49

212

DDR_B_D55

224

DDR_B_D50

225

DDR_B_DQS6

221

DDR_B_DQS#6

219

DDR_B_D60

237

DDR_B_D57

236

DDR_B_D58

249

DDR_B_D62

250

DDR_B_D56

232

DDR_B_D61

233

DDR_B_D59

245

DDR_B_D63

246

DDR_B_DQS7

242

DDR_B_DQS#7

240

DDR_B_DQS1 <6>

DDR_B_DQS#1 <6>

DDR_B_DQS0 <6>

DDR_B_DQS#0 <6>

DDR_B_DQS2 <6>

DDR_B_DQS#2 <6>

DDR_B_DQS3 <6>

DDR_B_DQS#3 <6>

DDR_B_DQS4 <6>

DDR_B_DQS#4 <6>

DDR_B_DQS5 <6>

DDR_B_DQS#5 <6>

DDR_B_DQS6 <6>

DDR_B_DQS#6 <6>

DDR_B_DQS7 <6>

DDR_B_DQS#7 <6>

1 2

RD27

2_0402_1%

CD72

0.1U_0402_10V6K

STD

DIMM2_CHB_EVENT# DDR_DRAMRST#_R

CHANNEL-B

RD25 240_0402_1%

DDR_DRAMRST#_R<6,17>

2

1

DI

+0.6V_DDRB_VREFCA

DDR_B_CLK0<6> DDR_B_CLK#0<6>

DDR_B_CLK1<6>

DDR_B_CLK#1<6>

DDR_B_CKE0<6> DDR_B_CKE1<6>

DDR_B_CS#0<6> DDR_B_CS#1<6>

DDR_B_ODT0<6> DDR_B_ODT1<6>

DDR_B_BG0<6> DDR_B_BG1<6> DDR_B_BA0<6> DDR_B_BA1<6>

DDR_B_MA0<6> DDR_B_MA1<6> DDR_B_MA2<6> DDR_B_MA3<6> DDR_B_MA4<6> DDR_B_MA5<6> DDR_B_MA6<6> DDR_B_MA7<6> DDR_B_MA8<6> DDR_B_MA9<6> DDR_B_MA10<6> DDR_B_MA11<6> DDR_B_MA12<6> DDR_B_MA13<6> DDR_B_MA14_WE#<6> DDR_B_MA15_CAS#<6> DDR_B_MA16_RAS#<6>

DDR_B_ACT#<6>

DDR_B_PAR<6> DDR_B_ALERT#<6>

12

PCH_SMBDATA<7,17,19,22>

PCH_SMBCLK<7,17,19,22>

For ECC DIMM

CD92

0.1U_0402_10V6K

@ESD@

PLACE NEAR TO SODIMM

MM Side

2

1

TOP: JDIMM2 CONN

D D

@

12

RD19

0_0402_5%

RD22 0_0402_5%

Non-ECC DIMM

12

RD20 0_0402_5%

12

RD23

@

0_0402_5%

+3VS+3VS+3VS

12

@

12

RD21

0_0402_5%

SA2_CHB_DIM2SA1_CHB_DIM2SA0_CHB_DIM2

RD24 0_0402_5%

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL B : WRITE ADDRESS: 0XA4 READ ADDRESS: 0XA3 SA0 = 0; SA1 = 1; SA2 = 0. DDR4 POR OPERATING SPEED: 1867 MT/S STRETCH GOAL IS 2133 MT/S

C C

Layout Note: Place near JDIMM2.257,259

10uF*2 1uF*2

10U_0603_6.3V6M

1U_0402_6.3V6K

10U_0603_6.3V6M

1

CD62

2

Layout Note: PLACE THE CAP WITHIN 200 MILS FROM THE JDIMM2

B B

+0.6V_DDRB_VREFCA

2

CD69

0.1U_0402_10V6K

1

Layout Note: Place near JDIMM2

10U_0603_6.3V6M

1

A A

2

1U_0402_6.3V6K

1

CD63

CD64

CD65

2

2.2uF*1

0.1uF*1

2

CD70

2.2U_0402_6.3V6M

1

10uF*6 1uF*8

10U_0603_6.3V6M

CD73

CD74

1

2

330uF*1

10U_0603_6.3V6M

CD75

CD76

CD77

1

2

Layout Note: Place near JDIMM2.258

+0.6V_0.6VS+2.5V

1

2

10U_0603_6.3V6M

CD79

CD78

1

2

1

2

@

10uF*2 1uF*1

10U_0603_6.3V6M

1U_0402_6.3V6K

1

CD66

CD67

CD68

2

+3V_PRIM_DB+3V_PRIM

1 2

RD33 0_0402_5%

+1.2V_VDDQ+1.2V_VDDQ

10U_0603_6.3V6M

1U_0402_6.3V6K

CD80

1

CD83

2

@

1U_0402_6.3V6K

CD84

Interleaved Memory

8/2 6

+3V_PRIM_DB

0.1U_0402_10V6K

2

CD60

1

PLACE NEAR TO PIN

1U_0402_6.3V6K

1

CD85

2

1U_0402_6.3V6K

1

CD86

CD87

2

+1.2V_VDDQ

2.2U_0402_6.3V6M

+0.6V_DDRB_VREFCA

2

CD61

1

1U_0402_6.3V6K

1

CD88

CD89

2

DDR_B_D[0..15]<6>

DDR_B_D[16..31]<6>

DDR_B_D[32..47]<6>

DDR_B_D[48..63]<6>

111 112 117 118 123 124 129 130 135 136

255

164

1 2 5 6

9 10 14 15 18 19 22 23 26 27 30 31 35 36 39 40 43 44 47 48 51 52 56 57 60 61 64 65 68 69 72 73 77 78 81 82 85 86 89 90 93 94 98

262

Part Number:LTCX0069FA0

art Value:S SOCKET FOX AS0A827-H2SB-7H 260P DDR4

P

1U_0402_6.3V6K

1

CD90

2

JDIMM2B

STD

VDD1

VDD11

VDD2

VDD12

VDD3

VDD13

VDD4

VDD14

VDD5

VDD15

VDD6

VDD16

VDD7

VDD17

VDD8

VDD18

VDD9

VDD19

VDD10

VDDSPD

VREFCA

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GND

FOX_AS0A827-H2SB-7H

CONN@

VPP1 VPP2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GND

VTT

141 142 147 148 153 154 159 160 163

258

257 259

99 102 103 106 107 167 168 171 172 175 176 180 181 184 185 188 189 192 193 196 197 201 202 205 206 209 210 213 214 217 218 222 223 226 227 230 231 234 235 238 239 243 244 247 248 251 252

261

+1.2V_VDDQ

+0.6V_0.6VS

+2.5V

9/8 Modify

+1.2V_VDDQ

DDR_DRAMRST#_R

+1.2V_VDDQ

2

CD71

@

0.1U_0402_10V6K

1

2

CD81

0.1U_0402_10V6K

1

RD26 1K_0402_1%

1 2

RD28 1K_0402_1%

1 2

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/08/03 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

P19-DDRIV_CHB: DIMM0

Document Number Re v

LA-D707P

1

of

18 60Wednesday, May 11, 2016

of

18 60Wednesday, May 11, 2016

of

18 60Wednesday, May 11, 2016

v0.2

5

Aditya11ttt.com

D D

C C

4

3

2

1

+3VS<5,6,7,9,10,11,13,17,18,20,21,22,23,24,26,28,32,33,34,35,36,37,38,52,55,56>

+3VS

EDP_HPD<5>

EDP_HPD

12

RT11 100K_0402_5%

RTD2132 SMBus revrse to PCH

1 2

EC_SMB_CK2<7,10,22,26,37> EC_SMB_DA2<7,10,22,26,37>

PCH_SMBCLK<7,17,18,22>

PCH_SMBDATA<7,17,18,22>

EDP_CPU_AUX_C<5>

B B

<CPU>

EDP_CPU_AUX#_C<5>

EDP_CPU_LANE_P0_C<5>

EDP_CPU_LANE_N0_C<5>

EDP_CPU_LANE_P1_C<5>

EDP_CPU_LANE_N1_C<5>

A A

EC_BKOFF#<26>

100K_0402_5%

5

RT193 0_0201_5%

1 2

RT194 0_0201_5%

1 2

RT195 0_0201_5%@

1 2

RT196 0_0201_5%@

Layout notes

L

CC97~CC102 must closed to connector

1 2

CT102 .1U_0402_16V7K

1 2

CT101 .1U_0402_16V7K

1 2

CT98 .1U_0402_16V7K

1 2

CT97 .1U_0402_16V7K

1 2

CT103 .1U_0402_16V7K

eDP@

1 2

CT100 .1U_0402_16V7K

eDP@

DB phase : add eDP Lan1 for FHD

20141117

@

1 2

RT14 0_0402_5%

+3VS

TS_BKOFF#

EC_BKOFF#

RT12

LVDS@

12

1

B

2

A

1 2

RT15 0_0402_5%

5

3

CIICSCL1 CIICSDA1

EDP_CPU_AUX

EDP_CPU_AUX#

EDP_CPU_LANE_P0

EDP_CPU_LANE_N0

EDP_CPU_LANE_P1

EDP_CPU_LANE_N1

CT24

1 2

0.1U_0402_16V7K

UT3

P

4

Y

G

LVDS@

TC7SH08FUF_SSOP5

@

PD 100K on LVDS page

EDP_HPD

Delete BKL_PWM_CPU and DP_INT_PWM 20141113

EC_TS_BKOFF# <20>

4

RT34 0_0201_5%

1 2

EDP_HPD_PANEL

EDP_CPU_LANE_N0 EDP_CPU_LANE_P0

EDP_CPU_AUX EDP_CPU_AUX#

EDP_HPD_PANEL <20>

EDP_CPU_LANE_P1

EDP_CPU_LANE_N1

DB phase : add eDP Lan1 for FHD

20141117

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

0_0804_8P4R_5%

1 8 2 7 3 6 4 5

RP6

2

RT16 0_0402_5%

RT17 0_0402_5%

2013/3/1

EDP_LANE_N0 EDP_LANE_P0

EDP_AUX

eDP@

1 2

EDP_AUX#

SD309000080

Layout notes

L

RT16~RT19 must closed to connector

Compal Secret Data

Layout notes

L

RP6 RP9 RP10 must closed to connector

LVDS_TXP1_LP1

LVDS_TXN1_LN1

Deciphered Date

2

LVDS_TXP1_LP1 <20>

LVDS_TXN1_LN1 <20>

2015/3/1

EDP_AUX

EDP_AUX# EDP_LANE_N0 EDP_LANE_P0

RP9

SD309000080

eDP@

4 5 3 6 2 7 1 8

Title

Size

Date: Sheet

LCD_CLK LCD_DATA LVDS_TXN2_LN0 LVDS_TXP2_LP0

0_0804_8P4R_5%

4

Compal Electronics, Inc.

LVDS Translator-RTD2132N

Document Number Re v

LA-D707P

Wednesday, May 11, 2016

LCD_CLK <20> LCD_DATA <20> LVDS_TXN2_LN0 <20> LVDS_TXP2_LP0 <20>

1

v0.2

6019

of

LVDS Power

Aditya11ttt.com

ENVDD_CPU<5>

D D

5

+3VS

1 2

R172 0_0402_5%

+3VS

5

4

RG1

1500P_0402_50V7K

<SI> change to standard par SA00006Y800 (Dif f er ent f oot pri nt)

N6U@

UG1

VIN

EN

G524B1T11U_SOT23-5

SA00006Y800

0_0201_5%

1 2

@

CG1

eDP@

VOUT

1

2

GND

3

/OC

1

2

1

2

Main SA00006Y800

2nd SA00007U000 3rd SA000079400

UG1

6U@

G524B2T11U SOT-23

SA00007BW00

CG2

4.7U_0603_6.3V6K

4

+LCDVDD

0.1U_0402_16V7K CG3

1

2

W=60mils

SM010014520 3000ma 220ohm @100mhz

DCR 0.04

C117

@EMI@

680P_0402_50V7K

INVPWR_B+ +19.5VB

1

C118 68P_0402_50V8J

2

3

W=60mils

JPHW1

@

2

112

JUMP_43X79

6U@

21

FU1

FUSE 0438.500WR 0.5A 32V UL/CSA FAST

SP040004X00

2

+3VS<5,6,7,9,10,11,13,17,18,19,21,22,23,24,26,28,32,33,34,35,36,37,38,52,55,56>

+19.5VB<38,47,48,49,50,53,55,56>

+3VALW<7,13,23,26,27,30,33,35,48,49,50,51,55>

+3VS

+19.5VB

+3VALW

1

Camera

1 2

R170 0_0402_5%

L12

@EMI@

USB20_N5<11>

Part Number = SM070003Y00

USB20_P5<11>

C C

1

4

WCM-2012-900T_4P

1 2

R171 0_0402_5%

USB20_N5_R

2

USB20_P5_R

3

USB20_P5_R

USB20_N5_R

D_MIC_CLK<24>

D_MIC_DATA<24>

Touch Screen

<DB> for 5V/3V TS option

TS@

QTS1

2N7002K_SOT23

+VCC_TOUCH_IN

+3VALW

12

@

13

D

S

RG4 0_0402_5%@

RG5 0_0402_5%TS@

RTS2 100K_0402_5%

B B

+VCC_TOUCH_IN

TS@

1

CTS1

0.1U_0402_16V4Z

A A

1

TS6U@

C5223

2

4.7U 6.3V M X5R

SE00000SO00

+VCC_TOUCH

1

0.1U 16V K X7R

2

@

CTS3

2

12

123

DGS

TS@

QTS2 S TR LP2301ALT1G 1P SOT-23-3

1 2

R36 0_0603_5%@

JPHW3

JP@

112

JUMP_43X39

3

OUT

2

GND

AP2330W-7_SC59-3

Touch Screen Power

TS@

RTS1 1K_0402_5%

CTS2

TS@

1 2

0.047U_0402_16V7K

2

TS6U@

FG2SA00004ZA00

1

IN

2

G

1 2

USB20_N6<11>

USB20_P6<11>

+5VALW

12

TS@

RTS3 100K_0402_5%

TOUCH_ON# <26>

+3VS

+5VS

Part Number = SM070003Y00

5

4

@ESD@ SCA00000U10

D7

2

1

3

PESD5V0U2BT_SOT23-3

<DB>LA1/LA2 closed to Aduio codec

D_MIC_DATA

D_MIC_L_CLK

D_MIC_L_DATA

BKL_PWM_CPU<5>

TS_GPIO_CPU<10>

TS_GPIO_EC<26>

1 2

R5175 0_0402_5%

L13

1

4

WCM-2012-900T_4P

1 2

R173 0_0402_5%

@EMI@

2

3

EMI@ SM01000B600

1 2

LA1 FBMA-L10-160808-301LMT_2P

1 2

R175 0_0402_5%

@ESD@

D3

2

3

PESD5V0U2BT_SOT23-3

1 2

R259 0_0402_5%

TS_GPIO_CPU

TS_GPIO_EC

SCA00000U10

1

D_MIC_L_CLKD_MIC_CLK

D_MIC_L_DATA

R260

1 2

@

R5187

1 2

INVTPWM

<PV> Touch GPIO control by EC

USB20_N6_R

USB20_P6_R

12

0_0402_5%

12

C593 220P_0402_50V7K

12

C594 220P_0402_50V7K

EDP_CPU_LANE_ P 1 EDP_CPU_LANE_ N1

EDP_CPU_LANE_ P 0 EDP_CPU_LANE_ N0

EDP_CPU_AUX EDP_CPU_AUX #

LVDS@

R163 100K_0402_5%

EC_TS_BKOFF#<19>

TS_GPIO

USB20_P6_R

USB20_N6_R

D6

2

1

3

PESD5V0U2BT_SOT23-3

@ESD@ SCA00000U10

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

EC_TS_BKOFF#

2013/02/26 2015/07/08

R166 33_0402_5%

1 2

12

R5176 10K_0402_5%

+3VS

Compal Secret Data

JP@

JUMP_43X39

6U@

FG3 SA00004ZA00

1

IN

AP2330W-7_SC59-3

Deciphered Date

2

DISPOFF#

112

INVTPWM

DISPOFF#

LVDS_TXP1_LP1<19>

LVDS_TXN1_LN1<19>

LVDS_TXP2_LP0<19>

LVDS_TXN2_LN0<19>

LCD_CLK<19>

LCD_DATA<19>

EDP_HPD_PANEL<19>

INVPWR_B+

+VCC_TOUCH

+3VS_CAMERA

JPHW4

2

OUT

GND

3

2

Touch screen

Came ra

+3VS_CAMERA

LCD/LED PANEL Conn.

+LCDVDD

USB20_P6_R

USB20_N6_R DISPOFF# INVTPWM TS_GPIO

USB20_N5_R USB20_P5_R

D_MIC_L_CLK D_MIC_L_DATA

1

2

1

@

C5221 .1U_0402_16V7K

6U@

C5222

4.7U 6.3V M X5R

2

SE00000SO00

Compal Electronics, Inc.

Title

Size

Date: Sheet

Compal Electronics, Inc.

LVDS Connector

Document Number Re v

LA-C707P

CONN@

JLVDS1

1

2

G1

3

G2

4

G3

5

G4

6

G5

7

G6

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

STARC_107K40-000001-G2

SP01000XE00

1

41 42 43 44 45 46

v0.2

of

20 60Wednesday, May 11, 2016

5

Aditya11ttt.com

4

3

2

1

PCH_DPB_P0<5> PCH_DPB_N0<5>

<CPU>

D D

PCH_DPB_P1<5> PCH_DPB_N1<5>

PCH_DPB_P2<5> PCH_DPB_N2<5>

PCH_DPB_P3<5> PCH_DPB_N3<5>

PCH_DPB_P0 PCH_DPB_N0

PCH_DPB_P1 PCH_DPB_N1

PCH_DPB_P2 PCH_DPB_N2

PCH_DPB_P3 PCH_DPB_N3

1 2 1 2

CG270.1U_0402_16V7K CG280.1U_0402_16V7K

CG290.1U_0402_16V7K CG300.1U_0402_16V7K

CG310.1U_0402_16V7K CG320.1U_0402_16V7K

CG330.1U_0402_16V7K CG340.1U_0402_16V7K

2 7

3 6

4 5

RP3 470_0804_8P4R_5%

1 8

2 7

3 6

4 5

RP4 470_0804_8P4R_5%

<Diner SI> change to 8.2 ohm and parallel 0.47p by EMI request

<PV> change to 10 ohm by EMI request

<DB> Delete Choke add parallel 150ohm

PCH_DPB_P3_C HDMI_R_CK+

C C

PCH_DPB_N3_C HDMI_R_CK-

B B

PCH_DPB_P2_C

PCH_DPB_N2_C

HDMI Chock 2nd : SM070003K00

+5VS

A A

1

1 2

RG59 8.2_0402_1%

1 2

RG60 8.2_0402_1%

1 2

RG63 8.2_0402_1%

1 2

RG61 8.2_0402_1%

1 2

RG65 8.2_0402_1%

1 2

RG64 8.2_0402_1%

1 2

RG70 8.2_0402_1%

1 2

RG66 8.2_0402_1%

L

FG1

OUT

IN

GND

AP2330W-7_SC59-3

SA00004ZA00

W=40mils

3

2

0.1U_0402_16V7K

2

CG71

0.47P_0402_50V

1

HDMI_R_D0-PCH_DPB_N0_C

2

CG72

0.47P_0402_50V

1

HDMI_R_D0+PCH_DPB_P0_C

HDMI_R_D1+PCH_DPB_P1_C

2

CG73

0.47P_0402_50V

1

HDMI_R_D1-PCH_DPB_N1_C

HDMI_R_D2+

2

CG74

0.47P_0402_50V

1

HDMI_R_D2-

Layout notes

40 mils

+HDMI_CRT_5V

1

CG46

2

PCH_DPB_P0_C PCH_DPB_N0_C

PCH_DPB_P1_C PCH_DPB_N1_C

PCH_DPB_P2_C PCH_DPB_N2_C

PCH_DPB_P3_C PCH_DPB_N3_C

QG1B

SB00000I700

2N7002KDW_SOT363-6

3

4

+3VS

HDMI_R_CK+

HDMI_R_CK-

HDMI_R_D0+ HDMI_R_D0+

HDMI_R_D0- HDMI_R_D0-

HDMI_R_D1- HDMI_R_D1-

HDMI_R_D1+ HDMI_R_D1+

HDMI_R_D2- HDMI_R_D2-

HDMI_R_D2+ HDMI_R_D2+

HP_DETECT

HDMI_SDATA

HDMI_SCLK

5

@ESD@

D21

1

2

4

5

3

8

L05ESDL5V0NA-4_SLP2510P8-10-9

SC300002C00

@ESD@

D22

1

2

4

5

3

8

L05ESDL5V0NA-4_SLP2510P8-10-9

SC300002C00

SC300002800

DG1

@ESD@

1

2

4

5

3

8

IP4292CZ10-TB

9

10

8

9

7

6

9

10

8

9

7

6

9

10

8

9

7

6

HDMI_R_CK+

HDMI_R_CK-

HP_DETECT

HDMI_SDATA

HDMI_SCLK

PCH_DDPB_HPD<5>

1M_0402_5%

DB phase : For ESD request

20141117

PCH_DDPB_CLK<5>

PCH_DDPB_DAT<5>

+3VS

@

CM26

RG47

+HDMI_CRT_5V

@

10P_0402_50V8J

1

2

+3VS

12

2

QG1A

2N7002KDW_SOT363-6

SB00000I700

2.2K_0804_8P4R_5%

10P_0402_50V8J

1

CM27

2

+HDMI_CRT_5V<22>

+3VS<5,6,7,9,10,11,13,17,18,19,20,22,23,24,26,28,32,33,34,35,36,37,38,52,55,56>

+5VS<20,24,26,27,30,34,35,52,53,56>

20K_0402_5%

HP_DETECT

12

RG56

1

CM17

@

220P_0402_50V7K

2

+3VS

5

QG2B

SB00000I700

2N7002DWH_SOT363-6

QG2A 2N7002DWH_SOT363-6

61

5V Level

PCH_DDPB_CLK HDMI_SCLK

PCH_DDPB_DAT

RG105

1 8 2 7 3 6 4 5

HDMI_SDATA HDMI_SCLK PCH_DDPB_DAT PCH_DDPB_CLK

HDMI Conn.

CONN@

HP_DETECT

+HDMI_CRT_5V

HDMI_SDATA HDMI_SCLK

HDMI_R_CK-

HDMI_R_CK+ HDMI_R_D0-

HDMI_R_D0+ HDMI_R_D1-

HDMI_R_D1+ HDMI_R_D2-

HDMI_R_D2+

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Utility

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

ACON_HMRBL-AK120D

DC232004700

GND1 GND2 GND3 GND4

23 22 21 20

34

+3VS

2

SB00000I700

+HDMI_CRT_5V

+3VS

+5VS

HDMI_SDATA

61

5

Security Classification

2011/06/29 2011/06/29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2011/06/29 2011/06/29

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date : Sheet

2

Date : Sheet

Compal Electronics, Inc.

HDMI Conn/Level shift

Document Number Re v

LA-D707P

1

o f

21 60Wednesday, May 11, 2016

o f

21 60Wednesday, May 11, 2016

o f

21 60Wednesday, May 11, 2016

v0.2

5

Aditya11ttt.com

DP to CRT converter

4

3

2

1

+5VS<20,21,24,26,27,30,34,35,52,53,56>

+3VS<5,6,7,9,10,11,13,17,18,19,20,21,23,24,26,28,32,33,34,35,36,37,38,52,55,56>

+HDMI_CRT_5V<21>

+5VS

+3VS

+HDMI_CRT_5V

CRT@

C60

1

2

+3VS_CRT

0.1U_0402_16V4Z

12

CRT@

R35

CRT@

C61

10U_0603_6.3V6M

1

2

CRT@

R48

4.7K_0402_5%

@

R52

4.7K_0402_5%

+3VS_CRT

@

C40

10U_0603_6.3V6M

1

2

12

100K_0402_5%

DDI2_AUX_DN_C

DDI2_AUX_DP_C

PCH_DPC_P0_C PCH_DPC_N0_C

PCH_DPC_P1_C PCH_DPC_N1_C

+3VS_CRT_DVDD

CRT@

C63

0.1U_0402_16V4Z

1

2

1

2

+VCCK_1V2

CRT@

12

R44

12K_0402_1%

CRT@

C41

0.1U_0402_16V4Z

+3VS_CRT

CRT@

C45

1

2

CRT@

C42

1U_0402_6.3V6K

1

2

CRT@

C46

0.1U_0402_16V4Z

1

2

CRT@

U4104

1

HPD

27

AUX_N

26

AUX_P

29

LANE0P

30

LANE0N

31

LANE1P

32

LANE1N

19

VCCK_12

24

AVCC_33

25

AVCC_12

28

RRX

11

BLUE_N

13

GREEN_N

14

GND_DAC

16

RED_N

33

EPAD_GND

RTD2168-CG_QFN32

Part Number = SA000077U00

CRT@

C43

1

0.1U_0402_25V6

2

5

DVCC_33

+3VS_CRT_DVDD

9

20

DVCC_33

VDD_DAC_33

VGA_SDA VGA_SCL

HSYNC VSYNC

RED_P

GREEN_P

BLUE_P

POL1_SDA POL2_SCL

SMB_SCL

SMB_SDA

LDO_EN

XI/CKIN

CRT@

C47

C48

0.1U_0402_16V4Z

10U_0603_6.3V6M

1

2

6 4 8 7

VGA_RED

15

VGA_GRN

12

VGA_BLU

10

POL1_SDA

22

POL1_SCL

23

RTD2168_SMB_SCL

2

RTD2168_SMB_SDA

3

LDO_EN_1V2

21

XTALOUT_2168

18

XO

XTALIN_2168

17

<SI> change to +HDMI_CRT_5V for SVTP test fail

+HDMI_CRT_5V

182736

45

CRT@

R38

2.2K_0804_8P4R_5%

CRT_DATA CRT_CLK HSYNC VSYNC

RTD2168_SMB_SCL RTD2168_SMB_SDA

+3VS_CRT +3VS_CRT

12

@

POL1_SDA POL1_SCL

12

R53 0_0402_5% R54 0_0402_5%

R42

4.7K_0402_5%

CRT@

R45

4.7K_0402_5%

1 2 1 2

1 2

R39 0_0402_5%@

1 2

R40 0_0402_5%@

12

@

CRT@

R43

4.7K_0402_5%

R46

4.7K_0402_5%

EC_SMB_CK2 <7,10,19,26,37> EC_SMB_DA2 <7,10,19,26,37>

PCH_SMBCLK <7,17,18,19> PCH_SMBDATA <7,17,18,19>

2014-11-24 follow vendor suggest change 36 ohm

1 2

HSYNC

VSYNC

CRT@

L5 36_0402_1%

1 2

CRT@

L6 36_0402_1%

Layout notes

L

R61,R62,R58,R59 close to RTD2168 R55,R57,R60,R56 close to CONN

10P_0402_50V8J

CRT@

C56

1

2

HSYNC_R

VSYNC_R

50 impedance

|← → |

VGA_RED

VGA_GRN

VGA_BLU VGA_BL

12

R51 75_0402_1%

R49 75_0402_1%

R50 75_0402_1%

CRT@

C67

C66

1

22P_0402_50V8

2

CRT@

CRT@ SM01000LU00

1 2

L7 BLM15BA220SN1D 0402

CRT@ SM01000LU00

1 2

L8 BLM15BA220SN1D 0402

CRT@ SM01000LU00

1 2

L9 BLM15BA220SN1D 0402

C69

C68

1

2

CRT@

22P_0402_50V8

2

CRT@

<KBL SI> Change ESD diode package

D4&D5 Only Pop for 6U SKU India Country

1

CRT@

C57 10P_0402_50V8J

2

+HDMI_CRT_5V

C71

C70

1

W=40mils

22P_0402_50V8

2

CRT@

D4

SC300001G00

6

+HDMI_CRT_5V

CRT_CLK

VGA_RE VGA_GR

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT23-6

D5

SC300001G00

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT23-6

CRT Connector

VGA_RE

CRT_DATA

VGA_GR

HSYNC_R

VSYNC_R

C72

0.1U_0201_10V6K

1

CRT_CLK

@

2

I/O2

GND

I/O1

I/O2

GND

I/O1

11

12

13

14

10 15

3

6UINDESD@

2

1

3

6UINDESD@

2

1

CONN@

JCRT1

6

1 7

2 8

3 9

4

5

C-K_80454-5K1-152

DC060004S10

VSYNC_RHSYNC_R

CRT_DATA

G

16 17

VGA_BL

For Power consumption

Measurement

D D

C C

B B

A A

+3VS_CRT+3VS

JPHW2

2

112

JUMP_43X39

JP@

R47 1M_0402_5%

XTALOUT_2168 XTALIN_2168

X1

Crystal

@

3

OUT

2

C64

GND

18P_0402_50V8J

1

27MHZ_10PF_X3G027000BA1H-U

2

@

GND

<PV> change short pad

+3VS +3VS_CRT_DVDD

1 2

R34 0_0603_5%

DDI2_AUX_DN<5> DDI2_AUX_DP<5>

PCH_DPC_P0<5> PCH_DPC_N0<5>

PCH_DPC_P1<5> PCH_DPC_N1<5>

CRT@

C58

1

2.2U_0402_6.3V6M

2

4

1

C65

IN

18P_0402_50V8J

1

2

@

DDI2_HPD<5>

1 2

C49 0.1U_0402_16V7KCRT@

1 2

C52 0.1U_0402_16V7KCRT@

12

C50 0.1U_0402_16V7KCRT@

12

C53 0.1U_0402_16V7KCRT@

12

C51 0.1U_0402_16V7KCRT@

12

C54 0.1U_0402_16V7KCRT@

+VCCK_1V2

CRT@

C59

1

0.1U_0402_16V4Z

2

LDO_EN_1V2

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

2014/02/18 2015/02/20

Deciphered Date

Compal Electronics, Inc.

Title

DP to CRT RTD2168

Size

Document Number Rev

Custom v0.2

LA-D707P

Date: Sheet o f

1

22 60Wednesday, May 11, 2016

5

Aditya11ttt.com

J1

JP@

2

112

+3VALW

RL35

1 2

@

0_0201_5%

D D

1

@

CL20

2

4.7U_0603_6.3V6K

@giga8111@

CL19 close to UL1: Pin 32

CL20 close to UL1: Pin 11

C C

CL19

1

2

4.7U_0603_6.3V6K

1500P_0402_50V7K

+LAN_VDD_3V3

CL9

1

CL28

@

2

1

CL5

2

0.1U_0402_16V7K

Swap P/N 08/16

2

CL1

0.01U_0402_16V7K

1

B B

11/17 reserver for ESD request

1

@EMI@

CL4

0.1U_0402_16V7K

2

JUMP_43X79

@

5

IN

GND

4

SS

APL3512_SOT23-5

+VDDREG

giga8111@

1

CL10

@

2

0.1U_0402_16V7K

4.7U_0603_6.3V6K

CL10& CL16 close to UL1: Pin 23CL9 & CL5 close to UL1: Pin 11,32

SP050005L00 Footprint

+V_DAC

LAN_MDIN3 LAN_MDIP3

LAN_MDIN2 LAN_MDIP2

LAN_MDIN1 LAN_MDIP1

LAN_MDIN0 LAN_MDIP0

TSL1

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+

6

TD2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+ TD4-12MX4-

CAP_LAN-8700GS

SP050008V00

2016-03-03:Change Single Source

(SP050008V00) 10/100 (SP050008Y00) Giga

@ESD@

DM12

4

UG5

OUT

EN

CL16

0.1U_0402_16V7K

100_8166@

LANGND

+LAN_VDD_3V3 Rising time need>0.5mS and <100mS

1

2

3

1

CL29

@

0.1U_0402_16V7K

2

CLK_PCIE_LAN<9> CLK_PCIE_LAN#<9>

PCIE_PTX_C_DRX_P5<11> PCIE_PTX_C_DRX_N5<11>

PCIE_PRX_DTX_P5<11> PCIE_PRX_DTX_N5<11>

25

XGND

24

MCT1

RJ45_TX3-

23

MX1+

RJ45_TX3+

22

MX1-

21

MCT2

RJ45_TX2-

20

MX2+

RJ45_TX2+

19

MX2-

18

MCT3

RJ45_RX1-

17

MX3+

RJ45_RX1+

16

MX3-

15

MCT4

RJ45_TX0-

14

MX4+

RJ45_TX0+

13

TSL1

S X'FORM_ LAN-8100G 1G

SP050008Y00

LAN_MDIN0LAN_MDIP0

3

powe rail need to check

+LAN_VDD_3V3

5

Vbus

2

GND

4

+LAN_VDD_3V3

8151/8166 Co-Lay

LAN_MDIP0 LAN_MDIN0 LAN_MDIP1 LAN_MDIN1 LAN_MDIP2 LAN_MDIN2 LAN_MDIP3 LAN_MDIN3

CL2

LAN_CLKREQ#_RLAN_CLKREQ#

PCIE_PRX_C_DTX_P5 PCIE_PRX_C_DTX_N5

2.49K_0402_1%

1

CL3

EMI@

120P_0402_50V8J

2

3

GND

RL11

3

2

RSET

1 2

LAN_MDIN2LAN_MDIP2

12

LAN_CLKREQ#<9>

PLT_RST#<9,26,28,32,36> EC_PME# <26>

1 2

RL55 0_0805_5%Rshort@

giga8111@

PLT_RST#

CLK_PCIE_LAN CLK_PCIE_LAN#

PCIE_PTX_C_DRX_P5

PCIE_PTX_C_DRX_N5 PCIE_PRX_DTX_P5 PCIE_PRX_DTX_N5

1 8 2 7 3 6 4 5

75_0804_8P4R_1%

SD300002E80

DL1

ESD@

SCA00000U10

RL6 0_0201_5%Rshort@

1 2

CR11 0.1U_0402_10V7K

1 2

CR13 0.1U_0402_10V7K

RP5

2

3

YSLC05CH_SOT23-3

1

LANGND

@ESD@

DM13

4

2

SE167100J80

10P_1808_3KV

1

4

powe rail need to check

+LAN_VDD_3V3

5

Vbus

3

8/15 Change to LDO Mode

+LAN_REGOUT

100_8166@

UL1

1

MDIP0

2

MDIN0

4

MDIP1

5

MDIN1

6

MDIP2

7

MDIN2

9

MDIP3

10

MDIN3

12

CLKREQB

19

PERSTB

15

REFCLK_P

16

REFCLK_N

13

HSIP

14

HSIN

17

HSOP

18

HSON

31

RSET

SA000063500

(SA000063500) 8166GSH 10/100 (SA000084T00) 8111HSH-CG Giga

@

CL21

RTL8111G

UL1

RTL8151GH

SA000084T00

2.2UH +-5% NLC252018T-2R2J-N

1

2

0.1U_0402_16V7K

giga8111@

VDDREG(VDD33)

@

1 2

LL1 0_0603_5%

LL2

1 2

giga8111@

CL8

giga8111@

LL2, CL8, CL23 for 8161

CL8 & CL18 close LL2

+LAN_VDD_1V0

3

AVDD10

8

AVDD10

30

AVDD10

22

DVDD10

11

AVDD33

32

AVDD33

23

+VDDREG +LAN_REGOUT

24

REGOUT

LANWAKEB

ISOLATEB

LED1/GPO

LED2(LED1)

CKXTAL1 CKXTAL2

LED0

GND

EC_PME#

21

EC_LAN_ISOLATEB#_R

20

LAN_ACT#

27 26

LED1/GPO

LAN_LINK#

25

28

XTLI

29

XTLO

33

1

CL23

2

4.7U_0603_6.3V6K

giga8111@

+LAN_VDD_3V3

2

LDO mode Switcing mode

LL1

SMT

CL21

SMT

0.1U_0402_16V7K

LL2

CL8,CL23

CL11

@

1

2

0.1U_0402_16V7K

CL12

SMT

1

CL13

2

0.1U_0402_16V7K

Place CL11~CL12 close UL1 Pin 3,8

+LAN_VDD_3V3=40mil

+VDDREG=40mil

L

+LAN_REGOUT=60mil

+LAN_VDD_3V3

RL10

1 2

0_0603_5%

+LAN_VDD_3V3

12

RL15 10K_0402_5%

EC control 08/17 Add 0ohm

TH1

LAN_ACT# LAN_ACT#_R

RL31 510_0402_5%

1

@

2

1

@

2

@

1

CL14

giga8111@

2

0.1U_0402_16V7K

11/18 modify vendor review results

+LAN_VDD_3V3

12

CL35 68P_0402_50V8J

12

RL30 510_0402_5%

CL34 68P_0402_50V8J

+LAN_VDD_1V0

1

2

0.1U_0402_16V7K

CL13 & CL15 close UL1 Pin22

CL14 & CL27 close UL1 Pin30

1U_0402_6.3V6K

1

@

CL26

CL15

2

10P_0402_50V8J

1

2

0.1U_0402_16V7K

2

1

11/15 change CONN.

JLAN1

10

A2_AmberLED+

9

A1_AmberLED-

8

TX3-

7

TX3+

6

RX1-

5

TX2-

4

TX2+

3

RX1+

2

TX0-

1

TX0+

11

B2_WhiteLED+

12

B1_WhiteLED-

CONN@

LAN_LINK#_RLAN_LINK#

RJ45_TX3-

RJ45_TX3+

RJ45_RX1-

RJ45_TX2-

RJ45_TX2+

RJ45_RX1+

RJ45_TX0-

RJ45_TX0+

1

1U_0402_6.3V6K

1 @

CL27

2

EC_LAN_ISOLATEB#_R

RM11

15K_0402_5%

1 2

0923 PV CNG from DP00 to E500

12

RL71M_0402_5%

3

YL1

10P_0402_50V8J

2

OSC1OSC

CL25

1

GND2GND

4

25MHZ 10PF 5YEA25000102IF50Q3

SJ10000E500

13

GND1

14

GND2

LANGND

CL24

12

+3VS

RM61K_0402_5%

XTLI

XTLO

LAN_MDIP3 LAN_MDIN3

LAN_MDIP1 LAN_MDIN1

6

YSUSB2.0-5_SOT-23-6-6

SC300001400

A A

1

6

YSUSB2.0-5_SOT-23-6-6

SC300001400

5

4

1

CR RTS5237S move to S/B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

2013/02/26 2015/07/08

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size

Date: Sheet

Compal Electronics, Inc.

LAN 8151/8166_ CR RTS5238

Document Number Re v

LA-D707P

1

23 60Wednesday, May 11, 2016

v0.2

of

5

Aditya11ttt.com

+3VS<5,6,7,9,10,11,13,17,18,19,20,21,22,23,26,28,32,33,34,35,36,37,38,52,55,56>

+1.8VS<12>

+5VS<20,21,26,27,30,34,35,52,53,56>

1 2

CA1 4.7U_0402_6.3V6M

1 2

D D

RA3 1K_0402_5%

MUTE_LED_IN<26>

11/24 modify mute LED that controled by EC

+3VS

CPVDD

2

CA17

4.7U_0603_6.3V6K

1

C C

<SI> QA2 change from NMOS to BJT

<PV> QA2 change to QA1.

HDA_SYNC_AUDIO<8>

HDA_RST_AUDIO#<8>

D_MIC_DATA<20> D_MIC_CLK<20>

EC_MUTE#<26>

1 2

+3VS

RA6

4.7K_0402_5%

HDA_RST_AUDIO#

Part Number = SB000008E10 @

@

PLUG_IN#

+1.8VS +DVDD

12

B

2

E

3 1

QA1 MMBT3904WH_SOT323-3

DA3 CH751H-40PT_SOD323-2

@SCS00003500

1 2

CA4 4.7U_0402_6.3V6M

+MIC2_VREFO

12

10K_0402_5%

RA30

1 2

CA11 10U_0603_6.3V6M

1 2

CA14 2.2U_0402_6.3V6M

1 2

CA15 2.2U_0402_6.3V6M

1 2

RA10 39.2K_0402_1%

@

RA25

2.2K_0402_5%

C

21

12

1K_0402_5% RA26

PD#

12

10K_0402_5% RA11

PC Beep

B B

SB Beep

EC Beep

EC_BEEP#<26>

HDA_SPKR<8,10>

L

Layout notes Close chip Pin12

+3VS

+1.8VS

+5VS

INT_MICR_C INT_MICL_CINT_MIC

PC_BEEP

HDA_RST_AUDIO#

ALDO_CAP

ACPVEE

CPVDD CBN CBP

SENSEA

PC_BEEP_R

1 2

CA31 .1U_0402_16V7K

1 2

CA33 .1U_0402_16V7K

4

UA1

20

MIC1_R

19

MIC1_L

18

MIC2_R

17

MIC2_L

31

MIC1_VREFO_L

30

MIC1_VREFO_R

29

MIC2_VREFO

23

LINE2_R

24

LINE2_L

16

MONO_OUT

12

PCBEEP

10

SYNC

11

RESET#

7

LDO3-CAP

34

CPVEE

36

CPVDD

35

CBN

37

CBP

2

GPIO0/DMIC_DATA

3

GPIO1/DMIC_CLK

13

SENSE_A

14

SENSE_B

47

PDB

ALC3227-CG_MQFN48P_6X6

Power down (PD#) power stage for save power 0V: Power down power stage

3.3V: Power up power stage

RA19 47K_0402_5%

1 2

12

RA20 10K_0402_5%

DVDD

DVDD_IO

AVDD1 AVDD2

PVDD1 PVDD2

SPK_OUT_R+

SPK_OUT_R-

SPK_OUT_L+

SPK_OUT_L-

HPOUT_R HPOUT_L

SDATA_OUT

SDATA_IN

BCLK

LINE1_L

LINE1_R

SPDIFO/GPIO2

JDREF

VREF LDO1_CAP LDO2_CAP

AVSS1 AVSS2

DVSS

Thermal Pad

1 2

CA34 .1U_0402_16V7K

1 9

26 40

41 46

45 44

42 43

33 32

5 8

6

22 21 48

15 28 27 39

25 38

4 49

PC_BEEP

3

+DVDD +DVDD_IO

+5VS_AVDD +1.8VS_AVDD

+5VS_PVDD

SPK_R+ SPK_R-

SPK_L+ SPK_L-

HPOUT_R HPOUT_L HP_OUTL

SDATA_IN

JDREF AVREF

CA18 10U_0603_6.3V6M CA19 10U_0603_6.3V6M

Internal Speaker

change 30 ohm from vendor suggest

1 2

RA4 30_0402_1%

1 2

RA5 30_0402_1%

1 2

RA7 22_0402_5%

MIC_JD

RA9 20K_0402_1%

12

CA16 .1U_0402_16V7K

1 2 1 2

RA29 100K_0402_5%

add 100k from vendor suggest 2014 1120

GNDA

2014 1120

12

AVREF

CA24 2.2U_0402_6.3V6M

HP_OUTR

GNDA

1 2

<PV> change short pad

1 2

RA2 0_0603_5%Rshort@

L

Layout notes

CA5 CA6 close Pin1 CA7 CA8 close Pin9

CA9 CA10 close Pin26 CA12 CA13 close Pin40

<PV> change short pad

+5VS_AVDD

CA9

.1U_0402_16V7K

1

2

Headph one

HDA_SDOUT_AUDIO <8> HDA_SDIN0 <8>

HDA_BITCLK_AUDIO <8>

GNDA

SPK_RSPK_R+ SPK_LSPK_L+

Reserve for ESD request.

2

3

DA4 YSLC05CH_SOT23-3

SCA00002900 ESD@

1

GNDA

+5VS_PVDD

CA20

.1U_0402_16V7K

1

2

<PV> change short pad

1 2

RA13 0_0603_5%Rshort@

1 2

RA14 0_0603_5%Rshort@

1 2

RA15 0_0603_5%Rshort@

1 2

RA16 0_0603_5%Rshort@

HP_OUTR_R

GNDA

CA10

4.7U_0603_6.3V6K

CA21

.1U_0402_16V7K

2

10U_0603_6.3V6M

CA5

.1U_0402_16V7K

1

2

1 2

LA4 0_0603_5%Rshort@

2

Need to check 20141110

1

LA6

1 2

TAI-TECH HCB2012VF-601T20 0805

CA23

10U_0603_6.3V6M

CA22

10U_0603_6.3V6M

1

2

1

Internal SPK

wide 40 MIL

HP_OUTL_RINT_MIC_R

2

3

DA6 YSLC05CH_SOT23-3

SCA00000U10 @ESD@

1

CA6

1

2

SM01000NS00

CA7

.1U_0402_16V7K

CA8

10U_0603_6.3V6M

1

2

+5VS

CA12

.1U_0402_16V7K

+5VS

2

3

DA8 YSLC05CH_SOT23-3

SCA00002900

1

Jack detect Combo Mic = High Normal HP = Low

1

+1.8VS+DVDD_IO+DVDD+3VS

1 2

@

LA3 SUPPRE_ KC FBMA-10-100505-101T 0402

PCB Footprint = R_0402

1 2

LA7 0_0402_5%

<7/1>LA3/LA4/LA5/LA6 change to 0-ohm.

<9/1>LA3/LA4/LA5/LA6 change to 0-ohm short-pad

1 2

LA5 0_0402_5%

CA13

4.7U_0603_6.3V6K

1

2

1

GNDA

<DB> Change PWR Rail

+3VS

Need to check 20141110

<DB> Change PWR Rail

+1.8VS+1.8VS_AVDD

PCB Footprint = ACES_50278-00401-001_4P

<DB> change foorprint

1

C125

2

220P_0402_50V7K

@EMI@

+MIC2_VREFO

12

JSPK1

1 2 3 4

SP02000H310

C126

@EMI@

RA17

2.2K_0402_5%

INT_MIC

1 2

5

3

GND

6

4

GND

E-T_3703K-F04N-03R

CONN@

SPK_R-_CONN SPK_R+_CONN SPK_L-_CONN SPK_L+_CONN

MIC_JD

1

2

220P_0402_50V7K

1

C123

C124

2

220P_0402_50V7K

@EMI@

1 2

RA18

CA32

10U_0603_6.3V6M

22K_0402_5%

2

1

GNDA

COMBO AUDIO JACK

CONN@

1

GNDA

JHP

3

1

5

6 2 4 7

GND

YUQIU_PJ750-F07J1BE-A

DC2301411240

of

24 60Wednesday, May 11, 2016

v0.2

1 2

RA27 0_0402_5%

1 2

RA28 0_0402_5%

1 2

CA40

@EMI@

.1U_0402_16V7K

1 2

CA38

@EMI@

A A

.1U_0402_16V7K

1 2

CA39

@EMI@

.1U_0402_16V7K

1 2

CA29

EMI@

.1U_0402_16V7K

1 2

CA30

EMI@

.1U_0402_16V7K

GNDA

5

4

3

INT_MIC

HP_OUTL

HP_OUTR

RA24

22K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

RA21 0_0402_5%

1 2

RA22 0_0402_5%

1 2

RA23 0_0402_5%

12

2013/01/04 2015/01/04

HPR, HPL, 15mil Keep 30mil

CA35

100P_0402_50V8J

CA37

10P_0402_50V8J

CA36

10P_0402_50V8J

1

2

@EMI@

GNDA GNDA GNDAGNDA

Compal Secret Data

Deciphered Date

INT_MIC_R

HP_OUTL_R

PLUG_IN#

HP_OUTR_R

Pin6 and Pin5 Normal OPEN

Compal Electronics, Inc.

Title

Size

C

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

AUDIO ALC3227-CG

Document Number Re v

LA-D707P

A

Aditya11ttt.com

B

C

D

E

WIN 7 Debug Solution

Option 1 : For Closed Chassis Platforms

1 1

2 2

3 3

4 4

Security Classification

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/29 2011/06/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet

D

Date : Sheet

Compal Electronics, Inc.

DC Interface

LA-D707P

DC Interface

E

25 60Wednesday, May 11, 2016

of

Document Number Re v

v0.2

5

Aditya11ttt.com

+3VS

+3VALW_EC<45>

+3VL<13,33,46,47,48>

ESD@

D D

<

+3VALW_EC

C C

VCIN1_ACOK<47>

For Solve tPCH04(Min 9ms) Sequence Timing

<DB> for leakage of LED light

+5VS

B B

RK19 100K_0402_5%

RK20 100K_0402_5%

A A

CK4

PLT_RST#

12

0.1U_0402_16V7K

SI> un-mount RC , Internal PU in 9022

@

RK7 330K_0402_5%

@

CK5 0.1U_0402_16V7K

RK28

100K_0402_5%

RK26

100K_0402_5%

1 2

@

1 2

@

1 2

MUTE_LED_OUT

12

E51TXD_P80DATA

12

PCH_DPWROK

PCH_PWROK

12

R4958 0_0402_5%

R5094 0_0402_5%

R4960 0_0402_5%

EC_RST#

@

1 2

VCIN1_ACOK_R

VCIN1_AC_IN_R

VCIN1_AC_IN_RVCIN1_AC_IN

@

EC_SMB_CK1<46,47>

EC_SMB_DA1<46,47> EC_SMB_CK2<7,10,19,22,37> EC_SMB_DA2<7,10,19,22,37>

2014- 11-13 : Pin16 from MINI1_LED# to PM_SLP_SUS# Pin29 from PM_SLP_SUS# remove Pin25 from EC_INVT_PWM remove Pin19 from EC_+1.05VS_PG to GPU_HOT# Pin21 from GPU_HOT# to EC_+1.05VS_PG Pin25 from EC_INVT_PWM remove

Pin122 from GPU_THERMAL_DET# to PBTN_OUT# Pin123 from X to PM_SLP_S4# Pin18 remove Pin36 remove no support USB CHR

RK21

10K_0402_5%

NMI_DBG#

+3VALW_EC

12

DK2

CH751H-40PT_SOD323-2

PM_CLKRUN#<7> EC_PCIE_WAKE#<9,32>

SCS00003500

+3VS

+3VALW_EC

+3VL

EC_SCI#<5,10>

KSI[0..7]<27>

KSO[0..17]<27>

1 2

RK15 0_0402_5%

1 2

RK16 0_0402_5%

PM_SLP_S3#<9,12,35> PM_SLP_S5#<9>

PM_SLP_SUS#<9,13>

PCH_SUSWARN#<9>

WLAN_ON_LED#<27>

GPU_PROCHOT#<37,56>

MUTE_LED_IN<24>

E51TXD_P80DATA<32> E51RXD_P80CLK<32>

MUTE_LED_OUT<27>

21

4

+3VL

<PV> change short pad

1 2

RK1 0_0603_5%

@

PM_SLP_S3# PM_SLP_S5#

SUSACK# PM_SLP_SUS# PCH_SUSWARN#

TOUCH_ON# EC_KBRST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

CLK_PCI_LPC PLT_RST# EC_RST#

PM_CLKRUN#_R

WLAN_ON_LED#

FAN_SPEED1 VCIN1_ACOK_R E51TXD_P80DATA E51RXD_P80CLK PCH_PWROK

AC_LED#

PBTN_OUT# PM_SLP_S4#

TOUCH_ON#<20> EC_KBRST#<7>

SERIRQ<7,28>

LPC_FRAME#<7,28>

LPC_AD3<7,28> LPC_AD2<7,28> LPC_AD1<7,28> LPC_AD0<7,28>

CLK_PCI_LPC<7>

PLT_RST#<9,23,28,32,36>

EC_SCI#

1 2 1 2

RK10 0_0402_5% RK6 0_0402_5%

FAN_SPEED1<34>

PCH_PWROK<9>

AC_LED#<45>

PBTN_OUT#<9>

PM_SLP_S4#<9,12,35,49>

NMI_DBG#_CPU <5,10>

0.1U_0402_16V7K CK1

1

2

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

EC_SMB_CK2_R EC_SMB_DA2_R

+3VALW_EC

0.1U_0402_16V7K CK2

1

2

UK1

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CLK1/GPIO44

78

EC_SMB_DAT1/GPIO45

79

EC_SMB_CLK2/GPIO46

80

EC_SMB_DAT2/GPIO47

6

PM_SLP_S3#/GPIO04

14

GPIO07

15

GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

AC_PRESENT/GPIO0D

25

PWM2/GPIO11

28

FAN_SPEED1/GPIO14

29

FANFB1/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

PBTN_OUT#/GPIO5D

123

PM_SLP_S4#/GPIO5E

KB9022QD_LQFP128_14X14

+3VALW_EC

LPC & MISC

Int. K/B

Matrix

3

LK1 S SUPPRE_ TAI-TECH HCB1005KF-221T15 0402

1 2

9

22

VCC_LPC

PWM Output

PS2 Interface

SM Bus

11

+EC_VCCA

+3V_EC_VDD

33

67

96

111

125

VCC

VCC0

AVCC

EC_VCCST_PG/GPIO0F

BEEP#/GPIO10

EC_FAN_PWM/GPIO12

AC_OFF/GPIO13

VCIN1_BATT_TEMP/AD0/GPIO38 VCIN1_BATT_DROP/AD1/GPIO39

AD Input

DA Output

SPI Device Interface

SPI Flash ROM

VCOUT0_MAIN_PWR_ON/GPXIOA07

GPIO

GND

24

35

ADP_I/AD2/GPIO3A

AD_BID/AD3/GPIO3B

AD4/GPIO42 AD5/GPIO43

DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

DA2/GPIO3E DA3/GPIO3F

EC_MUTE#/PSCLK1/GPIO4A

USB_EN#/PSDAT1/GPIO4B

PSCLK2/GPIO4C PSDAT2/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

ENKBL/GPXIOA00

WOL_EN/GPXIOA01

ME_EN/GPXIOA02

VCIN0_PH1/GPXIOD00

MISO/GPIO5B MOSI/GPIO5C

SPICLK/GPIO58

SPICS#/GPIO5A

EC_CIR_RX/AD6/GPIO40

SYS_PWROK/AD7/GPIO41

BATT_CHG_LED#/GPIO52

CAPS_LED#/GPIO53

GPIO

PWR_LED#/GPIO54

BATT_LOW_LED#/GPIO55

SYSON/GPIO56 VR_ON/GPIO57

DPWROK_EC/GPIO59

EC_RSMRST#/GPXIOA03

VCIN1_ADP_PROCHOT/GPXIOA05

VCOUT1_PROCHOT#/GPXIOA06

BKOFF#/GPXIOA08

GPO

PCH_PWR_EN/GPXIOA10

PWR_VCCST_PG/GPXIOA11

VCIN1_AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF#/GPXIOD03

GPI

LID_SW#/GPXIOD04

SUSP#/GPXIOD05

PECI/GPXIOD07

V18R/VCC_IO2

GND

AGND

69

94

20mil

113

ECAGND

TAI-TECH HCB1005KF-221T15 0402

ECAGND <45>

1

2

ECAGND

1 2

0_0402_5%

GPXIOA04

GPXIOA09

GPXIOD06

CK3

0.1U_0402_16V7K

RK3

21 23 26 27

63 64 65 66 75 76

68 70 71 72

83 84 85 86 87 88

97 98 99 109

119 120 126 128

73 74 89

GPIO50

90 91 92 93 95 121 127

100 101 102 103 104 105 106 107 108

110 112 114 115 116 117 118

124

LK2

12

+3VALW_EC

PX@

+3VL

RK4

56K +-1% 0402

SD034560280

EC_VCCST_PG_R

EC_FAN_PWM1 EC_CLR_CMOS

B/I# VGA_AC_BATT ADP_I BOARD_ID ADP_ID EC_PME#_EC_R

NMI_DBG# VR_PWRGD EC_MUTE#

EC_SMB_CK3 EC_SMB_DA3 VR_ON WLAN_OFF_LED# TP_CLK TP_DATA

ENBKL

ME_Flash_EN VCIN0_PH

EC_SPI_CLK

SYS_PWROK EC_S0IX_EN BAT_CHG_LED CAP_LOCK# PWR_LED# ACIN SYSON BT_ON_EC PCH_DPWROK

PCH_RSMRST# USB_ON# VCIN1_PH H_PROCHOT#_EC MAINPWON EC_BKOFF#

1 2

RK25 0_0402_5%

PCH_PWR_EN +1.0V_VS_PG_PWR

VCIN1_AC_IN_R EC_ON ON/OFF# LID_SW# SUSP# VCIN1_AC_IN EC_PECI

+V18R

1 2

RK17 43_0402_1%

1

CK8

4.7U_0603_6.3V6K

2

EC Board ID (UMA, Dis, phase) control table

RK2 100K_0402_1%

1 2

BOARD_ID

UMA@

RK4

43K +-1% 0402

1 2

SD034430280

EC_VCCST_PG_R <9,35>

EC_BEEP# <24>

EC_FAN_PWM1 <34>

1 2

R5178 0_0201_5%

ME_Flash_EN <8>

VCIN0_PH <45>

TS_GPIO_EC <20>

PCH_RSMRST# <9>

EC_ON <48>

ON/OFF# <33> LID_SW# <33>

SUSP# <12,13,35,49>

DB_UMA_15kohm:SD034150280, S RES 1/16W 15K +-1% 0402 DB_DIS_20kohm:SD034200280, S RES 1/16W 20K +-1% 0402

SI_UMA_27kohm:SD034270280, S RES 1/16W 27K +-1% 0402 SI_DIS_33kohm:SD034330280, S RES 1/16W 33K +-1% 0402

PV_UMA_43kohm:SD034430280, S RES 116W 43K +-1% 0402

PV_DIS_56kohm:SD034560280, S RES 1/16W 56K +-1% 0402

MV_UMA_75kohm:SD034750280, S RES 1/16W 75K +-1% 0402 MV_DIS_100kohm:SD034100380, S RES 1/16W 100K +-1% 0402

Board ID control

B/I# <46> VGA_AC_BATT <37> ADP_I <45,47>

MINI1_LED# <32>

VR_PWRGD <52> EC_MUTE# <24>

EC_SMB_CK3 <37> EC_SMB_DA3 <37> VR_ON <35,52>

ENBKL <5>

WL_PWREN_EC <30>

EC_SPI_SO <7> EC_SPI_SI <7>

EC_SPI_CS0# <7>

SYS_PWROK <9>

EC_S0IX_EN <12> BAT_CHG_LED <45> CAP_LOCK# <27>

PWR_LED# <33>

ACIN <9,37>

SYSON <12,35,49> BT_ON_EC <32>

PCH_DPWROK <9>

USB_ON# <31,33> VCIN1_PH <45>SUSACK#<9>

MAINPWON <48> EC_BKOFF# <19>

DGPU_PWR_EN <10,38,55,56>

PCH_PWR_EN <13,35,51>

+1.0V_VS_PG_PWR <50>

+3VALW_EC

H_PECI <5>

2

DB

15Kohm

UMA

20Kohm

Dis

2014- 11-13 : Pin64 from BOARD_ID to X no support KBL Pin66 from X to BOARD_ID Pin76 Pin97 swap Pin84 from PM_SLP_S4# to USB_ON# Pin68 from +1.05V_VS_PG_PWR to MINI1_LED# Pin70 NC , no support Pin72 NC , no support Pin86 NC , no suppout

ADP_ID <45>

EC_PME# <23>

WLAN_OFF_LED# <27>

TP_CLK <27> TP_DATA <27>

2014- 11-13 : Pin108 from USB_ON# to +1.05V_VS_PG_PWR Pin106 NC , no support 2014- 11-1 8 Pin108 from +1.05V_VS_PG_PWR to VGA_AC_BATT 2014- 11-2 4 Pin108 from VGA_AC_BATT to 1.05V_VS_PG_PWR

2014-11-25 Reserve for co-lay Nuvoton NPCE388N

SI PV

27Kohm 33Kohm

43Kohm 56Kohm

MV

75Kohm

100Kohm

Current

Reserve EC_CLR_CMOS for clear CMOS

(2016-03-04 : Confirm intel platform not support EC Clear CMOS function)

1 2

RK106 0_0402_5%

EC_CLR_CMOS

R483

@

10K_0402_5%

1 2

<SI> EC request to add RK9

VR_HOT#<52>

EC_SPI_CLK PCH_SPI_CLK_R

CC128 RC369 place near EC Side

VR_HOT#

H_PROCHOT#_EC

TP_CLK

TP_DATA

PCH_PWR_EN PLT_RST# EC_ON

100K_0804_8P4R_5%

PBTN_OUT#

EC_CLR_CMOS

LID_SW#

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

EC_SCI#

SYSON

SUSP#

1 2

RC369

EMI@

EMI request

RP12

15_0402_5%

1

NoteRK4

@

13

@

D

2

Q51

G

2N7002K_SOT23-3

S

1 2

0_0402_5%

RK8

13

D

2

G

QK1

@

2N7002_SOT23-3

RK12 4.7K_0402_5%

RK13 4.7K_0402_5%

R295 1K_0402_5%@

RK107 10K_0402_5%

RK18 47K_0402_5%

22P_0402_50V8J

S

1 2

RK9 0_0402_5%

1 2

18 27 36 45

1 2

@

12

18 27 36 45

2.2K_0804_8P4R_5%

12

RK23 100K_0402_5%

1 2

@

RK27 100K_0402_5%

1 2

@

CC144

@EMI@

CLR_CMOS# <9>

PROCHOT# <5>

+3VALW

+3VL

+3VALW_EC

+3VS

RP11

RK1410K_0402_5% @

PCH_SPI_CLK_R <7>

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/29 2011/06/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

EC ENE-KB9022

Size

Document Number R ev

Custom

LA-D707P

Date: Sheet

2

Date: Sheet

1

26 60Wednesday, May 11, 2016

v0.2

of

TP Button BD Connector

Aditya11ttt.com

+3VALW<7,13,20,23,26,30,33,35,48,49,50,51,55>

+5VALW<12,13,20,30,31,33,35,38,48,49>

+3VALW

+5VALW

TP_CLK<26> TP_DATA<26>

TP_SMBCLK<7> TP_SMBDATA<7>

PS2+SMBus

YSLC05CH_SOT23-3

SCA00000U10

ESD@

DM5

+3VALW

2

3

1

2

470P_0402_50V8J

C135

1

C136

2

470P_0402_50V8J

CONN@

JTP1

1

2

3

4

5

6

7

G1

8

G2

JXT_FP202DH-006M10M

SP01001YK00

<SI> add 470p for EMI issue

1

@

+5VALW +5VALW

1

@EMI@

C134 470P_0402_50V8J

2

2014-11-24 BOM control

Amber

12

R157

3.3K_0402_5%

12

White

R158

3.3K_0402_5%

KSI[0..7]<26>

KSO[0..17]<26>

MUTE_LED_OUT<26>

1

CC122 100P_0402_50V8J

2

ESD@

CAP_LOCK#<26>

KSI7 KSI6 KSI5 KSI4 KSI3 KSI2 KSI1 KSI0

1

CC123 100P_0402_50V8J

2

ESD@

KSO17 KSO16 KSO15 KSO14 KSO13 KSO12 KSO11 KSO10

KSO9 KSO8 KSO7 KSO6 KSO5 KSO4 KSO3 KSO2 KSO1

KSO0

CAP_LOCK#

WLAN_OFF_LED# WLAN_ON_LED#

CAP_LOCK# MUTE_LED_OUT

Keyboard conn

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15 KSO16

+5VS

1 2

R203 3.3K_0402_5%

1 2

R207 3.3K_0402_5%

+5VS

KSO17

JKB1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

ACES_50690-0320N-P01

CONN@ SP01001RG00

G1

32

G2

33 34

WLAN_OFF_LED#<26> WLAN_ON_LED# <26>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2013/02/26 2015/07/08

Compal Secret Data

Deciphered Date

KSI0

ESD@

C193 100P_0402_50V8J

Title

Size

B

Date : She et

12

Compal Electronics, Inc.

KB/TP

Document Number Re v

LA-D707P

27 60Wednesday, May 11, 2016

v0.2

o f

5

Aditya11ttt.com

4

3

2

1

H3

H_2P8

HOLEA

1

H10

H_5P0

HOLEA

1

+3VS

+3VS<5,6,7,9,10,11,13,17,18,19,20,21,22,23,24,26,32,33,34,35,36,37,38,52,55,56>

D D

TPM2.0

+3VS

0.1U_0402_16V4Z

R28

0_0402_5%

+3VS_TPM

TPM@

C35

TPM@

0.1U_0402_16V4Z

@

1

C36

2

PLT_RST#

12

1

C37

2

@

1

2

0.1U_0402_16V4Z

1 2

R26 0_0402_5%TPM@

1

@

C34

C C

LPC_AD0<7,26> LPC_AD1<7,26> LPC_AD2<7,26> LPC_AD3<7,26>

LPC_FRAME#<7,26> PLT_RST#<9,23,26,32,36>

SERIRQ<7,26>

CLK_PCI_TPM<7>

+3VS_TPM

B B

1 2

R27

@

4.7K_0402_5%

1 2

R29 4.7K_0402_5%@

12

TPM@

R31

4.7K_0402_5%

0.1U_0402_16V4Z

@

U4

26

LAD0

23

LAD1

20

LAD2

17

LAD3

22

LFRAME#

16

LRESET#

27

SERIRQ

21

LCLK

6

GPIO

7

PP

4

GND

11

GND

18

GND

25

GND

SLB9665TT2.0-FW-5.00_TSSOP28

VDD VDD VDD VDD

2

5 10 19 24

1

NC

2

NC

3

NC

8

NC

9

NC

12

NC

13

NC

14

NC

15

NC

28

NC

H4

H_2P5

HOLEA

@

1

H15

H_5P0

HOLEA

@

1

H19

H_2P4X3P0N

HOLEA

@

Screw Hole

H2

H1

H_2P5

HOLEA

@

1

H16

H_5P0

HOLEA

@

1

H8

H_2P4N

HOLEA

@

1

@

H17

H_5P0

HOLEA

@

1

H18

H_2P4X3P0N

HOLEA

1

H14

H_2P8

HOLEA

1

@

H11

H_5P0

HOLEA

1

@

H12

H_2P8

HOLEA

1

H7

H_2P5

HOLEA

1

@

H6

H_2P5

HOLEA

1

@

H5

H_2P5

HOLEA

@

H9

H_5P0

HOLEA

1

@

1

@

FD3

SLB9665 (SA00007XU00 )-->TPM2.0 SLB9660 (SA00007AB00 ) -->TPM1.2

A A

Security Classification

2013/02/26 2015/07/08

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2013/02/26 2015/07/08

3

Compal Secret Data

Deciphered Date

@

1

FIDUCIAL_C40M80

2

FD4

@

1

FIDUCIAL_C40M80

Compal Electronics, Inc.

Title

Size

Date : She et

Compal Electronics, Inc.

TPM/Screw

Document Number Re v

LA-D707P

FD2

@

1

FIDUCIAL_C40M80

FD1

@

1

FIDUCIAL_C40M80

28 60Wednesday, May 11, 2016

1

v0.2

o f

5

Aditya11ttt.com

4

3

2

1

BOM control

Plat f or m Silego P/N

D D

Intel ULT UMA

Intel ULT Dis

SLG3NB3455VTR SA00008IQ00

SLG3NB3456VTR SA00008J800

Compal PN

25MHz(A) 32.768KHz 24MHz(B) 27MHz 8MHz Remark

1 1 1

1 1 1 1

X X

X

GCLKUMA@

GCLKPX@

Base on A32 32.768KHz use 10ppm, G-CLK 25MHz X'TAL use 10ppm.

C C

B B

A A

Security Classification

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/06/10 2014/07/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

GCLK

Size

Document Number R ev

LA-D707P

Date: Sheet

1

29

v0.2

of

60Wednesday, May 11, 2016

of

60Wednesday, May 11, 2016

of

60Wednesday, May 11, 2016

5

Aditya11ttt.com

4

3

2

1

G1 G2

+5VS

+5VALW

+3VALW

+3VS_WLAN_R

9 10

+5VS<20,21,24,26,27,34,35,52,53,56>

2.5" SATA HDD

D D

<PV> change short pad

+5VS

1 2

R201 0_0603_5%

1 2

R202 0_0603_5%

+5VS_HDD1

SATA_PTX_DRX_P0<11> SATA_PTX_DRX_N0<11>

SATA_PRX_DTX_N0<11>

SATA_PRX_DTX_P0<11>

1 2

C155 0.01U_0402_16V7K

1 2

C156 0.01U_0402_16V7K

1 2

C153 0.01U_0402_16V7K

1 2

C154 0.01U_0402_16V7K

<SI> add 470p for EMI issue

C C

+5VS_HDD1

SATA_PTX_C_DRX_P0 SATA_PTX_C_DRX_N0

SATA_PRX_C_DTX_N0 SATA_PRX_C_DTX_P0

+5VALW<12,13,20,27,31,33,35,38,48,49>

+3VALW<7,13,20,23,26,27,33,35,48,49,50,51,55>

+3VS_WLAN_R<32>

<DB> change JHDD pin define

CONN@

JHDD

1

2

3

4

5

6

7

8

2

C140 470P_0402_50V8J

1

EMI@

8

ACES_51524-0080N-001

SP01001A900

2.5" SATA ODD

+5VS

+5VS_ODD

C227

10U_0603_6.3V6M

B B

+3VALW

10U_0603_6.3V6M

1

2

1

2

@

C229

2

C228

10U_0603_6.3V6M

ODD_PWR<10>

+5VALW

WL_PWREN_EC<26>

U20

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

C224

1U_0402_10V4Z

1

EM5209VF DFN 14P DUAL LOAD SW

SA00007PM00

2

VOUT1 VOUT1

CT1

GND

CT2

VOUT2 VOUT2

GPAD

14 13

12

11

10

9 8

15

C226

1 2

560P_0402_50V7K C230

12

100P_0402_50V8J

1

2

1U_0402_10V4Z

C223

+3VS_WLAN_R

ODD_PLUG#<11>

SATA_PTX_DRX_P1<11> SATA_PTX_DRX_N1<11>

SATA_PRX_DTX_N1<11> SATA_PRX_DTX_P1<11>

CH751H-40PT_SOD323-2

SCS00003500

1 2

2 1

DC6

CS11 0.01U_0402_16V7K CS14 0.01U_0402_16V7K

CS15 0.01U_0402_16V7K CS18 0.01U_0402_16V7K

@

R51920_0201_5%

12 12

ODD_DA#<10>

CH751H-40PT_SOD323-2

+5VS_ODD

1 2

@

2 1

DC7

SCS00003500

SATA_PTX_C_DRX_P1 SATA_PTX_C_DRX_N1

SATA_PRX_C_DTX_N1 SATA_PRX_C_DTX_P1

R51930_0201_5%

1

ESD@

CS7

2

0.1U_0402_16V7K

CONN@

JODD

1

2

3

4

5

6

7

8

9

10

11

GND

12

GND

ACES_51524-0100N-001

SP01001AI00

A A

Security Classification

2013/02/26 2015/07/08

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2013/02/26 2015/07/08

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

B

Date : She et

2

Date : She et

Compal Electronics, Inc.

HDD/ODD Conn

Document Number Re v

LA-D707P

1

o f

30 60Wednesday, May 11, 2016

o f

30 60Wednesday, May 11, 2016

o f

30 60Wednesday, May 11, 2016

v0.2

A

Aditya11ttt.com

USB3_TX1_N<11>

1 1

2 2

USB3_TX1_P<11>

USB3_RX1_N<11>

USB3_RX1_P<11>

LM3 2nd : SM070002J00

USB3_TX1_N USB3_TX1_C_N

0.1U_0402_16V7K

USB3_TX1_P USB3_TX1_C_P

0.1U_0402_16V7K

1 2

RS6 0_0402_5%

1 2

RS3 0_0402_5%

<SI> change to 0504 choke

LM3

USB20_P1<11>

USB20_N1<11>

SM070003Z00

1 2

MCM1012B900F06BP_4P

34

USB20_P1_C

USB20_N1_C

B

12

CS2

12

CS1

LM1,LM2 2nd : SM070003K00

USB3RXDN1_C

RG76

150_0402_5%

@

1 2

USB3RXDP1_C

1 2

RS2 0_0402_5%

@

1 2

RS1 0_0402_5%

<DB> Delete Choke add parallel 150ohm

C

USB3TXDN1_C_R

RG75

150_0402_5%

1 2

USB3TXDP1_C_R

D

+5VALW<12,13,20,27,30,33,35,38,48,49>

USB3.0 need support 3.5A

hange USB PWR SW SA00007AO00

c

+5VALW

W=100mils

USB_ON#<26,33>

USB_ON#

RS4 0_0402_5%

ESD@

DM1

1

YSLC05CH_SOT23-3

low active

1

CS3

0.1U_0402_16V7K

2

1 2

SCA00000U10

USB20_N1_C

2

USB20_P1_C

3

US1

OUT

5

IN

GND

4

EN

OCB

SY6288D20AAC_SOT23-5

SA00007AO00

1

2

3

+USB_VCCA

@

CS4

W=100mils

1

CS5

2

1000P_0402_50V7K

<DB> change JUSB1 footprint

E

+5VALW

1

2

1

2

0.1U_0402_16V7K

DB Phase add CS22 reserve 20141113

@

+

CS6

CS22

2

47U_0805_6.3V6M

150U_B2_6.3VM_R45M

USB2.0/USB3.0 port 1

JUSB1

USB3RXDN1_C

USB3RXDP1_C

USB3TXDN1_C_R

ESD@

USB3TXDP1_C_R

DM2

1

2

4

5

3

8

TVWDF1004AD0 DFN ESD

SC300002800

9

10

8

9

7

6

USB3RXDN1_C

USB3RXDP1_C

USB3TXDN1_C_R

USB3TXDP1_C_R

USB20_N1_C USB20_P1_C

USB3RXDN1_C USB3RXDP1_C

USB3TXDN1_C_R USB3TXDP1_C_R

1 2 3 4 5 6 7 8 9

CONN@

VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+

TAITW_PUBAU1-09FNLS1NN4H0

GND GND GND GND

10 11 12 13

3 3

USB20_N2<11>

USB20_P2<11>

USB2.0 port x 1

<SI> change to 0504 choke

LM5

SM070003Z00

1 2

MCM1012B900F06BP_4P

34

USB20_N2_C

USB20_P2_C

D29 ESD@

SCA00000U10

1

YSLC05CH_SOT23-3

USB20_N2_C

2

USB20_P2_C

3

+USB_VCCA

USB20_N2_C USB20_P2_C

CONN@

JUSB2

1

VBUS

2

D-

3

D+

4

SHIELD

5

GND

6

GND

7

GND

8

GND

TAITW_PUBAU0-04FLBSCNN4H0

LM5 2nd : SM070002J00

4 4

Security Classification

2013/02/26 2015/07/08

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2013/02/26 2015/07/08

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

B

Date : She et

D

Date : She et

Compal Electronics, Inc.

USB 3.0/2.0 conn

Document Number Re v

LA-D707P

E

o f

31 60Wednesday, May 11, 2016

o f

31 60Wednesday, May 11, 2016

o f

31 60Wednesday, May 11, 2016

v0.2

5

Aditya11ttt.com

4

3

2

1

0.1U_0402_25V6

@RF@

R5182

1

CN2

22U_0603_6.3V6K

2

100P_0402_50V8J

12

+3VS

+5VALW

+3VALW

+3VS_WLAN_R

DB Phase For RF request 20141117

12

@RF@

R5183

1

2

0.1U_0402_25V6

0.1U_0402_16V7K

@RF@

R5184

CN3

100P_0402_50V8J

12

+3VS<5,6,7,9,10,11,13,17,18,19,20,21,22,23,24,26,28,33,34,35,36,37,38,52,55,56>

+5VALW<12,13,20,27,30,31,33,35,38,48,49>

+3VALW<7,13,20,23,26,27,30,33,35,48,49,50,51,55>

+3VS_WLAN_R<30>

D D

+3VS_WLAN

JWLAN1

1

1_GND

USB20_P4<11> USB20_N4<11>

+3VS_WLAN

12

RN3 10K_0402_5%

1 2

C C

EC_PCIE_WAKE#<9,26>

RN13 0_0201_5%

MC_WAKE#

CLK_PCIE_WLAN<9>

CLK_PCIE_WLAN#<9>

DB Phase For RF request 20141117

PCIE_PTX_C_DRX_P6<11>

PCIE_PTX_C_DRX_N6<11>

PCIE_PRX_DTX_P6<11>

PCIE_PRX_DTX_N6<11>

MINI1_CLKREQ#<9>

10P_0402_50V8J

12

@RF@

R5186

R5185

3

3_USB_D+

5

5_USB_D-

7

7_GND

9

9_N/C

11

11_N/C

13

13_N/C

15

15_N/C

17

17_N/C

19

19_N/C

21

21_N/C

23

23_N/C

25

33_GND

27

35_PERp0

29

37_PERn0

31

39_GND

33

41_PETp0

35

43_PETn0

37

45_GND

39

47_REFCLKP0

41

49_REFCLKN0

43

51_GND

45

53_CLKREK0#

47

55_PEWake0#

49

57_GND

51

59_N/C

53

61_N/C

55

63_GND

57

65_N/C

59

67_N/C

61

69_GND

63

71_N/C

65

73_N/C

67

75_GND

LOTES_APCI0019-P003H

CONN@ SP070010DA0

W_DISABLE2#_54 W_DISABLE1#_56

3.3V_2

3.3V_4

LED1#_6

N/C_8 N/C_10 N/C_12 N/C_14

LED2#_16

GND_18

N/C_20 N/C_22

N/C_32 N/C_34 N/C_36

CLink Reset_38 CLink DATA_40

CLink CLK_42

COEX3_44 COEX2_46 COEX1_48

SUSCLK_50

PERST0#_52

N/C_58 N/C_60 N/C_62

RESERVED_64

N/C_66 N/C_68 N/C_70

3.3V_72

3.3V_74

GND

GND NC_70 NC_71

2 4 6 8 10 12 14 16 18 20 22

24 26 28 30 32 34 36 38 40 42

RN14 0_0201_5%

44 46 48 50 52 54 56 58 60 62 64 66

68 69 70 71

+3VS_WLAN

100P_0402_50V8J

12

@RF@

+3VS_WLAN

R5180

12

E51TXD_P80DATA <26> E51RXD_P80CLK <26>

SUSCLK <9> PLT_RST# <9,23,26,28,36>

BT_ON_EC <26>

WL_OFF# <10>

R5179

@RF@

1 2

<MV > connect to +3VS_WLAN

1 2

0.1U_0402_25V6

RN7

4.7K_0402_5%

DB Phase For RF request 20141117

MINI1_LED# <26>

+3VS_WLAN

12

@RF@

R5181

+3VS_WLAN_R +3VS_WLAN

R271

1 2

0_0805_5%

NGFF and WLAN

+3VS +3VS_WLAN

B B

2

G

WAKE#<9>

1 3

D

@

2N7002H_SOT23-3

S

QB8

Unpop QB4 and RL23 for not support OBFF

A A

5

@

RL25

100K_0402_5%

MC_WAKE#

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2013/02/26 2015/07/08

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size

Date: Sheet

Compal Electronics, Inc.

WLAN-BT

Document Number Re v

LA-D707P

1

32 60Wednesday, May 11, 2016

v0.2

of

A

Aditya11ttt.com

B

C

D

E

+3VL<13,26,46,47,48>

EMI@

1 2

1

EMI@

C137

2

470P_0402_50V8J

+5VALW<12,13,20,27,30,31,35,38,48,49>

+3VS<5,6,7,9,10,11,13,17,18,19,20,21,22,23,24,26,28,32,34,35,36,37,38,52,55,56>

+3VALW<7,13,20,23,26,27,30,35,48,49,50,51,55>

C139

470P_0402_50V8J

11/26 change CONN.

CONN@

JIO1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

G1 G2

CVILU_CF31181D0R4-10-NH

SP011411241

Powert Button Connector

1 1

@EMI@

C166

LID_SW#<26> ON/OFF#<26>

2 2

+3VL

1

0.1U_0402_16V7K

2

<DB> change JPWR footprint by DFB request

JPWR

1

2

3 4

SP01000TB10

PCB Footprint = HB_A090420-SAHR21_4P

Layout notes

L

PJ9 place Top layer, PJ6 place Bottom layer

5

3

G1

6

4

G2

E-T_6916K-Q04N-03R

CONN@

SHORT PADS

PJ9

@

ON/OFF#

1

CC125 100P_0402_50V8J

2

ESD@

@

PJ6

1 2

SHORT PADS

LID_SW#

R215

12

100K_0402_5%

+3VL

IO BD Connector ( USB2.0,Card reader,HDD & PWR LED )

<SI> add 470p for EMI issue

+5VALW

+3VS

+3VALW

USB20_N7_C USB20_P7_C

USB20_N3_C USB20_P3_C

SATA_LED#

PWR_LED#

1

EMI@

C138

2

470P_0402_50V8J

DB phase : modify pin define

20141114

<SI> add 470p for EMI issue

Card reader

USB2.0 ( on small BD )

USB_ON#<26,31>

SATA_LED#<11>

PWR_LED#<26>

+3VL

+5VALW

+3VS

+3VALW

19 20

LM4

3 3

USB20_N3<11>

USB20_P3<11>

CC1523.3P_0402_50V8J

EMI@

<MV> add AC cap

USB20_N7<11>

USB20_P7<11>

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

Compal Secret Data

Deciphered Date

EMI@

2015/07/082013/02/26

CC1543.3P_0402_50V8J

D

SM070003Z00

1 2

MCM1012B900F06BP_4P

<SI> change to 0504 choke

LM6

SM070003Z00

1 2

MCM1012B900F06BP_4P

Title

Size

Document Number Re v

B

LA-D707P

Date : She et

LA-D707P

USB20_N3_C

34

USB20_P3_C

USB20_N7_C

34

USB20_P7_C

Compal Electronics, Inc.

IO CON

33 60Wednesday, May 11, 2016

E

v0.2

o f

A

Aditya11ttt.com

B

C

D

+3VS<5,6,7,9,10,11,13,17,18,19,20,21,22,23,24,26,28,32,33,35,36,37,38,52,55,56>

E

+3VS

+5VS<20,21,24,26,27,30,35,52,53,56>

1 1

2 2

+5VS

<PV> change short pad

1A

R5177

1 2

0_0603_5%

10U_0603_10V6M

40 mils

+FAN1

0.1U_0402_16V7K

C4801

1

2

Layout notes

L

C4801 C5214 close to CONN

C5214

1

Close to Connector

2

+3VS

12

RE50 10K_0402_5%

FAN_SPEED1<26>

+FAN1

1

CE24

0.01U_0402_25V7K

2

RE51

1 2

@

10K_0402_5%

EC_FAN_PWM1<26>

EC_FAN_PWM1

+FAN1

<DB> change FAN pin define

CONN@

JFAN1

6

GND2

5

GND1

4

3

2

1

ACES_50271-0040N-001

SP02000TS00

+5VS

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2015/07/082013/02/26

D

Title

Size

Document Number Re v

B

Date : She et

Compal Electronics, Inc.

FAN

LA-D707P

E

v0.2

o f

34 60Wednesday, May 11, 2016

o f

34 60Wednesday, May 11, 2016

o f

34 60Wednesday, May 11, 2016

A

Aditya11ttt.com

B

C

D

E

1

2

0.1U_0402_25V6 CC163

@ESD@

+5VS

PM_SLP_S3#<9,12,26>

For meet tPLT17 & tCPU28 power down sequence. tPLT17 : 1us (Max) tCPU28 : 1us (Max)

+3VALW

12

R5096 100K_0402_1%

@

PM_SLP_S3_H

61

PM_SLP_S3#

For meet tPLT15 power down sequence(Un-Stuf f) tPLT15 : 1us (Max)

PM_SLP_S4#<9,12,26,49>

2

R5095

100K_0402_1%

5

@

Q5003A DMN65D8LDW-7_SOT363-6

SB00000I700

+3VALW

12

@

PM_SLP_S4_H

34

@

Q5003B DMN65D8LDW-7_SOT363-6

SB00000I700

61

2

@

Q5002A DMN65D8LDW-7_SOT363-6

SB00000I700

34

@

Q5002B DMN65D8LDW-7_SOT363-6

5

SB00000I700

61

@

2

Q5004A DMN65D8LDW-7_SOT363-6

SB00000I700

34

@

Q5004B

5

DMN65D8LDW-7_SOT363-6

SB00000I700

VR_ON <26,52>

EC_VCCST_PG_R <9,26>

SUSP#

SYSON <12,26,49>

@RF@

10U_0603_6.3V6M

C575

1

@ESD@

1

2

+5VALW

CC162

0.1U_0402_25V6

@ESD@

Q21

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

EM5209VF DFN 14P DUAL LOAD SW

1

SA00007PM00

CC158

2

0.1U_0402_25V6

VOUT1 VOUT1

CT1

GND

CT2

VOUT2 VOUT2

GPAD

14 13

12

11

10

9 8

15

1 2

C554 100P_0402_50V8J

1 2

C557 680P_0402_50V7K

+3VALW

1 1

2 2

+5VALW

SUSP#<12,13,26,49>

CC161

0.1U_0402_25V6

@ESD@

1

2

@ESD@

SUSP#

1

CC160

CC157

2

0.1U_0402_25V6

@ESD@

2

22U_0805_6.3V6M

CC140

1

2

+3VS

C570

10U_0603_6.3V6M

1

2

For +1.8V_PRIM Discharge

+1.8V_PRIM+5VALW

12

R5092 100K_0402_1%

PCH_PWR_EN#

61

3 3

PCH_PWR_EN<13,26,51>

2

Q5001A DMN65D8LDW-7_SOT363-6

SB00000I700

12

R5093 22_0603_1%

34

Q5001B DMN65D8LDW-7_SOT363-6

5

SB00000I700

4 4

Security Classification

A

Security Classification

2014/10/09 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2014/10/09 2015/12/31

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet

D

Date : Sheet

Compal Electronics, Inc.

DC Interface

Document Number Re v

LA-D707P

DC Interface

E

o f

35 60Wednesday, May 11, 2016

o f

35 60Wednesday, May 11, 2016

o f

35 60Wednesday, May 11, 2016

v0.2

1

Aditya11ttt.com

2

3

4

5

U666A @

A A

12

R1691 0_0402_5%

SD028000080

PX@ SA00000OH00

4

12

PX@

R1631 100K_0402_5%

AF30

PCIE_RX0P

AE31

PCIE_RX0N

AE29

PCIE_RX1P

AD28

PCIE_RX1N

AD30

PCIE_RX2P

AC31

PCIE_RX2N

AC29

PCIE_RX3P

AB28

PCIE_RX3N

AB30

PCIE_RX4P

AA31

PCIE_RX4N

AA29

PCIE_RX5P

Y28

PCIE_RX5N

Y30

PCIE_RX6P

W31

PCIE_RX6N

W29

PCIE_RX7P

V28

PCIE_RX7N

V30

NC#V30

U31

NC#U31

U29

NC#U29

T28

NC#T28

T30

NC#T30

R31

NC#R31

R29

NC#R29

P28

NC#P28

P30

NC#P30

N31

NC#N31

N29

NC#N29

M28

NC#M28

M30

NC#M30

L31

NC#L31

L29

NC#L29

K30

NC#K30

CLOCK

AK30

PCIE_REFCLKP

AK32

PCIE_REFCLKN

N10

TEST_PG

AL27

PERSTB

216-0841018 A0 SUN PRO S3

SA000098V10

GPU_RST#

PCI EXPRESS INTERFACE

DC5

CH751H-40PT_SOD323-2

1 2

R1146 0_0402_5%R30@

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

SCS00003500

21

R70@

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

NC#W24 NC#W23

NC#V27 NC#U26

NC#U24 NC#U23

NC#T26 NC#T27

NC#T24 NC#T23

NC#P27 NC#P26

NC#P24 NC#P23

NC#M27

NC#N26

PEG_PTX_C_DRX_P0<11> PEG_PTX_C_DRX_N0<11>

PEG_PTX_C_DRX_P1<11> PEG_PTX_C_DRX_N1<11>

PEG_PTX_C_DRX_P2<11> PEG_PTX_C_DRX_N2<11>

PEG_PTX_C_DRX_P3<11> PEG_PTX_C_DRX_N3<11>

B B

C C

DGPU_HOLD_RST#<10>

PLT_RST#<9,23,26,28,32>

D D

CLK_PEG_VGA<9> CLK_PEG_VGA#<9>

R1400 1K_0402_5%PX@

0_0402_5%

DGPU_HOLD_RST#

PLT_RST#

MC74VHC1G08DFT2G_SC70-5

1 2

+3VS_VGA +3VS

@

R1681

2

B

1

A

CLK_PEG_VGA CLK_PEG_VGA#

GPU_RST#

12

5

U6

P

Y

G

3

AC Coupling Capacitor

<DB> PCIe Gen3: Recommended value is 220 nF

PCIe Gen1 and Gen2 only: Recommended value is 100 nF

PEG_PRX_DTX_P0

AH30 AG31

AG29 AF28

AF27 AF26

AD27 AD26

AC25 AB25

Y23 Y24

AB27 AB26

Y27 Y26

W24 W23

V27 U26

U24 U23

T26 T27

T24 T23

P27 P26

P24 P23

M27 N26

Y22

AA22

PEG_PRX_DTX_N0

PEG_PRX_DTX_P1 PEG_PRX_DTX_N1

PEG_PRX_DTX_P2 PEG_PRX_DTX_N2

PEG_PRX_DTX_P3 PEG_PRX_DTX_N3

1 2

R5159 1.69K_0402_1%PX@

1 2

R717 1K_0402_1%PX@

VGA_PWRGD <56>

12

C51870.22U 6.3V K X5R 0402 PX@

12

C51880.22U 6.3V K X5R 0402 PX@

12

C51890.22U 6.3V K X5R 0402 PX@

12

C51900.22U 6.3V K X5R 0402 PX@

12

C51910.22U 6.3V K X5R 0402 PX@

12

C51920.22U 6.3V K X5R 0402 PX@

12

C51930.22U 6.3V K X5R 0402 PX@

12

C51940.22U 6.3V K X5R 0402 PX@

+1.0VS_VGA

<DB> CHANGE TO +1.0VS_VGA

PEG_PRX_C_DTX_P0 <11> PEG_PRX_C_DTX_N0 <11>

PEG_PRX_C_DTX_P1 <11> PEG_PRX_C_DTX_N1 <11>

PEG_PRX_C_DTX_P2 <11> PEG_PRX_C_DTX_N2 <11>

PEG_PRX_C_DTX_P3 <11> PEG_PRX_C_DTX_N3 <11>

No Use GPU Display Port outpud

U666F

@

AB11 AB12

AL15 AK14

AH16 AJ15

AL17 AK16

AH18 AJ17

AL19 AK18

AH20 AJ19

AL21 AK20

AH22 AJ21

AL23 AK22

AK24 AJ23

R1676 0_0402_5%R70@ R1675 0_0402_5%R70@

TXCAP_DPA3P

TXCAM_DPA3N

TX0P_DPA2P TX0M_DPA2N

TX1P_DPA1P TX1M_DPA1N

TX2P_DPA0P TX2M_DPA0N

NC_TXOUT_L3P NC_TXOUT_L3N

TMDP

TXCBP_DPB3P

TXCBM_DPB3N

TX3P_DPB2P TX3M_DPB2N

TX4P_DPB1P TX4M_DPB1N

TX5P_DPB0P TX5M_DPB0N

NC_TXOUT_U3P NC_TXOUT_U3N

216-0841018 A0 SUN PRO S3

?

VARY_BL

DIGON

1 2 1 2

+VGA_CORE

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2013/01/11 2013/12/31

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

Size

Custom

Date: Sheet

Compal Electronics, Inc.

SUN_PCIE/DP

Document Number Re v

LA-D707P

5

36 60Wednesday, May 11, 2016

v0.2

of

1

Aditya11ttt.com

1 2

R162 0_0402_5%

1 2

R164 0_0402_5%

EC_SMB_DA2<7,10,19,22,26>

A A

B B

EC_SMB_CK2<7,10,19,22,26>

VGA_AC_BATT<26>

+3VS_VGA

GPU_PROCHOT#<26,56>

VGA_SMB_DA3EC_SMB_DA2

@

VGA_SMB_CK3EC_SMB_CK2

@

ME2N7002D1KW-G 2N_SOT363-6

R1451

@

10K_0402_5%

1 2

3

Q16B

@

5

4

1 2

R1463 10K_0402_5%

1 2

@

R1464 10K_0402_5%

SB00000I700

ME2N7002D1KW-G 2N_SOT363-6

R174 0_0402_5%

REAK CURRENT CONTROL ( Topaz only )

+3VS_VGA +1.8VS_VGA

DIR

1 2

R1662 0_0402_5%R30@

1 2

R1663 0_0402_5%R30@

JTAG_TRSTB JTAG_TDI JTAG_TMS JTAG_TCK

XO_IN

XO_IN2

GPIO19_CTF

VGA_CLKREQ#

TESTEN

3

2

NC

2

1

UV4

A1

B1 C1 D2

C366 10U_0603_6.3V6M

C440 0.1U_0402_10V6K

R1455

@R30@

@

10K_0402_5%

R1449 R1450

+3VS_VGA

PX@

C341

33_0402_5%

1 2 1 2

33_0402_5%

10K_0402_5%

+3VS_VGA

GPU_VID3 GPU_VID1

GPU Side PWR IC

C C

D D

8.2P_0402_50V_NPO

R1454 10K_0402_5%

1 2

@R30@ @R30@

R1458 10K_0402_5%

XTALIN XTALOUT

2

1

GPU_VID3_GPIO15 GPU_SVD GPU_VID1_GPIO20 GPU_SVC

@R30@

@

R1457

R1456 10K_0402_5%

1 2

12

@R30@

GPU_VID3 GPU_SVD GPU_VID1

RP34

@

1 8 2 7 3 6 4 5

10K_8P4R_5%

1 2

R1447

PX@

10K_0402_5%

1 2

R1448

PX@

10K_0402_5%

1 2

R1446

PX@

10K_0402_5%

1 2

R1443

PX@

10K_0402_5%

1 2

R1439

PX@

1K_0402_5%

PX@

1 2

R349

10M_0402_5%

Y6

PX@

4

NC

OSC

1

OSC

27MHZ 10PF +-10PPM 7V27000050

SJ100009700

1

+3VS_VGA

10K_0402_5%

2

PX@

6 1

Q2416A

PX@

354

Q2416B

SB00000I700

61

Q16A

@

2

ME2N7002D1KW-G 2N_SOT363-6

1 2

R1440

@

1K_0402_5%

@R30@

C439

0.1U_0402_10V6K

@R30@

VCCB

B1 B2

GND

@R30@

12

@R30@

12

PX@

2

C350

8.2P_0402_50V_NPO

1

A2 B2 C2 D1

GPU_SVC

VCCA A1 A2 DIR

SN74LVC2T45YZPR_DSBGA8

PX@

2

1

12

R327

VGA_AC_BATT_R

GPU_GPIO6

@

C442

0.1U_0402_10V6K

2

@R30@

C441

0.1U_0402_10V6K

1

33_0402_5%

1 2

R1452

1 2

R1453

33_0402_5%

@R30@ @R30@

12

PX@

10K_0402_5%

+3VS_VGA+3VS_VGA

R328

R1444 100K_0402_5%@ R1445 4.7K_0402_5%PX@

1 2 1 2

ACIN<9,26>

+VGA_CORE

VGA_CLKREQ#<9>

+1.8VS_VGA

2

VGA_SMB_DA3

VGA_SMB_CK3

ACIN VGA_AC_BATT_R

1 2

R1459 4.7K_0402_5%R70@

1 2

R1460 4.7K_0402_5%R70@

1

T292

+VGA_CORE

VGA_AC_BATT_R

1 2

R1442 10K_0402_5%R30@

1 2

R169 0_0402_5%@

1 2

R5189 0_0402_5%R70@

1 2

R176 0_0402_5%R70@

1 2

ACIN

@

R165 0_0402_5%

1 2

R1661 0_0402_5%

1 2

R177 0_0402_5%R70@

1 2

R178 0_0402_5%R70@

11/15 :

ollow AMD check list R167 non-pop by vendor

f

R167 0_0402_5%@

1 2

C5213

@

68P_0402_50V8J

+VGA_CORE

R179 0_0402_5%R70@

R180 0_0402_5%R70@

R181 0_0402_5%R70@

Enable MLPS

L54

PX@ SM010009U00

1 2

BLM15BD121SN1D_0402

C414 10U_0603_6.3V6MPX@

C421 1U_0402_6.3V4ZPX@

C438 0.1U_0402_10V6KPX@

2

13mA

12

1

2

T70

1 2

T401 T302 T303 T304 T305 T306 T307 T308 T309 T310 T311 T312 T313 T314 T315 T316 T317

GPU_GPIO0 GPU_GPIO1

GPU_GPIO2 VGA_SMB_DA3 VGA_SMB_CK3 GPU_GPIO5 GPU_GPIO6

GPU_VID3

GPU_GPIO17 GPU_GPIO18 GPIO19_CTF GPU_VID1

VGA_CLKREQ#_R

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

1

TESTEN

T318

T221

XTALIN XTALOUT

XO_IN XO_IN2

THERM_D+

THERM_D-

GPIO28 +TSVDD

N9

1

L9

1

AE9

1 1

Y11

AE8

1

AD9

1

AC10

1 1

AD7 AC8

1

AC7

1

AB9

1 1

AB8 AB7

1

AB4

1

AB2

1

Y8

1

Y7

1

W6

V6

AC6 AC5

AA5 AA6

U1

W1

U3 Y6

AA1

R1 R3

U6

U10

T10

U8 U7 T9 T8 T7

P10

P4 P2 N6 N5 N3 Y9 N1

M4

R6

W10

M2

P8 P7 N8

AK10

AM10

N7

L6 L5 L3 L1 K4 K7

AF24

AB13

W8 W9 W7

AD10

AJ9 AL9

AC14

AB16

1

AC16

AM28

AK28

AC22

AB22

T4 T2

R5 AD17 AC17

U666B

@

DBG_DATA16 DBG_DATA15 DBG_DATA14 DBG_DATA13 DBG_DATA12 DBG_DATA11 DBG_DATA10 DBG_DATA9

DVO

DBG_DATA8 DBG_DATA7 DBG_DATA6 DBG_DATA5 DBG_DATA4 DBG_DATA3 DBG_DATA2 DBG_DATA1 DBG_DATA0

NC#W6 NC#V6

NC#AC5 NC#AC6

NC#AA5 NC#AA6

NC#U1 NC#W1 NC#U3 NC#Y6 NC#AA1

I2C

SCL SDA

GENERAL PURPOSE I/O

GPIO_0 GPIO_1 GPIO_2 SMBDATA SMBCLK GPIO_5_AC_BATT GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16 GPIO_17_THERMAL_INT GPIO_18 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21 GPIO_22_ROMCSB GPIO_29 GPIO_30 CLKREQB

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO TESTEN NC#AF24

GENERICA GENERICB GENERICC GENERICD GENERICE NC#AJ9 NC#AL9

HPD1 PX_EN

DBG_VREFG

PLL/CLOCK

XTALIN XTALOUT

XO_IN XO_IN2

SEYMOUR/FutureASIC

DPLUS

THERMAL

DMINUS

GPIO28_FDO TSVDD TSVSS

216-0841018 A0 SUN PRO S3

3

U?

DPA

DPB

DPC

AVSSN#AK26

AVSSN#AJ25

AVSSN#AG25

DAC1

FutureASIC/SEYMOUR/PARK

RSVD#AK12

GENLK_CLK

GENLK_VSYNC

SWAPLOCKA SWAPLOCKB

DDC/AUX

DDCVGACLK

DDCVGADATA

?

3

NC#AF2 NC#AF4

NC#AG3 NC#AG5

NC#AH3 NC#AH1

NC#AK3 NC#AK1

NC#AK5 NC#AM3

NC#AK6 NC#AM5

NC#AJ7

NC#AH6

NC#AK8

NC#AL7

NC#V4 NC#U5

NC#W3

NC#V2

NC#Y4

NC#W5

NC#AA3

NC#Y2

NC#J8

HSYNC VSYNC

RSET

AVDD

AVSSQ

VDD1DI VSS1DI

CEC_1

RSVD#AL11 RSVD#AJ11

DDC1CLK

DDC1DATA

AUX1P

AUX1N

DDC2CLK

DDC2DATA

AUX2P

AUX2N

NC#AD20 NC#AC20

NC#AE16 NC#AD16

4

Resistor Divider Lookup Lable

AF2 AF4

AG3 AG5

AH3 AH1

AK3 AK1

AK5 AM3

AK6 AM5

AJ7 AH6

AK8 AL7

V4 U5

W3 V2

Y4 W5

PLL_ANALOG_OUT

AA3 Y2

J8

+1.8VS_VGA +3VS_VGA

AM26

R

AK26

AL25

G

AJ25

AH24

B

AG25

AH26

1 2

AJ27

R5191

4.7K_0402_5%

AD22

PX@

AG24 AE22

AE23 AD23

AM12

SVI2_SVD

AK12

SVI2_SVT

AL11

SVI2_SVC

AJ11

AL13 AJ13

AG13 AH12

PS_0

AC19

PS_0

PS_1

PS_2

PS_3

TS_A

PS_1

AD19

PS_2

AE17

PS_3

AE20

AE19

AE6 AE5

AD2 AD4

AC11 AC13

1 2

AD13

R1667 0_0402_5%R70@

AD11

1 2

R1668 0_0402_5%R70@

FB_GND

AD20

FB_VDDC

AC20

AE16 AD16

VGA_VSSSENSE

AC1

VGA_VCCSENSE

AC3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0402 1% resistors are equired

R1469

+VGA_VDDIO<56>

1 2

R1673

R70@

0_0402_5%

PX@

R1461

10K_0402_5%

GPU_SVD

GPU_SVC

R1467

10K_0402_5%

1 2

R1664 0_0402_5%R70@

1 2

R1665 0_0402_5%R70@

1 2

R1666 0_0402_5%R70@

+VGA_CORE

1 2

R1669 0_0402_5%R70@

1 2

R1670 0_0402_5%R70@

R1672 10_0402_5%PX@

R1677 10_0402_5%PX@

R_pd (ohm)R_pu (ohm)

Bitd [3:1]

NC

8.45k

4.53k

6.98k

4.53k

3.24k

3.4k

4.75k

2k

4.99k

5.62k

10k

NC

000

<DB> use Gen3

001

010

011

100

101

110

111

Capacitor Divider Lookup Lable

Cap (nF) Bitd [5:4]

680nF

00

82nF

01

10nF 1 0

NC

16.2K_0402_1%

GPU_SVD GPU_SVT GPU_SVC

11

R1674 0_0402_5%

@

R1462 10K_0402_5%

1 2

R1468

PX@

10K_0402_5%

1 2

R30@

GPU_SVD <56> GPU_SVT <56> GPU_SVC <56>

0.082U_0402_16V6K

1 2

@

1 2

@

1 2

(default)

Memory Type Conf i gura t i on SizeMemory ID

SA00009HF00

000

SA00008DN00

001

SA00009I400

010

SA00009IB00

011

SA000076P80

100

101

110

111

VGA_VSSSENSE <56> VGA_VCCSENSE <56>

1 2

+3VS_VGA

2013/01/11 2013/12/31

CV271 0.1U_0402_16V4Z

+VGA_CORE

@PX@

RV133 2.2K_0402_5%

THERM_D+ THERM_D-

Compal Secret Data

4

@PX@

12

THERM_D-

12

CV272

1 2

2200P_0402_50V7K

@PX@

Deciphered Date

+3VS_VGA

PX@

C5203

C=NC

+1.8VS_VGA

R=NC

1

2

+1.8VS_VGA

12

PX@

R5165

8.45K_0402_1%

PX@

R5166 2K_0402_1%

<DB> use Gen3

PX@

R5167

8.45K_0402_1%

PX@

R5168 2K_0402_1%

PX@

R5164

4.75K_0402_1%

X76@

R5174

8.45K_0402_1%

X76@

R5169

4.75K_0402_1%

PS_0[3:1]=001

PS_0[5:4]=11

PS_0

PS_1[3:1]=000

PS_1[5:4]=11

PS_1

PS_2[3:1]=000

PS_2[5:4]=11

PS_2

PS_3[3:1]=000

PS_3[5:4]=11

PS_3

Micron MT41J256M16LY-091G:N

Hynix H5TC4G63CFR-N0C

Micron MT41K512M16HA-107G:A

Hynix H5TC8G63CMR-11C

Samsung K4W4G1646E-BC1A

+3VS_VGA+3VS

@PX@

RP13

2.2K_0804_8P4R_5%

@PX@

UV13

1

SCL

VDD

2

D+

SDA

3

ALERT#

D-

T_CRIT#4GND

NCT7718W_MSOP8

SA000067P00

Address:1001100xb (x is R/W bit)

5

Strap Name :

PS_0[1] ROM_CONFIG[0]

PS_0[2] ROM_CONFIG[1]

PS_0[3] ROM_CONFIG[2]

PS_0[4] N/A

PS_0[5] AUD_PORT_CONN_PINSTRAP[0]

Strap Name :

PS_1[1] STRAP_BIF_GEN3_EN_A

PS_1[2] TRAP_BIF_CLK_PM_EN

PS_1[3] N/A

PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING

PS_1[5] STRAP_TX_DEEMPH_EN

Strap Name :

PS_2[1] N/A

PS_2[2] N/A

PS_2[3] STRAP_BIOS_ROM_EN

PS_2[4] STRAP_BIF_VGA_DIS

PS_2[5] N/A

Strap Name :

PS_3[1] BOARD_CONFIG[0] (Memory ID)

PS_3[2] BOARD_CONFIG[1] (Memory ID)

PS_3[3] BOARD_CONFIG[2] (Memory ID)

PS_3[4] AUD_PORT_CONN_PINSTRAP[1]

PS_3[5] AUD_PORT_CONN_PINSTRAP[2]

R5174 R5169

NC

2GB

8.45K

4GB

4.53K

4GB

6.98K 4.99K

4.53K 4.99K

2GB

3.24K 5.62K

3.4K

4.75K

+3VS_VGA

THS_SCL

18

THS_SDA

27

EC_SMB_DA3

36

EC_SMB_CK3

45

THS_SCL

8

THS_SDATHERM_D+

7

6

5

Title

Size

Custom

Date: Sheet

ME2N7002D1KW-G 2N_SOT363-6

2

@PX@

EC_SMB_CK3

61

Q2415A

5

@PX@

SB00000I700

1 2

R168 0_0402_5%

Compal Electronics, Inc.

SUN_MSIC

Document Number Re v

EC_SMB_DA3

3

4

Q2415B ME2N7002D1KW-G 2N_SOT363-6

SB00000I700

@PX@

2.2K_0402_5%

RV134

GPU_GPIO17

@

LA-D707P

5

4.75K

10K

NC

12

2K

X76 P/N

X7667032L04

X7667032L03

X7662732L03

EC_SMB_CK3 <26>

EC_SMB_DA3 <26>

+3VS_VGA

of

37 60Wednesday, May 11, 2016

v0.2

1

Aditya11ttt.com

2

3

4

5

+1.5VS to +1.5VS_VGA (2.096A)

+1.5VS_VGA

1 2

370mA (HDMI)

88mA (Display Port)

1

+DP_VDDR

1

C4461U_0402_6.3V4Z

C4470.1U_0402_10V6K

2

@

280mA

+DP_VDDC

1

C4510.1U_0402_10V6K

C4501U_0402_6.3V4Z

2

@

Delete +1.5VS to +1.5VS_VGA power switch

PX@

R4102

60mA

@PX@

PX@

818mA

10_0603_5%

1 2

3

PXS_PWREN#

5

QV4101B

PX@

4

ME2N7002D1KW-G 2N_SOT363-6

SB00000I700

JG3

JP@

2

112

0.1U_0402_16V7K

JP@

1

2

0.1U_0402_25V6

1

2

JUMP_43X39

JG18

112

JUMP_43X39

0.1U_0402_25V6

C4124

CC164

1

2

PX@

@ESD@

C4125

PX@

R346 10_0603_5%

PX@

1 2

13

D

PX@

S

ME2N7002D1W-G 1N_SC70-3

2

G

Q91

SB00000Z600

<DB> CHANGE TO +1.0VS_VGA

PXS_PWREN#

A A

B B

C C

+3VS to +3VS_VGA (25mA)

+1.8V_PRIM to +1.8VS_VGA (311mA)

+3VS +3VS_VGA

0.1U_0402_16V7K C4111

1

DGPU_PWR_EN

+5VALW

2

PX@

DGPU_PWR_EN

+1.8V_PRIM +1.8VS_VGA

0.1U_0402_16V7K C4123

1

2

PX@

Main: SA00004MM00, TI, TPS22966 2nd: SA00006FD00, A-Power, APE8990GN3B 3rd: AOS, AOZ1331 (engineering sample available on 2013/Jan/18)

PX@

U4103

1

VOUT1

VIN1

2

VOUT1

VIN1

3

ON1

4

5

6 7

GND

VBIAS

ON2

VIN2

VOUT2

VIN2

VOUT2

GPAD

TPS22966DPUR_SON14_2X3

SA00007PM00

<Diner SI> change to NC & 470p

14 13

12

1 2

C4112

CT1

470P_0402_50V7K

11

10

1 2

C4126

CT2

470P_0402_50V7K

9 8

15

+1.8VS_VGA

R319 0_0603_5%

+1.0VS_VGA

R320 0_0603_5%

No Use GPU Display Port outpud

U666G

@

U?

DP POWER

AG15

DP_VDDR#AG15

AG16

DP_VDDR#AG16

AF16

DP_VDDR#AF16

AG17

DP_VDDR#AG17

AG18

DP_VDDR#AG18

AG19

DP_VDDR#AG19

AF14

DP_VDDR#AF14

AG20

DP_VDDC#AG20

AG21

DP_VDDC#AG21

AF22

DP_VDDC#AF22

AG22

DP_VDDC#AG22

AD14

DP_VDDC#AD14

AG14

DP_VSSR

AH14

DP_VSSR

AM14

DP_VSSR

AM16

DP_VSSR

AM18

DP_VSSR

AF23

DP_VSSR

AG23

DP_VSSR

AM20

DP_VSSR

AM22

DP_VSSR

AM24

DP_VSSR

AF19

DP_VSSR

AF20

DP_VSSR

AE14

DP_VSSR

AF17

DPAB_CALR

216-0841018 A0 SUN PRO S3

NC/DP POWER

?

NC#AE11 NC#AF11 NC#AE13 NC#AF13

NC#AG8

NC#AG10

NC#AF6 NC#AF7 NC#AF8 NC#AF9

NC#AE1 NC#AE3 NC#AG1 NC#AG6 NC#AH5

NC#AF10

NC#AG9 NC#AH8 NC#AM6 NC#AM8 NC#AG7

NC#AG11

NC#AE10

AE11 AF11 AE13 AF13 AG8 AG10

AF6 AF7 AF8 AF9

AE1 AE3 AG1 AG6 AH5 AF10 AG9 AH8 AM6 AM8 AG7 AG11

AE10

U666E

@

AA27

GND

AB24

GND

AB32

GND

AC24

GND

AC26

GND

AC27

GND

AD25

GND

AD32

GND

AE27

GND

AF32

GND

AG27

GND

AH32

GND

K28

GND

K32

GND

L27

GND

M32

GND

N25

GND

N27

GND

P25

GND

P32

GND

R27

GND

T25

GND

T32

GND

U25

GND

U27

GND

V32

GND

W25

GND

W26

GND

W27

GND

Y25

GND

Y32

GND

M6

GND

N13

GND

N16

GND

N18

GND

N21

GND

P6

GND

P9

GND

R12

GND

R15

GND

R17

GND

R20

GND

T13

GND

T16

GND

T18

GND

T21

GND

T6

GND

U15

GND

U17

GND

U20

GND

U9

GND

V13

GND

V16

GND

V18

GND

Y10

GND

Y15

GND

Y17

GND

Y20

GND

R11

GND

T11

GND

AA11

GND

M12

GND

N11

GND

V11

GND

216-0841018 A0 SUN PRO S3

U?

A3

GND

A30

GND

AA13

GND

AA16

GND

AB10

GND

AB15

GND

AB6

GND

AC9

GND

AD6

GND

AD8

GND

AE7

GND

AG12

GND

AH10

GND

AH28

GND

B10

GND

B12

GND

B14

GND

B16

GND

B18

GND

B20

GND

B22

GND

B24

GND

B26

GND

B6

GND

B8

GND

C1

GND

C32

GND

E28

GND

F10

GND

F12

GND

F14

GND

F16

GND

F18

GND

F2

GND

F20

GND

F22

GND

F24

GND

F26

GND

F6

GND

?

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

VSS_MECH VSS_MECH VSS_MECH

F8 G10 G27 G31 G8 H14 H17 H2 H20 H6 J27 J31 K11 K2 K22 K6

A32 AM1 AM32

+1.0V_PRIM to +1.0VS_VGA (4.016A)

+1.0V_PRIM

PX@

U4102 AO4354_SO8

8 7

0.1U_0402_16V7K

6 5

C4113

1

SB00000ZN00

2

PX@

1 2

+19.5VB

D D

1

PX@

R4109 200K_0402_5%

PXS_PWREN#

2

0.95VSG_GATE

12

61

@

1.5M_0402_5%

PX@

Q4102A ME2N7002D1KW-G 2N_SOT363-6

SB00000I700

R4104

4

+1.0VS_VGA

<DB> CHANGE TO +1.0VS_VGA

1 2 3

1

C4122

PX@

0.01U_0402_25V7K

2

1U_0402_6.3V4Z

10U_0603_6.3V6M

C4114

1

2

PX@

2

PX@

C4115

1 2 3

4

PX@

R4107 10_0603_5%

PXS_PWREN#

5

PX@

Q4102B ME2N7002D1KW-G 2N_SOT363-6

SB00000I700

PX@

R4113 100K_0402_5%

PX@

Q4105B

SB00000I700

4

1 2 3

5

4

ME2N7002D1KW-G 2N_SOT363-6

PXS_PWREN#

DGPU_PWR_EN<10,26,55,56>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2013/01/11 2013/12/31

DGPU_PWR_EN PXS_PWREN#

12

R4115

PX@

100K_0402_5%

Compal Secret Data

Deciphered Date

+VGA_CORE+5VALW

PX@

R4114 470_0603_5%

1 2 61

2

PX@

Q4105A

SB00000I700

ME2N7002D1KW-G 2N_SOT363-6

Compal Electronics, Inc.

Title

Size

Custom

Date: Sheet

Compal Electronics, Inc.

SUN_Power/GND

Document Number Re v

LA-D707P

5

v0.2

of

38 60Wednesday, May 11, 2016

1

Aditya11ttt.com

2

3

4

5

C4220.1U_0402_10V6K

C4330.1U_0402_10V6K

1

2

PX@

1

2

PX@

+3VS_VGA

+1.8VS_VGA

+1.5VS_VGA

2

C3719

1

PX@

0.01U_0402_16V7K

L24

PX@

1 2

BLM15BD121SN1D_0402

SM010009U00

L48

PX@

1 2

BLM15BD121SN1D_0402

SM010009U00

C36510U_0603_6.3V6M

C3720

PX@

1

C36710U_0603_6.3V6M

2

PX@

2

C3721

1

PX@

0.01U_0402_16V7K

1

C40810U_0603_6.3V6M

2

PX@

C3702.2U_0402_6.3V5M

C37510U_0603_6.3V6M

2

PX@

2

C3890.1U_0402_10V6K

C3722

C3723

1

PX@

0.01U_0402_16V7K

1

C4281U_0402_6.3V4Z

C4290.1U_0402_10V6K

C4101U_0402_6.3V4Z

2

@

PX@

1

C4340.1U_0402_10V6K

C4091U_0402_6.3V4Z

+1.0VS_VGA

2

BLM15BD121SN1D_0402

PX@

1

C3732.2U_0402_6.3V5M

C3712.2U_0402_6.3V5M

C3722.2U_0402_6.3V5M

2

PX@

1

C3810.1U_0402_10V6K

C3900.1U_0402_10V6K

C3910.1U_0402_10V6K

2

PX@

1

C41710U_0603_6.3V6M

2

PX@

<DB> CHANGE TO +1.0VS_VGA

L53

PX@

1 2

SM010009U00

1

C3742.2U_0402_6.3V5M

U666D

2

1A

PX@

1

C3920.1U_0402_10V6K

2

PX@

13mA

+VDD_CT

25mA

+VDDR3

90mA

+MPLL_PVDD

75mA

+SPLL_PVDD

100mA

+SPLL_VDDC

1

C4350.1U_0402_10V6K

C4121U_0402_6.3V4Z

C41110U_0603_6.3V6M

2

PX@

@

MEM I/O

H13

VDDR1

H16

VDDR1

H19

VDDR1

J10

VDDR1

J23

VDDR1

J24

VDDR1

J9

VDDR1

K10

VDDR1

K23

VDDR1

K24

VDDR1

K9

VDDR1

L11

VDDR1

L12

VDDR1

L13

VDDR1

L20

VDDR1

L21

VDDR1

L22

VDDR1

LEVEL TRANSLATION

AA20

VDD_CT

AA21

VDD_CT

AB20

VDD_CT

AB21

VDD_CT

I/O

AA17

VDDR3

AA18

VDDR3

AB17

VDDR3

AB18

VDDR3

V12

VDDR4

Y12

VDDR4

U12

VDDR4

PLL

L8

MPLL_PVDD

H7

SPLL_PVDD

H8

SPLL_VDDC

J7

SPLL_PVSS

216-0841018 A0 SUN PRO S3

U?

PCIE

PCIE_PVDD

NC#AB23 NC#AC23 NC#AD24 NC#AE24 NC#AE25 NC#AE26 NC#AF25 NC#AG26

PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC

CORE

POWER

BIF_VDDC BIF_VDDC

ISOLATED

CORE I/O

VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI

?

VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC

+PCIE_PVDD:

50mA (PCIE2.0) 80mA (PCIE3.0)

AM30

AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26

L23 L24 L25

+PCIE_VDDC:

L26 M22

1.88A (PCIE2.0)

N22

2.5A (PCIE3.0)

N23 N24 R22 T22 U22 V22

AA15 N15 N17 R13 R16 R18 Y21 T12 T15 T17 T20 U13 U16 U18 V21 V15 V17 V20 Y13 Y16 Y18 AA12 M11 N12 U11

1.4A

R21

+BIF_VDDC

U21

+VGA_CORE

M13 M15 M16 M17 M18 M20 M21 N20

+1.8VS_VGA

1

C38010U_0603_6.3V6M

2

PX@

1

C3871U_0402_6.3V4Z

C3940.1U_0402_10V6K

2

PX@

<DB> CHANGE TO +1.0VS_VGA

+1.0VS_VGA

C38410U_0603_6.3V6M

1

2

PX@

1

C38610U_0603_6.3V6M

2

@

+VGA_CORE

1

C3991U_0402_6.3V4Z

C3981U_0402_6.3V4Z

2

PX@

1

C4031U_0402_6.3V4Z

C3831U_0402_6.3V4Z

2

PX@

1

C3881U_0402_6.3V4Z

C3724

2

@

PX@

1U_0402_6.3V6K

21A (VDDC + VDDCI (Merged) - PRO S3 (DDR3))

<DB> CHANGE TO +1.0VS_VGA

+1.0VS_VGA

R398

1 2

0_0805_5%

1

C41310U_0603_6.3V6M

2

@

1

C4151U_0402_6.3V4Z

C4161U_0402_6.3V4Z

2

@

C3725

PX@

1

2

1U_0402_6.3V6K

A A

B B

+VGA_CORE

VDDC

VDDCI

+1.0VS_VGA

PCIE_VDDC

BIF_VDDC

SPLL_VDDC

+1.5VS_VGA

VDDR1

TBD

3.5A

2.5A

1.4A

100mA

1.5A

5 (1@) 10 (2@)

1 3 0

10uF 1uF

2 (1@) 5 (1@)

10uF 1uF

3 5 5

10uF+1.8VS_VGA

PCIE_PVDD

MPLL_PVDD

SPLL_PVDD

VDDR4

VDD_CT

100mA

130mA

75mA

(300mA)

13mA

1 1 1

+TSVDD 13mA

C C

+DP_VDDR

+DP_VDDC

+3VS_VGA

VDDR3

25mA

0

1uF10uF

00 0

11 1

1uF

1 11

00 0

1 11

00 0

0 00

1uF10uF

2 (1@)

0.1uF

0

0.1uF

0

0.1uF

111

0.1uF

1

+1.8VS_VGA

1 2

BLM15BD121SN1D_0402

SM010009U00

+1.8VS_VGA

1 2

0 +-5% 0603

SD013000080

L56

PX@

1

C4051U_0402_6.3V4Z

C40410U_0603_6.3V6M

2

PX@

L47

PX@

1

C40610U_0603_6.3V6M

C4071U_0402_6.3V4Z

2

PX@

D D

Security Classification

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2013/01/11 2013/12/31

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

Size

Custom

Date: Sheet

Compal Electronics, Inc.

SUN_Power

Document Number Re v

LA-D707P

5

39 60Wednesday, May 11, 2016

v0.2

of

1

Aditya11ttt.com

2

3

4

5

PX@

C469

M_DA[63..0]

M_MA[15..0]

M_DQM[7..0]

M_DQS[7..0]

M_DQS#[7..0]

40.2_0402_1%

100_0402_1%

PX@

R455 10_0402_1%

1

2

+1.5VS_VGA+1.5VS_VGA

12

PX@

R365

12

PX@

R457

12

PX@

R5161

5.1K_0402_1%

+MVREFSA

1

PX@

C514 1U_0402_6.3V4Z

2

DRAM_RST

12

R5162 120_0402_1%PX@

1 2

R460 51.1_0402_1%@

1 2

R373 51.1_0402_1%@

Route 50ohms single-ended/100ohm dif f and keep short debug only, for clock observat i on,i f not need, DNI.

C542 0.1U_0402_16V4Z@ C541

1 2

1 2 1 2

@

M_DA0 M_DA1 M_DA2 M_DA3 M_DA4 M_DA5 M_DA6 M_DA7 M_DA8 M_DA9 M_DA10 M_DA11 M_DA12 M_DA13 M_DA14 M_DA15 M_DA16 M_DA17 M_DA18 M_DA19 M_DA20 M_DA21 M_DA22 M_DA23 M_DA24 M_DA25 M_DA26 M_DA27 M_DA28 M_DA29 M_DA30 M_DA31 M_DA32 M_DA33 M_DA34 M_DA35 M_DA36 M_DA37 M_DA38 M_DA39 M_DA40 M_DA41 M_DA42 M_DA43 M_DA44 M_DA45 M_DA46 M_DA47 M_DA48 M_DA49 M_DA50 M_DA51 M_DA52 M_DA53 M_DA54 M_DA55 M_DA56 M_DA57 M_DA58 M_DA59 M_DA60 M_DA61 M_DA62 M_DA63

+MVREFDA +MVREFSA

DRAM_RST

0.1U_0402_16V4Z

@

U666C

K27

DQA0_0

J29

DQA0_1

H30

DQA0_2

H32

DQA0_3

G29

DQA0_4

F28

DQA0_5

F32

DQA0_6

F30

DQA0_7

C30

DQA0_8

F27

DQA0_9

A28

DQA0_10

C28

DQA0_11

E27

DQA0_12

G26

DQA0_13

D26

DQA0_14

F25

DQA0_15

A25

DQA0_16

C25

DQA0_17

E25

DQA0_18

D24

DQA0_19

E23

DQA0_20

F23

DQA0_21

D22

DQA0_22

F21

DQA0_23

E21

DQA0_24

D20

DQA0_25

F19

DQA0_26

A19

DQA0_27

D18

DQA0_28

F17

DQA0_29

A17

DQA0_30

C17

DQA0_31

E17

DQA1_0

D16

DQA1_1

F15

DQA1_2

A15

DQA1_3

D14

DQA1_4

F13

DQA1_5

A13

DQA1_6

C13

DQA1_7

E11

DQA1_8

A11

DQA1_9

C11

DQA1_10

F11

DQA1_11

A9

DQA1_12

C9

DQA1_13

F9

DQA1_14

D8

DQA1_15

E7

DQA1_16

A7

DQA1_17

C7

DQA1_18

F7

DQA1_19

A5

DQA1_20

E5

DQA1_21

C3

DQA1_22

E1

DQA1_23

G7

DQA1_24

G6

DQA1_25

G1

DQA1_26

G3

DQA1_27

J6

DQA1_28

J1

DQA1_29

J3

DQA1_30

J5

DQA1_31

K26

MVREFDA

J26

MVREFSA

J25

NC#J25

K25

MEM_CALRP0

L10

DRAM_RST

K8

CLKTESTA

L7

CLKTESTB

216-0841018 A0 SUN PRO S3

U?

GDDR5/DDR3GDDR5/DDR3

MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6

MAA0_7/MAA_7 MAA0_8/MAA_13 MAA0_9/MAA_15

MAA1_0/MAA_8

MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12

MAA1_5/MAA_BA2 MAA1_6/MAA_BA0 MAA1_7/MAA_BA1

MAA1_8/MAA_14

MAA1_9/RSVD

WCKA0_0/DQMA0_0

WCKA0B_0/DQMA0_1

WCKA0_1/DQMA0_2

WCKA0B_1/DQMA0_3

WCKA1_0/DQMA1_0

MEMORY INTERFACE

WCKA1B_0/DQMA1_1

WCKA1_1/DQMA1_2

WCKA1B_1/DQMA1_3

EDCA0_0/QSA0_0 EDCA0_1/QSA0_1 EDCA0_2/QSA0_2 EDCA0_3/QSA0_3 EDCA1_0/QSA1_0 EDCA1_1/QSA1_1 EDCA1_2/QSA1_2 EDCA1_3/QSA1_3

DDBIA0_0/QSA0_0B DDBIA0_1/QSA0_1B DDBIA0_2/QSA0_2B DDBIA0_3/QSA0_3B DDBIA1_0/QSA1_0B DDBIA1_1/QSA1_1B DDBIA1_2/QSA1_2B DDBIA1_3/QSA1_3B

ADBIA0/ODTA0

ADBIA1/ODTA1

?

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B RASA1B

CASA0B CASA1B

CSA0B_0 CSA0B_1

CSA1B_0 CSA1B_1

CKEA0 CKEA1

WEA0B WEA1B

M_MA0

K17

M_MA1

J20

M_MA2

H23

M_MA3

G23

M_MA4

G24

M_MA5

H24

M_MA6

J19

M_MA7

K19

M_MA13

G20

M_MA15

L17

M_MA8

J14

M_MA9

K14

M_MA10

J11

M_MA11

J13

M_MA12

H11

M_BA2

G11

M_BA0

J16

M_BA1

L15

M_MA14

G14 L16

M_DQM0

E32

M_DQM1

E30

M_DQM2

A21

M_DQM3

C21

M_DQM4

E13

M_DQM5

D12

M_DQM6

E3

M_DQM7

F4

M_DQS0

H28

M_DQS1

C27

M_DQS2

A23

M_DQS3

E19

M_DQS4

E15

M_DQS5

D10

M_DQS6

D6

M_DQS7

G5

M_DQS#0

H27

M_DQS#1

A27

M_DQS#2

C23

M_DQS#3

C19

M_DQS#4

C15

M_DQS#5

E9

M_DQS#6

C5

M_DQS#7

H4

VRAM_ODT0

L18

VRAM_ODT1

K16

M_CLK0

H26

M_CLK#0

H25

M_CLK1

G9

M_CLK#1

H9

M_RAS#0

G22

M_RAS#1

G17

M_CAS#0

G19

M_CAS#1

G16

M_CS#0

H22 J22

M_CS#1

G13 K13

M_CKE0

K20

M_CKE1

J17

M_WE#0

G25

M_WE#1

H10

M_BA2 <41,42> M_BA0 <41,42> M_BA1 <41,42>

VRAM_ODT0 <41> VRAM_ODT1 <42>

M_CLK0 <41> M_CLK#0 <41>

M_CLK1 <42> M_CLK#1 <42>

M_RAS#0 <41> M_RAS#1 <42>

M_CAS#0 <41> M_CAS#1 <42>

M_CS#0 <41> M_CS#0_1 <41>

M_CS#1 <42> M_CS#1_1 <42>

M_CKE0 <41> M_CKE1 <42>

M_WE#0 <41> M_WE#1 <42>

For 512 VRAM 2Rank Colay

M_DA[63..0]<41,42>

M_MA[15..0]<41,42>

M_DQM[7..0]<41,42>

A A

40.2_0402_1%

100_0402_1%

B B

DRAM_RST#<41,42>

C C

M_DQS[7..0]<41,42>

M_DQS#[7..0]<41,42>

12

PX@

R363

+MVREFDA

12

1

PX@

R364

C467 1U_0402_6.3V4Z

2

PX@

R5160

49.9_0402_1%

1 2

120P_0402_50V8J

Place close to GPU (within 25mm) and place componment close to each other

D D

Security Classification

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2013/01/11 2013/12/31

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

Size

Custom

Date: Sheet

Compal Electronics, Inc.

SUN_MEM

Document Number Re v

LA-D707P

5

40 60Wednesday, May 11, 2016

v0.2

of

1

Aditya11ttt.com

2

3

4

5

Memory Partition A - Lower 32 bits

M_DA[63..0]<40,42>

M_MA[15..0]<40,42>

M_DQM[7..0]<40,42>

M_DQS[7..0]<40,42>

M_DQS#[7..0]<40,42>

A A

B B

C C

R5171

40.2_0402_1%

PX@

12

1

PX@

C506

0.01U_0402_25V7K

2

M_CLK0 M_CLK#0

12

R5170

40.2_0402_1%

PX@

M_DA[63..0]

M_MA[15..0]

M_DQM[7..0]

M_DQS[7..0]

M_DQS#[7..0]

PX@

R454

240_0402_1%

4.99K_0402_1%

12

+1.5VS_VGA

12

PX@

R452

+FBA_VREF0 +FBA_VREF1

PX@

R453

12

1

PX@

C472

0.1U_0402_10V6K

2

M_BA0<40,42> M_BA1<40,42> M_BA2<40,42>

M_CLK0<40> M_CLK#0<40> M_CKE0<40>

VRAM_ODT0<40> M_CS#0<40> M_RAS#0<40> M_CAS#0<40> M_WE#0<40>

DRAM_RST#<40,42>

M_CS#0_1<40>

R465 240_0402_1%PX@

1

C49110U_0603_6.3V6M

2

PX@

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15

M_BA0 M_BA1 M_BA2

M_CLK0 M_CLK#0 M_CKE0

VRAM_ODT0 M_CS#0 M_RAS#0 M_CAS#0 M_WE#0

M_DQS2 M_DQS0

M_DQM2 M_DQM0

M_DQS#2 M_DQS#0

VRAM_ODT0

M_CKE0

12

1

C5111U_0402_6.3V4Z

C5121U_0402_6.3V4Z

2

PX@

1

C5101U_0402_6.3V4Z

C5191U_0402_6.3V4Z

2

PX@

U1406

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

SDRAM DDR3

H5TC2G63FFR-11C_FBGA96

X76@

1

C5321U_0402_6.3V4Z

C5211U_0402_6.3V4Z

2

PX@

M_DA17

E3

DQL0

M_DA23

F7

DQL1

M_DA21

F2

DQL2

M_DA22

F8

DQL3

M_DA18

H3

DQL4

M_DA19

H8

DQL5

M_DA16

G2

DQL6

M_DA20

H7

DQL7

M_DA5

D7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

1

C4800.1U_0402_10V6K

C5201U_0402_6.3V4Z

2

@

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

1

2

PX@

M_DA3

C3

M_DA4

C8

M_DA1

C2

M_DA6

A7

M_DA0

A2

M_DA7

B8

M_DA2

A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

U1406 side

1

C4810.1U_0402_10V6K

C4820.1U_0402_10V6K

2

PX@

1

C4850.1U_0402_10V6K

2

PX@

+1.5VS_VGA

1

C4830.1U_0402_10V6K

2

PX@

+1.5VS_VGA

1

C5310.1U_0402_10V6K

2

PX@

240_0402_1%

1

C4860.1U_0402_10V6K

2

@

4.99K_0402_1%

12

PX@

R456

PX@

R463

PX@

R464

+1.5VS_VGA

12

R466 240_0402_1%PX@

1

PX@

C540

0.1U_0402_10V6K

2

1

C49010U_0603_6.3V6M

2

PX@

12

1

C4961U_0402_6.3V4Z

2

PX@

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15

M_BA0 M_BA1 M_BA2

M_CLK0 M_CLK#0 M_CKE0

VRAM_ODT0 M_CS#0 M_RAS#0 M_CAS#0 M_WE#0

M_DQS3 M_DQS1

M_DQM3 M_DQM1

M_DQS#3 M_DQS#1

DRAM_RST#

VRAM_ODT0 M_CS#0_1 M_CKE0

1

C4981U_0402_6.3V4Z

C4971U_0402_6.3V4Z

2

PX@

M8 H1

N3

P7 P3

N2

P8

P2 R8 R2

T8 R3

L7 R7 N7

T3

T7 M7

M2 N8 M3

J7

K7

K9

K1

L2

J3

K3

L3

F3 C7

E7 D3

G3

B7

T2

L8

J1

L1

J9

L9

1

C4991U_0402_6.3V4Z

2

PX@

U1407

96-BALL SDRAM DDR3

1

C5331U_0402_6.3V4Z

C5161U_0402_6.3V4Z

2

PX@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

1

C4740.1U_0402_10V6K

2

@

PX@

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS/CS0 RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET

ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

H5TC2G63FFR-11C_FBGA96

X76@

1

C5181U_0402_6.3V4Z

2

PX@

M_DA30

E3

M_DA27

F7

M_DA31

F2

M_DA24

F8

M_DA29

H3

M_DA26

H8

M_DA28

G2

M_DA25

H7

M_DA8

D7

M_DA14

C3

M_DA9

C8

M_DA12

C2

M_DA10

A7

M_DA15

A2

M_DA11

B8

M_DA13

A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

U1407 side

1

C4750.1U_0402_10V6K

C4760.1U_0402_10V6K

2

PX@

+1.5VS_VGA

+1.5VS_VGA+1.5VS_VGA

1

C4770.1U_0402_10V6K

2

PX@

+1.5VS_VGA

1

C5340.1U_0402_10V6K

C4780.1U_0402_10V6K

C4790.1U_0402_10V6K

2

@

PX@

D D

Security Classification

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2013/01/11 2013/12/31

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

Size

Custom

Date: Sheet

Compal Electronics, Inc.

SUN_VRAM A Lower

Document Number Re v

LA-D707P

5

41 60Wednesday, May 11, 2016

v0.2

of

1

Aditya11ttt.com

2

Memory Partition A - Upper 32 bits

3

4

5

4.99K_0402_1%

12

+1.5VS_VGA

PX@

R461

PX@

R462

12

1

PX@

C539

0.1U_0402_10V6K

2

R445 240_0402_1%PX@

12

+FBA_VREF3

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15

M_BA0 M_BA1 M_BA2

M_CLK1 M_CLK#1 M_CKE1

VRAM_ODT1 M_CS#1 M_RAS#1 M_CAS#1 M_WE#1

M_DQS6 M_DQS7

M_DQM6 M_DQM7

M_DQS#6 M_DQS#7

DRAM_RST#

VRAM_ODT1 M_CS#1_1 M_CKE1

U1409

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

SDRAM DDR3

H5TC2G63FFR-11C_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

M_DA49

E3

M_DA53

F7

M_DA51

F2

M_DA54

F8

M_DA50

H3

M_DA55

H8

M_DA48

G2

M_DA52

H7

M_DA60

D7

M_DA59

C3

M_DA63

C8

M_DA56

C2

M_DA62

A7

M_DA57

A2

M_DA61

B8

M_DA58

A3

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

+1.5VS_VGA

12

PX@

R458

A A

B B

40.2_0402_1%

C C

R5173

PX@

M_DA[63..0]<40,41>

M_MA[15..0]<40,41>

M_DQM[7..0]<40,41>

M_DQS[7..0]<40,41>

M_DQS#[7..0]<40,41>

M_CLK1 M_CLK#1

12

R5172

40.2_0402_1%

PX@

1

PX@

C507

0.01U_0402_25V7K

2

M_DA[63..0]

M_MA[15..0]

M_DQM[7..0]

M_DQS[7..0]

M_DQS#[7..0]

4.99K_0402_1%

PX@

R410

240_0402_1%

+FBA_VREF2

12

1

PX@

R459

C473

0.1U_0402_10V6K

2

M_BA0<40,41> M_BA1<40,41> M_BA2<40,41>

M_CLK1<40> M_CLK#1<40> M_CKE1<40>

VRAM_ODT1<40> M_CS#1<40> M_RAS#1<40> M_CAS#1<40> M_WE#1<40>

DRAM_RST#<40,41>

12

M_CS#1_1<40>

R411 240_0402_1%PX@

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15

M_BA0 M_BA1 M_BA2

M_CLK1 M_CLK#1 M_CKE1

VRAM_ODT1 M_CS#1 M_RAS#1 M_CAS#1 M_WE#1

M_DQS4 M_DQS5

M_DQM4 M_DQM5

M_DQS#4 M_DQS#5

DRAM_RST#

VRAM_ODT1

M_CKE1

12

U1408

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

SDRAM DDR3

H5TC2G63FFR-11C_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

M_DA38

E3

M_DA36

F7

M_DA37

F2

M_DA35

F8

M_DA39

H3

M_DA32

H8

M_DA34

G2

M_DA33

H7

M_DA41

D7

M_DA44

C3

M_DA43

C8

M_DA45

C2

M_DA42

A7

M_DA46

A2

M_DA40

B8

M_DA47

A3

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

+1.5VS_VGA

PX@

R444

240_0402_1%

U1408 side U1409 side

1

C5251U_0402_6.3V4Z

C49510U_0603_6.3V6M

2

PX@

D D

1

C5261U_0402_6.3V4Z

C5131U_0402_6.3V4Z

C5241U_0402_6.3V4Z

2

PX@

2

1

C5271U_0402_6.3V4Z

2

PX@

1

C5281U_0402_6.3V4Z

C5040.1U_0402_10V6K

C5361U_0402_6.3V4Z

2

@

PX@

1

C5090.1U_0402_10V6K

C5080.1U_0402_10V6K

C5050.1U_0402_10V6K

2

PX@

+1.5VS_VGA +1.5VS_VGA

1

C5231U_0402_6.3V4Z

C5001U_0402_6.3V4Z

2

PX@

4

1

C5381U_0402_6.3V4Z

C5221U_0402_6.3V4Z

2

@

PX@

1

C4870.1U_0402_10V6K

C4840.1U_0402_10V6K

C4880.1U_0402_10V6K

2

PX@

1

C5300.1U_0402_10V6K

C5290.1U_0402_10V6K

C5350.1U_0402_10V6K

2

@

PX@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C49210U_0603_6.3V6M

2

PX@

2013/01/11 2013/12/31

1

C5011U_0402_6.3V4Z

C5031U_0402_6.3V4Z

C5021U_0402_6.3V4Z

2

PX@

Compal Secret Data

PX@

Deciphered Date

PX@

1

C4890.1U_0402_10V6K

C4930.1U_0402_10V6K

C4940.1U_0402_10V6K

C5370.1U_0402_10V6K

2

PX@

@

PX@

Title

SUN_VRAM A Upper

Size

Document Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

LA-D707P

5

of

42 60Wednesday, May 11, 2016

v0.2

5

Aditya11ttt.com

D D

4

3

@

2

0 ohm

1

R

CPU

PU801

+3VS

DGPU_PWR_EN

C C

GPIO78

U4103

EN

1. +3VS_VGA

PU8

GPU_PWRGD

1.8V_PWRGD

@

DGPU_PWROK

GPIO77

R

PU801

NMOS

PXS_PWREN#

+1.05VS

B B

2. VGA_CORE

U4102

3. +1.05VS_VGA GPU_RST

GPU

0 ohm

DGPU_HOLD_RST#

PLT_RST#

CPU

GPIO80

4. +1.5VS_VGA

U4102

+1.5VS

EN_1.8V

R

C

PU8

5. +1.8VS_VGA

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

D

Date: Sheet

RSVD

Document Number Rev

LA-D707P

1

43 60Wednesday, May 11, 2016

of

v0.2

5

Aditya11ttt.com

D D

C C

4

3

2

1

B B

A A

Security Classification

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Document Number Re v

Custom

Date : Sheet

2

Date : Sheet

Compal Electronics, Inc.

HW Reserve

LA-D707P

1

v0.2

o f

44 60Wednesday, May 11, 2016

o f

44 60Wednesday, May 11, 2016

o f

44 60Wednesday, May 11, 2016

5

Aditya11ttt.com

4

3

2

1

+19.5V_ADPIN

D D

C C

PJP1

@

ACES_51483-00801-001

9

10

GND GND

1

2

3

4

5

6

7

8

ADP_SIGNAL Charge_LED ACIN_LED

2

3

PD1

ESD@

1

L30ESD24VC3-2_SOT23-3

ADP_SIGNAL

2

3

PD2

ESD@

1

L30ESD24VC3-2_SOT23-3

12

PC1

EMI@

PR3 10K_0402_5%

1 2

12

100P_0402_50V8J

PL1

EMI@

5A_Z120_25M_0805_2P

1 2

PL2

DISEMI@

5A_Z120_25M_0805_2P

1 2

PC2

EMI@

1000P_0402_50V7K

12

PD3

PR5

10K_0402_5%

GLZ3.6B_LL34-2

+19.5V_VIN

PR1

@

0_0402_5%

12

PC3

PC4

EMI@

100P_0402_50V8J

1000P_0402_50V7K

AC_LED#<26>

ADP_ID <26>

12

PC6

PC5

@

100P_0402_50V8J

1000P_0402_50V7K

2014-10-06:

Change EC Power Rail Name

+3VALW_EC

12

PR7

16.2K_0402_1%

12

PH1 100K_0402_1%_NCP15WF104F03RC

BAT_CHG_LED<26>

1 2

12

PR2 100K_0402_5%

PR4 2K_0402_5%

1 2

12

PR6

100K_0402_5%

ADP_I <26,47>

12

PR8

5.9K_0402_1%

12

PR9 10K_0402_1%

ACIN_LED

Charge_LED

VCIN1_PH <26>VCIN0_PH <26>

ECAGND <26>

B B

Initail RecoveryInitail Recovery

OTP 92 C 56 C 0.65V 0.45V

A A

Security Classification

5

Security Classification

2015/10/09

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2015/10/09

3

Compal Secret Data

Deciphered Date

2018/10/09

2

45W UMA

65W DIS

Compal Electronics, Inc.

Title

DC Conn

Size

Document Number Re v

LA-D707P

Date : Sheet

0.95V 0.67V

Wednesday, May 11, 2016

1

v0.2

6045

o f

5

Aditya11ttt.com

D D

PJPB1

@

TAITW_PMPCR3-08MLBS1ZZ4H4

GND GND

1

2

3

4

5

6

7

8

9 10

4

+14.8V_BATT+

PR10 100_0402_5%

1 2

PR11 100_0402_5%

1 2

EMI@

5A_Z120_25M_0805_2P

1 2

EMI@

5A_Z120_25M_0805_2P

1 2

12

PC7

EMI@

1000P_0402_50V7K

PL3

PL4

12

EC_SMB_DA1 <26,47>

EC_SMB_CK1 <26,47>

3

PC8

EMI@

0.01U_0402_50V7K

12

+14.8V_BATT

PC9

12

1U_0603_25V6

@EMI@

2

PC10

@EMI@

1000P_0402_50V7K

1

+3VL

12

PR13

C C

2

3

PR12

100_0402_5%

1 2

100K_0402_5%

2

B/I# <26>

3

PD5

PD4

ESD@

1

L30ESD24VC3-2_SOT23-3

B B

A A

5

4

ESD@

1

L30ESD24VC3-2_SOT23-3

Security Classification

2015/10/09

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/09

3

Compal Secret Data

Deciphered Date

2018/10/09

2

Compal Electronics, Inc.

Title

BATT Conn

Size

Document Number Re v

LA-D707P

Wednesday, May 11, 2016

Date : Sheet

1

v0.2

6046

o f

A

Aditya11ttt.com

Protection for reverse input

B

+19.5VB

C

D

@

2

G

PR202

1 2 3

4

CHG_ACDRV_R

@

3M_0402_5%

1 2

12

PR201

@

1M_0402_5%

1 2

1 1

Need check the SOA for inrush

PQ202

+19.5V_VIN

MDU1512RH_POWERDFN56-8-5

5

12

PC201

2200P_0402_50V7K

2 2

PR204@

0_0402_5%

S

12

Vds = 60V Id = 250mA

2N7002KW_SOT323-3

1 2 3

PC202

0.1U_0402_25V6

12

PR208

PR209

4.12K_0603_1%

Rds(on) typ = 35mohm max Vgs = 20V Vds = 30V ID = 7.7A (Ta=70C)

PQ203 AON7506_DFN33-8-5

4

P2P1

5

12

PC208

0.1U_0402_25V6

1 2

+3VL

PR214 100K_0402_1%

max Power loss 0.22W for 90W;0.12W for 65W system CSR rating: 1W VACP-VACN spec < 80.64mV

PR203

0.01_1206_1%

1

2

0.1U_0402_25V6

4

3

1 2

PC209

CHG_ACP

CHG_ACN

CHG_CMSRC

CHG_ACDRV

Vgs = 20V

13

D

PQ201

VCIN1_ACOK<26>

3 3

PR218

422K_0402_1%

+19.5V_VIN

1 2

12

PC226

1U_0603_25V6

@EMI@

+19.5V_VIN

3

12

1U_0603_25V6K

1 12

PC210

0.1U_0402_25V6

PC212

1 2

CHG_VCC

20

21

PAD

1

ACN

2

ACP

3

CMSRC

BQ24725ARGRR_QFN20_3P5X3P5

4

ACDRV

5

ACOK

6

CHG_ACDET

12

PC227

PC228

1U_0603_25V6

@EMI@

EMI@

1UH_2.8A_30%_4X4X2_F

1 2

Isat: 4A DCR: 27mohm

VF = 0.5V

2

PD201 BAS40CW_SOT323-3

PC211

0.047U_0402_25V7K

1 2

PR206

10_1206_1%

PR207

CHG_LX

CHG_DH

18

19

VCC

HIDRV

PHASE

PU201

IOUT7SDA8SCL9ILIM

ACDET

CHG_IOUT

PC229

@EMI@

PL201

12

2.2_0603_5%

CHG_BST

17

12

PC230

1U_0603_25V6

@EMI@

12

CHG_REGN

16

BTST

REGN LODRV

BATDRV

10

CHG_ILIM

12

PC232

PC231

1U_0603_25V6

@EMI@

CHG_B+

12

PC204

PC203

10U_0805_25V6K

Rds(on) = 30mohm max Vgs = 20V Vds = 30V ID = 7A (Ta=70C)

VF = 0.37V

PD202 RB751V-40_SOD323-2

1 2

PC213

1U_0603_25V6K

GND

SRP

SRN

PR217

100K_0402_1%

CHG_DH

15

14

13

12

11

12

0_0402_5%

1 2

DL_CHG

PR212

10_0603_1%

CHG_SRP

1 2

PR213

6.8_0603_1%

CHG_SRN

1 2

CHG_BATDRV

PR216

620K_0402_1%

1 2

PC222

0.01U_0402_50V7K

@

12

PR215

12

PC206

PC205

EMI@

2200P_0402_50V7K

@EMI@

4

CHG_CSOP1

12

CHG_CSON1

PC221

.1U_0402_16V7K

+3VL

0.1U_0402_25V6

12

CHG_BATDRV

5

PQ205

AON7408L_DFN8-5

123

CHG_LX

5

PQ206

AON7408L_DFN8-5

123

12

PC233

PC234

@EMI@

1000P_0402_50V7K

7X7X3 Isat: 6.5A DCR: 30mohm

PL202

10UH_3.5A_20%_7X7X3_M

1 2

12

PR211@EMI@

4.7_1206_5%

12

PC220@EMI@

680P_0402_50V7K

12

PC235

@EMI@

1000P_0402_50V7K

1 2

PR205

4.12K_0603_1%

CHG

12

PC236

@EMI@

1000P_0402_50V7K

AON7506_DFN33-8-5

CHG_BATDRV_R

0.01_1206_1%

1

2

CHG_CSOP1

12

PC216

0.1U_0402_25V6

12

PC237

@EMI@

1000P_0402_50V7K

Support max charge 3.5A Power loss: 0.245W CSR rating: 1W VSRP-VSRN spec < 81.28mV

PR210

PC238

@EMI@

PQ204

4

PC239

@EMI@

1000P_0402_50V7K

1 2 35

4

3

CHG_CSON1

12

PC217

Rds(on) = 35mohm max Vgs = 20V Vds = 30V ID = 7.7A (Ta=70C)

12

PC207

0.01U_0402_50V7K

+14.8V_BATT

12

0.1U_0402_25V6

PC214

PC215

10U_0805_25V6K

PR224

@

0_0402_5%

12

PC223

2200P_0402_50V7K

PR222

66.5K_0402_1%

PC224

12

PR223

0_0402_5%

100P_0402_50V8J

1 2

Vin Dectector

4 4

Min. Typ Max. L-->H 17.16V 17.63V 18.12V H-->L 16.76V 17.22V 17.70V

VILIM = 20*ILIM*Rsr ILIM = 3.3*100/(100+620)/20/0.01 = 2.29 A

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/09 2018/10/09

1 2

PR225

@

0_0402_5%

1 2

12

PC225 100P_0402_50V8J

Close EC chip

Compal Secret Data

Deciphered Date

C

@

EC_SMB_CK1 <26,46>

EC_SMB_DA1 <26,46>

ADP_I <26,45>

Compal Electronics, Inc.

Title

Size

Date : Sheet

Compal Electronics, Inc.

CHARGER(BQ24725)

Document Number Re v

CHARGER(BQ24725)

47 60Wednesday, May 11, 2016

D

47 60Wednesday, May 11, 2016

v0.2

o f

5

Aditya11ttt.com

4

3

2

1

Module model information

RT8243A_V1.mdd

D D

+19.5VB_3V/5V

+19.5VB

C C

Vout=VFB * (1+(R1/R2)) VFB=2V

B B

Vout=2*(1+(13.3K(PR38)/20K(PR40))) Vout=3.3V

ENLDO threshold ON: 1.2min 1.6typ 2max OFF: 0.9min 0.95typ 1max

B+ threshold ON: 5.19min 6.92typ 8.65max OFF: 3.89min 4.11typ 4.33max

VIN rising threshold: 5.1typ 5.5max falling threshold: 3.5min 4.5max

+3.3VALWP Ipeak=4.26A ; Imax=3A Delta I=1.92A=>1/2Delta I=0.96A Rds(on)=15.8m ohm(max) ; Rds(on)=12.4m ohm(typical) OCP = 5.1A

A A

TDC:4.31A Fsw:375KHz H-MOS PD:0.3736W ∆ T:12 L-MOS PD:0.2713W ∆ T:7.9 Choke PD:1.5158W ∆ T:24 OVP margin for Vos:8% @ 330uF cap, 6% @ 220uF

PJB1

@

112

JUMP_43X79

+3VALWP

2

+3VALW

12

PC34

0.1U_0402_25V6

@EMI@

1

+

2

12

PC35

PC33

2200P_0402_50V7K

EMI@

4.7U_0805_25V6-K

PL9

3.3UH_6.3A_20%_7X7X3_M

1 2

PC40

220U 6.3VM_R15

PC39

4.7U_0805_25V6-K

4

3

2

D1

LX_3V LX_3V

PR47

4.7_1206_5%

@EMI@

PC41

680P_0402_50V7K

@EMI@

D110D2/S1

12

S2

6

7

5

SPOK<9>

1

G1

9

G2

PQ7

AON7934_DFN3X3A8-10

8

1 2

PC38

0.1U_0402_25V6

MAINPWON<26>

℃

5

4

ENTRIPx adjustment range: 0.5V~3V, floating or over 4.5V will shutdown channel.

PR38

13.3K_0402_1%

1 2

PR40

20K_0402_1%

12

2.2_0603_5%

1 2

+19.5VB_3V/5V

EC_ON<26>

1 2

FB=1 .98 V(Mi n)

2.006V(Typ)

2.03V(Max)

PR111

10K_0402_1%

PR46

BST_3V

UG_3V

LG_3V

499K_0402_1%

1 2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

6

7

8

9

10

PR49

2.2K_0402_5%

1 2

PR52

@

0_0402_5%

1 2

402K_0402_1%

Issued Date

PGOOD

BOOT2

UGATE2

PHASE2

LGATE2

FB_3V

5

FB2

RT8243AZQW_WQFN20_3X3

VIN11ENLDO12ENM13LDO514LDO3

12

PC45 0.1U_0603_25V7K

PR50

150K_0402_1%

PR51

PR53

3

12

PR41 100K_0402_1%12PR42 56K_0402_1%

ENTRIP2

3

4

TON

ENTRIP2

PU2

ENM

12

ENM

12

PR44 113K_0402_1%

ENTRIP1

2

ENTRIP1

12

4.7U_0603_10V6K

PC48

4.7U_0603_10V6K

2015/10/09

PR39

30K_0402_1%

1 2

PR43

20K_0402_1%

1 2

FB=1 .98 V(Mi n)

2.006V(Typ)

FB_5V

2.03V(Max)

1

FB1

PAD

BYP1

BOOT1

UGATE1

PHASE1

LGATE1

15

+3VLP

12

PC46

4.7U_0603_10V6K

+VLP

PC47

21

20

19

18

17

16

2.2_0603_5%

BST_5V

1 2

UG_5V

LX_5V

LG_5V

PJP10

@

JUMP_43X39

112

PJP11

@

JUMP_43X39

112

Compal Secret Data

Deciphered Date

PR45

ENLDO (V)

Low Low

">1.6V" =>High

">1.6V"

">2.3V"

=>High

=>High ">2.3V"

">1.6V"

=>High

">2.3V"

">1.6V"

=>High

">2.3V"

">1.6V"

=>High

+19.5VB_3V/5V

12

2

Trace width need meet LDO5 demand

12

PC36

PC44

4.7U_0805_25V6-K

PC37

0.1U_0402_25V6

1 2

AON7934_DFN3X3A8-10

Typ: 175mA

+3VL

Rds(on):12.4mΩ ~15.8mΩ

Typ: 225mA

+VL

5V=375KHz 3V=400KHz (Vin=12 ~ 25v) (By Rton= 56K ohm)

+5VALWP Ipeak=9.26A ; Imax=6.5A Delta I=3.483A=>1/2Delta I=1.742A Rds(on)=15.8m ohm(max) ; Rds(on)=12.4m ohm(typical) OCP =11.11A

TDC:4.9A Fsw:321KHz H-MOS PD:0.4173W ∆ T:13.4 L-MOS PD:0.3442W ∆ T:10 Choke PD:1.9613W ∆ T:30 OVP margin for Vos:9% @ 330uF cap, 8% @ 220uF

2018/10/09

2

ENM (V)

Low

9

PQ8

ENTRIP1 (V)

D2/S1

ENTRIP2 (V)

X X

Off

On On

On

Vout=VFB * (1+(R1/R2)) VFB=2V Vout=2*(1+(30K(PR39)/20K(PR43))) Vout=5V

4

3

2

1

D1

G1

D1

S2

G2

6

7

5

8

+3VALWP +3VALW

+5VALWP +5VALW

℃ ℃

Title

Size

Custom

Date : Sheet

Date : Sheet o f

LDO5 LDO3 +5VALW +3V ALW

Off Off Off Off

On On Of f Off

XX

On

Off

On

On On Of f On

OnOn On On

Off

10

℃

Document Number Re v

2.2UH_7.8A_20%_7X7X3_M

LX_5V

12

PR48

4.7_1206_5%

12

@EMI@

PC42

@EMI@

680P_0402_50V7K

@

112

JUMP_43X118

@

112

JUMP_43X118

Compal Electronics, Inc.

Wednesday, May 11, 2016

OnOnOn Off

PL8

1 2

PJP2

2

PJP3

2

3VALW/5VALW

LA-D707P

1

OffOff

1

+

PC43

2

220U 6.3VM_R15

48 60

+5VALWP

o f

v0.2

5

Aditya11ttt.com

4

3

2

1

Module model information

RT8207M_V1.mdd For Single layer RT8207M_V2.mdd For Dual layer

D D

Pin19 need pull separate from +1.35VP. If you have +1.35V and +0.675V sequence question,

PJB2

@

2

+19.5VB

112

JUMP_43X79

+1.2VP

12

C C

PC56

22U_0603_6.3V6M

12

PC58

PC59

PC57

22U_0603_6.3V6M

+19.5VB_1.35VP

12

PC49

@EMI@

2200P_0402_50V7K

LX_1.35VP

PR56

PC64

12

PC50

PC51

10U_0805_25V6K

12

0.1U_0603_25V7K

10U_0805_25V6K

4

1

3

2

D1

G1

9

D110D2/S1

S2

G2

6

7

5

8

PQ11 AON7934_DFN3X3A8-10

Rds(on):12.4mΩ ~15.8mΩ

+5VALW +1.2VP

12

PL11

1UH_11A_20%_7X7X3_M

1 2

@EMI@

PC62

22U_0603_6.3V6M

4.7_1206_5%

@EMI@

680P_0402_50V7K

12

PC61

22U_0603_6.3V6M

+1.35VP Ipeak=7.4A ; Imax=6A Delta I=2.2A=>1/2Delta I=1.1A (F=521K Hz) Rds(on)=15.8m ohm(max) ; Rds(on)=12.4m ohm(typical)

OCP = 8.88

Choke: 7x7x3 Rdc=8.3mohm(Typ), 10mohm(Max)

Switching Frequency: 285kHz Ipeak=10 A Iocp~13A OVP: 110%~120% VFB=0.75V, Vout=1.3545V

2

014/12/2 3

change from SUSP# to SM_PG_CTRL

12

PC52

2.5V PG Enable 1.2V

BST_1.35VP_R

PR57

5.1_0603_5%

1 2

DDR_PWROK

@

PAD

2.2_0603_5%

1 2

PR55

11.5K_0402_1%

1 2

1U_0402_6.3V6K

12

PC63

1U_0402_6.3V6K

5.1_0603_5%

1 2

+19.5VB_1.35VP

SUSP#<12,13,26,35>

PR54

PC55

1 2

VDD_1.35VP

PR65

SYSON<12,26,35,49>

LG_1.35VP

CS_1.35VP

+2.5V_PG

SM_PG_CTRL<6>

Mode Level +0.675VSP VTTREF_1.35V S5 L off off S3 L off on

B B

S0 H on on

Note: S3 - sleep ; S5 - power off

you can change from +1.35VP to +1.35VS.

BST_1.35VP

UG_1.35VP

LX_1.35VP

16

18

15

LGATE

14

PGND

13

CS

12

VDDP

11

VDD

PR59

470K_0402_1%

1 2

@

0_0402_5%

1 2

0_0402_5%

1 2

0_0402_5%

1 2

PHASE

PGOOD

10

PR1815

PR61

@

0_0402_5%

PR62

@

PR63

@

0.1U_0402_10V7K

17

9

TON_1.35VP

@

20

19

21

VTT

PAD

BOOT

UGATE

S5

TON

8

EN_1.35VP

12

PC65

0.1U_0402_10V7K

VLDOIN

VTTGND

VTTSNS

GND

VTTREF

VDDQ

FB

S3

6

7

FB_1.35VP

EN_0.675VSP

1

2

3

4

5

PU3 RT8207PGQW_WQFN20_3X3

+1.2VP

12

PC66

@

+0.6VSP

VTTREF_1.35VP

6.04K_0402_1%

1 2

12

PR60 10K_0402_1%

PR58

VFB=0.75 V

+1.2VP

12

PJP4

@

JUMP_43X118

112

PJP5

@

JUMP_43X39

112

PC53

10U_0603_6.3V6M

2

12

PC54

12

PC60

0.033U_0402_16V7K

+1.2VP

0.675Volt +/- 5% TDC 0.7A Peak Current 1A

+0.6VSP

10U_0603_6.3V6M

Vout=Vref * (1+(R1/R2)) Vref= 0.75 V Vout= 0.75* (1+(6.04K (PR58 )/10 K(PR60))) Vout= 1.2V

+1.2V_VDDQ

+0.6V_0.6VS

Module model information

SY803 2_V2 .mdd

PJM5

12

PCM24

PCM23

22U_0603_6.3V6M

Compal Secret Data

@

JUMP_43X39

2

112

+2.5VP

Imax= 2A, Ipeak= 3A FB=0. 6V

Vout=0.6V* (1+Rup/Rdown)

Deciphered Date

2

Vout=0.6V * (1+(R1/R2)) Vout= 0.6*( 1+(32.4K( PRM23 )/10 K(PRM26)) ) Vout= 2.5V

Compal Electronics, Inc.

Title

2018/10/09

Title

Size

Date: Sheet

1.2VP/0.6VSP/2.5VP(RT8207P/SY8032A)

Document Number Rev

Wednesday, May 11, 2016

1

49 60

of

Note : When design Vin=5V, please stuff snubber to prevent Vin damage

+3VALW

PRM27

@

0_0402_5%

PM_SLP_S4#<9,12,26,35>

SYSON<12,26,35,49>

A A

1 2

PRM24

@

0_0402_5%

1 2

PJM4

@

JUMP_43X39

112

+3VALW

1M_0402_1%

EN_2.5V

PRM25

5

4

2

Enable 1.2V

12

PCM21

22U_0603_6.3V6M

1 2

PRM21

100K_0402_5%

12

PCM25

@

0.1U_0402_16V7K

+2.5V_PG

PUM2 SY8032ABC_SOT23-6

4

IN

5

PG

FB6EN

+2.5VP +2.5V

PLM3

1UH_2.3A_+-20%_2.5X2X1.2_F

LX_2.5V

3

LX

2

GND

1

1 2

12

PCM22

68P_0402_50V8J

2015/10/09

12

@EMI@

4.7_0402_5%

PRM22

PRM23

32.4K_0402_1%

12

Rup

12

FB_2.5V

PRM26

10K_0402_1%

12

Rdow n

PCM26

@EMI@

680P_0402_50V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

v0.2Custom

A

Aditya11ttt.com

1 1

B

C

D

+3V_PRIM

12

LX_1V

FB_1V

LDO3V_1V

PR611 100K_0402_5%

PL1207

EMI@

5A_Z120_25M_0805_2P

+19.5VB

+1.8V_PG<51>

2 2

EN :H>0.8V ; L<0.4V

EN pin don't floating If have pull down resistor at HW side, please delete PR601.

3 3

1 2

PR603

@

0_0402_5%

1 2

12

PC605

@EMI@

12

0_0402_5%

12

@

0_0402_5%

@

PR609

PC606

0.1U_0402_25V6

PR607

PC604

EMI@

2200P_0402_50V7K

12

PC601

@

0.1U_0402_25V6

PR601

1M_0402_1%

The current limit is set to 6A, 9A or 12A when this pin is pull low, floating or pull high.

+3VALW

10U_0805_25V6K

12

+19VB_1V

12

PC607

10U_0805_25V6K

EN_1V

ILMT_1V

+3VALW

PU601

2

3

4

5

7

8

18

11

13

15

12

PC614 1U_0402_6.3V6K

IN

GND

EN

ILMT

BYP

SY8286RAC_QFN20_3X3

VCC

PAD

9

PG

1

BS

6

LX

19

LX

20

LX

14

FB

17

10

NC

12

NC

16

NC

21

Confirm HW side

+1.0V_VS_PG_PWR <26>

PR606

@

0_0402_5%

1 2

12

PC613

2.2U_0402_6.3V6M

BST_1V_RBST_1V

PC603

0.1U_0201_10V6K

1 2

+1.0V_PRIM

PR605

@EMI@

4.7_1206_5%

SNUB_1V

1 2

(Common Part SH00000YE00)

PL602

3

4

1UH_11A_20%_7X7X3_M

FB=0.6V

@EMI@

2

1

R1

R2

PC602

680P_0603_50V7K

1 2

12

PR608

14K_0402_1%

12

PR610 20K_0402_1%

Vout=0.6V* (1+R1/R2) =0.6*(1+(14K(PR608)/20K(PR610)))

12

PC615

@

22U_0603_6.3V6M

12

PC608

PC609

330P_0402_50V7K

22U_0603_6.3V6M

Vout=1.0V

PC610

12

PC616

@

22U_0603_6.3V6M

12

PC611

22U_0603_6.3V6M

12

PC618

PC617

@

12

PC612

22U_0603_6.3V6M

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/09 2018/10/09

Compal Secret Data

Deciphered Date

C

Title

Size

Document Number Re v

Custom

Date : Sheet

1.0VS(SY8286)

D

50 60Wednesday, May 11, 2016

v0.2

o f

5

Aditya11ttt.com

D D

PJB4

@

+3VALW

C C

2015/01/06 PGOOD from +3VS

+3V_PRIM

change to +3V_PRIM

PCH_PWR_EN<13,26,35>

1 2

PR94

@

0_0402_5%

JUMP_43X39

112

+1.8V_PG<50>

EN_1.8V

12

2014/12/13 change net name to PCH_PWR_EN

4

PC94

22U_0603_6.3V6M

1 2

2

1 2

PR1814

100K_0402_5%

12

PR95

PC98

@

1M_0402_1%

PU6

SY8032ABC_SOT23-6

IN_1.8V LX_1.8V

4

IN

5

PG

GND

FB6EN

0.1U_0402_16V7K

3

Imax= 2A, Ipeak= 3A FB=0.6V

PL15

1UH_2.8A_30%_4X4X2_F

3

LX

2

1

1 2

12

@EMI@

PR93

4.7_0603_5%

SNUB_1.8V

12

@EMI@

PC99

680P_0402_50V7K

20K_0402_1%

FB_1.8V

10K_0402_1%

PR92

PR96

12

Rup

12

Rdown

12

PC95

68P_0402_50V8J

2

PJP9

@

2

+1.8VSP +1.8V_PRIM

112

JUMP_43X79

+1.8VSP

12

PC97

PC96

22U_0603_6.3V6M

Vout=0.6V * (1+(R1/R2)) Vout=0.6*(1+(20K(PR92)/10K(PR96))) Vout=1.8V

1

Note: When design Vin=5V, please stuff snubber

B B

to prevent Vin damage

Vout=0.6V* (1+Rup/Rdown)

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2015/10/09 2018/10/09

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

B

Date : She et

2

Date : She et

Compal Electronics, Inc.

1.8VS(SY8032A)

Document Number Re v

LA-D707P

1

o f

51 60

o f

51 60

o f

51 60

v0.2

1

Aditya11ttt.com

PR1101=2*PR1106/(10*IOUTmax*Load line) U22 Iout@GT=31A PR1101=25.5kohm

PR1106=Iout limit*Load line/10

U22 OCP@GT=40A PR1106=12.4kohm

A A

program IccMax_2ph

DIFFOUT_GT

12

PR1104

100K_0402_1%

B B

220K_0402_5%_B25/50 4700K

SWN1_GT<52,53>

PR1103

649_0402_1%

PR1105

4.7K_0402_1%

PC1104

3300P_0402_25V7K

12

FB_GT

12

COMP_GT

Place close to PL1203

PH901

12

PR1102

12

PC1102

12

PC1103

PR1109

84.5K_0603_1%

1 2

SWN1_GT<52,53>

Place close to PL1203

C C

472mV/120uA=3.933K Act i ve Poi nt110 degr eeC = 4. 206K

D D

CSN1_GT<53>

2014/12/24 P

R1243 change to 1k ohm

RIccMAX2ph(PR1104)= (IccMAX2Ph+32)*200kohm/ 127 U22 IccMAX@GT= 31A PR1104= 100K

Load line=(PR1108+(PR1107+PH901/(PR1107*PH901)))*Iout tltal*DCR/PR1109 U22 Load line@GT= 3.1m PR1109 , PR1110@GT=84.5K

VSSSA_SENSE<12>

VCCSA_SENSE<12>

+VCC_SA

49.9_0402_1%

470P_0402_50V7K

15P_0402_50V8J

12

CSCOMP_GT_R

Place close to PQ1201

12

PR1107 75K_0402_1%

12

PR1108 165K_0402_1%

+5VS

PH1102

VCCGT_SENSE<14>

VSSGT_SENSE<14>

12

PR1111

2K_0402_1%

1 2

PR1112

10_0402_1%

1 2

PR1243 1K_0402_1%

1 2

12

100K_0402_1%_B25/50 4250K

+VCC_GT

PC1108

33P_0402_50V8J

TSENSE_GT

12

PR1115

1.07K_0402_1%

TSENSE_GT_R

12

PC1107

820P_0402_25V7

CSP1_GT

12

PC1110

0.1U_0402_25V6

CSREF_GT

CSP2_GT

12

PR1116

61.9K_0402_1%

1

2

PC1136

PC1137

PC1139

PR1101

PC1101

1 2

PR1117

BST1_GT<53>

UG1_GT<53> LX1_GT<53> LG1_GT<53>

@

2200P_0402_50V7K

0_0402_5%

1 2

12

1.78K_0402_1%

1 2

1000P_0402_50V7K

12

IOUT_GT

DIFFOUT_GT FB_GT COMP_GT ILIM_GT CSCOMP_GT CSSUM_GT CSREF_GT CSP2_GT CSP1_GT TSENSE_GT

VRMP

1 2

PC1113

0.01U_0402_50V7K

1 2

PR1150

PR1149

PC1135

1 2

PR1156

1.24K_0402_1%

1 2

PC1138

3300P_0402_50V7-K

CPU core_VCC

12

PC1114

1U_0603_10V6K

close to CPU

PR1154

100_0402_1%

1 2

PR1153

100_0402_1%

close to CPU

PR1159 100_0402_1%

1 2

close to CPU

PR1160 100_0402_1%

1 2

PR1152

@

0_0402_5%

1 2

1000P_0402_50V7K

1 2

PR1151

@

0_0402_5%

PR1157

@

0_0402_5%

1 2

1000P_0402_50V7K

1 2

PR1158

@

0_0402_5%

close to CPU

25.5K_0402_1%

1 2

PR1106

12.4K_0402_1%

12

PC1109

0.01U_0402_50V7K

470P_0402_50V8J

12

PC1112

0.1U_0402_25V6

+19VB_CPU

1K_0402_1%

1 2

NCP81206 Operat i ng Fr equency Rosc =21. 5 K

I/A and GT are around 450KHz and SA is 600KHz

IccMAX@SA= 5A

PR1123= 11K

Refer IccMAX table in datasheet

IccMAX@VCORE= 28A

RIccMAX@VCORE= 24.9K

Refer IccMAX table in datasheet

2

PR1155

20K_0402_1%

1 2

VSP_GT

1

IOUT_2ph

2

DIFFOUT_2ph/ICCMax_2ph

3

FB_2ph

4

COMP_2ph

5

ILIM_2ph

6

CSCOMP_2ph

7

CSSUM_2ph

8

CSREF_2ph

9

CSP2_2ph

10

CSP1_2ph

11

TSENSE_2ph

12

VRMP

13

VCC

+5VS

1 2

PR1118

2.2_0603_5%

PR1120

1 2

21.5K_0402_1%

VSN_GT

53

EPAD

+5VS

PR1148

PC1133

PC1116

12

1.5K_0402_1%

12

0.015U_0402_25V7K

51

52

VSN_2ph

BST114PVCC

15

12

2.2U_0603_10V6K

3

RDRPSP(PR1149)= Load line*(PR1146+PH1105+PR1145)/(gm Load line@SA= 10.3m gm=1mS

PR1149=1.78K

RLIMSP(PR1147)= 1.3V/(gm*(PH1105+PR1145)*IoutLIMIT*DCR/(PR1146+PH1105+PR1145)) OCP@SA= 9.6A gm=1mS PR1147=24K

RIOUTSP(PR1144)= 2V/(gm*(PH1105+PR1145)*ICCMAX*DCR/(PR1146+PH1105+PR1146)) IOUTSP@SA= 5A gm=1mS

PR1144=69.8K

Place close

12

PR1145

12K_0402_1%

0.01U_0402_50V7K

SCLK_CORE ALERT#_CORE SDIO_CORE VR_HOT_CORE IOUT_CORE CSP_CORE CSN_CORE ILIM_CORE COMP_CORE VSN_CORE VSP_CORE

PC1119

BST_CORE <53> UG_CORE <53> LX_CORE <53> LG_CORE <53>

12

to PL1206

PH1105 100K_0402_1%_B25/50 4250K

CSN_SA_R

12

PR1146

7.5K_0603_1%

1 2

PR1143 10K_0402_1%

1 2

PR1142

@

0_0402_5%

1 2

PR1141=43.2k for debug

PR1137

52.3K_0402_1%

1 2

PC1128

82P_0402_50V8J

1 2

12

PC1132

PC1134

15P_0402_50V8J

1000P_0402_50V7K

PSYS_MON

VSP_SA

49

50

PSYS

VSP_1b

VSP_2ph

SW116LG1/ROSC17LG2/ICCMAX_1a19SW2

HG1

VR_PWRGD_R

VSN_SA

CSP_SA

CSN_SA

ILIM_SA

IOUT_SA

COMP_SA

44

45

47

48

43

42

40

46

41

EN

ILIM_1b

CSP_1b

VSN_1b

CSN_1b

IOUT_1b

VR_RDY

COMP_1b

PWM/ADDR_VBOOT

TSENSE_1ph

HG325SW324LG3/ICCMAX_1b23BST222HG2

BST3

20

21

18

26

1 2

PR1123

11K_0402_1%

N27484288

12

PR1121

29.4K_0402_1%

RDRPSP(PR1128)= Load line*(PR1136+PH1104+PR1135)/(gm * DCR) /(PH1104+PR1135) Load line@VCORE= 2.1m gm=1mS

PR1128=2.1K

RIOUTSP(PR1137)= 2V/(gm*(PH1104+PR1135)*ICCMAX*DCR/(PR1136+PH1104+PR1135)) IOUTSP@VCORE= 28A gm=1mS

PR1137=64.9K

RLIMSP(PR1134)= 1.3V/(gm*(PH1104+PR1135)*IoutLIMIT*DCR/(PR1136+PH1104+PR1135)) OCP@VCORE= 35A gm=1mS

PR1134=33.2K

3

12

PR1147

24K_0402_1%

PC1130

PC1131

1000P_0402_50V7K

PC1129

470P_0402_50V8J

1 2

PR1144

69.8K_0402_1%

1 2

VR_ON_R

39

DRON

38

SCLK

37

ALERT#

36

SDIO

35

VR_HOT#

34

IOUT_1a

33

CSP_1a

32

CSN_1a

31

ILIM_1a

30

COMP_1a

29

VSN_1a

28

VSP_1a

PU1101

NCP81206MNTXG_QFN52_6X6

27

TSENSE_CORE

0.1U_0402_25V6

CSN_SA <53>

SWN_SA <53>

+3VS

VR_PWRGD <26>

VR_ON <26,35>

PR1141

51.1K_0402_1%

1 2

PWM_SA <53>

DRON <53>

4

* DCR) /(PH1105+PR1145)

49.9_0402_1%

1 2

@

0_0402_5%

1 2

10_0402_1%

1 2

8200P_0402_25V7K

2.1K_0402_1%

1 2

PC1121

1000P_0402_50V7K

TSENSE_CORE

PR1125

1.07K_0402_1%

TSENSE_CORE_R

12

PR1126

61.9K_0402_1%

4

+1.0V_VCCST

PR1139

45.3_0402_1%

PR1164

PR1165

PR1163

12

1 2

PC1124

1 2

PC1123 15P_0402_50V8J

PC1120

2200P_0402_50V7K

1 2

PR1127

1K_0402_1%

PR1128

1 2

PR1242

2.1K_0402_1%

12

5

12

PR1140

110_0402_1%

@

1 2

PR1161

100_0402_1%

12

PC1126

0.01U_0402_50V7K

1 2

PR1133

2.49K_0402_1%

12

PC1127

PC1122 1000P_0402_50V7K

PR1138

PR1162

499_0402_1%

100_0402_1%

@

1 2

12

PR1136

7.5K_0603_1%

PR1135

12K_0402_1%

CSN_CORE_R

12

PH1104 100K_0402_1%_B25/50 4250K

Place

0.022U_0402_25V7K

close to PL1205

1000P_0402_50V7K

PR1129

@

0_0402_5%

1 2

PR1130

@

0_0402_5%

12

PC1105

VR_HOT#

0.1U_0402_25V6

SOC_SVID_CLK <14>

SOC_SVID_ALERT#_R <14>

SOC_SVID_DAT <14>

VR_HOT# <26>

2015/01/05 change PR1141 from 51.1k to

43.2k, to set the Vboot voltage from 0V to 1.2V

SWN_CORE <53>

CSN_CORE <53>

1 2

PC1125

1 2

PR1134

28K_0402_1%

PR1131

100_0402_1%

1 2

close to CPU

PR1132

100_0402_1%

1 2

VSSSENSE <14>

VCCSENSE <14>

+VCC_CORE

close to CPU

472mV/120uA=3.933K Act i ve Poi nt 110 degr eeC = 4. 206K

Place close

PH1103

to PQ1205

100K_0402_1%_B25/50 4250K

Title

VCC_CORE_U22(NCP81206)

Size

Document Number Re v

Date: Sheet

5

v0.2

of

52 60Wednesday, May 11, 2016

of

52 60Wednesday, May 11, 2016

of

52 60Wednesday, May 11, 2016

1

Aditya11ttt.com

2

3

4

5

Input Capacitor: 10uF_080 5_X5R_25 V

12

5

BST1_GT_R

PC1115

PC1118

DRVH

GND

DRVL

PAD

9

SW

12

LX_CORE

8

7

6

5

4

12

PQ1201

123

MDU1516URH_POWERDFN56-8-5

LX1_GT

5

PQ1202

AON6794_DFN5X6-8-5

123

5

PQ1205

123

MDU1516URH_POWERDFN56-8-5

5

PQ1206

123

AON6794_DFN5X6-8-5

PC1241

0.22U_0603_25V7K

UG_SA

LG_SA

A A

B B

C C

D D

UG1_GT<52>

PR1119

2.2_0603_5%

PC1242

1 2

0.22U_0603_25V7K

PR1124

2.2_0603_5%

BST_CORE_R

1 2

0.22U_0603_25V7K

PR1241

2.2_0603_5%

1 2

PU1502

NCP81253MNTBG_DFN8_2X2

1

BST

2

PWM

3

EN

4

VCC

12

BST1_GT<52>

LX1_GT<52>

LG1_GT<52>

UG_CORE<52>

BST_CORE<52>

LX_CORE<52>

LG_CORE<52>

PWM_SA<52>

DRON<52>

+5VS

2.2U_0603_10V6K

2014/12/ 31 change PU1502 VCC pin from +5VALW to +5VS

12

PC1201

10U_0805_25V6K

12

PR1210

4.7_1206_5%

@EMI@

SNUB1_GT

12

PC1210

@EMI@

680P_0603_50V7K

InputCap acitor: 10uF_080 5_X5R_25 V

12

PC1221

10U_0805_25V6K

12

PR1230

4.7_1206_5%

@EMI@

SNUB_CORE

12

PC1230

680P_0603_50V7K

@EMI@

LX_SA

5

6

7

8

12

PC1203

10U_0805_25V6K

PL1203

1

2

12

PC1222

10U_0805_25V6K

PL1205

1

2

10

D1

G1

D2/S1

PQ1207

9

AON7934_DFN3X3A8-10

PC1204

10U_0805_25V6K

4

3

12

PC1223

10U_0805_25V6K

4

3

4

3

2

UG_SALG_SA

1

PC1202

10U_0805_25V6K

0.24UH_22A_+-20%_7X7X3_M

12

0.24UH_22A_+-20%_7X7X3_M

S2

G2

0.24uH (DCR 1.19 +-5%)

PC1224

+19VB_CPU

1

12

+

PC1384

PC1385

PC1205

2

0.1U_0402_25V6

EMI@

2200P_0402_50V7K

@EMI@

100U_25V_NC_6.3X6

H=5.8mm

+VCC_GT

Choke 0.24uH SH000010N00

CSN1_GT <52>

SWN1_GT <52>

12

PC1387

0.1U_0402_25V6

10U_0805_25V6K

@EMI@

+VCC_CORE

0.24uH (DCR 1.19 +-5%)

Choke 0.24uH SH000010N00

Input Capacitor: 10uF_080 5_X5R_25 V

12

PR1240

@EMI@

SNUB_SA

12

PC1240

@EMI@

1

12

PC1386

2

EMI@

2200P_0402_50V7K

H=5.8mm

CSN_CORE <52>

SWN_CORE <52>

12

PC1231

PC1232

10U_0805_25V6K

0.47UH_MMD05CZR47M_12A_20%

Choke 0.47uH SH000015M00

4.7_1206_5%

0.47uH (DCR 6.2 +-5%)

680P_0603_50V7K

PL1201

EMI@

5A_Z120_25M_0805_2P

1 2

PL1202

EMI@

5A_Z120_25M_0805_2P

1 2

GT_CORE FSW = 450kHz DCR = 1.19 mohm +/- 5% TDC@GT_CORE = 18A TYP MAX H/S Rds(on) = 11.7 mohm , 14 mohm L/S Rds(on) = 2.7 mohm , 3.3 mohm

+VCC_GT

1

+

2

+19.5VB

PC2123

390U_2.5V_ESR10M_6.3X6

+19VB_CPU

+

PC1225

CPU_CORE FSW = 450kHz

100U_25V_NC_6.3X6

DCR = 1.19 mohm +/- 5%

TDC@VCC_CORE = 21A TYP MAX H/S Rds(on) = 11.7 mohm , 14 mohm L/S Rds(on) = 2.7 mohm , 3.3 mohm

+VCC_CORE

1

+

PC2124

PC1383

2

@

330U_D1_2VY_R9M

390U_2.5V_ESR10M_6.3X6

+19VB_CPU

12

PC1389

PC1388

0.1U_0402_25V6

@EMI@

EMI@

+VCC_SA

2200P_0402_50V7K

PL1206

1

4

3

2

Total VCORE Output Capacitor: 4 X 22uF_0603_X5R 4 X 22uF_0603_X5R on CPU back side

SA_CORE FSW = 450kHz DCR = 6.2 mohm +/- 5% TDC@SA_CORE = 4A TYP MAX H/S Rds(on) = 12.4 mohm , 15.8 mohm L/S Rds(on) = 8.4 mohm , 10.3 mohm

CSN_SA <52>

SWN_SA <52>

Total VCC_GT Output Capacitor: 13 X 22uF_0603_X5R + 1 X 330uF 13 X 22uF_0603_X5R on CPU back side

1

PC1302

PC1301

2

1

2

22U_0603_6.3V6M

1

PC1311

PC1312

2

22U_0603_6.3V6M

1

PC1351

2

@

22U_0603_6.3V6M

1

PC1361

2

22U_0603_6.3V6M

1

PC1391

2

22U_0603_6.3V6M

1

PC1303

2

22U_0603_6.3V6M

1

PC1313

2

@

22U_0603_6.3V6M

2014/12/ 25 add 7 pcs 22uF cap for primary side, total 20 pcs

1

PC1352

2

@

22U_0603_6.3V6M

1

PC1362

2

@

22U_0603_6.3V6M

Total VCORE Output Capacitor: 8 X 22uF_0603_X5R 4 X 22uF_0603_X5R on CPU back side

1

PC1392

2

22U_0603_6.3V6M

1

PC1304

2

1

2

PC1353

22U_0603_6.3V6M

PC1363

22U_0603_6.3V6M

1

2

PC1305

2

22U_0603_6.3V6M

1

PC1317

PC1319

2

@

22U_0603_6.3V6M

Total VCORE Output Capacitor: 20 X 22uF_0603_X5R + 2 X 330uF 13 X 22uF_0603_X5R on CPU back side.

1

PC1354

2

@

22U_0603_6.3V6M

1

PC1364

2

@

22U_0603_6.3V6M

1

PC1394

PC1393

2

22U_0603_6.3V6M

1

PC1307

PC1306

2

1

2

PC1355

22U_0603_6.3V6M

PC1365

22U_0603_6.3V6M

1

PC1395

2

22U_0603_6.3V6M

1

PC1314

PC1320

2

22U_0603_6.3V6M

1

PC1357

PC1356

2

@

22U_0603_6.3V6M

1

PC1366

PC1367

2

@

22U_0603_6.3V6M

1

PC2118

2

@

22U_0603_6.3V6M

2015/5/1 9 ADD 5pcs cap on +Vcc_IA

1

PC1396

2

@

22U_0603_6.3V6M

2014/12/ 25 change 3pcs to un-mount

1

2

1

2

22U_0603_6.3V6M

1

2

@

PC1397

PC1308

22U_0603_6.3V6M

PC1316

22U_0603_6.3V6M

1

PC1358

2

@

1

PC1368

2

PC2119

22U_0603_6.3V6M

+VCC_SA

22U_0603_6.3V6M

+VCC_GT

+VCC_GT <14,52,54>

1

PC1309

PC1310

2

@

22U_0603_6.3V6M

1

PC1315

PC1318

2

22U_0603_6.3V6M

+VCC_CORE

+VCC_CORE <14,52,54>

1

PC1359

PC1360

2

22U_0603_6.3V6M

1

PC2120

2

@

22U_0603_6.3V6M

1

PC1398

2

@

22U_0603_6.3V6M

@

22U_0603_6.3V6M

1

PC1369

PC1370

2

@

22U_0603_6.3V6M

1

PC2122

PC2121

2

@

22U_0603_6.3V6M

+VCC_SA <12,52,54>

1

Title

VCC_CORE_PowerStage

Size

Document Number Re v

53 60Wednesday, May 11, 2016

Date: Sheet

2

3

4

Date: Sheet

5

53 60Wednesday, May 11, 2016

v0.2

of

5

Aditya11ttt.com

VCC_CORE Place on CPU Back Side. 22U_0603 * 13 pcs + 1U_0201*35 pcs

4

3

VCC_GT Place on CPU Back Side. 22U_0603 * 13 pcs + 1U_0201*12 pcs

2

2014/12 /25 add 1 pcs 1uF cap for back side, total 13 pcs

1

+VCC_GT+VCC_CORE

D D

C C

B B

1

PC2001

2

22U_0603_6.3V6M

12

PC2021

1U_0201_6.3V6M

12

PC2031

1U_0201_6.3V6M

12

PC2076

1U_0201_6.3V6M

PC2002

PC2022

PC2032

PC2077

22U_0603_6.3V6M

12

1U_0201_6.3V6M

12

1U_0201_6.3V6M

12

1U_0201_6.3V6M

1

PC2003

2

22U_0603_6.3V6M

12

PC2023

1U_0201_6.3V6M

12

PC2033

1U_0201_6.3V6M

12

PC2078

1U_0201_6.3V6M

PC2004

PC2024

PC2034

PC2079

22U_0603_6.3V6M

12

1U_0201_6.3V6M

12

1U_0201_6.3V6M

12

1U_0201_6.3V6M

1

PC2005

PC2025

PC2035

PC2080

2

22U_0603_6.3V6M

12

1U_0201_6.3V6M

12

1U_0201_6.3V6M

12

1U_0201_6.3V6M

PC2006

PC2026

PC2036

PC2081

1

2

22U_0603_6.3V6M

12

1U_0201_6.3V6M

12

1U_0201_6.3V6M

12

1U_0201_6.3V6M

1

2

PC2007

PC2027

PC2037

PC2082

22U_0603_6.3V6M

12

1U_0201_6.3V6M

12

1U_0201_6.3V6M

12

1U_0201_6.3V6M

1

PC2008

2

22U_0603_6.3V6M

12

PC2028

1U_0201_6.3V6M

12

PC2038

1U_0201_6.3V6M

12

PC2083

1U_0201_6.3V6M

PC2009

PC2029

PC2039

PC2084

1

2

22U_0603_6.3V6M

12

1U_0201_6.3V6M

12

1U_0201_6.3V6M

12

1U_0201_6.3V6M

1

PC2010

2

@

22U_0603_6.3V6M

PC2030

1U_0201_6.3V6M

PC2040

1U_0201_6.3V6M

PC2085

1U_0201_6.3V6M

PC2011

22U_0603_6.3V6M

1

PC2012

2

22U_0603_6.3V6M

1

PC2013

22U_0603_6.3V6M

PC2014

2

@

22U_0603_6.3V6M

20150324 add 6 pcs cap for transient test

2

@

1

PC2041

22U_0603_6.3V6M

PC2061

1U_0201_6.3V6M

22U_0603_6.3V6M

1

PC2042

2

22U_0603_6.3V6M

12

PC2062

1U_0201_6.3V6M

1

PC1323

PC1322

2

@

22U_0603_6.3V6M

1

2

12

1

PC1321

2

@

PC2043

22U_0603_6.3V6M

PC2063

1U_0201_6.3V6M

22U_0603_6.3V6M

1

PC2044

2

22U_0603_6.3V6M

12

PC2064

1U_0201_6.3V6M

1

PC1325

PC1324

2

@

22U_0603_6.3V6M

PC2045

22U_0603_6.3V6M

PC2065

1U_0201_6.3V6M

22U_0603_6.3V6M

1

PC2046

2

22U_0603_6.3V6M

12

PC2066

1U_0201_6.3V6M

1

PC1326

2

22U_0603_6.3V6M

1

PC2047

PC2048

2

22U_0603_6.3V6M

12

PC2067

PC2068

1U_0201_6.3V6M

VCC_SA Place on CPU Back Side. 22U_0603 * 4 pcs + 1U_0201 * 7 pcs

PC2049

PC2069

1

2

22U_0603_6.3V6M

12

1U_0201_6.3V6M

PC2050

PC2070

1

2

22U_0603_6.3V6M

12

1U_0201_6.3V6M

PC2051

PC2071

1

2

22U_0603_6.3V6M

12

1U_0201_6.3V6M

PC2052

PC2072

1

2

22U_0603_6.3V6M

1U_0201_6.3V6M

PC2053

22U_0603_6.3V6M

12

PC2073

1U_0201_6.3V6M

+VCC_SA

1

PC2101

PC2102

2

22U_0603_6.3V6M

1

PC2103

PC2104

2

22U_0603_6.3V6M

+VCC_SA

12

PC2087

PC2086

1U_0201_6.3V6M

A A

5

PC2088

12

1U_0201_6.3V6M

PC2089

12

1U_0201_6.3V6M

PC2090

1U_0201_6.3V6M

12

PC2112

1U_0201_6.3V6M

12

PC2113

1U_0201_6.3V6M

12

PC2111

1U_0201_6.3V6M

Security Classification

2015/10/09

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/09

3

Compal Secret Data

Deciphered Date

2018/10/09

2

Compal Electronics, Inc.

Title

VCC_CORE_PROCESSOR DECOUPLING

Size

Document Number Re v

LA-D707P

Wednesday, May 11, 2016

Date : Sheet

PC2114

12

1U_0201_6.3V6M

PC2115

1

12

1U_0201_6.3V6M

PC2116

12

1U_0201_6.3V6M

PC2117

1U_0201_6.3V6M

o f

v0.2

6054

A

Aditya11ttt.com

B

C

D

Confirm HW side

1 1

PJB7

@

2

PRW5

PRW6

DIS@

1M_0402_1%

112

JUMP_43X79

12

DIS@

0.1U_0402_25V6

PCW12

12

PCW3

PCW2

0.1U_0402_25V6

DISEMI@

2200P_0402_50V7K

@DISEMI@

+3VALW

12

PRW8

@

0_0402_5%

12

PRW9

@DIS@

0_0402_5%

The current limit is set to 6A, 9A or 12A when this pin is pull low, floating or pull high.

+19.5VB

DIS@

DGPU_PWR_EN

2 2

EN :H>0.8V ; L<0.4V

EN pin don't floating If have pull down resistor at HW side, please delete PR601.

22K_0402_5%

1 2

+19VB_1.5V

12

PCW5

PCW14

10U_0805_25V6K

DIS@

EN_1.5V

ILMT_1.5V

+3VALW

DIS@

2

3

4

5

7

8

18

11

13

15

12

PCW13

DIS@

1U_0402_6.3V6K

VRAM_PG<56>

PUW1

IN

GND

EN

ILMT

BYP

SY8286RAC_QFN20_3X3

PG

BS

LX

FB

VCC

NC

PAD

VRAM_PG

9

1

6

19

20

14

17

10

12

16

21

+3VS

LX_1.5V

FB_1.5V

LDO3V_1.5V

12

@DIS@

100K_0402_5%

PRW3

PRW1

@

0_0402_5%

1 2

12

DIS@

2.2U_0402_6.3V6M

PCW11

BST_1.5V_RBST_1.5V

PCW4

DIS@

0.1U_0201_10V6K

1 2

PRW2

@DISEMI@

4.7_1206_5%

1 2

SNUB_1.5V

@DISEMI@

680P_0603_50V7K

1 2

(Common Part SH00000YE00)

PLW1

DIS@

3

4

1UH_11A_20%_7X7X3_M

2

1

FB=0.6V

R1

R2

12

PRW4

DIS@

12

PRW7

DIS@

Vout=0.6V* (1+R1/R2) =0.6*(1+(15K(PRW4)/10K(PRW7)))

PCW1

15K_0402_1%

10K_0402_1%

Vout=1.5V

12

PCW6

DIS@

330P_0402_50V7K

+1.5VRAMP

12

PCW7

DIS@

22U_0603_6.3V6M

PCW9

PCW8

DIS@

22U_0603_6.3V6M

DIS@

22U_0603_6.3V6M

PJW2

@

JUMP_43X118

112

PCW10

DIS@

22U_0603_6.3V6M

2

+1.5VRAMP

+1.5VS_VGA

3 3

4 4

Security Classification

A

B

Security Classification

2015/10/09

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/09

Compal Secret Data

Deciphered Date

C

2018/10/09

Compal Electronics, Inc.

Title

1.5VS_VGA(SY8286)

Size

Document Number Re v

LA-D707P

Date : Sheet

Wednesday, May 11, 2016

D

v0.2

6055

o f

A

Aditya11ttt.com

VGA_VCCSENSE<37>VGA_VSSSENSE<37>

12

PRV28

@

0_0402_5%

1 1

DIS@

270P_0402_50V7K

+VGA_VDDIO is pull high at HW Side

2 2

PRV51

DIS@

4.87K_0402_1%

1 2

12

PHV2

DIS@

100K_0402_1%_B25/50 4250K

PHV2 is next to PLV2

3 3

VGA_VREF

PCV98

DIS@

0.47U_0402_6.3V6K

+VGA_VDDIO<37>

VGA_PWRGD<36>

12

PRV47

DIS@

12

DIS@

21.5K_0402_1%

12

VGA_IMON

PRV43

DIS@

4.7K_0402_1%

GPU_SVC<37>

GPU_SVD<37>

GPU_SVT<37>

28.7K_0402_1%

PRV55

DIS@

11K_0402_1%

DIS@

64.9K_0402_1%

VGA_SET1 VGA_SET2

DIS@

8.66K_0402_1%

Vset1=5*2.8k/(1k+124k+2.8k)=110mV

1 2

PCV87

12

@DIS@

.1U_0402_16V7K

PRV73

PRV71

PRV75

PRV29

@

0_0402_5%

DIS@

10K_0402_1%

1 2

470P_0402_50V7K

PCV93

DIS@

2.2U_0603_10V7K

1 2

12

PCV99

VGA_VCC

1 2

31.6K_0402_1%

1 2

DIS@

1 2

DIS@

1K_0402_1%

DIS@

470_0402_1%

OCP_TDC (Respect to OCP_ SPIKE): 60%

DVID Compensation: 0

RSET:100%

DVID Boost Compensation:22.5mV

Vset2=5*470/(1K+31.6k+470)=71mV

4 4

QRTH (for VDD) :Disable

B

PRV33

PCV88

VGA_VREF

PRV45 0_0402_5%@

1 2

PRV48 0_0402_5%@

1 2

PRV50 0_0402_5%@

VGA_SET1

VGA_SET2

GPU_PROCHOT#<26,37>

Pull high at HW side

PRV74

PRV72

PRV76

LL=1m ohm

PRV34

DIS@

200K_0402_1%

1 2

PCV89

DIS@

68P_0402_50V8J

1 2

VGA_FB

VGA_COMP

+5VS

11

12

10

13

14

RGND

15

IMON

16

V064

17

IMONA

18

VDDIO

19

PWROK

20

SVC

21

SVD

22

SVT

23

OFS

24

OFSA

25

SET1

26

SET2

APU_core TDC 31A(1H1L) *2phase Peak Current 46.5A FSW=300kHz DCR 0.98mohm +/-5%

9

FB

VSEN

COMP

ISEN3N

RT8880CGQW_WQFN52_6X6

OCP_L27VCC28IBIAS29COMPA30FBA31VSENA32ISENA2P33ISENA2N34ISENA1N35ISENA1P36EN37PGOODA

VGA_VCC

VGA_IBIAS

12

DIS@

100K_0402_1%

ISEN3P

PRV60

DIS@

C

PRV37

DIS@

124K_0402_1%

1 2

+5VS

VGA_UGATE2

VGA_BOOT2

7

VGA_ISEN1N

PUV1

VGA_TONSET

VGA_ISEN2N

VGA_ISEN2P

4

2

3

5

6

ISEN2N

ISEN1N

+5VS

1

PWM3

GND

BOOT2

ISEN2P

UGATE2

TONSET

PHASE2

LGATE2

PVCC

LGATE1

PHASE1

UGATE1

BOOT1

LGATEA1

PHASEA1

UGATEA1

BOOTA1

PWMA2

TONSETA

PGOOD

38

39

1 2

PRV78

@DIS@

0_0402_5%

1 2

PRV79

@

0_0402_5%

12

PCV102

0.1U_0402_25V6

@DIS@

VGA_ISEN1P

8

ISEN1P

VGA_BOOT1

53

VGA_PHASE2VGA_PHASE2

52

VGA_LGATE2

51

VGA_PVCC

50

VGA_LGATE1

49

VGA_PHASE1

48

VGA_UGATE1

47

VGA_BOOT1

46

45

44

43

42

41

40

GPU_PGD<10>

1 2

PRV59

DIS@

10K_0402_1%

VGA_BOOT2

GPU_B+

FSW=400kHz

VGA_PHASE1

PRV10

DIS@

2.2_0603_1%

1 2

+5VS

+3VS

DGPU_PWR_EN <10,26,38,55>

VRAM_PG <55>

DIS@

2.2_0603_1%

1 2

VGA_UGATE1

0.22U_0603_25V7K

VGA_PVCC

VGA_VCC

12

PCV94

DIS@

2.2U_0603_10V7K

PRV27

VGA_BOOT1-1

DIS@

12

PRV61

DIS@

10K_0402_1%

1 2

VGA_BOOT2-1

PCV9

PCV95

DIS@

1 2

2.2U_0603_10V7K

PRV6

@

0_0603_5%

1 2

DIS@

AON6794_DFN5X6-8-5

VGA_LGATE1

DIS@

PRV41

2.2_0402_1%

1 2

PRV42

2.2_0603_5%

DIS@

+3VS

VGA_UGATE2

VGA_PHASE2

1 2

DIS@

0.22U_0603_25V7K

PQV20

PCV26

D

aximum Current: 28A(TDC)

M

load line:1m ohm

slew rate:50mV/uS

5

PQV1

4

DIS@

123

MDU1516URH_POWERDFN56-8-5

5

4

+5VS

PRV67

@

0_0603_5%

1 2

PQV22

DIS@

AON6794_DFN5X6-8-5

VGA_LGATE2

PRV9

12

@DISEMI@

VGA_SNB_APU1

12

123

PCV12

@DISEMI@

VGA_ISEN1N

5

4

5

4

PCV2

DIS@

10U_0805_25V6K

4.7_1206_5%

680P_0603_50V7K

VGA_ISEN1P

PQV21

DIS@

123

MDU1516URH_POWERDFN56-8-5

123

GPU_B+

12

PCV3

DIS@

10U_0805_25V6K

PRV44

DIS@

3.4K_0603_1%

1 2

DIS@

910_0402_1%

1 2

PRV70

12

4.7_1206_5%

@DISEMI@

VGA_SNB_APU2

12

PCV107

680P_0603_50V7K

@DISEMI@

0.1U_0402_25V6

PLV2

DIS@

0.22UH_24A_20%_ 7X7X4_M

1

2

1 2

PCV96

DIS@

.1U_0402_16V7K

PRV53

12

@DIS@

0.1U_0402_25V6

GPU_B+

12

PCV100

PCV103

DIS@

10U_0805_25V6K

PRV69

DIS@

3.4K_0603_1%

1 2

VGA_ISEN2P

VGA_ISEN2N

E

PJB8

@

2

112

12

PCV91

4

+VGA_CORE

3

VGA_ISEN1N-1

PCV97

APU_core Peak FSW=400kHz DCR 0.98mohm +/-5% H/S Rds(on) :8.3mohm , 10mohm L/S Rds(on) :2.3mohm , 2.8mohm

12

DIS@

0.22UH_24A_20%_ 7X7X4_M

1

2

1 2

DIS@

.1U_0402_16V7K

PRV77

DIS@

910_0402_1%

1 2

JUMP_43X79

12

PCV4

@DISEMI@

2200P_0402_50V7K

Maximum Current: 28A(TDC)

load line:1m ohm

slew rate:50mV/uS

Current 46.5A

PLV3

4

+VGA_CORE

3

PCV106

VGA_ISEN2N-1

12

PCV108

@DIS@

0.1U_0402_25V6

1

+

DIS@

100U_25V_NC_6.3X6

2

+19.5VB

PCV1

DVID Compensation : 0

NB OLL Setting :0

Security Classification

OCPTRGDELAY (for VDD/VDDNB) : 40ms

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2015/10/09 2018/10/09

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size

Date: Sheet

Compal Electronics, Inc.

VGA_CORE(RT8880A)

Document Number Re v

56 60Wednesday, May 11, 2016

E

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+VGA_CORE

4

3

2

1

PCV51

1

+

DIS@

560U_2.5V_M

2

PCV52

1

+

DIS@

560U_2.5V_M

2

PCV53

1

+

DIS@

560U_2.5V_M

D D

2

+VGA_CORE

12

DIS@

PCV54

2.2U_0402_6.3V6M

12

DIS@

PCV55

2.2U_0402_6.3V6M

12

DIS@

PCV56

2.2U_0402_6.3V6M

12

DIS@

PCV57

2.2U_0402_6.3V6M

12

DIS@

PCV58

2.2U_0402_6.3V6M

12

DIS@

PCV59

2.2U_0402_6.3V6M

12

DIS@

PCV60

2.2U_0402_6.3V6M

12

DIS@

PCV61

2.2U_0402_6.3V6M

+VGA_CORE

12

C C

DIS@

PCV62

2.2U_0402_6.3V6M

12

DIS@

PCV63

2.2U_0402_6.3V6M

12

DIS@

PCV64

2.2U_0402_6.3V6M

12

DIS@

PCV65

2.2U_0402_6.3V6M

12

DIS@

PCV66

2.2U_0402_6.3V6M

12

DIS@

PCV67

2.2U_0402_6.3V6M

12

DIS@

PCV68

2.2U_0402_6.3V6M

12

DIS@

PCV69

2.2U_0402_6.3V6M

+VGA_CORE

12

DIS@

PCV70 10U_0603_6.3V6M

12

DIS@

PCV71 10U_0603_6.3V6M

12

DIS@

PCV72 10U_0603_6.3V6M

12

DIS@

PCV73 10U_0603_6.3V6M

12

DIS@

PCV74 10U_0603_6.3V6M

12

DIS@

PCV75 10U_0603_6.3V6M

12

DIS@

PCV76 10U_0603_6.3V6M

12

DIS@

PCV84 10U_0603_6.3V6M

560u X 3

2.2u X 16 10u X 8 1u X 3

0.1u X 2

B B

+VGA_CORE

12

DIS@

PCV77 1U_0402_6.3V6K

12

DIS@

PCV78 1U_0402_6.3V6K

12

DIS@

PCV79 1U_0402_6.3V6K

12

@DIS@

PCV80 1U_0402_6.3V6K

+VGA_CORE +VGA_CORE

12

DIS@

PCV81

A A

0.1U_0402_10V7K

12

DIS@

PCV82

0.1U_0402_10V7K

12

@DIS@

PCV83

0.1U_0402_10V7K

12

@DIS@

PCV85 22U_0603_6.3V6M

Security Classification

2015/10/09

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/09

Compal Secret Data

Deciphered Date

2018/10/09

Compal Electronics, Inc.

Title

VGA_CORE_CHIP DECOUPLING

Size

Document Number R ev

LA-D707P

Wednesday, May 11, 2016

Date : Sheet

v0.2

6057

o f

5

4

3

2

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AC Adapter 19.5V

P.45

D D

Charge

DC Battery 3S1P 4S1P

C C

Charger BQ24725

P.47

Discharge

P.46

+19.5VB

+2.5V_PG

SM_PG_CTRL

4

3

RT8243AZQW

ECON

EN

Vin

Vout

+3VALW

PCH_PWR_EN

Vin

EN

SY8032A

DC/DC (+5VALW/+3VALW)

Vout

PGOOD

P.48

Vin

DDR4 RT8027P

EN S5

EN S3

Vin

+1.0V_PRIM

+1.8V_PG +1.0V_VS_PG_PWR

SY8286

EN

PGOOD

+3VALW

PM_SLP_S4#

SPOK

Vout

P.49

Vout

P.50

Vin

SY8032A

EN

+0.6V_0.6VS

+1.2V_VDDQ

DDR_PWROK

+1.0V_PRIM

Vout

PGOOD

P.51

Vout

PGOOD

P.49

+1.8V_PRIM

+1.8V_PG

+2.5V

+2.5V_PG

2

CPU DC/DC NCP81206

INPUTS OUTPUTS

B+

SYSTEM DC/DC RT8243AZQW

INPUTS OUTPUTS

B+

SYSTEM DC/DC RT8207P / 8032

INPUTS OUTPUTS

B+

SYSTEM DC/DC SY8286

INPUTS OUTPUTS

SYSTEM DC/DC SY8032A

INPUTS

+3VALW

SYSTEM DC/DC RT8880

INPUTS OUTPUTS

B+

SYSTEM DC/DC S

Y8286

INPUTS OUTPUTS

B+

VCC_SA VCC_GT VCC_VORE

+5VALW/+3VALW

+1.2V_VDDQ

+0.6V_0.6VS

+1.0V_PRIMB+

OUTPUTS

+VGA_CORE

+1.5VS_VGA

1

52~54

48

49

+2.5V

50

51

+1.8V_PRIM

56~57

55

Vin

B B

VR_ON

NCP81206 DC/DC

VR_ON

(CPU_CORE)

Vin

RT8880

Vout

PGOOD

P.52,53

Vout

+VCC_CORE

+VCC_GT

+VCC_SA

VR_PWRGD

+VGA_CORE

DC/DC (VGA_CORE)

DGPU_PWR_EN

A A

DGPU_PWR_EN

EN

Vin

EN

SY8286 DC/DC (VGA_RAM)

P.56

PGOOD

Vout

PGOOD

P.55

GPU_PGD

+1.5VS_VGA

VRAM_PG

5

4

3

2

1

5

Aditya11ttt.com

4

3

2

1

Item

D D

SKL_SI

C C

Page# Title

1 52

2 50

3 55

4 48

5 55

6 56

7 56

8 47

9 48

10 49

11 50

12 53

13 55

14 56

15 55

16 53

Change Value

Change part number

Add Jump

Add Net

pop to unpop unpop to pop

Add Net and R

Change jump to

ISN choke

colay bead

Change jump to Bead

colay bead

Change R Value

Change C unpop to pop

Change Common part

Date

11/06

11/18

11/24

11/6

Request Owner

Power

EE

EMI

EE

Power

Issue Description

(Set VR prochot# from 110C to 120C)

Change from 5x5 choke to 7x7 follow Candy design

For easy debug

For VGA CORE sequence and VID error issue

EMI ISN issue

EMI power noise issue

HW f i ne t une VRA M po wer sequence

(Change to Common part)

Solution Description

Change PR1115 and PR1125 Value 0 ohm to 1.07K ohm

Change PL602 part number from SH00000Z200 to SH00000YE00

Change PLW1 part number from SH00000Z200 to SH00000YE00

+3VL and +VL add Jump

Delete PG pin test point VRAM_PG

Add Net VRAM_PG

PRV61 from unpop to pop PRV78 and PCV102 from pop to unpop

Add Net VRAM_PG Add PRV79

Delete jump PJB9

Add ISN choke PL201

Add Bead footprint PL7

Add Bead footprint PL10

Delete jump PJB3

Add Bead PL1207

Delete jump PJB5

Add Bead PL1201 PL1202

Add Bead footprint PL1208

Add Bead footprint PL1209 and PL1210

Change PRW5 value from 0 ohm to 22K ohm

Change PCW12 from unpop to pop (VGA sequence)

Change PC1331 PC1383 PC1390 from SGA20331E10 to SGA00009S00

Rev.

B B

SKL_PV

A A

Title

Power_PIR(SI)

Size

Document Number Re v

Document Number Re v LA-D707P v0.2

C

LA-D707P v0.2

C

LA-D707P v0.2

5

4

3

2

C

Date: Sheet

1

59 60Wednesday, May 11, 2016

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P. I. R. List

D D

KBL_SI

KBL_PV

C C

B B

A A

Title

Power_PIR(PV)

Size

Document Number Re v

Document Number Re v LA-D707P v0.2

C

LA-D707P v0.2

C

LA-D707P v0.2

C

Date: Sheet

5

Date: Sheet

4

3

2

60 60Wednesday, May 11, 2016

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Compal LA-e811p Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual