Compal LA-E791P Schematic

A

1 1

B

C D

E

Compal Confidential

CSL50 Schematics Document

2 2

Sky Lake-U(2+2)-DDR4 SODIMMx2

GPU AMD R17M-M1-30

R17M-M2-50

(DDR3L 4GB)

3 3

Date : 2018-01-08 REV :1.0

4 4

SecurityClassification

IssuedDate

THIS SHEET OF ENGINEERING DRAW ING IS TH E PROPRIETA RY PRO PERTY OF C OMPAL EL ECT RONICS, INC. AND CONTAINS CONFIDENSTiIzAeL
AND TRA DE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPET ENT DIVISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZE D BY CO MPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMA TIO N IT CONTAINS

A

B

MAY BE U SED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONS ENT OF COMPAL ELEC TRO NICS, INC.

2015/10/22 2017/10/22

C D

Compal Secret Data

DecipheredDate

Title

Document Number

Custom

Date: Monday,January08, 2018 Sheet

Compal Electronics, Inc.

Cover Page

CSL50 LA-E791P

E

1 of 59

Rev

v0.3

A

VRAM
DDR3L x 8PCS
256Mbx16(4GB)

1 1

JLAN

RJ45CONN

P.29

RTL8111HSH-CG

B

AMD
R17M-M1-30
R17M-M2-50

JEDP

eDPCONN

HDMICONN

JHDMI

LAN

UV1 UC1

PCIex4 Port
#1~#4 PCIe3.
0:8Gb/s

Sky Lake-U22
Kaby Lake-RU22
KabyLake-RU42

P.27

P.28

DDI x4Lane Port1

UL1

P.29

PCIex1 Port#5

PCIe Gen1 Only:2.5Gb/s

eDPx2Lane

C

Dual Channel Interleaved
DDR4 2133MHz1.2V

SATA3.0

SATA3.0

PCIe 3.0:8Gb/s

Port0

Port1

PCIe x2

Port#11~#12

D

DDR4-SO-DIMM X2

JHDD

P.30

SATAODD

(KeyM)

M.2 SSD

*need supported Intel Optane (3D Xpoint)

NVMe

JODD

P.30

JSSD

P.19

ChA:JDIIII MM1(REV)
ChB:JDIIII MM2(STD)

P.17~18

(sub board)

(sub board)

(sub board)

2.5" SATA HDD

M.2 SATA SSD

eMMC

E

*sub board

LS-G072P
DA4002LZ000

*sub board
LS-G074P
DA6001WR00S

*sub board
LS-G075P
DA6001WS00S

SATA3.0 Port2

JKBL

P.34

JWLAN

P.30

ECENE

KB9022QD

JKB

Int.KBD

P.34 P.34

PCIex1 Port#6

PCIe Gen1 Only:2.5Gb/s

UK1

33MHz

P.33

PS2

JTP

TouchPad

*sub board
LS-G073PR01
DA4002M0000

SMBus

SPI
50MHz

UC2

1356PBGA

SKL-U 15W2+2

LPC

KBL-U 15W2+2

2 2

NGFFWLAN+BT
(Key E)

PUB1

Charger

P.47

3 3

Battery

dGPU

PJPB1

P.46

UV1

P.22

Thermalsensor

UC3

G753T11U

Fan

75x70

P.10

P.38

SMBus1

SMBus2

JFAN

KBlight

SPIROM
8MBytes

4

SLB9670VQ2.0

P.07

UT1

TPM

P.35

USB3.0

5Gb/s

USB2.0
480Mb/s

HDA 24MHz

Port1

USB3.0port

Port2

USB3.0port

Port3

USB2.0Port

Port4

CardReader

AK6485RB 63-GLF-GR

(sub board)

Port5

Camera

Port6

Bluetooth

Port7

TouchScreen

UA1

HDA Aduiocodec

ALC3247-CG

P.32

JUSB1

Port1

P.30

JUSB2

P.31

Port2

JIO

P.31

*sub board
LS-G071PR01
DA6001WJ000

P.29

JEDP

P.27

JWLAN

P.30

JEDP

P.27

Internal SPK

ComboJack

JSPK

P.32

JHP

P.32

4

SecurityClassification

IssuedDate

THIS SH E ET O F E NG IN EE R IN G D RA WIN G IS TH E PR OP RIE TA RY PR O PE RTY O F C OM PA L E LECT RONI CS , INC . A ND C ONTA INS CONFIDENTSI
AN D TR AD E SE CR E T INF ORM A TI ON . TH IS SHE ET M AY N OT BE TR A N SF ER E D F RO M TH E CU STO DY OF TH E CO M PE TE NT DIV IS ION OF R &D

DEP ARTM E NT E XC E PT A S AU THORI ZE D B Y CO M PA L ELE CTRO NICS , I NC. NE ITHE R TH IS SH E ET N OR TH E IN FO RM A TIO N IT CON TA INS

A

B

MA Y BE U S ED BY OR D IS CLOS E D TO A N Y TH IRD PA R TY W ITH O UT P RIO R W R ITTE N C ON S EN T OF C O MP AL ELE CTRO NICS , IN C.

C

2017/08/24 2018/08/24

Compal Secret Data

DecipheredDate

Title

iiiAzeLDocument Number

Custom

D

Compal Electronics, Inc.

Block Diagrams

CSL50 LA-E791P

E

Rev

v0.3

of 59Date: Monday, January 08, 2018 Sheet 2

5

4

3

2

1

AC

Adapter 19.5V

P.45

D D

Charge

Charger
BQ24725

+19.5VB

EC_ON

P.47

DC

Battery

Discharge

P.46

+2.5V_PG

C C

SM_PG_CTRL

+1.8V_PG

+5VALW/+3VALW
(SY8288C/SY8286B)

Vout

EN

Vout

Vin

PGOOD

P.48

+1.2V/+0.6VS

(G5616B)

Vin

EN S5

EN S3

+1.0V_PRIM

Vin

(SY8286R)

EN

Vout

Vout

P.49

Vout

PGOOD

P.50

+3VALW

+5VALW

SPOK

+0.6V_0.6VS

+1.2V_VDDQ

+1.0V_PRIM

+1.0V_VS_PG_PWR

+3VALW

PCH_PWR_EN

+3VALW

PM_SLP_S4#

Vin

EN

Vin

EN

G5719

G5719

Vout

PGOOD

P.51

Vout

PGOOD

P.49

+1.8V_PRIM

+1.8V_PG

+2.5V

+2.5V_PG

CPU_CORE

Vin

(RT3602AE)

VR_ON

B B

EN

Vout

Vout

Vout

PGOOD

+VCC_CORE

+VCC_GT

+VCC_SA

VR_PWRGD

P.52,53

+VGA_CORE
(RT8812A)

Vin

VRAM_PG

EN

+1.35VS_VGA

Vin

A A

DGPU_PWR_EN

(SY8286R)

EN

Vout

PGOOD

P.56

Vout

PGOOD

P.55

5

4

+VGA_CORE

GPU_PGD

+1.35VS_VGA

VRAM_PG

Security Classification

Issued Date

THIS S HE E T OF E NGINEERIN G DRA W ING IS THE P ROP RIE TA RY P ROP E RTY OF CO M P A L ELECTRONICS,,, INC. A ND CONTAINS CONFIDENTSIIiAzL
AND TRA DE S EC RET INFO RM AT ION. THIS SHE E T MA Y NOT BE TR A NSFE RED F ROM THE CUSTOD Y OF THE COM P ETE NT D IVISION OF R&D
DEP ARTM E NT E XCE PT AS A UTHOR IZE D B Y C OMP A L ELE CTR ONICS , INC. NEIIITHER THIS SHE ET NOR THE INFO RM A TION IIIT CONTAINS
MA Y BE USE D BY OR DIS CLOS ED TO ANY THIRD P A RTY W ITHOU T P RIO R W RIT TE N C ONS ENT OF COM P AL E LECT RONI CS, IIINC...

3

2016/09/01 2019/09/01

Compal SecretData

Deciphered Date

2

Compal Electronics, Inc.

Title

Power BlockDiagram

e Document Number

CSL50 LA-E791P

Friday,,, January 05,,, 2018

Dattte:

Rev

58

Sheettt

1

v0.3

59

of

A

Power rail Control (EC) Source (CPU)
+RTCVCC X X
VIN X X
BATT+ X X
B+ X X
+VL X X
+3VL X X
+5VALW EC_ON X
+3VALW EC_ON X
+3VALW _EC EC_ON X

1 1

+3V_PCH PCH_PWR_EN X
+1.2V_VDDQ SYSON PM_SLP_S5#/PM_SLP_S4#
+5VS SUSP# PM_SLP_S3#
+3VS SUSP# PM_SLP_S3#
+1.5VS SUSP# PM_SLP_S3#
+1.05VS SUSP# PM_SLP_S3#
+0.6V_0.6VS SUSP#
+VCC_CORE X VR12.5_VR_ON

BOM Structure Table (1/2)

Function

DGPU SKU
UMA SKU UMA@

TPM TPM@

2 2

R_i3_7020U_QN96@

UC1

R_SI_i3_7020U_QN96 Y02.3G

SA0000BLD00

S IC A32 FJ8067703282620 QN96 Y0 2S.3GICA32 FJ8067703282227 QP8K Y02.2G
R_i7_8550U_QNBF@ U_i3_7020U_QNZU@

UC1 UC1

R_SI_i7_8550U_QNBF Y01.8G

SA0000AWC10 SA0000BLH00

S IC A32 FJ8067703281816 QNBF Y0 1S8GCAI. 32 FJ8067702739769 QNZU H02.3G

UC1

3 3

CPU

Stuff Un-Stuff

PX@

R_i3_8130U_QP8K@

UC1

R_SI_i3-8130U_QP8KY0 2.2G

SA0000BKN10

U_SI_i3-7020U_QNZU H02.3G

SMBCLK

R7

SMBDATA

R8

SML0CLK

R9

SML0DATA

W2

SML1CLK

W3

SML1DATA

V3

U6
U7

+3V_PRIM

@

+3V_PRIM

2N7002

+3V_PRIM

2N7002

+3VS

EC_SMB_CK2
EC_SMB_DA2

R=1K

+3V_PRIM

R=499

+3V_PRIM+3VS +3VS_DGPU_AON

R=1K R=2.2K

2N7002

i3_7100U_R1@

i3_7100U

SA0000A38H0
S IC FJ8067702739738 SR343 H0 2.4GBGA

U_i5_7200U_SR342@

U_SI_i5-7200U_SR342H02.5G

SA0000A37H0

S IC FJ8067702739739 SR342 H0 2.5GBGA

U_i7_7500U_SR341@ ZZZ

U_SI_i7-7500U_SR341H02.7G

SA0000A34F0

S IC FJ8067702739740 SR341 H0 2.7GBGA

R_i5_8250U_QNEF@

R_SI_i5_8250U_QNEFY0 1.6G i5_8250U

SA0000AWB10 SA0000AWB30

S IC FJ8067703282221 SR3LA Y0 1.6G FCBGA S IC FJ8067703282221 SR3LA Y0 1.6GA32!

R_i7_8550U_SR3LC@

R_SI_i7-8550U_SR3LC Y01.8G

SA0000AWC20

S IC FJ8067703281816 SR3LC Y0 1.8G FCBGA S IC FJ8067703281816 SR3LC Y0 1.8G A32!

+3VS

R=10K

+3VALW

R=10K

2N7002

B

SOC SMBUS Address Table

SOC_SMBUS NetName PowerRail Device Address (7bit)

SMBCLK
SMBDATA

UC1

UC1

UC1

UC1

UC1

PCH_SMBCLK
PCH_SMBDATA

TP_SMBCLK
TP_SMBDAT

+3VS_DGPU_AON

R=2.2K

PX@

I2CS_SCL
I2CS_SDA

+3V_PRIM

i3_7100U_R3@

UC1

i3_7100U

SA0000A38J0
S IC FJ8067702739738SR343 H02.4G A32!

i5_7200U_R3@

i5_7200U

SA0000A37J0
S IC FJ8067702739739 SR342 H0 2.5GA32!

i7_7500U_R3@

UC1

i7_7500U

SA0000A34H0
S IC FJ8067702739740SR341 H02.7G A32!

i5_8250U_R3@

UC1

i7_8550U_R3@

UC1

i7_8550U

SA0000AWC30

SO-DIMMA

SO-DIMMB

TouchPad

DGPU

DIMM1 0x50 0xA0 0xA1
DIMM2 0x52 0xA4 0xA5

TouchPAD

KBLU_2G@

DA6001WM000

PCB 29M LA-G07AP REV0 MB 3 PCB 29L LA-G07CP REV0 MB3

DAZ_U2G@
DAZ23T00600

KBLU_UMA@

DA6001YA000 DA6001YB000

PCB 29M LA-G07DP REV0 M/B 3 PCB 29L LA-E791PREV0 M/B 3

C

Address(8bit)
Write Read

0x2C 0x58 0x59

MX110@

UV1

N16V-GMR1-S-A2

SA00009IT00

S IC N16V-GMR1-S-A2 BGA595P

ZZZ

2G MicronUC1

M2G_R1@
X7674032L01

ZZZ

2G Hynix

H2G_R1@
X7674032L04

ZZZ

2G Samsu ng

S2G_R1@
X7674032L05

DAX

KBLU-2G

ZZZ

DAZ_U2G

DAX

KBLU-UMA

M2G_R3@
X7674032L06

H2G_R3@
X7674032L07

2G Samsu ng

S2G_R3@
X7674032L08

ZZZ

DAZ_R2G

DAZ_R2G@
DAZ23T00500

ZZZ

2G Micron

ZZZ

2G Hynix

ZZZ

KBLR_2G@

DA6001WI000

KBLR-UMA

KBLR_UMA@

KBLR-2G

DAX

MX130@

UV1

N16S-GTR-S-A2

SA00009FP00

S IC N16S-GTR-S-A2 BGA 595PGPU

ZZZ

4G Micron

M4G_R1@
X7674032L26

ZZZ

4G Hynix

H4G_R1@
X7674032L25

ZZZ

4G Samsu ng

S4G_R1@
X7674032L27

DAX

ZZZ

4G Micron

M4G_R3@
X7674032L29

4G Hynix

H4G_R3@
X7674032L28

ZZZ

4G Samsu ng

S4G_R3@
X7674032L30

DAX

KBLU-4G

KBLU_4G@
DA8001EH000

ZZZ

DAZ_U4G

DAZ_U4G@
DAZ23T00600

Part Number Description

RO0000002HM HDMI W/Logo:RO0000002HM

RO0000003HM

DAX

KBLR-4G

KBLR_4G@
DA8001EI000

ZZZ

DAZ_R4G

DAZ_R4G@
DAZ23T00500

D

EC SMBUS Address Table

(TBC)

EC_SMBUSPort PowerRail Device Address (7bit)

SMBUS Port1 +3VL_EC

BAT 0x16

CHGR 0x12

dGPU

SMBUS Port2 +3VS

Thermal
Sensor

0x90

PCH

Power State

STATE

SIGNAL

SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

S0 (FullON) HIGH HIGH HIGH ON ON ON ON
S3 (Suspend toRAM) LOW HIGH HIGH ON ON OFF OFF
S4 (Suspend toDisk)
S5 (SoftOFF)

ROYALTY HDMI W/LOGO45@

ZZZ

EMC for EE

X4E@

X4EABB32L01

SMT EMC FOR EE AG07CCSL50

LOW LOW HIGH ON OFF OFF OFF

LOW LOW LOW ON OFF OFF OFF

<USB2.0 port>

USB2.0port DESTINATION

1 USB3.0Type-C
2 USB2.0/USB3.0
3 USB2.0/USB3.0
4 BT
5 HD/IR_1/IR_2Camera
6 IR_2Camera
7 CardReader

8 X
9 X

10 X

<PCI-E,SATA,USB3.0/CLK>

2
3

62

DESTINATION

USB3.0Type-C

USB3.0Type-C
USB2.0/USB3.0
USB2.0/USB3.0

GPU(DISonly)
GPU(DISonly)

GPU(DISonly)

GPU(DISonly)

LAN

WLAN

HDD
ODD CLK3

X
X

NVMe x2

SATASSD

Lane# PCI-E SATA USB3.0

1 1

2
3

4 4
5 1 5

6
7

3

8

4

9

5

10

6

11

7

0

12
13
14
15
16

1a

8

10

1191b*

12

2

E

CLK

X
X
X
X

CLK0

CLK1
CLK2

X

X
X

CLK4

X

X

U9
U8

UK1:+3VALW_EC(+3VL)

4 4

EC

EC_SMB_CK2

EC_SMB_DA2

79
80

EC_SMB_CK1

77

EC_SMB_DA1

78

A

+3V_SMBUS

R=2.2K

R=0

R=100

GSEN_I2DAT

GSEN_I2CLK

Thermal Sensor:G753T11U

Address : 0x48

G-Sensor
HP2DC

BAT

Charger

B

Security C lassi fication

Issued Date

THI S S HEE T O F ENGIINE ERIING D RAW ING IS THE P ROP RI ETAR Y P RO PE RTY O F CO MPAL E LE CTR O NI CS, INC . AND CO NTAI NS CONFIDENTSSIAizL
AND TRAD E SEC RE T I NFO RMATI O N. THI S SHE ET MAY NO T BE TR ANSF ER ED FR OM THE C USTO DY OF THE CO MPE TENT DIVISION OF R&D
DEP ARTME NT E XCE PT AS AUTHO RI ZE D BY COMP AL EL EC TRO NIC S, I NC. NE ITHE R THI S S HEE T NO R THE I NF OR MATI ON IT CO NTAI NS

C

MAY BE USE D BY OR DIS CLO SED TO ANY THI RD PAR TY W I THO UT PRI OR WR ITTE N C ONS ENT OF CO MPAL E LE CTR ONI CS , I NC.

2016/12/15

Compal SecretData

Deciphered Date

D

2019/12/15

Title

e Document Number

Custom

Compal Electronics,Inc.

NotesList

LA-G07DP(KBL-U_UMA_v60.L

Sheet 3 of 59Date: Friday, January05,2018

E

Rev

3

)

[Diner-PWR Sequence_SKL-U22_DDR3L_Volume_NON CS]

5

4

3

2

1

+3VL_RTC

SOC_RTCRST#

G3->S0

tPCH01_Min : 9 ms

S0->S3/DS3

S0/DS3->S0

+19VB
+3VLP/+5VLP

D D

EC_ON
+5VALW/+3VALW /+3VALW_DSW
PM_BATLOW#

tPCH04_Min : 9 ms

Pull-up to DSW well if not im plemen ted.

PCH_PWR_EN (SLP_SUS#)
+3V_PRIM
+1.8V_PRIM
EXT_PW R_GATE#

+1.0V_MPHYPLL

+1.0V_PRIM_CORE

+1.0V_PRIM

tPCH06_Min : 200 us

tPCH34_Max : 20 ms

SUSACK#

PCH_DPWRO K

EC_RSMRST#

AC_PRESENT

C C

ON/OFF

PBTN_OUT #

Minimum dur ation of PWRBT N# asser tion = 16mS. PW RBTN# can assert before or after RSMRST#

PM_SLP_S5#

ESPI_RST#

If EXT_PW R_GATE# Toffmin is too small, Pwr
gate may choose to compl etely i gnore it

tPCH02_Min : 10 ms

tPCH03_Min : 10 ms

tPLT02_Min : 0 ms Max : 90 ms

tPCH18_Min : 90 us

PM_SLP_S4#

SYSON

+1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC

PM_SLP_S3#

SUSP#

+1.0VS_VCCSTG

+1.0VS_VCCIO

+5VS/+3VS/+1.5VS/+1.05VS

B B

EC_VCCST_PG

VR_ON

SM_PG_CTRL

+0.675VS_VTT

+VCC_SA

tCPU04 Min : 100 ns

tCPU10 Min : 1 ms

T4 = Min : 20ms Max : 3 0ms(EC Control)

tCPU19 Max : 100 ns

tCPU18 Max : 35us

tCPU09 Min : 1 ms

+VCC_CORE

+VCC_GT

VR_PWRG D

PCH_PWRO K

tCPU16 Min : 0 ns

H_CPUPWRGD
SYS_PWROK

SUS_STAT#

A A

SOC_PLTRST#

S0->S5

+3VL_RTC

SOC_RTCRST#
+19VB
+3VLP/+5VLP
EC_ON
+5VALW/+3VALW /+3VALW_DSW
PM_BATLOW#

PCH_PWR_EN (SLP_SUS#)
+3V_PRIM
+1.8V_PRIM
EXT_PWR_GATE#

+1.0V_MPHYPLL

+1.0V_PRIM_CORE

+1.0V_PRIM

SUSACK#

PCH_DPWRO K

EC_RSMRST#

AC_PRESENT

ON/OFF

PBTN_OUT #

PM_SLP_S5#

ESPI_RST#

PM_SLP_S4#

SYSON

+1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC

PM_SLP_S3#

SUSP#

+1.0VS_VCCSTG

+1.0VS_VCCIO

+5VS/+3VS/+1.5VS/+1.05VS

EC_VCCST_PG

VR_ON

SM_PG_CTRL

+0.675VS_VTT

+VCC_SA

+VCC_CORE

+VCC_GT

VR_PWRG D

PCH_PWRO K

H_CPUPWRGD
SYS_PWROK

SUS_STAT#

SOC_PLTRST#

SecurityClas sification

IssuedDate

THIS SHE ET OF ENGI NE ERI NG D RAW ING I STHE PROP RI ETA RY PROP E RTY OF COMP AL E LECTRONI CS, INC. AND CONTAI NS CONF ID EN AND
TRAD E SE CRE T INF ORMA TI ON. THI S SHE ET MA Y NOT BE TRA NSF ERE D F ROM THE CUS TOD YOF THE COMP E TENT DIVI SION OF R& DE PARTME
NT EX CEP T AS AUTHOR I ZED BY C OMPA L ELE CTRONI C S,I NC. NEI THER THI S SHE ET NOR THE INF ORMA TI ON I TCONTA I NS MA Y BE US ED BY OR
DISCLOSED TO A NY THI RD PARTY WI THOUT PRI OR W RITTE N CONS E NT OF COMP AL E LEC TRONI CS, INC.

5

4

3

Compal Secret Data

DecipheredDate

Compal Electronics,Inc.

Title

TSSIAizL

e

DocumentNumber

D

Custo

m

Date: Friday, January 05,2018 Sheet 4 of 59

2

HWReserve

CSL50 LA-E791P

Rev

v0.3

1

A

B

C D E

UC1A

UC1D

D63

CATERR#

A54

PECI
PROCHOT#

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

OPCE_RCOMP

H65

OPC_RCOMP

SKL-U_BGA1356

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

GPP_E18/DDPB_CTRLCLK

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKL-U_BGA1356

SKL-U

CPUMISC

4 OF20

<28> HOST_DP1_N0
<28> HOST_DP1_P0

SOC_DP1_CTRL_DATA(Internal Pull Down):

<HDMI>

Display Port B Detected

1 1

0 = Port B is not detected.
1 = Port B is detected.

<28> HOST_DP1_N1
<28> HOST_DP1_P1
<28> HOST_DP1_N2
<28> HOST_DP1_P2
<28> HOST_DP1_N3
<28> HOST_DP1_P3

SOC_DP2_CTRL_DATA(Internal Pull Down):
Display Port C Detected
0 = Port C is not detected.

HDMI DDC (Port B)

<28> HOST_DP1_CTRL_CLK
<28> HOST_DP1_CTRL_DATA

HOST_DP1_CTRL_CLK L13

HOST_DP1_CTRL_DATA L12

1 = Port C is detected.

EDP_COMP

+1.0V_VCCST

1

RC2

2 2

COMPENSATIONPU FOReDP

+1.0V_PRIM

RC1 1

CAD note:
Trace width=20 mils,Spacing=25mil,Maxlength=100mils

2 H_THERMTRIP#

1K_0402_5%

2 EDP_COMP

24.9_0402_1%

<33> PROCHOT#

+1.0V_PRIM

1

RC3
1K_0402_5%

2

1 2

RC4 499_0402_1%

1

DS11
CK0402101V05_0402-2

ESD@

SCV00001K00

2

RC5 2

RC6 2
RC7 2

RC82

T248 TP@

<33> H_PECI

1 49.9_0402_1% CPU_POPIRCOMP AT16

1 49.9_0402_1% PCH_OPIRCOMP

1 49.9_0402_1% EDRAM_OPIO_RCOMP H66

1 49.9_0402_1% EOPIO_RCOMP

CATERR#
H_PECI

H_PROCHOT#_R C65
H_THERMTRIP# C63

SKL-U

DDI

DISPLAYS IDEBAND S

JTAG

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST#

1 OF20

Rev_0.53

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

JTAGX

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP

B61
D60
A61 SOC_XDP_TDO
C60
B59

B56 PCH_JTAG_TCK1
D59 SOC_XDP_TDI
A56 SOC_XDP_TDO
C59 SOC_XDP_TMS
C61 SOC_XDP_TRST#
A59 CPU_XDP_TCK0

EDP_AUXN
EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

CPU_XDP_TCK0
SOC_XDP_TDI

SOC_XDP_TMS
SOC_XDP_TRST#

Rev_0.53

C47
C46
D46
C45
A45
B45
A47
B47

E45
F45

B52
G50

F50

E48

F48

G46

F46

L9 HOST_DP1_HPD

L7

L6
N9
L10

R12

R11

U13

DDI2_HPD
NMI_DBG#_CPU
EC_SCI#
EDP_HPD

ENBKL
ENVDD_CPU

EDP_TXN0 <27>
EDP_TXP0 <27>
EDP_TXN1 <27>
EDP_TXP1 <27>

EDP_AUXN <27>
EDP_AUXP <27>

HOST_DP1_HPD <28>

TP@ T408

NMI_DBG#_CPU <10,33>
EC_SCI# <33>
EDP_HPD <27>

ENBKL <33>
BKL_PWM_CPU <27>
ENVDD_CPU <27>

RC123 1 @ 2 100K_0402_5% ENVDD_CPU

RC124 1

From HDMI

2 100K_0402_5% ENBKL

<eDP>

From eDP

XDPCONN

3 3

+1.0V_PRIM

RC11 2 @
RC13 2 @
RC15 2 1 51 +-1% 0402 SOC_XDP_TDO
RC364 2 @ 1 51_0402_5% CPU_XDP_TCK0

+1.0V_PRIM

RC14 2 @ 1 51_0402_5% XDP_PREQ#

RC31 1 @ 2 1K_0402_5% XDP_ITP_PMODE

4 4

A

RC365 2 @ 1 51_0402_1% SOC_XDP_TRST#

RC35 2 1 51_0402_1% CPU_XDP_TCK0
RC37 2 @ 1 51_0402_5% PCH_JTAG_TCK1
RC366 1 @ 2 0_0402_5% CFG3

1 51_0402_5% SOC_XDP_TMS
1 51_0402_5% SOC_XDP_TDI

SD000008H80

XDP_PREQ# <11>

XDP_ITP_PMODE <16>

SD000008H80

CFG3 <16>

B

SecurityClassification

IssuedDate

THIS SHEE T OF ENGINEERING DR AW ING IS T HE PROP RIET ARY PROPERT Y O F CO MPAL ELECT RON ICS, INC. AN D CON TAINS CONFIDENTSSIAizL
AND T RADE SECR ET INF ORMA T ION. TH IS SHEET MAY NOT BE T RANS FERED FRO M T HE CUST ODY OF T HE COMPET ENT DIVISION OF R& D
DEPA RT MENT EXCEPT AS AUT H ORIZ ED BY CO MPAL EL ECT RON ICS, INC. NEITHER TH IS SHEET NOR T HE INFORM AT ION IT CONT AINS
MAY BE USED BY O R DISCLO SED T O ANY T HIRD PAR T Y W IT HOUT PRIO R W RIT T EN C ONS ENT OF COMP AL ELECT RONIC S, INC.

C D

2017/04/10 2019/12/15

Compal SecretData

DecipheredDate

Custom

Title

e Document Number

Date:

Compal Electronics, Inc.

SKL-U(1/12)DDI,MSIC,XDP,EDP

CSL50 LA-E791P

Friday, January 05, 2018 Sheet 5 of 59

E

Rev

v0.3

5

Interleaved Memory

4

3

2

1

Interleaved Memory

D D

UC1B

<17> DDR_M0_D[0..15]

<17> DDR_M0_D[16..31]

C C

<17> DDR_M0_D[32..47]

<17> DDR_M0_D[48..63]

B B

A A

AL71

DDR_M0_D0
DDR_M0_D1
DDR_M0_D2 AN68
DDR_M0_D3 AN69
DDR_M0_D4 AL70
DDR_M0_D5 AL69
DDR_M0_D6 AN70
DDR_M0_D7 AN71
DDR_M0_D8 AR70

DDR_M0_D9

DDR_M0_D10AU71
DDR_M0_D11AU68
DDR_M0_D12AR71
DDR_M0_D13AR69
DDR_M0_D14AU70
DDR_M0_D15AU69
DDR_M0_D16BB65
DDR_M0_D17AW65
DDR_M0_D18AW63
DDR_M0_D19AY63
DDR_M0_D20BA65
DDR_M0_D21AY65
DDR_M0_D22BA63
DDR_M0_D23BB63
DDR_M0_D24BA61
DDR_M0_D25AW61
DDR_M0_D26BB59
DDR_M0_D27AW59
DDR_M0_D28BB61
DDR_M0_D29AY61
DDR_M0_D30BA59
DDR_M0_D31AY59
DDR_M0_D32AY39
DDR_M0_D33AW39
DDR_M0_D34AY37
DDR_M0_D35AW37
DDR_M0_D36BB39
DDR_M0_D37BA39
DDR_M0_D38BA37
DDR_M0_D39BB37
DDR_M0_D40AY35
DDR_M0_D41AW35
DDR_M0_D42AY33
DDR_M0_D43AW33
DDR_M0_D44BB35
DDR_M0_D45BA35
DDR_M0_D46BA33
DDR_M0_D47BB33
DDR_M0_D48AY31
DDR_M0_D49AW31
DDR_M0_D50AY29
DDR_M0_D51AW29
DDR_M0_D52BB31
DDR_M0_D53BA31
DDR_M0_D54BA29
DDR_M0_D55BB29
DDR_M0_D56AY27
DDR_M0_D57AW27
DDR_M0_D58AY25
DDR_M0_D59AW25
DDR_M0_D60BB27
DDR_M0_D61BA27
DDR_M0_D62BA25
DDR_M0_D63BB25

DDR0_DQ[0]

AL68

DDR0_DQ[1]
DDR0_DQ[2]
DDR0_DQ[3]
DDR0_DQ[4]
DDR0_DQ[5]
DDR0_DQ[6]
DDR0_DQ[7]
DDR0_DQ[8]

AR68

DDR0_DQ[9]

DDR0_DQ[10]
DDR0_DQ[11]
DDR0_DQ[12]
DDR0_DQ[13]
DDR0_DQ[14]
DDR0_DQ[15]
DDR0_DQ[16]/DDR0_DQ[32]
DDR0_DQ[17]/DDR0_DQ[33]
DDR0_DQ[18]/DDR0_DQ[34]
DDR0_DQ[19]/DDR0_DQ[35]
DDR0_DQ[20]/DDR0_DQ[36]
DDR0_DQ[21]/DDR0_DQ[37]
DDR0_DQ[22]/DDR0_DQ[38]
DDR0_DQ[23]/DDR0_DQ[39]
DDR0_DQ[24]/DDR0_DQ[40]
DDR0_DQ[25]/DDR0_DQ[41]
DDR0_DQ[26]/DDR0_DQ[42]
DDR0_DQ[27]/DDR0_DQ[43]
DDR0_DQ[28]/DDR0_DQ[44]
DDR0_DQ[29]/DDR0_DQ[45]
DDR0_DQ[30]/DDR0_DQ[46]
DDR0_DQ[31]/DDR0_DQ[47]
DDR0_DQ[32]/DDR1_DQ[0]
DDR0_DQ[33]/DDR1_DQ[1]
DDR0_DQ[34]/DDR1_DQ[2]
DDR0_DQ[35]/DDR1_DQ[3]
DDR0_DQ[36]/DDR1_DQ[4]
DDR0_DQ[37]/DDR1_DQ[5]
DDR0_DQ[38]/DDR1_DQ[6]
DDR0_DQ[39]/DDR1_DQ[7]
DDR0_DQ[40]/DDR1_DQ[8]
DDR0_DQ[41]/DDR1_DQ[9]
DDR0_DQ[42]/DDR1_DQ[10]
DDR0_DQ[43]/DDR1_DQ[11]
DDR0_DQ[44]/DDR1_DQ[12]
DDR0_DQ[45]/DDR1_DQ[13]
DDR0_DQ[46]/DDR1_DQ[14]
DDR0_DQ[47]/DDR1_DQ[15]
DDR0_DQ[48]/DDR1_DQ[32]
DDR0_DQ[49]/DDR1_DQ[33]
DDR0_DQ[50]/DDR1_DQ[34]
DDR0_DQ[51]/DDR1_DQ[35]
DDR0_DQ[52]/DDR1_DQ[36]
DDR0_DQ[53]/DDR1_DQ[37]
DDR0_DQ[54]/DDR1_DQ[38]
DDR0_DQ[55]/DDR1_DQ[39]
DDR0_DQ[56]/DDR1_DQ[40]
DDR0_DQ[57]/DDR1_DQ[41]
DDR0_DQ[58]/DDR1_DQ[42]
DDR0_DQ[59]/DDR1_DQ[43]
DDR0_DQ[60]/DDR1_DQ[44]
DDR0_DQ[61]/DDR1_DQ[45]
DDR0_DQ[62]/DDR1_DQ[46]
DDR0_DQ[63]/DDR1_DQ[47]

SKL-U_BGA1356

RC905

100K_0402_5% @

2 1

RC906

100K_0402_5% @

DDR_PG_CTRL

SB00000QJ00,S TRDRC5115E0LNPN
SOT323-3

+1.2V_VDDQ

12 2

@ 100K_0402_5%

12

@

3

UC9

SB000008E10

MMBT3904WH NPN SOT323-3

DDRCH-A

2 OF20

RC904

1 SM_PG_CTRL

<Cocoa_1020>
PDG#543016, ODT: CPU side no connect, DRAM side connect to VDDQ(Memory down);

SKL-U

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]

Rev_0.53 Rev_0.53

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]

DDR0_MA[3]
DDR0_MA[4]

DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA

DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

AU53 DDR_M0_CLK#0
AT53 DDR_M0_CLK0
AU55 DDR_M0_CLK#1

AT55 DDR_M0_CLK1

DDR_M0_CKE0

BA56

DDR_M0_CKE1

BB56
AW56

AY56

DDR_M0_CS#0

AU45

AU43 DDR_M0_CS#1

AT45 DDR_M0_ODT0
AT43 DDR_M0_ODT1

BA51 DDR_M0_MA5
BB54 DDR_M0_MA9
BA52 DDR_M0_MA6
AY52 DDR_M0_MA8
AW 52 DDR_M0_MA7

AY55 DDR_M0_BG0

AW 54 DDR_M0_MA12

BA54 DDR_M0_MA11

BA55 DDR_M0_ACT#

AY54 DDR_M0_BG1

AU46 DDR_M0_MA13
AU48 DDR_M0_MA15_CAS#
AT46 DDR_M0_MA14_WE#
AU50 DDR_M0_MA16_RAS#

AU52 DDR_M0_BA0
AY51 DDR_M0_MA2
AT48 DDR_M0_BA1
AT50 DDR_M0_MA10
BB50 DDR_M0_MA1
AY50 DDR_M0_MA0

BA50 DDR_M0_MA3

BB52 DDR_M0_MA4

AM70 DDR_M0_DQS#0

AM69 DDR_M0_DQS0

AT69 DDR_M0_DQS#1

AT70 DDR_M0_DQS1

BA64 DDR_M0_DQS#2
AY64 DDR_M0_DQS2
AY60 DDR_M0_DQS#3
BA60 DDR_M0_DQS3
BA38 DDR_M0_DQS#4
AY38 DDR_M0_DQS4
AY34 DDR_M0_DQS#5
BA34 DDR_M0_DQS5
BA30 DDR_M0_DQS#6
AY30 DDR_M0_DQS6
AY26 DDR_M0_DQS#7
BA26 DDR_M0_DQS7

AW 50 DDR_M0_ALERT#

AT52 DDR_M0_PAR

AY67 +0.6V_VREFCA

AY68

BA67 +0.6V_B_VREFDQ
AW 67 DDR_PG_CTRL

For VTT power control

DDR_PG_CTRL 2

DDR_M0_CLK#0 <17>
DDR_M0_CLK0 <17>
DDR_M0_CLK#1 <17>
DDR_M0_CLK1 <17>

DDR_M0_CKE0 <17>
DDR_M0_CKE1 <17>

DDR_M0_CS#0 <17>
DDR_M0_CS#1 <17>
DDR_M0_ODT0 <17>
DDR_M0_ODT1 <17>

DDR_M0_MA5 <17>
DDR_M0_MA9 <17>
DDR_M0_MA6 <17>
DDR_M0_MA8 <17>
DDR_M0_MA7 <17>
DDR_M0_BG0 <17>
DDR_M0_MA12 <17>
DDR_M0_MA11 <17>
DDR_M0_ACT# <17>
DDR_M0_BG1 <17>

DDR_M0_MA13 <17>
DDR_M0_MA15_CAS# <17>
DDR_M0_MA14_WE# <17>
DDR_M0_MA16_RAS# <17>
DDR_M0_BA0 <17>
DDR_M0_MA2 <17>
DDR_M0_BA1 <17>
DDR_M0_MA10 <17>
DDR_M0_MA1 <17>

DDR_M0_MA0 <17>
DDR_M0_MA3 <17>
DDR_M0_MA4 <17>

DDR_M0_DQS#0 <17>
DDR_M0_DQS0 <17>
DDR_M0_DQS#1 <17>
DDR_M0_DQS1 <17>
DDR_M0_DQS#2 <17>
DDR_M0_DQS2 <17>
DDR_M0_DQS#3 <17>
DDR_M0_DQS3 <17>
DDR_M0_DQS#4 <17>
DDR_M0_DQS4 <17>
DDR_M0_DQS#5 <17>
DDR_M0_DQS5 <17>
DDR_M0_DQS#6 <17>
DDR_M0_DQS6 <17>
DDR_M0_DQS#7 <17>
DDR_M0_DQS7 <17>

DDR_M0_ALERT# <17>
DDR_M0_PAR <17>

+0.6V_VREFCA
+0.6V_B_VREFDQ

0.1U_0201_10V6K 2 1 CC57
UC7

1

NC

A

3

GND

74AUP1G07SE-7_SOT353-5

SA00007WE00

VCC

+1.2V_VDDQ

5

4

Y

<18> DDR_M1_D[0..15]

<18> DDR_M1_D[16..31]

<18> DDR_M1_D[32..47]

<18> DDR_M1_D[48..63]

+3VS

1

RC394
100K_0402_5%

2

SM_PG_CTRL <49>

UC1C

DDR_M1_D0 AF65
DDR_M1_D1 AF64

DDR_M1_D2 AK65
DDR_M1_D3 AK64
DDR_M1_D4 AF66
DDR_M1_D5 AF67
DDR_M1_D6 AK67
DDR_M1_D7 AK66
DDR_M1_D8 AF70
DDR_M1_D9 AF68
DDR_M1_D10AH71
DDR_M1_D11AH68
DDR_M1_D12AF71
DDR_M1_D13AF69
DDR_M1_D14AH70
DDR_M1_D15AH69
DDR_M1_D16AT66
DDR_M1_D17AU66 DDR1_DQ[16]/DDR0_DQ[48]
DDR_M1_D18AP65 DDR1_DQ[17]/DDR0_DQ[49]
DDR_M1_D19AN65 DDR1_DQ[18]/DDR0_DQ[50]
DDR_M1_D20AN66 DDR1_DQ[19]/DDR0_DQ[51]
DDR_M1_D21AP66
DDR_M1_D22AT65
DDR_M1_D23AU65
DDR_M1_D24AT61
DDR_M1_D25AU61
DDR_M1_D26AP60
DDR_M1_D27AN60
DDR_M1_D28AN61
DDR_M1_D29AP61
DDR_M1_D30AT60
DDR_M1_D31AU60
DDR_M1_D32AU40
DDR_M1_D33AT40
DDR_M1_D34AT37
DDR_M1_D35AU37
DDR_M1_D36AR40
DDR_M1_D37AP40
DDR_M1_D38AP37
DDR_M1_D39AR37
DDR_M1_D40AT33
DDR_M1_D41AU33
DDR_M1_D42AU30
DDR_M1_D43AT30
DDR_M1_D44AR33
DDR_M1_D45AP33

DDR_M1_D46AR30
DDR_M1_D47AP30
DDR_M1_D48AU27
DDR_M1_D49AT27
DDR_M1_D50AT25
DDR_M1_D51AU25 DDR1_DQ[50]
DDR_M1_D52AP27
DDR_M1_D53AN27
DDR_M1_D54AN25
DDR_M1_D55AP25
DDR_M1_D56AT22
DDR_M1_D57AU22
DDR_M1_D58AU21
DDR_M1_D59AT21
DDR_M1_D60AN22
DDR_M1_D61AP22
DDR_M1_D62AP21
DDR_M1_D63AN21

DDR1_DQ[0]/DDR0_DQ[16]
DDR1_DQ[1]/DDR0_DQ[17]

DDR1_DQ[2]/DDR0_DQ[18]

DDR1_DQ[3]/DDR0_DQ[19]

DDR1_DQ[4]/DDR0_DQ[20]
DDR1_DQ[5]/DDR0_DQ[21]
DDR1_DQ[6]/DDR0_DQ[22]

DDR1_DQ[7]/DDR0_DQ[23]

DDR1_DQ[8]/DDR0_DQ[24]

DDR1_DQ[9]/DDR0_DQ[25]

DDR1_DQ[10]/DDR0_DQ[26]

DDR1_DQ[11]/DDR0_DQ[27]

DDR1_DQ[12]/DDR0_DQ[28]

DDR1_DQ[13]/DDR0_DQ[29]

DDR1_DQ[14]/DDR0_DQ[30]
DDR1_DQ[15]/DDR0_DQ[31]

DDR1_DQ[20]/DDR0_DQ[52]

DDR1_DQ[21]/DDR0_DQ[53]

DDR1_DQ[22]/DDR0_DQ[54]

DDR1_DQ[23]/DDR0_DQ[55]

DDR1_DQ[24]/DDR0_DQ[56]

DDR1_DQ[25]/DDR0_DQ[57]

DDR1_DQ[26]/DDR0_DQ[58]
DDR1_DQ[27]/DDR0_DQ[59]

DDR1_DQ[28]/DDR0_DQ[60]
DDR1_DQ[29]/DDR0_DQ[61]
DDR1_DQ[30]/DDR0_DQ[62]
DDR1_DQ[31]/DDR0_DQ[63]

DDR1_DQ[32]/DDR1_DQ[16]
DDR1_DQ[33]/DDR1_DQ[17]

DDR1_DQ[34]/DDR1_DQ[18]
DDR1_DQ[35]/DDR1_DQ[19]

DDR1_DQ[36]/DDR1_DQ[20]

DDR1_DQ[37]/DDR1_DQ[21]

DDR1_DQ[38]/DDR1_DQ[22]

DDR1_DQ[39]/DDR1_DQ[23]
DDR1_DQ[40]/DDR1_DQ[24]
DDR1_DQ[41]/DDR1_DQ[25]

DDR1_DQ[42]/DDR1_DQ[26]

DDR1_DQ[43]/DDR1_DQ[27]

DDR1_DQ[44]/DDR1_DQ[28]

DDR1_DQ[45]/DDR1_DQ[29]
DDR1_DQ[46]/DDR1_DQ[30]

DDR1_DQ[47]/DDR1_DQ[31]

DDR1_DQ[489]]
DDR1_DQ[51]

DDR1_DQ[52]

DDR1_DQ[53]

DDR1_DQ[54]

DDR1_DQ[55]
DDR1_DQ[56]

DDR1_DQ[57]

DDR1_DQ[58]
DDR1_DQ[59]
DDR1_DQ[60]
DDR1_DQ[61]

DDR1_DQ[62]

DDR1_DQ[63]

SKL-U_BGA1356

+1.2V_VDDQ

DDR_DRAMRST#

12

RC32
470_0402_5%

SKL-U

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]

DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDR_M1_BG0

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_M1_MA12
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDR_M1_BG1
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB [9]/DDR1_MA [0]

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]

DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_M1_DQS#2
DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_M1_DQS2
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDR_M1_DQS#4
DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDR_M1_DQS4
DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_M1_DQS#5
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]

DDRCH-B

3 OF20

1 Rshort@2 DDR_DRAMRST#_R RC33

0_0402_5%

AN45 DDR_M1_CLK#0

DDR1_CKN[0]

AN46 DDR_M1_CLK#1

DDR1_CKN[1]

AP45 DDR_M1_CLK0

DDR1_CKP[0]

AP46 DDR_M1_CLK1

DDR1_CKP[1]

AN56

DDR1_CKE[0]
DDR1_CKE[1]

DDR_M1_CKE1

DDR1_CKE[2]

AP53

DDR1_CKE[3]

BB42 DDR_M1_CS#0

DDR1_CS#[0]

AY42 DDR_M1_CS#1

DDR1_CS#[1]

BA42 DDR_M1_ODT0

DDR1_ODT[0]

AW 42 DDR_M1_ODT1

DDR1_ODT[1]

AY48 DDR_M1_MA5
AP50 DDR_M1_MA9

BA48 DDR_M1_MA6
BB48 DDR_M1_MA8
AP48 DDR_M1_MA7

AN48 DDR_M1_MA11
AN53 DDR_M1_ACT#

BA43 DDR_M1_MA13

AY43 DDR_M1_MA15_CAS#

AY44 DDR_M1_MA14_W E#

AW 44 DDR_M1_MA16_RAS#

BB44 DDR_M1_BA0
AY47 DDR_M1_MA2
BA44 DDR_M1_BA1

AW 46 DDR_M1_MA10

AY46 DDR_M1_MA1

BA46 DDR_M1_MA0

BB46 DDR_M1_MA3

DDR1_MA[3]

BA47 DDR_M1_MA4

DDR1_MA[4]

AH66 DDR_M1_DQS#0

AH65 DDR_M1_DQS0

AG69 DDR_M1_DQS#1

AG70 DDR_M1_DQS1

AR61 DDR_M1_DQS#3

AR60 DDR_M1_DQS3

AR32 DDR_M1_DQS5

AR25 DDR_M1_DQS#6

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]

DRAM_RESET#
DDR_RCOMP[0]

AR27 DDR_M1_DQS6
AR22 DDR_M1_DQS#7
AR21 DDR_M1_DQS7

AN43 DDR_M1_ALERT# AP43

DDR1_ALERT#

DDR_M1_PAR

DDR1_PAR

AT13 DDR_DRAMRST# AR18

SM_RCOMP0 RC38 1

AT18 SM_RCOMP1 RC39 1

DDR_RCOMP[1]

AU18 SM_RCOMP2 RC40 1

DDR_RCOMP[2]

DDR_DRAMRST#_R <17,18>

FET+R(SO-DIMM)

DDR_M1_CLK#0 <18>
DDR_M1_CLK#1 <18>
DDR_M1_CLK0 <18>
DDR_M1_CLK1 <18>

DDR_M1_CKE0 <18>

C0KER_MD1_DAP55

DDR_M1_CKE1 <18>

AN55

DDR_M1_CS#0 <18>
DDR_M1_CS#1 <18>
DDR_M1_ODT0 <18>
DDR_M1_ODT1 <18>

DDR_M1_MA5 <18>
DDR_M1_MA9 <18>
DDR_M1_MA6 <18>
DDR_M1_MA8 <18>
DDR_M1_MA7 <18>
DDR_M1_BG0 <18>
DDR_M1_MA12 <18>
DDR_M1_MA11 <18>
DDR_M1_ACT# <18>
DDR_M1_BG1 <18>

DDR_M1_MA13 <18>
DDR_M1_MA15_CAS# <18>
DDR_M1_MA14_WE# <18>
DDR_M1_MA16_RAS# <18>
DDR_M1_BA0 <18>
DDR_M1_MA2 <18>
DDR_M1_BA1 <18>
DDR_M1_MA10 <18>
DDR_M1_MA1 <18>
DDR_M1_MA0 <18>
DDR_M1_MA3 <18>
DDR_M1_MA4 <18>

DDR_M1_DQS#0 <18>
DDR_M1_DQS0 <18>
DDR_M1_DQS#1 <18>
DDR_M1_DQS1 <18>
DDR_M1_DQS#2 <18>
DDR_M1_DQS2 <18>
DDR_M1_DQS#3 <18>
DDR_M1_DQS3 <18>
DDR_M1_DQS#4 <18>
DDR_M1_DQS4 <18>
DDR_M1_DQS#5 <18>
DDR_M1_DQS5 <18>
DDR_M1_DQS#6 <18>
DDR_M1_DQS6 <18>
DDR_M1_DQS#7 <18>
DDR_M1_DQS7 <18>

DDR_M1_ALERT# <18>
DDR_M1_PAR <18>

2 121_0402_1%
2 80.6_0402 _1%

2 100_0402_1%

DDR_PG_CTRL 1

From ESD Team Request

@ESD@

CC70 100P_0402_50V8J

2

SecurityClassification

IssuedDate

THIS SH E ET O F E NG IN EE R IN G D RA WIN G IS TH E PR OP RIE TA RY PR O PE RTY O F C OM PA L E LECT RONI CS , INC . A ND C ONTA INS CONFIDENTSI
AN D TR AD E SE CR E T INF ORM A TI ON . TH IS SHE ET M AY N OT BE TR AN S FE RE D FR OM TH E C US TO D Y OF TH E C O MP ETE N T DIV IS ION OF R & D

DEP ARTM E NT E XC E PT AS AUTH ORIZ E D BY C OM P AL ELE CTR ONICS , I NC. NE ITHE R THIS S HE E T N OR TH E IN F OR M ATIO N IT CO NTA INS

5

4

MA Y BE U S ED BY OR D IS CLOS E D TO A N Y TH IRD P AR TY W ITH O UT P RIO R W R ITTE N C ON S EN T OF C O MP AL ELE CTR ONIC S , INC.

3

2017/04/10 2019/12/15

Compal Secret Data

DecipheredDate

Compal Electronics,Inc.

Title

iiiAzeLDocument Number

Custom

2

Date: Friday, January 05, 2018

SKL-U(2/12)DDRIII

CSL50 LA-E791P

1

Sheet 6 of

Rev

v0.3

59

5

HOST_SPI_0_CLK AV2

<35> HOST_SPI_0_SO
<35> HOST_SPI_0_SI

D D

to SPI ROM UC2

C C

HOST_SPI_0_CS0#_R1
HOST_SPI_0_CS0#_R2
HOST_SPI_0_SO_R 3
HOST_SPI_0_SO_R 4

HOST_SPI_0_HOLD# 1
HOST_SPI_0_SI_R 2
HOST_SPI_0_SI_R 3

HOST_SPI_0_WP# 2 1 HOST_SPI_0_SIO2

SPI ROM ( 8MByte Only)

HOST_SPI_0_CS0#_R 1
HOST_SPI_0_SO_R 2
HOST_SPI_0_WP#

ACES_91960-0084L_8P-T

Use socketfootprint

B B

<35> HOST_SPI_0_CS2#

<33> EC_KBRST#

To TPM

<33,35> SERIRQ

RPH11

15_0804_8P4R_5%

RPH12

4 5

15_0804_8P4R_5%

RC388 15_0402_5%

UC2

CS# VCC
DO(IO1) HOLD#(IO3)

3

WP#(IO2) CLK

4

GND DI(IO0)

XM25QH64AHIG SOP 8P

SPI ROM Part:

SA0000B8300

Main:SA0000B8300, S IC FL 64M XM25QH64AHIG SOP 8P(XMC)

SourceFrom

8 EC_SPI_CS0#
7 HOST_SPI_0_CS0#
6 EC_SPI_SO
5 HOST_SPI_0_SO

8 HOST_SPI_0_SIO3
7 HOST_SPI_0_SI
6 EC_SPI_SI

+3V_SPI

8
7

HOST_SPI_0_HOLD#

6

HOST_SPI_0_CLK_R

5

HOST_SPI_0_SI_R

2nd: SA000039A40, S IC FL 64M W25Q64JVSSIQ SOIC 8P SPI ROM(Winbond)

3th: SA00008SL00, S IC FL 64M MX25L6473FM2I-08G SOP 8P(MXIC)

4rd: SA00007LA10, S IC FL 64M GD25B64CSIGR SOP 8P SPI ROM(GigaDevice)

HOST_SPI_0_SO AW3
HOST_SPI_0_SI

HOST_SPI_0_SIO2 AW2
HOST_SPI_0_SIO3 AU4
HOST_SPI_0_CS0# AU3

HOST_SPI_0_CS2# AU1

EC_KBRST#
SERIRQ

LPC Mode

EC_SPI_CS0# <33>
EC_SPI_SO<33>

EC_SPI_SI <33>

CC8

1 2 0.1U_0201_10V6K

AW13

AY11

SPI0_CLK
SPI0_MISO

AV3

AU2

M2
M3
J4
V1
V2

M1

G3
G2

G1

4

UC1E

SPI- FLASH

SPI0_MOSI

SPI0_IO2
SPI0_IO3
SPI0_CS0#

SPI0_CS1#

SPI0_CS2#

SPI- TOUCH

GPP_D1/SPI1_CLK

GPP_D2/SPI1_MISO

GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2

GPP_D22/SPI1_IO3

GPP_D0/SPI1_CS#

CLINK

CL_CLK
CL_DATA

CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

SKL-U_BGA1356

QC1A

SMBCLK 6

L2N7002SDW1T1G 2NSC88-6

SB00001FF00

SMBDATA

SML1CLK

QC2A

L2N7002SDW1T1G 2N SC88-6

SB00001FF00 @

SML1DATA

SKL-U

LPC

5 OF20

+3VS +3VS

2

1

5

QC1B

3 4

L2N7002SDW1T1G 2N SC88-6

SB00001FF00

@

6 1

L2N7002SDW1T1G 2N SC88-6

+3VS

2

3 4

QC2B

SB00001FF00

+3V_PRIM +3VALW

5

3 2 1

SMBUS ,SMLINK

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

RC216

10K_0402_5%

1 2

Rev_0.53

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A8/CLKRUN#

2

RC215

10K_0402_5%

1

PCH_SMBCLK <17,18>

PCH_SMBDATA <17,18>

R7 SMBCLK
R8 SMBDATA

SMBALERT#

R10

R9 SML0CLK

W2

SML0DATA

W1

SML0ALERT#

W3 SML1CLK

V3

SML1DATA

AM7 GPP_B231

AY13 LPC_AD0

LPC_AD1

BA13

LPC_AD2

BB13

LPC_AD3

AY12

LPC_FRAME#

BA12

SUS_STAT#

BA11

AW9 CLK_PCI0

AY9

PM_CLKRUN#

AW11

<DB> Un-pop QC2 for new 0x90 thermalsensor

EC_SMB_CK2 <10,33>

EC_SMB_DA2 <10,33>

TP@ T239

2SML1ALERT#

RC902@

0_0201_5%

TP@ T234

LPC_AD0 <33>
LPC_AD1 <33>

LPC_AD2 <33>
LPC_AD3 <33> 7 2
LPC_FRAME# <33> EC_KBRST#

TP@ T2402 5 4

RC387 1 2 22_0402_5%

PM_CLKRUN# <33>

CC182

22P 50V J NPO 0402

EMI@

SMB

(Link to XDP, DDR, TP)

SML1

(Link to EC,DGPU, LAN, Thermal Sensor)

CLK_PCI_LPC <33>

1

2

SML0ALERT# (Internal Pull Down):
eSPI or LPC
0 = LPC is selected for EC --> For KB9022/9032 Use 1
= eSPI is selected for EC --> For KB9032 Only.

SML0ALERT#

1

RC218
1K_0402_1%

2

SML1ALERT# RC903 2 @ 1150K_0402_1%

SML0ALERT# RC360 2 @ 1 10K_0402_5%

SMBALERT#

To EC

SML0CLK
SML0DATA

SML1CLK
SML1DATA

SMBCLK
SMBDATA

HOST_SPI_0_SIO2 RC3901@ 21K_0402_1%
HOST_SPI_0_SIO3 RC3911@ 21K_0402_1%

HOST_SPI_0_CS0#_R 1 @2

HOST_SPI_0_SIO3 RC51 1ES@ 2 1K_0402_1%

RC49 1 2 499_0402_1%
RC50 1 2 499_0402_1%

RC357 1K_0402_5%

8 1

6 3

RPC19 10K_0804_8P4R_5%

RPC7

1 8
2

7

3
465

1K_0804_8P4R_5%

+3V_SPI

+3V_PRIM

+3VS

+3V_PRIM

From W W36 MOW for SKL-U ESsample

2

RC82

RC81

10K_0402_5%

1 2

1

TP_SMBCLK <34>

TP_SMBDATA <34>

PM_CLKRUN#

SERIRQ

1

RC107

1 2

RC122 8.2K_0402_5%

2

8.2K_0402_5%

+3VS_PGPPA

Follow 543016_SKL_U_Y_PDG_0_9

CLK Source CPU to SPI ROMUC2&EC

HOST_SPI_0_CLK 2 1 HOST_SPI_0_CLK_R

15_0402_5%

RC368 EMI@

1 2

CC9
10P_0402_50V8J

@EMI@

HOST_SPI_0_CLK_R <33,35>

2

SMBCLK 1

L2N7002SDW1T1G 2NSC88-6

SMBDATA 4

SB00001FF00

10K_0402_5%

6

QC7A

5

3

QC7B SB00001FF00

L2N7002SDW1T1G 2NSC88-6

EON SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P MXIC

SA00006N100 SIC FL 64M MX25L6473EM2I-10G SOP 8P
WINBOND SA000039A30 S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM
Micron SA00005L100 S IC FL 64M N25Q064A13ESEC0FSO8W 8P

A A

SecurityClassification

IssuedDate

THIS SHEE T OF ENGINEERING DR AW ING IS T HE PROP RIET ARY PROPERT Y O F CO MPAL ELECT RON ICS, INC. AN D CON TAINS CONFIDENTSSIAizL
AND T RADE SECR ET INF ORMA T ION. TH IS SHEET MAY NOT BE T RANS FERED FRO M T HE CUST ODY OF T HE COMPET ENT DIVISION OF R& D
DEPA RT MENT EXCEPT AS AUT H ORIZ ED BY CO MPAL EL ECT RON ICS, IN C. NEIT HER THIS SHEET N OR T HE INFO RMAT ION IT CONTAIN S

5

4

MAY BE USED BY O R DISCLO SED T O ANY T HIRD PAR T Y W IT HOUT PRIO R W RITT EN CONSE NT OF COMP AL ELEC T RONIC S, IN C.

3 2

2017/04/10 2019/12/15

Compal SecretData

DecipheredDate

e Document Number

Custom

Compal Electronics, Inc.

Title

SKL-U(3/12)SPI,ESPI,SMB,LPC

CSL50 LA-E791P

Sheet 7 of 59Date: Friday, January 05, 2018

1

Rev

v0.3

5

4

3 2

1

1 @ 2 RC3801

9OF20

SKL-U

7OF20

1K_0402_1%

@

D

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

SDIO/SDXC

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#
GPP_G6/SD_CLK

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

RC367 1Rshort@20_0402_5%

2

G

3 HDA_SDOUT

QC380

S

MESS138W-G_SOT323-3

Rev_0.53

C37

CSI2_CLKN0

D37

CSI2_CLKP0

C32

CSI2_CLKN1

D32

CSI2_CLKP1

C29

CSI2_CLKN2

D29

CSI2_CLKP2

B26

CSI2_CLKN3

A26

CSI2_CLKP3

E13 CSI2_COMP RC802

CSI2_COMP

B7

AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1

AM2
AM3
AP4

AT1 EMMC_RCOMP 2

Rev_0.53

GPP_G7/SD_WP

SD_RCOMP

GPP_F23

AB11

VRAMCLK_SEL

AB13

PROJECT_ID

AB12

PLAT_SEL0

W12

PLAT_SEL1

W11

W10
W8
W7

BA9

BB9
AB7 SD_RCOMP RC76 2

AF13SOC_GPIOF17

1 200_0402_1%

T235TP@

HDA_SDOUT:
ME Flash Descriptor Security Override

Low : Disabled(Default)
High : Enabled

1 100_0402_1%

1

RC89

200_0402_1%

+3V_PRIM

1

PX@ RC127

10K_0402_5%

2

1

RC128

UMA@ 10K_0402_5%

2

X76 BOM control RAM size

Net Name 4G 2G

VRAMCLK_SEL

PLAT_SEL0

0 KBL-U KBL-R
1 SKL-U NA

1 0

PLAT_SEL0
PLAT_SEL1

PLAT_SEL1

0 1

PROJECT_ID

VRAM Clock

VRAMCLK_SEL

KBLR@

1 2

KBLU@

1 2

SKYL@

RC918

10K_0402_5%

SD028100280

2G VRAM 4G VRAM

RC919
10K_0402_5%

RC918
10K_0402_5%

UMA DIS

0

0

+3V_PRIM

2

RC900

X76@

10K_0402_5%

1

2

RC901

X76@

10K_0402_5%

1

+3V_PRIM

SKYL@

RC916
10K_0402_5%

1 2

KBLU@

RC917

10K_0402_5%

1 2

KBLR@

RC917

10K_0402_5%

SD028100280

1

1

UC1G

D D

<32> HDA_SDIN0

T38TP@
T39TP@

<10,32> HDA_SPKR

C C

HDA forAUDIO

1 8

EMI@

22P50VJNPO0402

@R

F@

22P50V J NPO0402

2
3
4

<32> HDA_SYNC_R
<32> HDA_RST#_R
<32> HDA_SDOUT_R

<32> HDA_BIT_CLK_R

CC143

EMI request

B B

A A

CC183

HDA_SYNC

HDA_BIT_CLK AY22

HDA_SDOUT

HDA_SDIN0

HDA_RST#

SOC_GPIOF1
SOC_GPIOF0

HDA_SPKR

RPC9

7 HDA_SYNC
6 HDA_RST#
5 HDA_SDOUT

33_0804_8P4R_5%

2 EMI@ 1 HDA_BIT_CLK

RC383 33_0402_5%

BA22

HDA_BLK/I2S0_SCLK

BB22
BA21
AY21

AW22

J5

AY20

AW20

AK7
AK6
AK9

AK10

H5

D7
D8

C8

AW5

A36

B36
C38
D38
C36
D36

A38

B38
C31

D31

C33
D33

A31

B31

A33

B33

A29

B29
C2
D2
A27
B27
C27
D27

AUDIO

HDA_SYNC/I2S0_SFRM
HDA_SDO/I2S0_TXD

HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK

GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD

GPP_F1/I2S2_SFRM

GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD

GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0

GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1

GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKL-U_BGA1356

+3V_HDA

UC1I

CSI-2

CSI2_DN0
CSI2_DP0
CSI2_DN1
CSI2_DP1
CSI2_DN2
CSI2_DP2
CSI2_DN3
CSI2_DP3

CSI2_DN4
CSI2_DP4

CSI2_DN5

CSI2_DP5
CSI2_DN6
CSI2_DP6
CSI2_DN7
CSI2_DP7

CSI2_DN8

CSI2_DP8

8

CSI2_DN9

8

CSI2_DP9
CSI2_DN10
CSI2_DP10

CSI2_DN11

CSI2_DP11

SKL-U_BGA1356

<33> ME_FLASH_EN

SKL_ULT

SecurityClassification

IssuedDate

THIS SHEET OF ENGIN EERING DRAW ING IS THE PROPRIETARY PROP ERT Y OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENSSTiIzAeL
AND TRA DE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPET ENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
MAY BE U SED BY OR DISCLOSED TO AN Y THIRD PART Y W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL E LECTRONICS , INC.

5

4

2017/04/10 2019/12/15

3 2

Compal Secret Data

DecipheredDate

Compal Electronics,Inc.

Title

SKL-U(4/12)HDA,EMMC,SDIO,CSI2

DocumentNumber

Custom

CSL50 LA-E791P

Date: Friday,January 05, 2018 Sheet

Rev

v0.3

59

of

8

1

+RTCVCC

RC91 1 2 20K_0402_5% PCH_SRTCRST#
CC10 1 2 1U_0402_6.3V6K

CLRP1 1 2 SHORT PADS

RC93 1 2 20K_0402_5% PCH_RTCRST#

CC11 1 2 1U_0402_6.3V6K
CLRP2 1 2 SHORT PADS

D D

C C

B B

A A

RC941 2 1M_0402_5% SM_INTRUDER#

PCH_RTCRST# 2

0_0402_5%

PCH_SRTCRST# 2

0_0402_5%

+3VS

RC165
RC105

+3VALW_DSW

RC925
RC926

+3V_PRIM

RC927
RC928

CLRP3
RC100
RC101

+3VALW_DSW

+3V_PRIM

+3VALW_DSW

RC111 2 @ 1 100K_0402_5% PBTN_OUT #

From EC(open-dra in)

<33,40> EC_VCCST_PG_R

5

1

R1088

1

R1089

1

2

10K_0402_5%

1

2 CLKREQ_PCIE#5

10K_0402_5%

RPC10

1 CLKREQ_PCIE#1

8

2 CLKREQ_PCIE#2

7

3 CLKREQ_PEG#0

6

4 CLKREQ_PCIE#3

5

10K_0804_8P4R_5%

1

2

10K_0402_5%

1

2 LAN_WAKE#

10K_0402_5%

1

2 PCH_RSMRST#

10K_0402_5%

1

2 SYS_RESET#

10K_0402_5%

2 1

1 @

1K_0402_5%

2

1 PCH_DPW ROK

100K_0402_5%

1

RC103

1

RC104

1 @ 2 AC_PRESENT_R

RC106

12

@

JCMOS1

0_0603_5%

CLKREQ_PCIE#4

PCH_PWRO K

SYS_RESET#

SHORT PADS

2 SUSCLK

2

8.2K_0402_5%

2 W AKE#

1K_0402_5%
10K_0402_5%

2 10K_0402_5% SOC_VRALERT#RC1151@

+1.0V_VCCST

5

Clear CMOS close to RAM door

CLR ME

CLR CMOS

CLR_CMOS# <33>

From 545659_SKL_PCH_U_Y_EDS_R0_7

<Cocoa_1027>
check un-use GPIO for terminat ion guidance

DS12

2

1 PCH_PWRO K

CK0402101V05_0402-2

ESD@
SCV00001K00

PM_BATLOW#

Only For Power Sequence Debug

<33> SUSACK#

DS13

1

CK0402101V05_0402-2
DS14

1

CK0402101V05_0402-2

ESD@

C5229 1 2 SYS_PWROK

0.1U_0402_25V6

1

RC113
1K_0402_5%

2

RC1161

2 60.4_0402_1% EC_VCCST_P G

ESD@

SCV00001K00

2 H_CPUPWRGD

@ESD@
SCV00001K00

2 SUSACK#

4

LAN

W LAN

PCIe SSD

PCH
PLTRST

Buffer

PLT_RST#_PCH

2 Rshort@

RC110 0_0402_5%

4

<29> CLK_PCIE_N1

<29> CLK_PCIE _P1

<29> CLKREQ_PCIE#1

<30> CLK_PCIE_N2

<30> CLK_PCIE_P 2

<30> CLKREQ_PCIE#2

<31> CLK_PCIE_N4
<31> CLK_PCIE_P4

<31> CLKREQ_PCIE#4

RC99 1 2 0_0402_5%

+3VS

@ UC8 0.1U_0201_10V6K

1

IN1

2

IN2

G P

3 5

T296 TP@

<33> PCH_RSMRST#

RC102 1 @ 2 1K_0402_5% H_C PUPWRGD A68

<33> SYS_PW ROK

<33> PCH_PW ROK

<33> PCH_SUSWARN#

1

<30> WAKE#

3

UC1J

D42

CLKOUT_PCIE_N0

C42

CLKREQ_PEG#0
CLK_PCIE_N1

CLK_PCIE_P1
CLKREQ_PCIE#1

CLK_PCIE_N2
CLK_PCIE_P2
CLKREQ_PCIE#2

CLKREQ_PCIE#3
CLK_PCIE_N4

CLK_PCIE_P4
CLKREQ_PCIE#4

CLKREQ_PCIE#5 AU7

@

CC145

1 2

4

O

SN74AHC1G08DCKR_SC70-5

PLT_RST#_PCH
SYS_RESET#
PCH_RSMRST#

EC_VCCST_PG B65
SYS_PWROK

PCH_PWRO K
PCH_DPWROK_R BB20

PCH_SUSWARN#
SUSACK#_R

WAKE#
LAN_WAKE#

T94 TP@

PCH_RSMRST# PCH_PWRO K

<33> PCH_DPWROK

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKR EQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

GPP_B10/SRCCLKR EQ5#

SKL-U_BGA1356

PLT_RST#

AY17

PLT_RST# <29,30,31,33,35>

UC1K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

RSMRST#

PROCPW RGD

VCCST_PW RGD

B6

SYS_PWROK

BA20

PCH_PW ROK

DSW_PW ROK

AR13

GPP_A13/SUSW ARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW 17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKL-U_BGA1356

DC3 SCS00000Z00

RB751V-40 SOD-323

1 2

2

1

DC4

SCS00000Z00

RB751V-40 SOD-323

SecurityClassification

THIS SH E ET O F E NG IN EE R IN G D RA WIN G IS TH E PR OP RIE TA RY PR O PE RTY O F C OM PA L E LECT RONI CS , INC . A ND C ONTA INS CONFIDENTSI
AN D TR AD E SE CR E T INF ORM A TI ON . TH IS SHE ET M AY N OT BE TR AN S FE RE D FR OM TH E C US TO D Y OF TH E C O MP ETE N T DIV IS ION OF R & D

DEP ARTM E NT E XC E PT AS AUTH ORIZ E D BY C OM P AL ELE CTR ONICS , I NC. NE ITHE R THIS S HE E T N OR TH E IN F OR M ATIO N IT CO NTA INS
MA Y BE U S ED BY OR DIS C LOS ED TO A NY THI RD P A RTY W I TH OU T PR IO R W RITT E N CO NS E NT OF CO MP A L E LEC TRON ICS , INC .

3

SYSTEMPOWERMANAGEMENT

IssuedDate

SKL_ULT

CLOCKSIGNALS

10 OF20

PCH_KBLU24_OUT RX2 2 1 33_0402_1% PCH_XTAL24U_OUT 1 2

SKL-U

GPP_B11/EXT_ PWR_GATE#

11 OF20

SPOK <48>

2 Rshort@1 PCH_DPWROK_R

RC112 0_0402 _5%

2017/04/10 2019/12/15

2

Rev_0.53

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

GPP_B12/SLP_ S0#

GPD9/SLP_WLAN#

GPD1/ACPRESENT

GPP_B2/VRALERT#

F43
E43

GPD8/SUSCLK

XCLK_BIASREF

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

GPD6/SLP_A#

GPD3/PW RBT N#

GPD0/BATLOW#

GPP_A11/PME#

BA17 SUSCLK

PCH_KBLU24_IN

E37

XTAL24_IN

E35 PCH_KBLU24_OUT

XTAL24_OUT

RTCX1
RTCX2

SRTCRST#

RTCRST#

KBLU@ KBLU@

Rev_0.53

SLP_SUS#
SLP_LAN#

INTRUDER#

Compal Secret Data

XCLK_BIASREF RC96 1 2 2.7K_0402_1%

E42

AM18 PCH_RTCX1

AM20 PCH_RTCX2

AN18 PCH_SRTCRST#

AM16 PCH_RTCRST #

<DB> Add RX1~4 for KBL U/R Colay
Change XTAL(YC1) to 2016Type

PCH_KBLU24_IN RX1 2 1 33_0402_1% PCH_XTAL24U_IN

KBLU@

CC12

24MHzParrrrrrtttttt::::::
Maiiiiiin::::::SJ10000X700,,,,,, S CRYSTAL 24MHZ 18PF

+--20PPM 8Y24000033((((((TXC))))))::::::2......0x1......6mm

2nd::::::SJ10000TK00,,,,,, S CRYSTAL 24MHZ18PF

+--20PPM7M24000027((((((TXC))))))::::::3......2x2......5mm

AT11 PM_SLP_S0#
AP15 PM_SLP_S3#
BA16 PM_SLP_S4#
AY16 PM_SLP_S5#

AN15 PM_SLP_SUS#

AW15
BB17

AN16 PM_SLP_A#

BA15 PBTN_OUT#

AY15 AC_PRESENT_R 2

AU13 PM_BATLOW # RC108

AU11 EC_PCIE_W AKE#_CPU

AP16 SM_INTRUDER#

AM10 EXT _PWR _GATE#

AM11 SOC_VRALERT#

DecipheredDate

2

SUSCLK <30>

KBLU@

RC92 1M_0402_5%

YC1 KBLU@

24MHZ 18PF XRCGB24M000F2P51R0

3

3

NC NC

SJ10000UJ00

27P_0402_50V

8 J

PM_SLP_SUS# <33>

2 @ 1

RC922 0_0402_ 5%

TP@T298

1

1

4 2

PBTN_O UT# <33>

1

0_0402_5%

+1.0V_CLK5_F24NS

XCLK_BIASREF

PCH_RTCX2

PCH_RTCX1

KBLU@

CC13

27P_0402_50V

8 J

<SI> CC15/CC16 SI change 3.9p=>6.8p

TP@T254
TP@T255
TP@T256
TP@T257
TP@T258

PM_SLP_S3# <12,33,40>
PM_SLP_S4# <12,33,40,49>
PM_SLP_S5# <33>

ACIN <33>

EC_PCIE_W AKE# <30,33>

Compal Electronics,Inc.

Title

SKL-U(5/12)CLK,GPIO

iiiAzeLDocument Number

Custom

CSL50 LA-E791P

1

RC97 1 @ 2 60.4_0402 _1%

1 2

RC98 10M_0402_5%

YC2

32.768KHZ 9PF 10PPM 9H03200055

1 2

SJ10000Q800

6.8P 50V C NPO 0402

CC15

1

SE07168AC80

2

1

CC16

6.8P 50V C NPO 0402

1

SE07168AC80

2

Rev

Sheet 9 of 59Date: Friday, January 05, 2018

v0.3

5

4

3

2

1

UC1F

LPSS ISH

AN8

GPP_B15/GSPI0 _CS#

AP7

GPP_B16/GSPI 0_CLK

AP8

GSPI0_MOSI

D D

TP@T129
TP@T128

<30> W L_OFF#

TP@T133
TP@T132

UART_2_CTXD_DRXD

12

R5194

@

0_0402_5%

UART_2_CRXD_DTXD

C C

SOC_GPIOB21
GSPI1_MOSI

UART_0_CRXD_DTXD
UART_0_CTXD_DRXD

WL_OFF#

UART_2_CRXD_DTXD
UART_2_CTXD_DRXD

Functional Strap Definitions

SPKR (Internal Pull Down):
TOP Swap Override
0 = Disable TOP Swap mode.---> AAX05 Use
1 = Enable TOP Swap Mode.

GPP_B17/GSPI0 _MISO

AR7

GPP_B18/GSPI0 _MOSI

AM5

GPP_B19/GSPI1 _CS#

AN7

GPP_B20/GSPI1 _CLK

AP5

GPP_B21/GSPI 1_MISO

AN5

GPP_B22/GSPI1 _MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_T XD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CT S#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_T XD

AD3

GPP_C22/UART2_RT S#

AD4

GPP_C23/UART2_CT S#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_ SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

SKL-U_BGA1356

Strap Pin

+3VS

RC117 1 @ 2 100K_0402_5% HDA_SPKR

RC118 1 @2 4.7K_0402_5% GSPI0_MOSI

RC201 1 @2 150K_0402_1% GSPI1_MOSI

GSPI0_MOSI (Internal Pull Down):

SKL-U

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0 BDATA/I2C4 B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

6 OF20

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART 1_RXD

GPP_C13/UART1_T XD/ISH_UART 1_TXD
GPP_C14/UART1_RT S#/ISH_UART 1_RTS#
GPP_C15/UART1_CT S#/ISH_UART 1_CTS#

GPP_A12/BM_BUSY#/ISH_GP6

HDA_SPKR <8,32>

Rev_0.53

GPP_D9
GPP_D10
GPP_D11
GPP_D12

GPP_A18/ISH_G P0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_G P5

P2
P3
P4
P1

M4
N3

N1
N2

AD11

AD12

U1
U2

U3

U4
AC1

DGPU_HOLD_RST#

AC2
AC3
AB4

AY8
BA8
BB7

BA7

AY7
AW7
AP13 SOC_GPIOA12

TS_GPIO_CPU <27>

DGPU_PWR_EN <33>

ODD_PW R <37>

ODD_DA# <37>

T122 T P@

CPU THERMAL SENSOR

Address : 0x48

UC3

<7,33> EC_SMB_CK2 EC_SMB_DA2 <7,33>

1

SMBCLK SMBDATA

2

GND

ALERT#

G753T11U_SO T23-5

SA00008CH00

<DB> Change Thermal Sensor IC

5

43

+Vs

+3VS

1

CC127

0.1U_0201_10V6K

2

<5,33> NMI_DBG#_CPU

DGPU_PWR_EN RC382 1

RPC14

1

WL_O FF#
SOC_GPIOB21
NMI_DBG#_CPU 4

DGPU_HOLD_RST# RC923 1 @ 2 10K_0402_5%

ODD_PW R

ODD_DA#

2

3

10K_0804_8P4R_5%

RC929 1 2 10K_0402_5%

RC930 1 2 10K_0402_5%

2 10K_0402_5%

8
7
6
5

+3VS

+3V_PRIM

+3VS

No Reboot
0 = Disable No Reboot mode. --> AAX05 Use
1 = Enable No Reboot Mode. (PCH will disable the TCO

Timer system reboot feature). This function is useful
when runningITP/XDP.

B B

GSPI1_MOSI (Internal Pull Down):
Boot BIOS Strap Bit
0 = SPI Mode --> AAX05 Use
1 = LPC Mode

A A

SecurityClassification

Issued Date

THIS SH E ET O F E NG IN EE R IN G DRAW ING IS TH E P RO P RIE TA R Y P RO PE RTY O F C OM PA L E LECTR ONIC S , INC. AN D C ONTA INS CONFIDENTSIiiAzeL
AN D TR AD E SE CR E T INF ORM A TI ON . TH IS SH EE T MA Y NO T BE TR A N SF ER E D F RO M TH E CU S TO DY OF TH E CO M PE TE N T D IVIS ION OF R& D

DEP ARTM E NT E XC E PT AS A UTH OR IZ ED BY CO M PA L E LEC TRON ICS , INC . NEITHE R THIS S HE E T N OR TH E IN F OR MA TIO N IT CON TA INS

5

4

MA Y BE U S ED BY OR DIS C LOS ED TO A NY THIR D P A RTY W I TH OU T PR IO R W RITTE N C O NS EN T OF CO MP A L E LECT RONIC S , INC.

3

2017/04/10 2019/12/15

Compal Secret Data

DecipheredDate

Compal Electronics,Inc.

Title

SKL-U(6/12)GPIO

Document Number

Custom

2

CSL50 LA-E791P

Sheet 10 of 59Date: Friday, January 05, 2018

1

Rev

v0.3

5

4

3 2

1

UC1H

PCIE/USB3/SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

D D

<29> PCIE_CRX_DTX_N5

*PCIe for DeviceDown
Place AC coupling capacitors very close to either
the transmitter or the receiver.
*TX/RX with Cap

*PCI Express*Connector
Place AC caps closer to the PCIe* connector.
*Only TX with Cap, RX Cap on Add in Card

LAN

WLAN

HDD

C C

ODD

M.2SSD

*For PCIe* Gen 3/ SATA multiplexed configuration,
motherboard Tx requires a 220 nF
AC capacitor and NO AC capacitor is required for
motherboard Rx channel. This option DOES NOT
s*uPplpaocretADCCccaopusplceldosOeDrDsto/tDheviMc.e2sc.

*Only TX with Cap, RXCap on Add inCard

B

A A

onnector.

<29> PCIE_CRX_DTX_P5
<29> PCIE_CTX_C_DRX_N5
<29> PCIE_CTX_C_DRX_P5

<30> PCIE_CRX_DTX_N6

<30> PCIE_CRX_DTX_P6
<30> PCIE_CTX_C_DRX_N6
<30> PCIE_CTX_C_DRX_P6

<37> SATA_CRX_DTX_N0
<37> SATA_CRX_DTX_P0
<37> SATA_CTX_DRX_N0
<37> SATA_CTX_DRX_P0

<37> SATA_CRX_DTX_N1
<37> SATA_CRX_DTX_P1
<37> SATA_CTX_DRX_N1
<37> SATA_CTX_DRX_P1

<31> PCIE_CRX_DTX_N11

<31> PCIE_CRX_DTX_P11
<31> PCIE_CTX_C_DRX_N11
<31> PCIE_CTX_C_DRX_P11

<31> PCIE_CRX_DTX_N12

<31> PCIE_CRX_DTX_P12
<31> PCIE_CTX_C_DRX_N12
<31> PCIE_CTX_C_DRX_P12

CC177 2
CC176 2

CC175 2
CC174 2

RC1201

<5> XDP_PREQ#

CC178 0.22U 6.3V K X5R 04022 1
CC179 0.22U 6.3V K X5R 04022 1

CC180 0.22U 6.3V K X5R 04022 1
CC181 0.22U 6.3V K X5R 04022 1

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

2 100_0402_1% PCIE_RCOMPN

XDP_PREQ#

SOC_GPIOA7

PCIE_CRX_DTX_N5 F16
PCIE_CRX_DTX_P5 E16

PCIE_CTX_DRX_N5 C19
PCIE_CTX_DRX_P5D19

PCIE_CRX_DTX_N6G18

PCIE_CRX_DTX_P6 F18
PCIE_CTX_DRX_N6 D20
PCIE_CTX_DRX_P6 C20

PCIE_RCOMPP

PCIE_CRX_DTX_N11 E28
PCIE_CRX_DTX_P11 E27
PCIE_CTX_DRX_N11 D24
PCIE_CTX_DRX_P11 C24
PCIE_CRX_DTX_N12E30
PCIE_CRX_DTX_P12 F30
PCIE_CTX_DRX_N12A25
PCIE_CTX_DRX_P12 B25

When PCIE8/SATA1A is used
as SATA Port 1 (ODD), then
PCIE11/SATA1B (M.2 SSD)
cannot be used as SATA

Port 1.

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

PCIE5_RXN

PCIE5_RXP
PCIE5_TXN

PCIE5_TXP

PCIE6_RXN

PCIE6_RXP
PCIE6_TXN

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

PCIE11_RXN/SATA1B_RXN

PCIE11_RXP/SATA1B_RXP

PCIE11_TXN/SATA1B_TXN
PCIE11_TXP/SATA1B_TXP

PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0

PCIE12_RXP/SATA2_RXP

PCIE12_TXN/SATA2_TXN

PCIE12_TXP/SATA2_TXP

SKL-U_BGA1356

SKL-U

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN

USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

8OF20

GPIO DEVICE CONTROL

USB_OC0#

USB_OC1#

USB_OC2#

USB2 Port 1 and Port 2

USB2 Port 3

N/A

USB_OC3# N/A

DEVSLP0

DEVSLP1

DEVSLP2

SATA_GP0

SATA_GP1

SATA_GP2

N/A

N/A

NGFF SSD KEY- M

N/A

ODD_PLUG#

PCIE/SATA

Rev_0.53

USB3_1_RXN
USB3_1_RXP

USB3_1_TXN
USB3_1_TXP

USB3_4_RXN
USB3_4_RXP

USB3_4_TXN
USB3_4_TXP

USB2N_1
USB2P_1

USB2N_2

USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB2_COMP

USB2_ID

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E8/SATALED#

H8
G8
C13
D13

J6

H6

B13
A13

J10

H10

B15

A15

E10
F10
C15
D15

AB9

AB10

AD6

AD7

AH3

AJ3

AD9

AD10

AJ1

AJ2

AF6
AF7

AH1
AH2

AF8
AF9

AG1
AG2

AH7
AH8

AB6 USB2_COMP

AG3

USB2_ID

AG4 USB2_VBUSSENSE

A9 USB_OC0 #

C9 USB_OC1#
D9 USB_OC2#
B9 USB_OC3#

DEVSLP0

J1

J2 DEVSLP1

J3

H2 SATA_GP0
H3 ODD_PLUG#

G4 SSD1_IF

H1

USB3_CRX_DTX_N1 <38>

USB3_CRX_DTX_P1 <38>

USB3_CTX_DRX_N1 <38>

USB3_CTX_DRX_P1 <38>

USB3_CRX_DTX_N2 <38>

USB3_CRX_DTX_P2 <38>

USB3_CTX_DRX_N2 <38>

USB3_CTX_DRX_P2 <38>

USB20_N1 <38>
USB20_P1 <38>

USB20_N2 <38>
USB20_P2 <38>

USB20_N3 <39>
USB20_P3 <39>

USB20_N4 <39>

USB20_P4 <39>

USB20_N5 <27>
USB20_P5 <27>

USB20_N6 <30>
USB20_P6 <30>

USB20_N7 <27>
USB20_P7 <27>

RC1191 2 113_0402_1%

T241TP@

USB2.0/USB3.0
USB2.0/USB3.0
USB2.0
CardReader

Camera

BT
TS

DEVSLP2<31>

ODD_PLUG#<37>
SSD1_IF<31>

SATA_LED#<39>

DEVSLP1 1
SOC_GPIOA7

SATA_LED#
SATA_GP0 2 7
SSD1_IF 3 6
ODD_PLUG# 4 5

USB_OC1# 1 8
USB_OC3# 2 7
USB_OC0# 3 6
USB_OC2# 4 5

USB2_ID

RC201 Rshort@20_0402_5%

USB2_VBUSSENSE1

RC21

RC3621

RC361

RPC13

1 8

10K_0804_8P4R_5%

RPC20

10K_0804_8P4R_5%

USB2.0/USB3.0

USB2.0/USB3.0

Rshort@2

0_0402_5%

2
210K_0402_5%

10K_0402_5%

+3V_PRIM

+3VS

B

SecurityClassification

IssuedDate

THIS SHEET OF ENGIN EERING DRAW ING IS THE PROPRIETARY PROP ERT Y OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENSSTiiIzzAeL
AND TRA DE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPET ENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
MAY BE U SED BY OR DISCLOSED TO AN Y THIRD PART Y W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL E LECTRONICS , INC.

5

4

2017/04/10 2019/12/15

3 2

Compal Secret Data

DecipheredDate

Custom

Compal Electronics,Inc.

Title

SKL-U(7/12)PCIE,USB,SATA

DocumentNumber

CSL50 LA-E791P

Sheet

1

Rev

v0.3

11 of 59Date: Friday,January 05,2018

5

4

3 2

1

+1.0V_PRIM TO+1.0V_VCCSTU

+1.2V_VDDQ

+5VALW

1U_0402_6.3V6K

1

CC98

0.1U_0402_2 5V6

D D

<33,40,49>SYSON

<9,33,40,49>PM_SLP_S4#

<33,40,49> SUSP#

<9,33,40> PM_SLP_S3#

C C

RC142 1 2 0_0402_5%
RC144 1 @ 20_0402_5%
RC168 1 2 0_0402_5%
RC194 1 @ 20_0402_5%

1

2

@

CC151

2

+1.8V_PRIM

1

@

2

1U_0402_6.3V6K

CC99

1U_0402_6.3V6K

1

CC97

I (Max) : 0.04 A(+1.0V_VCCSTU)

@

RON(Max) : 25 mohm

2

V drop : 0.001 V

UC5

1

VIN1

2

EN_1.0V_VCCSTU 3

4

EN_1.8VS

VBIAS

5

ON2

6

VIN2

7

EM5209VF_DFN14_2X3

SA00007PM00

I (Max) : 0.536 A(+1.8VS)
RON(Max) : 25 mohm

V drop : 0.013 V

VIN1
ON1

VIN2

+1.0V_PRIM

14

VOUT1

13

VOUT1

VOUT2
VOUT2

GPAD

12 1.0V_VCCSTU_CT1 12

CT1

11 10P_0402_50V8J

GND

10

CT2

9

8

15

R51881 @ 2 0_0603_5%

CC95

1.8VS_CT2 1 2

@CC94

1000P_0402_50V7K

+1.0V_VCCSTU+1.0V_PRIM

+1.8VS

1

CC100

0.1U_0201_10V6K

2

I (Max) : 4.5 A

1

CC96

0.1U_0201_1 0V6K

2

+1.2V_VDDQ
+1.0V_VCCST

+1.0V_PRIM

+1.2V_VCCSFR_OC

+1.0V_VCCSFR

<Cocoa_1113>
Per

543977_SKL_PDDG_Rev0_91,

change CC95 value from
1000pf to 10pf for meet

<= 65us timing for
+1.0V_VCCSTU power rail.

+1.0V_VCCSTU +1.0V_VCCST

RC1401 2 0_0402_5%

AU23
AU28

AU35
AU42

BB23
BB32
BB41
BB47
BB51

AM40

AL23

A18
A22

K20
K21

UC1N

VDDQ_AU23
VDDQ_AU28

VDDQ_AU35
VDDQ_AU42

VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51

VDDQC

VCCST
VCCSTG_A22
VCCPLL_OC
VCCPLL_K20

VCCPLL_K21

SKL-U_BGA1356

+1.0V_PRIM TO +1.0VS_VCCSTG /+1.0VS_VCCIO

+5VALW

+1.0V_PRIM

1

@

2

2 0_0402_5%

CC117

1U_0402_6.3V6K

Imax : 2.77A

0.1U_0201_1 0V6K

1

CC88

2

@

B B

<33> EC_S0IX_EN

For Verify S0IX

+1.0V_PRIM

SUSP# RC1861

RC1871 2 0_0402_5%

<Cocoa_1027>

connect to EC, check /w EC

@

I (Max) : 3 A(+1.0VS_VCCIO)
RON(Max) : 6.2 mohm

V drop : 0.019 V

@

UC6

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON GND

TPS22961DNYR_WSON8

Part Number =SA00007XR00

VOUT

6

5

PSC SideBSC Side

RC189

+1.0VS_VCCSTG_IO

1 @2

SD002000080

0_0805_5%

Imax : 3A

RC208 Follow 544669_SKL_U DDR3L_RVP7_Schematic_Rev0_53

+1.0V_PRIM

CC89

+1.0V_PRIM

CC90 1 20.1U_0201_10V6K

near pin A22

@

1 2 0.1U_0201_10V6K

+1.2V_VDDQ

BSC Side

RC1431 2 0_0402_5%

+1.2V_VDDQ

CPU POWER 3 OF4

14 OF20

PSC Side

1

2

+1.0V_VCCSFR

1

2

SKL-U

1U_0402_6.3V6K

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

CC48

Rev_0.53

VCCIO
VCCIO

VCCIO
VCCIO

VCCIO
VCCIO
VCCIO

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

RC208 Follow 544669_SKL_U DDR3L_RVP7_Schematic_Rev1.0

1U_0402_6.3V6K

CC55

+1.0V_PRIM

AK28
AK30

AL30
AL42

AM28
AM30
AM42

AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30

AM23VCCIO_SENSE

AM22VSSIO_SENSE

VSSSA_SENSE

H21

H20 VCCSA_SENSE

I (Max) : 3.4 A

+VCC_SA

I (Max) : 5 A

T124TP@
T125TP@

VSSSA_SENSE <52>
VCCSA_SENSE <52>

+1.0V_PRIM

BSC SidePSC Side

BSC SidePSC Side

1U_0402_6.3V6K

1

CC56

2

1

CC27

2

A A

1

CC28

2

2

5

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1U_0201_6.3V6K

1U_0201_6.3V6K

1

CC29

2

1U_0201_6.3V6K

1

CC30

1

CC31

2

2

1U_0402_6.3V6K

1U_0201_6.3V6K

1

CC32

2

1U_0402_6.3V6K

1

CC33

1

CC34

2

2

4

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CC36

CC35

CC47 Follow 543016_SKL_U_Y_PDG_0_9

2

SecurityClassification

IssuedDate

THIS SHEET OF ENGINEERING DRAW ING IS TH E PROPRIETA RY PRO PERTY OF C OMPAL EL ECT RONICS, INC. AND CONTAINS CONFIDENSTiIzAeL
AND TRA DE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZE D BY CO MPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMA TIO N IT CONTAINS
MAY BE U SED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONS ENT OF COMPAL ELEC TRO NICS, INC.

3 2

1U_0402_6.3V6K

1

CC47

2

2017/04/10 2019/12/15

Compal Secret Data

DecipheredDate

10U_0603_6.3V6M

1

1

CC37

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CC38

2

10U_0603_6.3V6M

1

CC39

CC40

2

+1.35V_VDDQ_CPU : 10UF/6.3V/0603 *6

Custom

1

2

1UF/6.3V/0402 * 4

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CC41

2

Title

Document Number

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CC42

1

CC43

2

2

1U_0402_6.3V6K

1

CC44

CC45

2

Compal Electronics,Inc.

SKL-U(8/12)Power

CSL50 LA-E791P

Sheet 12

1

1U_0402_6.3V6K

1

CC46

2

Rev

v0.3

of

59Date: Friday, January05,2018

5

+1.0V_PRIM

RC148 1 Rshort@20_0603_5%

D D

@

+1.0V_APLL

22U_0603_6.3V6

M

1

2

+3V_PRIM

22U_0603_6.3V6

M

1

CC134

CC142

@

2

RC150 1 Rshort@20_0402_5%

1U_0402_6.3V6

K

1

CC72

2

Follow 543016_SKL_U_Y_PDG_1_0

+1.0V_CLK5_F24NS

RC152 1 Rshort@20_0603_5%

10U_0402_6.3V6

M

10U_0402_6.3V6

M

1

1

@

@

+1.0V_CLK4_F100OC

RC190 1 Rshort@20_0603_5%

@

C C

Imax : 2.57A

near pin AF18,
AF19,V20,V21

RC175 1 Rshort@20_0402_5%

B B

RC169 1 Rshort@20_0603_5%

RC162 1 Rshort@20_0402_5%

2

22U_0603_6.3V6

M

1

2

@

CC130

CC135

2

22U_0603_6.3V6

M

1

CC137

CC136

@

2

+1.0V_PRIM

+1.0V_MPHYAON

+1.0V_CLK6_24T BT

1U_0402_6.3V6

K

1

@

CC86

2

+1.0V_DTS

1U_0402_6.3V6

K

1

CC76

2

1U_0402_6.3V6

K

1

CC87

2

1U_0402_6.3V6

K

1

CC75

2

+3V_PRIM

RC197 1 Rshort@20_0402_5%

1U_0402_6.3V6

K

1

@

CC67

10U_0402_6.3V6

M

1

@

CC139

CC138

2

RC154 1 Rshort@20_0402_5%

RC161 1 Rshort@20_0402_5%

RC163 1 Rshort@20_0402_5%

RC1721 Rshort@20_0402_5%

RC167 1 Rshort@20_0402_5%

RC171 1 Rshort@20_0402_5%

2

22U_0603_6.3V6

M

1

@

2

Follow 543016_SKL_U_Y_PDG_0_9

+1.0V_PRIM +3V_PRIM +1.8V_PRIM

A A

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

1

CC112

CC111

@

@

2

2

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

1

CC114

CC113

@

@

2

2

22U_0402_6.3V6

M

22U_0402_6.3V6

M

1

1

CC116

@

@

2

2

+3VS

CC115

RC178 1 Rshort@20_0402_5%

+3VALW

RC173 1 Rshort@20_0603_5%

Follow 543016_SKL_U_Y_PDG_0_9

5

4

+3V_HDA

+3V_PGPPA

+3V_SPI

+3V_PGPPB

K

1

2

+3V_PGPPC

K

1

2

+3V_1.8V_PGPPD

K

1

@

2

+3V_PGPPE

K

1

2

+3V_PRIM_RTC

K

1

2

4

1

CC63

1U_0201_6.3V6K

2

1U_0402_6.3V6

CC102

1U_0402_6.3V6

CC73

RC2061 @ 2 0_0402_5%

1U_0402_6.3V6

CC103

1U_0402_6.3V6

CC74

0.1U_0201_10V6

1U_0402_6.3V6

1

K CC78

CC77

2

+3VS_PGPPA

+3VALW_DSW

+1.8V_PRIM

3

M

1

near pin K15,L 15

2

near pin N18

near pin AF20,
AF21,T19, T20

near pin N15, N16,
N17,P15,P16

K

1

2

NEEDTOCHECK
BOM

3

2

22U_0603_6.3V6

1U_0402_6.3V6

CC147

@

CC80

+1.0V_PRIM

22U_0603_6.3V6

M

1

CC148

2

+1.0V_PRIM

+1.0V_PRIM

+1.0V_PRIM

22U_0603_6.3V6

M

1

CC81

2

1U_0402_6.3V6

K

1

CC61

@

2

+1.0VO_DSW

1U_0402_6.3V6

K

CC68

1

2

1U_0201_6.3V6

K

1

CC141

2

22U_0603_6.3V6

M

1

@

CC82

2

+1.0V_PRIM

1U_0201_6.3V6

K

1

+1.0V_MPHYAON

CC85

+1.0V_PRIM

2

+1.0V_PRIM

+1.0V_APLL

+1.0V_PRIM

+3VALW_DSW

+3V_HDA
+3V_SPI

+1.0V_PRIM

+3V_PRIM
+1.0V_PRIM

+1.0V_PRIM

Per 543016_SKL_U_Y_PDG_0_9

VCCRTC does not exce ed 3.2 V From P DG

Power Rail Voltage

1U_0201_6.3V6

K

1

2

2.574A

1.87A

0.64A

+1.0V_PRIM

CC91

CPUPOWER4 OF4

SKL-U

15 OF20

RTCBattery

MAX. 8000mil

UC1O

0.69A

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0 DCPRTC

L15

VCCAMPHYPLL_1P 0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

SKL-U_BGA1356

CC7 Close UC1.AK19.

+RTCVCC

+CHGRTC 3.383V(MAX)

BAT54C(VF) 240 mV

+3VL_RTC 3.143V

Result : Pass

1U_0201_6.3V6K

CC7

1

2

15mils

1

BAV70W 3P C/C_SOT-323

SC600000B00

KabylakeNoSupportDeepS3.

+3VALW TO +3V_PRIM

I (Max) : 0.1 A

+1.2V_VCCSFR_OC

+1.2V_VDDQ

SecurityClassification

Issued Date

THIS SH E ET O F E NG IN EE R IN G DRAW ING IS TH E P RO P RIE TA R Y P RO PE RTY O F C OM PA L E LECTR ONIC S , INC. AN D C ONTA INS CONFIDENTSIiiAzeL
AN D TR AD E SE CR E T INF ORM A TI ON . TH IS SH EE T MA Y NO T BE TR A N SF ER E D F RO M TH E CU S TO DY OF TH E CO M PE TE N T D IVIS ION OF R& D

DEP ARTM E NT E XC E PT AS A UTH OR IZ ED BY CO M PA L E LEC TRON ICS , INC . NEITHE R THIS S HE E T N OR TH E IN F OR MA TIO N IT CON TA INS
MA Y BE U S ED BY OR D IS CLOS E D TO A N Y TH IRD P AR TY W ITH O UT P RIO R W R ITTE N C ON S EN T OF C O MP AL ELE CTR ONIC S , I NC.

1

CC150

1U_0402_6.3V6

K

2

2017/04/10 2019/12/15

RC141

1

2

0_0402_5%

Compal Secret Data

DecipheredDate

0.1U_0201_10V6

1

K CC49

2

2

+3VALW

Rev_0.53

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19
VCCRTC_BB14

VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5

VCCCLK6

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

+RTCBAT T_R

DC1

2 2
3

@

Title

Document Number

Custom

1

1209_follow G group GPIO

CC71 0.1U_0201_10V6K

From Battery

15mils15mils

1

RC393

+3V_LID

powe rail to +3V_PRIM

+3V_PGPPA
+3V_PGPPB
+3V_PGPPC
+3V_1.8V_PGPPD
+3V_PGPPE
+1.8V_PRIM
+3V_PRIM For SD CARD

+3V_PRIM
+1.0V_DTS
+1.8V_PRIM

+3V_PRIM_RTC

+RTCVCC

+1.0V_CLK6_24T BT

+1.0V_APLL
+1.0V_CLK4_F100OC
+1.0V_CLK5_F24NS
+1.0V_CLK6_24T BT

2

AK15
AG15
Y16
Y15
T16
AF16
AD15

V19
T1
AA1
AK17
AK19

BB14
BB10 +DCPRTC 1 2
A14
K19
L21
N20
L19
A10
AN11 PRIMCORE_VID0

AN13 PRIMCORE_VID1

1K_0402_5%

RC19

+3VL

I (Max) : 0.46A(+3V_PRIM)
RDS(Typ) : 65 mohm

V drop : 0.03 V

1

1U_0402_6.3V6

K CC50

2

Compal Electronics,Inc.

SKL-U(9/12)Power

CSL50 LA-E791P

1

T130 TP@
T131 TP@

1

0_0805_5%

Sheet 13 of 59Date: Friday, January 05, 2018

+3V_PRIM

0.1U_0201_10V6

1

K CC51

2

Rev

v0.3

5

4

3

2

1

VCCGT_SEN SE
VSSGT_SENSE

+VCC_ GT

AA 63
AA 64
AA 66
AA 67
AA 69
AA 70
AA 71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71

A48
A 53
A 58
A 62
A 66

J 43
J 45
J 46
J 48
J 50
J 52
J 53
J 55
J 56
J 58
J 60
K 48
K 50
K 52
K 53
K 55
K 56
K 58
K 60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
M62
N63
N64
N66
N67
N69

J70
J 69

UC1M

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGT

VCCGT_S ENSE

VSSGT_S ENSE

SKL-U_BGA 1356

CPUPOWE R2 OF 4

SKL-U

13 OF 20

Rev_0.53

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGTX_ AK 42
VCCGTX_ AK 43
VCCGTX_ AK 45
VCCGTX_ AK 46
VCCGTX_ AK 48
VCCGTX_ AK 50
VCCGTX_ AK 52
VCCGTX_ AK 53
VCCGTX_ AK 55
VCCGTX_ AK 56
VCCGTX_ AK 58
VCCGTX _AK 60
VCCGTX _AK 70
VCCGTX _AL43
VCCGTX _AL46
VCCGTX _AL50
VCCGTX _AL53
VCCGTX_ AL56

VCCGTX_ AL60
VCCGTX_ AM 48
VCCGTX_ AM 50
VCCGTX_ AM 52
VCCGTX_ AM 53
VCCGTX_ AM 56
VCCGTX_ AM 58
VCCGTX_ AU 58
VCCGTX_ AU 63

VCCGTX_ BB 57

VCCGTX_ BB66

VCCGTX_ SENSE

VSSGTX_SEN SE

+VCC_ GT+VCC_ CORE +VCC_ CORE

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK4 2
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60

AK 70

AL43
AL46
AL50
AL53

AL56
AL60
AM48

AM5 0
AM5 2
AM5 3
AM5 6
AM5 8
AU58
AU63

BB5 7

BB66

AK62V CCGTX_SE NSE

AL61 VSSGTX_ SENSE

+VCC_ GTX_VR

1

1 2

JUMP_ 43X39_ 0805

For CPU2+3e SKU

T155 TP@
T219 TP@

JU4 2B

2

JUMP@

+VCC_ CORE

2

JUMP@

2

2

JUMP@

RC920 0_0402_5%

+VCC_ GT_VR

1 @ 2

JU4 2A

1

+VCC_ CORE

+VCC_ GT

Trace Length < 25 mils

VCC CORE _SEN SE < 52>

VSS CORE _SEN SE <52>

VR_SV ID_CLK <52>

+1.0V _PRIM

CPUPOWE R1 OF 4

VR_AL ERT# <52>

SKL-U

12 OF20

Rev_0.53

VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42

VCC_J 30
VCC_J 33
VCC_J 37
VCC_J 40
VCC_K 33
VCC_K 35
VCC_K 37
VCC_K 38
VCC_K 40
VCC_K 42
VCC_K 43

VCC _SEN SE

VSS_SENS E

VIDALE RT#

VIDSCK

VIDS OUT

VCCSTG_ G20

G32

G33
G35
G37
G38
G40

G42
J30
J33
J37
J 40
K 33

K35
K37
K38
K40
K42
K43

E32

E33

B63 SO C_SVID_A LERT#

A63

D64 VR_S VID_DATA

G20

(To VR)

UC1L

A30

VCC_A 30

A34

VCC_A 34

A39

VCC_A3 9

A 44

VCC_A 44

AK 33

VCC_AK 33

AK35

VCC_AK 35

AK3 7

VCC_AK 37

2

220_040 2_5%

AK38

VCC_AK 38

AK 40

VCC_AK 40

AL33

VCC_AL 33

AL37

VCC_AL 37

AL40

VCC_AL 40

AM32

VCC_AM 32

AM33

VCC_AM 33

AM35

VCC_AM 35

AM37

VCC_AM 37

AM38

VCC_AM 38

G30

VCC_G30

K32

RSVD_K32

AK3 2

RSVD_AK32

AB6 2

VCCOPC _AB 62

P 62

VCCOPC _P62

V 62

VCCOPC _V62

H63

VCC_OPC _1P8_H63

G61

VCC_OP C_1P8_ G61

AC63

VCC OPC_ SENS E

AE 63

VSS OPC _SENS E

AE6 2

VCCEOP IO

AG62

VCCEOP IO

AL63

VCCEOP IO_SENS E

AJ 62

VSSEOPIO_ SENSE

SKL-U_BGA 1356

+ 1.0V_V CCST

Pla ce th e PU

resi stor s cl ose to CPU

RC179
56_0402 _5%

2 1

D D

For CPU2+3e SKU

C C

SVID ALERT

SOC_SV ID_ALER T# 1

RC180

1 2

JUMP_ 43X39_ 0805

JU22

1

1

JUMP_ 43X39_ 0805

JU42A/JU42B for KBLR
JU221 for KBLU

SOC PINS K52 AND AK52
SHOULD BE LEFT UNCONNECTED
FOR KBL R U42 DESIGNS

< 52> VC CGT_SENS E
< 52> VS SGT_SEN SE

Trace Length < 25 mils

+1.0V _VCCST

SVID DATA

B B

A A

5

Plac e t he PU
resi sto rs c lose to CPU

12

RC181
100_040 2_1%

VR_SV ID_DATA <52> (To VR)

Security Classification

Issued Date

THIS SHE ET OF ENGIN EERIN G DRAW ING IS THE PROPR IETAR Y PROP ERTY OF COM PAL E LECTR ONICS, INC. A ND CON TAINS CONFID EN A ND
TRADE SECR ET IN FORMA TION. THIS SHE ET MAY NOT BE TRA NSFERE D F ROM THE CUS TODY OF THE COM PETEN T DIV ISION OF R&
DEPAR TMENT EXC EPT AS A UTHORIZED BY COMPA L ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATI ON IT CONTAINS
MAY BE USED BY OR DISCLOS ED TO ANY THIRD P ARTY W ITHOUT PRIOR W RITTEN CONSENT OF C OMPAL ELECTRON ICS, INC.

4

3

2017/04/10

Compal Secret Data

Deciphered Date

2019/12/15

2

Compal Electronics,Inc.

Title

SKL-U(10/12)Power,SVID

TAI L

Siizee

Docum entN umber

D

Custom

CSL50 LA-E791P

Date: Friday, January 05, 2018 Sheet 14 of 59

1

Rev

v0.3

5

4

3 2

1

D D

A5

VSS

A67

VSS

A70

VSS

AA2

VSS

AA4

VSS

AA65

VSS

AA68

VSS

AB15

VSS

AB16

VSS

AB18

VSS

AB21

VSS

AB8

VSS

AD13

VSS

AD16

VSS

AD19

VSS

AD20

VSS

AD21

VSS

AD62

VSS

AD8

VSS

AE64

VSS

AE65

VSS

AE66

VSS

AE67

VSS

AE68

C C

B B

AE69

AF1
AF10
AF15
AF17

AF2

AF4
AF63

AG16
AG17
AG18
AG19
AG20
AG21
AG71

AH13

AH6

AH63
AH64
AH67

AJ15

AJ18

AJ20

AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69

AK8
AL28

AL32
AL35
AL38

AL45
AL48

AL52
AL55
AL58
AL64

AJ4

AL2

AL4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS

VSS
VSS
VSS
VSS

SKL-U

UC1P

GND 1 OF3

16OF20

SKL-U_BGA1356

SKL-U

AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38

AV1

AV68

AV69
AV70

AV71

AW10

AW12
AW14

AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57

AW6
AW60
AW62
AW64
AW66

AW8

AY66

B10
B14

B18

B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71

BA1
BA10
BA14
BA18

BA2
BA23
BA28

BA32
BA36

F68
BA45

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS
VSS
VSS

VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS

VSS
VSS

UC1Q

GND 2 OF3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS
VSS
VSS

VSS
VSS

VSS
VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS

VSS
VSS
VSS
VSS

VSS
VSS

VSS
VSS
VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS
VSS

VSS
VSS

Rev_0.53 Rev_0.53

AL65

VSS

AL66

VSS

AM13

VSS

AM21

VSS

AM25

VSS

AM27

VSS

AM43

VSS

AM45

VSS

AM46

VSS

AM55

VSS

AM60

VSS

AM61

VSS

AM68

VSS

AM71

VSS

AM8

VSS

AN20

VSS

AN23

VSS

AN28

VSS

AN30

VSS

AN32

VSS

AN33

VSS

AN35

VSS

AN37

VSS

AN38

VSS

AN40

VSS

AN42

VSS

AN58

VSS

AN63

VSS

AP10

VSS

AP18

VSS

AP20

VSS

AP23

VSS

AP28

VSS

AP32

VSS

AP35

VSS

AP38

VSS

AP42

VSS

AP58

VSS

AP63

VSS

AP68

VSS

AP70

VSS

AR11

VSS

AR15

VSS

AR16

VSS

AR20

VSS

AR23

VSS

AR28

VSS

AR35

VSS

AR42

VSS

AR43

VSS

AR45

VSS

AR46

VSS

AR48

VSS

AR5

VSS

AR50

VSS

AR52

VSS

AR53

VSS

AR55

VSS

AR58

VSS

AR63

VSS

AR8

VSS

AT2

VSS

AT20

VSS

AT23

VSS

AT28

VSS

AT35

VSS

AT4

VSS

AT42

VSS

AT56

VSS

AT58

VSS

17OF20

SKL-U_BGA1356

BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30

BB34
BB38

BB43
BB55

BB6
BB60

BB64
BB67
BB70

C1
C25

C5
D10

D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58

D6
D62

D66
D69
E11
E15
E18

E21

E46
E50
E53
E56

E6
E65

E71
F1

F13
F2

F22
F23
F27
F28
F32
F33
F35
F37

F38

F4
F40

F42
BA41

G10
G22
G43
G45
G48

G52
G55
G58

G60

G63
G66

H15
H18

H71

K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71

F8

VSS
VSS

VSS
VSS
VSS
VSS

G5

VSS
VSS

VSS
VSS

G6

VSS
VSS

VSS
VSS

VSS
VSS

VSS

J11

VSS

J13

VSS

J25

VSS

J28

VSS

J32

VSS

J35

VSS

J38

VSS

J42

VSS

J8

VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

L11

VSS

L16

VSS

L17

VSS

UC1R

GND 3 OF3

SKL-U_BGA1356

SKL-U

18OF20

Rev_0.53

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS

VSS
VSS
VSS
VSS

L18
L2

L20
L4

L8
N10

N13
N19
N21

N6

N65
N68

P17
P19

P20
P21

R13
R6

T15
T17
T18

T2
T21

T4
U10

U63
U64
U66
U67
U69
U70
V16
V17
V18
W13

W6
W9

Y17
Y19
Y20
Y21

A A

SecurityClassification

IssuedDate

THIS SHEET OF ENGIN EERING DRAW ING IS THE PROPRIETARY PROP ERT Y OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENSSTiIzAeL
AND TRA DE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPET ENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS

5

4

MAY BE U SED BY OR DISCLOSED TO AN Y THIRD PART Y W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL E LECTRONICS , INC.

2017/04/10 2019/12/15

3 2

Compal Secret Data

DecipheredDate

Custom

Title

DocumentNumber

Compal Electronics,Inc.

SKL-U(11/12)GND

CSL50 LA-E791P

Sheet

1

Rev

v0.3

15 of 59Date: Friday,January 05,2018

5

D D

<5>CFG3

C C

<5> XDP_ITP_PMODE

B B

CFG_RCOMPE60

XDP_ITP_PMODE E8

SI1/15

CFG4 E70

4

E68

CFG[0]

B67

CFG[1]

D65

CFG[2]

D67

CFG[3]

CFG[4]

C68

CFG[5]

D68

CFG[6]

C67

CFG[7]

F71

CFG[8]

G69

CFG[9]

F70

CFG[10]

G68

CFG[11]

H70

CFG[12]

G71

CFG[13]

H69

CFG[14]

G70

CFG[15]

E63

CFG[16]

F63

CFG[17]

E66

CFG[18]

F66

ITP_PMODE

AY2

RSVD_AY2

AY1

D1

RSVD_D1

D3

RSVD_D3

K46

RSVD_K46

K45

RSVD_K45

AL25

RSVD_AL25

AL27

C71

RSVD_C71

B70
F60
A52

BA70

RSVD_TP_BA70

BA68

RSVD_TP_BA68

J71

RSVD_J71

J68

RSVD_J68

F65

VSS_F65

G65

F61

RSVD_F61

E61

RSVD_E61

UC1S

CFG[19]
CFG_RCOMP

RSVD_AY1

RSVD_AL27

RSVD_B70

RSVD_F60
RSVD_A52

VSS_G65

SKL-U_BGA1356

RESERVED SIGNALS-1

SKL-U

19OF20

Rev_0.53

RSVD_TP_BB68
RSVD_TP_BB69

RSVD_TP_AK13
RSVD_TP_AK12

RSVD_BB2
RSVD_BA3

TP5
TP6

RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2

RSVD_B3
RSVD_A3

RSVD_AW1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4

RSVD_C4

RSVD_A69
RSVD_B69

RSVD_AY3

RSVD_D71

RSVD_C70

RSVD_C54

RSVD_D54

TP1
TP2

VSS_AY71

ZVM#

RSVD_TP_AW71
RSVD_TP_AW70

MSM#

PROC_SELECT#

3 2

BB68
BB69

AK13
AK12

BB2
BA3

AU5

AT5

D5
D4
B2

Remove T166 / T167 for 24MHz GND shielding

C2

B3

A3

AW1
E1

E2

BA4

BB4

A4

C4
BB5

TP4

A69

B69

AY3
D71

C70

C54

D54
AY4

BB3
AY71

PM_ZVM#

AR56

AW71

AW70
AP56PM_MSM#

C64 SKL_CNL#

T158TP@
T159TP@

T162TP@
T163TP@

T252TP@

RC1821 2 0_0402_5%

1 RC183 2 0_0402_5%

T225TP@

T230TP@

1 @ 2

RC184 100K_0402_5%

+1.0V_VCCST

Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0

<DB> Add ball E3/C7 for KBL U/R Colay

UC1T

AW69

RSVD_AW69

AW68

RSVD_AW68

AU56

RSVD_AU56

AW48

RSVD_AW48

PCH_KBLR24_OUT

PCH_KBLR24_OUTRX4 2 KBLR@ 1 33_0402_1%PCH_XTAL24R_OUT1 KBLR@ 2

For 2+3e Solution
PM_ZVM#

PM_MSM#

C7

RSVD_C7

U12

RSVD_U12

U11

RSVD_U11

H11

RSVD_H11

SKL-U_BGA1356

PCH_KBLR24_IN RX3 2KBLR@ 1 33_0402_1%PCH_XTAL24R_IN

SKL-U

SPARE

Rev_0.53

RSVD_F6
RSVD_E3
RSVD_C11

RSVD_B11

RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52

20OF20

RC915 1M_0402_5%

24MHZ 18PFXRCGB24M000F2P51R0

3

3 1

27P_0402_50V8J

KBLR@

CC168

24MHzParrrttt::::::
Maiiiiiin::::::SJ10000X700,,,,,,S CRYSTAL 24MHZ 18PF+-20PPM
8Y24000033(((TXC)))
2nd::::::SJ10000TK00,,,,,,S CRYSTAL24MHZ18PF+-20PPM
7M24000027(((TXC)))

1

F6
E3 PCH_KBLR24_IN
C11
B11
A11
D12
C12
F52

KBLR@

YC3 SJ10000UJ00

NC NC

4 2

1

27P_0402_50V8J

KBLR@

CC169

CFG_RCOMP1

RC185

CFG4

RC193

A A

Display Port Presence Strap

CFG4

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

5

2

49.9_0402_1%

2

1

1K_0402_1%

SecurityClassification

IssuedDate

THIS SHEET OF ENGINEERING DRAW ING IS TH E PROPRIETA RY PRO PERTY OF C OMPAL EL ECT RONICS, INC. AND CONTAINS CONFIDENSTiIzAeL
AND TRA DE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZE D BY CO MPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMA TIO N IT CONTAINS

4

MAY BE U SED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONS ENT OF COMPAL ELEC TRO NICS, INC.

2017/04/10 2019/12/15

3 2

Compal Secret Data

DecipheredDate

Document Number

Custom

Compal Electronics,Inc.

Title

SKL-U(12/12)RSVD

CSL50 LA-E791P

Sheet

1

Rev

16 of 59Date: Friday,January05,2018

v0.3

5

CHANNEL-A

4

REVERSE TYPE

Interleaved Memory

TOP: JDIMM1 CONN Non-ECC DIMM

D D

@

2

1

1

RD1

0_0402_5%

RD3
0_0402_5%

2

1

@

2

1

2

RD4

0_0402_5%

SA1_CHA_DIM1SA0_CHA_DIM1

RD5
0_0402_5%

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL A :

WRITE ADDRESS: 0XA0
READ ADDRESS: 0XA1
SA0 = 0; SA1 = 0; SA2 = 0.

DDR4 POR OPERATING SPEED: 1867 MT/S

C C

STRETCH GOAL IS 2133 MT/S

Layout Note:
Place near JDIMM1.257,259

+2.5V +0.6V_0.6VS

10U_0603_6.3V6

M

1

1

CD3

2

2

Layout Note:
PLACE THE CAP near JDIMM1. 164

B B

+0.6V_DDR_VREFCA

2 2

CD11 CD12

0.1U_0201_10V6K 12.2U_0402_6.3V6M

1

Layout Note:
Place near JDIMM1

10U_0603_6.3V6

M

10U_0603_6.3V6

M

1 1 1 1 1 1 1

CD93

A A

CD16

2

2

10uF*2
1uF*2

@ESD@

0.1U_0201_10V6

10U 6.3V M X5R 0603 H0.8

1U_0402_6.3V6

K

1

CD4

2

10U_0603_6.3V6

M

CD17

2

2

K

1U_0402_6.3V6

K

1

1

CD5

2

10U_0603_6.3V6

M

CC159

CD6

2

2.2uF*1

0.1uF*1

10uF*6
1uF*8
330uF*1

10U_0603_6.3V6

M

10U_0603_6.3V6

M

CD18

CD19

2

2

5

+3VS+3VS+3VS

1

RD2

@

0_0402_5%

2

SA2_CHA_DIM1

1

RD6
0_0402_5%

2

+3V_PRIM_DA

0.1U_0201_10V6

K

CD1

2

1

PLACE NEAR TO PIN

Layout Note:
Place near JDIMM1.258

10uF*2
1uF*1

10U_0603_6.3V6

M

10U_0603_6.3V6

M

1

2

10U_0603_6.3V6

M

10U_0603_6.3V6

M

10U_0603_6.3V6

M

1

1

CD21

CD20

CD22

CD23

2

2

2

@

1U_0402_6.3V6

K

1

1

CD8

CD7

RD32 0_0402_5%

2

1 2

CD9

2

+3V_PRIM_DA+3V_PRIM

+1.2V_VDDQ+1.2V_VDDQ

10U_0603_6.3V6

M

1U_0402_6.3V6

K

1U_0402_6.3V6

1 1 1

CD95

CD96

2

K

2

1

2

K

CD24

2

<6> DDR_M0_D[0..15]
<6> DDR_M0_D[16..31]
<6> DDR_M0_D[32..47]

<6> DDR_M0_D[48..63]

+1.2V_VDDQ

2.2U_0402_6.3V6M

+0.6V_DDR_VREFCA

2

CD2

1

Part Number:LTCX0069GA0
Part Value:S SOCKET FOX AS0A827-H2RB-7H 260P DDR4

JDIMM1B

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND

FOX_AS0A827-H2RB-7H

CONN@

STD

141

VDD11

142

VDD12

147

VDD13

148

VDD14

153

VDD15

154

VDD16

159

VDD17

160

VDD18

163

VDD19

258

VTT

257

VPP1

259

VPP2

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

261

GND

+1.2V_VDDQ

1U_0402_6.3V6

K

1U_0402_6.3V6

1U_0402_6.3V6

1U_0402_6.3V6

1U_0402_6.3V6

K

1U_0402_6.3V6

K

1

CD25

2

K

1 1 1 1 1 1

CD26

CD27

2

2

4 3

K

1U_0402_6.3V6

K

1U_0402_6.3V6

CD29

CD28

2

2

K

CD31

CD30

2

CD94

2

C174

330U_2.5V_M

3

+1.2V_VDDQ

+0.6V_0.6VS

+2.5V

+1.2V_VDDQ

PLACE NEAR TO SODIMM

1

+

Part Number =SF000006S00

2

2

JDIMM1A

DDR_M0_CLK0
DDR_M0_CLK#0
DDR_M0_CLK1
DDR_M0_CLK#1

DDR_M0_CKE0
DDR_M0_CKE1

DDR_M0_CS#0
DDR_M0_CS#1

DDR_M0_ODT0
DDR_M0_ODT1

DDR_M0_BG0
DDR_M0_BG1
DDR_M0_BA0
DDR_M0_BA1

DDR_M0_MA0
DDR_M0_MA1
DDR_M0_MA2
DDR_M0_MA3
DDR_M0_MA4
DDR_M0_MA5
DDR_M0_MA6
DDR_M0_MA7
DDR_M0_MA8
DDR_M0_MA9
DDR_M0_MA10
DDR_M0_MA11
DDR_M0_MA12
DDR_M0_MA13

DDR_M0_MA14_WE# 151
DDR_M0_MA15_CAS# 156

DDR_M0_MA16_RAS# 152
DDR_M0_ACT#
DDR_M0_PAR

DDR_M0_ALERT# 116

DIMM1_CHA_EVENT# 134

DDR_DRAMRST#_R108

PCH_SMBDATA
PCH_SMBCLK

SA2_CHA_DIM1 166

SA1_CHA_DIM1
SA0_CHA_DIM1

256

9/8 Modify

RD7 2 1
240_0402_<1

<6> DDR_M0_CLK0
<6> DDR_M0_CLK#0
<6> DDR_M0_CLK1
<6> DDR_M0_CLK#1

<6> DDR_M0_CKE0
<6> DDR_M0_CKE1

<6> DDR_M0_CS#0
<6> DDR_M0_CS#1

<6> DDR_M0_ODT0
<6> DDR_M0_ODT1

<6> DDR_M0_BG0
<6> DDR_M0_BG1
<6> DDR_M0_BA0
<6> DDR_M0_BA1

<6> DDR_M0_MA0
<6> DDR_M0_MA1
<6> DDR_M0_MA2
<6> DDR_M0_MA3
<6> DDR_M0_MA4
<6> DDR_M0_MA5
<6> DDR_M0_MA6
<6> DDR_M0_MA7
<6> DDR_M0_MA8
<6> DDR_M0_MA9
<6> DDR_M0_MA10
<6> DDR_M0_MA11
<6> DDR_M0_MA12
<6> DDR_M0_MA13

<6> DDR_M0_MA14_WE#

<6> DDR_M0_MA15_CAS#

<6> DDR_M0_MA16_RAS#
<6> DDR_M0_ACT#
<6> DDR_M0_PAR

<6> DDR_M0_ALERT#

6,18> DDR_DRAMRST#_R

<7,18> PCH_SMBDATA
<7,18> PCH_SMBCLK

For ECC DIMM

+1.2V_VDDQ

DDR_DRAMRST#_R

@ESD@

CD10

0.1U_0402_25V6

2 1

+1.2V_VDDQ

DIMM Side

+0.6V_DDR_VREFCA

RD8

2

@

CD13

0.1U_0402_10V6K

1

SecurityClassification

Issued Date

THIS SH E ET O F E NG IN EE R IN G DRAW ING IS TH E P R OP RIE TA RY P RO P ER TY O F C OM P AL E LEC TRONI CS , INC . A ND C ONTA INS CONFIDENTSIiAzeL
AN D TR AD E SE CR E T INF ORM A TI ON . TH IS S H EE T MA Y NO T BE TR A N SF ER E D F RO M TH E CU S TO DY OF TH E CO M PE TE N T D IVIS ION OF R & D
DEP ARTM E NT E XC E PT AS A UTH OR IZ ED BY CO M PA L E LEC TRONI CS , INC . NEITHE R THIS SH E ET NO R TH E IN FO RM A TIO N IT C ONTA INS M
AY BE US E D BY OR DIS CLO SE D TO AN Y THIRD P A RTY W ITH OU T PR IO R WR ITTE N C O NS EN T OF CO MP AL ELE CTR ONICS , IN C.

1K_0402_1%

1 2

1 RD9

2_0402_1%

RD10
1K_0402_1%

1 2

2017/04/10 2019/12/15

2

CD14

0.1U_0402_10V6K

1

Compal Secret Data

DecipheredDate

2

STD

137

CK0(T)

139

CK0#(C) DQ1

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

A14_W E#
A15_CAS#

A16_RAS#

114

ACT#

143

PARITY

ALERT#

EVENT#
RESET#

254

SDA

253

SCL

SA2

260

SA1

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7# DQS6(T)

96

DM8#/DBI8# DQS6#(C)

FOX_AS0A827-H2RB-7H

CONN@

CPU Side

+0.6V_VREFCA

2

DQ0
DQ2

DQ3
DQ4
DQ5

DQ6
DQ7

DQS0(T)

DQS0#(C)

DQ8
DQ9

DQ10

DDR_M0_D9

DQ12
DQ13
DQ14

DDR_M0_DQS1

DQS1(T)

DQS1#(C)

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQS2(T)

DQS2#(C)

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS3(T)

DQS3#(C)

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS4(T)

DQS4#(C)

DQ40
DQ41
DQ42

DQ43
DQ44

DQ45
DQ46

DQ47

DQS5(T)

DQS5#(C)

DQ48
DQ49
DQ50

DQ51
DQ52

DQ53
DQ54

DQ55

219

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS7(T)

DQS7#(C)

VREF traces should be at least 20 mils
wide with 20 mils spacing to other

1

signals

CD15

0.022U_0402_25V7K

2

2

RD11

24.9_0402_1%

1

DDR_M0_D0

8

DDR_M0_D4

7
20 DDR_M0_D3
21 DDR_M0_D7

DDR_M0_D1

4

DDR_M0_D5

3
16 DDR_M0_D2
17 DDR_M0_D6

13 DDR_M0_DQS0

11 DDR_M0_DQS#0

28 DDR_M0_D8

29 DDR_M0_D12
41 DDR_M0_D14

42 DDR_M0_D10

25 DDR_M0_D13
38 DDR_M0_D11

37 DDR_M0_D15

32 DDR_M0_DQS#1

50 DDR_M0_D21
49 DDR_M0_D17
62 DDR_M0_D23
63 DDR_M0_D18
46 DDR_M0_D16
45 DDR_M0_D20
58 DDR_M0_D19
59 DDR_M0_D22
55 DDR_M0_DQS2

53 DDR_M0_DQS#2

70 DDR_M0_D25
71 DDR_M0_D28
83 DDR_M0_D30
84 DDR_M0_D31
66 DDR_M0_D24
67 DDR_M0_D29
79 DDR_M0_D27
80 DDR_M0_D26
76 DDR_M0_DQS3

74 DDR_M0_DQS#3

174 DDR_M0_D32
173 DDR_M0_D37
187 DDR_M0_D34
186 DDR_M0_D39
170 DDR_M0_D36
169 DDR_M0_D33
183 DDR_M0_D35
182 DDR_M0_D38

179 DDR_M0_DQS4

177 DDR_M0_DQS#4

195 DDR_M0_D44

194 DDR_M0_D45
207 DDR_M0_D42
208 DDR_M0_D43
191 DDR_M0_D41
190 DDR_M0_D40
203 DDR_M0_D46
204 DDR_M0_D47

200 DDR_M0_DQS5

DDR_M0_DQS#5

198

216 DDR_M0_D53

215 DDR_M0_D48
228 DDR_M0_D54
229 DDR_M0_D50
211 DDR_M0_D52
212 DDR_M0_D49
224 DDR_M0_D55
225 DDR_M0_D51

221 DDR_M0_DQS6

DDR_M0_DQS#6

237 DDR_M0_D60
236 DDR_M0_D57
249 DDR_M0_D59
250 DDR_M0_D62
232 DDR_M0_D56
233 DDR_M0_D61
245 DDR_M0_D58
246 DDR_M0_D63

242 DDR_M0_DQS7

240 DDR_M0_DQS#7

DDR_M0_DQS0 <6>

DDR_M0_DQS#0 <6>

DQ11

24

DQ15

34

Title

Document Number

DDR_M0_DQS1 <6>

DDR_M0_DQS#1 <6>

DDR_M0_DQS2 <6>

DDR_M0_DQS#2 <6>

DDR_M0_DQS3 <6>

DDR_M0_DQS#3 <6>

DDR_M0_DQS4 <6>

DDR_M0_DQS#4 <6>

DDR_M0_DQS5 <6>

DDR_M0_DQS#5 <6>

DDR_M0_DQS6 <6>

DDR_M0_DQS#6 <6>

DDR_M0_DQS7 <6>

DDR_M0_DQS#7 <6>

Compal Electronics,Inc.

P18-DDRIV_CHA: DIMM0

CSL50 LA-E791P

1

Rev

Sheet 17 of 59Date: Friday, January 05, 2018

1

v0.3

5

4

3

2

1

STD (5.2 mm)

CHANNEL-B

TOP: JDIMM2 CONN Non-ECC

D D

+3VS +3VS +3VS

1

@

2

1

2

RD19

0_0402_5%

RD22
0_0402_5%

12

1

RD20
0_0402_5%

@

0_0402_5%

2

RD23

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL B :

WRITE ADDRESS: 0XA4

READ ADDRESS: 0XA3
SA0 = 0; SA1 = 1; SA2 = 0.

DDR4 POR OPERATING SPEED: 1867 MT/S
STRETCH GOAL IS 2133 MT/S

C C

Layout Note:
Place near JDIMM2.257,259

10uF*2
1uF*2

10U_0603_6.3V6

M

10U_0603_6.3V6

M

1

2

Layout Note:

PLACE THE CAP WITHIN 200 MILS
FROM THE JDIMM2

B B

+0.6V_DDRB_VREFCA

2 2

1

A A

1U_0402_6.3V6

K

1U_0402_6.3V6

1

CD62

2

CD69 CD70

0.1U_0201_10V6K 12.2U_0402_6.3V6M

Layout Note:
Place near JDIMM2

M

1

2

K

1

1

CD63

CD64

CD65

2

2

2.2uF*1

0.1uF*1

10U_0603_6.3V6

10U_0603_6.3V6

M

10U_0603_6.3V6

M

1

CD73

2

M

1

1

CD75

CD74

2

2

5

10uF*6
1uF*8
330uF*1

10U_0603_6.3V6

M

1

CD76

2

M

10U_0603_6.3V6

M

10U_0603_6.3V6

1

1

CD78

CD77

2

2

@

DIMM

1

RD21

@

0_0402_5%

2

SA2_CHB_DIM2SA1_CHB_DIM2SA0_CHB_DIM2

1

RD24
0_0402_5%

2

Layout Note:
Place near JDIMM2.258

+0.6V_0.6VS+2.5V

M

1

2

10U_0603_6.3V6

M

1

CD79

2

RD33

@

10U_0603_6.3V6

CD66

10U_0603_6.3V6

CD80

10U_0603_6.3V6

M

1

CD67

2

1 2

+1.2V_VDDQ+1.2V_VDDQ

1

2

10uF*2
1uF*1

1U_0402_6.3V6

K

1

2

+3V_PRIM_DB+3V_PRIM

0_0402_5%

1U_0402_6.3V6

K

CD83

CD68

1U_0402_6.3V6

K

1

CD84

2

Interleaved Memory

<6> DDR_M1_D[0..15]
<6> DDR_M1_D[16..31]
<6> DDR_M1_D[32..47]
<6> DDR_M1_D[48..63]

111
112
117
118
123
124
129
130
135
136

255
164

262

0.1U_0201_10V6K

1U_0402_6.3V6

K

1

CD85

2

+3V_PRIM_DB

1

CD60

2

PLACE NEAR TO PIN

1U_0402_6.3V6

K

1

2

K

1U_0402_6.3V6

K

1

1

CD87

CD86

2

2

4

+1.2V_VDDQ

2.2U_0402_6.3V6M

+0.6V_DDRB_VREFCA

2

1

1U_0402_6.3V6

K

1

CD88

2

CD61

Part Number:LTCX0069FA0
Part Value:S SOCKET FOX AS0A827-H2SB-7H 260P DDR4

1U_0402_6.3V6

K

1U_0402_6.3V6

1

CD89

CD90

2

JDIMM2B

STD

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10

VDDSPD

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

GND GND

FOX_AS0A827-H 2SB-7H

CONN@

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19

VPP1
VPP2

<6> DDR_M1_CLK0
<6>DDR_M1_CLK#0

<6> DDR_M1_CLK1

<6> DDR_M1_CLK#1

<6> DDR_M1_CKE0
<6> DDR_M1_CKE1

<6> DDR_M1_CS#0
<6> DDR_M1_CS#1

141
142
147
148
153
154
159
160
163

258

VTT

257

259

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

261

+1.2V_VDDQ

+0.6V_0.6VS

+2.5V

+1.2V_VDDQ

9/8 Modify

RD25 2
240<_064,1072>_1%

+1.2V_VDDQ

DDR_DRAMRST#_R

<6> DDR_M1_ODT0
<6> DDR_M1_ODT1

<6> DDR_M1_BG0
<6> DDR_M1_BG1
<6> DDR_M1_BA0
<6> DDR_M1_BA1

<6> DDR_M1_MA0
<6> DDR_M1_MA1
<6> DDR_M1_MA2
<6> DDR_M1_MA3
<6> DDR_M1_MA4
<6> DDR_M1_MA5
<6> DDR_M1_MA6
<6> DDR_M1_MA7
<6> DDR_M1_MA8
<6> DDR_M1_MA9
<6> DDR_M1_MA10
<6> DDR_M1_MA11
<6> DDR_M1_MA12
<6> DDR_M1_MA13

<6> DDR_M1_MA14_W E#

<6> DDR_M1_MA15_CAS#

<6> DDR_M1_MA16_RAS#
<6> DDR_M1_ACT#

<6> DDR_M1_PAR

<6> DDR_M1_ALERT #

1

DDR_DRAMRST#_R

<7,17> PCH_SMBDATA

<7,17> PCH_SMBCLK

For ECC DIMM

@ESD@

CD92

0.1U_0402_25V6

2 1

PLACE NEAR TO SODIMM

+1.2V_VDDQ

2

CD71

@

0.1U_0402_10V6K

1

2

CD81

0.1U_0402_10V6K

1

SecurityClassification

IssuedDate

THIS SH E ET O F E NG IN EE R IN G D RA WIN G IS TH E PR OP RIE TA RY PR O PE RTY O F C OM PA L E LECT RONI CS , INC . A ND C ONTA INS CONFIDENTSI
AN D TR AD E SE CR E T INF ORM A TI ON . TH IS S HE E T MA Y NO T BE TR AN SF E RE D F RO M TH E C US TO DY OF TH E C OM PE TE N T DIV ISION OF R &D
DEP ARTM E NT E XC E PT AS AUTH ORIZ E D BY C OM P AL ELE CTR ONICS , I NC. NE ITHE R THIS S H EE T NO R TH E IN F O RM AT IO N IT C ONTA INS M
AY BE US E D BY OR DIS CLO SE D TO AN Y THIRD P A RTY W ITH OU T PR IO R WR ITTE N C O NS EN T OF CO MP AL E LECT RONIC S , INC.

3

RD26
1K_0402_1%

1 2

RD28
1K_0402_1%

1 2

2017/04/10 2019/12/15

DIMM Side

+0.6V_DDRB_VREFC A

1 RD27 2

2

CD72

0.1U_0402_10V 6K

1

Compal Secret Data

DecipheredDate

2_0402_1%

2

DDR_M1_CLK0
DDR_M1_CLK#0
DDR_M1_CLK1
DDR_M1_CLK#1

DDR_M1_CKE0
DDR_M1_CKE1

DDR_M1_CS#0
DDR_M1_CS#1

DDR_M1_ODT0
DDR_M1_ODT1

DDR_M1_BG0
DDR_M1_BG1
DDR_M1_BA0
DDR_M1_BA1

DDR_M1_MA0
DDR_M1_MA1
DDR_M1_MA2
DDR_M1_MA3
DDR_M1_MA4
DDR_M1_MA5
DDR_M1_MA6
DDR_M1_MA7
DDR_M1_MA8
DDR_M1_MA9
DDR_M1_MA10
DDR_M1_MA11
DDR_M1_MA12
DDR_M1_MA13

DDR_M1_MA14_WE# 151
DDR_M1_MA15_CAS# 156

DDR_M1_MA16_RAS#
DDR_M1_ACT#
DDR_M1_PAR 143

DDR_M1_ALERT#
DIMM2_CHB_EVENT# 134
DDR_DRAMRST#_R

PCH_SMBDATA

PCH_SMBCLK

SA2_CHB_DIM2
SA1_CHB_DIM2
SA0_CHB_DIM2

1

CD82

0.022U_0402_25V7K

2

2

RD29

24.9_0402_1%

1

JDIMM2A

137
139
138
140

109
110

149
157
162
165

155
161

115
113
150
145

144
133
132
131
128
126
127
122
125
121
146
120
119

152

114

116
108

254
253

166
260
256

101
105

100
104

178
199
220
241

STD

CK0(T)
CK0#(C) DQ1
CK1(T) DQ2
CK1#(C)

CKE0
CKE1

S0#
S1#
S2#/C0
S3#/C1

ODT0
ODT1

BG0
BG1
BA0
BA1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12

158

A13
A14_WE#
A15_CAS#

A16_RAS#

ACT#
PARITY

ALERT#

EVENT#

RESET#

SDA

SCL

SA2
SA1

SA0

92

CB0_NC

91

CB1_NC
CB2_NC
CB3_NC

88

CB4_NC

87

CB5_NC
CB6_NC

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#
DM4#/DBI4#
DM5#/DBI5#
DM6#/DBI6#
DM7#/DBI7#

96

DM8#/DBI8# DQS6#(C)

FOX_AS0A827-H2SB-7H

CONN@

DQ0

DQ3
DQ4
DQ5

DQ6
DQ7

DQS0(T)

DQS0#(C)

DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQS1(T)

DQS1#(C)

DQ16
DQ17
DQ18

DQ19
DQ20

DQ21
DQ22

DQ23

DQS2(T)

DQS2#(C)

DQ24
DQ25
DQ26

DQ27
DQ28

DQ29
DQ30

DQ31

DQS3(T)

DQS3#(C)

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS4(T)

DQS4#(C)

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQS5(T)

DQS5#(C)

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQS6(T)

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS7(T)

DQS7#(C)

DDR_M1_D15

8

DDR_M1_D10

7

DDR_M1_D11

20
21 DDR_M1_D12

DDR_M1_D14

4

DDR_M1_D9

3
16 DDR_M1_D8
17 DDR_M1_D13
13 DDR_M1_DQS1

11 DDR_M1_DQS#1

28 DDR_M1_D0
29 DDR_M1_D5
41 DDR_M1_D7
42 DDR_M1_D6
24 DDR_M1_D4
25 DDR_M1_D1
38 DDR_M1_D3
37 DDR_M1_D2
34 DDR_M1_DQS0

32 DDR_M1_DQS#0

50 DDR_M1_D20

49 DDR_M1_D17
62 DDR_M1_D19
63 DDR_M1_D22
46 DDR_M1_D21
45 DDR_M1_D16
58 DDR_M1_D18
59 DDR_M1_D23

55 DDR_M1_DQS2

53 DDR_M1_DQS#2

70 DDR_M1_D25

71 DDR_M1_D24
83 DDR_M1_D31
84 DDR_M1_D27
66 DDR_M1_D28
67 DDR_M1_D29
79 DDR_M1_D30

80 DDR_M1_D26
76 DDR_M1_DQS3
74 DDR_M1_DQS#3

174 DDR_M1_D37

173 DDR_M1_D33

187 DDR_M1_D35
186 DDR_M1_D38
170 DDR_M1_D32
169 DDR_M1_D36
183 DDR_M1_D34
182 DDR_M1_D39
179 DDR_M1_DQS4
177 DDR_M1_DQS#4

195 DDR_M1_D44
194 DDR_M1_D45
207 DDR_M1_D42
208 DDR_M1_D47
191 DDR_M1_D40
190 DDR_M1_D41
203 DDR_M1_D43
204 DDR_M1_D46
200 DDR_M1_DQS5
198 DDR_M1_DQS#5

216 DDR_M1_D48
215 DDR_M1_D53
228 DDR_M1_D54
229 DDR_M1_D51
211 DDR_M1_D52
212 DDR_M1_D49
224 DDR_M1_D55
225 DDR_M1_D50
221 DDR_M1_DQS6
219 DDR_M1_DQS#6

237 DDR_M1_D60
236 DDR_M1_D57
249 DDR_M1_D58
250 DDR_M1_D62
232 DDR_M1_D56
233 DDR_M1_D61
245 DDR_M1_D59
246 DDR_M1_D63
242 DDR_M1_DQS7

240 DDR_M1_DQS#7

CPU Side

+0.6V_B_VREFDQ

VREF traces should be at least 20 mils
wide with 20 mils spacing to other
signals

Tiiitlle

iiiAzeLDocument Number

Compal Electronics,Inc.

P19-DDRIV_CHB: DIMM0

CSL50 LA-E791P

1

DDR_M1_DQS1 <6>

DDR_M1_DQS#1 <6>

DDR_M1_DQS0 <6>

DDR_M1_DQS#0 <6>

DDR_M1_DQS2 <6>

DDR_M1_DQS#2 <6>

DDR_M1_DQS3 <6>

DDR_M1_DQS#3 <6>

DDR_M1_DQS4 <6>

DDR_M1_DQS#4 <6>

DDR_M1_DQS5 <6>

DDR_M1_DQS#5 <6>

DDR_M1_DQS6 <6>

DDR_M1_DQS#6 <6>

DDR_M1_DQS7 <6>

DDR_M1_DQS#7 <6>

Sheet 18 of 59Date: Friday, January 05, 2018

Rev

v0.3

5

eDPPower

0.1U_0201_10V6K

4.7U_0402_6.3V6M

1

1

CG3

CG2

*UG1 +LCDVDD Current Limit :0.8A

D D

Rshort@

< 5> E NVDD_CP U

+3V S

+3V S

+3V S

R6 1 2 EN VDD_ CPU_R 1

0_0402_ 5%

R5198 1 @ 2 UG2_F LAG1 2

ENVDD_ CPU R5200 1 @ 2 UG2_ EN2 3

100K_0402_5%

0_0402_ 5%

R52011

100K_0402_5%

R5199 1 @ 2 UG2_FLAG2

100K_0402_5%

2

FLAG1

UG2

EN1

EN2

4

FLAG2 OUT2

G510F51 U_MSOP 8

SA0000 BEY00

@

2

2

9

GND

8

IN1

7

OUT1

6

IN2

5

Camera

R170 EMI@ 1

< 11>U SB20_N 5

< 11>U SB20_P5

C C

< 32> D_MIC_CLK

<32> D_MIC_DATA

SM070 005U00 M URATA DLM0 NSN900 HY2D

L12

D_MIC_CLK

D_MIC_DATA 1 Rshort@2 D _MIC_L_D ATA

2

4

0_0201_5%

4

3

1

@EMI@

1 2

EMI@

1 2

R171 0_02 01_5%

R175 0_04 02_5%

3 USB20_ N5_R

2

USB20_P5_R

4

W=60mils

+LCDV DD

1

2

USB20 _P5_R2

USB20 _N5_R 3

+3V S

SM010014520 3000ma
220ohm@100mhz
DCR0.04

@EMI@ C117

680P_0402_5 0V7K

+3V S_CAM ERA

0.1U_0402_16V7K
C5232

1st:SA000080300, S IC G5250Q1T73U SOT-23 3P POWER SWITCH_0.4A
2nd:SA00004ZA00, S IC AP2330W-7 SC59 3P PWRSW_0.4A

+3V S

1U_0402_6.3V4Z

1

1

CG76

2

2

@ESD@

SCA0 0000U10

D7

1

PESD5 V0U2BT_S OT23 -3

1 @ 2

R5196

SD0130 00080

*FG3 Camera Current Limit : 0.4A

+LCDV DD

0.1U_0402_16V7K

C5231

0_0603_ 5%

INVPW R_B+

1

2

1

@

2

1

C118
68P_0402 _50V8J

2

0.1U_0201_10V6K

1U_0402_6.3V4Z

1

CG75

CG1

2

+3V S_CAM ERA

1 1

@

C5221 C5222

.1U_04 02_16V 7K 24.7U_0402_6.3V6M

2

W=60mils

L1 1 @ 2 0_0805 _5%

SD0020 00080

L2 1 @ 2 0_0805_5%

SD0 0200008 0

1 2

FU1 0.75A_24V_MF-MSMF075/24

SP04000 9I00

+3V S

1U_0402_6.3V4Z

1

CG4

2

SE00000 SO00

3

+19VB

C593 2

C594 2

<EC>

<CPU>

<CPU>

<CPU>

<6,7,9,10,11,13,17,18,28,29,30,31,3 2,33,36,39,40,52> + 3V S

<7,13,29,30,33,34,35,40,48,49,50,51> + 3VAL W

< 33>EC_ BKOFF#

< 5> BKL _PW M_CPU

< 5>E DP_HPD

< 5> E DP_ AUXP
< 5> E DP_ AUXN

< 5> EDP _TXP0

< 5> EDP_TX N0

< 5> EDP _TXP1

< 5> EDP_TX N1

1 220P_0402_50V7KINVTPW M
1

220P_0402_50V7K

DISPOFF#

1 Rshort@2

R259

2

<46,47,48,49,50,53> + 19VB

1

R166233_0402 _5%

R5176
10K_0402 _5%

2 1

0_0402_ 5%

@ R163

2 1

RT34 1 Rshort@2 0_0201_5%EDP_HP D_R

RT11
100K_0402_5 %

2 1

2 .1U_ 0402_16V 7K E DP_ AUXP _C

CT102 1

CT101 1

2

.1U_04 02_16V7K

CT98 1 2 .1U_04 02_16V7K EDP _TXP0_C

2

.1U_04 02_16V7K

CT97 1

CT103 1 2 .1U_0 402_16V7K EDP _TXP 1_C

2

CT100 1

.1U_04 02_16V7K

100K_0402_5%

DISPOFF#

INVTPW M

+3V S
+19VB

+3VAL W

EDP _AUX N_C

EDP_TX N0_C

EDP_TX N1_C

1

R5175 EMI@

1

Touch Screen

@ESD@

CTS3

4.7U_0402_6.3V6M

CTS6

4.7U_0402_6.3V6M

D6

1

PESD5V0U2BT_ SOT23- 3

SCA 00000U10

Touch Screen Power Selection:

+3VS _TOUCH

1

@

2

+5VS _TOUCH

1

TS@

2

5

USB20 _P7_R 2

USB20 _N7_R 3

B B

A A

< 11>U SB20_P7

< 11>U SB20_N 7

RTS 7 1 @ 2 0_ 0402_5%

@

3

2

RTS 8 1 @ 2 0_0 402_5%

3

2

FG4

OUT

GND

SA0000 4ZA00

G5250Q1T73U SOT-23 3P POWERSWITCH

TS@

OUT

GND

SA0000 4ZA00

G5250Q1T73U SOT-23 3P POWERSWITCH

1

IN

FG2

1

IN

SM070005U00

MURATA DL M0NSN90 0HY2D

+3VS_TOU CH only f or FHD wi th TS

0.1U_0402_16V4Z

+5VS_TOU CH only f or HD with TS

0.1U_0 402_16V4Z

2

0_0201_ 5%

L13

1 1 @EMI@ 22

4 3

4

EMI@

1 2

R173 0_02 01_5%

+3VS

1

@CTS7

2

+5VS

3

20mil

20mil

TS@

1

CTS1

2

4

USB20_P7_R

USB20_N7_ R

<10> TS_GPIO_C PU

< 33> TS _GPIO_EC

1 @ 2

R260 0_0402_5%

1 2

R5187 0_040 2_5%

3

TS_GPIO

EDP _TXP1 _C
EDP _TXN1 _C

EDP _TXP0 _C
EDP _TXN0 _C

EDP _AUX P_C
EDP _AUX N_C

+LCDV DD

EDP_HP D_R

Camera

Compal Secret Data

USB20 _P7_R

USB20_N7_ R

DISPOFF#
INVTPW M
TS_GPIO

USB20_N5_ R
USB20_P5_R

D_MIC_CLK
D_MIC_L_ DATA

Deciphered Date

2

Touch screen

INVPW R_B+

+5VS_ TOUCH
+3VS_ TOUCH

+3V S_CAM ERA

Security Classification

Issued Date

THIS SHE ET OF ENGINEE RING DRAW ING IS THE PROPRIE TARY PROP ERTY OF COMP AL EL ECTRONICS , INC. AND CONTAINS CONFIDENTSIiiA
AND TRA DE SEC RET INF ORMATI ON. THIS S HEET MAY NOT BE TRA NSFERE D FR OM THE CU STODY OF THE CO MPETENT DIVISION OF R& D
DEPAR TMENT EXC EPT AS AU THORIZED B Y COMPA L ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CONTAINS MAY
BE USED B Y OR DISC LOSED TO ANY THIRD P ARTY W ITHOUT PRIOR W RITTEN CONS ENT OF COMPA L EL ECTRONICS , INC.

2017/08/24 2018/08/24

eDP

CONN@

JEDP

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16
17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25 GND

25

36

26 GND

35

26

27 GND

34

27

28 GND

33

28

29 GND

32

29

30 GND

31

30

ACES_ 50203- 03001-002

SP01002 3710

Title

eDP CONN/Camera/TS

zeeLDocument Number

CSL50 LA-E791P

Compal Electronics, Inc.

Sheet 27 of 59Date: Friday, January 05, 2018

1

Rev

v0.3

5

<5> HOST_DP1_P0
<5> HOST_DP1_N0

<5> HOST_DP1_P1

<CPU>

<5> HOST_DP1_N1

<5> HOST_DP1_P2
<5> HOST_DP1_N2

D D

C C

B B

A A

<5> HOST_DP1_P3
<5> HOST_DP1_N3

HDMI_CLKP

HDMI_CLKN

HDMI_TX_P2

HDMI_TX_N0

HOST_DP1_P0 0.1U_0402_16V7K 1 2 CG8
HOST_DP1_N0 0.1U_0402_16V7K 1 2 CG9

HOST_DP1_P1 0.1U_0402_16V7K 1
HOST_DP1_N1 0.1U_0402_16V7K 1

HOST_DP1_P2 0.1U_0402_16V7K 1
HOST_DP1_N2 0.1U_0402_16V7K 1

HOST_DP1_P3 0.1U_0402_16V7K 1
HOST_DP1_N3 0.1U_0402_16V7K 1

*DDA30_LA-F292PR02: RS_8.2ohm_RP_360ohm

RG591 EMI@ 2 15 +-1%0402

RG601 EMI@ 2 15 +-1%0402

RG631 EMI@ 2 15 +-1%0402

RG611 EMI@ 2 15 +-1%0402

RG651 EMI@ 2 15 +-1%0402

RG101 EMI@ 2 15 +-1%0402

RG121 EMI@ 2 15 +-1%0402

RG131 EMI@ 2 15 +-1%0402

FG1

+5VS

1

IN

AP2330W-7_SC59-3

SA00004ZA00

OUT

GND

2 CG10
2 CG11

2 CG12
2 CG13

2 CG14
2 CG15

RP1 RP2
470_0804_8P4R_5% 470_0804_8P4R_5%

W=40mils

3

2

0.1U_0402_16V7K 2 4.7U_0402_6.3V6M

4

567

8

432

1

HDMI_R_CLKP

CG71 EMI@

360+-5%0402

SD028360080

1 2

HDMI_R_CLKN

HDMI_R_TX_N2HDMI_TX_N2

CG72 EMI@
360+-5%0402

SD028360080

1 2

HDMI_R_TX_P2

HDMI_R_TX_P1HDMI_TX_P1

CG73 EMI@
360+-5%0402

SD028360080

1 2

HDMI_R_TX_N1HDMI_TX_N1

HDMI_R_TX_P0HDMI_TX_P0

CG74 EMI@
360+-5%0402

SD028360080

1 2

HDMI_R_TX_N0

1

CG46 CG47

567

8

432

1

+HDMI_CRT_5V

1

2

HDMI_TX_P2
HDMI_TX_N2

HDMI_TX_P1
HDMI_TX_N1

HDMI_TX_P0

HDMI_TX_N0
HDMI_CLKP

HDMI_CLKN

QG1B SB00001FF00

L2N7002SDW1T1G2NSC88-6

3 4

+3VS

HDMI_R_TX_N0 1
HDMI_R_TX_P0 2
HDMI_R_CLKN 4
HDMI_R_CLKP 5

HDMI_R_TX_N1 1
HDMI_R_TX_P1 2
HDMI_R_TX_N2 4

HP_DETECT
HDMI_CTRL_DAT2

HDMI_CTRL_CLK4

3 2

5

@ESD@

D21

1

2

4

5

3

3

8

AZ1045-04F.R7G DFN2510P10EESD

SC300001Y00

@ESD@

D22

1

2

4

5

3

3

8

AZ1045-04F.R7G DFN2510P10EESD

SC300001Y00

@ESD@

DG1

1

1

2 9

4

5

5

3

3

8

AZ1045-04F.R7G DFN2510P10EESD

SC300001Y00

9HDMI_R_TX_N0

10

8HDMI_R_TX_P0

9

7 HDMI_R_CLKN

7

6 HDMI_R_CLKP

6

9 HDMI_R_TX_N1

10

8 HDMI_R_TX_P1

9

7 HDMI_R_TX_N2

7

6 HDMI_R_TX_P2HDMI_R_TX_P2 5

6

9 HP_DETECT

10

8 HDMI_CTRL_DAT

7 HDMI_CTRL_CLK

7

6

6

<5> HOST_DP1_HPD

RG47

1M_0402_5%

<5> HOST_DP1_CTRL_CLK

<5> HOST_DP1_CTRL_DATA

+HDMI_CRT_5V

+3VS

@

@

10P_0402_50V8J

1

1

CM26

2

2

+3VS

12

2

1 6 HDMI_HPD

QG1A

L2N7002SDW1T1G2NSC88-6

SB00001FF00

10P_0402_50V8J

CM27

5V Level

RG105

8 HDMI_CTRL_CLK

1

7 HDMI_CTRL_DAT

2

6 HOST_DP1_CTRL_CLK

3

5 HOST_DP1_CTRL_DATA

4

2.2K_0804_8P4R_5%

1 2

10K_0402_5%

1

RG56

20K_0402_5%

2

HOST_DP1_CTRL_CLK

HOST_DP1_CTRL_DATA

HP_DETECT

+HDMI_CRT_5V

HDMI_CTRL_DAT
HDMI_CTRL_CLK

HDMI_R_CLKN
HDMI_R_CLKP

HDMI_R_TX_N0
HDMI_R_TX_P0

HDMI_R_TX_N1
HDMI_R_TX_P1

HDMI_R_TX_N2
HDMI_R_TX_P2

1

<6,7,9,10,11,13,17,18,27,29,30,31,32,33,36,39,40,52> +3VS

<27,32,33,34,36,37,40>+5VS

RG108

HP_DETECT

1

@

CM17

220P_0402_50V7K

2

+3VS

2

1

6 HDMI_CTRL_CLK

QG2A SB00001FF00
L2N7002SDW1T1G2NSC88-6

4

QG2B SB00001FF00
L2N7002SDW1T1G2NSC88-6

+3VS

5

HDMIConn.

JHDMICONN@

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Utility

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+ GND1

3

D2- GND2

2

D2_shield GND3

1

D2+ GND4

ACON_HMRBL-AK120H

DC231709273

23

22

21

20

+3VS

+5VS

3 HDMI_CTRL_DAT

SecurityClassification

IssuedDate

THIS SHEET OF ENGIN EERING DRAW ING IS THE PROPRIETARY PROP ERT Y OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENSSTiIzAeL
AND TRA DE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPET ENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY
BE USED BY OR DISCLOSED TO ANY T HIRD PARTY W ITHOUT PRIOR W RITTE N C ONSENT OF COMP AL ELECTRO NICS, INC.

5

4

2017/08/24 2018/08/24

3 2

Compal Secret Data

DecipheredDate

Title

DocumentNumber

Date: Friday,January 05, 2018 Sheet

Compal Electronics, Inc.

HDMI Conn/Level shift

CSL50 LA-E791P

1

28 of 59

Rev

v0.3

5

JL33

1

2

1 2

+3VALW

1

@

CL28

1500P_0402_50V7K

D D

CL20

@

2

CL9, CL20 close to UL1 Pin 11
CL5 & CL19 close toUL1: Pin 32

C C

B B

2

1

1

@

CL19

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

2 1

0.01U_0402_16V7K 20.1U_0402_16V7K

1

LAN_MDIP0

<33>LAN_PW R_EN

+LAN_VDD_3V3

1

CL5

CL9

2

0.1U_0402_16V7K

4

@ESD@

DM12

4

@EMI@

CL1 CL4

1

2

0.1U_0402_16V7K

JUMP_43X79

@

UL2

VOUT

5

VIN

GND

4

EN

/OC

G524B1T11U_SOT23-5

SA00006Y800

+LAN_VDD_3V3

1

1

CL10

CL16

2

2

4.7U_0603_6.3V6K

0.1U_0402_16V7K

CL10& CL16 close to UL1: Pin23

3 LAN_MDIN0

3

TSL1

4

TCT2 MCT2

5

TD2+ MX2+
TD2- MX2-

7

TCT3 MCT3

8

TD3+ MX3+
TD3- MX3-

10

TCT4 MCT4
TD4+ MX4+
TD4- MX4-

LAN-8100G1G

SP050008Y00

TCT1 MCT1
TD1+ MX1+
TD1- MX1-

+V_DAC 1
LAN_MDIP0 2
LAN_MDIN0 3

LAN_MDIP1
LAN_MDIN1 6

LAN_MDIP2
LAN_MDIN2 9

LAN_MDIP3 11
LAN_MDIN3 12

+LAN_VDD_3V3 Rising
time

JUMP@

LANGND

<100mS

1

2

3

<9> CLKREQ_PCIE#1

<9,30,31,33,35> PLT_RST#

<9> CLK_PCIE_P1
<9> CLK_PCIE_N1

<11> PCIE_CTX_C_DRX_P5
<11> PCIE_CTX_C_DRX_N5

<11> PCIE_CRX_DTX_P5
<11> PCIE_CRX_DTX_N5

25 XGND RL55 1 @ 20_080 5_5%
24
23

RJ45_MDIP0

22 RJ45_MDIN0
21

RJ45_MDIP1

20
19 RJ45_MDIN1

18

RJ45_MDIP2

17
16

RJ45_MDIN2

15

RJ45_MDIP3

14

RJ45_MDIN3

13

need>0.5mS and

+LAN_VDD_3V3

PCIE_CTX_C_DRX_P5

PCIE_CTX_C_DRX_N5
PCIE_CRX_DTX_P5 CR11 1
PCIE_CRX_DTX_N5 CR13 1 2 0.1U_0402_10V7KPCIE_CRX_C_DTX_N5

MCT1 1

MCT2 2

MCT3 3

MCT4 4

@ESD@

LAN_MDIP2 4

4

4

CLKREQ_PCIE#1 2 Rshort@1

PLT_RST#RL6 0_0201_5%

CLK_PCIE_P1
CLK_PCIE_N1

RP5

8
7
6
5

75_0804_8P4R_1%

SD300002E80

2

3

DL1

3

2

PESD5V0U2BT 3P CCSOT23 ESD

ESD@
SCA00000T00

1

1

DM13

3 LAN_MDIN2

3

RTL8107ESH-CG/RTL8111HSH-CG Co-Lay

LAN_MDIP0
LAN_MDIN0

LAN_MDIP1
LAN_MDIN1
LAN_MDIP2

LAN_MDIN2
LAN_MDIP3

LAN_MDIN3 10

CLKREQ_PCIE#1_R

2 0.1U_0402_10V7K PCIE_CRX_C_DTX_P5 17

2

RL11

2.49K_0402_1%

1

2

CL2

SE167100J80

10P_1808_3KV

1

1

CL3
120P_0402_50V8J

EMI@

LANGND

2

+LAN_REGOUT

2.2UH +-20%1239AS-H-2R2M=P22A

UL1
RTL8111HSH-CG

SA000084T00

MDIP0

2

MDIN0

4

MDIP1

5

MDIN1

6

MDIP2

7

MDIN2

9

MDIP3

MDIN3

12

CLKREQB

19

PERSTB LANWAKEB

15

REFCLK_P

16

REFCLK_N

13

HSIP

14

HSIN

HSOP

18

HSON

RSET 31

RSET

(SA0000ALR00) RTL8107ESH-CG 10/100

(SA000084T00)RTL8111HSH-CGGiga

LL2

1 2

SH000014700

VDDREG(VDD33)

AVDD10
AVDD10
AVDD10
DVDD10

AVDD33
AVDD33

REGOUT

ISOLATEB

LED1/GPO

LED2(LED1)

CKXTAL1
CKXTAL2

3

CL29

8
3

0

2

2

3

2

23

24 +L AN_REGOUT

20

27

LED0

26

25

29

33

GND

1

@

2

4.7U_0402_6.3V6M

+LAN_VDD_1V0

31

11

21

EC_PME#

EC_LAN_ISOLATEB#_R
LAN_ACT#

LED1/GPO

LAN_LINK#

28

XTLOI

CL8, CL23closeLL2.

CL26closeUL1Pin3.
CL12closeUL1Pin 8.

CL13~ CL15close UL1 Pin22.
CL11, CL27 close UL1 Pin30.

1

1

CL8

CL23

2

2

0.1U_0402_16V7K

4.7U_0603_6.3V6K

L

+LAN_VDD_3V3

+LAN_VDD_3V3

CL11

2

2

0.1U_0402_16V7K

+LAN_VDD_3V3=40mil
+VDDREG=40mil

+LAN_REGOUT=60mil

+LAN_VDD_3V3

+LAN_VDD_3V3

1 @ 2

RL56 4.7K_0402_5%

1

1

CL12

2

+LAN_VDD_1V0

1U_0402_6.3V6K

1 1

CL13

0.1U_0402_16V7K

2 1

CL14 CL15

2

0.1U_0402_16V7K

RL15
10K_0402_5%

EC_PME#<33>

LAN_LINK# LAN_LINK#_R

LAN_ACT# LAN_ACT#_R LAN_LINK#_R

1

@

2

1

1K+-5%0402

1

510_0402_5%

CL26

CL25

10P_0402_50V8J

2

0.1U_0402_16V7K

2

RL30

2

RL31

1U_0402_6.3V6K

1

1

@

CL27

2

2

0.1U_0402_16V7K

EC_LAN_ISOLATEB#_R 2

1K_0402_5%

RM11
15K_0402_5%

1 2

1

2

1M_0402_5%

RL7

YL1

1

NC NC

2

2 4

1

SJ10000UP00

25MHZ10PFXRCGB25M000F2P34R0

31

3

1

+3VS

RM6

2

10P_0402_50V8J

CL24

1

+LAN_VDD_3V3

LAN_ACT#_R A2

XTLI
XTLO

RJ45_MDIN3 8
RJ45_MDIP3 7
RJ45_MDIN1 6
RJ45_MDIN25
RJ45_MDIP2 4
RJ45_MDIP1 3
RJ45_MDIN0 2
RJ45_MDIP0 1

JLAN

A1

White_LED+

White_LED-

DI_D4-

DI_D4+

RX_D2-

BI_D3­BI_D3+
RX_D2+

TX_D1-

TX_D1+

B1

Amber_LED+

B2

Amber_LED-

SINGA_2RJ3081-1A8211F

DC231710035

1

9

GND1

10

GND2

11

GND3

12

GND4

LANGND

powe rail need tocheck

+LAN_VDD_3V3 +LAN_VDD_3V3

A A

LAN_MDIN1 6

5

Vbus

6 1

YSUSB2.0-5_SOT-23-6-6

SC300001G00

2

GND

1 LAN_MDIP1

5

powe rail need tocheck

Vbus

6

YSUSB2.0-5_SOT-23-6-6

SC300001G00

25

GND

1 LAN_MDIP3LAN_MDIN3 6

1

Security C lassi fication

Issued Date

THI S S HEE T O F ENG INE E RI NG DR AWI NG IS THE PR OPR IE TAR Y PR OP ERTY OF C OMP AL EL ECTR ONI C S, I NC. AND CO NTAI NS CONFIDENTSSIAizL
AND TRAD E SE CRE T I NFO RMATI O N. THI S SHE ET MAY NO T BE TR ANSF ER ED F ROM THE CUSTO DY OF THE CO MPE TENT DIVIS ION OF R& D DE
PAR TME NT E XC EPT AS AUTHO R IZ ED BY CO MPAL E LE CTRO NI CS, INC . NE IT HER THI S SHE ET NOR THE INF OR MATI ON IT CO NTAI NS

4

3

MAY BE USE D BY OR D IS CLOSED TO ANY THI RD PAR TY WI THO UT PRI OR WR ITTE N C ONS ENT OF CO MPAL ELE CTR ONI CS , I NC.

2017/08/24

Compal SecretData

Deciphered Date

2

2018/08/24

Title

e DocumentNumber

Compal Electronics, Inc.

LAN 8111

CSL50 LA-E791P

1

Sheet 29 of

Rev

v0.3

59Date: Friday, January 05,2018

5

4

3

2

1

100P_0402_50V8J

1

CN2

22U_0603_6.3V6K

2

+3V S

+3VAL W

100P_0402_50V8J

0.1U_0402_25V6

2 1

2 1

0.1U_0402_16V7K
CN3

1

2

<6,7,9,10,11,13,17,18,27,28,29,31,3 2,33,36,39,40,52> + 3VS

<7,13,29,33,34,35,40,48,49,50,51> + 3V ALW

D D

+3VS_ WL AN

CONN@

JWLA N

1 2

1_GND

< 11>U SB20_P6
< 11>U SB20_N 6

+3VS_ WL AN

12

RN3

10K_0402 _5%

C C

< 9,33>EC_ PCIE_W AKE#

< 9> C LK_PCIE _P2

< 9> CLK_PCIE_N2

< 11> P CIE_CTX_C _DRX_P 6

< 11> PC IE_CTX_C _DRX_N6

< 11> P CIE_CRX_ DTX_P6

< 11> PC IE_CRX_D TX_N6

< 9> CLKRE Q_PCIE#2

@R F@ @R F@

10P_0402_50V8J

R51 85

2 1

10P_0402_50V8J

R51 86

2 1

3

3_USB _D+

5

5_USB _D-

7

7_GND

9

9_N/C

11

11_N/C

13

13_N/C

15

15_N/C

17

17_N/C

19

19_N/C

21

21_N/C

23

23_N/C

25 24

33_GND

27

35_PE Rp0

29

37_PE Rn0

31

39_GND

33

41_PETp0

35

43_PETn0

37

45_GND

39

47_REFCLKP0

41

49_REFCLKN0

43

51_GND

45

53_CLK REK0#

47

55_PE Wake 0# W _DISABLE 2#_54

49

57_GND W _DISA BLE 1#_5 6

51

59_N/C

53

61_N/C

55

63_GND

57

65_N/C

59

67_N/C

61

69_GND

63

71_N/C

65

73_N/C

67

75_GND 3.3V_74

LOTES_A PCI0019 -P 003H

SP07001 0DA0

3.3V_2

3.3V_4

LED1#_6

N/C_8
N/C_10
N/C_12
N/C_14

LED2#_16

GND_18

N/C_20
N/C_22

N/C_32
N/C_34
N/C_36

CLink Rese t_38

CLink DATA_ 40

CLink CLK_42

COEX3_44
COEX2_46

COEX 1_48

SUSCLK _50

PERST0 #_52

48

N/C_58
N/C_60

N/C_62

RESER VED_64

N/C_66
N/C_68
N/C_70

3.3V_72

GND

GND
NC_70
NC_71

4
6
8

10

12

14
16

18
20
22

26
28
30

32
34
36
38

40

42

44

46

50

52

54

56

58

60
62

64
66

68
69
70
71

RN14 1 Rshort@20_0201_5 %

@R F@

R5179

+3VS_ WL AN

100P_0402_50V8J

@R F@

2 1

+3VS_ WL AN

1 2

0.1U_0402_25V6

R5180

2 1

E 51TXD_P 80DATA < 33>
E 51RXD_ P80CLK <33>

RN7

4.7K_0402 _5%

SUSCLK < 9>
PLT_RST# <9,29,31,33,35>

BT_ON_E C < 33>

W L_OFF# < 10>

+3VS_ WL AN

10K_0402_5%

BT_ON_E C

@R F@

R5181

+3VS_ WL AN

1

RN15 @RF@

2

0.1U_0402_25V6

@R F@ @R F@ @RF@

R5182 R5183 R5184

2 1

2 1

+3VS_ WL AN

Active Low

WL_ PWREN_E C# <33>

+3VS_ WL AN

1

2

RW L1

200K_0402_5 %

2 2 1

QWL1

1

DGS

PJ23011P SOT23-3

SB00000 T900

1 @ 2

RWL2 0 _0603_5%

CW L1

1 2

0.1U_0402_16V4Z

3

+3VAL W

NGFF and WLAN

Unpop QB8 and RL25 for not supportOBFF

B B

2

G

@

< 9> W AKE#

1 3 EC_ PCIE_W AKE#

D

S

SB00000 EN00

QB 8

2N7002H _SOT23-3

RL25 @

100K_0402_5 %

+3VS_ WL AN+3V S

2

1

CW L2

0.1U_0402_16V4Z

A A

Security Classification

Issued Date

THIS SHE ET OF ENGINEE RING DRAW ING IIIS THE PROPRIETA RY PROPE RTY OF COMPA L ELECTRONIIICS,,, IIINC. AND CON TAINS CONFIDENTSI
AND TRA DE SEC RET INFORMATION... THIS SHE ET MA Y NOT BE TRANS FERED FROM THE CUS TODY OF THE COM PETENT DIVISIIION OF R& D
DEPAR TMENT EXC EPT AS AU THORIZED B Y COMPA L ELE CTRONICS, IIINC... NEITHER THIIIS SHE ET NOR THE IIINFORMATION IIIT CONTAIIINS MAY

5

4

3

BE USED B Y OR DISC LOSED TO ANY THIIIRD PA RTY W ITHOUT PRIOR W RIIITTEN CONSEN T OF C OMPAL ELECTRONICS, INC.

2017/08/24 2018/08/24

Compal Secret Data

Deciphered Date

2

Tiitttlle

iiiAzeeLDocumenttt Number

Compal Electronics, Inc.

WLAN-BT

CSL50 LA-E791P

1

Rev

Sheet 30 of 59Date: Friday, January 05,,, 2018

v0.3

5

+3VS

CSS5

1

18P_0201_50VNPO

RF@

D D

RF@

2

JPHW9

1

1 2

JUMP_43X79 CS27 CSS7 CS8 CS9 1CSS6

JUMP@

10P_0201_50V

2

<SSD>

C C

SSD1_IF PU on CPU side RPC13.3_10K

100K_0402_5%

<11> SSD1_IF

B B

+3VS_SSD

2

1 @1

47U_0603_6.3V6M

2

2

<11> PCIE_CTX_C_DRX_N11

<11> PCIE_CTX_C_DRX_P11

<11> PCIE_CRX_DTX_P12

<11> PCIE_CRX_DTX_N12

<11> PCIE_CTX_C_DRX_N12
<11> PCIE_CTX_C_DRX_P12

+3VS

2

@ RS21

D

1 13

S

1

0.1U_0201_1 0V6K

10U_0603_10V6M

2 1

<11> PCIE_CRX_DTX_N11

<11> PCIE_CRX_DTX_P11

<9> CLK_PCIE_N4
<9> CLK_PCIE_P4

2

G

QS1 SB000009Q80
2N7002KW_SOT323-3

1U_0402_6.3V6K

2

@EMI@CS16

VARIST_CK0402101V050402

SSD_PDET

+3VS

RS22 10K_0402_5%

pre PV: change to 10K for redriver detect pin voltage level

1

CS10

10P_0201_50V

2

RF@

1 2

1 2

4

JSSD

1

GND 3P3VAUX

3

GND 3P3VAUX

5

PETn3 NC

7

PETp3 NC

9

GND DAS/DSS#

11

PERn3 3P3VAUX

13

PERp3 3P3VAUX

15

GND 3P3VAUX

17

PETn2 3P3VAUX

19

PETp2

21

GND

23

PERn2

25

PERp2

27

GND

Key TYP.M

29

PETn1

31

PETp1

33

GND

35

PERn1

37

PERp1 DEVSLP

39

GND

41

PETn0/SATA-B+

43

PETp0/SATA-B-

45

GND

47

PERn0/SATA-A-

49

PERp0/SATA-A+ PERST#

51

GND CLKREQ#

53

REFCLKN PEWake#

55

REFCLKP

57

GND

67

NC

69

PEDET 3P3VAUX

71

GND 3P3VAUX

73

GND 3P3VAUX

75

GND

3 2

NC
NC

NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC

NC
NC

SUSCLK(32kHz)

GND1

YPCI0016-P003A 67PA32

DC04000L9A0CONN@

GND2

2
4
6
8
10
12
14

16
18

20
22

24
26
28
30
32
34
36

38
40

42
44
46
48

50
52
54

56
58

68
70
72
74

76

77

+3VS_SSD

TS123

TP@

PLT_RST#_SSD
CLKREQ_PCIE#4

RS46 1 2 10K_0402_5%

RT3

1 Rshort@ 2 0_0201_5%

+3VS<6,7,9,10,11,13,17,18,27,28,29,30,32,33,36,39,40,52>

DEVSLP2<11>

PLT_RST# <9,29,30,33,35>

CLKREQ_PCIE#4<9>

1

+3VS

A A

SecurityClassification

IssuedDate

THIS SHEET OF ENGIN EERING DRAW ING IS THE PROPRIETARY PROP ERT Y OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENSSTiIzAeL
AND TRA DE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPET ENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY
BE USED BY OR DISCLOSED TO ANY T HIRD PARTY W ITHOUT PRIOR W RITTE N C ONSENT OF COMP AL ELECTRO NICS, INC.

5

4

2017/08/24 2018/08/24

3 2

Compal Secret Data

DecipheredDate

Compal Electronics, Inc.

Title

M.2SSD

DocumentNumber

CSL50 LA-E791P

Date: Friday, January05,2018

Sheet of

1

Rev

v0.3

5931

5

4

3

2

1

UA1

<8>HDA_SYNC_R
<8>HDA_BIT_CLK_R

D D

100K_0402_5% 2.2K_0402_5%

RA24 1 2 INT_MIC RA40 1 2 MIC2-VREFO 23

CA30 1 2 10U 6.3V M X5R 0603
CA31 1 2 2.2U 6.3V M X5R 0402

CA15 1 21U_0402_6.3V6K
CA391 2 10U 6.3VM X 5R0603

+1.8VS

2 1

@EMI@

1

CA41
10P_0402_50V8J

2

D_MIC_DATA
D_MIC_CLK_R

+DVDD

<27> D_MIC_DATA

<27> D_MIC_CLK

GNDA
GNDA

BLM15PX221SN1DEMI@ LA6

CA34 RA5322_0402_5%

22P 50V J NPO 0402

EMI@ INT_MIC

GNDA

<33> MUTE_LED_IN

1

PLUG_IN# 1

1 2 1 2

EMI@

CA29

1 2

10U6.3V M X5R0603

CA16 2 11U_0 402_6.3V6K CBP30

RA41

2 100K_0402_1%
2 200K_0402_1%

RA42

BCLK

MIC2_CAP 15

PC_BEEP

LDO1_CAP
VREF

CPVEE
CPVDD

PDB

9

SYNC

5

BCLK

14

MIC2-R/SLEEVE

13

MIC2-L/RING2

MIC2_CAP

11

PCBEEP

MIC2-VREFO

24

LINE1-VREFO-LSDATA_IN

21

LDO1-CAP

22

VREF

27

CPVEE

29

CPVDD

CBN 28

CBN

CBP

2

GPIO0/DMIC_DATA12

3

GPIO1/DMIC_CLK LDO2_CAP

10

DCDET

12

JD1

40

PDB

ALC3247-CG_MQFN40_5X5

1

DVDD

8

DVDD_IO

20

AVDD1

33

AVDD2

34

PVDD1

39

PVDD2

16 VD33STB1 RA232

VD33STB

35 S PK_L+

SPK_OUT_L+

36 SPK_L -

SPK_OUT_L-

37SPK_R-

SPK_OUT_R-

38SPK_R+

SPK_OUT_R+

26 HPOUT_R RA38 1

HPOUT_R

25 HPOUT_L RA371

HPOUT_L

4

SDATA_OUT

7 HDA_SDIN0_R 1 RA26 2

18

LINE1_L

17

LINE1_R

32 CA27 1 2 10U 6.3V M X5R0603

6 CA281 2 10U 6.3V M X5R 0603

LDO3_CAP

19

AVSS1

31

AVSS2

41

THERMALPAD

GNDA
GNDA

+3VS

0_0402_5%

+DVDD
+DVDD_IO

+5VS_AVDD
+1.8VS_AVDD

+5VS_PVDD1
+5VS_PVDD2

22_0402_5%

2 30_0402_1%HP_OUTR
2 30_0402_1%HP_OUTL

GNDA

HDA_SDOUT_R<8>
HDA_SDIN0<8>

Headphone

+5VS

+5VS

1 2

RA39 1

RA8

0_0402_5%

0_0402_5%

+5VS_PVDD1

1

1

2

2

0.1U 16V K X7R 0402 CA20

10U 6.3V M X5R 0603 CA19

+5VS_PVDD2

2

1

1

2

0.1U 16V K X7R 0402 CA22

AZ5125-01H.R7G_SOD523-2

2

10U 6.3V M X5R 0603 CA21

+3VS +DV DD

RA1

1 2

0_0402_5%

+5VS +5VS_AVDD

1 2

0_0402_5%

DA6

@

SC400005Q00

2 1

2

4.7U_0402_6.3V6M CA36

RA4

CA7

Internal SPK

RA36 1 EMI@ 2 0_0603_5%SPK_R-_CONN

C C

<8>HDA_RST#_R

<33> EC_MUTE#

B B

HDA_RST#_R

EC_MUTE#

Place RA51/RA52/RA53 on moat of UA1 BOT side

RA51 1

Rshort@

RA52 1

Rshort@

RA541 2 0_0603_5%

Rshort@

1

RA6

RA7@

1 2

0_0402_5%

1 2

CA9

0.1U16VK X7R0402

EMI@

1 2

CA10

0.1U16VK X7R0402

EMI@

1 2

CA11 @EMI@

0.1U16V K X7R0402

1 2

CA12 @EMI@

0.1U16V K X7R0402

1 2

CA13

0.1U16VK X7R0402

EMI@

+3VS +DVDD

@

2 2

@ 3QA2

E

MMBT3904WH_SOT323-3

SB000008E10

1 2

DA2 SCS00000Z00

RB751V-40SOD-323

R5260

1 2

0_0201_5%

20_0603_5%

20_0603_5%

2

0_0402_5%

GNDA

1

RA10
10K_0402_0.5%

B

1

C

@

1

100K_0402_5%

2

1

2

RA9

PDB

0.1U 16V K X7R 0402 CA23

PC Beep

EC Beep<33> EC_BEEP#

SB Beep <8,10>HDA_SPKR

0.1U 16V K X7R0402

CA43

0.1U 16VK X7R0402

Close to Codec pin34

1 2 PC_BEEP_R CA44

1 2

RA16
47K_0402_5%

1 2

1

2

RA17
10K_0402_5%

1 2 PC_BEEP CA42

0.1U16V KX 7R0402

SPK_R-

RA34 1 EMI@ 2 0_0603_5%SPK_R+_CONN

SPK_R+

RA33 1 EMI@ 2 0_0603_5%SPK_L-_CONN

SPK_L-

RA35 1 EMI@ 2 0_0603_5%SPK_L+_CONN

SPK_L+

wide 40 MIL

1 RA13 2 0_0402_5%

INT_MIC

1 RA14 2 0_0402_5%

HP_OUTL

HP_OUTR

1RA15 2 0_0402_5%

EMI@

EMI@

EMI@

1

2

220P_0402_50V7K

@EMI@ C11

Reserve for ESD request.

INT_MIC_R

3

GNDA

2

DA4
L03ESDL5V0CC3-2_SOT23-3

SCA00002900
ESD@

1

HP_OUTR_RHP_OUTL_R

1/20:Swap DA3

INT_MIC_R
HP_OUTL_R

PLUG_IN#

HP_OUTR_R

1

1

1

2

2

@EMI@

2

@EMI@

@EMI@

100P_0603_50V7CA24

100P_0603_50V7CA25

100P_0603_50V7CA26

GNDA

1 1

2

1 1

2

220P_0402_50V7K

0.1U 16V K X7R 0402 CA37

10U6.3V MX5R 0603

1

2

@EMI@ C12

+3VS +DVDD_IO

1

2

2

CA5

CA6

4.7U_0402_6.3V6M

0.1U16V KX7R 0402

GNDA

1

1

2

2

220P_0402_50V7K

220P_0402_50V7K

@EMI@ C14

@EMI@ C13

2

3

DA5
L03ESDL5V0CC3-2_SOT23-3

SCA00002900
@ESD@

1

3 3:M/G_EARTH
1 1:L/R_TIPSPRING

5 5:TRANSFERTERMINAL

6 6:MAKETERMINAL
2 2:R/L_RINGA

4 4:G/M_RINGB
7 7:MS_SHELL

GNDA

RA2

1 2

0_0402_5%

11

2 2

4.7U_0402_6.3V6M CA32

+1.8VS +1.8VS_A VDD

RA5

1 2

0_0402_5%

CONN@

JSPK

1

1

2

2

3

3

4

4

5

G1

6

G2

ACES_50278-00401-001

JHP

SINGA_2SJ3095-067111F

DC23000DY00

Pin6 and Pin5
Normal OPEN

0.1U 16V K X7R 0402 CA33

1

CA8

2

4.7U_0402_6.3V6M

GNDA

A A

Security C lassi fication

Issued Date

THI S S HEE T O F ENG I NEE RI NG DR AWI NG IS THE PR OP RIE TAR Y P ROP ER TY OF COMP AL EL EC TRO NIC S, I NC. AND C ONTAI NS CONFIDENTSSIA
AND TRAD E SE CRE T I NFO RMATI O N. THI S SHE ET MAY NO T BE TR ANSF ER ED FR OM THE CUSTO DY OF THE CO MPE TENT DIVIS ION OF R& D
DEP ARTME NT E XCE PT AS AUTHO RI ZE D BY COMP AL EL EC TRO NIC S, I NC. NE ITHE R THI S S HEE T NO R THE I NF OR MATI ON IT CO NTAI NS

5

4

3

MAY BE USE D BY OR DIISCLO SED TO ANY THIR D P ARTY W ITHO UT PR I OR W RI TTE N CO NS ENT OF COMP AL E LE CTR ONI CS , I NC.

2017/08/24

Compal SecretData

Deciphered Date

2

2018/08/24

Title

iizLeDoc umentNumber

Custom

Compal Electronics, Inc.

AUDIO ALC3258-CG
CSL50 LA-E791P

1

v0.3

Sheet 32 of 59Date: Friday, January05,2018

Rev

5

<9,19,2 9,30 ,31, 35> PLT_RST #

<5> EC_SCI#

<7> PM_CLKRUN#

<9,12,4 0> PM_SLP_ S 3 #

<9> PM_SLP_ S5 #

<9> SUSACK#

<9> PM_SLP_ SUS#

<9> PCH _SUSW ARN#

+3VS

+3VALW _EC

+3VL

<7> EC_KBRST #

<7> LPC_FRAME#

<7> CLK_PCI_LPC

<34> KSI[0..7]

<34> KSO[0..1 7]

RK15 1
RK16 1

<32> MUTE_LED_IN

<36> FAN_SPEED 1

<30> E51TXD_P80D ATA

<30> E51RXD_P80 CLK

<9> PCH_PW ROK

<34> MUTE_LED_OUT

<9> PBTN_OUT#

<9,12,4 0,49> PM_SLP_ S 4 #

<6,7,9, 10,1 1,13 ,17, 18,19,22, 23,24,27,28, 29,3 0,31,32, 36,3 9,40 ,52,55>
+3VS

D D

+3VALW _EC

C C

<47> VCIN1_ACOK

For Sol ve tPCH04(Min 9ms) Seq uenc e Ti min g

+5VS

B B

2

2

RK20 100K_0402_5%

RK108 10K_0402_5%

A A

10K_0402_5%

NMI_DBG#

ESD@

1 PLT_RST#

2

CK4 0.1U_0402_25V6

@

2

RK7

2

@ 1

CK5

RK28

100K_0402_5%

RK26

100K_0402_5%

1 @ 2 PCH_PW ROK

1 2MUTE_LED_ IN

RK21

0.1U_04 02_16V7 K

22P 50V J NPO 0402

VCIN1_AC_IN 1 @ 2 VCIN1_AC_IN_R R4960

1 MUT E_LED_O UT

1 E51TXD_P80DATA

+3VALW _EC

1

2

1 2

DK2 SCS00000Z 00

RB751V-40 SO D-323

1 330K_040 2_5%

1 2 1 2

CK9

EMI@

R4958 0_0402_5%

R5094

<7,10,2 2> EC _SMB_CK 2
<7,10,2 2> EC _SMB_DA 2

5

<22,45> +3VALW _EC

<13,39, 46,4 7,48> +3VL

EC_RST #

CLK_PCI_LPC

RK109 22_0402_5%

EMI@

1 @ 2 VCIN1_ACOK_R

1

2 VCIN1_AC _IN_R

0_0402_5%

0_0402_5%

<46,47> EC_SMB_ CK 1
<46,47> EC_SMB_ DA 1

NMI_DBG#_CPU <5,10>

<9,30> EC_PCIE_W AKE#

+3VL

RK1

T2403 T P@

<7,35> SERIRQ

<7> LPC_ AD3
<7> LPC_ AD2
<7> LPC_ AD1
<7> LPC_ AD0

EC_SCI#

1 @ 2

RK10 1 @
RK6

2 0_0402_ 5%
2 0_0402_ 5%

<45> AC_LED#

4

1

2

0_0603_5%

2 0_0402_5%

PM_SLP_S3#
PM_SLP_S5#

SUSACK#
PM_SLP_ SU S#
PCH_SUSWAR N#

4

1

2

TOUCH_ON
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_PCI_LPC
PLT_RST#
EC_RST #

PM_CLKRUN#_R

0_0402_5%

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

EC_SMB_CK 2_R
EC_SMB_DA 2_R

MUTE_LED_IN
FAN_SPEED1
VCIN1_ACOK_R
E51TXD_P80D ATA
E51RXD_P80CLK
PCH_PW RO K

AC_LED#

PBTN_O UT#
PM_SLP_ S4#

0.1U_0201_10V 6

K

0.1U_0201_10V 6

K

CK1

1

2

KB9022QD_ LQFP128_ 14X 14

3 2

+3VALW _EC

CK2

UK1

1

GATEA20/GPI O00

2

KBRST#/GPIO0 1

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

PC &MISC

LPC_ADL0

12

CLK_PCI_EC

13

PCIRST# /GPIO 05

37

EC_RST #

20

EC_SCI#/GPIO 0E

38

CLKRUN#/GPIO 1D

55

KSI0/GPIO 30

56

KSI1/GPIO 31

57

KSI2/GPIO 32

58

KSI3/GPIO 33

59

KSI4/GPIO 34

60

KSI5/GPIO 35

61

KSI6/GPIO 36

62

KSI7/GPIO 37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/G PIO 2 A

50

KSO11/G PIO 2 B

51

KSO12/G PIO 2C

52

KSO13/G PIO 2D

53

KSO14/G PIO 2 E

54

KSO15/G PIO2F

81

KSO16/G PIO4 8

82

KSO17/G PIO49

77

EC_SMB_C LK 1/ GPIO 44

78

EC_SMB_DA T 1/GPIO 45

79

EC_SMB_C LK 2/ GPIO 46

80

EC_SMB_DA T 2/GPIO 47

6

PM_SLP_ S3#/GPIO 04

14

GPIO07

15

GPIO08

16

GPIO0A

17

GPIO0B

18 GPIO0C
19 AC_PRESEN T/GP IO 0D

25

PW M2/GPIO11

28

FAN_SPEED1 / GPIO 14

29

FANFB1/GPIO15

30

EC_TX/ GPIO1 6

31

EC_RX/G PIO 17

32

PCH_PW RO K/GPIO1 8

34

SUSP _LED #/G PIO1 9

36

NUM_LED #/GPIO1A

122

PBTN_O UT#/G PIO5D

123

PM_SLP_ S 4#/G PIO 5E V18R/VCC_IO2

SA00007 5S30

LK1 SM01000Q 500
S SUPPRE_ TAI-TECH HCB1005KF-221T15 0402

+3VALW _EC

1 2 +EC_VCCA

+3V_LID

9223396111

VCC

VCC

VCC

VCC0

Pin111:VCC0

VCC_LPC

PWMOutput

ADInput

DAOutput

PS2Interface

Int. K/B

Matrix

SPI DeviceInterface

SPI FlashROM

SMBus

VCIN1_ADP_ PR OCH OT/ GPXIOA 05

VCOUT 0_MAIN_ PW R_O N/GPXIO A 07

GPIOGPO

GND

GND

GND

GND

112435

94

1 RK3 2

67

125

VCC

AVCC

EC_VCCST_PG/GPIO 0F

BEEP#/G PIO10

EC_FAN_ PW M/GPIO12

AC_OFF /GPIO1 3

VCIN1_B ATT_TEMP/A D0/G PIO3 8

VCIN1_B ATT_DROP/A D1/G PIO3 9

ADP_I/AD2/GPIO3A

AD_BID/AD3/G PIO3 B

EN_DFAN 1/DA1/GPIO 3D

EC_MUTE#/PSC LK1 /G PIO 4A

USB_EN#/PSDAT 1/GPIO4B

PSCLK2/GPIO4C
PSDAT 2/GPIO 4D

TP_CLK/GPIO4E

TP_DAT A/GPIO 4F

ENKBL/G PXIO A00

W OL_EN/GPXIOA01

ME_EN/G PXIOA 02

VCIN0_PH1/GP XIOD00

MISO/GPIO 5B

MOSI/GPIO 5C
SPICLK/GPIO58
SPICS#/GPIO 5A

EC_CIR_R X/AD6/GPIO40

SYS_PW ROK/AD7/GPIO 41

BATT_CHG_LED#/GP IO52

CAPS_LED#/G PIO53

GPIO

PW R_LED#/GPIO 54

BATT_LOW _LED#/G PIO5 5

SYSON/G PIO 56
VR_ON/GPIO5 7

DPW ROK_EC/GPIO59

EC_RSMRST#/G PXIOA 03

VCOUT 1_PROCHO T#/G PXIOA 06

BKOFF#/GPXIOA08

PCH_PW R_EN/GPXIOA 10

PW R_VCCST_PG/ GPXIO A 11

VCIN1_AC_IN/GPXIOD01

ALW_PW E_EN EC_ON/G PXIOD 02

ON/OFF#/GPXIOD03

GPI

LID_SW #/GPXIOD04

SUSP#/G PXIOD 05

PECI/GP XIOD0 7

GND

AGND

69

20mil

113

ECAGND 2 1

TAI-T ECH H CB1005KF -221T15 0402

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PRO PRIETAR Y PROPER TY OF COMPAL E LECTRO NICS, INC. AND C ONTAINS CON FIDENTIAL
AND TRADE SECRET INFORMAT ION. TH IS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&SD
DEPART MENT EXC EPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEIT HER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE U SED BY OR DISCL OSED TO ANY THIRD PART Y W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTR ONICS, INC.

3 2

1

CK3

0.1U_02 01_10V6 K

2

ECAGND

0_0402_5%

AD4/GPI O42
AD5/GPI O43

DA0/GPIO 3C

DA2/GPIO 3E
DA3/GPIO3F

GPIO50

GPXIOA04

GPXIOA09

GPXIOD0 6

LK2 SM01000Q 500

ECAGND <45>

+3VALW _EC

2

1

+3VL+3V_EC_VD D

21 EC_VC CST_PG _R

23
26 EC_FAN_PW M1
27 EC_CLR_ CMOS

63

64

65

BOARD_ID

66
75
76

68
70 NMI_DBG#

71 VR_PW RGD

72 EC_MU TE#

83

84

85 VR_ON

86

87 T P_CLK

88 TP_DATA

97 ENBKL

98

99 ME_FLASH_ EN

109 VCIN 0_PH

119

120

126

128

73
74 SYS_PW ROK

89 EC_S0IX_ EN

90

91 CAP_LOCK#
92 PW R_LED#

93

95 SYSON
121 BT_ON_EC

127

100
101

102

103

104

105

106

107

108

110 VCIN1_ AC_IN _R

112 EC_ON

114 O N/OFF#

115

116

117
118 EC_PECI RK17 1

124

2

U_PX@

RK4

56K + -1%0402

SD034560280

R_PX@

RK4

330K +-1% 0402

SD034330380

1

B/I#
ADP_I

ADP_ID
EC_PME#_ EC_R R5178 1 2

EC_SPI_CLK

BAT_CH G_LED

PCH_DPW RO K

PCH_RSMR ST#

USB_ON#

VCIN1_PH
H_PROCHOT#_EC
MAINPWON
EC_BKOFF #

RK25 1 2 0_0402_5%

PCH_PW R_EN
+1.0VS_PG

LID_SW #

SUSP#

VCIN1_AC_IN

+V18R

1

CK8

4.7U_04 02_6.3V6M

2

2017/04/10 2019/12/15

RK2
100K_0402_1%

BOARD_ID

U_UMA@

RK4

43K + -1%0402

SD034430280

R_UMA@

RK4

270K +-1% 0402

SD00000G28 0

0_0201_5%

EC_VCCST_PG_R <9,40>

EC_BEEP# < 32>

EC_FAN_ PW M1 <36>

B/I# <46>

ADP_I <45,47>

KBL_ON# <34>

VR_PW RGD <52>
EC_MUTE# <32>

VR_ON <40,52>
LAN_PW R_EN <29>
TP_CLK <34>

TP_DAT A <34>

ENBKL <5>

W L_PW REN_EC# <30>

ME_FLASH_EN <8>

VCIN0_PH <45>

EC_SPI_ SO <7>
EC_SPI_SI <7>

EC_SPI_CS 0# <7>

TS_GPIO_EC <27>
SYS_PW ROK <9>

EC_S0IX_ EN <12>
BAT_CH G_LED <45>
CAP_LOC K# <34>

PW R_LED# <39>

ACIN <9>

SYSON <12,40, 49>
BT_ON _EC <30>
PCH_DPW ROK <9>

PCH_RSMR ST# <9>

USB_ON# < 38,39>
VCIN1_PH <45>

MAINPW ON <48>
EC_BKOF F# <27>

+1.0VS_PG <50>

EC_ON <39,48>

ON/OFF# <3 9>
LID_SW # <39>

SUSP# <12,40,4 9>

2 43_0402_1%

+3VALW _EC

Compal SecretData

Deciphered Date

1

EC Board ID (UMA, DIS, phase) control table

RK4

DB SI PV MV DB SI PV MV
UMA 15K 27K 43K 75K 130K 200K 270K 430K
DIS

DGPU_PWR_EN <10,24>
PCH_PW R_EN <40,51>

H_PECI <5>

20K

U_DB_UMA_15kohm:SD034150280, S RES 1/16W 15K+-1%0402
U_DB_ DIS_20kohm:SD034200280, S RES 1/16W 20K +-1% 0402

U_SI_UMA_27kohm:SD034270280,S RES1 /16W27K +-1%0402 (2017-10-05 : 2018OPP Add EC Clear CMOS function)
U_SI_ DIS_33kohm:SD034330280, S RES 1/16W 33K +-1%0402

U_PV_UMA_43kohm:SD034430280, S RES 116W 43K +-1% 0402 RK106 1 2 0_0402_5%
U_PV_ DIS_56kohm:SD034560280, S RES 1/16W 56K +-1%0402

U_MV_UMA_75kohm:SD034750280, S RES 1/16W 75K +-1% 0402
U_MV_ DIS_100kohm:SD034100380, S RES 1/16W 100K+-1%0402

R_DB_UMA_130kohm:SD034130380, S RES 116W 130K+-1%0402
R_DB_ DIS_160kohm:SD034160380, S RES 116W160K +-1%0402

R_SI_UMA_200kohm:SD034200380, SRES 1/16W 200K+-1% 0402
R_SI_ DIS_240kohm:SD000001B80, S RES 116W 240K+-1%0402

R_PV_UMA_270kohm:SD00000G280, S RES 1/16W 270K +-1% 0402
R_PV_ DIS_330kohm:SD034330380, S RES 1/16W 330K+-1%0402

ADP_ID <45>

EC_PME# <29>

KBL-U KBL-R

(0x02) (0x04) (0x06) (0x08) (0x0A) (0x0C) (0x0E) (0x10)

33K

56K

100K

160K

240K

(0x03)

(0x05)

EC_CLR_ CMOS

<52> VR_HOT#

EC_SPI_CLK RC369 1 2 HOST_SPI_0_CLK_R

CC128 RC369 place near ECSid e

Custom

(0x07)

(0x09)

(0x0B)

Reserve EC_CLR_CMOS for clear CMOS

(2016-03-04 ::::Confirmintelplatformnotsupport ECClear CMOS function)

13

2

G

R483
10K_0402_5%

@

1 2

VR_HOT # 1

RK8

H_PROCHOT#_EC 2

@QK1

2N7002_SOT23-3

SB00000 EN 00

RK91 2 0_0402_5%

TP_CLK

TP_DAT A

PLT_RST# 7 2
EC_ON 6 3

PCH_PW R_EN 5

PBTN_O UT# R295 1 @

EC_CLR_ CMOS 1 @ 2 R K107

LID_SW #

EC_SMB_CK 1
EC_SMB_DA 1
EC_SMB_CK 2
EC_SMB_DA 2

RK12 1 2 4.7K_0402_5%

RK13 1 2 4.7K_0402_5%

RP12

8 1

100K_0804_8P4R_5%

EMI@ 15_0402_5%

4

RK18 2 @ 1 47K_ 0402_5%

EC_SCI# RK14 2 1 10K_0402_5%

SYSON RK23 1 @ 2 100K_0402 _5%

SUSP# RK27 1 2 10 0K_0402_5%

50V J NPO 0402

EMI request

Compal Electronics,Inc.

Titl e

EC ENE-KB9022

ize Document Number

CSL50 LA-E791P

(0x0D)

@

D

Q51
2N7002K_SOT23 -3

SB00000 EN0 0

S

2 0_0402_5%

D

1

G

S

3

2 1K_0402_ 5%

10K_0402_5%

8
7
6
5

2.2K_0804_8P4R _5%

CC144 22P

@EMI@

1

330K

1 RP11
2
3
4

Sheet 33 of 59Date: Tuesday, J anuary 09, 2018

CLR_CMOS# <9>

+3VALW _EC

+3V_SMBUS

560K

(0x0F)

(0x11)

PROCHO T# <5>

+3VALW

+3VL

+3VS

HOST_ SPI_0_CLK_R <7,35>

Rev

v0.3

TP Button BDConnector

<7,13,29,30,33,35,40,48,49,50,51>+3VALW

<12,37,38,39,40,48,49,52,53>+5VALW

+3VALW

+5VALW

<33> TP_CLK
<33> TP_DATA

<7> TP_SMBCLK
<7> TP_SMBDATA

PS2+SMBus

PESD5V0U2BT 3P CC SOT23ESD

<33> KBL_ON#

DM5

SCA00000T00

ESD@

100K_0402_5%

R23

+3VALW

2

3

1

@

2

1

1

2

0.047U_0402_16V7K

@

C68

@

C135

470P_0402_50V8J

Q9

2

PJ2301 1PSOT23-3

1

SB00000T900

2

1

C136

2

470P_0402_50V8J

+5VS+5VALW

+5VS_KBL

S

G

D

1 3

CONN@

JTP

1

1

2

2

3

3

4

4

5

7

5 G1

6

8

6 G2

ACES_51524-0060N-001

SP010014M10

ACES_51575-00401-001

4

4 G2

3

3 G1

2

2

1

1

JKBL

SP01002BY00

6
5

<33> KSI[0..7]

<33> KSO[0..17]

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

KSO17
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10

KSO9
KSO8
KSO7

KSO6

KSO5
KSO4
KSO3
KSO2
KSO1

KSO0

<33>CAP_LOCK#

<33> MUTE_LED_OUT

1 1

CC122 CC123

100P_0402_50V8J 2100P_0402_50V8J

2

ESD@ ESD@

JKB1 KB Spec
Pin1 KSI1 KSI1
Pin32 5V 5V

CAP_LOCK#

CAP_LOCK#
MUTE_LED_OUT

R203

1K_0402_5%

1
1

R207

549_0402_1%

+5VS

KSI0

+5VS

2
2

Keyboard conn

CONN@

JKB

ESD@

32

32

31

31

30

30

29

29

28

28

27

27

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5
4

3

3

2

2

1

1

ACES_50690-0320N-P01

SP01001RG00

KSI1

KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
KSO16
KSO17

CAP_LOCK#_R

MUTE_LED_OUT_R 4

C193 2 1100P_0402_50V8J

G2
G1

34
33

SecurityClassification

IssuedDate

THIS SHEET OF ENGIN EERING DRAW ING IS THE PROPRIETARY PROP ERT Y OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENSSTiIzAeL
AND TRA DE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPET ENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
MAY BE U SED BY OR DISCLOSED TO AN Y THIRD PART Y W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL E LECTRONICS , INC.

2017/08/24 2018/08/24

Compal Secret Data

DecipheredDate

Custom

Title

DocumentNumber

Date: Friday,January 05, 2018 Sheet 34 of 59

Compal Electronics, Inc.

KB/TP

CSL50 LA-E791P

Rev

v0.3

5

4

3 2

+3VALW

1

+3VALW <7,13,29,30,33,34,40,48,49,50,51>

D D

TPM2.0

<9,29,30,31,33>PLT_RST#

<7,33> HOST_SPI_0_CLK_R

<7,33>SERIRQ

<7> HOST_SPI_0_CS2#

<7> HOST_SPI_0_SI

<7> HOST_SPI_0_SO

+3VS_TPM

C C

B B

RT6 1 2 HOST_SPI_0_CLK_R_TPM 19

TPM@33_0402_5%

RT7 1 2 HOST_SPI_0_CS2#_TPM 20

TPM@ 33_0402_5%

RT8 1 2 HOST_SPI_0_SI_TPM21

TPM@ 33_0402_5%

RT9 1

TPM@33_0402_5%

1 TPM@ 2 PLT_RST#_TPM 17

R28 0_0402_5%

1 TPM@2 TPM_SERIRQ

R52020_0402_5%

2

HOST_SPI_0_SO_TPM

2 1 TPM_GPIO

RT10 TPM@ 4.7K_0402_5%

1 @ 2

RT35

4.7K_0402_5%

RT12

4.7K_0402_5%

TPM@

TPM_PP

1

2

UT1

RST#

18

PIRQ#

SCLK

CS#

MOSI

24

MISO

6

GPIO

7

PP

2

GND

9

GND

23

GND

32

GND

33

PAD

TPM@

SLB9670VQ1.2 FW6.40_VQFN32_5X5

SA00009N230

VDD
VDD
VDD

NC
NC
NC

NC
NC
NC

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC

1

8

2

2
3

4
5

10

11
12

13
14

15
16
25
26
27
28
29
30
31

+3VS_TPM

0.1U_0402_1 6V4Z

1

2

TPM@

CT1

0.1U_0402_1 6V4Z

1

2

TPM@

CT3

RC9341 2 0_0402_5%

1

1

CT4

0.1U_0402_1 6V4Z

2

TPM@

2

TPM@

CT2

1U_0402_6.3V6K

+3VALW

TPM@

Screw Hole

H1 H2

H_2P4N H_3P0

@

@

1

@

FIDUCIAL_C40M80

JESDJUMP@

1

1 2

JUMP_43X39

1

H13 H14

H_2P3H_3P3

1

FD1

2

H4

H_3P0

@

1

H16 H17 H18 H19

H_2P3 H_2P4X2P9N H_6P0NH_6P0N

1

@ @

FD2

1

FIDUCIAL_C40M80

@

@

1

1

@

1

@

1

FD3

@

1

FIDUCIAL_C40M80

CPU

H8 H9 H10 H11 H_5P0

H_5P0H_5P0H_5P0

@ @

@ @

1

1

@

1

FD4

1

FIDUCIAL_C40M80

1

1

@

A A

SecurityClassification

IssuedDate

THIS SHEET OF ENGIN EERING DRAW ING IS THE PROPRIETARY PROP ERT Y OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENSSTiIzAeL
AND TRA DE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPET ENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY
BE USED BY OR DISCLOSED TO ANY T HIRD PARTY W ITHOUT PRIOR W RITTE N C ONSENT OF COMP AL ELECTRO NICS, INC.

5

4

2017/08/24 2018/08/24

3 2

Compal Secret Data

DecipheredDate

Title

DocumentNumber

Date: Friday,January 05, 2018 Sheet

Compal Electronics,Inc.

TPM/Screw

CSL50 LA-E791P

1

35 of 59

Rev

v0.3

A

+5VS

1A

1 1

1Rshort@2+FAN1

R5177

0_0603_5%

40 mils

C4801

10U_0603_10V6M

Layout notes

L

C4801 C5214 close toCONN

C5214

0.1U_0402_1 6V7K

1

1

Close to Connector

2

2

2 2

B

<33> FAN_SPEED1

C D

+3VS

1

RE50
10K_0402_5%

2

1

CE24

0.01U_0402_25V7K

2

+FAN1

1 @ 2 EC_FAN_PWM1

<33> EC_FAN_PWM1

RE51

10K_0402_5%

+FAN1

CONN@

JFAN

6

GND2

5

GND1

4

4

3

3

2

2

1

1

ACES_50271-0040N-001

SP02000TS00

E

3 3

4 4

SecurityClassification

IssuedDate

THIS SHEET OF ENGIN EERING DRAW ING IS THE PROPRIETARY PROP ERT Y OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENSSTiIzAeL
AND TRA DE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPET ENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
MAY BE U SED BY OR DISCLOSED TO AN Y THIRD PART Y W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/08/24 2018/08/24

C D

Compal Secret Data

DecipheredDate

Title

DocumentNumber

Custom

Date: Friday,January 05,2018

Compal Electronics, Inc.

FAN

CSL50 LA-E791P

Sheet 36 of 59

E

Rev

v0.3

5

4

3 2

1

<27,28,32,33,34,36,40> +5VS

2.5" SATAHDD

D D

+5VS

C C

<PV> change shortpad

R201 1 Rshort@20_0603_5%
R202 1 Rshort@20_0603_5%

+5VS_HDD1

<11> SATA_CTX_DRX_P0
<11> SATA_CTX_DRX_N0

<11> SATA_CRX_DTX_N0
<11> SATA_CRX_DTX_P0

*Design Constraint:AC capacitors to be placed as close
as possible to theconnector.
Maximum distance from AC capacitors to connector is 500
mils.

C155 1 2 0.01U_0402_16V7K
C156 1 2 0.01U_0402_16V7K

C153 1 2 0.01U_0402_16V7K
C154 1 2 0.01U_0402_16V7K

<12,34,38,39,40,48,49,52,53> +5VALW

<7,13,29,30,33,34,35,40,48,49,50,51>+3VALW

+5VS_HDD1

SATA_CTX_C_DRX_P0
SATA_CTX_C_DRX_N0

SATA_CRX_C_DTX_N0
SATA_CRX_C_DTX_P0

2

C140

470P_0402_50V8J

1

EMI@

CONN@

JHDD

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

GND

10

GND

ACES_51524-00801-001

SP01001A910

+5VS
+5VALW
+3VALW

SATAODD

+5VALW

1

ROD1

100K_0402_5%

D

1 2

2

<10>ODD_PWR

B B

+5VS

G

QOD2
2N7002K_SOT23

SB00000EN00

S

3

80mil 80mil

1

COD2

2

0.047U_0402_16V7K

10U_0603_6.3V6M

COD1

2 1

PJ23011P SOT23-3

1

ROD2
1K_0402_5%

2 2

G

1

3

S

D

QOD1

SB00000T900

2 @ 1

ROD3 0_0805_5%

+5VS_ODD

1

2

1 0.01U_0402_16V7K
1 0.01U_0402_16V7K

1 0.01U_0402_16V7K

2

1 0.01U_0402_16V7K

0_0402_5%

CS11 2
CS14 2

CS15
CS18 2

<10>ODD_DA#

<11> SATA_CTX_DRX_P1

<11> SATA_CTX_DRX_N1

<11> SATA_CRX_DTX_N1

<11> SATA_CRX_DTX_P1

<11>ODD_PLUG#

1

@

COD

COD

2

3

0.1U_0402_1 6V4Z

4

4.7U_0603_6 .3V6K

R5192

1Rshort@2

+5VS_ODD

SATA_CTX_C_DRX_P1
SATA_CTX_C_DRX_N1

SATA_CRX_C_DTX_N1
SATA_CRX_C_DTX_P1

1 Rshort@2ODD_DA#_R R5193

ODD_PLUG#_R

0_0402_5%

1

ESD@

CS7

2

0.1U_0402_16V7K

JODD

S1

GND

S2

A+

S3

A-

S4

GND

S5

B-

S6

B+

S7

GND

P1

DP

P2

+5V

P3

+5V

P4

MD

P5

GND

P6

GND

GND GND

SDAN_603010-013041

SP010029L00
SDAN_603010-013041_13P
CONN@

1

2

A A

SecurityClassification

IssuedDate

THIS SHEET OF ENGINEERING DRAW ING IS TH E PROPRIETA RY PRO PERTY OF C OMPAL EL ECT RONICS, INC. AND CONTAINS CONFIDENSTiIIzAeL
AND TRA DE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZE D BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NO R THE INFORMAT ION IT CONTAINS MAY
BE USED BY OR DISC LOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

5

4

2017/08/24 2018/08/24

3 2

Compal Secret Data

DecipheredDate

Title

DocumentNumber

Custom

Date: Friday,January05,2018 Sheet

Compal Electronics, Inc.

HDD/ODD Conn

CSL50 LA-E791P

1

37 of 59

Rev

v0.3

A

2

< 11>USB3_CTX_DRX_N1

<11> US B3_CTX_ DRX_P1

1 1

< 11>USB3_CRX_DTX_N1

<11> US B3_CRX_D TX_P1

RS 6 EMI@ 0_0402_5% 1

RS 3 EMI@ 0_0402_5% 1

1 USB 3_CTX_C_ DRX_N1 1 2 USB3_CTX_L_DRX_N1

CS2

0.1U_0402_16V7K

1 USB 3_CTX_C_ DRX_P1 1

2

0.1U_0402_16V7K

CS1

2

USB3_CRX_L_DTX_N1

2

RG76

@ 150_ 0402_5%

1

2

USB3_CRX_L_DTX_P1

RS 2 EMI@ 0_0402_5 %

RS1 EMI@ 0_040 2_5%

2

B

2

RG75

@ 150_ 0402_5%

1

USB3_CTX_L_DRX_P1

< 33,39>U SB_ON#

+5VAL W

W=100mils

USB_ON # 1

RS 4 Rshort@ 0_0402_5%

1

CS3

0.1U_0402_16V7K

2

2

C

<12,24,34,37,39,40,48,49,52,53> +5V ALW

US1

1

OUT

5

IN

2

GND

4

EN

3

OCB

EM520 3J-20 SOT23 5P LOAD SW ITCH

SA00008RA00

+USB_ VCCA

CS 4

EMI@

W=100mils

1

2

1000P _0402_50V7K

D

+5VAL W

1

1

CS5

2

0.1U_0402_16V7K

@

1

+

CS 6

2

47U_0805_6.3V6M

CS28

CS22

390P_0402_5 0V7K

2 1

2

EMI@

150U_B 2_6.3 VM_R45M

E

USB2.0/USB3.0 port 1

USB20_N1_ R
USB20_P1_R

+USB_ VCCA

JUSB 1

1

VBUS

2

D-

3

D+

4

GND1

5

SSRX-

6

SSRX+ GND3

7

GND2 GND4

8

SSTX- GN D5

9

SSTX+ GND6

ACON_TA RAW -9U13 95_9P-T

DC231709285
CONN@

10
11
12
13

< 11>U SB20_P1

< 11>U SB20_N 1

RS 47 @E MI@

1 2

0_0201_ 5%

SM070 005U00 DLM 0NSN900HY2D_4P 1

1

4

LM3

USB2.0ChokePart:
Main:SM070005U00, S COM FI_ MURATA DLM0NSN900HY2D(MURATA)
2nd:SM070004X00,SCOMFI_PANASONICEXC14CE900U(PANASONIC)

4

EMI@

RS 48 @E MI@

1 2

0_0201_ 5%

2

2

3

3

USB20_P1_R

USB20_N1_ R

USB3_CTX_L_DRX_P1

USB3_CTX_L_DRX_N1

USB3_CRX_L_DTX_P1
USB3_CRX_L_DTX_N1

DM2

1

1

2

2

4

4

5

5

3

3

8

DT1140-04LP-7 U-DFN2510-10

SC3000 05M00

ESD@

9 USB3 _CTX_L_DRX _P1

10

8 USB3_CTX_L_DRX_N1

9

7 USB3_ CRX_L_DTX_P 1

7

6 USB3_CRX_L_DTX_N1

6

USB3_CRX_L_DTX_N1
USB3_CRX_L_DTX_P1

USB3_CTX_L_DRX_N1
USB3_CTX_L_DRX_P1

2 2

USB2.0ChokePart:
Main:SM070005U00, S COM FI_ MURATA DLM0NSN900HY2D(MURATA)
2nd:SM070004X00,SCOMFI_PANASONICEXC14CE900U(PANASONIC)

RS 49 @E MI@

1 2

0_0201_ 5%

DLM0NSN900HY2D_4P

SM070005U00

< 11>U SB20_P2

< 11>U SB20_N 2

< 11>USB3_CTX_DRX_N2

<11> US B3_CTX_ DRX_P2

3 3

4 4

< 11>USB3_CRX_DTX_N2

<11> US B3_CRX_ DTX_P2

CS23

CS24

RS 10 E MI@ 0_0402_5% 1

RS 9 EMI@ 0_0402_5% 1

1

4

LM5

USB3_CTX_C_DRX_N2

12

0.1U_0402_16V7K

USB3_CTX_C_DRX_P2

12

0.1U_0402_16V7K

2

2

1

4

EMI@

RS5 0 @EMI@

1 2

0_0201_ 5%

USB3_CRX_L_DTX_N2

2

RG107

@ 150_ 0402_5%

1

USB3_CRX_L_DTX_P2

2

2

3

3

USB20_P2_R

USB20_N2_ R

RS 8 EMI@ 0_0402_5% 1

2

RS 7 EMI@ 0_0402_5% 1

2

USB3_CTX_L_DRX_N2

RG106

@ 150_ 0402_5%

1

2

USB3_CTX_L_DRX_P2

USB3_CRX_L_DTX_N2 1

USB3_CRX_L_DTX_P2 2

USB3_CTX_L_DRX_N2 4

USB3_CTX_L_DRX_P2 5

DM1 4

ESD@

1

2

4

5

3

3

8

USB3.0ESDPart:
Main:SC300005M00,SDIO(BR) DT1140-04LP-7U-DFN2510-10(DIODES))))
2nd:SC300003Z00, SDIO(BR)PUSB3F96DFN2510A-10ESD(NXP)
3rd:SC300005N00, SDIO(BR) L02U5V0NA-4C SLP2510P8(LITE ON)

9 USB3_CRX_L_DTX_N2

10

8 USB 3_CRX_L_D TX_P2

9

7 USB3_CTX_L_DRX_N2

7

6 USB 3_CTX_L _DRX_P2

6

DT1140-04LP-7 U-DFN2510-10

SC3000 05M00

USB20_P1_R

+USB_ VCCA

USB20_N1_ R

DM1

6

5

I/O2

I/O4

VDD4GND

I/O3 I/O1

AZC099 -04S .R7G_SOT2 3-6

SC3000 01G00

USB2.0/USB3.0 port 2

+USB _VCCA

USB20_N2_ R
USB20_P2_R

USB3_CRX_L_DTX_N2
USB3_CRX_L_DTX_P2

USB3_CTX_L_DRX_N2
USB3 _CTX_L_D RX_P2

USB20_P2_R

3

2

1 USB20 _N2_R

JUSB 2

1

VBUS

2

D-

3

D+

4

GND1

5

SSRX-

6

SSRX+ GND3

7

GND2 GND4

8

SSTX- GN D5

9

SSTX+ GND6

ACON_TA RAW -9U13 95_9P-T

DC231709285
CONN@

10
11
12
13

Security Classification

Issued Date

THIS SHE ET OF ENGINEE RING DRAW ING IS THE PROPRIE TARY PROP ERTY OF COMP AL EL ECTRONICS , INC. AND CONTAINS CONFIDENTSIiiA
AND TRA DE SEC RET INF ORMATI ON. THIS S HEET MAY NOT BE TRA NSFERE D FR OM THE CU STODY OF THE CO MPETENT DIVISION OF R& D
DEPAR TMENT EXC EPT AS AU THORIZED B Y COMPA L ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CONTA INS

A

B

C

MAY BE US ED BY OR DISCLOS ED TO ANY THIRD PA RTY W ITHOUT PRIOR W RITTEN CONSE NT OF COMPAL ELEC TRONICS, INC.

2017/08/24 2018/08/24

Compal Secret Data

Deciiphered Date

D

Title

zeeLDocument Number

Custom

Compal Electronics, Inc.

USB 3.0/2.0 conn

CSL50 LA-E791P

E

Rev

Sheet 38 of 59Date: Tuesday, J anuary 09, 2018

v0.3

A

+3V_LID

+3VL

R215

100K_0402_5%

<33> ON/OFF#

1 1

ON/OFF#

Layout notes

L

JP6 place Bottomlayer

AZ5123-02S.R7G 3P CA SOT23

Q4108

2 1

1 3

2N7002K_SOT23-3

SB00000EN00

ESDDiode

LID_SW#
ON/OFF#_R

3

ESD@

D1

SCA00001B00

Power Button Switch

2

G

S

1 2

ON/OFF#_R 1

@

JP6

SHORTPADS

D

2

1

Lid Switch (Hall Effect Sensor)

8

5

7

4.7K_0402_5%

10P_0402_50V

8 J

1

C19

2

+3V_LID

+3V_LID

R126

2 1

1

100P_0402_50V

8 J

2

ESD@

+3V_SMBUS

+3VL +3V_LID

DH2

0.1U_0201_10V6K

RB751V-40 SOD-323

1 2

1

C18

2

LID_SW#_OUT

2

10K_0402_5%

DB@

<33,48> EC_ON

2

APX8131AI-TRG SOT-23

1 R124

+3VL

U4018

3 LID_SW#_OUT

OUT

VDD

1

GND

SA00009EM00

+3VL

2

G

Q32

1

3

D

S

DB@

2N7002K_SOT23-3

SB00000EN00

U4019

1 CP VCC
2 D PR#

6

3 Q# CLR#

Q

4 GND

NL17SZ74USG US 8P FLIP-FLOP

SA00003ML00

DB@

DH3 DB@ RB751V­40SOD-323

2 1

2 1

DH4
RB751V-40 SOD-323

2 1

DH5
RB751V-40SOD-323

2 2

3 3

B

SW1 SN10000CU00

SW TJG-533KQRH SPST DIP H1.55 6P

C5228

+3V_LID

DB@

1 2

2

6

5

1 2

R5197

0_0402_5%

R13

470K_0402_5%

+3V_LID

DB@

1 2

3
4

R125

10K_0402_5%

LID_SW# <33>

C D

<13,33,46,47,48> +3VL

<6,7,9,10,11,13,17,18,19,2 2,23,24,27,28,29,30,31,32,33,36,40,52,55> +3VS

IO BD Connector ( USB2.0,Card reader,HDD & PWR LED )

USB2.0( on small BD)

<33,38> USB_ON#

<11> USB20_N3

<11> USB20_P3

<11> USB20_N4

<11> USB20_P4

<12,24,34,37,38,40,48,49,52,53> +5VALW

<7,13,29,30,33,34,35,40,4 8,49,50,51,55> +3VALW

+5VALW

+3VS

USB20_N4_R

Cardreader

<11> SATA_LED#
<33> PWR_LED#

CC1523.3P_0402_50V8J

EMI@

CC1543.3P_0402_50V8J

EMI@

USB20_P4_R
USB20_N3_R

USB20_P3_R

1

2

470P_0402_50V8J

LM4

4

4 3

1

1 2

SM070005U00 DLM0NSN900HY2D_4P

LM6

4

4 3

1

1 2

SM070005U00 DLM0NSN900HY2D_4P

EMI@

1 2

1

EMI@EMI@

C138 C137

2

470P_0402_50V8J

RS51 @EMI@

1 2

0_0201_5%

EMI@

RS52 @EMI@

1 2

0_0201_5%

RS53 @EMI@

1 2

0_0201_5%

EMI@

RS54 @EMI@

1 2

0_0201_5%

C139

470P_0402_50V8J

3

2 USB20_P3_R

3

2

CONN@

JIO

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

CVILU_CF31181D0R4-10-NH

SP011411241

USB20_N3_R

USB20_N4_R

USB20_P4_R

E

+3VL
+5VALW
+3VS
+3VALW

19

G1

20

G2

4 4

Security Classification

Issued Date

THIS S HE E T OF E NGI NE ERI NG DRA W ING IS THE PR OP RIE TARY PR OP ERTY OF COM PA L ELE CTRO NICS , INC. A ND CON TA INS CONFIDENSSTiIzAeL
AND TRA DE SE CRET INF ORM A TION . THIS S HEE T M AY N OT BE TRA NSFE RE D FRO M THE CUSTO DY OF THE CO MP ETE NT DIVIS ION OF R&D

DEP ARTM E NT EX CEP T AS AU THOR IZE D BY CO MP AL ELE CTR ONIC S , INC. NEITHE R THIS S HEE T NOR THE INF ORM A TION IT CON TAIN S

A

B

MA Y BE US ED BY OR D IS CLOS ED TO A NY THIRD P ARTY W ITH OUT PRI OR W RITTE N C ONS E NT OF COM P AL ELE CTRO NICS , IN C.

2017/0 8/2 4 2018/0 8/2 4 T itle

C D

Compal Secret Data

Deciphered Date

Custom

Document Number

Compal Electronics, Inc.

IOCON

CSL50 LA-E791P

Sheet 39 of 59Date: Tuesday, January 09, 2018

E

Rev

v0.3

A

+3VALW

1 1

2 2

+5VALW

<12,33,49>SUSP#

SUSP#

1

1

CC16

CC16

2

1

0.1U_0402_2 5V6

@ESD@ @ESD@ @ESD@ @ESD@@ESD@

1

CC15

2

2

0

0.1U_0402_2 5V6

7

0.1U_0402_2 5V6

+5VALW

Q21

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

EM5209VF_DFN14_3X2

1

CC162

2

0.1U_0402_25V6

SA00007PM00

1

CC158

2

0.1U_0402_25V6

For +1.8V_PRIM Discharge

3 3

<33,51> PCH_PWR_EN

B

14

VOUT1

13

VOUT1

12

CT1

GND

CT2

VOUT2
VOUT2

GPAD

+5VALW +1.8V_PRIM

12

R5092
100K_0402_1%

61

Q5001A

2

L2N7002SDW1T1G2NSC88-6

SB00001FF00

C557 1 2 680P_0402_50V7K

11

10

C554 1 2 100P_0402_50V8J

9
8

15

PCH_PWR_EN#5

10U_0603_6.3V6M

1

C575

@RF@

2

1

R5093
22_0603_1%

Q5001B
L2N7002SDW1T1G2NSC88-6

SB00001FF00

4 3

2

C D

+3VS
+5VS

+3VS

1

C570

10U_0603_6.3V6M

2

+5VS

CC140

@ESD@

0.1U_0402_2 5V6

1

CC163

2

<9,12,33> PM_SLP_S3#

<9,12,33,49>PM_SLP_S4#

22U_0805_6.3V6M

1

2

+3VS <6,7,9,10,11,13,17,18,27,28,29,30,31,32,33,36,39,52>
+5VS <27,28,32,33,34,36,37>

For meet tPLT17 & tCPU28 powerdown sequence.

tPLT17 : 1us (Max)
tCPU28 :1us (Max)

+3VALW

1

R5096

@

100K_0402_1%

2

PM_SLP_S3_H

61

@

PM_SLP_S3#

For meet tPLT15 power downsequence(Un-Stuff)
tPLT15 : 1us(Max)

2

R5095@

100K_0402_1%

5

Q5003A
L2N7002SDW1T1G2N SC88-6

SB00001FF00

+3VALW

1

2

PM_SLP_S4_H 5

34

@

Q5003B
L2N7002SDW1T1G2NSC88-6

SB00001FF00

61

@

2

Q5002A
L2N7002SDW1T1G2NSC88-6

SB00001FF00

34

@

Q5002B
L2N7002SDW1T1G2NSC88-6

5

SB00001FF00

61

@

2

Q5004A
L2N7002SDW1T1G2NSC88-6

SB00001FF00

34

@

Q5004B
L2N7002SDW1T1G2NSC88-6

SB00001FF00

SUSP#

E

VR_ON <33,52>

EC_VCCST_PG_R<9,33>

SYSON<12,33,49>

4 4

SecurityClassification

IssuedDate

THIS SHEET OF ENGINEERING DRAW ING IS TH E PROPRIETA RY PRO PERTY OF C OMPAL EL ECT RONICS, INC. AND CONTAINS CONFIDENSTiIzAeL
AND TRA DE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZE D BY CO MPAL ELECTRONI CS, INC. NEITHER THIS SHEET NO R THE INFORMAT ION IT CONTAINS
MAY BE U SED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONS ENT OF COMPAL ELEC TRO NICS, INC.

A

B

2017/08/24 2018/08/24

C D

Compal Secret Data

DecipheredDate

Document Number

Custom

Title

Compal Electronics, Inc.

DC Interface

CSL50 LA-E791P

E

Rev

v0.3

40 of 59Date: Friday,January05,2018 Sheet

5

4

3 2

1

2 1

EMI@ PC1

0.022U_0402_25V7K

PR3
10K_0402_5%

EMIVGA@ PL12

5A_Z80_0805_2P

1 2

EMI@ PL11

5A_Z80_08 05_2

1

2 1

EMI@ PC2

1000P_0402_50V7K

12

PR5

10K_0402_5%

+19V_VIN

P

2

<33> AC_LED#

1

1
2

2

EMI@ PC4

EMI@ PC3

100P_0402_50V8J

1000P_0402_50V7K

ADP_ID <33>

12

2 1

PD3

2 1

LUDZS3.6BT1G_SOD323-2

PC6

@ PC5

100P_0402_50V8J

1000P_0402_50V7K

<33> BAT_CHG_LED

@PR1

0_0402_5%

1 2ACIN_LED

1

PR2
100K_0402_5%

2

PR4
750_0402_1%

1 2Charge_LED

1

PR6

100K_0402_5%

2

+19V_ADPIN

@ PJP1

D D

C C

ACES_51483-00801-001

1

1

2

2

3

3

4

4

5

5

6 ADP_SIGNAL

6

7

7

8

8

9

GND

10

GND

Charge_LED

ACIN_LED

2

3

ESD@ PD1

1

L30ESD24VC3-2_SOT23-3

ADP_SIGNAL1 2

2

3

ESD@ PD2

1

L30ESD24VC3-2_SOT23-3

<33,47> ADP_I

+3VALW_EC

1

PR9

16.2K_0402_1%

1

PR10

5.9K_0402_1%

1 22

PH1

B B

100K_0402_1%_B25/504250K

ECAGND <33>

A A

SecurityClassification

IssuedDate

THIS SHEET OF ENGIN EERING DRAW ING IS THE PROPRIETARY PROP ERT Y OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENSSTiIzAeL
AND TRA DE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPET ENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY
BE USED BY OR DISCLOSED TO ANY T HIRD PARTY W ITHOUT PRIOR W RITTE N C ONSENT OF COMP AL ELECTRO NICS, INC.

5

4

2016/09/01 2019/09/01

3 2

Compal Secret Data

DecipheredDate

1 2

PR13
10K_0402_1%

2

Compal Electronics, Inc.

Title

DCConn

DocumentNumber

CSL50 LA-E791P

Date: Friday, January05,2018

VCIN1_PH <33>VCIN0_PH <33>

Rev

v0.3

59

of

Sheet

1

45

5

D D

@ PR18

0_0402_5%

OCTEK_BTJ-08KPBR4B

C C

@

GND
GND

PJPB1

8
7
6

5

4
3
2
1

10
9
8
7
6

5
4

3
2
1

EC_SMB_CK1_R
EC_SMB_DA1_R

+3V_LID_R

B/I#_R

1 2

4

+3V_LID

+12.6V_BATT+

PR14
100_0402_5%

1 2

PR15
100_0402_5%

1 2

PR17
100_0402_5%

1 2

2 1

2 1

@EMI@ PC10

100P_0402_50V8J

+3VL

1

2

EMI@ PL13

5A_Z80_0805_2P

1 2

EMI@ PL14

5A_Z80_0805_2P

1 2

EMI@ PC8

1000P_0402_50V7K

PR16
100K_0402_5%

3 2

@EMI@

PC9

PC11

2 1

0.01U_0402_50V7K

100P_0402_50V8J

2 1

EMI@

EC_SMB_CK1 <33,47>

EC_SMB_DA1 <33,47>

B/I# <33>

+12.6V_BATT

L2N7002SDW1T1G2N SC88-6

+3VL

PQ2B

+3V_LID +19VB

12

PR20
470K_0402_5%

5

1

4 3

2

1

PR19

1.8K+-1%0805

6 2 1

2

1

PR21

@

1M_0402_5%

PQ2A

L2N7002SDW1T1G2NSC88-6

B B

A A

SecurityClassification

IssuedDate

THIS SHEET OF ENGIN EERING DRAW ING IS THE PROPRIETARY PROP ERT Y OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENSSTiIzAeL
AND TRA DE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPET ENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY
BE USED BY OR DISCLOSED TO ANY T HIRD PARTY W ITHOUT PRIOR W RITTE N C ONSENT OF COMP AL ELECTRO NICS, INC.

5

4

2016/09/01 2019/09/01

3 2

Compal Secret Data

DecipheredDate

Compal Electronics, Inc.

Title

BATTConn

DocumentNumber

CSL50 LA-E791P

Date: Friday, January05,2018

Sheet of

1

Rev

v0.3

5946

A

B

C

D

Protection for reverse input

13

D

2

G

PRB2 @

1 1

1M_0402_5%

1 2

CHG_N002

@ PRB3

3M_0402_5%

1 2

@ PQB2

2N7002KW_SOT323-3

S

+19VB

+19V_VIN

2 2

3 3

PQB11
EMB04N03H_EDFN5X6-8-5

5

PCB4

2 1

2200P_0402_50V7

K

4

ACDRV_CHG_R

P1

1
2
3

PCB5

2 1

0.1U_0402_25V

PRB9

2 1

4.12K_0603_1

6

2 1

%

PQB12

AON7506_DFN33-8-5

1
2
3

PRB10

4.12K_0603_1

%

5

4

+3VL

<33> VCIN1_ACOK

+19V_VIN

PCB1

P2

0.1U_0402_25V

2 1

6

1 2

PRB1

0.01_1206_1%

1
2

1 2

PCB10

0.1U_0402_25V6

ACP_CHG

PRB15

100K_0402_1%

PRB17
422K_0402_1%

1 2

4
3

CMSRC_CHG

ACDRV_CHG

2 1

ACN_CHG

+19V_VIN

3

1 1

PCB11

0.1U_0402_25V

6

2

PCB13

1 2

VCC_CHG

1U_0603_25V6K

20

21

PAD

1

ACN

2

ACP

3

CMSRC

BQ24725ARGRR_QFN20_3P5X3P5

4

ACDRV

5

ACOK

6

ACDET _CHG

EMI@ PLB11

1UH_2.8A_30%_4X4X2_F

1 2

2

PDB1
BAS40CW_SOT323-3

CHG_N003PCB12

0.047U_0402_25V7K

1 2 CHG_N001

PRB6 10_1206_1%

LX_CHG

UG_CHG

18

19

VCC

PHASE

PUB1

IOUT

ACDET

7

8

IOUT_CHG

HIDRV

SDA

12

PRB7

2.2_0603_5%

REGN_CHG

BTST_CHG 2 1

16

17

BTST

REGN

LODRV

BATDRV

ILIM

SCL

9

10

2 1

1 SCL_CHG

+19VB_CHG

2 1

2 1

@ PCB6

10U_0805_25V6K

PDB2
RB751V-40_SOD323-2

1 2

PCB14

1U_0603_25V6K

15 LG_CHG

14

GND

13

SRP1 2 SRP_R

SRP

SRN1 2 SRN_R

12

SRN

11 BATDRV_CHG

ILIM_CHG

12

PCB21

PRB20

0.01U_0402_50V7K

100K_0402_1

%

PCB7

2 1

@EMI@ PCB8

2200P_0402_50V7

10U_0805_25V6K

AONH36334_DFN3X3A8-10

PRB13
10_0603_1%

PRB14

6.8_0603_1%

1 2

PRB16
453K_0402_1%

PQB13
AON7506_DFN33-8-5

1

PRB5

4.12K_0603_1%

2 1 SRP_R

5

2 BATDRV_CHG_R

PRB11

0.01_1206_1%

2

PCB17

0.1U_0402_25V

6

K

2 1

PCB25

10U_0805_25V6

K

PQB1

5 S2

6 S2

7 S2
8 G2

PCB20
.1U_0402_16V7K

2 1

BATDRV_CHG

10

4

D1

D1

3

D1

2

D1

1

UG_CHG

G1

D2/S1

9

4.7UH_5.5A_20%_7X7X3_M

LX_CHG 1 2 CHG 1

1

2 1 SNUB_CHG 2

PLB1

EMI@PRB12

4.7_1206_5%

EMI@ PCB19

680P_0402_50V7

K

1
2
3

4

PCB9

2 1

0.01U_0402_50V7

K

+12.6V_BATT

4
3

PCB16

PCB15

2 1

PCB18

2 1 SRN_R

0.1U_0402_25V

6

2 1

10U_0805_25V6K

10U_0805_25V6K

+3VL

02_5% PRB19

2 1 SDA_CHG

2

0_0402_5% PRB18

@ 0_04

@

PCB23

PRB21

PCB22

2 1

0.22U_0402_16V7

K

66.5K_0402_1

4 4

L-->H
H-->L

VILIM = 20*ILIM*Rsr
ILIM = 3.3*100/(100+620)/20/0.02

A

Vin Dectector

Min. Typ

17.16V 17.63V

16.76V 17.22V

= 2.291 A

Max.

18.12V

17.70V

B

2 1

2 1

%

100P_0402_50V

8 J

@ PRB22

0_0402_5%

1 2

12

SecurityClassification

Issued Date

THIS SHEET O F EN GINEER IN G DR AW IN G IS T H E PR O PR IET ARY PR OPER T Y OF CO MPA L EL EC TRO NIC S, INC . AN D CON TAINS CONFIDENSSTiIzAeL
AND T R AD E SEC RET IN FOR MAT ION . T HIS SH EET MAY N OT BE T RAN SF ER ED FR O M TH E CU ST O DY OF T HE CO MPET EN T DIVISION OF R&D
DEPAR T MEN T EXC EPT AS AU T HO RIZ ED BY C OMPAL EL EC T RON IC S, INC . NEIT HER T HIS SH EET NO R THE IN FO R MAT IO N IT CO NT AIN S
MAY BE USED BY OR DISC LOS ED TO AN Y T H IRD PAR T Y W IT HO UT PR IO R WRIT TEN C ONSEN T OF COMPAL EL EC TRO NIC S, INC.

EC_SMB_CK1 <33,46>

EC_SMB_DA1 <33,46>

ADP_I <33,45>

PCB24

0.1U_0402_25V6

Close EC chip

2016/09/01 2019/09/01

Compal Secret Data

DecipheredDate

C

Title

Document Number

Date: Friday, January 05, 2018

Compal Electronics, Inc.

CHARGER

Rev

Sheet

D

47 of 59

v0.3

5

4

3

2

1

+19VB

D D

EMI@ PL304

5A_Z80_0805_2P

1 2

0.1U_0402_25V

@EMI@ PC303

+19VB_3V

6

2 1

2 1

PC305

2200P_0402_ 50V7

K

EMI@ PC304

10U_0805_25V6

K

+3VALW

12

PR304

100K_0402_5%

<9> SPOK

C C

+19VB

PR307
499K_0402_1%

1 2

+19VB

B B

<33,39> EC_ON

<33> MAINPWON

ENLDO_3V5V

1

PR309
499K_0402_1%

2

@ PR311

1

EMI@ PL303

5A_Z80_0805_2P

1 2

2.2K_0402_5%

1 2

0_0402_5%

2

PR301

1

PR313

1M_0402_1

2

2 Cell battery : Cin=10uF*2pcs
3 Cell ~ 4 Cell battery : Cin=10uF*1pcs

+19VB_5V

+19VB_5V

LX_5V 6

PC314

2 1

10U_0805_25V6

K

EMI@ PC316

5V_3V_EN

PC327

21

%

4.7U_0402_6.3V6

M

2 1

2 1

0.1U_0402_25V6

2200P_0402_ 50V7

K

@EMI@ PC317

1SPOK_5V

@ PR310

0_0402_5%

2

SPOK

ENLDO_3V5V

5V_3V_EN

2 1

LX_3V6

ENLDO_3V5V

5V_3V_EN

LX

7

GND

8

GND

9

PG

10

NC

PU301
SY8286BR AC_QFN20_3X3

3

IN

LX

7

GND

8

GND

9

PG

10

NC

EN112EN2

FF

11

13

3V_FB

2

1

4

3IN5

INININ

EN1

EN2

FF

OUT

11

12

13

14

15

2 1

1000P_0402_50V7K

5V_FB 1 2 5V_FB_1 1 2

BST_3V

1

2IN4IN5

IN

BS

20

LX

19

LX

18

GND

17

LDO

16

NC

21

GND

NC

OUT

3.3V LDO 150mA~300mA

14

15

PC312
1000P_0402_50V7K

1 2 3V_FB_1 1 2

BST_5V1 2 BST_5V_R 1 2

PU302
SY8288CRAC_QFN20_3X3

BS

20

LX

19

LX

18

GND

17 VCC_5V 1 2

VCC

16

NC

21

GND

LDO

+5VL

5V LDO 150mA~300mA

PC325

4.7U_0603_6.3V6

M

PC326

@ PR302

0_0402_5%

1 2 BST_3V_R 1 2

+3VLP

PC310

4.7U_0603_6.3V6M

2 1

PR305

1K_0402_1%

@ PR306

0_0402_5%

LX_5V

PC318

2.2U_0402_6.3V6M

PR312

1K_0402_1%

PC302

0.1U_0201_10V6K

LX_3V

PC313

0.1U_0201_10V6K

@EMI@

@EMI@

PR30

3

@EMI@

2 13V_S2 N 1

@EMI@

PC311

680P_0402_5 0V7K 4.7_1206_5%

PR308

4.7_1206_5%

2 1 5V_SN 2 1

PC324

680P_0402_50V7K

PL302

1.5UH_6A_20%_ 5X5X3_M

1 2

PL301

2.2UH_7.8A_20%_7X7X3_M

1 2

+3VALWP

2 1

2 1

PC306

22U_0603_6.3V6M

2 1

2 1

PC308

PC307

PC309

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

Fsw : 600K Hz

@PJ302

1

2

1 2

JUMP_43X118

@ PJ303

JUMP_43X39

1

1

2

2

+3VALW+3VALWP

+3VL+3VLP

+5VALWP

2 1

2 1

2 1

PC322

PC301

22U_0603_6.3V6M

22U_0603_6.3V6M

2 1

2 1

PC328

PC319

PC323

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

Fsw : 600K Hz

@PJ305

1

2

2

1

JUMP_43X118

+5VALW+5VALWP

A A

SecurityClassification

Issued Date

THIS SH E ET OF EN GIN E E RIN G D RA W IN G IS TH E PR OP RIE TA RY P RO P ER TY OF CO MP A L E L EC TR ON IC S , INC . AN D C ONTA INS CONFIDENTSSIAizL
AN D TR AD E S EC RE T IN FO RM A TIO N. THIS S HE E T MA Y NO T BE TR AN SF ER E D FR O M TH E C US TO DY OF TH E CO MP E TE NT DIV ISION OF R & D
DE P AR TM EN T EX C EP T A S A UTH O RIZ E D B Y C OM P AL E LE CTR O NIC S , IN C. NE ITHE R TH IS SH EE T N OR TH E IN F OR M ATI O N IT CONT AIN S

5

4

MA Y BE US ED BY OR DIS CL OS ED TO A N Y TH IR D PA RTY W ITH O UT PR IO R W RI TTE N C ON SE NT OF C OM P AL EL E CTR O NIC S , INC.

3

2016/09/01 2019/09/01

Compal SecretData

DecipheredDate

2

Title

e Document Number

Custom

Date:

Compal Electronics,Inc.

3VALW/5VALW

Friday, J an uar y 05, 2018

CSL50 LA-E791P

Sheet 48 of 59

1

v0.3

Rev

5

D D

EMI@ PLM2

5A_Z80_0805_2P

+19VB

1 2

+1.2VP

21

2 1

2 1

2 1

2 1

PCM8

PCM9

PCM10

C C

22U_0603_6.3V6M

+1.2VP

+0.6VSP

PCM11

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

@ PJM2

JUMP_43X118

1

2

1 2

@ PJM3

JUMP_43X39

1

1

2

PCM12

2

2 1

22U_0603_6.3V6M

+19VB_DDR

1UH_11A_20%_7X7X3_M

1 2LX_DDR

PCM13

22U_0603_6.3V6M

2 1

2200P_0402_50V7K

@EMI@ PCM1

PLM1

@EMI@ PRM3

4.7_1206_5%

@EMI@ PCM14

680P_0402_50V7K

+1.2V_VDDQ

+0.6V_0 .6VS

PCM2

21

10U_0805_25V6K

10

SNB_DDR

2 1 2 1

4

D1

D1

S2

5

4

PRM1

2.2_0603_5%

BST_DDR_R

PCM4

0.1U_0603_25V7K

21

1

3

2

D1

D1

G1

9

D2/S1

S2

S2

G2

6

7

8

+5VALW +1.2VP

PQM1
AONH363 34_DFN3X3A8-10

PRM4

5.1_0603_5%

1 2

@

PTPM1

1 2

PRM2

11.5K_0402_1%

1 2 CS_DDR13

1U_0402_6.3V6K

PCM16

1U_0402_6.3V6K

2 1

5.1_0603_5%

1 2

PWROK_DDR

+19VB_DDR

PCM7

1 2

VDD_DDR

PRM5

LG_DDR 15

VDDP_DDR

PG_+2.5V

<12,33,40> SYSON

<12,33,40> SUSP#

<6> SM_PG_CTRL

DL

14

CS

12

11

BST_DDR

UG_DDR

LX_DDR

PGND

VPP

VCC

PRM7

470K_0402_1%

1 2

@ PRM8

0_0402_5%

1 2

1 2

0_0402_5%

@PR M11

0_0402_5%

1 2

@ PRM12

0_0402_5%

1 2

3

16

17

LX

PGOOD

9

10

TON_DDR

@PRM10

0.1U_0402_10V7K

DH

TON

PCM17

@

@PC M18

18

20

19

VTT

BST

VLDOIN

VTTGND

VTTSNS

VTTREF

VDDQSNS

S5

S3

VDDQSET

6

8

7

FB_DDR

S5_DDR

S3_DDR

2 1

0.1U_0402_10V7K

2 1

+1.2VP

PUM1
G5616BRZ1U_TQFN20_3X 3

21

PAD

1

2

3

GND

4

5

1

2

VTTREF_DDR

6.04K_0402_1%

1 2

PRM9
10K_0402_1%

PRM6

PCM5

2 1

10U_0603_6.3V6M

Vout=0.75* (1+PRM6/PRM9)=1.2V

PCM6

21

10U_0603_6.3V6M

PCM15

0.033U_0402_16V7K

2 1

+1.2VP

2

1

+0.6VSP

B B

@ PJ250 2

JUMP_43X39

1

PC2501

22U_0603_ 6.3V6M

2

2

Enable 1.2V

EN_2.5V

PR250 3

4

2 1

12

1 2

PR2504

100K_0402_5%

PC2502

21

@

PG_+2.5V

.1U_0402_16V7K

@ PJ250 1

@ PR2501

0_0402_5%

1

@ PR2502

0_0402_5%

1 2

2

JUMP_43X39

1

1

+3VALW

1M_0402_1%

+3VALW

<9,12,33,40> PM_SLP_S4#

A A

5

2016.12.27

SYSON

PU250 1

IN_2.5V LX_2.5V

4
5
6 1

VIN

LX

PG

GND

VFB EN

G5719CTB1U_SOT23-6

3
2

PL2501

1UH_MHCD252012A-1R0M-A8S_3A_20%

1 2

@EMI@ PR2505

4.7_0402_5%

2 1

SNB_2.5V

@EMI@ PC2503

680P_0402_50V7K

2 1

3

PR2506

32.4K_0402_1%

FB_2.5V

PRM250 7

10K_0402_1%

Securi ty Classifica tion

Issued Date

THI S SH EE T O F E NGI NE ERI NG DRAWIIING I S T HE P RO PR IE TARY PR OP E RT Y O F CO MPAL ELECTR ONIIICS, INC... AND CONTAI NS CONFIDENTSIiAzL
AND T RA DE SE CR ET INFORMATIO N... THI S S HE ET MA Y NOT BE T R ANS FE R ED F RO M T HE CUS TOD Y OF THE C OM P ET ENT DIIIVISION OF R&D
DEP ARTME NT E XC EP T AS AUTHO RI ZE D BY C OMP AL E LECTRONIC S,,, I NC . NEIITHE R T HI S SH EE T N OR T HE I NF OR MAT IO N I T CO NTAI NS
MA Y BE USE D BY OR DI SC LO SED TO AN YTHI R D PA RT Y W I TH OU T P RI OR W RITTE N C ONS ENT OF C OMP AL EL EC TRO NIC S, IIINC.

+2.5VP +2.5V

2 1

PC2504

21

PC2505

68P_0402_50V8J

2 1

12

22U_0603_6.3V6M

2016/09/01 Deciphered Date

2

1 2

+2.5VP

2 1

PC2506

22U_0603_6.3V6M

Vout=0.6V *(1+PR2506/PR2507)=2.544V
Imax= 2A, Ipeak= 3A

Compal Secret Data

2

2019/09/01

e DocumentttNumber

Custom

Compal Electronics, Inc.

Title

1.2VP/0.6VSP/2.5V

Friday,,, Januar y 05 , 2018

Rev

Sheettt 49of 59Date:::

1

v0.3

A

B

C

D

2

+1.0V_PRIMP

22U_0603_6.3V6

M

+1.0V_PRIM

+1.0V_PRIMP

1 1

<33> +1.0VS_PG

PR1005

100K_0402_1%

EMI@ PL1002

5A_Z80_0805_2P

2

1 2

1

2 1

K PC1001

10U_0805_25V6

2200P_0402_50V7K

+19VB

2 2

<51> +1.8V_PG

PR1001
0_0402_5%

1

EMI@ PC1003

EN_1V

+19VB_1V

2 1

2 1

0.1U_0402_25V

6 @EMI@ PC1004

ILMT_1V 13

+3VALW

PR1002

2

1M_0402_1

%

N :H>0.8V ; L<0.4V

N pin don't floating
f have pull down resisto r at HW s ide,

lease delete PR601.

3 3

2 1

+3VALW

K @

PC1005

0.1U_0402_25V7

The current limit is se t to 6A, 9 A or 12A whe n this pin
is pull low, floating o r pull high.

12

1

2

@ PR1003

0_0402_5%

@ PR1004

0_0402_5%

18
11

15

12

PC1006
1U_0402_6.3V6K

2

3 IN

4 IN

5 IN
7

GND

8

PU1001

IN

GND
GND

EN

ILMT

BYP

SY8286RAC_QFN20_3X3

VCC

PAD

9

PG

1

BS

LX_1V

6

LX

19

LX

20

LX

FB_1V

14

FB

VCC_1V

17

10

NC

12

NC

16

NC

21

2 1

@ PR1006

0_0402_5%

BST_1V 1 2 BST_1V_R 1 2

2 1

PC1008

2.2U_0402_6.3V6M

+3VALW

PC1007

0.1U_0402_25V6

@EMI@

PR1007

1

4.7_1206_5% 680P_0402_50V7K

PL1001
1UH_6.6A_20%_5X5X3_M

1 2

@EMI@

PC1009

2SNB_1V 1 2

PR1008

20K_0402_1%

FB=0.6V

PR1009
30K_0402_1%

2 1

2 1

1 2

12

PC1010

330P_0402_50V7

12

PR1010

1K_0402_1

2 1

PC1011

K

22U_0603_6.3V6

M

%

@ PJ1002

JUMP_43X118

1

1 2

2 1

2 1

PC1012

PC1013

22U_0603_6.3V6

M

22U_0603_6.3V6

M

VGA@ PC1014

4 4

SecurityClassification

Issued Date

TH IS SH E ET O F EN G IN EER IN G DR AWIN G IS THE P R OPR IET A RY PR O P ER T Y O F C O MP A L EL EC T RON IC S, INC. A N D C O NT AIN S CONFIDENTSI
AN D T R AD E S E CR E T IN FO RMAT IO N . TH IS S H EE T MA Y NO T BE T R AN S FE R ED F R OM T H E CU S T O DY OF T H E C OM P ET E NT DIVISION OF R& D
DE P AR T ME N T E XCE P T A S AU T HO R IZ E D BY C OM P AL EL EC TR O NIC S, IN C. NE IT H ER T H IS S H EE T NO R TH E IN F OR MAT IO N IT C ONT AIN S

A

B

MA Y BE U SE D BY OR DISC LO SED TO A NY TH IR D P AR T Y W IT H O UT PR IO R W R IT T EN C ON S ENT OF C O MP A L EL EC TR O NIC S, INC .

2016/09/01 2019/09/01

Compal Secret Data

Deciphered Date

C

Title

izzeLDocument Number

Custom

1.0V_PRIM

D

Rev

Sheet 50 of 59Date: Friday, January 05, 2018

v0.3

5

D D

@PJ1801

JUMP_43X39

+3VALW

C C

<33,40>PCH_PWR_EN

+3V_PRIM

<50>+1.8V_PG

1 2 EN_1.8V

@PR1804

0_0402_5%

2016.11.23

2

1

1

2

2 1

PC1801

22U_0603_6.3V6M

1 2

1 2

PR1801
100K_0402_5%

PR1805

2 1

1M_0402_1

%

4

PU1801

IN_1.8V LX_1.8V

4

VIN

5

PG

6

VFB EN

G5719CTB1U_SOT23-6

@PC180

5

.1U_0402_16V7K

GND

3

LX

2

1

3 2

PL1801

1UH_MHCD252012A-1R0M-A8S_3A_20%

1 2

1

@EMI@

PR1802

4.7_0603_5%

2

SNUB_1.8V

@EMI@

PC1806

680P_0402_50V7K

2 1

20K_0402_1%

FB_1.8V

10K_0402_1%

PR1803

PR1806

1

21

PC1802

2

1

2

68P_0402_50V8

@PJ1802

1 2

JUMP_43X79

2

+1.8VSP +1.8V_PRIM

1

+1.8VSP

2 1

2 1

J

PC1804

PC1803

22U_0603_6.3V6

22U_0603_6.3V6

M

M

Vout=0.6V*(1+PR1803/PR1806)=1.8V

1

Imax= 2A, Ipeak= 3A

B B

A A

Security Classification

Issued Date

THIS S HE E T OF ENG INE ERI NG DR A W ING IS THE PR O PRI ETARY P R O PE RTY O F CO M PA L ELECT RO NICS, INC. AND C ONT A I NS CONFIDENTSiAzL
AN D T R ADE SE C RE T I N FOR M ATI O N. TH IS SHE E T M AY NOT BE T RAN SFE R ED F R OM T HE C UST O DY OF THE CO M PET ENT DIVISIO N OF R& D
DE PAR T MEN T E XC E PT AS A UTH O R IZ E D BY C OM P AL ELE CT RONICS, IN C. NEIT HER T HIS S HEE T NO R THE IN F OR M ATI O N IT CON T AIN S
MA Y BE US E D BY OR D ISC LOS ED TO A NY T HIR D PAR T Y W I T HOU T P RIO R W R I TTEN C ON S ENT OF CO M PAL EL ECT R ONI CS, INC.

5

4

2016/09/01 2019/09/01

3 2

Compal Secret Data

DecipheredDate

Title

e DocumentNumber

B

Date:

Compal Electronics, Inc.

1.8V_PRIM

CSL50 LA-E791P

Sheet 51 of

1

Rev

v0.3

59

1

2

3

4

5

A A

B B

C C

RT3602_VREF

953_0402_1%

PRZ3

PRZ2

1 2 1

PRZ6

PRZ5

2

%

16.2K_0402_

1

PRZ17

2

464_0402_1%

PRZ28

2

536_0402_1%

<14>VCCCORE_SENSE

Vref=0.6V

PCZ3

0.1U_0402_50V7K

2 1

PRZ

6.8K_0402_

1

+VCC_SA

PRZ1
100_0402_1%

VCCSA_SENSE_R 1 2

PRZ11

2 1 2 1

11K_0402_1% 1.78K_0402_1%

2 1 2 1

4 10_0402_1%

%

RT3602_SET1
RT3602_SET2
RT3602_SET3

VR_PSYS

PRZ20

PRZ19

PRZ18

@

2 1

1

5.23K_0402_1%

PRZ29

K_0402_1

2.21

2

1

2

1

1

10K_0402_1

%

1.1K_0402_1%

PRZ30

1

2

2.1K_0402_1%

%

1

PRZ31

2

1

+VCC_CORE

@ PCZ7

0.1U_0402_10V6K

2

0_0402_5%

1

PRZ41

100_0402_1%

1 2

PRZ47
0_0402_5%

1 2

2

VSEN_CORE

Ra Rb/Rc

U22

N/A

U42

PRZ43
10K_0402_1%

1 2

1 2

270P_0402_50V7K
PCZ11

Stuff

N/AStuff

<12> VCCSA_SENSE

RT3602_VREF

<53>AVCORE1

<53>AVCORE2

+5VALW

close to chock

1 2

PCZ1282P_0402_50V8J

RT3602_VREF

PRZ6

PRZ68

PRZ67 PRZ63

2 1 2 1

2 1 2 1

4 374_0402_1%

8.25K_0402_1%

115_0402_1% 8.25K_0402_1%

1 2

PRZ15

1 2

0_0402_5%

PHZ1

100K_0402_1%_B25/50 4250K

1 2 PHZ1_R1

PRZ45

52.3K_0402_1%

1 2

Rb

1 2

U22@ PRZ105 10K_0402_1%

<53> AISPCORE1

TSEN_CORE_R

TSEN_GT_R

1

2IMON_CORE_R

PRZ33

38.3K_0402_1%

PCZ13

0.1U_0402_50V7K

1 2
U42@

PCZ16 0.1U_0402_50V7K

+5VALW

TSEN_CORE_R 1 2 1

PRZ8
10K_0402_1%

PCZ5 390P_0402_50V7K

PRZ26

42.2K_0402_1%

2

@ PCZ9

0.1U_0402_10V6K

1 2

U42@ PRZ106

1 2ISEN1N_MAIN

0_0402_5%

<53>AISPCORE2

U22@ PRZ10410K_0402_1%

PRZ51 PRZ52
110K_0402_1% 1.65K_0402_1%

PHZ2

1 2

100K_0402_1%_B25/50 4250K

1 2

12

1 2

PRZ35

14.7K_0402_1%

Ra

1 Rc2

PCZ668P_0402_50V8J

FB_SA

RT3602_SET2 5
RT3602_SET3 6

TSEN_CORE

PRZ53

2.2_0805_1%

2

+19VB_CPU

PRZ10

49.9K_0402_1%

1 2

1 2

0_0402_5%

IMON_COR1E

RT3602_SET12

FB_CORE 3

COMP_CORE4

RT3602_V1IN2

2

+5VALW

<14>

PRZ95

IMON_MAIN
SET1

FB_MAIN
COMP_MAIN
SET2

SET3

7

ISEN1N_MAIN

8

ISEN2N_MAIN

9

ISEN2P_MAIN

10

ISEN1P_MAIN

11

TSEN_MAIN

VIN

2 1
1

PCZ19

0.22U_0402_25V

A K

PRZ65

10_0402_1%

1 2

4.7U_0603_10V6K

<53>AVCCSA

VSSSA_SENSE

VSSCORE_SENSE

1

1

100_0402_1

% PRZ94

2

PRZ21

2

1

RGND_MAIN

VSEN_CO

49484746454443424140393837

N

GND

RGND_MAI

V

C

C NC NC

141516

RT3602_VCC 13

PCZ23

2 1

2
2
Z
C

21

P

PRZ24

2 1

0_0402_5%

2 1

2

PRZ22100_0402_1%

FB_SA

RGND_S

A

COMP_S

R E

VR_PSYS

I

N

PS

VSEN_MA

RGND_SA

Y S FB_SA

PWM1_MA

I N

17

192021

DRVEN_SET 18

PWM_COR

E 1

PWM_COR

E 2

@ PCZ4

0.47U_0402_25V6K

12

V6K

.3

2 1

6
_

PRZ13

2

64.9K_0402_1%

0.47U_040

8<12>

RT3602_VREF 3.9_0402_1%

IMON_SA

RT3602_EN

A

PUZ1
NCP81218MNTXG_QFN48_6X6

E T

IMON_SA

ISENN_SA

ISENP_SA

COMP_SA

PWM_SA

VREF06/PS

DRVEN

VCLK

ALERT#

VDIO

VR_HOT#

IMON_AUXI
ISENP_AUXI
ISENN_AUXI

VSEN_AUXI
COMP_AUXI
RGND_AUXI

PWM2_MA

I N

DRVEN_SET NC NCNC

22

FB_GT24

TSEN_GT 23

1U_0603_25V6K

<53>

<53>

<53>

PWM_GT

1

PRZ66
110K_0402_1%

AISPVCCSA <53>

PRZ23
10K_0402_5%

1 2

PRZ25
0_0402_5%

1 2

EN

36

VR_READY

35

34 1

33 PRZ98 49.9_0402_1%
32
31

30
29
28

VSEN_GT

27

26

25

PWM_AUXI

TSEN_AU

X I

PCZ230

2 1 RGND_AUXI

RT3602_VREF

2

1

PRZ14
453_0402_1%

+3VS

VR_PWRGD<33>

VR_ON<33,40>

PRZ36

45.3_0402_1%

PWM_SA<53>
DRVEN <53>

2

PRZ991 210_0402_1%

IMON_GT

COMP_GT

PCZ18

0.1U_0402_50V7K

FB_AUXI

PRZ107

1

2

0_0402_5%

PRZ93
0_0201_5%

2 1

VSSGT_SENSE <14>

+1.0V_VCCST

2

1

2

100_0402_1%

PRZ38

PR1Z100100_20402_1%

@PCZ15 0.47U_0402_25V6K

1 2

AISP1 <53>
AVGT1<53>

1 2

PCZ20 82P_0402_50V8J

PCZ22

Z39

1

2

1

75_0402_1%

PR

PRZ48

28.7K_0402_1% PRZ49866_0402_1%

1 2 1 2

PRZ54

29.4K_0402_1%

1 2

1 2

2 1

7

0.1U_0402_25V

6

VR_SVID_CLK <14>
VR_ALERT#<14>
VR_SVID_DATA <14>

VR_HOT#<33>

RT3602_VREF

PRZ50
0_0201_5%

VSEN_GT

1 2

PRZ56
10K_0402_1%

1 2

1 2

PCZ21

270P_0402_50V7K

FB_GT

PRZ59
100_0402_1%

1 2

+VCC_GT

VCCGT_SENSE <14>

PRZ71

PRZ70

2

1

2

549K_0402_1%

1

%

PRZ73

11.5K_0402_

D D

1

1

182K_0402_1%

PRZ74

1

2

2 1

4.02K_0402_1%

2

+5VALW

1

DRVEN_SET

1 2

2

@ PRZ72

0_0402_5%

PRZ75

0_0402_5%

3

2 1

1 2

PRZ69

PHZ3

1.65K_0402_1%

100K_0402_1%_B25/50

4250K

TSEN_GT_R 2

Security Classification

Issued Date

THIS SHE ET OF ENGINEE RING DRAW ING IS THE PROPR IETARY PROP ERTY OF COM PAL E LECTRONICS , INC. AND CON TAINS CONFIDENTSSIAizL
AND TRA DE SEC RET INF ORMATI ON. THIS S HEET M A Y NOT B E TRANSFE RED FROM THE CU STODY OF THE CO MPETENT DIVISION OF R& D
DEPAR TMENT EXC EPT AS AU THORIZED B Y COMPA L ELE CTRONICS, IN C. NEITHE R THIS SHE ET NOR THE INFORM ATION IT C ONTAINS M A Y
BE USED B Y OR D ISCLOSED TO AN Y THIRD PARTY W ITHOUT PR IOR W RITTEN CONSENT OF CO MPAL ELECTRONIC S, INC .

2016/09/01 2019/09/01

Compal SecretData

Deciphered Date

4

Compal Electronics,Inc.

Title

CPU_CORE

e Document Number

CSL50 LA-E791P

Date: Friday, January05, 2018

Rev

52

Sheet

5

v0.3

59

of

1

PRZ76

CORE1_BST

<52> PWM_CORE1

+5VALW

<52> DRVEN

1 PRZ802 VCC_CORE1 8

A A

1_0402_5%

2 1

PCZ40

2.2U_0402_16V6K

2.2_0603_5%

1 2

PUZ2

4

3

BOOT UGATE

5

2

PWM PHASE

1

EN PGND

VCC LGATE

9

GND

RT9610CGQW_WDFN8_2X2

CORE1_BST_R

PCZ28

0.1U_0402_25V6

2 1

CORE1_UG
CORE1_LX

6

7

CORE1_LG

1

0_0603_5%

PRZ78

2 CORE1_UG_R 4

2

53

PQZ1

2

1

AON6380_DFN5X6-8-5

PQZ2

5

4.7_1206_5%

@EMI@PRZ82

4

321

AON6314_N_DFN56-8-5

2 1CORE1_SNUB 21

@EMI@PCZ44

680P_0402_50V7K

2 1

EMI@ PCZ30

@EMI@PCZ29

0.1U_0402_25V6

1 2 1 2

AISPCORE1_R

PRZ85 PRZ102

2.1K_0603_1%2.1K_0 603_1%

PCZ31

2 1

2200P_0402_50V7K

Rdc=1.19 mohm

PCZ32

2 1

10U_0805_25V6K

10U_0805_25V6K

PLZ1

1 4
2 3

0.24UH_22A_+-20%_7X7X3_M

2 1

PCZ42

0.1U_0402_25V6

1 2

PRZ88

4.22K_0402_1%

1 2

+19VB_CPU

1

+

2

U42@ PCZ26

+VCC_CORE

1

+

2

PCZ229

100U_25V_NC_6.3X6

100U_25V_NC_6.3X6

EMI@ PLZ3

5A_Z80_0805_2P

1 2

U22@ PCZ26

68U_25V_M_R0.36

AVCORE1<52>

AISPCORE1<52>

3

+19VB

<52> PWM_CORE2

+5VALW

1 2 VCC_CORE2 8

U42@PRZ81

1_0402_5%

2 1

CORE2_BST

DRVEN1

U42@

PCZ41

2.2U_0402_16V6K

1 2

PUZ3U42@

4

3

BOOT UGATE

5

PWM PHASE

EN PGND

VCC LGATE

9

GND

RT9610CGQW_WDFN8_2X2

U42@PRZ77

2.2_0603_5%

2
6
7

CORE2_UG
CORE2_LX

CORE2_BST_R

2 1

CORE2_LG

U42@

PCZ35

0.1U_0402_25V6

4

1

U42@PRZ79

0_0603_5%

2 CORE2_UG_R 4

U42@

PQZ4
AON6314_N_DFN56-8-5

5

+19VB_CPU

5

321

5

4

321

U42@

PQZ3
AON6380_DFN5X6-8-5

4.7_1206_5%

@EMIU42@ PRZ84

2 1CORE2_SNUB 2 1

@EMIU42@PCZ45

680P_0402_50V7K

2 1

2 1

2 1

10U_0603_25V6M

U42@ PCZ37

0.1U_0402_25V6

EMIU42@PCZ36

U42@ PCZ34

EMIU42@ PCZ33

2200P_0402_50V7K

Rdc=1.19 mohm

U42@ PLZ2
1 4

2 3

0.24UH_22A_+-20%_7X7X3_M

U42@ PRZ87 U42@ PRZ103 U42@PCZ43

2.1K_0603_1% 2.1K_0603_1%0.1 U_0402_25V6

AISPCORE2_R

1 2 1 2 1 2

2 1

10U_0603_25V6M

+VCC_CORE

U42@ PRZ90

4.22K_0402_1%

1 2

AVCORE2<52>

AISPCORE2<52>

+19VB_CPU

PRG2

PUG1

4

BOOT UGATE

5

PWM PHASE
EN

8

VCC LGATE

RT9610CGQW_WDFN8_2X2

SA_BST

DRVEN1

PCA1

2.2U_0402_16V6K

2.2_0603_5%

1 2

3

6

PGND

7

9

GND

1 2

PUA1

4

3

BOOT UGATE

5

2

PWM PHASE

EN PGND

8

7

VCC LGATE

GND

RT9610CGQW_WDFN8_2X2

2

PRA2

2.2_0603_5%

9

GT_BST_R

PCG2

0.1U_0402_25V6

2 1

GT_UG
GT_LX

SA_BST_R

SA_UG
SA_LX

6

GT_LG

2 1

SA_LG

1 2 GT_UG_R

PRG3

2.2_0603_5%

PCA3

0.1U_0402_25V6

53

PQG1

EMI@ PCG3

2

1

5

D1 2D1 3D1

AON6380_DFN5X6-8-5

PQG2

AON6314_N_DFN56-8-5

EMI@ PCG9

4

10

D1

S

0.1U_0402_25V6

1

EMI@PRG4

4.7_1206_5%

2

21GT_SNUB

330P_0402_50V7K

PQA1
AONH36334_DFN3X3A8-10

2

S

2

4

4

321

1

9

D2/S1

G2 G1

7 S6 25

8

1 PRG1 2 VCC_GT

1_0402_5%

1

2 1

2 VCC_SA

2 1

GT_BST

DRVEN 1

PCG1

2.2U_0402_16V6K

B B

<52> PWM_GT

+5VALW

C C

<52> PWM_SA

+5VALW

PRA1 1_0402_5%

D D

2 1

2 1

EMI@ PCG4

2200P_0402_50V7K

AISP1_R

PCA5

PCA4

2 1

10U_0805_25V6K

2 1 SA_SNUB 21

@EMI@ PCA8 @EMI@ PRA4

680P_0402_50V7K 4.7_1206_5%

PCG6

PCG5

PCG11

2 1

2 1

10U_0805_25V6K

10U_0805_25V6K

PRG6 PRG9

1.58K_0603_1% 1.58K_0603_1%

1 2 1 2

2 1

2 1

10U_0805_25V6K

@EMI@PCA6

EMI@ PCA2

0.1U_0402_25V6

1 2 1 2

AISPVCCSA_R

PRA6 PRA9
953_0603_1%953_0603_1%

PCG10

2 1

2 1

EMI@ PCG12

10U_0805_25V6K

10U_0805_25V6K

Rdc=1.19 mohm

PLG1

1 4
2 3

0.24UH_22A_20%_7X7X3_M

PRG7

3K_0402_1%

1 2

+19VB_CPU

2 1

2200P_0402_50V7K

2 1

0.1U_0402_25V6

PCG8

0.1U_0402_25V6

1 2

PRG8
10K_0402_1%

1 2

1 2

AVGT1_R

PHG1

10K_0402_1%_B25/503370K

Rdc=6.2 mohm

PLA1

1 4
2 3

0.47UH_NA12.2A_20%

PRA7 PRA8

866_0402_1% 1K_0402_1%

1 2 1 2

1K_0402_5%_TSM0B102J3652RE

+VCC_GT

PCA7

0.1U_0402_25V6

1 2

1 2

AVCCSA_R

PHA1

AVGT1 <52>

AISP1<52 >

+VCC_SA

AVCCSA <52>

AISPVCCSA<52>

VCC_CO RE

FSW=500kHz

Choke= 0.24uH
DCR=1.19 mohm +/- 5%

U22
LL=2.4 mohm
TDC=21 A
ICCMAX =32A
OCP=40 A

U42
LL=2.4 mohm
TDC=42 A
ICCMAX =64A
OCP=70 A

VCC_GT

FSW=500kHz

Choke= 0.24uH
DCR=1.19 mohm +/- 5%

U22
LL=3.1 mohm
TDC=18 A
ICCMAX =31A
OCP=39 A

U42
LL=3.1 mohm
TDC=12 A
ICCMAX =28A
OCP=39 A

VCC_SA

FSW=600kHz

DCR=6.2 mohm +/- 5%

U22
LL=10.3 mohm
TDC=4A
ICCMAX =4.5A
OCP=9. 5A

U42
LL=10.3 mohm
TDC=
ICCMAX =5A
OCP=9. 5A

Secur ityClas sification Compal Sec ret Data

Issued Date

THIS S HEE T OF ENGI NE ER I NG DRA WING IS THE PROP RI E TAR Y PROP ER TY OF C OMPA L ELE CTR ONI CS ,I NC. A ND C ONTA INS CONFIDENTSSIAizL
AND TRA D E SE CRE T INF ORMA TIO N. THI S SHE ET MA Y NOT BE TRA NS FER E DF ROM THE C US TOD Y OF THE COM PE TEN T DI VIS ION OF R&D
DEP ART MEN T EX CEP T AS AUT HOR IZE D BY C OMPA L ELE CTR ONI CS , INC. NEI THER THI S SHE ET NOR THE INF ORMA TIO N IT CONT AI NS MA YBE

1

2

3

USE D BY OR DI SCL OSED TO ANY THIRD PART Y W ITHOU T PRI OR W RITTE N C ONS EN T OF C OMP AL EL ECT RON ICS ,I NC.

2016/09/01

Deciphered Date

4

2019/09/01

Title

e Document Number

Date: Friday, January 05,2018

Com pal Electronics, Inc.

CPU Power stage

CSL50 LA-E791 P

5

Rev

53 of59

Sheet

v0.3

5

1

2

M

PCZ83

22U_0603_6.3V6

M

VCC_CORE：
U22
390uF*1
22uF*18

1uF*35

U42
390uF*2
22uF*22
1uF*35

1

1

PCZ84

2

2

@ PCZ97

22U_0603_6.3V6

M

1

2

@ PCZ98

22U_0603_6.3V6

M

+VCC_CORE +VCC_GT

1

+

PCZ68

D D

2

1

1

PCZ78

2

2

@ PCZ79

22U_0603_6.3V6

22U_0603_6.3V6

M

2016.12.29

1

+

2

330U_2V_M

U42@PCZ215

390U_2.5V_ESR10M_6.3X

6

1

2

@ PCZ80

M

1

1

M

PCZ82

PCZ81

2

2

22U_0603_6.3V6

22U_0603_6.3V6

22U_0603_6.3V6

M

4

VCC_GT：
U22 & U42
390uF*1
22uF*33

1uF*13

1

+

PCZ69

2

1

1

PCZ99

2

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

2

1

PCZ72

PCZ71

PCZ70

2

2

22U_0603_6.3V6

M

22U_0603_6.3V6M 390U_2.5V_ESR10M_6.3X6

1

1

PCZ74

PCZ73

2

2

22U_0603_6.3V6

M

22U_0603_6.3V6

M

3 2 1

VCC_SA：
U22 & U42
22uF*9
1uF*7

+VCC_SA

1

PCZ75

2

22U_0603_6.3V6

M

1

1

PCZ77

PCZ76

2

2

@

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

1

PCZ86

PCZ85

2

2

22U_0603_6.3V6

M

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

PCZ87

2

1

1

PCZ88

2

22U_0603_6.3V6

M

1

PCZ89

PCZ90

2

2

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

1

PCZ91

PCZ119

2

2

22U_0603_6.3V6

M

22U_0603_6.3V6

M

22U_0603_6.3V6

1

1

1

PCZ93

PCZ94

2

2

22U_0603_6.3V6

M

M

1

PCZ96

PCZ95

2

2

@

22U_0603_6.3V6

M

22U_0603_6.3V6

22U_0603_6.3V6

M

M

1

1

PCZ100

2

C C

1

PCZ147

2

2 1

PCZ167

2 1

B B

PCZ187

2 1

PCZ200

1

PCZ101

PCZ102

2

2

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

1

PCZ148

PCZ150

2

2

22U_0603_6.3V6

M

22U_0603_6.3V6

M

2 1

PCZ168

1U_0201_6.3V6

M

1U_0201_6.3V6

M

2 1

PCZ188

1U_0201_6.3V6

M

1U_0201_6.3V6

M

2 1

PCZ201

1U_0201_6.3V6

M

1U_0201_6.3V6

M

1

1

PCZ104

PCZ103

2

2

22U_0603_6.3V6

M

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

1

2

22U_0603_6.3V6

M

2 1

PCZ169

1U_0201_6.3V6

2 1

PCZ189

1U_0201_6.3V6

2 1

PCZ202

1U_0201_6.3V6

121

PCZ155

PCZ154

22U_0603_6.3V6

2 1

PCZ170

1U_0201_6.3V6

M

2 1

PCZ190

1U_0201_6.3V6

M

2 1

PCZ203

1U_0201_6.3V6

M

PCZ127

M

2 1

PCZ172

M

2016.11.21

2 1

PCZ192

M

2 1

PCZ205

M

PCZ129

2

22U_0603_6.3V6

M

22U_0603_6.3V6

M

M

2 1

2 1

2 1

PCZ173

2 1

PCZ193

2016.11.21

2 1

PCZ206

PCZ174

1U_0201_6.3V6

M

1U_0201_6.3V6

2 1

PCZ194

1U_0201_6.3V6

M

1U_0201_6.3V6

2 1

PCZ207

1U_0201_6.3V6

M

1U_0402_6.3V6

1U_0201_6.3V6

1U_0402_6.3V6

K

M

1U_0201_6.3V6

M

2016.11.21

2 1

M

2 1

K

2 1

PCZ175

PCZ176

1U_0201_6.3V6

M

1U_0201_6.3V6

M

2 1

PCZ195

PCZ196

1U_0402_6.3V6

K

1U_0201_6.3V6

M

2 1

PCZ208

PCZ209

1U_0201_6.3V6

M

1U_0201_6.3V6

M

2

22U_0603_6.3V6

M

2 1

PCZ171

M

1U_0201_6.3V6

2 1

PCZ191

1U_0201_6.3V6

M

2 1

PCZ204

M

1U_0201_6.3V6

1

PCZ109

2

1

PCZ131

2

1

PCZ157

2

2 1

PCZ177

2 1

PCZ197

1

2

22U_0603_6.3V6

M

1

2

22U_0603_6.3V6

M

1

2

22U_0603_6.3V6

M

2 1

1U_0402_6.3V6

K

2016.11.21

2 1

1U_0201_6.3V6

M

1

1

1

PCZ111

PCZ110

22U_0603_6.3V6

PCZ132

22U_0603_6.3V6

PCZ158

22U_0603_6.3V6

PCZ178

1U_0201_6.3V6

PCZ198

1U_0201_6.3V6

PCZ112

2

22U_0603_6.3V6

M

1

PCZ134

2

M

22U_0603_6.3V6

1

PCZ159

2

M

22U_0603_6.3V6

2 1

PCZ179

1U_0201_6.3V6

M

2 1

PCZ199

1U_0201_6.3V6

M

PCZ113

2

2

M

22U_0603_6.3V6

M

1

1

PCZ136

PCZ135

2 2

22U_0603_6.3V6

M

M

2016.11.10

1

1

PCZ160

2

2

22U_0603_6.3V6

M

M

U42@ PCZ161

2 1

2 1

PCZ180

PCZ181

1U_0201_6.3V6

M

M

BOM option

M

by JU22(for GT) and JU42A (for IA)

1

1

PCZ114

2

22U_0603_6.3V6

M

1

PCZ137

2

22U_0603_6.3V6

M

1

2

22U_0603_6.3V6

M

U42@ PCZ162

2 1

1U_0201_6.3V6

M

1

1

PCZ115

PCZ116

2

@

22U_0603_6.3V6

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

PCZ163

2

22U_0603_6.3V6

22U_0603_6.3V6

M

2 1

PCZ182

1U_0201_6.3V6

M

PCZ117

2

2

M

22U_0603_6.3V6

M

22U_0603_6.3V6

M

2016.11.21

1

1

PCZ164

2

M

PCZ184

PCZ183

1U_0201_6.3V6

M

1

PCZ166

PCZ165

2

2

22U_0603_6.3V6

M

22U_0603_6.3V6

M

22U_0603_6.3V6

M

2 1

2 1

2 1

1U_0201_6.3V6

PCZ186

PCZ185

1U_0201_6.3V6

M

1U_0201_6.3V6

M

M

2 1

2 1

PCZ140

PCZ141

1U_0402_6.3V6

K

2 1

2 1

PCZ142

PCZ143

1U_0201_6.3V6

M

1U_0201_6.3V6

M

2 1

2 1

PCZ144

1U_0201_6.3V6

1U_0201_6.3V6

M

2 1

PCZ145

M

PCZ146

1U_0201_6.3V6

M

1U_0201_6.3V6

M

U42@

+VCC_GT_VR +VCC_GTX_VR

1

2 1

2 1

PCZ210

1U_0201_6.3V6

A A

2 1

PCZ211

M

1U_0201_6.3V6

M

2 1

2 1

PCZ214

PCZ213

PCZ212

1U_0201_6.3V6

M

1U_0201_6.3V6

M

1U_0201_6.3V6

M

1

PCZ130

2

PCZ133

2

22U_0603_6.3V6

M

22U_0603_6.3V6

M

SecurityClassification

IssuedDate

THIS SHEE T OF ENGINEERING DR AW ING IS T HE PROP RIET ARY PROPERT Y O F CO MPAL ELECT RON ICS, INC. AN D CONTAINS CONFIDENTSSIAizL
AND T RADE SECR ET INF ORMA T ION. TH IS SHEET MAY NOT BE T RANSFER ED FRO M T HE CUST ODY OF T HE COMPET ENT DIVISION OF R& D
DEPA RT MENT EXCEPT AS AUT H ORIZ ED BY CO MPAL EL ECT RON ICS, IN C. NEIT HER THIS SHEET N OR T HE INFO RMAT ION IT CONTAIN S MAY

5

4

BE USE D BY O R DISCLOSED T O AN Y T HIRD PAR T Y W IT HOUT PRIO R W RIT TEN CONSENT OF COMPAL ELECT RONICS, INC.

3 2

2016/09/01

1

2

22U_0603_6.3V6

M

U42@ PCZ149

Compal SecretData

DecipheredDate

1

2

22U_0603_6.3V6

M

U42@ PCZ152

Compal Electronics, Inc.

2019/09/01

Title

PROCESSORDECOUPLING

e Document Number

CSL50 LA-E791P

Date: Friday, January 05, 2018

Sheet of

1

Rev

v0.3

5954