Compal LA-E541P Schematics

1 1

Compal Confidential

2 2

DIS M/B Schematics Document

Intel KabyLake U/KabyLake R Processor with DDR4

N16S-GTR(940) (23x23mm) N16V-GMR1(920) (23x23mm)

3 3

2017-06-05

LA-E541P

DIUYA/YB/SA/SB/SD (KBL-R)

REV

FAB: JB501

：

2.A

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

Compal Electronics, Inc.

Cover Page

LA-E541P

2.A

1 51Wednesday, June 21, 2 017

2.A

1 1

nVIDIA N16V-GMR1 / N16S-GTR

VRAM(GDDR5)*2 2GB

N16V-GMR1 (Cruze) N16S-GTR (Alpine/Cruze)

eDP Panel

HDMI Conn.

PCIe x4

eDP x1 4 Lanes (Alpine) 2 Lanes (Cruze)

DDI

Intel KBL-U 15W/28W

Memory Bus

DDR4 2133MHz (1.2V)

( 2400 MHz )

USB3.0 x3

1356pin BGA

SD Card Connector

2 2

Wireless LAN (WIFI + BT combo) NGFF Half

Card Reader Realtek RTS5220-GR

I/O Board

PCIE SSD (2242/2280) M.2 NGFF

SPI ROM (8MB) W25Q64FVSSIQ

Touch Pad

USB2.0 x6

PCIe x6

SPI

I2C x1

REV：2.A

FAB: JB501

I2C (SPI)

HDA

SATA x1

3 3

CH-A DDR4 SODIMM/LPDIMM x1

Type-C Connector (CC+MUX)

USB3.0 repeater Periom PI3EQX7502A

USB3.0 Connector

USB3.0 Connector Alpine I/O Board

USB Charger TI TPS2546RTER

USB 2.0 Connector

Cruze I/O Board

Camera

Blue Tooth (WIFI + BT combo) NGFF Half

Finger Printer (Option)

Touch Panel

Audio Codec Realtek ALC3240

Int. Speaker

Int. Array Mic x2

Combo Jack

HDD Conn.

LPC

Alpine Sub-borad

I/O Board

Sensor Board (G sensor)

4 4

Cruze Sub-borad

I/O Board

Nuvoton NPCE388NB0DX

I2C x1

Int. KBD

G Sensor x1 (For Alpine)

I2C x1

G Sensor x1 (For Alpine)

Hall sensor x1 (For Cruze)

Hall sensor x2 (For Alpine)

I/O Board

Sensor Board

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT B E TRANSFERED FROM T HE CUSTODY OF THE COMPE TENT DIVISION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT B E TRANSFERED FROM T HE CUSTODY OF THE COMPE TENT DIVISION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT B E TRANSFERED FROM T HE CUSTODY OF THE COMPE TENT DIVISION OF R& D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORMATION IT CONTAINS MAYB E USED BY OR DISCLOSED T O ANY THIRD PARTY WIT HOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS , INC.

MAYB E USED BY OR DISCLOSED T O ANY THIRD PARTY WIT HOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS , INC.

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet of

Cover Page

Document Number Re v

LA-E541P

2 51Wednesday, June 21, 2017

2.A

Voltage Rails

power plane

+5VALW

B+

A A

State

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

B B

+3VALW

EC SM Bus1 address

Device

Smart Battery

Address

0001 011x 16h

+1.2V

O O

EC SM Bus2 address

Device

NCT7718W

PCH SM Bus address

Device

DDR_JDI MM1 Touch Pad

Address

1010 000x A0h

+5VS

+3VS

+1.35V S

+VCC_COR E

+VGA_COR E

+VCC_GFX CORE_AXG

+1.8VS

+0.6VS

+1.0VAL W

XXX

Address

1001 100x 98h

GPU SM Bus address

Device

Internal thermal sensor

SMBUS Control Table

VGA

C C

D D

SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 SMB_EC_CK4 SMB_EC_DA4 PCH_SMBCLK PCH_SMBDATA SML0CLK SML0DATA SML1CLK SML1DATA

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SOURCE

NECP38 8

+3VALW

NECP38 8

+3VS

NECP38 8

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

SIGNAL

+3VGS

X X X X X X X X X

SLP_S1 #

LOW

LOW LOW LOW

CHARGER

VX X

+19V_V IN

+3VALW

V X

+3VS

SLP_S4 #SLP_S3 # +V+VAL WSLP_S5 # Clock+VS

HIGHHIGHHIGH

HIGH HIGH HIGH

LOW

HIGH

LOWLOW

+3VS

HIGH

LOWLOW

BOM Structure Table

For DIS DIS@ For UMA UMA@ For T ouch Pan el with SPI TS_SP I@ For T ouch Pan el with I2C TS_I2 C@ For Keyboard backlight KBL@

For Samsung VRAM For Micron VRAM For Hynix VRAM For UHD Pa nel UHD@ For Finger Printer FP@ For SSD SSD@

For ESD ESD@ For R F RF@

No ES D No RF @RF@ Conne ctor ME@ For V ARM X76 X76@ For Test Point TP@ For Debug @DCI@

For S IMR series only S_IMR @ For YOGA s eries only

For C PU Type

EC SM Bus4 address

Device

BMA250E

Address

1001 111x 9Eh

Thermal

SODIMMNECP388BATT

Sensor

+3VS

ONONON

OFF

Item

Address

0001 100X 18h

DGPU TP

+3VS

ONON

LOW

OFF

USB 2.0 Port Table

BOM Structure

NOKBL @No K eyboard backlight S2G@ M2G@ H2G@

EMI@For EMI

@EMI@No EM I @ESD@

Item

For K BL U22 CPU

For K BL U42 CPU

For G PU Type

For EMI

For Thermal sensor EX_TH M@

BOM Structure

U22@

U42@ N16S_ R1@ N16S_ R3@ N16V_ R1@ N16V_ R3@

U22_E MI@ U42_E MI@

FP_ES D@For ESD

Port

1 2 3 4 5 6 7

USB 3.0 Port Table

Port

1 2 3 4 5 6

SATA Port Table

Port

S_AL@For S series only

YOGA@ i7_750 0U_R1@ i5_720 0U_R1@ i3_710 0U_R1@ i7_750 0U_R3@ i5_720 0U_R3@ i3_710 0U_R3@ pt_441 5U_R1@ pt_441 5U_R3@ i3_600 6U_R3@

0 1

X4E

Yoga Series S Series

ZZZ4

X4E Y Series

X4EA5R38LA1

Yoga Series (U42)

G-

PCH

SENSOR

+3VS

GPU part

UV1

N16S_R1@

N16S-GTR-S-A2 BGA 595P

SA00009FP00

UV1

N16S_R3@

N16S-GTR-S-A2 BGA 595P

SA00009FP30

UV1

N16V_R1@

N16V-GMR1-S-A2 BGA 595P

SA00009IT00

UV1

N16V_R3@

N16V-GMR1-S-A2 BGA 595P

SA00009IT30

ZZZ

X4E Y Series

X4EA5R38LL2

GDDR5 VRAM * 2

UV6

K4G80325FB-HC03

SA000094R20

CPU part

KBL U22 (= U22@)

UC1

QLYK H0 2.4G

SA0000A38A0

UC1

SR343 H0 2.4G

SA0000A38B0

ZZZ3

X4E_YA@

X4E_U42_YA@

S2G@

i3_7100U_R1@

i3_7100U_R3@

X4E_YA_FP@

X4E Y Series FP SKU

X4EA5R38LA2

ZZZ

X4E_U42_YA_FP@ ZZZ1

X4E Y Series FP SKU

X4EA5R38LL1

UV7

K4G80325FB-HC03

SA000094R20

RV65

SD034499180

4.99K_0402_1%

S2G@

UC1

i5_7200U_R1@

QLYJ H0 2.5G

SA0000A37A0

UC1

i5_7200U_R3@

SR342 H0 2.5G

SA0000A37B0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT B E TRANSFERED FROM T HE CUSTODY OF THE COMPE TENT DIVISION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT B E TRANSFERED FROM T HE CUSTODY OF THE COMPE TENT DIVISION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT B E TRANSFERED FROM T HE CUSTODY OF THE COMPE TENT DIVISION OF R& D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORMATION IT CONTAINS MAYB E USED BY OR DISCLOSED T O ANY THIRD PARTY WIT HOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS , INC.

MAYB E USED BY OR DISCLOSED T O ANY THIRD PARTY WIT HOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS , INC.

S2G@

ZZZ5

X4E_YB@

X4E Y Series UHD SKU

X4EA5R38LE2

X4E_U42_YB@

X4E Y Series UHD SKU

X4EA5R38LO2

UV6

MT51J256M32HF

SA000096K20

UC1

i7_7500U_R1@

QLYH H0 2.7G

SA0000A3490

UC1

i7_7500U_R3@

SR341 H0 2.7G

SA0000A34A0

2017/06/05 2018/06/05

ZZZ6

X4E Y Series UHD&FP SKU

X4EA5R38LE1

ZZZ2

X4E Y Series UHD&FP SKU

X4EA5R38LO1

M2G@

RV65

UC1

pt_4415U_R1@

QLYM H0 2.3G

SA0000ADV00

UC1

pt_4415U_R3@

SR348 H0 2.3G

SA0000ADV20

Compal Secret Data

Exter nal USB Port

USB3 Type-C Port USB2/3 Port (MB)

USB2/3 Port (IO/B)

USB3 Type-C Port Camera

Finger Printer (Option)

NGFF WLAN+BT

USB3 Type-C (MUX) USB2/3 Port (MB)

USB2/3 Port (IO/B)

HDD

X4E_YB_FP@

X4E_U42_YB_FP@

UV7

M2G@

MT51J256M32HF

SA000096K20

SD034100280

10K_0402_1%

M2G@

SKL U22 (= U22@)

UC1

i3_6006U_R3@

SR2JG K1 i3-6006U 2.0G C38!

SA0000ACN10

Deciphered Date

PCIE Port Table

Lane

10 11 12

X4E_S@

X4E_U42_S@

H2G@

ZZZ7

X4E S Series FP SKU

X4EA5R38L02

ZZZ

X4E S Series FP SKU

X4EA5R38LR2

RV65

SD034301280

30.1K_0402_1%

H2G@

ZZZ8

X4E S Series

X4EA5R38L01

S Series (U42)

ZZZ

X4E S Series

X4EA5R38LR1

X7671138L01X7671138L03 X7671138L02

UV6

H5GC8H24MJR-T2C

SA00009ZG10

Port

1 2

3 4 5 6 7 8 9

X4E_S_FP@

X4E_U42_S_FP@

UV7

H5GC8H24MJR-T2C

SA00009ZG10

KBL U42 (= U42@)

UC1

QNEF Y0 1.6G FCBGA

SA0000AWB00

UC1

QNEF Y0 1.6G FCBGA

SA0000AWB50

GPU

Card Reader NGFF WLAN+BT

SSD

HDMI Logo

ZZZ

45@

HDMI Logo

RO0000003HM

PCB part

ZZZ

YOGA@

PCB Y Series

DA80019S02A

ZZZ

S_AL@

PCB S Series

H2G@

i5_QNEF_R1@

i5_QNEF_R3@

Title

Notes List

Size

Document Number Re v

Custom

Date : Sheet of

DA80019S12A

ZZZ

S_IMR@

PCB S Series

DA80019S12A

UC1

i7_QNBF_R1@

QNBF Y0 1.8G FCBGA

SA0000AWC00

UC1

i7_QNBF_R3@

QNBF Y0 1.8G FCBGA

SA0000AWC50

Compal Electronics, Inc.

LA-E541P

2.A

3 51Wednesday, June 21, 2017

2.A

-PowerMap_KBL_DDR4_Volume_NON CS]

B+

D D

C C

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELEC TRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELEC TRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELEC TRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2017/06/05 2018/06/05

Deciphered Date

Compal Electronics, Inc.

Title

Power MAP

Size Document Number Re v

Size Document Number Rev

LA-C071P

Date: Sheet

4 51Wednesday, June 21, 2017

2.A

G3->S0 S0->S3 ->S0

+3VL_RTC

SOC_RTCRST#

B+

D D

+3VLP/+5V LP

EC_ON

+5VALW/+3VALW/+3VALW _DSW

PM_BATLOW#

tPCH01_Min : 9 ms

tPCH04_Min : 9 ms

Pull-up to DSW well if not implemented.

/DS3 DS3S0/

PCH_PWR_EN (SLP_SUS#)

+3V_PRIM

+1.8V_PRIM

EXT_PWR_GATE#

+1.0V_MPHYPLL

+1.0V_PRIM_CORE

+1.0V_PRIM

tPCH06_Min : 200 us

SUSACK#

PCH_DPWROK

EC_RSMRST#

C C

AC_PRESENT

tPCH34_Max : 20 ms

tPCH02_Min : 10 ms

tPCH03_Min : 10 ms

tPLT02_Min : 0 ms Max : 90 ms

ON/OFF

PBTN_OUT#

Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

PM_SLP_S5#

ESPI_RST#

If EXT_PWR_GATE# Toffmin is too small, Pwr gate may choose to completely ignore it

tPCH43_Min : 95 ms

tPCH18_Min : 90 us

PM_SLP_S4#

SYSON

+1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC

PM_SLP_S3#

SUSP#

+1.0VS_VCCSTG

+1.0VS_VCCIO

B B

+5VS/+3VS/+1.5VS /+1.05VS

EC_VCCST_PG

VR_ON

SM_PG_CTRL

+0.675VS_VTT

+VCC_SA

tCPU04 Min : 100 ns

tCPU10 Min : 1 ms

T <=10msec

T = 10msec

tCPU19 Max : 100 ns

tCPU18 Max : 35 us

tCPU09 Min : 1 ms

+VCC_CORE

+VCC_GT

VR_PWRGD

PCH_PWROK

tCPU16 Min : 0 ns

H_CPUPWRGD

SYS_PWROK

A A

SUS_STAT#

SOC_PLTRST#

S0->S5

+3VL_RTC

SOC_RTCRST#

B+

+3VLP/+5V LP

EC_ON

+5VALW/+3VALW/+3VALW _DSW

PM_BATLOW#

PCH_PWR_EN (SLP_SUS#)

+3V_PRIM

+1.8V_PRIM

EXT_PWR_GATE#

+1.0V_MPHYPLL

+1.0V_PRIM_CORE

+1.0V_PRIM

SUSACK#

PCH_DPWROK

EC_RSMRST#

AC_PRESENT

ON/OFF

PBTN_OUT#

PM_SLP_S5#

ESPI_RST#

PM_SLP_S4#

SYSON

+1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC

PM_SLP_S3#

SUSP#

+1.0VS_VCCSTG

+1.0VS_VCCIO

+5VS/+3VS/+1.5VS /+1.05VS

EC_VCCST_PG

VR_ON

SM_PG_CTRL

+0.675VS_VTT

+VCC_SA

+VCC_CORE

+VCC_GT

VR_PWRGD

PCH_PWROK

H_CPUPWRGD

SYS_PWROK

SUS_STAT#

SOC_PLTRST#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2017/06/05 2018/06/05

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Power Sequence

5 51Wednesday, J une 21, 2017

2.A

1 1

<HDMI>

HDMI DDC (Port C)

2 2

UC1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

HDMI_TX2-_CK<27> HDMI_TX2+_CK<27> HDMI_TX1-_CK<27> HDMI_TX1+_CK<27> HDMI_TX0-_CK<27> HDMI_TX0+_CK<27> HDMI_CLK-_CK<2 7> HDMI_CLK+_CK< 27>

HDMICLK_NB<27> HDMIDAT_NB<27>

TS_I2C_RST#<26>

EDP_COMP

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

GPP_E20/DDPC_CTRLCLK

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22

N12

GPP_E23

E52

EDP_RCOMP

SKL-U_BGA1356

DDI

DISPLAY SIDEBANDS

SKL-U

1 OF 20

EDP

Rev_1.0

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP

RSVD RSVD

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52

G50 F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

EDP_TXN0 <26> EDP_TXP0 <26> EDP_TXN1 <26> EDP_TXP1 <26> EDP_TXN2 <26> EDP_TXP2 <26> EDP_TXN3 <26> EDP_TXP3 <26>

EDP_AUXN <26> EDP_AUXP <26>

TMDS_B_HPD <27>

EC_SCI# <10,32>

EDP_HPD <26>

ENBKL <26,32> INVPWM <26> PCH_ENVDD <26>

<eDP>

From HDMI

From eDP

< Compensation PU For eDP >

+1.0VS_VCCIO

EDP_COMP

1 2

RC3 24.9_0402_1 %

Trace width=20 mils, Spacing=25mil, Max length=100mils

+1.0V_VCCST

H_THERMT RIP#

1 2

RC5 1K_0402_5%

3 3

H_PROCHOT#<32>

+1.0VS_VCCIO

RC4 1K_0402_5%

1 2

RC6 499_0402_ 1%

RC7 49.9_0402_1 % RC8 49.9_0402_1 % RC9 49.9_0402_1 %@ RC10 49.9_0 402_1%@

If routed MS, PECI requires 18 mils spacing to other signals

T99 TP@

H_PECI< 32>

T100 T P@

T103 T P@ T105 T P@ T107 T P@ T109 T P@

TS_INT#<26>

12 12 12 12

SOC_CATERR# H_PECI H_PROCHOT# _R H_THERMT RIP# SOC_OCC#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3

CPU_POPIRCOMP PCH_OPIRCOMP EDRAM_OPIO_RCOMP EOPIO_RCOMP

UC1D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

GPP_E3/CPU_GP0

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKL-U_BGA1356 @

SKL-U

CPU MISC

4 OF 20

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

Rev_1.0

JTAGX

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

CPU_XDP_TCK 0 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST #

PCH_JTAG_TC K1 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST # CPU_XDP_TCK 0

T116 TP@

< PU/PD for CMC Debug >

SOC_XDP_TMS

SOC_XDP_TDI

SOC_XDP_TDO

CPU_XDP_TCK 0

PCH_JTAG_TC K1

SOC_XDP_TRST #

RC11 51_0402_5 %@

RC12 51_0402_5 %@

RC13 51_0402_5 %@DCI@

RC14 51_0402_5 %@DCI@

RC15 51_0402_5 %@

RC23 51_0402_5 %@

+1.0VS_VCCIO

1 2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet of

Compal Electronics, Inc.

SKL-U(1/12)DDI,EDP,MISC,CMC

Custom

LA-E541P

2.A

6 51Wednesday, June 21, 2 017

2.A

Interleaved Memory

D D

DDR_A_D[0..15]<18>

DDR_A_D[16..31 ]<1 8>

C C

DDR_A_D[32..47 ]<1 8>

DDR_A_D[48..63 ]<1 8>

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

UC1B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

Interleave / Non-Interleaved

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKL-U_BGA1356 @

SKL-U

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR3L / LPDDR3 / DDR4

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

Interleave / Non-Interleaved

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

2 OF 20

DDR0_ALERT#

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

Rev_1.0

DDR0_MA[3] DDR0_MA[4]

DDR0_PAR

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54 AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50

BA50 BB52 AM70 AM69 AT69 AT70

BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26

AW50 AT52

AY67 AY68 BA67

AW67

DDR_A_CLK#0 DDR_A_CLK0 DDR_A_CLK#1 DDR_A_CLK1

DDR_A_CKE0 DDR_A_CKE1

DDR_A_CS#0 DDR_A_CS#1 DDR_A_ODT0 DDR_A_ODT1

DDR_A_MA5 DDR_A_MA9 DDR_A_MA6 DDR_A_MA8 DDR_A_MA7 DDR_A_BG0 DDR_A_MA12 DDR_A_MA11

DDR_A_MA13 DDR_A_MA15 DDR_A_MA14 DDR_A_MA16 DDR_A_BA0 DDR_A_MA2 DDR_A_BA1 DDR_A_MA10 DDR_A_MA1 DDR_A_MA0

DDR_A_MA3 DDR_A_MA4 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1

DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7

DDR_PG_CT RL

T119TP@ T118TP@

DDR_A_CLK#0 <18> DDR_A_CLK0 <18> DDR_A_CLK#1 <18> DDR_A_CLK1 <18>

DDR_A_CKE0 <18> DDR_A_CKE1 <18>

DDR_A_CS#0 <18> DDR_A_CS#1 <18> DDR_A_ODT0 <18> DDR_A_ODT1 <18>

DDR_A_MA5 <18> DDR_A_MA9 <18> DDR_A_MA6 <18> DDR_A_MA8 <18> DDR_A_MA7 <18> DDR_A_BG0 <1 8> DDR_A_MA12 <18> DDR_A_MA11 <18> M_A_ACT# <18> DDR_A_BG1 <1 8> DDR_A_MA13 <18> DDR_A_MA15 <18> DDR_A_MA14 <18> DDR_A_MA16 <18> DDR_A_BA0 <1 8> DDR_A_MA2 <18> DDR_A_BA1 <1 8> DDR_A_MA10 <18> DDR_A_MA1 <18> DDR_A_MA0 <18>

DDR_A_MA3 <18> DDR_A_MA4 <18> DDR_A_DQS#0 <18> DDR_A_DQS0 <18> DDR_A_DQS#1 <18> DDR_A_DQS1 <18>

DDR_A_DQS#2 <18> DDR_A_DQS2 <18> DDR_A_DQS#3 <18> DDR_A_DQS3 <18> DDR_A_DQS#4 <18> DDR_A_DQS4 <18> DDR_A_DQS#5 <18> DDR_A_DQS5 <18> DDR_A_DQS#6 <18> DDR_A_DQS6 <18> DDR_A_DQS#7 <18> DDR_A_DQS7 <18>

DDR_A_ALERT# <18> DDR_A_PARITY <1 8>

+0.6V_VREFCA <18> +0.6V_A_VREFDQ <18>

Trace width/Spacing >= 20mils

UC1C

Interleave / Non-Interleaved

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKL-U_BGA1356 @

SKL-U

DDR3L / LPDDR3 / DDR4

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

Interleave / Non-Interleaved

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

3 OF 20

Rev_1.0

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52 BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46

BB46 BA47

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32

AR25 AR27 AR22 AR21 AN43 AP43 AT13 AR18 AT18 AU18

DDR_DRAMRST #

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

T123TP@

DDR_DRAMRST # <18>

1 2

RC16 121_040 2_1%

1 2

RC17 80.6_040 2_1%

1 2

RC18 100_040 2_1%

+1.2V

CC101 0.1U_0201_10V6K

UC7

DDR_PG_CT RL

A A

NC1VCC

GND

74AUP1G07GW _TSSOP5

SA00007WE0 0

+3VS

RC54 220K_0402_ 5%

RC19 2M_0402_5 %

DDR_VTT_PG_ CTRL <42>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

DDR_DRAMRST #

+1.2V

RC20 470_0402_ 5%

CC96 100P_0402_ 50V8J

ESD@

Close to CPU

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

SKL-U(2/12)DDR3L

LA-E541P

Wednesday, June 21, 2 017

LA-E541P

2.A

SML0ALERT# (Internal Pull Down):

eSPI or LPC

0 = LPC is selected for EC ==> Default

D D

+3VALW

1 2

RC21 1K_0402_5%@

1 2

RC22 1K_0402_5%@

1 2

RC24 1K_0402_5%@

SOC_SPI_IO2

SOC_SPI_IO3

1 = eSPI is selected for EC

SOC_SML0CLK SOC_SML0DATA

RPC12

1 8 2 7 3 6 4 5

499_0804_ 8P4R_1%

+3VS

UC1E

+3VS

1 2

RC112 10K_0402 _5%

+1.8VS_3VS_PGPPA

1 2

RC25 8.2K_0402_5 %

C C

KB_RST#

SERIRQ

TS_SPI_CLK<2 6>

TS_SPI_SO<26> TS_SPI_SI<26>

TS_SPI_CS#0<26>

SERIRQ<32>

SOC_SPI_CLK SOC_SPI_SO SOC_SPI_SI SOC_SPI_IO2 SOC_SPI_IO3 SOC_SPI_CS#0

TS_SPI_CLK TS_SPI_SO TS_SPI_SI

TS_SPI_CS#0

SERIRQ

AW13

AY11

SPI - FLASH

AV2

SPI0_CLK

AW3

SPI0_MISO

AV3

SPI0_MOSI

AW2

SPI0_IO2

AU4

SPI0_IO3

AU3

SPI0_CS0#

AU2

SPI0_CS1#

AU1

SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK

GPP_D2/SPI1_MISO

GPP_D3/SPI1_MOSI

GPP_D21/SPI1_IO2

GPP_D22/SPI1_IO3

GPP_D0/SPI1_CS#

C LINK

CL_CLK

CL_DATA

CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

SKL-U_BGA1356 @

SKL-U

SMBUS, SMLINK

LPC

GPP_A14/SUS_STAT#/ESPI_RESET#

5 OF 20

Rev_1.0

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

R7 R8 R10

R9 W2 W1

W3 V3 AM7

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9 AW11

PCH_SMB_CL K PCH_SMB_DATA SOC_SMBALERT#

SOC_SML0CLK SOC_SML0DATA SOC_SML0ALERT #

SOC_SML1ALERT #

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME#

LPC_CLK0

PM_CLKRUN#KB_RST#

T124TP@

T125TP@

1 2

RC26 22_04 02_5%EMI@

PCH_SMB_CL K <18>

PCH_SMB_DATA <18 >

EC_SMB_CK2 <22,32,36 > EC_SMB_DA2 <22,32,36 >

LPC_AD0 <32> LPC_AD1 <32> LPC_AD2 <32> LPC_AD3 <32>

LPC_FRAME# <32>

SMB

(Link to DDR)

SML1

(Link to EC,DGPU,Thermal Sensor)

CLK_LPC_EC < 32>

SOC_SML1ALERT #

PCH_SMB_CL K PCH_SMB_DATA EC_SMB_CK2 EC_SMB_DA2

PM_CLKRUN#

RC113 150K_040 2_5%@

RC31 8.2K_04 02_5%@

Follow 543016_SKL_U_Y_PDG_0_9

1 2

RPC2

1 8 2 7 3 6 4 5

1K_0804_8P 4R_5%

1 2

+3VS

+1.8VS_3VS_PGPPA

RPC1, RPC3 and RC30 are close to UC3

SOC_SPI_SO SOC_SPI_CLK SOC_SPI_CLK_0_R SOC_SPI_SI

B B

From EC

From SOC

EC_SPI_CLK<32> EC_SPI_MOSI<32 > EC_SPI_CS0#<32>

EC_SPI_MISO<32 >

SOC_SPI_IO3

SOC_SPI_IO2

RPC1

SOC_SPI_SO_0_R

1 8 2 7

SOC_SPI_SI_0_R

3 6

SOC_SPI_IO3_0_R

4 5

33_0804_8 P4R_5%

EMI@

SOC_SPI_IO2_0_R

1 2

RC30 33_0402_5 %EMI@

RPC3

1 8 2 7 3 6 4 5

33_0804_8 P4R_5%

EMI@

SOC_SPI_CLK_0_ R

SOC_SPI_CS#0 SOC_SPI_SO_0_R

EC_SPICLK EC_MOSI SOC_SPI_SI_0_R EC_SPICS# EC_MISO

< SPI ROM - 8M >

SOC_SPI_CS#0

SOC_SPI_IO2_0_R

A A

UC3

/CS

DO(IO1)

/WP(IO2)

GND

W25Q64FVSSIQ_SO8

/HOLD(IO3)

DI(IO0)

+3VALW

CC2 0.1U_0201_10V K X5R

VCC

SOC_SPI_IO3_0_RSOC_SPI_SO_0_R

SOC_SPI_CLK_0_ R

CLK

SOC_SPI_SI_0_R

1 2

CC3 10P_0402_5 0V8J

@EMI@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

Compal Electronics, Inc.

SKL-U(3/12)SPI,SMB,LPC,ESPI

LA-E541P

8 51Wednesday, June 21, 2 017

2.A

D D

< HD AUDIO >

HDA_BITCLK_AUDIO<28> HDA_SYNC_AUDIO<28>

RPC4

1 8 2 7 3 6 4 5

33_0804_8 P4R_5%

EMI@

HDA_BIT_CLK HDA_SYNC

HDA_SDOUT

HDA_SYNC HDA_BIT_CLK

HDA_SDIN0<28>HDA_SDOUT_AUD IO< 28>

HDA_SDOUT

< To Enable ME Override >

1 2

C C

ME_EN<32>

RC116 0_0402_5%

+3VS

1 2

RC33 2.2K_0402_5%@

HDA_SDOUT

HDA_SPKR

HDA_SPKR<28>

HDA_SPKR

SPKR ( Internal Pull Down):

B B

TOP Swap Override

0 = Disable TOP Swap mode. ==> Default

1 = Enable TOP Swap Mode.

UC1G

BA22 AY22 BB22 BA21 AY21

AW22

AY20

AW20

AK10

AW5

AK7 AK6 AK9

AUDIO

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK

GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0

GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1

GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKL-U_BGA1356 @

UC1I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKL-U_BGA1356 @

SKL-U

9 OF 20

GPP_A17/SD_PWR_EN#/ISH_GP7

7 OF 20

Rev_1.0

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK GPP_F12/EMMC_CMD

EMMC_RCOMP

SDIO / SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

C37 D37 C32 D32 C29 D29 B26 A26

E13

RC80 100_0 402_1%@

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

RC129 200_040 2_1%@

Rev_1.0

1 2

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

1 2

RC76 200_0 402_1%@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

Compal Electronics, Inc.

SKL-U(4/12)HDA,EMMC,SDIO,CSI2

LA-E541P

Wednesday, June 21, 2 017

LA-E541P

2.A

SOC_XTAL24_IN XTAL24_IN

U22_EMI@

1 2

RC154 33_0402 _1%

SOC_XTAL24_OUT XTAL24_OUT

+3VS

D D

RPC5

CLKREQ_PCIE#4

CLKREQ_PCIE#5

27 36 45

10K_0804_8 P4R_5%

RPC6

CR_CLKREQ#

WLANCLK_R EQ#

27 36

SSDCLK_REQ#

10K_0804_8 P4R_5%

+3VS

RC134

1 2

+3VL_RTC

C C

+3VALW

B B

ESD@

+3VALW

RC47 1K_04 02_5%

VGA_CLKREQ#

10K_0402_5 %

1 2

RC36 20K_0 402_5%

1 2

CC6 1U_0402_6 .3V6K

1 2

RC37 20K_0 402_5%

1 2

CC7 1U_0402_6 .3V6K

1 2

CLRP2 SHORT PADS

1 2

RC39 1M_04 02_5%

RPC7

PCH_PWR OK

EC_RSMRST#

27 36

SYS_RESET#

10K_0804_8 P4R_5%

1 2

CC97 100P_0402_ 50V8J

1 2

CC94 100P_0402_ 50V8J

1 2

CC95 100P_0402_ 50V8J

1 2

SYS_RESET#

EC_RSMRST#

SYS_PWROK

WAKE#

EC_SCI# <6,32>

SOC_SRTCRS T#

SOC_RTCRST #

CLR CMOS

SM_INTRUDER#

Card Reader RTS5220

1 2

RC38 0_040 2_5%

Only For Power Sequence Debug

From EC (Open-Drain)

A A

VCCST_PWR GD<3 2>

DGPU

SSD

NGFF WL+BT

+1.0V_VCCST

EC_CLEAR_CMO S# <32>

RC52 1K_0402_5%

CLK_PEG_VGA#<19> CLK_PEG_VGA<19>

VGA_CLKREQ#<19>

CLK_PCIE_SSD#<31> CLK_PCIE_SSD<31> SSDCLK_REQ#< 31>

CLK_PCIE_WL AN#<30> CLK_PCIE_WL AN<30> WLANCLK_R EQ#<30>

CLK_PCIE_CR#<35> CLK_PCIE_CR<35>

CR_CLKREQ#<35 >

EC_RSMRST#<32>

T132 TP @

SYS_PWROK<3 2>

PCH_PWR OK<32>

1 2

RC53 60.4_0 402_1%

CC117 100P_0402_ 50V8J

ESD@

VGA_CLKREQ#

SSDCLK_REQ#

WLANCLK_R EQ#

CLKREQ_PCIE#4

CLKREQ_PCIE#5

< PCH PLTRST Buffer >

SOC_PLTRST #

SOC_PLTRST # SYS_RESET# EC_RSMRST#

H_CPUPW RGD EC_VCCST_PG

SYS_PWROK PCH_PWR OK EC_RSMRST#

WAKE#

EC_VCCST_PG

UC1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKL-U_BGA1356 @

1 2

RC42 0_0402_5%

+3VS

UC4

TC7SH08FU F_SSOP5

SA007080100

UC1K

AN10

GPP_B13/PLTRST#

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKL-U_BGA1356 @

SYSTEM POWER MANAGEMENT

SKL-U

CLOCK SIGNALS

10 OF 20

100P_0402_50V8J

100K_0402_5%

RC44

ESD@

CC8

SKL-U

GPP_B11/EXT_PWR_GATE#

11 OF 20

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev_1.0

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XCLK_BIASREF

PCI_RST# <19,30,31 ,32,35>

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

GPP_B2/VRALERT#

F43 E43

BA17

SUSCLK

SOC_XTAL24_IN

E37

XTAL24_IN

XTAL24_OUT

RTCX1 RTCX2

SRTCRST#

RTCRST#

Rev_1.0

SLP_SUS#

SLP_LAN#

INTRUDER#

2017/06/05 2018/06/05

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

AM10 AM11

E35

E42

AM18 AM20

AN18 AM16

SOC_XTAL24_OUT

XCLK_BIASREF

SOC_RTCX1 SOC_RTCX2

SOC_SRTCRS T# SOC_RTCRST #

PM_SLP_S0# PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#

SLP_WLAN# PM_SLP_A#

PBTN_OUT# AC_PRESENT PM_BATLOW#

SM_INTRUDER#

SOC_VRALERT#

Compal Secret Data

PM_SLP_S3# <32> PM_SLP_S4# <32,40,42>

1 2

RC103 0_0402_ 5%

Deciphered Date

SUSCLK <30>

T130TP@

T131TP@

T133TP@ T134TP@

U22_EMI@

1 2

RC155 33_0402 _1%

SOC_RTCX2

SOC_RTCX1

PBTN_OUT# <32>

EC_VCIN1_AC_BYPASS <22,32>

Custom

Date : Sheet of

U22@

1 2

RC34 1M_04 02_5%

U22@

YC1

24MHZ_18PF_XRC GB24M000F2P51R0

SJ10000UJ00

U22@

27P_0402_50V8J

CC4

XCLK_BIASREF

PM_BATLOW#

AC_PRESENT

SOC_VRALERT#

Title

SKL-U(5/12)CLK,PM,GPIO

Size Document Number Re v

1 2

RC35 2.7K_0402_1 %

1 2

RC110 60.4_0402 _1%@

1 2

RC41 10M_0402_5%

YC2

1 2

32.768KHZ_9P F_9H03280012

6.8P_0402_50V8C

Compal Electronics, Inc.

SJ10000Q400

CC9

1 2

RC46 8.2K_0402_5 %

1 2

RC48 10K_0402_5 %@

1 2

RC50 10K_0402_5 %@

LA-E541P

27P_0402_50V8J

+1.0V_CLK5_F2 4NS

10 51Wednesday, June 21, 2017

U22@

CC5

+3VALW

6.8P_0402_50V8C

CC10

2.A

GSPI0_MOSI (Internal Pu ll Down):

No Reboot

0 = Disable No Reboot mode. ==> Default

1 = Enable No Reboot Mode. (PCH will disable the TCO Timer system reboot feature). This funct i on is usef ul

D D

when running ITP/XDP.

+3VS

1 2

RC206 10K_0402 _5%@

1 2

RC205 10K_0402 _5%@

STORAGE_PRSNT 1

GSPI1_MOSI (Internal Pu ll Down):

Boot BIOS Strap Bit

1 2

RC208 10K_0402 _5%@

1 2

RC207 10K_0402 _5%@

STORAGE_PRSNT 2

0 = SPI Mode ==> Default

1 = LPC Mode

+3VS

1 2

RC59 4.7K_0402_5 %@

1 2

RC60 150K_0402_ 5%@

C C

+3VS

RPC10

1 8 2 7 3 6 4 5

49.9K_0804_ 8P4R_1%

RPC8

18 27 36 45

10K_0804_8 P4R_5%

RPC11

18 27 36 45

2.2K_0804_8 P4R_5%

+3VS

B B

+3VS

GSPI0_MOSI

GSPI1_MOSI

UART0_RX UART0_TX

DGPU_PWR _EN DGPU_HOLD_R ST#

WLBT_OFF#

I2C1_SCL_TS I2C1_SDA_TS I2C0_SCL_TP I2C0_SDA_TP

Touch PAD

Touch Panel

EC Sensor

UC1F

AN8

AH10

AH11 AH12

AF11 AF12

AP7 AP8 AR7

AM5 AN7 AP5 AN5

AB1 AB2

AB3

AD1 AD2 AD3 AD4

U7 U6

U8 U9

AH9

SOC_GPIOB17 GSPI0_MOSI

SENSOR_EC_INT<32>

TP_INT#<33>

WLBT_OFF#<30>

UART0_RX<3 0>

UART0_TX<30>

I2C0_SDA_TP<33> I2C0_SCL_TP<33>

I2C1_SDA_TS<26> I2C1_SCL_TS<26>

I2C2_SDA_SEN<3 2> I2C2_SCL_SEN<32>

GSPI1_MOSI

SOC_GPIOC10

LPSS ISH

GPP_B15/GSPI0_CS# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL

SKL-U_BGA1356 @

SKL-U

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6

6 OF 20

Rev_1.0

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_D15/ISH_UART0_RTS#

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

P2 P3

STORAGE_PRSNT 2

STORAGE_PRSNT 1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

DGPU_PWR _EN

AC1

DGPU_HOLD_R ST#

AC2

GPU_ALL_PGOOD

AC3

DGPU_PRSNT

AB4

MB_ID

AY8 BA8

DGPU_SEL

BB7 BA7 AY7 AW7

TP_PRSNT

AP13

DGPU_PWR _EN <24,32> DGPU_HOLD_R ST# <19> GPU_ALL_PGOOD <24>

Funct i on

DIS

UMA Only

+3VS

RC61 10K_0 402_5%UMA@

RC62 10K_0 402_5%DIS@

Funct i on

YOGA series

S series 1

+3VS

RC146 10K_0402 _5%S_AL@

RC147 10K_0402 _5%YOGA@

Funct i on

N16V-GRM1(920)

+3VS

RC210 10K_0402 _5%

RC209 10K_0402 _5%

1 2

N16S_R1@

1 2

N16V_R1@

1 2

DGPU_PRSNT (GPP_C1 5)

MB_ID

DGPU_SEL

1N16S-GTR-S(94 0)

DGPU_PRSNT

RC146 S_IMR@ 10K_0402_5 %

MB_ID

DGPU_SEL

RC210 N16S_R3 @ 10K_0402_5 %

RC209 N16V_R3@ 10K_0402_5 %

SOC_GPIOC10 GPU_ EVENT#

SOC_GPIOB17 GC6_FB_EN

A A

1 2

RC204 0_0402_ 5%

1 2

RC195 0_0402_ 5%

GPU_EVENT# <22>

GC6_FB_EN <2 2,23>

TO DGPU

+3VS

1 2

RC212 10K_0402 _5%@

1 2

RC211 10K_0402 _5%@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

Compal Electronics, Inc.

SKL-U(6/12)GPIO,I2C,GSPI

TP_PRSNT

LA-E541P

2.A

11 51Wednesday, June 21, 2017

2.A

D D

UC1H

PCIE / USB3 / SATA

PCIE_PRX_DTX_N1<19> PCIE_PRX_DTX_P1<19>

PCIE_PTX_C_DRX_N 1<19> PCIE_PTX_C_DRX_P1<19>

PCIE_PRX_DTX_N2<19> PCIE_PRX_DTX_P2<19>

PCIE_PTX_C_DRX_N 2<19>

dGPU

C C

Card Reader

NGFF WLAN+BT

HDD

PCIE_PTX_C_DRX_P2<19>

PCIE_PRX_DTX_N3<19> PCIE_PRX_DTX_P3<19>

PCIE_PTX_C_DRX_N 3<19>

PCIE_PTX_C_DRX_P3<19>

PCIE_PRX_DTX_N4<19>

PCIE_PRX_DTX_P4<19> PCIE_PTX_C_DRX_N 4<19> PCIE_PTX_C_DRX_P4<19>

PCIE_PRX_DTX_N5<35> PCIE_PRX_DTX_P5<35> PCIE_PTX_C_DRX_N 5<35> PCIE_PTX_C_DRX_P5<35>

PCIE_PRX_DTX_N6<30> PCIE_PRX_DTX_P6<30> PCIE_PTX_C_DRX_N 6<30> PCIE_PTX_C_DRX_P6<30>

SATA_PRX_DTX_N0<29> SATA_PRX_DTX_P0<29> SATA_PTX_DRX_N0<29> SATA_PTX_DRX_P0<2 9>

PCIE_PRX_DTX_N9<31> PCIE_PRX_DTX_P9<31>

PCIE_PTX_C_DRX_N 9<31> PCIE_PTX_C_DRX_P9<31>

PCIE_PRX_DTX_N10<31>

PCIE_PRX_DTX_P10<31> PCIE_PTX_C_DRX_N 10<31> PCIE_PTX_C_DRX_P1 0<31>

SSD

B B

PCIE_PRX_DTX_N11<31> PCIE_PRX_DTX_P11<31>

PCIE_PTX_C_DRX_N 11<31>

PCIE_PTX_C_DRX_P1 1<31> PCIE_PRX_DTX_N12<31> PCIE_PRX_DTX_P12<31>

PCIE_PTX_C_DRX_N 12<31> PCIE_PTX_C_DRX_P1 2<31>

1 2

CC11 0.22U_0402 _6.3V6KDIS@

1 2

CC14 0.22U_0402 _6.3V6KDIS@

1 2

CC15 0.22U_0402 _6.3V6KDIS@

1 2

CC16 0.22U_0402 _6.3V6KDIS@

1 2

CC12 0.22U_0402 _6.3V6KDIS@

1 2

CC13 0.22U_0402 _6.3V6KDIS@

1 2

CC17 0.22U_0402 _6.3V6KDIS@

1 2

CC18 0.22U_0402 _6.3V6KDIS@

0.1U_0201_ 10V K X5R

1 2

CC19 CC20

CC102 CC103

CC110 0.22U_04 02_6.3V6KSSD@ CC109 0.22U_04 02_6.3V6KSSD@

CC114 0.22U_04 02_6.3V6KSSD@ CC113 0.22U_04 02_6.3V6KSSD@

CC116 0.22U_04 02_6.3V6KSSD@ CC115 0.22U_04 02_6.3V6KSSD@

CC112 0.22U_04 02_6.3V6KSSD@ CC111 0.22U_04 02_6.3V6KSSD@

0.1U_0201_ 10V K X5R

1 2

0.1U_0201_ 10V K X5R

1 2

0.1U_0201_ 10V K X5R

1 2

1 2 1 2

1 2

RC71 100_0 402_1%

1 2 1 2

T147 T P@ T148 T P@

PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3

PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4

PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5

PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6

PCIE_PTX_DRX_N9 PCIE_PTX_DRX_P9

PCIE_PTX_DRX_N10 PCIE_PTX_DRX_P10

PCIE_RCOMPN PCIE_RCOMPP

XDP_PRDY# XDP_PREQ#

PCIE_PTX_DRX_N11 PCIE_PTX_DRX_P11

PCIE_PTX_DRX_N12 PCIE_PTX_DRX_P12

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

PCIE_RCOMPN

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL-U_BGA1356

SKL-U

USB2

8 OF 20

SSIC / USB3

USB3_2_RXN / SSIC_RXN USB3_2_RXP / SSIC_RXP

USB3_2_TXN / SSIC_TXN USB3_2_TXP / SSIC_TXP

GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

Rev_1.0

USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_3_RXN USB3_3_RXP USB3_3_TXN USB3_3_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

USB2_VBUSSENSE

GPP_E9/USB2_OC0#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E8/SATALED#

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6 AG3 AG4

A9 C9 D9 B9

J1 J2 J3

H2 H3 G4

USB20_N1 USB20_P1

USB20_N2 USB20_P2

USB20_N3 USB20_P3

USB20_N5 USB20_P5

USB20_N6 USB20_P6

USB20_N7 USB20_P7

USB2_COMP

RC70 113_0402_ 1% RC104 1K_0402_ 5% RC105 1K_0402_ 5%

USB_OC3#

USB3_RX1_N <34>

USB3_RX1_P <34>

USB3_TX1_N <34>

USB3_TX1_P <34>

USB3_RX2_N <35>

USB3_RX2_P <35>

USB3_TX2_N <35>

USB3_TX2_P <35>

USB3_RX3_N <35>

USB3_RX3_P <35>

USB3_TX3_N <35>

USB3_TX3_P <35>

USB20_N1 <34> USB20_P1 <34>

USB20_N2 <35> USB20_P2 <35>

USB20_N3 <35> USB20_P3 <35>

USB20_N5 <26> USB20_P5 <26>

USB20_N6 <29> USB20_P6 <29>

USB20_N7 <30> USB20_P7 <30>

1 2 1 2 1 2

USB_OC0# <34> USB_OC1# <35> USB_OC2# <35>

WL_OFF# <30>

USB3 Type-C (MUX)

USB2/3 Port (MB)

USB2/3 Port (IO/B)

USB3 Type-C Port

USB2/3 Port (MB)

USB2/3 Port (IO/B)

Cam era

Finger Printer

NGFF WLAN+BT

USB_OC1# USB_OC3# USB_OC0# USB_OC2#

WL_OFF#

10K_0804_8 P4R_5%

1 2

RC139 10K_0402 _5%@

RPC9

+3VALW

18 27 36 45

+3VS

When PCIE8/SATA1A is used as SATA Port 1 (ODD), then PCIE11/SATA1B (M.2 SSD) cannot be used as SATA Port 1.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(7/12)PCIE,USB,SATA

Size Document Number Re v

Custom

Date : Sheet of

LA-E541P

12 51Wednesday, June 21, 2017

2.A

+1.2V

UC1N

+VL

+1.0VALW

1U_0402_6.3V6K

D D

+1.0VALW TO +1.0V_VCCST

SYSON<32,42>

SUSP#<3 2,37,42>

RC74 0_040 2_5%

RC75 0_040 2_5%

+1.8VALW TO +1.8VS

C C

+VL

0.1U_0201_10V K X5R

SUSP#

B B

RC81 0_040 2_5%

1U_0402_6.3V6K

CC21

+1.8VALW

I(Max) : 0.16 A(+1.0V_VCCST)

CC22

RON(Max) : 25 mohm V drop : 0.004 V

EN_1.0V_VCCSTU

EN_1.8VS

1U_0402_6.3V6K

6 7

EM5209VF DFN 14P D UAL LOAD SW

CC26

I(Max) : 0.2 A(+1.8VS) RON(Max) : 25 mohm V drop : 0.005 V

UC5

VIN1 VIN1

ON1

VBIAS

ON2

VIN2 VIN2

VOUT1 VOUT1

GND

VOUT2 VOUT2

GPAD

CT1

CT2

14 13

8200P_0402 _25V7K

1000P_0402 _50V7K

+1.0V_VCCST_R

RC136 0_0402_5%

1 2

CC24

1 2

CC25

+1.8VS_R

RC137 0_0402_ 5%

Follow 543977_SKL_PDDG_Rev0_91 CC24 10PF ->22us(Spec:<= 65us)

+1.0VALW TO +1.0VS_VCCIO

+1.0VALW

1U_0402_6.3V6K

CC30

I(Max) : 3.04 A(+1.0VS_VCCIO) RON(Max) : 6.2 mohm V drop : 0.019 V

CC32

UC6

VIN1

VIN2

VIN thermal

VBIAS

AOZ1334DI-01_DFN 8 P

VOUT

GND

+1.0VS_VCCIO_STG

1 2

RC79 0_080 5_5%

+1.0VS_VCCIO

+1.0V_VCCST

+1.8VS

CC33

0.1U_0201_ 10V K X5R

0.1U_0201_10V K X5R

CC23

0.1U_0201_10V K X5R

CC27

+1.0VS_VCCIO

+1.0V_VCCST

AM40

SKL-U

VDDQ_AU23 VDDQ_AU28 VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51

VDDQC

VCCST

VCCSTG_A22

VCCPLL_OC

VCCPLL_K20 VCCPLL_K21

SKL-U_BGA1356

+1.0V_VCCST

CPU POWER 3 OF 4

VCCSA_SENSE

14 OF 20

1U_0402_6.3V6K

CC28

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE

AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51

AL23

A18

A22

K20 K21

Close to A18 Close to K20 Close to A22

1U_0402_6.3V6K

+1.0VS_VCCIO

Rev_1.0

AK28

VCCIO

AK30

VCCIO

AL30

VCCIO

AL42

VCCIO

AM28

VCCIO

AM30

VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

+VCCSA

VSSSA_SENSE VCCSA_SENSE

Trace Length Match < 25 mils

+1.0VS_VCCIO

CC34

VSSSA_SENSE <46> VCCSA_SENSE <46>

BSC SidePSC Side

1U_0402_6.3V6K

CC35

+1.0VS_VCCIO +1.2V

1U_0402_6.3V6K

10U_0603_6.3V6M

CC36

A A

1U_0402_6.3V6K

CC37

CC38

PSC SideBSC Side BSC SidePSC Side

1U_0402_6.3V6K

CC40

CC39

CC42

CC41

1U_0402_6.3V6K

BSC Side

CC29

1U_0402_6.3V6K

CC43

Close to CPUUnderneath CPU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/06/05 2018/06/05

22U_0603_6.3V6M

CC44

Close to CPUClose to AM40 Underneath CPUClose to AL23

Compal Secret Data

10U_0603_6.3V6M

CC45

CC46

Deciphered Date

10U_0603_6.3V6M

CC47

CC48

1U_0402_6.3V6K

CC50

CC49

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

SKL-U(8/12)Power

LA-E541P

2.A

13 51Wednesday, June 21, 2017

2.A

D D

1 2

22U_0603_6.3V6M

CC72

CC51 1U_0402_6 .3V6K

1 2

CC54 1U_0402_6 .3V6K

Imax : 2.57A

1 2

CC55 1U_0402_6 .3V6K

1 2

CC56 1U_0402_6 .3V6K

Close to K17

1 2

CC60 22U_0603_ 6.3V6M

Imax : 1.54A

1 2

CC61 1U_0402_6 .3V6K

Close to P15

+1.0V_AMPHYPLL

+1.0V_APLL

+3VALW

+3V_1.8V_HDA

1 2

CC65 1U_0402_6 .3V6K

Close to AF20

1 2

CC67 1U_0402_6 .3V6K

Close to AJ21

1 2

CC68 1U_0402_6 .3V6K

Close to N18

22U_0603_6.3V6M

CC73

CC74

Follow 543016_SKL_U_Y_PDG_1_0

+1.0VALW

LC1

MURATA BLM15EG22 1SN1D

1 2

RF@

SM01000HC0 0

R_0402

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC148 0_0603_ 5%

C C

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC85 0_060 3_5%

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC87 0_060 3_5%

B B

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC91 0_060 3_5%

1U_0402_6.3V6K

+1.0V_APLL

+1.0V_AMPHYPLL

22U_0603_6.3V6M

CC58

+1.0V_CLK5_F2 4NS

22U_0603_6.3V6M

CC63

+1.0V_CLK4_F1 00OC

22U_0603_6.3V6M

CC69

+1.0V_CLK6_24 TBT

1U_0402_6.3V6K

CC84

CC83

0.1U_0201_10V K X5R

CC31

RF@

1U_0402_6.3V6K

CC59

22U_0603_6.3V6M

CC64

22U_0603_6.3V6M

CC70

22U_0603_6.3V6M

CC85

+3VALW

22U_0603_6.3V6M

CC86

LC2

MURATA BLM15EG22 1SN1D

1 2

SM01000HC0 0

R_0402

+3VS

LPC 3.3V

1 2

RC93 0_0402_5%

+3V_1.8V_HDA

RF@

+1.8VS_3VS_PGPPA

0.1U_0201_10V K X5R

CC66

+1.0VALW +3VALW +1.8VALW

22U_0603_6.3V6M

CC71

+1.0VALW

DCPDSW

UC1O

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB_1P0

SKL-U_BGA1356

SKL-U

CPU POWER 4 OF 4

15 OF 20

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE VCCPGPPF VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

Rev_1.0

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

+1.8VALW

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19

AA1

AK17

AK19 BB14

BB10

A14

K19

L21

N20

L19

A10

AN11 AN13

+3VALW

DCPRTC

VCCPGPPF support 1.8V only

+1.0VALW

1 2

CC57 1U_0402 _6.3V6K

+3VL_RTC

1 2

CC62 0.1U_0201 _10V K X5R

+1.0V_CLK6_24 TBT

+1.0V_APLL

+1.0V_CLK4_F1 00OC

+1.0V_CLK5_F2 4NS

+1.0V_CLK6_24 TBT

RTC Battery

22U_0603_6.3V6M

CC76

CC75

+3VALW

1U_0402_6.3V6K

CC77

CC80

1U_0402_6.3V6K

CC78

CC81

1U_0402_6.3V6K

Close to AK17Close to T16Close to Y16Close to AG15

+3VL_RTC +RTCBAT T

W=20mil s

1 2

0.1U_0201_10V K X5R

CC79

RC90 0_040 2_5%

CC82 1U_0402_6 .3V6K

Safty suggestion remove EE side, Keep PWR side

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(9/12)Power

Size Document Number Re v

Custom

Date : Sheet of

LA-E541P

14 51Wednesday, June 21, 2017

2.A

U22/U42 co-lay

+VCCGT_VCCCOR E

D D

R418

U42@

112

SOLDER_PREFOR MS_0603

R414

U42@

112

SOLDER_PREFOR MS_0603

R419

U22@

112

SOLDER_PREFOR MS_0603

+VCCCORE

+VCCGT

+VCCGT +VCCGT

+VCCGT_VCCCOR E

+VCCCORE +VCCCORE

C C

T157 T P@ T158 T P@

B B

VCCOPC_SENSE VSSOPC_SENSE

AK33 AK35 AK37 AK38 AK40

AL33 AL37

AL40 AM32 AM33 AM35 AM37 AM38

AK32

AB62

AC63 AE63

AE62 AG62

AL63

AJ62

A30 A34 A39 A44

G30

K32

P62 V62

H63

G61

UC1L

VCC_A30 VCC_A34 VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RSVD

VCCOPC_AB62 VCCOPC_P62 VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE VSSOPC_SENSE

VCCEOPIO VCCEOPIO

VCCEOPIO_SENSE VSSEOPIO_SENSE

SKL-U_BGA1356

SKL-U

CPU POWER 1 OF 4

12 OF 20

Rev_1.0

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VCC_SENSE VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

SOC_SVID_ALERT#

B63

VR_SVID_CLK

A63

VR_SVID_DATA

D64

G20

ALERT signal must be routed between CLK and DATA signals

Trace Length Match < 25 mils

VCCCORE_SENSE <4 6> VSSCORE_SENSE <46>

VR_SVID_CLK <46>

+1.0VS_VCCIO

VCCGT_SENSE<46> VSSGT_SENSE<46>

1 2

R416 0_0603_5%U22@

VCCGT_SENSE VSSGT_SENSE

+VCCGT_K52

Trace Length Match < 25 mils

SVID ALERT

+1.0V_VCCST

Place the PU resistors close to CPU

RC94 56_0402_5 %

AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71

A48 A53 A58 A62 A66

J43 J45 J46 J48 J50 J52 J53 J55 J56 J58 J60 K48 K50 K52 K53 K55 K56 K58 K60 L62 L63 L64 L65 L66 L67 L68 L69 L70 L71

M62

N63 N64 N66 N67 N69

J70 J69

UC1M

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT_SENSE VSSGT_SENSE

SKL-U_BGA1356

SKL-U

CPU POWER 2 OF 4

13 OF 20

Rev_1.0

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70 VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56 VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63 VCCGTX_BB57 VCCGTX_BB66

VCCGTX_SENSE

VSSGTX_SENSE

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

1 2

R417 0_0 402_5%U22@

VCCGTX_SENSE VSSGTX_SENSE

+VCCGT_VCCCOR E

T161 TP @ T162 TP @

+VCCGT

SOC_SVID_ALERT#

SVID DATA

A A

VR_SVID_DATA

1 2

RC95 220 _0402_5%

+1.0V_VCCST

Place the PU resistors close to CPU

RC96 100_0402_ 1%

VR_ALERT# <46>

VR_SVID_DATA <46>

(To VR)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(10/12)Power,SVID

Size Document Number Re v

Custom

Date : Sheet of

LA-E541P

15 51Wednesday, June 21, 2017

2.A

+ 33 hidden pages

Compal LA-E541P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual