Compal LA-E541P Schematics

A

1 1

B

C

D

E

Compal Confidential

2 2

DIS M/B Schematics Document

Intel KabyLake U/KabyLake R Processor with DDR4

N16S-GTR(940) (23x23mm) N16V-GMR1(920) (23x23mm)

3 3

2017-06-05

LA-E541P

DIUYA/YB/SA/SB/SD (KBL-R)

REV

FAB: JB501

：

2.A

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

Cover Page

LA-E541P

2.A

1 51Wednesday, June 21, 2 017

E

1 51Wednesday, June 21, 2 017

2.A

A

B

C

D

E

1 1

nVIDIA N16V-GMR1 / N16S-GTR

VRAM(GDDR5)*2 2GB

N16V-GMR1 (Cruze) N16S-GTR (Alpine/Cruze)

eDP Panel

HDMI Conn.

PCIe x4

eDP x1 4 Lanes (Alpine) 2 Lanes (Cruze)

DDI

Intel KBL-U 15W/28W

Memory Bus

DDR4 2133MHz (1.2V)

( 2400 MHz )

USB3.0 x3

1356pin BGA

SD Card Connector

2 2

Wireless LAN (WIFI + BT combo) NGFF Half

Card Reader Realtek RTS5220-GR

I/O Board

PCIE SSD (2242/2280) M.2 NGFF

SPI ROM (8MB) W25Q64FVSSIQ

Touch Pad

USB2.0 x6

PCIe x6

x4

SPI

I2C x1

REV：2.A

FAB: JB501

I2C (SPI)

HDA

SATA x1

3 3

CH-A DDR4 SODIMM/LPDIMM x1

Type-C Connector (CC+MUX)

USB3.0 repeater Periom PI3EQX7502A

USB3.0 Connector

USB3.0 Connector Alpine I/O Board

USB Charger TI TPS2546RTER

USB 2.0 Connector

Cruze I/O Board

Camera

Blue Tooth (WIFI + BT combo) NGFF Half

Finger Printer (Option)

Touch Panel

Audio Codec Realtek ALC3240

Int. Speaker

Int. Array Mic x2

Combo Jack

HDD Conn.

LPC

Alpine Sub-borad

I/O Board

Sensor Board (G sensor)

4 4

A

Cruze Sub-borad

I/O Board

EC

Nuvoton NPCE388NB0DX

I2C x1

Int. KBD

B

G Sensor x1 (For Alpine)

C

I2C x1

G Sensor x1 (For Alpine)

Hall sensor x1 (For Cruze)

Hall sensor x2 (For Alpine)

I/O Board

Sensor Board

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT B E TRANSFERED FROM T HE CUSTODY OF THE COMPE TENT DIVISION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT B E TRANSFERED FROM T HE CUSTODY OF THE COMPE TENT DIVISION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT B E TRANSFERED FROM T HE CUSTODY OF THE COMPE TENT DIVISION OF R& D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORMATION IT CONTAINS MAYB E USED BY OR DISCLOSED T O ANY THIRD PARTY WIT HOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS , INC.

MAYB E USED BY OR DISCLOSED T O ANY THIRD PARTY WIT HOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS , INC.

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet of

Cover Page

Document Number Re v

LA-E541P

E

2 51Wednesday, June 21, 2017

2.A

1

Voltage Rails

power plane

+5VALW

B+

A A

State

S0

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

B B

+3VALW

O

X

EC SM Bus1 address

Device

Smart Battery

Address

0001 011x 16h

+1.2V

O O

O

X

EC SM Bus2 address

Device

NCT7718W

PCH SM Bus address

Device

DDR_JDI MM1 Touch Pad

Address

1010 000x A0h

+5VS

+3VS

+1.35V S

+VCC_COR E

+VGA_COR E

+VCC_GFX CORE_AXG

+1.8VS

+0.6VS

+1.0VAL W

X

XX

X

XXX

Address

1001 100x 98h

GPU SM Bus address

Device

Internal thermal sensor

SMBUS Control Table

VGA

C C

D D

SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 SMB_EC_CK4 SMB_EC_DA4 PCH_SMBCLK PCH_SMBDATA SML0CLK SML0DATA SML1CLK SML1DATA

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SOURCE

NECP38 8

+3VALW

NECP38 8

+3VS

NECP38 8

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

SIGNAL

1

V

+3VGS

X X X X X X X X X

X

SLP_S1 #

LOW

LOW LOW LOW

CHARGER

VX X

+19V_V IN

+3VALW

X

V

V X

X

+3VS

X

XX

X

SLP_S4 #SLP_S3 # +V+VAL WSLP_S5 # Clock+VS

HIGHHIGHHIGH

HIGH HIGH HIGH

LOW

HIGH

LOWLOW

X

V

+3VS

HIGH

LOWLOW

2

BOM Structure Table

For DIS DIS@ For UMA UMA@ For T ouch Pan el with SPI TS_SP I@ For T ouch Pan el with I2C TS_I2 C@ For Keyboard backlight KBL@

For Samsung VRAM For Micron VRAM For Hynix VRAM For UHD Pa nel UHD@ For Finger Printer FP@ For SSD SSD@

For ESD ESD@ For R F RF@

No ES D No RF @RF@ Conne ctor ME@ For V ARM X76 X76@ For Test Point TP@ For Debug @DCI@

For S IMR series only S_IMR @ For YOGA s eries only

For C PU Type

EC SM Bus4 address

Device

BMA250E

Address

1001 111x 9Eh

Thermal

SODIMMNECP388BATT

Sensor

X

V

+3VS

XX

X

ONONON

ON

OFF

ON

OFF

2

Item

Address

0001 100X 18h

DGPU TP

X

V

+3VS

X

V

X

+3VS

ONON

ON

LOW

OFF

3

4

5

USB 2.0 Port Table

BOM Structure

NOKBL @No K eyboard backlight S2G@ M2G@ H2G@

EMI@For EMI

@EMI@No EM I @ESD@

Item

For K BL U22 CPU

For K BL U42 CPU

For G PU Type

For EMI

For Thermal sensor EX_TH M@

BOM Structure

U22@

U42@ N16S_ R1@ N16S_ R3@ N16V_ R1@ N16V_ R3@

U22_E MI@ U42_E MI@

FP_ES D@For ESD

Port

1 2 3 4 5 6 7

USB 3.0 Port Table

Port

1 2 3 4 5 6

SATA Port Table

Port

S_AL@For S series only

YOGA@ i7_750 0U_R1@ i5_720 0U_R1@ i3_710 0U_R1@ i7_750 0U_R3@ i5_720 0U_R3@ i3_710 0U_R3@ pt_441 5U_R1@ pt_441 5U_R3@ i3_600 6U_R3@

0 1

X4E

Yoga Series S Series

ZZZ4

X4E Y Series

X4EA5R38LA1

Yoga Series (U42)

G-

PCH

SENSOR

X

V

+3VS

X

V

+3VS

X

V

+3VS

X

V

X

+3VS

X

GPU part

UV1

N16S_R1@

N16S-GTR-S-A2 BGA 595P

SA00009FP00

UV1

N16S_R3@

N16S-GTR-S-A2 BGA 595P

SA00009FP30

UV1

N16V_R1@

N16V-GMR1-S-A2 BGA 595P

SA00009IT00

UV1

N16V_R3@

N16V-GMR1-S-A2 BGA 595P

SA00009IT30

3

ZZZ

X4E Y Series

X4EA5R38LL2

GDDR5 VRAM * 2

UV6

K4G80325FB-HC03

SA000094R20

CPU part

KBL U22 (= U22@)

UC1

QLYK H0 2.4G

SA0000A38A0

UC1

SR343 H0 2.4G

SA0000A38B0

ZZZ3

X4E_YA@

X4E_U42_YA@

S2G@

i3_7100U_R1@

i3_7100U_R3@

X4E_YA_FP@

X4E Y Series FP SKU

X4EA5R38LA2

ZZZ

X4E_U42_YA_FP@ ZZZ1

X4E Y Series FP SKU

X4EA5R38LL1

UV7

K4G80325FB-HC03

SA000094R20

RV65

SD034499180

4.99K_0402_1%

S2G@

UC1

i5_7200U_R1@

QLYJ H0 2.5G

SA0000A37A0

UC1

i5_7200U_R3@

SR342 H0 2.5G

SA0000A37B0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT B E TRANSFERED FROM T HE CUSTODY OF THE COMPE TENT DIVISION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT B E TRANSFERED FROM T HE CUSTODY OF THE COMPE TENT DIVISION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT B E TRANSFERED FROM T HE CUSTODY OF THE COMPE TENT DIVISION OF R& D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORMATION IT CONTAINS MAYB E USED BY OR DISCLOSED T O ANY THIRD PARTY WIT HOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS , INC.

MAYB E USED BY OR DISCLOSED T O ANY THIRD PARTY WIT HOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS , INC.

S2G@

ZZZ5

X4E_YB@

X4E Y Series UHD SKU

X4EA5R38LE2

X4E_U42_YB@

X4E Y Series UHD SKU

X4EA5R38LO2

UV6

MT51J256M32HF

SA000096K20

UC1

i7_7500U_R1@

QLYH H0 2.7G

SA0000A3490

UC1

i7_7500U_R3@

SR341 H0 2.7G

SA0000A34A0

2017/06/05 2018/06/05

ZZZ6

X4E Y Series UHD&FP SKU

X4EA5R38LE1

ZZZ2

X4E Y Series UHD&FP SKU

X4EA5R38LO1

M2G@

RV65

UC1

pt_4415U_R1@

QLYM H0 2.3G

SA0000ADV00

UC1

pt_4415U_R3@

SR348 H0 2.3G

SA0000ADV20

Compal Secret Data

4

Exter nal USB Port

USB3 Type-C Port USB2/3 Port (MB)

USB2/3 Port (IO/B)

USB3 Type-C Port Camera

Finger Printer (Option)

NGFF WLAN+BT

USB3 Type-C (MUX) USB2/3 Port (MB)

USB2/3 Port (IO/B)

HDD

X4E_YB_FP@

X4E_U42_YB_FP@

UV7

M2G@

MT51J256M32HF

SA000096K20

SD034100280

10K_0402_1%

M2G@

SKL U22 (= U22@)

UC1

i3_6006U_R3@

SR2JG K1 i3-6006U 2.0G C38!

SA0000ACN10

Deciphered Date

PCIE Port Table

Lane

10 11 12

X4E_S@

X4E_U42_S@

H2G@

ZZZ7

X4E S Series FP SKU

X4EA5R38L02

ZZZ

X4E S Series FP SKU

X4EA5R38LR2

RV65

SD034301280

30.1K_0402_1%

H2G@

ZZZ8

X4E S Series

X4EA5R38L01

S Series (U42)

ZZZ

X4E S Series

X4EA5R38LR1

X7671138L01X7671138L03 X7671138L02

UV6

H5GC8H24MJR-T2C

SA00009ZG10

Port

1 2

1

3 4 5 6 7 8 9

X4E_S_FP@

X4E_U42_S_FP@

UV7

H5GC8H24MJR-T2C

SA00009ZG10

KBL U42 (= U42@)

UC1

QNEF Y0 1.6G FCBGA

SA0000AWB00

UC1

QNEF Y0 1.6G FCBGA

SA0000AWB50

GPU

Card Reader NGFF WLAN+BT

3

SSD

HDMI Logo

ZZZ

45@

HDMI Logo

RO0000003HM

PCB part

ZZZ

YOGA@

PCB Y Series

DA80019S02A

ZZZ

S_AL@

PCB S Series

H2G@

i5_QNEF_R1@

i5_QNEF_R3@

Title

Notes List

Size

Document Number Re v

Custom

Date : Sheet of

DA80019S12A

ZZZ

S_IMR@

PCB S Series

DA80019S12A

UC1

i7_QNBF_R1@

QNBF Y0 1.8G FCBGA

SA0000AWC00

UC1

i7_QNBF_R3@

QNBF Y0 1.8G FCBGA

SA0000AWC50

Compal Electronics, Inc.

LA-E541P

5

2.A

3 51Wednesday, June 21, 2017

2.A

5

4

3

2

1

-PowerMap_KBL_DDR4_Volume_NON CS]

B+

D D

C C

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELEC TRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELEC TRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELEC TRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

2017/06/05 2018/06/05

Deciphered Date

Compal Electronics, Inc.

Title

Power MAP

Size Document Number Re v

Size Document Number Rev

LA-C071P

Date: Sheet

1

4 51Wednesday, June 21, 2017

of

2.A

5

4

3

2

1

G3->S0 S0->S3 ->S0

+3VL_RTC

SOC_RTCRST#

B+

D D

+3VLP/+5V LP

EC_ON

+5VALW/+3VALW/+3VALW _DSW

PM_BATLOW#

tPCH01_Min : 9 ms

tPCH04_Min : 9 ms

Pull-up to DSW well if not implemented.

/DS3 DS3S0/

PCH_PWR_EN (SLP_SUS#)

+3V_PRIM

+1.8V_PRIM

EXT_PWR_GATE#

+1.0V_MPHYPLL

+1.0V_PRIM_CORE

+1.0V_PRIM

tPCH06_Min : 200 us

SUSACK#

PCH_DPWROK

EC_RSMRST#

C C

AC_PRESENT

tPCH34_Max : 20 ms

tPCH02_Min : 10 ms

tPCH03_Min : 10 ms

tPLT02_Min : 0 ms Max : 90 ms

ON/OFF

PBTN_OUT#

Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

PM_SLP_S5#

ESPI_RST#

If EXT_PWR_GATE# Toffmin is too small, Pwr gate may choose to completely ignore it

tPCH43_Min : 95 ms

tPCH18_Min : 90 us

PM_SLP_S4#

SYSON

+1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC

PM_SLP_S3#

SUSP#

+1.0VS_VCCSTG

+1.0VS_VCCIO

B B

+5VS/+3VS/+1.5VS /+1.05VS

EC_VCCST_PG

VR_ON

SM_PG_CTRL

+0.675VS_VTT

+VCC_SA

tCPU04 Min : 100 ns

tCPU10 Min : 1 ms

T <=10msec

T = 10msec

tCPU19 Max : 100 ns

tCPU18 Max : 35 us

tCPU09 Min : 1 ms

+VCC_CORE

+VCC_GT

VR_PWRGD

PCH_PWROK

tCPU16 Min : 0 ns

H_CPUPWRGD

SYS_PWROK

A A

SUS_STAT#

SOC_PLTRST#

S0->S5

+3VL_RTC

SOC_RTCRST#

B+

+3VLP/+5V LP

EC_ON

+5VALW/+3VALW/+3VALW _DSW

PM_BATLOW#

PCH_PWR_EN (SLP_SUS#)

+3V_PRIM

+1.8V_PRIM

EXT_PWR_GATE#

+1.0V_MPHYPLL

+1.0V_PRIM_CORE

+1.0V_PRIM

SUSACK#

PCH_DPWROK

EC_RSMRST#

AC_PRESENT

ON/OFF

PBTN_OUT#

PM_SLP_S5#

ESPI_RST#

PM_SLP_S4#

SYSON

+1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC

PM_SLP_S3#

SUSP#

+1.0VS_VCCSTG

+1.0VS_VCCIO

+5VS/+3VS/+1.5VS /+1.05VS

EC_VCCST_PG

VR_ON

SM_PG_CTRL

+0.675VS_VTT

+VCC_SA

+VCC_CORE

+VCC_GT

VR_PWRGD

PCH_PWROK

H_CPUPWRGD

SYS_PWROK

SUS_STAT#

SOC_PLTRST#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

2017/06/05 2018/06/05

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Power Sequence

1

of

5 51Wednesday, J une 21, 2017

2.A

A

1 1

<HDMI>

HDMI DDC (Port C)

2 2

B

UC1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

HDMI_TX2-_CK<27> HDMI_TX2+_CK<27> HDMI_TX1-_CK<27> HDMI_TX1+_CK<27> HDMI_TX0-_CK<27> HDMI_TX0+_CK<27> HDMI_CLK-_CK<2 7> HDMI_CLK+_CK< 27>

HDMICLK_NB<27> HDMIDAT_NB<27>

TS_I2C_RST#<26>

EDP_COMP

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22

N12

GPP_E23

E52

EDP_RCOMP

SKL-U_BGA1356

C

DDI

DISPLAY SIDEBANDS

SKL-U

1 OF 20

EDP

Rev_1.0

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP

RSVD RSVD

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

D

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52

G50 F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

@

EDP_TXN0 <26> EDP_TXP0 <26> EDP_TXN1 <26> EDP_TXP1 <26> EDP_TXN2 <26> EDP_TXP2 <26> EDP_TXN3 <26> EDP_TXP3 <26>

EDP_AUXN <26> EDP_AUXP <26>

TMDS_B_HPD <27>

EC_SCI# <10,32>

EDP_HPD <26>

ENBKL <26,32> INVPWM <26> PCH_ENVDD <26>

<eDP>

From HDMI

From eDP

E

< Compensation PU For eDP >

+1.0VS_VCCIO

EDP_COMP

1 2

RC3 24.9_0402_1 %

Trace width=20 mils, Spacing=25mil, Max length=100mils

+1.0V_VCCST

H_THERMT RIP#

1 2

RC5 1K_0402_5%

3 3

H_PROCHOT#<32>

+1.0VS_VCCIO

12

RC4 1K_0402_5%

1 2

RC6 499_0402_ 1%

RC7 49.9_0402_1 % RC8 49.9_0402_1 % RC9 49.9_0402_1 %@ RC10 49.9_0 402_1%@

If routed MS, PECI requires 18 mils spacing to other signals

T99 TP@

H_PECI< 32>

T100 T P@

T103 T P@ T105 T P@ T107 T P@ T109 T P@

TS_INT#<26>

12 12 12 12

SOC_CATERR# H_PECI H_PROCHOT# _R H_THERMT RIP# SOC_OCC#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3

CPU_POPIRCOMP PCH_OPIRCOMP EDRAM_OPIO_RCOMP EOPIO_RCOMP

UC1D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKL-U_BGA1356 @

SKL-U

CPU MISC

4 OF 20

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

Rev_1.0

JTAGX

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

CPU_XDP_TCK 0 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST #

PCH_JTAG_TC K1 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST # CPU_XDP_TCK 0

T116 TP@

< PU/PD for CMC Debug >

SOC_XDP_TMS

SOC_XDP_TDI

SOC_XDP_TDO

CPU_XDP_TCK 0

PCH_JTAG_TC K1

SOC_XDP_TRST #

RC11 51_0402_5 %@

RC12 51_0402_5 %@

RC13 51_0402_5 %@DCI@

RC14 51_0402_5 %@DCI@

RC15 51_0402_5 %@

RC23 51_0402_5 %@

+1.0VS_VCCIO

1 2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

SKL-U(1/12)DDI,EDP,MISC,CMC

Custom

LA-E541P

E

2.A

6 51Wednesday, June 21, 2 017

2.A

5

4

3

2

1

Interleaved Memory

D D

DDR_A_D[0..15]<18>

DDR_A_D[16..31 ]<1 8>

C C

DDR_A_D[32..47 ]<1 8>

DDR_A_D[48..63 ]<1 8>

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

UC1B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

Interleave / Non-Interleaved

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKL-U_BGA1356 @

SKL-U

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR3L / LPDDR3 / DDR4

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

Interleave / Non-Interleaved

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

2 OF 20

DDR0_ALERT#

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

Rev_1.0

DDR0_MA[3] DDR0_MA[4]

DDR0_PAR

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54 AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50

BA50 BB52 AM70 AM69 AT69 AT70

BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26

AW50 AT52

AY67 AY68 BA67

AW67

DDR_A_CLK#0 DDR_A_CLK0 DDR_A_CLK#1 DDR_A_CLK1

DDR_A_CKE0 DDR_A_CKE1

DDR_A_CS#0 DDR_A_CS#1 DDR_A_ODT0 DDR_A_ODT1

DDR_A_MA5 DDR_A_MA9 DDR_A_MA6 DDR_A_MA8 DDR_A_MA7 DDR_A_BG0 DDR_A_MA12 DDR_A_MA11

DDR_A_MA13 DDR_A_MA15 DDR_A_MA14 DDR_A_MA16 DDR_A_BA0 DDR_A_MA2 DDR_A_BA1 DDR_A_MA10 DDR_A_MA1 DDR_A_MA0

DDR_A_MA3 DDR_A_MA4 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1

DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7

DDR_PG_CT RL

T119TP@ T118TP@

DDR_A_CLK#0 <18> DDR_A_CLK0 <18> DDR_A_CLK#1 <18> DDR_A_CLK1 <18>

DDR_A_CKE0 <18> DDR_A_CKE1 <18>

DDR_A_CS#0 <18> DDR_A_CS#1 <18> DDR_A_ODT0 <18> DDR_A_ODT1 <18>

DDR_A_MA5 <18> DDR_A_MA9 <18> DDR_A_MA6 <18> DDR_A_MA8 <18> DDR_A_MA7 <18> DDR_A_BG0 <1 8> DDR_A_MA12 <18> DDR_A_MA11 <18> M_A_ACT# <18> DDR_A_BG1 <1 8> DDR_A_MA13 <18> DDR_A_MA15 <18> DDR_A_MA14 <18> DDR_A_MA16 <18> DDR_A_BA0 <1 8> DDR_A_MA2 <18> DDR_A_BA1 <1 8> DDR_A_MA10 <18> DDR_A_MA1 <18> DDR_A_MA0 <18>

DDR_A_MA3 <18> DDR_A_MA4 <18> DDR_A_DQS#0 <18> DDR_A_DQS0 <18> DDR_A_DQS#1 <18> DDR_A_DQS1 <18>

DDR_A_DQS#2 <18> DDR_A_DQS2 <18> DDR_A_DQS#3 <18> DDR_A_DQS3 <18> DDR_A_DQS#4 <18> DDR_A_DQS4 <18> DDR_A_DQS#5 <18> DDR_A_DQS5 <18> DDR_A_DQS#6 <18> DDR_A_DQS6 <18> DDR_A_DQS#7 <18> DDR_A_DQS7 <18>

DDR_A_ALERT# <18> DDR_A_PARITY <1 8>

+0.6V_VREFCA <18> +0.6V_A_VREFDQ <18>

Trace width/Spacing >= 20mils

UC1C

Interleave / Non-Interleaved

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKL-U_BGA1356 @

SKL-U

DDR3L / LPDDR3 / DDR4

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

Interleave / Non-Interleaved

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

3 OF 20

Rev_1.0

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52 BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46

BB46 BA47

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32

AR25 AR27 AR22 AR21 AN43 AP43 AT13 AR18 AT18 AU18

DDR_DRAMRST #

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

T123TP@

DDR_DRAMRST # <18>

1 2

RC16 121_040 2_1%

1 2

RC17 80.6_040 2_1%

1 2

RC18 100_040 2_1%

+1.2V

@

12

CC101 0.1U_0201_10V6K

UC7

DDR_PG_CT RL

A A

5

NC1VCC

2

A

3

GND

74AUP1G07GW _TSSOP5

SA00007WE0 0

+3VS

12

5

RC54 220K_0402_ 5%

4

Y

12

RC19 2M_0402_5 %

@

4

DDR_VTT_PG_ CTRL <42>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

DDR_DRAMRST #

2

+1.2V

12

RC20 470_0402_ 5%

1

CC96 100P_0402_ 50V8J

ESD@

2

Close to CPU

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

SKL-U(2/12)DDR3L

LA-E541P

Wednesday, June 21, 2 017

LA-E541P

1

2.A

51

7

5

4

3

2

1

SML0ALERT# (Internal Pull Down):

eSPI or LPC

0 = LPC is selected for EC ==> Default

D D

+3VALW

1 2

RC21 1K_0402_5%@

1 2

RC22 1K_0402_5%@

1 2

RC24 1K_0402_5%@

SOC_SPI_IO2

SOC_SPI_IO3

1 = eSPI is selected for EC

SOC_SML0CLK SOC_SML0DATA

RPC12

1 8 2 7 3 6 4 5

499_0804_ 8P4R_1%

+3VS

UC1E

+3VS

1 2

RC112 10K_0402 _5%

+1.8VS_3VS_PGPPA

1 2

RC25 8.2K_0402_5 %

C C

KB_RST#

SERIRQ

TS_SPI_CLK<2 6>

TS_SPI_SO<26> TS_SPI_SI<26>

TS_SPI_CS#0<26>

SERIRQ<32>

SOC_SPI_CLK SOC_SPI_SO SOC_SPI_SI SOC_SPI_IO2 SOC_SPI_IO3 SOC_SPI_CS#0

TS_SPI_CLK TS_SPI_SO TS_SPI_SI

TS_SPI_CS#0

SERIRQ

AW13

AY11

SPI - FLASH

AV2

SPI0_CLK

AW3

SPI0_MISO

AV3

SPI0_MOSI

AW2

SPI0_IO2

AU4

SPI0_IO3

AU3

SPI0_CS0#

AU2

SPI0_CS1#

AU1

SPI0_CS2#

SPI - TOUCH

M2

GPP_D1/SPI1_CLK

M3

GPP_D2/SPI1_MISO

J4

GPP_D3/SPI1_MOSI

V1

GPP_D21/SPI1_IO2

V2

GPP_D22/SPI1_IO3

M1

GPP_D0/SPI1_CS#

C LINK

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

SKL-U_BGA1356 @

SKL-U

SMBUS, SMLINK

LPC

GPP_A14/SUS_STAT#/ESPI_RESET#

5 OF 20

Rev_1.0

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

R7 R8 R10

R9 W2 W1

W3 V3 AM7

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9 AW11

PCH_SMB_CL K PCH_SMB_DATA SOC_SMBALERT#

SOC_SML0CLK SOC_SML0DATA SOC_SML0ALERT #

SOC_SML1ALERT #

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME#

LPC_CLK0

PM_CLKRUN#KB_RST#

T124TP@

T125TP@

1 2

RC26 22_04 02_5%EMI@

PCH_SMB_CL K <18>

PCH_SMB_DATA <18 >

EC_SMB_CK2 <22,32,36 > EC_SMB_DA2 <22,32,36 >

LPC_AD0 <32> LPC_AD1 <32> LPC_AD2 <32> LPC_AD3 <32>

LPC_FRAME# <32>

SMB

(Link to DDR)

SML1

(Link to EC,DGPU,Thermal Sensor)

CLK_LPC_EC < 32>

SOC_SML1ALERT #

PCH_SMB_CL K PCH_SMB_DATA EC_SMB_CK2 EC_SMB_DA2

PM_CLKRUN#

RC113 150K_040 2_5%@

RC31 8.2K_04 02_5%@

Follow 543016_SKL_U_Y_PDG_0_9

1 2

RPC2

1 8 2 7 3 6 4 5

1K_0804_8P 4R_5%

1 2

+3VS

+1.8VS_3VS_PGPPA

RPC1, RPC3 and RC30 are close to UC3

SOC_SPI_SO SOC_SPI_CLK SOC_SPI_CLK_0_R SOC_SPI_SI

B B

From EC

From SOC

EC_SPI_CLK<32> EC_SPI_MOSI<32 > EC_SPI_CS0#<32>

EC_SPI_MISO<32 >

SOC_SPI_IO3

SOC_SPI_IO2

RPC1

SOC_SPI_SO_0_R

1 8 2 7

SOC_SPI_SI_0_R

3 6

SOC_SPI_IO3_0_R

4 5

33_0804_8 P4R_5%

EMI@

SOC_SPI_IO2_0_R

1 2

RC30 33_0402_5 %EMI@

RPC3

1 8 2 7 3 6 4 5

33_0804_8 P4R_5%

EMI@

SOC_SPI_CLK_0_ R

SOC_SPI_CS#0 SOC_SPI_SO_0_R

EC_SPICLK EC_MOSI SOC_SPI_SI_0_R EC_SPICS# EC_MISO

< SPI ROM - 8M >

SOC_SPI_CS#0

SOC_SPI_IO2_0_R

A A

5

UC3

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

W25Q64FVSSIQ_SO8

/HOLD(IO3)

DI(IO0)

+3VALW

CC2 0.1U_0201_10V K X5R

8

VCC

SOC_SPI_IO3_0_RSOC_SPI_SO_0_R

7

SOC_SPI_CLK_0_ R

6

CLK

SOC_SPI_SI_0_R

5

4

@

1 2

1

CC3 10P_0402_5 0V8J

2

@EMI@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

Compal Electronics, Inc.

SKL-U(3/12)SPI,SMB,LPC,ESPI

LA-E541P

1

8 51Wednesday, June 21, 2 017

2.A

5

D D

4

3

2

1

< HD AUDIO >

HDA_BITCLK_AUDIO<28> HDA_SYNC_AUDIO<28>

RPC4

1 8 2 7 3 6 4 5

33_0804_8 P4R_5%

EMI@

HDA_BIT_CLK HDA_SYNC

HDA_SDOUT

HDA_SYNC HDA_BIT_CLK

HDA_SDIN0<28>HDA_SDOUT_AUD IO< 28>

HDA_SDOUT

< To Enable ME Override >

1 2

C C

ME_EN<32>

RC116 0_0402_5%

+3VS

1 2

RC33 2.2K_0402_5%@

HDA_SDOUT

HDA_SPKR

HDA_SPKR<28>

HDA_SPKR

SPKR ( Internal Pull Down):

B B

TOP Swap Override

0 = Disable TOP Swap mode. ==> Default

1 = Enable TOP Swap Mode.

UC1G

BA22 AY22 BB22 BA21 AY21

AW22

AY20

AW20

AK10

AW5

AK7 AK6 AK9

AUDIO

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKL-U_BGA1356 @

UC1I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKL-U_BGA1356 @

SKL-U

9 OF 20

GPP_A17/SD_PWR_EN#/ISH_GP7

7 OF 20

Rev_1.0

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK GPP_F12/EMMC_CMD

EMMC_RCOMP

SDIO / SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

C37 D37 C32 D32 C29 D29 B26 A26

E13

RC80 100_0 402_1%@

B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

RC129 200_040 2_1%@

Rev_1.0

1 2

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

1 2

RC76 200_0 402_1%@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

SKL-U(4/12)HDA,EMMC,SDIO,CSI2

LA-E541P

Wednesday, June 21, 2 017

LA-E541P

1

51

9

2.A

5

4

3

2

SOC_XTAL24_IN XTAL24_IN

U22_EMI@

1 2

RC154 33_0402 _1%

1

SOC_XTAL24_OUT XTAL24_OUT

+3VS

D D

RPC5

CLKREQ_PCIE#4

18

CLKREQ_PCIE#5

27 36 45

10K_0804_8 P4R_5%

@

RPC6

CR_CLKREQ#

18

WLANCLK_R EQ#

27 36

SSDCLK_REQ#

45

10K_0804_8 P4R_5%

+3VS

RC134

1 2

+3VL_RTC

C C

+3VALW

B B

ESD@

+3VALW

RC47 1K_04 02_5%

VGA_CLKREQ#

10K_0402_5 %

1 2

RC36 20K_0 402_5%

1 2

CC6 1U_0402_6 .3V6K

1 2

RC37 20K_0 402_5%

1 2

CC7 1U_0402_6 .3V6K

1 2

CLRP2 SHORT PADS

1 2

RC39 1M_04 02_5%

RPC7

PCH_PWR OK

18

EC_RSMRST#

27 36

SYS_RESET#

45

10K_0804_8 P4R_5%

1 2

CC97 100P_0402_ 50V8J

1 2

CC94 100P_0402_ 50V8J

1 2

CC95 100P_0402_ 50V8J

1 2

SYS_RESET#

EC_RSMRST#

SYS_PWROK

WAKE#

EC_SCI# <6,32>

SOC_SRTCRS T#

SOC_RTCRST #

CLR CMOS

SM_INTRUDER#

Card Reader RTS5220

1 2

RC38 0_040 2_5%

Only For Power Sequence Debug

From EC (Open-Drain)

A A

5

VCCST_PWR GD<3 2>

DGPU

SSD

NGFF WL+BT

+1.0V_VCCST

12

EC_CLEAR_CMO S# <32>

RC52 1K_0402_5%

1

2

CLK_PEG_VGA#<19> CLK_PEG_VGA<19>

VGA_CLKREQ#<19>

CLK_PCIE_SSD#<31> CLK_PCIE_SSD<31> SSDCLK_REQ#< 31>

CLK_PCIE_WL AN#<30> CLK_PCIE_WL AN<30> WLANCLK_R EQ#<30>

CLK_PCIE_CR#<35> CLK_PCIE_CR<35>

CR_CLKREQ#<35 >

EC_RSMRST#<32>

T132 TP @

SYS_PWROK<3 2>

PCH_PWR OK<32>

1 2

RC53 60.4_0 402_1%

CC117 100P_0402_ 50V8J

ESD@

4

VGA_CLKREQ#

SSDCLK_REQ#

WLANCLK_R EQ#

CLKREQ_PCIE#4

CLKREQ_PCIE#5

< PCH PLTRST Buffer >

SOC_PLTRST #

SOC_PLTRST # SYS_RESET# EC_RSMRST#

H_CPUPW RGD EC_VCCST_PG

SYS_PWROK PCH_PWR OK EC_RSMRST#

WAKE#

EC_VCCST_PG

UC1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKL-U_BGA1356 @

1 2

RC42 0_0402_5%

+3VS

5

UC4

1

P

B

2

A

TC7SH08FU F_SSOP5

SA007080100

UC1K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKL-U_BGA1356 @

G

3

SYSTEM POWER MANAGEMENT

SKL-U

CLOCK SIGNALS

10 OF 20

@

4

Y

3

100P_0402_50V8J

100K_0402_5%

12

RC44

12

ESD@

CC8

SKL-U

GPP_B11/EXT_PWR_GATE#

11 OF 20

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev_1.0

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XCLK_BIASREF

PCI_RST# <19,30,31 ,32,35>

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

GPP_B2/VRALERT#

F43 E43

BA17

SUSCLK

SOC_XTAL24_IN

E37

XTAL24_IN

XTAL24_OUT

RTCX1 RTCX2

SRTCRST#

RTCRST#

Rev_1.0

SLP_SUS#

SLP_LAN#

INTRUDER#

2017/06/05 2018/06/05

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

AM10 AM11

E35

E42

AM18 AM20

AN18 AM16

SOC_XTAL24_OUT

XCLK_BIASREF

SOC_RTCX1 SOC_RTCX2

SOC_SRTCRS T# SOC_RTCRST #

PM_SLP_S0# PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#

SLP_WLAN# PM_SLP_A#

PBTN_OUT# AC_PRESENT PM_BATLOW#

SM_INTRUDER#

SOC_VRALERT#

Compal Secret Data

PM_SLP_S3# <32> PM_SLP_S4# <32,40,42>

1 2

RC103 0_0402_ 5%

Deciphered Date

SUSCLK <30>

T130TP@

T131TP@

T133TP@ T134TP@

2

U22_EMI@

1 2

RC155 33_0402 _1%

SOC_RTCX2

SOC_RTCX1

PBTN_OUT# <32>

EC_VCIN1_AC_BYPASS <22,32>

Custom

Date : Sheet of

U22@

1 2

RC34 1M_04 02_5%

U22@

YC1

24MHZ_18PF_XRC GB24M000F2P51R0

SJ10000UJ00

1

U22@

27P_0402_50V8J

1

CC4

2

XCLK_BIASREF

PM_BATLOW#

AC_PRESENT

SOC_VRALERT#

Title

SKL-U(5/12)CLK,PM,GPIO

Size Document Number Re v

1 2

RC35 2.7K_0402_1 %

1 2

RC110 60.4_0402 _1%@

1 2

RC41 10M_0402_5%

YC2

1 2

32.768KHZ_9P F_9H03280012

6.8P_0402_50V8C

1

2

Compal Electronics, Inc.

SJ10000Q400

CC9

1 2

RC46 8.2K_0402_5 %

1 2

RC48 10K_0402_5 %@

1 2

RC50 10K_0402_5 %@

LA-E541P

1

NC

2

NC

4

3

27P_0402_50V8J

1

2

+1.0V_CLK5_F2 4NS

10 51Wednesday, June 21, 2017

U22@

CC5

1

2

+3VALW

6.8P_0402_50V8C

CC10

2.A

5

4

3

2

1

GSPI0_MOSI (Internal Pu ll Down):

No Reboot

0 = Disable No Reboot mode. ==> Default

1 = Enable No Reboot Mode. (PCH will disable the TCO Timer system reboot feature). This funct i on is usef ul

D D

when running ITP/XDP.

+3VS

1 2

RC206 10K_0402 _5%@

1 2

RC205 10K_0402 _5%@

STORAGE_PRSNT 1

GSPI1_MOSI (Internal Pu ll Down):

Boot BIOS Strap Bit

1 2

RC208 10K_0402 _5%@

1 2

RC207 10K_0402 _5%@

STORAGE_PRSNT 2

0 = SPI Mode ==> Default

1 = LPC Mode

+3VS

1 2

RC59 4.7K_0402_5 %@

1 2

RC60 150K_0402_ 5%@

C C

+3VS

RPC10

1 8 2 7 3 6 4 5

49.9K_0804_ 8P4R_1%

RPC8

18 27 36 45

10K_0804_8 P4R_5%

RPC11

18 27 36 45

2.2K_0804_8 P4R_5%

+3VS

B B

+3VS

GSPI0_MOSI

GSPI1_MOSI

UART0_RX UART0_TX

DGPU_PWR _EN DGPU_HOLD_R ST#

WLBT_OFF#

I2C1_SCL_TS I2C1_SDA_TS I2C0_SCL_TP I2C0_SDA_TP

Touch PAD

Touch Panel

EC Sensor

UC1F

AN8

AH10

AH11 AH12

AF11 AF12

AP7 AP8 AR7

AM5 AN7 AP5 AN5

AB1 AB2

W4

AB3

AD1 AD2 AD3 AD4

U7 U6

U8 U9

AH9

SOC_GPIOB17 GSPI0_MOSI

SENSOR_EC_INT<32>

TP_INT#<33>

WLBT_OFF#<30>

UART0_RX<3 0>

UART0_TX<30>

I2C0_SDA_TP<33> I2C0_SCL_TP<33>

I2C1_SDA_TS<26> I2C1_SCL_TS<26>

I2C2_SDA_SEN<3 2> I2C2_SCL_SEN<32>

GSPI1_MOSI

SOC_GPIOC10

LPSS ISH

GPP_B15/GSPI0_CS# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL

SKL-U_BGA1356 @

SKL-U

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6

6 OF 20

Rev_1.0

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_D15/ISH_UART0_RTS#

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

P2 P3

STORAGE_PRSNT 2

P4

STORAGE_PRSNT 1

P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

DGPU_PWR _EN

AC1

DGPU_HOLD_R ST#

AC2

GPU_ALL_PGOOD

AC3

DGPU_PRSNT

AB4

MB_ID

AY8 BA8

DGPU_SEL

BB7 BA7 AY7 AW7

TP_PRSNT

AP13

DGPU_PWR _EN <24,32> DGPU_HOLD_R ST# <19> GPU_ALL_PGOOD <24>

Funct i on

DIS

UMA Only

+3VS

RC61 10K_0 402_5%UMA@

RC62 10K_0 402_5%DIS@

Funct i on

YOGA series

S series 1

+3VS

RC146 10K_0402 _5%S_AL@

RC147 10K_0402 _5%YOGA@

Funct i on

N16V-GRM1(920)

+3VS

RC210 10K_0402 _5%

RC209 10K_0402 _5%

1 2

N16S_R1@

1 2

N16V_R1@

1 2

DGPU_PRSNT (GPP_C1 5)

0

1

MB_ID

0

DGPU_SEL

0

1N16S-GTR-S(94 0)

DGPU_PRSNT

RC146 S_IMR@ 10K_0402_5 %

MB_ID

DGPU_SEL

RC210 N16S_R3 @ 10K_0402_5 %

RC209 N16V_R3@ 10K_0402_5 %

SOC_GPIOC10 GPU_ EVENT#

SOC_GPIOB17 GC6_FB_EN

A A

1 2

RC204 0_0402_ 5%

1 2

RC195 0_0402_ 5%

5

GPU_EVENT# <22>

GC6_FB_EN <2 2,23>

TO DGPU

+3VS

1 2

RC212 10K_0402 _5%@

1 2

RC211 10K_0402 _5%@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

SKL-U(6/12)GPIO,I2C,GSPI

TP_PRSNT

LA-E541P

1

2.A

11 51Wednesday, June 21, 2017

2.A

5

D D

4

3

2

1

UC1H

@

PCIE / USB3 / SATA

PCIE_PRX_DTX_N1<19> PCIE_PRX_DTX_P1<19>

PCIE_PTX_C_DRX_N 1<19> PCIE_PTX_C_DRX_P1<19>

PCIE_PRX_DTX_N2<19> PCIE_PRX_DTX_P2<19>

PCIE_PTX_C_DRX_N 2<19>

dGPU

C C

Card Reader

NGFF WLAN+BT

HDD

PCIE_PTX_C_DRX_P2<19>

PCIE_PRX_DTX_N3<19> PCIE_PRX_DTX_P3<19>

PCIE_PTX_C_DRX_N 3<19>

PCIE_PTX_C_DRX_P3<19>

PCIE_PRX_DTX_N4<19>

PCIE_PRX_DTX_P4<19> PCIE_PTX_C_DRX_N 4<19> PCIE_PTX_C_DRX_P4<19>

PCIE_PRX_DTX_N5<35> PCIE_PRX_DTX_P5<35> PCIE_PTX_C_DRX_N 5<35> PCIE_PTX_C_DRX_P5<35>

PCIE_PRX_DTX_N6<30> PCIE_PRX_DTX_P6<30> PCIE_PTX_C_DRX_N 6<30> PCIE_PTX_C_DRX_P6<30>

SATA_PRX_DTX_N0<29> SATA_PRX_DTX_P0<29> SATA_PTX_DRX_N0<29> SATA_PTX_DRX_P0<2 9>

PCIE_PRX_DTX_N9<31> PCIE_PRX_DTX_P9<31>

PCIE_PTX_C_DRX_N 9<31> PCIE_PTX_C_DRX_P9<31>

PCIE_PRX_DTX_N10<31>

PCIE_PRX_DTX_P10<31> PCIE_PTX_C_DRX_N 10<31> PCIE_PTX_C_DRX_P1 0<31>

SSD

B B

PCIE_PRX_DTX_N11<31> PCIE_PRX_DTX_P11<31>

PCIE_PTX_C_DRX_N 11<31>

PCIE_PTX_C_DRX_P1 1<31> PCIE_PRX_DTX_N12<31> PCIE_PRX_DTX_P12<31>

PCIE_PTX_C_DRX_N 12<31> PCIE_PTX_C_DRX_P1 2<31>

1 2

CC11 0.22U_0402 _6.3V6KDIS@

1 2

CC14 0.22U_0402 _6.3V6KDIS@

1 2

CC15 0.22U_0402 _6.3V6KDIS@

1 2

CC16 0.22U_0402 _6.3V6KDIS@

1 2

CC12 0.22U_0402 _6.3V6KDIS@

1 2

CC13 0.22U_0402 _6.3V6KDIS@

1 2

CC17 0.22U_0402 _6.3V6KDIS@

1 2

CC18 0.22U_0402 _6.3V6KDIS@

0.1U_0201_ 10V K X5R

1 2

CC19 CC20

CC102 CC103

CC110 0.22U_04 02_6.3V6KSSD@ CC109 0.22U_04 02_6.3V6KSSD@

CC114 0.22U_04 02_6.3V6KSSD@ CC113 0.22U_04 02_6.3V6KSSD@

CC116 0.22U_04 02_6.3V6KSSD@ CC115 0.22U_04 02_6.3V6KSSD@

CC112 0.22U_04 02_6.3V6KSSD@ CC111 0.22U_04 02_6.3V6KSSD@

0.1U_0201_ 10V K X5R

1 2

0.1U_0201_ 10V K X5R

1 2

0.1U_0201_ 10V K X5R

1 2

1 2 1 2

1 2

RC71 100_0 402_1%

1 2 1 2

T147 T P@ T148 T P@

PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3

PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4

PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5

PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6

PCIE_PTX_DRX_N9 PCIE_PTX_DRX_P9

PCIE_PTX_DRX_N10 PCIE_PTX_DRX_P10

PCIE_RCOMPN PCIE_RCOMPP

XDP_PRDY# XDP_PREQ#

PCIE_PTX_DRX_N11 PCIE_PTX_DRX_P11

PCIE_PTX_DRX_N12 PCIE_PTX_DRX_P12

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL-U_BGA1356

SKL-U

USB2

8 OF 20

SSIC / USB3

USB3_2_RXN / SSIC_RXN USB3_2_RXP / SSIC_RXP

USB3_2_TXN / SSIC_TXN USB3_2_TXP / SSIC_TXP

GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

Rev_1.0

USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_3_RXN USB3_3_RXP USB3_3_TXN USB3_3_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

USB2_VBUSSENSE

GPP_E9/USB2_OC0#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E8/SATALED#

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6 AG3 AG4

A9 C9 D9 B9

J1 J2 J3

H2 H3 G4

H1

USB20_N1 USB20_P1

USB20_N2 USB20_P2

USB20_N3 USB20_P3

USB20_N5 USB20_P5

USB20_N6 USB20_P6

USB20_N7 USB20_P7

USB2_COMP

RC70 113_0402_ 1% RC104 1K_0402_ 5% RC105 1K_0402_ 5%

USB_OC3#

USB3_RX1_N <34>

USB3_RX1_P <34>

USB3_TX1_N <34>

USB3_TX1_P <34>

USB3_RX2_N <35>

USB3_RX2_P <35>

USB3_TX2_N <35>

USB3_TX2_P <35>

USB3_RX3_N <35>

USB3_RX3_P <35>

USB3_TX3_N <35>

USB3_TX3_P <35>

USB20_N1 <34> USB20_P1 <34>

USB20_N2 <35> USB20_P2 <35>

USB20_N3 <35> USB20_P3 <35>

USB20_N5 <26> USB20_P5 <26>

USB20_N6 <29> USB20_P6 <29>

USB20_N7 <30> USB20_P7 <30>

1 2 1 2 1 2

USB_OC0# <34> USB_OC1# <35> USB_OC2# <35>

WL_OFF# <30>

USB3 Type-C (MUX)

USB2/3 Port (MB)

USB2/3 Port (IO/B)

USB3 Type-C Port

USB2/3 Port (MB)

USB2/3 Port (IO/B)

Cam era

Finger Printer

NGFF WLAN+BT

USB_OC1# USB_OC3# USB_OC0# USB_OC2#

WL_OFF#

10K_0804_8 P4R_5%

1 2

RC139 10K_0402 _5%@

RPC9

+3VALW

18 27 36 45

+3VS

When PCIE8/SATA1A is used as SATA Port 1 (ODD), then PCIE11/SATA1B (M.2 SSD) cannot be used as SATA Port 1.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(7/12)PCIE,USB,SATA

Size Document Number Re v

Custom

Date : Sheet of

2

Date : Sheet of

LA-E541P

1

12 51Wednesday, June 21, 2017

2.A

5

4

3

2

1

+1.2V

UC1N

@

+VL

+1.0VALW

1U_0402_6.3V6K

D D

+1.0VALW TO +1.0V_VCCST

SYSON<32,42>

SUSP#<3 2,37,42>

RC74 0_040 2_5%

RC75 0_040 2_5%

12

+1.8VALW TO +1.8VS

C C

+VL

0.1U_0201_10V K X5R

1

@

2

SUSP#

B B

RC81 0_040 2_5%

1U_0402_6.3V6K

CC21

1

2

+1.8VALW

I(Max) : 0.16 A(+1.0V_VCCST)

CC22

1

RON(Max) : 25 mohm V drop : 0.004 V

@

2

1

EN_1.0V_VCCSTU

EN_1.8VS

1U_0402_6.3V6K

1

@

2

3

4

5

6 7

EM5209VF DFN 14P D UAL LOAD SW

CC26

I(Max) : 0.2 A(+1.8VS) RON(Max) : 25 mohm V drop : 0.005 V

UC5

VIN1 VIN1

ON1

VBIAS

ON2

VIN2 VIN2

VOUT1 VOUT1

GND

VOUT2 VOUT2

GPAD

CT1

CT2

14 13

12

11

8200P_0402 _25V7K

10

9

1000P_0402 _50V7K

8

15

+1.0V_VCCST_R

RC136 0_0402_5%

1 2

CC24

1 2

CC25

+1.8VS_R

RC137 0_0402_ 5%

Follow 543977_SKL_PDDG_Rev0_91 CC24 10PF ->22us(Spec:<= 65us)

+1.0VALW TO +1.0VS_VCCIO

+1.0VALW

1U_0402_6.3V6K

CC30

1

2

12

I(Max) : 3.04 A(+1.0VS_VCCIO) RON(Max) : 6.2 mohm V drop : 0.019 V

CC32

UC6

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

AOZ1334DI-01_DFN 8 P

VOUT

GND

+1.0VS_VCCIO_STG

6

5

1 2

RC79 0_080 5_5%

12

+1.0VS_VCCIO

+1.0V_VCCST

1

2

+1.8VS

1

2

1

CC33

@

0.1U_0201_ 10V K X5R

2

0.1U_0201_10V K X5R

CC23

0.1U_0201_10V K X5R

CC27

+1.0VS_VCCIO

+1.0V_VCCST

AM40

SKL-U

VDDQ_AU23 VDDQ_AU28 VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51

VDDQC

VCCST

VCCSTG_A22

VCCPLL_OC

VCCPLL_K20 VCCPLL_K21

SKL-U_BGA1356

+1.0V_VCCST

CPU POWER 3 OF 4

VCCSA_SENSE

14 OF 20

1U_0402_6.3V6K

1

CC28

2

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE

1

2

AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51

AL23

A18

A22

K20 K21

Close to A18 Close to K20 Close to A22

1U_0402_6.3V6K

+1.0VS_VCCIO

Rev_1.0

AK28

VCCIO

AK30

VCCIO

AL30

VCCIO

AL42

VCCIO

AM28

VCCIO

AM30

VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

+VCCSA

VSSSA_SENSE VCCSA_SENSE

Trace Length Match < 25 mils

+1.0VS_VCCIO

CC34

VSSSA_SENSE <46> VCCSA_SENSE <46>

BSC SidePSC Side

1U_0402_6.3V6K

1

CC35

@

2

+1.0VS_VCCIO +1.2V

1U_0402_6.3V6K

10U_0603_6.3V6M

CC36

1

@

2

A A

5

4

1U_0402_6.3V6K

CC37

CC38

1

@

2

PSC SideBSC Side BSC SidePSC Side

1U_0402_6.3V6K

CC40

CC39

1

2

CC42

CC41

1

2

1U_0402_6.3V6K

1

2

BSC Side

CC29

1U_0402_6.3V6K

CC43

1

2

Close to CPUUnderneath CPU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/06/05 2018/06/05

22U_0603_6.3V6M

CC44

1

2

Close to CPUClose to AM40 Underneath CPUClose to AL23

Compal Secret Data

10U_0603_6.3V6M

CC45

CC46

1

2

Deciphered Date

2

10U_0603_6.3V6M

CC47

CC48

1

@

2

@

2

1U_0402_6.3V6K

CC50

CC49

1

@

2

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

SKL-U(8/12)Power

LA-E541P

1

2.A

13 51Wednesday, June 21, 2017

2.A

5

4

3

2

1

D D

1 2

22U_0603_6.3V6M

CC72

1

@

2

CC51 1U_0402_6 .3V6K

@

1 2

CC54 1U_0402_6 .3V6K

Imax : 2.57A

@

1 2

CC55 1U_0402_6 .3V6K

1 2

CC56 1U_0402_6 .3V6K

Close to K17

1 2

CC60 22U_0603_ 6.3V6M

Imax : 1.54A

@

1 2

CC61 1U_0402_6 .3V6K

Close to P15

+1.0V_AMPHYPLL

+1.0V_APLL

+3VALW

+3V_1.8V_HDA

1 2

CC65 1U_0402_6 .3V6K

@

Close to AF20

1 2

CC67 1U_0402_6 .3V6K

@

Close to AJ21

1 2

CC68 1U_0402_6 .3V6K

Close to N18

22U_0603_6.3V6M

CC73

CC74

1

@

2

Follow 543016_SKL_U_Y_PDG_1_0

+1.0VALW

LC1

MURATA BLM15EG22 1SN1D

1 2

RF@

SM01000HC0 0

R_0402

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC148 0_0603_ 5%

C C

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC85 0_060 3_5%

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC87 0_060 3_5%

B B

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC91 0_060 3_5%

1U_0402_6.3V6K

1

@

2

+1.0V_APLL

2

1

+1.0V_AMPHYPLL

22U_0603_6.3V6M

CC58

1

@

2

+1.0V_CLK5_F2 4NS

22U_0603_6.3V6M

CC63

1

@

2

+1.0V_CLK4_F1 00OC

22U_0603_6.3V6M

CC69

1

@

2

+1.0V_CLK6_24 TBT

1U_0402_6.3V6K

CC84

CC83

1

@

2

0.1U_0201_10V K X5R

CC31

RF@

1U_0402_6.3V6K

CC59

22U_0603_6.3V6M

CC64

22U_0603_6.3V6M

CC70

22U_0603_6.3V6M

CC85

1

@

2

+3VALW

22U_0603_6.3V6M

CC86

LC2

MURATA BLM15EG22 1SN1D

1 2

SM01000HC0 0

R_0402

+3VS

LPC 3.3V

1 2

RC93 0_0402_5%

+3V_1.8V_HDA

RF@

+1.8VS_3VS_PGPPA

0.1U_0201_10V K X5R

CC66

1

2

+1.0VALW +3VALW +1.8VALW

22U_0603_6.3V6M

CC71

1

@

2

+1.0VALW

DCPDSW

UC1O

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB_1P0

SKL-U_BGA1356

@

SKL-U

CPU POWER 4 OF 4

15 OF 20

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE VCCPGPPF VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

Rev_1.0

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

+1.8VALW

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19

T1

AA1

AK17

AK19 BB14

BB10

A14

K19

L21

N20

L19

A10

AN11 AN13

+3VALW

DCPRTC

VCCPGPPF support 1.8V only

+1.0VALW

1 2

CC57 1U_0402 _6.3V6K

+3VL_RTC

1 2

CC62 0.1U_0201 _10V K X5R

+1.0V_CLK6_24 TBT

+1.0V_APLL

+1.0V_CLK4_F1 00OC

+1.0V_CLK5_F2 4NS

+1.0V_CLK6_24 TBT

RTC Battery

22U_0603_6.3V6M

CC76

CC75

1

@

2

+3VALW

@

1U_0402_6.3V6K

1

2

CC77

CC80

@

2

1U_0402_6.3V6K

1

CC78

2

1

CC81

2

1U_0402_6.3V6K

Close to AK17Close to T16Close to Y16Close to AG15

+3VL_RTC +RTCBAT T

W=20mil s

1 2

0.1U_0201_10V K X5R

CC79

RC90 0_040 2_5%

1

CC82 1U_0402_6 .3V6K

2

Safty suggestion remove EE side, Keep PWR side

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(9/12)Power

Size Document Number Re v

Custom

Date : Sheet of

2

Date : Sheet of

LA-E541P

14 51Wednesday, June 21, 2017

1

14 51Wednesday, June 21, 2017

2.A

5

4

3

2

1

U22/U42 co-lay

+VCCGT_VCCCOR E

D D

R418

U42@

2

112

SOLDER_PREFOR MS_0603

R414

U42@

2

112

SOLDER_PREFOR MS_0603

R419

U22@

2

112

SOLDER_PREFOR MS_0603

+VCCCORE

+VCCGT

+VCCGT +VCCGT

+VCCGT_VCCCOR E

+VCCCORE +VCCCORE

C C

T157 T P@ T158 T P@

B B

VCCOPC_SENSE VSSOPC_SENSE

AK33 AK35 AK37 AK38 AK40

AL33 AL37

AL40 AM32 AM33 AM35 AM37 AM38

AK32

AB62

AC63 AE63

AE62 AG62

AL63

AJ62

A30 A34 A39 A44

G30

K32

P62 V62

H63

G61

UC1L

VCC_A30 VCC_A34 VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RSVD

VCCOPC_AB62 VCCOPC_P62 VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE VSSOPC_SENSE

VCCEOPIO VCCEOPIO

VCCEOPIO_SENSE VSSEOPIO_SENSE

SKL-U_BGA1356

@

SKL-U

CPU POWER 1 OF 4

12 OF 20

Rev_1.0

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VCC_SENSE VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

SOC_SVID_ALERT#

B63

VR_SVID_CLK

A63

VR_SVID_DATA

D64

G20

ALERT signal must be routed between CLK and DATA signals

Trace Length Match < 25 mils

VCCCORE_SENSE <4 6> VSSCORE_SENSE <46>

VR_SVID_CLK <46>

+1.0VS_VCCIO

VCCGT_SENSE<46> VSSGT_SENSE<46>

1 2

R416 0_0603_5%U22@

VCCGT_SENSE VSSGT_SENSE

+VCCGT_K52

Trace Length Match < 25 mils

SVID ALERT

+1.0V_VCCST

Place the PU resistors close to CPU

12

RC94 56_0402_5 %

AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71

A48 A53 A58 A62 A66

J43 J45 J46 J48 J50 J52 J53 J55 J56 J58 J60 K48 K50 K52 K53 K55 K56 K58 K60 L62 L63 L64 L65 L66 L67 L68 L69 L70 L71

M62

N63 N64 N66 N67 N69

J70 J69

UC1M

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT_SENSE VSSGT_SENSE

SKL-U_BGA1356

@

SKL-U

CPU POWER 2 OF 4

13 OF 20

Rev_1.0

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70 VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56 VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63 VCCGTX_BB57 VCCGTX_BB66

VCCGTX_SENSE

VSSGTX_SENSE

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

1 2

R417 0_0 402_5%U22@

VCCGTX_SENSE VSSGTX_SENSE

+VCCGT_VCCCOR E

T161 TP @ T162 TP @

+VCCGT

SOC_SVID_ALERT#

SVID DATA

A A

VR_SVID_DATA

1 2

RC95 220 _0402_5%

5

+1.0V_VCCST

Place the PU resistors close to CPU

12

RC96 100_0402_ 1%

VR_ALERT# <46>

VR_SVID_DATA <46>

(To VR)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(10/12)Power,SVID

Size Document Number Re v

Custom

Date : Sheet of

2

Date : Sheet of

LA-E541P

1

15 51Wednesday, June 21, 2017

2.A

5

D D

SKL-U

UC1P

A5

VSS

A67

VSS

A70

VSS

AA2

VSS

AA4

VSS

AA65

VSS

AA68

VSS

AB15

VSS

AB16

VSS

AB18

VSS

AB21

VSS

AB8

VSS

AD13

VSS

AD16

VSS

AD19

VSS

AD20

VSS

AD21

VSS

AD62

VSS

AD8

VSS

AE64

VSS

AE65

VSS

AE66

VSS

AE67

C C

B B

AE68 AE69

AF10 AF15 AF17

AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13

AH63 AH64 AH67

AJ15

AJ18

AJ20

AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69

AL28

AL32

AL35

AL38

AL45

AL48

AL52

AL55

AL58

AL64

AF1

AF2 AF4

AH6

AJ4

AK8 AL2

AL4

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-U_BGA1356

@

GND 1 OF 3

16 OF 20

Rev_1.0

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

4

UC1Q

AT63

VSS

AT68

VSS

AT71

VSS

AU10

VSS

AU15

VSS

AU20

VSS

AU32

VSS

AU38

VSS

AV1

VSS

AV68

VSS

AV69

VSS

AV70

VSS

AV71

VSS

AW10

VSS

AW12

VSS

AW14

VSS

AW16

VSS

AW18

VSS

AW21

VSS

AW23

VSS

AW26

VSS

AW28

VSS

AW30

VSS

AW32

VSS

AW34

VSS

AW36

VSS

AW38

VSS

AW41

VSS

AW43

VSS

AW45

VSS

AW47

VSS

AW49

VSS

AW51

VSS

AW53

VSS

AW55

VSS

AW57

VSS

AW6

VSS

AW60

VSS

AW62

VSS

AW64

VSS

AW66

VSS

AW8

VSS

AY66

VSS

B10

VSS

B14

VSS

B18

VSS

B22

VSS

B30

VSS

B34

VSS

B39

VSS

B44

VSS

B48

VSS

B53

VSS

B58

VSS

B62

VSS

B66

VSS

B71

VSS

BA1

VSS

BA10

VSS

BA14

VSS

BA18

VSS

BA2

VSS

BA23

VSS

BA28

VSS

BA32

VSS

BA36

VSS

F68

VSS

BA45

VSS

SKL-U_BGA1356

@

SKL-U

GND 2 OF 3

17 OF 20

3

Rev_1.0

BA49

VSS

BA53

VSS

BA57

VSS

BA6

VSS

BA62

VSS

BA66

VSS

BA71

VSS

BB18

VSS

BB26

VSS

BB30

VSS

BB34

VSS

BB38

VSS

BB43

VSS

BB55

VSS

BB6

VSS

BB60

VSS

BB64

VSS

BB67

VSS

BB70

VSS

C1

VSS

C25

VSS

C5

VSS

D10

VSS

D11

VSS

D14

VSS

D18

VSS

D22

VSS

D25

VSS

D26

VSS

D30

VSS

D34

VSS

D39

VSS

D44

VSS

D45

VSS

D47

VSS

D48

VSS

D53

VSS

D58

VSS

D6

VSS

D62

VSS

D66

VSS

D69

VSS

E11

VSS

E15

VSS

E18

VSS

E21

VSS

E46

VSS

E50

VSS

E53

VSS

E56

VSS

E6

VSS

E65

VSS

E71

VSS

F1

VSS

F13

VSS

F2

VSS

F22

VSS

F23

VSS

F27

VSS

F28

VSS

F32

VSS

F33

VSS

F35

VSS

F37

VSS

F38

VSS

F4

VSS

F40

VSS

F42

VSS

BA41

VSS

2

SKL-U

F8 G10 G22 G43 G45 G48

G5 G52 G55 G58

G6 G60 G63 G66 H15 H18 H71

J11 J13 J25 J28 J32 J35 J38 J42

J8 K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71 L11 L16 L17

UC1R

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-U_BGA1356

@

GND 3 OF 3

18 OF 20

Rev_1.0

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(11/12)GND

Size Document Number Re v

Custom

Date : Sheet of

2

Date : Sheet of

LA-E541P

1

16 51Wednesday, June 21, 2017

2.A

5

D D

4

3

2

1

UC1S

E68

CFG[0]

B67

CFG[1]

D65

CFG[2]

D67

CFG[3]

AL25 AL27

BA70 BA68

E70 C68 D68 C67 F71 G69 F70 G68 H70 G71 H69 G70

E63 F63

E66 F66

E60

E8

AY2 AY1

D1 D3

K46 K45

C71 B70

F60

A52

J71 J68

F65 G65

F61 E61

CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2 RSVD_AY1

RSVD_D1 RSVD_D3

RSVD_K46 RSVD_K45

RSVD_AL25 RSVD_AL27

RSVD_C71 RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70 RSVD_TP_BA68

RSVD_J71 RSVD_J68

VSS_F65 VSS_G65

RSVD_F61 RSVD_E61

SKL-U_BGA1356

@

CFG4

C C

B B

CFG_RCOMP

SKL-U

RESERVED SIGNALS-1

19 OF 20

Rev_1.0

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

RSVD_D5 RSVD_D4

RSVD_B2

RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4

RSVD_C4

RSVD_A69 RSVD_B69

RSVD_AY3

RSVD_D71 RSVD_C70

RSVD_C54 RSVD_D54

VSS_AY71

ZVM#

RSVD_TP RSVD_TP

MSM#

PROC_SELECT#

BB68 BB69

AK13 AK12

BB2 BA3

AU5

TP5

AT5

TP6

D5 D4 B2 C2

B3 A3

AW1

E1 E2

BA4 BB4

A4 C4

BB5

TP4

A69 B69

AY3

D71 C70

C54 D54

AY4

TP1

BB3

TP2

AY71 AR56

AW71 AW70

AP56 C64

RC97 0_0402_5%@

RC213 0_0402_ 5%@

PM_MSM# SKL_CNL#

1 2

T185 TP @

1 2

RC99 100 K_0402_5%@

+1.0V_VCCST

Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0

+1.8VALW

1 2

RC98 0_0402_5%@

1 2

1U_0402_6.3V6K

1

CC98

@

2

SOC_XTAL24_OUT _U42

@

RC102 0_0402_5%

AW69 AW68

AU56

AW48

C7 U12 U11 H11

SOC_XTAL24_IN_U4 2 XTAL24_IN_U42

SOC_XTAL24_OUT _U42

SPARE

SKL-U

20 OF 20

RSVD_F6

RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12 RSVD_F52

UC1T

RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48 RSVD_C7 RSVD_U12 RSVD_U11 RSVD_H11

SKL-U_BGA1356

@

U42_EMI@

1 2

RC106 33_0402 _1%

U42_EMI@

1 2

RC107 33_0402 _1%

Rev_1.0

F6

SOC_XTAL24_IN_U4 2

E3 C11 B11 A11 D12 C12 F52

XTAL24_OUT_U4 2

U42@

1 2

RC40 1M_04 02_5%

U42@

YC3

24MHZ_18PF_XRC GB24M000F2P51R0

SJ10000UJ00

1

NC

27P_0402_50V8J

CC126

2

1

NC

2

4

3

27P_0402_50V8J

CC52

2

U42@

1

Stuff 100k(RC99) for CannonLake-U

Un-stuff 100k(RC99) for SkyLake-U

1 2

RC100 49.9_0402_1%

1 2

RC101 1K_0402_5%

A A

Display Port Presence Strap

CFG4

CFG_RCOMP

CFG4

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(12/12)CFG,RSVD

Size Document Number Re v

Custom

Date : Sheet of

2

Date : Sheet of

LA-E541P

1

17 51Wednesday, June 21, 2017

2.A

A

DDR_A_DQS#[0..7]<7>

DDR_A_D[0..63]<7>

DDR_A_DQS[0..7]<7>

DDR_A_MA[0..16]<7>

DDR_A_BA0<7>

DDR_A_BA1<7>

DDR_A_BG0<7> DDR_A_BG1<7>

1 1

Layout Note: Place near JDIMM1

2 2

DDR_A_CLK0< 7> DDR_A_CLK#0<7>

DDR_A_CLK1< 7>

DDR_A_CLK#1<7>

DDR_A_CKE0<7>

DDR_A_CKE1<7>

DDR_A_CS#0< 7> DDR_A_CS#1< 7>

PCH_SMB_DATA<8> PCH_SMB_CLK<8>

DDR_A_ODT0<7> DDR_A_ODT1<7>

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

+1.2V

1U_0402_6.3V6K

1

CD4

@

2

1U_0402_6.3V6K

1

CD5

@

2

1U_0402_6.3V6K

1

CD6

CD7

@

2

1U_0402_6.3V6K

1

CD8

CD9

2

1U_0402_6.3V6K

1

CD17

CD18

@

2

4 as near side of the DIMM close to VDD pins

+1.2V

10U_0603_6.3V6M

CD10

1

2

10U_0603_6.3V6M

CD11

CD12

1

@

2

CD13

1

2

10U_0603_6.3V6M

CD14

1

2

10U_0603_6.3V6M

CD19

CD15

1

@

2

330U_D3_2.5VY_R6M

10U_0603_6.3V6M

1

CD35

CD20

1

+

@

2

Place these caps on the VTT plane close to DIMM

+0.6VS

1

2

10U_0603_6.3V6M

CD22

1

2

+3VS

1

2

10U_0603_6.3V6M

CD23

2.2U_0402_6.3V6M

CD37

1

2

close to DIMM

+3VS_DIMM

0.1U_0201_10V6K

CD28

1U_0402_6.3V6K

3 3

4 4

1U_0402_6.3V6K

CD30

CD31

1

2

+2.5V

10U_0603_6.3V6M

CD36

1

2

1U_0402_6.3V6K

CD33

CD32

1

2

1U_0402_6.3V6K

CD29

1

2

B

Interleaved Memory

+1.2V +1.2V

DDR_A_D4 DDR_A_D1

DDR_A_D5 DDR_A_D0

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D7

DDR_A_D3

DDR_A_D11

DDR_A_D12

DDR_A_D13 DDR_A_D14

DDR_A_D15 DDR_A_D10

DDR_A_D16 DDR_A_D17

DDR_A_D20 DDR_A_D21

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D22

DDR_A_D18

DDR_A_D24

DDR_A_D28

DDR_A_D30 DDR_A_D31

DDR_A_D26 DDR_A_D27

DDR_A_CKE0 DDR_A_CKE1

DDR_A_BG1 DDR_A_BG0

DDR_A_MA9

DDR_A_MA8 DDR_A_MA6

DDR_A_MA1

DDR_A_CLK0

DDR_A_PARITY< 7>

+2.5V

DDR_A_CLK#0

DDR_A_BA1

DDR_A_CS#0 DDR_A_MA14

DDR_A_ODT0 DDR_A_CS#1

DDR_A_ODT1

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D38

DDR_A_D34

DDR_A_D41

DDR_A_D40

DDR_A_D43 DDR_A_D47

DDR_A_D42 DDR_A_D46

DDR_A_D52

DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D55

DDR_A_D50

DDR_A_D58

DDR_A_D56

DDR_A_D57 DDR_A_D60

DDR_A_D59 DDR_A_D61

+3VS_DIMM

JDIMM1

1 3 5 7 9

15 17 19 21

27 29

35

39

43

47

51

77

81

85

89

93

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143

145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231 233 235 237 239 241 243 245 247 249 251 253 255 257 259

DEREN_40-42271-26001RHF

SP07001CW00

ME@

VSS DQ5 VSS DQ1 VSS DQS0_C11DM0*/DBI0* DQS0_T13VSS VSS DQ7 VSS DQ3 VSS23DQ12 DQ1325VSS VSS DQ9 VSS31DQS1_C DM1*/DBI1*33DQS1_T VSS DQ1537DQ14 VSS DQ1041DQ11 VSS DQ2145DQ20 VSS DQ1749DQ16 VSS DQS2_C53DM2*/DBI2* DQS2_T55VSS VSS57DQ22 DQ2359VSS VSS61DQ18 DQ1963VSS VSS65DQ28 DQ2967VSS VSS69DQ24 DQ2571VSS VSS73DQS3_C DM3*/DBI3*75DQS3_T VSS DQ3079DQ31 VSS DQ2683DQ27 VSS CB5_NC87CB4_NC VSS CB1_NC91CB0_NC VSS DQS8_C95DM8*/DBI8* DQS8_T97VSS VSS99CB6_NC CB2_NC VSS

CB7_NC CB3_NC VSS

RESET* CKE0

CKE1

VDD1

VDD2 BG1 BG0

ALERT*

VDD3

VDD4 A12 A9 VDD5

VDD6 A8 A6 VDD7

VDD8 A3 A1

EVENT*

VDD9

VDD10

CK0_T

CK1_T

CK0_C

CK1_C

VDD11

VDD12

PARITY

BA1

A10_AP

VDD13

VDD14 S0* A14_WE*

A16_RAS*

VDD15

VDD16 ODT0

A15_CAS* S1* VDD17

VDD18

ODT1

S2*/C0

VDD19

VREFCA S3*/C1 VSS DQ37

DQ36 VSS DQ33

DQ32 VSS DQS4_C

DM4*/DBI4* DQS4_T VSS

DQ39 DQ38 VSS

DQ35 DQ34 VSS

DQ45 DQ44 VSS

DQ41 DQ40 VSS

DQS5_C

DM5*/DBI5*

DQS5_T VSS DQ46

DQ47 VSS DQ42

DQ43 VSS DQ52

DQ53 VSS DQ49

DQ48 VSS DQS6_C

DM6*/DBI6* DQS6_T VSS

DQ54 DQ55 VSS

DQ50 DQ51 VSS

DQ60 DQ61 VSS

DQ57 DQ56 VSS

DQS7_C

DM7*/DBI7*

DQS7_T VSS DQ62

DQ63 VSS DQ58

DQ59 VSS SCL VDDSPD VPP1 VPP2

C

D

E

Reverse Type

2-3A to 1 D IMMs/channel

RD10

2_0402_1%

1 2

1

2

RD12

24.9_0402_1%

+1.2V

12

RD19 1K_0402_1%

RD20 1K_0402_1%

+DIMM_VREF_DQ

DDR_DRAMRST# <7>

2

VSS

4

DQ4

6

VSS

8

DQ0

10

VSS

12 14

DDR_A_D6

16

DQ6

18

VSS DQ2 VSS

DQ8 VSS

VSS

ACT*

A11

A7

A5 A4

A2

A0

BA0

A13

SA2 VSS

VSS

VSS SDA SA0 VTT SA1

GND GND

DDR_A_D2

20

22

DDR_A_D9

24

26

DDR_A_D8

28

30

DDR_A_DQS#1

32

DDR_A_DQS1

34

36

38

40

42

44

46

48

50

52

54

56

DDR_A_D23

58

60

DDR_A_D19

62

64

DDR_A_D29

66

68

DDR_A_D25

70

72

DDR_A_DQS#3

74

DDR_A_DQS3

76

78

80

82

84

86

88

90

92

94

96

98

100

102

104

106

DDR_DRAMRST#_R

108

110

112

114

116

118

DDR_A_MA11DDR_A_MA12

120

DDR_A_MA7

122

124

DDR_A_MA5

126

DDR_A_MA4

128

130

DDR_A_MA2DDR_A_MA3

132

134

136

DDR_A_CLK1

138

DDR_A_CLK#1

140

142

DDR_A_MA0

144

DDR_A_MA10

146

148

DDR_A_BA0

150

DDR_A_MA16

152

154

DDR_A_MA15

156

DDR_A_MA13

158

160

162

164

166

168

DDR_A_D36DDR_A_D37

170

172

174

176

178

180

DDR_A_D39

182

184

DDR_A_D35

186

188

DDR_A_D44

190

192

DDR_A_D45

194

196

DDR_A_DQS#5

198

DDR_A_DQS5

200

202

204

206

208

210

DDR_A_D48

212

214

DDR_A_D53

216

218

220

222

DDR_A_D54

224

226

DDR_A_D51

228

230

DDR_A_D63

232

234

DDR_A_D62

236

238

DDR_A_DQS#7

240

DDR_A_DQS7

242

244

246

248

250

252

PCH_SMB_DATAPCH_SMB_CLK

254

DDR_A_SA0

256

258

DDR_A_SA1

260

261

262

CD34 100P_0201_25V8J

+0.6VS

1 2

ESD@

DDR_A_ALERT# <7>

+DIMM_VREF_DQ

+0.6V_VREFCA<7>

+0.6V_A_VREFDQ<7>

M_A_ACT# <7>

1 2

RD21 0_0402_5%

1 2

RD22 0_0402_5%@

DDR_DRAMRST#_R

+3VS

RD14

10K_0402_5%

@

1 2

DDR_A_SA1 DDR_A_SA0

12

RD16 0_0402_5%

+0.6V_VREFCA_R

20mil

0.022U_0402_16V7K

1 2

RD11 0_0402_5%

+3VS

RD13

10K_0402_5%

@

1 2

12

CD21

RD15 0_0402_5%

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet of

DDR4_DIMM

Document Number Re v

LA-E541P

E

18 51Wednesday, Jun e 21, 2017

2.A

1

PLT_RST_VGA_MON # PLT_RST_VGA#

CLKREQ_PCIE#0_ R

PCI_RST#<10,30,3 1,32,35>

DGPU_HOLD_R ST#<11>

CLKREQ_PCIE#0_ R

CLK_PEG_VGA<10> CLK_PEG_VGA#<10>

PCIE_PRX_DTX_P1<12> PCIE_PRX_DTX_N1<12>

PCIE_PTX_C_DRX_P1<12> PCIE_PTX_C_DRX_N1<12>

PCIE_PRX_DTX_P2<12> PCIE_PRX_DTX_N2<12>

PCIE_PTX_C_DRX_P2<12> PCIE_PTX_C_DRX_N2<12>

PCIE_PRX_DTX_P3<12> PCIE_PRX_DTX_N3<12>

PCIE_PTX_C_DRX_P3<12> PCIE_PTX_C_DRX_N3<12>

PCIE_PRX_DTX_P4<12> PCIE_PRX_DTX_N4<12>

PCIE_PTX_C_DRX_P4<12> PCIE_PTX_C_DRX_N4<12>

RV16 0_ 0402_5%@

+3VS_DGPU_AON

RV68

10K_0402_5 %

DIS@

1 2

12

PCIE_PRX_DTX_P1 PCIE_PRX_DTX_N1

PCIE_PTX_C_DRX_P1 PCIE_PTX_C_DRX_N 1

PCIE_PRX_DTX_P2 PCIE_PRX_C_DTX_P2 PCIE_PRX_DTX_N2

PCIE_PTX_C_DRX_P2 PCIE_PTX_C_DRX_N 2

PCIE_PRX_DTX_P3 PCIE_PRX_DTX_N3

PCIE_PTX_C_DRX_P3 PCIE_PTX_C_DRX_N 3

PCIE_PRX_DTX_P4 PCIE_PRX_DTX_N4

PCIE_PTX_C_DRX_P4 PCIE_PTX_C_DRX_N 4

+3VS

UV12

5

IN1

VCC

OUT

IN2

GND

DIS@

3

+3VS_DGPU

12

2

G

S

VGS(Max) : 2.5 V

1 2

MC74VHC1G08D FT2G_SC70-5

4

RV17 10K_0402_5 %

DIS@

QV3 2N7002K_SOT 23-3

13

D

DIS@

1

2

CV121

1U_0402_6.3V6K

1

@

2

RV375 0_040 2_5%@

PCIE CLK

A A

PCIE X4 Bus

B B

Reset Control

(From PC H)

(From GPU)

C C

PLT_RST_VGA_H OLD#<22>

CLK_ REQ

DGPU_PWR OK<23,24,49>

D D

2

1 2

RV379 0_040 2_5%

NOGC6@

1 2

CV11 0.22U_04 02_6.3V6KDIS@

1 2

CV12 0.22U_04 02_6.3V6KDIS@

1 2

CV13 0.22U_04 02_6.3V6KDIS@

1 2

CV14 0.22U_04 02_6.3V6KDIS@

1 2

CV15 0.22U_04 02_6.3V6KDIS@

1 2

CV16 0.22U_04 02_6.3V6KDIS@

1 2

CV17 0.22U_04 02_6.3V6KDIS@

1 2

CV18 0.22U_04 02_6.3V6KDIS@

+3VS_DGPU_AON

1

2

VGA_CLKREQ#

5

IN1

VCC

IN2

GND

3

UV15 MC74VHC1G08D FT2G_SC70-5

OUT

GC6@

12

RV18 10K_0402_5 %

@

PCIE_PRX_C_DTX_P1 PCIE_PRX_C_DTX_N 1

PCIE_PRX_C_DTX_N 2

PCIE_PRX_C_DTX_P3 PCIE_PRX_C_DTX_N 3

PCIE_PRX_C_DTX_P4 PCIE_PRX_C_DTX_N 4

PLT_RST_VGA_MON # <22>

PLT_RST_VGA#

4

12

RV378 10K_0402_5 %

DIS@

VGA_CLKREQ# <1 0>

(To SOC)

Near U V1

UV1A

COMMON

1/14 PCI_EXPRESS

AB6

PEX_WAKE#

AC7

PEX_RST#

AC6

PEX_CLKREQ#

AE8

PEX_REFCLK

AD8

PEX_REFCLK#

AC9

PEX_TX0

AB9

PEX_TX0#

AG6

PEX_RX0

AG7

PEX_RX0#

AB10

PEX_TX1

AC10

PEX_TX1#

AF7

PEX_RX1

AE7

PEX_RX1#

AD11

PEX_TX2

AC11

PEX_TX2#

AE9

PEX_RX2

AF9

PEX_RX2#

AC12

PEX_TX3

AB12

PEX_TX3#

AG9

PEX_RX3

AG10

PEX_RX3#

AB13

PEX_TX4

AC13

PEX_TX4#

AF10

PEX_RX4

AE10

PEX_RX4#

AD14

PEX_TX5

AC14

PEX_TX5#

AE12

PEX_RX5

AF12

PEX_RX5#

AC15

PEX_TX6

AB15

PEX_TX6#

AG12

PEX_RX6

AG13

PEX_RX6#

AB16

PEX_TX7

AC16

PEX_TX7#

AF13

PEX_RX7

AE13

PEX_RX7#

AD17

PEX_TX8

AC17

PEX_TX8#

AE15

PEX_RX8

AF15

PEX_RX8#

AC18

PEX_TX9

AB18

PEX_TX9#

AG15

PEX_RX9

AG16

PEX_RX9#

AB19

PEX_TX10

AC19

PEX_TX10#

AF16

PEX_RX10

AE16

PEX_RX10#

AD20

PEX_TX11

AC20

PEX_TX11#

AE18

PEX_RX11

AF18

PEX_RX11#

AC21

PEX_TX12

AB21

PEX_TX12#

AG18

PEX_RX12

AG19

PEX_RX12#

AD23

PEX_TX13

AE23

PEX_TX13#

AF19

PEX_RX13

AE19

PEX_RX13#

AF24

PEX_TX14

AE24

PEX_TX14#

AE21

PEX_RX14

AF21

PEX_RX14#

AG24

PEX_TX15

AG25

PEX_TX15#

AG21

PEX_RX15

AG22

PEX_RX15#

N16S-GT-S-A2_BGA59 5

@

NC FOR GM108

NC FOR GF117/GK208/GM108

3

PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD

PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ

NC FOR GF119

PEX_PLL_HVDD PEX_PLL_HVDD

PEX_SVDD_3V3

VDD_SENSE

GND_SENSE

PEX_TSTCLK_OUT PEX_TSTCLK_OUT#

PEX_PLLVDD PEX_PLLVDD

TESTMODE

PEX_TERMP

AA22 AB23 AC24 AD25 AE26 AE27

AA10 AA12 AA13 AA16 AA18 AA19 AA20 AA21 AB22 AC23 AD24 AE25 AF26 AF27

AA8 AA9

AB8

F2

F1

AF22 AE22

AA14 AA15

AD9

AF25

balls

1

2

Place near balls

1

2

VDD_SENSE_GPU

GND_SENSE_GPU

PEX_PLL_CLK_OU T PEX_PLL_CLK_OU T#

PEX_PLLVDD_GPU

GPU_TESTMOD E

PEX_TERMP

1U_0402_6.3V6K

CV202

CV205

1

DIS@

@

2

1U_0402_6.3V6K

CV201

CV200

1

@

2

Place near BGA

0.1U_0201_10V6K

4.7U_0402_6.3V6M

CV207

CV5

1

DIS@

2

RV4 200_0 402_1%@

GPU_TESTMODE <22>

12

RV376

2.49K_0402_ 1%

DIS@

4

Place near BGAPlace near

4.7U_0402_6.3V6M

10U_0603_6.3V6M

CV2

CV199

1

2

1

DIS@

@

2

Place near BGA

4.7U_0402_6.3V6M

10U_0603_6.3V6M

CV3

CV198

1

2

4.7U_0402_6.3V6M

VDD_SENSE_GPU <49>

GND_SENSE_GPU <49>

1

@

2

+3VS_DGPU_AON

CV4

DIS@

1

@

2

+1.0VS_DGPU

1.0V

10U_0603_6.3V6M

22U_0603_6.3V6M

CV204

@

CV203

DIS@

1

2

1.0V

1

2

CV9

@

22U_0603_6.3V6M

CV10

@

CV7

1

@

2

+1.0VS_DGPU

22U_0603_6.3V6M

CV8

1

DIS@

2

To POWER

trace width: 16mils differential voltage sensing. differential signal routing.

12

1.0V

Place near BALL Place near BGA

0.1U_0201_10V6K

1

2

1U_0402_6.3V6K

CV208

DIS@

CV206

1

2

1

DIS@

2

1 2

RV377 0_040 2_5%

4.7U_0402_6.3V6M CV6

DIS@

5

+1.0VS_DGPU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet of

4

Date : Sheet of

Compal Electronics, Inc.

NV(1/5)-PCIE

LA-E541P

5

2.A

19 51Wednesday, June 21, 2017

2.A

1

Vinaﬁx

2

3

4

5

UV1H UV1G

COMMON

4/14 IFPAB

AA6

7/14 IFPEF

IFPEF_PLLVDD

IFPEF_RSET

IFPAB_RSET

V7

IFPAB_PLLVDD

W7

IFPAB_PLLVDD

W6

IFPA_IOVDD

Y6

IFPB_IOVDD

IFPAB

N16S-GT-S-A2_BGA59 5

@

A A

B B

UV1J

COMMON

J7

K7

K6

C C

IFPE

H6

IFPE_IOVDD

J6

IFPF_IOVDD

IFPF

D D

N16S-GT-S-A2_BGA59 5

@

NC FOR GF117/GK208/GM108

1

IFPA/B

NC FOR GF117/GM108

IFPE/F

DVI-DL

I2CY_SDA I2CY_SCL

TXC TXC

TXD0 TXD0

TXD1

NC FOR GF117/GM108

TXD2 TXD2

HPD_E

DVI-DL

TXD3 TXD3

TXD4 TXD4

NC FOR GF117/GM108

TXD5 TXD5

NC FOR GF117/GM108

GF117

NC

GF119/GK208

DVI-SL/H DMI

I2CY_SDA I2CY_SCL

TXC TXC

TXD0 TXD0

TXD1TXD1 TXD1

TXD2 TXD2

NC FOR GK208

HPD_E

NC FOR GF117

GF119/GK208

DVI-SL/H DMI

I2CZ_SDA I2CZ_SCL

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

NC FOR GK208

HPD_F

NC FOR GF117

IFPA_TXC# IFPA_TXC

IFPA_TXD0# IFPA_TXD0

IFPA_TXD1# IFPA_TXD1

IFPA_TXD2# IFPA_TXD2

IFPA_TXD3# IFPA_TXD3

IFPB_TXC# IFPB_TXC

IFPB_TXD4# IFPB_TXD4

IFPB_TXD5# IFPB_TXD5

IFPB_TXD6# IFPB_TXD6

IFPB_TXD7# IFPB_TXD7

GPIO14

AC4 AC3

Y3 Y4

AA2 AA3

AA1 AB1

AA5 AA4

AB4 AB5

AB2 AB3

AD2 AD3

AD1 AE1

AD5 AD4

B3

IFPE_AUX# IFPE_AUX

IFPE_L3# IFPE_L3

IFPE_L2# IFPE_L2

IFPE_L1# IFPE_L1

IFPE_L0# IFPE_L0

IFPF_AUX# IFPF_AUX

IFPF_L3# IFPF_L3

IFPF_L2# IFPF_L2

IFPF_L1# IFPF_L1

IFPF_L0# IFPF_L0

DP

GPIO18

DP

GPIO19

UV1K

COMMON

3/14 DACA

W5

DACA_VDD

AE2

DACA_VREF

AF2

DACA_RSET

N16S-GT-S-A2_BGA59 5

@

+1.0VS_DGPU

1V

J3 J2

J1 K1

K3 K2

M3 M2

M1 N1

+1.0VS_DGPU

C2

1V

H4 H3

J5 J4

K5 K4

L4 L3

M5 M4

DAC_A

GF117/GM108 GF117

NC

TSEN_VREF

DIS@

1 2

LV5 PBY16080 8T-300Y-N 0603

1 2

LV6 0_0603_5%

NC

NC NC

NC

GM108 GF117

Place near balls

22U_0603_6.3V6M

1

2

CV61

DIS@

GM108/GK208

DACA_HSYNC DACA_VSYNC

DACA_RED

DACA_GREEN

DACA_BLUE

GK208

22U_0603_6.3V6M

CV35

1

DIS@

2

I2CA_SCL I2CA_SDA

10U_0603_6.3V6M

1

2

I2CA_SCL

B7

I2CA_SDA

A7

AE3 AE4

I2CA_SCL <22>

I2CA_SDA <22>

AG3

AF4

AF3

GPU_PLLVDD

0.1U_0201_10V K X5R

22U_0603_6.3V6M

CV31

CV32

1

DIS@

2

L6

DIS@

M6

N6

12

A10

Place near ballsPlace near BGA

0.1U_0201_10V K X5R

CV34

CV30

1

DIS@

2

VID_PLLVDD

0.1U_0201_10V K X5R

CV60

1

DIS@

2

RV21 10K_0402_1 %

C11

90-OHM DIFF Impedance for XTALIN & XTALOUT.

1

CV210 18P_0402_5 0V8J

2

F7

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/06/05 2018/06/05

Compal Secret Data

COMMON

5/14 IFPC

T6

IFPC_RSET

M7

IFPC_PLLVDD

N7

IFPC_PLLVDD

P6

IFPC_IOVDD

N16S-GT-S-A2_BGA59 5

@

UV1I

COMMON

6/14 IFPD

U6

IFPD_RSET

T7

IFPD_PLLVDD

R7

IFPD_PLLVDD

R6

IFPD_IOVDD

N16S-GT-S-A2_BGA59 5

@

UV1M

COMMON

9/14 XTAL_PLL

PLLVDD SP_PLLVDD

VID_PLLVDD

GF119/GK208

XTALSSIN

XTALIN

N16S-GT-S-A2_BGA59 5

@

DIS@

Deciphered Date

IFPD

X'TAL

NC

GF117/GM108

YV1 27MHZ_10PF_XRC GB27M000F2P18R0

SJ10000UI00

1

DIS@

4

NC

2

NC FOR GF117/GM108

NC

4

IFPC

IFPD

XTALOUTBUFF

3

IFPC

GF119/GK208

DVI/HDMI

I2CW_SDA I2CW_SCL

TXC TXC

TXD0

NC FOR GF117/GM108

TXD0

TXD1 TXD1

TXD2 TXD2

GF119/GK208

DVI/HDMI

I2CX_SDA I2CX_SCL

NC FOR GF117/GM108

C10

B10

XTALOUT

Title

Size Document Number Re v

Date : Sheet of

DP

N5

IFPC_AUX#

N4

IFPC_AUX

N3

IFPC_L3#

N2

IFPC_L3

R3

IFPC_L2#

R2

IFPC_L2

R1

IFPC_L1#

T1

IFPC_L1

T3

IFPC_L0#

T2

IFPC_L0

GF117

NC

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

GF117

NC

XTAL_OUTBUFF

RV110

1.5K_0402_1 %

GPIO15

DP

IFPD_AUX# IFPD_AUX

IFPD_L3# IFPD_L3

IFPD_L2# IFPD_L2

IFPD_L1# IFPD_L1

IFPD_L0# IFPD_L0

GPIO17

DIS@

C3

P4 P3

R5 R4

T5 T4

U4 U3

V4 V3

D4

RV23

@

10K_0402_1 %

1 2

RV20

DIS@

10K_0402_1 %

1 2

+3VS_DGPU_AON

1 2

1

CV209

DIS@

18P_0402_5 0V8J

2

Compal Electronics, Inc.

NV(2/5)-IFP_ABCDEF_DAC_XTAL

LA-E541P

5

2.A

20 51Wednesday, June 21, 2017

2.A

1

2

3

4

5

CV215

CV44

1

2

1

2

4.7U_0402_6.3V6M CV216

DIS@

4.7U_0402_6.3V6M CV213

DIS@

2

UV1D

COMMON

12/14 FBVDDQ

B26

FBVDDQ

C25

FBVDDQ

E23

FBVDDQ

E26

FBVDDQ

F14

FBVDDQ

F21

FBVDDQ

G13

FBVDDQ

G14

FBVDDQ

G15

FBVDDQ

G16

FBVDDQ

G18

FBVDDQ

G19

FBVDDQ

G20

FBVDDQ

G21

FBVDDQ

L22

FBVDDQ

L24

FBVDDQ

L26

FBVDDQ

M21

FBVDDQ

N21

FBVDDQ

R21

FBVDDQ

T21

FBVDDQ

V21

FBVDDQ

W21

FBVDDQ

H24

FBVDDQ_AON

H26

FBVDDQ_AON

J21

FBVDDQ_AON

K21

FBVDDQ_AON

N16S-GT-S-A2_BGA59 5

@

GF117 GF119

GK208

FBVDDQ FBVDDQ FBVDDQ FBVDDQ

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CALTERM_GND

+3VS_DGPU

+3VS_DGPU_AON

D22

C24

B25

Near Ball

1 2

RV41 40.2_040 2_1%DIS@

RV42 40.2_040 2_1%DIS@

RV43 60.4_040 2_1%DIS@

GPU_Decoupling CAPs @ Power Page

+VGA_CORE

Voltage by GPU SKU

+1.35VS_VRAM

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

UV1E

COMMON

11/14 NVVDD

K10

VDD

K12

VDD

K14

VDD

K16

VDD

K18

VDD

L11

VDD

L13

VDD

L15

VDD

L17

VDD

M10

VDD

M12

VDD

M14

VDD

M16

VDD

M18

VDD

N11

VDD

N13

VDD

N15

VDD

N17

VDD

P10

VDD

P12

VDD

P14

VDD

P16

VDD

P18

VDD

R11

VDD

R13

VDD

R15

VDD

R17

VDD

T10

VDD

T12

VDD

T14

VDD

T16

VDD

T18

VDD

U11

VDD

U13

VDD

U15

VDD

U17

VDD

V10

VDD

V12

VDD

V14

VDD

V16

VDD

V18

VDD

N16S-GT-S-A2_BGA59 5

@

Compal Secret Data

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

4

+1.35VS_VRAM

4.7U_0402_6.3V6M

CV217

CV38

1

A A

B B

1

DIS@

2

1U_0402_6.3V6K

CV218

1

DIS@

2

Place under GPU

1U_0402_6.3V6K

0.1U_0201_10V6K

CV221

CV222

1

DIS@

2

22U_0603_6.3V6M

CV45

1

DIS@

2

Place near GPU

0.1U_0201_10V6K

1

DIS@

2

10U_0603_6.3V6M

1

DIS@

2

CIZ00 22uF x1 change to 10uF x2

C C

D D

UV1C

COMMON

14/14 XVDD/VDD33

AD10

NC

AD7

NC

F11

3V3AUX_NC

V5

FERMI_RSVD1_NC

V6

FERMI_RSVD2_NC

CONFIGURABLE

POWER CHANNELS

* nc on substrate

G1

XPWR_G1

G2

XPWR_G2

G3

XPWR_G3

G4

XPWR_G4

G5

XPWR_G5

G6

XPWR_G6

G7

XPWR_G7

V1

XPWR_V1

V2

XPWR_V2

W1

XPWR_W1

W2

XPWR_W2

W3

XPWR_W3

W4

XPWR_W4

N16S-GT-S-A2_BGA59 5

@

3V3_AON 3V3_AON

1

Under GPU Near GPU

G8

VDD33

GM108

VDD33 VDD33

G10 G12

G9

VDD33

0.1U_0201_10V6K

CV220

1

DIS@

2

1U_0402_6.3V6K

0.1U_0201_10V6K

CV219

CV211

1

DIS@

2

Near GPUUnder GPU

0.1U_0201_10V6K

1U_0402_6.3V6K

CV214

1

2

DIS@

CV212

1

DIS@

2

** XPWR pins are configurable.

These pins are not connected on the substrate.

Therefore, XPW R pins can be assigned as needed,

to improve Top layer routing, power delivery.

UV1F

COMMON

13/14 GND

A2

GND

AB17

GND

AB20

GND

AB24

GND

AC2

GND

AC22

GND

AC26

GND

AC5

GND

AC8

GND

AD12

GND

AD13

GND

A26

GND

AD15

GND

AD16

GND

AD18

GND

AD19

GND

AD21

GND

AD22

GND

AE11

GND

AE14

GND

AE17

GND

AE20

GND

AB11

GND

AF1

GND

AF11

GND

AF14

GND

AF17

GND

AF20

GND

AF23

GND

AF5

GND

AF8

GND

AG2

GND

AG26

GND

AB14

GND

B1

GND

B11

GND

B14

GND

B17

GND

B20

GND

B23

GND

B27

GND

B5

GND

B8

GND

E11

GND

E14

GND

E17

GND

E2

GND

E20

GND

E22

GND

E25

GND

E5

GND

E8

GND

H2

GND

H23

GND

H25

GND

H5

GND

K11

GND

K13

GND

K15

GND

K17

GND

L10

GND

L12

GND

L14

GND

L16

GND

L18

GND

L2

GND

L23

GND

L25

GND

L5

GND

M11

GND

N16S-GT-S-A2_BGA59 5

@

M13

GND

M15

GND

M17

GND

N10

GND

N12

GND

N14

GND

N16

GND

N18

GND

P11

GND

P13

GND

P15

GND

P17

GND

P2

GND

P23

GND

P26

GND

P5

GND

R10

GND

R12

GND

R14

GND

R16

GND

R18

GND

T11

GND

T13

GND

T15

GND

T17

GND

U10

GND

U12

GND

U14

GND

U16

GND

U18

GND

U2

GND

U23

GND

U26

GND

U5

GND

V11

GND

V13

GND

V15

GND

V17

GND

Y2

GND

Y23

GND

Y26

GND

Y5

GND

AA7

GND

AB7

GND

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet of

Compal Electronics, Inc.

NV(3/5)-POWER

LA-E541P

5

21 51Wednesday, June 21, 2017

2.A

1

UV1N

COMMON

E12

THERMDN

F12

GPU_JTAG_TCK

T231 TP@

GPU_JTAG_TMS

T232 TP@

GPU_JTAG_TDI

T242 TP@ T243 TP@

GPU_JTAG_TDO

GPU_JTAG_TRST#

A A

THERMDP

AE5

JTAG_TCK

AD6

JTAG_TMS

AE6

JTAG_TDI

AF6

JTAG_TDO

AG4

JTAG_TRST#

N16S-GT-S-A2_BGA595

@

8/14 MISC1

GPIO

GM108

GPIO16 GPIO20 GPIO21

GPIO8

GPIO16 GPIO20

GK208

GPIO8

GF117

NC NC

GK208

GM108 OVERT

GF117 GF119

NC NC

I2CS_SCL

D9

I2CS_SCL

I2CS_SDA

D8

I2CS_SDA

I2CC_SCL

A9

I2CC_SCL

I2CC_SDA

B9

I2CC_SDA

I2CB_SCL

C9

I2CB_SCL

I2CB_SDA

C8

I2CB_SDA

GPIO0_GC6_FB_EN

C6

GPIO0

B2

GPIO1

D6

GPIO2

C7

GPIO3

F9

GPIO4

DGPU_MAIN_EN

A3

GPIO5

GPU_EVENT#_D

A4

GPIO6

B6

GPIO7

GPIO8_OVERT#

A6

GPIO8

GPIO9_ALERT#

F8

GPIO9

MEM_VREF

C5

GPIO10

GPU_VID0

E7

GPIO11

VGA_AC_DET

D7

GPIO12

B4

PSI

GPIO13

D5

GPIO16

NC NC NC

GPIO20 GPIO21

NC

E6

PLT_RST_VGA_HOLD#

C4

PLT_RST_VGA_MON#

E9

2

1 2

RV203 2.2K_0402_5%DIS@

1 2

RV204 2.2K_0402_5%DIS@

1 2

RV205 2.2K_0402_5%@

1 2

RV206 2.2K_0402_5%@

1 2

RV202 0_0402_5%

For GC6 2.0

DV1 RB751V-40_SOD323-2GC6@

DV5 RB751V-40_SOD323-2DIS@

+3VS_DGPU_AON

I2CS SMBUS: 0x96 and 0x9E(Default)

12

GC6_FB_EN <11,23>

DGPU_MAIN_EN < 24,49> GPU_EVENT# <11>

GPU_PROHOT# <32>

MEM_VREF <25> GPU_VID0 <49>

PSI <49>

PLT_RST_VGA_HOLD# <19>

PLT_RST_VGA_MON# <19>

To EC

To DGPU VR

From EC

To DGPU VR

3

PLT_RST_VGA_HOLD# DGPU_MAIN_EN

PSI VGA_AC_DET

GPU_EVENT#_D

GPIO8_OVERT#

GPIO9_ALERT#

GPU_JTAG_TRST#

FB_CLAMP<23>

I2CA_SCL<20> I2CA_SDA<20>

GPU_TESTMODE<1 9>

FB_CLAMP

I2CA_SCL I2CA_SDA I2CB_SCL I2CB_SDA

GPU_BUFRST

GPU_TESTMODE

MEM_VREF

PLT_RST_VGA_MON#

GC6_FB_EN

RPV5

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

DIS@

1 2

RV72 10K_0402_5%GC6@

1 2

RV69 100K_0402_5%DIS@

RPV6

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

DIS@

RPV3

1 8 2 7 3 6 4 5

2.2K_0804_8P4R_5%

1 2

RV67 10K_0402_5%@

1 2

RV71 10K_0402_5%DIS@

1 2

RV102 100K_0402_5%DIS@

1 2

RV70 10K_0402_5%@

1 2

RV88 10K_0402_5%GC6@

@

4

+3VS_DGPU_AON

5

UV1L

COMMON

10/14 MISC2

E10

VMON_IN0_NC

F10

B B

+3VS_DGPU_AON

RV265 0_0402_5%

1 2

@

12

C C

VMON_IN1_NC

D1

STRAP0

D2

STRAP1

E4

STRAP2

E3

STRAP3

D3

STRAP4

C1

F6

STRAPREF0

F4

RV380

40.2K_0402_1%

F5

DIS@

VGA_AC_DET EC_VCIN1_AC_B YPASS

NC FOR

STRAP2

GM108

STRAP3 STRAP4

STRAP5_NC

MULTISTRAP_REF0_GND

MULTISTRAP_REF1_GND

MULTISTRAP_REF2_GND

N16S-GT-S-A2_BGA595

@

+3VS Reserve for leakage issue

+3VS +3VS

RV15

@

10K_0402_5%

1 2

RV126 0_0402_5%@

DV4

@

RB751V-40_SOD323-2

12

1 2

GF117

GK208

GM108

NC

GK208

GM108

1 2

ROM_CS#

ROM_SI

ROM_SO

ROM_SCLK

BUFRST#

PGOOD

NC

GF119GF117

RV26

@

10K_0402_5%

D12

ROM_SI

B12

ROM_SO

A12

ROM_SCLK

C12

GPU_BUFRST

D11

D10

STRAP

ROM_SI ROM_SO ROM_SCLK

EC_VCIN1_AC_BYPASS <10,32>

+3VS_DGPU

10K_0402_1%

14.7K_0402_1%

12

RV84

@

4.99K_0402_1%

12

DIS@

RV65

@

4.99K_0402_1%

12

RV81

@

12

RV80

@

4.99K_0402_1%

12

RV64

RV381

DIS@

STRAP

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

+3VS_DGPU_AON

STRAP0 : PU 49.9K (50K) STRAP[1:5] : Reserved

45.3K_0402_1%

12

10K_0402_1%

RV61

@

4.99K_0402_1%

45.3K_0402_1%

12

RV385

@

4.99K_0402_1%

12

RV389

RV382

@

4.99K_0402_1%

12

RV388

RV387

@

49.9K_0402_1%

12

RV384

RV51

DIS@

@

4.99K_0402_1%

12

RV383

RV390

@

Internal Ther mal Sensor

+3VS_DGPU_AON

Link to PCH SML 1

PU @ PCH SIDE

EC_SMB_CK2 <8,32,36>

EC_SMB_DA2 <8,32,36>

I2CS_SCL

I2CS_SDA

S

2N7002KDW_SOT363-6

G

2

DIS@

QV2A

S

61

D

2N7002KDW_SOT363-6

G

5

DIS@

QV2B

34

D

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

NV(4/5)-GPIO/Strap

Size

Document Number Re v

LA-E541P

Date : Sheet of

5

22 51Wednesday, Jun e 21, 2017

2.A

1

2

3

4

5

UV1B

COMMON

FBA_D[0..31]<25>

A A

FBA_D[32..63]<25>

B B

FBA_DBI[3..0]<25>

FBA_DBI[7..4]<25>

C C

D D

FBA_EDC[3..0]<25>

FBA_EDC[7..4]<25>

For VRAM DEBUG using

T2401 TP@

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DBI0 FBA_DBI1 FBA_DBI2 FBA_DBI3 FBA_DBI4 FBA_DBI5 FBA_DBI6 FBA_DBI7

FBA_EDC0 FBA_EDC1 FBA_EDC2 FBA_EDC3 FBA_EDC4 FBA_EDC5 FBA_EDC6 FBA_EDC7

FB_VREF

2/14 FBA

E18

FBA_D0

F18

FBA_D1

E16

FBA_D2

F17

FBA_D3

D20

FBA_D4

D21

FBA_D5

F20

FBA_D6

E21

FBA_D7

E15

FBA_D8

D15

FBA_D9

F15

FBA_D10

F13

FBA_D11

C13

FBA_D12

B13

FBA_D13

E13

FBA_D14

D13

FBA_D15

B15

FBA_D16

C16

FBA_D17

A13

FBA_D18

A15

FBA_D19

B18

FBA_D20

A18

FBA_D21

A19

FBA_D22

C19

FBA_D23

B24

FBA_D24

C23

FBA_D25

A25

FBA_D26

A24

FBA_D27

A21

FBA_D28

B21

FBA_D29

C20

FBA_D30

C21

FBA_D31

R22

FBA_D32

R24

FBA_D33

T22

FBA_D34

R23

FBA_D35

N25

FBA_D36

N26

FBA_D37

N23

FBA_D38

N24

FBA_D39

V23

FBA_D40

V22

FBA_D41

T23

FBA_D42

U22

FBA_D43

Y24

FBA_D44

AA24

FBA_D45

Y22

FBA_D46

AA23

FBA_D47

AD27

FBA_D48

AB25

FBA_D49

AD26

FBA_D50

AC25

FBA_D51

AA27

FBA_D52

AA26

FBA_D53

W26

FBA_D54

Y25

FBA_D55

R26

FBA_D56

T25

FBA_D57

N27

FBA_D58

R27

FBA_D59

V26

FBA_D60

V27

FBA_D61

W27

FBA_D62

W25

FBA_D63

D19

FBA_DQM0

D14

FBA_DQM1

C17

FBA_DQM2

C22

FBA_DQM3

P24

FBA_DQM4

W24

FBA_DQM5

AA25

FBA_DQM6

U25

FBA_DQM7

E19

FBA_DQS_WP0

C15

FBA_DQS_WP1

B16

FBA_DQS_WP2

B22

FBA_DQS_WP3

R25

FBA_DQS_WP4

W23

FBA_DQS_WP5

AB26

FBA_DQS_WP6

T26

FBA_DQS_WP7

F19

FBA_DQS_RN0

C14

FBA_DQS_RN1

A16

FBA_DQS_RN2

A22

FBA_DQS_RN3

P25

FBA_DQS_RN4

W22

FBA_DQS_RN5

AB27

FBA_DQS_RN6

T27

FBA_DQS_RN7

D23

FB_VREF_PROBE

N16S-GT-S-A2_BGA59 5

@

GF117/GF119

GK208

FBA_DEBUG0 FBA_DEBUG1

FB_PLLAVDD

NC

GF119

FBA_CMD0

C27

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

NC

GF119

GF117

FBA_CMD32

FBA_CMD34 FBA_CMD35

FBA_CLK0 FBA_CLK0# FBA_CLK1 FBA_CLK1#

FBA_WCK01 FBA_WCK01# FBA_WCK23 FBA_WCK23# FBA_WCK45 FBA_WCK45# FBA_WCK67 FBA_WCK67#

FB_PLLAVDD

NC

FB_PLLAVDD

FB_DLLAVDD

C26 E24 F24 D27 D26 F25 F26 F23 G22 G23 G24 F27 G25 G27 G26 M24 M23 K24 K23 M27 M26 M25 K26 K22 J23 J25 J24 K27 K25 J27 J26

B19

F22 J22

D24 D25 N22 M22

D18 C18 D17 D16 T24 U24 V24 V25

F16

P22

H22

FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

RV82 60.4_040 2_1%@ RV83 60.4_040 2_1%@

FBA_CLK0 FBA_CLK0# FBA_CLK1 FBA_CLK1#

FBA_WCK0 FBA_WCK0# FBA_WCK1 FBA_WCK1# FBA_WCK2 FBA_WCK2# FBA_WCK3 FBA_WCK3#

+1.0VS_PLLAVDD

Close to P22

1 2 1 2

CV55

0.1U_0201_10V K X5R

1

DIS@

2

FB_CLAMP <22>

FBA_CKE_L

FBA_CKE_H

FBA_RST_L

FBA_RST_H

GDDR5 design

FBVDDQ_GPU

1.35V

FBA_WCK0 <25 > FBA_WCK0# <2 5> FBA_WCK1 <25 > FBA_WCK1# <2 5> FBA_WCK2 <25 > FBA_WCK2# <2 5> FBA_WCK3 <25 > FBA_WCK3# <2 5>

Close to F16

CV52

0.1U_0201_10V K X5R

2

DIS@

1

Close to H22

FBA_CMD[0..31] <2 5>

FBA_CMD14

FBA_CMD30

FBA_CMD13

FBA_CMD29

+1.35VS_VRAM

FBA_CLK0 <25> FBA_CLK0# <25> FBA_CLK1 <25> FBA_CLK1# <25>

+1.0VS_PLLAVDD +1.0VS_DGPU

CV53

0.1U_0201_10V K X5R

CV51

22U_0603_6.3V6M

1

DIS@

2

Near GPU

FB_CLAMP

F3

FB_CLAMP

For GC6

+1.35VS_VRAM +1.35VS_VRAM

10K_0402_5%

DIS@

RV255

1 2

10K_0402_5%

DIS@

RV253

1 2

LV7

DIS@

1.0V

1 2

PBY160808T-3 00Y-N 0603

1

2

CV223

0.1U_0201_ 10V K X5R

GC6_FB_EN<11,2 2>

DGPU_PWR OK<19,24,49>

10K_0402_5%

RV256

10K_0402_5%

RV254

GC6_FB_EN

+3VS

1

@

2

UV23

GC6@

5

MC74VHC1G32D FT2G SC70-5

2

B

4

Vcc

Y

1

A

G

3

1 2

RV201 0_040 2_5%

NOGC6@

Stuff RV201 if not support GC6

1.35V_PWR_ EN <24,49>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet of

4

Date : Sheet of

Compal Electronics, Inc.

NV(5/5)-MEMORY FBA

LA-E541P

5

2.A

23 51Wednesday, June 21, 2017

2.A

5

D D

+3VS to +3VS_DGPU

RV261 47K_0402_5%

DIS@

1 2

DGPU_MAIN_EN#

RV263

DGPU_MAIN_EN<22,49>

C C

DGPU_MAIN_EN

+3VS to +3VS_DGPU_AON

DGPU_PWR_EN<11,32>

DGPU_PWR_EN

0_0402_5%

1 2

RV264 0_0402_5%

1 2

1

2

+5VALW

RV258 47K_0402_5%

DIS@

1 2

DGPU_PWR_EN#

1

2

CV321

1U_0402_6.3V6K

@

5

CV317

1U_0402_6.3V6K

@

DIS@

RV262 10K_0402_5%

61

QV30A

DIS@

L2N7002DW1T1G 2N SC88-6

RV259 10K_0402_5%

3

QV30B

DIS@

L2N7002DW1T1G 2N SC88-6

4

DIS@

DGPU_MAIN_EN#_GATE

DGPU_PWR_EN#_GATE

4

QV26

DIS@

ME2301DC-G_SOT23-3

D

S

13

G

2

1

0.1U_0201_10V K X5R

2

QV20

DIS@

ME2301DC-G_SOT23-3

D

S

13

G

2

1

0.1U_0201_10V K X5R

2

3

+3VS_DGPU+3VS+5VALW

RV260

470_0603_5%

12

@

1

2

13

D

CV319

4.7U_0402_6.3V6M

CV320

DIS@

CV313

DIS@

CV318

1U_0402_6.3V6K

2

1

@

2

1

1U_0402_6.3V6K

CV312

4.7U_0402_6.3V6M

1

2

@

CV311

@

S

+3VS_DGPU_AON+3VS

D

S

2

G

QV25 2N7002K_SOT23-3

12

RV257

470_0603_5%

@

13

2

G

QV19 2N7002K_SOT23-3

DGPU_MAIN_EN#

@

1.35V_PWR_EN<23,49>

DGPU_PWR_EN#

@

2

G

RV252

100K_0402_1%

12

@

1.35V_PWR_EN#

61

D

QV145A 2N7002KDW_SOT363-6

S

@

+1.35VS_VRAM+5VALW +5VALW

RV251

22_0603_1%

12

@

34

D

QV145B

5

2N7002KDW_SOT363-6

G

S

2

+1.0V_PRIM to +1.0VS_DGPU

@

1 2

@

RV128 0_0402_5%

DGPU_MAIN_EN#

2

G

I_Continuous(Max) : 0.79 A(+1.0VS_DGPU) RON(Max) : 22 mohm V drop : 0.0175 V Rising : ~ 208us

+1.0VALW +1.0VS_DGPU

CV133

0.1U_0201_10V6K

CV314

RV266

47K_0402_5%

DIS@

1 2

DGPU_MAIN_EN_GATEDGPU_MAIN_EN

13

D

QV146 2N7002K_SOT23-3

S

RV85 47K_0402_5%

DIS@

1

@

2

DIS@

1U_0402_6.3V6K

1

DIS@

2

DGPU_MAIN_EN_R_GATE

12

1

QV5

DIS@

ME2320D-G 1N SOT-23-3

1 3

D

S

G

2

0.047U_0402_16V4Z CV315

DIS@

1 2

CV316

0.1U_0201_10V K X5R

1

DIS@

2

B B

DGPU_PWROK<19,23,49>

A A

5

DGPU_PWROK

+1.35VGS_PGOOD

DIS@

1 2

DG4 RB751V-40_SOD323-2

1 2

RG83 0_0402_5 %

+3VS_DGPU_AON

1 2

4

RG82 10K_0402_5%

DIS@

GPU_ALL_PGOOD

GPU_ALL_PGOOD <11>+1.35VGS_PGOOD<49>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

DGPU_DC/DC Interface

Size

Document Number Re v

LA-E541P

Date : Sheet of

1

24 51Wednesday, Jun e 21, 2017

2.A

5

4

3

2

1

Memory Partition A

MF=0 MF=0

UV6

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WC K23#

D4

WCK01 WCK23

P5

WCK23# WC K01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

K4G80325FB-HC03_FBGA170~D @

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14

DQ23 DQ15 DQ8 DQ16 DQ9 DQ17

DQ10 DQ18

DQ11 DQ19

DQ12 DQ20

DQ13 DQ21

DQ14 DQ22

DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

2

G

FBA_D[0..63]

FBA_EDC[7..0]

1 2

RV200 931_0402_1%DIS@

13

D

QV50 2N7002W-T/R7_SOT323-3

DIS@

S

+1.35VS_VRAM

12

RV125 549_0402_1%

DIS@

12

FBA_DBI0<23> FBA_DBI1<23> FBA_DBI2<23> FBA_DBI3<23>

FBA_CLK0<23> FBA_CLK0#<23> FBA_CMD14<2 3> FBA_CMD30<2 3>

FBA_CMD2< 23> FBA_CMD4< 23> FBA_CMD3< 23> FBA_CMD1< 23>

FBA_CMD6< 23> FBA_CMD11<2 3> FBA_CMD10<2 3> FBA_CMD7< 23> FBA_CMD9< 23>

FBA_CMD8< 23> FBA_CMD12<2 3> FBA_CMD0< 23> FBA_CMD15<2 3> FBA_CMD5< 23>

FBA_WCK0#<23> FBA_WCK0<23>

FBA_WCK1#<23> FBA_WCK1<23>

FBA_CMD13<2 3>

+1.35VS_VRAM +1.35VS_VRAM

+FBA_VREFC0

W=16mils

CV159

RV127

1.33K_0402_1%

DIS@

820P_0402_25V7

CV158

820P_0402_25V7

1

DIS@

2

FBA_D[0..63]<23>

FBA_EDC[7..0]<23>

D D

Samsung_X76 6873 8L05

Micron_X76 6873 8L06

C C

B B

MEM_VREF<22>

RV116 1K_0402_1%DIS@ RV118 1K_0402_1%DIS@ RV120 121_0402_1%DIS@

FBA_EDC0 FBA_EDC1 FBA_EDC2 FBA_EDC3

FBA_DBI0 FBA_DBI1 FBA_DBI2 FBA_DBI3

FBA_CLK0 FBA_CLK0# FBA_CMD14

FBA_CMD2 FBA_CMD4 FBA_CMD3 FBA_CMD1

FBA_CMD6 FBA_CMD11 FBA_CMD10 FBA_CMD7 FBA_CMD9

12 12 12

FBA_CMD8 FBA_CMD12 FBA_CMD0 FBA_CMD15 FBA_CMD5

FBA_WCK0# FBA_WCK0

FBA_WCK1# FBA_WCK1

+FBA_VREFC0

FBA_CMD13

Place near pin J14 of each vram

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

FBA_D0

A4

FBA_D1

A2

FBA_D2

B4

FBA_D3

B2

FBA_D4

E4

FBA_D5

E2

FBA_D6

F4

FBA_D7

F2

FBA_D8

A11

FBA_D9

A13

FBA_D10

B11

FBA_D11

B13

FBA_D12

E11

FBA_D13

E13

FBA_D14

F11

FBA_D15

F13

FBA_D16

U11

FBA_D17

U13

FBA_D18

T11

FBA_D19

T13

FBA_D20

N11

FBA_D21

N13

FBA_D22

M11

FBA_D23

M13

FBA_D24

U4

FBA_D25

U2

FBA_D26

T4

FBA_D27

T2

FBA_D28

N4

FBA_D29

N2

FBA_D30

M4

FBA_D31

M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

BYTE0

BYTE1

BYTE2

BYTE3

FBA_CLK0 FBA_CLK0#

Near to VRAM

FBA_CLK1 FBA_CLK1#

Near to VRAM

RV123

80.6_0402_1%

RV175

DIS@

80.6_0402_1%

FBA_DBI4<23> FBA_DBI5<23> FBA_DBI6<23> FBA_DBI7<23>

FBA_CLK1<23> FBA_CLK1#<23>

FBA_CMD18<2 3> FBA_CMD20<2 3> FBA_CMD19<2 3> FBA_CMD17<2 3>

FBA_CMD22<2 3> FBA_CMD27<2 3> FBA_CMD26<2 3> FBA_CMD23<2 3> FBA_CMD25<2 3>

FBA_CMD24<2 3> FBA_CMD28<2 3> FBA_CMD16<2 3> FBA_CMD31<2 3> FBA_CMD21<2 3>

FBA_WCK2#<23> FBA_WCK2<23>

FBA_WCK3#<23> FBA_WCK3<23>

FBA_CMD29<2 3>

DIS@

12

RV117 1K_0402_1%DIS@ RV119 1K_0402_1%DIS@ RV121 121_0402_1%DIS@

FBA_EDC4 FBA_EDC5 FBA_EDC6 FBA_EDC7

FBA_DBI4 FBA_DBI5 FBA_DBI6 FBA_DBI7

FBA_CLK1 FBA_CLK1# FBA_CMD30

FBA_CMD18 FBA_CMD20 FBA_CMD19 FBA_CMD17

FBA_CMD22 FBA_CMD27 FBA_CMD26 FBA_CMD23 FBA_CMD25

12 12 12

FBA_CMD24 FBA_CMD28 FBA_CMD16 FBA_CMD31 FBA_CMD21

FBA_WCK2# FBA_WCK2

FBA_WCK3# FBA_WCK3

+FBA_VREFC0

FBA_CMD29

UV7

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WC K23#

D4

WCK01 WCK23

P5

WCK23# WC K01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

K4G80325FB-HC03_FBGA170~D @

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

FBA_D32

A4

FBA_D33

A2

FBA_D34

B4

FBA_D35

B2

FBA_D36

E4

FBA_D37

E2

FBA_D38

F4

FBA_D39

F2

FBA_D40

A11

FBA_D41

A13

FBA_D42

B11

FBA_D43

B13

FBA_D44

E11

FBA_D45

E13

FBA_D46

F11

FBA_D47

F13

FBA_D48

U11

FBA_D49

U13

FBA_D50

T11

FBA_D51

T13

FBA_D52

N11

FBA_D53

N13

FBA_D54

M11

FBA_D55

M13

FBA_D56

U4

FBA_D57

U2

FBA_D58

T4

FBA_D59

T2

FBA_D60

N4

FBA_D61

N2

FBA_D62

M4

FBA_D63

M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

BYTE4

BYTE5

BYTE6

BYTE7

+1.35VS_VRAM+1.35VS_VRAM

+1.35VS_VRAM

0.1U_0201_10V K X5R

10U_0603_6.3V6M

CV373

CV160

1

DIS@

2

A A

5

1U_0402_6.3V6K

CV162

CV161

1

DIS@

2

4

1U_0402_6.3V6K

CV164

CV163

1

DIS@

@

2

0.1U_0201_10V K X5R

CV165

1

@

2

0.1U_0201_10V K X5R

CV374

CV166

CV167

1

@

2

CV375

1

DIS@

2

0.1U_0201_10V K X5R

CV376

CV377

CV378

1

DIS@

2

3

CV379

1

DIS@

2

1U_0402_6.3V6K

CV380

1

@

@DIS@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.35VS_VRAM

0.1U_0201_10V K X5R

10U_0603_6.3V6M

1U_0402_6.3V6K

CV389

CV381

1

DIS@

2

2017/06/05 2018/06/05

1

DIS@

2

CV169

CV168

1

@

2

Compal Secret Data

2

CV170

1

DIS@

2

Deciphered Date

1U_0402_6.3V6K

CV172

CV173

CV174

CV171

1

DIS@

2

1

@

DIS@

2

CV175

1

@

2

0.1U_0201_10V K X5R

CV382

CV383

1

DIS@

@

2

Title

N16P_GDDR5_A

Size

Document Number Re v

LA-E541P

Date : Sheet of

0.1U_0201_10V K X5R

CV385

CV384

1

DIS@

@

2

Compal Electronics, Inc.

1

0.1U_0201_10V K X5R

CV386

1

@

2

25 51Wednesday, Jun e 21, 2017

0.1U_0201_10V K X5R

CV388

CV387

1

DIS@

2

2.A

5

4

3

2

1

+3VS

W=20mils W=20mils

R201

150K_0402_ 5%

@

R212 0_0603_5%

CMOS_ON#_R

1

@

C204

0.1U_0201_ 10V K X5R

2

Q201 ME2301DC-G_ SOT23-3

S

1 2

DISPOFF#

100K_0402_ 5%

W=60mils

R205

1 2

+LCDVDD_CON N

1

2

C201

4.7U_0402_ 6.3V6M

CMOS_ON#<32>

+3VS

W=60mils

1

C217 1U_0402_6 .3V6K

D D

C C

2

From PCH

From EC

PCH_ENVDD<6>

ENBKL<6,32>

BKOFF#<32>

LCD Power Circuit

12

R202

@

100K_0402_ 5%

R210

100K_0402_ 5%

@

1 2

U202

5

OUT

IN

GND

4

OC

EN

EM5203AJ-20 SOT 23 5P

SA00008R900

2

1

1 2

R204 0_0402_5 %

1

2

3

+3VS

5

P

B

A

G

3

+LCDVDD

R211 0_0805_5 %

U203 TC7SH08FU F_SSOP5

4

Y

@

eDP

1 2

EDP_HPD<6>

100K_0402_ 5%

R207 0_0402_5 %

12

R209

EMI

1 2

R206 0 _0402_5%

B B

USB20_P5<12>

USB20_N5<12>

1 2

R208 0 _0402_5%

EDP_HPD_R

1

UHD_ESD@

C391

0.1U_0201_ 10V K X5R

2

USB20_P5_R

USB20_N5_R

Camera

DMIC

G sensor

+3VS+3VS

12

R286 100K_0402_ 5%@

12

R285

4.7K_0402_5 %@

TS_INT#TS_I2C_RST#

R135

@

10K_0402_5 %

1 2

Touch Panel

1 2

@

D

13

G

2

INVPWM<6>

EDP_AUXN<6> EDP_AUXP<6>

EDP_TXP0<6> EDP_TXN0<6>

EDP_TXP1<6> EDP_TXN1<6>

EDP_TXP2<6> EDP_TXN2<6>

EDP_TXP3<6> EDP_TXN3<6>

EMI

DMIC_CLK<28> DMIC_DAT<28>

EC_SMB_DA4<29,32> EC_SMB_CK4<29,32>

TS_I2C_RST#<6> TS_DISABLE#<32>

TS_INT#<6>

Camera

B+ +LEDVDD

1 2

C206 0 .1U_0201_10V K X5R

1 2

C207 0 .1U_0201_10V K X5R

1 2

C208 0 .1U_0201_10V K X5R

1 2

C209 0 .1U_0201_10V K X5R

1 2

C210 0 .1U_0201_10V K X5R

1 2

C211 0 .1U_0201_10V K X5R

1 2

C213 0 .1U_0201_10V K X5R UHD@

1 2

C212 0 .1U_0201_10V K X5R UHD@

1 2

C214 0 .1U_0201_10V K X5R UHD@

1 2

C215 0 .1U_0201_10V K X5R UHD@

@EMI@

1 2

C216 1 0P_0402_50V8J

1

2

+3VS_CMOS

C202

0.1U_0201_ 10V K X5R

1 2

R203 0_0805_5 %

W=100mils

W=60mils

+LCDVDD_CON N

+3VS_CMOS

W=20mils

+3VS

1

@

C203 10U_0603_ 6.3V6M

2

DISPOFF# EDP_HPD_R

EDP_AUXN_C EDP_AUXP_C

EDP_TXP0_C EDP_TXN0_C

EDP_TXP1_C EDP_TXN1_C

EDP_TXP2_C EDP_TXN2_C

EDP_TXP3_C EDP_TXN3_C

USB20_N5_R USB20_P5_R

TS_I2C_RST# TS_DISABLE# TS_SPI_CLK_C TS_SPI_CS#0_C TS_SPI_SI_C TS_INT# TS_SPI_SO_C

4.7U_0805_25V6-K

C205

1

2

eDP CONN.

JEDP1

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

45

40

G5

44

39

G4

43

38

G3

42

37

G2

41

36

G1 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

ACES_50398-04 041-001

SP010013I00

ME@

TS_SPI_CLK<8>

I2C1_SCL_TS<11>

TS_SPI_CS#0<8>

I2C1_SDA_TS<11>

A A

TS_SPI_SI<8>

TS_SPI_SO< 8>

5

TS_SPI_CLK

I2C1_SCL_TS

TS_SPI_CS#0

I2C1_SDA_TS

TS_SPI_SI

TS_SPI_SO

1 2

R218 3 3_0402_5%

TS_SPI@

1 2

R214 0 _0402_5%

1 2

R217 3 3_0402_5%

TS_SPI@

1 2

R213 0 _0402_5%

1 2

R219 3 3_0402_5%

TS_SPI@

1 2

R220 3 3_0402_5%

TS_SPI@

TS_SPI_CLK_C

TS_SPI_CS#0_C

TS_SPI_SI_C

TS_SPI_SO_C

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet of

Compal Electronics, Inc.

eDP / Camera

Custom

eDP / Camera

LA-E541P

1

26 51Wednesday, June 21, 2017

2.A

5

4

3

2

1

EMI

1 2

HDMI_CLK+_CK<6>

D D

HDMI_CLK-_CK<6>

HDMI_TX0+_CK<6>

HDMI_TX0-_CK<6>

HDMI_TX1+_CK<6>

HDMI_TX1-_CK<6 >

CH13 0.1U _0201_10V K X5R

1 2

CH14 0.1U _0201_10V K X5R

1 2

CH15 0.1U _0201_10V K X5R

1 2

CH16 0.1U _0201_10V K X5R

1 2

CH17 0.1U _0201_10V K X5R

1 2

CH18 0.1U _0201_10V K X5R

HDMI_CLK+_CK _C

HDMI_CLK-_CK_ C

HDMI_TX0+_CK_ C

HDMI_TX0-_CK_C

HDMI_TX1+_CK_ C

HDMI_TX1-_CK_C

1 2

RH11 8.2_0402 _1%EMI@

1 2

RH15 8.2_0402 _1%EMI@

1 2

RH17 8.2_0402 _1%EMI@

1 2

RH18 8.2_0402 _1%EMI@

1 2

RH19 8.2_0402 _1%EMI@

1 2

RH20 8.2_0402 _1%EMI@

HDMI_CLK+_CON N

HDMI_CLK-_CON N

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_CLK+_CON N HDMI_CLK-_CON N

HDMI_TX0+_CONN HDMI_TX0-_CONN

HDMI_TX1+_CONN HDMI_TX1-_CONN

HDMI_TX2+_CONN HDMI_TX2-_CONN

EMI

1 2

RH12 150_0 402_5%EMI@

1 2

RH13 150_0 402_5%EMI@

1 2

RH14 150_0 402_5%EMI@

1 2

RH16 150_0 402_5%EMI@

@

CH12

0.1U_0201_ 10V K X5R

+5VS

1

2

For HDMI

UH11

1

IN

G5250Q1T73 U_SC59-3

GND

+5V_Display

W=40mils

3

OUT

2

1

CH11

0.1U_0201_ 10V K X5R

2

1

2

4

5

3

RH23

+3VS

12

QH14

G

2

2N7002K_SOT 23-3

13

D

S

HDMICLK_RHDMICLK_R

HDMIDAT_RHDMIDAT_R

12

RH24 20K_0402_5 %

9

HDMI_TX2-_CONN HDMI_TX2-_CONN

8

7

6

L05ESDL5V0NA-4 SLP2510P8 ESD

HDMI_DET

+5V_Display

HDMIDAT_R HDMICLK_R

HDMI_CLK-_CON N

HDMI_CLK+_CON N HDMI_TX0-_CONN

HDMI_TX0+_CONN HDMI_TX1-_CONN

HDMI_TX1+_CONN HDMI_TX2-_CONN

HDMI_TX2+_CONN

DH12

@ESD@

HDMI_TX1-_CONNHDMI_TX1-_CONN

1

10

9

7

6

1

HDMI_TX1+_CONNHDMI_TX1+_CONN

2

4

HDMI_TX2+_CONNHDMI_TX2+_CONN

5

3

8

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Utility

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

ACON_HMRBL-AK12 0D

DC2320047 00

ME@

23

GND1

22

GND2

21

GND3

20

GND4

DH13

HDMI_TX0-_CONN

HDMI_TX0+_CONN

HDMI_CLK-_CON N HDMI_C LK-_CONN

HDMI_CLK+_CON N HDMI_CLK+_CON N

@ESD@

9

10

8

9

7

6

L05ESDL5V0NA-4 SLP2510P8 ESD

1

2

4

5

3

8

HDMI_TX0-_CONN

HDMI_TX0+_CONN

+3VS

2

G

QH17 2N7002K_SOT 23-3

HDMI_TX2+_CONN

HDMI_TX2-_CONN

1M_0402_5 %

TMDS_B_HPD<6>

DH11

@ESD@

9

10

8

HDMI_DET HDMI_DET

+5V_Display +5V_Displ ay

9

7

6

L05ESDL5V0NA-4 SLP2510P8 ESD

1

2

4

5

3

8

1 2

C C

HDMI_TX2+_CK<6>

HDMI_TX2-_CK<6 >

CH19 0 .1U_0201_10V K X5R

1 2

CH20 0 .1U_0201_10V K X5R

HDMI_TX2+_CK_ C

HDMI_TX2-_CK_C

1 2

RH21 8.2_0402 _1%

EMI@

1 2

RH22 8.2_0402 _1%

EMI@

Near JHDMI1

RPH11

45 36 27 18

470 +-5% 8P4 R

RPH12

45 36 27 18

470 +-5% 8P4 R

B B

+3VS +5V_Display

2.2K_0402_5%

12

RH26

HDMICLK_NB<6>

HDMIDAT_NB<6>

A A

+3VS

2.2K_0402_5%

12

RH25

5

4

QH15B 2N7002KDW 2N SC88-6

QH15A

2

2N7002KDW 2N SC88-6

61

3

13

D

S

2.2K_0402_5%

12

RH27

RH28

HDMICLK_R

HDMIDAT_R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

2

Date : Sheet of

HDMI

LA-E541P

1

2.A

27 51Wednesday, June 21, 201 7

2.A

A

ALC3240

+1.8VS

4.7U_0402_ 4V6M CA40

@

1 1

wide 40MIL

2 2

HDA_SDIN0<9>

+MIC2-VREFO

HDA_SDOUT_AUD IO<9>

HDA_BITCLK_AUDIO<9>

@EMI@

CA5222P_04 02_50V8J

1 2

RA58 2.2K _0402_5%

1 2

RA54 2.2K _0402_5%

GNDA

CA63 2.2U_0 402_6.3V6M

GNDA GNDA

HDA_SYNC_AUDIO<9 >

12

RA5233_0402_5%

PC_BEEP

EXT_MIC_RING2 EXT_MIC_SLEEVE

12

SPK_L2+ SPK_L1SPK_R1SPK_R2+

1 2

HDA_SDIN0_AUDIO

12

CA612.2U_0402_ 6.3V6M

CA642.2U_0402_ 6.3V6M

CA512.2U_0402_ 6.3V6M

+5VS to +5VDDA_CODEC

+5VS

RA48 0_0603_ 5%

3 3

Place RA48 on GNDA moat

12

Place near Pin20

+5VDDA_CODEC

1

CA58

2

1U_0402_6.3V6K

GNDA

1

CA55

2

0.1U_0201_10V K X5R

UA1

7

SDATA-IN

4

SDATA-OUT

11

PCBEEP

5

RA5033_0402_5% @EMI@

BCLK

13

MIC2-L(PORT-F-L)/RING

14

MIC2-R(PORT-F-R)/SLEEVE

15

MIC2-CAP

23

MIC2-VREFO

35

SPK-OUT-LP

36

SPK-OUT-LN

37

SPK-OUT-RN

38

SPK-OUT-RP

21

LDO1

LDO1-CAP

32

LDO2

LDO2-CAP

6

LDO3

LDO3-CAP

10

DC DET

9

SYNC

ALC3240-VA3-CG_MQFN 40_5X5

Each Platform Power Net Support List：：：：

Each Platform HDA Link Voltage Support (Pin 8)：：：：

+5VDDA_CODEC

Intel Broadwell

Intel Skylake

Intel Broadwell

Intel Skylake

+3VDD_CODEC

2

1

29

CPVDD

AVDD120AVSS1

33

B

+5VS_PVDD

2

1

CA53

CA1

1

2

4.7U_0402_6.3V6M

0.1U_0201_10V K X5R

34

39

DVDD

HPOUT-L(PORT-I-L)

PVDD1

PVDD2

HPOUT-R(PORT-I-R)

VREF

CPVEE

LINE1-R(PORT-C-R)

LINE1-L(PORT-C-L)

LINE1-VREFO-L

HP/ LINE1-JD(JD1)

GPIO0/DMIC-DATA12

GPIO1/DMIC-CLK

DVDD-IO

CBN CBP

PDB

THERMAL PAD

AVDD2

AVSS2

VD33STB

31

19

16

+3VALW

GNDA

1 2

RA53 0_ 0402_5%

1 2

CA60 1U_0402_6.3V6K

2

CA66

1

25 26

22 27

CPVEE

17 18 24 12

2

DMIC_CLK_R

3

8

28 30

40

PDB

41

+1.8VS

Place RA53 on GNDA moat

1 2

RA2 0_0805_ 5%

1

CA49

2

4.7U_0402_6.3V6M

0.1U_0201_10V K X5R

Headphone

HP_OUTL HP_OUTR

1 2

CA68 1U_040 2_6.3V6K

CA70 1U_040 2_6.3V6K

LINE1-R LINE1-L

PLUG_IN_R

1 2

RA46 0_ 0402_5%

GNDA

12

+LINE1-VREFO-R

LA9 220_0402_ 5%EMI@

+IOVDD_CODEC

1

CA57 1U_0402_6 .3V6K

2

Place near Pin33

+1.5V S +1.8 VS +3VS +5VS +3VA LW

1.5V(S0) 1.8V(S 0) 3.3V (S0) 5V(S0) 3.3V(S0 ~S5)

X

V V VV

3.3V 1.5V

V (default) V

+5VS

12

GNDA

EMI

RA43 10K_0402_5 %

1 2

C

@

External DMIC

DMIC_DAT <26> DMIC_CLK <26>

EC_MUTE# < 32>

VVVV

D

Input

EMI

W=40mils W=40mils

EXT_MIC_SLEEVE EXT_MIC_RING2 HP_OUTL HP_OUTR

For Universal Audio Jack

LINE1-L

CA46 1U_040 2_6.3V6K

LINE1-R

CA54 1U_040 2_6.3V6K

RA36 4.7K_0 402_5%

+LINE1-VREFO-R

HGNDA / HGNDB , W=60mils

HGNDB HPOUT_L HPOUT_L 1

PLUG_IN HPOUT_R HPOUT_R1

HGNDA

RA49 4.7K_0 402_5%

@

1 2

RA63 0_04 02_5%

@

1 2

RA64 0_04 02_5%

1 2

@ESD@

RA42 FBMA-L11-160 808-121LMT 060 3EMI@ RA31 FBMA-L11-160 808-121LMT 060 3EMI@

12

DA8

L03ESDL5V0CC3-2_SOT23-3

2

3

1

3

SCA00002900

ESD@

Output

SPEAK 4 ohm : 40MIL SPEAK 8 ohm : 20MIL

SPK_R1SPK_R2+ SPK_L1SPK_L2+

1 2

LA5 0_0603_5%

1 2

LA6 0_0603_5%

1 2

LA7 0_0603_5%

1 2

LA8 0_0603_5%

EMI

ESD protection needs to be placed near connector side

DA3

SPK_R1-_CONN SPK_L2+_CONN

+5VS

SPK_R2+_CON N

ESD

@ESD@

6

I/O4

I/O2

5

VDD

GND

4

I/O3

I/O1

AZC099-04S.R7G_ SOT23-6

3

2

1

1 2

EMI@

1

CA65

2

470P_0402_50V7K

EMI@

1

2

E

CA50

Combo Jack (Normal Open)

EMI@

CA56

1 2

220P_0402_50V7K

470P_0402_50V7K

1 2

place close audio codec

+3VDD_CODEC

RA51 100K_0402_ 1%

1 2

PLUG_IN_R PLUG_IN

12 12

RA45 47 _0402_5%EMI@ RA56 47 _0402_5%EMI@

@

RA44

RA57

1 2

10K_0402_5%

GNDA GNDA GNDA GN DA GNDA GNDA

1 2 1 2

RA23 20 0K_0402_1%

Combo Jack (Normal Open)

JHP1

ME@

3 1

5

6 2

4

CA71

1000P_0402_50V7K

EMI@

7

1

CA47

2

1000P_0402_50V7K

EMI@

SINGA_2SJ3095-067 111F

DC23000DY00

1

2

1000P_0402_50V7K

JSPK1

6

GND2

5

GND1

4

3

2

1

ACES_50271-00 40N-001

SP02000TS0 0

DA9

L03ESDL5V0CC3-2_SOT23-3

2

SCA00002900

1

SPK_R1-_CONN SPK_R2+_CON N SPK_L1-_CONN SPK_L2+_CON N

SPK_L1-_CONN

33K_0402_5%

12

RA62

@ESD@

1

CA67

CA45

2

1000P_0402_50V7K

EMI@

HGNDB HGNDA

HPOUT_L HPOUT_R

EMI@

CA59

220P_0402_50V7K

ME@

+3VS to +IOVDD_CODEC

+3VS

4 4

RA6 0_0603_ 5%

12

Place near Pin8

1

CA48

2

0.1U_0201_10V K X5R

A

+3VS to +3VDD_CODEC

+3VDD_CODEC+ 3VS+IOVDD_CODEC

RA59 0_06 03_5%

12

Place near Pin1

1

CA62

2

0.1U_0201_10V K X5R

PC Beep

1 2

RA41 47 K_0402_5%

EC Beep APU Beep

12

CA44

1U_0402_6.3V6K

B

BEEP#<32>

HDA_SPKR<9>

1 2

RA55 47 K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

place close audio codec

BEEP_N

1

2

GNDA

100P_0402_50V8J

12

CA69 0.1U_0 402_10V7K

CA43

12

RA47

@ESD@

27K_0402_5 %

2017/06/05 2018/06/05

PC_BEEP

Compal Secret Data

Deciphered Date

D

EMI

GND

Title

Size Document Number Re v

Custom

Date : Sheet of

EMI@

1 2

CA41 0.1U_0201_ 10V K X5R

1 2

RA60 0_ 0402_5%

1 2

RA61 0_ 0402_5%

EMI@

1 2

CA42 0.1U_0201_ 10V K X5R

GNDA

Compal Electronics, Inc.

HD Audio Codec_ ALC3240

LA-E541P

E

2.A

28 51Wednesday, June 21, 2017

2.A

A

B

C

D

E

F

G

H

HDD

1 1

Near Connector

1

2

SATA_PTX_C_DRX_P0 SATA_PTX_C_DRX_N 0

SATA_PRX_C_DTX_N 0 SATA_PRX_C_DTX_P0

+3V_HDD

+5V_HDD

12

R420 0_0402_5%

1 2

SATA_PTX_DRX_P0<1 2>

Near HDD

+5V_HDD

10U_0603_6.3V6M

0.1U_0201_10V K X5R

1000P_0402_50V7K

C237

1

@

2 2

2

C238

C232

1

2

(G-Sensor for 360-degree reverse)

3 3

+3VS

1 2

R231 0_0402_5 %

0.1U_0201_10V K X5R

YOGA@

2

C231

1

U231 YOGA@

7

VDD

10

CSB

5

INT1

6

INT2

EC_SMB_DA4<26,32> EC_SMB_CK4<26,32>

2

SDx SCx12GNDIO

BMA250E_LGA12

VDDIO

SDO GND

+3VS

3 11

PS

4

NC

1 9 8

0.1U_0201_10V K X5R

@

2

C240

1

SATA_PTX_DRX_N0<12>

SATA_PRX_DTX_N0<12> SATA_PRX_DTX_P0<12>

Finger Printer

C233 0.01U_040 2_16V7K

1 2

C234 0.01U_040 2_16V7K

1 2

C235 0.01U_040 2_16V7K

1 2

C236 0.01U_040 2_16V7K

1 2

R232 0 _0805_5%@

+3VS

1 2

R233 0_0805_5 %

+5VS

ESD

D202

9

10

8

USB20_P6 USB20_P6

USB20_N6 USB20_N6

9

7

6

L05ESDL5V0NA-4 SLP2510P8 ESD

0.1U_0201_ 10V K X5R

@ESD@

FP_ESD@

1

2

4

5

3

8

C239

SMB Address: 0001 1000

USB20_N6<12> USB20_P6<12>

JHDD1

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12 V1222GND

SDAN_603006 -022041

DC01000CE 00

ME@

GND

USB20_N6 USB20_P6

24 23

+3VS

12

R234 0_0402_5%

+3VS_FP+3VS_GS_R

JFP1

1

2

3

4

9

4

GND

10

55GND

6

7

8

ACES_51580-00 841-P01

SP01002GM00 ME@

SATA HDD Conn.

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/06/05 2018/06/05

E

Compal Secret Data

Deciphered Date

F

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet of

G

Compal Electronics, Inc.

HDD/FP/G-Sensor

Custom

LA-E541P

29 51Wednesday, June 21, 2017

H

2.A

A

B

C

D

E

NGFF for WLAN / BT (E- KEY)

1 1

+3VS +3VS_WLAN

1 2

R242 0_0805_5 %

1

C243

4.7U_0402_ 6.3V6M

2

2 2

@

1

C244

0.1U_0201_ 10V K X5R

2

JWLAN1

1

GND

BT

WLAN

3 3

4 4

USB20_P7<12>

USB20_N7<12>

PCIE_PTX_C_DRX_P6<12> PCIE_PTX_C_DRX_N 6<12>

PCIE_PRX_DTX_P6<12> PCIE_PRX_DTX_N6<12>

CLK_PCIE_WL AN< 10>

CLK_PCIE_WL AN#<10>

WLANCLK_R EQ#<10>

PCIE_WAKE#<32>

1 2

R246 0 _0402_5%

1 2

R249 0 _0402_5%@

WLANCLK_R EQ#_R

WAKE#_R

3

USB_D+

5

USB_D-

7

GND

9

SIDO_CLK

11

SDIO_CMD

13

SDO_DAT0

15

SDO_DAT1

17

SDO_DAT2

19

SDO_DAT3

21

SDIO_WAKE#

23

SDIO_RESET#

33

GND

35

PETP0

37

PETN0

39

GND

41

PERP0

43

PERN0

45

GND

47

REFCLKP0

49

REFCLKN0

51

GND

53

CLKEQ0#

55

PEWAKE0#

57

GND

59

RSRVD/PETP1

61

RSRVD/PETN1

63

GND

65

RSRVD/PERP1

67

RSRVD/PERN1

69

GND

71

RESERVED

73

RESERVED

75

GND

77

MTG77

LOTES_APCI0128-P0 05A

SP070011H0 0 ME@

PCM_CLK

PCM_SYNC

PCM_OUT

UART_WAKE#

UART_RX

UART_TX UART_CTS UART_RTS

RESERVED RESERVED RESERVED

PERST0# W_DISABLE2# W_DISABLE1#

I2C_DATA

RESERVED RESERVED RESERVED RESERVED

3.3VAUX

3.3VAUX LED1#

PCM_IN

LED2#

GND

COEX3 COEX2 COEX1

SUSCLK

I2C_CLK

ALERT

3.3VAUX

MTG76

+3VS_WLAN

2 4 6 8 10 12 14 16 18 20 22

32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74

76

R251

100K_0402_ 5%

WL_UART_ RX

WL_UART_ TX

1 2

1 8 2 7 3 6 4 5

1 2

R243 0_0 402_5%

1 2

R244 0_0 402_5%

SUSCLK_R WL_RST # BT_DISABLE_R

Note: The real behavior of BT_DISABLE are BT_DISABLE=LOW, BT=OFF

BT_DISABLE=HIGH, BT=ON

R252

100K_0402_ 5%

@

1 2

R245 0_0 402_5%

1 2

R247 0_0 402_5%

1 2

R248 0_0 402_5%

RP241

@

0_0804_8P4 R_5%

WL_RST #

UART for intel debugging in WIN7

UART0_TX <11>

UART0_RX <1 1>

EC_TX <3 2> EC_RX <32>

SUSCLK <10>

WLBT_OFF# <11>

WL_OFF# <12>

1 2

R250 0_0402_5%

PCI_RST# <10,19,31,32 ,35>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

NGFF WLAN / BT

LA-E541P

E

30 51Wednesday, June 21, 2017

2.A

A

B

C

D

E

NGFF for SSD (M-KEY)

1 1

+3VS +3VS_SSD

1 2

R261 0_0805_5 %

10U_0603_6.3V6M

C261

C263

1

SSD@

2

@

0.01U_0402_16V7K

0.1U_0201_10V6K

C264

C262

1

@

SSD@

2

2 2

JSSD1

1

GND

3

GND

PCIE_PRX_DTX_N9<12>

PCIE_PRX_DTX_P9<12>

PCIE_PTX_C_DRX_N 9<12>

PCIE_PTX_C_DRX_P9<12>

PCIE_PRX_DTX_N10<12>

PCIE_PRX_DTX_P10<12>

PCIE_PTX_C_DRX_N 10<12>

PCIE_PTX_C_DRX_P1 0<12>

PCIE_PRX_DTX_N11<12>

PCIE_PRX_DTX_P11<12>

PCIE_PTX_C_DRX_N 11<12>

PCIE_PTX_C_DRX_P1 1<12>

PCIE_PRX_DTX_P12<12>

PCIE_PRX_DTX_N12<12>

PCIE_PTX_C_DRX_N 12<12>

PCIE_PTX_C_DRX_P1 2<12>

CLK_PCIE_SSD#<1 0>

CLK_PCIE_SSD<10>

3 3

4 4

5

PERn3

7

PERp3

9

GND

11

PETn3

13

PETp3

15

GND

17

PERn2

19

PERp2

21

GND

23

PETn2

25

PETp2

27

GND

29

PERn1

31

PERp1

33

GND

35

PETn1

37

PETp1

39

GND

41

PERn0/SATA-B+

43

PERp0/SATA-B-

45

GND

47

PETn0/SATA-A-

49

PETp0/SATA-A+

51

GND

53

REFCLKN

55

REFCLKP

57

GND

67

NC PEDET(NC-PCIE/GND-SATA)693P3VAUX

71

GND

73

GND

75

GND

LOTES_APCI0079-P0 05A

SP07001EZ00

ME@

SUSCLK(32kHz)

3P3VAUX 3P3VAUX

DAS/DSS#

3P3VAUX 3P3VAUX 3P3VAUX 3P3VAUX

DEVSLP

PERST#

CLKREQ#

PEWake#

3P3VAUX 3P3VAUX

GND1 GND2

2 4 6

NC

8

NC

10 12 14 16 18 20

NC

22

NC

24

NC

26

NC

28

NC

30

NC

32

NC

34

NC

36

NC

38 40

NC

42

NC

44

NC

46

NC

48

NC

50 52 54 56

NC

58

NC

68 70 72 74

76 77

PCI_RST#

+3VS_SSD

PCI_RST# <10,19,30,32 ,35>

SSDCLK_REQ# <10>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

NGFF SSD

LA-E541P

E

31 51Wednesday, June 21, 2017

2.A

+3VALW_EC

KSO[0..15]<3 3>

+3VALW_EC

+3VALW

ESD

@

C116

0.1U_0201_ 10V K X5R

+3VS

+3VALW_EC

KSI[0..7]< 33>

R108

1 2

2.2K_0402_5 %

R109

1 2

2.2K_0402_5 %

R117

1 2

1K_0402_5%

R106

1 2

10K_0402_5 %

@

1

2

1 2

R118 10K_0402_5%

1 2

0.1U_0201_ 10V K X5R

1 2

R104 47K_0402_5%

KSO[0..15]

KSI[0..7]

EC_SMB_CK1

EC_SMB_DA1

PCIE_WAKE#

PBTN_OUT#

PCH_PWR OK<10>

EC_FAN_SPEED1

L101 BLM15AX601SN1D _2P

SM01000KL0 0

C106

L102 BLM15AX601SN1D _2P

SM01000KL0 0

+3VL

EMI

@EMI@

12

C108 22P_04 02_50V8J

C109

0.1U_0201_ 10V K X5R

PCIE_WAKE#<30>

+EC_VCCA

1

C107

@

1000P_0402 _50V7K

2

ECAGND

R125 100K_0402_5%

@EMI@

R103 10_0402_ 1%

12

PCI_RST#<10,19,3 0,31,35>

2

1

12

ESD@

ESD

R101

1 2

0_0402_5%

C121

100P_0402_50V8J

R113

@

1

@ESD@

2

1 2

10K_0402_5 %

Share ROM

+3VL +3VL

1 2

R102 0_0603_5 %

C102

0.1U_0201_10V K X5R

C103

0.1U_0201_10V K X5R

1

2

12

NOVO#<35>

CC_LINK<34>

SERIRQ<8>

LPC_FRAME#<8>

LPC_AD3<8> LPC_AD2<8> LPC_AD1<8> LPC_AD0<8>

CLK_LPC_EC<8>

EC_SCI#<6,10>

3V/5VALW_PG<35,37,41,4 3>

0.1U_0402_16V7K

C110

TYPEC_PWR _DIS#<34> TP_DISABLE# <33> 5VLDO_EN<41>

EC_SMB_CK1<39,40> EC_SMB_DA1<39,40> EC_SMB_CK2<8,22 ,36> EC_SMB_DA2<8,22 ,36>

USB_CHG_ST ATUS#<35 >

USB_CHG_CT L1<35> EC_CLEAR_CMO S#<10>

USB_CHG_CT L3<35> USB_CHG_EN<35>

USB_CHG_CT L2<35>

KB_BL_PW M<33>

EC_FAN_SPEED1<36>

VCIN1_AC_IN<40>

EC_TX<30> EC_RX<30>

PBTN_OUT#<10>

PM_SLP_S4#<10,40,4 2>

CMOS_ON#<26>

EC_RST# EC_SCI#

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

EC_PCIE_WAKE#

PCH_PWR OK

+3VALW_EC

C104

1000P_0402_50V7K

C105

1000P_0402_50V7K

1

2

@

U11

1 2 3 4 5 7 8

10

12 13 37 20 38

55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82

77 78 79 80

6 14 15 16 17 18 19 25 28 29 30 31 32 34 36

122 123

NPCE388NA1D X LQFP 128P KBC

2

@

GPIO85/GA20 GPIO86/KBRST# SERIRQ/GPIOF0 LFRAME#/GPIOF6 LAD3/GPIOF4 LAD2/GPIOF3 LAD1/GPIOF2

LPC & MISC

LAD0/GPIOF1

LCLK/GPIOF5 LRESET#/GPIOF7 ECRST# GPIO54/ECSCI# GPIO11/CLKRUN#

KBSIN0/GPIOA0 KBSIN1/GPIOA1 KBSIN2/GPIOA2 KBSIN3/GPIOA3 KBSIN4/GPIOA4/N2TCK KBSIN5/GPIOA5/N2TMS KBSIN6/GPIOA6 KBSIN7/GPIOA7 KBSOUT0/GPIOB0/SOUT_CR/JENK# KBSOUT1/GPIOB1/TEST# KBSOUT2/GP(I)OB2/TRIST# KBSOUT3/GP(I)OB3/XORTR# KBSOUT4/GPIOB4/SDP_VIS# KBSOUT5/GPIOB5/TDO KBSOUT6/GPIOB6/RDY# KBSOUT7/GPIOB7 KBSOUT8/GPIOC0 KBSOUT9/GPIOC1 KBSOUT10&P80_CLK/GPIOC2 KBSOUT11&P80_DAT/GPIOC3 KBSOUT12/GPIO64/TCK KBSOUT13/GPIO63/TMS KBSOUT14/GPIO62/TDI KBSOUT15/GPIO61/XOR_OUT GPIO60/KBSOUT16 GPIO57/KBSOUT17

GPIO17/SCL1/N2TCK GPIO22/SDA1/N2TMS GPIO73/SCL2 GPIO74/SDA2

GPIO24 GPIO10/LPCPD# GPIO65/SMI# GPIO34/1_WIRE/CIRRXL GPIO01/TB2 GPIO43 GPIO42/CIRTX2 GPIO13/C_PWM GPIO56/TA1 GPIO14/TB1 GPIO83/SOUT_CR/P80_DATA GPIO87/SIN_CR/P80_CLK GPIO27/RSMRST# GPIO66/G_PWM GPIO33/H_PWM

GPIO00/EXTCLK GPIO55/CLKOUT/IOX_DIO

22

9

VCC1/LPC

SM Bus

11

+EC_VCCA

33

96

111

125

VSBY

VCC2

VCC3

VCC4

VCC5/SPI

PWM Output

AD Input

DA Output

PS2 Interface

Int. K/B Matrix

SPI Flash ROM

GPIO

GND1

GND2

GND3

GND4

GND5

24

35

94

113

1

C101 100P_0402_ 50V8J

@

2

67

AVCC

GPIO15/A_PWM GPIO21/B_PWM GPIO32/D_PWM GPIO45/E_PWM

GPIO90/AD0 GPIO91/AD1 GPIO92/AD2 GPIO93/AD3 GPIO05/AD4 GPIO04/AD5

GPIO94/DA0 GPIO95/DA1 GPIO96/DA2 GPIO97/DA3

GPIO31/SCL3/PSCLK1 GPIO23/SDA3/PSDAT1 GPIO47/SCL4/PSCLK2 GPIO53/SDA4/PSDAT2

GPIO50/PSCLK3 GPIO52/PSDAT3

GPIO02 GPIO75

GPIO

GPIO76

VCIN1/GPIO16

F_SDI&F_SDIO1/GPO80

F_SDIO&F_SDIO0/GPIOC6

F_CLK/GPIOC4

F_CS0#/GPIOC5

GPIO03/AD6/CIRRXM

GPIO07/AD7/CIRTX1

GPIO67/N2TMS

GPIO51/N2TCK

GPIO36

GPIO40/F_PWM

GPIO35

GPIO06/IOX_DOUT

GPIO81/F_WP#

GPIO84/IOX_SCLK

GPIO26/RSMRST#

GPIO20/TA2/IOX_DIO

VC_IN2/GPIO72 VC_OUT2/GPIO37 VC_OUT1/GPIO25

GPIO77 GPIO44 GPIO12

GPIO30/F_WP#

AC_IN/GPIO41/F_WP#

EC_ON/GPIO71

ON_OFFBTN#/GPIO70

GPO82/IOX_LDSH/LIDIN

GPIO46/CIRRXM/PLCIN

PECI

VCORF

AGND

69

VTT

21 23

BEEP#

26

EC_VCIN1_AC_BYPASS

27

63 64 65 66 75 76

68 70 71 72

83 84

EC_SMB_CK4_ R

85

EC_SMB_DA4_R

86 87 88

97 98 99 109

119 120 126 128

73 74 89 90 91 92 93 95

SYSON USB_CHG_ILIM_SEL

121

SENSOR_EC_INT

127

YOGA only

100 101 102

VCOUT1_PROCH OT#

103 104 105

BKOFF#

106 107 108

EC_VCIN1_AC_BYPASS

110

EC_ON

112 114

LID_SW#

115 116

SUSP# NUVOTON_VTT

117 118

PECI

124

+V18R

4.7U_0402_6.3V6M

R123 0_0402_5% R124 0_0402_5%

CUST_TEMP 1 <36>

1 2

R115 0_0402_5 %@

C114

1

2

BEEP# <28> EC_FAN_PWM 1 < 36>

VCIN1_BATT_TEMP <39,40 >

VCIN1_BATT_DROP <41>

ADP_I <4 0>

CUST_TEMP 2 <36>

TAB_SW# <33> TS_DISABLE# <26> DGPU_PWR _EN <11,24>

USB_EN# <35>

1 2 1 2

DIR_SET <34>

ENBKL <6,2 6>

SYS_PWROK <10>

ME_EN < 9>

VCIN0_PH1 <39>

EC_SPI_MISO <8> EC_SPI_MOSI <8> EC_SPI_CLK <8> EC_SPI_CS0# <8 >

CAPS_LED# <33>

PWR_LED # <33,35,36 >

SYSON <13,42> USB_CHG_ILIM_SEL <35 >

SENSOR_EC_INT <11>

EC_RSMRST# <10>

GPU_PROHOT# <2 2> VCOUT1_PROCH OT# <40> VCOUT0_MAIN_PW R_ON <41>

BKOFF# <26>

PM_SLP_S3# <10>

VR_ON <46>

EC_VCIN1_AC_BYPASS <10,22> EC_ON < 35,41>

ON/OFF# <33 ,35>

LID_SW# <33,35>

SUSP# <13 ,37,42>

R114 43_0402_1%

+3VALW_EC

7/26 update

YOGA only

1 2

R107 10K_0402 _5%@

EC_MUTE# <2 8>

1

2

H_PECI <6>

C120

100P_0402_50V8J

1

@ESD@

2

I2C2_SCL_SEN <11> I2C2_SDA_SEN <11> EC_SMB_CK4 <26,29 > EC_SMB_DA4 <26,29 >

C117

100P_0402_50V8J

1

@ESD@

2

VCCST_PWR GD <10>

+3VALW

C118

@ESD@

C119

100P_0402_50V8J

1

@ESD@

2

YOGA only

BATT_CHG_LE D# <36>

BATT_LOW_ LED# <36>

VR_PWRGD <46>

USB_EN#

VCIN1_BATT_TEMP

VCIN1_AC_IN

EC_SMB_CK4 EC_SMB_DA4

I2C2_SCL_SEN I2C2_SDA_SEN

KBL_SELECT

KB_BL_PW M

ON/OFF#

NUVOTON_VTT

SUSP#

1 2

R105 10K_0402 _5%

1 2

C111 100P _0402_50V8J

1 2

C112 100P _0402_50V8J

1 2

R110 4 .7K_0402_5%@

1K_0804_8P 4R_5%

4 5 3 6 2 7 1 8

RP101

YOGA@

1K_0804_8P 4R_5%

4 5 3 6 2 7 1 8

RP102

YOGA@

+3VALW

10K_0402_5%

12

R130

YOGA@

KB_MUTLI_KEY <33 >

Funct i on

KBL

NO KBL

KBL_ID

1

0

1 2

R282 100K_040 2_5%

1 2

R116 0_0402_5%

1 2

R128 100K_040 2_5%

+1.8VS

+5VALW

+3VS

12

R121 10K_0402_5 %

NOKBL@

+3VL

+1.0V_VCCST

Testing Only

JP1

JP2

@

SHORT PADS

@

SHORT PADS

ECAGND

12

ON/OFF#

12

ON/OFF#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/06/05 2018/06/05

SYSON

ESD@

C115

1

2

0.1U_0201_10V K X5R

Compal Secret Data

Deciphered Date

ESD

VCOUT1_PROCH OT#

VR_HOT#<46>

1 2

R111 0_0402_5 %

1 2

R112 0_0402_5 %

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

Compal Electronics, Inc.

EC NPCE388

1

ESD@

C113 100P_0402_ 50V8J

2

LA-E541P

H_PROCHOT# <6>

2.A

32 51Wednesday, June 21, 2017

2.A

Keyboard Backlight

R278

0_0402_5%

+5VALW +VCC_KB_LED+5VS

12

R276 10K_0402_5 %

@

2

IN

+5VS

12

R275 10K_0402_5 %

KBL@

1 2

KB_BL_PW M<32>

Q271

S

R277

1 2

30K_0402_1 %

KBL@

1

OUT

@

GND

Q272

DTC124EKAT1 46_SC59-3

3

D

13

ME2301DC-G_ SOT23-3

G

KBL@

2

0.01U_0402_16V7K

C278

1

KBL@

2

Keyboard

CAPS_LED#<32>

JKBL1

1

C279

CVILU_CF5004FD0 RD-10-NH

2

3

4

5

GND

6

GND

LTCX007VP00 ME@

0.1U_0201_10V K X5R

10U_0603_6.3V6M

C277

1

KBL@

@

2

R283

KSI[0..7]

KSO[0..15]

0_0402_5%

SD0280000 80

S_AL@

R272

PWR_LED #<32,35 ,36>

KB_MUTLI_KEY<32>

ON/OFF#<32,35>

866_0402_ 1%

SD0348660 80

S_AL@

KSI[0..7] < 32>

KSO[0..15] < 32>

R271 866_0402 _1%

KB_MUTLI_KEY SELECT

Funct i on

Power Key (Cruze )

Funct i on Key (Alpine)

BOM control

S_IMR@

S_AL@

YOGA@

12

@ESD@

12

C272 0 .1U_0201_10V K X5R

1 2

12

R272 866_0402_ 1%S_IMR@

R284 0_0402_5%YOGA@

R283 0_0402_5%S_IMR@

+5VALW

@ESD@

JKB1

1

2

3

D303

KSO15

3

4

KSO10

4

5

KSO11

5

6

KSO14

6

7

KSO13

7

8

KSO12

8

9

KSO3

9

10

KSO6

10

11

KSO8

11

12

KSO7

12

13

KSO4

13

14

KSO2

14

15

KSI0

15

16

KSO1

16

17

KSO5

17

18

KSI3

18

19

KSI2

19

20

KSO0

20

21

KSI5

21

22

KSI4

22

23

KSO9

23

24

KSI6

24

25

KSI7

25

26

KSI1

26

27 28 29 30 31 32

2

3

1

L03ESDL5V0CC3-2_SOT23-3

33

27

GND

34

28

GND 29 30 31 32

JXT_FP257H-03 2S10M

SP01002FA00 ME@

0.1U_0201_10V K X5R

C271

1

2

ESD@

Touch PadHall -Sensor for 0-deg reverse (TOP)

+3VALW

0.1U_0201_ 10V K X5R

R273 only for 520S

1

C273

2

YOGA@

R273

1 2

100K_0402_ 5%

S_AL@

2

VDD

OUTPUT

GND

U281

1

APX8132 SOT-23F 3P

SA00008K800

YOGA@

R273

100K_0402_ 5%

S_IMR@

3

1

C274 10P_0402_5 0V8J

YOGA@

2

LID_SW# <32,35>

Hall -Sensor for 360-deg reverse (BOT)

R274

+3VALW

0.1U_0201_ 10V K X5R

C275

YOGA@

1

2

1 2

100K_0402_ 5%

@

2

VDD

OUTPUT

GND

U282

1

APX8132 SOT-23F 3P

SA00008K800

YOGA@

3

1

C276 10P_0402_5 0V8J

YOGA@

2

TAB_SW# <32 >

+3VS

1 2

R279 0_0402_5 %

+3VS

12

4.7K_0402_5 %

I2C0_SCL_TP<11> I2C0_SDA_TP<11>

TP_INT#<11>

TP_DISABLE#<32>

100P_0402_ 50V8J

C281

1

C282 100P_0402_ 50V8J

2

@

D281

PSOT24C_SOT 23-3

@ESD@

ESD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

0.1U_0201_10V K X5R

C280

@R 280

TP_VCC

TP_INT#

2

3

1

Title

KBL/KBD/Hall Sensor/TP

Size Document Number Re v

Custom

Date : Sheet of

ME@ SP01001AE00

ACES_51522-00 801-001

8

7

10

7

G2

6

9

6

G1

5

4

3

2

1

JTP1

Compal Electronics, Inc.

LA-E541P

2.A

33 51Wednesday, June 21, 2017

2.A

5

4

3

2

1

USB Type-C Port

D D

USB3 MUX

UT12

3

HC_EN

4

MC_EN

CC_LINK<32>

DIR_SET<32>

RT33 5.1K_0402_1%

C C

1 2

USBCTXDP1_C USBCTXDN1_C

USBCRXDP1 USBCRXDN1

USBCTXDP2_C USBCTXDN2_C

USBCRXDP2 USBCRXDN2

EN_VCONN

5

CC_EN

6

VCONN_EN

7

DIR_SET

30

REXT

25

TXP_0

26

TXN_0

16

RXP_0

15

RXN_0

27

TXP_1

28

TXN_1

14

RXP_1

13

RXN_1

9

VSSA

17

VCCSA

21

VCCSA

24

VSSA

EJ179V_QFN32_4 X4

SA00009EK00

EJ179V

V33C

VCC3A

V33B

VCONN

SR0_IN SR1_IN

ZCC1_IN ZCC2_IN

CC1_IN CC2_IN

TXP TXN

RXP RXN

EP

+USBC_VBUS +VCONN

F11

RT69

1 2

0_0402_5%

@

+VCONN

21

RB551V-30_SOD 323-2

0.1U_0201_10V K X5R

CT20

1

2

Intel_PCH_USB3. 0

USB3_TX1_P <12> USB3_TX1_N <1 2>

USB3_RX1_P <12>

USB3_RX1_N <12>

1

2

+3VALW

12

20

29

11

1 32

31 2

23 22

19 18

8 10

33

0.2A_9V_PICOSMDC020 S-2

+3VALW

CU_MODE_0

TYPEC_CC_ILIM_ADJ#

CC1_Z_MODE CC2_Z_MODE

CC1 CC2

PD11

0.1U_0201_10V K X5R

CT21

10U_0603_6.3V6M

12

CT22

1

2

0.1U_0201_10V K X5R

CT19

1

2

USBCTXDP1_C USBCTXDN1_C

1 2

CT63 0.1U _0201_10V K X5R

1 2

CT64 0.1U _0201_10V K X5R

USB_OC0#<1 2>

TYPEC_PWR _DIS#<32>

1 2

CT27 0.1U_0201 _10V K X5R

1 2

CT28 0.1U_0201 _10V K X5R

RT51

EMI

USB20_P1<12>

+3VALW +3 VALW +3VALW +3VALW+3VALW

12

RT31

B B

10K_0402_5 %

12

RT32 10K_0402_5 %

@

12

RT34 10K_0402_5 %

@

CU_MODE_0 TYPEC _CC_ILIM_ADJ# CC1_Z_MODE CC2_Z_M ODEEN_VCONN

12

RT35 10K_0402_5 %

12

RT36 10K_0402_5 %

12

RT37 10K_0402_5 %

@

12

RT38 10K_0402_5 %

@

12

RT39 10K_0402_5 %

12

RT40 10K_0402_5 %

@

12

RT41 10K_0402_5 %

ESD

USB20_N1<12>

Profile Selection

EN_VCON N

1

Currently set ting

A A

1

0

CU_MODE _0

0

1

0

1

X

0

1

X

CC[1:2]_ Z_MODE CURRNET SELECTTYPEC_CC_I LIM_A DJ#

00

01 10 11

DFP 900mA

DFP 1.5A

DFP 3A

UFP

EXTERNAL RESISTER

USBCRXDN2

USBCRXDP2

USBCRXDN1 USBCRXDN 1

USBCRXDP1

+USBC_VBUS +USB C_VBUS

JUSBCX1

A1

GND

USBCTXDP1 USBCTXDN1

CC1

USB20_P1_C ONN USB20_N1_C ONN

USBCRXDN2 USBCRXDP2

1 2

RT50 0_0402_5%@

1 2

RT42 10K_0402_5%

1 2

0_0402_5%

2N7002K_SOT 23-3

DT14

3

I/O2

2

GND

1

I/O1

AZC099-04S.R7G_ SOT23-6

DT12

9

10

8

9

7

6

L05ESDL5V0NA-4 SLP2510P8 ESD

A2

SSTXP1

A3

SSTXN1

A4

VBUS

A5

CC1

A6

DP1

A7

DN1

A8

SBU1

A9

VBUS

A10

SSRXN2

A11

SSRXP2

A12

GND

1

GND

2

GND

3

GND

4

GND

5

GND

LOTES_AUSB037 2-P001A

LTCX007XY00 ME@

+5VALW +USBC_VBUS

TYPEC_OC0# CC_LINK_ENCC_ LINK

13

D

S

I/O4

VDD

I/O3

1

2

4

5

3

8

QT1

1

2

4

5

3

6

5

4

USBCRXDN2

USBCRXDP2

USBCRXDP1

0.1U_0201_10V K X5R

CT26

1

@RF@

2

LT12

3 4

MCM1012B90 0F06BP_4P

USB20_P1_C ONN

+USBC_VBUS

USB20_N1_C ONN

@

2

G

@

USB20_P1

USB20_N1

ESD@

B12

GND

B11 B10

B9

B8

B7 B6

B5

B4

B3 B2

B1

6 7 8 9 10

USBCRXDP1 USBCRXDN1

USB20_N1_C ONN USB20_P1_C ONN

CC2

USBCTXDN2 USBCTXDP2

SSRXP1 SSRXN1

VBUS

SBU2

DN2 DP2

CC2

VBUS

SSTXN2 SSTXP2

GND

GND GND GND GND GND

3A/Active High

W=120mi ls

10P_0402_50V8J

CT25

1

2

EMI@

UT13

5

IN

3

FLAG

4

EN(#EN)

0.1U_0201_10V K X5R G517G1TO1U_ TSOT23-5

SA0000A9700

CT23

1

2

USB20_P1_C ONN

12

USB20_N1_C ONN

DT13

9

CC1

CC2 CC2

USBCTXDP1

USBCTXDN1

USBCTXDP2 USBCTXDP2

USBCTXDN2 USBCTXDN2

10

8

9

7

6

L05ESDL5V0NA-4 SLP2510P8 ESD

DT11

9

10

8

9

7

6

L05ESDL5V0NA-4 SLP2510P8 ESD

1 2

CT30 0.1U _0201_10V K X5R

1 2

CT29 0.1U _0201_10V K X5R

1 2

CT61 0.1U _0201_10V K X5R

1 2

CT62 0.1U _0201_10V K X5R

W=120mi ls

1

OUT

2

GND

ESD@

1

CC1

1

2

4

5

3

8

ESD@

1

USBCTXDP1

1

2

USBCTXDN1

2

4

5

3

8

USBCTXDN2_C USBCTXDP2_C

220U_6.3V_ESR18M

470P_0402_50V7K

1

CT60

CT24

1

+

2

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

Type-C

LA-E541P

1

34 51Wednesday, June 21, 2017

2.A

5

4

3

2

1

USB Charge

22U_0603_6.3V6M

C338

C337

1

2

D D

+5VALW_CHG

22U_0603_6.3V6M

C330

R332 0_0402_5 %@

USB20_N3<12> USB20_P3<12>

USB_CHG_ILIM_SEL< 32>

USB_CHG_EN<32>

USB_CHG_CTL1<32> USB_CHG_CTL2<32> USB_CHG_CTL3<32>

C C

USB20_P3_C

USB20_N3_C

0.1U_0201_10V K X5R

1

C333

2

R345 0_0402_ 5%

R344 0_0402_ 5%

12

C332

1

@

2

EMI

10K_0402_5%

12

R343

@

USB_OC2#_U 331

10K_0402_5%

R341

@

12

10K_0402_5%

12

R339

U331

1

IN

13

STATUS#

FAULT#

2

DM_OUT

DM_IN

3

DP_OUT

DP_IN

4

ILIM_SEL

ILIM_LO

5

EN

ILIM_HI

6

CTL1

7

CTL2 CTL3

SA000064O00

GND

GPAD

12

8

TPS2546RT ER_QFN16_3X3

USB20_P3_R

USB20_N3_R

+5V_CHGUSB

80mil

12

OUT

9

11 10

15

R333 51.1K_040 2_1%

16

R334 22.1K_040 2_1%

14 17

1 2 1 2

3V/5VALW_PG<32,37,41,43>

+3VL

12

USB20_N3_C USB20_P3_C

EC_ON<32,41>

10K_0402_5%

R338

For USB Charger to improve +5VALWP power ripple

USB_CHG_ST ATUS# <32>USB_OC2#<1 2>

22U_0603_ 6.3V6M

1 2

R337 4 70K_0402_1%

@

R340 0_0402_ 5%

12

10U_0603_6.3V6M

22U_0603_6.3V6M

C340

C339

1

2

USB Charge switch

+VL

1 2

1

0_0603_5%

C335

2

+VL

R331

1 2

100K_0402_ 5%

EC_ON_R

0.1U_0201_10V K X5R

1

C336

@

2

1

2

R336

2

G

10U_0603_6.3V6M

C341

+5VALW_CHG

13

47U_0805_6.3V6M

22U_0603_6.3V6M

C342

C343

1

2

C344

1

2

22U_0603_6.3V6M

C345

1

2

C346

1

@

2

USB3 with Charge

Card Reader

PCI_RST#<10,19,3 0,31,32> USB3_RX3_P<12> USB3_RX3_N<12>

USB3_TX3_P<12> USB3_TX3_N<12>

PCIE_PRX_DTX_N5<12> PCIE_PRX_DTX_P5<12>

CLK_PCIE_CR#<10> CLK_PCIE_CR<10>

PCIE_PTX_C_DRX_N 5<12> PCIE_PTX_C_DRX_P5<12>

USB2

LID_SW#<32,33 >

+CHGRTC_ R

R342 0_0402_5%

@

PWR_LED #<32,33 ,36>

Novo#<32>

ON/OFF#<32,33>

+5V_CHGUSB

+5VALW

22U_0603_6.3V6M

D

S

13

C334

Q332

2N7002K_SOT23-3

D

Q331

S

1

G

2

ME2301DC-G_SOT23-3

1

C331

0.1U_0201_ 10V K X5R@

2

Lid/Novo/PW R

CR_CLKREQ#< 10>

1 2

+5VALW

+3VALW

+3VS

W=100mils

IO CONN

PCI_RST#

PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5

CLK_PCIE_CR# CLK_PCIE_CR

PCIE_PTX_C_DRX_N 5 PCIE_PTX_C_DRX_P5

USB20_N3_R USB20_P3_R

LID_SW#

Novo# ON/OFF#

PWR_LED #

JIO1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

GND

31

32

GND

32

ACES_51547-03 201-P01

SP01001PC0 0 ME@

33 34

Close to CPU RPC6

+5VALWP

USB3.0_Port

B B

+5VALW +USB3_VCCA

2A/Active Low

W=80mil s

USB_EN#<32>

A A

5

USB_EN#

C305

0.1U_0201_ 10V K X5R

D301

9

10

8

U3RXDP2 U3RXDP2

9

7

U3TXDN2

7

6

U3TXDP2

6

L05ESDL5V0NA-4 SLP2510P8 ESD

5

4

1

SY6288D20AAC_SOT 23-5

2

ESD@

1

2

4

5

3

8

U301

IN

EN

1

2

4

5

3

OUT

GND

OCB

U3RXDN2U3R XDN2

U3TXDN2

U3TXDP2

W=80mil s

1

2

3

USB_OC1#_U 301

220U_6.3V_M

1

C304

+

2

U2DP2

R301

1 2

0_0402_5%

470P_0402_50V7K

C303

1

@

2

D302

3

I/O2

2

GND

1

I/O1

L30ESDL5V0C6 -4_SOT23-6

4

@

ESD@

I/O4

VDD

I/O3

6

5

4

USB_OC1# <12>

+USB3_VCCA

U2DN2

Intel_PCH_USB2. 0

USB20_N2<12>

USB20_P2<12 >

Intel_PCH_USB3. 0

USB3_RX2_N<12>

USB3_RX2_P<12>

USB3_TX2_N<12>

USB3_TX2_P<12>

3

L301

EMI@

C301

0.1U_0201_ 10V K X5R

U3TXDN2_L

1 2

C302

0.1U_0201_ 10V K X5R

U3TXDP2_L

1 2

1

2

MCM1012B90 0F06BP_4P

R302 0_0402_5 %

R303 0_0402_5 %

R304 0_0402_5 %

R305 0_0402_5 %

1 2

@

1 2

@

1 2

@

1 2

@

4

3

U2DN2

3

U2DP2

U3RXDN2

U3RXDP2

U3TXDN2

U3TXDP2

Place TX AC coupling Cap (C172,173). Close to connector

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

2

+USB3_VCCA

W=80mils

JUSB1

U3TXDP2

U3TXDN2 U2DP2

U2DN2 U3RXDP2

U3RXDN2

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND

2

D-

6

SSRX+

4

GND

5

SSRX-

ACON_TARBA-9U139 3

DC23300N8 00

ME@

Title

Size Document Number Re v

Custom

Date : Sheet of

10

GND

11

GND

12

GND

13

GND

USB2 / USB3 / FP / IO Board

LA-E541P

1

2.A

35 51Wednesday, June 21, 2017

2.A

5

4

3

2

1

Thermal Sensor

+3VS_DGPU + 3VS

12

R362

0_0402_5%

D D

EX_THM@

Close to U361

1

C361

2200P_0402 _50V7K

EX_THM@

2

+3V_Thermal

REMO TE1+ /-: Trace width/space:10/10 mil Trace length:<8"

REMOTE1+

C362

@

100P_0402_ 50V8J

REMOTE1-

C C

R363 4 .7K_0402_5%

Close to CPU

1

C

2

Q361

B

MMST3904-7 -F_SOT323-3

2

E

3 1

REMOTE1+

REMOTE1-

1 2

EX_THM@

@

R361 0_0402_5%

@

GPU

U361

EX_THM@

ALERT#

8

SCL

7

SDA

6

5

1

VDD

2

D+

3

D-

T_CRIT#4GND

NCT7718W _MSOP8

SMB Address: 1001100x

EC_SMB_CK2+3V_Thermal

EC_SMB_DA2

CUST_TEMP 1<32> CUST_TEMP 2<32>

EC_SMB_CK2 <8,22,32>

EC_SMB_DA2 <8,22,32>

DDR VRAM

+EC_VCCA

16.5K_0402_1%

12

R364

12

R366 100K +-1% 04 02 B25/50 4250K

ECAGND

SL200002H 00

+EC_VCCA

12

DIS@

12

R367 100K +-1% 04 02 B25/50 4250K

DIS@

SL200002H 00

ECAGND

16.5K_0402_1%

R365

Power LED & Battery LED

FAN

Power (White)

PWR_LED #<32,33 ,35>

+5VS

1 2

R371 0_0603_5 %

B B

EC_FAN_PWM 1<32>

EC_FAN_SPEED1<32>

A A

+5VS_FAN

5

1

C371 10U_0603_ 6.3V6M

2

ME@

SP02001C50 0

CVILU_CI1804M1VRA-NH

6

GND

5

GND

4

3

2

1

JFAN1

BATT_CHG_LE D#<32>

BATT_LOW_ LED#<32>

4

PWR_LED #

BATT_CHG_LE D#

BATT_LOW_ LED#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

LED2

21

LTW-C19 3TS5-C_WHITE

SC50000BB1 0

S_AL@

LED5

21

LTW-C19 3TS5-C_WHITE

SC50000BB1 0

S_IMR@

Battery ( Whi te )

LED3

21

LTW-C19 3TS5-C_WHITE

SC50000BB1 0

YOGA@

LED6

21

LTW-C19 3TS5-C_WHITE

SC50000BB1 0

S_IMR@

Battery (amber)

LED4

A

LTST-C191 KFKT-2CA_ORANGE

SC5000059 30

YOGA@

LED7

A

LTST-C191 KFKT-2CA_ORANGE

SC5000059 30

S_IMR@

2017/06/05 2018/06/05

1 2

R377 412_0402 _1%

S_AL@

1 2

R376 412_0402 _1%

LED3

21

R378 442_0402 _1%

LED4

21

Compal Secret Data

R377

1K_0402_1%

S_IMR@

YOGA@

LTW-C19 3TS5-C_WHITE

SC50000BB1 0

S_AL@

1 2

YOGA@

LTST-C191 KFKT-2CA_ORANGE

SC5000059 30

S_AL@

Deciphered Date

2

+5VALW

+VL

R376

+VL

R378

412_0402_ 1%

S_AL@

1K_0402_1%

S_IMR@

182_0402_ %

S_AL@

412_0402_ 1%

S_IMR@

TOP

BOT

Power (White)

YOGA (YOGA@ )

S series (S_AL@ )

S IMR (S_IMR@ )

LED / Res.

IO Board

LED2

LED5

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

Battery(Wh ite) LED / Res.

R376

LED3

R377 412 Ω

R377 1K Ω

FAN / LED / Thermal Senser

412 Ω

R376

LED3

412 Ω

R376

LED6

1K Ω

LA-E541P

1

Battery(am ber) LED / Res.

R378

LED4

442 Ω

R378

LED4

182 Ω

R378

LED7

412 Ω

36 51Wednesday, June 21, 201 7

2.A

A

DC to DC

B

C

D

E

1 1

2 2

Discharge

For +1.8VALW Discharge For +0.6VS Discharge

3 3

3V/5VALW_PG<32,35,41,43>

4 4

2

G

Q401A

2N7002KDW _SOT363-6

SUSP#< 13,32,42>

+5VALW

0.1U_0201_10V K X5R

12

R401 100K_0402_ 1%

1.8VALW_PW R_EN#

61

D

S

+3VALW

0.1U_0201_10V K X5R 10U_0603_6.3V6M

C381

1

2

10U_0603_6.3V6M

C388

C387

1

2

5

G

Q401B

2N7002KDW _SOT363-6

J5

112

JUMP_43X79

+3VS

10U_0603_6.3V6M

0.1U_0201_10V K X5R C385

C384

1

@

2

+5VS

10U_0603_6.3V6M

0.1U_0201_10V K X5R

C389

C390

1

@

2

J4

2

C382

@

+VL

+3VALW to +3VS

U381

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

EM5209VF_DFN14 _3X2

SA00007PM00

VOUT1 VOUT1

GND

VOUT2 VOUT2

GPAD

+3VALW_3VS

14 13

12

CT1

11

10

CT2

9 8

15

1 2

C383

1 2

C386

+5VALW_5VS

470P_0402_ 50V7K

220P_0402_ 50V7K

112

JUMP_43X79

2

+5VALW to +5VS

RF

+3VS +3VS +5VALW + VGA_CORE

@RF@

+1.0VALW

@RF@

+3VS

0.1U_0201_10V K X5R

@RF@

CC53

2

1

+1.0VALW

0.1U_0201_10V K X5R

@RF@

CC118

2

1

+3VS

0.1U_0201_10V K X5R

CC99

@RF@

2

1

+VCCSA +VCCGT

0.1U_0201_10V K X5R

CC119

@RF@

2

1

+1.0VALW

CC100

CC120

@RF@

+VCCGT

2

1

0.1U_0201_10V K X5R

CC104

@RF@

2

1

@RF@

2

1

+VCCCORE

0.1U_0201_10V K X5R

+VCCGT+3VS

0.1U_0201_10V K X5R

CC105

CC121

@RF@

2

1

+VGA_CORE

0.1U_0201_10V K X5R

CC123

@RF@

CC122

2

1

+1.0VALW +1 .0VALW

+VCCGT +VGA_CORE

0.1U_0201_10V K X5R

CC124

@RF@

2

1

0.1U_0201_10V K X5R

CC125

Screw Hold

1

Shielding Clip

Larger

CLIP10

CLIP1 HOLEA

Smaller

CLIP2 HOLEA

CLIP11

HOLEA

@

1

@

1

CLIP3 HOLEA

@

1

@

1

CLIP4 HOLEA

@

1

LASER BARCODE

CODE1

@

BARCODE_8X8

CODE3

@

BARCODE_20X4

CLIP12 HOLEA

@

1

CLIP5

CLIP6

HOLEA

@

1

CODE2

@

BARCODE_12X4

CODE4

@

BARCODE_10X10

CLIP7 HOLEA

@

1

CLIP8 HOLEA

@

1

CLIP9 HOLEA

@

1

CLIP14 HOLEA

@

1

+1.8VALW+5VALW

12

34

D

S

R402 22_0603_1 %

100K_0402_ 5%

SUSP#

CPU VGA

H4

H2

1

H8 HOLEA

FD1

H3

HOLEA

1

H_3P3

H9 HOLEA

1

H_4P6X6P6

FD2

FD3

FD4

1

H1 HOLEA

H_3P3

R411

470_0402_ 5%

2

G

+0.6VS

12

13

D

S

@

Q411 2N7002K_SOT 23-3

@

KB

H_4P6X6P1

+5VALW

12

R412

@

SUSP

13

D

2

Q412

G

2N7002K_SOT 23-3

@

S

HOLEA

1

H_3P3

H5 HOLEA

1

H_3P3

H10 HOLEA

1

H_2P5-G

H17 HOLEA

1

H_3P5X2P5N

H11 HOLEA

H_2P5-G

H15 HOLEA

1

H_2P0N

1

NGFF

H6 HOLEA

1

H_3P2

H12 HOLEA

H_2P5-G

H16 HOLEA

1

H_3P5X2P5N

H7 HOLEA

1

H_3P2

H13 HOLEA

1

H_2P5-G

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

DC to DC

LA-E541P

E

37 51Wednesday, June 21, 2017

2.A

5

D D

4

3

2

1

ACES_50278-00401-001

C C

+RTCBATT

B B

6

G2

5

G1

4

APDIN

4

3

2

1

JDCIN1

@

PD101

S SCH DIO BAS40CW SOT-323

2

1

3

7A_32VDC_0437007.WRML

PR101

+CHGRTC

45.3K_0603_1%

1 2

PR103

1K_0603_5%

1 2

PF101

21

PR102

1.5K_0603_5%

1 2

+19V_APDIN

12

PC101

1000P_0402_50V7K

EMI@

5A_Z120_25M_0805_2P

12

PC102

100P_0402_50V8J

EMI@

+3VLP

+CHGRTC_R

PL101

EMI_90W@

1 2

EMI@

1 2

PL102 5A_Z120_25M_0805_2P

12

+19V_VIN

12

PC103

100P_0402_50V8J

EMI@

PC104

1000P_0402_50V7K

EMI@

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PWR- DCIN / Vin Detector

Size Document Number

Custom

KBL

Date: Sheet o f

1

38Wednesday, June 21, 2017

5

D D

4

3

2

1

EMI@

PL201 5A_Z120_25M_0805_2P

1 2

EMI@

PL202

1 2

5A_Z120_25M_0805_2P

12

PC201

EMI@

1000P_0402_50V7K

EC_SMB_CK1 <32,40>

EC_SMB_DA1 <32,40>

+3VLP

+3VALW

VCIN1_BATT_TEMP <32,40>

+12.6V_BATT+

12

PC202

0.01U_0402_25V7K

EMI@

PH201 under CPU botten side :

CPU thermal protection at 93 +-3 degree C Recovery at 56 +-3 degree C

+EC_VCCA

12

PR206

VCIN0_PH1<32>

16.5K_0402_1%

12

PH201 100K +-1% 0402 B25/50 4250K

ECAGND

PR203 200K_0402_1%

+8.4V_VMB

JBAT1

VMB2

1

2

3

4

5

6

7

8

C C

SUYIN_125022HB008M200ZL

B B

GND GND GND GND

CONN@

9 10 11 12

EC_SMDA

EC_SMCA

12

PR201

100_0402_1%

12

PR202

PR204 200K_0402_1%@

PR205 10K_0402_5%

PF201

21

15A_24V_F1206HB15V024TM

100_0402_1%

1 2

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR- BATTERY CONN/OTP

Size Document Number Rev

Custom

KBL

Date: Sheet o f

2

Date: Sheet o f

1

39 51Wednesday, June 21, 2017

2.A

5

4

3

2

1

Module model information

ISL95 520_Hyb rid_Boo st_V2.m dd

D D

Protection for reverse input

Vgs = 20V Vds = 60V Id = 250mA

1 2

PR738

1M_0402_1%

Need check the SOA for inrush

+19V_VIN

C C

5

12

PR729

392K_0402_1%

1 2

PR737

3M_0402_5%

PQ740 EMB04N03H 1N EDFN5X6-8

4

ASGATE_CHG_R

PR729 and PR732 are ACDET set t i ng base on your proj ect to set

12

PR732

0x3CH <BIT9> PSYS current gain Rs1 = 10mΩ and Rs2 = 5mΩ o r Rs1 = 10mΩ a nd Rs2 = 10mΩ BIT0 = 1.14uA/W BIT1 = 0.285uA/W ===== ======= ======= ======= ======= ======= ======= ======= === Rs1 = 20m Ω and Rs2 = 10mΩ or R s1 = 20m Ω and R s2 = 20mΩ BIT0 = 2.28uA/W BIT1 = 0.57uA/W

Ipsys = KPSYS x ( VAD P x IAD P + VBA T x I BAT ) R_Psys = 1.2V / Ipsys

B B

A A

KPSYS = 1.14uA/W adapter wattage = 45W Battery wattage = 40Wh Ipsys = 1.14 x (45+40) = 96.9uA R_Psys = 1.2V / 96.9uA = 12.3K-ohm. ===== ======= ======= ======= ======= ==== adapter wattage = 65W Battery wattage = 40Wh Ipsys = 1.14 x (65+40) = 119.7uA R_Psys = 1.2V / 96.9uA = 10K- ohm.

**Design Notes** For 45W/65W /90W system, 2S/3S/4S battery Maximum Charging current 3.5A Maximum Battery discharge power 55W #Register Setting

1. 0X3DH bit10 set 0 (default 1) to enable turbo boost function

2. Disable turbo when AC only #Circuit Design

1. ACLIM and CCLIM are devider voltage control.

2. Use 7X7 choke and 3X3 H/L side MOSFET Charge current 3A Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W) Power density : 0.61 (23X16) #Protect function

1. ACOVP : VCC voltage > 24V

2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable 175s(default).

3. ACOC : OX3CH bit4 set1 release adapter limit function (default:Enable).

4. CHGOCP : based on charge current setting

5. BATOVP : 4.6V/Cell

6. BATLOWV : No.

7. TSHUT : 150C

  

(Rs1 = 10mΩ a nd Rs2 = 5mΩ or Rs1 = 20mΩ and R s2 = 10mΩ). CC_LIM = VccLIM / 64 x Rs2 ===== ======= ======= ======= ======= ======= ======= ======= ====== = (Rs1 = 10mΩ a nd Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20mΩ). CC_LIM = VccLIM / 32 x Rs2 ===== ======= ======= ======= ======= ======= ======= ======= ====== = AC_LIM = Vac_LIM / 32 x Rs1

5

VCIN1_AC_IN<32>

VDD_CHG

12

PR741

100K_0402_1%

12

PR731

VCOUT1_PROCHOT#<32>

158K_0402_1%

49.9K_0402_1%

ACIN_CHG BST_CHG_R

EC_SMB_DA1<32,39>

EC_SMB_CK1<32,39>

ADP_I<32>

PMON_SKYLAKE<46>

PC748

1000P_0402_25V8J

Close to EC.

VCIN1_AC_IN

L2N7002WT1G_SC70-3

Battery current limimed by CCLIm ~ 3.89A. Adapter current limimed by ACLIm ~ 4.33A. (PR779 and PQ741 are for cha nge ACLIm when AC in)

4

13

D

2

PQ707

G

L2N7002WT1G_SC70-3

S

Rds(on) = 15.8mohm max Vgs = 20V Vds = 30V ID = 10.5A (Ta=70C)

+19V_P1

PQ712

AON7506_DFN33-8-5

1 2 3

12

PC715

2200P_0402_50V7K

support Turbo boost : 2200P no support Turb o boost : 0.1u

12

@

76.8K_0402_1%

@

PQ741

13

D

2

G

S

1 2 3 5

4

12

PR762 4.02K_0402_1%

PR763 4.02K_0402_1%

@

1 2

PR769 0_0402_5%

@

1 2

PR770 0_0402_5%

@

1 2

PR777 0_0402_5%

@

1 2

PR780 0_0402_5%

Close to EC.

Follow adapter a nd battery wattage in Vsys current source. Base on CPU Core VR design. The resistor is pop on CPU VR schema tic.

VDD_CHG

VDD=5V

12

PR750 200K_0402_1%

PR749

200K_0402_1%

PR779

1 2

12

PR752 154K_0402_1%

PR751

76.8K_0402_1%

max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W CSR rating: 1W VCSIP-VCSIN spec < 81mV

PL704

EMI@

1UH_2.8A_30%_4X4X2_F

1 2

Isat: 10A DCR: 14mohm

12

BGATE_CHG

OPCP_CHG

VBAT_CHG

25

26

VBAT

QPCP

BGATE

BOOT

UGATE

PHASE

LGATE

VDDP

VDD

DCIN

NTC

ACLIM

15

16

CSOP_CHG

PU703 IC_ISL88739HRZ-T_QFN_32P_CHARGER

24

23

22

21

20

19

18

17

12

27

PR778 10K_0402_1%

Fs=729KHZ ~ +/- 15%

CSON_CHG

BATGO NE(BATT _TEMP) logic high: above 2.4V logic low: under 0.8V

PC224 10P_0402_25V8J

VCIN1_BATT_TEMP <32,39>

PR745

100_0402_1%

1 2

PR771 2. 2_0603_5%

BST_CHG

UG_CHG

LX_CHG

LG_CHG

VDDP_CHG

VDD_CHG

PR757 100K_0402_1%

PC757

1U_0603_25V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR TH E INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR TH E INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR TH E INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0_0402_5%

1

ACIN

2

ACOK

3

SDA

4

SCL

5

PROCHOT#

6

AMON

7

BMON

8

PSYS

33

CCLIM_CHG

COMP_CHG

12

PR913

0.01_1206_1%

1

4

3

2

CSIP_CHG_R

12

PR772

@

CSIP_CHG

32

AGND

9

PC751

@

560P_0402_50V7K

CSIP

PROG

1 2

CSIN_CHG

31

CSIN

10

12

PR754

12

3

PR740

2_0402_5%

PC747

0.1U_0402_25V6

12

PC750 0.22U_0603_25V7K

OPCN_CHG

29

28

30

CMSRC

ASGATE

CCLIM11COMP

FSET12BATGONE13CSON14CSOP

12

FSET_CHG

12

100_0402_1%

PR755

38.3K_0402_1%

PC752

1 2

0.015U_0402_25V7K

CSIN_CHG_R

OPCN

+19V_P2 +19VB_CHG

CMSRC_CHG

ASGATE_CHG

AMON_ISL95520

12

PR727

@

10K_0402_1%

ACLIM_CHG

PROG_CHG

12

PR753

182K_0402_1%

Hybrid boost power mode Cell = 3s

Rds(on) = 32mohm max Vgs = 20V Vds = 30V ID = 8A (Ta=70C)

1 2

PR760 4. 7_0402_5%

12

PC768 1U_0402_16V6K

PR743 10_1206_5%

1 2

VF = 0.38V

1 2

B+

PC762

PC721

12

10U_0805_25V6K

3

2

12

@EMI@

PC765

0.1U_0402_25V7K

12

PC769 1U_0402_16V6K

+19V_VIN

EMI@

PC1236

12

2200P_0402_25V7K

Rds(on) = 32mohm max Vgs = 20V Vds = 30V ID = 8A (Ta=70C)

PQ305

AON7408L_DFN8-5

3 5

241

5

PQ706

4

123

AON7752_DFN3X3EP8-5

PR1446

@

1 2

0_0603_5%

A31 connect to BA

CSOP_CHG_R

Compal Secret Data

2

Other team connect to bat t conn

CSON_CHG_R

Deciphered Date

12

PR766

4.7_1206_5%

EMI@

12

PC767

680P_0603_50V7K

EMI@

12

PC760

10U_0805_25V6K

+12.6V_BATT+

0.22U_0603_25V7K

1 2

PD703

1

SCH DIO BAS40CW SOT-323

1 2

PR742 2_0402_5%

12

PC708

0.1U_0402_25V6

1 2

PR776 0_0402_5%@

2017/06/05 2018/06/05

PQ705 AON7506_DFN33-8-5

4.7UH_5.5A_20%_7X7X3_M

1 2 35

4

PC779

@

1 2

0.1U_0402_25V7K

7X7X3 Isat: 6.5A DCR: 28mohm

PL700

1 2

BA

+17.4V_BATT_CHG

Support max charge 3.5A Power loss: 0.245W CSR rating: 1W VCSPP-VCSON spec < 81mV

PR765

0.01_1206_1%

1

2

PM_SLP_S4#<10,32,42>

LTC015EUBFS8TL_UMT3F

4

3

12

PC775

10U_0805_25V6K

LMUN5113T1G_SOT323-3

PQ711

2

12

PC776

10U_0603_25V6M

PQ710

13

+12.6V_BATT+

12

PC761

10U_0805_25V6K

2

1 3

BA

For A31 only. Turn off C harger IC on battery only. Depend on customer design for system pow er consumption.

Compal Electronics, Inc.

Title

Size

Date: Sheet of

Compal Electronics, Inc.

PWR_CHARGER

Document Number Re v

KBL

1

40 51Wednesday, June 21, 2017

2.A

A

B

C

D

E

Module model information

SY828 6B_V 3_single.mdd SY8286B_V3_du al.m dd

B+

EMI@

1 1

PL503

1 2

5A_Z120_25M_0805_2P

12

@RF@

PC11192 22P_0402_50V8J

12

PC501

PC529

@EMI@

10U_0805_25V6K

12

PC502

PC503

2200P_0402_50V7K

EMI@

0.1U_0402_25V6

10U_0805_25V6K

+3VL

Check pull up resistor of SPOK at HW side

3V/5VALW_PG<32,35,37,43>

PR510

2.2K_0402_5%

EC_ON<32,35>

2 2

VCOUT0_MAIN_PWR_ON<32>

12

PC532 1U_0402_16V6K

B+

5A_Z120_25M_0805_2P

PR506 499K_0402_1%

B+

3 3

1 2

150K_0402_1%

PR508

ENLDO_3V5V

12

@

0_0402_5%

1 2

EMI@

1 2

PR511

PL504

1 2

12

EN1 and EN2 dont't be floating. EN :H>0.8V ; L<0.4V

5V_3V_EN

12

PC527

PR513

1M_0402_1%

4.7U_0402_6.3V6M

+19VB_5V

12

PC514

PC513

10U_0805_25V6K

+3VLP

12

PR509

PR516

@

ENLDO_3V5V

5VLDO_EN<32>

0_0402_5%

1 2

PR517

0_0402_5%

1 2

+19VB_5V

4 4

12

PR514

560K_0402_5%

12

PR515

105K_0402_1%

VCIN1_BATT_DROP <32>

12

PC528 1000P_0402_25V8J

A

@

100K_0402_5%

12

PC530

@

4.7U_0402_6.3V6M

12

PR518

@

100K_0402_5%

B

12

PR501

100K_0402_5%

EN1 and EN2 dont't be floating. EN :H>0.8V ; L<0.4V

Fsw : 600K Hz

2 Cell battery : Cin=10uF*2pcs 3 Cell ~ 4 Cell battery : Cin=10uF*1pcs

+19VB_5V

LX_5V

12

PC515

PC516

0.1U_0402_25V6

2200P_0402_50V7K

EMI@

@EMI@

3V/5VALW_PG

5V_3V_EN

PU501 SY8286BRAC_QFN20_3X3

2

5

LX_3V

6

7

8

9

10

ENLDO_3V5V

5V_3V_EN

LX

GND

PG

NC

IN3IN4IN

EN112EN2

FF13OUT14NC

11

3V_FB 3V_FB_1

Fsw : 600K Hz

PU502 SY8288CRAC_QFN20_3X3

1

2

5

6

LX

7

GND

8

GND

9

PG

10

NC

11

IN

IN3IN4IN

EN112EN2

FF13OUT14LDO

15

12

PC526

1000P_0402_25V8J

5V_FB 5V_FB_1

Security Cl assification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

IN

BS

GND

VCC

NC

GND

1 2

Issued Date

keep short pad, snubber is for EMI only.

PR502

@

BST_3V

1

BS

15

PC511 1000P_0402_25V8J

LX

0_0402_5%

1 2

20

LX

19

LX

18

GND

17

LDO

NC

GND

12

16

21

3.3V LDO 150mA~300mA

1 2

20

19

18

17

16

21

1K_0402_1%

1 2

keep short pad, snubber is for EMI only.

PR505

@

0_0402_5%

BST_5V B ST_5V_RBST_5V_R

1 2

LX_5V

VCC_5V

1 2

+5VLP

PC524

4.7U_0603_6.3V6M

PR512

1K_0402_1%

1 2

C

PC504

0.1U_0201_10V6K

BST_3V_R+19VB_3V

1 2

LX_3V

+3VLP

PC509

4.7U_0603_6.3V6M

PR504

PC512

0.1U_0201_10V6K

1 2

PC517

4.7U_0603_6.3V6M

2017/06/05 2018/06/05

Use 7x7x3 size when the layout space is enough.

PL501

1.5UH_6A_20%_5X5X3_M

1

2

12

RF@

PR503

4.7_1206_5%

3V_SN

12

RF@

PC510

680P_0603_50V7K

PL502

3.3UH_PIMB104T-3R3MS_10A_20%

1 2

12

PR507

RF@

4.7_1206_5%

5V_SN

12

RF@

PC525

680P_0603_50V7K

Compal Secret Data

Deciphered Date

4

3

12

PC505

PC506

22U_0603_6.3V6M

Vout is 3.234V~3.366V

TDC=6A

+3VALWP +3VALW

12

PC520

PC519

22U_0603_6.3V6M

Vout is 4.998V~5.202V

+5VALWP

D

+3VALWP

12

PC507

22U_0603_6.3V6M

PC531

PC508

@RF@

22P_0402_50V8J

22U_0603_6.3V6M

Iocp=10A

PJ502

@

2

112

JUMP_43X118

PJP502

@

JUMP_43X39

2

+3VLP

112

+3VL

+5VALWP

12

PC518

PC521

22U_0603_6.3V6M

Iocp=10AT DC=6 A

PJ504

@

2

112

JUMP_43X118

PJP504

@

JUMP_43X39

2

+5VLP +VL

Compal Electronics, Inc.

Title

+3VALW/+5VALW

Size Document Number Rev

Custom

KBL

Date: Sheet o f

112

E

+5VALW

41 51Wednesday, June 21, 2017

2.A

5

PL601

EMI@

12

PC613

22U_0603_6.3V6M

5A_Z120 _25M_0805_2P

1 2

12

PC614

22U_0603_6.3V6M

+12.6VB_ DDR

12

PC602

PC601

0.1U_0402_25V6

EMI@

@EMI@

PL603

1UH_11A _20%_7X7X3_M

1

2

RF@

4.7_1206 _5%

RF@

680P_04 02_50V7K

B+

D D

+1.2VP

12

PC609

22U_0603_6.3V6M

C C

Mode Level +0.675VSP VTTREF_1.35V S5 L off off S3 L off on S0 H on on

Note: S3 - sleep ; S5 - power off

12

PC612

PC611

PC610

22U_0603_6.3V6M

+3VALW

B B

JUMP_43 X79

0_0402_ 5%@

PR615

4.7U_060 3_6.3V6K

12

PR612

PM_SLP_S4#<10,32,40>

A A

1 2

47K_040 2_5%

1

2

PJ603

@

2

12

PC621

12

PC623

0.1U_0402_16V7K

4

12

PC604

PC603

2200P_0402_50V7K

4

3

PR603

PC615

MOSFET: 3x3 DFN H/S Rds(on): 27mohm(Typ), 34mohm(Max) Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C

L/S Rds(on): 19mohm(Typ), 23.5mohm(Max) Idsm: 11A@Ta=25C, 8.8A@Ta=70C

Choke: 7x7x3 Rdc=6.7mohm(Typ), 7.4mohm(Max)

Switching Frequency:540kHz Ipeak=8A Iocp~9.6A OVP: 113%~120% VFB=0.75V, Vout=1.3545V

10U_0805_25V6K

AON7408 L_DFN8-5

12

10U_0805_25V6K

5

123

4

PQ602 AON7506 _DFN33-8-5

PQ601

12

PC605

0.1U_060 3_25V7K

+5VALW

3 5

241

+5VALW

12

PC620

1U_0402 _6.3V6K

Vout=0.8V* (1+Rup/Rdown)

PU602

APL5930 KAI-TRG_SO8

6

VCNTL

5

VIN

9

VIN

8

EN

7

POK

3

VOUT

4

VOUT

2

FB

GND

1

Rup

Rdown

PR604

5.1_0603 _5%

1 2

PC617

1U_0402 _10V6K

12

PR614

3.4K_0402_1%

12

PR616

1.6K_0402_1%

3

BST_DDR _R

+5VALW

12

DDR_VTT_PG_CTRL<7>

12

PC622

2.2_0603 _5%

1 2

PR602

13K_040 2_1%

1 2

0.01U_0402_25V7K

PR601

LG_DDR

CS_DDR

PC608

1U_0402 _10V6K

1 2

VDD_DDR

PR605

5.1_0603 _5%

+12.6VB_ DDR

SYSON<13,32>

SUSP#<13,32,37>

12

PC624

BST_DDR

UG_DDR

LX_DDR

PU601

15

LGATE

14

PGND

13

CS

12

VDDP

11

VDD

PR608 4 70K_0402_1%

1 2

PR610

1 2

0.1U_040 2_10V7K

+2.5VP

22U_0603_6.3V6M

Ultra Low Dropout 0.23V(typical) at 3A Output Current

2

Pin19 need pull separate from +1.35VP. If you have +1.35V and +0.675V sequence question, you can change from +1.35VP to +1.35VS.

+1.2VP

12

18

16

17

PHASE

RT8207P GQW_W QFN20_3X3

PGOOD

9

10

TON_DDR

0_0402_ 5%@

PC618

@

PR611

1 2

PR606

1 2

UGATE

TON

8

EN_DDR

12

0_0402_ 5%

0_0402_ 5%@

19

20

21

VTT

BOOT

S5

PAD

VTTGND

VTTSNS

GND

VTTREF

VDDQ

FB

6

FB_DDR

1

2

3

4

5

VTTREF_ DDR

1 2

12

PR609 10K_040 2_1%

PR607

6.04K_04 02_1%

VLDOIN

S3

7

EN_0.675VSP

+1.2VP +1.2V

12

PC619

@

0.1U_040 2_10V7K

+0.6VSP +0.6VS

+2.5VP +2.5V

+1.2VP

@

112

JUMP_43 X118

PJ604

@

112

JUMP_43 X39

@

JUMP_43 X79

PJ601

PJ605

112

PC606

10U_0603_6.3V6M

12

+1.2VP

2

1

0.675Volt +/- 5% TDC 0.7A Peak Current 1A

+0.6VSP

PC607

10U_0603_6.3V6M

PC616

0.033U_0 402_16V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

5

4

2017/06/ 05

3

Compal Secret Data

Deciphered Date

2018/06/ 05

2

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : S heet o f

Compal Electronics, Inc.

RT8207P

KBL

Wednesday, June 21, 2017

1

42 51

2.ACustom

5

4

3

2

1

Module model information

APL59 30_V2.md d

D D

+3VALW

JUMP_43X79

PJ701

@

C C

PR701

0_0402_5%

@

3V/5VALW_PG<32,35,37,41>

1 2

PR704

1M_0402_5%

4.7U_0603_6.3V6K

12

@

PC702

PC704

0.1U_0402_16V7K

+3VALW

B B

1

2

12

+5VALW

PR702 100K_0402_5%

1 2

12

PC701

1U_0402_6.3V6K

PU701

APL5930KAI-TRG_SO8

6

VCNTL

5

VIN

9

VIN

8

EN

7

POK

PGOOD <44>

Ultra Low Dropout 0.23V(typical) at 3A Output Current

3

VOUT

4

VOUT

2

FB

GND

1

Rup

Rdown

12

PR703

PC703

12.7K_0402_1%

12

PR705

10K_0402_1%

12

0.01U_0402_25V7K

PC705

22U_0603_6.3V6M

+1.8VALWP

+1.8VALWP +1.8VALW

PJ702

@

112

JUMP_43X79

2

Vout=0.8V* (1+Rup/Rdown)

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number Re v

Custom

Date : S heet o f

2

Date : S heet o f

Compal Electronics, Inc.

APL5930

KBL

1

2.A

43 51W ednesday, June 21, 2017

2.A

A

B

C

D

E

Module model information

SY828 6_V1_ sing le. mdd SY828 6_V1_ dual .md d

+3VALW

Confirm HW side

1 1

EMI@

B+

PR801

0_0402_5%@

PGOOD<43>

EN :H>0.8V ; L<0.4V

EN pin don't floating If have pull down resistor at HW side, please delete PR601.

2 2

1 2

1M_0402_1%

PR806

12

+19VB_1V

PL802

1 2

5A_Z120_25M_0805_2P

12

PC812

@

0.1U_0402_25V6

12

PC801

PC803

0.1U_0402_25V6

EMI@

@EMI@

2200P_0402_50V7K

+19VB_1V

12

PC804

10U_0805_25V6K

+3VALW

12

@

PR808 0_0402_5%

The current limit is set to 6A, 9A or 12A when this pin is pull low, floating or pull high.

EN_1V

ILMT_1V

2

3

4

5

7

8

18

11

13

15

12

PC813 1U_0402_6.3V6K

PU801

IN

GND

EN

ILMT

BYP

SY8286RAC_QFN20_3X3

PG

BS

LX

FB

VCC

NC

PAD

12

PR803

@

10K_0402_5%

9

1

LX_1V

6

19

20

FB_1V

14

LDO_3V

17

10

12

16

21

keep short pad, snubber is for EMI only.

PR804

@

0_0402_5%

BST_1V_RBST_1V

1 2

12

PC811

2.2U_0402_6.3V6M

PC805

0.1U_0201_10V6K

1 2

=0.6*(1+(14.3/20))

PR802

RF@

4.7_1206_5%

SNUB_1V

1 2

Use 7x7x3 size when the layout space is enough.

PL801

1 2

1UH_6.6A_20%_5X5X3_M

FB=0.6V

Vout=1.029V

RF@

680P_0603_50V7K

12

R1

12

R2Vout=0.6V* (1+R1/R2)

PC802

1 2

PR805

14.3K_0402_1%

PR807 20K_0402_1%

+1.0VALWP

12

PC806

12

PC807

PC808

22U_0603_6.3V6M

330P_0402_50V7K

12

22U_0603_6.3V6M

12

PC810

PC809

22U_0603_6.3V6M

PC814

@

22U_0603_6.3V6M

+1.0VALWP

PC815

@

22U_0603_6.3V6M

PJ802

@

JUMP_43X118

2

112

+1.0VALW

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/06/05 2018/06/05

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

SY8286

Size

Document Number Re v

C

KBL

Date: Shee t of

E

44 51Wednesday, J une 21, 2017

2.A

CPU CORE

5

4

3

2

1

D D

PRI2, PRI8 place near CPU side. If the resisters are at HW side and POP. PRI2, PRI8 can be canceled.

+VCCSA

VCCSA_SENSE<13>

VSSSA_SENSE<13>

+VCCCORE +3VS

VCCCORE_SENSE<15>

VSSCORE_SENSE<15>

C C

CSP_1a_VCORE_R< 47>

CSP_2a_VCORE_R< 47>

CSN_2a_VCORE<47>

CSN_1a_VCORE<47>

B B

1 2

PRI30 100K_0603_1%

1 2

PRI38 100K_0603_1%U42@

1 2

PRI43 10_0402_1%U42@

1 2

PRI44 10_0402_1%

CSP_1a_VCORE_R

CSP_2a_VCORE_R

PRI11, PRI16 place near CPU side. If the resisters are at HW side and POP. PRI11, PRI16 can be canceled.

PRI31 165K_0402_1%

1 2

12

PCI26

0.22U_0402_25V6K

1 2

PRI47 2.15K_0402_1%

1 2

PRI54 2.15K_0402_1%U42@

1 2

+5VS

PRI118

U22@

1K_0402_1%

PRI2 100_0402_1%

1 2

PRI8 100_0402_1%

1 2

PRI11 100_0402_1%

1 2

PRI16 100_0402_1%

Close to CORE choke

PHI2

220K_0402_5%_B25/50 4700K

1 2

PRI32

CSCOMP_2ph_CPU_R

75K_0402_1%

1 2

PCI18

1000P_0402_50V7K

12

PCI22

0.1U_0402_25V6

100K_0402_1%_B25/50 4250K

PCI23

U42@

12

PCI19 100P_0402_50V8J

U42@

16.9K_0402_1%

PHI4

PRI3

0_0402_5%@

1 2

PRI6

0_0402_5%

@

1 2

PRI13

0_0402_5%@

1 2

PRI17

0_0402_5%@

1 2

U42@

909_0402_1%

PRI39

TSENSE_2ph_CPU_R

12

1000P_0402_50V7K

PRI20

49.9_0402_1%

470P_0402_50V7K

15P_0402_50V8J

U22@

9.76K_0402_1%

1 2

PRI48

61.9K_0402_1%

PCI5

12

PCI9 1000P_0402_50V7K

PRI19

PCI12

PCI15

PRI39

PRI45 0_0402_5%@

1000P_0402_50V7K

12

VSPP_1b_CPU_R

12

VSNN_1b_CPU_R

12

U22@

PRI20

604_0402_1%

12

PRI25

12

PCI16 2200P_0402_50V7K

PCI28

VSN_2ph_CPU_R

4.75K_0402_1%

ILIM_2ph_CPU CSCOMP_2ph_CPU CSSUM_2ph_CPU CSREF_2ph_CPU CSP2_2ph_CPU CSP1_2ph_CPU

TSENSE_2ph_CPU

+19VB_CPU

12

20K_0402_1%

PCI11 3300P_0402_25V7K

U22_SKL@

28.7K_0402_1%

RIOU T@CO RE

PRI23

25.5K_0402_1%

1 2

IC NCP81218MNTXG QFN 48P

IOUT_2ph_CPU DIFFOUT_2ph_CPU

COMP_2ph_CPU

0.01U_0402_50V7K

+5VS

Fsw for CORE & GT

A A

OCP for VCCSA

PCI3

1000P_0402_50V7K

1 2

PRI4

1.78K_0402_1%

1 2

PRI7

1K_0402_1%

1 2

PCI8 2200P_0402_25V7K

PRI10

1 2

PRI18

806_0402_1%

1 2

PRI23

U22_KBL@

1 2

PCI13

1 2

PRI46 1K_0402_1%

PCI30

PRI55 2_0402_1%

1 2

PCI33

1U_0603_10V6K

U22_SKL@

45.3K_0402_1%

U42@

19.1K_0402_1%

VSP_1b_CPU

RDRPSP

VSN_1b_CPU

VSP_2ph_CPU

VSN_2ph_CPU

U42@

23.2K_0402_1%

470P_0402_50V7K

PUI1

1

IOUT_2ph

2

DIFFOUT_2ph

3

FB_2ph

4

COMP_2ph

5

ILIM_2ph

6

CSCOMP_2ph

7

CSSUM_2ph

8

CSREF_2ph

9

CSP2_2ph

10

CSP1_2ph

11

TSENSE_2ph

12

VRMP_CPU

VRMP

12

PRI59

U42@

100K_0402_1%

PRI63

PRI23

ROSC_COREGT_CPU

33.2K_0402_1%

PRI5

49

12

Fsw for SA

PRI63

TAB

48

47

VSN_2ph

13

VCC_CPU

PRI60

24K_0402_1%

44

46

45

PSYS

VSP_1b

VSN_1b

VSP_2ph

PWM2_2ph17PWM1_2ph

16

ROSC_SAUS_CPU

12

ICCMAX_2ph_CPU

U42@

19.1K_0402_1%

PMON_SKYLAKE <40>

1 2

8200P_0402_25V7K

COMP_1b_CPU

12

PRI5

U22@

24K_0402_1%

CSP_1b_VCCSA

U22@

IOUT_1b_CPU

ILIM_1b_CPU

42

41

40

43

38

39

ILIM_1b

CSP_1b

CSN_1b

IOUT_1b

COMP_1b

ADDR_VBOOT21ICCMAX_1b20ICCMAX_1a19ICCMAX_2ph18RSOC_SAUS15ROSC_COREGT14VCC

PWM_1a22TSENSE_1ph

23

ICCMAX_1b_CPU

ICCMAX_1a_CPU

ADDR_VBOOT_CPU

12

PRI64 97.6K_0402_1%

PRI63 51.1K_0402_1%

U22_KBL@

PRI65

PSYS: Please confirm c harger pull low resistance. Charger side should be un pop.

PRI1

PCI1

1.5K_0402_1%

1 2

PCI2

15P_0402_50V8J

12

PCI4

1000P_0402_50V7K

12

PCI6

PRI14

68.1K_0402_1%

1 2

PCI10 470P_0402_50V7K

IMVP8_EN Upper Threshold > 0.8V Lower Threshold < 0.3V

EN_CPU

37

EN

VR_RDY

PWM_1b

DRVON

SCLK

ALERT#

SDIO

VR_HOT#

IOUT_1a

CSP_1a CSN_1a

ILIM_1a

COMP_1a

VSN_1a

VSP_1a

24

VSP_1a_CPU

TSENSE_1ph_CPU TSENSE_1ph_CPU_R

12

PRI65 15.8K_0402_1%

U22@

0.01U_0402_25V7K

1 2

PRI21 0_0402_5%@

1 2

36 35

SCLK_CPUFB_2ph_CPU

34

ALERT#_CPU

33

SDIO_CPU

32

VR_HOTL#

31 30 29 28

ILIM_1a_CPU

27

COMP_1a_CPU

26 25

VSN_1a_CPU

1000P_0402_50V7K

PRI56

2.94K_0402_1%

1 2

PCI32

1000P_0402_50V7K

PWM_1a_CPU <47>

12

PRI66 35.7K_0402_1%

VBO OT: Debug setting=51.1K

PWM2_2ph_CPU <47>

PWM1_2ph_CPU <47>

PRI69 10_0402_5%

1 2

12

PCI36

12

PCI7

2200P_0402_50V7K

1200P_0402_50V7K

PRI14

U42@

57.6K_0402_1%

VR_ON <32>

PWM_1b_CPU <47>

DRVON <47>

PRI36 49.9_0402_1%

1 2 1 2

PRI37 0_0402_5%@

1 2

PRI40 10_0402_1%

1 2

PRI41 100_0402_1%

PCI24

3300P_0402_50V7-K

VSN_1a_CPU_R

1 2

PRI49 909_0402_1%

1 2

2.94K_0402_1% PRI115

PRI50

@

0_0402_5%

1 2

12

PCI31

VSP_1a_CPU_R

PRI61

@

0_0402_5%

1 2

12

PCI34

1000P_0402_50V7K

472mV/ 120u A=3. 933K Active Point110 degreeC = 4.206K

12

PHI1 100K_0402_1%_B25/50 4250K

CSN_1b_VCCSA_NTC

12

PRI9 12K_0402_1%

+1.0V_VCCST

12

@

PRI26 45.3_0402_1%

PRI57

@

0_0402_5%

1 2

12

PRI62

61.9K_0402_1%

7.5K_0603_1%

PRI27 110_0402_1%

PRI58 100_0402_1%

Close to SA choke

1 2

PRI12

12

PRI33 100_0402_1%

IOUT_1a_CPU CSP_1a_VCORE

PRI51

100_0402_1%

1 2

12

PHI5 100K_0402_1%_B25/50 4250K

CSN_1b_VCCSA <47>

PCI14

0.1U_0402_25V6

VR_SVID_CLK <15> VR_ALERT# <15> VR_SVID_DATA <15>

VSSGT_SENSE <15>

VCCGT_SENSE <15>

CSP_1b_VCCSA_R <47>

12

PRI15 10K_0402_1%

12

PRI24

@

110_0402_1%

VR_HOT# <32>

PCI17 470P_0402_50V7K

1 2

PRI42

61.9K_0402_1%

1 2

12

PCI25

15P_0402_50V8J

+VCCGT

ESD@

PCI35

100P_0402_50V8J

12

PCI29 1500P_0402_50V7K

12

PRI52

2.49K_0402_1%

PRI34

7.5K_0603_1%

1 2

12

PCI20

0.022U_0402_16V7K

12

1000P_0402_50V7K

12

PRI53

36.5K_0402_1%

VR_PWRGD <32>

PRI29 12K_0402_1%

1 2

PCI21

0.01U_0402_25V7K

1 2

12

PCI37

PCI27

OCP for GT

PRI70 10_0402_5%

2200P_0402_50V7K

CSP1_VGT1 <47>

Close to GT choke

CSN1_VGT_NTC

12

PHI3

CSN1_VGT1<47>

100K_0402_1%_B25/50 4250K

Title

NCP81218

Size

Document Number Re v

Date: Sheet o f

5

4

3

2

Date: Sheet o f

1

46 51Wednesday, June 21, 2017

2.A

CPU POWER STAGES

5

+19VB_CPU

BST1_VCORE1_R

DRVH

SW

GND

DRVL

PAD

9

PCI42

0.22U_0603_16V7K

1 2

8

7

6

5

UG_VCORE1

LG_VCORE1

PRI68

2.2_0603_5%

PCI43

BST1_VCORE1

DRVON

12

1 2

PUI2 NCP81151MNTBG_DFN8_2X2

1

BST

2

PWM

3

EN

4

VCC

D D

PWM1_2ph_CPU<46>

+5VS

2.2U_0603_16V6K

5

4

5

4

PQI6 AON6380 1N DFN5X6-8

123

PQI7 AON6314 1N DFN5X6-8

123

4

InputC apacito r: 10uF_0 805_X5R_ 25V

12

PCI38

PCI39

10U_0805_25V6K

LX_VCORE1

12

RF@

SNB_VCORE1

12

RF@

PRI71

4.7_1206_5%

PCI45 680P_0603_50V7K

12

PCI41

PCI40

EMI@

@EMI@

0.1U_0402_25V6

2200P_0402_50V7K

PLI3

0.22UH_24A_20%_ 7X7X4_M

1

4

3

2

3

PLI1

EMI@

5A_Z120_25M_0805_2P

1 2

PLI2

EMI@

5A_Z120_25M_0805_2P

1 2

1

+

2

PC135

PC136

33U_25V_NC_6.3X4.5

CSN_1a_VCORE <46>

CSP_1a_VCORE_R <46>

B+

VCC_C ORE FSW=4 50kHz DCR = 1.19 mohm +/- 5% TYP MAX H/S Rds(on) :11.7mohm , 14mohm L/S Rds(on) :2.7mohm , 3.3mohm

1

+

2

330U_B2_2.5VM_R9M

+VCCCORE

@U42@

PCI94

2

1

C C

12

U42@

PCI53

+19VB_CPU

PRI73

2.2_0603_5%

BST_VGT1_R

1 2

BST_VGT1

PUI3 NCP81253MNTBG_DFN8_2X2

PCI58

2.2U_0603_16V6K

BST_VCCSA_R

DRVH

GND

DRVL

PAD

9

SW

5

1

BST

2

PWM

3

EN

4

VCC

PCI69

0.22U_0603_16V7K

1 2

8

7

6

5

DRVH

DRVL

FLAG

SW

GND

PWM_1a_CPU<46>

DRVON<46>

+5VS

B B

PWM_1b_CPU<46>

A A

+5VS

DRVON

12

PRI83

2.2_0603_5%

1 2

BST_VCCSA

PUI5 NCP81253MNTBG_DFN8_2X2

1

BST

2

PWM

3

EN

4

VCC

PCI70

2.2U_0603_16V6K

12

PCI57

0.22U_0603_16V7K

9

UG_VGT1

8

LX_VGT1 LX_VGT1

7

6

LG_VGT1

5

12

PCI65

UG_VCCSA

LX_VCCSA

LG_VCCSA

4

3

D1

D110D2/S1

S2

6

5

10U_0805_25V6K

AON793 4 Rds(on)=12.4~15.8m ohm

PQI1

1

2

AON7934_DFN3X3A8-10

D1

G1

LX_VCCSA

9

S2

G2

7

8

PCI66

10U_0805_25V6K

12

PQI2

12

PRI84

RF@

4.7_1206_5%

SNB_VCCSA

PCI71

RF@

680P_0603_50V7K

2

1

D1

G1

D2/S1

S24S2

S23G2

5

6

LG_VGT1

12

PCI68

PCI67

@EMI@

EMI@

0.1U_0402_25V6

2200P_0402_50V7K

PLI6

0.47UH_NA__12.2A_20%

1

2

7

AON6992_DFN5X6D-8-7

12

PCI51

PCI50

10U_0805_25V6K

RF@

12

PRI77

4.7_1206_5%

SNUB_VGT1

12

RF@

PCI64

680P_0603_50V7K

+19VB_CPU

4

3

+VCCSA

CSN_1b_VCCSA <46>

CSP_1b_VCCSA_R <46>

4

PCI46

@EMI@

0.1U_0402_25V6

PLI4

0.22UH_24A_20%_ 7X7X4_M

1

4

3

2

1

12

+

PCI47

2

PC148

EMI@

2200P_0402_50V7K

33U_25V_NC_6.3X4.5

+VCCGT +VCCCORE

1

+

PCI92

2

330U_D1_2VY_R9M

CSN1_VGT1 <46>

CSP1_VGT1 <46>

PWM2_2ph_CPU<46>

+5VS

3

U42@

DRVON

12

PCI59

2.2U_0603_16V6K

PRI74

U42@

2.2_0603_5%

BST_VCORE2 BST_VCORE2_R

1 2

U42@

PUI4 NCP81151MNTBG_DFN8_2X2

1

2

3

4

9

BST

FLAG

8

PWM

DRVH

7

EN

SW

6

VCC

GND

5

DRVL

5

U42@

PQI9

12

U42@

PCI60

0.22U_0603_16V7K

UG_VCORE2

LX_VCORE2 LX_VCORE2

LG_VCORE2

2

4

123

5

123

AON6380 1N DFN5X6-8

U42@

PQI10 AON6314 1N DFN5X6-8

PCI54

PCI56

PCI55

10U_0805_25V6K

0.1U_0402_25V6

2200P_0402_50V7K

@U42_EMI@

U42_EMI@

PLI5

U42@

0.22UH_24A_20%_ 7X7X4_M

1

2

12

PRI78

4.7_1206_5%

U42_RF@

SNUB_VCORE2

12

PCI63

680P_0603_50V7K

U42_RF@

+19VB_CPU

4

3

CSN_2a_VCORE <46>

CSP_2a_VCORE_R <46>

Title

Power Stage

Size Document Number R ev

Date: Sh eet

1

PCI93

+

U42@

2

330U_D1_2VY_R9M

of

47 51Wednesday, June 21, 2017

of

47 51Wednesday, June 21, 2017

of

47 51Wednesday, June 21, 2017

2.A

5

VCC_CORE Place on CPU Back Side @ V09 22U_0603 * 36pcs +1U_0201*35 pcs

4

3

2

VCC_GT Place on CPU Back Side @ V09 22U_0603 * 32 pcs +1U_020 1*12 pcs

1

+VCCCORE

U42@

1

PC1118

PC1119

2

22U_0603_6.3V6M

1

PC1169

2

22U_0603_6.3V6M

1

2

PC11195

22U_0603_6.3V6M

1

2

22U_0603_6.3V6M

PC1170

22U_0603_6.3V6M

1

PC1120

2

PC11197

PC11196

22U_0603_6.3V6M

U42@

+VCCGT_VCCCORE

1

2

PC11198

22U_0603_6.3V6M

U42@

1

D D

C C

1

PC1101

2

22U_0603_6.3V6M

12

PC1153

1U_0201_6.3V6M

12

PC1171

1U_0201_6.3V6M

12

PC1197

1U_0201_6.3V6M

1

PC1103

PC1102

2

22U_0603_6.3V6M

12

PC1155

PC1154

1U_0201_6.3V6M

12

PC1172

PC1173

1U_0201_6.3V6M

12

PC1199

PC1198

1U_0201_6.3V6M

1

PC1104

2

22U_0603_6.3V6M

12

PC1156

1U_0201_6.3V6M

12

PC1174

1U_0201_6.3V6M

12

PC1200

1U_0201_6.3V6M

1

PC1106

PC1105

2

22U_0603_6.3V6M

12

PC1158

PC1157

1U_0201_6.3V6M

12

PC1176

PC1175

1U_0201_6.3V6M

12

PC1201

PC1202

1U_0201_6.3V6M

1

PC1109

PC1108

PC1107

2

22U_0603_6.3V6M

12

PC1159

PC1177

PC1203

PC1161

PC1160

1U_0201_6.3V6M

12

PC1179

PC1178

1U_0201_6.3V6M

12

PC1204

PC1205

1U_0201_6.3V6M

1

PC1110

2

22U_0603_6.3V6M

12

PC1162

1U_0201_6.3V6M

12

PC1180

1U_0201_6.3V6M

1

PC1111

2

22U_0603_6.3V6M

VCC_SA Place on CPU Back Side @ V09 22U_0603 * 9 pcs + 1U_0201*7

12

PC1164

PC1163

1U_0201_6.3V6M

12

PC1182

PC1181

1U_0201_6.3V6M

1

PC1112

PC1113

2

22U_0603_6.3V6M

12

PC1165

1U_0201_6.3V6M

12

PC1183

1U_0201_6.3V6M

1

PC1114

PC1115

2

22U_0603_6.3V6M

1

PC1166

2

22U_0603_6.3V6M

1

PC1224

2

22U_0603_6.3V6M

U42@

1

2

1

2

U42@

1

PC1116

PC1117

2

22U_0603_6.3V6M

1

PC1167

PC1168

2

22U_0603_6.3V6M

1

2

PC11193

PC11194

22U_0603_6.3V6M

U42@

+VCCGT

1

2

PC11199

22U_0603_6.3V6M

U42@

1

PC1121

PC1122

PC1123

2

22U_0603_6.3V6M

12

PC1206

1U_0201_6.3V6M

1

PC1124

2

22U_0603_6.3V6M

1

2

12

1

PC1137

PC1184

PC1207

PC1139

PC1138

2

22U_0603_6.3V6M

1U_0201_6.3V6M

22U_0603_6.3V6M

12

PC1185

PC1186

1U_0201_6.3V6M

1

12

PC1125

1

2

12

PC1127

PC1126

2

22U_0603_6.3V6M

PC1140

PC1187

22U_0603_6.3V6M

1

PC1142

PC1141

2

22U_0603_6.3V6M

1U_0201_6.3V6M

22U_0603_6.3V6M

12

PC1189

PC1188

1U_0201_6.3V6M

1

PC1128

PC1129

2

22U_0603_6.3V6M

1

PC1144

PC1143

2

22U_0603_6.3V6M

12

PC1191

PC1190

1U_0201_6.3V6M

1

PC1131

PC1130

2

22U_0603_6.3V6M

1

12

PC1145

PC1235

2

22U_0603_6.3V6M

12

PC1193

PC1192

1U_0201_6.3V6M

1

PC1132

PC1133

2

22U_0603_6.3V6M

1

PC1147

PC1148

2

22U_0603_6.3V6M

1

PC1194

PC1195

2

22U_0603_6.3V6M

1

PC1134

1

2

1

2

PC1136

PC1135

2

22U_0603_6.3V6M

PC1149

PC1196

22U_0603_6.3V6M

1

2

22U_0603_6.3V6M

1

PC1150

PC1152

PC1151

2

22U_0603_6.3V6M

+VCCSA

1

2

B B

A A

5

4

1

PC1208

2

22U_0603_6.3V6M

1

PC1210

PC1209

2

22U_0603_6.3V6M

1

PC1211

PC1212

2

22U_0603_6.3V6M

1

PC1213

2

22U_0603_6.3V6M

1

PC1214

PC1215

2

22U_0603_6.3V6M

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PC1216

2

22U_0603_6.3V6M

Issued Date

12

PC1218

PC1217

1U_0201_6.3V6M

2017/06/05 2018/06/05

12

PC1219

PC1220

1U_0201_6.3V6M

12

PC1222

1U_0201_6.3V6M

Deciphered Date

PC1223

1U_0201_6.3V6M

2

PC1221

Compal Secret Data

1U_0201_6.3V6M

Compal Electronics, Inc.

Title

PWR-PROCESSOR_DECOUPLING

Size

Document Number Re v

C

KBL

Date: Sheet o f

1

48 51Wednesday, J une 21, 2017

2.A

5

4

3

2

1

3.PWM-VID S pec and component Values

PR8

PR7

PR10

PR20

PR21

PC9

Rboot

PR1451

2K_0402_1%

1 2

VGA@

1

PC1494

2

0.01U_0402_16V7K

@VGA@

RGND

VGA_B+

GND_SENSE_GPU<19>

+VGA_CORE

VDD_SENSE_GPU<19>

VGA@

PU1001

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND

18

GND

11

EN

13

ILMT

15

BYP

12

VGA@

PC1240 1U_0402_6.3V6K

Config A

0.6V

96

30K

PSI Pull high on HW side

VGA@

12

PR1458 20K_0402_1%

1 2

12

PC1482

2700P_0402_50V7K

VGA@

PR1467

VGA@

1 2

499K_0402_1%

@VGA@

VGA@

@VGA@

SY8286RAC_QFN20_3X3

Config B

Rrefadj

PR1448 20K_0402_1%

VGA@

C

0_0402_1%

1 2

PR1453

10_0402_1%

VGA@

10_0402_1%

1 2

4

Config C

0.65V0 .6V

1.15V

1.2V1.2V

0.9V0.9V0.875 V

25mV6.25mV6.25mV

2096

20K39K

39K

30K20K39K

3K2K1.5K

24K18K

01.5K

3K

1.8nf2.7nf1.5nf

PWM VID and Ou tput voltage control

1.Boot mode

2.Standby mode (don't support)

3.Normal mode

@VGA@

PR1463

0_0402_1%

1 2

PSI<22>

PR1464

@VGA@

0_0402_1%

GPU_VID0<22>

VCC

PAD

1 2

GPU_PSI

REFADJ

VGA@

4

5

PU1002

PSI

VID

6

REFADJ

7

REFIN

VREF_VGA

TON

Rton

PR1461

PR1449

PR1462 0_0402_1%

PG

BS

LX

FB

NC

REFIN

8

VREF

RT8812AGQW_WQFN20_3X3

9

TON

10

RGND

VSNS

SS11PGOOD13BOOT2

GND

RGND

12

PC1483

@VGA@

+3VS

12

@VGA@

PR1060 100K_0402_5%

9

BST_1.35V BST_1.35V_R

1

LX_1.35V

6

19

20

FB_1.35V

14

LDO_3V_1.35V

17

10

12

16

21

1

Css

PC1493

2

@VGA@

1000P_0402_50V7K

GPU_VSENSE

Confirm HW side

+1.35VGS_PGOOD <24>

12

0.01U_0402_16V7K

12

VGA@

PC1246

2.2U_0402_6.3V6M

PR1468

VGA@

1K_0402_5%

1 2

12

@VGA@

PC1481

.1U_0402_16V7K

PR1455

VGA@

2.2_0603_1%

BST1_VGA

GPU_EN

3

EN

VGA@

keep short pad, snubber is for EMI only.

1 2

2

1

BOOT1

20

UGATE1

PHASE1

19

LGATE1

18

PVCC

17

LGATE2

16

PHASE2

UGATE2

14

15

PR1460

VGA@

2.2_0603_1%

BST2_VGA

1 2

PR1456

10K_0402_5%

1 2

@VGA@

0_0402_5%

1 2

DH2_VGA-2

+3VS_DGPU_AON

DGPU_PWROK <19,23,24>

VGA@

PR1061

Vout=0.6V* ( 1+R1/R2) =0.6*(1+(1 2.4/10))

Vout=1.344V

Pull high on HW side

DGPU_MAIN_EN <22,24>

EN High Threshold = 1.6VRref1

DH1_VGA_1

BST1_VGA-1

1

VGA@

PC1495

0.22U_0603_25V7K

2

LX1_VGA

DL1_VGA

PR1454

VGA@

1_0603_1%

GPU_PVCC

1 2

12

VGA@

DL2_VGA

1U_0603_10V6K

LX2_VGA

1

VGA@

PC1492

0.22U_0603_25V7K

2

BST2_VGA-2

PC1237

0.1U_0201_10V6K

1 2

+1.35VGSP

DH1_VGA_1

LX1_VGA

DL1_VGA

Rocset

+5VS

PC1477

DH2_VGA-2

LX2_VGA

DL2_VGA

PC1238

VGA_RF@

PR1067

VGA_RF@

4.7_1206_5%

1 2

Use 7x7x3 size when the layout space is enough.

PL602

1 2

1UH_6.6A_20%_5X5X3_M

VGA@

FB=0.6 V

3

SNUB_1.35V

R1

R2

12

VGA@

12

PR1063 10K_0402_1%

VGA@

@

JUMP_43X118

112

680P_0603_50V7K

1 2

12

PR1062

12.4K_0402_1%

VGA@

PJ902

2

12

PC1239

PC1243

22U_0603_6.3V6M

330P_0402_50V7K

VGA@

+1.35VS_VRAM

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PC1244

VGA@

Module model information: RT8812A-2P_V1A.mdd for IC portion RT8812A-2P_V1B.mdd for SW portion

PL903

VGA_EMI@

VGA_B+

12

PC1474

PC1473

10U_0805_25V6K

LX1_VGA

LX2_VGA

10U_0805_25V6K

VGA@

PL904

VGA@

0.24UH_22A_+-20%_ 7X7X3_M

1

2

12

PR1452

VGA_RF@

4.7_1206_5%

SNUB_VGA1

12

PC1479

VGA_RF@

680P_0603_50V7K

12

PC1488

VGA@

10U_0805_25V6K

VGA@

12

PR1459

4.7_1206_5%

SNUB_VGA2

12

PC1490 680P_0603_50V7K

VGA@

2

1

PQ1401

D1

G1

7

D2/S1

S24S2

S23G2

AON6992_DFN5X6D-8-7

5

6

12

PR1457

10.7K_0402_1%

VGA@

2

1

PQ1402

D1

G1

7

D2/S1

S24S2

S23G2

AON6992_DFN5X6D-8-7

5

6

HCB2012KF-121T50_2P

12

PC1480

2200P_0402_50V7K

VGA_EMI@

4

3

1

+

2

PC1478

VGA@

330U_D1_2VY_R9M

VGA_B+

12

PC1489

VGA@

10U_0805_25V6K

PL905

0.24UH_22A_+-20%_ 7X7X3_M

1

4

3

2

VGA_RF@

12

PC1491

0.1U_0402_25V6

@VGA_EMI@

1

+

2

VGA@

+VGA_CORE

12

B+

+VGA_CORE

PC1475

330U_D1_2VY_R9M

VGA@

+VGA_CORE

Near GPU Core

12

PC835

PC11191

VGA@

10U_0402_6.3V6M

1

+

PC1476

2

330U_B2_2.5VM_R9M

+VGA_CORE EDP-Continuous 26.5A EDP-Peak 53A OCP min 66.4A

12

PC837

PC836

VGA@

22U_0603_6.3V6M

VGA@

4.7U_0402_6.3V6M

12

PC839

PC840

PC838

VGA@

4.7U_0402_6.3V6M

12

PC847

PC842

PC841

VGA@

22U_0603_6.3V6M

VGA@

4.7U_0402_6.3V6M

+1.35VGSP

12

PC1247

VGA@

PC1245

22U_0603_6.3V6M

VGA@

22U_0603_6.3V6M

+VGA_CORE

12

PC831

0.1U_0402_25V6

@VGA_RF@

2017/06/05 2018/06/05

PC833

PC832

0.1U_0402_25V6

@VGA_RF@

Compal Secret Data

2

12

PC834

0.1U_0402_25V6

@VGA_RF@

Deciphered Date

+VGA_CORE

12

PC821

VGA@

12

PC843

VGA@

Under GPU Core

12

PC822

PC823

PC824

VGA@

4.7U_0603_6.3V6M

12

1U_0402_16V6K

VGA@

4.7U_0402_6.3V6M

12

PC845

PC844

PC846

1U_0402_16V6K

VGA@

Title

Size

Custom

Date : Sheet of

GB4-128 package

12

PC826

PC825

VGA@

4.7U_0402_6.3V6M

PWR-CPU_GFX

Document Number Re v

KBL

12

PC827

VGA@

4.7U_0402_6.3V6M

Compal Electronics, Inc.

12

PC829

PC830

PC828

VGA@

4.7U_0603_6.3V6M

4.7U_0402_6.3V6M

1

4.7U_0402_6.3V6M

49 51Wednesday, Jun e 21, 2017

2.A

D D

PWM-VID Spec

Vmin

Vmax

Vboot

Voltage step

N of Voltage

Rrefadj

level

Rref1

Rboot

Rref2=PR20+PR21

C

Vboot=Vvref*Rref2/(Rref1+Rref2+Rboot)

Rt=Rrefadj // (Rboot+Rref2)

Vmin= Vvref*[Rref2/(Rref2+Rboot)]*[Rt/(Rref1+Rt)]

Vmax=Vvref*Rref2/[(Rref1//Rrefadj)+Rboot+ Rref2]

Vout=Vmin+N*V step

Vstep=(Vmax-Vm in)/Nmax

C C

12

VGA@

PR1466

18K_0402_1%

Rref2

12

@VGA@

PR1469

0_0402_5%

12

VGA@

PC1484

1U_0402_6.3V6K

B B

PR1444

0_0402_5%

PR1445

VGA@

1M_0402_1%

LDO_3V_1.35V

12

@VGA@

PR1440 0_0402_5%

ILMT_1.35V

@VGA@

12

@VGA@

0.22U_0402_10V6K

1 2

PC1472

B+

1.35V_PWR_ENEN_1.35V

PL906

VGA_EMI@

HCB2012KF-121T50_0805

1 2

B+_1.35V

PC1242

2200P_0402_50V7K

VGA_EMI@

12

1.35V_PWR_EN <23,24>

12

PC1249

PC1248

0.1U_0402_25V6 10U_0805_25V6K

VGA@

@EMI@

+19VB_1.35V

EN_1.35V

ILMT_1.35V

+3VALW

A A

EN :H>0.8V ; L<0.4V

EN pin don't floating If have pull down resistor at HW side, please delete PR601.

The current limit is set to 6A, 9A or 12A when this pin is pull low, floating or pull high.

5

Compal LA-E541P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual