A
COMPAL CONFIDENTIAL
B
C
D
E
1 1
MODEL NAME : CAZ10
PCB NO : LA-E122P
BOM P/N : 431A4D31L0X
Steamboat 12"/13" NonAR
Kabylake U
2 2
@ : Nopop Component
EMI@ : EMI Component
@EMI@ : EMI Nopop Component
ESD@ : ESDComponent
@ESD@ : ESD Nopop Component
2016-11-09
REV : 1.0 (A00)
3 3
RF@ : RF Component
@RF@ : RF Nopop Component
CXDP@ : XDP Component
MB PCB
Part Number
DA800187010
Description
PCB 1S5 LA-E122P REV0 MB NON-AR 1
CONN@ : Connector Component
ESPI@ : ESPI interface Component
LPC@ : External ESPI Component (SHD)
Layout Dell logo
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
COPYRIGHT 2016
ALL RIGHT RESERVED
REV:A00
PWB:
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Power CKT : 1107
A
B
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
D
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-E122P
LA-E122P
LA-E122P
1 59Wednesday, November 09, 2016
1 59Wednesday, November 09, 2016
1 59Wednesday, November 09, 2016
E
1.0
1.0
1.0
A
B
C
D
E
Steamboat 12&13 w/o AR Block Diagram
Memory BUS (DDR4)
2133 MHz
USB
up to 16GB
USB2.0[1]
USB3.0[1]
HDA Codec
ALC3246
1 1
2 2
PCIE[1]
Card reader
RTS5242
P29
SD4.0
P29
3 3
PCIE[9]
Intel Jacksonville
WGI219LM
Transformer
RJ45
P28
P28
P28
EDP CONN
HDMI 1.4
CONN
SATA[1]
M.2,3042 Key B
WWAN/LTE/Cache
P30
USB2.0[4]
USB3.0[2]
P27
eDP 14": Lane x 4; 12" :Lane x 2
HDMI
P22
SW2_DP1
To type C
SW2_DP2
To M2 WiGig card
M.2,3030 Key A
WLAN+BT/WIGIG
W25Q80DVSSIG
8M 4K sector
PCIE[4]
SW2_DP2
DP DeMUX
PS8338B
PCIE[3]
P30
USB2.0[7]
P32
reserve
P22
SHD_IO
DDI[1]
DDI[2]
INTEL
KABYLAKE_U MCP
SPI
ESPI
SMSC KBC
MEC5105
P32-33
PAGE 6~19
HD Audio I/F
SATA[2]/PCIE[12][11]
W25Q128FVSIQ
128M 4K sector
P8
W25Q128FVSIQ
128M 4K sector
TPM1.2/2.0 Nuvoton
NPCT650VB2YX
KB/TP CONN
FAN CONN
P8
reserve
P38
P33
P34
Steamboat 12 only support one DIMM
Reverse Type
DDR4-SO-DIMM X1
BANK 0, 1, 2, 3
P20~21
USB2.0[8]
USB2.0[5]
SLGC55544CVTR
USB POWER SHARE
USB2.0[1]_PS
P36
USB3.0[1]
USB2.0[2]
USB3.0[3]
INT.Speaker
Universal Jack
P31
Dig. MIC
P31
P31
P27
Trough eDP Cable
M.2 2280
SSD Conn
P35
LCD Touch
Camera
USB3.0 Conn
PS(Ext Port 1)
Right
USB3.0 Conn
(Ext Port 2)
Left Front
P27
P27
Trough eDP Cable
P36
P37
only 14"
LID SWITCH
LED board
USH CONN
P34
CPU&PCH XDP Port
Non-AR Type C
DP1.2 4 lanes
TX/RX
USB 3.0 + AM
Type C CONN.
4 4
USB2.0
CC
Vbus
HS Redriver Switch
TUSB546
P23
GPIO
PD Solution
TPS65982D
P24-35P26
SW2_DP1
USB3.0[6]
SMBUS
USB2.0[9]
Smart Card
5V VR
Charger
A
B
TDA8034HN
RFID/NFC
Fingerprint
CONN
C
USB2.0[10]
SPI
USH TPM1.2
BCM58102
SPI
USH board
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
P34
D
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
AUTOMATIC POWER
SWITCH(APS)
DC/DC Interface
POWER ON/OFF
SW & LED
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Block diagram
Block diagram
Block diagram
LA-E122P
LA-E122P
LA-E122P
E
P14
P11
P40
P39
1.0
1.0
2 59Wednesday, November 09, 2016
2 59Wednesday, November 09, 2016
2 59Wednesday, November 09, 2016
1.0
5
POWER STATES
Signal
State
S0 (Full ON) / M0
S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON ON OFF
D D
S4 (Suspend to DISK) / M3 ON ON OFF
S5 (SOFT OFF) / M3 ON ON OFFLOW HIGHLOW
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF HIGH
S5 (SOFT OFF) / M-OFF
SLP
S3#
HIGH
LOW HIGH HIGH
LOW HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
SLP
SLP
S5#
S4#
HIGH HIGH
LOW
LOW
SLP
A#
HIGH
HIGH
ALWAYS
PLANE
ON
PM TABLE
+5V_ALW
+3.3V_ALW
+3.3V_ALW_DSW
C C
State
S0
S3
S5 S4/AC
S5 S4/AC doesn't exist
power
plane
+3.3V_ALW_PCH +1.2V_MEM
+RTC_CELL
+1.8V_PRIM
+1.0V_PRIM
+1.0V_PRIM_CORE
+5V_ALW2
+3.3V_ALW2
+3.3V_RTC_LDO
+1.0V_MPHYGT
ON
ON
+3.3V_CV2
+2.5V_MEM
+1.0V_VCCST
+5V_RUN
+3.3V_RUN
+0.6V_DDR_VTT
+1.8V_RUN
+VCC_CORE
+VCC_GT
+VCC_SA
+1.0VS_VCCIO
ON ON
ON
OFF
OFFOFF
OFFON
OFF
OFF
M
PLANE
ON
4
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
CLOCKS
OFF
OFF
OFF
USB3.0
USB3.0-1
USB3.0-2
USB3.0-3
USB3.0-4
USB3.0-5
USB3.0-6
SSIC
SSIC
3
2
1
NonAR config
PCIE
PCIE-1
PCIE-2
PCIE-3
PCIE-4
PCIE-5
PCIE-6
PCIE-7
PCIE-8
PCIE-9
PCIE-10
PCIE-11
PCIE-12
SATA
JUSB3-->Left Rear (SB14 only)
SATA-0
SATA-1
SATA-1*
SATA-2
M.2 3042(SATA Cache)
M.2 2280 SSD
(PCIex2 or SATA)
12" not support JUSB3
JUSB1-->Right
M.2 3042(LTE)
JUSB2-->Left Front
Card Reader (PCIE)
Type-C Port
M.2 3030(WLAN)
M.2 3030(WIGIG)
NA
NA
NA
LOM
NA
USB PORT#DESTINATION
1
2
3
4
5
6
7
8
9
10
DESTINATION
JUSB1-->Right
JUSB2-->Left Front
JUSB3-->Left Rear (SB14 only)
M2 3042(WWAN)
Camera
NA
M.2 3030(BT)
Touch Screen
Type-C Port
USH
B B
A A
AR use 1086PP
Non AR use 1080PP
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Port assignment
Port assignment
Port assignment
LA-E122P
LA-E122P
LA-E122P
1
3 59Wednesday, November 09, 2016
3 59Wednesday, November 09, 2016
3 59Wednesday, November 09, 2016
1.0
1.0
1.0
5
Barrel
ADAPTER
D D
CHARGER
ISL88738
(PU901)
Type-C
ADAPTER
+PWR_SRC
SY8210A
(PU200)
SYX196D
(PU301)
SY8288C
(PU102)
4
SIO_SLP_S4#
0.6V_DDR_VTT_ON
SIO_SLP_SUS#
ALWON
+1.2V_MEM
+0.6V_DDR_VTT
+1.0V_PRIM
+5V_ALW
+5V_ALW2
TPS22961
(UZ26)
3
SIO_SLP_SUS#
SIO_SLP_S4#
+VCC_SFR_OC
TPS62134C
(PU401)
TPS62134D
(PU402)
EM5209
(UZ4)
RUN_ON
SIO_SLP_SUS#
RUN_ON
TPS22961
(UZ19)
TPS22961
(UZ21)
+1.0VS_VCCIO
+1.0V_PRIM_CORE
+5V_RUN
2
1
CPU PWR
PCH PWR
GT3 PWR
AUD_PWR_EN
Peripheral Device PWR
TYPE-C Power
+5V_RUN_AUDIO
RUN_ON
SIO_SLP_S0#
SIO_SLP_S4#
EM5209
(@UZ5)
+1.0V_VCCSTG
+1.0V_VCCST
BATTERY
SY8288B
C C
(PU100)
ALWON
+3.3V_RTC_LDO
+3.3V_ALW2
SLGC55544C
(UI3)
SY6288
(UI1)
USB_PWR_SHR_VBUS_EN
USB_PWR_EN1#
+5V_USB_CHG_PWR
+USB_EX2_PWR
+3.3V_ALW
RT8097A
(PU501)
+5V_ALW
CSD97374C
(PU604)
IMVP_VR_ON
+VCC_GT+VCC_SA
CSD97374C
(PU603)
IMVP_VR_ON
+VCC_CORE
TPS65982D
(UT5)
ISL95857
(PU602)
IMVP_VR_ON
B B
+PP_HV(5V~20V)
AO6405
(QV1)
EN_INVPWR
+BL_PWR_SRC
TYPE-C
+TBTA_Vbus_1(5V~20V)
EM5209
(UZ2)
EM5209
(UZ3)
EM5209
(UZ4)
G524B1T11U
(UV24)
SIO_SLP_SUS#
SIO_SLP_LAN#
AUX_EN_WOWL
@SIO_SLP_WLAN#
SIO_SLP_SUS#
@PCH_ALW_ON
RUN_ON
3.3V_WWAN_EN
ENVCC_PCH
+1.8V_PRIM
+3.3V_LAN
+3.3V_WLAN
+3.3V_ALW_PCH
+3.3V_RUN
+3.3V_WWAN
+LCDVDD
AOZ1336
(UZ8)
LP2301
(QV8)
LP2301A
(QZ1)
EM5209
(@UZ5)
RUN_ON
3.3V_TS_EN
3.3V_CAM_EN#
AUD_PWR_EN
+1.8V_RUN
+3.3V_TSP
+3.3V_CAM
+3.3V_RUN_AUDIO
A A
AP2204
(UT8)
5
+5V_ALW
+5V_TBT_VBUS
AP2112K
(UT7)
4
+3.3V_VDD_PIC
AP7361C
(PU503)
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
SIO_SLP_S4#
+2.5V_MEM
for DDR4
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Power rails
Power rails
Power rails
LA-E122P
LA-E122P
LA-E122P
1
4 59Wednesday, November 09, 2016
4 59Wednesday, November 09, 2016
4 59Wednesday, November 09, 2016
1.0
1.0
1.0
5
AW44
BB43
KBL-U
D D
AW45 AW42
03
SML1_SMBDATA
SML1_SMBCLK
D8E11
03
00
00
AY44
BB39
UPD2_SMBCLK
D7
UPD2_SMBDAT
E7
MEM_SMBCLK
MEM_SMBDATA
SML0_SMBCLK
SML0_SMBDATA
1K
1K
4
+3.3V_ALW_PCH
2.2K
2.2K
499
499
+3.3V_ALW
1K
1K
+3.3V_ALW_PCH
+3.3V_ALW_PCH
3
DMN65D8LDW-7
DMN65D8LDW-7
28
31
LOM
2
1
2.2K
2.2K
+3.3V_RUN
202
200
53
51
DIMMA
XDP
@2.2K
@2.2K
B3
E5
C12
E10
C3
B4
USH_SMBCLK
USH_SMBDAT
UPD1_SMBCLK
UPD1_SMBDAT
2.2K
2.2K
C C
01
01
02
02
KBC
04
04
+3.3V_ALW
+3.3V_ALW
DMN66D0LDW-7
DMN66D0LDW-7
2.2K
2.2K
2.2K
2.2K
+3.3V_CV2
M9
USH
L9
USH/B
+3.3V_TBTA_FLASH
B5
PD
A5
MEC 5105
F7
05
B6
05
A12
06
N10
B B
A A
06
07
07
08 C5
08
09
09
1010M3
EXPANDER_GPU_SMCLK
M4
EXPANDER_GPU_SMDATA
M7
C8
F6
E9
N2
PBAT_CHARGER_SMBCLK
PBAT__CHARGER_SMBDAT
2.2K
2.2K
2.2K
2.2K
+3.3V_ALW
+3.3V_ALW
100 ohm
100 ohm
Expander IO
Charger
7
BATTERY
6
CONN
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Port assignment
Port assignment
Port assignment
LA-E122P
LA-E122P
LA-E122P
1
5 59Wednesday, November 09, 2016
5 59Wednesday, November 09, 2016
5 59Wednesday, November 09, 2016
1.0
1.0
1.0
5
4
3
2
1
+3.3V_RUN
CPU_DP1_CTRL_CLK
RC175 2.2K_0402_5%
RC178 2.2K_0402_5%
D D
RC176 2.2K_0402_5%
RC177 2.2K_0402_5%
12
CPU_DP1_CTRL_DATA
12
CPU_DP2_CTRL_CLK
12
CPU_DP2_CTRL_DATA
12
AR(AR)/
HDMI(Non AR)
PS8338(AR)
+1.0VS_VCCIO
C C
B B
CPU_DP1_N0<22>
CPU_DP1_P0<22>
CPU_DP1_N1<22>
CPU_DP1_P1<22>
CPU_DP1_N2<22>
CPU_DP1_P2<22>
CPU_DP1_N3<22>
CPU_DP1_P3<22>
CPU_DP2_N0<21>
CPU_DP2_P0<21>
CPU_DP2_N1<21>
CPU_DP2_P1<21>
CPU_DP2_N2<21>
CPU_DP2_P2<21>
CPU_DP2_N3<21>
CPU_DP2_P3<21>
12
CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA
CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA
GPP_E23
EDP_COMP
CPU_DP1_CTRL_CLK<22>
CPU_DP1_CTRL_DATA<22>
CPU_DP2_CTRL_CLK<21>
CPU_DP2_CTRL_DATA<21>
@
T120
PAD~D
RC2 24.9_0402_1%
COMPENSATION PU FOR eDP
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
UC1A
CPU@
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
KBL-U_BGA1356
SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0
UC1I
CPU@
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
D33
CSI2_DP5
A31
CSI2_DN6
B31
CSI2_DP6
A33
CSI2_DN7
B33
CSI2_DP7
A29
CSI2_DN8
B29
CSI2_DP8
C28
CSI2_DN9
D28
CSI2_DP9
A27
CSI2_DN10
B27
CSI2_DP10
C27
CSI2_DN11
D27
CSI2_DP11
KBL-U_BGA1356
SKL-U
DDI
DISPLAY SIDEBANDS
SKL_ULT
EDP
1 OF 20
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
EDP_DISP_UTIL
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
9 OF 20
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
CSI2_COMP
TBT_FORCE_PWR
EMMC_RCOMP
EDP_TXN0 <27>
EDP_TXP0 <27>
EDP_TXN1 <27>
EDP_TXP1 <27>
CPU_DP1_AUXN
CPU_DP1_AUXP
CPU_DP3_AUXN
CPU_DP3_AUXP
CPU_DP1_HPD <22>
CPU_DP2_HPD <21>
EDP_HPD <27>
PANEL_BKLEN <27>
EDP_BIA_PWM <27>
ENVDD_PCH <27,32>
1 2
RC3
1 2
RC4 200_0402_1%
100_0402_1%
EDP_AUXN <27>
EDP_AUXP <27>
@
T281
PAD~D
@
T282
PAD~D
CPU_DP2_AUXN <21>
CPU_DP2_AUXP <21>
@
T1
PAD~D
@
T2
PAD~D
T19 @PAD~D
EDP_HPD
1 2
RC1 100K_0402_5%
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (1/14)
CPU (1/14)
CPU (1/14)
LA-E122P
LA-E122P
LA-E122P
6 59Wednesday, November 09, 2016
6 59Wednesday, November 09, 2016
6 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
4
3
2
1
For DDR4
DDR_A_DQS#[0..7]<20>
2 OF 20
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52
AM70
AM69
AT69
AT70
BA64
AY64
AY60
BA60
BA38
AY38
AY34
BA34
BA30
AY30
AY26
BA26
AW50
AT52
AY67
AY68
BA67
AW67
DDR_A_D[0..63]<20>
DDR_A_DQS[0..7]<20>
DDR_A_MA[0..16]<20>
DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#1
DDR_A_CLK1
DDR_A_CKE0
DDR_A_CKE1
DDR_A_CKE2
DDR_A_CKE3
DDR_A_CS#0
DDR_A_CS#1
DDR_A_ODT0
DDR_A_ODT1
DDR_A_MA5
DDR_A_MA9
DDR_A_MA6
DDR_A_MA8
DDR_A_MA7
DDR_A_BG0
DDR_A_MA12
DDR_A_MA11
DDR_A_ACT#
DDR_A_BG1
DDR_A_MA13
DDR_A_MA15
DDR_A_MA14
DDR_A_MA16
DDR_A_BA0
DDR_A_MA2
DDR_A_BA1
DDR_A_MA10
DDR_A_MA1
DDR_A_MA0
DDR_A_MA3
DDR_A_MA4
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_ALERT#
DDR_A_PARITY
+DDR_VREF_A_DQ
+DDR_VREF_B_DQ
DDR_A_CLK#0 <20>
DDR_A_CLK0 <20>
DDR_A_CLK#1 <20>
DDR_A_CLK1 <20>
DDR_A_CKE0 <20>
DDR_A_CKE1 <20>
@
T3
PAD~D
@
T4
PAD~D
DDR_A_CS#0 <20>
DDR_A_CS#1 <20>
DDR_A_ODT0 <20>
DDR_A_ODT1 <20>
DDR_A_BG0 <20>
DDR_A_ACT# <20>
DDR_A_BG1 <20>
DDR_A_BA0 <20>
DDR_A_BA1 <20>
DDR0_PAR,DDR0_ALERT# for DDR4
DDR_A_ALERT# <20>
DDR_A_PARITY <20>
+DDR_VREF_CA
@
T132
PAD~D
@
T226
PAD~D
DDR_VTT_CTRL <20>
UC1C
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
KBL-U_BGA1356
CPU@
SKL-U
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DRAM_RESET#
DDR_RCOMP[0]
DDR CH - B
DDR_RCOMP[1]
DDR_RCOMP[2]
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
3 OF 20
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
DDR1_PAR,DDR1_ALERT# for DDR4
DDR_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DDR_DRAMRST# <20>
DDR4, Ballout for side by side(Interleave)
D D
UC1B
CPU@
DDR_A_D0
AL71
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
C C
B B
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
KBL-U_BGA1356
SKL-U
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR CH - A
DDR0_ODT[1]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR0_ALERT#
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
DDR0_MA[3]
DDR0_MA[4]
DDR0_PAR
DDR4 COMPENSATION SIGNALS
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil
A A
1 2
RC5 121_0402_1%
1 2
RC6 80.6_0402_1%
1 2
RC7 100_0402_1%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (2/14)
CPU (2/14)
CPU (2/14)
LA-E122P
LA-E122P
LA-E122P
7 59Wednesday, November 09, 2016
7 59Wednesday, November 09, 2016
7 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236
PCH_SPI_CLK
PCH_SPI_D1
CXDP@
1 2
PCH_SPI_DO_XDP<14>
D D
C C
B B
A A
PCH_SPI_DO2_XDP<14>
PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R
33_0402_5%
@EMI@
12
RC28
33P_0402_50V8J
@EMI@
12
CC7
RC10 1K_0402_1%
CXDP@
1 2
RC11 1K_0402_1%
PCH_SPI_CS#2<34>
PCH_CL_CLK1<30>
+1.8V?
+3.3V_RUN
+3.3V_1.8V_ESPI
33_0402_5%
@EMI@
12
RC29
33P_0402_50V8J
@EMI@
12
CC8
PCH_SPI_CS#0_R1
PCH_SPI_D2_R1 PCH_SPI_CLK_0_R
PCH_SPI_CS#1_R1
PCH_SPI_D2_R1
PCH_CL_DATA1<30>
PCH_CL_RST1#<30>
RC13 10K_0402_5%LPC@
SIO_RCIN#<32>
ESPI_ALERT#<32>
RC21 8.2K_0402_1%
+3.3V_SPI
@
RC37 0_0402_5%
RC39 33_0402_5%
RC42 0_0402_5%@
RC43 33_0402_5%
@
PCH_SPI_D0
PCH_SPI_D2
PCH_SPI_D3
PCH_SPI_CS#0
PCH_SPI_CS#1
PCH_SPI_CS#2
12
12
PCH_SPI_D2_R1
RC30 1K_0402_5%
@
RC31 1K_0402_5%
@
RC316 1K_0402_5%
@
1 2
1 2
1 2
1 2
12
PCH_SPI_D3_R1
12
PCH_SPI_D3_R1
12
03/02:follow Intel MOW_2015WW06
4
UC1E
AV2
SPI0_CLK
AW3
SPI0_MISO
AV3
SPI0_MOSI
AW2
SPI0_IO2
AU4
SPI0_IO3
AU3
SPI0_CS0#
AU2
SPI0_CS1#
AU1
SPI0_CS2#
M2
GPP_D1/SPI1_CLK
M3
GPP_D2/SPI1_MISO
J4
GPP_D3/SPI1_MOSI
V1
GPP_D21/SPI1_IO2
V2
GPP_D22/SPI1_IO3
M1
GPP_D0/SPI1_CS#
G3
CL_CLK
G2
CL_DATA
G1
CL_RST#
AW13
GPP_A0/RCIN#
AY11
GPP_A6/SERIRQ
KBL-U_BGA1356
PCH_SPI_CS#0_R2
PCH_SPI_D1_0_R
PCH_SPI_D2_0_R
PCH_SPI_CS#1_R2
PCH_SPI_D1_1_R
PCH_SPI_D2_1_R
CPU@
SPI - FLASH
SPI - TOUCH
C LINK
PCH_SPI_D1_R1<34>
PCH_SPI_D0_R1<34>
PCH_SPI_CLK_R1<34>
128Mb Flash ROM
1
2
3
4
W25Q128FVSIQ_SO8
128Mb Flash ROM
@
1
2
3
4
W25Q128FVSIQ_SO8
PCH_SPI_CLK_R1
PCH_SPI_D0_R1
PCH_SPI_D1_R1
UC5
/CS
IO1
IO2
GND
UC6
/CS
IO1
IO2
GND
SKL-U
LPC
SOFTWARE TAA
PCH_SPI_D1_R1
PCH_SPI_D0_R1
PCH_SPI_CLK_R1
PCH_SPI_D3_R1
RC407 33_0402_5%
@
RC408 33_0402_5%
@
RC409 33_0402_5%
@
RC410 33_0402_5%
@
+3.3V_SPI
8
VCC
PCH_SPI_D3_0_R
7
IO3
6
CLK
PCH_SPI_D0_0_R
5
IO0
+3.3V_SPI
8
VCC
PCH_SPI_D3_1_R
7
IO3
PCH_SPI_CLK_1_R
6
CLK
PCH_SPI_D0_1_R
5
IO0
SMBUS, SMLINK
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
RPC1
PCH_SPI_D1_0_R
1 8
PCH_SPI_D0_0_R
2 7
PCH_SPI_CLK_0_R
3 6
PCH_SPI_D3_0_R
4 5
33_0804_8P4R_5%
1 2
1 2
1 2
1 2
CC9
1 2
0.1U_0201_10V6K
CC10
@
1 2
0.1U_0201_10V6K
3
5 OF 20
PCH_SPI_D3_1_RPCH_SPI_D3_R1
PCH_SPI_CLK_1_R
PCH_SPI_D0_1_R
PCH_SPI_D1_1_R
R7
R8
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
+3.3V_SPI
MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#
SML0_SMBCLK
SML0_SMBDATA
GPP_C5
SML1_SMBCLK
SML1_SMBDATA
GPP_B23
ESPI_IO0_R
ESPI_IO1_R
ESPI_IO2_R
ESPI_IO3_R
ESPI_CLK
PCI_CLK_LPC1
RC32 0_0402_5%
@
1 2
@
RC33 0_0402_5%
1 2
@
RC34 0_0402_5%
1 2
@
RC35 0_0402_5%
1 2
@
RC36 0_0402_5%
1 2
@
RC38 0_0402_5%
1 2
@
RC40 0_0402_5%
+3.3V_ALW_PCH
@
RC41 0_0402_5%
SML0_SMBCLK <28>
SML0_SMBDATA <28>
SML1_SMBCLK <32>
SML1_SMBDATA <32>
1 2
RC366
1 2
RC367
1 2
RC368
1 2
RC369
ESPI_CS# <32,33>
ESPI_RESET# <32>
1 2
RC16
EMI@
ESPI_CLK_5105
SML0_SMBCLK
SML1_SMBCLK
MEM_SMBCLK
1 2
1 2
RC22@ 22_0402_5%
CLKRUN# <32>
PCH_SPI_CS#1_R1
12
PCH_SPI_D0_R1
PCH_SPI_D1_R1
PCH_SPI_CLK_R1
PCH_SPI_CS#0_R1
PCH_SPI_D2_R1
PCH_SPI_D3_R1
2
15_0402_5%
15_0402_5%
15_0402_5%
15_0402_5%
15_0402_5%
CHECK,LPC_CLK FOR DEBUG CARD?
ESPI_IO0 <32,33>
ESPI_IO1 <32,33>
ESPI_IO2 <32,33>
ESPI_IO3 <32,33>
RF Request
1 2
CC316@RF@ 33P_0402_50V8J
1 2
CC318@RF@ 33P_0402_50V8J
1 2
CC319@RF@ 33P_0402_50V8J
1 2
CC320@RF@ 33P_0402_50V8J
Place close CPU side
E-T_6705K-Y20N-00L
22
21
PCH_SPI_CS#1
PCH_SPI_D0
PCH_SPI_D1
PCH_SPI_CLK
PCH_SPI_CS#0
PCH_SPI_D2
PCH_SPI_D3
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
JSPI1
CONN@
MEM_SMBCLK
MEM_SMBDATA
DMN65D8LDW-7_SOT363-6
ESPI_CLK_5105 <32,33>
GND2
GND1
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+3.3V_RUN
5
3 4
QC2B
2
1
6
QC2A
DMN65D8LDW-7_SOT363-6
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
SML0_SMBCLK
SML0_SMBDATA
Reserve
SML0_SMBCLK
SML0_SMBDATA
CLKRUN#
PCH_SMB_ALERT#
TLS CONFIDENTIALITY
HIGH
LOW(DEFAULT)
WEAK INTERNAL 20K PD
GPP_C5
EC interface
HIGH
LOW(DEFAULT)
WEAK INTERNAL 20k PD
GPP_B23
EXI BOOT STALL BYPASS
HIGH
LOW(DEFAULT)
WEAK INTERNAL PD
1
For BR/SB
DDR_XDP_WAN_SMBCLK <14,20>
DDR_XDP_WAN_SMBDAT <14,20>
1 2
RC318 2.2K_0402_5%
1 2
RC319 2.2K_0402_5%
1 2
RC12 1K_0402_5%
1 2
RC14 1K_0402_5%
1 2
RC15 1K_0402_5%
1 2
RC17 1K_0402_5%
1 2
RC347 499_0402_1%
1 2
RC348 499_0402_1%
1 2
RC19 499_0402_1%@
1 2
RC20 499_0402_1%@
1 2
RC27 8.2K_0402_5%LPC@
+3.3V_ALW_PCH
1 2
RC23 2.2K_0402_5%
ENABLE
DISABLE
+3.3V_ALW_PCH
1 2
RC25 4.7K_0402_5%ESPI@
ESPI
LPC
+3.3V_ALW_PCH
1 2
RC317 150K_0402_5%
ENABLED
DIABLED
+3.3V_RUN
+3.3V_ALW_PCH
+3.3V_LAN
+3.3V_RUN
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (3/14)
CPU (3/14)
CPU (3/14)
LA-E122P
LA-E122P
LA-E122P
8 59Wednesday, November 09, 2016
8 59Wednesday, November 09, 2016
8 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
4
3
2
1
For BR/SB
UC1F
+3.3V_RUN
BBS_BIT6
AH10
AH11
AH12
AF11
AF12
AN8
AP7
AP8
AR7
AM5
AN7
AP5
AN5
AB1
AB2
AB3
AD1
AD2
AD3
AD4
AH9
W4
U7
U6
U8
U9
D D
RC282 100K_0402_5%
RC237 10K_0402_5%
RC402 49.9K_0402_1%@
RC403 49.9K_0402_1%@
+3.3V_ALW_PCH
RC283 10K_0402_5%
RC330 49.9K_0402_1%
RC331 49.9K_0402_1%
C C
+3.3V_RUN
RC186 4.7K_0402_5%@
12
12
12
12
12
12
12
12
3.3V_TS_EN
SIO_EXT_SCI#
NRB_BIT
LPSS_UART2_RXD
LPSS_UART2_TXD
SIO_EXT_WAKE#
LPSS_UART2_RXD
LPSS_UART2_TXD
MEDIACARD_IRQ#<29>
TPM_PIRQ#<34>
SIO_EXT_SCI#<32>
3.3V_TS_EN<27>
I2C1_SDA_TP<38>
I2C1_SCK_TP<38>
+3.3V_RUN
10K_0402_5%
12
SBIOS_TX<33>
RC267
RC405 100K_0402_5%@
ONE_DIMM#
NRB_BIT
GPP_C8
LPSS_UART2_RXD
LPSS_UART2_TXD
NO REBOOT STRAP
HIGH
LOW(DEFAULT)
Weak IPD
B B
+3.3V_ALW_PCH
RC184 8.2K_0402_5%
@
No REBOOT
REBOOT ENABLE
BBS_BIT6
12
1 2
10K_0402_5%
12
DIMM Detect
HIGH
LOW
@
RC268
ONE_DIMM#
1 DIMM
2 DIMM
CPU@
LPSS ISH
GPP_B15/GSPI0_CS#
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI
GPP_B19/GSPI1_CS#
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI
GPP_C8/UART0_RXD
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS#
GPP_C11/UART0_CTS#
GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS#
GPP_C23/UART2_CTS#
GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL
GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL
GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL
GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL
GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
KBL-U_BGA1356
+5V_ALW
LPSS_UART2_TXD
LPSS_UART2_RXD
SKL-U
CONN@
JUART1
1
1
2
2
3
3
4
4
5
GND
6
GND
CVILU_CI1804M1VRA-NH
GPP_D9
GPP_D10
GPP_D11
GPP_D12
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
GPP_D15/ISH_UART0_RTS#
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
MEM_INTERLEAVED
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
GPP_A12/BM_BUSY#/ISH_GP6
6 OF 20
+3.3V_ALW_PCH +3.3V_ALW_PCH
RC371
10K_0402_5%
1 2
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
MEM_INTERLEAVED
AR_DET#
ISH_I2C2_SDA
ISH_I2C2_SCL
RTD3_CIO_PWR_EN
CLKDET#
TPM_TYPE
LID_CL#_PCH
ISH_I2C2_SDA <30>
ISH_I2C2_SCL <30>
9/24: Reserve for embedded location ,refer Intel PDG 0.9
ISH_UART0_RXD <30>
ISH_UART0_TXD <30>
ISH_UART0_RTS# <30>
ISH_UART0_CTS# <30>
SIO_EXT_WAKE# <32>
T18 @PAD~D
LCD_CBL_DET# <27>
@
T258
PAD~D
@
T268
PAD~D
GPP_A GROUP is +1.8V
AR_DET#
WWAN
WLAN
ISH_I2C2_SDA
ISH_I2C2_SCL
LCD_CBL_DET#
Reserved
RC400
10K_0402_5%
1 2
1 2
RC363 1K_0402_5%
1 2
RC362 1K_0402_5%
1 2
RC287 100K_0402_5%
TPM_TYPE
RC349 100_0402_1%@
+1.8V_RUN
+3.3V_RUN
1 2
BOOT BIOS Destination(Bit 6)
HIGH
LOW(DEFAULT)
Internal 20k PD
LPC
SPI
12
@
10K_0402_5%
RC372
DIMM TYPE
HIGH Interleave
12
@
10K_0402_5%
RC401
AR_DET#
NON ARHIGH
LOW ARLOW Non-Interleave
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (4/14)
CPU (4/14)
CPU (4/14)
LA-E122P
LA-E122P
LA-E122P
9 59Wednesday, November 09, 2016
9 59Wednesday, November 09, 2016
9 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
4
3
2
1
For NON AR, Steamboat
UC1H
CPU@
PCIE/USB3/SATA
D D
Card Reader RTS5242----->
Type-C Port ----->
M.2 3030(WLAN) --->
M.2 3030(WiGig) --->
C C
M.2 3042(SATA Cache
)--->
10/100/1G LAN --->
M2 2280 SSD --->
B B
PCIE_PRX_DTX_N1<29>
PCIE_PRX_DTX_P1<29>
PCIE_PTX_DRX_N1<29>
PCIE_PTX_DRX_P1<29>
USB3_PRX_DTX_N6<23>
USB3_PRX_DTX_P6<23>
USB3_PTX_DRX_N6<23>
USB3_PTX_DRX_P6<23>
PCIE_PRX_DTX_N3<30>
PCIE_PRX_DTX_P3<30>
PCIE_PTX_DRX_N3<30>
PCIE_PTX_DRX_P3<30>
PCIE_PRX_DTX_N4<30>
PCIE_PRX_DTX_P4<30>
PCIE_PTX_DRX_N4<30>
PCIE_PTX_DRX_P4<30>
SATA_PRX_DTX_N1<30>
SATA_PRX_DTX_P1<30>
SATA_PTX_DRX_N1<30>
SATA_PTX_DRX_P1<30>
PCIE_PRX_DTX_N9<28>
PCIE_PRX_DTX_P9<28>
PCIE_PTX_DRX_N9<28>
PCIE_PTX_DRX_P9<28>
1 2
RC45 100_0402_1%
CPU_XDP_PRDY#<14>
CPU_XDP_PREQ#<14>
PCIE_PRX_DTX_N11<35>
PCIE_PRX_DTX_P11<35>
PCIE_PTX_DRX_N11<35>
PCIE_PTX_DRX_P11<35>
PCIE_PRX_DTX_N12<35>
PCIE_PRX_DTX_P12<35>
PCIE_PTX_DRX_N12<35>
PCIE_PTX_DRX_P12<35>
PCIE_RCOMPN
PCIE_RCOMPP
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
KBL-U_BGA1356
SKL-U
SSIC / USB3
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB2
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
8 OF 20
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
USBCOMP
USB2_ID
AG3
USB2_VBUSSENSE
AG4
A9
C9
USB_OC2# USB_OC2#
D9
USB_OC3#
B9
J1
J2
J3
HDD_DET#
H2
M3042_PCIE#_SATA
H3
M2280_PCIE_SATA#
G4
H1
SATALED#
USB3_PRX_DTX_N1 <36>
USB3_PRX_DTX_P1 <36>
USB3_PTX_DRX_N1 <36>
USB3_PTX_DRX_P1 <36>
USB3_PRX_DTX_N2 <30>
USB3_PRX_DTX_P2 <30>
USB3_PTX_DRX_N2 <30>
USB3_PTX_DRX_P2 <30>
USB3_PRX_DTX_N3 <37>
USB3_PRX_DTX_P3 <37>
USB3_PTX_DRX_N3 <37>
USB3_PTX_DRX_P3 <37>
USB20_N1 <36>
USB20_P1 <36>
USB20_N2 <37>
USB20_P2 <37>
USB20_N4 <30>
USB20_P4 <30>
USB20_N5 <27>
USB20_P5 <27>
USB20_N7 <30>
USB20_P7 <30>
USB20_N8 <27>
USB20_P8 <27>
USB20_N9 <24>
USB20_P9 <24>
USB20_N10 <34>
USB20_P10 <34>
1 2
RC44 113_0402_1%
USB2_ID <24>
1 2
RC338 1K_0402_5%
USB_OC0# <36>
USB_OC1# <37>
Reserve
M3042_DEVSLP <30>
M2280_DEVSLP <35>
M3042_PCIE#_SATA <32>
M2280_PCIE_SATA# <35>
SATALED# <30,35,39>
-----> Ext USB3 Port 1 Charge (Right)
-----> M.2 3042(LTE)
-----> Ext USB3 Port 2 (Lert Front)
-----> Ext USB Port 1 Charge (Right)
-----> Ext USB Port 2(Left Front)
-----> M2 3042(WWAN)
-----> Camera
-----> M.2 3030(BT)
-----> LCD Touch
-----> Typce-C(Non AR)
-----> USH
NEED DOUBLE CHECK
USB_OC3#
USB_OC0#
USB_OC1#
10K_8P4R_5%
USB2_ID
@
RC337 0_0402_5%
M2280_PCIE_SATA#
SATALED#
M3042_PCIE#_SATA
HDD_DET#
RPC3
4 5
3
2
1
1 2
4 5
3
2
1
10K_8P4R_5%
RPC4
6
7
8
+3.3V_ALW_PCH
+3.3V_RUN
6
7
8
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (5/14)
CPU (5/14)
CPU (5/14)
LA-E122P
LA-E122P
LA-E122P
10 59Wednesday, November 09, 2016
10 59Wednesday, November 09, 2016
10 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
CLK_PCIE_N0<29>
Cardreader--->
D D
WLAN--->
WIGIG--->
M.2 SDD--->
LAN--->
+3.3V_LAN
C C
+3.3V_ALW_DSW
+1.0V_VCCST
+3.3V_ALW_PCH
B B
H_CPUPWRGD VCCST_PWRGD
12
CLK_PCIE_P0<29>
CLKREQ_PCIE#0<29>
+3.3V_RUN
CLK_PCIE_N1<30>
CLK_PCIE_P1<30>
CLKREQ_PCIE#1<30>
+3.3V_RUN
CLK_PCIE_N2<30>
CLK_PCIE_P2<30>
CLKREQ_PCIE#2<30>
+3.3V_RUN
CLK_PCIE_N3<35>
CLK_PCIE_P3<35>
CLKREQ_PCIE#3<35>
+3.3V_RUN
CLK_PCIE_N4<28>
CLK_PCIE_P4<28>
CLKREQ_PCIE#4<28>
+3.3V_RUN
+3.3V_RUN
RL70 10K_0402_5%@
RC323 10K_0402_5%
RC67 1K_0402_5%
RC71 1K_0402_5%
RC74 10K_0402_5%@
10/6 depop, prevent singal step.
RC411 10K_0402_5%@
@
T9
PAD~D
VCCST_PWRGD<14,32,33>
100P_0402_50V8J
12
CC300ESD@
ESD Request:place near CPU side
LAN_WAKE#
12
12
PCH_PCIE_WAKE#
12
VCCST_PWRGD
12
ME_SUS_PWR_ACK
12
PCH_PWROK
12
100P_0402_50V8J
CC301ESD@
@RF@
@RF@
@RF@
@RF@
@RF@
1 2
RC373 0_0402_5%
RC189 10K_0402_5%
1 2
RC374 0_0402_5%
RC47 10K_0402_5%
1 2
RC375 0_0402_5%
RC50 10K_0402_5%
1 2
RC376 0_0402_5%
RC59 10K_0402_5%
1 2
RC377 0_0402_5%
RC51 10K_0402_5%
@
RC190 10K_0402_5%
PCH_RSMRST#_AND<14,38>
1 2
RC77 1K_0402_5%@
1 2
RC78 60.4_0402_1%
ME_SUS_PWR_ACK<32>
PM_LANPHY_ENABLE<28>
12
12
12
12
12
12
PCH_PLTRST#
PCH_PCIE_WAKE#<32,33>
CLKREQ_PCIE#0_R
CLKREQ_PCIE#1_R
CLKREQ_PCIE#2_R
CLKREQ_PCIE#3_R
CLKREQ_PCIE#4_R
CLKREQ_PCIE#5_R
TC7SH08FU_SSOP5~D
H_CPUPWRGDH_CPUPWRGD_R
VCCST_PWRGD_CPU
SYS_PWROK<14,32>
PCH_PWROK<47>
PCH_DPWROK<33>
SUSACK#<32>
LAN_WAKE#<28,32>
3.3V_CAM_EN#<27>
RC311 10K_0402_5%
@
RC62 0_0402_5%
@
RC244 0_0402_5%
UC7
PCH_PLTRST#
SYS_RESET#
PCH_RSMRST#_AND
12
RC215
POP
NO Support Deep sleep
DE-POP
Support Deep sleep
PCH_DPWROK PCH_RSMRST#_AND
A A
0.01UF_0402_25V7K
1
2
1 2
RC215 0_0402_5%@
100K_0402_1%
12
@
RC220
CC266
12
RC75
10K_0402_5%
5
XDP_DBRESET#<14>
+3.3V_RUN
XDP_DBRESET#
RC225@ 8.2K_0402_5%
RC227@ 8.2K_0402_5%
4
SKL_ULT
CLOCK SIGNALS
PLTRST_LAN# <28>
PCH_PLTRST#_EC <33>
PCH_PLTRST#_AND <29,30,34,35>
SKL-U
5
P
B
4
O
A
G
UC12@
74AHC1G09GW_TSSOP5
3
SYS_RESET#_R
D42
C42
AR10
B42
A42
AT7
D41
C41
AT8
D40
C40
AT10
B40
A40
AU8
E40
E38
AU7
1 2
1 2
+3.3V_ALW_PCH
5
1
P
B
2
A
G
3
AN10
BA20
BB20
AR13
AP11
BB15
AM15
AW17
12
12
UC1J
CPU@
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
GPP_B5/SRCCLKREQ0#
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
GPP_B6/SRCCLKREQ1#
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
GPP_B7/SRCCLKREQ2#
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
GPP_B8/SRCCLKREQ3#
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
GPP_B9/SRCCLKREQ4#
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#
KBL-U_BGA1356
PCH_PLTRST#_AND
4
O
12
RC65
@
100K_0402_5%
UC1K
CPU@
SYSTEM POWER MANAGEMENT
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
PCH_PWROK
DSW_PWROK
GPP_A13/SUSWARN#/SUSPW RDNACK
GPP_A15/SUSACK#
WAKE#
GPD2/LAN_WAKE#
GPD11/LANPHYPC
AT15
GPD7/RSVD
KBL-U_BGA1356
1 2
@
RC290 0_0402_5%
+3.3V_RUN
1
ME_RESET#
2
if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)
4
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_OUT
XCLK_BIASREF
GPP_B11/EXT_PWR_GATE#
GPP_B2/VRALERT#
1 2
RC224 1K_0402_5%
F43
E43
BA17
E37
XTAL24_IN
E35
E42
AM18
RTCX1
AM20
RTCX2
AN18
SRTCRST#
AM16
RTCRST#
10 OF 20
PCH_PLTRST#
PCH_PLTRST#_AND
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
INTRUDER#
11 OF 20
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
CLK_ITPXDP_N
CLK_ITPXDP_P
SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
PCH_RTCX1
PCH_RTCX2
SRTCRST#
PCH_RTCRST# <32>
PCH_RTCRST#
CMOS1 must take care short & touch risk on layout placement
1 2
RC60 0_0402_5%
@
1 2
@
RC325 0_0402_5%
SIO_SLP_S0#
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
PCH_BATLOW#
AU13
AU11
PME#
AP16
INTRUDER#
MPHYP_PWR_EN
AM10
AM11
VRALERT#
+3.3V_RUN
@
RC291
10K_0402_5%
1 2
SYS_RESET#
3
1 2
RC297 0_0402_5%
@
1 2
RC298 0_0402_5%
@
SUSCLK <30,35>
1 2
RC52 2.7K_0402_1%
1 2
@
RC324 59_0402_1%
546765_546765_2014WW48_Skylake_MOW_Rev_1_0
1 2
RC56 20K_0402_5%
1 2
CC24 1U_0402_6.3V6K
1 2
RC57 20K_0402_5%
1 2
CC25 1U_0402_6.3V6K
1
1
2
SHORT PADS~D
@
CMOS1
SIO_SLP_S0# <17,34,45>
SIO_SLP_S3# <32,33>
SIO_SLP_S4# <17,32,43,46>
SIO_SLP_S5# <32>
SIO_SLP_SUS# <17,32,40,44,45,46>
SIO_SLP_LAN# <32,40>
SIO_SLP_WLAN# <32,40>
SIO_SLP_A# <32>
SIO_PWRBTN# <14,32>
AC_PRESENT <32>
@
T115
PAD~D
connect to VCCMPHYGTAON_1P0 enable pin
2
For SB/KW w/o AR
XTAL24_IN
CLK_ITPXDP_N_R <14>
CLK_ITPXDP_P_R <14>
+1.0V_CLK5
For Skylake, pop RC52,depop RC324
For Cannonlake, pop RC324,depop RC52
+RTC_CELL
2
PLTRST_TPM# <34>
2
XTAL24_OUT XTAL24_OUT_R
PCH_RTCX1
PCH_RTCX2
12
ESD Request:place near CPU side
SYS_RESET#
@ESD@
0.1U_0402_25V6
CC302
@
1
CC21
1 2
1M_0402_1%
RC46
1 2
1 2
RC295 0_0402_5%
For Skylake,YC1 24 MHz (50 Ohm ESR)
For Cannonlake,YC1 38.4 MHz (30 Ohm ESR)
546765_546765_2014WW48_Skylake_MOW_Rev_1_0
RC54
10M_0402_5%
1 2
1 2
@
RC296 0_0402_5%
8/21 can change to 10K for merge to RP
PCH_BATLOW#
AC_PRESENT
INTRUDER#
MPHYP_PWR_EN
VRALERT#
SIO_SLP_LAN#
SUSCLK
+3.3V_ALW_PCH
+3.3V_ALW
+3.3V_ALW
POWER_SW#_MB<33,39>
3
1
PCH_RTCX2_R
1 2
RC72 8.2K_0402_5%
1 2
RC243 10K_0402_5%
1 2
RC69 1M_0402_5%
1 2
RC387 10K_0402_5%@
1 2
RC73 10K_0402_5%
@
1 2
RC344 10K_0402_5%@
1 2
RC68 10K_0402_5%@
1 2
RC48 1K_0402_5%@
SIO_SLP_S3#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#
PCH_RTCRST#
SYS_RESET#
SIO_SLP_S0#
4
2
12
12P_0402_50V8J
YC1
24MHZ_12PF_X3G024000DC1H
CC22
1 2
12P_0402_50V8J
CC23
1 2
15P_0402_50V8J
YC2
32.768KHZ_12.5PF_9H03200042
ESR MAX=50k ohm
CC26
1 2
12P_0402_50V8J
+3.3V_ALW_DSW
+RTC_CELL
+3.3V_ALW_PCH
+3.3V_ALW
JAPS1
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
GND
20
GND
CVILU_CF4218FH0R0-05-NH
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (6/14)
CPU (6/14)
CPU (6/14)
LA-E122P
LA-E122P
LA-E122P
11 59Wednesday, November 09, 2016
11 59Wednesday, November 09, 2016
11 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
4
3
2
+1.0V_VCCSTG
1
PCH_JTAG_TDI
PCH_JTAG_TDO
D D
+1.0V_VCCST
RC79 49.9_0402_1%@
RC80 1K_0402_5%
+1.0V_VCCSTG
RC83 1K_0402_5%
+3.3V_RUN
RC414 10K_0402_5%
RC413 10K_0402_5%
C C
B B
RC278 10K_0402_5%
RC272 10K_0402_5%
@
RC279 10K_0402_5%
RC345 100K_0402_5%
RC292 10K_0402_5%
+3.3V_ALW_PCH
RC346 10K_0402_5%
RC288 10K_0402_5%
H_CATERR#
12
H_THERMTRIP#
12
H_PROCHOT#
12
TOUCHPAD_INTR#
12
CAM_MIC_CBL_DET#
12
CONTACTLESS_DET#
12
TOUCH_SCREEN_PD#
12
AUD_PWR_EN
12
IR_CAM_DET#
12
HOST_SD_WP#
12
SIO_EXT_SMI#
12
KB_DET#
12
HDA_SYNC_R<31>
HDA_BIT_CLK_R<31>
HDA_SDOUT_R<31>
HDA_RST#_R<31>
Close to RC93
TOUCH_SCREEN_PD# don't move to RPC,
ME_FWP
HDA_BIT_CLK_R
12
PECI_EC<32>
H_PROCHOT#<32,47,50>
H_THERMTRIP#<20,33>
TOUCH_SCREEN_DET#<27>
1 2
RC92 33_0402_5%
1 2
RC93 33_0402_5%EMI@
1 2
RC94 33_0402_5%
1 2
RC223 1K_0402_5%
1 2
RC95 33_0402_5%
47P_0402_50V8J
RF@
CC27
1 2
RC84 499_0402_1%
XDP_OBS0_R<14>
XDP_OBS1_R<14>
@
T10
PAD~D
@
T11
PAD~D
SIO_EXT_SMI#<32>
TOUCH_SCREEN_PD#<27>
TOUCHPAD_INTR#<32,38>
12
12
RC88
49.9_0402_1%
IR_CAM_DET#<27>
KB_DET#<38>
SPKR<31>
RC89
HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT
HDA_SDIN0<31>
HDA_RST#
H_PROCHOT#_R
H_THERMTRIP#
XDP_OBS2_R
XDP_OBS3_R
TOUCHPAD_INTR#
CPU_POPIRCOMP
PCH_POPIRCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
12
12
RC90
49.9_0402_1%
49.9_0402_1%
IR_CAM_DET#
KB_DET#
H_CATERR#
RC91
49.9_0402_1%
BA22
AY22
BB22
BA21
AY21
AW22
AY20
AW20
AK10
AW5
D63
A54
C65
C63
A65
C55
D55
B54
C56
A6
A7
BA5
AY5
AT16
AU16
H66
H65
UC1G
HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD
AK7
GPP_F1/I2S2_SFRM
AK6
GPP_F0/I2S2_SCLK
AK9
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD
H5
GPP_D19/DMIC_CLK0
D7
GPP_D20/DMIC_DATA0
D8
GPP_D17/DMIC_CLK1
C8
GPP_D18/DMIC_DATA1
GPP_B14/SPKR
KBL-U_BGA1356
UC1D
CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP
KBL-U_BGA1356
CPU@
AUDIO
RF Request. Place near CPU side (Intel MOW)
+3.3V_ALW_PCH +3.3V_ALW_PCH
HDA_SDOUT
12
ENABLE
DISABLE
SPKR
5
RC183 8.2K_0402_5%
@
TOP SWAP STRAP
A A
HIGH
LOW(DEFAULT)
Internal 20k PD
RC187 4.7K_0402_5%
@
Flash Descriptor Security override
HIGH
LOW(DEFAULT)
12
DISABLE
ENABLE
4
HDA_RST# HDA_SDIN0 HDA_SDOUT
1
2
CC331
RF@
2.2P_0402_50V8C
CPU@
CPU MISC
SKL-U
JTAG
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
SKL-U
1
2
CC332
RF@
2.2P_0402_50V8C
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
B61
PROC_TCK
D60
PROC_TDI
A61
PROC_TDO
C60
PROC_TMS
B59
B56
D59
A56
C59
C61
PCH_TRST#
A59
JTAGX
4 OF 20
SDIO/SDXC
GPP_A17/SD_PWR_EN#/ISH_GP7
GPP_A16/SD_1P8_SEL
1
2
CC333
RF@
2.2P_0402_50V8C
3
CPU_XDP_TCLK XDP_JTAGX
@
RC328 0_0402_5%
CPU_XDP_TCLK
CPU_XDP_TDI
CPU_XDP_TDO
CPU_XDP_TMS
CPU_XDP_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
CPU_XDP_TRST#
XDP_JTAGX
RC87 1K_0402_5%@
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
SD_RCOMP
1 2
GPP_F23
7 OF 20
CPU_XDP_TCLK <14>
CPU_XDP_TDI <14>
CPU_XDP_TDO <14>
CPU_XDP_TMS <14>
CPU_XDP_TRST# <14>
PCH_JTAG_TCK <14>
PCH_JTAG_TDI <14>
PCH_JTAG_TDO <14>
PCH_JTAG_TMS <14>
AB11
AB13
AB12
W12
CONTACTLESS_DET#
W11
W10
AUD_PWR_EN
W8
W7
BA9
BB9
SD_RCOMP
AB7
AF13
1 2
RC86 51_0402_5%
@
+1.0V_VCCSTG
1 2
RC96 200_0402_1%
PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX
@ESD@
0.1U_0402_25V6
12
CC303
1 2
CAM_MIC_CBL_DET# <27>
CONTACTLESS_DET# <34>
AUD_PWR_EN <31>
ESD request,Place near CPU side.
PCH_JTAG_TMS
Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the entire region of the SPI flash to be updated using FPT.
+3.3V_ALW_PCH
ME_FWP PCH has internal 20K PD.
(suspend power rail)
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
HOST_SD_WP# <29>
@ESD@
0.1U_0402_25V6
12
CC304
2
1 2
RC81 51_0402_5%
1 2
RC82 100_0402_5%
1 2
RC130 51_0402_5%
ME_FWPME_FW_EC
1 2
@
@
RC222
1K_0402_5%
1 2
RC221 0_0402_5%
PT,ST pop RC222 and SW1; MP pop RC221
ME_FW_EC<32>
@ESD@
0.1U_0402_25V6
12
CC305
ME_FWP
H_THERMTRIP# H_PROCHOT#
0.1U_0402_25V6
12
1
2
3
4
5
@ESD@
CC312
@
SW1
A
B
C
G1
G2
SS3-CMFTQR9_3P
12
0.1U_0402_25V6
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (7/14)
CPU (7/14)
CPU (7/14)
LA-E122P
LA-E122P
LA-E122P
1
@ESD@
CC310
1.0
1.0
12 59Wednesday, November 09, 2016
12 59Wednesday, November 09, 2016
12 59Wednesday, November 09, 2016
1.0
5
D D
4
CFG[0..19]<14>
3
2
1
CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin
12
RC113 10K_0402_1%
@
CFG0
RC112 10K_0402_1%
@
RC110 10K_0402_1%
@
12
12
Stall reset sequence
HIGH(DEFAULT)
LOW
C C
RC109 1K_0402_5%
eDP enable
HIGH(DEFAULT)
LOW
B B
No stall(Normal Operation)
stall
12
CFG4
Disabled
Enabled
+1.0V_PRIM_XDP
RC114 49.9_0402_1%
RC115 1.5K_0402_5%
ITP_PMODE<14>
@
T16
PAD~D
@
T17
PAD~D
CFG_RCOMP
12
ITP_PMODE
12
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
AL25
AL27
BA70
BA68
E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
E8
AY2
AY1
D1
D3
K46
K45
C71
B70
F60
A52
J71
J68
F65
G65
F61
E61
UC1S
CPU@
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2
RSVD_AY1
RSVD_D1
RSVD_D3
RSVD_K46
RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70
RSVD_TP_BA68
RSVD_J71
RSVD_J68
VSS_F65
VSS_G65
RSVD_F61
RSVD_E61
KBL-U_BGA1356
RESERVED SIGNALS-1
SKL-U
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
TP5
TP6
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
TP4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
TP1
TP2
VSS_AY71
ZVM#
RSVD_TP_AW71
RSVD_TP_AW70
MSM#
PROC_SELECT#
19 OF 20
BB68
BB69
AK13
AK12
BB2
BA3
AU5
AT5
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
A69
B69
AY3
D71
C70
C54
D54
AY4
BB3
AY71
AR56
AW71
AW70
AP56
C64
@
T12
PAD~D
@
T13
PAD~D
@
T14
PAD~D
@
T15
PAD~D
@
T130
PAD~D
@
T126
PAD~D
@
T127
PAD~D
@
T113
PAD~D
@
T114
PAD~D
1 2
RC120 100K_0402_5%@
For Skylake , RC120 depop
For Cannonlake, RC120 pop
546765_546765_2014WW48_Skylake_MOW_Rev_1_0
UC1T
1/5 2014WW52 MOW reserve to support
Cannonlake-U PCH compatibility
close UC1.U11/U12 and <400mil
1 2
RC313 0_0402_5%
@
+VCC_1P8+1.8V_PRIM
AW69
RSVD_AW69
AW68
RSVD_AW68
AU56
RSVD_AU56
AW48
RSVD_AW48
C7
RSVD_C7
U12
RSVD_U12
U11
RSVD_U11
H11
1
2
@
RSVD_H11
KBL-U_BGA1356
CC222
1U_0402_6.3V6K
ZVM# for SKYLAKE-U 2+3e
MSM# for SKYLAKE-U 2+3e
+1.0V_VCCST
SPARE
SKL-U
RSVD_F6
RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
20 OF 20
F6
E3
C11
B11
A11
D12
C12
F52
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (8/14)
CPU (8/14)
CPU (8/14)
LA-E122P
LA-E122P
LA-E122P
13 59Wednesday, November 09, 2016
13 59Wednesday, November 09, 2016
13 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
+1.0V_PRIM
1 2
RC216 0_0603_1%
@
+1.0V_PRIM_XDP
0.1U_0201_10V6K
0.1U_0201_10V6K
@
CC28
1
1
2
2
D D
Place near
JXDP1
VCCST_PWRGD<11,32,33>
PCH_RSMRST#_AND<11,38>
C C
+1.0V_VCCST
+3.3V_RUN
+1.0V_PRIM_XDP
5
+1.0V_PRIM_XDP
@
CC29
XDP_OBS0_R<12>
XDP_OBS1_R<12>
RC123 1K_0402_5%@
RC124CXDP@
PCH_SPI_DO_XDP<8>
SYS_PWROK<11,32>
RC132 150_0402_5%
RC218 150_0402_5%@
RC219 10K_0402_5%@
RC137 3K_0402_5%
RC138 51_0402_5%
@
RC239 0_0402_5%
CXDP@
RC240 0_0402_5%
CXDP@
RC5 need to close to JCPU1
1 2
1 2
1K_0402_5%
12
12
12
12
12
FIVR_EN
CFG0
RC217 0_0402_5%
@
RC126 1K_0402_5%@
RC128 0_0402_5%
CXDP@
RC129 0_0402_5%
@
DDR_XDP_WAN_SMBDAT<8,20>
DDR_XDP_WAN_SMBCLK<8,20>
FIVR_EN_R
FIVR_EN
FIVR_EN
XDP_DBRESET#
CPU_XDP_PREQ#
CPU_XDP_PREQ#<10>
CPU_XDP_PRDY#<10>
1 2
1 2
1 2
1 2
1 2
1 2
PCH_JTAG_TCK<12>
CPU_XDP_TCLK<12>
CPU XDP
H_VCCST_PWRGD_XDP
SIO_PWRBTN#<11,32>
CPU_XDP_PREQ#
CPU_XDP_PRDY#
RESET_OUT#_R
CPU_XDP_TCLK
+1.0V_PRIM_XDP
CFG0
CFG1
CFG2
CFG3
XDP_OBS0
XDP_OBS1
CFG4
CFG5
CFG6
CFG7
FIVR_EN_R
+3.3V_ALW_PCH+1.0VS_VCCIO
1 2
0.1U_0402_25V6
12
CC33@
Place near JXDP1.47
4
XDP_PRSNT_PIN1
JXDP1
1
1
3
3
5
5
7
7
9
9
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556
575758
595960
61
61
62
GND
E-T_6601K-Y61N-04L
RC133
1.5K_0402_5%
CXDP@
PCH_SPI_DO_XDP
RESET_OUT#_R
CXDP@
1 2
1 2
2
2
4
4
6
6
8
8
10
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
63
CFG3
RC121 0_0402_5%
RC122 0_0402_5%@
CONN@
GND
Place near JXDP1.48
+1.0V_PRIM_XDP
XDP_DBRESET#
CFG17
CFG16
CFG8
CFG9
CFG10
CFG11
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15
ITP_PMODE
XDP_DBRESET#
TDO_XDP
TRST#_XDP
TDI_XDP
XDP_TMS
0.1U_0402_25V6
CXDP@
12
CC32
3
CFG[0..19]<13>
CLK_ITPXDP_P_R <11>
CLK_ITPXDP_N_R <11>
ITP_PMODE <13>
XDP_DBRESET# <11>
PCH_SPI_DO2_XDP <8>
SIO_PWRBTN#
Place near JXDP1.41
+3.3V_ALW_DSW
1.5K_0402_5%
1 2
0.1U_0402_25V6
12
2
+3.3V_RUN
CC30
12
0.1U_0201_10V6K
TDO_XDP
TDI_XDP
XDP_TMS
TRST#_XDP
RUNPWROK<32>
@
RC241
CC269
@
UC8
14
VCC
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
74CBTLV3126BQ_DHVQFN14_2P5X3
CPU_XDP_TMS
RC131 51_0402_5%
CPU_XDP_TDI
RC134 51_0402_5%
CPU_XDP_TDO
RC135 100_0402_5%
CPU_XDP_TRST#
RC136
@
CPU_XDP_TCLK
RC139 51_0402_5%
XDP_TMS
TDI_XDP
TDO_XDP
1 2
@
RC228 0_0402_5%
1 2
@
RC229 0_0402_5%
1 2
@
RC230 0_0402_5%
GND PAD
1 2
1 2
1 2
1 2
1 2
1B
2B
3B
4B
GND
51_0402_5%
1
3
6
8
11
7
15
+1.0V_VCCSTG
PCH_JTAG_TMS <12>
PCH_JTAG_TDI <12>
PCH_JTAG_TDO <12>
CPU_XDP_TDO <12>
CPU_XDP_TDI <12>
CPU_XDP_TMS <12>
CPU_XDP_TRST# <12>
B B
A A
TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#
@ESD@
0.1U_0402_25V6
12
CC306
ESD request,Place near JXDP1 side. ESD request,Place near UC8 side.
@ESD@
0.1U_0402_25V6
12
CC307
@ESD@
0.1U_0402_25V6
12
CC308
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (9/14)
CPU (9/14)
CPU (9/14)
LA-E122P
LA-E122P
LA-E122P
14 59Wednesday, November 09, 2016
14 59Wednesday, November 09, 2016
14 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
4
3
2
1
+VCC_CORE: 0.3~1.35V
D D
@
T122
PAD~D
@
T123
PAD~D
C C
VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e
(w/ on package cache)
+VCC_CORE +VCC_CORE
+VCC_CORE_G0
+VCC_CORE_G1
A30
VCC_A30
A34
VCC_A34
A39
VCC_A39
A44
VCC_A44
AK33
VCC_AK33
AK35
VCC_AK35
AK37
VCC_AK37
AK38
VCC_AK38
AK40
VCC_AK40
AL33
VCC_AL33
AL37
VCC_AL37
AL40
VCC_AL40
AM32
VCC_AM32
AM33
VCC_AM33
AM35
VCC_AM35
AM37
VCC_AM37
AM38
VCC_AM38
G30
VCC_G30
K32
RSVD_K32
AK32
RSVD_AK32
AB62
VCCOPC_AB62
P62
VCCOPC_P62
V62
VCCOPC_V62
H63
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61
AC63
VCCOPC_SENSE
AE63
VSSOPC_SENSE
AE62
VCCEOPIO
AG62
VCCEOPIO
AL63
VCCEOPIO_SENSE
AJ62
VSSEOPIO_SENSE
KBL-U_BGA1356
UC1L
CPU@
SKL-U
CPU POWER 1 OF 4
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
12 OF 20
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
VCCSENSE
VSSSENSE
H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT
+1.0V_VCCSTG_R
VIDSCLK <47>
+VCC_CORE
RC140
100_0402_1%
1 2
12
RC141
100_0402_1%
1 2
RC143 0_0603_5%
@
VCCSENSE <47>
VSSSENSE <47>
+1.0V_VCCSTG
VIDSCLK
RF Request
1 2
CC321@RF@ 33P_0402_50V8J
Place close CPU side
PSC(Primary side cap) : Place as close to the package as possible
BSC(Backside cap) : Place on secondary side, underneath the package
Component placement order:
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source
B B
SVID ALERT
VIDALERT_N<47>
SVID DATA
A A
VIDSOUT<47>
+1.0V_VCCST
1 2
+1.0V_VCCST
1 2
56_0402_1%
RC152
100_0402_1%
RC157
CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 - 1500mils
H_CPU_SVIDALRT#
12
RC153220_0402_5%
CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 - 1500mils
VIDSOUT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (10/14)
CPU (10/14)
CPU (10/14)
LA-E122P
LA-E122P
LA-E122P
15 59Wednesday, November 09, 2016
15 59Wednesday, November 09, 2016
15 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
4
3
2
1
+VCCGT: 0.3~1.35V
+VCCGTX : 0.3~1.35V
+VCC_GT +VCC_GT
D D
C C
+VCC_GT
RC161
100_0402_1%
1 2
VCC_GT_SENSE<47>
VSS_GT_SENSE<47>
B B
VCC_GT_SENSE
VSS_GT_SENSE
12
RC163
100_0402_1%
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
M62
N63
N64
N66
N67
N69
A48
A53
A58
A62
A66
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
J70
J69
UC1M
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENSE
KBL-U_BGA1356
CPU@
CPU POWER 2 OF 4
SKL-U
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
13 OF 20
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
VCCGTX for SKYLAKE-U 2+3e
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
Reserve for soldering
+VCC_GTUS
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (11/14)
CPU (11/14)
CPU (11/14)
LA-E122P
LA-E122P
LA-E122P
16 59Wednesday, November 09, 2016
16 59Wednesday, November 09, 2016
16 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
4
3
2
1
+5V_ALW
CZ104
@
1 2
4
O
@
1
2
CC253
1U_0402_6.3V6K
UZ34
1
2
+1.2V_MEM
1
2
CC250
1U_0402_6.3V6K
@
RZ119 0_0402_5%
UZ26
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
CC251
1U_0402_6.3V6K
SIO_SLP_S0#
SIO_SLP_S3#
AND
1 2
+VCCPLL_OC source
+1.2V_MEM+1.2V_MEM_CPUCLK
@
1 2
RC231 0_0402_5%
D D
PSC
1
1
2
1
CC177
CC176
2
2
10U_0402_6.3V6M
10U_0402_6.3V6M
PSC
22U_0603_6.3V6M
CC294
1
1
2
2
+1.0V_VCCST
C C
B B
PSC
1
2
CC195
1U_0402_6.3V6K
VDDQ: 8.45A
1
CC179
CC178
2
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
CC296
CC295
1
2
+1.0V_VCCSTG
BSC
1
2
@
CC199
PSC
1
CC297
2
10U_0402_6.3V6M
1U_0402_6.3V6K
+1.2V_MEM_CPUCLK
+VCC_SFR_OC
1
2
CC288
1U_0402_6.3V6K
1
2
CC322
RF@
RF Request
+1.0V_VCCST source
+1.2V_MEM
2.2P_0402_50V8C
AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51
AM40
AL23
A18
A22
K20
K21
UC1N
CPU@
CPU POWER 3 OF 4
VDDQ_AU23
VDDQ_AU28
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51
VDDQC
VCCST
VCCSTG_A22
VCCPLL_OC
VCCPLL_K20
VCCPLL_K21
KBL-U_BGA1356
+1.0V_VCCST
1
2
CC202
PSC
1U_0402_6.3V6K
SKL-U
+VCC_SA
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
14 OF 20
1 2
RC168 100_0402_1%
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
+1.0VS_VCCIO
VCCIO_SENSE
VSSIO_SENSE
+VCC_SA
+1.0VS_VCCIO
12
RC166
100_0402_1%
VSA_SEN- <47>
VSA_SEN+ <47>
RC165
1 2
12
RC167
100_0402_1%
VCCIO_SENSE <45>
VSSIO_SENSE <45>
100_0402_1%
12
CZ102 1U_0402_6.3V6K
VCCSTG_EN
SIO_SLP_SUS#<11,32,40,44,45,46>
SIO_SLP_S4#<11,17,32,43,46>
1 2
@
RZ120 0_0402_5%
+3.3V_ALW
5
1
P
B
2
A
G
3
+1.0VS_VCCIO
0.1U_0402_10V7K
TC7SH08FU_SSOP5~D
PSC
1
2
CC252
1U_0402_6.3V6K
+1.0V_VCCSTG source
+VCC_SFR_OC
6
VOUT
5
GND
S0 S0Ix S3
HIGH
HIGH
HIGH LOW LOW
LOW
HIGH
LOW
LOW
1 2
CZ103 0.1U_0201_10V6K
+1.0V_VCCST+1.0V_VCCSTG
1 2
RZ151 0_0603_5%
@
+1.0V_PRIM
12
CZ100 1U_0402_6.3V6K
SIO_SLP_S4#<11,17,32,43,46>
A A
5
+1.0V_PRIM
+5V_ALW
UZ21
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
4.4mohm/6A
TR=12.5us@Vin=1.05V
VOUT
GND
6
5
4
+1.0V_VCCST_C
PJP1
@
12
PAD-OPEN1x1m
1 2
CZ101 0.1U_0201_10V6K
+1.0V_VCCST
SIO_SLP_S0#<11,34,45>
RUN_ON<32,33,40,45>
TC7SH08FU_SSOP5~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
12
CZ105 1U_0402_6.3V6K
@
+5V_ALW
+3.3V_ALW
5
1
P
B
O
2
A
G
UZ35
3
1 2
RZ320 0_0402_5%
4
VCCSTG_EN
1
2
7
3
4
UZ19
VIN1
VIN2
VIN thermal
VBIAS
ON
TPS22961DNYR_WSON8
4.4mohm/6A
TR=12.5us@Vin=1.05V
VOUT
GND
2
12
@
PJP2
PAD-OPEN1x1m
+1.0V_VCCSTG_C
6
5
DELL CONFIDENTIAL/PROPRIETARY
pop option with UZ19
1 2
CZ106 0.1U_0201_10V6K
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (12/14)
CPU (12/14)
CPU (12/14)
LA-E122P
LA-E122P
LA-E122P
17 59Wednesday, November 09, 2016
17 59Wednesday, November 09, 2016
17 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
+1.0V_PRIM
Imax : 2.57A
D D
+1.8V_PRIM
C C
+3.3V_ALW_PCH
LPC@
+1.8V_PRIM
@ESPI@
B B
1 2
@
RC299 0_0603_5%
1 2
@
RC300 0_0402_5%
1 2
@
RC301 0_0402_5%
1 2
@
RC302 0_0402_5%
1 2
@
RC303 0_0402_5%
1 2
@
RC304 0_0402_5%
@
1 2
RC234 0_0402_5%
1 2
@
RC235 0_0402_5%
1 2
RC211 0_0402_5%
1 2
RC212 0_0402_5%
1 2
@
RC305 0_0402_5%
1 2
@
RC306 0_0402_5%
1 2
@
RC307 0_0402_5%
1 2
@
RC308 0_0402_5%
+3.3V_ALW_PCH
1 2
LC1 BLM15GA750SN1D_2P
1
CC215
2
@
1U_0402_6.3V6K
+1.0V_MPHYAON
+1.0V_CLK6
+1.0V_DTS
+1.0V_CLK1
+1.0V_CLK3
+1.8V_PGPPF
+3.3V_1.8V_PGPPG
+3.3V_1.8V_PGPPA
+3.3V_PGPPB+3.3V_ALW_PCH
+3.3V_PGPPC
+3.3V_PGPPD
+3.3V_PGPPE
8/28 schematic review
close UC1.AF20 and <400mil
+3.3V_1.8V_ESPI
PJP4
@
1 2
PAD-OPEN1x1m
Must be +1.8V for eSPI I/F
+3.3V_VCCHDA
1
CC313
2
0.1U_0201_10V6K
close UC1.AJ19 and <400mil
+1.0V_MPHYAON
1
2
CC203
1U_0402_6.3V6K
+1.0V_MPHYGT
close UC1.N15 and CC210 <400mil, CC211 <120mil
1
2
+1.0V_SRAM
1
2
close UC1.K15, UC1.L15 and <100mil
@
1 2
RC169 0_0603_5%
1
2
CC281
@
0.1U_0201_10V6K
+1.0V_PRIM
1 2
LC2 BLM15GA750SN1D_2P
1
CC225
2
@
47U_0805_6.3V6M
close UC1.V15 and <100mil
4
close UC1.AL1 and <120mil
1
2
CC204
1U_0402_6.3V6K
1
CC210
2
CC211
@
1U_0402_6.3V6K
47U_0805_6.3V6M
CC217
+1.0V_APLLEBB
@
1U_0402_6.3V6K
1
2
+1.0V_AMPHYPLL+1.0V_MPHYGT
1
CC219
2
@
+1.0V_PRIM_CORE+1.0VO_DSW
1
2
close UC1.AB19 and <400milclose UC1.K17 and <120mil
CC205
@
1U_0402_6.3V6K
close UC1.AF18 and <400mil
+1.0V_AMPHYPLL
+1.0V_APLL
+1.0V_PRIM
+3.3V_ALW_DSW
+3.3V_VCCHDA
+3.3V_SPI
+3.3V_ALW_PCH
+1.0V_PRIM
close UC1.N18 and <120mil
CC218
1U_0402_6.3V6K
close UC1.K15 and <120mil
1
2
CC264
@
1U_0402_6.3V6K
47U_0805_6.3V6M
+1.0V_APLL
1
CC314
2
0.1U_0201_10V6K
+1.0V_PRIM
1
CC206
2
@
AB19
1U_0402_6.3V6K
AB20
P18
AF18
AF19
V20
V21
AL1
K17
L1
N15
N16
N17
P15
P16
K15
L15
V15
AB17
Y18
AD17
AD18
AJ17
AJ19
AJ16
AF20
AF21
T19
T20
AJ21
AK20
N18
1 2
@
RC170 0_0402_5%
close UC1.K19 and <100mil
@
RC173 0_0402_5%
close UC1.N20 and <100mil
UC1O
CPU@
CPU POWER 4 OF 4
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
DCPDSW_1P0
VCCMPHYAON_1P0
VCCMPHYAON_1P0
VCCMPHYGT_1P0_N15
VCCMPHYGT_1P0_N16
VCCMPHYGT_1P0_N17
VCCMPHYGT_1P0_P15
VCCMPHYGT_1P0_P16
VCCAMPHYPLL_1P0
VCCAMPHYPLL_1P0
VCCAPLL_1P0
VCCPRIM_1P0_AB17
VCCPRIM_1P0_Y18
VCCDSW_3P3_AD17
VCCDSW_3P3_AD18
VCCDSW_3P3_AJ17
VCCHDA
VCCSPI
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCPRIM_3P3_AJ21
VCCPRIM_1P0_AK20
VCCAPLLEBB
KBL-U_BGA1356
1 2
3
PCH PWR
+1.0V_CLK2+1.0V_PRIM
1
CC220
2
@
47U_0805_6.3V6M
+1.0V_CLK4+1.0V_PRIM
1
CC226
2
@
47U_0805_6.3V6M
SKL-U
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCPRIM_3P3_V19
VCCPRIM_1P0_T1
VCCATS_1P8
VCCRTCPRIM_3P3
VCCRTC_AK19
VCCRTC_BB14
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
15 OF 20
close UC1.L19 and <100mil
close UC1.AG15 and <120mil
Must be +1.8V
AK15
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
AN13
+3.3V_1.8V_PGPPA
+3.3V_PGPPD
+1.8V_PGPPF
+3.3V_1.8V_PGPPG
+1.0V_DTS
+3.3V_ALW_PCH
close UC1.BB10 and <120mil
+1.0V_CLK1
+1.0V_CLK2
+1.0V_CLK3
+1.0V_CLK4
+1.0V_CLK5
+3.3V_PGPPB
close UC1.AA1 and <400mil
close UC1.AK19 and <120mil
+DCPRTC
CORE_VID0 <45>
CORE_VID1 <45>
Take care!!! Note1 on Page 19
1 2
@
RC171 0_0402_5%
1
CC221
2
@
47U_0805_6.3V6M
+1.0V_MPHYGT source
561280_561280_KBL_UY_PDG_Rev0p9 :MPHY has defeature
2
close UC1.Y16 and <400mil
+3.3V_PGPPC
1
1
CC265
2
@
CC207
2
@
1U_0402_6.3V6K
1U_0402_6.3V6K
+RTC_CELL
1
1
2
CC270
2
CC214
+1.0V_CLK6
0.1U_0201_10V6K
0.1U_0201_10V6K
close UC1.A10 and <120mil
1
CC216
2
@
1U_0402_6.3V6K
+3.3V_PGPPE
close UC1.T16 and <400mil
1
CC208
2
@
1U_0402_6.3V6K
1
2
CC213
1U_0402_6.3V6K
+3.3V_ALW_PCH+1.0V_CLK5+1.0V_PRIM
+1.0V_MPHYGT
+3.3V_ALW_PCH
+1.8V_PRIM
1
2
CC212
1U_0402_6.3V6K
close UC1.AK17 and <120mil
1
1
CC223
2
2
CC224
1U_0402_6.3V6K
0.1U_0201_10V6K
1
1 2
@
RC309 0_0603_5%
1 2
@
RC310 0_0603_5%
+3.3V_1.8V_PGPPG
1
CC209
2
@
1U_0402_6.3V6K
close UC1.V19 and <120mil
+1.0V_SRAM
+1.0V_APLLEBB
close UC1.AD15 and <400mil
1
CC326
2
1U_0402_6.3V6K
RF Request
+1.0V_APLL +3.3V_VCCHDA +1.0V_APLLEBB
1
1
2
2
CC324
CC323
RF@
RF@
2.2P_0402_50V8C
1 2
PAD-OPEN1x3m
1
2
CC325
2.2P_0402_50V8C
PJP3
@
RF@
+1.0V_MPHYGT+1.0V_PRIM
2.2P_0402_50V8C
+3.3V_ALW +3.3V_ALW_DSW
A A
1 2
@
RC214 0_0402_5%
22U_0603_6.3V6M
22U_0603_6.3V6M
@
@
CC279
CC280
1
1
2
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (13/14)
CPU (13/14)
CPU (13/14)
LA-E122P
LA-E122P
LA-E122P
18 59Wednesday, November 09, 2016
18 59Wednesday, November 09, 2016
18 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
4
3
2
1
Note1: VCCPRIM_CORE Implementation with PCH CORE_VID Recommendation
CPU@
SKL-U
UC1P
GND 1 OF 3
A5
VSS
A67
VSS
A70
VSS
AA2
VSS
AA4
D D
C C
B B
AA65
AA68
AB15
AB16
AB18
AB21
AD13
AD16
AD19
AD20
AD21
AD62
AD8
AE64
AE65
AE66
AE67
AE68
AE69
AF10
AF15
AF17
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH6
AH63
AH64
AH67
AJ15
AJ18
AJ20
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AL28
AL32
AL35
AL38
AL45
AL48
AL52
AL55
AL58
AL64
AB8
AF1
AF2
AF4
AJ4
AK8
AL2
AL4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
KBL-U_BGA1356
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
16 OF 20
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
BA10
BA14
BA18
BA23
BA28
BA32
BA36
BA45
AV1
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1
BA2
F68
CPU@
UC1Q
GND 2 OF 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
KBL-U_BGA1356
SKL-U
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
17 OF 20
BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41
F8
VSS
G10
VSS
G22
VSS
G43
VSS
G45
VSS
G48
VSS
G5
VSS
G52
VSS
G55
VSS
G58
VSS
G6
VSS
G60
VSS
G63
VSS
G66
VSS
H15
VSS
H18
VSS
H71
VSS
J11
VSS
J13
VSS
J25
VSS
J28
VSS
J32
VSS
J35
VSS
J38
VSS
J42
VSS
J8
VSS
K16
VSS
K18
VSS
K22
VSS
K61
VSS
K63
VSS
K64
VSS
K65
VSS
K66
VSS
K67
VSS
K68
VSS
K70
VSS
K71
VSS
L11
VSS
L16
VSS
L17
VSS
KBL-U_BGA1356
CPU@
UC1R
GND 3 OF 3
SKL-U
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
18 OF 20
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (14/14)
CPU (14/14)
CPU (14/14)
LA-E122P
LA-E122P
LA-E122P
19 59Wednesday, November 09, 2016
19 59Wednesday, November 09, 2016
19 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
4
3
2
1
For DDR4
DDR_A_DQS#[0..7]<7>
DDR_A_D[0..63]<7>
DDR_A_DQS[0..7]<7>
DDR_A_MA[0..16]<7>
Layout Note:
D D
C C
B B
A A
Place near JDIMM1
+1.2V_MEM
10U_0603_10V6M
10U_0603_10V6M
CD1
12
12
+1.2V_MEM
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CD9
+0.6V_DDR_VTT
12
DIMM Select
DIMM1
*
DIMM2
DIMM3
DIMM4
10U_0603_10V6M
CD2
12
1U_0402_6.3V6K
12
CD10
Layout Note:
Place near
JDIMM1.258
10U_0603_10V6M
CD22
SA01SA1
0
1
0
1
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
330U_D3_2.5VY_R6M
@
CD4
CD5
CD3
12
1U_0402_6.3V6K
12
CD11
1U_0402_6.3V6K
CD23
1
2
0
0
1
CD6
12
12
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CD13
CD14
CD12
1U_0402_6.3V6K
CD24
1
2
12
SA2
12
0
0
0
0
12
1U_0402_6.3V6K
12
RD4
@
0_0402_5%
@
RD5
0_0402_5%
12
CD7
CD8
CD17
12
+
+2.5V_MEM
1U_0402_6.3V6K
12
CD16
CD15
+DDR_VREF_A_CA
+3.3V_RUN+3.3V_RUN+3.3V _RUN
12
RD6
@
0_0402_5%
12
@
RD7
0_0402_5%
12
@
0_0402_5%
12
0.1U_0402_10V6K
1
CD25
2
RD8
DIMM1_SA0
DIMM1_SA1
DIMM1_SA2
@
RD9
0_0402_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_10V6M
CD19
12
1
2
1
2
@
RD10
0_0603_5%
2.2U_0402_6.3V6M
CD27
10U_0603_10V6M
1
CD20
CD21
2
+3.3V_RUN_DIMM1
0.1U_0201_10V6K
CD28
1
2
DDR_XDP_WAN_SMBCLK<8,14>
DDR_A_CKE0<7>
DDR_A_BG1<7>
DDR_A_BG0<7>
DDR_A_CLK0<7>
DDR_A_CLK#0<7>
DDR_A_PARITY<7>
DDR_A_BA1<7>
DDR_A_CS#0<7>
DDR_A_MA14<7>
DDR_A_ODT0<7>
DDR_A_CS#1<7>
DDR_A_ODT1<7>
T51PAD~D
@
1
1
CD18
2
2
2.2U_0402_6.3V6M
@
1
CD26
2
+3.3V_RUN
JDIMM1 REV Type H=9.2
JDIMM1
1
DDR_A_D4
DDR_A_D0
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D6
DDR_A_D9
DDR_A_D8
DDR_A_D10
DDR_A_D14
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D19
DDR_A_D23
DDR_A_D28
DDR_A_D24
DDR_A_D26 DDR_A_D27
DDR_A_D30 DDR_A_D31
DDR_A_CKE0
DDR_A_BG1
DDR_A_BG0
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA6
DDR_A_MA3
DDR_A_MA1
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_PARITY
DDR_A_BA1
DDR_A_CS#0
DDR_A_MA14
DDR_A_ODT0
DDR_A_CS#1
DDR_A_ODT1
DDR_A_D32
DDR_A_D36
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D35
DDR_A_D34
DDR_A_D40
DDR_A_D44
DDR_A_D42 DDR_A_D46
DDR_A_D47 DDR_A_D43
DDR_A_D52
DDR_A_D48
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D55
DDR_A_D51
DDR_A_D59
DDR_A_D58
DDR_A_D62
DDR_A_D63
+3.3V_RUN_DIMM1
VSS1
3
DQ5
5
VSS3
7
DQ1
9
VSS5
DQS0_c11DM0_n/DBI0_n
13
DQS0_t
15
VSS8
17
DQ7
19
VSS10
21
DQ3
23
VSS12
25
DQ13
27
VSS14
29
DQ9
31
VSS16
33
DM1_n/DBI_n
35
VSS17
37
DQ15
39
VSS19
41
DQ10
43
VSS21
45
DQ21
47
VSS23
49
DQ17
51
VSS25
DQS2_c53DM2_n/DBI2_n
55
DQS2_t
57
VSS28
59
DQ23
61
VSS30
63
DQ19
65
VSS32
67
DQ29
69
VSS34
71
DQ25
73
VSS36
DM3_n/DBI3_n75DQS3_t
77
VSS37
79
DQ30
81
VSS39
83
DQ26
85
VSS41
87
CB5/NC
89
VSS43
91
CB1/NC
93
VSS45
DQS8_c95DM8_n/DBI_n/NC
97
DQS8_t
99
VSS48
101
CB2/NC
103
VSS50
105
CB3/NC
107
VSS52
109
CKE0
111
VDD1
113
BG1
115
BG0
117
VDD3
119
A12
121
A9
123
VDD5
125
A8
127
A6
129
VDD7
131
A3
133
A1
135
VDD9
137
CK0_t
139
CK0_c
141
VDD11
143
PARITY
145
BA1
147
VDD13
149
CS0_n
151
WE_n/A14
153
VDD15
155
ODT0
157
CS1_n
159
VDD17
161
ODT1
163
VDD19
165
C1, CS3_n,NC
167
VSS53
169
DQ37
171
VSS55
173
DQ33
175
VSS57
177
DQS4_c
179
DQS4_t
181
VSS60
183
DQ38
185
VSS62
187
DQ34
189
VSS64
191
DQ44
193
VSS66
195
DQ40
197
VSS68
199
DM5_n/DBI5_n
201
VSS69
203
DQ46
205
VSS71
207
DQ42
209
VSS73
211
DQ52
213
VSS75
215
DQ49
217
VSS77
219
DQS6_c
221
DQS6_t
223
VSS80
225
DQ55
227
VSS82
229
DQ51
231
VSS84
233
DQ61
235
VSS86
237
DQ56
239
VSS88
241
DM7_n/DBI7_n
243
VSS89
245
DQ62
247
VSS91
249
DQ58
251
VSS93
253
SCL
255
VDDSPD
257
VPP1
259
VPP2
261
GND1
LCN_DAN05-Q0406-0103
CONN@
LINK SP07001D200 DONE
EVENT_n/NF
RAS_n/A16
CAS_n/A15
C0/CS2_n/NC
DM4_n/DBI4_n
DM6_n/DBI6_n
VSS11
VSS13
VSS15
DQS1_c
DQS1_t
VSS18
VSS20
VSS22
VSS24
VSS26
VSS27
VSS29
VSS31
VSS33
VSS35
DQS3_c
VSS38
VSS40
VSS42
CB4/NC
VSS44
CB0/NC
VSS46
VSS47
CB6/NC
VSS49
CB7/NC
VSS51
RESET_n
VDD2
ACT_n
ALERT_n
VDD4
VDD6
VDD8
VDD10
CK1_t/NF
CK1_c/NF
VDD12
A10/AP
VDD14
VDD16
VDD18
VREFCA
VSS54
VSS56
VSS58
VSS59
VSS61
VSS63
VSS65
VSS67
DQS5_c
DQS5_t
VSS70
VSS72
VSS74
VSS76
VSS78
VSS79
VSS81
VSS83
VSS85
VSS87
DQS7_c
DQS7_t
VSS90
VSS92
VSS94
GND2
VSS2
VSS4
VSS6
VSS7
VSS9
DQ12
DQ14
DQ11
DQ20
DQ16
DQ22
DQ18
DQ28
DQ24
DQ31
DQ27
CKE1
DQ36
DQ32
DQ39
DQ35
DQ45
DQ41
DQ47
DQ43
DQ53
DQ48
DQ54
DQ50
DQ60
DQ57
DQ63
DQ59
+1.2V_MEM+1.2V_MEM
2
DDR_A_D1
4
DQ4
6
DDR_A_D5
8
DQ0
10
12
14
DDR_A_D3
16
DQ6
18
DDR_A_D7
20
DQ2
22
DDR_A_D11
24
26
DDR_A_D12
28
DQ8
30
DDR_A_DQS#1
32
DDR_A_DQS1
34
36
DDR_A_D13
38
40
DDR_A_D15
42
44
DDR_A_D17DDR_A_D21
46
48
DDR_A_D16DDR_A_D20
50
52
54
56
DDR_A_D18
58
60
DDR_A_D22
62
64
DDR_A_D29
66
68
DDR_A_D25
70
72
DDR_A_DQS#3
74
DDR_A_DQS3
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
DDR_DRAMRST#_R
108
DDR_A_CKE1
110
112
DDR_A_ACT#
114
DDR_A_ALERT#
116
118
DDR_A_MA11
120
A11
A7
A5
A4
A2
A0
BA0
A13
SA2
SDA
SA0
VTT
SA1
DDR_A_MA7
122
124
DDR_A_MA5
126
DDR_A_MA4
128
130
DDR_A_MA2
132
JDIMM1_EVENT#
134
136
DDR_A_CLK1
138
DDR_A_CLK#1
140
142
DDR_A_MA0
144
DDR_A_MA10
146
148
DDR_A_BA0
150
DDR_A_MA16
152
154
DDR_A_MA15
156
DDR_A_MA13
158
160
162
164
DIMM1_SA2
166
168
DDR_A_D37
170
172
DDR_A_D33
174
176
178
180
DDR_A_D38
182
184
DDR_A_D39
186
188
DDR_A_D41
190
192
DDR_A_D45
194
196
DDR_A_DQS#5
198
DDR_A_DQS5
200
202
204
206
208
210
DDR_A_D49
212
214
DDR_A_D53
216
218
220
222
DDR_A_D54
224
226
DDR_A_D50
228
230
DDR_A_D56
232
234
DDR_A_D57
236
238
DDR_A_DQS#7
240
DDR_A_DQS7
242
244
DDR_A_D60
246
248
DDR_A_D61
250
252
254
DIMM1_SA0
256
258
DIMM1_SA1
260
262
DDR_A_CKE1 <7>
DDR_A_ACT# <7>
DDR_A_ALERT# <7>
DDR_A_CLK1 <7>
DDR_A_CLK#1 <7>
DDR_A_BA0 <7>
+DDR_VREF_A_CA
T50 PAD~D
@
+DDR_VREF_A_CA
DDR_XDP_WAN_SMBDAT <8,14>
+0.6V_DDR_VTT+2.5V_MEM
+1.2V_MEM
470_0402_1%
12
RD11
1 2
@
RD12 0_0402_5%
+1.2V_MEM
12
12
1
CD29
@
0.1U_0402_25V6
2
JDIMM1_EVENT#
DDR_VTT_CTRL<7>
1 2
RD14 1K_0402_5%
@
UD1
1
NC
VCC
2
A
Y
3
GND
74AUP1G07SE-7_SOT353_5P
+1.2V_MEM
5
4
DDR_DRAMRST#DDR_DRAMRST#_R
1K_0402_1%
RD15
1 2
RD17 2_0402_1%
1K_0402_1%
RD16
1 2
CD32@0.1U_0201_10V6K
1 2
RD19 100K_04 02_5%
CHECK
DDR_DRAMRST# <7>
0.022U_0402_16V7K
CD31
12
24.9_0402_1%
12
RD18
H_THERMTRIP# <1 2,33>
0.6V_DDR_VTT_ON <43>
+3.3V_RUN
+DDR_VREF_CA+DDR_VREF_A_CA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
DDR4
DDR4
DDR4
LA-E122P
LA-E122P
LA-E122P
1
20 59Wednesday, November 09, 2016
20 59Wednesday, November 09, 2016
20 59Wednesday, November 09, 2016
1.0
1.0
1.0
5
4
3
2
1
For Steamboat12/14 &Kirkwood
+3.3V_RUN
0.1U_0201_10V6K
0.1U_0201_10V6K
CV84
1
1
2
2
CPU_DP2_P0_C
CPU_DP2_N0_C
CPU_DP2_P1_C
CPU_DP2_N1_C
CPU_DP2_P2_C
CPU_DP2_N2_C
CPU_DP2_P3_C
CPU_DP2_N3_C
SW2_PS8338_P1
SW2_PS8338_P0
CPU_DP2_AUXP_C
CPU_DP2_AUXN_C
SW2_PS8338_CFG0
SW2_PS8338_PC10
SW2_PS8338_PC11
SW2_PS8338_PC20
SW2_PS8338_PC21
+3.3V_RUN
CV85
UV7
5
VDD33
21
VDD33
30
VDD33
51
VDD33
57
VDD33
6
IN_D0p
7
IN_D0n
9
IN_D1p
10
IN_D1n
12
IN_D2p
13
IN_D2n
15
IN_D3p
16
IN_D3n
4
IN_CA_DET
3
IN_HPD
2
I2C_CTL_EN
1
Pl1/SCL_CTL
60
Pl0/SDA_CTL
22
IN_DDC_SCL
23
IN_DDC_SDA
24
IN_AUXp
25
IN_AUXn
59
CFG0
58
CFG1
56
PC10
55
PC11
54
PC20
53
PC21
11
GND
19
GND
52
GND
61
PAD(GND)
PS8338BQFN60GTR-A0_QFN60_5X9
OUT1_D0p
OUT1_D0n
OUT1_D1p
OUT1_D1n
OUT1_D2p
OUT1_D2n
OUT1_D3p
OUT1_D3n
OUT2_D0p
OUT2_D0n
OUT2_D1p
OUT2_D1n
OUT2_D2p
OUT2_D2n
OUT2_D3p
OUT2_D3n
OUT1_AUXp_SCL
OUT1_AUXn_SDA
OUT2_AUXp_SCL
OUT2_AUXn_SDA
OUT1_CA_DET
OUT1_HPD
OUT2_CA_DET
OUT2_HPD
PEQ
CEXT
REXT
Priority : Dockport -> WIGI
SW
PD
50
49
47
46
45
44
42
41
40
39
37
36
35
34
32
31
26
27
28
29
SW2_DP2_CADET
43
48
SW2_DP1_CADET
33
38
SW2_PS8338_SW
18
SW2_PS8338_PEQ
8
14
17
20
RV97
12
12
4.99K_0402_1%
2.2U_0402_6.3V6M
CV96
SW2_DP2_P0 <30>
SW2_DP2_N0 <30>
SW2_DP2_P1 <30>
SW2_DP2_N1 <30>
SW2_DP2_P2 <30>
SW2_DP2_N2 <30>
SW2_DP2_P3 <30>
SW2_DP2_N3 <30>
SW2_DP1_P0 <23>
SW2_DP1_N0 <23>
SW2_DP1_P1 <23>
SW2_DP1_N1 <23>
SW2_DP1_P2 <23>
SW2_DP1_N2 <23>
SW2_DP1_P3 <23>
SW2_DP1_N3 <23>
SW2_DP2_AUXP <30>
SW2_DP2_AUXN <30>
SW2_DP1_AUXP <23,24>
SW2_DP1_AUXN <23,24>
SW2_DP2_HPD <30>
SW2_DP1_HPD <23,24>
WIGI
Dockport
SW2_DP1_AUXN
D D
C C
RV70 100K_0402_5%
RV71 100K_0402_5%
RV85 4.7K_0402_5%
RV89 4.7K_0402_5%
RV95 4.7K_0402_5%
RV73 1M_0402_5%
RV74 1M_0402_5%
RV76 100K_0402_5%
RV77 100K_0402_5%
+3.3V_RUN
@
RV79
RV81
1 2
4.7K_0402_5%
4.7K_0402_5%
12
RV82
RV80
@
4.7K_0402_5%
4.7K_0402_5%
12
SW2_DP2_AUXN
12
SW2_PS8338_CFG0
12
SW2_PS8338_SW
12
SW2_PS8338_P0
12
SW2_DP1_CADET
12
SW2_DP2_CADET
12
SW2_DP1_AUXP
12
SW2_DP2_AUXP
12
@
@
RV83
1 2
12
RV84
@
@
@
RV93
RV87
RV91
1 2
1 2
4.7K_0402_5%
4.7K_0402_5%
12
12
RV90
@
@
4.7K_0402_5%
4.7K_0402_5%
1 2
1 2
4.7K_0402_5%
4.7K_0402_5%
12
RV94
RV88
@
4.7K_0402_5%
4.7K_0402_5%
12
SW2_PS8338_P1
SW2_PS8338_PEQ
SW2_PS8338_PC10
SW2_PS8338_PC11
SW2_PS8338_PC20
SW2_PS8338_PC21
CPU_DP2_P0<6>
CPU_DP2_N0<6>
CPU_DP2_P1<6>
CPU_DP2_N1<6>
CPU_DP2_P2<6>
CPU_DP2_N2<6>
CPU_DP2_P3<6>
CPU_DP2_N3<6>
CPU_DP2_CTRL_CLK<6>
CPU_DP2_CTRL_DATA<6>
for support TMDS signal need contact SCL/SDA to P22,23
CPU_DP2_AUXP<6>
CPU_DP2_AUXN<6>
CV62 CV61 close to pin30 &57
CV66,CV69,CV70 close to pin5,21,51
0.01UF_0402_25V7K
0.01UF_0402_25V7K
12
CV81
CV86 0.1U_0201_10V6K
CV87 0.1U_0201_10V6K
CV88 0.1U_0201_10V6K
CV89 0.1U_0201_10V6K
CV90 0.1U_0201_10V6K
CV91 0.1U_0201_10V6K
CV92 0.1U_0201_10V6K
CV93 0.1U_0201_10V6K
1 2
CV94 0.1U_0201_10V6K
1 2
CV95 0.1U_0201_10V6K
12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
CPU_DP2_HPD<6>
0.1U_0201_10V6K
CV83
1
CV82
2
B B
A A
Port switching control or priority configuration. Internal pull down ~150KΩ, 3.3V
I/O
For Control Switching Mode (CFG0 = L):
SW = L: Port1 is selected (default)
SW = H: Port2 is selected
For Automatic Switching Mode (CFG0 = H):
SW = L: Port1 has higher priority when both ports are plugged
SW = H: Port2 has higher priority when both ports are plugged (default)
vender sugguest MUX use LLEQ PEQ=M and PI0=H !!
Programmable input equalization levels, Internal pull down at ~150Kohm,3.3V I/O
PEQ =
L: default,LEQ, compensate channel loss up to 11.5dB @HBR2
H: HEQ, compensate channel loss up to 14.5dB @HBR2
M:LLEQ, compensate channel loss up to 8.5dB @HBR2
PI0:Automatic EQ disable, Internal pull down ~150K ohm, 3.3V I/O
PI0 = L: Automatic EQ enable(default)
H: Automatic EQ disable
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DP SW2 PS8338
DP SW2 PS8338
DP SW2 PS8338
LA-E122P
LA-E122P
LA-E122P
21 59Wednesday, November 09, 2016
21 59Wednesday, November 09, 2016
21 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
544332211
0.1U_0201_10V6K
CV39
1
@
2
+3.3V_RUN
+3.3V_RUN
+5V_RUN
1
AP2330W-7_SC59-3
IN
UV2
GND2OUT
3
12
RV19@10K_0402_5%
1 2
RV10 470_0402_1%
1 2
RV11 470_0402_1%
1 2
RV12 470_0402_1%
1 2
RV13 470_0402_1%
1 2
RV14 470_0402_1%
1 2
RV15 470_0402_1%
1 2
RV16 470_0402_1%
1 2
RV17 470_0402_1%
1 2
RV18 10K_0402_5%
+VHDMI_VCC
0.1U_0201_10V6K
1
@
2
HDMI_HPD
HDMI_CTRL_DATA
HDMI_CTRL_CLK
HDMI_CEC
HDMI_L_CLKN
HDMI_L_CLKP
HDMI_L_TX_N0
HDMI_L_TX_P0
HDMI_L_TX_N1
HDMI_L_TX_P1
HDMI_L_TX_N2
HDMI_L_TX_P2
HDMI_OB
2
G
For 1.65G HDMI from CPU
10U_0603_10V6M
CV41
12
CV40
HDMI connector
ACON_HMRBL-A41L0F
19
HPD
18
+5V
17
DDC/CEC GND
16
SDA
15
SCL
14
Reserved
13
CEC
12
CK-
11
CK_Shield
10
CK+
9
D0-
8
D0_Shield
7
D0+
6
D1-
5
D1_Shield
4
D1+
3
D2-
2
D2_Shield
1
D2+
JHDMI1
LINK DC231604012 (temp) DONE
1
D
QV4
L2N7002W T1G_SC-70-3
S
3
GND
GND
GND
GND
CONN@
23
22
21
20
5
EMI@
LV31 8.2NH_LQP15MN8N2B02D
1 2
D D
C C
CPU_DP1_P0<6>
CPU_DP1_N0<6>
CPU_DP1_P1<6>
CPU_DP1_N1<6>
CPU_DP1_P2<6>
CPU_DP1_N2<6>
CPU_DP1_P3<6>
CPU_DP1_N3<6>
1 2
CV31 0.1U_0402_25V6
1 2
CV32 0.1U_0402_25V6
1 2
CV33 0.1U_0402_25V6
1 2
CV34 0.1U_0402_25V6
1 2
CV35 0.1U_0402_25V6
1 2
CV36 0.1U_0402_25V6
12
0.1U_0402_25V6
CV37
12
0.1U_0402_25V6
CV38
HDMI_TX_P2
HDMI_TX_N2
HDMI_TX_P1
HDMI_TX_N1
HDMI_TX_P0
HDMI_TX_N0
HDMI_CLKP
HDMI_CLKN
HCM1012GH900BP_4P
2
2
1
EMI@
LV32 8.2NH_LQP15MN8N2B02D
EMI@
LV33 8.2NH_LQP15MN8N2B02D
2
1
EMI@
LV34 8.2NH_LQP15MN8N2B02D
EMI@
LV35 8.2NH_LQP15MN8N2B02D
2
1
EMI@
LV36 8.2NH_LQP15MN8N2B02D
EMI@
LV37 12NH_LQG15HN12NJ02D_5%
2
1
EMI@
LV38 12NH_LQG15HN12NJ02D_5%
3
1
4
LV3
@EMI@
1 2
1 2
HCM1012GH900BP_4P
2
3
1
4
LV6
@EMI@
1 2
1 2
HCM1012GH900BP_4P
2
3
1
4
LV9
@EMI@
1 2
1 2
HCM1012GH900BP_4P
2
3
1
4
LV12
@EMI@
1 2
HDMI_L_TX_P2
3
EMI@
RV26
300_0402_5%
4
1 2
HDMI_L_TX_N2
RV29
300_0402_5%
1 2
RV32
300_0402_5%
1 2
RV35
300_0402_5%
1 2
HDMI_L_TX_P1
EMI@
HDMI_L_TX_N1
HDMI_L_TX_P0
EMI@
HDMI_L_TX_N0
HDMI_L_CLKP
EMI@
HDMI_L_CLKN
HDMI_TX_P2
HDMI_TX_N2
HDMI_TX_P1
HDMI_TX_N1
HDMI_TX_P0
HDMI_TX_N0
HDMI_CLKP
HDMI_CLKN
3
4
3
4
3
4
+3.3V_RUN
1M_0402_5%
RV20
CPU_DP1_HPD<6>
1 2
G
123
D
S
QV5
L2N7002W T1G_SC-70-3
HDMI_HPD
1 2
RV21 20K_0402_5%
B B
+3.3V_RUN
QV3A
2
DMN65D8LDW-7_SOT363-6
HDMI_CTRL_CLK
1
CPU_DP1_CTRL_CLK<6>
CPU_DP1_CTRL_DATA<6>
5
QV3B
DMN65D8LDW-7_SOT363-6
6
HDMI_CTRL_DATA
34
1 2
RV22 2.2K_0402_5%
1 2
RV23 2.2K_0402_5%
+VHDMI_VCC
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
HDMI CONN
HDMI CONN
HDMI CONN
LA-E122P
LA-E122P
LA-E122P
22 59Wednesday, November 09, 2016
22 59Wednesday, November 09, 2016
22 59Wednesday, November 09, 2016
1.0
1.0
1.0
5
4
3
2
1
+3.3V_RUN
+3.3V_VDD_PIC
D D
+3.3V_CPS
C C
RT308 4.7K_0402_5%
MUX1_SSEQ0
B B
1 2
@
LT11 BLM15PX600SN1D_2P
1 2
LT13 BLM15PX600SN1D_2P
AUX1_SNOOP_EN#
12
+3.3V_CPS
1K_0402_5%
@
RT137
1 2
20K_0402_5%
1K_0402_5%
@
12
12
RT138
RT302
+3.3V_CPS
12
10U_0402_6.3V6M
1
CT117
2
MUX1_DPEQ1
0.1U_0201_10V6K
0.1U_0201_10V6K
CT118
CT119
1
2
SW2_DP1_P0<21>
SW2_DP1_N0<21>
SW2_DP1_P1<21>
SW2_DP1_N1<21>
SW2_DP1_P2<21>
SW2_DP1_N2<21>
SW2_DP1_P3<21>
SW2_DP1_N3<21>
USB3_PTX_DRX_P6<10>
USB3_PTX_DRX_N6<10>
0.1U_0201_10V6K
1
2
TBTA_RX1N<26>
TBTA_RX1P<26>
TBTA_RX2N<26>
TBTA_RX2P<26>
+3.3V_CPS
1K_0402_5%
1 2
1K_0402_5%
12
CT120
1
2
@
RT247
RT248
0.1U_0201_10V6K
CT121
SW2_DP1_HPD<21,24>
for pin control , connect to PD GPIO
Check I2C or Pin control
20K_0402_5%
@
12
RT303
TUSB546: Pop RT246,Depop CT122
PS8740:Depop RT246,Pop CT122
1 2
@
RT246 0_0402_5%
1 2
1 2
CT103 0.1U_0402_25V6
CT104 0.1U_0402_25V6
1 2
1 2
CT105 0.1U_0402_25V6
CT106 0.1U_0402_25V6
1 2
1 2
CT107 0.1U_0402_25V6
CT108 0.1U_0402_25V6
1 2
1 2
CT109 0.1U_0402_25V6
CT110 0.1U_0402_25V6
1 2
1 2
CT113 0.1U_0402_25V6
CT114 0.1U_0402_25V6
@
12
CT1222.2U_0402_6.3V6M @
+3.3V_CPS_R1
SW2_DP1_P0_C
SW2_DP1_N0_C
SW2_DP1_P1_C
SW2_DP1_N1_C
SW2_DP1_P2_C
SW2_DP1_N2_C
SW2_DP1_P3_C
SW2_DP1_N3_C
USB3_PTX_C_DRX_P6
USB3_PTX_C_DRX_N6
AUX1_SNOOP_EN#
1 2
RT380 0_0402_5%
MUX1_USB_EQ0
+3.3V_CPS
1K_0402_5%
1 2
1K_0402_5%
12
UT9
1
VCC
6
VCC
20
VCC
28
VCC
9
DP0p
10
DP0n
12
DP1p
13
DP1n
15
DP2p
16
DP2n
18
DP3p
19
DP3n
31
RX1n
30
RX1p
39
RX2n
40
RX2p
8
SSTXp
7
SSTXn
29
SNK_CAD/DCI_DAT
32
HPDIN/DCI_CLK
41
PAD
TUSB546_QFN40_4X6
@
RT143
20K_0402_5%
12
RT144
EQ1
EQ0
I2C_EN
DPEQ1
DPEQ0/A1
SSEQ1
SSEQ0/A0
FLIP/SCL
CTL0/SDA
CTL1
TX1n
TX1p
TX2p
TX2n
SSRXp
SSRXn
SBU1
SBU2
AUXp
AUXn
@
RT304
MUX1_USB_EQ0
38
MUX1_I2C_EN
17
MUX1_DPEQ1
2
MUX1_DPEQ0
14
MUX1_SSEQ1
3
MUX1_SSEQ0
11
MUX1_FLIP_SEL
21
MUX1_USB_SEL
22
MUX1_DP_SEL
23
34
33
37
36
USB3_PRX_C_DTX_P6
5
USB3_PRX_C_DTX_N6
4
TUSB546A_SBU1_R
27
TUSB546A_SBU2_R
26
SW2_DP1_AUXP_C
24
SW2_DP1_AUXN_C
25
MUX1_FLIP_SEL <24>
MUX1_USB_SEL <24>
MUX1_DP_SEL <24>
TBTA_TX1N <26>
TBTA_TX1P <26>
TBTA_TX2P <26>
TBTA_TX2N <26>
12
1 2
1 2
12
12
12
CT111 0.1U_0402_25V6
CT112 0.1U_0402_25V6
RT132 0_0402_5%@
RT133 0_0402_5%@
CT115 0.1U_0402_25V6@
CT116 0.1U_0402_25V6@
MUX1_USB_EQ1
35
For NON-AR port1
+3.3V_CPS
1K_0402_5%
@
RT145
MUX1_I2C_EN
I2C Programming or Pin Strap Programming Select,Internally
30k pull-up and 60k pull-down
I2C_EN =
0: Tie 1k to GND,Pin Strap(I2C disable)
R:Tie 20k to GND,TI Test Mode(I2C enabled)
F: Float,TI Test Mode(I2C enabled)
USB3_PRX_DTX_P6 <10>
USB3_PRX_DTX_N6 <10>
TBTA_SBU1 <24,26>
TBTA_SBU2 <24,26>
SW2_DP1_AUXP <21,24>
SW2_DP1_AUXN <21,24>
1:Tie 1k to VCC,I2C enabled
SW2_DP1_AUXN_C
SW2_DP1_AUXP_C
1 2
1K_0402_5%
12
1 2
1 2
20K_0402_5%
@
12
RT300
RT301
RT131100K_0402_5%
RT130100K_0402_5%
+3.3V_CPS
Ser the USB receiver equalizer gain for upstream facing
SSTXP/N,Internally 30k pull-up and 60k pull-down
SSEQ =
0: Tie 1k to GND
R:Tie 20k to GND
F: Float
1:Tie 1k to VCC
+3.3V_CPS
1K_0402_5%
@
RT135
MUX1_SSEQ1
A A
1 2
20K_0402_5%
1K_0402_5%
@
12
12
RT136
RT305
5
Select the DisplayPort receiver equalizer gain ,Internally
30k pull-up and 60k pull-down
DPEQ =
0: Tie 1k to GND
R:Tie 20k to GND
F: Float
1:Tie 1k to VCC
1K_0402_5%
@
RT139
1 2
20K_0402_5%
@
1K_0402_5%
12
12
RT306
RT140
4
Ser the USB receiver equalizer gain for downstream facing
RX1 and RX2 when USB utilized,Internally 30k pull-up and
60k pull-down
USB_EQ =
0: Tie 1k to GND
R:Tie 20k to GND
F: Float
1:Tie 1k to VCC
+3.3V_CPS+3.3V_CPS
1K_0402_5%
@
RT141
MUX1_USB_EQ1MUX1_DPEQ0
1 2
20K_0402_5%
1K_0402_5%
@
12
12
RT142
RT307
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Compal Electronics, Inc.
DP/USB3 Repeater SW TUSB546
DP/USB3 Repeater SW TUSB546
DP/USB3 Repeater SW TUSB546
LA-E122P
LA-E122P
LA-E122P
23 59Wednesday, November 09, 2016
23 59Wednesday, November 09, 2016
23 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
+3.3V_TBTA_FLASH+3.3V_TBTA_FLASH
12
12
12
CT70
.1U_0402_16V7K
TBTA_ROM_HOLD#_PD
TBTA_ROM_CLK_PD_R
TBTA_ROM_DI_PD_R
TBTA_ROM_CLK_PD_R
TBTA_ROM_DI_PD_R
TBTA_ROM_DO_PD_R
TBTA_ROM_CS#_PD_R
JDB1
7
GND
8
GND
ACES_50506-00641-P01
CONN@
DIV = R2/(R1+R2)
0.70
12
8
VCC
7
HOLD#(IO3)
6
CLK
5
DI(IO0)
W25Q80DVSSIG_SO8
@
1 2
RT54 0_0402_5%
@
1 2
RT55 0_0402_5%
@
1 2
RT56 0_0402_5%
@
1 2
RT57 0_0402_5%
+3.3V_TBTA_FLASH
1
1
TBTA_ROM_CLK_PD_R
2
2
TBTA_ROM_DI_PD_R
3
3
TBTA_ROM_DO_PD_R
4
4
TBTA_ROM_CS#_PD_R
5
5
6
6
Configuration
DIV_maxDIV_min
0.080.00
0.180.10
0.280.20
0.380.30
0.480.40
0.580.50
0.680.60
1.00 7
UT6
TBTA_ROM_CS#_PD_R
1
CS#
TBTA_ROM_DO_PD_R
2
DO(IO1)
TBTA_ROM_WP#_PD
3
WP#(IO2)
4
GND
TBTA_ROM_CLK_PD
TBTA_ROM_DI_PD
TBTA_ROM_DO_PD
TBTA_ROM_CS#_PD
DescriptionFactory Device
UFP only
5V @0.9A Sink capability w ith "Ask for Max/" for
anything from 0.9 -3.0A
0
TBT Alternate Modes not supported
DisplayPort Alternate Modes not sup ported
TI VID supported
UFP only
5V @0.9A Sink capability w ith "Ask for Max/" for
anything from 0.9 -3.0A
1
TBT Alternate Modes not supported
DisplayPort Alternate Modes -Sink , C and D pin configuration
TI VID supported
UFP only
5V @3.0A Source capability
2
TBT Alternate Modes not supported
DisplayPort Alternate Modes not sup ported
TI VID supported
UFP only
5V @3.0A Source capability
3
TBT Alternate Modes not supported
DisplayPort Alternate Modes -Sink , C and D pin configuration
TI VID supported
DRP
5V @0.9-3.0A Sink capability
5V @3.0A Source capability
TBT Alternate Modes not supported
4
DisplayPort Alternate Modes not sup ported
TI VID supported
Accepts data and power role s waps, but does not
initiate.
DRP
5V @0.9-3.0A Sink capability
5V @3.0A Source capability
TBT Alternate Modes not supported
5
DisplayPort Alternate Modes - Source, C, D, and E
pin configurations.
TI VID supported
Accepts power role sw aps but will not initi ate.
Accepts data role swap t o UFP and can initiate.
DRP
5V @0.9-3.0A Sink capability
5V @3.0A Source capability
TBT Alternate Modes not supported
6
DisplayPort Alternate Modes - Source, C, D, and E
pin configurations.
TI VID supported
Accepts power role sw aps but will not initi ate.
Accepts data role swap t o DFP and can initiate.
Infinite boot retry from Flash to Host I/F cycles.
RT50
3.3K_0402_5%
D D
C C
B B
A A
12
RT53
RT51
RT52
3.3K_0402_5%
3.3K_0402_5%
3.3K_0402_5%
UPD1_SMBCLK<32>
+3.3V_TBTA_FLASH
+3.3V_TBTA_FLASH
4
UPD1_SMBDAT<32>
UPD1_ALERT#<32>
10K_0402_1%
RT76
1 2
PD1_GPIO8
12
RT377
43K_0402_1%
RT81
RT82 1M_0402_5%@
TI ref ckt: 100k
Intel ref ckt: 1M
MUX1_DP_SEL/MUX1_USB_SEL c ontrol by:
GPIO: Pop RT89,RT90;Depop RT375,RT376
I2C:Depop RT89,RT90;pop RT375,RT376
MUX1_FLIP_SEL<23,24>
MUX1_USB_SEL<23,24>
Check AUX conne ct to PD or PS 8743B
TBTA_AUXN_C
12
RT95
RT96
12
100K_0402_5%
TBTA_AUXP_C
100K_0402_5%
+3.3V_VDD_PIC
126
QT1A
@
DMN66D0LDW-7_SOT363-6
@
1 2
RT58 0_0402_5%
DMN66D0LDW-7_SOT363-6
@
RT59 0_0402_5%
@
1 2
RT60 0_0402_5%
TI is 3x1uf
UART_MOSI
12
100K_0402_5%
UART_MISO
12
@
@
UPD1_SMBCLK_Q
5
UPD1_SMBDAT_Q
34
QT1B
@
1 2
UPD1_SMBUS_ALERT#
1
1
CT72
CT71
2
2
2.2U_0402_16V6K
2.2U_0402_16V6K
MUX1_FLIP_SEL<23,24>
EN_PD_HV_1<51>
AC1_DISC#<50,51>
SW2_DP1_HPD<21,23>
USB2_ID<10>
MUX1_DP_SEL<23>
MUX1_USB_SEL<23,24>
1 2
RT375 0_0402_5%
1 2
RT376 0_0402_5%
+VCC1V8D_TBTA_LDO
RT97 0_0402_5%@
3
+5V_ALW
@
PJP8
1 2
PAD-OPEN 1x3m
+TBTA_LDO_BMC
+VCC1V8D_TBTA_LDO
+VCC1V8A_TBTA_LDO
1
2
+3.3V_VDD_PIC
CT73
2.2U_0402_16V6K
+3.3V_TBTA_FLASH
+3.3V_ALW
MUX1_FLIP_SEL
EN_PD_HV_1
UART_MOSI
UART_MISO
T219@ PAD~D
T220@ PAD~D
UPD1_SMBCLK_Q TBTA_DEBUG1
UPD1_SMBDAT_Q
SW2_DP1_AUXP<21,23>
SW2_DP1_AUXN<21,23>
1 2
PJP7
@
1 2
PAD-OPEN1x1m
+3.3V_TBTA_FLASH
RT66 3.3K_0402_5%
@
RT67 3.3K_0402_5%
@
RT68 10K_0402_5%
@
@
@
@
@
RT74 0_0402_5%
@
RT75 0_0402_5%
@
RT339 0_0402_5%
@
RT86 1M_0402_5%
RT87 0_0402_5%@
RT88 0_0402_5%@
@
@
@
@
RT378 10K_0402_5%
RT379 10K_0402_5%
12
12
12
1 2
RT69 0_0402_5%
1 2
RT70 0_0402_5%
12
RT71 1M_0402_5%
1 2
RT72 0_0402_5%
1 2
RT73 0_0402_5%
12
12
12
USB20_P9<10>
USB20_N9<10>
@
RT83 0_0402_5%
RT84 0_0402_5%
@
RT85 0_0402_5%
@
12
1 2
1 2
1 2
1 2
RT89 0_0402_5%
RT90 0_0402_5%
1 2
1 2
RT92 0_0402_5%
RT93 0_0402_5%
1 2
CT80 0.1U_0201_10V6K
1 2
CT81 0.1U_0201_10V6K
+3.3V_TBTA_FLASH
@
RT98
0_0402_5%
1 2
12
@
RT99
0_0402_5%
1
2
UPD1_SMBDAT_Q
UPD1_SMBCLK_Q
UPD1_SMBUS_ALERT#
MUX1_FLIP_SEL_R
EN_PD_HV_1_R
PD1_GPIO2
AC1_DISC#_R
SW2_DP1_HPD_R
OTG_ID
PD1_GPIO6
PD1_GPIO7
TBTA_ROM_CLK_PD
TBTA_ROM_DI_PD
TBTA_ROM_DO_PD
TBTA_ROM_CS#_PD
1 2
12
CT74
1U_0402_16V6K
12
12
12
12
RT100
TI is 1x47uf+1x0.1uf
1 2
@
RT63 0_0402_5%
PD1_GPIO8
TBTA_MRESET
TBTA_LSTX_R
TBTA_LSRX_R
TBTA_DEBUG3
TBTA_DEBUG4
TBTA_DEBUG2
TBTA_AUXP_C
TBTA_AUXN_C
TBTA_ROSC
15K_0402_1%
1
CT75
2
22U_0805_25V6M
UT5
F1
I2C_ADDR
D1
I2C_SDA1
D2
I2C_SCL1
C1
I2C_IRQ1_N
A5
I2C_SDA2
B5
I2C_SCL2
B6
I2C_IRQ2_N
B2
GPIO0
C2
GPIO1
D10
GPIO2
G11
GPIO3
C10
GPIO4
E10
GPIO5
G10
GPIO6
D7
GPIO7
H6
GPIO8
A3
SPI_CLK
B4
SPI_MOSI
A4
SPI_MISO
B3
SPI_SS_N
L5
USB_RP_P
K5
USB_RP_N
E2
UART_TX
F2
UART_RX
F4
SWD_DATA
G4
SWD_CLK
E11
MRESET
L4
TBT_LSTX/R2P
K4
TBT_LSRX/P2R
L3
DIG_AUD_P/DEBUG3
K3
DIG_AUD_N/DEBUG4
L2
DEBUG1
K2
DEBUG2
J1
AUX_P
J2
AUX_N
F10
BUSPOWER_N
G2
R_OSC
1
1
CT77
CT76
2
2
22U_0805_25V6M
+3.3V_VDD_PIC_PDA
H1
VIN_3V3
2
1
For NON-AR port1
+TBTA_Vbus_1
1
CT78
2
22U_0805_25V6M
22U_0805_25V6M
1 2
RT64 0_0402_5%
@
1 2
RT65 0_0402_5%
@
+5V_ALW_PDA
A11
B11
B1
VDDIO
H10
K1
A2
LDO_1V8A
LDO_1V8D
GND
HRESET
GNDE5GND
E7
A1
E6
D6
12
RT101
100K_0402_5%
E1
GND
F5
LDO_BMC
GND
GND
G5
PP_CABLE
GND
GND
GNDH4GND
B8
D8
H5
0.22U_0402_16V7K
C11
D11
GNDA6GNDA7GNDA8GND
PP_5V0
PP_5V0
PP_5V0
PP_5V0
GND
GNDF6GNDF7GND
GND
GNDG7GND
SSH7GNDL1GND
F8
E8
H8
G6
G8
1
CT87
2
B7
GND
L11
B10
A10
SENSEP
SENSEN
DEBUG_CTL1
DEBUG_CTL2
TPS65982_BGA96
12
RT103
@
0_0402_5%
HV_GATE1_A
HV_GATE2_A
A9
+TBTA_Vbus_1
HV_GATE1B9HV_GATE2
VOUT_3V3
LDO_3V3
C_USB_TP
C_USB_TN
C_USB_BP
C_USB_BN
C_CC1
C_CC2
RPD_G1
RPD_G2
C_SBU1
C_SBU2
RESET_N
VBUS
VBUS
VBUS
VBUS
TI has 1x1uf
H11
12
J10
J11
K11
H2
G1
K6
L6
K7
L7
TI has 2x220pf
L9
L10
WHEN CONNECT BU SPOWERZ TO GND ,
CONNECT ALSO RP D_Gn to C_CCn
K9
@
K10
RT104 0_0402_5%
@
RT105 0_0402_5%
TBTA_DBG_CTL1
E4
TBTA_DBG_CTL2
D5
TBTA_SBU1_R
K8
TBTA_SBU2_R
L8
TBTA_RESET_N_EC_R
F11
+3.3V_PDA_VOUT
+3.3V_TBTA_FLASH
1
CT82
CT83
2
1U_0603_25V6K
1U_0402_16V6K
TBTA_TOP_P <26>
TBTA_TOP_N <26>
TBTA_BOT_P <26>
TBTA_BOT_N <26>
1 2
1 2
RT106 10K_0402_5%
RT107 10K_0402_5%
1 2
@
RT108 0_0402_5%
1 2
@
RT109 0_0402_5%
1
2
1 2
1 2
CT84
10U_0603_6.3V6M
TBTA_CC1 <26 >
12
+3.3V_TBTA_FLASH
RT1100_0402_5%
@
TBTA_CC2 <26 >
1
2
TBTA_SBU1 <23,26 >
TBTA_SBU2 <23,26 >
1
CT85
CT86
2
820PF_0402_50V7K
820PF_0402_50V7K
Need Link TPS65982D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
[Type C]PD Controller TI
[Type C]PD Controller TI
[Type C]PD Controller TI
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-E122P
LA-E122P
LA-E122P
1
24 59Wednesday, November 09, 2016
24 59Wednesday, November 09, 2016
24 59Wednesday, November 09, 2016
1.0
1.0
1.0
+5V_ALW
5
4
3
2
1
DT1
+5V_TBT_VBUS
D D
C C
1N4148WS-7-F_SOD323-2
1N4148WS-7-F_SOD323-2
DT3
1 2
1N4148WS-7-F_SOD323-2
1U_0402_10V6K
1
CT93
2
12
DT2
12
+5V_TBTA_VBUS_D
+5V_PD_VDD
100K_0402_5%
12
3
VOUT
AP2204R-5.0TRG1_SOT89-3
@
0.1U_0201_10V6K
RT393
1
2
UT8
1
VCC
2
GND
1
CT88
2
1U_0402_10V6K
CT89
RT111 100K_0402_5%
+TBTA_VBUS_1
1U_0603_50V6K
1
2
1 2
CT94
UT7
VCC1VOUT
2
GND
EN3ADJ/NC
AP2112K-3.3TRG1_SOT23-5
1
CT90
1U_0402_10V6K
2
5
4
2.2U_0603_25V6K
0.1U_0402_25V6K
12
12
@
CT91
+3.3V_VDD_PIC
CT92
place near UT7
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
[Type C]PD Power
[Type C]PD Power
[Type C]PD Power
LA-E122P
LA-E122P
LA-E122P
25 59Wednesday, November 09, 2016
25 59Wednesday, November 09, 2016
25 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
4
3
2
1
For NON AR Config
D D
RF Request
12P_0402_50V8J
RF@
1
CT189
2
2
3
ESD@
L30ESD24VC3-2_SOT23-3
1
DT4
TBTA_RX1P
TBTA_RX1N
TBTA_SBU2
TBTA_BOT_N_R
TBTA_BOT_P_R
TBTA_CC2TBTA_SBU1
TBTA_TX2N_C
TBTA_TX2P_C
Check ,FROM PWR PAGE
TBTA_RX1P <23>
TBTA_RX1N <23>
1 2
CT100 0.47U_0201_25V
TBTA_SBU2 <23,24>
1 2
@EMI@
1 2
RT122 0_0402_5%
@EMI@
RT123 0_0402_5%
TBTA_CC2 <24>TBTA_SBU1<23,24>
1 2
CT102 0.47U_0201_25V
TBTA_BOT_N <24>
12
CT980.22U_0201_6.3V6K
TBTA_TX2N <23>
12
CT970.22U_0201_6.3V6K
TBTA_TX2P <23>
+TBTA_VBUS+TBTA_VBUS +TBTA_VBUS +TBTA_VBUS
JUSBC1
A1
TBTA_TX1P<23>
TBTA_TX1N<23>
TBTA_TOP_P<24>
C C
B B
A A
TBTA_TOP_N<24> TBTA_BOT_P <24>
TBTA_TX1P_C
TBTA_TX1N_C
TBTA_SBU1 TBTA_CC2
TBTA_RX2N
TBTA_RX2P
TBTA_TOP_P_R
TBTA_TOP_N_R
ESD@
1 2
ESD8011MUT5G_X3DFN2-2
ESD@
1 2
ESD8011MUT5G_X3DFN2-2
ESD@
1 2
ESD8011MUT5G_X3DFN2-2
ESD@
1 2
ESD8011MUT5G_X3DFN2-2
ESD@
1 2
ESD8011MUT5G_X3DFN2-2
ESD@
1 2
ESD8011MUT5G_X3DFN2-2
ESD@
1 2
ESD8011MUT5G_X3DFN2-2
ESD@
1 2
ESD8011MUT5G_X3DFN2-2
1 2
1 2
CT95 0.22U_0201_6.3V6K
CT96 0.22U_0201_6.3V6K
1 2
@EMI@
1 2
RT120 0_0402_5%
@EMI@
RT121 0_0402_5%
DT5
DT6
DT7
DT8
DT9
DT10
DT11
DT12
TBTA_CC1<24>
TBTA_RX2N<23>
TBTA_RX2P<23>
TBTA_TX1P_C
TBTA_TX1N_C
12
CT990.47U_0201_25V
TBTA_CC1
TBTA_TOP_P_R
TBTA_TOP_N_R
12
CT1010.47U_0201_25V
Premium 12/14/15 UMA:Check SBU1/SBU2 connect to PD or PS8740B
Link DC23300MEBL Done
TBTA_RX1P
TBTA_RX1N
TBTA_SBU2TBTA_CC1
TBTA_TX2P_C
TBTA_TX2N_C
TBTA_BOT_P_R
TBTA_BOT_N_R
GND_A1
A2
SSTXp1
A3
SSTXn1
A4
VBUS_A4
A5
CC1
A6
Dp1
A7
Dn1
A8
SBU1
A9
VBUS_A9
A10
SSRXn2
A11
SSRXp2
A12
GND_A12
1
GND1
3
GND3
JAE_DX07B024XJ1R1300~D
CONN@
DT13
ESD@
1 2
ESD8011MUT5G_X3DFN2-2
DT14
ESD@
1 2
ESD8011MUT5G_X3DFN2-2
DT15
ESD@
1 2
ESD8011MUT5G_X3DFN2-2
DT16
ESD@
1 2
ESD8011MUT5G_X3DFN2-2
DT17
ESD@
1 2
ESD8011MUT5G_X3DFN2-2
DT18
ESD@
1 2
ESD8011MUT5G_X3DFN2-2
DT19
ESD@
1 2
ESD8011MUT5G_X3DFN2-2
DT20
ESD@
1 2
ESD8011MUT5G_X3DFN2-2
TOP
B12
GND_B12
B11
SSRXp1
B10
SSRXn1
B9
VBUS_B9
B8
SBU2
B7
Dn2
B6
Dp2
B5
CC2
B4
Bottom
VBUS_B4
B3
SSTXn2
B2
SSTXp2
B1
GND_B1
2
GND2
4
GND4
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
USB 3.0 CONN TYPE C
USB 3.0 CONN TYPE C
USB 3.0 CONN TYPE C
LA-E122P
LA-E122P
LA-E122P
1
26 59Wednesday, November 09, 2016
26 59Wednesday, November 09, 2016
26 59Wednesday, November 09, 2016
1.0
1.0
1.0
5
LINK 50398-04041-001 DONE
JEDP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D D
+BL_PWR_SRC
12
C C
Close to JEDP1.17~19
BIA_PWM
4.7K_0402_5%
12
RV1
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
41
36
G1
42
37
G2
43
38
G3
44
39
G4
45
40
G5
ACES_50398-04041-001
CONN@
0.1U_0603_50V7K
@
CV11
Close to JEDP1.30~31 Close to JEDP1.11 Close to JEDP1.1 Close to JEDP1.10
DV1
1
BAT54CW_SOT323-3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
+LCDVDD
3
2
+3.3V_TSP
USB20_N5_R
USB20_P5_R
LV1
EMI@
DISP_ON
TOUCH_SCREEN_DET#
EDP_AUXN_C
EDP_AUXP_C
EDP_TXP0_C
EDP_TXN0_C
EDP_TXP1_C
EDP_TXN1_C
0.1U_0201_10V6K
1
@
CV12
2
EDP_BIA_PWM
BIA_PWM_EC
TOUCH_SCREEN_PD# <12>
+3.3V_RUN
+3.3V_CAM
CAM_MIC_CBL_DET# <12>
Pin15: LOOP_BACK
+BL_PWR_SRC
1 2
+LCDVDD
BIA_PWM
BLM15PX221SN1D_2P
EDP_HPD <6>
LCD_TST <32>
TOUCH_SCREEN_DET# <12>
12
CV1 0.1U_0402_25V6
12
CV2 0.1U_0402_25V6
12
CV3 0.1U_0402_25V6
12
CV4 0.1U_0402_25V6
12
CV5 0.1U_0402_25V6
12
CV6 0.1U_0402_25V6
LCD_CBL_DET# <9>
+3.3V_CAM +3.3V_TSP
0.1U_0201_10V6K
1
@
CZ1
2
EDP_BIA_PWM <6>
BIA_PWM_EC <32>
0.1U_0201_10V6K
1
@
2
RF Request
+LCDVDD +3.3V_CAM +BL_PWR_SRC
12P_0402_50V8J
82P_0402_50V8J
12P_0402_50V8J
82P_0402_50V8J
RF@
RF@
B B
RF@
1
1
1
CV22
CV20
CV21
2
2
2
12P_0402_50V8J
82P_0402_50V8J
RF@
RF@
1
CV23
2
RF@
1
1
CV24
CV25
2
2
100P_0402_50V8J
12
EMI Request
EDP_HPD
RV7 100K_0402_5%@
EDP_TXP0 <6>
EDP_TXN0 <6>
EDP_TXP1 <6>
EDP_TXN1 <6>
CZ2
DISP_ON
4.7K_0402_5%
12
4
100P_0402_50V8J
12
CA5@EMI@
CA6@EMI@
1 2
EDP_AUXN <6>
EDP_AUXP <6>
+3.3V_RUN
RV2
0.1U_0201_10V6K
1
@
CA7
2
1
BAT54CW_SOT323-3
+LCDVDD
Reserve for EA
DV2
DMIC0 <31>
DMIC_CLK0 <31>
3
2
223
1
3
1
TOUCH_PANEL_INTR#:
USB20_N8_R
USB20_P8_R
AZC199-02SPR7G_SOT23-3
@ESD@
DV4
Close lid >> TP_EN = 0 >> Disable touch events
Open lid >> TP_EN = 1 >> Enable touch events
ESD depop location
TOUCH_SCREEN_DET#
Due to SB12/14 Mic. receive path is different
between Touch and Non-Touch Panel, so add
TOUCH_SCREEN_DET# pin for different verb
table
USB20_N5_R
USB20_P5_R
PANEL_BKLEN <6>
PANEL_BKEN_EC <32>
3
EXC24CQ900U_4P
1 2
LV27
+3.3V_RUN
10K_0402_5%
RV8
1 2
@ESD@
ESD8011MUT5G_X3DFN2-2
12
DV7
ESD depop location
12
EMI@
2
34
@ESD@
ESD8011MUT5G_X3DFN2-2
DV8
RF Request
+3.3V_TSP
RF@
12P_0402_50V8J
1
CV18
2
USB20_N8 <10>
USB20_P8 <10>
RF@
82P_0402_50V8J
1
CV19
2
JIR1
CONN@
1
2
3
4
7
5
GND
8
6
GND
E-T_4251K-F06N-40L
1
2
3
4
5
6
For Touchscreen
3.3V_TS_EN<9>
2
G
For 2LANE EDP &3.3V_TSP
For Breckenridge&Steamboat 12
+PWR_SRC
IR_CAM_DET# <12>
For Breckenridge 12
10K_0402_5%
RV6
1 2
L2N7002WT1G_SC-70-3
13
D
QV7
S
RF Request
+PWR_SRC
QV8
LP2301A LT1G_SOT23-3
123
D
S
G
RF@
100P_0402_50V8J
1
CZ3
2
+3.3V_RUN+3.3V_RUN +3.3V_TSP
1
LCDVDD POWER
WebCAM
+3.3V_CAM +3.3V_RUN
3.3V_CAM_EN#<11>
A A
USB20_P5<10>
5
EXC24CQ900U_4P
1 2
LZ1
LP2301A LT1G_SOT23-3
EMI@
QZ1
123
D
34
S
G
USB20_P5_R
USB20_N5_R
Backlight POWER
+PWR_SRC
1000P_0402_50V7K
270K_0402_5%
CV13
RV4
1 2
1 2
BL_PWR_SRC_ON
0.01U_0402_50V7K
1
2
CV14
4
1 2
RV5 4 7K_0402_5%
EN_INVPWR<32>USB20_N5<10>
S
4 5
QV1
D
6
2
1
G
AO6405_TSOP6
3
QV2
L2N7002WT1G_SC-70-3
123
D
G
+BL_PWR_SRC
12
S
0.1U_0603_50V7K
CV15
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+LCDVDD +EDP_VDD
CV16
@
12
10U_0603_10V6M
LCD_VCC_TEST_EN<32>
ENVDD_PCH<6,32>
PJP13
@
1 2
PAD-OPEN1 x1m
BAT54CW_SOT323-3
2
+3.3V_ALW
UV24
1
VOUT
2
GND
3
/OC
DV3
2
3
G524B1T11U_SOT23-5
1
EN_LCDPWR
5
VIN
4
EN
0.01UF_0402_25V7K
@
CV17
12
100K_0402_5%
RV3
1 2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
eDP CONN & Touch screen
eDP CONN & Touch screen
eDP CONN & Touch screen
LA-E122P
LA-E122P
LA-E122P
1
27 59Wednesday, November 09, 2016
27 59Wednesday, November 09, 2016
27 59Wednesday, November 09, 2016
1.0
1.0
1.0
5
+3.3V_LAN
RL1@ 10K_0402_5%
RL2@ 10K_0402_5%
RL4 4.7K_0402_5%@
D D
PM_LANPHY_ENABLE<11>
+0.9V_LAN
22U_0603_6.3V6M
1
12
CL12
2
Note:
+1.0V_LAN will work at 0.95V to 1.15V
C C
B B
+3.3V_LAN
12
+3.3V_LAN
12
For WLAN can't recognize during enable
Unobtrusive mode(BITS152312)
A A
TP_LAN_JTAG_TMS
12
TP_LAN_JTAG_TCK
12
CLKREQ_PCIE#4
12
1 2
@
RL7 0_0402_5%
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
CL9
1
2
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
LOM_ACTLED_YEL#
RL29
1M_0402_5%
LOM_SPD100LED_ORG#
RL30
1M_0402_5%
LOM_SPD10LED_GRN#
0.1U_0201_10V6K
CL11
CL10
CL8
1
1
2
2
When LAN & W LAN are exist at the same time, W LAN will disable
+3.3V_LAN
5
1
P
B
2
A
G
TC7SH08FU_SSOP5~D
3
QL1A
DMN65D8LDW-7_SOT363-6
126
SYS_LED_MASK#
QL1B
DMN65D8LDW-7_SOT363-6
LED_100_ORG#
34
5
SYS_LED_MASK#
QL2A
DMN65D8LDW-7_SOT363-6
126
SYS_LED_MASK#
QL2B
DMN65D8LDW-7_SOT363-6
34
5
+3.3V_LAN
XTALO_R
27P_0402_50V8J
12
CL13
@
CL15
1 2
0.1U_0201_10V6K
4
O
UL2
LAN_ACTLED_YEL#
LED_10_GRN#
CLKREQ_PCIE#4<11>
PCIE_PRX_DTX_P9<10>
PCIE_PRX_DTX_N9<10>
PCIE_PTX_DRX_P9<10>
PCIE_PTX_DRX_N9<10>
10K_0402_5%
RL5 @
1 2
12
SYS_LED_MASK# <32,39>
SMBus Device Address 0xC8
10K_0402_5%
RL9@
1 2
@
RL34 0_0402_5%
YL1
3
IN
OUT
4
GND
GND
25MHZ_18PF_7V25000034
LOM_CABLE_DETECT# <32>
PLTRST_LAN#<11>
CLK_PCIE_P4<11>
CLK_PCIE_N4<11>
SML0_SMBCLK<8>
SML0_SMBDATA<8>
LAN_WAKE#<11,32>
T88@ PAD~D
T89@ PAD~D
12
1
2
12
CLKREQ_PCIE#4
PCIE_PRX_C_DTX_P9
1 2
CL1 0.1U_0402_25V6
PCIE_PRX_C_DTX_N9
1 2
CL2 0.1U_0402_25V6
PCIE_PTX_C_DRX_P9
1 2
CL5 0.1U_0402_25V6
PCIE_PTX_C_DRX_N9
1 2
CL6 0.1U_0402_25V6
RL11
1M_0402_5%
27P_0402_50V8J
CL14
0.1U_0201_10V6K
0.1U_0201_10V6K
12
12
CL16
CL17
0.1U_0201_10V6K
0.1U_0201_10V6K
12
CL20
LAN_DISABLE#_R
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
LAN_TEST_EN
3.01K_0402_1%
1K_0402_5%
12
12
RL13
RL12
LAN_MDIN3_L
LAN_MDIP3_L
LAN_MDIN1_L
LAN_MDIP1_L
LAN_MDIN2_L
LAN_MDIP2_L
LAN_MDIN0_L
12
CL21
LAN_MDIP0_L
4
UL1
48
CLK_REQ_N
36
PE_RST_N
44
PE_CLKP
45
PE_CLKN
38
PETp
39
PETn
41
PERp
42
PERn
28
SMB_CLK
31
SMB_DATA
2
LANWAKE_N
3
LAN_DISABLE_N
26
LED0
27
LED1
25
LED2
32
JTAG_TDI
34
JTAG_TDO
33
JTAG_TMS
35
JTAG_TCK
9
XTALO
XTAL_OUT
10
XTALI
XTAL_IN
30
TEST_EN
12
RBIAS
WGI219LM-QREF- A0_QFN48_6X6~D
change to SA000081G1L ,(S IC WGI219LM SLKJ2 A0 QFN 48P PHY A31 ! )
TL1
1
TD1+
2
TD1-
3
TDCT1
4
TDCT2
5
TD2+
6
TD2-
7
TD3+
8
TD3-
9
TDCT3
10
TDCT4
11
TD4+
12
TD4-
MHPC_NS692417
GND
GND
CHASSIS
CHASSIS
PCIE
SMBUS
JTAG LED
MDI_PLUS0
MDI_MINUS0
MDI_PLUS1
MDI_MINUS1
MDI_PLUS2
MDI
MDI_MINUS2
MDI_PLUS3
MDI_MINUS3
SVR_EN_N
RSVD_VCC3P3_1
VDD3P3_IN
VDD3P3_4
VDD3P3_15
VDD3P3_19
VDD3P3_29
VDD0P9_47
VDD0P9_46
VDD0P9_37
VDD0P9_43
VDD0P9_11
VDD0P9_40
VDD0P9_22
VDD0P9_16
VDD0P9_8
CTRL0P9
VSS_EPAD
1:1
EMI@
CL22 10P_1808_3KV8J
0601:EMI ask to change 150pF
LAN_MDIP0
13
LAN_MDIN0
14
LAN_MDIP1
17
LAN_MDIN1
18
LAN_MDIP2
20
LAN_MDIN2
21
LAN_MDIP3
23
LAN_MDIN3
24
VCT_LAN_R1
6
+RSVD_VCC3P3_1
1
5
+3.3V_LAN_OUT
4
15
19
29
+0.9V_LAN
47
46
37
43
11
40
22
16
8
+REGCTL_PNP10RES_BIAS
7
49
1 2
Idc_min=500mA
DCR=100mohm
Place CL3, CL4 and LL1 close to UL1
1:1
1:1
1:1
1 2
24
TX1+
23
TX1-
22
TXCT1
21
TXCT2
20
TX2+
19
TX2-
18
TX3+
17
TX3-
16
TXCT3
15
TXCT4
14
TX4+
13
TX4-
use 40mil trace if necessary
3
Layout Notice : Place bead as
close UL4 as possible
1 2
RL71
RL72
RL73
RL74
RL75
RL76
RL77
RL78
RJ45_MDIN3
RJ45_MDIP3
RJ45_MDIN1
RJ45_MDIP1
RJ45_MDIN2
RJ45_MDIP2
RJ45_MDIN0
RJ45_MDIP0
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
0.1U_0201_10V6K
12
Z2806
Z2808
+GND_CHASSIS
2.2_0603_5%
2.2_0603_5%
2.2_0603_5%
2.2_0603_5%
2.2_0603_5%
2.2_0603_5%
2.2_0603_5%
2.2_0603_5%
@
RL30_0402_5%
22U_0805_6.3V6M
1
CL7
CL28
2
+0.9V_LAN
LL14.7UH_BRC2012T4R7MD_20%
0.1U_0201_10V6K
1
2
Z2805
Z2807
1 2
1 2
Place CL28 close to UL1.5
10U_0603_10V6M
@
CL3
CL4
12
12
12
12
RL17 75_0402_1%
RL16 75_0402_1%
RL15 75_0402_1%
RL64.7K_0402_5%
LAN_MDIP0_L
LAN_MDIN0_L
LAN_MDIP1_L
LAN_MDIN1_L
LAN_MDIP2_L
LAN_MDIN2_L
LAN_MDIP3_L
LAN_MDIN3_L
@
RL80_0603_5%
+3.3V_LAN
+3.3V_LAN
2
RF Request
+3.3V_LAN_OUT
@RF@
@RF@
12P_0402_50V8J
82P_0402_50V8J
1
1
CL29
CL30
2
2
470P_0402_50V7K
1
12
CL18
2
LAN_ACTLED_YEL# LAN_ACTLED_YEL_R#
LED_10_GRN# LED_10_GRN_R#
LED_100_ORG# LED_100_ORG_R#
1 2
RL14 150_0402_5%
RJ45_MDIN3
RJ45_MDIP3
RJ45_MDIN1
RJ45_MDIN2
RJ45_MDIP2
RJ45_MDIP1
RJ45_MDIN0
RJ45_MDIP0
1 2
RL19 150_0402_5%
1 2
RL20 150_0402_5%
0.1U_0201_10V6K
+3.3V_LAN
CL19
RJ45 LOM circuit
+3.3V_LAN:20mils
JLOM1
CONN@
10
Yellow LED-
9
Yellow LED+
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
11
Green LED-
13
Orange LED-
12
Green-Orange LED+
SANTA_130470-19
GND
GND
GND
GND
1
17
16
15
14
Link DC231603220 (temp) DONE
12
RL18 75_0402_1%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
LAN Clarkvillie & RJ45
LAN Clarkvillie & RJ45
LAN Clarkvillie & RJ45
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-E122P
LA-E122P
LA-E122P
1
28 59Wednesday, November 09, 2016
28 59Wednesday, November 09, 2016
28 59Wednesday, November 09, 2016
1.0
1.0
1.0
A
B
C
D
E
For PCIE Interface
1 1
+3.3V_MMI_IN+3.3V_RUN
PJP14
+3.3V_MMI_AUX
RR19 10K_0402_5%
1 2
PAD-OPEN1x2m
1 2
12
+3.3V_MMI_AUX+3.3V_MMI_IN
R2740_0603_5% @
MEDIACARD_IRQ#
support D3 Hot(if D3 cold PIN11,PIN27 need Add MOS on/off 3V3AUX)
7/18 Vender suggest.
PCH_PLTRST#_AND< 11,30,34,35>
CLKREQ_PCIE#0<11>
CLK_PCIE_P0<11>
CLK_PCIE_N0<11>
1 2
PCIE_PTX_DRX_P1<10>
PCIE_PTX_DRX_N1<10>
PCIE_PRX_DTX_P1<10>
PCIE_PRX_DTX_N1<10>
CR11 0.1U_0402_25V6
CR12 0.1U_0402_25V6
CR13 0.1U_0402_25V6
CR14 0.1U_0402_25V6
+1.2V_LDO
CR13 close to UR2.10
CR9 CR10 close to UR2.14
4.7U_0603_6.3V6K
1
CR5
12
2
1 2
1 2
1 2
0.1U_0201_10V6K
CR6
MEDIACARD_IRQ#<9 >
0.1U_0201_10V6K
+1.8V_RUN_CARD
1
CR7
2
PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1
PCIE_PRX_C_DTX_P1
PCIE_PRX_C_DTX_N1
SD/MMCCD#
12
+RREF
RR4
1
2
1
2
5
6
3
4
7
8
32
31
30
10
14
13
9
6.2K_0402_1%
+3.3V_MMI_AUX
4.7U_0402_6.3V6M
0.1U_0201_10V6K
1
CR1
2
UR1
PERST#
CLK_REQ#
REFCLKP
REFCLKN
HSIP
HSIN
HSOP
HSON
WAKE#
MS_INS#
SD_CD#
AV12
DV12S
SD_VDD2
RREF
CR2
27
RTS5242
33
+3.3V_MMI_IN
0.1U_0201_10V6K
1
CR3
2
11
3V3_IN
CARD_3V3
3V3aux
DV33_18
SP1
SP2
SP3
SP4
SP5
SP6
SP7
SD_LN1_P
SD_LN1_M
SD_LN0_P
SD_LN0_M
SDREG2
GPIO
E-PAD
RTS5242-GR_QFN32_4X4
10U_0402_6.3V6M
CR4
1
2
12
18
15
SD/MMCDAT1/RCLK-
16
SD/MMCDAT0/RCLK+
17
SD/MMCCLK
19
SD/MMCCMD
20
SD/MMCDAT3
21
SD/MMCDAT2
29
SDWP
SD_UHS2_D1P
22
SD_UHS2_D1N
23
SD_UHS2_D0P
26
SD_UHS2_D0N
25
24
+SDREG2
28
+DV33_18
SD_GPIO
+3.3V_RUN_CARD
@EMI@
7/18 Vender suggest
1 2
CR15
1U_0402_6.3V6K
12
RR310K_0402_5%
1 2
CR22 1U_0402_6.3V6K
1 2
@
1 2
RR9 0_0402_5%
@
1 2
RR10 0_0402_5%
1 2
RR5 0_0402_5%
@
1 2
RR6 0_0402_5%
@
1 2
RR7 0_0402_5%
@
RR8 0_0402_5%
+3.3V_MMI_AUX
SD/MMCDAT1/RCLK-_R
SD/MMCDAT0/RCLK+_R
SD/MMCCLK_R
SD/MMCCMD_R
SD/MMCDAT3_R
SD/MMCDAT2_R
@EMI@
5P_0402_50V8C
12
CR21
EMI depop location
RF Request
+3.3V_MMI_IN+3.3V_MMI_AUX
@RF@
@RF@
12P_0402_50V8J
82P_0402_50V8J
1
1
CR27
CR28
2
2
2 2
@RF@
@RF@
82P_0402_50V8J
12P_0402_50V8J
1
1
CR26
CR25
2
2
3 3
HOST_SD_WP#
High
Low
SDWP_Q SDWP
Low
Low
Low
High Write Protect(FW LOCK)
STATUS
Write Enable
QR1
L2N7002WT1G_SC-70-3
SDWP_Q
1 3
D
SDWP
HOST_SD_WP#<12>
S
G
2
+3.3V_RUN_CARD +1.8V_RUN_CARD
2
CR17
1 2
CR18
1
0.1U_0201_10V6K
4.7U_0603_6.3V6K
2
CR19
1
+3.3V_RUN_CARD
+1.8V_RUN_CARD
CR20
1 2
0.1U_0201_10V6K
4.7U_0603_6.3V6K
SD/MMCCMD_R
SD/MMCCLK_R
SD/MMCCD#
SD/MMCDAT0/RCLK+_R
SD/MMCDAT1/RCLK-_R
SD/MMCDAT2_R
SD/MMCDAT3_R
SD_UHS2_D0P
SD_UHS2_D0N
SD_UHS2_D1P
SD_UHS2_D1N
JSD1
CONN@
4
VDD1
15
VDD2
3
CMD
5
CLK
9
CD
16
SWIO
7
DAT0/RCLK+
8
DAT1/RCLK-
1
DAT2
2
CD/DAT3
18
D0+
19
D0-
22
D1+
21
D1-
6
VSS1
17
VSS2
20
VSS3
23
VSS4
T-SOL_158-1240902600
GND1
GND2
GND3
GND4
GND5
10
11
12
13
14
CR38,CR39 near JSD1.4 CR40,CR41 near JSD1.14
4 4
LINK SP071603151 (temp) DONE
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
A
B
C
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
D
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Card Reader RTS5242
Card Reader RTS5242
Card Reader RTS5242
LA-E122P
LA-E122P
LA-E122P
E
29 59Wednesday, November 09, 2016
29 59Wednesday, November 09, 2016
29 59Wednesday, November 09, 2016
1.0
1.0
1.0
5
+3.3V_WW AN
NGFF slot B Key B
WWAN_PW R_EN
12
RZ43 47K_0402_5%
D D
Drop HCA functi on in DVT1.0
NonAR config su pport SATA onl y,
C C
+3.3V_WW AN
.047U_0402_16V7K
.047U_0402_16V7K
33P_0402_50V8J
22U_0603_6.3V6M
12
12
12
12
CZ19
CZ17
CZ18
CZ20
B B
USB3_PTX_DRX_P2<10>
USB3_PTX_DRX_N2<10>
100P_0402_50V8J
RF@
12
SATA_PTX_DRX_N1<10>
SATA_PTX_DRX_P1<10>
33P_0402_50V8J
12
CZ21
USB3_PRX_DTX_P2<10>
USB3_PRX_DTX_N2<10>
SLOT2_CONFIG_3<32>
CZ198
SLOT2_CONFIG_0<32>
WWAN_W AKE#<32>
SATA_PRX_DTX_P1<10>
SATA_PRX_DTX_N1<10>
1 2
CZ10 0.1U_0402_25V6
1 2
CZ11 0.1U_0402_25V6
SLOT2_CONFIG_1<32>
SLOT2_CONFIG_2<32>
+3.3V_WW AN
47P_0402_50V8J
RF@
12
12
CZ23
USB3_PTX_C_DRX_P2
12
CI30 0.1U_0402_25V6
USB3_PTX_C_DRX_N2
12
CI29 0.1U_0402_25V6
@RF@
RF Request
100P_0402_50V8J
2000P_0402_50V7K
RF@
12
CZ24
USB20_P4_L
USB20_N4_L
RZ326 0_0402_5%
USB3_PRX_L_DTX_N2
USB3_PRX_L_DTX_P2
USB3_PTX_L_DRX_N2
USB3_PTX_L_DRX_P2
SATA_PTX_C_DRX_N1
SATA_PTX_C_DRX_P1
RF@
100U_B2_6.3VM_R35M
RF@
1
+
CZ26
CZ25
2
1 2
RI27 0_0402_5%
@RF@
LI16
1 2
HCM2012GA900AE_4P
1 2
RI28 0_0402_5%
@RF@
1 2
RI29 0_0402_5%
@RF@
HCM2012GA900AE_4P
1 2
LI17
RI30 0_0402_5%
@RF@
T225PAD~D
@
RF@
RF@
1 2
12
SIM Card Push-Push
CONN@
JSIM1
C8
UIM_DATA
UIM_CLK
+SIM_PWR
UIM_CLK
A A
47P_0402_50V8J
@RF@
12
CZ38
51_0402_5%
RF@
12
RZ334
UIM_RESET
4.7U_0402_6.3V6M
12
CZ37
SIM_DET
5
RFU1
C7
IO
C6
VPP
C5
GND
C4
RFU2
C3
CLK
C2
RST
C1
VCC
1
DLSW
2
DTSW
JAE_SF51S006V4DR1000Q
S P
0 7
0 0
1 7
I 0
+SIM_PWR
@RF@
15K_0402_5%
12
RZ335
UIM_DATA UIM_RESET
33P_0402_50V8J
@RF@
12
CZ39
3
GND1
4
GND2
5
GND3
6
GND4
7
GND5
8
GND6
9
GND7
0
L I
N K
D
O N
E
+SIM_PWR
33P_0402_50V8J
@RF@
0.1U_0402_25V6
1
12
CZ40
2
RF Request
RF@
CZ41
8 0
34
34
4
JNGFF2
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
GND
BELLW_80149-3221
1 4
9 -
USB3_PRX_L_DTX_P2
USB3_PRX_L_DTX_N2
USB3_PTX_L_DRX_P2
USB3_PTX_L_DRX_N2
4
3 2
CONN@
2 1
STATE #
+3.3V_WW AN
2
2
4
4
WWAN_PW R_EN
6
6
WWAN_RADIO_DIS#_R
8
8
SLOT2_SATA_LED#
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
62
62
64
64
66
66
68
GND
L
I N
K
WWAN_RADIO_DIS#<32>
HW_GPS_DISABLE#<32>
USB20_P4<10>
USB20_N4<10>
CONFIG_0
0
1
8
14
15
RN101 0_0402_5%@
HW_GPS_DISABLE#_R
UIM_RESET
UIM_CLK
UIM_DATA
ISH_I2C2_SCL_R
ISH_I2C2_SDA_R
RZ76 0_0402_5%
@
RZ77 0_0402_5%
@
9/24: Reserve for embedded location ,refer Intel PDG 0.9
PCH_PLTRST#_AND
PCIE_WAKE#
@
RZ131 0_0402_5%
@
RZ132 0_0402_5%
WWAN_COEX3
WWAN_COEX2
WWAN_COEX1
SIM_DET
D O
N E
CONFIG_1
GND
GND
HIGH GND
HIGH
HIGH
GND
HIGH
GND
GND
HIGH
1 2
12
12
RZ128 0_0201_5%@RF@
RZ129 0_0201_5%@RF@
RZ130 0_0201_5%@RF@
RB751S40T1G_SOD523-2
RB751S40T1G_SOD523-2
RI47 0_0402_5%
@RF@
1 2
@RF@
+SIM_PWR
12
12
PORT80_DET# <32>
HOST_DEBUG_TX <32,33>
1 2
1 2
1 2
1 2
DZ5
1 2
DZ6
RF Request
1 2
HCM2012GA900AE_4P
LI8
RF@
1 2
RI48 0_0402_5%
CONFIG_2
GND
GND
GND
HIGH
HIGH
SATALED# <10 ,35,39>
M3042_DEVSLP <10>
ISH_I2C2_SCL <9>
ISH_I2C2_SDA <9>
WLAN_COEX3
WLAN_COEX2
WLAN_COEX1
WWAN_RADIO_DIS#_R
HW_GPS_DISABLE#_R
USB20_P4_L
34
USB20_N4_L
CONFIG_3
GND
GND
HIGH
HIGH
3
WLAN
WIGI
Module Type
SSD-SATA
SSD-PCIE(2 lane)
WWAN
HCA-PCIE(1 lane)
NA
3
2
1
for no AR,Brekenridge 12/14/15 UMA/Steamboat
NGFF slot A Key A
JNGFF1
CONN@
1
1 2
DZ1
1 2
DZ2
RF Request
RI49 0_0402_5%
@RF@
HCM2012GA900AE_4P
1 2
LI9
@RF@
2
1
3
3
5
5
7
7
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
76
GND
LCN_DAN05-67306-0100
S P
WLAN_WIGIG60GHZ_DIS#_R
BT_RADIO_DIS#_R
1 2
34
RF@
1 2
RI50 0_0402_5%
0 7
0 0
USB20_P7_L
USB20_N7_L
1 9
F 0
USB20_P7_L
USB20_N7_L
SW2_DP2_N3<21>
SW2_DP2_P3<21>
SW2_DP2_N2<21>
SW2_DP2_P2<21>
PCIE_PTX_DRX_P3<10>
PCIE_PTX_DRX_N3<10>
PCIE_PTX_DRX_P4<10>
PCIE_PTX_DRX_N4<10>
1 2
1 2
CV145 0.1U_0402_25V6
CV146 0.1U_0402_25V6
1 2
1 2
CV148 0.1U_0402_25V6
CV147 0.1U_0402_25V6
1 2
CZ12 0.1U_0402_25V6
1 2
CZ13 0.1U_0402_25V6
PCIE_PRX_DTX_P3<10>
PCIE_PRX_DTX_N3<10>
CLK_PCIE_P1<11>
CLK_PCIE_N1<11>
CLKREQ_PCIE#1<11>
PCIE_WAKE#<33,35>
1 2
CZ14 0.1U_0402_25V6
1 2
CZ15 0.1U_0402_25V6
PCIE_PRX_DTX_P4<10>
PCIE_PRX_DTX_N4<10>
CLK_PCIE_P2<11>
CLK_PCIE_N2<11>
WLAN_WIGIG60GHZ_DIS#<32>
BT_RADIO_DIS#<32>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
SW2_DP2_N3_C
SW2_DP2_P3_C
SW2_DP2_N2_C
SW2_DP2_P2_C
SW2_DP2_HPD<21>
PCIE_PTX_C_DRX_P3
PCIE_PTX_C_DRX_N3
PCIE_WAKE#
PCIE_PTX_C_DRX_P4
PCIE_PTX_C_DRX_N4
RB751S40T1G_SOD523-2
RB751S40T1G_SOD523-2
USB20_P7<10>
USB20_N7<10>
+3.3V_WLAN
2
2
4
4
6
6
16
16
18
18
SW2_DP2_AUXN_C
20
20
SW2_DP2_AUXP_C
22
22
24
24
SW2_DP2_N1_C
26
26
SW2_DP2_P1_C
28
28
30
30
SW2_DP2_N0_C
32
32
SW2_DP2_P0_C
34
34
36
36
38
38
40
40
42
42
WLAN_COEX3
44
44
WLAN_COEX2
46
46
WLAN_COEX1
48
48
50
52
54
56
58
60
62
64
66
68
70
72
74
GND
0
L I
50
52
54
56
58
60
62
64
66
68
70
72
74
77
N K
D
+3.3V_WLAN
12
WIGIG_32KHZ
PCH_PLTRST#_AND
BT_RADIO_DIS#_R
WLAN_WIGIG60GHZ_DIS#_R
ISH_UART0_RXD_R
ISH_UART0_TXD_R
ISH_UART0_CTS#_R
ISH_UART0_RTS#_R
PCH_PLTRST#_AND
PCIE_WAKE#
9/24: Reserve for embedded location ,refer Intel PDG 0.9
O N
E
0.1U_0201_10V6K
0.01UF_0402_25V7K
1
1
CZ30
CZ28
2
2
RF Request
+3.3V_WLAN
15P_0402_50V8J
12
Power Rating TBD
PWR
Rail
+3.3V
Voltage
Tolerance
Primary Power Aux Power
Peak Normal Normal
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
12
12
CV1500.1U_0402_ 25V6
CV1490.1U_0402_ 25V6
12
12
CV1520.1U_0402_ 25V6
CV1530.1U_0402_ 25V6
12
12
CV1560.1U_0402_ 25V6
CV1570.1U_0402_ 25V6
PCH_CL_RST1# < 8>
PCH_CL_DATA1 <8>
PCH_CL_CLK1 <8>
@
1 2
RZ56 0_0402_5%
PCH_PLTRST#_AND <11,29,34,35>
12
12
RZ78 0_0402_5%
@
12
RZ79 0_0402_5%
@
12
RZ80 0_0402_5%
@
RZ81 0_0402_5%
@
CLKREQ_PCIE#2 <11>
0.01UF_0402_25V7K
10U_0603_10V6M
CZ27
RF@
CZ33
0.1U_0201_10V6K
1
CZ29
2
15P_0402_50V8J
RF@
CZ35
12
12
NGFF Card
NGFF Card
NGFF Card
LA-E122P
LA-E122P
LA-E122P
1
12
CZ31
15P_0402_50V8J
RF@
CZ36
12
Place near JNGFF1.2/JNGFF1.4Place near JNGFF1.72/JNGFF1.74
15P_0402_50V8J
RF@
12
CZ34
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SW2_DP2_AUXN <21>
SW2_DP2_AUXP <21>
SW2_DP2_N1 < 21>
SW2_DP2_P1 <21>
SW2_DP2_N0 < 21>
SW2_DP2_P0 <21>
SUSCLK <11,35>
ISH_UART0_RXD <9>
ISH_UART0_TXD <9>
ISH_UART0_CTS# <9>
ISH_UART0_RTS# <9>
4.7U_0603_6.3V6K
CZ32
30 59Wednesday, November 09, 2016
30 59Wednesday, November 09, 2016
30 59Wednesday, November 09, 2016
1.0
1.0
1.0
5
1W x 1ch, 4ohm (Transducer spec is 8Ohm /0.5Watt per unit, there are two transduc er units in one speaker box.)
Internal Speakers Header
40 mils trace keep 20 mil spacing
1 2
LA6 B LM15PX330SN1D_2P
EMI@
1 2
LA7 B LM15PX330SN1D_2P
INT_SPK_R+
INT_SPK_R-
D D
EMI@
1 2
LA8 B LM15PX330SN1D_2P
EMI@
1 2
LA9 B LM15PX330SN1D_2P
EMI@
@ESD@
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
12
1000P_0402_50V7K
12
12
12
CA23@EMI@
CA19@EMI@
CA22@EMI@
CA24@EMI@
DA6
INT_SPKR_L+INT_SPK_L+
INT_SPKR_L-INT_SPK_LINT_SPKR_R+
INT_SPKR_R-
L03ESDL5V0CC3-2_SOT23-3
2
2
3
1
1
JSPK1
1
1
2
2
3
3
4
4
L03ESDL5V0CC3-2_SOT23-3
5
3
GND
6
@ESD@
GND
ACES_50278-0040N-001
Link SP02001CE00 DONE
DA7
CONN@
Close to UA1
Close to UA1 pin6
HDA_BIT_CLK_R
33_0402_5%
12
RA17@EMI@
10P_0402_50V8J
12
C C
CA33@EMI@
Place closely to Pin 13.
AUD_HP_NB_SENSE
place close to UA1 pin3
+3.3V_RUN_AUDIO
100K_0402_1%
12
200K_0402_1%
12
DMIC_CLK0
82P_0402_50V8J
1
2
RA59
RA60
RF@
CA54
AUD_SENSE_A
+3.3V_RUN_AUDIO
0.1U_0402_25V6
@
12
CA41
Add for solve
pop noise and
detect issue
4
+3.3V_RUN_AUDIO
1U_0603_10V6K
+3.3V_RUN_AUDIO
100K_0402_5%
RA61
1 2
12
LA12 BLM15PX600SN1D_2P
12
LA14 BLM15PX600SN1D_2P
0.1U_0201_10V6K
1
2
place close to pin1
HDA_SYNC_R<12>
HDA_BIT_CLK_R<12>
HDA_SDOUT_R<12>
RA52100K_0402_5%
12
RA1810K_0402_5%
12
CA31
12
HDA_BIT_CLK_R
Place RA9 close to codec
HDA_SDIN0<12>
DMIC0<27>
DMIC_CLK0 DMIC_CLK_CODEC
DMIC_CLK0<27>
PD#
AUD_SENSE_B
EMI@
10U_0603_10V6M
CA61
CA10
12
1 2
RA9 33_0402_5%
1 2
RA14
HDA_SDOUT_R
HDA_SDIN0_R
22_0402_5%
12
12
12
INT_SPK_L+
INT_SPK_LINT_SPK_RINT_SPK_R+
AUD_SENSE_A
AUD_SENSE_B
0.1U_0201_10V6K
1
2
12
RA44100K_0402_5%
CA5110U_0603_10V6M
CA5210U_0603_10V6M
CA5310U_0603_10V6M
+3.3V_RUN_AUDIO_IO
CA55
3
+5V_RUN_PVDD_L
10U_0603_10V6M
CA56
12
place close to pin9
+3.3V_RUN_AUDIO_DVDD
1
9
UA1
11
I2C_SDA
12
I2C_SCL
10
SYNC
6
BIT-CLK
5
SDATA-OUT
8
SDATA-IN
4
EAPD/DC DET
2
GPIO0/DMIC-DATA12
3
GPIO1/DMIC-CLK
47
PDB
48
SPDIFO/GPIO2/DMIC-DATA-34/DMIC-CLK-In/MIC-GPI
27
LDO1-CAP
39
LDO2-CAP
7
LDO3-CAP
42
SPK-L+
43
SPK-L-
44
SPK-R-
45
SPK-R+
13
HP/LINE1 JD1
14
MIC2/LINE2 JD2
15
SPDIFO/FRONT JD3/GPIO3
ALC3246-CG_MQFN48_6X6
41
DVDD
PVDD1
DVDD-IO
2
SPKR_R
RING2
SLEEVE
12
SPKR <12>
BEEP <32>
place close to pin46place close to pin41
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
CA45
1
2
+VDDA_AVDD1
+1.8V_RUN_AUDIO
26
36
40
46
AVDD1
AVDD2
PVDD2
CPVDD
LINE1-VREFO-L
LINE1-VREFO-R
MIC2-VREFO
VREF
CBN
CBP
5VSTB
CPVEE
MIC2-L/RING2
MIC2-R/SLEEVE
MIC-CAP
LINE2-L
LINE2-R
LINE1-L
LINE1-R
PCBEEP
HP-OUT-L
HP-OUT-R
AVSS1
AVSS2
THERMAL PAD
CA47
1
1
CA46
2
2
31
+LINE1-VREFO-L
30
+LINE1-VREFO-R
29
+MIC2-VREFO
28
35
CA35 2.2U_0402_6.3V6M
37
CA29 1U_0603_10V6K
20
RA53 0_0402_5%
@
@
RA54 0_0402_5%
34
CA49 1U_0603_10V6K
SLEEVE/RING2 please keep 40 mils trace width
17
RING2
18
SLEEVE
19
24
23
LINE1_L HP_OUT_L
22
LINE1_R
21
AUD_PC_BEEP
16
HP_OUT_L AUD_HP_OUT_L
32
HP_OUT_R
33
25
38
49
LA13
1 2
HCB2012VF-601T20_2P
10U_0603_10V6M
1
CA48
2
place close to pin26
10U_0603_10V6M
12
CA9
place close to pin40
10U_0603_10V6M
CA58
12
1 2
RA57 4.7K_0402_5%
1 2
RA58 4.7K_0402_5%
1 2
12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
600 Ohm/2A
0.1U_0201_10V6K
BLM15PX600SN1D_2P
CA8
1
2
@
0.1U_0201_10V6K
CA57
1
2
AUD_PC_BEEP SPKR_R
CA2510U_0603_10V6M
CA4310U_0603_10V6M
CA4410U_0603_10V6M
+5V_RUN_AUDIO
0.1U_0201_10V6K
10U_0603_10V6M
CA60
1
1
CA59
2
2
+5V_RUN_AUDIO
LA5
1 2
1 2
RA3 0_0603_5%
AUD_HP_OUT_L
AUD_HP_OUT_R
Place CA29 close to Codec
+5V_ALW
+RTC_CELL
CA27 0.1U_0402_25V6
CA28 0.1U_0402_25V6
HP_OUT_R
AUD_HP_OUT_R
RA716.2_0 402_1%
RA816.2_0 402_1%
+1.8V_RUN
AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
RA5 2.2K_0402_5%
+MIC2-VREFO
12
12
AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
RA6 2.2K_0402_5%
BEEP_R
RA12 1K_0402_5%
RA13 1K_0402_5%
1 2
1 2
1 2
1 2
100P_0402_50V8J
12
CA72@
1
10K_0402_5%
@
RA51
+1.8V_RUN_AUDIO
33P_0402_50V8J
1
2
BEEP_R
100P_0402_50V8J
10K_0402_5%
@
12
12
RA45
CA62@
RF Request
+5V_RUN_AUDIO
RF@
RF@
68P_0402_50V8J
12P_0402_50V8J
1
1
CA64
CA63
2
2
RF Request
+1.8V_RUN
RF@
CA69
12P_0402_50V8J
RF@
1
CA65
2
RF Request
+3.3V_RUN_AUDIO
RF@
12P_0402_50V8J
1
CA67
2
68P_0402_50V8J
RF@
1
CA66
2
RF@
68P_0402_50V8J
1
CA68
2
place at AGND and DGND plane
1 2
@
@
@
@
@
UZ5
@
1
VIN1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
VIN27VOUT2
EM5209VF_SON14_2X3
RA35 0_0402_5%
1 2
RA36 0_0402_5%
1 2
RA37 0_0402_5%
1 2
RA38 0_0402_5%
1 2
RA39 0_0402_5%
+3.3V_RUN_AUDIO_UZ5
14
VOUT1
13
VOUT1
12
CT1
11
GND
10
CT2
9
VOUT2
+5V_RUN_AUDIO_UZ5
8
15
GPAD
PAD-OPEN1x1m
+3.3V_RUN_AUDIO
12
PAD-OPEN1x1m
@
CZ125 0.1U_0201_10V6K
CZ126
@
CZ127
@
1 2
PAD-OPEN1x1m
CZ128 0.1U_0201_10V6K
@
PJP19
@
1 2
+5V_RUN
PJP15@
+3.3V_RUN +3.3V_RUN_AUDIO
1 2
1 2
1000P_0402_50V7K
1 2
220P_0402_50V7K
PJP16@
1 2
B B
Power sequence +5V_RUN_AUDIO(501us) > +3.3V_RUN_AUDIO(1204 us) > +1.5V_RUN
Reserve for support D3 cold
+3.3V_RUN
A A
AUD_PWR_EN<12>
+5V_ALW
+5V_RUN
5
CLASS-D POWER D OWN CONTROL CI RCUIT
AUD_NB_MUTE#<32>
HDA_RST#_R<12>
HDA_Link is 3.3V,no need level shift circ uit
PJP17
@
1 2
+5V_RUN_AUDIO
PAD-OPEN1x2m
PJP18
@
1 2
PAD-OPEN1x1m
+5V_RUN_AUDIO
500mA
4
2.5A
1 2
@
RA48 0_0402_5%
DA8
@
RB751S40T1G_SOD523-2
1 2
RA50 0_0402_5%@
21
RE313@one control line if DVDD is 3.3V
DE2@two control lines1
Add this Filter to avoid other
components/chips be infl uenced
680P_0402_50V7K
@ESD@
ESD@
DA1
AZ5123-02S.R7G_SOT23-3
3
2017/01/01
2017/01/01
2017/01/01
2
1
ESD@
DA2
L03ESDL5V0CC3-2_SOT23-3
1
2
CA13
AUD_HP_NB_SENSE
2
PD#
2016/01/01
2016/01/01
2016/01/01
RING2_R
AUD_HP_OUT_L1
AUD_HP_OUT_R1
SLEEVE_R
680P_0402_50V7K
ESD@
1
2
CA1
2
1
Compal Secret Data
Compal Secret Data
Compal Secret Data
2
EMI@
330P_0402_50V8J
CA2
EMI@
330P_0402_50V8J
680P_0402_50V7K
1
1
CA3
2
2
Deciphered Date
Deciphered Date
Deciphered Date
ESD@
2
3
CA4
1
1 2
LA10 BLM15PX330SN1D_2P
ESD@
RING2
AUD_HP_OUT_L
@EMI@
1 2
RA55 0_0402_5%
Only BR15U UMA use LA2,LA3,because 6L
AUD_HP_OUT_R
@EMI@
1 2
RA56 0_0402_5%
1 2
LA11 BLM15PX330SN1D_2P
ESD@
SLEEVE
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HP-Out-Right Nokia-MIC
HP-Out-Left
Universal Jack
JHP1
7
4
1
5
6
2
3
ESD@
3
DA3
AZ5123-02S.R7G_SOT23-3
1
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
SINGA_2SJ3095-085111F
680P_0402_50V7K
@ESD@
Link DC23000DG10 DONE
1
CA12
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Codec ALC3246
Codec ALC3246
Codec ALC3246
LA-E122P
LA-E122P
LA-E122P
Wednesday, November 09, 2016
Wednesday, November 09, 2016
Wednesday, November 09, 2016
iPhone-MIC
Global Headset
CONN@
GND
#4 G/M
#1 L/R
#5
#6 AGND
#2 R/L
#3 M/G
1
Normal
Open
31 59
31 59
31 59
1.0
1.0
1.0
5
+RTC_CELL
+3.3V_ALW_UE1
+3.3V_ALW
+3.3V_ALW_UE1
D D
0.1U_0201_10V6K
0.1U_0201_10V6K
CE19
1
2
close to pin G8/M9
RF Request
+3.3V_ALW
1
2
+3.3V_ALW_UE1
CE20
+3.3V_ALW_UE1
12
1 2
10U_0603_6.3V6M
CE16
0.1U_0201_10V6K
1
CE15
PJP22
@
PAD-OPEN1x1m
2
68P_0402_50V8J
12P_0402_50V8J
RF@
RF@
1
1
CE60
CE59
2
2
PJP20
@
+1.8V_PRIM
C C
+3.3V_ALW
+3.3V_ALW
@
RE526 10K_0402_5%
RE532 4.7K_0402_5%
B B
1 2
1
PAD-OPEN1x1m
CE22
0.1U_0201_10V6K
2
@
1 2
PAD-OPEN1x1m
RPE10
1
8
2
7
3456
100K_0804_8P4R_5%
1 2
RE95 100K_0402 _5%
@
USH_DET#
1 2
BCM5882_ALERT#
1 2
PJP21
CV2_ON_R
IMVP_VR_ON_EC
RUN_ON_EC
+3.3V_ALW
Close to pin H1
+1.8V_3.3V_ALW_VTR3
1
0.1U_0201_10V6K
Close to pin N5
2
TBT_RESET_N_EC_R
+3.3V_ALW2
100K_0402_5%
RE63
VCCST_PWRGD<11,14,33>
CE21
1 2
@
RE32 0_0402_5%
0.1U_0201_10V6K
CE13
1
12
2
12
RE314100_04 02_1%
22U_0603_6.3V6M
@
1
CE17
2
+VSS_PLL
SIO_SLP_SUS#<11,17,40,44,45,46>
1 2
@
RE308 0_0402_5%
SB12 only for wireless charger
SB12 only for wireless charger
12
RE57 1K_0402_5%
1U_0402_6.3V6K
0.1U_0201_10V6K
CE14
CE23
1
2
0.1U_0201_10V6K
1
CE18
2
1 2
RE349 43K_0402_1%
change to PS2
12
100K_0402_5%
RE58
WLAN_WIGIG60GHZ_DIS#<30>
CLK_TP_SIO_I2C_DAT<38>
DAT_TP_SIO_I2C_CLK<38>
1 2
1
1
JTAG1 CONN@
@SHORT PADS~D
2
2
A A
MEC_XTAL1 MEC_XTAL2
10P_0402_50V8J
12
CE28
JTAG_RST#
1U_0402_6.3V6K
100_0402_1%
12
12
RE65@
CE30
MEC_XTAL2_R
32 KHz Clock
YE1
1 2
32.768KHZ_9PF_X1A000141000200
5
12
@
RE290
0_0402_5%
8/28 schematic review
10P_0402_50V8J
12
CE29
For MEC5105 Rev.A:Pop RE361,Depop RE360,RE362
For MEC5105 Rev.B:Depop RE361,Pop RE360,RE362
For WDT issue fix options&assessm ent:Pop RE361, Depop RE362
SHD_IO2
PRIM_PWRGD_GPIO024
GPIO055 use for SHD_CS# (LPC) or PCH_RSMRST#(eSPI)
GPIO024 use for SHD_IO2 (LPC) or PRIM_PWRGD(eSPI)
PCH_RSMRST#_GPIO204
SHD_CS#
CLKRUN#<8>
SIO_EXT_SMI#<12>
SIO_RCIN#<8>
SIO_EXT_SCI#<9>
+3.3V_ALW_UE1
+1.8V_3.3V_ALW_VTR3
PCH_DPWROK_EC<33>
RUN_ON_EC<33>
SIO_EXT_WAKE#<9>
BT_RADIO_DIS#<30>
PBAT_PRES#<41,50>
PCH_ALW_ON<40>
AC_PRESENT<11>
SML1_SMBDATA<8>
SML1_SMBCLK<8>
WWAN_W AKE#<30>
SUSACK#<11>
SIO_PWRBTN#<11,14>
LID_CL#_NB<33>
JTAG_TDI<33>
JTAG_TDO<33>
JTAG_CLK<33>
JTAG_TMS<33>
FAN1_TACH<33>
LCD_TST<27>
WWAN_RADIO_DIS#<30>
FAN1_PWM<33>
BIA_PWM_EC<27>
ACAV_IN_NB<41,50,51>
PANEL_BKEN_EC<27>
SIO_SLP_WLAN#<11,40>
AC_DIS<50>
BCM5882_ALERT#<34>
MSCLK<33>
MSDATA<33>
AUD_NB_MUTE#<31>
EN_INVPWR<27>
IMVP_VR_ON_EC<33>
SIO_SLP_S3#<11,33>
SIO_SLP_S5#<11>
@
T264
PAD~D
AC_DISC#<41,51>
USH_DET#<34>
@
T262
PAD~D
BC_DAT_ECE1117<38>
BC_CLK_ECE1117<38>
SLOT2_CONFIG_3<30>
ESPI_RESET#<8>
ESPI_ALERT#<8>
PCH_PLTRST#_5105<33>
ESPI_CLK_5105<8,33>
ESPI_CS#<8,33>
ESPI_IO0<8 ,33>
ESPI_IO1<8 ,33>
ESPI_IO2<8 ,33>
ESPI_IO3<8 ,33>
SYS_PWROK<11,14>
ENVDD_PCH<6,27>
4
+RTC_CELL_VBAT
0.1U_0201_10V6K
CE11
1
2
+3.3V_EC_PLL
RUN_ON_EC
BT_RADIO_DIS#
PCH_ALW_ON
WWAN_W AKE#
VCCST_PWRGD_EC
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#
LCD_TST
WWAN_RADIO_DIS#
PS_ID<41>
SHD_CS#
SHD_CLK
TBT_RESET_N_EC_R
VGA_ID
AC_DIS
MSCLK
MSDATA
EN_INVPWR
PRIM_PWRGD_GPIO024
IMVP_VR_ON_ECPCH_ALW_ON
VBUS3_ECOK
GPIO126
RTCRST_ON_GPIO122
DCIN3_EN
SIO_EXT_SMI#_EC
SIO_RCIN#_EC
CLKRUN#_EC
SIO_EXT_SCI#_EC
SYS_PWROK
MEC_XTAL1
MEC_XTAL2_R
@
1 2
RE360 0_0402_5%
@
1 2
RE361 49.9K_0402_1%
1 2
RE362 100K_0402_5%
LPC@
1 2
RE363 0_0402_5%
1 2
@ESPI@
RE364 0_0402_5%
1 2
RE337 0_0402_5%LPC@
1 2
RE338 0_0402_5%LPC@
1 2
RE339 0_0402_5%LPC@
1 2
RE341 0_0402_5%LPC@
4
3
GPIO223
GPIO224
eSPI
NA NANA
LPC
SHD_IO0
GPIO204
NA
eSPI
RSMRST#
LPC
For EVT/DVT1.0 Only,SA00009GL10, S IC MEC5105K-TMP2-TN WFBGA 169P EC
After DVT1.1,SA00009GL00, S IC MEC5105K-D1-TN WFBGA 169P EC
UE1
A2
VBAT
B7
VTR_ANALOG
K2
VREF_ADC
F1
VTR_PLL
H1
VTR_REG
G8
VTR1
M9
VTR2
N5
VTR3
F8
GPIO020
E8
GPIO045
M12
GPIO120
C2
GPIO166
F9
GPIO175
N4
GPIO230
M8
GPIO231
K8
GPIO233
E11
GPIO007/SMB03_DATA/PS2_CLK0B
D8
GPIO010/SMB03_CLK/PS2_DAT0B
M13
GPIO110/PS2_CLK2
K12
GPIO111/PS2_DAT2
L13
GPIO112/PS2_CLK1A
K11
GPIO113/PS2_DAT1A
K10
GPIO114/PS2_CLK0A/nEC_SCI
N11
GPIO115/PS2_DAT0A
E10
GPIO154/SMB02_DATA/PS2_CLK1B
C12
GPIO155/SMB02_CLK/PS2_DAT1B
E9
GPIO145/SMB09_DATA/JTAG_TDI
F6
GPIO146/SMB09_CLK/JTAG_TDO
C8
GPIO147/SMB08_DATA/JTAG_CLK
C5
GPIO150/SMB08_CLK/JTAG_TMS
G13
JTAG_RST#
E3
GPIO050/FAN_TACH0/GTACH0
D1
GPIO051/FAN_TACH1/GTACH1
M2
GPIO052/FAN_TACH2/LRESET#
L10
GPIO053/PWM0/GPWM0
L11
GPIO054/PWM1/GPWM1
M5
GPIO055/PWM2/SHD_CS#/(RSMRST#)
J8
GPIO056/PWM3/SHD_CLK
N1
GPIO001/PWM4
L8
GPIO002/PWM5
N6
GPIO014/PWM6/GPTP-IN6
J9
GPIO015/PWM7
H11
GPIO035/PWM8/CTOUT1
D9
GPIO133/PWM9
H12
GPIO134/PWM10/UART1_RTS#
G10
GPIO135/UART1_CTS#
H10
GPIO170/TFDP_CLK/UART1_TX
G9
GPIO171/TFDP_DATA/UART1_RX
A4
GPIO022/GPTP-IN0
B2
GPIO023/GPTP-IN1
C1
GPIO024/nRESETI
N7
GPIO031/GPTP-OUT1
K9
GPIO032/GPTP-OUT0
N8
GPI0040/GPTP-OUT2
F13
GPIO121/PVT_IO0
E13
GPIO124/GPTP-OUT6/PVT_CS#
C13
GPIO125/GPTP-OUT5/PVT_CLK
E12
GPIO126/PVT_IO3
F11
GPIO122/BCM0_DAT/PVT_IO1
F12
GPIO123/BCM0_CLK/PVT_IO2
D12
GPIO046/BCM1_DAT
D13
GPIO047/BCM1_CLK
F4
GPIO041/SYS_SHDN#
B1
SYSPWR_PRES
K7
GPIO011/nSMI
N3
GPIO021/LPCPD#
K6
GPIO061/LPCPD#/ESPI_RESET#
H7
GPIO063/SER_IRQ/ESPI_ALERT#
K1
GPIO064/LRESET#
G7
GPIO065/PCI_CLK/ESPI_CLK
H6
GPIO066/LFRAME#/ESPI_CS#
K5
GPIO070/LAD0/ESPI_IO0
L4
GPIO071/LAD1/ESPI_IO1
G6
GPIO072/LAD2/ESPI_IO2
L5
GPIO073/LAD3/ESPI_IO3
L2
GPIO067/CLKRUN#
M1
GPIO100/nEC_SCI
G4
GPIO106/PWROK
L12
GPIO107/nSMI
A1
XTAL1
A3
XTAL2
1.8V_PRIM_PWRGD <46>
+3.3V_ALW
PCH_RSMRST# <38>
CLKRUN#_EC
SIO_EXT_SMI#_EC
SIO_RCIN#_EC
SIO_EXT_SCI#_EC
SHD_IO1
GPIO011
NA NA
SIO_EXT_SMI#
VSS1
A6
GPIO227
*PRIM_PWRGD NA
SHD_IO2
* For Version B IC
GPIO100
VSS2
A13
GPIO056
GPIO016
SHD_CLK
SHD_IO3
GPIO021
SIO_RCIN#
SIO_EXT_SCI#
LPCPD#
GPIO034/RC_ID1/SPI0_CLK
GPIO036/RC_ID2/SPI0_MISO
GPIO003/SMB00_DATA/SPI0_CS#
GPIO004/SMB00_CLK/SPI0_MOSI
GPIO060/KBRST/48MHZ_OUT
GPIO127/A20M/UART0_CTS#
GPIO025/TIN0/nEM_INT/UART_CLK
GPIO005/SMB01_DATA/GPTP-OUT4
GPIO006/SMB01_CLK/GPTP-OUT7
GPIO012/SMB07_DATA/TOUT3
GPIO013/SMB07_CLK/TOUT2
GPIO130/SMB10_DATA/TOUT1
GPIO131/SMB10_CLK/TOUT0
GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD#
GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR#
GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR#
GPIO140/SMB06_CLK/ICT5
GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI#
GPIO224/GPTP-IN4/SHD_IO1
GPIO016/GPTP-IN7/SHD_IO3/ICT3
GPIO165/32KHZ_IN/CTOUT0
GPIO221/GPTP-IN3/32KHZ_OUT
GPIO042/PECI_DAT/SB-TSI_DAT
GPIO160/PWM11/PROCHOT#
VSS_ADCH4VR_CAPJ1VSS_PLL
VSS3
E6
VSS_ANALOG
C4
G1
+VSS_PLL
+VR_CAP
12
CE31 1U_0402_6.3V6K
+3.3V_ALW
RE68
1 2
61
RUN_ON<17,33,40,45>
2
3
GPIO055
PCH_RSMRST#
SHD_CS#
GPIO067
NA
CLKRUN#
GPIO033/RC_ID0
GPIO057/VCC_PWRGD
GPIO104/UART0_TX
GPIO105/UART0_RX
GPIO225/UART0_RTS#
GPIO026/TIN1
GPIO027/TIN2
GPIO030/TIN3
GPIO017/GPTP-IN5
GPIO151/ICT4
GPIO152/GPTP-OUT3
GPIO156/LED0
GPIO157/LED1
GPIO153/LED2
GPIO226/LED3
GPIO132/SMB06_DATA
GPIO200/ADC00
GPIO201/ADC01
GPIO202/ADC02
GPIO203/ADC03
GPIO204/ADC04
GPIO205/ADC05
GPIO206/ADC06
GPIO207/ADC07
GPIO210/ADC08
GPIO211/ADC09
GPIO212/ADC10
GPIO213/ADC11
GPIO214/ADC12
GPIO215/ADC13
GPIO216/ADC14
GPIO217/ADC15
GPIO222/SER_IRQ
GPIO223/SHD_IO0
GPIO227/SHD_IO2
GPIO164/VCI_OVRD_IN
VCI_OUT
GPIO163/VCI_IN0#
GPIO162/VCI_IN1#
GPIO161/VCI_IN2#
GPIO000/VCI_IN3#
GPIO044/VREF_VTT
GPIO043/SB-TSI_CLK
DN1_DP1A
DP1_DN1A
DN2_DP2A
DP2_DN2A
DN3_DP3A
DP3_DN3A
DN4_DP4A
DP4_DN4A
GPIO103/THERMTRIP2#
THERMTRIP1#
MEC5105_WFBGA169_11X11
+3.3V_RUN
100K_0402_5%
RUNPWROK
RUN_ON#
5
DMN65D8LDW-7_SOT363-6
QE2A
BGPO0
RE67
VSET
VIN
VCP
10K_0402_5%
1 2
DMN65D8LDW-7_SOT363-6
34
2
TYPEC_ID
F2
PANEL_ID
J10
BOARD_ID
J13
UPD2_SMBDAT
E7
UPD2_SMBCLK
D7
G3
HW_GPS_DISABLE#
H5
G11
G12
B13
UPD1_ALERT#
F10
PCIE_WAKE#_R
N13
N12
M11
H9
L9
M10
N9
C11
D10
D11
E1
E5
B3
EXPANDER_GPU_SMDAT
M7
EXPANDER_GPU_SMCLK
M4
PBAT_CHARGER_SMBDAT
M3
PBAT_CHARGER_SMBCLK
N2
N10
A12
RTCRST_ON_GPIO141
B6
F7
UPD1_SMBDAT
B4
UPD1_SMBCLK
C3
I_BATT_R
J4
I_SYS_R
J5
J6
G2
H2
J2
J3
K3
D3
D2
E2
G5
F5
K4
L1
L3
H8
J7
L6
L7
M6
D6
C7
A5
D5
B5
D4
E4
C6
F3
J11
K13
J12
A8
A7
A10
A9
B9
B8
A11
B10
C10
C9
B11
H3
B12
H13
QE2B
@
PCH_RSMRST#_GPIO204
USB_PWR_SHR_VBUS_EN
USB_PWR_SHR_LFT_EN#
USB_PWR_EN1#
USB_PWR_EN2#
UPD2_ALERT#
CV2_ON_R
SHD_IO0
SHD_IO1
SHD_IO2
SHD_IO3
VCI_IN1#
VCI_IN2#
POA_WAKE#
32KHZ_OUT
+PECI_VREF
PECI_EC_R
M3042_PCIE#_SATA
REM_DIODE1_N
REM_DIODE1_P
REM_DIODE2_N
REM_DIODE2_P
REM_DIODE4_N
REM_DIODE4_P
+VR_CAP
VSET_5105
THERMATRIP2#
THERMATRIP1#
H_PROCHOT#_R1
RTCRST_ON_GPIO141
RTCRST_ON_GPIO122
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
TYPEC_ID <33>
PANEL_ID <33>
BOARD_ID <33 >
RUNPWROK <14>
HW_GPS_DISABLE# <30>
HOST_DEBUG_TX <30,33>
ME_FW_EC <12>
ME_SUS_PWR_ACK <11>
UPD1_ALERT# <24>
PCIE_WAKE#_R <33>
SIO_SLP_S4# <11,17,43,46>
SIO_SLP_A# <11>
SIO_SLP_LAN# <11,40>
BEEP <31>
SLOT2_CONFIG_1 <30>
SLOT2_CONFIG_0 <30>
BREATH_LED# <39>
BAT1_LED# <39>
BAT2_LED# <39>
LCD_VCC_TEST_EN <27>
USH_SMBDAT <34>
USH_SMBCLK <34>
EXPANDER_GPU_SMDAT <33>
EXPANDER_GPU_SMCLK <33>
PBAT_CHARGER_SMBDAT <41,50>
PBAT_CHARGER_SMBCLK <41,50>
SLOT2_CONFIG_2 <30>
SYS_LED_MASK# <28,39>
UPD1_SMBDAT <24>
UPD1_SMBCLK <24>
1 2
RE64 300_0402_5%
1 2
RE312 300_0402_5%
1 2
RE318 0_0402_5%
USB_PWR_SHR_VBUS_EN <36>
USB_PWR_SHR_LFT_EN# <36>
USB_PWR_EN1# <37>
AUX_EN_WOWL <40>
LOM_CABLE_DETECT# <28>
BC_INT#_ECE1117 <38>
PORT80_DET# <30>
PCH_PCIE_WAKE# <11,33>
LAN_WAKE# <11,28>
SHD_IO0 <33>
1 2
RE539 100_0402_5%
1 2
RE366 24.9_0402_1%LPC@
1 2
RE368 24.9_0402_1%LPC@
1 2
RE370 24.9_0402_1%LPC@
1 2
RE372 24.9_0402_1%LPC@
Place near UE1 Place near UE9
EC_FPM_EN <34>
ACAV_IN <33,50>
ALWON <42>
POWER_SW_IN# <33>
POA_WAKE# <34>
3.3V_WWA N_EN <40>
1 2
CE54 10P_0402_50V8J
@
1 2
RE60 43_0402_5%
1 2
CE24 2200P_0402_50V7K
1 2
CE26 2200P_0402_50V7K
1 2
CE27 2200P_0402_50V7K
VSET_5105 <33>
I_ADP <50>
THERMATRIP2# <33>
1 2
RE288 100_0402_5%
1 2
@
RE514 0_0402_5%
1 2
@
RE515 0_0402_5%
I_BATT <50>
I_SYS <47,50>
TOUCHPAD_INTR# <12,38>
CV2_ON <34>
SHD_IO0_R1 SHD_IO0_R2
SHD_IO1_R1
SHD_IO2_R1
SHD_IO3_R1
PECI_EC <12>
M3042_PCIE#_SATA <10>
H_PROCHOT# <12,47,50>
RTCRST_ON
2
G
12
RE93
100K_0201_5%
2
LPC@
RE374 24.9_0402_1%
RE367 45.3_0402_1%LPC@
RE369 45.3_0402_1%LPC@
RE371 45.3_0402_1%LPC@
RE373 45.3_0402_1%LPC@
+PECI_VREF
REM_DIODE1_N
REM_DIODE1_P
REM_DIODE2_N
REM_DIODE2_P
REM_DIODE4_N
REM_DIODE4_P
RE94
1 2
75_0402_5%
13
D
QE12
L2N7002WT1G_SC-70-3
S
1 2
1 2
1 2
1 2
1 2
RE59 close to UE2 at least 250mils
1 2
@
RE59 0_0402_5%
0.1U_0201_10V6K
CE25
12
REM_DIODE1_N <33>
REM_DIODE1_P <33>
REM_DIODE2_N <33>
REM_DIODE2_P <33>
REM_DIODE4_N <33>
REM_DIODE4_P <33>
For EMI request
ESPI_CLK_5105
33_0402_5%
12
RE350
33P_0402_50V8J
12
PCH_RTCRST# <11>
1
For SB
UPD1_SMBDAT
UPD1_SMBCLK
UPD1_ALERT#
UPD2_ALERT#
PBAT_CHARGER_SMBDAT
PBAT_CHARGER_SMBCLK
EXPANDER_GPU_SMDAT
EXPANDER_GPU_SMCLK
UPD2_SMBCLK
UPD2_SMBDAT
SLOT2_CONFIG_0
SLOT2_CONFIG_1
SLOT2_CONFIG_2
SLOT2_CONFIG_3
USB_PWR_SHR_VBUS_EN
USB_PWR_SHR_LFT_EN#
USB_PWR_EN1#
USB_PWR_EN2#
AC_DIS
HW_GPS_DISABLE#
WLAN_WIGIG60GHZ_DIS#
WWAN_W AKE#
SYS_LED_MASK#
THERMATRIP1#
PORT80_DET#
LOM_CABLE_DETECT#
+1.0V_VCCST
PCIE_WAKE#_R
GPIO126
BC_DAT_ECE1117
WWAN_RADIO_DIS#
BT_RADIO_DIS#
+3.3V_ALW
SHD_CLK_R1
SHD_IO0_R2
I_BATT_R
I_SYS_R
PCH_RSMRST#
SYS_PWROK
I_SYS_R
LCD_TST
EN_INVPWR
PORT80_DET#
VGA_ID
VGA_ID
SHD_CLK_R1SHD_CLK
SHD_IO1_R2
SHD_IO2_R2
SHD_IO3_R2
@EMI@
@EMI@
CE57
SHD_IO2_R1
SHD_IO3_R1
SHD_CS#
VCI_IN1#
VCI_IN2#
POA_WAKE#
LPC@
LPC@
8
7
6
5
RE302 2.2K_0402_5%
RE303 2.2K_0402_5%
RE91 100K_0402_5%
RE92 100K_0402_5%
RE37 2.2K_0402_ 5%
RE43 2.2K_0402_ 5%
RE524 2.2K_0402_5%
RE525 2.2K_0402_5%
2.2K_0804_8P4R_5%
100K_0804_8P4R_5%
100K_0804_8P4R_5%
RE83 100K_0402_5%@
RE12 100K_0402_5%
RE8 100K_0402_5%
RE38 10K_0402_5%
RE21 10K_0402_ 5%
RE301 10K_0402_5%
RE512 100K_0402_5%
@
RE505 100K_0402_5%
RE35 10K_0402_5%
RE5 10K_0402_5%
RE365 100K_0402_5%
RE10 100K_0402 _5%
RE11 100K_0402 _5%
RE376 1K_0402_5%
RE377 1K_0402_5%
RE98 4.7K_0402_5%LPC@
LPC@
VCC
HOLD#(IO3)
CLK
DI(IO0)
W25Q80DVSSIG_SO8
CE3 2200P_0402_50V7K
CE4 2200P_0402_50V7K
RE342 10K_0402_5%
RE56 10K_0402_5%
@
RE313
RE20 100K_0402 _5%
RE55 100K_0402_5%
RE513 100K_0402_5%
@
1 2
RE507 100K_0402_5%
1 2
RE508 100K_0402_5%
1 2
RE324 100K_0402_5%
RE84 100K_0402 _5%
RE85 100K_0402 _5%@
Discrete
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
EC MEC5105
EC MEC5105
EC MEC5105
LA-E122P
LA-E122P
LA-E122P
1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
RPE12
1
2
3
4 5
4 5
3
2
1
RPE9
RPE11
1
2
3
4 5
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
CS#
DO(IO1)
WP#(IO2)
GND
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
8
7
6
6
7
8
8
7
6
UE9
1
2
3
4
10K_0402_5%
VGA_ID0
0
1UMA
SHD_CS#
SHD_IO1_R2SHD_IO3_R2
SHD_IO2_R2
+RTC_CELL
+3.3V_ALW
32 59Wednesday, November 09, 2016
32 59Wednesday, November 09, 2016
32 59Wednesday, November 09, 2016
+3.3V_ALW
+3.3V_ALW
1.0
1.0
1.0
5
+1.8V_3.3V_ALW_VTR3
+3.3V_ALW
UE6
1
5
NC
VCC
CONN@
2
A
4
Y
3
GND
74AUP1G07GW_TSS OP5
+3.3V_RUN
JESPI
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
1 2
RE375 0_0 402_5%
LPC@
8
9
9
10
10
11
GND1
12
GND2
PCH_PLTRST#_EC<11>
D D
ACES_50506-01041-P01
LPC 80Port Debug LPC ESPI
1
+3.3V_RUN
2
+3.3V_RUN
LPC_LAD0
3
LPC_LAD1
C C
B B
Control Byte
0 1 0 0 A2 A1 A0 R/W
R/W = 0 = Write
R/W = 1 = Read
4
LPC_LAD2
5
LPC_LAD3
6
LPC_FRAME#
7
PCH_PLTRST#
8
GND
9
LPC_CLOCK
10
PCH_DPWROK_EC<32>
@
RE530 1M_04 02_5%
12
1U_0402_6.3V6K
@
CE503
12
ACAV_IN<32 ,33,50>
In DC mode, ACAV_IN is LOW. This circuit doesn't affect PCH_DPWROK.
In AC mode, 1. ACAV_IN is high. GPIO223 is tri-state. QE13B is ON. QE13A can prevent backdrive to PCH_DPWROK.
2. EC fetches code and the drives GPIO223 to LOW to turn off QE13B. When QE13B is off, un-plug/plug AC will not affect DSW_DPWROK.
3. When WDT occurs, GPIO223 is tri-state (EC reset). ACAV_IN charges CE503. When AC is removed, ACAV_IN goes LOW immediately.
QE13B still kepps on according to RC discharging rate. PCH_DPWROK is LOW because ACAV_IN is LOW.
@
+3.3V_ALW
SMBus address 0x40
WRST#
+3.3V_ALW
10K_0402_5%
10K_0402_5%
10K_0402_5%
12
12
12
@
@
@
RE15
RE13
RE17
10K_0402_5%
10K_0402_5%
10K_0402_5%
12
12
12
RE14
RE18
RE16
+3.3V_ALW
10K_0402_5%
12
RE6
A A
1U_0402_6.3V6K
12
CE500
RE340
10K_0402_ 5%
1 2
PCH_PLTRST#_EC
+3.3V_RUN
+3.3V_RUN
ESPI_IO0
ESPI_IO1
ESPI_IO2
ESPI_IO3
ESPI_CS#
NA
GND
ESPI_CLK
@
CE6
0.1U_0402_25V6K
1 2
@
RE34 0_0402_5%
GPIO223 is OD. When EC fetches
the code, set GPIO223 to Low.
SHD_IO0 <32 >ACAV_IN<32,33 ,50>
5
QE13B
DMN65D8LDW-7_SOT363-6
6 1
34
EXPANDER_GPU_SMCLK<32 >
EXPANDER_GPU_SMDAT<32>
@
T267
PAD~D
PCH_PLTRST#_5105 <32>
ESPI_IO0 <8,32>
ESPI_IO1 <8,32>
ESPI_IO2 <8,32>
ESPI_IO3 <8,32 >
ESPI_CS# <8,32>
ESPI_CLK_5105 <8,32>
WDT option
MEC5105 rev.B
MEC5105 rev.C
+3.3V_ALW
1
2
2
QE13A
@
DMN65D8LDW-7_SOT363-6
0.1U_0402_25V6K
1
12
CE1
2
EXPANDER_ALERT#
PAGE
8
18 RC212_0ohm RC211_0ohm
31
32
Pop RE361, QE13, CE503, RE530, UE7, CE5,CE6, RE348
Depop RE362, RE536, RE537
Pop RE362, RE536
Depop RE361, QE13, CE503, RE530, UE7, CE5,CE6, RE348, RE537
@
UE7
5
1
VDD
RESET
3
4
MR
@
RE348
10K_0402_ 5%
1 2
1 2
1U_0402_6.3V6K
CE2
18
19
20
WRST#
MCP23008T-E-ML_QFN20_4X4
CT
2
GND
RT9826-30GB
1 2
RE536 0_0402_5%
@
RE537
10K_0402_5%
CT: 3300 pF ~ 10ms delay
Reset Threshold Level 3.0V
To prevent backdrive to PCH_DPWROK_EC
when AC is plugged before +3.3V_ALW ramps up.
UE2
VSTBY33
SCL
SDL
16
GP7
1
15
A2
GP6
2
14
A1
GP5
3
13
A0
GP4
12
GP3
4
11
WRST#
GP2
10
GP1
7
9
INT
GP0
5
NC
6
NC
8
17
NC
VSS
21
EPAD
Link Microchip MCP23008 SA0000ADQ00 OK (9/6)
5
4
ESPI LPC
RC25_10K RC8_15ohm
RC13/RC27_8.2K
0603 0603
RE337,RE338
RE339,RE340,
RE341
0_ohm
RE2 / RE3
0_ohm
PCH_DPWROK <11>
12
@
CE5
3300P_0402_50V7-K
VBUS2_ECOK <41,51>
DCIN2_EN <41>
SATA_LED_EN <39>
VBUS1_ECOK <51>
DCIN1_EN <51>
USH_PWR_STATE# <34>
4
CONN@
JDEG1
1
1
2
2
3
3
4
4
5
5
6
11
6
G1
7
12
7
G2
8
8
9
9
10
10
ACES 50506-01 041-P01
+EC_DEBUG_VCC
3
12
RE71
49.9_0402_1%
DEBUG_TX
@
3
10K_8P4R_5%
678
RPE7
123
4 5
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
MSCLK
MSDATA
HOST_DEBUG_TX
SBIOS_TX<9>
HOST_DEBUG_TX <30,32>
MSDATA <32>
MSCLK <32>
1 2
RE30 0_0402_5%
+1.0VS_VCCIO
+1.0V_VCCST
POWER_SW_IN#<32>
LID_CL#_NB
JTAG_TDI <32>
JTAG_TMS <32>
JTAG_CLK <32>
JTAG_TDO <32>
CHECK
QE11
@
2
1 3
D
L2N7002WT1G_SC-70-3
1 2
@
RE90 0_0402_5%
+RTC_CELL
+3.3V_ALW
12
12
RF Request
+3.3V_ALW
+3.3V_ALW
1 2
RE306
0_0402_5%
@
SIO_SLP_S3# <11,32,33>
G
RE70 2.2 K_0402_5%
S
100K_0402_5%
12
RE31
1 2
RE33 1K_0402_5%
2.2U_0402_6.3V6M
12
CE12
100K_0402_5%
RE25
RE26
.047U_0402_16V7K
10_0402_5%
CE8
1
CE61
2
68P_0402_50V8J
RF@
CE10@
1 2
1U_0402_6.3 V6K
12
LID_CL# <39>LID_CL#_NB<32>
TYPEC_ID<32>
CE62RE343
4700p240K
*
4700p130K
4700p
62K
33K
4700p
8.2K
4700p
4700p
4.3K
2K
4700p
4700p
1K
PD_ACE_DET# rise time is measured from 5%~68%.
100K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
12
12
12
12
RE74
RE75@
RE72
RE73
RE86
10K_0402_ 5%
1 2
RE69
1 2
+3.3V_ALW
8.2K_0402_ 5%
1 2
2
B
E
H_THERMTRIP#<12,20>
2
PCIE_WAKE#_R<32>
POWER_SW#_MB <11,39>
+3.3V_ALW
RE343
240K_0402_5%
1 2
12
CE62
4700P_040 2_25V7K
REV
Single Port ACE w/o AR
Single Port ACE w/AR
Dual Port ACE w/o AR
Dual Port ACE w/AR
Dual Port ACE (w/AR +w/o AR)
IMVP_VR_ON_EC<32>
SIO_SLP_S3#<11,32,33>
RUN_ON_EC<32>
RUN_ON_EC
Stuff RE275 and no stuff RE274 keep E5 design
Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
IMVP_VR_ON_EC
SIO_SLP_S3#
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
RE79
240K 4700p
130K
62K
33K 4700p
8.2K
4.3K
*
2K
BOARD_ID rise time is measured from 5%~68%.
Rest=1.58K , Tp=96 degree???
+3.3V_RUN
RE48 10 K_0402_5%
RE51 10 K_0402_5%
5105 Channel
DP1/DN1
DP2/DN2
DN2a/DP2a
DP3/DN3
DP4/DN4
0.1U_0402_25V6
THERMATRIP2# <32>
CE36
LMBT3904WT1G SC70-3
12
C
QE4
3 1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
100P_0402_50V8J
C
@
CE39
3 1
1 2
1 2
@
RE275 0_0402_5%
12
@
RE3040_0402_ 5%
+3.3V_ALW
@
CE53
1 2
0.1U_0402_25V6K
5
1
P
B
4
O
2
A
G
UE3
3
1 2
@
RE2800_0402_5%
12
@
RE2920_0402_ 5%
+3.3V_ALW
@
CE52
1 2
0.1U_0402_25V6K
5
1
P
B
4
O
2
A
G
UE5
3
+3.3V_ALW
12
RE79
REV
X00
X01
X02
X03
X04
A00
4.3K_0402_5%
12
CE40
4700P_040 2_25V7K
VSET_5105 <32>
BOARD_ID<32> PANEL_ID<32>
CE40
4700p
4700p
4700p
4700p
4700p
4700p1K
VSET_5105
0.1U_0402_25V6
1.58K_0402_1%
12
12
RE77
CE38
Link 50271-0040N-001 DONE
FAN1_PWM
1 2
FAN1_TACH
1 2
Thermal diode mapping
ACES_50271-00 40N-001
Location
CPU (QE3)
WiGig (QE5)
DDR (QE7)
NA
CPU VR (QE6)
DP4/DN4 for Skin on
QE6, place QE6 close to
Vcore VR choke.
REM_DIODE4_P <32>
2
B
E
QE6
LMBT3904WT1G SC70-3
REM_DIODE4_N <32>
DELL CONFIDENTIAL/PROPRIETARY
1
For SB
PCIE_WAKE# <30,35>
1 2
PCH_PCIE_WAKE# <11,32>
RE2740_0402_5%
@
+3.3V_ALW
UE4
1
5
NC
2
A
3
GND
74AUP1G07GW_TSS OP5
RE300 CE47
*
33K
1
2
3
4
5
6
C
2
B
E
QE3
3 1
LMBT3904WT1G SC70-3
100P_0402_50V8J
B
2
LMBT3904WT1G SC70-3
MEC5105 support
MEC5105 support
MEC5105 support
1
PANEL_IDBOARD_ID
12
CE37@
VCC
Y
+3.3V_ALW
12
12
4700p240K
4700p130K
4700p
4700p4.3K
FAN1_PWM
FAN1_TACH
10U_0603_6.3V6M
12
CE32
REM_DIODE1_P <32>
REM_DIODE1_N <32>
C
E
3 1
LMBT3904WT1G SC70-3
LA-E122P
LA-E122P
LA-E122P
4
RE300
240K_0402_5%
CE47
4700P_040 2_25V7K
PANEL SIZE
12"
14"
15"
17"
FAN1_PWM <32>
FAN1_TACH <32>
+5V_RUN
RB751S40T1G_SOD523-2
@
DE1
2 1
2
B
QE5
VCCST_PWRGD <11,14,32>
REM_DIODE2_P <32>
REM_DIODE2_N <32>
33 59We dnesday, November 09, 2016
33 59We dnesday, November 09, 2016
33 59We dnesday, November 09, 2016
IMVP_VR_ON
IMVP_VR_ON <47>
RUN_ON <17,32,40,45>
PANEL_ID rise time is measured from 5%~68%.
JFAN1
1
2
3
4
GND1
GND2
CONN@
Place under CPU
Place CE35 close to the QE3 as possible
100P_0402_50V8J
CE35@
1 2
DP2/DN2 for WiGig on QE5, place QE5 close
to WiGig and CE37 close to QE5
DN2a/DP2a for DDR on QE7, place QE7 close
to DDR and CE46 close to QE7
100P_0402_50V8J
E
31
12
QE7
CE46@
C
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
1.0
1.0
1.0
5
4
3
2
1
For NUVOTON TPM
@
1 2
+3.3V_RUN
D D
TPM_PIRQ#
33_0402_5%
33_0402_5%
TPM_PIRQ#<9>
33_0402_5%EMI@
PLTRST_TPM#<11>
@
T283
+3.3V_M_TPM+3.3V_ALW_PCH
+3.3V_RUN
12
RZ362
@
10K_0402_5%
PCH_SPI_D1_2_R
PCH_SPI_D0_2_R
PCH_SPI_CLK_2_R
PCH_SPI_CS#2_R
PAD~D
10K_0402_5%
12
RZ62
PCH_SPI_CS#2_R
UZ12
29
GPIO0/SDA/XOR_OUT
30
TPM_LPM#
TPM_GPIO4
@
RZ113 100_0402_5%
GPIO1/SCL
3
GPIO2/GPX
6
GPIO3/BADD
24
LAD0/MISO
21
LAD1/MOSI
18
LAD2/SPI_IRQ#
15
LAD3
19
LCKL/SCLK
20
LFRAME#/SCS#
17
LRESET#/SPI_RST#/SRESET#
27
SERIRQ
13
CLKRUN#/GPIO4/SINT#
28
LPCPD#
4
PP
5
TEST
NPCT650VB2YX_QFN32_5X5
1 2
RZ113 RZ111
1K MMBT3906
1K
100
10K
+3.3V_M_TPM
S
3
G
2
D
1
POP
LP2301A
Reserved
LP2301ALT1G_SOT23-3
@
QZ9
TPM_LPM#
PJP391
1 2
PAD-OPEN1x1m
+3.3V_M_TPM
1 2
RZ69 10K_0402_5%
1 2
@
RZ112 0_0402_5%
1 2
@
RZ363 0_0402_5%
1 2
RZ58
1 2
RZ59
1 2
RZ60
@
1 2
RZ61 0_0402_5%
PCH_SPI_CLK_R1<8>
SIO_SLP_S0#<11,17,45>
PCH_SPI_D1_R1<8>
PCH_SPI_D0_R1<8>
PCH_SPI_CS#2<8>
PCH_SPI_CLK_2_R
33_0402_5%
RZ63
0.1U_0402_25V6
1 2
12
@EMI@
@EMI@
CZ56
C C
B B
A A
RZ89 0_0402_5%
+3.3V_ALW
1
VSB
8
VDD
14
VHIO
22
VHIO
2
NC
7
NC
10
NC
11
NC
25
NC
26
NC
31
NC
9
GND
16
GND
23
GND
32
GND
33
PGND
12
12
@
RZ111
10K_0402_5%
1
2
+UZ12_TPM
0.1U_0201_10V6K
1
CZ51
2
+UZ12_TPM
4.7U_0402_6.3V6M
1
CZ75
2
10U_0603_10V6M
place CZ51,CZ52 as close as UZ12.1
CZ52
0.1U_0201_10V6K
1
2
CZ53,CZ55 as close as UZ12.14
CZ54 as close as UZ12.22
place CZ50, CZ75 as close as UZ12.8
0.1U_0201_10V6K
1
CZ50
2
+3.3V_M_TPM
0.1U_0201_10V6K
10U_0603_10V6M
1
1
CZ53
CZ54
CZ55
2
2
PCH_PLTRST#_AND<11,29,30,35>
+PWR_SRC
RF Request
USH_SMBCLK
CZ62 68P_0402_50V8J
@RF@
USH_SMBDAT
CZ63 68P_0402_50V8J
@RF@
RF Request RF Request
+3.3V_ALW +3.3V_M_TPM
12P_0402_50V8J
68P_0402_50V8J
RF@
RF@
1
1
CZ57
CZ58
2
2
+3.3V_ALW
1 2
RZ8 4.7K_0402_5%
1 2
RZ9 4.7K_0402_5%
1 2
RZ10 100K_0402_5%
@
1 2
RZ85 0_0402_5%
1 2
RZ114 0_0402_5%
@
@
1 2
USH_DET#<32>
PCH_PLTRST#_AND
ESD@
.047U_0402_16V7K
12
CZ61
For ESD solution
1 2
1 2
RZ87 0_0402_5%
@
RB751S40T1G_SOD523-2
BCM5882_ALERT#<32>
USH_PWR_STATE#<33>
CONTACTLESS_DET#<12>
DZ7
USH_SMBCLK
USH_SMBDAT
USH_PWR_STATE#
CV2_ON<32>
POA_WAKE#<32>
EC_FPM_EN<32>
USB20_N10<10>
USB20_P10<10>
USH_SMBCLK<32>
USH_SMBDAT<32>
+3.3V_ALW
+5V_ALW
+3.3V_RUN
+5V_RUN
12
+5V_ALW
0.1U_0201_10V6K
1
CZ64
2
RF@
68P_0402_50V8J
1
CZ69
2
12P_0402_50V8J
RF@
1
CZ59
2
+PWR_SRC_R
@
68P_0402_50V8J
RF@
1
CZ60
2
USH_RST#_R
USH_DET#_R
Close to JUSH1
USH CONN
JUSH1
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
GND1
28
GND2
CVILU_CF5026FD0RK-05-NH
Update to LTCX007Q600 (DVT1.0)
+3.3V_ALW+3.3V_RUN+5V_RUN
0.1U_0201_10V6K
0.1U_0201_10V6K
1
1
@
CZ66
2
2
RF@
68P_0402_50V8J
1
1
CZ71
2
2
0.1U_0201_10V6K
1
@
@
CZ67
CZ68
2
+3.3V_ALW+3.3V_RUN+5V_RUN+5V_ALW
RF@
68P_0402_50V8J
RF@
68P_0402_50V8J
1
CZ72
CZ73
2
RF Request
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
USH & TPM
USH & TPM
USH & TPM
LA-E122P
LA-E122P
LA-E122P
34 59Wednesday, November 09, 2016
34 59Wednesday, November 09, 2016
34 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
4
3
2
1
For Brekenridge 12/14/15 UMA/Steamboat
RF Request
D D
+3.3V_HDD_M2
68P_0402_50V8J
@RF@
1
CN60
2
+3.3V_HDD_M2
0.1U_0201_10V6K
@
CN61
1
2
0.1U_0201_10V6K
22U_0603_6.3V6M
CN62
1
2
22U_0603_6.3V6M
12
12
CN63
CN64
2280 SSD
NGFF slot C Key M
Place near HDD CONN
2.8A
PJP31
@
1 2
PAD-OPEN1x3m
M2280_DEVSLP <10>
PCH_PLTRST#_AND <11,29,30,34>
CLKREQ_PCIE#3 <11>
PCIE_WAKE# <30,33>
1 2
+3.3V_RUN
SATALED# <10,30,39>
SUSCLK <11,30>
NVME_LED#
RN100 0_0402_5%@
PCIE_WAKE#
SUSCLK_R
+3.3V_HDD_M2
1 2
@
RN99 0_0402_5%
JNGFF3
CONN@
1
GND
3
GND
5
PERn3
7
PERp3
9
GND
+3.3V_HDD_M2
M2280_DEVSLP
1 2
C C
B B
RN37@ 10K_0402_5%
PCIE_PRX_DTX_N11<10>
PCIE_PRX_DTX_P11<10>
PCIE_PTX_DRX_N11<10>
PCIE_PTX_DRX_P11<10>
PCIE_PRX_DTX_P12<10>
PCIE_PRX_DTX_N12<10>
PCIE_PTX_DRX_N12<10>
PCIE_PTX_DRX_P12<10>
if signal is PCIE GEN3/SATA GEN3 maybe change C value
or no need for DG0.9 SATA EXPRESS HDD
CLK_PCIE_N3<11>
CLK_PCIE_P3<11>
M2280_PCIE_SATA#<10>
PCIE_PTX_C_DRX_N11
PCIE_PTX_C_DRX_P11
PCIE_PTX_C_DRX_N12
PCIE_PTX_C_DRX_P12
12
CN69 0.22U_0402_10V6K
12
CN70 0.22U_0402_10V6K
12
CN71 0.22U_0402_10V6K
12
CN72 0.22U_0402_10V6K
11
PETp3
13
PETn3
15
GND
17
PERn2
19
PERp2
21
GND
23
PETp2
25
PETn2
27
GND
29
PERn1
31
PERp1
33
GND
35
PETn1
37
PETp1
39
GND
41
PERn0/SATA-B+
43
PERp0/SATA-B-
45
GND
47
PETn0/SATA-A-
49
PETp0/SATA-A+
51
GND
53
REFCLKN
55
REFCLKP
57
GND
67
N/C
69
PEDET (OC-PCIe/GND-SATA)
71
GND
73
GND
75
GND
77
GND
LOTES_APCI0170-P001A
SUSCLK(32kHz) (O)(0/3.3V)
3.3VAUX
3.3VAUX
DAS/DSS#
3.3VAUX
3.3VAUX
3.3VAUX
3.3VAUX
DEVSLP
PERST#
CLKREQ#
PEWake#
3.3VAUX
3.3VAUX
3.3VAUX
GND
2
4
6
N/C
8
N/C
10
12
14
16
18
20
N/C
22
N/C
24
N/C
26
N/C
28
N/C
30
N/C
32
N/C
34
N/C
36
N/C
38
40
N/C
42
N/C
44
N/C
46
N/C
48
N/C
50
52
54
56
N/C
58
N/C
68
70
72
74
76
Link DC04000LI00 DONE
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
M2 2280 Socket
M2 2280 Socket
M2 2280 Socket
LA-E122P
LA-E122P
LA-E122P
35 59Wednesday, November 09, 2016
35 59Wednesday, November 09, 2016
35 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
4
3
2
1
+5V_USB_CHG_PWR
DI4
D D
C C
+5V_ALW
RI13
USB3_PRX_DTX_N1<10>
USB3_PRX_DTX_P1<10>
USB3_PTX_DRX_N1<10>
USB3_PTX_DRX_P1<10>
ILIM_SEL
12
10K_0402_5%
12
CI13 0.1U_0402_25V6
12
CI16 0.1U_0402_25V6
USB20_N1<10>
USB20_P1<10>
USB_OC0#<10>
USB_PWR_SHR_VBUS_EN<32>
USB_PWR_SHR_LFT_EN#<32>
ILIM_SEL
+5V_ALW
1
2
3
13
4
5
6
7
8
SA000097E10 Link Done
USB3_PRX_DTX_N1 USB3_PRX_DTX_N1
USB3_PRX_DTX_P1
USB3_PTX_C_DRX_N1
USB3_PTX_C_DRX_P1
VOUT
DP_IN
DM_IN
ILIM_L
ILIM_HI
GND
12
10
11
15
16
9
NC
14
17
+5V_USB_CHG_PWR
UI3
VIN
DM_OUT
DP_OUT
FAULT#
ILIM_SEL
EN
CTL1
CTL2
CTL3
Thermal Pad
SLGC55544CVTR_TQFN16_3X3
ESD@
1
1
2
2
4
4
5
3
3
8
L05ESDL5V0NA-4_SLP2510P8-10-9
SW_USB20_P1
SW_USB20_N1
RI14
12
22.1K_0402_1%
9
10
8
9
7
7
6
65
USB3_PRX_DTX_P1
USB3_PTX_C_DRX_N1
USB3_PTX_C_DRX_P1
SW_USB20_N1
SW_USB20_P1
LI7
EMI@
1 2
EXC24CQ900U_4P
150U_B2_6.3VM_R35M
@
1
CI32
+
2
34
1
2
100U_1206_6.3V6M
CI14
USB20_N1_R
USB20_P1_R
0.1U_0201_10V6K
CI17
1
2
3
1
1
AZC199-02SPR7G_SOT23-3
ESD@
223
DI5
USB20_N1_R
USB20_P1_R
USB3_PRX_DTX_N1
USB3_PRX_DTX_P1
USB3_PTX_C_DRX_N1
USB3_PTX_C_DRX_P1
JUSB1
CONN@
1
VBUS
2
D-
3
D+
4
GND
5
SSRX-
6
SSRX+
7
8
9
GND
GND
GND
SSTX-
GND
SSTX+
GND
ACON_TCRA2-9U1U93
LINK DC231604011 DONE
RF Request
+5V_USB_CHG_PWR
RF@
RF@
68P_0402_50V8J
12P_0402_50V8J
1
1
CI44
CI43
2
2
10
11
12
13
B B
A A
+5V_ALW
47U_0603_6.3V6M
47U_0603_6.3V6M
@
1
1
CI34
2
2
@
CI33
Place near UI3.1
10U_0402_6.3V6M
0.1U_0201_10V6K
@
1
2
CI19
1
CI31
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
JUSB1+PS
JUSB1+PS
JUSB1+PS
LA-E122P
LA-E122P
LA-E122P
36 59Wednesday, November 09, 2016
36 59Wednesday, November 09, 2016
36 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
USB3_PRX_DTX_N3<10>
USB3_PRX_DTX_P3<10>
USB3_PTX_DRX_N3<10>
USB3_PTX_DRX_P3<10>
D D
C C
4
12
CI5 0.1U_0402_25V6
12
CI4 0.1U_0402_25V6
3
DI1
USB3_PRX_DTX_N3 USB3_PRX_DTX_N3
USB3_PRX_DTX_P3 USB3_PRX_DTX_P3
USB3_PTX_C_DRX_N3 USB3_PTX_C_DRX_N3
USB3_PTX_C_DRX_P3 USB3_PTX_C_DRX_P3
USB20_P2<10>
USB20_N2<10>
USB20_P2
USB20_N2
DFB request:
main SM070003Z00 (INPAQ_MCM1012B900F06BP_4P)
Footprint use 2nd source SM070004400 (PANAS_EXC24CQ900U_4P)
Pitch change from 0.5mm to 0.55mm
ESD@
1
1
2
2
4
4
5
3
3
8
L05ESDL5V0NA-4_SLP2510P8-10-9
1 2
10
9
7
65
EXC24CQ900U_4P
LI3
EMI@
9
8
7
6
34
USB20_P2_R
USB20_N2_R
2
1
For Breckenridge/Steamboat 12&Kirkwood
+USB_EX2_PW R
+5V_ALW
12
RF Request
RF@
12P_0402_50V8J
1
1
CI45
2
2
0.1U_0201_10V6K
10U_0603_10V6M
CI7
@
1
CI6
2
RF@
68P_0402_50V8J
Part Reference
+USB_EX2_PWR
100U_1206_6.3V6M
12
CI1
USB_PWR_EN1#<32>
JUSB2
CONN@
1
USB20_N2_R
223
1
1
USB20_P2_R
USB3_PRX_DTX_N3
USB3_PRX_DTX_P3
AZC199-02SPR7G_SOT23-3
USB3_PTX_C_DRX_N3
ESD@
USB3_PTX_C_DRX_P3
DI2
0.1U_0201_10V6K
CI3
1
3
2
VBUS
2
D-
3
D+
4
GND
5
SSRX-
6
SSRX+
7
GND
8
SSTX-
9
SSTX+
ACON_TCRA2-9U1U93
GND
GND
GND
GND
10
11
12
13
LINK DC231604011 DONE
+USB_EX2_PWR
UI1
1
OUT
5
IN
2
GND
4
EN
3
OCB
SY6288D20AAC_SOT23-5
USB_OC1# <10>
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
JUSB2
JUSB2
JUSB2
LA-E122P
LA-E122P
LA-E122P
1
37 59Wednesday, November 09, 2016
37 59Wednesday, November 09, 2016
37 59Wednesday, November 09, 2016
1.0
1.0
1.0
5
4
3
2
1
RF Request
Touch Pad
+3.3V_TP
4.7K_0402_5%
4.7K_0402_5%
12
12
RZ18
D D
DAT_TP_SIO_I2C_CLK<32>
CLK_TP_SIO_I2C_DAT<32>
10P_0402_50V8J
10P_0402_50V8J
12
12
CZ80
CZ81
RZ22 0_0402_5%
@
RZ23 0_0402_5%
@
@
RZ346 0_0402_5%
@
RZ347 0_0402_5%
PS2
12
12
1 2
1 2
I2C From EC
+3.3V_TP +3.3V_TP
2.2K_0402_5%
2.2K_0402_5%
12
12
RZ20
C C
I2C1_SDA_TP<9>
I2C1_SCK_TP<9>
RZ21
@
RZ26 0_0402_5%
@
RZ29 0_0402_5%
1 2
1 2
RZ19
DAT_TP_SIO_R
CLK_TP_SIO_R
I2C1_SDA_TP_R
I2C1_SCK_TP_R
I2C1_SDA_TP_R
I2C1_SCK_TP_R
10K_0402_5%
10K_0402_5%
12
12
@
RZ116
+3.3V_RUN +3.3V_TP
@
RZ117
PJP35
@
1 2
PAD-OPEN1x1m
Keyboard
BC_INT#_ECE1117<32>
BC_DAT_ECE1117<32>
BC_CLK_ECE1117<32>
KB_DET#<12>
+5V_RUN
+3.3V_ALW
+3.3V_TP
TOUCHPAD_INTR#<12,32>
Reserve for future use
KB_DET#
BC_INT#_ECE1117
BC_DAT_ECE1117
BC_CLK_ECE1117
DAT_TP_SIO_R
CLK_TP_SIO_R
I2C1_SDA_TP_R
I2C1_SCK_TP_R
I2C From CPU
+3.3V_TP
1
CZ83
RF@
68P_0402_50V8J
2
CVILU_CF5020FD0RK-05-NH
22
GND
21
GND
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
CONN@
JKBTP1
CHECK PIN DEFINE
Update to LTCX007Q500 (DVT1.0)
+5V_RUN+3.3V_ALW+3.3V_TP
0.1U_0201_10V6K
0.1U_0201_10V6K
1
@
CZ90
2
0.1U_0201_10V6K
1
1
@
CZ91
2
2
Place close to JKBTP1
@
CZ92
Plan is for I2C to be driven by the EC for Win7 and Pre-OS (will utilize Intel I2C drivers for Win7)
For Win8.1 and 10 the EC will control TP over I2C Pre-OS and then the PCH will drive I2C when in Windows
Route PS2 from EC to the touch pad also for contingency plan if I2C has issues
B B
RSMRST circuit
+3.3V_ALW
@
CZ82
1 2
0.1U_0201_10V6K
5
1
PCH_RSMRST#<32>
ALW_PWRGD_3V_5V<42>
A A
P
B
2
A
G
3
4
O
UZ6
TC7SH08FU_SSOP5~D
PCH_RSMRST#_AND <11,14>
EDP Cable nonTS_HD/FHD-HD Cam@
Part Number
DC02C00E000 H-CONN SET 1S5 MB-LCD-CAMERA NTS FHD
EDP Cable nonTS_FHD-IR@
Part Number
DC02C00E100 H-CONN SET 1S5 MB-LCD-CAMERA-IR NTS FHD
EDP Cable TS_TS-FHD-HD Cam@
Part Number
DC02C00E200 H-CONN SET 1S5 MB-LCD-CAMERA-TS FHD
Description
Description
Description
LED Cable@
Part Number
DC02002LT00 H-CONN SET 1S5 MB-LED/B
FP FFC@
Part Number
NBX00023000 FFC 12P F P0.5 PAD=0.3 56MM MB-FP 1S5
TP FFC@
Part Number
NBX00022Y00 FFC 20P F P0.5 PAD=0.3 92MM MB-TP 1S5
USH Board FFC@
Part Number
NBX00022Z00 FFC 26P F P0.5 PAD=0.3 81.6MM MB-USH 1S5
RTC BATT@
Part Number
GC02001DS00 BATT CR2032 3V 225MAH PA 5 W/C 30MM
@FAN
Part Number Description
@Speak
Part Number Description
FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
DC28A000800
SPK PACK ZJX 2.0W 4 OHM FG
PK230003Q0L
Description
Description
Description
Description
Description
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Keyboard
Keyboard
Keyboard
LA-E122P
LA-E122P
LA-E122P
38 59Wednesday, November 09, 2016
38 59Wednesday, November 09, 2016
38 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
4
3
2
1
means EC can swi tch battery white led and HDD LED by hot ke y “Fn+H”
SATA_LED_EN<33>
D D
SATALED#<10,30,35>
BAT2_LED#<32,39>
HDD LED MUX
5
BAT2_LED#_R
34
QZ2B
@
DMN65D8LDW-7_SOT363-6
+3.3V_ALW
2
61
QZ2A
@
DMN65D8LDW-7_SOT363-6
BAT2_LED#_R
2
R1=10K/R2=10K
Change back to SB000002T00 4/25
DDTA144VCA-7-F_SOT23-3
QZ3
@
1 3
1 2
RZ25 150_0402_5%@
BATT_WHITE#
Battery LED
BAT2_LED#<32,39>
BAT1_LED#<32>
1 2
RZ361 100_0402_5%
1 2
RZ28 330_0402_5%
LED P/N change to SC50000FL00 from SC50000BA00
BATT_WHITE#
BATT_YELLOW#
Breath LED
QZ7B
C C
+3.3V_ALW
@
CZ93
1 2
0.1U_0201_10V6K
5
1
SYS_LED_MASK#<28,32>
LID_CL#<33,39>
B
2
A
P
MASK_BASE_LEDS#
4
O
G
UZ10
TC7SH08FU_SSOP5~D
3
BREATH_LED#<32>
DMN65D8LDW-7_SOT363-6
BREATH_LED#_Q BREATH_WHITE_LED_SNIFF#
34
5
MASK_BASE_LEDS#
1 2
RZ32 330_0402_5%
POWER & INSTANT ON SWITCH
SW3
1
POWER_SW#_M B<11,33>
B B
2
4
SKRBAAE010_4P
3
LTW-C193DC-C_WHITE
Place LED3 close to SW3
LED board CONN
BATT_YELLOW#
BATT_WHITE#
LID_CL#<33,39>
+3.3V_ALW
+5V_ALW
LED3
21
+5V_ALW
JLED1
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
ACES_50209-0060N-P01
Fiducial Mark
FD1@
1
FIDUCIAL MARK~D
FD2@
1
FIDUCIAL MARK~D
FD3@
1
FIDUCIAL MARK~D
FD4@
1
FIDUCIAL MARK~D
A A
Mask All LEDs (Unobtrusive mode)
Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened) 11
H1@
H2@
H_3P4
H3@
H_3P4
H_3P4
H_3P4
1
1
1
LED Circuit Control Table
H5@
H6@
H4@
H_1P0N
H_1P0N
1
1
SYS_LED_MASK# LID_CL#
0
1 0
H8@
H7@
H_3P2
1
1
H_3P2
H25@
H_3P2
1
1
H23@
H_2P6
1
H_3P2
H_2P6
X
FANCPU NGFF
H26@
H10@
H12@
H9@
H_2P6
1
1
H14@
H24@
H_2P6
1
1
H_3P8
H_2P6
H_2P6
H_3P5
1
1
H27@
H15@
H_3P5
H_3P5
1
1
H20@
H29@
H16@
H_3P1
H_3P1
H_2P6
1
1
1
H18@
H28@
H_2P6
H_2P6
1
1
H39@
H37@
H38@
H_2P6
1
1
H33@
1
H_2P3N
H21@
H22@
H_3P5
H_3P5
1
1
1
H30@
H_2P3X2P7N
1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PAD, LED
PAD, LED
PAD, LED
LA-E122P
LA-E122P
LA-E122P
1
39 59Wednesda y, November 09, 2016
39 59Wednesda y, November 09, 2016
39 59Wednesda y, November 09, 2016
1.0
1.0
1.0
5
4
3
2
1
+3.3V_ALW
SIO_SLP_WLAN#<11,32>
D D
AUX_EN_WOWL<32>
1 2
RZ38 100K_0402_5%
1 2
RZ71 0_0402_5%
@
1 2
@
RZ70 0_0402_5%
+5V_ALW
SIO_SLP_LAN#<11,32>
AUX_EN_WOWL
UZ2
1
VIN1
VOUT1
2
VIN1
VOUT1
3
ON1
4
VBIAS
5
ON2
6
VIN2
VOUT2
VIN27VOUT2
GPAD
EM5209VF_SON14_2X3
GND
CT1
CT2
+3.3V_WLAN_UZ2
14
13
12
11
10
9
+3.3V_LAN_UZ2
8
15
1 2
PAD-OPEN1x2m
1 2
CZ122 0.1U_0201_10V6K
1 2
CZ109 470P_0402_50V7K
1 2
CZ110 470P_0402_50V7K
1 2
CZ111 0.1U_0201_10V6K
@
1 2
PAD-OPEN1x1m
PJP37
+3.3V_WLAN
+3.3V_LAN
1A
2A
PJP36
@
+1.8V_RUN source+3.3V_WLAN/+3.3V_LAN source
RUN_ON<17,32,33,40,45>
Reserve R/C for Audio power sequence, +5V->+3.3V->+1.8V
1 2
@
RZ345 0_0402_5%
@
CZ197
470P_0402_50V7K
+5V_ALW
12
+1.8V_PRIM
UZ8
1
VOUT
VIN
2
VOUT
VIN
3
ON
4
VBIAS
AOZ1336_DFN8_2X2
GND
GND
CT
7
+1.8V_RUN_UZ8
8
6
5
9
0.013A
PJP42
@
1 2
PAD-OPEN1x1m
1 2
CZ120 0.1U_0201_10V6K
1 2
CZ121 470P_0402_50V7K
+1.8V_RUN
+3.3V_ALW_PCH/+3.3V_RUN source
0.63A
PJP38
@
1 2
+3.3V_ALW
C C
1 2
RZ65 0_0402_5%
PCH_ALW_ON<32>
SIO_SLP_SUS#<11,17,32,44,45,46>
@
@
1 2
RZ64 0_0402_5%
+5V_ALW
RUN_ON
UZ3
1
VIN1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
VIN27VOUT2
EM5209VF_SON14_2X3
VOUT1
VOUT1
GND
VOUT2
GPAD
CT1
CT2
+3.3V_ALW_PCH_UZ3
14
13
12
11
10
9
+3.3V_RUN_UZ3
8
15
PAD-OPEN1x1m
1 2
CZ112 0.1U_0201_10V6K
1 2
CZ113 470P_0402_50V7K
1 2
CZ114 1000P_0402_50V7K
1 2
CZ115 0.1U_0201_10V6K
1 2
PAD-OPEN1x3m
+3.3V_ALW_PCH
PJP39
@
+3.3V_RUN
3.435A
+5V_RUN/+3.3V_WWAN source
B B
@
PJP40
CZ116 0.1U_0201_10V6K
CZ117 470P_0402_50V7K
CZ118 470P_0402_50V7K
CZ119 0.1U_0201_10V6K
@
1 2
+3.3V_WWAN_UZ4
1
RF@
2200P_0402_50V7K
2
1 2
PAD-OPEN1x2m
1 2
1 2
1 2
1 2
PJP41
PAD-OPEN1x3m
CZ124
+5V_ALW
RUN_ON<17,32,33,40,45>
3.3V_WWAN_EN
3.3V_WWAN_EN
+3.3V_ALW
3.3V_WWAN_EN<32>
1 2
RZ40 100K_0402_5%
A A
UZ4
1
VIN1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
VIN27VOUT2
EM5209VF_SON14_2X3
VOUT1
VOUT1
GND
VOUT2
GPAD
CT1
CT2
14
13
12
11
10
+3.3V_WWAN_UZ4
9
8
15
+5V_RUN_UZ4
RF Request
5
4
2A
+5V_RUN
+3.3V_WWAN
2.5A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Power control
Power control
Power control
LA-E122P
LA-E122P
LA-E122P
1
40 59Wednesday, November 09, 2016
40 59Wednesday, November 09, 2016
40 59Wednesday, November 09, 2016
1.0
1.0
1.0
5
4
3
2
1
+COINCELL
COIN RTC Battery
12
PR2
PD3
12
34
PQ1B
3
1
PBAT_PRES# <32,50>PBAT_CHARGER_SMBCLK <32,50>
PR17
100K_0402_5%
5
1K_0402_5%
+Z4012
2
PS_ID <32>
+RTC_CELL
1
PC3
1U_0603_25V6K
2
PR25
@
1 2
0_0402_5%
+COINCELL
+3.3V_VDD_DCIN
+3.3V_RTC_LDO
D D
2
100K_0402_1%
15K_0402_1%
12
PR14
100K_0402_5%
1
PD2
EMC@
TVNST52302AB0_SOT523-3
3
PBAT_CHARGER_SMBDAT <32,50>
PR6
1 2
PR8
1 2
+DC_IN_SS
12
PC8
10U_0805_25V6K
PBATT+_C
PR3
@
1 2
0_0402_5%
D
S
1 3
PQ2
FDV301N-G_SOT23-3
G
2
C
2
PQ3
B
MMST3904-7-F_SOT323~D
E
3 1
S SCH DIO 5A 100V 15UA 0.88V TO227-3
PL1
EMC@
FBMJ4516HS720NT_2P
1 2
PL2
EMC@
FBMJ4516HS720NT_2P
1 2
+PBATT
+3.3V_ALW
12
PR1
100K_0402_5%
BAS40CW SOT-323
+3.3V_ALW
PR4
PR5
33_0402_5%
1 2
2.2K_0402_5%
1 2
+5V_ALW
12
PR7
10K_0402_1%
PD5
2
1
3
PQ4
AON7409_DFN8-5
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE IN FORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTR ONICS, INC.
3
1
2
35
4
12
PR16
49.9K +-1% 0402
PR20
@
13
D
0_0402_5%
2
1 2
PQ7
G
S
DMN65D8LW-7_SOT323-3
+SDC_IN
+SDC_IN
12
12
PC4
12
PR11
0.022U_0603_50V7K
499K +-1% 0402
12
PR24
100K_0402_5%
PR10
300K +-5% 0402
PQ5
S
G
2
12
D
1 3
PR15
100K_0402_5%
AO3409 P-CHANNEL SOT-23
61
2
PQ1A
DMN65D8LDW-7_SOT363-6
VBUS2_ECOK <33,51>
PR19
@
0_0402_5%
1 2
+3.3V_VDD_DCIN
DMN65D8LDW-7_SOT363-6
2
1
PD1
EMC@
TVNST52302AB0_SOT523-3
2
Primary Battery Connector
PBATT1
@
1
1
2
2
3
3
4
4
5
5
12
PC1
EMC@
2200P_0402_50V7K
C C
6
6
7
7
8
8
9
9
10
10
11
GND
12
GND
DEREN_40-42251-01001RHF
PBAT_SMBCLK_C
PBAT_SMBDAT_C
PBAT_PRES#_C
GND
NB_PSID PS_ID
2
3
1
PRP1
100_0804_8P4R_5%
EMC@
BLM15AG102SN1D_2P
PD4
EMC@
PESD5V0U2BT_SOT23-3
+DC_IN
PL4
EMC@
FBMJ4516HS720NT_2P
1 2
B B
PJPDC1
@
7
GND
6
GND
-DCIN_JACK-DCIN_JACK
5
5
4
4
+DCIN_JACK
3
3
2
2
1
1
CVILU_CI0805M1HRC-NH
PR26
@
1 2
DCIN2_EN<33>
A A
0_0402_5%
PR28
5
PC7 can't over 1000P
12
PC5
EMC@
1000P_0603_50V7K
ACAV_IN_NB<32,50,51>
PQ8
DMN65D8LW-7_SOT323-3
D
S
13
G
2
12
1 2
100K_0402_5%
+3.3V_ALW
PC7
@EMC@
0_0402_5%
12
0.1U_0603_25V7K
PR29
@
12
PR13
4.7K_0805_5%
@
0.1U_0402_10V7K
PR21
@
0_0402_5%
1 2
1 2
@
0_0402_5%
12
PR27
100K_0402_5%
+3.3V_VDD_DCIN
PR22
PC9
12
1
B
2
A
+3.3V_VDD_DCIN
5
P
G
3
PC6
1 2
0.022U_0603_50V7K
PU1
MC74VHC1G08DFT2G SC70 5P AND
1 2
4
O
0_0402_5%
4
3
18
27
36
45
PL3
12
DC_IN+ Source
S1 S2
PQ9
AON7409_DFN8-5
1
2
3 5
4
12
PR12
499K +-1% 0402
12
13
PR23
@
2
G
PR18
49.9K +-1% 0402
D
PQ6
S
DMN65D8LW-7_SOT323-3
12
PC2
JRTC1
@
EMC@
2200P_0402_50V7K
1
3
1
G
4
22G
ACES_50271-0020N-001
+DC_IN
2
1
1U_0603_50V6K
1
PC11
2
12
PC10
2.2U 10V M X5R 0402
AC_DISC# <32,51>
PU2
VIN
3
VOUT
GND
AP2204RA-3.3TRG1_SOT89-3
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+DCIN
+DCIN
+DCIN
LA-E121P
LA-E121P
LA-E121P
1
41 59Wednesday, November 09, 2016
41 59Wednesday, November 09, 2016
41 59Wednesday, November 09, 2016
1.0
1.0
1.0
A
1 1
+PWR_SRC
PJP100
21
PAD-OPEN 1x2m~D
PC100
EMC@
100P 50V J NPO 0402
2 2
+3.3V_ALW
12
PC103
EMC@
100P 50V J NPO 0402
PR107
100K_0402_5%
1 2
PGOOD_3V
12
3V_VIN
PC105
12
PC104
10U_0805_25V6K
10U_0805_25V6K
B
BST_3V
2
EN112EN2
IN3IN4IN
FF13OUT14NC
3V_FB
1
IN
BS
20
LX
19
LX
18
GND
17
LDO
16
NC
21
GND
15
PC113
1000P_0402_50V7K
1 2
12
PR108
1K_0402_5%
1 2
1 2
PC111
4.7U_0603_6.3V6K
5
12
LX_3V
3V5V_EN
PU100
6
LX
7
GND
8
GND
SY8288BRAC_QFN20_3X3
9
PG
10
NC
11
ENLDO_3V5V
C
PR100
@
0_0603_5%
1 2
@
0_0402_5%
1 2
PR105
@
0_0402_5%
LX_3V
PR104
PC102
1 2
0.1U_0603_25V7K
+3.3V_ALW2
+3.3V_RTC_LDO
3.3V LDO 150mA~300mA
PGOOD_3V
PGOOD_5V
PL100
1.5UH +-20% 9A 7X7X3 MOLDING, A.7
1 2
PR106
12
EMC@
4.7 +-5% 1206
3V_SN
12
PC112
EMC@
680P_0603_50V7K
D
PR119
@
0_0402_5%
1 2
1 2
PR120
@
0_0402_5%
PR102
ENLDO_3V5V
PR103
499K_0402_1%
1 2
12
499K_0402_1%
12
12
PC106
22UF_0805_6.3V6M
Vout is 3.234V~3.366V
ALW_PWRGD_3V_5V <38>
+PWR_SRC
+3.3V_ALWP
12
PC107
22UF_0805_6.3V6M
12
12
PC108
22UF_0805_6.3V6M
+3.3V_ALWP +3.3V_ALW
12
PC129
PC109
22UF_0805_6.3V6M
PC110
3VALWP
TDC 5.9 A
22UF_0805_6.3V6M
Peak Current 8.4 A
22UF_0805_6.3V6M
OCP Current 10.1A
PJP102
112
JUMP_43X118
2
E
+PWR_SRC
PJP101
21
PAD-OPEN 1x2m~D
3 3
RB520SM-30T2R_EMD2-2
@
PD100
2 1
ALWON<32>
4 4
1 2
PR114 0_0402_5%
@
12
5V_VIN
12
12
PC115
0.1U_0402_25V6
@EMC@
PR116
1M_0402_1%
+3.3V_ALW
12
PC116
2200P_0402_50V7K
@EMC@
3V5V_EN
PC128
4.7U_0402_6.3V6M
PC117
10U_0805_25V6K
12
PC118
10U_0805_25V6K
PR113
100K_0402_5%
1 2
12
PGOOD_5V
EN1 and EN2 dont't floating
LX_5V
10
5
PU102
6
LX
7
GND
8
GND
SY8288CRAC_QFN20_3X3
9
PG
NC
EN112EN2
11
3V5V_EN
ENLDO_3V5V
BST_5V
2
1
IN
IN3IN4IN
BS
LX
LX
GND
VCC
NC
GND
FF13OUT14LDO
15
+5V_ALW2
5V LDO 150mA~300mA
12
PC126
PC127
1000P_0402_50V7K
5V_FB
20
19
18
17
16
21
4.7U_0603_6.3V6K
1 2
PR111
@
0_0603_5%
1 2
LX_5V
PC119
1 2
4.7U_0603_6.3V6K
1K_0402_5%
1 2
PR117
PC114
1 2
0.1U_0603_25V7K
PL101
1.5UH +-20% 9A 7X7X3 MOLDING, A.7
1 2
12
PR112
@EMC@
4.7_1206_5%
5V_SN
12
PC125
@EMC@
680P_0603_50V7K
12
12
12
PC121
PC120
22UF_0805_6.3V6M
22UF_0805_6.3V6M
12
12
PC122
PC123
22UF_0805_6.3V6M
22UF_0805_6.3V6M
5VALWP
TDC 5.5 A
Peak Current 7.9 A
OCP Current 9.5 A
PJP103
112
JUMP_43X118
2
+5V_ALW+5V_ALWP
+5V_ALWP
12
PC130
PC124
22UF_0805_6.3V6M
22UF_0805_6.3V6M
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+5V_ALW/3.3V_ALW
+5V_ALW/3.3V_ALW
+5V_ALW/3.3V_ALW
LA-E121P
LA-E121P
LA-E121P
42 59Wednesday, November 09, 2016
42 59Wednesday, November 09, 2016
42 59Wednesday, November 09, 2016
E
1.0
1.0
1.0
5
D D
4
3
2
1
+PWR_SRC
C C
The current limit is
set to 8A, 12A or 16A
when this pin is pull
low, floating or pull
high
+1.2V_DDR OCP set 8A
B B
PJP202
PAD-OPEN 1x2m~D
21
12
PC200
10U_0805_25V6K
+3.3V_ALW
1 2
1 2
0.6V_DDR_VTT_ON<20>
12
PC201
@
PR205
0_0402_5%
ILMT_DDR
PR207
@
0_0402_5%
100P 50V J NPO 0402
100P 50V J NPO 0402
EMC@
EMC@
12
12
10U_0805_25V6K
SIO_SLP_S4#<11,17,32,46>
PC203
PC202
PR208
@
0_0402_5%
1 2
PR210
@
0_0402_5%
1 2
+3.3V_ALW
1U_0402_6.3V6K
12
PR209
1M_0402_5%
+1.2V_DDR_B+
PC206
2.2U_0402_6.3V6M
12
12
PC221
@
12
PC207
ILMT_DDR
EN_1.2V
EN_0.6V
12
0.1U_0402_10V7K
1M_0402_5%
12
PR212
PU200
10
IN
13
BYP
14
VCC
4
VTTGND
9
PGND
15
SGND
17
ILMT
1
S5
2
S3
SY8210AQVC_QFN19_4X3
0.1U_0402_10V7K
@
PC222
19
OT
18
PR203
PG
BS
LX
FB
VDDQSNS
VLDOIN
VTT
VTTSNS
VTTREF
Mode S3 S5 VOUT VTT
Normal H H on on
Stadby L H on off
Shutdown L L off off
@
0_0603_5%
1 2
12
11
16
8
7
6
5
3
LX_DDR
+1.2V_DDRP
PC205
1 2
0.1U_0603_16V7K
PC218
1U_0402_10V6K
12
EMC@
PR202
4.7_1206_5%
1 2
1 2
1UH +-20% 11A 7X7X3 MOLDING, A.2
PC209
22U_0603_6.3V6M
1 2
+0.6VSP
22U_0603_6.3V6M
12
PC219
EMC@
PC204
680P_0603_50V7K
1 2
PL201
330P_0402_50V7K
PC208
12
R1
R2
PJP200@
JUMP_43X118
112
+1.2V_DDR
TDC 6.5A
Peak Current 9.4A
OCP Current 11.2A
+1.2V_DDRP
102K_0402_1%
12
PR204
22U_0603_6.3V6M
22U_0603_6.3V6M
PC210
12
100K_0402_1%
12
PR206
2
PC211
12
12
22U_0603_6.3V6M
22U_0603_6.3V6M
PC213
PC212
12
JUMP_43X39
12
@
112
22U_0603_6.3V6M
PC214
PJP201
100P 50V J NPO 0402
EMC@
EMC@
100P_0402_50V8J
PC216
12
PC217
12
+0.6V_DDR_VTT+0.6VSP+1.2V_MEM+1.2V_DDRP
2
0.6Volt +/- 5%
TDC 0.007A
Peak Current 0.01A
OCP Current 2A (fix)
Note: S3 - sleep ; S5 - power off
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+1.2V_MEN/+0.6V_DDR_VTT
+1.2V_MEN/+0.6V_DDR_VTT
+1.2V_MEN/+0.6V_DDR_VTT
LA-E121P
LA-E121P
LA-E121P
43 59Wednesday, November 09, 2016
43 59Wednesday, November 09, 2016
43 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
4
3
2
1
D D
EN_+1VALWP
+PWR_SRC
C C
+3.3V_ALW
12
PR307
@
0_0402_5%
12
PR310
@
0_0402_5%
PAD-OPEN 1x2m~D
ILMT_+1VALWP
PJP301
21
12
12
PC301
100P 50V J NPO 0402
EMC@
+1.0V_PRIM
+1VALW P_B+
12
12
PC306
PC305
PC303
100P 50V J NPO 0402
EMC@
10U_0603_25V6M
10U_0603_25V6M
ILMT_+1VALWP
PU301
8
IN
EN
GND
ILMT
PG
BS
LX
FB
BYP
LDO
9
3
2
SYX196DQNC_QFN10_3X3
1
BST_+1VALWP
6
10
4
7
5
12
PC304
0.1U_0603_25V7K
1 2
SW_+1VALWP
12
PC313
4.7U_0603_6.3V6K
BST_+1VALWP_C
+3.3V_ALW
PC312
4.7U_0603_6.3V6K
PR304
@
0_0603_5%
1 2
12
1M_0402_1%
PR302
FB_+1VALWP
PR312
@
0_0402_5%
1 2
PR303
EMC@
4.7_1206_5%
1 2
PL301
0.68UH +-20% 7.9A 5X5X3 MOLDING, A.3
1 2
EMC@
SNB_+1VALWP
12
PR306
21.5K_0402_1%
12
PR311
31.6K_0402_1%
680P_0603_50V7K
SIO_SLP_SUS# <11,17,32,40,45,46>
+1VALWP
PC302
1 2
12
PC307
12
330P_0402_50V7K
PR308
1K_0402_5%
12
12
PC308
22U_0603_6.3V6M
PJP302
2
112
JUMP_43X118
+1.0V_PRIM
+1VALWP
12
12
PC309
22U_0603_6.3V6M
PC311
PC310
22U_0603_6.3V6M
22U_0603_6.3V6M
TDC 4.9A
Peak Current 7.1 A
B B
OCP Current 8.6A
TYP MAX
Choke DCR 11.0mohm , 12.0mohm
The current limit is set to 6A, 9A or 12A when this pin
is pull low, floating or pull high
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+1VALWP
+1VALWP
+1VALWP
LA-E121P
LA-E121P
LA-E121P
44 59Wednesday, November 09, 2016
44 59Wednesday, November 09, 2016
44 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
4
3
2
1
+3.3V_ALW
LPM LOGIC OUTPUT VOLTAGE
EN_1VS_VCCIO
13
PU401
EN
PVIN
PVIN
TPS62134CRGT_QFN16_3X3
AVIN
VID0
VID1
8
12
PR427
0_0402_5%
@
12
14
LPM
PR404
0_0402_5%
7
SS_1VS_VCCIO
12
@
PJP401
JUMP_43X79
2
+1VS_VCCIOP
12
PR421
0 +-5% 0402
1 2
112
PR422
@
0_0402_5%
12
12
PC407
PC406
22U_0603_6.3V6M
VCCIO_SENSE <17>
VSSIO_SENSE <17>
12
PC422
22U_0603_6.3V6M
22U_0603_6.3V6M
+1VS_VCCIOP +1.0VS_VCCIO
15
17
TP
PGND16PGND
1
VOS
2
SW
3
SW
4
PG
FBS5AGND6SS
PC410
470P_0402_50V7K
LX_1VS_VCCIO
+1VS_VCCIOP
PL402
1UH_1277AS-H-1R0N-P2_3.3A_30%
1 2
12
PR405
EMC@
4.7_0603_5%
SNUB_1VS_VCCIO
12
PC401
EMC@
470P_0402_50V7K
@
PR412
1 2
0_0402_5%
TPS62134C 1 0
+1VS_VCCIOP
PR425
@
0_0402_5%
PR403
1M_0402_1%
VIN_1VS_VCCIO
VID0_VCCIO
VID1_VCCIO
1 2
12
12
PC402
@
0.1U_0402_25V6
12
11
10
9
SIO_SLP_S0#<11,17,34,45>
PR402
@
0_0402_5%
RUN_ON<17,32,33,40>
D D
Vin=3~17V
+5V_ALW
+3.3V_ALW
12
@
10K_0402_1%
12
C C
10K_0402_1%
PR413
PR415
12
PR414
10K_0402_1%
12
PR416
@
10K_0402_1%
VID0_VCCIO
VID1_VCCIO
PJP403
1 2
PAD-OPEN1x1m
12
PC408
0.1U_0402_25V6
@EMC@
12
PC409
2200P_0402_50V7K
@EMC@
1 2
12
12
PC403
PC404
10U_0603_10V6M
10U_0603_10V6M
"R" for SILERGY
VID1 LOGIC
0
1
1
1
+1.0VS_VCCIO
TDC 1.9 A
Peak Current 2.7 A
OCP Current 3.3 A
TYP MAX
Choke DCR 48.0mohm
VID0 LOGIC
X
0
1
1
X
0
1
0
1 1.05
0(LPM)
0.80
0.95
1.00
+3.3V_ALW
12
PR410
PR426
@
0_0402_5%
SIO_SLP_S0#<11,17,34,45>
1 2
@
0_0402_5%
PR406
@
0_0402_5%
SIO_SLP_SUS#<11,17,32,40,44,46>
VID0_PRIM_CORE
VID1_PRIM_CORE
Vin=3~17V
+5V_ALW
PJP404
1 2
PAD-OPEN1x1m
12
PC417
0.1U_0402_25V6
@EMC@
CORE_VID0<18>
CORE_VID1<18>
PC418
@EMC@
B B
+3.3V_ALW
PR417
10K_0402_1%
PR419
@
10K_0402_1%
12
PR418
10K_0402_1%
12
PR420
@
10K_0402_1%
12
12
A A
1 2
12
12
PC412
PC413
10U_0603_10V6M
10U_0603_10V6M
12
2200P_0402_50V7K
PR407
1M_0402_1%
VIN_1V_PRIM
PR408
@
0_0402_5%
1 2
PR411
@
0_0402_5%
1 2
12
12
PC411
EN_1.0V_PRIM_COREP
@
0.1U_0402_25V6
13
15
14
PU402
EN
12
11
10
9
VID0_PRIM_CORE
LPM
PVIN
PVIN
TPS62134DRGT_QFN16_3X3
AVIN
VID0
VID1
8
VID1_PRIM_CORE
7
SS_1V_PRIM
12
17
PGND16PGND
12
PR428
PC420
@
1M_0402_1%
470P_0402_50V7K
+1.0V_PRIM_COREP +1.0V_PRIM_CORE
TP
1
VOS
SW
SW
PG
FBS5AGND6SS
+1.0V_PRIM_COREP
1UH_1277AS-H-1R0N-P2_3.3A_30%
LX_1V_PRIM
2
3
12
@
100K_0402_1%
12
SNUB_1V_PRIM
12
PR424
4
PL404
1 2
PR409
EMC@
4.7_0603_5%
PC419
EMC@
470P_0402_50V7K
PR423
@
0_0402_5%
1 2
Rup
"R" for SILERGY
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE IN FORMATION IT CONTAINS
5
4
3
PJP402
JUMP_43X79
112
2
+1.0V_PRIM_COREP
12
PC424
22U_0603_6.3V6M
PC416
PC415
22U_0603_6.3V6M
22U_0603_6.3V6M
+1.0V_PRIM_CORE
TDC 1.8 A
Peak Current 2.6 A
OCP Current 3.1 A
TYP MAX
Choke DCR 48.0mohm
TPS62134D 1 0
LPM LOGIC OUTPUT VOLTAGE
VID1 LOGIC
0
1
1
1
VID0 LOGIC
X
0
1
1
X
0
1
0
1 1.00
0.7(LPM)
0.85
0.90
0.95
12
12
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
+1VS_VCCIOP/+1.0V_PRIM_COREP
+1VS_VCCIOP/+1.0V_PRIM_COREP
+1VS_VCCIOP/+1.0V_PRIM_COREP
LA-E121P
LA-E121P
LA-E121P
1
45 59Wednesday, November 09, 2016
45 59Wednesday, November 09, 2016
45 59Wednesday, November 09, 2016
1.0
1.0
1.0
5
D D
SIO_SLP_SUS#<11,17,32,40,44,45>
C C
4
PC502
22U_0603_6.3V6M
1 2
PJP501
PR504
@
0_0402_5%
1M_0402_1%
1 2
PAD-OPEN1x1m
PR505
PR517
100K_0402_5%
12
+3.3V_ALW
+3.3V_ALW
1.8V_PRIM_PWRGD<32>
1 2
Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage
12
EN_1.8VALW
12
PC505
@
0.1U_0402_16V7K
VIN_1.8VALW
4
5
PU501
IN
LX
PG
GND
FB6EN
RT8097ALGE_SOT23-6
3
2
1
3
LX_1.8VALW
PJP502
PL501
1 2
PR502
PC506
PAD-OPEN1x1m
20K_0402_1%
FB_1.8VALW
PR506
10K_0402_1%
1 2
PR501
+1.8VALWP
Imax= 2A, Ipeak= 3A
FB=0.6V
1UH_1277AS-H-1R0N-P2_3.3A_30%
12
@EMC@
4.7_0603_5%
SNUB_1.8VALW
12
@EMC@
680P_0402_50V7K
Vout=0.6V* (1+Rup/Rdown)
12
Rup
12
Rdown
PC503
12
68P_0402_50V8J
+1.8V_PRIM
12
PC501
22U_0603_6.3V6M
+1.8V_PRIM
TDC 0.7 A
Peak Current 1.0 A
OCP Current 1.2 A
2
1
+1.8VALWP
12
PC504
22U_0603_6.3V6M
B B
+2.5V_MEN
TDC 0.3A by power budget
AP7361 U-DFN3030-8 Pd limit=1.7W
Peak loading=1.1A.
Pd=(3.3-2.5)*1.1=0.88W < 1.7W
12
12
PR516
10.2K_0402_1%
OCP is 1.1~1.5A
2.5VSP
12
PC515
0.01UF_0402_25V7K
PAD-OPEN1x1m
12
PC516
22U_0603_6.3V6M
PJP506
1 2
+2.5V_MEM
EN_2.5V
@
PC513
PU503
AP7361C-FGE-7_U-DFN3030-8_3X3
9
GND
1
OUT
8
IN
2
NC
7
NC
3
ADJ/NC
6
NC
4
GND
5
EN
PR515
21.5K_0402_1%
PJP505
+3.3V_ALW
SIO_SLP_S4#<11,17,32,43>
A A
1 2
PAD-OPEN1x1m
@
0_0402_5%
1 2
PR513
PR514
1M_0402_1%
+2.5V_VIN
12
PC514
4.7U_0603_6.3V6K
12
12
.1U_0402_16V7K
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE IN FORMATION IT CONTAINS
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+1.8VALWP/+1.5VSP
+1.8VALWP/+1.5VSP
+1.8VALWP/+1.5VSP
LA-E121P
LA-E121P
LA-E121P
1
46 59Wednesday, November 09, 2016
46 59Wednesday, November 09, 2016
46 59Wednesday, November 09, 2016
1.0
1.0
1.0
5
4
3
2
1
+1.0V_VCCST
PR602
@
12
PR601
PR604
@
75_0402_1%
45.3_0402_1%
+3.3V_RUN
PCH_PWROK<11>
IMVP_VR_ON<33>
I_SYS<32,50>
470K_0402_5%
VCCSENSE<15>
VSSSENSE<15>
12
12
PR605
100_0402_1%
PR625 0_0402_5%@
PR616 0_0402_5%@
PR620
@
0_0402_5%
1 2
FCCM_GT<48>
PWM1_GT<48>
PH603
1 2
27.4K_0402_1%
PR647
1 2
PC629
2200P_0402_50V7K
1 2
PC639
1500P 50V K X7R 0402
1 2
PR648
1 2
1.5K_0402_1%
@
PC651
1 2
330P_0402_50V7K
PC654
1 2
0.01UF_0402_25V7K
PC602
0.1U_0402_25V6
1 2
1 2
1 2
PR6121.91K_0402_1%
1 2
PR614 0_0402_5%@
1 2
1 2
PU602
1
PSYS
2
IMON_B
3
NTC_B
4
COMP_B
5
FB_B
6
RTN_B
7
ISUMP_B
8
ISUMN_B
9
ISEN1_B
10
ISEN2_B
41
AGND
PC625
330P_0402_50V7K
1 2
PR629
93.1K_0402_1%
1 2
1 2
PR635
10K_0402_1%
PR639
5.49K +-1% 0402
1 2
PC636
33P 50V J NPO 0402
1 2
PR645
316_0402_1%
1 2
PR61849.9_0402_1%
PR62610_0402_1%
@
VIDSCLK_B
37
38
39
40
VR_HOT#
VR_READY
VR_ENABLE
FCCM_B11PWM1_B12PWM2_B13IMON_A14NTC_A15COMP_A
IMON_IA
12
2K_0402_1%
PR650
PC647
1 2
680P_0402_50V7K
12
PC653
0.082U_0402_16V7K
12
1 2
VIDSOUT_B
VIDALERT_N_B
36
35
SCLK
ALERT#
16
NTC_IA
COMP_IA
PR608
78.7K_0402_1%
1 2
PR611
48.7K_0402_1%
32
33
34
VIN
SDA
VCC
PROG231PROG1
PWM_C
FCCM_C
ISUMN_C
ISUMP_C
RTN_C
FB_C
COMP_C
IMON_C
PWM_A
FCCM_A
FB_A
RTN_A18ISUMP_A19ISUMN_A
17
20
S IC ISL95857AHRTZ-TS2778 TQFN 40P PWM
FB_IA
PR657
4.42K_0402_1%
1 2
ISUMP_IA <48>
12
Local sense put on HW site
D D
H_PROCHOT#<12,32,50>
470K_0402_5%
VCC_GT_SENSE<16>
C C
VSS_GT_SENSE<16>
ISUMP_GT<48>
ISUMN_GT<48>
B B
A A
PH601
1 2
1 2
PR631
27.4K_0402_1%
2200P_0402_50V7K
@
1 2
330P_0402_50V7K
PC619
1 2
0.01UF_0402_25V7K
12
10K_0402_5%
12
PH602
PC614
1 2
PC618
PR628
4.42K_0402_1%
PC641
.1U_0402_16V7K
PC616
68P 50V J NPO 0402
1 2
12
PR633
12
1 2
PC605 47P_0402_50V8J~D
PR610
10K_0402_1%
1 2
PR617
3.92K_0402_1%
1 2
12
11K_0402_1%
@
PC624
12
PC620
0.033U_0402_16V7K
VIDSCLK<15>
VIDALERT_N<15>
VIDSOUT<15>
PR678
100_0402_1%
1 2
PC617
1200P_0402_50V7K
1 2
1.91K_0402_1%
PC621
680P_0402_50V7K
1 2
0.082U_0402_16V7K
12
PC626
0.047U_0402_25V7K
1 2
PR622
1 2
PR632
1K_0402_1%
1 2
PR613
88.7K +-1% 0402
1 2
PC613
330P 50V K X7R 0402
1 2
PR621
316_0402_1%
PR623
2K_0402_1%
1 2
PC627
2200P_0402_50V7K
1 2
PR638
374_0402_1%
1 2
+5V_ALW
0_0402_5%
1 2
@
0_0402_5%
1 2
12
PC603
PC604
1U_0603_10V6K
0.22U_0603_25V7K
PWM_VSA
30
FCCM_VSA
29
28
27
26
FB_VSA
25
COMP_VSA
24
IMON_VSA
23
22
PWM_IA <48>
21
FCCM_IA <48>
12
PC630
2200P_0402_50V7K
12
PR644
1K_0402_1%
PC642
0.033U_0402_16V7K
1 2
PC646
0.047U_0402_25V7K
1 2
PR656
11K_0402_1%
1 2
PH605
10KB_0402_5%
1 2
PR603
12
CPU_B+
PR640
348 +-1% 0402
PC645
.1U_0402_16V7K
12
+5V_ALW
ISUMN_IA <48>
PR619 2.2_0603_5%
1 2
PC611
0.22U_0603_16V7K
1 2
PWM_SA
12
@
PR606
0_0402_5%
PWM_VSA
12
PC628
33P 50V J NPO 0402
PC631
12
330P_0402_50V7K
PR651
PC643
1
2
3
12
PR630
12
4700P 25V K X7R 0402
12
133K +-1% 0402
Local sense put on HW site
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
VCC_SA
TDC 4 A
Peak Current 4.5A
OCP current 5.4A
Choke DCR 13 m ohm
SA_UGATE
PU614
S IC ISL95808HRZ-TS2778 DFN MOSFET DRIVE
UGATE
BOOT
PWM
GND4LGATE
2.49K +-1% 0402
12
12
PHASE
FCCM
VCC
TP
9
+5V_ALW
1 2
PC632
1000P 50V K X7R 0402
PR646
1 2
316_0402_1%
1 2
1.62K_0402_1%
PR652
@
2K_0402_1%
PC601
@
470P 50V K X7R 0402
2
8
7
6
SA_LGATE
5
12
12
FCCM_VSA
PC685
1U_0402_10V6K
1 2
PR636 649 +-1% 0402
1 2
1K_0402_1%
PC640
1 2
2200P_0402_50V7K
PR649
@
PR679
0_0402_5%
PR641
PJP603
VCCSA_B+ CPU_B+
1 2
PAD-OPEN1x1m
VCCSA_B+
12
12
PC612
PC608
10U_0805_25V6K
10U_0805_25V6K
4
1
3
2
PQ501
AON7934_DFN3X3A-8-10
D1
D1
D1
D110D2/S1
S2
S2
S2
6
7
5
G1
9
G2
8
.1U_0402_16V7K
SA_SW
12
PC637
PC644
1 2
12
@EMC@
PR627
4.7_1206_5%
SA_SNUBSA_SNUB
12
PC622
680P_0603_50V7K
@EMC@
0.033U_0402_16V7K
PC650
@
0.082U_0402_16V7K
12
1 2
4
3
12
PR624
3.65K_0603_1%
ISUMP_VSA
PC633
3300P 25V K X7R 0402
0.01UF_0402_25V7K
330P_0402_50V7K
PL614
0.47UH_MMD05CZR47M_12A_20%
1
2
ISUMN_VSA
ISUMP_VSA
12
PR642
2.61K_0402_1%
PR643
12
1 2
11K_0402_1%
VSA_SEN- <17>
PC649
1 2
@
PC652
1 2
VSA_SEN+ <17>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PWR_VCORE_ISL95857
PWR_VCORE_ISL95857
PWR_VCORE_ISL95857
LA-E121P
LA-E121P
LA-E121P
1
47 59Wednesday, November 09, 2016
47 59Wednesday, November 09, 2016
47 59Wednesday, November 09, 2016
+VCC_SA
10KB_0402_5%
PH604
ISUMN_VSA
1.0
1.0
1.0
5
4
3
2
1
D D
CPU_B+
EMC@
EMC@
1
PC660
9
8
7
6
5
100P 50V J NPO 0402
PGND2
PWM
BOOT
BOOT_R
VIN
+
12
PC606
2
@
100U_D_20VM_R55M
PU610
VSW
PGND1
VDD
SKIP#
PR659
@
0_0402_5%
<47>
12
12
12
PC657
PC656
PC663
10U_0805_25V6K
C C
PC686
B B
10U_0805_25V6K
10U_0805_25V6K
PWM_IA<47>
12
12
PR662
10P_0402_50V8K
5.11K_0402_1%
12
12
PC659
PC658
10U_0805_25V6K
100P 50V J NPO 0402
PC655
1 2
0.22U_0603_16V7K
1 2
PR660
2.2_0603_5%
12
PC680
1000P_0402_50V7K
S IC CSD97396Q4M VSON 8P DR MOS
PJP601
1 2
PAD-OPEN 4x4m
@EMC@
PL602
1 2
9A Z80 10M 1812_2P
4
3
2
1
12
12
PC661
FCCM_IA
+PWR_SRC
CORE_SW
1U_0402_10V6K
VCC_core
TDC 21A
Peak Current 32A
OCP current 38.4A
Choke DCR 0.9 +-7%m ohm
PL610
0.15UH_MMD06CZER15MG_37A_20%
4
EMC@
PR663
+5V_ALW
3
12
12
PR661
3.65K_0603_1%
4.7 +-5% 1206
ISUMP_IA
CORE_SNUB
12
PC662
680P_0603_50V7K
EMC@
VCC_GT
TDC 18A
Peak Current 31A
OCP current 37.2A
1
2
<47>
ISUMN_IA
+VCC_CORE
<47>
GPU_B+
12
12
PC665
10U_0805_25V6K
@
12
12
PC673
PC672
PC664
PWM1_GT<47>
PC688
10U_0805_25V6K
@
12
10P_0402_50V8K
10U_0805_25V6K
12
PR680
5.11K_0402_1%
10U_0805_25V6K
PC671
1 2
0.22U_0603_16V7K
1 2
PR672
2.2_0603_5%
12
PC679
1000P_0402_50V7K
9
8
7
6
5
S IC CSD97396Q4M VSON 8P DR MOS
Choke DCR 0.9 +-7%m ohm
PU612
PGND2
PWM
BOOT
BOOT_R
VIN
@
VSW
PGND1
VDD
SKIP#
PR671
0_0402_5%
<47>
GT_SW1
4
3
2
1
12
12
PC677
1U_0402_10V6K
FCCM_GT
PJP602
PAD-OPEN 1x2m~D
@EMC@
PR676
+5V_ALW
21
CPU_B+GPU_B+
PL612
0.15UH_MMD06CZER15MG_37A_20%
1
4
12
4.7_1206_5%
GT_SNUB1
12
PC678
680P_0603_50V7K
@EMC@
3
GT1P
PR674
3.65K_0603_1%
1 2
ISUMP_GT
<47>
+VCC_GT
2
<47>
ISUMN_GT
A A
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PWR_VCORE_ISL95857
PWR_VCORE_ISL95857
PWR_VCORE_ISL95857
LA-E121P
LA-E121P
LA-E121P
1
1.0
1.0
48 59Wednesday, November 09, 2016
48 59Wednesday, November 09, 2016
48 59Wednesday, November 09, 2016
1.0
4 4
3 3
2 2
1 1
+VCC_CORE +VCC_GT
VCC_CORE Place on CPU
22U_0603 * 33 pcs +1U_0201*35 pcs
A
B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VCC_SA Place on CPU
22U_0603 * 12 pcs + 1U_0201*7 pcs
C
PC1127
330U_D2_2.5VM_R9M
1
2
+
2
+
PC1062
12
@
PC1170
22U_0603_6.3V6M
12
@
PC1171
22U_0603_6.3V6M
12
@
PC1172
22U_0603_6.3V6M
12
@
PC1173
22U_0603_6.3V6M
12
@
PC1174
22U_0603_6.3V6M
12
PC1099
1U_0201_6.3V6M
1
330U_D3_2VM_R6M
12
PC1095
1U_0201_6.3V6M
12
PC1094
1U_0201_6.3V6M
12
PC1096
1U_0201_6.3V6M
12
PC1090
1U_0201_6.3V6M
12
PC1093
1U_0201_6.3V6M
12
PC1091
1U_0201_6.3V6M
12
PC1097
1U_0201_6.3V6M
12
PC1092
1U_0201_6.3V6M
12
PC1098
1U_0201_6.3V6M
12
PC1050
1U_0201_6.3V6M
12
PC1051
1U_0201_6.3V6M
12
PC1052
1U_0201_6.3V6M
12
PC1053
1U_0201_6.3V6M
12
PC1054
1U_0201_6.3V6M
12
PC1126
1U_0201_6.3V6M
12
PC1164
1U_0201_6.3V6M
12
PC1125
1U_0201_6.3V6M
12
PC1083
1U_0201_6.3V6M
12
PC1030
1U_0201_6.3V6M
12
PC1031
1U_0201_6.3V6M
12
PC1032
1U_0201_6.3V6M
12
PC1033
1U_0201_6.3V6M
12
PC1034
1U_0201_6.3V6M
12
PC1035
1U_0201_6.3V6M
12
PC1036
1U_0201_6.3V6M
12
PC1037
1U_0201_6.3V6M
12
PC1038
1U_0201_6.3V6M
12
PC1039
1U_0201_6.3V6M
12
PC1084
1U_0201_6.3V6M
12
PC1086
1U_0201_6.3V6M
12
PC1085
1U_0201_6.3V6M
12
PC1088
1U_0201_6.3V6M
12
PC1087
1U_0201_6.3V6M
12
PC1089
1U_0201_6.3V6M
PC1081
22U_0603_6.3V6M
PC1080
22U_0603_6.3V6M
PC1082
22U_0603_6.3V6M
PC1067
22U_0603_6.3V6M
PC1072
22U_0603_6.3V6M
PC1069
22U_0603_6.3V6M
PC1074
22U_0603_6.3V6M
PC1070
22U_0603_6.3V6M
PC1061
22U_0603_6.3V6M
PC1071
22U_0603_6.3V6M
PC1066
22U_0603_6.3V6M
PC1073
22U_0603_6.3V6M
PC1068
22U_0603_6.3V6M
PC1075
22U_0603_6.3V6M
PC1064
22U_0603_6.3V6M
PC1065
22U_0603_6.3V6M
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
PC1076
22U_0603_6.3V6M
PC1078
22U_0603_6.3V6M
PC1077
22U_0603_6.3V6M
PC1079
22U_0603_6.3V6M
PC1001
22U_0603_6.3V6M
PC1002
22U_0603_6.3V6M
PC1003
22U_0603_6.3V6M
PC1004
22U_0603_6.3V6M
PC1005
22U_0603_6.3V6M
PC1006
22U_0603_6.3V6M
PC1007
22U_0603_6.3V6M
PC1008
22U_0603_6.3V6M
PC1009
22U_0603_6.3V6M
PC1010
22U_0603_6.3V6M
PC1011
22U_0603_6.3V6M
PC1012
22U_0603_6.3V6M
PC1013
22U_0603_6.3V6M
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
+330u_D2*2 pcs
A
B
C
+VCC_SA
330U_D2_2.5VM_R9M
D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
Title
Size Document Number Rev
Date: Sheet of
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PROCESSOR DECOUPLING
PROCESSOR DECOUPLING
PROCESSOR DECOUPLING
LA-E121P
LA-E121P
LA-E121P
E
49 59Wednesday, November 09, 2016
49 59Wednesday, November 09, 2016
49 59Wednesday, November 09, 2016
1.0
1.0
1.0
12
PC1153
1U_0201_6.3V6M
12
PC1147
1U_0201_6.3V6M
12
PC1148
1U_0201_6.3V6M
12
PC1149
1U_0201_6.3V6M
12
PC1150
1U_0201_6.3V6M
12
PC1151
1U_0201_6.3V6M
12
PC1152
1U_0201_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
12
PC1057
12
PC1058
12
PC1059
12
PC1060
12
PC1139
12
PC1140
12
PC1141
12
PC1142
12
PC1143
12
PC1144
12
PC1145
12
PC1146
1
2
+
PC1128
2
+
PC1063
12
@
PC1181
22U_0603_6.3V6M
12
@
PC1180
22U_0603_6.3V6M
12
@
PC1177
22U_0603_6.3V6M
12
@
PC1179
22U_0603_6.3V6M
12
@
PC1176
22U_0603_6.3V6M
12
@
PC1178
22U_0603_6.3V6M
12
@
PC1175
22U_0603_6.3V6M
12
PC1040
1U_0201_6.3V6M
1
330U_D3_2VM_R6M
12
PC1041
1U_0201_6.3V6M
12
PC1042
1U_0201_6.3V6M
12
PC1043
1U_0201_6.3V6M
12
PC1044
1U_0201_6.3V6M
12
PC1045
1U_0201_6.3V6M
12
PC1046
1U_0201_6.3V6M
12
PC1047
1U_0201_6.3V6M
12
PC1048
1U_0201_6.3V6M
12
PC1049
1U_0201_6.3V6M
12
PC1055
1U_0201_6.3V6M
12
PC1056
1U_0201_6.3V6M
PC1133
22U_0603_6.3V6M
PC1137
22U_0603_6.3V6M
PC1129
22U_0603_6.3V6M
PC1132
22U_0603_6.3V6M
PC1136
22U_0603_6.3V6M
PC1134
22U_0603_6.3V6M
PC1135
22U_0603_6.3V6M
PC1138
22U_0603_6.3V6M
PC1027
22U_0603_6.3V6M
PC1028
22U_0603_6.3V6M
PC1130
22U_0603_6.3V6M
PC1029
22U_0603_6.3V6M
PC1131
22U_0603_6.3V6M
12
12
12
12
12
12
12
12
12
12
12
12
12
PC1014
22U_0603_6.3V6M
PC1015
22U_0603_6.3V6M
PC1016
22U_0603_6.3V6M
PC1017
22U_0603_6.3V6M
PC1018
22U_0603_6.3V6M
PC1019
22U_0603_6.3V6M
PC1020
22U_0603_6.3V6M
PC1021
22U_0603_6.3V6M
PC1022
22U_0603_6.3V6M
PC1023
22U_0603_6.3V6M
PC1024
22U_0603_6.3V6M
PC1025
22U_0603_6.3V6M
PC1026
22U_0603_6.3V6M
12
12
12
12
12
12
12
12
12
12
12
12
12
VCC_GT Place on CPU (U22)
22U_0603 * 26 pcs +1U_0201*12 pcs
+330u_D2*2 pcs
D
E
A
+SDC_IN
1 1
PR909
3.3 +-1% 0402
12
PC926
DCIN_ISL88738
VDD_ISL88738
ACIN_ISL88738
PC938
10P_0402_50V8J
1 2
1U 25V K X5R 0402
17
DCIN
18
VDD
19
ACIN
20
OTGEN/CMIN
21
SDA
22
SCL
23
PROCHOT#
24
ACOK
PR933
100K_0402_1%
1 2
0_0402_5%
PR951
@
1 2
COMP_ISL88738
12
PR934
12
499 +-1% 0402
PC943
@
12
560P_0402_50V7K
PC944
0.01UF 25V K X7R 0402
Close to EC ADP_I pin
PC1286
H_PROCHOT#<12,32,47>
+SDC_IN
12
@
0_0402_5%
1 2
PR928 0_0402_5%@
1 2
PR931
100K_0402_1%
1 2
12
12
1 2
PR919
+PWR_SRC
PD901
SDMK0340L-7-F_SOD323-2~D
+VBUS_DC_SS
+VBUS_DC_SS
+VBUS_DC_SS+VBUS_DC_SS
2 2
+DC_IN_SS
+DC_IN_SS
+DC_IN_SS+DC_IN_SS
SDMK0340L-7-F_SOD323-2~D
PC931 1U_0603_25V6
PD903
2 1
RB520SM-30T2R_EMD2-2
PD904
1 2
12
12
0.1U 25V K X5R 0402
PR916
1_0805_5%~D
1 2
12
PC933
1U_0402_6.3V6K
ACAV_IN1
PQ909
13
DMN65D8LW-7_SOT323-3
AC_DIS<32>
3 3
2
G
12
1M_0402_1%
PR927
D
154K_0402_1%
S
PR925
PR918
100K_0402_1%
1 2
PBAT_CHARGER_SMBDAT<32,41>
12
PBAT_CHARGER_SMBCLK<32,41>
PROCHOT#_ISL88738<51>
PBAT_PRES#<32,41>
PR944
442K_0402_1%
ACIN_ISL88738
PR945
100K_0402_5%
PR960 0_0402_5%@
PR920 0_0402_5%@
1 2
1 2
1 2
PR926 0_0402_5%@
ACOK_ISL88738
@
100K_0402_1%
1 2
PR943
@
0_0603_5%
1 2
OTGEN/CMIN
PROCHOT#_ISL88738
PR930
PR922 0_0402_5%@
+3.3V_ALW
CMOUT<51>
4 4
PR901
0.01_1206_1%
1
2
12
3.3 +-1% 0402
CSIP_ISL88738
PC925
4.7U 6.3V M X5R 0402
1 2
ADP_ISL88738
CSIP_ISL88738
CSIN_ISL88738
13
14
15
16
ADP
CSIP
CSIN
BATGONE
OTGPG/CMOUT26PROG27AMON/BMON29PSYS30VBAT
28
25
12
PR932
@
12
12
PR9470_0402_5%
I_BATT
I_BATT <32>
I_ADP <32>
B
+PWR_SRC_AC
EMC@
1UH +-20% 6.6A 5X5X3 MOLDING, A.3
4
3
12
PR910
CSIN_ISL88738
PC930
0.22U_0603_25V7K
1 2
PR914
@
0_0603_5%
1 2
UG1_ISL88738
LX1_ISL88738
BOOT1_ISL88738
11
10
12
BOOT1
PHASE1
UGATE1
ASGATE
CMOP
31
12
105K +-1% 0402
0_0402_5%
PR949
VBAT1_ISL88738
@
12
PC947
0.1U_0402_25V6
@
PR935
0_0402_5%
I_SYS <32,47>
I_ADP
0.1U_0402_25V6
PL901
12
PJP901
1 2
PAD-OPEN 4x4m
12
PC927
1U 25V K X5R 0402
LG1_ISL88738
PU901
9
33
S IC ISL88738HRTZ-T TQFN 32P PWM
PAD
VDDP_ISL88738
8
LGATE1
VDDP
LG2_ISL88738
7
LGATE2
LX2_ISL88738
6
PHASE2
UG2_ISL88738
5
UGATE2
BOOT2_ISL88738
4
BOOT2
3
VSYS
CSOP_ISL88738
2
CSOP
CSON_ISL88738
1
CSON
BGATE
32
BGATE_ISL88738
12
@
12
PR936
0_0402_5%
PR948
12.7K +-1% 0402
PC950
@
1 2
PC902
@EMC@
PR915
4.7_0402_5%
1 2
1U_0402_6.3V6K
0.22U_0603_25V7K
4.7U 6.3V M X5R 0402
PR940
100_0402_1%
12
PC903
0.1U_0402_25V6
@EMC@
VDD_ISL88738
PC932
12
PC934
12
PR929 0_0402_5%@
1 2
PC945
12
12
12
PC911
22U_0805_25V6M
2200P_0402_50V7K
PR921
2.2_0603_5%
1 2
PC939 0.1U_0402_25V6@
1 2
PC942 1U 25V K X5R 0402
1 2
PR937 2.2 +-1% 0402
PR938 2.2 +-1% 0402
1 2
1 2
1 2
PC946 1U 25V K X5R 0402
+PBATT
12
PC904
22U_0805_25V6M
12
+PWR_SRC
+CHARGER_SRC
12
PC905
PC906
22U_0805_25V6M
22U_0805_25V6M
PQ905
AON6992_DFN5X6D-8-7
S2
3
AC1_DISC#<24,51>
ACAV_IN_NB<32,41,51>
C
D
+PWR_SRC
1
1
12
+
PC909
2
15U_B2_25VM_R100M
@
UG1_ISL88738
1
2
D1
G1
D2/S1
S24S2
G2
5
6
LG1_ISL88738
1 2
0_0402_5%
1 2
0_0402_5%
1
+
+
PC910
PC951
2
2
15U_B2_25VM_R100M
15U_B2_25VM_R100M
@
@
PL902
2.2UH_PCMB103T-2R2MS_13A_20%
7
1 2
12
PR923
LX1_ISL88738
4.7_1206_5%
@EMC@
SNUB_CHG1
12
PC940
680P_0603_50V7K
@EMC@
PR939
@
3
PR941
@
2
12
PR924
LX2_ISL88738
4.7_1206_5%
@EMC@
SNUB_CHG2
12
PC941
680P_0603_50V7K
@EMC@
1 2
PD905
BAT54CW_SOT323-3
1
ACAV_IN1
7
PR950
@
0_0402_5%
0.1U_0402_10V7K
PR942
@
1 2
0_0402_5%
UG2_ISL88738
PQ904
AON6992_DFN5X6D-8-7
1
2
D1
G1
D2/S1
S24S2
G2
5
6
LG2_ISL88738
LM393_P
PC949
1 2
1
B
2
A
12
PC913
10U_0805_25V6K
12
PC928
0.1U_0402_25V6
@EMC@
S2
3
5
P
Y
G
3
12
12
PC915
PC914
PC916
10U_0805_25V6K
10U_0805_25V6K
12
PC929
2200P_0402_50V7K
@EMC@
PR917
0.005_1206_1%
1
2
MC74VHC1G08DFT2G SC70 5P AND
PU903
PR946
@
1 2
4
0_0402_5%
12
10U_0805_25V6K
4
3
12
12
PC917
10U_0805_25V6K
+VCHGR
12
PC918
10U_0805_25V6K
12
PC919
10U_0805_25V6K
12
PC920
10U_0805_25V6K
PQ906
AON7409_DFN8-5
1
2
3 5
4
12
12
PC935
PC936
10U_0805_25V6K
ACAV_IN<32,33>
PR953
100K_0402_1%
Add PR953 for IT8010 voltage leakage issue
PC937
1 2
10U_0805_25V6K
BGATE_ISL88738
4700P_0402_25V7K
+PBATT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
P59 PWR-Charger
P59 PWR-Charger
P59 PWR-Charger
LAE121
LAE121
D
LAE121
50 59Wednesday, November 09, 2016
50 59Wednesday, November 09, 2016
50 59Wednesday, November 09, 2016
1.0
1.0
1.0
5
DCIN_AC_Detector
PC1201
@
0.01U_0402_25V7K~D
1 2
12
3
2
BAT54CW_SOT323-3
PC1206
220P_0402_50V8J~D
PD1801
1
LM393_P
8
3
P
+
2
-
G
4
EMI Part
5A_Z120_25M_0805_2P
1 2
1 2
5A_Z120_25M_0805_2P
EMC@
12
PC1208
EMC@
1000P_0402_50V7K
LM393_P
PR1203
1.8M_0402_1%
1 2
PU1201A
LM393DGKR_VSSOP8
1
O
PL1201
EMC@
PL1202
+3.3V_VDD_DCIN
12
PR1206
1K_0402_1%
12
PC1207
1200P_0402_50V7K
12
PR1227
ACAV_IN_NB
100K_0402_5%
ACAV_IN_NB <32,41,50,51>
12
PC1216
100P_0402_50V8J
EMC@
+TBTA_Vbus_1
+3.3V_VDD_DCIN
+DC_IN
D D
C C
+3.3V_VDD_DCIN
+3.3V_VDD_PIC
12
12
PR1201
PR1208
240K_0402_1%
102K_0402_1%
(>17.6V)
12
PR1219
23.2K +-1% 0402
12
12
PC1205
PR1217
84.5K_0402_1%
100P_0402_50V8J~D
+TBTA_VBUS
PC1209 can't over 1000P
B B
+TBTA_Vbus_1 +3.3V_VDD_PIC
12
PR1237
100K_0402_1%
@
12
PR1239
150K_0402_1%
@
12
12
12
PC1211
PR1247
PR1246
100P_0402_50V8J
@
100K_0402_1%
@
100K +-1% 0402
S3 OVP
PD1205
@
SDMK0340L-7-F_SOD323-2
1 2
1 2
0_0402_5%
@
5
6
12
PC1212
@
100P_0402_50V8J
PR1238
+
-
LM393_P
8
P
G
4
PU1201B
LM393DGKR_VSSOP8
7
O
12
PR1240
100K_0402_1%
1 2
0_0402_5%
12
PR1243
PC1213
@
@
1200P_0402_50V7K
+TBTA_Vbus_1
4
5
12
PC1214
@
+AC_IN
+3.3V_VDD_PIC
PR1236
100K_0402_5%
1 2
34
PQ1209B
DMN65D8LDW-7_SOT363-6
0.01UF_0402_25V7K
PJP1202
112
JUMP_43X118
PQ1206
S3
AON7409_DFN8-5
4
12
61
2
(From TI GPIO1)
2
1
2
35
12
1 2
PC1210
1500P_0402_50V7K
PR1229
49.9K +-1% 0402
PQ1209A
DMN65D8LDW-7_SOT363-6
EN_PD_HV_1<24,51>
EN_PD_HV_1<24,51>
PR1228
+3.3V_VDD_PIC
PR1210
1M_0402_5%
DCIN1_EN<33>
499K +-1% 0402
12
150K_0402_1%
12
PR1255
@
PR1253
100K_0402_5%
EN_PD_HV_1#
5
12
1 2
0_0402_5%
PR1221
@
34
2
PQ1214B
@
DMN65D8LDW-7_SOT363-6
0_0402_5%
+3.3V_ALW
12
PR1251
300K +-5% 0402
12
PR1252
100K_0402_5%
61
PC1204
0.1U_0402_10V7K
PR1254
1 2
0_0402_5%
PR1211
@
1 2
1 2
0_0402_5%
PR1215
@
12
PR1224
100K_0402_5%
3
G
2
PQ1214A
DMN65D8LDW-7_SOT363-6
12
5
1
P
B
2
A
G
3
PQ1205
DMN65D8LW-7_SOT323-3
D
S
13
G
2
1 2
0_0402_5%
PQ1215
PC1202
AO3409 P-CHANNEL SOT-23
4
PR1226
100K_0402_5%
+3.3V_VDD_PIC
12
12
PR1205
499K +-1% 0402
2200P 50V K X7R 0603
1 2
1 2
S
D
1 3
+3.3V_VDD_PIC
PU1200
MC74VHC1G08DFT2G SC70 5P AND
O
PR1225
@
S4 S5
PQ1213
AON7409_DFN8-5
1
2
3 5
12
PR1212
49.9K +-1% 0402
61
2
PR1216
0_0402_5%
@
EN_PD_HV_1<24,51>
AC1_DISC#<24,50>
4
PQ1201A
DMN65D8LDW-7_SOT363-6
PR1260
@
0_0402_5%
1 2
1 2
0_0402_5%
@
PR1244
+VBUS_DC_SS
VBUS1_ECOK<33,51>
+3.3V_ALW
PR1259
100K_0402_5%
1 2
34
D
5
G
S
ACAV_IN_NB<32,41,50,51>
VBUS1_ECOK
100K_0402_5%
PQ1208B
DMN65D8LDW-7 2N SOT363-6
VBUS2_ECOK<33,41>
VBUS1_ECOK<33,51>
PR1234
2
G
@
0_0402_5%
1 2
PR1261
2
12
100K_0402_5%
+3.3V_ALW
S
1 2
0_0402_5%
PR1220
@
PR1222
1 2
61
D
1 2
0_0402_5%
@
PD1202
S SCH DIO 5A 100V 15UA 0.88V TO227-3
2
1
3
PQ1202
AON7409_DFN8-5
1
2
35
4
12
PR1213
34
49.9K +-1% 0402
5
PQ1201B
DMN65D8LDW-7_SOT363-6
PR1235
@
100K_0402_5%
0_0402_5%
1 2
PR1242
@
1 2
1 2
0_0402_5%
PR1257
@
2
G
+3.3V_ALW
PQ1208A
PR1232
100K_0402_5%
1 2
DMN65D8LDW-7 2N SOT363-6
34
D
5
G
PQ1207B
PR1241
DMN65D8LDW-7 2N SOT363-6
S
12
PR1207
499K +-1% 0402
61
D
S
2
G
1 2
PR1258
@
0_0402_5%
12
+3.3V_ALW+3.3V_ALW
PQ1211A
PC1203
1 2
+3.3V_ALW
DMN65D8LDW-7 2N SOT363-6
S
1500P_0402_50V7K
100K_0402_5%
5
G
1 2
61
D
12
S
G
PQ1203
2
D
1 3
12
AO3409 P-CHANNEL SOT-23
34
PQ1204B
DMN65D8LDW-7_SOT363-6
PR1233
@
AC_DISC# <32,41,51>
34
D
12
S
PQ1211B
DMN65D8LDW-7 2N SOT363-6
PR1230
100K_0402_5%
PQ1207A
DMN65D8LDW-7 2N SOT363-6
PR1202
300K +-5% 0402
PR1209
100K_0402_5%
5
+3.3V_ALW
1 2
61
D
S
PC1217
@
1500P_0402_50V7K
1 2
0_0402_5%
PR1218
@
PR1231
100K_0402_5%
0_0402_5%
PR1245
@
1 2
G
PQ1210A
DMN65D8LDW-7 2N SOT363-6
+3.3V_VDD_PIC
2
1
+SDC_IN
12
PR1214
100K_0402_5%
61
1 2
2
0_0402_5%
PQ1204A
DMN65D8LDW-7_SOT363-6
@
34
D
5
G
S
13
D
2
G
S
PQ1216
AC_DISC# <32,41,51>
PR1223
CMOUT <50>
PQ1210B
DMN65D8LDW-7 2N SOT363-6
PROCHOT#_ISL88738 <50>
DMN65D8LW-7_SOT323-3
OVP setting: 5.5V
PR1248
12
PR1249
10K_0402_5%
@
0_0402_5%
1 2
1 2
0_0402_5%
@
PR1250
13
D
2
G
S
A A
PQ1212
DMN65D8LW-7_SOT323-3
LPS_PROTECT#
PT1
@
PAD~D
(From EC)
EN_PD_HV_1 <24,51>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
TypeC_PD
TypeC_PD
TypeC_PD
LA-E121P
LA-E121P
LA-E121P
1
1.0
1.0
51 59Wednesday, November 09, 2016
51 59Wednesday, November 09, 2016
51 59Wednesday, November 09, 2016
1.0
5
4
Version Change List ( P. I. R. List )
3
2
1
Item
D D
1
2
3
4
5
C C
6
7
8
9
Change CPU VR
56
version
CHARGER
59
1Type-C PD
60
Selector
Change the S4
fast turn off
60
circuit to avoid
the leakage
Fine tune the
DC-IN detect
60
voltage
location
57
alignment
Decrease the
charger input
59
leakage voltage
56
50
60
MOS leakage
problem
Reserve the OVP
function
Date
2016
05/24
2016
05/30
2016
05/30
2016
06/13
2016
06/13
2016
06/13
2016
06/13
2016
06/17
2016
07/01
Owner
Compal
Compal
Compal
Compal location alignment
Compal
Compal
Compal
Compal
change solution version to fix PS4 funciton issue change ISL95857HRTZ to ISL95857AHRTZ
Add the Circuit for Multiple Input Detach
detection & PROCHOT#
Change the S4 fast turn off circuit to
avoid the leakage
For Temp/Voltage test to fine tune the
DC-IN detect voltage from 17.6V to 16.9V
To decrease the charger input leakage voltage
for TypeC AC
Regulate VR load lineRegulate VR
To solve the MOS leakage problem to avoid the
error active
Reserve the OVP function to protect the typeC device
Request
Issue
Description
Solution
Description
Charger: Add PR960 and depop PR919 let the PU901.20 CMIN connect to GND,
add 1 net PROCHOT#_ISL88738
TypeC: Add PQ1216 to drive the PROCHOT# and PC1217 to do the reserve.
Re-connect the PR1251.1 and PQ1215.3 from +VBUS_DC_SS to +AC_IN
PR1219 change from 22.6K to 23.2K. SD034232280Compal
VCCSA change the PU606 to PU614 and PL601 to PL614
IA change the PU603 to PU610 and PL603 to PL610
GT change the PU604 to PU612 and PL604 to PL612
Change the PD903 from SCS0340L010 to SCS00006C00.
PR651 change to 124K ohm SD034124380,PR613 change to 88.7k ohm
SD034887280, PC601 change to 470pF SE074471K80, PC639 change to
1500pF SE074152K80, PR639 change to 5.49K ohm, SD034549180, PC636
change to 33pF SE071330J80
PR12, PR11, PR1205, PR1207 and PR1228 change to 499K from 1M ohm
PR16, PR18, PR1212, PR1213 and PR1229 change to 49.9K from 1M ohm
PR10, PR1251 and PR1202 change to 300K from 100K ohm.
Depop PJP1202, PR1255, PR1239, PR1246, PC1211, PR1237,
PC1212, PD1205, PC1213, PC1214 and PR1248
Change the PR1247 from 200K_0402_1% to 100K_0402_5% ohm
Re-modify the S11 OVP description to S3 OVP.
Rev.Page# Title
X01
X01
X01
X01
X01
X01
X01
X02
X02
B B
10
11
12
13
A A
14
MOS leakage
50
problem
Change Charger
59
version
Change Charger
59
version
Change Charger
59
version
Change Charger
59
version
5
2016
07/01
2016
07/02
2016
07/14
2016
07/19
2016
08/11
Compal
Compal
Compal
Compal
Compal
To solve the MOS leakage problem to avoid
the error active
Charger IC update version
Charger IC update version
Charger IC update version
Charger IC update version
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
PR10 change to 300K from 100K ohm
Change the charger solution version to SA00009VW20
Change the PC926, PC927, PC942 and PC946 from @ to 1uF/0402
Change the PC925 and PC945 from 1uF to 4.7uF/0402
Change the PR909 and PR910 from 1 Ohm to 3.3 Ohm.
Change the PC944 from 47nF to 10nF.
Change the PR934 from 0 Ohm to 499 Ohm
Change PR932 from 118K to 105K
Connect PD901 to PWR_SRC the charger output
Add PC937
Add PC1286 (CAP 0.1U 25V K X5R 0402)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PWR P.I.R
PWR P.I.R
PWR P.I.R
LA-E121P
LA-E121P
LA-E121P
X02
X02
X02
X02
X02
1.0
1.0
52 59Wednesday, November 09, 2016
52 59Wednesday, November 09, 2016
52 59Wednesday, November 09, 2016
1
1.0
5
4
Version Change List ( P. I. R. List )
3
2
1
Item
Date
Request
Owner
D D
15
56 SA OVP
54
16
17
C C
18
19
20
21
Enable LPM mode
For IT8010
voltage leakage
59
issue
Modify symbol to
60 Modify PD1202,PD5 to 2nd source because vendor EOL
2nd source
57 RF request 2016
52 2016
RF request
51 2016
RF request
2016
08/30
2016
08/30
2016
09/02
2016
09/08
09/08
09/08
09/08
Compal
SA OVP when C status change
Compal Enable low power mode
Compal Add PR953 for IT8010 voltage leakage issue Add PR953 100K
Compal
Compal
Compal
RF need to add BOM in SB
RF need to add BOM in SB
RF need to add BOM in SB
Issue
Description
1.Change PC633 to 3300P
2.Change PR630 to 2.49K
3.Change PC628 to 33P
4.Change PC632 to 1000P
5.Change PC631 to 4700P
6.Remove PC601
7.Remove PR652
8.Change PL614 to SH000015M00, (S COIL .47UH)
9. Change PR636 to 649
10. Change PR651 to 133K
1. Remove PR410
2. Add PR426
Modify PD1202,PD5 to 2nd source(SCS00005X00) because vendor EOLCompal
Add snubber and D-cap capacitance
1.PC659/PC660 need add 100pf
2.PR663 need add 4.7//PC662 need add 680pf
Add snubber and D-cap capacitance
1.PC202/PC203/PC216/PC217 need add 100pf
2.PR202 need add 4.7//PC204 need add 680pf
Add snubber and D-cap capacitance
1.PC100/PC103 need add 100pf
2.PR106 need add 4.7//PC112 need add 680pf
Solution
Description
Rev.Page# Title
X03
X03
X03
X03
X03
X03
X03
B B
53
22
23
24
25
26
A A
27
RF request
59 For EMI request
Fine tune for
56
IC register
PWR_CHARGER59 Change PR948 to 13.3K
For Max Power
54 1. VCCIO use local sense: PR421 change to 0 ohm, de-pop PR422,PR412
125W
+5V voltage
51
droop
2016
09/08
2016
09/08
2016
09/29
2016
10/03
2016
10/04
2016
10/04
Compal
RF need to add BOM in SB
Compal Add PL901 EMI need to add PL901 in SB
Compal Fine tune for IC register PR640 Change 348
Pmax change need to modify RpsysCompal
Compal
Because Pmax change , so modify Rpsys
5V_ALW toType-C connector exist voltage droop
problem, need add a resistor on fb net
Add snubber and D-cap capacitance
1.PC301/PC303 need add 100pf
2.PR303 need add 4.7//PC302 need add 680pf
2. VCCIO change to 0.95V: De-pop PR413,PR416, pop PR415,PR414
Add PR121 in 5V ALW fbCompal
X03
X03
X03
X03
X03
X03
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PWR P.I.R
PWR P.I.R
PWR P.I.R
LA-E121P
LA-E121P
LA-E121P
53 59Wednesday, November 09, 2016
53 59Wednesday, November 09, 2016
53 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
4
Version Change List ( P. I. R. List )
3
2
1
Item
Date
Request
Owner
D D
28 Change PD1202,PD5 to common P/N. PD1202,PD5
50
C C
P/N.
2016
10/21
CompalBOM change to common
Issue
Description
Change to : SCS00009T00 - S SCH DIO 5A 100V 15UA 0.88V TO227-3
Solution
Description
Rev.Page# Title
A00
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PWR P.I.R
PWR P.I.R
PWR P.I.R
LA-E121P
LA-E121P
LA-E121P
54 59Wednesday, November 09, 2016
54 59Wednesday, November 09, 2016
54 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
4
3
Version Change List ( P. I. R. List ) LA-E122P
2
1
TitlePage#
D D
1 24 2016/05/23 EE UT5.D6 need to PD for TI suggestion
2 23
5 31
C C
6 0.2(X01)Depop RT132, RT133, CT115, CT116DP_AUX go through PD ,not TUSB5462016/05/23 EE23
8 39 2016/05/23 EE Remove HDD LED MUX feature Add RZ361 and depop QZ3, QZ2, RZ25 0.2(X01)
10 32 2016/05/23 EE Schematic align
11
12
B B
15
16 11 2016/05/23 EE
17
21
A A
22
[Type C]PD
Controller TI
DP/USB3
Repeater SW
TUSB546
[Type C]PD
Controller TI
[Type C]PD
Power
Codec ALC3246
DP/USB3
Repeater SW
TUSB546
[Type C]PD
Controller TI
PAD, LED
DP/USB3
Repeater SW
TUSB546
EC MEC5105
EC MEC5105
33
CPU (5/14)
10
USH & TPM
34 Atmel request for current TPM silicon Add CZ74 (pop) and RZ72(depop) for UZ12.7
CPU (4/14)
9 Cardreader change to RTS5242 (PCIE) Add net MEDIACARD_IRQ# to UC1.AN8
Card Reader
29 Cardreader change to RTS5242 (PCIE) Cardreader schematic change from RTS5330 (USB) to RTS5242 (PCIE)
CPU (5/14)
10 Cardreader change to RTS5242 (PCIE)
CPU (5/14)
10
CPU (6/14)
11
NGFF Card
30
M2 2280 Socket
35
NGFF Card
30
EC MEC5105
32
5
Date Issue DescriptionItem
Owner
Pop RT101 0.2(X01)
2016/05/23 EE TI TUSB546 sample change to ES3 Chagne UT9 from SA00009R700 to SA00009R710 0.2(X01)
Schematic alignEE2016/05/23243 0.2(X01)Add net name
TypeC PD solution (dead battery mode)EE2016/05/2325 0.2(X01)4
UT5.B2 : MUX1_FLIP_SEL_R
UT5.C2 : EN_PD_HV_1_R
UT5.D10 : PD1_GPIO2
UT5.G11 : AC1_DISC#_R
UT5.C10 : SW2_DP1_HPD_R
UT5.E10 : OTG_ID
UT5.G10 : PD1_GPIO6
UT5.D7 : PD1_GPIO7
RT111 change from 10K to 100K (SD028100380)
CT90 change from 100P to 1U (SE00000QL10)
2016/05/23 EMI EMI request CA2/CA3 change from 2200P to 330P (SE000006I80) 0.2(X01)
DP_AUX go through PD ,not TUSB5462016/05/23 EE247 0.2(X01)Pop RT108, RT109, CT80, CT81
2016/05/23239 Pop RT308Disable AUX snoop featureEE 0.2(X01)
Add net VCI_IN1# and add PU RE507
Add net VCI_IN2# and add PU RE508
2016/05/23
2016/05/23
2016/05/2313
2016/05/2314
EE 0.2(X01)
EE
EE
Schematic align for SB12 only
Schematic align for SB12 only
Add net USB_PWR_EN2# and PU RPE11.4
Add net USB_OC2# and PU RPC3.1
2016/05/23 EE
Change net from USB3.0 port 5 to PCIE port1
Delete USB2.0 port 6
2016/05/23 EE
2016/05/2318 EE
2016/05/2319 EE
2016/05/2320 EE
2016/05/23
2016/05/23
EE
EE
No support M.2 3042 (HCA), but keep SATA
cache for nonAR config
No support M.2 3042 (HCA), but keep SATA
cache for nonAR config
No support M.2 3042 (HCA), but keep SATA
cache for nonAR config
Remove HDD LED MUX feature
Remove HDD LED MUX feature
PORT80_DET#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
Change net from PCIE port 10 to SATA port1
Assign CLKREQ_PCIE#0 to Cardreader
Change net from PCIE port 10 to SATA port1
Depop RN100
Depop RN101
Change location RE510 to RE512
Reserve RE513 100k (SD028100380) to GND
Solution Description
2
Rev.
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)EE
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (1/5)
EE P.I.R (1/5)
EE P.I.R (1/5)
LA-E122P
LA-E122P
LA-E122P
55 59Wednesday, November 09, 2016
55 59Wednesday, November 09, 2016
55 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
Request
5
4
3
Version Change List ( P. I. R. List ) LA-E122P
2
1
TitlePage#
D D
26 ME
27 EE Symbol pin name change
30 2016/05/25 ME
C C
31 6 2016/05/31 EE
32 23 2016/05/31 EE Schematic align SW2_DP1_HPD Add RT380 place near TUSB546 0.2(X01)
33 39 2016/05/31 ME
34 30 2016/06/01 Intel reviwe result
35 28 EMI request
36 31 Audio EA modify (meet GS mark)
37 11 Crystal EA modify
B B
38 34 TPM change to Nuvoton NPCT650JBAYX
39 34
40 12
41 30
42 31
43 27
44 30 Debug card reserve Add RZ131, RZ132 for PORT80_DET# and HOST_DEBUG_TX
A A
45 34
CPU (1/14)
6 EE2016/05/2323
CPU (12/14)
17 EE24
EC MEC5105
32 2016/05/2425 EE
PAD, LED
EC MEC5105
32 2016/05/25
[Type C]PD
Controller TI
DP/USB3
Repeater SW
2329 2016/05/25 EE
TUSB546
34
USH & TPM
38
Keyboard
CPU (1/14)
DP/USB3
Repeater SW
TUSB546
PAD, LED
NGFF Card
LAN Clarkvillie
& RJ45
Codec ALC3246
CPU (6/14)
USH & TPM
USH & TPM
CPU (7/14)
NGFF Card
Codec ALC3246
eDP CONN&
Touch screen
NGFF Card
USH & TPM
Date Issue DescriptionItem
2016/05/23
Owner
Follow Intel PDG AUX topology
S0ix(modern standy) support for VCCPLL_OC
Delete RC179/RC180/RC181/RC182
Add test point T281/T282 for CPU_DP1_AUXN and CPU_DP1_AUXP
Pop RZ120 and Depop UZ34
Add net name VCCSTG_EN(UZ19.4) and connect to RZ120.1
Schematic align Delete RE506 and reserve PD 100K RE95 for TBT_RESET_N_EC_R 0.2(X01)
2016/05/24 ME39
MB ME drawing change H20/H37 change to H_3P1, H10 change to H_3P8, H26 change to H_3P2
UE1.C1 pin name change to GPIO024_nRESETI 0.2(X01)
2016/05/2524
Symbol pin name change
Symbol pin name change
Connector update
UT5.A6/A7/A8/B7 pin name change to GND, UT5.D6 pin name change to HRESET28 0.2(X01)EE
UT9.29 pin name change to SNK_CAD/DCI_DAT
UT9.32 pin name change to HPDIN/DCI_CLK
JUSH1 change to LTCX007Q600
JKBTP1 change to LTCX007Q500
DP HPD base on INTEL PDG Delete RC312/RC242 0.2(X01)
MB ME drawing change Add H39 H_2P3N and change H25 to H_3P2 0.2(X01)
CZ28,CZ29 change from 0.047uF to 0.01uF
CZ27 change from 0.1uF(@)_0201 to 10uF_0603
CZ32/CZ31/CZ29 place near JNGFF1.2/JNGFF1.4
CZ27/CZ30/CZ28 place near JNGFF1.72/JNGFF1.74
2016/06/01
2016/06/01
2016/06/01
EE
EE Change CL22 from 1500P to 150P (SE00000FA80) 0.2(X01)
EE Change RA7, RA8 from 24.9ohm to 16.2ohm (SD00001U900) 0.2(X01)
EE Change CC21, CC22 from 15pf to 12pf 0.2(X01)
EE All page
UZ12 change to NPCT650JB2YX (SA00008EL70)
Add CZ75 4.7uF (SE00000SO00) for +UZ12_TPM
Add CC331 2.2PF (SE07122AC80) for HDA_RST#
Add CC332 2.2PF (SE07122AC80) for HDA_SDIN0
Add CC333 2.2PF (SE07122AC80) for HDA_SDOUT
Add RZ128 0 ohm connect WWAN_COEX3 and WLAN_COEX3
Add RZ129 0 ohm connect WWAN_COEX2 and WLAN_COEX2
Add RZ130 0 ohm connect WWAN_COEX1 and WLAN_COEX1
2016/06/04
2016/06/04
2016/06/04
2016/06/04
EE Vendor schematic review
RF Intel MOW request
RF
Intel reviwe result
(WWAN Coex feature support)
ESD ESD request Change LA10, LA11 to SM01000OZ00 0.2(X01)
EMI EMI request Change LV1 to SM01000NY00 0.2(X01)
2016/06/06 EE 0.2(X01)
EE Schematic align Change loaction RZ90 to RZRZ3622016/06/07 0.2(X01)
Solution Description
Rev.
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)2016/06/01
0.2(X01)2016/06/04
0.2(X01)
0.2(X01)
Request
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (2/5)
EE P.I.R (2/5)
EE P.I.R (2/5)
LA-E122P
LA-E122P
LA-E122P
56 59Wednesday, November 09, 2016
56 59Wednesday, November 09, 2016
56 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
4
3
Version Change List ( P. I. R. List ) LA-E122P
2
1
TitlePage#
D D
46 34
47 23
49
50 Change UD1 from SA00007WE00 to SA00007UR00EE
51 23
C C
55 32
56 31
57 34
58 30
59 24
60 33
61 21
B B
62 11
63 39 EE Intel suggestion2016/07/20 H5, H6 cnage from 1.1mm to 1.0mm 0.3(X02)
64 31 2016/07/20 EMI EMI request to solve EMI noise at Headphone Add RA38, RA39 to AGND and DGND 0.3(X02)
65
67 27 2016/07/22 ESD ESD request Reserve the ESD diode DV7 on USB20_N5 and USB_P5 for system damage issue 0.3(X02)
68 27
69 32
A A
70 25
USH & TPM
DP/USB3
Repeater SW
TUSB546
CPU (7/14)
1248
HDMI CONN
21 EMI request 0.2(X01)2016/06/14
20 2nd source align
DDR4
DP/USB3
Repeater SW
TUSB546
EC MEC5105
USH & TPM
EC MEC5105
Support
EC MEC5105
Codec ALC3246
USH & TPM
NGFF Card
[Type C]PD
Controller TI
EC MEC5105
Support
HDMI CONN
CPU (6/14)
PAD, LED
eDP CONN &
Touch screen
LAN
Clarkvillie
28 EMI EMI request2016/07/21 Change CL22 from 150P to 10P (SE167100J80) 0.3(X02)
& RJ45
EC MEC5105
Support
eDP CONN &
Touch screen
eDP CONN &
Touch screen
EC MEC5105
[Type C]PD
Power
5
Date Issue DescriptionItem
Owner
EE TPM pre-config Reserve RZ363 ohm for GPIO2 and SIO_SLP_S3#2016/06/14 0.2(X01)
EE Schematic align Change net name from MUX1_LP_EN to AUX1_SNOOP_EN#2016/06/14 0.2(X01)
RF RF request Change CC27 from 22pf to 47pf (SE071470J80)2016/06/14 0.2(X01)
EMI
Change RV33,RV34 to 12nH (SHI0000PJ00)
Change RV24,RV25,RV27,RV28,RV30,RV31 (SHI0000QS00)
Change RV26,RV29,RV32,RV35 to SHI0000PJ00 to 300ohm (SD028300080)
2016/06/14
EE 2nd source align Change LT11 from SM01000MS00 to SM01000MO002016/06/14 0.2(X01)
EE2016/07/13 Change UE1 to SA00009GL00 & Depop RE361,Pop RE360,RE362 0.3(X02)
EE2016/07/13 Pop RZ363 and depop (@) RZ111,RZ112, RZ113,QZ9 0.3(X02)
EE2016/07/13 Change RE79 to 62Kohm (SD028620280) 0.3(X02)
EE GPIO map update2016/07/13
For MEC5105K-D1-TN EC sample52 32
TPM pre-config53 34
Board ID54 33
1.UE1.F11 add RTCRST_ON_GPIO122 & reserve RE515@ to QE12.2
2.UE1.B6 change to RTCRST_ON_GPIO141 and add RE514 to QE12.2
EE ESD request (2nd source align)2016/07/13 Change LA10, LA11 back to SM01000NA00 0.3(X02)
EE USH BOM modify2016/07/13
1.RZ10 changed to 100K -Let USH_PWR_STATE# keep low at S5
2.DZ7 depop and pop RZ87 - X8 have no difference JUSH1 pin define with X7
EE Symbol error2016/07/13 Re-link JSIM1 symbol and change SIM_DET to JSIM1.2 0.3(X02)
EE For PD sample 2016/07/13 Change UT5 from SA00009W200 to SA00009W210 0.3(X02)
EE Vendor schematic review2016/07/13 Add net WRST# to UE2.4 and CE500 1uf (SE000000K80) 0.3(X02)
EMI EMI request2016/07/13
EE Sync up schematic with AR2016/07/18 Add PU RC190 to CLKREQ_PCIE#5 0.3(X02)
2016/07/2166 33
EE Vendor schematic review Add RE523 0 ohm for UE2 power pin soft start 0.3(X02)
1. Change RV24 to LV31, RV25 to LV32, RV27 to LV33, RV28 to LV34, RV30
to LV35, RV31 to LV36 and from SHI0000QS00 to SHI0000QT00
2. Change RV33 to LV37, RV34 to LV38 and from SHI0000PJ00 to SHI00006Q00
2016/07/25 ESD ESD request (layout limit) Change DV7 to DV7 and DV8 (SC40000AR00) 0.3(X02)
2016/07/25 EE Vendor schematic review
Change RPE12.1 to RE524 (10Kohm) for EXPANDER_GPU_SMDAT
Change RPE12.2 to RE524 (10Kohm) for EXPANDER_GPU_SMCLK
2016/07/25 EE For UT7 2nd source issue Add RT393 PD 100K ohm to +5V_PD_VDD for discharging instantly 0.3(X02)
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
Solution Description
2
Rev.
0.2(X01)
0.3(X02)
0.3(X02)
0.3(X02)
0.3(X02)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (3/5)
EE P.I.R (3/5)
EE P.I.R (3/5)
LA-E122P
LA-E122P
LA-E122P
57 59Wednesday, November 09, 2016
57 59Wednesday, November 09, 2016
57 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
Request
5
4
3
Version Change List ( P. I. R. List ) LA-E122P
2
1
TitlePage#
D D
71 2016/08/0133
72 2016/08/0138
73 2016/08/0114
74 11 2016/08/01
75 34
76
C C
83 31
84 ME request (LED brightness)39 ME
B B
88
89
90
91 Schematic alignEE2016/09/30
93 23
EC MEC5105
Support
Keyboard
CPU (9/14)
CPU (6/14)
USH & TPM
EC MEC5105
33
Support
32
EC MEC5105
EC MEC5105
3277 Change RE79 to 33kohm (SD028330280) 0.4(X03)
Support
EC MEC5105
3378 EE2016/09/06 Add QE13,RE530,RE531 0.4(X03)
Support
EC MEC5105
EC MEC5105
USH & TPM
EC MEC5105
Support
Codec ALC3246
PAD, LED
EC MEC5105
Support
EC MEC5105
3286
DP/USB3 Repeater
2387
SW TUSB546
EC MEC5105
33
Support
EC MEC5105
33
Support
EC MEC5105
33
Support
DP/USB3 Repeater
23 Reserve RT399~RT402 (0ohm) for TBT RX 0.5(X04)
SW TUSB546
EC MEC5105
3292 Prevent EOS issue on MEC5105
DP/USB3 Repeater
SW TUSB546
Date Issue DescriptionItem
Owner
EE Vendor schematic review Change RE14,RE15,RE18 from 100k ohm to 10k ohm 0.3(X02)
EE Touchpad I2C EA
Chagne RZ20, RZ21 from 4.7k ohm to 2.2k ohm
Change CZ80, CZ81 from 330pf to 10pf
EE Intel suggestion Change RC137 from 1k ohm to 3k ohm 0.3(X02)
EE Intel suggestion Depop RC190 0.3(X02)
2016/09/06 EE TPM change NPCT650VB2YX Change UZ12 from to SA00008EL70 to SA00008EL80 0.4(X03)
Expander I/O change to Microchip MCP23008EE2016/09/06
Change UE2 from SA00009VL00 to SA0000ADQ00, remove RE523
Change RE524, RE525 from 10Kohm to 2.2Kohm
Board IDEE2016/09/06
EC watchdog reserve
Schematic align3279 EE2016/09/06
2016/09/08 EE
2016/09/13 EE
EE
2016/09/13 RF Pop CA54 82pf for DMIC_CLK0 0.4(X03)
EC request for GPIO setting80 32
EC request for GPIO setting81 34
EC watchdog delete82 33 2016/09/13
RF request
Reserve RE526(10K) PU for USH_DET# to +3.3V_ALW 0.4(X03)
Reserve RE505 PU for LOM_CABLE_DETECT#
Add RE532 PU for BCM5882_ALERT#
Pop RZ8, RZ9 for USH_SMBCLK and USH_SMBDAT 0.4(X03)
Delete QE13,RE530,RE531 0.4(X03)
2016/09/13 Change RZ361 from 150ohm to 100ohm (SB12 only) 0.4(X03)
Dell requestEE2016/09/263385
EE2016/09/26
EE2016/09/26
WDT schematic option 2 Use Option2: pop RE361 / depop RE362 0.5(X04)
BITS296634/287982-Cannot wake on LAN
via Type-C to LAN dongle
Add LT13 for +3.3V_VDD_PIC and depop LT11
Change +3.3V_RUN to +3.3V_CPS for this page
WDT schematic2016/09/29 EE Add QE13, CE503, RE530 0.5(X04)
Board ID2016/09/30 EE Change RE79 to 8.2kohm (SD028820180) 0.5(X04)
2016/09/30 EE Change CE12 to 2.2uf and RE33 to 1Kohm 0.5(X04)
BITS294007-Sometimes need to press power
button twice to power on system
2016/10/05 EE Add 100ohm serial resistor on CV2_ON close to UE1.H8 0.5(X04)
2016/10/05 EE Schematic align (BME) Remove RT399~RT402 (0ohm) for TBT RX 0.5(X04)
Solution Description
Rev.
0.3(X02)
0.4(X03)
0.4(X03)
0.5(X04)Reserve RE536/RE537 for resistors for PCH_DPWROK circuit
0.5(X04)
Request
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (4/5)
EE P.I.R (4/5)
EE P.I.R (4/5)
LA-E122P
LA-E122P
LA-E122P
58 59Wednesday, November 09, 2016
58 59Wednesday, November 09, 2016
58 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
5
4
3
Version Change List ( P. I. R. List ) LA-E122P
2
1
TitlePage#
D D
96
97
98
C C
EC MEC5105
Support
EC MEC5105
3295
EC MEC5105
33
Support
All page
All
CPU (7/14)
12
[Type C]PD
2499 TI PD CC1/CC2 CAP change
Controller TI
Date Issue DescriptionItem
Owner
Board IDEE2016/11/043394
EE2016/11/04
MEC5105 change from revB to revC
Change MEC5105 CPN to SA00009GL30
Depop RE361,Pop RE362
MEC5105 revC WDT schematic2016/11/04 EE Pop RE536, Depop QE13, CE503, RE530, UE7, CE5,CE6, RE348 1.0(A00)
0 ohm short pad2016/11/04 EE Change 0 ohm to short pad 1.0(A00)
Service Mode Switch remove2016/11/04 EE Depop SW1, RC222 and pop RC221 1.0(A00)
2016/11/04 EE Change CT85,CT86 to 820pf (SE000003W00) 1.0(A00)
Solution Description
Rev.
1.0(A00)Change RE79 to 4.3kohm (SD028820180)
1.0(A00)
Request
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (5/5)
EE P.I.R (5/5)
EE P.I.R (5/5)
LA-E122P
LA-E122P
LA-E122P
59 59Wednesday, November 09, 2016
59 59Wednesday, November 09, 2016
59 59Wednesday, November 09, 2016
1
1.0
1.0
1.0
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