Compal LA-E121P Schematics Rev0.1
A
COMPAL CONFIDENTIAL
B
C
D
E
1 1
MODEL NAME : CAZ10
PCB NO : LA-E121P
BOM P/N : 431A4231L01
Steamboat 12" AR
Kabylake U
2 2
@ : Nopop Component
EMI@ : EMI Component
@EMI@ : EMI Nopop Component
ESD@ : ESDComponent
@ESD@ : ESD Nopop Component
2016-04-25
REV : 0.1 (X00)
3 3
RF@ : RF Component
@RF@ : RF Nopop Component
CXDP@ : XDP Component
MB PCB
Part Number
DA800186000
Description
PCB 1S5 LA-E121P REV0 MB AR 1
CONN@ : Connector Component
ESPI@ : ESPI interface Component
LPC@ : External ESPI Component (SHD)
Layout Dell logo
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
COPYRIGHT 2016
ALL RIGHT RESERVED
REV:X00
PWB:
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Power CKT : 0425
A
B
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
D
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-E121P
LA-E121P
LA-E121P
152Monday, April 25, 2016
152Monday, April 25, 2016
152Monday, April 25, 2016
E
0.1
0.1
0.1
A
B
C
D
E
Steamboat 12 w/ AR Block Diagram
Memory BUS (DDR4)
1 1
HDMI 1.4
CONN
P22
HDMI
EDP CONN
P28
AR-SP
PD Solution
TPS65982D
PCIE[9]
P29
P29
P29
TBT
P25-26
M.2,3042 Key B
WWAN/LTE/HCA
USB2.0/SMBusUSB2.0/SMBus
PCIE[10]
P31
USB2.0[4]
USB3.0[2]
TypeC
P27
2 2
Intel Jacksonville
WGI219LM
Transformer
RJ45
3 3
eDP 14": Lane x 4; 12" :Lane x 2
PCIE[5][6][7][8]
SW2_DP1
To type CP23-24
DP DeMUX
PS8338B
SW2_DP2
To M2 WiGig card
PCIE[4]
M.2,3030 Key A
WLAN+BT/WIGIG
SW1_DP2
W25Q80DVSSIG
8M 4K sector
P33
reserve
PCIE[3]
P31
USB2.0[7]
P21
SHD_IO
DDI[1]
DDI[2]
INTEL
KABYLAKE_U MCP
SPI
ESPI
SMSC KBC
MEC5105
P33-34
PAGE 6~19
HD Audio I/F
SATA[2]/PCIE[12][11]
W25Q128FVSIQ
128M 4K sector
P8
W25Q128FVSIQ
128M 4K sector
TPM2.0
ATTPM20P-G1MA1-ABF
KB/TP CONN
FAN CONN
P8
reserve
P39
P34
2133MHz
up to 16GB
USB2.0[1]
USB
USB3.0[1]
HDA Codec
ALC3246
P35
)*+,-.!,*%&/%!"#$%0122!3*%!"+%4566
Reverse Type
DDR4-SO-DIMM X1
BANK 0, 1, 2, 3
P20~21
USB2.0[8]
USB2.0[5]
SLGC55544CVTR
USB POWER SHARE
USB2.0[1]_PS
P37
USB3.0[1]
USB2.0[2]
USB3.0[3]
USB2.0[6]
USB3.0[5]
INT.Speaker
Universal Jack
P32
Dig. MIC
P32
P32
P28
Trough eDP Cable
M.2 2280
SSD Conn
P36
LCD Touch
Camera
USB3.0 Conn
PS(Ext Port 1)
Right
USB3.0 Conn
(Ext Port 2)
Left Front
Card reader
RTS5330
P30
P28
P28
Trough eDP Cable
P37
P38
!"#$%&'(
SD4.0
P30
LID SWITCH
LED board
USH CONN
P35
CPU&PCH XDP Port
AUTOMATIC POWER
Smart Card
4 4
TDA8034HN
RFID/NFC
Fingerprint
CONN
SPI
SPI
USH TPM1.2
BCM58102
USH board
USB2.0[10]
P35
SWITCH(APS)
DC/DC Interface
POWER ON/OFF
SW & LED
P14
P11
P41
P40
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
A
B
C
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
D
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Block diagram
Block diagram
Block diagram
LA-E121P
LA-E121P
LA-E121P
E
252Monday, April 25, 2016
252Monday, April 25, 2016
252Monday, April 25, 2016
0.1
0.1
0.1
5
POWER STATES
Signal
State
S0 (Full ON) / M0
S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON ON OFF
D D
S4 (Suspend to DISK) / M3 ON ON OFF
S5 (SOFT OFF) / M3 ON ON OFFLOW HIGHLOW
S3 (Suspend to RAM) / M-O FF
S4 (Suspend to DISK) / M-OFF HIGH
S5 (SOFT OFF) / M-OFF
SLP
S3#
HIGH
LOW HIGH HIGH
LOW HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW ON OFF OFF O FF OFF
SLP
SLP
S5#
S4#
HIGH HIGH
LOW
LOW
SLP
A#
HIGH
HIGH
ALWAYS
PLANE
ON
PM TABLE
+5V_ALW
+3.3V_ALW
+3.3V_ALW_DSW
C C
State
S0
S3
S5 S4/AC
S5 S4/AC doesn't exist
power
plane
+3.3V_ALW_PCH +1.2V_MEM
+RTC_CELL
+1.8V_PRIM
+1.0V_PRIM
+1.0V_PRIM_CORE
+5V_ALW2
+3.3V_ALW2
+3.3V_RTC_LDO
+1.0V_MPHYGT
ON
ON
+3.3V_CV2
+2.5V_MEM
+1.0V_VCCST
+5V_RUN
+3.3V_RUN
+0.6V_DDR_VTT
+1.8V_RUN
+VCC_CORE
+VCC_GT
+VCC_SA
+1.0VS_VCCIO
ON ON
ON
OFF
OFFOFF
OFFON
OFF
OFF
M
PLANE
ON
4
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
CLOCKS
OFF
OFF
OFF
USB3.0
USB3.0-1
USB3.0-2
USB3.0-3
USB3.0-4
USB3.0-5
USB3.0-6
SSIC
SSIC
3
PCIE
SATA
JUSB1-->Right
M.2 3042(LTE)
JUSB2-->Left Front
JUSB3-->Left Rear (SB14 only)
PCIE-1
PCIE-2
PCIE-3
PCIE-4
Card Reader
NA
M.2 3030(WLAN)
M.2 3030(WIGIG)
PCIE-5
PCIE-6
PCIE-7
PCIE-8
PCIE-9
PCIE-10
PCIE-11
PCIE-12
SATA-0
SATA-1
SATA-1*
SATA-2
Alpine Ridge - SP
LOM
M.2 3042( HCA)
M.2 2280 SSD
(PCIex2 or SATA)
&/(%"!*%0122!3*%=>)?@
2
USB PORT#DESTINATION
1
2
3
4
5
6
7
8
9
10
DESTINATION
JUSB1-->Right
JUSB2-->Left Front
JUSB3-->Left Rear (SB14 only)
M2 3042(WWAN)
Camera
Card Reader
M.2 3030(BT)
Touch Screen
NA
USH
1
78%9!":;<
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
AR use 1086PP
Non AR use 1080PP
5
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Port assignment
Port assignment
Port assignment
LA-E121P
LA-E121P
LA-E121P
1
352Monday, April 25, 2016
352Monday, April 25, 2016
352Monday, April 25, 2016
0.1
0.1
0.1
5
Barrel
ADAPTER
D D
CHARGER
ISL88738
(PU901)
Type-C
ADAPTER
+PWR_SRC
SY8210A
(PU200)
SYX196D
(PU301)
SY8288C
(PU102)
4
SIO_SLP_S4#
0.6V_DDR_VTT_ON
SIO_SLP_SUS#
ALWON
+1.2V_MEM
+0.6V_DDR_VTT
+1.0V_PRIM
+5V_ALW
+5V_ALW2
TPS22961
(UZ26)
3
SIO_SLP_SUS#
SIO_SLP_S4#
+VCC_SFR_OC
TPS62134C
(PU401)
TPS62134D
(PU402)
EM5209
(UZ4)
RUN_ON
SIO_SLP_SUS#
RUN_ON
TPS22961
(UZ19)
TPS22961
(UZ21)
+1.0VS_VCCIO
+1.0V_PRIM_CORE
+5V_RUN
2
1
CPU PWR
PCH PWR
GT3 PWR
AUD_PW R_EN
Peripheral Device PWR
TYPE-C Power
+5V_RUN_AUDIO
RUN_ON
SIO_SLP_S0#
SIO_SLP_S4#
EM5209
(@UZ5)
+1.0V_VCCSTG
+1.0V_VCCST
BATTERY
SY8288B
C C
(PU100)
ALWON
+3.3V_RTC_LDO
+3.3V_ALW2
SLGC55544C
(UI3)
SY6288
(UI1)
USB_PWR_SHR_VBUS_EN
USB_PWR_EN1#
+5V_USB_CHG_PWR
+USB_EX2_PWR
+3.3V_ALW
RT8097A
(PU501)
+5V_ALW
CSD97374C
(PU604)
IMVP_VR_ON
+VCC_GT+VCC_SA
CSD97374C
(PU603)
IMVP_VR_ON
+VCC_CORE
TPS65982D
(UT5)
ISL95857
(PU602)
IMVP_VR_ON
B B
+PP_HV(5V~20V)
AO6405
(QV1)
EN_INVPWR
+BL_PWR_SRC
ABCDEF
+TBTA_Vbus_1(5V~20V)
EM5209
(UZ2)
EM5209
(UZ3)
EM5209
(UZ4)
G524B1T11U
(UV24)
SIO_SLP_SUS#
SIO_SLP_LAN#
AUX_EN_ WOWL
@SIO_SLP_WL AN#
SIO_SLP_SUS#
@PCH_ALW_ ON
RUN_ON
3.3V_WWAN_EN
ENVCC_PCH
+1.8V_PRIM
+3.3V_LAN
+3.3V_WLAN
+3.3V_ALW_PCH
+3.3V_RUN
+3.3V_WWAN
+LCDVDD
AOZ1336
(UZ8)
LP2301
(QV8)
LP2301A
(QZ1)
EM5209
(@UZ5)
RUN_ON
3.3V_TS_EN
3.3V_CAM_EN#
AUD_PW R_EN
+1.8V_RUN
+3.3V_TSP
+3.3V_CAM
+3.3V_RUN_AUDIO
A A
AP2204
(UT8)
5
+5V_ALW
+5V_TBT_VBUS
AP2112K
(UT7)
4
+3.3V_VDD_PIC
AP7361C
(PU503)
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
SIO_SLP_S4#
+2.5V_MEM
for DDR4
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Power rails
Power rails
Power rails
LA-E121P
LA-E121P
LA-E121P
1
452Monday, April 25, 2016
452Monday, April 25, 2016
452Monday, April 25, 2016
0.1
0.1
0.1
5
AW44
BB43
KBL-U
D D
AW45 AW42
03
SML1_SMBDATA
SML1_SMBCLK
D8E11
03
00
00
AY44
BB39
UPD2_SMBCLK
D7
UPD2_SMBDAT
E7
MEM_SMBCLK
MEM_SMBDATA
SML0_SMBCLK
SML0_SMBDATA
1K
1K
4
+3.3V_ALW_PCH
2.2K
2.2K
499
499
+3.3V_ALW
1K
1K
+3.3V_ALW_PCH
+3.3V_ALW_PCH
3
DMN65D8LDW-7
DMN65D8LDW-7
28
31
LOM
2
1
2.2K
2.2K
+3.3V_RUN
202
200
53
51
DIMMA
XDP
@2.2K
@2.2K
B3
E5
C12
E10
C3
B4
USH_SMBCLK
USH_SMBDAT
UPD1_SMBCLK
UPD1_SMBDAT
2.2K
2.2K
C C
01
01
02
02
KBC
04
04
+3.3V_ALW
+3.3V_ALW
DMN66D0LDW-7
DMN66D0LDW-7
2.2K
2.2K
2.2K
2.2K
+3.3V_CV2
M9
USH
L9
USH/B
+3.3V_TBTA_FLASH
B5
PD
A5
MEC 5105
F7
05
B6
05
A12
06
N10
B B
A A
06
07
07
08 C5
08
09
09
1010M3
EXPANDER_GPU_SMCLK
M4
EXPANDER_GPU_SMDATA
M7
C8
F6
E9
N2
PBAT_CHARGER_SMBCLK
PBAT__CHARGER_SMBDAT
2.2K
2.2K
2.2K
2.2K
+3.3V_ALW
+3.3V_ALW
100 ohm
100 ohm
Expander IO
Charger
7
BATTERY
6
CONN
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Port assignment
Port assignment
Port assignment
LA-E121P
LA-E121P
LA-E121P
1
552Monday, April 25, 2016
552Monday, April 25, 2016
552Monday, April 25, 2016
0.1
0.1
0.1
5
4
3
2
1
+3.3V_RUN
CPU_DP1_CTRL_CLK
RC175 2.2K_0402_5%
RC178 2.2K_0402_5%
D D
RC176 2.2K_0402_5%
RC177 2.2K_0402_5%
12
CPU_DP1_CTRL_DATA
12
CPU_DP2_CTRL_CLK
12
CPU_DP2_CTRL_DATA
12
78G78HI
J465GK!"%78H
C)L@@LG78H
+1.0VS_VCCIO
C C
B B
CPU_DP1_N0<23>
CPU_DP1_P0<23>
CPU_DP1_N1<23>
CPU_DP1_P1<23>
CPU_DP1_N2<23>
CPU_DP1_P2<23>
CPU_DP1_N3<23>
CPU_DP1_P3<23>
CPU_DP2_N0<21>
CPU_DP2_P0<21>
CPU_DP2_N1<21>
CPU_DP2_P1<21>
CPU_DP2_N2<21>
CPU_DP2_P2<21>
CPU_DP2_N3<21>
CPU_DP2_P3<21>
12
CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA
CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA
EDP_COMP
CPU_DP1_CTRL_CLK<23>
CPU_DP1_CTRL_DATA<23>
CPU_DP2_CTRL_CLK<21>
CPU_DP2_CTRL_DATA<21>
@
T120
PAD~D
RC2 24.9_0402_1%
COMPENSATION PU FOR eDP
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
UC1A
CPU@
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DD PB_CTRLCLK
L12
GPP_E19/DD PB_CTRLDATA
N7
GPP_E20/DD PC_CTRLCLK
N8
GPP_E21/DD PC_CTRLDATA
N11
GPP_E22/DD PD_CTRLCLK
N12
GPP_E23/DD PD_CTRLDATA
E52
EDP_RCOMP
KBL-U_BGA1356
SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0
UC1I
CPU@
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
D33
CSI2_DP5
A31
CSI2_DN6
B31
CSI2_DP6
A33
CSI2_DN7
B33
CSI2_DP7
A29
CSI2_DN8
B29
CSI2_DP8
C28
CSI2_DN9
D28
CSI2_DP9
A27
CSI2_DN10
B27
CSI2_DP10
C27
CSI2_DN11
D27
CSI2_DP11
KBL-U_BGA1356
SKL-U
DDI
DISPLAY SI DEBANDS
SKL_ULT
EDP
1 OF 20
GPP_F13/EM MC_DATA0
GPP_F14/EM MC_DATA1
GPP_F15/EM MC_DATA2
GPP_F16/EM MC_DATA3
GPP_F17/EM MC_DATA4
GPP_F18/EM MC_DATA5
GPP_F19/EM MC_DATA6
GPP_F20/EM MC_DATA7
GPP_F21/EM MC_RCLK
EDP_DISP_UTIL
GPP_E13/DD PB_HPD0
GPP_E14/DD PC_HPD1
GPP_E15/DD PD_HPD2
GPP_E16/DD PE_HPD3
GPP_E17/ED P_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLA SHTRIG
EMMC
GPP_F22/EM MC_CLK
GPP_F12/EM MC_CMD
EMMC_RCOMP
9 OF 20
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
CSI2_COMP
EMMC_RCOMP
EDP_TXN0 <28>
EDP_TXP0 <28>
EDP_TXN1 <28>
EDP_TXP1 <28>
CPU_DP1_AUXN
CPU_DP1_AUXP
CPU_DP3_AUXN
CPU_DP3_AUXP
CPU_DP1_HPD <23>
CPU_DP2_HPD <21>
EDP_HPD <28>
PANEL_BKLEN <28>
EDP_BIA_PWM <28>
ENVDD_PCH <28,33>
1 2
RC3
1 2
RC4 200_0402_1%
100_0402_1%
TBT_FORCE_PWR <23>
EDP_AUXN <28>
EDP_AUXP <28>
CPU_DP1_AUXN <23>
CPU_DP1_AUXP <23>
CPU_DP2_AUXN <21>
CPU_DP2_AUXP <21>
@
T1
PAD~D
@
T2
PAD~D
CPU_DP1_AUXN
CPU_DP2_AUXN
CPU_DP2_AUXP
CPU_DP1_AUXP
EDP_HPD
CPU_DP1_HPD
CPU_DP2_HPDGPP_E23
1 2
RC179 100K_0402_5%
1 2
RC181 100K_0402_5%
1 2
RC182 100K_0402_5%
1 2
RC180 100K_0402_5%
1 2
RC1 100K_0402_5%
1 2
RC312 100K_0402_5%
@
1 2
RC242 100K_0402_5%
+3.3V_RUN
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (1/14)
CPU (1/14)
CPU (1/14)
LA-E121P
LA-E121P
LA-E121P
652Monday, April 25, 2016
652Monday, April 25, 2016
652Monday, April 25, 2016
1
0.1
0.1
0.1
5
4
3
2
1
M!3%448'
DDR_A_DQS#[0..7]<20>
2 OF 20
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52
AM70
AM69
AT69
AT70
BA64
AY64
AY60
BA60
BA38
AY38
AY34
BA34
BA30
AY30
AY26
BA26
AW50
AT52
AY67
AY68
BA67
AW67
DDR_A_D[0..63]<20>
DDR_A_DQS[0..7]<20>
DDR_A_MA[0..16]<20>
DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#1
DDR_A_CLK1
DDR_A_CKE0
DDR_A_CKE1
DDR_A_CKE2
DDR_A_CKE3
DDR_A_CS#0
DDR_A_CS#1
DDR_A_ODT0
DDR_A_ODT1
DDR_A_MA5
DDR_A_MA9
DDR_A_MA6
DDR_A_MA8
DDR_A_MA7
DDR_A_BG0
DDR_A_MA12
DDR_A_MA11
DDR_A_ACT#
DDR_A_BG1
DDR_A_MA13
DDR_A_MA15
DDR_A_MA14
DDR_A_MA16
DDR_A_BA0
DDR_A_MA2
DDR_A_BA1
DDR_A_MA10
DDR_A_MA1
DDR_A_MA0
DDR_A_MA3
DDR_A_MA4
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_ALERT#
DDR_A_PARITY
+DDR_VREF_A_DQ
+DDR_VREF_B_DQ
DDR_A_CLK#0 <20>
DDR_A_CLK0 <20>
DDR_A_CLK#1 <20>
DDR_A_CLK1 <20>
DDR_A_CKE0 <20>
DDR_A_CKE1 <20>
@
T3
PAD~D
@
T4
PAD~D
DDR_A_CS#0 <20>
DDR_A_CS#1 <20>
DDR_A_ODT0 <20>
DDR_A_ODT1 <20>
DDR_A_BG0 <20>
DDR_A_ACT# <20>
DDR_A_BG1 <20>
DDR_A_BA0 <20>
DDR_A_BA1 <20>
DDR0_PAR,DDR0_ALERT# for DDR4
DDR_A_ALERT# <20>
DDR_A_PARITY <20>
+DDR_VREF_CA
@
T132
PAD~D
@
T226
PAD~D
DDR_VTT_CTRL <20>
UC1C
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
KBL-U_BGA1356
CPU@
SKL-U
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR CH - B
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR1_ALERT#
DDR1_PAR
3 OF 20
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
DDR1_PAR,DDR1_ALERT# for DDR4
DDR_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DDR_DRAMRST# <20>
DDR4, Ballout for side by side(Interleave)
D D
UC1B
CPU@
DDR_A_D0
AL71
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
C C
B B
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
KBL-U_BGA1356
SKL-U
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR CH - A
DDR0_ODT[1]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR0_ALERT#
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
DDR0_MA[3]
DDR0_MA[4]
DDR0_PAR
DDR4 COMPENSATION SIGNALS
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil
A A
1 2
RC5 121_0402_1%
1 2
RC6 80.6_0402_1%
1 2
RC7 100_0402_1%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (2/14)
CPU (2/14)
CPU (2/14)
LA-E121P
LA-E121P
LA-E121P
752Monday, April 25, 2016
752Monday, April 25, 2016
752Monday, April 25, 2016
1
0.1
0.1
0.1
5
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236
PCH_SPI_CLK
PCH_SPI_D1
CXDP@
1 2
PCH_SPI_DO_XDP<14>
D D
C C
B B
A A
PCH_SPI_DO2_XDP<14>
PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R
33_0402_5%
@EMI@
12
RC28
33P_0402_50V8J
@EMI@
12
CC7
RC10 1K_0402_1%
CXDP@
1 2
RC11 1K_0402_1%
PCH_SPI_CS#2<35>
PCH_CL_CLK1<31>
+1.8V?
+3.3V_RUN
+3.3V_1.8V_ESPI
33_0402_5%
@EMI@
12
RC29
33P_0402_50V8J
@EMI@
12
CC8
PCH_SPI_CS#0_R1
PCH_SPI_D2_R1 PCH_SPI_CLK_0_R
PCH_SPI_CS#1_R1
PCH_SPI_D2_R1
PCH_CL_DATA1<31>
PCH_CL_RST1#<31>
RC13 10K_0402_5%LPC@
SIO_RCIN#<33>
ESPI_ALERT#<33>
RC21 8.2K_0402_1%
+3.3V_SPI
RC37 0_0402_5%
RC39 33_0402_5%
RC42 0_0402_5%@
RC43 33_0402_5%
@
PCH_SPI_D0
PCH_SPI_D2
PCH_SPI_D3
PCH_SPI_CS#0
PCH_SPI_CS#1
PCH_SPI_CS#2
12
12
PCH_SPI_D2_R1
RC30 1K_0402_5%
@
RC31 1K_0402_5%
@
RC316 1K_0402_5%
@
1 2
1 2
1 2
1 2
12
PCH_SPI_D3_R1
12
PCH_SPI_D3_R1
12
03/02:follow Intel MOW_2015WW06
4
UC1E
AV2
SPI0_CLK
AW3
SPI0_MISO
AV3
SPI0_MOSI
AW2
SPI0_IO2
AU4
SPI0_IO3
AU3
SPI0_CS0#
AU2
SPI0_CS1#
AU1
SPI0_CS2#
M2
GPP_D1/SPI1 _CLK
M3
GPP_D2/SPI1 _MISO
J4
GPP_D3/SPI1 _MOSI
V1
GPP_D21/SP I1_IO2
V2
GPP_D22/SP I1_IO3
M1
GPP_D0/SPI1 _CS#
G3
CL_CLK
G2
CL_DATA
G1
CL_RST#
AW13
GPP_A0/RCIN #
AY11
GPP_A6/SER IRQ
KBL-U_BGA1356
PCH_SPI_CS#0_R2
PCH_SPI_D1_0_R
PCH_SPI_D2_0_R
PCH_SPI_CS#1_R2
PCH_SPI_D1_1_R
PCH_SPI_D2_1_R
CPU@
SPI - FLASH
SPI - TOUCH
C LINK
PCH_SPI_D1_R1<35>
PCH_SPI_D0_R1<35>
PCH_SPI_CLK_R1<35>
128Mb Flash ROM
1
2
3
4
W25Q128FVSIQ_SO8
128Mb Flash ROM
@
1
2
3
4
W25Q128FVSIQ_SO8
PCH_SPI_CLK_R1
PCH_SPI_D0_R1
PCH_SPI_D1_R1
UC5
/CS
IO1
IO2
GND
UC6
/CS
IO1
IO2
GND
SKL-U
LPC
SOFTWARE TAA
PCH_SPI_D1_R1
PCH_SPI_D0_R1
PCH_SPI_CLK_R1
PCH_SPI_D3_R1
RC407 33_0402_5%
@
RC408 33_0402_5%
@
RC409 33_0402_5%
@
RC410 33_0402_5%
@
+3.3V_SPI
8
VCC
PCH_SPI_D3_0_R
7
IO3
6
CLK
PCH_SPI_D0_0_R
5
IO0
+3.3V_SPI
8
VCC
PCH_SPI_D3_1_R
7
IO3
PCH_SPI_CLK_1_R
6
CLK
PCH_SPI_D0_1_R
5
IO0
SMBUS, SMLINK
GPP_C0/SMB CLK
GPP_C1/SMB DATA
GPP_C2/SMB ALERT#
GPP_C3/SML 0CLK
GPP_C4/SML 0DATA
GPP_C5/SML 0ALERT#
GPP_C6/SML 1CLK
GPP_C7/SML 1DATA
GPP_B23/SM L1ALERT#/PCHH OT#
GPP_A1/LAD 0/ESPI_IO0
GPP_A2/LAD 1/ESPI_IO1
GPP_A3/LAD 2/ESPI_IO2
GPP_A4/LAD 3/ESPI_IO3
GPP_A5/LFR AME#/ESPI_CS#
GPP_A14/SU S_STAT#/ESPI_RE SET#
GPP_A9/CLK OUT_LPC0/ESPI_CL K
GPP_A10/CLK OUT_LPC1
GPP_A8/CLK RUN#
RPC1
PCH_SPI_D1_0_R
1 8
PCH_SPI_D0_0_R
2 7
PCH_SPI_CLK_0_R
3 6
PCH_SPI_D3_0_R
4 5
33_0804_8P4R_5%
1 2
1 2
1 2
1 2
CC9
1 2
0.1U_0201_10V6K
CC10
@
1 2
0.1U_0201_10V6K
3
5 OF 20
PCH_SPI_D3_1_RPCH_SPI_D3_R1
PCH_SPI_CLK_1_R
PCH_SPI_D0_1_R
PCH_SPI_D1_1_R
R7
R8
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
+3.3V_SPI
MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#
SML0_SMBCLK
SML0_SMBDATA
GPP_C5
SML1_SMBCLK
SML1_SMBDATA
GPP_B23
ESPI_IO0_R
ESPI_IO1_R
ESPI_IO2_R
ESPI_IO3_R
ESPI_CLK
PCI_CLK_LPC1
RC32 0_0402_5%
@
RC33 0_0402_5%
RC34 0_0402_5%
RC35 0_0402_5%
RC36 0_0402_5%
RC38 0_0402_5%
RC40 0_0402_5%
+3.3V_ALW_PCH
RC41 0_0402_5%
SML0_SMBCLK <29>
SML0_SMBDATA <29>
SML1_SMBCLK <33>
SML1_SMBDATA <33>
1 2
RC366
1 2
RC367
1 2
RC368
1 2
RC369
ESPI_CS# <33,34>
ESPI_RESET# <33>
1 2
RC16
EMI@
ESPI_CLK_5105
SML0_SMBCLK
SML1_SMBCLK
MEM_SMBCLK
1 2
RC22@ 22_0402_5%
CLKRUN# <33>
PCH_SPI_CS#1_R1
12
PCH_SPI_D0_R1
12
PCH_SPI_D1_R1
12
PCH_SPI_CLK_R1
12
PCH_SPI_CS#0_R1
12
PCH_SPI_D2_R1
12
PCH_SPI_D3_R1
12
12
2
15_0402_5%
15_0402_5%
15_0402_5%
15_0402_5%
15_0402_5%
CHECK,LPC_CLK FOR DEBUG CARD?
ESPI_IO0 <33,34>
ESPI_IO1 <33,34>
ESPI_IO2 <33,34>
ESPI_IO3 <33,34>
8M%8+N1+0*
1 2
CC316@RF@ 33P_0402_50V8J
1 2
CC318@RF@ 33P_0402_50V8J
1 2
CC319@RF@ 33P_0402_50V8J
1 2
CC320@RF@ 33P_0402_50V8J
Place close CPU side
E-T_6705K-Y20N-00L
22
21
PCH_SPI_CS#1
PCH_SPI_D0
PCH_SPI_D1
PCH_SPI_CLK
PCH_SPI_CS#0
PCH_SPI_D2
PCH_SPI_D3
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
JSPI1
CONN@
MEM_SMBCLK
MEM_SMBDATA
DMN65D8LDW-7_SOT363-6
ESPI_CLK_5105 <33,34>
GND2
GND1
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+3.3V_RUN
5
3 4
QC2B
2
1
6
QC2A
DMN65D8LDW-7_SOT363-6
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
SML0_SMBCLK
SML0_SMBDATA
Reserve
SML0_SMBCLK
SML0_SMBDATA
CLKRUN#
PCH_SMB_ALERT#
TLS CONFIDENTIALITY
HIGH
LOW(DEFAULT)
WEAK INTERNAL 20K PD
GPP_C5
EC interface
HIGH
LOW(DEFAULT)
WEAK INTERNAL 20k PD
GPP_B23
EXI BOOT STALL BYPASS
HIGH
LOW(DEFAULT)
WEAK INTERNAL PD
1
M!3%?8I)?
DDR_XDP_WAN_SMBCLK <14,20>
DDR_XDP_WAN_SMBDAT <14,20>
1 2
RC318 2.2K_0402_5%
1 2
RC319 2.2K_0402_5%
1 2
RC12 1K_0402_5%
1 2
RC14 1K_0402_5%
1 2
RC15 1K_0402_5%
1 2
RC17 1K_0402_5%
1 2
RC347 499_0402_1%
1 2
RC348 499_0402_1%
1 2
RC19 499_0402_1%@
1 2
RC20 499_0402_1%@
1 2
RC27 8.2K_0402_5%LPC@
+3.3V_ALW_PCH
1 2
RC23 2.2K_0402_5%
ENABLE
DISABLE
+3.3V_ALW_PCH
1 2
RC25 4.7K_0402_5%ESPI@
ESPI
LPC
+3.3V_ALW_PCH
1 2
RC317 150K_0402_5%
ENABLED
DIABLED
+3.3V_RUN
+3.3V_ALW_PCH
+3.3V_LAN
+3.3V_RUN
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (3/14)
CPU (3/14)
CPU (3/14)
LA-E121P
LA-E121P
LA-E121P
852Monday, April 25, 2016
852Monday, April 25, 2016
852Monday, April 25, 2016
1
0.1
0.1
0.1
5
4
3
2
1
M!3%?8I)?
UC1F
+3.3V_RUN
BBS_BIT6
AH10
AH11
AH12
AF11
AF12
AN8
AP7
AP8
AR7
AM5
AN7
AP5
AN5
AB1
AB2
AB3
AD1
AD2
AD3
AD4
AH9
W4
U7
U6
U8
U9
D D
RC282 100K_0402_5%
RC237 10K_0402_5%
RC402 49.9K_0402_1%@
RC403 49.9K_0402_1%@
+3.3V_ALW_PCH
RC283 10K_0402_5%
RC330 49.9K_0402_1%
RC331 49.9K_0402_1%
C C
3.3V_TS_EN
12
SIO_EXT_SCI#
12
LPSS_UART2_RXD
12
LPSS_UART2_TXD
12
SIO_EXT_WAKE#
12
LPSS_UART2_RXD
12
LPSS_UART2_TXD
12
RC405 100K_0402_5%@
TPM_PIRQ#<35>
SIO_EXT_SCI#<33>
3.3V_TS_EN<28>
12
SBIOS_TX<34>
I2C1_SDA_T P<39>
I2C1_SCK_T P<39>
ONE_DIMM#
NRB_BIT
GPP_C8
LPSS_UART2_RXD
LPSS_UART2_TXD
CPU@
LPSS ISH
GPP_B15/GSPI0 _CS#
GPP_B16/GSPI0 _CLK
GPP_B17/GSPI0 _MISO
GPP_B18/GSPI0 _MOSI
GPP_B19/GSPI1 _CS#
GPP_B20/GSPI1 _CLK
GPP_B21/GSPI1 _MISO
GPP_B22/GSPI1 _MOSI
GPP_C8/UAR T0_RXD
GPP_C9/UAR T0_TXD
GPP_C10/UA RT0_RTS#
GPP_C11/UA RT0_CTS#
GPP_C20/UA RT2_RXD
GPP_C21/UA RT2_TXD
GPP_C22/UA RT2_RTS#
GPP_C23/UA RT2_CTS#
GPP_C16/I2C 0_SDA
GPP_C17/I2C 0_SCL
GPP_C18/I2C 1_SDA
GPP_C19/I2C 1_SCL
GPP_F4/I2C2_ SDA
GPP_F5/I2C2_ SCL
GPP_F6/I2C3_ SDA
GPP_F7/I2C3_ SCL
GPP_F8/I2C4_ SDA
GPP_F9/I2C4_ SCL
KBL-U_BGA1356
SKL-U
GPP_D9
GPP_D10
GPP_D11
GPP_D12
GPP_D5/ISH_ I2C0_SDA
GPP_D6/ISH_ I2C0_SCL
GPP_D7/ISH_ I2C1_SDA
GPP_D8/ISH_ I2C1_SCL
GPP_F10/I2C5 _SDA/ISH_I2C2_SD A
GPP_F11/I2C5 _SCL/ISH_I2C2_SC L
GPP_D13/ISH _UART0_RXD/SM L0BDATA/I2C4B_ SDA
GPP_D14/ISH _UART0_TXD/SM L0BCLK/I2C4B_SC L
GPP_D15/ISH _UART0_RTS#
GPP_D16/ISH _UART0_CTS#/SM L0BALERT#
GPP_C12/UA RT1_RXD/ISH_UA RT1_RXD
GPP_C13/UA RT1_TXD/ISH_UA RT1_TXD
GPP_C14/UA RT1_RTS#/ISH_U ART1_RTS#
GPP_C15/UA RT1_CTS#/ISH_U ART1_CTS#
GPP_A18/ISH _GP0
GPP_A19/ISH _GP1
GPP_A20/ISH _GP2
GPP_A21/ISH _GP3
GPP_A22/ISH _GP4
GPP_A23/ISH _GP5
GPP_A12/BM _BUSY#/ISH_GP6
6 OF 20
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
MEM_INTERLEAVED
AR_DET#
ISH_I2C2_SD A
ISH_I2C2_SC L
CLKDET#
TPM_TYPE
LID_CL#_PCH
ISH_I2C2_SD A <31>
ISH_I2C2_SC L <31>
9/24: Reserve for embedded location ,refer Intel PDG 0.9
ISH_UART0 _RXD <31>
ISH_UART0 _TXD <31>
ISH_UART0 _RTS# < 31>
ISH_UART0 _CTS# < 31>
SIO_EXT_WAKE# <33>
RTD3_CIO_PWR_EN <23>
LCD_CBL_DET# <28>
@
T258
PAD~D
@
T268
PAD~D
OCCP7%O8Q>C%;0%R&SLT
WWAN
WLAN
ISH_I2C2_SD A
ISH_I2C2_SC L
LCD_CBL_DET#
+1.8V_RUN
1 2
RC363 1K_0402_5%
1 2
RC362 1K_0402_5%
+3.3V_RUN
1 2
RC287 100K_0402_5%
TPM_TYPE
+3.3V_RUN
NRB_BIT
RC186 4.7K_0402_5%@
12
NO REBOOT STRAP
HIGH
LOW(DEFAULT)
Weak IPD
B B
+3.3V_ALW_PCH
RC184 8.2K_0402_5%
@
No REBOOT
REBOOT ENABLE
BBS_BIT6
12
+3.3V_RUN
10K_0402_5%
1 2
10K_0402_5%
12
DIMM Detect
HIGH
LOW
RC267
@
RC268
ONE_DIMM#
1 DIMM
2 DIMM
+5V_ALW
LPSS_UART2_TXD
LPSS_UART2_RXD
CONN@
JUART1
1
1
2
2
3
3
4
4
5
GND
6
GND
CVILU_CI1804M1VRA-NH
MEM_INTERLEAVED
+3.3V_ALW_PCH +3.3V_ALW_PCH
RC371
10K_0402_5%
1 2
AR_DET#
Reserved
RC400
@
10K_0402_5%
1 2
RC349 100_0402_1%@
1 2
BOOT BIOS Destination(Bit 6)
HIGH
LOW(DEFAULT)
Internal 20k PD
A A
LPC
SPI
12
@
10K_0402_5%
RC372
DIMM TYPE
HIGH Interleave
12
10K_0402_5%
RC401
AR_DET#
NON ARHIGH
LOW ARLOW Non-Interleave
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (4/14)
CPU (4/14)
CPU (4/14)
LA-E121P
LA-E121P
LA-E121P
952Monday, April 25, 2016
952Monday, April 25, 2016
952Monday, April 25, 2016
1
0.1
0.1
0.1
5
4
3
2
1
M!3%78U)*+,-.!,*&/I&'
UC1H
CPU@
PCIE/USB3/SATA
D D
Card Reader RTS5330----->
M.2 3030(WLAN) --->
M.2 3030(WiGig) --->
AR(PCIE5~8) --->
C C
10/100/1G LAN --->
M.2 3042(HCA)--->
M2 2280 SSD --->
B B
USB3_PRX_DTX_N5<30>
USB3_PRX_DTX_P5<30>
USB3_PTX_DRX_N5<30>
USB3_PTX_DRX_P5<30>
PCIE_PRX_DTX_N3<31>
PCIE_PRX_DTX_P3<31>
PCIE_PTX_DRX_N3<31>
PCIE_PTX_DRX_P3<31>
PCIE_PRX_DTX_N4<31>
PCIE_PRX_DTX_P4<31>
PCIE_PTX_DRX_N4<31>
PCIE_PTX_DRX_P4<31>
PCIE_PRX_DTX_N5<23>
PCIE_PRX_DTX_P5<23>
PCIE_PTX_DRX_N5<23>
PCIE_PTX_DRX_P5<23>
PCIE_PRX_DTX_N6<23>
PCIE_PRX_DTX_P6<23>
PCIE_PTX_DRX_N6<23>
PCIE_PTX_DRX_P6<23>
PCIE_PRX_DTX_N7<23>
PCIE_PRX_DTX_P7<23>
PCIE_PTX_DRX_N7<23>
PCIE_PTX_DRX_P7<23>
PCIE_PRX_DTX_N8<23>
PCIE_PRX_DTX_P8<23>
PCIE_PTX_DRX_N8<23>
PCIE_PTX_DRX_P8<23>
PCIE_PRX_DTX_N9<29>
PCIE_PRX_DTX_P9<29>
PCIE_PTX_DRX_N9<29>
PCIE_PTX_DRX_P9<29>
PCIE_PRX_DTX_N10<31>
PCIE_PRX_DTX_P10<31>
PCIE_PTX_DRX_N10<31>
PCIE_PTX_DRX_P10<31>
1 2
RC45 100_0402_1%
CPU_XDP_PRDY#<14>
CPU_XDP_PREQ#<14>
PCIE_PRX_DTX_N11<36>
PCIE_PRX_DTX_P11<36>
PCIE_PTX_DRX_N11<36>
PCIE_PTX_DRX_P11<36>
PCIE_PRX_DTX_N12<36>
PCIE_PRX_DTX_P12<36>
PCIE_PTX_DRX_N12<36>
PCIE_PTX_DRX_P12<36>
PCIE_RCOMPN
PCIE_RCOMPP
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA #
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
KBL-U_BGA1356
SKL-U
SSIC / USB3
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB2
USB2_VBUSSENSE
GPP_E9/USB 2_OC0#
GPP_E10/US B2_OC1#
GPP_E11/US B2_OC2#
GPP_E12/US B2_OC3#
GPP_E4/DEV SLP0
GPP_E5/DEV SLP1
GPP_E6/DEV SLP2
GPP_E0/SAT AXPCIE0/SATAGP0
GPP_E1/SAT AXPCIE1/SATAGP1
GPP_E2/SAT AXPCIE2/SATAGP2
GPP_E8/SAT ALED#
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
8 OF 20
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
USBCOMP
USB2_ID
AG3
USB2_VBUSSENSE
AG4
A9
C9
D9
USB_OC3#
B9
J1
J2
J3
HDD_DET#
H2
M3042_PCIE#_SATA
H3
M2280_PCIE_SATA#
G4
H1
SATALED#
USB3_PRX_DTX_N1 <37>
USB3_PRX_DTX_P1 <37>
USB3_PTX_DRX_N1 <37>
USB3_PTX_DRX_P1 <37>
USB3_PRX_DTX_N2 <31>
USB3_PRX_DTX_P2 <31>
USB3_PTX_DRX_N2 <31>
USB3_PTX_DRX_P2 <31>
USB3_PRX_DTX_N3 <38>
USB3_PRX_DTX_P3 <38>
USB3_PTX_DRX_N3 <38>
USB3_PTX_DRX_P3 <38>
USB20_N1 <37>
USB20_P1 <37>
USB20_N2 <38>
USB20_P2 <38>
USB20_N4 <31>
USB20_P4 <31>
USB20_N5 <28>
USB20_P5 <28>
USB20_N6 <30>
USB20_P6 <30>
USB20_N7 <31>
USB20_P7 <31>
USB20_N8 <28>
USB20_P8 <28>
USB20_N10 <35>
USB20_P10 <35>
1 2
RC44 113_0402_1%
1 2
RC337 0_0402_5%
1 2
RC338 1K_0402_5%
USB_OC0# <37>
USB_OC1# <38>
Reserve
M3042_DEVSLP <31>
M2280_DEVSLP <36>
Reserve
M3042_PCIE#_SATA <33>
M2280_PCIE_SATA# <36>
SATALED# <36,40>
-----> Ext USB3 Port 1 Charge (Right)
-----> M.2 3042(LTE)
-----> Ext USB3 Port 2 (Left Front)
-----> Ext USB Port 1 Charge (Right)
-----> Ext USB Port 2 (Left Front)
-----> M2 3042(WWAN)
-----> Camera
-----> Card Reader RTS5330
-----> M.2 3030(BT)
-----> LCD Touch
-----> USH
USB_OC3#
USB_OC0#
USB_OC1#
NEED DOUBLE CHECK
M2280_PCIE_SATA#
SATALED#
HDD_DET#
RPC3
4 5
3
2
1
10K_8P4R_5%
RPC4
4 5
3
2
1
10K_8P4R_5%
+3.3V_ALW_PCH
6
7
8
+3.3V_RUN
6
7
8
M3042_PCIE#_SATA
A A
12
RC412 10K_0402_5%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (5/14)
CPU (5/14)
CPU (5/14)
LA-E121P
LA-E121P
LA-E121P
10 52Monday, April 25, 2016
10 52Monday, April 25, 2016
10 52Monday, April 25, 2016
1
0.1
0.1
0.1
5
CLK_PCIE_N0<31>
WWAN--->
D D
WLAN--->
WIGIG--->
M.2 SDD--->
LAN--->
AR --->
+3.3V_LAN
C C
+3.3V_ALW_DSW
+1.0V_VCCST
+3.3V_ALW_PCH
B B
H_CPUPWRGD VCCST_PWRGD
12
CLK_PCIE_P0<31>
CLKREQ_PCIE#0<31>
+3.3V_RUN
CLK_PCIE_N1<31>
CLK_PCIE_P1<31>
CLKREQ_PCIE#1<31>
+3.3V_RUN
CLK_PCIE_N2<31>
CLK_PCIE_P2<31>
CLKREQ_PCIE#2<31>
+3.3V_RUN
CLK_PCIE_N3<36>
CLK_PCIE_P3<36>
CLKREQ_PCIE#3<36>
+3.3V_RUN
CLK_PCIE_N4<29>
CLK_PCIE_P4<29>
CLKREQ_PCIE#4<29>
+3.3V_RUN
CLK_PCIE_N5<23>
CLK_PCIE_P5<23>
CLKREQ_PCIE#5<23>
+3.3V_RUN
RL70 10K_0402_5%@
RC323 10K_0402_5%
RC67 1K_0402_5%
RC71 1K_0402_5%
RC74 10K_0402_5%@
10/6 depop, prevent singal step.
RC411 10K_0402_5%@
@
T9
PAD~D
VCCST_PWRGD<14,33,34>
100P_0402_50V8J
12
CC300ESD@
ESD Request:place near CPU side
12
12
12
12
12
12
100P_0402_50V8J
CC301ESD@
RC373 0_0402_5%
RF@
RC189 10K_0402_5%
RC374 0_0402_5%
RF@
RC47 10K_0402_5%
RC375 0_0402_5%
RF@
RC50 10K_0402_5%
RC376 0_0402_5%
RF@
RC59 10K_0402_5%
RC377 0_0402_5%
RF@
RC51 10K_0402_5%
RC378 0_0402_5%
RF@
RC190 10K_0402_5%
LAN_WAKE#
PCH_PCIE_WAKE#
VCCST_PWRGD
ME_SUS_PWR_ACK
PCH_PWROK
RC77 1K_0402_5%@
RC78 60.4_0402_1%
PCH_RSMRST#_AND<14,39>
1 2
1 2
12
12
12
12
12
12
12
12
12
12
12
12
PCH_PLTRST#
ME_SUS_PWR_ACK<33>
PCH_PCIE_WAKE#<33,34>
PM_LANPHY_ENABLE<29>
CLKREQ_PCIE#0_R
CLKREQ_PCIE#1_R
CLKREQ_PCIE#2_R
CLKREQ_PCIE#3_R
CLKREQ_PCIE#4_R
CLKREQ_PCIE#5_R
TC7SH08FU_SSOP5~D
H_CPUPWRGDH_CPUPWRGD_R
VCCST_PWRGD_CPU
SYS_PWROK<14,33>
PCH_PWROK<48>
PCH_DPWROK<34>
SUSACK#<33>
LAN_WAKE#<29,33>
3.3V_CAM_EN#<28>
RC311 10K_0402_5%
RC62 0_0402_5%
RC244 0_0402_5%
UC7
PCH_PLTRST#
SYS_RESET#
PCH_RSMRST#_AND
12
RC215
POP
NO Support Deep sleep
DE-POP
Support Deep sleep
PCH_DPWROK PCH_RSMRST#_AND
A A
1
2
1 2
RC215 0_0402_5%@
100K_0402_1%
0.01UF_0402_25V7K
12
@
RC220
CC266
12
RC75
10K_0402_5%
5
XDP_DBRESET#<14>
+3.3V_RUN
XDP_DBRESET#
RC225@ 8.2K_0402_5%
RC227@ 8.2K_0402_5%
4
SKL_ULT
CLOCK SIGNALS
PLTRST_LAN# <29>
PCH_PLTRST#_EC <34>
PCH_PLTRST#_AND <23,31,35,36>
SKL-U
5
P
B
4
O
A
G
UC12@
74AHC1G09GW_TSSOP5
3
SYS_RESET#_R
D42
C42
AR10
B42
A42
AT7
D41
C41
AT8
D40
C40
AT10
B40
A40
AU8
E40
E38
AU7
1 2
1 2
+3.3V_ALW_PCH
5
1
P
B
2
A
G
3
AN10
AY17
BA20
BB20
AR13
AP11
BB15
AM15
AW17
AT15
12
12
UC1J
CPU@
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
GPP_B5/SRC CLKREQ0#
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
GPP_B6/SRC CLKREQ1#
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
GPP_B7/SRC CLKREQ2#
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
GPP_B8/SRC CLKREQ3#
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
GPP_B9/SRC CLKREQ4#
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
GPP_B10/SR CCLKREQ5#
KBL-U_BGA1356
PCH_PLTRST#_AND
4
O
12
RC65
@
100K_0402_5%
UC1K
CPU@
SYSTEM POWER MANAGEMENT
GPP_B13/PLT RST#
B5
SYS_RESET#
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
PCH_PWROK
DSW_PWROK
GPP_A13/SU SWARN#/SUSP WRDNACK
GPP_A15/SU SACK#
WAKE#
GPD2/LAN_W AKE#
GPD11/LANP HYPC
GPD7/RSVD
KBL-U_BGA1356
1 2
RC290 0_0402_5%
+3.3V_RUN
1
ME_RESET#
2
if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)
4
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSC LK
XTAL24_OUT
XCLK_BIASREF
GPP_B11/EXT _PWR_GATE#
GPP_B2/VRA LERT#
1 2
RC224 1K_0402_5%
F43
E43
BA17
E37
XTAL24_IN
E35
E42
AM18
RTCX1
AM20
RTCX2
AN18
SRTCRST#
AM16
RTCRST#
10 OF 20
PCH_PLTRST#
PCH_PLTRST#_AND
GPP_B12/SLP _S0#
GPD4/SLP_S 3#
GPD5/SLP_S 4#
GPD10/SLP_S 5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_W LAN#
GPD6/SLP_A #
GPD3/PWR BTN#
GPD1/ACPR ESENT
GPD0/BATLOW #
GPP_A11/PM E#
INTRUDER #
11 OF 20
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
CLK_ITPXDP_N
CLK_ITPXDP_P
SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
PCH_RTCX1
PCH_RTCX2
SRTCRST#
PCH_RTCRST# <33>
PCH_RTCRST#
CMOS1 must take care short & touch risk on layout placement
1 2
RC60 0_0402_5%
@
1 2
RC325 0_0402_5%
SIO_SLP_S0#
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
PCH_BATLOW#
AU13
AU11
PME#
AP16
INTRUDER #
MPHYP_PWR_EN
AM10
AM11
VRALERT#
+3.3V_RUN
@
RC291
10K_0402_5%
1 2
SYS_RESET#
3
1 2
RC297 0_0402_5%
@
1 2
RC298 0_0402_5%
@
SUSCLK <31,36>
1 2
RC52 2.7K_0402_1%
1 2
@
RC324 59_0402_1%
546765_546765_2014WW48_Skylake_MOW_Rev_1_0
1 2
RC56 20K_0402_5%
1 2
CC24 1U_0402_6.3V6K
1 2
RC57 20K_0402_5%
1 2
CC25 1U_0402_6.3V6K
1
1
2
SHORT PADS~D
@
CMOS1
SIO_SLP_S0# <17,46>
SIO_SLP_S3# <23,33,34>
SIO_SLP_S4# <17,33,44,47>
SIO_SLP_S5# <33>
SIO_SLP_SUS# <17,33,41,45,46,47>
SIO_SLP_LAN# <33,41>
SIO_SLP_WLAN# <33,41>
SIO_SLP_A# <33>
SIO_PWRBTN# <14,33>
AC_PRESENT <33>
@
T115
PAD~D
connect to VCCMPHYGTAON_1P0 enable pin
2
CLK_ITPXDP_N_R <14>
CLK_ITPXDP_P_R <14>
+1.0V_CLK5
For Skylake, pop RC52,depop RC324
For Cannonlake, pop RC324,depop RC52
+RTC_CELL
2
PLTRST_TPM# <35>
2
M!3%)?IVW%>67%X%78
1M_0402_1%
RC46
XTAL24_IN
XTAL24_OUT XTAL24_OUT_R
PCH_RTCX1
PCH_RTCX2
SYS_RESET#
0.1U_0402_25V6
12
ESD Request:place near CPU side
1 2
RC295 0_0402_5%
8/21 can change to 10K for merge to RP
+3.3V_ALW_PCH
+3.3V_ALW
+3.3V_ALW
@ESD@
CC302
1 2
For Skylake,YC1 24 MHz (50 Ohm ESR)
For Cannonlake,YC1 38.4 MHz (30 Ohm ESR)
546765_546765_2014WW48_Skylake_MOW_Rev_1_0
RC54
10M_0402_5%
1 2
1 2
RC296 0_0402_5%
PCH_BATLOW#
AC_PRESENT
INTRUDER #
MPHYP_PWR_EN
VRALERT#
SIO_SLP_LAN#
SUSCLK
POWER_SW#_MB<34,40>
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
3
1
PCH_RTCX2_R
1 2
RC72 8.2K_0402_5%
1 2
RC243 10K_0402_5%
1 2
RC69 1M_0402_5%
1 2
RC387 10K_0402_5%@
1 2
RC73 10K_0402_5%
@
1 2
RC344 10K_0402_5%@
1 2
RC68 10K_0402_5%@
1 2
RC48 1K_0402_5%@
SIO_SLP_S3#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#
PCH_RTCRST#
SYS_RESET#
SIO_SLP_S0#
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU (6/14)
CPU (6/14)
CPU (6/14)
LA-E121P
LA-E121P
LA-E121P
1
CC21
1 2
15P_0402_50V8J
4
YC1
24MHZ_12PF_X3G024000DC1H
2
12
CC22
1 2
15P_0402_50V8J
CC23
1 2
15P_0402_50V8J
YC2
32.768KHZ_12.5PF_9H03200042
ESR MAX=50k ohm
CC26
1 2
12P_0402_50V8J
+3.3V_ALW_DSW
+RTC_CELL
+3.3V_ALW_PCH
+3.3V_ALW
JAPS1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
GND
20
GND
CVILU_CF4218FH0R0-05-NH
1
11 52Monday, April 25, 2016
11 52Monday, April 25, 2016
11 52Monday, April 25, 2016
CONN@
0.1
0.1
0.1
5
4
3
2
+1.0V_VCCSTG
1
PCH_JTAG_TDI
PCH_JTAG_TDO
D D
+1.0V_VCCST
RC79 49.9_0402_1%@
RC80 1K_0402_5%
+1.0V_VCCSTG
RC83 1K_0402_5%
+3.3V_RUN
RC414 10K_0402_5%
RC413 10K_0402_5%
C C
B B
RC278 10K_0402_5%
RC272 10K_0402_5%
@
RC279 10K_0402_5%
RC345 100K_0402_5%
RC292 10K_0402_5%
+3.3V_ALW_PCH
RC346 10K_0402_5%
RC288 10K_0402_5%
+3.3V_ALW_PCH +3.3V_ALW_PCH
RC183 8.2K_0402_5%
@
H_CATERR#
12
H_THERMTRIP#
12
H_PROCHOT#
12
TOUCHPAD_INTR#
12
CAM_MIC_CBL_DET#
12
CONTACTLESS_DET#
12
TOUCH_SCREEN_PD#
12
AUD_PWR_EN
12
IR_CAM_D ET#
12
HOST_SD_WP#
12
SIO_EXT_SMI#
12
12
HDA_BIT_CLK_R<32>
12
SPKR
KB_DET#
HDA_SYNC_R<32>
HDA_SDOUT_R<32>
HDA_RST#_R<32>
@EMI@
22P_0402_50V8J
Close to RC93
TOUCH_SCREEN_PD# don't move to RPC,
ME_FWP
HDA_BIT_CLK_R
1
CC27
2
PECI_EC<33>
H_PROCHOT#<33,48,51>
H_THERMTRIP#<20,34>
1 2
RC92 33_0402_5%
1 2
RC93 33_0402_5%EMI@
1 2
RC94 33_0402_5%
1 2
RC223 1K_0402_5%
1 2
RC95 33_0402_5%
RC187 4.7K_0402_5%
@
RC84 499_0402_1%
T10
T11
TOUCH_SCREEN_PD#<28>
TOUCHPAD_INTR#<33,39>
TOUCH_SCREEN_DET#<28>
12
IR_CAM_D ET#<28>
@
T269
PAD~D
HDA_SDOUT
12
1 2
XDP_OBS0_R<14>
XDP_OBS1_R<14>
@
PAD~D
@
PAD~D
SIO_EXT_SMI#<33>
12
RC88
49.9_0402_1%
KB_DET#<39>
SPKR<32>
RC89
HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT
HDA_SDIN0<32>
HDA_RST#
H_PROCHOT#_R
H_THERMTRIP#
XDP_OBS2_R
XDP_OBS3_R
TOUCHPAD_INTR#
CPU_POPIRCOMP
PCH_POPIRCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
12
12
RC90
49.9_0402_1%
49.9_0402_1%
IR_CAM_D ET#
TBT_PWR_EN
KB_DET#
H_CATERR#
RC91
49.9_0402_1%
BA22
AY22
BB22
BA21
AY21
AW22
AY20
AW20
AK10
AW5
D63
A54
C65
C63
A65
C55
D55
B54
C56
A6
A7
BA5
AY5
AT16
AU16
H66
H65
UC1G
HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_ MCLK
I2S1_SFRM
I2S1_TXD
AK7
GPP_F1/I2S2_ SFRM
AK6
GPP_F0/I2S2_ SCLK
AK9
GPP_F2/I2S2_ TXD
GPP_F3/I2S2_ RXD
H5
GPP_D19/DM IC_CLK0
D7
GPP_D20/DM IC_DATA0
D8
GPP_D17/DM IC_CLK1
C8
GPP_D18/DM IC_DATA1
GPP_B14/SPK R
KBL-U_BGA1356
UC1D
CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
GPP_E3/CPU _GP0
GPP_E7/CPU _GP1
GPP_B3/CPU _GP2
GPP_B4/CPU _GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOM P
OPC_RCOMP
KBL-U_BGA1356
CPU@
AUDIO
CPU@
CPU MISC
SKL-U
SKL-U
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
JTAGX
4 OF 20
SDIO/SDXC
GPP_A17/SD _PWR_EN#/ISH _GP7
CPU_XDP_TCLK
B61
CPU_XDP_TDI
D60
CPU_XDP_TDO
A61
CPU_XDP_TMS
C60
CPU_XDP_TRST#
B59
PCH_JTAG_TCK
B56
PCH_JTAG_TDI
D59
PCH_JTAG_TDO
A56
PCH_JTAG_TMS
C59
CPU_XDP_TRST#
C61
XDP_JTAGX
A59
RC87 1K_0402_5%@
GPP_G0/SD_C MD
GPP_G1/SD_D ATA0
GPP_G2/SD_D ATA1
GPP_G3/SD_D ATA2
GPP_G4/SD_D ATA3
GPP_G5/SD_C D#
GPP_G6/SD_C LK
GPP_G7/SD_W P
GPP_A16/SD _1P8_SEL
SD_RCOMP
GPP_F23
CPU_XDP_TCLK XDP_JTAGX
1 2
7 OF 20
RC328 0_0402_5%
CPU_XDP_TCLK <14>
CPU_XDP_TDI <14>
CPU_XDP_TDO <14>
CPU_XDP_TMS <14>
CPU_XDP_TRST# <14>
PCH_JTAG_TCK <14>
PCH_JTAG_TDI <14>
PCH_JTAG_TDO <14>
PCH_JTAG_TMS <14>
AB11
AB13
TBT_CIO_PLUG_EVENT#
AB12
W12
CONTACTLESS_DET#
W11
W10
AUD_PWR_EN
W8
W7
BA9
BB9
SD_RCOMP
AB7
AF13
12
RC86 51_0402_5%
@
+1.0V_VCCSTG
1 2
RC96 200_0402_1%
PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX
@ESD@
0.1U_0402_25V6
12
CC303
1 2
CAM_MIC_CBL_DET# <28>
TBT_CIO_PLUG_EVENT# <23>
CONTACTLESS_DET# <35>
AUD_PWR_EN <32>
ESD request,Place near CPU side.
PCH_JTAG_TMS
Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the entire region of the SPI flash to be updated using FPT.
+3.3V_ALW_PCH
ME_FWP PCH has internal 20K PD.
(suspend power rail)
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
HOST_SD_WP# <30>
@ESD@
0.1U_0402_25V6
12
CC304
1 2
RC81 51_0402_5%
1 2
RC82 100_0402_1%
1 2
RC130 51_0402_5%
RC221 0_0402_5%
@
PT,ST pop RC222 and SW1; MP pop RC221
RC222
1K_0402_5%
1 2
ME_FW_EC<33>
@ESD@
0.1U_0402_25V6
12
CC305
ME_FWPME_FW_EC
12
SW1
1
A
2
ME_FWP
12
B
3
C
4
G1
5
G2
SS3-CMFTQR9_3P
H_THERMTRIP# H_PROCHOT#
@ESD@
0.1U_0402_25V6
CC312
@ESD@
0.1U_0402_25V6
12
CC310
TOP SWAP STRAP
A A
HIGH
LOW(DEFAULT)
Internal 20k PD
ENABLE
DISABLE
5
Flash Descriptor Security override
HIGH
LOW(DEFAULT)
DISABLE
ENABLE
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (7/14)
CPU (7/14)
CPU (7/14)
LA-E121P
LA-E121P
LA-E121P
12 52Monday, April 25, 2016
12 52Monday, April 25, 2016
12 52Monday, April 25, 2016
1
0.1
0.1
0.1
5
D D
4
CFG[0..19]<14>
3
2
1
CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin
12
RC113 10K_0402_1%
@
CFG0
RC112 10K_0402_1%
@
RC110 10K_0402_1%
@
12
12
Stall reset sequence
HIGH(DEFAULT)
LOW
C C
RC109 1K_0402_5%
eDP enable
HIGH(DEFAULT)
LOW
B B
No stall(Normal Operation)
stall
12
CFG4
Disabled
Enabled
+1.0V_PRIM_XDP
RC114 49.9_0402_1%
RC115 1.5K_0402_5%
ITP_PMODE<14>
@
T16
PAD~D
@
T17
PAD~D
CFG_RCOMP
12
ITP_PMODE
12
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
AL25
AL27
BA70
BA68
E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
E8
AY2
AY1
D1
D3
K46
K45
C71
B70
F60
A52
J71
J68
F65
G65
F61
E61
UC1S
CPU@
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2
RSVD_AY1
RSVD_D1
RSVD_D3
RSVD_K46
RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70
RSVD_TP_BA68
RSVD_J71
RSVD_J68
VSS_F65
VSS_G65
RSVD_F61
RSVD_E61
KBL-U_BGA1356
RESERVED SIGNALS -1
SKL-U
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
TP5
TP6
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
TP4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
TP1
TP2
VSS_AY71
ZVM#
RSVD_TP_AW71
RSVD_TP_AW70
MSM#
PROC_SELECT#
19 OF 20
BB68
BB69
AK13
AK12
BB2
BA3
AU5
AT5
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
A69
B69
AY3
D71
C70
C54
D54
AY4
BB3
AY71
AR56
AW71
AW70
AP56
C64
@
T12
PAD~D
@
T13
PAD~D
@
T14
PAD~D
@
T15
PAD~D
@
T128
PAD~D
@
T129
PAD~D
@
T130
PAD~D
@
T126
PAD~D
@
T127
PAD~D
@
T113
PAD~D
@
T114
PAD~D
1 2
RC120 100K_0402_5%@
For Skylake , RC120 depop
For Cannonlake, RC120 pop
546765_546765_2014WW48_Skylake_MOW_Rev_1_0
UC1T
1/5 2014WW52 MOW reserve to support
Cannonlake-U PCH compatibility
close UC1.U11/U12 and <400mil
1 2
RC313 0_0402_5%
@
+VCC_1P8+1.8V_PRIM
AW69
RSVD_AW69
AW68
RSVD_AW68
AU56
RSVD_AU56
AW48
RSVD_AW48
C7
RSVD_C7
U12
RSVD_U12
U11
RSVD_U11
H11
1
2
CC222
@
RSVD_H11
KBL-U_BGA1356
1U_0402_6.3V6K
ZVM# for SKYLAKE-U 2+3e
MSM# for SKYLAKE-U 2+3e
+1.0V_VCCST
SPARE
SKL-U
RSVD_F6
RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
20 OF 20
F6
E3
C11
B11
A11
D12
C12
F52
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (8/14)
CPU (8/14)
CPU (8/14)
LA-E121P
LA-E121P
LA-E121P
13 52Monday, April 25, 2016
13 52Monday, April 25, 2016
13 52Monday, April 25, 2016
1
0.1
0.1
0.1
+1.0V_PRIM
1 2
RC216 0_0603_1%
@
+1.0V_PRIM_XDP
0.1U_0201_10V6K
0.1U_0201_10V6K
@
CC28
1
1
2
2
D D
Place near
JXDP1
VCCST_PWRGD<11,33,34>
PCH_RSMRST#_AND<11,39>
C C
+1.0V_VCCST
+3.3V_RUN
+1.0V_PRIM_XDP
5
+1.0V_PRIM_XDP
@
CC29
XDP_OBS0_R<12>
XDP_OBS1_R<12>
RC123 1K_0402_5%@
RC124CXDP@
PCH_SPI_DO_XDP<8>
SYS_PWROK<11,33>
RC132 150_0402_5%
RC218 150_0402_5%@
RC219 10K_0402_5%@
RC137 1K_0402_5%
RC138 51_0402_5%
@
RC239 0_0402_5%
CXDP@
RC240 0_0402_5%
CXDP@
RC5 need to close to JCPU1
1 2
1 2
1K_0402_5%
12
12
12
12
12
FIVR_EN
CFG0
RC217 0_0402_5%
@
RC126 1K_0402_5%@
RC128 0_0402_5%
CXDP@
RC129 0_0402_5%
@
DDR_XDP_WAN_SMBDAT<8,20>
DDR_XDP_WAN_SMBCLK<8,20>
FIVR_EN_R
FIVR_EN
FIVR_EN
XDP_DBRESET#
CPU_XDP_PREQ#
CPU_XDP_PREQ#<10>
CPU_XDP_PRDY#<10>
1 2
1 2
1 2
1 2
1 2
1 2
PCH_JTAG_TCK<12>
CPU_XDP_TCLK<12>
CPU XDP
H_VCCST_PWRGD_XDP
SIO_PWRBTN#<11,33>
CPU_XDP_PREQ#
CPU_XDP_PRDY#
RESET_OUT#_R
CPU_XDP_TCLK
+1.0V_PRIM_XDP
CFG0
CFG1
CFG2
CFG3
XDP_OBS0
XDP_OBS1
CFG4
CFG5
CFG6
CFG7
FIVR_EN_R
+3.3V_ALW_PCH+1.0VS_VCCIO
1 2
0.1U_0402_25V6
12
CC33@
Place near JXDP1.47
4
XDP_PRSNT_PIN1
JXDP1
1
1
3
3
5
5
7
7
9
9
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556
575758
595960
61
61
62
GND
E-T_6601K-Y61N-04L
RC133
1.5K_0402_5%
CXDP@
PCH_SPI_DO_XDP
RESET_OUT#_R
CXDP@
1 2
1 2
2
2
4
4
6
6
8
8
10
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
63
CFG3
RC121 0_0402_5%
RC122 0_0402_5%@
CONN@
GND
Place near JXDP1.48
+1.0V_PRIM_XDP
XDP_DBRESET#
CFG17
CFG16
CFG8
CFG9
CFG10
CFG11
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15
ITP_PMODE
XDP_DBRESET#
TDO_XDP
TRST#_XDP
TDI_XDP
XDP_TMS
0.1U_0402_25V6
CXDP@
12
CC32
3
CFG[0..19]<13>
CLK_ITPXDP_P_R <11>
CLK_ITPXDP_N_R <11>
ITP_PMODE <13>
XDP_DBRESET# <11>
PCH_SPI_DO2_XDP <8>
SIO_PWRBTN#
Place near JXDP1.41
+3.3V_ALW_DSW
1.5K_0402_5%
1 2
0.1U_0402_25V6
12
2
+3.3V_RUN
CC30
12
0.1U_0201_10V6K
TDO_XDP
TDI_XDP
XDP_TMS
TRST#_XDP
RUNPWROK<33>
@
RC241
CC269
@
UC8
14
VCC
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
74CBTLV3126BQ_DHVQFN14_2P5X3
CPU_XDP_TMS
RC131 51_0402_5%
CPU_XDP_TDI
RC134 51_0402_5%
CPU_XDP_TDO
RC135 100_0402_1%
CPU_XDP_TRST#
RC136
@
CPU_XDP_TCLK
RC139 51_0402_5%
XDP_TMS
TDI_XDP
TDO_XDP
1 2
RC228 0_0402_5%
1 2
RC229 0_0402_5%
1 2
RC230 0_0402_5%
GND PAD
1 2
1 2
1 2
1 2
1 2
1B
2B
3B
4B
GND
51_0402_5%
1
3
6
8
11
7
15
+1.0V_VCCSTG
PCH_JTAG_TMS <12>
PCH_JTAG_TDI <12>
PCH_JTAG_TDO <12>
CPU_XDP_TDO <12>
CPU_XDP_TDI <12>
CPU_XDP_TMS <12>
CPU_XDP_TRST# <12>
B B
A A
TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#
@ESD@
0.1U_0402_25V6
12
CC306
ESD request,Place near JXDP1 side. ESD request,Place near UC8 side.
@ESD@
0.1U_0402_25V6
12
CC307
@ESD@
0.1U_0402_25V6
12
CC308
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (9/14)
CPU (9/14)
CPU (9/14)
LA-E121P
LA-E121P
LA-E121P
14 52Monday, April 25, 2016
14 52Monday, April 25, 2016
14 52Monday, April 25, 2016
1
0.1
0.1
0.1
5
4
3
2
1
+VCC_CORE: 0.3~1.35V
D D
@
T122
PAD~D
@
T123
PAD~D
C C
VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e
(w/ on package cache)
+VCC_CORE +VCC_CORE
+VCC_CORE_G0
+VCC_CORE_G1
A30
VCC_A30
A34
VCC_A34
A39
VCC_A39
A44
VCC_A44
AK33
VCC_AK33
AK35
VCC_AK35
AK37
VCC_AK37
AK38
VCC_AK38
AK40
VCC_AK40
AL33
VCC_AL33
AL37
VCC_AL37
AL40
VCC_AL40
AM32
VCC_AM32
AM33
VCC_AM33
AM35
VCC_AM35
AM37
VCC_AM37
AM38
VCC_AM38
G30
VCC_G30
K32
RSVD_K32
AK32
RSVD_AK32
AB62
VCCOPC_AB62
P62
VCCOPC_P62
V62
VCCOPC_V62
H63
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61
AC63
VCCOPC_SENSE
AE63
VSSOPC_SENSE
AE62
VCCEOPIO
AG62
VCCEOPIO
AL63
VCCEOPIO_SENSE
AJ62
VSSEOPIO_SENSE
KBL-U_BGA1356
UC1L
CPU@
SKL-U
CPU POWER 1 OF 4
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
12 OF 20
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
VCCSENSE
VSSSENSE
H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT
+1.0V_VCCSTG_R
VIDSCLK <48>
+VCC_CORE
RC140
100_0402_1%
1 2
12
RC141
100_0402_1%
1 2
RC143 0_0603_5%
@
VCCSENSE <48>
VSSSENSE <48>
+1.0V_VCCSTG
VIDSCLK
8M%8+N1+0*
1 2
CC321@RF@ 33P_0402_50V8J
Place close CPU side
PSC(Primary side cap) : Place as close to the package as possible
BSC(Backside cap) : Place on secondary side, underneath the package
Component placement order:
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source
B B
SVID ALERT
VIDALERT_N<48>
SVID DATA
A A
VIDSOUT<48>
+1.0V_VCCST
1 2
+1.0V_VCCST
1 2
56_0402_1%
RC152
100_0402_1%
RC157
CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 - 1500mils
H_CPU_SVIDALRT#
12
RC153220_0402_5%
CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 - 1500mils
VIDSOUT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (10/14)
CPU (10/14)
CPU (10/14)
LA-E121P
LA-E121P
LA-E121P
15 52Monday, April 25, 2016
15 52Monday, April 25, 2016
15 52Monday, April 25, 2016
1
0.1
0.1
0.1
5
4
3
2
1
+VCCGT: 0.3~1.35V
+VCCGTX : 0.3~1.35V
+VCC_GT +VCC_GT
D D
C C
+VCC_GT
RC161
100_0402_1%
1 2
VCC_GT_SENSE<48>
VSS_GT_SENSE<48>
B B
VCC_GT_SENSE
VSS_GT_SENSE
12
RC163
100_0402_1%
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
M62
N63
N64
N66
N67
N69
A48
A53
A58
A62
A66
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
J70
J69
UC1M
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENSE
KBL-U_BGA1356
CPU@
CPU POWER 2 OF 4
SKL-U
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
13 OF 20
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
VCCGTX for SKYLAKE-U 2+3e
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
Reserve for soldering
+VCC_GTUS
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (11/14)
CPU (11/14)
CPU (11/14)
LA-E121P
LA-E121P
LA-E121P
16 52Monday, April 25, 2016
16 52Monday, April 25, 2016
16 52Monday, April 25, 2016
1
0.1
0.1
0.1
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