Compal LA-E061P Schematics

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Compal Confidential

B5W11 MB Schematic Document

LA-E061P

3

Rev: 1.0

2016.07.18

4

Secu rity Cl assifica tion

Issued Da te

THIS SHEE T OF ENG INEERING DRAW ING I S THE P ROPRIETAR Y PRO PERTY O F CO MPAL ELE CTRONICS, INC. AND CON TAINS CON FIDENTIAL

AND TRA DE SE CRET INF ORMATION. THIS SHEET MAY NO T BE TRA NSFERED FRO M THE CU STODY O F THE COM PETENT DIVI SION OF R& D

DEPARTME NT EXC EPT AS AUTH ORIZED BY COMPAL ELE CTRONICS, INC . NE ITHER TH IS SHEE T NO R THE I NFORMATIO N IT CONTAINS

MAY BE USED BY O R DISCLO SED TO AN Y THIRD P ARTY WI THOUT PRI OR WR ITTEN CONSE NT OF COMP AL EL ECTRONICS, I NC.

A

B

2016/0 7/18 2016/1 1/10

C

Comp al Secre t Data

Decipher ed Date

CompalElectronics,Inc.

Tit le

CoverSheet

Size Docu ment N umber R e v

Custom

B5W11M/BLA-E061P

Da te : Sh eet

D

Da te : Sh eet

E

o f

1 44Monday, July 18, 2016

o f

1 44Monday, July 18, 2016

o f

1 44Monday, July 18, 2016

4

1.0

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B

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1

2

NGFF WLAN

USB port 5

page 24

PCIe 1.0

2.5G T/s

port 6

PCIe 1.0

2.5G T/s

port 5

LAN(GbE) Realtek 8111H

page 23

HDMI Conn.

page 22

DDI2

HDMI x 4 lanes

LAN(GbE)

SATA3.0 SATA3.0

port 7 (SATA0) (SATA1)

SATA HDD

Conn.

eDP

page 21

eDP

DDI

Flexible IO

6.0 Gb/s6.0 Gb/s

port 8

SATA CDROM Conn.

Intel Kabylake U

Kabylake U Kabylake PCH-LP(MCP)

(KBL-U_2+2)

Processor

Dual Core + GT2

15W 1356pin BGA

page 07~18

Memory BUS

Dual Channel

1.2V DDR4 1866 /2133

USBx 8

48 M H z

HD Audio

SPI

Interleaved Memory

page 19

260pin DDR4-SO-DIMM X2

page 20

USB 2.0

USB 3.0 conn x1

USB port 1 USB port 7

page 28 page 21

conn x2

USB port2,3 Port3 on Sub/B

page 28

3.3V 2 4MH z

CMOS Camera

HDA Codec ALC233

Fan Control

Card Reader RTS5170 SD only

USB port 8

on Sub/B

page 28

page 25

page 31

Touch

Screen

I2C (PORT1)

USB port 6

page 21

1

2

3

RTC CKT.

page 15

Power On/Of f CKT.

page 30

4

DC/DC Interface CKT.

Power Circuit DC/DC

page 33~43

RJ45 conn.

page 23

page 32

A

page 26

Sub Board

LS-D671

IO/B

page 28

page 26

B

Int.KBD

page 30

ENE

KB9022

LPC/eSPI BUS

CLK = 24 MHz

page 29

SPI ROM 64Mb

page 9

Touch Pad PS2 (from EC) / I2C (from SOC)

page 30

Secu rity Cl assifica tion

Issued Da te

THIS SHEE T OF ENG INEERING DRAW ING I S THE P ROPRIETAR Y PRO PERTY O F CO MPAL ELE CTRONICS, INC. AND CON TAINS CON FIDENTIAL

AND TRA DE SE CRET INF ORMATION. THIS SHEET MAY NO T BE TRA NSFERED FRO M THE CU STODY O F THE COM PETENT DIVI SION OF R& D

DEPARTME NT EXC EPT AS AUTH ORIZED BY COMPAL ELE CTRONICS, INC . NE ITHER TH IS SHEE T NO R THE I NFORMATIO N IT CONTAINS

MAY BE USED BY O R DISCLO SED TO AN Y THIRD P ARTY WI THOUT PRI OR WR ITTEN CONSE NT OF COMP AL EL ECTRONICS, I NC.

C

www.schematic-x.blogspot.com

Comp al Secre t Data

2016/0 7/18 2016/1 1/10

Comp al Secre t Data

Decipher ed Date

D

Int. Speaker

page 25

Tit le

Size Docu ment N umber R e v

Custom

Da te : Sh eet

Int. AMIC

page 25 page 28

Compal Electronics, Inc.

Block Diagrams

B5W11 M/B LA-E061P

E

UAJ

on Sub/B

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4

1.0

A

Board ID Table for AD channel

Vc c 3.3V +/- 5%

Board ID

1

2

BOM Structure Table

100K +/- 1%Ra

Rb V mi n

0 1 2 3 4 5 6 7

0 0 V 12K +/- 1% 0.347 V 0.345 V 0.360 V 15K +/- 1% 20K +/- 1% 27K +/- 1% 33K +/- 1% 43K +/- 1% 56K +/- 1%

BOM Option Table

It em BOM Structure

Unp op

Connector For Acer BYOC B YO C@ No Acer BYOC NBYO C@

COD EC(ALC2 33) 233@ LPC MODE for EC LPC @ ESPI MODE for EC ES PI@ For Intel CMC

EMI requirement EMI requirement depop ESD requirement

3

ESD requirement depop LAN(81 11GUS ) LAN(811 1H) 8 111H @ RF requirement

@ CONN @

255@COD EC(ALC2 55)

CMC @

EMI@ @EMI@ ESD@ @ESD @ 8111GUS @

RF@

B

BI D

V ty p

BI D

0 V 0.300 V

V

ma x

BI D

0.423 V 0.430 V 0.438 V

BOM Option Table

It em BOM Structure

SkyLake plat f or m KabyLake plat f or m KBL @

CPU Code

SKL@

QKJW @

EC AD3

0x00 - 0x13 0x14 - 0x1E 0x1F - 0x25 0x26 - 0x300.541 V 0.550 V 0.559 V 0x31 - 0x3A0.691 V 0.702 V 0.713 V 0x3B - 0x450.807 V 0.819 V 0.831 V 0x46 - 0x540.978 V 0.992 V 1.006 V 0x55 - 0x641.169 V 1.185 V 1.200 V

PCB Revision

0.1

C

D

E

Power State

STATE

S0 (Full ON) ON ON ON ONHIGH HIGH HIGH

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S3# SLP_S4# SLP _S5# +VALW +V +VS Cloc k

LOW HIGH

LOWLOW

HIGH

ONONON

ON

OFF

OFFLOW LOW LOW

OFF

1

Voltage Rails

Power Plane

+19V_VIN

+17.4V_BATT

+19VB

+VCC _COR E

+VCC_ GT

+VCC _S A

+0.6VS_V TT

+1.0VALW_PRI M +1.0V Always power rail

+1.0 V_VCC ST U Sustain voltage f or processor in Standby modes

+VC CIO

+1. 0VS_V CCST G +1.0V ALW_PRIM G ated ver sion of V CCST

+1.2 V_V DD Q

+1.8VALW_PRI M +1.8V Always power rail

+1.8VS System +1.8V power rail

+3VLP +19VB to +3VLP power rail for suspend power

+3VALW System +3VALW always on power rail

+3VS

+5VALW

+5VS System +5V power rail

+RT CVCC

Note : ON*1 means pow er p lane is ON only when WOL enable and RT C wake at BIOS setting, other wise it is OF F.

Descr ipt ion

Adap ter pow er suppl y

Batt ery power supply

AC or batte ry power rail for power circuit.

Processor IA Cores Power Rail

Processor Graphics P ower Rails

System Agent power rail

DDR +0.6VS pow er rail for DDR termina tor .

CPU IO power ra il

DDR4 +1 .2V Power R ail

System +3V power rail

+5V Always power rail

RTC Ba ttery Pow er

S0

N/A

ON

S3

S4/S5

N/AN/A

N/A N/A

N/AN/A

OF F O FF

OF F

OF F O FF

OF FOF F

ON

ON*1

OF F

ON

OF F O FF

OF FOF F

OF F

ON

ON*1

OF F

ON

ON*1

OF F

ON

OF FOF F

ON ON

2

3

43 level BOM table

431A3EBO L01

4

SMT MB AE061 B5W11 QKJW HDMI

A

BOM Structure43 Level Des cr i pti on

4

Security Classification

Issued Date

THIS SH EET OF ENGIN EERING D RAWING IS THE P ROPRIETARY PROPERT Y OF COMPAL ELECTRO NICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFER ED FRO M THE CUS TODY OF THE COMP ETENT DIVIS ION OF R&D

DEPARTMENT EXCEP T AS AUTHO RIZED BY C OMPAL ELE CTRONICS, INC. NEITHE R THIS SHEET NOR THE I NFORMATION IT CONTAINS

MAY BE USE D BY OR DIS CLOSED TO AN Y THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL EL ECTRONICS, INC.

B

MAY BE USE D BY OR DIS CLOSED TO AN Y THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL EL ECTRONICS, INC.

C

2016/07/18 2016/11/10

Compa l Secret Dat a

Deciphered Date

CompalElectronics,Inc.

Titl e

Notes List

Size Document Number R ev

Custom

B5W11M/BLA-E061P

Dat e: She et

D

Dat e: She et

E

3 44Monday, July 18, 2016

1.0

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1

ADAPTER

BATTE RY

CHARG ER

2

+3VLP

LD O

+19 VB

DR VON

SYS ON

SM_PG _CTR L

5V_ EN

3V_ EN

NCP 81253MNTBG (PU9 001 )

NCP 81151MNTBG (PU9 003 )

NCP 81253MNTBG (PU9 004 )

RT82 07KGQW (PU501)

SY8286C RAC (PU402)

SY8286BR AC (PU401)

+5VALWP

+VCC_CO RE

+VCC_GT

+VCC_SA

+1.2VP

+0.6VS P

JUMP (PJ40 2)

JUMP (PJ40 1)

JUMP (PJ50 1)

JUMP (PJ50 2)

+5VALW

+3VALW+3VALW P

+1.2V_VDDQ

+0.6VS_VTT

SUSP #

USB_E N

SYS ON

LAN_ PWR _EN

TP_PW R_E N

WL AN _ON

SUSP #

SPO K

JUMP (JPC1,JPC2 )

EM5209 VF (UQ1)

SY6288C 20AA C (US21)

APL5 336KAI (PU502)

R-Short (RC 173)

JUMP (JPC7)

APL5 336KAI (PU502)

SY6288C 20AA C (UL1)

SY6288C 20AA C (UK1)

SY6288C 20AA C (UM1)

EM5209 VF (UQ1)

G971 ADJF11 U (PU702)

+5VS_OUT

+USB3_VC CA

+2.5VP

+3VALW_ DSW

+3VALW_PRIM

+2.5VP

+3V_LA N

+3V_PTP

+3VS_W LAN

+3VS_OUT

+1.8VALWP

+1.2V_VDD Q_CPU

JUMP (JPQ2)

JUMP (JPQ1)

JUMP (PJ70 2)

R-Short (RC 197)

R-Short (RC 161)

R-Short (RC 163)

R-Short (RC 172)

R-Short (RC 167)

R-Short (RC 187)

R-Short (RC 171)

R-Short (RC 208)

R-Short (RC 141)

+5VS

+3VALW_1.8 VALW_ PG PPA

+3VALW_PGP PB

+3VALW_P GPP C

+3VALW_ 1.8VALW_P GPP D

+3VALW_P GPP E

+3VALW_P GPP G

+3VALW_RT C

+3VS

+1.8VALW_PRIM

+1.2V_VDDQ C

+1.2V_VCC SFR_ OC

SUSP #

EM5209 VF (UC5)

R-Short (RC 178)

0 ohm (RM 1)

R-Short (RA 2)

R-Short (RA 5)

SOC_ ENVD D

R-Short (RX8)

AP233 0W (UY1)

R-Short (RO 3)

0 ohm (RO 2)

JUMP (JPA1 )

R-Short (RF1)

SY6288C 20AA C (UX1)

+1.8VS

+TS_PWR

+HDMI_5V_OU T

+5VS_HDD

+5VS_ODD

+VDDA

+VCC_FAN 1

+1.8VS_3VS_P GPPA

+3VS_W LAN

+3VS_D VDDI O

+3VS_DVDD

+LCDVD D

R-Short (RA 6)

+1.8VS_V DDA

1

2

EN _1V ALW

3

4

A

SY82 88 RAC (PU601)

JUMP (PJ60 1)

B

SYS ON

SUSP #

R-Short (RC 148)

JUMP (JPC9)

R-Short (RC 162)

R-Short (RC 169)

R-Short (RC 164)

R-Short (RC 190)

R-Short (RC 152)

R-Short (RC 175)

EM5209 VF (UC5)

AOZ 1336 (UC8)

C

+1.0 VALW_A PLL

+1.0VALW_ MP HYP LL

+1.0VALW _DTS

+1.0VALW_C LK6_24TBT

+1.0VALW_VCC CLK 2

+1.0VALW_CLK 4_F100 OC

+1.0VALW_ CLK5_ F24NS

+1.0VALW_ MPHYAO N

+1.0V_VC CSTU

+1.0VS_VCC STG_ IO

Security Classif ication

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.0VALW_PRIM+1.0VALWP

R-Short (RC 209)

R-Short (RC 149)

R-Short (RC 176)

R-Short (RC 156)

R-Short (RC 143)

R-Short (RC 140)

R-Short (RC 188)

JUMP (JPC5)

Compal S ecret Data

2016/07/18 2014/04/12

Compal S ecret Data

+1.0VALW _MP HYGT

+1.0VALW_AMPH YPLL

+1.0VALW_SR AM

+1.0VALW _APLL EBB

+1.0V_VCC SFR

+1.0V_VC CST

+1.0VS_VC CSTG

+VCCIO

Deciphered Date

D

Compal Electronics, Inc.

Titl e

Size Docum ent N umb er R e v

Custom

Da te : She et

Power Rail

B5W11 M/B LA-E061P

E

o f

4 44Monday, July 18, 2016

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4 44Monday, July 18, 2016

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4 44Monday, July 18, 2016

3

4

1.0

A

B

C

D

E

2. 2 K

BH 1 0

2. 2 K

SOC_ SMBC LK

SOC_SMBDATA

1

Sk ylak e

BG 1 2

+3VALW_PRI M

2N 7002D W

2. 2 K

+3VS

SO-D IMM 2

1

SOC

SOC_ SM L0C LK

SOC_SML0 DATA

SOC_ SM L1C LK

SOC_SML1 DATA

2

77

SCL 1

SDA 1

KBC

3

KB9022

SCL 2

SDA 2

78

79

80

EC_SM B_CK 1

EC_SMB _DA 1

SOC_ SM L1C LK

SOC_SML1 DATA

49 9

+3VALW_PRI M

2. 2 K

+3VALW_PRI M

+3VLP_EC

100 ohm

0 ohm

EC_S MB_CK1 _CHGR

EC_S MB_DA1_C HGR

7

6

12

11

2

BATTE RY

CON N

Ch arge r

3

Need check

I2C Address Table

BUS

I2C_0 (+3VS)

I2C_1 (+3VS)

SOC_SMBCLK +3VS

SOC_SML1CLK

Device

Reserved (Touch Panel)

SB8787-1200 (TP-ELAN)

DIMM2

PCH-LP (SOC)

Addr ess( 7 bit)

0x2CTM-P 2969 -001 ( TP)

0x1 5

0xA4

0x9 0

+3VALW_PRIM

4

EC_SMB_CK1 +3VLP

BQ24780 (Charger IC)

BATTERY PACK

0x1 2 0x1 6

Addres s(8b it)

Wr ite

Rea d

4

Secu rity Cl assifica tion

Issued Da te

THIS SHEE T OF ENG INEERING DRAW ING I S THE P ROPRIETAR Y PRO PERTY O F CO MPAL ELE CTRONICS, INC. AND CON TAINS CON FIDENTIAL

AND TRA DE SE CRET INF ORMATION. THIS SHEET MAY NO T BE TRA NSFERED FRO M THE CU STODY O F THE COM PETENT DIVI SION OF R& D

DEPARTME NT EXC EPT AS AUTH ORIZED BY COMPAL ELE CTRONICS, INC . NE ITHER TH IS SHEE T NO R THE I NFORMATIO N IT CONTAINS

MAY BE USED BY O R DISCLO SED TO AN Y THIRD P ARTY WI THOUT PRI OR WR ITTEN CONSE NT OF COMP AL EL ECTRONICS, I NC.

A

B

2016/0 7/18 2016/1 1/10

C

Comp al Secre t Data

Decipher ed Date

CompalElectronics,Inc.

Tit le

SMBUS_Routing_Table

Size Docu ment N umber R e v

Custom

B5W11M/BLA-E061P

Da te : Sh eet

D

Da te : Sh eet

5 44Monday, July 18, 2016

E

1.0

o f

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B

C

D

E

PWR Sequence_SKL-U2+2_DDR3L_Value_NON CS

+RT CVC C

1

SOC _RT CRS T#

+19 VB

+3V LP

EC_ON

+5 VALW /+3VA LW(+3 VALW _D SW. ..)

SPO K tPCH06_Min : 200 us (+3VALW stable (@95% of full value) to +1.0VALW_PRIM startin g to ramp)

+1 .8 VALW _PR IM

+1 .8VALW _PG

+VCCP RIM_ CORE/ +1 .0 VALW _P RI M

EC_R SMRST #

ON/ OFF

2

PBT N_O UT#

PM_S LP_S 5#

ESP I_R ST#

PM_S LP_S 4#

SYSO N

+1. 0V_V CCST U

+1. 2V_ VDD Q

PM_S LP_S 3#

SUSP #

+1. 0VS_ VCC STG

+VCC IO

3

+5VS/+3V S/+ 1.8 VS /+1 .5V S

EC_V CCS T_P G

VR_O N

SM_PG _C TR L

+0.6V S_ VT T

+VCC _SA

VR_ PW RGD

PCH_ PWRO K (SYS _PWR OK)

H_CP UPW RGD

PLT_R ST#

4

+VCC_C ORE / +VCC _GT

tPCH01_Min : 9 ms

tPCH43_Min : 95 ms

tPCH04_Min : 9 ms

tPCH34_M ax : 2 0 ms

tPCH03_Min : 10 ms

Minimu m duratio n of PWRBT N# assertio n = 16mS. PWRB TN# can assert befo re or after RSM RST#

tPCH18_Min : 90 us

tCPU04 Min : 100 ns

tCPU10 Min : 1 ms

tCPU00 Min : 1 ms

tCPU19 Max : 100 ns

tCPU18 Max : 35 us

tCPU09 Min : 1 ms

tCPU16 Min : 0 ns

tPLT05 Min : Pla tform depend ent

1

2

3

4

Secur ity Cla ssifica tion

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/07/ 18 2016/11/10

Compal Secret Data

Deciphere d Date

CompalElectronics,Inc.

Title

PowerSequence

Size Document Number R ev

Custom

B5W11M/BLA-E061P

Date : Sheet

D

Date : Sheet

E

6 44Monday, July 18, 2016

1.0

of

A

B

C

D

E

1

Funct i onal Stra p Def ini t i ons

#543016 PDG2.0 P.844

DDP B_CTR LDATA DDP C_CTR LDATA Display Port B/C Detected NC =Port is not detected. PU =Port is detected.

2

+VCCIO

1

RC1 24.9_0402_1%

#543016 PDG2. 0 P.225 COMPENSATI ON PU for eDP Trace wi dth=5 mils, Spacing= 25mil,Max len gth=600mi ls

+1.0V_VCCST

RC2 1K_0402_5%

+3VS

RC157 100K_ 0402_5%

3

+1.0VS_VCCSTG

RC11 51_0402_5%CMC@

RC13 51_0402_5%CMC@

RC15 100_0402_5%CMC@

RC17 100_0402_5%CMC@

4

RC35 51_0402_5%CMC@

2

#543016 PDG2. 0 P.857 PU 1K to VCCST

1

2

1

2

@

CC52

@ESD@

.1U_0402_16V7K

H_PECI

1

2

CC53

@ESD@

.1U_0402_16V7K

H_PROCHOT#_R

1

2

For Intel debug, place to CPU side. #543016 PDG2. 0 P.629

1

2

1

2

1

2

1

2

1

2

EDP_COMP

H_THERMTRIP#

TP_INT#

SOC_XDP_TMS

SOC_XDP_TDI

SOC_XDP_TDO

CPU_XDP_TCK0

CPU sid e

CMC s ide

H_PROCHOT#<29>

EC_TP_IN T#<29,30>

HDMI

HDMI DDC (Port C)

SOC_DP2_CTRL_CLK<22> SOC_DP2_CTRL_DATA<22>

+1.0VS_VCCSTG

SPI touch INT follow CRB

SOC_DP2_N0<22>

SOC_DP2_P0<22> SOC_DP2_N1<22> SOC_DP2_P1<22>

SOC_DP2_N2<22> SOC_DP2_P2<22> SOC_DP2_N3<22>

SOC_DP2_P3<22>

SOC_DP2_CTRL_CLK SOC_DP2_CTRL_DATA

EDP_COMP

1

RC3 1K_0402_5%

RC4

499_0402_1%

2

1

2

RC9 100K_0402_5%

+3VS

I2C_TS_INT#<21>

@

1

2

DC2RB751V-40_SOD323-2

1

2

RC137 0_0402_5%

RC5 49.9_0402_1%

RC6 49.9_0402_1%

RC7 49.9_0402_1%

RC8 49.9_0402_1%

#543016 PDG2. 0 P.873 PROC_POPIR COMP/ PCH_ OPI RCO MP PD 50o hm

#544669 CRB1.1 P.52 EDRAM_O PIO_RCOMP/ EOPI O_R COM P PD 50o hm

1

2

1

2

1

2

1

2

UC1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKL-U_BGA1356

@

Reserve d CA TERR# for sight i ngs i ss ue c heck

H_PECI<29>

1

T166@

T160@

T161@

2

CPU_POPIRCOMP PCH_OPIRCOMP EDRAM_OPIO_RCOMP EOPIO_RCOMP

H_CATERR#

H_PECI

H_PROCHOT#_R

H_THERMTRIP#

XDP_BPM#0 XDP_BPM#1

I2C_TS_INT#

TP_INT#

DDI

DISPLAY SIDEBANDS

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKL-U_BGA1356

@

UC1D

SKL -U

1 OF 20

CPU MISC

EDP

SKL -U

4 OF 20

Rev_ 0.5 3

EDP_TXN[0]

EDP_TXP[0]

EDP_TXN[1]

EDP_TXP[1]

EDP_TXN[2]

EDP_TXP[2]

EDP_TXN[3]

EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP

DDI2_AUXN

DDI2_AUXP

DDI3_AUXN DDI3_AUXP

GPP_E13/DDPB_HPD0

GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

Rev_ 0.5 3

JTA G

PROC_TCK

PROC_TDI

PROC_TDO

PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI

PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

JTAGX

C47

C46

D46

C45

A45

B45

A47

B47

E45 F45

B52

G50 F50

E48

F48

G46 F46

L9

L7 L6 N9

L10

R12 R11

U13

B61 D60 A61

C60 B59

B56 D59

A56 C59

C61

A59

SOC_DP2_HPD

EC_SCI# CPU_EDP_HPD

ENBKL SOC_BKL_PWM

SOC_ENVDD

CPU_XDP_TCK0

SOC_XDP_TDI SOC_XDP_TDO

SOC_XDP_TMS SOC_XDP_TRST#

PCH_JTAG_TCK1

SOC_XDP_TDI SOC_XDP_TDO

SOC_XDP_TMS SOC_XDP_TRST#

CPU_XDP_TCK0

EDP_TXN0 <21> EDP_TXP0 <21>

EDP_TXN1 <21> EDP_TXP1 <21>

EDP_AUXN <21>

EDP_AUXP <21>

SOC_DP2_HPD <22>

EC_SCI# <29>

CPU_EDP_ HPD <21>

ENBKL <29> SOC_BKL_PWM <21>

SOC_ENVDD <21>

T194 @

T195 @

eDP

From HDMI

From e DP

EC_SCI#

RC212 10K_0402_5%

+3VS

1

2

@

EC_SCI# SO C in ternal PU

#545659 P CH EDS1.51 P.131 SCI capability is available on all GPIOs, while NMI and SMI capability is available on only select GPIO s. Below are the PCH GPIOs that can be routed to generate SMI# or NMI:

GPP_B14, GPP_B20, GPP_B23‧‧‧‧ GPP_C [ 23 : 22 ]‧‧‧‧ GPP_D [ 4 : 0 ]‧‧‧‧

GPP_E [ 8 : 0 ] , GPP_E [ 16 : 13 ]‧‧‧‧

CC81

@ESD@

SOC_XDP_TRST#

.1U_0402_16V7K

1

2

1

2

3

4

Secur ity Cla ssifica tion

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/07/ 18 2016/11/10

Compal Secret Data

Deciphere d Date

CompalElectronics,Inc.

Title

Size Document Number R ev

Custom

Date : Sheet

D

Date : Sheet

CompalElectronics,Inc.

SKL-U(1/12)DDI,MSIC,XDP,EDP

B5W11M/BLA-E061P

E

of

7 44Monday, July 18, 2016

of

7 44Monday, July 18, 2016

of

7 44Monday, July 18, 2016

1.0

A

B

C

D

E

Interleaved Memory

1

2

3

DDR_A_D[0..15]<19>

DDR_A_D[16..31]<19>

DDR_A_D[32..47]<19>

DDR_A_D[48..63]<19>

ZZZ

PCB B5W11 LA-E061P LS-D671P

DAZ1P5 00100

ES Sample

UC1

CPU_G0 2.6G

QKJW@

SA0000 9UR10

DDR_A_D0

DDR_A_D1 DDR_A_D2

DDR_A_D3 DDR_A_D4 DDR_A_D5

DDR_A_D6

DDR_A_D7

DDR_A_D8 DDR_A_D9

DDR_A_D10

DDR_A_D11 DDR_A_D12

DDR_A_D13

DDR_A_D14

DDR_A_D15

DDR_A_D16

DDR_A_D17

DDR_A_D18

DDR_A_D19 DDR_A_D20

DDR_A_D21 DDR_A_D22

DDR_A_D23

DDR_A_D24

DDR_A_D25

DDR_A_D26 DDR_A_D27

DDR_A_D28

DDR_A_D29

DDR_A_D30

DDR_A_D31

DDR_A_D32

DDR_A_D33

DDR_A_D34

DDR_A_D35

DDR_A_D36

DDR_A_D37

DDR_A_D38

DDR_A_D39

DDR_A_D40

DDR_A_D41

DDR_A_D42

DDR_A_D43

DDR_A_D44

DDR_A_D45

DDR_A_D46

DDR_A_D47

DDR_A_D48

DDR_A_D49

DDR_A_D50

DDR_A_D51

DDR_A_D52

DDR_A_D53 DDR_A_D54

DDR_A_D55

DDR_A_D56

DDR_A_D57

DDR_A_D58

DDR_A_D59

DDR_A_D60 DDR_A_D61 DDR_A_D62

DDR_A_D63

UC1B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKL-U_BGA1356

@

SKL -U

DDR0_CKN[0]

DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1]

DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1]

DDR0_ODT[0]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]

DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]

DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]

DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSP[3]/DDR0_DQSP[5]

DDR0_DQSN[4]/DDR1_DQSN[0]

DDR0_DQSP[4]/DDR1_DQSP[0]

DDR0_DQSN[5]/DDR1_DQSN[1]

DDR0_DQSP[5]/DDR1_DQSP[1]

DDR0_DQSN[6]/DDR1_DQSN[4]

DDR0_DQSP[6]/DDR1_DQSP[4]

DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

2 OF 20

DDR0_ODT[1]

DDR0_DQSN[0]

DDR0_DQSP[0]

DDR0_DQSN[1]

DDR0_DQSP[1]

DDR0_ALERT#

DDR_VREF_CA

DDR0_VREF_DQ

DDR1_VREF_DQ

DDR_VTT_CNTL

DDR0_MA[3]

DDR0_MA[4]

DDR0_PAR

DDR_PG_CTRL

DDR_A_CLK#0

AU53

DDR_A_CLK0

AT53

DDR_A_CLK#1

AU55

DDR_A_CLK1

AT55

DDR_A_CKE0

BA56

DDR_A_CKE1

BB56

AW56 AY56

DDR_A_CS#0

AU45

DDR_A_CS#1

AU43

DDR_A_ODT0

AT45

DDR_A_ODT1

AT43

DDR_A_MA5

BA51

DDR_A_MA9

BB54

DDR_A_MA6

BA52

DDR_A_MA8

AY52

DDR_A_MA7

AW52

DDR_A_BG0

AY55

DDR_A_MA12

AW54

DDR_A_MA11

BA54

DDR_A_ACT#

BA55

DDR_A_BG1

AY54

DDR_A_MA13

AU46

DDR_A_MA15

AU48

DDR_A_MA14

AT46

DDR_A_MA16

AU50

DDR_A_BA0

AU52

DDR_A_MA2

AY51

DDR_A_BA1

AT48

DDR_A_MA10

AT50

DDR_A_MA1

BB50

DDR_A_MA0

AY50

DDR_A_MA3

BA50

DDR_A_MA4

BB52

DDR_A_DQS#0

AM70

DDR_A_DQS0

AM69

DDR_A_DQS#1

AT69

DDR_A_DQS1

AT70

DDR_A_DQS#2

BA64

DDR_A_DQS2

AY64

DDR_A_DQS#3

AY60

DDR_A_DQS3

BA60

DDR_A_DQS#4

BA38

DDR_A_DQS4

AY38

DDR_A_DQS#5

AY34

DDR_A_DQS5

BA34

DDR_A_DQS#6

BA30

DDR_A_DQS6

AY30

DDR_A_DQS#7

AY26

DDR_A_DQS7

BA26

DDR_A_ALERT#

AW50

DDR_A_PAR

AT52

+0.6V_A_VREFCA

AY67 AY68

+0.6V_B_VREFCA

BA67

DDR_PG_CTRL

AW67

1

2

3

74AUP1G07GW_TSSOP5

Change PN to SA 00007UR00.

T14@

T15@

1

2

UC7

NC

VCC

A

GND

DDR_A_CLK#0 <19> DDR_A_CLK0 <19>

DDR_A_CLK#1 <19> DDR_A_CLK1 <19>

DDR_A_CKE0 <19>

DDR_A_CKE1 <19>

DDR_A_CS#0 <19>

DDR_A_CS#1 <19>

DDR_A_ODT0 <19>

DDR_A_ODT1 <19>

DDR_A_MA5 <19>

DDR_A_MA9 <19> DDR_A_MA6 <19> DDR_A_MA8 <19>

DDR_A_MA7 <19>

DDR_A_BG0 <19>

DDR_A_MA12 <19> DDR_A_MA11 <19>

DDR_A_ACT# <19> DDR_A_BG1 <19>

DDR_A_MA13 <19>

DDR_A_MA15 <19> DDR_A_MA14 <19> DDR_A_MA16 <19>

DDR_A_BA0 <19>

DDR_A_MA2 <19>

DDR_A_BA1 <19>

DDR_A_MA10 <19> DDR_A_MA1 <19> DDR_A_MA0 <19>

DDR_A_MA3 <19> DDR_A_MA4 <19>

DDR_A_DQS#0 <19>

DDR_A_DQS0 <19> DDR_A_DQS#1 <19> DDR_A_DQS1 <19>

DDR_A_DQS#2 <19> DDR_A_DQS2 <19> DDR_A_DQS#3 <19>

DDR_A_DQS3 <19> DDR_A_DQS#4 <19> DDR_A_DQS4 <19>

DDR_A_DQS#5 <19> DDR_A_DQS5 <19> DDR_A_DQS#6 <19>

DDR_A_DQS6 <19> DDR_A_DQS#7 <19> DDR_A_DQS7 <19>

DDR_A_ALERT# <19> DDR_A_PAR <19>

+0.6V_A_VREFCA

+0.6V_B_VREFCA

#543016 PDG2. 0 P.190 Trace width/S pacing >= 20mils Place com ponment nea r SODIMM

+1.2V_VDDQ

+3VS

CC57.1U_0402_16V7K

1

2

RC16 1M_0402_5%@

1

RC10 100K_0402_5%

5

4

Y

DDR_B_D[0..15]<20>

DDR_B_D[16..31]<20>

DDR_B_D[32..47]<20>

DDR_B_D[48..63]<20>

SM_PG_CTRL <37>

DDR_V TT_CNTL to DDR VTT suppl ied ramped <35u S (tC PU18 )

DDR_B_D0 DDR_B_D1

DDR_B_D2

DDR_B_D3

DDR_B_D4 DDR_B_D5

DDR_B_D6

DDR_B_D7

DDR_B_D8

DDR_B_D9

DDR_B_D10

DDR_B_D11

DDR_B_D12

DDR_B_D13

DDR_B_D14

DDR_B_D15

DDR_B_D16

DDR_B_D17

DDR_B_D18

DDR_B_D19

DDR_B_D20 DDR_B_D21

DDR_B_D22

DDR_B_D23

DDR_B_D24

DDR_B_D25 DDR_B_D26

DDR_B_D27 DDR_B_D28

DDR_B_D29

DDR_B_D30

DDR_B_D31

DDR_B_D32

DDR_B_D33

DDR_B_D34 DDR_B_D35

DDR_B_D36 DDR_B_D37

DDR_B_D38

DDR_B_D39

DDR_B_D40

DDR_B_D41

DDR_B_D42

DDR_B_D43

DDR_B_D44

DDR_B_D45

DDR_B_D46

DDR_B_D47

DDR_B_D48

DDR_B_D49 DDR_B_D50

DDR_B_D51

DDR_B_D52

DDR_B_D53

DDR_B_D54

DDR_B_D55

DDR_B_D56

DDR_B_D57

DDR_B_D58

DDR_B_D59

DDR_B_D60

DDR_B_D61

DDR_B_D62

DDR_B_D63

UC1C

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKL-U_BGA1356

@

SKL -U

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]

DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]

DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2]

DDR1_DQSP[0]/DDR0_DQSP[2]

DDR1_DQSN[1]/DDR0_DQSN[3]

DDR1_DQSP[1]/DDR0_DQSP[3]

DDR1_DQSN[2]/DDR0_DQSN[6]

DDR1_DQSP[2]/DDR0_DQSP[6]

DDR1_DQSN[3]/DDR0_DQSN[7]

DDR1_DQSP[3]/DDR0_DQSP[7]

DDR1_DQSN[4]/DDR1_DQSN[2]

DDR1_DQSP[4]/DDR1_DQSP[2]

DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[5]/DDR1_DQSP[3]

DRAM_RESET#

DDR_RCOMP[0]

DDR CH - B

3 OF 20

DDR_RCOMP[1]

DDR_RCOMP[2]

Rev_ 0.5 3Rev_ 0.5 3

DDR1_CKN[0] DDR1_CKN[1]

DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2]

DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1]

DDR1_ODT[0]

DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6]

DDR1_DQSP[6]

DDR1_DQSN[7]

DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR

DDR_B_CLK#0

AN45

DDR_B_CLK#1

AN46

DDR_B_CLK0

AP45

DDR_B_CLK1

AP46

DDR_B_CKE0

AN56

DDR_B_CKE1

AP55 AN55

AP53

DDR_B_CS#0

BB42

DDR_B_CS#1

AY42

DDR_B_ODT0

BA42

DDR_B_ODT1

AW42

DDR_B_MA5

AY48

DDR_B_MA9

AP50

DDR_B_MA6

BA48

DDR_B_MA8

BB48

DDR_B_MA7

AP48

DDR_B_BG0

AP52

DDR_B_MA12

AN50

DDR_B_MA11

AN48

DDR_B_ACT#

AN53

DDR_B_BG1

AN52

DDR_B_MA13

BA43

DDR_B_MA15

AY43

DDR_B_MA14

AY44

DDR_B_MA16

AW44

DDR_B_BA0

BB44

DDR_B_MA2

AY47

DDR_B_BA1

BA44

DDR_B_MA10

AW46

DDR_B_MA1

AY46

DDR_B_MA0

BA46

DDR_B_MA3

BB46

DDR_B_MA4

BA47

DDR_B_DQS#0

AH66

DDR_B_DQS0

AH65

DDR_B_DQS#1

AG69

DDR_B_DQS1

AG70

DDR_B_DQS#2

AR66

DDR_B_DQS2

AR65

DDR_B_DQS#3

AR61

DDR_B_DQS3

AR60

DDR_B_DQS#4

AT38

DDR_B_DQS4

AR38

DDR_B_DQS#5

AT32

DDR_B_DQS5

AR32

DDR_B_DQS#6

AR25

DDR_B_DQS6

AR27

DDR_B_DQS#7

AR22

DDR_B_DQS7

AR21

DDR_B_ALERT#

AN43

DDR_B_PAR

AP43

AT13

AR18

SM_RCOMP0

AT18

SM_RCOMP1

AU18

SM_RCOMP2

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

#543016 PDG2. 0 P.139 W=12-1 5 Space= 20/25 L =500mil

DDR_DRAMRST#

T17@ T18@

DDR_DRAMRST# <19,20>

1

RC38 121_0402_1%

1

RC39 80.6_0402_1%

1

RC40 100_0402_1%

@ESD@

1

CC70 .1U_0402_16V7K

2015MOW02, Can't install Cap on DRAMRST

DDR_B_CLK#0 <20>

DDR_B_CLK#1 <20>

DDR_B_CLK0 <20>

DDR_B_CLK1 <20>

DDR_B_CKE0 <20>

DDR_B_CKE1 <20>

DDR_B_CS#0 <20> DDR_B_CS#1 <20>

DDR_B_ODT0 <20> DDR_B_ODT1 <20>

DDR_B_MA5 <20>

DDR_B_MA9 <20> DDR_B_MA6 <20> DDR_B_MA8 <20>

DDR_B_MA7 <20>

DDR_B_BG0 <20>

DDR_B_MA12 <20> DDR_B_MA11 <20>

DDR_B_ACT# <20> DDR_B_BG1 <20>

DDR_B_MA13 <20>

DDR_B_MA15 <20> DDR_B_MA14 <20> DDR_B_MA16 <20>

DDR_B_BA0 <20>

DDR_B_MA2 <20>

DDR_B_BA1 <20>

DDR_B_MA10 <20> DDR_B_MA1 <20> DDR_B_MA0 <20>

DDR_B_MA3 <20> DDR_B_MA4 <20>

DDR_B_DQS#0 <20>

DDR_B_DQS0 <20> DDR_B_DQS#1 <20> DDR_B_DQS1 <20>

DDR_B_DQS#2 <20> DDR_B_DQS2 <20> DDR_B_DQS#3 <20>

DDR_B_DQS3 <20> DDR_B_DQS#4 <20> DDR_B_DQS4 <20>

DDR_B_DQS#5 <20> DDR_B_DQS5 <20> DDR_B_DQS#6 <20>

DDR_B_DQS6 <20> DDR_B_DQS#7 <20> DDR_B_DQS7 <20>

DDR_B_ALERT# <20>

DDR_B_PAR <20>

2

1

2

3

4

Secur ity Cla ssifica tion

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/07/ 18 2016/11/10

Compal Secret Data

Deciphere d Date

CompalElectronics,Inc.

Title

Size Document Number R ev

Custom

Date : Sheet

D

Date : Sheet

SKL-U(2/12)DDR4

B5W11M/BLA-E061P

Monday, July 18, 2016

of

8

of

8

of

E

8

4

1.0

44

A

1

UC1E

SPI0_CLK SPI0_MISO

SPI0_MOSI SPI0_IO2 SPI0_IO3

SPI0_CS0# SPI0_CS1# SPI0_CS2#

M2

GPP_D1/SPI1_CLK

M3

GPP_D2/SPI1_MISO

J4

GPP_D3/SPI1_MOSI

V1

GPP_D21/SPI1_IO2

V2

GPP_D22/SPI1_IO3

M1

GPP_D0/SPI1_CS#

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

SKL-U_BGA1356

@

SOC_SPI_IO3_0_R

1

SOC_SPI_SI_0_R

2

SOC_SPI_CLK_0_R

3

SOC_SPI_SO_0_R

4

SOC_SPI_IO2_0_R

1

SPI - F LASH

SPI - TOUCH

C LINK

SPI ROM

SOC_SPI_CLK SOC_SPI_SO SOC_SPI_SI

SOC_SPI_IO2

SOC_SPI_IO3

SOC_SPI_CS#0

AW3

AW2

AV2

AV3

AU4

AU3 AU2 AU1

SPI Touch

2

EC_KBRST#_R<29>

TPM_SERIRQ<29>

3

EC_KBRST#_R

TPM_SERIRQ

LPC Mo de

RPC5 and RC52 are close UC2

SOC_SPI_IO3 SOC_SPI_SI

SOC_SPI_CLK

SOC_SPI_SO

SOC_SPI_IO2

AW13

AY11

RPC5

8

7

6 5

15_0804_8P4R_5%

2

RC52 15_0402_5%

SKL -U

SOC_SPI_CS#0

SOC_SPI_SO_0_R

SOC_SPI_IO2_0_R

B

SMBUS, SMLINK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

LPC

5 OF 20

SOC_SPI_CLK_0_R

ROM Socket, co- lay with UC2 .

SOC_SPI_CS#0

SOC_SPI_IO2_0_R SOC_SPI_IO3_0_R

GPP_A1/LAD0/ESPI_IO0

GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

SPI ROM ( 8MByte )

UC2

1

/CS

2

DO(IO1)

3

4

/HOLD(IO3)

/WP(IO2)

GND

W25Q64FVSSIQ_SO8

DI(IO0)

1

2

@EMI@

RC24 0_0402_5%

JC1

1

CS#

3

WP#

7

HOLD#

4

GND

ACES_91960-0084N_MX25L3206EM2I

CONN@

VCC

CLK

SI/SIO0

SO/SIO1

VCC

SCLK

C

SOC_SMBCLK

R7

SOC_SMBDATA

R8

SOC_SMBALERT#

R10

SOC_SML0CLK

R9

SOC_SML0DATA

W2

SOC_SML0ALERT#

W1

SOC_SML1CLK

W3

SOC_SML1DATA

V3

SOC_SML1ALERT#

AM7

Change RC 144~RC14 7, RC45 to 1 5ohm w hen use ESPI

LPC_AD0

+3VALW_SPI

8

SOC_SPI_IO3_0_R

7

SOC_SPI_CLK_0_R

6

SOC_SPI_SI_0_R

5

AY13

BA13 BB13 AY12

BA12 BA11

AW9

AY9 AW11

1

LPC_AD1

LPC_AD2

LPC_AD3

LPC_FRAME#

ESPI_RST#

CLKOUT_LPC0

PM_CLKRUN#

CC8 .1U_0402_16V7K

2

RC144 0_0402_5%@

RC145 0_0402_5%@

RC146 0_0402_5%@

RC147 0_0402_5%@

T239@

Strap Pin

2

SOC_SML1CLK <29> SOC_SML1DATA <29>

T234@

1

2

1

2

1

2

1

2

LPC_FRAME# <29> ESPI_RST# <29>

1

2

RC45 22_0402_5%

LPC@

2015MOW06 n o need PU1K on SPI_IO2/I O3

1

2

CC9

@EMI@

10P_0402_50V8J

+3VALW_SPI

8

SOC_SPI_CLK_0_R

6

SOC_SPI_SI_0_R

5

SOC_SPI_SO_0_R

2

SOC_SPI_IO2

SOC_SPI_IO3

1

RC2024.7K_0402_5% ESPI@

SMB

+3VALW_PRIM

SML 1

LPC_AD0_R <29>

LPC_AD1_R <29>

LPC_AD2_R <29> LPC_AD3_R <29>

CLK_LPC_EC <29>

1

RC47 1K_0402_1%@

1

RC48 1K_0402_1%@

(to DDR, G sensor )

( to EC , Therma l se nsor)

ESPI / LPC Bus

ESPI : +1. 8V LPC : +3.3V

*

To EC

+3VALW_SPI

2

D

SOC_SMBCLK_1

SOC_SMBDATA_1

SOC_SML0CLK

SOC_SML0DATA

SOC_SML1CLK SOC_SML1DATA SOC_SMBCLK

SOC_SMBDATA

+3VS

SOC_SMBCLK

SOC_SMBDATA

*

3

D

PM_CLKRUN#

TPM_SERIRQ

SML0ALERT# / GPP_C5 (Internal Pull Down): (Sampled: Rising edge of RSMRST# )

eSPI or LPC 0 = LPC is selected for EC --> For KB9022/9032 Use 1 = eSPI is selected for EC --> For KB9032 Only.

SMBALERT# / GPP_C2 (Internal Pull Down): (Sampled: Rising edge of RSMRST# )

TLS Conf i den tiali ty 0 = Disable Intel ME Crypto Transport Layer Security (TLS) cipher suite (no conf i dent iali ty). 1 = Enable Intel ME Crypto (TLS) (with conf i dent ial i ty). Must be pulled up to support Intel AMT with TLS and Intel SBA (Small Business Advantage) with TLS.

5

G

6

RC222 2.2K_0402_5%

RC223 2.2K_0402_5%

RC49 499_0402_1%

RC50 499_0402_1%

QC2B 2N7002KDW_SOT363-6

SOC_SMBCLK_1

4

S

2

G

QC2A

2N7002KDW_SOT363-6

1

S

D

RC107 10K_0402_5%

RC112 10K_0402_5%

1

RPC7

1

2 3

4

2.2K_0804_8P4R_5%

SOC_SMBDATA_1

1

2

1

2

E

2

8

7

6 5

+1.8VS_3VS_PGPPA

+3VS

+3VALW_PRIM

1

SOC_SMBCLK_1 <19,20>

SOC_SMBDATA_1 <19,20>

2

3

4

Secur ity Cla ssifica tion

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/07/ 18 2016/11/10

Compal Secret Data

Deciphere d Date

CompalElectronics,Inc.

Title

SKL-U(3/12)SPI,ESPI,SMB,LPC

Size Document Number R ev

Custom

B5W11M/BLA-E061P

Date : Sheet

D

Date : Sheet

E

of

9 44Monday, July 18, 2016

of

9 44Monday, July 18, 2016

of

9 44Monday, July 18, 2016

4

1.0

A

B

C

D

E

1

HDA for AUDIO

HDA_SDIN0<25>

HDA_SYNC_R<25> HDA_SDOUT_R<25>

HDA_BIT_CLK_R<25> HDA_RST#_R<25>

ME_EN<29>

HDA_SDO / I2S_TXD0 (Inter nal Pull Down): (Sampled : Risi ng e dge of P CH_PWROK ) Flash D escriptor S ecurity Over ride 0 = Enable security measures def i ne d i n t he Fl ash

2

Descri pto r. 1 = Dis able Flash Descriptor Security (overrid e). T his strap should only be assert ed h igh using external

pull-up in man ufacturing/d ebug env ironments ON LY.

SPKR / GPP_B14 (Internal Pull Down): (Sampled:Rising edge of PCH_PWROK)

TOP Swap Override 0 = Disable TOP Swap mode.

*

1 = Enable TOP Swap Mode.

Intel HD Audio link capabilit i es > Two SDI signals to su pport two externa l codecs. > Drivers variable requency (5MHz to 24MHz) B CLK to support:

-- SDO double pumped up to 48 Mb/s

-- SDI's single pumped up to 24 Mb/s > Provides cadence for 44.1 kHz based sample r ate o utput. > Support 1.5V, 1.8V, and 3.3V modes.

3

RPC9

1 2

3

4

33_0804_8P4R_5%

1

@

RC77 0_0402_5%

HDA_SDIN0

8

7 6

5

2

HDA_SYNC HDA_SDOUT HDA_BIT_CLK HDA_RST#

1

9 OF 20

SKL -U

7 OF 20

CSI2_CLKN0 CSI2_CLKP0

CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2

CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EM M C

GPP_F13/EMMC_DATA0

GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3

GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6

GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

SDIO/ SDX C

GPP_G0/SD_CMD

GPP_G1/SD_DATA0

GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_A17/SD_PWR_EN#/ISH_GP7

Rev_ 0.5 3

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

C37 D37

C32 D32 C29

D29 B26 A26

CSI2_COMP

E13

DGPU_PRSNT#

B7

AP2

AP1 AP3 AN3

AN1 AN2 AM4

AM1

AM2 AM3

AP4

EMMC_RCOMP

AT1

Rev_ 0.5 3

AB11 AB13

AB12 W12 W11

W10 W8 W7

BA9 BB9

AB7

SD_RCOMP

AF13

GPP_F23

#543016 PDG2. 0 P.551

2

RC80 100_0402_1%

2

RC89 200_0402_1%

#543016 PDG2. 0 P.393

#543016 PDG2. 0 P.403 SDIO signals are mult i pl ex ed wi t h GPI Os a nd def ault to GPIO fu nct i onalit y ( as i nput). I f S DI O i nt erf ace i s not used, the signals can be used as GPIOs instead. If the GPIO funct i onali t y is al s o not use d, t he si gnal s can be lef t as no-c onnect.

RC76

200_0402_1%

SD_RCOMP

1

2

#543016 PDG2. 0 P.879

1

+3VALW_1.8VALW_PGPPD

DGPU_PRSNT#

2

1

RC133 10K_0402_5%

2

3

UC1G

HDA_SYNC HDA_BIT_CLK

HDA_SDOUT HDA_SDIN0

HDA_RST#

PCH_SPKR<25>

PCH_SPKR

BA22 AY22

BB22 BA21 AY21

AW22

AY20

AW20

AK10

AW5

AK7 AK6

AK9

A36 B36

C38 D38 C36

D36 A38 B38

C31 D31 C33

D33 A31 B31

A33 B33

A29

B29 C28 D28 A27 B27 C27

D27

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK

HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK I2S1_SFRM

I2S1_TXD

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK

GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKL-U_BGA1356

@

UC1I

CSI-2

CSI2_DN0 CSI2_DP0

CSI2_DN1 CSI2_DP1 CSI2_DN2

CSI2_DP2 CSI2_DN3 CSI2_DP3

CSI2_DN4 CSI2_DP4 CSI2_DN5

CSI2_DP5 CSI2_DN6 CSI2_DP6

CSI2_DN7 CSI2_DP7

CSI2_DN8

CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11

CSI2_DP11

SKL-U_BGA1356

@

AUDIO

SKL _U LT

4

Secur ity Cla ssifica tion

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/07/ 18 2016/11/10

Compal Secret Data

Deciphere d Date

CompalElectronics,Inc.

Title

SKL-U(4/12)HDA,EMMC,SDIO,CSI2

Size Document Number R ev

Custom

B5W11M/BLA-E061P

Date : Sheet

Monday, July 18, 2016

Date : Sheet

Monday, July 18, 2016

D

Monday, July 18, 2016

E

of

10

of

10

of

10

4

1.0

44

A

B

C

D

E

+RTCVCC

1

RC91 20K_0402_5%

CC10 1U_0402_6.3V6K

RC93 20K_0402_5%

CC11 1U_0402_6.3V6K

JCMOS1 0_0603_5%@

2

1

2

1

2

1

2

1

2

SOC_SRTCRST#

SOC_RTCRST#

Place at RAM DOOR

1

RC113 1K_0402_5%

RC116

60.4_0402_1%

2

1

SM_INTRUDER#

CLKREQ_PCIE#1

CLKREQ_PCIE#2

CLKREQ_PCIE#5 CLKREQ_PCIE#4

CLKREQ_PCIE#3 CLKREQ_PCIE#0

2

PCH_PWROK

EC_RSMRST#

SYS_RESET#

LAN_WAKE#

SYS_PWROK

WAKE#

SYS_RESET#

H_CPUPWRGD

SYS_PWROK

PCH_PWROK

EC_RSMRST#

1

RPC12

2

1 2

3

4

+1.0V_VCCST

2

RC94 1M_0402_5%

+3VS

2

1

RC121 10K_0402_5%

1

RC123 10K_0402_5%

8

7 6

5

10K_0804_8P4R_5%

From EC(open-drain)

EC_VCCST_PG_R<29,32>

Note fo r VCCST_PWR GD

1. 1.0V to lerance

2. PDG2. 0 P.598 Figure4 3-5 note17: whe n failure eve nts, VCCST_PW RGD and PCH_PWROK de-a ssert at the same t i me

+3VALW_PRIM

+3VALW_DSW

3

4

RC110 10K_0402_5%

+3VALW_DSW

RC104 1K_0402_5%

WAKE# (DSX wa ke event) 10 KΩ pull- up t o Vcc DS W 3_3. The pull-up is required even if PCIe* interface is not used on the plat f or m.

RPC11

1

8

2

7

3

6

4

5

10K_0804_8P4R_5%

1

2

1

2

@ESD@

1

2

CC51 .1U_0402_16V7K

@ESD@

1

2

CC50 .1U_0402_16V7K

@ESD@

1

2

CC66 .1U_0402_16V7K

@ESD@

1

2

CC65 .1U_0402_16V7K

@ESD@

1

2

CC69 .1U_0402_16V7K

CLR CM OS

EC_VCCST_PG

GL AN

NG FF

SOC_XTAL24_IN

SOC_XTAL24_OUT

UC1J

D42

CLKOUT_PCIE_N0

C42

CLKREQ_PCIE#0

CLK_PCIE_N1<23> CLK_PCIE_P1<23> CLKREQ_PCIE#1<23>

CLK_PCIE_N2<24> CLK_PCIE_P2<24> CLKREQ_PCIE#2<24>

PLT_RST#<29>

EC_RSMRST#<29>

T95 @

T89 @

SYS_PWROK<29,32>

PCH_PWROK<29,32>

SUSPWRDNACK<29>

T92 @

CLK_PCIE_N1

CLK_PCIE_P1 CLKREQ_PCIE#1

CLK_PCIE_N2

CLK_PCIE_P2

CLKREQ_PCIE#2

CLKREQ_PCIE#3

CLKREQ_PCIE#4

CLKREQ_PCIE#5

PLT_RST#

SYS_RESET# EC_RSMRST#

H_CPUPWRGD EC_VCCST_PG

SYS_PWROK

PCH_PWROK PCH_DPWROK

SUSPWRDNACK

SUSACK#

WAKE#

LAN_WAKE#

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKL-U_BGA1356

@

UC1K

SYSTEM POWER MANAGEMENT

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKL-U_BGA1356

@

PBTN_OUT#<29>

SYS_PWROK

EC_RSMRST#

PCH PLTRST Buf f er

PLT_RST#

UC3 MC74VHC1G08DFT2G_SC70-5

RC125

SKL _U LT

CLOCK SIGNALS

10 OF 20

SKL -U

GPP_B11/EXT_PWR_GATE#

11 OF 20

PBTN_OUT#_R

1

2

@

RC109 0_0402_5%

RC114 0_0402_5%

RC122 0_0402_5%

2

1

2

B

A

2

+3VS

PCH_DPWROK

1

@

PCH_PWROK

1

@

5

P

PLT_RST_BUF#

4

Y

G

@

3

1

0_0402_5%@

Rev_ 0.5 3

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

Rev_ 0.5 3

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B2/VRALERT#

PLT_RST_BUF# <23,24>

1

RC118 100K_0402_5%

2

F43 E43

BA17

E37 E35

E42

AM18 AM20

AN18 AM16

AT11 AP15 BA16

AY16

AN15 AW15

BB17 AN16

BA15

AY15 AU13

AU11

AP16

AM10 AM11

CLK_CPU_ITP#

CLK_CPU_ITP

SUSCLK

SOC_XTAL24_IN SOC_XTAL24_OUT

XCLK_BIASREF

SOC_RTCX1

SOC_RTCX2

SOC_SRTCRST# SOC_RTCRST#

PM_SLP_S0#

PM_SLP_S3#

PM_SLP_S4# PM_SLP_S5#

SLP_SUS#

SLP_LAN# SLP_WLAN# PM_SLP_A#

PBTN_OUT#_R AC_PRESENT PM_BATLOW#

SM_INTRUDER#

EXT_PWR_GATE#

SOC_VRALERT#

T164 @

T165 @

T185 @

PM_SLP_S0# <29> PM_SLP_S3# <29,32> PM_SLP_S4# <29,32>

T84@

T90@

T87@

T88@

T94@

AC_PRESENT <29>

T91@

T93@

1

2

Foll ow 2014M OW48 Skylake U PU 2.7k ohm to 1V Cannonla ke U PD 60.4 ohm

XCLK_BIASREF

XCLK_BIA SRE F T:50ohm S :12/15 L:1000 Via:2

201 4M OW4 8: Skylake-U use 24M 50 oh m ESR Cannonl ake U use 38.4M 30 o hm E SR

SOC_RTCX2

SOC_RTCX1

Change PN to SJ10000Q400

CC15

6.8P_0402_50V8C

PBTN_OUT#_R

AC_PRESENT

PM_BATLOW#

SOC_VRALERT#

1

2

RC111 100K_0402_5%@

RC106 10K_0402_5%@

RC103 10K_0402_5%

1

2

RC92 1M_0402_5%

YC1 24MHZ_12PF_7V24000020

3

CC12

15P_0402_50V8J

1

RC96 2.7K_0402_1%

1

RC136 60.4_0402_1%@

RC98 10M_0402_5%

1

32.768KHZ_9PF_X1A000141000200

PCH internal PU

1

EC internal PU

1

Default : GPI

2

RC115 10K_0402_5%@

GND

4

1

YC2

CC16

8.2P_0402_50V8D

2

1

GND

2

1

CC13

15P_0402_50V8J

1

2

+1.0VALW_CLK5_F24NS

1

2

+3VALW_DSW

+3VALW_PRIM

1

2

3

4

#543016 PDG2. 0 P.599 PROCPWRGD is used only for pow er seq uence debug and is not required to be connected to anything on the plat f or m .

A

Secur ity Cla ssifica tion

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/07/ 18 2016/11/10

Compal Secret Data

Deciphere d Date

CompalElectronics,Inc.

Title

SKL-U(5/12)CLK,GPIO

Size Document Number R ev

Custom

B5W11M/BLA-E061P

Date : Sheet

D

Date : Sheet

E

11 44Monday, July 18, 2016

1.0

of

A

B

C

D

E

1

+3VS

RC62 49.9K_0402_1%

RC63 49.9K_0402_1%

RC64 49.9K_0402_1%

2

RC65 49.9K_0402_1%

+3VALW_PGPPC

+3VS

RC126 1K_0402_5%

RC127 1K_0402_5%

RC128 2.2K_0402_5%

RC129 2.2K_0402_5%

3

1

2

@

2

@

1

UART_2_CRXD_DTXD

UART_2_CTXD_DRXD

UART_2_CRTS_DCTS

UART_2_CCTS_DRTS

2

I2C_0_SDA I2C_0_SCL

I2C_1_SDA

I2C_1_SCL

UART_2_CRXD_DTXD<24>

UART_2_CTXD_DRXD<24>

no use

I2C_0_SDA<21> I2C_0_SCL<21>

I2C_1_SDA<30>

I2C_1_SCL<30>

TS_EN<21,29>

T135 @

T134 @

T131 @

T130 @

T128 @

T129 @

T111@

T112@

TS_EN

GSPI0_MOSI

GSPI1_MOSI

UART_2_CRXD_DTXD UART_2_CTXD_DRXD UART_2_CRTS_DCTS

UART_2_CCTS_DRTS

I2C_0_SDA I2C_0_SCL

I2C_1_SDA I2C_1_SCL

I2C_2_SDA I2C_2_SCL

I2C_3_SDA I2C_3_SCL

I2C_4_SDA I2C_4_SCL

UC1F

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

SKL-U_BGA1356

@

LP SS ISH

Funct i onal Stra p Def ini t i o

GSPI0_MOSI /GPP _B18 (Internal Pull Down): (Rising edge of PCH_PWROK) No Reboot

0 = Disable No Reboot mode. --> AAX05 Use

*

1 = Enable No Reboot Mode. (PCH will disable the TCO Timer system reboot feature). This funct i on i s usef ul when running ITP/XDP.

GSPI1_MOSI / GPP_B22 (Internal Pull Down): (Rising edge of PCH_PWROK)

Boot BIOS Strap Bit 0 = SPI Mode --> AAX05 Use

*

1 = LPC Mode

SKL -U

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

6 OF 20

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A18/ISH_GP0

GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3

GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

Rev_ 0.5 3

GPP_D9

GPP_D10

GPP_D11 GPP_D12

P2

P3

P4 P1

M4 N3

N1

N2

AD11

AD12

U1

U2 U3 U4

AC1 AC2 AC3

AB4

AY8

BA8 BB7 BA7

AY7 AW7

AP13

CPU_ID

PROJECT_ID0 PROJECT_ID1

ISH_I2C0_SDA

ISH_I2C0_SCL

ISH_I2C1_SDA

ISH_I2C1_SCL

I2C_5_SDA I2C_5_SCL

ISH sensor HUB (Reserve f or Verif y)

T105 @

T106 @

no use

SkyL ake Kab yLake

PROJECT_ID0

PROJECT_ID1

Project ID

*

B5W 1 S Res erved Res erved Res erved

ISH_I2C1_SCL ISH_I2C1_SDA

ISH_I2C0_SCL ISH_I2C0_SDA

CPU _ID

0 1

2

RC207 10K_0402_5%@

1

RC210 10K_0402_5%

2

RC211 10K_0402_5%@

1

RC213 10K_0402_5%

1

2

3 4

@

+1.8VS_3VS_PGPPA

CPU_ID

1

2

1

2

0 0 0 1 1 1

+3VALW_1.8VALW_PGPPD

RPC19

8 7

6

5

1K_0804_8P4R_5%

RC177 0_0402_5% ESPI@

RC178

0_0402_5% @

+3VALW_1.8VALW_PGPPD

1

RC215 10K_0402_5%

KBL@

2

1

RC214 10K_0402_5%

SKL@

2

+3VALW_1.8VALW_PGPPD

Project_ ID 0Project_ ID 1

GPP_D11GPP_D 12

1 0

+3VS

+1.8VS

1

2

1

2

1

2

3

4

Secur ity Cla ssifica tion

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/07/ 18 2016/11/10

Compal Secret Data

Deciphere d Date

CompalElectronics,Inc.

Title

SKL-U(6/12)GPIO

Size Document Number R ev

Custom

B5W11M/BLA-E061P

Date : Sheet

D

Date : Sheet

E

of

12 44Monday, July 18, 2016

of

12 44Monday, July 18, 2016

of

12 44Monday, July 18, 2016

4

1.0

A

B

C

D

E

UC1H

PCIE/ US B3/ SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

1

T196@

T197@

1

PCIE_CRX_DTX_N5 PCIE_CRX_DTX_P5

PCIE_CTX_DRX_N5

PCIE_CTX_DRX_P5

PCIE_CRX_DTX_N6 PCIE_CRX_DTX_P6

PCIE_CTX_DRX_N6

PCIE_CTX_DRX_P6

PCIE_RCOMPN PCIE_RCOMPP

XDP_PRDY# XDP_PREQ#

PIRQA#

PCIE_CR X_DTX_N5<23>

GL AN

NGFF WLAN+BT(Key E)

2

HD D

OD D

3

PCIE_CR X_DTX_P5<23> PCIE_CTX_C_DRX_N5<23>

PCIE_CTX_C_DRX_P5<23>

PCIE_CR X_DTX_N6<24> PCIE_CR X_DTX_P6<24>

PCIE_CTX_C_DRX_N6<24> PCIE_CTX_C_DRX_P6<24>

SATA_CRX_DTX_N0<26> SATA_CRX_DTX_P0<26>

SATA_CTX_DRX_N0<26>

SATA_CTX_DRX_P0<26>

SATA_CRX_DTX_N1<26>

SATA_CRX_DTX_P1<26>

SATA_CTX_DRX_N1<26> SATA_CTX_DRX_P1<26>

+3VALW_PRIM

1

2

CC25 .1U_0402_16V7K

1

2

CC26 .1U_0402_16V7K

1

2

CC60 .1U_0402_16V7K

1

2

CC62 .1U_0402_16V7K

#543016 PDG2. 0 P.285 PCIE_R COMPN/PCIE _RC OMP P BO=4 W= 12 S=12 R=1 00ohm

1

RC120 100_0402_1%

2

RC135 10K_0402_5%@

When PCIE8/ SATA1A is us ed as SATA Port 1 (ODD), then PCIE11/SAT A1B (M.2 SS D) cannot be used as SATA Port

1.

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL-U_BGA1356

@

SKL -U

8 OF 20

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP

USB3_2_TXN/SSIC_1_TXN USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN

USB3_3_RXP/SSIC_2_RXP

USB3_3_TXN/SSIC_2_TXN USB3_3_TXP/SSIC_2_TXP

USB 2

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2#

GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1

GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1

GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

Rev_ 0.5 3

USB3_1_RXN USB3_1_RXP USB3_1_TXN

USB3_1_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN

USB3_4_TXP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3

USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6

USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9

USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

H8 G8 C13

D13

J6 H6

B13 A13

J10

H10 B15 A15

E10 F10 C15

D15

USB20_N1

AB9

USB20_P1

AB10

USB20_N2

AD6

USB20_P2

AD7

USB20_N3

AH3

USB20_P3

AJ3

AD9 AD10

USB20_N5

AJ1

USB20_P5

AJ2

USB20_N6

AF6

USB20_P6

AF7

USB20_N7

AH1

USB20_P7

AH2

USB20_N8

AF8

USB20_P8

AF9

AG1

AG2

AH7 AH8

2015MOW10 , USB2_ID Co nnected to GN D Directly

USB2_COMP

AB6

USB2_ID

AG3

USB2_VBUSSENSE

AG4

USB_OC0#

A9 C9 D9

Unused OC pin need set to GPI.

B9

J1 J2

J3

H2 H3

G4

H1

USB3_CRX_DTX_N1 <28>

USB3_CRX_DTX_P1 <28>

USB3_CTX_DRX_N1 <28>

USB3_CTX_DRX_P1 <28>

USB20_N1 <28> USB20_P1 <28>

USB20_N2 <28> USB20_P2 <28>

USB20_N3 <28> USB20_P3 <28>

USB20_N5 <24> USB20_P5 <24>

USB20_N6 <21>

USB20_P6 <21>

USB20_N7 <21> USB20_P7 <21>

USB20_N8 <28>

USB20_P8 <28>

1

RC119 113_0402_1%

RC130 0_0402_5%

RC131 0_0402_5%

2

1

2

1

2

USB_OC0# <28>

USB3 MB

USB2 MB

TO D/B U SB2

BT

TS

Ca mer a

TO D/B CR

USB_OC0#

RC132 10K_0402_5%

1

2

+3VALW_PRIM

1

2

3

GP I O

US B _O C 0 #

US B _O C 1 #

US B _O C 2 #

US B _O C 3 #

DE V S L P0

DE V S L P1

DE V S L P2

SA T A_ G P 0

4

A

SA T A_ G P 1

SA T A_ G P 2

B

DEVI CE C ONTR OL

USB2 Port 1

NA

DEVSL P[2:0] Imp lementa t i o n DEVSLP is a host-controlled hardware signal which enables a SATA host and device to enter an ultr a-low interface power s tate, including the po ssibility to com pletely power down host and device PHYs. The processor pro vides three SATA DEVSLP signals, DEVSLP[ 2:0] for SKL U.

When hi gh, DEVSLP re quests t he S AT A devic e t o ent er i nt o t he DEVSL P po wer st at e. ‧‧‧‧ When l o w, DEVSL P r e quests t he SATA devi ce t o exit fr o m t he DEVSL P po wer stat e ‧‧‧‧

and transit i o n t o ac t i ve state.

SATA Gene ral Purpose ( SATAGP[2:0]) Signal s

The pr ocess or pr ovi des t hr ee S AT A ge ner al pur pos e i nput si gnal s, SATAGP[ 2: 0] f or S KL U. ‧‧‧‧

These signals can be conf i g ur ed as i nt erl ock s wi tc h i nputs c orr es pondi ng t o a gi ve n S ATA port.

When use d as a n i nt erl ock s wit c h st at us i ndi ca t i on, this si g nal s houl d be dr i ven to 0 ‧‧‧‧

to indicate that the switch is clos ed and to a 1 to indicate that the switch is open.

If mecha ni cal pr es ence s wit c hes will not be used on t he pl a t fo rm, SAT AGP[2: 0] ‧‧‧‧

signals can be conf i g ur ed as GPP_E[ 2: 0] GPI Os si gnal s.

Secur ity Cla ssifica tion

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/07/ 18 2016/11/10

Compal Secret Data

Deciphere d Date

D

CompalElectronics,Inc.

Title

SKL-U(7/12)PCIE,USB,SATA

Size Document Number R ev

Custom

B5W11M/BLA-E061P

Date : Sheet

E

of

13 44Monday, July 18, 2016

of

13 44Monday, July 18, 2016

of

13 44Monday, July 18, 2016

4

1.0

A

B

C

D

E

+1.0VALW_PRIM TO +1.0V_VCCSTU / +1.0VCCST

+5VALW

+1.0VALW_PRIM

1U_0402_6.3V6K

CC98

1

2

1

SYSON<29,32,37>

SUSP#<29,32,35,37>

2

3

+1.0VALW_PRIM

1

Imax : 3.44 A

For Power consumption Measure ment

CC107 .1U_0402_16V7K

1

2

@

SUSP#

2

CC105 .1U_0402_16V7K

1

RC142 20K_0402_5%

1

RC168 0_0402_5%@

2

+1.8VALW_PRIM

JPC4

2

1

2

JUMP_43X79

@

+5VALW

1

RC186 0_0402_5%

1

2

1

CC104 1U_0402_6.3V6K@

1

2

JPC8 JUMP_43X39

@

+1.0VALW_PRIM TO +1.0VS_VCCSTG

+1.0VALW_PRIM_JP

1U_0402_6.3V6K

CC117

1

2

SUSP#_R1

2

@

1U_0402_6.3V6K

CC106

1

@

2

+1.0VALW_PRIM_JP

SUSP#_R1

+5VALW

1U_0402_6.3V6K

CC97

1

@

2

EN_1.0V_VCCSTU

EN_1.8VS

+1.8VALW_VS

2

1U_0402_6.3V6K

CC99

1

@

2

+1.8VALW_PRIM TO +1.8VS

UC6

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

UC8

1

VIN

2

VIN

3

ON

4

VBIAS

AOZ1336_DFN8_2X2

VOUT

GND

@

VOUT VOUT

CT

GND GND

UC5

1

VOUT1

VIN1

2

VOUT1

VIN1

3

4

5

6

7

EM5209VF_DFN14_2X3

6

5

7 8

6

5 9

CT1

ON1

GND

VBIAS

ON2

CT2

VIN2

VOUT2

VIN2

VOUT2

GPAD

+1.0VS_VCCSTG_IO

@

1

CC126 1000P_0402_50V7K

14

13

12

11

10

9

8

15

VCCSTG, VCCIO SLEW RATE <=10 ms

2

+1.0V_VCCSTU

1

CC95

1000P_0402_50V7K

1

CC94

1000P_0402_50V7K

1

RC188 0_0402_5%@

JPC5

@

1

JUMP_43X79

1

CC127 .1U_0402_16V7K

2

+1.8VS

1

CC96 .1U_0402_16V7K

2

1

CC100 .1U_0402_16V7K

2

+1.0VS_VCCSTG

+VCCIO

Imax : 3.4 A

+1.2V_VDDQ

JPC1

1

@

JUMP_43X118

JPC2

1

@

JUMP_43X118

+1.0VS_VCCSTG

+1.2V_VCCSFR_OC

+1.0V_VCCSFR

+1.2V_VDDQ_CPU

RC208 0_0402_5%@

+1.0V_VCCSTU

RC140 0_0402_5%@

RC143 0_0402_5%@

+1.2V_VDDQ_CPU

RC141 0_0402_5%@

2

+1.2V_VDDQC

+1.0V_VCCST

1

+1.2V_VDDQ_CPU

2

+1.0VS_VCCSTG

UC1N

CPU POWER 3 OF 4

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

BB47

VDDQ_BB47

BB51

VDDQ_BB51

AM40

0. 0 9 A

VDDQC

A18

0. 0 4 A

VCCST

A22

VCCSTG_A22

AL23

VCCPLL_OC

K20

VCCPLL_K20

K21

VCCPLL_K21

SKL-U_BGA1356

@

+1.2V_VDDQC

CC47 10U_0603_6.3V6M

+1.0V_VCCST

CC48 1U_0402_6.3V6K

+1.0V_VCCSFR

CC55 1U_0402_6.3V6K

+1.2V_VCCSFR_OC

CC49 1U_0402_6.3V6K

CC56 1U_0402_6.3V6K

SKL -U

6. 3 5 A

0. 0 4 A

0. 2 6 A

0. 1 2 A

14 OF 20

PSC Si de

1

2

PSC Si de

1

2

PSC Si de

1

2

BSC Si de

1

2

1

2

@

2. 7 3 A

6A

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE VCCSA_SENSE

BSC Si de

Rev_ 0.5 3

VCCIO VCCIO

VCCIO VCCIO VCCIO

VCCIO VCCIO

VCCSA VCCSA VCCSA

VCCSA VCCSA

+VCCIO

AK28 AK30

AL30 AL42 AM28

AM30 AM42

AK23 AK25 G23

G25 G27 G28

J22 J23 J27

K23 K25 K27

K28 K30

AM23

AM22

H21 H20

#543016 PDG2.0 P.750 +1.35V_VDDQC : 1x 10uF

#543016 PDG2.0 P.750 +1.0V_VCCST : 1x 1uF

#543016 PDG2.0 P.750 +1.0V_VCCSFR : 1x 1uF

#543016 PDG2.0 P.750 +1.35V_VCCSFR_OC : 1x 1uF

#543016 PDG2.0 P.750 +1.0V_VCCSTG : 1x 1uF (Placeholder)

+VCC_SA

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

T124 @

T125 @

VSSSA_SENSE <40> VCCSA_SENSE <40>

Reference GND as possible.

1

2

3

+VCCIO

22U_0603_6.3V6M

CC58

1

@

2

4

CC59

1

@

A

@

2

1U_0402_6.3V6K

1

2

CC28

CC27

@

2

#543016 PDG2.0 P.750 +VCCIO : 4x 1uF 0402

PSC Si deBSC Si de

1U_0402_6.3V6K

1

CC33

2

1U_0402_6.3V6K

1

CC34

2

1U_0402_6.3V6K

1

CC35

CC36

2

Secur ity Cla ssifica tion

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Da te

+1.2V_VDDQ_CPU

22U_0603_6.3V6M

CC37

1

2

#543016 PDG2.0 P.750 +1.35V_VDDQ_CPU : 4x 10uF 0402 3x 22uF 0603

C

22U_0603_6.3V6M

CC41

2016/07/ 18 2016/11/10

10U_0603_6.3V6M

CC54

1

CC38

2

Compal Secret Data

10U_0603_6.3V6M

1

CC39

2

10U_0603_6.3V6M

1

CC40

2

Deciphere d Date

10U_0603_6.3V6M

1

CC42

@

2

D

BSC Si dePSC Si de

1U_0402_6.3V6K

1

CC44

CC43

@

2

1U_0402_6.3V6K

1

CC45

CC46

@

2

4

CompalElectronics,Inc.

Title

SKL-U(8/12)Power

Size Document Number R ev

Custom

B5W11M/BLA-E061P

Date : Sheet

E

14 44Monday, July 18, 2016

1.0

of

A

B

C

D

E

1

2

3

4

+1.0VALW_PRIM

RC175 0_0402_5%@

+1.0VALW_PRIM

RC148 0_0603_5%@

+3VALW

RC173 0_0402_5%@

+3VALW_PRIM

RC198 0_0402_5%@

RC154 0_0402_5%@

+3VALW

+1.0VALW_PRIM

1

JPC7

1

JUMP_43X39

@

HSIO Imax : 3.5 A

JPC9

1

JUMP_43X79

@

2

+1.0VALW_MPHYPLL

2

+1.0VALW_MPHYAON

+1.0VALW_APLL

+3VALW_DSW

+3VALW_PRIM

1

2

CC87

CC87 near K17 (<3 mm )

+3VALW_HDA

CC63 near AJ19 ( <10 mm)

+3VALW_SPI

1U_0402_6.3V6K

1

2

CC123 22U_0603_6.3V6M@

1

2

CC63 1U_0402_6.3V6K@

#543016 PDG2.0 P.764

1

RC209 0_0603_5%@

RC149 0_0603_5%@

RC176 0_0603_5%@

RC156 0_0402_5%@

2

1

2

1

2

1

2

+1.0VALW_MPHYGT

1

CC82 22U_0603_6.3V6M

1

CC80 1U_0402_6.3V6K

CC80 nea r N15 (<3m m) CC82 ne ar N15 ( <10mm)

+1.0VALW_AMPHYPLL

CC61 near K15 (<3 mm )

1

CC61 1U_0402_6.3V6K

+1.0VALW_SRAM

CC122 ne ar AF20 ( <10mm)

1

CC122 1U_0402_6.3V6K

+1.0VALW_APLLEBB

CC68 nea r N18 (<3m m)

1

CC68 1U_0402_6.3V6K

CC91

1

2

1U_0402_6.3V6K

@

Near AB19 (<10 mm)

+1.0VALW_PRIM

1

2

CC76 1U_0402_6.3V6K@

near AF18 (< 10 mm)

CC85 1U_0402_6.3V6K

+1.0VALW_MPHYAON

+1.0VALW_MPHYGT

+1.0VALW_AMPHYPLL

+1.0VALW_APLL

+1.0VALW_PRIM

+1.0VALW_SRAM

+1.0VALW_PRIM

+1.0VALW_APLLEBB

2

@

2

@

2

@

2

+3VALW_DSW

+3VALW_HDA

+3VALW_SPI

+3VALW_PRIM

1

+1.0VALW_PRIM

DCPDSW_1P0

UC1O

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

SKL-U_BGA1356

@

CPU POWER 4 OF 4

SKL -U

0. 8 9 A

2. 5 7 A

HSIO

2. 1 A

HSIO

15 OF 20

#543016 PDG2. 0 P.470 VCCRTC does not exceed 3.2 V.

Power Rai l Volta ge

+CHGR TC

BAT54 C(V F)

+RTC VCC

Rev_ 0.5 3

VCCPGPPA VCCPGPPB

VCCPGPPC VCCPGPPD VCCPGPPE

VCCPGPPF VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

#543016 PDG2.0 P.758

+1.0VALW_PRIM

22U_0603_6.3V6M

CC111

1

@

2

3.383V (MA X)

240 mV

3. 143V

Result : Pass

+3VALW_PRIM

22U_0603_6.3V6M

CC112

AK15 AG15

Y16 Y15 T16

AF16 AD15

V19

T1

AA1

AK17

AK19 BB14

BB10

A14

K19

L21

N20

L19

A10

AN11 AN13

22U_0603_6.3V6M

1

@

2

+3VALW_1.8VALW_PGPPA

+3VALW_PGPPB

+3VALW_PGPPC +3VALW_1.8VALW_PGPPD

+3VALW_PGPPE +1.8VALW_PRIM +3VALW_PGPPG

+3VALW_PRIM

+1.0VALW_DTS

+1.8VALW_PRIM

+3VALW_RTC

+RTCVCC

1

2

CC71 .1U_0402_16V7K

CC113

@

PRIMCORE_VID0 PRIMCORE_VID1

+1.8VALW_PRIM

22U_0603_6.3V6M

CC114

1

@

2

+1.0VALW_CLK6_24TBT

+1.0VALW_VCCCLK2

+1.0VALW_APLL

+1.0VALW_CLK4_F100OC

+1.0VALW_CLK5_F24NS

+1.0VALW_CLK6_24TBT

22U_0603_6.3V6M

CC116

1

@

2

RTC Battery

+RTCBA TT

W=20m ils

DC1

1

BAS40-04_SOT23-3

cap place close AK19.

T136 @

T138 @

22U_0603_6.3V6M

CC115

+CHGRTC

2

W=1 0m il

3

No use

SPI Touch

W=20m ils

+RTCVC C

1

2

CC84 .1U_0402_16V7K

CC102 1U_0402_6.3V6K @

CC102 near A G15 (<3 mm)

CC73 1U_0402_6.3V6K @

CC73 near Y1 6 (<10 mm)

CC103 1U_0402_6.3V6K

CC74 1U_0402_6.3V6K @

CC74 near T16 (< 10 mm)

CC83 1U_0402_6.3V6K @

CC67 1U_0402_6.3V6K @

CC67 near V19 (< 3 mm)

+1.0VALW_DTS

CC72 1U_0402_6.3V6K

CC72 near AA1 (< 10 mm)

CC78 .1U_0402_16V7K

CC77 1U_0402_6.3V6K

CC77,CC78 n ear AK17 (< 3 mm)

CC86 1U_0402_6.3V6K @

CC86 near A10 (< 3 mm)

CC75

1U_0402_6.3V6K @

CC124

22U_0603_6.3V6M @

CC125

22U_0603_6.3V6M @

+3VALW_1.8VALW_PGPPA

+3VALW_PGPPB

1

2

+3VALW_PGPPC

1

2

+3VALW_1.8VALW_PGPPD

1

2

+3VALW_PGPPE

1

2

+3VALW_PGPPG

1

2

1

2

+1.0VALW_PRIM

1

2

RC1620_0402_5% @

1

2

+3VALW_RTC

1

2

1

2

+1.0VALW_CLK6_24TBT

1

2

+1.0VALW_VCCCLK2

1

2

1

2

+1.0VALW_CLK4_F100OC

1

2

+1.0VALW_CLK5_F24NS

+3VALW_PRIM

+1.8VALW_PRIM

1

2

1

2

1

2

1

2

+1.8VALW_PRIM

1

2

1

2

1

2

1

2

+1.8VALW_PRIM

1

2

+1.0VALW_PRIM

1

2

+1.0VALW_PRIM

1

2

+1.0VALW_PRIM

1

2

+1.0VALW_PRIM

1

2

+3VALW_PRIM

RC1960_0402_5% ESPI@

RC1970_0402_5% @

+3VALW_PRIM

RC1610_0402_5% @

+3VALW_PRIM

RC1630_0402_5% @

+3VALW_PRIM

RC2060_0402_5% @

RC1720_0402_5% @

+3VALW_PRIM

RC1670_0402_5% @

+3VALW_PRIM

RC1870_0402_5% @

+3VALW_PRIM

RC1710_0402_5% @

RC1690_0402_5% @

RC1640_0603_5% @

RC1900_0603_5% @

RC1520_0603_5% @

1

2

3

4

Secur ity Cla ssifica tion

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/07/ 18 2016/11/10

Compal Secret Data

Deciphere d Date

CompalElectronics,Inc.

Title

SKL-U(9/12)Power

Size Document Number R ev

Custom

B5W11M/BLA-E061P

Date : Sheet

D

Date : Sheet

E

15 44Monday, July 18, 2016

1.0

of

1

SOC_SVID_ALERT#

SOC_SVID_DAT

2

#543016 PDG2. 0 P.273

56_0402_5%

RC180

220_0402_5%

1

A

RC179

2

1

2

+1.0V_VCCST

1

RC181 100_0402_1%

Place the PU

2

resistors clos e to CPU

SOC_SVID_ALERT#_R <40>

SOC_SVID_DAT <40>

B

To VR

#544924 SKL ED S1.2 P .141 VCCOPC 1.0V 3. 2A VCC_ OPC_1P 8 1 .8V 50 mA VCCEO PIO 0. 8V,1.0V 2A

For CPU 2+3e SKU

T132 @

T133 @

T137 @ T139 @

VCCOPC_SENSE

VSSOPC_SENSE

VCCEOPIO_SENSE VSSEOPIO_SENSE

+VCC_CORE

AK33

AK35 AK37 AK38

AK40 AL33 AL37

AL40 AM32 AM33

AM35 AM37 AM38

AK32

AB62

AC63

AE63

AE62

AG62

AL63

AJ62

A30 A34

A39 A44

G30

K32

P62

V62

H63

G61

SKL-U_BGA1356

@

UC1L

CPU POWER 1 OF 4

VCC_A30 VCC_A34

VCC_A39 VCC_A44 VCC_AK33

VCC_AK35 VCC_AK37 VCC_AK38

VCC_AK40 VCC_AL33 VCC_AL37

VCC_AL40 VCC_AM32 VCC_AM33

VCC_AM35 VCC_AM37 VCC_AM38

VCC_G30

RSVD_K32

RSVD_AK32

VCCOPC_AB62 VCCOPC_P62

VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE

VSSOPC_SENSE

VCCEOPIO VCCEOPIO

VCCEOPIO_SENSE VSSEOPIO_SENSE

SKL -U

12 OF 20

C

#544924 S KL EDS1.2 P. 134 VCC U(15W) -dual core GT2 29 A(MAX)

0.55- 1.5 2V

VCC_G32 VCC_G33 VCC_G35

VCC_G37 VCC_G38 VCC_G40

VCC_G42

VCC_K33 VCC_K35 VCC_K37 VCC_K38

VCC_K40 VCC_K42 VCC_K43

VCC_SENSE

VSS_SENSE

VIDALERT#

VIDSOUT

VCCSTG_G20

Rev_ 0.5 3

VCC_J30 VCC_J33

VCC_J37 VCC_J40

VIDSCK

+VCC_CORE

G32 G33 G35

G37 G38 G40

G42 J30 J33

J37 J40 K33 K35 K37 K38

K40 K42 K43

E32

E33

B63 A63

D64

G20

Trace Length < 25 mils

SOC_SVID_ALERT#

SOC_SVID_CLK SOC_SVID_DAT

+1.0V S(SUSP# )

VCCGT_SENSE<40> VSSGT_SENSE<40>

Trace Length < 25 mils

VCCSENSE <40>

VSSSENSE <40>

SOC_SVID_CLK <40>

+1.0VS_VCCSTG

D

#544924 S KL EDS1.2 P. 136 VCCGT U(1 5W)-dual core G T2 31A(MAX)

0.55- 1.5 V

VCCGT_SENSE VSSGT_SENSE

+VCC_GT

AA63 AA64 AA66

AA67 AA69 AA70

AA71 AC64 AC65

AC66 AC67 AC68

AC69 AC70 AC71

A48 A53

A58 A62 A66

J43 J45 J46

J48 J50 J52

J53 J55 J56

J58 J60

K48

K50 K52 K53

K55 K56 K58

K60 L62 L63

L64 L65 L66

L67 L68 L69

L70 L71

M62

N63 N64 N66

N67 N69

J70

J69

UC1M

VCCGT VCCGT

VCCGT VCCGT VCCGT

VCCGT VCCGT

VCCGT_SENSE

VSSGT_SENSE

SKL-U_BGA1356

@

CPU POWER 2 OF 4

SKL -U

13 OF 20

Rev_ 0.5 3

VCCGT VCCGT VCCGT

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT VCCGT VCCGT

VCCGT

VCCGTX_AK42 VCCGTX_AK43

VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48

VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53

VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58

VCCGTX_AK60 VCCGTX_AK70 VCCGTX_AL43

VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53

VCCGTX_AL56 VCCGTX_AL60

VCCGTX_AM48

VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53

VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58

VCCGTX_AU63

VCCGTX_BB57 VCCGTX_BB66

VCCGTX_SENSE VSSGTX_SENSE

N70 N71 R63

R64 R65 R66

R67 R68 R69

R70 R71 T62 U65 U68 U71

W63 W64 W65

W66 W67 W68

W69 W70 W71

Y62

AK42 AK43

AK45 AK46 AK48

AK50 AK52 AK53

AK55 AK56 AK58

AK60 AK70 AL43

AL46 AL50 AL53

AL56 AL60 AM48

AM50 AM52 AM53

AM56 AM58 AU58

AU63 BB57 BB66

VCCGTX_SENSE

AK62

VSSGTX_SENSE

AL61

+VCC_GT

E

For CPU2+3e S KU

T155 @ T219 @

1

2

3

4

Secur ity Cla ssifica tion

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/07/ 18 2016/11/10

Compal Secret Data

Deciphere d Date

CompalElectronics,Inc.

Title

SKL-U(10/12)Power,SVID

Size Document Number R ev

Custom

B5W11M/BLA-E061P

Date : Sheet

D

Date : Sheet

E

of

16 44Monday, July 18, 2016

of

16 44Monday, July 18, 2016

of

16 44Monday, July 18, 2016

3

4

1.0

A

B

C

D

E

1

A5

A67

A70

AA2

AA4

AA65

AA68 AB15

AB16 AB18

AB21

AB8

AD13 AD16

AD19 AD20

AD21 AD62

AD8

AE64

AE65 AE66

AE67

2

3

AE68

AE69

AF1

AF10 AF15

AF17

AF2

AF4

AF63

AG16 AG17

AG18 AG19

AG20 AG21

AG71 AH13

AH6

AH63

AH64 AH67

AJ15 AJ18

AJ20

AJ4

AK11 AK16

AK18 AK21

AK22 AK27

AK63 AK68

AK69

AK8

AL2

AL28

AL32 AL35

AL38

AL4

AL45 AL48

AL52 AL55

AL58 AL64

UC1P

GND 1 OF 3

VSS VSS

SKL-U_BGA1356

@

SKL -U

Re v _0 . 53 Re v _0 . 53

AT63 AT68

AT71

AU10

AU15 AU20

AU32 AU38

AV1

AV68

AV69 AV70 AV71

AW10

AW12 AW14

AW16 AW18

AW21 AW23

AW26 AW28

AW30 AW32

AW34 AW36

AW38 AW41

AW43 AW45

AW47 AW49

AW51 AW53

AW55 AW57

AW6

AW60

AW62 AW64

AW66

AW8

AY66

B10

B14 B18

B22 B30

B34 B39

B44 B48

B53 B58

B62 B66

B71 BA1

BA10 BA14

BA18

BA2

BA23 BA28

BA32 BA36

BA45

F68

16 OF 20

VSS VSS

AL65 AL66

AM13 AM21

AM25 AM27

AM43 AM45

AM46 AM55

AM60 AM61

AM68 AM71

AM8 AN20

AN23 AN28

AN30 AN32

AN33 AN35

AN37 AN38

AN40 AN42

AN58 AN63

AP10 AP18

AP20 AP23

AP28 AP32

AP35 AP38

AP42 AP58

AP63 AP68

AP70 AR11

AR15 AR16

AR20 AR23

AR28 AR35

AR42 AR43

AR45 AR46

AR48 AR5

AR50 AR52

AR53 AR55

AR58 AR63

AR8 AT2

AT20 AT23

AT28 AT35

AT4 AT42

AT56 AT58

UC1Q

GND 2 OF 3

VSS VSS

VSS VSS VSS VSS

VSS VSS

VSS VSS VSS VSS

VSS VSS

VSS

SKL-U_BGA1356

@

SKL -U

17 OF 20

VSS VSS

VSS

BA49 BA53

BA57 BA6

BA62 BA66

BA71 BB18

BB26 BB30

BB34 BB38

BB43 BB55

BB6 BB60

BB64 BB67

BB70 C1

C25 C5

D10 D11

D14 D18

D22 D25

D26 D30

D34 D39

D44 D45

D47 D48

D53 D58

D6 D62

D66 D69

E11 E15

E18 E21

E46 E50

E53 E56

E6 E65

E71 F1

F13 F2

F22 F23

F27 F28

F32 F33

F35 F37

F38 F4

F40 F42

BA41

UC1R

F8

VSS

G10

VSS

G22

VSS

G43

VSS

G45

VSS

G48

VSS

G5

VSS

G52

VSS

G55

VSS

G58

VSS

G6

VSS

G60

VSS

G63

VSS

G66

VSS

H15

VSS

H18

VSS

H71

VSS

J11

VSS

J13

VSS

J25

VSS

J28

VSS

J32

VSS

J35

VSS

J38

VSS

J42

VSS

J8

VSS

K16

VSS

K18

VSS

K22

VSS

K61

VSS

K63

VSS

K64

VSS

K65

VSS

K66

VSS

K67

VSS

K68

VSS

K70

VSS

K71

VSS

L11

VSS

L16

VSS

L17

VSS

SKL-U_BGA1356

@

GND 3 OF 3

SKL -U

18 OF 20

Re v _0 . 53

VSS

VSS VSS

L18

L2 L20

L4 L8

N10 N13

N19 N21

N6 N65

N68 P17

P19 P20

P21 R13

R6 T15

T17 T18

T2 T21

T4 U10

U63 U64

U66 U67

U69 U70

V16 V17

V18 W13

W6 W9

Y17 Y19

Y20 Y21

1

2

3

4

Secu rity Cl assifica tion

2016/0 7/18 2016/1 1/10

Issued Da te

THIS SHEE T OF ENG INEERING DRAW ING I S THE P ROPRIETAR Y PRO PERTY O F CO MPAL ELE CTRONICS, INC. AND CON TAINS CON FIDENTIAL

AND TRA DE SE CRET INF ORMATION. THIS SHEET MAY NO T BE TRA NSFERED FRO M THE CU STODY O F THE COM PETENT DIVI SION OF R& D

DEPARTME NT EXC EPT AS AUTH ORIZED BY COMPAL ELE CTRONICS, INC . NE ITHER TH IS SHEE T NO R THE I NFORMATIO N IT CONTAINS

MAY BE USED BY O R DISCLO SED TO AN Y THIRD P ARTY WI THOUT PRI OR WR ITTEN CONSE NT OF COMP AL EL ECTRONICS, I NC.

A

B

2016/0 7/18 2016/1 1/10

C

Comp al Secre t Data

Decipher ed Date

CompalElectronics,Inc.

Tit le

Size Docu ment N umber R e v

Custom

Da te : Sh eet

D

Da te : Sh eet

SKL-U(11/12)GND

B5W11M/BLA-E061P

o f

17 44Monday, July 18, 2016

o f

17 44Monday, July 18, 2016

o f

17 44Monday, July 18, 2016

E

4

1.0

A

B

C

D

E

1

2

3

Display Port Presence Strap

1 : Disabled; No Physical Display Port

CFG4

at t ached t o E mbedded Di spl ay Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

1

RC18549.9_0402_1%

1

RC1931K_0402_1%

CFG_RCOMP

CFG4

UC1S

CFG[0] CFG[1]

CFG[2] CFG[3] CFG[4]

CFG[5] CFG[6] CFG[7]

CFG[8] CFG[9]

CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18]

CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2

RSVD_AY1

RSVD_D1 RSVD_D3

RSVD_K46 RSVD_K45

RSVD_AL25

RSVD_AL27

RSVD_C71 RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70

RSVD_TP_BA68

RSVD_J71

RSVD_J68

VSS_F65

VSS_G65

RSVD_F61

RSVD_E61

RESERVED SIGNALS-1

AL25

AL27

BA70

BA68

E68 B67

D65 D67 E70

C68 D68 C67

F71 G69

F70 G68 H70 G71 H69 G70

E63 F63

E66

F66

E60

E8

AY2

AY1

D1 D3

K46 K45

C71 B70

F60

A52

J71

J68

F65

G65

F61

E61

SKL-U_BGA1356

@

T213 @

T215 @

T220 @

T222 @

CFG0 CFG1

CFG2 CFG3 CFG4

CFG5 CFG6 CFG7 CFG8 CFG9 CFG10

CFG11 CFG12 CFG13

CFG14 CFG15

CFG16 CFG17

CFG18

CFG19

CFG_RCOMP

XDP_ITP_PMODE

T167@

T168@

T169@

T170@

T171@

T172@

T173@

T174@

T175@

T176@

T177@

T178@

T179@

T180@

T181@

T182@

T183@

T184@

T186@

T188@

T189@

SKL -U

19 OF 20

Rev_ 0.5 3

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

RSVD_D5

RSVD_D4 RSVD_B2 RSVD_C2

RSVD_B3

RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4

RSVD_C4

RSVD_A69 RSVD_B69

RSVD_AY3

RSVD_D71 RSVD_C70

RSVD_C54 RSVD_D54

VSS_AY71

ZVM#

RSVD_TP_AW71 RSVD_TP_AW70

MSM#

PROC_SELECT#

BB68 BB69

AK13 AK12

BB2 BA3

AU5

TP5

AT5

TP6

D5

D4 B2 C2

B3

A3

AW1

E1 E2

BA4 BB4

A4

C4

BB5

TP4

A69 B69

AY3

D71 C70

C54 D54

AY4

TP1

BB3

TP2

AY71

AR56

AW71 AW70

AP56

C64

T156 @

T157 @

T158 @

T159 @

T162 @

T163 @

T199 @

1

RC182 0_0402_5%@

T214 @

T216 @

1

RC183 0_0402_5%@

PM_ZVM#

T225 @

T221 @

T223 @

PM_MSM#

T230 @

SKL_CNL#

#544669 CRB1.1 P.54 #544924 S KL EDS1.2 P. 125 PROC_S ELECT# This pin is for compat i bili ty wi t h f ut ur e plat f or ms. It s houl d be unco nnecte d f or the processor.

1

RC184 100K_0402_5%

2

@

+1.0V_VCCST

2

+1.8VALW_PRIM

2

RC57

@

0_0402_5%

1

CC79 1U_0402_6.3V6K

2

@

CC79 near U 11,U12 (<10 mm)

14MOW52, Con nect U11, U12 to 1.8V fo r Cannonl ake-U PCH compat i bi lit y

For 2+3e So lut i o n

PM_ZV M# Zero Voltage Mode: Control Signal to OPC VR, when low OPC VR output is 0V.

PM_MS M# Minimum Speed Mode: Control signal to VccEOPIO VR (connected only in 2 VR solut i on f or OPC).

AW69 AW68

AU56

AW48

C7

U12 U11 H11

UC1T

RSVD_AW69 RSVD_AW68

RSVD_AU56 RSVD_AW48 RSVD_C7

RSVD_U12 RSVD_U11 RSVD_H11

SKL-U_BGA1356

@

SPA RE

SKL -U

20 OF 20

Rev_ 0.5 3

RSVD_F6 RSVD_E3

RSVD_C11

RSVD_B11 RSVD_A11 RSVD_D12

RSVD_C12 RSVD_F52

F6 E3 C11

B11 A11 D12

C12 F52

1

2

3

4

Secur ity Cla ssifica tion

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/07/ 18 2016/11/10

Compal Secret Data

Deciphere d Date

CompalElectronics,Inc.

Title

SKL-U(12/12)RSVD

Size Document Number R ev

Custom

B5W11M/BLA-E061P

Date : Sheet

D

Date : Sheet

E

of

18 44Monday, July 18, 2016

of

18 44Monday, July 18, 2016

of

18 44Monday, July 18, 2016

4

1.0

A

DDR_A_DQS#[0..7]<8>

DDR_A_D[0..63]<8>

DDR_A_DQS[0..7]<8>

DDR_A_MA[0..16]<8>

DDR_A_BA0<8>

DDR_A_BA1<8>

DDR_A_BG0<8>

DDR_A_BG1<8> DDR_A_ACT#<8>

1

Layo ut Not e: Place near JDIMM1

+1.2V_VDDQ

2

+1.2V_VDDQ

10U_0603_6.3V6M

Layo ut Not e: Plac e near JDIM M1. 257, 259

3

4

DDR_A_ALERT#<8>

DDR_A_PAR<8>

DDR_A_CLK0<8> DDR_A_CLK#0<8>

DDR_A_CLK1<8>

DDR_A_CLK#1<8>

DDR_A_CKE0<8>

DDR_A_CKE1<8> DDR_A_CS#0<8>

DDR_A_CS#1<8>

SOC_SMBDATA_1<9,20> SOC_SMBCLK_1<9,20>

DDR_A_ODT0<8>

DDR_A_ODT1<8>

1U_0402_6.3V6K

1

CD5

CD4

2

10U_0603_6.3V6M

CD11

CD12

CD10

1

2

10U_0603_6.3V6M

1

CD61

2

+3VS

1

RD40

0_0402_5%

@

2

1

RD43

0_0402_5%

@

2

DDR_A_BA0

DDR_A_BA1

DDR_A_BG0

DDR_A_BG1

DDR_A_ACT# DDR_A_ALERT# DDR_A_PAR

DDR_A_CLK0

DDR_A_CLK#0

DDR_A_CLK1 DDR_A_CLK#1

DDR_A_CKE0

DDR_A_CKE1

DDR_A_CS#0

DDR_A_CS#1

SOC_SMBDATA_1 SOC_SMBCLK_1

DDR_A_ODT0 DDR_A_ODT1

Not e : Check voltage tolera nce of VREF_DQ at the DIMM socket

1U_0402_6.3V6K

CD6

10U_0603_6.3V6M

+2.5V

A

1

CD7

2

10U_0603_6.3V6M

CD13

1

2

1U_0402_6.3V6K

1

CD60

2

1

RD41

0_0402_5%

@

2

1

RD44

0_0402_5%

@

2

1

CD8

2

10U_0603_6.3V6M

CD14

1

2

RD42

DDR_A_SA2 DDR_A_SA1

DDR_A_SA0

RD45

1U_0402_6.3V6K

1

CD9

CD57

2

10U_0603_6.3V6M

CD19

CD15

1

2

Layo ut Not e: Place near JDIM M1.2 55

1U_0402_6.3V6K

1

2

CD20

1

2

CD56

Follow MA51

1

+

CD16 330U_D2_2V_Y

@

2

SGA00 009 S00 330U 2V H1.9 9mohm POLY

+3VS

1

CD27

.1U_0402_16V7K

2

B

RD58

240_0402_1%

B

+1.2V_VDDQ

2

1

2

1

+2.5V

RD59

240_0402_1%

+3VS

+1.2V_VDDQ

DDR_A_D4

DDR_A_D0

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D7

DDR_A_D6

DDR_A_D12

DDR_A_D9

DDR_A_D15

DDR_A_D14

DDR_A_D21

DDR_A_D20

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D22

DDR_A_D18

DDR_A_D28

DDR_A_D29

DDR_A_D26

DDR_A_D30

DDR_A_DQS#8 DDR_A_DQS8

DDR_A_CKE0

DDR_A_BG1 DDR_A_BG0

DDR_A_MA12

DDR_A_MA9

DDR_A_MA8 DDR_A_MA6

DDR_A_MA3 DDR_A_MA1

DDR_A_CLK0 DDR_A_CLK#0

DDR_A_PAR

DDR_A_BA1

DDR_A_CS#0

DDR_A_MA14

DDR_A_ODT0 DDR_A_CS#1

DDR_A_ODT1

DDR_A_D33

DDR_A_D36

DDR_A_DQS#4

DDR_A_DQS4

DDR_A_D35

DDR_A_D34

DDR_A_D40

DDR_A_D41

DDR_A_D42

DDR_A_D43

DDR_A_D49

DDR_A_D52

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50

DDR_A_D51

DDR_A_D56

DDR_A_D57

DDR_A_D63

DDR_A_D60

SOC_SMBCLK_1

JDIMM1

1

VSS

3

DQ5

5

VSS

7

DQ1

9

VSS

11

DQS0_C

13

DQS0_T

15

VSS

17

DQ7

19

VSS

21

DQ3

23

VSS

25

DQ13

27

VSS

29

DQ9

31

VSS

33

DM1*/DBI1*

35

VSS

37

DQ15

39

VSS

41

DQ10

43

VSS

45

DQ21

47

VSS

49

DQ17

51

VSS

53

DQS2_C

55

DQS2_T

57

VSS

59

DQ23

61

VSS

63

DQ19

65

VSS

67

DQ29

69

VSS

71

DQ25

73

VSS

75

DM3*/DBI3*

77

VSS

79

DQ30

81

VSS

83

DQ26

85

VSS

87

CB5_NC

89

VSS

91

CB1_NC

93

VSS

95

DQS8_C

97

DQS8_T

99

VSS

101

CB2_NC

103

VSS

105

CB3_NC

107

VSS

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_T

139

CK0_C

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

S0*

151

A14_WE*

153

VDD15

155

ODT0

157

S1*

159

VDD17

161

ODT1

163

VDD19

165

S3*/C1

167

VSS

169

DQ37

171

VSS

173

DQ33

175

VSS

177

DQS4_C

179

DQS4_T

181

VSS

183

DQ38

185

VSS

187

DQ34

189

VSS

191

DQ44

193

VSS

195

DQ40

197

VSS

199

DM5*/DBI5*

201

VSS

203

DQ46

205

VSS

207

DQ42

209

VSS

211

DQ52

213

VSS

215

DQ49

217

VSS

219

DQS6_C

221

DQS6_T

223

VSS

225

DQ55

227

VSS

229

DQ51

231

VSS

233

DQ61

235

VSS

237

DQ56

239

VSS

241

DM7*/DBI7*

243

VSS

245

DQ62

247

VSS

249

DQ58

251

VSS

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

FOX_AS0A827-H2RB-7H

CONN@

DM0*/DBI0*

DQ12

DQS1_C DQS1_T

DQ14

DQ11

DQ20

DQ16

DM2*/DBI2*

DQ22

DQ18

DQ28

DQ24

DQS3_C

DQS3_T

DQ31

DQ27

CB4_NC

CB0_NC

DM8*/DBI8*

CB6_NC

CB7_NC

RESET*

CKE1 VDD2

ALERT*

VDD4

VDD6

VDD8

EVENT*

VDD10

CK1_T

CK1_C VDD12

A10_AP

VDD14

A16_RAS*

VDD16

A15_CAS*

VDD18

S2*/C0

VREFCA

DQ36

DQ32

DM4*/DBI4*

DQ39

DQ35

DQ45

DQ41

DQS5_C

DQS5_T

DQ47

DQ43

DQ53

DQ48

DM6*/DBI6*

DQ54

DQ50

DQ60

DQ57

DQS7_C DQS7_T

DQ63

DQ59

ACT*

C

+1.2V_VDDQ

2

VSS DQ4

VSS

DQ0 VSS

VSS DQ6

VSS

DQ2 VSS

VSS DQ8

VSS

A11

A7

A5

A4

A2

A0

BA0

A13

SA2

VSS

SDA SA0 VTT

SA1

GND GND

DDR_A_D1

4

6

DDR_A_D5

8 10

12

14

DDR_A_D3

16

18

DDR_A_D2

20 22

DDR_A_D8

24

26

DDR_A_D13

28

30

DDR_A_DQS#1

32

DDR_A_DQS1

34

36

DDR_A_D11

38 40

DDR_A_D10

42

44

DDR_A_D17

46

48

DDR_A_D19

50 52 54

56

DDR_A_D16

58

60

DDR_A_D23

62 64

DDR_A_D24

66

68

DDR_A_D25

70

72

DDR_A_DQS#3

74

DDR_A_DQS3

76

78

DDR_A_D27

80

82

DDR_A_D31

84 86

88

90

92 94

96

98 100

102

104 106

DDR_DRAMRST#

108

DDR_A_CKE1

110 112

DDR_A_ACT#

114

DDR_A_ALERT#

116 118

DDR_A_MA11

120

DDR_A_MA7

122 124

DDR_A_MA5

126

DDR_A_MA4

128 130

DDR_A_MA2

132

DDR_A_EVENT#

134 136

DDR_A_CLK1

138

DDR_A_CLK#1

140 142

DDR_A_MA0

144

DDR_A_MA10

146 148

DDR_A_BA0

150

DDR_A_MA16

152 154

DDR_A_MA15

156

DDR_A_MA13

158 160

162

164

DDR_A_SA2

166

168

DDR_A_D32

170 172

DDR_A_D37

174 176 178

180

DDR_A_D38

182 184

DDR_A_D39

186

188

DDR_A_D44

190

192

DDR_A_D45

194 196

DDR_A_DQS#5

198

DDR_A_DQS5

200 202

DDR_A_D46

204

206

DDR_A_D47

208

210

DDR_A_D53

212 214

DDR_A_D48

216 218 220

222

DDR_A_D55

224 226

DDR_A_D54

228 230

DDR_A_D58

232

234

DDR_A_D59

236 238

DDR_A_DQS#7

240

DDR_A_DQS7

242 244

DDR_A_D61

246 248

DDR_A_D62

250

252

SOC_SMBDATA_1

254

DDR_A_SA0

256 258

DDR_A_SA1

260

261 262

C

+1.2V_VDDQ

1

RD1 470_0402_5%

2

+1.2V_VDDQ

2

1

10m i ls

RD60

240_0402_1%

+0.6V_DDRA_VREFCA

.1U_0402_16V7K

DDR_DRAMRST# <8,20>

1

CD1

2

+1.2V_VDDQ

Place near to SO-DIMM connector.

Layo ut Not e: Place near JDIM M1.2 58

+0.6VS_VTT

Security Classif ication

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/07/18 2016/11/10

+0.6V_A_VREFCA

1

RD9

1K_0402_1%

RD10

2

2_0402_1%

1

RD11 1K_0402_1%

2

+0.6VS_VTT

10U_0603_6.3V6M

1

CD58

2

Compal S ecret Data

Deciphered Date

D

2

1

2

D

1

2

1

RD12

2

1U_0402_6.3V6K

CD24

CD21

0.022U_0402_16V7K

24.9_0402_1%

1U_0402_6.3V6K

1

CD25

2

E

Reverse Type

2-3A to 1 DIMMs/channel

Interleaved Memory

CompalElectronics,Inc.

Titl e

Size Docum ent N umb er R e v

Custom

Da te : She et

DDR4_DIMMA

B5W11M/BLA-E061P

E

1

2

3

4

1.0

o f

19 44Monday, July 18, 2016

o f

19 44Monday, July 18, 2016

o f

19 44Monday, July 18, 2016

1

Layo ut Not e: Place near JDIMM2

+1.2V_VDDQ

1U_0402_6.3V6K

2

3

4

1

CD32

2

+1.2V_VDDQ

10U_0603_6.3V6M

CD38

1

2

Layo ut Not e: Plac e near JDIM M1. 257, 259

1

2

+3VS

1

2

1

2

A

DDR_B_DQS#[0..7]<8>

DDR_B_D[0..63]<8>

DDR_B_DQS[0..7]<8>

DDR_B_MA[0..16]<8>

DDR_B_BA0<8>

DDR_B_BA1<8>

DDR_B_BG0<8>

DDR_B_BG1<8> DDR_B_ACT#<8> DDR_B_ALERT#<8>

DDR_B_PAR<8>

DDR_B_CLK0<8>

DDR_B_CLK#0<8> DDR_B_CLK1<8> DDR_B_CLK#1<8>

DDR_B_CKE0<8>

DDR_B_CKE1<8> DDR_B_CS#0<8>

DDR_B_CS#1<8>

SOC_SMBDATA_1<9,19>

SOC_SMBCLK_1<9,19>

DDR_B_ODT0<8> DDR_B_ODT1<8>

1U_0402_6.3V6K

1

CD33

2

10U_0603_6.3V6M

CD39

1

2

+2.5V

10U_0603_6.3V6M

1

CD68

2

1

RD51

0_0402_5%

@

2

RD54

0_0402_5%

1

@

2

DDR_B_BA0

DDR_B_BA1

DDR_B_BG0

DDR_B_BG1 DDR_B_ACT#

DDR_B_ALERT#

DDR_B_PAR

DDR_B_CLK0 DDR_B_CLK#0

DDR_B_CLK1 DDR_B_CLK#1

DDR_B_CKE0

DDR_B_CKE1

DDR_B_CS#0

DDR_B_CS#1

SOC_SMBDATA_1 SOC_SMBCLK_1

DDR_B_ODT0 DDR_B_ODT1

1U_0402_6.3V6K

1

CD34

CD40

A

1

2

1

2

1

2

RD53

0_0402_5%

@

DDR_B_SA2 DDR_B_SA1 DDR_B_SA0

RD56

0_0402_5%

@

1

CD35

CD36

2

10U_0603_6.3V6M

CD41

CD42

1

2

Layo ut Not e: Place near JDIM M2.2 55

1

2

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

CD67

RD52

0_0402_5%

@

RD55

0_0402_5%

@

1U_0402_6.3V6K

1

CD37

2

10U_0603_6.3V6M

CD43

1

2

1U_0402_6.3V6K

1

CD69

CD70

2

10U_0603_6.3V6M

CD45

CD44

1

2

+3VS

1

2

CD55

2.2U_0402_6.3V6M

B

RD61

240_0402_1%

B

+1.2V_VDDQ

2

1

2

1

+2.5V

RD62

240_0402_1%

+3VS

+1.2V_VDDQ

DDR_B_D15

DDR_B_D14

DDR_B_DQS#1

DDR_B_DQS1

DDR_B_D8

DDR_B_D12

DDR_B_D4

DDR_B_D0

DDR_B_D6

DDR_B_D7

DDR_B_D20

DDR_B_D21

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D22

DDR_B_D23

DDR_B_D29

DDR_B_D28

DDR_B_D30

DDR_B_D31

DDR_B_DQS#8 DDR_B_DQS8

DDR_B_CKE0

DDR_B_BG1 DDR_B_BG0

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8

DDR_B_MA6

DDR_B_MA3 DDR_B_MA1

DDR_B_CLK0

DDR_B_CLK#0

DDR_B_PAR

DDR_B_BA1

DDR_B_CS#0

DDR_B_MA14

DDR_B_ODT0 DDR_B_CS#1

DDR_B_ODT1

DDR_B_D33

DDR_B_D32

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D35

DDR_B_D34

DDR_B_D40

DDR_B_D41

DDR_B_D43

DDR_B_D46

DDR_B_D48

DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50

DDR_B_D51

DDR_B_D56

DDR_B_D61

DDR_B_D59

DDR_B_D58

SOC_SMBCLK_1

JDIMM2

1

VSS

3

DQ5

5

VSS

7

DQ1

9

VSS

11

DQS0_C

13

DQS0_T

15

VSS

17

DQ7

19

VSS

21

DQ3

23

VSS

25

DQ13

27

VSS

29

DQ9

31

VSS

33

DM1*/DBI1*

35

VSS

37

DQ15

39

VSS

41

DQ10

43

VSS

45

DQ21

47

VSS

49

DQ17

51

VSS

53

DQS2_C

55

DQS2_T

57

VSS

59

DQ23

61

VSS

63

DQ19

65

VSS

67

DQ29

69

VSS

71

DQ25

73

VSS

75

DM3*/DBI3*

77

VSS

79

DQ30

81

VSS

83

DQ26

85

VSS

87

CB5_NC

89

VSS

91

CB1_NC

93

VSS

95

DQS8_C

97

DQS8_T

99

VSS

101

CB2_NC

103

VSS

105

CB3_NC

107

VSS

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_T

139

CK0_C

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

S0*

151

A14_WE*

153

VDD15

155

ODT0

157

S1*

159

VDD17

161

ODT1

163

VDD19

165

S3*/C1

167

VSS

169

DQ37

171

VSS

173

DQ33

175

VSS

177

DQS4_C

179

DQS4_T

181

VSS

183

DQ38

185

VSS

187

DQ34

189

VSS

191

DQ44

193

VSS

195

DQ40

197

VSS

199

DM5*/DBI5*

201

VSS

203

DQ46

205

VSS

207

DQ42

209

VSS

211

DQ52

213

VSS

215

DQ49

217

VSS

219

DQS6_C

221

DQS6_T

223

VSS

225

DQ55

227

VSS

229

DQ51

231

VSS

233

DQ61

235

VSS

237

DQ56

239

VSS

241

DM7*/DBI7*

243

VSS

245

DQ62

247

VSS

249

DQ58

251

VSS

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

FOX_AS0A827-H2SB-7H

CONN@

DM0*/DBI0*

DQ12

DQS1_C

DQS1_T

DQ14

DQ11

DQ20

DQ16

DM2*/DBI2*

DQ22

DQ18

DQ28

DQ24

DQS3_C

DQS3_T

DQ31

DQ27

CB4_NC

CB0_NC

DM8*/DBI8*

CB6_NC

CB7_NC

RESET*

CKE1

VDD2

ALERT*

VDD4

VDD6

VDD8

EVENT*

VDD10

CK1_T CK1_C

VDD12

A10_AP

VDD14

A16_RAS*

VDD16

A15_CAS*

VDD18

S2*/C0

VREFCA

DQ36

DQ32

DM4*/DBI4*

DQ39

DQ35

DQ45

DQ41

DQS5_C DQS5_T

DQ47

DQ43

DQ53

DQ48

DM6*/DBI6*

DQ54

DQ50

DQ60

DQ57

DQS7_C

DQS7_T

DQ63

DQ59

ACT*

C

+1.2V_VDDQ

2

VSS

DQ4

VSS DQ0

VSS

DQ6

VSS DQ2

VSS

DQ8

VSS

A11

A7

A5 A4

A2

A0

BA0

A13

SA2

VSS

VSS SDA

SA0 VTT SA1

GND GND

DDR_B_D11

4

6

DDR_B_D10

8

10

12 14

DDR_B_D13

16

18

DDR_B_D9

20

22

DDR_B_D5

24 26

DDR_B_D1

28

30

DDR_B_DQS#0

32

DDR_B_DQS0

34

36

DDR_B_D3

38

40

DDR_B_D2

42 44

DDR_B_D16

46

48

DDR_B_D17

50

52

54 56

DDR_B_D18

58

60

DDR_B_D19

62

64

DDR_B_D24

66 68

DDR_B_D25

70

72

DDR_B_DQS#3

74

DDR_B_DQS3

76 78

DDR_B_D26

80

82

DDR_B_D27

84

86

88 90

92

94 96 98

100

102 104

106

DDR_DRAMRST#

108

DDR_B_CKE1

110

112

DDR_B_ACT#

114

DDR_B_ALERT#

116

118

DDR_B_MA11

120

DDR_B_MA7

122

124

DDR_B_MA5

126

DDR_B_MA4

128

130

DDR_B_MA2

132

DDR_B_EVENT#

134

136

DDR_B_CLK1

138

DDR_B_CLK#1

140

142

DDR_B_MA0

144

DDR_B_MA10

146

148

DDR_B_BA0

150

DDR_B_MA16

152

154

DDR_B_MA15

156

DDR_B_MA13

158

160

162 164

DDR_B_SA2

166

168

DDR_B_D36

170

172

DDR_B_D37

174 176

178

180

DDR_B_D38

182

184

DDR_B_D39

186 188

DDR_B_D44

190

192

DDR_B_D45

194

196

DDR_B_DQS#5

198

DDR_B_DQS5

200

202

DDR_B_D47

204 206

DDR_B_D42

208 210

DDR_B_D52

212 214

DDR_B_D53

216

218 220 222

DDR_B_D55

224 226

DDR_B_D54

228

230

DDR_B_D60

232 234

DDR_B_D57

236 238

DDR_B_DQS#7

240

DDR_B_DQS7

242 244

DDR_B_D62

246

248

DDR_B_D63

250

252

SOC_SMBDATA_1

254

DDR_B_SA0

256 258

DDR_B_SA1

260

261 262

C

+1.2V_VDDQ

2

1

10m i ls

+0.6VS_VTT

Security Classif ication

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_DRAMRST# <8,19>

1

CD30 .1U_0402_16V7K

@ESD@

2

RD63

240_0402_1%

CD65

+1.2V_VDDQ

1

2

+0.6V_DDRB_VREFCA

.1U_0402_16V7K

Place near to SO-DIMM connector.

Layo ut Not e: Place near JDIM M1.2 58

1

2

2016/07/18 2016/11/10

1

RD46 1K_0402_1%

RD49

2

2_0402_1%

1

RD47 1K_0402_1%

2

+0.6VS_VTT

1U_0402_6.3V6K

10U_0603_6.3V6M

1

CD62

CD64

2

Compal S ecret Data

D

+0.6V_B_VREFCA

2

1

CD66

2

1

RD50

24.9_0402_1%

2

1U_0402_6.3V6K

1

CD63

2

Deciphered Date

D

0.022U_0402_16V7K

E

Standard Type

2-3A to 1 DIMMs/channel

Interleaved Memory

CompalElectronics,Inc.

Titl e

Size Docum ent N umb er R e v

Custom

Da te : She et

DDR4_DIMMB

B5W11M/BLA-E061P

E

20 44Monday, July 18, 2016

1

2

3

4

1.0

o f

A

B

C

D

E

+3VS

CX1

1U_0402_6.3V6K

1

2

SOC_ENVDD<7>

EDP _TX P0< 7>

EDP _TX N0<7 >

EDP _TX P1< 7>

EDP _TX N1<7 >

EDP _A UXP< 7> EDP _A UXN<7 >

+3VS

LCD POWER CIRCUIT

UX1

5

IN

4

EN

SY6288C20AAC_SOT23-5

1

RX9

100K_0402_5%

@

2

1

2

CX8 .1U_0402_16V7K

1

2

CX9 .1U_0402_16V7K

1

2

CX10 .1 U_0402_16V7K

1

2

CX11 .1 U_0402_16V7K

1

2

CX14 .1 U_0402_16V7K

1

2

CX15 .1 U_0402_16V7K

1

2

1

2

RX3100K_0402_5% @

RX4100K_0402_5% @

OUT

GND

OC

1

2

3

EDP_AUXN_C EDP_AUXP_C

EDP_TXP0_C EDP_TXN0_C EDP_TXP1_C

EDP_TXN1_C

EDP_AUXP_C EDP_AUXN_C

W=60mils

+LCDVDD

1

2

CX3

4.7U_0603_6.3V6K

1

CX4 .1U_0402_16V7K

2

@

SOC_BKL_PWM<7>

BKOFF#<29>

+19VB

W=60mils W=60mils

SM0 1000EJ0 0 300 0ma 22 0oh m@ 100 mh z DCR 0.04

SOC_BKL_PWM

CPU _ED P_ HPD<7>

HCB2012KF-221T30_0805

1

EMI@

RX1 100K_0402_5%@

CX12 220P_0402_50V7K

BKOFF#

CX13 220P_0402_50V7K

RX2 10K_0402_5%@

Touch Screen

+5VS

+3VS

1

RX7 0_0603_5%@

1

RX8 0_0603_5%@

3

USB20_N7<13>

USB20_P7<13>

Camera

USB20_N7

USB20_P7

RX10

RX11

1

@EMI@

2

0_0402_5%

2

0_0402_5%

2

+TS_PWR

USB20_N7_CAMERA

USB20_P7_CAMERA

LX1

2

68P_0402_50V8J

1

2

1

2

1

RX5 0_0402_5%

1

@

RX6 100K_0402_5%

2

+INVPWR_B+

CX2

@EMI@

2

@EMI@

2

1

2

EDP_HPD

1000P_0402_50V7K

1

2

CX5

@EMI@

Touch Screen

USB20_P6<13> USB20_N6<13> I2C_0_SCL<12>

I2C_0_SDA<12>

I2C_TS_RST#<29> I2C_TS_INT#<7>

+INVPWR_B+

TS_EN<12,29 >

For Camera

+LCDVDD

+TS_PWR

+3VS

Place closed to JEDP1

+3VS

1

CX6 .1U_0402_16V7K

2

W=60mils

SOC_BKL_PWM

BKOFF# EDP_HPD

EDP_AUXN_C EDP_AUXP_C

EDP_TXP0_C EDP_TXN0_C

EDP_TXP1_C EDP_TXN1_C

TS_EN

USB20_P6 USB20_N6 I2C_0_SCL

I2C_0_SDA I2C_TS_RST# I2C_TS_INT#

USB20_P7_CAMERA USB20_N7_CAMERA

+LCDVDD

1

CX7 .1U_0402_16V7K

2

@

JEDP1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

STARC_107K40-000001-G2

CONN@

SP01000XE00

1

41

G1

42

G2

43

G3

44

G4

45

G5

46

G6

2

3

4

Secu rity Cl assifica tion

2016/0 7/18 2016/1 1/10

Issued Da te

THIS SHEE T OF ENG INEERING DRAW ING I S THE P ROPRIETAR Y PRO PERTY O F CO MPAL ELE CTRONICS, INC. AND CON TAINS CON FIDENTIAL

AND TRA DE SE CRET INF ORMATION. THIS SHEET MAY NO T BE TRA NSFERED FRO M THE CU STODY O F THE COM PETENT DIVI SION OF R& D

DEPARTME NT EXC EPT AS AUTH ORIZED BY COMPAL ELE CTRONICS, INC . NE ITHER TH IS SHEE T NO R THE I NFORMATIO N IT CONTAINS

MAY BE USED BY O R DISCLO SED TO AN Y THIRD P ARTY WI THOUT PRI OR WR ITTEN CONSE NT OF COMP AL EL ECTRONICS, I NC.

A

B

2016/0 7/18 2016/1 1/10

C

Comp al Secre t Data

Decipher ed Date

Compal Electronics, Inc.

Tit le

Size Docu ment N umber R e v

Custom

Da te : Sh eet

D

Da te : Sh eet

Compal Electronics, Inc.

eDP Connector

B5W11 M/B LA-E061P

E

o f

21 44Monday, July 18, 2016

o f

21 44Monday, July 18, 2016

o f

21 44Monday, July 18, 2016

4

1.0

A

B

C

D

E

@EMI@

1

@EMI@

1

@EMI@

1

@EMI@

1

@EMI@

1

@EMI@

1

@EMI@

1

@EMI@

1

HDMI_SDATA HDMI_SCLK

2

0_0402_5%

2

0_0402_5%

2

0_0402_5%

2

0_0402_5%

2

0_0402_5%

2

0_0402_5%

2

0_0402_5%

2

0_0402_5%

HDMI_HPD

HDMI_R_CK-

HDMI_R_CK+

HDMI_R_D0-

HDMI_R_D0+

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D2-

HDMI_R_D2+

RY1

RY2

RY3

RY4

RY5

RY7

RY8

RY10

2

3

1

HDMI_R_CK-

HDMI_R_CK+

HDMI_R_D0-

HDMI_R_D0+

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D2-

HDMI_R_D2+

HDMI connector

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Utility

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

2 1

GND

D2-

GND

D2_shield

GND

D2+

GND

YUQIU_H050FD019M190BA

CONN@

DC232004800

1

2

3

20

21 22

23

+HDMI_5V_OUT

YSLC05CH_SOT23-3

HDMI_C_CLK-

HDMI_C_CLK+

HDMI_C_TX0-

HDMI_C_TX0+

HDMI_C_TX1-

HDMI_C_TX1+

HDMI_C_TX2-

HDMI_C_TX2+

DY1

@ESD@

W=4 0mi ls

+5VS

UY1

1

2

3

1

AP2330W-7_SC59-3

OUT

IN

GND

3

2

+HDMI_5V_OUT

1

2

CY9 .1U_0402_16V7K

SOC_DP2_HPD<7>

RPY1

HDMI_SDATA HDMI_SCLK

HDMI_SDATA

470_8P4R_5%

1

2

3

4

1

2 3

4

RPY2 470_8P4R_5%

+3VS

8

7

6

5

8

7 6

5

HDMI_GND

6

D

2

G

QY1A

2N7002KDW_SOT363-6

S

1

2

SOC_DP2_N1<7>

SOC_DP2_P1<7>

SOC_DP2_P0<7> SOC_DP2_N0<7>

SOC_DP2_P2<7> SOC_DP2_N2<7>

SOC_DP2_N3<7> SOC_DP2_P3<7>

RY6

1M_0402_5%

SOC_DP2_CTRL_DATA<7>

SOC_DP2_CTRL_CLK<7>

CY4 .1U_0402_16V7K

CY3 .1U_0402_16V7K

CY1 .1U_0402_16V7K

CY2 .1U_0402_16V7K

CY5 .1U_0402_16V7K

CY6 .1U_0402_16V7K

CY8 .1U_0402_16V7K

CY7 .1U_0402_16V7K

+3VS

1

2

4

+HDMI_5V_OUT

1

2

1

2

1

2

1

2

1

2

1

2

1

2

+3VS

G

5

S

3

D

QY1B

2N7002KDW_SOT363-6

1

2

3

+3VS

4

DMN66D0LDW-7_SOT363-6

5

G

3

4

S

D

QY2A

DMN66D0LDW-7_SOT363-6

HDMI_C_TX1HDMI_C_TX1+

HDMI_C_TX2+

HDMI_C_TX2-

HDMI_C_TX0+ HDMI_C_TX0-

HDMI_C_CLK-

HDMI_C_CLK+

HDMI_HPD

1

RY9

100K_0402_5%

2

RPY3

8

7

SOC_DP2_CTRL_DATA

6

SOC_DP2_CTRL_CLK

5

2.2K_0804_8P4R_5%

+3VS

2

G

6

1

S

D

QY2B

HDMI_SCLK

Intel spec Ron/Cout : 3ohm/10pF. SB000016K00, S TR PJT138KA 2N SOT363-6

4

Secu rity Cl assifica tion

2016/0 7/18 2016/1 1/10

Issued Da te

THIS SHEE T OF ENG INEERING DRAW ING I S THE P ROPRIETAR Y PRO PERTY O F CO MPAL ELE CTRONICS, INC. AND CON TAINS CON FIDENTIAL

AND TRA DE SE CRET INF ORMATION. THIS SHEET MAY NO T BE TRA NSFERED FRO M THE CU STODY O F THE COM PETENT DIVI SION OF R& D

DEPARTME NT EXC EPT AS AUTH ORIZED BY COMPAL ELE CTRONICS, INC . NE ITHER TH IS SHEE T NO R THE I NFORMATIO N IT CONTAINS

MAY BE USED BY O R DISCLO SED TO AN Y THIRD P ARTY WI THOUT PRI OR WR ITTEN CONSE NT OF COMP AL EL ECTRONICS, I NC.

A

B

2016/0 7/18 2016/1 1/10

C

Comp al Secre t Data

Decipher ed Date

Compal Electronics, Inc.

Tit le

Size Docu ment N umber R e v

Custom

Da te : Sh eet

D

Da te : Sh eet

Compal Electronics, Inc.

HDMI CONN.

B5W11 M/B LA-E061P

E

o f

22 44Monday, July 18, 2016

o f

22 44Monday, July 18, 2016

o f

22 44Monday, July 18, 2016

4

1.0

A

B

C

D

E

1

2

3

4

+3VALW

1

RL1

Change t o R-short a t PVT if t est ok.

UL1

@

5

IN

4

EN

SY6288C20AAC_SOT23-5

LAN_PWR_EN

CL1

1U_0402_6.3V6K

2

1

+3V_LAN Risi ng t i me r equest: 0. 5~ 100 mS

SA0 00 02 8Y 10 High act i v e. EN t hreshold vol tage :1 .2~2.0V Curre nt l imit thr eshold : 1.5~2. 8A Output turn-on risi ng t i me: 1.3 ~2. 7 ms

PU to +3VS at PCH side

CLKREQ_PCIE#1<11>

PCIE_CTX_C_DRX_P5<13> PCIE_CTX_C_DRX_N5<13>

CLK_PCIE_P1<11>

CLK_PCIE_N1<11>

A

LAN_TERMAL

1

CL20

0.1U_0402_16V7K

2

LAN_MIDI0+ LAN_MIDI0-

LAN_MIDI1+ LAN_MIDI1-

LAN_MIDI2+

LAN_MIDI2-

LAN_MIDI3+ LAN_MIDI3-

Place close to TCT pin

+3V_LAN

2

0_0805_5%@

1

OUT

2

GND

3

OC

LAN_PWR_EN <29>

UL2

RTL8111GS-CG_QFN32_4X4

8111GUS@ SA00006M L00

TL1

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+

6

TD2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

GST5009-E

SP0500 06B10

H : 4mm

MCT1 MX1+

MX1-

MCT2 MX2+

MX2-

MCT3 MX3+

MX3-

MCT4 MX4+

MX4-

60m il60m il

LAN_MIDI0+

LAN_MIDI0+LAN_VDD LAN_MIDI1+

LAN_MIDI1LAN_MIDI2+ LAN_MIDI2-

+LAN_VDD LAN_MIDI3+ LAN_MIDI3-

+3V_LAN

24 23

22

21 20

19

18 17

16

15 14

13

Close to U20 Pin 23

CL2

8111GUS@

4.7U_0603_6.3V6K

UL2

1

MDIP0

2

MDIN0

3

AVDD10

4

MDIP1

5

MDIN1

6

MDIP2

7

MDIN2

8

AVDD10

9

MDIP3

10

MDIN3

11

AVDD33

12

CLKREQB

13

HSIP

14

HSIN

15

REFCLK_P

16

REFCLK_N

S IC RTL8111H-CG QFN 32P E-LAN CTRL

SA0 00080 P00

Use 8111GS symbol

8

7

6

5

RPL1 75_0804_8P4R_1%

1

2

3

4

RJ45_GND

B

+3V_LAN

1

2

8111H@

RJ45_MIDI0+ RJ45_MIDI0-

RJ45_MIDI1+

RJ45_MIDI1-

RJ45_MIDI2+ RJ45_MIDI2-

RJ45_MIDI3+ RJ45_MIDI3-

2

CL3

8111GUS@

0.1U_0402_16V7K

1

PERSTB

ISOLATEB

LANWAKEB

DVDD10

VDDREG

REGOUT

LED1/GPIO

CKXTAL1 CKXTAL2

AVDD10

AVDD33

HSOP

HSON

LED2

LED0

RSET

GND

( Should be place within 200 mils ) Close to Pin 24

PCIE_CRX_C_DTX_P5

17

PCIE_CRX_C_DTX_N5

18 19 20

21 22 23

24 25 26

27 28 29

30 31 32

33

PLT_RST_BUF#

ISOLATEB

LAN_PME#

+LAN_VDD +3V_LAN

+REGOUT

LAN_LED2

GPO

LAN_LED0

XTLO XTLI

+LAN_VDD LAN_RST

+3V_LAN

RJ45_MIDI0+

RJ45_MIDI0-

RJ45_MIDI1+

RJ45_MIDI2+

RJ45_MIDI2-

RJ45_MIDI1-

RJ45_MIDI3+

RJ45_MIDI3-

Secur ity Cla ssifica tion

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.1uF close to Pi n 3,8,22,30

1

IDC=1200 mA

8111GUS@

1

2

1

2

1

LL1

CL15.1U_0402_16V7K

CL16.1U_0402_16V7K

2

0_0805_5%@

2

1

2

PCIE_CRX_DTX_P5 <13>

PCIE_CRX_DTX_N5 <13>

PLT_RST_BUF# <11,24>

EC_PME# <29>

0.1U_0402_16V7K

4.7U_0603_6.3V6K

CL5

CL4

1

8111GUS@

2

GPO

W=6 0m ils W=6 0m ils

+REGOUT

RL13

2.2UH +-5% NLC252018T-2R2J-N

0.1U_0402_16V7K CL21

1

8111H@

2

close to Pin 17, 18

2

RL2 0_0402_5%@

T7 @

T8 @

RL3

1

2

2.49K_0402_1%

1uF reserved for Pin 22

CL7

CL6

1U_0402_6.3V6K

1

2

@

1

2

+3V_LAN

1

RL4 10K_0402_5%

@

2

RL5 0_0402_5%@

0.1U_0402_16V7K

CL8

LAN Connector

JRJ45

1

PR1+

2

PR1-

3

PR2+

4

PR3+

5

PR3-

6

PR2-

Issued Da te

7

PR4+

8

PR4-

SANTA_130452-W

CONN@

DC23400AX00

C

2016/07/ 18 2014/10/28

9

GND

10

GND

40m il

RJ45_GND

40m il

@EMI@

JUMP_43X118

JPL1

1

CL19 10P_0402_50V8J

MESC5V02BD03_SOT23-3

Compal Secret Data

Deciphere d Date

DL1

ESD@

2

3

1

D

+LAN_VDD

0.1U_0402_16V7K

CL9

0.1U_0402_16V7K

1

2

CL10

1

2

1

LANGND

1

JPL2

@EMI@

B88069X9231T203_4P5X3P2-2

2

0.1uF close to Pin 11,32

0.1U_0402_16V7K

+3V_LAN

1

RL12

10K_0402_5%

2

LAN_PME#

LAN_GPO <29>

Title

Size Document Number R ev

Custom

Date : Sheet

CL11

4.7U_0603_6.3V6K

1

@

2

XTLI

1

CL17 10P_0402_50V8J

2

Consider VCC33 may be connected to Main Power or chip set/bios's G PO, the pull-low resistor RL7 can be NC on ly when Main Power or chipset /bios's GPO c an ensure to drive the ISOLATEB pin t o a voltage level < 0.8V at the system stat e S3~S5.

Compal Electronics, Inc.

LAN_RTL8111H

B5W11 M/B LA-E061P

CL12

4.7U_0603_6.3V6K

1

@

2

SJ10000E800

YL1 25MHZ_10PF_7V25000014

1

+3VS

E

CL13

0.1U_0402_16V7K

GND

2

RL6 1K_0402_5%

1

RL7 15K_0402_5%

2

W=6 0m ils

+3V_LAN

CL14

0.1U_0402_16V7K

1

2

GND

4

12P_0402_50V8J

ISOLATEB

23 44Monday, July 18, 2016

1

2

3

XTLO

3

1

CL18

2

3

4

1.0

of

A

Wireless LAN

B

C

D

E

1

60 m il

+3VS

1

RM1 0_0805_5 %

NBYOC@

+3VS_WLAN

2

1

CM1

4.7U_0603_6.3V6K

2

1

@

CM2

2

.1U_0402_16V7K

1

CM3

.1U_0402_16V7K

2

1U_0402_6.3V6K

+3VALW

CM4

UM1

5

1

@

2

WLAN_ON<29>

IN

4

EN

SY6288C20AAC_SOT23-5

BYOC@

OUT

GND

1

2

3

OC

+3VS_WLAN

W=6 0mi ls

1

NGFF WL+BT (KEY E)

LED1#

LED2#

GND1

+3VS_WLAN

2 4

6 8

10 12

14 16

18 20

UART_2_CRXD_DTXD

22

PH +3VS at SOC side, for win7 USB3 debug

UART_2_CTXD_DRXD

24

26 28

E51TXD_P80DATA_R

30

E51RXD_P80CLK_R

32

34 36

38 40

SUSCLK_R

42

WL_RST#_R

44

BT_ON

46

WL_OFF#

48

50 52

54

P80CLK and BT_ON enable seperate.

56

58 60

62 64

66

68

RM2 0_0402_5%@

RM7 0_0402_5%@

T205 @

RM4 0_0402_5%@

UART_2_CRXD_DTXD <12>

UART_2_CTXD_DRXD <12>

1

2

1

2

1

2

1

RM3 100K_0402_5%

2

E51TXD_P80DATA <29>

E51RXD_P80CLK <29 >

PLT_RST_BUF# <11,23>

BT_ON <29>

WL_OFF# <29>

2

3

2

USB20_P5<13>

For BT

PCIE_CTX_C_DRX_P6<13>

PCIE_CTX_C_DRX_N6<13>

PCIE_CRX_DTX_P6<13> PCIE_CRX_DTX_N6<13>

CLK_PCIE_P2<11>

CLK_PCIE_N2<11>

CLKREQ_PCIE#2<11>

3

WLAN_PME#<29>

+3VS_WLAN

USB20_N5<13>

RM6

1

2

10K_0402_5%

USB20_P5 USB20_N5

PCIE_CTX_C_DRX_P6 PCIE_CTX_C_DRX_N6

PCIE_CRX_DTX_P6

PCIE_CRX_DTX_N6

CLK_PCIE_P2 CLK_PCIE_N2

CLKREQ_PCIE#2

WLAN_PME#

1 3 5 7

9

11

13 15

17 19

21 23

25 27

29 31

33 35

37 39

41 43

45 47

49 51

53 55

57 59

61 63

65 67

69

KEY E

JNGFF1

GND_1 USB_D+ USB_DGND_7

SDIO_CLK SDIO_CMD

SDIO_DAT0 SDIO_DAT1

SDIO_DAT2 SDIO_DAT3

SDIO_WAKE SDIO_RST

GND_33 PET_RX_P0

PET_RX_N0 GND_39

PER_TX_P0 PER_TX_N0

GND_45 REFCLK_P0

REFCLK_N0 GND_51

CLKREQ0# PEWAKE0#

GND_57 RSVD/PCIE_RX_P1

RSVD/PCIE_RX_N1 GND_63

RSVD/PCIE_TX_P1 RSVD/PCIE_TX_N1

GND_69 RSVD_71

RSVD_73 GND_75

GND2

BELLW_80152-3221

CONN@

3.3VAUX_2

3.3VAUX_4

PCM_CLK

PCM_SYNC

PCM_OUT

PCM_IN

GND_18

UART_WAKE

UART_TX

UART_RX

UART_RTS UART_CTS

CLink_RST

CLink_DATA

CLink_CLK

COEX3

COEX2 COEX1

SUSCLK(32KHz)

PERST0#

W_DISABLE2# W_DISABLE1#

I2C_DAT I2C_CLK

I2C_IRQ

RSVD_64

RSVD_66 RSVD_68

RSVD_70

3.3VAUX_72

3.3VAUX_74

SP070013E00

4

Secu rity Cl assifica tion

2016/0 7/18 2016/1 1/10

Issued Da te

THIS SHEE T OF ENG INEERING DRAW ING I S THE P ROPRIETAR Y PRO PERTY O F CO MPAL ELE CTRONICS, INC. AND CON TAINS CON FIDENTIAL

AND TRA DE SE CRET INF ORMATION. THIS SHEET MAY NO T BE TRA NSFERED FRO M THE CU STODY O F THE COM PETENT DIVI SION OF R& D

DEPARTME NT EXC EPT AS AUTH ORIZED BY COMPAL ELE CTRONICS, INC . NE ITHER TH IS SHEE T NO R THE I NFORMATIO N IT CONTAINS

MAY BE USED BY O R DISCLO SED TO AN Y THIRD P ARTY WI THOUT PRI OR WR ITTEN CONSE NT OF COMP AL EL ECTRONICS, I NC.

A

B

2016/0 7/18 2016/1 1/10

C

Comp al Secre t Data

Decipher ed Date

Compal Electronics, Inc.

Tit le

Size Docu ment N umber R e v

Custom

Da te : Sh eet

D

Da te : Sh eet

Compal Electronics, Inc.

M.2 Key E (WLAN)

B5W11 M/B LA-E061P

E

o f

24 44Monday, July 18, 2016

o f

24 44Monday, July 18, 2016

o f

24 44Monday, July 18, 2016

4

1.0

A

HD Audio Codec

SM0 1000E J00 3000 mA 2 20ohm @100 mhz DCR 0 .04

+VDDA

1

Pin9 nee d to match ing with S OC HDA inter fa ce.

UA1

2

ALC233-VB2-CG_MQFN48_6X6

233@ SA00007 BF10

HP_PLUG#<28>

Pin 20 ALC283 : NC ALC255/256/233 : Pow er for combo jack depo p c ircuit at system shutdown mode

Pin 4 ALC283 : DVSS ALC255/256/233 : D C DET (For Japen c ustomer only)

3

DOS mo de

OS mode

4

BEEP#<29>

PCH_SPKR<10>

1

@

1

@

.1U_0402_16V7K

1

RA25 0_0402_5%@

JPA2 JUMP_43X39

JPA4 JUMP_43X39

CA31

GN D

2

LA1 HCB2012KF-221T30_0805

2

RA2 0_0402_5 %@

+3VS

2

RA5 0_0402_5%@

+3VS

INT_MIC_R

10m il

HP_PLUG#

+3VS

RA21 22K_0402_5%

2

RA22 22K_0402_5%

2

GND & GNDA moat

2

1

2

1

2

@

2

GND A

A

2

RA9 1K_0402_5%

Com bo MIC

EC_MUTE#<29>

HDA_RST#_R<1 0>

1

GN D

1

CA1

10U_0603_6.3V6M

1

2

GN D

Place near Pi n41

CA5 10U_0603_6.3V6M

CA6 .1U_0402_16V7K

20m il

CA10

10U_0603_6.3V6M

Place near P in1

INT_MIC

CA32

CA33

RING2

SLEEVE

+MICBIAS

+MICBIAS2

1

RA16 0_0402_5%@

1

EC_MUTE#

HDA_RST#_R

1

40m il

Close codec

2

RA13 200K _0402_1%

2

RA14 100K _0402_1%

+3VS_DVDD

+3VALW

GND A

BEEP#_R

2

1

@

CA28

100P_0402_50V8J

RA23

4.7K_0402_5%

2

1

GN D

JPA3 JUMP_43X39

1

2

1

2

@

JPA5 JUMP_43X39

1

2

1

2

@

GND A

40mil

CA2

.1U_0402_16V7K

1

2

Place near Pi n46

1

2

1

2

Place near P in9

1

2

GN D

LINE1-L LINE1-R

LINE2_L

2

4.7U_0603_6.3V6K

LINE2_R

2

4.7U_0603_6.3V6K

+MICBIAS

+MICBIAS2

MONO_IN

SENSE_A

1

CA19

2.2U_0402_6.3V6M

2

1

2

CA27

.1U_0402_16V7K

MONO_IN

1

2

10/20 vendor revi ew change to 0. 1uF.

GN D

.1U_0402_16V7K

1

2

CA2210U_0603_6.3V6M

+3VS_DVDDIO

+3VS_DVDD

CA3

.1U_0402_16V7K

1

2

@

CA11

UA1

22

LINE1-L(PORT-C-L)

21

LINE1-R(PORT-C-R)

24

LINE2-L(PORT-E-L)

23

LINE2-R(PORT-E-R)

17

MIC2-L(PORT-F-L) /RING2

18

MIC2-R(PORT-F-R) /SLEEVE

31

LINE1-VREFO-L

30

LINE1-VREFO-R

2

GPIO0/DMIC-DATA

3

GPIO1/DMIC-CLK

47

PDB

11

RESETB

12

PCBEEP

13

SENSE A

14

SENSE B

37

CBP

35

CBN

36

CPVDD

20

CPVREF

19

MIC-CAP

4

DVSS

49

Thermal PAD

ALC255-CG_MQFN48_6X6

SA000082700 255@

B

+PVDD_HDA

+AVDD1_HDA

GN D

+1.8VS_VDDA

26

PVDD1

46

AVDD1

PVDD2

40

AVDD2

SPK-OUT-L-

SPK-OUT-L+

SPK-OUT-R+

SPK-OUT-R-

HPOUT-L(PORT-I-L)

HPOUT-R(PORT-I-R)

SYNC

BCLK

SDATA-OUT

SDATA-IN

SPDIF-OUT/GPIO2

MONO-OUT

MIC2-VREFO

LDO3-CAP

LDO2-CAP

LDO1-CAP

VREF

JDREF

CPVEE

AVSS1

AVSS2

9

41

1

DVDD

DVDD-IO

1

2

GND A

Place near Pi n26

GND A

Place near Pi n40

43

42

45 44

32 33

10

6

HDA_SDOUT_R

5

HDA_SDIN0_AUDIO

8

48

16

29

7

39

27

CODEC_VREF

28

15

34

25

38

CA8

.1U_0402_16V7K

1

2

@

CA12

.1U_0402_16V7K

1

2

@

SPKL-

SPKL+

SPKR+ SPKR-

HP_LEFT HP_RIGHT

HDA_SYNC_R HDA_BIT_CLK_R

1

@EMI@

RA10 0_0402_5%

CPVEE

GND A

Pin 15 ALC283 : Ref. Resistor for Jack Detect ALC255/256/233 : Jac k Detect for SPDI F-OUT and SPK-OUT port

B

20m il

1

RA1

CA9

10U_0603_6.3V6M

0_0603_5%

GND & G NDA moat

CA13

10U_0603_6.3V6M

1

2

1

CA26

2.2U_0402_6.3V6M

2

GN D

C

(output = 300 mA)

+5VS

40mil

CA4

.1U_0402_16V7K

1

2

@ESD@

GN D

2

@

+VDDA

JPA1

1

2

JUMP_43X118

@

GND & G NDA moat

40mil

4.7 5 V

+VDDA

D

Int. Speaker Conn.

SPKR+ SPKR-

SPKL+ SPKL-

EMI r equest for s olve E MI no ise, S M01000O W00.

Analog MIC(SMD)

1

2

RA6

@

0_0402_5%

HDA_SYNC_R <1 0>

HDA_BIT_CLK_R <10>

2

CA15

@EMI@

22P_0402_50V8J

1

2

RA33 33_0402_5%

+MIC2_VREFO

1

2

CA1810U_0603_6.3V6M

1

2

CA2010U_0603_6.3V6M

1

2

CA2110U_0603_6.3V6M

1

2

RA15 100K_0402_5%

Securi ty C lassifi cation

Issu ed D ate

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY O F COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFO RMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

+1.8VS

GN D

HDA_SDOUT_R <10>

HDA_SDIN0 <10>

GN D

GND A

10m il

.1U_0402_16V7K

Place near pin28

Place near Codec

CA23

CA24

2.2U_0402_6.3V6M

1

2

@

Headphone Out

GND A

+MICBIAS

Compal Secret Data

2016/07/18 2016/11/10

Compal Secret Data

Deciph ered Dat e

D

2.2K_0402_5%

INT_MIC_R

HP_LEFT

HP_RIGHT

LINE1-L

LINE1-R

DA5

1

BAT54A-7-F_SOT23-3

1

RA7

+MICBIAS2

2

LA2EMI@ PBY160808T-121Y-N_2P

2

LA3EMI@ PBY160808T-121Y-N_2P

2

LA4EMI@ PBY160808T-121Y-N_2P

2

LA5EMI@ PBY160808T-121Y-N_2P

@ESD@

TVNST52302AB0_SOT523-3

2

15m il

1

CA14

@EMI@

220P_0402_50V7K

2

DA1

1

RA8

@

0_0603_5%

GND A

+MIC2_VREFO

RA19

2.2K_0402_5%

1

RA24

RA27

2

3

2

0_0603_5%@

1

2

0_0603_5%@

1

2

CA29 4.7U_0603_6.3V6K

1

2

CA30 4.7U_0603_6.3V6K

2

RA29

4.7K_0402_5%

2

RA32

4.7K_0402_5%

Title

HD Audio Codec ALC255/ALC233 C olay

Size Document Number R e v

Custom

Dat e: Shee t

E

40mil

2

3

1

GND

2

3

@ESD@

DA2 TVNST52302AB0_SOT523-3

1

GND

15m il

INT_MIC_R_1

SPK_R+ SPK_R-

SPK_L+

SPK_L-

GND

1

2

Omnidi rect i onal

Follo w EA52 _BM(LA-B511P) foot print

1

RA20

2.2K_0402_5%

2

SLEEVE

RING2

HPOUT_L_1

HPOUT_R_1

1

Compal Electronics, Inc.

B5W11 M/B LA-E061P

SLEEVE <28> RING2 <28>

E

HPOUT_L_1 <28>

HPOUT_R_1 <28>

JSPK1

1

2

3

4

5

G1

6

G2

ACES_50278-00401-001

CONN@

SP0 20 00 RR 00

AMIC1

+

-

GETTOP SOM4013SL-G423-RC-HS

@

CY000 002V00

of

25 44Monday, July 18, 2016

of

25 44Monday, July 18, 2016

of

25 44Monday, July 18, 2016

1

2

3

4

1.0

A

B

C

D

E

SATA HDD Conn.

1

SATA_CTX_DRX_P0<13> SATA_CTX_DRX_N0<13>

SATA_CRX_DTX_N0<13> SATA_CRX_DTX_P0<13>

2

+3VS

1

2

SATA_CTX_DRX_P0 SATA_CTX_DRX_N0

SATA_CRX_DTX_N0 SATA_CRX_DTX_P0

CO11 .1U_0402_16V7K

@

+5VS_HDD

10U_0603_6.3V6M

1

2

100 mi ls

CO12

SATA ODD Conn.

JHDD1

1

2

CO1 0.01U_0402_16V7K

CO2 0.01U_0402_16V7K

1

2

1

2

CO3 0.01U_0402_16V7K

1

2

CO4 0.01U_0402_16V7K

+3VS

1

RO3 0_0805_5%@

+5VS

CO13

.1U_0402_16V7K

1

@

2

SATA_CTX_C_DRX_P0 SATA_CTX_C_DRX_N0

SATA_CRX_C_DTX_N0 SATA_CRX_C_DTX_P0

RO1 0_0402_5%

1

@

2

+3VS_HDD

2

+5VS_HDD

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

21 22

GND

V12

GND

V12

GND

V12

GND

SANTA_194403-1

CONN@

LTCX00 7 8W 00

23 24 25 26

SATA_CTX_DRX_P1<13>

SATA_CTX_DRX_N1<13>

SATA_CRX_DTX_N1<13> SATA_CRX_DTX_P1<13>

OD D_E N<29 >

ODD_EN

CO5 0.01U_0402_16V7K

CO6 0.01U_0402_16V7K

CO7 0.01U_0402_16V7K

CO8 0.01U_0402_16V7K

+5VS

RO2 0_0805_5%

1

NBYOC@

+5VS

5

4

1

2

1

2

1

2

1

2

+5VS_ODD

2

10U_0603_6.3V6M

1

2

UO1

OUT

IN

GND

OC

EN

SY6288C20AAC_SOT23-5

BYOC@

CO9

1

2

3

+5 VS_O DD

.1U_0402_16V7K

CO10

1

2

+5VS_ODD

ODD_OC#

SATA_CTX_C_DRX_P1

SATA_CTX_C_DRX_N1

SATA_CRX_C_DTX_N1 SATA_CRX_C_DTX_P1

80m ils

ODD_MD

T206

@

T207

@

JODD1

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

DP

9

+5V

10

+5V

11

MD

12

GND

13

GND

SANTA_201501-2

CONN@

SP01001MV00

14

15

1

2

3

4

Secu rity Cl assifica tion

2016/0 7/18 2016/1 1/10

Issued Da te

THIS SHEE T OF ENG INEERING DRAW ING I S THE P ROPRIETAR Y PRO PERTY O F CO MPAL ELE CTRONICS, INC. AND CON TAINS CON FIDENTIAL

AND TRA DE SE CRET INF ORMATION. THIS SHEET MAY NO T BE TRA NSFERED FRO M THE CU STODY O F THE COM PETENT DIVI SION OF R& D

DEPARTME NT EXC EPT AS AUTH ORIZED BY COMPAL ELE CTRONICS, INC . NE ITHER TH IS SHEE T NO R THE I NFORMATIO N IT CONTAINS

MAY BE USED BY O R DISCLO SED TO AN Y THIRD P ARTY WI THOUT PRI OR WR ITTEN CONSE NT OF COMP AL EL ECTRONICS, I NC.

A

B

2016/0 7/18 2016/1 1/10

C

Comp al Secre t Data

Decipher ed Date

Compal Electronics, Inc.

Tit le

Size Docu ment N umber R e v

Custom

Da te : Sh eet

D

Da te : Sh eet

Compal Electronics, Inc.

HDD/ODD/ HDD Re-Driver

B5W11 M/B LA-E061P

E

o f

26 44Monday, July 18, 2016

o f

26 44Monday, July 18, 2016

o f

26 44Monday, July 18, 2016

3

4

1.0

5

4

3

2

1

D

C

D

C

SPACE

B

A

Secu rity Cl assifica tion

Issued Da te

THIS SHEE T OF ENG INEERING DRAW ING I S THE P ROPRIETAR Y PRO PERTY O F CO MPAL ELE CTRONICS, INC. AND CON TAINS CON FIDENTIAL

AND TRA DE SE CRET INF ORMATION. THIS SHEET MAY NO T BE TRA NSFERED FRO M THE CU STODY O F THE COM PETENT DIVI SION OF R& D

DEPARTME NT EXC EPT AS AUTH ORIZED BY COMPAL ELE CTRONICS, INC . NE ITHER TH IS SHEE T NO R THE I NFORMATIO N IT CONTAINS

MAY BE USED BY O R DISCLO SED TO AN Y THIRD P ARTY WI THOUT PRI OR WR ITTEN CONSE NT OF COMP AL EL ECTRONICS, I NC.

5

4

2016/0 7/18 2016/1 1/10

3

Comp al Secre t Data

Decipher ed Date

CompalElectronics,Inc.

Tit le

EMMC STORAGE

Size Docu ment N umber R e v

Custom

B5W11M/BLA-E061P

Da te : Sh eet

Monday, July 18, 2016

Da te : Sh eet

Monday, July 18, 2016

2

Monday, July 18, 2016

1

o f

27

o f

27

o f

27

A

1.0

44

A

B

C

D

E

USB3.0 (Port 1)

USB3_CTX_DRX_N1<13>

1

2

USB3_CTX_DRX_P1<13>

USB3_CRX_DTX_N1<13>

USB3_CRX_DTX_P1<13>

USB2.0 (Port 2)

For ESD request

DS21

CS22

1

2

USB20_P1<13>

USB20_N1<13>

.1U_0402_16V7K

USB3_CTX_C_DRX_P1

.1U_0402_16V7K

USB3_CRX_DTX_N1

USB3_CRX_DTX_P1

USB20_P1

USB20_N1

USB3_CTX_C_DRX_N1

1

2

CS21

1

RS21

1

RS22

1

RS24

1

RS25

LS23

2

3

MCM1012B900F06BP_4P

EMI@

@RF@

2

0_0402_5%

2

0_0402_5%

2

0_0402_5%

2

0_0402_5%

1

4

USB3_CTX_L_DRX_N1

USB3_CTX_L_DRX_P1

USB3_CRX_L_DTX_N1

USB3_CRX_L_DTX_P1

U2DP1_L

U2DN1_L

USB3_CTX_L_DRX_P1

USB3_CTX_L_DRX_N1

USB3_CRX_L_DTX_P1

USB3_CRX_L_DTX_N1

+USB3_VCCA

ESD@

1

2

4

5

3

8

L05ESDL5V0NA-4 SLP2510P8

DS22

6

5

4

AZC099-04S.R7G_SOT23-6

I/O4

VDD

I/O3

ESD@

10

9

7

6

I/O2

GND

I/O1

USB3_CTX_L_DRX_P1

9

USB3_CTX_L_DRX_N1

8

USB3_CRX_L_DTX_P1

7

USB3_CRX_L_DTX_N1

6

3

2

1

USB_EN<29>

U2DP1_L

U2DN1_L

+5VALW

CS23 .1U_0402_16V7K

1

2

USB_EN

Max H:6mm SF 00 00 06 90 0

USB3_CRX_L_DTX_N1 USB3_CRX_L_DTX_P1

USB3_CTX_L_DRX_N1 USB3_CTX_L_DRX_P1

US21

5

IN

4

EN

SY6288C20AAC_SOT23-5

1

+

CS25

2

220U_C6_6.3V_M_R15

U2DN1_L

U2DP1_L

1

OUT

2

GND

3

RS23 0_0402_5%@

OC

+USB3_VCCA

W= 10 0m il s

1

CS26 470P_0402_50V7K

2

@

+USB3_VCCA

W= 10 0m il s

1

2

USB3.0 Conn.

JUSB1

1

VBUS

2

D-

3

D+

4

GND

5

StdA-SSRX-

6

StdA-SSRX+

7

GND-DRAIN

8

StdA-SSTX-

9

StdA-SSTX+

LOTES_AUSB0015-P001A

CONN@

DC23300AI00

1

CS24 .1U_0402_16V7K

2

@

GND GND GND

GND

10 11 12

13

USB_OC0# <13>

1

2

3

USB20_P2_L

ESD@

EMI@

I/O2

GND

I/O1

1

USB20_N2_L

4

USB20_P2_L

3

2

USB20_N2_L

1

B

USB20_P2<13>

USB20_N2<13>

+USB3_VCCA

4

A

2

3

MCM1012B900F06BP_4P LS24

DS23

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT23-6

+USB3_VCCA

W= 10 0m il s

1

CS27 470P_0402_50V7K

2

@

USB2.0 Conn

JUSB2

USB20_N2_L

USB20_P2_L

1 2 3

4

DC23300AH00

Secur ity Cla ssifica tion

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

5

VBUS

G1

6

D-

G2

7

D+

G3

8

GND

G4

ACON_UARC9-4K1986

CONN@

Compal Secret Data

2016/07/ 18 2016/11/10

Compal Secret Data

Deciphere d Date

D

Need check pin def i ni t i on

IO/B (USB, AUDIO, CR)

HPOUT_L_1<25>

HPOUT_R_ 1<2 5>

SLEEVE<25> RING2<25>

HP_PLUG#<25>

+3VS

USB20_N8<13>

USB20_P8<13>

USB20_P3<13>

USB20_N3<13>

+5VALW

Title

Size Document Number R ev

Custom

Date : Sheet

HPOUT_L_1

HPOUT_R_1

SLEEVE RING2

HP_PLUG#

GNDA

USB20_N8

USB20_P8

USB20_P3 USB20_N3

USB_EN

Compal Electronics, Inc.

USB Conn/IO_B

B5W11 M/B LA-E061P

JUSB3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

G1

22

G2

ACES_85201-2005N

CONN@

SP010011U00

E

3

4

1.0

of

28 44Monday, July 18, 2016

of

28 44Monday, July 18, 2016

of

28 44Monday, July 18, 2016

1

2

CB9 1000P_0402_50V7K

+3VLP_EC

1

2

1

EC_PME# PU +3V_LAN at LAN s ide

+3VLP_EC

RB13 2.2K_0402_5%

RB14 2.2K_0402_5%

For turn off internal LPC module of KB9032

CB5 100P_0402_50V8J@ESD@

2

3

@

RB5 47K_0402_5%

1

2

1

2

ESPI@

1

RB8 47K_0402_5%

RB9 47K_0402_5%

CB6 100P_0402_50V8J

@EMI@

2

CB7 22P_0402_50V8J

EC_KBRST#_R<9>

2

ESPI@

1

2

1

2

1

2

@EMI@

2

1

RB10 33_0402_5%

For abnor mal shutdo wn

DB2 RB751V-40_SOD323-2

SPOK

Board ID

4

1

DB3 RB751V-40_SOD323-2

1

DB4 RB751V-40_SOD323-2

1

+3VLP_EC

2

RB1 100K_0402_1%

Ra

1

AD_BID

1

RB4 15K_0402_1%

Rb

2

Analog Board ID def initio n, Please see page 3.

A

EC_PME#

ESPI_RST#

PLT_RST#

AC_IN

CLK_LPC_EC

1

RB12 0_0402_5%

1

@

2

1

CB4 .1U_0402_16V7K

2

@

A

EC_RST#

EC_SMB_CK1

EC_SMB_DA1

EC_KBRST#

2

EC_RSMRST#

PCH_PWROK

EC_VCCST_PG_R

+3VLP

ESPI Bus Pin : 1~5.7.8.10.12.14 LPC Bus Pin : 3~5.7.8.10.12.13

Combine w/ SMI

PU at CPU side

PWR_SUSP_LED#<30>

SUSPWRDNACK<11>

SOC_SML1CLK<9>

SOC_SML1DATA<9>

E51TXD_P80DATA<24>

E51RXD_P80CLK< 24>

B

RB22

@

0_0805_5%

1

2

.1U_0402_16V7K

CB1

1

2

SUSPWRDNACK

EC_KBRST#

TPM_SERIRQ<9>

LPC_FRAME#<9>

LPC_AD3_R<9>

LPC_AD2_R<9>

LPC_AD1_R<9>

LPC_AD0_R<9>

CLK_LPC_EC<9>

PLT_RST#<11>

EC_RST#<31>

EC_SCI#<7>

WLAN_ON<24>

KSI[0..7]<30>

KSO[0..17]<30>

EC_SMB_CK1<34,35>

EC_SMB_DA1<34,35>

PM_SLP_S3#<11,32>

ESPI_RST#<9>

SPOK<36,39>

TP_EN<30>

TS_EN<12,21>

WL_OFF#<24>

AC_PRESENT<11>

FAN_SPEED1<31>

VR_ON<32,40>

PCH_PWROK<11,32>

VR_PWRGD<40>

PBTN_OUT#<11>

PM_SLP_S4#<11,32>

TPM_SERIRQ

LPC_FRAME#

LPC_AD3_R

LPC_AD2_R

LPC_AD1_R

LPC_AD0_R

CLK_LPC_EC

PLT_RST#

EC_RST#

EC_SCI#

WLAN_ON

KSI0

KSI1

KSI2

KSI3

KSI4

KSI5

KSI6

KSI7

KSO0

KSO1

KSO2 KSO3

KSO4

KSO5 KSO6

KSO7

KSO8

KSO9

KSO10

KSO11

KSO12

KSO13

KSO14

KSO15

KSO16 KSO17

EC_SMB_CK1 EC_SMB_DA1

SOC_SML1CLK

SOC_SML1DATA

PM_SLP_S3#

ESPI_RST#

SPOK

TP_EN

TS_EN

WL_OFF#

AC_PRESENT

FAN_SPEED1

VR_ON

E51TXD_P80DATA

E51RXD_P80CLK

PCH_PWROK

PWR_SUSP_LED#

VR_PWRGD

PBTN_OUT#

PM_SLP_S4#

CO-LAY wit h KB9032QA (SA0000 80J00)

B

+3VALW_1.8VALW_PGPPA

CB2

1

2

UB1

1 2

3 4 5 7 8

10

12 13

37

20

38

55 56

57 58 59

60 61 62

39 40 41

42 43 44

45 46 47

48 49 50

51 52 53

54

81 82

77

78 79 80

6

14

15 16 17

18 19

25

28 29

30 31 32

34

36

122

123

+3VLP_EC

1

RB2

@

RB3 0_0402_5%

2

@

+3VCC_LPC

GATEA20/GPIO00 KBRST#/GPIO01

SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1

LPC & MISC

LPC_AD0

CLK_PCI_EC PCIRST#/GPIO05

EC_RST#

EC_SCI#/GPIO0E

CLKRUN#/GPIO1D

KSI0/GPIO30 KSI1/GPIO31

KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34

KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37

KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22

KSO3/GPIO23 KSO4/GPIO24

Int. K /B

KSO5/GPIO25

Matrix

KSO6/GPIO26 KSO7/GPIO27 KSO8/GPIO28

KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B

KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E

KSO15/GPIO2F

KSO16/GPIO48 KSO17/GPIO49

EC_SMB_CLK1/GPIO44

EC_SMB_DAT1/GPIO45 EC_SMB_CLK2/GPIO46 EC_SMB_DAT2/GPIO47

PM_SLP_S3#/GPIO04

GPIO07

GPIO08 GPIO0A GPIO0B

GPIO0C AC_PRESENT/GPIO0D

PWM2/GPIO11

FAN_SPEED1/GPIO14 FANFB1/GPIO15

EC_TX/GPIO16 EC_RX/GPIO17 PCH_PWROK/GPIO18

SUSP_LED#/GPIO19

NUM_LED#/GPIO1A

PBTN_OUT#/GPIO5D

PM_SLP_S4#/GPIO5E

C

PN :SM 0100 0K5 00

LB1 FBMA-L11-160808-800LMT_0603

1

2

0_0402_5%

9

22

33

96

67

125

111

VCC

VCC0

VCC_LPC

PWM Output

PS2 Inter face

AVCC

EC_VCCST_PG/GPIO0F

EC_FAN_PWM/GPIO12

VCIN1_BATT_TEMP/AD0/GPIO38 VCIN1_BATT_DROP/AD1/GPIO39

AD Input

DA Output

EN_DFAN1/DA1/GPIO3D

EC_MUTE#/PSCLK1/GPIO4A

USB_EN#/PSDAT1/GPIO4B

VCIN0_PH1/GPXIOD00

SPI Device Inter face

SPI Flash ROM

EC_CIR_RX/AD6/GPIO40

SYS_PWROK/AD7/GPIO41

BATT_CHG_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO55

SM Bus

EC_RSMRST#/GPXIOA03

VCIN1_ADP_PROCHOT/GPXIOA05

VCOUT1_PROCHOT#/GPXIOA06

VCOUT0_MAIN_PWR_ON/GPXIOA07

GPIO

GPO

PCH_PWR_EN/GPXIOA10

PWR_VCCST_PG/GPXIOA11

VCIN1_AC_IN/GPXIOD01

GPI

GND

11

AGND

GND

24

35

69

94

113

ECAGND

Secur ity Cla ssifica tion

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VLP_ECA

1

CB3 .1U_0402_16V7K

2

ECAGND

21

AD4/GPIO42 AD5/GPIO43

DA0/GPIO3C

DA2/GPIO3E

DA3/GPIO3F

GPIO50

GPXIOA04

GPXIOA09

GPXIOD06

BATT_TEMP

2

100P_0402_50V8J

2

23

26

27

63 64 65

66

75 76

68

70 71

72

83

84 85 86

87 88

97 98

99

109

119

120

126 128

73 74

89

90 91 92

93 95

121

127

100 101

102 103 104

105 106 107

108

110

112

114 115 116

117 118

124

1

2016/07/ 18 2016/11/10

BEEP#/GPIO10

AC_OFF/GPIO13

ADP_I/AD2/GPIO3A

AD_BID/AD3/GPIO3B

PSCLK2/GPIO4C PSDAT2/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

ENKBL/GPXIOA00

WOL_EN/GPXIOA01

ME_EN/GPXIOA02

MISO/GPIO5B

MOSI/GPIO5C

SPICLK/GPIO58 SPICS#/GPIO5A

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

SYSON/GPIO56

VR_ON/GPIO57

DPWROK_EC/GPIO59

BKOFF#/GPXIOA08

EC_ON/GPXIOD02

ON/OFF#/GPXIOD03 LID_SW#/GPXIOD04

SUSP#/GPXIOD05

PECI/GPXIOD07

V18R/VCC_IO2

KB9022QD_LQFP128_14X14

20m il

1

CB8

LB2

FBMA-L11-160808-800LMT_0603

PN :SM 0100 0K5 00

C

ECAGND <34>

EC_VCCST_PG_R

BEEP#

FAN_PWM1

I2C_TS_RST#

BATT_TEMP

VCIN1_BATT_DROP

ADP_I

AD_BID

WLAN_PME#

EC_PME#

LAN_PWR_EN

EC_MUTE# USB_EN

PM_SLP_S0#

TP_CLK

TP_DATA

ENBKL

TP_PWR_EN

ME_EN

VCIN0_PH

BT_ON

SYS_PWROK_R

BATT_4S

BATT_BLUE_LED#

ODD_EN

PWR_LED#_R

BATT_AMB_LED#

SYSON

EC_TP_INT#

EC_RSMRST#

VCIN1_ADP_PROCHOT VCOUT1_PROCHOT#

MAINPWON

BKOFF#

LAN_GPO

3V_EN_R

AC_IN

EC_ON

ON/OFFBTN#

LID_SW#

SUSP#

H_PECI_R

RB19 43_0402_1%

EC_VCCST_PG_R < 11,32>

BEEP# <25>

FAN_PWM1 <31> I2C_TS_RST# <21>

BATT_TEMP<34> VCIN1_BATT_DROP <34>

ADP_I <34,35>

WLAN_PME# <24>

EC_PME# <23>

LAN_PWR_EN <23>

EC_MUTE# <25>

USB_EN <28>

T85 @

PM_SLP_S0# <11>

TP_CLK <30>

TP_DATA <30>

ENBKL <7>

TP_PWR_EN <30>

ME_EN <10>

VCIN0_PH <34>

BT_ON <24>

BATT_4S < 35>

BATT_BLUE_LED# <30>

ODD_EN <26>

PWR_LED#_R <30>

BATT_AMB_LED#<30>

SYSON <14,32,37>

EC_TP_INT# <7,30>

EC_RSMRST# <11>

VCIN1_ADP_PROCHOT <34>

MAINPWON <31,34,36>

BKOFF# <21>

LAN_GPO <23>

AC_IN <35>

EC_ON <36>

ON/OFFBTN# <30>

LID_SW# <30>

SUSP# <14,32,35,37>

1

2

+3VLP_EC

Compal Secret Data

Deciphere d Date

PU at PTP side

H_PECI <7>

D

LID_SW#

I2C_TS_RST#

SYS_PWROK_R

MAINPWON

3V_EN_R

H_PROCHOT#<7>

D

H_PROCHOT#

Title

Size Document Number R ev

Custom

Date : Sheet

1

RB11 0_0402_5%

For Th ermal Porte ct Shutdown

DB1 RB751V-40_SOD323-2

1

RB16 1K_0402_5%

1

RB20 0_0402_5%@

1

RB21 0_0402_5%@

Compal Electronics, Inc.

EC ENE KB9022

B5W11 M/B LA-E061P

@

2

E

1

RB15 100K_0402_1%

2

RB6 100K_0402_5%

2

3V_EN

VR_HOT#

VCOUT1_PROCHOT#

E

2

1

RB17 1M_0402_5%

SYS_PWROK <11,32>

3V_EN <36>

1

2

VR_HOT# <40>

of

29 44Monday, July 18, 2016

of

29 44Monday, July 18, 2016

of

29 44Monday, July 18, 2016

+3VLP_EC

1

2

3

4

1.0

A

KB Conn.

ON/OFF BTN

RK1 100K_0402_5%

1

2

+3VLP

ON/OFFB TN#<29>

1

Test Only

BOT

2

SWK1

@

EVQPLDA15_4P

1

2

5

6

ON/OFFBTN#

3

4

KSI[0..7]

KSO[0..17]

KSI[0..7] <29>

KSO[0..17] <29>

B

30 29 28

27

ON/OFFBTN#

26

KSO0

25

KSO1

24

KSO2

23

KSO3

22

KSO4

21

KSO5

20

KSO6

19

KSO7

18

KSO8

17

KSO9

16

KSO10

15

KSO11

14

KSO12

13

KSO13

12

KSO14

11

KSO15

10

KSO16

9

KSO17

8

KSI0

7

KSI1

6

KSI2

5

KSI3

4

KSI4

3

KSI5

2

KSI6

1

KSI7

ACES_85201-2805

SP0100 0GO00

GND2 GND1 28

27 26 25

24 23 22

21 20 19

18 17 16

15 14 13

12 11 10

9 8 7

6 5 4

3 2 1

CONN@

JKB1

C

TP/B Conn.

+3VALW

2

CK3

1U_0402_6.3V6K

I2C_1_SCL<12>

I2C_1_SDA<12>

1

TP_PWR_EN follow SYSON behavior

2N7002KDW_SOT363-6

RK8 0_0402_5%@

2N7002KDW_SOT363-6

5

OUT

IN

GND

4

EN

SY6288C20AAC_SOT23-5

+3V_PTP

5

G

QK1B

3

4

S

D

1

2

QK1A

6

1

RK9 0_0402_5%

UK1

1

2

3

OC

TP_PWR _EN <29>

2.2K_0402_5%

2

G

D

@

D

+3VALW

RK5

4.7K_0402_5%

+3VS

EC PS2

PCH I2C

+3V_PTP

1

2

EC_TP_IN T#<7 ,29>

1

RK6

4.7K_0402_5%

2

TP_CLK

TP_DATA

.1U_0402_16V7K

TP_EN<2 9>

2

@

2

@

2

+3V_PTP

4.7U_0603_6.3V6K

CK1

1

2

+3V_PTP

1

RK7

2

1

S

2

1

RK10

2.2K_0402_5%

2

I2C_1_SCL_R

I2C_1_SDA_R

+3V_PTP

2

1

RK4 10K_0402_5%

EC_TP_INT#

TP_CLK<29>

TP_DAT A<29>

1

RK20_0402_5%

1

RK30_0402_5%

CK2

1

TP_CLK TP_DATA

I2C_1_SDA_R I2C_1_SCL_R

EC_TP_INT#

TP_EN

+3V_PTP

E

10

JTP1

1

2

3

4

5

6

7

8

9

GND

ACES_51524-00801-001

CONN@

SP01001A910

1

2

Lid Switch

(Hall Effect Switch)

Follow 2015

+3VLP

UG1

OUT

2

VDD

1

CG2

3

.1U_0402_16V7K

2

GND

APX8132AI_TSOT-23-3

SA00008K800, S IC APX8132AI-T RG SOT-23 3P HALL SENS OR

LID_SW#

3

1

LID_SW# <29>

3

Bat t er y L E D

RG4

BATT_AM B_LED#<29>

BATT_BLU E_LED#<2 9>

RG8

@

0_0402_5%

1

PWR_L ED#_R<29>

100K_0402_5% @

avoid flash issue when

4

Secur ity Cla ssifica tion

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

abnormall shutdown

2016/07/ 18 2016/11/10

1

RG9

2

Compal Secret Data

Deciphere d Date

2

1

2

G

3

PWR_LED#

D

QG2 L2N7002LT1G_SOT23-3

@

S

D

PWR_S USP_LED#<29>

BATT_AMB_LED#

BATT_BLUE_LED#

Follow Z5W1M LED.

PWR_S USP_LED#

PWR_L ED#

Title

Size Document Number R ev

Custom

Date : Sheet

1.24K_0402_1%

1

RG6

820_0402_5%

RG11

1.24K_0402_1%

1

RG10

820_0402_5%

Compal Electronics, Inc.

KB & TP & TPM & LID SW & LED

B5W11 M/B LA-E061P

LED1

A

2

Power LED

2

4

3

B

2

1

LTST-C295TBKF-CA_AMBER-BLUE

LED2

A

4

3

B

2

1

LTST-C295TBKF-CA_AMBER-BLUE

E

30 44Monday, July 18, 2016

+5VALW

4

1.0

of

A

B

C

D

E

FAN1 Conn

1

2

3

CF2

@EMI@

1000P_0402_50V7K

FAN_SPEED1<29>

+5VS

1

2

+3VS

1

RF2 10K_0402_5%

2

1

CF3 1000P_0402_50V7K

@EMI@

2

40m il

1

RF1 0_0603_5%@

2

CF1

4.7U_0603_6.3V6K

1

FAN_PWM1<29>

Screw Hole

+VCC_FAN1

2

H_3P0

H_3P6

40m il

+VCC_FAN1 FAN_SPEED1

FAN_PWM1

JFAN1

1

2

3

4

5

G1

6

G2

ACES_50278-00401-001

CONN@

SP0200 0RR00

H_3P3X3P0N

H5

H4

H3

H_3P0

1

@

H13

H_3P6

1

@

H23

@

1

H6

H_3P0

1

@

H15

H14

H_3P6

1

@

H25

H_3P0N

@

1

H9

H_3P0

@

H_3P0

1

H11

H10

H_3P0

1

@

H12 H_2P8X2P5N

@

1

FD1

@

1

FIDUCIAL_C40M80

FD3

@

1

FIDUCIAL_C40M80

FD2

@

1

FIDUCIAL_C40M80

FD4

@

1

FIDUCIAL_C40M80

Reset Circuit

BI_GATE PH to +RTCVCC at PWR s ide

BI_GATE<34>

2N7002KDW_SOT363-6

BI_GATE

QG1B

+3VLP

2

RG3 10K_0402_5%

1

BI_GATE#

2

C70 .1U_0402_16V7K

G

3

D

5

G

1

2

S

4

1

RG1 0_0402_5%@

1

RG2 0_0402_5%@

6

D

2N7002KDW_SOT363-6 QG1A

S

1

2

MAINPWON <2 9,34,36>

EC_RST# < 29>

1

2

3

BI SW

Reset But t on

SWG2

1

SKPMAME010_2P

2

BI_GATE

SWG1

3

4

ATE-2-V-TR_4P

H : 3.8mm

1

2

BI_S <34>

Release : Bat t er y Off Push : Bat t er y ON

4

Secur ity Cla ssifica tion

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/07/ 18 2016/11/10

Compal Secret Data

Deciphere d Date

Compal Electronics, Inc.

Title

Size Document Number R ev

Custom

Date : Sheet

D

Date : Sheet

Compal Electronics, Inc.

FAN & Screw Hole & Reset

B5W11 M/B LA-E061P

E

of

31 44Monday, July 18, 2016

of

31 44Monday, July 18, 2016

of

31 44Monday, July 18, 2016

4

1.0

A

B

C

D

E

DC Interface

2

RQ2 0_0402_5%@

1

2

SUSP#

SUSP#<14,29,35,37>

1

RQ1 0_0402_5%

2N7002KDW_SOT363-6

10K_0402_5%

1

2

@

1

100K_0402_5% @

SUSP

2

G

1

R30

@

2

CQ4

@

.1U_0402_16V7K

2

CQ2

@

.1U_0402_16V7K

+5VALW

2

R25

1

Q4A

@

6

D

S

1

+5VALW

5VS_ON

+5VALW

3VS_ON

+3VALW

+0.6VS_VTT

1

R26 470_0603_5%@

2

+0.6VS_VTT_R

3

D

S

4

UQ1

1

2

3

4

5

6

7

EM5209VF_DFN14_2X3

Q4B

@

2N7002KDW_SOT363-6

5

SUSP

G

VIN1

ON1

VBIAS

ON2

VIN2

VOUT1

GND

VOUT2

GPAD

SYSON_2V5#<37>

For Power ON/Off Sequence

+5VS

+3VS

.1U_0402_16V7K

14

13

1

2

12

CT1

CQ1 1000P_0402_50V7K

11

1

2

10

CT2

CQ3

9

8

15

SYSON_2V5#

L2N7002WT1G_SC-70-3

+5VS_OUT

1

1000P_0402_50V7K

+3VS_OUT

1

R31

470_0603_5%

2

Q7

@

JPQ2

@

1

2

JUMP_43X118

JPQ1

@

1

2

JUMP_43X118

+2.5V

2

@

1

D

G

S

3

2

+5VS

+3VS

470_0603_5%

+1.2V_VDDQ_R

2N7002KDW_SOT363-6

SYSON#

+1.2V_VDDQ

R27

Q5A

2

G

@

S

.1U_0402_16V7K

1

CQ5

CQ6

2

2N7002KDW_SOT363-6

PM_SLP_S3#<11,29>

+5VALW

2

R28 100K_0402_5%

@

1

SYSON#

Q5B

@

6

D

1

2N7002KDW_SOT363-6

3

D

G

S

4

SYSON

5

SYSON <14,29,37>

PM_SLP_S4#<11,29>

R24

100K_0402_5%

Q2A

2

G

100K_0402_5%

2N7002KDW_SOT363-6

2

G

+3VALW

S

R29

Q6A

1

2

6

D

1

+3VALW

1

2

6

S

1

D

PM_SLP_S3

PM_SLP_S4

G

2

S

1

G

5

S

4

G

5

S

4

G

2

S

1

G

5

S

4

G

5

S

4

Q1A 2N7002KDW_SOT363-6

6

D

EC_VCCST_PG_R <11,29>

MOW14 , Fo r t CPU2 8 2 00us( max) SLP_S 3# to VCCST _PWR GD deas sert ion

Q1B 2N7002KDW_SOT363-6

3

VR_ON <29,40>

MOW14 , Fo r t PLT1 7 2 00us( max) SLP_S3 # to IMVP VR _ON d easse rtion

Q2B 2N7002KDW_SOT363-6

3

SUSP#

MOW14 , Fo r t PLT1 8 2 00us( max)

Q3A 2N7002KDW_SOT363-6

6

Q3B 2N7002KDW_SOT363-6

3

Q6B 2N7002KDW_SOT363-6

3

SLP_S3# t o VCCI O VR di sable

@

SYS_PWROK <11,29>

@

PCH_PWROK <11,29>

SYSON

MOW14 , Fo r t PLT1 5 2 00us( max) SLP_S4# to VDDQ ramp dow n

1

2

3

4

Secur ity Cla ssifica tion

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/07/ 18 2016/11/10

Compal Secret Data

Deciphere d Date

Compal Electronics, Inc.

Title

Size Document Number R ev

Custom

Date : Sheet

D

Date : Sheet

Compal Electronics, Inc.

DC Interface

B5W11 M/B LA-E061P

of

32 44Monday, July 18, 2016

of

32 44Monday, July 18, 2016

of

E

32 44Monday, July 18, 2016

3

4

1.0

A

B

C

D

E

schematic from A4WAS

1

PL101

+19V_ADPIN

PJP101

@

ACES_50305-00441-001_4P

1

2

3

4 GND GND

2

+3VLP

PBJ101 @

- +

2

ML1220T 13RE

3

1

PR101

@

0_0402_5%

1

PR102

560_0603 _5%

1

EMI@

100P_0603_50V8

2

HCB2012KF-121T50_0805

PC102

2

PR103

560_0603 _5%

1

EMI@

1

2

+RTCBA TT

+19V_VIN

2

+CHGRTC

1

EMI@

1000P_0603_50V7K

2

PC104

1

2

3

4

Secur ity Cla ssifica tion

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2015/10/ 02 2016/11/10

Compal Secret Data

Deciphere d Date

CompalElectronics,Inc.

Title

PWRDCIN/Pre-charge

Size Document Number R ev

Custom

B5W1SM/BLA-D671P

Date : Sheet

D

Date : Sheet

E

of

33 44Monday, July 18, 2016

of

33 44Monday, July 18, 2016

of

33 44Monday, July 18, 2016

4

0.2

A

2013/07/23 change PC5 and PC6 function field from 37.1 to 47.1

B

C

D

E

schematic from A4WAS

+3V LP

1

MB:Battery Con Put TOP Side

Battery Bot Side

PIN1 GND PIN2 GND PIN3 S MD PIN4 S MC PIN5 TEMP PIN6 BI PIN7 Batt + PIN8 Batt +

2

change PL201, PL202 SM01000C000 to comm part SM01000P200

2013/06/07 Add for ENE9022 Battery Voltage drop detection. Connect to ENE9022 pin64 AD1.

3

VAL50/ZAL20 Battery is 3-cell NVDC design. B+=9V Change PR12=50k if Battery is 2-cell NVDC design B+=6V

PJP201

@

1

2

EC_SMB_DA1-1

3

EC_SMB_CK1-1

4

BATT_TS

5

BATT_B/I

6

7

8

9

GND

10

GND

CVILU_CI9908M2HR0-NH

+17. 4V_BAT T+

0.1U_0402_25V6

1

EMI@

1000P_0402_50V7K

2

PC204

@

PR207 100_0402_1%

1

2

PR205 100_0402_1%

1

2

PR202

200K_0402_1%

1

PR203 1K_0402_1%

PL201

EMI@

HCB2012KF-121T50_0805

1

PL202

EMI@

HCB2012KF-121T50_0805

1

PC201

+19VB_5V

2

1

2

BI_GATE<31>

2

1

PR209

@

80.6K_0402_1%

2

1

PR211

@

10K_0402_1%

2

+3V LP

100K_0402_5%

1

PC202

EMI@

0.01U_0402_25V7K

2

PR210

@

0_0402_5%

1

BAT T_TE MP <2 9>

+RT CVC C

1

PR212

2

+17. 4V_BAT T

2

EC_SMB_DA1 <29,35>

EC_SMB_CK1 <29,35>

PQ201 Change to SB00000QO00, SB501380010(BSS138LT1G Del)

1

D

2

PQ201

G

BSS138LT1G_SOT23-3

S

3

PR217

@

0_0402_1%

BI_S < 31>

2

1

VCIN 1_BA TT_DRO P <29>

T202 T201 must close to PH201

2014/09/25 update

For KB9022 sense 20mΩ

45W PR206 10K ohm SD034100 280

PH1

+3V LP_E CA

100K_0402_1%_NCP15WF104F03RC

PH201

T202@

T201@

<45, 47>

100K_0402_1%

MAINPWON<29,31,36>

2V 1V

1

PR204

16.9K_0402_1%

2

1

2

PC203 must close to EC pin

PC203

@

0.1U_0402_25V6

1

2

PR213

@

MAINPWON

Re c o veryAc t i v e

45 W, 0.4 7V5 8. 5W, 0. 6 1V

1

2

VCIN 0_PH <2 9>

1

PC205

@

0.1U_0603_25V7K

2

PU201

@

1

VCC

TMSNS1

2

GND

RHYST1

3

OT1

TMSNS2

4

RHYST2

OT2

G718TM1U_SOT23-8

1

PR215

@

10K_0402_1%

2

8

7

6

5

close to RTC

2

PR216

@

47K_0402_1%

1

PR214

@

10K_0402_1%

2

1

@

PH203

2

100K_0402_1%_NCP15WF104F03RC

PH1 under CPU botten side : CPU thermal protection at 89 +-3 degree C Recovery at 56 +-3 degree C

ADP_ I <2 9,35>

2

45W@

PR206 10K_0402_1%

1

PR208

10K_0402_1%

2

VCIN 1_ADP_ PROCH OT <29 >

1

PH202

@

100K_0402_1%_NCP15WF104F03RC

2

1

2

3

4

Secur ity Cla ssifica tion

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

ECAG ND<29 >

Compal Secret Data

2015/10/ 02 2016/11/10

Compal Secret Data

Deciphere d Date

D

CompalElectronics,Inc.

Title

PWR-BATTERYCONN/OTP

Size Document Number R ev

Custom

B5W1SM/BLA-D671P

Date : Sheet

E

of

34 44Monday, July 18, 2016

of

34 44Monday, July 18, 2016

of

34 44Monday, July 18, 2016

4

0.2

A

Protection for reverse input

Need check the SOA for inrush

PR301

1

+19V_VIN

2

3

For 4S per cell 4.35V battery

4

1M_0402_5%

MDU1512RH_POWERDFN56-8-5

5

1

PC301

2

2200P_0402_50V7K

BATT_4S<29>

SUSP#<14,29,32,37>

PQ302

1

2

3M_0402_5%

1

2 3

4

BQ24725A_ACDRV_1

PR323

100K_0402_1%

1

2

PQ308

2

G

A

PQ301

2

G

PR302

2

+19V_P1

1

PR304@

0_0402_5%

2

BQ2472 5A_ACDET

2

1

D

S

2N7002KW_SOT323-3

3

Vgs = 20V

1

D

Vds = 60V Id = 250mA

S

2N7002KW_SOT323-3

3

1

PC302

2

0.1U_0402_25V6

1

PR309

2

4.12K_0603_1%

1

PR321

2M_0402_1%

2

1

PR322

@

0_0402_5%

2

1

PQ307 LTC015EUBFS8TL_UMT3F

3

PQ303 AON7506_DFN33-8-5

1 2

3

PR310

4.12K_0603_1%

+19V_P2

5

4

PC308

0.1U_0402_25V6

+3VLP

PR315 100K_0402_1%

1

2

PR303

0.02_1206_1%

1

2

1

PC309

0.1U_0402_25V6

BQ24725A_ACP

BQ2472 5A_CMSRC

BQ24725 A_ACDRV

2

AC_IN<29>

PR318 422K_04 02_1%

1

+19V_VIN

1

PC321

2

2200P_0402_50V7K

Vin Dectector

Min. Typ Max. L-->H 17.16V 17.63V 18.12V H-->L 16.76V 17.22V 17.70V

VILIM = 20*ILIM*Rsr ILIM = 3.3*100/(100+316)/20/0.01 = 3.966 A

B

C

D

schematic from module

+19VB

PJ301

@

JUMP_43X79

1

2

1

2

PL301

EMI@

4

3

+19V_VIN

1

2

BQ24725A_ACN

PR319

66.5K_0402_1%

PC310

2

PC312

1

1U_0603_25V6K

21

1

2

3

4

5

1

2

0.1U_0402_25V6

PU301

PAD

ACN

ACP

CMSRC

ACDRV

ACOK

PC322

100P_0402_50V8J

1UH +-30% 2.8A

1

Isat: 4 A DCR: 27mohm

VF = 0.5V

2

3

PD301 BAS40CW_SOT323-3

1

PC311

1

0.047U_0402_25V7K

1

2

PR306

2

BQ24725A_VCC

20

VCC

BQ24735RGRR_QFN20_3P5X3P5

ACDET

6

BQ24725A_ACDET

1

2

1

10_1206_1%

PR307

2

2.2_0603_5%

BQ24725A_LX

DH_CHG

BQ24725A_BST

18

17

19

HIDRV

PHASE

IOUT

SDA

7

8

9

BQ24725A_IOUT

PR320 0_0402_5%

1

2

BTST

SCL

2

1

2

BQ24725A_REGN

16

REGN

LODRV

BATDRV

ILIM

10

BQ24725A_ILIM

1

2

1

2

+19VB_C HG

1

PC303

2

10U_0805_25V6K

VF = 0.37V

PD302 RB751V-40_SOD323-2

DH_CH G

1

2

PC313

1U_0603_25V6K

DL_CHG

15

14

GND

13

SRP

12

SRN

BQ24725 A_BATDRV

11

1

PC320

PR317

2

100K_0402_1%

PC323

@

100P_0402_50V8J

1

PC305

2

EMI@

PR308

@

0_0603_5%

2

PR324

1

2

2200P_0402_25V7K

2

CSOP1

CSON1

0.1U_0603_16V7K

2

4

1

2

1

PC304

2

10U_0805_25V6K

Rds(on) = 30mohm max Vgs = 20V Vds = 30V ID = 7A (Ta=70 C)

1

PR313

10_0603_1%

1

PR314

6.8_0603_1%

1

316K_04 02_1%

0.01U_0402_25V7K

EC_SMB_CK 1 <2 9,34>

EC_SMB_DA 1 <2 9,34>

ADP_I <2 9,34>

PC306

@EMI@

PC319

0.1U_0402_25V6

+3VLP

PQ305

5

AON7506_DFN33-8-5

3

2

1

5

3

2

1

BQ24725 A_BATDRV

3.3UH_PCMB053T-3R3MS_5A_20%

BQ24725 A_LX

PQ306

1

PR312

2

4.7_1206_5%

AON7506_DFN33-8-5

1

2

PC318

680P_0402_50V7K

5*5* 3

PL302

@EMI@

PQ304 AON7506_DFN33-8-5

5

4

BQ24725A_BATDRV_1

1

2

PR305

4.12K_0603_1%

Support max charge 3.5A Power l oss: 0.245W CSR rating: 1W VSRP-VSRN spec < 81.28mV

PR311

0.01_1206_1%

1

2

CHG

2

CSOP1

1

PC316

2

0.1U_0402_25V6

1

2

3

1

PC307

2

0.01U_0402_50V7K

+17.4V _BATT

4

3

CSON1

1

2

PC314

2

PC317

0.1U_0402_25V6

1

PC324

PC315

2

10U_0805_25V6K

Close EC chip

Security Classification

Issued Date

THIS SHEET O F ENGINEE RING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D

DEPARTMENT EX CEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY B E USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY B E USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/02 2014/05/24

Compal Secret Data

Deci phered D ate

C

Compal Electronics, Inc.

Title

Size Document Number R ev

Dat e: Shee t

Compal Electronics, Inc.

CHARGER

Common Circuit

D

o f

35 44Monday, July 18, 2016

o f

35 44Monday, July 18, 2016

o f

35 44Monday, July 18, 2016

1

2

3

4

0.2

A

B

C

D

E

PR402

PR404

1

2

150K_0402_1%

PL404

499K_0402_1%

1

2

+19 VB

1

2

PC408

PC407

22U_0603_6.3V6M

Ipea k= 4. 834 A Imax =3 .38 4A Io cp =10 A

PC409

22U_0603_6.3V6M

1

2

PC420

22U_0603_6.3V6M

Ipea k= 7.7 4A Imax =5 .41 8A Io cp =10 A

+3V ALWP

PC410

22U_0603_6.3V6M

1

2

PC421

22U_0603_6.3V6M

PC423

PC422

22U_0603_6.3V6M

+3V ALWP

+5V ALWP

ENLDO_3V5V

PJ403

@

JUMP_43X79

1

2

1

2

LX_3V

6

7

8

9

10

ENLDO_3V5V

3V_EN

1

PC417

2

0.1U_0402_25V6

@EMI@

PR413

0_0402_5%

SPOK

PU401 SY8286BRAC_QFN20_3X3

2

3

4

5

IN

LX

GND

PG

NC

EN1

EN2

FF

12

11

13

14

3V_FB

PU402 SY8286CRAC_QFN20_3X3

5

LX_5V

6

LX

7

GND

8

GND

9

PG

10

NC

SPOK_R

1

@

2

ENLDO_3V5V

11

5V_EN

BST_3V

1

IN

BS

20

LX

19

LX

18

GND

17

LDO

16

NC

21

GND

OUT

NC

15

3.3V LDO 150mA~300mA

PC402 1000P_0402_25V8J

1

2

3

4

1

IN

EN2

12

EN1

13

FF

OUT

14

15

1

2

1000P_0402_25V8J

5V_FB

BS

GND

VCC

GND

LDO

LX

NC

PC427

PC413

1

@

0_0603_5%

1K_0402_5%

1

+19 VB

PL401

EMI@

HCB2012KF-121T50_0805

1

2

+19VB_3V

1

PC403

2

0.1U_0402_25V6

@EMI@

1

PC404

2

PC405

2200P_0402_50V7K

EMI@

10U_0805_25V6K

+3V ALWP

Check pull up resistor of SPOK at HW side

SPOK<29,39>

PJ404

@

JUMP_43X79

1

2

1

2

+19 VB

3

EC_ON<29>

MAINPW ON<29,31,34>

2

PL403

EMI@

HCB2012KF-121T50_0805

1

2

PR410

2.2K_0402_5%

1

PR411

@

0_0402_5%

1

2

1

PR412

1M_0402_1%

2

PR406

100K_0402_5%

+19V B_5V

1

PC414

2

@

10U_0805_25V6K

5V_EN

1

PC428

2

1

2

3V_EN<29>

+19VB_5V

1

PC415

PC416

2

10U_0805_25V6K

2200P_0402_50V7K

EMI@

4.7U_0402_6.3V6M

EN1 and EN2 dont't floating

PR401

PC401

1

2

1

PC411

4.7U_0603_6.3V6M

2

PR403

1

BST_5V

20

19

18

17

16

21

5V LDO 150 mA~300mA

4.7U_0603_6.3V6M

2

0.1U_0603_25V7K

+3V LP

2

PR408

@

0_0603_5%

1

2

LX_5V

PC419 4.7U_0603_6.3V6M

1

2

VL

PR407

1K_0402_5%

1

2

LX_3V

1.5UH_PC MB053T-1R5 MS_6A_20%

1

PR405

@EMI@

2

3V_SN

1

2

PC412

@EMI@

PC418

1

2

0.1U_0603_25V7K

5*5*3 Common part SH000016800

PL402

1

2

4.7_1206_5%

680P_0603_50V7K

5*5*3 Common part SH000016800

1.5UH_PC MB053T-1R5 MS_6A_20%

1

PR409

@EMI@

2

4.7_1206_5%

5V_SN

1

2

PC426

@EMI@

680P_0603_50V7K

schematic from A4WAS

@

1

2

PC424

22U_0603_6.3V6M

@

1

2

PC425

22U_0603_6.3V6M

PJ401

@

1

JUMP_43X118

PJ402

@

1

JUMP_43X118

+5V ALWP

PC429

22U_0603_6.3V6M

2

1

2

3

+3V ALW

+5V ALW

4

Secur ity Cla ssifica tion

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2015/10/ 02 2016/11/10

Compal Secret Data

Deciphere d Date

CompalElectronics,Inc.

Title

PWR-3.3VALWP/5VALWP

Size Document Number R ev

Custom

B5W1SM/BLA-D671P

Date : Sheet

D

Date : Sheet

E

of

36 44Monday, July 18, 2016

of

36 44Monday, July 18, 2016

of

36 44Monday, July 18, 2016

4

0.2

A

B

C

D

E

schematic from A4WAS IC change RT8207K

PJ503

@

JUMP_43X79

1

2

1

2

PL501

EMI@

1

+19VB

HCB2012KF-121T50_0805

1

2

+1.2VP

2

1

2

PC510

22U_0603_6.3V6M

1

2

PC511

PC512

22U_0603_6.3V6M

1

2

PC513

PC514

22U_0603_6.3V6M

+19VB_1.2VP

1

2

1UH_6.6A_20%_5X5X3_M

1

2

PC515

22U_0603_6.3V6M

+19VB_1.2V P

1

PC502

2

0.1U_0402_25V6

@EMI@

PL502

1

@EMI@

4.7_1206_5%

@EMI@

680P_0402_50V7K

PC503

EMI@

2200P_0402_50V7K

2

1

2

LX_1.2VP

PR504

PC518

PR502

16K_0402_1%

1

2

2.2_0603_5%

1

LG_1.2VP

PR503

2

PC509

1U_0402_10V6K

1

VDD_1.2VP

PR511

2.2_0402_1%

2

CS_1.2VP

2

1

2

1

PC504

PC505

2

10U_0805_25V6K

1

2

1

2

PQ503 AON7408L_DFN8-5

10U_0805_25V6K

5

0.1U_0603_25V7K

4

1

2

3

5

4

PQ502

1

2

3

SI7716ADN-T1-GE3_POWERPAK8-5

1

PC506

2

+5VALW

BST_1.2VP_R

PR505

5.1_0603_5%

1

PC517

1U_0402_10V6K

2

+5VALW

+19VB_1.2VP

SYSON<14, 29,32>

+3VALW

3

+5VALW

PR516

100K_0402_1%

SYSON_2V5#

D

DMN66D0LDW-7_SOT363-6

4.7U_0603_6.3V6M

5

G

1

2

6

PQ504A

2

1

SYSON<14,29,32>

4

PR515

@

0_0402_5%

2

G

S

1

SYSON_2V5#<32>

A

PC520

PQ504B

3

S

4

D

2

@

2

PJ505 JUMP_43X79

1

2

1

6.49K_0402_1%

VIN_2.5VALW

1

PR513

2

VREF_2.5VALW

1

PR512

2

20.5K_0402_1%

DMN66D0LDW-7_SOT363-6

B

1

2

PC522

0.1U_0402_16V7K

PU502

1

VIN

2

GND

3

VREF

4

VOUT

APL5336KAI-TRL_SOP8P8

+2.5VP

1

10U_0805_6.3V6M

2

+2. 5V P

8

NC

7

NC

6

VCNTL

5

NC

9

TP

PC524

Secu rity Cl assifica tion

Issued Da te

THIS SHEE T OF ENG INEERING DRAW ING I S THE P ROPRIETAR Y PRO PERTY O F CO MPAL ELE CTRONICS, INC. AND CON TAINS CON FIDENTIAL

AND TRA DE SE CRET INF ORMATION. THIS SHEET MAY NO T BE TRA NSFERED FRO M THE CU STODY O F THE COM PETENT DIVI SION OF R& D

DEPARTME NT EXC EPT AS AUTH ORIZED BY COMPAL ELE CTRONICS, INC . NE ITHER TH IS SHEE T NO R THE I NFORMATIO N IT CONTAINS

MAY BE USED BY O R DISCLO SED TO AN Y THIRD P ARTY WI THOUT PRI OR WR ITTEN CONSE NT OF COMP AL EL ECTRONICS, I NC.

@

1

1U_0402_6.3V6K

2

PJ504

2

1

2

JUMP_43X79

2015/1 0/02 2016/1 1/10

C

SM_PG_CTRL<8>

+5VALW

PC521

SUSP#<14,29,32,35>

Mode Level +0.6VSP VTTREF_1.2V S5 L off off S3 L off on S0 H on on

+2. 5V

Note: S3 - sleep ; S5 - power off

Comp al Secre t Data

Decipher ed Date

Pin19 need pull separate from +1.35VP. If you have +1.35V and +0 .675V sequence question, you can change from +1.35VP to +1.35VS.

BST_1.2VP

UG_1.2VP

LX_1.2VP

15

14

13

12

11

PR507 470K_0402_1%

1

PR501

2.2K_0402_5%

1

16

PHASE

LGATE

PGND

CS

RT8207PGQW_WQFN 20_3X3

VDDP

VDD

PGOOD

10

TON_1.2VP

2

PC501

0.1U_0402_10V7K

PR509

@

0_0402_5%

1

2

PR510

@

0_0402_5%

1

2

0.1U_0402_10V7K

17

PU501

9

19

20

18

21

VTT

BOOT

UGATE

S5

TON

8

EN_1.2VP

1

2

PAD

VTTGND

VTTSNS

GND

VTTREF

VDDQ

FB

6

FB_1.2VP

1

2

3

4

5

1

2

VTTREF_1.2VP

PR506

6.19K_0402_1%

1

PR508 10K_0402_1%

+1.2VP

VLDOIN

S3

7

EN_0.6VSP

+1.2VP

1

PC519

@

2

+0.6VSP

MOSFET: 3x3 DFN H/S Rds( on): 27mohm( Typ), 32mohm (Max) Idsm: 7.5A@Ta=25 C, 5.5A@Ta= 70C

L/S Rd s(on): 13mohm(T yp), 15.8mohm(Ma x) Idsm: 12A@Ta=25C , 10.5A@Ta= 70C

Choke: 7 x7x3 Rdc= 14mohm(Typ), 1 5mohm(M ax)

Switch ing Freque ncy: 538k Hz Ip eak = 7.5 A Io cp = Ip e a k* 1 . 2 A OVP: 110%~120% VFB=0.75 V, Vout=1. 365V MOSFET footp rint: SIS4 12DN

CompalElectronics,Inc.

Tit le

RT8207P

Size Docu ment N umber R e v

Custom

B5W1SM/BLA-D671P

Da te : Sh eet

D

Da te : Sh eet

0.6Volt +/- 5% TDC 0.7A Peak Current 1A

+1.2VP

+0.6VSP

1

PC507

2

10U_0603_6.3V6M

1

2

PC508

10U_0603_6.3V6M

PC516

0.033U_0402_16V7K

+1.2VP

E

+1.2V_VDDQ

+0.6VS_VT T

37 44Monday, July 18, 2016

2

Vout=0.75V* (1+Rup/Rdown)

=0.75*(1+(6.19/10)) =1.21V

PJ501

@

JUMP_43X118

1

PJ502

@

JUMP_43X39

1

2

3

4

0.2

o f

A

B

C

D

E

schematic from A4WAS

EN pin don't floating If have pull down resistor at HW side, pls delete PR702

PJ705

@

JUMP_43X79

1

+19VB

LDO_3V

1

PR607

@

0_0402_5%

2

ILMT_1VALW

1

PR609

@

0_0402_5%

2

The current limit is set to 6A, 8A or 12A when this pin is pull low, floating or pull high

2

1

2

PL601

EMI@

HCB2012KF-121T50_0805

1

2

+19VB_1VALW

1

PC605

PC604

2

EMI@

@EMI@

2200P_0402_50V7K

PR601

1M_0402_1%

PC602

PR605

@EMI@

4.7_1206_5%

1

1UH_6.6A_20%_5X5X3_M

1

FB = 0.6V

1

PC614 1U_0402_6.3V6K

2

PU601

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND

18

GND

11

EN

13

ILMT

15

BYP

SY8288RAC_QFN20_3X3

9

PG

BST_1VALW

1

BS

LX_1VALW

6

LX

19

LX

20

LX

FB_1VALW

14

FB

LDO_3V

17

VCC

10

NC

12

NC

16

NC

21

PAD

PR606

@

0_0603_5%

1

2

1

PC613

2.2U_0402_6.3V6M

2

Pin 7 BYP is for CS. Common NB can delete +3VALW and PC15

BST_1VALW_R

PC603

1

2

0.1U_0603_25V7K

+19VB_1VALW

1

PC606

2

0.1U_0402_25V6

10U_0805_25V6K

EN_1VALW

ILMT_1VALW

+3VALW

@EMI@

680P_0603_50V7K

SNUB_1VALW

1

2

1

PR610

20K_0402_1%

2

1

PR608

PC608

2

14K_0402_1%

330P_0402_50V7K

2

PL602

2

Ru p

Rdo w n

Vout=0.6V* (1+Rup/Rdo wn) =0.6* (1+( 14/20)) Vout=1.02V

PJ601

@

JUMP_43X118

1

2

+1.0VAL WP

1

2

+1.0VA LW_PRIM

+1.0VALWP

1

PC609

2

22U_0603_6.3V6M

PC610

22U_0603_6.3V6M

PC611

2

22U_0603_6.3V6M

Ipe ak =9 .5A Ima x= 6. 65A

1

PC612

2

22U_0603_6.3V6M

1

+

PC615

2

PC616

2

@

22U_0603_6.3V6M

220U_B2_4VM_R35M

+3VALW

2

PR603

@

10K_0402_1%

1

PR602

@

EN_1VALW

1

2

0_0402_5%

1

PC601

@

0.22U_0402_10V6K

2

+1.8VALW_PG <39>

1

2

3

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION O F R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2015/10/02 2016/11/10

Compal Secret Data

Deciphered Date

D

CompalElectronics,Inc.

Titl e

VCCP

Siz e

Docu men t Num ber R e v

C

B5W1SM/BLA-D671P

Da te : She et

E

38 44Monday, July 18, 2016

o f

3

4

0.2

A

B

C

D

E

schematic from A4WAS IC change to G971

1

+3VALW

1

PJ703

@

1

JUMP_43X79

VIN_1.8VALW

4.7U_0603_6.3V6K

2

3

2

VIN_1.8VALW

1

PC708

2

+1.8VALW_PG<38>

1

SPO K<2 9,36 >

PR708

@

0_0402_5%

2

PR710

1M_0402_1%

1

2

+3VALW

2

1

2

PR702

10K_0402_1%

EN_1.8VALW

PC710

@

0.1U_0402_16V7K

+3VALW

1

PC707

1U_0402_6.3V6K

2

6

PU702

7

POK

8

VEN

VIN

VPP

TPAD

VO

ADJ

GND

G971ADJF11U_SO8

1

VIN_1.8VALW

5

9

3

4

2

+1.8VALWP

1

Ru p

2

1

2

PR711

10K_0402_1%

1

2

PR709

12.7K_0402_1%

FB_1.8VS

Rdo w n

Vout=0.8V* (1+Rup/Rdo wn)

Vout=0.8V* (1+(12.7/10)) = 1.816V

PJ702

@

JUMP_43X79

1

2

1

2

+1.8VALW_PRIM

2

+1.8VALWP

PC709

1

PC711

0.01U_0402_25V7K

22U_0603_6.3V6M

2

3

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION O F R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2015/10/02 2016/11/10

Compal Secret Data

Deciphered Date

D

CompalElectronics,Inc.

Titl e

SY8032

Siz e

Docu men t Num ber R e v

C

B5W1SM/BLA-D671P

Da te : She et

E

39 44Monday, July 18, 2016

o f

4

0.2

A

B

C

D

E

schematic from A4WAS

PC802

0.01U_0402_25V7K

1

PR803 100_0402_1%

1

VCCSA_SENSE<14>

VSSSA_SENSE<14>

VCCGT_SENSE<16>

VSSGT_SENSE<16>

2

SWN_GT1

CSN_GT1<41>

SWN_GT1<41>

3

+VCC_S A

+VCC_ GT

PR825

73.2K_0603_1%

1

PR845

2.26K_0402_1%

2

THERM_ 220K 5% 0402

PR830

165K_0402_1%

1

PC821

2

0.1U_0402_25V6

2

1

PR809 100_0402_1%

1

2

PR810 100_0402_1%

1

100_0402_1%

pla c e clo s e to GT c hock

PH803

1

2

PR831

75K_0402_1%

1000P_0402_50V7K

+5VS

1

2

PC822

0.1U_0402_16V7K

PC817

2

PR815

2

PC818 56P_0402_50V8

2

1

2

1

PR868 0_0402_5%@

PH801

PR804

@

0_0402_5%

1

1000P_0402_50V7K

1

PR806

@

0_0402_5%

PR812

@

0_0402_5%

1

PR813

@

0_0402_5%

1

49.9_0402_1%

PC812

470P_0402_50V7K

PC814

15P_0402_50V8J

PR833

12.4K_0402_1%

2

1

@

1

0_0402_5%

2

PR844

1 0 0

度度度度

C

pla c e

+5VALW

clo s e

100K_0402_1%_NCP15WF104F03RC

to GT high side

PR817

1

PR864

61.9K_0402_1%

2

PC805

+5VS

1

VSNN_1b

2

PR811 20K_0402_1%

1

PC808

1000P_0402_50V7K

2

1

2

1

2

1

2

1

2

2200P_0402_50V7K

2

+19VB

1

2

PC827 1000P_0402_50V7K

VSPP_1b

1

VSNN_2ph

PR820

549_0402_1%

PR823

4.75K_0402_1%

PC816

1

PR801

1K_0402_1%

@

1

2_0402_1%

PR870

1

2_0402_1%

1U_0603_10V6K

PC803

1000P_0402_50V7K

1

PR805

1.8K_0402_1%

1

PR807

649_0402_1%

1

2

VSP_2ph

PR814

1K_0402_1%

1

2

3300P_0402_50V7-K

2

1

PR822 24.9K_0402_1%

2

1

2

PR850

2

1

PC831

2

VSP_1b

2

VSN_1b

2

PC807 2200P_0402_50V7K

VSN_2ph

2

PC810

1

2

PC813

49

470P_0402_50V7K

TAB

1

IOUT_2ph

2

DIFFOUT_2ph

3

FB_2ph

4

COMP_2ph

5

ILIM_2ph

6

CSCOMP_2ph

7

CSSUM_2ph

8

CSREF_2ph

9

CSP2_2ph

10

CSP1_2ph

11

TSENSE_2ph

12

VRMP

PC801

0.01U_0402_50V7K

1

PR853

2

33.2K_0402_1%

1

PR808

24K_0402_1%

2

47

48

VSN_2ph

VCC

14

13

PR854

24K_0402_1%

VSP_2ph

ROSC_COREGT

46

PSYS

RSOC_SAUS

15

1

2

44

45

VSP_1b

PU801

NCP81208

PWM1_2ph

17

16

39

43

41

42

40

ILIM_1b

CSP_1b

VSN_1b

CSN_1b

COMP_1b

ADDR_VBOOT

ICCMAX_1b

ICCMAX_1a

ICCMAX_2ph

PWM2_2ph

21

20

19

18

22

1

PR856

2

48.7K_0402_1%

1

2

1

2

1

PC806

PR819

66.5K_0402_1%

2

PC811 470P_0402_50V7K

1

37

38

EN

IOUT_1b

VR_RDY

PWM_1b

DRVON

SCLK

ALERT#

SDIO

VR_HOT#

IOUT_1a

CSP_1a

CSN_1a

ILIM_1a

COMP_1a

VSN_1a

PWM_1a

TSENSE_1ph

VSP_1a

23

24

VSP_1a

1000P_0402_50V7K

1

PR857

2

100K_0402_1%

PR802

1.5K_0402_1%

1

2

PC804 15P_0402_50V8J

2

1000P_0402_50V7K

PC809

1

2

PR863

@

0_0402_5%

2

36

35

34

SCLK

33

ALERT#

32

SDIO

31

30

29

28

27

26

25

VSN_1a

PR846 2.43K_0402_1%

1

2

PC830

PWM _1a <4 1>

1

PR858

PR859

2

15.8K_0402_1%

1

PC833

2

@

0.01U_0402_25V7K

4700P_0402_25V7K

VR_O N <2 9,3 2>

PWM _1b <4 1>

DR VON <41>

PR834

49.9_0402_1%

1

PR860

@

1

0_0402_5%

PR862

1

10_0402_1%

PR869 100_0402_1%

PC824

3300P_0402_50V7-K

1

2

1

PR843

715_0402_1%

2

1

PR867 2.43K_0402_1%

10K_0402_1%

1

PH802 100K_0402_1%_NCP15WF104F03RC

pla c e clo s e

2

to SA c hock

1

PR816

15K_0402_1%

2

PR818

8.25K_0603_1%

1

2

PR824 45.3_0402_1%

@

2

1

2

PR865

@

0_0402_5%

2

1

PC828 1000P_0402_50V7K

2

1

2

PR847

@

0_0402_5%

1

PR852

@

0_0402_5%

2

PC832

1000P_0402_50V7K

CSN _1b < 41>

1

SW_ 1b < 41>

+1.0V_VC CST

close to the longer distance phase(81208 or 81210) Alert ,D a ta , Cl k .

1

2

PR866 100_0402_1%

PR826 110_0402_1%

SOC _S VID_ CLK <16>

SOC _S VID _AL ER T#_ R <1 6>

SOC _SV ID_D AT <16>

PR840 100_0402_1%

2

PR851 100_0402_1%

2

1

2

61.9K_0402_1%

PR855

+3VS

PR821 10K_0402_1%

1

PC815

PR828

@

2

0.1U_0402_16V7K

110_0402_1%

15P_0402_50V8J

1

VSSSENSE <16>

VCCSENSE <16>

1

+VCC_ CORE

1

PH805 100K_0402_1%_NCP15WF104F03RC

pla c e

2

clo s e to VCC_CORE high side

VR_ HO T# < 29>

PC819

470P_0402_50V7K

1

PR836

66.5K_0402_1%

2

1

PC829

2

VR_ PW RGD <29>

2

1

PC825

2

1

4700P_0402_25V7K

PR848

1.62K_0402_1%

2

PR829

8.25K_0603_1%

1

PC820

2

PR842

1

0.033U_0402_16V7K

1

2

34.8K_0402_1%

2

PR835

15K_0402_1%

1

PC834

@

2

2200P_0402_25V7K

PC826

1000P_0402_50V7K

SW_1a <41>

2

pla c e clo s e to L1

1

PH804 100K_0402_1%_NCP15WF104F03RC

2

CSN_1a <41>

1

2

3

PWM 1_2 ph <41 >

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION O F R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2015/10/02 2016/11/10

Compal Secret Data

Deciphered Date

D

CompalElectronics,Inc.

Titl e

IMVP8,NCP81206

Siz e

Docu men t Num ber R e v

C

B5W1SM/BLA-D671P

Da te : She et

E

40 44Monday, July 18, 2016

o f

4

0.2

A

+19VB_C PU

1

PWM_1a<40>

DRVON<40>

+5VS

1

2

3

PWM_1b<40>

DRVON

+5VS

1

2

4

PR9001

2.2_0603_5%

1

PU9001

NCP81253MNTBG_DFN8_2X2

1

BST

DRVH

2

PWM

3

EN

4

VCC

PAD

9

PC9049

4.7U_0603_6.3V6K

PR9013

2.2_0603_5%

1

PU9004

NCP81253MNTBG_DFN8_2X2

1

BST

DRVH

2

PWM

3

EN

4

VCC

PAD

9

PC9154

4.7U_0603_6.3V6K

GND

DRVL

GND

DRVL

SW

PC9001

0.22U_0603_16V7K

2

1

HG_VCORE

8

SW_VCORE

7

6

5

LG_VCORE

PC9119

0.22U_0603_16V7K

1

2

8

7

6

5

2

0_0603_5%

1

5

4

1

2

3

2

HG_SA

10

SW _S A

LG_SA

@EMI@

PR9015

PQ9001

AON6794_DFN5X6-8-5

4

D1

5

2

LG_VCORE

3

D1

S2

6

4

D1

S2

5

PQ9002

1

2

3

5

4

2

3

InputC apaci tor: 10uF_0 805_X 5R_2 5V

AON79 34 Rds(on)=12.4~15.8m ohm

PQ9008

2

1

AON7934_DFN3X3A8-10

D1

G1

9

D2/S1

S2

G2

7

8

B

InputC apaci tor: 10uF_0 805_X 5R_2 5V

1

PC9015

2

PC9002

PC9014

10U_0805_25V6K

AON6428L_DFN8-5

PQ9003

@

1

2

PC9115

10U_0805_25V6K

0.1U_0402_25V6

@EMI@

(Common Part) SH000011H00 7*7*4

PL9001 0.22UH 20% FDUE0640J -H 25A

1

PR9002

4.7_1206_5%

2

@EMI@

AON6794_DFN5X6-8-5

1

PC9073

2

680P_0603_50V7K

@EMI@

1

PC9117

2

PC9116

10U_0805_25V6K

@EMI@

DCR=6.2m ohm +-5% Common part SH000015M00

SW_SA

1

PR9014

4.7_1206_5%

2

@EMI@

1

PC9155

2

680P_0603_50V7K

@EMI@

PC9208

@EMI@

0.1U_0402_25V6

4

3

100P_0402_25V8K

@

JUMP_43X79

1

2

4

3

1

+

PC9004

33U_25V_M

2

1

PC9210

@

2

PJ903

2

+19VB

1

2

1

PC9003

2

EMI@

2200P_0402_50V7K

1

2

DCR=0.98m ohm +-5% Common part SH000011H00

PWM1_2ph<40>

+19VB_SA

1

PC9118

2

EMI@

2200P_0402_50V7K

0.1U_0402_25V6

PL9006

1

2

0.47UH_MMD05CZR47M_12A_20%

PJ901

@

JUMP_43X79

1

2

1

2

PL9002

EMI@

HCB2012KF-121T50_0805

1

2

+VCC_ CORE

CSN_1a <40>

SW_1a <40>

DRVON

+VCC_S A

CSN_1b <40>

SW_1b <40>

C

+19VB

change PL9002, PL9003 SM01000C000 to comm part SM01000P200

NCP81151MNTBG_DFN8_2X2

1

+5VS

@

PC9209

100P_0402_25V8K

2

1

2

2.2_0603_5%

1

PU9003

1

BST

2

PWM

3

EN

4

VCC

PC9090

4.7U_0603_6.3V6K

PR9005

0.22U_0603_16V7K

2

FLAG

DRVH

SW

GND

DRVL

PC9083

1

9

8

7

6

5

2

HG1_GT

SW1_GT

LG1_GT

D

E

schematic from A4WAS

VCC : Imax=21A Ipeak=29 A Iocp=37.7A

VCC G T: Imax=18A Ipeak=31A Iocp=40A

VCC S A: Imax=4A Ipeak=4.5A Iocp=10A

PJ902

@

JUMP_43X79

1

2

1

2

PL9007

EMI@

1

+

PC9187

5

4

PQ9005

AON6428L_DFN8-5

1

2

3

LG1_GT

5

1

PQ9007

4

@

2

1

2

3

1

AON6794_DFN5X6-8-5

2

5

PQ9009

4

1

2

3

AON6794_DFN5X6-8-5

1

@

33U_25V_M

PC9085

2

0.1U_0402_25V6

@EMI@

(Common Part) SH000011H00 7*7*4

PL9005 0.22UH 20% FDUE0640J -H 25A

1

2

PR9010

4.7_1206_5%

@EMI@

PC9092

680P_0603_50V7K

@EMI@

1

PC9086

2

PC9087

EMI@

2200P_0402_50V7K

4

3

PR9009 10_0402_1%

1

+19VB_CPU_GT

1

2

PC9088

PC9206

10U_0805_25V6K

+VCC_GT

DCR=0.98m ohm +-5% Common part SH000011H00

2

1

2

PC9207

10U_0805_25V6K

+VCC_ GT

CSN_GT1 <40>

SWN_GT1 <40>

HCB2012KF-121T50_0805

1

2

10U_0805_25V6K

1

InputC apaci tor: 10uF_0 805_X 5R_2 5V

+19VB

2

1

2

3

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION O F R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2015/10/02 2016/11/10

Compal Secret Data

Deciphered Date

D

CompalElectronics,Inc.

Titl e

PowerTrain

Siz e

Docu men t Num ber R e v

C

B5W1SM/BLA-D671P

Da te : She et

E

41 44Monday, July 18, 2016

0.2

o f

1

2

3

4

0.2

o f

42 44Monday, July 18, 2016

E

schematic from A4WAS

+VCC_S A

PC9125 22U_0603_6.3V6M

+VCC_SA

2

1

PC9124 22U_0603_6.3V6M

2

1

PC9123 22U_0603_6.3V6M

2

1

PC9121

@

22U_0603_6.3V6M

2

1

PC9120

@

22U_0603_6.3V6M

2

1

@

PC9136

22U_0603_6.3V6M

2

1

D

PC9104 22U_0603_6.3V6M

+VCC_GT

2

1

PC9103

+VCC_ GT

22U_0603_6.3V6M

2

1

PC9102 22U_0603_6.3V6M

2

1

PC9101 22U_0603_6.3V6M

2

1

C

PC9100 22U_0603_6.3V6M

2

1

PC9099 22U_0603_6.3V6M

2

1

PC9098 22U_0603_6.3V6M

2

1

PC9097

@

22U_0603_6.3V6M

2

1

PC9096 22U_0603_6.3V6M

2

1

PC9095 22U_0603_6.3V6M

2

1

PC9140 22U_0603_6.3V6M

1

PC9139 22U_0603_6.3V6M

1

PC9138 22U_0603_6.3V6M

1

PC9137 22U_0603_6.3V6M

1

PC9203 22U_0603_6.3V6M

1

PC9204 22U_0603_6.3V6M

1

PC9114

@

22U_0603_6.3V6M

2

1

PC9112

@

22U_0603_6.3V6M

2

1

PC9111 22U_0603_6.3V6M

2

1

PC9110 22U_0603_6.3V6M

2

1

PC9109 22U_0603_6.3V6M

2

1

PC9108

@

22U_0603_6.3V6M

2

1

PC9107 22U_0603_6.3V6M

2

1

PC9130

@

22U_0603_6.3V6M

2

1

PC9129 22U_0603_6.3V6M

2

1

PC9126 22U_0603_6.3V6M

2

1

2

PC9162

1U_0201_4V6M

1

PC9161

1U_0201_4V6M

1

PC9160

1U_0201_4V6M

1

PC9159

1U_0201_4V6M

1

PC9158

1U_0201_4V6M

1

PC9157

1U_0201_4V6M

1

PC9156

1U_0201_4V6M

1

PC9135 22U_0603_6.3V6M

2

1

PC9134

@

22U_0603_6.3V6M

2

1

PC9133 22U_0603_6.3V6M

2

1

PC9163 22U_0603_6.3V6M

1

PC9167 22U_0603_6.3V6M

1

PC9165 22U_0603_6.3V6M

1

PC9168 22U_0603_6.3V6M

1

PC9170 22U_0603_6.3V6M

1

PC9171 22U_0603_6.3V6M

1

PC9169 22U_0603_6.3V6M

1

2

SA

pop:

22uF_0603*9

1uF_0201*7

unpop:

2

PC9188 22U_0603_6.3V6M

2

1

PC9189 22U_0603_6.3V6M

2

1

PC9190 22U_0603_6.3V6M

2

1

PC9191 22U_0603_6.3V6M

2

1

PC9194 22U_0603_6.3V6M

2

1

PC9195 22U_0603_6.3V6M

2

1

PC9186

@

220U_D2 SX_2VY_R9M

+

2

1

PC9093

@

220U_D2 SX_2VY_R9M

+

2

1

+

2

1

SGA20 221D4 0

22uF_0603*3

PC9153

0.47U_0201_4V6M

2

1

PC9152

1U_0201_4V6M

2

1

PC9151

0.47U_0201_4V6M

2

1

PC9176

0.47U_0201_4V6M

2

1

PC9149

1U_0201_4V6M

2

1

PC9148

1U_0201_4V6M

2

1

PC9147

1U_0201_4V6M

2

1

PC9146

@

1U_0201_4V6M

2

1

PC9145

1U_0201_4V6M

2

1

PC9144

0.47U_0201_4V6M

2

1

PC9143

1U_0201_4V6M

1

PC9142

1U_0201_4V6M

1

PC9183

1U_0201_4V6M

1

PC9181

1U_0201_4V6M

1

Compal Secret Data

2

330uF*1

22uF_0603*30

1uF_0201*9

0.47uF_0201*4

unpop:

220_D2*2

22uF_0603*6

1uF_0201*1