Compal LA-E051P Schematics Rev1.0

A

1 1

B

C

D

E

Compal Confidential

C1PR2 MB Schematic Document

2 2

LA-E051P

(Eagle 21")

Rev: 1.0

3 3

ZZZ

DA@

4 4

PCB 1SJ LA-E051P REV1 MB

DAC00006010

A

B

2017-01-09

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Cover Sheet

Cover Sheet

Cover Sheet

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1 103Monday, January 09, 2017

1 103Monday, January 09, 2017

1 103Monday, January 09, 2017

E

1.0

1.0

1.0

A

eDP

eDP Panel
Conn.

1 1

HDMI 2.0
Conn.

Display Port
Conn. x2

TYPE-C

2 2

3 3

Conn.

4 lane

page 65

HDMI
4 lane

page 66

DP
4 lane x 2

page 67

DP/USB3.1 Gen2

page 70

DP/USB3.1

M.2 WLAN
Dual Band

page 31

802.11 ac/agn

PCIe x4 PCIe x4

DDI

Nvidia N17E-G3

with GDDR5X*8

page 41~52

Nvidia N17E-G3

with GDDR5X*8

page 53~64

PCIe x1PCIe x2

LAN(GbE)

Killer Ethernet

E2500

page 30

RJ45

Conn.

page 30

M.2 SSDM.2 SSDM.2 SSD

page 28 page 28 page 29 page 29 page 27

SUB/B

USB 3.0/B

IO/B

4 4

PWR BTN/B

Marco Key/B

page 32

page 32 page 33

page 35

page 35

FAN LED/B

page 35

POGO/B

Light Bar Left/B

Light Bar Right/B

LOGO LED/B

A

page 35

page 35

page 35

RTC CKT.

Power On/Off CKT.

DC/DC Interface CKT.

Power Circuit DC/DC

page 23

page 41

page 25~26

page 72~97

MIO

DP
4 lane

Thunderbolt
AR4C

Power delivery

TPS65982

SATA3.0 SATA3.0SATA3.0 SATA3.0

B

SLI

Master GPU

Slave GPU

page 68,69

page 70

Card Reader

RTS5227

SD Conn.(IO/B)

B

PEG X8 (0~7)
8GT/s

PEG X8 (8~15)
8GT/s

PCIe x4

PCIe x1

page 32

SATA HDDM.2 SSD

Conn.Conn.Conn.Conn.Conn.

Cable Type

SATA3.0

6.0 Gb/s

SATA3.0

Kabylake H PROCESSOR

BGA1440

(42X28) (KBL-H_4+2)

Processor

PCIe

PCIe

Kabylake PCH - H
FCBGA(23X23)

837pin FCBGA

PCIe

LPC/eSPI BUS

CLK=24MHz

ENE

KB9022

page 38

C

Fan Control x5

Memory BUS

Dual Channel

1.2V DDR4 1866/2133

page 06~13

X4 DMI

USB Bus

CM238

HD Audio

3.3V 24MHz

page 08~24

SPI

SPI ROM

16M

page 19

TPM

page 40 page 40

C

G-Sensor
LIS3DHTR

D

page 39

260pin DDR4-SO-DIMM X2

260pin DDR4-SO-DIMM X2

USB3.0 USB3.0

page 32 page 32 page 32 page 32

USB3.0 USB3.0 USB3.0 USB3.0

FHD CAM Eye Tracker

Conn. Conn.

USB2.0 USB2.0 USB2.0

HDA Codec Speaker, Woofer

ALC299

page 36 page 37 page 36,37

USB3.0

Conn.(IO/B)Conn.(IO/B)

Conn.(USB/B)

Touch Screen

page 34page 65 page 65 page 33 page 33 page 31

USB/I2C

Ext Amp.

ALC1006

Head Phone

Amp.

MIC Jack

Conn.

SSSeeecccuuurrriiitttyyy CCClllaaassssssiiifffiiicccaaatttiiiooon

TTTHHHIIISSS SSSHHHEEEEEETTT OOOFFF EEENNNGGGIIINNNEEEEEERRRIIINNNGGG DDDRRRAAAWWWIIINNNGGG IIISSS TTTHHHEEE PPPRRROOOPPPRRRIIIEEETTTAAARRRYYY PPPRRROOOPPPEEERRRTTTYYY OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... AAANNNDDD CCCOOONNNTTTAAAIIINNNSSS CCCOOONNNFFFIIIDDDEEENNNTTTIIIAAALLL
AAANNNDDD TTTRRRAAADDDEEE SSSEEECCCRRREEETTT IIINNNFFFOOORRRMMMAAATTTIIIOOONNN...TTTHHHIIISSS SSSHHHEEEEEETTT MMMAAAYYY NNNOOOTTT BBBEEE TTTRRRAAANNNSSSFFFEEERRREEEDDD FFFRRROOOMMM TTTHHHEEE CCCUUUSSSTTTOOODDDYYY OOOFFF TTTHHHEEE CCCOOOMMMPPPEEETTTEEENNNTTT DDDIIIVVVIIISSSIIIOOONNN OOOFFF RRR&&&DDD
DDDEEEPPPAAARRRTTTMMMEEENNNTTT EEEXXXCCCEEEPPPTTT AAASSS AAAUUUTTTHHHOOORRRIIIZZZEEEDDD BBBYYY CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,,IIINNNCCC... NNNEEEIIITTTHHHEEERRR TTTHHHIIISSS SSSHHHEEEEEETTT NNNOOORRR TTTHHHEEE IIINNNFFFOOORRRMMMAAATTTIIIOOONNN IIITTT CCCOOONNNTTTAAAIIINNNSSS
MMMAAAYYY BBBEEEUUUSSSEEEDDD BBBYYY OOORRR DDDIIISSSCCCLLLOOOSSSEEEDDD TTTOOO AAANNNYYY TTTHHHIIIRRRDDD PPPAAARRRTTTYYY WWW IIITTTHHHOOOUUUTTT PPPRRRIIIOOORRR WWWRRRIIITTTTTTEEENNN CCCOOONNNSSSEEENNNTTT OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, III NNNCCC...

IIIssussussueeeddd DDDaaattteee

nn

222000111666///000222///000111 222000111777///111222///333111

CCCooommmpppaaalll SSSeeecccrrreeettt DDDaaatttaaa

D

USB2.0

Conn.

Head Phone

Jack
Conn.

ON IO/B

DDDeeecicicippphhheeerrreeeddd DDDaaattteee

page 14,15

page 16,17

Offline USB Charger

USB3.0

Conn.(USB/B)

Key Board

page 32

E

POGO

Conn.Conn.

Touch Pad

USB2.0 USB2.0

CCCooompmpmpaaalll EEEllleeeccctttrororonnniiicccs,s,s, InInInccc...

TTTiiitttllleee

SSSiiizzzeee DDDooocucucumememennnttt NNNuuumbmbmb eeerrr RRReeevvv

CCCuuussstttooo mmm

DDDaaattt eee::: SSShhheeeeeettt ooo fff

BlBlBloooccckkk DDDiiiaaagggrrraaammmsss

C1C1C1PPPR2R2R2 LLLA-A-A-E0E0E0555111PPP

E

M.2

Blue Tooth

111...000

222 111000333MMMooonnndddaaayyy,,, JJJaaannnuuuaaarrryyy 000999,,, 222000111777

A

B

C

D

E

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

1 1

2 2

I2C Address Table

I2C_0 (+3VS) N/C

I2C_1 (+3VALW)

3 3

100K +/- 5%Ra

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

0
12K +/- 1% 0.347 V 0.345 V 0.360 V
15K +/- 1%
20K +/- 1%
27K +/- 1%
33K +/- 1%
43K +/- 1%
56K +/- 1%
75K +/- 1%
100K +/- 1%
130K +/- 1%
160K +/- 1%
200K +/- 1%
240K +/- 1%
270K +/- 1%
330K +/- 1%
430K +/- 1%
560K +/- 1%
750K +/- 1%

NC

BUS

Rb V min

BID

0.423 V 0.430 V 0.438 V

1.398 V

1.634 V

1.849 V

2.015 V

2.185 V

2.316 V

2.395 V

2.521 V

2.667 V

2.791 V

2.905 V

3.000 V

Device

V typ

BID

0.000 V

1.414 V

1.650 V

1.865 V

2.031 V

2.200 V

2.329 V

2.408 V

2.533 V

2.677 V

2.800 V

2.912 V

3.000 V

Address(7 bit)

N/C
DIMM1

PCH_SMBCLK

(+3VS)

EC_SMB_CK1
(+3VLP)

EC_SMB_CK3
(+3VALW)

EC_SMB_CK2

(+3VS)

DIMM2
DIMM3
DIMM4
LIS3DHTR(G-sensor)
BQ24780 (Charger IC)

BATTERY PACK
PD(TPS65982)

9116 (LED driver, M/B)

5
59116 (LED driver, USB/B)

N17E-G3 (Master)
N17E-G3 (Slave)

0x30
0x12
0x16
0x00
0xC0
0xC2
0x9E

0x9C
AMP for SPK(ALC1006) 0x24
AMP for Woofer(ALC1006) 0x26
HP AMP (SV3S700)

External Thermal Sensor

0xE4

0x4D

V

max

BID

0.300 V

1.430 V

1.667 V

1.881 V

2.046 V

2.215 V

2.343 V

2.421 V

2.544 V

2.687 V

2.808 V

2.919 V

Address(8bit)

Write Read

EC AD

0x00 - 0x13
0x14 - 0x1E
0x1F - 0x25
0x26 - 0x300.541 V 0.550 V 0.559 V
0x31 - 0x3A0.691 V 0.702 V 0.713 V
0x3B - 0x450.807 V 0.819 V 0.831 V
0x46 - 0x540.978 V 0.992 V 1.006 V
0x55 - 0x641.169 V 1.185 V 1.200 V
0x65 - 0x76
0x77 - 0x87
0x88 - 0x96
0x97 - 0xA4
0xA5 - 0xAF
0xB0 - 0xB7
0xB8 - 0xBF
0xC0 - 0xC9
0xCA - 0xD4
0xD5 - 0xDD
0xDE - 0xF0
0xF1 - 0xFF

43 level BOM table

431A54BOL01
431A54BOL02 SMT MB AE051 C1PR2 G3 QL3X 2.4G HDMI
431A54BOL03 SMT MB AE051 C1PR2 G3 QLM4 2.9G HDMI QLM4@/QLF5@/CAM@/TBT@/TOBII@/CMC@/DA@
431A54BOL04 SMT MB AE051 C1PR2 I7-7820HK 2.9G HDMI SR32P@/SR30U@/CAM@/TBT@/TOBII@/CMC@/DA@

SMT MB AE051 C1PR2 G3 QL2X 2.7G HDMI QL2X@/QJGE@/CAM@/TBT@/TOBII@/CMC@/DA@

QL3X@/QJGE@/CAM@/TBT@/TOBII@/CMC@/DA@

BOM Structure43 Level Description

Power State

STATE

S0 (Full ON) ON ON ON ONHIGH HIGH HIGH

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

LOW HIGH

BOM Structure Table

BOM Option Table

Item BOM Structure

Unpop @

Connector

EMC requirement depop

For EYE Tracker TOBII@
For Alpine Ridge TBT@
For HD camera power

For Intel CMC debug

TPM TPM@
For G-Sensor GSEN@

ESPI MODE for EC ESPI@
For PCB DA PN
HDMI logo P/N
For PCH

For CPU

CONN@
EMC@EMC requirement
XEMC@

CAM@

CMC@

DA@
45@
QJGE@,QLF5@,

SR30U@

QL3X@,QL2X@
QLM4@,SR32P@

ONONON

HIGH

LOWLOW

HIGH

OFF

ON

OFFLOW LOW LOW

OFF

OFF

OFF

OFF

OFF

OFF

Voltage Rails

Power Plane

+RTCVCC

+19V_VIN

+17.4V_BATT Battery power supply
+19VB

+3VLP
+5VALW
+3VALW System +3VALW always on power rail
+3VALW_DSW +3VALW power for PCH DSW rails
+3VALW_PCH_PRIM
+3VALW_SPI
+1.0VALW +1.0V Always power rail

+1.0V_VCCST

+5VS System +5V power rail
+3VS

+1.0VS_VCCSTG +1.0VALW_PRIM Gated version of VCCST
+0.6VS_VTT DDR +0.675VS power rail for DDR terminator .

+VCC_CORE
+VCC_GT
+VCCIO

+VCC_SA

+3VSDGPU
+1.8VSDGPU_AON

+NVVDD1
+NVVDD2

+1.35VSDGPU +1.5VS power rail for GPU

+1.0VSDGPU

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Description
RTC Battery Power
Adapter power supply

AC or battery power rail for power circuit.
+19VB to +3VLP power rail for suspend power

+5V Always power rail

+3VALW power for PCH power rails

+3VALW_PRIM supply for the SPI IO

DDR IV +1.2V power rail+1.2V_VDDQ
Sustain voltage for processor in Standby modes

System +3V power rail

Core voltage for CPU
Sliced graphics power rail
CPU IO power rail

System Agent power rail

+3VS power rail for GPU circuit
+1.8VALW power rail for GPU(AON rails)
+1.8VS power rail for GPU GC6+1.8VSDGPU_MAIN
Core voltage for VGA
Core voltage for VGA

+1.05VS power rail for GPU

NV name COMPAL name

NVVDD

FDVDD
FBVDDQ

VPP

IFP_IOVDD
IFPx_PLLVDD
PEX_DVDD

/

PEX_HVDD

PEX_PLL_HVDD
FBx_PLL_AVDD
GPCPLL_AVDDx/Core_PLLVDD
VID_PLLVDD

4 4

SP_PLLVDD

1V8_MAIN +1.8VSDGPU_MAIN

1V8_AON

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

PCB Revision

0.1

0.2

0.3

1.0

+NVVDD1
+NVVDD2NVVDDS

+1.35VSDGPU
+1.35VSDGPU

+1.8VSDGPU_AON

+1.0VSDGPU
+1.8VSDGPU_MAIN
+1.0VSDGPU
+1.8VSDGPU_MAIN
+1.8VSDGPU_MAIN
+1.8VSDGPU_MAIN
+1.8VSDGPU_MAIN
+1.8VSDGPU_MAIN

+1.8VSDGPU_AON

S0

ON

N/A N/A N/A

N/A

ON
ON
ON
ON
ON

ON
ON
ON ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON

ON

S4

S3

ON ON

ON

N/A

N/A

N/A N/A

N/A

ON ON

ON

ON ON

ON

ON

ON

ON ON

ON
ON
ON ON ONON
ON

ON

OFF

ON

OFF
OFF

OFF
OFF OFF
OFF OFF OFF

OFF

OFF

OFF

OFF

OFF

OFF
OFF OFF OFF

OFF

OFF

OFF OFF

OFF

OFF OFF
OFF
OFF OFF

OFFOFF
OFF OFF OFF
OFF OFF OFF

S5

N/AN/AN/A

ON*

ON*ON

ON

OFF
OFF
OFF
OFF

OFF
OFF
OFF

OFFOFF

OFFOFF
OFF
OFF

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Notes List

Notes List

Notes List

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

E

3 103Monday, January 09, 2017

3 103Monday, January 09, 2017

3 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

JUMP
(PJ703)

+VCCIOP_EN

JUMP
(PJ701)

JUMP
(PJ506)

D D

C C

SM_PG_CTRL

JUMP

(PJ1301 ,PJ13 02)

JUMP

(PJ1901 ,PJ19 02)

EN_1VGAP

JUMP
(PJ1601 )

EN_1VGAPS

JUMP
(PJ2402 )

5V_EN
3V_EN

JUMP
(PJ401)

ADAPTER

CHARGER

B+

BATTERY

B B

EN_1VALW

JUMP
(PJ601)

SUSP#

JUMP
(PJ2201 )

A A

+CPU_B+

SYSON

TPS51225CRUKR
(PU401)

SY8286RAC
(PU2201)

DRON

SY8286RAC
(PU701)

RT8207PGQW
(PU501)

0 ohm
(PR1301 )

0 ohm
(PR1901 )

SY8288RAC
(PU1601)

SY8286RAC
(PU2405)

SY8288RAC
(PU601)

NCP81151MNT BG
(PU901,PU903,PU904,PU9 05)

JUMP
(

PJ704)

+VCCIOP

+1.2VP

+0.6VSP

GPU1_B+

GPU2_B+

+1.0VS_VGAP +1.0VS DGPU

+1.0VS_VGAP_S

+5VALWP

+3VALWP

+1.0VALWP +1.0VALW

+1.8VSP +1.8VS

SA_B+

JUMP
(PJ2202 )

DRON

JUMP
(PJ702)

JUMP

(PJ501, PJ50 2)

JUMP
(PJ503)

0 ohm
(PR1302 )

JUMP
(PJ1401 )

JUMP
(PJ1701 )

0 ohm
(PR1902 )

JUMP
(PJ2001 )

JUMP
(PJ2301 )

JUMP
(PJ1602 )

JUMP
(PJ2303 )

JUMP

(PJP404 ,PJP4 05)

JUMP

(PJP402 ,PJP4 03)

JUMP
(PJ602)

NCP81253MNT BG
(PU902)

+VCCIO

+0.6VS_VTT

0 ohm
(PR1402 )

1.35VSDGPU_EN

0 ohm
(PR2002 )

1.35VSDGPU_EN_S

+VCCCORE

+1.2V_VDDQ

NVVDD1_B+

RT8812AGQW
(PU1701)

NVVDD1_S_B+

RT8812AGQW
(PU2301)

+1.0VSDGPU_ S

+5VALW

+3VALW

R-Short
(RA71)

R-Short
(RA70)

R-Short
(RA56)

1V8_AON_EN

1V8_AON_EN_S

NVVDD1_EN

NVVDD2_B+

NVVDD1_EN_S

NVVDD2_S_B+

FBMA-L11
(LH1)

FBMA-L11
(LH2)

FBMA-L11
(LH3)

0 ohm
(RH113 )

0 ohm
(RH86)

0 ohm
(RH138 )

0 ohm
(RH140 )

0 ohm
(RH141 )

SYSON

SUSP#

AOZ1331
(UG12)

AOZ1331
(UG30)

+VCCSA

0 ohm
(RC41)

0 ohm
(RC42)

UP9511PQGJ
(PU1201)

NVVDD2_EN

+1.35VS_VGAP

UP9511PQGJ
(PU1801)

NVVDD2_EN_S

+1.35VS_VGAP_S

USBKB_EN

SUSP#

FAN_EN

TOBII_EN

POGO_EN

CAM_EN

0 ohm
(RH135 )

0 ohm
(RH89)

0 ohm
(RH136 )

R-Short
(R315)

0 ohm
(R312)

SYSON

WLAN_PW R_EN

LAN_PWR _EN

LBPWR_EN

SUSP#

SUSP#

TPS22961DNYR
(U40)

TPS22961DNYR
(U42)

+1.8VS_AVDD_AMP

+1.8VS_DVDD_AMP

+1.8VS_AVDD

+VDDQ_CLK

+1.2V_VCCPLL_O C

+NVVDD1

NCP81278MNT XG
(PU1401)

+NVVDD1_S

NCP81278MNT XG
(PU2001)

SY6288C20A AC
(U12)

JUMP
(J29)

AOZ1331
(U41)

RT8525DGQW
(PU2403)

SY6288C20A AC
(U19)

SY6288C20A AC
(U13)

SY6288C20A AC
(U18)

+3VALW_DSW

+3VALW_PCH_PRIM

+3VALW_HDA

+3VALW_PD

+3.3V_TBT_SX

SY8003ADFC
(PU502)

SY6288C20A AC
(U9)

SY6288C20A AC
(UL3)

SY6288C20A AC

(UE3)

AOZ1331
(U43)

AOZ1331
(U41)

JUMP
(J17)

JUMP
(J27)

JUMP
(J16)

+1.0VALW_AMPHYPLL

+1.0VALW_AUSB_AZPLL

+1.0VALW_VCCCLK5

+1.0VALW_MPHY

+1.0VALW_PRIM

+1.0VALW_VCCCLK

+1.0VALW_PRIMAL22

+1.0VALW_PRIMAD15

+1.0V_VCCST_OUT

+1.0VS_VCCSTG_O UT

+1.8VSDGPU_AON

+1.8VSDGPU_AON_S

+NVVDD2

JUMP

(PJP170 1,PJP 1702 )

+1.35VSDGPU

+NVVDD2_S

JUMP

(PJP230 1,PJP 2302 )

+1.35VSDGPU_S

+5V_KB

+5VALW_PD

JUMP

+5VS

(J15)

+12VS

+5V_TOBII

+5V_POGO

0 ohm
(R353)

0 ohm
(R358)

0 ohm
(R355)

+5V_3DCAM

0 ohm

+3VALW_SPI

(RH27)

0 ohm
(R313)

+2.5VP +2.5V

JUMP
(PJ505)

+3VS_TBT

+3VS_WLAN

+3V_LAN

+5V_LBPWR

+3VS_NGFF1

+3VS_NGFF2

+3VS

0 ohm

R343)

(

0 ohm
(R347)

1V8_MAIN_EN

AOZ1331
(UG12)

1V8_MAIN_EN_S

AOZ1331
(UG30)

+VCC_FAN1

+VCC_FAN2

+VCC_FAN3

+1.0V_VCCST

+1.0V_VCCSTG

+1.8VSDGPU_MAIN

+1.8VSDGPU_MAIN_S

3VSDGPU_EN_R

3VSDGPU_EN_S_R

CAM_EN

+3VS

0 ohm
(RH87)

0 ohm
(R360)

0 ohm
(R219)

0 ohm
(RA5)

0ohm
(RA1)

0 ohm
(RA72 )

0 ohm
(RC40)

EN_DFAN

DGPU_ENVDD

TPS22961
(UG14)

TPS22961
(UG29)

SY6288C20A AC
(U16)

SY6288C20A AC

(UV3)

+1.0V_VCCSFR

NCT3942S
(U29)

NCT3942S
(U46)

0 ohm
(R412)

JUMP
(J18)

JUMP
(J28)

AP2330W

(UV1)

SY6288C20A AC
(U34)

+3VSDGPU

+3VSDGPU_S

+3VS_CAM

+3VS_DP

+3VS_VCCATS

+3V_RD

+3VS_TPM

+3VS_DVDDIO

+3VS_DVDD

+3VS_DVDDIO_AMP

+VCC_FAN4

+VCC_FAN5

+5VS_HDD

+VDDA

+5VS_PVDD_AMP

+HDMI_5V_OUT

+LCDVDD

HCB2012KF
(

LA2)

+5VS_AVDD

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Power Map

Power Map

Power Map

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

4 103Monday, January 09, 2017

4 103Monday, January 09, 2017

4 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

BIOS : 0.04
AC mode

Power On

S3 S3 Resume

Power Off

Plug in

+3VLP

D D

EC_ON

+5VALW

→

ON/OFFBTN#

+3VALW

92.95ms

→

→

8.914

+3VLP

EC_ON

+5VALW

ON/OFFBTN#

+

3VALW

→

+1.0ALW

EC_RSMRST#

PBTN_OUT#

PM_SLP_S5#

PM_SLP_S4#

C C

PM_SLP_S3#

SYSON

+1.0V_VCCST

+1.2V_VDDQ

+2.5V

SUSP#

+1.0VS_VCCSTG

+VCCIO

+1.8VS

+3VS

+5VS

B B

EC_VCCST_PG

DDR_PG_CTRL

+0.6VS_VTT

VR_ON

+VCCSA

PCH_PWROK

SYS_PWROK

PLT_RST#

+VCCCORE

PLTRST_CPU#

H_CPUPWRGD

93.42ms

30.4ms

→

→

121.1ms

21ms

←

←

→

16.52ms

→

16.56ms

→

16.58ms

→

→

69.64us

9.95us

→

→

584.8us

5.366ms

→

18.2ms

→

12.76us

→

287.3us

→

260.3us

→

1.431ms

→

1.372ms

→

37.63ms

→

37.63ms

→

13.03us

→

37.64ms

2.067ms

→

17.25ms

→

→

→

148.4ms

2.068ms

→

153.8ms

2.068ms

→

49.57ms

→

358.5us

→

13.85us

→

118.5us

→

1.053ms

→

→

→

→

→

→

→

→

→

11.04ns

→

83.9us

→

6.877us

7.297us

11.17us

→

→

3.84ms

3.03ms

529.6us

1.981ms

116.6us

171.6us

184us

529.4us

8.493ms

→

14us

→

258.3us

→

256.8us

→

1.288ms

→

1.389ms

→

→

→

→

28.86ms

28.86ms

→

28.86ms

→

→

→

→

12.14us

2.077ms

14.16ms

164.6ms

1.526ms

→

169ms

1.526ms

→

54.47ms

→

→

→

→

→

533.3us

→

461.6us

→

359.1us

4.51us

→

→

122.3us

→

1.079ms

→

17.87ms

→

14.02us

→

154.3us

→

→

→

→

→

7.824us

→

8.395us

→

→

11.17us

→

→

→

1.3ms

4.086ms

3.266ms

1.994ms

1.341ms

123.2us

164.9us

177.3us

8.95S

8.392S

8.392S

1.0ALW

+

EC_RSMRST#

PBTN_OUT#

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

S

YSON

+1.0V_VCCST

+1.2V_VDDQ

+2.5V

SUSP

+1.0VS_VCCSTG

+VCCIO

+1.8VS

+3VS

+5VS

EC_VCCST_PG

DDR_PG_CTRL

+0.6VS_VTT

VR_ON

+VCCSA

PCH_PWROK

SYS_PWROK

PLT_RST#

→

→

28.52ns

→

83.29us

569.1us

+VCCCORE

PLTRST_CPU#

H_CPUPWRGD

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Power Sequence

Power Sequence

Power Sequence

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

1

5 103Monday, January 09, 2017

5 103Monday, January 09, 2017

5 103Monday, January 09, 2017

1.0

1.0

1.0

A

K36

DDI1_TXP[0]

K37

DDI1_TXN[0]

J35

DDI1_TXP[1]

UC1

1 1

2 2

QL3X@

S IC CL8067702869811 QL3X A0 2.4G FCBGA 1440

SA0000A1520

QL2X@

UC1

S IC CL8067702869810 QL2X A0 2.7G FCBGA 1440

SA0000A1320

UC1

QLM4@

S IC CL8067702870009 QLM4 B0 2.9G BGA

SA0000ADA10

UC1

SR32P@

S IC CL8067702870009 SR32P B0 2.9G ABO!

SA0000ADA30

J34
H37
H36

J37

J38
D27

E27
H34

H33
F37
G38
F34
F35
E37
E36

F26
E26

C34
D34
B36
B34
F33
E33
C33
B33

A27
B27

DDI1_TXN[1]
DDI1_TXP[2]
DDI1_TXN[2]
DDI1_TXP[3]
DDI1_TXN[3]

DDI1_AUXP
DDI1_AUXN

DDI2_TXP[0]
DDI2_TXN[0]
DDI2_TXP[1]
DDI2_TXN[1]
DDI2_TXP[2]
DDI2_TXN[2]
DDI2_TXP[3]
DDI2_TXN[3]

DDI2_AUXP
DDI2_AUXN

DDI3_TXP[0]
DDI3_TXN[0]
DDI3_TXP[1]
DDI3_TXN[1]
DDI3_TXP[2]
DDI3_TXN[2]
DDI3_TXP[3]
DDI3_TXN[3]

DDI3_AUXP
DDI3_AUXN

S

KL-H_BGA1440

@

UC1D

B

SKYLAKE_HAL O

BGA1440

4 OF 14

EDP_TXP[0]
EDP_TXN[0]
EDP_TXP[1]
EDP_TXN[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXP
EDP_AUXN

EDP_DISP_UTIL

EDP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

D29
E29
F28
E28
B29
A29
B28
C28

C26
B26

A33

EDP_COMP

D37

EDP_COMP
Trace = 20 mils
Spacing = 25 mils
Max lenght = 100 mils

G27
G25
G29

?REV = 1

CPU_DISPA_SDI

12

RC47 20_0402_1%

C

+VCCIO

12

RC124.9_0402_1%

CPU_DISPA_BCLK_R <20>
CPU_DISPA_SDO_R <20>

CPU_DISPA_SDI_R <20>

D

E

CMC CONN

RC3 0_0603_5%CMC@

+3VALW_PCH_PRIM

1 2

RC2 1K_0402_5%

+1.0VS_VCCSTG

RC4 51_0402_5%

3 3

Place to CPU side

Place to CPU side

4 4

RC5 51_0402_5%
RC6 51_0402_5%

+1.0VALW_XDP

RC8 2.2K_0402_5%CMC@

RC10 0_0402_5%@
RC11 0_0402_5%@

RC13 51_0402_5%
RC15 51_0402_5%@
RC17 51_0402_5%@

RC60 1K_0402_5%@

12
12
12

1 2

12
12

12
12
12

1 2

XDP_SPI_SI

CPU_XDP_TMS
CPU_XDP_TDI
CPU_XDP_TDO

XDP_ITP_PMODE

XDP_PRSENT_CPU
XDP_PRSENT_PCH

CPU_XDP_TCK0
PCH_JTAG_TCK1
CPU_XDP_TRST#

CFG0

CMC@

CPU_XDP_TDO<9,20>
CPU_XDP_TDI<9,20>
CPU_XDP_TMS<9,20>

CPU_XDP_TCK0<9,20>

CPU_XDP_TRST#<9,24>
PCH_JTAG_TCK1<20>

XDP_SPI_IO2<19>

XDP_SPI_SI<19>

XDP_ITP_PMODE<20>

EC_RSMRST#<20,38>

CPU_XDP_TDO
CPU_XDP_TDI
CPU_XDP_TMS
CPU_XDP_TCK0

CPU_XDP_TRST#
PCH_JTAG_TCK1

CFG3
XDP_SPI_IO2

XDP_SPI_SI
XDP_ITP_PMODE XDP_HOOK6

RPC1

1 8
2 7
3 6
4 5

0_0804_8P4R_5%

CMC@

RPC2

1 8
2 7
3 6
4 5

0_0804_8P4R_5%

CMC@

RPC3

1 8
2 7
3 6
4 5

0_0804_8P4R_5%

1 2

CMC@

RC56 1K_0402_5%

XDP_TDO
XDP_TDI
XDP_TMS
XDP_TCK0

XDP_TRST#

XDP_TCK1
XDP_PRSENT_CPU
XDP_PRSENT_PCH

XDP_HOOK3

XDP_HOOK0EC_RSMRST#

CFG0<9>
CFG1<9>
CFG2<9>
CFG3<9>
CFG4<9>
CFG5<9>
CFG6<9>
CFG7<9>

CFG17<9>
CFG16<9>

CFG8<9>

CFG9<9>
CFG10<9>
CFG11<9>
CFG12<9>
CFG13<9>
CFG14<9>
CFG15<9>

CFG19<9>
CFG18<9>

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7

CFG17
CFG16

CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG19
CFG18

JPCMC1

OBS DATA

1

DATA_0

3

DATA_1

5

DATA_2

7

DATA_3

9

DATA_4

11

DATA_5

13

DATA_6

15

DATA_7

17

DATA_CLK_1P

21

DATA_CLK_1N

2

DATA_8

4

DATA_9

6

DATA_10

8

DATA_11

10

DATA_12

12

DATA_13

14

DATA_14

16

DATA_15

18

DATA_CLK_2P

20

DATA_CLK_2N

INTEL_CMC_PRIMARY

CONN@

1 2

CMC_DEBUG_36P

+1.0VALW_XDP+1.0VALW_PRIM

JTAG/RC/HOOKS

VCCOBS_AB

XDP_TRST*

XDP_TDI

XDP_TMS
XDP_TCK0
XDP_TCK1

XDP_TDO

XDP_PREQ*

XDP_PRDY*

HOOK_0
HOOK_3
HOOK_6

XDP_PRSNT_PCH*
XDP_PRSNT_CPU*

GND

<MT> GND

+1.0VALW_XDP

22

XDP_TRST#

28

XDP_TDI

29

XDP_TMS

30

XDP_TCK0

32

XDP_TCK1

31

XDP_TDO

35

XDP_PREQ#

33

XDP_PRDY#

34

XDP_HOOK0

27

XDP_HOOK3

25

XDP_HOOK6

26

XDP_PRSENT_PCH

24

XDP_PRSENT_CPU

23
19

36

XDP_PREQ# <9,24>
XDP_PRDY# <9,24>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

A

B

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

C

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

D

Date: Sheet o f

Compal Electronics, Inc.

SKL-H(1/9)DDI,EDP

SKL-H(1/9)DDI,EDP

SKL-H(1/9)DDI,EDP

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

E

6 103Monday, January 09, 2017

6 103Monday, January 09, 2017

6 103Monday, January 09, 2017

1.0

1.0

1.0

A

B

C

D

E

CHANNEL-A

Interleaved Memory

1 1

DDR_A_D[0..15]<14,15>

DDR_A_D[16..31]<14,15>

DDR_A_D[32..47]<14,15>

2 2

DDR_A_D[48..63]<14,15>

3 3

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

UC1A

BR6

DDR0_DQ[0]

BT6

DDR0_DQ[1]

BP3

DDR0_DQ[2]

BR3

DDR0_DQ[3]

BN5

DDR0_DQ[4]

BP6

DDR0_DQ[5]

BP2

DDR0_DQ[6]

BN3

DDR0_DQ[7]

BL4

DDR0_DQ[8]

BL5

DDR0_DQ[9]

BL2

DDR0_DQ[10]

BM1

DDR0_DQ[11]

BK4

DDR0_DQ[12]

BK5

DDR0_DQ[13]

BK1

DDR0_DQ[14]

BK2

DDR0_DQ[15]

BG4

DDR0_DQ[16]/DDR0_DQ[32]

BG5

DDR0_DQ[17]/DDR0_DQ[33]

BF4

DDR0_DQ[18]/DDR0_DQ[34]

BF5

DDR0_DQ[19]/DDR0_DQ[35]

BG2

DDR0_DQ[20]/DDR0_DQ[36]

BG1

DDR0_DQ[21]/DDR0_DQ[37]

BF1

DDR0_DQ[22]/DDR0_DQ[38]

BF2

DDR0_DQ[23]/DDR0_DQ[39]

BD2

DDR0_DQ[24]/DDR0_DQ[40]

BD1

DDR0_DQ[25]/DDR0_DQ[41]

BC4

DDR0_DQ[26]/DDR0_DQ[42]

BC5

DDR0_DQ[27]/DDR0_DQ[43]

BD5

DDR0_DQ[28]/DDR0_DQ[44]

BD4

DDR0_DQ[29]/DDR0_DQ[45]

BC1

DDR0_DQ[30]/DDR0_DQ[46]

BC2

DDR0_DQ[31]/DDR0_DQ[47]

AB1

DDR0_DQ[32]/DDR1_DQ[0]

AB2

DDR0_DQ[33]/DDR1_DQ[1]

AA4

DDR0_DQ[34]/DDR1_DQ[2]

AA5

DDR0_DQ[35]/DDR1_DQ[3]

AB5

DDR0_DQ[36]/DDR1_DQ[4]

AB4

DDR0_DQ[37]/DDR1_DQ[5]

AA2

DDR0_DQ[38]/DDR1_DQ[6]

AA1

DDR0_DQ[39]/DDR1_DQ[7]

V5

DDR0_DQ[40]/DDR1_DQ[8]

V2

DDR0_DQ[41]/DDR1_DQ[9]

U1

DDR0_DQ[42]/DDR1_DQ[10]

U2

DDR0_DQ[43]/DDR1_DQ[11]

V1

DDR0_DQ[44]/DDR1_DQ[12]

V4

DDR0_DQ[45]/DDR1_DQ[13]

U5

DDR0_DQ[46]/DDR1_DQ[14]

U4

DDR0_DQ[47]/DDR1_DQ[15]

R2

DDR0_DQ[48]/DDR1_DQ[32]

P5

DDR0_DQ[49]/DDR1_DQ[33]

R4

DDR0_DQ[50]/DDR1_DQ[34]

P4

DDR0_DQ[51]/DDR1_DQ[35]

R5

DDR0_DQ[52]/DDR1_DQ[36]

P2

DDR0_DQ[53]/DDR1_DQ[37]

R1

DDR0_DQ[54]/DDR1_DQ[38]

P1

DDR0_DQ[55]/DDR1_DQ[39]

M4

DDR0_DQ[56]/DDR1_DQ[40]

M1

DDR0_DQ[57]/DDR1_DQ[41]

L4

DDR0_DQ[58]/DDR1_DQ[42]

L2

DDR0_DQ[59]/DDR1_DQ[43]

M5

DDR0_DQ[60]/DDR1_DQ[44]

M2

DDR0_DQ[61]/DDR1_DQ[45]

L5

DDR0_DQ[62]/DDR1_DQ[46]

L1

DDR0_DQ[63]/DDR1_DQ[47]

BA2

DDR0_ECC[0]

BA1

DDR0_ECC[1]

AY4

DDR0_ECC[2]

AY5

DDR0_ECC[3]

BA5

DDR0_ECC[4]

BA4

DDR0_ECC[5]

AY1

DDR0_ECC[6]

AY2

DDR0_ECC[7]

DDR CHANNEL A

S

KL-H_BGA1440

REV = 1

@

SKYLAKE_HALO

BGA1440

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSN[7]/DDR1_DQSN[5]

1 OF 14

DDR0_CKP[0]
DDR0_CKN[0]
DDR0_CKN[1]

DDR0_CKP[1]
DDR0_CLKP[2]
DDR0_CLKN[2]
DDR0_CLKP[3]
DDR0_CLKN[3]

DDR0_CKE[0]

DDR0_CKE[1]

DDR0_CKE[2]

DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1]

DDR0_CS#[2]

DDR0_CS#[3]

DDR0_ODT[0]

DDR0_ODT[1]

DDR0_ODT[2]

DDR0_ODT[3]

DDR0_MA[3]
DDR0_MA[4]

DDR0_PAR

DDR0_ALERT#

DDR0_DQSN[0]
DDR0_DQSN[1]

DDR0_DQSP[0]
DDR0_DQSP[1]

DDR0_DQSP[8]
DDR0_DQSN[8]

?

DDR_A_CLK0

AG1

DDR_A_CLK#0

AG2

DDR_A_CLK#1

AK1

DDR_A_CLK1

AK2

DDR_A_CLK2

AL3

DDR_A_CLK#2

AK3

DDR_A_CLK3

AL2

DDR_A_CLK#3

AL1

DDR_A_CKE0

AT1

DDR_A_CKE1

AT2

DDR_A_CKE2

AT3

DDR_A_CKE3

AT5

DDR_A_CS#0

AD5

DDR_A_CS#1

AE2

DDR_A_CS#2

AD2

DDR_A_CS#3

AE5

DDR_A_ODT0

AD3

DDR_A_ODT1

AE4

DDR_A_ODT2

AE1

DDR_A_ODT3

AD4

DDR_A_BA0

AH5

DDR_A_BA1

AH1

DDR_A_BG0

AU1

DDR_A_RAS#

AH4

DDR_A_WE#

AG4

DDR_A_CAS#

AD1

DDR_A_MA0

AH3

DDR_A_MA1

AP4

DDR_A_MA2

AN4

DDR_A_MA3

AP5

DDR_A_MA4

AP2

DDR_A_MA5

AP1

DDR_A_MA6

AP3

DDR_A_MA7

AN1

DDR_A_MA8

AN3

DDR_A_MA9

AT4

DDR_A_MA10

AH2

DDR_A_MA11

AN2

DDR_A_MA12

AU4

DDR_A_MA13

AE3

DDR_A_BG1

AU2

DDR_A_ACT#

AU3

DDR_A_PAR

AG3

DDR_A_ALERT# DDR_B_PAR

AU5

DDR_A_DQS#0

BR5

DDR_A_DQS#1

BL3

DDR_A_DQS#2

BG3

DDR_A_DQS#3

BD3

DDR_A_DQS4

AB3

DDR_A_DQS5

V3

DDR_A_DQS6

R3

DDR_A_DQS7

M3

DDR_A_DQS0

BP5

DDR_A_DQS1

BK3

DDR_A_DQS2

BF3

DDR_A_DQS3

BC3

DDR_A_DQS#4

AA3

DDR_A_DQS#5

U3

DDR_A_DQS#6

P3

DDR_A_DQS#7

L3
AY3

BA3

DDR_A_CLK0 <14>
DDR_A_CLK#0 <14>
DDR_A_CLK#1 <14>
DDR_A_CLK1 <14>
DDR_A_CLK2 <15>
DDR_A_CLK#2 <15>
DDR_A_CLK3 <15>
DDR_A_CLK#3 <15>

DDR_A_CKE0 <14>
DDR_A_CKE1 <14>
DDR_A_CKE2 <15>
DDR_A_CKE3 <15>

DDR_A_CS#0 <14>
DDR_A_CS#1 <14>
DDR_A_CS#2 <15>
DDR_A_CS#3 <15>

DDR_A_ODT0 <14>
DDR_A_ODT1 <14>
DDR_A_ODT2 <15>
DDR_A_ODT3 <15>

DDR_A_BA0 <14,15>
DDR_A_BA1 <14,15>
DDR_A_BG0 <14,15>

DDR_A_RAS# <14,15>
DDR_A_WE# <14,15>
DDR_A_CAS# <14,15>

DDR_A_MA0 <14,15>
DDR_A_MA1 <14,15>
DDR_A_MA2 <14,15>
DDR_A_MA3 <14,15>
DDR_A_MA4 <14,15>
DDR_A_MA5 <14,15>
DDR_A_MA6 <14,15>
DDR_A_MA7 <14,15>
DDR_A_MA8 <14,15>
DDR_A_MA9 <14,15>
DDR_A_MA10 <14,15>
DDR_A_MA11 <14,15>
DDR_A_MA12 <14,15>
DDR_A_MA13 <14,15>
DDR_A_BG1 <14,15>
DDR_A_ACT# <14,15>

DDR_A_PAR <14,15>
DDR_A_ALERT# <14,15> DDR_B_PAR <16,17>

DDR_A_DQS#0 <14,15>
DDR_A_DQS#1 <14,15>
DDR_A_DQS#2 <14,15>
DDR_A_DQS#3 <14,15>
DDR_A_DQS4 <14,15>
DDR_A_DQS5 <14,15>
DDR_A_DQS6 <14,15>
DDR_A_DQS7 <14,15>

DDR_A_DQS0 <14,15>
DDR_A_DQS1 <14,15>
DDR_A_DQS2 <14,15>
DDR_A_DQS3 <14,15>
DDR_A_DQS#4 <14,15>
DDR_A_DQS#5 <14,15>
DDR_A_DQS#6 <14,15>
DDR_A_DQS#7 <14,15>

DDR_B_D[0..15]<16,17>

DDR_B_D[16..31]<16,17>

DDR_B_D[32..47]<16,17>

DDR_B_D[48..63]<16,17>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

SM_RCOMP0

12

RC19121_0402_1%

SM_RCOMP1

12

RC2075_0402_1%

SM_RCOMP2

12

RC21100_0402_1%

Place close to CPU

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
Trace = 12~15 mils
Spacing = 20 mils
Max lenght = 500 mils

CHANNEL-B

Interleaved Memory

UC1B

BT11

DDR1_DQ[0]/DDR0_DQ[16]

BR11

DDR1_DQ[1]/DDR0_DQ[17]

BT8

DDR1_DQ[2]/DDR0_DQ[18]

BR8

DDR1_DQ[3]/DDR0_DQ[19]

BP11

DDR1_DQ[4]/DDR0_DQ[20]

BN11

DDR1_DQ[5]/DDR0_DQ[21]

BP8

DDR1_DQ[6]/DDR0_DQ[22]

BN8

DDR1_DQ[7]/DDR0_DQ[23]

BL12

DDR1_DQ[8]/DDR0_DQ[24]

BL11

DDR1_DQ[9]/DDR0_DQ[25]

BL8

DDR1_DQ[10]/DDR0_DQ[26]

BJ8

DDR1_DQ[11]/DDR0_DQ[27]

BJ11

DDR1_DQ[12]/DDR0_DQ[28]

BJ10

DDR1_DQ[13]/DDR0_DQ[29]

BL7

DDR1_DQ[14]/DDR0_DQ[30]

BJ7

DDR1_DQ[15]/DDR0_DQ[31]

BG11

DDR1_DQ[16]/DDR0_DQ[48]

BG10

DDR1_DQ[17]/DDR0_DQ[49]

BG8

DDR1_DQ[18]/DDR0_DQ[50]

BF8

DDR1_DQ[19]/DDR0_DQ[51]

BF11

DDR1_DQ[20]/DDR0_DQ[52]

BF10

DDR1_DQ[21]/DDR0_DQ[53]

BG7

DDR1_DQ[22]/DDR0_DQ[54]

BF7

DDR1_DQ[23]/DDR0_DQ[55]

BB11

DDR1_DQ[24]/DDR0_DQ[56]

BC11

DDR1_DQ[25]/DDR0_DQ[57]

BB8

DDR1_DQ[26]/DDR0_DQ[58]

BC8

DDR1_DQ[27]/DDR0_DQ[59]

BC10

DDR1_DQ[28]/DDR0_DQ[60]

BB10

DDR1_DQ[29]/DDR0_DQ[61]

BC7

DDR1_DQ[30]/DDR0_DQ[62]

BB7

DDR1_DQ[31]/DDR0_DQ[63]

AA11

DDR1_DQ[32]/DDR1_DQ[16]

AA10

DDR1_DQ[33]/DDR1_DQ[17]

AC11

DDR1_DQ[34]/DDR1_DQ[18]

AC10

DDR1_DQ[35]/DDR1_DQ[19]

AA7

DDR1_DQ[36]/DDR1_DQ[20]

AA8

DDR1_DQ[37]/DDR1_DQ[21]

AC8

DDR1_DQ[38]/DDR1_DQ[22]

AC7

DDR1_DQ[39]/DDR1_DQ[23]

W8

DDR1_DQ[40]/DDR1_DQ[24]

W7

DDR1_DQ[41]/DDR1_DQ[25]

V10

DDR1_DQ[42]/DDR1_DQ[26]

V11

DDR1_DQ[43]/DDR1_DQ[27]

W11

DDR1_DQ[44]/DDR1_DQ[28]

W10

DDR1_DQ[45]/DDR1_DQ[29]

V7

DDR1_DQ[46]/DDR1_DQ[30]

V8

DDR1_DQ[47]/DDR1_DQ[31]

R11

DDR1_DQ[48]

P11

DDR1_DQ[49]

P7

DDR1_DQ[50]

R8

DDR1_DQ[51]

R10

DDR1_DQ[52]

P10

DDR1_DQ[53]

R7

DDR1_DQ[54]

P8

DDR1_DQ[55]

L11

DDR1_DQ[56]

M11

DDR1_DQ[57]

L7

DDR1_DQ[58]

M8

DDR1_DQ[59]

L10

DDR1_DQ[60]

M10

DDR1_DQ[61]

M7

DDR1_DQ[62]

L8

DDR1_DQ[63]

AW11

DDR1_ECC[0]

AY11

DDR1_ECC[1]

AY8

DDR1_ECC[2]

AW8

DDR1_ECC[3]

AY10

DDR1_ECC[4]

AW10

DDR1_ECC[5]

AY7

DDR1_ECC[6]

AW7

DDR1_ECC[7]

G1

DDR_RCOMP[0]

H1

DDR_RCOMP[1]

J2

DDR_RCOMP[2]

S

KL-H_BGA1440

REV = 1 ?

@

DDR CHANNEL B

SKYLAKE_HALO

BGA1440

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSP[5]/DDR1_DQSP[3]

2 OF 14

DDR1_CKP[0]
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[1]

DDR1_CLKP[2]

DDR1_CLKN[2]

DDR1_CLKP[3]

DDR1_CLKN[3]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1]
DDR1_CS#[2]
DDR1_CS#[3]

DDR1_ODT[0]
DDR1_ODT[1]
DDR1_ODT[2]
DDR1_ODT[3]

DDR1_MA[3]
DDR1_MA[4]

DDR1_PAR

DDR1_ALERT#

DDR1_DQSN[6]
DDR1_DQSN[7]

DDR1_DQSP[6]
DDR1_DQSP[7]

DDR1_DQSP[8]
DDR1_DQSN[8]

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

AM9
AN9
AM8
AM7
AM11
AM10
AJ10
AJ11

AT8
AT10
AT7
AT11

AF11
AE7
AF10
AE10

AF7
AE8
AE9
AE11

AH10
AH11
AF8

AH8
AH9
AR9

AJ9
AK6
AK5
AL5
AL6
AM6
AN7
AN10
AN8
AR11
AH7
AN11
AR10
AF9
AR7
AT9

AJ7
AR8

BP9
BL9
BG9
BC9
AC9
W9
R9
M9

BR9
BJ9
BF9
BB9
AA9
V9
P9
L9

AW9
AY9

BN13
BP13
BR13

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK#1
DDR_B_CLK1
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK3
DDR_B_CLK#3

DDR_B_CKE0
DDR_B_CKE1
DDR_B_CKE2
DDR_B_CKE3

DDR_B_CS#0
DDR_B_CS#1
DDR_B_CS#2
DDR_B_CS#3

DDR_B_ODT0
DDR_B_ODT1
DDR_B_ODT2
DDR_B_ODT3

DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#

DDR_B_BA0
DDR_B_BA1
DDR_B_BG0

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_BG1
DDR_B_ACT#

DDR_B_ALERT#

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

+0.6V_VREFCA
+0.6V_B_VREFDQ

DDR_B_CLK0 <16>
DDR_B_CLK#0 <16>
DDR_B_CLK#1 <16>
DDR_B_CLK1 <16>
DDR_B_CLK2 <17>
DDR_B_CLK#2 <17>
DDR_B_CLK3 <17>
DDR_B_CLK#3 <17>

DDR_B_CKE0 <16>
DDR_B_CKE1 <16>
DDR_B_CKE2 <17>
DDR_B_CKE3 <17>

DDR_B_CS#0 <16>
DDR_B_CS#1 <16>
DDR_B_CS#2 <17>
DDR_B_CS#3 <17>

DDR_B_ODT0 <16>
DDR_B_ODT1 <16>
DDR_B_ODT2 <17>
DDR_B_ODT3 <17>

DDR_B_RAS# <16,17>
DDR_B_WE# <16,17>
DDR_B_CAS# <16,17>

DDR_B_BA0 <16,17>
DDR_B_BA1 <16,17>
DDR_B_BG0 <16,17>

DDR_B_MA0 <16,17>
DDR_B_MA1 <16,17>
DDR_B_MA2 <16,17>
DDR_B_MA3 <16,17>
DDR_B_MA4 <16,17>
DDR_B_MA5 <16,17>
DDR_B_MA6 <16,17>
DDR_B_MA7 <16,17>
DDR_B_MA8 <16,17>
DDR_B_MA9 <16,17>
DDR_B_MA10 <16,17>
DDR_B_MA11 <16,17>
DDR_B_MA12 <16,17>
DDR_B_MA13 <16,17>
DDR_B_BG1 <16,17>
DDR_B_ACT# <16,17>

DDR_B_ALERT# <16,17>

DDR_B_DQS#0 <16,17>
DDR_B_DQS#1 <16,17>
DDR_B_DQS#2 <16,17>
DDR_B_DQS#3 <16,17>
DDR_B_DQS#4 <16,17>
DDR_B_DQS#5 <16,17>
DDR_B_DQS#6 <16,17>
DDR_B_DQS#7 <16,17>

DDR_B_DQS0 <16,17>
DDR_B_DQS1 <16,17>
DDR_B_DQS2 <16,17>
DDR_B_DQS3 <16,17>
DDR_B_DQS4 <16,17>
DDR_B_DQS5 <16,17>
DDR_B_DQS6 <16,17>
DDR_B_DQS7 <16,17>

+0.6V_VREFCA
+0.6V_B_VREFDQ

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom
Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

SKL-H(2/9)DDRIII

SKL-H(2/9)DDRIII

SKL-H(2/9)DDRIII

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Monday, January 09, 2017

Monday, January 09, 2017

Monday, January 09, 2017

E

7

1.0

1.0

1.0

103

103

103

7

7

A

B

C

D

E

PEG 2x8 reverse

1 1

1 2

PCIE_CRX_C_GTX_P15<53>
PCIE_CRX_C_GTX_N15<53>

PCIE_CRX_C_GTX_P14<53>
PCIE_CRX_C_GTX_N14<53>

PCIE_CRX_C_GTX_P13<53>
PCIE_CRX_C_GTX_N13<53>

PCIE_CRX_C_GTX_P12<53>

Slave GPU

2 2

Master GPU

3 3

PCIE_CRX_C_GTX_N12<53>
PCIE_CRX_C_GTX_P11<53>

PCIE_CRX_C_GTX_N11<53>
PCIE_CRX_C_GTX_P10<53>

PCIE_CRX_C_GTX_N10<53>
PCIE_CRX_C_GTX_P9<53>

PCIE_CRX_C_GTX_N9<53>
PCIE_CRX_C_GTX_P8<53>

PCIE_CRX_C_GTX_N8<53>
PCIE_CRX_C_GTX_P7<41>

PCIE_CRX_C_GTX_N7<41>
PCIE_CRX_C_GTX_P6<41>

PCIE_CRX_C_GTX_N6<41>
PCIE_CRX_C_GTX_P5<41>

PCIE_CRX_C_GTX_N5<41>
PCIE_CRX_C_GTX_P4<41>

PCIE_CRX_C_GTX_N4<41>
PCIE_CRX_C_GTX_P3<41>

PCIE_CRX_C_GTX_N3<41>
PCIE_CRX_C_GTX_P2<41>

PCIE_CRX_C_GTX_N2<41>
PCIE_CRX_C_GTX_P1<41>

PCIE_CRX_C_GTX_N1<41>
PCIE_CRX_C_GTX_P0<41>

PCIE_CRX_C_GTX_N0<41>

CC87 0.22U_0402_16V7K

1 2

CC88 0.22U_0402_16V7K

1 2

CC85 0.22U_0402_16V7K

1 2

CC86 0.22U_0402_16V7K

1 2

CC83 0.22U_0402_16V7K

1 2

CC84 0.22U_0402_16V7K

1 2

CC81 0.22U_0402_16V7K

1 2

CC82 0.22U_0402_16V7K

1 2

CC80 0.22U_0402_16V7K

1 2

CC79 0.22U_0402_16V7K

1 2

CC78 0.22U_0402_16V7K

1 2

CC77 0.22U_0402_16V7K

1 2

CC76 0.22U_0402_16V7K

1 2

CC75 0.22U_0402_16V7K

1 2

CC73 0.22U_0402_16V7K

1 2

CC74 0.22U_0402_16V7K

1 2

CC49 0.22U_0402_16V7K

1 2

CC50 0.22U_0402_16V7K

1 2

CC51 0.22U_0402_16V7K

1 2

CC52 0.22U_0402_16V7K

1 2

CC57 0.22U_0402_16V7K

1 2

CC58 0.22U_0402_16V7K

1 2

CC59 0.22U_0402_16V7K

1 2

CC60 0.22U_0402_16V7K

1 2

CC61 0.22U_0402_16V7K

1 2

CC62 0.22U_0402_16V7K

1 2

CC63 0.22U_0402_16V7K

1 2

CC64 0.22U_0402_16V7K

1 2

CC65 0.22U_0402_16V7K

1 2

CC66 0.22U_0402_16V7K

1 2

CC67 0.22U_0402_16V7K

1 2

CC68 0.22U_0402_16V7K

CAD note:
Trace width=12 mils,Spacing=15mil,Max length=400mils

+VCCIO

DMI_CRX_PTX_P0<18>
DMI_CRX_PTX_N0<18>

DMI_CRX_PTX_P1<18>
DMI_CRX_PTX_N1<18>

DMI_CRX_PTX_P2<18>
DMI_CRX_PTX_N2<18>

DMI_CRX_PTX_P3<18>
DMI_CRX_PTX_N3<18>

1 2

RC22 24.9_0402_1%

PCIE_CRX_GTX_P15
PCIE_CRX_GTX_N15

PCIE_CRX_GTX_P14
PCIE_CRX_GTX_N14

PCIE_CRX_GTX_P13
PCIE_CRX_GTX_N13

PCIE_CRX_GTX_P12
PCIE_CRX_GTX_N12

PCIE_CRX_GTX_P11
PCIE_CRX_GTX_N11

PCIE_CRX_GTX_P10
PCIE_CRX_GTX_N10

PCIE_CRX_GTX_P9
PCIE_CRX_GTX_N9

PCIE_CRX_GTX_P8
PCIE_CRX_GTX_N8

PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7

PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5

PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

PEG_RCOMP

DMI_CRX_PTX_P0
DMI_CRX_PTX_N0

DMI_CRX_PTX_P1
DMI_CRX_PTX_N1

DMI_CRX_PTX_P2
DMI_CRX_PTX_N2

DMI_CRX_PTX_P3
DMI_CRX_PTX_N3

E25
D25

E24
F24

E23
D23

E22
F22

E21
D21

E20
F20

E19
D19

E18
F18

D17
E17

F16
E16

D15
E15

F14
E14

D13
E13

F12
E12

D11
E11

F10
E10

G2

D8
E8

E6

F6

D5
E5

J8
J9

UC1C

PEG_RXP[0]
PEG_RXN[0]

PEG_RXP[1]
PEG_RXN[1]

PEG_RXP[2]
PEG_RXN[2]

PEG_RXP[3]
PEG_RXN[3]

PEG_RXP[4]
PEG_RXN[4]

PEG_RXP[5]
PEG_RXN[5]

PEG_RXP[6]
PEG_RXN[6]

PEG_RXP[7]
PEG_RXN[7]

PEG_RXP[8]
PEG_RXN[8]

PEG_RXP[9]
PEG_RXN[9]

PEG_RXP[10]
PEG_RXN[10]

PEG_RXP[11]
PEG_RXN[11]

PEG_RXP[12]
PEG_RXN[12]

PEG_RXP[13]
PEG_RXN[13]

PEG_RXP[14]
PEG_RXN[14]

PEG_RXP[15]
PEG_RXN[15]

PEG_RCOMP

DMI_RXP[0]
DMI_RXN[0]

DMI_RXP[1]
DMI_RXN[1]

DMI_RXP[2]
DMI_RXN[2]

DMI_RXP[3]
DMI_RXN[3]

S

KL-H_BGA1440

REV = 1

@

SKYLAKE_HALO

BGA1440

3 OF 14

PEG_TXP[0]
PEG_TXN[0]

PEG_TXP[1]
PEG_TXN[1]

PEG_TXP[2]
PEG_TXN[2]

PEG_TXP[3]
PEG_TXN[3]

PEG_TXP[4]
PEG_TXN[4]

PEG_TXP[5]
PEG_TXN[5]

PEG_TXP[6]
PEG_TXN[6]

PEG_TXP[7]
PEG_TXN[7]

PEG_TXP[8]
PEG_TXN[8]

PEG_TXP[9]
PEG_TXN[9]

PEG_TXP[10]
PEG_TXN[10]

PEG_TXP[11]
PEG_TXN[11]

PEG_TXP[12]
PEG_TXN[12]

PEG_TXP[13]
PEG_TXN[13]

PEG_TXP[14]
PEG_TXN[14]

PEG_TXP[15]
PEG_TXN[15]

DMI_TXP[0]
DMI_TXN[0]

DMI_TXP[1]
DMI_TXN[1]

DMI_TXP[2]
DMI_TXN[2]

DMI_TXP[3]
DMI_TXN[3]

B25
A25

B24
C24

B23
A23

B22
C22

B21
A21

B20
C20

B19
A19

B18
C18

A17
B17

C16
B16

A15
B15

C14
B14

A13
B13

C12
B12

A11
B11

C10
B10

B8
A8

C6
B6

B5
A5

D4
B4

?

PCIE_CTX_GRX_P15
PCIE_CTX_GRX_N15

PCIE_CTX_GRX_P14
PCIE_CTX_GRX_N14

PCIE_CTX_GRX_P13
PCIE_CTX_GRX_N13

PCIE_CTX_GRX_P12
PCIE_CTX_GRX_N12

PCIE_CTX_GRX_P11
PCIE_CTX_GRX_N11

PCIE_CTX_GRX_P10
PCIE_CTX_GRX_N10

PCIE_CTX_GRX_P9
PCIE_CTX_GRX_N9

PCIE_CTX_GRX_P8
PCIE_CTX_GRX_N8

PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7

PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6

PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5

PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4

PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3

PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0

DMI_CTX_PRX_P0
DMI_CTX_PRX_N0

DMI_CTX_PRX_P1
DMI_CTX_PRX_N1

DMI_CTX_PRX_P2
DMI_CTX_PRX_N2

DMI_CTX_PRX_P3
DMI_CTX_PRX_N3

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

DMI_CTX_PRX_P0 <18>
DMI_CTX_PRX_N0 <18>

DMI_CTX_PRX_P1 <18>
DMI_CTX_PRX_N1 <18>

DMI_CTX_PRX_P2 <18>
DMI_CTX_PRX_N2 <18>

DMI_CTX_PRX_P3 <18>
DMI_CTX_PRX_N3 <18>

CC1040.22U_0402_16V7K
CC1030.22U_0402_16V7K

CC1020.22U_0402_16V7K
CC1010.22U_0402_16V7K

CC990.22U_0402_16V7K
CC1000.22U_0402_16V7K

CC970.22U_0402_16V7K
CC980.22U_0402_16V7K

CC950.22U_0402_16V7K
CC960.22U_0402_16V7K

CC940.22U_0402_16V7K
CC930.22U_0402_16V7K

CC920.22U_0402_16V7K
CC910.22U_0402_16V7K

CC900.22U_0402_16V7K
CC890.22U_0402_16V7K

CC30.22U_0402_16V7K
CC40.22U_0402_16V7K

CC50.22U_0402_16V7K
CC60.22U_0402_16V7K

CC70.22U_0402_16V7K
CC80.22U_0402_16V7K

CC90.22U_0402_16V7K
CC100.22U_0402_16V7K

CC110.22U_0402_16V7K
CC120.22U_0402_16V7K

CC130.22U_0402_16V7K
CC140.22U_0402_16V7K

CC150.22U_0402_16V7K
CC160.22U_0402_16V7K

CC170.22U_0402_16V7K
CC180.22U_0402_16V7K

PCIE_CTX_C_GRX_P15 <53>
PCIE_CTX_C_GRX_N15 <53>

PCIE_CTX_C_GRX_P14 <53>
PCIE_CTX_C_GRX_N14 <53>

PCIE_CTX_C_GRX_P13 <53>
PCIE_CTX_C_GRX_N13 <53>

PCIE_CTX_C_GRX_P12 <53>
PCIE_CTX_C_GRX_N12 <53>

PCIE_CTX_C_GRX_P11 <53>
PCIE_CTX_C_GRX_N11 <53>

PCIE_CTX_C_GRX_P10 <53>
PCIE_CTX_C_GRX_N10 <53>

PCIE_CTX_C_GRX_P9 <53>
PCIE_CTX_C_GRX_N9 <53>

PCIE_CTX_C_GRX_P8 <53>
PCIE_CTX_C_GRX_N8 <53>

PCIE_CTX_C_GRX_P7 <41>
PCIE_CTX_C_GRX_N7 <41>

PCIE_CTX_C_GRX_P6 <41>
PCIE_CTX_C_GRX_N6 <41>

PCIE_CTX_C_GRX_P5 <41>
PCIE_CTX_C_GRX_N5 <41>

PCIE_CTX_C_GRX_P4 <41>
PCIE_CTX_C_GRX_N4 <41>

PCIE_CTX_C_GRX_P3 <41>
PCIE_CTX_C_GRX_N3 <41>

PCIE_CTX_C_GRX_P2 <41>
PCIE_CTX_C_GRX_N2 <41>

PCIE_CTX_C_GRX_P1 <41>
PCIE_CTX_C_GRX_N1 <41>

PCIE_CTX_C_GRX_P0 <41>
PCIE_CTX_C_GRX_N0 <41>

Slave GPU

Master GPU

4 4

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/02/01 2017/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

SKL-H(3/9) PEG,DMI

SKL-H(3/9) PEG,DMI

SKL-H(3/9) PEG,DMI

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

8 103Monday, January 09, 2017

8 103Monday, January 09, 2017

8 103Monday, January 09, 2017

E

1.0

1.0

1.0

A

B

C

D

E

SKYLAKE_HALO

BGA1440

5 OF 14

REV = 1 ?

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]

CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[17]
CFG[16]
CFG[19]
CFG[18]

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]

PROC_TDO

PROC_TDI

PROC_TMS

PROC_TCK

PROC_TRST#
PROC_PREQ#
PROC_PRDY#

CFG_RCOMP

+1.0V_VCCST

+1.0VS_VCCSTG

From EC(open-drain)

H_PROCHOT#<38,75>

DDR_VTT_CNTL to DDR
VTT supplied ramped
<35uS
(tCPU18)

(To VR)

BN25
BN27
BN26
BN28
BR20
BM20
BT20
BP20
BR23
BR22
BT23
BT22
BM19
BR19
BP19
BT19

BN23
BP23
BP22
BN22

XDP_BPM#0

BR27

XDP_BPM#1

BT27
BM31
BT30

CPU_XDP_TDO

BT28

CPU_XDP_TDI

BL32

CPU_XDP_TMS

BP28

CPU_XDP_TCK0

BR28

CPU_XDP_TRST#

BP30

XDP_PREQ#

BL30

XDP_PRDY#SKL_CNL_N

BP27

CFG_RCOMP

BT25

1 2

RC27 1K_0402_5%

12

RC31
1K_0402_5%

1 2

RC33 499_0402_1%

DDR_PG_CTRL

CFG0 <6>
CFG1 <6>
CFG2 <6>
CFG3 <6>
CFG4 <6>
CFG5 <6>
CFG6 <6>
CFG7 <6>
CFG8 <6>
CFG9 <6>
CFG10 <6>
CFG11 <6>
CFG12 <6>
CFG13 <6>
CFG14 <6>
CFG15 <6>

CFG17 <6>
CFG16 <6>
CFG19 <6>
CFG18 <6>

PAD

T25

@

PAD

T26

@

CPU_XDP_TDO <6,20>
CPU_XDP_TDI <6,20>
CPU_XDP_TMS <6,20>
CPU_XDP_TCK0 <6,20>

CPU_XDP_TRST# <6,24>
XDP_PREQ# <6,24>
XDP_PRDY# <6,24>

1 2

RC23 49.9_0402_1%

THERMTRIP#

PROCHOT

12

UC3

NC1VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

Change PN to SA00007UR00.

H_CPUPW RGD

PROCHOT

THERMTRIP#

1 2

CH49 .1U_0402_16V7K

1 2

CH50 .1U_0402_16V7K

1 2

CH51 .1U_0402_16V7K

ESD Reserve ,place close to cpu.

+1.2V_VDDQ

+3VS

CC19.1U_0402_16V7K

5

4

Y

12

RC36
220K_0402_5%

RC38
2M_0402_5%@

1 2

CRB 330K

CPU_BCLK<21>
CPU_BCLK#<21>

CPU_PCIBCLK<21>
CPU_PCIBCLK#<21>

CPU_24M<21>

1 1

H_SKTOCC#<20>

2 2

From EC OD output

EC_VCCST_PG_R<26,38>

3 3

PM_DOW N_R<19>

H_SKTOCC# H_SKTOCC#_R

1 2

@

RC32 1K_0402_5%

CPU_24M#<21>

CPU_SVID_CLK<81>

H_CPUPW RGD<20>
PLTRST_CPU#<19>
H_PM_SYNC<19>

H_PECI<19,38>

THERMTRIP#<19>

1 2

@

1 2

RC57 0_0402_5%
RC34 0_0402_5%@

+1.0V_VCCST

PAD

12

RC25
1K_0402_5%

1 2

RC28 60.4_0402_1%

RC30 20_0402_1%

SVID ALERT

+1.0V_VCCST

CPU_SVID_ALERT#

1 2

RC35 56_0402_5%

1 2

RC37 220_0402_5%

CPU_BCLK
CPU_BCLK#

CPU_PCIBCLK
CPU_PCIBCLK#

CPU_24M
CPU_24M#

CPU_SVID_ALERT#
CPU_SVID_CLK
CPU_SVID_DAT

PROCHOT
DDR_PG_CTRL

EC_VCCST_PG
H_CPUPW RGD

PLTRST_CPU#
H_PM_SYNC
PM_DOW N
H_PECI

THERMTRIP#

CATERR#

T69

@

FLOAT FOR SKL
GND FOR CNL

EC_VCCST_PG

12

Place the PU
resistors close to CPU

PM_DOW N

CPU_SVID_ALERT#_R <81>

B31
A32

D35
C36

E31
D31

BH31
BH32
BH29
BR30

BT13

H13

BT31
BP35
BM34
BP31
BT34

BR33

BN1

BM30

J31

UC1E

BCLKP
BCLKN

PCI_BCLKP
PCI_BCLKN

CLK24P
CLK24N

VIDALERT#
VIDSCK
VIDSOUT
PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD
PROCPWRGD

RESET#
PM_SYNC
PM_DOWN
PECI
THERMTRIP#

SKTOCC#
PROC_SELECT#

CATERR#

S

KL-H_BGA1440

@

Follow PDG1.0
Table 12-16

SVID DATA

4 4

+1.0V_VCCST

1 2

RC39 100_0402_1%

Place the PU
resistors close to CPU

Reference SKL EDS 0.85 Table 6-8
CFG signals internal PH default value = 1

Description

Stall reset sequence after PCU PLL

CFG[0]

CFG[4]

CFG[7]

CFG[1]
CFG[3]

CFG[8:19]

XEMC@

XEMC@

XEMC@

SM_PG_CTRL <77>

lock until de-asserted
— 1 = (Default) Normal Operation;

*

No stall.
— 0 = Stall.

Enable eDP

*

— 1 = Disabled.
— 0 = Enabled.

PEG Training:
— 1 = (default) PEG Train immediately

*

following RESET# de assertion.
— 0 = PEG Wait for BIOS for training

Reserved configuration lane.

PCIE
pore
assign

1 x 16
1 x 16

reverse
2 x 8

2 x 8
reverse
1 x 8
+ 2 x 4
1x8+2x4
reverse

Config. Signals

1 1 1
1 1
1 1

*

1

0 0 0

2x8 reverse

CFG 6 int. PU 1 V

CFG6
CFG7

CFG5
CFG2

CFG4

Display Port Presence : 0 enable / 1 disable

1 2

RC61 1K_0402_1%

1 2

RC62 1K_0402_1%

1 2

@

RC66 1K_0402_1%

1 2

RC26 1K_0402_1%

1 2

RC29 1K_0402_1%

1 2

RC24 1K_0402_1%

CFG[2]CFG[5]CFG[6]

0
0 0
00

+1.0V_VCCST

+1.0V_VCCST

0

1

CPU_SVID_DAT

Security Classification

Security Classification

CPU_SVID_DAT <81>

A

B

(To VR)

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/02/01 2017/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

SKL-H(4/9)CLK,GPIO

SKL-H(4/9)CLK,GPIO

SKL-H(4/9)CLK,GPIO

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

9 103Monday, January 09, 2017

9 103Monday, January 09, 2017

9 103Monday, January 09, 2017

E

1.0

1.0

1.0

A

1 1

2 2

3 3

VCC 27A (U 15W Dual Core GT2)

+VCCCORE +VCCCORE

AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37
AB38
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38
AF35
AF36
AF37
AF38

UC1G

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

K13

VCC

K14

VCC

L13

VCC

N13

VCC

N14

VCC

N30

VCC

N31

VCC

N32

VCC

N35

VCC

N36

VCC

N37

VCC

N38

VCC

P13

VCC

SKL-H_BGA1440

EV = 1 ?

R

@

SKYLAKE_HAL O

BGA1440

7 OF 14

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC_SENSE

VSS_SENSE

V32
V33
V34
V35
V36
V37
V38
W13
W14
W29
W30
W31
W32
W35
W36
W37
W38
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
L14
P29
P30
P31
P32
P33
P34
P35
P36
R13
R31
R32
R33
R34
R35
R36
R37
R38
T29
T30
T31
T32
T35
T36
T37
T38
U29
U30
U31
U32
U33
U34
U35
U36
V13
V14
V31
P14

Trace Length < 25 mils

AG37
AG38

VCCSENSE <81>

VSSSENSE <81>

B

BG34
BG35
BG36
BH33
BH34
BH35
BH36
BH37
BH38

BJ37
BJ38
BL36
BL37

BM36
BM37
BN36
BN37
BN38
BP37
BP38
BR37
BT37
BE38
BF13
BF14
BF29
BF30
BF31
BF32
BF35
BF36
BF37
BF38
BG29
BG30
BG31
BG32
BG33
BC36
BC37
BC38
BD13
BD14
BD29
BD30
BD31
BD32
BD33
BD34
BD35
BD36
BE31
BE32
BE37

UC1H

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

SKL-H_BGA1440

@

SKYLAKE_HAL O

BGA1440

8 OF 14

REV = 1

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

Rev_0. 53

?

C

PWR remove VCCGT 3/10

Reserve resistor to Gnd

AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BE33
BE34
BE35
BE36

12

RC67

@

0_0402_5%

D

SKYLAKE_HAL O

AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35

AJ36
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AL13
AL29
AL30
AL31
AL32
AL35
AL36
AL37
AL38

AM13
AM14
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AN13
AN14
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38

AP13
AP14
AP29
AP30
AP31
AP32
AP35
AP36
AP37
AP38

AR29
AR30
AR31
AR32
AR33
AR34
AR35
AR36

AT14
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38

AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38

UC1N

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

SKL-H_BGA1440

REV = 1

@

BGA1440

DEL VCCGT net 3/16

4 OF 14

1

VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX

VCCGT_SENSE

VSSGTX_SENSE

VSSGT_SENSE

VCCGTX_SENSE

E

AF29
AF30
AF31
AF32
AF33
AF34
AG13
AG14
AG31
AG32
AG33
AG34

EDS:Rail is unconnected for Processors w ithout GT3/4.

AG35
AG36
AH13
AH14
AH29
AH30
AH31
AH32
AJ13
AJ14

AH38
AH35
AH37
AH36

Trace Length < 25 mils

?

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

A

B

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

C

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

SKL-H(5/9)Power,SVID

SKL-H(5/9)Power,SVID

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

D

Date: Sheet o f

SKL-H(5/9)Power,SVID

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

E

1.0

1.0

10 103Monday, January 09, 2017

10 103Monday, January 09, 2017

10 103Monday, January 09, 2017

1.0

A

B

C

CPU_CORE/VCCGT/VCCSA decoupling capacitor place to PWR side

D

E

+1.0V_VCCST

1 2

+1.0VS_VCCSTG

+1.2V_VDDQ

+1.2V_VDDQ

RC40 0_0402_5%@

(1.0VS)

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

CC21

CC22

2

1 2

@

RC41 0_0603_5%

1 2

RC42 0_0402_5%@

1 1

2 2

3 3

+1.0V_VCCSFR

+1.0V_VCCST

1

CC23
1U_0402_6.3V6K

2

+VDDQ_CLK

10U_0603_6.3V6M

1

CC24

2

(1.2V)

+1.2V_VCCPLL_OC

1U_0402_6.3V6K

1

CC25

2

1 2

CC20 1U_0402_6.3V6K

Place at Back Side

BSC Side
Y

12

1U_0402_6.3V6K

1

CC26

2

Place at Back Side
BH13/G11

RVP11 47u*1,10u*7,1u*3
CAP place on PWR side.

RVP11
PWR NEED PROVIDE

0.95V FOR VCCIO

+VCCSA

+VCCIO

K29
K30
K31
K32
K33
K34
K35

M29
M30
M31
M32
M33
M34
M35
M36

AG12

G15
G17
G19
G21
H15
H16
H17
H19
H20
H21
H26
H27

J30

L31
L32
L35
L36
L37
L38

J15
J16
J17
J19
J20
J21
J26
J27

UC1I

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

SKL-H_BGA1440

EV = 1

R

@

SKYLAKE_HALO

BGA1440

9 OF 14

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDQC

VCCPLL_OC
VCCPLL_OC

VCCST
VCCSTG
VCCSTG

VCCPLL
VCCPLL

VCCSA_SENSE
VSSSA_SENSE

VCCIO_SENSE

VSSIO_SENSE

+1.2V_VDDQ

AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6

Y12
BH13

G11

H30
H29

120mA

G30
H28

145mA

J28

M38
M37

H14
J14

check PH/PL on pwr side ??
0219

?

VCCSA_SENSE
VSSSA_SENSE

VCCIO_SENSE
VSSIO_SENSE

+VDDQ_CLK
+1.2V_VCCPLL_OC

+1.0V_VCCST
+1.0VS_VCCSTG

+1.0V_VCCSFR

VCCSA_SENSE <81>
VSSSA_SENSE <81>

VCCIO_SENSE <80>
VSSIO_SENSE <80>

NOTE:
VCCPLL_OC is allowed to be turned off
during S3 & DS3 if it is not powered
directly from VDDQ

+1.2V_VDDQ

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CC27

CC28

2

1

1

CC29

2

2

10U_0603_6.3V6M

1

CC30

1

CC31

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CC33

CC32

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CC34

2

10U_0603_6.3V6M

1

CC35

CC36

2

22U_0603_6.3V6M

CC37

1

1

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

CC38

22U_0603_6.3V6M

CC39

1

2

CC40

1

2

+VCCIO

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CC41

2

2

10U_0603_6.3V6M

1

CC42

2

22U_0603_6.3V6M

CC69

1

CC43

1

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

CC70

1

2

22U_0603_6.3V6M

CC71

CC72

1

2

Place at Back SidePlace at Back Side Follow ORB 3/20

4 4

A

+1.35V_VDDQ_CPU : 10UF/6.3V/0603 *10
update CRB cap QTY

22UF/6.3V/0603 * 4

B

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/02/01 2017/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

SKL-H(6/9)POWER

SKL-H(6/9)POWER

SKL-H(6/9)POWER

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

11 103Monday, January 09, 2017

11 103Monday, January 09, 2017

11 103Monday, January 09, 2017

E

1.0

1.0

1.0

A

B

C

D

E

BR7

BP7

BN9
BN7
BN4
BN2

BM9
BM6
BM2

BH9
BH8
BH5
BH4
BH1

BE6
BD9

C17
C13

BT9
BT5

C9

SKYLAKE_HALO

UC1L

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL-H_BGA1440

REV = 1

@

BGA1440

2 OF 14

1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS

SKYLAKE_HALO

UC1J

C25
C23
C21
C19
C15
C11
C8
C5
BM29
BM25
BM18
BM11
BM8
BM7
BM5
BM3
BL38
BL35
BL13
BL6
BK25
BK22
BK13
BK6
BJ30
BJ29
BJ15
BJ12
BH11
BH10
BH7
BH6
BH3
BH2
BG37
BG14
BG6
BF34
BF6
BE30
BE5
BE4
BE3
BE2
BE1
BD38
BD37
BD12
BD11
BD10
BD8
BD7
BD6
BC33
BC14
BC13
BC6
BB30
BB29
BB6
BB5

C2
BT36
BT35
BT4
BT3
BR38

?

T27PAD @
T28PAD @
T29PAD @

EDRAM

CRB EDRAM

OPC_RCOMP
OPCE_RCOMP
OPCE_RCOMP2

BJ17
BJ19

BJ20
BK17
BK19
BK20

BL16

BL17

BL18

BL19

BL20

BL21
BM17
BN17

BJ23

BJ26

BJ27
BK23
BK26
BK27

BL23

BL24

BL25

BL26

BL27

BL28
BM24

BL15
BM16

BL22
BM22

BP15
BR15

BT15
BP16

BR16

BT16

BN15
BM15

BP17
BN16

BM14

BL14

BJ35

BJ36

AT13

AW13

AU13
AY13

BT29
BR25
BP25

SKL-H_BGA1440

@

BGA1440

VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VCCOPC_SENSE
VSSOPC_SENSE

RSVD
RSVD

VCCEOPIO
VCCEOPIO
VCCEOPIO

RSVD
RSVD
RSVD

VCCEOPIO_SENSE
VSSEOPIO_SENSE

RSVD
RSVD

VCC_OPC_1P8
VCC_OPC_1P8

RSVD
RSVD

ZVM#
MSM#

ZVM2#
MSM2#

OPC_RCOMP
OPCE_RCOMP
OPCE_RCOMP2

REV = 1

0 OF 14

1

?

SKYLAKE_HALO

UC1F

Y9
Y8
Y7

V6

U6

T9
T8
T7
T5
T4
T3
T2
T1

P6

N9
N8
N7
N6
N5
N4
N3
N2
N1

K9
K8
K7
K5
K4
K3
K2

SKL-H_BGA1440

@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA1440

6 OF 14

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NCTFVSS

K1
J36
J33
J32
J25
J22
J18
J10
J7
J4
H35
H32
H25
H22
H18
H12
H11
G28
G26
G24
G23
G22
G20
G18
G16
G14
G12
G10
G9
G8
G6
G5
G4
F36
F31
F29
F27
F25
F23
F21
F19
F17
F15
F13
F11
F9
F8
F5
F4
F3
F2
E38
E35
E34
E9
E4
D33
D30
D28
D26
D24
D22
D20
D18
D16
D14
D12
D10
D9
D6
D3
C37
C31
C29
C27

D38

?REV = 1

BA38
BA37
BA12
BA11
BA10

AY34
AY33
AY14

AY12
AW30
AW29
AW12

AW5
AW4
AW3
AW2

AW1
AV38
AV37
AU34
AU33
AU12
AU11
AU10

AT30

AT29
AR38

AR37
AR14
AR13

AP34
AP33
AP12
AP11
AP10

AN30
AN29
AN12

AM38
AM37
AM12

AL34

AL33

AL14

AL12

AL10

Y38
Y37
Y14

1 1

2 2

3 3

4 4

Y13
Y11
Y10

W34
W33
W12

V30
V29
V12

U38
U37

T34
T33
T14
T13
T12
T11
T10

R30
R29
R12

P38

P37

P12
N34

N33
N12

N11
N10

M14
M13
M12

L34

L33

L30

L29

K38

K11

K10

W5
W4
W3
W2
W1

M6

BB4
BB3
BB2
BB1

BA9
BA8
BA7
BA6

AU9
AU8
AU7
AU6

AT6

AR5
AR4
AR3
AR2
AR1

AP9
AP8

AN6
AN5

AM5
AM4
AM3
AM2
AM1

AL9
AL8
AL7
AL4

B9

SKYLAKE_HALO

UC1M

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL-H_BGA1440

REV = 1

@

BGA1440

1

3 OF 14

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS

AK30
AK29
AK4
AJ38
AJ37
AJ6
AJ5
AJ4
AJ3
AJ2
AJ1
AH34
AH33
AH12
AH6
AG30
AG29
AG11
AG10
AG8
AG7
AG6
AF14
AF13
AF12
AF4
AF3
AF2
AF1
AE34
AE33
AE6
AD30
AD29
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AC38
AC37
AC12
AC6
AC5
AC4
AC3
AC2
AC1
AB34
AB33
AB6
AA30
AA29
AA12
A30
A28
A26
A24
A22
A20
A18
A16
A14
A12
A10
A9
A6

B37
B3
A34
A4
A3

?

BT32
BT26
BT24
BT21
BT18
BT14
BT12

BR36
BR34
BR29
BR26
BR24
BR21
BR18
BR14
BR12

BP34
BP33
BP29
BP26
BP24
BP21
BP18
BP14
BP12

BN34
BN31
BN30
BN29
BN24
BN21
BN20
BN19
BN18
BN14
BN12

BM38
BM35
BM28
BM27
BM26
BM23
BM21
BM13
BM12

BL29
BK29
BK15
BK14

BJ32

BJ31

BJ25

BJ22
BH14
BH12

BG38
BG13
BG12
BF33
BF12
BE29

BC34
BC12
BB12

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/02/01 2017/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

SKL-H(8/9)GND

SKL-H(8/9)GND

SKL-H(8/9)GND

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1.0

1.0

1.0

12 103Monday, January 09, 2017

12 103Monday, January 09, 2017

12 103Monday, January 09, 2017

E

A

B

C

D

E

1 1

2 2

3 3

PROC_TRIGIN_R<24>

PROC_TRIGOUT_R<24>

1 2

RC45 30_0402_1%

PROC_TRIGIN_R
PROC_TRIGOUT

BR1

BT2

BN35

J24

H24
BN33
BL34

N29

R14
AE29
AA14

A36
A37

H23

J23
F30

E30
B30

C30

BR35
BR31
BH30

D1

E1
E3
E2

G3

J3

UC1K

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD
RSVD

RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD

PROC_TRIGIN
PROC_TRIGOUT

RSVD
RSVD

RSVD
RSVD

RSVD
RSVD

RSVD
RSVD
RSVD

SKL-H_BGA1440

@

SKYLAKE_HALO

BGA1440

11 OF 14

EV = 1

Rev_0 .53

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD
RSVD

VSS

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD
RSVD

RSVD
RSVD

VSS

RSVD_TP
RSVD_TP

RSVD
RSVD
RSVD

NCTF
NCTF
NCTF
NCTF
NCTF
NCTF

BM33
BL33

BJ14
BJ13

BK28
BJ28

BJ18
BJ16

BK16

BK24
BJ24

BK21
BJ21

BT17
BR17

BK18
BJ34

BJ33

G13
AJ8
BL31

NCTF_0

B2

NCTF_1

B38

NCTF_2

BP1

NCTF_3

BR2

NCTF_4

C1

NCTF_5

C38

?R

T13 PAD@
T14 PAD@
T15 PAD@
T16 PAD@
T17 PAD@
T18 PAD@

4 4

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/02/01 2017/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

SKL-H(9/9)RSVD

SKL-H(9/9)RSVD

SKL-H(9/9)RSVD

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1.0

1.0

1.0

13 103Monday, January 09, 2017

13 103Monday, January 09, 2017

13 103Monday, January 09, 2017

E

5

4

3

2

1

CHANNEL-A

TOP DIMM1

REVERSE TYPE

Interleaved Memory

TOP: JDIMM1 CONN Non-ECC DIMM

D D

12

@

12

RD1
0_0402_ 5%

RD3

@

0_0402_ 5%

12

@

12

RD4
0_0402_ 5%

RD5
0_0402_ 5%

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL A :
WRITE ADDRESS: 0XA0
READ ADDRESS: 0XA1
SA0 = 0; SA1 = 0; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S
STRETCH GOAL IS 2133 MT/S

C C

B B

Layout Note:
Place near JDIMM1.257,259

+2.5V +0.6VS_VTT

10U_0603_6.3V6M

1

1

CD3

2

2

Layout Note:
PLACE THE CAP near JDIMM1. 164

+0.6V_DDR_ VREFCA

2

CD11
.1U_0402 _16V7K

1

10uF*2
1uF*2

1U_0402_6.3V6K

10U_0603_6.3V6M

1U_0402_6.3V6K

1

1

CD5

CD4

CD6

2

2

2.2uF*1

0.1uF*1

2

CD12

2.2U_040 2_6.3V6M

1

+3VS+3VS+3VS

12

@

@

12

Layout Note:
Place near JDIMM1.258

1

2

PLACE NEAR TO PIN

+3VS

.1U_0402_16V7K

2

1

RD2
0_0402_ 5%

SA2_CHA_ DIM1SA1_CHA_ DIM1SA0_CHA _DIM1

RD6
0_0402_ 5%

10U_0603_6.3V6M

CD7

2

CD1

1

+1.2V_VDDQ

@

+0.6V_DDR_ VREFCA

10uF*2
1uF*1

1U_0402_6.3V6K

10U_0603_6.3V6M

1

1

CD9

CD8

2

2

2.2U_0402_6.3V6M

CD2

+3VS

DDR_A_D[0..15]<7,15>
DDR_A_D[16..31]<7,15>
DDR_A_D[32..47]<7,15>
DDR_A_D[48..63]<7,15>

JDIMM1B

STD

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND

SP07001CU00

LCN_DAN05 -Q0526-0103

CONN@

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19

VPP1
VPP2

141
142
147
148
153
154
159
160
163

258

VTT

257
259

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

261

GND

+1.2V_VDDQ

+0.6VS_VTT

+2.5V

+1.2V_VDDQ

need PU when use E CC dimm

DDR_DRAMRST#_R

RD7

240_040 2_1%

12

2

1

+1.2V_VDDQ

.1U_0402_16V7K

CD10

XEMC@

PLACE NEAR TO SODIMM

(5.2 mm)

DDR_A_CLK 0<7>
DDR_A_CLK #0<7>
DDR_A_CLK 1<7>
DDR_A_CLK #1<7>

DDR_A_CKE 0<7>
DDR_A_CKE 1<7>

DDR_A_CS# 0<7>
DDR_A_CS# 1<7>

DDR_A_ODT0<7>
DDR_A_ODT1<7>

DDR_A_BG0<7,1 5>
DDR_A_BG1<7,1 5>
DDR_A_BA0<7,15>
DDR_A_BA1<7,15>

DDR_A_MA0<7,15>
DDR_A_MA1<7,15>
DDR_A_MA2<7,15>
DDR_A_MA3<7,15>
DDR_A_MA4<7,15>
DDR_A_MA5<7,15>
DDR_A_MA6<7,15>
DDR_A_MA7<7,15>
DDR_A_MA8<7,15>
DDR_A_MA9<7,15>
DDR_A_MA1 0<7,15>
DDR_A_MA1 1<7,15>
DDR_A_MA1 2<7,15>
DDR_A_MA1 3<7,15>
DDR_A_W E#<7,15>
DDR_A_CAS #<7,15>
DDR_A_RAS #<7,15>

DDR_A_ACT#<7,15 >
DDR_A_PAR<7,15>

DDR_A_ALERT#<7,15>

DDR_DRAMRST#_R<15,16,17,20>

PCH_SMBDA TA_R<15,16,17,20 ,40>
PCH_SMBCL K_R<15,16,17,2 0,40>

DIMM1_CHA_ EVENT#

For ECC DIMM

DDR_A_CLK 0
DDR_A_CLK #0
DDR_A_CLK 1
DDR_A_CLK #1

DDR_A_CKE 0
DDR_A_CKE 1

DDR_A_CS# 0
DDR_A_CS# 1

DDR_A_ODT0
DDR_A_ODT1

DDR_A_BG0
DDR_A_BG1
DDR_A_BA0
DDR_A_BA1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA1 0
DDR_A_MA1 1
DDR_A_MA1 2
DDR_A_MA1 3
DDR_A_W E#
DDR_A_CAS #
DDR_A_RAS #

DDR_A_ACT#
DDR_A_PAR

DDR_A_ALERT#
DDR_DRAMRST#_R

PCH_SMBDA TA_R
PCH_SMBCL K_R

SA2_CHA_ DIM1
SA1_CHA_ DIM1
SA0_CHA_ DIM1

JDIMM1A

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_W E#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

SP07001CU00

LCN_DAN05 -Q0526-0103

conn need link

CONN@

STD

DQS0(T)

DQS0#(C)

DQS1(T)

DQS1#(C)

DQS2(T)

DQS2#(C)

DQS3(T)

DQS3#(C)

DQS4(T)

DQS4#(C)

DQS5(T)

DQS5#(C)

DQS6(T)

DQS6#(C)

DQS7(T)

DQS7#(C)

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DDR_A_D5

8

DQ0

DDR_A_D0

7

DQ1

DDR_A_D2

20

DQ2

DDR_A_D3

21

DQ3

DDR_A_D1

4

DQ4

DDR_A_D4

3

DQ5

DDR_A_D6

16

DQ6

DDR_A_D7

17

DQ7

DDR_A_DQS 0

13

DDR_A_DQS #0

11

DDR_A_D8

28

DQ8

DDR_A_D12

29

DQ9

DDR_A_D14

41

DDR_A_D11

42

DDR_A_D9

24

DDR_A_D13

25

DDR_A_D10

38

DDR_A_D15

37

DDR_A_DQS 1

34

DDR_A_DQS #1

32

DDR_A_D17

50

DDR_A_D20

49

DDR_A_D23

62

DDR_A_D18

63

DDR_A_D16

46

DDR_A_D21

45

DDR_A_D19

58

DDR_A_D22

59

DDR_A_DQS 2

55

DDR_A_DQS #2

53

DDR_A_D25

70

DDR_A_D28

71

DDR_A_D30

83

DDR_A_D31

84

DDR_A_D24

66

DDR_A_D29

67

DDR_A_D27

79

DDR_A_D26

80

DDR_A_DQS 3

76

DDR_A_DQS #3

74

DDR_A_D32

174

DDR_A_D37

173

DDR_A_D35

187

DDR_A_D39

186

DDR_A_D36

170

DDR_A_D33

169

DDR_A_D34

183

DDR_A_D38

182

DDR_A_DQS 4

179

DDR_A_DQS #4

177

DDR_A_D44

195

DDR_A_D45

194

DDR_A_D42

207

DDR_A_D43

208

DDR_A_D41

191

DDR_A_D40

190

DDR_A_D46

203

DDR_A_D47

204

DDR_A_DQS 5

200

DDR_A_DQS #5

198

DDR_A_D48

216

DDR_A_D50

215

DDR_A_D53

228

DDR_A_D55

229

DDR_A_D52

211

DDR_A_D49

212

DDR_A_D54

224

DDR_A_D51

225

DDR_A_DQS 6

221

DDR_A_DQS #6

219

DDR_A_D60

237

DDR_A_D57

236

DDR_A_D62

249

DDR_A_D58

250

DDR_A_D56

232

DDR_A_D61

233

DDR_A_D59

245

DDR_A_D63

246

DDR_A_DQS 7

242

DDR_A_DQS #7

240

DDR_A_DQS 0 <7,15>

DDR_A_DQS #0 <7,15>

DDR_A_DQS 1 <7,15>

DDR_A_DQS #1 <7,15>

DDR_A_DQS 2 <7,15>

DDR_A_DQS #2 <7,15>

DDR_A_DQS 3 <7,15>

DDR_A_DQS #3 <7,15>

DDR_A_DQS 4 <7,15>

DDR_A_DQS #4 <7,15>

DDR_A_DQS 5 <7,15>

DDR_A_DQS #5 <7,15>

DDR_A_DQS 6 <7,15>

DDR_A_DQS #6 <7,15>

DDR_A_DQS 7 <7 ,15>

DDR_A_DQS #7 <7,15>

Layout Note:
Place near JDIMM1

10uF*6

uF*8

1
330uF*1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD17

CD16

1

1

2

2

A A

CD19

CD18

1

2

5

CD20

1

2

CD21

1

1

2

2

+1.2V_VDDQ+1.2V_VDDQ

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

CD22

CD23

1

1

2

2

@

@

1U_0402_6.3V6K

1

1

CD24

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD26

CD25

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CD27

2

4

1U_0402_6.3V6K

1

1

CD29

CD28

2

2

+1.2V_VDDQ

1U_0402_6.3V6K

1

CD30

2

1

+

CD31

CD32
330U_D3_ 2.5VY_R6M

SGA0000 6A00

2

@

3

+1.2V_VDDQ

DIMM Side

+0.6V_DDR_ VREFCA

RD8

Issued Date

Issued Date

Issued Date

1 2

1 2

1K_0402 _1%

RD10
1K_0402 _1%

2

CD14
.1U_0402 _16V7K

1

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

2

CD13
.1U_0402 _16V7K

1

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

1 2

RD9

2_0402_ 1%

Deciphered Date

Deciphered Date

Deciphered Date

2

CPU Side

+0.6V_VRE FCA

1

CD15

0.022U_0 402_25V 7K

2

RD11

24.9_0402_1%

1 2

VREF traces should be at least 20 mils
wide with 20 mils spacing to other
signals

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P12-DDRIV_CHA: DIMM0

P12-DDRIV_CHA: DIMM0

P12-DDRIV_CHA: DIMM0

Document Number Re v

Document Number Re v

Document Number Re v

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

1.0

1.0

14 103Monday, January 09, 2017

14 103Monday, January 09, 2017

14 103Monday, January 09, 2017

1.0

5

4

3

2

1

(5.2 mm)

DDR_A_CLK 2
DDR_A_CLK #2
DDR_A_CLK 3
DDR_A_CLK #3

DDR_A_CKE 2
DDR_A_CKE 3

DDR_A_CS# 2
DDR_A_CS# 3

DDR_A_ODT2
DDR_A_ODT3

DDR_A_BG0
DDR_A_BG1
DDR_A_BA0
DDR_A_BA1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA1 0
DDR_A_MA1 1
DDR_A_MA1 2
DDR_A_MA1 3
DDR_A_W E#
DDR_A_CAS #
DDR_A_RAS #

DDR_A_ACT#
DDR_A_PAR

DDR_A_ALERT#
DIMM2_CHA_ EVENT#
DDR_DRAMRST#_R

PCH_SMBDA TA_R

PCH_SMBCL K_R

SA2_CHA_ DIM2
SA1_CHA_ DIM2
SA0_CHA_ DIM2

JDIMM2A

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_W E#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

SP07001D800

LCN_DAN05 -Q0526-0102

STD

CONN@

DQS0(T)

DQS0#(C)

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQS1(T)

DQS1#(C)

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQS2(T)

DQS2#(C)

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS3(T)

DQS3#(C)

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS4(T)

DQS4#(C)

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQS5(T)

DQS5#(C)

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQS6(T)

DQS6#(C)

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS7(T)

DQS7#(C)

conn need link

DDR_A_D5

8

DQ0

DDR_A_D0

7

DQ1

DDR_A_D2

20

DQ2

DDR_A_D3

21

DQ3

DDR_A_D1

4

DQ4

DDR_A_D4

3

DQ5

DDR_A_D6

16

DQ6

DDR_A_D7

17

DQ7

DDR_A_DQS 0

13

DDR_A_DQS #0

11

DDR_A_D8

28

DQ8

DDR_A_D12

29

DQ9

DDR_A_D14

41

DDR_A_D11

42

DDR_A_D9

24

DDR_A_D13

25

DDR_A_D10

38

DDR_A_D15

37

DDR_A_DQS 1

34

DDR_A_DQS #1

32

DDR_A_D17

50

DDR_A_D20

49

DDR_A_D23

62

DDR_A_D18

63

DDR_A_D16

46

DDR_A_D21

45

DDR_A_D19

58

DDR_A_D22

59

DDR_A_DQS 2

55

DDR_A_DQS #2

53

DDR_A_D25

70

DDR_A_D28

71

DDR_A_D30

83

DDR_A_D31

84

DDR_A_D24

66

DDR_A_D29

67

DDR_A_D27

79

DDR_A_D26

80

DDR_A_DQS 3

76

DDR_A_DQS #3

74

DDR_A_D32

174

DDR_A_D37

173

DDR_A_D35

187

DDR_A_D39

186

DDR_A_D36

170

DDR_A_D33

169

DDR_A_D34

183

DDR_A_D38

182

DDR_A_DQS 4

179

DDR_A_DQS #4

177

DDR_A_D44

195

DDR_A_D45

194

DDR_A_D42

207

DDR_A_D43

208

DDR_A_D41

191

DDR_A_D40

190

DDR_A_D46

203

DDR_A_D47

204

DDR_A_DQS 5

200

DDR_A_DQS #5

198

DDR_A_D48

216

DDR_A_D50

215

DDR_A_D53

228

DDR_A_D55

229

DDR_A_D52

211

DDR_A_D49

212

DDR_A_D54

224

DDR_A_D51

225

DDR_A_DQS 6

221

DDR_A_DQS #6

219

DDR_A_D60

237

DDR_A_D57

236

DDR_A_D62

249

DDR_A_D58

250

DDR_A_D56

232

DDR_A_D61

233

DDR_A_D59

245

DDR_A_D63

246

DDR_A_DQS 7

242

DDR_A_DQS #7

240

DDR_A_DQS 0 <7,14>

DDR_A_DQS #0 <7,14>

DDR_A_DQS 1 <7,14>

DDR_A_DQS #1 <7,14>

DDR_A_DQS 2 <7,14>

DDR_A_DQS #2 <7,14>

DDR_A_DQS 3 <7,14>

DDR_A_DQS #3 <7,14>

DDR_A_DQS 4 <7,14>

DDR_A_DQS #4 <7,14>

DDR_A_DQS 5 <7,14>

DDR_A_DQS #5 <7,14>

DDR_A_DQS 6 <7,14>

DDR_A_DQS #6 <7,14>

DDR_A_DQS 7 <7,14>

DDR_A_DQS #7 <7,14>

12

+1.2V_VDDQ

STD

DDR_A_CLK 2<7>

DDR_A_CLK #2<7>
DDR_A_CLK 3<7>
DDR_A_CLK #3<7>

DDR_A_CKE 2<7>

DDR_A_CKE 3<7>

DDR_A_CS# 2<7>

DDR_A_CS# 3<7>

DDR_A_ODT2<7>

DDR_A_ODT3<7>

DDR_A_BG0<7,14>

DDR_A_BG1<7,14>

DDR_A_BA0<7,14>

DDR_A_BA1<7,14>

DDR_A_MA0<7,14 >

DDR_A_MA1<7,14 >

DDR_A_MA2<7,14 >

DDR_A_MA3<7,14 >

DDR_A_MA4<7,14 >

DDR_A_MA5<7,14 >

DDR_A_MA6<7,14 >

DDR_A_MA7<7,14 >

DDR_A_MA8<7,14 >

DDR_A_MA9<7,14 >

DDR_A_MA1 0<7,14>

DDR_A_MA1 1<7,14>

DDR_A_MA1 2<7,14>

DDR_A_MA1 3<7,14>

DDR_A_W E#<7,14>

DDR_A_CAS #<7,14>

DDR_A_RAS #<7,14>

DDR_A_ACT#<7,14>

DDR_A_PAR<7,14>

DDR_A_ALERT#<7,14>

DDR_DRAMRST#_R<14,16,17,20>

PCH_SMBDA TA_R<14,16,17,20 ,40>
PCH_SMBCL K_R<14,16,17,2 0,40>

For ECC DIMM

CHANNEL-A

BOT: JDIMM2 CONN

D D

C C

B B

12

RD12

@

0_0402_ 5%

12

RD15

@

0_0402_ 5%

@

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL A :
WRITE ADDRESS: 0XA2
READ ADDRESS: 0XA3
SA0 = 1; SA1 = 0; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S
STRETCH GOAL IS 2133 MT/S

Layout Note:
P

lace near JDIMM2.257,259

+2.5V

Layout Note:
PLACE THE CAP WITHIN 200 MILS
FROM THE JDIMM2

+0.6V_DDR_ VREFCA

2

CD42
.1U_0402 _16V7K

1

10uF*2
1uF*2

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

1

1

CD37

CD35

CD36

2

2

2

CD43

2.2U_040 2_6.3V6M

1

Layout Note:
Place near JDIMM2

1U_0402_6.3V6K

1

CD38

2

2.2uF*1

0.1uF*1

Non-ECC DIMM

12

RD13
0_0402_ 5%

12

RD16

@

0_0402_ 5%

Layout Note:
Place near JDIMM2.258

BOT DIMM2

+3VS+3VS+3VS

12

RD14

@

0_0402_ 5%

SA2_CHA_ DIM2SA1_CHA_ DIM2SA0_CHA_ DIM2

12

RD17

@

0_0402_ 5%

+0.6VS_VTT

PLACE NEAR TO PIN

10uF*2
1uF*1

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

1

2

CD41

CD40

CD39

2

2

+3VS

.1U_0402_16V7K

2.2U_0402_6.3V6M

2

2

CD34

CD33

1

1

Interleaved Memory

DDR_A_D[0..15]<7,14>
DDR_A_D[16..31]<7,14>
DDR_A_D[32..47]<7,14>
DDR_A_D[48..63]<7,14>

JDIMM2B

CONN@

STD

+1.2V_VDDQ

+0.6V_DDR_ VREFCA

+3VS

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND

SP07001D800

LCN_DAN05 -Q0526-0102

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19

VPP1
VPP2

141
142
147
148
153
154
159
160
163

258

VTT

257
259

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

261

GND

+1.2V_VDDQ

+0.6VS_VTT

+2.5V

+1.2V_VDDQ

need PU when use E CC dimm

RD18

240_040 2_1%

10uF*6

+1.2V_VDDQ +1.2V_VDDQ

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD45

CD44

1

1

1

2

2

2

A A

5

1uF*8

10U_0603_6.3V6M

10U_0603_6.3V6M

CD46

CD47

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD48

1

2

10U_0603_6.3V6M

@

@

CD50

CD51

CD49

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD53

CD52

2

2

1U_0402_6.3V6K

1

1

1

CD54

CD55

CD56

2

2

2

4

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD57

CD59

CD58

2

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

3

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P13-DDRIV_CHA: DIMM1

P13-DDRIV_CHA: DIMM1

P13-DDRIV_CHA: DIMM1

Document Number Re v

Document Number Re v

Document Number Re v

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

15 103Monday, January 09, 2017

15 103Monday, January 09, 2017

15 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

CHANNEL-B

TOP: JDIMM3 CONN

D D

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

C C

B B

A A

12

RD19

0_0402_ 5%

@

12

RD22

@

0_0402_ 5%

SPD ADDRESS FOR CHANNEL B :
WRITE ADDRESS: 0XA4
READ ADDRESS: 0XA3
SA0 = 0; SA1 = 1; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S
STRETCH GOAL IS 2133 MT/S

Layout Note:
Place near JDIMM3.257,259

10uF*2
1uF*2

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1

1

CD62

2

2

Layout Note:
PLACE THE CAP WITHIN 200 MILS
FROM THE JDIMM3

+0.6V_DDRB _VREFCA

2

CD69
.1U_0402 _16V7K

1

Layout Note:
Place near JDIMM3

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

1

1

CD63

CD64

CD65

2

2

2.2uF*1

0.1uF*1

2

CD70

2.2U_040 2_6.3V6M

1

10U_0603_6.3V6M

10U_0603_6.3V6M

CD74

CD75

CD73

1

1

2

2

Non-ECC DIMM

12

RD20

@

0_0402_ 5%

12

RD23

@

0_0402_ 5%

10uF*6
1uF*8
330uF*1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD76

CD77

1

1

1

2

2

2

+3VS+3VS+3VS

12

@

12

Layout Note:
Place near JDIMM3.258

+0.6VS_VTT+2.5V

PLACE NEAR TO PIN

+3VS

10U_0603_6.3V6M

CD78

CD79

1

2

@

TOP DIMM3

RD21

0_0402_ 5%

SA2_CHB_ DIM3SA1_CHB_ DIM3SA0_CHB_DIM3

RD24

@

0_0402_ 5%

10uF*2
1uF*1

10U_0603_6.3V6M

1U_0402_6.3V6K

10U_0603_6.3V6M

1

1

1

CD67

CD68

CD66

2

2

2

.1U_0402_16V7K

2.2U_0402_6.3V6M

2

2

CD60

CD61

1

1

+1.2V_VDDQ+1.2V_VDDQ

10U_0603_6.3V6M

CD80

1

2

@

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

1

CD84

CD83

2

2

Interleaved Memory

DDR_B_D[0..15]<7,17>
DDR_B_D[16..31]<7,17>
DDR_B_D[32..47]<7,17>
DDR_B_D[48..63]<7,17>

+1.2V_VDDQ

+0.6V_DDRB _VREFCA

+3VS

JDIMM3B

CONN@

STD

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND

SP07001D100

S SOCKET L CN DAN05-Q0 926-0103 260P DDR4

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19

VPP1
VPP2

141
142
147
148
153
154
159
160
163

258

VTT

257
259

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

261

GND

+1.2V_VDDQ

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

1

CD86

CD87

CD85

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD88

CD89

2

2

1

+

CD90

CD91
330U_D3_ 2.5VY_R6M

SGA0000 6A00

2

+1.2V_VDDQ

+0.6VS_VTT

+2.5V

+1.2V_VDDQ

need PU when use E CC dimm

2

@

1

2

1

RD25

240_040 2_1%

DDR_DRAMRST#_R

PLACE NEAR TO SODIMM

CD71
.1U_0402 _16V7K

CD81
.1U_0402 _16V7K

REVERSE TYPE

DDR_B_CLK 0<7>

DDR_B_CLK #0<7>

DDR_B_CLK 1<7>

DDR_B_CLK #1<7>

DDR_B_CKE 0<7>

DDR_B_CKE 1<7>

DDR_B_CS# 0<7>

DDR_B_CS# 1<7>

DDR_B_ODT0<7>

DDR_B_ODT1<7>

DDR_B_BG0<7,17>

DDR_B_BG1<7,17>

DDR_B_BA0<7,17>

DDR_B_BA1<7,17>

DDR_B_MA0<7,17 >

DDR_B_MA1<7,17 >

DDR_B_MA2<7,17 >

DDR_B_MA3<7,17 >

DDR_B_MA4<7,17 >

DDR_B_MA5<7,17 >

DDR_B_MA6<7,17 >

DDR_B_MA7<7,17 >

DDR_B_MA8<7,17 >

DDR_B_MA9<7,17 >

DDR_B_MA1 0<7,17>

DDR_B_MA1 1<7,17>

DDR_B_MA1 2<7,17>

DDR_B_MA1 3<7,17>

DDR_B_W E#<7,17>

DDR_B_CAS #<7,17>

DDR_B_RAS #<7,17>

DDR_B_ACT#<7,17>

DDR_B_PAR<7,17>

+1.2V_VDDQ

2

1

RD26
1K_0402 _1%

RD28
1K_0402 _1%

DDR_DRAMRST#_R<14,15,17,20>

.1U_0402_16V7K

CD119

XEMC@

+0.6V_DDRB _VREFCA

DDR_B_ALERT#<7,17>

PCH_SMBDA TA_R<14,15,17,20 ,40>
PCH_SMBCL K_R<14,15,17,2 0,40>

DIMM Side

12

+1.2V_VDDQ

1 2

1 2

DDR_B_CLK 0
DDR_B_CLK #0
DDR_B_CLK 1
DDR_B_CLK #1

DDR_B_CKE 0
DDR_B_CKE 1

DDR_B_CS# 0
DDR_B_CS# 1

DDR_B_ODT0
DDR_B_ODT1

DDR_B_BG0
DDR_B_BG1
DDR_B_BA0
DDR_B_BA1

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA1 0
DDR_B_MA1 1
DDR_B_MA1 2
DDR_B_MA1 3
DDR_B_W E#
DDR_B_CAS #
DDR_B_RAS #

DDR_B_ACT#
DDR_B_PAR

DDR_B_ALERT#
DIMM3_CHB_ EVENT#
DDR_DRAMRST#_R

PCH_SMBDA TA_R

PCH_SMBCL K_R

SA2_CHB_ DIM3
SA1_CHB_ DIM3
SA0_CHB_ DIM3

For ECC DIMM

1 2

RD27

2_0402_ 1%

(9.2 mm)

JDIMM3A

STD

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_W E#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

SP07001D100

S SOCKET L CN DAN05-Q0 926-0103 260P DDR4

CPU Side

+0.6V_B_ VREFDQ

REF traces should be at least 20 mils

V

1

2

1 2

wide with 20 mils spacing to other
signals

CD82

0.022U_0 402_25V 7K

RD29

24.9_0402_1%

CONN@

DQS0(T)

DQS0#(C)

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQS1(T)

DQS1#(C)

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQS2(T)

DQS2#(C)

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS3(T)

DQS3#(C)

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS4(T)

DQS4#(C)

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQS5(T)

DQS5#(C)

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQS6(T)

DQS6#(C)

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS7(T)

DQS7#(C)

conn need link

DDR_B_D0

8

DQ0

DDR_B_D1

7

DQ1

DDR_B_D7

20

DQ2

DDR_B_D3

21

DQ3

DDR_B_D5

4

DQ4

DDR_B_D4

3

DQ5

DDR_B_D2

16

DQ6

DDR_B_D6

17

DQ7

DDR_B_DQS 0

13

DDR_B_DQS #0

11

DDR_B_D9

28

DQ8

DDR_B_D14

29

DQ9

DDR_B_D13

41

DDR_B_D15

42

DDR_B_D8

24

DDR_B_D10

25

DDR_B_D11

38

DDR_B_D12

37

DDR_B_DQS 1

34

DDR_B_DQS #1

32

DDR_B_D17

50

DDR_B_D18

49

DDR_B_D19

62

DDR_B_D21

63

DDR_B_D16

46

DDR_B_D22

45

DDR_B_D23

58

DDR_B_D20

59

DDR_B_DQS 2

55

DDR_B_DQS #2

53

DDR_B_D25

70

DDR_B_D30

71

DDR_B_D29

83

DDR_B_D24

84

DDR_B_D28

66

DDR_B_D27

67

DDR_B_D31

79

DDR_B_D26

80

DDR_B_DQS 3

76

DDR_B_DQS #3

74

DDR_B_D39

174

DDR_B_D35

173

DDR_B_D36

187

DDR_B_D32

186

DDR_B_D38

170

DDR_B_D34

169

DDR_B_D37

183

DDR_B_D33

182

DDR_B_DQS 4

179

DDR_B_DQS #4

177

DDR_B_D41

195

DDR_B_D45

194

DDR_B_D46

207

DDR_B_D43

208

DDR_B_D40

191

DDR_B_D44

190

DDR_B_D42

203

DDR_B_D47

204

DDR_B_DQS 5

200

DDR_B_DQS #5

198

DDR_B_D51

216

DDR_B_D52

215

DDR_B_D55

228

DDR_B_D53

229

DDR_B_D48

211

DDR_B_D54

212

DDR_B_D49

224

DDR_B_D50

225

DDR_B_DQS 6

221

DDR_B_DQS #6

219

DDR_B_D56

237

DDR_B_D57

236

DDR_B_D60

249

DDR_B_D63

250

DDR_B_D61

232

DDR_B_D59

233

DDR_B_D58

245

DDR_B_D62

246

DDR_B_DQS 7

242

DDR_B_DQS #7

240

DDR_B_DQS 0 <7,17>

DDR_B_DQS #0 <7,17>

DDR_B_DQS 1 <7,17>

DDR_B_DQS #1 <7,17>

DDR_B_DQS 2 <7,17>

DDR_B_DQS #2 <7,17>

DDR_B_DQS 3 <7,17>

DDR_B_DQS #3 <7,17>

DDR_B_DQS 4 <7,17>

DDR_B_DQS #4 <7,17>

DDR_B_DQS 5 <7,17>

DDR_B_DQS #5 <7,17>

DDR_B_DQS 6 <7,17>

DDR_B_DQS #6 <7,17>

DDR_B_DQS 7 <7,17>

DDR_B_DQS #7 <7,17>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

5

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P14-DDRIV_CHB: DIMM0

P14-DDRIV_CHB: DIMM0

P14-DDRIV_CHB: DIMM0

Document Number Re v

Document Number Re v

Document Number Re v

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

16 103Monday, January 09, 2017

16 103Monday, January 09, 2017

16 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

CHANNEL-B

BOT: JDIMM4 CONN Non-ECC DIMM

D D

12

RD30

@

0_0402_ 5%

12

RD33

@

0_0402_ 5%

12

RD31
0_0402_ 5%

12

RD34

0_0402_ 5%

@

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL B :
WRITE ADDRESS: 0XA6
READ ADDRESS: 0XA7
SA0 = 1; SA1 = 1; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S

C C

B B

STRETCH GOAL IS 2133 MT/S

Layout Note:
P

lace near JDIMM4.257,259

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CD94

CD95

2

2

+0.6V_DDRB _VREFCA

2

CD101
.1U_0402 _16V7K

1

10uF*2
1uF*2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

CD96

2

2

CD102

2.2U_040 2_6.3V6M

1

CD97

2.2uF*1

0.1uF*1

+2.5V

Layout Note:
PLACE THE CAP WITHIN 200 MILS
FROM THE JDIMM4

+3VS+3VS+3 VS

@

12

@

12

Layout Note:
Place near JDIMM4.258

+0.6VS_VTT

10U_0603_6.3V6M

1

CD98

2

BOT DIMM4 (9.2 mm)

Interleaved Memory

DDR_B_D[0..15]<7,16>

RD32

0_0402_ 5%

SA2_CHB_ DIM4SA1_CHB_ DIM4SA0_CHB_ DIM4

RD35

@

0_0402_ 5%

10uF*2
1uF*1

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

1

CD99

CD100

2

DDR_B_D[16..31]<7,16 >
DDR_B_D[32..47]<7,16 >
DDR_B_D[48..63]<7,16 >

+1.2V_VDDQ

+3VS

.1U_0402_16V7K

2.2U_0402_6.3V6M

+0.6V_DDRB _VREFCA

2

2

CD92

CD93

1

1

LACE NEAR TO PIN

P

JDIMM4B

STD

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND

SP07001DO00

LCN_DAN05 -Q0926-0102

CONN@

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19

VPP1
VPP2

141
142
147
148
153
154
159
160
163

258

VTT

257
259

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

261

GND

+1.2V_VDDQ

+0.6VS_VTT
+2.5V

RD36

+1.2V_VDDQ

need PU when use E CC dimm

240_040 2_1%

+1.2V_VDDQ

DDR_DRAMRST#_R

PLACE NEAR TO SODIMM

Layout Note:
Place near JDIMM4

STD

CONN@

DDR_B_CLK 2<7>
DDR_B_CLK #2<7>

DDR_B_CLK 3<7>

DDR_B_CLK #3<7>
DDR_B_CKE 2<7>

DDR_B_CKE 3<7>
DDR_B_CS# 2<7>

DDR_B_CS# 3<7>

DDR_B_ODT2<7>
DDR_B_ODT3<7>

DDR_B_BG0<7,16>
DDR_B_BG1<7,16>
DDR_B_BA0<7,16>
DDR_B_BA1<7,16>

DDR_B_MA0<7,16 >
DDR_B_MA1<7,16 >
DDR_B_MA2<7,16 >
DDR_B_MA3<7,16 >
DDR_B_MA4<7,16 >
DDR_B_MA5<7,16 >
DDR_B_MA6<7,16 >
DDR_B_MA7<7,16 >
DDR_B_MA8<7,16 >
DDR_B_MA9<7,16 >
DDR_B_MA1 0<7,16>
DDR_B_MA1 1<7,16>
DDR_B_MA1 2<7,16>
DDR_B_MA1 3<7,16>
DDR_B_W E#<7,16>
DDR_B_CAS #<7,16>
DDR_B_RAS #<7,16>

DDR_B_ACT#<7,16>
DDR_B_PAR<7,16>

DDR_B_ALERT#<7,16>

DDR_DRAMRST#_R<14,15,16, 20>

PCH_SMBDA TA_R<14,15,16,20 ,40>
PCH_SMBCL K_R<14,15,16,2 0,40>

DIMM4_CHB_ EVENT#

12

DDR_B_CLK 2
DDR_B_CLK #2
DDR_B_CLK 3
DDR_B_CLK #3

DDR_B_CKE 2
DDR_B_CKE 3

DDR_B_CS# 2
DDR_B_CS# 3

DDR_B_ODT2
DDR_B_ODT3

DDR_B_BG0
DDR_B_BG1
DDR_B_BA0
DDR_B_BA1

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA1 0
DDR_B_MA1 1
DDR_B_MA1 2
DDR_B_MA1 3
DDR_B_W E#
DDR_B_CAS #
DDR_B_RAS #

DDR_B_ACT#

DDR_B_PAR
DDR_B_ALERT#

DDR_DRAMRST#_R

PCH_SMBDA TA_R
PCH_SMBCL K_R

SA2_CHB_ DIM4
SA1_CHB_ DIM4
SA0_CHB_ DIM4

For ECC DIMM

.1U_0402_16V7K

2

CD120

1

XEMC@

JDIMM4A

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_W E#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

SP07001DO00

LCN_DAN05 -Q0926-0102

STD

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQS0(T)

DQS0#(C)

DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQS1(T)

DQS1#(C)

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQS2(T)

DQS2#(C)

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS3(T)

DQS3#(C)

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS4(T)

DQS4#(C)

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQS5(T)

DQS5#(C)

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQS6(T)

DQS6#(C)

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS7(T)

DQS7#(C)

conn need link

DDR_B_D0

8

DDR_B_D1

7

DDR_B_D7

20

DDR_B_D3

21

DDR_B_D5

4

DDR_B_D4

3

DDR_B_D2

16

DDR_B_D6

17

DDR_B_DQS 0

13

DDR_B_DQS #0

11

DDR_B_D9

28

DDR_B_D14

29

DDR_B_D13

41

DDR_B_D15

42

DDR_B_D8

24

DDR_B_D10

25

DDR_B_D11

38

DDR_B_D12

37

DDR_B_DQS 1

34

DDR_B_DQS #1

32

DDR_B_D17

50

DDR_B_D18

49

DDR_B_D19

62

DDR_B_D21

63

DDR_B_D16

46

DDR_B_D22

45

DDR_B_D23

58

DDR_B_D20

59

DDR_B_DQS 2

55

DDR_B_DQS #2

53

DDR_B_D25

70

DDR_B_D30

71

DDR_B_D29

83

DDR_B_D24

84

DDR_B_D28

66

DDR_B_D27

67

DDR_B_D31

79

DDR_B_D26

80

DDR_B_DQS 3

76

DDR_B_DQS #3

74

DDR_B_D39

174

DDR_B_D35

173

DDR_B_D36

187

DDR_B_D32

186

DDR_B_D38

170

DDR_B_D34

169

DDR_B_D37

183

DDR_B_D33

182

DDR_B_DQS 4

179

DDR_B_DQS #4

177

DDR_B_D41

195

DDR_B_D45

194

DDR_B_D46

207

DDR_B_D43

208

DDR_B_D40

191

DDR_B_D44

190

DDR_B_D42

203

DDR_B_D47

204

DDR_B_DQS 5

200

DDR_B_DQS #5

198

DDR_B_D51

216

DDR_B_D52

215

DDR_B_D55

228

DDR_B_D53

229

DDR_B_D48

211

DDR_B_D54

212

DDR_B_D49

224

DDR_B_D50

225

DDR_B_DQS 6

221

DDR_B_DQS #6

219

DDR_B_D56

237

DDR_B_D57

236

DDR_B_D60

249

DDR_B_D63

250

DDR_B_D61

232

DDR_B_D59

233

DDR_B_D58

245

DDR_B_D62

246

DDR_B_DQS 7

242

DDR_B_DQS #7

240

DDR_B_DQS 0 <7,16>

DDR_B_DQS #0 <7,16>

DDR_B_DQS 1 <7,16>

DDR_B_DQS #1 <7,16>

DDR_B_DQS 2 <7,16>

DDR_B_DQS #2 <7,16>

DDR_B_DQS 3 <7,16>

DDR_B_DQS #3 <7,16>

DDR_B_DQS 4 <7,16>

DDR_B_DQS #4 <7,16>

DDR_B_DQS 5 <7,16>

DDR_B_DQS #5 <7,16>

DDR_B_DQS 6 <7,16>

DDR_B_DQS #6 <7,16>

DDR_B_DQS 7 <7,16>

DDR_B_DQS #7 <7,16>

10uF*6

+1.2V_VDDQ +1.2V_VDDQ

10U_0603_6.3V6M

1

2

A A

10U_0603_6.3V6M

10U_0603_6.3V6M

CD103

CD104

1

1

2

2

5

1uF*8

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD105

CD106

1

1

2

2

@

CD107

CD109

CD108

1

1

1

2

2

2

1U_0402_6.3V6K

@

CD110

1

2

1U_0402_6.3V6K

1

1

CD111

CD112

2

2

1

1

CD113

2

4

1

CD115

CD114

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD118

CD116

CD117

2

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

3

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P15-DDRIV_CHB: DIMM1

P15-DDRIV_CHB: DIMM1

P15-DDRIV_CHB: DIMM1

Document Number Re v

Document Number Re v

Document Number Re v

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

17 103Monday, January 09, 2017

17 103Monday, January 09, 2017

17 103Monday, January 09, 2017

1.0

1.0

1.0

A

UH1

QJGE@

S IC GLSSKU QJGE D1 FCBGA 837P PCH-H

SA00008RM70

IO Board (left side)

UH1

1 1

QLF5@

S IC GL82CM238 QLF5 D1 BGA 837P PCH-H

SA0000ACM10

SR30U@

UH1

S IC GL82CM238 SR30U D1 BGA PCH-H ABO !

SA0000ACM30

back

3D CAM

U3 Board (right side)

front

U3 Board (right side)
back

USB3_PTX_DRX_N2<32>
USB3_PTX_DRX_P2<32>
USB3_PRX_DTX_N2<32>
USB3_PRX_DTX_P2<32>

USB3_PTX_DRX_N6<34>
USB3_PTX_DRX_P6<34>
USB3_PRX_DTX_N6<34>
USB3_PRX_DTX_P6<34>
USB3_PTX_DRX_N5<32>
USB3_PTX_DRX_P5<32>
USB3_PRX_DTX_N5<32>
USB3_PRX_DTX_P5<32>

USB3_PTX_DRX_P4<32>
USB3_PTX_DRX_N4<32>
USB3_PRX_DTX_P4<32>
USB3_PRX_DTX_N4<32>

CHECK ACER DVR for port use

front panel sp ec 5"
int cable 16"

DMI_CTX_PRX_N0<8>
DMI_CTX_PRX_P0<8>

2 2

#546884 P.231 PCIE_RCOMPN/PCIE_RCOMPP
BO=4 W=12~15 S=12 R=100ohm

PCIE_PRX_DTX_N1<32>

CARD READER

WIGI G

WLAN

LAN

3 3

Thunderbol t

PCIE_PRX_DTX_P1<32>

PCIE_PTX_C_DRX_N1<32>

PCIE_PTX_C_DRX_P1<32>
PCIE_PTX_C_DRX_N2<31>
PCIE_PTX_C_DRX_P2<31>

PCIE_PRX_DTX_N2<31>

PCIE_PRX_DTX_P2<31>

PCIE_PRX_DTX_N3<31>

PCIE_PRX_DTX_P3<31>

PCIE_PTX_C_DRX_N3<31>
PCIE_PTX_C_DRX_P3<31>

PCIE_PRX_DTX_N4<30>

PCIE_PRX_DTX_P4<30>

PCIE_PTX_C_DRX_N4<30>
PCIE_PTX_C_DRX_P4<30>

PCIE_PRX_DTX_N5<68>

PCIE_PRX_DTX_P5<68>

PCIE_PTX_C_DRX_N5<68>
PCIE_PTX_C_DRX_P5<68>

PCIE_PRX_DTX_N6<68>

PCIE_PRX_DTX_P6<68>

PCIE_PTX_C_DRX_N6<68>
PCIE_PTX_C_DRX_P6<68>

PCIE_PRX_DTX_N7<68>

PCIE_PRX_DTX_P7<68>

PCIE_PTX_C_DRX_N7<68>
PCIE_PTX_C_DRX_P7<68>

PCIE_PRX_DTX_N8<68>

PCIE_PRX_DTX_P8<68>

PCIE_PTX_C_DRX_N8<68>
PCIE_PTX_C_DRX_P8<68>

DMI_CRX_PTX_N0<8>

DMI_CRX_PTX_P0<8>
DMI_CTX_PRX_N1<8>
DMI_CTX_PRX_P1<8>

DMI_CRX_PTX_N1<8>

DMI_CRX_PTX_P1<8>
DMI_CTX_PRX_N2<8>
DMI_CTX_PRX_P2<8>

DMI_CRX_PTX_N2<8>

DMI_CRX_PTX_P2<8>
DMI_CTX_PRX_N3<8>
DMI_CTX_PRX_P3<8>

DMI_CRX_PTX_N3<8>

DMI_CRX_PTX_P3<8>

1 2

RH5 100_0402_1%

12

CH58 .1U_0402_16V7K

12

CH55 .1U_0402_16V7K

12

CH56 .1U_0402_16V7K

12

CH57 .1U_0402_16V7K

12

CH3 .1U_0402_16V7K

12

CH4 .1U_0402_16V7K

12

CH1 .1U_0402_16V7K

12

CH2 .1U_0402_16V7K

12

CH62 0.22U_0402_16V7KTBT@

12

CH59 0.22U_0402_16V7KTBT@

12

CH61 0.22U_0402_16V7KTBT@

12

CH60 0.22U_0402_16V7KTBT@

12

CH65 0.22U_0402_16V7KTBT@

12

CH64 0.22U_0402_16V7KTBT@

12

CH66 0.22U_0402_16V7KTBT@

12

CH63 0.22U_0402_16V7KTBT@

B

DMI_CTX_PRX_N0
DMI_CTX_PRX_P0
DMI_CRX_PTX_N0
DMI_CRX_PTX_P0
DMI_CTX_PRX_N1
DMI_CTX_PRX_P1
DMI_CRX_PTX_N1
DMI_CRX_PTX_P1
DMI_CTX_PRX_N2
DMI_CTX_PRX_P2
DMI_CRX_PTX_N2
DMI_CRX_PTX_P2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
DMI_CRX_PTX_N3
DMI_CRX_PTX_P3

PCIE_RCOMPN
PCIE_RCOMPP

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4
PCIE_PRX_DTX_N5
PCIE_PRX_DTX_P5
PCIE_PTX_DRX_N5
PCIE_PTX_DRX_P5
PCIE_PRX_DTX_N6
PCIE_PRX_DTX_P6
PCIE_PTX_DRX_N6
PCIE_PTX_DRX_P6
PCIE_PRX_DTX_N7
PCIE_PRX_DTX_P7
PCIE_PTX_DRX_N7
PCIE_PTX_DRX_P7
PCIE_PRX_DTX_N8
PCIE_PRX_DTX_P8
PCIE_PTX_DRX_N8
PCIE_PTX_DRX_P8

UH1F

C11

USB3_1_TXN

B11

USB3_1_TXP

B7

USB3_1_RXN

A7

USB3_1_RXP

B12

USB3_2_TXN/SSIC_1_TXN

A12

USB3_2_TXP/SSIC_1_TXP

C8

USB3_2_RXN/SSIC_1_RXN

B8

USB3_2_RXP/SSIC_1_RXP

B15

USB3_6_TXN

C15

USB3_6_TXP

K15

USB3_6_RXN

K13

USB3_6_RXP

B14

USB3_5_TXN

C14

USB3_5_TXP

G13

USB3_5_RXN

H13

USB3_5_RXP

D13

USB3_3_TXP/SSIC_2_TXP

C13

USB3_3_TXN/SSIC_2_TXN

A9

USB3_3_RXP/SSIC_2_RXP

B10

USB3_3_RXN/SSIC_2_RXN

B13

USB3_4_TXP

A14

USB3_4_TXN

G11

USB3_4_RXP

E11

USB3_4_RXN

S

KL-H-PCH_BGA837

@

UH1B

L27

DMI_RXN0

N27

DMI_RXP0

C27

DMI_TXN0

B27

DMI_TXP0

E24

DMI_RXN1

G24

DMI_RXP1

B28

DMI_TXN1

A28

DMI_TXP1

G27

DMI_RXN2

E26

DMI_RXP2

B29

DMI_TXN2

C29

DMI_TXP2

L29

DMI_RXN3

K29

DMI_RXP3

B30

DMI_TXN3

A30

DMI_TXP3

B18

PCIE_RCOMPN

C17

PCIE_RCOMPP

H15

PCIE1_RXN/USB3_7_RXN

G15

PCIE1_RXP/USB3_7_RXP

A16

PCIE1_TXN/USB3_7_TXN

B16

PCIE1_TXP/USB3_7_TXP

B19

PCIE2_TXN/USB3_8_TXN

C19

PCIE2_TXP/USB3_8_TXP

E17

PCIE2_RXN/USB3_8_RXN

G17

PCIE2_RXP/USB3_8_RXP

L17

PCIE3_RXN/USB3_9_RXN

K17

PCIE3_RXP/USB3_9_RXP

B20

PCIE3_TXN/USB3_9_TXN

C20

PCIE3_TXP/USB3_9_TXP

E20

PCIE4_RXN/USB3_10_RXN

G19

PCIE4_RXP/USB3_10_RXP

B21

PCIE4_TXN/USB3_10_TXN

A21

PCIE4_TXP/USB3_10_TXP

K19

PCIE5_RXN

L19

PCIE5_RXP

D22

PCIE5_TXN

C22

PCIE5_TXP

G22

PCIE6_RXN

E22

PCIE6_RXP

B22

PCIE6_TXN

A23

PCIE6_TXP

L22

PCIE7_RXN

K22

PCIE7_RXP

C23

PCIE7_TXN

B23

PCIE7_TXP

K24

PCIE8_RXN

L24

PCIE8_RXP

C24

PCIE8_TXN

B24

PCIE8_TXP

S

KL-H-PCH_BGA837

@

REV = 1.3

REV = 1.3

SPT-H_PCH

USB

LPC/eSPI

SATA

SPT-H_PCH

DMI

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

6 OF 12

USB 2.0

PCIe/USB 3

GPP_F15/USB2_OCB_4
GPP_F16/USB2_OCB_5
GPP_F17/USB2_OCB_6
GPP_F18/USB2_OCB_7

2 OF 12

GPP_G19/SMI#
GPP_G18/NMI#

GPP_E6/DEVSLP2
GPP_E5/DEVSLP1
GPP_E4/DEVSLP0

GPP_F9/DEVSLP7
GPP_F8/DEVSLP6
GPP_F7/DEVSLP5
GPP_F6/DEVSLP4
GPP_F5/DEVSLP3

USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9

USB2P_9
USB2N_10
USB2P_10
USB2N_11
USB2P_11
USB2N_12
USB2P_12
USB2N_13
USB2P_13
USB2N_14
USB2P_14

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

USB2_COMP

USB2_VBUSSENSE

RSVD_AB13

USB2_ID

GPD7/RSVD

C

LPC_AD0

?

?

AT22

LPC_AD1

AV22

LPC_AD2

AT19

LPC_AD3

BD16

LPC_FRAME#

BE16
BA17

SERIRQ
LPC_PIRQA#

AW17
AT17
BC18

LPC_CLK

BC17

CK_LPC_TPM_R

AV19
M45

N43

AE45
AG43
AG42
AB39
AB36
AB43
AB42
AB41

AF5
AG7

USB20_N2

AD5

USB20_P2

AD7
AG8
AG10

USB20_N4

AE1

USB20_P4

AE2

USB20_N5

AC2

USB20_P5

AC3

USB20_N6

AF2

USB20_P6

AF3

USB20_N7

AB3

USB20_P7

AB2

USB20_N8

AL8

USB20_P8

AL7

USB20_N9

AA1

USB20_P9

AA2

USB20_N10

AJ8

USB20_P10

AJ7

USB20_N11

W2

USB20_P11

W3

USB20_N12

AD3

USB20_P12

AD2
V2
V1
AJ11
AJ13

USB_OC0#

AD43

USB_OC1#

AD42

USB_OC2#

AD39

USB_OC3#

AC44

USB_OC4#

Y43

USB_OC5#

Y41

USB_OC6#

W44

USB_OC7#

W43

USB2_COMP

AG3

USB2_VBUSSENSE

AD10
AB13

USB2_ID

AG2

USB2_COMP

BD14

SE= 50 ohm
Spacing = 15 mils
Max lenght = 1000 mils

LPC_AD0 <38,40>
LPC_AD1 <38,40>
LPC_AD2 <38,40>
LPC_AD3 <38,40>

LPC_FRAME# <38,40>
SERIRQ <38,40>

ESPI_RST# <38>

RH2 22_0402_5%
RH4 22_0402_5%TPM@

12
12

DEVSLP2 <29>
DEVSLP0 <28>

DEVSLP1 <28>
DEVSLP3 <29>

USB20_N2 <32>
USB20_P2 <32>

USB20_N4 <32>
USB20_P4 <32>
USB20_N5 <32>
USB20_P5 <32>
USB20_N6 <33>
USB20_P6 <33>
USB20_N7 <31>
USB20_P7 <31>
USB20_N8 <65>
USB20_P8 <65>
USB20_N9 <65>
USB20_P9 <65>
USB20_N10 <33>
USB20_P10 <33>
USB20_N11 <34>
USB20_P11 <34>
USB20_N12 <33>
USB20_P12 <33>

RH6 113_0402_1%

To JSSD3
To JSSD1

SW confirmed 0422
To JSSD2

To JSSD4

1 2
1 2

@

RH149 0_0402_5%

1 2

@

RH150 0_0402_5%

LPC Bus

LPC : +3.3V

To TPM
del EC_KBRST#_R

no coding

USB3 LEFT

USB3 RIGHT

USB3 RIGHT

TP

BT

TS (Reseve)

FHD CAM

Int. KB

EYE TRACKER

Int. KB BL

D

LPC_CLK_R <38>
CK_LPC_TPM <40>

To EC

SERIRQ

DG requierment 8.2k PH +3VS
CRB 10K PH +3vs

LPC_PIRQA#

ESPI / LPC Bus
ESPI : +1.8V
LPC : +3.3V

1 2

RH1 10K_0402_5%

RH122 10K_0402_5%

reference PDG1.0 50-30

USB_OC0#
USB_OC1#
USB_OC3#
USB_OC2#

USB_OC5#
USB_OC4#
USB_OC6#
USB_OC7#

RPH1

10K_0804_8P4R_5%

RPH15

10K_0804_8P4R_5%

@

12

18
27
36
45

18
27
36
45

E

+3VS

+3VS

+3VALW_PCH_PRIM

+3VALW_PCH_PRIM

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(1/7)DMI,PCIE,USB

PCH(1/7)DMI,PCIE,USB

PCH(1/7)DMI,PCIE,USB

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

E

18 103Monday, January 09, 2017

18 103Monday, January 09, 2017

18 103Monday, January 09, 2017

1.0

1.0

1.0

A

PCH PLTRST Buf f er

on-board devic e driving it to opposite direct i on duri ng

B

C

D

E

RPH3 and close UH6

RPH3

PCH_SPI_SOPCH_SPI_SO_0_R

1 8

PCH_SPI_SIPCH_SPI_SI_0_R

2 7

PCH_SPI_CLKPCH_SPI_CLK_0_R

3 6

PCH_SPI_IO3PCH_SPI_IO3_0_R

To SPI ROM

UH1A

@

PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_CS#0
PCH_SPI_CLK

PCH_SPI_IO2
PCH_SPI_IO3

1

IN1

2

IN2

12

GPP_F13

DGPU_PRSNT#

0
1

+3VS

A

EC_PME#_R

BD17
AG15

AG14
AF17
AE17

AR19
AN17

BB29
BE30
BD31
BC31

AW31

BC29
BD30
AT31

AN36
AL39
AN41
AN38
AH43
AG44

1 2

@

RH19 0_0402_5%

CH5

.1U_0402_16V7K

1 2

5

UH5

P

PLT_RST_BUF#

4

O

G

3

RH34
10K_0402_5%

GPP_A11/PME#
RSVD

RSVD
RSVD
RSVD

TP2
TP1

SPI0_MOSI
SPI0_MISO
SPI0_CS0#
SPI0_CLK
SPI0_CS1#
SPI0_IO2
SPI0_IO3
SPI0_CS2#

GPP_D1/SPI1_CLK
GPP_D0/SPI1_CS#
GPP_D3/SPI1_MOSI
GPP_D2/SPI1_MISO
GPP_D22/SPI1_IO3
GPP_D21/SPI1_IO2

S

KL-H-PCH_BGA837

@

12

1 1

EC_PME#<30,38>

1 2

RH115 0_0402_5%

SPI ROM
0127 Jason

TBT_CIO_PLUG_EVENT #<68>

RTD3_CIO_PWR_EN<68>

RTD3_USB_PW R_EN<68>

TBT_FORCE_PW R<68>

TBT_BATLOW#<68>

AR GPIO , confirm SW 0422

2 2

PLT_RST#

MC74VHC1G08DFT2G_SC70-5

3 3

DGPU_PRSNT#

DIS
UMA

4 4

SPT-H_PCH

PLT_RST_BUF# <28,29,30,31,32,41,53,68>

RH24
100K_0402_5%

SSD Slot_1
PCIe/SATA

SSD Slot_3
SATA

SSD Slot_1
PCIe/SATA

SSD Slot_2
PCIe/SATA

GPP_B13/PLTRST#

GPP_G16/GSXCLK

GPP_G12/GSXDOUT

GPP_G13/GSXSLOAD

GPP_G14/GSXDIN

GPP_G15/GSXSRESET#

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

GPP_H18/SML4ALERT#

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H15/SML3ALERT#

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H12/SML2ALERT#

GPP_H11/SML2DATA

GPP_H10/SML2CLK

1 OF 12

REV = 1.3

PCIE_PTX_DRX_P11<28>
PCIE_PTX_DRX_N11<28>

PCIE_PRX_DTX_P11<28>
PCIE_PRX_DTX_N11<28>

SATA_PTX_DRX_N1B<29>
SATA_PTX_DRX_P1B<29>
SATA_PRX_DTX_N1B<29>
SATA_PRX_DTX_P1B< 29>

PCIE_PTX_DRX_P12<28>
PCIE_PTX_DRX_N12<28>

PCIE_PRX_DTX_P12<28>

PCIE_PRX_DTX_N12<28>
PCIE_PTX_DRX_P20<28>
PCIE_PTX_DRX_N20<28>

PCIE_PRX_DTX_P20<28>

PCIE_PRX_DTX_N20<28>
PCIE_PTX_DRX_P19<28>
PCIE_PTX_DRX_N19<28>

PCIE_PRX_DTX_P19<28>

PCIE_PRX_DTX_N19<28>

INTRUDER#

?

BB27
P43

R39
R36
R42
R41

AF41
AE44
BC23
BD24

BC36
BE34
BD39
BB36
BA35
BC35
BD35
AW35
BD34

BE11

B

SM_INTRUDER#

PLT_RST#

Del I2C_TS_INT#
Del I2C_TP_INT#

for server and WS use

PAD

RH13 1M_0402_5%

PCIE_PTX_DRX_P11

PCIE_PTX_DRX_N11

PCIE_PRX_DTX_P11

PCIE_PRX_DTX_N11

DGPU_PRSNT#

PCIE_PTX_DRX_P12

PCIE_PTX_DRX_N12

PCIE_PRX_DTX_P12

PCIE_PRX_DTX_N12

PCIE_PTX_DRX_P20
PCIE_PTX_DRX_N20
PCIE_PRX_DTX_P20

PCIE_PRX_DTX_N20

PCIE_PTX_DRX_P19

PCIE_PTX_DRX_N19

PCIE_PRX_DTX_P19

PCIE_PRX_DTX_N19

PLT_RST# <38,40>

T23

@

1 2

AV2
AV3

AW2

R44
R43
U39
N42

U43
U42
U41

M44

U36
P44
T45
T44

B33
C33
K31

L31

AB33
AB35
AA44
AA45

B38
C38
D39
E37

C36
B36
G35
E35

A35
B35
H33
G33

J45
K44
N38
N39
H44
H43

L39

L37

+RTCVCC

UH1C

CL_CLK
CL_DATA
CL_RST#

GPP_G8/FAN_PWM_0
GPP_G9/FAN_PWM_1
GPP_G10/FAN_PWM_2
GPP_G11/FAN_PWM_3

GPP_G0/FAN_TACH_0
GPP_G1/FAN_TACH_1
GPP_G2/FAN_TACH_2
GPP_G3/FAN_TACH_3
GPP_G4/FAN_TACH_4
GPP_G5/FAN_TACH_5
GPP_G6/FAN_TACH_6
GPP_G7/FAN_TACH_7

PCIE11_TXP
PCIE11_TXN
PCIE11_RXP
PCIE11_RXN

GPP_F10/SCLOCK
GPP_F11/SLOAD
GPP_F13/SDATAOUT0
GPP_F12/SDATAOUT1

PCIE14_TXN/SATA1B_TXN
PCIE14_TXP/SATA1B_TXP
PCIE14_RXN/SATA1B_RXN
PCIE14_RXP/SATA1B_RXP

PCIE13_TXN/SATA0B_TXN
PCIE13_TXP/SATA0B_TXP
PCIE13_RXN/SATA0B_RXN
PCIE13_RXP/SATA0B_RXP

PCIE12_TXP
PCIE12_TXN
PCIE12_RXP
PCIE12_RXN
PCIE20_TXP/SATA7_TXP
PCIE20_TXN/SATA7_TXN
PCIE20_RXP/SATA7_RXP
PCIE20_RXN/SATA7_RXN
PCIE19_TXP/SATA6_TXP
PCIE19_TXN/SATA6_TXN
PCIE19_RXP/SATA6_RXP
PCIE19_RXN/SATA6_RXN

S

KL-H-PCH_BGA837

@

REV = 1.3

SPI ROM ( 16MByte )

PCH_SPI_CS#0

PCH_SPI_IO2_0_R

RH21,RH22 place to within 1100 mil of SPIO_MOSI/SPI0_IO2 pin for XDP

XDP_SPI_SI<6>
XDP_SPI_IO2<6>

SPT-H_PCH

CLINK

FAN

3 OF 12

C

PCH_SPI_CLK_0_R

PCIe/SATA

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_F0/SATAXPCIE3/SATAGP3
GPP_F1/SATAXPCIE4/SATAGP4
GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6
GPP_F4/SATAXPCIE7/SATAGP7

HOST

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4 5

15_0804_8P4R_5%

1 2

RH30 15_0402_5%

UH6

1

/CS

2

DO(IO1)

/HOLD(IO3)

3

/WP(IO2)

4

GND

W25Q128FVSIQ_SO8

PCIE9_RXN/SATA0A_RXN
PCIE9_RXP/SATA0A_RXP

PCIE9_TXN/SATA0A_TXN
PCIE9_TXP/SATA0A_TXP

PCIE10_RXN/SATA1A_RXN
PCIE10_RXP/SATA1A_RXP

PCIE10_TXN/SATA1A_TXN
PCIE10_TXP/SATA1A_TXP

PCIE15_RXN/SATA2_RXN
PCIE15_RXP/SATA2_RXP
PCIE15_TXN/SATA2_TXN
PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN
PCIE16_RXP/SATA3_RXP
PCIE16_TXN/SATA3_TXN
PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN
PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_TXN
PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN
PCIE18_RXP/SATA5_RXP
PCIE18_TXN/SATA5_TXN
PCIE18_TXP/SATA5_TXP

GPP_F21/EDP_BKLTCTL

DI(IO0)

XEMC@

1 2

RH35
0_0402_5%

1 2

RH21 1K_0402_1%CMC@

1 2

RH22 1K_0402_1%CMC@

GPP_E8/SATALED#

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THERMTRIP#

PECI

PM_SYNC

PLTRST_PROC#

PM_DOWN

PCH_SPI_IO2PCH_SPI_IO2_0_R

+3VALW_SPI

8

VCC

7
6

CLK

5

G31
H31
C31
B31

G29
E29
C32
B32

F41
E41
B39
A39

D43
E42
A41
A40

H42
H40
E45
F45

K37
G37
G45
G44

AD44
AG36
AG35
AG39
AD35
AD31
AD38
AC43
AB44

W36
W35
W42

AJ3
AL3
AJ4
AK2
AH2

?

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

1 2

PCH_SPI_IO3_0_RPCH_SPI_SO_0_R
PCH_SPI_CLK_0_R
PCH_SPI_SI_0_R

XEMC@

1 2

CH7
10P_0402_50V8J

PCIE_PRX_DTX_N9
PCIE_PRX_DTX_P9
PCIE_PTX_DRX_N9
PCIE_PTX_DRX_P9

PCIE_PRX_DTX_N10
PCIE_PRX_DTX_P10
PCIE_PTX_DRX_N10
PCIE_PTX_DRX_P10

PCIE_PRX_DTX_N17

PCIE_PRX_DTX_P17

PCIE_PTX_DRX_N17

PCIE_PTX_DRX_P17

PCIE_PRX_DTX_N18

PCIE_PRX_DTX_P18

PCIE_PTX_DRX_N18

PCIE_PTX_DRX_P18

SATA_LED#
SATA_GP0
SATA_GP2

SATA_GP3
SATA_GP1

PCH_BKL_PW M
ENBKL

PCH_ENVDD

PCH_THERMTRIP#
PCH_PECI
H_PM_SYNC_R
PLTRST_CPU#

CH6
.1U_0402_16V7K

PCH_SPI_SI
PCH_SPI_IO2

RH25 100K_0402_5%@
RH26 100K_0402_5%@
RH159 100K_0402_5%@

1 2

RH23 620_0402_5%

1 2

RH121 12.1_0402_1%@
RH12 30_0402_1%

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Follow MOW 2015WW09

PCH_SPI_IO2

PCH_SPI_IO3

Follow MOW WW36
p

ull down with pre-ES1/ES1 samples

751 PU +3V

Functional Strap Definitions

SPI0_M OSI
int. PH
This strap should sample HIGH. There should NOT be any
on-board devic e driving it to opposite direct i on duri ng
strap sampling.

SPI0_M ISO
int. PH
This strap should sample HIGH. There should NOT be any

strap sampling.
SPI0_ IO2

int. PH
This strap should sample HIGH. There should NOT be any
on-board devic e driving it to opposite direct i on duri ng
strap sampling.

SPI0_ IO3
int. PH
This strap should sample HIGH. There should NOT be any
on-board devic e driving it to opposite direct i on duri ng
strap sampling.

GPP_H12
int. PD
This strap should sample LOW.

PCIE_PRX_DTX_N9 <28>
PCIE_PRX_DTX_P9 <28>
PCIE_PTX_DRX_N9 <28>
PCIE_PTX_DRX_P9 <28>

PCIE_PRX_DTX_N10 <28>
PCIE_PRX_DTX_P10 <28>
PCIE_PTX_DRX_N10 <28>
PCIE_PTX_DRX_P10 <28>

SATA_PRX_DTX_N2 <27>
SATA_PRX_DTX_P2 <27>
SATA_PTX_DRX_N2 <27>

SATA_PTX_DRX_P2 <27>

SATA_PRX_DTX_N3 <29>
SATA_PRX_DTX_P3 <29>
SATA_PTX_DRX_N3 <29>

SATA_PTX_DRX_P3 <29>

PCIE_PRX_DTX_N17 <28>
PCIE_PRX_DTX_P17 <28>
PCIE_PTX_DRX_N17 <28>
PCIE_PTX_DRX_P17 <28>

PCIE_PRX_DTX_N18 <28>
PCIE_PRX_DTX_P18 <28>
PCIE_PTX_DRX_N18 <28>
PCIE_PTX_DRX_P18 <28>

SATA_LED# <28>

SATA_GP0 <28>
SATA_GP2 <29>

SATA_GP3 <29>
SATA_GP1 <28>

1 2
1 2
1 2

12

PLTRST_CPU# <9>

PM_DOWN_R <9>

D

1 2

RH28 1K_0402_1%

1 2

RH29 1K_0402_1%@

1 2

RH32 1K_0402_1%

1 2

RH33 1K_0402_1%@

PCH_SPI_CS#0
PCH_SPI_IO2_0_R
PCH_SPI_IO3_0_R

SSD Slot_1
PCIe/SATA

HDD

SSD Slot_4
SATA

SSD Slot_2
PCIe/SATA

To JSSD1
To JSSD3

SW confirmed 0422

To JSSD4
To JSSD2

del PWM/ENVDD/ENBKL
check PL can del or not? 3/25

THERMTRIP# <9>
H_PECI <9,38>
H_PM_SYNC <9>

+3VALW_SPI

SCLK

SI/SIO0

SO/SIO1

VCC

+3VALW_SPI

8

PCH_SPI_CLK_0_R

6

PCH_SPI_SI_0_R

5

PCH_SPI_SO_0_R

2

SATA_LED#

RH160 10K_0402_5%

SATA_GP0
SATA_GP2
SATA_GP3
SATA_GP1

10K_0804_8P4R_5%

RPH14

+3VS

12

18
27
36
45

@

JROM1

1

CS#

3

WP#

7

HOLD#

4

GND

ACES_91960-0084N_MX25L3206EM2I

CONN@

CONN TO EC & CPU

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(2/7)SPI,SATA,XDP

PCH(2/7)SPI,SATA,XDP

PCH(2/7)SPI,SATA,XDP

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

E

1.0

1.0

19 103Monday, January 09, 2017

19 103Monday, January 09, 2017

19 103Monday, January 09, 2017

1.0

A

B

C

D

E

HDA for AUDIO

<38> ME_EN

<36> HDA_SDOUT_R
<36> HDA_BIT_CLK_R
<36> HDA_RST #_R
<36> HDA_SYNC_R

1 1

+3VALW_DSW

2 2

3 3

Functional Strap Definitions

SMBALERT# / GPP_C2
int. PD
0 = Disable Intel ME (TLS) (Default)
1 = Enable Intel ME (TLS)

SML0ALERT# / GPP_C5
int. PD
0 = LPC Is selected for EC. (Default)
1 = eSPI Is selected for EC.

SML1ALERT# / PCHHOT# / GPP_B23
int. PD

SPKR / GPP_B14
int. PD
0 = Disable “ Top S wap” mode. ( Def ault )
1 = Enable “ Top Swap” mode.

HDA_SDO
int. PD
0 = Enable security measures defined in the Flash

4 4

Descriptor. (Default)
1 = Disable Flash Descriptor Security (override).

DDPB_CTRLDATA / GPP_I6
int. PD
0 = Port B is not detected.
1 = Port B is detected. (Default)

<36> HDA_SDIN0

+3VALW_PCH_PRIM

RPH6

10K_0804_8P4R_5%

Follow 543016_SKL_U_Y_PDG_0_9

+3VALW_DSW

EC_RSMRST#

+RTCVCC

CRB 8.2K

1 2

RH40 10K_0402_5%

1 2

@

RH41 10K_0402_5%

1 2

RH42 1K_0402_5%

12

@

RH44 0_0402_5%

12

@

RH45 0_0402_5%

1

1 2

CH8 1U_0402_6.3V6K

1

1 2

CH9 1U_0402_6.3V6K

1
1

Place at RAM DOOR
(DVT 7./11)

SYS_RESET#

18

LAN_WAKE#

27

EC_RSMRST#

36

PCH_PWROK

45

PCH_DPWROK

PCH_PWROKSYS_PWROK

2

20K_0402_5%RH46

2

20K_0402_5%RH49

2

0_0603_5%@JCMOS1

2

0_0603_5%@JCMOS2

A

1 2

@

RH36 0_0402_5%

RPH5

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

HDA_SDIN0

PM_BATLOW#
AC_PRESENT_R

WAKE#

PCH_SRTCRST#

Remove CLR ME

PCH_RTCRST #

CLR CMOS

HDA_SDOUT
HDA_BIT_CLK
HDA_RST#
HDA_SYNC

<6> CPU_DISPA_SDO_R

<6> CPU_DISPA_SDI_R

<6> CPU_DISPA_BCLK_R

<26,38> PCH_PWROK

<6,38> EC_RSMRST#

(SO-DIMM,G-sensor)

(AUDIO,EC,VGA,)

+3VALW_PCH_PRIM

+3VALW_PCH_PRIM

DDPC_CTRLDATA / GPP_I8
int. PD
0 = Port C is not detected.
1 = Port C is detected. (Default)

DDPD_CTRLDATA / GPP_I10
int. PD
0 = Port D is not detected. (Default)
1 = Port D is detected.

1 2

@

RH142 4.7K_0402_5%

1 2

RH50 499_0402_1%

1 2

RH51 499_0402_1%

T66

@PAD

route from VGA?

1 2

RH116

30_0402_1%

1 2

RH117

30_0402_1%

PCH_SMBALERT#

CRB

PCH_SML0CLK
PCH_SML0DATA

B

PCH_EDP_HPD

HDA_BIT_CLK
HDA_RST#
HDA_SDIN0

HDA_SDOUT
HDA_SYNC

CPU_DISPA_SDO
CPU_DISPA_SDI_R
CPU_DISPA_BCLK

PCH_RTCRST #
PCH_SRTCRST#

PCH_PWROK
EC_RSMRST#

PCH_DPWROK

PCH_SMBALERT#

PCH_SMBCLK
PCH_SMBDATA

PCH_SML0CLK
PCH_SML0DATA

PCH_SML1CLK
PCH_SML1DATA

UH1E

AW4

GPP_I0/DDPB_HPD0

AY2

GPP_I1/DDPC_HPD1

AV4

GPP_I2/DDPD_HPD2

BA4

GPP_I3/DDPE_HPD3

BD7

GPP_I4/EDP_HPD

SKL-H-PCH_BGA837

REV = 1.3

@

UH1D

BA9

HDA_BCLK

BD8

HDA_RST#

BE7

HDA_SDI0

BC8

HDA_SDI1

BB7

HDA_SDO

BD9

HDA_SYNC

BD1

RSVD_BD1

BE2

RSVD_BE2

AM1

DISPA_SDO

AN2

DISPA_SDI

AM2

DISPA_BCLK

AL42

GPP_D8/I2S0_SCLK

AN42

GPP_D7/I2S0_RXD

AM43

GPP_D6/I2S0_TXD

AJ33

GPP_D5/I2S0_SFRM

AH44

GPP_D20/DMIC_DATA0

AJ35

GPP_D19/DMIC_CLK0

AJ38

GPP_D18/DMIC_DATA1

AJ42

GPP_D17/DMIC_CLK1

BC10

RTCRST#

BB10

SRTCRST#

AW11

PCH_PWROK

BA11

RSMRST#

AV11

DSW_PWROK

BB41

GPP_C2/SMBALERT#

AW44

GPP_C0/SMBCLK

BB43

GPP_C1/SMBDATA

BA40

GPP_C5/SML0ALERT#

AY44

GPP_C3/SML0CLK

BB39

GPP_C4/SML0DATA

AT27

GPP_B23/SML1ALERT#/PCHHOT#

AW42

GPP_C6/SML1CLK

AW45

GPP_C7/SML1DATA

SKL-H-PCH_BGA837

REV = 1.3

@

+3VALW_PCH_PRIM

+3VS

+3VALW_PCH_PRIM

+3VS

SPT-H_PCH

AUDIO

2.2K_0804_8P4R_5%

2.2K_0804_8P4R_5%

PDG_0_71 requirement PH to +3V_PCH
10/14 Dan

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I9/DDPD_CTRLCLK

GPP_I10/DDPD_CTRLDATA

5 OF 12

SPT-H_PCH

SMBUS

RPH9

18
27
36
45

RPH8

18
27
36
45

GPP_F14
GPP_F23

GPP_F22
GPP_G23
GPP_G22
GPP_G21
GPP_G20
GPP_H23

GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_A13/SUSWARN#/SUSPWRDNACK

JTAG

4 OF 12

PCH_SMBCLK
PCH_SMBDATA
PCH_SMBCLK_R
PCH_SMBDATA_R

PCH_SML1CLK
PCH_SML1DATA
EC_SMB_CK2
EC_SMB_DA2

SSSeeecccuuurrriiitttyyy CCClllaaassssssiiifffiiicccaaatttiiiooonnn

IIIssssssuuueeeddd DDDaaattteee

TTT HHHIIISSS SSSHHHEEEEEETTT OOOFFF EEENNNGGGIIINNNEEEEEERRRIIINNNGGG DDDRRRAAAWWWIIINNNGGG IIISSS TTTHHHEEE PPPRRROOOPPPRRRIIIEEETTTAAARRRYYY PPPRRROOOPPPEEERRRTTTYYY OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCC SSS,,, IIINNNCCC... AAANNNDDD CCCOOONNNTTTAAAIIINNNSSS CCCOOONNNFFFIIIDDDEEENNNTTTIIIAAALLL
AAANNNDDD TTTRRRAAADDDEEE SSSEEECCCRRREEETTT IIINNNFFFOOORRRMMMAAATTTIIIOOONNN... TTTHHHIIISSS SSSHHHEEEEEETTT MMMAAAYYY NNNOOOTTT BBBEEE TTTRRRAAANNNSSSFFFEEERRREEEDDD FFFRRROOOMMM TTTHHHEEE CCCUUUSSSTTTOOODDDYYY OOOFFF TTTHHHEEE CCCOOOMMMPPPEEETTTEEENNNTTT DDDIIIVVVIIISSSIIIOOONNN OOOFFF RRR&&&DDD
DDDEEEPPPAAARRRTTTMMMEEENNNTTT EEEXXXCCCEEEPPPTTT AAASSS AAAUUUTTTHHHOOORRRIIIZZZEEEDDD BBBYYY CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... NNNEEEIIITTTHHHEEERRR TTTHHHIIISSS SSSHHHEEEEEETTT NNNOOORRR TTTHHHEEE IIINNNFFFOOORRRMMMAAATTTIIIOOONNN IIITTT CCCOOONNNTTTAAAIIINNNSSS
MMMAAAYYY BBBEEE UUUSSSEEEDDD BBBYYY OOORRR DDDIIISSSCCCLLLOOOSSSEEEDDD TTTOOO AAANNNYYY TTTHHHIIIRRRDDD PPPAAARRR TTTYYY WWWIIITTTHHHOOOUUUTTT PPPRRR IIIOOORRR WWWRRRIIITTTTTTEEENNN CCCOOONNNSSSEEENNNTTT OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCC SSS,,, IIINNNCCC...

C

?

BB3
BD6
BA5
BC4
BE5
BE6

Y44
V44
W39
L43
L44
U35
R35
BD36

GPP_A8/CLKRUN#
GPD11/LANPHYPC
GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_B1

GPP_G17/ADR_COMPLETE

GPP_B0

GPP_B11

SYS_PWROK

WAKE#

GPD6/SLP_A#

SLP_LAN#

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE#
GPD1/ACPRESENT

SLP_SUS#

GPD3/PWRBTN#

SYS_RESET#

GPP_B14/SPKR

PROCPWRGD

ITP_PMODE

JTAGX
JTAG_TMS
JTAG_TDO

JTAG_TDI

JTAG_TCK

<14,15,16,17,40> PCH_SMBCLK_R

<14,15,16,17,40> PCH_SMBDATA_R

<26,32,36,38,41,53> EC_SMB_CK2

<26,32,36,38,41,53> EC_SMB_DA2

222000111666///000222///000111 222000111777///111222///333111

H_SKTOCC# <9>

BB17

PM_CLKRUN#

AW22
AR15

SLP_WLAN#

AV13

DDR_DRAMRST#

BC14

PCH_VRALERT#

BD23
AL27
AR27
N44

GC6_FB_EN_S_R

AN24

SYS_PWROK

AY1
BC13

WAKE#

BC15
AV15

PM_SLP_S0#

BC26

PM_SLP_S3#

AW15

PM_SLP_S4#

BD15

PM_SLP_S5#

BA13
AN15

SUSCLK
PM_BATLOW#

BD13
BB19
BD19

LAN_WAKE#

BD11

AC_PRESENT_R

BB15

PM_SLP_SUS#

BB13

PBTN_OUT#_R

AT13

SYS_RESET#

AW1

PCH_SPKR

BD26

H_CPUPWRGD

AM3

XDP_ITP_PMODE

AT2

CPU_XDP_TCK0

AR3

CPU_XDP_TMS

AR2

CPU_XDP_TDO

AP1

CPU_XDP_TDI

AP2

PCH_JTAG_TCK1

AN3

?

1

1 2

@

RH52 0_0402_5%

(DIMM,G-SENEOR,)

EC_SMB_CK2

EC_SMB_DA2

(IO Brd /AUDIO/EC/VGA/VGA2)

CCCooommmpppaaalll SSSeeecrcrcreeettt DDDaaatttaaa

DeDeDecicicippphhheeererereddd DaDaDatetete

PM_CLKRUN# <40>

@ T32

PAD

GC6_FB_EN_S_R <22>

SYS_PWROK <26,38>

2

0_0402_5%@RH154

@ T70

PAD

PM_SLP_S3# <26,38>
PM_SLP_S4# <26,38,77>

@ T6

PAD

SUSCLK <28,29,31>

@ T34

PAD

PCH_SPKR <36>

H_CPUPWRGD <9>

XDP_ITP_PMODE <6>
CPU_XDP_TCK0 <6,9>
CPU_XDP_TMS <6,9>
CPU_XDP_TDO <6,9>
CPU_XDP_TDI <6,9>
PCH_JTAG_TCK1 <6>

PCH_SMBCLK_R

PCH_SMBDATA_R

D

TBT_PCIE_WAKE_N <68>

@ T12

PAD

SUSPWRDNACK <38>

+3VS

QH1A

2

DMN66D0LDW -7_SOT363-6

5

QH1B
DMN66D0LDW -7_SOT363-6

34

+3VS

QH2A

2

DMN66D0LDW -7_SOT363-6

5

QH2B
DMN66D0LDW -7_SOT363-6

34

DDR_DRAMRST#

61

61

+3VS

PM_CLKRUN#

PCH_VRALERT#

PBTN_OUT#_R

PBTN_OUT#_R

AC_PRESENT_R

SYS_PWROK

SYS_RESET#

PCH_SMBCLK

PCH_SMBDATA

PCH_SML1CLK

PCH_SML1DATA

RH39 10K_0402_5%

RH43 10K_0402_5%

RH128 100K_0402_5%

RH47 0_0402_5%

RH48 0_0402_5%

RH130 10K_0402_5%

CH10
.1U_0402_16V7K

XEMC@

+1.2V_VDDQ

12

RH153
470_0402_5%

1 2

RH161 0_0402_5%

1

@

.1U_0402_16V7K
CH67

2

Compal Electronics, Inc.Compal Electronics, Inc.Compal Electronics, Inc.

TTTiiitttlll eee

PCPCPCH(H(H(333///777)))GGGPIPIPIOOO,,,SSSMMMBBBUUUSSS

SSSiiizezeze DDDooocucucumememennnttt NNNuuumbmbmbeeerrr RRReee vvv

CCCuuussstttooommm

C1PR2 LA-E051PC1PR2 LA-E051PC1PR2 LA-E051P

DDDaaattteee::: SSShhheeeeeettt ooo fff

1 2

@

@

1 2

@

1 2

@

1 2

1 2

@

12

12

CRB 8.2K

+3VALW_PCH_PRIM

DDR_DRAMRST#_R <14,15,16,17>

E

+3VALW_DSW

PBTN_OUT# <38>

AC_PRESENT <38>

222000 111000333MMMooonnndddaaayyy,,, JJJaaannnuuuaaarrryyy 000999,,, 222000111777

111...000

A

+3VS

RPH11

CLKREQ_PCIE#1

18

CLKREQ_PCIE#3

27

CLKREQ_PCIE#5

36

CLKREQ_PCIE#4

1 1

Follow PDG 0.71Table 52-17
10/13 Dan
CHECK NEEDED IF UNUSE?

2 2

1 2

RH71 10M_0402_5%

1 2

32.768KHZ 9PF 20PPM

8.2P_0402_50V8D

1

CH13

2

3 3

45

10K_0804_8P4R_5%

RPH12

18
27
36
45

10K_0804_8P4R_5%

RPH13

18
27
36
45

10K_0804_8P4R_5%

YH1

CLKREQ_PCIE#7
CLKREQ_PCIE#2

PEG_CLKREQ#_S
CLKREQ_PCIE#6

PEG_CLKREQ#

RTCX1

RTCX2

6.8P_0402_50V8B

1

CH14

2

Check if need PH alone

XTAL24_OUT

1 2

RH72 1M_0402_5%

YH2
24MHZ_12PF_7V24000020

3

15P_0402_50V8J

3

GND

CH11

4

GND

1

1

2

XTAL24_IN

15P_0402_50V8J

CH12

B

+1.0VALW_VCCCLK5

PEG master

CR

WIGI G

WLAN

LAN

Thunderbol t
SSD Slot_1
SSD Slot_2
PEG secondary

FOLLOW RVP11

CPU_24M<9>
CPU_24M#<9>

CPU_BCLK<9>
CPU_BCLK#<9>

XTAL24_OUT
XTAL24_IN

PEG_CLKREQ#<41>
CLKREQ_PCIE#1<32>
CLKREQ_PCIE#2<31>
CLKREQ_PCIE#3<31>
CLKREQ_PCIE#4<30>
CLKREQ_PCIE#5<68>
CLKREQ_PCIE#6<28>
CLKREQ_PCIE#7<28>

PEG_CLKREQ#_S<53>

RH67

2.7K_0402_1%

12

C

XCLK_BIASREF

RTCX1
RTCX2

PEG_CLKREQ#
CLKREQ_PCIE#1
CLKREQ_PCIE#2
CLKREQ_PCIE#3
CLKREQ_PCIE#4
CLKREQ_PCIE#5
CLKREQ_PCIE#6
CLKREQ_PCIE#7
PEG_CLKREQ#_S

UH1G

AR17

GPP_A16/CLKOUT_48

G1

CLKOUT_CPUNSSC_P

F1

CLKOUT_CPUNSSC_N

G2

CLKOUT_CPUBCLK_P

H2

CLKOUT_CPUBCLK_N

A5

XTAL24_OUT

A6

XTAL24_IN

E1

XCLK_BIASREF

BC9

RTCX1

BD10

RTCX2

BC24

GPP_B5/SRCCLKREQ0#

AW24

GPP_B6/SRCCLKREQ1#

AT24

GPP_B7/SRCCLKREQ2#

BD25

GPP_B8/SRCCLKREQ3#

BB24

GPP_B9/SRCCLKREQ4#

BE25

GPP_B10/SRCCLKREQ5#

AT33

GPP_H0/SRCCLKREQ6#

AR31

GPP_H1/SRCCLKREQ7#

BD32

GPP_H2/SRCCLKREQ8#

BC32

GPP_H3/SRCCLKREQ9#

BB31

GPP_H4/SRCCLKREQ10#

BC33

GPP_H5/SRCCLKREQ11#

BA33

GPP_H6/SRCCLKREQ12#

AW33

GPP_H7/SRCCLKREQ13#

BB33

GPP_H8/SRCCLKREQ14#

BD33

GPP_H9/SRCCLKREQ15#

R13

CLKOUT_PCIE_N15

R11

CLKOUT_PCIE_P15

P1

CLKOUT_PCIE_N14

R2

CLKOUT_PCIE_P14

W7

CLKOUT_PCIE_N13

Y5

CLKOUT_PCIE_P13

U2

CLKOUT_PCIE_N12

U3

CLKOUT_PCIE_P12

S

KL-H-PCH_BGA837

@

REV = 1.3

SPT-H_PCH

CLKOUT_CPUPCIBCLK_N
CLKOUT_CPUPCIBCLK_P

7 OF 12

D

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5

CLKOUT_PCIE_N6
CLKOUT_PCIE_P6

CLKOUT_PCIE_N7
CLKOUT_PCIE_P7

CLKOUT_PCIE_N8
CLKOUT_PCIE_P8

CLKOUT_PCIE_N9
CLKOUT_PCIE_P9

CLKOUT_PCIE_N10

CLKOUT_PCIE_P10

CLKOUT_PCIE_N11

CLKOUT_PCIE_P11

?

L1
L2
J1
J2

N7
N8

L7
L5

D3
F2

E5
G4

D5
E6

D8
D7

R8
R7

U5
U7

W10
W11

N3
N2

P3
P2

R3
R4

CLK_CPU_ITP#
CLK_CPU_ITP
CPU_PCIBCLK#
CPU_PCIBCLK

CLK_PEG_GPU_N0

CLK_PEG_GPU_P0

CLK_PCIE_N1

CLK_PCIE_P1

CLK_PCIE_N2

CLK_PCIE_P2

CLK_PCIE_N3

CLK_PCIE_P3

CLK_PCIE_N4

CLK_PCIE_P4

CLK_PCIE_N5

CLK_PCIE_P5

CLK_PCIE_N6

CLK_PCIE_P6

CLK_PCIE_N7

CLK_PCIE_P7

PAD

T37

@

PAD

T38

@

CPU_PCIBCLK# <9>
CPU_PCIBCLK <9>

CLK_PEG_GPU_N0 <41>

CLK_PEG_GPU_P0 <41>

CLK_PCIE_N1 <32>

CLK_PCIE_P1 <32>

CLK_PCIE_N2 <31>

CLK_PCIE_P2 <31>

CLK_PCIE_N3 <31>

CLK_PCIE_P3 <31>

CLK_PCIE_N4 <30>

CLK_PCIE_P4 <30>

CLK_PCIE_N5 <68>

CLK_PCIE_P5 <68>

CLK_PCIE_N6 <28>

CLK_PCIE_P6 <28>

CLK_PCIE_N7 <28>

CLK_PCIE_P7 <28>

CLK_PEG_GPU_S_N8 <53>

CLK_PEG_GPU_S_P8 <53>

E

PEG master

CR

WIGI G

WLAN

LAN

Thunderbol t

SSD Slot_1

SSD Slot_2

PEG secondary

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

A

B

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

C

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(4/7)CLK

PCH(4/7)CLK

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

D

Date: Sheet o f

PCH(4/7)CLK

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1.0

1.0

21 103Monday, January 09, 2017

21 103Monday, January 09, 2017

E

21 103Monday, January 09, 2017

1.0

A

B

C

D

E

Functional Strap Definitions

GSPI1_MOSI / GPP_B22
int. PD
Boot BIOS Destination
0 = SPI (Default)
1 = LPC

1 1

GSPI0_MOSI / GPP_B18
int.

PD
0 = Disable “ No Reboot ” mode. ( Def ault)
1 = Enable “ No Reboot ” mode ( PCH will di sable t he T CO
Timer system reboot feature).

+3VS

UART_2_CRXD_DTXD

RH73 49.9K_0402_1%
RH74 49.9K_0402_1%
RH75 49.9K_0402_1%
RH76 49.9K_0402_1%

2 2

+3VALW _PCH_PRIM

12

UART_2_CTXD_DRXD

12

UART_2_CCTS_DRTS

12

@

UART_2_CRTS_DCTS

12

@

+3VS

1 2

RH144 1K_0402_5%

1 2

RH145 1K_0402_5%

1 2

RH146 2.2K_0402_5%

1 2

RH147 2.2K_0402_5%

+3VS

1 2

RH162 10K_0402_5%

I2C_0_SCL

I2C_0_SDA

I2C_1_SCL

I2C_1_SDA

DGPU_PW R_EN

+3VS

PCH internal PU by BIOS set t i ng

EC_SCI#_B20

8 move to B11

B1
confirmed

del TS_EN

DGPU_PW R_LEVEL<38,41,53>

DGPU_HOLD_RST#_S<53>
DGPU_HOLD_RST#<41>

DGPU_PW R_EN<38,41,45,53,57>

UART_2_CTXD_DRXD<31>

UART_2_CRXD_DTXD<31>

@

RH7 10K_0402_5%

RH8 0_0402_5%

1 2

RH143 0_0402_5%

12

1 2

@

remove EC_LID_OUT#

confirm with SW

GPU_EVENT_S_R#
GC6_FB_EN_R
GPU_EVENT_R#

DGPU_PW R_LEVEL_R

@

DGPU_HOLD_RST#_S
DGPU_HOLD_RST#
DGPU_PW R_EN

UART_2_CCTS_DRTS
UART_2_CRTS_DCTS
UART_2_CTXD_DRXD
UART_2_CRXD_DTXD

EC_SCI#_B20

I2C_1_SCL
I2C_1_SDA
I2C_0_SCL
I2C_0_SDA

EC_SCI#

EC_SCI# <38>

UH1K

AT29

GPP_B22/GSPI1_MOSI

AR29

GPP_B21/GSPI1_MISO

AV29

GPP_B20/GSPI1_CLK

BC27

GPP_B19/GSPI1_CS#

BD28

GPP_B18/GSPI0_MOSI

BD27

GPP_B17/GSPI0_MISO

AW27

GPP_B16/GSPI0_CLK

AR24

GPP_B15/GSPI0_CS#

AV44

GPP_C9/UART0_TXD

BA41

GPP_C8/UART0_RXD

AU44

GPP_C11/UART0_CTS#

AV43

GPP_C10/UART0_RTS#

AU41

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AT44

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AT43

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU43

GPP_C12/UART1_RXD/ISH_UART1_RXD

AN43

GPP_C23/UART2_CTS#

AN44

GPP_C22/UART2_RTS#

AR39

GPP_C21/UART2_TXD

AR45

GPP_C20/UART2_RXD

AR41

GPP_C19/I2C1_SCL

AR44

GPP_C18/I2C1_SDA

AR38

GPP_C17/I2C0_SCL

AT42

GPP_C16/I2C0_SDA

AM44

GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA

AJ44

GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL

SK

L-H-PCH_BGA837

REV = 1.3

@

SPT-H_PCH

GPP_D9
GPP_D10
GPP_D11
GPP_D12

GPP_D16/ISH_UART0_CTS#

11 OF 12

GPP_D15/ISH_UART0_RTS#

GPP_H20/ISH_I2C0_SCL
GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL
GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
GPP_A20/ISH_GP2
GPP_A19/ISH_GP1
GPP_A18/ISH_GP0
GPP_A17/ISH_GP7

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA

AL44
AL36

PROJECT_ID0

AL35

PROJECT_ID1

AJ39
AJ43

AL43
AK44
AK45

BC38
BB38

BD38
BE39

BC22
BD18
BE21
BD22
BD21
BB22
BC19

?

T44

@

PAD

DRAM_OC <77>

T46

@

PAD

G_INT#

1 2

RH77 10K_0402_5%

RH151
100K_0402_5%

+3VS

@

G_INT# <40>

12

@

BIOS not check in EVT 4/22

PROJECT_ID0

3 3

GPU_EVENT_R# GPU_EVENT#

GPU_EVENT_S_R# GPU_EVENT#_S

GC6_FB_EN_S_R<20>

1 2

RH78 0_0402_5%

1 2

RH79 0_0402_5%

1 2

RH156 0_0402_5%

1 2

RH155 0_0402_5%

GPU_GC6_FB_ENGC6_FB_EN_R

GPU_GC6_FB_EN_S

GPU_EVENT# <41>

GPU_GC6_FB_EN <41>

GPU_EVENT#_S <53>

GPU_GC6_FB_EN_S <53>

TO DGPU

PROJECT_ID1

@

1 2

RH80 10K_0402_5%

1 2

RH81 10K_0402_5%

1 2

@

RH82 10K_0402_5%

1 2

RH83 10K_0402_5%

Project ID

*

C1PR2
Reserved
Reserved
Reserved

4 4

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/02/01 2017/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

+3VALW _PCH_PRIM

Project_ID0Project_ID1

GPP_D11GPP_D12
0 0
0

1

1
0

1 1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PCH(5/7)UART,I2C,GPIO

PCH(5/7)UART,I2C,GPIO

PCH(5/7)UART,I2C,GPIO

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

22 103Monday, January 09, 2017

22 103Monday, January 09, 2017

22 103Monday, January 09, 2017

E

1.0

1.0

1.0

A

@

@

22U_0603_6.3V6M

+1.0VALW_PRIM+1.0VALW

+1.0VALW_DCPDSW

Near PIN
BA29

1

CH15
1U_0402_6.3V6K

2

+1.0VALW_VCCCLK

1

CH28

2

+1.0VALW_VCCCLK5

22U_0603_6.3V6M

CH29

1

2

Near PIN
K2,K3

1

CH27
1U_0402_6.3V6K

2

@

RH86 0_0805_5%

1 2

@

1 1

RH137 for Deep SX.

+1.0VALW

2 2

1 2

RH137 0_0402_5%

1 2

RH138 0_0603_5%

LH3

FBMA-L11-160808-800LMT_0603

1 2

modify follow PDG 05/18

+1.0VALW_AUSB_AZPLL

@

CH47

22U_0603_6.3V6M

Near PIN
U21,U23,U25,U26,V26

CH17

22U_0603_6.3V6M

+1.0VALW_AUSB_AZPLL

CH23

22U_0603_6.3V6M

+1.0VALW_PRIMAL22

@

+1.0VALW_PRIMAD15

@

+1.0VALW_MPHY

1 2

RH113 0_0603_5%

NO USE MPHYGT ON H
CHANGE TO +1.0VALW_MPHY

1 2

3 3

4 4

LH1

FBMA-L11-160808-800LMT_0603

1 2

LH2

FBMA-L11-160808-800LMT_0603

1 2

RH140 0_0402_5%

1 2

RH141 0_0402_5%

1

1

2

2

1

1

2

2

1

1

2

2

1U_0402_6.3V6K

CH48

+1.0VALW_AMPHYPLL

22U_0603_6.3V6M

CH18

Near PIN
AJ5,AL5

CH24
22U_0603_6.3V6M

modify follow PDG 05/18

1U_0402_6.3V6K

1U_0402_6.3V6K

CH37

CH38

1

1

2

2

Near PIN V28
Near PIN AC17

Near PIN
A42,A43,B43

1

CH19
1U_0402_6.3V6K

2

@

B

+1.0VALW_DCPDSW

+1.0VALW_VCCCLK

+1.0VALW_VCCCLK5

+1.0VALW_MPHY

+1.0VALW_AMPHYPLL

+1.0VALW_MPHY

+3VALW_HDA
+3VALW_DSW

CH68

.1U_0402_16V7K

+1.0VALW_PRIM

MAX 1.307A

1

2

Near PIN W15
Add 05/18

+3VALW_PCH_PRIM

1

@

2

+3VALW_PCH_PRIM

22U_0603_6.3V6M

1

@

2

2.899A

0.0454A

0.021A

0.050A

0.024A

0.137A

0.006A

0.110A

0.030A

0.533A

0.012A

0.033A

0.075A

1

CH54
1U_0402_6.3V6K

2

1U_0402_6.3V6K

CH39

22U_0603_6.3V6M

CH41

1

@

2

PCH_EDS Table10-4
1

2/30 J

AA23

VCCPRIM_1P0

AA26

VCCPRIM_1P0

AA28

VCCPRIM_1P0

AC23

VCCPRIM_1P0

AC26

VCCPRIM_1P0

AC28

VCCPRIM_1P0

AE23

VCCPRIM_1P0

AE26

VCCPRIM_1P0

Y23

VCCPRIM_1P0

Y25

VCCPRIM_1P0

BA29

DCPDSW_1P0

N17

VCCCLK1

R19

VCCCLK3

U20

VCCCLK4

V17

VCCCLK2

R17

VCCCLK2

K2

VCCCLK5

K3

VCCCLK5

U21

VCCMPHY_1P0

U23

VCCMPHY_1P0

U25

VCCMPHY_1P0

U26

VCCMPHY_1P0

V26

VCCMPHY_1P0

A43

VCCMPHYPLL_1P0

B43

VCCMPHYPLL_1P0

C44

VCCPCIE3PLL_1P0

C45

VCCPCIE3PLL_1P0

V28

VCCAPLLEBB_1P0

AC17

VCCPRIM_1P0

AJ5

VCCUSB2PLL_1P0

AL5

VCCUSB2PLL_1P0

AN19

VCCHDAPLL_1P0

BA15

VCCHDA

W15

VCCDSW_3P3

+1.0VALW_PRIM

@

+1.0VALW_PRIM

CH42

@

UH1H

SKL-H-PCH_BGA837

REV = 1.3

@

1U_0402_6.3V6K

1

CH40

2

22U_0603_6.3V6M

22U_0603_6.3V6M

CH44

CH43

1

1

@

2

2

C

SPT-H_PCH

CORE

MPHY

USB

VCCGPIO

8 OF 12

VCCPRIM_1P0
VCCDSW_3P3

VCCPGPPBCH
VCCPGPPBCH

VCCPGPPEF
VCCPGPPEF

VCCPRIM_3P3

VCCPRIM_1P0

VCCRTCPRIM_3P3

VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0

VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3

Power Rail Volt age

+CHG RTC

BAT5 4C(VF)

+3VL _RT C

3.38 3V(MAX)

240 mV

3.14 3V

Result : Pass

VCCPGPPA

VCCPGPPG

VCCATS
VCCRTC

DCPRTC

VCCSPI
VCCSPI

VCCSPI
VCCPGPPD
VCCPGPPD
VCCPGPPD
VCCPGPPD

D

+3VALW

+3VALW_PCH_PRIM +3VALW_SPI

AL22

0.0908A

BA24

0.195A

BA31

0.082A

BC42

0.2726A

BD40
AJ41

0.1410A

AL41
AD41

0.1318A

AN5

0.2875A

AD15

0.0061A

AD13

0.007A

BA20

0.0002A

BA22
BA26

AJ20
AJ21
AJ23
AJ25

BE41

0.029A

BE43
BE42
BC44

0.078A

BA45
BC45
BB45

BD3

0.117A

BE3
BE4

?

+1.0VALW_PRIMAL22
+3VALW_DSW

+3VALW_PCH_PRIM

+1.0VALW_PRIMAD15
+3VS_VCCATS
+3VALW_PCH_PRIM

+RTCVCC

1 2

CH26 .1U_0402_16V7K

+1.0VALW_PRIM

+3VALW_SPI

+3VALW_PCH_PRIM

+3VALW_PCH_PRIM

+RTCBATT

Near PIN BA26

JRTC1

1

3

1

NC1

2

4

2

NC2

ACES_50273-0020N-001

SP02000SJ00

CONN@

+3VALW_PCH_PRIM

RH87 0_0402_5%

.1U_0402_16V7K

1 2

RH135 0_0603_5%

1 2

RH89 0_0805_5%

1 2

RH136 0_0402_5%

1 2

RH27 0_0402_5%

1 2

CH20 1U_0402_6.3V6K

@

1 2

CH21 1U_0402_6.3V6K

@

1 2

CH22 .1U_0402_16V7K

1 2

CH25 1U_0402_6.3V6K

1 2

CH30 .1U_0402_16V7K

1 2

CH31 .1U_0402_16V7K

1 2

CH32 .1U_0402_16V7K

1 2

CH35 .1U_0402_16V7K

1 2

CH36 1U_0402_6.3V6K

1 2

@

1

CH46

2

+3VALW_DSW

@

+3VALW_PCH_PRIM

@

+3VALW_HDA

@

@

Near PIN BD3,BE3,BE4

Near PIN BA20

Near PIN AN5

No requirment
Near PIN BC44

Near PIN BC42,BD40

Near PIN AJ41 , AL41

Near PIN AD41

Near PIN BA20

+3VS_VCCATS+3VS

1 2

CH16 1U_0402_6.3V6K

Near PIN

@

AD13

RTC Battery

Change to non-charge circuit
DVT 7/11

+RTCVCC +RTCBATT

1

2

CH45

1U_0402_6.3V6K

DH2

1

CHN202UPT_SC70-3

PN : SC600000B00

E

3

RH163 1K_0402_5%

W=20mils

2

1 2

+CHGRTC

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(6/7)POWER

PCH(6/7)POWER

PCH(6/7)POWER

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

E

23 103Monday, January 09, 2017

23 103Monday, January 09, 2017

23 103Monday, January 09, 2017

1.0

1.0

1.0

A

1 1

B

C

D

E

UH1I

SPT-H_PCH

AC18

VSS

AN4

VSS

AN10

VSS

BE14

VSS

BE18

VSS

BE23

VSS

BE28

VSS

BE32

VSS

BE37

VSS

BE40

VSS

BE9

VSS

C10

VSS

C2

VSS

C28

VSS

C37

VSS

J7

VSS

K10

VSS

M35
M42

AA17
AA18
AA20
AA21
AA25
AA29

AA42
AB10

K27
K33
K36

K4
K42
K43

L12
L13
L15

L4

L41

L8

N10
N15
N19
N22
N24
N35
N36

N4
N41

N5
P17
P19
P22
P45
R10
R14
R22
R29
R33
R38

R5

T1

T2

T4

Y18
Y20
Y21
Y26
Y28

Y29
A18
A25
A32
A37

AA4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

9 OF 12

S

KL-H-PCH_BGA837

@

UH1J

BD2

VSS

BD45

2 2

3 3

BD44

BE44

D45

BB1
BC1

A42
B45
B44

A4
A3
B2
A2
B1

A44

C1
D1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

RSVD
RSVD

SKL-H-PCH_BGA837

SPT-H_PCH

AR22

RSVD

W13

RSVD

U13

RSVD

P31

RSVD

N31

RSVD

P27

RSVD

R27

RSVD

N29

RSVD

P29

RSVD

AN29

RSVD

R24

RSVD

P24

RSVD

XDP_PREQ#

AT3

PREQ#

PRDY#

CPU_TRST#

PCH_TRIGOUT

PCH_TRIGIN

10 OF 12

REV = 1.3

@

AT4
AY5
AL2
AK1

?

XDP_PRDY#
CPU_XDP_TRST#
PROC_TRIGIN
PROC_TRIGOUT_R

RH114 30_0402_1%

XDP_PREQ# <6,9>
XDP_PRDY# <6,9>
CPU_XDP_TRST# <6,9>

12

PROC_TRIGIN_R <13>

PROC_TRIGOUT_R <13>

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

REV = 1.3

AR5
AR7
U15
AL4
AE29
AE4
AE42
AF18
AF20
AF21
AF23
AF25
AF26
AF28
AF29
AG11
AG13
AG31
AG32
AG33
AG38
AG4
AH1
AH17
AH18
AH20
AH21
AH23
AH25
AH26
AH28
AH29
AH45
AJ10
AJ14
AJ15
AJ17
AJ18
AJ26
AJ28
AJ29
AJ31
AJ32
AJ36
AK4
AK42
AU7
AV17
AV24
AV27
AV31
AV33
AV6
AW13
AW19
AW29
AW37
AW9
AY38
AY45
B25
B3
B37
B40
B6
BA1
BB11
BB16
BB21
BB25
BB30
BB34
BC2
BD43

?

W14
W31
W32
W33
W38

C42
D10
D12
D15
D16
D17
D19
D21
D24
D25
D27
D29
D30
D31
D33
D35
D36
E13
E15
E31
E33
F44

F8

G42

G9
H17
H19
H22
H24
H27
H29

H3
H35

J10
J11

J3

J39

J5
T42
U10
U11
U14
U17
U18
U28
U29
U31
U32
U33
U38

U4

U8
V18
V20
V21
V23
V25
V29

V3
V45

W4
W8

Y17

SPT-H_PCH

UH1L

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

S

KL-H-PCH_BGA837

@

12 OF 12

REV = 1.3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB11
AB7
AB14
AB31
AB32
AB38
AB4
AB5
AC1
AC20
AC21
AC25
AC29
AC45
AB8
AD11
AD14
AB15
AD32
AD33
AD36
AD4
AD8
AE18
AE20
AE21
AE25
AE28
AL10
AL11
AL13
AL17
AL19
AL24
AL29
AL32
AL33
AL38
AM15
AM17
AM19
AM22
AM24
AM27
AM29
AM45
AN11
AN22
AN27
AN31
AN39
AN7
AN8
AP11
AP4
AR33
AR34
AR42
AR9
AT10
AT15
AT36
AT9
AU1
AU35
AU36
AU39
AU45
C4

?

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

A

B

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

C

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(7/7)GND

PCH(7/7)GND

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

D

Date: Sheet o f

PCH(7/7)GND

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1.0

1.0

24 103Monday, January 09, 2017

24 103Monday, January 09, 2017

E

24 103Monday, January 09, 2017

1.0

A

B

C

D

E

1 1

1 2

SUSP#<26,28,32,38,68,75,77,79,80>

10mil

2 2

3 3

@

R342 0_0402_5%

R344 10K_0402_5%

1 2

+5VS and +3VS switch

5VS_GATE

3VS_GATE

1

C375
.1U_0402_16V7K

2

+3VALW +5VALW

1U_0402_6.3V6K

1

C825

2

+3VALW

1

2

+5VALW

20mohm/6A per channel

1U_0402_6.3V6K

C824

U41

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

AOZ1331_SON14_2X3

SHORT DEFAULT

14

VOUT1

13

VOUT1

12

1 2

CT1

11

GND

1 2

10

CT2

9

VOUT2

8

VOUT2

15

GPAD

SHORT DEFAULT

+3VALW

C379

C378

10U_0603_6.3V6M

1

2

5VS

C368
1000P_0402_50V7K
C371
1000P_0402_50V7K

3VS

10U_0603_6.3V6M

C380

1

2

1 2

JUMP_43X118

@

1 2

JUMP_43X118

@

+5VALW

10U_0603_6.3V6M

1

2

+1.0VALW TO +1.0V_VCCST

+5VS

J15

J16

+3VS

C369

.1U_0402_16V7K

C370

10U_0603_6.3V6M

1

1

2

2

SYSON<26,38,77,78>

C376

.1U_0402_16V7K

C377

10U_0603_6.3V6M

1

1

2

2

+1.0VALW

+5VALW

1

12

C374@

C373

2

1U_0402_6.3V6K

.1U_0402_16V7K

U40

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm /6A
TR=12.5us@Vin=1.05V

VOUT

GND

+1.0V_VCCST_OUT

6

5

1

C372
.1U_0402_16V7K

2

R343

0_0603_5%

1 2

@

+1.0V_VCCST

+1.0VALW TO +1.0VS_VCCSTG

C381

10U_0603_6.3V6M

1

2

1

2

SUSP#

+1.0VALW

+5VALW

.1U_0402_16V7K

@

1U_0402_6.3V6K

12

C384

C383

U42

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm /6A
TR=12.5us@Vin=1.05V

VOUT

GND

+1.0VS_VCCSTG_OUT

6

5

12

C382
.1U_0402_16V7K

+1.0VS_VCCSTG

R347

0_0603_5%

12

@

@

+1.0VS_VCCSTG

1

C385
.1U_0402_16V7K

2

del Load SW for +3VALW_PCH

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

A

B

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

C

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet o f

Date: Sheet o f

D

Date: Sheet

Compal Electronics, Inc.

DC/DC Interface

DC/DC Interface

DC/DC Interface
C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

E

1.0

1.0

1.0

of

25 103Monday, January 09, 2017

25 103Monday, January 09, 2017

25 103Monday, January 09, 2017

A

B

C

D

E

1 2

61

SDATA

ALERT#

SCLK

+0.6VS_VTT+5VALW

+5VALW+1.2V_VDDQ

8
7
6
5

12

R12
470_0603_5%@

+0.6VS_VTT_R

34

Q26B

@

DMN66D0LDW-7_SOT363-6

5

SUSP

R14
100K_0402_5%

@

1 2

SYSON#

34

5

Q27B

@

DMN66D0LDW-7_SOT363-6

EC_SMB_CK2
EC_SMB_DA2

TH_ALERT#

1 2

R798 10K_0402_5%

SYSON <25,38,77,78>

EC_SMB_CK2 <20,32,36,38,41,53>
EC_SMB_DA2 <20,32,36,38,41,53>

+3VS

For Power Of f Sequence

R11

100K_0402_5% @

SUSP

SUSP#<25,28,32,38,68,75,77,79,80>

R16

10K_0402_5%

@

SYSON# SYSON

DMN66D0LDW-7_SOT363-6

+3VS

.1U_0402_16V7K

C823

1

2

TH_THERM#

R1

100K_0402_5%

Q20B

5

R2

100K_0402_5%

Q23B

5

+3VALW

12

34

+3VALW

12

34

PM_SLP_S3

PM_SLP_S4

Q20A
DMN66D0LDW-7_SOT363-6

61

2
2

61

Q21A
DMN66D0LDW-7_SOT363-6

5

34

Q21B
DMN66D0LDW-7_SOT363-6

Q22A

@

DMN66D0LDW-7_SOT363-6

61

2
5

34

Q22B

@

DMN66D0LDW-7_SOT363-6

Reserved 05/18

Q23A
DMN66D0LDW-7_SOT363-6

61

2

EC_VCCST_PG_R <9,38>

For tCPU28 200us(max)

VR_ON <38,80,81>

For tPLT17 200us(max)

SUSP#

For tPLT18 200us(max)

SYS_PWROK <20,38>

PCH_PW ROK <20,38>

SYSON

For tPLT15 200us(max)

External Thermal Sensor

+3VS

1 2

R801 10K_0402_5%

1 1

DMN66D0LDW-7_SOT363-6

PM_SLP_S3#<20,38>

2 2

DMN66D0LDW-7_SOT363-6

3 3

PM_SLP_S4#<20,38,77>

1 2

61

2

Q26A

@

12

DMN66D0LDW-7_SOT363-6

R13

470_0603_5%

@

2

Q27A

@

U52

1

VDD

2

D+

3

D­THERM#4GND

ADM1032ARMZ-2REEL_MSOP8

PN : SA00003PU00

4 4

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/02/01 2017/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

DC Interface

DC Interface

DC Interface

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1.0

1.0

1.0

26 103Monday, January 09, 2017

26 103Monday, January 09, 2017

26 103Monday, January 09, 2017

E

A

+3VS

1 1

2 2

4.7K_0402_5%

4.7K_0402_5%

12

12

R30

R31

4.7K_0402_5%

4.7K_0402_5%

R36

R37

@

1 2

@

1 2

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

12

12

1 2

R34

R33

@

@

4.7K_0402_5%

4.7K_0402_5%

R39

R40

1 2

4.7K_0402_5%

12

R32

R41

@

@

1 2

A_DE
B_DE

A_EQ1
A_EQ2

B_EQ1
B_EQ2

4.7K_0402_5%

4.7K_0402_5%

12

R38

R42

1 2

B

C

D

E

HDD Re-Driver

U7

12

SATA_PTX_DRX_P2<19>
SATA_PTX_DRX_N2<19>

SATA_PRX_DTX_P2<19>

SATA_PRX_DTX_N2<19>

C38 0.01U_0402_16V7K

12

C30 0.01U_0402_16V7K

12

C31 0.01U_0402_16V7K

12

C36 0.01U_0402_16V7K

+3VS

SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2

SATA_PRX_C_DTX_P2
SATA_PRX_C_DTX_N2

A_EQ1
A_EQ2

B_EQ1
B_EQ2

1 2

R27 4.7K_0402_5%@
R29 4.99K_0402_1%

12

1

A_INP

2

A_INN

5

B_OUTP

4

B_OUTN

17

A_EQ1

18

A_EQ2

19

B_EQ1

13

B_EQ2

7

EN

6

REXT

PS8527CTQFN20GTR2A2_TQFN20_4X4

A_OUTP
A_OUTN

B_INN

VDD
VDD

B_INP

A_DE
B_DE

DEW

EPAD

GND

+3VS

10
20

15
14

11
12

9
8
16
21

3

RDSATA_PTX_DRX_P2
RDSATA_PTX_DRX_N2

RDSATA_PRX_DTX_P2

RDSATA_PRX_DTX_N2
A_DE
B_DE

+3VS

0.1U_0402_16V7K

0.01U_0402_16V7K

1

1

2

C33

C32

2

HDD cable Conn

JHDD1

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

G1

22

G2

23

G3

24

G4

STARC_115B20-100020-G2-R

SP010022I00

change for DVT

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

HDD & G-Sensor

HDD & G-Sensor

HDD & G-Sensor

E

1.0

1.0

1.0

27 103Monday, January 09, 2017

27 103Monday, January 09, 2017

27 103Monday, January 09, 2017

1 2

@

1 2

R357 0_0402_5%@

RDSATA_PTX_C_DRX_P2
RDSATA_PTX_C_DRX_N2

RDSATA_PRX_C_DTX_N2
RDSATA_PRX_C_DTX_P2

+3VS

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

RDSATA_PTX_DRX_P2
RDSATA_PTX_DRX_N2

RDSATA_PRX_DTX_N2

3 3

+5VS_HDD

RDSATA_PRX_DTX_P2

1 2

C34 0.01U_0402_16V7K

1 2

C35 0.01U_0402_16V7K

1 2

C39 0.01U_0402_16V7K

1 2

C37 0.01U_0402_16V7K

100mils

C42

1000P_0402_50V7K

C41

.1U_0402_16V7K

C40

10U_0603_6.3V6M

1

2

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

1

1

@

2

2

G_INT2<40>

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

C

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+5VS +5VS_HDD

R412 0_0805_5%

D

5

4

3

2

1

SSD

NGFF Slot_1 Key M

JSSD1

1

GND

3

GND

5

PERn3

7

PERp3

9

GND

11

PETn3

13

PETp3

15

GND

17

PERn2

19

PERp2

21

GND

23

PETn2

25

PETp2

27

GND

29

PERn1

31

PERp1

33

GND

35

PETn1

37

PETp1

39

GND

41

PERn0/SA TA-B+

43

PERp0/SA TA-B-

45

GND

47

PETn0/SATA-A -

49

PETp0/SATA-A +

51

GND

53

REFCLKN

55

REFCLKP

57

GND

67

NC
PEDET(NC-PCIE/GND-SATA)693P3VAUX

71 72

GND

73

GND

75

GND

LOTES_APCI0096-P00 2A

CONN@

SP07001CS00

Note: Replace Footprint, PN, Value on original symbol

CLK_PCIE_N6

CLK_PCIE_P6

+3VS_NGFF1

12

PCIE_PRX_DTX_N12
PCIE_PRX_DTX_P12

PCIE_PTX_C_DRX_N12
PCIE_PTX_C_DRX_P12

PCIE_PRX_DTX_N11
PCIE_PRX_DTX_P11

PCIE_PTX_C_DRX_N11
PCIE_PTX_C_DRX_P11

PCIE_PRX_DTX_N10
PCIE_PRX_DTX_P10

PCIE_PTX_C_DRX_N10
PCIE_PTX_C_DRX_P10

PCIE_PRX_R_DTX_P9
PCIE_PRX_R_DTX_N9

PCIE_PTX_C_DRX_N9
PCIE_PTX_C_DRX_P9

PEDET0

PCIE_PRX_DTX_N12<19>
PCIE_PRX_DTX_P12<1 9>

D D

C C

PCIE_PTX_DRX_N12<19>
PCIE_PTX_DRX_P12<19 >

PCIE_PRX_DTX_N11<19>
PCIE_PRX_DTX_P11<1 9>

PCIE_PTX_DRX_N11<19>
PCIE_PTX_DRX_P11<19 >

PCIE_PRX_DTX_N10<19>
PCIE_PRX_DTX_P10<1 9>

PCIE_PTX_DRX_N10<19>
PCIE_PTX_DRX_P10<19 >

PCIE_PRX_DTX_P9<19>
PCIE_PRX_DTX_N9<19>

PCIE_PTX_DRX_N9<19>
PCIE_PTX_DRX_P9<19>

SATA_GP0<19>

1 2

CN1 0.22U_0402_16V7K

1 2

CN2 0.22U_0402_16V7K

1 2

CN3 0.22U_0402_16V7K

1 2

CN4 0.22U_0402_16V7K

1 2

CN5 0.22U_0402_16V7K

1 2

CN6 0.22U_0402_16V7K

1 2

RN1 0_0402_5%@

1 2

RN2 0_0402_5%@

1 2

CN7 0.22U_0402_16V7K

1 2

CN8 0.22U_0402_16V7K

CLK_PCIE_N6<21>
CLK_PCIE_P6<2 1>

RN4

10K_040 2_5%

1 2

@

RN5 0_0402_ 5%

34

D

G

5

S

Q35A

@

DMN66D0LDW -7_SOT36 3-6

3P3VAUX
3P3VAUX

DAS/DSS#

3P3VAUX
3P3VAUX
3P3VAUX
3P3VAUX

DEVSLP

PERST#
CLKREQ#
PEWake#

SUSCLK(32 kHz)

3P3VAUX
3P3VAUX

GND1
GND2

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC

NC
NC

(left side)

+3VS_NGFF1

2
4
6
8

PCIE_LED1#

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58

SUSCLK_S SD1

68
70

74
76

77

DEVSLP0 <1 8>

PLT_RST_BUF# <19,29 ,30,31,32,41,53,6 8>

CLKREQ_P CIE#6 <21>

1 2

@

RN3 0_0402_5%

SUSCLK <20,29,31>

SSD

NGFF Slot_2 Key M

JSSD2

1

GND

3

GND

5

PERn3

7

PERp3

9

GND

11

PETn3

13

PETp3

15

GND

17

PERn2

19

PERp2

21

GND

23

PETn2

25

PETp2

27

GND

29

PERn1

31

PERp1

33

GND

35

PETn1

37

PETp1

39

GND

41

PERn0/SA TA-B+

43

PERp0/SA TA-B-

45

GND

47

PETn0/SATA-A -

49

PETp0/SATA-A +

51

GND

53

REFCLKN

55

REFCLKP

57

GND

67

NC
PEDET(NC-PCIE/GND-SATA)693P3VAUX

71 72

GND

73

GND

75

GND

LOTES_APCI0096-P00 2A

CONN@

SP07001CS00

Note: Replace Footprint, PN, Value on original symbol

RN9

PCIE_PRX_DTX_N20
PCIE_PRX_DTX_P20

PCIE_PTX_C_DRX_N20
PCIE_PTX_C_DRX_P20

PCIE_PRX_DTX_N19
PCIE_PRX_DTX_P19

PCIE_PTX_C_DRX_N19
PCIE_PTX_C_DRX_P19

PCIE_PRX_DTX_N18
PCIE_PRX_DTX_P18

PCIE_PTX_C_DRX_N18
PCIE_PTX_C_DRX_P18

PCIE_PRX_R_DTX_P17
PCIE_PRX_R_DTX_N17

PCIE_PTX_C_DRX_N17
PCIE_PTX_C_DRX_P17

CLK_PCIE_N7

CLK_PCIE_P7

+3VS_NGFF2

12

PEDET1

PCIE_PRX_DTX_N20<19>
PCIE_PRX_DTX_P20<19 >

PCIE_PTX_DRX_N20<19>
PCIE_PTX_DRX_P20<19 >

PCIE_PRX_DTX_N19<19>
PCIE_PRX_DTX_P19<19 >

PCIE_PTX_DRX_N19<19>

B B

A A

PCIE_PTX_DRX_P19<19 >

PCIE_PRX_DTX_N18<19>
PCIE_PRX_DTX_P18<19 >

PCIE_PTX_DRX_N18<19>
PCIE_PTX_DRX_P18<19 >

PCIE_PRX_DTX_P17<19 >
PCIE_PRX_DTX_N17<19>

PCIE_PTX_DRX_N17<19>
PCIE_PTX_DRX_P17<19 >

SATA_GP1<19>

1 2

CN9 0.22U_0402_16V7K

1 2

CN10 0.22U_0 402_16V 7K

1 2

CN11 0.22U_0 402_16V 7K

1 2

CN12 0.22U_0 402_16V 7K

1 2

CN13 0.22U_0 402_16V 7K

1 2

CN14 0.22U_0 402_16V 7K

1 2

RN7 0_0402_5%@

1 2

RN6 0_0402_5%@

1 2

CN15 0.22U_0 402_16V 7K

1 2

CN16 0.22U_0 402_16V 7K

CLK_PCIE_N7<21>
CLK_PCIE_P7<21>

10K_040 2_5%

1 2

@

RN10 0_0402 _5%

61

D

G

2

S

Q35B

@

DMN66D0LDW -7_SOT36 3-6

3P3VAUX
3P3VAUX

DAS/DSS#

3P3VAUX
3P3VAUX
3P3VAUX
3P3VAUX

DEVSLP

PERST#

CLKREQ#

PEWake#

SUSCLK(32 kHz)

3P3VAUX
3P3VAUX

GND1
GND2

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC

NC
NC

(left side)

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58

68
70

74
76

77

+3VS_NGFF2

PCIE_LED2#

PLT_RST_BUF#

SUSCLK_S SD2

DEVSLP1 <1 8>

CLKREQ_P CIE#7 <21>

1 2

@

RN8 0_0402_5 %

SUSCLK

+3VS_NGFF PWR

RN19

10K_040 2_5%

+3VS_NGFF1

0.047U_0402_16V4Z

1

2

PEDET

+3VS_NGFF2

0.047U_0402_16V4Z

1

2

PEDET

R351 0_0402_ 5%

C391

1

2

+3VS+3VS

33P_0402_50V8J

1

2

+3VALW

10U_0603_6.3V6M

12

RN18
10K_040 2_5%

PCIE_LED1#

PCIE_LED2#

1

CN19

2

@

C392

10U_0603_6.3V6M

1

2

33P_0402_50V8J

CN20

SUSP#<25,26,32,38 ,68,75,77,79,80>

12

0.047U_0402_16V4Z

1

CN17

CN18

2

Module Type
0
1

0.047U_0402_16V4Z

1

CN24

2

SATA

PCIE

33P_0402_50V8J

33P_0402_50V8J

1

1

CN26

CN25

CN27

2

2

Module Type
0
1

SATA

PCIE

12

C388

0.01U_0402_16V7K

1
2

22U_0603_6.3V6M

1

CN21

2

22U_0603_6.3V6M

1

CN28

2

+3V_NGFF_GATE

12

+5VALW

+3VS

5

VCC

IN1
IN2

GND

MC74VHC1G 08DFT2G_SC70-5

3

22U_0603_6.3V6M

1

CN22

2

22U_0603_6.3V6M

1

CN29

2

+3VALW

+3VALW

1U_0402_6.3V6K

1

2

U71

4

OUT

1

+

CN23
220U_B2_4VM_R35M

2

U43

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

AOZ1331_SON14_2 X3

20mohm/6A per channel

C826

PCIE_LED#

SATA_LED#<19 >

14

VOUT1

13

VOUT1

12

CT1

11

GND

10

CT2

9

VOUT2

8

VOUT2

15

GPAD

SHORT DEFAULT

+3VS

5

U72

1

VCC

IN1

OUT

2

IN2

GND

MC74VHC1G 08DFT2G_SC70-5

3

placement close PCIE SSD side

1

+

CN40
330U_D2E _6.3VM_R25M

2

+3V_NGFF_1

C435

1 2

1000P_0 402_50V 7K
C434

1 2

1000P_0 402_50V 7K

PCIE_SATA_LED#

4

CR_LED#<32>

+3V_NGFF_2

RN20
10K_040 2_5%

1 2

JUMP_43X118

@

1 2

JUMP_43X118

@

+3VS

12

@

+3VS_NGFF1

J17

+3VS_NGFF2

J27

+3VS

5

1

VCC

IN1

2

IN2

GND

MC74VHC1G 08DFT2G_SC70-5

3

C387

10U_0603_6.3V6M

C386

.1U_0402_16V7K

1

1

2

2

C407

10U_0603_6.3V6M

C408

.1U_0402_16V7K

1

1

2

2

U73

4

OUT

STORAGE_L ED# <38>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

5

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

M.2 SSD PCIe/SATA

M.2 SSD PCIe/SATA

M.2 SSD PCIe/SATA

Document Number Re v

Document Number Re v

Document Number Re v

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

28 103Monday, January 09, 2017

28 103Monday, January 09, 2017

28 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

SSD

NGFF Slot_3 Key M

(right side)

JSSD3

1

GND

3

GND

5

PERn3

7

PERp3

9

GND

11

PETn3

D D

+3VS_NGFF1

12

RN11
10K_040 2_5%

SATA_PRX_ C_DTX_P1B
SATA_PRX_ C_DTX_N1B

SATA_PTX_C_ DRX_N1B
SATA_PTX_C_ DRX_P1B

PEDET2

1 2

SATA_PRX_ DTX_P1B<19>
SATA_PRX_ DTX_N1B<19>

SATA_PTX_DRX_N1B<19>
SATA_PTX_DRX_P1B<19>

SATA_GP2<19>

C C

CN31 0.01U_0 402_16V 7K

1 2

CN30 0.01U_0 402_16V 7K

1 2

CN32 0.01U_0 402_16V 7K

1 2

CN33 0.01U_0 402_16V 7K

RN13 0_0402_5%

1 2

@

34

D

G

5

S

Q36A

@

DMN66D0LDW -7_SOT36 3-6

13

PETp3

15

GND

17

PERn2

19

PERp2

21

GND

23

PETn2

25

PETp2

27

GND

29

PERn1

31

PERp1

33

GND

35

PETn1

37

PETp1

39

GND

41

PERn0/SA TA-B+

43

PERp0/SA TA-B-

45

GND

47

PETn0/SATA-A -

49

PETp0/SATA-A +

51

GND

53

REFCLKN

55

REFCLKP

57

GND

67

NC
PEDET(NC-PCIE/GND-SATA)693P3VAUX

71 72

GND

73

GND

75

GND

LOTES_APCI0096-P00 2A

CONN@

SP07001CS00

3P3VAUX
3P3VAUX

DAS/DSS#

3P3VAUX
3P3VAUX
3P3VAUX
3P3VAUX

DEVSLP

PERST#

CLKREQ#

PEWake#

SUSCLK(32 kHz)

3P3VAUX
3P3VAUX

GND1
GND2

Note: Replace Footprint, PN, Value on original symbol

+3VS_NGFF2

2
4
6

NC

8

NC

10
12
14
16
18
20

NC

22

NC

24

NC

26

NC

28

NC

30

NC

32

NC

34

NC

36

NC

38
40

NC

42

NC

44

NC

46

NC

48

NC

50
52
54
56

NC

58

NC

SUSCLK_S SD3

68
70

74
76

77

DEVSLP2 <1 8>

PLT_RST_BUF# <19,28 ,30,31,32,41,53,6 8>

1 2

SUSCLK

@

RN12 0_0402_5%

SUSCLK <20,28,31>

+3VS_NGFF1

0.047U_0402_16V4Z

1

2

0.047U_0402_16V4Z

33P_0402_50V8J

1

1

1

CN36

CN35

CN34

2

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

33P_0402_50V8J

1

1

CN39

CN38

CN37

2

2

PEDET

0
1

B B

1 2

SATA_PRX_ DTX_P3<19>
SATA_PRX_ DTX_N3<1 9>

SATA_PTX_DRX_N3<1 9>
SATA_PTX_DRX_P3<19>

SATA_GP3<19>

A A

5

CN42 0.01U_ 0402_16 V7K

1 2

CN41 0.01U_ 0402_16 V7K

1 2

CN43 0.01U_ 0402_16 V7K

1 2

CN49 0.01U_ 0402_16 V7K

RN17 0_0402_5%

1 2

61

D

S

Q36B
DMN66D0LDW -7_SOT36 3-6

PEDET

@

G

2

@

0
1

Module Type

SATA

PCIE

SATA_PRX_ C_DTX_P3
SATA_PRX_ C_DTX_N3

SATA_PTX_C_ DRX_N3
SATA_PTX_C_ DRX_P3

+3VS_NGFF2

12

RN15
10K_040 2_5%

PEDET3

Module Type

SATA

PCIE

4

SSD

NGFF Slot_4 Key M

JSSD4

1

GND

3

GND

5

PERn3

7

PERp3

9

GND

11

PETn3

13

PETp3

15

GND

17

PERn2

19

PERp2

21

GND

23

PETn2

25

PETp2

27

GND

29

PERn1

31

PERp1

33

GND

35

PETn1

37

PETp1

39

GND

41

PERn0/SA TA-B+

43

PERp0/SA TA-B-

45

GND

47

PETn0/SATA-A -

49

PETp0/SATA-A +

51

GND

53

REFCLKN

55

REFCLKP

57

GND

67

NC
PEDET(NC-PCIE/GND-SATA)693P3VAUX

71 72

GND

73

GND

75

GND

LOTES_APCI0096-P00 2A

CONN@

SP07001CS00

Note: Replace Footprint, PN, Value on original symbol

3P3VAUX
3P3VAUX

DAS/DSS#

3P3VAUX
3P3VAUX
3P3VAUX
3P3VAUX

DEVSLP

CLKREQ#

PEWake#

SUSCLK(32 kHz)

3P3VAUX
3P3VAUX

PERST#

GND1
GND2

2
4
6

NC

8

NC

10
12
14
16
18
20

NC

22

NC

24

NC

26

NC

28

NC

30

NC

32

NC

34

NC

36

NC

38
40

NC

42

NC

44

NC

46

NC

48

NC

50
52
54
56

NC

58

NC

68
70

74
76

77

3

(right side)

+3VS_NGFF1

DEVSLP3 <1 8>

PLT_RST_BUF#

SUSCLK_S SD4

1 2

SUSCLK

@

RN16 0_0402_5%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

+3VS_NGFF2

0.047U_0402_16V4Z

0.047U_0402_16V4Z

33P_0402_50V8J

33P_0402_50V8J

1

1

1

CN44

2

2

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1

CN45

CN50

CN46

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

CN48

CN47

2

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

M.2 SSD SATA

M.2 SSD SATA

M.2 SSD SATA

Document Number Re v

Document Number Re v

Document Number Re v

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

29 103Monday, January 09, 2017

29 103Monday, January 09, 2017

29 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

UL1

30
29
35
36
33
32

4
2
3

25
26

28
27
41

8

XTLI

7

XTLO

5

LED_0

38
39

LED_2

23

S IC E250 0-RIV1-RL Q FN 40P E-LAN CTRL

LED_1

12

RL13
10K_040 2_5%

1

2

1U_0402_6.3V6K~D

TX_P
TX_N
RX_P
RX_N
REFCLK_P
REFCLK_N
CLKREQ#
PERST#
WAKE#

SMCLK
SMDATA

NC
TESTMODE
GND

XTLI
XTLO

ISOLAT#

LED_0
LED_1
LED_2

+AVDDL

CL23

W=20mils

1

1

CL24

2

2

1U_0402_6.3V6K~D

VDD33

AVDD33

AVDDL
AVDDL
AVDDL
AVDDL

AVDDL_REG

AVDDH

AVDDH_REG

DVDDL_REG

TRXP0

TRXN0

TRXP1

TRXN1

TRXP2

TRXN2

TRXP3

TRXN3

RBIAS

0.1U_0402_16V7K~D

W=40mils

1
16

13

+AVDDL

19
31
34
6

22

+AVDDH

9

37

+DVDDL

LAN_MDIP0

11

LAN_MDIN0

12

LAN_MDIP1

14

LAN_MDIN1

15

LAN_MDIP2

17

LAN_MDIN2

18

LAN_MDIP3

20

LAN_MDIN3

21

40

LX

24

PPS

1 2

10

+RBIAS

RL3

2.37K_0402_1%~D

+3V_LAN

+AVDDH

W=20mils

1

CL7

2

W=20mils

+DVDDL

1

1

CL6

CL5

2

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

close to UL1 pin37

1

CL8

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

1

CL9

2

0.1U_0402_16V7K~D

close to UL1 pin9 close to UL1 pin22

CL25

1

1

2

1

CL26

CL14

2

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

4.7U_0603_6.3V6K~D

CL27

1

2

0.1U_0402_16V7K~D

CL28

1

2

0.1U_0402_16V7K~D

CL29

1

2

0.1U_0402_16V7K~D

CL17

CLK_PCIE_P4<21>
CLK_PCIE_N4<21>

CLKREQ_P CIE#4<21>

PLT_RST_BUF#<19,28,29,31,32,41,53,6 8>

YL1

2

1

15P_0402_50V8J~D

W=40mils

1

CL21

2

0.1U_0402_16V7K~D

PCIE_PRX_DTX_P4
PCIE_PRX_DTX_N4

PCIE_PTX_C_DRX_P4
PCIE_PTX_C_DRX_N4

4

GND2GND

OSC1OSC

3

25MHZ_10PF_7V25000014

2

CL10

CL11

1

1A

1

1

CL19

2

2

1U_0402_6.3V6K~D

PLT_RST_BUF#

15P_0402_50V8J~D

CL20

10U_0603_6.3V6M~D

LAN_PME#

+3V_LAN

+3V_LAN

1

2

PCIE_PRX_DTX_P4<18>
PCIE_PRX_DTX_N4<18>

PCIE_PTX_C_DRX_P4<18>

+3V_LAN

PCIE_PTX_C_DRX_N4<18>

1 2

@

RL10 0_0402_ 5%

1 2

RL1 4.7K_0402_5%~D

+3V_LAN

1

CL16

2

1000P_0402_50V7K~D

D D

EC_PME#<1 9,38>

remind : if no support wake,

don't monitor this pin

+3VALW

C C

4.7U_060 3_6.3V6K

LAN_PW R_EN<38>

CL12

1

2

LAN_PW R_EN

1

CL13

0.1U_040 2_16V7K

2

1

CL15

0.1U_0402_16V7K

2

UL3

5

OUT

IN

GND

4

OC

EN

SY6288C20AAC_SOT23 -5

1
2
3

PCIE_PRX_C_DTX_P4

12

CL1 0.1U_0402_1 6V7K

PCIE_PRX_C_DTX_N4

12

CL2 0.1U_0402_1 6V7K

RL2 30K_0402_5%

1 2

RL11 10K_0402_5%

1 2

RL12 10K_0402_5%

1

CL18

2

10U_0603_6.3V6M~D

1 2

CL22

0.1U_0402_16V7K~D

close to UL1 pin13 close to UL1 pin19close to UL1 pin31close to UL1 pin1 close to UL1 pin16 close to UL1 pin6 close to UL1 pin34

B B

A A

5

check need power or not? 3/15

2

CL31

1

+VDDCT_L

1000P_0402_50V7K~D

1

CL32

2

LAN_MDIN0
LAN_MDIP0

LAN_MDIN1
LAN_MDIP1

LAN_MDIN2
LAN_MDIP2

LAN_MDIN3
LAN_MDIP3

0.1U_0402_16V7K~D

1
2
3

4
5
6

7
8
9

10
11
12

2

1

CL33

CL34

1

2

0.1U_0402_16V7K~D

1000P_0402_50V7K~D

TL1

TCT1

MCT1

TD1+

MX1+

TD1-

MX1-

TCT2

MCT2

TD2+

MX2+

TD2-

MX2-

TCT3

MCT3

TD3+

MX3+

TD3-

MX3-

TCT4

MCT4

TD4+

MX4+

TD4-

MX4-

350UH_GS T5009-CLF

2

1

CL35

CL36

1

2

1000P_0402_50V7K~D

TIMAG: S X'FORM_ IH-160 LAN,SP050006F00
BOTHHAND: S X'FORM_ GST5009-E LF LAN,SP050006B10

RJ45_CT0

24

RJ45_MIDI0 -

23

RJ45_MIDI0 +

22

RJ45_CT1

21

RJ45_MIDI1 -

20

RJ45_MIDI1 +

19

RJ45_CT2

18

RJ45_MIDI2 -

17

RJ45_MIDI2 +

16

RJ45_CT3

15

RJ45_MIDI3 -

14

RJ45_MIDI3 +

13

change to comon

2

1

CL37

CL38

1

2

0.1U_0402_16V7K~D
1000P_0402_50V7K~D

4

0.1U_0402_16V7K~D

RL6

1 2

75_0402 _1%~D

RL7

1 2

75_0402 _1%~D

RL8

1 2

75_0402 _1%~D

RL9

1 2

75_0402 _1%~D

RJ45_GND

JUMP_43X118

3

40mil

RJ45_GND

40mil

@

J5

1 2

C67
10P_040 2_50V8J

2

3

D1

EMC@

MESC5V02 BD03_SOT23-3

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

LAN Connector

RJ45_MIDI0 +
RJ45_MIDI0 ­RJ45_MIDI1 +
RJ45_MIDI2 +
RJ45_MIDI2 ­RJ45_MIDI1 ­RJ45_MIDI3 +
RJ45_MIDI3 -

LANGND

LANGND

12

JP1

XEMC@

B88069X 9231T203_4P5X3P2-2

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

JRJ45

1

TX0+

2

TX0-

3

TX1+

4

TX2+

5

TX2-

6

TX1-

7

TX3+

8

TX3-

9

GND

10

GND

SANTA_130 409-9

CONN@

DC234007A00

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

LAN E2400

LAN E2400

LAN E2400

Document Number Re v

Document Number Re v

Document Number Re v

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

30 103Monday, January 09, 2017

30 103Monday, January 09, 2017

30 103Monday, January 09, 2017

1.0

1.0

1.0

A

B

C

D

E

Wireless LAN

60mil

+3VS +3VS_W LAN

1 2

@

1 1

2 2

R63 0_0805_5%

+3VALW

1

C71
1U_0402_6.3V6K

2

WLAN_PWR_EN<38>

Follow SUSP#.

+3VS_W LAN

R380 10K_0402_5%

1 2

1

C69
.1U_0402_16V7K

2

U9

5

OUT

IN

GND

4

WLAN_PME#

OC

EN

SY6288C20AAC_SOT23-5

1

@

C70
.1U_0402_16V7K

2

W=60mils

1
2
3

1

C68

4.7U_0603_6.3V6K

2

+3VS_W LAN

WLAN

WIGI G

USB2 Port7

(For BT)

PCIE_PTX_C_DRX_P3<18>

PCIE_PTX_C_DRX_N3<18>

PCIE_PRX_DTX_P3<18>
PCIE_PRX_DTX_N3<18>

CLK_PCIE_P3<21>
CLK_PCIE_N3<21>

CLKREQ_PCIE#3<21>

WLAN_PME#<38>

PCIE_PTX_C_DRX_N2<18>

PCIE_PTX_C_DRX_P2<18>

PCIE_PRX_DTX_N2<18>
PCIE_PRX_DTX_P2<18>

CLK_PCIE_N2<21>
CLK_PCIE_P2<21>

USB20_P7<18>
USB20_N7<18>

check WiGig pin define

USB20_P7
USB20_N7

PCIE_PTX_C_DRX_P3
PCIE_PTX_C_DRX_N3

PCIE_PRX_DTX_P3
PCIE_PRX_DTX_N3

CLK_PCIE_P3
CLK_PCIE_N3

WLAN_PME#

PCIE_PTX_C_DRX_N2
PCIE_PTX_C_DRX_P2

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2

CLK_PCIE_N2
CLK_PCIE_P2

JNGFF

1

GND_1

3

USB_D+

5

USB_D-

7

GND_7

9

SDIO_CLK

11

SDIO_CMD

13

SDIO_DAT0

15

SDIO_DAT1

17

SDIO_DAT2

19

SDIO_DAT3

21

SDIO_WAKE

23

SDIO_RST

33

GND_33

35

PET_RX_P0

37

PET_RX_N0

39

GND_39

41

PER_TX_P0

43

PER_TX_N0

45

GND_45

47

REFCLK_P0

49

REFCLK_N0

51

GND_51

53

CLKREQ0#

55

PEWAKE0#

57

GND_57

59

RSVD/PCIE_RX_P1

61

RSVD/PCIE_RX_N1

63

GND_63

65

RSVD/PCIE_TX_P1

67

RSVD/PCIE_TX_N1

69

GND_69

71

RSVD_71

73

RSVD_73

75

GND_75

77

GND2

LOTES_APCI0163-P001A

CONN@

KEY E

3.3VAUX_2

3.3VAUX_4

PCM_SYNC

UART_WAKE

UART_RTS
UART_CTS

CLink_RST

CLink_DATA

CLink_CLK

SUSCLK(32KHz)

W_DISABLE2#
W_DISABLE1#

3.3VAUX_72

3.3VAUX_74

LED1#

PCM_CLK

PCM_OUT

PCM_IN

LED2#

GND_18

UART_TX

UART_RX

COEX3
COEX2
COEX1

PERST0#

I2C_DAT
I2C_CLK

I2C_IRQ
RSVD_64
RSVD_66
RSVD_68
RSVD_70

GND1

2
4
6
8
10
12
14
16
18
20
22

32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74

76

+3VS_W LAN

UART_2_CRXD_DTXD_R

UART_2_CTXD_DRXD_R

E51TXD_P80DATA_R
E51RXD_P80CLK_R

T47@

T48@

T49

@

T50

@

T51

@

SUSCLK_R
WL_RST#_R

WL_OFF#

T52

@

T53

@

T54

@

T65

@

WG_RST#_R
CLKREQ_PCIE#2
WG_PME#

PH +3VS at SOC side, for win7 USB3 debug

1 2

R64 0_0402_5%

1 2

R65 0_0402_5%

1 2

R66 0_0402_5%@

1 2

R422 0_0402_5%@

1 2

R71 0_0402_5%@

1 2

R72 0_0402_5%@

1 2

R74 0_0402_5%@

1 2

R75 0_0402_5%@

@

@

UART_2_CRXD_DTXD

UART_2_CTXD_DRXD

PLT_RST_BUF#
WLAN_PME#

E51RXD_P80CLK and BT_ON enable seperate.

R69 100K_0402_5%

SP071603150

NGFF WL+BT (KEY E)
WiGig

Note: Replace Footprint, PN, Value on original symbol

UART_2_CRXD_DTXD <22>

UART_2_CTXD_DRXD <22>

12

E51TXD_P80DATA <38>
E51RXD_P80CLK <38>

SUSCLK <20,28,29>

PLT_RST_BUF# <19,28,29,30,32,41,53,68>
BT_ON <38>
WL_OFF# <38>

CLKREQ_PCIE#2 <21>

3 3

4 4

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/02/01 2017/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

M.2 Key E (WLAN)

M.2 Key E (WLAN)

M.2 Key E (WLAN)

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1.0

1.0

1.0

31 103Monday, January 09, 2017

31 103Monday, January 09, 2017

31 103Monday, January 09, 2017

E

5

4

3

2

1

USB3.0 I/O & SUB/B

60pin I/O Conn.

JUSB2

CONN@

D D

+5VALW

.1U_0402_16V7K

22U_0603_6.3V6M

C413

1

1

C412

2

2

PCH input (Host)

U3 Port2

close JUSB2

CARD READER

C C

USB3_PRX_DTX_P2<18>
USB3_PRX_DTX_N2<18>

USB3_PTX_DRX_N2<18>
USB3_PTX_DRX_P2<18>

+5VALW

EC_MUTE#<36,38>

EC_AMP_GAIN0<38>
EC_AMP_GAIN1<38>

EC_SMB_CK2<20,26,36,38,41,53>
EC_SMB_DA2<20,26,36,38,41,53>

PLT_RST_BUF#<19,28,29,30,31,41,53,68>
PCIE_PRX_DTX_P1<18>
PCIE_PRX_DTX_N1<18>

PCIE_PTX_C_DRX_P1<18>
PCIE_PTX_C_DRX_N1<18>

CLK_PCIE_P1<21>
CLK_PCIE_N1<21>

CLKREQ_PCIE#1<21>

+3VS +3VS

1

1

3

3

5

5

7

7

9

9
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950

51

51

53

53

55

55

57

57

59

59

61

GND

63

GND

65

GND

ACES_50050-06071-001

SP01001BY00

GND
GND
GND

2

2

4

4

6

6

8

8

10

10

12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

52

54

54

56

56

58

58

60

60

62
64
66

USB20_P2 <18>
USB20_N2 <18>

USB_EN <38>

+5VALW

+3VALW

+5VALW

GNDA

MIC_IN_L <36>

MIC_IN_R <36>

HPOUT_L <36>

HPOUT_R <36>

HP_AMP_EN <38>

SUSP# <25,26,28,38,68,75,77,79,80>

HPOUT_JD <36,38>

MIC_JD <36>

CR_LED# <28>

USB SUB/B CONN

+3VALW

1

1

B B

.1U_0402_16V7K

C87

2

C86
1U_0402_6.3V6K

2

USB A

charge port

USB B

+5VALW

.1U_0402_16V7K

22U_0603_6.3V6M

C415

1

1

218mA

C414

2

2

For 2nd 59116
DVT 7/11

USB3_PTX_DRX_N4<18>
USB3_PTX_DRX_P4<18>

USB3_PRX_DTX_P4<18>
USB3_PRX_DTX_N4<18>

USB3_PTX_DRX_P5<18>
USB3_PTX_DRX_N5<18>

USB3_PRX_DTX_P5<18>
USB3_PRX_DTX_N5<18>

USB20_P4<18>

USB20_N4<18>

LEDPWR_EN<38>

EC_SMB_CK3<35,38,70>
EC_SMB_DA3<35,38,70>

50pin USB3 Conn.

USB20_P4
USB20_N4

+3VALW

USB_EN

close JUSB3

PAD

T75

USB20_N5<18>

USB20_P5<18>

A A

5

4

3

@

PAD

T76

@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

JUSB3

52

G151G2

49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11

9
7
5
3
1

50

49

50

48

47

48

46

45

46

44

43

44

42

41

42

40

39

40

38

37

38

36

35

36

34

33

34

32

31

32

30

29

30

28

27

28

26

25

26

24

23

24

22

21

22

20

19

20

18

17

18

16

15

16

14

13

14

12

11

12

10

9

10

8

7

8

6

5

6

4

3

4

2

1

2

CVILU_CBRB050SE2FP1R0-NH

CONN@

SP01001I300

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+5VALW

2

BI_S1 <40>

USB_CHARGE_2A <38>

USB_CB <38>

USB_SELCDP <38>

USB_CEN <38>

12

+3VLP

R35210K_0402_5%

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet

Compal Electronics, Inc.

USB3.0 Redriver

USB3.0 Redriver

USB3.0 Redriver

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

of

32 103Monday, January 09, 2017

32 103Monday, January 09, 2017

32 103Monday, January 09, 2017

1.0

1.0

1.0

A

INT_KBD Conn.

B

C

D

E

1 1

+5VALW +5V_KB

C100

EMC@

.1U_0402_16V7K

1 2

USBKB_EN<38>

USBKB_EN

support wake follow SYSON

2 2

U12

5

IN

4

EN

SY6288C20AAC_SOT23-5

SA000079400

OUT
GND

+5V_KB

C437

47U_0805_6.3V6M~D

W=100mils

12

C101

@

22U_0603_6.3V6M

1

1

C102

EMC@

2

2

.1U_0402_16V7K

1

W=60mils

2
3

OC

USB20_N10<18>

USB20_P10<18>

USB20_N12<18>

USB20_P12<18>

USB20_P10

USB20_P12

1 2

@

R96 0_0402_5%

1 2

@

R97 0_0402_5%

1 2

@

R384 0_0402_5%

1 2

@

R383 0_0402_5%

USB20_N10_RUSB20_N10

USB20_P10_R

USB20_N12_RUSB20_N12

USB20_P12_R

USB20_N12_R

+5V_KB

USB20_P12_R

add for KB BL

1A_check spec

+5V_KB

I = 0.5A

USB20_N10_R
USB20_P10_R
USB20_N12_R
USB20_P12_R

D33

XEMC@

6

I/O4

5

VDD

GND

4

I/O3

AZC099-04S.R7G_SOT23-6

SC300001G00

JKB1

1

1

2

2

3

3

4

4

5

G7

5

6

G8

6

ACES_50273-0060N-001

CONN@

SP020010E00

3

I/O2

2

1

I/O1

7
8

USB20_N10_R

USB20_P10_R

Touch PAD use POGO design

3 3

POGO_EN<38>

support wake follow SYSON and SLIDE_DET#

4 4

A

+5VALW

1 2

.1U_0402_16V7K

1U_0402_6.3V6K

1

12

C104

C105

2

U13

5

OUT

IN

GND

4

OC

EN

SY6288C20AAC_SOT23-5

SA000079400

SLIDE_DET#<38>

DMN66D0LDW -7_SOT363-6

1
2
3

+3VALW

34

D

G

5

S

Q37A

1

C106

2

.1U_0402_16V7K

12

R805
100K_0402_5%

61

D

G

S

Q37B
DMN66D0LDW -7_SOT363-6

B

1

C107

2

2

+5V_POGO

12

C108

22U_0603_6.3V6M

+3VALW

12

R804
100K_0402_5%

SLIDE_DET#_POGO

@

47U_0805_6.3V6M~D

USB20_P6<18>

USB20_N6<18>

USB20_N6_L

USB20_P6_L

C

@

R109 0_0402_5%

1 2

@

R110 0_0402_5%

D30

6

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

XEMC@

I/O4

I/O2

VDD

GND

I/O3

I/O1

AZC099-04S.R7G_SOT23-6

SC300001G00

USB20_P6_L

USB20_N6_L

SLIDE_DET#_POGO

3

2

POGO_FN_R

1

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

POGO_FN<38>

D

+5V_POGO

I = 1A

USB20_N6_L
USB20_P6_L

POGO_FN_R

SLIDE_DET#_POGO

R382

20K_0402_5%

1 2

R381 10K_0402_5%

12

checked 3/15

High

POGO_FN

number keyTouch pad

Un-plug is low.

Gnd/Vbus/D-/D+/Det/Gnd _ module side pindefine

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Compal Electronics, Inc.

KEY BOARD

KEY BOARD

KEY BOARD

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Low

E

JPOGO1

1

1

2

2

3

3

4

9

4

GND

5

10

5

GND

6

6

7

7

8

8

CONN@

ACES_87212-08G0L

SP020008R00

33 103Monday, January 09, 2017

33 103Monday, January 09, 2017

33 103Monday, January 09, 2017

1.0

1.0

1.0

A

B

C

D

E

3D CAMERA

1 1

USB3_PTX_DRX_N6<18>
USB3_PTX_DRX_P6<18>

USB3_PRX_DTX_P6<18>

USB3_PRX_DTX_N6<18>

2 2

USB3_PTX_DRX_N6
USB3_PTX_DRX_P6

USB3_PRX_DTX_P6
USB3_PRX_DTX_N6

PAD

T71

@

PAD

T72

@

PAD

T73

@

PAD

T74

@

Tobii Eye Tracker

+5VALW

C126

TOBII@

.1U_0402_16V7K

1 2

3 3

TOBII_EN<38>

TOBII_EN

U19

5

IN

4

EN

SY6288C20AAC_SOT23-5

TOBII@

follow SUSP#

+5V_TOBII

TOBII@

TOBII@

1

12

C441

C442

2

GND

+5V_TOBII

1
2
3

+5V_TOBII

1

C124
.1U_0402_16V7K

2

TOBII@

W=60mils

JTOBII

CONN@

USB20_N11<18>

USB20_P11<18>

USB20_N11

USB20_P11

1 2

@

R121 0_0402_5%

1 2

@

R122 0_0402_5%

USB20_N11_R

USB20_P11_R

+5V_TOBII

USB20_N11_R
USB20_P11_R

1

1

2

2

3

3

4

4

7

5

G7

5

8

6

G8

6

ACES_50273-0060N-001

SP020010E00

OUT

OC

22U_0603_6.3V6M

47U_0805_6.3V6M~D

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

Compal Electronics, Inc.

CAMERA

CAMERA

CAMERA

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

E

1.0

1.0

34 103Monday, January 09, 2017

34 103Monday, January 09, 2017

34 103Monday, January 09, 2017

1.0

5

+5VALW

D D

LBPWR_EN<38>

1 2

@

RE20 0_0402_5%

UE3

5

OUT

IN

GND

4

OC

EN

SY6288C20AAC_SOT23-5

1
2
3

+5V_LBPWR

follow SYSON

DMN66D0LDW -7_SOT363-6

EC_SMB_CK3

EC_SMB_DA3

C C

+5V_LBPWR

RE23

4.7K_0402_5%

LB_LED_R2_DRV#

+5V_LBPWR

B B

4.7K_0402_5%

LB_LED_G2_DRV#

4.7K_0402_5%

LB_LED_B2_DRV#

RE27

+5V_LBPWR

RE31

+5V_LBPWR

12

12

12

12

RE21
1K_0402_5%

LB_LED_R2_DRV

34

D

G

5

S

QE4A
DMN66D0LDW -7_SOT363-6

+5V_LBPWR

12

RE25
1K_0402_5%

LB_LED_G2_DRV

61

D

G

2

QE4B

S

DMN66D0LDW -7_SOT363-6

+5V_LBPWR

12

RE29
1K_0402_5%

LB_LED_B2_DRV

61

D

G

2

QE17B

S

DMN66D0LDW -7_SOT363-6

2

G

2

G

2

G

LB_LED_R2_DRV#_A#

13

D

QE34
AO3418L_SOT23-3

S

LB_LED_G2_DRV#_A#

13

D

QE35
AO3418L_SOT23-3

S

LB_LED_B2_DRV#_A#

13

D

QE36
AO3418L_SOT23-3

S

4

EC_SMB_CK3<32,38,70>
EC_SMB_DA3<32,38,70>

+5V_LBPWR

QH4A

@

2

6 1

QH4B

DMN66D0LDW -7_SOT363-6

@

default bypass

4.7K_0402_5%

LB_LED_R3_DRV#

4.7K_0402_5%

LB_LED_G3_DRV#

4.7K_0402_5%

LB_LED_B3_DRV#

1 2

RE52 0_0402_5%@

1 2

RE53 0_0402_5%@

+5V_LBPWR

5

3 4

LOGO Backlight

+5V_LBPWR

12

RE24

+5V_LBPWR

12

RE28

+5V_LBPWR

12

RE32

RE55

2.2K_0402_5%

2.2K_0402_5%

12

12

@

EC_SMB_CK3_LBPWR

EC_SMB_DA3_LBPW R

+5V_LBPWR

12

RE22
1K_0402_5%

LB_LED_R3_DRV

61

D

G

2

QE2B

S

DMN66D0LDW -7_SOT363-6

+5V_LBPWR

12

RE26

1K_0402_5%

LB_LED_G3_DRV

34

D

G

5

S

QE3A
DMN66D0LDW -7_SOT363-6

+5V_LBPWR

12

RE30
1K_0402_5%

LB_LED_B3_DRV

61

D

G

2

QE3B

S

DMN66D0LDW -7_SOT363-6

3

+5V_LBPWR

12

EC_SMB_CK3_LBPWR
EC_SMB_DA3_LBPW R

1 2

RE3 4.7K_0402_1%~D

1 2

RE4 4.7K_0402_1%~D

1 2

RE5 4.7K_0402_1%

1 2

RE54

@

RE6 4.7K_0402_1%

12

RE7
10K_0402_5%

AD3 AD2 AD1 AD0
0 0 0 0

RE2

4.7K_0402_1%

24

25
26

31

AD0

32

AD1

1

AD2

2

AD3

12
13
28
29
30

7

18

UE1

RESET

SCL
SDA

A0
A1
A2
A3

N.C.
N.C.
N.C.
N.C.
N.C.

GND
GND

TLC59116FIRHBR_VQFN32_5X5

OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8

OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15

GND
GND

27

Vcc

3
4
5
6
8
9
10
11
14
15
16
17
19
20
21
22

23
33

set RE7 to 10k / output = 1.875mA

R Light Bar BacklightL Light Bar Backlight

+5V_LBPWR

12

RE14
1K_0402_5%

LB_LED_R1_DRV

34

D

G

5

S

QE1A
DMN66D0LDW -7_SOT363-6

+5V_LBPWR

12

RE16
1K_0402_5%

LB_LED_G1_DRV

61

D

G

2

QE1B

S

DMN66D0LDW -7_SOT363-6

+5V_LBPWR

12

RE18
1K_0402_5%

LB_LED_B1_DRV

34

D

G

5

S

QE2A
DMN66D0LDW -7_SOT363-6

2

G

2

G

2

G

LB_LED_R3_DRV#_A#

13

D

QE31
AO3418L_SOT23-3

S

LB_LED_G3_DRV#_A#

13

D

QE32
AO3418L_SOT23-3

S

LB_LED_B3_DRV#_A#

13

D

QE33
AO3418L_SOT23-3

S

4.7K_0402_5%

LB_LED_R1_DRV#

4.7K_0402_5%

LB_LED_G1_DRV#

4.7K_0402_5%

LB_LED_B1_DRV#

+5V_LBPWR

12

RE15

+5V_LBPWR

12

RE17

+5V_LBPWR

12

RE19

+5V_LBPWR

LB_LED_R1_DRV#
LB_LED_G1_DRV#
LB_LED_B1_DRV#
LB_LED_R2_DRV#
LB_LED_G2_DRV#
LB_LED_B2_DRV#
LB_LED_R3_DRV#
LB_LED_G3_DRV#
LB_LED_B3_DRV#
FAN_LED_R_DRV#
FAN_LED_G_DRV#
FAN_LED_B_DRV#
PWR_LED_R_DRV#
PWR_LED_G_DRV#
PWR_LED_B_DRV#

2

1

CE1
.1U_0402_16V7K

2

R
L
LOGO

Fan/PWR board

LB_LED_R1_DRV#_A#

13

D

2

QE28

G

AO3418L_SOT23-3

S

LB_LED_G1_DRV#_A#

13

D

2

QE29

G

AO3418L_SOT23-3

S

LB_LED_B1_DRV#_A#

13

D

2

QE30

G

AO3418L_SOT23-3

S

Light Bar

EC_ESB_CLK<38>
EC_ESB_DAT<38>

+5VALW

+3VLP

EC_ESB_CLK
EC_ESB_DAT

1

SP02000I900

ACES_87212-1600L

CONN@

18
17
16
15
14
13
12
11
10

SP020008R00

ACES_87212-08G0L

8
7
6
5
4
3
2
1

2

PWR_LED_R_DRV#

4

PWR_LED_G_DRV#

6

PWR_LED_B_DRV#

8
10
12
14
16
18
20

22

9
8
7
6
5
4
3
2
1

FAN B

CONN@

JFANBL

+5VALW

LB_LED_R1_DRV#_A#
LB_LED_G1_DRV#_A#
LB_LED_B1_DRV#_A#
LB_LED_R2_DRV#_A#
LB_LED_G2_DRV#_A#
LB_LED_B2_DRV#_A#
LB_LED_R3_DRV#_A#
LB_LED_G3_DRV#_A#
LB_LED_B3_DRV#_A#

+5VALW

FAN_LED_R_DRV#
FAN_LED_G_DRV#
FAN_LED_B_DRV#

+5V_LBPWR

PWR B / Marco Key

JPWR

112
334
556
778
9910
111112
131314
151516
171718
191920

G121G2

ACES_87216-2016

SP02000IT00

CONN@

JLB1

8
7
6
5
4
3
2
1

GND
GND
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

GND
GND

10
9

+5VALW

ON/OFFBTN# <38,40>

LID_SW# <38>

+3VLP
+5V_LBPWR

A A

QE17A

S

5

G

D

3 4

DMN66D0LDW -7_SOT363-6

5

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

A Cover BKL

A Cover BKL

A Cover BKL

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

1

35 103Monday, January 09, 2017

35 103Monday, January 09, 2017

35 103Monday, January 09, 2017

1.0

1.0

1.0

A

SM01000EJ00 3000ma 220ohm@100mhz

+VDDA

DCR 0.05

LA1

1 2

HCB2012K F-221T30_2P_0805

CA3

10U_0402_6.3V6M

CA4

.1U_0402_16V7K

1

1 1

1

2

2

CA5

10U_0402_6.3V6M

.1U_0402_16V7K

1

1

2

2

CA7

10U_0402_6.3V6M

CA8

CA6

.1U_0402_16V7K

1

1

2

2

near Pin46near Pin41

1 2

CA10 .1U_ 0402_16 V7K

near Pin18

1 2

+3VS

2 2

SML1CLK_ AUDIO
SML1DATA_A UDIO

+3VS_DVDD

EAPD<37>

3 3

J19
JUMP_43X39

112

J20
JUMP_43X39

112

J21
JUMP_43X39

112

J22
JUMP_43X39

112

J31
JUMP_43X39

112

J30
JUMP_43X39

112

J32
JUMP_43X39

112

@

RA6 10K_0402_5%
RA7 10K_0402_5%@

2

2

2

2

2

2

2

RA860_0402_5%

EC_MUTE#<3 2,38>

HDA_RST#_R<2 0>

@

@

@

@

4 4

@

@

@

1 2

GND GNDA

@

RA5 0_0402_5%

1 2

+3VS

RA1 0_0402_5%

+3VS_DVDD

RA23

4.7K_0402_5%

4.7K_0402_5%

12

CA23 1U_0 402_6.3V6K

1 2

@

RA75 100K _0402_1 %

+3VS_DVDD

12

12
12

I2C for EC to AMP (just need when boot)
need check ref circuit 0427

OE

A

@

L

H

A=B Open

12

1 2

CA9 10U_04 02_6.3V6M

@

near Pin3

LINE1_L
LINE1_R

RA21

12

DMIC_DATA
DMIC_CLK

I2S_MCLK
I2S_DIN_R
I2S_LRCK
I2S_BCLK
I2S_DOUT

1 2

MONO_IN

MUTE#

LINE1_JD1

10U_0402_6.3V6M

@

RA3
100K_04 02_1%

RA4
10K_040 2_5%

EC_SMB_CK2<20,26,32,3 8,41,53>

1

2

CA29

CA1

10U_0402_6.3V6M

MUTE# <37>

GNDA

.1U_0402_16V7K

1

2

1

2

+3VS_DVDDIO

+3VS_DVDD

CA2

UA1

36

LINE1-L(PO RT-C-L)

35

LINE1-R(PORT-C-R)

30

MIC2-L(PORT-F-L) /RING2

31

MIC2-R(PORT-F-R) /S LEEVE

4

GPIO0/DMIC-DATA12

1

GPIO2/DMIC-DATA34

5

GPIO1/DMIC-CLK

7

I2C-CLK

6

I2C-DATA

11

I2S-MCLK

8

I2S-IN

12

I2S-LRCK

10

I2S-BCLK

9

I2S-OUT

23

CBP

24

CBN

34

PCBEEP

13

DC-DET/EAPD

2

PDB

48

HP/LINE1-JD(JD1)

47

I2S-IN/I2S-OUT-JD(JD2)

32

MIC2-CAP

ALC299-CG _MQFN48_6 X6

AMP_INIT

1 2

18

3

DVDD

DVDD-IO

PCH_SPKR<20>

RA790_0402_ 5% @

B

+5VS_PVDD

+5VS_AVDD

+1.8VS_A VDD

40

41

46

AVDD1

PVDD1

PVDD2

BEEP#<38>

UA4

1

OE1

VCC

2

1A

OE2

3

1B

2B

4

GND

2A

SN74CBT3306PWR_TSSOP8~H

B

SM01000EJ00 3000ma 220ohm@100mhz
DCR 0.04

near Pin40

+5VALW

20

33

LA2

1 2

HCB2012K F-221T30_2P_0805

CA15

.1U_0402_16V7K

CA14

10U_0402_6.3V6M

1

1

2

2

GNDA

1

2

near Pin20

CPVDD/AVDD2

5VSTB/AUX MODE

43

SPK-OUT-L-

42

SPK-OUT-L+

45

SPK-OUT-R+

44

SPK-OUT-R-

MIC2-VREFO-R

MIC2-VREFO-L

LDO1-CAP
LDO2-CAP
LDO3-CAP

VREF

CPVEE
AVSS1

AVSS2

Thermal Pad

+5VS

1 2

RA80 0_040 2_5%@

27
26

15
14
17
16

29
28

39
21
19

38

25
37

22
49

CA33

100P_04 02_50V8 J

2

CA75
.1U_0402 _16V7K

1

HPOUT-L(PORT-I-L)

HPOUT-R(PORT-I-R)

AUDIOLINK:SYNC

AUDIOLINK:BCLK

AUDIOLINK:SDATA-OUT

AUDIOLINK:SDATA-IN

RA19
1K_0402 _5%

1 2

1 2

RA20
1K_0402 _5%

8
7
6
5

RA56 0_0 402_5%

CA17

.1U_0402_16V7K

CA16

10U_0402_6.3V6M

1

2

GNDA

299_SPK L­299_SPK L+

299_SPK R+
299_SPK R-

HDA_SYNC_R
HDA_BIT_CLK _R
HDA_SDOUT_R
HDA_SDIN0_AUDIO

CODEC_VRE F

CPVEE

GNDA GNDAGNDA

1

2

@

1 2

12

RA22
10K_040 2_5%

+5VS +VDDA

J18

1 2

JUMP_43X118

@

+VDDA

CA11

10U_0402_6.3V6M

CA13

.1U_0402_16V7K

1

1

2

2

+1.8VS

@

1 2

RA17 33_0402_5%

+MIC2_VREFO_R
+MIC2_VREFO_L

CA24

10U_0402_6.3V6M

1

1

2

2

CA28

2.2U_0402_6.3V6M

CA27

1U_0402_6.3V6K

1

1

2

2

1 2

CA30 .1U_0402_16V7K

AMP_INIT <3 8>

SML1DATA_A UDIO <37>SML1CLK_ AUDIO<37>

EC_SMB_DA2 <20,26,3 2,38,41,53>

GNDA GNDA

MONO_INBEE P#_R

CA25

10U_0402_6.3V6M

10U_0402_6.3V6M

1

2

C

HPOUT_L <3 2>
HPOUT_R <32>

HDA_SYNC_R <20>
HDA_BIT_CLK _R <20>
HDA_SDOUT_R <20>

HDA_SDIN0 <20>

RA18

100K_0402_5%

CA26

12

HPOUT_JD_R

MIC_JD_R

C

D

299_SPK L+

1006_SP KL+<37>
1006_SP KL-<3 7>

299_SPK R+
299_SPK R-

1006_SP KR+<37>
1006_SP KR-<37>

HDA_BIT_CLK _R

12

RA83

EMC@

100_040 2_5%

1

CA78

EMC@

330P_04 02_50V7 K

2

+3VS_DVDD

12

RA73

2

G

QA2
L2N7002WT1G_SC-7 0-3

+3VS_DVDD

12

2

G

QA3
L2N7002WT1G_SC-7 0-3

Issued Date

Issued Date

Issued Date

100K_04 02_1%

HPOUT_JD <32,38>

RA74
100K_04 02_1%

MIC_JD <32>

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

13

D

S

1 2

@

RA76 0_0402_5 %

13

D

S

1 2

@

RA77 0_0402_5 %

Close Type = reverse

Open type = bypass

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

1 2

LA7 PBY16 0808T-121Y-N_ 2PEMC@

1 2

LA8 PBY16 0808T-121Y-N_ 2PEMC@

1 2

LA9 PBY16 0808T-121Y-N_ 2PEMC@

1 2

LA10 PBY160808T-121Y-N_2PEMC@

1006_SP K_L-<37>

680P_04 02_50V7 K

1 2

LA3 PBY16 0808T-121Y-N_ 2PEMC@

1 2

LA4 PBY16 0808T-121Y-N_ 2PEMC@

1 2

LA5 PBY16 0808T-121Y-N_ 2PEMC@

1 2

LA6 PBY16 0808T-121Y-N_ 2PEMC@

1006_SP K_R-<37>

DMIC-IN

L03ESDL5V0CC3-2_SOT23-3

680P_04 02_50V7 K

DA3

1

MESC5V02 BD03_SOT23-3

XEMC@

DA4

1

MESC5V02 BD03_SOT23-3

XEMC@

DA7

XEMC@

1

CA79

EMC@

330P_04 02_50V7 K

12

CA32

EMC@

10P_040 2_50V8J

12

Headphone Out

MIC-IN

LINE1_L
LINE1_R

JACK Detect

JD1

LINE1-JD

HP-JD

100K

200K

I2S_MCLK

RA28 33_040 2_5%

I2S_LRCK

RA29 33_040 2_5%

I2S_BCLK

RA30 33_040 2_5%

I2S_DOUT

RA31 33_040 2_5%

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

CA65

XEMC@

CA63

XEMC@

299_SPK _R+

2

299_SPK _R-

3

1006_SP K_R+

2

1006_SP K_R-_R

3

DMIC_DATA

2

DMIC_CLK_L

3

RA85

EMC@

100_040 2_5%

+MIC2_VREFO_R
+MIC2_VREFO_L

1 2

CA21 4.7 U_0603_6.3V6K

1 2

CA22 4.7 U_0603_6.3V6K

1 2
1 2
1 2
1 2

40mil

1 2

RA62 0.1_0402_1%

1006_SP K_L-_R<37>1006_SPK_L+<37>

1

1

CA66
680P_04 02_50V7 K

2

2

XEMC@

1 2

RA61 0.1_0402_1%

1

1

1006_SP K_R-_R<37>1006_ SPK_R+<37>

CA64
680P_04 02_50V7 K

2

2

XEMC@

DMIC_CLK

1 2

LA15

EMC@

FBMA-L11-1 60808-22 1LMT_2P

DMIC_CLK

12

HPOUT_L
HPOUT_R

XEMC@

1 2

CA76 330 P_0402_ 50V7K

1 2

CA77 330 P_0402_ 50V7K

XEMC@

Reserved by vendor request, 5/9.

1 2

RA15 2.2K_0402_5%

1 2

RA16 2.2K_0402_5%

1 2

RA8 1K_040 2_5%

1 2

RA9 1K_040 2_5%

+3VS_DVDD

12

RA12

100K_04 02_1%

CA20

.1U_0402_16V7K

1

@

2

CA36

22P_0402_50V8J

CA35

22P_0402_50V8J

1

2

XEMC@

XEMC@

CA38

22P_0402_50V8J

CA37

22P_0402_50V8J

1

2

1

1

2

2

XEMC@

XEMC@

Place Close Codec

Custom

Custom

Custom
Date: Sheet of

Date: Sheet of

Date: Sheet of

E

299_SPK _L+
299_SPK _L-

1006_SP K_L+
1006_SP K_L-_R

6
5
4
3
2
1

ACES_87212-04G0

CONN@

SP020008V00

JSPK1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

GND1

10

GND2

ACES_50273-0080N-001

CONN@

SP020010D00

JDMIC1

GND
GND
4
3
2
1

299_SPK _L+
299_SPK _L-299_SPK L­1006_SP K_L+
1006_SP K_L-_R

299_SPK _R+
299_SPK _R­1006_SP K_R+
1006_SP K_R-_R

DA5

1

MESC5V02 BD03_SOT23-3

XEMC@

DA6

1

MESC5V02 BD03_SOT23-3

XEMC@

CA31

.1U_0402 _16V7K

DMIC_DATA
DMIC_CLK_L

2
3

2
3

+3VS

1

2

Place near codec.

GNDA

MIC_IN_L <32>
MIC_IN_R <32 >

HPOUT_JD_RLINE1_JD1

12

RA13200K_0 402_1%

MIC_JD_R

12

RA14100K_0 402_1%

I2S_MCLK_R
I2S_LRCK_R
I2S_BCLK _R
I2S_DOUT_R
I2S_DIN_R

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

HD Audio Codec ALC299

HD Audio Codec ALC299

HD Audio Codec ALC299

Size

Document Number Re v

Size

Document Number Re v

Size

Document Number Re v

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

E

I2S_MCLK_R <37>
I2S_LRCK_R <37>
I2S_BCLK _R <37>
I2S_DOUT_R <37 >

I2S_DIN_R <37>

36 103Monday, January 09, 2017

36 103Monday, January 09, 2017

36 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

For SPK Conn.

D D

RA72 0_0402_5%

C C

B B

A A

+3VS_DVDDIO_AMP

1 2

@

CA40

10U_0402_6.3V6M

1

2

1 2

@

RA70 0_0402_5%

+3VS_DVDDIO_AMP +1.8VS_DVDD_AMP

CA42

.1U_0402_16V7K

CA43

10U_0402_6.3V6M

1

1

2

2

+3VS_DVDDIO_AMP

12

12

Address Set t i ng
Hi:0x26

CA39

.1U_0402_16V7K

1

2

CA41

.1U_0402_16V7K

1

2

CA44

.1U_0402_16V7K

1

2

RA54
10K_0402_5%

ASEL2

RA55
10K_0402_5%

@

+1.8VS+3VS

1 2

RA71 0_0402_5%

Hi:0x 26
Low:0x24

EAPD<36>

MUTE#<36>

+1.8VS_AVDD_AMP

@

+3VS_DVDDIO_AMP

Address Set t i ng

Low:0x24

+1.8VS_AVDD_AMP

CA48

10U_0402_6.3V6M

1

1

2

2

+5VS_PVDD_AMP

12

RA60
10K_0402_5%

@

PBTL2

12

RA59
0_0402_5%

Output Mode Select i on

Low:BTL
Hi:PBTL

CA46

10U_0402_6.3V6M

1

2

12

@

12

CA47

.1U_0402_16V7K

CA45

.1U_0402_16V7K

1

2

RA52
10K_0402_5%

ASEL1

RA53
10K_0402_5%

DA1

2

3

BAT54ATB_SOT-523-3

1

2

CA61

10U_0402_6.3V6M

1

LDO_1V5_UA3

.1U_0402_16V7K

1

2

LDO_1V5_UA2

CA49

.1U_0402_16V7K

CA50

10U_0402_6.3V6M

1

1

2

2

+5VS_PVDD_AMP+1.8VS_DVDD_AMP+1.8VS

12

RA58
10K_0402_5%

@

PBTL

12

RA57
0_0402_5%

Output Mode Select i on

Low:BTL
Hi:PBTL

+3VS_DVDDIO_AMP

12

RA78
100K_0402_1%

AMP_PD

+1.8VS_DVDD_AMP +5VS_PVDD_AMP
+3VS_DVDDIO_AMP

CA62

+1.8VS_AVDD_AMP

close IC

+1.8VS_DVDD_AMP
+3VS_DVDDIO_AMP

+1.8VS_AVDD_AMP

SML1DATA_AUDIO<36>
SML1CLK_AUDIO<36>

CA55 1U_0402_6.3V6K

close IC

CA56 2.2U_0402_6.3V6M
CA57 2.2U_0402_6.3V6M

LDO_1V5_UA3

SML1DATA_AUDIO
SML1CLK_AUDIO

I2S_MCLK_R
I2S_BCLK_R
I2S_LRCK_R
I2S_DOUT_R
I2S_DIN

AMP_PD

ASEL2
PBTL2

1 2

CA58 1U_0402_6.3V6K

1 2

CA59 2.2U_0402_6.3V6M

1 2

CA60 2.2U_0402_6.3V6M

GNDA

LDO_1V5_UA2

I2S_MCLK_R
I2S_BCLK_R
I2S_LRCK_R
I2S_DOUT_R
I2S_DIN

AMP_PD

ASEL1
PBTL

1 2
1 2
1 2

GNDA

For woofer Conn.

13
12

17
18

3
4

5
6
7
8

10

9

11

14
30

19

2

28

15
16
20

ALC1006-CG_QFN48_6X6

UA2

13

DVDD

12

DVDD_IO

17

AVDD2

18

LDO_A1.5

3

SDA

4

SCL

5

MCLK

6

BCLK

7

LRCLK

8

DACDAT

10

SPDIF_OUT/I2S_DATAOUT

9

SPDIF_IN

11

PBD_JD

14

ASEL

30

GND

19

VREF

2

BYPASS_2

28

BYPASS_28

15

DVSS

16

AGND_16

20

AGND_20

ALC1006-CG_QFN48_6X6

UA3

DVDD
DVDD_IO

AVDD2
LDO_A1.5

SDA
SCL

MCLK
BCLK
LRCLK
DACDAT
SPDIF_OUT/I2S_DATAOUT
SPDIF_IN

PBD_JD

ASEL
GND

VREF
BYPASS_2
BYPASS_28

DVSS
AGND_16
AGND_20

SPK R

SPK L

RISENSE-/RVSENSE+

LISENSE-/LVSENSE+

ASK vendor for sense pin connect i on

44

PVDD_R

47

PGND_R

RISENSE+
RVSENSE-

LVSENSE-

AVDD1_43
AVDD1_42

44
47

25
46
24
26
45
41

38
22
39
21
23
40

43
42

1
27
29
37
36
35
34
33
32
31
48
49

OUT_RN

OUT_RP
PVDD_L

PGND_L

OUT_LN

LISENSE+

OUT_LP

NC_1
NC_27
NC_29
NC_37
NC_36
NC_35
NC_34
NC_33
NC_32
NC_31
NC_48

E_PAD

WOOFER_1-_R

WOOFER1­WOOFER_1-

WOOFER_1+

WOOFER1+

WOOFER_2-_R

WOOFER2­WOOFER_2-

WOOFER_2+

WOOFER2+

25
46
24
26
45
41

38
22
39
21
23
40

43
42

1
27
29
37
36
35
34
33
32
31
48
49

SPK R

SPK L

RISENSE-/RVSENSE+

LISENSE-/LVSENSE+

PVDD_R
PGND_R

OUT_RN

RISENSE+

RVSENSE-

OUT_RP
PVDD_L

PGND_L

OUT_LN
LISENSE+
LVSENSE-

OUT_LP

AVDD1_43
AVDD1_42

NC_1
NC_27
NC_29
NC_37
NC_36
NC_35
NC_34
NC_33
NC_32
NC_31
NC_48
E_PAD

+5VS_PVDD_AMP

+5VS_PVDD_AMP
+5VS_PVDD_AMP

+5VS_PVDD_AMP

+5VS_PVDD_AMP

+5VS_PVDD_AMP
+5VS_PVDD_AMP

WOOFER1+
WOOFER1­WOOFER2+
WOOFER2-

1006_SPK_R-_R <36>

1006_SPKR- <36>

1006_SPK_R- <36>

1006_SPK_R+ <36>

1006_SPKR+ <36>

1006_SPK_L-_R <36>

1006_SPKL- <36>
1006_SPK_L- <36>

1006_SPK_L+ <36>

1006_SPKL+ <36>

+5VS_PVDD_AMP +5VS_PVDD_AMP

CA71

10U_0402_6.3V6M

1

2

near Pin43/44 near Pin41/42

1 2

LA11 PBY160808T-121Y-N_2PEMC@

1 2

LA12 PBY160808T-121Y-N_2PEMC@

1 2

LA13 PBY160808T-121Y-N_2PEMC@

1 2

LA14 PBY160808T-121Y-N_2PEMC@

+5VS +5VS_PVDD_AMP

1 2

JUMP_43X118

+5VS_PVDD_AMP +5VS_PVDD_AMP

CA51

1

2

near Pin43/44 near Pin41/42

I2S_MCLK_R<36>

I2S_BCLK_R<36>
I2S_LRCK_R<36>
I2S_DOUT_R<36>

I2S_DIN_R<36>

CA72

.1U_0402_16V7K

1

2

CA73

10U_0402_6.3V6M

1

2

WOOFER_1+
WOOFER_1­WOOFER_2+
WOOFER_2-

12

@

12

@

CA67680P_0402_50V7K

12

CA68680P_0402_50V7K

@

12

CA69680P_0402_50V7K

@

CA70680P_0402_50V7K

J28

@

10U_0402_6.3V6M

CA52

.1U_0402_16V7K

1

2

I2S_MCLK_R
I2S_BCLK_R
I2S_LRCK_R
I2S_DOUT_R
I2S_DIN_R I2S_DIN

CA34

22P_0402_50V8J

XEMC@

CA53

10U_0402_6.3V6M

CA54

.1U_0402_16V7K

1

1

2

2

1 2

RA32

1

2

33_0402_5%

close AMP

CA74

.1U_0402_16V7K

1

2

Subwoofer Conn.

1 2

RA65 0.1_0402_1%

1 2

RA68 0.1_0402_1%

WOOFER_1-_R
WOOFER_2-_R

JSPK3

1

1

2

2

3

5

3

G1

4

6

4

G2

CVILU_CI4304M2HR0-NH

CONN@

SP02000Y500

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Amplifier & I/O Ports

Amplifier & I/O Ports

Amplifier & I/O Ports

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

1.0

1.0

37 103Monday, January 09, 2017

37 103Monday, January 09, 2017

37 103Monday, January 09, 2017

1.0

A

B

C

D

E

Board ID

C205

+3VLP_EC

U28

1

GATEA20/G PIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME #

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPI O05

37

EC_RST#

20

EC_SCI#/G PIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CLK1/GPIO4 4

78

EC_SMB_DAT1/GPIO45

79

EC_SMB_CLK2/GPIO4 6

80

EC_SMB_DAT2/GPIO47

6

PM_SLP_S3#/GPIO04

14

GPIO07

15

GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

AC_PRESE NT/GPIO0D

25

PWM2/GPIO11

28

FAN_SPEE D1/GPIO14

29

FANFB1/GP IO15

30

EC_TX/GPIO 16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO1 8

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

PBTN_OUT#/GP IO5D

123

PM_SLP_S4#/GPIO5E

12

R192
0_0402_ 5%

@

+3VLP_LPC

LPC & MISC

Int. K/B
Matrix

+1.3 5VSD GPU

+1.0 VSDG PU

L10
FBMA-L11-1 60808-80 0LMT_0603

1 2

9

111

22

33

96

125

VCC

VCC

VCC

VCC

VCC0

VCC_LPC

PWM Output

VCIN1_BATT_TEMP/AD0/GPIO38
VCIN1_BATT_DROP/AD1/GP IO39

AD Input

DA Output

EC_MUTE#/PS CLK1/GPIO4A

PS2 Interface

SPI Device Interface

SPI Flash ROM

GPIO

SM Bus

VCIN1_ADP _PROCHOT/GP XIOA05

VCOUT1_PROCHOT#/GPXIOA06

VCOUT0_MAIN_PWR_ON/GPXIOA0 7

GPIO

GPO

PWR_VCCST_PG/GPX IOA11

GPI

GND

GND

GND

GND

GND

11

24

35

94

113

to VGA

USB_EN#/PSDAT1/GPIO 4B

SYS_PWROK/AD7/GPIO41

BATT_CHG_LED#/GPIO52

BATT_LOW_LED#/GPI O55

PCH_PWR_EN/GPXIOA10

+3VLP

JP3

2

112

JUMP_43X39

@

For Power consumption

1 1

For turn off internal LPC module of KB9032 ESPI Bus Pin : 1~5.7.8.10.12.1 4

ESPI@

ESPI@

1 2

1 2

XEMC@

ESPI_RST#

ACOK

LPC_CLK_ R

12

R199
33_0402 _5%

PLT_RST#

EC_SMB_CK1
EC_SMB_DA1

SLIDE_DET#

1 2

R196 47K_0402_5%

1 2

R197 47K_0402_5%

C208 100P_ 0402_50 V8JXEMC@

Reserved for ESD 2014/9/17

C209 100P_0402_50V8J

XEMC@

12

C210
22P_040 2_50V8J

2 2

+3VLP_EC +3VLP_EC

1 2

R203 2.2K_0402_5%

1 2

R204 2.2K_0402_5%

+3VLP_EC

1 2

R411 100K_0402_5%

PU at CPU side

for marco key 3810

+3VLP_EC

3 3

4 4

12

R426 4.7K_0402 _5%

12

R427 4.7K_0402 _5%

3VSDGPU_ EN<45>

NVVDD1_EN<41,84>
NVVDD1_EN_S<53,91>

+3VLP_EC

47K_0402_5%

12

2

1

R385

@

.1U_0402_16V7K~D

C436

@

EC_ESB_CLK
EC_ESB_DAT

EC_ESB_CLK

RST#
EC_ESB_DAT

UE5

@

1

ESB_CLK

2

GPIO00

3

RST#

4

ESB_DAT

5

GPIO01

6

GPIO02

7

GPIO03

8

GPIO04

9

GPIO05

10

GPIO06

11

GPIO07/CAS_CLK

12

GND

KC3810_QFN24_4X4

Measurement

LPC Bus Pin : 3 ~5.7.8.10.12.13

Combine w/ SMI

EYE tracker

slide module

For amp & HP

9V fan PWR

TEST_EN#

GPIO08/CAS_DAT

GPIO09
GPIO0A

GPIO0B
GPIO0C/PWM0
GPIO0D/PWM1
GPIO0E/P WM2
GPIO0F/PWM3

GPIO10/E SB_RUN#

GPIO11/B aseAddOpt

GND

25

1 2

R799 0_0402_5%@

1 2

R800 0_0402_5%@

EC_AMP_G AIN0<32>
EC_AMP_G AIN1<32>

13
14
15
16
17
18
19
20
21
22
23
24

VCC

SUSPWRDNACK<20>

SERIRQ<18,40>
LPC_FRAME #<18,40>
LPC_AD3<18,40>
LPC_AD2<18,40>
LPC_AD1<18,40>
LPC_AD0<18,40>

LPC_CLK_ R<18>
PLT_RST#<1 9,40>

EC_SCI#<22>

WLAN_P WR_EN<31>

POGO_EN<33>

POGO_FN<33>

TBT_HRESET<70>
DGPU_PW R_EN<22,41,45 ,53,57>
EC_TBT_WA KE#<68>

SLIDE_DET#<33>

HPOUT_JD<32,36>

HP_AMP_E N<32>

AMP_INIT<36 >

USBKB_EN<33>

EC_SMB_CK1<74,75>
EC_SMB_DA1<74,75>
EC_SMB_CK2<20,26,32,36 ,41,53>
EC_SMB_DA2<20,26,32,36 ,41,53>

PM_SLP_S3#<20,26>
ESPI_RST#<18>

EC_ESB_CLK<35>
EC_ESB_DAT<35>

AC_PRESE NT<20>

GPU_OVERT<41,53>
FAN_SPEE D3<39>
FAN_SPEE D2<39>

E51TXD_P8 0DATA<31>

E51RXD_P 80CLK<31 >

PCH_PWROK<20,26>

PBTN_OUT#<20>

PM_SLP_S4#<20,26,77>

LCD_OD<65 >

TOBII_EN<34>

AC_OFF2<72>
AC_OFF1<72>

AC_IN1<72 ,73>
AC_IN2<72 ,73>

SPOK<76>

TS_EN<65>

FAN_9V<78 >

VGATE<81>

W=60mils

R399 10K_0402 _5%

.1U_0402_16V7K

1

@

2

.1U_0402_16V7K

C204

1

2

SUSPWRDNACK
SERIRQ

LPC_FRAME #
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

LPC_CLK_ R
PLT_RST#
EC_RST#
EC_SCI#

EC suggest NC

EC suggest NC

DGPU_PW R_EN
EC_TBT_WA KE#

AC_OFF2
AC_OFF1
AC_IN1
AC_IN2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

PM_SLP_S3#
ESPI_RST#

SPOK
EC_ESB_CLK

EC_ESB_DAT
AC_PRESE NT

E51TXD_P8 0DATA
E51RXD_P 80CLK

VGATE

PBTN_OUT#
PM_SLP_S4#

@

+3VLP_EC

CE3

.1U_0402_16V7K

1

2

KSI4
KSI5
KSI6
KSI7

3VSDGPU_ EN_S <57>

1V8_AON_EN <45>

1V8_AON_EN_S <57 >

1.35VSDG PU_EN <41,89 >

1.35VSDG PU_EN_S <53,9 6>
EC_NVVDD_ EN <41>

EC_NVVDD_ EN_S <53>

1.0VSDGP U_EN <90>

1.0VSDGP U_EN_S <97>

12

+3VLP_ECA

+3VLP_ECA

1

C206
.1U_0402 _16V7K

2

ECAGND

67

AVCC

EC_VCCST_PG/GPIO0F

BEEP#/GPIO10

EC_FAN_PWM/GPIO12

AC_OFF/GP IO13

ADP_I/AD2 /GPIO3A

AD_BID/AD3/GPIO3B

AD4/GPIO42
AD5/GPIO43

DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

DA2/GPIO3E

DA3/GPIO3F

PSCLK2/G PIO4C
PSDAT2/GPIO4D
TP_CLK/GPIO4E

TP_DATA/GPIO 4F

ENKBL/GP XIOA00

WOL_E N/GPXIOA0 1

ME_EN/GPXIOA02

VCIN0_PH1 /GPXIOD00

MISO/GPIO 5B

MOSI/GPIO 5C

SPICLK/GPIO58

SPICS#/GPIO5A

EC_CIR_RX/AD6/GPIO4 0

GPIO50

CAPS_LED#/GPIO53

PWR_LE D#/GPIO54

SYSON/GPIO56
VR_ON/GPIO57

DPWROK_EC/GPIO5 9

EC_RSMRST#/GPXIOA03

GPXIOA04

BKOFF#/GPXIOA08

GPXIOA09

VCIN1_AC_ IN/GPXIOD0 1

EC_ON/GPXIOD02
ON/OFF#/GPXIOD03
LID_SW #/GPXIOD0 4

SUSP#/GP XIOD05

GPXIOD06

PECI/GPXIOD07

V18R/VCC_ IO2

AGND

KB9022Q D_LQFP12 8_14X14

69

20mil

BATT_TEMP

1 2

C212

100P_04 02_50V8 J

ECAGND

L11

FBMA-L11-1 60808-80 0LMT_0603

ECAGND <74>

21
23

BEEP#

26
27

BATT_TEMP

63

PD_IRQ#

64

ADP_I

65

AD_BID

66

WLAN_P ME#

75

EC_PME#

76

LAN_PW R_EN

68

USB_CB

70

EN_DFAN

71

EC_TBTA_RESET

72

EC_MUTE#

83

USB_EN

84

EC_SMB_CK3

85

EC_SMB_DA3

86

USB_CEN

87

WL_OFF#

88

97

VR_ON

98

ME_EN

99

VCIN0_PH

109

USB_SELCDP

119

EC_RSMRST#

120

DGPU_PW R_LEVEL

126

EC_VCCST_PG_R

128

73

SYS_PWROK_R

74

BATT_4S

89
90
91
92
93
95

SYSON

121

USB_CHARG E_2A

127

100
101

VCIN1_ADP _PROCHOT

102

VCOUT1_PROCHOT#

103
104

MAINPWO N

105

BKOFF#

106

3V_EN_R

107
108

110

EC_ONPCH_PWROK

112
114

ON/OFFBTN#

LID_SW #

115
116

SUSP#

GPU_ALERT

117

EC_PECI

118
124

12

EC_FAN_PWM1 <39>

BEEP# <36>

EC_FAN_PWM3 <39>
EC_FAN_PWM2 <39>

BATT_TEMP <74 ,75>

PD_IRQ# <70>

ADP_I <74,75>
WLAN_P ME# <31>

EC_PME# <19,30>EC_RST#<40>

LAN_PW R_EN <30>
USB_CB <32>

EN_DFAN <3 9>

EC_TBTA_RESET <7 0>
EC_MUTE# <32,36>

USB_EN <32>
EC_SMB_CK3 <32,35,7 0>
EC_SMB_DA3 <32,35,7 0>

USB_CEN <32>

WL_OFF# <31>

DGPU_ENBKL <41>
VR_ON <26,80,81>
ME_EN <20>
VCIN0_PH <7 4>

USB_SELCDP <32>

EC_RSMRST# <6,20>
DGPU_PW R_LEVEL <22,4 1,53>
EC_VCCST_PG_R <9,26>

FAN_SPEE D5 <39>
BATT_4S <75>

LEDPWR_EN <32>

CAM_EN <65>

DDR_ALERT <75,77>

STORAGE_LED# <28>

SYSON <25,26 ,77,78>

LBPWR_ EN <35>

USB_CHARG E_2A <32>

FAN_SPEE D1 <39>

FAN_SPEE D4 <39>

VCIN1_ADP _PROCHOT <74>

MAINPWO N <40 ,74,76>

BKOFF# <65>

FAN_EN <78>

BT_ON <31>

ACOK <72,75>

EC_ON <76>

ON/OFFBTN# <35,40>
LID_SW # <35>
SUSP# <25,26,28,3 2,68,75,77,79,80>

GPU_ALERT <41,53>

1 2

R208 33_0402_1%

remove LAN GPO
remove EC_KBRST#, 3/22
remove DCHG_I, 3/10
remove VCIN1_BATT_DROP, 3/9
remove EC_LID_OUT#
remove KBL_EN

checked with EC 0226

for TBT

add EN_DFAN 0307

for TBT

change to DGPU out

check with pwr for remove

For LED/Logo

12V fan PWR

for DVT 7/11

H_PECI <9,19>

+3VLP_EC

EC_SMB_CK3
EC_SMB_DA3

SYS_PWROK_R

R201 0 _0402_5 %

Reserved Only

For abnormal shutdown

SPOK

For Thermal Portect Shutdown

D15
RB751V-40_SOD323 -2

1 2

MAINPWO N

1

C211

.1U_0402 _16V7K

H_PROCHOT#<9,75>

XEMC@

2

R212 0_0402_5%@

R213 0_0402_5%@

3V_EN_R

1 2

1 2

R209

1 2

1K_0402 _5%

+3VLP_EC

Ra

1 2
12

Rb

Analog Board ID definition,
P

lease see page 3.

USB_CB

R198 4.7K_0402_5%

1 2

@

LID_SW #

1 2

R207 100K_0402_1%

EC_PME#

PD_IRQ#

PD_IRQ#
GPU_ALERT
GPU_OVERT

1 2

R417 10K_0402_5%TBT@

1 2

R371 10K_0402_5%@

1 2

R205 10K_0402_5%

1 2

R206 10K_0402_5%

@

1 2

D16 RB751V-40_SOD323-2

1 2

D17 RB751V-40_SOD323-2

1 2

D18 RB751V-40_SOD323-2

R210
1M_0402_5%

VR_HOT#

VCOUT1_PROCHOT#H_PROCHOT#

R191
100K_04 02_1%

AD_BID

R193
20K_040 2_1%

@

12

12

@

EC_VCCST_PG_R

1 2

1

C207
.1U_0402 _16V7K

2

@

+5VALW

12

R4294.7K_0 402_5%

12

R4284.7K_0 402_5%

SYS_PWROK <20,26>

R19447K_0 402_5%

+3VS

EC_RSMRST#

PCH_PWROK

3V_EN <76>

VR_HOT# <81>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

A

B

C

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

EC ENE-KB9022

EC ENE-KB9022

EC ENE-KB9022

Size

Document Number Re v

Size

Document Number Re v

Size

Document Number Re v

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet of

Date: Sheet of

Date: Sheet of

E

38 103Monday, January 09, 2017

38 103Monday, January 09, 2017

38 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

FAN Control circuit-1 (Lef t) FAN Control circuit-2 (Right)

2

1

R353 0_0603_5%@

+12VS

D D

FAN_SPEED3<38>

EC_FAN_PWM3<38>

12

+VCC_FAN3

+3VS

12

R216
10K_0402_5%

1

C221
1000P_0402_50V7K

XEMC@

2

40mil

+VCC_FAN3

C217

4.7U_0603_25V6K

1 2

C218

@

1000P_0402_50V7K

1 2

JFAN3

1

1

2

2

3

3

4

4

5

G1

6

G2

ACES_50278-00401-001

CONN@

SP02000RR00

R358 0_0603_5%@

+12VS

FAN_SPEED2<38>

EC_FAN_PWM2<38>

12

FAN Control circuit-3 (Center) FAN Control circuit-4/5 (lower)

C C

R355 0_0603_5%@

+5VS

FAN_SPEED1<38>

EC_FAN_PWM1<38>

B B

12

+VCC_FAN1

+3VS

12

R356
10K_0402_5%

1

C401
1000P_0402_50V7K

XEMC@

2

check fan speed & PWM need PH?
level shift?

40mil

+VCC_FAN1

C405

4.7U_0603_25V6K

1 2

C404

@

1000P_0402_50V7K

1 2

JFAN1

1

1

2

2

3

3

4

4

5

G5

6

G6

ACES_50273-0040N-001

CONN@

SP02000TI00

+5VS

C213

4.7U_0603_6.3V6K

1 2

U29

1

EN

2

+VCC_FAN4

EN_DFAN<38>

EN_DFAN

+VCC_FAN5
EN_DFAN

R373
0_0402_5%

@

R214
0_0402_5%

+5VS

12

@

12

1 2

1

2

3
4

1

C215
.1U_0402_16V7K

2

@

C431

4.7U_0603_6.3V6K

U46

1

EN

2

VIN

3

VOUT

4

VSET

NCT3942S SOP 8P

C432
.1U_0402_16V7K

@

VIN
VOUT
VSET

NCT3942S SOP 8P

+3VS

12

R217
10K_0402_5%

1

C222
1000P_0402_50V7K

XEMC@

2

GND
GND
GND
GND

8

GND

7

GND

6

GND

5

GND

+VCC_FAN2

8
7
6
5

40mil

+VCC_FAN2

FAN_SPEED4<38>

FAN_SPEED5<38>

C219

4.7U_0603_25V6K

1 2

C220

@

1000P_0402_50V7K

1 2

+3VS

12

1

2

JFAN2

1

1

2

2

3

3

4

4

5

G1

6

G2

ACES_50278-00401-001

CONN@

SP02000RR00

+3VS

12

R354
10K_0402_5%

R374 0_0402_5%@

1

C406
1000P_0402_50V7K

XEMC@

2

R376
10K_0402_5%

+VCC_FAN5

R375 0_0402_5%@

C433
1000P_0402_50V7K

XEMC@

40mil

+VCC_FAN4

12

40mil

12

C403

4.7U_0603_6.3V6K

1 2

C402

@

1000P_0402_50V7K

1 2

C430

4.7U_0603_6.3V6K

1 2

C429

@

1000P_0402_50V7K

1 2

JFAN4

1

1

2

4

2

GND

3

5

3

GND

JXT_WB201H-003G10M

CONN@

SP020019O00

JFAN5

1

1

2

4

2

GND

3

5

3

GND

JXT_WB201H-003G10M

CONN@

SP020019O00

Screw Hole

H21

H27

H23

H28

H5

H_3P0

H_3P0

H_3P7

H_3P0

H_3P0

1

1

1

@

@

@

H11

H15

H17

H_3P7

H_3P7

H_3P7

1

1

1

@

@

@

H_3P0

1

@

H10

H_3P7

A A

1

@

H1

H25

H_3P0

1

@

H13

H_3P7

1

@

5

H12

H_3P0

1

@

H14

H_3P7

1

@

H26

H_3P0

H_3P0

1

1

1

@

@

@

H6

H8

H7

H_3P7

H_3P7

H_3P7

1

1

1

@

@

@

H34

H33

H_3P0

H_3P0

1

1

@

@

H9

H16

H18

H_3P7

H_3P7

1

1

1

@

@

@

H_3P3

H_3P8

H20

H22

H24

H_3P3

1

@

H2

H_3P8

1

@

H29

H_3P3

H_3P3

1

1

1

@

@

@

H4

H3

H19

H_3P8

H_3P8

1

1

1

@

@

@

4

H31

H30

H_3P0X3P5N

H_3P0X3P5N

@

@

1

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

1

Issued Date

Issued Date

Issued Date

H32

H_3P0N

@

3

1

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

FD1

@

1

FIDUCIAL_C40M80

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

FD2

@

1

FIDUCIAL_C40M80

FIDUCIAL_C40M80

2

FD3

@

1

FD4

@

1

FIDUCIAL_C40M80

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

FAN CTRL & Screw Hole

FAN CTRL & Screw Hole

FAN CTRL & Screw Hole
C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

1.0

1.0

39 103Monday, January 09, 2017

39 103Monday, January 09, 2017

39 103Monday, January 09, 2017

1.0

TPM Board for 2016 Reset Circuit

+3VALW +3VALW_TPM +3VS +3VS_TPM

1 2

R218
0_0603_5%

TPM@

10U_0603_6.3V6M

1

2

TPM@

GPIO3/BADD with Internal PH (default)

CLKRUN PH 10K to +3VS at PCH side

LPCPD# had internal PH

SERIRQ PH 10K to +3VS at PCH side

*

BADD

0

1

SELECTION

EEh - EFh

7Eh - 7Fh

reserve G-Sensor

+3VLP

1 2

.1U_0402_16V7K

C223

C224

1

near pin5

2

TPM@

1 2

R2200_0402_5% @

LPC_AD0<18,38>
LPC_AD1<18,38>
LPC_AD2<18,38>
LPC_AD3<18,38>

CK_LPC_TPM<18>
LPC_FRAME#<18,38>

PLT_RST#<19,38>

SERIRQ<18,38>

PM_CLKRUN#<20>

CK_LPC_TPM

R219

0_0603_5%

TPM@

29

1 2

XEMC@

30

24
21
18
15

19
20
17
27
13
28

TPM_BADD

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

CK_LPC_TPM
LPC_FRAME#
PLT_RST#

SERIRQ

PM_CLKRUN#

R221 33_0402_5%

10U_0603_6.3V6M

C225

1

1

2

2

TPM@

U31

TPM@

XOR_OUT/SDA/GPIO0
SCL/GPIO1

3

GPX/GPIO2

6

GPIO3/BADD
LAD0/MISO

LAD1/MOSI
LAD2/SPI_IRQ#
LAD3

LCLK/SCLK
LFRAME#/SCS#
LRESET#/SPI_RST#/SRESET#
SERIRQ
CLKRUN#/GPIO4/SINT#
LPCPD#

4

PP

5

TEST

NPCT650LA0YX_QFN32_5X5

Change PN to SA00009QQ 00

1 2

C229 22P_0402_50V8J

XEMC@

C227

.1U_0402_16V7K

C226

.1U_0402_16V7K

1

2

TPM@

TPM@

near pin10, 19, 24

VSB

VDD1
VDD2
VDD3

NC1
NC2
NC3
NC4
NC5
NC6
NC7

GND1
GND2
GND3
GND4
PGND

Reserved

C228

.1U_0402_16V7K

1

2

TPM@

BI_GATE PH to +RTCVCC at PWR side

BI_GATE<74>

1
8

14
22

2
7
10
11
25
26
31

9
16
23
32
33
12

+3VALW_TPM
+3VS_TPM

BI SW

BI_GATE

DMN66D0LDW-7_SOT363-6

Q18A

G

5

R224
10K_0402_5%

1 2

BI_GATE#

2

34

1

D

S

C230
.1U_0402_16V7K

2

BI SW (Bot) BI SW (Top)

SWG1

BI_S1<32>

1 2

SKPMAME010_2P

BI_S <74>

move to pwr/b

1 2

@

R222 0_0402_5%

1 2

@

R223 0_0402_5%

61

D

G

S

Q18B
DMN66D0LDW-7_SOT363-6

MAINPWON <38,74,76>

EC_RST# <38>

Reset BTN

SW5

1 2

SKPMAME010_2P

BI_GATE

H : 3.8mm

Release : Bat t er y Off
P

ush : Bat t er y ON

+3VS

PCH_SMBCLK_R<14,15,16,17,20>
PCH_SMBDATA_R<14,15,16,17,20>

1 2

R230 10K_0402_5%@

1 2

R231 10K_0402_5%GSEN@

+3VS

12

R229
10K_0402_5%

U32

GSEN@

8

CS

4

SCLSPC

6

SDA/SDI/SDO

7

SDO/SA0

16

ADC1

15

ADC2

13

ADC3

2

NC

3

NC

LIS3DHTR_LGA16_3X3

GSEN@

LIS3 DH
SA0 ->0, Address is 0011 000 (0x30h)
SA0 ->1, Address is 0011 001 (0x32h)

Vdd_IO

INT1
INT2

RES

GND
GND

Vdd

+3VS

1
14

11
9

10

5
12

C231 10U_0603_6.3V6M
C232 .1U_0402_16V7K

G_INT#
G_INT2

INT1/2 all High Active

1 2
1 2

G_INT# <22>
G_INT2 <27>

GSEN@
GSEN@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

ON/OFF BTN

+3VLP

ON/OFFBTN#<35,38>

Test Only

BOT

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

R225
100K_0402_5%

12

SW2

@

EVQPLDA15_4P

1
2

Compal Secret Data

Compal Secret Data

Compal Secret Data

3
4

5

6

Deciphered Date

Deciphered Date

Deciphered Date

ON/OFFBTN#

Move Lid Switch to JPWR

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

BTN/LID/G-Sensor/TPM

BTN/LID/G-Sensor/TPM

BTN/LID/G-Sensor/TPM

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

40 103Monday, January 09, 2017

40 103Monday, January 09, 2017

40 103Monday, January 09, 2017

1.0

1.0

1.0

5

+1.8VSDG PU_AON

1

CG1

1 2

RG3
10K_02 01_5%

SYS_PEX _RST_MON#

GPU_PEX _RST_HOL D#

+1.8VSDG PU_AON

12

61

G

2

DGPU_PE X_RST#_ G

2

G

QG501B

61

PJT138 KA 2N SOT3 63-6

S

D

UG9W

BG5

BF12

BJ1
BJ2

BK24

BL23
BM23
BM24

BL24

BK23

5

DGPU_HOL D_RST#
PLT_RS T_BUF#

+1.8VSDG PU_MAIN

DGPU_PE X_RST#

RG516
10K_02 01_5%

D

QG502B

S

PJT138 KA 2N SOT3 63-6

5

34

SGD

13/23 MISC 1

OVERT

TS_VREF

THERMDN
THERMDP

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST*

NVJTAG_SEL

DGPU_PE X_RST#

QG501A
PJT138 KA 2N SOT3 63-6

GPU_OVE RT_M

DGPU_HOL D_RST#<22>

PLT_RS T_BUF#<19,28 ,29,30,31,3 2,53,68>

UG9

MASTER

D D

S IC N17E-G3-A1/8GB BGA 2152 GPU ABO !

SA0000 9PS20

SLAVE

UG25

S IC N17E-G3-A1/8GB BGA 2152 GPU ABO !

SA0000 9PS20

C C

DGPU_GC 6_FB_EN

ALERT_ R

OVERT

B B

OVERT

JTAG_T CLK

T59 PAD~D@

JTAG_T MS

T60 PAD~D@

JTAG_T DI

T61 PAD~D@

JTAG_T DO

T62 PAD~D@

JTAG_T RST#

1 2

RG518
10K_02 01_5%

A A

12

RG26
10K_02 01_5%

5

1

IN B

VCC
OUT Y

2

IN A

GND

NL17SZ0 8DFT2G_ SC70-5

3

10K_02 01_5%

DG1

2

3

BAT54A W-L_SOT 323-3

@

+1.8VSDG PU_AON

5

1

IN B

VCC
OUT Y

2

IN A

GND

NL17SZ0 8DFT2G_ SC70-5

3

I2CS_SCL
I2CS_SDA

I2CC_SCL
I2CC_SDA

I2CB_SCL
I2CB_SDA

N17E-G1_ BGA2152 ~D@

0.1U_020 1_6.3V6K

2

UG10

4

+3VSDGP U

12

RG6

@

1

1

CG916

0.1U_020 1_6.3V6K

2

UG101

4

+1.8VSDG PU_AON

5

1

IN B

VCC

OUT Y

2

IN A

GND

NL17SZ0 8DFT2G_ SC70-5

3

GPU_ALE RT <38,53>

BJ8
BH8

BG9
BH9

BG8
BF8

BD6

GPIO0

BB5

GPIO1

BD1

GPIO2

BE4

GPIO3

BE1

GPIO4

BG2

GPIO5

BD2

GPIO6

BD7

GPIO7

BH4

GPIO8

BJ3

GPIO9

BD3

GPIO10

BH3

GPIO11

BE6

GPIO12

BB1

GPIO13

BG4

GPIO14

BG1

GPIO15

BE2

GPIO16

BH1

GPIO17

BE3

GPIO18

BD4

GPIO19

BE5

GPIO20

BA5

GPIO21

BB6

GPIO22

BG3

GPIO23

BD5

GPIO24

BB2

GPIO25

BE7

GPIO26

BA4

GPIO27

BB4

GPIO28

BA3

GPIO29

BB3

GPIO30

BA2

GPIO31

BA1

GPIO32

DGPU_RS T#

12

RG7
0_0201 _5%

DGPU_PE X_RST#

1

CG917
.1U_0402 _16V7K

2

1

CG918
.1U_0402 _16V7K

2

GPU_OVE RT<38,5 3>

1

CG246

0.1U_020 1_6.3V6K

2

UG22

4

VGA_SMB _CK2
VGA_SMB _DA2

I2CC_S CL_R
I2CC_S DA_R

1 2

RG19 1.8K_0 402_5%

1 2

RG20 1.8K_0 402_5%

DGPU_GC 6_FB_EN
GPU_EVE NT#_D

FRAME_L OCK#
NVVDD_P SI
GPU_INV_ PWM

ALERT

GPIO12

GPU_ENBK L

SYS_PEX _RST_MON#
DGPU_ED P_HPD#

Master_SLI _RASTER _SYNCO
Master_SLI _SWAPR DY_IN
GPU_PEX _RST_HOL D#

1 2

@

RG705 0_02 01_5%

@

1V8_MAI N_EN

DGPU_PE X_RST#_ G <66 >

@

DG23
RB751S 40T1G_S OD523-2

NVVDD_V ID <84 >

NVVDDS_ VID <8 7>
1V8_MAI N_EN <45>

NVVDD_P SI <84,87 >

MEM_VREF <49 ,50,51,52>
DGPU_ENV DD < 65>

GPU_OVE RT_M

12

+1.8VSDG PU_AON

DP0_HPD _GPU# <6 8>

DGPU_ED P_HPD# <65>
DGPU_DP 4_HPD# <67>

DGPU_DP 5_HPD# <67>

DGPU_HDMI_ HPD# <6 6>

OC_WA RN# <45>

4

SYS_PEX _RST_MON#

1 2

RG787 0_040 2_5%

+3VS

RG795
10K_04 02_5%

1 2

1 2

DG13
RB751S 40T1G_S OD523-2

34

D

G

5

QG502A

S

PJT138 KA 2N SOT3 63-6

DGPU_PE X_RST#_ G

VGA_SMB _CK2

2

G

VGA_SMB _DA2

S

D

+1.8VSDG PU_AON

12

RG11

RG12

1.8K_0402_1%

1.8K_0402_1%

I2CC_S CL_R

I2CC_S DA_R

12

DG2
RB751S 40T1G_S OD523-2

20160201_Update Net Name

+1.8VSDG PU_AON

12

RG690
1K_040 2_5%

12

4

2

CG911

@

.1U_0402 _16V7K

1

EC_NVVD D_EN<38>

NVVDD_E N

RG768 15K_040 2_1%

+1.8VSDG PU_AON

12

RG506
10K_02 01_5%

@

DG4
RB751S 40T1G_S OD523-2

5

QG6A
PJT138 KA 2N SOT3 63-6

34

SGD

QG6B

61

PJT138 KA 2N SOT3 63-6

DGPU_PE X_RST#_ G

12

5

QG7A
PJT138 KA 2N SOT3 63-6

34

SGD

2

G

QG7B

61

PJT138 KA 2N SOT3 63-6

S

D

GPU_EVE NT# <22>

1/28 SLI GPIO connection with NV confirmed

RG688
0_0402 _5%

1 2

RG689
100K_0 402_5%

Slave_SLI _RASTER _SYNC0 <53>

Master_SLI _SWAPR DY_IN <5 3>

+3VSDGP U

12

RG771

4.7K_04 02_1%

@

DG14

RB751S 40T1G_S OD523-2

12

12

RG767 20K_040 2_1%

DG6
RB751S 40T1G_S OD523-2

1 2

12

12

EC_SMB_ CK2 <20,26,32 ,36,38,53>

EC_SMB_ DA2 <20,26,32 ,36,38,53>

+3VS

1

CG910

0.1U_020 1_6.3V6K

2

5

1

P

B

4

O

2

A

G

UG99

@

3

TC7SH08 FU_SSOP5 ~D

NVVDD1_ EN <38,84 >

Placed n eer PQ1201

2

CG906
.1U_0402 _16V7K

1

NVVDD2_ EN_R1

1 2

RG789 0_04 02_5%

Placed neer PU1401

2

CG907

0.22U_04 02_16V7 K

1

NVVDD1_ PGOOD <8 4,87,90>
NVVDD2_ PGOOD <8 7,90>

I2CC_S CL <45>

I2CC_S DA <45>

ALERT_ R

PEG_CL KREQ#<21>

@

NVVDD_E N

@

DGPU_PW R_EN<22 ,38,45,53,5 7>

1 2

@

RG695 0_02 01_5%

PJT138 KA 2N SOT3 63-6

NVVDD2_ EN <87,90 >

NVVDD2_ EN_R1

FRAME_L OCK#

RB751S 40T1G_S OD523-2

GPIO12

RB751S 40T1G_S OD523-2

GPU_EVE NT#_D

OVERT
DGPU_HOL D_RST#

GPU_PEX _RST_HOL D#

GPIO12
VGA_SMB _CK2

VGA_SMB _DA2
SYS_PEX _RST_MON#
NVVDD_P SI

ALERT

OC_WA RN#

DGPU_GC 6_FB_EN
MEM_VREF
DGPU_PE X_RST#
GPU_INV_ PWM
DGPU_ENV DD
GPU_ENBK L

+1.8VSDG PU_MAIN

RG1
10K_02 01_5%

1 2
5

3 4

SGD

QG5A

+1.8VSDG PU_AON

1

IN B

2

IN A

+1.8VSDG PU_AON

RG502

10K_02 01_5%

DG17

DG18

RG8 10K_02 01_5%
RG9 10K_02 01_5%
RG13 10K_ 0201_5%@
RG14 10K_ 0201_5%
RG16 100K _0201_5 %
RG17 1.8K_0 402_5%
RG18 1.8K_0 402_5%
RG21 10K_ 0201_5%
RG15 10K_ 0201_5%

RG504 10 K_0201_ 5%
RG692 10 K_0201_ 5%

RG22 10K_ 0201_5%
RG24 100K _0201_5 %
RG25 1M_020 1_1%
RG150 10 0K_0201 _5%
RG151 10 0K_0201 _5%
RG501 10 0K_0201 _5%

3

+1.8VSDG PU_AON

RG2
10K_02 01_5%

1 2

5

U69

NVVDD2_ EN_1 NVVDD2 _EN

VCC

4

OUT Y
GND

NL17SZ0 8DFT2G_ SC70-5

3

DGPU_ENV DD

12

G

S

QG523

MESS138 W-G_SOT 323-3

12

12

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2

3

2

NV KEN: connect to 3.3V will have sequence issue, recommand use 1.8V

RG4 0 _0402_ 5%

+1.8VSDG PU_AON

12

RG805
10K_02 01_5%

1 2

DGPU_GC 6_FB_EN

DGPU_PE X_RST#_ R

G-SYNC# <65>

DGPU_PE X_RST#

PCIE_C RX_C_GT X_P0<8>
PCIE_C RX_C_GT X_N0<8>

PCIE_C TX_C_GR X_P0<8>
PCIE_C TX_C_GR X_N0<8>

PCIE_C RX_C_GT X_P1<8>
PCIE_C RX_C_GT X_N1<8>

PCIE_C TX_C_GR X_P1<8>
PCIE_C TX_C_GR X_N1<8>

PCIE_C RX_C_GT X_P2<8>
PCIE_C RX_C_GT X_N2<8>

PCIE_C TX_C_GR X_P2<8>
PCIE_C TX_C_GR X_N2<8>

PCIE_C RX_C_GT X_P3<8>
PCIE_C RX_C_GT X_N3<8>

PCIE_C TX_C_GR X_P3<8>
PCIE_C TX_C_GR X_N3<8>

PCIE_C RX_C_GT X_P4<8>
PCIE_C RX_C_GT X_N4<8>

PCIE_C TX_C_GR X_P4<8>
PCIE_C TX_C_GR X_N4<8>

PCIE_C RX_C_GT X_P5<8>
PCIE_C RX_C_GT X_N5<8>

PCIE_C TX_C_GR X_P5<8>
PCIE_C TX_C_GR X_N5<8>

PCIE_C RX_C_GT X_P6<8>
PCIE_C RX_C_GT X_N6<8>

PCIE_C TX_C_GR X_P6<8>
PCIE_C TX_C_GR X_N6<8>

PCIE_C RX_C_GT X_P7<8>
PCIE_C RX_C_GT X_N7<8>

PCIE_C TX_C_GR X_P7<8>
PCIE_C TX_C_GR X_N7<8>

1 2

RG792 0_040 2_5%

+3VS

12

RG517
10K_02 01_5%

@

123

D

VGA_One Shot <53,72>

DGPU_PW R_LEVE L <22,38,5 3>

+1.8VSDG PU_AON

DGPU_PE G_CLKRE Q#

CLK_PE G_GPU_P0<21>
CLK_PE G_GPU_N0<21>

+3VS

G

5

UG9A

BK26

BL26

BM26
BM27

BG26
BH26

BL27

BK27

BF26

BE26
BK29

BL29
BF27

BG27
BM29

BM30
BG29

BH29

BL30

BK30

BF29

BE29
BK32

BL32
BF30

BG30
BM32

BM33
BG32

BH32

BL33

BK33

BF32

BE32
BK35

BL35
BF33

BG33
BM35

BM36
BG35

BH35

BL36

BK36

BF35

BE35
BK38

BL38
BF36

BG36
BM38

BM39
BG38

BH38

BL39

BK39

BF38

BE38
BK41

BL41
BF39

BG39
BM41

BM42
BH41

BG41

BL42

BK42

+1.0VS_V GA_PGOO D<90>

12

RG773
100K_0 201_5%

GC6_FB _EN#

34

D

QG524A

S

PJT138 KA 2N SOT3 63-6

1/23 PCI_EXPRESS

PEX_RS T*
PEX_CLKREQ*
PEX_REFCLK

PEX_REFCLK*
PEX_TX0

PEX_TX0*
PEX_RX0

PEX_RX0*
PEX_TX1

PEX_TX1*
PEX_RX1

PEX_RX1*
PEX_TX2

PEX_TX2*
PEX_RX2

PEX_RX2*
PEX_TX3

PEX_TX3*
PEX_RX3

PEX_RX3*
PEX_TX4

PEX_TX4*
PEX_RX4

PEX_RX4*
PEX_TX5

PEX_TX5*
PEX_RX5

PEX_RX5*
PEX_TX6

PEX_TX6*
PEX_RX6

PEX_RX6*
PEX_TX7

PEX_TX7*
PEX_RX7

PEX_RX7*
PEX_TX8

PEX_TX8*
PEX_RX8

PEX_RX8*
PEX_TX9

PEX_TX9*
PEX_RX9

PEX_RX9*
PEX_TX10

PEX_TX10*
PEX_RX10

PEX_RX10*
PEX_TX11

PEX_TX11*
PEX_RX11

PEX_RX11*
PEX_TX12

PEX_TX12*
PEX_RX12

PEX_RX12*
PEX_TX13

PEX_TX13*
PEX_RX13

PEX_RX13*
PEX_TX14

PEX_TX14*
PEX_RX14

PEX_RX14*
PEX_TX15

PEX_TX15*
PEX_RX15

PEX_RX15*

2

BB33

PEX_DVDD_1

BB35

PEX_DVDD_2

BB36

PEX_DVDD_3

BC33

PEX_DVDD_4

BC35

PEX_DVDD_5

BC36

PEX_DVDD_6

BD33

PEX_DVDD_7

BD36

PEX_DVDD_8

Under GPU

BB26

PEX_HVDD_1

BB27

PEX_HVDD_2

BB29

PEX_HVDD_3

BB32

PEX_HVDD_4

BC26

PEX_HVDD_5

BC27

PEX_HVDD_6

BC29

PEX_HVDD_7

BC30

PEX_HVDD_8

BC32

PEX_HVDD_9

BD27

PEX_HVDD_10

BD30

PEX_HVDD_11

PEX_PLL_HVDD

PEX_TERMP

N17E-G1_ BGA2152 ~D@

3
2

DAN202UT 106_SC7 0-3

+3VS

12

RG774
10K_02 01_5%

61

D

G

QG524B

S

PJT138 KA 2N SOT3 63-6

DG5

GPU_GC6 _FB_EN <22>

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

2

BB30

BL44

1

Under GPU

+PEX_PLL_HVDD

1

2

PEX_TE RMP

12

RG10
100K_0 201_5%

1

1

1

CG2

CG13

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CG17

CG23

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CG34

CG570

2

0.1U_0201_6.3V6K

4.7U_0603_6.3V6K

12

RG23

2.49K_0 402_1%

1.35VSD GPU_EN <3 8,89>

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

1

CG3

CG4

2

2

1U_0402_6.3V6K

1

1

CG18

CG19

2

2

1U_0402_6.3V6K

1 2

1

1

CG571

CG572

2

2

1U_0402_6.3V6K

4.7U_0603_6.3V6K

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1

CG5

2

1U_0402_6.3V6K

4.7U_0603_6.3V6K

1

CG20

2

1U_0402_6.3V6K

4.7U_0603_6.3V6K

LG1
PBY1608 08T-301Y-N

1

CG14

2

4.7U_0603_6.3V6K

1

CG11

2

4.7U_0603_6.3V6K

+1.8VSDG PU_MAIN

GPU_ENBK L

GPU_INV_ PWM

1

22uF 10uF 4.7uF 1uF 0.1uF

+1.0VSDG PU

PEX_DVDD

2

2

1

PEX_HVDD

CG6

CG871

CG7

1

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

+1.8VSDG PU_MAIN

2

2

12

CG12

CG21

1

CG24

1

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

+3VS

12

RG794
100K_0 201_5%

GPU_ENBK L#

34

D

G

5

QG526A

S

PJT138 KA 2N SOT3 63-6

+1.8VSDG PU_AON

5

U65

1

P

NC

Y

2

A

G

NL17SZ0 7DFT2G_ SC70-5

3

SA0000 4BV00

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1 1 2

1 2

+3VS

12

RG704
10K_02 01_5%

61

D

G

2

QG526B

S

PJT138 KA 2N SOT3 63-6

PU at CONN side.

4

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

N17E-G1(1/6) PCIE,GPIO-M

N17E-G1(1/6) PCIE,GPIO-M

N17E-G1(1/6) PCIE,GPIO-M

Document Number Rev

Document Number Rev

Document Number Rev

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

DGPU_ENB KL <38>

DGPU_INV _PWM <65>

41 103Mond ay, January 09, 2017

41 103Mond ay, January 09, 2017

41 103Mond ay, January 09, 2017

4

42

1.0

1.0

1.0

5

UG9N

7/23 IFPAB

RG679
1K_0402_1%

IFPAB_RSET

12

D D

+IFPX_PLLVDD

1

CG568

2

BD23

IFPAB_RSET

BD21

IFPAB_PLLVDD

.1U_0402_16V7K

4

DL-DVI

SDA

SDA

SCL

SCL

TXC

TXC

TXC

TXC

TXD0

TXD0

TXD0

TXD0

TXD1

TXD1

TXD1

TXD1

TXD2

TXD2

TXD2

TXD2

DPDVI/HDM I

IFPA_AUX_SDA*

IFPA_AUX_SCL

IFPA_L3*

IFPA_L3

IFPA_L2*

IFPA_L2

IFPA_L1*

IFPA_L1

IFPA_L0*

IFPA_L0

BH11
BG11

BF21
BG21

BG23
BH23

BF23
BE23

BF24
BG24

3

TBT_DP0_AUXN <68>
TBT_DP0_AUXP <68>

TBT_DP0_N3 <68>
TBT_DP0_P3 <68>

TBT_DP0_N2 <68>
TBT_DP0_P2 <68>

TBT_DP0_N1 <68>
TBT_DP0_P1 <68>

TBT_DP0_N0 <68>
TBT_DP0_P0 <68>

Type-C DP

2

1

Under GPU

+1.0VSDGPU

1

1

CG566

2

4.7U_0402_6.3V6M

C C

1

CG567

2

CG565

2

1U_0402_6.3V6K

.1U_0402_16V7K

BB17

IFP_IOVDD_2

BB15

IFP_IOVDD_1

BB18

IFP_IOVDD_3

BB20

1

CG562

2

.1U_0402_16V7K

IFP_IOVDD_4

IFPAB

Under GPU

B B

SDA

IFPB_AUX_SDA*

SCL

IFPB_AUX_SCL

TXC
TXC

TXD0

TXD3

TXD0

TXD3

TXD1

TXD4

TXD1

TXD4

TXD2

TXD5

TXD2

TXD5

N17E-G1_BGA2152~D@

IFPB_L3*

IFPB_L3

IFPB_L2*

IFPB_L2

IFPB_L1*

IFPB_L1

IFPB_L0*

IFPB_L0

BG12
BH12

BL18
BK18

BK20
BL20

BM20
BM21

BL21
BK21

+1.8VSDGPU_MAIN

1 2

LG5
PBY160808T-300Y-N_2P

+1.0VSDGPU

+1.0VSDGPU

Under GPU

RG38
1K_0402_1%

IFPEF_RSET

12

+IFPX_PLLVDD

Under GPU

12

CG247

22U_0603_6.3V6M

1

CG43

2

IFPx_IOVDD

IFPx_PLLVDD

UG9O

6/23 IFPF

BC21

IFP_IOVDD_11

BC23

1

CG40

2

1

2

1

2

4.7U_0402_6.3V6M

IFP_IOVDD_12

.1U_0402_16V7K

IFPF

UG9P

10/23 IFPE

BD17

IFPEF_RSET

BD15

IFPEF_PLLVDD

CG49

CG51

IFPE

.1U_0402_16V7K

BC18

IFP_IOVDD_9

BC20

IFP_IOVDD_10

.1U_0402_16V7K

22uF 10uF 4.7uF 1uF 0.1uF

3

1

IFPF_AUX_SDA*

N17E-G1_BGA2152~D@

N17E-G1_BGA2152~D@

DP

IFPF_AUX_SCL

IFPF_L3*

IFPF_L3

IFPF_L2*

IFPF_L2

IFPF_L1*

IFPF_L1

IFPF_L0*

IFPF_L0

DP

IFPE_AUX_SDA*

IFPE_AUX_SCL

IFPE_L3*

IFPE_L3

IFPE_L2*

IFPE_L2

IFPE_L1*

IFPE_L1

IFPE_L0*

IFPE_L0

BM9
BM8

BK11
BL11

BM11
BM12

BL12
BK12

BK14
BL14

BL8
BK8

BG14
BH14

BF14
BE14

BF15
BG15

BG17
BH17

DVI/HDMI

DVI/HDMI

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

6

1

2

DP5_AUXN <67>
DP5_AUXP <67>

DP5_TXN3 <67>
DP5_TXP3 <67>

DP5_TXN2 <67>
DP5_TXP2 <67>

DP5_TXN1 <67>
DP5_TXP1 <67>

DP5_TXN0 <67>
DP5_TXP0 <67>

DP4_AUXN <67>
DP4_AUXP <67>

DP4_TXN3 <67>
DP4_TXP3 <67>

DP4_TXN2 <67>
DP4_TXP2 <67>

DP4_TXN1 <67>
DP4_TXP1 <67>

DP4_TXN0 <67>
DP4_TXP0 <67>

DP5

DP4

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Under GPU

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Compal Electronics, Inc.

N17E-G1(2/6) eDP,HDMI,mDP-M

N17E-G1(2/6) eDP,HDMI,mDP-M

N17E-G1(2/6) eDP,HDMI,mDP-M

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

42 103Monday, January 09, 2017

42 103Monday, January 09, 2017

42 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

BC15
BC17

BD20

BD18

BB21
BB23

UG9Q

9/23 IFPD

IFPD

IFP_IOVDD_7
IFP_IOVDD_8

UG9R

8/23 IFPC

IFPCD_RSET

IFPCD_PLLVDD

IFPC

IFP_IOVDD_5
IFP_IOVDD_6

DVI/HDMI

DVI/HDMI

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

N17E-G1_BGA2152~D@

IFPD_AUX_SDA*

IFPD_AUX_SCL

N17E-G1_BGA2152~D@

DP

IFPC_AUX_SDA*

IFPC_AUX_SCL

IFPC_L3*

IFPC_L3

IFPC_L2*

IFPC_L2

IFPC_L1*

IFPC_L1

IFPC_L0*

IFPC_L0

DP

IFPD_L3*

IFPD_L3

IFPD_L2*

IFPD_L2

IFPD_L1*

IFPD_L1

IFPD_L0*

IFPD_L0

BF11
BE11

BM14
BM15

BL15
BK15

BK17
BL17

BM17
BM18

BL9
BK9

BF17
BE17

BF18
BG18

BG20
BH20

BF20
BE20

TMDS_SDATA <66>
TMDS_SCLK <66>

VGA_TMDS_TXCN <66>
VGA_TMDS_TXCP <66>

VGA_TMDS_TX0N <66>
VGA_TMDS_TX0P <66>

VGA_TMDS_TX1N <66>
VGA_TMDS_TX1P <66>

VGA_TMDS_TX2N <66>
VGA_TMDS_TX2P <66>

EDP_AUXN <65>
EDP_AUXP <65>

EDP_TXN3 <65>
EDP_TXP3 <65>

EDP_TXN2 <65>
EDP_TXP2 <65>

EDP_TXN1 <65>
EDP_TXP1 <65>

EDP_TXN0 <65>
EDP_TXP0 <65>

HDMI 2.0

eDP

RG37
1K_0402_1%

D D

+IFPX_PLLVDD

12

IFPCD_RSET

1

2

CG47

.1U_0402_16V7K

Under GPU

+1.0VSDGPU

1

CG48

2

.1U_0402_16V7K

C C

Under GPU

B B

+1.0VSDGPU

1

1

CG42

2

CG53

2

.1U_0402_16V7K

4.7U_0402_6.3V6M

Under GPU

A A

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2016/02/01 2017/12/31

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N17E-G1(1/6) PCIE,GPIO

N17E-G1(1/6) PCIE,GPIO

N17E-G1(1/6) PCIE,GPIO

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

1.0

1.0

1.0

43 103Monday, January 09, 2017

43 103Monday, January 09, 2017

43 103Monday, January 09, 2017

5

D D

4

3

2

1

UG9B

2/23 FBA

FBA_D0<49>
FBA_D1<49>
FBA_D2<49>
FBA_D3<49>
FBA_D4<49>
FBA_D5<49>
FBA_D6<49>
FBA_D7<49>
FBA_D8<49>
FBA_D9<49>
FBA_D10<49>
FBA_D11<49>
FBA_D12<49>
FBA_D13<49>
FBA_D14<49>
FBA_D15<49>
FBA_D16<49>
FBA_D17<49>
FBA_D18<49>
FBA_D19<49>
FBA_D20<49>
FBA_D21<49>
FBA_D22<49>
FBA_D23<49>
FBA_D24<49>
FBA_D25<49>
FBA_D26<49>
FBA_D27<49>
FBA_D28<49>
FBA_D29<49>
FBA_D30<49>
FBA_D31<49>
FBA_D32<49>
FBA_D33<49>
FBA_D34<49>
FBA_D35<49>
FBA_D36<49>
FBA_D37<49>
FBA_D38<49>
FBA_D39<49>
FBA_D40<49>

C C

FBA_D41<49>
FBA_D42<49>
FBA_D43<49>
FBA_D44<49>
FBA_D45<49>
FBA_D46<49>
FBA_D47<49>
FBA_D48<49>
FBA_D49<49>
FBA_D50<49>
FBA_D51<49>
FBA_D52<49>
FBA_D53<49>
FBA_D54<49>
FBA_D55<49>
FBA_D56<49>
FBA_D57<49>
FBA_D58<49>
FBA_D59<49>
FBA_D60<49>
FBA_D61<49>
FBA_D62<49>
FBA_D63<49>

FBA_DBI0<49>
FBA_DBI1<49>
FBA_DBI2<49>
FBA_DBI3<49>
FBA_DBI4<49>
FBA_DBI5<49>
FBA_DBI6<49>
FBA_DBI7<49>

FBA_EDC 0<49>
FBA_EDC 1<49>
FBA_EDC 2<49>
FBA_EDC 3<49>
FBA_EDC 4<49>
FBA_EDC 5<49>
FBA_EDC 6<49>
FBA_EDC 7<49>

+FBX_PLLA VDD

1

CG59

2

.1U_0402_16V7K

B B

U51

FBA_D0

U48

FBA_D1

U50

FBA_D2

U49

FBA_D3

R51

FBA_D4

R50

FBA_D5

R47

FBA_D6

U46

FBA_D7

V46

FBA_D8

Y45

FBA_D9

Y47

FBA_D10

Y46

FBA_D11

V50

FBA_D12

V47

FBA_D13

U52

FBA_D14

V51

FBA_D15

AJ44

FBA_D16

AG48

FBA_D17

AJ45

FBA_D18

AG49

FBA_D19

AF46

FBA_D20

AF47

FBA_D21

AF48

FBA_D22

AD47

FBA_D23

AD49

FBA_D24

AD48

FBA_D25

AC46

FBA_D26

AC47

FBA_D27

AA47

FBA_D28

AA46

FBA_D29

AA45

FBA_D30

Y44

FBA_D31

AW51

FBA_D32

BA52

FBA_D33

AW50

FBA_D34

BA51

FBA_D35

BA50

FBA_D36

BB50

FBA_D37

BA49

FBA_D38

AW49

FBA_D39

AV48

FBA_D40

AT49

FBA_D41

AT47

FBA_D42

AT48

FBA_D43

AT46

FBA_D44

AV51

FBA_D45

AV52

FBA_D46

AV49

FBA_D47

AJ48

FBA_D48

AJ46

FBA_D49

AJ47

FBA_D50

AK49

FBA_D51

AM47

FBA_D52

AM46

FBA_D53

AN48

FBA_D54

AN49

FBA_D55

AM44

FBA_D56

AM45

FBA_D57

AN45

FBA_D58

AN46

FBA_D59

AR48

FBA_D60

AN47

FBA_D61

AR47

FBA_D62

AR46

FBA_D63

U47

FBA_DQM0

Y48

FBA_DQM1

AG47

FBA_DQM2

AC48

FBA_DQM3

BB51

FBA_DQM4

AV50

FBA_DQM5

AM48

FBA_DQM6

AR49

FBA_DQM7

R48

FBA_DQS_WP0

V48

FBA_DQS_WP1

AF44

FBA_DQS_WP2

AA48

FBA_DQS_WP3

BB52

FBA_DQS_WP4

AT50

FBA_DQS_WP5

AK48

FBA_DQS_WP6

AR51

FBA_DQS_WP7

W47

GND_694

W49

GND_695

W51

GND_696

W6

GND_697

W8

GND_698

Y14

GND_699

Y15

GND_700

Y16

GND_701

AF42

FB_REFPLL_AVDD0

L29

FB_REFPLL_AVDD1

1

CG60

2

.1U_0402_16V7K

10K_0402_5 %
RG53

1 2

FBA_CMD1 3
FBA_CMD2 9
FBA_CMD1 7

FBA_CMD1

10K_0402_5 %
RG47

1 2

Y51

FBA_CMD1
FBA_CMD2

FBA_CMD1 7
FBA_CMD1 8

1

2

FBA_CMD0 <49>
FBA_CMD1 <49>
FBA_CMD2 <49>
FBA_CMD3 <49>
FBA_CMD4 <49>
FBA_CMD5 <49>
FBA_CMD6 <49>
FBA_CMD7 <49>
FBA_CMD8 <49>
FBA_CMD9 <49>
FBA_CMD1 0 <49>
FBA_CMD1 1 <49>
FBA_CMD1 2 <49>
FBA_CMD1 3 <49>
FBA_CMD1 4 <49>
FBA_CMD1 5 <49>
FBA_CMD1 6 <49>
FBA_CMD1 7 <49>
FBA_CMD1 8 <49>
FBA_CMD1 9 <49>
FBA_CMD2 0 <49>
FBA_CMD2 1 <49>
FBA_CMD2 2 <49>
FBA_CMD2 3 <49>
FBA_CMD2 4 <49>
FBA_CMD2 5 <49>
FBA_CMD2 6 <49>
FBA_CMD2 7 <49>
FBA_CMD2 8 <49>
FBA_CMD2 9 <49>
FBA_CMD3 0 <49>
FBA_CMD3 1 <49>

FBA_CLK0 <49>
FBA_CLK0 # <49>
FBA_CLK1 <49>
FBA_CLK1 # <49>

FBA_WCK0 1 <49>
FBA_WCK0 1# <49 >

FBA_WCK2 3 <49>
FBA_WCK2 3# <49 >

FBA_WCK4 5 <49>
FBA_WCK4 5# <49 >

FBA_WCK6 7 <49>
FBA_WCK6 7# <49 >

1 2

LG6
PBY160808T-300Y-N_2P

1 2

LG2
PBY160808T-300Y-N_2P

12

CG54

CG55

0.1U_0402_16V7K

22U_0603_6.3V6M

FBA_CMD0

Y52

FBA_CMD1

Y49

FBA_CMD2

AA52

FBA_CMD3

AA51

FBA_CMD4

AA50

FBA_CMD5

AC50

FBA_CMD6

AC51

FBA_CMD7

AC52

FBA_CMD8

AC49

FBA_CMD9

AD52

FBA_CMD10

AD51

FBA_CMD11

AD50

FBA_CMD12

AF50

FBA_CMD13

AF51

FBA_CMD14

AF52

FBA_CMD15

AN50

FBA_CMD16

AN51

FBA_CMD17

AN52

FBA_CMD18

AM49

FBA_CMD19

AM52

FBA_CMD20

AM51

FBA_CMD21

AM50

FBA_CMD22

AK50

FBA_CMD23

AK51

FBA_CMD24

AK52

FBA_CMD25

AJ49

FBA_CMD26

AJ52

FBA_CMD27

AJ51

FBA_CMD28

AJ50

FBA_CMD29

AG50

FBA_CMD30

AG51

FBA_CMD31

AG52

FBA_CMD32

AF49

FBA_CMD33

Y50

FBA_CMD34

AR50

FBA_CMD35

AA44

FBA_DBG_RFU1

AN44

FBA_DBG_RFU2

AG45

FBA_CLK0

AG46

FBA_CLK0*

AK46

FBA_CLK1

AK45

FBA_CLK1*

U45

FBA_WCK01

U44

FBA_WCK01*

V45

FBA_WCKB01

V44

FBA_WCKB01*

AC45

FBA_WCK23

AC44

FBA_WCK23*

AD46

FBA_WCKB23

AD45

FBA_WCKB23*

AV47

FBA_WCK45

AV46

FBA_WCK45*

AW48

FBA_WCKB45

AW47

FBA_WCKB45*

AR45

FBA_WCK67

AR44

FBA_WCK67*

AT45

FBA_WCKB67

AT44

FBA_WCKB67*

AN42

FBA_PLL_AVDD

Under GPU Under GPU Under GPU Under GPU

N17E-G1_BGA21 52~D@

+1.35VSDGPU

10K_0402_5 %
RG54

1 2

10K_0402_5 %
RG48

1 2

+1.8VSDGPU_MA IN

FBB_D0<50>
FBB_D1<50>
FBB_D2<50>
FBB_D3<50>
FBB_D4<50>
FBB_D5<50>
FBB_D6<50>
FBB_D7<50>
FBB_D8<50>
FBB_D9<50>
FBB_D10<50>
FBB_D11<50>
FBB_D12<50>
FBB_D13<50>
FBB_D14<50>
FBB_D15<50>
FBB_D16<50>
FBB_D17<50>
FBB_D18<50>
FBB_D19<50>
FBB_D20<50>
FBB_D21<50>
FBB_D22<50>
FBB_D23<50>
FBB_D24<50>
FBB_D25<50>
FBB_D26<50>
FBB_D27<50>
FBB_D28<50>
FBB_D29<50>
FBB_D30<50>
FBB_D31<50>
FBB_D32<50>
FBB_D33<50>
FBB_D34<50>
FBB_D35<50>
FBB_D36<50>
FBB_D37<50>
FBB_D38<50>
FBB_D39<50>
FBB_D40<50>
FBB_D41<50>
FBB_D42<50>
FBB_D43<50>
FBB_D44<50>
FBB_D45<50>
FBB_D46<50>
FBB_D47<50>
FBB_D48<50>
FBB_D49<50>
FBB_D50<50>
FBB_D51<50>
FBB_D52<50>
FBB_D53<50>
FBB_D54<50>
FBB_D55<50>
FBB_D56<50>
FBB_D57<50>
FBB_D58<50>
FBB_D59<50>
FBB_D60<50>
FBB_D61<50>
FBB_D62<50>
FBB_D63<50>

FBB_DBI0<50>
FBB_DBI1<50>
FBB_DBI2<50>
FBB_DBI3<50>
FBB_DBI4<50>
FBB_DBI5<50>
FBB_DBI6<50>
FBB_DBI7<50>

FBB_EDC 0<50>
FBB_EDC 1<50>
FBB_EDC 2<50>
FBB_EDC 3<50>
FBB_EDC 4<50>
FBB_EDC 5<50>
FBB_EDC 6<50>
FBB_EDC 7<50>

UG9C

3/23 FBB

H32

FBB_D0

D32

FBB_D1

A33

FBB_D2

B32

FBB_D3

E32

FBB_D4

G32

FBB_D5

J30

FBB_D6

F32

FBB_D7

H36

FBB_D8

G36

FBB_D9

J36

FBB_D10

F36

FBB_D11

F33

FBB_D12

D33

FBB_D13

J32

FBB_D14

G33

FBB_D15

E45

FBB_D16

D45

FBB_D17

F45

FBB_D18

G45

FBB_D19

D42

FBB_D20

E42

FBB_D21

F42

FBB_D22

H41

FBB_D23

E41

FBB_D24

F39

FBB_D25

E39

FBB_D26

D39

FBB_D27

F38

FBB_D28

E38

FBB_D29

D36

FBB_D30

E36

FBB_D31

M50

FBB_D32

P48

FBB_D33

M51

FBB_D34

M49

FBB_D35

P47

FBB_D36

P52

FBB_D37

R46

FBB_D38

P46

FBB_D39

L50

FBB_D40

L51

FBB_D41

L52

FBB_D42

L49

FBB_D43

M46

FBB_D44

L47

FBB_D45

M48

FBB_D46

M47

FBB_D47

D48

FBB_D48

C50

FBB_D49

C48

FBB_D50

C49

FBB_D51

E49

FBB_D52

E50

FBB_D53

F49

FBB_D54

F48

FBB_D55

F50

FBB_D56

D52

FBB_D57

J50

FBB_D58

H48

FBB_D59

H51

FBB_D60

J51

FBB_D61

H49

FBB_D62

H52

FBB_D63

C32

FBB_DQM0

E33

FBB_DQM1

E44

FBB_DQM2

G39

FBB_DQM3

P49

FBB_DQM4

L48

FBB_DQM5

D50

FBB_DQM6

H50

FBB_DQM7

B33

FBB_DQS_WP0

E35

FBB_DQS_WP1

G44

FBB_DQS_WP2

H38

FBB_DQS_WP3

P50

FBB_DQS_WP4

J48

FBB_DQS_WP5

D51

FBB_DQS_WP6

F51

FBB_DQS_WP7

Y17

GND_702

Y18

GND_703

Y19

GND_704

Y20

GND_705

Y21

GND_706

Y22

GND_707

Y23

GND_708

Y24

GND_709

10K_0402_5 %
RG55

1 2

FBB_CMD1 3
FBB_CMD2 9
FBB_CMD1 7

FBB_CMD1

10K_0402_5 %
RG49

1 2

N17E-G1_BGA21 52~D@

+1.35VSDGPU

FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8

FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
FBB_CMD32
FBB_CMD33
FBB_CMD34
FBB_CMD35

FBB_DBG_RFU1
FBB_DBG_RFU2

FBB_CLK0

FBB_CLK0*

FBB_CLK1

FBB_CLK1*

FBB_WCK01

FBB_WCK01*

FBB_WCKB01

FBB_WCKB01*

FBB_WCK23

FBB_WCK23*

FBB_WCKB23

FBB_WCKB23*

FBB_WCK45

FBB_WCK45*

FBB_WCKB45

FBB_WCKB45*

FBB_WCK67

FBB_WCK67*

FBB_WCKB67

FBB_WCKB67*

FBB_PLL_AVDD

10K_0402_5 %
RG56

1 2

10K_0402_5 %
RG50

1 2

B35

FBB_CMD1
FBB_CMD2

FBB_CMD1 7
FBB_CMD1 8

0.1U_0402_16V7K

1

2

CG56

FBB_CMD0 <50>
FBB_CMD1 <50>
FBB_CMD2 <50>
FBB_CMD3 <50>
FBB_CMD4 <50>
FBB_CMD5 <50>
FBB_CMD6 <50>
FBB_CMD7 <50>
FBB_CMD8 <50>
FBB_CMD9 <50>
FBB_CMD1 0 <50>
FBB_CMD1 1 <50>
FBB_CMD1 2 <50>
FBB_CMD1 3 <50>
FBB_CMD1 4 <50>
FBB_CMD1 5 <50>
FBB_CMD1 6 <50>
FBB_CMD1 7 <50>
FBB_CMD1 8 <50>
FBB_CMD1 9 <50>
FBB_CMD2 0 <50>
FBB_CMD2 1 <50>
FBB_CMD2 2 <50>
FBB_CMD2 3 <50>
FBB_CMD2 4 <50>
FBB_CMD2 5 <50>
FBB_CMD2 6 <50>
FBB_CMD2 7 <50>
FBB_CMD2 8 <50>
FBB_CMD2 9 <50>
FBB_CMD3 0 <50>
FBB_CMD3 1 <50>

FBB_CLK0 <50>
FBB_CLK0 # <50>
FBB_CLK1 <50>
FBB_CLK1 # <50>

FBB_WCK0 1 <50>
FBB_WCK0 1# <50 >

FBB_WCK2 3 <50>
FBB_WCK2 3# <50 >

FBB_WCK4 5 <50>
FBB_WCK4 5# <50 >

FBB_WCK6 7 <50>
FBB_WCK6 7# <50 >

20160201_Change PN

A35
D35
A36
B36
C36
C38
B38
A38
D38
A39
B39
C39
C41
B41
A41
B49
A49
A48
D47
A47
B47
C47
C45
B45
A45
D44
A44
B44
C44
C42
B42
A42
D41
C35
B50

J35
J41

H42
G42
F47
E47

J33
H33
G35
H35
J39
H39
F41
G41
L46
L45
M44
M45
H47
H46
J47
J46

L38

FBC_D0<51>
FBC_D1<51>
FBC_D2<51>
FBC_D3<51>
FBC_D4<51>
FBC_D5<51>
FBC_D6<51>
FBC_D7<51>
FBC_D8<51>
FBC_D9<51>
FBC_D10<5 1>
FBC_D11<5 1>
FBC_D12<5 1>
FBC_D13<5 1>
FBC_D14<5 1>
FBC_D15<5 1>
FBC_D16<5 1>
FBC_D17<5 1>
FBC_D18<5 1>
FBC_D19<5 1>
FBC_D20<5 1>
FBC_D21<5 1>
FBC_D22<5 1>
FBC_D23<5 1>
FBC_D24<5 1>
FBC_D25<5 1>
FBC_D26<5 1>
FBC_D27<5 1>
FBC_D28<5 1>
FBC_D29<5 1>
FBC_D30<5 1>
FBC_D31<5 1>
FBC_D32<5 1>
FBC_D33<5 1>
FBC_D34<5 1>
FBC_D35<5 1>
FBC_D36<5 1>
FBC_D37<5 1>
FBC_D38<5 1>
FBC_D39<5 1>
FBC_D40<5 1>
FBC_D41<5 1>
FBC_D42<5 1>
FBC_D43<5 1>
FBC_D44<5 1>
FBC_D45<5 1>
FBC_D46<5 1>
FBC_D47<5 1>
FBC_D48<5 1>
FBC_D49<5 1>
FBC_D50<5 1>
FBC_D51<5 1>
FBC_D52<5 1>
FBC_D53<5 1>
FBC_D54<5 1>
FBC_D55<5 1>
FBC_D56<5 1>
FBC_D57<5 1>
FBC_D58<5 1>
FBC_D59<5 1>
FBC_D60<5 1>
FBC_D61<5 1>
FBC_D62<5 1>
FBC_D63<5 1>

FBC_DBI0<51>
FBC_DBI1<51>
FBC_DBI2<51>
FBC_DBI3<51>
FBC_DBI4<51>
FBC_DBI5<51>
FBC_DBI6<51>
FBC_DBI7<51>

FBC_EDC 0<51>
FBC_EDC 1<51>
FBC_EDC 2<51>
FBC_EDC 3<51>
FBC_EDC 4<51>
FBC_EDC 5<51>
FBC_EDC 6<51>
FBC_EDC 7<51>

C6
D6
A6
B6
B4
A4
B3
C4
D9
C9
E9
B9
B8
A8

F6
E6
F18
G18
E18
H18
D15
E15
G17
H17
J15
H15
E14
F14
H11
G11
F11
E11
J29
F30
H29
G30
B30
A30
H30
C30
D27
J26
F27
G27
C27
B27
A27
G29
H20
D18
G20
E20
F23
E21
D21
E23
G24
H26
F24
G26
F26
D26
B26
C26

A5
C8
J18
F12
D29
E27
F20
E26

D5
D8
E17
E12
E30
B29
G21
E24

Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y32

UG9D

4/23 FBC

FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63

FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7

FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7

GND_710
GND_711
GND_712
GND_713
GND_714
GND_715
GND_716
GND_717

FBC_CMD1 3
FBC_CMD2 9
FBC_CMD1 7
FBC_CMD1

UG9E

C11

FBC_CMD1

FBC_CMD0

B11

FBC_CMD1

A11

FBC_CMD2

D11

FBC_CMD3

A12

FBC_CMD4

B12

FBC_CMD5

C12

FBC_CMD6

C14

FBC_CMD7

B14

FBC_CMD8

A14

FBC_CMD9

D14

FBC_CMD10

A15

FBC_CMD11

B15

FBC_CMD12

C15

FBC_CMD13

C17

FBC_CMD14

B17

FBC_CMD15

B24

FBC_CMD16

A24

FBC_CMD17

D23

FBC_CMD18

A23

FBC_CMD19

B23

FBC_CMD20

C23

FBC_CMD21

C21

FBC_CMD22

B21

FBC_CMD23

A21

FBC_CMD24

D20

FBC_CMD25

A20

FBC_CMD26

B20

FBC_CMD27

C20

FBC_CMD28

C18

FBC_CMD29

B18

FBC_CMD30

A18

FBC_CMD31

D17

FBC_CMD32

A17

FBC_CMD33

A9

FBC_CMD34

C24

FBC_CMD35

J14

FBC_DBG_RFU1

J23

FBC_DBG_RFU2

G15

FBC_CLK0

F15

FBC_CLK0*

H21

FBC_CLK1

J21

FBC_CLK1*

F8

FBC_WCK01

G8

FBC_WCK01*

G9

FBC_WCKB01

F9

FBC_WCKB01*

H12

FBC_WCK23

G12

FBC_WCK23*

G14

FBC_WCKB23

H14

FBC_WCKB23*

J27

FBC_WCK45

H27

FBC_WCK45*

E29

FBC_WCKB45

F29

FBC_WCKB45*

G23

FBC_WCK67

H23

FBC_WCK67*

H24

FBC_WCKB67

J24

FBC_WCKB67*

L17

FBC_PLL_AVDD

N17E-G1_BGA21 52~D@

+1.35VSDGPU +1.35VSDGPU

10K_0402_5 %

10K_0402_5 %

RG57

RG58

1 2

1 2

10K_0402_5 %

10K_0402_5 %

RG52

RG51

1 2

1 2

FBC_CMD0 <51>

FBC_CMD2

FBC_CMD1 <51>
FBC_CMD2 <51>
FBC_CMD3 <51>
FBC_CMD4 <51>
FBC_CMD5 <51>
FBC_CMD6 <51>
FBC_CMD7 <51>
FBC_CMD8 <51>
FBC_CMD9 <51>
FBC_CMD1 0 <51>
FBC_CMD1 1 <51>
FBC_CMD1 2 <51>
FBC_CMD1 3 <51>
FBC_CMD1 4 <51>
FBC_CMD1 5 <51>

FBC_CMD1 7

FBC_CMD1 6 <51>

FBC_CMD1 8

FBC_CMD1 7 <51>
FBC_CMD1 8 <51>
FBC_CMD1 9 <51>
FBC_CMD2 0 <51>
FBC_CMD2 1 <51>
FBC_CMD2 2 <51>
FBC_CMD2 3 <51>
FBC_CMD2 4 <51>
FBC_CMD2 5 <51>
FBC_CMD2 6 <51>
FBC_CMD2 7 <51>
FBC_CMD2 8 <51>
FBC_CMD2 9 <51>
FBC_CMD3 0 <51>
FBC_CMD3 1 <51>

FBC_CLK0 <51>
FBC_CLK0 # <51>
FBC_CLK1 <51>
FBC_CLK1 # <51>

FBC_WCK 01 <5 1>
FBC_WCK 01# <51>

FBC_WCK 23 <5 1>
FBC_WCK 23# <51>

FBC_WCK 45 <5 1>
FBC_WCK 45# <51>

FBC_WCK 67 <5 1>
FBC_WCK 67# <51>

0.1U_0402_16V7K
CG57

1

20160201_Change PN 20160201_Change PN

2

FBD_D0<52>
FBD_D1<52>
FBD_D2<52>
FBD_D3<52>
FBD_D4<52>
FBD_D5<52>
FBD_D6<52>
FBD_D7<52>
FBD_D8<52>
FBD_D9<52>
FBD_D10<5 2>
FBD_D11<5 2>
FBD_D12<5 2>
FBD_D13<5 2>
FBD_D14<5 2>
FBD_D15<5 2>
FBD_D16<5 2>
FBD_D17<5 2>
FBD_D18<5 2>
FBD_D19<5 2>
FBD_D20<5 2>
FBD_D21<5 2>
FBD_D22<5 2>
FBD_D23<5 2>
FBD_D24<5 2>
FBD_D25<5 2>
FBD_D26<5 2>
FBD_D27<5 2>
FBD_D28<5 2>
FBD_D29<5 2>
FBD_D30<5 2>
FBD_D31<5 2>
FBD_D32<5 2>
FBD_D33<5 2>
FBD_D34<5 2>
FBD_D35<5 2>
FBD_D36<5 2>
FBD_D37<5 2>
FBD_D38<5 2>
FBD_D39<5 2>
FBD_D40<5 2>
FBD_D41<5 2>
FBD_D42<5 2>
FBD_D43<5 2>
FBD_D44<5 2>
FBD_D45<5 2>
FBD_D46<5 2>
FBD_D47<5 2>
FBD_D48<5 2>
FBD_D49<5 2>
FBD_D50<5 2>
FBD_D51<5 2>
FBD_D52<5 2>
FBD_D53<5 2>
FBD_D54<5 2>
FBD_D55<5 2>
FBD_D56<5 2>
FBD_D57<5 2>
FBD_D58<5 2>
FBD_D59<5 2>
FBD_D60<5 2>
FBD_D61<5 2>
FBD_D62<5 2>
FBD_D63<5 2>

FBD_DBI0<52>
FBD_DBI1<52>
FBD_DBI2<52>
FBD_DBI3<52>
FBD_DBI4<52>
FBD_DBI5<52>
FBD_DBI6<52>
FBD_DBI7<52>

FBD_EDC 0<52>
FBD_EDC 1<52>
FBD_EDC 2<52>
FBD_EDC 3<52>
FBD_EDC 4<52>
FBD_EDC 5<52>
FBD_EDC 6<52>
FBD_EDC 7<52>

AK8
AK4
AK2
AK3
AK5
AK6
AK9
AK7
AG4
AF9
AG6
AG7
AJ4
AJ5
AJ6
AG5

AA6
AA5
AC5
AC4
AD7
AC6
AF6
AD6
AF7
AF8
AF2
AF3

AJ1
AG1
AA7
AD5

AJ3
AG2
AA9
AF4

Y33
Y34
Y35
Y36
Y37
Y38
Y39

Y6
Y5
V5
Y4

F4
E1
F3
F5
D2
D1
C3
C2
J5
J4
L8
J2
F1
F2
H4
H5
V7
V8
V6
V9
U4
R5
R6
U8
P6
R9
P4
P5
L7
L6
L4
L5

D3
H3
U5

M9

E3
H2
U6

M5

Y9

5/23 FBD

FBD_D0
FBD_D1
FBD_D2
FBD_D3
FBD_D4
FBD_D5
FBD_D6
FBD_D7
FBD_D8
FBD_D9
FBD_D10
FBD_D11
FBD_D12
FBD_D13
FBD_D14
FBD_D15
FBD_D16
FBD_D17
FBD_D18
FBD_D19
FBD_D20
FBD_D21
FBD_D22
FBD_D23
FBD_D24
FBD_D25
FBD_D26
FBD_D27
FBD_D28
FBD_D29
FBD_D30
FBD_D31
FBD_D32
FBD_D33
FBD_D34
FBD_D35
FBD_D36
FBD_D37
FBD_D38
FBD_D39
FBD_D40
FBD_D41
FBD_D42
FBD_D43
FBD_D44
FBD_D45
FBD_D46
FBD_D47
FBD_D48
FBD_D49
FBD_D50
FBD_D51
FBD_D52
FBD_D53
FBD_D54
FBD_D55
FBD_D56
FBD_D57
FBD_D58
FBD_D59
FBD_D60
FBD_D61
FBD_D62
FBD_D63

FBD_DQM0
FBD_DQM1
FBD_DQM2
FBD_DQM3
FBD_DQM4
FBD_DQM5
FBD_DQM6
FBD_DQM7

FBD_DQS_WP0
FBD_DQS_WP1
FBD_DQS_WP2
FBD_DQS_WP3
FBD_DQS_WP4
FBD_DQS_WP5
FBD_DQS_WP6
FBD_DQS_WP7

GND_0718
GND_0719
GND_0720
GND_0721
GND_0722
GND_0723
GND_0724
GND_0725

FBD_CMD1 3
FBD_CMD2 9
FBD_CMD1 7
FBD_CMD1

GP104

1 2

1 2

FBD

10K_0402_5 %
RG450

10K_0402_5 %
RG451

N17E-G1_BGA21 52~D@

FBD_DBG_RFU1
FBD_DBG_RFU2

FBD_WCK01*
FBD_WCKB01

FBD_WCKB01*

FBD_WCK23*
FBD_WCKB23

FBD_WCKB23*

FBD_WCK45*
FBD_WCKB45

FBD_WCKB45*

FBD_WCK67*
FBD_WCKB67

FBD_WCKB67*

FBD_PLL_AVDD

GP106

UNUSED

1 2

1 2

FBD_CMD0
FBD_CMD1
FBD_CMD2
FBD_CMD3
FBD_CMD4
FBD_CMD5
FBD_CMD6
FBD_CMD7
FBD_CMD8

FBD_CMD9
FBD_CMD10
FBD_CMD11
FBD_CMD12
FBD_CMD13
FBD_CMD14
FBD_CMD15
FBD_CMD16
FBD_CMD17
FBD_CMD18
FBD_CMD19
FBD_CMD20
FBD_CMD21
FBD_CMD22
FBD_CMD23
FBD_CMD24
FBD_CMD25
FBD_CMD26
FBD_CMD27
FBD_CMD28
FBD_CMD29
FBD_CMD30
FBD_CMD31
FBD_CMD32
FBD_CMD33
FBD_CMD34
FBD_CMD35

FBD_CLK0

FBD_CLK0*

FBD_CLK1

FBD_CLK1*

FBD_WCK01

FBD_WCK23

FBD_WCK45

FBD_WCK67

10K_0402_5 %
RG453

10K_0402_5 %
RG452

AD2

FBD_CMD1
FBD_CMD2

FBD_CMD1 7
FBD_CMD1 8

0.1U_0402_16V7K

1

2

FBD_CMD0 <52>
FBD_CMD1 <52>
FBD_CMD2 <52>
FBD_CMD3 <52>
FBD_CMD4 <52>
FBD_CMD5 <52>
FBD_CMD6 <52>
FBD_CMD7 <52>
FBD_CMD8 <52>
FBD_CMD9 <52>
FBD_CMD1 0 <52>
FBD_CMD1 1 <52>
FBD_CMD1 2 <52>
FBD_CMD1 3 <52>
FBD_CMD1 4 <52>
FBD_CMD1 5 <52>
FBD_CMD1 6 <52>
FBD_CMD1 7 <52>
FBD_CMD1 8 <52>
FBD_CMD1 9 <52>
FBD_CMD2 0 <52>
FBD_CMD2 1 <52>
FBD_CMD2 2 <52>
FBD_CMD2 3 <52>
FBD_CMD2 4 <52>
FBD_CMD2 5 <52>
FBD_CMD2 6 <52>
FBD_CMD2 7 <52>
FBD_CMD2 8 <52>
FBD_CMD2 9 <52>
FBD_CMD3 0 <52>
FBD_CMD3 1 <52>

FBD_CLK0 <52>
FBD_CLK0 # <52>
FBD_CLK1 <52>
FBD_CLK1 # <52>

FBD_WCK 01 <52>
FBD_WCK 01# <52>

FBD_WCK 23 <52>
FBD_WCK 23# <52>

FBD_WCK 45 <52>
FBD_WCK 45# <52>

FBD_WCK 67 <52>
FBD_WCK 67# <52>

CG58

AD1
AD4
AC1
AC2
AC3
AA3
AA2
AA1
AA4
Y1
Y2
Y3
V3
V2
V1
L3
L2
L1
M4
M1
M2
M3
P3
P2
P1
R4
R1
R2
R3
U3
U2
U1
V4
AD3
J3

AC9
P9

Y8
Y7
R8
R7

AJ8
AJ7
AG8
AG9
AD8
AD9
AC7
AC8
J6
J7
H7
H6
P8
P7
M7
M8

+FBX_PLLA VDD+FBX_PLLA VDD+FBX_PLLA VDD +FBX_PLLA VDD

V11

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

N17E-G1(3/6) MEM Interface-M

N17E-G1(3/6) MEM Interface-M

N17E-G1(3/6) MEM Interface-M

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

44 103Monda y, January 09, 2017

44 103Monda y, January 09, 2017

44 103Monda y, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

I2CC_SCL<41>
I2CC_SDA<41>

CG862

3VSDGPU_EN_R

.1U_0402_16V7K

+3VSDGPU

RG60

+3VSDGPU

+3VS

1

2

+5VALW

CG861

3
2

DAN202UT106_SC7 0-3
DG21

12

1.8K_0402_1%

1

2

1

12

RG61

1.8K_0402_1%

4

11
12

14
15

1
2

6
7

DGPU_PWR_EN

1V8_MAIN_EN

UG14

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON 8

1V8_AON_EN_R

100P_0402_50V8J~D

1

CG61

2

UG11

16

VPU

VS

13

IN-1

TC

IN+1

10

PV

IN-2

9

Critical

IN+2

8

IN-3

Warning

IN+3

5

A0

SCL

3

SDA

GND

INA3221AIRGVR_VQFN16_ 4X4

+1.8VSDGPU_AON

5

1

VCC

IN B

2

IN A

GND

3

6

VOUT

5

GND

12

RG777
100K_0201_5%

+3VSDGPU

12

1 2

RG797 0_040 2_5%

12

RG65
10K_0402_1%

U67

3VSDGPU_EN_1 3VSDGPU_EN_R

1 2

4

OUT Y

NL17SZ08DFT2G_SC7 0-5

+3VSDGPU

1

2

CG857

10U_0603_6.3V6M

RG783 10K_0 402_5%

1

CG858

0.1U_0402_16V7K

2

+1.8VSDGPU_AON

RG63
10K_0402_1%

2

G

6 1

D

0.1U_0402_16V7K

1

2

S

CG914

QG5B
PJT138KA 2N SOT363-6

@

OC_WARN# <41>

+NVVDD1

UG9G

19/23 VDD_2/2

AP21

VDD_145
VDD_146
VDD_147
VDD_148
VDD_149
VDD_150
VDD_151
VDD_152
VDD_153
VDD_154
VDD_155
VDD_156
VDD_157
VDD_158
VDD_159
VDD_160
VDD_161
VDD_162
VDD_163
VDD_164
VDD_165
VDD_166
VDD_167
VDD_168
VDD_169
VDD_170
VDD_171
VDD_172
VDD_173
VDD_174
VDD_175
VDD_176
VDD_177
VDD_178
VDD_179
VDD_180
VDD_181
VDD_182
VDD_183
VDD_184
VDD_185
VDD_186
VDD_187
VDD_188
VDD_189
VDD_190
VDD_191
VDD_192
VDD_193
VDD_194
VDD_195
VDD_196
VDD_197
VDD_198
VDD_199
VDD_200
VDD_201
VDD_202
VDD_203
VDD_204
VDD_205
VDD_206
VDD_207
VDD_208
VDD_209
VDD_210
VDD_211
VDD_212
VDD_213
VDD_214
VDD_215
VDD_216
VDD_217
VDD_218

VDD_219
VDD_220
VDD_221
VDD_222
VDD_223
VDD_224
VDD_225
VDD_226
VDD_227
VDD_228
VDD_229
VDD_230
VDD_231
VDD_232
VDD_233
VDD_234
VDD_235
VDD_236
VDD_237
VDD_238
VDD_239
VDD_240
VDD_241
VDD_242
VDD_243
VDD_244
VDD_245
VDD_246
VDD_247
VDD_248
VDD_249
VDD_250
VDD_251
VDD_252
VDD_253
VDD_254
VDD_255
VDD_321
VDD_322
VDD_323
VDD_324
VDD_325
VDD_326
VDD_327
VDD_328
VDD_329
VDD_330
VDD_331
VDD_332
VDD_333
VDD_334
VDD_335
VDD_336
VDD_337
VDD_338
VDD_339
VDD_340
VDD_341
VDD_342
VDD_343
VDD_344
VDD_345
VDD_346
VDD_347
VDD_348
VDD_349
VDD_350
VDD_351
VDD_352
VDD_353
VDD_354
VDD_355
VDD_356

AP22
AP23
AP30

D D

C C

B B

AP31
AP32
AP33
AP34
AR13
AR40

AT14
AT15
AT16
AT17
AT18
AT19
AT20
AT21
AT22
AT23
AT24
AT25
AT26
AT27
AT28
AT29
AT30
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AT39

AT42
AU43
AV19
AV20
AV21
AV22
AV23
AV30
AV31
AV32
AV33
AV34
AV42
AV43
AV44
AW13
AW40
AW42
AW43
AW44
AW45

AY14

AY18

AY22

AY26

AY27

AY31

AY35

AY39

AY43

AY45
BA43
BA44
BA45
BA46
BA47
BB38
BB39

10U_0603_6.3V6M

470U_X_2VY_R9M

CG244

1

CG245

1

+

2

2

+NVVDD1

BB45
BB46
BB47
BB48
BC38
BC39
BC40
BC41
BC45
BC47
BC49
BD39
BD41
BD46
BD47
BD48
BD49
BD50
BD51
BE41
BE42
BE43
BE46
BE47
BE48
BE49
BE50
BE51
BE52
BF42
BF44
BF45
BF47
BF49
BF51
BG43
BG44
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U27
U28
U29
U30
U31
U32
U33
U34
U35
U36
U37
U38
U39
V13
V40
W19
W20
W21
W22
W23
W30
W31
W32
W33
W34

+NVVDD2

UG9J

23/23 VDDS

AP27

VDDS_057
VDDS_058
VDDS_059
VDDS_060
VDDS_061
VDDS_062
VDDS_063
VDDS_064
VDDS_065
VDDS_066
VDDS_067
VDDS_068
VDDS_069
VDDS_070
VDDS_071
VDDS_072
VDDS_073
VDDS_074
VDDS_075
VDDS_076
VDDS_077
VDDS_078
VDDS_079
VDDS_080
VDDS_081
VDDS_082
VDDS_083
VDDS_084
VDDS_085
VDDS_086
VDDS_087
VDDS_088
VDDS_089
VDDS_090
VDDS_091
VDDS_092
VDDS_093
VDDS_094
VDDS_095
VDDS_096
VDDS_097
VDDS_098
VDDS_099
VDDS_100
VDDS_101
VDDS_102
VDDS_103
VDDS_104
VDDS_105
VDDS_106
VDDS_107
VDDS_108
VDDS_109
VDDS_110
VDDS_111
VDDS_112

VDDS_001
VDDS_002
VDDS_003
VDDS_004
VDDS_005
VDDS_006
VDDS_007
VDDS_008
VDDS_009
VDDS_010
VDDS_011
VDDS_012
VDDS_013
VDDS_014
VDDS_015
VDDS_016
VDDS_017
VDDS_018
VDDS_019
VDDS_020
VDDS_021
VDDS_022
VDDS_023
VDDS_024
VDDS_025
VDDS_026
VDDS_027
VDDS_028
VDDS_029
VDDS_030
VDDS_031
VDDS_032
VDDS_033
VDDS_034
VDDS_035
VDDS_036
VDDS_037
VDDS_038
VDDS_039
VDDS_040
VDDS_041
VDDS_042
VDDS_043
VDDS_044
VDDS_045
VDDS_046
VDDS_047
VDDS_048
VDDS_049
VDDS_050
VDDS_051
VDDS_052
VDDS_053
VDDS_054
VDDS_055
VDDS_056

VDDS_SENSE
GNDS_SENSE

N17E-G1_BGA2152~D@

AP28
AP29
AP35
AP36
AP37
AP38
AP39
AV14
AV15
AV16
AV17
AV18
AV24
AV25
AV26
AV27
AV28
AV29
AV35
AV36
AV37
AV38
AV39

R14
R15
R16
R17
R18
R24
R25
R26
R27
R28
R29
R35
R36
R37
R38

R39
W14
W15
W16
W17
W18
W24
W25
W26
W27
W28
W29
W35
W36
W37
W38
W39

+NVVDD2

AC14
AC15
AC16
AC17
AC18
AC24
AC25
AC26
AC27
AC28
AC29
AC35
AC36
AC37
AC38
AC39
AF14
AF15
AF16
AF17
AF18
AF24
AF25
AF26
AG27
AG28
AG29
AG35
AG36
AG37
AG38
AG39
AK14
AK15
AK16
AK17
AK18
AK24
AK25
AK26
AK27
AK28
AK29
AK35
AK36
AK37
AK38
AK39
AP14
AP15
AP16
AP17
AP18
AP24
AP25
AP26

BM45
BM44

NVVDDS_VCC_SENSE <87>
NVVDDS_VSS_SENSE <87>

+1.35VSDGPU +1.35VSDGPU

UG9H

20/23 FBVDDQ

AA10

FBVDDQ_01

AA11

FBVDDQ_02

AA42

FBVDDQ_03

AA43

FBVDDQ_04

AC10

FBVDDQ_05

AC11

FBVDDQ_06

AC42

FBVDDQ_07

AC43

FBVDDQ_08

AD10

FBVDDQ_09

AD11

FBVDDQ_10

AD42

FBVDDQ_11

AD43

FBVDDQ_12

AF10

FBVDDQ_13

AF43

FBVDDQ_14

AG10

FBVDDQ_15

AG11

FBVDDQ_16

AG42

FBVDDQ_17

AG43

FBVDDQ_18

AJ10

FBVDDQ_19

AJ11

FBVDDQ_20

AJ42

FBVDDQ_21

AJ43

FBVDDQ_22

AK10

FBVDDQ_23

AK11

FBVDDQ_24

AK42

FBVDDQ_25

AK43

FBVDDQ_26

AM42

FBVDDQ_27

AM43

FBVDDQ_28

AN43

FBVDDQ_29

AR42

FBVDDQ_30

AR43

FBVDDQ_31

R42

FBVDDQ_76

R43

FBVDDQ_77

U10

FBVDDQ_78

U11

FBVDDQ_79

U43

FBVDDQ_80

V10

FBVDDQ_81

V42

FBVDDQ_82

V43

FBVDDQ_83

Y10

FBVDDQ_84

Y11

FBVDDQ_85

Y42

FBVDDQ_86

Y43

FBVDDQ_87

10U_0603_6.3V6M

470U_X_2VY_R9M

CG242

1

CG243

1

+

2

2

FB_CAL_TERM_GND

N17E-G1_BGA2152~D@

FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
FBVDDQ_43
FBVDDQ_44
FBVDDQ_45
FBVDDQ_46
FBVDDQ_47
FBVDDQ_48
FBVDDQ_49
FBVDDQ_50
FBVDDQ_51
FBVDDQ_52
FBVDDQ_53
FBVDDQ_54
FBVDDQ_55
FBVDDQ_56
FBVDDQ_57
FBVDDQ_58
FBVDDQ_59
FBVDDQ_60
FBVDDQ_61
FBVDDQ_62
FBVDDQ_63
FBVDDQ_64
FBVDDQ_65
FBVDDQ_66
FBVDDQ_67
FBVDDQ_68
FBVDDQ_69
FBVDDQ_70
FBVDDQ_71
FBVDDQ_72
FBVDDQ_73
FBVDDQ_74
FBVDDQ_75

FBVDDQ_SENSE

FB_VREF

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

AT43
K12
K14
K15
K17
K18
K20
K21
K23
K24
K26
K27
K29
K30
K32
K33
K35
K36
K38
K39
K41
L14
L15
L18
L20
L21
L23
L24
L26
L27
L30
L32
L33
L35
L36
L39
M10
M43
P10
P11
P42
P43
R10
R11

E52

P45

R44
P44
R45

FBCAL_VDDQ
FBCAL_GND
FBCAL_TERM

FB_VDDQ_SENSE <89>

1 2

RG67 40.2_0402_1%

1 2

RG68 40.2_0402_1%

1 2

RG69 60.4_0402_1%

CSSN_NVVDD<85>

CSSP_NVVDD<85>
CSSN_NVVDDS<87>

CSSP_NVVDDS<87>

+1.35VSDGPU

1 2

CSSN_B+<85>

RG59

2

10_0402_1%

RG62
10_0402_1%

1 2

CSSP_B+<85>

1 2

RG64
10_0402_1%

RG66
10_0402_1%

1 2
1 2

RG138
10_0402_1%

RG137
10_0402_1%

1 2

CG62

1

VIN1N
VIN1P

10U_0603_6.3V6M

VIN2N
VIN2P

2

VIN3N

CG63

VIN3P

1

10U_0603_6.3V6M

2

CG183

1

10U_0603_6.3V6M

3VSDGPU_EN<38>

DGPU_PWR_EN<2 2,38,41,53,57>

RG784 0_040 2_5%

RG779 0_0 402_5%

RG799

1 2

@

1 2

+1.35VS_VGA_PGOOD<89>

12

665K_0402_1%

10K_0402_5%

12

RG800

665K_0402_1%

+1.8VSDGPU_MAIN

RG515

12

RG801

665K_0402_1%

12

@

1U_0402_6.3V6K

1

2

1V8_AON_EN_R1

0.1U_0402_16V7K
CG240

Place under GPU

22uF 10 uF 4.7uF 1uF 0.1uF470uF

BK45

VDD_SENSE

BL45

GND_SENSE

N17E-G1_BGA2152~D@

Place under GPU

1

1

1

1

1

CG18610U_0 603_6.3V6M

CG18710U_0 603_6.3V6M

CG18510U_0 603_6.3V6M

CG18410U_0 603_6.3V6M

2

2

2

A A

2

1

1

1

CG18810U_0 603_6.3V6M

CG19110U_0 603_6.3V6M

CG19010U_0 603_6.3V6M

CG18910U_0 603_6.3V6M

2

2

2

2

1

CG1921U_0402_6.3V4Z

2

NVVDD_VCC_SENSE <84>
NVVDD_VSS_SENSE <84>

1

1

CG1941U_0402_6.3V4Z

CG1931U_0402_6.3V4Z

2

2

FBVDDQ

+1.35VSDGPU+1.35VSDGPU

1

1

1

1

1

CG1961U_0402_6.3V4Z

CG1951U_0402_6.3V4Z

CG1971U_0402_6.3V4Z

CG1981U_0402_6.3V4Z

2

2

2

2

1

1

1

CG2001U_0402_6.3V4Z

CG2011U_0402_6.3V4Z

CG1991U_0402_6.3V4Z

2

2

2

1

1

1

CG2021U_0402_6.3V4Z

CG2051U_0402_6.3V4Z

CG2041U_0402_6.3V4Z

CG2031U_0402_6.3V4Z

2

2

2

2

1

1

1

1

CG2091U_0402_6.3V4Z

CG2081U_0402_6.3V4Z

CG2061U_0402_6.3V4Z

CG2071U_0402_6.3V4Z

2

2

2

2

1

1

1

1

CG2111U_0402_6.3V4Z

CG2101U_0402_6.3V4Z

2

2

1

1

CG2131U_0402_6.3V4Z

CG2141U_0402_6.3V4Z

CG2151U_0402_6.3V4Z

CG2121U_0402_6.3V4Z

2

2

2

2

1 139 24

Place under GPU

1

CG21610U_0 603_6.3V6M

2

1

1

1

1

CG22022U_0 603_6.3V6M

CG21710U_0 603_6.3V6M

CG21910U_0 603_6.3V6M

CG21810U_0 603_6.3V6M

2

2

2

2

+1.8VS

+1.8VSDGPU_AON

12

12

@

.1U_0402_16V7K

RG71

4.7K_0402_5%

1V8_AON_EN_R

CG864

RG70
10K_0402_5%

1 2

1V8_AON_EN<38>

1

1

1

1

CG22222U_0 603_6.3V6M

CG22322U_0 603_6.3V6M

CG22122U_0 603_6.3V6M

CG22422U_0 603_6.3V6M

2

2

2

2

1

1

1

1

CG22822U_0 603_6.3V6M

CG22622U_0 603_6.3V6M

CG22722U_0 603_6.3V6M

CG22522U_0 603_6.3V6M

2

2

2

2

RG780 0_0 402_5%@

1V8_MAIN_EN<41>

+1.8VS +1.8VSDGPU_AON

1U_0402_6.3V6K

1U_0402_6.3V6K

CG923

CG922

1

1

2

2

1V8_MAIN_EN

+1.8VS

22U_0603_6.3V6M

CG288

12

+1V8_AON / +1V8_MAIN

+1.8VS

+5VS

+1.8VSDGPU_AON

1

2

UG12

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

AOZ1331_SON14_2X3

VOUT1
VOUT1

VOUT2
VOUT2

+1.8VSDGPU_MAIN

10U_0603_6.3V6M

CG290

1

2

+1.8VSDGPU_AON

10U_0603_6.3V6M

CG289

1

2

.1U_0402_16V7K

CG925

1

2

14
13

CG64

12

1 2

CT1
GND
CT2

GPAD

220P_0402_50V8J

11

CG65

10

1 2

220P_0402_50V8J

9
8

15

.1U_0402_16V7K

CG924

1

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

ANDTRADE SECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

ANDTRADE SECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPTAS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHERTHIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHERTHIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHERTHIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BEUSED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT PRIOR WRITTENCONSENT OF COMPALELECTRONICS, INC.

MAY BEUSED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT PRIOR WRITTENCONSENT OF COMPALELECTRONICS, INC.

5

4

3

MAY BEUSED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT PRIOR WRITTENCONSENT OF COMPALELECTRONICS, INC.

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

N17E-G1(4/6) Power

N17E-G1(4/6) Power

N17E-G1(4/6) Power

Size

Size

Size

Document N umber Re v

Document N umber Re v

Document N umber Re v

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

45 10 3Monday, January 09, 2017

45 10 3Monday, January 09, 2017

45 10 3Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

AW14
AW15
AW16
AW17
AW18
AW19
AW20
AW21
AW22
AW23
AW24
AW25
AW26
AW27
AW28
AW29
AW30
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AW39

AW46
AW52

AR20
AR21
AR22
AR23
AR24
AR25
AR26
AR27
AR28
AR29
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AR38
AR39

AR52

AT51
AT52

AU10
AU14
AU15
AU16
AU17
AU18
AU19

AU20
AU21
AU22
AU23
AU24
AU25
AU26
AU27
AU28
AU29
AU30
AU31
AU32
AU33
AU34
AU35
AU36
AU37
AU38
AU39

AU45
AU47
AU49
AU51

AV45

AY10

AY47
AY49
AY51

UG9L

17/23 GND_2/3

GND_238
GND_239
GND_240
GND_241
GND_242
GND_243
GND_244
GND_245
GND_246
GND_247
GND_248
GND_249
GND_250
GND_251
GND_252
GND_253
GND_254
GND_255
GND_256
GND_257

AR4

GND_258
GND_259

AR9

GND_260

AT4

GND_261

AT5

GND_262
GND_263
GND_264

AT8

GND_265
GND_266
GND_267
GND_268
GND_269
GND_270
GND_271
GND_272

AU2

GND_273
GND_274
GND_275
GND_276
GND_277
GND_278
GND_279
GND_280
GND_281
GND_282
GND_283
GND_284
GND_285
GND_286
GND_287
GND_288
GND_289
GND_290
GND_291
GND_292
GND_293

AU4

GND_294
GND_295
GND_296
GND_297
GND_298

AU6

GND_299

AU8

GND_300

AV4

GND_301
GND_302

AV9

GND_303
GND_304
GND_305
GND_306
GND_307
GND_308
GND_309
GND_310
GND_311
GND_312
GND_313
GND_314
GND_315
GND_316
GND_317
GND_318
GND_319
GND_320
GND_321
GND_322
GND_323
GND_324
GND_325
GND_326
GND_327
GND_328
GND_329

AW4

GND_330
GND_331

AW5

GND_332
GND_333

AW8

GND_334
GND_335

AY2

GND_336

AY4

GND_337
GND_338
GND_339
GND_340

AY6

GND_341

AY8

GND_342

B1

GND_343

B10

GND_344

B13

GND_345

B16

GND_346

B19

GND_347

B2

GND_348

B22

GND_349

B25

GND_350

B28

GND_351

B31

GND_352

B34

GND_353

B37

GND_354

B40

GND_355

B43

GND_356

B46

GND_357

B48

GND_358

N17E-G1_BGA2152~D@

GND_361
GND_362
GND_363
GND_364
GND_365
GND_366
GND_367
GND_368
GND_369
GND_370
GND_371
GND_372
GND_373
GND_374
GND_375
GND_376
GND_377
GND_378
GND_379
GND_380
GND_381
GND_382
GND_383
GND_384
GND_385
GND_386
GND_387
GND_388
GND_389
GND_390
GND_391
GND_392
GND_393
GND_394
GND_395
GND_396
GND_397
GND_398
GND_399
GND_400
GND_401
GND_402
GND_403
GND_404
GND_405
GND_406
GND_407
GND_408
GND_409
GND_410
GND_411
GND_412
GND_413
GND_414
GND_415
GND_416
GND_417
GND_418
GND_419
GND_420
GND_421
GND_422
GND_423
GND_424
GND_425
GND_426
GND_427
GND_428
GND_429
GND_430
GND_431
GND_432
GND_433
GND_434
GND_435
GND_436
GND_437
GND_438
GND_439
GND_440
GND_441
GND_442
GND_443
GND_444
GND_445
GND_446
GND_447
GND_448
GND_449
GND_450
GND_451
GND_452
GND_453
GND_454
GND_455
GND_456
GND_457
GND_458
GND_459
GND_460
GND_461
GND_462
GND_463
GND_464
GND_465
GND_466
GND_467
GND_468
GND_469
GND_470
GND_471
GND_472
GND_473
GND_474
GND_475
GND_476
GND_477
GND_478
GND_479
GND_359
GND_360

B52
B7
BA48
BB49
BC13
BC16
BC19
BC2
BC22
BC25
BC28
BC31
BC34
BC37
BC4
BC51
BC6
BC8
BD26
BD29
BD32
BD35
BD38
BD52
BE10
BE13
BE15
BE16
BE18
BE19
BE21
BE22
BE24
BE25
BE27
BE28
BE30
BE31
BE33
BE34
BE36
BE37
BE39
BE40
BF2
BF4
BF41
BF6
BG10
BG13
BG16
BG19
BG22
BG25
BG28
BG31
BG34
BG37
BG40
BG42
BG7
BH15
BH18
BH2
BH21
BH24
BH27
BH30
BH33
BH36
BH39
BH42
BH5
BJ10
BJ12
BJ13
BJ14
BJ15
BJ16
BJ17
BJ18
BJ19
BJ20
BJ21
BJ22
BJ23
BJ24
BJ25
BJ26
BJ27
BJ28
BJ29
BJ30
BJ31
BJ32
BJ33
BJ34
BJ35
BJ36
BJ37
BJ38
BJ39
BJ40
BJ41
BJ42
BJ43
BJ7
BK1
BL1
BL10
BL13
BL16
BL19
BL2
BL22
BL25
BL28
BL31
BL34
B5
B51

AA49
AB10

AB14
AB15
AB16
AB17
AB18
AB19

AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB31
AB32
AB33
AB34
AB35
AB36
AB37
AB38
AB39

AB43
AB45
AB47
AB49
AB51

AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AD39
AD44
AE10

AE43
AE45
AE47
AE49
AE51

AF19
AF20
AF21
AF22
AF23
AF27
AF28
AF29
AF35
AF36
AF37
AF38
AF39
AF45

AG14
AG15
AG16
AG17
AG18
AG24
AG25
AG26

AG30
AG31
AG32
AG33
AG34
AG44
AH10

AH43
AH45
AH47
AH49
AH51

UG9K

16/23 GND_1/3

A2

GND_001

A26

GND_002

A29

GND_003

A3

GND_004

A32

GND_005

A50

GND_006

A51

GND_007
GND_008

AA8

GND_009
GND_010
GND_011
GND_012
GND_013
GND_014
GND_015
GND_016

AB2

GND_017
GND_018
GND_019
GND_020
GND_021
GND_022
GND_023
GND_024
GND_025
GND_026
GND_027
GND_028
GND_029
GND_030
GND_031
GND_032
GND_033
GND_034
GND_035
GND_036
GND_037

AB4

GND_038
GND_039
GND_040
GND_041
GND_042
GND_043

AB6

GND_044

AB8

GND_045
GND_046
GND_047
GND_048
GND_049
GND_050
GND_051
GND_052
GND_053
GND_054
GND_055
GND_056
GND_057
GND_058
GND_059
GND_060
GND_061
GND_062
GND_063
GND_064
GND_065
GND_066
GND_067
GND_068
GND_069
GND_070
GND_071
GND_072
GND_073

AE2

GND_074

AE4

GND_075
GND_076
GND_077
GND_078
GND_079
GND_080

AE6

GND_081

AE8

GND_082

AF1

GND_083
GND_084
GND_085
GND_086
GND_087
GND_088
GND_089
GND_090
GND_091
GND_092
GND_093
GND_094
GND_095
GND_096
GND_097

AF5

GND_098
GND_099
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106

AG3

GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114

AH2

GND_115

AH4

GND_116
GND_117
GND_118
GND_119
GND_120
GND_121

N17E-G1_BGA2152~D@

GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_200
GND_201
GND_202
GND_203
GND_204
GND_205
GND_206
GND_207
GND_208
GND_209
GND_210
GND_211
GND_212
GND_213
GND_214
GND_215
GND_216
GND_217
GND_218
GND_219
GND_220
GND_221
GND_222
GND_223
GND_224
GND_225
GND_226
GND_227
GND_228
GND_229
GND_230
GND_231
GND_232
GND_233
GND_234
GND_235
GND_236
GND_237
GND_480

GND_H
GND_F

AH6
AH8
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ2
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AJ37
AJ38
AJ39
AJ9
AK1
AK44
AK47
AL10
AL14
AL15
AL16
AL17
AL18
AL19
AL2
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AL33
AL34
AL35
AL36
AL37
AL38
AL39
AL4
AL43
AL45
AL47
AL49
AL51
AL6
AL8
AM4
AM9
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AN39
AN4
AN5
AN8
AP10
AP2
AP4
AP43
AP45
AP47
AP49
AP51
AP6
AP8
AR14
AR15
AR16
AR17
AR18
AR19
BL37
BD24
BC24

+NVVDD1 +NVVDD1

UG9I

21/23 NC/1V8

AT9

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10

4.7U_0402_6.3V6M

1V8_AON_1
1V8_AON_2
1V8_AON_3

VDD18_01
VDD18_02
VDD18_03
VDD18_04
VDD18_05
VDD18_06
VDD18_07
VDD18_08
VDD18_09
VDD18_10
VDD18_11
VDD18_12

N17E-G1_BGA2152~D@

0.1U_0201_6.3V6K

1U_0402_6.3V4Z

CG293

CG292

CG291

1

1

2

1

2

2

BA6
BA9

D D

C C

BD14
BE12

BG6
BH6

BJ11

BJ9

BK44

+1.8VSDGP U_AON

1

2

+1.8VSDGP U_AON

BA10
BB14
BC14

+1.8VSDGP U_MAIN

AM10
AM11
AN10
AN11
AR10
AR11
AT10
AT11
AV10
AV11
AW10
AW11

0.1U_0201_6.3V6K
CG294

Under GPU

+1.8VSDGP U_MAIN

4.7U_0402_6.3V6M
CG295

1

1

2

+1.8VSDGP U_MAIN

0.1U_0201_6.3V6K
CG301

1

2

2

1

2

B B

1U_0402_6.3V4Z

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

CG296

CG297

1

1

2

2

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K
CG303

CG302

1

1

2

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

CG298

CG300

CG299

1

1

2

2

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

CG304

1

2

0.1U_0201_6.3V6K

CG306

CG305

CG307

1

1

2

2

AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AA39
AB13
AB40
AC19
AC20
AC21
AC22
AC23
AC30
AC31
AC32
AC33
AC34
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AE31
AE32
AE33
AE34
AE35
AE36
AE37
AE38
AE39

AG13
AG19
AG20
AG21
BG45
BG46
BG47
BG48
BG49
BG50
BG51
BG52
BH44
BH45
BH47
BH48
BH49
BH50
BH51
BH52

BK47
BK48
BK49
BK50
BK51

AF13
AF30
AF31
AF32
AF33
AF34
AF40

BJ44
BJ45
BJ46
BJ47
BJ48
BJ49
BJ50
BJ51
BJ52

UG9F

18/21 VDD_1/2

VDD_001
VDD_002
VDD_003
VDD_004
VDD_005
VDD_006
VDD_007
VDD_008
VDD_009
VDD_010
VDD_011
VDD_012
VDD_013
VDD_014
VDD_015
VDD_016
VDD_017
VDD_018
VDD_019
VDD_020
VDD_021
VDD_022
VDD_023
VDD_024
VDD_025
VDD_026
VDD_027
VDD_028
VDD_029
VDD_030
VDD_031
VDD_032
VDD_033
VDD_034
VDD_035
VDD_036
VDD_037
VDD_038
VDD_039
VDD_040
VDD_041
VDD_042
VDD_043
VDD_044
VDD_045
VDD_046
VDD_047
VDD_048
VDD_049
VDD_050
VDD_051
VDD_052
VDD_053
VDD_054
VDD_055
VDD_056
VDD_057
VDD_058
VDD_059
VDD_060
VDD_061
VDD_062
VDD_063
VDD_064
VDD_065
VDD_066
VDD_067
VDD_068
VDD_069
VDD_070
VDD_071
VDD_072
VDD_073
VDD_074
VDD_075
VDD_256
VDD_257
VDD_258
VDD_259
VDD_260
VDD_261
VDD_262
VDD_263
VDD_264
VDD_265
VDD_266
VDD_267
VDD_268
VDD_269
VDD_270
VDD_271
VDD_272
VDD_273
VDD_274
VDD_275
VDD_276
VDD_277
VDD_278
VDD_279
VDD_280
VDD_281
VDD_282
VDD_283
VDD_284
VDD_285

AG22

VDD_076

AG23

VDD_077

AG40

VDD_078

AH14

VDD_079

AH15

VDD_080

AH16

VDD_081

AH17

VDD_082

AH18

VDD_083

AH19

VDD_084

AH20

VDD_085

AH21

VDD_086

AH22

VDD_087

AH23

VDD_088

AH24

VDD_089

AH25

VDD_090

AH26

VDD_091

AH27

VDD_092

AH28

VDD_093

AH29

VDD_094

AH30

VDD_095

AH31

VDD_096

AH32

VDD_097

AH33

VDD_098

AH34

VDD_099

AH35

VDD_100

AH36

VDD_101

AH37

VDD_102

AH38

VDD_103

AH39

VDD_104

AK19

VDD_105

AK20

VDD_106

AK21

VDD_107

AK22

VDD_108

AK23

VDD_109

AK30

VDD_110

AK31

VDD_111

AK32

VDD_112

AK33

VDD_113

AK34

VDD_114

AL13

VDD_115

AL40

VDD_116

AM14

VDD_117

AM15

VDD_118

AM16

VDD_119

AM17

VDD_120

AM18

VDD_121

AM19

VDD_122

AM20

VDD_123

AM21

VDD_124

AM22

VDD_125

AM23

VDD_126

AM24

VDD_127

AM25

VDD_128

AM26

VDD_129

AM27

VDD_130

AM28

VDD_131

AM29

VDD_132

AM30

VDD_133

AM31

VDD_134

AM32

VDD_135

AM33

VDD_136

AM34

VDD_137

AM35

VDD_138

AM36

VDD_139

AM37

VDD_140

AM38

VDD_141

AM39

VDD_142

AP19

VDD_143

AP20

VDD_144

BK52

VDD_286

BL46

VDD_287

BL47

VDD_288

BL48

VDD_289

BL49

VDD_290

BL50

VDD_291

BL51

VDD_292

BL52

VDD_293

BM47

VDD_294

BM48

VDD_295

BM49

VDD_296

BM50

VDD_297

BM51

VDD_298

N14

VDD_299

N18

VDD_300

N22

VDD_301

N26

VDD_302

N27

VDD_303

N31

VDD_304

N35

VDD_305

N39

VDD_306

P13

VDD_307

P40

VDD_308

R19

VDD_309

R20

VDD_310

R21

VDD_311

R22

VDD_312

R23

VDD_313

R30

VDD_314

R31

VDD_315

R32

VDD_316

R33

VDD_317

R34

VDD_318

U14

VDD_319

U15

VDD_320

N17E-G1_BGA2152~D@

Under GPU

A A

UG9M

22/23 GND_3/3

BL43

GND_482

BL5

GND_483

BL7

GND_484

BM2

GND_485

BM3

GND_486

C1

GND_487

C29

GND_488

C33

GND_489

C5

GND_490

C51

GND_491

C52

GND_492

D10

GND_493

D12

GND_494

D13

GND_495

D16

GND_496

D19

GND_497

D22

GND_498

D24

GND_499

D25

GND_500

D28

GND_501

D30

GND_502

D31

GND_503

D34

GND_504

D37

GND_505

D4

GND_506

D40

GND_507

D43

GND_508

D46

GND_509

D49

GND_510

D7

GND_511

E2

GND_512

E4

GND_513

E48

GND_514

E5

GND_515

E51

GND_516

E8

GND_517

F10

GND_518

F13

GND_519

F16

GND_520

F17

GND_521

F19

GND_522

F21

GND_523

F22

GND_524

F25

GND_525

F28

GND_526

F31

GND_527

F34

GND_528

F35

GND_529

F37

GND_530

F40

GND_531

F43

GND_532

F44

GND_533

F46

GND_534

F52

GND_535

F7

GND_536

G2

GND_537

G38

GND_538

G4

GND_539

G47

GND_540

G49

GND_541

G51

GND_542

G6

GND_543

H1

GND_544

H10

GND_545

H13

GND_546

H16

GND_547

H19

GND_548

H22

GND_549

H25

GND_550

H28

GND_551

H31

GND_552

H34

GND_553

H37

GND_554

H40

GND_555

H43

GND_556

J1

GND_557

J12

GND_558

J17

GND_559

J20

GND_560

J38

GND_561

J49

GND_562

J52

GND_563

K13

GND_564

K16

GND_565

K19

GND_566

K2

GND_567

K22

GND_568

K25

GND_569

K28

GND_570

K31

GND_571

K34

GND_572

K37

GND_573

K4

GND_574

K40

GND_575

K45

GND_576

K47

GND_577

K49

GND_578

K51

GND_579

K6

GND_580

K8

GND_581

M52

GND_582

M6

GND_583

N10

GND_584

N2

GND_585

N4

GND_586

N43

GND_587

N45

GND_588

N47

GND_589

N49

GND_590

N51

GND_591

BL40

GND_481

N17E-G1_BGA2152~D@

GND_592
GND_593
GND_594
GND_595
GND_596
GND_597
GND_598
GND_599
GND_600
GND_601
GND_602
GND_603
GND_604
GND_605
GND_606
GND_607
GND_608
GND_609
GND_610
GND_611
GND_612
GND_613
GND_614
GND_615
GND_616
GND_617
GND_618
GND_619
GND_620
GND_621
GND_622
GND_623
GND_624
GND_625
GND_626
GND_627
GND_628
GND_629
GND_630
GND_631
GND_632
GND_633
GND_634
GND_635
GND_636
GND_637
GND_638
GND_639
GND_640
GND_641
GND_642
GND_643
GND_644
GND_645
GND_646
GND_647
GND_648
GND_649
GND_650
GND_651
GND_652
GND_653
GND_654
GND_655
GND_656
GND_657
GND_658
GND_659
GND_660
GND_661
GND_662
GND_663
GND_664
GND_665
GND_666
GND_667
GND_668
GND_669
GND_670
GND_671
GND_672
GND_673
GND_674
GND_675
GND_676
GND_677
GND_678
GND_679
GND_680
GND_681
GND_682
GND_683
GND_684
GND_685
GND_686
GND_687
GND_688
GND_689
GND_690
GND_691
GND_692
GND_693

N6
N8
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P51
R49
R52
T10
T14
T15
T16
T17
T18
T19
T2
T20
T21
T22
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
T33
T34
T35
T36
T37
T38
T39
T4
T43
T45
T47
T49
T51
T6
T8
U7
U9
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
V31
V32
V33
V34
V35
V36
V37
V38
V39
V49
V52
W10
W2
W4
W43
W45

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

5

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

N17E-G1(5/6) Power,GND-M

N17E-G1(5/6) Power,GND-M

N17E-G1(5/6) Power,GND-M

Document Number Re v

Document Number Re v

Document Number Re v

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

46 103Monday, January 09, 2017

46 103Monday, January 09, 2017

46 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

+1.8VSDGPU_AON

UG9T

15/23 MISC 2

BL3

STRAP0

BL4

STRAP1

BM4

STRAP2

BM5

STRAP3

BK5

STRAP4

BJ5

STRAP5

N17E-G1_BGA2152~D@

ROM_CS*

ROM_SI

ROM_SO

ROM_SCLK

BUFRST*

BJ4
BK2

BK4
BK3

BF9

ROM_CS#
ROM_SI

ROM_SO
ROM_SCLK

GPU_BUFRST#

@

T63
PAD~D

@

RG84
100K_0402_1%

1 2

RG87
100K_0402_1%

1 2

1 2

1 2

1

4.7uF10uF22uF 0.1uF1uF

RG78
100K_0402_1%

11

1 2

@

STRAP0

6

RG90
100K_0402_1%

1 2

RG79
100K_0402_1%

1 2

@

RG91
100K_0402_1%

1 2

STRAP1

RG80
100K_0402_1%

1 2

@

RG92
100K_0402_1%

1 2

STRAP2

RG81
100K_0402_1%

1 2

RG93

@

100K_0402_1%

1 2

STRAP3

RG82
100K_0402_1%

1 2

@

RG94
100K_0402_1%

1 2

STRAP4

RG83
100K_0402_1%

1 2

RG95
100K_0402_1%

1 2

@

STRAP5

47uF

D D

VID_PLLVDD

SP_PLLVDD
GPCPLL_AVDD

1

MICRON

@

RG85
100K_0402_1%

RG88
100K_0402_1%

+1.8VSDGPU_AON

@

RG86
100K_0402_1%

1 2

RG89
100K_0402_1%

1 2

MT58K256M32 - 100:A

Strap 0 Stra p1 Stra p2 Strap3 Strap4 Strap5 ROM_SO ROM_ SI ROM_SC LK

PD

PD

PD

1 2

LG4
PBY160808T-301Y-N

CG239

1

2

.1U_0402_16V7K

CG238

PD

100kOhm

PD

100kOhm

.1U_0402_16V7K

CG237

1

2

1

2

100kOhm

100kOhm

.1U_0402_16V7K

CG236

aster

M

v

Sl

ave

x

C C

+1.8VSDGPU_MAIN

1 2

B B

100kOhm

PD

100kOhm

LG3
PBY160808T-300Y-N_2P

100kOhm

100kOhm

+1.8VSDGPU_MAIN

22U_0603_6.3V6M

12

Under GPU

PD

PU

100kOhm

PD

PD

100kOhm

Under GPU

47U_0805_6.3V6M~D

12

.1U_0402_16V7K

1

2

.1U_0402_16V7K

10U_0603_6.3V6M

CG232

CG231

1

1

2

2

.1U_0402_16V7K

.1U_0402_16V7K

CG235

CG234

1

1

2

2

12

RG101
10K_0402_5%

CG230

CG233

PD

UG9S

U42

BJ6
BL6

PD

100kOhm

PU

100kOhm

14/23 XTAL/PLL

SP_PLLVDD
VID_PLLVDD

GPCPLL_AVDD0
GPCPLL_AVDD1
XS_PLLVDD

XTAL_SSIN
XTAL_IN

1

1 2

YG1

1

GND

RG99
10M_0402_5%

2

PU

100kOhm

100kOhm

100kOhm

100kOhm

PU

PU

PD

100kOhm

BD12
BC12

AF11
BB24

XTALIN XTALOUT

CG75
22P_0402_50V8J

PD

100kOhm

PU

100kOhm

PD

100kOhm

XTAL_OUTBUFF

XTAL_OUT

N17E-G1_BGA2152~D@

3

3

GND

4

27MHZ_16PF_7V27000011

BK6
BM6

XTALOUTBUFF_R

CG76
22P_0402_50V8J

12

RG98
10K_0402_5%

ROM_CS#

1 2

RG76 0_0402_5%

RG74
10K_0402_5%

DGPU_ROM_SO_RROM_SO

+1.8VSDGPU_AON

12

UG13

1

CS#

2

DO(IO1)

3

WP#(IO2)

4

GND

W25Q80EW SSIG_SO8

VCC

HOLD#(IO3)

DI(IO0)

CLK

DGPU VBIOS ROM 8M

+1.8VSDGPU_AON

8
7

DGPU_ROM_SCLK

6

DGPU_ROM_SI

5

1

CG66
.1U_0402_16V7K

2

1 2
1 2

RG75
33_0402_5%

RG77
33_0402_5%

ROM_SCLK
ROM_SI

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

N17E-G1(6/6) Strap Pin,ROM-M

N17E-G1(6/6) Strap Pin,ROM-M

N17E-G1(6/6) Strap Pin,ROM-M

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

47 103Monday, January 09, 2017

47 103Monday, January 09, 2017

47 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

UG9V

11/23 MIOA

D D

.1U_0402_16V7K

C C

B B

.1U_0402_16V7K

1K_0402_1%

CG569

1K_0402_1%

CG904

+1.8VSDGPU_MAIN

12

RG682

12

1

2

+1.8VSDGPU_MAIN

12

RG759

12

1

2

+1.8VSDGPU_MAIN

49.9_0402_1%

1 2
1 2

+MIOA_VREF

RG683
1K_0402_1%

+1.8VSDGPU_MAIN

49.9_0402_1%

1 2
1 2

+MIOB_VREF

RG761
1K_0402_1%

RG680

RG681

49.9_0402_1%

RG760

RG762

49.9_0402_1%

12mils

+MIOA_VDDQ

MIOA_GND

12mils

+MIOB_VDDQ

MIOB_GND

AM5

MIOA_CAL_PD_VDDQ

AM6

MIOA_CAL_PU_GND

AM7

MIOA_VREF

UG9U

12/23 MIOB

AV7

MIOB_CAL_PD_VDDQ

AV8

MIOB_CAL_PU_GND

AW9

MIOB_VREF

MIOA_CTL3
MIOA_HSYNC
MIOA_VSYNC

MIOA_CLKOUT

MIOA_CLKIN

N17E-G1_BGA2152~D@

MIOB_CTL3
MIOB_HSYNC
MIOB_VSYNC

GP106GP104

UNUSEDMIOB

MIOB_CLKOUT

MIOB_CLKIN

N17E-G1_BGA2152~D@

MIOA_D0
MIOA_D1
MIOA_D2
MIOA_D3
MIOA_D4
MIOA_D5
MIOA_D6
MIOA_D7
MIOA_D8

MIOA_D9
MIOA_D10
MIOA_D11

MIOA_DE

MIOB_D0

MIOB_D1

MIOB_D2

MIOB_D3

MIOB_D4

MIOB_D5

MIOB_D6

MIOB_D7

MIOB_D8

MIOB_D9
MIOB_D10
MIOB_D11

MIOB_DE

AN9
AM2
AN7
AN6
AR1
AR6
AR5
AM8
AN3
AR8
AR3
AR2

AT7
AM1
AR7
AN1

AN2
AM3

AT3
AV6
AT2
AT1
AW6
AV2
AV1
AV3
AW3
BA8
AW7
BB8

BB7
AV5
BA7
AW2

AW1
AT6

20160201_Update Net Name

MIOA_D0 <60>
MIOA_D1 <60>
MIOA_D2 <60>
MIOA_D3 <60>
MIOA_D4 <60>
MIOA_D5 <60>
MIOA_D6 <60>
MIOA_D7 <60>
MIOA_D8 <60>
MIOA_D9 <60>
MIOA_D10 <60>
MIOA_D11 <60>

MIOA_CTL3 <60>
MIOA_HSYNC <60>
MIOA_VSYNC <60>
MIOA_DE <60>

MIOA_CLKOUT_S_TO_M <60>

MIOA_CLKIN_M_TO_S <60>

Slave drives these clocks to the Master to latch the rasterized data

Output of the Master and input to the Slave

A A

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2016/02/01 2017/12/31

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N17E-G1(1/6) PCIE,GPIO

N17E-G1(1/6) PCIE,GPIO

N17E-G1(1/6) PCIE,GPIO

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

1.0

1.0

1.0

48 103Monday, January 09, 2017

48 103Monday, January 09, 2017

48 103Monday, January 09, 2017

5

0-15 FUNCT ION

16-3 1

CMD0

CMD16
CMD17
CMD18

CMD3

CMD19

CMD4 A0_A10

CMD20

CMD5 A12_A13

CMD21

CMD6

CMD22

CMD7

CMD23

CMD8

CMD24

CMD9

D D

C C

B B

CMD25

CMD10

CMD26

CMD11

CMD27

CMD12

CMD28

CMD13 CKE#

CMD29

CMD14

CMD30

CMD15

CMD31 WE#

MEM_VREF<41 ,50,51,52>

CAS#
RST#CMD1
RAS#CMD2

A1_A9

ABI#

A6_A11

A7_A8

A4_BA2
A5_BA1
A3_BA3
A2_BA0

A14_A15

2

G

1

3

1 2

RG111
931_0402_1%

D

QG2

S

MESS138W-G_SOT 323-3

FBA_EDC3<44>
FBA_EDC2<44>
FBA_EDC1<44>
FBA_EDC0<44>

FBA_DBI3<44>
FBA_DBI2<44>
FBA_DBI1<44>

+1.35VSDGPU

CG79

820P_0402_25V7

FBA_DBI0<44>

FBA_CMD15<44>

FBA_CMD9<44>
FBA_CMD11<44>
FBA_CMD12<44>
FBA_CMD10<44>

FBA_CMD4<44>
FBA_CMD7<44>
FBA_CMD8<44>
FBA_CMD3<44>
FBA_CMD5<44>
FBA_CMD14<44>

12

RG104 1K_0402 _1%

12

RG108 121_040 2_1%

FBA_CMD6<44>
FBA_CMD0<44>
FBA_CMD2<44>
FBA_CMD13<44>

FBA_WCK23#<44 >
FBA_WCK23<44>

FBA_WCK01#<44 >
FBA_WCK01<44>

FBA_CMD1<44>

+1.35VSDGPU

FBA_CLK0<44>
FBA_CLK0#<44> FBA_CLK1#<44>

+1.35VSDGPU

12

RG110
549_0402_1%

+FBA_VREFC

W=16mils

12

1

1

CG78

RG112

2

2

1.33K_0402_1%

820P_0402_25V7

UG1

MF=0 MF=1 MF= 0MF=1

D3

EDC0 EDC3

D12

EDC1 EDC2

T12

EDC2 EDC1

T3

EDC3 EDC0

E3

DBI0# DBI3#

E12

DBI1# DBI2#

R12

DBI2# DBI1#

R3

DBI3# DBI0#

K11

CK

K10

CK#

H11

CKE# WE#

J11

BA0/A2 BA2/A4

L10

BA1/A5 BA3/A3

L11

BA2/A4 BA0/A2

J10

BA3/A3 BA1/A5

L4

A8/A7 A10/A0

J5

A9/A1 A11/A6

J4

A10/A0 A8/A7

L5

A11/A6 A9/A1

K5

A12/A13

K12

A14/A15

W12

MF

H13

ZQ

M2

TCK

M13

TDI

A12

TDO

H2

TMS

K4

ABI#

H4

RAS# CAS#

M4

CAS# RAS#

M11

WE# CKE#

D5

WCK01# WCK23#

D4

WCK01 WCK23

T5

WCK23# WCK01#

T4

WCK23 WCK01

K13

VREFC

K2

RESET#

A10

VSS_1

A5

VSS_2

B1

VSS_3

B14

VSS_4

D1

VSS_5

D11

VSS_6

D14

VSS_7

F1

VSS_8

F14

VSS_9

H1

VSS_10

H14

VSS_11

J12

VSS_12

J3

VSS_13

K1

VSS_14

K14

VSS_15

K3

VSS_16

L12

VSS_17

L3

VSS_18

M1

VSS_19

M14

VSS_20

P1

VSS_21

P14

VSS_22

T1

VSS_23

T11

VSS_24

T14

VSS_25

V1

VSS_26

V14

VSS_27

W10

VSS_28

W5

VSS_29

A1

VDD_1

A11

VDD_2

A14

VDD_3

A4

VDD_4

D10

VDD_5

G1

VDD_6

G14

VDD_7

H10

VDD_8

H5

VDD_9

J1

VDD_10

J14

VDD_11

L1

VDD_12

L14

VDD_13

M10

VDD_14

M5

VDD_15

N1

VDD_16

N14

VDD_17

T10

VDD_18

W1

VDD_19

W11

VDD_20

W14

VDD_21

W4

SGRAM GDDR5X

VDD_22

4

190-BAL L

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ9 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

MICRON_GDDR5X

3

UG2

B4
B3
C4
C3
F4
F3
G4
G3
B11
B12
C11
C12
F11
F12
G11
G12
V11
V12
U11
U12
P11
P12
N11
N12
V4
V3
U4
U3
P4
P3
N4
N3

A13

VDDQ_1

A2

VDDQ_2

B10

VDDQ_3

B5

VDDQ_4

C1

VDDQ_5

C13

VDDQ_6

C14

VDDQ_7

C2

VDDQ_8

E1

VDDQ_9

E11

VDDQ_10

E13

VDDQ_11

E14

VDDQ_12

E2

VDDQ_13

E4

VDDQ_14

F10

VDDQ_15

F5

VDDQ_16

G13

VDDQ_17

G2

VDDQ_18

H12

VDDQ_19

H3

VDDQ_20

J13

VDDQ_21

J2

VDDQ_22

L13

VDDQ_23

L2

VDDQ_24

M12

VDDQ_25

M3

VDDQ_26

N13

VDDQ_27

N2

VDDQ_28

P10

VDDQ_29

P5

VDDQ_30

R1

VDDQ_31

R11

VDDQ_32

R13

VDDQ_33

R14

VDDQ_34

R2

VDDQ_35

R4

VDDQ_36

U1

VDDQ_37

U13

VDDQ_38

U14

VDDQ_39

U2

VDDQ_40

V10

VDDQ_41

V5

VDDQ_42

W13

VDDQ_43

W2

VDDQ_44

B13

VSSQ_1

B2

VSSQ_2

C10

VSSQ_3

C5

VSSQ_4

D13

VSSQ_5

D2

VSSQ_6

E10

VSSQ_7

E5

VSSQ_8

F13

VSSQ_9

F2

VSSQ_10

G10

VSSQ_11

G5

VSSQ_12

N10

VSSQ_13

N5

VSSQ_14

P13

VSSQ_15

P2

VSSQ_16

R10

VSSQ_17

R5

VSSQ_18

T13

VSSQ_19

T2

VSSQ_20

U10

VSSQ_21

U5

VSSQ_22

V13

VSSQ_23

V2

VSSQ_24

A3

VPP_1

W3

VPP_2

+1.35VSDGPU

+1.8VSDGPU_AON

FBA_D24 <44>
FBA_D25 <44>
FBA_D26 <44>
FBA_D27 <44>
FBA_D28 <44>
FBA_D29 <44>
FBA_D30 <44>
FBA_D31 <44>
FBA_D16 <44>
FBA_D17 <44>
FBA_D18 <44>
FBA_D19 <44>
FBA_D20 <44>
FBA_D21 <44>
FBA_D22 <44>
FBA_D23 <44>
FBA_D8 <44>
FBA_D9 <44>
FBA_D10 <44>
FBA_D11 <44>
FBA_D12 <44>
FBA_D13 <44>
FBA_D14 <44>
FBA_D15 <44>
FBA_D0 <44>
FBA_D1 <44>
FBA_D2 <44>
FBA_D3 <44>
FBA_D4 <44>
FBA_D5 <44>
FBA_D6 <44>
FBA_D7 <44>

FBA_CLK1<44>

FBA_EDC4<44 >
FBA_EDC5<44 >
FBA_EDC6<44 >
FBA_EDC7<44 >

FBA_DBI4<44>
FBA_DBI5<44>
FBA_DBI6<44>
FBA_DBI7<44>

FBA_CMD29<44>

FBA_CMD28<44>
FBA_CMD26<44>
FBA_CMD25<44>
FBA_CMD27<44>

FBA_CMD24<44>
FBA_CMD19<44>
FBA_CMD20<44>
FBA_CMD23<44>
FBA_CMD21<44>
FBA_CMD30<44>

12

RG136 1K_0402 _1%

12

RG140 121_040 2_1%

FBA_CMD22<44>
FBA_CMD18<44>
FBA_CMD16<44>
FBA_CMD31<44>

FBA_WCK45#<44>
FBA_WCK45<44>

FBA_WCK67#<44>
FBA_WCK67<44>

+FBA_VREFC+FBA_VREFC

FBA_CMD17<44>

+1.35VSDGPU

MF=0 MF=1 MF= 0MF=1

D3

EDC0 EDC3

D12

EDC1 EDC2

T12

EDC2 EDC1

T3

EDC3 EDC0

E3

DBI0# DBI3#

E12

DBI1# DBI2#

R12

DBI2# DBI1#

R3

DBI3# DBI0#

K11

CK

K10

CK#

H11

CKE# WE#

J11

BA0/A2 BA2/A4

L10

BA1/A5 BA3/A3

L11

BA2/A4 BA0/A2

J10

BA3/A3 BA1/A5

L4

A8/A7 A10/A0

J5

A9/A1 A11/A6

J4

A10/A0 A8/A7

L5

A11/A6 A9/A1

K5

A12/A13

K12

A14/A15

W12

MF

H13

ZQ

M2

TCK

M13

TDI

A12

TDO

H2

TMS

K4

ABI#

H4

RAS# CAS#

M4

CAS# RAS#

M11

WE# CKE#

D5

WCK01# WCK23#

D4

WCK01 WCK23

T5

WCK23# WCK01#

T4

WCK23 WCK01

K13

VREFC

K2

RESET#

A10

VSS_1

A5

VSS_2

B1

VSS_3

B14

VSS_4

D1

VSS_5

D11

VSS_6

D14

VSS_7

F1

VSS_8

F14

VSS_9

H1

VSS_10

H14

VSS_11

J12

VSS_12

J3

VSS_13

K1

VSS_14

K14

VSS_15

K3

VSS_16

L12

VSS_17

L3

VSS_18

M1

VSS_19

M14

VSS_20

P1

VSS_21

P14

VSS_22

T1

VSS_23

T11

VSS_24

T14

VSS_25

V1

VSS_26

V14

VSS_27

W10

VSS_28

W5

VSS_29

A1

VDD_1

A11

VDD_2

A14

VDD_3

A4

VDD_4

D10

VDD_5

G1

VDD_6

G14

VDD_7

H10

VDD_8

H5

VDD_9

J1

VDD_10

J14

VDD_11

L1

VDD_12

L14

VDD_13

M10

VDD_14

M5

VDD_15

N1

VDD_16

N14

VDD_17

T10

VDD_18

W1

VDD_19

W11

VDD_20

W14

VDD_21

W4

SGRAM GDDR5X

VDD_22

190-BAL L

MF=0MF=1

2

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ9 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

MICRON_GDDR5X

1

B4
B3
C4
C3
F4
F3
G4
G3
B11
B12
C11
C12
F11
F12
G11
G12
V11
V12
U11
U12
P11
P12
N11
N12
V4
V3
U4
U3
P4
P3
N4
N3

A13

VDDQ_1

A2

VDDQ_2

B10

VDDQ_3

B5

VDDQ_4

C1

VDDQ_5

C13

VDDQ_6

C14

VDDQ_7

C2

VDDQ_8

E1

VDDQ_9

E11

VDDQ_10

E13

VDDQ_11

E14

VDDQ_12

E2

VDDQ_13

E4

VDDQ_14

F10

VDDQ_15

F5

VDDQ_16

G13

VDDQ_17

G2

VDDQ_18

H12

VDDQ_19

H3

VDDQ_20

J13

VDDQ_21

J2

VDDQ_22

L13

VDDQ_23

L2

VDDQ_24

M12

VDDQ_25

M3

VDDQ_26

N13

VDDQ_27

N2

VDDQ_28

P10

VDDQ_29

P5

VDDQ_30

R1

VDDQ_31

R11

VDDQ_32

R13

VDDQ_33

R14

VDDQ_34

R2

VDDQ_35

R4

VDDQ_36

U1

VDDQ_37

U13

VDDQ_38

U14

VDDQ_39

U2

VDDQ_40

V10

VDDQ_41

V5

VDDQ_42

W13

VDDQ_43

W2

VDDQ_44

B13

VSSQ_1

B2

VSSQ_2

C10

VSSQ_3

C5

VSSQ_4

D13

VSSQ_5

D2

VSSQ_6

E10

VSSQ_7

E5

VSSQ_8

F13

VSSQ_9

F2

VSSQ_10

G10

VSSQ_11

G5

VSSQ_12

N10

VSSQ_13

N5

VSSQ_14

P13

VSSQ_15

P2

VSSQ_16

R10

VSSQ_17

R5

VSSQ_18

T13

VSSQ_19

T2

VSSQ_20

U10

VSSQ_21

U5

VSSQ_22

V13

VSSQ_23

V2

VSSQ_24

A3

VPP_1

W3

VPP_2

+1.35VSDGPU

+1.8VSDGPU_AON

FBA_D32 <44>
FBA_D33 <44>
FBA_D34 <44>
FBA_D35 <44>
FBA_D36 <44>
FBA_D37 <44>
FBA_D38 <44>
FBA_D39 <44>
FBA_D40 <44>
FBA_D41 <44>
FBA_D42 <44>
FBA_D43 <44>
FBA_D44 <44>
FBA_D45 <44>
FBA_D46 <44>
FBA_D47 <44>
FBA_D48 <44>
FBA_D49 <44>
FBA_D50 <44>
FBA_D51 <44>
FBA_D52 <44>
FBA_D53 <44>
FBA_D54 <44>
FBA_D55 <44>
FBA_D56 <44>
FBA_D57 <44>
FBA_D58 <44>
FBA_D59 <44>
FBA_D60 <44>
FBA_D61 <44>
FBA_D62 <44>
FBA_D63 <44>

Under VRAM

+1.35VSDGPU +1.35VSDGPU +1.35VSDGPU

1

1

1

1

CG891U_0402_6.3V4Z

CG871U_0402_6.3V4Z

CG861U_0402_6.3V4Z

CG881U_0402_6.3V4Z

2

2

2

2

+1.8VSDGPU_AON

A A

Under VRAM

1

CG92

2

.1U_0402_16V7K

1

1

CG911U_0402_6.3V4Z

CG901U_0402_6.3V4Z

CG1041U_0402_6.3V4Z

CG1031U_0402_6.3V4Z

2

2

2

2

1

1

CG93

CG873

CG308

2

2

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

5

1

1

1

1

1

1

CG7921U_0402_6.3V4Z

CG7911U_0402_6.3V4Z

CG1061U_0402_6.3V4Z

CG1051U_0402_6.3V4Z

2

2

2

2

1

2

Under VRAM

1

1

1

CG5781U_0402_6.3V4Z

CG5771U_0402_6.3V4Z

CG5791U_0402_6.3V4Z

2

2

2

Near VRAM

1

1

1

CG5751U_0402_6.3V4Z

2

1

1

CG5741U_0402_6.3V4Z

CG5761U_0402_6.3V4Z

CG5731U_0402_6.3V4Z

CG5801U_0402_6.3V4Z

2

2

2

2

1

1

CG8410U_0402_6.3V4Z

CG8310U_0402_6.3V4Z

2

2

4

1

1

1

1

CG8510U_0402_6.3V4Z

CG10210U_0402_6.3V4Z

CG10010U_0402_6.3V4Z

CG10110U_0402_6.3V4Z

2

2

2

2

1

1

1

1

CG79010U_0402_6.3V4Z

CG78810U_0402_6.3V4Z

CG78910U_0402_6.3V4Z

CG78710U_0402_6.3V4Z

2

2

2

2

+1.35VSDGPU

Near VRAM

1

1

1

CG8222U_0603_6.3V6M

CG8022U_0603_6.3V6M

CG8122U_0603_6.3V6M

2

2

2

1

CG9822U_0603_6.3V6M

2

1

1

1

1

CG9722U_0603_6.3V6M

CG79322U_0603_6.3V6M

CG78522U_0603_6.3V6M

CG78622U_0603_6.3V6M

2

2

2

2

3

VDD

VDDQ

4 5

4 5

12

8

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

N17E-GDDR5_A-M

N17E-GDDR5_A-M

N17E-GDDR5_A-M

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

49 103Monday, January 09, 2017

49 103Monday, January 09, 2017

49 103Monday, January 09, 2017

22uF 10uF 4.7uF 1uF 0.1uF

1.0

1.0

1.0

5

FBB_EDC3<44 >
FBB_EDC2<44 >
FBB_EDC1<44 >
FBB_EDC0<44 >

FBB_DBI3<44>
FBB_DBI2<44>
FBB_DBI1<44>

FBB_CLK0<44>

12

12

RG121
549_0402_1%

RG123

1.33K_0402_1%

+FBB_VREFC

1

CG113

2

820P_0402_25V7

FBB_CLK0#<44 >

W=16mils

1

CG114

2

820P_0402_25V7

D D

C C

+1.35VSDGPU

1 2

RG122
931_0402_1%

1

D

MEM_VREF<41 ,49,51,52>

B B

2

G

3

QG3

S

MESS138W-G_SOT 323-3

FBB_DBI0<44>

FBB_CMD15<44>

FBB_CMD9<44>
FBB_CMD11<44>
FBB_CMD12<44>
FBB_CMD10<44>

FBB_CMD4<44>
FBB_CMD7<44>
FBB_CMD8<44>
FBB_CMD3<44>
FBB_CMD5<44>

+1.35VSDGPU

FBB_CMD14<44>

RG115 1K_04 02_1%
RG119 121_0 402_1%

FBB_CMD6<44>
FBB_CMD0<44>
FBB_CMD2<44>
FBB_CMD13<44>

FBB_WCK23#<44>
FBB_WCK23<44>

FBB_WCK01#<44>
FBB_WCK01<44>

FBB_CMD1<44>

12
12

+1.35VSDGPU

+FBB_VREFC

4

UG3

MF=0 MF=1 MF= 0MF=1

D3

EDC0 EDC3

D12

EDC1 EDC2

T12

EDC2 EDC1

T3

EDC3 EDC0

E3

DBI0# DBI3#

E12

DBI1# DBI2#

R12

DBI2# DBI1#

R3

DBI3# DBI0#

K11

CK

K10

CK#

H11

CKE# WE#

J11

BA0/A2 BA2/A4

L10

BA1/A5 BA3/A3

L11

BA2/A4 BA0/A2

J10

BA3/A3 BA1/A5

L4

A8/A7 A10/A0

J5

A9/A1 A11/A6

J4

A10/A0 A8/A7

L5

A11/A6 A9/A1

K5

A12/A13

K12

A14/A15

W12

MF

H13

ZQ

M2

TCK

M13

TDI

A12

TDO

H2

TMS

K4

ABI#

H4

RAS# CAS#

M4

CAS# RAS#

M11

WE# CKE#

D5

WCK01# WCK23#

D4

WCK01 WCK23

T5

WCK23# WCK01#

T4

WCK23 WCK01

K13

VREFC

K2

RESET#

A10

VSS_1

A5

VSS_2

B1

VSS_3

B14

VSS_4

D1

VSS_5

D11

VSS_6

D14

VSS_7

F1

VSS_8

F14

VSS_9

H1

VSS_10

H14

VSS_11

J12

VSS_12

J3

VSS_13

K1

VSS_14

K14

VSS_15

K3

VSS_16

L12

VSS_17

L3

VSS_18

M1

VSS_19

M14

VSS_20

P1

VSS_21

P14

VSS_22

T1

VSS_23

T11

VSS_24

T14

VSS_25

V1

VSS_26

V14

VSS_27

W10

VSS_28

W5

VSS_29

A1

VDD_1

A11

VDD_2

A14

VDD_3

A4

VDD_4

D10

VDD_5

G1

VDD_6

G14

VDD_7

H10

VDD_8

H5

VDD_9

J1

VDD_10

J14

VDD_11

L1

VDD_12

L14

VDD_13

M10

VDD_14

M5

VDD_15

N1

VDD_16

N14

VDD_17

T10

VDD_18

W1

VDD_19

W11

VDD_20

W14

VDD_21

W4

SGRAM GDDR5X

VDD_22

190-BAL L

MF=1

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15

DQ9 DQ16

DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23

DQ0 DQ24

DQ1 DQ25

DQ2 DQ26

DQ3 DQ27

DQ4 DQ28

DQ5 DQ29

DQ6 DQ30

DQ7 DQ31

MICRON_GDDR5X

3

B4
B3
C4
C3
F4
F3
G4
G3
B11
B12
C11
C12
F11
F12
G11
G12
V11
V12
U11
U12
P11
P12
N11
N12
V4
V3
U4
U3
P4
P3
N4
N3

A13

VDDQ_1

A2

VDDQ_2

B10

VDDQ_3

B5

VDDQ_4

C1

VDDQ_5

C13

VDDQ_6

C14

VDDQ_7

C2

VDDQ_8

E1

VDDQ_9

E11

VDDQ_10

E13

VDDQ_11

E14

VDDQ_12

E2

VDDQ_13

E4

VDDQ_14

F10

VDDQ_15

F5

VDDQ_16

G13

VDDQ_17

G2

VDDQ_18

H12

VDDQ_19

H3

VDDQ_20

J13

VDDQ_21

J2

VDDQ_22

L13

VDDQ_23

L2

VDDQ_24

M12

VDDQ_25

M3

VDDQ_26

N13

VDDQ_27

N2

VDDQ_28

P10

VDDQ_29

P5

VDDQ_30

R1

VDDQ_31

R11

VDDQ_32

R13

VDDQ_33

R14

VDDQ_34

R2

VDDQ_35

R4

VDDQ_36

U1

VDDQ_37

U13

VDDQ_38

U14

VDDQ_39

U2

VDDQ_40

V10

VDDQ_41

V5

VDDQ_42

W13

VDDQ_43

W2

VDDQ_44

B13

VSSQ_1

B2

VSSQ_2

C10

VSSQ_3

C5

VSSQ_4

D13

VSSQ_5

D2

VSSQ_6

E10

VSSQ_7

E5

VSSQ_8

F13

VSSQ_9

F2

VSSQ_10

G10

VSSQ_11

G5

VSSQ_12

N10

VSSQ_13

N5

VSSQ_14

P13

VSSQ_15

P2

VSSQ_16

R10

VSSQ_17

R5

VSSQ_18

T13

VSSQ_19

T2

VSSQ_20

U10

VSSQ_21

U5

VSSQ_22

V13

VSSQ_23

V2

VSSQ_24

A3

VPP_1

W3

VPP_2

+1.35VSDGPU

+1.8VSDGPU_AON

FBB_D24 <44>
FBB_D25 <44>
FBB_D26 <44>
FBB_D27 <44>
FBB_D28 <44>
FBB_D29 <44>
FBB_D30 <44>
FBB_D31 <44>
FBB_D16 <44>
FBB_D17 <44>
FBB_D18 <44>
FBB_D19 <44>
FBB_D20 <44>
FBB_D21 <44>
FBB_D22 <44>
FBB_D23 <44>
FBB_D8 <44>
FBB_D9 <44>
FBB_D10 <44>
FBB_D11 <44>
FBB_D12 <44>
FBB_D13 <44>
FBB_D14 <44>
FBB_D15 <44>
FBB_D0 <44>
FBB_D1 <44>
FBB_D2 <44>
FBB_D3 <44>
FBB_D4 <44>
FBB_D5 <44>
FBB_D6 <44>
FBB_D7 <44>

FBB_CLK1<44>
FBB_CLK1#<44 >

RG116 1K_0402 _1%
RG120 121_040 2_1%

2

MF=0

UG4

MF=0 MF=1 MF= 0MF=1

12
12

+FBB_VREFC

+1.35VSDGPU

D3

EDC0 EDC3

D12

EDC1 EDC2

T12

EDC2 EDC1

T3

EDC3 EDC0

E3

DBI0# DBI3#

E12

DBI1# DBI2#

R12

DBI2# DBI1#

R3

DBI3# DBI0#

K11

CK

K10

CK#

H11

CKE# WE#

J11

BA0/A2 BA2/A4

L10

BA1/A5 BA3/A3

L11

BA2/A4 BA0/A2

J10

BA3/A3 BA1/A5

L4

A8/A7 A10/A0

J5

A9/A1 A11/A6

J4

A10/A0 A8/A7

L5

A11/A6 A9/A1

K5

A12/A13

K12

A14/A15

W12

MF

H13

ZQ

M2

TCK

M13

TDI

A12

TDO

H2

TMS

K4

ABI#

H4

RAS# CAS#

M4

CAS# RAS#

M11

WE# CKE#

D5

WCK01# WCK23#

D4

WCK01 WCK23

T5

WCK23# WCK01#

T4

WCK23 WCK01

K13

VREFC

K2

RESET#

A10

VSS_1

A5

VSS_2

B1

VSS_3

B14

VSS_4

D1

VSS_5

D11

VSS_6

D14

VSS_7

F1

VSS_8

F14

VSS_9

H1

VSS_10

H14

VSS_11

J12

VSS_12

J3

VSS_13

K1

VSS_14

K14

VSS_15

K3

VSS_16

L12

VSS_17

L3

VSS_18

M1

VSS_19

M14

VSS_20

P1

VSS_21

P14

VSS_22

T1

VSS_23

T11

VSS_24

T14

VSS_25

V1

VSS_26

V14

VSS_27

W10

VSS_28

W5

VSS_29

A1

VDD_1

A11

VDD_2

A14

VDD_3

A4

VDD_4

D10

VDD_5

G1

VDD_6

G14

VDD_7

H10

VDD_8

H5

VDD_9

J1

VDD_10

J14

VDD_11

L1

VDD_12

L14

VDD_13

M10

VDD_14

M5

VDD_15

N1

VDD_16

N14

VDD_17

T10

VDD_18

W1

VDD_19

W11

VDD_20

W14

VDD_21

W4

VDD_22

190-BAL L

SGRAM GDDR5X

MICRON_GDDR5X

FBB_EDC4<44>
FBB_EDC5<44>
FBB_EDC6<44>
FBB_EDC7<44>

FBB_DBI4<44>
FBB_DBI5<44>
FBB_DBI6<44>
FBB_DBI7<44>

FBB_CMD29<44>

FBB_CMD28<44>
FBB_CMD26<44>
FBB_CMD25<44>
FBB_CMD27<44>

FBB_CMD24<44>
FBB_CMD19<44>
FBB_CMD20<44>
FBB_CMD23<44>
FBB_CMD21<44>
FBB_CMD30<44>

FBB_CMD22<44>
FBB_CMD18<44>
FBB_CMD16<44>
FBB_CMD31<44>

FBB_WCK45#<44 >
FBB_WCK45<44>

FBB_WCK67#<44 >
FBB_WCK67<44>

FBB_CMD17<44>

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15

DQ9 DQ16

DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23

DQ0 DQ24

DQ1 DQ25

DQ2 DQ26

DQ3 DQ27

DQ4 DQ28

DQ5 DQ29

DQ6 DQ30

DQ7 DQ31

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8

VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
VDDQ_28
VDDQ_29
VDDQ_30
VDDQ_31
VDDQ_32
VDDQ_33
VDDQ_34
VDDQ_35
VDDQ_36
VDDQ_37
VDDQ_38
VDDQ_39
VDDQ_40
VDDQ_41
VDDQ_42
VDDQ_43
VDDQ_44

VSSQ_1

VSSQ_2

VSSQ_3

VSSQ_4

VSSQ_5

VSSQ_6

VSSQ_7

VSSQ_8

VSSQ_9
VSSQ_10
VSSQ_11
VSSQ_12
VSSQ_13
VSSQ_14
VSSQ_15
VSSQ_16
VSSQ_17
VSSQ_18
VSSQ_19
VSSQ_20
VSSQ_21
VSSQ_22
VSSQ_23
VSSQ_24

B4
B3
C4
C3
F4
F3
G4
G3
B11
B12
C11
C12
F11
F12
G11
G12
V11
V12
U11
U12
P11
P12
N11
N12
V4
V3
U4
U3
P4
P3
N4
N3

A13
A2
B10
B5
C1
C13
C14
C2
E1
E11
E13
E14
E2
E4
F10
F5
G13
G2
H12
H3
J13
J2
L13
L2
M12
M3
N13
N2
P10
P5
R1
R11
R13
R14
R2
R4
U1
U13
U14
U2
V10
V5
W13
W2

B13
B2
C10
C5
D13
D2
E10
E5
F13
F2
G10
G5
N10
N5
P13
P2
R10
R5
T13
T2
U10
U5
V13
V2

A3

VPP_1

W3

VPP_2

+1.35VSDGPU

+1.8VSDGPU_AON

FBB_D32 <44>
FBB_D33 <44>
FBB_D34 <44>
FBB_D35 <44>
FBB_D36 <44>
FBB_D37 <44>
FBB_D38 <44>
FBB_D39 <44>
FBB_D40 <44>
FBB_D41 <44>
FBB_D42 <44>
FBB_D43 <44>
FBB_D44 <44>
FBB_D45 <44>
FBB_D46 <44>
FBB_D47 <44>
FBB_D48 <44>
FBB_D49 <44>
FBB_D50 <44>
FBB_D51 <44>
FBB_D52 <44>
FBB_D53 <44>
FBB_D54 <44>
FBB_D55 <44>
FBB_D56 <44>
FBB_D57 <44>
FBB_D58 <44>
FBB_D59 <44>
FBB_D60 <44>
FBB_D61 <44>
FBB_D62 <44>
FBB_D63 <44>

1

Under VRAM

+1.35VSDGPU +1.35VSDGPU

1

1

1

1

1

1

1

CG5941U_0402_6.3V4Z

CG5951U_0402_6.3V4Z

CG6051U_0402_6.3V4Z

CG5881U_0402_6.3V4Z

2

2

2

A A

+1.8VSDGPU_AON

1

1

CG6091U_0402_6.3V4Z

CG5891U_0402_6.3V4Z

CG5901U_0402_6.3V4Z

2

2

2

Under VRAM

1

1

CG94

CG95

2

2

.1U_0402_16V7K

.1U_0402_16V7K

5

1

CG5871U_0402_6.3V4Z

2

2

CG309

.1U_0402_16V7K

1

1

CG5811U_0402_6.3V4Z

CG6041U_0402_6.3V4Z

CG8011U_0402_6.3V4Z

CG8021U_0402_6.3V4Z

2

2

2

2

1

1

CG876

2

2

.1U_0402_16V7K

Under VRAM Near VRAM

1

1

1

CG6001U_0402_6.3V4Z

CG6031U_0402_6.3V4Z

2

2

1

1

1

1

CG6011U_0402_6.3V4Z

CG5991U_0402_6.3V4Z

CG5971U_0402_6.3V4Z

CG6021U_0402_6.3V4Z

CG5981U_0402_6.3V4Z

2

2

2

2

2

+1.35VSDGPU +1.35VSDGPU

1

1

CG5961U_0402_6.3V4Z

2

2

2

4

1

CG58610U_0402_6.3V4Z

CG59110U_0402_6.3V4Z

1

1

1

1

CG60610U_0402_6.3V4Z

CG58410U_0402_6.3V4Z

CG60810U_0402_6.3V4Z

CG58210U_0402_6.3V4Z

2

2

2

2

1

1

1

1

CG80010U_0402_6.3V4Z

CG79710U_0402_6.3V4Z

CG79910U_0402_6.3V4Z

CG79810U_0402_6.3V4Z

2

2

2

2

1

1

CG79422U_0603_6.3V6M

CG59322U_0603_6.3V6M

2

2

Near VRAM

1

1

1

CG58522U_0603_6.3V6M

CG59222U_0603_6.3V6M

CG60722U_0603_6.3V6M

2

2

2

1

1

1

CG79522U_0603_6.3V6M

CG58322U_0603_6.3V6M

CG79622U_0603_6.3V6M

2

2

2

3

22uF 10uF 4.7uF 1uF 0.1uF

4 5

VDD

4 5

VDDQ

12

8

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

N17E-GDDR5_B-M

N17E-GDDR5_B-M

N17E-GDDR5_B-M

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

50 103Monday, January 09, 2017

50 103Monday, January 09, 2017

50 103Monday, January 09, 2017

1.0

1.0

1.0

5

FBC_EDC3<44>
FBC_EDC2<44>
FBC_EDC1<44>
FBC_EDC0<44>

FBC_DBI3<44>
FBC_DBI2<44>
FBC_DBI1<44>

D D

C C

1 2

RG133
931_0402_1%

1

D

MEM_VREF<41 ,49,50,52>

B B

2

G

QG4

S

3

MESS138W-G_SOT 323-3

FBC_CLK0<44> FBC_CLK1<44>
FBC_CLK0#<44>

+1.35VSDGPU

12

RG132
549_0402_1%

+FBC_VREFC

12

1

1

CG148

RG134

CG149

2

2

1.33K_0402_1%

820P_0402_25V7

820P_0402_25V7

FBC_DBI0<44>

FBC_CMD15<44>

FBC_CMD9<44>
FBC_CMD11<44>
FBC_CMD12<44>
FBC_CMD10<44>

FBC_CMD4<44>
FBC_CMD7<44>
FBC_CMD8<44>
FBC_CMD3<44>
FBC_CMD5<44>

+1.35VSDGPU

FBC_CMD14<44>

RG126 1K_0402 _1%
RG130 121_040 2_1%

FBC_CMD6<44>
FBC_CMD2<44>

FBC_CMD13<44>

FBC_WCK23#<44>
FBC_WCK23<44>

FBC_WCK01#<44>
FBC_WCK01<44>

FBC_CMD1<44>

12
12

+1.35VSDGPU

4

UG5

MF=0 MF=1 MF= 0MF=1

D3

EDC0 EDC3

D12

EDC1 EDC2

T12

EDC2 EDC1

T3

EDC3 EDC0

E3

DBI0# DBI3#

E12

DBI1# DBI2#

R12

DBI2# DBI1#

R3

DBI3# DBI0#

K11

CK

K10

CK#

H11

CKE# WE#

J11

BA0/A2 BA2/A4

L10

BA1/A5 BA3/A3

L11

BA2/A4 BA0/A2

J10

BA3/A3 BA1/A5

L4

A8/A7 A10/A0

J5

A9/A1 A11/A6

J4

A10/A0 A8/A7

L5

A11/A6 A9/A1

K5

A12/A13

K12

A14/A15

W12

MF

H13

ZQ

M2

TCK

M13

TDI

A12

TDO

H2

TMS

K4

ABI#

H4

RAS# CAS#

M4

CAS# RAS#

M11

WE# CKE#

D5

WCK01# WCK23#

D4

WCK01 WCK23

T5

WCK23# WCK01#

T4

WCK23 WCK01

K13

VREFC

K2

RESET#

A10

VSS_1

A5

VSS_2

B1

VSS_3

B14

VSS_4

D1

VSS_5

D11

VSS_6

D14

VSS_7

F1

VSS_8

F14

VSS_9

H1

VSS_10

H14

VSS_11

J12

VSS_12

J3

VSS_13

K1

VSS_14

K14

VSS_15

K3

VSS_16

L12

VSS_17

L3

VSS_18

M1

VSS_19

M14

VSS_20

P1

VSS_21

P14

VSS_22

T1

VSS_23

T11

VSS_24

T14

VSS_25

V1

VSS_26

V14

VSS_27

W10

VSS_28

W5

VSS_29

A1

VDD_1

A11

VDD_2

A14

VDD_3

A4

VDD_4

D10

VDD_5

G1

VDD_6

G14

VDD_7

H10

VDD_8

H5

VDD_9

J1

VDD_10

J14

VDD_11

L1

VDD_12

L14

VDD_13

M10

VDD_14

M5

VDD_15

N1

VDD_16

N14

VDD_17

T10

VDD_18

W1

VDD_19

W11

VDD_20

W14

VDD_21

W4

SGRAM GDDR5X

VDD_22

3

MF=1 MF=0

190-BAL L

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15

DQ9 DQ16

DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23

DQ0 DQ24

DQ1 DQ25

DQ2 DQ26

DQ3 DQ27

DQ4 DQ28

DQ5 DQ29

DQ6 DQ30

DQ7 DQ31

MICRON_GDDR5X

B4
B3
C4
C3
F4
F3
G4
G3
B11
B12
C11
C12
F11
F12
G11
G12
V11
V12
U11
U12
P11
P12
N11
N12
V4
V3
U4
U3
P4
P3
N4
N3

A13

VDDQ_1

A2

VDDQ_2

B10

VDDQ_3

B5

VDDQ_4

C1

VDDQ_5

C13

VDDQ_6

C14

VDDQ_7

C2

VDDQ_8

E1

VDDQ_9

E11

VDDQ_10

E13

VDDQ_11

E14

VDDQ_12

E2

VDDQ_13

E4

VDDQ_14

F10

VDDQ_15

F5

VDDQ_16

G13

VDDQ_17

G2

VDDQ_18

H12

VDDQ_19

H3

VDDQ_20

J13

VDDQ_21

J2

VDDQ_22

L13

VDDQ_23

L2

VDDQ_24

M12

VDDQ_25

M3

VDDQ_26

N13

VDDQ_27

N2

VDDQ_28

P10

VDDQ_29

P5

VDDQ_30

R1

VDDQ_31

R11

VDDQ_32

R13

VDDQ_33

R14

VDDQ_34

R2

VDDQ_35

R4

VDDQ_36

U1

VDDQ_37

U13

VDDQ_38

U14

VDDQ_39

U2

VDDQ_40

V10

VDDQ_41

V5

VDDQ_42

W13

VDDQ_43

W2

VDDQ_44

B13

VSSQ_1

B2

VSSQ_2

C10

VSSQ_3

C5

VSSQ_4

D13

VSSQ_5

D2

VSSQ_6

E10

VSSQ_7

E5

VSSQ_8

F13

VSSQ_9

F2

VSSQ_10

G10

VSSQ_11

G5

VSSQ_12

N10

VSSQ_13

N5

VSSQ_14

P13

VSSQ_15

P2

VSSQ_16

R10

VSSQ_17

R5

VSSQ_18

T13

VSSQ_19

T2

VSSQ_20

U10

VSSQ_21

U5

VSSQ_22

V13

VSSQ_23

V2

VSSQ_24

A3

VPP_1

W3

VPP_2

FBC_D24 <44>
FBC_D25 <44>
FBC_D26 <44>
FBC_D27 <44>
FBC_D28 <44>
FBC_D29 <44>
FBC_D30 <44>
FBC_D31 <44>
FBC_D16 <44>
FBC_D17 <44>
FBC_D18 <44>
FBC_D19 <44>
FBC_D20 <44>
FBC_D21 <44>
FBC_D22 <44>
FBC_D23 <44>
FBC_D8 <44>
FBC_D9 <44>
FBC_D10 <44>
FBC_D11 <44>
FBC_D12 <44>
FBC_D13 <44>
FBC_D14 <44>
FBC_D15 <44>
FBC_D0 <44>
FBC_D1 <44>
FBC_D2 <44>
FBC_D3 <44>
FBC_D4 <44>
FBC_D5 <44>
FBC_D6 <44>
FBC_D7 <44>

+1.35VSDGPU +1.35VSDGP U

+1.8VSDGPU_AON +1.8VSDGPU_AON

FBC_CLK1#<44>

FBC_EDC4<44>
FBC_EDC5<44>
FBC_EDC6<44>
FBC_EDC7<44>

FBC_DBI4<44>
FBC_DBI5<44>
FBC_DBI6<44>
FBC_DBI7<44>

FBC_CMD29<44>

FBC_CMD28<44>
FBC_CMD26<44>
FBC_CMD25<44>
FBC_CMD27<44>

FBC_CMD24<44>
FBC_CMD19<44>
FBC_CMD20<44>
FBC_CMD23<44>
FBC_CMD21<44>
FBC_CMD30<44>

12

RG127 1K_04 02_1%

12

RG131 121_0 402_1%

FBC_CMD22<44>
FBC_CMD18<44>FBC_CMD0<44>
FBC_CMD16<44>
FBC_CMD31<44>

FBC_WCK45#<44>
FBC_WCK45<44>

FBC_WCK67#<44>
FBC_WCK67<44>

+FBC_VREFC+FBC_VREFC

FBC_CMD17<44>

+1.35VSDGPU

UG6

MF=0 MF=1 MF= 0MF=1

D3

EDC0 EDC3

D12

EDC1 EDC2

T12

EDC2 EDC1

T3

EDC3 EDC0

E3

DBI0# DBI3#

E12

DBI1# DBI2#

R12

DBI2# DBI1#

R3

DBI3# DBI0#

K11

CK

K10

CK#

H11

CKE# WE#

J11

BA0/A2 BA2/A4

L10

BA1/A5 BA3/A3

L11

BA2/A4 BA0/A2

J10

BA3/A3 BA1/A5

L4

A8/A7 A10/A0

J5

A9/A1 A11/A6

J4

A10/A0 A8/A7

L5

A11/A6 A9/A1

K5

A12/A13

K12

A14/A15

W12

MF

H13

ZQ

M2

TCK

M13

TDI

A12

TDO

H2

TMS

K4

ABI#

H4

RAS# CAS#

M4

CAS# RAS#

M11

WE# CKE#

D5

WCK01# WCK23#

D4

WCK01 WCK23

T5

WCK23# WCK01#

T4

WCK23 WCK01

K13

VREFC

K2

RESET#

A10

VSS_1

A5

VSS_2

B1

VSS_3

B14

VSS_4

D1

VSS_5

D11

VSS_6

D14

VSS_7

F1

VSS_8

F14

VSS_9

H1

VSS_10

H14

VSS_11

J12

VSS_12

J3

VSS_13

K1

VSS_14

K14

VSS_15

K3

VSS_16

L12

VSS_17

L3

VSS_18

M1

VSS_19

M14

VSS_20

P1

VSS_21

P14

VSS_22

T1

VSS_23

T11

VSS_24

T14

VSS_25

V1

VSS_26

V14

VSS_27

W10

VSS_28

W5

VSS_29

A1

VDD_1

A11

VDD_2

A14

VDD_3

A4

VDD_4

D10

VDD_5

G1

VDD_6

G14

VDD_7

H10

VDD_8

H5

VDD_9

J1

VDD_10

J14

VDD_11

L1

VDD_12

L14

VDD_13

M10

VDD_14

M5

VDD_15

N1

VDD_16

N14

VDD_17

T10

VDD_18

W1

VDD_19

W11

VDD_20

W14

VDD_21

W4

VDD_22

190-BAL L

SGRAM GDDR5X

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15

DQ9 DQ16

DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23

DQ0 DQ24

DQ1 DQ25

DQ2 DQ26

DQ3 DQ27

DQ4 DQ28

DQ5 DQ29

DQ6 DQ30

DQ7 DQ31

MICRON_GDDR5X

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8

VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
VDDQ_28
VDDQ_29
VDDQ_30
VDDQ_31
VDDQ_32
VDDQ_33
VDDQ_34
VDDQ_35
VDDQ_36
VDDQ_37
VDDQ_38
VDDQ_39
VDDQ_40
VDDQ_41
VDDQ_42
VDDQ_43
VDDQ_44

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8

VSSQ_9
VSSQ_10
VSSQ_11
VSSQ_12
VSSQ_13
VSSQ_14
VSSQ_15
VSSQ_16
VSSQ_17
VSSQ_18
VSSQ_19
VSSQ_20
VSSQ_21
VSSQ_22
VSSQ_23
VSSQ_24

2

B4
B3
C4
C3
F4
F3
G4
G3
B11
B12
C11
C12
F11
F12
G11
G12
V11
V12
U11
U12
P11
P12
N11
N12
V4
V3
U4
U3
P4
P3
N4
N3

A13
A2
B10
B5
C1
C13
C14
C2
E1
E11
E13
E14
E2
E4
F10
F5
G13
G2
H12
H3
J13
J2
L13
L2
M12
M3
N13
N2
P10
P5
R1
R11
R13
R14
R2
R4
U1
U13
U14
U2
V10
V5
W13
W2

B13
B2
C10
C5
D13
D2
E10
E5
F13
F2
G10
G5
N10
N5
P13
P2
R10
R5
T13
T2
U10
U5
V13
V2

A3

VPP_1

W3

VPP_2

FBC_D32 <44>
FBC_D33 <44>
FBC_D34 <44>
FBC_D35 <44>
FBC_D36 <44>
FBC_D37 <44>
FBC_D38 <44>
FBC_D39 <44>
FBC_D40 <44>
FBC_D41 <44>
FBC_D42 <44>
FBC_D43 <44>
FBC_D44 <44>
FBC_D45 <44>
FBC_D46 <44>
FBC_D47 <44>
FBC_D48 <44>
FBC_D49 <44>
FBC_D50 <44>
FBC_D51 <44>
FBC_D52 <44>
FBC_D53 <44>
FBC_D54 <44>
FBC_D55 <44>
FBC_D56 <44>
FBC_D57 <44>
FBC_D58 <44>
FBC_D59 <44>
FBC_D60 <44>
FBC_D61 <44>
FBC_D62 <44>
FBC_D63 <44>

1

Under VRAM Near VRAMUnder VRAM

+1.35VSDGPU +1.35VSDGPU

1

CG6341U_0402_6.3V4Z

2

A A

1

CG6231U_0402_6.3V4Z

2

+1.8VSDGPU_AON

1

CG6171U_0402_6.3V4Z

CG6241U_0402_6.3V4Z

2

2

1

1

CG6191U_0402_6.3V4Z

CG6181U_0402_6.3V4Z

CG6381U_0402_6.3V4Z

2

2

2

Under VRAM

1

1

CG99

CG96

2

2

.1U_0402_16V7K

.1U_0402_16V7K

5

CG6161U_0402_6.3V4Z

.1U_0402_16V7K

1

1

1

1

1

1

1

CG8041U_0402_6.3V4Z

CG6331U_0402_6.3V4Z

CG8031U_0402_6.3V4Z

CG6101U_0402_6.3V4Z

2

2

2

2

2

1

1

CG311

CG878

2

2

.1U_0402_16V7K

1

1

1

1

1

1

CG6281U_0402_6.3V4Z

CG6271U_0402_6.3V4Z

CG6291U_0402_6.3V4Z

CG6301U_0402_6.3V4Z

CG6321U_0402_6.3V4Z

CG6261U_0402_6.3V4Z

2

2

2

2

2

2

+1.35VSDGPU +1.35VSDGPU

Near VRAM

1

1

1

1

1

CG6311U_0402_6.3V4Z

CG6251U_0402_6.3V4Z

2

2

1

CG61510U_0402_6.3V4Z

CG61110U_0402_6.3V4Z

CG62110U_0402_6.3V4Z

CG63710U_0402_6.3V4Z

2

2

2

2

4

1

1

1

1

CG80610U_0402_6.3V4Z

CG61310U_0402_6.3V4Z

CG63510U_0402_6.3V4Z

CG80810U_0402_6.3V4Z

2

2

2

2

1

1

CG80710U_0402_6.3V4Z

CG80510U_0402_6.3V4Z

2

2

1

1

1

1

CG62222U_0603_6.3V6M

CG62022U_0603_6.3V6M

CG80922U_0603_6.3V6M

CG63622U_0603_6.3V6M

2

2

2

2

1

1

1

1

CG81122U_0603_6.3V6M

CG81022U_0603_6.3V6M

CG61422U_0603_6.3V6M

CG61222U_0603_6.3V6M

2

2

2

2

3

22uF 10uF 4.7uF 1uF 0.1uF

4 5

VDD

4 5

VDDQ

12

8

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

N17E-GDDR5_C-M

N17E-GDDR5_C-M

N17E-GDDR5_C-M

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

51 103Monday, January 09, 2017

51 103Monday, January 09, 2017

51 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

MF=1 MF=0

UG7

MF=0 MF=1 MF= 0MF=1

12
12

+1.35VSDGPU

D3

EDC0 EDC3

D12

EDC1 EDC2

T12

EDC2 EDC1

T3

EDC3 EDC0

E3

DBI0# DBI3#

E12

DBI1# DBI2#

R12

DBI2# DBI1#

R3

DBI3# DBI0#

K11

CK

K10

CK#

H11

CKE# WE#

J11

BA0/A2 BA2/A4

L10

BA1/A5 BA3/A3

L11

BA2/A4 BA0/A2

J10

BA3/A3 BA1/A5

L4

A8/A7 A10/A0

J5

A9/A1 A11/A6

J4

A10/A0 A8/A7

L5

A11/A6 A9/A1

K5

A12/A13

K12

A14/A15

W12

MF

H13

ZQ

M2

TCK

M13

TDI

A12

TDO

H2

TMS

K4

ABI#

H4

RAS# CAS#

M4

CAS# RAS#

M11

WE# CKE#

D5

WCK01# WCK23#

D4

WCK01 WCK23

T5

WCK23# WCK01#

T4

WCK23 WCK01

K13

VREFC

K2

RESET#

A10

VSS_1

A5

VSS_2

B1

VSS_3

B14

VSS_4

D1

VSS_5

D11

VSS_6

D14

VSS_7

F1

VSS_8

F14

VSS_9

H1

VSS_10

H14

VSS_11

J12

VSS_12

J3

VSS_13

K1

VSS_14

K14

VSS_15

K3

VSS_16

L12

VSS_17

L3

VSS_18

M1

VSS_19

M14

VSS_20

P1

VSS_21

P14

VSS_22

T1

VSS_23

T11

VSS_24

T14

VSS_25

V1

VSS_26

V14

VSS_27

W10

VSS_28

W5

VSS_29

A1

VDD_1

A11

VDD_2

A14

VDD_3

A4

VDD_4

D10

VDD_5

G1

VDD_6

G14

VDD_7

H10

VDD_8

H5

VDD_9

J1

VDD_10

J14

VDD_11

L1

VDD_12

L14

VDD_13

M10

VDD_14

M5

VDD_15

N1

VDD_16

N14

VDD_17

T10

VDD_18

W1

VDD_19

W11

VDD_20

W14

VDD_21

W4

VDD_22

190-BAL L

SGRAM GDDR5X

MICRON_GDDR5X

FBD_EDC3<44>
FBD_EDC2<44>
FBD_EDC1<44>
FBD_EDC0<44>

FBD_DBI3<44>
FBD_DBI2<44>
FBD_DBI1<44>

+1.35VSDGPU

RG158 1K_0402 _1%
RG157 121_040 2_1%

FBD_DBI0<44>

FBD_CMD15<44>

FBD_CMD9<44>
FBD_CMD11<44>
FBD_CMD12<44>
FBD_CMD10<44>

FBD_CMD4<44>
FBD_CMD7<44>
FBD_CMD8<44>
FBD_CMD3<44>
FBD_CMD5<44>
FBD_CMD14<44>

FBD_CMD6<44>
FBD_CMD0<44>
FBD_CMD2<44>
FBD_CMD13<44>

FBD_WCK23#<44>
FBD_WCK23<44>

FBD_WCK01#<44>
FBD_WCK01<44>

FBD_CMD1<44>

D D

C C

+1.35VSDGPU

12

1 2

12

RG156
931_0402_1%

1

D

MEM_VREF<41 ,49,50,51>

B B

2

G

QG8

S

3

MESS138W-G_SOT 323-3

FBD_CLK0<44> FBD_CLK1<44>
FBD_CLK0#<44>

RG155
549_0402_1%

+FBD_VREFC

W=16mils

1

1

CG256

CG265

RG154

2

2

1.33K_0402_1%

820P_0402_25V7

820P_0402_25V7

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ9 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8

VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
VDDQ_28
VDDQ_29
VDDQ_30
VDDQ_31
VDDQ_32
VDDQ_33
VDDQ_34
VDDQ_35
VDDQ_36
VDDQ_37
VDDQ_38
VDDQ_39
VDDQ_40
VDDQ_41
VDDQ_42
VDDQ_43
VDDQ_44

VSSQ_1

VSSQ_2

VSSQ_3

VSSQ_4

VSSQ_5

VSSQ_6

VSSQ_7

VSSQ_8

VSSQ_9

VSSQ_10
VSSQ_11
VSSQ_12
VSSQ_13
VSSQ_14
VSSQ_15
VSSQ_16
VSSQ_17
VSSQ_18
VSSQ_19
VSSQ_20
VSSQ_21
VSSQ_22
VSSQ_23
VSSQ_24

B4
B3
C4
C3
F4
F3
G4
G3
B11
B12
C11
C12
F11
F12
G11
G12
V11
V12
U11
U12
P11
P12
N11
N12
V4
V3
U4
U3
P4
P3
N4
N3

A13
A2
B10
B5
C1
C13
C14
C2
E1
E11
E13
E14
E2
E4
F10
F5
G13
G2
H12
H3
J13
J2
L13
L2
M12
M3
N13
N2
P10
P5
R1
R11
R13
R14
R2
R4
U1
U13
U14
U2
V10
V5
W13
W2

B13
B2
C10
C5
D13
D2
E10
E5
F13
F2
G10
G5
N10
N5
P13
P2
R10
R5
T13
T2
U10
U5
V13
V2

A3

VPP_1

W3

VPP_2

FBD_D24 <44>
FBD_D25 <44>
FBD_D26 <44>
FBD_D27 <44>
FBD_D28 <44>
FBD_D29 <44>
FBD_D30 <44>
FBD_D31 <44>
FBD_D16 <44>
FBD_D17 <44>
FBD_D18 <44>
FBD_D19 <44>
FBD_D20 <44>
FBD_D21 <44>
FBD_D22 <44>
FBD_D23 <44>
FBD_D8 <44>
FBD_D9 <44>
FBD_D10 <44>
FBD_D11 <44>
FBD_D12 <44>
FBD_D13 <44>
FBD_D14 <44>
FBD_D15 <44>
FBD_D0 <44>
FBD_D1 <44>
FBD_D2 <44>
FBD_D3 <44>
FBD_D4 <44>
FBD_D5 <44>
FBD_D6 <44>
FBD_D7 <44>

+1.35VSDGPU +1.35VSDGPU

+1.8VSDGPU_AON +1 .8VSDGPU_AON

FBD_CLK1#<44>

FBD_EDC4<44>
FBD_EDC5<44>
FBD_EDC6<44>
FBD_EDC7<44>

FBD_DBI4<44>
FBD_DBI5<44>
FBD_DBI6<44>
FBD_DBI7<44>

FBD_CMD29<44>

FBD_CMD28<44>
FBD_CMD26<44>
FBD_CMD25<44>
FBD_CMD27<44>

FBD_CMD24<44>
FBD_CMD19<44>
FBD_CMD20<44>
FBD_CMD23<44>
FBD_CMD21<44>
FBD_CMD30<44>

12

RG161 1K_0402 _1%

12

RG162 121_040 2_1%

FBD_CMD22<44>
FBD_CMD18<44>
FBD_CMD16<44>
FBD_CMD31<44>

FBD_WCK45#<44>
FBD_WCK45<44>

FBD_WCK67#<44>
FBD_WCK67<44>

FBD_CMD17<44>

+1.35VSDGPU

UG8

MF=0 MF=1 MF= 0MF=1

D3

EDC0 EDC3

D12

EDC1 EDC2

T12

EDC2 EDC1

T3

EDC3 EDC0

E3

DBI0# DBI3#

E12

DBI1# DBI2#

R12

DBI2# DBI1#

R3

DBI3# DBI0#

K11

CK

K10

CK#

H11

CKE# WE#

J11

BA0/A2 BA2/A4

L10

BA1/A5 BA3/A3

L11

BA2/A4 BA0/A2

J10

BA3/A3 BA1/A5

L4

A8/A7 A10/A0

J5

A9/A1 A11/A6

J4

A10/A0 A8/A7

L5

A11/A6 A9/A1

K5

A12/A13

K12

A14/A15

W12

MF

H13

ZQ

M2

TCK

M13

TDI

A12

TDO

H2

TMS

K4

ABI#

H4

RAS# CAS#

M4

CAS# RAS#

M11

WE# CKE#

D5

WCK01# WCK23#

D4

WCK01 WCK23

T5

WCK23# WCK01#

T4

+FBD_VREFC+FBD_VREFC

WCK23 WCK01

K13

VREFC

K2

RESET#

A10

VSS_1

A5

VSS_2

B1

VSS_3

B14

VSS_4

D1

VSS_5

D11

VSS_6

D14

VSS_7

F1

VSS_8

F14

VSS_9

H1

VSS_10

H14

VSS_11

J12

VSS_12

J3

VSS_13

K1

VSS_14

K14

VSS_15

K3

VSS_16

L12

VSS_17

L3

VSS_18

M1

VSS_19

M14

VSS_20

P1

VSS_21

P14

VSS_22

T1

VSS_23

T11

VSS_24

T14

VSS_25

V1

VSS_26

V14

VSS_27

W10

VSS_28

W5

VSS_29

A1

VDD_1

A11

VDD_2

A14

VDD_3

A4

VDD_4

D10

VDD_5

G1

VDD_6

G14

VDD_7

H10

VDD_8

H5

VDD_9

J1

VDD_10

J14

VDD_11

L1

VDD_12

L14

VDD_13

M10

VDD_14

M5

VDD_15

N1

VDD_16

N14

VDD_17

T10

VDD_18

W1

VDD_19

W11

VDD_20

W14

VDD_21

W4

VDD_22

190-BAL L

SGRAM GDDR5X

MICRON_GDDR5X

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15

DQ9 DQ16

DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23

DQ0 DQ24

DQ1 DQ25

DQ2 DQ26

DQ3 DQ27

DQ4 DQ28

DQ5 DQ29

DQ6 DQ30

DQ7 DQ31

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8

VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
VDDQ_28
VDDQ_29
VDDQ_30
VDDQ_31
VDDQ_32
VDDQ_33
VDDQ_34
VDDQ_35
VDDQ_36
VDDQ_37
VDDQ_38
VDDQ_39
VDDQ_40
VDDQ_41
VDDQ_42
VDDQ_43
VDDQ_44

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8

VSSQ_9
VSSQ_10
VSSQ_11
VSSQ_12
VSSQ_13
VSSQ_14
VSSQ_15
VSSQ_16
VSSQ_17
VSSQ_18
VSSQ_19
VSSQ_20
VSSQ_21
VSSQ_22
VSSQ_23
VSSQ_24

B4
B3
C4
C3
F4
F3
G4
G3
B11
B12
C11
C12
F11
F12
G11
G12
V11
V12
U11
U12
P11
P12
N11
N12
V4
V3
U4
U3
P4
P3
N4
N3

A13
A2
B10
B5
C1
C13
C14
C2
E1
E11
E13
E14
E2
E4
F10
F5
G13
G2
H12
H3
J13
J2
L13
L2
M12
M3
N13
N2
P10
P5
R1
R11
R13
R14
R2
R4
U1
U13
U14
U2
V10
V5
W13
W2

B13
B2
C10
C5
D13
D2
E10
E5
F13
F2
G10
G5
N10
N5
P13
P2
R10
R5
T13
T2
U10
U5
V13
V2

A3

VPP_1

W3

VPP_2

FBD_D32 <44>
FBD_D33 <44>
FBD_D34 <44>
FBD_D35 <44>
FBD_D36 <44>
FBD_D37 <44>
FBD_D38 <44>
FBD_D39 <44>
FBD_D40 <44>
FBD_D41 <44>
FBD_D42 <44>
FBD_D43 <44>
FBD_D44 <44>
FBD_D45 <44>
FBD_D46 <44>
FBD_D47 <44>
FBD_D48 <44>
FBD_D49 <44>
FBD_D50 <44>
FBD_D51 <44>
FBD_D52 <44>
FBD_D53 <44>
FBD_D54 <44>
FBD_D55 <44>
FBD_D56 <44>
FBD_D57 <44>
FBD_D58 <44>
FBD_D59 <44>
FBD_D60 <44>
FBD_D61 <44>
FBD_D62 <44>
FBD_D63 <44>

Under VRAM

+1.35VSDGPU +1.35VSDGPU

1

1

1

1

1

CG6531U_0402_6.3V4Z

CG6521U_0402_6.3V4Z

CG6471U_0402_6.3V4Z

CG6461U_0402_6.3V4Z

CG6631U_0402_6.3V4Z

2

2

2

2

2

+1.8VSDGPU_AON

A A

CG107

.1U_0402_16V7K

5

1

1

1

1

CG6621U_0402_6.3V4Z

CG6451U_0402_6.3V4Z

CG6671U_0402_6.3V4Z

CG6481U_0402_6.3V4Z

2

2

2

2

Under VRAM

1

1

1

CG316

CG108

2

2

2

.1U_0402_16V7K

.1U_0402_16V7K

1

1

1

CG8171U_0402_6.3V4Z

CG8161U_0402_6.3V4Z

CG6391U_0402_6.3V4Z

2

2

2

1

CG879

2

.1U_0402_16V7K

Under VRAM

1

1

1

CG6611U_0402_6.3V4Z

CG6571U_0402_6.3V4Z

CG6591U_0402_6.3V4Z

2

2

2

1

1

CG6561U_0402_6.3V4Z

CG6551U_0402_6.3V4Z

2

2

+1.35VSDGPU +1.3 5VSDGPU

Near VRAM

1

1

1

CG6601U_0402_6.3V4Z

CG6541U_0402_6.3V4Z

CG6581U_0402_6.3V4Z

2

2

2

1

1

1

1

1

CG65010U_0402_6.3V4Z

CG64410U_0402_6.3V4Z

2

2

4

1

CG66610U_0402_6.3V4Z

CG64010U_0402_6.3V4Z

CG66410U_0402_6.3V4Z

CG64210U_0402_6.3V4Z

2

2

2

2

Near VRAM

1

1

1

1

1

CG81310U_0402_6.3V4Z

CG81510U_0402_6.3V4Z

CG81210U_0402_6.3V4Z

CG81410U_0402_6.3V4Z

2

2

2

2

1

1

1

CG81822U_0603_6.3V6M

CG65122U_0603_6.3V6M

CG64922U_0603_6.3V6M

CG66522U_0603_6.3V6M

2

2

2

2

1

1

1

1

CG81922U_0603_6.3V6M

CG64122U_0603_6.3V6M

CG82022U_0603_6.3V6M

CG64322U_0603_6.3V6M

2

2

2

2

3

22uF 10uF 4.7uF 1uF 0.1uF

4 5

VDD

4 5

VDDQ

12

8

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

N17E-GDDR5_D-M

N17E-GDDR5_D-M

N17E-GDDR5_D-M

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

52 103Monday, January 09, 2017

52 103Monday, January 09, 2017

52 103Monday, January 09, 2017

1.0

1.0

1.0

5

+1.8VSDGPU_AON_S

1

CG320

1 2

RG535
10K_0201_5%

ALERT_S_R

OVERT_S

12

RG551
10K_0201_5%

DGPU_HOLD_RST#_S
PLT_RST_BUF#

SYS_PEX_RST_MON#_S

GPU_PEX_RST_HOLD# _S

+1.8VSDGPU_MAIN_S

DGPU_PEX_RST#_ S

+1.8VSDGPU_AON_S

12

RG558
10K_0201_5%

61

D

G

2

QG509B

S

PJT138KA 2N SOT36 3-6

DGPU_PEX_RST#_ S_G

2

G

QG522B

61

PJT138KA 2N SOT36 3-6

S

D

UG25W

13/23 MISC 1

BG5

OVERT

BF12

TS_VREF

BJ1

THERMDN

BJ2

THERMDP

BK24

JTAG_TCK

BL23

JTAG_TMS

BM23

JTAG_TDI

BM24

JTAG_TDO

BL24

JTAG_TRST*

BK23

NVJTAG_SEL

N17E-G1_BGA2152 ~D

@

5

+1.8VSDGPU_AON_S

1

IN B

2

IN A

DGPU_PEX_RST#_ S

5

QG522A
PJT138KA 2N SOT36 3-6

34

SGD

DGPU_HOLD_RST#_S<22>

PLT_RST_BUF#<19,28,29,30,31,32,41,68>

D D

C C

DGPU_GC6_FB_EN_S

B B

OVERT_S

JTAG_TCLK_S

T19 PAD~D@

JTAG_TMS_S

T20 PAD~D@

JTAG_TDI_S

T21 PAD~D@

JTAG_TDO_S

T22 PAD~D@

JTAG_TRST#_S

1 2

RG527
10K_0201_5%

A A

5

1

IN B

VCC

OUT Y

2

IN A

GND

NL17SZ08DFT2G_ SC70-5

3

10K_0201_5%

DG8

2

3

BAT54AW-L_SO T323-3

@

1

CG919

0.1U_0201_6.3V6K

2

5

UG102

VCC

4

OUT Y
GND

NL17SZ08DFT2G_ SC70-5

3

GPU_OVERT_S

0.1U_0201_6.3V6K

2

UG23

DGPU_RST#_S

4

+3VSDGPU_S

12

RG560

@

1

DGPU_PEX_RST#_ S_G

+1.8VSDGPU_AON_S

5

1

IN B

VCC

OUT Y

2

IN A

GND

NL17SZ08DFT2G_ SC70-5

3

GPU_ALERT <38,41>

BJ8

I2CS_SCL

BH8

I2CS_SDA

BG9

I2CC_SCL

BH9

I2CC_SDA

BG8

I2CB_SCL

BF8

I2CB_SDA

BD6

GPIO0

BB5

GPIO1

BD1

GPIO2

BE4

GPIO3

BE1

GPIO4

BG2

GPIO5

BD2

GPIO6

BD7

GPIO7

BH4

GPIO8

BJ3

GPIO9

BD3

GPIO10

BH3

GPIO11

BE6

GPIO12

BB1

GPIO13

BG4

GPIO14

BG1

GPIO15

BE2

GPIO16

BH1

GPIO17

BE3

GPIO18

BD4

GPIO19

BE5

GPIO20

BA5

GPIO21

BB6

GPIO22

BG3

GPIO23

BD5

GPIO24

BB2

GPIO25

BE7

GPIO26

BA4

GPIO27

BB4

GPIO28

BA3

GPIO29

BB3

GPIO30

BA2

GPIO31

BA1

GPIO32

12

RG564
0_0201_5%

DGPU_PEX_RST#_ S

1

CG920

@

.1U_0402_16V7K

2

1

CG921

@

.1U_0402_16V7K

2

GPU_OVERT<38,41>

1

CG322

0.1U_0201_6.3V6K

2

UG24

4

VGA_SMB_CK2_S
VGA_SMB_DA2_S

I2CC_SCL_R_ S
I2CC_SDA_R_S

1 2

RG545 1.8K _0402_5%

1 2

RG549 1.8K _0402_5%

DGPU_GC6_FB_EN_S
GPU_EVENT#_D_S

ALERT_S

GPIO12_S

SYS_PEX_RST_MON#_S

Slave_SLI_SWAPR DY_IN
GPU_PEX_RST_HOLD# _S

1 2

@

RG706 0 _0201_5%

1V8_MAIN_EN_S

DG24
RB751S40T1G_ SOD523-2

GPU_OVERT_S

12

+1.8VSDGPU_AON_S

NVVDD_VID_S <9 1>

NVVDDS_VID_S <9 4>
1V8_MAIN_EN_S <57>

NVVDD_PSI_S <91,94 >

MEM_VREF_S <6 1,62,63,64>

RG691 0 _0201_5%

OC_WARN#_S <57>

SYS_PEX_RST_MON#_S

1 2

RG790 0_0 402_5%

+3VS

RG796
10K_0402_5%

1 2

34

D

G

5

QG509A

S

PJT138KA 2N SOT36 3-6

VGA_SMB_CK2_S

VGA_SMB_DA2_S

1 2

4

@

.1U_0402_16V7K

EC_NVVDD_EN_S<38>

NVVDD_EN_S

1 2

DG15
RB751S40T1G_ SOD523-2

+1.8VSDGPU_AON_S

12

RG562
10K_0201_5%

@

DG9
RB751S40T1G_ SOD523-2

DGPU_PEX_RST#_ S_G

5

QG520A
PJT138KA 2N SOT36 3-6

34

SGD

2

G

QG520B

61

PJT138KA 2N SOT36 3-6

S

D

12

GPU_EVENT#_S <22>

DG11
RB751S40T1G_ SOD523-2

1/28 SLI GPIO connection with NV confirmed

Slave_SLI_RASTER _SYNC0 <41>

Master_SLI_SWAPRD Y_IN <41>

4

CG913

2

1

RG770 15K _0402_1%

12

ALERT_S_R

+3VSDGPU_S

12

RG772

@

4.7K_0402_1%

DG16

RB751S40T1G_ SOD523-2

12

12

RG769 20K _0402_1%

DG10
RB751S40T1G_ SOD523-2

1 2

12

NVVDD1_PGOOD_S <91,94,97>
NVVDD2_PGOOD_S <94,97>

EC_SMB_CK2 <20,26,32,36,38,41 >

EC_SMB_DA2 <20,26,32,36,38,41 >

1 2

@

RG694 0 _0201_5%

+3VS

1

CG912

0.1U_0201_6.3V6K

2

5

1

P

B

4

O

2

A

G

UG100

@

3

TC7SH08FU_SSOP5~D

NVVDD1_EN_S <38,91 >

Placed n eer PQ1801

2

CG908
.1U_0402_16V7K

1

NVVDD2_EN_S_R

Placed neer PU2001

2

CG909

0.22U_0402_16V 7K

1

GPU_EVENT#_D_S
OVERT_S
DGPU_HOLD_RST#_S

GPU_PEX_RST_HOLD# _S

GPIO12_S
VGA_SMB_CK2_S
VGA_SMB_DA2_S
SYS_PEX_RST_MON#_S
NVVDD_PSI_S

ALERT_S
OC_WARN#_S

DGPU_GC6_FB_EN_S
MEM_VREF_S
DGPU_PEX_RST#_ S

PEG_CLKREQ#_ S<21>

@

NVVDD_EN_S

1 2

@

RG791 0 _0402_5%

DGPU_PWR_EN<22,38,41,45 ,57>

I2CC_SCL_R_ S

I2CC_SDA_R_S

1 2

RG553 10K_02 01_5%

1 2

RG525 10K_02 01_5%

1 2

RG539 10K_02 01_5%@

1 2

RG550 10K_02 01_5%

1 2

RG538 100K_0 201_5%

1 2

RG522 1.8K_04 02_5%

1 2

RG543 1.8K_04 02_5%

1 2

RG537 10K_02 01_5%

1 2

RG542 10K_02 01_5%

1 2

RG555 10K_02 01_5%

1 2

RG693 10K_02 01_5%

1 2

RG528 10K_02 01_5%

1 2

RG536 100K_0 201_5%

1 2

RG561 1M_0201_ 1%

NVVDD2_EN_S <94,97 >

NVVDD2_EN_S_R

GPIO12_S

+1.8VSDGPU_AON_S

12

RG546

1.8K_0402_1%

3

RB751S40T1G_ SOD523-2

RB751S40T1G_ SOD523-2

12

RG557

1.8K_0402_1%

2

G

61

S

D

+1.8VSDGPU_AON_S

3

+1.8VSDGPU_MAIN_S

RG534
10K_0201_5%

1 2

QG517A

5

PJT138KA 2N SOT36 3-6

3 4

SGD

+1.8VSDGPU_AON_S

5

1

IN B

VCC
OUT Y

2

IN A

GND

NL17SZ08DFT2G_ SC70-5

3

DG19

12

12

DG20

DGPU_PEX_RST#_ S_G

5

QG521A
PJT138KA 2N SOT36 3-6

34

SGD

QG521B
PJT138KA 2N SOT36 3-6

U70

4

+1.8VSDGPU_AON_S

RG524
10K_0201_5%

1 2

DGPU_PEX_RST#_ S

DGPU_PEG_CLKREQ #_S

CLK_PEG_GPU_S_ P8<21>
CLK_PEG_GPU_S_ N8<21>

PCIE_CRX_C_G TX_P8<8>
PCIE_CRX_C_G TX_N8<8 >

PCIE_CRX_C_G TX_P9<8>
PCIE_CRX_C_G TX_N9<8 >

PCIE_CRX_C_G TX_P10<8>
PCIE_CRX_C_G TX_N10<8>

PCIE_CRX_C_G TX_P11<8>
PCIE_CRX_C_G TX_N11<8>

PCIE_CRX_C_G TX_P12<8>
PCIE_CRX_C_G TX_N12<8>

PCIE_CRX_C_G TX_P13<8>
PCIE_CRX_C_G TX_N13<8>

PCIE_CRX_C_G TX_P14<8>
PCIE_CRX_C_G TX_N14<8>

PCIE_CRX_C_G TX_P15<8>
PCIE_CRX_C_G TX_N15<8>

NVVDD2_EN_S_1 NVVDD2_EN_S

1 2

RG793 0 _0402_5%

VGA_OneShot <41,72>

DGPU_PWR_LEVE L <22 ,38,41>

I2CC_SCL_S <57>

I2CC_SDA_S <57>

1 2

RG526 0 _0402_5%

PCIE_CTX_C_G RX_P8<8>
PCIE_CTX_C_G RX_N8<8 >

PCIE_CTX_C_G RX_P9<8>
PCIE_CTX_C_G RX_N9<8 >

PCIE_CTX_C_G RX_P10<8>
PCIE_CTX_C_G RX_N10<8>

PCIE_CTX_C_G RX_P11<8>
PCIE_CTX_C_G RX_N11<8>

PCIE_CTX_C_G RX_P12<8>
PCIE_CTX_C_G RX_N12<8>

PCIE_CTX_C_G RX_P13<8>
PCIE_CTX_C_G RX_N13<8>

PCIE_CTX_C_G RX_P14<8>
PCIE_CTX_C_G RX_N14<8>

PCIE_CTX_C_G RX_P15<8>
PCIE_CTX_C_G RX_N15<8>

DGPU_PEX_RST#_ S_R

2

UG25A

1/23 PCI_EXPRESS

BK26

PEX_RST*

BL26

PEX_CLKREQ*

BM26

PEX_REFCLK

BM27

PEX_REFCLK*

BG26

PEX_TX0

BH26

PEX_TX0*

BL27

PEX_RX0

BK27

PEX_RX0*

BF26

PEX_TX1

BE26

PEX_TX1*

BK29

PEX_RX1

BL29

PEX_RX1*

BF27

PEX_TX2

BG27

PEX_TX2*

BM29

PEX_RX2

BM30

PEX_RX2*

BG29

PEX_TX3

BH29

PEX_TX3*

BL30

PEX_RX3

BK30

PEX_RX3*

BF29

PEX_TX4

BE29

PEX_TX4*

BK32

PEX_RX4

BL32

PEX_RX4*

BF30

PEX_TX5

BG30

PEX_TX5*

BM32

PEX_RX5

BM33

PEX_RX5*

BG32

PEX_TX6

BH32

PEX_TX6*

BL33

PEX_RX6

BK33

PEX_RX6*

BF32

PEX_TX7

BE32

PEX_TX7*

BK35

PEX_RX7

BL35

PEX_RX7*

BF33

PEX_TX8

BG33

PEX_TX8*

BM35

PEX_RX8

BM36

PEX_RX8*

BG35

PEX_TX9

BH35

PEX_TX9*

BL36

PEX_RX9

BK36

PEX_RX9*

BF35

PEX_TX10

BE35

PEX_TX10*

BK38

PEX_RX10

BL38

PEX_RX10*

BF36

PEX_TX11

BG36

PEX_TX11*

BM38

PEX_RX11

BM39

PEX_RX11*

BG38

PEX_TX12

BH38

PEX_TX12*

BL39

PEX_RX12

BK39

PEX_RX12*

BF38

PEX_TX13

BE38

PEX_TX13*

BK41

PEX_RX13

BL41

PEX_RX13*

BF39

PEX_TX14

BG39

PEX_TX14*

BM41

PEX_RX14

BM42

PEX_RX14*

BH41

PEX_TX15

BG41

PEX_TX15*

BL42

PEX_RX15

BK42

PEX_RX15*

DGPU_GC6_FB_EN_S

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

2

BB33

PEX_DVDD_1

BB35

PEX_DVDD_2

BB36

1

PEX_DVDD_3
PEX_DVDD_4
PEX_DVDD_5
PEX_DVDD_6
PEX_DVDD_7
PEX_DVDD_8

BC33
BC35
BC36
BD33
BD36

1

CG314

2

2

1U_0402_6.3V6K

Under GPU

BB26

PEX_HVDD_1

BB27

PEX_HVDD_2

BB29

1

Under GPU

PEX_TERMP_S

+3VS

12

61

D

G

2

S

Deciphered Date

Deciphered Date

Deciphered Date

1

CG312

2

2

1U_0402_6.3V6K

+PEX_PLL_HVDD_S

1

CG310

0.1U_0201_6.3V6K

2

RG541

2.49K_0402_1 %

RG776
10K_0201_5%

QG525B
PJT138KA 2N SOT36 3-6

PEX_HVDD_3

BB32

PEX_HVDD_4

BC26

PEX_HVDD_5

BC27

PEX_HVDD_6

BC29

PEX_HVDD_7

BC30

PEX_HVDD_8

BC32

PEX_HVDD_9

BD27

PEX_HVDD_10

BD30

PEX_HVDD_11

BB30

PEX_PLL_HVDD

BL44

PEX_TERMP

N17E-G1_BGA2152 ~D@

+1.0VS_VGA_PGOO D_S<9 7>

+3VS

12

RG775
100K_0201_5 %

GC6_FB_EN#_S

34

D

G

5

QG525A

S

PJT138KA 2N SOT36 3-6

Compal Secret Data

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

CG321

1U_0402_6.3V6K

CG317

1U_0402_6.3V6K

12

1 2

1

2

1

2

LG7
PBY160808T-301Y-N

PEX_DVDD

PEX_HVDD

1

CG330

CG323

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CG313

CG331

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+1.8VSDGPU_MAIN_S

3

1

2

DAN202UT106_SC70 -3
DG7

GPU_GC6_FB_EN_S <22>

1

+1.0VSDGPU_S

1

2

1

CG335

2

4.7U_0603_6.3V6K

1

CG329

2

4.7U_0603_6.3V6K

12

2

CG341

CG872

CG315

2

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

4.7U_0603_6.3V6K

+1.8VSDGPU_MAIN_S

2

2

1

CG325

2

4.7U_0603_6.3V6K

11

21

RG547
100K_0201_5 %

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

12

CG327

CG333

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

4.7uF10u F22uF

0.1uF1uF

2

4

2 4

1.35VSDGPU_EN_S <3 8,96>

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

N17E-G1(1/6) PCIE,GPIO-S

N17E-G1(1/6) PCIE,GPIO-S

N17E-G1(1/6) PCIE,GPIO-S

Document Number Rev

Document Number Rev

Document Number Rev

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

1

CG343

2

22U_0805_6.3V6M

CG340

22U_0603_6.3V6M

53 103Monday, January 09, 2017

53 103Monday, January 09, 2017

53 103Monday, January 09, 2017

1.0

1.0

1.0

5

UG25N

7/23 IFPAB

BD23

BD21

IFPAB_RSET

IFPAB_PLLVDD

D D

DL-DVI

SDA

SDA

SCL

SCL

TXC

TXC

TXC

TXC

TXD0

TXD0

TXD0

TXD0

TXD1

TXD1

TXD1

TXD1

TXD2

TXD2

TXD2

TXD2

DPDVI/HDMI

IFPA_AUX_SDA*

IFPA_AUX_SCL

IFPA_L3*

IFPA_L3

IFPA_L2*

IFPA_L2

IFPA_L1*

IFPA_L1

IFPA_L0*

IFPA_L0

4

BH11
BG11

BF21
BG21

BG23
BH23

BF23
BE23

BF24
BG24

3

2

1

IFPB_L3*

IFPB_L3

IFPB_L2*

IFPB_L2

IFPB_L1*

IFPB_L1

IFPB_L0*

IFPB_L0

BG12
BH12

BL18
BK18

BK20
BL20

BM20
BM21

BL21
BK21

SDA

IFPB_AUX_SDA*

SCL

IFPB_AUX_SCL

BB17

IFP_IOVDD_2

BB15

IFP_IOVDD_1

BB18

IFP_IOVDD_3

BB20

IFP_IOVDD_4

C C

IFPAB

TXC
TXC

TXD0

TXD3

TXD0

TXD3

TXD1

TXD4

TXD1

TXD4

TXD2

TXD5

TXD2

TXD5

N17E-G1_BGA2152~D@

22uF 10uF 4.7uF 1uF 0.1uF

UG25P

10/23 IFPE

BD17

IFPEF_RSET

BD15

IFPEF_PLLVDD

IFPE

BC18

IFP_IOVDD_9

BC20

BC21
BC23

IFP_IOVDD_10

UG25O

6/23 IFPF

IFP_IOVDD_11
IFP_IOVDD_12

B B

IFPF

A A

DVI/HDMI

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

DVI/HDMI

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

IFPE_AUX_SDA*

IFPE_AUX_SCL

N17E-G1_BGA2152~D@

N17E-G1_BGA2152~D@

DP

IFPE_L3*

IFPE_L3

IFPE_L2*

IFPE_L2

IFPE_L1*

IFPE_L1

IFPE_L0*

IFPE_L0

DP

IFPF_AUX_SDA*

IFPF_AUX_SCL

IFPF_L3*

IFPF_L3

IFPF_L2*

IFPF_L2

IFPF_L1*

IFPF_L1

IFPF_L0*

IFPF_L0

BL8
BK8

BG14
BH14

BF14
BE14

BF15
BG15

BG17
BH17

BM9
BM8

BK11
BL11

BM11
BM12

BL12
BK12

BK14
BL14

IFPx_IOVDD

IFPx_PLLVDD

1

2

4

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

N17E-G1(2/6) eDP,HDMI,mDP-S

N17E-G1(2/6) eDP,HDMI,mDP-S

N17E-G1(2/6) eDP,HDMI,mDP-S

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

54 103Monday, January 09, 2017

54 103Monday, January 09, 2017

54 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

BD20

BD18

BB21
BB23

BC15
BC17

UG25R

8/23 IFPC

IFPCD_RSET

IFPCD_PLLVDD

IFPC

IFP_IOVDD_5
IFP_IOVDD_6

UG25Q

9/23 IFPD

IFPD

IFP_IOVDD_7
IFP_IOVDD_8

DVI/HDMI

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

DVI/HDMI

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

IFPC_AUX_SDA*

IFPC_AUX_SCL

N17E-G1_BGA2152~D@

IFPD_AUX_SDA*

IFPD_AUX_SCL

N17E-G1_BGA2152~D@

DP

DP

IFPC_L3*

IFPC_L3

IFPC_L2*

IFPC_L2

IFPC_L1*

IFPC_L1

IFPC_L0*

IFPC_L0

IFPD_L3*

IFPD_L3

IFPD_L2*

IFPD_L2

IFPD_L1*

IFPD_L1

IFPD_L0*

IFPD_L0

BL9
BK9

BF17
BE17

BF18
BG18

BG20
BH20

BF20
BE20

BF11
BE11

BM14
BM15

BL15
BK15

BK17
BL17

BM17
BM18

D D

C C

B B

A A

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2016/02/01 2017/12/31

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N17E-G1(1/6) PCIE,GPIO

N17E-G1(1/6) PCIE,GPIO

N17E-G1(1/6) PCIE,GPIO

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

1.0

1.0

1.0

55 103Monday, January 09, 2017

55 103Monday, January 09, 2017

55 103Monday, January 09, 2017

5

D D

4

3

2

1

UG25B

2/23 FBA

FBE_D0<61>
FBE_D1<61>
FBE_D2<61>
FBE_D3<61>
FBE_D4<61>
FBE_D5<61>
FBE_D6<61>
FBE_D7<61>
FBE_D8<61>
FBE_D9<61>
FBE_D10<61>
FBE_D11<61>
FBE_D12<61>
FBE_D13<61>
FBE_D14<61>
FBE_D15<61>
FBE_D16<61>
FBE_D17<61>
FBE_D18<61>
FBE_D19<61>
FBE_D20<61>
FBE_D21<61>
FBE_D22<61>
FBE_D23<61>
FBE_D24<61>
FBE_D25<61>
FBE_D26<61>
FBE_D27<61>
FBE_D28<61>
FBE_D29<61>
FBE_D30<61>
FBE_D31<61>
FBE_D32<61>
FBE_D33<61>
FBE_D34<61>
FBE_D35<61>
FBE_D36<61>
FBE_D37<61>
FBE_D38<61>
FBE_D39<61>
FBE_D40<61>
FBE_D41<61>
FBE_D42<61>
FBE_D43<61>
FBE_D44<61>
FBE_D45<61>
FBE_D46<61>
FBE_D47<61>

C C

FBE_D48<61>
FBE_D49<61>
FBE_D50<61>
FBE_D51<61>
FBE_D52<61>
FBE_D53<61>
FBE_D54<61>
FBE_D55<61>
FBE_D56<61>
FBE_D57<61>
FBE_D58<61>
FBE_D59<61>
FBE_D60<61>
FBE_D61<61>
FBE_D62<61>
FBE_D63<61>

FBE_DBI0<61>
FBE_DBI1<61>
FBE_DBI2<61>
FBE_DBI3<61>
FBE_DBI4<61>
FBE_DBI5<61>
FBE_DBI6<61>
FBE_DBI7<61>

FBE_EDC 0<61>
FBE_EDC 1<61>
FBE_EDC 2<61>
FBE_EDC 3<61>
FBE_EDC 4<61>
FBE_EDC 5<61>
FBE_EDC 6<61>
FBE_EDC 7<61>

+FBX_PLLA VDD_S

1

CG371

2

.1U_0402_16V7K

B B

U51

FBA_D0

U48

FBA_D1

U50

FBA_D2

U49

FBA_D3

R51

FBA_D4

R50

FBA_D5

R47

FBA_D6

U46

FBA_D7

V46

FBA_D8

Y45

FBA_D9

Y47

FBA_D10

Y46

FBA_D11

V50

FBA_D12

V47

FBA_D13

U52

FBA_D14

V51

FBA_D15

AJ44

FBA_D16

AG48

FBA_D17

AJ45

FBA_D18

AG49

FBA_D19

AF46

FBA_D20

AF47

FBA_D21

AF48

FBA_D22

AD47

FBA_D23

AD49

FBA_D24

AD48

FBA_D25

AC46

FBA_D26

AC47

FBA_D27

AA47

FBA_D28

AA46

FBA_D29

AA45

FBA_D30

Y44

FBA_D31

AW51

FBA_D32

BA52

FBA_D33

AW50

FBA_D34

BA51

FBA_D35

BA50

FBA_D36

BB50

FBA_D37

BA49

FBA_D38

AW49

FBA_D39

AV48

FBA_D40

AT49

FBA_D41

AT47

FBA_D42

AT48

FBA_D43

AT46

FBA_D44

AV51

FBA_D45

AV52

FBA_D46

AV49

FBA_D47

AJ48

FBA_D48

AJ46

FBA_D49

AJ47

FBA_D50

AK49

FBA_D51

AM47

FBA_D52

AM46

FBA_D53

AN48

FBA_D54

AN49

FBA_D55

AM44

FBA_D56

AM45

FBA_D57

AN45

FBA_D58

AN46

FBA_D59

AR48

FBA_D60

AN47

FBA_D61

AR47

FBA_D62

AR46

FBA_D63

U47

FBA_DQM0

Y48

FBA_DQM1

AG47

FBA_DQM2

AC48

FBA_DQM3

BB51

FBA_DQM4

AV50

FBA_DQM5

AM48

FBA_DQM6

AR49

FBA_DQM7

R48

FBA_DQS_WP0

V48

FBA_DQS_WP1

AF44

FBA_DQS_WP2

AA48

FBA_DQS_WP3

BB52

FBA_DQS_WP4

AT50

FBA_DQS_WP5

AK48

FBA_DQS_WP6

AR51

FBA_DQS_WP7

W47

GND_694

W49

GND_695

W51

GND_696

W6

GND_697

W8

GND_698

Y14

GND_699

Y15

GND_700

Y16

GND_701

AF42

FB_REFPLL_AVDD0

L29

FB_REFPLL_AVDD1

1

CG373

2

.1U_0402_16V7K

10K_0402_5 %
RG568

1 2

FBE_CMD1 3
FBE_CMD2 9
FBE_CMD1 7
FBE_CMD1

10K_0402_5 %
RG573

1 2

N17E-G1_BGA21 52~D@

+1.35VSDGPU_ S

1 2

1 2

Y51

FBA_CMD0

FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_CMD32
FBA_CMD33
FBA_CMD34
FBA_CMD35

FBA_DBG_RFU1
FBA_DBG_RFU2

FBA_CLK0

FBA_CLK0*

FBA_CLK1

FBA_CLK1*

FBA_WCK01

FBA_WCK01*
FBA_WCKB01
FBA_WCKB01*

FBA_WCK23

FBA_WCK23*
FBA_WCKB23
FBA_WCKB23*

FBA_WCK45

FBA_WCK45*
FBA_WCKB45
FBA_WCKB45*

FBA_WCK67

FBA_WCK67*
FBA_WCKB67
FBA_WCKB67*

FBA_PLL_AVDD

FBE_CMD1
FBE_CMD2

FBE_CMD1 7
FBE_CMD1 8

1

2

FBE_CMD0 <61>
FBE_CMD1 <61>
FBE_CMD2 <61>
FBE_CMD3 <61>
FBE_CMD4 <61>
FBE_CMD5 <61>
FBE_CMD6 <61>
FBE_CMD7 <61>
FBE_CMD8 <61>
FBE_CMD9 <61>
FBE_CMD1 0 <61>
FBE_CMD1 1 <61>
FBE_CMD1 2 <61>
FBE_CMD1 3 <61>
FBE_CMD1 4 <61>
FBE_CMD1 5 <61>
FBE_CMD1 6 <61>
FBE_CMD1 7 <61>
FBE_CMD1 8 <61>
FBE_CMD1 9 <61>
FBE_CMD2 0 <61>
FBE_CMD2 1 <61>
FBE_CMD2 2 <61>
FBE_CMD2 3 <61>
FBE_CMD2 4 <61>
FBE_CMD2 5 <61>
FBE_CMD2 6 <61>
FBE_CMD2 7 <61>
FBE_CMD2 8 <61>
FBE_CMD2 9 <61>
FBE_CMD3 0 <61>
FBE_CMD3 1 <61>

FBE_CLK0 <61>
FBE_CLK0 # <61>
FBE_CLK1 <61>
FBE_CLK1 # <61>

FBE_WCK0 1 <61>
FBE_WCK0 1# <61 >

FBE_WCK2 3 <61>
FBE_WCK2 3# <61 >

FBE_WCK4 5 <61>
FBE_WCK4 5# <61 >

FBE_WCK6 7 <61>
FBE_WCK6 7# <61 >

1 2

LG10
PBY160808T-300Y-N_2P

1 2

LG9
PBY160808T-300Y-N_2P

12

CG369

CG374

0.1U_0402_16V7K

22U_0603_6.3V6M

Y52
Y49
AA52
AA51
AA50
AC50
AC51
AC52
AC49
AD52
AD51
AD50
AF50
AF51
AF52
AN50
AN51
AN52
AM49
AM52
AM51
AM50
AK50
AK51
AK52
AJ49
AJ52
AJ51
AJ50
AG50
AG51
AG52
AF49
Y50
AR50

AA44
AN44

AG45
AG46
AK46
AK45

U45
U44
V45
V44
AC45
AC44
AD46
AD45
AV47
AV46
AW48
AW47
AR45
AR44
AT45
AT44

AN42

+1.8VSDGPU_MA IN_S

FBF_D0<62>
FBF_D1<62>
FBF_D2<62>
FBF_D3<62>
FBF_D4<62>
FBF_D5<62>
FBF_D6<62>
FBF_D7<62>
FBF_D8<62>
FBF_D9<62>
FBF_D10<62>
FBF_D11<62>
FBF_D12<62>
FBF_D13<62>
FBF_D14<62>
FBF_D15<62>
FBF_D16<62>
FBF_D17<62>
FBF_D18<62>
FBF_D19<62>
FBF_D20<62>
FBF_D21<62>
FBF_D22<62>
FBF_D23<62>
FBF_D24<62>
FBF_D25<62>
FBF_D26<62>
FBF_D27<62>
FBF_D28<62>
FBF_D29<62>
FBF_D30<62>
FBF_D31<62>
FBF_D32<62>
FBF_D33<62>
FBF_D34<62>
FBF_D35<62>
FBF_D36<62>
FBF_D37<62>
FBF_D38<62>
FBF_D39<62>
FBF_D40<62>
FBF_D41<62>
FBF_D42<62>
FBF_D43<62>
FBF_D44<62>
FBF_D45<62>
FBF_D46<62>
FBF_D47<62>
FBF_D48<62>
FBF_D49<62>
FBF_D50<62>
FBF_D51<62>
FBF_D52<62>
FBF_D53<62>
FBF_D54<62>
FBF_D55<62>
FBF_D56<62>
FBF_D57<62>
FBF_D58<62>
FBF_D59<62>
FBF_D60<62>
FBF_D61<62>
FBF_D62<62>
FBF_D63<62>

FBF_DBI0<62>
FBF_DBI1<62>
FBF_DBI2<62>
FBF_DBI3<62>
FBF_DBI4<62>
FBF_DBI5<62>
FBF_DBI6<62>
FBF_DBI7<62>

FBF_EDC 0<62>
FBF_EDC 1<62>
FBF_EDC 2<62>
FBF_EDC 3<62>
FBF_EDC 4<62>
FBF_EDC 5<62>
FBF_EDC 6<62>
FBF_EDC 7<62>

Under GPU Under GPU Under GPU Under GPU

10K_0402_5 %
RG575

10K_0402_5 %
RG572

H32
D32
A33
B32
E32
G32
J30
F32
H36
G36
J36
F36
F33
D33
J32
G33
E45
D45
F45
G45
D42
E42
F42
H41
E41
F39
E39
D39
F38
E38
D36
E36
M50
P48
M51
M49
P47
P52
R46
P46
L50
L51
L52
L49
M46
L47
M48
M47
D48
C50
C48
C49
E49
E50
F49
F48
F50
D52
J50
H48
H51
J51
H49
H52

C32
E33
E44
G39
P49
L48
D50
H50

B33
E35
G44
H38
P50
J48
D51
F51

Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24

FBF_CMD1 3
FBF_CMD2 9

FBF_CMD1 7
FBF_CMD1

UG25C

3/23 FBB

FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63

FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7

FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7

GND_702
GND_703
GND_704
GND_705
GND_706
GND_707
GND_708
GND_709

UG25D

B35

FBF_CMD1
FBF_CMD2

FBF_CMD1 7
FBF_CMD1 8

1

2

FBF_CMD0 <62>
FBF_CMD1 <62>
FBF_CMD2 <62>
FBF_CMD3 <62>
FBF_CMD4 <62>
FBF_CMD5 <62>
FBF_CMD6 <62>
FBF_CMD7 <62>
FBF_CMD8 <62>
FBF_CMD9 <62>
FBF_CMD1 0 <62>
FBF_CMD1 1 <62>
FBF_CMD1 2 <62>
FBF_CMD1 3 <62>
FBF_CMD1 4 <62>
FBF_CMD1 5 <62>
FBF_CMD1 6 <62>
FBF_CMD1 7 <62>
FBF_CMD1 8 <62>
FBF_CMD1 9 <62>
FBF_CMD2 0 <62>
FBF_CMD2 1 <62>
FBF_CMD2 2 <62>
FBF_CMD2 3 <62>
FBF_CMD2 4 <62>
FBF_CMD2 5 <62>
FBF_CMD2 6 <62>
FBF_CMD2 7 <62>
FBF_CMD2 8 <62>
FBF_CMD2 9 <62>
FBF_CMD3 0 <62>
FBF_CMD3 1 <62>

FBF_CLK0 <62>
FBF_CLK0 # <62>
FBF_CLK1 <62>
FBF_CLK1 # <62>

FBF_WCK0 1 <6 2>
FBF_WCK0 1# < 62>

FBF_WCK2 3 <6 2>
FBF_WCK2 3# < 62>

FBF_WCK4 5 <6 2>
FBF_WCK4 5# < 62>

FBF_WCK6 7 <6 2>
FBF_WCK6 7# < 62>

0.1U_0402_16V7K
CG372

FBB_CMD0

A35

FBB_CMD1

D35

FBB_CMD2

A36

FBB_CMD3

B36

FBB_CMD4

C36

FBB_CMD5

C38

FBB_CMD6

B38

FBB_CMD7

A38

FBB_CMD8

D38

FBB_CMD9

A39

FBB_CMD10

B39

FBB_CMD11

C39

FBB_CMD12

C41

FBB_CMD13

B41

FBB_CMD14

A41

FBB_CMD15

B49

FBB_CMD16

A49

FBB_CMD17

A48

FBB_CMD18

D47

FBB_CMD19

A47

FBB_CMD20

B47

FBB_CMD21

C47

FBB_CMD22

C45

FBB_CMD23

B45

FBB_CMD24

A45

FBB_CMD25

D44

FBB_CMD26

A44

FBB_CMD27

B44

FBB_CMD28

C44

FBB_CMD29

C42

FBB_CMD30

B42

FBB_CMD31

A42

FBB_CMD32

D41

FBB_CMD33

C35

FBB_CMD34

B50

FBB_CMD35

J35

FBB_DBG_RFU1

J41

FBB_DBG_RFU2

H42

FBB_CLK0

G42

FBB_CLK0*

F47

FBB_CLK1

E47

FBB_CLK1*

J33

FBB_WCK01

H33

FBB_WCK01*

G35

FBB_WCKB01

H35

FBB_WCKB01*

J39

FBB_WCK23

H39

FBB_WCK23*

F41

FBB_WCKB23

G41

FBB_WCKB23*

L46

FBB_WCK45

L45

FBB_WCK45*

M44

FBB_WCKB45

M45

FBB_WCKB45*

H47

FBB_WCK67

H46

FBB_WCK67*

J47

FBB_WCKB67

J46

FBB_WCKB67*

L38

FBB_PLL_AVDD

N17E-G1_BGA21 52~D@

+1.35VSDGPU_ S +1.35VSDGPU_ S +1.35VSDGPU_S

10K_0402_5 %

10K_0402_5 %

RG577

RG571

1 2

1 2

10K_0402_5 %

10K_0402_5 %

RG582

RG570

1 2

1 2

FBG_D0<63>
FBG_D1<63>
FBG_D2<63>
FBG_D3<63>
FBG_D4<63>
FBG_D5<63>
FBG_D6<63>
FBG_D7<63>
FBG_D8<63>
FBG_D9<63>
FBG_D10<63>
FBG_D11<63>
FBG_D12<63>
FBG_D13<63>
FBG_D14<63>
FBG_D15<63>
FBG_D16<63>
FBG_D17<63>
FBG_D18<63>
FBG_D19<63>
FBG_D20<63>
FBG_D21<63>
FBG_D22<63>
FBG_D23<63>
FBG_D24<63>
FBG_D25<63>
FBG_D26<63>
FBG_D27<63>
FBG_D28<63>
FBG_D29<63>
FBG_D30<63>
FBG_D31<63>
FBG_D32<63>
FBG_D33<63>
FBG_D34<63>
FBG_D35<63>
FBG_D36<63>
FBG_D37<63>
FBG_D38<63>
FBG_D39<63>
FBG_D40<63>
FBG_D41<63>
FBG_D42<63>
FBG_D43<63>
FBG_D44<63>
FBG_D45<63>
FBG_D46<63>
FBG_D47<63>
FBG_D48<63>
FBG_D49<63>
FBG_D50<63>
FBG_D51<63>
FBG_D52<63>
FBG_D53<63>
FBG_D54<63>
FBG_D55<63>
FBG_D56<63>
FBG_D57<63>
FBG_D58<63>
FBG_D59<63>
FBG_D60<63>
FBG_D61<63>
FBG_D62<63>
FBG_D63<63>

FBG_DBI0<63>
FBG_DBI1<63>
FBG_DBI2<63>
FBG_DBI3<63>
FBG_DBI4<63>
FBG_DBI5<63>
FBG_DBI6<63>
FBG_DBI7<63>

FBG_EDC0<63>
FBG_EDC1<63>
FBG_EDC2<63>
FBG_EDC3<63>
FBG_EDC4<63>
FBG_EDC5<63>
FBG_EDC6<63>
FBG_EDC7<63>

C6
D6
A6
B6
B4
A4
B3
C4
D9
C9
E9
B9
B8
A8

F6

E6
F18
G18
E18
H18
D15
E15
G17
H17

J15
H15
E14
F14
H11
G11
F11
E11

J29
F30
H29
G30
B30
A30
H30
C30
D27

J26
F27
G27
C27
B27
A27
G29
H20
D18
G20
E20
F23
E21
D21
E23
G24
H26
F24
G26
F26
D26
B26
C26

A5

C8

J18
F12
D29
E27
F20
E26

D5

D8
E17
E12
E30
B29
G21
E24

Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y32

FBG_CMD13

FBG_CMD29

FBG_CMD17

FBG_CMD1

4/23 FBC

FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63

FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7

FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7

GND_710
GND_711
GND_712
GND_713
GND_714
GND_715
GND_716
GND_717

1 2

1 2

10K_0402_5 %
RG580

10K_0402_5 %
RG578

N17E-G1_BGA21 52~D@

1 2

1 2

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8

FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30
FBC_CMD31
FBC_CMD32
FBC_CMD33
FBC_CMD34
FBC_CMD35

FBC_DBG_RFU1
FBC_DBG_RFU2

FBC_CLK0
FBC_CLK0*

FBC_CLK1
FBC_CLK1*

FBC_WCK01

FBC_WCK01*
FBC_WCKB01

FBC_WCKB01*

FBC_WCK23

FBC_WCK23*
FBC_WCKB23

FBC_WCKB23*

FBC_WCK45

FBC_WCK45*
FBC_WCKB45

FBC_WCKB45*

FBC_WCK67

FBC_WCK67*
FBC_WCKB67

FBC_WCKB67*

FBC_PLL_AVDD

10K_0402_5 %
RG569

10K_0402_5 %
RG581

C11

FBG_CMD1

B11
A11
D11
A12
B12
C12
C14
B14
A14
D14
A15
B15
C15
C17
B17
B24
A24
D23
A23
B23
C23
C21
B21
A21
D20
A20
B20
C20
C18
B18
A18
D17
A17
A9
C24

J14
J23

G15
F15
H21
J21

F8
G8
G9
F9
H12
G12
G14
H14
J27
H27
E29
F29
G23
H23
H24
J24

L17

FBG_CMD0 <63>

FBG_CMD2

FBG_CMD1 <63>
FBG_CMD2 <63>
FBG_CMD3 <63>
FBG_CMD4 <63>
FBG_CMD5 <63>
FBG_CMD6 <63>
FBG_CMD7 <63>
FBG_CMD8 <63>
FBG_CMD9 <63>
FBG_CMD10 <63>
FBG_CMD11 <63>
FBG_CMD12 <63>
FBG_CMD13 <63>
FBG_CMD14 <63>
FBG_CMD15 <63>

FBG_CMD17

FBG_CMD16 <63>

FBG_CMD18

FBG_CMD17 <63>
FBG_CMD18 <63>
FBG_CMD19 <63>
FBG_CMD20 <63>
FBG_CMD21 <63>
FBG_CMD22 <63>
FBG_CMD23 <63>
FBG_CMD24 <63>
FBG_CMD25 <63>
FBG_CMD26 <63>
FBG_CMD27 <63>
FBG_CMD28 <63>
FBG_CMD29 <63>
FBG_CMD30 <63>
FBG_CMD31 <63>

FBG_CLK0 <63>
FBG_CLK0# <63>
FBG_CLK1 <63>
FBG_CLK1# <63>

FBG_WCK01 <63 >
FBG_WCK01 # <6 3>

FBG_WCK23 <63 >
FBG_WCK23 # <6 3>

FBG_WCK45 <63 >
FBG_WCK45 # <6 3>

FBG_WCK67 <63 >
FBG_WCK67 # <6 3>

0.1U_0402_16V7K
CG370

1

20160201_Change PN20160201_Change PN 20160201_Change PN

2

FBH_D0<64>
FBH_D1<64>
FBH_D2<64>
FBH_D3<64>
FBH_D4<64>
FBH_D5<64>
FBH_D6<64>
FBH_D7<64>
FBH_D8<64>
FBH_D9<64>
FBH_D10<6 4>
FBH_D11<6 4>
FBH_D12<6 4>
FBH_D13<6 4>
FBH_D14<6 4>
FBH_D15<6 4>
FBH_D16<6 4>
FBH_D17<6 4>
FBH_D18<6 4>
FBH_D19<6 4>
FBH_D20<6 4>
FBH_D21<6 4>
FBH_D22<6 4>
FBH_D23<6 4>
FBH_D24<6 4>
FBH_D25<6 4>
FBH_D26<6 4>
FBH_D27<6 4>
FBH_D28<6 4>
FBH_D29<6 4>
FBH_D30<6 4>
FBH_D31<6 4>
FBH_D32<6 4>
FBH_D33<6 4>
FBH_D34<6 4>
FBH_D35<6 4>
FBH_D36<6 4>
FBH_D37<6 4>
FBH_D38<6 4>
FBH_D39<6 4>
FBH_D40<6 4>
FBH_D41<6 4>
FBH_D42<6 4>
FBH_D43<6 4>
FBH_D44<6 4>
FBH_D45<6 4>
FBH_D46<6 4>
FBH_D47<6 4>
FBH_D48<6 4>
FBH_D49<6 4>
FBH_D50<6 4>
FBH_D51<6 4>
FBH_D52<6 4>
FBH_D53<6 4>
FBH_D54<6 4>
FBH_D55<6 4>
FBH_D56<6 4>
FBH_D57<6 4>
FBH_D58<6 4>
FBH_D59<6 4>
FBH_D60<6 4>
FBH_D61<6 4>
FBH_D62<6 4>
FBH_D63<6 4>

FBH_DBI0<64>
FBH_DBI1<64>
FBH_DBI2<64>
FBH_DBI3<64>
FBH_DBI4<64>
FBH_DBI5<64>
FBH_DBI6<64>
FBH_DBI7<64>

FBH_EDC0<6 4>
FBH_EDC1<6 4>
FBH_EDC2<6 4>
FBH_EDC3<6 4>
FBH_EDC4<6 4>
FBH_EDC5<6 4>
FBH_EDC6<6 4>
FBH_EDC7<6 4>

AK8
AK4
AK2
AK3
AK5
AK6
AK9
AK7
AG4
AF9
AG6
AG7

AJ4
AJ5
AJ6

AG5

Y6
Y5
V5

Y4
AA6
AA5
AC5
AC4
AD7
AC6
AF6
AD6
AF7
AF8
AF2
AF3

F4

E1

F3

F5

D2

D1

C3

C2

L8

F1

F2

H4

H5

V7

V8

V6

V9

U4

R5

R6

U8

P6

R9

P4

P5

L7

L6

L4

L5

AJ1
AG1
AA7
AD5

D3
H3
U5
M9

AJ3
AG2
AA9
AF4

E3
H2
U6
M5

Y33

Y34

Y35

Y36

Y37

Y38

Y39

Y9

FBH_CMD13
FBH_CMD29

FBH_CMD17
FBH_CMD1

J5
J4

J2

UG25E

5/23 FBD

FBD_D0
FBD_D1
FBD_D2
FBD_D3
FBD_D4
FBD_D5
FBD_D6
FBD_D7
FBD_D8
FBD_D9
FBD_D10
FBD_D11
FBD_D12
FBD_D13
FBD_D14
FBD_D15
FBD_D16
FBD_D17
FBD_D18
FBD_D19
FBD_D20
FBD_D21
FBD_D22
FBD_D23
FBD_D24
FBD_D25
FBD_D26
FBD_D27
FBD_D28
FBD_D29
FBD_D30
FBD_D31
FBD_D32
FBD_D33
FBD_D34
FBD_D35
FBD_D36
FBD_D37
FBD_D38
FBD_D39
FBD_D40
FBD_D41
FBD_D42
FBD_D43
FBD_D44
FBD_D45
FBD_D46
FBD_D47
FBD_D48
FBD_D49
FBD_D50
FBD_D51
FBD_D52
FBD_D53
FBD_D54
FBD_D55
FBD_D56
FBD_D57
FBD_D58
FBD_D59
FBD_D60
FBD_D61
FBD_D62
FBD_D63

FBD_DQM0
FBD_DQM1
FBD_DQM2
FBD_DQM3
FBD_DQM4
FBD_DQM5
FBD_DQM6
FBD_DQM7

FBD_DQS_WP0
FBD_DQS_WP1
FBD_DQS_WP2
FBD_DQS_WP3
FBD_DQS_WP4
FBD_DQS_WP5
FBD_DQS_WP6
FBD_DQS_WP7

GND_0718
GND_0719
GND_0720
GND_0721
GND_0722
GND_0723
GND_0724
GND_0725

1 2

1 2

GP104

10K_0402_5 %
RG567

10K_0402_5 %
RG576

AD2

FBH_CMD1
FBH_CMD2

FBH_CMD17
FBH_CMD18

0.1U_0402_16V7K

1

2

FBH_CMD0 <64>
FBH_CMD1 <64>
FBH_CMD2 <64>
FBH_CMD3 <64>
FBH_CMD4 <64>
FBH_CMD5 <64>
FBH_CMD6 <64>
FBH_CMD7 <64>
FBH_CMD8 <64>
FBH_CMD9 <64>
FBH_CMD10 <64>
FBH_CMD11 <64>
FBH_CMD12 <64>
FBH_CMD13 <64>
FBH_CMD14 <64>
FBH_CMD15 <64>
FBH_CMD16 <64>
FBH_CMD17 <64>
FBH_CMD18 <64>
FBH_CMD19 <64>
FBH_CMD20 <64>
FBH_CMD21 <64>
FBH_CMD22 <64>
FBH_CMD23 <64>
FBH_CMD24 <64>
FBH_CMD25 <64>
FBH_CMD26 <64>
FBH_CMD27 <64>
FBH_CMD28 <64>
FBH_CMD29 <64>
FBH_CMD30 <64>
FBH_CMD31 <64>

FBH_CLK0 <64>
FBH_CLK0# <64>
FBH_CLK1 <64>
FBH_CLK1# <64>

FBH_WCK01 <64>
FBH_WCK01 # <64>

FBH_WCK23 <64>
FBH_WCK23 # <64>

FBH_WCK45 <64>
FBH_WCK45 # <64>

FBH_WCK67 <64>
FBH_WCK67 # <64>

CG375

FBD_CMD0

AD1

FBD_CMD1

AD4

FBD_CMD2

AC1

FBD_CMD3

AC2

FBD_CMD4

AC3

FBD_CMD5

AA3

FBD_CMD6

AA2

FBD_CMD7

AA1

FBD_CMD8

AA4

FBD_CMD9

Y1

FBD_CMD10

Y2

FBD_CMD11

Y3

FBD_CMD12

V3

FBD_CMD13

V2

FBD_CMD14

V1

FBD_CMD15

L3

FBD_CMD16

L2

FBD_CMD17

L1

FBD_CMD18

M4

FBD_CMD19

M1

FBD_CMD20

M2

FBD_CMD21

M3

FBD_CMD22

P3

FBD_CMD23

P2

FBD_CMD24

P1

FBD_CMD25

R4

FBD_CMD26

R1

FBD_CMD27

R2

FBD_CMD28

R3

FBD_CMD29

U3

FBD_CMD30

U2

FBD_CMD31

U1

FBD_CMD32

V4

FBD_CMD33

AD3

FBD_CMD34

J3

FBD_CMD35

AC9

FBD_DBG_RFU1

P9

FBD_DBG_RFU2

Y8

FBD_CLK0

Y7

FBD_CLK0*

R8

FBD_CLK1

R7

FBD_CLK1*

AJ8

FBD_WCK01

AJ7

FBD_WCK01*

AG8

FBD_WCKB01

AG9

FBD_WCKB01*

AD8

FBD_WCK23

AD9

FBD_WCK23*

AC7

FBD_WCKB23

AC8

FBD_WCKB23*

J6

FBD_WCK45

J7

FBD_WCK45*

H7

FBD_WCKB45

H6

FBD_WCKB45*

P8

FBD_WCK67

P7

FBD_WCK67*

M7

FBD_WCKB67

M8

FBD_WCKB67*

+FBX_PLLA VDD_S+FBX_PLLA VDD_S+FBX_PLLA VDD_S +FBX_PLLA VDD_S

V11

FBD_PLL_AVDD

GP106

UNUSED

FBD

N17E-G1_BGA21 52~D@

10K_0402_5 %
RG579

1 2

10K_0402_5 %
RG574

1 2

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

N17E-G1(3/6) MEM Interface-S

N17E-G1(3/6) MEM Interface-S

N17E-G1(3/6) MEM Interface-S

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

56 103Monda y, January 09, 2017

56 103Monda y, January 09, 2017

56 103Monda y, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

D D

VDD_219
VDD_220
VDD_221
VDD_222
VDD_223
VDD_224
VDD_225
VDD_226
VDD_227
VDD_228
VDD_229
VDD_230
VDD_231
VDD_232
VDD_233
VDD_234
VDD_235
VDD_236
VDD_237
VDD_238
VDD_239
VDD_240
VDD_241
VDD_242
VDD_243
VDD_244
VDD_245
VDD_246
VDD_247
VDD_248
VDD_249
VDD_250
VDD_251
VDD_252
VDD_253
VDD_254
VDD_255
VDD_321
VDD_322
VDD_323
VDD_324
VDD_325
VDD_326
VDD_327
VDD_328
VDD_329
VDD_330
VDD_331
VDD_332
VDD_333
VDD_334
VDD_335
VDD_336
VDD_337
VDD_338
VDD_339
VDD_340
VDD_341
VDD_342
VDD_343
VDD_344
VDD_345
VDD_346
VDD_347
VDD_348
VDD_349
VDD_350
VDD_351
VDD_352
VDD_353
VDD_354
VDD_355
VDD_356

+NVVDD1_S

BB45
BB46
BB47
BB48
BC38
BC39
BC40
BC41
BC45
BC47
BC49
BD39
BD41
BD46
BD47
BD48
BD49
BD50
BD51
BE41
BE42
BE43
BE46
BE47
BE48
BE49
BE50
BE51
BE52
BF42
BF44
BF45
BF47
BF49
BF51
BG43
BG44
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U27
U28
U29
U30
U31
U32
U33
U34
U35
U36
U37
U38
U39
V13
V40
W19
W20
W21
W22
W23
W30
W31
W32
W33
W34

+NVVDD2_S

UG25J

23/23 VDDS

AP27

VDDS_057

AP28

VDDS_058

AP29

VDDS_059

AP35

VDDS_060

AP36

VDDS_061

AP37

VDDS_062

AP38

VDDS_063

AP39

VDDS_064

AV14

VDDS_065

AV15

VDDS_066

AV16

VDDS_067

AV17

VDDS_068

AV18

VDDS_069

AV24

VDDS_070

AV25

VDDS_071

AV26

VDDS_072

AV27

VDDS_073

AV28

VDDS_074

AV29

VDDS_075

AV35

VDDS_076

AV36

VDDS_077

AV37

VDDS_078

AV38

VDDS_079

AV39

VDDS_080

R14

VDDS_081

R15

VDDS_082

R16

VDDS_083

R17

VDDS_084

R18

VDDS_085

R24

VDDS_086

R25

VDDS_087

R26

VDDS_088

R27

VDDS_089

R28

VDDS_090

R29

VDDS_091

R35

VDDS_092

R36

VDDS_093

R37

VDDS_094

R38

VDDS_095

R39

VDDS_096

W14

VDDS_097

W15

VDDS_098

W16

VDDS_099

W17

VDDS_100

W18

VDDS_101

W24

VDDS_102

W25

VDDS_103

W26

VDDS_104

W27

VDDS_105

W28

VDDS_106

W29

VDDS_107

W35

VDDS_108

W36

VDDS_109

W37

VDDS_110

W38

VDDS_111

W39

VDDS_112

VDDS_SENSE

GNDS_SENSE

N17E-G1_BGA2152 ~D@

VDDS_001
VDDS_002
VDDS_003
VDDS_004
VDDS_005
VDDS_006
VDDS_007
VDDS_008
VDDS_009
VDDS_010
VDDS_011
VDDS_012
VDDS_013
VDDS_014
VDDS_015
VDDS_016
VDDS_017
VDDS_018
VDDS_019
VDDS_020
VDDS_021
VDDS_022
VDDS_023
VDDS_024
VDDS_025
VDDS_026
VDDS_027
VDDS_028
VDDS_029
VDDS_030
VDDS_031
VDDS_032
VDDS_033
VDDS_034
VDDS_035
VDDS_036
VDDS_037
VDDS_038
VDDS_039
VDDS_040
VDDS_041
VDDS_042
VDDS_043
VDDS_044
VDDS_045
VDDS_046
VDDS_047
VDDS_048
VDDS_049
VDDS_050
VDDS_051
VDDS_052
VDDS_053
VDDS_054
VDDS_055
VDDS_056

AC14
AC15
AC16
AC17
AC18
AC24
AC25
AC26
AC27
AC28
AC29
AC35
AC36
AC37
AC38
AC39
AF14
AF15
AF16
AF17
AF18
AF24
AF25
AF26
AG27
AG28
AG29
AG35
AG36
AG37
AG38
AG39
AK14
AK15
AK16
AK17
AK18
AK24
AK25
AK26
AK27
AK28
AK29
AK35
AK36
AK37
AK38
AK39
AP14
AP15
AP16
AP17
AP18
AP24
AP25
AP26

BM45
BM44

+NVVDD2_S

NVVDDS_VCC_SENSE_ S <94>
NVVDDS_VSS_SENSE_ S <94>

+1.35VSDGPU_S +1.35VSDGPU_S

UG25H

20/23 FBVDDQ

AA10

FBVDDQ_01

AA11

FBVDDQ_02

AA42

FBVDDQ_03

AA43

FBVDDQ_04

AC10

FBVDDQ_05

AC11

FBVDDQ_06

AC42

FBVDDQ_07

AC43

FBVDDQ_08

AD10

FBVDDQ_09

AD11

FBVDDQ_10

AD42

FBVDDQ_11

AD43

FBVDDQ_12

AF10

FBVDDQ_13

AF43

FBVDDQ_14

AG10

FBVDDQ_15

AG11

FBVDDQ_16

AG42

FBVDDQ_17

AG43

FBVDDQ_18

AJ10

FBVDDQ_19

AJ11

FBVDDQ_20

AJ42

FBVDDQ_21

AJ43

FBVDDQ_22

AK10

FBVDDQ_23

AK11

FBVDDQ_24

AK42

FBVDDQ_25

AK43

FBVDDQ_26

AM42

FBVDDQ_27

AM43

FBVDDQ_28

AN43

FBVDDQ_29

AR42

FBVDDQ_30

AR43

FBVDDQ_31

R42

FBVDDQ_76

R43

FBVDDQ_77

U10

FBVDDQ_78

U11

FBVDDQ_79

U43

FBVDDQ_80

V10

FBVDDQ_81

V42

FBVDDQ_82

V43

FBVDDQ_83

Y10

FBVDDQ_84

Y11

FBVDDQ_85

Y42

FBVDDQ_86

Y43

FBVDDQ_87

470U_X_2VY_R9M

10U_0603_6.3V6M

CG389

1

CG380

1

+

2

2

FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
FBVDDQ_43
FBVDDQ_44
FBVDDQ_45
FBVDDQ_46
FBVDDQ_47
FBVDDQ_48
FBVDDQ_49
FBVDDQ_50
FBVDDQ_51
FBVDDQ_52
FBVDDQ_53
FBVDDQ_54
FBVDDQ_55
FBVDDQ_56
FBVDDQ_57
FBVDDQ_58
FBVDDQ_59
FBVDDQ_60
FBVDDQ_61
FBVDDQ_62
FBVDDQ_63
FBVDDQ_64
FBVDDQ_65
FBVDDQ_66
FBVDDQ_67
FBVDDQ_68
FBVDDQ_69
FBVDDQ_70
FBVDDQ_71
FBVDDQ_72
FBVDDQ_73
FBVDDQ_74
FBVDDQ_75

FBVDDQ_SENSE

FB_VREF

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

N17E-G1_BGA2152 ~D@

AT43
K12
K14
K15
K17
K18
K20
K21
K23
K24
K26
K27
K29
K30
K32
K33
K35
K36
K38
K39
K41
L14
L15
L18
L20
L21
L23
L24
L26
L27
L30
L32
L33
L35
L36
L39
M10
M43
P10
P11
P42
P43
R10
R11

E52

P45

FBCAL_VDDQ_S

R44

FBCAL_GND_S

P44

FBCAL_TERM_S

R45

CSSN_B+_S<92>

CSSP_B+_S<92>

CSSN_NVVDD_S<92>

CSSP_NVVDD_S<92>
CSSN_NVVDDS_S<94>

CSSP_NVVDDS_S<94>

FB_VDDQ_SENSE_S <96>

1 2

RG590 40.2_0402_1%

1 2

RG599 40.2_0402_1%

1 2

RG584 60.4_0402_1%

+1.35VSDGPU_S

1 2

RG594
10_0402_1%

RG601
10_0402_1%

1 2
1 2

RG592
10_0402_1%

RG598
10_0402_1%

1 2
1 2

RG587
10_0402_1%

RG583
10_0402_1%

1 2

2

CG432

1

VIN1N_S
VIN1P_S

10U_0603_6.3V6M

VIN2N_S
VIN2P_S

2

VIN3N_S
VIN3P_S

CG383

1

10U_0603_6.3V6M

2

CG408

1

10U_0603_6.3V6M

3VSDGPU_EN_S<38>

12

RG802

665K_0402_1%

12

12

RG804

RG803

665K_0402_1%

665K_0402_1%

1 2

@

RG786 0_0402_5%

+NVVDD1_S

UG25G

19/23 VDD_2/2

AP21

VDD_145

AP22

VDD_146

AP23

VDD_147

AP30

VDD_148

AP31

VDD_149

AP32

VDD_150

AP33

VDD_151

AP34

VDD_152

AR13

VDD_153

AR40

VDD_154

AT14

VDD_155

AT15

VDD_156

AT16

VDD_157

AT17

VDD_158

AT18

VDD_159

AT19

VDD_160

AT20

VDD_161

AT21

VDD_162

AT22

VDD_163

AT23

VDD_164

AT24

VDD_165

AT25

VDD_166

AT26

VDD_167

AT27

VDD_168

AT28

VDD_169

AT29

VDD_170

AT30

VDD_171

AT31

VDD_172

AT32

VDD_173

AT33

VDD_174

AT34

VDD_175

AT35

VDD_176

AT36

VDD_177

AT37

VDD_178

AT38

VDD_179

AT39

VDD_180

AT42

VDD_181

AU43

VDD_182

AV19

VDD_183

AV20

C C

VDD_184

AV21

VDD_185

AV22

VDD_186

AV23

VDD_187

AV30

VDD_188

AV31

VDD_189

AV32

VDD_190

AV33

VDD_191

AV34

VDD_192

AV42

VDD_193

AV43

VDD_194

AV44

VDD_195

AW13

VDD_196

AW40

VDD_197

AW42

VDD_198

AW43

VDD_199

AW44

VDD_200

AW45

VDD_201

AY14

VDD_202

AY18

VDD_203

AY22

VDD_204

AY26

VDD_205

AY27

VDD_206

AY31

VDD_207

AY35

VDD_208

AY39

VDD_209

AY43

VDD_210

AY45

VDD_211

BA43

VDD_212

BA44

VDD_213

BA45

VDD_214

BA46

VDD_215

BA47

VDD_216

BB38

VDD_217

BB39

VDD_218

470U_X_2VY_R9M

10U_0603_6.3V6M

CG384

1

CG409

1

+

2

2

I2CC_SCL_S<53>
I2CC_SDA_S<53 >

10K_0402_5%

+3VSDGPU_S

RG588

+1.8VSDGPU_MAIN_S

12

RG604

@

1

2

12

1.8K_0402_1%

1U_0402_6.3V6K

0.1U_0402_16V7K
CG377

12

RG596

1.8K_0402_1%

CG870

3VSDGPU_EN_S_R

.1U_0402_16V7K

100P_0402_50V8J~D

1

CG391

2

UG27

4

VS

11

IN-1

12

IN+1

14

IN-2

15

Critical

IN+2

1

IN-3

Warning

2

IN+3

6

SCL

7

SDA

INA3221AIRGVR _VQFN16_4X4

+3VS

1

2

+5VALW

CG868

16

VPU

13

TC

10

PV

9

1 2

RG798 0_0 402_5%

8
5

A0

3

RG603

GND

10K_0402_1%

DGPU_PWR_EN

1

1V8_MAIN_EN_S

2

+3VSDGPU_S

UG29

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

1

TPS22961DNYR_W SON8

2

+3VSDGPU_S

+1.8VSDGPU_AON_S

12

RG595
10K_0402_1%

12

+1.8VSDGPU_AON_S

5

U68

3VSDGPU_EN_S_1 3VSDGPU_EN_S _R

IN B

VCC

4

OUT Y

IN A

GND

NL17SZ08DFT2G_ SC70-5

3

+3VSDGPU_S

6

VOUT

GND

10U_0603_6.3V6M

5

2

QG517B

G

PJT138KA 2N SOT36 3-6

6 1

S

D

1 2

RG785 10K _0402_5%

1

CG859

2

1

CG860

0.1U_0402_16V7K

2

OC_WARN#_S <53>

0.1U_0402_16V7K
CG915

1

@

2

22uF 10uF 4.7uF 1uF 0.1uF470uF

BK45

VDD_SENSE

B B

GND_SENSE

N17E-G1_BGA2152 ~D@

Place under GPU

+1.35VSDGPU_S +1.35VSDGPU_S

1

1

CG40310U_0603_6.3V6M

CG37610U_0603_6.3V6M

2

2

A A

1

1

1

1

1

CG40410U_0603_6.3V6M

CG40510U_0603_6.3V6M

CG39610U_0603_6.3V6M

CG43410U_0603_6.3V6M

CG38210U_0603_6.3V6M

2

2

2

2

2

NVVDD_VCC_SENSE_S <91>

BL45

NVVDD_VSS_SENSE_S <91>

1

1

CG4061U_0402_6.3V4Z

CG41110U_0603_6.3V6M

2

2

1

1

1

1

1

1

CG4121U_0402_6.3V4Z

CG3941U_0402_6.3V4Z

CG3991U_0402_6.3V4Z

CG4161U_0402_6.3V4Z

2

2

2

2

1

1

CG4221U_0402_6.3V4Z

CG4131U_0402_6.3V4Z

CG4271U_0402_6.3V4Z

CG3931U_0402_6.3V4Z

2

2

2

2

1

1

1

1

CG4071U_0402_6.3V4Z

2

1

CG4151U_0402_6.3V4Z

CG3951U_0402_6.3V4Z

CG4301U_0402_6.3V4Z

CG4181U_0402_6.3V4Z

2

2

2

2

1

1

1

1

1

CG3971U_0402_6.3V4Z

CG4311U_0402_6.3V4Z

2

2

1

CG3901U_0402_6.3V4Z

CG4231U_0402_6.3V4Z

CG4331U_0402_6.3V4Z

CG3791U_0402_6.3V4Z

2

2

2

2

1

1

1

1

CG4261U_0402_6.3V4Z

CG4011U_0402_6.3V4Z

CG4201U_0402_6.3V4Z

CG4211U_0402_6.3V4Z

2

2

2

2

1 139 24

FBVDDQ

Place under GPU

1

1

1

1

CG42510U_0603_6.3V6M

CG38110U_0603_6.3V6M

CG38710U_0603_6.3V6M

CG42810U_0603_6.3V6M

2

2

2

2

1V8_AON_EN_S_R1

1 2

RG782 0_0 402_5%@

1 2

1V8_MAIN_EN_S

RG781 0_0 402_5%

+1.8VS

12

RG589
10K_0402_5%

22U_0603_6.3V6M

CG388

+1.35VS_VGA_PGO OD_S<96>

@

+1.8VS

+1.8VSDGPU_AON_S

12

.1U_0402_16V7K

12

RG593

4.7K_0402_5%

CG867

DGPU_PWR_EN<22,38,41,45 ,53>

1

1

1

1

1

1

1

1

CG38622U_0603_6.3V6M

CG40222U_0603_6.3V6M

2

2

1

CG41022U_0603_6.3V6M

CG42922U_0603_6.3V6M

CG38522U_0603_6.3V6M

CG37822U_0603_6.3V6M

CG40022U_0603_6.3V6M

CG41722U_0603_6.3V6M

CG39222U_0603_6.3V6M

2

2

2

2

2

2

2

1V8_AON_EN_S<38>

1V8_MAIN_EN_S<53>

+1.8VS +1.8VSDGPU_AON_S

1U_0402_6.3V6K

1U_0402_6.3V6K

CG926

CG927

1

1

2

2

3
2

DAN202UT106_SC70 -3
DG22

+1V8_AON / +1V8_MAIN

+1.8VS

1V8_AON_EN_S_R

+5VS

+1.8VSDGPU_AON_S

1

2

1V8_AON_EN_S_R

1

UG30

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

AOZ1331_SON14_ 2X3

VOUT1
VOUT1

VOUT2
VOUT2

12

RG778
100K_0201_5 %

14
13

CG424

12

1 2

220P_0402_5 0V8J

CT1

11

GND

CG414

10

1 2

CT2

9
8

15

GPAD

220P_0402_5 0V8J

.1U_0402_16V7K

1

2

+1.8VSDGPU_MAIN_S

CG928

+1.8VSDGPU_AON_S

10U_0603_6.3V6M

CG419

1

2

.1U_0402_16V7K

10U_0603_6.3V6M

CG929

CG398

1

1

2

2

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

5

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

N17E-G1(4/6) Power-S

N17E-G1(4/6) Power-S

N17E-G1(4/6) Power-S

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

57 103Monday, January 09, 2017

57 103Monday, January 09, 2017

57 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

UG25M

22/23 GND_3/3

BL43

GND_482

BL5

GND_483

BL7

GND_484

BM2

GND_485

BM3

GND_486

C1

GND_487

C29

GND_488

C33

GND_489

C5

GND_490

C51

GND_491

C52

GND_492

D10

GND_493

D12

GND_494

D13

GND_495

D16

GND_496

D19

GND_497

D22

GND_498

D24

GND_499

D25

GND_500

D28

GND_501

D30

GND_502

D31

GND_503

D34

GND_504

D37

GND_505

D4

GND_506

D40

GND_507

D43

GND_508

D46

GND_509

D49

GND_510

D7

GND_511

E2

GND_512

E4

GND_513

E48

GND_514

E5

GND_515

E51

GND_516

E8

GND_517

F10

GND_518

F13

GND_519

F16

GND_520

F17

GND_521

F19

GND_522

F21

GND_523

F22

GND_524

F25

GND_525

F28

GND_526

F31

GND_527

F34

GND_528

F35

GND_529

F37

GND_530

F40

GND_531

F43

GND_532

F44

GND_533

F46

GND_534

F52

GND_535

F7

GND_536

G2

GND_537

G38

GND_538

G4

GND_539

G47

GND_540

G49

GND_541

G51

GND_542

G6

GND_543

H1

GND_544

H10

GND_545

H13

GND_546

H16

GND_547

H19

GND_548

H22

GND_549

H25

GND_550

H28

GND_551

H31

GND_552

H34

GND_553

H37

GND_554

H40

GND_555

H43

GND_556

J1

GND_557

J12

GND_558

J17

GND_559

J20

GND_560

J38

GND_561

J49

GND_562

J52

GND_563

K13

GND_564

K16

GND_565

K19

GND_566

K2

GND_567

K22

GND_568

K25

GND_569

K28

GND_570

K31

GND_571

K34

GND_572

K37

GND_573

K4

GND_574

K40

GND_575

K45

GND_576

K47

GND_577

K49

GND_578

K51

GND_579

K6

GND_580

K8

GND_581

M52

GND_582

M6

GND_583

N10

GND_584

N2

GND_585

N4

GND_586

N43

GND_587

N45

GND_588

N47

GND_589

N49

GND_590

N51

GND_591

BL40

GND_481

N17E-G1_BGA2152~D@

GND_592
GND_593
GND_594
GND_595
GND_596
GND_597
GND_598
GND_599
GND_600
GND_601
GND_602
GND_603
GND_604
GND_605
GND_606
GND_607
GND_608
GND_609
GND_610
GND_611
GND_612
GND_613
GND_614
GND_615
GND_616
GND_617
GND_618
GND_619
GND_620
GND_621
GND_622
GND_623
GND_624
GND_625
GND_626
GND_627
GND_628
GND_629
GND_630
GND_631
GND_632
GND_633
GND_634
GND_635
GND_636
GND_637
GND_638
GND_639
GND_640
GND_641
GND_642
GND_643
GND_644
GND_645
GND_646
GND_647
GND_648
GND_649
GND_650
GND_651
GND_652
GND_653
GND_654
GND_655
GND_656
GND_657
GND_658
GND_659
GND_660
GND_661
GND_662
GND_663
GND_664
GND_665
GND_666
GND_667
GND_668
GND_669
GND_670
GND_671
GND_672
GND_673
GND_674
GND_675
GND_676
GND_677
GND_678
GND_679
GND_680
GND_681
GND_682
GND_683
GND_684
GND_685
GND_686
GND_687
GND_688
GND_689
GND_690
GND_691
GND_692
GND_693

N6
N8
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P51
R49
R52
T10
T14
T15
T16
T17
T18
T19
T2
T20
T21
T22
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
T33
T34
T35
T36
T37
T38
T39
T4
T43
T45
T47
T49
T51
T6
T8
U7
U9
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
V31
V32
V33
V34
V35
V36
V37
V38
V39
V49
V52
W10
W2
W4
W43
W45

AR20
AR21
AR22
AR23
AR24
AR25
AR26
AR27
AR28
AR29
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AR38
AR39

AR52

AU10
AU14
AU15
AU16
AU17
AU18
AU19

AU20
AU21
AU22
AU23
AU24
AU25
AU26
AU27
AU28
AU29
AU30
AU31
AU32
AU33
AU34
AU35
AU36
AU37
AU38
AU39

AU45
AU47
AU49
AU51

AW14
AW15
AW16
AW17
AW18
AW19
AW20
AW21
AW22
AW23
AW24
AW25
AW26
AW27
AW28
AW29
AW30
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AW39

AW46
AW52

AT51
AT52

AV45

AY10

AY47
AY49
AY51

UG25L

17/23 GND_2/3

GND_238
GND_239
GND_240
GND_241
GND_242
GND_243
GND_244
GND_245
GND_246
GND_247
GND_248
GND_249
GND_250
GND_251
GND_252
GND_253
GND_254
GND_255
GND_256
GND_257

AR4

GND_258
GND_259

AR9

GND_260

AT4

GND_261

AT5

GND_262
GND_263
GND_264

AT8

GND_265
GND_266
GND_267
GND_268
GND_269
GND_270
GND_271
GND_272

AU2

GND_273
GND_274
GND_275
GND_276
GND_277
GND_278
GND_279
GND_280
GND_281
GND_282
GND_283
GND_284
GND_285
GND_286
GND_287
GND_288
GND_289
GND_290
GND_291
GND_292
GND_293

AU4

GND_294
GND_295
GND_296
GND_297
GND_298

AU6

GND_299

AU8

GND_300

AV4

GND_301
GND_302

AV9

GND_303
GND_304
GND_305
GND_306
GND_307
GND_308
GND_309
GND_310
GND_311
GND_312
GND_313
GND_314
GND_315
GND_316
GND_317
GND_318
GND_319
GND_320
GND_321
GND_322
GND_323
GND_324
GND_325
GND_326
GND_327
GND_328
GND_329

AW4

GND_330
GND_331

AW5

GND_332
GND_333

AW8

GND_334
GND_335

AY2

GND_336

AY4

GND_337
GND_338
GND_339
GND_340

AY6

GND_341

AY8

GND_342

B1

GND_343

B10

GND_344

B13

GND_345

B16

GND_346

B19

GND_347

B2

GND_348

B22

GND_349

B25

GND_350

B28

GND_351

B31

GND_352

B34

GND_353

B37

GND_354

B40

GND_355

B43

GND_356

B46

GND_357

B48

GND_358

N17E-G1_BGA2152~D@

GND_361
GND_362
GND_363
GND_364
GND_365
GND_366
GND_367
GND_368
GND_369
GND_370
GND_371
GND_372
GND_373
GND_374
GND_375
GND_376
GND_377
GND_378
GND_379
GND_380
GND_381
GND_382
GND_383
GND_384
GND_385
GND_386
GND_387
GND_388
GND_389
GND_390
GND_391
GND_392
GND_393
GND_394
GND_395
GND_396
GND_397
GND_398
GND_399
GND_400
GND_401
GND_402
GND_403
GND_404
GND_405
GND_406
GND_407
GND_408
GND_409
GND_410
GND_411
GND_412
GND_413
GND_414
GND_415
GND_416
GND_417
GND_418
GND_419
GND_420
GND_421
GND_422
GND_423
GND_424
GND_425
GND_426
GND_427
GND_428
GND_429
GND_430
GND_431
GND_432
GND_433
GND_434
GND_435
GND_436
GND_437
GND_438
GND_439
GND_440
GND_441
GND_442
GND_443
GND_444
GND_445
GND_446
GND_447
GND_448
GND_449
GND_450
GND_451
GND_452
GND_453
GND_454
GND_455
GND_456
GND_457
GND_458
GND_459
GND_460
GND_461
GND_462
GND_463
GND_464
GND_465
GND_466
GND_467
GND_468
GND_469
GND_470
GND_471
GND_472
GND_473
GND_474
GND_475
GND_476
GND_477
GND_478
GND_479
GND_359
GND_360

B52
B7
BA48
BB49
BC13
BC16
BC19
BC2
BC22
BC25
BC28
BC31
BC34
BC37
BC4
BC51
BC6
BC8
BD26
BD29
BD32
BD35
BD38
BD52
BE10
BE13
BE15
BE16
BE18
BE19
BE21
BE22
BE24
BE25
BE27
BE28
BE30
BE31
BE33
BE34
BE36
BE37
BE39
BE40
BF2
BF4
BF41
BF6
BG10
BG13
BG16
BG19
BG22
BG25
BG28
BG31
BG34
BG37
BG40
BG42
BG7
BH15
BH18
BH2
BH21
BH24
BH27
BH30
BH33
BH36
BH39
BH42
BH5
BJ10
BJ12
BJ13
BJ14
BJ15
BJ16
BJ17
BJ18
BJ19
BJ20
BJ21
BJ22
BJ23
BJ24
BJ25
BJ26
BJ27
BJ28
BJ29
BJ30
BJ31
BJ32
BJ33
BJ34
BJ35
BJ36
BJ37
BJ38
BJ39
BJ40
BJ41
BJ42
BJ43
BJ7
BK1
BL1
BL10
BL13
BL16
BL19
BL2
BL22
BL25
BL28
BL31
BL34
B5
B51

AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AD39
AD44

AG14
AG15
AG16
AG17
AG18
AG24
AG25
AG26

AG30
AG31
AG32
AG33
AG34
AG44
AH10

AH43
AH45
AH47
AH49
AH51

AA49
AB10

AB14
AB15
AB16
AB17
AB18
AB19

AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB31
AB32
AB33
AB34
AB35
AB36
AB37
AB38
AB39

AB43
AB45
AB47
AB49
AB51

AE10

AE43
AE45
AE47
AE49
AE51

AF19
AF20
AF21
AF22
AF23
AF27
AF28
AF29
AF35
AF36
AF37
AF38
AF39
AF45

UG25K

16/23 GND_1/3

A2

GND_001

A26

GND_002

A29

GND_003

A3

GND_004

A32

GND_005

A50

GND_006

A51

GND_007
GND_008

AA8

GND_009
GND_010
GND_011
GND_012
GND_013
GND_014
GND_015
GND_016

AB2

GND_017
GND_018
GND_019
GND_020
GND_021
GND_022
GND_023
GND_024
GND_025
GND_026
GND_027
GND_028
GND_029
GND_030
GND_031
GND_032
GND_033
GND_034
GND_035
GND_036
GND_037

AB4

GND_038
GND_039
GND_040
GND_041
GND_042
GND_043

AB6

GND_044

AB8

GND_045
GND_046
GND_047
GND_048
GND_049
GND_050
GND_051
GND_052
GND_053
GND_054
GND_055
GND_056
GND_057
GND_058
GND_059
GND_060
GND_061
GND_062
GND_063
GND_064
GND_065
GND_066
GND_067
GND_068
GND_069
GND_070
GND_071
GND_072
GND_073

AE2

GND_074

AE4

GND_075
GND_076
GND_077
GND_078
GND_079
GND_080

AE6

GND_081

AE8

GND_082

AF1

GND_083
GND_084
GND_085
GND_086
GND_087
GND_088
GND_089
GND_090
GND_091
GND_092
GND_093
GND_094
GND_095
GND_096
GND_097

AF5

GND_098
GND_099
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106

AG3

GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114

AH2

GND_115

AH4

GND_116
GND_117
GND_118
GND_119
GND_120
GND_121

N17E-G1_BGA2152~D@

GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_200
GND_201
GND_202
GND_203
GND_204
GND_205
GND_206
GND_207
GND_208
GND_209
GND_210
GND_211
GND_212
GND_213
GND_214
GND_215
GND_216
GND_217
GND_218
GND_219
GND_220
GND_221
GND_222
GND_223
GND_224
GND_225
GND_226
GND_227
GND_228
GND_229
GND_230
GND_231
GND_232
GND_233
GND_234
GND_235
GND_236
GND_237
GND_480

GND_H
GND_F

AH6
AH8
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ2
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AJ37
AJ38
AJ39
AJ9
AK1
AK44
AK47
AL10
AL14
AL15
AL16
AL17
AL18
AL19
AL2
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AL33
AL34
AL35
AL36
AL37
AL38
AL39
AL4
AL43
AL45
AL47
AL49
AL51
AL6
AL8
AM4
AM9
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AN39
AN4
AN5
AN8
AP10
AP2
AP4
AP43
AP45
AP47
AP49
AP51
AP6
AP8
AR14
AR15
AR16
AR17
AR18
AR19
BL37
BD24
BC24

+NVVDD1_S +NV VDD1_S

0.1U_0201_6.3V6K
CG444

BA10
BB14
BC14

AM10
AM11
AN10
AN11
AR10
AR11
AT10
AT11
AV10
AV11
AW10
AW11

+1.8VSDGP U_AON_S

+1.8VSDGP U_MAIN_S

UG25I

21/23 NC/1V8

AT9

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10

4.7U_0402_6.3V6M

1V8_AON_1
1V8_AON_2
1V8_AON_3

VDD18_01
VDD18_02
VDD18_03
VDD18_04
VDD18_05
VDD18_06
VDD18_07
VDD18_08
VDD18_09
VDD18_10
VDD18_11
VDD18_12

N17E-G1_BGA2152~D@

0.1U_0201_6.3V6K

1U_0402_6.3V4Z

CG442

CG446

CG441

1

1

1

2

2

2

BA6

BA9
BD14
BE12

D D

C C

BG6

BH6

BJ11

BJ9

BK44

+1.8VSDGP U_AON_S

1

2

Under GPU

+1.8VSDGP U_MAIN_S

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
CG438

1

1

2

2

B B

+1.8VSDGP U_MAIN_S

0.1U_0201_6.3V6K
CG435

1

1

2

2

1U_0402_6.3V4Z

4.7U_0402_6.3V6M
CG443

CG440

1

1

2

2

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K
CG449

CG448

1

1

2

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

CG437

0.1U_0201_6.3V6K
CG445

CG436

CG447

1

1

2

2

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

CG439

1

2

CG451

CG450

1

1

2

2

AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AA39
AB13
AB40
AC19
AC20
AC21
AC22
AC23
AC30
AC31
AC32
AC33
AC34
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AE31
AE32
AE33
AE34
AE35
AE36
AE37
AE38
AE39

AG13
AG19
AG20
AG21
BG45
BG46
BG47
BG48
BG49
BG50
BG51
BG52
BH44
BH45
BH47
BH48
BH49
BH50
BH51
BH52

BK47
BK48
BK49
BK50
BK51

AF13
AF30
AF31
AF32
AF33
AF34
AF40

BJ44
BJ45
BJ46
BJ47
BJ48
BJ49
BJ50
BJ51
BJ52

UG25F

18/21 VDD_1/2

VDD_001
VDD_002
VDD_003
VDD_004
VDD_005
VDD_006
VDD_007
VDD_008
VDD_009
VDD_010
VDD_011
VDD_012
VDD_013
VDD_014
VDD_015
VDD_016
VDD_017
VDD_018
VDD_019
VDD_020
VDD_021
VDD_022
VDD_023
VDD_024
VDD_025
VDD_026
VDD_027
VDD_028
VDD_029
VDD_030
VDD_031
VDD_032
VDD_033
VDD_034
VDD_035
VDD_036
VDD_037
VDD_038
VDD_039
VDD_040
VDD_041
VDD_042
VDD_043
VDD_044
VDD_045
VDD_046
VDD_047
VDD_048
VDD_049
VDD_050
VDD_051
VDD_052
VDD_053
VDD_054
VDD_055
VDD_056
VDD_057
VDD_058
VDD_059
VDD_060
VDD_061
VDD_062
VDD_063
VDD_064
VDD_065
VDD_066
VDD_067
VDD_068
VDD_069
VDD_070
VDD_071
VDD_072
VDD_073
VDD_074
VDD_075
VDD_256
VDD_257
VDD_258
VDD_259
VDD_260
VDD_261
VDD_262
VDD_263
VDD_264
VDD_265
VDD_266
VDD_267
VDD_268
VDD_269
VDD_270
VDD_271
VDD_272
VDD_273
VDD_274
VDD_275
VDD_276
VDD_277
VDD_278
VDD_279
VDD_280
VDD_281
VDD_282
VDD_283
VDD_284
VDD_285

AG22

VDD_076

AG23

VDD_077

AG40

VDD_078

AH14

VDD_079

AH15

VDD_080

AH16

VDD_081

AH17

VDD_082

AH18

VDD_083

AH19

VDD_084

AH20

VDD_085

AH21

VDD_086

AH22

VDD_087

AH23

VDD_088

AH24

VDD_089

AH25

VDD_090

AH26

VDD_091

AH27

VDD_092

AH28

VDD_093

AH29

VDD_094

AH30

VDD_095

AH31

VDD_096

AH32

VDD_097

AH33

VDD_098

AH34

VDD_099

AH35

VDD_100

AH36

VDD_101

AH37

VDD_102

AH38

VDD_103

AH39

VDD_104

AK19

VDD_105

AK20

VDD_106

AK21

VDD_107

AK22

VDD_108

AK23

VDD_109

AK30

VDD_110

AK31

VDD_111

AK32

VDD_112

AK33

VDD_113

AK34

VDD_114

AL13

VDD_115

AL40

VDD_116

AM14

VDD_117

AM15

VDD_118

AM16

VDD_119

AM17

VDD_120

AM18

VDD_121

AM19

VDD_122

AM20

VDD_123

AM21

VDD_124

AM22

VDD_125

AM23

VDD_126

AM24

VDD_127

AM25

VDD_128

AM26

VDD_129

AM27

VDD_130

AM28

VDD_131

AM29

VDD_132

AM30

VDD_133

AM31

VDD_134

AM32

VDD_135

AM33

VDD_136

AM34

VDD_137

AM35

VDD_138

AM36

VDD_139

AM37

VDD_140

AM38

VDD_141

AM39

VDD_142

AP19

VDD_143

AP20

VDD_144

BK52

VDD_286

BL46

VDD_287

BL47

VDD_288

BL48

VDD_289

BL49

VDD_290

BL50

VDD_291

BL51

VDD_292

BL52

VDD_293

BM47

VDD_294

BM48

VDD_295

BM49

VDD_296

BM50

VDD_297

BM51

VDD_298

N14

VDD_299

N18

VDD_300

N22

VDD_301

N26

VDD_302

N27

VDD_303

N31

VDD_304

N35

VDD_305

N39

VDD_306

P13

VDD_307

P40

VDD_308

R19

VDD_309

R20

VDD_310

R21

VDD_311

R22

VDD_312

R23

VDD_313

R30

VDD_314

R31

VDD_315

R32

VDD_316

R33

VDD_317

R34

VDD_318

U14

VDD_319

U15

VDD_320

N17E-G1_BGA2152~D@

Under GPU

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

5

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

N17E-G1(5/6) Power,GND-S

N17E-G1(5/6) Power,GND-S

N17E-G1(5/6) Power,GND-S

Document Number Re v

Document Number Re v

Document Number Re v

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

58 103Monday, January 09, 2017

58 103Monday, January 09, 2017

58 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

+1.8VSDGPU_AON_S

D D

47uF

VID_PLLVDD

SP_PLLVDD
GPCPLL_AVDD

1

1

4.7uF10uF22uF 0.1uF1uF

RG625
100K_0402_1%

11

1 2

@

STRAP0_S

RG607
100K_0402_1%

1 2

@

STRAP1_S

6

RG614
100K_0402_1%

1 2

RG634
100K_0402_1%

1 2

RG627
100K_0402_1%

1 2

@

RG613
100K_0402_1%

1 2

STRAP2_S

RG628
100K_0402_1%

1 2

@

RG633
100K_0402_1%

1 2

STRAP3_S

RG617
100K_0402_1%

1 2

@

RG611
100K_0402_1%

1 2

STRAP4_S

RG610
100K_0402_1%

1 2

STRAP5_S

RG630
100K_0402_1%

1 2

UG25T

15/23 MISC 2

BL3

STRAP0

BL4

STRAP1

BM4

STRAP2

BM5

STRAP3

BK5

STRAP4

BJ5

STRAP5

N17E-G1_BGA2152~D@

ROM_CS*

ROM_SI

ROM_SO

ROM_SCLK

BUFRST*

BJ4
BK2

BK4
BK3

BF9

GPU_BUFRST#_S

ROM_CS#_S
ROM_SI_S

ROM_SO_S
ROM_SCLK_S

@

T58
PAD~D

RG615
100K_0402_1%

1 2

RG612
100K_0402_1%

1 2

@

1 2

1 2

@

RG606
100K_0402_1%

RG632
100K_0402_1%

+1.8VSDGPU_AON_S

RG629
100K_0402_1%

1 2

RG616
100K_0402_1%

1 2

MICRON

MT58K256M32 - 100:A

Strap 0 Stra p1 Stra p2 Strap3 Strap4 Strap5 ROM_SO ROM_ SI ROM_SC LK

PD

PD

PD

1 2

LG11
PBY160808T-301Y-N

CG463

1

2

.1U_0402_16V7K

CG452

PD

100kOhm

PD

100kOhm

.1U_0402_16V7K

CG459

1

2

1

2

100kOhm

100kOhm

.1U_0402_16V7K

CG462

x

v

+1.8VSDGPU_MAIN_S

Master

Slave

1 2

C C

B B

100kOhm

PD

100kOhm

LG12
PBY160808T-300Y-N_2P

100kOhm

100kOhm

+1.8VSDGPU_MAIN_S

22U_0603_6.3V6M

12

Under GPU

PD

PU

100kOhm

PD

PD

100kOhm

Under GPU

10U_0603_6.3V6M

47U_0805_6.3V6M~D

12

.1U_0402_16V7K

1

2

.1U_0402_16V7K

CG454

CG458

1

1

2

2

.1U_0402_16V7K

.1U_0402_16V7K

CG456

CG460

1

1

2

2

12

100kOhm

100kOhm

100kOhm

CG461

CG453

RG623
10K_0402_5%

PD

U42

BJ6
BL6

100kOhm

100kOhm

UG25S

14/23 XTAL/PLL

SP_PLLVDD
VID_PLLVDD

GPCPLL_AVDD0
GPCPLL_AVDD1
XS_PLLVDD

XTAL_SSIN
XTAL_IN

PD

PU

1

1 2

YG2

1

GND

100kOhm

100kOhm

100kOhm

N17E-G1_BGA2152~D@

RG624
10M_0402_5%

2

PU

100kOhm

PU

PU

PD

100kOhm

BD12
BC12

AF11
BB24

XTALIN_S XTALOUT_S

CG457
22P_0402_50V8J

PD

PU

PD

XTAL_OUTBUFF

XTAL_OUT

3

3

GND

4

27MHZ_16PF_7V27000011

BK6
BM6

XTALOUTBUFF_R_S

CG464
22P_0402_50V8J

12

RG619
10K_0402_5%

ROM_CS#_S

RG631
10K_0402_5%

DGPU_ROM_SO_S_RROM_SO_S

1 2

RG626 0_0402_5%

+1.8VSDGPU_AON_S

12

UG35

1

CS#

2

DO(IO1)

3

WP#(IO2)

4

GND

W25Q80EW SSIG_SO8

PN : SA00009ZQ00

DGPU VBIOS ROM

VCC

HOLD#(IO3)

DI(IO0)

CLK

+1.8VSDGPU_AON_S

8
7

DGPU_ROM_SCLK_S

6

DGPU_ROM_SI_S

5

1

CG465
.1U_0402_16V7K

2

RG621
33_0402_5%

1 2
1 2

RG620
33_0402_5%

ROM_SCLK_S
ROM_SI_S

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

N17E-G1(6/6) Strap Pin,ROM-S

N17E-G1(6/6) Strap Pin,ROM-S

N17E-G1(6/6) Strap Pin,ROM-S

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

59 103Monday, January 09, 2017

59 103Monday, January 09, 2017

59 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

UG25V

11/23 MIOA

+1.8VSDGPU_MAIN_S

RG686

1

2

RG765

1

2

+1.8VSDGPU_MAIN_S

12

+MIOA_VREF_S

12

RG687
1K_0402_1%

+1.8VSDGPU_MAIN_S

12

+MIOB_VREF_S

12

RG766
1K_0402_1%

RG684

49.9_0402_1%

1 2
1 2

RG685

49.9_0402_1%

RG763

49.9_0402_1%

1 2
1 2

RG764

49.9_0402_1%

12mils

+MIOA_VDDQ_S

MIOA_GND_S

12mils

+MIOB_VDDQ_S

MIOB_GND_S

AM5

MIOA_CAL_PD_VDDQ

AM6

MIOA_CAL_PU_GND

AM7

MIOA_VREF

UG25U

12/23 MIOB

AV7

MIOB_CAL_PD_VDDQ

AV8

MIOB_CAL_PU_GND

AW9

MIOB_VREF

MIOA_CTL3
MIOA_HSYNC
MIOA_VSYNC

MIOA_CLKOUT

MIOA_CLKIN

N17E-G1_BGA2152~D@

MIOB_HSYNC

MIOB_VSYNC

GP106GP104

MIOB_CLKOUT

D D

1K_0402_1%

CG668

.1U_0402_16V7K

C C

+1.8VSDGPU_MAIN_S

1K_0402_1%

B B

CG905

.1U_0402_16V7K

UNUSEDMIOB

MIOA_D0
MIOA_D1
MIOA_D2
MIOA_D3
MIOA_D4
MIOA_D5
MIOA_D6
MIOA_D7
MIOA_D8

MIOA_D9
MIOA_D10
MIOA_D11

MIOA_DE

MIOB_D0
MIOB_D1
MIOB_D2
MIOB_D3
MIOB_D4
MIOB_D5
MIOB_D6
MIOB_D7
MIOB_D8

MIOB_D9
MIOB_D10
MIOB_D11

MIOB_CTL3

MIOB_DE

MIOB_CLKIN

AN9
AM2
AN7
AN6
AR1
AR6
AR5
AM8
AN3
AR8
AR3
AR2

AT7
AM1
AR7
AN1

AN2
AM3

AT3
AV6
AT2
AT1
AW6
AV2
AV1
AV3
AW3
BA8
AW7
BB8

BB7
AV5
BA7
AW2

AW1
AT6

20160201_Update Net Name

MIOA_D0 <48>
MIOA_D1 <48>
MIOA_D2 <48>
MIOA_D3 <48>
MIOA_D4 <48>
MIOA_D5 <48>
MIOA_D6 <48>
MIOA_D7 <48>
MIOA_D8 <48>
MIOA_D9 <48>
MIOA_D10 <48>
MIOA_D11 <48>

MIOA_CTL3 <48>
MIOA_HSYNC <48>
MIOA_VSYNC <48>
MIOA_DE <48>

MIOA_CLKOUT_S_TO_M <48>

MIOA_CLKIN_M_TO_S <48>

N17E-G1_BGA2152~D@

A A

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2016/02/01 2017/12/31

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N17E-G1(1/6) PCIE,GPIO

N17E-G1(1/6) PCIE,GPIO

N17E-G1(1/6) PCIE,GPIO

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

1.0

1.0

1.0

60 103Monday, January 09, 2017

60 103Monday, January 09, 2017

60 103Monday, January 09, 2017

5

FBE_EDC3<56>
FBE_EDC2<56>
FBE_EDC1<56>
FBE_EDC0<56>

FBE_DBI3<56>
FBE_DBI2<56>
FBE_DBI1<56>

+1.35VSDGPU_S

RG638 1K_0402 _1%
RG643 121_040 2_1%

FBE_DBI0<56>

FBE_CMD15<56>

FBE_CMD9<56>
FBE_CMD11<56>
FBE_CMD12<56>
FBE_CMD10<56>

FBE_CMD4<56>
FBE_CMD7<56>
FBE_CMD8<56>
FBE_CMD3<56>
FBE_CMD5<56>
FBE_CMD14<56>

FBE_CMD6<56>
FBE_CMD0<56>
FBE_CMD2<56>
FBE_CMD13<56>

FBE_WCK23#<56 >
FBE_WCK23<56>

FBE_WCK01#<56 >
FBE_WCK01<56>

FBE_CMD1<56>

D D

C C

+1.35VSDGPU_S

12

RG640
549_0402_1%

1 2

12

RG645
931_0402_1%

1

D

MEM_VREF_S<53,62,63,64>

B B

2

G

3

QG513

S

MESS138W-G_SOT 323-3

RG644

+FBE_VREFC

1.33K_0402_1%

FBE_CLK0<56>
FBE_CLK0#<56>

W=16mils

1

1

CG483

CG481

2

2

820P_0402_25V7

820P_0402_25V7

12
12

+1.35VSDGPU_S

4

D12

E12
R12

K11
K10
H11

K12

W12
H13

M13
A12

M11

K13

A10

B14
D11

D14

H14

K14

M14
P14

V14
W10

A11
A14

D10
G14

H10

M10

N14

W11
W14

UG91

MF=0 MF=1 MF= 0MF=1

D3

EDC0 EDC3
EDC1 EDC2

T12

EDC2 EDC1

T3

EDC3 EDC0

E3

DBI0# DBI3#
DBI1# DBI2#
DBI2# DBI1#

R3

DBI3# DBI0#

CK
CK#
CKE# WE#

J11

BA0/A2 BA2/A4

L10

BA1/A5 BA3/A3

L11

BA2/A4 BA0/A2

J10

BA3/A3 BA1/A5

L4

A8/A7 A10/A0

J5

A9/A1 A11/A6

J4

A10/A0 A8/A7

L5

A11/A6 A9/A1

K5

A12/A13
A14/A15

MF
ZQ

M2

TCK
TDI
TDO

H2

TMS

K4

ABI#

H4

RAS# CAS#

M4

CAS# RAS#
WE# CKE#

D5

WCK01# WCK23#

D4

WCK01 WCK23

T5

WCK23# WCK01#

T4

WCK23 WCK01

VREFC

K2

RESET#

VSS_1

A5

VSS_2

B1

VSS_3
VSS_4

D1

VSS_5
VSS_6
VSS_7

F1

VSS_8

F14

VSS_9

H1

VSS_10
VSS_11

J12

VSS_12

J3

VSS_13

K1

VSS_14
VSS_15

K3

VSS_16

L12

VSS_17

L3

VSS_18

M1

VSS_19
VSS_20

P1

VSS_21
VSS_22

T1

VSS_23

T11

VSS_24

T14

VSS_25

V1

VSS_26
VSS_27
VSS_28

W5

VSS_29

A1

VDD_1
VDD_2
VDD_3

A4

VDD_4
VDD_5

G1

VDD_6
VDD_7
VDD_8

H5

VDD_9

J1

VDD_10

J14

VDD_11

L1

VDD_12

L14

VDD_13
VDD_14

M5

VDD_15

N1

VDD_16
VDD_17

T10

VDD_18

W1

VDD_19
VDD_20

190-BAL L

VDD_21

W4

VDD_22

SGRAM GDDR5X

3

MF=1 MF=0

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15

DQ9 DQ16

DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23

DQ0 DQ24

DQ1 DQ25

DQ2 DQ26

DQ3 DQ27

DQ4 DQ28

DQ5 DQ29

DQ6 DQ30

DQ7 DQ31

MICRON_GDDR5X

B4
B3
C4
C3
F4
F3
G4
G3
B11
B12
C11
C12
F11
F12
G11
G12
V11
V12
U11
U12
P11
P12
N11
N12
V4
V3
U4
U3
P4
P3
N4
N3

A13

VDDQ_1

A2

VDDQ_2

B10

VDDQ_3

B5

VDDQ_4

C1

VDDQ_5

C13

VDDQ_6

C14

VDDQ_7

C2

VDDQ_8

E1

VDDQ_9

E11

VDDQ_10

E13

VDDQ_11

E14

VDDQ_12

E2

VDDQ_13

E4

VDDQ_14

F10

VDDQ_15

F5

VDDQ_16

G13

VDDQ_17

G2

VDDQ_18

H12

VDDQ_19

H3

VDDQ_20

J13

VDDQ_21

J2

VDDQ_22

L13

VDDQ_23

L2

VDDQ_24

M12

VDDQ_25

M3

VDDQ_26

N13

VDDQ_27

N2

VDDQ_28

P10

VDDQ_29

P5

VDDQ_30

R1

VDDQ_31

R11

VDDQ_32

R13

VDDQ_33

R14

VDDQ_34

R2

VDDQ_35

R4

VDDQ_36

U1

VDDQ_37

U13

VDDQ_38

U14

VDDQ_39

U2

VDDQ_40

V10

VDDQ_41

V5

VDDQ_42

W13

VDDQ_43

W2

VDDQ_44

B13

VSSQ_1

B2

VSSQ_2

C10

VSSQ_3

C5

VSSQ_4

D13

VSSQ_5

D2

VSSQ_6

E10

VSSQ_7

E5

VSSQ_8

F13

VSSQ_9

F2

VSSQ_10

G10

VSSQ_11

G5

VSSQ_12

N10

VSSQ_13

N5

VSSQ_14

P13

VSSQ_15

P2

VSSQ_16

R10

VSSQ_17

R5

VSSQ_18

T13

VSSQ_19

T2

VSSQ_20

U10

VSSQ_21

U5

VSSQ_22

V13

VSSQ_23

V2

VSSQ_24

A3

VPP_1

W3

VPP_2

+1.35VSDGPU_S

+1.8VSDGPU_AON_S

FBE_D24 <56>
FBE_D25 <56>
FBE_D26 <56>
FBE_D27 <56>
FBE_D28 <56>
FBE_D29 <56>
FBE_D30 <56>
FBE_D31 <56>
FBE_D16 <56>
FBE_D17 <56>
FBE_D18 <56>
FBE_D19 <56>
FBE_D20 <56>
FBE_D21 <56>
FBE_D22 <56>
FBE_D23 <56>
FBE_D8 <56>
FBE_D9 <56>
FBE_D10 <56>
FBE_D11 <56>
FBE_D12 <56>
FBE_D13 <56>
FBE_D14 <56>
FBE_D15 <56>
FBE_D0 <56>
FBE_D1 <56>
FBE_D2 <56>
FBE_D3 <56>
FBE_D4 <56>
FBE_D5 <56>
FBE_D6 <56>
FBE_D7 <56>

FBE_CLK1<56>
FBE_CLK1#<56 >

FBE_EDC4<56 >
FBE_EDC5<56 >
FBE_EDC6<56 >
FBE_EDC7<56 >

FBE_DBI4<56>
FBE_DBI5<56>
FBE_DBI6<56>
FBE_DBI7<56>

FBE_CMD29<56>

FBE_CMD28<56>
FBE_CMD26<56>
FBE_CMD25<56>
FBE_CMD27<56>

FBE_CMD24<56>
FBE_CMD19<56>
FBE_CMD20<56>
FBE_CMD23<56>
FBE_CMD21<56>
FBE_CMD30<56>

12

RG635 1K_0402 _1%

12

RG636 121_040 2_1%

FBE_CMD22<56>
FBE_CMD18<56>
FBE_CMD16<56>
FBE_CMD31<56>

FBE_WCK45#<56>
FBE_WCK45<56>

FBE_WCK67#<56>
FBE_WCK67<56>

FBE_CMD17<56>

+1.35VSDGPU_S

UG92

MF=0 MF=1 MF= 0MF=1

D3

EDC0 EDC3

D12

EDC1 EDC2

T12

EDC2 EDC1

T3

EDC3 EDC0

E3

DBI0# DBI3#

E12

DBI1# DBI2#

R12

DBI2# DBI1#

R3

DBI3# DBI0#

K11

CK

K10

CK#

H11

CKE# WE#

J11

BA0/A2 BA2/A4

L10

BA1/A5 BA3/A3

L11

BA2/A4 BA0/A2

J10

BA3/A3 BA1/A5

L4

A8/A7 A10/A0

J5

A9/A1 A11/A6

J4

A10/A0 A8/A7

L5

A11/A6 A9/A1

K5

A12/A13

K12

A14/A15

W12

MF

H13

ZQ

M2

TCK

M13

TDI

A12

TDO

H2

TMS

K4

ABI#

H4

RAS# CAS#

M4

CAS# RAS#

M11

WE# CKE#

D5

WCK01# WCK23#

D4

WCK01 WCK23

T5

WCK23# WCK01#

T4

+FBE_VREFC+FBE_VREF C

WCK23 WCK01

K13

VREFC

K2

RESET#

A10

VSS_1

A5

VSS_2

B1

VSS_3

B14

VSS_4

D1

VSS_5

D11

VSS_6

D14

VSS_7

F1

VSS_8

F14

VSS_9

H1

VSS_10

H14

VSS_11

J12

VSS_12

J3

VSS_13

K1

VSS_14

K14

VSS_15

K3

VSS_16

L12

VSS_17

L3

VSS_18

M1

VSS_19

M14

VSS_20

P1

VSS_21

P14

VSS_22

T1

VSS_23

T11

VSS_24

T14

VSS_25

V1

VSS_26

V14

VSS_27

W10

VSS_28

W5

VSS_29

A1

VDD_1

A11

VDD_2

A14

VDD_3

A4

VDD_4

D10

VDD_5

G1

VDD_6

G14

VDD_7

H10

VDD_8

H5

VDD_9

J1

VDD_10

J14

VDD_11

L1

VDD_12

L14

VDD_13

M10

VDD_14

M5

VDD_15

N1

VDD_16

N14

VDD_17

T10

VDD_18

W1

VDD_19

W11

VDD_20

W14

VDD_21

W4

VDD_22

190-BAL L

SGRAM GDDR5X

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15

DQ9 DQ16

DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23

DQ0 DQ24

DQ1 DQ25

DQ2 DQ26

DQ3 DQ27

DQ4 DQ28

DQ5 DQ29

DQ6 DQ30

DQ7 DQ31

MICRON_GDDR5X

2

B4
B3
C4
C3
F4
F3
G4
G3
B11
B12
C11
C12
F11
F12
G11
G12
V11
V12
U11
U12
P11
P12
N11
N12
V4
V3
U4
U3
P4
P3
N4
N3

A13

VDDQ_1

A2

VDDQ_2

B10

VDDQ_3

B5

VDDQ_4

C1

VDDQ_5

C13

VDDQ_6

C14

VDDQ_7

C2

VDDQ_8

E1

VDDQ_9

E11

VDDQ_10

E13

VDDQ_11

E14

VDDQ_12

E2

VDDQ_13

E4

VDDQ_14

F10

VDDQ_15

F5

VDDQ_16

G13

VDDQ_17

G2

VDDQ_18

H12

VDDQ_19

H3

VDDQ_20

J13

VDDQ_21

J2

VDDQ_22

L13

VDDQ_23

L2

VDDQ_24

M12

VDDQ_25

M3

VDDQ_26

N13

VDDQ_27

N2

VDDQ_28

P10

VDDQ_29

P5

VDDQ_30

R1

VDDQ_31

R11

VDDQ_32

R13

VDDQ_33

R14

VDDQ_34

R2

VDDQ_35

R4

VDDQ_36

U1

VDDQ_37

U13

VDDQ_38

U14

VDDQ_39

U2

VDDQ_40

V10

VDDQ_41

V5

VDDQ_42

W13

VDDQ_43

W2

VDDQ_44

B13

VSSQ_1

B2

VSSQ_2

C10

VSSQ_3

C5

VSSQ_4

D13

VSSQ_5

D2

VSSQ_6

E10

VSSQ_7

E5

VSSQ_8

F13

VSSQ_9

F2

VSSQ_10

G10

VSSQ_11

G5

VSSQ_12

N10

VSSQ_13

N5

VSSQ_14

P13

VSSQ_15

P2

VSSQ_16

R10

VSSQ_17

R5

VSSQ_18

T13

VSSQ_19

T2

VSSQ_20

U10

VSSQ_21

U5

VSSQ_22

V13

VSSQ_23

V2

VSSQ_24

A3

VPP_1

W3

VPP_2

+1.35VSDGPU_S

+1.8VSDGPU_AON_S

FBE_D32 <56>
FBE_D33 <56>
FBE_D34 <56>
FBE_D35 <56>
FBE_D36 <56>
FBE_D37 <56>
FBE_D38 <56>
FBE_D39 <56>
FBE_D40 <56>
FBE_D41 <56>
FBE_D42 <56>
FBE_D43 <56>
FBE_D44 <56>
FBE_D45 <56>
FBE_D46 <56>
FBE_D47 <56>
FBE_D48 <56>
FBE_D49 <56>
FBE_D50 <56>
FBE_D51 <56>
FBE_D52 <56>
FBE_D53 <56>
FBE_D54 <56>
FBE_D55 <56>
FBE_D56 <56>
FBE_D57 <56>
FBE_D58 <56>
FBE_D59 <56>
FBE_D60 <56>
FBE_D61 <56>
FBE_D62 <56>
FBE_D63 <56>

1

+1.35VSDGPU_S +1.35VSDGPU_S

A A

Under VRAM Near VRAMUnder VRAM

1

1

1

CG6821U_0402_6.3V4Z

CG6931U_0402_6.3V4Z

2

2

+1.8VSDGPU_AON_S

1

1

CG6761U_0402_6.3V4Z

CG6831U_0402_6.3V4Z

2

2

1

1

1

CG6971U_0402_6.3V4Z

CG6781U_0402_6.3V4Z

CG6771U_0402_6.3V4Z

2

2

2

Under VRAM

1

1

CG109

CG110

2

2

.1U_0402_16V7K

.1U_0402_16V7K

5

1

CG6751U_0402_6.3V4Z

2

.1U_0402_16V7K

1

1

1

CG6691U_0402_6.3V4Z

CG8211U_0402_6.3V4Z

CG8221U_0402_6.3V4Z

CG6921U_0402_6.3V4Z

2

2

2

2

1

1

CG318

CG880

2

2

.1U_0402_16V7K

1

1

1

CG6911U_0402_6.3V4Z

CG6881U_0402_6.3V4Z

2

2

1

1

1

CG6851U_0402_6.3V4Z

CG6871U_0402_6.3V4Z

CG6891U_0402_6.3V4Z

CG6861U_0402_6.3V4Z

2

2

2

2

+1.35VSDGPU_S

Near VRAM

1

1

CG6901U_0402_6.3V4Z

2

1

1

CG6841U_0402_6.3V4Z

2

1

CG67910U_0402_6.3V4Z

CG67410U_0402_6.3V4Z

2

2

1

1

1

1

1

CG67010U_0402_6.3V4Z

CG67210U_0402_6.3V4Z

CG69610U_0402_6.3V4Z

CG69410U_0402_6.3V4Z

CG82610U_0402_6.3V4Z

CG82410U_0402_6.3V4Z

2

2

2

2

2

2

4

+1.35VSDGPU_S

1

1

1

1

1

CG82310U_0402_6.3V4Z

2

2

2

2

2

2

1

CG68122U_0603_6.3V6M

CG69522U_0603_6.3V6M

CG67322U_0603_6.3V6M

CG68022U_0603_6.3V6M

1

1

CG82510U_0402_6.3V4Z

1

1

CG82822U_0603_6.3V6M

CG67122U_0603_6.3V6M

CG82922U_0603_6.3V6M

CG82722U_0603_6.3V6M

2

2

2

2

3

22uF 10uF 4.7uF 1uF 0.1uF

4 5

VDD

4 5

VDDQ

12

8

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

N17E-GDDR5_A-S

N17E-GDDR5_A-S

N17E-GDDR5_A-S

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

61 103Monday, January 09, 2017

61 103Monday, January 09, 2017

61 103Monday, January 09, 2017

1.0

1.0

1.0

5

FBF_EDC3<56>
FBF_EDC2<56>
FBF_EDC1<56>
FBF_EDC0<56>

FBF_DBI3<56>
FBF_DBI2<56>
FBF_DBI1<56>

+1.35VSDGPU_S

RG656 1K_04 02_1%
RG647 121_0 402_1%

FBF_DBI0<56>

FBF_CMD15<56>

FBF_CMD9<56>
FBF_CMD11<56>
FBF_CMD12<56>
FBF_CMD10<56>

FBF_CMD4<56>
FBF_CMD7<56>
FBF_CMD8<56>
FBF_CMD3<56>
FBF_CMD5<56>
FBF_CMD14<56>

FBF_CMD6<56>
FBF_CMD0<56>
FBF_CMD2<56>
FBF_CMD13<56>

FBF_WCK23#<56 >
FBF_WCK23<56>

FBF_WCK01#<56 >
FBF_WCK01<56>

FBF_CMD1<56>

FBF_CLK0<56>

+1.35VSDGPU_S

12

RG653
549_0402_1%

12

RG652

1.33K_0402_1%

FBF_CLK0#<56>

+FBF_VREFC

1

CG508

2

820P_0402_25V7

W=16mils

1

CG494

2

820P_0402_25V7

D D

C C

1 2

RG648
931_0402_1%

1

D

MEM_VREF_S<53,61,63,64>

B B

2

G

QG514

S

3

MESS138W-G_SOT 323-3

12
12

+FBF_VREFC

+1.35VSDGPU_S

4

D3

D12

T12

T3

E3
E12
R12

R3

K11
K10
H11

J11
L10
L11
J10

L4

J5

J4

L5

K5
K12

W12

H13

M2
M13
A12

H2

K4
H4

M4
M11

D5
D4

T5
T4

K13

K2

A10

A5
B1

B14

D1
D11
D14

F1

F14

H1
H14

J12

J3

K1
K14

K3

L12

L3

M1

M14

P1
P14

T1

T11
T14

V1
V14

W10

W5

A1
A11
A14

A4
D10

G1
G14
H10

H5
J1

J14

L1

L14
M10

M5

N1

N14

T10

W1

W11
W14

W4

MF=1

UG93

MF=0 MF=1 MF= 0MF=1

EDC0 EDC3
EDC1 EDC2
EDC2 EDC1
EDC3 EDC0

DBI0# DBI3#
DBI1# DBI2#
DBI2# DBI1#
DBI3# DBI0#

CK
CK#
CKE# WE#

BA0/A2 BA2/A4
BA1/A5 BA3/A3
BA2/A4 BA0/A2
BA3/A3 BA1/A5

A8/A7 A10/A0
A9/A1 A11/A6
A10/A0 A8/A7
A11/A6 A9/A1
A12/A13
A14/A15

MF
ZQ

TCK
TDI
TDO
TMS

ABI#
RAS# CAS#
CAS# RAS#
WE# CKE#

WCK01# WCK23#
WCK01 WCK23

WCK23# WCK01#
WCK23 WCK01

VREFC

RESET#

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20

190-BAL L

VDD_21
VDD_22

SGRAM GDDR5X

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15

DQ9 DQ16

DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23

DQ0 DQ24

DQ1 DQ25

DQ2 DQ26

DQ3 DQ27

DQ4 DQ28

DQ5 DQ29

DQ6 DQ30

DQ7 DQ31

MICRON_GDDR5X

3

UG94

B4
B3
C4
C3
F4
F3
G4
G3
B11
B12
C11
C12
F11
F12
G11
G12
V11
V12
U11
U12
P11
P12
N11
N12
V4
V3
U4
U3
P4
P3
N4
N3

A13

VDDQ_1

A2

VDDQ_2

B10

VDDQ_3

B5

VDDQ_4

C1

VDDQ_5

C13

VDDQ_6

C14

VDDQ_7

C2

VDDQ_8

E1

VDDQ_9

E11

VDDQ_10

E13

VDDQ_11

E14

VDDQ_12

E2

VDDQ_13

E4

VDDQ_14

F10

VDDQ_15

F5

VDDQ_16

G13

VDDQ_17

G2

VDDQ_18

H12

VDDQ_19

H3

VDDQ_20

J13

VDDQ_21

J2

VDDQ_22

L13

VDDQ_23

L2

VDDQ_24

M12

VDDQ_25

M3

VDDQ_26

N13

VDDQ_27

N2

VDDQ_28

P10

VDDQ_29

P5

VDDQ_30

R1

VDDQ_31

R11

VDDQ_32

R13

VDDQ_33

R14

VDDQ_34

R2

VDDQ_35

R4

VDDQ_36

U1

VDDQ_37

U13

VDDQ_38

U14

VDDQ_39

U2

VDDQ_40

V10

VDDQ_41

V5

VDDQ_42

W13

VDDQ_43

W2

VDDQ_44

B13

VSSQ_1

B2

VSSQ_2

C10

VSSQ_3

C5

VSSQ_4

D13

VSSQ_5

D2

VSSQ_6

E10

VSSQ_7

E5

VSSQ_8

F13

VSSQ_9

F2

VSSQ_10

G10

VSSQ_11

G5

VSSQ_12

N10

VSSQ_13

N5

VSSQ_14

P13

VSSQ_15

P2

VSSQ_16

R10

VSSQ_17

R5

VSSQ_18

T13

VSSQ_19

T2

VSSQ_20

U10

VSSQ_21

U5

VSSQ_22

V13

VSSQ_23

V2

VSSQ_24

A3

VPP_1

W3

VPP_2

+1.35VSDGPU_S

+1.8VSDGPU_AON_S

FBF_D24 <56>
FBF_D25 <56>
FBF_D26 <56>
FBF_D27 <56>
FBF_D28 <56>
FBF_D29 <56>
FBF_D30 <56>
FBF_D31 <56>
FBF_D16 <56>
FBF_D17 <56>
FBF_D18 <56>
FBF_D19 <56>
FBF_D20 <56>
FBF_D21 <56>
FBF_D22 <56>
FBF_D23 <56>
FBF_D8 <56>
FBF_D9 <56>
FBF_D10 <56>
FBF_D11 <56>
FBF_D12 <56>
FBF_D13 <56>
FBF_D14 <56>
FBF_D15 <56>
FBF_D0 <56>
FBF_D1 <56>
FBF_D2 <56>
FBF_D3 <56>
FBF_D4 <56>
FBF_D5 <56>
FBF_D6 <56>
FBF_D7 <56>

FBF_EDC4<56>
FBF_EDC5<56>
FBF_EDC6<56>
FBF_EDC7<56>

FBF_DBI4<56>
FBF_DBI5<56>
FBF_DBI6<56>

FBF_CLK1<56>
FBF_CLK1#<56 >

FBF_DBI7<56>

FBF_CMD29<56>

FBF_CMD28<56>
FBF_CMD26<56>
FBF_CMD25<56>
FBF_CMD27<56>

FBF_CMD24<56>
FBF_CMD19<56>
FBF_CMD20<56>
FBF_CMD23<56>
FBF_CMD21<56>
FBF_CMD30<56>

12

RG654 1K_0402 _1%

12

RG650 121_040 2_1%

FBF_CMD22<56>
FBF_CMD18<56>
FBF_CMD16<56>
FBF_CMD31<56>

FBF_WCK45#<56 >
FBF_WCK45<56>

FBF_WCK67#<56 >
FBF_WCK67<56>

+FBF_VREFC

FBF_CMD17<56>

+1.35VSDGPU_S

MF=0 MF=1 MF= 0MF=1

D3

EDC0 EDC3

D12

EDC1 EDC2

T12

EDC2 EDC1

T3

EDC3 EDC0

E3

DBI0# DBI3#

E12

DBI1# DBI2#

R12

DBI2# DBI1#

R3

DBI3# DBI0#

K11

CK

K10

CK#

H11

CKE# WE#

J11

BA0/A2 BA2/A4

L10

BA1/A5 BA3/A3

L11

BA2/A4 BA0/A2

J10

BA3/A3 BA1/A5

L4

A8/A7 A10/A0

J5

A9/A1 A11/A6

J4

A10/A0 A8/A7

L5

A11/A6 A9/A1

K5

A12/A13

K12

A14/A15

W12

MF

H13

ZQ

M2

TCK

M13

TDI

A12

TDO

H2

TMS

K4

ABI#

H4

RAS# CAS#

M4

CAS# RAS#

M11

WE# CKE#

D5

WCK01# WCK23#

D4

WCK01 WCK23

T5

WCK23# WCK01#

T4

WCK23 WCK01

K13

VREFC

K2

RESET#

A10

VSS_1

A5

VSS_2

B1

VSS_3

B14

VSS_4

D1

VSS_5

D11

VSS_6

D14

VSS_7

F1

VSS_8

F14

VSS_9

H1

VSS_10

H14

VSS_11

J12

VSS_12

J3

VSS_13

K1

VSS_14

K14

VSS_15

K3

VSS_16

L12

VSS_17

L3

VSS_18

M1

VSS_19

M14

VSS_20

P1

VSS_21

P14

VSS_22

T1

VSS_23

T11

VSS_24

T14

VSS_25

V1

VSS_26

V14

VSS_27

W10

VSS_28

W5

VSS_29

A1

VDD_1

A11

VDD_2

A14

VDD_3

A4

VDD_4

D10

VDD_5

G1

VDD_6

G14

VDD_7

H10

VDD_8

H5

VDD_9

J1

VDD_10

J14

VDD_11

L1

VDD_12

L14

VDD_13

M10

VDD_14

M5

VDD_15

N1

VDD_16

N14

VDD_17

T10

VDD_18

W1

VDD_19

W11

VDD_20

W14

VDD_21

W4

SGRAM GDDR5X

VDD_22

190-BAL L

MF=0

2

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ9 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

MICRON_GDDR5X

1

B4
B3
C4
C3
F4
F3
G4
G3
B11
B12
C11
C12
F11
F12
G11
G12
V11
V12
U11
U12
P11
P12
N11
N12
V4
V3
U4
U3
P4
P3
N4
N3

A13

VDDQ_1

A2

VDDQ_2

B10

VDDQ_3

B5

VDDQ_4

C1

VDDQ_5

C13

VDDQ_6

C14

VDDQ_7

C2

VDDQ_8

E1

VDDQ_9

E11

VDDQ_10

E13

VDDQ_11

E14

VDDQ_12

E2

VDDQ_13

E4

VDDQ_14

F10

VDDQ_15

F5

VDDQ_16

G13

VDDQ_17

G2

VDDQ_18

H12

VDDQ_19

H3

VDDQ_20

J13

VDDQ_21

J2

VDDQ_22

L13

VDDQ_23

L2

VDDQ_24

M12

VDDQ_25

M3

VDDQ_26

N13

VDDQ_27

N2

VDDQ_28

P10

VDDQ_29

P5

VDDQ_30

R1

VDDQ_31

R11

VDDQ_32

R13

VDDQ_33

R14

VDDQ_34

R2

VDDQ_35

R4

VDDQ_36

U1

VDDQ_37

U13

VDDQ_38

U14

VDDQ_39

U2

VDDQ_40

V10

VDDQ_41

V5

VDDQ_42

W13

VDDQ_43

W2

VDDQ_44

B13

VSSQ_1

B2

VSSQ_2

C10

VSSQ_3

C5

VSSQ_4

D13

VSSQ_5

D2

VSSQ_6

E10

VSSQ_7

E5

VSSQ_8

F13

VSSQ_9

F2

VSSQ_10

G10

VSSQ_11

G5

VSSQ_12

N10

VSSQ_13

N5

VSSQ_14

P13

VSSQ_15

P2

VSSQ_16

R10

VSSQ_17

R5

VSSQ_18

T13

VSSQ_19

T2

VSSQ_20

U10

VSSQ_21

U5

VSSQ_22

V13

VSSQ_23

V2

VSSQ_24

A3

VPP_1

W3

VPP_2

+1.35VSDGPU_S

+1.8VSDGPU_AON_S

FBF_D32 <56>
FBF_D33 <56>
FBF_D34 <56>
FBF_D35 <56>
FBF_D36 <56>
FBF_D37 <56>
FBF_D38 <56>
FBF_D39 <56>
FBF_D40 <56>
FBF_D41 <56>
FBF_D42 <56>
FBF_D43 <56>
FBF_D44 <56>
FBF_D45 <56>
FBF_D46 <56>
FBF_D47 <56>
FBF_D48 <56>
FBF_D49 <56>
FBF_D50 <56>
FBF_D51 <56>
FBF_D52 <56>
FBF_D53 <56>
FBF_D54 <56>
FBF_D55 <56>
FBF_D56 <56>
FBF_D57 <56>
FBF_D58 <56>
FBF_D59 <56>
FBF_D60 <56>
FBF_D61 <56>
FBF_D62 <56>
FBF_D63 <56>

Under VRAM Near VRAMUnder VRAM

+1.35VSDGPU_S +1.35VSDGPU_S

1

1

1

1

CG7051U_0402_6.3V4Z

CG7061U_0402_6.3V4Z

CG7121U_0402_6.3V4Z

2

2

2

Under VRAM

1

CG111

2

.1U_0402_16V7K

1

CG7071U_0402_6.3V4Z

2

1

CG900

2

.1U_0402_16V7K

1

CG7221U_0402_6.3V4Z

CG7111U_0402_6.3V4Z

2

2

A A

+1.8VSDGPU_AON_S

5

1

1

1

CG7261U_0402_6.3V4Z

CG7041U_0402_6.3V4Z

2

2

1

CG319

2

.1U_0402_16V7K

1

1

1

CG6981U_0402_6.3V4Z

CG8341U_0402_6.3V4Z

CG7211U_0402_6.3V4Z

CG8351U_0402_6.3V4Z

2

2

2

2

1

CG881

2

.1U_0402_16V7K

1

1

1

CG7171U_0402_6.3V4Z

CG7201U_0402_6.3V4Z

2

2

1

1

1

CG7151U_0402_6.3V4Z

CG7161U_0402_6.3V4Z

CG7141U_0402_6.3V4Z

CG7181U_0402_6.3V4Z

2

2

2

2

+1.35VSDGPU_S +1.3 5VSDGPU_S

Near VRAM

1

1

1

CG7191U_0402_6.3V4Z

CG7131U_0402_6.3V4Z

2

2

4

1

1

1

CG72510U_0402_6.3V4Z

CG70810U_0402_6.3V4Z

CG70310U_0402_6.3V4Z

2

2

2

1

1

1

CG72310U_0402_6.3V4Z

CG83010U_0402_6.3V4Z

CG70110U_0402_6.3V4Z

CG69910U_0402_6.3V4Z

2

2

2

2

4 5

VDD

4 5

1

1

1

1

1

CG83310U_0402_6.3V4Z

CG83210U_0402_6.3V4Z

CG83110U_0402_6.3V4Z

2

2

2

1

1

CG70922U_0603_6.3V6M

CG71022U_0603_6.3V6M

CG72422U_0603_6.3V6M

2

2

2

1

1

CG70222U_0603_6.3V6M

2

1

1

CG70022U_0603_6.3V6M

CG83722U_0603_6.3V6M

CG83622U_0603_6.3V6M

CG83822U_0603_6.3V6M

2

2

2

2

3

VDDQ

12

8

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

N17E-GDDR5_B-S

N17E-GDDR5_B-S

N17E-GDDR5_B-S

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

62 103Monday, January 09, 2017

62 103Monday, January 09, 2017

62 103Monday, January 09, 2017

22uF 10uF 4.7uF 1uF 0.1uF

1.0

1.0

1.0

5

FBG_CLK0<56>

W=16mils

1

CG517

2

820P_0402_25V7

FBG_CLK0#<56>

+1.35VSDGPU_S

1

1

1

1

CG7441U_0402_6.3V4Z

CG7471U_0402_6.3V4Z

CG7461U_0402_6.3V4Z

CG7491U_0402_6.3V4Z

2

2

2

2

D D

C C

1

D

MEM_VREF_S<53,61,62,64>

B B

2

G

QG515

S

3

MESS138W-G_SOT 323-3

+1.35VSDGPU_S +1.35VSDGPU_S

Under VRAM Near VRAMUnder VRAM

1

1

1

1

CG7511U_0402_6.3V4Z

2

CG7351U_0402_6.3V4Z

CG7341U_0402_6.3V4Z

CG7401U_0402_6.3V4Z

CG7411U_0402_6.3V4Z

2

2

2

+1.35VSDGPU_S

12

RG667
549_0402_1%

1 2

RG666
931_0402_1%

1

1

1

CG7361U_0402_6.3V4Z

CG7551U_0402_6.3V4Z

2

2

2

+FBG_VREFC

12

1

CG532

RG661

2

1.33K_0402_1%

820P_0402_25V7

1

1

1

1

1

CG7331U_0402_6.3V4Z

CG7271U_0402_6.3V4Z

CG7501U_0402_6.3V4Z

CG8471U_0402_6.3V4Z

CG8461U_0402_6.3V4Z

2

2

2

2

2

RG658 1K_0402 _1%
RG659 121_040 2_1%

1

1

1

CG7451U_0402_6.3V4Z

CG7481U_0402_6.3V4Z

CG7421U_0402_6.3V4Z

CG7431U_0402_6.3V4Z

2

2

2

4

MF=1

UG95

MF=0 MF=1 MF= 0MF=1

12
12

+FBG_VREFC

+1.35VSDGPU_S

1

CG84010U_0402_6.3V4Z

2

D3

D12

T12

T3

E3

E12

R12

R3

K11
K10

H11

J11
L10
L11
J10

L4
J5
J4
L5
K5

K12

W12
H13

M2

M13

A12

H2

K4
H4
M4

M11

D5
D4

T5
T4

K13

K2

A10

A5
B1

B14

D1
D11
D14

F1

F14

H1
H14

J12

J3

K1

K14

K3

L12

L3

M1
M14

P1

P14

T1

T11
T14

V1

V14

W10

W5

A1

A11
A14

A4
D10

G1
G14
H10

H5

J1

J14

L1

L14

M10

M5

N1
N14

T10

W1
W11
W14

W4

1

CG83910U_0402_6.3V4Z

CG73710U_0402_6.3V4Z

2

EDC0 EDC3
EDC1 EDC2
EDC2 EDC1
EDC3 EDC0

DBI0# DBI3#
DBI1# DBI2#
DBI2# DBI1#
DBI3# DBI0#

CK
CK#
CKE# WE#

BA0/A2 BA2/A4
BA1/A5 BA3/A3
BA2/A4 BA0/A2
BA3/A3 BA1/A5

A8/A7 A10/A0
A9/A1 A11/A6
A10/A0 A8/A7
A11/A6 A9/A1
A12/A13
A14/A15

MF
ZQ

TCK
TDI
TDO
TMS

ABI#
RAS# CAS#
CAS# RAS#
WE# CKE#

WCK01# WCK23#
WCK01 WCK23

WCK23# WCK01#
WCK23 WCK01

VREFC

RESET#

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22

Near VRAM

1

1

1

CG73210U_0402_6.3V4Z

CG84410U_0402_6.3V4Z

2

2

2

190-BAL L

SGRAM GDDR5X

1

CG75410U_0402_6.3V4Z

2

1

CG72810U_0402_6.3V4Z

2

MICRON_GDDR5X

1

CG75210U_0402_6.3V4Z

2

FBG_EDC3<56>
FBG_EDC2<56>
FBG_EDC1<56>
FBG_EDC0<56>

FBG_DBI3<5 6>
FBG_DBI2<5 6>
FBG_DBI1<5 6>
FBG_DBI0<5 6>

FBG_CMD15<56>

FBG_CMD9<56>
FBG_CMD11<56>
FBG_CMD12<56>
FBG_CMD10<56>

FBG_CMD4<56>
FBG_CMD7<56>
FBG_CMD8<56>
FBG_CMD3<56>
FBG_CMD5<56>
FBG_CMD14<56>

FBG_CMD6<56>
FBG_CMD0<56>
FBG_CMD2<56>
FBG_CMD13<56>

FBG_WCK23#<56>
FBG_WCK23<56>

FBG_WCK01#<56>
FBG_WCK01<56>

FBG_CMD1<56>

+1.35VSDGPU_S

1

2

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ9 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

1

1

CG73010U_0402_6.3V4Z

CG84510U_0402_6.3V4Z

2

2

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8

VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
VDDQ_28
VDDQ_29
VDDQ_30
VDDQ_31
VDDQ_32
VDDQ_33
VDDQ_34
VDDQ_35
VDDQ_36
VDDQ_37
VDDQ_38
VDDQ_39
VDDQ_40
VDDQ_41
VDDQ_42
VDDQ_43
VDDQ_44

VSSQ_1

VSSQ_2

VSSQ_3

VSSQ_4

VSSQ_5

VSSQ_6

VSSQ_7

VSSQ_8

VSSQ_9
VSSQ_10
VSSQ_11
VSSQ_12
VSSQ_13
VSSQ_14
VSSQ_15
VSSQ_16
VSSQ_17
VSSQ_18
VSSQ_19
VSSQ_20
VSSQ_21
VSSQ_22
VSSQ_23
VSSQ_24

VPP_1
VPP_2

B4
B3
C4
C3
F4
F3
G4
G3
B11
B12
C11
C12
F11
F12
G11
G12
V11
V12
U11
U12
P11
P12
N11
N12
V4
V3
U4
U3
P4
P3
N4
N3

A13
A2
B10
B5
C1
C13
C14
C2
E1
E11
E13
E14
E2
E4
F10
F5
G13
G2
H12
H3
J13
J2
L13
L2
M12
M3
N13
N2
P10
P5
R1
R11
R13
R14
R2
R4
U1
U13
U14
U2
V10
V5
W13
W2

B13
B2
C10
C5
D13
D2
E10
E5
F13
F2
G10
G5
N10
N5
P13
P2
R10
R5
T13
T2
U10
U5
V13
V2

A3
W3

+1.35VSDGPU_S

1

CG84122U_0603_6.3V6M

2

1

CG84222U_0603_6.3V6M

2

+1.35VSDGPU_S

+1.8VSDGPU_AON_S

1

1

CG73822U_0603_6.3V6M

CG73922U_0603_6.3V6M

2

2

FBG_D24 <56>
FBG_D25 <56>
FBG_D26 <56>
FBG_D27 <56>
FBG_D28 <56>
FBG_D29 <56>
FBG_D30 <56>
FBG_D31 <56>
FBG_D16 <56>
FBG_D17 <56>
FBG_D18 <56>
FBG_D19 <56>
FBG_D20 <56>
FBG_D21 <56>
FBG_D22 <56>
FBG_D23 <56>
FBG_D8 <56>
FBG_D9 <56>
FBG_D10 <56>
FBG_D11 <56>
FBG_D12 <56>
FBG_D13 <56>
FBG_D14 <56>
FBG_D15 <56>
FBG_D0 <56>
FBG_D1 <56>
FBG_D2 <56>
FBG_D3 <56>
FBG_D4 <56>
FBG_D5 <56>
FBG_D6 <56>
FBG_D7 <56>

1

CG75322U_0603_6.3V6M

2

3

12
12

+FBG_VREFC

+1.35VSDGPU_S

D3
D12
T12

T3

E3
E12
R12

R3

K11
K10
H11

J11
L10
L11
J10

L4

J5

J4

L5

K5
K12

W12

H13

M2
M13
A12

H2

K4
H4

M4
M11

D5
D4

T5
T4

K13

K2

A10

A5
B1

B14

D1
D11
D14

F1
F14

H1
H14

J12

J3

K1
K14

K3

L12

L3

M1

M14

P1
P14

T1
T11
T14

V1
V14

W10

W5

A1
A11
A14

A4
D10

G1
G14
H10

H5
J1

J14

L1

L14
M10

M5

N1
N14
T10

W1
W11
W14

W4

FBG_EDC4<56>
FBG_EDC5<56>
FBG_EDC6<56>
FBG_EDC7<56>

FBG_DBI4<56>
FBG_DBI5<56>
FBG_DBI6<56>

FBG_CLK1<56>
FBG_CLK1#<56>

1

1

1

CG72922U_0603_6.3V6M

CG73122U_0603_6.3V6M

CG84322U_0603_6.3V6M

2

2

2

FBG_DBI7<56>

FBG_CMD29<56>

FBG_CMD28<56>
FBG_CMD26<56>
FBG_CMD25<56>
FBG_CMD27<56>

FBG_CMD24<56>
FBG_CMD19<56>
FBG_CMD20<56>
FBG_CMD23<56>
FBG_CMD21<56>
FBG_CMD30<56>

RG662 1K_0402 _1%
RG664 121_040 2_1%

FBG_CMD22<56>
FBG_CMD18<56>
FBG_CMD16<56>
FBG_CMD31<56>

FBG_WCK45#<56>
FBG_WCK45<56>

FBG_WCK67#<56>
FBG_WCK67<56>

FBG_CMD17<56>

2

MF=0

UG96

MF=0 MF=1 MF= 0MF=1

EDC0 EDC3
EDC1 EDC2
EDC2 EDC1
EDC3 EDC0

DBI0# DBI3#
DBI1# DBI2#
DBI2# DBI1#
DBI3# DBI0#

CK
CK#
CKE# WE#

BA0/A2 BA2/A4
BA1/A5 BA3/A3
BA2/A4 BA0/A2
BA3/A3 BA1/A5

A8/A7 A10/A0
A9/A1 A11/A6
A10/A0 A8/A7
A11/A6 A9/A1
A12/A13
A14/A15

MF
ZQ

TCK
TDI
TDO
TMS

ABI#
RAS# CAS#
CAS# RAS#
WE# CKE#

WCK01# WCK23#
WCK01 WCK23

WCK23# WCK01#
WCK23 WCK01

VREFC

RESET#

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20

190-BAL L

VDD_21

SGRAM GDDR5X

VDD_22

VDD

VDDQ

B4

DQ24 DQ0

B3

DQ25 DQ1

C4

DQ26 DQ2

C3

DQ27 DQ3

F4

DQ28 DQ4

F3

DQ29 DQ5

G4

DQ30 DQ6

G3

DQ31 DQ7

B11

DQ16 DQ8

B12

DQ17 DQ9

C11

DQ18 DQ10

C12

DQ19 DQ11

F11

DQ20 DQ12

F12

DQ21 DQ13

G11

DQ22 DQ14

G12

DQ23 DQ15

V11

DQ9 DQ16

V12

DQ9 DQ17

U11

DQ10 DQ18

U12

DQ11 DQ19

P11

DQ12 DQ20

P12

DQ13 DQ21

N11

DQ14 DQ22

N12

DQ15 DQ23

V4

DQ0 DQ24

V3

DQ1 DQ25

U4

DQ2 DQ26

U3

DQ3 DQ27

P4

DQ4 DQ28

P3

DQ5 DQ29

N4

DQ6 DQ30

N3

DQ7 DQ31

A13

VDDQ_1

A2

VDDQ_2

B10

VDDQ_3

B5

VDDQ_4

C1

VDDQ_5

C13

VDDQ_6

C14

VDDQ_7

C2

VDDQ_8

E1

VDDQ_9

E11

VDDQ_10

E13

VDDQ_11

E14

VDDQ_12

E2

VDDQ_13

E4

VDDQ_14

F10

VDDQ_15

F5

VDDQ_16

G13

VDDQ_17

G2

VDDQ_18

H12

VDDQ_19

H3

VDDQ_20

J13

VDDQ_21

J2

VDDQ_22

L13

VDDQ_23

L2

VDDQ_24

M12

VDDQ_25

M3

VDDQ_26

N13

VDDQ_27

N2

VDDQ_28

P10

VDDQ_29

P5

VDDQ_30

R1

VDDQ_31

R11

VDDQ_32

R13

VDDQ_33

R14

VDDQ_34

R2

VDDQ_35

R4

VDDQ_36

U1

VDDQ_37

U13

VDDQ_38

U14

VDDQ_39

U2

VDDQ_40

V10

VDDQ_41

V5

VDDQ_42

W13

VDDQ_43

W2

VDDQ_44

B13

VSSQ_1

B2

VSSQ_2

C10

VSSQ_3

C5

VSSQ_4

D13

VSSQ_5

D2

VSSQ_6

E10

VSSQ_7

E5

VSSQ_8

F13

VSSQ_9

F2

VSSQ_10

G10

VSSQ_11

G5

VSSQ_12

N10

VSSQ_13

N5

VSSQ_14

P13

VSSQ_15

P2

VSSQ_16

R10

VSSQ_17

R5

VSSQ_18

T13

VSSQ_19

T2

VSSQ_20

U10

VSSQ_21

U5

VSSQ_22

V13

VSSQ_23

V2

VSSQ_24

A3

VPP_1

W3

VPP_2

MICRON_GDDR5X

22uF 10uF 4.7uF 1uF 0.1uF

4 5

4 5

+1.35VSDGPU_S

+1.8VSDGPU_AON_S

12

8

FBG_D32 <56>
FBG_D33 <56>
FBG_D34 <56>
FBG_D35 <56>
FBG_D36 <56>
FBG_D37 <56>
FBG_D38 <56>
FBG_D39 <56>
FBG_D40 <56>
FBG_D41 <56>
FBG_D42 <56>
FBG_D43 <56>
FBG_D44 <56>
FBG_D45 <56>
FBG_D46 <56>
FBG_D47 <56>
FBG_D48 <56>
FBG_D49 <56>
FBG_D50 <56>
FBG_D51 <56>
FBG_D52 <56>
FBG_D53 <56>
FBG_D54 <56>
FBG_D55 <56>
FBG_D56 <56>
FBG_D57 <56>
FBG_D58 <56>
FBG_D59 <56>
FBG_D60 <56>
FBG_D61 <56>
FBG_D62 <56>
FBG_D63 <56>

1

+1.8VSDGPU_AON_S

Under VRAM

1

1

1

1

CG116

CG115

CG324

CG882

2

2

2

.1U_0402_16V7K

A A

.1U_0402_16V7K

5

2

.1U_0402_16V7K

.1U_0402_16V7K

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

N17E-GDDR5_C-S

N17E-GDDR5_C-S

N17E-GDDR5_C-S

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

63 103Monday, January 09, 2017

63 103Monday, January 09, 2017

63 103Monday, January 09, 2017

1.0

1.0

1.0

5

FBH_CLK0<56>

+FBH_VREFC

1

2

1

CG8531U_0402_6.3V4Z

2

CG553

1

CG8521U_0402_6.3V4Z

2

820P_0402_25V7

W=16mils

1

CG552

2

820P_0402_25V7

FBH_CLK0#<56>

+1.35VSDGPU_S

RG673 1K_0402 _1%
RG677 121_040 2_1%

Under VRAM

1

1

1

CG7781U_0402_6.3V4Z

2

1

1

CG7731U_0402_6.3V4Z

CG7751U_0402_6.3V4Z

CG7721U_0402_6.3V4Z

CG7761U_0402_6.3V4Z

2

2

2

2

D D

C C

+1.35VSDGPU_S

12

RG670
549_0402_1%

1 2

12

RG669
931_0402_1%

1

D

MEM_VREF_S<53,61,62,63>

B B

2

G

QG516

S

3

MESS138W-G_SOT 323-3

Under VRAM

+1.35VSDGPU_S +1.35VSDGPU_S

1

1

1

1

CG7801U_0402_6.3V4Z

2

1

CG7691U_0402_6.3V4Z

2

1

CG7631U_0402_6.3V4Z

CG7701U_0402_6.3V4Z

CG7641U_0402_6.3V4Z

CG7651U_0402_6.3V4Z

2

2

2

2

RG671

1.33K_0402_1%

1

1

1

1

CG7791U_0402_6.3V4Z

CG7561U_0402_6.3V4Z

CG7621U_0402_6.3V4Z

CG7841U_0402_6.3V4Z

2

2

2

2

4

MF=1

UG97

MF=0 MF=1 MF= 0MF=1

12
12

+FBH_VREFC

+1.35VSDGPU_S

1

CG7711U_0402_6.3V4Z

2

D3

EDC0 EDC3

D12

EDC1 EDC2

T12

EDC2 EDC1

T3

EDC3 EDC0

E3

DBI0# DBI3#

E12

DBI1# DBI2#

R12

DBI2# DBI1#

R3

DBI3# DBI0#

K11

CK

K10

CK#

H11

CKE# WE#

J11

BA0/A2 BA2/A4

L10

BA1/A5 BA3/A3

L11

BA2/A4 BA0/A2

J10

BA3/A3 BA1/A5

L4

A8/A7 A10/A0

J5

A9/A1 A11/A6

J4

A10/A0 A8/A7

L5

A11/A6 A9/A1

K5

A12/A13

K12

A14/A15

W12

MF

H13

ZQ

M2

TCK

M13

TDI

A12

TDO

H2

TMS

K4

ABI#

H4

RAS# CAS#

M4

CAS# RAS#

M11

WE# CKE#

D5

WCK01# WCK23#

D4

WCK01 WCK23

T5

WCK23# WCK01#

T4

WCK23 WCK01

K13

VREFC

K2

RESET#

A10

VSS_1

A5

VSS_2

B1

VSS_3

B14

VSS_4

D1

VSS_5

D11

VSS_6

D14

VSS_7

F1

VSS_8

F14

VSS_9

H1

VSS_10

H14

VSS_11

J12

VSS_12

J3

VSS_13

K1

VSS_14

K14

VSS_15

K3

VSS_16

L12

VSS_17

L3

VSS_18

M1

VSS_19

M14

VSS_20

P1

VSS_21

P14

VSS_22

T1

VSS_23

T11

VSS_24

T14

VSS_25

V1

VSS_26

V14

VSS_27

W10

VSS_28

W5

VSS_29

A1

VDD_1

A11

VDD_2

A14

VDD_3

A4

VDD_4

D10

VDD_5

G1

VDD_6

G14

VDD_7

H10

VDD_8

H5

VDD_9

J1

VDD_10

J14

VDD_11

L1

VDD_12

L14

VDD_13

M10

VDD_14

M5

VDD_15

N1

VDD_16

N14

VDD_17

T10

VDD_18

W1

VDD_19

W11

VDD_20

W14

VDD_21

W4

VDD_22

+1.35VSDGPU_S

1

CG76610U_0402_6.3V4Z

2

1

CG76110U_0402_6.3V4Z

2

SGRAM GDDR5X

1

CG84810U_0402_6.3V4Z

2

190-BAL L

MICRON_GDDR5X

Near VRAM

1

1

1

CG75710U_0402_6.3V4Z

CG78110U_0402_6.3V4Z

CG78310U_0402_6.3V4Z

2

2

2

FBH_EDC3<56>
FBH_EDC2<56>
FBH_EDC1<56>
FBH_EDC0<56>

FBH_DBI3<56>
FBH_DBI2<56>
FBH_DBI1<56>
FBH_DBI0<56>

FBH_CMD15<56>

FBH_CMD9<56>
FBH_CMD11<56>
FBH_CMD12<56>
FBH_CMD10<56>

FBH_CMD4<56>
FBH_CMD7<56>
FBH_CMD8<56>
FBH_CMD3<56>
FBH_CMD5<56>
FBH_CMD14<56>

FBH_CMD6<56>
FBH_CMD0<56>
FBH_CMD2<56>
FBH_CMD13<56>

FBH_WCK23#<56>
FBH_WCK23<56>

FBH_WCK01#<56>
FBH_WCK01<56>

FBH_CMD1<56>

1

1

CG7771U_0402_6.3V4Z

CG7741U_0402_6.3V4Z

2

2

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15

DQ9 DQ16

DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23

DQ0 DQ24

DQ1 DQ25

DQ2 DQ26

DQ3 DQ27

DQ4 DQ28

DQ5 DQ29

DQ6 DQ30

DQ7 DQ31

VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
VDDQ_28
VDDQ_29
VDDQ_30
VDDQ_31
VDDQ_32
VDDQ_33
VDDQ_34
VDDQ_35
VDDQ_36
VDDQ_37
VDDQ_38
VDDQ_39
VDDQ_40
VDDQ_41
VDDQ_42
VDDQ_43
VDDQ_44

VSSQ_10
VSSQ_11
VSSQ_12
VSSQ_13
VSSQ_14
VSSQ_15
VSSQ_16
VSSQ_17
VSSQ_18
VSSQ_19
VSSQ_20
VSSQ_21
VSSQ_22
VSSQ_23
VSSQ_24

1

1

CG75910U_0402_6.3V4Z

CG84910U_0402_6.3V4Z

2

2

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

B4
B3
C4
C3
F4
F3
G4
G3
B11
B12
C11
C12
F11
F12
G11
G12
V11
V12
U11
U12
P11
P12
N11
N12
V4
V3
U4
U3
P4
P3
N4
N3

A13
A2
B10
B5
C1
C13
C14
C2
E1
E11
E13
E14
E2
E4
F10
F5
G13
G2
H12
H3
J13
J2
L13
L2
M12
M3
N13
N2
P10
P5
R1
R11
R13
R14
R2
R4
U1
U13
U14
U2
V10
V5
W13
W2

B13
B2
C10
C5
D13
D2
E10
E5
F13
F2
G10
G5
N10
N5
P13
P2
R10
R5
T13
T2
U10
U5
V13
V2

A3

VPP_1

W3

VPP_2

1

1

CG85010U_0402_6.3V4Z

CG85110U_0402_6.3V4Z

2

2

+1.35VSDGPU_S

+1.8VSDGPU_AON_S

+1.35VSDGPU_S

FBH_D24 <56>
FBH_D25 <56>
FBH_D26 <56>
FBH_D27 <56>
FBH_D28 <56>
FBH_D29 <56>
FBH_D30 <56>
FBH_D31 <56>
FBH_D16 <56>
FBH_D17 <56>
FBH_D18 <56>
FBH_D19 <56>
FBH_D20 <56>
FBH_D21 <56>
FBH_D22 <56>
FBH_D23 <56>
FBH_D8 <56>
FBH_D9 <56>
FBH_D10 <56>
FBH_D11 <56>
FBH_D12 <56>
FBH_D13 <56>
FBH_D14 <56>
FBH_D15 <56>
FBH_D0 <56>
FBH_D1 <56>
FBH_D2 <56>
FBH_D3 <56>
FBH_D4 <56>
FBH_D5 <56>
FBH_D6 <56>
FBH_D7 <56>

1

CG76822U_0603_6.3V6M

2

Near VRAM

1

1

1

CG78222U_0603_6.3V6M

CG76722U_0603_6.3V6M

CG76022U_0603_6.3V6M

2

2

2

3

UG98

MF=0 MF=1 MF= 0MF=1

12
12

+FBH_VREFC

D3

EDC0 EDC3

D12

EDC1 EDC2

T12

EDC2 EDC1

T3

EDC3 EDC0

E3

DBI0# DBI3#

E12

DBI1# DBI2#

R12

DBI2# DBI1#

R3

DBI3# DBI0#

K11

CK

K10

CK#

H11

CKE# WE#

J11

BA0/A2 BA2/A4

L10

BA1/A5 BA3/A3

L11

BA2/A4 BA0/A2

J10

BA3/A3 BA1/A5

L4

A8/A7 A10/A0

J5

A9/A1 A11/A6

J4

A10/A0 A8/A7

L5

A11/A6 A9/A1

K5

A12/A13

K12

A14/A15

W12

MF

H13

ZQ

M2

TCK

M13

TDI

A12

TDO

H2

TMS

K4

ABI#

H4

RAS# CAS#

M4

CAS# RAS#

M11

WE# CKE#

D5

WCK01# WCK23#

D4

WCK01 WCK23

T5

WCK23# WCK01#

T4

WCK23 WCK01

K13

VREFC

K2

RESET#

A10

VSS_1

A5

VSS_2

B1

VSS_3

B14

VSS_4

D1

VSS_5

D11

VSS_6

D14

VSS_7

F1

VSS_8

F14

VSS_9

H1

VSS_10

H14

VSS_11

J12

VSS_12

J3

VSS_13

K1

VSS_14

K14

VSS_15

K3

VSS_16

L12

VSS_17

L3

VSS_18

M1

VSS_19

M14

VSS_20

P1

VSS_21

P14

VSS_22

T1

VSS_23

T11

VSS_24

T14

VSS_25

V1

VSS_26

V14

VSS_27

W10

VSS_28

W5

VSS_29

A1

VDD_1

A11

VDD_2

A14

VDD_3

A4

VDD_4

D10

VDD_5

G1

VDD_6

G14

VDD_7

H10

VDD_8

H5

VDD_9

J1

VDD_10

J14

VDD_11

L1

VDD_12

L14

VDD_13

M10

VDD_14

M5

VDD_15

N1

VDD_16

N14

VDD_17

T10

VDD_18

W1

VDD_19

W11

VDD_20

W14

VDD_21

W4

VDD_22

FBH_EDC4<56 >
FBH_EDC5<56 >
FBH_EDC6<56 >
FBH_EDC7<56 >

FBH_DBI4<56>
FBH_DBI5<56>
FBH_DBI6<56>

FBH_CLK1<56>
FBH_CLK1#<56>

1

1

1

1

CG85422U_0603_6.3V6M

CG85622U_0603_6.3V6M

CG75822U_0603_6.3V6M

CG85522U_0603_6.3V6M

2

2

2

2

FBH_DBI7<56>

FBH_CMD29<56>

FBH_CMD28<56>
FBH_CMD26<56>
FBH_CMD25<56>
FBH_CMD27<56>

FBH_CMD24<56>
FBH_CMD19<56>
FBH_CMD20<56>
FBH_CMD23<56>
FBH_CMD21<56>
FBH_CMD30<56>

RG674 1K_0402 _1%
RG668 121_040 2_1%

FBH_CMD22<56>
FBH_CMD18<56>
FBH_CMD16<56>
FBH_CMD31<56>

FBH_WCK45#<56>
FBH_WCK45<56>

FBH_WCK67#<56>
FBH_WCK67<56>

FBH_CMD17<56>

+1.35VSDGPU_S

190-BAL L

SGRAM GDDR5X

2

MF=0

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15

DQ9 DQ16

DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23

DQ0 DQ24

DQ1 DQ25

DQ2 DQ26

DQ3 DQ27

DQ4 DQ28

DQ5 DQ29

DQ6 DQ30

DQ7 DQ31

MICRON_GDDR5X

22uF 10uF 4.7uF 1uF 0.1uF

VDD

VDDQ

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8

VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
VDDQ_28
VDDQ_29
VDDQ_30
VDDQ_31
VDDQ_32
VDDQ_33
VDDQ_34
VDDQ_35
VDDQ_36
VDDQ_37
VDDQ_38
VDDQ_39
VDDQ_40
VDDQ_41
VDDQ_42
VDDQ_43
VDDQ_44

VSSQ_1

VSSQ_2

VSSQ_3

VSSQ_4

VSSQ_5

VSSQ_6

VSSQ_7

VSSQ_8

VSSQ_9
VSSQ_10
VSSQ_11
VSSQ_12
VSSQ_13
VSSQ_14
VSSQ_15
VSSQ_16
VSSQ_17
VSSQ_18
VSSQ_19
VSSQ_20
VSSQ_21
VSSQ_22
VSSQ_23
VSSQ_24

VPP_1
VPP_2

4 5

4 5

1

B4
B3
C4
C3
F4
F3
G4
G3
B11
B12
C11
C12
F11
F12
G11
G12
V11
V12
U11
U12
P11
P12
N11
N12
V4
V3
U4
U3
P4
P3
N4
N3

A13
A2
B10
B5
C1
C13
C14
C2
E1
E11
E13
E14
E2
E4
F10
F5
G13
G2
H12
H3
J13
J2
L13
L2
M12
M3
N13
N2
P10
P5
R1
R11
R13
R14
R2
R4
U1
U13
U14
U2
V10
V5
W13
W2

B13
B2
C10
C5
D13
D2
E10
E5
F13
F2
G10
G5
N10
N5
P13
P2
R10
R5
T13
T2
U10
U5
V13
V2

A3
W3

+1.35VSDGPU_S

+1.8VSDGPU_AON_S

FBH_D32 <56>
FBH_D33 <56>
FBH_D34 <56>
FBH_D35 <56>
FBH_D36 <56>
FBH_D37 <56>
FBH_D38 <56>
FBH_D39 <56>
FBH_D40 <56>
FBH_D41 <56>
FBH_D42 <56>
FBH_D43 <56>
FBH_D44 <56>
FBH_D45 <56>
FBH_D46 <56>
FBH_D47 <56>
FBH_D48 <56>
FBH_D49 <56>
FBH_D50 <56>
FBH_D51 <56>
FBH_D52 <56>
FBH_D53 <56>
FBH_D54 <56>
FBH_D55 <56>
FBH_D56 <56>
FBH_D57 <56>
FBH_D58 <56>
FBH_D59 <56>
FBH_D60 <56>
FBH_D61 <56>
FBH_D62 <56>
FBH_D63 <56>

12

8

+1.8VSDGPU_AON_S

A A

5

Under VRAM

1

1

CG117

CG118

2

2

.1U_0402_16V7K

.1U_0402_16V7K

1

1

CG326

CG903

2

2

.1U_0402_16V7K

.1U_0402_16V7K

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

N17E-GDDR5_D-S

N17E-GDDR5_D-S

N17E-GDDR5_D-S

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

64 103Monday, January 09, 2017

64 103Monday, January 09, 2017

64 103Monday, January 09, 2017

1.0

1.0

1.0

A

B

C

D

E

LED PANEL Conn.

JEDP2

W=80mils

ACES_50273-01001-001ES_87212-10G0

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

10

SP02000UL00

11

G11

9

12

G12

10

use JBTN symbol, SP02000UL00 footprint

XEMC@

Place closed to JEDP1

+LCDVDD

1

C242
.1U_0402_16V7K

2

@

EDP_TXN3_C
EDP_TXP3_C

EDP_TXN2_C
EDP_TXP2_C

EDP_TXN1_C
EDP_TXP1_C

EDP_TXN0_C
EDP_TXP0_C

EDP_AUXP_C
EDP_AUXN_C

+LCDVDD

EDP_HPD

USB20_N8_R
USB20_P8_R
BKOFF#_LCD
DGPU_INV_PWM

USB20_N9_R
USB20_P9_R
LCD_OD_3V

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39

eDP CONN.

eDP CONN.

eDP CONN.

JEDP1

1

GND

2

BATT_WHITE_LED

3

BATT_YELLOW_LED

4

BREATH_WHITE_LED

5

VR_SRC

6

VR_SRC

7

VR_SRC

8

NC

9

DISP_ON/OFF#
PWM
CONNTST_GND
VR_GND
VR_GND
VR_GND
LCD_B_CLK+
LCD_B_CLK­GND
LVDS_B2+
LVDS_B2­LVDS_B1+
LVDS_B1­LVDS_B0+
LVDS_B0­GND
LVDS_A_CLK+
LVDS_A_CLK­GND
LVDS_A2+
LVDS_A2­LVDS_A1+
LVDS_A1­LVDS_A0+
LVDS_A0­EDID_DATA
EDID_CLK
BIST
V_EDID
LCD_VDD
LCD_VDD
CONNTST40MGND1

ACES_59003-04006-001

SP01001BT00

CONN@

46

MGND6

45

MGND5

44

MGND4

43

MGND3

42

MGND2

41

65 103Monday, January 09, 2017

65 103Monday, January 09, 2017

65 103Monday, January 09, 2017

E

1.0

1.0

1.0

68P_0402_50V8J

XEMC@

DGPU_INV_PWM<41>

R406
10K_0402_5%@

LCD_OD_3V

+INVPWR_B+B+

1000P_0402_50V7K

1

1

C239

XEMC@

2

2

+LCDVDD

XEMC@

1 2

C252 220P_0402_50V7K

1 2

R234 10K_0402_5%@

1 2

R379 100K_0402_5%@

LCD POWER CIRCUIT

C236

1U_0402_6.3V6K

1

1 1

2 2

2

DGPU_ENVDD<41>

EDP_TXP0<43>

EDP_TXN0<43>

EDP_TXP1<43>

EDP_TXN1<43>

EDP_TXP2<43>

EDP_TXN2<43>

EDP_TXP3<43>

EDP_TXN3<43>

EDP_AUXP<43>

EDP_AUXN<43>

+3VS

C243 .1U_0402_16V7K
C244 .1U_0402_16V7K
C245 .1U_0402_16V7K
C246 .1U_0402_16V7K
C247 .1U_0402_16V7K
C248 .1U_0402_16V7K
C250 .1U_0402_16V7K
C251 .1U_0402_16V7K

C253 .1U_0402_16V7K
C254 .1U_0402_16V7K

U34

5

IN

4

EN

SY6288C20AAC_SOT23-5

12

R232
100K_0402_5%

@

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

EDP_TXP0_C
EDP_TXN0_C
EDP_TXP1_C
EDP_TXN1_C
EDP_TXP2_C
EDP_TXN2_C
EDP_TXP3_C
EDP_TXN3_C

EDP_AUXP_C
EDP_AUXN_C

W=60mils

1

OUT

2

GND

3

OC

EDP_AUXN_C

R236100K_0402_5%

EDP_AUXP_C

R237100K_0402_5%

EDP_AUXN

R414100K_0402_5%

EDP_AUXP

R413100K_0402_5%

+LCDVDD+5VS

1

2

C237

4.7U_0603_6.3V6K

DGPU_EDP_HPD#<41>

1

C238
.1U_0402_16V7K

2

@

Q33B

DMN66D0LDW-7_SOT363-6

+1.8VSDGPU_AON

12

R372
10K_0402_5%

61

D

G

S

2

1 2

12

R238
100K_0402_5%

R235
0_0402_5%

@

EDP_HPD

W=80mils W=80mils

BKOFF#<38>

LCD_OD<38>

F1

21

7A_32V_S1206-H-7.0A

Q33A

DMN66D0LDW-7_SOT363-6

SM01000EJ00 3000ma
220ohm@100mhz

DCR 0.04

+3VS

5

34

SGD

1 3

D

2N7002W -T/R7_SOT323-3

1 2

R808 0_0402_5%

+LCDVDD

2

L12

HCB2012KF-221T30_0805

1 2

EMC@

12

R405
510_0402_1%

BKOFF#_LCD

+3VS

12

G

S

Q29

@

+INVPWR_B+B+_INVPWR

C240

12

R400

2.2K_0402_5%

1 2

R233 100K_0402_5%@

1 2

C249 220P_0402_50V7K

G-SYNC#<41>

HD CAM POWER CIRCUIT

+3VS_CAM

+3VS

C110

EMC@

.1U_0402_16V7K

3 3

CAM_EN<38>

1 2

CAM_EN

U16

5

OUT

IN

GND

4

EN

SY6288C20AAC_SOT23-5

CAM@

+3VS_CAM

1
2
3

OC

W=60mils

TS POWER CIRCUIT

+3VS+5VS

R415 0_0603_5%@
R416 0_0603_5%@

C426 1U_0402_6.3V6K@

4 4

C255 .1U_0402_16V7K@

12
12

U45

+TS_PW R_IN

12

12

TS_EN<38>

12

5

IN

4

EN

SY6288C20AAC_SOT23-5

R370
100K_0402_5%

@

@

1

OUT

2

GND

3

OC

SY6288C20 Current Limit 3A

A

+3VS_CAM

W=60mils

1

@

2

C428

4.7U_0603_6.3V6K

1

C111
.1U_0402_16V7K

2

CAM@

+TS_PW R

1

2

B

C427

@

.1U_0402_16V7K

1 2

12

CI2

CI1

1

@

CAM@

10U_0603_6.3V6M~D

47U_0805_6.3V6M~D

2

USB20_N8<18>

USB20_P8<18>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

USB20_N9<18>

USB20_P9<18>

1 2

R378 0_0402_5%XEMC@

1 2

R377 0_0402_5%XEMC@

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

C

@

R111 0_0402_5%

1 2

@

R112 0_0402_5%

USB20_N8_R

USB20_P8_R

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

USB20_N9_R

USB20_P9_R

D

Touch Screen

HD Cam

+TS_PW R

+3VS_CAM

default floating

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

5

4

3

2

1

Place close to JHDMI

W=20mils

+5VS

D D

12

VGA_TMDS_TXCP<43>

VGA_TMDS_TXCN<43>

VGA_TMDS_TX0P<43>

VGA_TMDS_TX0N<43>

VGA_TMDS_TX1P<43>

VGA_TMDS_TX1N<43>

C C

B B

VGA_TMDS_TX2P<43>

VGA_TMDS_TX2N<43>

CV2 .1U_0402_16V7K

12

CV1 .1U_0402_16V7K

12

CV4 .1U_0402_16V7K

12

CV3 .1U_0402_16V7K

12

CV6 .1U_0402_16V7K

12

CV5 .1U_0402_16V7K

12

CV8 .1U_0402_16V7K

12

CV7 .1U_0402_16V7K

TMDS_TXCP
TMDS_TXCN
TMDS_TX1P
TMDS_TX1N

TMDS_TX2P
TMDS_TX2N
TMDS_TX0P
TMDS_TX0N

RP1

1 8
2 7
3 6
4 5

499_0804_8P4R_1%

RP2

1 8
2 7
3 6
4 5

499_0804_8P4R_1%

TMDS_TXCP

TMDS_TXCN

TMDS_TX0P

TMDS_TX0N TMDS_L_TX1N_R

TMDS_TX1P

TMDS_TX1N

TMDS_TX2P

TMDS_TX2N

1 2

RV35 0_0402_5%@

1 2

RV36 0_0402_5%@

1 2

RV37 0_0402_5%@

1 2

RV38 0_0402_5%@

1 2

RV39 0_0402_5%@

1 2

RV40 0_0402_5%@

1 2

RV41 0_0402_5%@

1 2

RV42 0_0402_5%@

LV1

EMC@

1 2

HCM1012GH900BP_4P

LV2

EMC@

1 2

HCM1012GH900BP_4P

LV3

EMC@

1 2

HCM1012GH900BP_4P

LV4

EMC@

1 2

HCM1012GH900BP_4P

+3VS

2

G

TMDS_L_TXCP

TMDS_L_TXCN

34

TMDS_L_TX0P

TMDS_L_TX0N

34

TMDS_L_TX1P

TMDS_L_TX1N

34

TMDS_L_TX2P

TMDS_L_TX2N

34

13

D

QX1
L2N7002WT1G_SC-70-3

S

1 2

RV27 6.04 +-1% 0402

1 2

RV28 6.04 +-1% 0402

1 2

RV29 6.04 +-1% 0402

1 2

RV30 6.04 +-1% 0402

1 2

RV31 6.04 +-1% 0402

1 2

RV32 6.04 +-1% 0402

1 2

RV33 6.04 +-1% 0402

1 2

RV34 6.04 +-1% 0402

TMDS_L_TXCP_R

TMDS_L_TXCN_R

TMDS_L_TX0P_R

TMDS_L_TX0N_R

TMDS_L_TX1P_R

TMDS_L_TX1N_R

TMDS_L_TX2P_R

TMDS_L_TX2N_R

DGPU_HDMI_HPD#<41>

UV1

1

IN

AP2330W -7_SC59-3

+1.8VSDGPU_AON

2N7002W -T/R7_SOT323-3

OUT

GND

+HDMI_5V_OUT

DGPU_PEX_RST#_G<41>

TMDS_SCLK<43>

TMDS_SDATA<43>

W=20mils

3

2

+1.8VSDGPU_AON

Q30

+HDMI_5V_OUT +HDMI_5V_OUT

W=20mils

1

CV9

2

0.1U_0402_16V7K

RP3

2.2K_0804_8P4R_5%

12

RX12
10K_0402_5%

13

D

2

G

S

2

3

1

TMDS_SCLK_R

18

TMDS_SDATA

27

TMDS_SCLK

36

TMDS_SDATA_R

45

5

34

SGD

Q31A

2

PJT138KA 2N SOT363-6

G

61

S

D

Q31B
PJT138KA 2N SOT363-6

12

R395
100K_0402_5%

MESC5V02BD03_SOT23-3

D32

XEMC@

HDMI_HPLUG

TMDS_SDATA_R
TMDS_SCLK_R

TMDS_L_TXCN_R
TMDS_L_TXCP_R

TMDS_L_TX0N_R
TMDS_L_TX0P_R

TMDS_L_TX1P_R
TMDS_L_TX2N_R

TMDS_L_TX2P_R

TMDS_SCLK_R

TMDS_SDATA_R

HDMI_HPLUG

+3VS

12

RV3
10K_0402_5%@

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Utility

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4
3
2
1

GND

D1+

GND

D2-

GND

D2_shield

GND

D2+

GND

LOTES_ABA-HDM-013-P09

DC231603150

CONN@

NPTH

24
20
21
22
23

A A

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2016/02/01 2017/12/31

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HDMI LS & Conn.

HDMI LS & Conn.

HDMI LS & Conn.

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

66 103Monday, January 09, 2017

66 103Monday, January 09, 2017

66 103Monday, January 09, 2017

1

1.0

1.0

1.0

A

B

C

D

E

VGA side

1 2

R391 100K_0402_5%

1 2

R392 100K_0402_5%

DP4_AUXP
DP4_AUXN

Display Port

1 1

DGPU_DP4_HPD#<41>

conn side

+3VS_DP

1 2

R401 100K_0402_5%

1 2

R402 100K_0402_5%

+1.8VSDGPU_AON

12

RX7
10K_0402_5%

QV97A

34

DMN66D0LDW-7_SOT363-6

D

G

5

S

W=40mils W=40mils

+3VS

2 2

.1U_0402_16V7K

+3VS

CV56

10K_0402_5%

12

RX14

12

UV3

5

OUT

IN

GND

4

OC

EN

SY6288C20AAC_SOT23-5

1
2
3

+3VS_DP

.1U_0402_16V7K

1

CV27

2

VGA side

1 2

R393 100K_0402_5%

1 2

R394 100K_0402_5%

DP4_AUXP_C
DP4_AUXN_C

DP4_HPD

12

R396
100K_0402_5%

DP5_AUXP
DP5_AUXN

DP4_HPD

12

DP4_AUXP<42>
DP4_AUXN<42>

DP4_TXP3<42>
DP4_TXN3<42>

DP4_TXP2<42>
DP4_TXN2<42>

DP4_TXP1<42>
DP4_TXN1<42>

DP4_TXP0<42>
DP4_TXN0<42>

CV35 .1U_0402_16V7K

12

CV36 .1U_0402_16V7K

12

CV38 .1U_0402_16V7K

12

CV39 .1U_0402_16V7K

12

CV40 .1U_0402_16V7K

12

CV37 .1U_0402_16V7K

12

CV42 .1U_0402_16V7K

12

CV41 .1U_0402_16V7K

12

CV44 .1U_0402_16V7K

12

CV43 .1U_0402_16V7K

DP4_AUXP_C
DP4_AUXN_C

DP4_TXP3_C
DP4_TXN3_C

DP4_TXP2_C
DP4_TXN2_C

DP4_TXP1_C
DP4_TXN1_C

DP4_TXP0_C
DP4_TXN0_C

JDP1

18

HOT PLUG

DP_PWR

15

AUX_CH_P

17

AUX_CH_N

10

LANE3_P

12

LANE3_N

7

LANE2_P

9

LANE2_N

4

LANE1_P

6

LANE1_N

1

LANE0_P

3

LANE0_N

TAIWI_DP008-207CRL-TW

DC061603150

CONN@

Return

GND1
GND2
GND3
GND4

GND
GND
GND
GND
GND
GND
GND

W=40mils

20
19
16
14
13
11
8
5
2

21
22
23
24

+3VS_DP

Display Port

conn side

+3VS_DP

3 3

DGPU_DP5_HPD#<41>

1 2

R403 100K_0402_5%

1 2

R404 100K_0402_5%

+1.8VSDGPU_AON

12

RX9
10K_0402_5%

QV97B

61

DMN66D0LDW-7_SOT363-6

D

G

2

S

DP5_AUXP_C
DP5_AUXN_C

DP5_HPD

12

R397
100K_0402_5%

DP5_HPD

12

DP5_AUXP<42>
DP5_AUXN<42>

DP5_TXP3<42>
DP5_TXN3<42>

DP5_TXP2<42>
DP5_TXN2<42>

DP5_TXP1<42>
DP5_TXN1<42>

DP5_TXP0<42>
DP5_TXN0<42>

CV46 .1U_0402_16V7K

12

CV45 .1U_0402_16V7K

12

CV48 .1U_0402_16V7K

12

CV47 .1U_0402_16V7K

12

CV50 .1U_0402_16V7K

12

CV49 .1U_0402_16V7K

12

CV52 .1U_0402_16V7K

12

CV51 .1U_0402_16V7K

12

CV54 .1U_0402_16V7K

12

CV53 .1U_0402_16V7K

DP5_AUXP_C
DP5_AUXN_C

DP5_TXP3_C
DP5_TXN3_C

DP5_TXP2_C
DP5_TXN2_C

DP5_TXP1_C
DP5_TXN1_C

DP5_TXP0_C
DP5_TXN0_C

JDP2

18

HOT PLUG

DP_PWR

15

AUX_CH_P

17

AUX_CH_N

10

LANE3_P

12

LANE3_N

7

LANE2_P

9

LANE2_N

4

LANE1_P

6

LANE1_N

1

LANE0_P

3

LANE0_N

TAIWI_DP008-207CRL-TW

DC061603150

CONN@

Return

GND1
GND2
GND3
GND4

GND
GND
GND
GND
GND
GND
GND

W=40mils

20
19
16
14
13
11
8
5
2

21
22
23
24

+3VS_DP

4 4

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/02/01 2017/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DP Connector

DP Connector

DP Connector

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1.0

1.0

1.0

67 103Monday, January 09, 2017

67 103Monday, January 09, 2017

67 103Monday, January 09, 2017

E

5

+3.3V_TBT_SX

12

+3VS

G

2

CLKREQ_P CIE#5<21>

PU at PCH side.

D D

+3.3V_LC

R268

12

TBT@

TBT@

10K_0402_5%

DP0_HPD_GPU#<41>

C C

2N7002W -T/R7_SOT323-3

S

Q34
L2N7002WT1G_SC-7 0-3

R269

12

TBT@

10K_0402_5%

TBT@

R270

12

R271

12

TBT@

10K_0402_5%

+1.8VSDGP U_AON

Q32

10K_0402_5%

TBT_TDI
TBT_TMS
TBT_TCK
TBT_TDO

D

S

R265
10K_040 2_5%TBT@

TBT_CLKREQ_PCIE#5

13

D

TBT@

PCIE X4 Bus

(Link to PCH Port 5 ~8)

PCIE CLK

(From PCH CLKOUT0)

DDC:3.3V
PU @ SOC side

12

R390
10K_040 2_5%TBT@

13

DP0_HPD

2

G

12

R398
100K_04 02_5%

+3VS_TBT

Follow Intel recommend, 5/4.

HDMI_SCLK
HDMI_SDATA

RTD3_CIO_PW R_EN_R
RTD3_USB_P WR_EN_R

Follow Intel recommend, 4/28.

TBT_I2C_SDA1
TBT_I2C_SCL1
TBT_PCIE_W AKE_N
TBT_CIO_PLUG _EVENT#
SLP_S3#

BATLOW#
TBTA_I2C_INT1

TBT_POC_GPIO_1
TBT_SRC_CFG1

CFG1 PU is HDMI MODE
CFG1 PL if DPSRC NOT IN USE

B B

A A

TBT_SRC_CFG1="0" => AUX CONNECTS TO AR
TBT_SRC_CFG1="1" => DDC CONNECTS TO AR
3/3

TBT_TMU_CLK_OUT
TBT_FORCE_PW R_R

PS8338 Internal PD

DP0_HPD_GPU#
TBTA_LSTX

TBTA_HPD
TBTA_LSRX
TBT_SNK1_DDC_CLK
SNK0_CONFIG1

PB_LSTX
PB_LSRX
PB_DPSRC_HPD

SNK0_DDC_ CLK
SNK0_DDC_ DATA

SNK0_DDC_connect 2k PU only if SRC0 is connected HDMI
otherrise can be 100k PD

TBT_DP0_AUXP
TBT_DP0_AUXN

12

R281 2.2K_0402 _5%TBT@

12

R282 2.2K_0402 _5%TBT@

12

R283 10K_040 2_5%TBT@

12

R284 10K_040 2_5%@

12

R409 10K_040 2_5%TBT@

12

R286 2.2K_0402 _5%TBT@

12

R287 2.2K_0402 _5%TBT@

12

R288 10K_040 2_5%TBT@

12

R289 10K_040 2_5%TBT@

12

R290 10K_040 2_5%TBT@

12

R291 10K_040 2_5%TBT@

12

R292 10K_040 2_5%TBT@

12

R293 10K_040 2_5%TBT@

12

R294 10K_040 2_5%@

12

R369 1M_0402_5%TBT@

1 2

R295 100K_0402_5%TBT@

1 2

R296 100K_0402_5%TBT@

1 2

R299 100K_0402_5%@

1 2

R300 1M_0402_1 %TBT@

1 2

R301 100K_0402_5%TBT@

1 2

R302 1M_0402_1 %TBT@

1 2

R303 100K_0402_5%TBT@

1 2

R304 100K_0402_5%TBT@

1 2

R305 100K_0402_5%TBT@

1 2

R306 100K_0402_5%TBT@

1 2

R309 100K_0402_5%TBT@

follow SP ref sch v0.998

1 2

R388 100K_0402_5%TBT@

1 2

R389 100K_0402_5%TBT@

1 2

R802 100K_0402_5%TBT@

1 2

R803 100K_0402_5%TBT@

+3.3V_TBT_SX

Ref B 10k PL / BAD40 100K PL 3/3

USB3_A_TTX_C_DRX_P1<70>
USB3_A_TTX_C_DRX_N1<7 0>

USB3_A_TTX_C_DRX_P0<70>
USB3_A_TTX_C_DRX_N0<7 0>

USB3_A_TRX_DTX_P1<70>

USB3_A_TRX_DTX_N1<70 >

USB3_A_TRX_DTX_P0<70>

USB3_A_TRX_DTX_N0<70 >

4

PCIE_PTX_C_DRX_P5<18>
PCIE_PTX_C_DRX_N5<18>

PCIE_PTX_C_DRX_P6<18>
PCIE_PTX_C_DRX_N6<18>

PCIE_PTX_C_DRX_P7<18>
PCIE_PTX_C_DRX_N7<18>

PCIE_PTX_C_DRX_P8<18>
PCIE_PTX_C_DRX_N8<18>

CLK_PCIE_P5<21>
CLK_PCIE_N5<21>

TBT_DP0_P0<4 2>

TBT_DP0_N0<42>

TBT_DP0_P1<4 2>

TBT_DP0_N1<42>

TBT_DP0_P2<4 2>

TBT_DP0_N2<42>

TBT_DP0_P3<4 2>

TBT_DP0_N3<42>

TBT_DP0_AUXP<42>

TBT_DP0_AUXN<42>

TBT_A_AUX_P _C<70>
TBT_A_AUX_N_C<70>

TBT_A_USB20 _P<70>
TBT_A_USB20 _N<70>

TBTA_LSTX<7 0>

TBTA_LSRX<70>

TBTA_HPD<70>

C275 0.1U_0 402_16V 7KTBT@
C277 0.1U_0 402_16V 7KTBT@

C279 0.1U_0 402_16V 7KTBT@
C281 0.1U_0 402_16V 7KTBT@

C282 0.1U_0 402_16V 7KTBT@
C284 0.1U_0 402_16V 7KTBT@

C286 0.1U_0 402_16V 7KTBT@
C287 0.1U_0 402_16V 7KTBT@

C291 0.1U_0 402_16V 7KTBT@
C292 0.1U_0 402_16V 7KTBT@

C295 0.2 2U_0201_ 6.3V6MTBT@
C296 0.2 2U_0201_ 6.3V6MTBT@

C297 0.2 2U_0201_ 6.3V6MTBT@
C299 0.2 2U_0201_ 6.3V6MTBT@

C300 0.1U_0 402_16V 7KTBT@
C302 0.1U_0 402_16V 7KTBT@

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

TBT@

R285 4.75K _0402_0 .5%

1 2
1 2

1 2
1 2

1 2
1 2

PCIE_PTX_C_DRX_P5
PCIE_PTX_C_DRX_N5

PCIE_PTX_C_DRX_P6
PCIE_PTX_C_DRX_N6

PCIE_PTX_C_DRX_P7
PCIE_PTX_C_DRX_N7

PCIE_PTX_C_DRX_P8
PCIE_PTX_C_DRX_N8

TBT_CLKREQ_PCIE#5

12

TBT@

R280 14K_040 2_1%

12

12

TBT@

R297 499_040 2_1%

TBT_DP0_P0_ C
TBT_DP0_N0_C

TBT_DP0_P1_ C
TBT_DP0_N1_C

TBT_DP0_P2_ C
TBT_DP0_N2_C

TBT_DP0_P3_ C
TBT_DP0_N3_C

TBT_DP0_AUXP_C
TBT_DP0_AUXN_C

DP0_HPD
SNK0_DDC_ CLK

SNK0_DDC_ DATA

TBT_SNK1_DDC_CLK
SNK0_CONFIG1

DPSNK_RBIAS
TBT_TDI

TBT_TMS
TBT_TCK
TBT_TDO

TBT_RBIAS
TBT_RSENSE

USB3_A_TTX_DRX_P1
USB3_A_TTX_DRX_N1

USB3_A_TTX_DRX_P0
USB3_A_TTX_DRX_N0

TBT_A_AUX_P
TBT_A_AUX_N

PA_USB2_RBIAS PB_USB2_RBIAS

AB11
AC11

AB13
AC13

AB15
AC15

AB17
AC17

AB19
AC19

AB21
AC21

AC23
AB23

Y23
Y22

T23
T22

M23
M22

H23
H22

V19

T19

AC5

AB7

AC7

AB9

AC9

Y11

W11

AA2

Y5

R4

Y12

W12

Y6
Y8

N4

Y18

Y4
V4
T4

W4

H6

J6

A15
B15

A17
B17

A19
B19

B21
A21

Y15

W15

E20
D20

A5
A4

M4

H19

V18

AC1

L15

N15
C23

C22

3

U36A

PCIE_RX0_P
PCIE_RX0_N

PCIE_RX1_P
PCIE_RX1_N

PCIE_RX2_P
PCIE_RX2_N

PCIE_RX3_P
PCIE_RX3_N

PCIE_REFCLK_100_IN_P
PCIE_REFCLK_100_IN_N
PCIE_CLKREQ_N

DPSNK0_ML0_P
DPSNK0_ML0_N

DPSNK0_ML1_P
DPSNK0_ML1_N

DPSNK0_ML2_P
DPSNK0_ML2_N

DPSNK0_ML3_P
DPSNK0_ML3_N

DPSNK0_A UX_P
DPSNK0_A UX_N

DPSNK0_HPD
DPSNK0_DDC_CLK

DPSNK0_DDC_DATA
DPSNK1_ML0_P

DPSNK1_ML0_N
DPSNK1_ML1_P

DPSNK1_ML1_N
DPSNK1_ML2_P

DPSNK1_ML2_N
DPSNK1_ML3_P

DPSNK1_ML3_N
DPSNK1_A UX_P

DPSNK1_A UX_N
DPSNK1_HPD
DPSNK1_DDC_CLK

DPSNK1_DDC_DATA
DPSNK_RBIAS
TDI

TMS
TCK
TDO

RBIAS
RSENSE

PA_RX1_P
PA_RX1_N

PA_TX1_P
PA_TX1_N

PA_TX0_P
PA_TX0_N

PA_RX0_P
PA_RX0_N

PA_DPSRC_AUX_P
PA_DPSRC_AUX_N

PA_USB2_D_P
PA_USB2_D_N

PA_LSTX
PA_LSRX
PA_DPSRC_HPD

PA_USB2_RBIAS
THERMDA

THERMDA
PCIE_ATEST
TEST_EDM
FUSE_VQP S_64

FUSE_VQP S_128
MONDC_CIO_ 0

MONDC_CIO_ 1

AR4C_FC-CSP337

@

2

PCIE_TX0_P
PCIE_TX0_N

PCIE_TX1_P
PCIE_TX1_N

PCIE_TX2_P
PCIE_TX2_N

PCIE_TX3_P
PCIE_TX3_N

PCIe GEN3

SINK PORT 0

SINK PORT 1

MISC

Port A

TBT PORTS

POC

DEBUG

DPSRC_ML0 _P
DPSRC_ML0 _N

DPSRC_ML1 _P
DPSRC_ML1 _N

DPSRC_ML2 _P
DPSRC_ML2 _N

DPSRC_ML3 _P
DPSRC_ML3 _N

DPSRC_AUX _P
DPSRC_AUX _N

SOURCE PORT 0

DPSRC_RBIAS

LC GPIOPOC GPIO

TEST_PWR_ GOOD

Misc

XTAL_25_OUT

PB_DPSRC_AUX_P
PB_DPSRC_AUX_N

PORT B

PB_USB2_D_P
PB_USB2_D_N

PB_DPSRC_HPD

POC

PB_USB2_RBIAS

MONDC_DPSNK_0
MONDC_DPSNK_1

MONDC_DPSRC

PERST_N

PCIE_RBIA S

DPSRC_HPD

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7

GPIO_8
POC_GPIO _0
POC_GPIO _1
POC_GPIO _2
POC_GPIO _3
POC_GPIO _4
POC_GPIO _5
POC_GPIO _6

TEST_EN

RESET_N

XTAL_25_IN

EE_DO

EE_CS_N

EE_CLK

PB_RX1_P
PB_RX1_N

PB_TX1_P
PB_TX1_N

PB_TX0_P
PB_TX0_N

PB_RX0_P
PB_RX0_N

PB_LSTX
PB_LSRX

MONDC_SVR

ATEST_P
ATEST_N

USB2_ATES T

EE_DI

PCIE_PRX_C_DTX_N5

V22

PCIE_PRX_C_DTX_P6

P23

PCIE_PRX_C_DTX_N6

P22

PCIE_PRX_C_DTX_P7

K23

PCIE_PRX_C_DTX_N7

K22

PCIE_PRX_C_DTX_P8

F23

PCIE_PRX_C_DTX_N8

F22

TBT_RST#_R

L4

PCIE_RBIA S

N16
R2

R1
N2

N1
L2

L1
J2

J1
W19

Y19

DPSRC_HPD

G1

DPSRC_RBIAS

N6
U1

U2

TBT_EE_WP_N

V1

TBT_TMU_CLK_OUT

V2

TBT_PCIE_W AKE_N

W1

TBT_CIO_PLUG _EVENT#

W2

HDMI_SDATA

Y1

HDMI_SCLK

Y2

TBT_SRC_CFG1

AA1
J4

TBT_POC_GPIO_1

E2

RTD3_USB_P WR_EN_R

D4

TBT_FORCE_PW R_R

H4
F2

BATLOW#
SLP_S3#

D2

RTD3_CIO_PW R_EN_R

F1

TBT_TEST_EN

E1

TBT_TEST_PWG

AB5
F4

TBT_XTAL_25_ IN

D22

TBT_XTAL_25_ OUT

D23
AB3

AC4
AC3
AB4

B7
A7

A9
B9

A11
B11

A13
B13

Y16
W16

E19
D19

PB_LSTX

B4

PB_LSRX

B5

PB_DPSRC_HPD

G2
F19
D6
A23

B23
E18
W13
W18
AB2

R264 0_040 2_5%@

1 2

R266 3.01K_040 2_1%TBT@

R410 1M_0402_1 %TBT@
R267 14K_0402_1%TBT@

R272 0_0402_5%@

R278 100_0 402_5%TBT@
R279 100_0 402_5%TBT@

TBT_EE_DI <70>
TBT_EE_DO <70 >
TBT_EE_CS_N <70>
TBT_EE_CLK <70 >

1 2

TBT@

R298 499_040 2_1%

R310

3.3K_0402_5%

TBT@

1 2
1 2

1 2

R273 0_0 402_5%@
R274 0_0 402_5%@
R275 0_0 402_5%@
R276 0_0 402_5%@

R277 0_0 402_5%@

1 2
1 2

12

12

1 2
1 2
1 2
1 2
1 2

3.3K_0402_5%

TBT_I2C_SDA1 <70>
TBT_I2C_SCL1 <70>

TBTA_I2C_INT1 <70>

TBT_RESET_N <7 0>

12

R307

TBT@

PCIE_PRX_C_DTX_P5

V23

PCIE_PRX_DTX_P5

12

C2710 .22U_040 2_16V7K TBT@

PCIE_PRX_DTX_N5

12

C2720 .22U_040 2_16V7K TBT@

PCIE_PRX_DTX_P6

12

C2730 .22U_040 2_16V7K TBT@

PCIE_PRX_DTX_N6

12

C2740 .22U_040 2_16V7K TBT@

PCIE_PRX_DTX_P7

12

C3970 .22U_040 2_16V7K TBT@

PCIE_PRX_DTX_N7

12

C3980 .22U_040 2_16V7K TBT@

PCIE_PRX_DTX_P8

12

C3990 .22U_040 2_16V7K TBT@

PCIE_PRX_DTX_N8

12

C4000 .22U_040 2_16V7K TBT@

T24@

EC_TBT_WA KE# <38>

TBT_CIO_PLUG _EVENT# <19>

T67@
T68@

RTD3_USB_P WR_EN <19 >
TBT_FORCE_PW R <19>
TBT_BATLOW# <19>
SUSP# <25,26,28,3 2,38,75,77,79,80>
RTD3_CIO_PW R_EN <19>

Y1
25MHZ_12PF_7V250 00012

1

1

1

C293

10P_040 2_50V8J

2

TBT@

12

R308

3.3K_0402_5%

TBT@

TBT_EE_CS_N
TBT_EE_DO
TBT_EE_WP_N TBT_EE _CLK

1
2
3
4

PCIE_PRX_DTX_P5 <18>

PCIE_PRX_DTX_N5 <18>

PCIE_PRX_DTX_P6 <18>

PCIE_PRX_DTX_N6 <18>

PCIE_PRX_DTX_P7 <18>

PCIE_PRX_DTX_N7 <18>

PCIE_PRX_DTX_P8 <18>

PCIE_PRX_DTX_N8 <18>

PLT_RST_BUF# <19,2 8,29,30,31,32,41,53>

POC_GPIO _0

POC_GPIO _1

POC_GPIO _2

POC_GPIO _3

POC_GPIO _4

POC_GPIO _5

POC_GPIO _6

TBT_PCIE_W AKE_N

to EC

to CPU GPP_D0 (PCH supports SCI function pin)3/3

3

3

GND

4

+3.3V_FLA SH

HOLD#(IO3)

DI(IO0)

1

2

VCC

CLK

1

2

C305
.1U_0402 _16V7K

GND

TBT@

2

U37

CS#
DO(IO1)
WP#(IO2 )

GND

W25Q8 0DVSSIG_SO8

TBT@

TBT_PCIE_W AKE_N <20>

TBTB_I2C_INT not use 3/3
From CPU GPP_D2
From_CPU_GPP_22 (GPO pin)
From CPU GPP_D21

From CPU GPP_D3

C294
10P_040 2_50V8J

TBT@

8
7
6

TBT_EE_DI

5

1

interrupt from port power switch

interrupt from port power switch

rtd3 power enable for USB mode

force full power on

bat t ery l o w i ndi c at i on

slp_s3 system indicat i on

rtd3 power enable for cio mode

to CPU wake#

on Sx systems don’ t connect it

n
non Sx systems don’ t connect it

12

R311

3.3K_0402_5%

TBT@

U36

TBT@

S IC JHL63 40 SLLSQ C1 THUNDERBO LT ABO!

SA00009YL70

5

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Alpine Ridge

Alpine Ridge

Alpine Ridge

Size

Document Number Re v

Size

Document Number Re v

Size

Document Number Re v

Custom

Custom

Custom
Date: Sheet of

Date: Sheet of

Date: Sheet of

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

68 103Monday, January 09, 2017

68 103Monday, January 09, 2017

68 103Monday, January 09, 2017

1.0

1.0

1.0

5

+3VALW +3.3V_TBT_SX

Option 1 for wake support over TBT:

1.Connect R312 and R313,

2.Simple BIOS implementation

D D

Option 2 for wake support over TBT:

1.Connect R312 and R314

2.Bios need to implement Sx emtry pre-notice flow by PCIe2TBT
Option 3 No wake support at all from AR

1. Connect R313 and R314

C C

B B

A A

1 2

R312 0_0603_5%

TBT@

1 2

R314 0_0603_5%

@

R313

+3VS_TBT+3VS

+3.3V_TBT_S0 +3VS_TBT

C345

TBT@

0_0603_5%

TBT@

1 2

1U_0201_6.3V6K

1

C313

C314

TBT@

TBT@

2

+0.9V_USB

1U_0201_6.3V6K

1U_0201_6.3V6K

1

C334

TBT@

1U_0201_6.3V6K

47U_0603_6.3V

C346

1

1

TBT@

2

TBT@

2

1

C335

TBT@

2

2

L14
1UH +-20% LQM18PN1R0MFHD

1 2

TBT@

47U_0603_6.3V

C347

1

2

1U_0201_6.3V6K

1

2

C336

TBT@

C320

TBT@

1

2

1

2

1U_0201_6.3V6K

C337

+0.9V_DP

1U_0201_6.3V6K

C315

TBT@

C319

TBT@

+0.9V_CIO

TBT@

4

0.1U_0201_6.3V6K

1

C307

C306

TBT@

2

U36B

1U_0201_6.3V6K

1U_0201_6.3V6K

1

C321

TBT@

2

1U_0201_6.3V6K

1

C328

TBT@

2

1U_0201_6.3V6K

1

1

C338

TBT@

2

2

C343

1U_0201_6.3V6K

1

1

C322

C316

TBT@

TBT@

2

2

+0.9V_PCIE

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

C330

C329

TBT@

TBT@

2

2

1U_0201_6.3V6K

+3.3V_ANA_PCIE
+3.3V_ANA_USB2

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

C344

TBT@

TBT@

2

2

L8

1U_0201_6.3V6K

VCC0P9_DP

L11

VCC0P9_DP

L12

1

2

1

2

1U_0201_6.3V6K

VCC0P9_DP

M8

VCC0P9_DP

T11

VCC0P9_DP

T12

VCC0P9_DP

L6

VCC0P9_ANA_DPSRC

M6

VCC0P9_ANA_DPSRC

V11

VCC0P9_ANA_DPSNK

V12

VCC0P9_ANA_DPSNK

V13

VCC0P9_ANA_DPSNK

M13

VCC0P9_PCIE

M15

VCC0P9_PCIE

M16

VCC0P9_PCIE

L19

VCC0P9_ANA_PCIE_1

N19

VCC0P9_ANA_PCIE_1

L18

VCC0P9_ANA_PCIE_2

M18

VCC0P9_ANA_PCIE_2

N18

VCC0P9_ANA_PCIE_2

R15

VCC0P9_USB

R16

VCC0P9_USB

R8

VCC0P9_CIO

R9

VCC0P9_CIO

R11

VCC0P9_CIO

R12

VCC0P9_CIO

L16

VCC3P3_ANA_PCIE

J16

VCC3P3_ANA_USB2

A6

VSS_ANA

A8

VSS_ANA

A10

VSS_ANA

A12

VSS_ANA

A14

VSS_ANA

A16

VSS_ANA

A18

VSS_ANA

A20

VSS_ANA

A22

VSS_ANA

B6

VSS_ANA

B8

VSS_ANA

B10

VSS_ANA

B12

VSS_ANA

B14

VSS_ANA

B16

VSS_ANA

B18

VSS_ANA

B20

VSS_ANA

B22

VSS_ANA

D8

VSS_ANA

D9

VSS_ANA

D11

VSS_ANA

D12

VSS_ANA

D13

VSS_ANA

D15

VSS_ANA

D16

VSS_ANA

D18

VSS_ANA

E8

VSS_ANA

E9

VSS_ANA

E11

VSS_ANA

E15

VSS_ANA

E16

VSS_ANA

E22

VSS_ANA

E23

VSS_ANA

F9

VSS_ANA

F16

VSS_ANA

F20

VSS_ANA

G22

VSS_ANA

G23

VSS_ANA

H1

VSS_ANA

H2

VSS_ANA

H12

VSS_ANA

H13

VSS_ANA

H15

VSS_ANA

H16

VSS_ANA

H20

VSS_ANA

J5

VSS_ANA

J18

VSS_ANA

J19

VSS_ANA

J20

VSS_ANA

J22

VSS_ANA

J23

VSS_ANA

K1

VSS_ANA

K2

VSS_ANA

L5

VSS_ANA

L20

VSS_ANA

L22

VSS_ANA

L23

VSS_ANA

M1

VSS_ANA

M2

VSS_ANA

M5

VSS_ANA

M19

VSS_ANA

M20

VSS_ANA

N5

VSS_ANA

N20

VSS_ANA

N22

VSS_ANA

N23

VSS_ANA

AR4C_FC-CSP337

@

TBT@

R6

VCC3P3_LC

VSS_ANAP1VSS_ANAP2VSS_ANAR5VSS_ANA

1

2

R18

1U_0201_6.3V6K

F8

VSS_ANA

R19

R20

3

+3.3V_TBT_S0

R13

VCC3P3_S0

VCC3P3_SX

VCC0P9_SVR_SENSE

VCC0P9_LVR_SENSE

GND VCC

VSS_ANA

VSS_ANA

VSS_ANA

VSS_ANAT1VSS_ANAT2VSS_ANAT5VSS_ANA

R22

R23

C308

H9

VCC3P3_SVR
VCC3P3_SVR
VCC3P3_SVR

VCC3P3A

VCC0P9_SVR

VCC0P9_SVR
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA

SVR_IND
SVR_IND
SVR_IND

SVR_VSS
SVR_VSS
SVR_VSS

VCC0P9_LVR

VCC0P9_LVR

VCC0P9_LVR

VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA

VSS_ANA

VSS_ANA

T20

U23

U22

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

TBT@

2

+3VS_TBT+3.3V_TBT_SX+3.3V_LC

1U_0201_6.3V6K

1

C309

TBT@

2

A2
A3
B3

L9
M9
E12
E13

C317

F11
F12

TBT@

F13
F15
J9

TBT_SVR_IND

C1
C2
D1

A1
B1
B2

+0.9V_LVR_OUT

F18
H18
J11
H11

V5
V6
V8
V9
V15
V16
V20
W5
W6
W8
W9
W20
W22
W23
Y9
Y13
Y20
AA22
AA23
AB6
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC6
AC8
AC10
AC12
AC14
AC16
AC18
AC20
AC22
D5
E4
E5
E6
F5
F6
H5
H8
J8
J12
J13
J15
L13
M11
M12
N8
N9
N11
N12
N13
T6
T8
T9
T13
T15
T16
T18
AB1
AC2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

C310

TBT@

2

1U_0201_6.3V6K

1

C323

TBT@

2

1 2

6/3, Change PN
to SHI000MD00

C339

TBT@

10U_0402_6.3V6M

1

1

C311

TBT@

2

2

1U_0201_6.3V6K

1

1

C324

TBT@

2

2

L13 0.6UH_MND-04ABIR60M-XGL_20%

TBT@

10U_0402_6.3V6M

1

1

C340

TBT@

2

2

C312

TBT@

+0.9V_SVR

1U_0201_6.3V6K

C325

TBT@

TBT@

10U_0402_6.3V6M

C341

TBT@

10U_0402_6.3V6M

1

2

1U_0201_6.3V6K

1U_0201_6.3V6K

1

C326

TBT@

2

47U_0603_6.3V

C331

1

TBT@

2

1U_0201_6.3V6K

1

C342

TBT@

2

1U_0201_6.3V6K

1

C327

TBT@

2

47U_0603_6.3V

C332

1

TBT@

2

1U_0201_6.3V6K

1

2

1U_0201_6.3V6K

1

1

C318

TBT@

2

2

47U_0603_6.3V

C333

1

2

Share same GND plane

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Alpine Ridge-POWER

Alpine Ridge-POWER

Alpine Ridge-POWER

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

69 103Monday, January 09, 2017

69 103Monday, January 09, 2017

69 103Monday, January 09, 2017

1.0

1.0

1.0

5

D D

2

G

S

3 4

DMN66D0LDW-7_SOT363-6

+3VALW

12

5

SGD

Q38A

TBT@

PD_IRQ# PU at EC side

100K_0402_5%

TBT_A_AUX_P_C<68>

TBT_A_AUX_N_C<6 8>

R806

2.2K_0402_5%

R807

2.2K_0402_5%

12

TBT@

TBT@

TBTA_I2C_SCL2

TBTA_I2C_SDA2

PD_IRQ#< 38>

TBT_A_USB20_P<68>

TBT_A_USB20_N<68>

TBTA_LSTX<68>
TBTA_LSRX<68>

+3.3V_TBT_SX

R326 100K_0402_5%TBT@
R328 100K_0402_5%TBT@

12

R330

TBT@

100K_0402_5%

R331 100K_0402_5%TBT@
R332 100K_0402_5%TBT@

12

+3.3V_FLASH

R335

TBT@

+1.8VS

TI suggest reserve 0ohm to 1.8V,3.3V,GND

1

C359

2.2U_0402_6.3V6M

2

TBT@

TBT_I2C_SDA1<68>
TBT_I2C_SCL1<68>

TBTA_I2C_INT1<68>

TBTA_I2C_SDA2
TBTA_I2C_SCL2

12

R319

@

10K_0402_5%

TBTA_HPD<68>

TBT_EE_CLK<68>

TBT_EE_DI<68>

TBT_EE_DO<68>

TBT_EE_CS_N<68>

TBT_A_USB20_P
TBT_A_USB20_N

12

R3201M_04 02_5%

TBT@

12

TBT@

R321 100K_0402_5%

1 2

R323 0_0402_5%@

1 2

R325 0_0402_5%@

12
12

12
12

1 2

BUSPOWER#

TBT@

R336 0_0402_5%

1 2

@

12

R338 0_0402_5%

R341

0_0402_5%

@

1 2

+3VALW

6 1

+3.3V_FLASH

12

@

12

@

D

Q38B

DMN66D0LDW-7_SOT363-6

TBT@

R420
10K_0402_5%

GPIO8_CFG

R421
10K_0402_5%

EC_SMB_CK3<32,35,38>

EC_SMB_DA3<32,35,38>

C C

Reserved for TPS65982D

B B

1

C360

2.2U_0603_10V7K

TBT@

2

C362

TBT@

GPIO8_CFG

PD_UART

TBT_MRESET

TBTA_DIG_AUD_P
TBTA_DIG_AUD_N

TBTA_DEBUG1
TBTA_DEBUG2

TBTA_ROSC

R340
15K_0402_1%

TBT@

4

+3VALW_PD

1

2

F1

D1
D2
C1

A5
B5
B6

B2

C2
D10
G11
C10
E10
G10

D7

H6

A3
B4
A4
B3

L5
K5

E2
F2

F4

G4

E11

L4
K4

L3
K3

L2
K2

J1
J2

F10

G2

R315 0_0402_5%@

22U_0603_6.3V6M

1

C351

2

TBTA_LDO_BMC
+1.8VD_TBTA_LDO
+1.8VA_TBTA_LDO

1

C361

2.2U_0603_10V7K

TBT@

2

10U_0402_6.3V6M

U39

I2C_ADDR
I2C_SDA1

I2C_SCL1
I2C_IRQ1_N

I2C_SDA2
I2C_SCL2
I2C_IRQ2_N

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SS_N

USB_RP_P
USB_RP_N

UART_TX
UART_RX

SWD_DATA
SWD_CLK

MRESET

TBT_LSTX/R2P
TBT_LSRX/P2R

DIG_AUD_P/DEBUG3
DIG_AUD_N/DEBUG4

DEBUG1
DEBUG2

AUX_P
AUX_N

BUSPOWER_N

R_OSC

TBT@

TBT_HRESET<38>

100K_0402_5%

1 2

+3VALW_PD+3VALW

1

2

+5VALW_PD +20V_HV_SYS

22U_0603_6.3V6M

22U_0603_6.3V6M
C352

TBT@

1

2

B1

H1

VDDIO

VIN_3V3

R418

TBT@

1

1

C354

C353

TBT@

TBT@

2

2

H10

A2

K1

E1

LDO_BMC

LDO_1V8A

LDO_1V8D

GND

GND

GND

GND

GND

GNDE5GND

GNDH4GND

F5

E7

A1

E6

D6

H5

G5

12

C348
.1U_0402_16V7K

TBT@

22U_0603_6.3V6M

TBT@

A11

B11

C11

PP_5V0

PP_5V0

PP_CABLE

GND

GNDF6GNDF7GND

GND

GND

E8

B8

D8

W=120mils

+5VALW +5VALW _PD

@

JUMP_43X79

4.7U_0805_50VAK

1

C355

@

2

0_0402_5%

12

R425

TBT@

D11

B7

B10

PP_HVA6PP_HVA7PP_HVA8PP_HV

PP_5V0

PP_5V0

F8

G6

GND

GNDG7GND

G8

GND

GNDH7GNDL1GND

H8

L11

SS

1

C367

0.22U_0402_16V7K

2

TBT@

SENSEP

J29

112

A10

SENSEN

VOUT_3V3

LDO_3V3

C_USB_TP

C_USB_TN

C_USB_BP
C_USB_BN

RPD_G1
RPD_G2

DEBUG_CTL1
DEBUG_CTL2

C_SBU1
C_SBU2

RESET_N

TPS65982_BGA96

2

12

C356
1U_0603_25V6K

TBT@

A9

HV_GATE1B9HV_GATE2

VBUS
VBUS
VBUS
VBUS

C_CC1
C_CC2

3

H11
J10
J11
K11

H2

G1

K6
L6

K7
L7

L9
L10

K9
K10

E4
D5

K8
L8

F11

TBT_A_USB20_PT
TBT_A_USB20_NT

TBT_A_USB20_PB
TBT_A_USB20_NB

TBTA_CC1
TBTA_CC2

RPD_G1
RPD_G2

DEBUG_CTL1
DEBUG_CTL2

1 2

R333 0_0402_5%@

1 2

R334 0_0402_5%@

1 2

R337 0_0402_5%@

2

3

SDM10U45-7_SOD523-2~D

D31

EMC@

2 1

1

+3.3V_TBT_SX_R

1

C363
1U_0402_6.3V6K

2

TBT@

C365 220P_0402_50V8J

C366 220P_0402_50V8J

1 2

R322 0_0402_5%@

1 2

R324 0_0402_5%@

1 2

R423 0_0402_5%TBT@

1 2

R424 0_0402_5%TBT@

1 2

0_0402_5%

USB3_A_TTX_C_DRX_P0<68>
USB3_A_TTX_C_DRX_N0<68>

TBT@

TBTA_CC1
TBT_A_USB20_PT

TBT_A_USB20_NT
TBTA_SBU1

TBT@

USB3_A_TRX_DTX_N1<68>
USB3_A_TRX_DTX_P1<68>

L30ESD24VC3-2_SOT23-3

D19

EMC@

+3.3V_FLASH

1

C364
10U_0603_6.3V6M

2

TBT@

TBT@

12

TBT@

12

TBTA_SBU1
TBTA_SBU2

R339

12
12

TBT@

TBT_RESET_N <68>

EC_TBTA_RESET <38>

R327 1 0K_0402_5%TBT@
R329 1 0K_0402_5%

TBT@

2

+TBTA_VBUS +TBTA_VBUS

JUSB1

A1

GND

A2

C3490.4 7U_0201_25V

12

C3570.4 7U_0201_25V

VBUS

A5

CC1

A6

DP1

A7

DN1

A8

RFU1

A9

VBUS

A10

SSRXN2

A11

SSRXP2

A12

GND

1

GND

2

GND

JAE_DX07S024JJ2

CONN@

USB3_A_TTX_C_DRX_P0

USB3_A_TTX_C_DRX_N0

USB3_A_TRX_DTX_P0

USB3_A_TRX_DTX_N0

USB3_A_TTX_C_DRX_P1

USB3_A_TTX_C_DRX_N1

USB3_A_TRX_DTX_P1

USB3_A_TRX_DTX_N1

+3.3V_FLASH

SSTXP1

A3

SSTXN1

A4

12

SSRXP1
SSRXN1

TOP

SSTXN2

Bottom

SSTXP2

1 2

D20
PESD5V0H1BSF SOD962

1 2

D21
PESD5V0H1BSF SOD962

1 2

D22
PESD5V0H1BSF SOD962

1 2

D24
PESD5V0H1BSF SOD962

1 2

D25
PESD5V0H1BSF SOD962

1 2

D26
PESD5V0H1BSF SOD962

1 2

D27
PESD5V0H1BSF SOD962

1 2

D29
PESD5V0H1BSF SOD962

VBUS
RFU2

VBUS

EMC@

EMC@

EMC@

EMC@

EMC@

EMC@

EMC@

EMC@

1

B12

GND

B11
B10

B9
B8
B7

DN2

B6

DP2

B5

CC2

B4
B3

B2
B1

GND

4

GND

3

GND

USB3_A_TRX_DTX_P0 <68>
USB3_A_TRX_DTX_N0 <68>

TBT@

TBTA_SBU2

TBT_A_USB20_NB
TBT_A_USB20_PB

TBTA_CC2

TBT@

USB3_A_TTX_C_DRX_N1 <68>
USB3_A_TTX_C_DRX_P1 <68>

12

C3500.47U_0201_25V

12

C3580.4 7U_0201_25V

TBTA_SBU1

+5VALW

TBT_A_USB20_NT

TBTA_SBU2

TBT_A_USB20_PB

6

I/O4

5

VDD

4

I/O3

AZC099-04SP.R7G_SOT23-6

SC300003S00

SC300003S00

AZC099-04SP.R7G_SOT23-6

1

I/O1

2

GND

3

I/O2

D28 EMC@

H36

H35

H_2P4X0P9

1

@

H38

H_2P4X0P9

1

@

D23EMC@

TBT_A_USB20_PT

3

I/O2

2

GND

TBTA_CC1

1

I/O1

TBT_A_USB20_NB

4

I/O3

VDD

I/O4

+5VALW

5

TBTA_CC2

6

H_2P4X0P9

1

@

H39

H_2P4X0P9

1

@

H37

H_2P4X0P9

1

@

H40

H_2P4X0P9

1

@

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROP ERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROP ERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROP ERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFORMATION. THIS SHE ET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SE CRET INFORMATION. THIS SHE ET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SE CRET INFORMATION. THIS SHE ET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIV ISION OF R&D
DEPARTMENT EXCEPT A S AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT A S AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT A S AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYB E USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC.

MAYB E USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAYB E USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PD+Type C

PD+Type C

PD+Type C

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

Date : She et o f

Date : She et o f

Date : She et o f

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

70

70

70

1.0

1.0

1.0

103Mon day, January 09, 2017

103Mon day, January 09, 2017

103Mon day, January 09, 2017

5

D D

C C

4

3

2

1

B B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

5

4

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Adaptor Proposal

Adaptor Proposal

Adaptor Proposal

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet o f

Date: Sheet o f

2

Date: Sheet o f

1

71 103Monday, January 09, 2017

71 103Monday, January 09, 2017

71 103Monday, January 09, 2017

1.0

1.0

1.0

5

PD105

RB751V-40_SOD323-2

ADAPDET1_L

1 2

JP101

@
9

GND_4

8

GND_3

7

GND_2

6

VGA_OneShot<41,53>

ACOK<38,75>

GND_1

FOX_JPD113D-DB570-7F

JP102

@

9

GND_4

8

GND_3

7

GND_2

6

GND_1

FOX_JPD113D-DB570-7F

VGA_OneShot

D D

C C

B B

A A

ACOK

DETECT

DC+_1
DC+_2

5
1
2
3

DC-_1

4

DC-_2

5

DETECT

1

DC+_1

2

DC+_2

3

DC-_1

4

DC-_2

PQ109A
2N7002KDW_SOT363-6

61

D

G

S

PQ108A
2N7002KDW_SOT363-6

61

D

G

S

PQ108B
2N7002KDW_SOT363-6

34

D

S

PQ109B
2N7002KDW_SOT363-6

34

D

S

ADAPDET2_L

2

2

5

G

5

G

1 2

RB751V-40_SOD323-2

1 2

PD102
1SS355_UMD2-2

2 1

2 1

PC120

EMI@

1000P_0603_50V8J

PD109

PC122

1 2

EMI@

PD103
1SS355_UMD2-2

12

12

1000P_0603_50V8J

0.22U_0402_25V6K

12

169K_0402_1%

common part(SM01000C000)

EMI@

5A_Z120_25M_0805_2P

ADAPDET1 <75>

EMI@

5A_Z120_25M_0805_2P

EMI@

5A_Z120_25M_0805_2P

EMI@

PC101

EMI@

100P_0603_50V8

5A_Z120_25M_0805_2P

EMI@

5A_Z120_25M_0805_2P

common part(SM01000C000)

5A_Z120_25M_0805_2P

ADAPDET2 <75>

5A_Z120_25M_0805_2P

5A_Z120_25M_0805_2P

PC103

EMI@

100P_0603_50V8

470K_0402_1%

PC109

PR124

0.22U_0402_25V6K

12

169K_0402_1%

PR116

12

PR117

470K_0402_1%

PC110

12

PR118

5A_Z120_25M_0805_2P

5A_Z120_25M_0805_2P

12

LM393DR_SO8

12

PL101

1 2

PL102

1 2

PL103

1 2

PL104

1 2

PL109

1 2

EMI@

1 2

EMI@

1 2

EMI@

1 2

EMI@

1 2

EMI@

1 2

1

PU102A

PL105

PL106

PL107

PL108

PL110

+19V_ref

12

PR149

8

P

O

G

4

PU102B

LM393DR_SO8

7

4

+19V_VIN1+19V_ADPIN1

12

PC121

1 2

PC102

EMI@

EMI@

1000P_0603_50V8J

1000P_0603_50V8J

+19V_VIN2+19V_ADPIN2

12

PC123

EMI@

1000P_0603_50V8J

AC_IN1

PC111

100P_0402_50V8J

AC_IN2

PC104

EMI@

1000P_0603_50V8J

+5VS

12

PR119

150K_0402_1%

12

12

PR120

100K_0402_1%

1 2

0_0402_5%

3

+

1 2

2

-

PR111

0_0402_5%

8

5

P

+

O

6

1 2

-

G

PR103

0_0402_5%

4

3

AC_off1<38>

AC_IN1<38,73>

PR127

392K_0402_1%

2N7002KDW_SOT363-6

PR129

+19V_VIN2

12

PQ107A

12

105K_0402_1%

PR136

392K_0402_1%

PR138

105K_0402_1%

2

G

ADAPDET1

12

12

1 2

+19V_VIN1+19V_VIN1

PR128

200K_0402_1%

PQ107B

2N7002KDW_SOT363-6

61

D

S

AC_off2<38>

AC_IN2<38,73>

+19V_VIN2

61

D

2

G

S

ADAPDET2

PR152
0_0402_5%

12

5

PR137

200K_0402_1%

PQ110A

2N7002KDW_SOT363-6

2

LM393DG_SO8

12

PR147

47.5K_0402_1%

2.2_0402_1%

12

1

PU101A

LM393DG_SO8

PR145

PC118

1U_0805_25V4Z

1M_0402_1%

1 2

PR132

+19V_ref

12

PR148

0_0402_5%

19V_ref

8

3

P

+

O

2

-

G

4

PR105

1M_0402_1%

1 2

19V_ref

8

P

+

7

O

-

G

PU101B

4

+19V_VIN2 +19V_VIN1

3

2

1

+19V_ref

12

PR133

22K_0402_1%

1 2

12

PC115

1000P_0402_50V7K

1 2

PR135
10K_0402_1%

PR107

22K_0402_1%

5

1 2

6

PR109
10K_0402_1%

1 2

BAT54CW-7-F SOT-323
PD107

+19V_VIN1

12

12

12

PC105

1000P_0402_50V7K

+3Vref

+19V_VIN1

12

12

PR146

PR130

10K_0402_5%

@

47.5K_0402_1%

12

PR106

10K_0402_1%

PQ110B

2N7002KDW_SOT363-6

G920AT24U_SOT89-3
PU103

3

OUT

GND

4.7U_0805_10V4Z

1

12

@

GLZ4.3B_LL34-2

+3Vref

12

IN

12

12

2

PD104

PR104

@

+19V_VIN2

10K_0402_5%

PD101

@

GLZ4.3B_LL34-2

PR131

10K_0402_1%

34

D

G

S

PR153
0_0402_5%

1 2

12

34

D

5

G

S

+3Vref

12

PC117

PR134

84.5K_0402_1%

12

PR139

18.7K_0402_1%

+3Vref

+19V_VIN2

12

PR108

84.5K_0402_1%

12

PR110

18.7K_0402_1%

1

PC116

1000P_0402_50V7K

12

+3Vref

N123084208 <73>

PC106
1000P_0402_50V7K

+CHGRTC

PR102

1 2

0_0603_5%

5

+3VLP

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

2017/12/312016/02/01

2017/12/312016/02/01

2017/12/312016/02/01

Title

PWR DCIN / RTC battery

PWR DCIN / RTC battery

PWR DCIN / RTC battery

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

SKL_H 42

Monday, January 09, 2017

Monday, January 09, 2017

Monday, January 09, 2017

1

1.0

1.0

1.0

10372

10372

10372

5

PQ102

@

AON6403_DFN5X6-8-5

1
2
35

4

AC_IN1

AC_IN2

PR126

0_0402_5%

1 2

AC_IN1

PR125

100K_0402_5 %

1 2

PQ101
AON6403_DFN5X6-8-5

4

PR114

0_0402_5%

1 2

PQ104
AON6403_DFN5X6-8-5

4

12

PC124

@

0.1U_0402_25V6

5

G

1
2
35

12

1
2
35

2

G

34

D

PQ105B

2N7002KDW_SO T363-6

S

+19V_VIN1

D D

C C

+19V_VIN2

B B

@

PR113

2

G

12

12

PC107

0.1U_0603_25V7K

12

226K_0402_1%

13

D

S

PC108

@

0.1U_0603_25V7K

PR115

226K_0402_1%

S

PR112

200K_0402_1%

PQ106

L2N7002WT1G 1N SC-70-3

AON6403_DFN5X6-8-5

1
2
3 5

12

PR101

200K_0402_1%

12

61

D

PQ105A

2N7002KDW_SO T363-6

SW1

PQ117

LMUN5113T1G_SOT323 -3

1 3

112

JUMP_43X118

112

JUMP_43X118

PQ116

4

2

PQ118A
2N7002KDW_SO T363-6

61

D

S

PJ101@

2

PJ102@

2

+19V_VIN

PU104B

LM358DT_SO8

8

5

PR160

@

P

+

7

0

6

-

G

4

2

1

0

G

PC119

2200P_0402_ 50V7K

1 2

PC125

0.47U_0402_25V 6K

1 2

1 2

SW2

+19V_VIN

0_0402_5%

1 2

8

P

+

-

G

4

PR158

4.7K_0402_1%

1 2

PR159
20K_0402_1%

PU104A
LM358DT_SO8

3
2

PR154

1 2

100K_0402_1%

100K_0402_1 %

1 2

34

D

5

G

S

PC126

1U_0402_16V

1 2

PR155

N123084208 <72 >

PQ118B

2N7002KDW_SOT363-6

4

PR156

1 2

100K_0402_1%

12

PC127

PR157

1 2

100K_0402_1%

0.047U_0402_25V7K

ACIN1=1 ACIN1=0

ACIN2=1

ACIN2=0

SW1→ ON
SW2→ OFF
SW3→ ON
SW4→ OFF

SW1→ ON
SW2→ OFF
SW3→ OFF
SW4→ ON

SW1→ OFF
SW2→ ON
SW3→ OFF
SW4→ ON

SW1→ OFF
SW2→ OFF
SW3→ OFF
SW4→ ON

3

SW3

+19V_VIN2

8
7

5

PQ113

AO4423L_SO8

AC_IN1<38,72>

AC_IN2<38,72>

1
2
36

4

12

1
2
3 6

12

PR141

PC113

@

200K_0402_1%

0.1U_0603_25V7K

12

PR142

226K_0402_1%

PR143

0_0402_5%

2

1 2

G

PR144

0_0402_5%

5

1 2

G

PQ114

AO4423L_SO8

4

8
7

5

1 2

PC114

@

5600P_0402_ 25V7K

61

D

PQ115A
2N7002KDW_SO T363-6

S

34

D

PQ115B
2N7002KDW_SO T363-6

S

2

1

+GPU2_IN

SW4

PQ111

AON6403_DFN5X6-8-5

1

+GPU2_IN

2N7002KW_SOT 323-3

2
3 5

DISCHG_G

PR121

200K_0402_1 %

1 2

12

PR122
47K_0402_1%

13

D

2

PQ112

G

S

4

12

12

PC112

0.1U_0603_25V7K

B+

PR123
200K_0402_1 %

61

D

S

34

D

S

PJ103@

112

JUMP_43X118

PQ103A
2N7002KDW_SO T363-6

2

1 2

G

PR150

0_0402_5%

PQ103B
2N7002KDW_SO T363-6

1 2

5

G

PR151

0_0402_5%

2

B+

AC_IN1

AC_IN2

A A

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

5

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

2017/12/312016/02/01

2017/12/312016/02/01

2017/12/312016/02/01

Title

PWR DCIN / RTC battery

PWR DCIN / RTC battery

PWR DCIN / RTC battery

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

Date: Sheet o f

Monday, January 09, 2017

Date: Sheet o f

Monday, January 09, 2017

Date: Sheet o f

Monday, January 09, 2017

1

1.0

1.0

1.0

10373

10373

10373

5

4

3

2

1

+3VLP_ECA

PR201 100_0402_1%

1 2

PR202 100_0402_1%

D D

PJ201

@

1

1

2

2

3

3

EC_SMB_DA1-1

4

4

EC_SMB_CK1-1

5

5

BATT_TS

6

6

BATT_B/I

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_50458-01001-P01

C C

+V_BATT+

12

1 2

PL201

EMI@

5A_Z120_25M_0805_2P

1 2

PL202

EMI@

5A_Z120_25M_0805_2P

1 2

PL203

EMI@

5A_Z120_25M_0805_2P

1 2

PC201

EMI@

1000P_0603_50V8J

PR203

200K_0402_5%

1 2

1 2

PR205 1K_0402_1%

12

+3VLP

BI_GATE<40>

+BATT+

PC203

EMI@

0.01U_0603_25V7K

BATT_TEMP <38,75>

COMPOUT<75>

+RTCVCC

2

G

EC_SMB_DA1 <38,75>
EC_SMB_CK1 <38,75>

12

PR207
422K_0402_1%

2

G

13

D

PQ202

S

@

BSS138LT1G_SOT23-3

ADP_I<38,75>

12

PR204

16.5K_0402_1%

PR206

137K_0402_1%

VCIN1_ADP_PROCHOT<38>

13

D

PQ201

S

BSS138LT1G_SOT23-3

12

PR214

@

0_0402_5%

BI_S <40>

PR208

95.3K_0402_1%

VCIN0_PH<38>

1 2

PC202 must close to EC pin

12

PH201100K_0402_1%_TSM0B104F4251RZ

PT01PAD @

1 2

PAD

PT02

@

PC202

@

0.022U_0402_16V7K

1 2

ECAGND <38>

---Battery_pin define--­PIN1 GND
PIN2 GND
PIN3 GND
PIN4 SMD
PIN5 SMC
PIN6 TS
PIN7 B/I
PIN8 BATT+
PIN9 BATT+

MAINPWON<38,40,76>

PIN10 BATT+

MAINPWON

PR210

100K_0402_1%

12

B B

A A

---Battery Con_pin define--­PIN10 Batt+
PIN9 Batt+
PIN8 Batt+
PIN7 B/I
PIN6 TS
PIN5 SMC
PIN4 SMD
PIN3 GND
PIN2 GND
PIN1 GND

12

PC204

0.1U_0603_25V7K

PU201

1

VCC

TMSNS1

2

GND

RHYST1

3

OT1

TMSNS2

4

RHYST2

OT2

G718TM1U_SOT23-8

33K_0402_1%

PR211

8
7
6
5

PR213

18.7K_0402_1%

12

G718_TMSNS1
G718_RHYST1
G718_TMSNS2

PR212

18.7K_0402_1%

12

12

PH203

@

100K_0402_1%_NCP15WF104F03RC

12

+3VLP

12

PR209

33K_0402_1%

(Common Part)
SL200002H00

12

PH202

@

100K_0402_1%_NCP15WF104F03RC

close fan1

For KB9022
OTP

Active Recovery

VCIN0_PH(V)

26.11K7.3KPH201(ohm)

PH201 under CPU botten side :
CPU thermal protection at 92 degree C ( shutdown )

Recovery at 56 degree C

For KB9022
sense 5mΩ

330W
PR208=95.3K ohm

Active Recovery

1V(462W)

1V(462W)56C, 2V92C, 1V

close fan2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

5

4

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Title

Title

Title

PWR-BATTERY CONN/OTP

PWR-BATTERY CONN/OTP

PWR-BATTERY CONN/OTP

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

SKL_H 42

Date: Sheet o f

Date: Sheet o f

2

Date: Sheet o f

1

74 103Monday, January 09, 2017

74 103Monday, January 09, 2017

74 103Monday, January 09, 2017

1.0

1.0

1.0

5

13

D

S

+19V_VIN

D D

PC301

1000P_0402_ 50V7K

1 2

C C

1 2

PC303

1000P_0402_ 50V7K

PQ301
EMB04N03H_EDFN5X6-8-5

5

PQ304
EMB04N03H_EDFN5X6-8-5

5

ACFET_GATE_1

4

ACFET_GATE_2

12

4

12

PR301

4.7_0402_5%

4.7_0402_5%
PR305

+19V_P1

1
2
3

1
2
3

12

12

+6V_CHG_REGN

+19V_VIN

PR334

100K_0402_1 %

1 2

2

PQ311

G

12

PR335

49.9K_0402_1%

2

G

12

PR336

49.9K_0402_1%

2

G

ACDET_CHG

2

13

D

S

2N7002KW_SOT 323-3

12

1 2
13

B B

ADAPDET1<72>

ADAPDET2<72>

ADPI = 0.005*40*IADP = 0.2 * IADP
Adapter =330W

CP = 330W/19V*0.9 = 15.63A
ADPI = 3.12V
Hybrid trigger = CP*107% = 16.72A
ADPI = 3.34V
PROCHOT = 330W/19V*110% = 19.1A
ADPI = 3.82V

A A

For 4S per cell 4.35V battery

BATT_4S<38>

SUSP#<25,26,2 8,32,38,68,77,79,80>

PQ302
L2N7002WT1G 1 N SC-70-3

Inverse_GATE

2

G

PR302

3M_0402_5%

1
2
3

PC302

0.1U_0402_25V6

12

PR310

4.12K_0603_1%

ACOK<38,72>

13

D

PQ312

S

BSS138LT1G_SOT23-3

13

D

S

PQ313

BSS138LT1G_SOT23-3

PR332

2M_0402_1%

PR333
0_0402_5%

PQ310
LTC015EUBFS8TL _UMT3F

4

PR303

1M_0402_1%

12

PQ303
EMB04N03H_EDFN5X6-8-5

4

PQ305
EMB04N03H_EDFN5X6-8-5

1
2
3

4

RBFET_GATE

PR311

4.12K_0603_1%

PR319

1 2

100K_0402_1 %

13

D

PQ314

S

@

BSS138LT1G_SOT23-3

12

5

5

0.1U_0603_25V7 K

12

2

G

PR320

PC313

1 2

120K_0402_5%

PR325

49.9K_0402_1%

COMPOUT

+19V_P2

+19V_VIN

12

common part(SD00000K820)

PR337

0.01_1206_1%

134
2

PR304

0.01_1206_1%

134
2

0_0402_5%

PC314

1 2

ADP_I<38,74>

AC Det
Max:18.16V
Typ :17 .98V
Min :17.8V

PC325

0.01UF_0402_25 V7K

ACN

12

PR307

0_0402_5%

PC315

0.01UF_0402_25 V7K

1 2

ACN_CHG

ACDET_CHG

1 2

PR322
0_0402_5%

+19V_VIN

ACP

12

PR306

0.1U_0402_25V6

ACP_CHG

12

PR321

324K_0402_1%

12

Iada=0~17.36A(33 0W)

ADP_I = 40*Iadapter*Rsense

PD106

BAT54CW-7-F SOT -323

2

3

B+

1 2

PC316

1U_0603_25V6K

PU301

29

PWPD

1

ACN

2

ACP

CMSRC_CHG

3

CMSRC

ACDRV_CHG

4

ACDRV

5

ACOK

6

ACDET

ADPI_CHGR

7

IADP

PC324

1 2

100P_0402_50V8J

IDCHG_CHGR

1 2

PC326
100P_0402_5 0V8J

0.047U_0402_25V7K

1

VCC_CHGR_R

12

PR312

10_1206_1%

VCC_CHGR

LX_CHG

28

27

VCC

BQ24780SRUYR_QFN28 _4X4

IDCHG8PROCHOT#10SCL

PR328

0_0402_5%

@

1 2

<81>

<9,38>

psys_MON

PC304

1 2

BST_CHGR_R

1 2

12

PR313

2.2_0603_5%

BTST_CHG

DH_CHG

24

26

25

BTST

REGN

HIDRV

PHASE

PMON9SDA11CMPIN

12

PROCHOT#_CHGR

EC_SMB_DA1_CHGR

EC_SMB_CK1_CHGR

PR3290_0402_5%

PR331

1 2

1 2

1 2

PR330 0_0402_5%

EC_SMB_CK1

EC_SMB_DA1

H_PROCHOT#

B+

PC310

2.2U_0603_16V6K

+6V_CHG_REGN

DL_CHG

23

22

LODRV

14

13

0_0402_5%

DDR_ALERT

<38,74>

3

@EMI@

5A Z120 25M 0805

1 2

@

JUMP_43X79

GND

SRP

SRN

BATDRV

BATSRC

TB_STAT#

BATPRES#

CMPOUT

COMPOUT

<38,74>

2

PQ306 AON6426_DFN5X6-8-5

1
2

5

PL301

PC321

1 2

4

BATFET_GATE

12

BATDRV_CHG

134
2

134

SRP

2

0.1U_0402_25V6

3

PC305

1 2

0.022U_0603_25 V7K
PR308

10K_0402_1%

PR317

0.01_1206_1%

PR338

0.01_1206_1%

PC322

1 2

common part
(SD00000K820)

SRN

PC323

0.1U_0402_25V6

1 2

PL302

PJ301

2

112

+3VLP

21

ILIM

SRP_CHG

20

SRN_CHG

19

BATDRV_CHG

18

BATSRC_CHG

17

TB_STAT#_CHG

16

15

<74>

<38,77>

PC306

@EMI@

TB_STAT#_CHG : LOW
Hybrid discharge= 0.2V = 8A
TB_STAT#_CHG : High

12

Charger limit = 0.3V = 3A

PR315
715K_0402_1 %

PR314

392K_0402_1%

PQ308

1 2

13

D

L2N7002WT1G 1 N SC-70-3

TB_STAT#_CHG

2

G

S

1 2

PR316

25.5K_0402_1 %

12

PR323
10K_0402_1%

BATPRES#_CHGR

+3VALW

PR326
0_0402_5%

1 2

BATT_TEMP

12

12

PC308

PC312

1U_0402_25V6K

0.1U_0402_25V6

@EMI@

<38,74>

CHG_B+

12

12

PC309

10U_0805_25V6K

10U_0805_25V6K

PQ307

common part

PR324
10_0402_1%

1 2

PR327
10_0402_1%

1 2

3 5

241

PQ309

3 5

241

(SH00000YC00)

7x7x3

5.5A
40mohm

AON7506_DFN33-8-5

4.7UH_5.5A_20%_7X7 X3_M

1 2

12

PR318

4.7_1206_5%

EMI@

SNUB_CHG

12

PC318
680P_0402_5 0V7K

EMI@

AON7506_DFN33-8-5

0.1U_0402_25V6

DH_CHG

LX_CHG

DL_CHG

+BATT_CHG

12

PR309
10_0402_1%

BATSRC_CHG

+BATT+

12

12

12

PC319

PC317

PC320

10U_0805_25V5K~D

10U_0805_25V5K~D

10U_0805_25V5K~D

1

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADESECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

5

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS,INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PWR_CHARGER

PWR_CHARGER

PWR_CHARGER

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C1PRG LA-E051P

C1PRG LA-E051P

C1PRG LA-E051P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

75 103Monday, January 09, 2017

75 103Monday, January 09, 2017

75 103Monday, January 09, 2017

1.0

1.0

1.0

5

Input Current: 7.5A

3.3V*10A/0.85/12V=2.23

D D

5V*10A/0.85/12V=5.27

4

3

PR410

6.49K_0402_1%

1 2

PR403

10K_0402_1%

1 2

VFB=2V

+3VLP

PC413

4.7U_0603_6.3V6K

1 2

VFB=2V

PR402

16K_0402_1%

1 2

PR404

10K_0402_1%

1 2

2

Output capacitor ESR need follow
below equation to make sure feed back
loop stability
ESR=20mV*L*fsw/2V

1

12

PL403

@EMI@

5A Z120 25M 0805

B+

1 2

PJ401

@

2

112

JUMP_43X118

C C

+3VALWP

3.3VALWP
TDC=8.26A
Peak Current 11.8A
OCP current 14.16A (Pr405=100k)
FSW=355kHz

B B

H/S Rds(on) : 11.2mohm 14mohm
L/S Rds(on) : 6.7mohm 8.5mohm

RT8243A_B+

12

12

PC401

PC402

0.1U_0402_25V6

10U_0805_25V6K

EMI@

TYP MAX

12

PC403

EMI@

2200P_0402_50V7K

10X10X4
Isat:14A
DCR: 16.5mΩ (Max)

PL401

4.7UH_MMD-10DZ-4R7M-X2_9.5A_20%

1 2

1

+

PC407

2

330U_6.3V_ESR17M_6.3X6

PQ401

AON7518_DFN8-5

123

LX_3V

12

PR411

PQ403

4.7_1206_5%

@EMI@

12

AON7534_DFN3X3-8-5

PC411

680P_0603_50V8J

@EMI@

POK need pull high, it
will pull high on VS
transfer circuit

5

4

3 5

241

SPOK<38>

0.1U_0402_25V6

+3VALW

PC405

1 2

100K_0402_5%

1 2

0_0603_5%

1 2

3V_EN<38>

PR401

PR408

LX_3V

UG_3V

LG_3V

BST_3V

RT8243A_B+

PR405

100K_0402_1%

CS2

5

CS2

6

EN2

7

PGOOD

8

TPS51225CRUKR_QFN20_3X3

SW2

9

VBST2

10

DRVH2

DRVL211VIN12VREG513VO114DRVL1

OVP=Vout*(112.5%~117.5%)
OCP=Vtrip/Rdson+Iripple/2

Vtrip=Ics(min)*Rcs/8+1mV
Vcs=Ics*Rcs should be in the range of 0.2~2V
Ics=9~11uA

Vout=VFB*(1+Rtop/Rbot)
VFB=2V

FB_3V

4

VFB2

PU401

FB_5V

3

2

VREG3

VL

12

PC415

4.7U_0603_6.3V6K

12

PR407

97.6K_0402_1%

CS1

1

21

CS1

PAD

VFB1

EN1

VCLK

SW1

VBST1

DRVH1

15

5V_EN

20

@

200_0402_1%

19

1 2

LX_5V

18

BST_5V

17

UG_5V

16

+5VALWP

PR479

PR409

0_0603_5%

1 2

LG_5V

RT8243A_B+

12

PC404

10U_0805_25V6K

PC406

0.1U_0402_25V6

1 2

PJP404

112

PJP405

112

12

12

PC417

PC418

10U_0805_25V6K

2

@JUMP_43X118

2

@JUMP_43X118

5

10U_0805_25V6K

4

3 5

241

PQ402

13X13X6
I

AON7518_DFN8-5

123

PQ404

AON7534_DFN3X3-8-5

5VALWP
TDC=15.75A
Peak Current 22.5A
OCP current 27A (Pr407=97.6k)
FSW=300kHz

H/S Rds(on) : 11.2mohm 14mohm
L/S Rds(on) : 6.7mohm 8.5mohm

+5VALW+5VALWP +3VALW+3VALWP

sat:28A

DCR: 8.4mΩ (Max)

PL402

4.7UH_MMD-12FDN4R7M-M1L_15A_20%

LX_5V

1 2

12

PQ405

12

AON7534_DFN3X3-8-5

3 5

241

TYP MAX

PR412

4.7_1206_5%

@EMI@

PC414

ESR = 14mohm

680P_0603_50V8J

@EMI@

PJP402

112

PJP403

112

1

1

+

+

PC409

PC410

2

2

330U_6.3V_ESR17M_6.3X6

330U_6.3V_ESR17M_6.3X6

2

@JUMP_43X118

2

@JUMP_43X118

+5VALWP

EC_ON<38>

MAINPWON<38,40,74>

A A

1 2

PR474

0_0402_5%

1 2

1/19
PR416 402K change to 1M

5

12

12

PR475

1M_0402_1%

PC457

4.7U_0603_10V6K

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

PWR_3V & 5VALWP

PWR_3V & 5VALWP

PWR_3V & 5VALWP

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C

C

C

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

76 103Monday, January 09, 2017

76 103Monday, January 09, 2017

76 103Monday, January 09, 2017

1.0

1.0

1.0

5V_EN

PR476

2.2K_0402_5%

5

4

3

2

1

PR502

DL_DDR

CS_DDR

VDD_DDR

12

PC513
1U_0402_10V6K

B+_DDR

PR501

0_0603_5%

1 2

15

14

13

12

11

PR508
432K_0402_1%

1 2

PR509

@

0_0402_5%

1 2

PR511

0_0402_5%

1 2

PR512

0_0402_5%

1 2

1 2

PR513

@

0_0402_5%

DH_DDR

LX_DDR

16

17

PHASE

UGATE

LGATE

PGND

PU501

CS

RT8207PGQW_WQFN20_3X3

VDDP

VDD

PGOOD

TON

9

10

TON_DDR

PC515

@

+1.2VP

+1.2VP

PJ501

19

PG

7

LX_DDR_L

LX20LX

LX

6

LX_DDR_L

JUMP_43X118

JUMP_43X118

LX_DDR

2

1

PAD

BS

IN

IN

IN

IN

@

112

PJ502

@

112

JUMP_43X118

Pj507

@

2

JUMP_43X39

1

0.1U_0603_25V7K

21
1

2

3

4

5

2

2

@

112

@

1 2

PJ503

PC509

2

1 2

12

PC527

@

10U_0805_25V6K

+1.2V_VDDQ

+0.6VS_VTT

PR524

@

0_0603_5%

@EMI@

5A Z120 25M 0805

1 2

12

PC528

@

10U_0805_25V6K

PL2412

B+_DDR

+0.6VSP

12

BST_DDR

18

19

20

21

VTT

PAD

BOOT

S5

8

7

S3_DDR

S5_DDR

12

0.1U_0402_10V7K

12

VLDOIN

S3

VTTGND

VTTSNS

VTTREF

FB

6

FB_DDR

12

PC516

@

0.1U_0402_10V7K

GND

VDDQ

PR507

6.04K_0402_1%

1 2

FB=0 .75 V

PR510
10K_0402_1%

1

2

3

VTTREF_DDRTVDDP_DDR

4

5

Vo=0.75V x[1+(6.04K/10K)]=1.203V

Vo=0.75V x[1+(6.04K/7.5K)]=1.354V for OC

12

PR520

@

30K_0402_1%

13

D

2

G

S

PQ503

@

BSS138LT1G_SOT23-3

+1.2VP

+0.6VSP

12

PC526

@

22U_0603_6.3V6M

12

+1.2VP

+1.2VP

PC2474

@

330P_0402_25V8J

1 2

PR522

@

100K_0402_1%

1 2

PC505

10U_0603_6.3V6M

DRAM_OC <22>

Pj508

@

JUMP_43X39

112

PC506

10U_0603_6.3V6M

+1.2VP

+0.6VSP

12

PC514

0.033U_0402_16V7K

+3VALW

PR525

@

16

FB

VDDQ

VTT

VTTSNS

VTTREF

10

S3_DDR

0_0402_5%

1 2

PC507

@

1U_0402_10V6K

1 2

18

17

GND

BIAS

ALERT

PU503

@

SY8310RAC_QFN20_3X3

GND

S3

S5

8

9

S5_DDR

DDR_ALERT<38,75>

+3VS

2

PR523

@

1 2

100K_0402_1%

12

PR521

@

100K_0402_1%

FB2_DDR

15

14

13

12

12

PC524

11

@

12

22U_0603_6.3V6M

PC525

@

1U_0402_16V6K

RILIM

PC502

0.1U_0603_25V7K

1 2

PR504

7.5K_0402_1%

1 2

1 2

PR505

5.1_0603_5%

12

PC512
1U_0402_10V6K

PM_SLP_S4#<20,26,38>

SYSON<25,26,38,78>

SM_PG_CTRL<9>

SUSP#<25,26,28,32,38,68,75,79,80>

BST_DDR-1

0_0402_5%

1 2

PL502

@EMI@

5A Z120 25M 0805

1 2

B+

PJ506

@

2

112

D D

JUMP_43X118

+1.2VP

12

12

PC2467

@

22U_0603_6.3V6M

C C

12

12

PC2470

PC2469

PC2468

@

@

@

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

STATE

S

S3

S4/S5

B B

MOSFET: 3x3 DFN
H/S Rds(on):23.2mohm(Typ), 27.8mohm(Max)
Idsm: 10.1A@Ta=25C, 8.1A@Ta=70C

MOSFET: 5x6 DFN
L/S Rds(on): 4.2mohm(Typ), 5mohm(Max)
Idsm: 36.1A@Ta=25C

Choke: 10x10x4
Rdc=2.35mohm(Typ),

Switching Frequency: 585kHz
Ipeak=11.5A
Iocp=13.8A
OVP: 113%~120%
VFB=0.75V, Vout=1.2V

OCP: Ilimit + Iripple/2
RILIM=ILIMITxRDSon/10uA

B+_DDR

12

12

PC501

PC503

2200P_0402_50V7K

4.7U_0805_25V6-K

@EMI@

7X7X4
Isat:15A
DCR: 7.4mΩ (Max)

12

12

PC2472

PC2471

@

@

22U_0603_6.3V6M

22U_0603_6.3V6M

S3 S5 VDDQ VTT

0

Hi

Hi

Lo

Hi

Lo

Lo

12

PC504

4.7U_0805_25V6-K

1UH_11A_20%_7X7X3_M

1

+

PC510

2

560U_2.5V_M

ON ON

ON OFF

OFF OFF

12

PC517

4.7U_0805_25V6-K

MDV1528URH_PDFN33-8-5

PL501

1 2

PR503

@EMI@

4.7_1206_5%

PC511

@EMI@

680P_0603_50V7K

SNB_DDR

PQ501

12

12

5

4

123

5

PQ502
MDU1512RH_POW ERDFN56-8-5

4

+5VALW

123

+5VALW

1 2

PR506

5.1_0603_5%

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

DDR RT8207P

DDR RT8207P

DDR RT8207P

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C

C

C

SKL_H 42

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

77 103Monday, January 09, 2017

77 103Monday, January 09, 2017

77 103Monday, January 09, 2017

1.0

1.0

1.0

5

D D

+3VALW

C C

EMI@

PL2404

5A_Z120_25M_0805_2P

+5VALW

B B

FAN_EN<38>

1 2

PR2434

100K_0402_5%

1 2

1 2

PR2438

10K_0402_5%

12

100K_0402_5%

AON7403L_DFN8-5

1
3

PC2424

0.01U_0402_16V7K

PR2433

10K_0402_5%

2

G

PR2436

PQ2413

PQ2412

EN_+12VSP

1 2

@EMI@

5A Z120 25M 0805

@

JUMP_43X79

4

1 2

VIN_12VSP_ON#_R

13

D

2N7002KW_SOT323-3

S

12

0.1U_0402_10V7K

PL504

1 2

PJ504

112

22U_0603_6.3V6M

52

12

0.022U_0402_25V7K

PC2432

2

VIN_2.5VP

PC518

PC2431

EMI@

0.01U_0402_25V7K

5.9K_0402_1%

4

EN_2.5VP

12

PU502

1
2
3

12

4

SY8003ADFC DFN 8P

SA00007QP00

FB
PG
IN
PGND

PGND
SGND

9
8

7

EN

LX_2.5VP

6

LX

5

NC

FB=0.6V

PC523

0.1U_0402_16V7K

PL503

1UH_PH041H-1R0MS_3.8A_20%

1 2

SH00000YG00

12

SNUB_2.5VP

12

PR517

PR516

42.2K_0402_1%

4.7_0603_5%

@EMI@

FB_2.5VP

PR518

13.3K_0402_1%

PC522

Vout=0.6V* (1+Rup/Rdown)

@EMI@

680P_0402_50V7K

2.503V= 0.6V*(1+42.2K/13.3K)

3

PR515

180K_0402_1%

1 2

12

PR514

1M_0402_5%

4x4xH1.8
DCR(max): 32.4mohm
Idc / Isat: 4A

12

12

Rup

PC519

68P_0402_50V8J

12

Rdown

2

syson <25,26,38,77>

+2.5VP

22U_0603_6.3V6M

22U_0603_6.3V6M

@

TDC : 0.84A

PC521

PC520

12

12

I

ocp : 1.44A

FSW : 1MHz

@

PJ505

2

+2.5VP +2.5V

112

JUMP_43X79

1

OVP=2.5V*105%=2.625V

7X7X1.8
Isat:13A
DCR: 35mΩ (Max)

PC2427
1U_0402_16V6K

VDC_+12VSP

COMP_+12VSP

SS_+12VSP

FSW_+12VSP
FAULT_+12VSP

12

PR2437
100K_0402_5%

PL2405

1 2

PU2403

1

VDC

2

VIN

3

COMP

4

SS

5

FSW
FAULT6FB

RT8525DGQW_WDFN12_3X3

LX_12VP

EN
DRV
GND

ISW

OVP

TP

12

12

12
11
10
9
8
7
13

PR2443

1_0805_1%

@EMI@

PC2437

@EMI@

680P_0402_50V7K

EN_+12VSP
DRV_+12VSP

ISW_+12VSP
OVP_+12VSP
FB_+12VSP

PR2444

1 2

4.7K_0402_1%

5

4

12

+5VALWin

PC2421

PR2439

PC2429

12

12

PC2425

PC2422

22U_1206_16V6-M

12

12

12

22U_1206_16V6-M

PC2430

1U_0402_16V6K

PC2426

12

PC2428

12

100P_0402_50V8J

0.47U_0402_25V6K

22U_1206_16V6-M

12

2.2UH +-20% MMD-06AH-2R2M-X2A 6A

12

12

PR2435

19.6K_0402_1%

VDC_+12VSP

PD902

SX34F_SMAF2

PQ2414

MDV1526URH

123

PR2440

0.02_1206_1%

12

OVP_+12VSP FB_+12VSP

12

PR2445

1.4K_0402_1%

12

PR2447

1 2

12

1 2

PR2442

6.65K_0402_1%

PR2446

110K_0402_1%

12

PR2441

12.7K_0402_1%

280K_0402_1%

PC2436

1000P_0402_25V-J

13

D

2

G

S

PQ2411

L2N7002WT1G 1N SC-70-3

3A Current Limit DC/DC boost Converter

22U_1206_16V6-M

12

PC2439

FAN_9V : Low
Vout=1.25V*(1+110k/12.7k)=12.07V
OVP=2.5*(1+6.65k/1.4k)=14.37V

FAN_9V : Hi
Vout=1.25V*(1+78.9k/12.7k)=9.015V

FAN_9V <38>

22U_1206_16V6-M

22U_1206_16V6-M

PC2438

PC2475

12

12

+12VS

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

2.5V / FAN 12V

2.5V / FAN 12V

2.5V / FAN 12V

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C

C

C

SKL_H 42

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

78 103Monday, January 09, 2017

78 103Monday, January 09, 2017

78 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

D D

B+

LDO_3V_1VALW

12

PR603

@

0_0402_5%

ILMT_1VALW

12

PR605

@

0_0402_5%

The current limit is set to 8A ,12A ,16A, when this pin
is pull low, floating or pull high

C C

B B

A A

B+_FUSE

JUMP_43X79

@EMI@

5A Z120 25M 0805

1 2

The current limit is set to 7.5A ,10.5A ,13.5A, when this pin
is pull low, floating or pull high

@

PJ2201

112

PL2411

5A Z120 25M 0805

2

susp#<25,26,28,32,38,68,75,77,80>

LDO_3V_1.8VSP

EN pin don't floating

PJ601

@

2

112

JUMP_43X79

PL602

@EMI@

1 2

12

PC2202

PC2201

0.1U_0402_25V6

2200P_0402_50V7K

@EMI@

@EMI@

PR2207
0_0402_5%

1 2

PR2208
0_0402_5%

1 2

PC603

EMI@

2200P_0402_50V7K

B+_+1.8VSP

12

@

+1VALW_B+

12

PC604

0.1U_0402_25V6

@EMI@

PR609
1M_0402_1%

PR2203

0_0402_5%

1M_0402_1%

+3VALW

12

1 2

PC2204

EN_+1.8VSP

12

PR2205

10U_0805_25V6K

PC605

10U_0805_25V6K

EN_1VALW

12

12

12

EN_1VALW
ILMT_1VALW

+1VALW_B+

+3VALW

12

@

0.22U_0402_10V6K

12

PC2211

@

PC614

0.1U_0402_16V7K

12

PR608

10K_0402_1%

1 2

ILMT_+1.8VSP

PU601

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND

18

GND

11

EN

13

ILMT

15

BYP

SY8288RAC_QFN20_3X3

PC613
1U_0402_6.3V6K

2
3
4
5
7

8
18
11
13
15

12

PC2213

1U_0603_16V7

PU2201

IN
IN
IN
IN
GND
GND
GND
EN
ILMT
BYP

SY8286RAC_QFN20_3X3

PG
BS
LX
LX
LX
FB

VCC

NC
NC
NC

PAD

+3VALW

9
1
6
19
20
14
17
10
12
16
21

PG

BS
LX
LX
LX
FB

VCC

NC
NC
NC

PAD

LX_1VALW

FB_1VALW
LDO_3V_1VALW

9
1
6
19
20

FB_1.8VSP

14

LDO_3V_1.8VSP

17
10
12
16
21

BS_1.8VSP_RBS_1.8VSP

PC601

0.1U_0603_25V7K

1 2

0.1U_0603_25V7K

PC2203

1 2

PR601

BST_1VALW_RBST_1VALW

12

PC612

2.2U_0402_6.3V6M

Pin 7 BYP is for CS.
Common NB can delete +3VALW and PC15

PR2201
0_0603_5%

1 2

LX_1.8VSP

PC2210

12

2.2U_0402_16V6K

1 2

0_0603_5%

PR602

@EMI@

4.7_1206_5%

SNB_1VALW

1 2

(Common Part)
S

H00000Z200

PL601

1UH_6.6A_20%_5X5X3_M

1 2

FB = 0.6V

Rdown Vout=0.6V* (1+Rup/Rdown)

(Common Part)

H00000Z200

S

PL2201

1UH_6.6A_20%_5X5X3_M

1 2

12

@EMI@

PR2204

4.7_0603_5%

SNB_1.8VSP

12

@EMI@

PC2212

680P_0402_50V7K

Vout=0.6V* (1+Rup/Rdown)

= 0.6V*(1+20k/10k)

= 1.8V

@EMI@

680P_0603_50V7K

5X5X3
Isat:6.6A
DCR: 14mΩ (Max)

12

Rup

12

PC602

1 2

12

PR604

21.5K_0402_1%

PR606

31.6K_0402_1%

5X5X3
Isat:6.6A
DCR: 14mΩ (Max)

OVP=1.8*115%=2.07V

+1.0VALWP

12

12

PC607

PC606

330P_0402_50V7K

+1.8VGSP
TDC 5.18A
Peak Current 5.18A
OCP current 6.21A
FSW=500kHz

12

Rup

PR2202

12

PR2206

Rdown

PC608

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC2209

20K_0402_1%

330P_0402_50V7K

10K_0402_1%

PJ602

@

JUMP_43X118

2

112

+1.0VALW

+1.0VALWP

12

12

PC609

PC610

22U_0603_6.3V6M

22U_0603_6.3V6M

=0.6*(1+(21.5K/31.6K))

Vout=1.008V 0.8%

TDC 2A
Peak Current 2.9A
OCP current 3.48A
FSW=500kHz

+1.8VSP

PC2206

12

22U_0603_6.3V6M

12

PC2207

22U_0603_6.3V6M

PJ2202

@

112

JUMP_43X118

PC2208

22U_0603_6.3V6M

2

+1.8VS+1.8VSP

12

PC2205

22U_0603_6.3V6M

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

+1.0VALWP / +1.8VSP

+1.0VALWP / +1.8VSP

+1.0VALWP / +1.8VSP

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C

C

C

C1PRG LA-E051P

C1PRG LA-E051P

C1PRG LA-E051P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

79 103Monday, January 09, 2017

79 103Monday, January 09, 2017

79 103Monday, January 09, 2017

1.0

1.0

1.0

5

D D

B+

C C

PJ701

@

112

JUMP_43X79

12

PC704

0.1U_0402_25V6

@EMI@

+3VALW

+VCCIOP_B+

12

PC705

10U_0805_25V6K

+VCCIOP_EN
+VCCIOP_ILMT

12

PC716

1U_0402_6.3V6K

2
3
4
5
7

8
18
11
13
15

2

12

PC703

2200P_0402_50V7K

EMI@

+VCCIOP_LDO_3V

12

PR709

@

0_0402_5%

+VCCIOP_ILMT

12

PR714
0_0402_5%

B B

The current limit is set to 6.5A, 9.5A or 12.5A when this pin
is pull low, floating or pull high

4

PU701

IN
IN
IN
IN
GND
GND
GND
EN
ILMT
BYP

SY8286RAC_QFN20_3X3

Pin 7 BYP is for CS.
Common NB can delete +3VALW and PC15

VR_ON<26,38,81>

SUSP#<25,26,28,32,38,68,75,77,79>

VR_ON

SUSP#

check delay time with HW

9

PG

+VCCIOP_BST +VCCIOP_BST_R

1

BS

6

LX

19

LX

20

LX
FB

VCC

NC
NC
NC

PAD

14

+VCCIOP_LDO_3V

17
10
12
16
21

PR711

@

0_0402_5%

1 2

PR713

1K_0402_5%

1 2

+VCCIOP_FB

12

PR715

1M_0402_5%

PR701
0_0603_5%

1 2

+VCCIOP_LX

2.2U_0402_6.3V6M

+VCCIOP_EN

12

3

PR702

@EMI@

4.7_1206_5%

SNB_+VCCIOP

1 2

(Common Part)
SH00000Z200

PL701

1UH_6.6A_20%_5X5X3_M

1 2

PC715

PC701

0.1U_0603_25V7K

1 2

FB = 0.6V

Rdown

12

PC717

0.1U_0402_25V6

@EMI@

680P_0603_50V7K

1 2

12

PR704

1 2

1 2

12K_0402_1%

12

PR706

20.5K_0402_1%

Rup

PR705

PC702

5X5X3
I

sat:11A

DCR: 14mΩ (Max)

12

PC706

330P_0402_50V7K

PR703

1K_0402_1%

10_0402_1%

VCCIO_SENSE_R

5X5X3
Isat:6.6A
DCR: 14mΩ (Max)

12

12

PC707

22U_0603_6.3V6M

2

PC708

12

22U_0603_6.3V6M

12

PC709

22U_0603_6.3V6M

PR708

0_0402_5%

1 2

PR710

0_0402_5%

1 2

Imax=3.85A, Ipeak=5.5A, Iocp:6.6A

12

12

PC710

22U_0603_6.3V6M

12

PC711

22U_0603_6.3V6M

VCCIO_SENSE

VSSIO_SENSE

PC712

22U_0603_6.3V6M

+VCCIO

12

12

PC713

PC714

PC718

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

add 4 to 9 0603 22UF

Vout=0.6V* (1+Rup/Rdown)

=0.6*(1+(12k/20.5k))

OVP=0.95V*115%=1.0925V
Vout=0.951 V 2%

PR707
100_0402_1%

1 2

VCCIO_SENSE <11>

12

VSSIO_SENSE <11>

PR712
100_0402_1%

+VCCIOP

1

+VCCIOP

PJ702

@

112

JUMP_43X118

2

+VCCIO

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom
Date: Sheet of

Date: Sheet of

2

Date: Sheet of

0.95VS

0.95VS

0.95VS

1.0

1.0

80 103Monday, January 09, 2017

80 103Monday, January 09, 2017

1

80 103Monday, January 09, 2017

1.0

1

PC802

VSN_1PH_R

VSN_3PH_A_R

4.02K_0402_1%

1 2

PR835

Place close
to IA choke (Phase 1)

SW1_3PH_A<82>
SW2_3PH_A<82>
SW3_3PH_A<82>
SW4_3PH_A<82>
CSN1_3PH_A<82>
CSN2_3PH_A<82>
CSN3_3PH_A<82>
CSN4_3PH_A<82>

SW1_3PH_A

SW2_3PH_A

SW3_3PH_A

SW4_3PH_A

2200P_0402_50V7K

1 2

PR806

619_0402_1%

1 2

PC804
1000P_0402_50V7K

1 2

1 2

PR811

2.32K_0402_1%

1 2

1000P_0402_50V7K

PC809
1000P_0402_50V7K

1 2

3300P_0402_50V7K

PC815

15P_0402_50V8J

1 2

COMP_3PH_A_R

220K +-5% 0402 B25/50 4700K

PR845 100K_0603_1%
PR847 100K_0603_1%
PR849 100K_0603_1%
PR828 100K_0603_1%
PR851 10_0402_1%
PR854 10_0402_1%
PR855 10_0402_1%
PR829 10_0402_1%

CSREF_3PH_A

CSREF_3PH_A

CSREF_3PH_A

CSREF_3PH_A

PR803
100_0402_1%

VSSSA_SENSE<11>

1 2

A A

VCCSA_SENSE< 11>

+VCCSA

+VCCCORE

PR813
100_0402_1%

1 2

PR816
100_0402_1%

1 2

VCCSENSE<10>

VSSSENSE<10>

B B

C C

PR826
100_0402_1%

1 2

PR805

1 2

0_0402_5%

PR810

1 2

0_0402_5%

PR819

1 2

0_0402_5%

PR821

1 2

0_0402_5%

VSP_1PH_R

PC806

1 2

PR822

1K_0402_1%

1 2

PC811

PC819

3300P_0402_50V7K

PH801

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2

PR861

2.61K_0402_1%

1 2

PR868

2.61K_0402_1%

1 2

PR870

2.61K_0402_1%

1 2

PR856

2.61K_0402_1%

VSN_3PH_A

12

2

VSN_1PH

VSP_1PH

VSP_3PH_A

12

CSCOMP_3PH_A_R

12

PC833

0.1U_0402_25V6

12

PC835

0.1U_0402_25V6

12

PC837

0.1U_0402_25V6

12

PC826

0.1U_0402_25V6

PR832

49.9_0402_1%

1 2

CSP1_3PH_A

CSP2_3PH_A

CSP3_3PH_A

CSP4_3PH_A

12

12

FB_3PH_A_R

PR843

75K_0402_1%

PR846

165K_0402_1%

PC816
470P_0402_50V8J

1 2

1 2

PR836

590_0402_1%

12

PC825

1 2

PC824

220P_0402_50V8J

1000P_0402_50V7K

IccMAX_CORE

CSN_1PH<82>

PR834

22.6K_0402_1%

1 2

PC820

470P_0402_50V8J

1 2

1 2

PR841

23.7K_0402_1%

12

VRMP
connec t
to 3A rail

PC830

0.01U_0402_50V7K

1 2

1 2

+5VS

PWM1_3PH_A/ICCMAX3A<82>

PWM2_3PH_A/ADDR<82>

PWM3_3PH_A/VBOOT<82>

PWM4_3PH_A/ROSC_3PH<82>

100K +-1% 0402 B25/50 4250K

100K +-1% 0402 B25/50 4250K

Place close to SA choke

1 2

PR823

1.5K_0402_1%

VSP_3PH_A
VSN_3PH_A
IMON_3PH_A

DIFFOUT_3PH_A

FB_3PH_A
COMP_3PH_A
ILIM_3PH_A
CSCOMP_3PH_A
CSSUM_3PH_A
CSREF_3PH_A
CSP1_3PH_A
CSP2_3PH_A
CSP3_3PH_A

PC823

0.1U_0402_25V6

+CPU_B+

12

PR852
1K_0402_1%

12

PR857

2.2_0402_1%

PH804

PH802

1 2

COMP_1PH_C

0.1U_0402_25V6

PC832

1U_0402_10V6K

12

CSN_1PH_NTC

PC801

0.01U_0402_50V7K

1 2

PC805

0.01U_0402_50V7K

1 2

PR818

19.1K_0402_1%

1 2

PC808

1000P_0402_50V7K

12

1 2

PC812
15P_0402_50V8J

1

VSP_3PH_A

2

VSN_3PH_A

3

IMON_3PH_A

4

DIFFOUT_3PH_A

5

FB_3PH_A

6

COMP_3PH_A

7

ILIM_3PH_A

8

CSCOMP_3PH_A

9

CSSUM_3PH_A

10

CSREF_3PH_A

11

CSP1_3PH_A

12

CSP2_3PH_A

13

CSP3_3PH_A

PC829

TSENSE_3PH_A

1 2

DRON<82>

TSENSE_3PH_A

PR871
0_0402_5%

1 2
12

PR874

61.9K_0402_1%

3

1 2

1 2

PC810

0.01U_0402_25V7K

VSN_1PH
VSP_1PH

53

TAB

VRMP

VCC_CPU

12

PR801
12K_0402_1%

52

VSP_1PH

15

PR862

95.3K_0402_1%

4

PR802

7.5K_0603_1%

1 2

+3VS

12

12

12

PC807

470P_0402_50V7K

PR815

PR817

10K_0402_1%

42.2K_0402_1%

SW_1PH <82>

81205_SCLK

81205_ALERT

81205_SDIO

PR809

49.9_0402_1%

1 2

0_0402_5%

1 2

PR814

10_0402_1%

1 2

+1.0V_VCCST

12

PR804

100_0402_1%

@

1 2

PR812

12

PC803

PR808

PR807

1 2

0.1U_0402_25V6

45.3_0402_1%

100_0402_1%

CPU_SVID_CLK <9>

CPU_SVID_ALERT#_R <9>

CPU_SVID_DAT <9>

5

VGATE <38>

PR827

0_0402_5%

1 2

PR825

37.4K_0402_1%

1 2

PWM1_1PH/ICCMAX1<82>

VR_ON <26,38,80>

IccMAX_SA

+1.0V_VCCST

81205_SDIO

81205_ALERT

81205_SCLK

PWM1_1PH/ICCMAX1

IMON_1PH

CSP_1PH

CSN_1PH

ILIM_1PH

COMP_1PH

45

47

51

49

44

43

50

48

42

46

EN

VR_RDY

ILIM_1PH

CSP_1PH

VSN_1PH

CSN_1PH

IMON_1PH

COMP_1PH

PWM_1PH/ICCMAX_1PH

PWM1_3PH_A/ICCMAX_3PH_A18PWM2_3PH_A/ADDR19PWM3_3PH_A/VBOOT20PWM3_3PH_B/ROSC_3PH21PWM2_3PH_B/ROSC_1PH22PWM1_3PH_B/ICCMAX_3PH_B23DRON

VCC16TTSENSE_3PH_A14VRMP

TTSENSE_1PH/PSYS24TTSENSE_3PH_B25CSP3_3PH_B

17

12

12

PR864

4.32K_0402_1%

41

40

SDIO

SCLK

ALRT#

DIFFOUT_3PH_B

CSCOMP_3PH_B

CSSUM_3PH_B

CSREF_3PH_B

26

CSP4_3PH_A

PR865

24.9K_0402_1%

VRHOT#

VSP_3PH_B
VSN_3PH_B

IMON_3PH_B

FB_3PH_B

COMP_3PH_B

ILIM_3PH_B

CSP1_3PH_B
CSP2_3PH_B

12

PU801
NCP81205FMNTXG_QFN52_6X6

VR_HOT#_CPU

39
38
37
36
35
34
33
32
31
30
29

CSP1_3PH_B

28

CSP2_3PH_B

27

12

PR866

PR867

130K_0402_1%

97.6K_0402_1%

PR837

100_0402_1%

1 2

1 2

2K_0402_1%

1 2
1 2

2K_0402_1%

PR858
20K_0402_1%

1 2

PR820

PR824

PR830

@

1K_0402_1%

VR_HOT# <38>

+5VS

PSYS_MON <75>

VCC_CORE

ccMAX = 68A

I
VCC_SA

IccMAX = 11.1A

Place close to IA MOS

D D

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADESECRET INFORMATION.T HISSHEET MAY NOT BET RANSFERED FROM THECUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADESECRET INFORMATION.T HISSHEET MAY NOT BET RANSFERED FROM THECUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADESECRET INFORMATION.T HISSHEET MAY NOT BET RANSFERED FROM THECUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT ASAUTHORIZED BY COMPALELECT RONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENTEXCEPT ASAUTHORIZED BY COMPALELECT RONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENTEXCEPT ASAUTHORIZED BY COMPALELECT RONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

Compal Secret Data

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Title

Title

Title

CPU IC

CPU IC

CPU IC

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

SKL_H 42

Date: Sheet of

Date: Sheet of

Date: Sheet of

5

81 103Monday, January 09, 2017

81 103Monday, January 09, 2017

81 103Monday, January 09, 2017

1.0

1.0

1.0

5

PR901

2.2_0603_1%

BST1_CORE BST1_CORE_R

1 2

PC901

D D

PWM1_3PH_A/ICCMAX3A<81>

DRON<81>

C C

PWM2_3PH_A/ADDR<81>

B B

PWM3_3PH_A/VBOOT<81>

DRON

DRON

1 2

PR915

0_0402_5%

1 2

PR922
0_0402_5%

1 2

PR907
0_0402_5%

+5VS

+5VS

+5VS

EN1_CORE

12

EN2_CORE

12

EN3_CORE

12

PU901
NCP81151MNTBG_DFN8_2X2

FLAG

1

BST

DRVH

2

PWM

SW

3

EN

GND

4

VCC

DRVL

PC911

2.2U_0402_6.3V6M

PR910

2.2_0603_1%

1 2

PU904
NCP81151MNTBG_DFN8_2X2

FLAG

1

BST

DRVH

2

PWM

SW

3

EN

GND

4

VCC

DRVL

PC926

2.2U_0402_6.3V6M

PR918

2.2_0603_1%

BST3_CORE BST3_CORE_R

1 2

PU905
NCP81151MNTBG_DFN8_2X2

FLAG

1

BST

DRVH

2

PWM

SW

3

EN

GND

4

VCC

DRVL

PC944

2.2U_0402_6.3V6M

0.22U_0603_25V7K

1 2

9

HG1_CORE

8
7
6

LG1_CORE

5

BST2_CORE_RBST2_CORE

PC923

0.22U_0603_25V7K

1 2

9

HG2_CORE

8
7
6

LG2_CORE

5

PC942

0.22U_0603_25V7K

1 2

9

HG3_CORE

8
7
6

LG3_CORE

5

PR905

1 2

0_0805_5%

PR913

0_0805_5%

1 2

PR920
0_0805_5%

1 2

4

12

12

PC905

2

1

HG1_CORE_R

PQ903

D1

G1

7

D2/S1

S24S2

G2

5

3

6

2

1

PQ907

D1

G1

7

D2/S1

S24S2

G2

5

3

6

2

1

PQ910

D1

G1

7

D2/S1

S24S2

G2

5

3

6

10U_0805_25V6K

S2

PR908

AON6992_DFN5X6D-8-7

1 2

4.7_1206_5%

@EMI@

SNB1_CORE

12

PC913

1000P_0603_50V7K

@EMI@

12

12

PC919

10U_0805_25V6K

S2

PR916

AON6992_DFN5X6D-8-7

4.7_1206_5%

1 2

@EMI@

SNB2_CORE

12

PC927

1000P_0603_50V7K

@EMI@

12

12

PC938

10U_0805_25V6K

S2

PR923

AON6992_DFN5X6D-8-7

4.7_1206_5%

1 2

@EMI@

SNB3_CORE

12

PC946

1000P_0603_50V7K

@EMI@

12

12

PC907

PC909

PC906

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10X10X4
Isat:60A
DCR: 0.8925mΩ (Max)

PL901

1

4
3

2

0.22UH +-20% MMD-10DZ-R22MEX2L 35A

12

PC920

10U_0805_25V6K

10X10X4
Isat:60A
DCR: 0.8925mΩ (Max)

1
2

PC933

10U_0805_25V6K

10X10X4
Isat:60A
DCR: 0.8925mΩ (Max)

1
2

+CPU_B+

12

PC921

PC922

10U_0805_25V6K

10U_0805_25V6K

PL904

4
3

0.22UH +-20% MMD-10DZ-R22MEX2L 35A

+CPU_B+

12

12

PC940

PC939

10U_0805_25V6K

10U_0805_25V6K

PL906

4
3

0.22UH +-20% MMD-10DZ-R22MEX2L 35A

+CPU_B+

+VCCCORE

CSN1_3PH_A <81>

SW1_3PH_A <81>

+VCCCORE

CSN2_3PH_A <81>

SW2_3PH_A <81>

+VCCCORE

CSN3_3PH_A <81>

SW3_3PH_A <81>

3

PR902

2.2_0603_1%

1 2

PU902
NCP81253MNTBG_DFN8_2X2

1

BST

2

PWM

3

EN

4

VCC

12

PC932

PC931

EMI@

0.1U_0402_25V6

@EMI@

2200P_0402_50V7K

PU903
NCP81151MNTBG_DFN8_2X2

1
2
3
4

PC924

2.2U_0402_6.3V6M

FLAG
DRVH

DRVL

12

2.2_0603_1%

1 2

BST
PWM
EN
VCC

DRON

PWM4_3PH_A/ROSC_3PH<81>

PWM1_1PH/ICCMAX1<81>

1

+

2

DRON

PC928

100U_25V_NC_6.3X6

PR904

0_0402_5%

1 2

+CPU_B+

1

+

PC929

2

1 2

PR912

0_0402_5%

+5VS

100U_25V_NC_6.3X6

1

+

2

+5VS

PC930

100U_25V_NC_6.3X6

EN_SA

12

PC910

2.2U_0402_6.3V6M

EN4_CORE

12

9
8
7

SW

6

GND

5

@EMI@

5A Z120 25M 0805

1 2

PR909

FLAG
DRVH

SW

GND

DRVL

2

BST_SA_RBST_SA

PJ703

@

112

JUMP_43X118

PL707

BST4_core_RBST4_core

9
8
7
6
5

PC904

0.22U_0603_25V7K

1 2

HG_SA
SW_SA

LG_SA

2

1 2

HG4_core

0_0805_5%

1 2

PC915

0.22U_0603_25V7K
PR911

0_0805_5%

1 2

LG4_core

PR903

PQ902

B+

AON7934_DFN3X3A8-10

HG_SA_R

4

3

2

D1

D1

D1

D110D2/S1

S2

S2

S2

6

7

5

1

HG4_GT_R

G1

7

D2/S1

G2

6

1

PJ704

@

SA_B+

12

12

PC902

PC903

10U_0805_25V6K

10U_0805_25V6K

PL902

0.47UH_MMD06CZR47M_17.5A_20%

1

1

G1

9

G2

8

2

PQ906

D1

S24S2

S2

5

3

AON6992_DFN5X6D-8-7

2

PR906

4.7_1206_5%

1 2

@EMI@

SNB_SA

12

PC912

1000P_0603_50V7K

@EMI@

12

12

PC916

10U_0805_25V6K

PR914

4.7_1206_5%

1 2

@EMI@

SNB4_CORE

12

PC925

1000P_0603_50V7K

@EMI@

2

+CPU_B+

112

JUMP_43X79

7X7X4
Isat:26A
DCR: 4.2mΩ (Max)

4

+VCCSA

3

CSN_1PH <81>

SW_1PH <81>

+CPU_B+

12

12

PC917

10U_0805_25V6K

1
2

PC914

PC918

10U_0805_25V6K

10U_0805_25V6K

10X10X4
Isat:60A
DCR: 0.8925mΩ (Max)

PL903

4
3

0.22UH +-20% MMD-10DZ-R22MEX2L 35A

+VCCCORE

CSN4_3PH_A <81>

SW4_3PH_A <81>

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

SKL_H 42

Title

Title

Title

CPU_CORE

CPU_CORE

CPU_CORE

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C

C

C

Compal Electronics, Inc.

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

82 103Monday, January 09, 2017

82 103Monday, January 09, 2017

82 103Monday, January 09, 2017

1.0

1.0

1.0

1

+VCCCORE

2

3

4

5

3 X 330uF
30 X22uF
63 X1uF

1

1

PC947

2

2

A A

22U_0603_6.3V6M

1

1

PC981

2

2

22U_0603_6.3V6M

1

1

PC948

2

22U_0603_6.3V6M

1

PC982

2

22U_0603_6.3V6M

1

PC950

PC949

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC984

PC983

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC951

2

22U_0603_6.3V6M

1

PC985

2

22U_0603_6.3V6M

1

PC953

PC952

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC986

PC987

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC954

PC988

PC956

PC955

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC990

PC989

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC957

1U_0201_6.3V6M

12

12

PC991

1U_0201_6.3V6M

12

12

PC958

1U_0201_6.3V6M

12

PC992

1U_0201_6.3V6M

12

PC960

PC959

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC994

PC993

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC961

PC962

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC995

PC996

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC963

1U_0201_6.3V6M

12

PC997

1U_0201_6.3V6M

12

12

PC965

PC964

PC998

PC966

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC999

PC1000

1U_0201_6.3V6M

1U_0201_6.3V6M

12

PC967

1U_0201_6.3V6M

12

12

PC1001

1U_0201_6.3V6M

12

12

PC968

1U_0201_6.3V6M

12

PC1002

1U_0201_6.3V6M

12

12

PC970

PC969

PC1003

PC971

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

12

PC1005

PC1004

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC973

PC972

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1007

PC1006

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC974

PC1008

PC976

PC975

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1010

PC1009

1U_0201_6.3V6M

1U_0201_6.3V6M

1

+

PC977

2

330U_D2_2V_Y

+VCCCORE

1

1

+

PC978

2

@

1

+

+

PC979

PC980

2

2

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

1

1

+

+

PC1105

PC1104

2

2

@

@

330U_D2_2V_Y

330U_D2_2V_Y

1

1

2

B B

1

1

PC1011

PC1012

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

PC1014

PC1013

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1015

2

22U_0603_6.3V6M

1

PC1017

PC1016

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1020

PC1019

PC1018

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

12

PC1022

PC1021

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1023

1U_0201_6.3V6M

12

PC1025

PC1024

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1026

PC1027

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1028

PC1030

PC1029

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

12

12

PC1032

PC1031

PC1033

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1034

1U_0201_6.3V6M

12

12

PC1036

PC1035

PC1037

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1040

PC1039

PC1038

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

12

PC1042

PC1041

PC1043

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

+VCCSA

SE00000M000

1

1

2

1

2

1

1

PC1155

PC1154

PC1164

PC1156

2

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1

PC1165

2

22U_0603_6.3V6M

1

1

PC1157

2

22U_0603_6.3V6M

1

PC1159

PC1158

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1160

PC1162

PC1161

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

Total VCCSA Output Capacitor:
3 X 1uF_0201

1

12 X 22uF_0603

PC1163

2

22U_0603_6.3V6M

22U_0603_6.3V6M

SE00000UC00

12

C C

12

12

PC1167

PC1166

PC1168

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

D D

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4

Title

Title

Title

Processor decoupling

Processor decoupling

Processor decoupling

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C

C

C

SKL_H 42

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

5

83 103Monday, January 09, 2017

83 103Monday, January 09, 2017

83 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

NVVDD1_ISUMP1<85>

12

12

PC1202

@

1 2

PR1202

0.1U_0402_25V6

12

NVVDD1_PROG1

24

GPU1_PWM4

0_0402_5%

PR1266

1 2

@

@

1 2

0_0402_5%

NVVDD1_PROG2

GPU1_CSPSUM

21

22

APL223APL1

CSPSUM

10

GPU1_PWM3

GPU1_PWM2 GPU1_CSNSUM

0_0402_5%

0_0402_5%

PR1268

PR1267

1 2

1 2

@

@

20K_0402_1%

PR1209

PR1213 0_0402_5%@

PC1205 0.1U_0402_25V6@

PC1206 0.1U_0402_25V6@

PC1208 0.12U_0402_10V6K

CSNSUM

PR12540_0402_5%

PR12560_0402_5%

PR12570_0402_5%

1 2

PC1204

1 2

PU1201

PR1255

PR1263

NVVDD1_B+

12

PR1207

91K_0402_1%

12

0.1U_0402_25V6@

1 2

12

12

PR1217
0_0402_5%

12

12

PR1218

2.4K_0402_1%

GPU1_COMP

GPU1_EAP

30

29

EAP

COMP

FB
FBRTN
APL3
APL4
LPC
EN
PSI
PGOOD
VID
REFADJ
GND

REFIN1VREF2FSW3PWM84PWM75PWM66PWM57PWM48PWM39PWM2

GPU1_REFIN

12

16.5K_0402_1%

12

309_0402_1%

1 2

PC1218

PR1206

0_0402_5%

PR1208

15.8K_0402_1%

NVVDD1_PROG5

PR1219

0_0402_5%

GPU1_SS

GPU1_VINMON

27

26

25

28

SS

LLTH

IMON

VINMON

UP9511PQGJ_VQFN40_5X5

NVVDD1_PROG6

0.01U_0402_16V

PC1201

PC1203

0_0402_5%

PC1212

@

1 2

PR1225
1K_0402_1%

PR1235
0_0402_1%

PR1242

PC1217

0.1U_0402_25V6

1 2

PC1207

0.015U_0402_16V7K

12

PR1223

@

12

12

GPU1_PSI

GPU1_VID
GPU1_REFADJ

12

R1

6.19K_0402_1%

PR1247

4.32K_0402_1%

R2

PR1265

20.5K_0402_1%

12

C

4700P_0402_25V7K

PR1216

PC1209 0.1U_0402_25V6@

1 2

R4

R5

PR1201
10K_0402_5%

0_0402_5%

1 2

0_0402_5%

31
32
33
34
35
36
37
38
39
40
41

R3

12

12

NVVDD1_FBRTN

D D

0.01U_0402_16V7K

PR1220

PR1222
0_0402_5%

NVVDD_VCC_SENSE<45>

+NVVDD1

C C

NVVDD_VSS_SENSE<45>

PR1271

0_0402_5%

NVVDD1_EN<38,41>

+3VS

B B

1 2

1 2

PR1270

@

0_0402_1%

NVVDD_PSI<41,87>

PR1241
0_0402_5%

12

0.1U_0402_25V6

12

12

12

PR1224 100_0402_5%

PR1228
0_0402_5%

12

12

PR1231

100_0402_5%

NVVDD1_FBRTN

+3VALW

1 2

34

D

PQ1201B

5

G

S

DMN53D0LDW-7 2N SOT363-6

PC1215

@

+1.8VS

PR1238

0_0402_5%

1 2

@

PR1243

0_0402_5%

1 2

@

PC1211

1 2

@

0.1U_0402_25V6

PC1213

1 2

0.1U_0402_25V6

PC1214

1 2

@

0.1U_0402_25V6

PR1236
10K_0402_1%

61

D

PQ1201A

2

G

S

DMN53D0LDW-7 2N SOT363-6

+3VS

NVVDD1_PGOOD<41,87,90>

NVVDD_VID<41>

NVVDD1_PROG3

NVVDD1_PROG4

NVVDD1_LPC

PR1239
30K_0402_1%

1 2

PR1226
0_0402_5%@

1 2

PR1244
10K_0402_5%

1 2

1 2

0_0402_1%

0.1U_0402_25V6

PR1246

PWMVID 的 RC BOM 標 公式
請 根 據GPU's confi g 設定

NVVDD1_ISUMP2 <85>

12

PR1203

20K_0402_1%

NTC1_La NTC1_Lb

@

PR1210

1 2

0_0402_5%

1 2

1 2

1 2

1 2

PR1221

499_0402_1%

20

ISEN1

19

ISEN2

18

ISEN3

17

ISEN4

16

ISEN5

15

ISEN6

14

ISEN7

13

ISEN8

12

5VCC

11

PWM1

12

12

12

@

12

NTC1_La NTC1_Lb

12

470K_0402_5%_TSM0B474J4702RE

12

PC1210

0.1U_0402_10V6K

GPU1_ISEN1
GPU1_ISEN2
GPU1_ISEN3
GPU1_ISEN4
GPU1_ISEN5

PR1233 100K_0402_5%

PR1245

GPU1_PWM1

0_0402_5%

1 2

PR1269 0_0402_5%

NVVDD1_ISUMP3<86>

PR1204

20K_0402_1%

PR1211 1_0402_1%
PR1212 1_0402_1%
PR1214 1_0402_1%
PR1215 1_0402_1%

1 2

12

12

12
12
12
12

PH1201

@

PR1227 2.2K_0402_1%

12

PR1229 2.2K_0402_1%

12

PR1230 2K_0402_1%

12

PR1232 2K_0402_1%

12

+5VCC

+5VCC

1U_0402_6.3V6K

12

NVVDD1_PWM1 <85>

NVVDD1_PWM2 <85>

NVVDD1_PWM3 <86>

NVVDD1_PWM4 <86>

NVVDD1_ISUMP4<86>

PR1205

layout 上 :

20K_0402_1%

請 將 Tota l DC R sensin g 的compon en t
放 靠 近Control le r .

NVVDD1_ISUMN1 <85>
NVVDD1_ISUMN2 <85>
NVVDD1_ISUMN3 <86>
NVVDD1_ISUMN4 <86>

close phase1

layout 上 : 請 將 RSE N1 ~ 4
放 靠 近 C o n t r o l l e r.

NVVDD1_PH1

NVVDD1_PH2
NVVDD1_PH3

12

NVVDD1_PH4

PR1237 2.2_0603_1%

PC1216

+5VS

12

PR1248

@

1 2

1 2

NVVDD1_PROG1

@

1 2

43K_0402_5%

PR1258

0_0402_5%

PR1259

1 2

NVVDD1_PROG2

Master GPU

NVVDD1_PROG6

12

Fsw=300kHz

PR1234 0_0402_5%

PR1240

1 2

33K_0402_5%

PR1252

@

1 2

PR1262

1 2

PR1253

1 2

51K_0402_5%

PR1264

0_0402_5%

1 2

NVVDD1_LPC

PR1249

36K_0402_5%

0_0402_5%

NVVDD1_PROG3

請 教AUTO
PHASE的 設 定

+5VS

PR1251

PR1250

@

@

1 2

1 2

10K_0402_5%

PR1260

0_0402_5%

1 2

PR1261

1 2

NVVDD1_PROG4

Cold Boot = 4-phase
Warm Boot = 4-phase

10K_0402_5%

0_0402_5%

NVVDD1_PROG5

49.9K_0402_1%

73.2K_0402_1%

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

+NVVDD Controller

+NVVDD Controller

+NVVDD Controller

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C

C

C

C1PRG LA-E051P

C1PRG LA-E051P

C1PRG LA-E051P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

84 103Monday, January 09, 2017

84 103Monday, January 09, 2017

84 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

Master GPU

33U_D2_25VM_R40M

GPU1_B+

4
3

CSSN_B+<45>CSSP_B+<45> CSSN_NVVDD<45>CSSP_NVVDD<45>

NVVDD1_PWM1
NVVDD1_ZCD_EN#1

NVVDD1_BOOT1
NVVDD1_PHASE1

PC1316

PC1302

1 2

1

2

10U_0805_25V6K

+

PC1305

PR1301

1
2

0.005_2512_1%

1

+

PC1306

2

33U_D2_25VM_R40M

D D

NVVDD1_PWM1<84>

NVVDD1_B+

C C

B+

1

+

PC1309

2

@

+5VS

PR1303

0_0402_5%

@

1 2

+5VS

PC1301

1U_0603_16V7

12

PR1306

0_0402_5%

1 2

@

12

12

12

PC1313

PC1312

0.1U_0402_25V6

EMI@

EMI@

2200P_0402_50V7K

PJ1301@

2

112

JUMP_43X118

PJ1302

@

2

112

JUMP_43X79

100U_25V_NC_6.3X6

PR1305
1K_0402_1%

12

PR1308

1 2

0_0402_1%

0.1U_0603_50V7K

12

PC1314

10U_0805_25V6K

12

12

PC1308

PC1315

10U_0805_25V6K

10U_0805_25V6K

PR1302

1

4
3

2

0.005_2512_1%

PU1301

1

PWM

CGND

2

ZCD_EN#

3
4
5
6
7
8

9
10
11
12
13

GL

VCIN

DSBL#

CGND

THWn

BOOT

VDRV

NC

PGND

PHASE

GL

VIN

SW

VIN

SW

PGND

SW

SW

SW

SW

SW

SW

SW

SW14SW

SIC632CDT1GE3_POWERPAK31_5X5

NVVDD1_B+

28
27

NVVDD1_DSBL1

26
25

NVVDD1_VDRV1

24
23
22
21
20
19
18
17
16
15

PR1304

1 2

10K_0402_1%

PR1307

2.2_0603_1%

PC1303

1U_0603_16V7

12

PC1321

@EMI@

3300P_0805_50V7K

+5VS

12

12

@EMI@

2.2_0603_1%

GPU1_SNB1

12

PR1309

13X13X4

sat:70A

NVVDD1_PH1

NVVDD1_ISUMP1<84>

NVVDD1_ISUMN1<84>

I
DCR: 0.5mΩ (Max)

PL1301

NVVDD1_PH1

1
2

0.22UH_MMD12DZNR22MEX_40A_20%

4
3

+NVVDD1

+5VS

PR1310

0_0402_5%

@

1 2

PR1312

NVVDD1_PWM2<84>

B B

NVVDD1_B+

A A

5

+5VS

1U_0603_16V7

12

PR1313

0_0402_5%

1 2

@

12

12

PC1330

PC1331

0.1U_0402_25V6

EMI@

EMI@

2200P_0402_50V7K

1K_0402_1%

12

PC1322

12

PC1333

PC1332

10U_0805_25V6K

PR1315

1 2

PC1323

0_0402_1%

1 2

0.1U_0603_50V7K

12

12

12

PC1334

PC1335

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

4

NVVDD1_PWM2
NVVDD1_ZCD_EN#2

NVVDD1_BOOT2
NVVDD1_PHASE2

PU1302

1

PWM

CGND

2

ZCD_EN#

3

4

5

6

7

8

9
10
11
12
13

GL

VCIN

DSBL#

CGND

THWn

BOOT

VDRV

NC

PGND

PHASE

GL

VIN

SW

VIN

SW

PGND

SW

SW

SW

SW

SW

SW

SW

SW14SW

SIC632CDT1GE3_POWERPAK31_5X5

28
27

NVVDD1_DSBL2

26
25

NVVDD1_VDRV2

24
23
22
21
20
19
18
17
16
15

3

+5VS

PR1311

1 2

10K_0402_1%

PR1314

2.2_0603_1%

12

PC1324

1U_0603_16V7

12

12

PR1316

@EMI@

2.2_0603_1%

GPU1_SNB2

12

PC1342

@EMI@

3300P_0805_50V7K

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NVVDD1_PH2

NVVDD1_ISUMP2<84>

NVVDD1_ISUMN2<84>

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

13X13X4
Isat:70A
DCR: 0.5mΩ (Max)

NVVDD1_PH2

PL1302

1
2

0.22UH_MMD12DZNR22MEX_40A_20%

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4
3

2

+NVVDD1

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

PWR_+NVVDD

PWR_+NVVDD

PWR_+NVVDD

Document Number Rev

Document Number Rev

Document Number Rev

SKL_H 42

1

1.0

1.0

85 103Monday, January 09, 2017

85 103Monday, January 09, 2017

85 103Monday, January 09, 2017

1.0

5

4

3

2

1

Master GPU

D D

+5VS

PR1319

1 2

10K_0402_1%

PR1321

2.2_0603_1%

PC1345

1U_0603_16V7

12

PR1325
10K_0402_1%

1 2

PR1328

2.2_0603_1%

1U_0603_16V7

12

PC1384

+5VS

12

NVVDD1_PH3

NVVDD1_PH3

12

PR1323

2.2_0603_1%

@EMI@

GPU_SNB3

12

NVVDD1_ISUMP3<84>

PC1363

NVVDD1_ISUMN3<84>

@EMI@

3300P_0805_50V7K

+5VS

12

PC1366

12

PR1330

@EMI@

2.2_0603_1%

GPU1_SNB4

12

NVVDD1_PH4

NVVDD1_PH4

NVVDD1_ISUMP4<84>

NVVDD1_ISUMN4<84>

13X13X4

sat:70A

I
DCR: 0.5mΩ (Max)

PL1303

1

4
3

2

0.22UH_MMD12DZNR22MEX_40A_20%

13X13X4
Isat:70A
DCR: 0.5mΩ (Max)

PL1304

1

4
3

2

0.22UH_MMD12DZNR22MEX_40A_20%

+NVVDD1

+NVVDD1

PR1318

0_0402_5%

@

1 2

PR1317

NVVDD1_PWM3<84>

NVVDD1_B+

C C

NVVDD1_PWM4<84>

B B

NVVDD1_B+

+5VS

12

PR1320

0_0402_5%

1 2

@

12

12

PC1353

PC1354

0.1U_0402_25V6

EMI@

EMI@

2200P_0402_50V7K

+5VS

PR1324

0_0402_5%

@

1 2

+5VS

12

PR1327

0_0402_5%

1 2

@

12

12

PC1373

PC1374

0.1U_0402_25V6

EMI@

EMI@

2200P_0402_50V7K

1K_0402_1%

12

PC1343

1U_0603_16V7

12

PC1355

PC1356

10U_0805_25V6K

PC1364

1U_0603_16V7

12

PC1376

PC1375

10U_0805_25V6K

12

10U_0805_25V6K

12

10U_0805_25V6K

12

PC1357

10U_0805_25V6K

PR1326
1K_0402_1%

12

PC1377

10U_0805_25V6K

PR1322

1 2

0_0402_1%

12

PC1358

10U_0805_25V6K

12

PR1329

1 2

0_0402_1%

12

PC1378

10U_0805_25V6K

PC1344

1 2

0.1U_0603_50V7K

PC1365

1 2

0.1U_0603_50V7K

NVVDD1_PWM3
NVVDD1_ZCD_EN#3

NVVDD1_BOOT3
NVVDD1_PHASE3

NVVDD1_PWM4
NVVDD1_ZCD_EN#4

NVVDD1_BOOT4
NVVDD1_PHASE4

PU1303

1

PWM

2

ZCD_EN#

3

VCIN

4

CGND

5

BOOT

6

NC

7

PHASE

8

VIN

9

VIN

10

PGND

11

SW

12

SW

13

SW
SW14SW

SIC632CDT1GE3_POWERPAK31_5X5

PU1304

1

PWM

2

ZCD_EN#

3

VCIN

4

CGND

5

BOOT

6

NC

7

PHASE

8

VIN

9

VIN

10

PGND

11

SW

12

SW

13

SW
SW14SW

SIC632CDT1GE3_POWERPAK31_5X5

CGND

DSBL#

THWn

VDRV

PGND

CGND

DSBL#

THWn

VDRV

PGND

28
27

GL

26
25
24
23
22

GL

21

SW

20

SW

19

SW

18

SW

17

SW

16

SW

15

28
27

GL

26
25
24
23
22

GL

21

SW

20

SW

19

SW

18

SW

17

SW

16

SW

15

NVVDD1_DSBL3
NVVDD1_VDRV3

NVVDD1_DSBL4
NVVDD1_VDRV4

@EMI@

3300P_0805_50V7K

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

PWR_+NVVDD

PWR_+NVVDD

PWR_+NVVDD

Document Number Rev

Document Number Rev

Document Number Rev

SKL_H 42

1

86 103Monday, January 09, 2017

86 103Monday, January 09, 2017

86 103Monday, January 09, 2017

1.0

1.0

1.0

5

Master GPU

D D

EN can't float

PR1427

0_0402_5%

PR1412

PR1428

PR1407

1 2

PR1401

1 2

0_0402_5%@

12

PR1410

@

0_0402_5%

NVVDDS_VID<41>

Avoid high dV/dt

PR1403
100K_0402_1%

1 2

PC1556

@

1 2

0.1U_0402_16V7K

NVVDD2_DGPU_PSI_R

1 2

PR1409

0_0402_5%

12

R1

PR1414

6.19K_0402_1%

NVVDD2_HG1
NVVDD2_EN_R

NVVDD2_DGPU_VID_R

R3

12

PR1415

NVVDD2_VREF_R

12

C

NVVDD2_EN<41,90>

NVVDD1_PGOOD

1 2

+3VS

@

0_0402_5%

1 2

+1.8VS

10K_0402_1%

NVVDD_PSI

C C

B B

1 2
@

0_0402_5%

12

NVVDD2_BST1_R

1 2

NVVDD2_REFIN

4.32K_0402_1%

PC1440

@

1500P_0402_50V7K

NVVDD2_SW1

PC1409

0.22U_0603_25V7K

PR1404

2.2_0603_1%

NVVDD2_BST1

NVVDD2_VIDBUF

12

R4

PR1416

16.5K_0402_1%

NVVDD2_REFIN_R

R5

PR1421
309_0402_1%

1 2

PR1422

+5VS

R2

20.5K_0402_1%

4

12

PC1401

4.7U_0603_6.3V

NVVDD2_LG2NVVDD2_LG1

NVVDD2_SW2

PU1401

18

17

19

LG2

LG1

PH1

PVCC

COMP/OPT

VIDBUF6REFIN7VREF8FS9FBRTN

NVVDD2_FS

12

PC1429

1 2

0.01U_0402_16V

16

NCP81278MNTXG_QFN20_3X3

PH2

NVVDD2_BST2

15

BST2

NVVDD2_HG2

14

HG2

13

PGOOD

NVVDD2_COMP

12
11

FB

10

NVVDD2_FB

PR1413

NVVDD2_FBRTN

39.2K_0402_1%

PR1418

10K_0402_5%

PC1439

1000P_0402_25V

PR1423
0_0402_1%

1 2

20

1

BST1

2

HG1

3

EN

4

PSI

5

VID

GND

21

12

NVVDD2_VREF

PC1428

4700P_0402_25V7K

12

12

12

0.22U_0603_25V7K

NVVDD2_BST2_R

PR1405

2.2_0603_1%

1 2

1 2

PR1411

82.5K_0402_1%

NVVDD2_COMP_R

PC1425

100P_0402_50V8J

1 2

1 2

NVVDD2_VCC_SENSE_R

PR1424
0_0402_1%

1 2

PC1410

PR1406

10K_0402_5%

@

Ipeak= 84A
Imax = 40A
Iocp = 100.8A

PC1419
10P_0402_25V8J

1 2

PR1417

49.9_0603_1%

1 2

NVVDD2_FB_R

PC1438
47P_0402_50V8J

1 2

Avoid high dV/dt

3

+3VS

1 2

NVVDD2_PGOOD <41,90>

12

PR1408

51.1K_0402_1%

Place close to GPU

PR1425
100_0402_5%

12

PR1426

12

100_0402_5%

GPU1_B+

NVVDD2_HG1

NVVDD2_SW1

NVVDD2_LG1

NVVDD2_HG2

NVVDD2_SW2

NVVDD2_LG2

+NVVDD2

NVVDDS_VCC_SENSE <45>

NVVDDS_VSS_SENSE <45>

2

PJ1401@

2

112

JUMP_43X118

2

1

PQ1401

D1

G1

7

D2/S1

G2

5

6

1

G1

7

D2/S1

G2

5

6

7

S24S2

S2

3

AON6992_DFN5X6D-8-7

2

PQ1403

D1

S24S2

S2

3

AON6992_DFN5X6D-8-7

PR1402

1
2

0.005_2512_1%

CSSP_NVVDDS<45> CSSN_NVVDDS<45>

2

1

PQ1402

D1

G1

D2/S1

S24S2

S2

G2

5

3

6

7

1

D2/S1

6

2

PQ1404

D1

G1

S24S2

S2

G2

5

3

AON6992_DFN5X6D-8-7

0.22UH_MMD-10DZ-R22MEX2L_35A_20%

4
3

10X10X4
I

sat:60A

DCR: 0.82mΩ (Max)

PL1401

1 2

10X10X4
Isat:60A
DCR: 0.82mΩ (Max)

PL1402

0.22UH_MMD-10DZ-R22MEX2L_35A_20%

AON6992_DFN5X6D-8-7

1 2

12

12

PC1405

PC1404

0.1U_0402_25V6

EMI@

EMI@

2200P_0402_50V7K

12

12

PC1423

PC1422

0.1U_0402_25V6

EMI@

EMI@

2200P_0402_50V7K

12

12

PC1407

PC1406

10U_0805_25V6K

10U_0805_25V6K

12

PC1427

PC1426

10U_0805_25V6K

10U_0805_25V6K

NVVDD2_B+

12

PC1402

10U_0805_25V6K

NVVDD2_B+

12

1

12

PC1408

10U_0805_25V6K

+NVVDD2

1

+

PC1424

2

100U_25V_NC_6.3X6

+NVVDD2

Config

Vmax

A A

Vboot

R1
R2
R3
R4
R5
C

5

A

0.6Vmin

1.2

0.875
39K
39K

1.5K
30K

1.5K

1.5n

0.6

1.2

0.9
20K
20K
2K
18K
0

2.7n

B

C

0.65

1.15

0.9
39K

NVVDDS
TDC 28A
Peak Current 84A
OCP=100.8A

H/S Rds(on): <8.6mohm
L/S Rds(on): <2.5mohm

MAX

30K
3K
24K
3K

1.8n

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

PWR_+NVVDDS

PWR_+NVVDDS

PWR_+NVVDDS

Document Number Rev

Document Number Rev

Document Number Rev

SKL_H 42

1

87 103Monday, January 09, 2017

87 103Monday, January 09, 2017

87 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

Master GPU

D D

+NVVDD1

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1441

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1443

PC1442

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1445

PC1444

12

12

1U_0402_6.3V6K

PC1446

PC1447

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1449

PC1448

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1451

PC1450

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1452

12

1U_0402_6.3V6K

PC1453

PC1454

12

+NVVDD
330uF X 8

+NVVDD2

47uF_0805 X 2
22uF_0603 X 4
10uF_0603 X11

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1463

12

12

C C

1U_0402_6.3V6K

PC1485

12

12

1U_0402_6.3V6K

PC1505

12

12

10U_0603_6.3V6M

PC1533

12

B B

12

1

+

PC1347

2

330U_D2_2V_Y

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1464

12

1U_0402_6.3V6K

PC1486

12

1U_0402_6.3V6K

PC1506

12

10U_0603_6.3V6M

PC1534

12

1

1

+

+

PC1367

2

2

330U_D2_2V_Y

PC1466

PC1465

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1488

PC1487

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1507

PC1508

12

12

10U_0603_6.3V6M

10U_0603_6.3V6M

PC1536

PC1535

12

12

1

+

PC1530

PC1529

2

330U_D1_2VY_R9M

330U_D1_2VY_R9M

1U_0402_6.3V6K

PC1467

PC1468

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1489

PC1490

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1510

PC1509

12

12

10U_0603_6.3V6M

10U_0603_6.3V6M

PC1538

PC1537

1

+

PC1310

2

12

12

1

+

PC1304

2

330U_D2_2V_Y

330U_D2_2V_Y

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1469

12

1U_0402_6.3V6K

PC1491

12

1U_0402_6.3V6K

PC1511

10U_0603_6.3V6M

PC1539

12

1

+

PC1325

2

330U_D2_2V_Y

1U_0402_6.3V6K

PC1470

PC1471

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1493

PC1492

12

12

22U_0805_6.3VAM

22U_0805_6.3VAM

1

1

2

1

+

2

PC1513

PC1512

2

10U_0603_6.3V6M

10U_0603_6.3V6M

PC1541

PC1540

12

12

PC1326

330U_D2_2V_Y

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1472

12

1U_0402_6.3V6K

PC1494

12

22U_0805_6.3VAM

1

PC1514

2

10U_0603_6.3V6M

PC1542

12

1U_0402_6.3V6K

PC1473

PC1474

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1495

PC1496

12

12

22U_0805_6.3VAM

47U_0805_6.3V6M

1

2

PC1516

12

12

PC1515

10U_0603_6.3V6M

PC1543

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1476

PC1475

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1498

PC1497

12

47U_0805_6.3V6M

PC1518

1uF_0402 X 49

12

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1455

12

1U_0402_6.3V6K

PC1477

12

10U_0603_6.3V6M

PC1501

12

1U_0402_6.3V6K

PC1456

PC1457

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1479

PC1478

12

12

10U_0603_6.3V6M

10U_0603_6.3V6M

PC1503

PC1502

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1459

PC1458

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1481

PC1480

12

12

10U_0603_6.3V6M

47U_0805_6.3V6M

PC1517

PC1504

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1461

PC1460

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC1482

PC1483

12

1

1

+

+

PC1430

PC1411

2

2

330U_D2_2V_Y

330U_D2_2V_Y

+NVVDD2
330uF X 2
47uF_0805 X 1
10uF_0603 X 4

1U_0402_6.3V6K

1uF_0402 X 16

PC1462

12

1U_0402_6.3V6K

PC1484

12

A A

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2016/02/01 2017/12/31

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Date: Sheet o f

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

PWR_VGA DECOUPLING

PWR_VGA DECOUPLING

PWR_VGA DECOUPLING

SKL_H 42

88 103Monday, January 09, 2017

88 103Monday, January 09, 2017

88 103Monday, January 09, 2017

1

1.0

1.0

1.0

5

D D

PC1701

TON_+1.35VS_VGAP_R

12

0.1U_0402_25V6

PR1704

12

12

Rref1

PR1713

PR1707

20K_0402_1%

20K_0402_1%

2.2_0402_1%

12

12

PR1710

8.87K_0402_1%

12

Rref2

B+_+1.5VS_VGAP1

+3VS

C C

1.35VSDGPU_EN<38,41>

Vboot=Vref*R2/(R1+R2+80)

B B

PR1705

10K_0402_1%

+1.35VS_VGA_PGOOD<45>

12

PC1723

0.1U_0402_25V6

PC1724

0.033U_0402_25VK

=2*20K/(8.87k+20K+80)

=1.382V

PR1701

383K_0402_1%

12

TON_+1.35VS_VGAP UG1_+1.35VS_VGAP

12

EN_+1.35VS_VGAP

12

PC1719

0.1U_0402_25V6

VREF_+1.35VS_VGAP

REFIN_+1.35VS_VGAP

SS_+1.35VS_VGAP

12

PC1725

@

47P_0402_50V8J

PU1701

9

TON

13

PGOOD

3

EN

4

PSI

5

VID

8

VREF

7

REFIN

6

REFADJ

11

SS

21

GND

RT8812AGQW-GP

OPS

4

+5VALW

PR1702

2.2_0603_5%

1 2

PVCC_+1.5VS_VGAP1

18

PVCC

UGATE1

BOOT1

PHASE1

LGATE1

UGATE2

BOOT2

PHASE2

LGATE2

VSNS

RGND

12

PC1708

2.2U_0603_16V6K

2

1

20

19

14

15

16

17

12

10

BOOT1_+1.35VS_VGAP

SW1_+1.35VS_VGAP

LG1_+1.35VS_VGAP

UG2_+1.35VS_VGAP

BOOT2_+1.35VS_VGAP

SW2_+1.35VS_VGAP

LG2_+1.35VS_VGAP

RGND

PR1716

1 2

0_0402_5%

@

2.2_0603_5%

PR1708

11.5K_0402_1%

2.2_0603_5%

PR1711
100_0402_5%

1 2

PR1717

0_0402_5%

@

1 2

PR1706

BOOT1_+1..35VS_VGAP_R

12

Rocset for 66A

12

PR1709

BOOT2_+1.35VS_VGAP_R

12

12

PC1726

0.1U_0402_25V6

PC1717

0.22U_0603_25V7K

12

PC1720

0.22U_0603_25V7K

12

3

B+_+1.5VS_VGAP1

12

12

12

PC1703

PC1704

PC1702

10U_0805_25V6K

0.1U_0402_25V6

@EMI@

EMI@

2200P_0402_50V7K

7X7X4

PQ1701

AON6992 2N DFN5X6D

G1

7

12

6

12

PQ1702

AON6992 2N DFN5X6D

G1

7

12

6

12

Isat:24A
DCR: 1.47mΩ (Max)

PL1701

0.36UH_PDME064T-R36MS1R405_24A_20%

1 2

PR1703

@EMI@

4.7_1206_5%

SNB1_+1.35VS_VGAP

PC1718

@EMI@

680P_0402_50V7K

PC1721

7X7X4
Isat:24A
DCR: 1.47mΩ (Max)

@EMI@

SNB2_+1.35VS_VGAP

@EMI@

10U_0805_25V6K

PL1702

0.36UH_PDME064T-R36MS1R405_24A_20%

1 2

PR1712

4.7_1206_5%

PC1735

680P_0402_50V7K

2

D1

D2/S1

S24S2

S23G2

5

2

D1

D2/S1

S24S2

S23G2

5

1

1

2

PJ1701

@

JUMP_43X79

2

GPU1_B+

112

PL1703

@EMI@

5A Z120 25M 0805

12

12

PC1705

PC1706

10U_0805_25V6K

10U_0805_25V6K

1 2

Master GPU

1

+1.5V_VGAP
TDC 38.5A
Peak Current 55A
OCP current 66A
FSW=397kHz

+1.35VS_VGAP

1

1

+

PC1710

PC1709

2

560U_2.5V_M

12

12

PC1722

10U_0805_25V6K

12

+

PC1713

2

560U_2.5V_M

12

PC1731

22U_0603_6.3V6M

12

12

12

PC1716

PC1714

PC1715

22U_0603_6.3V6M

12

PC1732

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

FB_VDDQ_SENSE<45>

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

PJP1701

2

112

@JUMP_43X118

PJP1702

2

112

@JUMP_43X118

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1

1

+

+

+

PC1734

PC1733

2

2

2

470U_X_2VY_R9M

470U_X_2VY_R9M

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PWR_+1.5VRAM

PWR_+1.5VRAM

PWR_+1.5VRAM

SKL_H 42

1

PC1736

470U_X_2VY_R9M

+1.35VSDGPU+1.35VS_VGAP

1.0

1.0

89 103Monday, January 09, 2017

89 103Monday, January 09, 2017

89 103Monday, January 09, 2017

1.0

5

D D

EN pin don't floating

B+_FUSE

PF1

B+

+3VALW

12

PR1603

@

0_0402_5%

ILMT_1VGAP LDO_3V_1VGAP

12

PR1605

@

C C

0_0402_5%

The current limit is set to 8A ,12A ,16A, when this pin
is pull low, floating or pull high

21

7A_32V_S1206-H-7.0A

+1.0VS_VGAP_B+

PJ1601

@

JUMP_43X79

112

2

12

PC1605

PC1603

@

0.1U_0402_25V6

@EMI@

10U_0805_25V6K

12

EN_1VGAP
ILMT_1VGAP

+3VS

12

PC1611

10U_0805_25V6K

+3VALW

4

+3VS

PR1610
10K_0402_5%

1 2

PU1601

18
11
13
15

12

PC1613
1U_0402_6.3V6K

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND
GND
EN
ILMT
BYP

SY8288RAC_QFN20_3X3

9

PG

1

BS

LX_1VGAP

6

LX

19

LX

20

LX

FB_1VGAP

14

FB

17

VCC

10

NC

12

NC

16

NC

21

PAD

3

+1.0VS_VGA_PGOOD <41>

PR1601

1 2

BST_1VGAP_RBST_1VGAP

0_0603_5%

12

PC1612

2.2U_0402_6.3V6M

Pin 7 BYP is for CS.
Common NB can delete +3VALW and PC15

PC1604

0.1U_0603_25V7K

1 2

PR1602

@EMI@

4.7_1206_5%

SNB_1VGAP

1 2

(Common Part)
SH00000Z200

PL1601

1UH_6.6A_20%_5X5X3_M

1 2

FB = 0.6V

2

PC1602

@EMI@

680P_0603_50V7K

1 2

5X5X3
Isat:6.6A
DCR: 14mΩ (Max)

12

Rup

Rdown

12

PR1604

PC1606

21.5K_0402_1%

12

330P_0402_50V7K

PR1606

31.6K_0402_1%

Vout=0.6V* (1+Rup/Rdown)

=0.6*(1+(21.5K/31.6K))

1

+1.0VS_VGAP

12

12

12

12

PC1607

PC1608

PC1609

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

PC1610

22U_0603_6.3V6M

+1.0VS_VGAP

PJ1602

@

JUMP_43X118

112

2

+1.0VSDGPU

Vout=1.008V

PR1607

@

10K_0402_5%

PD1601

PC1614

0.022U_0402_25V7K

4

@

RB751V-40_SOD323-2

12

PD1602

@

RB751V-40_SOD323-2

12

PD1603

@

RB751V-40_SOD323-2

12

PR1608

10K_0402_5%

12

1.0VSDGPU_EN <38>

NVVDD2_PGOOD <41,87>

NVVDD1_PGOOD <41,84,87>

NVVDD2_EN <41,87>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

1 2

EN_1VGAP

12

PR1609

B B

A A

5

1M_0402_1%

12

Ipeak=3.6A
Imax=2.52A
Iocp=4.32A

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

PWR_+1.0VS_VGA

PWR_+1.0VS_VGA

PWR_+1.0VS_VGA

Document Number Rev

Document Number Rev

Document Number Rev

SKL_H 42

1

90 103Monday, January 09, 2017

90 103Monday, January 09, 2017

90 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

20K_0402_1%

12

@

GPU2_ISEN1
GPU2_ISEN2
GPU2_ISEN3
GPU2_ISEN4
GPU2_ISEN5

GPU2_PWM1

1 2

PR1869 0_0402_5%

12

PC1810

0.1U_0402_10V6K

PR1845

0_0402_5%

NVVDD1_S_ISUMP3<93>

12

PR1804

NTC2_La NTC2_Lb

470K_0402_5%_TSM0B474J4702RE

12

20K_0402_1%

PR18111_0402_1%
PR18121_0402_1%
PR18141_0402_1%
PR18151_0402_1%

1 2

PH1801

@

PR1827 2.2K_0402_1%

PR1829 2.2K_0402_1%
PR1830 2K_0402_1%
PR1832 2K_0402_1%

PR1833 100K_0402_5%

+5VCC_S

12

NVVDD1_S_PWM1 <92>

NVVDD1_S_PWM2 <92>

NVVDD1_S_PWM3 <93>

NVVDD1_S_PWM4 <93>

NVVDD1_S_ISUMP4<93>

12

PR1805

20K_0402_1%

12
12
12
12

12
12
12
12
12

1U_0402_6.3V6K

PC1816

NVVDD1_S_ISUMN1 <92>
NVVDD1_S_ISUMN2 <92>
NVVDD1_S_ISUMN3 <93>
NVVDD1_S_ISUMN4 <93>

layout 上 : 請 將 RSE N1 ~ 4
放 靠 近 C o n t r o l l e r.

NVVDD1_S_PH1
NVVDD1_S_PH2
NVVDD1_S_PH3
NVVDD1_S_PH4

+5VCC_S

PR1837 2.2_0603_1%

@

1 2

PR1858

1 2

layout 上 :
請 將 Tota l DC R sensin g 的compon en t
放 靠 近Control le r .

+5VS

12

PR1848

43K_0402_5%

PR1859

0_0402_5%

1 2

1 2

PR1854

@

36K_0402_5%

0_0402_5%

請 教 AU TO
PHASE的 設 定

PR1849

@

1 2

PR1860

0_0402_5%

1 2

Slave GPU

NVVDD1_S_PROG6

12

Fsw=300kHz

PR1834 0_0402_5%

PR1840

1 2

+5VS

10K_0402_5%

PR1850

@

1 2

10K_0402_5%

PR1861

0_0402_5%

1 2

33K_0402_5%

PR1851

@

1 2

PR1862

1 2

PR1852

1 2

51K_0402_5%

49.9K_0402_1%

PR1864

0_0402_5%

73.2K_0402_1%

1 2

NVVDD1_S_ISUMP1<92>

12

PC1802

PR1806

0_0402_5%

@

1 2

0.1U_0402_25V6

12

PR1808

15.8K_0402_1%

NVVDD1_S_PROG5

NVVDD1_S_PROG2

NVVDD1_S_PROG1

GPU2_CSPSUM

26

25

24

22

LLTH

APL223APL1

IMON

CSPSUM

GPU2_PWM3

GPU2_PWM4

0_0402_5%

0_0402_5%

PR1866

PR1867

1 2

1 2

@

@

@

1 2

PR1801
10K_0402_5%

12

PC1804

12

PR1818

2.4K_0402_1%

1 2

PU1801

31

FB

32

FBRTN

33

APL3

34

APL4

35

LPC

36

EN

37

PSI

38

PGOOD

39

VID

40

REFADJ

41

GND

GPU2_REFIN

12

PR1855

16.5K_0402_1%

12

PR1863

309_0402_1%

NVVDD1_S_FBRTN

NVVDD1_S_B+

12

PR1807

91K_0402_1%

0.1U_0402_25V6@

1 2

12

PR1817
0_0402_5%

12

12

PR1819

0_0402_5%

GPU2_SS

GPU2_VINMON

GPU2_EAP

GPU2_COMP

27

30

29

28

SS

EAP

COMP

VINMON

REFIN1VREF2FSW3PWM84PWM75PWM66PWM57PWM48PWM39PWM2

NVVDD1_S_PROG6

1 2

PC1818

0.01U_0402_16V

PC1801

0.1U_0402_25V6

D D

PC1803

0.01U_0402_16V7K

1 2

PR1816

0_0402_5%

1 2

PC1807

0.015U_0402_16V7K

PR1820

12

PR1822

0_0402_5%

NVVDD_VCC_SENSE_S<57>

+NVVDD1_S

C C

NVVDD_VSS_SENSE_S<57>

PR1871
0_0402_5%

1 2

PR1870

@

0_0402_1%

12

PR1841
0_0402_5%

12

PC1815

@

0.1U_0402_25V6

12

NVVDD1_EN_S<38,53>

+3VS

B B

NVVDD_PSI_S<53,94>

12

PR1824

12

100_0402_5%

PC1813

1 2

PR1828
0_0402_5%

12

12

PR1831

100_0402_5%

NVVDD1_S_FBRTN

+3VALW

PR1836
10K_0402_1%

1 2

34

D

PQ1801B

5

DMN53D0LDW-7 2N SOT363-6

+1.8VS

PR1838

@

PR1843

@

G

1 2

1 2

DMN53D0LDW-7 2N SOT363-6

S

0_0402_5%

0_0402_5%

2

G

PC1811

@

0.1U_0402_25V6

PC1814

@

PQ1801A

1 2

0.1U_0402_25V6

NVVDD1_S_PROG3
NVVDD1_S_PROG4

1 2

NVVDD1_S_LPC

0.1U_0402_25V6

61

D

S

1 2

+3VS

NVVDD1_PGOOD_S<53,94,97>

PR1839
30K_0402_1%

PR1844
10K_0402_5%

1 2

PR1826
0_0402_5%@

1 2

0_0402_5%

PC1812

@

1 2

0.1U_0402_25V6

1K_0402_1%

PR1835

1 2

0_0402_1%

PR1825

PR1842

PC1817

12

12

PR1823

@

12

GPU2_PSI

GPU2_VID
GPU2_REFADJ

R1

6.19K_0402_1%

PR1847

4.32K_0402_1%

R2

PR1865

20.5K_0402_1%

C

4700P_0402_25V7K

@

PC1809 0.1U_0402_25V6

0_0402_5%

1 2

R3

12

R4

R5

12

NVVDD1_S_ISUMP2<92>

12

PR1802

20K_0402_1%

NTC2_La NTC2_Lb

@

PR1809

1 2

0_0402_5%

1 2

PR1813 0_0402_5%@

1 2

PC1805 0.1U_0402_25V6@

1 2

PC1806 0.1U_0402_25V6@

1 2

PC1808 0.12U_0402_10V6K

PR1821

499_0402_1%

21

CSNSUM

ISEN1
ISEN2
ISEN3
ISEN4
ISEN5
ISEN6
ISEN7
ISEN8

5VCC

PWM1

10

UP9511PQGJ_VQFN40_5X5

PR1853 0_0402_5%

PR1856 0_0402_5%

GPU2_PWM2 GPU2_CSNSUM

PR1857 0_0402_5%

0_0402_5%

PR1868

1 2

12

PR1803

@

PR1810

1 2

0_0402_5%

20
19
18
17
16
15
14
13
12
11

12

12

12

PR1846

NVVDD_VID_S<53>

A A

5

1 2

0_0402_1%

PWMVID 的 RC BOM
請 根 據GPU's confi g 設定

4

NVVDD1_S_PROG1

NVVDD1_S_PROG2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

NVVDD1_S_PROG3

NVVDD1_S_PROG4

Cold Boot = 4-phase
Warm Boot = 4-phase

NVVDD1_S_LPC

NVVDD1_S_PROG5

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

+NVVDD SLAVE Controller

+NVVDD SLAVE Controller

+NVVDD SLAVE Controller

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C

C

C

C1PRG LA-E051P

C1PRG LA-E051P

C1PRG LA-E051P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

1.0

1.0

91 103Monday, January 09, 2017

91 103Monday, January 09, 2017

91 103Monday, January 09, 2017

1.0

5

4

3

2

1

Slave GPU

33U_D2_25VM_R40M

GPU2_B+

4
3

CSSN_B+_S<57>

NVVDD1_S_PWM1
NVVDD1_S_ZCD_EN#1

NVVDD1_S_BOOT1
NVVDD1_S_PHASE1

1

+

PC1910

2

@

100U_25V_NC_6.3X6

PU1901

1

PWM

CGND

2

ZCD_EN#

3

VCIN

DSBL#

4

CGND

THWn

5

BOOT

VDRV

6

NC

PGND

7

PHASE

8

VIN

9

VIN

10

PGND

11

SW

12

SW

13

SW
SW14SW

SIC632CDT1GE3_POWERPAK31_5X5

PR1901

1
2

0.005_2512_1%

CSSP_B+_S<57> CSSN_NVVDD_S<57>CSSP_NVVDD_S <57>

PC1903

1 2

1

1

+

+

PC1904

PC1916

PC1905

2

2

10U_0805_25V6K

33U_D2_25VM_R40M

+5VS

PR1903

@

PR1906

@

+GPU2_IN

0_0402_5%

1 2

+5VS

PC1902

1U_0603_16V7

12

0_0402_5%

1 2

12

12

12

PC1913

PC1908

0.1U_0402_25V6

EMI@

EMI@

2200P_0402_50V7K

D D

NVVDD1_S_PWM1<91>

NVVDD1_S_B+

C C

PC1914

12

10U_0805_25V6K

PJ1901@

112

JUMP_43X118

PJ1902

@

112

JUMP_43X79

PR1905
1K_0402_1%

12

PC1915

10U_0805_25V6K

2

2

12

PR1908

1 2

0_0402_1%

12

PC1909

10U_0805_25V6K

0.1U_0603_50V7K

GL

GL
SW
SW
SW
SW
SW
SW

1
2

0.005_2512_1%

28
27

NVVDD1_S_DSBL1

26
25

NVVDD1_S_VDRV1

24
23
22
21
20
19
18
17
16
15

PR1902

4
3

1 2

1U_0603_16V7

12

PR1909

@EMI@

2.2_0603_1%

@EMI@

PC1921

3300P_0805_50V7K

NVVDD1_S_B+

PR1904

10K_0402_1%

PR1907

2.2_0603_1%

PC1901

12

12

+5VS

12

GPU2_SNB1

NVVDD1_S_ISUMP1<91>

NVVDD1_S_ISUMN1<91>

NVVDD1_S_PH1

NVVDD1_S_PH1

13X13X4

sat:70A

I
DCR: 0.5mΩ (Max)

PL1901

1

4
3

2

0.22UH_MMD12DZNR22MEX_40A_20%

+NVVDD1_S

+5VS

PR1910

0_0402_5%

@

1 2

PR1911

NVVDD1_S_PWM2<91>

B B

NVVDD1_S_B+

A A

5

+5VS

1U_0603_16V7

12

PR1912

0_0402_5%

1 2

@

12

12

PC1928

PC1927

0.1U_0402_25V6

EMI@

EMI@

2200P_0402_50V7K

1K_0402_1%

12

PC1922

12

PC1929

PC1930

10U_0805_25V6K

PR1915

1 2

PC1923

0_0402_1%

1 2

0.1U_0603_50V7K

12

12

12

PC1932

PC1931

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

4

NVVDD1_S_PWM2
NVVDD1_S_ZCD_EN#2

NVVDD1_S_BOOT2
NVVDD1_S_PHASE2

PU1902

1

PWM

2

ZCD_EN#

3

VCIN

4

CGND

5

BOOT

6

NC

7

PHASE

8

VIN

9

VIN

10

PGND

11

SW

12

SW

13

SW
SW14SW

SIC632CDT1GE3_POWERPAK31_5X5

CGND
DSBL#

THWn

VDRV
PGND

28
27

GL

26
25
24
23
22

GL

21

SW

20

SW

19

SW

18

SW

17

SW

16

SW

15

NVVDD1_S_DSBL2
NVVDD1_S_VDRV2

@EMI@

3300P_0805_50V7K

3

+5VS

PR1913

1 2

10K_0402_1%

PR1914

2.2_0603_1%

12

PC1924

1U_0603_16V7

12

12

@EMI@

2.2_0603_1%

GPU2_SNB2

PC1942

12

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NVVDD1_S_PH2

NVVDD1_S_PH2

PR1916

NVVDD1_S_ISUMP2<91>

NVVDD1_S_ISUMN2<91>

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

13X13X4
Isat:70A
DCR: 0.5mΩ (Max)

PL1902

1

4
3

2

0.22UH_MMD12DZNR22MEX_40A_20%

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

PWR_SLAVE_+NVVDD

PWR_SLAVE_+NVVDD

PWR_SLAVE_+NVVDD

Document Number Rev

Document Number Rev

Document Number Rev

SKL_H 42

1

92 103Monday, January 09, 2017

92 103Monday, January 09, 2017

92 103Monday, January 09, 2017

+NVVDD1_S

1.0

1.0

1.0

5

4

3

2

1

Slave GPU

D D

NVVDD1_S_PWM3<91>

NVVDD1_S_B+

C C

NVVDD1_S_PWM4<91>

NVVDD1_S_B+

B B

+5VS

PR1917

1 2

10K_0402_1%

1U_0603_16V7

PC1943

PC1963

@EMI@

3300P_0805_50V7K

+5VS

PR1926

1 2

10K_0402_1%

PR1928

2.2_0603_1%

PC1966

1U_0603_16V7

PC1984

@EMI@

PR1921

2.2_0603_1%

12

@EMI@

GPU2_SNB3

12

12

PR1930

@EMI@

GPU2_SNB4

12

3300P_0805_50V7K

+5VS

12

PR1923

2.2_0603_1%

12

2.2_0603_1%

13X13X4

sat:70A

I

NVVDD1_S_PH3

NVVDD1_S_PH3

NVVDD1_S_ISUMP3<91>

NVVDD1_S_ISUMN3<91>

NVVDD1_S_PH4

NVVDD1_S_ISUMP4<91>

NVVDD1_S_ISUMN4<91>

DCR: 0.5mΩ (Max)

0.22UH_MMD12DZNR22MEX_40A_20%

NVVDD1_S_PH4

0.22UH_MMD12DZNR22MEX_40A_20%

PL1903

1

4
3

2

13X13X4
Isat:70A
DCR: 0.5mΩ (Max)

PL1904

1

4
3

2

+NVVDD1_S

+NVVDD1_S

PR1918

0_0402_5%

@

1 2

PR1919
1K_0402_1%

12

10U_0805_25V6K

12

10U_0805_25V6K

12

PC1952

10U_0805_25V6K

PR1925
1K_0402_1%

12

PC1973

10U_0805_25V6K

12

PR1922

1 2

0_0402_1%

12

PC1953

10U_0805_25V6K

12

PR1929

1 2

0_0402_1%

12

PC1974

10U_0805_25V6K

PC1945

1 2

0.1U_0603_50V7K

PC1965

1 2

0.1U_0603_50V7K

+5VS

PC1944

1U_0603_16V7

12

PR1920

0_0402_5%

1 2

@

12

PC1948

0.1U_0402_25V6

EMI@

+5VS

PR1924

@

1 2

PR1927

1 2

@

12

PC1969

0.1U_0402_25V6

EMI@

12

12

PC1949

PC1950

PC1951

10U_0805_25V6K

EMI@

2200P_0402_50V7K

0_0402_5%

+5VS

PC1964

1U_0603_16V7

12

0_0402_5%

12

12

PC1970

EMI@

PC1972

PC1971

10U_0805_25V6K

2200P_0402_50V7K

NVVDD1_S_PWM3
NVVDD1_S__ZCD_EN#3

NVVDD1_S_BOOT3
NVVDD1_S_PHASE3

NVVDD1_S_PWM4
NVVDD1_S_ZCD_EN#4

NVVDD1_S_BOOT4
NVVDD1_S_PHASE4

PU1903

1

PWM

2

ZCD_EN#

3

VCIN

4

CGND

5

BOOT

6

NC

7

PHASE

8

VIN

9

VIN

10

PGND

11

SW

12

SW

13

SW
SW14SW

SIC632CDT1GE3_POWERPAK31_5X5

PU1904

1

PWM

2

ZCD_EN#

3

VCIN

4

CGND

5

BOOT

6

NC

7

PHASE

8

VIN

9

VIN

10

PGND

11

SW

12

SW

13

SW
SW14SW

SIC632CDT1GE3_POWERPAK31_5X5

CGND

DSBL#

THWn

VDRV

PGND

CGND

DSBL#

THWn

VDRV

PGND

28
27

GL

26
25
24
23
22

GL

21

SW

20

SW

19

SW

18

SW

17

SW

16

SW

15

28
27

GL

26
25
24
23
22

GL

21

SW

20

SW

19

SW

18

SW

17

SW

16

SW

15

NVVDD1_S_DSBL3
NVVDD1_S_VDRV3

NVVDD1_S_DSBL4
NVVDD1_S_VDRV4

12

12

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

PWR_SLAVE+NVVDD

PWR_SLAVE+NVVDD

PWR_SLAVE+NVVDD

Document Number Rev

Document Number Rev

Document Number Rev

93 103Monday, January 09, 2017

93 103Monday, January 09, 2017

1

93 103Monday, January 09, 2017

1.0

1.0

1.0

5

Slave GPU

D D

PR2003

12

0_0402_5%

EN can't float

PR2004
100K_0402_1%

1 2

@

1 2

0.1U_0402_16V7K

NVVDD2_S_DGPU_PSI_R

PR2019

@

PR2009

1 2

0_0402_5%

12

PR2014

PC2156

NVVDD2_S_DGPU_VID_R

R1

12

PR2017

6.19K_0402_1%

12

NVVDD2_S_HG1
NVVDD2_S_EN_R

R3

NVVDD2_S_VREF_R

C

PR2027
0_0402_5%

1 2

PR2010

@

0_0402_5%

1 2

PR2012
10K_0402_1%

1 2

PR2007

@

0_0402_5%

1 2

@

1 2

0_0402_5%

NVVDDS_VID_S<53>

NVVDD2_EN_S<53,97>

NVVDD1_PGOOD_S

+3VS

+1.8VS

NVVDD_PSI_S<53,91>

C C

Avoid high dV/dt

B B

12

NVVDD2_S_BST1_R

1 2

NVVDD2_S_REFIN

4.32K_0402_1%

PC2040

@

1500P_0402_50V7K

NVVDD2_S_SW1

PC2010

0.22U_0603_25V7K

PR2005

2.2_0603_1%

NVVDD2_S_BST1

NVVDD2_S_VIDBUF

R4

12

PR2015

16.5K_0402_1%

NVVDD2_S_REFIN_R

R5

PR2021
309_0402_1%

1 2

PR2022

+5VS

R2

20.5K_0402_1%

4

12

PC2002

4.7U_0603_6.3V

NVVDD2_S_LG2NVVDD2_S_LG1

NVVDD2_S_SW2

PU2001

18

17

19

LG2

LG1

PH1

PVCC

COMP/OPT

VIDBUF6REFIN7VREF8FS9FBRTN

NVVDD2_S_FS

12

PC2029

1 2

0.01U_0402_16V

16

NCP81278MNTXG_QFN20_3X3

PH2

15

BST2

14

HG2

13

PGOOD

12
11

FB

10

PR2013

NVVDD2_S_FBRTN

39.2K_0402_1%

10K_0402_5%

PC2039

1000P_0402_25V

PR2023
0_0402_1%

1 2

20

1

BST1

2

HG1

3

EN

4

PSI

5

VID

GND

21

12

NVVDD2_S_VREF

PC2028

4700P_0402_25V7K

12

NVVDD2_S_BST2

NVVDD2_S_HG2

NVVDD2_S_COMP

NVVDD2_S_FB

NVVDD2_S_COMP_R

PR2018

12

NVVDD2_S_VCC_SENSE_R

12

NVVDD2_S_BST2_R

PR2001

2.2_0603_1%

1 2

1 2

PR2011

82.5K_0402_1%

PC2026
100P_0402_50V8J

1 2

1 2

PR2024
0_0402_1%

1 2

PC2001

0.22U_0603_25V7K

10K_0402_5%

PC2019
10P_0402_25V8J

1 2

PR2016

49.9_0603_1%

1 2

NVVDD2_S_FB_R

PC2038
47P_0402_50V8J

1 2

Avoid high dV/dt

3

+3VS

PR2006

1 2

NVVDD2_PGOOD_S <53,97>

12

PR2008

@

51.1K_0402_1%

Ipeak= 84A
Imax = 40A
Iocp = 100.8A

Place close to GPU

PR2025
100_0402_5%

12

12

PR2026
100_0402_5%

GPU2_B+

NVVDD2_S_HG1

NVVDD2_S_SW1

NVVDD2_S_LG1

NVVDD2_S_HG2

NVVDD2_S_SW2

NVVDD2_S_LG2

+NVVDD2_S

NVVDDS_VCC_SENSE_S <57>

NVVDDS_VSS_SENSE_S <57>

2

PJ2001@

2

112

JUMP_43X118

2

1

PQ2001

D1

G1

7

D2/S1

G2

5

6

1

G1

7

D2/S1

G2

5

6

7

S24S2

S2

3

AON6992_DFN5X6D-8-7

2

PQ2003

D1

S24S2

S2

3

AON6992_DFN5X6D-8-7

PR2002

1
2

0.005_2512_1%

CSSP_NVVDDS_S<57> CSSN_NVVDDS_S<57>

2

1

PQ2002

D1

G1

D2/S1

S24S2

S2

G2

5

3

6

7

1

D2/S1

6

2

PQ2004

D1

G1

S24S2

S2

G2

5

3

0.22UH_MMD-10DZ-R22MEX2L_35A_20%

4
3

10X10X4
I

sat:60A

DCR: 0.82mΩ (Max)

AON6992_DFN5X6D-8-7

PL2001

1 2

10X10X4
Isat:60A
DCR: 0.82mΩ (Max)

PL2002

0.22UH_MMD-10DZ-R22MEX2L_35A_20%

AON6992_DFN5X6D-8-7

1 2

12

12

PC2005

0.1U_0402_25V6

EMI@

PC2022

0.1U_0402_25V6

EMI@

12

PC2006

EMI@

2200P_0402_50V7K

12

PC2023

EMI@

2200P_0402_50V7K

12

PC2007

PC2008

10U_0805_25V6K

10U_0805_25V6K

NVVDD2_S_B+

12

12

12

PC2025

PC2024

10U_0805_25V6K

10U_0805_25V6K

PC2027

12

10U_0805_25V6K

+NVVDD2_S

1

NVVDD2_S_B+

1

+

PC2009

2

100U_25V_NC_6.3X6

+NVVDD2_S

12

PC2003

10U_0805_25V6K

Config

Vmax
Vboot

A A

R1
R2
R3
R4
R5
C

5

A

0.6Vmin

1.2

0.875
39K
39K

1.5K
30K

1.5K

1.5n

0.6

1.2

0.9
20K
20K
2K
18K
0

2.7n

B

C

0.65

1.15

0.9
39K

NVVDDS
TDC 28A
Peak Current 74A
OCP=89A

H/S Rds(on):6.7mohm ,8.5mohm
L/S Rds(on):1.8mohm ,2.3mohm

TYP MAX

30K
3K
24K
3K

1.8n

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

PWR_SLAVE_+NVVDDS

PWR_SLAVE_+NVVDDS

PWR_SLAVE_+NVVDDS

Document Number Rev

Document Number Rev

Document Number Rev

SKL_H 42

1

94 103Monday, January 09, 2017

94 103Monday, January 09, 2017

94 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

Slave GPU

D D

+NVVDD1_S

+NVVDD1_S
330uF X 8
47uF_0805 X 2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2042

PC2041

12

12

12

1U_0402_6.3V6K

PC2043

PC2044

12

12

1U_0402_6.3V6K

PC2045

12

1U_0402_6.3V6K

PC2046

PC2047

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2048

12

1U_0402_6.3V6K

PC2049

12

1U_0402_6.3V6K

PC2050

PC2051

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2052

12

1U_0402_6.3V6K

PC2053

PC2054

12

22uF_0603 X 4
10uF_0603X 11
1uF_0402 X 49

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2063

12

C C

12

12

B B

12

PC2064

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2085

PC2086

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2107

PC2108

12

12

10U_0603_6.3V6M

10U_0603_6.3V6M

PC2133

PC2146

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2066

PC2065

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2087

PC2088

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2109

PC2110

12

12

10U_0603_6.3V6M

10U_0603_6.3V6M

PC2147

PC2148

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2068

PC2067

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2089

PC2090

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2111

PC2112

12

12

10U_0603_6.3V6M

10U_0603_6.3V6M

PC2149

PC2150

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2070

PC2069

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2091

PC2092

12

12

22U_0805_6.3VAM

1U_0402_6.3V6K

PC2113

1

PC2114

2

10U_0603_6.3V6M

10U_0603_6.3V6M

PC2151

PC2152

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2071

12

1U_0402_6.3V6K

PC2093

12

22U_0805_6.3VAM

1

PC2115

2

10U_0603_6.3V6M

PC2153

12

1U_0402_6.3V6K

PC2072

PC2073

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2095

PC2094

12

12

22U_0805_6.3VAM

22U_0805_6.3VAM

1

1

2

10U_0603_6.3V6M

12

PC2117

PC2116

2

10U_0603_6.3V6M

PC2154

PC2155

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2074

12

1U_0402_6.3V6K

PC2096

12

47U_0805_6.3V6M

PC2118

12

1U_0402_6.3V6K

PC2075

PC2076

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2097

PC2098

12

47U_0805_6.3V6M

PC2119

+NVVDD2_S

+NVVDD2_S
330uF X 2
47uF_0805 X 1
10uF_0603 X 4

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2055

12

1U_0402_6.3V6K

PC2077

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2057

PC2056

12

12

1U_0402_6.3V6K

12

12

1U_0402_6.3V6K

PC2079

PC2078

12

12

10U_0603_6.3V6M

PC2101

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2059

PC2058

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2080

PC2081

12

10U_0603_6.3V6M

10U_0603_6.3V6M

PC2102

PC2103

12

1U_0402_6.3V6K

PC2060

12

12

12

PC2061

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

PC2083

PC2082

12

12

47U_0805_6.3V6M

10U_0603_6.3V6M

PC2104

1

PC2105

12

+

2

1uF_0402 X 16

1U_0402_6.3V6K

PC2062

1U_0402_6.3V6K

PC2084

330U_D2_2V_Y

330U_D2_2V_Y

1

PC2030

PC2011

+

2

1

1

1

+

+

PC2130

PC2129

2

2

330U_D1_2VY_R9M

A A

1

+

+

PC1955

2

330U_D1_2VY_R9M

5

PC1976

2

330U_D2_2V_Y

330U_D2_2V_Y

1

1

+

+

PC1934

PC1911

2

2

330U_D2_2V_Y

1

1

+

+

PC1912

PC1935

2

2

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2016/02/01 2017/12/31

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Date: Sheet o f

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

PWR_VGA DECOUPLING

PWR_VGA DECOUPLING

PWR_VGA DECOUPLING

C1PRG LA-E051P

C1PRG LA-E051P

C1PRG LA-E051P

95 103Monday, January 09, 2017

95 103Monday, January 09, 2017

95 103Monday, January 09, 2017

1

1.0

1.0

1.0

5

Slave GPU

D D

PC2315

TON_+1.35VS_VGAP_R_S

12

0.1U_0402_25V6

PR2303

B+_+1.5VS_VGAP2

+3VS

C C

1.35VSDGPU_EN_S<38,53>

PR2305

10K_0402_1%

+1.35VS_VGA_PGOOD_S<57>

12

PC2323

0.1U_0402_25V6

PC2324

0.033U_0402_25VK

Vboot=Vref*R2/(R1+R2+80)

B B

2.2_0402_1%

12

PR2308

12

20K_0402_1%

12

PR2310

Rref1

8.87K_0402_1%

12

12

Rref2

PR2313

20K_0402_1%

=2*20K/(8.87k+20K+80)

=1.382V

PR2304

383K_0402_1%

12

TON_+1.35VS_VGAP_S UG1_+1.35VS_VGAP_S

12

EN_+1.35VS_VGAP_S

12

PC2319

0.1U_0402_25V6

VREF_+1.35VS_VGAP_S

REFIN_+1.35VS_VGA_S

SS_+1.35VS_VGAP_S

12

PC2325

@

47P_0402_50V8J

PU2301

9

TON

13

PGOOD

3

EN

4

PSI

5

VID

8

VREF

7

REFIN

6

REFADJ

11

SS

21

GND

RT8812AGQW-GP

OPS

4

+5VALW

PR2301

2.2_0603_5%

1 2

PVCC_+1.35VS_VGAP_S

18

PVCC

UGATE1

BOOT1

PHASE1

LGATE1

UGATE2

BOOT2

PHASE2

LGATE2

VSNS

RGND

12

PC2301

2.2U_0603_16V6K

2

1

20

19

14

15

16

17

12

10

BOOT1_+1.35VS_VGAP_S

SW1_+1.35VS_VGAP_S

LG1_+1.35VS_VGAP_S

11.5K_0402_1%

UG2_+1.35VS_VGAP_S

BOOT2_+1.35VS_VGAP_S

SW2_+1.35VS_VGAP_S

LG2_+1.35VS_VGAP_S

RGND_s

PR2316

@

0_0402_5%

1 2

1 2

2.2_0603_5%

PR2307

2.2_0603_5%

PR2311
100_0402_5%

1 2

PR2317

@

0_0402_5%

PR2306

BOOT1_+1.35VS_VGAP_S_R

12

Rocset

12

PR2309

BOOT2_+1.35VS_VGAP_R_S

12

12

PC2326

0.1U_0402_25V6

PC2317

0.22U_0603_25V7K

12

PC2321

0.22U_0603_25V7K

12

3

B+_+1.5VS_VGAP2

12

12

12

PC2303

PC2302

PC2304

10U_0805_25V6K

0.1U_0402_25V6

@EMI@

EMI@

2200P_0402_50V7K

PQ2301

AON6992 2N DFN5X6D

0.36UH_PDME064T-R36MS1R405_24A_20%

7

1 2

12

@EMI@

4.7_1206_5%

SNB1_+1.5VS_VGAP2

12

@EMI@

680P_0402_50V7K

7X7X4
Isat:24A

AON6992 2N DFN5X6D

PQ2302

DCR: 1.47mΩ (Max)

7

12

@EMI@

4.7_1206_5%

SNB2_+1.5VS_VGAP2

12

@EMI@

680P_0402_50V7K

7X7X4
Isat:24A
DCR: 1.47mΩ (Max)

PL2301

PR2302

PC2318

PC2320

10U_0805_25V6K

PL2302

0.36UH_PDME064T-R36MS1R405_24A_20%

1 2

PR2312

PC2335

2

D1

D2/S1

S24S2

S23G2

5

2

D1

D2/S1

S24S2

S23G2

5

1

G1

6

1

G1

6

2

PJ2301

@

JUMP_43X79

2

112

PL2303

@EMI@

5A Z120 25M 0805

12

PC2305

10U_0805_25V6K

1 2

B+_+1.5VS_fuse

PF2

21

7A_32V_S1206-H-7.0A

GPU2_B+

+1.5V_VGAP_S
TDC 38.5A
Peak Current 55A
OCP current 66A
FSW=397kHz

1

+1.35VS_VGAP_S

1

1

+

+

PC2309

PC2308

2

2

560U_2.5V_M

560U_2.5V_M

12

12

PC2322

10U_0805_25V6K

12

12

12

PC2312

12

PC2458

22U_0603_6.3V6M

12

PC2314

PC2313

PC2316

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

12

PC2457

22U_0603_6.3V6M

22U_0603_6.3V6M

FB_VDDQ_SENSE_S<57>

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+1.35VS_VGAP_S

PJP2301

2

112

@JUMP_43X118

PJP2302

2

112

@JUMP_43X118

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

+

PC2459
470U_X_2VY_R9M

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PWR_+1.5VRAM

PWR_+1.5VRAM

PWR_+1.5VRAM

SKL_H 42

1

+1.35VSDGPU_S

96 103Monday, January 09, 2017

96 103Monday, January 09, 2017

96 103Monday, January 09, 2017

1.0

1.0

1.0

5

EN pin don't floating

PL2402

2

PC2446

EMI@

+1.0VS_VGAPS_B+

12

12

PC2454

0.1U_0402_25V6

2200P_0402_50V7K

@EMI@

PR2466
1M_0402_1%

PC2453

10U_0805_25V6K

EN_1VGAPS

12

12

EN_1VGAPS
ILMT_1VGAPS

D D

B+

+3VALW

12

PR2465

@

0_0402_5%

ILMT_1VGAPS LDO_3V_1VGAPS

12

PR2468

@

0_0402_5%

The current limit is set to 8A ,12A ,16A, when this pin
is pull low, floating or pull high

C C

PJ2402

@

112

JUMP_43X79

@EMI@

5A Z120 25M 0805

1 2

+3VALW

+3VS

10K_0402_5%

1 2

12

0.022U_0402_25V7K

PR2453

@

PC2449

4

2
3
4
5
7

8
18
11
13
15

12

PC2447
1U_0402_6.3V6K

PD2401

@

RB751V-40_SOD323-2

PD2402

@

RB751V-40_SOD323-2

PD2403

@

RB751V-40_SOD323-2

PR2475

10K_0402_5%

PU2405

IN
IN
IN
IN
GND
GND
GND
EN
ILMT
BYP

SY8286RAC_QFN20_3X3

12

12

12

12

+3VS

9

PG

1

BS

LX_1VGAPS

6

LX

19

LX

20

LX

FB_1VGAPS

14

FB

17

VCC

10

NC

12

NC

16

NC

21

PAD

1.0VSDGPU_EN_S <38>

NVVDD2_PGOOD_S <53,94>

NVVDD1_PGOOD_S <53,91,94>

NVVDD2_EN_S <53,94>

3

PR2464
10K_0402_5%

1 2

1 2

+1.0VS_VGA_PGOOD_S <53>

PR2470

BST_1VGAPS_RBST_1VGAPS

0_0603_5%

12

PC2443

2.2U_0402_6.3V6M

Pin 7 BYP is for CS.
Common NB can delete +3VALW and PC15

0.1U_0603_25V7K

PC2455

1 2

PR2472

@EMI@

4.7_1206_5%

1 2

(Common Part)
S

H00000Z200

PL2410

1UH_6.6A_20%_5X5X3_M

1 2

FB = 0.6V

SNB_1VGAPS

Rup

Rdown

2

PC2456

@EMI@

680P_0603_50V7K

1 2

5X5X3
Isat:6.6A
DCR: 14mΩ (Max)

12

PR2473

12

PR2467

31.6K_0402_1%

Vout=0.6V* (1+Rup/Rdown)

12

12

PC2451

21.5K_0402_1%

12

PC2444

PC2448

22U_0603_6.3V6M

330P_0402_50V7K

=0.6*(1+(21.5K/31.6K))

Vout=1.008V

Ipeak=3.6A
Imax=2.52A
Iocp=4.32A

1

+1.0VS_VGAP_S

12

12

PC2452

PC2450

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

PJ2303

@

JUMP_43X118

2

+1.0VS_VGAP_S

112

+1.0VSDGPU_S

B B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

PWR_+1.0VS_VGA

PWR_+1.0VS_VGA

PWR_+1.0VS_VGA

Document Number Rev

Document Number Rev

Document Number Rev

SKL_H 42

1

97 103Monday, January 09, 2017

97 103Monday, January 09, 2017

97 103Monday, January 09, 2017

1.0

1.0

1.0

5

Version Change L ist ( P. I. R. List )

Item

D D

10

11

12

14

15

16

17

18

19

C C

20

21

22

23

24

25

27

28

29

30

31

32

33

34

35

36

37

B B

38

39

40

41

42

43

44

45

46

47

48

49

50

A A

51

52

Tit lePag e#

non-POP

P72

1

P72

change

2

3

P73 non-PO P reduce inrush current PC114 cha nge to non-POP

4

P73 change keep AC_in2 voltage 3V

5

6

7

8

9

Add 7/20

P76
P76 change rise 5valw level to 5.1V

change 8/3P84

changeP87

deleteP89

P89 change rise 1.35V level to 1.38V

non-POP

P91

P94 change

P96 delete

changeP96 rise 1.35V level to 1.38V

P90 delete
P75 change

P87

change

P94 PR2007 pin1 change from NVVDDS_PSI_S to NVVDD_PSI_S

change

P90

change

non-POP PD2401、PD2403、PR245 3 chang e t o non- POPP97

P97

change
P84
P91

change PR1844 change to POP 10k_SD028100280 and pull high chan ge from +3VSDGPU_S to +3VS

Add267/28

P79
P89 PO P

changeP72

P84 change 8/2 Jims_Liu

change 8/2 Jims_L iu HW request change
P91

P84 change 8/3 Jims_Liu NV suggest
P84

P80 change 8/3 Jims_Liu

add

P78

add & delete

change Jims_Li u

P78

P76

change 8/4 Jims_L iu

change 8/4

P87
P94 8/4 Jims_Liu NV recommend

change

add

change 8/9 Jims_L iu FAE recommend
P87

P78 change

changeP75

change

P72

unpopP74

POP

P96

add & delete Jims_Liu

P78

P7253change

54

P78 change

55

P72

56

P73

57

popP73

Reque st

Date

Owne r

7/20

Jims_Liu

7/20

Jims_Liu

7/20

Jims_Liu

7/20

Jims_Liu
Jims_Liu

7/20

Jims_Liu
Jims_Liu

7/20

Jims_Liu

7/20

Jims_Liu

7/20

Jims_Liu

8/3

Jims_Liu

7/20

Jims_Liu

7/20

Jims_Liu

7/20

Jims_Liu

7/20

Jims_Liu

8/11

Jims_Liu

7/26

Jims_Liu
Jims_Liu

7/26

Jims_Liu

7/26
7/26

Jims_Liu

7/26

Jims_Liu

7/26

Jims_Liu

7/26

Jims_Liu

7/26

Jims_Liu
Jims_Liu for Transient test

7/28

Jims_Liu for Transient test
Jims_Liu8/2

8/3

Jims_Liu for FAN_12V ripple8/3P78

8/4 for FAN_12V ripple

Jims_Liu8/4chan ge

Jims_Liu

Jims_Liu8/4chan ge

8/11

Jims_Liu

8/11

Jims_Liu

8/11
8/12

7/28

8/19

8/24

Jims_Liu for one shot discharge

8/24

Jims_Liu for buyer

10/18a dd

Jims_Liu

10/18a dd
10/18

Jims_Liu for AC_in PC112 change to UNPOP

5

Issu e
Desc ript ion

AC_IN1 & AC_IN2
output level

SPOK pull high

for NVVDD1 ENable
sequenc e

for NVVDD2 response

not support OC

for NVVDD1_S ENable
sequenc e

for NVVDD2_S response PC2019 change from 0.01u to 10pF_SE00000F180

not support OC

DFB issue delete PC1601_2200pF_EMI
charger I limit

HW PSI pin co mbine
HW PSI pin co mbine
HW request

HW request
HW request
HW request
change sequencychange
change sequency

for ACOK signal quality PU102 pin8 & pin1 & pin7 VCC change from +5VALWP to +19V_ref

HW request change
Vth to 1.8V

Vth to 1.8V
mos SOAJims_L iu8/3changeP75

NV suggestJims_Liu8/3cha nge

change c ommon part PL701 change from 1uH_SH00000NW00 to 1uH_SH00000Z200

dynamic FAN_9VJims_L iu

change c ommon part

for buyerJims_Liu8/4changeP82

change c ommon part EMI bead PL101,PL102,PL103,PL104,PL105,PL106,PL107,PL108,PL109,PL110,PL201,PL202,PL203,PL2404 change from SM01000C000 to SM01000P200

NV recommend

FAE recommendJims_L iu8/4

FAE recommendJims_L iu8/9changeP87

for over shoot &
output ripple

change size &

common part

change voltage rat i ngJims_Liu

for Transient testJims_Liu

for FAN_12V ripple

for EMI
for AC_inJims_Liu

Solu tion
Desc ript ion

PD101 & PD104(SC400001200) change form POP to non-POP

PU102 pin8 VCC change from +5VS to +5VALWPfor one shot sequence

PR125 change from 0 to 100kohm_SD028100380
Add PR401_100kohm_SD028100380
PR402 change from 15k to 15.4kohm_SD034154280

PR1236 pull high voltage, change from +3VSDGPU to +3VALWP
PR1270 pull high voltage, change from +3VSDGPU to +3VS

PC1419 change from 0.01u to 10pF_SE00000F180
PC1425 change from 0.1u_0603 to 100pF_SE071101J80_0402
PC1428 change from 1500pF to 4700pF_SE075472K80

Delete PR1715, PC1736,PQ1703,PR1714
PR1710 change from 10k to 8.87k ohm_SD034887180

PR1713 change from 34.8k to 20k ohm_SD034200280

PR1836 pull high voltage, change from +3VSDGPU_S to +3VALW
PR1870 pull high voltage, change from +3VSDGPU_S to +3VS

PC2026 change from 0.1u_0603 to 100pF_SE071101J80_0402
PC2028 change from 1500pF to 4700pF_SE075472K80

Delete PR2315, PC2336,PQ2303,PR2314
PR2310 change from 10k to 8.87k ohm_SD034887180

PR2313 change from 34.8k to 20k ohm_SD034200280

PR314 change from 20k_SD034200280 to 392k_SD034392380
PR316 change from 2k_SD034200180 to 25.5k_SD034255280
PR315 c hange from 52.3k_SD034523280 to 715k_SD034715380
PR1407 pin1 change from NVVDDS_PSI to NVVDD_PSI

PD1601、P D1603、 PR160 7 c hang e t o non- POPnon-POPP90

PR1608 change to POP 10k_SD028100280

PR2475 change to POP 10k_SD028100280

PR1244 change to POP 10k_SD028100280 and pull high change from +3VSDGPU to +3VS

Add PC2208_22uF_SE00000M000
PC1710_560uF_SF000002P00 change to POP

PR124 & PR118 change from 1.5M to 16.9k_SD034169280

PQ301 & PQ304 change from AON6426_SB000017B00 to MDU1512_SB00000SY00
PC1217 c hange from 1500p_SE074152K80 to 4700p_SE075472K80
PC1817 c hange from 1500p_SE074152K80 to 4700p_SE075472K80

add PR2447 280k_SD034280380, PQ2411 2N7002_SB00000ST00
delete PC2435_33u_SGA00007I00, add PC2439 & PC2475 & PC2438_22u_SE00000GB5Q

PC2436 change from 47PF to 1000P_SE00000H180
PR2435 change from 56.2k to 19.6k_SD000003580

PC407 & PC409 & PC410 change from 330u_SF000001G00 to 330u_SF000006B00

PC928,PC929,PC930,PC1309,PC1424,PC1910,PC2009,P change from 100u_SF000005100 to 100u_SF000007100change c ommon part

PL901,PL903,PL904,PL906 change from 0.22u_SH00000NM00 to 0.22u_SH00000QZ00

PR1425 PR1426 change from 10ohm_SD028100A80 to 100ohm_SD028100080

PR2025 PR2026 change from 10ohm_SD028100A80 to 100ohm_SD028100080

add PJ507, PJ508, PL2412,PC2474P77

PC1440 1500pF_SE074152K80 change to UNPOP
PR1421 change from 330ohm_SD028330080 to 309ohm_SD000017700

PC2040 1500pF_SE074152K80 change to UNPOP
PR2021 change from 330ohm_SD028330080 to 309ohm_SD000017700

PC2428 c hange from 0.1u_SE00000G880 to 0.47u_SE000002F80
PC2425 change from 100u_SGA00006B00 to 22u_SE00000GB5Q
Add PC2421 & PC2422 22u_SE00000GB5Q

PL301 change from 10x10 4.7uH_SH00000HR00 to 7x7 4.7uH_ SH00000YC00

PC109 & PC110 change from 0.022u_16V_SE076223K80 to 0.022u_25V_SE075223K80

PH202 & PH202 change to unpopthermal requirementJims_Liu

PC1710_560uF_SF000002P00 change to POP

PC2421, PC2422, PC2425, PC2438, PC2439, PC2475 change from SE00000GB5Q to SE00000GB00

PR116 & PR117 change from 47k_SD034470280 to 470k_SD034470380
PR118 & PR124 change from 16.9k_SD034169280 to 169k_SD034169380
PC109 & PC110 change from 0.022u_SE075223K80 to 0.22u_SE000015W00
PC2436 change from 1000pF_50V_SE00000H180 to 1000p_SE068102J80_25V

Add PC120, PC121, PC122, PC123 0.1uF_SE042104K80
Add PC124 0.1uF_SE00000G880_unpop

PQ116 change to B2B.

4

Page 1

4

Rev.

PQ1201 change from 2N7002_SB00000EO00 to DMN53D_SB000018X00

PQ1801 change from 2N7002_SB00000EO00 to DMN53D_SB000018X00

3

3

2

2

1

Title

Title

Title

<Title>

<Title>

<Title>

Size

Size

Size

Document Number Re v

Document Number Rev

Document Number Rev
<Doc> 1.0

E

<Doc> 1.0

E

<Doc> 1.0

E

Date: Sheet o f

Date: Sheet of

Date: Sheet of

1

98 103Monday, January 09, 2017

98 103Monday, January 09, 2017

98 103Monday, January 09, 2017

5

Version Change List ( P. I. R.
List )

Item

58

59

60

61

62

63

64

D D

65

66

67

68

69

70
71
72

73

74

75

76

C C

77

78

79

80

81

82

83

84

B B

85

86

Tit lePag e# Date

P73 change Jims_Liu for AC_in

changeP73
change

P85 change

add

P85

change

P92

add

P92
P73 Jims_Liu
P73 ac_in signalJims_Liu

add 10/28

P90

add 10/31

P90

add 10/31

P80

add 11/01

P89

add

P96

add 11/03

P96

change
change PU104 change to unpopfor debugJims_L iu

P73

change

change & add 12/ 8

P87

P94

change & add 12/ 13 for NVVDD2 drop PR1409 change from 5.1k_SD034510180 to 0 ohm_SD028000080

P87

P94

P89

add 12/13

P96

change

P73

P75 change

changeP72

changeP73

changeP79

Reque st
Owne r

10/18
10/18

Jims_Liu

10/18

Jims_Liu
Jims_Liu

10/21

Jims_Liu

10/21

Jims_Liu

10/21

Jims_Liu

10/21add
10/21add

Jims_Liu for crash risk

Jims_Liu avoid burn
Jims_Liu
Jims_Liu for Remote sense

11/01

Jims_Liu avoid burn

11/03

Jims_Liu

11/16

Jims_LiuP74
Jims_Liu

12/8change & add PR2009 change from 0 ohm_SD028000080 to 5.1k_SD034510180

Jims_Liu

Jims_Liu

12/13change & add

Jims_Liu

Jims_Liu

12/22

Jims_Liu for AC_in2 signal PC112 chang to pop

12/22

Jims_Liu

01/06

Jims_Liu avoid s pike voltage

01/06

01/06

Jims_Liu

01/06

Issu e
Desc ript ion

for inrush current
HW requestP76

change & non-pop10 /21

for DFX

change & non-pop

for DFX
ac_in signal debug

for +19V_VIN shape

for Remote senseJims_Li u

for prochot 140%
for NVVDD2 drop PR1409 change from 0 ohm_SD028000080 to 5.1k_SD034510180

for NVVDD2_S drop

for NVVDD2_S drop

for VRAM

for B2B damage PQ301,PQ303,PQ304,PQ305 change from mdu1512_SB00000SY00 to EMB04N03H_SB00001C500

ac_in1 signalJims_Liu

cap rat i ng vol tage changeP78
change to AP partJims_Liu

Solu tion
Desc ript ion

PQ111 change from AO4423L_SB00000N100 to AON6403_SB00001F700
PQ303 & PQ305 change from AON6426_SB000017B00 to MDU1512_SB00000SY00
PR402 c hange from 15.4K_SD034154280 to 16k_SD00000G080

PC1309 placement from NVVDD1_B+ to B+, change to non-pop

add input cap PC1305 & PC1306 33u_D2_SGA00008V00

PC1910 placement from NVVDD1_S_B+ to GPU2_B+, change to non-pop

add input cap PC1904 & PC1905 33u_D2_SGA00008V00

add PJ101,PJ102,PJ103

add PQ117 S LMUN5113T1G PNP SOT323-3_SB000013X00
PQ118 2N7002kDW_SB00000EO00
PU104 L M393DG_SO8_SA003930010
PR154,PR155,PR156,PR157,PR159 100k_SD034100380
PR158 4.7k_SD034470180
PC119 2200P_SE074222K80
PC125 1u_SE000010V00
PC126 0.47u_SE000002F80
PC127 0.047u_SE00000MJ00

add pc1611 10U_SE00000QK00
PC1605 10U_SE00000QK00 change to unpop
Delete P L1602 EMI bead SM01000P200
add PF1_SP040003Q00

delete PL702_SM01000P200

add pr1716, pr1717 SD028000080 R short
add pr2316, pr2317 SD028000080 R short
add PF2_SP040003Q00

PC510,PC1709,PC1710,PC2308,PC2309 change from 560u_SF000002P00 to 560u_SF000006300for EL part

P208 c hange from 110K_SD034110380 to 95.3K_SD03495328011/16

Add PR1428 & PR1429 10k_SD034100280

Add PR2028 & PR2029 10k_SD034100280

Add unpop PR1412 &PR1410 0 ohm_SD028000080
Add PR1428 10k_SD034100280
unpop PR1407

PR2009 change from 5.1k_SD034510180 to 0 ohm_SD028000080
Add unpop PR2010 & PR2019 0 ohm_SD028000080
Add PR2012 10k_SD034100280
unpop PR2007

Add PC1733, PC1734, PC1736 & PC2459 470UF_SGA00003N00

PC126 change from 0.47u_SE000002F80 to 1u_SE00000OU00
pu104 change from L M393_SA003930010 to LM358_SA00000QO00
PQ116 change to pop

PC120,PC121,PC122,PC123 change from 0.1uF_SE042104K80 to 1000pF_SE024102J80
PR145 change from 0ohm to 2.2ohm_SD00000J180

PC125 change from 1u_SE000010V00 to 0.47u_SE00000WA00
PR159 change from 100k_SD034100380 to 20k_SD034200280
PC2428 c hange from 0.47u_SE000002F80 to 0.47u_SE00000WA00

PC2213 change from 1u_SE120105K80 to 1u_SE00000G900

Pag e
2

4

3

2

1

Rev.

A A

Title

Title

57

5

4

3

2

Title

<Title>

<Title>

<Title>

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev
<Doc> 1.0

E

<Doc> 1.0

E

<Doc> 1.0

E

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

99 103Monday, January 09, 2017

99 103Monday, January 09, 2017

99 103Monday, January 09, 2017

A

Version change list (P.I.R. List)

B

C

D

E

Page 1 of 4 for HW

Item Page PhaseSolution DescriptionTitle

Date

Issue Description

Rev.

1. Remove PWR_SUSP_LED#/ BATT_AMB_LED#/ BATT_AMB_LED#/ PWR_LED

1

1 1

32,38 7/11

EC

USB2 32 7/11

3 2 2

234 RTC BATT use non-chargeable type. 1. Add RH163, change DH2 PN.

PCH

PCH

7/11 Leakage issue. 1. unpop RH143.

7/11

Change LED design and update EC GPIO. DVT

TI USB3.0 re-driver no funct i on.

from U28, add EC_SMB_CK3/ EC_SMB_DA3 for 2nd 59116 on USB/B.

2. Add SATA_LED# to pin93,move BT_ON to pin108,
move FW_GPIO to pin 90.

1. Del USB3.0 re-driver circuit.
U10,C443~C446,R3,R118~R120,R407,R408.

DVT

DVT

DVT

0.2

0.2

0.2

0.2

1. unpop RG780, pop RG779.

2. unpop RG515/RG784, pop RG783.

3. unpop RG789, pop RG792, change RG768 to 20k.

4. unpop RG782, pop RG781.

5. unpop RG604/RG786, pop RG785.

DVT

0.2

53,57

GPU

7/115 41,45,

Change GPU power sequence by HW control.

6. unpop RG791, pop RG793, change RG770 to 20k.

1. JSPK1/JSPK2 change to 8 pin conn SP020010D00.

2. JDMIC1 change to SP020008V00 (pitch change to 1mm).

6 27,32,

2 2

35,36

CONN 7/18

ME change connector.

3. JHDD1 change to SP010022I00.

4. JFANBL change to SP020008R00.

5. JPWRB & JBTN change to SP02000IT00.

DVT

0.2

6. JUSB2 change to SP01001BY00.

7. JUSB3 change to SP01001I300.

7

49~52,
61~64

9 25 Change jump size.

3810

3 3

GPU

Jump

EC

PCH

7/18

Change VRAM MEM_VREF MOS PN. 1. QG2~4/QG8/QG513~516 change to SB000010N00.

FAN power rail. 1. Change JFAN3 power from 12V to 5V.8 39 FA N 7/19

7/19 1. Change J15/J16 from 43*79 to 43*118.

7/19

7/19Camera3411

7/1912 19,22

EC debug.

TI USB3.0 re-driver no funct i on.

EC_SCI# change GPIO pin.

1. Del T71~T74, replace by R799,R800.

1. Del USB3.0 re-driver circuit.
U44,C393~C396,C409~C411,R360~R366,R116,R117.

1. Move EC_SCI# from GPP_G3 to GPP_B20.

Symbol pin def i ne. 1. JFANBL pin reverse for new conn def i ne.13 CONN 7/2235

1. Reserve RA81, add RA82 for SPDIF_OUT.Reserve SPDIF_OUT.7/22Codec3614

DVT

DVT

DVT

DVT

DVT

DVT

DVT

DVT

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

1. Change YH1 to SJ10000Q400.

7/22Crystal21,6815

2016 1. unpop CH67.

PCH

Crystal EA.

Follow design guide.7/22

2. Change CH13 to 8.2pF/ CH14 to 6.8pF.

3. Change C293/C294 to 10pF.

17 31 M.2 7/22 UART debug. 1. Pop R64,R65.

EC

1. Change R193 to 12k, pop R191.3818 Board ID.7/22

1. Reverse JUSB3, JDMIC1, swap JSPK1 pin.Symbol pin def i ne.32,35,3619 7/25CONN

GPU

1. Add netname for MIO.Add netname for MIO.48,602 0 7/25

1. JCAM2 pin6 connect to +3VS.21 3 4 Correct netname.CONN 7/25

DVT

DVT

DVT

DVT

DVT

DVT

DVT

0.2

0.2

0.2

0.2

0.2

0.2

0.2

1. Change UG10,UG23 to SA00003R000.

2. Remove RG520,RG521,RG503,RG523,RG556,RG531.

4 4

57,60,66

41,45,53,

22

GPU

Sequence f i ne tune, ri ppl e i ssue, c orr ect connect i on.7/26

3. Add UG101,CG916,RG797,UG102,CG919,RG798,DG23,RG795,DG24,RG796.

4. Reserve CG917,CG918,CG920,CG921.

5. Pop RG787,RG790.

DVT

0.2

6. Depop UG99,CG910,CG911,RG771,UG100,CG912,CG913,RG772.

7. Change RG4,RG526 to 0402 size.

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2015/10/02 2016/11/10

2015/10/02 2016/11/10

2015/10/02 2016/11/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PIR-HW1

PIR-HW1

PIR-HW1

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

C1PRG LA-E051P

C1PRG LA-E051P

C1PRG LA-E051P

Date : Sheet of

Date : Sheet of

D

Date : Sheet of

E

100 103Monday, January 09, 2017

100 103Monday, January 09, 2017

100 103Monday, January 09, 2017

1.0

1.0

1.0