Compal LA-E051P Schematics Rev1.0

A

1 1

B

C

D

E

Compal Confidential

C1PR2 MB Schematic Document

2 2

LA-E051P

(Eagle 21")

Rev: 1.0

3 3

ZZZ

DA@

4 4

PCB 1SJ LA-E051P REV1 MB

DAC00006010

A

B

2017-01-09

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Cover Sheet

Cover Sheet

Cover Sheet

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1 103Monday, January 09, 2017

1 103Monday, January 09, 2017

1 103Monday, January 09, 2017

E

1.0

1.0

1.0

A

eDP

eDP Panel
Conn.

1 1

HDMI 2.0
Conn.

Display Port
Conn. x2

TYPE-C

2 2

3 3

Conn.

4 lane

page 65

HDMI
4 lane

page 66

DP
4 lane x 2

page 67

DP/USB3.1 Gen2

page 70

DP/USB3.1

M.2 WLAN
Dual Band

page 31

802.11 ac/agn

PCIe x4 PCIe x4

DDI

Nvidia N17E-G3

with GDDR5X*8

page 41~52

Nvidia N17E-G3

with GDDR5X*8

page 53~64

PCIe x1PCIe x2

LAN(GbE)

Killer Ethernet

E2500

page 30

RJ45

Conn.

page 30

M.2 SSDM.2 SSDM.2 SSD

page 28 page 28 page 29 page 29 page 27

SUB/B

USB 3.0/B

IO/B

4 4

PWR BTN/B

Marco Key/B

page 32

page 32 page 33

page 35

page 35

FAN LED/B

page 35

POGO/B

Light Bar Left/B

Light Bar Right/B

LOGO LED/B

A

page 35

page 35

page 35

RTC CKT.

Power On/Off CKT.

DC/DC Interface CKT.

Power Circuit DC/DC

page 23

page 41

page 25~26

page 72~97

MIO

DP
4 lane

Thunderbolt
AR4C

Power delivery

TPS65982

SATA3.0 SATA3.0SATA3.0 SATA3.0

B

SLI

Master GPU

Slave GPU

page 68,69

page 70

Card Reader

RTS5227

SD Conn.(IO/B)

B

PEG X8 (0~7)
8GT/s

PEG X8 (8~15)
8GT/s

PCIe x4

PCIe x1

page 32

SATA HDDM.2 SSD

Conn.Conn.Conn.Conn.Conn.

Cable Type

SATA3.0

6.0 Gb/s

SATA3.0

Kabylake H PROCESSOR

BGA1440

(42X28) (KBL-H_4+2)

Processor

PCIe

PCIe

Kabylake PCH - H
FCBGA(23X23)

837pin FCBGA

PCIe

LPC/eSPI BUS

CLK=24MHz

ENE

KB9022

page 38

C

Fan Control x5

Memory BUS

Dual Channel

1.2V DDR4 1866/2133

page 06~13

X4 DMI

USB Bus

CM238

HD Audio

3.3V 24MHz

page 08~24

SPI

SPI ROM

16M

page 19

TPM

page 40 page 40

C

G-Sensor
LIS3DHTR

D

page 39

260pin DDR4-SO-DIMM X2

260pin DDR4-SO-DIMM X2

USB3.0 USB3.0

page 32 page 32 page 32 page 32

USB3.0 USB3.0 USB3.0 USB3.0

FHD CAM Eye Tracker

Conn. Conn.

USB2.0 USB2.0 USB2.0

HDA Codec Speaker, Woofer

ALC299

page 36 page 37 page 36,37

USB3.0

Conn.(IO/B)Conn.(IO/B)

Conn.(USB/B)

Touch Screen

page 34page 65 page 65 page 33 page 33 page 31

USB/I2C

Ext Amp.

ALC1006

Head Phone

Amp.

MIC Jack

Conn.

SSSeeecccuuurrriiitttyyy CCClllaaassssssiiifffiiicccaaatttiiiooon

TTTHHHIIISSS SSSHHHEEEEEETTT OOOFFF EEENNNGGGIIINNNEEEEEERRRIIINNNGGG DDDRRRAAAWWWIIINNNGGG IIISSS TTTHHHEEE PPPRRROOOPPPRRRIIIEEETTTAAARRRYYY PPPRRROOOPPPEEERRRTTTYYY OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... AAANNNDDD CCCOOONNNTTTAAAIIINNNSSS CCCOOONNNFFFIIIDDDEEENNNTTTIIIAAALLL
AAANNNDDD TTTRRRAAADDDEEE SSSEEECCCRRREEETTT IIINNNFFFOOORRRMMMAAATTTIIIOOONNN...TTTHHHIIISSS SSSHHHEEEEEETTT MMMAAAYYY NNNOOOTTT BBBEEE TTTRRRAAANNNSSSFFFEEERRREEEDDD FFFRRROOOMMM TTTHHHEEE CCCUUUSSSTTTOOODDDYYY OOOFFF TTTHHHEEE CCCOOOMMMPPPEEETTTEEENNNTTT DDDIIIVVVIIISSSIIIOOONNN OOOFFF RRR&&&DDD
DDDEEEPPPAAARRRTTTMMMEEENNNTTT EEEXXXCCCEEEPPPTTT AAASSS AAAUUUTTTHHHOOORRRIIIZZZEEEDDD BBBYYY CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,,IIINNNCCC... NNNEEEIIITTTHHHEEERRR TTTHHHIIISSS SSSHHHEEEEEETTT NNNOOORRR TTTHHHEEE IIINNNFFFOOORRRMMMAAATTTIIIOOONNN IIITTT CCCOOONNNTTTAAAIIINNNSSS
MMMAAAYYY BBBEEEUUUSSSEEEDDD BBBYYY OOORRR DDDIIISSSCCCLLLOOOSSSEEEDDD TTTOOO AAANNNYYY TTTHHHIIIRRRDDD PPPAAARRRTTTYYY WWW IIITTTHHHOOOUUUTTT PPPRRRIIIOOORRR WWWRRRIIITTTTTTEEENNN CCCOOONNNSSSEEENNNTTT OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, III NNNCCC...

IIIssussussueeeddd DDDaaattteee

nn

222000111666///000222///000111 222000111777///111222///333111

CCCooommmpppaaalll SSSeeecccrrreeettt DDDaaatttaaa

D

USB2.0

Conn.

Head Phone

Jack
Conn.

ON IO/B

DDDeeecicicippphhheeerrreeeddd DDDaaattteee

page 14,15

page 16,17

Offline USB Charger

USB3.0

Conn.(USB/B)

Key Board

page 32

E

POGO

Conn.Conn.

Touch Pad

USB2.0 USB2.0

CCCooompmpmpaaalll EEEllleeeccctttrororonnniiicccs,s,s, InInInccc...

TTTiiitttllleee

SSSiiizzzeee DDDooocucucumememennnttt NNNuuumbmbmb eeerrr RRReeevvv

CCCuuussstttooo mmm

DDDaaattt eee::: SSShhheeeeeettt ooo fff

BlBlBloooccckkk DDDiiiaaagggrrraaammmsss

C1C1C1PPPR2R2R2 LLLA-A-A-E0E0E0555111PPP

E

M.2

Blue Tooth

111...000

222 111000333MMMooonnndddaaayyy,,, JJJaaannnuuuaaarrryyy 000999,,, 222000111777

A

B

C

D

E

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

1 1

2 2

I2C Address Table

I2C_0 (+3VS) N/C

I2C_1 (+3VALW)

3 3

100K +/- 5%Ra

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

0
12K +/- 1% 0.347 V 0.345 V 0.360 V
15K +/- 1%
20K +/- 1%
27K +/- 1%
33K +/- 1%
43K +/- 1%
56K +/- 1%
75K +/- 1%
100K +/- 1%
130K +/- 1%
160K +/- 1%
200K +/- 1%
240K +/- 1%
270K +/- 1%
330K +/- 1%
430K +/- 1%
560K +/- 1%
750K +/- 1%

NC

BUS

Rb V min

BID

0.423 V 0.430 V 0.438 V

1.398 V

1.634 V

1.849 V

2.015 V

2.185 V

2.316 V

2.395 V

2.521 V

2.667 V

2.791 V

2.905 V

3.000 V

Device

V typ

BID

0.000 V

1.414 V

1.650 V

1.865 V

2.031 V

2.200 V

2.329 V

2.408 V

2.533 V

2.677 V

2.800 V

2.912 V

3.000 V

Address(7 bit)

N/C
DIMM1

PCH_SMBCLK

(+3VS)

EC_SMB_CK1
(+3VLP)

EC_SMB_CK3
(+3VALW)

EC_SMB_CK2

(+3VS)

DIMM2
DIMM3
DIMM4
LIS3DHTR(G-sensor)
BQ24780 (Charger IC)

BATTERY PACK
PD(TPS65982)

9116 (LED driver, M/B)

5
59116 (LED driver, USB/B)

N17E-G3 (Master)
N17E-G3 (Slave)

0x30
0x12
0x16
0x00
0xC0
0xC2
0x9E

0x9C
AMP for SPK(ALC1006) 0x24
AMP for Woofer(ALC1006) 0x26
HP AMP (SV3S700)

External Thermal Sensor

0xE4

0x4D

V

max

BID

0.300 V

1.430 V

1.667 V

1.881 V

2.046 V

2.215 V

2.343 V

2.421 V

2.544 V

2.687 V

2.808 V

2.919 V

Address(8bit)

Write Read

EC AD

0x00 - 0x13
0x14 - 0x1E
0x1F - 0x25
0x26 - 0x300.541 V 0.550 V 0.559 V
0x31 - 0x3A0.691 V 0.702 V 0.713 V
0x3B - 0x450.807 V 0.819 V 0.831 V
0x46 - 0x540.978 V 0.992 V 1.006 V
0x55 - 0x641.169 V 1.185 V 1.200 V
0x65 - 0x76
0x77 - 0x87
0x88 - 0x96
0x97 - 0xA4
0xA5 - 0xAF
0xB0 - 0xB7
0xB8 - 0xBF
0xC0 - 0xC9
0xCA - 0xD4
0xD5 - 0xDD
0xDE - 0xF0
0xF1 - 0xFF

43 level BOM table

431A54BOL01
431A54BOL02 SMT MB AE051 C1PR2 G3 QL3X 2.4G HDMI
431A54BOL03 SMT MB AE051 C1PR2 G3 QLM4 2.9G HDMI QLM4@/QLF5@/CAM@/TBT@/TOBII@/CMC@/DA@
431A54BOL04 SMT MB AE051 C1PR2 I7-7820HK 2.9G HDMI SR32P@/SR30U@/CAM@/TBT@/TOBII@/CMC@/DA@

SMT MB AE051 C1PR2 G3 QL2X 2.7G HDMI QL2X@/QJGE@/CAM@/TBT@/TOBII@/CMC@/DA@

QL3X@/QJGE@/CAM@/TBT@/TOBII@/CMC@/DA@

BOM Structure43 Level Description

Power State

STATE

S0 (Full ON) ON ON ON ONHIGH HIGH HIGH

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

LOW HIGH

BOM Structure Table

BOM Option Table

Item BOM Structure

Unpop @

Connector

EMC requirement depop

For EYE Tracker TOBII@
For Alpine Ridge TBT@
For HD camera power

For Intel CMC debug

TPM TPM@
For G-Sensor GSEN@

ESPI MODE for EC ESPI@
For PCB DA PN
HDMI logo P/N
For PCH

For CPU

CONN@
EMC@EMC requirement
XEMC@

CAM@

CMC@

DA@
45@
QJGE@,QLF5@,

SR30U@

QL3X@,QL2X@
QLM4@,SR32P@

ONONON

HIGH

LOWLOW

HIGH

OFF

ON

OFFLOW LOW LOW

OFF

OFF

OFF

OFF

OFF

OFF

Voltage Rails

Power Plane

+RTCVCC

+19V_VIN

+17.4V_BATT Battery power supply
+19VB

+3VLP
+5VALW
+3VALW System +3VALW always on power rail
+3VALW_DSW +3VALW power for PCH DSW rails
+3VALW_PCH_PRIM
+3VALW_SPI
+1.0VALW +1.0V Always power rail

+1.0V_VCCST

+5VS System +5V power rail
+3VS

+1.0VS_VCCSTG +1.0VALW_PRIM Gated version of VCCST
+0.6VS_VTT DDR +0.675VS power rail for DDR terminator .

+VCC_CORE
+VCC_GT
+VCCIO

+VCC_SA

+3VSDGPU
+1.8VSDGPU_AON

+NVVDD1
+NVVDD2

+1.35VSDGPU +1.5VS power rail for GPU

+1.0VSDGPU

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Description
RTC Battery Power
Adapter power supply

AC or battery power rail for power circuit.
+19VB to +3VLP power rail for suspend power

+5V Always power rail

+3VALW power for PCH power rails

+3VALW_PRIM supply for the SPI IO

DDR IV +1.2V power rail+1.2V_VDDQ
Sustain voltage for processor in Standby modes

System +3V power rail

Core voltage for CPU
Sliced graphics power rail
CPU IO power rail

System Agent power rail

+3VS power rail for GPU circuit
+1.8VALW power rail for GPU(AON rails)
+1.8VS power rail for GPU GC6+1.8VSDGPU_MAIN
Core voltage for VGA
Core voltage for VGA

+1.05VS power rail for GPU

NV name COMPAL name

NVVDD

FDVDD
FBVDDQ

VPP

IFP_IOVDD
IFPx_PLLVDD
PEX_DVDD

/

PEX_HVDD

PEX_PLL_HVDD
FBx_PLL_AVDD
GPCPLL_AVDDx/Core_PLLVDD
VID_PLLVDD

4 4

SP_PLLVDD

1V8_MAIN +1.8VSDGPU_MAIN

1V8_AON

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

PCB Revision

0.1

0.2

0.3

1.0

+NVVDD1
+NVVDD2NVVDDS

+1.35VSDGPU
+1.35VSDGPU

+1.8VSDGPU_AON

+1.0VSDGPU
+1.8VSDGPU_MAIN
+1.0VSDGPU
+1.8VSDGPU_MAIN
+1.8VSDGPU_MAIN
+1.8VSDGPU_MAIN
+1.8VSDGPU_MAIN
+1.8VSDGPU_MAIN

+1.8VSDGPU_AON

S0

ON

N/A N/A N/A

N/A

ON
ON
ON
ON
ON

ON
ON
ON ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON

ON

S4

S3

ON ON

ON

N/A

N/A

N/A N/A

N/A

ON ON

ON

ON ON

ON

ON

ON

ON ON

ON
ON
ON ON ONON
ON

ON

OFF

ON

OFF
OFF

OFF
OFF OFF
OFF OFF OFF

OFF

OFF

OFF

OFF

OFF

OFF
OFF OFF OFF

OFF

OFF

OFF OFF

OFF

OFF OFF
OFF
OFF OFF

OFFOFF
OFF OFF OFF
OFF OFF OFF

S5

N/AN/AN/A

ON*

ON*ON

ON

OFF
OFF
OFF
OFF

OFF
OFF
OFF

OFFOFF

OFFOFF
OFF
OFF

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Notes List

Notes List

Notes List

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

E

3 103Monday, January 09, 2017

3 103Monday, January 09, 2017

3 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

JUMP
(PJ703)

+VCCIOP_EN

JUMP
(PJ701)

JUMP
(PJ506)

D D

C C

SM_PG_CTRL

JUMP

(PJ1301 ,PJ13 02)

JUMP

(PJ1901 ,PJ19 02)

EN_1VGAP

JUMP
(PJ1601 )

EN_1VGAPS

JUMP
(PJ2402 )

5V_EN
3V_EN

JUMP
(PJ401)

ADAPTER

CHARGER

B+

BATTERY

B B

EN_1VALW

JUMP
(PJ601)

SUSP#

JUMP
(PJ2201 )

A A

+CPU_B+

SYSON

TPS51225CRUKR
(PU401)

SY8286RAC
(PU2201)

DRON

SY8286RAC
(PU701)

RT8207PGQW
(PU501)

0 ohm
(PR1301 )

0 ohm
(PR1901 )

SY8288RAC
(PU1601)

SY8286RAC
(PU2405)

SY8288RAC
(PU601)

NCP81151MNT BG
(PU901,PU903,PU904,PU9 05)

JUMP
(

PJ704)

+VCCIOP

+1.2VP

+0.6VSP

GPU1_B+

GPU2_B+

+1.0VS_VGAP +1.0VS DGPU

+1.0VS_VGAP_S

+5VALWP

+3VALWP

+1.0VALWP +1.0VALW

+1.8VSP +1.8VS

SA_B+

JUMP
(PJ2202 )

DRON

JUMP
(PJ702)

JUMP

(PJ501, PJ50 2)

JUMP
(PJ503)

0 ohm
(PR1302 )

JUMP
(PJ1401 )

JUMP
(PJ1701 )

0 ohm
(PR1902 )

JUMP
(PJ2001 )

JUMP
(PJ2301 )

JUMP
(PJ1602 )

JUMP
(PJ2303 )

JUMP

(PJP404 ,PJP4 05)

JUMP

(PJP402 ,PJP4 03)

JUMP
(PJ602)

NCP81253MNT BG
(PU902)

+VCCIO

+0.6VS_VTT

0 ohm
(PR1402 )

1.35VSDGPU_EN

0 ohm
(PR2002 )

1.35VSDGPU_EN_S

+VCCCORE

+1.2V_VDDQ

NVVDD1_B+

RT8812AGQW
(PU1701)

NVVDD1_S_B+

RT8812AGQW
(PU2301)

+1.0VSDGPU_ S

+5VALW

+3VALW

R-Short
(RA71)

R-Short
(RA70)

R-Short
(RA56)

1V8_AON_EN

1V8_AON_EN_S

NVVDD1_EN

NVVDD2_B+

NVVDD1_EN_S

NVVDD2_S_B+

FBMA-L11
(LH1)

FBMA-L11
(LH2)

FBMA-L11
(LH3)

0 ohm
(RH113 )

0 ohm
(RH86)

0 ohm
(RH138 )

0 ohm
(RH140 )

0 ohm
(RH141 )

SYSON

SUSP#

AOZ1331
(UG12)

AOZ1331
(UG30)

+VCCSA

0 ohm
(RC41)

0 ohm
(RC42)

UP9511PQGJ
(PU1201)

NVVDD2_EN

+1.35VS_VGAP

UP9511PQGJ
(PU1801)

NVVDD2_EN_S

+1.35VS_VGAP_S

USBKB_EN

SUSP#

FAN_EN

TOBII_EN

POGO_EN

CAM_EN

0 ohm
(RH135 )

0 ohm
(RH89)

0 ohm
(RH136 )

R-Short
(R315)

0 ohm
(R312)

SYSON

WLAN_PW R_EN

LAN_PWR _EN

LBPWR_EN

SUSP#

SUSP#

TPS22961DNYR
(U40)

TPS22961DNYR
(U42)

+1.8VS_AVDD_AMP

+1.8VS_DVDD_AMP

+1.8VS_AVDD

+VDDQ_CLK

+1.2V_VCCPLL_O C

+NVVDD1

NCP81278MNT XG
(PU1401)

+NVVDD1_S

NCP81278MNT XG
(PU2001)

SY6288C20A AC
(U12)

JUMP
(J29)

AOZ1331
(U41)

RT8525DGQW
(PU2403)

SY6288C20A AC
(U19)

SY6288C20A AC
(U13)

SY6288C20A AC
(U18)

+3VALW_DSW

+3VALW_PCH_PRIM

+3VALW_HDA

+3VALW_PD

+3.3V_TBT_SX

SY8003ADFC
(PU502)

SY6288C20A AC
(U9)

SY6288C20A AC
(UL3)

SY6288C20A AC

(UE3)

AOZ1331
(U43)

AOZ1331
(U41)

JUMP
(J17)

JUMP
(J27)

JUMP
(J16)

+1.0VALW_AMPHYPLL

+1.0VALW_AUSB_AZPLL

+1.0VALW_VCCCLK5

+1.0VALW_MPHY

+1.0VALW_PRIM

+1.0VALW_VCCCLK

+1.0VALW_PRIMAL22

+1.0VALW_PRIMAD15

+1.0V_VCCST_OUT

+1.0VS_VCCSTG_O UT

+1.8VSDGPU_AON

+1.8VSDGPU_AON_S

+NVVDD2

JUMP

(PJP170 1,PJP 1702 )

+1.35VSDGPU

+NVVDD2_S

JUMP

(PJP230 1,PJP 2302 )

+1.35VSDGPU_S

+5V_KB

+5VALW_PD

JUMP

+5VS

(J15)

+12VS

+5V_TOBII

+5V_POGO

0 ohm
(R353)

0 ohm
(R358)

0 ohm
(R355)

+5V_3DCAM

0 ohm

+3VALW_SPI

(RH27)

0 ohm
(R313)

+2.5VP +2.5V

JUMP
(PJ505)

+3VS_TBT

+3VS_WLAN

+3V_LAN

+5V_LBPWR

+3VS_NGFF1

+3VS_NGFF2

+3VS

0 ohm

R343)

(

0 ohm
(R347)

1V8_MAIN_EN

AOZ1331
(UG12)

1V8_MAIN_EN_S

AOZ1331
(UG30)

+VCC_FAN1

+VCC_FAN2

+VCC_FAN3

+1.0V_VCCST

+1.0V_VCCSTG

+1.8VSDGPU_MAIN

+1.8VSDGPU_MAIN_S

3VSDGPU_EN_R

3VSDGPU_EN_S_R

CAM_EN

+3VS

0 ohm
(RH87)

0 ohm
(R360)

0 ohm
(R219)

0 ohm
(RA5)

0ohm
(RA1)

0 ohm
(RA72 )

0 ohm
(RC40)

EN_DFAN

DGPU_ENVDD

TPS22961
(UG14)

TPS22961
(UG29)

SY6288C20A AC
(U16)

SY6288C20A AC

(UV3)

+1.0V_VCCSFR

NCT3942S
(U29)

NCT3942S
(U46)

0 ohm
(R412)

JUMP
(J18)

JUMP
(J28)

AP2330W

(UV1)

SY6288C20A AC
(U34)

+3VSDGPU

+3VSDGPU_S

+3VS_CAM

+3VS_DP

+3VS_VCCATS

+3V_RD

+3VS_TPM

+3VS_DVDDIO

+3VS_DVDD

+3VS_DVDDIO_AMP

+VCC_FAN4

+VCC_FAN5

+5VS_HDD

+VDDA

+5VS_PVDD_AMP

+HDMI_5V_OUT

+LCDVDD

HCB2012KF
(

LA2)

+5VS_AVDD

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Power Map

Power Map

Power Map

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

4 103Monday, January 09, 2017

4 103Monday, January 09, 2017

4 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

BIOS : 0.04
AC mode

Power On

S3 S3 Resume

Power Off

Plug in

+3VLP

D D

EC_ON

+5VALW

→

ON/OFFBTN#

+3VALW

92.95ms

→

→

8.914

+3VLP

EC_ON

+5VALW

ON/OFFBTN#

+

3VALW

→

+1.0ALW

EC_RSMRST#

PBTN_OUT#

PM_SLP_S5#

PM_SLP_S4#

C C

PM_SLP_S3#

SYSON

+1.0V_VCCST

+1.2V_VDDQ

+2.5V

SUSP#

+1.0VS_VCCSTG

+VCCIO

+1.8VS

+3VS

+5VS

B B

EC_VCCST_PG

DDR_PG_CTRL

+0.6VS_VTT

VR_ON

+VCCSA

PCH_PWROK

SYS_PWROK

PLT_RST#

+VCCCORE

PLTRST_CPU#

H_CPUPWRGD

93.42ms

30.4ms

→

→

121.1ms

21ms

←

←

→

16.52ms

→

16.56ms

→

16.58ms

→

→

69.64us

9.95us

→

→

584.8us

5.366ms

→

18.2ms

→

12.76us

→

287.3us

→

260.3us

→

1.431ms

→

1.372ms

→

37.63ms

→

37.63ms

→

13.03us

→

37.64ms

2.067ms

→

17.25ms

→

→

→

148.4ms

2.068ms

→

153.8ms

2.068ms

→

49.57ms

→

358.5us

→

13.85us

→

118.5us

→

1.053ms

→

→

→

→

→

→

→

→

→

11.04ns

→

83.9us

→

6.877us

7.297us

11.17us

→

→

3.84ms

3.03ms

529.6us

1.981ms

116.6us

171.6us

184us

529.4us

8.493ms

→

14us

→

258.3us

→

256.8us

→

1.288ms

→

1.389ms

→

→

→

→

28.86ms

28.86ms

→

28.86ms

→

→

→

→

12.14us

2.077ms

14.16ms

164.6ms

1.526ms

→

169ms

1.526ms

→

54.47ms

→

→

→

→

→

533.3us

→

461.6us

→

359.1us

4.51us

→

→

122.3us

→

1.079ms

→

17.87ms

→

14.02us

→

154.3us

→

→

→

→

→

7.824us

→

8.395us

→

→

11.17us

→

→

→

1.3ms

4.086ms

3.266ms

1.994ms

1.341ms

123.2us

164.9us

177.3us

8.95S

8.392S

8.392S

1.0ALW

+

EC_RSMRST#

PBTN_OUT#

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

S

YSON

+1.0V_VCCST

+1.2V_VDDQ

+2.5V

SUSP

+1.0VS_VCCSTG

+VCCIO

+1.8VS

+3VS

+5VS

EC_VCCST_PG

DDR_PG_CTRL

+0.6VS_VTT

VR_ON

+VCCSA

PCH_PWROK

SYS_PWROK

PLT_RST#

→

→

28.52ns

→

83.29us

569.1us

+VCCCORE

PLTRST_CPU#

H_CPUPWRGD

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Power Sequence

Power Sequence

Power Sequence

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

1

5 103Monday, January 09, 2017

5 103Monday, January 09, 2017

5 103Monday, January 09, 2017

1.0

1.0

1.0

A

K36

DDI1_TXP[0]

K37

DDI1_TXN[0]

J35

DDI1_TXP[1]

UC1

1 1

2 2

QL3X@

S IC CL8067702869811 QL3X A0 2.4G FCBGA 1440

SA0000A1520

QL2X@

UC1

S IC CL8067702869810 QL2X A0 2.7G FCBGA 1440

SA0000A1320

UC1

QLM4@

S IC CL8067702870009 QLM4 B0 2.9G BGA

SA0000ADA10

UC1

SR32P@

S IC CL8067702870009 SR32P B0 2.9G ABO!

SA0000ADA30

J34
H37
H36

J37

J38
D27

E27
H34

H33
F37
G38
F34
F35
E37
E36

F26
E26

C34
D34
B36
B34
F33
E33
C33
B33

A27
B27

DDI1_TXN[1]
DDI1_TXP[2]
DDI1_TXN[2]
DDI1_TXP[3]
DDI1_TXN[3]

DDI1_AUXP
DDI1_AUXN

DDI2_TXP[0]
DDI2_TXN[0]
DDI2_TXP[1]
DDI2_TXN[1]
DDI2_TXP[2]
DDI2_TXN[2]
DDI2_TXP[3]
DDI2_TXN[3]

DDI2_AUXP
DDI2_AUXN

DDI3_TXP[0]
DDI3_TXN[0]
DDI3_TXP[1]
DDI3_TXN[1]
DDI3_TXP[2]
DDI3_TXN[2]
DDI3_TXP[3]
DDI3_TXN[3]

DDI3_AUXP
DDI3_AUXN

S

KL-H_BGA1440

@

UC1D

B

SKYLAKE_HAL O

BGA1440

4 OF 14

EDP_TXP[0]
EDP_TXN[0]
EDP_TXP[1]
EDP_TXN[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXP
EDP_AUXN

EDP_DISP_UTIL

EDP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

D29
E29
F28
E28
B29
A29
B28
C28

C26
B26

A33

EDP_COMP

D37

EDP_COMP
Trace = 20 mils
Spacing = 25 mils
Max lenght = 100 mils

G27
G25
G29

?REV = 1

CPU_DISPA_SDI

12

RC47 20_0402_1%

C

+VCCIO

12

RC124.9_0402_1%

CPU_DISPA_BCLK_R <20>
CPU_DISPA_SDO_R <20>

CPU_DISPA_SDI_R <20>

D

E

CMC CONN

RC3 0_0603_5%CMC@

+3VALW_PCH_PRIM

1 2

RC2 1K_0402_5%

+1.0VS_VCCSTG

RC4 51_0402_5%

3 3

Place to CPU side

Place to CPU side

4 4

RC5 51_0402_5%
RC6 51_0402_5%

+1.0VALW_XDP

RC8 2.2K_0402_5%CMC@

RC10 0_0402_5%@
RC11 0_0402_5%@

RC13 51_0402_5%
RC15 51_0402_5%@
RC17 51_0402_5%@

RC60 1K_0402_5%@

12
12
12

1 2

12
12

12
12
12

1 2

XDP_SPI_SI

CPU_XDP_TMS
CPU_XDP_TDI
CPU_XDP_TDO

XDP_ITP_PMODE

XDP_PRSENT_CPU
XDP_PRSENT_PCH

CPU_XDP_TCK0
PCH_JTAG_TCK1
CPU_XDP_TRST#

CFG0

CMC@

CPU_XDP_TDO<9,20>
CPU_XDP_TDI<9,20>
CPU_XDP_TMS<9,20>

CPU_XDP_TCK0<9,20>

CPU_XDP_TRST#<9,24>
PCH_JTAG_TCK1<20>

XDP_SPI_IO2<19>

XDP_SPI_SI<19>

XDP_ITP_PMODE<20>

EC_RSMRST#<20,38>

CPU_XDP_TDO
CPU_XDP_TDI
CPU_XDP_TMS
CPU_XDP_TCK0

CPU_XDP_TRST#
PCH_JTAG_TCK1

CFG3
XDP_SPI_IO2

XDP_SPI_SI
XDP_ITP_PMODE XDP_HOOK6

RPC1

1 8
2 7
3 6
4 5

0_0804_8P4R_5%

CMC@

RPC2

1 8
2 7
3 6
4 5

0_0804_8P4R_5%

CMC@

RPC3

1 8
2 7
3 6
4 5

0_0804_8P4R_5%

1 2

CMC@

RC56 1K_0402_5%

XDP_TDO
XDP_TDI
XDP_TMS
XDP_TCK0

XDP_TRST#

XDP_TCK1
XDP_PRSENT_CPU
XDP_PRSENT_PCH

XDP_HOOK3

XDP_HOOK0EC_RSMRST#

CFG0<9>
CFG1<9>
CFG2<9>
CFG3<9>
CFG4<9>
CFG5<9>
CFG6<9>
CFG7<9>

CFG17<9>
CFG16<9>

CFG8<9>

CFG9<9>
CFG10<9>
CFG11<9>
CFG12<9>
CFG13<9>
CFG14<9>
CFG15<9>

CFG19<9>
CFG18<9>

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7

CFG17
CFG16

CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG19
CFG18

JPCMC1

OBS DATA

1

DATA_0

3

DATA_1

5

DATA_2

7

DATA_3

9

DATA_4

11

DATA_5

13

DATA_6

15

DATA_7

17

DATA_CLK_1P

21

DATA_CLK_1N

2

DATA_8

4

DATA_9

6

DATA_10

8

DATA_11

10

DATA_12

12

DATA_13

14

DATA_14

16

DATA_15

18

DATA_CLK_2P

20

DATA_CLK_2N

INTEL_CMC_PRIMARY

CONN@

1 2

CMC_DEBUG_36P

+1.0VALW_XDP+1.0VALW_PRIM

JTAG/RC/HOOKS

VCCOBS_AB

XDP_TRST*

XDP_TDI

XDP_TMS
XDP_TCK0
XDP_TCK1

XDP_TDO

XDP_PREQ*

XDP_PRDY*

HOOK_0
HOOK_3
HOOK_6

XDP_PRSNT_PCH*
XDP_PRSNT_CPU*

GND

<MT> GND

+1.0VALW_XDP

22

XDP_TRST#

28

XDP_TDI

29

XDP_TMS

30

XDP_TCK0

32

XDP_TCK1

31

XDP_TDO

35

XDP_PREQ#

33

XDP_PRDY#

34

XDP_HOOK0

27

XDP_HOOK3

25

XDP_HOOK6

26

XDP_PRSENT_PCH

24

XDP_PRSENT_CPU

23
19

36

XDP_PREQ# <9,24>
XDP_PRDY# <9,24>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

A

B

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

C

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

D

Date: Sheet o f

Compal Electronics, Inc.

SKL-H(1/9)DDI,EDP

SKL-H(1/9)DDI,EDP

SKL-H(1/9)DDI,EDP

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

E

6 103Monday, January 09, 2017

6 103Monday, January 09, 2017

6 103Monday, January 09, 2017

1.0

1.0

1.0

A

B

C

D

E

CHANNEL-A

Interleaved Memory

1 1

DDR_A_D[0..15]<14,15>

DDR_A_D[16..31]<14,15>

DDR_A_D[32..47]<14,15>

2 2

DDR_A_D[48..63]<14,15>

3 3

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

UC1A

BR6

DDR0_DQ[0]

BT6

DDR0_DQ[1]

BP3

DDR0_DQ[2]

BR3

DDR0_DQ[3]

BN5

DDR0_DQ[4]

BP6

DDR0_DQ[5]

BP2

DDR0_DQ[6]

BN3

DDR0_DQ[7]

BL4

DDR0_DQ[8]

BL5

DDR0_DQ[9]

BL2

DDR0_DQ[10]

BM1

DDR0_DQ[11]

BK4

DDR0_DQ[12]

BK5

DDR0_DQ[13]

BK1

DDR0_DQ[14]

BK2

DDR0_DQ[15]

BG4

DDR0_DQ[16]/DDR0_DQ[32]

BG5

DDR0_DQ[17]/DDR0_DQ[33]

BF4

DDR0_DQ[18]/DDR0_DQ[34]

BF5

DDR0_DQ[19]/DDR0_DQ[35]

BG2

DDR0_DQ[20]/DDR0_DQ[36]

BG1

DDR0_DQ[21]/DDR0_DQ[37]

BF1

DDR0_DQ[22]/DDR0_DQ[38]

BF2

DDR0_DQ[23]/DDR0_DQ[39]

BD2

DDR0_DQ[24]/DDR0_DQ[40]

BD1

DDR0_DQ[25]/DDR0_DQ[41]

BC4

DDR0_DQ[26]/DDR0_DQ[42]

BC5

DDR0_DQ[27]/DDR0_DQ[43]

BD5

DDR0_DQ[28]/DDR0_DQ[44]

BD4

DDR0_DQ[29]/DDR0_DQ[45]

BC1

DDR0_DQ[30]/DDR0_DQ[46]

BC2

DDR0_DQ[31]/DDR0_DQ[47]

AB1

DDR0_DQ[32]/DDR1_DQ[0]

AB2

DDR0_DQ[33]/DDR1_DQ[1]

AA4

DDR0_DQ[34]/DDR1_DQ[2]

AA5

DDR0_DQ[35]/DDR1_DQ[3]

AB5

DDR0_DQ[36]/DDR1_DQ[4]

AB4

DDR0_DQ[37]/DDR1_DQ[5]

AA2

DDR0_DQ[38]/DDR1_DQ[6]

AA1

DDR0_DQ[39]/DDR1_DQ[7]

V5

DDR0_DQ[40]/DDR1_DQ[8]

V2

DDR0_DQ[41]/DDR1_DQ[9]

U1

DDR0_DQ[42]/DDR1_DQ[10]

U2

DDR0_DQ[43]/DDR1_DQ[11]

V1

DDR0_DQ[44]/DDR1_DQ[12]

V4

DDR0_DQ[45]/DDR1_DQ[13]

U5

DDR0_DQ[46]/DDR1_DQ[14]

U4

DDR0_DQ[47]/DDR1_DQ[15]

R2

DDR0_DQ[48]/DDR1_DQ[32]

P5

DDR0_DQ[49]/DDR1_DQ[33]

R4

DDR0_DQ[50]/DDR1_DQ[34]

P4

DDR0_DQ[51]/DDR1_DQ[35]

R5

DDR0_DQ[52]/DDR1_DQ[36]

P2

DDR0_DQ[53]/DDR1_DQ[37]

R1

DDR0_DQ[54]/DDR1_DQ[38]

P1

DDR0_DQ[55]/DDR1_DQ[39]

M4

DDR0_DQ[56]/DDR1_DQ[40]

M1

DDR0_DQ[57]/DDR1_DQ[41]

L4

DDR0_DQ[58]/DDR1_DQ[42]

L2

DDR0_DQ[59]/DDR1_DQ[43]

M5

DDR0_DQ[60]/DDR1_DQ[44]

M2

DDR0_DQ[61]/DDR1_DQ[45]

L5

DDR0_DQ[62]/DDR1_DQ[46]

L1

DDR0_DQ[63]/DDR1_DQ[47]

BA2

DDR0_ECC[0]

BA1

DDR0_ECC[1]

AY4

DDR0_ECC[2]

AY5

DDR0_ECC[3]

BA5

DDR0_ECC[4]

BA4

DDR0_ECC[5]

AY1

DDR0_ECC[6]

AY2

DDR0_ECC[7]

DDR CHANNEL A

S

KL-H_BGA1440

REV = 1

@

SKYLAKE_HALO

BGA1440

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSN[7]/DDR1_DQSN[5]

1 OF 14

DDR0_CKP[0]
DDR0_CKN[0]
DDR0_CKN[1]

DDR0_CKP[1]
DDR0_CLKP[2]
DDR0_CLKN[2]
DDR0_CLKP[3]
DDR0_CLKN[3]

DDR0_CKE[0]

DDR0_CKE[1]

DDR0_CKE[2]

DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1]

DDR0_CS#[2]

DDR0_CS#[3]

DDR0_ODT[0]

DDR0_ODT[1]

DDR0_ODT[2]

DDR0_ODT[3]

DDR0_MA[3]
DDR0_MA[4]

DDR0_PAR

DDR0_ALERT#

DDR0_DQSN[0]
DDR0_DQSN[1]

DDR0_DQSP[0]
DDR0_DQSP[1]

DDR0_DQSP[8]
DDR0_DQSN[8]

?

DDR_A_CLK0

AG1

DDR_A_CLK#0

AG2

DDR_A_CLK#1

AK1

DDR_A_CLK1

AK2

DDR_A_CLK2

AL3

DDR_A_CLK#2

AK3

DDR_A_CLK3

AL2

DDR_A_CLK#3

AL1

DDR_A_CKE0

AT1

DDR_A_CKE1

AT2

DDR_A_CKE2

AT3

DDR_A_CKE3

AT5

DDR_A_CS#0

AD5

DDR_A_CS#1

AE2

DDR_A_CS#2

AD2

DDR_A_CS#3

AE5

DDR_A_ODT0

AD3

DDR_A_ODT1

AE4

DDR_A_ODT2

AE1

DDR_A_ODT3

AD4

DDR_A_BA0

AH5

DDR_A_BA1

AH1

DDR_A_BG0

AU1

DDR_A_RAS#

AH4

DDR_A_WE#

AG4

DDR_A_CAS#

AD1

DDR_A_MA0

AH3

DDR_A_MA1

AP4

DDR_A_MA2

AN4

DDR_A_MA3

AP5

DDR_A_MA4

AP2

DDR_A_MA5

AP1

DDR_A_MA6

AP3

DDR_A_MA7

AN1

DDR_A_MA8

AN3

DDR_A_MA9

AT4

DDR_A_MA10

AH2

DDR_A_MA11

AN2

DDR_A_MA12

AU4

DDR_A_MA13

AE3

DDR_A_BG1

AU2

DDR_A_ACT#

AU3

DDR_A_PAR

AG3

DDR_A_ALERT# DDR_B_PAR

AU5

DDR_A_DQS#0

BR5

DDR_A_DQS#1

BL3

DDR_A_DQS#2

BG3

DDR_A_DQS#3

BD3

DDR_A_DQS4

AB3

DDR_A_DQS5

V3

DDR_A_DQS6

R3

DDR_A_DQS7

M3

DDR_A_DQS0

BP5

DDR_A_DQS1

BK3

DDR_A_DQS2

BF3

DDR_A_DQS3

BC3

DDR_A_DQS#4

AA3

DDR_A_DQS#5

U3

DDR_A_DQS#6

P3

DDR_A_DQS#7

L3
AY3

BA3

DDR_A_CLK0 <14>
DDR_A_CLK#0 <14>
DDR_A_CLK#1 <14>
DDR_A_CLK1 <14>
DDR_A_CLK2 <15>
DDR_A_CLK#2 <15>
DDR_A_CLK3 <15>
DDR_A_CLK#3 <15>

DDR_A_CKE0 <14>
DDR_A_CKE1 <14>
DDR_A_CKE2 <15>
DDR_A_CKE3 <15>

DDR_A_CS#0 <14>
DDR_A_CS#1 <14>
DDR_A_CS#2 <15>
DDR_A_CS#3 <15>

DDR_A_ODT0 <14>
DDR_A_ODT1 <14>
DDR_A_ODT2 <15>
DDR_A_ODT3 <15>

DDR_A_BA0 <14,15>
DDR_A_BA1 <14,15>
DDR_A_BG0 <14,15>

DDR_A_RAS# <14,15>
DDR_A_WE# <14,15>
DDR_A_CAS# <14,15>

DDR_A_MA0 <14,15>
DDR_A_MA1 <14,15>
DDR_A_MA2 <14,15>
DDR_A_MA3 <14,15>
DDR_A_MA4 <14,15>
DDR_A_MA5 <14,15>
DDR_A_MA6 <14,15>
DDR_A_MA7 <14,15>
DDR_A_MA8 <14,15>
DDR_A_MA9 <14,15>
DDR_A_MA10 <14,15>
DDR_A_MA11 <14,15>
DDR_A_MA12 <14,15>
DDR_A_MA13 <14,15>
DDR_A_BG1 <14,15>
DDR_A_ACT# <14,15>

DDR_A_PAR <14,15>
DDR_A_ALERT# <14,15> DDR_B_PAR <16,17>

DDR_A_DQS#0 <14,15>
DDR_A_DQS#1 <14,15>
DDR_A_DQS#2 <14,15>
DDR_A_DQS#3 <14,15>
DDR_A_DQS4 <14,15>
DDR_A_DQS5 <14,15>
DDR_A_DQS6 <14,15>
DDR_A_DQS7 <14,15>

DDR_A_DQS0 <14,15>
DDR_A_DQS1 <14,15>
DDR_A_DQS2 <14,15>
DDR_A_DQS3 <14,15>
DDR_A_DQS#4 <14,15>
DDR_A_DQS#5 <14,15>
DDR_A_DQS#6 <14,15>
DDR_A_DQS#7 <14,15>

DDR_B_D[0..15]<16,17>

DDR_B_D[16..31]<16,17>

DDR_B_D[32..47]<16,17>

DDR_B_D[48..63]<16,17>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

SM_RCOMP0

12

RC19121_0402_1%

SM_RCOMP1

12

RC2075_0402_1%

SM_RCOMP2

12

RC21100_0402_1%

Place close to CPU

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
Trace = 12~15 mils
Spacing = 20 mils
Max lenght = 500 mils

CHANNEL-B

Interleaved Memory

UC1B

BT11

DDR1_DQ[0]/DDR0_DQ[16]

BR11

DDR1_DQ[1]/DDR0_DQ[17]

BT8

DDR1_DQ[2]/DDR0_DQ[18]

BR8

DDR1_DQ[3]/DDR0_DQ[19]

BP11

DDR1_DQ[4]/DDR0_DQ[20]

BN11

DDR1_DQ[5]/DDR0_DQ[21]

BP8

DDR1_DQ[6]/DDR0_DQ[22]

BN8

DDR1_DQ[7]/DDR0_DQ[23]

BL12

DDR1_DQ[8]/DDR0_DQ[24]

BL11

DDR1_DQ[9]/DDR0_DQ[25]

BL8

DDR1_DQ[10]/DDR0_DQ[26]

BJ8

DDR1_DQ[11]/DDR0_DQ[27]

BJ11

DDR1_DQ[12]/DDR0_DQ[28]

BJ10

DDR1_DQ[13]/DDR0_DQ[29]

BL7

DDR1_DQ[14]/DDR0_DQ[30]

BJ7

DDR1_DQ[15]/DDR0_DQ[31]

BG11

DDR1_DQ[16]/DDR0_DQ[48]

BG10

DDR1_DQ[17]/DDR0_DQ[49]

BG8

DDR1_DQ[18]/DDR0_DQ[50]

BF8

DDR1_DQ[19]/DDR0_DQ[51]

BF11

DDR1_DQ[20]/DDR0_DQ[52]

BF10

DDR1_DQ[21]/DDR0_DQ[53]

BG7

DDR1_DQ[22]/DDR0_DQ[54]

BF7

DDR1_DQ[23]/DDR0_DQ[55]

BB11

DDR1_DQ[24]/DDR0_DQ[56]

BC11

DDR1_DQ[25]/DDR0_DQ[57]

BB8

DDR1_DQ[26]/DDR0_DQ[58]

BC8

DDR1_DQ[27]/DDR0_DQ[59]

BC10

DDR1_DQ[28]/DDR0_DQ[60]

BB10

DDR1_DQ[29]/DDR0_DQ[61]

BC7

DDR1_DQ[30]/DDR0_DQ[62]

BB7

DDR1_DQ[31]/DDR0_DQ[63]

AA11

DDR1_DQ[32]/DDR1_DQ[16]

AA10

DDR1_DQ[33]/DDR1_DQ[17]

AC11

DDR1_DQ[34]/DDR1_DQ[18]

AC10

DDR1_DQ[35]/DDR1_DQ[19]

AA7

DDR1_DQ[36]/DDR1_DQ[20]

AA8

DDR1_DQ[37]/DDR1_DQ[21]

AC8

DDR1_DQ[38]/DDR1_DQ[22]

AC7

DDR1_DQ[39]/DDR1_DQ[23]

W8

DDR1_DQ[40]/DDR1_DQ[24]

W7

DDR1_DQ[41]/DDR1_DQ[25]

V10

DDR1_DQ[42]/DDR1_DQ[26]

V11

DDR1_DQ[43]/DDR1_DQ[27]

W11

DDR1_DQ[44]/DDR1_DQ[28]

W10

DDR1_DQ[45]/DDR1_DQ[29]

V7

DDR1_DQ[46]/DDR1_DQ[30]

V8

DDR1_DQ[47]/DDR1_DQ[31]

R11

DDR1_DQ[48]

P11

DDR1_DQ[49]

P7

DDR1_DQ[50]

R8

DDR1_DQ[51]

R10

DDR1_DQ[52]

P10

DDR1_DQ[53]

R7

DDR1_DQ[54]

P8

DDR1_DQ[55]

L11

DDR1_DQ[56]

M11

DDR1_DQ[57]

L7

DDR1_DQ[58]

M8

DDR1_DQ[59]

L10

DDR1_DQ[60]

M10

DDR1_DQ[61]

M7

DDR1_DQ[62]

L8

DDR1_DQ[63]

AW11

DDR1_ECC[0]

AY11

DDR1_ECC[1]

AY8

DDR1_ECC[2]

AW8

DDR1_ECC[3]

AY10

DDR1_ECC[4]

AW10

DDR1_ECC[5]

AY7

DDR1_ECC[6]

AW7

DDR1_ECC[7]

G1

DDR_RCOMP[0]

H1

DDR_RCOMP[1]

J2

DDR_RCOMP[2]

S

KL-H_BGA1440

REV = 1 ?

@

DDR CHANNEL B

SKYLAKE_HALO

BGA1440

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSP[5]/DDR1_DQSP[3]

2 OF 14

DDR1_CKP[0]
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[1]

DDR1_CLKP[2]

DDR1_CLKN[2]

DDR1_CLKP[3]

DDR1_CLKN[3]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1]
DDR1_CS#[2]
DDR1_CS#[3]

DDR1_ODT[0]
DDR1_ODT[1]
DDR1_ODT[2]
DDR1_ODT[3]

DDR1_MA[3]
DDR1_MA[4]

DDR1_PAR

DDR1_ALERT#

DDR1_DQSN[6]
DDR1_DQSN[7]

DDR1_DQSP[6]
DDR1_DQSP[7]

DDR1_DQSP[8]
DDR1_DQSN[8]

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

AM9
AN9
AM8
AM7
AM11
AM10
AJ10
AJ11

AT8
AT10
AT7
AT11

AF11
AE7
AF10
AE10

AF7
AE8
AE9
AE11

AH10
AH11
AF8

AH8
AH9
AR9

AJ9
AK6
AK5
AL5
AL6
AM6
AN7
AN10
AN8
AR11
AH7
AN11
AR10
AF9
AR7
AT9

AJ7
AR8

BP9
BL9
BG9
BC9
AC9
W9
R9
M9

BR9
BJ9
BF9
BB9
AA9
V9
P9
L9

AW9
AY9

BN13
BP13
BR13

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK#1
DDR_B_CLK1
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK3
DDR_B_CLK#3

DDR_B_CKE0
DDR_B_CKE1
DDR_B_CKE2
DDR_B_CKE3

DDR_B_CS#0
DDR_B_CS#1
DDR_B_CS#2
DDR_B_CS#3

DDR_B_ODT0
DDR_B_ODT1
DDR_B_ODT2
DDR_B_ODT3

DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#

DDR_B_BA0
DDR_B_BA1
DDR_B_BG0

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_BG1
DDR_B_ACT#

DDR_B_ALERT#

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

+0.6V_VREFCA
+0.6V_B_VREFDQ

DDR_B_CLK0 <16>
DDR_B_CLK#0 <16>
DDR_B_CLK#1 <16>
DDR_B_CLK1 <16>
DDR_B_CLK2 <17>
DDR_B_CLK#2 <17>
DDR_B_CLK3 <17>
DDR_B_CLK#3 <17>

DDR_B_CKE0 <16>
DDR_B_CKE1 <16>
DDR_B_CKE2 <17>
DDR_B_CKE3 <17>

DDR_B_CS#0 <16>
DDR_B_CS#1 <16>
DDR_B_CS#2 <17>
DDR_B_CS#3 <17>

DDR_B_ODT0 <16>
DDR_B_ODT1 <16>
DDR_B_ODT2 <17>
DDR_B_ODT3 <17>

DDR_B_RAS# <16,17>
DDR_B_WE# <16,17>
DDR_B_CAS# <16,17>

DDR_B_BA0 <16,17>
DDR_B_BA1 <16,17>
DDR_B_BG0 <16,17>

DDR_B_MA0 <16,17>
DDR_B_MA1 <16,17>
DDR_B_MA2 <16,17>
DDR_B_MA3 <16,17>
DDR_B_MA4 <16,17>
DDR_B_MA5 <16,17>
DDR_B_MA6 <16,17>
DDR_B_MA7 <16,17>
DDR_B_MA8 <16,17>
DDR_B_MA9 <16,17>
DDR_B_MA10 <16,17>
DDR_B_MA11 <16,17>
DDR_B_MA12 <16,17>
DDR_B_MA13 <16,17>
DDR_B_BG1 <16,17>
DDR_B_ACT# <16,17>

DDR_B_ALERT# <16,17>

DDR_B_DQS#0 <16,17>
DDR_B_DQS#1 <16,17>
DDR_B_DQS#2 <16,17>
DDR_B_DQS#3 <16,17>
DDR_B_DQS#4 <16,17>
DDR_B_DQS#5 <16,17>
DDR_B_DQS#6 <16,17>
DDR_B_DQS#7 <16,17>

DDR_B_DQS0 <16,17>
DDR_B_DQS1 <16,17>
DDR_B_DQS2 <16,17>
DDR_B_DQS3 <16,17>
DDR_B_DQS4 <16,17>
DDR_B_DQS5 <16,17>
DDR_B_DQS6 <16,17>
DDR_B_DQS7 <16,17>

+0.6V_VREFCA
+0.6V_B_VREFDQ

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom
Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

SKL-H(2/9)DDRIII

SKL-H(2/9)DDRIII

SKL-H(2/9)DDRIII

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Monday, January 09, 2017

Monday, January 09, 2017

Monday, January 09, 2017

E

7

1.0

1.0

1.0

103

103

103

7

7

A

B

C

D

E

PEG 2x8 reverse

1 1

1 2

PCIE_CRX_C_GTX_P15<53>
PCIE_CRX_C_GTX_N15<53>

PCIE_CRX_C_GTX_P14<53>
PCIE_CRX_C_GTX_N14<53>

PCIE_CRX_C_GTX_P13<53>
PCIE_CRX_C_GTX_N13<53>

PCIE_CRX_C_GTX_P12<53>

Slave GPU

2 2

Master GPU

3 3

PCIE_CRX_C_GTX_N12<53>
PCIE_CRX_C_GTX_P11<53>

PCIE_CRX_C_GTX_N11<53>
PCIE_CRX_C_GTX_P10<53>

PCIE_CRX_C_GTX_N10<53>
PCIE_CRX_C_GTX_P9<53>

PCIE_CRX_C_GTX_N9<53>
PCIE_CRX_C_GTX_P8<53>

PCIE_CRX_C_GTX_N8<53>
PCIE_CRX_C_GTX_P7<41>

PCIE_CRX_C_GTX_N7<41>
PCIE_CRX_C_GTX_P6<41>

PCIE_CRX_C_GTX_N6<41>
PCIE_CRX_C_GTX_P5<41>

PCIE_CRX_C_GTX_N5<41>
PCIE_CRX_C_GTX_P4<41>

PCIE_CRX_C_GTX_N4<41>
PCIE_CRX_C_GTX_P3<41>

PCIE_CRX_C_GTX_N3<41>
PCIE_CRX_C_GTX_P2<41>

PCIE_CRX_C_GTX_N2<41>
PCIE_CRX_C_GTX_P1<41>

PCIE_CRX_C_GTX_N1<41>
PCIE_CRX_C_GTX_P0<41>

PCIE_CRX_C_GTX_N0<41>

CC87 0.22U_0402_16V7K

1 2

CC88 0.22U_0402_16V7K

1 2

CC85 0.22U_0402_16V7K

1 2

CC86 0.22U_0402_16V7K

1 2

CC83 0.22U_0402_16V7K

1 2

CC84 0.22U_0402_16V7K

1 2

CC81 0.22U_0402_16V7K

1 2

CC82 0.22U_0402_16V7K

1 2

CC80 0.22U_0402_16V7K

1 2

CC79 0.22U_0402_16V7K

1 2

CC78 0.22U_0402_16V7K

1 2

CC77 0.22U_0402_16V7K

1 2

CC76 0.22U_0402_16V7K

1 2

CC75 0.22U_0402_16V7K

1 2

CC73 0.22U_0402_16V7K

1 2

CC74 0.22U_0402_16V7K

1 2

CC49 0.22U_0402_16V7K

1 2

CC50 0.22U_0402_16V7K

1 2

CC51 0.22U_0402_16V7K

1 2

CC52 0.22U_0402_16V7K

1 2

CC57 0.22U_0402_16V7K

1 2

CC58 0.22U_0402_16V7K

1 2

CC59 0.22U_0402_16V7K

1 2

CC60 0.22U_0402_16V7K

1 2

CC61 0.22U_0402_16V7K

1 2

CC62 0.22U_0402_16V7K

1 2

CC63 0.22U_0402_16V7K

1 2

CC64 0.22U_0402_16V7K

1 2

CC65 0.22U_0402_16V7K

1 2

CC66 0.22U_0402_16V7K

1 2

CC67 0.22U_0402_16V7K

1 2

CC68 0.22U_0402_16V7K

CAD note:
Trace width=12 mils,Spacing=15mil,Max length=400mils

+VCCIO

DMI_CRX_PTX_P0<18>
DMI_CRX_PTX_N0<18>

DMI_CRX_PTX_P1<18>
DMI_CRX_PTX_N1<18>

DMI_CRX_PTX_P2<18>
DMI_CRX_PTX_N2<18>

DMI_CRX_PTX_P3<18>
DMI_CRX_PTX_N3<18>

1 2

RC22 24.9_0402_1%

PCIE_CRX_GTX_P15
PCIE_CRX_GTX_N15

PCIE_CRX_GTX_P14
PCIE_CRX_GTX_N14

PCIE_CRX_GTX_P13
PCIE_CRX_GTX_N13

PCIE_CRX_GTX_P12
PCIE_CRX_GTX_N12

PCIE_CRX_GTX_P11
PCIE_CRX_GTX_N11

PCIE_CRX_GTX_P10
PCIE_CRX_GTX_N10

PCIE_CRX_GTX_P9
PCIE_CRX_GTX_N9

PCIE_CRX_GTX_P8
PCIE_CRX_GTX_N8

PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7

PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5

PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

PEG_RCOMP

DMI_CRX_PTX_P0
DMI_CRX_PTX_N0

DMI_CRX_PTX_P1
DMI_CRX_PTX_N1

DMI_CRX_PTX_P2
DMI_CRX_PTX_N2

DMI_CRX_PTX_P3
DMI_CRX_PTX_N3

E25
D25

E24
F24

E23
D23

E22
F22

E21
D21

E20
F20

E19
D19

E18
F18

D17
E17

F16
E16

D15
E15

F14
E14

D13
E13

F12
E12

D11
E11

F10
E10

G2

D8
E8

E6

F6

D5
E5

J8
J9

UC1C

PEG_RXP[0]
PEG_RXN[0]

PEG_RXP[1]
PEG_RXN[1]

PEG_RXP[2]
PEG_RXN[2]

PEG_RXP[3]
PEG_RXN[3]

PEG_RXP[4]
PEG_RXN[4]

PEG_RXP[5]
PEG_RXN[5]

PEG_RXP[6]
PEG_RXN[6]

PEG_RXP[7]
PEG_RXN[7]

PEG_RXP[8]
PEG_RXN[8]

PEG_RXP[9]
PEG_RXN[9]

PEG_RXP[10]
PEG_RXN[10]

PEG_RXP[11]
PEG_RXN[11]

PEG_RXP[12]
PEG_RXN[12]

PEG_RXP[13]
PEG_RXN[13]

PEG_RXP[14]
PEG_RXN[14]

PEG_RXP[15]
PEG_RXN[15]

PEG_RCOMP

DMI_RXP[0]
DMI_RXN[0]

DMI_RXP[1]
DMI_RXN[1]

DMI_RXP[2]
DMI_RXN[2]

DMI_RXP[3]
DMI_RXN[3]

S

KL-H_BGA1440

REV = 1

@

SKYLAKE_HALO

BGA1440

3 OF 14

PEG_TXP[0]
PEG_TXN[0]

PEG_TXP[1]
PEG_TXN[1]

PEG_TXP[2]
PEG_TXN[2]

PEG_TXP[3]
PEG_TXN[3]

PEG_TXP[4]
PEG_TXN[4]

PEG_TXP[5]
PEG_TXN[5]

PEG_TXP[6]
PEG_TXN[6]

PEG_TXP[7]
PEG_TXN[7]

PEG_TXP[8]
PEG_TXN[8]

PEG_TXP[9]
PEG_TXN[9]

PEG_TXP[10]
PEG_TXN[10]

PEG_TXP[11]
PEG_TXN[11]

PEG_TXP[12]
PEG_TXN[12]

PEG_TXP[13]
PEG_TXN[13]

PEG_TXP[14]
PEG_TXN[14]

PEG_TXP[15]
PEG_TXN[15]

DMI_TXP[0]
DMI_TXN[0]

DMI_TXP[1]
DMI_TXN[1]

DMI_TXP[2]
DMI_TXN[2]

DMI_TXP[3]
DMI_TXN[3]

B25
A25

B24
C24

B23
A23

B22
C22

B21
A21

B20
C20

B19
A19

B18
C18

A17
B17

C16
B16

A15
B15

C14
B14

A13
B13

C12
B12

A11
B11

C10
B10

B8
A8

C6
B6

B5
A5

D4
B4

?

PCIE_CTX_GRX_P15
PCIE_CTX_GRX_N15

PCIE_CTX_GRX_P14
PCIE_CTX_GRX_N14

PCIE_CTX_GRX_P13
PCIE_CTX_GRX_N13

PCIE_CTX_GRX_P12
PCIE_CTX_GRX_N12

PCIE_CTX_GRX_P11
PCIE_CTX_GRX_N11

PCIE_CTX_GRX_P10
PCIE_CTX_GRX_N10

PCIE_CTX_GRX_P9
PCIE_CTX_GRX_N9

PCIE_CTX_GRX_P8
PCIE_CTX_GRX_N8

PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7

PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6

PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5

PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4

PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3

PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0

DMI_CTX_PRX_P0
DMI_CTX_PRX_N0

DMI_CTX_PRX_P1
DMI_CTX_PRX_N1

DMI_CTX_PRX_P2
DMI_CTX_PRX_N2

DMI_CTX_PRX_P3
DMI_CTX_PRX_N3

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

DMI_CTX_PRX_P0 <18>
DMI_CTX_PRX_N0 <18>

DMI_CTX_PRX_P1 <18>
DMI_CTX_PRX_N1 <18>

DMI_CTX_PRX_P2 <18>
DMI_CTX_PRX_N2 <18>

DMI_CTX_PRX_P3 <18>
DMI_CTX_PRX_N3 <18>

CC1040.22U_0402_16V7K
CC1030.22U_0402_16V7K

CC1020.22U_0402_16V7K
CC1010.22U_0402_16V7K

CC990.22U_0402_16V7K
CC1000.22U_0402_16V7K

CC970.22U_0402_16V7K
CC980.22U_0402_16V7K

CC950.22U_0402_16V7K
CC960.22U_0402_16V7K

CC940.22U_0402_16V7K
CC930.22U_0402_16V7K

CC920.22U_0402_16V7K
CC910.22U_0402_16V7K

CC900.22U_0402_16V7K
CC890.22U_0402_16V7K

CC30.22U_0402_16V7K
CC40.22U_0402_16V7K

CC50.22U_0402_16V7K
CC60.22U_0402_16V7K

CC70.22U_0402_16V7K
CC80.22U_0402_16V7K

CC90.22U_0402_16V7K
CC100.22U_0402_16V7K

CC110.22U_0402_16V7K
CC120.22U_0402_16V7K

CC130.22U_0402_16V7K
CC140.22U_0402_16V7K

CC150.22U_0402_16V7K
CC160.22U_0402_16V7K

CC170.22U_0402_16V7K
CC180.22U_0402_16V7K

PCIE_CTX_C_GRX_P15 <53>
PCIE_CTX_C_GRX_N15 <53>

PCIE_CTX_C_GRX_P14 <53>
PCIE_CTX_C_GRX_N14 <53>

PCIE_CTX_C_GRX_P13 <53>
PCIE_CTX_C_GRX_N13 <53>

PCIE_CTX_C_GRX_P12 <53>
PCIE_CTX_C_GRX_N12 <53>

PCIE_CTX_C_GRX_P11 <53>
PCIE_CTX_C_GRX_N11 <53>

PCIE_CTX_C_GRX_P10 <53>
PCIE_CTX_C_GRX_N10 <53>

PCIE_CTX_C_GRX_P9 <53>
PCIE_CTX_C_GRX_N9 <53>

PCIE_CTX_C_GRX_P8 <53>
PCIE_CTX_C_GRX_N8 <53>

PCIE_CTX_C_GRX_P7 <41>
PCIE_CTX_C_GRX_N7 <41>

PCIE_CTX_C_GRX_P6 <41>
PCIE_CTX_C_GRX_N6 <41>

PCIE_CTX_C_GRX_P5 <41>
PCIE_CTX_C_GRX_N5 <41>

PCIE_CTX_C_GRX_P4 <41>
PCIE_CTX_C_GRX_N4 <41>

PCIE_CTX_C_GRX_P3 <41>
PCIE_CTX_C_GRX_N3 <41>

PCIE_CTX_C_GRX_P2 <41>
PCIE_CTX_C_GRX_N2 <41>

PCIE_CTX_C_GRX_P1 <41>
PCIE_CTX_C_GRX_N1 <41>

PCIE_CTX_C_GRX_P0 <41>
PCIE_CTX_C_GRX_N0 <41>

Slave GPU

Master GPU

4 4

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/02/01 2017/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

SKL-H(3/9) PEG,DMI

SKL-H(3/9) PEG,DMI

SKL-H(3/9) PEG,DMI

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

8 103Monday, January 09, 2017

8 103Monday, January 09, 2017

8 103Monday, January 09, 2017

E

1.0

1.0

1.0

A

B

C

D

E

SKYLAKE_HALO

BGA1440

5 OF 14

REV = 1 ?

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]

CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[17]
CFG[16]
CFG[19]
CFG[18]

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]

PROC_TDO

PROC_TDI

PROC_TMS

PROC_TCK

PROC_TRST#
PROC_PREQ#
PROC_PRDY#

CFG_RCOMP

+1.0V_VCCST

+1.0VS_VCCSTG

From EC(open-drain)

H_PROCHOT#<38,75>

DDR_VTT_CNTL to DDR
VTT supplied ramped
<35uS
(tCPU18)

(To VR)

BN25
BN27
BN26
BN28
BR20
BM20
BT20
BP20
BR23
BR22
BT23
BT22
BM19
BR19
BP19
BT19

BN23
BP23
BP22
BN22

XDP_BPM#0

BR27

XDP_BPM#1

BT27
BM31
BT30

CPU_XDP_TDO

BT28

CPU_XDP_TDI

BL32

CPU_XDP_TMS

BP28

CPU_XDP_TCK0

BR28

CPU_XDP_TRST#

BP30

XDP_PREQ#

BL30

XDP_PRDY#SKL_CNL_N

BP27

CFG_RCOMP

BT25

1 2

RC27 1K_0402_5%

12

RC31
1K_0402_5%

1 2

RC33 499_0402_1%

DDR_PG_CTRL

CFG0 <6>
CFG1 <6>
CFG2 <6>
CFG3 <6>
CFG4 <6>
CFG5 <6>
CFG6 <6>
CFG7 <6>
CFG8 <6>
CFG9 <6>
CFG10 <6>
CFG11 <6>
CFG12 <6>
CFG13 <6>
CFG14 <6>
CFG15 <6>

CFG17 <6>
CFG16 <6>
CFG19 <6>
CFG18 <6>

PAD

T25

@

PAD

T26

@

CPU_XDP_TDO <6,20>
CPU_XDP_TDI <6,20>
CPU_XDP_TMS <6,20>
CPU_XDP_TCK0 <6,20>

CPU_XDP_TRST# <6,24>
XDP_PREQ# <6,24>
XDP_PRDY# <6,24>

1 2

RC23 49.9_0402_1%

THERMTRIP#

PROCHOT

12

UC3

NC1VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

Change PN to SA00007UR00.

H_CPUPW RGD

PROCHOT

THERMTRIP#

1 2

CH49 .1U_0402_16V7K

1 2

CH50 .1U_0402_16V7K

1 2

CH51 .1U_0402_16V7K

ESD Reserve ,place close to cpu.

+1.2V_VDDQ

+3VS

CC19.1U_0402_16V7K

5

4

Y

12

RC36
220K_0402_5%

RC38
2M_0402_5%@

1 2

CRB 330K

CPU_BCLK<21>
CPU_BCLK#<21>

CPU_PCIBCLK<21>
CPU_PCIBCLK#<21>

CPU_24M<21>

1 1

H_SKTOCC#<20>

2 2

From EC OD output

EC_VCCST_PG_R<26,38>

3 3

PM_DOW N_R<19>

H_SKTOCC# H_SKTOCC#_R

1 2

@

RC32 1K_0402_5%

CPU_24M#<21>

CPU_SVID_CLK<81>

H_CPUPW RGD<20>
PLTRST_CPU#<19>
H_PM_SYNC<19>

H_PECI<19,38>

THERMTRIP#<19>

1 2

@

1 2

RC57 0_0402_5%
RC34 0_0402_5%@

+1.0V_VCCST

PAD

12

RC25
1K_0402_5%

1 2

RC28 60.4_0402_1%

RC30 20_0402_1%

SVID ALERT

+1.0V_VCCST

CPU_SVID_ALERT#

1 2

RC35 56_0402_5%

1 2

RC37 220_0402_5%

CPU_BCLK
CPU_BCLK#

CPU_PCIBCLK
CPU_PCIBCLK#

CPU_24M
CPU_24M#

CPU_SVID_ALERT#
CPU_SVID_CLK
CPU_SVID_DAT

PROCHOT
DDR_PG_CTRL

EC_VCCST_PG
H_CPUPW RGD

PLTRST_CPU#
H_PM_SYNC
PM_DOW N
H_PECI

THERMTRIP#

CATERR#

T69

@

FLOAT FOR SKL
GND FOR CNL

EC_VCCST_PG

12

Place the PU
resistors close to CPU

PM_DOW N

CPU_SVID_ALERT#_R <81>

B31
A32

D35
C36

E31
D31

BH31
BH32
BH29
BR30

BT13

H13

BT31
BP35
BM34
BP31
BT34

BR33

BN1

BM30

J31

UC1E

BCLKP
BCLKN

PCI_BCLKP
PCI_BCLKN

CLK24P
CLK24N

VIDALERT#
VIDSCK
VIDSOUT
PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD
PROCPWRGD

RESET#
PM_SYNC
PM_DOWN
PECI
THERMTRIP#

SKTOCC#
PROC_SELECT#

CATERR#

S

KL-H_BGA1440

@

Follow PDG1.0
Table 12-16

SVID DATA

4 4

+1.0V_VCCST

1 2

RC39 100_0402_1%

Place the PU
resistors close to CPU

Reference SKL EDS 0.85 Table 6-8
CFG signals internal PH default value = 1

Description

Stall reset sequence after PCU PLL

CFG[0]

CFG[4]

CFG[7]

CFG[1]
CFG[3]

CFG[8:19]

XEMC@

XEMC@

XEMC@

SM_PG_CTRL <77>

lock until de-asserted
— 1 = (Default) Normal Operation;

*

No stall.
— 0 = Stall.

Enable eDP

*

— 1 = Disabled.
— 0 = Enabled.

PEG Training:
— 1 = (default) PEG Train immediately

*

following RESET# de assertion.
— 0 = PEG Wait for BIOS for training

Reserved configuration lane.

PCIE
pore
assign

1 x 16
1 x 16

reverse
2 x 8

2 x 8
reverse
1 x 8
+ 2 x 4
1x8+2x4
reverse

Config. Signals

1 1 1
1 1
1 1

*

1

0 0 0

2x8 reverse

CFG 6 int. PU 1 V

CFG6
CFG7

CFG5
CFG2

CFG4

Display Port Presence : 0 enable / 1 disable

1 2

RC61 1K_0402_1%

1 2

RC62 1K_0402_1%

1 2

@

RC66 1K_0402_1%

1 2

RC26 1K_0402_1%

1 2

RC29 1K_0402_1%

1 2

RC24 1K_0402_1%

CFG[2]CFG[5]CFG[6]

0
0 0
00

+1.0V_VCCST

+1.0V_VCCST

0

1

CPU_SVID_DAT

Security Classification

Security Classification

CPU_SVID_DAT <81>

A

B

(To VR)

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/02/01 2017/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

SKL-H(4/9)CLK,GPIO

SKL-H(4/9)CLK,GPIO

SKL-H(4/9)CLK,GPIO

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

9 103Monday, January 09, 2017

9 103Monday, January 09, 2017

9 103Monday, January 09, 2017

E

1.0

1.0

1.0

A

1 1

2 2

3 3

VCC 27A (U 15W Dual Core GT2)

+VCCCORE +VCCCORE

AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37
AB38
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38
AF35
AF36
AF37
AF38

UC1G

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

K13

VCC

K14

VCC

L13

VCC

N13

VCC

N14

VCC

N30

VCC

N31

VCC

N32

VCC

N35

VCC

N36

VCC

N37

VCC

N38

VCC

P13

VCC

SKL-H_BGA1440

EV = 1 ?

R

@

SKYLAKE_HAL O

BGA1440

7 OF 14

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC_SENSE

VSS_SENSE

V32
V33
V34
V35
V36
V37
V38
W13
W14
W29
W30
W31
W32
W35
W36
W37
W38
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
L14
P29
P30
P31
P32
P33
P34
P35
P36
R13
R31
R32
R33
R34
R35
R36
R37
R38
T29
T30
T31
T32
T35
T36
T37
T38
U29
U30
U31
U32
U33
U34
U35
U36
V13
V14
V31
P14

Trace Length < 25 mils

AG37
AG38

VCCSENSE <81>

VSSSENSE <81>

B

BG34
BG35
BG36
BH33
BH34
BH35
BH36
BH37
BH38

BJ37
BJ38
BL36
BL37

BM36
BM37
BN36
BN37
BN38
BP37
BP38
BR37
BT37
BE38
BF13
BF14
BF29
BF30
BF31
BF32
BF35
BF36
BF37
BF38
BG29
BG30
BG31
BG32
BG33
BC36
BC37
BC38
BD13
BD14
BD29
BD30
BD31
BD32
BD33
BD34
BD35
BD36
BE31
BE32
BE37

UC1H

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

SKL-H_BGA1440

@

SKYLAKE_HAL O

BGA1440

8 OF 14

REV = 1

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

Rev_0. 53

?

C

PWR remove VCCGT 3/10

Reserve resistor to Gnd

AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BE33
BE34
BE35
BE36

12

RC67

@

0_0402_5%

D

SKYLAKE_HAL O

AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35

AJ36
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AL13
AL29
AL30
AL31
AL32
AL35
AL36
AL37
AL38

AM13
AM14
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AN13
AN14
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38

AP13
AP14
AP29
AP30
AP31
AP32
AP35
AP36
AP37
AP38

AR29
AR30
AR31
AR32
AR33
AR34
AR35
AR36

AT14
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38

AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38

UC1N

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

SKL-H_BGA1440

REV = 1

@

BGA1440

DEL VCCGT net 3/16

4 OF 14

1

VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX

VCCGT_SENSE

VSSGTX_SENSE

VSSGT_SENSE

VCCGTX_SENSE

E

AF29
AF30
AF31
AF32
AF33
AF34
AG13
AG14
AG31
AG32
AG33
AG34

EDS:Rail is unconnected for Processors w ithout GT3/4.

AG35
AG36
AH13
AH14
AH29
AH30
AH31
AH32
AJ13
AJ14

AH38
AH35
AH37
AH36

Trace Length < 25 mils

?

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

A

B

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

C

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

SKL-H(5/9)Power,SVID

SKL-H(5/9)Power,SVID

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

D

Date: Sheet o f

SKL-H(5/9)Power,SVID

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

E

1.0

1.0

10 103Monday, January 09, 2017

10 103Monday, January 09, 2017

10 103Monday, January 09, 2017

1.0

A

B

C

CPU_CORE/VCCGT/VCCSA decoupling capacitor place to PWR side

D

E

+1.0V_VCCST

1 2

+1.0VS_VCCSTG

+1.2V_VDDQ

+1.2V_VDDQ

RC40 0_0402_5%@

(1.0VS)

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

CC21

CC22

2

1 2

@

RC41 0_0603_5%

1 2

RC42 0_0402_5%@

1 1

2 2

3 3

+1.0V_VCCSFR

+1.0V_VCCST

1

CC23
1U_0402_6.3V6K

2

+VDDQ_CLK

10U_0603_6.3V6M

1

CC24

2

(1.2V)

+1.2V_VCCPLL_OC

1U_0402_6.3V6K

1

CC25

2

1 2

CC20 1U_0402_6.3V6K

Place at Back Side

BSC Side
Y

12

1U_0402_6.3V6K

1

CC26

2

Place at Back Side
BH13/G11

RVP11 47u*1,10u*7,1u*3
CAP place on PWR side.

RVP11
PWR NEED PROVIDE

0.95V FOR VCCIO

+VCCSA

+VCCIO

K29
K30
K31
K32
K33
K34
K35

M29
M30
M31
M32
M33
M34
M35
M36

AG12

G15
G17
G19
G21
H15
H16
H17
H19
H20
H21
H26
H27

J30

L31
L32
L35
L36
L37
L38

J15
J16
J17
J19
J20
J21
J26
J27

UC1I

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

SKL-H_BGA1440

EV = 1

R

@

SKYLAKE_HALO

BGA1440

9 OF 14

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDQC

VCCPLL_OC
VCCPLL_OC

VCCST
VCCSTG
VCCSTG

VCCPLL
VCCPLL

VCCSA_SENSE
VSSSA_SENSE

VCCIO_SENSE

VSSIO_SENSE

+1.2V_VDDQ

AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6

Y12
BH13

G11

H30
H29

120mA

G30
H28

145mA

J28

M38
M37

H14
J14

check PH/PL on pwr side ??
0219

?

VCCSA_SENSE
VSSSA_SENSE

VCCIO_SENSE
VSSIO_SENSE

+VDDQ_CLK
+1.2V_VCCPLL_OC

+1.0V_VCCST
+1.0VS_VCCSTG

+1.0V_VCCSFR

VCCSA_SENSE <81>
VSSSA_SENSE <81>

VCCIO_SENSE <80>
VSSIO_SENSE <80>

NOTE:
VCCPLL_OC is allowed to be turned off
during S3 & DS3 if it is not powered
directly from VDDQ

+1.2V_VDDQ

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CC27

CC28

2

1

1

CC29

2

2

10U_0603_6.3V6M

1

CC30

1

CC31

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CC33

CC32

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CC34

2

10U_0603_6.3V6M

1

CC35

CC36

2

22U_0603_6.3V6M

CC37

1

1

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

CC38

22U_0603_6.3V6M

CC39

1

2

CC40

1

2

+VCCIO

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CC41

2

2

10U_0603_6.3V6M

1

CC42

2

22U_0603_6.3V6M

CC69

1

CC43

1

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

CC70

1

2

22U_0603_6.3V6M

CC71

CC72

1

2

Place at Back SidePlace at Back Side Follow ORB 3/20

4 4

A

+1.35V_VDDQ_CPU : 10UF/6.3V/0603 *10
update CRB cap QTY

22UF/6.3V/0603 * 4

B

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/02/01 2017/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

SKL-H(6/9)POWER

SKL-H(6/9)POWER

SKL-H(6/9)POWER

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

11 103Monday, January 09, 2017

11 103Monday, January 09, 2017

11 103Monday, January 09, 2017

E

1.0

1.0

1.0

A

B

C

D

E

BR7

BP7

BN9
BN7
BN4
BN2

BM9
BM6
BM2

BH9
BH8
BH5
BH4
BH1

BE6
BD9

C17
C13

BT9
BT5

C9

SKYLAKE_HALO

UC1L

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL-H_BGA1440

REV = 1

@

BGA1440

2 OF 14

1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS

SKYLAKE_HALO

UC1J

C25
C23
C21
C19
C15
C11
C8
C5
BM29
BM25
BM18
BM11
BM8
BM7
BM5
BM3
BL38
BL35
BL13
BL6
BK25
BK22
BK13
BK6
BJ30
BJ29
BJ15
BJ12
BH11
BH10
BH7
BH6
BH3
BH2
BG37
BG14
BG6
BF34
BF6
BE30
BE5
BE4
BE3
BE2
BE1
BD38
BD37
BD12
BD11
BD10
BD8
BD7
BD6
BC33
BC14
BC13
BC6
BB30
BB29
BB6
BB5

C2
BT36
BT35
BT4
BT3
BR38

?

T27PAD @
T28PAD @
T29PAD @

EDRAM

CRB EDRAM

OPC_RCOMP
OPCE_RCOMP
OPCE_RCOMP2

BJ17
BJ19

BJ20
BK17
BK19
BK20

BL16

BL17

BL18

BL19

BL20

BL21
BM17
BN17

BJ23

BJ26

BJ27
BK23
BK26
BK27

BL23

BL24

BL25

BL26

BL27

BL28
BM24

BL15
BM16

BL22
BM22

BP15
BR15

BT15
BP16

BR16

BT16

BN15
BM15

BP17
BN16

BM14

BL14

BJ35

BJ36

AT13

AW13

AU13
AY13

BT29
BR25
BP25

SKL-H_BGA1440

@

BGA1440

VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VCCOPC_SENSE
VSSOPC_SENSE

RSVD
RSVD

VCCEOPIO
VCCEOPIO
VCCEOPIO

RSVD
RSVD
RSVD

VCCEOPIO_SENSE
VSSEOPIO_SENSE

RSVD
RSVD

VCC_OPC_1P8
VCC_OPC_1P8

RSVD
RSVD

ZVM#
MSM#

ZVM2#
MSM2#

OPC_RCOMP
OPCE_RCOMP
OPCE_RCOMP2

REV = 1

0 OF 14

1

?

SKYLAKE_HALO

UC1F

Y9
Y8
Y7

V6

U6

T9
T8
T7
T5
T4
T3
T2
T1

P6

N9
N8
N7
N6
N5
N4
N3
N2
N1

K9
K8
K7
K5
K4
K3
K2

SKL-H_BGA1440

@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA1440

6 OF 14

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NCTFVSS

K1
J36
J33
J32
J25
J22
J18
J10
J7
J4
H35
H32
H25
H22
H18
H12
H11
G28
G26
G24
G23
G22
G20
G18
G16
G14
G12
G10
G9
G8
G6
G5
G4
F36
F31
F29
F27
F25
F23
F21
F19
F17
F15
F13
F11
F9
F8
F5
F4
F3
F2
E38
E35
E34
E9
E4
D33
D30
D28
D26
D24
D22
D20
D18
D16
D14
D12
D10
D9
D6
D3
C37
C31
C29
C27

D38

?REV = 1

BA38
BA37
BA12
BA11
BA10

AY34
AY33
AY14

AY12
AW30
AW29
AW12

AW5
AW4
AW3
AW2

AW1
AV38
AV37
AU34
AU33
AU12
AU11
AU10

AT30

AT29
AR38

AR37
AR14
AR13

AP34
AP33
AP12
AP11
AP10

AN30
AN29
AN12

AM38
AM37
AM12

AL34

AL33

AL14

AL12

AL10

Y38
Y37
Y14

1 1

2 2

3 3

4 4

Y13
Y11
Y10

W34
W33
W12

V30
V29
V12

U38
U37

T34
T33
T14
T13
T12
T11
T10

R30
R29
R12

P38

P37

P12
N34

N33
N12

N11
N10

M14
M13
M12

L34

L33

L30

L29

K38

K11

K10

W5
W4
W3
W2
W1

M6

BB4
BB3
BB2
BB1

BA9
BA8
BA7
BA6

AU9
AU8
AU7
AU6

AT6

AR5
AR4
AR3
AR2
AR1

AP9
AP8

AN6
AN5

AM5
AM4
AM3
AM2
AM1

AL9
AL8
AL7
AL4

B9

SKYLAKE_HALO

UC1M

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL-H_BGA1440

REV = 1

@

BGA1440

1

3 OF 14

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS

AK30
AK29
AK4
AJ38
AJ37
AJ6
AJ5
AJ4
AJ3
AJ2
AJ1
AH34
AH33
AH12
AH6
AG30
AG29
AG11
AG10
AG8
AG7
AG6
AF14
AF13
AF12
AF4
AF3
AF2
AF1
AE34
AE33
AE6
AD30
AD29
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AC38
AC37
AC12
AC6
AC5
AC4
AC3
AC2
AC1
AB34
AB33
AB6
AA30
AA29
AA12
A30
A28
A26
A24
A22
A20
A18
A16
A14
A12
A10
A9
A6

B37
B3
A34
A4
A3

?

BT32
BT26
BT24
BT21
BT18
BT14
BT12

BR36
BR34
BR29
BR26
BR24
BR21
BR18
BR14
BR12

BP34
BP33
BP29
BP26
BP24
BP21
BP18
BP14
BP12

BN34
BN31
BN30
BN29
BN24
BN21
BN20
BN19
BN18
BN14
BN12

BM38
BM35
BM28
BM27
BM26
BM23
BM21
BM13
BM12

BL29
BK29
BK15
BK14

BJ32

BJ31

BJ25

BJ22
BH14
BH12

BG38
BG13
BG12
BF33
BF12
BE29

BC34
BC12
BB12

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/02/01 2017/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

SKL-H(8/9)GND

SKL-H(8/9)GND

SKL-H(8/9)GND

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1.0

1.0

1.0

12 103Monday, January 09, 2017

12 103Monday, January 09, 2017

12 103Monday, January 09, 2017

E

A

B

C

D

E

1 1

2 2

3 3

PROC_TRIGIN_R<24>

PROC_TRIGOUT_R<24>

1 2

RC45 30_0402_1%

PROC_TRIGIN_R
PROC_TRIGOUT

BR1

BT2

BN35

J24

H24
BN33
BL34

N29

R14
AE29
AA14

A36
A37

H23

J23
F30

E30
B30

C30

BR35
BR31
BH30

D1

E1
E3
E2

G3

J3

UC1K

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD
RSVD

RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD

PROC_TRIGIN
PROC_TRIGOUT

RSVD
RSVD

RSVD
RSVD

RSVD
RSVD

RSVD
RSVD
RSVD

SKL-H_BGA1440

@

SKYLAKE_HALO

BGA1440

11 OF 14

EV = 1

Rev_0 .53

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD
RSVD

VSS

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD
RSVD

RSVD
RSVD

VSS

RSVD_TP
RSVD_TP

RSVD
RSVD
RSVD

NCTF
NCTF
NCTF
NCTF
NCTF
NCTF

BM33
BL33

BJ14
BJ13

BK28
BJ28

BJ18
BJ16

BK16

BK24
BJ24

BK21
BJ21

BT17
BR17

BK18
BJ34

BJ33

G13
AJ8
BL31

NCTF_0

B2

NCTF_1

B38

NCTF_2

BP1

NCTF_3

BR2

NCTF_4

C1

NCTF_5

C38

?R

T13 PAD@
T14 PAD@
T15 PAD@
T16 PAD@
T17 PAD@
T18 PAD@

4 4

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/02/01 2017/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

SKL-H(9/9)RSVD

SKL-H(9/9)RSVD

SKL-H(9/9)RSVD

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1.0

1.0

1.0

13 103Monday, January 09, 2017

13 103Monday, January 09, 2017

13 103Monday, January 09, 2017

E

5

4

3

2

1

CHANNEL-A

TOP DIMM1

REVERSE TYPE

Interleaved Memory

TOP: JDIMM1 CONN Non-ECC DIMM

D D

12

@

12

RD1
0_0402_ 5%

RD3

@

0_0402_ 5%

12

@

12

RD4
0_0402_ 5%

RD5
0_0402_ 5%

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL A :
WRITE ADDRESS: 0XA0
READ ADDRESS: 0XA1
SA0 = 0; SA1 = 0; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S
STRETCH GOAL IS 2133 MT/S

C C

B B

Layout Note:
Place near JDIMM1.257,259

+2.5V +0.6VS_VTT

10U_0603_6.3V6M

1

1

CD3

2

2

Layout Note:
PLACE THE CAP near JDIMM1. 164

+0.6V_DDR_ VREFCA

2

CD11
.1U_0402 _16V7K

1

10uF*2
1uF*2

1U_0402_6.3V6K

10U_0603_6.3V6M

1U_0402_6.3V6K

1

1

CD5

CD4

CD6

2

2

2.2uF*1

0.1uF*1

2

CD12

2.2U_040 2_6.3V6M

1

+3VS+3VS+3VS

12

@

@

12

Layout Note:
Place near JDIMM1.258

1

2

PLACE NEAR TO PIN

+3VS

.1U_0402_16V7K

2

1

RD2
0_0402_ 5%

SA2_CHA_ DIM1SA1_CHA_ DIM1SA0_CHA _DIM1

RD6
0_0402_ 5%

10U_0603_6.3V6M

CD7

2

CD1

1

+1.2V_VDDQ

@

+0.6V_DDR_ VREFCA

10uF*2
1uF*1

1U_0402_6.3V6K

10U_0603_6.3V6M

1

1

CD9

CD8

2

2

2.2U_0402_6.3V6M

CD2

+3VS

DDR_A_D[0..15]<7,15>
DDR_A_D[16..31]<7,15>
DDR_A_D[32..47]<7,15>
DDR_A_D[48..63]<7,15>

JDIMM1B

STD

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND

SP07001CU00

LCN_DAN05 -Q0526-0103

CONN@

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19

VPP1
VPP2

141
142
147
148
153
154
159
160
163

258

VTT

257
259

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

261

GND

+1.2V_VDDQ

+0.6VS_VTT

+2.5V

+1.2V_VDDQ

need PU when use E CC dimm

DDR_DRAMRST#_R

RD7

240_040 2_1%

12

2

1

+1.2V_VDDQ

.1U_0402_16V7K

CD10

XEMC@

PLACE NEAR TO SODIMM

(5.2 mm)

DDR_A_CLK 0<7>
DDR_A_CLK #0<7>
DDR_A_CLK 1<7>
DDR_A_CLK #1<7>

DDR_A_CKE 0<7>
DDR_A_CKE 1<7>

DDR_A_CS# 0<7>
DDR_A_CS# 1<7>

DDR_A_ODT0<7>
DDR_A_ODT1<7>

DDR_A_BG0<7,1 5>
DDR_A_BG1<7,1 5>
DDR_A_BA0<7,15>
DDR_A_BA1<7,15>

DDR_A_MA0<7,15>
DDR_A_MA1<7,15>
DDR_A_MA2<7,15>
DDR_A_MA3<7,15>
DDR_A_MA4<7,15>
DDR_A_MA5<7,15>
DDR_A_MA6<7,15>
DDR_A_MA7<7,15>
DDR_A_MA8<7,15>
DDR_A_MA9<7,15>
DDR_A_MA1 0<7,15>
DDR_A_MA1 1<7,15>
DDR_A_MA1 2<7,15>
DDR_A_MA1 3<7,15>
DDR_A_W E#<7,15>
DDR_A_CAS #<7,15>
DDR_A_RAS #<7,15>

DDR_A_ACT#<7,15 >
DDR_A_PAR<7,15>

DDR_A_ALERT#<7,15>

DDR_DRAMRST#_R<15,16,17,20>

PCH_SMBDA TA_R<15,16,17,20 ,40>
PCH_SMBCL K_R<15,16,17,2 0,40>

DIMM1_CHA_ EVENT#

For ECC DIMM

DDR_A_CLK 0
DDR_A_CLK #0
DDR_A_CLK 1
DDR_A_CLK #1

DDR_A_CKE 0
DDR_A_CKE 1

DDR_A_CS# 0
DDR_A_CS# 1

DDR_A_ODT0
DDR_A_ODT1

DDR_A_BG0
DDR_A_BG1
DDR_A_BA0
DDR_A_BA1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA1 0
DDR_A_MA1 1
DDR_A_MA1 2
DDR_A_MA1 3
DDR_A_W E#
DDR_A_CAS #
DDR_A_RAS #

DDR_A_ACT#
DDR_A_PAR

DDR_A_ALERT#
DDR_DRAMRST#_R

PCH_SMBDA TA_R
PCH_SMBCL K_R

SA2_CHA_ DIM1
SA1_CHA_ DIM1
SA0_CHA_ DIM1

JDIMM1A

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_W E#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

SP07001CU00

LCN_DAN05 -Q0526-0103

conn need link

CONN@

STD

DQS0(T)

DQS0#(C)

DQS1(T)

DQS1#(C)

DQS2(T)

DQS2#(C)

DQS3(T)

DQS3#(C)

DQS4(T)

DQS4#(C)

DQS5(T)

DQS5#(C)

DQS6(T)

DQS6#(C)

DQS7(T)

DQS7#(C)

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DDR_A_D5

8

DQ0

DDR_A_D0

7

DQ1

DDR_A_D2

20

DQ2

DDR_A_D3

21

DQ3

DDR_A_D1

4

DQ4

DDR_A_D4

3

DQ5

DDR_A_D6

16

DQ6

DDR_A_D7

17

DQ7

DDR_A_DQS 0

13

DDR_A_DQS #0

11

DDR_A_D8

28

DQ8

DDR_A_D12

29

DQ9

DDR_A_D14

41

DDR_A_D11

42

DDR_A_D9

24

DDR_A_D13

25

DDR_A_D10

38

DDR_A_D15

37

DDR_A_DQS 1

34

DDR_A_DQS #1

32

DDR_A_D17

50

DDR_A_D20

49

DDR_A_D23

62

DDR_A_D18

63

DDR_A_D16

46

DDR_A_D21

45

DDR_A_D19

58

DDR_A_D22

59

DDR_A_DQS 2

55

DDR_A_DQS #2

53

DDR_A_D25

70

DDR_A_D28

71

DDR_A_D30

83

DDR_A_D31

84

DDR_A_D24

66

DDR_A_D29

67

DDR_A_D27

79

DDR_A_D26

80

DDR_A_DQS 3

76

DDR_A_DQS #3

74

DDR_A_D32

174

DDR_A_D37

173

DDR_A_D35

187

DDR_A_D39

186

DDR_A_D36

170

DDR_A_D33

169

DDR_A_D34

183

DDR_A_D38

182

DDR_A_DQS 4

179

DDR_A_DQS #4

177

DDR_A_D44

195

DDR_A_D45

194

DDR_A_D42

207

DDR_A_D43

208

DDR_A_D41

191

DDR_A_D40

190

DDR_A_D46

203

DDR_A_D47

204

DDR_A_DQS 5

200

DDR_A_DQS #5

198

DDR_A_D48

216

DDR_A_D50

215

DDR_A_D53

228

DDR_A_D55

229

DDR_A_D52

211

DDR_A_D49

212

DDR_A_D54

224

DDR_A_D51

225

DDR_A_DQS 6

221

DDR_A_DQS #6

219

DDR_A_D60

237

DDR_A_D57

236

DDR_A_D62

249

DDR_A_D58

250

DDR_A_D56

232

DDR_A_D61

233

DDR_A_D59

245

DDR_A_D63

246

DDR_A_DQS 7

242

DDR_A_DQS #7

240

DDR_A_DQS 0 <7,15>

DDR_A_DQS #0 <7,15>

DDR_A_DQS 1 <7,15>

DDR_A_DQS #1 <7,15>

DDR_A_DQS 2 <7,15>

DDR_A_DQS #2 <7,15>

DDR_A_DQS 3 <7,15>

DDR_A_DQS #3 <7,15>

DDR_A_DQS 4 <7,15>

DDR_A_DQS #4 <7,15>

DDR_A_DQS 5 <7,15>

DDR_A_DQS #5 <7,15>

DDR_A_DQS 6 <7,15>

DDR_A_DQS #6 <7,15>

DDR_A_DQS 7 <7 ,15>

DDR_A_DQS #7 <7,15>

Layout Note:
Place near JDIMM1

10uF*6

uF*8

1
330uF*1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD17

CD16

1

1

2

2

A A

CD19

CD18

1

2

5

CD20

1

2

CD21

1

1

2

2

+1.2V_VDDQ+1.2V_VDDQ

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

CD22

CD23

1

1

2

2

@

@

1U_0402_6.3V6K

1

1

CD24

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD26

CD25

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CD27

2

4

1U_0402_6.3V6K

1

1

CD29

CD28

2

2

+1.2V_VDDQ

1U_0402_6.3V6K

1

CD30

2

1

+

CD31

CD32
330U_D3_ 2.5VY_R6M

SGA0000 6A00

2

@

3

+1.2V_VDDQ

DIMM Side

+0.6V_DDR_ VREFCA

RD8

Issued Date

Issued Date

Issued Date

1 2

1 2

1K_0402 _1%

RD10
1K_0402 _1%

2

CD14
.1U_0402 _16V7K

1

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

2

CD13
.1U_0402 _16V7K

1

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

1 2

RD9

2_0402_ 1%

Deciphered Date

Deciphered Date

Deciphered Date

2

CPU Side

+0.6V_VRE FCA

1

CD15

0.022U_0 402_25V 7K

2

RD11

24.9_0402_1%

1 2

VREF traces should be at least 20 mils
wide with 20 mils spacing to other
signals

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P12-DDRIV_CHA: DIMM0

P12-DDRIV_CHA: DIMM0

P12-DDRIV_CHA: DIMM0

Document Number Re v

Document Number Re v

Document Number Re v

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

1.0

1.0

14 103Monday, January 09, 2017

14 103Monday, January 09, 2017

14 103Monday, January 09, 2017

1.0

5

4

3

2

1

(5.2 mm)

DDR_A_CLK 2
DDR_A_CLK #2
DDR_A_CLK 3
DDR_A_CLK #3

DDR_A_CKE 2
DDR_A_CKE 3

DDR_A_CS# 2
DDR_A_CS# 3

DDR_A_ODT2
DDR_A_ODT3

DDR_A_BG0
DDR_A_BG1
DDR_A_BA0
DDR_A_BA1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA1 0
DDR_A_MA1 1
DDR_A_MA1 2
DDR_A_MA1 3
DDR_A_W E#
DDR_A_CAS #
DDR_A_RAS #

DDR_A_ACT#
DDR_A_PAR

DDR_A_ALERT#
DIMM2_CHA_ EVENT#
DDR_DRAMRST#_R

PCH_SMBDA TA_R

PCH_SMBCL K_R

SA2_CHA_ DIM2
SA1_CHA_ DIM2
SA0_CHA_ DIM2

JDIMM2A

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_W E#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

SP07001D800

LCN_DAN05 -Q0526-0102

STD

CONN@

DQS0(T)

DQS0#(C)

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQS1(T)

DQS1#(C)

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQS2(T)

DQS2#(C)

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS3(T)

DQS3#(C)

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS4(T)

DQS4#(C)

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQS5(T)

DQS5#(C)

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQS6(T)

DQS6#(C)

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS7(T)

DQS7#(C)

conn need link

DDR_A_D5

8

DQ0

DDR_A_D0

7

DQ1

DDR_A_D2

20

DQ2

DDR_A_D3

21

DQ3

DDR_A_D1

4

DQ4

DDR_A_D4

3

DQ5

DDR_A_D6

16

DQ6

DDR_A_D7

17

DQ7

DDR_A_DQS 0

13

DDR_A_DQS #0

11

DDR_A_D8

28

DQ8

DDR_A_D12

29

DQ9

DDR_A_D14

41

DDR_A_D11

42

DDR_A_D9

24

DDR_A_D13

25

DDR_A_D10

38

DDR_A_D15

37

DDR_A_DQS 1

34

DDR_A_DQS #1

32

DDR_A_D17

50

DDR_A_D20

49

DDR_A_D23

62

DDR_A_D18

63

DDR_A_D16

46

DDR_A_D21

45

DDR_A_D19

58

DDR_A_D22

59

DDR_A_DQS 2

55

DDR_A_DQS #2

53

DDR_A_D25

70

DDR_A_D28

71

DDR_A_D30

83

DDR_A_D31

84

DDR_A_D24

66

DDR_A_D29

67

DDR_A_D27

79

DDR_A_D26

80

DDR_A_DQS 3

76

DDR_A_DQS #3

74

DDR_A_D32

174

DDR_A_D37

173

DDR_A_D35

187

DDR_A_D39

186

DDR_A_D36

170

DDR_A_D33

169

DDR_A_D34

183

DDR_A_D38

182

DDR_A_DQS 4

179

DDR_A_DQS #4

177

DDR_A_D44

195

DDR_A_D45

194

DDR_A_D42

207

DDR_A_D43

208

DDR_A_D41

191

DDR_A_D40

190

DDR_A_D46

203

DDR_A_D47

204

DDR_A_DQS 5

200

DDR_A_DQS #5

198

DDR_A_D48

216

DDR_A_D50

215

DDR_A_D53

228

DDR_A_D55

229

DDR_A_D52

211

DDR_A_D49

212

DDR_A_D54

224

DDR_A_D51

225

DDR_A_DQS 6

221

DDR_A_DQS #6

219

DDR_A_D60

237

DDR_A_D57

236

DDR_A_D62

249

DDR_A_D58

250

DDR_A_D56

232

DDR_A_D61

233

DDR_A_D59

245

DDR_A_D63

246

DDR_A_DQS 7

242

DDR_A_DQS #7

240

DDR_A_DQS 0 <7,14>

DDR_A_DQS #0 <7,14>

DDR_A_DQS 1 <7,14>

DDR_A_DQS #1 <7,14>

DDR_A_DQS 2 <7,14>

DDR_A_DQS #2 <7,14>

DDR_A_DQS 3 <7,14>

DDR_A_DQS #3 <7,14>

DDR_A_DQS 4 <7,14>

DDR_A_DQS #4 <7,14>

DDR_A_DQS 5 <7,14>

DDR_A_DQS #5 <7,14>

DDR_A_DQS 6 <7,14>

DDR_A_DQS #6 <7,14>

DDR_A_DQS 7 <7,14>

DDR_A_DQS #7 <7,14>

12

+1.2V_VDDQ

STD

DDR_A_CLK 2<7>

DDR_A_CLK #2<7>
DDR_A_CLK 3<7>
DDR_A_CLK #3<7>

DDR_A_CKE 2<7>

DDR_A_CKE 3<7>

DDR_A_CS# 2<7>

DDR_A_CS# 3<7>

DDR_A_ODT2<7>

DDR_A_ODT3<7>

DDR_A_BG0<7,14>

DDR_A_BG1<7,14>

DDR_A_BA0<7,14>

DDR_A_BA1<7,14>

DDR_A_MA0<7,14 >

DDR_A_MA1<7,14 >

DDR_A_MA2<7,14 >

DDR_A_MA3<7,14 >

DDR_A_MA4<7,14 >

DDR_A_MA5<7,14 >

DDR_A_MA6<7,14 >

DDR_A_MA7<7,14 >

DDR_A_MA8<7,14 >

DDR_A_MA9<7,14 >

DDR_A_MA1 0<7,14>

DDR_A_MA1 1<7,14>

DDR_A_MA1 2<7,14>

DDR_A_MA1 3<7,14>

DDR_A_W E#<7,14>

DDR_A_CAS #<7,14>

DDR_A_RAS #<7,14>

DDR_A_ACT#<7,14>

DDR_A_PAR<7,14>

DDR_A_ALERT#<7,14>

DDR_DRAMRST#_R<14,16,17,20>

PCH_SMBDA TA_R<14,16,17,20 ,40>
PCH_SMBCL K_R<14,16,17,2 0,40>

For ECC DIMM

CHANNEL-A

BOT: JDIMM2 CONN

D D

C C

B B

12

RD12

@

0_0402_ 5%

12

RD15

@

0_0402_ 5%

@

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL A :
WRITE ADDRESS: 0XA2
READ ADDRESS: 0XA3
SA0 = 1; SA1 = 0; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S
STRETCH GOAL IS 2133 MT/S

Layout Note:
P

lace near JDIMM2.257,259

+2.5V

Layout Note:
PLACE THE CAP WITHIN 200 MILS
FROM THE JDIMM2

+0.6V_DDR_ VREFCA

2

CD42
.1U_0402 _16V7K

1

10uF*2
1uF*2

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

1

1

CD37

CD35

CD36

2

2

2

CD43

2.2U_040 2_6.3V6M

1

Layout Note:
Place near JDIMM2

1U_0402_6.3V6K

1

CD38

2

2.2uF*1

0.1uF*1

Non-ECC DIMM

12

RD13
0_0402_ 5%

12

RD16

@

0_0402_ 5%

Layout Note:
Place near JDIMM2.258

BOT DIMM2

+3VS+3VS+3VS

12

RD14

@

0_0402_ 5%

SA2_CHA_ DIM2SA1_CHA_ DIM2SA0_CHA_ DIM2

12

RD17

@

0_0402_ 5%

+0.6VS_VTT

PLACE NEAR TO PIN

10uF*2
1uF*1

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

1

2

CD41

CD40

CD39

2

2

+3VS

.1U_0402_16V7K

2.2U_0402_6.3V6M

2

2

CD34

CD33

1

1

Interleaved Memory

DDR_A_D[0..15]<7,14>
DDR_A_D[16..31]<7,14>
DDR_A_D[32..47]<7,14>
DDR_A_D[48..63]<7,14>

JDIMM2B

CONN@

STD

+1.2V_VDDQ

+0.6V_DDR_ VREFCA

+3VS

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND

SP07001D800

LCN_DAN05 -Q0526-0102

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19

VPP1
VPP2

141
142
147
148
153
154
159
160
163

258

VTT

257
259

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

261

GND

+1.2V_VDDQ

+0.6VS_VTT

+2.5V

+1.2V_VDDQ

need PU when use E CC dimm

RD18

240_040 2_1%

10uF*6

+1.2V_VDDQ +1.2V_VDDQ

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD45

CD44

1

1

1

2

2

2

A A

5

1uF*8

10U_0603_6.3V6M

10U_0603_6.3V6M

CD46

CD47

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD48

1

2

10U_0603_6.3V6M

@

@

CD50

CD51

CD49

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD53

CD52

2

2

1U_0402_6.3V6K

1

1

1

CD54

CD55

CD56

2

2

2

4

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD57

CD59

CD58

2

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

3

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P13-DDRIV_CHA: DIMM1

P13-DDRIV_CHA: DIMM1

P13-DDRIV_CHA: DIMM1

Document Number Re v

Document Number Re v

Document Number Re v

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

15 103Monday, January 09, 2017

15 103Monday, January 09, 2017

15 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

CHANNEL-B

TOP: JDIMM3 CONN

D D

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

C C

B B

A A

12

RD19

0_0402_ 5%

@

12

RD22

@

0_0402_ 5%

SPD ADDRESS FOR CHANNEL B :
WRITE ADDRESS: 0XA4
READ ADDRESS: 0XA3
SA0 = 0; SA1 = 1; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S
STRETCH GOAL IS 2133 MT/S

Layout Note:
Place near JDIMM3.257,259

10uF*2
1uF*2

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1

1

CD62

2

2

Layout Note:
PLACE THE CAP WITHIN 200 MILS
FROM THE JDIMM3

+0.6V_DDRB _VREFCA

2

CD69
.1U_0402 _16V7K

1

Layout Note:
Place near JDIMM3

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

1

1

CD63

CD64

CD65

2

2

2.2uF*1

0.1uF*1

2

CD70

2.2U_040 2_6.3V6M

1

10U_0603_6.3V6M

10U_0603_6.3V6M

CD74

CD75

CD73

1

1

2

2

Non-ECC DIMM

12

RD20

@

0_0402_ 5%

12

RD23

@

0_0402_ 5%

10uF*6
1uF*8
330uF*1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD76

CD77

1

1

1

2

2

2

+3VS+3VS+3VS

12

@

12

Layout Note:
Place near JDIMM3.258

+0.6VS_VTT+2.5V

PLACE NEAR TO PIN

+3VS

10U_0603_6.3V6M

CD78

CD79

1

2

@

TOP DIMM3

RD21

0_0402_ 5%

SA2_CHB_ DIM3SA1_CHB_ DIM3SA0_CHB_DIM3

RD24

@

0_0402_ 5%

10uF*2
1uF*1

10U_0603_6.3V6M

1U_0402_6.3V6K

10U_0603_6.3V6M

1

1

1

CD67

CD68

CD66

2

2

2

.1U_0402_16V7K

2.2U_0402_6.3V6M

2

2

CD60

CD61

1

1

+1.2V_VDDQ+1.2V_VDDQ

10U_0603_6.3V6M

CD80

1

2

@

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

1

CD84

CD83

2

2

Interleaved Memory

DDR_B_D[0..15]<7,17>
DDR_B_D[16..31]<7,17>
DDR_B_D[32..47]<7,17>
DDR_B_D[48..63]<7,17>

+1.2V_VDDQ

+0.6V_DDRB _VREFCA

+3VS

JDIMM3B

CONN@

STD

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND

SP07001D100

S SOCKET L CN DAN05-Q0 926-0103 260P DDR4

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19

VPP1
VPP2

141
142
147
148
153
154
159
160
163

258

VTT

257
259

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

261

GND

+1.2V_VDDQ

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

1

CD86

CD87

CD85

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD88

CD89

2

2

1

+

CD90

CD91
330U_D3_ 2.5VY_R6M

SGA0000 6A00

2

+1.2V_VDDQ

+0.6VS_VTT

+2.5V

+1.2V_VDDQ

need PU when use E CC dimm

2

@

1

2

1

RD25

240_040 2_1%

DDR_DRAMRST#_R

PLACE NEAR TO SODIMM

CD71
.1U_0402 _16V7K

CD81
.1U_0402 _16V7K

REVERSE TYPE

DDR_B_CLK 0<7>

DDR_B_CLK #0<7>

DDR_B_CLK 1<7>

DDR_B_CLK #1<7>

DDR_B_CKE 0<7>

DDR_B_CKE 1<7>

DDR_B_CS# 0<7>

DDR_B_CS# 1<7>

DDR_B_ODT0<7>

DDR_B_ODT1<7>

DDR_B_BG0<7,17>

DDR_B_BG1<7,17>

DDR_B_BA0<7,17>

DDR_B_BA1<7,17>

DDR_B_MA0<7,17 >

DDR_B_MA1<7,17 >

DDR_B_MA2<7,17 >

DDR_B_MA3<7,17 >

DDR_B_MA4<7,17 >

DDR_B_MA5<7,17 >

DDR_B_MA6<7,17 >

DDR_B_MA7<7,17 >

DDR_B_MA8<7,17 >

DDR_B_MA9<7,17 >

DDR_B_MA1 0<7,17>

DDR_B_MA1 1<7,17>

DDR_B_MA1 2<7,17>

DDR_B_MA1 3<7,17>

DDR_B_W E#<7,17>

DDR_B_CAS #<7,17>

DDR_B_RAS #<7,17>

DDR_B_ACT#<7,17>

DDR_B_PAR<7,17>

+1.2V_VDDQ

2

1

RD26
1K_0402 _1%

RD28
1K_0402 _1%

DDR_DRAMRST#_R<14,15,17,20>

.1U_0402_16V7K

CD119

XEMC@

+0.6V_DDRB _VREFCA

DDR_B_ALERT#<7,17>

PCH_SMBDA TA_R<14,15,17,20 ,40>
PCH_SMBCL K_R<14,15,17,2 0,40>

DIMM Side

12

+1.2V_VDDQ

1 2

1 2

DDR_B_CLK 0
DDR_B_CLK #0
DDR_B_CLK 1
DDR_B_CLK #1

DDR_B_CKE 0
DDR_B_CKE 1

DDR_B_CS# 0
DDR_B_CS# 1

DDR_B_ODT0
DDR_B_ODT1

DDR_B_BG0
DDR_B_BG1
DDR_B_BA0
DDR_B_BA1

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA1 0
DDR_B_MA1 1
DDR_B_MA1 2
DDR_B_MA1 3
DDR_B_W E#
DDR_B_CAS #
DDR_B_RAS #

DDR_B_ACT#
DDR_B_PAR

DDR_B_ALERT#
DIMM3_CHB_ EVENT#
DDR_DRAMRST#_R

PCH_SMBDA TA_R

PCH_SMBCL K_R

SA2_CHB_ DIM3
SA1_CHB_ DIM3
SA0_CHB_ DIM3

For ECC DIMM

1 2

RD27

2_0402_ 1%

(9.2 mm)

JDIMM3A

STD

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_W E#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

SP07001D100

S SOCKET L CN DAN05-Q0 926-0103 260P DDR4

CPU Side

+0.6V_B_ VREFDQ

REF traces should be at least 20 mils

V

1

2

1 2

wide with 20 mils spacing to other
signals

CD82

0.022U_0 402_25V 7K

RD29

24.9_0402_1%

CONN@

DQS0(T)

DQS0#(C)

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQS1(T)

DQS1#(C)

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQS2(T)

DQS2#(C)

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS3(T)

DQS3#(C)

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS4(T)

DQS4#(C)

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQS5(T)

DQS5#(C)

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQS6(T)

DQS6#(C)

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS7(T)

DQS7#(C)

conn need link

DDR_B_D0

8

DQ0

DDR_B_D1

7

DQ1

DDR_B_D7

20

DQ2

DDR_B_D3

21

DQ3

DDR_B_D5

4

DQ4

DDR_B_D4

3

DQ5

DDR_B_D2

16

DQ6

DDR_B_D6

17

DQ7

DDR_B_DQS 0

13

DDR_B_DQS #0

11

DDR_B_D9

28

DQ8

DDR_B_D14

29

DQ9

DDR_B_D13

41

DDR_B_D15

42

DDR_B_D8

24

DDR_B_D10

25

DDR_B_D11

38

DDR_B_D12

37

DDR_B_DQS 1

34

DDR_B_DQS #1

32

DDR_B_D17

50

DDR_B_D18

49

DDR_B_D19

62

DDR_B_D21

63

DDR_B_D16

46

DDR_B_D22

45

DDR_B_D23

58

DDR_B_D20

59

DDR_B_DQS 2

55

DDR_B_DQS #2

53

DDR_B_D25

70

DDR_B_D30

71

DDR_B_D29

83

DDR_B_D24

84

DDR_B_D28

66

DDR_B_D27

67

DDR_B_D31

79

DDR_B_D26

80

DDR_B_DQS 3

76

DDR_B_DQS #3

74

DDR_B_D39

174

DDR_B_D35

173

DDR_B_D36

187

DDR_B_D32

186

DDR_B_D38

170

DDR_B_D34

169

DDR_B_D37

183

DDR_B_D33

182

DDR_B_DQS 4

179

DDR_B_DQS #4

177

DDR_B_D41

195

DDR_B_D45

194

DDR_B_D46

207

DDR_B_D43

208

DDR_B_D40

191

DDR_B_D44

190

DDR_B_D42

203

DDR_B_D47

204

DDR_B_DQS 5

200

DDR_B_DQS #5

198

DDR_B_D51

216

DDR_B_D52

215

DDR_B_D55

228

DDR_B_D53

229

DDR_B_D48

211

DDR_B_D54

212

DDR_B_D49

224

DDR_B_D50

225

DDR_B_DQS 6

221

DDR_B_DQS #6

219

DDR_B_D56

237

DDR_B_D57

236

DDR_B_D60

249

DDR_B_D63

250

DDR_B_D61

232

DDR_B_D59

233

DDR_B_D58

245

DDR_B_D62

246

DDR_B_DQS 7

242

DDR_B_DQS #7

240

DDR_B_DQS 0 <7,17>

DDR_B_DQS #0 <7,17>

DDR_B_DQS 1 <7,17>

DDR_B_DQS #1 <7,17>

DDR_B_DQS 2 <7,17>

DDR_B_DQS #2 <7,17>

DDR_B_DQS 3 <7,17>

DDR_B_DQS #3 <7,17>

DDR_B_DQS 4 <7,17>

DDR_B_DQS #4 <7,17>

DDR_B_DQS 5 <7,17>

DDR_B_DQS #5 <7,17>

DDR_B_DQS 6 <7,17>

DDR_B_DQS #6 <7,17>

DDR_B_DQS 7 <7,17>

DDR_B_DQS #7 <7,17>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

5

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P14-DDRIV_CHB: DIMM0

P14-DDRIV_CHB: DIMM0

P14-DDRIV_CHB: DIMM0

Document Number Re v

Document Number Re v

Document Number Re v

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

16 103Monday, January 09, 2017

16 103Monday, January 09, 2017

16 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

CHANNEL-B

BOT: JDIMM4 CONN Non-ECC DIMM

D D

12

RD30

@

0_0402_ 5%

12

RD33

@

0_0402_ 5%

12

RD31
0_0402_ 5%

12

RD34

0_0402_ 5%

@

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL B :
WRITE ADDRESS: 0XA6
READ ADDRESS: 0XA7
SA0 = 1; SA1 = 1; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S

C C

B B

STRETCH GOAL IS 2133 MT/S

Layout Note:
P

lace near JDIMM4.257,259

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CD94

CD95

2

2

+0.6V_DDRB _VREFCA

2

CD101
.1U_0402 _16V7K

1

10uF*2
1uF*2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

CD96

2

2

CD102

2.2U_040 2_6.3V6M

1

CD97

2.2uF*1

0.1uF*1

+2.5V

Layout Note:
PLACE THE CAP WITHIN 200 MILS
FROM THE JDIMM4

+3VS+3VS+3 VS

@

12

@

12

Layout Note:
Place near JDIMM4.258

+0.6VS_VTT

10U_0603_6.3V6M

1

CD98

2

BOT DIMM4 (9.2 mm)

Interleaved Memory

DDR_B_D[0..15]<7,16>

RD32

0_0402_ 5%

SA2_CHB_ DIM4SA1_CHB_ DIM4SA0_CHB_ DIM4

RD35

@

0_0402_ 5%

10uF*2
1uF*1

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

1

CD99

CD100

2

DDR_B_D[16..31]<7,16 >
DDR_B_D[32..47]<7,16 >
DDR_B_D[48..63]<7,16 >

+1.2V_VDDQ

+3VS

.1U_0402_16V7K

2.2U_0402_6.3V6M

+0.6V_DDRB _VREFCA

2

2

CD92

CD93

1

1

LACE NEAR TO PIN

P

JDIMM4B

STD

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND

SP07001DO00

LCN_DAN05 -Q0926-0102

CONN@

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19

VPP1
VPP2

141
142
147
148
153
154
159
160
163

258

VTT

257
259

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

261

GND

+1.2V_VDDQ

+0.6VS_VTT
+2.5V

RD36

+1.2V_VDDQ

need PU when use E CC dimm

240_040 2_1%

+1.2V_VDDQ

DDR_DRAMRST#_R

PLACE NEAR TO SODIMM

Layout Note:
Place near JDIMM4

STD

CONN@

DDR_B_CLK 2<7>
DDR_B_CLK #2<7>

DDR_B_CLK 3<7>

DDR_B_CLK #3<7>
DDR_B_CKE 2<7>

DDR_B_CKE 3<7>
DDR_B_CS# 2<7>

DDR_B_CS# 3<7>

DDR_B_ODT2<7>
DDR_B_ODT3<7>

DDR_B_BG0<7,16>
DDR_B_BG1<7,16>
DDR_B_BA0<7,16>
DDR_B_BA1<7,16>

DDR_B_MA0<7,16 >
DDR_B_MA1<7,16 >
DDR_B_MA2<7,16 >
DDR_B_MA3<7,16 >
DDR_B_MA4<7,16 >
DDR_B_MA5<7,16 >
DDR_B_MA6<7,16 >
DDR_B_MA7<7,16 >
DDR_B_MA8<7,16 >
DDR_B_MA9<7,16 >
DDR_B_MA1 0<7,16>
DDR_B_MA1 1<7,16>
DDR_B_MA1 2<7,16>
DDR_B_MA1 3<7,16>
DDR_B_W E#<7,16>
DDR_B_CAS #<7,16>
DDR_B_RAS #<7,16>

DDR_B_ACT#<7,16>
DDR_B_PAR<7,16>

DDR_B_ALERT#<7,16>

DDR_DRAMRST#_R<14,15,16, 20>

PCH_SMBDA TA_R<14,15,16,20 ,40>
PCH_SMBCL K_R<14,15,16,2 0,40>

DIMM4_CHB_ EVENT#

12

DDR_B_CLK 2
DDR_B_CLK #2
DDR_B_CLK 3
DDR_B_CLK #3

DDR_B_CKE 2
DDR_B_CKE 3

DDR_B_CS# 2
DDR_B_CS# 3

DDR_B_ODT2
DDR_B_ODT3

DDR_B_BG0
DDR_B_BG1
DDR_B_BA0
DDR_B_BA1

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA1 0
DDR_B_MA1 1
DDR_B_MA1 2
DDR_B_MA1 3
DDR_B_W E#
DDR_B_CAS #
DDR_B_RAS #

DDR_B_ACT#

DDR_B_PAR
DDR_B_ALERT#

DDR_DRAMRST#_R

PCH_SMBDA TA_R
PCH_SMBCL K_R

SA2_CHB_ DIM4
SA1_CHB_ DIM4
SA0_CHB_ DIM4

For ECC DIMM

.1U_0402_16V7K

2

CD120

1

XEMC@

JDIMM4A

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_W E#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

SP07001DO00

LCN_DAN05 -Q0926-0102

STD

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQS0(T)

DQS0#(C)

DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQS1(T)

DQS1#(C)

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQS2(T)

DQS2#(C)

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS3(T)

DQS3#(C)

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS4(T)

DQS4#(C)

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQS5(T)

DQS5#(C)

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQS6(T)

DQS6#(C)

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS7(T)

DQS7#(C)

conn need link

DDR_B_D0

8

DDR_B_D1

7

DDR_B_D7

20

DDR_B_D3

21

DDR_B_D5

4

DDR_B_D4

3

DDR_B_D2

16

DDR_B_D6

17

DDR_B_DQS 0

13

DDR_B_DQS #0

11

DDR_B_D9

28

DDR_B_D14

29

DDR_B_D13

41

DDR_B_D15

42

DDR_B_D8

24

DDR_B_D10

25

DDR_B_D11

38

DDR_B_D12

37

DDR_B_DQS 1

34

DDR_B_DQS #1

32

DDR_B_D17

50

DDR_B_D18

49

DDR_B_D19

62

DDR_B_D21

63

DDR_B_D16

46

DDR_B_D22

45

DDR_B_D23

58

DDR_B_D20

59

DDR_B_DQS 2

55

DDR_B_DQS #2

53

DDR_B_D25

70

DDR_B_D30

71

DDR_B_D29

83

DDR_B_D24

84

DDR_B_D28

66

DDR_B_D27

67

DDR_B_D31

79

DDR_B_D26

80

DDR_B_DQS 3

76

DDR_B_DQS #3

74

DDR_B_D39

174

DDR_B_D35

173

DDR_B_D36

187

DDR_B_D32

186

DDR_B_D38

170

DDR_B_D34

169

DDR_B_D37

183

DDR_B_D33

182

DDR_B_DQS 4

179

DDR_B_DQS #4

177

DDR_B_D41

195

DDR_B_D45

194

DDR_B_D46

207

DDR_B_D43

208

DDR_B_D40

191

DDR_B_D44

190

DDR_B_D42

203

DDR_B_D47

204

DDR_B_DQS 5

200

DDR_B_DQS #5

198

DDR_B_D51

216

DDR_B_D52

215

DDR_B_D55

228

DDR_B_D53

229

DDR_B_D48

211

DDR_B_D54

212

DDR_B_D49

224

DDR_B_D50

225

DDR_B_DQS 6

221

DDR_B_DQS #6

219

DDR_B_D56

237

DDR_B_D57

236

DDR_B_D60

249

DDR_B_D63

250

DDR_B_D61

232

DDR_B_D59

233

DDR_B_D58

245

DDR_B_D62

246

DDR_B_DQS 7

242

DDR_B_DQS #7

240

DDR_B_DQS 0 <7,16>

DDR_B_DQS #0 <7,16>

DDR_B_DQS 1 <7,16>

DDR_B_DQS #1 <7,16>

DDR_B_DQS 2 <7,16>

DDR_B_DQS #2 <7,16>

DDR_B_DQS 3 <7,16>

DDR_B_DQS #3 <7,16>

DDR_B_DQS 4 <7,16>

DDR_B_DQS #4 <7,16>

DDR_B_DQS 5 <7,16>

DDR_B_DQS #5 <7,16>

DDR_B_DQS 6 <7,16>

DDR_B_DQS #6 <7,16>

DDR_B_DQS 7 <7,16>

DDR_B_DQS #7 <7,16>

10uF*6

+1.2V_VDDQ +1.2V_VDDQ

10U_0603_6.3V6M

1

2

A A

10U_0603_6.3V6M

10U_0603_6.3V6M

CD103

CD104

1

1

2

2

5

1uF*8

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD105

CD106

1

1

2

2

@

CD107

CD109

CD108

1

1

1

2

2

2

1U_0402_6.3V6K

@

CD110

1

2

1U_0402_6.3V6K

1

1

CD111

CD112

2

2

1

1

CD113

2

4

1

CD115

CD114

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD118

CD116

CD117

2

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

3

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P15-DDRIV_CHB: DIMM1

P15-DDRIV_CHB: DIMM1

P15-DDRIV_CHB: DIMM1

Document Number Re v

Document Number Re v

Document Number Re v

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

17 103Monday, January 09, 2017

17 103Monday, January 09, 2017

17 103Monday, January 09, 2017

1.0

1.0

1.0

A

UH1

QJGE@

S IC GLSSKU QJGE D1 FCBGA 837P PCH-H

SA00008RM70

IO Board (left side)

UH1

1 1

QLF5@

S IC GL82CM238 QLF5 D1 BGA 837P PCH-H

SA0000ACM10

SR30U@

UH1

S IC GL82CM238 SR30U D1 BGA PCH-H ABO !

SA0000ACM30

back

3D CAM

U3 Board (right side)

front

U3 Board (right side)
back

USB3_PTX_DRX_N2<32>
USB3_PTX_DRX_P2<32>
USB3_PRX_DTX_N2<32>
USB3_PRX_DTX_P2<32>

USB3_PTX_DRX_N6<34>
USB3_PTX_DRX_P6<34>
USB3_PRX_DTX_N6<34>
USB3_PRX_DTX_P6<34>
USB3_PTX_DRX_N5<32>
USB3_PTX_DRX_P5<32>
USB3_PRX_DTX_N5<32>
USB3_PRX_DTX_P5<32>

USB3_PTX_DRX_P4<32>
USB3_PTX_DRX_N4<32>
USB3_PRX_DTX_P4<32>
USB3_PRX_DTX_N4<32>

CHECK ACER DVR for port use

front panel sp ec 5"
int cable 16"

DMI_CTX_PRX_N0<8>
DMI_CTX_PRX_P0<8>

2 2

#546884 P.231 PCIE_RCOMPN/PCIE_RCOMPP
BO=4 W=12~15 S=12 R=100ohm

PCIE_PRX_DTX_N1<32>

CARD READER

WIGI G

WLAN

LAN

3 3

Thunderbol t

PCIE_PRX_DTX_P1<32>

PCIE_PTX_C_DRX_N1<32>

PCIE_PTX_C_DRX_P1<32>
PCIE_PTX_C_DRX_N2<31>
PCIE_PTX_C_DRX_P2<31>

PCIE_PRX_DTX_N2<31>

PCIE_PRX_DTX_P2<31>

PCIE_PRX_DTX_N3<31>

PCIE_PRX_DTX_P3<31>

PCIE_PTX_C_DRX_N3<31>
PCIE_PTX_C_DRX_P3<31>

PCIE_PRX_DTX_N4<30>

PCIE_PRX_DTX_P4<30>

PCIE_PTX_C_DRX_N4<30>
PCIE_PTX_C_DRX_P4<30>

PCIE_PRX_DTX_N5<68>

PCIE_PRX_DTX_P5<68>

PCIE_PTX_C_DRX_N5<68>
PCIE_PTX_C_DRX_P5<68>

PCIE_PRX_DTX_N6<68>

PCIE_PRX_DTX_P6<68>

PCIE_PTX_C_DRX_N6<68>
PCIE_PTX_C_DRX_P6<68>

PCIE_PRX_DTX_N7<68>

PCIE_PRX_DTX_P7<68>

PCIE_PTX_C_DRX_N7<68>
PCIE_PTX_C_DRX_P7<68>

PCIE_PRX_DTX_N8<68>

PCIE_PRX_DTX_P8<68>

PCIE_PTX_C_DRX_N8<68>
PCIE_PTX_C_DRX_P8<68>

DMI_CRX_PTX_N0<8>

DMI_CRX_PTX_P0<8>
DMI_CTX_PRX_N1<8>
DMI_CTX_PRX_P1<8>

DMI_CRX_PTX_N1<8>

DMI_CRX_PTX_P1<8>
DMI_CTX_PRX_N2<8>
DMI_CTX_PRX_P2<8>

DMI_CRX_PTX_N2<8>

DMI_CRX_PTX_P2<8>
DMI_CTX_PRX_N3<8>
DMI_CTX_PRX_P3<8>

DMI_CRX_PTX_N3<8>

DMI_CRX_PTX_P3<8>

1 2

RH5 100_0402_1%

12

CH58 .1U_0402_16V7K

12

CH55 .1U_0402_16V7K

12

CH56 .1U_0402_16V7K

12

CH57 .1U_0402_16V7K

12

CH3 .1U_0402_16V7K

12

CH4 .1U_0402_16V7K

12

CH1 .1U_0402_16V7K

12

CH2 .1U_0402_16V7K

12

CH62 0.22U_0402_16V7KTBT@

12

CH59 0.22U_0402_16V7KTBT@

12

CH61 0.22U_0402_16V7KTBT@

12

CH60 0.22U_0402_16V7KTBT@

12

CH65 0.22U_0402_16V7KTBT@

12

CH64 0.22U_0402_16V7KTBT@

12

CH66 0.22U_0402_16V7KTBT@

12

CH63 0.22U_0402_16V7KTBT@

B

DMI_CTX_PRX_N0
DMI_CTX_PRX_P0
DMI_CRX_PTX_N0
DMI_CRX_PTX_P0
DMI_CTX_PRX_N1
DMI_CTX_PRX_P1
DMI_CRX_PTX_N1
DMI_CRX_PTX_P1
DMI_CTX_PRX_N2
DMI_CTX_PRX_P2
DMI_CRX_PTX_N2
DMI_CRX_PTX_P2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
DMI_CRX_PTX_N3
DMI_CRX_PTX_P3

PCIE_RCOMPN
PCIE_RCOMPP

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4
PCIE_PRX_DTX_N5
PCIE_PRX_DTX_P5
PCIE_PTX_DRX_N5
PCIE_PTX_DRX_P5
PCIE_PRX_DTX_N6
PCIE_PRX_DTX_P6
PCIE_PTX_DRX_N6
PCIE_PTX_DRX_P6
PCIE_PRX_DTX_N7
PCIE_PRX_DTX_P7
PCIE_PTX_DRX_N7
PCIE_PTX_DRX_P7
PCIE_PRX_DTX_N8
PCIE_PRX_DTX_P8
PCIE_PTX_DRX_N8
PCIE_PTX_DRX_P8

UH1F

C11

USB3_1_TXN

B11

USB3_1_TXP

B7

USB3_1_RXN

A7

USB3_1_RXP

B12

USB3_2_TXN/SSIC_1_TXN

A12

USB3_2_TXP/SSIC_1_TXP

C8

USB3_2_RXN/SSIC_1_RXN

B8

USB3_2_RXP/SSIC_1_RXP

B15

USB3_6_TXN

C15

USB3_6_TXP

K15

USB3_6_RXN

K13

USB3_6_RXP

B14

USB3_5_TXN

C14

USB3_5_TXP

G13

USB3_5_RXN

H13

USB3_5_RXP

D13

USB3_3_TXP/SSIC_2_TXP

C13

USB3_3_TXN/SSIC_2_TXN

A9

USB3_3_RXP/SSIC_2_RXP

B10

USB3_3_RXN/SSIC_2_RXN

B13

USB3_4_TXP

A14

USB3_4_TXN

G11

USB3_4_RXP

E11

USB3_4_RXN

S

KL-H-PCH_BGA837

@

UH1B

L27

DMI_RXN0

N27

DMI_RXP0

C27

DMI_TXN0

B27

DMI_TXP0

E24

DMI_RXN1

G24

DMI_RXP1

B28

DMI_TXN1

A28

DMI_TXP1

G27

DMI_RXN2

E26

DMI_RXP2

B29

DMI_TXN2

C29

DMI_TXP2

L29

DMI_RXN3

K29

DMI_RXP3

B30

DMI_TXN3

A30

DMI_TXP3

B18

PCIE_RCOMPN

C17

PCIE_RCOMPP

H15

PCIE1_RXN/USB3_7_RXN

G15

PCIE1_RXP/USB3_7_RXP

A16

PCIE1_TXN/USB3_7_TXN

B16

PCIE1_TXP/USB3_7_TXP

B19

PCIE2_TXN/USB3_8_TXN

C19

PCIE2_TXP/USB3_8_TXP

E17

PCIE2_RXN/USB3_8_RXN

G17

PCIE2_RXP/USB3_8_RXP

L17

PCIE3_RXN/USB3_9_RXN

K17

PCIE3_RXP/USB3_9_RXP

B20

PCIE3_TXN/USB3_9_TXN

C20

PCIE3_TXP/USB3_9_TXP

E20

PCIE4_RXN/USB3_10_RXN

G19

PCIE4_RXP/USB3_10_RXP

B21

PCIE4_TXN/USB3_10_TXN

A21

PCIE4_TXP/USB3_10_TXP

K19

PCIE5_RXN

L19

PCIE5_RXP

D22

PCIE5_TXN

C22

PCIE5_TXP

G22

PCIE6_RXN

E22

PCIE6_RXP

B22

PCIE6_TXN

A23

PCIE6_TXP

L22

PCIE7_RXN

K22

PCIE7_RXP

C23

PCIE7_TXN

B23

PCIE7_TXP

K24

PCIE8_RXN

L24

PCIE8_RXP

C24

PCIE8_TXN

B24

PCIE8_TXP

S

KL-H-PCH_BGA837

@

REV = 1.3

REV = 1.3

SPT-H_PCH

USB

LPC/eSPI

SATA

SPT-H_PCH

DMI

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

6 OF 12

USB 2.0

PCIe/USB 3

GPP_F15/USB2_OCB_4
GPP_F16/USB2_OCB_5
GPP_F17/USB2_OCB_6
GPP_F18/USB2_OCB_7

2 OF 12

GPP_G19/SMI#
GPP_G18/NMI#

GPP_E6/DEVSLP2
GPP_E5/DEVSLP1
GPP_E4/DEVSLP0

GPP_F9/DEVSLP7
GPP_F8/DEVSLP6
GPP_F7/DEVSLP5
GPP_F6/DEVSLP4
GPP_F5/DEVSLP3

USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9

USB2P_9
USB2N_10
USB2P_10
USB2N_11
USB2P_11
USB2N_12
USB2P_12
USB2N_13
USB2P_13
USB2N_14
USB2P_14

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

USB2_COMP

USB2_VBUSSENSE

RSVD_AB13

USB2_ID

GPD7/RSVD

C

LPC_AD0

?

?

AT22

LPC_AD1

AV22

LPC_AD2

AT19

LPC_AD3

BD16

LPC_FRAME#

BE16
BA17

SERIRQ
LPC_PIRQA#

AW17
AT17
BC18

LPC_CLK

BC17

CK_LPC_TPM_R

AV19
M45

N43

AE45
AG43
AG42
AB39
AB36
AB43
AB42
AB41

AF5
AG7

USB20_N2

AD5

USB20_P2

AD7
AG8
AG10

USB20_N4

AE1

USB20_P4

AE2

USB20_N5

AC2

USB20_P5

AC3

USB20_N6

AF2

USB20_P6

AF3

USB20_N7

AB3

USB20_P7

AB2

USB20_N8

AL8

USB20_P8

AL7

USB20_N9

AA1

USB20_P9

AA2

USB20_N10

AJ8

USB20_P10

AJ7

USB20_N11

W2

USB20_P11

W3

USB20_N12

AD3

USB20_P12

AD2
V2
V1
AJ11
AJ13

USB_OC0#

AD43

USB_OC1#

AD42

USB_OC2#

AD39

USB_OC3#

AC44

USB_OC4#

Y43

USB_OC5#

Y41

USB_OC6#

W44

USB_OC7#

W43

USB2_COMP

AG3

USB2_VBUSSENSE

AD10
AB13

USB2_ID

AG2

USB2_COMP

BD14

SE= 50 ohm
Spacing = 15 mils
Max lenght = 1000 mils

LPC_AD0 <38,40>
LPC_AD1 <38,40>
LPC_AD2 <38,40>
LPC_AD3 <38,40>

LPC_FRAME# <38,40>
SERIRQ <38,40>

ESPI_RST# <38>

RH2 22_0402_5%
RH4 22_0402_5%TPM@

12
12

DEVSLP2 <29>
DEVSLP0 <28>

DEVSLP1 <28>
DEVSLP3 <29>

USB20_N2 <32>
USB20_P2 <32>

USB20_N4 <32>
USB20_P4 <32>
USB20_N5 <32>
USB20_P5 <32>
USB20_N6 <33>
USB20_P6 <33>
USB20_N7 <31>
USB20_P7 <31>
USB20_N8 <65>
USB20_P8 <65>
USB20_N9 <65>
USB20_P9 <65>
USB20_N10 <33>
USB20_P10 <33>
USB20_N11 <34>
USB20_P11 <34>
USB20_N12 <33>
USB20_P12 <33>

RH6 113_0402_1%

To JSSD3
To JSSD1

SW confirmed 0422
To JSSD2

To JSSD4

1 2
1 2

@

RH149 0_0402_5%

1 2

@

RH150 0_0402_5%

LPC Bus

LPC : +3.3V

To TPM
del EC_KBRST#_R

no coding

USB3 LEFT

USB3 RIGHT

USB3 RIGHT

TP

BT

TS (Reseve)

FHD CAM

Int. KB

EYE TRACKER

Int. KB BL

D

LPC_CLK_R <38>
CK_LPC_TPM <40>

To EC

SERIRQ

DG requierment 8.2k PH +3VS
CRB 10K PH +3vs

LPC_PIRQA#

ESPI / LPC Bus
ESPI : +1.8V
LPC : +3.3V

1 2

RH1 10K_0402_5%

RH122 10K_0402_5%

reference PDG1.0 50-30

USB_OC0#
USB_OC1#
USB_OC3#
USB_OC2#

USB_OC5#
USB_OC4#
USB_OC6#
USB_OC7#

RPH1

10K_0804_8P4R_5%

RPH15

10K_0804_8P4R_5%

@

12

18
27
36
45

18
27
36
45

E

+3VS

+3VS

+3VALW_PCH_PRIM

+3VALW_PCH_PRIM

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(1/7)DMI,PCIE,USB

PCH(1/7)DMI,PCIE,USB

PCH(1/7)DMI,PCIE,USB

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

E

18 103Monday, January 09, 2017

18 103Monday, January 09, 2017

18 103Monday, January 09, 2017

1.0

1.0

1.0

A

PCH PLTRST Buf f er

on-board devic e driving it to opposite direct i on duri ng

B

C

D

E

RPH3 and close UH6

RPH3

PCH_SPI_SOPCH_SPI_SO_0_R

1 8

PCH_SPI_SIPCH_SPI_SI_0_R

2 7

PCH_SPI_CLKPCH_SPI_CLK_0_R

3 6

PCH_SPI_IO3PCH_SPI_IO3_0_R

To SPI ROM

UH1A

@

PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_CS#0
PCH_SPI_CLK

PCH_SPI_IO2
PCH_SPI_IO3

1

IN1

2

IN2

12

GPP_F13

DGPU_PRSNT#

0
1

+3VS

A

EC_PME#_R

BD17
AG15

AG14
AF17
AE17

AR19
AN17

BB29
BE30
BD31
BC31

AW31

BC29
BD30
AT31

AN36
AL39
AN41
AN38
AH43
AG44

1 2

@

RH19 0_0402_5%

CH5

.1U_0402_16V7K

1 2

5

UH5

P

PLT_RST_BUF#

4

O

G

3

RH34
10K_0402_5%

GPP_A11/PME#
RSVD

RSVD
RSVD
RSVD

TP2
TP1

SPI0_MOSI
SPI0_MISO
SPI0_CS0#
SPI0_CLK
SPI0_CS1#
SPI0_IO2
SPI0_IO3
SPI0_CS2#

GPP_D1/SPI1_CLK
GPP_D0/SPI1_CS#
GPP_D3/SPI1_MOSI
GPP_D2/SPI1_MISO
GPP_D22/SPI1_IO3
GPP_D21/SPI1_IO2

S

KL-H-PCH_BGA837

@

12

1 1

EC_PME#<30,38>

1 2

RH115 0_0402_5%

SPI ROM
0127 Jason

TBT_CIO_PLUG_EVENT #<68>

RTD3_CIO_PWR_EN<68>

RTD3_USB_PW R_EN<68>

TBT_FORCE_PW R<68>

TBT_BATLOW#<68>

AR GPIO , confirm SW 0422

2 2

PLT_RST#

MC74VHC1G08DFT2G_SC70-5

3 3

DGPU_PRSNT#

DIS
UMA

4 4

SPT-H_PCH

PLT_RST_BUF# <28,29,30,31,32,41,53,68>

RH24
100K_0402_5%

SSD Slot_1
PCIe/SATA

SSD Slot_3
SATA

SSD Slot_1
PCIe/SATA

SSD Slot_2
PCIe/SATA

GPP_B13/PLTRST#

GPP_G16/GSXCLK

GPP_G12/GSXDOUT

GPP_G13/GSXSLOAD

GPP_G14/GSXDIN

GPP_G15/GSXSRESET#

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

GPP_H18/SML4ALERT#

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H15/SML3ALERT#

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H12/SML2ALERT#

GPP_H11/SML2DATA

GPP_H10/SML2CLK

1 OF 12

REV = 1.3

PCIE_PTX_DRX_P11<28>
PCIE_PTX_DRX_N11<28>

PCIE_PRX_DTX_P11<28>
PCIE_PRX_DTX_N11<28>

SATA_PTX_DRX_N1B<29>
SATA_PTX_DRX_P1B<29>
SATA_PRX_DTX_N1B<29>
SATA_PRX_DTX_P1B< 29>

PCIE_PTX_DRX_P12<28>
PCIE_PTX_DRX_N12<28>

PCIE_PRX_DTX_P12<28>

PCIE_PRX_DTX_N12<28>
PCIE_PTX_DRX_P20<28>
PCIE_PTX_DRX_N20<28>

PCIE_PRX_DTX_P20<28>

PCIE_PRX_DTX_N20<28>
PCIE_PTX_DRX_P19<28>
PCIE_PTX_DRX_N19<28>

PCIE_PRX_DTX_P19<28>

PCIE_PRX_DTX_N19<28>

INTRUDER#

?

BB27
P43

R39
R36
R42
R41

AF41
AE44
BC23
BD24

BC36
BE34
BD39
BB36
BA35
BC35
BD35
AW35
BD34

BE11

B

SM_INTRUDER#

PLT_RST#

Del I2C_TS_INT#
Del I2C_TP_INT#

for server and WS use

PAD

RH13 1M_0402_5%

PCIE_PTX_DRX_P11

PCIE_PTX_DRX_N11

PCIE_PRX_DTX_P11

PCIE_PRX_DTX_N11

DGPU_PRSNT#

PCIE_PTX_DRX_P12

PCIE_PTX_DRX_N12

PCIE_PRX_DTX_P12

PCIE_PRX_DTX_N12

PCIE_PTX_DRX_P20
PCIE_PTX_DRX_N20
PCIE_PRX_DTX_P20

PCIE_PRX_DTX_N20

PCIE_PTX_DRX_P19

PCIE_PTX_DRX_N19

PCIE_PRX_DTX_P19

PCIE_PRX_DTX_N19

PLT_RST# <38,40>

T23

@

1 2

AV2
AV3

AW2

R44
R43
U39
N42

U43
U42
U41

M44

U36
P44
T45
T44

B33
C33
K31

L31

AB33
AB35
AA44
AA45

B38
C38
D39
E37

C36
B36
G35
E35

A35
B35
H33
G33

J45
K44
N38
N39
H44
H43

L39

L37

+RTCVCC

UH1C

CL_CLK
CL_DATA
CL_RST#

GPP_G8/FAN_PWM_0
GPP_G9/FAN_PWM_1
GPP_G10/FAN_PWM_2
GPP_G11/FAN_PWM_3

GPP_G0/FAN_TACH_0
GPP_G1/FAN_TACH_1
GPP_G2/FAN_TACH_2
GPP_G3/FAN_TACH_3
GPP_G4/FAN_TACH_4
GPP_G5/FAN_TACH_5
GPP_G6/FAN_TACH_6
GPP_G7/FAN_TACH_7

PCIE11_TXP
PCIE11_TXN
PCIE11_RXP
PCIE11_RXN

GPP_F10/SCLOCK
GPP_F11/SLOAD
GPP_F13/SDATAOUT0
GPP_F12/SDATAOUT1

PCIE14_TXN/SATA1B_TXN
PCIE14_TXP/SATA1B_TXP
PCIE14_RXN/SATA1B_RXN
PCIE14_RXP/SATA1B_RXP

PCIE13_TXN/SATA0B_TXN
PCIE13_TXP/SATA0B_TXP
PCIE13_RXN/SATA0B_RXN
PCIE13_RXP/SATA0B_RXP

PCIE12_TXP
PCIE12_TXN
PCIE12_RXP
PCIE12_RXN
PCIE20_TXP/SATA7_TXP
PCIE20_TXN/SATA7_TXN
PCIE20_RXP/SATA7_RXP
PCIE20_RXN/SATA7_RXN
PCIE19_TXP/SATA6_TXP
PCIE19_TXN/SATA6_TXN
PCIE19_RXP/SATA6_RXP
PCIE19_RXN/SATA6_RXN

S

KL-H-PCH_BGA837

@

REV = 1.3

SPI ROM ( 16MByte )

PCH_SPI_CS#0

PCH_SPI_IO2_0_R

RH21,RH22 place to within 1100 mil of SPIO_MOSI/SPI0_IO2 pin for XDP

XDP_SPI_SI<6>
XDP_SPI_IO2<6>

SPT-H_PCH

CLINK

FAN

3 OF 12

C

PCH_SPI_CLK_0_R

PCIe/SATA

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_F0/SATAXPCIE3/SATAGP3
GPP_F1/SATAXPCIE4/SATAGP4
GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6
GPP_F4/SATAXPCIE7/SATAGP7

HOST

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4 5

15_0804_8P4R_5%

1 2

RH30 15_0402_5%

UH6

1

/CS

2

DO(IO1)

/HOLD(IO3)

3

/WP(IO2)

4

GND

W25Q128FVSIQ_SO8

PCIE9_RXN/SATA0A_RXN
PCIE9_RXP/SATA0A_RXP

PCIE9_TXN/SATA0A_TXN
PCIE9_TXP/SATA0A_TXP

PCIE10_RXN/SATA1A_RXN
PCIE10_RXP/SATA1A_RXP

PCIE10_TXN/SATA1A_TXN
PCIE10_TXP/SATA1A_TXP

PCIE15_RXN/SATA2_RXN
PCIE15_RXP/SATA2_RXP
PCIE15_TXN/SATA2_TXN
PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN
PCIE16_RXP/SATA3_RXP
PCIE16_TXN/SATA3_TXN
PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN
PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_TXN
PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN
PCIE18_RXP/SATA5_RXP
PCIE18_TXN/SATA5_TXN
PCIE18_TXP/SATA5_TXP

GPP_F21/EDP_BKLTCTL

DI(IO0)

XEMC@

1 2

RH35
0_0402_5%

1 2

RH21 1K_0402_1%CMC@

1 2

RH22 1K_0402_1%CMC@

GPP_E8/SATALED#

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THERMTRIP#

PECI

PM_SYNC

PLTRST_PROC#

PM_DOWN

PCH_SPI_IO2PCH_SPI_IO2_0_R

+3VALW_SPI

8

VCC

7
6

CLK

5

G31
H31
C31
B31

G29
E29
C32
B32

F41
E41
B39
A39

D43
E42
A41
A40

H42
H40
E45
F45

K37
G37
G45
G44

AD44
AG36
AG35
AG39
AD35
AD31
AD38
AC43
AB44

W36
W35
W42

AJ3
AL3
AJ4
AK2
AH2

?

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

1 2

PCH_SPI_IO3_0_RPCH_SPI_SO_0_R
PCH_SPI_CLK_0_R
PCH_SPI_SI_0_R

XEMC@

1 2

CH7
10P_0402_50V8J

PCIE_PRX_DTX_N9
PCIE_PRX_DTX_P9
PCIE_PTX_DRX_N9
PCIE_PTX_DRX_P9

PCIE_PRX_DTX_N10
PCIE_PRX_DTX_P10
PCIE_PTX_DRX_N10
PCIE_PTX_DRX_P10

PCIE_PRX_DTX_N17

PCIE_PRX_DTX_P17

PCIE_PTX_DRX_N17

PCIE_PTX_DRX_P17

PCIE_PRX_DTX_N18

PCIE_PRX_DTX_P18

PCIE_PTX_DRX_N18

PCIE_PTX_DRX_P18

SATA_LED#
SATA_GP0
SATA_GP2

SATA_GP3
SATA_GP1

PCH_BKL_PW M
ENBKL

PCH_ENVDD

PCH_THERMTRIP#
PCH_PECI
H_PM_SYNC_R
PLTRST_CPU#

CH6
.1U_0402_16V7K

PCH_SPI_SI
PCH_SPI_IO2

RH25 100K_0402_5%@
RH26 100K_0402_5%@
RH159 100K_0402_5%@

1 2

RH23 620_0402_5%

1 2

RH121 12.1_0402_1%@
RH12 30_0402_1%

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Follow MOW 2015WW09

PCH_SPI_IO2

PCH_SPI_IO3

Follow MOW WW36
p

ull down with pre-ES1/ES1 samples

751 PU +3V

Functional Strap Definitions

SPI0_M OSI
int. PH
This strap should sample HIGH. There should NOT be any
on-board devic e driving it to opposite direct i on duri ng
strap sampling.

SPI0_M ISO
int. PH
This strap should sample HIGH. There should NOT be any

strap sampling.
SPI0_ IO2

int. PH
This strap should sample HIGH. There should NOT be any
on-board devic e driving it to opposite direct i on duri ng
strap sampling.

SPI0_ IO3
int. PH
This strap should sample HIGH. There should NOT be any
on-board devic e driving it to opposite direct i on duri ng
strap sampling.

GPP_H12
int. PD
This strap should sample LOW.

PCIE_PRX_DTX_N9 <28>
PCIE_PRX_DTX_P9 <28>
PCIE_PTX_DRX_N9 <28>
PCIE_PTX_DRX_P9 <28>

PCIE_PRX_DTX_N10 <28>
PCIE_PRX_DTX_P10 <28>
PCIE_PTX_DRX_N10 <28>
PCIE_PTX_DRX_P10 <28>

SATA_PRX_DTX_N2 <27>
SATA_PRX_DTX_P2 <27>
SATA_PTX_DRX_N2 <27>

SATA_PTX_DRX_P2 <27>

SATA_PRX_DTX_N3 <29>
SATA_PRX_DTX_P3 <29>
SATA_PTX_DRX_N3 <29>

SATA_PTX_DRX_P3 <29>

PCIE_PRX_DTX_N17 <28>
PCIE_PRX_DTX_P17 <28>
PCIE_PTX_DRX_N17 <28>
PCIE_PTX_DRX_P17 <28>

PCIE_PRX_DTX_N18 <28>
PCIE_PRX_DTX_P18 <28>
PCIE_PTX_DRX_N18 <28>
PCIE_PTX_DRX_P18 <28>

SATA_LED# <28>

SATA_GP0 <28>
SATA_GP2 <29>

SATA_GP3 <29>
SATA_GP1 <28>

1 2
1 2
1 2

12

PLTRST_CPU# <9>

PM_DOWN_R <9>

D

1 2

RH28 1K_0402_1%

1 2

RH29 1K_0402_1%@

1 2

RH32 1K_0402_1%

1 2

RH33 1K_0402_1%@

PCH_SPI_CS#0
PCH_SPI_IO2_0_R
PCH_SPI_IO3_0_R

SSD Slot_1
PCIe/SATA

HDD

SSD Slot_4
SATA

SSD Slot_2
PCIe/SATA

To JSSD1
To JSSD3

SW confirmed 0422

To JSSD4
To JSSD2

del PWM/ENVDD/ENBKL
check PL can del or not? 3/25

THERMTRIP# <9>
H_PECI <9,38>
H_PM_SYNC <9>

+3VALW_SPI

SCLK

SI/SIO0

SO/SIO1

VCC

+3VALW_SPI

8

PCH_SPI_CLK_0_R

6

PCH_SPI_SI_0_R

5

PCH_SPI_SO_0_R

2

SATA_LED#

RH160 10K_0402_5%

SATA_GP0
SATA_GP2
SATA_GP3
SATA_GP1

10K_0804_8P4R_5%

RPH14

+3VS

12

18
27
36
45

@

JROM1

1

CS#

3

WP#

7

HOLD#

4

GND

ACES_91960-0084N_MX25L3206EM2I

CONN@

CONN TO EC & CPU

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(2/7)SPI,SATA,XDP

PCH(2/7)SPI,SATA,XDP

PCH(2/7)SPI,SATA,XDP

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

E

1.0

1.0

19 103Monday, January 09, 2017

19 103Monday, January 09, 2017

19 103Monday, January 09, 2017

1.0

A

B

C

D

E

HDA for AUDIO

<38> ME_EN

<36> HDA_SDOUT_R
<36> HDA_BIT_CLK_R
<36> HDA_RST #_R
<36> HDA_SYNC_R

1 1

+3VALW_DSW

2 2

3 3

Functional Strap Definitions

SMBALERT# / GPP_C2
int. PD
0 = Disable Intel ME (TLS) (Default)
1 = Enable Intel ME (TLS)

SML0ALERT# / GPP_C5
int. PD
0 = LPC Is selected for EC. (Default)
1 = eSPI Is selected for EC.

SML1ALERT# / PCHHOT# / GPP_B23
int. PD

SPKR / GPP_B14
int. PD
0 = Disable “ Top S wap” mode. ( Def ault )
1 = Enable “ Top Swap” mode.

HDA_SDO
int. PD
0 = Enable security measures defined in the Flash

4 4

Descriptor. (Default)
1 = Disable Flash Descriptor Security (override).

DDPB_CTRLDATA / GPP_I6
int. PD
0 = Port B is not detected.
1 = Port B is detected. (Default)

<36> HDA_SDIN0

+3VALW_PCH_PRIM

RPH6

10K_0804_8P4R_5%

Follow 543016_SKL_U_Y_PDG_0_9

+3VALW_DSW

EC_RSMRST#

+RTCVCC

CRB 8.2K

1 2

RH40 10K_0402_5%

1 2

@

RH41 10K_0402_5%

1 2

RH42 1K_0402_5%

12

@

RH44 0_0402_5%

12

@

RH45 0_0402_5%

1

1 2

CH8 1U_0402_6.3V6K

1

1 2

CH9 1U_0402_6.3V6K

1
1

Place at RAM DOOR
(DVT 7./11)

SYS_RESET#

18

LAN_WAKE#

27

EC_RSMRST#

36

PCH_PWROK

45

PCH_DPWROK

PCH_PWROKSYS_PWROK

2

20K_0402_5%RH46

2

20K_0402_5%RH49

2

0_0603_5%@JCMOS1

2

0_0603_5%@JCMOS2

A

1 2

@

RH36 0_0402_5%

RPH5

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

HDA_SDIN0

PM_BATLOW#
AC_PRESENT_R

WAKE#

PCH_SRTCRST#

Remove CLR ME

PCH_RTCRST #

CLR CMOS

HDA_SDOUT
HDA_BIT_CLK
HDA_RST#
HDA_SYNC

<6> CPU_DISPA_SDO_R

<6> CPU_DISPA_SDI_R

<6> CPU_DISPA_BCLK_R

<26,38> PCH_PWROK

<6,38> EC_RSMRST#

(SO-DIMM,G-sensor)

(AUDIO,EC,VGA,)

+3VALW_PCH_PRIM

+3VALW_PCH_PRIM

DDPC_CTRLDATA / GPP_I8
int. PD
0 = Port C is not detected.
1 = Port C is detected. (Default)

DDPD_CTRLDATA / GPP_I10
int. PD
0 = Port D is not detected. (Default)
1 = Port D is detected.

1 2

@

RH142 4.7K_0402_5%

1 2

RH50 499_0402_1%

1 2

RH51 499_0402_1%

T66

@PAD

route from VGA?

1 2

RH116

30_0402_1%

1 2

RH117

30_0402_1%

PCH_SMBALERT#

CRB

PCH_SML0CLK
PCH_SML0DATA

B

PCH_EDP_HPD

HDA_BIT_CLK
HDA_RST#
HDA_SDIN0

HDA_SDOUT
HDA_SYNC

CPU_DISPA_SDO
CPU_DISPA_SDI_R
CPU_DISPA_BCLK

PCH_RTCRST #
PCH_SRTCRST#

PCH_PWROK
EC_RSMRST#

PCH_DPWROK

PCH_SMBALERT#

PCH_SMBCLK
PCH_SMBDATA

PCH_SML0CLK
PCH_SML0DATA

PCH_SML1CLK
PCH_SML1DATA

UH1E

AW4

GPP_I0/DDPB_HPD0

AY2

GPP_I1/DDPC_HPD1

AV4

GPP_I2/DDPD_HPD2

BA4

GPP_I3/DDPE_HPD3

BD7

GPP_I4/EDP_HPD

SKL-H-PCH_BGA837

REV = 1.3

@

UH1D

BA9

HDA_BCLK

BD8

HDA_RST#

BE7

HDA_SDI0

BC8

HDA_SDI1

BB7

HDA_SDO

BD9

HDA_SYNC

BD1

RSVD_BD1

BE2

RSVD_BE2

AM1

DISPA_SDO

AN2

DISPA_SDI

AM2

DISPA_BCLK

AL42

GPP_D8/I2S0_SCLK

AN42

GPP_D7/I2S0_RXD

AM43

GPP_D6/I2S0_TXD

AJ33

GPP_D5/I2S0_SFRM

AH44

GPP_D20/DMIC_DATA0

AJ35

GPP_D19/DMIC_CLK0

AJ38

GPP_D18/DMIC_DATA1

AJ42

GPP_D17/DMIC_CLK1

BC10

RTCRST#

BB10

SRTCRST#

AW11

PCH_PWROK

BA11

RSMRST#

AV11

DSW_PWROK

BB41

GPP_C2/SMBALERT#

AW44

GPP_C0/SMBCLK

BB43

GPP_C1/SMBDATA

BA40

GPP_C5/SML0ALERT#

AY44

GPP_C3/SML0CLK

BB39

GPP_C4/SML0DATA

AT27

GPP_B23/SML1ALERT#/PCHHOT#

AW42

GPP_C6/SML1CLK

AW45

GPP_C7/SML1DATA

SKL-H-PCH_BGA837

REV = 1.3

@

+3VALW_PCH_PRIM

+3VS

+3VALW_PCH_PRIM

+3VS

SPT-H_PCH

AUDIO

2.2K_0804_8P4R_5%

2.2K_0804_8P4R_5%

PDG_0_71 requirement PH to +3V_PCH
10/14 Dan

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I9/DDPD_CTRLCLK

GPP_I10/DDPD_CTRLDATA

5 OF 12

SPT-H_PCH

SMBUS

RPH9

18
27
36
45

RPH8

18
27
36
45

GPP_F14
GPP_F23

GPP_F22
GPP_G23
GPP_G22
GPP_G21
GPP_G20
GPP_H23

GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_A13/SUSWARN#/SUSPWRDNACK

JTAG

4 OF 12

PCH_SMBCLK
PCH_SMBDATA
PCH_SMBCLK_R
PCH_SMBDATA_R

PCH_SML1CLK
PCH_SML1DATA
EC_SMB_CK2
EC_SMB_DA2

SSSeeecccuuurrriiitttyyy CCClllaaassssssiiifffiiicccaaatttiiiooonnn

IIIssssssuuueeeddd DDDaaattteee

TTT HHHIIISSS SSSHHHEEEEEETTT OOOFFF EEENNNGGGIIINNNEEEEEERRRIIINNNGGG DDDRRRAAAWWWIIINNNGGG IIISSS TTTHHHEEE PPPRRROOOPPPRRRIIIEEETTTAAARRRYYY PPPRRROOOPPPEEERRRTTTYYY OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCC SSS,,, IIINNNCCC... AAANNNDDD CCCOOONNNTTTAAAIIINNNSSS CCCOOONNNFFFIIIDDDEEENNNTTTIIIAAALLL
AAANNNDDD TTTRRRAAADDDEEE SSSEEECCCRRREEETTT IIINNNFFFOOORRRMMMAAATTTIIIOOONNN... TTTHHHIIISSS SSSHHHEEEEEETTT MMMAAAYYY NNNOOOTTT BBBEEE TTTRRRAAANNNSSSFFFEEERRREEEDDD FFFRRROOOMMM TTTHHHEEE CCCUUUSSSTTTOOODDDYYY OOOFFF TTTHHHEEE CCCOOOMMMPPPEEETTTEEENNNTTT DDDIIIVVVIIISSSIIIOOONNN OOOFFF RRR&&&DDD
DDDEEEPPPAAARRRTTTMMMEEENNNTTT EEEXXXCCCEEEPPPTTT AAASSS AAAUUUTTTHHHOOORRRIIIZZZEEEDDD BBBYYY CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... NNNEEEIIITTTHHHEEERRR TTTHHHIIISSS SSSHHHEEEEEETTT NNNOOORRR TTTHHHEEE IIINNNFFFOOORRRMMMAAATTTIIIOOONNN IIITTT CCCOOONNNTTTAAAIIINNNSSS
MMMAAAYYY BBBEEE UUUSSSEEEDDD BBBYYY OOORRR DDDIIISSSCCCLLLOOOSSSEEEDDD TTTOOO AAANNNYYY TTTHHHIIIRRRDDD PPPAAARRR TTTYYY WWWIIITTTHHHOOOUUUTTT PPPRRR IIIOOORRR WWWRRRIIITTTTTTEEENNN CCCOOONNNSSSEEENNNTTT OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCC SSS,,, IIINNNCCC...

C

?

BB3
BD6
BA5
BC4
BE5
BE6

Y44
V44
W39
L43
L44
U35
R35
BD36

GPP_A8/CLKRUN#
GPD11/LANPHYPC
GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_B1

GPP_G17/ADR_COMPLETE

GPP_B0

GPP_B11

SYS_PWROK

WAKE#

GPD6/SLP_A#

SLP_LAN#

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE#
GPD1/ACPRESENT

SLP_SUS#

GPD3/PWRBTN#

SYS_RESET#

GPP_B14/SPKR

PROCPWRGD

ITP_PMODE

JTAGX
JTAG_TMS
JTAG_TDO

JTAG_TDI

JTAG_TCK

<14,15,16,17,40> PCH_SMBCLK_R

<14,15,16,17,40> PCH_SMBDATA_R

<26,32,36,38,41,53> EC_SMB_CK2

<26,32,36,38,41,53> EC_SMB_DA2

222000111666///000222///000111 222000111777///111222///333111

H_SKTOCC# <9>

BB17

PM_CLKRUN#

AW22
AR15

SLP_WLAN#

AV13

DDR_DRAMRST#

BC14

PCH_VRALERT#

BD23
AL27
AR27
N44

GC6_FB_EN_S_R

AN24

SYS_PWROK

AY1
BC13

WAKE#

BC15
AV15

PM_SLP_S0#

BC26

PM_SLP_S3#

AW15

PM_SLP_S4#

BD15

PM_SLP_S5#

BA13
AN15

SUSCLK
PM_BATLOW#

BD13
BB19
BD19

LAN_WAKE#

BD11

AC_PRESENT_R

BB15

PM_SLP_SUS#

BB13

PBTN_OUT#_R

AT13

SYS_RESET#

AW1

PCH_SPKR

BD26

H_CPUPWRGD

AM3

XDP_ITP_PMODE

AT2

CPU_XDP_TCK0

AR3

CPU_XDP_TMS

AR2

CPU_XDP_TDO

AP1

CPU_XDP_TDI

AP2

PCH_JTAG_TCK1

AN3

?

1

1 2

@

RH52 0_0402_5%

(DIMM,G-SENEOR,)

EC_SMB_CK2

EC_SMB_DA2

(IO Brd /AUDIO/EC/VGA/VGA2)

CCCooommmpppaaalll SSSeeecrcrcreeettt DDDaaatttaaa

DeDeDecicicippphhheeererereddd DaDaDatetete

PM_CLKRUN# <40>

@ T32

PAD

GC6_FB_EN_S_R <22>

SYS_PWROK <26,38>

2

0_0402_5%@RH154

@ T70

PAD

PM_SLP_S3# <26,38>
PM_SLP_S4# <26,38,77>

@ T6

PAD

SUSCLK <28,29,31>

@ T34

PAD

PCH_SPKR <36>

H_CPUPWRGD <9>

XDP_ITP_PMODE <6>
CPU_XDP_TCK0 <6,9>
CPU_XDP_TMS <6,9>
CPU_XDP_TDO <6,9>
CPU_XDP_TDI <6,9>
PCH_JTAG_TCK1 <6>

PCH_SMBCLK_R

PCH_SMBDATA_R

D

TBT_PCIE_WAKE_N <68>

@ T12

PAD

SUSPWRDNACK <38>

+3VS

QH1A

2

DMN66D0LDW -7_SOT363-6

5

QH1B
DMN66D0LDW -7_SOT363-6

34

+3VS

QH2A

2

DMN66D0LDW -7_SOT363-6

5

QH2B
DMN66D0LDW -7_SOT363-6

34

DDR_DRAMRST#

61

61

+3VS

PM_CLKRUN#

PCH_VRALERT#

PBTN_OUT#_R

PBTN_OUT#_R

AC_PRESENT_R

SYS_PWROK

SYS_RESET#

PCH_SMBCLK

PCH_SMBDATA

PCH_SML1CLK

PCH_SML1DATA

RH39 10K_0402_5%

RH43 10K_0402_5%

RH128 100K_0402_5%

RH47 0_0402_5%

RH48 0_0402_5%

RH130 10K_0402_5%

CH10
.1U_0402_16V7K

XEMC@

+1.2V_VDDQ

12

RH153
470_0402_5%

1 2

RH161 0_0402_5%

1

@

.1U_0402_16V7K
CH67

2

Compal Electronics, Inc.Compal Electronics, Inc.Compal Electronics, Inc.

TTTiiitttlll eee

PCPCPCH(H(H(333///777)))GGGPIPIPIOOO,,,SSSMMMBBBUUUSSS

SSSiiizezeze DDDooocucucumememennnttt NNNuuumbmbmbeeerrr RRReee vvv

CCCuuussstttooommm

C1PR2 LA-E051PC1PR2 LA-E051PC1PR2 LA-E051P

DDDaaattteee::: SSShhheeeeeettt ooo fff

1 2

@

@

1 2

@

1 2

@

1 2

1 2

@

12

12

CRB 8.2K

+3VALW_PCH_PRIM

DDR_DRAMRST#_R <14,15,16,17>

E

+3VALW_DSW

PBTN_OUT# <38>

AC_PRESENT <38>

222000 111000333MMMooonnndddaaayyy,,, JJJaaannnuuuaaarrryyy 000999,,, 222000111777

111...000

A

+3VS

RPH11

CLKREQ_PCIE#1

18

CLKREQ_PCIE#3

27

CLKREQ_PCIE#5

36

CLKREQ_PCIE#4

1 1

Follow PDG 0.71Table 52-17
10/13 Dan
CHECK NEEDED IF UNUSE?

2 2

1 2

RH71 10M_0402_5%

1 2

32.768KHZ 9PF 20PPM

8.2P_0402_50V8D

1

CH13

2

3 3

45

10K_0804_8P4R_5%

RPH12

18
27
36
45

10K_0804_8P4R_5%

RPH13

18
27
36
45

10K_0804_8P4R_5%

YH1

CLKREQ_PCIE#7
CLKREQ_PCIE#2

PEG_CLKREQ#_S
CLKREQ_PCIE#6

PEG_CLKREQ#

RTCX1

RTCX2

6.8P_0402_50V8B

1

CH14

2

Check if need PH alone

XTAL24_OUT

1 2

RH72 1M_0402_5%

YH2
24MHZ_12PF_7V24000020

3

15P_0402_50V8J

3

GND

CH11

4

GND

1

1

2

XTAL24_IN

15P_0402_50V8J

CH12

B

+1.0VALW_VCCCLK5

PEG master

CR

WIGI G

WLAN

LAN

Thunderbol t
SSD Slot_1
SSD Slot_2
PEG secondary

FOLLOW RVP11

CPU_24M<9>
CPU_24M#<9>

CPU_BCLK<9>
CPU_BCLK#<9>

XTAL24_OUT
XTAL24_IN

PEG_CLKREQ#<41>
CLKREQ_PCIE#1<32>
CLKREQ_PCIE#2<31>
CLKREQ_PCIE#3<31>
CLKREQ_PCIE#4<30>
CLKREQ_PCIE#5<68>
CLKREQ_PCIE#6<28>
CLKREQ_PCIE#7<28>

PEG_CLKREQ#_S<53>

RH67

2.7K_0402_1%

12

C

XCLK_BIASREF

RTCX1
RTCX2

PEG_CLKREQ#
CLKREQ_PCIE#1
CLKREQ_PCIE#2
CLKREQ_PCIE#3
CLKREQ_PCIE#4
CLKREQ_PCIE#5
CLKREQ_PCIE#6
CLKREQ_PCIE#7
PEG_CLKREQ#_S

UH1G

AR17

GPP_A16/CLKOUT_48

G1

CLKOUT_CPUNSSC_P

F1

CLKOUT_CPUNSSC_N

G2

CLKOUT_CPUBCLK_P

H2

CLKOUT_CPUBCLK_N

A5

XTAL24_OUT

A6

XTAL24_IN

E1

XCLK_BIASREF

BC9

RTCX1

BD10

RTCX2

BC24

GPP_B5/SRCCLKREQ0#

AW24

GPP_B6/SRCCLKREQ1#

AT24

GPP_B7/SRCCLKREQ2#

BD25

GPP_B8/SRCCLKREQ3#

BB24

GPP_B9/SRCCLKREQ4#

BE25

GPP_B10/SRCCLKREQ5#

AT33

GPP_H0/SRCCLKREQ6#

AR31

GPP_H1/SRCCLKREQ7#

BD32

GPP_H2/SRCCLKREQ8#

BC32

GPP_H3/SRCCLKREQ9#

BB31

GPP_H4/SRCCLKREQ10#

BC33

GPP_H5/SRCCLKREQ11#

BA33

GPP_H6/SRCCLKREQ12#

AW33

GPP_H7/SRCCLKREQ13#

BB33

GPP_H8/SRCCLKREQ14#

BD33

GPP_H9/SRCCLKREQ15#

R13

CLKOUT_PCIE_N15

R11

CLKOUT_PCIE_P15

P1

CLKOUT_PCIE_N14

R2

CLKOUT_PCIE_P14

W7

CLKOUT_PCIE_N13

Y5

CLKOUT_PCIE_P13

U2

CLKOUT_PCIE_N12

U3

CLKOUT_PCIE_P12

S

KL-H-PCH_BGA837

@

REV = 1.3

SPT-H_PCH

CLKOUT_CPUPCIBCLK_N
CLKOUT_CPUPCIBCLK_P

7 OF 12

D

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5

CLKOUT_PCIE_N6
CLKOUT_PCIE_P6

CLKOUT_PCIE_N7
CLKOUT_PCIE_P7

CLKOUT_PCIE_N8
CLKOUT_PCIE_P8

CLKOUT_PCIE_N9
CLKOUT_PCIE_P9

CLKOUT_PCIE_N10

CLKOUT_PCIE_P10

CLKOUT_PCIE_N11

CLKOUT_PCIE_P11

?

L1
L2
J1
J2

N7
N8

L7
L5

D3
F2

E5
G4

D5
E6

D8
D7

R8
R7

U5
U7

W10
W11

N3
N2

P3
P2

R3
R4

CLK_CPU_ITP#
CLK_CPU_ITP
CPU_PCIBCLK#
CPU_PCIBCLK

CLK_PEG_GPU_N0

CLK_PEG_GPU_P0

CLK_PCIE_N1

CLK_PCIE_P1

CLK_PCIE_N2

CLK_PCIE_P2

CLK_PCIE_N3

CLK_PCIE_P3

CLK_PCIE_N4

CLK_PCIE_P4

CLK_PCIE_N5

CLK_PCIE_P5

CLK_PCIE_N6

CLK_PCIE_P6

CLK_PCIE_N7

CLK_PCIE_P7

PAD

T37

@

PAD

T38

@

CPU_PCIBCLK# <9>
CPU_PCIBCLK <9>

CLK_PEG_GPU_N0 <41>

CLK_PEG_GPU_P0 <41>

CLK_PCIE_N1 <32>

CLK_PCIE_P1 <32>

CLK_PCIE_N2 <31>

CLK_PCIE_P2 <31>

CLK_PCIE_N3 <31>

CLK_PCIE_P3 <31>

CLK_PCIE_N4 <30>

CLK_PCIE_P4 <30>

CLK_PCIE_N5 <68>

CLK_PCIE_P5 <68>

CLK_PCIE_N6 <28>

CLK_PCIE_P6 <28>

CLK_PCIE_N7 <28>

CLK_PCIE_P7 <28>

CLK_PEG_GPU_S_N8 <53>

CLK_PEG_GPU_S_P8 <53>

E

PEG master

CR

WIGI G

WLAN

LAN

Thunderbol t

SSD Slot_1

SSD Slot_2

PEG secondary

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

A

B

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

C

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(4/7)CLK

PCH(4/7)CLK

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

D

Date: Sheet o f

PCH(4/7)CLK

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1.0

1.0

21 103Monday, January 09, 2017

21 103Monday, January 09, 2017

E

21 103Monday, January 09, 2017

1.0

A

B

C

D

E

Functional Strap Definitions

GSPI1_MOSI / GPP_B22
int. PD
Boot BIOS Destination
0 = SPI (Default)
1 = LPC

1 1

GSPI0_MOSI / GPP_B18
int.

PD
0 = Disable “ No Reboot ” mode. ( Def ault)
1 = Enable “ No Reboot ” mode ( PCH will di sable t he T CO
Timer system reboot feature).

+3VS

UART_2_CRXD_DTXD

RH73 49.9K_0402_1%
RH74 49.9K_0402_1%
RH75 49.9K_0402_1%
RH76 49.9K_0402_1%

2 2

+3VALW _PCH_PRIM

12

UART_2_CTXD_DRXD

12

UART_2_CCTS_DRTS

12

@

UART_2_CRTS_DCTS

12

@

+3VS

1 2

RH144 1K_0402_5%

1 2

RH145 1K_0402_5%

1 2

RH146 2.2K_0402_5%

1 2

RH147 2.2K_0402_5%

+3VS

1 2

RH162 10K_0402_5%

I2C_0_SCL

I2C_0_SDA

I2C_1_SCL

I2C_1_SDA

DGPU_PW R_EN

+3VS

PCH internal PU by BIOS set t i ng

EC_SCI#_B20

8 move to B11

B1
confirmed

del TS_EN

DGPU_PW R_LEVEL<38,41,53>

DGPU_HOLD_RST#_S<53>
DGPU_HOLD_RST#<41>

DGPU_PW R_EN<38,41,45,53,57>

UART_2_CTXD_DRXD<31>

UART_2_CRXD_DTXD<31>

@

RH7 10K_0402_5%

RH8 0_0402_5%

1 2

RH143 0_0402_5%

12

1 2

@

remove EC_LID_OUT#

confirm with SW

GPU_EVENT_S_R#
GC6_FB_EN_R
GPU_EVENT_R#

DGPU_PW R_LEVEL_R

@

DGPU_HOLD_RST#_S
DGPU_HOLD_RST#
DGPU_PW R_EN

UART_2_CCTS_DRTS
UART_2_CRTS_DCTS
UART_2_CTXD_DRXD
UART_2_CRXD_DTXD

EC_SCI#_B20

I2C_1_SCL
I2C_1_SDA
I2C_0_SCL
I2C_0_SDA

EC_SCI#

EC_SCI# <38>

UH1K

AT29

GPP_B22/GSPI1_MOSI

AR29

GPP_B21/GSPI1_MISO

AV29

GPP_B20/GSPI1_CLK

BC27

GPP_B19/GSPI1_CS#

BD28

GPP_B18/GSPI0_MOSI

BD27

GPP_B17/GSPI0_MISO

AW27

GPP_B16/GSPI0_CLK

AR24

GPP_B15/GSPI0_CS#

AV44

GPP_C9/UART0_TXD

BA41

GPP_C8/UART0_RXD

AU44

GPP_C11/UART0_CTS#

AV43

GPP_C10/UART0_RTS#

AU41

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AT44

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AT43

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU43

GPP_C12/UART1_RXD/ISH_UART1_RXD

AN43

GPP_C23/UART2_CTS#

AN44

GPP_C22/UART2_RTS#

AR39

GPP_C21/UART2_TXD

AR45

GPP_C20/UART2_RXD

AR41

GPP_C19/I2C1_SCL

AR44

GPP_C18/I2C1_SDA

AR38

GPP_C17/I2C0_SCL

AT42

GPP_C16/I2C0_SDA

AM44

GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA

AJ44

GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL

SK

L-H-PCH_BGA837

REV = 1.3

@

SPT-H_PCH

GPP_D9
GPP_D10
GPP_D11
GPP_D12

GPP_D16/ISH_UART0_CTS#

11 OF 12

GPP_D15/ISH_UART0_RTS#

GPP_H20/ISH_I2C0_SCL
GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL
GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
GPP_A20/ISH_GP2
GPP_A19/ISH_GP1
GPP_A18/ISH_GP0
GPP_A17/ISH_GP7

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA

AL44
AL36

PROJECT_ID0

AL35

PROJECT_ID1

AJ39
AJ43

AL43
AK44
AK45

BC38
BB38

BD38
BE39

BC22
BD18
BE21
BD22
BD21
BB22
BC19

?

T44

@

PAD

DRAM_OC <77>

T46

@

PAD

G_INT#

1 2

RH77 10K_0402_5%

RH151
100K_0402_5%

+3VS

@

G_INT# <40>

12

@

BIOS not check in EVT 4/22

PROJECT_ID0

3 3

GPU_EVENT_R# GPU_EVENT#

GPU_EVENT_S_R# GPU_EVENT#_S

GC6_FB_EN_S_R<20>

1 2

RH78 0_0402_5%

1 2

RH79 0_0402_5%

1 2

RH156 0_0402_5%

1 2

RH155 0_0402_5%

GPU_GC6_FB_ENGC6_FB_EN_R

GPU_GC6_FB_EN_S

GPU_EVENT# <41>

GPU_GC6_FB_EN <41>

GPU_EVENT#_S <53>

GPU_GC6_FB_EN_S <53>

TO DGPU

PROJECT_ID1

@

1 2

RH80 10K_0402_5%

1 2

RH81 10K_0402_5%

1 2

@

RH82 10K_0402_5%

1 2

RH83 10K_0402_5%

Project ID

*

C1PR2
Reserved
Reserved
Reserved

4 4

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/02/01 2017/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

+3VALW _PCH_PRIM

Project_ID0Project_ID1

GPP_D11GPP_D12
0 0
0

1

1
0

1 1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PCH(5/7)UART,I2C,GPIO

PCH(5/7)UART,I2C,GPIO

PCH(5/7)UART,I2C,GPIO

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

22 103Monday, January 09, 2017

22 103Monday, January 09, 2017

22 103Monday, January 09, 2017

E

1.0

1.0

1.0

A

@

@

22U_0603_6.3V6M

+1.0VALW_PRIM+1.0VALW

+1.0VALW_DCPDSW

Near PIN
BA29

1

CH15
1U_0402_6.3V6K

2

+1.0VALW_VCCCLK

1

CH28

2

+1.0VALW_VCCCLK5

22U_0603_6.3V6M

CH29

1

2

Near PIN
K2,K3

1

CH27
1U_0402_6.3V6K

2

@

RH86 0_0805_5%

1 2

@

1 1

RH137 for Deep SX.

+1.0VALW

2 2

1 2

RH137 0_0402_5%

1 2

RH138 0_0603_5%

LH3

FBMA-L11-160808-800LMT_0603

1 2

modify follow PDG 05/18

+1.0VALW_AUSB_AZPLL

@

CH47

22U_0603_6.3V6M

Near PIN
U21,U23,U25,U26,V26

CH17

22U_0603_6.3V6M

+1.0VALW_AUSB_AZPLL

CH23

22U_0603_6.3V6M

+1.0VALW_PRIMAL22

@

+1.0VALW_PRIMAD15

@

+1.0VALW_MPHY

1 2

RH113 0_0603_5%

NO USE MPHYGT ON H
CHANGE TO +1.0VALW_MPHY

1 2

3 3

4 4

LH1

FBMA-L11-160808-800LMT_0603

1 2

LH2

FBMA-L11-160808-800LMT_0603

1 2

RH140 0_0402_5%

1 2

RH141 0_0402_5%

1

1

2

2

1

1

2

2

1

1

2

2

1U_0402_6.3V6K

CH48

+1.0VALW_AMPHYPLL

22U_0603_6.3V6M

CH18

Near PIN
AJ5,AL5

CH24
22U_0603_6.3V6M

modify follow PDG 05/18

1U_0402_6.3V6K

1U_0402_6.3V6K

CH37

CH38

1

1

2

2

Near PIN V28
Near PIN AC17

Near PIN
A42,A43,B43

1

CH19
1U_0402_6.3V6K

2

@

B

+1.0VALW_DCPDSW

+1.0VALW_VCCCLK

+1.0VALW_VCCCLK5

+1.0VALW_MPHY

+1.0VALW_AMPHYPLL

+1.0VALW_MPHY

+3VALW_HDA
+3VALW_DSW

CH68

.1U_0402_16V7K

+1.0VALW_PRIM

MAX 1.307A

1

2

Near PIN W15
Add 05/18

+3VALW_PCH_PRIM

1

@

2

+3VALW_PCH_PRIM

22U_0603_6.3V6M

1

@

2

2.899A

0.0454A

0.021A

0.050A

0.024A

0.137A

0.006A

0.110A

0.030A

0.533A

0.012A

0.033A

0.075A

1

CH54
1U_0402_6.3V6K

2

1U_0402_6.3V6K

CH39

22U_0603_6.3V6M

CH41

1

@

2

PCH_EDS Table10-4
1

2/30 J

AA23

VCCPRIM_1P0

AA26

VCCPRIM_1P0

AA28

VCCPRIM_1P0

AC23

VCCPRIM_1P0

AC26

VCCPRIM_1P0

AC28

VCCPRIM_1P0

AE23

VCCPRIM_1P0

AE26

VCCPRIM_1P0

Y23

VCCPRIM_1P0

Y25

VCCPRIM_1P0

BA29

DCPDSW_1P0

N17

VCCCLK1

R19

VCCCLK3

U20

VCCCLK4

V17

VCCCLK2

R17

VCCCLK2

K2

VCCCLK5

K3

VCCCLK5

U21

VCCMPHY_1P0

U23

VCCMPHY_1P0

U25

VCCMPHY_1P0

U26

VCCMPHY_1P0

V26

VCCMPHY_1P0

A43

VCCMPHYPLL_1P0

B43

VCCMPHYPLL_1P0

C44

VCCPCIE3PLL_1P0

C45

VCCPCIE3PLL_1P0

V28

VCCAPLLEBB_1P0

AC17

VCCPRIM_1P0

AJ5

VCCUSB2PLL_1P0

AL5

VCCUSB2PLL_1P0

AN19

VCCHDAPLL_1P0

BA15

VCCHDA

W15

VCCDSW_3P3

+1.0VALW_PRIM

@

+1.0VALW_PRIM

CH42

@

UH1H

SKL-H-PCH_BGA837

REV = 1.3

@

1U_0402_6.3V6K

1

CH40

2

22U_0603_6.3V6M

22U_0603_6.3V6M

CH44

CH43

1

1

@

2

2

C

SPT-H_PCH

CORE

MPHY

USB

VCCGPIO

8 OF 12

VCCPRIM_1P0
VCCDSW_3P3

VCCPGPPBCH
VCCPGPPBCH

VCCPGPPEF
VCCPGPPEF

VCCPRIM_3P3

VCCPRIM_1P0

VCCRTCPRIM_3P3

VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0

VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3

Power Rail Volt age

+CHG RTC

BAT5 4C(VF)

+3VL _RT C

3.38 3V(MAX)

240 mV

3.14 3V

Result : Pass

VCCPGPPA

VCCPGPPG

VCCATS
VCCRTC

DCPRTC

VCCSPI
VCCSPI

VCCSPI
VCCPGPPD
VCCPGPPD
VCCPGPPD
VCCPGPPD

D

+3VALW

+3VALW_PCH_PRIM +3VALW_SPI

AL22

0.0908A

BA24

0.195A

BA31

0.082A

BC42

0.2726A

BD40
AJ41

0.1410A

AL41
AD41

0.1318A

AN5

0.2875A

AD15

0.0061A

AD13

0.007A

BA20

0.0002A

BA22
BA26

AJ20
AJ21
AJ23
AJ25

BE41

0.029A

BE43
BE42
BC44

0.078A

BA45
BC45
BB45

BD3

0.117A

BE3
BE4

?

+1.0VALW_PRIMAL22
+3VALW_DSW

+3VALW_PCH_PRIM

+1.0VALW_PRIMAD15
+3VS_VCCATS
+3VALW_PCH_PRIM

+RTCVCC

1 2

CH26 .1U_0402_16V7K

+1.0VALW_PRIM

+3VALW_SPI

+3VALW_PCH_PRIM

+3VALW_PCH_PRIM

+RTCBATT

Near PIN BA26

JRTC1

1

3

1

NC1

2

4

2

NC2

ACES_50273-0020N-001

SP02000SJ00

CONN@

+3VALW_PCH_PRIM

RH87 0_0402_5%

.1U_0402_16V7K

1 2

RH135 0_0603_5%

1 2

RH89 0_0805_5%

1 2

RH136 0_0402_5%

1 2

RH27 0_0402_5%

1 2

CH20 1U_0402_6.3V6K

@

1 2

CH21 1U_0402_6.3V6K

@

1 2

CH22 .1U_0402_16V7K

1 2

CH25 1U_0402_6.3V6K

1 2

CH30 .1U_0402_16V7K

1 2

CH31 .1U_0402_16V7K

1 2

CH32 .1U_0402_16V7K

1 2

CH35 .1U_0402_16V7K

1 2

CH36 1U_0402_6.3V6K

1 2

@

1

CH46

2

+3VALW_DSW

@

+3VALW_PCH_PRIM

@

+3VALW_HDA

@

@

Near PIN BD3,BE3,BE4

Near PIN BA20

Near PIN AN5

No requirment
Near PIN BC44

Near PIN BC42,BD40

Near PIN AJ41 , AL41

Near PIN AD41

Near PIN BA20

+3VS_VCCATS+3VS

1 2

CH16 1U_0402_6.3V6K

Near PIN

@

AD13

RTC Battery

Change to non-charge circuit
DVT 7/11

+RTCVCC +RTCBATT

1

2

CH45

1U_0402_6.3V6K

DH2

1

CHN202UPT_SC70-3

PN : SC600000B00

E

3

RH163 1K_0402_5%

W=20mils

2

1 2

+CHGRTC

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(6/7)POWER

PCH(6/7)POWER

PCH(6/7)POWER

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

E

23 103Monday, January 09, 2017

23 103Monday, January 09, 2017

23 103Monday, January 09, 2017

1.0

1.0

1.0

A

1 1

B

C

D

E

UH1I

SPT-H_PCH

AC18

VSS

AN4

VSS

AN10

VSS

BE14

VSS

BE18

VSS

BE23

VSS

BE28

VSS

BE32

VSS

BE37

VSS

BE40

VSS

BE9

VSS

C10

VSS

C2

VSS

C28

VSS

C37

VSS

J7

VSS

K10

VSS

M35
M42

AA17
AA18
AA20
AA21
AA25
AA29

AA42
AB10

K27
K33
K36

K4
K42
K43

L12
L13
L15

L4

L41

L8

N10
N15
N19
N22
N24
N35
N36

N4
N41

N5
P17
P19
P22
P45
R10
R14
R22
R29
R33
R38

R5

T1

T2

T4

Y18
Y20
Y21
Y26
Y28

Y29
A18
A25
A32
A37

AA4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

9 OF 12

S

KL-H-PCH_BGA837

@

UH1J

BD2

VSS

BD45

2 2

3 3

BD44

BE44

D45

BB1
BC1

A42
B45
B44

A4
A3
B2
A2
B1

A44

C1
D1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

RSVD
RSVD

SKL-H-PCH_BGA837

SPT-H_PCH

AR22

RSVD

W13

RSVD

U13

RSVD

P31

RSVD

N31

RSVD

P27

RSVD

R27

RSVD

N29

RSVD

P29

RSVD

AN29

RSVD

R24

RSVD

P24

RSVD

XDP_PREQ#

AT3

PREQ#

PRDY#

CPU_TRST#

PCH_TRIGOUT

PCH_TRIGIN

10 OF 12

REV = 1.3

@

AT4
AY5
AL2
AK1

?

XDP_PRDY#
CPU_XDP_TRST#
PROC_TRIGIN
PROC_TRIGOUT_R

RH114 30_0402_1%

XDP_PREQ# <6,9>
XDP_PRDY# <6,9>
CPU_XDP_TRST# <6,9>

12

PROC_TRIGIN_R <13>

PROC_TRIGOUT_R <13>

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

REV = 1.3

AR5
AR7
U15
AL4
AE29
AE4
AE42
AF18
AF20
AF21
AF23
AF25
AF26
AF28
AF29
AG11
AG13
AG31
AG32
AG33
AG38
AG4
AH1
AH17
AH18
AH20
AH21
AH23
AH25
AH26
AH28
AH29
AH45
AJ10
AJ14
AJ15
AJ17
AJ18
AJ26
AJ28
AJ29
AJ31
AJ32
AJ36
AK4
AK42
AU7
AV17
AV24
AV27
AV31
AV33
AV6
AW13
AW19
AW29
AW37
AW9
AY38
AY45
B25
B3
B37
B40
B6
BA1
BB11
BB16
BB21
BB25
BB30
BB34
BC2
BD43

?

W14
W31
W32
W33
W38

C42
D10
D12
D15
D16
D17
D19
D21
D24
D25
D27
D29
D30
D31
D33
D35
D36
E13
E15
E31
E33
F44

F8

G42

G9
H17
H19
H22
H24
H27
H29

H3
H35

J10
J11

J3

J39

J5
T42
U10
U11
U14
U17
U18
U28
U29
U31
U32
U33
U38

U4

U8
V18
V20
V21
V23
V25
V29

V3
V45

W4
W8

Y17

SPT-H_PCH

UH1L

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

S

KL-H-PCH_BGA837

@

12 OF 12

REV = 1.3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB11
AB7
AB14
AB31
AB32
AB38
AB4
AB5
AC1
AC20
AC21
AC25
AC29
AC45
AB8
AD11
AD14
AB15
AD32
AD33
AD36
AD4
AD8
AE18
AE20
AE21
AE25
AE28
AL10
AL11
AL13
AL17
AL19
AL24
AL29
AL32
AL33
AL38
AM15
AM17
AM19
AM22
AM24
AM27
AM29
AM45
AN11
AN22
AN27
AN31
AN39
AN7
AN8
AP11
AP4
AR33
AR34
AR42
AR9
AT10
AT15
AT36
AT9
AU1
AU35
AU36
AU39
AU45
C4

?

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

A

B

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

C

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(7/7)GND

PCH(7/7)GND

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

D

Date: Sheet o f

PCH(7/7)GND

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1.0

1.0

24 103Monday, January 09, 2017

24 103Monday, January 09, 2017

E

24 103Monday, January 09, 2017

1.0

A

B

C

D

E

1 1

1 2

SUSP#<26,28,32,38,68,75,77,79,80>

10mil

2 2

3 3

@

R342 0_0402_5%

R344 10K_0402_5%

1 2

+5VS and +3VS switch

5VS_GATE

3VS_GATE

1

C375
.1U_0402_16V7K

2

+3VALW +5VALW

1U_0402_6.3V6K

1

C825

2

+3VALW

1

2

+5VALW

20mohm/6A per channel

1U_0402_6.3V6K

C824

U41

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

AOZ1331_SON14_2X3

SHORT DEFAULT

14

VOUT1

13

VOUT1

12

1 2

CT1

11

GND

1 2

10

CT2

9

VOUT2

8

VOUT2

15

GPAD

SHORT DEFAULT

+3VALW

C379

C378

10U_0603_6.3V6M

1

2

5VS

C368
1000P_0402_50V7K
C371
1000P_0402_50V7K

3VS

10U_0603_6.3V6M

C380

1

2

1 2

JUMP_43X118

@

1 2

JUMP_43X118

@

+5VALW

10U_0603_6.3V6M

1

2

+1.0VALW TO +1.0V_VCCST

+5VS

J15

J16

+3VS

C369

.1U_0402_16V7K

C370

10U_0603_6.3V6M

1

1

2

2

SYSON<26,38,77,78>

C376

.1U_0402_16V7K

C377

10U_0603_6.3V6M

1

1

2

2

+1.0VALW

+5VALW

1

12

C374@

C373

2

1U_0402_6.3V6K

.1U_0402_16V7K

U40

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm /6A
TR=12.5us@Vin=1.05V

VOUT

GND

+1.0V_VCCST_OUT

6

5

1

C372
.1U_0402_16V7K

2

R343

0_0603_5%

1 2

@

+1.0V_VCCST

+1.0VALW TO +1.0VS_VCCSTG

C381

10U_0603_6.3V6M

1

2

1

2

SUSP#

+1.0VALW

+5VALW

.1U_0402_16V7K

@

1U_0402_6.3V6K

12

C384

C383

U42

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm /6A
TR=12.5us@Vin=1.05V

VOUT

GND

+1.0VS_VCCSTG_OUT

6

5

12

C382
.1U_0402_16V7K

+1.0VS_VCCSTG

R347

0_0603_5%

12

@

@

+1.0VS_VCCSTG

1

C385
.1U_0402_16V7K

2

del Load SW for +3VALW_PCH

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

A

B

MAYBE USED BY OR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

C

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet o f

Date: Sheet o f

D

Date: Sheet

Compal Electronics, Inc.

DC/DC Interface

DC/DC Interface

DC/DC Interface
C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

E

1.0

1.0

1.0

of

25 103Monday, January 09, 2017

25 103Monday, January 09, 2017

25 103Monday, January 09, 2017

A

B

C

D

E

1 2

61

SDATA

ALERT#

SCLK

+0.6VS_VTT+5VALW

+5VALW+1.2V_VDDQ

8
7
6
5

12

R12
470_0603_5%@

+0.6VS_VTT_R

34

Q26B

@

DMN66D0LDW-7_SOT363-6

5

SUSP

R14
100K_0402_5%

@

1 2

SYSON#

34

5

Q27B

@

DMN66D0LDW-7_SOT363-6

EC_SMB_CK2
EC_SMB_DA2

TH_ALERT#

1 2

R798 10K_0402_5%

SYSON <25,38,77,78>

EC_SMB_CK2 <20,32,36,38,41,53>
EC_SMB_DA2 <20,32,36,38,41,53>

+3VS

For Power Of f Sequence

R11

100K_0402_5% @

SUSP

SUSP#<25,28,32,38,68,75,77,79,80>

R16

10K_0402_5%

@

SYSON# SYSON

DMN66D0LDW-7_SOT363-6

+3VS

.1U_0402_16V7K

C823

1

2

TH_THERM#

R1

100K_0402_5%

Q20B

5

R2

100K_0402_5%

Q23B

5

+3VALW

12

34

+3VALW

12

34

PM_SLP_S3

PM_SLP_S4

Q20A
DMN66D0LDW-7_SOT363-6

61

2
2

61

Q21A
DMN66D0LDW-7_SOT363-6

5

34

Q21B
DMN66D0LDW-7_SOT363-6

Q22A

@

DMN66D0LDW-7_SOT363-6

61

2
5

34

Q22B

@

DMN66D0LDW-7_SOT363-6

Reserved 05/18

Q23A
DMN66D0LDW-7_SOT363-6

61

2

EC_VCCST_PG_R <9,38>

For tCPU28 200us(max)

VR_ON <38,80,81>

For tPLT17 200us(max)

SUSP#

For tPLT18 200us(max)

SYS_PWROK <20,38>

PCH_PW ROK <20,38>

SYSON

For tPLT15 200us(max)

External Thermal Sensor

+3VS

1 2

R801 10K_0402_5%

1 1

DMN66D0LDW-7_SOT363-6

PM_SLP_S3#<20,38>

2 2

DMN66D0LDW-7_SOT363-6

3 3

PM_SLP_S4#<20,38,77>

1 2

61

2

Q26A

@

12

DMN66D0LDW-7_SOT363-6

R13

470_0603_5%

@

2

Q27A

@

U52

1

VDD

2

D+

3

D­THERM#4GND

ADM1032ARMZ-2REEL_MSOP8

PN : SA00003PU00

4 4

Security Classification

Security Classification

Security Classification

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/02/01 2017/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

DC Interface

DC Interface

DC Interface

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1.0

1.0

1.0

26 103Monday, January 09, 2017

26 103Monday, January 09, 2017

26 103Monday, January 09, 2017

E

A

+3VS

1 1

2 2

4.7K_0402_5%

4.7K_0402_5%

12

12

R30

R31

4.7K_0402_5%

4.7K_0402_5%

R36

R37

@

1 2

@

1 2

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

12

12

1 2

R34

R33

@

@

4.7K_0402_5%

4.7K_0402_5%

R39

R40

1 2

4.7K_0402_5%

12

R32

R41

@

@

1 2

A_DE
B_DE

A_EQ1
A_EQ2

B_EQ1
B_EQ2

4.7K_0402_5%

4.7K_0402_5%

12

R38

R42

1 2

B

C

D

E

HDD Re-Driver

U7

12

SATA_PTX_DRX_P2<19>
SATA_PTX_DRX_N2<19>

SATA_PRX_DTX_P2<19>

SATA_PRX_DTX_N2<19>

C38 0.01U_0402_16V7K

12

C30 0.01U_0402_16V7K

12

C31 0.01U_0402_16V7K

12

C36 0.01U_0402_16V7K

+3VS

SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2

SATA_PRX_C_DTX_P2
SATA_PRX_C_DTX_N2

A_EQ1
A_EQ2

B_EQ1
B_EQ2

1 2

R27 4.7K_0402_5%@
R29 4.99K_0402_1%

12

1

A_INP

2

A_INN

5

B_OUTP

4

B_OUTN

17

A_EQ1

18

A_EQ2

19

B_EQ1

13

B_EQ2

7

EN

6

REXT

PS8527CTQFN20GTR2A2_TQFN20_4X4

A_OUTP
A_OUTN

B_INN

VDD
VDD

B_INP

A_DE
B_DE

DEW

EPAD

GND

+3VS

10
20

15
14

11
12

9
8
16
21

3

RDSATA_PTX_DRX_P2
RDSATA_PTX_DRX_N2

RDSATA_PRX_DTX_P2

RDSATA_PRX_DTX_N2
A_DE
B_DE

+3VS

0.1U_0402_16V7K

0.01U_0402_16V7K

1

1

2

C33

C32

2

HDD cable Conn

JHDD1

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

G1

22

G2

23

G3

24

G4

STARC_115B20-100020-G2-R

SP010022I00

change for DVT

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

HDD & G-Sensor

HDD & G-Sensor

HDD & G-Sensor

E

1.0

1.0

1.0

27 103Monday, January 09, 2017

27 103Monday, January 09, 2017

27 103Monday, January 09, 2017

1 2

@

1 2

R357 0_0402_5%@

RDSATA_PTX_C_DRX_P2
RDSATA_PTX_C_DRX_N2

RDSATA_PRX_C_DTX_N2
RDSATA_PRX_C_DTX_P2

+3VS

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

RDSATA_PTX_DRX_P2
RDSATA_PTX_DRX_N2

RDSATA_PRX_DTX_N2

3 3

+5VS_HDD

RDSATA_PRX_DTX_P2

1 2

C34 0.01U_0402_16V7K

1 2

C35 0.01U_0402_16V7K

1 2

C39 0.01U_0402_16V7K

1 2

C37 0.01U_0402_16V7K

100mils

C42

1000P_0402_50V7K

C41

.1U_0402_16V7K

C40

10U_0603_6.3V6M

1

2

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

1

1

@

2

2

G_INT2<40>

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

C

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+5VS +5VS_HDD

R412 0_0805_5%

D

5

4

3

2

1

SSD

NGFF Slot_1 Key M

JSSD1

1

GND

3

GND

5

PERn3

7

PERp3

9

GND

11

PETn3

13

PETp3

15

GND

17

PERn2

19

PERp2

21

GND

23

PETn2

25

PETp2

27

GND

29

PERn1

31

PERp1

33

GND

35

PETn1

37

PETp1

39

GND

41

PERn0/SA TA-B+

43

PERp0/SA TA-B-

45

GND

47

PETn0/SATA-A -

49

PETp0/SATA-A +

51

GND

53

REFCLKN

55

REFCLKP

57

GND

67

NC
PEDET(NC-PCIE/GND-SATA)693P3VAUX

71 72

GND

73

GND

75

GND

LOTES_APCI0096-P00 2A

CONN@

SP07001CS00

Note: Replace Footprint, PN, Value on original symbol

CLK_PCIE_N6

CLK_PCIE_P6

+3VS_NGFF1

12

PCIE_PRX_DTX_N12
PCIE_PRX_DTX_P12

PCIE_PTX_C_DRX_N12
PCIE_PTX_C_DRX_P12

PCIE_PRX_DTX_N11
PCIE_PRX_DTX_P11

PCIE_PTX_C_DRX_N11
PCIE_PTX_C_DRX_P11

PCIE_PRX_DTX_N10
PCIE_PRX_DTX_P10

PCIE_PTX_C_DRX_N10
PCIE_PTX_C_DRX_P10

PCIE_PRX_R_DTX_P9
PCIE_PRX_R_DTX_N9

PCIE_PTX_C_DRX_N9
PCIE_PTX_C_DRX_P9

PEDET0

PCIE_PRX_DTX_N12<19>
PCIE_PRX_DTX_P12<1 9>

D D

C C

PCIE_PTX_DRX_N12<19>
PCIE_PTX_DRX_P12<19 >

PCIE_PRX_DTX_N11<19>
PCIE_PRX_DTX_P11<1 9>

PCIE_PTX_DRX_N11<19>
PCIE_PTX_DRX_P11<19 >

PCIE_PRX_DTX_N10<19>
PCIE_PRX_DTX_P10<1 9>

PCIE_PTX_DRX_N10<19>
PCIE_PTX_DRX_P10<19 >

PCIE_PRX_DTX_P9<19>
PCIE_PRX_DTX_N9<19>

PCIE_PTX_DRX_N9<19>
PCIE_PTX_DRX_P9<19>

SATA_GP0<19>

1 2

CN1 0.22U_0402_16V7K

1 2

CN2 0.22U_0402_16V7K

1 2

CN3 0.22U_0402_16V7K

1 2

CN4 0.22U_0402_16V7K

1 2

CN5 0.22U_0402_16V7K

1 2

CN6 0.22U_0402_16V7K

1 2

RN1 0_0402_5%@

1 2

RN2 0_0402_5%@

1 2

CN7 0.22U_0402_16V7K

1 2

CN8 0.22U_0402_16V7K

CLK_PCIE_N6<21>
CLK_PCIE_P6<2 1>

RN4

10K_040 2_5%

1 2

@

RN5 0_0402_ 5%

34

D

G

5

S

Q35A

@

DMN66D0LDW -7_SOT36 3-6

3P3VAUX
3P3VAUX

DAS/DSS#

3P3VAUX
3P3VAUX
3P3VAUX
3P3VAUX

DEVSLP

PERST#
CLKREQ#
PEWake#

SUSCLK(32 kHz)

3P3VAUX
3P3VAUX

GND1
GND2

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC

NC
NC

(left side)

+3VS_NGFF1

2
4
6
8

PCIE_LED1#

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58

SUSCLK_S SD1

68
70

74
76

77

DEVSLP0 <1 8>

PLT_RST_BUF# <19,29 ,30,31,32,41,53,6 8>

CLKREQ_P CIE#6 <21>

1 2

@

RN3 0_0402_5%

SUSCLK <20,29,31>

SSD

NGFF Slot_2 Key M

JSSD2

1

GND

3

GND

5

PERn3

7

PERp3

9

GND

11

PETn3

13

PETp3

15

GND

17

PERn2

19

PERp2

21

GND

23

PETn2

25

PETp2

27

GND

29

PERn1

31

PERp1

33

GND

35

PETn1

37

PETp1

39

GND

41

PERn0/SA TA-B+

43

PERp0/SA TA-B-

45

GND

47

PETn0/SATA-A -

49

PETp0/SATA-A +

51

GND

53

REFCLKN

55

REFCLKP

57

GND

67

NC
PEDET(NC-PCIE/GND-SATA)693P3VAUX

71 72

GND

73

GND

75

GND

LOTES_APCI0096-P00 2A

CONN@

SP07001CS00

Note: Replace Footprint, PN, Value on original symbol

RN9

PCIE_PRX_DTX_N20
PCIE_PRX_DTX_P20

PCIE_PTX_C_DRX_N20
PCIE_PTX_C_DRX_P20

PCIE_PRX_DTX_N19
PCIE_PRX_DTX_P19

PCIE_PTX_C_DRX_N19
PCIE_PTX_C_DRX_P19

PCIE_PRX_DTX_N18
PCIE_PRX_DTX_P18

PCIE_PTX_C_DRX_N18
PCIE_PTX_C_DRX_P18

PCIE_PRX_R_DTX_P17
PCIE_PRX_R_DTX_N17

PCIE_PTX_C_DRX_N17
PCIE_PTX_C_DRX_P17

CLK_PCIE_N7

CLK_PCIE_P7

+3VS_NGFF2

12

PEDET1

PCIE_PRX_DTX_N20<19>
PCIE_PRX_DTX_P20<19 >

PCIE_PTX_DRX_N20<19>
PCIE_PTX_DRX_P20<19 >

PCIE_PRX_DTX_N19<19>
PCIE_PRX_DTX_P19<19 >

PCIE_PTX_DRX_N19<19>

B B

A A

PCIE_PTX_DRX_P19<19 >

PCIE_PRX_DTX_N18<19>
PCIE_PRX_DTX_P18<19 >

PCIE_PTX_DRX_N18<19>
PCIE_PTX_DRX_P18<19 >

PCIE_PRX_DTX_P17<19 >
PCIE_PRX_DTX_N17<19>

PCIE_PTX_DRX_N17<19>
PCIE_PTX_DRX_P17<19 >

SATA_GP1<19>

1 2

CN9 0.22U_0402_16V7K

1 2

CN10 0.22U_0 402_16V 7K

1 2

CN11 0.22U_0 402_16V 7K

1 2

CN12 0.22U_0 402_16V 7K

1 2

CN13 0.22U_0 402_16V 7K

1 2

CN14 0.22U_0 402_16V 7K

1 2

RN7 0_0402_5%@

1 2

RN6 0_0402_5%@

1 2

CN15 0.22U_0 402_16V 7K

1 2

CN16 0.22U_0 402_16V 7K

CLK_PCIE_N7<21>
CLK_PCIE_P7<21>

10K_040 2_5%

1 2

@

RN10 0_0402 _5%

61

D

G

2

S

Q35B

@

DMN66D0LDW -7_SOT36 3-6

3P3VAUX
3P3VAUX

DAS/DSS#

3P3VAUX
3P3VAUX
3P3VAUX
3P3VAUX

DEVSLP

PERST#

CLKREQ#

PEWake#

SUSCLK(32 kHz)

3P3VAUX
3P3VAUX

GND1
GND2

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC

NC
NC

(left side)

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58

68
70

74
76

77

+3VS_NGFF2

PCIE_LED2#

PLT_RST_BUF#

SUSCLK_S SD2

DEVSLP1 <1 8>

CLKREQ_P CIE#7 <21>

1 2

@

RN8 0_0402_5 %

SUSCLK

+3VS_NGFF PWR

RN19

10K_040 2_5%

+3VS_NGFF1

0.047U_0402_16V4Z

1

2

PEDET

+3VS_NGFF2

0.047U_0402_16V4Z

1

2

PEDET

R351 0_0402_ 5%

C391

1

2

+3VS+3VS

33P_0402_50V8J

1

2

+3VALW

10U_0603_6.3V6M

12

RN18
10K_040 2_5%

PCIE_LED1#

PCIE_LED2#

1

CN19

2

@

C392

10U_0603_6.3V6M

1

2

33P_0402_50V8J

CN20

SUSP#<25,26,32,38 ,68,75,77,79,80>

12

0.047U_0402_16V4Z

1

CN17

CN18

2

Module Type
0
1

0.047U_0402_16V4Z

1

CN24

2

SATA

PCIE

33P_0402_50V8J

33P_0402_50V8J

1

1

CN26

CN25

CN27

2

2

Module Type
0
1

SATA

PCIE

12

C388

0.01U_0402_16V7K

1
2

22U_0603_6.3V6M

1

CN21

2

22U_0603_6.3V6M

1

CN28

2

+3V_NGFF_GATE

12

+5VALW

+3VS

5

VCC

IN1
IN2

GND

MC74VHC1G 08DFT2G_SC70-5

3

22U_0603_6.3V6M

1

CN22

2

22U_0603_6.3V6M

1

CN29

2

+3VALW

+3VALW

1U_0402_6.3V6K

1

2

U71

4

OUT

1

+

CN23
220U_B2_4VM_R35M

2

U43

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

AOZ1331_SON14_2 X3

20mohm/6A per channel

C826

PCIE_LED#

SATA_LED#<19 >

14

VOUT1

13

VOUT1

12

CT1

11

GND

10

CT2

9

VOUT2

8

VOUT2

15

GPAD

SHORT DEFAULT

+3VS

5

U72

1

VCC

IN1

OUT

2

IN2

GND

MC74VHC1G 08DFT2G_SC70-5

3

placement close PCIE SSD side

1

+

CN40
330U_D2E _6.3VM_R25M

2

+3V_NGFF_1

C435

1 2

1000P_0 402_50V 7K
C434

1 2

1000P_0 402_50V 7K

PCIE_SATA_LED#

4

CR_LED#<32>

+3V_NGFF_2

RN20
10K_040 2_5%

1 2

JUMP_43X118

@

1 2

JUMP_43X118

@

+3VS

12

@

+3VS_NGFF1

J17

+3VS_NGFF2

J27

+3VS

5

1

VCC

IN1

2

IN2

GND

MC74VHC1G 08DFT2G_SC70-5

3

C387

10U_0603_6.3V6M

C386

.1U_0402_16V7K

1

1

2

2

C407

10U_0603_6.3V6M

C408

.1U_0402_16V7K

1

1

2

2

U73

4

OUT

STORAGE_L ED# <38>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

5

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

M.2 SSD PCIe/SATA

M.2 SSD PCIe/SATA

M.2 SSD PCIe/SATA

Document Number Re v

Document Number Re v

Document Number Re v

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

28 103Monday, January 09, 2017

28 103Monday, January 09, 2017

28 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

SSD

NGFF Slot_3 Key M

(right side)

JSSD3

1

GND

3

GND

5

PERn3

7

PERp3

9

GND

11

PETn3

D D

+3VS_NGFF1

12

RN11
10K_040 2_5%

SATA_PRX_ C_DTX_P1B
SATA_PRX_ C_DTX_N1B

SATA_PTX_C_ DRX_N1B
SATA_PTX_C_ DRX_P1B

PEDET2

1 2

SATA_PRX_ DTX_P1B<19>
SATA_PRX_ DTX_N1B<19>

SATA_PTX_DRX_N1B<19>
SATA_PTX_DRX_P1B<19>

SATA_GP2<19>

C C

CN31 0.01U_0 402_16V 7K

1 2

CN30 0.01U_0 402_16V 7K

1 2

CN32 0.01U_0 402_16V 7K

1 2

CN33 0.01U_0 402_16V 7K

RN13 0_0402_5%

1 2

@

34

D

G

5

S

Q36A

@

DMN66D0LDW -7_SOT36 3-6

13

PETp3

15

GND

17

PERn2

19

PERp2

21

GND

23

PETn2

25

PETp2

27

GND

29

PERn1

31

PERp1

33

GND

35

PETn1

37

PETp1

39

GND

41

PERn0/SA TA-B+

43

PERp0/SA TA-B-

45

GND

47

PETn0/SATA-A -

49

PETp0/SATA-A +

51

GND

53

REFCLKN

55

REFCLKP

57

GND

67

NC
PEDET(NC-PCIE/GND-SATA)693P3VAUX

71 72

GND

73

GND

75

GND

LOTES_APCI0096-P00 2A

CONN@

SP07001CS00

3P3VAUX
3P3VAUX

DAS/DSS#

3P3VAUX
3P3VAUX
3P3VAUX
3P3VAUX

DEVSLP

PERST#

CLKREQ#

PEWake#

SUSCLK(32 kHz)

3P3VAUX
3P3VAUX

GND1
GND2

Note: Replace Footprint, PN, Value on original symbol

+3VS_NGFF2

2
4
6

NC

8

NC

10
12
14
16
18
20

NC

22

NC

24

NC

26

NC

28

NC

30

NC

32

NC

34

NC

36

NC

38
40

NC

42

NC

44

NC

46

NC

48

NC

50
52
54
56

NC

58

NC

SUSCLK_S SD3

68
70

74
76

77

DEVSLP2 <1 8>

PLT_RST_BUF# <19,28 ,30,31,32,41,53,6 8>

1 2

SUSCLK

@

RN12 0_0402_5%

SUSCLK <20,28,31>

+3VS_NGFF1

0.047U_0402_16V4Z

1

2

0.047U_0402_16V4Z

33P_0402_50V8J

1

1

1

CN36

CN35

CN34

2

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

33P_0402_50V8J

1

1

CN39

CN38

CN37

2

2

PEDET

0
1

B B

1 2

SATA_PRX_ DTX_P3<19>
SATA_PRX_ DTX_N3<1 9>

SATA_PTX_DRX_N3<1 9>
SATA_PTX_DRX_P3<19>

SATA_GP3<19>

A A

5

CN42 0.01U_ 0402_16 V7K

1 2

CN41 0.01U_ 0402_16 V7K

1 2

CN43 0.01U_ 0402_16 V7K

1 2

CN49 0.01U_ 0402_16 V7K

RN17 0_0402_5%

1 2

61

D

S

Q36B
DMN66D0LDW -7_SOT36 3-6

PEDET

@

G

2

@

0
1

Module Type

SATA

PCIE

SATA_PRX_ C_DTX_P3
SATA_PRX_ C_DTX_N3

SATA_PTX_C_ DRX_N3
SATA_PTX_C_ DRX_P3

+3VS_NGFF2

12

RN15
10K_040 2_5%

PEDET3

Module Type

SATA

PCIE

4

SSD

NGFF Slot_4 Key M

JSSD4

1

GND

3

GND

5

PERn3

7

PERp3

9

GND

11

PETn3

13

PETp3

15

GND

17

PERn2

19

PERp2

21

GND

23

PETn2

25

PETp2

27

GND

29

PERn1

31

PERp1

33

GND

35

PETn1

37

PETp1

39

GND

41

PERn0/SA TA-B+

43

PERp0/SA TA-B-

45

GND

47

PETn0/SATA-A -

49

PETp0/SATA-A +

51

GND

53

REFCLKN

55

REFCLKP

57

GND

67

NC
PEDET(NC-PCIE/GND-SATA)693P3VAUX

71 72

GND

73

GND

75

GND

LOTES_APCI0096-P00 2A

CONN@

SP07001CS00

Note: Replace Footprint, PN, Value on original symbol

3P3VAUX
3P3VAUX

DAS/DSS#

3P3VAUX
3P3VAUX
3P3VAUX
3P3VAUX

DEVSLP

CLKREQ#

PEWake#

SUSCLK(32 kHz)

3P3VAUX
3P3VAUX

PERST#

GND1
GND2

2
4
6

NC

8

NC

10
12
14
16
18
20

NC

22

NC

24

NC

26

NC

28

NC

30

NC

32

NC

34

NC

36

NC

38
40

NC

42

NC

44

NC

46

NC

48

NC

50
52
54
56

NC

58

NC

68
70

74
76

77

3

(right side)

+3VS_NGFF1

DEVSLP3 <1 8>

PLT_RST_BUF#

SUSCLK_S SD4

1 2

SUSCLK

@

RN16 0_0402_5%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

+3VS_NGFF2

0.047U_0402_16V4Z

0.047U_0402_16V4Z

33P_0402_50V8J

33P_0402_50V8J

1

1

1

CN44

2

2

Compal Secret Data

Compal Secret Data

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1

CN45

CN50

CN46

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

CN48

CN47

2

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

M.2 SSD SATA

M.2 SSD SATA

M.2 SSD SATA

Document Number Re v

Document Number Re v

Document Number Re v

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

29 103Monday, January 09, 2017

29 103Monday, January 09, 2017

29 103Monday, January 09, 2017

1.0

1.0

1.0

5

4

3

2

1

UL1

30
29
35
36
33
32

4
2
3

25
26

28
27
41

8

XTLI

7

XTLO

5

LED_0

38
39

LED_2

23

S IC E250 0-RIV1-RL Q FN 40P E-LAN CTRL

LED_1

12

RL13
10K_040 2_5%

1

2

1U_0402_6.3V6K~D

TX_P
TX_N
RX_P
RX_N
REFCLK_P
REFCLK_N
CLKREQ#
PERST#
WAKE#

SMCLK
SMDATA

NC
TESTMODE
GND

XTLI
XTLO

ISOLAT#

LED_0
LED_1
LED_2

+AVDDL

CL23

W=20mils

1

1

CL24

2

2

1U_0402_6.3V6K~D

VDD33

AVDD33

AVDDL
AVDDL
AVDDL
AVDDL

AVDDL_REG

AVDDH

AVDDH_REG

DVDDL_REG

TRXP0

TRXN0

TRXP1

TRXN1

TRXP2

TRXN2

TRXP3

TRXN3

RBIAS

0.1U_0402_16V7K~D

W=40mils

1
16

13

+AVDDL

19
31
34
6

22

+AVDDH

9

37

+DVDDL

LAN_MDIP0

11

LAN_MDIN0

12

LAN_MDIP1

14

LAN_MDIN1

15

LAN_MDIP2

17

LAN_MDIN2

18

LAN_MDIP3

20

LAN_MDIN3

21

40

LX

24

PPS

1 2

10

+RBIAS

RL3

2.37K_0402_1%~D

+3V_LAN

+AVDDH

W=20mils

1

CL7

2

W=20mils

+DVDDL

1

1

CL6

CL5

2

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

close to UL1 pin37

1

CL8

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

1

CL9

2

0.1U_0402_16V7K~D

close to UL1 pin9 close to UL1 pin22

CL25

1

1

2

1

CL26

CL14

2

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

4.7U_0603_6.3V6K~D

CL27

1

2

0.1U_0402_16V7K~D

CL28

1

2

0.1U_0402_16V7K~D

CL29

1

2

0.1U_0402_16V7K~D

CL17

CLK_PCIE_P4<21>
CLK_PCIE_N4<21>

CLKREQ_P CIE#4<21>

PLT_RST_BUF#<19,28,29,31,32,41,53,6 8>

YL1

2

1

15P_0402_50V8J~D

W=40mils

1

CL21

2

0.1U_0402_16V7K~D

PCIE_PRX_DTX_P4
PCIE_PRX_DTX_N4

PCIE_PTX_C_DRX_P4
PCIE_PTX_C_DRX_N4

4

GND2GND

OSC1OSC

3

25MHZ_10PF_7V25000014

2

CL10

CL11

1

1A

1

1

CL19

2

2

1U_0402_6.3V6K~D

PLT_RST_BUF#

15P_0402_50V8J~D

CL20

10U_0603_6.3V6M~D

LAN_PME#

+3V_LAN

+3V_LAN

1

2

PCIE_PRX_DTX_P4<18>
PCIE_PRX_DTX_N4<18>

PCIE_PTX_C_DRX_P4<18>

+3V_LAN

PCIE_PTX_C_DRX_N4<18>

1 2

@

RL10 0_0402_ 5%

1 2

RL1 4.7K_0402_5%~D

+3V_LAN

1

CL16

2

1000P_0402_50V7K~D

D D

EC_PME#<1 9,38>

remind : if no support wake,

don't monitor this pin

+3VALW

C C

4.7U_060 3_6.3V6K

LAN_PW R_EN<38>

CL12

1

2

LAN_PW R_EN

1

CL13

0.1U_040 2_16V7K

2

1

CL15

0.1U_0402_16V7K

2

UL3

5

OUT

IN

GND

4

OC

EN

SY6288C20AAC_SOT23 -5

1
2
3

PCIE_PRX_C_DTX_P4

12

CL1 0.1U_0402_1 6V7K

PCIE_PRX_C_DTX_N4

12

CL2 0.1U_0402_1 6V7K

RL2 30K_0402_5%

1 2

RL11 10K_0402_5%

1 2

RL12 10K_0402_5%

1

CL18

2

10U_0603_6.3V6M~D

1 2

CL22

0.1U_0402_16V7K~D

close to UL1 pin13 close to UL1 pin19close to UL1 pin31close to UL1 pin1 close to UL1 pin16 close to UL1 pin6 close to UL1 pin34

B B

A A

5

check need power or not? 3/15

2

CL31

1

+VDDCT_L

1000P_0402_50V7K~D

1

CL32

2

LAN_MDIN0
LAN_MDIP0

LAN_MDIN1
LAN_MDIP1

LAN_MDIN2
LAN_MDIP2

LAN_MDIN3
LAN_MDIP3

0.1U_0402_16V7K~D

1
2
3

4
5
6

7
8
9

10
11
12

2

1

CL33

CL34

1

2

0.1U_0402_16V7K~D

1000P_0402_50V7K~D

TL1

TCT1

MCT1

TD1+

MX1+

TD1-

MX1-

TCT2

MCT2

TD2+

MX2+

TD2-

MX2-

TCT3

MCT3

TD3+

MX3+

TD3-

MX3-

TCT4

MCT4

TD4+

MX4+

TD4-

MX4-

350UH_GS T5009-CLF

2

1

CL35

CL36

1

2

1000P_0402_50V7K~D

TIMAG: S X'FORM_ IH-160 LAN,SP050006F00
BOTHHAND: S X'FORM_ GST5009-E LF LAN,SP050006B10

RJ45_CT0

24

RJ45_MIDI0 -

23

RJ45_MIDI0 +

22

RJ45_CT1

21

RJ45_MIDI1 -

20

RJ45_MIDI1 +

19

RJ45_CT2

18

RJ45_MIDI2 -

17

RJ45_MIDI2 +

16

RJ45_CT3

15

RJ45_MIDI3 -

14

RJ45_MIDI3 +

13

change to comon

2

1

CL37

CL38

1

2

0.1U_0402_16V7K~D
1000P_0402_50V7K~D

4

0.1U_0402_16V7K~D

RL6

1 2

75_0402 _1%~D

RL7

1 2

75_0402 _1%~D

RL8

1 2

75_0402 _1%~D

RL9

1 2

75_0402 _1%~D

RJ45_GND

JUMP_43X118

3

40mil

RJ45_GND

40mil

@

J5

1 2

C67
10P_040 2_50V8J

2

3

D1

EMC@

MESC5V02 BD03_SOT23-3

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

LAN Connector

RJ45_MIDI0 +
RJ45_MIDI0 ­RJ45_MIDI1 +
RJ45_MIDI2 +
RJ45_MIDI2 ­RJ45_MIDI1 ­RJ45_MIDI3 +
RJ45_MIDI3 -

LANGND

LANGND

12

JP1

XEMC@

B88069X 9231T203_4P5X3P2-2

2016/02/01 2017/12/31

2016/02/01 2017/12/31

2016/02/01 2017/12/31

JRJ45

1

TX0+

2

TX0-

3

TX1+

4

TX2+

5

TX2-

6

TX1-

7

TX3+

8

TX3-

9

GND

10

GND

SANTA_130 409-9

CONN@

DC234007A00

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

LAN E2400

LAN E2400

LAN E2400

Document Number Re v

Document Number Re v

Document Number Re v

C1PR2 LA-E051P

C1PR2 LA-E051P

C1PR2 LA-E051P

1

30 103Monday, January 09, 2017

30 103Monday, January 09, 2017

30 103Monday, January 09, 2017

1.0

1.0

1.0