Compal LA-D891P Schematics Rev1.0

Vinaﬁx.com

A

smd.db-x7.ru

B

C

D

E

MODEL NAME : LA-D891P

PCB NO : DAA000CK000

BOM P/N : 431A4E31L01

1 1

Dell/Compal Confidential

2 2

Schematic Document

Pebble Creek (Kabylake U)

3 3

2016-12-20

Rev: 1.0

ZZZ

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P01-Cover Page

LA-D891P

E

1 65Tuesday, December 20, 2016

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12.3" 3:2 Samsung WUXGA+

ALS AMS-TAOS TSL2591

Touch Cntrl Wacom G12T-W9015

1 1

2 2

RFFEM

uSD Connector

USB3.0 / DP x 2lanes or DP x 4 lanes

VBUS

Port-A USB Type-C ALT mode with PD

3 3

Port-B USB Type-C ALT mode with PD

CC 2

USB (Top)

USB (Bottom)

p.40

USB3.0 / DP x 2lanes or DP x 4 lanes

VBUS

CC 2

USB (Top)

USB (Bottom)

p.40

Gyro + Accelerometer ST LSM6DS3TR

Compass ST LIS3MDLTR

Finger Print Reader NB 2023-S

Smart Card Reader NXP TDA8034HN

on IO board

SSD M.2 2280 Slot 3-Key-M

WWAN 4G LTE M.2 3042 Slot 2-Key-B

Hardware Crypto Accelera tor

Module : EM7455

LTE Coex

WLAN / BT 4.1 M.2 2230 Slot 1-Key-A WiGig (UI 3x3(UI)

Module : 8265NGW/QCNFA344A/18265NGW

SD4.0/SDXC

SD_WP

p.27

USB3.0 TypeA BC1.2 with Power Share TI TPS2546

MOSFET

VBUS PP_5V0 CC

TI-ACE 65982-D

VBUS PP_5V0 CC

TI-ACE 65982-D

I2C

p.35

MOSFET

I2C to EC

p.36

p.23

p.25

uSIM

p.26

p.24

CHRG_IN

From EC

5V_ALW

CHRG_IN

From EC

5V_ALW

p.22

p.31

p.22

p.31

SPI

0 8 2 2

2 4 0 3

0 3 2 2

GPIO (BIOS Controlled)

p.39

to EC

to PCH

on WF camera module

SPI ROM 16M (Main)

SPI ROM 4M(2nd)

NPCT650JBAYX

USH Control Vault Broadcom 58102

RDIF/NFC Antenna

A

RealTek RTS5242 PCIe to SD

USB3.0

5V@1.5A

Parade MUX PS8743A

Kickstand Open /Close detect ion (mechanical switch)

Module : DWRFID1603

BC1.2 TI TPS2546

p.39

A

SAR Proximity Sensor Smtech SX9310

Hall Sensor APX8132 or AH1806-W

p.7

p.31

IOB conn p.43

p.27

p.39

DP1.2 MUX

p.40

eDP x2 lanes

I2C

SPI SPI#2

I2C

SPI

USB 2.0

PCIe x 2lanes

GNSS I2C

PCIe x 2lanes

USB 3.0 / SSIC

USB 2.0

PCIe x 1lane

USB2.0

eLBS

CLINK

PCIe x 1lane

USB2.0

USB3.0

DP1.2 x 4lanes

USB3.0

DP1.2 x 4lanes

I2C 3

p.31

p.42 p.30

TABLET

B

eDP

ISH

I2C

I2C (iSH)

SPI#1

USB#7

Channel A

Channel B

CSI-2#2

CSI-02#0

USB2.0#5

KabyLake U

PCIe#7,8

I2C (iSH)

PCIe#11/PCIe#12

USB3 # 2 / SSIC

USB2 # 4

PCIe#5

PCIe#6

USB2#7

UART

CLINK

PCIe#9

USB2#9 UART

USB3#3

DDI#2

USB3.0#1

USB3.0#4

DDI#1

LPC

EC MEC1641

USB2#2

I2C_CLK

I2C_DAT

I2C_INT

I2C

HDA

GPIO

Memory Bus

MIPI CSI-2 x 2lanes

I2C

MIPI CSI-2 x 2lanes

D+/D-

4x DMIC

3DMIC on M/B 1DMIC on WFCAM

Dock_Detect

Channel A - 4GB

Channel A - 4GB LPDDR3 1866 32Gb x 32 QDP

Channel B - 4GB

Channel B - 4GB LPDDR3 1866 32Gb x 32 QDP

5MP FFC 5BF501T2/OV5670

8MP RFC 5BA802T2/OV8858

Face IR Module LiteOn 5SF106N2B

HDA

1.5V

p.28

EC JTAG

SPI Programmer

USB PD Debug

DCI Debug

Audio Codec ALC3253-CG

p.19

p.20

p.33

SKYCAM PMIC TPS68470YFFR_DBSGA56

I2C

p.33

p.43

Universal Headset Jack

p.28 p.29

2x Speaker

p.29

XDP DEbug

LPC Debug

APS Debug

Coin Cell

I2C_INT

CHRG_IN

C

5V/2A

p.34

GND

DET_L

I2C1 CLK

I2C1 DAT

I2C1 INT

5V

D+

D-

12V

DET_R

GND

DET_L

I2C1 CLK

I2C1 DAT

I2C1 INT

5V

D+

D-

12V

DET_R

GND

3.3V LDO Boost

VSW_3V3

SPI ROM 2MB

USB 2.0 D+ USB 2.0 D-

WCFW_EN

POGO_DET_R#

CHG_DICS(NC)

HEAD_DET# GPIO

VR_OUT

+VCC_EC

WC_DISC

I2C#1_INT

I2C#1_DAT

I2C#1_CLK

D

SPI

WC_OUT

GND

TPS61200

A/D

SPI

I2C_CLK

I2C_DAT

I2C_INT

VCC_EC VSW_3V3

VCC

CSR1021

WC PRU Board

TX/RX

I2C_CLK

I2C_DAT

I2C_INT

GPIO GPIO

KSO/KSI

GPIO

Pi-Matching i-pex conn

PTP_MODE# PTP_SLP#

Keyboard Matrix

BT ON/OFF ButtonGPIO

I2C_CLK

I2C_DAT

I2C_INT

PTP_MODE# EN

CLK

Charge/Low_BAT#

DAT

INT

I/O Expander TI TCA6416

I2C_CLK

I2C_DAT

I2C_INT

E

USB_D-

KB_LED_PWM

KB_BL_DET# MASK_LED# MUTE_LED#

BT_LED#

Accelermeter ST LNG2DMTR

USB 2.0 D+USB_D+ USB 2.0 D-

5V 5V

Keyboard

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2015/10/22 2013/10/28

Deciphered Date

Compal Electronics, Inc.

Title

P02-Block Diagram

Size Document Numb er Rev

LA-D891P

Date: Sheet of

Date: Sheet

E

2 65Tuesday, December 20, 2016

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A

smd.db-x7.ru

B

Rear Camera + 4th DMIC

C

D

E

BTB FPC 34 pin

1 1

Front Camera + ALS sensor+ LED

BTB FPC 30 pin

JUFC1

p.33

PWR_BUTTON Board

JWFC1

p.33

LS-D896P

IOB

M/B

2 2

LA-D891P

JIOB1

p.43

BATT_CONN

p.47

LS-D891P

IOB Cable

BTB FPC 40pin

JIOB2 eDP+iTouch

p.43

3 3

p.22

Dock Board LS-D892P (K/B + Bluetooth + Wireless Charge)

Base Board

BTB FPC 30pin

eDP+itouch Y-Cable Coaxial cable 50P

iTouch

14pin

LCD Panel

40pin

LS-D893P

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P03-DaughterB block diagram

LA-D891P

LA-D891PLA-D891P

E

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Board ID Table

3.3V +/- 5%Vcc

RBoard ID

0 1 2 3 4 5 6 7

240K +/- 5% 4700p 130K +/- 5% 62K +/- 5% 33K +/- 5%

8.2K +/- 5%

4.3K +/- 5% 2K +/- 5%

NC

C

4700p 4700p 4700p 4700p 4700p 4700p

REV

EVT1 DVT1 DVT1.1 DVT2 PVT

Board ID

0 1 2 3 4 5 6 7

PCB Revision

0.1

0.2

0.3

0.4

0.5

1.0

SMBUS Control Table

SOURCE

No use

1 1

PCH_SML0CLK PCH PCH_SML0DATA

PCH_SML1CLK PCH_SML1DATA

SMBCLK SMBDATA

EC_SMB00_CLK EC_SMB00_DAT

EC_SMB01_CLK EC_SMB01_DAT

EC_SMB03_CLK EC_SMB03_DAT

EC_SMB04_CLK EC_SMB04_DAT

EC_SMB05_CLK EC_SMB05_DAT

EC_SMB07_DAT

PCH

MEC1641

MEC1641EC_SMB07_CLK

Base BATT

V

Charger

V

XDP

V

V V V

PD Controller

V VV V

Trinity Dock

MUXP-SensorUSH

Link

USB 3.0Board ID Table

Flexible I/O

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Interface DESTINATION

USB 3.0 #1

USB 3.0 #2/SSIC

USB 3.0 #3

USB 3.0 #4

PCI-E#1 / USB 3.0#5

PCI-E#2 / USB 3.0#6

PCI-E #3

PCI-E #4

PCI-E #5

PCI-E #6

PCI-E #7

PCI-E #8 /SATA #0

PCI-E #9

USB Type-C Port-A

NGFF (WWAN)

USB 3.0 Type-A

USB Type-C Port-B

Reserved for AR

NGFF (WLAN)

NGFF (WLAN-WiGig)

NGFF (SSD)

NGFF (SSD) #7/#8 2lane PCI-E

Card Reader

PCI-E #10

PCI-E #11

NGFF (WWAN/HCA/2nd SSD)

PCI-E #12 NGFF (WWAN/HCA/2nd SSD)

Port Mapping USB 2.0 CLK

DESTINATIONUSB 2.0 PORT#

1

2

3

4

5

7

Type-C Port-A

Dock

Type-C Port-B NGFF (WWAN)

WWAN

CLK

IR CAM

WLAN

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE5

DESTINATIONDIFFERENTIAL

WiGig

NGFF (WLAN)

SSD

Card Reader

Displayport

DDI PORT# DESTINATION

DDI

B

C

USB Type-C Port-B

DP MUX (WiGig/type-c port-A)

FLEX CLOCKS DESTINATION

USB Type-A9

CLKOUT_LPC_0

USH10

CLKOUT_LPC_1

EC LPC

Debug

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Nu mber Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P04-Notes List

LA-D891P

Symbol Note :

@

: means de-pop

: means Digital Ground

: means Analog Ground

1.0

4 65Tuesday, December 20, 2016

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4

3

2

1

+3VS

UCPU1A

Functional Strap Definitions GPP_E19 (Internal Pull Down): DDPB_CTRLDATA 0 = Port B is not detected. 1 = Port B is detected. GPP_E21 (Internal Pull Down): DDPC_CTRLDATA

Type-C PortB

0 = Port C is not detected. 1 = Port C is detected.

D D

Type-C PortA / WiGig

+3VS

CPU_DP2_CTRL_C LK

RC43 2.2K_0402_5%

2

RC45 2.2K_0402_5%

2

RC178 2.2K_0402_5%

RC179 2.2K_0402_5%

+3V_PRIM

12

CPU_DP2_CTRL_D ATA

1

CPU_DP1_CTRL_CLK

1

CPU_DP1_CTRL_DATA

12

+1.0VS_VCCIO

CPU_DP2_CTRL_CLK38

CPU_DP2_CTRL_DATA38

DDI1_P2_TXN037

DDI1_P2_TXP037 DDI1_P2_TXN137 DDI1_P2_TXP137

DDI1_P2_TXN237 DDI1_P2_TXP237 DDI1_P2_TXN337

DDI1_P2_TXP337

PCH_DDI2_N038 PCH_DDI2_P038

PCH_DDI2_N138 PCH_DDI2_P138

PCH_DDI2_N238 PCH_DDI2_P238 PCH_DDI2_N338

PCH_DDI2_P338

CPU_DP1_CTRL_CLK CPU_DP1_CTRL_DATA

CPU_DP2_CTRL_CLK CPU_DP2_CTRL_DATA

1 2

RC108 24.9_0 402_1%

COMPENSATION PU FOR eDP

EDP_COMP

CAD Note:Trace width=20 mils, Isolation Spacing=25mil,

1 2

RC199

C C

UFCAM_CSI2_DN033 UFCAM_CSI2_DP033

UFCAM_CSI2_DN133 UFCAM_CSI2_DP133

WFCAM_CSI2_DN433

WFCAM_CSI2_DP433 WFCAM_CSI2_DN533 WFCAM_CSI2_DP533

WFCAM_CSI2_DN633 WFCAM_CSI2_DP633 WFCAM_CSI2_DN733

WFCAM_CSI2_DP733

B B

MEDIACARD_IRQ#

10K_0402_5%

UCPU1I

@

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKL-U_BGA1356

SKL_ULT

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1

GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5

GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

Max length=100 mils.

CSI2_CLKN0

CSI2_CLKP0 CSI2_CLKN1

CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3

CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

9 OF 20

C37

D37 C32

D32 C29 D29 B26

A26

CSI2_COMP

E13

RC197

@

B7

MEM_CONFIG0

AP2

MEM_CONFIG1

AP1

MEM_CONFIG2

AP3

MEM_CONFIG3

AN3 AN1

GNSS_OFF#

AN2

PCH_WWAN_WAKE#

AM4 AM1

USH_DET#

AM2

GNSS_IRQ

AM3

WWAN_PWR_OFF#

AP4

EMMC_RCOMP

AT1

UFCAM_CSI2_CLKN033

UFCAM_CSI2_CLKP033 WFCAM_CSI2_CLKN133 WFCAM_CSI2_CLKP133

RC114

1 2

0_0402_5%

RC66 200_0402_1%

1

GNSS_OFF# 25

PCH_WWAN_WAKE#25

USH_DET# 41,43

GNSS_IRQ 25

WWAN_PWR_OFF#25

2

MEDIACARD_IRQ#27

DDR Memory Configuratino Type Strap pin

+1.8VA

RH17

RH15 10K_0402_5%

@

2

RH12 10K_0402_5%

RH9 10K_0402_5%

12

10K_0402_5%@

1

12

MEM_CONFIG0

MEM_CONFIG1

MEM_CONFIG2

MEM_CONFIG3

RH18

RH16 10K_0402_5%

@

RH13 10K_0402_5%

@

2

RH10 10K_0402_5%

12

10K_0402_5%@

12

1

12

@

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKL-U_BGA1356

100_0402_1%

SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0

X76

X7669231L05

X7669231L07

X7669231L09

X7669231L06

X7669231L08

X7669231L10

X76_8G@

X768G X76

X7669231L01

X76_16G@

X7616G X76

X7669231L02

X76_32G@

X7632G

Samsung

A A

GPIO Pin

GPP_F13

GPP_F14

GPP_F15

GPP_F16 MEM_CONFIG3

5

Pin Name

MEM_CONFIG0

MEM_CONFIG1

MEM_CONFIG2

Micron

Micron 8G

0

16G

Mircon 32G

1

0 1

1866 Mbps

000

0 0 0 0 0 0 0

Hynix

16G

8G

1

0 11

01

0

0 1

0

Hynix 32G

0

4

Samsung 8G

0

1

16G

Samsung 32G

1

0

1

0

1

0

1

X76

X7669231L03

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SKL-U

DDI

DISPLAY SIDEBANDS

Issued Date

3

C47

C46

D46

C45

A45

B45

A47

B47

E45 F45

B52

G50 F50

E48

F48

G46 F46

L9

L7 L6 N9

L10

R12

R11

U13

PCH_DP1_HPD

PCH_DP2_HPD

I2C0_IRQ_TS

WLAN_RST#

EDP_HPD

eDP_TXN_P0 22 eDP_TXP_P0 22

eDP_TXN_P1 22

eDP_TXP_P1 22

eDP_AUXN 22 eDP_AUXP 22

PCH_DDI1_AUXN 37 PCH_DDI1_AUXP37

PCH_DDI2_AUXN 38 PCH_DDI2_AUXP38

PAD~D

PCH_DP1_HPD 36,37,41

PCH_DP2_HPD 38

I2C0_IRQ_TS 22

WLAN_RST# 24

EDP_HPD 22

PANEL_BKLEN 22 EDP_BIA_PWM 22

PCH_ENVDD 22

1 OF 20

EDP

EDP_TXN[0]

EDP_TXP[0]

EDP_TXN[1]

EDP_TXP[1]

EDP_TXN[2]

EDP_TXP[2]

EDP_TXN[3]

EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP

DDI2_AUXN

DDI2_AUXP

DDI3_AUXN DDI3_AUXP

GPP_E13/DDPB_HPD0

GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

CPU Option

SR343@

UCPU1 i3 NVPro

SA0000A387L

SR342@

UCPU1 i5 NVPro

SA0000A377L

SR340@

UCPU1 i5 Vpro

SA0000ADO2L

DRAM Option (R1) , R3 check P08

Micron 8G/1866

MICRON_8G@

UD1

MT52L256M32D1PF-107WT

SA00009XU0L

Micron 16G/1866

MICRON_16G@

UD1

MT52L512M32D2PF-107WT

SA00009U70L

MICRON_8G@

UD2

MT52L256M32D1PF-107W T

SA00009XU0L

MICRON_16G@

UD2

MT52L512M32D2PF-107W T

SA00009U70L

Micron 32G/1866

MICRON_32G@

UD1

MT52L1G32D4PG-107WT

SA00009XV0L

MICRON_32G@

UD2

MT52L1G32D4PG-107W T

SA00009XV0L

Hynix 8G/1866

HYNIX_8G@

UD1

H9CCNNN8GTMLAR-NUD FBGA

SA00008G60L

Hynix 16G/1866

HYNIX_16G@

UD1

H9CCNNNBJTMLAR-NUD FBGA

SA00008FJ0L

Hynix 32G/1866

HYNIX_32G@

UD1

H9CCNNNCLTMLAR-NUD FBGA

SA00008YT0L

HYNIX_8G@

UD2

H9CCNNN8GTMLAR-NUD FBGA

SA00008G60L

HYNIX_16G@

UD2

H9CCNNNBJTMLAR-NUD FBGA

SA00008FJ0L

HYNIX_32G@

UD2

H9CCNNNCLTMLAR-NUD FBGA

SA00008YT0L

Samsung 8G/1866

SAMSUNG_8G@

UD1

K4E8E324EB-EGCF FBGA178P

SA00009XY0L

Samsung 16G/1866

SAMSUNG_16G@

UD1

K4E6E304EB-EGCF FBGA1 7

SA00008QV2L

Samsung 32G/1866

SAMSUNG_32G@

UD1

4EBE304EB-EGCF FBGA17 8

SA00008X10L

2015/10/22 2013/10/28

SAMSUNG_8G@

UD2

K4E8E324EB-EGCF FBGA178P

SA00009XY0L

SAMSUNG_16G@

UD2

K4E6E304EB-EGCF FBGA1 7

SA00008QV2L

SAMSUNG_32G@

UD2

4EBE304EB-EGCF FBGA17 8

SA00008X10L

Compal Secret Data

Deciphered Date

MICRON_8G@

UD3

MT52L256M32D1PF-107WT

SA00009XU0L

MICRON_16G@

UD3

MT52L512M32D2PF-107WT

SA00009U70L

MICRON_32G@

UD3

MT52L1G32D4PG-107WT

SA00009XV0L

HYNIX_8G@

UD3

H9CCNNN8GTMLAR-NUD FBGA

SA00008G60L

HYNIX_16G@

UD3

H9CCNNNBJTMLAR-NUD FBGA

SA00008FJ0L

HYNIX_32G@

UD3

H9CCNNNCLTMLAR-NUD FBGA

SA00008YT0L

SAMSUNG_8G@

UD3

K4E8E324EB-EGCF FBGA178P

SA00009XY0L

SAMSUNG_16G@

UD3

K4E6E304EB-EGCF FBGA1 7

SA00008QV2L

SAMSUNG_32G@

UD3

4EBE304EB-EGCF FBGA17 8

SA00008X10L

2

2Lane eDP

@

T6

@

T5

SR33Z@

UCPU1 i7 VPro

SA0000ADP2L

MICRON_8G@

UD4

MT52L256M32D1PF-107WT

SA00009XU0L

MICRON_16G@

UD4

MT52L512M32D2PF-107WT

SA00009U70L

MICRON_32G@

UD4

MT52L1G32D4PG-107WT

SA00009XV0L

HYNIX_8G@

UD4

H9CCNNN8GTMLAR-NUD FBGA

SA00008G60L

HYNIX_16G@

UD4

H9CCNNNBJTMLAR-NUD FBGA

SA00008FJ0L

HYNIX_32G@

UD4

H9CCNNNCLTMLAR-NUD FBGA

SA00008YT0L

SAMSUNG_8G@

UD4

K4E8E324EB-EGCF FBGA178P

SA00009XY0L

SAMSUNG_16G@

UD4

K4E6E304EB-EGCF FBGA1 7

SA00008QV2L

SAMSUNG_32G@

UD4

4EBE304EB-EGCF FBGA17 8

SA00008X10L

I2C0_IRQ_TS

WLAN_RST#

GNSS_IRQ

USH_DET#

GNSS_OFF#

PCH_WWAN_WAKE#

EDP_HPD

PCH_DP1_HPD

PCH_DP2_HPD

DRAM Config Option

(Resistor pop location)

MEM_CONFIG0

X76_M8G@

RH18

10K_0402_5%

SD028100280

X76_M16G@

RH17

10K_0402_5%

SD028100280

X76_M32G@

RH18

10K_0402_5%

SD028100280

X76_H8G@

RH17

10K_0402_5%

SD028100280

X76_H16G@

RH18

10K_0402_5%

SD028100280

X76_H32G@

RH17

10K_0402_5%

SD028100280

X76_S8G@

RH18

10K_0402_5%

SD028100280

X76_S16G@

RH17

10K_0402_5%

SD028100280

X76_S32G@

RH18

10K_0402_5%

SD028100280

RC194 100K_0201_5%

2

RH505

1 2

RH8 10K_0201_5%

1

@

RH7 100K_0201_5%

1 2

RH5

1 2

RH6 100K_0201_5%

1 2

RC126 100 K_0402_5%

RC124 100K_0402_5%

RC46 100K_0402_5 %

MEM_CONFIG1 MEM_CONFIG2 MEM_CONFIG3

X76_M8G@

RH16

10K_0402_5%

SD028100280

X76_M16G@

RH16

10K_0402_5%

SD028100280

X76_M32G@

RH15

10K_0402_5%

SD028100280

X76_H8G@

RH15

10K_0402_5%

SD028100280

X76_H16G@

RH16

10K_0402_5%

SD028100280

X76_H32G@

RH16

10K_0402_5%

SD028100280

X76_S8G@

RH15

10K_0402_5%

SD028100280

X76_S16G@

RH15

10K_0402_5%

SD028100280

X76_S32G@

RH16

10K_0402_5%

SD028100280

1

2

12

X76_M8G@

RH13

10K_0402_5%

SD028100280

X76_M16G@

RH13

10K_0402_5%

SD028100280

X76_M32G@

RH13

10K_0402_5%

SD028100280

X76_H8G@

RH13

10K_0402_5%

SD028100280

X76_H16G@

RH12

10K_0402_5%

SD028100280

X76_H32G@

RH12

10K_0402_5%

SD028100280

X76_S8G@

RH12

10K_0402_5%

SD028100280

X76_S16G@

RH12

10K_0402_5%

SD028100280

X76_S32G@

RH13

10K_0402_5%

SD028100280

+3VS

10K_0201_5%

+1.8VA

10K_0201_5%

X76_M8G@

RH10

10K_0402_5%

SD028100280

X76_M16G@

RH10

10K_0402_5%

SD028100280

X76_M32G@

RH10

10K_0402_5%

SD028100280

X76_H8G@

RH10

10K_0402_5%

SD028100280

X76_H16G@

RH10

10K_0402_5%

SD028100280

X76_H32G@

RH10

10K_0402_5%

SD028100280

X76_S8G@

RH10

10K_0402_5%

SD028100280

X76_S16G@

RH10

10K_0402_5%

SD028100280

X76_S32G@

RH9

10K_0402_5%

SD028100280

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P05-MCP(1/14)DDI,EDP,CSI2,EMMC

1.0

LA-D891P

5 65Tuesday, December 20, 2016

1

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

LPDDR3, Ballout for side by side(Non-Interleave)

DDR_A_DQS#[0..7]19

DDR_A_DQS[0..7]19

DDR_A_D[0..63]19

DDR_A_CA1_[0..9]19

D D

C C

B B

DDR_A_CA2_[0..9]19

UCPU1B

@

DDR_A_D0 DDR_A_D1

DDR_A_D2

DDR_A_D3

DDR_A_D4

DDR_A_D5

DDR_A_D6

DDR_A_D7

DDR_A_D8 DDR_A_D9

DDR_A_D10 DDR_A_D11

DDR_A_D12 DDR_A_D13

DDR_A_D14 DDR_A_D15 DDR_A_D32

DDR_A_D33 DDR_A_D34 DDR_A_D35

DDR_A_D36 DDR_A_D37

DDR_A_D38 DDR_A_D39 DDR_A_D40

DDR_A_D41 DDR_A_D42 DDR_A_D43

DDR_A_D44 DDR_A_D45

DDR_A_D46 DDR_A_D47 DDR_B_D0

DDR_B_D1 DDR_B_D2 DDR_B_D3

DDR_B_D4 DDR_B_D5 DDR_B_D6

DDR_B_D7 DDR_B_D8

DDR_B_D9 DDR_B_D10 DDR_B_D11

DDR_B_D12 DDR_B_D13 DDR_B_D14

DDR_B_D15 DDR_B_D32 DDR_B_D33

DDR_B_D34 DDR_B_D35

DDR_B_D36 DDR_B_D37 DDR_B_D38

DDR_B_D39 DDR_B_D40 DDR_B_D41

DDR_B_D42 DDR_B_D43

DDR_B_D44 DDR_B_D45

DDR_B_D46 DDR_B_D47

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKL-U_BGA1356

DDR_B_DQS#[0..7]20

DDR_B_DQS[0..7]20

DDR_B_D[0..63]20

DDR_B_CA1_[0..9]20

DDR_B_CA2_[0..9]20

SKL-U

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]

DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]

DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[0]

DDR0_DQSP[0]

DDR0_DQSN[1]

DDR0_DQSP[1]

DDR0_ALERT#

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

DDR CH - A

DDR0_DQSN[2]/DDR0_DQSN[4]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSP[3]/DDR0_DQSP[5]

DDR0_DQSN[4]/DDR1_DQSN[0]

DDR0_DQSP[4]/DDR1_DQSP[0]

DDR0_DQSN[5]/DDR1_DQSN[1]

DDR0_DQSP[5]/DDR1_DQSP[1]

DDR0_DQSN[6]/DDR1_DQSN[4]

DDR0_DQSP[6]/DDR1_DQSP[4]

DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_CKN[0]

DDR0_CKP[0]

DDR0_CKN[1]

DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2]

DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1]

DDR0_ODT[0]

DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_PAR

2 OF 20

AU53

AT53

AU55

AT55

BA56 BB56 AW56

AY56

AU45

AU43

AT45

AT43

BA51

BB54

BA52

AY52

AW52

AY55

AW54 BA54

BA55 AY54

AU46

AU48

AT46

AU50

AU52

AY51

AT48

AT50

BB50 AY50

BA50 BB52

AM70

AM69

AT69

AT70

BA64

AY64

AY60

BA60

BA38

AY38

AY34

BA34

BA30

AY30

AY26

BA26

AW50

AT52

AY67 AY68 BA67

AW67

DDR_A_CLK#0

DDR_A_CLK0 DDR_A_CLK#1 DDR_A_CLK1

DDR_A_CKE0 DDR_A_CKE1

DDR_A_CKE2 DDR_A_CKE3

DDR_A_CS#0

DDR_A_CS#1

DDR_A_ODT0

DDR_VTT_CNTL

DDR_A_CLK#0 19

DDR_A_CLK0 19

DDR_A_CLK#1 19 DDR_A_CLK1 19

DDR_A_CKE0 19 DDR_A_CKE1 19

DDR_A_CKE2 19 DDR_A_CKE3 19

DDR_A_CS#0 19 DDR_A_CS#1 19

DDR_A_ODT0 19

DDR_A_CA1_0 19

DDR_A_CA1_1 19 DDR_A_CA1_2 19 DDR_A_CA1_3 19

DDR_A_CA1_4 19 DDR_A_CA1_5 19 DDR_A_CA1_6 19

DDR_A_CA1_7 19 DDR_A_CA1_8 19 DDR_A_CA1_9 19

DDR_A_CA2_0 19 DDR_A_CA2_1 19 DDR_A_CA2_2 19

DDR_A_CA2_3 19 DDR_A_CA2_4 19 DDR_A_CA2_5 19

DDR_A_CA2_6 19 DDR_A_CA2_7 19 DDR_A_CA2_8 19

DDR_A_CA2_9 19

DDR_A_DQS#0 19 DDR_A_DQS0 19

DDR_A_DQS#1 19 DDR_A_DQS1 19 DDR_A_DQS#4 19

DDR_A_DQS4 19 DDR_A_DQS#5 19 DDR_A_DQS5 19

DDR_B_DQS#0 20 DDR_B_DQS0 20 DDR_B_DQS#1 20

DDR_B_DQS1 20 DDR_B_DQS#4 20 DDR_B_DQS4 20

DDR_B_DQS#5 20 DDR_B_DQS5 20

+V_DDR_REF_CA 21

+V_DDR_REFA_R 21 +V_DDR_REFB_R 21

DDR_A_D16 DDR_A_D17

DDR_A_D18

DDR_A_D19

DDR_A_D20

DDR_A_D21

DDR_A_D22

DDR_A_D23 DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27 DDR_A_D28

DDR_A_D29 DDR_A_D30 DDR_A_D31

DDR_A_D48 DDR_A_D49 DDR_A_D50

DDR_A_D51 DDR_A_D52

DDR_A_D53 DDR_A_D54 DDR_A_D55

DDR_A_D56 DDR_A_D57 DDR_A_D58

DDR_A_D59 DDR_A_D60 DDR_A_D61

DDR_A_D62 DDR_A_D63

DDR_B_D16 DDR_B_D17 DDR_B_D18

DDR_B_D19 DDR_B_D20 DDR_B_D21

DDR_B_D22 DDR_B_D23

DDR_B_D24 DDR_B_D25 DDR_B_D26

DDR_B_D27 DDR_B_D28 DDR_B_D29

DDR_B_D30 DDR_B_D31 DDR_B_D48

DDR_B_D49 DDR_B_D50

DDR_B_D51 DDR_B_D52

DDR_B_D53 DDR_B_D54 DDR_B_D55

DDR_B_D56 DDR_B_D57 DDR_B_D58

DDR_B_D59 DDR_B_D60

DDR_B_D61 DDR_B_D62 DDR_B_D63

UCPU1C

@

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKL-U_BGA1356

SKL-U

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]

DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]

DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2]

DDR1_DQSP[0]/DDR0_DQSP[2]

DDR1_DQSN[1]/DDR0_DQSN[3]

DDR1_DQSP[1]/DDR0_DQSP[3]

DDR1_DQSN[2]/DDR0_DQSN[6]

DDR1_DQSP[2]/DDR0_DQSP[6]

DDR1_DQSN[3]/DDR0_DQSN[7]

DDR1_DQSP[3]/DDR0_DQSP[7]

DDR1_DQSN[4]/DDR1_DQSN[2]

DDR1_DQSP[4]/DDR1_DQSP[2]

DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

DDR1_CKN[0] DDR1_CKN[1]

DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2]

DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1]

DDR1_ODT[0]

DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6]

DDR1_DQSP[6]

DDR1_DQSN[7]

DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR

DRAM_RESET#

DDR_RCOMP[0] DDR_RCOMP[1]

DDR_RCOMP[2]

3 OF 20

AN45 AN46

AP45 AP46

AN56 AP55 AN55

AP53

BB42

AY42

BA42

AW42

AY48

AP50

BA48

BB48

AP48

AP52

AN50 AN48

AN53 AN52

BA43

AY43

AY44

AW44

BB44

AY47

BA44

AW46

AY46 BA46

BB46 BA47

AH66

AH65

AG69

AG70

AR66

AR65

AR61

AR60

AT38

AR38

AT32

AR32

AR25

AR27

AR22

AR21

AN43

AP43

AT13

AR18 AT18

AU18

DDR_B_CLK#0

DDR_B_CLK#1

DDR_B_CLK0

DDR_B_CLK1

DDR_B_CKE0

DDR_B_CKE1

DDR_B_CKE2 DDR_B_CKE3

DDR_B_CS#0 DDR_B_CS#1

DDR_B_ODT0

SM_RCOMP0

SM_RCOMP1 SM_RCOMP2

DDR_B_CLK#0 20

DDR_B_CLK#1 20 DDR_B_CLK0 20

DDR_B_CLK1 20

DDR_B_CKE0 20 DDR_B_CKE1 20

DDR_B_CKE2 20 DDR_B_CKE3 20

DDR_B_CS#0 20 DDR_B_CS#1 20

DDR_B_ODT0 20

DDR_B_CA1_0 20

DDR_B_CA1_1 20 DDR_B_CA1_2 20 DDR_B_CA1_3 20

DDR_B_CA1_4 20 DDR_B_CA1_5 20 DDR_B_CA1_6 20

DDR_B_CA1_7 20 DDR_B_CA1_8 20 DDR_B_CA1_9 20

DDR_B_CA2_0 20 DDR_B_CA2_1 20 DDR_B_CA2_2 20

DDR_B_CA2_3 20 DDR_B_CA2_4 20 DDR_B_CA2_5 20

DDR_B_CA2_6 20 DDR_B_CA2_7 20

DDR_B_CA2_8 20 DDR_B_CA2_9 20

DDR_A_DQS#2 19 DDR_A_DQS2 19

DDR_A_DQS#3 19 DDR_A_DQS3 19

DDR_A_DQS#6 19 DDR_A_DQS6 19 DDR_A_DQS#7 19

DDR_A_DQS7 19 DDR_B_DQS#2 20 DDR_B_DQS2 20

DDR_B_DQS#3 20 DDR_B_DQS3 20 DDR_B_DQS#6 20

DDR_B_DQS6 20 DDR_B_DQS#7 20 DDR_B_DQS7 20

@

T36

PAD~D

+1.2V_DDR

@

UC1

1

DDR_VTT_CNTL

NC

2

A

3

GND

74AUP1G07GW_TSSOP5

A A

VCC

5

4

Y

1

@

CC15

0.1U_0402_10V7K

2

+3VS

1

@

R32 100K_0402_5%

2

SM_PG_CTRL 54

LPDDR3 COMPENSATION SIGNALS

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

CAD Note: Trace width=12~15 mil, Spacing=20 mils

1

RC164 200_0402_1%

RC166 80.6_0402_1%

1 2

RC165 162_0402_1%

1

2

Max trace length= 500 mil

DELL CONFIDENTIAL/PROPRIETARY

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P06-MCP(2/14)LPDDR3

LA-D891P

1

1.0

6 65Tuesday, December 20, 2016

of

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

SPI_MOSI= SPI_IO0 SPI_MISO= SPI_IO1 PCH EDS R0.7 p.235~236

change to 1k 5% check it is XDP@

RC67 1K_0402_5%@XDP@

PCH_SPI_DO_XDP13 PCH_SPI_DO2_XDP13

D D

TPM_PIRQ#8,31

+3VS

1 2

RC73 10K_0402_5%

1

RC83 10K_0402_5%

C C

PCH_SPI_CS0#

SPI_SO_VROM1

SPI_IO2_VROM1

PCH_SPI_CS1#

SPI_SO_VROM2

SPI_IO2_VROM2

2

128Mb Flash ROM

UH1

1

2 3

4

PVT-002 depop UH2

32Mb Flash ROM

UH2

@

1 2

3 4

W25Q32FVZPIQ WSON 8P SPI ROM

PVT-014.01 de-pop debug XDP related resistor pop by using Memo

SIO_RCIN#

IRQ_SERIRQ

CS#

HOLD#_RESET#

DO WP#

GND

CS# DO

WP# GND

Themal Pad

W25Q128FVPIQ_WSON8

VCC

HOLD#

CLK

DI

Thermal_pad

1 2

RC69 1K_0402_5%@XDP@

1 2

RC198

@

1

8

VCC

7

6

CLK

5

DI

9

PVT-013.01 add thermal pad for use

+3.3V_SPI

8

SPI_IO3_VROM2

7

SPI_CLK_VROM2

6

SPI_SI_VROM2

5

9

PCH_SPI_CS2#31

TC1

2

0_0201_5%

SIO_RCIN#30

IRQ_SERIRQ30

+3.3V_SPI

0.1U_0402_25V6

SPI_IO3_VROM1

SPI_CLK_VROM1

SPI_SI_VROM1

CC89

2

1

0.1U_0402_25V6

CL_CLK24 CL_DATA24 CL_RST#24

CC90

1

2

PCH_SPI_CLK PCH_SPI_SO

PCH_SPI_SI

PCH_SPI_IO2

PCH_SPI_IO3

PCH_SPI_CS0#

PCH_SPI_CS1#

SIO_RCIN#

IRQ_SERIRQ

PVT-001.01 Remove co-layout

AV2

AW3

AV3

AW2

AU4 AU3 AU2

AU1

M2 M3

M1

AW13

AY11

J4

V1

V2

G3

G2 G1

@

SKL-U_BGA1356

UCPU1E

SPI - FLASH

SPI0_CLK

SPI0_MISO SPI0_MOSI SPI0_IO2

SPI0_IO3 SPI0_CS0# SPI0_CS1#

SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO

GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2

GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

C LINK

CL_CLK

CL_DATA CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

SKL-U

LPC

SMBUS, SMLINK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

PCH_SPI_CLK_TPM31 PCH_SPI_SI_TPM31

PCH_SPI_SO_TPM31

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1

GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

5 OF 20

SPI_SI_VROM1

SPI_CLK_VROM1

SPI_SO_VROM1

SPI_IO2_VROM1

SPI_IO3_VROM1

SPI_SI_VROM2 SPI_SO_VROM2 SPI_IO2_VROM2

SPI_IO3_VROM2

SPI_CLK_VROM2

DDR_XDP_SMBCLK

R7

DDR_XDP_SMBDAT

R8

PCH_SMB_ALERT#

R10

R9 W2

GPP_C5

W1

SML1_SMBCLK

W3

SML1_SMBDAT

V3

GPP_B23

AM7

AY13 BA13

BB13 AY12 BA12

BA11

PCI_CLK_LPC0

AW9

PCI_CLK_LPC1

AY9

AW11

CLKRUN#

RP2

1 2

3 6

4 5

33_0804_8P4R_5%

1 8

2 7 3

4 5

33_0804_8P4R_5%

1

2 7

3 6 4

33_0804_8P4R_5%

1 2

RH93 33_0201_1%

RP3

RP4

8

7

6

PCH_SPI_SI

8

PCH_SPI_SO PCH_SPI_IO2 PCH_SPI_IO3

5

PCH_SPI_CLK

PCH_SPI_SO

PCH_SPI_IO2 PCH_SPI_IO3

DDR_XDP_SMBCLK 13

DDR_XDP_SMBDAT 13

SML1_SMBCLK 30

SML1_SMBDAT 30

LPC_AD0 30,43 LPC_AD1 30,43

LPC_AD2 30,43 LPC_AD3 30,43

LPC_FRAME# 30,43

1 2

RC71 22_0402_5%

1 2

RC70 22_0402_5%

CLKRUN# 30

PCH_SPI_SI

PCH_SPI_CLK

CLK_PCI_MEC

CLK_LPC_DEBUG

CLK_PCI_MEC 30 CLK_LPC_DEBUG 43

2

Reserve for RF

+3VS

DDR_XDP_SMBDAT

DDR_XDP_SMBCLK

CLKRUN#

SML1_SMBCLK

SML1_SMBDAT

1

@12P_0402_50V8J

CC78

12

@12P_0402_50V8J

CC21

1 2

RC55 1K_0402_5%

1 2

RC51 1K_0402_5%

PCH_SMB_ALERT#

12

RN12.2K_0402_5%

12

RN22.2K_0402_5%

12

RC828.2K_0402_5%

+3V_PRIM

change RC49 to 2.2k

1 2

RC49 2.2K_0402_5%

+3V_PRIM

TLS CONFIDENTIALITY

HIGH LOW(DEFAULT)

GPP_C5

ENABLE DISABLE

+3V_PRIM

1

RC58 10K_0402_5%@

2

+3V_PRIM

RH19 1K_0402_5%~D

1 2

B B

SPI debug conn

SPI_CLK_VROM1

33_0402_5%

RC169@

1 2

33P_0402_50V8J

CC91@

1 2

from CPU to SPI ROM

PCH_SPI_CS1#

PCH_SPI_SI

PCH_SPI_SO

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_IO2

PCH_SPI_IO3

+3.3V_SPI

A A

PCH SPI

PVT-003.01 0R turn to short pad

RC177

1 2

RC176

1

RC175

1

RC174

1

RC173

1 2

RC172

1 2

RC171

1 2

+3V_PRIM

RC170

1

0_0402_1%@

2

0_0402_1%@

2

0_0402_1%@

2

0_0402_1%@

2

0_0402_1%@

SPI_PCH_CS1#

SPI_PCH_SI

SPI_PCH_SO

SPI_PCH_CLK

SPI_PCH_CS0#

SPI_PCH_IO2

SPI_PCH_IO3

SPI

JSPI1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

GND_1

22

GND_2

ACES_50696-0200M-P01

CONN@

9/5 MOW Option 1: Implement a 1 kOhm pull-down resistor on the signal and de-populate the required 1 kOhm pull-up resistor(MOW WW5). In this case, customers must ensure that the SPI flash device on the platform has HOLD functionality disabled by default.

Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y platforms with ES and SKL S/H platforms with pre-ES1/ES1 samples(MOW WW9).

@

RH20 1K_0402_5%~D

1 2

@

RH21 1K_0402_5%~D

1

@

2

PCH_SPI_IO2

PCH_SPI_IO3

EC interface

HIGH LOW(DEFAULT)

GPP_B23

EXI BOOT STALL BYPASS

HIGH LOW(DEFAULT)

ESPI LPC

1 2

RC64 4.7K_0402_5%@

ENABLE DISABLE

+3V_PRIM

DELL CONFIDENTIAL/PROPRIETARY

Security Classification

TPM

JSPI

5

4

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

P07-MCP(3/14)SPI,SMB,LPC

LA-D891P

1

7 65Tuesday, December 20, 2016

1.0

of

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

+3VS

UCPU1F

+3VS

1 2

RC56

1

RH3 49.9K_0402_1%

D D

+3V_PRIM

+3VS_TS

C C

1 2

RH4 49.9K_0402_1%

1 2

RC190 49.9K_0402_1%

@

1

RC191 49.9K_0402_1%

1 2

RC180

1 2

RC181

1 2

RC149

HOST_SD_WP#

10K_0402_5%

UART2_TXD

2

UART2_RXD

UART2_RTS#

UART2_CTS#

2

TPM_PIRQ#7,31

10K_0201_5%

10K_0402_5%

RC196

1

EDP_CAB_DET#

WWAN_RST#

SIO_EXT_SCI#

2

0_0201_5%

UART2_RTS#

EDP_CAB_DET#22

WLAN_ON24

SIO_EXT_SCI#30

3.3V_TS_EN44

DEBUG_UART0_TX30

BT_ON/OFF#24

HOST_SD_WP#27

UART2_RXD43 UART2_TXD43

UART2_RTS#43

PVT-016.01 ALS_CAL_I2C0_SDA change to TS_RST#

TS_RST#22 ALS_CAL_I2C0_SCL22

SKYCAM_I2C_DATA34 SKYCAM_I2C_CLK34

UART2_CTS#43

I2C1_SDA_TS22 I2C1_SCK_TS22

UF_I2C_DATA33

UF_I2C_CLK33

EDP_CAB_DET#

NRB_BIT

SIO_EXT_SCI#

GPP_B22

WWAN_RST#

HOST_SD_WP#

UART2_RXD

UART2_TXD

UART2_RTS# UART2_CTS#

TS_RST# ALS_CAL_I2C0_SCL

SKYCAM_I2C_DATA SKYCAM_I2C_CLK

I2C1_SDA_TS I2C1_SCK_TS

UF_I2C_DATA UF_I2C_CLK

@

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

SKL-U_BGA1356

LPSS ISH

GPP F group

1.8V only

SKL-U

GPP_D9

GPP_D10

GPP_D11 GPP_D12

GPP_D5/ISH_I2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP F group

1.8V only

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_D15/ISH_UART0_RTS#

GPP_A18/ISH_GP0

GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3

GPP_A22/ISH_GP4

GPP_A12/BM_BUSY#/ISH_GP6

GPP_A23/ISH_GP5

6 OF 20

P2

P3

P4 P1

M4 N3

N1

N2

AD11

AD12

U1

U2 U3 U4

AC1 AC2 AC3

AB4

AY8

BA8 BB7 BA7

AY7 AW7

AP13

DDR_CHB_EN DDR_CHA_EN

TS_ID0

ISH_I2C0_SDA 31

ISH_I2C0_SCL 3 1

ALS_I2C1_SDA33

ALS_I2C1_SCL 33

@

T15

PAD~D

ACCEL_INT1# 31 ACCEL_INT2# 31

TS_ID0 22

PCH_AUD_PW R_EN 30

3.3V_CAM_EN 34

ALS_I2C1_ALERT#33

DDR_CHA_EN

DDR_CHB_EN

DDR_CHA_EN

DDR_CHB_EN

2

RC184

@

ACCEL_INT1#

ACCEL_INT2#

TS_ID0

TS_RST#

ALS_CAL_I2C0_SCL

1

0_0402_5%

RH30 100K_0402_5%~D

1 2

RH29 100K_0402_5%~D

1 2

RH31 SHORT PADS

RH28 SHORT PADS

RC182

RC183

RC192 100K_0201_5%

RC205

RC206

1 2

2

1

1 2

KICKSTD_SW_DET#30,42

10K_0201_5%

+3V_PRIM

+3VS

1

RC48 4.7K_0402_5%

1 2

RC50 4.7K_0402_5%

+3V_PRIM

RC63 4.7K_0402_5%@

NO REBOOT STRAP

HIGH

B B

LOW(DEFAULT) Weak IPD

+3V_PRIM

2

1 2

I2C1_SDA_TS

I2C1_SCK_TS

NRB_BIT

No REBOOT REBOOT ENABLE

I2C1_SDA_TS

I2C1_SCK_TS SKYCAM_I2C_DATA

SKYCAM_I2C_CLK UF_I2C_DATA UF_I2C_CLK

X76

33P_0402_50V8J

12

33P_0402_50V8J

1

12

2

CC6@EMC@

CC12@EMC@

33P_0402_50V8J

CC13@EMC@

1

2

CC11@EMC@

33P_0402_50V8J

1

2

CC7@EMC@

X7669231L12

CC8@EMC@

DRAM Option (R3)

Micron 8G/1866

MICRON_8G_R3@

UD1

MT52L256M32D1PF-107WT

SA00009XU1L

MICRON_8G_R3@

UD2

MT52L256M32D1PF-107W T

SA00009XU1L

MICRON_8G_R3@

UD3

MT52L256M32D1PF-107WT

SA00009XU1L

MICRON_8G_R3@

UD4

MT52L256M32D1PF-107WT

SA00009XU1L

Micron 16G/1866

X7669231L15

X7669231L18

MICRON_16G_R3@

UD1

MT52L512M32D2PF-107WT

SA00009U71L

Micron 32G/1866

MICRON_32G_R3@

UD1

MT52L1G32D4PG-107WT

SA00009XV1L

MT52L512M32D2PF-107W T

MT52L1G32D4PG-107W T

MICRON_16G_R3@

UD2

SA00009U71L

MICRON_32G_R3@

UD2

SA00009XV1L

MICRON_16G_R3@

UD3

MT52L512M32D2PF-107WT

SA00009U71L

MICRON_32G_R3@

UD3

MT52L1G32D4PG-107WT

SA00009XV1L

MICRON_16G_R3@

UD4

MT52L512M32D2PF-107WT

SA00009U71L

MICRON_32G_R3@

UD4

MT52L1G32D4PG-107WT

SA00009XV1L

Hynix 8G/1866

X7669231L13

X7669231L16

HYNIX_8G_R3@

UD1

H9CCNNN8GTMLAR-NUD FBGA

SA00008G61L

Hynix 16G/1866

HYNIX_16G_R3@

UD1

H9CCNNNBJTMLAR-NUD FBGA

SA00008FJ1L

H9CCNNN8GTMLAR-NUD FBGA

H9CCNNNBJTMLAR-NUD FBGA

HYNIX_8G_R3@

UD2

SA00008G61L

HYNIX_16G_R3@

UD2

SA00008FJ1L

HYNIX_8G_R3@

UD3

H9CCNNN8GTMLAR-NUD FBGA

SA00008G61L

HYNIX_16G_R3@

UD3

H9CCNNNBJTMLAR-NUD FBGA

SA00008FJ1L

HYNIX_8G_R3@

UD4

H9CCNNN8GTMLAR-NUD FBGA

SA00008G61L

HYNIX_16G_R3@

UD4

H9CCNNNBJTMLAR-NUD FBGA

SA00008FJ1L

Hynix 32G/1866

12

RC65

@

8.2K_0402_5%

GPP_B22

X7669231L19

X76_8G_R3@

X768G3 X76

X7669231L11

BOOT BIOS Destination(Bit

6) HIGH

LOW(DEFAULT)

LPC SPI

A A

X76_16G_R3@

X7616G3 X76

X7669231L14

X76_32G_R3@

X7632G3 X76

X7669231L17

HYNIX_32G_R3@

UD1

H9CCNNNCLTMLAR-NUD FBGA

SA00008YT1L

Samsung 8G/1866

SAMSUNG_8G_R3@

UD1

K4E8E324EB-EGCF FBGA178P

SA00009XY1L

Samsung 16G/1866

SAMSUNG_16G_R3@

UD1

K4E6E304EB-EGCF FBGA1 7

SA00008QV3L

Samsung 32G/1866

SAMSUNG_32G_R3@

UD1

4EBE304EB-EGCF FBGA17 8

SA00008X11L

HYNIX_32G_R3@

UD2

H9CCNNNCLTMLAR-NUD FBGA

SA00008YT1L

SAMSUNG_8G_R3@

UD2

K4E8E324EB-EGCF FBGA178P

SA00009XY1L

SAMSUNG_16G_R3@

UD2

K4E6E304EB-EGCF FBGA1 7

SA00008QV3L

SAMSUNG_32G_R3@

UD2

4EBE304EB-EGCF FBGA17 8

SA00008X11L

HYNIX_32G_R3@

UD3

H9CCNNNCLTMLAR-NUD FBGA

SA00008YT1L

SAMSUNG_8G_R3@

UD3

K4E8E324EB-EGCF FBGA178P

SA00009XY1L

SAMSUNG_16G_R3@

UD3

K4E6E304EB-EGCF FBGA1 7

SA00008QV3L

SAMSUNG_32G_R3@

UD3

4EBE304EB-EGCF FBGA17 8

SA00008X11L

HYNIX_32G_R3@

UD4

H9CCNNNCLTMLAR-NUD FBGA

SA00008YT1L

SAMSUNG_8G_R3@

UD4

K4E8E324EB-EGCF FBGA178P

SA00009XY1L

SAMSUNG_16G_R3@

UD4

K4E6E304EB-EGCF FBGA1 7

SA00008QV3L

SAMSUNG_32G_R3@

UD4

4EBE304EB-EGCF FBGA17 8

SA00008X11L

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet of

Compal Electronics, Inc.

P08-MCP(4/14)GSPI,I2C,UART,ISH

LA-D891P

1

8 65Tuesday, December 20, 2016

of

1.0

Security Classification

DELL CONFIDENTIAL/PROPRIETARY

Security Classification

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

UCPU1H

@

PCIE/USB3/SATA

H13

D D

PCIE_PRX_WLANTX_N524

WLAN PCIe Gen2 x 1

WLAN - WiGig PCIe Gen2 x 1

PVT-011.01 rename P7 SATA -> PCIe

C C

rename P8 PCIe -> SATA

PCIe SSD

SATA SSD

Cardreader PCIe Gen2 x 1

+3VS

1

RC72 10K_0402_5%

M.2 2242 WWAN 2nd SSD SATA/PCIe 2 Lane ony 4/14

B B

PCIE_PRX_WLANTX_P524 PCIE_PTX_WLANRX_N524

PCIE_PTX_WLANRX_P524

PCIE_PRX_WLANTX_N624 PCIE_PRX_WLANTX_P624 PCIE_PTX_WLANRX_N624

PCIE_PTX_WLANRX_P624

PCIE_PRX_SSDTX_N723

PCIE_PRX_SSDTX_P723 PCIE_PTX_SSDRX_N723 PCIE_PTX_SSDRX_P723

SATA_PRX_SSDTX_N823

SATA_PRX_SSDTX_P823

SATA_PTX_SSDRX_N823 SATA_PTX_SSDRX_P823

PCIE_PRX_CARDTX_N927

PCIE_PRX_CARDTX_P927

PCIE_PTX_CARDRX_N927 PCIE_PTX_CARDRX_P927

1

RC113 100_0402_1%

2

PCIE_PRX_WWANTX_N1125

PCIE_PRX_WWANTX_P1125

PCIE_PTX_WWANRX_N1125 PCIE_PTX_WWANRX_P1125

PCIE_PRX_WWANTX_N1225

PCIE_PRX_WWANTX_P1225

PCIE_PTX_WWANRX_N1225 PCIE_PTX_WWANRX_P1225

2

CPU_XDP_PRDY#13 CPU_XDP_PREQ#13

PCIE_RCOMPN PCIE_RCOMPP

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL-U_BGA1356

SKL-U

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN

USB3_2_RXP/SSIC_1_RXP

USB3_2_TXN/SSIC_1_TXN USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP

USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0#

GPP_E10/USB2_OC1#

GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0

GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0

GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

USB3_1_RXN USB3_1_RXP

USB3_1_TXN

USB3_1_TXP

USB3_4_RXN USB3_4_RXP

USB3_4_TXN

USB3_4_TXP

USB2N_1

USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4

USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7

USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10

USB2P_10

USB2_COMP

USB2_ID

8 OF 20

H8 G8

C13 D13

J6

H6 B13 A13

J10 H10 B15

A15

E10 F10

C15 D15

AB9

AB10

AD6 AD7

AH3 AJ3

AD9

AD10

AJ1 AJ2

AF6 AF7

AH1

AH2

AF8 AF9

AG1 AG2

AH7

AH8

AB6 AG3

AG4

A9 C9

D9 B9

J1

J2 J3

H2

H3 G4

H1

USB3RN1 37

USB3RP1 37 USB3TN1 37

USB3TP1 37

USB3RN2 25 USB3RP2 25

USB3TN2 25

USB3TP2 25

USB3RN3 39

USB3RP3 39 USB3TN3 39

USB3TP3 39

USB3RN4 37 USB3RP4 37 USB3TN4 37

USB3TP4 37

USBCOMP

OTG_ID

VBUSSENSE

USB_OC0# USB_OC1# USB_OC2#

USB_OC3#

SIO_EXT_WAKE#

GPP_E1

SATA_LED#

RC137 113_0402_1%

RC62 0_0402_5%~D

RC61 1K_0402_5%

RC41

USB20_N1 35

USB20_P1 35

USB20_N2 43

USB20_P2 43

USB20_N3 36 USB20_P3 36

USB20_N4 25 USB20_P4 25

USB20_N5 43 USB20_P5 43

USB20_N7 24 USB20_P7 24

USB20_N9 39 USB20_P9 39

USB20_N10 43 USB20_P10 43

1

USB_OC2# 39

1

SATA_LED# 42

2

0_0201_5%

Type-C PortA

WWAN

USB3.0 Type-A

Type-C PortB

Type-C PortA

Dock

Type-C PortB

NGFF (WWAN)

IR Camera

NGFF (WLAN)

USB Type-A

USH

SSD_DEVSLP 23

SIO_EXT_WAKE#30

WWAN_DEVSLP25

m2280_PCIE_SATA# 23

m3042_PCIE#_SATA 41

PD1_OTG_ID 35

PD1_VBUS_SENSE35

SIO_EXT_WAKE#

USB_OC0#

USB_OC1#

USB_OC2#

USB_OC3#

m2280_PCIE_SATA#

SATA_LED#

Type-C PortA

2

RC59 10K_0402_5%

1

RC13 10K_0402_5%

1

RC11 10K_0402_5%

1

RC14 10K_0402_5%

1

RC12 10K_0402_5%

1

RC195

1

RC201

1

2

10K_0201_5%

2

10K_0201_5%

+3V_PRIM

GPP_E1

OTG_ID

VBUSSENSE

@

RC204

RH90

RH91

2

1 2

1

10K_0402_5%

2

10K_0201_5%

100K_0201_5%

A A

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

P09-MCP(5/14)PCIE,USB,SATA

LA-D891P

1

9 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

WiGig--->

D D

WLAN--->

WWAN--->

SSD--->

Card Reader --->

+3VALW

C C

+1.0V_VCCST

+3V_PRIM

B B

1 2

RC90 1K_0402_5%

1 2

RC143 10K_0402_5%

1 2

RC84 8.2K_0402_5%

+3VS

1

RC97@ 8.2K_0402_5%

1 2

RC25 1K_0402_5%

1 2

RC162 10K_0402_5%@

1 2

RC189 10K_0402_5%

H_VCCST_PWRGD_P13,32

100P_0402_50V8J~D

CA4

1

2

CLK0_PCIE_WiGig#24

CLK0_PCIE_WiGig24

CLKREQ_PCIE#024

CLK1_PCIE_WLAN#24 CLK1_PCIE_WLAN24

CLKREQ_PCIE#124

CLK2_PCIE_WWAN#25

CLK2_PCIE_WWAN25 CLKREQ_PCIE#225

CLK_PCIE_SSD#23 CLK_PCIE_SSD23

CLKREQ_PCIE#323

CLK_PCIE_MMI#27 CLK_PCIE_MMI27

CLKREQ_PCIE#527

PCH_PCIE_WAKE#

LAN_WAKE#

BATLOW#

ME_RESET#

H_VCCST_PWRGD_P

SUSWARN #

PCH_RSMRST#

@

T7

PAD~D

H_VCCST_PWRGD_PH_CPUPWRGD

100P_0402_50V8J~D

CA3

1

2

+3VS

3/31 check to here

H_CPUPWRGD_R

1 2

RC145 10K_0 402_5%

1

RC157 10K_0 402_5%

1 2

RC153 10K_0 402_5%

1 2

RC159 10K_0 402_5%

@

1 2

RC168 10K_0 402_5%

1 2

RC161 10K_0 402_5%

1 2

RC39 1K_0402_5%@

RC26 60.4_0402_1%

1 2

2

PLT_RST#22,23,24,25,27,30,31,34,43

PCH_RSMRST#13,30

SYS_PWROK13,30

PCH_PWROK58

PCH_DPWROK30

SUSWARN#30

SUSACK#30

PCH_PCIE_WAKE#30

LAN_WAKE#30

3.3V_IRCAM_EN#43

PCH_PLTRST#

SYS_RESET#

PCH_RSMRST#

H_CPUPWRGD

VCCST_PWRGDH_VCCST_PWRGD_P

PCH_DPWROK

SUSWARN#

PCH_PCIE_WAKE#

LAN_WAKE#

ESD Request:place near CPU side

RC215

POP DE-POP

PCH_DPWROK

A A

0.01U_0402_16V7K

1

2

NO Support Deep sleep Support Deep sleep

1

RC78 0_ 0402_5%@

100K_0402_5%~D

12

RC80

CC16

PCH_RSMRST#

2

XDP_DBRESET#13

if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)

5

4

UCPU1J

@

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKL-U_BGA1356

RC152

100K_0402_5%

4

CLOCK SIGNALS

RC150 0_0402_5%@

4

12

UCPU1K

@

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKL-U_BGA1356

XDP_DBRESET#

RC96@ 8.2K_0402_5%

O

SYSTEM POWER MANAGEMENT

ME_RESET#

12

SKL_ULT

1

2

+3VS

5

1

P

B

2

A

G

UC4

TC7SH08FU_SSOP5

3

SKL-U

1 2

RC34 0_0402_5%

+3VS

5

1

P

B

2

O

A

G

74AHC1G09GW _TSSOP5

3

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

10 OF 20

PCH_PLTRST#

2

RC154 10K_0402_5%

1

GPP_B11/EXT_PWR_GATE#

4

SYS_RESET#_R

UC3@

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CLK_ITPXDP_N_R

F43

CLK_ITPXDP_P_R

E43

BA17

E37 E35

E42

AM18 AM20

AN18 AM16

+RTCVCC

@

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B2/VRALERT#

11 OF 20

1

RC36 1K_0402_5%

Issued Date

3

SUSCLK

XTAL24_IN XTAL24_OUT

XCLK_BIASREF

PCH_RTCX1 PCH_RTCX2

SRTCRST#

RTC_RST#

RC31 2.7K_0402_1%

1U_0402_6.3V6K

1 2

RC89 20K_0201_5%

1 2

RC85

1U_0402_6.3V6K

AC_PRESENT

AT11

AP15 BA16 AY16

AN15 AW15 BB17

AN16

BA15 AY15

AU13

AU11 AP16

AM10 AM11

2

1 2

RC74 1K_0402_5%@

RC33 0_0402_5%

1 2

RC32 0_0402_5%

1 2

SUSCLK 23,24,25

1 2

RTC_RST# 30

12

@

1

CLRP1

CC25

20K_0201_5%

CC22

1 2

RC91 10 K_0402_5%

SIO_SLP_S0# SIO_SLP_S3# SIO_SLP_S4#

SIO_SLP_S5#

AC_PRESENT

BATLOW#

PME#

INTRUDER#

VRALERT#

+3VS

12

RC38

10K_0402_5%

@

SYS_RESET#

2015/10/22 2013/10/28

10K_0201_5%

2

1

2

SIO_SLP_SUS# 30,32,44,55,56,57

SIO_SLP_WLAN# 30

SIO_SLP_A# 30

SRTCRST#

PDG_An RC delay circuit with a time delay in the range of 18–25 ms should be provided. The circuit should be connected to VCCRTC.

+3VALW

SIO_SLP_S0# 31,45,57

SIO_SLP_S3# 30,32

SIO_SLP_S4# 30,32

@

T26

PAD~D

SIO_PWRBTN# 10,13,30

AC_PRESENT 30

@

T38

PAD~D

MPHYP_PWR_EN 45

Compal Secret Data

CLK_ITPXDP_N 13 CLK_ITPXDP_P 13

+1.0V_CLK

CMOS1

1

SHORT PADS~D

@

Deciphered Date

2

CMOS1 must take care short & touch risk on layout placement

INTRUDER#

VRALERT#

SLP_S0# for support connect stand by mode

8/21 CRB1.0 change to 0603 1/10W

2

XTAL24_IN

XTAL24_OUT

PCH_RTCX1 PCH_RTCX2

RTC_RST#

RC88

1

1 2

RC60 10K_0402_5%

2

1M_0402_5%

1

CC2

1 2

1M_0402_1%

2

RC35

1

RC86 10M_0402_5%

1 2

RC87 0_0402_5%

+RTCVCC

+3V_PRIM

PCH_RTCX2_R

APS CONN

+3V_PRIM

+3VALW

SIO_PWRBTN#10,13,30

3

4

YC1 24MHZ_12PF_7M24090001

1

2

12

SIO_SLP_S3#

SIO_SLP_S5#

SIO_SLP_S4#

SIO_SLP_A#

RTC_RST#

SYS_RESET#

SIO_SLP_S0#

15P_0402_50V8J

CC1

1 2

15P_0402_50V8J

CC23

1 2

6.8P_0402_50V8J

YC2 9PF 20PPM 9H03280012

ESR MAX=50k ohm

CC24

1 2

6.8P_0402_50V8J

20 19 18

17

16

15 14 13

12 11 10

9 8

7 6

5 4 3

2 1

ACES_50506-01841-P01

JAPS1

GND GND 18

17

16

15 14 13

12 11 10

9 8

7 6

5 4 3

2 1

CONN@

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P10-MCP(6/14)CLK,PM,RTC

LA-D891P

1

10 65Tuesday, December 20, 2016

1.0

of

Vinaﬁx.com

5

smd.db-x7.ru

+1.0V_VCCST

1 2

RC7 49 .9_0402_1%@

1 2

RC20 1K_0402_5%

+1.0V_VCCSTG

1 2

RC28 1K_0402_5%

D D

+3VS

1 2

RC9 10K_0402_5%

1

RC163 10K_0402_5%@

+3V_PRIM

1 2

RC8 10K_0402_5%

1 2

RC68 10K_0402_5%

H_CATERR#

H_THERMTRIP#

H_PROCHOT#

TOUCH_SCREEN_PD#

2

EC_SLP_S0IX#

SIO_EXT_SMI#

NFC_DET#

H_PECI30

H_PROCHOT#3 0,50,51,54,58

H_PROCHOT#

4

1 2

RC27 499_0402_1%

XDP_OBS0_R13 XDP_OBS1_R13

@

T9

PAD~D

@

T10

PAD~D

SIO_EXT_SMI#30

TOUCH_SCREEN_PD#22

EC_SLP_S0IX#30

EDRAM_OPIO_RCOMP

12

1

RC160

2

49.9_0402_1%

12

RC167

49.9_0402_1%

H_CATERR#

H_PROCHOT#_R

H_THERMTRIP#

XDP_OBS2_R XDP_OBS3_R

SIO_EXT_SMI#

TOUCH_SCREEN_PD#

NFC_DET#

CPU_POPIRCOMP PCH_POPIRCOMP

EOPIO_RCOMP

12

RC123

RC122

49.9_0402_1%

@

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKL-U_BGA1356

UCPU1D

CPU MISC

SKL-U

3

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_TRST#

JTAGX

4 OF 20

TCLK_XDP

B61

TDI_XDP

D60

TDO_XDP

A61

TMS_XDP

C60

TRST#_XDP

B59

PCH_JTAG_TCLK

B56

TDI_XDP

D59

TDO_XDP

A56

TMS_XDP

C59

TRST#_XDP

C61

TCLK_XDP

A59

TCLK_XDP 13 TDI_XDP 13 TDO_XDP 13

TMS_XDP 13 TRST#_XDP 13

PCH_JTAG_TCLK 13

1 2

RC3 1K_0402_5%@

2

+1.0V_VCCSTG

TDI_XDP

TDO_XDP

TMS_XDP

PCH_JTAG_TCLK

@

1

RC2 51_0402_5%

RC19 100_0402_5%

RC18 51_0402_5%

2

RC17 51_0402_5%

12

1

+1.0V_VCCSTG

+5VALW

Strap pin

1M_0201_5%

C C

ME_FWP#30

2

1

SKL-U

TPM@

@

SDIO/SDXC

CAM_CBL_DET#

GPP_G0/SD_CMD

GPP_G1/SD_DATA0 GPP_G2/SD_DATA1

GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD#

GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

7 OF 20

+3V_PRIM

RH11

1

RH14

2

AB11

AB13 AB12

W12

CONTACTLESS_DET#

W11 W10

W8

EDP_ID0

W7

BA9

BB9

SD_RCOMP

AB7

AF13

RC140 200_04 02_1%

UCPU1G

@

AUDIO

SPKR28

HDA_SYNC_R HDA_BLK_R

HDA_SDOUT_R

TPM_DET

SPKR

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

SKL-U_BGA1356

TPM_DET

100K_0402_5 %

1 2

HDA_SYNC28 HDA_BLK28 HDA_SDOUT28

HDA_SDI028

HDA_BLK

1

CC17

B B

@

22P_0402_50V8J

Close to RC77

RF@

2P_0201_25V8B

12

CC93

2

12

HDA_SDOUT

HDA_SDI0

RF@

2P_0201_25V8B

CC94

HDA_SDOUT

HDA_SDI0

RC75 33_0402_5%

1

RC77 33_0402_5%

1 2

RC76 33_0402_5%

2

From EC, for enable ME code programing

5

CAM_CBL_DET#43

SSD_PWR _EN 44 CONTACTLESS_DET# 43

WW AN_OFF# 25

SPK_ID 29 EDP_ID0 22

SD_PWR_ EN 44

NGFF_WW AN_PW REN 44

1 2

3

Q25B DMN2400UV-7_SOT-563-6

4

SPK_DET# added on 4/15

+DVDDIO

DMN2400UV-7_SOT-563-6

CAM_CBL_DET#

WWAN_OFF#

CONTACTLESS_DET#

EDP_ID0

2

RC188

1

2

6 1

Q25A

RC53 100K_0402_5%~D

RC202 10K_0402_5%

RC200 100K_0402_5%~D

RC193

HDA_SDO

ME debug mode , this signal has a weak internal PD L=>security measures defined in the Flash Descriptor will be in effect (default) H=>Flash Descriptor Security will be overridden

1

1 2

1

1 2

RC92

1

1K_0402_5%

Low = Disabled

*

High = Enabled

2

+3V_PRIM

100K_0201_5%

+3VS

HDA_SDOUT

2

TPM BOM Optional

+3V_PRIM +3V_PRIM

A A

1

RC158 8.2K_0402_5%

@

TOP SWAP STRAP

HIGH LOW(DEFAULT)

2

ENABLE DISABLE

SPKR

5

Flash Descriptor Security override

HIGH LOW(DEFAULT)

1 2

RC81 4.7K_0402_5%

@

HDA_SDOUT

DISABLE ENABLE

4

TPM_DET

TPM

1 = W/TPM

0 = W/O TPM

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

P11-MCP(7/14)MISC,JTAG,HDA,SDIO

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

LA-D891P

1

1.0

11 65Tuesday, December 20, 2016

of

Vinaﬁx.com

5

smd.db-x7.ru

D D

4

CFG[0..15]13

3

CFG0 CFG1

CFG2 CFG3 CFG4

CFG5 CFG6 CFG7

CFG8 CFG9 CFG10

CFG11 CFG12 CFG13

CFG14 CFG15

2

1

UCPU1S

@

1

RC29 10K_0402_1%

@

Stall reset sequence

HIGH(DEFAULT) LOW

C C

1 2

RC40 10K_0402_1%

eDP enable

HIGH(DEFAULT) LOW

B B

2

CFG0

No stall(Normal Operation) stall

CFG4

Disabled Enabled

RC37 10K_0402_1%

@

RC30 10K_0402_1%

@

+1.0VA_XDP

1

2

CFG1613 CFG1713

CFG1813

CFG1913

CFG_RCOMP

@

PAD~D

1

ITP_PMODE

1

2

RC112 49.9_0402_1%

2

RC10 1.5K_0402_5%

ITP_PMODE13

T31

T28

CFG0

CFG1

CFG2

CFG3 CFG4

CFG5

CFG6 CFG7 CFG8

CFG9 CFG10 CFG11

CFG12 CFG13 CFG14

CFG15

E68 B67

D65 D67

E70

C68

D68 C67

F71

G69

F70

G68 H70 G71

H69 G70

E63 F63

E66

F66

E60

AY2

AY1

K46 K45

AL25

AL27

C71

B70

F60

A52

BA70 BA68

J71 J68

F65

G65

F61 E61

E8

D1 D3

CFG[0] CFG[1]

CFG[2] CFG[3] CFG[4] CFG[5]

CFG[6] CFG[7]

CFG[8] CFG[9]

CFG[10]

CFG[11] CFG[12] CFG[13]

CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18]

CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2

RSVD_AY1

RSVD_D1 RSVD_D3

RSVD_K46 RSVD_K45

RSVD_AL25

RSVD_AL27

RSVD_C71 RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70 RSVD_TP_BA68

RSVD_J71 RSVD_J68

VSS_F65 VSS_G65

RSVD_F61 RSVD_E61

RESERVED SIGNALS-1

SKL-U

RSVD_TP_BB68

RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

TP5 TP6

RSVD_D5

RSVD_D4 RSVD_B2 RSVD_C2

RSVD_B3

RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4

RSVD_C4

TP4

RSVD_A69

RSVD_B69

RSVD_AY3

RSVD_D71 RSVD_C70

RSVD_C54

RSVD_D54

TP1 TP2

VSS_AY71

ZVM#

RSVD_TP_AW71 RSVD_TP_AW70

MSM#

PROC_SELECT#

BB68

BB69

AK13 AK12

BB2 BA3

AU5 AT5

D5

D4 B2 C2

B3

A3

AW1

E1 E2

BA4 BB4

A4

C4

BB5

A69

B69

AY3

D71 C70

C54

D54

AY4 BB3

AY71

AR56

AW71 AW70

AP56

C64

RC24 100K_0402_5%

PAD~D

1 2

@

T27

@

T30

@

T33

@

T34

@

T22

@

T37

@

T39

@

T40

@

T41

ZVM# for SKYLAKE-U 2+3e

Pebble Creek use 2+2e

@

T23

PAD~D

@

T29

PAD~D

MSM# for SKYLAKE-U 2+3e

+1.0V_VCCST

AW69 AW68

AU56

AW48

U12

U11 H11

C7

UCPU1T

@

RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48

RSVD_C7 RSVD_U12

RSVD_U11 RSVD_H11

SKL-U_BGA1356

SPARE

SKL-U

RSVD_F6

RSVD_E3 RSVD_C11 RSVD_B11

RSVD_A11 RSVD_D12 RSVD_C12

RSVD_F52

20 OF 20

F6

E3 C11 B11

A11 D12 C12

F52

SKL-U_BGA1356

19 OF 20

A A

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

P12-MCP(8/14)CFG,RSVD

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

LA-D891P

1

1.0

12 65Tuesday, December 20, 2016

of

Vinaﬁx.com

5

smd.db-x7.ru

PVT-003.02

0.01R turn to short pad

+1.0VA

D D

RC130

1 2

@

0_0603_5%

Place near JXDP1

CFG[0..15]12

C C

CFG0

CFG1 CFG2 CFG3

CFG4 CFG5 CFG6

CFG7 CFG8 CFG9

CFG10 CFG11 CFG12

CFG13 CFG14 CFG15

0.1U_0402_10V7K

1

2

XDP_OBS0_R11 XDP_OBS1_R11

+1.0VA_XDP

@

1

CC33

2

+1.0VS_VCCIO

+1.0V_VCCST

0.1U_0402_10V7K

@

CC37

+1.0VA_XDP

CFG3

RC141 1K_04 02_5%@XDP@

RC142 0_0402_5%@

PVT-014.04 de-pop debug XDP related resistor pop by using Memo

RC138 0_0402_5%

@XDP@

RC136 0_0402_5%

@XDP@

1 2

RC119 150_0402_5 %@

1

RC109 150_0402_5 %@

1

RC111 10K_0402_5%@

1

RC151 51_0402_5%

@

1

2

CC26@ 0 .1U_0402_25 V6

Place near JXDP1.47

PVT-014.02 de-pop debug XDP related resistor pop by using Memo

2

1

2

RC5 need to close to JCPU1

1

H_VCCST_PW RGD_P10,32

PCH_RSMRST#10,30

FIVR_EN

PCH_SPI_DO_XDP7

SYS_PWROK10,30

B B

PCH_SPI_DO_XDP

PCH_SPI_DO2_XDP7

CFG0

XDP_PRSENT#

RC132 1K_04 02_5%@

1

RC131@XDP@

RC121 0_0402_5%

1

RC144

RC100 0_0402_5%

1

RC99 0_0402_5%

1

RC187 33_0201_1%@XDP@

1

2

@XDP@

@

2

1K_0402_5%

2

1K_0402_5%

2

+3V_PRIM

5

U44

@XDP@

P

NC

Y

A

G

NL17SZ14DFT2G_SOT353-5

3

4

FIVR_EN_R

FIVR_EN

2

FIVR_EN

2

CPU_XDP_PREQ#

2

RESET_OUT#_R

XDP_PRSNT_PIN1

XDP_OBS0 XDP_OBS1

H_VCCST_PWRGD_XDP

FIVR_EN_R

RESET_OUT#_R

XDP_PRSENT#

XDP_PRSENT 45

+3V_PRIM

1

RC107

2

1.5K_0402_5%

PCH_SPI_DO_XDP XDP_DBRESET#

Place near JXDP1.48

CPU XDP

+1.0VA_XDP

XDP_PRSNT_PIN1

CPU_XDP_PREQ#9 CPU_XDP_PRDY#9

SIO_PWRBTN#10,30

DDR_XDP_SMBDAT7

DDR_XDP_SMBCLK7

PCH_JTAG_TCLK11

TCLK_XDP11

CPU_XDP_PREQ#

CFG0

CFG1

CFG2

CFG3

XDP_OBS0 XDP_OBS1

CFG4 CFG5

CFG6

CFG7

H_VCCST_PW RGD_XDP

SIO_PWRBTN#

FIVR_EN_R

RESET_OUT#_R

TCLK_XDP

3

+3VS

1K_0402_5%

1

RC120

2

0.1U_0402_25V6

@XDP@

12

CC31

PVT-014.03 de-pop debug XDP related resistor pop by using Memo

JXDP1

1

3

5

7

9

111112

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

595960

61

GND62GND

JXT_FP270H-061G1AM

CONN@

2

4 6

8

10

14 16 18

20

22

24 26 28

30 32 34

36

38

40 42 44

46 48 50

52 54 56

58

Place near JXDP1.41

2

4 6

8

10 12

14 16 18

20

22

24 26 28

30 32 34

36

38

40 42 44

46 48 50

52 54 56

58 60

63

SIO_PWRBTN#

+1.0VA_XDP

CFG17 CFG16

CFG8 CFG9

CFG10 CFG11

CFG19

CFG18

CFG12

CFG13

CFG14 CFG15

XDP_DBRESET#

TDO_XDP

TRST#_XDP

TDI_XDP

TMS_XDP

XDP_PRSENT#

+3VALW

1.5K_0402_5%

1

RC127

2

0.1U_0402_25V6

@

CC36

12

CFG17 12 CFG16 12

CFG8 12

CFG9 12

CFG10 12 CFG11 12

CFG19 12

CFG18 12

CFG12 12

CFG13 12

CFG14 12

CFG15 12

CLK_ITPXDP_P 10 CLK_ITPXDP_N 10

ITP_PMODE 12

XDP_DBRESET# 10

TDO_XDP 11

TRST#_XDP 11

TDI_XDP 11

TMS_XDP 11

2

TMS_XDP

TDI_XDP

TDO_XDP

TRST#_XDP

TCLK_XDP

51_0402_5%

100_0402_5%

51_0402_5%

1

+1.0V_VCCSTG

2

RC98

1

RC101

12

RC110

1

RC106

12

@

RC102

12

A A

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

P13-MCP(9/14)XDP

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

LA-D891P

1

13 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

PSC(Primary side cap) : Place as close to the package as possible BSC(Backside cap) : Place on secondary side, underneath the package

Component placement order: Package edge > 0402 caps > 0805 caps > Bulk caps >Power source

+VCC_CORE: 0.55~1.5V, 29A

D D

+VCC_EDRAM: 1V, 2.5A +V1.8S_EDRAM: 1.8V, 50mA +VCC_EOPIO: 0.8~1V, 2A

@

T8

PAD~D

@

T18

PAD~D

C C

+VCC_CORE +VCC_CORE

SKL-U

CPU POWER 1 OF 4

1.5V@29A

1V@2.5A

1V@0.05A

VCC_G32 VCC_G33

VCC_G35 VCC_G37 VCC_G38

VCC_G40 VCC_G42

VCC_J30

VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37

VCC_K38 VCC_K40

VCC_K42 VCC_K43

VCC_SENSE

VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

12 OF 20

G32 G33

G35 G37 G38

G40 G42 J30

J33 J37

J40 K33 K35 K37

K38 K40

K42 K43

E32

VCCSENSE

E33

VSSSENSE

H_CPU_SVIDALRT#

B63

VIDSCLK_R

A63

VIDSOUT_R

D64

G20

+1.0V_VCCSTG_R

+VCC_CORE_G0

+VCC_CORE_G1

@

A30

VCC_A30

A34

VCC_A34

A39

VCC_A39

A44

VCC_A44

AK33

VCC_AK33

AK35

VCC_AK35

AK37

VCC_AK37

AK38

VCC_AK38

AK40

VCC_AK40

AL33

VCC_AL33

AL37

VCC_AL37

AL40

VCC_AL40

AM32

VCC_AM32

AM33

VCC_AM33

AM35

VCC_AM35

AM37

VCC_AM37

AM38

VCC_AM38

G30

VCC_G30

K32

RSVD_K32

AK32

RSVD_AK32

AB62

VCCOPC_AB62

P62

VCCOPC_P62

V62

VCCOPC_V62

H63

VCC_OPC_1P8_H63

G61

VCC_OPC_1P8_G61

AC63

VCCOPC_SENSE

AE63

VSSOPC_SENSE

AE62

VCCEOPIO

AG62

VCCEOPIO

AL63

VCCEOPIO_SENSE

AJ62

VSSEOPIO_SENSE

SKL-U_BGA1356

UCPU1L

1V@2A

RC1

+VCC_CORE

1

2

12

1 2

Close CPU

RC5

100_0402_1%

RC6

100_0402_1%

0_0402_5%

VCCSENSE 58 VSSSENSE 58

+1.0V_VCCSTG

VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e (w/ on package cache)

SVID ALERT

+1.0V_VCCST

56_0402_1%

1

RC94

CAD Note: Place the PU resistors close to CPU RC204 close to CPU 300 - 1500mils

2

VIDALERT_N58

SVID DATA

B B

VIDSOUT58

SVID CLK

+1.0V_VCCST

100_0402_1%

12

+1.0V_VCCST

100_0402_1%

12

RC93

CAD Note: Place the PU resistors close to CPU RC208close to CPU 300 - 1500mils

@

RC95

CAD Note: Place the PU resistors close to CPU

H_CPU_SVIDALRT#

12

RC22220_0402_5%

12

RC230_0402_5%~D

VIDSOUT_R

RC208close to CPU 300 - 1500mils

VIDSCLK58

12

RC210_0402_5%~D

VIDSCLK_R

CDI#61280

10.2.7 SVID Topology

A A

Table 10-9. SVID Bus Routing Guidelines need double pull high

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

P14-MCP(10/14)PWR-VCC CORE

Size Document Number Rev

Date: Sheet

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

LA-D891P

1

1.0

14 65Tuesday, December 20, 2016

of

Security Classification

DELL CONFIDENTIAL/PROPRIETARY

Security Classification

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

+VCCGT: 0.55~1.5V, 54A +VCCGTX : 0.55~1.5V, 7A

+VCC_GT +VCC_GT

D D

C C

+VCC_GT

1

Close CPU

VCC_GT_SENSE58

VSS_GT_SENSE58

B B

RC44

100_0402_1%

2

VCC_GT_SENSE

VSS_GT_SENSE

1

A48

A53 A58 A62

A66 AA63 AA64

AA66 AA67 AA69

AA70 AA71 AC64

AC65 AC66 AC67

AC68 AC69 AC70

AC71

J43

J45

J46

J48

J50

J52

J53

J55

J56

J58

J60

K48

K50

K52

K53

K55

K56

K58

K60

L62

L63

L64

L65

L66

L67

L68

L69

L70

L71

M62

N63

N64 N66 N67

N69

J70

J69

UCPU1M

@

CPU POWER 2 OF 4

VCCGT

VCCGT VCCGT VCCGT

VCCGT VCCGT

VCCGT VCCGT VCCGT VCCGT

VCCGT VCCGT

VCCGT VCCGT VCCGT

VCCGT

VCCGT_SENSE

VSSGT_SENSE

SKL-U_BGA1356

SKL-U

1.5V@54A

1.5V@7A

VCCGTX_SENSE

VSSGTX_SENSE

VCCGT

VCCGT VCCGT VCCGT

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45

VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50

VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55

VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60

VCCGTX_AK70 VCCGTX_AL43 VCCGTX_AL46

VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56

VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50

VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56

VCCGTX_AM58 VCCGTX_AU58

VCCGTX_AU63

VCCGTX_BB57

VCCGTX_BB66

13 OF 20

N70

N71 R63 R64

R65 R66 R67

R68 R69 R70

R71 T62 U65

U68 U71 W63

W64 W65 W66

W67 W68 W69

W70 W71 Y62

AK42 AK43 AK45

AK46 AK48 AK50

AK52 AK53 AK55

AK56 AK58 AK60

AK70 AL43 AL46

AL50 AL53 AL56

AL60 AM48 AM50

AM52 AM53 AM56

AM58 AU58

AU63 BB57 BB66

AK62 AL61

+VCC_GTUS

Reserve for soldering

VCCGTX for SKYLAKE-U 2+3e Merged the GT and GTx rail

RC42

100_0402_1%

2

A A

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

P15-MCP(11/14)PWR-VCCGT

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

LA-D891P

1

15 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

+1.2V_DDR: 1.2V, 3.5A +1.0V_VCCST: 1V, 120mA; VCCPLL: 1V, 120mA +1.0V_VCCSTG: 1V, 40mA +VCCPLL_OC: 1.2V, 260mA +1.0VS_VCCIO: 0.85~0.95V, 3.1A +VCC_SA: 1.15V, 5.1A

D D

+1.2V_MEM_CPUCLK+1.2V_DDR

+1.2V_MEM_CPUCLK

PSC

1

CC68

2

1U_0201_6.3V6M

+1.2V_MEM_CPUCLK

1

RC156 0_0402_5%

2

BSCPSC

1

2

+1.2V_MEM_CPUCLK (VDDQC) Place on CPU Back Side (underneath the package): 1U_0201*1 pcs (@) Primary Side (close to package):

C C

10U_0402 * 1 pcs

1

CC83

CC76

2

@

10U_0402_6.3V6M

1U_0201_6.3V6M

+1.0V_VCCST

close to package

1

2

PSC

CC35

+1.0V_VCCSTG

1U_0402_6.3V6K

BSC

underneath the package

1

2

+VCCPLL_OC +1.0V_VCCST

CC4

@

1U_0402_6.3V6K

+1.2V_DDR

1V@0.12A

1V@0.04A

1.2V@0.26A

1V@0.12A

PSC

close to packageclose to package

AU23 AU28

AU35 AU42 BB23

BB32 BB41 BB47

BB51

AM40

A18

A22

AL23

K20

K21

1

2

CC3

UCPU1N

@

CPU POWER 3 OF 4

VDDQ_AU23 VDDQ_AU28

VDDQ_AU35 VDDQ_AU42 VDDQ_BB23

VDDQ_BB32 VDDQ_BB41 VDDQ_BB47

VDDQ_BB51

VDDQC

VCCST

VCCSTG_A22

VCCPLL_OC

VCCPLL_K20

VCCPLL_K21

SKL-U_BGA1356

1U_0402_6.3V6K

SKL-U

0.95V@3.1A

1.2V@3.5A

1.15V@5.1A

+VCC_SA

VCCIO VCCIO

VCCIO VCCIO VCCIO

VCCIO VCCIO

VCCSA VCCSA VCCSA

VCCSA VCCSA

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

14 OF 20

1 2

RC116 100_0402_1%

+1.0VS_VCCIO

AK28 AK30

AL30 AL42 AM28

AM30 AM42

AK23 AK25 G23

G25 G27 G28

J22 J23 J27

K23 K25 K27

K28 K30

AM23

AM22

H21 H20

+VCC_SA

VCCIO_SENSE VSSIO_SENSE

+1.0VS_VCCIO

12

RC115

100_0402_1%

VSA_SEN- 58 VSA_SEN+ 58

12

Close CPU

RC147

100_0402_1%

VCCIO_SENSE 57 VSSIO_SENSE 5 7

RC155

100_0402_1%

+1.2_DDR Decoupling Requirment Back Side (underneath the package): 10U_0402*2 pcs + 1U_0201*4 pcs (@) Primary Side (close to package): 10U_0402*4 pcs + 22U_0603*3 pcs

B B

+1.2V_DDR

PSC

1

CC86

CC87

CC88

2

22U_0603_6.3V6M

2

22U_0603_6.3V6M

1

CC82

CC19

2

10U_0402_6.3V6M

1

CC20

CC84

2

10U_0402_6.3V6M

BSC

1

CC85

2

CC18

2

@

10U_0402_6.3V6M

1

CC77

CC80

2

@

1U_0201_6.3V6M

1

CC74

CC75

2

@

1U_0201_6.3V6M

+1.0VS_VCCIO Decoupling Requirment Back Side (underneath the package): 10U_0402*2 pcs + 1U_0201*4 pcs (@) Primary Side (close to package): 1U_0402*4 pcs

+1.0VS_VCCIO

PSC

1

CC60

CC69

2

1U_0402_6.3V6K

1

CC63

2

1U_0402_6.3V6K

BSC

1

CC67

2

@

10U_0402_6.3V6M

CC71

CC62

2

@

10U_0402_6.3V6M

2

@

1U_0201_6.3V6M

CC61

1U_0402_6.3V6K

1

CC66

CC72

CC65

@

1U_0201_6.3V6M

2

@

1U_0201_6.3V6M

A A

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

P16-MCP(12/14)PWR-VCCIO,MEM

Size Document Number Rev

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

LA-D891P

1

1.0

16 65Tuesday, December 20, 2016

of

Security Classification

DELL CONFIDENTIAL/PROPRIETARY

Security Classification

Vinaﬁx.com

5

smd.db-x7.ru

D D

C C

+3VALW +1 .8VA +1.0VA +1.0V_PRIM_CORE

1

CC73

2

47U_0805_6.3V6M

+1.0VA

+1.0V_MPHYGT

1

2

1 2

RC125 0_0603_5%

1 2

RC47 0_0 402_5%

1 2

RC133 0_0603_5%

1 2

RC128 0_0402_5%

CC47

47U_0805_6.3V6M

1

2

+1.0V_MPHYAON

+1.0V_SRAM

+1.0V_APLLEBB

CC29

+1.0V_DTS

1

CC52

2

47U_0805_6.3V6M

+1.5VS_AUDIO

12

RC185

@

0_0603_5%

+3V_PRIM

12

RC186 0_0603_5%

L23

1 2

BLM18EG221SN1D_2P

CC53

2P_0201_25V8B

12

CDI#561280 3/23 follow PDG 5.76GHz An EMI Filter Implementation to Isolate

5.76 GHz Noise Coming From VccHDA

4

1

CC32

2

1U_0402_6.3V6K

1

CC14

2

1U_0402_6.3V6K

close UC1.AL1 and <120mil

+1.0V_MPHYGT

close UC1.K17 and <120mil

close UC1.N15 and CC210 <400mil, CC211 <120mil

1

CC43

CC39

2

@

CC64

2P_0201_25V8B

12

1U_0402_6.3V6K

47U_0805_6.3V6M

close UC1.AJ19 and <400mil

+1.0V_SRAM

close UC1.AF20 and <400mil

1

2

@

CC44

+1.0V_APLLEBB

1U_0402_6.3V6K

1

CC54

2

@

1U_0402_6.3V6K

close UC1.AF18 and <400mil

+1.0V_AMPHYPLL

close UC1.N18 and <120mil

1

CC38

2

1U_0402_6.3V6K

+1.0VA+1.0V_PRIM_CORE+1.0V_MPHYAON

close UC1.AB19 and <400mil

1

CC51

2

@

1U_0402_6.3V6K

1.0V@0.696A

1.0V@2.57A

1.0V@0.022A

1.0V@2.1A

1.0V@0.088A

+1.0V_APLL

+1.0VA

+3VALW

1.0V@0.026A

3.3V@0.118A

1.5V@0.068A

+3.3V_SPI

3.3V@0.011A

1.0V@0.642A

+3V_PRIM

+1.0VA

3.3V@0.075A

1.0V@0.033A

3

PCH PWR

+1.8VA

UCPU1O

@

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

SKL-U_BGA1356

CPU POWER 4 OF 4

SKL-U

VCCPGPPA VCCPGPPB

VCCPGPPC VCCPGPPD

VCCPGPPE

VCCPGPPF

VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

15 OF 20

2

RC134 0_0603_5%

1 2

RC139 0_0603_5%

AK15

3.3V@0.085A

AG15

Y16 Y15 T16

AF16

1.8V@0.161A

AD15

V19

T1

AA1

1.8V@0.006A

AK17

3.3V@0.001A

AK19

3.0V@0.001A

BB14

BB10

A14

K19

L21

N20

L19

A10

AN11 AN13

close UC1.BB10 and <120mil

+VCCCLK1

1.0V@0.135A

+VCCCLK2

+VCCCLK3

+VCCCLK4

+VCCCLK5

+VCCCLK6

1 2

+1.8V_PGPP

+3.3V_PGPP

+1.8V_PGPP

+3.3V_PGPP

close UC1.V19 and <120mil

+1.0V_DTS

CORE_VID0 57

CORE_VID1 57

1

close UC1.AG15 and <120milclose UC1.Y16 and <400milclose UC1.T16 and <400mil

1

CC58

2

@

1U_0402_6.3V6K

+3V_PRIM +1.8VA

12

CC46

close UC1.AA1 and <400mil

1

CC50

2

@

1U_0402_6.3V6K

1

CC48

2

4.7P_0402_50V8C

1U_0402_6.3V6K

1

CC45

2

@

+3V_PRIM

1U_0402_6.3V6K

close UC1.AK17 and <120mil

close UC1.AK19 and <120mil

1

CC81

2

CC70

2

0.1U_0402_10V7K

+RTCVCC

1

CC79

2

1U_0402_6.3V6K

0.1U_0402_10V7K

1

CC57

CC56

2

1U_0402_6.3V6K

0.1U_0402_10V7K

+3.3V_PGPP+3V_PRIM

B B

+1.0V_AMPHYPLL+1.0V_MPHYGT

1 2

RC129 0_0402_5%

+1.0VA

close UC1.V15 and <100mil

12

A A

L30

1 2

BLM18EG221SN1D_2P

CC92

2P_0201_25V8B

1

2

12

close UC1.K15 and <120mil

1

CC34

2

@

+1.0V_APLL

R121 0_0201_5%

CC49 2P_0201_25V8B

RC103 0_0603_5%

1U_0402_6.3V6K

+3VALW

22U_0603_6.3V6M

@

CC55

CC59

1

2

place near AD17,AD18,AJ17

2

1

+1.0V_CLK+1.0VA

close UC1.A10 and <120mil

1

CC28

2

1U_0402_6.3V6K

@

+1.0V_CLK

1

2

RC16

1 2

0_0402_5%

RC117

1

0_0603_5%

RC104

1

0_0603_5%

CC27 22U_0603_6.3V6M

+VCCCLK1

1

CC5

0.1U_0201_10V6K

2

Close to Pin A14 Close to Pin N20

2

+VCCCLK2

1

CC42

0.1U_0201_10V6K

2

+VCCCLK3

+1.0V_CLK

1

2

RC118

1 2

0_0603_5%

RC105

1

0_0603_5%

RC15

1

0_0402_5%

CC30 22U_0603_6.3V6M

+VCCCLK4

1

CC40

0.1U_0201_10V6K

2

+VCCCLK5

1

CC41

0.1U_0201_10V6K

2

Close to Pin L19Close to Pin K19

2

+VCCCLK6

DELL CONFIDENTIAL/PROPRIETARY

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

P17-MCP(13/14)PCH PWR

Size Document Num ber Rev

Date: Sheet of

Compal Electronics, Inc.

LA-D891P

1

17 65Tuesday, December 20, 2016

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

Note1: VCCPRIM_CORE Implementation with PCH CORE_VID Recommendation

R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424

GND 2 OF 3

SKL-U

VSS

VSS VSS VSS

VSS VSS

VSS VSS VSS

VSS VSS

VSS

BA49

BA53 BA57 BA6

BA62 BA66 BA71

BB18 BB26 BB30

BB34 BB38 BB43

BB55 BB6 BB60

BB64 BB67 BB70

C1 C25 C5

D10 D11 D14

D18 D22 D25

D26 D30 D34

D39 D44 D45

D47 D48

D53 D58 D6

D62 D66 D69

E11 E15 E18

E21 E46 E50

E53 E56 E6

E65 E71 F1

F13 F2 F22

F23 F27 F28

F32 F33 F35

F37 F38 F4

F40 F42

BA41

UCPU1R

@

F8

VSS

G10

VSS

G22

VSS

G43

VSS

G45

VSS

G48

VSS

G5

VSS

G52

VSS

G55

VSS

G58

VSS

G6

VSS

G60

VSS

G63

VSS

G66

VSS

H15

VSS

H18

VSS

H71

VSS

J11

VSS

J13

VSS

J25

VSS

J28

VSS

J32

VSS

J35

VSS

J38

VSS

J42

VSS

J8

VSS

K16

VSS

K18

VSS

K22

VSS

K61

VSS

K63

VSS

K64

VSS

K65

VSS

K66

VSS

K67

VSS

K68

VSS

K70

VSS

K71

VSS

L11

VSS

L16

VSS

L17

VSS

SKL-U_BGA1356

GND 3 OF 3

SKL-U

VSS VSS

VSS VSS VSS

18 OF 20

L18 L2

L20 L4 L8

N10 N13 N19

N21 N6 N65

N68 P17 P19

P20 P21 R13

R6 T15 T17

T18 T2 T21

T4 U10 U63

U64 U66 U67

U69 U70 V16

V17 V18 W13

W6 W9 Y17

Y19 Y20 Y21

AT63

AT68 AT71

AU10

AU15 AU20 AU32

AU38

AV1

AV68

AV69 AV70 AV71

AW10 AW12 AW14

AW16 AW18 AW21

AW23 AW26 AW28

AW30 AW32 AW34

AW36 AW38 AW41

AW43 AW45 AW47

AW49 AW51 AW53

AW55 AW57

AW6

AW60 AW62

AW64 AW66

AW8

AY66

B10 B14

B18 B22 B30

B34 B39 B44

B48 B53 B58

B62 B66 B71

BA1 BA10 BA14

BA18

BA2 BA23

BA28 BA32 BA36

F68

BA45

UCPU1Q

@

VSS

VSS VSS VSS

VSS VSS

VSS VSS VSS

VSS

GND 1 OF 3

SKL-U

VSS

VSS VSS VSS

VSS VSS

VSS VSS VSS

VSS VSS VSS VSS

VSS VSS

VSS VSS VSS

VSS

AL65

AL66 AM13 AM21

AM25 AM27 AM43

AM45 AM46 AM55

AM60 AM61 AM68

AM71 AM8 AN20

AN23 AN28 AN30

AN32 AN33 AN35

AN37 AN38 AN40

AN42 AN58 AN63

AP10 AP18 AP20

AP23 AP28 AP32

AP35 AP38 AP42

AP58 AP63 AP68

AP70 AR11 AR15

AR16 AR20 AR23

AR28 AR35

AR42 AR43 AR45

AR46 AR48 AR5 AR50

AR52 AR53

AR55 AR58 AR63

AR8 AT2 AT20

AT23 AT28 AT35

AT4 AT42 AT56

AT58

UCPU1P

@

A5

VSS

A67

VSS

A70

VSS

AA2

VSS

AA4

D D

C C

B B

AA65

AA68 AB15 AB16

AB18 AB21

AB8

AD13 AD16 AD19

AD20 AD21 AD62

AD8 AE64 AE65

AE66 AE67 AE68

AE69

AF1 AF10

AF15 AF17

AF2

AF4 AF63

AG16

AG17 AG18 AG19

AG20 AG21 AG71

AH13

AH6

AH63

AH64 AH67

AJ15

AJ18 AJ20

AJ4

AK11 AK16 AK18

AK21 AK22 AK27

AK63 AK68

AK69

AK8

AL2

AL28

AL32 AL35

AL38

AL4

AL45

AL48 AL52 AL55

AL58 AL64

VSS VSS

VSS VSS VSS

VSS VSS

VSS VSS VSS VSS

VSS VSS

VSS VSS VSS

VSS VSS

SKL-U_BGA1356

16 OF 20

SKL-U_BGA1356

17 OF 20

A A

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

P18-MCP(14/14)VSS

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

LA-D891P

1

18 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

+1.8VU +1.8VU

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

DDR_A_DQS#[0..7]6

DDR_A_DQS[0..7]6

DDR_A_D[0..63]6

DDR_A_CA1_[0..9]6

DDR_A_CA2_[0..9]6

D D

+1.2V_DDR

10U_0603_6.3V6M~D

CD2

12

+1.2V_DDR

1U_0402_6.3V6K~D

CD40

CD23

1

2

CD83

1

2

1U_0402_6.3V6K~D

CD24

1

2

+1.8VU

CD36

1

2

+1.2V_DDR

CD18

+1.2V_DDR

+1.2V_DDR +1.2V_DDR +1.2V_DDR

Closed to UD19

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CD59

12

C C

1U_0402_6.3V6K~D

CD38

1

2

1U_0402_6.3V6K~D

CD9

1

2

CD37

1

2

0.1U_0402_16V7K~D

CD11

1

2

CD16

1

CD27

2

+1.2V_DDR +1.2V_DDR

10U_0603_6.3V6M~D

CD31

12

B B

1U_0402_6.3V6K~D

CD10

CD14

1

2

UD4

@

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1

A10

VDD1

U3

VDD1

U4

VDD1

U5

VDD1

U6

VDD1

U10

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

H12

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

K12

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

A11

VDDQ

C12

VDDQ

E8

VDDQ

E12

VDDQ

G12

VDDQ

H8

VDDQ

H9

VDDQ

H11

VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

K11

VDDQ

L12

VDDQ

N8

VDDQ

N12

VDDQ

R12

VDDQ

U11

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

A12

NC

A13

NC

B1

NC

B13

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

U12

NC

U13

NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

P12

VSSQ

N6

VSSQ

M12

VSSQ

M6

VSSQ

L9

VSSQ

K10

VSSQ

H10

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

D12

VSSQ

C6

VSSQ

B12

VSSQ

B6

VSSQ

H9CCNNN8JTMLAR-NTM_FBGA178~D

DQS0#

DQS1#

DQS2#

DQS3#

Vref_DQ

Vref_CA

DQ0

DQ1 DQ2

DQ3

DQ4

DQ5 DQ6 DQ7

DQ8 DQ9

DQ10 DQ11

DQ12

DQ13 DQ14

DQ15

DQ16 DQ17

DQ18 DQ19

DQ20

DQ21 DQ22 DQ23

DQ24

DQ25 DQ26 DQ27

DQ28 DQ29

DQ30 DQ31

CA0

CA1

CA2 CA3

CA4

CA5

CA6 CA7

CA8

CA9

DQS0

DQS1

DQS2

DQS3

DM0

DM1

DM2

DM3

ZQ0

ZQ1

CKE0 CKE1

CS0# CS1#

CK#

ODT

VSS

VSS VSS

VSS

VSS VSS VSS

DDR_A_D27

P9

DDR_A_D29

N9

DDR_A_D25

N10

DDR_A_D31

N11

DDR_A_D28

M8

DDR_A_D24

M9

DDR_A_D30

M10

DDR_A_D26

M11

DDR_A_D20

F11

DDR_A_D17

F10

DDR_A_D22

F9

DDR_A_D18

F8

DDR_A_D21

E11

DDR_A_D16

E10

DDR_A_D23

E9

DDR_A_D19

D9

DDR_A_D51

T8

DDR_A_D55

T9

DDR_A_D49

T10

DDR_A_D53

T11

DDR_A_D50

R8

DDR_A_D54

R9

DDR_A_D48

R10

DDR_A_D52

R11

DDR_A_D56

C11

DDR_A_D61

C10

DDR_A_D62

C9

DDR_A_D59

C8

DDR_A_D60

B11

DDR_A_D57

B10

DDR_A_D63

B9

DDR_A_D58

B8

DDR_A_CA1_0

R2

DDR_A_CA1_1

P2

DDR_A_CA1_2

N2

DDR_A_CA1_3

N3

DDR_A_CA1_4

M3

DDR_A_CA1_5

F3

DDR_A_CA1_6

E3

DDR_A_CA1_7

E2

DDR_A_CA1_8

D2

DDR_A_CA1_9

C2

DDR_A_DQS3

L10

DDR_A_DQS2

G10

DDR_A_DQS6

P10

DDR_A_DQS7

D10

DDR_A_DQS#3

L11

DDR_A_DQS#2

G11

DDR_A_DQS#6

P11

DDR_A_DQS#7

D11

L8

G8

P8

D8

DDR_A0_ZQ0

B3

DDR_A0_ZQ1

B4

K3 K4

DDR_A_CS#0

L3

DDR_A_CS#1

L4

J3

CK

J2

DDR_A_ODT0

J8

J11

H4

B2

B5

C5

E4

E5

F5

H2

J12

K2

L6

M5

N4 N5

R4

R5

T2

T3 T4 T5

RD20 240_0402_1%

1 2

RD19 240_0402_1%

1 2

DDR_A_CKE0 6

DDR_A_CKE1 6

DDR_A_CS#0 6

DDR_A_CS#1 6

DDR_A_CLK0 6

DDR_A_CLK#06

DDR_A_ODT0 6

+VREFDQ_A

+VREFCA

Closed to DRAM Closed to DRAM

+VREFDQ_A

0.047U_0402_10V7K~D

CD21

1

2

0.047U_0402_10V7K~D

CD22

1

2

+1.2V_DDR +1.2V_ DDR +1.2V_DDR +1.2V_DDR

Closed to UD20

10U_0603_6.3V6M~D

CD80

12

1U_0402_6.3V6K~D

CD79

1

2

All VREF traces should have 10 mil trace width

+1.8VU

10U_0603_6.3V6M~D

12

+1.2V_DDR +1.2V_DDR

10U_0603_6.3V6M~D

CD12

12

1U_0402_6.3V6K~D

CD63

1

2

10U_0603_6.3V6M~D

CD3

12

+1.8VU

1U_0402_6.3V6K~D

CD50

CD84

1

2

+1.8VU

CD54

1

2

+1.2V_DDR

1U_0402_6.3V6K~D

CD61

1

2

0.1U_0402_16V7K~D

1U_0402_6.3V6K~D

CD39

1

2

CD65

1

2

1U_0402_6.3V6K~D

CD77

CD60

1

2

0.1U_0402_16V7K~D

1

2

1

CD74

CD57

2

+1.2V_DDR+1.2V_DDR

1U_0402_6.3V6K~D

CD56

CD58

1

2

UD2

@

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1

A10

VDD1

U3

VDD1

U4

VDD1

U5

VDD1

U6

VDD1

U10

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

H12

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

K12

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

A11

VDDQ

C12

VDDQ

E8

VDDQ

E12

VDDQ

G12

VDDQ

H8

VDDQ

H9

VDDQ

H11

VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

K11

VDDQ

L12

VDDQ

N8

VDDQ

N12

VDDQ

R12

VDDQ

U11

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

A12

NC

A13

NC

B1

NC

B13

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

U12

NC

U13

NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

P12

VSSQ

N6

VSSQ

M12

VSSQ

M6

VSSQ

L9

VSSQ

K10

VSSQ

H10

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

D12

VSSQ

C6

VSSQ

B12

VSSQ

B6

VSSQ

H9CCNNN8JTMLAR-NTM_FBGA178~D

Vref_DQ

Vref_CA

DQ0

DQ1 DQ2

DQ3

DQ4

DQ5 DQ6 DQ7

DQ8 DQ9

DQ10 DQ11

DQ12

DQ13 DQ14

DQ15

DQ16 DQ17

DQ18 DQ19

DQ20

DQ21 DQ22 DQ23

DQ24

DQ25 DQ26 DQ27

DQ28 DQ29

DQ30 DQ31

CA0

CA1

CA2 CA3

CA4

CA5

CA6 CA7

CA8

CA9

DQS0

DQS1

DQS2

DQS3

DQS0#

DQS1#

DQS2#

DQS3#

DM0

DM1

DM2

DM3

ZQ0

ZQ1

CKE0 CKE1

CS0# CS1#

CK#

ODT

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

DDR_A_D12

P9

DDR_A_D8

N9

DDR_A_D10

N10

DDR_A_D14

N11

DDR_A_D13

M8

DDR_A_D9

M9

DDR_A_D15

M10

DDR_A_D11

M11

DDR_A_D7

F11

DDR_A_D1

F10

DDR_A_D0

F9

DDR_A_D5

F8

DDR_A_D3

E11

DDR_A_D6

E10

DDR_A_D4

E9

DDR_A_D2

D9

DDR_A_D40

T8

DDR_A_D45

T9

DDR_A_D43

T10

DDR_A_D47

T11

DDR_A_D44

R8

DDR_A_D41

R9

DDR_A_D46

R10

DDR_A_D42

R11

DDR_A_D33

C11

DDR_A_D37

C10

DDR_A_D34

C9

DDR_A_D39

C8

DDR_A_D36

B11

DDR_A_D32

B10

DDR_A_D35

B9

DDR_A_D38

B8

DDR_A_CA2_0

R2

DDR_A_CA2_1

P2

DDR_A_CA2_2

N2

DDR_A_CA2_3

N3

DDR_A_CA2_4

M3

DDR_A_CA2_5

F3

DDR_A_CA2_6

E3

DDR_A_CA2_7

E2

DDR_A_CA2_8

D2

DDR_A_CA2_9

C2

DDR_A_DQS1

L10

DDR_A_DQS0

G10

DDR_A_DQS5

P10

DDR_A_DQS4

D10

DDR_A_DQS#1

L11

DDR_A_DQS#0

G11

DDR_A_DQS#5

P11

DDR_A_DQS#4

D11

L8

G8

P8

D8

DDR_A1_ZQ0

B3

DDR_A1_ZQ1

B4

K3 K4

DDR_A_CS#0

L3

DDR_A_CS#1

L4

J3

CK

J2

DDR_A_ODT0

J8

J11

H4

B2

B5

C5

E4 E5

F5

H2

J12

K2

L6

M5

N4 N5

R4

R5

T2

T3 T4 T5

RD1 240_0402_1%

1 2

RD2 240_0402_1%

1 2

DDR_A_CKE2 6 DDR_A_CKE3 6

DDR_A_CLK1 6 DDR_A_CLK#1 6

+VREFDQ_A

+VREFCA

+VREFDQ_A+VREFCA +VREFCA

0.047U_0402_10V7K~D

CD71

1

2

1

2

0.047U_0402_10V7K~D

CD69

Decoupling per DRAM device VDDQ 4x 0402 1uF 2x 0201 0.1uF 1x 0603 10uF VDDCA 2x 0402 1uF 1x 0603 10uF VDD2 3x 0402 1uF 1x 0603 10uF VDD1 2x 0402 1uF 1x 0603 10uF

A A

intel uesd 0201 for 0.1uF

+1.2V_DDR

10U_0603_6.3V6M~D

12

+1.8VU

10U_0603_6.3V6M~D

CD32

CD41

12

DELL CONFIDENTIAL/PROPRIETARY

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet of

Compal Electronics, Inc.

P19-DDRIII Channel A

LA-D891P

1

19 65Tuesday, December 20, 2016

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

DDR_B_DQS#[0..7]6

DDR_B_DQS[0..7]6

DDR_B_D[0..63]6

DDR_B_CA1_[0..9]6

DDR_B_CA2_[0..9]6

D D

10U_0603_6.3V6M~D

12

+1.2V_DDR

10U_0603_6.3V6M~D

CD17

1

2

+1.2V_DDR +1.2V_DDR +1.2V_DDR +1.2V_DDR

10U_0603_6.3V6M~D

CD1

12

C C

Closed to UD21

1U_0402_6.3V6K~D

CD13

1

2

1U_0402_6.3V6K~D

CD30

1

2

CD82

1

2

+1.2V_DDR

10U_0603_6.3V6M~D

CD73

1

2

B B

+1.8VU+1.8VU

1U_0402_6.3V6K~D

CD49

CD35

1

2

+1.8VU +1.8VU

CD7

1

2

+1.2V_DDR

1U_0402_6.3V6K~D

CD51

1

2

0.1U_0402_16V7K~D

CD15

1

2

+1.2V_DDR

1U_0402_6.3V6K~D

CD33

CD76

1

2

0.1U_0402_16V7K~D

1

2

1

CD28

CD6

2

+1.2V_DDR

1U_0402_6.3V6K~D

CD29

1

2

CD5

1

2

UD3

@

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1

A10

VDD1

U3

VDD1

U4

VDD1

U5

VDD1

U6

VDD1

U10

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

H12

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

K12

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

A11

VDDQ

C12

VDDQ

E8

VDDQ

E12

VDDQ

G12

VDDQ

H8

VDDQ

H9

VDDQ

H11

VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

K11

VDDQ

L12

VDDQ

N8

VDDQ

N12

VDDQ

R12

VDDQ

U11

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

A12

NC

A13

NC

B1

NC

B13

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

U12

NC

U13

NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

P12

VSSQ

N6

VSSQ

M12

VSSQ

M6

VSSQ

L9

VSSQ

K10

VSSQ

H10

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

D12

VSSQ

C6

VSSQ

B12

VSSQ

B6

VSSQ

H9CCNNN8JTMLAR-NTM_FBGA178~D

DQS0#

DQS1#

DQS2#

DQS3#

Vref_DQ

Vref_CA

DQ0

DQ1

DQ2 DQ3

DQ4 DQ5 DQ6

DQ7

DQ8 DQ9

DQ10

DQ11

DQ12

DQ13 DQ14

DQ15

DQ16

DQ17 DQ18 DQ19

DQ20 DQ21 DQ22

DQ23

DQ24 DQ25

DQ26 DQ27

DQ28 DQ29 DQ30

DQ31

CA0

CA1

CA2

CA3

CA4

CA5

CA6

CA7

CA8

CA9

DQS0

DQS1

DQS2

DQS3

DM0

DM1

DM2

DM3

ZQ0

ZQ1

CKE0

CKE1

CS0# CS1#

CK#

ODT

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS VSS VSS

VSS

12

1U_0402_6.3V6K~D

CD81

CD85

1

2

+1.2V_DDR

10U_0603_6.3V6M~D

1

2

1U_0402_6.3V6K~D

12

DDR_B_D30

P9

DDR_B_D28

N9

DDR_B_D26

N10

DDR_B_D27

N11

DDR_B_D29

M8

DDR_B_D24

M9

DDR_B_D25

M10

DDR_B_D31

M11

DDR_B_D48

F11

DDR_B_D51

F10

DDR_B_D50

F9

DDR_B_D54

F8

DDR_B_D52

E11

DDR_B_D49

E10

DDR_B_D55

E9

DDR_B_D53

D9

DDR_B_D62

T8

DDR_B_D58

T9

DDR_B_D61

T10

DDR_B_D56

T11

DDR_B_D63

R8

DDR_B_D59

R9

DDR_B_D57

R10

DDR_B_D60

R11

DDR_B_D19

C11

DDR_B_D18

C10

DDR_B_D16

C9

DDR_B_D17

C8

DDR_B_D23

B11

DDR_B_D22

B10

DDR_B_D21

B9

DDR_B_D20

B8

DDR_B_CA1_0

R2

DDR_B_CA1_1

P2

DDR_B_CA1_2

N2

DDR_B_CA1_3

N3

DDR_B_CA1_4

M3

DDR_B_CA1_5

F3

DDR_B_CA1_6

E3

DDR_B_CA1_7

E2

DDR_B_CA1_8

D2

DDR_B_CA1_9

C2

DDR_B_DQS3

L10

DDR_B_DQS6

G10

DDR_B_DQS7

P10

DDR_B_DQS2

D10

DDR_B_DQS#3

L11

DDR_B_DQS#6

G11

DDR_B_DQS#7

P11

DDR_B_DQS#2

D11

L8

G8

P8

D8

DDR_B0_ZQ0

B3

DDR_B0_ZQ1

B4

K3

K4

DDR_B_CS#0

L3

DDR_B_CS#1 DDR_B_CS#1

L4

J3

CK

J2

DDR_B_ODT0

J8

J11

H4

B2

B5

C5

E4 E5

F5

H2

J12 K2

L6

M5

N4 N5

R4 R5

T2 T3 T4

T5

RD13 240_0402_1%

1

RD14 240_0402_1%

+VREFDQ_B

+VREFCA

2

1

2

DDR_B_CKE0 6

DDR_B_CKE1 6 DDR_B_CKE3 6

DDR_B_CS#0 6

DDR_B_CS#1 6

DDR_B_CLK0 6 DDR_B_CLK#0 6

DDR_B_ODT0 6

Closed to DRAM Closed to DRAM

+VREFDQ_B +VREFDQ_B+VREFCA

0.047U_0402_10V7K~D

CD19

1

2

0.047U_0402_10V7K~D

CD47

1

2

+1.2V_DDR +1.2V_DD R +1.2V_DDR

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

CD64

1

2

All VREF traces should have 10 mil trace width

+1.2V_DDR+1.2V_DDR +1.2V_DDR

10U_0603_6.3V6M~D

Closed to UD22

1U_0402_6.3V6K~D

CD25

1

2

CD52

1

2

+1.8VU+1.8VU

1U_0402_6.3V6K~D

CD48

1U_0402_6.3V6K~D

1

2

CD75

1

2

CD55

1

2

1U_0402_6.3V6K~D

CD78

CD53

1

2

0.1U_0402_16V7K~D

1

CD26

2

+1.2V_DDR +1.2V_DDR

1U_0402_6.3V6K~D

CD62

CD8

1

2

UD1

1U_0402_6.3V6K~D

CD34

1

2

+1.2V_DDR

1U_0402_6.3V6K~D

CD68

1

2

A10

U10

H12

K12

+1.2V_DDR

A11

0.1U_0402_16V7K~D

1

CD4

2

1U_0402_6.3V6K~D

CD66

1

2

C12

E12

G12

H11

K11

N12

R12

U11

A12 A13

B13

U12 U13

P12

M12

K10

H10

D12

B12

@

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1 VDD1

U3

VDD1

U4

VDD1

U5

VDD1

U6

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

VDDQ

E8

VDDQ

H8

VDDQ

H9

VDDQ VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

L12

VDDQ

N8

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

NC NC

B1

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

NC NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

N6

VSSQ

M6

VSSQ

L9

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

C6

VSSQ

B6

VSSQ

H9CCNNN8JTMLAR-NTM_FBGA178~D

DQS0

DQS1

DQS2

DQS3

DQS0#

DQS1#

DQS2#

DQS3#

Vref_DQ

Vref_CA

DQ0

DQ1

DQ2 DQ3

DQ4 DQ5 DQ6

DQ7

DQ8 DQ9

DQ10

DQ11

DQ12 DQ13

DQ14

DQ15

DQ16 DQ17 DQ18

DQ19

DQ20 DQ21

DQ22 DQ23

DQ24 DQ25 DQ26

DQ27

DQ28

DQ29 DQ30 DQ31

CA0

CA1

CA2

CA3

CA4

CA5

CA6

CA7

CA8

CA9

DM0

DM1

DM2

DM3

ZQ0

ZQ1

CKE0 CKE1

CS0# CS1#

CK#

ODT

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

DDR_B_D9

P9

DDR_B_D15

N9

DDR_B_D13

N10

DDR_B_D12

N11

DDR_B_D14

M8

DDR_B_D10

M9

DDR_B_D8

M10

DDR_B_D11

M11

DDR_B_D39

F11

DDR_B_D38

F10

DDR_B_D37

F9

DDR_B_D33

F8

DDR_B_D34

E11

DDR_B_D35

E10

DDR_B_D32

E9

DDR_B_D36

D9

DDR_B_D1

T8

DDR_B_D5

T9

DDR_B_D7

T10

DDR_B_D2

T11

DDR_B_D0

R8

DDR_B_D4

R9

DDR_B_D3

R10

DDR_B_D6

R11

DDR_B_D41

C11

DDR_B_D45

C10

DDR_B_D42

C9

DDR_B_D47

C8

DDR_B_D44

B11

DDR_B_D40

B10

DDR_B_D43

B9

DDR_B_D46

B8

DDR_B_CA2_0

R2

DDR_B_CA2_1

P2

DDR_B_CA2_2

N2

DDR_B_CA2_3

N3

DDR_B_CA2_4

M3

DDR_B_CA2_5

F3

DDR_B_CA2_6

E3

DDR_B_CA2_7

E2

DDR_B_CA2_8

D2

DDR_B_CA2_9

C2

DDR_B_DQS1

L10

DDR_B_DQS4

G10

DDR_B_DQS0

P10

DDR_B_DQS5

D10

DDR_B_DQS#1

L11

DDR_B_DQS#4

G11

DDR_B_DQS#0

P11

DDR_B_DQS#5

D11

L8

G8

P8

D8

DDR_B1_ZQ0

B3

DDR_B1_ZQ1

B4

K3 K4

DDR_B_CS#0

L3 L4

J3

CK

J2

DDR_B_ODT0

J8

J11

H4

B2

B5

C5

E4 E5

F5

H2

J12 K2

L6

M5

N4 N5

R4 R5

T2 T3

T4 T5

RD8 240_0402_1%

1 2

RD7 240_0402_1%

1

2

DDR_B_CKE2 6

DDR_B_CLK1 6 DDR_B_CLK#1 6

+VREFDQ_B

+VREFCA

0.047U_0402_10V7K~D

1

2

0.047U_0402_10V7K~D

CD70

CD72

1

2

Decoupling per DRAM device VDDQ 4x 0402 1uF 2x 0201 0.1uF 1x 0603 10uF VDDCA 2x 0402 1uF 1x 0603 10uF VDD2 3x 0402 1uF 1x 0603 10uF VDD1 2x 0402 1uF 1x 0603 10uF

A A

intel uesd 0201 for 0.1uF

DELL CONFIDENTIAL/PROPRIETARY

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P20-DDRIII Channel B

LA-D891P

1

20 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

VREF traces should be at least 20 mils wide with 20 mils spacing to other signals/planes.

+V_DDR_REF_CA6

D D

4

+1.2V_DDR

M3 M1

RD10

1

2

1

2

1

4.99_0402_1%~D

CD46

0.022U_0402_16V7K~D

RD9

24.9_0402_1%

1

RD12

8.2K_0402_1%

2

1

RD11

8.2K_0402_1%

2

+VREFCA

3

2

1

2

+1.2V_DDR

1

2

1

2

RD6

8.2K_0402_1%

RD4

8.2K_0402_1%

+1.2V_DDR

M3 M1M1 M3

RD15

+V_DDR_REFA_R6

1

CD67

0.022U_0402_16V7K~D

2

1

RD17

C C

24.9_0402_1%

2

1

10_0402_1%~D

1

RD18

8.2K_0402_1%

2

1

RD16

8.2K_0402_1%

2

+VREFDQ_A +VREFDQ_B

+V_DDR_REFB_R6

1

CD20

0.022U_0402_16V7K~D

2

1

RD3

24.9_0402_1%

2

RD5

1

10_0402_1%~D

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P21-DDRIII Vref & Termination

LA-D891P

1

21 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

+3VALW

1

C42

0.1U_0402_10V7K

2

D D

LCD_VCC_TEST_EN3 0

ENVDD

PCH_ENVDD5

+3VALW

U8

5

IN

4

EN

SY6288C20AAC_SOT23-5

LCD_VCC_TEST_EN

BAT54CW-7-F_SOT323-3

R76 220K_0201_5%

OUT

GND

OC

1

2

3

D60

2

3

12

PVT-003.05 0R turn to short pad

+LCDVDD

1 2

R75@0_0603_5%

1

ENVDD

+LCDVDD

12

+LCDVDD

10U_0402_6.3V6M

C40

12

0.1U_0402_10V7K

@

C41

C169

1

2

eDP BackLight Power

0_0603_5%~D@

60mil60mil

0.1U_0402_25V6K~D

12

C233

@

+INV_PWR_SRC

10U_0603_25V6M

B+

R484

1 2

Q33

SI3457BDV-T1-E3_TSOP6~D

D

6

S

4 5

2

G

12

R485

1M_0402_5%~D

EN_INVPWR_R

12

R486

100K_0402_5%~D

1

D

Q32 DII-DMN65D8LW-7

S

3

1

C231

C C

EN_INVPWR30

0.1U_0402_25V6K~D

2

1

G

3

1

C232

2

EN_INVPWR Pull down resistor on p.30

BackLight PWM Control

eDP Conn

eDP_TXN_P15

eDP_TXP_P15

eDP_TXN_P05

eDP_TXP_P05

eDP_AUXP5

eDP_AUXN5

C180 0.1U_0201_10V6K

1

2

C179 0.1U_0201_10V6K

1 2

C177 0.1U_0201_10V6K

1 2

C178 0.1U_0201_10V6K

1 2

C175 0.1U_0201_10V6K

1 2

C176 0.1U_0201_10V6K

1 2

+LCDVDD

0.1U_0402_10V7K

2

1

C167

2

1

1U_1206_50V7

1

C1038

2

0.1U_0402_50V7K

1

C189

2

10U_0402_6.3V6M

@

C174

37.2V

C188

10U_0402_6.3V6M

12

+LED_AN

@

C182

0.1U_0402_50V7K

1

2

eDP_TXN_P1_R

eDP_TXP_P1_R

eDP_TXN_P0_R

eDP_TXP_P0_R

eDP_AUXP_R

eDP_AUXN_R

33P_0402_50V8J

1

2

@EMC@

C190

RF@

C172

PVT-001.02 0R turn to short pad remove co-layout

R412

1

R413

1

R414

1

R415

1 2

R416

1 2

R417

1

PLT_RST#10,23,24,25,27,30,31,34,43 TOUCH_SCREEN_PD#11 I2C1_SDA_TS8

I2C1_SCK_TS8

2

PVT-016.03 reserve TS_RST# path from GPP_C16

eDP_TXN_P1_CONN

0_0402_1%@

eDP_TXP_P1_CONN

0_0402_1%@

eDP_TXN_P0_CONN

0_0402_1%@

eDP_TXP_P0_CONN

0_0402_1%@

eDP_AUXP_CONN

0_0402_1%@

eDP_AUXN_CONN

0_0402_1%@

BL voltage : 33V. Panel BL Power max : 3.6W per pin AWG36 0.75A

PVT-016.02 ALS_CAL_I2C0_SDA change to no use

ALS_CAL_I2C0_SCL8

+3VS

R418 0_0402_5%

1 2

R419

1

R420

1

R421

1 2

R432

TS_ID08

TS_RST#8

1

PVT-003.04 0R turn to short pad

R495 0_0402_5%@

1

EDP_ID011

R464 0_0402_5%@

R465 0_0402_5%@

R466 0_0402_5%@

R467 0_0402_5%@

R468 0_0402_5%@

2

+LCDVDD

LCD_TST3 0

EDP_HPD5

LED_IFB852 LED_IFB752 LED_IFB652

LED_IFB552 LED_IFB452 LED_IFB352

LED_IFB252 LED_IFB152

+LED_AN

+3VS_TS

1

1 2

0_0402_1%@

I2C0_IRQ_TS5 EDP_CAB_DET#8

0_0402_1%@

eDP_TXN_P1_CONN eDP_TXP_P1_CONN

eDP_TXN_P0_CONN eDP_TXP_P0_CONN

eDP_AUXP_CONN eDP_AUXN_CONN

R433

1

PVT-003.03 0R turn to short pad

37.2V

2

TS_RST#R

TOUCH_SCREEN_PD#_R

TS_RST#R

CONN@

ACES_50398-05071-001

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

2

0_0402_1%@

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

JEDP1

55

G5

54

G4

53

G3

52

G2

51

G1

B B

PANEL_BKLEN5

PANEL_BKEN_EC30

BIA_PWM_EC30

EDP_BIA_PWM5

D39

2

1

3

BAT54CW-7-F_SOT323-3

D40

2

1

3

BAT54CW-7-F_SOT323-3

12

R61

220K_0201_5%

1

R67

220K_0201_5%

2

DISPOFF# 52

1

@EMC@

MC1

680P_0402_50V7K

2

INV_PWM 52

Touch Controller

TPK

Laibao

HH

Reserved

Panel

SHARP

BOE

EDP_ID0 TS_ID0

LOW

High

LOW

High

LOW

High High

+3VS_TS

1

2

EMC@

0.1U_0201_10V6K

15P_0402_50V8J

1

2

C196

C191

2

1

Truth Table for EDP_ID/TS_ID0

PVT-016.04 change from PLT_RST# to TS_RST#

TS_RST#R

@EMC@

0.1U_0402_10V7K

C193

TVNST52302AB0_SOT523-3

2

3

DI1

EMC@

1

A A

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

P22-eDP, TS

LA-D891P

1

22 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

D D

4

3

2

1

NGFF(SATA)

PVT-001.03 0R turn to short pad remove co-layout

R60

R59

1

CLK_PCIE_SSD10

CLK_PCIE_SSD#10

C

PVT-011.02 rename SATA -> PCIe rename PCIe -> SATA

PCIE_PRX_SSDTX_N79

PCIE_PRX_SSDTX_P79

PCIE_PTX_SSDRX_N79

PCIe SSD

SATA SSD

PCIE_PTX_SSDRX_P79

SATA_PRX_SSDTX_P89 SATA_PRX_SSDTX_N89

SATA_PTX_SSDRX_N89

SATA_PTX_SSDRX_P89

2

0_0402_1%@

2

0_0402_1%@

CD42 0.22U_0402_10V6K

1 2

CD43 0.22U_0402_10V6K

1

CD44 0.22U_0402_10V6K

1

CD45 0.22U_0402_10V6K

1

CLK_PCIE_SSD_R

CLK_PCIE_SSD#_R

2

PVT-011.03 rename SATA -> PCIe rename PCIe -> SATA

PCIE_PTX_SSDRX_N7_C

PCIE_PTX_SSDRX_P7_C

SATA_PTX_SSDRX_N8_C SATA_PTX_SSDRX_P8_C

CLK_PCIE_SSD#_R CLK_PCIE_SSD_R

JNGFF2

1

GND

3

GND

5

PERn3

7

PERp3

9

GND

11

PETn3

13

PETp3

15

GND

17

PERn2

19

PERp2

21

GND

23

PETn2

25

PETp2

27

GND

29

PERn1

31

PERp1

33

GND

35

PETn1

37

PETp1

39

GND

41

PERn0/SATA-B+

43

PERp0/SATA-B-

45

GND

47

PETn0/SATA-A-

49

PETp0/SATA-A+

51

GND

53

REFCLKn

55

REFCLKp

57

GND

2

3.3V

4

3.3V

6

NC

8

NC

DAS/DSS#/LED#

DEVSLP

PERST#/NC

CLKREQ#/NC

PEWAKE#/NC

3.3V

NC NC

NC NC NC

NC

NC NC NC

NC

10

12 14 16

18 20 22

24 26 28

30 32 34

36 38 40

42 44 46

48 50 52

54 56

58

+3.3VDX_SSD

SSD_LED#

PEWake#

SSD_LED# 42

If system didn't support DEVSLP, set Device Sleep Signal high and keep (from power on), device will ignore. If system support DEVSLP, set Device Sleep Signal low (from power on) device, device will support DEVSLP function as below:

T32

Device Sleep Signal H: SSD enter sleep model.

@

Device Sleep Signal L: SSD exit sleep model.

SSD_DEVSLP 9

PLT_RST# 10,22,24,25,27,30,31,34,43

R57 0_0402_5%

1 2

R64 10K_0402_5%

@

1 2

+3.3VDX_SSD

33P_0402_50V8J

1

2

RF@

+3.3VDX_SSD

1

C139

2

CLKREQ_PCIE#310

PCIE_WAKE_I#24,25,30

0.1U_0402_10V7K

4.7U_0402_6.3V6M

2

C143

1

4.7U_0402_6.3V6M

1

C141

2

C140

47P_0402_50V8J

1

C142

@

2

Solt M & Key M

PVT-003.06 0R turn to short pad

R66

m2280_PCIE_SATA#9

B B

m2280_PCIE_SATA# :

1 2

0_0402_1%@

SSD_PEDET

SATA - Low PCIe - High

Platform Pin-out

67

NC

69

PEDET (NC-PCIe/GND-SATA)

71

GND

73

GND

75

GND

77

GND

LOTES_APCI0146-P004A

CONN@

SUSCLK

3.3V

GND

R65 0_0402_5%

68

70 72 74

76

1 2

@

+3.3VDX_SSD

1

C32

0.1U_0402_10V7K

2

@EMC@

SUSCLK 10,24,25

C

A A

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2015/10/22 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

P23-SATA / PCIE SSD

Size Document Number Rev

Date: Sheet

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

LA-D891P

1.0

23 65Tuesday, December 20, 2016

of

1

of

Vinaﬁx.com

A

smd.db-x7.ru

B

C

D

E

Wireless LAN

1.8VA

PH 100k 1.8VA

1 1

2 2

3 3

PCH_WWAN_WAKE#

PCH

PCH_PCIE_WAKE#

+3VALW

PCH_WWAN_WAKE#

PCIE_WAKE_I#

WLAN_RST#5

PLT_RST#10,22,23,25,27,30,31,34,43

+3VLDO_EC

PH 100k

PVT-001.04 Remove co-layout

HCM1012GH900BP_4P

1

ML8

@0R

PCIE_WAKE_I#

EMC@

+3VS_WLAN

5

1

P

B

2

A

G

3

34

2

U23

Y

TC7SH08FU_SSOP5

PH 1k

EC

PCIE_WAKE_I#

USB20_P79

USB20_N79

4

JNGFF1 WWAN

PCIE_WAKE_I#

JNGFF2 SSD

PCIE_WAKE_I#

JNGFF3 WLAN

PCIE_WAKE_I#

USB20_P7_R

USB20_N7_R

WLAN_RST#_Q

1

R160

100K_0201_5%

2

CV7 0.1U_0201_16V6K

WLAN_DDI2_N038 WLAN_DDI2_P038

WLAN_DDI2_N138 WLAN_DDI2_P138

WLAN_DDI2_N238

WLAN_DDI2_P238

WLAN_DDI2_N338 WLAN_DDI2_P338

WLAN_DP_CLK_AUXP38 WLAN_DP_DAT_AUXN38

1 2

CV8 0.1U_0201_16V6K

1

2

CV5 0.1U_0201_16V6K

1 2

CV6 0.1U_0201_16V6K

1 2

CV15 0.1U_0201_16V6K

1 2

CV16 0.1U_0201_16V6K

1 2

CV13 0.1U_0201_16V6K

1

1 2

1

2

CV14 0.1U_0201_16V6K

CV4 0.1U_0201_16V6K

CV3 0.1U_0201_16V6K

WLAN_DDI2_N0_C WLAN_DDI2_P0_C

WLAN_DDI2_N1_C WLAN_DDI2_P1_C

WLAN_DDI2_N2_C

WLAN_DDI2_P2_C

WLAN_DDI2_N3_C WLAN_DDI2_P3_C

WLAN_DP_CLK_AUXP_C WLAN_DP_DAT_AUXN_C

USB20_P7_R

USB20_N7_R

+3VS_WLAN +3VS_WLAN

10U_0402_6.3V6M

C154

C148

12

JNGFF3

1 3

5 7

GND USB_D+

USB_DGND

1

2

C156

0.1U_0201_10V6K

10U_0402_6.3V6M

C153

15P_0402_50V8J

1

2

RF@

3.3VAUX

C152

LED1#

2 4 6

2

10U_0402_6.3V6M

12

+3VS_WLAN

10U_0402_6.3V6M

C155

C147

12

1

2

C150

0.1U_0201_10V6K

C146

15P_0402_50V8J

1

2

C149

2

RF@

Solt A & Key A

closed to pin 2, 4 closed to pin 72, 74

Platform Pin-out

17

WLAN_DDI2_N3_C WLAN_DDI2_P3_C

WLAN_DDI2_N2_C

WLAN_DDI2_P2_C

WIG_HPD

CV9 .1U_0402_16V7K

PCIE_PTX_WLANRX_P59

PCIE_PTX_WLANRX_N59

PCIE_PRX_WLANTX_P59 PCIE_PRX_WLANTX_N59

PCIE_PTX_WLANRX_P69 PCIE_PTX_WLANRX_N69

PCIE_PRX_WLANTX_P69 PCIE_PRX_WLANTX_N69

1 2

CV10 .1U_0402_16V7K

1 2

CV11 .1U_0402_16V7K

1 2

CV12 .1U_0402_16V7K

1 2

WIG_HPD_R38

3

PCIE_PTX_WLANRX_P5_C PCIE_PTX_WLANRX_N5_C

CLKREQ_PCIE#110

PCIE_WAKE_I#23,25,30

PCIE_PTX_WLANRX_P6_C PCIE_PTX_WLANRX_N6_C

+5VS

G

2

1

D

S

QV1 LBSS138LT1G_SOT-23-3

CLK1_PCIE_WLAN_R CLK1_PCIE_WLAN#_R

CLK0_PCIE_WiGig_R CLK0_PCIE_WiGig#_R

WIG_HPD

12

@

R162

100K_0402_5%

MLDIR Sense

19

DP_ML3N

21

DP_ML3P

23

GND

25

DP_ML2N

27

DP_ML2P

29

GND

31

DP_HPD

33

GND

35

PETP0

37

PETN0

39

GND

41

PERP0

43

PERN0

45

GND

47

REFCLKP0

49

REFCLKN0

51

GND

53

CLKQ0#

55

PEWAKE0#

57

GND

59

PETP1

61

PETN1

63

GND

65

PERP1

67

PERN1

69

GND

71

REFCLKP1

73

REFCLKN1

75

GND

77

GND

LOTES_APCI0145-P004A

CONN@

BT_OFF#_R

+3VS_WLAN

1

2

12

LED2#

DP_AUXN

DP_AUXP

DP_ML1N

DP_ML1P

DP_ML0N

DP_ML0P

CLink RESET

CLink DATA

CLink CLK

COEX3

COEX2 COEX1

SUSCLK

PERST0# W_DISABLE2# W_DISABLE1#

I2C_DATA

I2C_CLK

I2C IRQ

GPIO0 NFC RESET#

PERST1#

CLKREQ1#

PEWAKE1#

3.3VAUX

R156

@

100K_0402_5%

PJSOT24CW_SOT323-3

@

R158

220K_0201_5%

GND

1

D91

16 18 20

22 24 26

28 30 32

34 36 38

40 42 44

46 48 50

52 54 56

58 60 62

64 66 68

70 72 74

76

WLAN_DP_DAT_AUXN_C WLAN_DP_CLK_AUXP_C

WLAN_DDI2_N1_C

WLAN_DDI2_P1_C

WLAN_DDI2_N0_C WLAN_DDI2_P0_C

WLAN_RST#_Q BT_OFF#_R

WL_OFF#_R

WLAN_RST#_Q

PCIE_WAKE_I#

2

3

+3VS_WLAN

R161

PVT-003.07 0R turn to short pad

CLKREQ_PCIE#010

BT_ON/OFF# 8

BT_RADIO_DIS#30

1

2

0_0402_1%@

C151 0.1U_0201_10V6K

1 2

@EMC@

CL_RST# 7 CL_DATA 7 CL_CLK 7

NGFF_COEX3 25 NGFF_COEX2 25 NGFF_COEX1 25

SUSCLK 10,23,25

PVT-001.05 Remove co-layout

CLK1_PCIE_WLAN10

CLK1_PCIE_WLAN#10

HCM1012GH900BP_4P

1 2

EMC@

L24

34

CLK1_PCIE_WLAN_R

CLK1_PCIE_WLAN#_R

4 4

CLK0_PCIE_WiGig10

CLK0_PCIE_WiGig#10

A

PVT-001.06 0R turn to short pad remove co-layout

R167

R168

1 2

1

0_0402_1%@

2

0_0402_1%@

CLK0_PCIE_WiGig_R

CLK0_PCIE_WiGig#_R

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2015/10/22 2013/10/28

+3VS_WLAN

12

100K_0402_5%

WL_OFF#_R

12

R159

220K_0201_5%

Compal Secret Data

Deciphered Date

R157

@

D

D92

1

PJSOT24CW_SOT323-3

2

3

WLAN_ON 8

WLAN_WIGIG60GHZ_DIS#30

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet of

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

P24-WLAN / BT / WiGig

LA-D891P

E

24 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

+1.8VS_AUDIO +1.8VS

D D

USB3#2

PCIe#12

U4 USB3/PCIe MUX

Common Choke

PCIe/USB3.0

(SATA2)

PCH

PCIe#11

USB3#2 Common

JNGFF1

PCIe/SATA

USB2.0

+3VS_WWAN +3VS_WWAN

C105

0.1U_0201_10V6K

33P_0201_50V8J

RF@

22U_0603_6.3V6M

C103

1

2

closed to pin 2, 4

1

2

@RF@

47P_0402_50V8J

1

C106

2

1

C104

2

22U_0603_6.3V6M

C101

0.1U_0201_10V6K

C99

1

2

closed to pin 64, 66

33P_0201_50V8J

RF@

1

C102

2

+3VS_WWAN

@RF@

47P_0402_50V8J

C100

1

+

2

+3VS_WWAN

100U_A1_6.3VM_R70M

C97

100U_A1_6.3VM_R70M

1

C98

+

2

Choke

+1.8VS+3VS

12

R33

2

+3VS

R456

0.1U_0201_10V6K

PCIe/USB 3.0 Mux

C C

USB 3.0 #2

PCIE #12

B B

USB3TP29

USB3TN29

USB3RP29 USB3RN29

PCIE_PTX_WWANRX_P129 PCIE_PTX_WWANRX_N129

PCIE_PRX_WWANTX_P129 PCIE_PRX_WWANTX_N129

USB3TP2

USB3TN2 USB3RP2 USB3RN2

USB3TP

PCIE_PTX_WRX_UT_P12_SW

USB3TN

PCIE_PTX_WRX_UT_N12_SW

C217 0.1U_0201_10V6K

1 2

C215 0.1U_0201_10V6K

1 2

C31 0.22U_0402_10V6K

1 2

C30 0.22U_0402_10V6K

1

2

NGFF1_CONFIG_125,30

SEL=0 A to B SEL=1 A to C

USB3RP

PCIE_PRX_WTX_UR_P12_SW PCIE_PRX_WTX_UR_P12_SW_CONN

USB3RN

PCIE_PRX_WTX_UR_N12_SW PCIE_PRX_WTX_UR_N12_SW_CONN

USB3TP2_C USB3TN2_C

PCIE_PTX_WWANRX_P12_C PCIE_PTX_WWANRX_N12_C

PVT-001.07 Remove co-layout

ML1

EMC@

1

CMMI21T-670Y-N_4P

PVT-001.08 Remove co-layout

CMMI21T-670Y-N_4P

4

1

EMC@

ML2

U4

19

B0+

18

17

16

15

14 13

12

9

2

PI3PCIE3212ZBEX_TQFN20_2P5X4P5

34

2

3

2

VDD

B0-

VDD

B1+

VDD

B1-

C0+

A0+

C0C1+

C1-

SEL

PD

A0-

A1+

A1-

GND

PGND

PCIE_PTX_WRX_UT_P12_SW_CONN

PCIE_PTX_WRX_UT_N12_SW_CONN

1

6

10

PCIE_PTX_WRX_UT_P12_SW

3

PCIE_PTX_WRX_UT_N12_SW

4

PCIE_PRX_WTX_UR_P12_SW

7

PCIE_PRX_WTX_UR_N12_SW

8

5

11

20

21

1

2

10U_0402_6.3V6M

C28

1

2

PCIE_PRX_WWANTX_N119 PCIE_PRX_WWANTX_P119

PCIE_PTX_WWANRX_N119

PCIE_PTX_WWANRX_P119

1 2

10U_0402_6.3V6M

12

0_0402_5%

C228

@

NGFF1_CONFIG_030

PCH_WWAN_WAKE#5

C227

SAR_DPR30

PVT-003.09 0R turn to short pad

R38

1

CV2 0.22U_0402_10V6K

1 2

CV1 0.22U_0402_10V6K

1

2

NGFF1_CONFIG_125,30

NGFF1_CONFIG_230

G

1

D

DII-DMN65D8LW-7

Q5

R482 0_0402_5%

1 2

@

NGFF1_CONFIG_330

2

0_0402_1%@

PCIE_PRX_WTX_UR_N12_SW_CONN

PCIE_PRX_WTX_UR_P12_SW_CONN

PCIE_PTX_WRX_UT_N12_SW_CONN PCIE_PTX_WRX_UT_P12_SW_CONN

ANTCTRL041 ANTCTRL141

@

T25

T24

@

T20

@

10K_0201_1%

3

S

SAR_DPR_R

USB20_P4_CONN USB20_N4_CONN

WWAN_WAKE#

SAR_DPR_R

PCIE_PTX_WWANRX_N11_C PCIE_PTX_WWANRX_P11_C

CLK2_PCIE_WWAN#_R CLK2_PCIE_WWAN_R

JNGFF1

1

CONFIG_3

3

GND

5

7

9

11

GND

USB_D+

USB_DGND

1.8V

FULL_CARD_PWR_OFF#

3.3V

GPIO_9/DAS/DSS#/LED#1

Solt B & Key B

21

CONFIG_0

23

25 27

33

39

41

43 45

47

49 51

53

55 57

59

61 63

65

67 69 71

73 75

77

1.8V 1.8V

GPIO_11

1.8V

DPR GND

PERN1/USB3RXN/SSIC-RXN29UIM-RESET

PERp1/USB3RxP/SSIC-RxP31UIM-CLK GND

PETn1/USB3TxN/SSIC-TxN35UIM-PWR

PETp1/USB3TxP/SSIC-TxP37DEVSLP GND

PERn0/SATA_B+

PERp0/SATA_BGND

PETn0/SATA_A-

PETp0/SATA_A+ GND

REFCLKN

REFCLKP GND

1.8V

ANTCTL0

ANTCTL1

1.8V

ANTCTL2

1.8V

ANTCTL3

1.8V

RESET#

1.8V

CONFIG_1 GND

GND CONFIG_2

GND

LOTES_APCI0144-P007A

CONN@

1.8V/3.3V

1.8V (26MHZ)

PU.1.8V

(low active)

W_DISABLE#

1.8V

GPIO_5

1.8V

GPIO_6

GPIO_7

1.8V

GPIO_10

1.8V

GPIO_8

UIM-DATA

1.8V

GPIO_0

1.8V

GPIO_1

1.8V

GPIO_2

GPIO_3

1.8V

GPIO_4

PERST#

CLKREQ#

PEWAKE#

1.8V

COEX3

1.8V

COEX2

1.8V

COEX1

SIM DETECT

SUSCLK

3.3V

GND

NC

PVT-003.08 0R turn to short pad

R455

1

R35

10K_0201_1%

GNSS_OFF#_R

WWAN_OFF#_R

module with internal PU

UIM_DET#

+3VS_WWAN

2

4

6 8

10

20 22

24

26

28 30

32

34 36

38

40 42

44

46 48

50

52 54

56

58 60

62

64 66

68

70 72 74

76

R122 0_0402_5%

WWAN_PWR _OFF#_R WWAN_OFF#_R

GNSS_OFF#_R

R489

GNSS_SCL

GNSS_IRQ

UIM_DET#

SUSCLK_L

+3VS_WWAN

2

0_0402_1%@

+1.8VS +1.8VS

12

1 2

+3VS_WWAN

12

1

@

R492

R493

R494

R124

G

2

Q29

13

D

S

DII-DMN65D8LW-7

D94

2 1

RB751S40T1G_SOD523-2

D95

2

RB751S40T1G_SOD523-2

R123

100K_0402_5%

1

C108

0.1U_0201_10V6K

2

UIM_RESET 2 6

UIM_CLK 26 UIM_DATA 26

+SIM_PWR

2

0_0201_5%

PLT_RST# 10,22,23,24 ,27,30,31,34,43

CLKREQ_PCIE#210

PCIE_WAKE_I#23,24,30

1

1 2

@

1 2

@

1

@

1

C107

0.1U_0402_10V7K

2

@EMC@

WWAN_OFF_EC#41

1

WWAN_OFF# 11

+1.8VS

1

R479

@

47K_0402_5%

2

1 2

GPIO control pop R125 R479 depop R123

PVT-003.10 0R turn to short pad

WWAN_DEVSLP9

R219

GNSS_IRQ 5

2

0_0201_5%

2

0_0201_5%

GNSS_OFF# 5

UIM_DET 26

R125

@

0_0201_5%

FULL_CARD_PWR_OFF#

depop R125 R479 pop R123no use

1 2

0_0402_1%@

PVT-004 Reserve 0R for COEX1,2,3

WWAN_PWR_OFF#5

NGFF_COEX3 24 NGFF_COEX2 24 NGFF_COEX1 24

SUSCLK 10,23,24

State# CONFIG_0 CONFIG_1 CONFIG_2 CONFIG_3 Module Type Port Configuration (Pin 21) (Pin 69) (Pin 75) (Pin 1) 0 GND GND GND GND SSD – SATA N/A 1 GND HIGH GND GND SSD – PCIe N/A

PVT-001.09 Remove co-layout

DLW21HN900HQ2L_4P

CLK2_PCIE_WWAN10

CLK2_PCIE_WWAN#10

4

1

L9

EMC@

3

2

3

2

CLK2_PCIE_WWAN_R

CLK2_PCIE_WWAN#_R

2 GND GND HIGH GND WWAN – PCIe 0 3 GND HIGH HIGH GND WWAN – PCIe 1 4 GND GND GND HIGH WWAN – USB 3.0 0 5 GND HIGH GND HIGH WWAN – USB 3.0 1 6 GND GND HIGH HIGH WWAN – USB 3.0 2 7 GND HIGH HIGH HIGH WWAN – USB 3.0 3 8 HIGH GND GND GND WWAN – SSIC 0 9 HIGH HIGH GND GND WWAN – SSIC 1

A A

PVT-001.10 Remove co-layout

DLW21HN900H Q2L_4P

USB20_P49

USB20_N49

5

1

4

EMC@

L10

2

3

2

3

4

USB20_P4_CONN

USB20_N4_CONN

10 HIGH GND HIGH GND WWAN – SSIC 2 11 HIGH HIGH HIGH GND WWAN – SSIC 3 12 HIGH GND GND HIGH WWAN – PCIe 2 13 HIGH HIGH GND HIGH WWAN – PCIe 3 14 HIGH GND HIGH HIGH DDP|HCA - PCIe N/A 15 HIGH HIGH HIGH HIGH No Module N/A

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet of

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

P25-WWAN / 2nd SSD

LA-D891P

1

25 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

D D

4

3

2

1

uSIM CONN

+SIM_PWR

JSIM1

7

10

11

8

9

GND

DETECT

GND1 GND2

GND3

RESET CLOCK

JAE_SF56S006V4A

CONN@

UIM_DET25

C

UIM_DET UIM_RESET

VCC

GND

VPP

1

2

UIM_CLK

3

4

5

UIM_DATA

6

IO

4.7U_0402_6.3V6M

1

2

1

C145

2

@RF@

0.1U_0402_10V7K

C144

UIM_RESET 25

UIM_CLK 25

UIM_DATA 25

UIM_CLK

2

C137

RF@

47P_0402_50V8J~D

1

R155

RF@

51_0402_5%

2

UIM_DATA

@RF@

15K_0402_1%

1

R154

C136

2.2P_0402_50V8C~D

2

33P_0402_50V8J

RF@

2

C135

1

EMC@

2

ESD207-B1-02EL_TSLP-2-19-2

D64

2

C138

2.2P_0402_50V8C~D

1

EMC@

2

EMC@

1

ESD

UIM_DATAUIM_RESET

ESD207-B1-02EL_TSLP-2-19-2

D65

2

EMC@

1

ESD207-B1-02EL_TSLP-2-19-2

D63

2

EMC@

1

D62

2

EMC@

1

UIM_DETUIM_CLK

C134

2.2P_0402_50V8C~D

1

2

C133

2.2P_0402_50V8C~D

EMC@

1

EMC@

2

C

Normal Close

B B

A A

Security Classification

2041/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2041/09/08 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

P26-SIM Card CONN

Size Document Number Rev

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

LA-D891P

1.0

26 65Tuesday, December 20, 2016

1

of

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

Card Reader

1)Placing the RTS5242 chip and flash card socket locate to suit trace routing for SI / EMI / ESD.

2)Keep bulk and de-coupling capacitors as close as possible to the RTS5242 chip and flash card socket.

■ Bulk capacitor for Card_3V3 place closed to flash card socket.

■ Bulk capacitor for 3V3_IN / 3V3aux / DV12S place closed to RTS5242 chip.

3)Keep damping resistor (ex, for SD CLK / MS CLK) as close as possible to the RTS5242 chip.

4)Keep these capacitors for SD card / MS card signals as close as possible to flash card socket.

D D

+3VS_CR +3VS_CR

10U_0402_6.3V6M

CR7

12

DV33_18

SD_RCLK_M_L SD_RCLK_P_L

SD_CLK_L SD_CMD_L SD_D3_L

SD_D2_L

SP7_SDWP

0.1U_0402_10V7K

2

CR8

1

PVT-003.11 0R turn to short pad

RR2

1

RR3

1

RR4

1

RR6

1

RR8

1 2

RR9

1

SD_LN1_P

SD_LN1_M

SD_LN0_P SD_LN0_M

2

+SD_VDD1

EMC@

1

2

1

0_0402_1%@

SD_REG2

RR1010K_0402_5%

CR151U_0402_6.3V6K

SD_RCLK_M

SD_RCLK_P

SD_CLK

SD_CMD

SD_D3 SD_D2

SD_D2

1

2

+3VS_CR

2.2P_0402_50V8C~D

CR13

1

@

2.2P_0402_50V8C~D CR18

1

2

EMC@

1

2.2P_0402_50V8C~D

@

CR16

CR17

1

2

CR19

1U_0402_6.3V6K

2.2P_0402_50V8C~D

@

EMC@

2

CR10

CR11

1

2

PLT_RST#10,22,23,24,25,30,31,34,43

CLKREQ_PCIE#510

PCIE_PTX_CARDRX_P99

C

PCIE_PTX_CARDRX_N99 PCIE_PRX_CARDTX_P99 PCIE_PRX_CARDTX_N99

MEDIACARD_IRQ#5

+3VS_CR

Support Runtime D3 mode => DE-POP RR11 No Support Runtime D3 mode => POP RR11 (pull high)

0.1U_0402_10V7K

2

1

4.7U_0402_6.3V6M

CR5

1

CR6

2

CLK_PCIE_MMI_R CLK_PCIE_MMI#_R

CR22

1

CR23

1 2

CR14

1 2

CR12

1 2

RR12

@

RR11 10K_0402_5%

Close to UR1

CR9

2

1

0.1U_0402_10V7K

2

0.1U_0402_10V7K

1

2

+SD_VDD2

RR1 6.2K_0402_1%

2

1

PCIE_PTX_CARDRX_P9_C PCIE_PTX_CARDRX_N9_C

PCIE_PRX_CARDTX_P9_C

PCIE_PRX_CARDTX_N9_C

0_0402_5%

2

Close to UR1

0.1U_0402_10V7K

2

CR20

1

CD_WAKE#

SD_CD#

DV12S

RREF

4.7U_0402_6.3V6M

1

CR21

2

27

11

CARD_3V3

3V3_IN

3V3aux

DV33_18

SP1

RTS5242

E-PAD

RTS5242-GR_QFN32_4X4-S

33

SP2 SP3 SP4

SP5 SP6

SP7

SD_LN1_P

SD_LN1_M

SD_LN0_P

SD_LN0_M

SDREG2

GPIO

12

18

15

16 17 19

20 21

29

22 23

26 25

24

28

1

2

5 6

3 4

7

8

32

31

30

10

14

13

9

UR1

PERST#

CLK_REQ#

REFCLKP REFCLKN

HSIP HSIN

HSOP

HSON

WAKE#

MS_INS#

SD_CD#

AV12

DV12S

SD_VDD2

RREF

If GPIO not use for LED function, must be pull-high (Layout guide)

C

B B

JCR1

CONN@

PVT-001.11 remove co-layout

RR7 0_0402_5%~D

CLK_PCIE_MMI10

CLK_PCIE_MMI#10

1

RR5 0_0402_5%~D

1

2

A A

5

CLK_PCIE_MMI_R

CLK_PCIE_MMI#_R

For GPIO control SD_WP

SP7_SDWP

HOST_SD_WP#8

4

QR1

DMN2400UFB4-7_DFN1006H4-3

1 3

D

S

G

2

Security Classification

2041/09/08 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2041/09/08 2012/07/25

3

+SD_VDD1

1

2

Compal Secret Data

Deciphered Date

Close to JCR1

10U_0402_6.3V6M

0.1U_0402_10V7K

CR1

2

1

CR2

+SD_VDD2

SD_D2

SD_D3 SD_CMD

SD_CLK

SD_RCLK_P SD_RCLK_M SD_CD#

0.1U_0402_10V7K

4.7U_0402_6.3V6M

CR4

1

CR3

2

SD_LN0_P SD_LN0_M

SD_LN1_M

SD_LN1_P

Title

P27-Card Reader(RT5242)

Size Document Number Rev

Date: Sheet

Date: Sheet of

P27-Card Reader(RT5242)

1

DAT2

2

CD/DAT3

3

CMD

4

VDD1

5

CLK

6

VSS

7

DAT0/RCLK+

8

DAT1/RCLK-

9

CD

13

VDD2

14

SWIO

15

VSS

16

D0+

17

D0-

18

VSS

19

D1-

20

D1+

21

VSS

T-SOL_158-1000902614

Compal Electronics, Inc.

GND

10

11

12

22

23

27 65Tuesday, December 20, 2016

1

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4

3

2

1

2

1 2

0.22U_0402_16V7K

@

CA46

1

2

RA27

1K_0201_5%

RA8

BEEP30

+AVDD1

LA1 BLM21PG600SN1D_2P

1 2

1

CA19

2

10U_0603_6.3V6M

D D

AGND

+5VS_AUDIO

1

0_0201_5%

Beep sound

DMIC_CLK12 DMIC_DATA12 DMIC_DATA34

22P_0201_25V8

CA34

1

2

CA35

1

@EMC@

2

CA80 close with UA1 Pin6

CA41

1

@EMC@

2

CA81 close with DMIC12 CA84 close with DMIC34

Analog

Digital

C C

RA23 0_0402_5 %

1 2

RA22 0_0402_5 %

RA25 0_0402_5 %

1

1 2

2

+5VS_AUDIO

LA2 0_0603_5%

+DVDD

Moat

GND

RA29

1

0_0402_5%

RA36

@

1

0_0402_5%

2

B B

+3VS_AUDIO

AGND

20mA

2.2U_0402_6.3V6M

1

2

10mil

0.1U_0201_10V6K

CA39

CA33

1

2

For EMI

RA26

+3VS_AUDIO

+1.5VS_AUDIO

A A

1 2

0_0402_5%

RA18

@

1 2

0_0402_5%

CA42,CA31 close with UA1 Pin4

10mA

10mil

2.2U_0402_6.3V6M

1

2

0.1U_0201_10V6K

CA38

CA36

1

2

For EMI

CA105,CA104 close with UA1 Pin12

5

+AVDD1

150 mA

10U_0603_6.3V6M

CA22

1

2

AGND

1

2

10U_0603_6.3V6M

CA25

1

2

CA92,CA114 close to UA1 pin41

LA3 0_0603_5%

1 2

2

CA31 10U_0603_10V6M

1

CA103,CA104 close to UA1 pin46

1 2

RA40 100K_0201_5%

check divided voltage meet HP1

+DVDD+1.8VS_AUDIO

+DVDD

TC3

TC2

+DVDDIO

+DVDD

CA23

0.1U_0201_10V6K

HP_PLUG#29

PVT-003.12 0R turn to short pad

RA41

1

PVT-003.13 0R turn to short pad

RA42

4

RA28

1 2

0.22U_0402_16V7K

1K_0201_5%

CA47

1

2

SPKR11

Close to UA1 Pin32

CA20

AGND

10U_0603_6.3V6M

30mil

CA26

0.1U_0201_10V6K

1

2

30mil

@

CA30

0.1U_0201_10V6K

1

2

+5VS_AUDIO

HP2

RA13 100K_0402_ 1%

+DVDD

RA14 200K_0402_ 1%

2

0_0402_1%@

DMIC_CLK12 DMIC_DATA12

2

1

DMIC_CLK34 DMIC_DATA34

0_0402_1%@

0.22U_0402_16V7K

1

2

RA9

1

1K_0201_5%

AGND

RA10

1

100K_0201_5%

2

1

+RTCBATT

1 2

MIC1

1

2 3 4

SPK0641HT4H-1-7_8P

DMIC@

MIC3

1 2 3

4

SPK0641HT4H-1-7_8P

DMIC@

CA48

2

CA16

0.1U_0201_10V6K

CA17

2

2.2U_0402_6.3V6M

2

12

SPK_-OUT-L+29

SPK_-OUT-L-29

SPK_-OUT-R-29

SPK_-OUT-R+29

RA31

@

0_0402_5%

RA19 100K_0201_ 5%

RA15 100K_0201_ 5%

DMIC_DATA3433

DMIC_CLK3433

GND

VDD

GND

LRSEL CLK

GND

DAT

VDD

GND GND

LRSEL

GND

CLK

GND

DAT

1

2

12

1

1 2

0.1U_0201_10V6K

RA30 1K_0201_5%

AGND

HP2

RA12 0_0402_5%

1 2

2

DMIC_DATA34 DMIC_DATA12

DMIC_CLK34

5 6 7

8

5 6

7 8

CA14

1

2

1

DMIC_DATA34

DMIC_DATA12

CODEC_MUTE#

DMIC_CLK12

DMIC_CLK34

+DVDD

1

2

+DVDD

1

2

MONO_IN

1

@

CA13

100P_0201_25V7K

2

37

AVSS1

38

VREF

39

LDO1-CAP

40

AVDD1

41

PVDD1

42

SPK-L+

43

SPK-L-

44

SPK-R-

45

SPK-R+

46

PVDD2

47

5VSTB/AUX MODE

48

HP2/LINE2 JD

49

PGND

+DVDD

JACK_PLUG#

1

CA40

0.1U_0402_10V7K

2

RA24 22_0402_5%

1

RA32 22_0402_5%

1

33P_0402_50V8J

12

C73@EMC@

+DVDD

CA1

0.1U_0201_10V6K

CA2

0.1U_0201_10V6K

3

LINE1-L 29

LINE1-R 29

AGND

SLEEVE 29

RING2 29

CBN

CBP

AVSS2

AVDD2

MIC2-VREFO-R 29

MIC2-VREFO-L 29

HPOUT-L

HPOUT-R

24

23

22

21

20

19

18

17

16

15

14

13

HPOUT-L 29

HPOUT-R 29

CA18 1U_0603 _10V6K

1

CA21 1U_0603_ 10V6K

1 2

CA27 0.1U_0201_10V6K

CA28 10U_0402_6.3V6M

4/19 update CA28 from 0603 to 0402

10U_0603_6.3V6M

CA32

1

AGND

1 2

1

Place near UA1 pin25/26

2

AGND

2

MONO_IN

1

CA15 10U_0603_6.3V6M

32

33

34

35

36

LINE1-L

LINE2-L

LINE1-R

LINE2-R

29

30

31

PCBEEP

28

RING2

SLEEVE

MIC2-CAP

MIC2-VREFO-R

15mil 15mil

27

MIC2-VREFO-L

LINE1-VREFO-R-E/MONO

UA1

26

25

HP-OUT-L

HP-OUT-R

HP-OUT2-R

HP-OUT2-L

LDO2-CAP

LINE1-VREFO-L-E

LDO3-CAP

CPVEE

CPVDD

Codec

PDB

SPDIFO/GPIO2-DMIC-DATA-34

HP1/LINE1 JD

1

33P_0402_50V8J

C74@EMC@

PVT-003.14 0R turn to short pad

RA43

DMIC_CLK12 DMIC_DATA12

DVDD4GPIO0/DMIC-DATA5GPIO1/DMIC-CLK

3

2

33P_0402_50V8J

12

1 2

MIC4 on WF-CAM Module

MIC4 on WF-CAM ModuleMIC4 on WF-CAM Module

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

6

DMIC_CLK_R

C83@EMC@

1

0_0402_1%@

2 3

4

SYNC

DC DET/EAPD

BCLK

9

7

8

HDA_BLK_L

RA17 22_0402_5%

RA16 22_0402_5%

1

CA37

@

22P_0402_50V8G

2

MIC2

VDD

GND GND

LRSEL

GND

CLK

GND

DAT

SPK0641HT4H-1-7_8P

DMIC@

2015/10/22 2013/10/28

SDATA-OUT

SDATA-IN10DVDD-IO

11

HDA_SDI0_L

1

5 6

7 8

12

ALC3253-CG_MQFN48_6X6

+DVDDIO

2

+DVDD

1

2

+DVDD

1

2

Compal Secret Data

CA5

0.1U_0201_10V6K

CA6

0.1U_0201_10V6K

place near JWFC1

2

HDA_SDOUT 1 1

HDA_SDI0 11

HDA_SYNC 11

HDA_BLK 11

Deciphered Date

2

Analog

Pin14~40

Add Moat between Analog and Digital shape

Digital

Pin1~13, 41~48

+DVDD

1

RA33 10K_0402_5%

2

CODEC_MUTE#

HPOUT-LHPOUT-R

330P_0402_50V8J

1

CA9

2

AGND

CA24

0.1U_0201_10V6K

1

2

DMN66D0LDW-7_SOT363-6

12

@

RA21 1K_0201_5%

Title

Size Document Num ber Rev

Date: Sheet

Date: Sheet of

330P_0402_50V8J

1

CA11

2

AGND

+1.8VS_AUDIO

150 mA

10U_0603_6.3V6M

1

2

AGND

RA11

1

2

0_0402_5%

CA29

Analog

Digital

+3VLDO_EC

5

G

Q22A

4

3

S

D

Compal Electronics, Inc.

P28-Audio Codec ALC3253

LA-D891P

1

NB_MUTE# 30

28 65Tuesday, December 20, 2016

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2

1

Int. Speaker Conn.

40mil = For 4ohm 3W Speaker

D D

LA8 BLM15PX181SN1D_2P

SPK_-OUT-L+28 SPK_-OUT-L-28

EMC@

1 2

LA7 BLM15PX181SN1D_2P

1 2

SPK_L+ SPK_L+

TVNST52302AB0_SOT523-3

2

CA45

1000P_0402_50V7K~D

CA44

1

@EMC@

2

3

DA9

EMC@

1

SPK_L-SPK_L-

SPK_ID

SPK_ID11

RA38

Int. Speaker Conn.

RA39

10K_0402_5%

12

0_0402_1%@

PVT-003.15 0R turn to short pad

40mil = For 4ohm 3W Speaker

LA6 BLM15PX181SN1D_2P

SPK_-OUT-R+28 SPK_-OUT-R-28

C C

EMC@

1 2

LA5 BLM15PX181SN1D_2P

1 2

SPK_R+ SPK_R-

TVNST52302AB0_SOT523-3

2

CA42

1000P_0402_50V7K~D

CA43

1000P_0402_50V7K~D

1

@EMC@

2

@EMC@

2

3

DA8

EMC@

1

SPK_R+ SPK_R-

SPK_ID Speaker

High

Low

Main Soure

2nd Soure

+3V_PRIM

12

JSPK

SPK_L+

1

SPK_LSPK_R+

SPK_R-

1

2

3

4

5

G1

6

G2

ACES_50376-00601-001

CONN@

7 8

Universal Audio Jack

RA6 16.2_0402_1%

1

HPOUT-L28

HPOUT-R28

CA12 10U_0402_6.3V6 M

LINE1-L28

LINE1-R28

B B

1 2

CA10 10U_0402_6.3V6 M

1 2

use X5R for better performance

MIC2-VREFO-L28

MIC2-VREFO-R28

SLEEVE28

RING228

RA3 16.2_0402_1%

RA2 2.2K_0201_5%

1 2

RA1 2.2K_0201_5%

1

1 2

2

40mil

2

HPOUT-R_L

40mil

EMC@

L19 BLM15AX700SN1D_2P

1 2

L18 BLM15AX700SN1D_2P

1 2

EMC@

L12 BLM15PX330SN1D_2P

1 2

EMC@

L15 BLM15PX330SN1D_2P

1

2

1K_0201_5%

12

@

RA4

AGND AGND

1

2

AGND

ESD207-B1-02EL_TSLP-2-19-2

1K_0201_5%

12

@

RA5

680P_0201_50V7K

CA8

CA7

1

2

AGND

12

EMC@

DA4

1

2

ESD207-B1-02EL_TSLP-2-19-2

12

DA3

EMC@

HPOL_CONNHPOUT-L_L

HPOR_CONN

ESD207-B1-02EL_TSLP-2-19-2

EMC@

DA5

SLEEVE_CONN

RING2_CONN

ESD207-B1-02EL_TSLP-2-19-2

12

DA1

EMC@

Universal Audio Jack CONN

RING2_CONN HPOL_CONN

RA7

2

HP_PLUG#28

1

0_0201_5%

HP_PLUG#_R

HPOR_CONN SLEEVE_CONN

ESD207-B1-02EL_TSLP-2-19-2

12

DA6

EMC@

AGND

3

1

5

6

2

4

7

GND

8

GND

SINGA_2SJ3157-001111F

CONN@

JP1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P29-SPK CONN

LA-D891P

1

29 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

+3V_LDO

RE11

1 2

@

0_0603_5%

PVT-003.16

+LCDVDD

PVT-005.01 depop debug LED

12

R411 100_0402_5%

@

21

LED4

D D

PLT_RST#10,22,23,24,25,27,30,31,34,43

+3VLDO_EC

RE56 100K_0201_5%1

RE53 100K_0201_5%

RE63 100K_0201_5%1 2

RE40 100K_0201_5%

RE115 100K_0201_5%1 2

RE117 100K_0201_5%1

@

+RTCVCC_EC

C C

RE22 100K_0201_5%

RE27 100K_0201_5%1

RE25 100K_0201_5%

RE31 100K_0201_5%1 2

RE17 100K_0201_5%1

RE2 10K_0201_5%1 2

1

2

1 2

2

RE69 220K_0201_5%1 2

1 2

RE51 100K_0201_5%

RE24 100K_0201_5%

1 2

2

1

@

2

1 2

2

PWR_SW_IN#

CE21

1U_0402_6.3V6K

NGFF1_CONFIG_0

NGFF1_CONFIG_1

NGFF1_CONFIG_2 NGFF1_CONFIG_3

LID_CL_SIO# FP_POA_WAKE#

PWR_SW_IN#43,49

EN_INVPWR

LCD_TST

VBUS1_ECOK

PWR_SW_IN#

VBUS3_ECOK

PWR_SW_IN#

EC_ALWON

DCIN1_EN RUN_ON

GPIO171

RE113 10K_0201_5%

A

@

13

2

G

@

1 2

HT-191UD5_AMBER

for Debug

D

DII-DMN65D8LW-7

Q16

S

+3VLDO_EC

12

RE61

10K_0201_5%

ME_FWP#

12

@

RE54 10K_0201_5%

PVT-005.02 de-pop debug power SW pop by using Memo

1

3

TS-A52-3-P1-S017_4P

for Debug

1

0R turn to short pad

CE5

10U_0603_6.3V6M

2

KICKSTD_SW_DET#8,42

SW3

@

2

4

PMIC have internal pull up -->

WLAN_WIGIG60GHZ_DIS#24

32 KHz Clock

Y2

MEC_XTAL1

32.768KHZ_9.0PF_9H03200033

+3VLDO_EC

100K_0201_5%

12

B B

12

@

RE42

JTAG_RST#

SHORT PADS

1U_0402_6.3V4Z

RE41

1

CE24

2

1

CE12 18P_0402_50V8J

2

@

CLK_PCI_MEC

12

RE34

10_0402_1%

1

CE22

4.7P_0402_50V8C

2

MEC_XTAL2

1

2

1

CE11 18P_0402_50V8J

2

RTC_RST#10

Place close pin N6

Different with X6 project

+3VLDO_EC

GPIO170

GPIO171

RE7 10K_0201_5%

RE8 10K_0201_5%

1

12

1

2

5

RE5 10K_0201_5%

RE6 10K_0201_5%

12

DEBUG_UART0_TX8

JTAG_TDI

JTAG_TMS

JTAG_CLK JTAG_TDO

+3VLDO_EC

1

2

1

RE3

10K_0201_5%

RE1

10K_0201_5%

RE4

10K_0201_5%

@

2

move to USH board

RE9 49.9_0402_1%

1

GND1

GND2

2

1

2

3

4

5

6

7

HOST_DEBUG_TX

8

9

10

11

12

A A

JDEG3

ACES_50521-01041-P01

CONN@

4

+3VLDO_EC

0.1U_0201_10V6K

CE14

CE8

1

2

KICKSTD_SW_DET#

SIO_EXT_SMI#11

1

PANEL_BKEN_EC22

NGFF1_CONFIG_125

BT_RADIO_DIS#24

3.3V_NGFF1_EN44

SYS_PWROK10,13

FP_POA_EN43

EC_SLP_S0IX#11

EN_INVPWR22

ME_FWP#11

FP_POA_WAKE#43

USH_PWR_STATE#43

USH_PWR_STATE#

1

DII-DMN65D8LW-7

0.1U_0402_10V7K

1

2

ALWON

2.2K_0201_5%

RE122 1M_0201_5%1

2

0_0402_5%

CE30

1

2

ALWON53

RE12

Thermal diode mapping

1641 Channel

DP1/DN1

DP2/DN2

DP3/DN3

DP4/DN4

DP5/DN5

DP6/DN6

4

0.1U_0201_10V6K

CE10

1

2

PBAT_SMBDAT48 PBAT_SMBCLK48

PCH_PWR_EN44

PCIE_WAKE_I#23,24,25

NGFF1_CONFIG_225

DET_R#48

NGFF1_CONFIG_025

PCH_PCIE_WAKE#10

SIO_SLP_WLAN#10

RE119

1 2

AC_PRESENT10

VBUS2_ECOK48

PCH_RSMRST#10,13

FAN1_PWM43

VBUS1_ECOK48

UPD2_I2C_ALERT#36

DCIN3_EN48

SIO_RCIN#7

LAN_WAKE#10

LCD_TST22

BIA_PWM_EC22

LCD_VCC_TEST_EN22

USB_PWR_SHR_EN#39

SIO_EXT_SCI#8

PCH_DPWROK10

R127

1 2

DOCK_PWR_EN45

IRQ_SERIRQ7 PLT_RST#10,22,23,24,25,27,30,31,34,43

CLK_PCI_MEC7

LPC_FRAME#7,43

LPC_AD07,43

LPC_AD17,43 LPC_AD27,43 LPC_AD37,43

CLKRUN#7

SIO_EXT_WAKE#9

RE26

2

SUSWARN#10

NGFF1_CONFIG_1

EC_SLP_S0IX#

EN_INVPWR

ME_FWP#

FP_POA_WAKE#

RUN_ON

USH_PWR_STATE#

2

13

D

Q10

S

VSET_1641

RE58

1.96K_0402_1%

Location

CPU

SSD

WLAN

Charger

LCD

USH

3

LE1

+3VLDO_EC_L

+3VLDO_EC

CE17

TC24

ACAV_IN51

2

1

2

0_0201_5%

BEEP28

0_0402_5%

RTCRST_ON

0.1U_0201_10V6K

CE20

100K_0201_5%

12

0.1U_0201_10V6K

1

2

UPD2_I2C_ALERT#

LCD_TST

RE16

0.1U_0201_10V6K

FAN1_TACH43

AC_DISC#48

DCIN2_EN48

NB_MUTE#28

SAR_DPR25

LID_CL_SIO#43

G

0.1U_0201_10V6K

CE23

CE16

1

2

PBAT_SMBDAT

PBAT_SMBCLK

PCH_PWR_EN

PCIE_WAKE_I#

NGFF1_CONFIG_2

NGFF1_CONFIG_0

PCH_PCIE_WAKE#

RTCRST_ON

JTAG_CLK

JTAG_RST#

JTAG_TDI JTAG_TDO

JTAG_TMS

EC_PROCHOT#

SIO_EXT_SMI#_R

PLT_RST#

CLK_PCI_MEC

EC_ALWON

PWR_SW_IN#

RUNPWROK

BOARD_ID

MEC_XTAL1 MEC_XTAL2

@

1

CE3 100P_0402_50V8J

2

@

1

CE4 100P_0402_50V8J

2

@

1

CE1 100P_0402_50V8J

2

+3VALW

+RTCVCC

1 2

RE18

1

RE19

0_0402_5%

UE1

D7

GPIO007/SMB03_DATA

C7

GPIO010/SMB03_CLK

H13

GPIO110

G11

GPIO111

G10

GPIO112

F10

GPIO113

G13

GPIO114

G12

GPIO115

A8

GPIO154/PS2_CLK1B

E2

GPIO155/PS2_DAT1B

D9

GPIO147/JTAG_CLK

B10

nJTAG_RST

D10

GPIO145/JTAG_TDI

C10

GPIO146/JTAG_TDO

A10

GPIO150/JTAG_TMS

N7

GPIO050/FAN_TACH0

K8

GPIO051

L8

GPIO052

N8

GPIO016

N11

GPIO151

N12

GPIO152

M8

GPIO053/PWM0

N9

GPIO054

N10

GPIO055

M9

GPIO056

M10

GPIO001/PWM4

L10

GPIO014

K9

GPIO015

D11

GPIO035

C12

GPIO133

B12

GPIO134

K11

GPIO140

B4

GPIO123

C6

GPIO022/BCM_B_CLK

B6

GPIO023/BCM_B_DAT

D6

GPIO024/nBCM_B_INT

C4

GPIO047

C5

GPIO046

A5

GPIO045

N5

GPIO011/nSMI

M5

GPIO061/nLPCPD

L5

SER_IRQ/GPIO063

K3

nLRESET/GPIO64

N6

PCI_CLK/GPIO65

K5

nLFRAME/GPIO66

K6

LAD0

L6

LAD1

M6

LAD2

K7

LAD3

J3

nCLKRUN/GPIO67

L7

GPIO100/nEC_SCI

C1

VCI_OVRD_IN/GPIO164

E1

VCI_OUT

C2

nVCI_IN0/GPIO163

F2

GPIO062/nRESETO

F1

VCC_PWRGD/GPIO057

G1

GPIO033/RC_ID

H2

GPIO021

J1

GPIO060

M11

GPIO031

N13

GPIO032

L11

GPIO040

G4

GPIO017

H11

GPIO124

J11

GPIO025

J12

GPIO026/TIN1

J10

GPIO027

J13

GPIO030

H10

GPIO125

D1

GPIO165

C3

GPIO175/32KHZ_OUT

A1

XTAL1

B1

XTAL2

MEC1641-PZV_TFBGA144

1

C

E

3

1

C

E

3

C

E

3 1

0_0402_5%@

2

1

CE18

0.1U_0201_10V6K

2

Q7

2

B

MMBT3904WH_SOT323-3

Q8

2

B

MMBT3904WH_SOT323-3

Q2

2

B

MMBT3904WH_SOT323-3

1 2

FBMA-L11-160808-800LMT_0603

+RTCVCC_EC

F3

B2

K4

VTR1

VTR0

VBAT

VSS_XTAL

VSS2

VSS1

VSS0

J4

F4

A2

H4

REM_DIODE2_P

REM_DIODE2_N

LCD

REM_DIODE2_P

REM_DIODE3_P

WWAN

REM_DIODE3_N

A6

L4

K2

VTR4

VTR2

VTR3

AVSS1

F11

REM_DIODE3_P43

REM_DIODE3_N43

3

1

2

1

2

+3VLDO_EC

0.1U_0201_10V6K

CE7

1

2

F12

K12

VTR_FLASH

BGND

A3

K1

N4

H3

AVTR1

VTR_REG

AVTR_ADC

VREF_ADC

VSS_ADC

VSS_RO

VR_CAP

N3

H1

G2

+VR_CAP

OTP thermal diode

Q11

@

CE2 100P_0402_50V8J

@

CE26 100P_0402_50V8J

C

B

E

3 1

Q6

C

B

E

3 1

on USH board

0.1U_0201_10V6K

CE31

CE32

1

2

B11

VREF_VTT

GPIO104/UART_TX

GPIO105/UART_RX

GPIO106/NRESET_OUT

GPIO127/A20M

GPIO153/LED2

GPIO157/LED1 GPIO156/LED0

GPIO170/MSCLK

GPIO171/MSDATA

GPIO003/SMB00_DATA

GPIO004/SMB00_CLK

GPIO005/SMB01_DATA

GPIO006/SMB01_CLK

GPIO012/SMB07_DATA

GPIO013/SMB07_CLK

PECI_DAT

GPIO144/SMB04_CLK

GPIO143/SMB04_DATA

GPIO142/SMB05_CLK

GPIO141/SMB05_DATA

GPIO041/nSYS_SHDN

GPIO220/V_IN

ADC0/GPIO200

ADC1/GPIO201

ADC2/GPIO202 ADC3/GPIO203

ADC4/GPIO204

ADC8/GPIO210

ADC9/GPIO211

ADC10/GPIO212

ADC11/GPIO213

CE6

1

2

4.7U_0603_6.3V6K

REM_DIODE1_P

2

MMBT3904WH_SOT323-3

2

MMBT3904WH_SOT323-3

CPUSSD

REM_DIODE1_N

Charger

REM_DIODE1_P

+1.0V_VCCST

GPIO020

GPIO107

GPIO166

GPIO167

GPIO222

GPIO132

GPIO130

GPIO131

GPIO043

GPIO002

DP1_DN4

DN1_DP4

DP2_DN5

DN2_DP5

DP3_DN6

DN3_DP6

VSET

GPIO034

GPIO036

0.1U_0201_10V6K

CE25

1

2

A4

C9 B9

G3

H12

D4

E4

E3 B3

J2

K13

C11

E10

M7

A7

D3

UPD1_TD1_PS_SMBDAT

D2

UPD1_TD1_PS_SMBCLK

B7

VBUS3_ECOK

K10

UPD2_TD2_USH_SMBDAT

M12

UPD2_TD2_USH_SMBCLK

L12 M13

L13

PECI_EC

A12

USH_RST#_L

A11

B8 C8 A9

D8

L9

EC_IN_VOLUMEDOWN#

E12

E11

F13

E13

C13

D13

B13

A13

D12

L3

L1

M2 M4

N2

L2

M3

M1

N1

D5

B5

EC_PROCHOT#

HOST_DEBUG_TX

HOME_KEY#

USH_I2C_ALERT#

DSW_ON

3VALW_PG_EC

GPIO170 GPIO171

SUS_ON

RE47 0_0402_5%

CHG_MCP23017_SMBCLK CHG_MCP23017_SMBDAT

BASE_SMBCLK

BASE_SMBDAT

NGFF1_CONFIG_3

EC_IN_VOLUMEUP#

REM_DIODE1_P

REM_DIODE1_N

REM_DIODE2_P

REM_DIODE2_N

REM_DIODE3_P REM_DIODE3_N

VSET_1641

UPD1_I2C_ALERT#

SUSACK#

I_ADP

I_BATT

DCIN1_EN

P_SYS

BASE_SMB_ALERT#

CE27

CE29

CE28

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

RE50 75_0402_5%

1

D

Q12

2

DII-DMN65D8LW-7

G

S

3

SIO_SLP_S4#10,32

DET_L# 43,48

IMVP_VR_ON 32

HOME_KEY# 43

PROXIMITY_ACT#31

USH_I2C_ALERT#43

CHG_LED# 43 PWR_LED# 42,43

RE121

1

2

0_0201_5%

SML1_SMBDAT7 SML1_SMBCLK7

UPD1_TD1_PS_SMBDAT31,35,37

UPD1_TD1_PS_SMBCLK31,35,37

VBUS3_ECOK48

UPD2_TD2_USH_SMBDAT36,37,43

UPD2_TD2_USH_SMBCLK36,37,43 SIO_PWRBTN#10,13

AUX_EN_WLAN44

12

CHG_MCP23017_SMBCLK41,51 CHG_MCP23017_SMBDAT41,51

BASE_SMBCLK43

BASE_SMBDAT43

NGFF1_CONFIG_325

EC_IN_VOLUMEDOWN#42

EC_IN_VOLUMEUP#42

1

2

2200P_0402_50V7K

1

2

2200P_0402_50V7K

1

2

2200P_0402_50V7K

UPD1_I2C_ALERT#35

SUSACK# 10

I_ADP 51

RE124

@

DCIN1_EN 48

SIO_SLP_S3#10,32

SIO_SLP_SUS#10,32,44,55,56,57

P_SYS 51,58

SIO_SLP_A#10

USB3_PWR_SHR_VBUS_EN39

BASE_SMB_ALERT#43

1 2

2014/09/08 2013/10/28

2

1 2

USH_RST# 43

0_0201_5%

3VALW_PG30,48,53

P_SYS

I_ADP

RUNPWROK

Compal Secret Data

H_PROCHOT# 11,50,51,54,58

EN_PD_HV1 35,48

PCH_AUD_PWR_EN8

0.1U_0201_10V6K

CE13

1

2

I_BATT

0.1U_0201_10V6K

CE15

1

2

+3VS

1

RE79

10K_0402_5%

2

D90

2 1

RB751S40T1G_SOD523-2

RE80

1 2

RE81

RE82

1

RE83

1

RE84

1 2

RE85

1 2

RE86

@

1 2

RE109

PVT-008 resolve MS exit ha ng issue

Deciphered Date

PVT-006 change Board_ID to PVT

SIO_SLP_S4#

SUS_ON

RUN_ON

0.1U_0201_10V6K

CE19

1

2

0_0402_5%

0_0402_5%@

2

0_0402_5%

2

0_0402_5%

1

+3VLDO_EC

240K 4700p

12

1

2

R

C

130K 4700p 62K 33K

8.2K

4.3K

4.3K_0402_1%

BOARD_IDBOARD_ID

CE9

4700P_0402_25V7K

RE15

BOARD_ID rise time is measured from 5%~68%.

PBAT_SMBCLK PBAT_SMBDAT

UPD1_I2C_ALERT# UPD2_I2C_ALERT#

CHG_MCP23017_SMBCLK CHG_MCP23017_SMBDAT

UPD1_TD1_PS_SMBDAT UPD1_TD1_PS_SMBCLK

UPD2_TD2_USH_SMBDAT UPD2_TD2_USH_SMBCLK

DSW_ON

USH_I2C_ALERT#

BASE_SMB_ALERT#

PCIE_WAKE_I#

SUS_ON

EC_IN_VOLUMEDOWN#

HOME_KEY#

EC_IN_VOLUMEUP#

PCH_PCIE_WAKE#

BASE_SMBCLK

BASE_SMBDAT

PECI_EC

RE97 0_0402_5%1 2

1 2

RE98

RE99 0_0402_5%

1 2

RE100

1

RE114

RE120 0_0402_5%

check need +3V_PRIM PG??

2

1

2

1 2

3VALW_PG30,48,53

5VALW_PG53

1.2V_DDR_PG54

5VD_PG 53

1.0VA_PG 55

1.8VA_PG 56

1.8VU_PG 56

+1.0VS_VCCIO_PG57

1.0V_PRIM_CORE_PG57

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet

RE38 2.2K_0201_5%1

RE35 2.2K_0201_5%

RE20 2.2K_0201_5%1 2

RE52 2.2K_0201_5%

RE110 2.2K_0201_5%

RE111 2.2K_0201_5%1

PVT-007.01 improve compatibility with dock

RE30 1K_0201_5%

RE32 1K_0201_5%1 2

RE68 1K_0201_5%1 2

RE70 1K_0201_5%1

RE43 10K_0201_5%1 2

RE116 10K_0201_5%1 2

RE33 10K_0201_5%1 2

RE67 100K_0201_5%

RE112 100K_0201_5%1

RE65 10K_0201_5%1

RE62 10K_0201_5%1

RE64 10K_0201_5%

RE55

@

RE46 1K_0201_5%1 2

RE45 1K_0201_5%1

RE49

0_0402_5%@

RUN_ON_ECSIO_SLP_S3#

0_0402_5%@

if 1.2V DDR power Rail to avoid double pull high need to inform Power

Compal Electronics, Inc.

P30-EC SMSC MEC1641

LA-D891P

1

R C

2K 1K

1 2

1

1 2

1

1 2

Pre-EVT1,2 EVT1

4700p

DVT1

4700p

DVT1.1

4700p

DVT2

4700p

PVT 4700p 4700p

2

10K_0201_5%

2

43_0201_5%

SUS_ON_EC 32,43,45,54

RUN_ON_EC 32,54

AUD_PWR_EN 44

REV

+3VLDO_EC

H_PECI 11

30 65Tuesday, December 20, 2016

1.0

of

Vinaﬁx.com

5

smd.db-x7.ru

4

Gyro + Accelerometer

3

2

1

+3VS

check PH resistor Jayton 1k

RS18 2.2K_0201_5%

RS19 2.2K_0201_5%

D D

ACCEL_INT1#8

C C

RS10

RS9

RS11

@

RS6

@

E-Compass

ISH_I2C0_SCL8

ISH_I2C0_SDA8

ACCEL_INT1#

12

10K_0201_5%

12

10K_0201_5%

12

10K_0201_5%

12

10K_0201_5%

RS8

RS21

1 2

RS15

RS16

1 2

ISH_I2C0_SDA ISH_I2C0_SCL

ACCEL_INT1#_C

ACCEL_INT2#_C

ACCEL_INT1#_C ACCEL_INT2#_C

0_0201_5%

1 2

1

0_0201_5%

2

0_0201_5%

+3VS

12

ACCEL_INT1#_C

+3VS

12

SA1

PVT-003.17 0R turn to short pad

RS20

0_0402_1%@

+3VS_gyro

LGA1

5

VDDIO

1

SDO/SA0

2

SDx

3

SCx

4

INT1

6

GND1

7

GND2

LSM6DS3USTR_LGA14_2P5X3

PVT-003.21 0R turn to short pad

RS17

0_0402_1%@

+3VS_ecom

U3

6

VDDIO

5

VDD

1

SCL/SPC

9

SD0/SA1

11

SDA/SDI/SDO

3

GND

LIS3MDLTR_LGA12_2X2

add slave address

RES1 RES2

DRDY

VDD

INT2

CS_Aux

SCL

SDA

C1

CS

INT

NC

CS

2 12

4 8

10

7

8

9

10

11

12

13

14

ACCEL_INT2#_C

+3VS_gyro

ISH_I2C0_SCL

ISH_I2C0_SDA

CS8 1U _0402_6.3V6K

MAG_DRDY

+3VS_ecom

12

RS14

RS7

1 2

0_0201_5%

+3VS_gyro

+3VS_ecom

ACCEL_INT2# 8

Place close to LGA1 PIN1,3,22 and 23

1

CS4 10U_0402_6.3V6M

2

1

CS3

0.1U_0201_10V6K

2

1

CS5

0.1U_0201_10V6K

2

Place close to LGA2 PIN1,3,22 and 23

1

CS6 10U_0402_6.3V6M

2

1

CS7

0.1U_0201_10V6K

2

1

CS9

0.1U_0201_10V6K

2

TPM

+3V_PRIM +3VS_TPM

+3VALW +3VALW_TPM

+3VS_TPM

PVT-003.18

0.01R turn to short pad

R153

1 2

@

PVT-003.22

0.01R turn to short pad

R457

1 2

@

TPM@

1 2

R439

C226

@TPM@

0.1U_0201_10V6K

Reserve for EMI please close to U15

10K_0402_5%

PCH_SPI_CLK_TPM

12

0_0603_5%

TPM_PIRQ#

+3VALW_TPM

C229

TPM@

1

2

10U_0603_6.3V6M

+3VS_TPM

1

2

C230

TPM@

0.1U_0201_10V6K

+TPM_LPM

C128

C130

TPM@

1

2

10U_0603_6.3V6M

NOTE: Place 0.1 uF capacitors as close as possible to the device power pins

C125

TPM@

1

2

0.1U_0201_10V6K

R453 0_0402_5%@TPM@

PVT-003.19

0.01R turn to short pad

R454

1 2

@ 0_0603_5%

12

+TPM_LPM

close to U20.8

C224

TPM@

1

2

0.1U_0201_10V6K

+3VS_TPM

+3VS

1

2

C225

TPM@

4.7U_0402_6.3V6M

+3VALW_TPM

U4246

R450 0_0402_5%@TPM@

1

SAR Proximity Sensor

B B

ME - ANT QP-48G

+3VS

1

CS1

0.1U_0201_10V6K

2

JANT1

EMI_Spring

CONN@

1

2

ANT_CS0 SX9306_CS0

1

CS2

0.1U_0201_10V6K

10NH_LQG15HS10NJ 02D_5%_0402

LS1

2

1

RS2

0_0402_5%

RS1

0_0402_5%

2

+3VS+1.8VU

12

U1

C2

VDD

SVDDC1NIRQ

A3

CS0

B3

CS1

C3

CS2

SX9310ICSTRT_WLCSP9

@

T2

PAD~D

SCL

SDA

GND

12

RS5

2.2K_0402_5%

A2

B1

A1

B2

12

RS3

2.2K_0402_5%

PAD~D

1

RS4

2.2K_0402_5%

2

PS_SMBCLK

PS_SMBDAT

@

T4

@

T1

@

T3

PROXIMITY_ACT#30

+3VS

2

Q1A DMN2400UV-7_SOT-563-6

5

4

Q1B DMN2400UV-7_SOT-563-6

1

C8

0.1U_0201_10V6K

2

61

3

UPD1_TD1_PS_SMBCLK30,35,37

UPD1_TD1_PS_SMBDAT30,35,37

SIO_SLP_S0#10,45,57

PCH_SPI_CS2#

PCH_SPI_CLK_TPM7

PCH_SPI_CS2#7

PCH_SPI_CS2#

PCH_SPI_SO_TPM7

PCH_SPI_SI_TPM7

PLT_RST#10,22,23,24,25,27,30,34,43

R460

PVT-003.20

0.01R turn to short pad

TPM_PIRQ#7,8

TPM@

1 2

R458 100_0402_ 5%@TPM@

1 2

@

R451

R452 0_0402_5%@TPM@

2

TPM_LPM

0_0603_5%

TPM_PIRQ#

PCH_SPI_CLK_TPM

12

10K_0402_5%

12

+3VS_TPM

G

2

A A

S

@TPM@

Q13

DMP3099L-7_SOT23-3

D

1 3

TPM_LPM

1

2

29

GPIO0/SDA/XOR_OUT

30

GPIO1/SCL

3

GPIO2/GPX

6

GPIO3/BADD

24

LAD0/MISO

21

LAD1/MOSI

18

LAD2/SPI_IRQ#

15

LAD3

19

LCKL/SCLK

20

LFRAME#/SCS#

17

LRESET#/SPI_RST#/SRESET#

27

SERIRQ

13

CLKRUN#/GPIO4/SINT#

28

LPCPD#

4

PP

5

TEST

NPCT650VBBYX_QFN32_5X5

TPM@

NOTE: Follow the SPI topology layout guidelines in the relevant Intel Platform Design Guide

@TPM@

R459 10K_0402_5%

VSB

VDD

GND

PGND

Reserved

1

+TPM_LPM

8

14

+3VS_TPM

22

2

NC

7

NC

10

NC

11

NC

25

NC

26

NC

31

NC

9

16

23

32

33

12

Security Classification

2041/09/08 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2041/09/08 2013/10/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P31-Sensor / TPM

LA-D891P

1

31 65Tuesday, December 20, 2016

of

1.0

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smd.db-x7.ru

D D

4

3

2

1

+3VALW

5

B

VCC

A

G

3

+3VALW

5

P

B

A

G

3

U15

4

Y

12

0_0402_5%~D@

SIO_SLP_SUS#10,30,44,55,56,57

4

O

12

0_0402_5%~D@

H_VCCST_PWRGD_P10,13

+3VALW

1

B

2

UC8

RE44 100K_0402_5%

A

TC7SH08FU_SSOP5

SUS_ON_P 56

RUN_ON_EC30,54

5

P

4

O

G

3

1

2

VCCST_EN 45

RE48 100K_0402_5%

IMVP_VR_ON30,32

SIO_SLP_S3#10,30

IMVP_VR_ON30,32

C

SIO_SLP_S4#10,30

SUS_ON_EC30,43,45,54

B B

1

2

MC74VHC1G09DFT2G_SC70-5

RE10

1

2

UC7

TC7SH08FU_SSOP5

RE36

SIO_SLP_S3#

UC5

SIO_SLP_S3#

UC6

+3VALW

5

1

P

B

A

G

3

+3VALW

5

P

B

A

G

3

O

2

TC7SH08FU_SSOP5

RE13

1

2

TC7SH08FU_SSOP5

RE23

4

12

RE14 100K_0402_5%

12

0_0402_5%~D@

4

12

RE29 100K_0402_5%

12

0_0402_5%~D@

RUN_ON_P 44,45,56,57

IMVP_VR_ON_P 58

C

A A

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2015/10/22 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P32-PWRGD

LA-D891P

1.0

32 65Tuesday, December 20, 2016

1

of

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

8M Rear Camera (WF)

PVT-001.12 0R turn to short pad remove co-layout

WFCAM_CSI2_CLKN1_L

WFCAM_CSI2_CLKP1_L

D D

WFCAM_CSI2_DN4_L

WFCAM_CSI2_DP4_L

WFCAM_CSI2_DN5_L

WFCAM_CSI2_DP5_L

WFCAM_CSI2_DN6_L

C C

WFCAM_CSI2_DP6_L

R20

R19

R16

R13

R12

R9

R18

R17

2

1

0_0402_1%@

12

0_0402_1%@

12

0_0402_1%@

12

0_0402_1%@

12

0_0402_1%@

2

1

0_0402_1%@

2

1

0_0402_1%@

12

0_0402_1%@

WFCAM_CSI2_CLKN15

WFCAM_CSI2_CLKP15

WFCAM_CSI2_DN45

WFCAM_CSI2_DP45

WFCAM_CSI2_DN55

WFCAM_CSI2_DP55

WFCAM_CSI2_DN65

WFCAM_CSI2_DP65

Bypass cap close to CONN

+2.8V_VCM_OUT +2.8V_WF_AVDD +1.8V_WF_DOVDD

1

C14

2

0.1U_0201_10V6K

+1.2V_WF_DVDD

1

C7

2

0.1U_0201_10V6K

WFCAM_CSI2_DN7_L

WFCAM_CSI2_DP7_L

1

C15

2

0.1U_0201_10V6K

1

C10

2

2.2U_0402_6.3V6M

PVT-001.14 0R turn to short pad remove co-layout

R22

R21

1

C16

2

0.1U_0201_10V6K

+2.8V_WF_AVDD

10U_0402_6.3V6M

12

1

2

12

JAE_WP7B-S034VA1

37

GND

35

DMIC4 LRSEL to GND on Module

WFCAM_LED#34

10U_0402_6.3V6M

C210

C211

1

2

0_0402_1%@

C212

12

WFCAM_CSI2_DN75

WFCAM_CSI2_DP75

WFCAM_CSI2_DP7_L WFCAM_CSI2_DN7_L

WFCAM_CSI2_DP6_L WFCAM_CSI2_DN6_L

WFCAM_CSI2_CLKP1_L

WFCAM_CSI2_CLKN1_L

WFCAM_CSI2_DP4_L WFCAM_CSI2_DN4_L

WFCAM_CSI2_DP5_L WFCAM_CSI2_DN5_L

+2.8V_VCM_OUT

GND

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

JWFC1

CONN@

R15 100K_0201_5%

1 2

@

R14 100K_0201_5%

1 2

38

GND

36

GND

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

WF_SENSOR_RST#

2

1

DMIC_CLK34 28

DMIC_DATA34 28

WF_SENSOR_RST#34

WF_HCLK 34

WF_I2C_CLK 34 WF_I2C_DATA3 4

+1.2V_WF_DVDD

+1.8V_WF_DOVDD +2.8V_WF_AVDD +2.8V_VCM_OUT

WFCAM_CSI2_DN5_L WFCAM_CSI2_DP5_L

WFCAM_CSI2_DN4_L WFCAM_CSI2_DP4_L

WFCAM_CSI2_CLKN1_L

WFCAM_CSI2_CLKP1_L

WFCAM_CSI2_DN6_L

WFCAM_CSI2_DP6_L

WFCAM_CSI2_DN7_L WFCAM_CSI2_DP7_L

RA440_0201_5%

+DVDD

R435 0_0201_5%@

1

2

R11

PVT-003.23 0R turn to short pad

ESD8011MUT5G X3DFN2

EMC@

12

D18

1

2

@ 0 _0201_5%

ESD8011MUT5G X3DFN2

EMC@

12

D19

2

1

@RF@

47P_0201_25V8J

2

EMC@

ESD8011MUT5G X3DFN2

12

D14

+5VS

WF_VSYNC 34

C11

ESD8011MUT5G X3DFN2

EMC@

ESD8011MUT5G X3DFN2

EMC@

1

12

D15

D16

2

ESD8011MUT5G X3DFN2

EMC@

ESD8011MUT5G X3DFN2

EMC@

1

D17

2

ESD8011MUT5G X3DFN2

EMC@

ESD8011MUT5G X3DFN2

12

D12

EMC@

12

D13

D10

EMC@

1

D11

2

+1.8VA

UF_I2C_DATA

RH22 .2K_0201_5%

Bypass cap close to CONN

+1.2V_UF_DVDD +3VS_AUDIO +5VS

1

C5

0.1U_0201_10V6K

1

C6

2

0.1U_0201_10V6K

2.2U_0402_6.3V6M

+2.8V_VCM_OUT

R5 100K_0201_5%

1 2

1

C17

2

0.1U_0201_10V6K

1

C18

2

0.1U_0201_10V6K

@

R3 100K_0201_5%

1 2

1

2

0.1U_0201_10V6K

+2.8V_UF_AVDD

1

C3

2

+2.8V_VCM_OUT +1.8V_UF_VDD

1

C1

B B

2

0.1U_0201_10V6K

C2

12

RH12 .2K_0201_5%

12

UF_I2C_CLK

UF_SENSOR_RST#

+2.8V_UF_AVDD

10U_0402_6.3V6M

12

10U_0402_6.3V6M

C208

C4

1

2

C209

12

ALS_I2C1_SCL

ALS_I2C1_SDA ALS_I2C1_ALERT#

PVT-009 improve I2C-Bus SI

RS22 1K_0201_5%

RS23 1K_0201_5%

RS24 1K_0201_5%

12

2

1

2

+3VS +3VS

1

CS10

1U_0201_6.3V6K

2

5M Front Camera (UF)

DF37NC-30DS-0.4V(51)

JUFC1

CONN@

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

HRS_DF37NC-30DS-0P4V(51)

2

4 6

8

10

12 14

16

18 20

22

24 26

28

30

2

4 6

8

10

12 14

16

18 20

22

24 26

28

30

UFCAM_CSI2_DP1_L

UFCAM_CSI2_DN1_L

UFCAM_CSI2_CLKP0_L

UFCAM_CSI2_CLKN0_L

UFCAM_CSI2_DP0_L UFCAM_CSI2_DN0_L

RS25

1 2

@ 0_02 01_5%

RS27

1 2

@ 0_02 01_5%

RS26

1 2

@ 0_02 01_5%

PVT-003.24 0R turn to short pad

ALS_I2C1_SCL8 ALS_I2C1_SDA8

ALS_I2C1_ALERT#8

+3VS

UF_SENSOR_RST#

UF_I2C_DATA UF_I2C_CLK

UFCAM_CSI2_DP1_L UFCAM_CSI2_DN1_L

UFCAM_CSI2_CLKP0_L UFCAM_CSI2_CLKN0_L

UFCAM_CSI2_DP0_L

UFCAM_CSI2_DN0_L

EMC@

ESD8011MUT5G X3DFN2

12

D2

EMC@

ESD8011MUT5G X3DFN2

12

EMC@

12

D4

ESD8011MUT5G X3DFN2

1

D6

2

EMC@

ESD8011MUT5G X3DFN2

12

D7

D8

ESD8011MUT5G X3DFN2

EMC@

1

D9

2

EMC@

ESD8011MUT5G X3DFN2

1

D1

2

EMC@

ESD8011MUT5G X3DFN2

1

D3

D5

2

UFCAM_CSI2_CLKN0_L

UFCAM_CSI2_CLKP0_L

UFCAM_CSI2_DN0_L

UFCAM_CSI2_DP0_L

PVT-001.13 0R turn to short pad remove co-layout

R6

R4

2

R1

2

R2

2

12

0_0402_1%@

1

0_0402_1%@

1

0_0402_1%@

1

0_0402_1%@

UFCAM_CSI2_CLKN05

UFCAM_CSI2_CLKP05

UFCAM_CSI2_DN05

UFCAM_CSI2_DP05

+1.2V_UF_DVDD

+2.8V_UF_AVDD

+1.8V_UF_VDD

UF_SENSOR_RST#34

UF_I2C_DATA8

UF_I2C_CLK8

UF_HCLK34

UFCAM_LED#34

UF_SENSOR_RST#

UF_I2C_DATA

UF_I2C_CLK

+5VS

1 2

R487 5.1K +-1% 0201

PVT-018 R487 chang from 680OHM SD000012S80 to 5.1kOHM SD000008900 for adjust indicator LED to 20lux +-15

A A

UFCAM_CSI2_DN1_L

UFCAM_CSI2_DP1_L

R8

2

1

0_0402_1%@

R7

5

12

0_0402_1%@

UFCAM_CSI2_DN15

UFCAM_CSI2_DP15

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

P33-World/User Camera

LA-D891P

1

33 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

47P_0201_25V8J

@RF@

C69

2

0.01_0603_1%

2

0.01_0603_1%

+1.8V_UF_VDD

47P_0201_25V8J

1

2

1

2

R99

ILEDA

R447

ILEDB

@RF@

C53

+2.8V_VCM_OUT +2.8V_WF_AVDD

+1.8V_IO_OUT

+1.8V_WF_DOVDD

+1.2V_UF_DVDD +1.8V_UF_VDD

R116

1

2

@

0_0603_5%

PVT-003.27 0R turn to short pad

C88

4.7U_0402_6.3V6M

1 2

1

47P_0201_25V8J

1

@RF@

C77

2

+1.2V_WF_DVDD

0_0201_5%

2

0_0201_5%

1

R93

100K_0201_5%

2

+1.2V_UF_DVDD+1.8V_WF_DOVDD +1.8V_IO_OUT

47P_0201_25V8J

1

@RF@

C75

2

D D

C65

1

2

0.1U_0201_10V6K

@EMC@

C57

68P_0201_25V8

1 2

1

+3V_SKYCAM

C79

C80

1

2

0.1U_0201_10V6K

PLL_VDD

WF_I2C_DATA

WF_I2C_CLK

ANA2_EN

UF_SENSOR_RST#_R

WF_SENSOR_RST#_R

STROBE_IN

OSC_IN OSC_OUT

WF_HCLK_R UF_HCLK_R

PLL_COMP1 PLL_COMP2

0_0201_5%

2

0_0201_5%

SKY CAM PMIC

U12

H5

3V3_VDD1

G6

3V3_VDD2

D1

3V3_VDD3

B6

3V3_VDD4

A7

3V3_VDD5

B5

3V3_SUS

A5

PLL_VDD

D3

CPIO0

D6

CPIO1

F6

CPIO2

C3

CPIO3

C4

CPIO4

C6

CPIO5

E6

CPIO6

E4

S_RESETN

E5

S_ENABLE

D4

S_IDLE

C1

S_VSYNC

H2

RESET_IN

D2

S_STROBE

B1

OSC_IN

A1

OSC-OUT

D5

HCLK_A

C5

HCLK_B

A3

PLL_COMP1

A4

PLL_COMP2

G4

I2C_ICA

F4

I2C_ICB

F5

SDA

G5

SCL

TPS68470YFFR_DSBGA56

VCM_OUT

ANA_OUT

IO_OUT

S_IO_OUT

IO_GND

AUX1_OUT

AUX2_OUT

CORE_SW

CORE_FB

CORE_GND

WLED_SW1

WLED_SW2 WLED_SW3

WLED_OUT1 WLED_OUT2

WLED_OUT3

WLED_GND1 WLED_GND2

WLED_GND3

WLED_NTC

DRV_WLED1

DRV_WLED2

ILEDA ILEDB

PLL_GND

GND

H4

B7

E7 D7

F7

C7

A6

CORE_SW

G7

CORE_FB

H6 H7

F1

F2 F3

E1 E2

E3

G1 G2

G3

C2 H1

H3

B2

ILEDA

B3

ILEDB

PLL_GND

B4

A2

R113

R102

R106

R105

R98

L22

1UH_1269AS-H-1R0M-P2_2.5A_ 20%

+3VS_CAM

PVT-003.25

+1.8V_IO_OUT

WF_I2C_DATA

RH242.2K_0201_5%

12

WF_I2C_CLK

RH272.2K_0201_5%

12

+1.8VA

SKYCAM_I2C_DATA

RH262.2K_0201_5%

12

SKYCAM_I2C_CLK

RH252.2K_0201_5%

12

R95

8.2K_0201_5%

1

C52

2

0.01UF_0402_25V7K

1

2

0.01UF_0402_25V7K

@

C71

C62

2

R100

8.2K_0201_5%

R104

18P_0402_50V8J

1

C C

PLL_COMP1

12

1

C56

2

2200P_0402_50V7K

PLL_GND

1

C63

2

2200P_0402_50V7K

PLL_COMP2

12

@

2

1M_0402_5%

Y1

1

234

20MHZ_12PF_7V20000015

WF_HCLK33

UF_HCLK33

OSC_OUTOSC_IN

@

1

C67

2

18P_0402_50V8J

47P_0201_25V8J

0R turn to short pad

R90

1 2

@

0_0603_5%

+3V_PRIM

CAP close to PINA5

EMC@

C50

UF_SENSOR_RST#33

WF_SENSOR_RST#33

1

2

SKYCAM_I2C_DATA8

SKYCAM_I2C_CLK8

to GPP_F I2C2 1.8V

PVT-003.26 0R turn to short pad

WF_VSYNC33

PLT_RST#10,22,23,24,25,27,30,31,43

BLM15HD601SN1D_2P

L20

EMC@

L21

EMC@

BLM15HD601SN1D_2P

EMC@

C49

47P_0201_25V8J

1

C55

C76

1

2

10U_0603_6.3V6M

C64

1 2

PLL_GND

R101

1

R115

1 2

R107 0_0402_5%

1

@

R108 0_0402_5%@

1

2

@EMC@

C58

68P_0201_25V8

SKYCAM_I2C_DATA

SKYCAM_I2C_CLK

C61

1

2

4.7U_0402_6.3V6M

1U_0402_6.3V6K

WF_I2C_DATA33

WF_I2C_CLK33

1

2

4.7U_0402_6.3V6M

2

0_0402_1%@

2

1

2

R477

R478

1

2

1

1 2

1

1 2

47P_0201_25V8J

1

@RF@

C86

2

R92

@

1

0_0201_5%

+2.8V_WF_AVDD+2.8V_VCM_OUT

47P_0201_25V8J

1

@RF@

C66

2

+1.8V_WF_DOVDD

1U_0201_6.3V6M

C72

1

2

+1.8V_IO_OUT

1U_0201_6.3V6M

1

2

+3V_SKYCAM+3V_SKYCAM

1

R91

100K_0201_5%

2

12

R97

0_0201_5%

6

DMN2400UV-7_SOT-563- 6

2

Q9A

1

C78

+1.2V_UF_DVDD

1U_0201_6.3V6M

1

2

+2.8V_VCM_OUT

1U_0201_6.3V6M

1

2

3

Q9B DMN2400UV-7_SOT-563-6

5

4

C70

C87

+1.8V_UF_VDD

1U_0201_6.3V6M

1

2

+2.8V_WF_AVDD

1U_0201_6.3V6M

1

2

UFCAM_LED# 33

C54

C68

R448

@

1

+3V_PRIM

B B

+5VALW

3.3V_CAM_EN

C60

1U_0402_6.3V6K~D

2

1

R442

12

3.3V_CAM_EN8

U11

1 2

3

4

TPS22967DSGR_SON8_2X2

3.3V_CAM_EN

100K_0402_5%~D

0_0603_5%

VIN VIN

ON

VBIAS

VOUT VOUT

GND

2

CT

do not leave floating for U11 pin3

7 8

6

5

9

PVT-003.29

0.01R turn to short pad

R94

0_0603_5%

1

2

@

C51 2200P_0402_25V7K~D

1

2

+3VS_CAM

1

2

C59

0.1U_0402_10V7K

+3V_SKYCAM

+2.8V_UF_AVDD

47P_0201_25V8J

1

@RF@

C45

2

0_0603_5%

560K_0402_5%

470K_0402_5%

+2.8V_UF_AVDD

R78

R77

12

1

C1

R2

1

C43

100P_0402_50V8J

2

R1

2

U9

8

IN

47P_0201_25V8J

1

@RF@

C46

ANA2_EN

2

7

6

5

TPS79801QDGNRQ1_MSOP8

NC

EN

OUT

SENSE/FB

GND

TP

9

NC

1

2

3

4

PVT-003.28 0R turn to short pad

R79

1 2

@

+2.8V_UF_AVDD

1

C44

2

2.2U_0402_6.3V6M

ILEDB

R96

@

2

1

0_0201_5%

1

2

R431

@

100K_0201_5%

R429

@

1

0_0201_5%

+3V_SKYCAM+3V_SKYCAM

12

2

12

6

2

@

1

R430

@

100K_0201_5%

R428

@

0_0201_5%

DMN2400UV-7_SOT-563- 6

Q26A

3

@

DMN2400UV-7_SOT-563-6

5

4

WFCAM_LED# 33

1

2

R434

0_0201_5%

Q26B

R434 pop for EVT R434 de-pop for WF module with LED feature

VOUT = 1.275 V (1 + R2 / R1) + IFB* R2 VFB = 1.275 V IFB= 0.53μA at 25°C

A A

Output Range = 1.275 V to 28 V

A 100-pF capacitor (C1) placed in parallel with R2 of the output divider is necessary

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet of

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

P34-Camera PMIC

LA-D891P

1

34 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

+3.3V_LDO_PD1

EMC@

VCC

CLK

I2C1_DAT_PD1 I2C1_CLK_PD1

I2C1_INT#_PD1

I2C2_DAT_PD1 I2C2_CLK_PD1

I2C2_INT#_PD1

PD1_DEBUG1 PD1_DEBUG2

PD1_DEBUG_CTL1

PD1_DEBUG_CTL2

PD_EE_CS# PD_EE_MISO

PD_HOLD#

PD_EE_WP#

3

2

1 2

+3.3V_LDO_PD1

8

7 6 5 9

SPI ROM 8Mb

1M_0402_5%

PD_HOLD#

PD_EE_CLK

PD_EE_MOSI

UPD1_TD1_PS_SMBDAT30,31,37 UPD1_TD1_PS_SMBCLK30,31,37

UPD1_I2C_ALERT#30

USB20_P1_R

USB20_N1_R

UART_MISO UART_MOSI

+3.3V_LDO_PD1

UT1 TPS65982

TX/RX

RT29 1 0K_0402_5%

1

@

RT25 1 0K_0402_5%

@

RT32 1 0K_0402_5%

@

RT44 1 0K_0402_5%@

RT43 1 0K_0402_5%@

RT42 1 0K_0402_5%

@

RT6 4.7K_0201_ 5%

@

RT7 4.7K_0201_ 5%

D D

C C

PD_EE_CS# PD_EE_MISO

PD_EE_WP#

B B

@

+3.3V_LDO_PD1

USB20_P19

USB20_N19

RT35 4 .7K_0201_5%

RT36 4 .7K_0201_5%

RT47 4 .7K_0201_5%

RT48 4 .7K_0201_5%

RT10 4 .7K_0201_5%

RT49 4 .7K_0201_5%

1 2

3 4

2

1 2

2

1

1 2

1

2

1 2

1

2

1 2

PVT-001.15 Remove co-layout

HCM1012GH900BP_4P

4

1

ML7

RT15

RT18

U22

CS#

HOLD#(IO3)

DO(IO1)

WP#(IO2) GND

W25Q80DVZPIG_WSON8

DI(IO0)

thermal pad

UPD1_TD1_PS_SMBDAT

UPD1_TD1_PS_SMBCLK

UPD1_I2C_ALERT#

+5VALW +5VALW_PD1

RT41 0 _1206_5%

1 2

+3VALW

RT50 0_040 2_5%@

1

RT37 0_040 2_5%

1 2

UPD1_TD1_PS_SMBDAT UPD1_TD1_PS_SMBCLK UPD1_I2C_ALERT#

UPD1_TD1_PS_SMBCLK

UPD1_TD1_PS_SMBDAT

PD1_USBC_AMSEL37 PD1_USBC_EN37

RT2 1K_0201_ 5%

1

CT5

0.1U_0201_10V6K

2

SPI I/F

+3V_LDO

USB2.0 #1

+3VALW_PD1

2

RT30 0_ 0201_5%

1 2

@

RT26 0_ 0201_5%

1

@

RT33 0_ 0201_5%

1 2

@

RT40

1

@ 0 _0201_5%

RT39

1 2

@ 0 _0201_5%

RT38

1 2

@ 0 _0201_5%

PVT-003.31 0R turn to short pad

RT14 1K_ 0201_5%

1 2

RT13 1K_ 0201_5%

1 2

UART_MOSI36

UART_MISO36

RT5 0_0201 _5%

1 2

RT8 0_0201 _5%

1 2

RT3 0_0201 _5%

1

RT4 0_0201 _5%

1 2

2

PD1_LSTX

PVT-003.30 0R turn to short pad

RT107

1

@

0_0603_5%

+5VALW_PD1

+3VALW_PD1

2

TC4

TC5

TC11

TC10

TC8

TC9

TC7

2

+5VALW_PD1

1

2

I2C1_DAT_PD1 I2C1_CLK_PD1 I2C1_INT#_PD1

I2C2_DAT_PD1

I2C2_CLK_PD1

I2C2_INT#_PD1

PD_EE_CLK PD_EE_MOSI

PD_EE_MISO PD_EE_CS#

USB20_P1_R USB20_N1_R

PD1_AUX_P PD1_AUX_N

PD1_LSTX

PD1_DEBUG_CTL1 PD1_DEBUG_CTL2

PD1_DEBUG1 PD1_DEBUG2

PD1_DEBUG3

PD1_DEBUG4

PD1_HWRST41

CT16

4.7U_0402_6.3V6M

A6 A7

A8 B7

A11

C11

B11

D11

H10

B1

H1

D1 D2 C1

A5 B5

B6

A3

B4 A4 B3

K5

G4

F4

E2 F2

K4

E4 D5

K2

K3

F1

RT22 0_0402_5%

1 2

+VBUS1_PD_20V

1

CT17

4.7U_0402_6.3V6M

2

PVT-012.01 Update CPN from SA00009W210 S IC TPS65982DAZQZR BGA 96P POWER SWITCH to SA0000AK400 S IC SN1610042ZQZR BGA 96P POWER SWITCH

UT1

PP_HV PP_HV

PP_5V0

PP_CABLE

VDDIO

VIN_3V3

I2C_SDA1 I2C_SCL1 I2C_IRQ1_N

I2C_SDA2 I2C_SCL2

I2C_IRQ2_N

SPI_CLK

SPI_MOSI SPI_MISO SPI_SS_N

L5

USB_RP_P

USB_RP_N

J1

AUX_P

J2

AUX_N

SWD_CLK SWD_DATA

UART_TX UART_RX

L4

LSTX/R2P LSRX/P2R

DEBUG_CTL1 DEBUG_CTL2

L2

DEBUG1

DEBUG2

L3

DEBUG3 DEBUG4

I2C_ADDR

GND

A1

D6

1

2

GNDE5GND

GND

F5

E6

E7

G5

RT110

100K_0402_5%

1

CT11 1U_0402_25V6K

2

GND

GNDH4GND

B8

E8

D8

H5

GND

GNDF6GNDF7GND

F8

GND

G7

G6

1

CT19 1U_0402_25V6K

2

GND

H8

G8

GNDL1GND

L11

2

+3VALW_PD1

1

CT18

10U_0402_6.3V6M

2

B10

SENSEP

A10

SENSEN

VBUS VBUS VBUS

VBUS

LDO_3V3

LDO_BMC

C_CC1

C_CC2

RPD_G1 RPD_G2

C_SBU1 C_SBU2

GPIO0

GPIO1 GPIO2 GPIO3

GPIO4 GPIO5 GPIO6

GPIO7 GPIO8

MRESET

RESET_N

R_OSC

B9 A9

H11 J10 J11

K11

H2 G1

K1 A2

E1

L9

L10

K9 K10

K6 L6

K7 L7

K8 L8

B2

C2 D10 G11

C10 E10 G10

D7 H6

E11

F11

F10

G2

H7

SS

HV_GATE1 HV_GATE2

VOUT_3V3

LDO_1V8A LDO_1V8D

C_USB_TP C_USB_TN

C_USB_BP C_USB_BN

BUSPOWER_N

SN1610042ZQZR BGA 96P

1

RT109

@

0_0402_5%

+3VALW_PD1

1

CT14

1U_0201_6.3V6K

2

+VBUS1_PD_20V

+3.3V_VOUT_PD1

+3.3V_LDO_PD1 +1.8VA_LDO_PD1 +1.8VD_LDO_PD1

+BMC_LDO_PD1

PD1_CC1 PD1_CC2

CT8 220P_0201_25V7 K

1 2

CT7 220P_0201_25V7 K

1 2

PVT-003.32

PD1_GPIO0

PD1_GPIO1 PD1_GPIO2

PD1_GPIO3 SW_DP2_HPD_UT1 PD1_GPIO5

PD1_GPIO6 PD1_GPIO7 PD1_GPIO8

PD1_GPIO5

0.22U_0402_16V7K

1

2

0R turn to short pad

RT45 0_040 2_1%

RT46 0_040 2_1%

RT28 0_040 2_1%

RT20 0_040 2_1%

RT34 0_040 2_1%

RT31 0_040 2_1%

RT17 0_040 2_1%

RT97 0_040 2_1%

RT11 0_040 2_1%

RT27 0_040 2_1%

RT24 10 K_0402_5%

1 2

RT16 0_ 0402_5%@

1

1 2

1

15K_0402_1%

1

RT21

2

RT19 0_ 0402_5%@

RT23 0_ 0402_5%

CT6

1

CT15

2.2U_0402_6.3V6M

2

RT113 0_0201 _5%

RT114 0_0201 _5%

1 2

@

1

@

1 2

@

1 2

@

1 2

@

1 2

@

1

@

1 2

@

1 2

@

1

@

2

1

1 2

USBC1_TP1_L40 USBC1_TN1_L4 0

USBC1_BP2_L40 USBC1_BN2_L40

2

+3.3V_LDO_PD1

+1.8VD_LDO_PD1

PD1_GPIO8_EXT

+1.8VD_LDO_PD1

1

CT10

2.2U_0402_6.3V6M

2

1

2

USBC1_CC1 40 USBC1_CC2 40

CT12

2.2U_0402_6.3V6M

Dead batery support

PD1_CC1

PD1_CC2

PD1_USBC_POL37

EN_PD_HV1 30,48

TC20

AC1_DISC# 48

SW_DP2_HPD 37,38,41

PD1_OTG_ID 9

TC6

TC17

PD1_GPIO8_EXT

PD1_VBUS_SENSE9

+3.3V_LDO_PD1

10K_0402_1%

12

100K_0402_1%

12

PD1_GPIO1

PD1_GPIO2

RT103

RT104

TC19

RT99 1M_020 1_5%@

RT100 1M_0201 _5%

1 2

+3.3V_VOUT_PD1+BMC_LDO_PD1

1

CT13

1U_0201_6.3V6K

2

ESD8011MUT5G X3DFN2

12

+3.3V_LDO_PD1+1.8VA_LDO_ PD1

1

CT9

10U_0402_6.3V6M

2

ESD8011MUT5G X3DFN2

@EMC@

D96

@EMC@

12

D97

JUSBC1

UE1 MEC1641

UART Share ROM

UV1 PS8743A

SS Signal

For "-D" version only

Factory Set Device Configurations 7 Infinite boot retry from Flash to Host I/F cycles. DIV=RT104/(RT103+RT104) between 0.7~1.0

A A

UPD2_TD2_USH_SMBDAT

UPD2_TD2_USH_SMBCLK

UPD2_I2C_ALERT#

UT2 TPS65982

TX/RX

USB2.0 #3

JUSBC2

UV2 PS8743A

5

SS Signal

4

Security Classification

2041/09/08 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2041/09/08 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Num ber Rev

C

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P35-PD Controller TI

LA-D891P

1

35 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

SENSEP

SENSEN

VBUS VBUS VBUS

VBUS

LDO_3V3

C_CC1 C_CC2

RPD_G1

RPD_G2

C_SBU1

C_SBU2

GPIO0

GPIO1 GPIO2 GPIO3

GPIO4 GPIO5 GPIO6

GPIO7 GPIO8

MRESET

RESET_N

R_OSC

+3.3V_LDO_PD2+1.8VA_LDO_PD2

1

CT31

10U_0402_6.3V6M

2

B10

A10

B9 A9

H11 J10 J11

K11

H2 G1

K1 A2

E1

L9 L10

K9

K10

K6 L6

K7 L7

K8

L8

B2

C2 D10 G11

C10 E10 G10

D7 H6

E11

F11

F10

G2

H7

SS

+VBUS2_PD_20V

+3.3V_VOUT_PD2

+3.3V_LDO_PD2 +1.8VA_LDO_PD2 +1.8VD_LDO_PD2

+BMC_LDO_PD2

PD2_CC1

PD2_CC2

CT26 220P_0201_25V7K

1 2

CT25 220P_0201_25V7K

1

PVT-003.35

PD2_GPIO0

PD2_GPIO1 PD2_GPIO2

PD2_GPIO3 PCH_DP1_HPD_UT2

PD2_GPIO5

PD2_GPIO6 PD2_GPIO7 PD2_GPIO8

5/9 modify from RT55 to RT53

0.22U_0402_16V7K

1

2

0R turn to short pad

RT76 0_040 2_1%

RT75 0_040 2_1%

RT57 0_040 2_1%

RT59 0_040 2_1%

RT51 0_040 2_1%

RT52 0_040 2_1%

RT60 0_040 2_1%

RT98 0_040 2_1%

RT65 0_040 2_1%

RT58 10 K_0402_5%

1 2

RT55 0_ 0402_5%@

1 2

RT54 0_ 0402_5%@

1 2

RT53 0_ 0402_5%

1

15K_0402_1%

12

CT27

RT88

RT115 0_0201 _5%

1

1 2

USBC2_TP1_L40

USBC2_TN1_L4 0

USBC2_BP2_L40 USBC2_BN2_L40

2

@

2

@

2

@

2

@

2

@

PD2_GPIO8_EXT

2

+3.3V_LDO_PD2

+1.8VD_LDO_PD2

RT116 0_0201 _5%

2

1

1 2

1

1 2

2

USBC2_CC1 40 USBC2_CC2 40

Dead batery support

PD2_CC1

PD2_CC2

PD2_USBC_POL37

EN_PD_HV2 48

TC21

AC2_DISC# 48

PCH_DP1_HPD 5,37,41

TC16

TC12

TC18

PD2_GPIO8_EXT

TC22

power side pull down 1M RT101 non-mount

PD2_GPIO1

PD2_GPIO2

+3.3V_LDO_PD2

10K_0402_1%

1

2

100K_0402_1%

1

RT101 1M_ 0201_5%@

1

RT102 1M_ 0201_5%

1 2

RT105

RT106

@EMC@

ESD8011MUT5G X3DFN2

@EMC@

12

D98

2

ESD8011MUT5G X3DFN2

12

D99

GND

GNDE5GND

GND

F5

E6

E7

RT112

100K_0402_5%

+1.8VD_LDO_PD2

1

2

GNDH4GND

GND

B8

D8

H5

G5

CT20

2.2U_0402_6.3V6M

GND

GNDF6GNDF7GND

GND

F8

E8

G7

G6

+3.3V_VOUT_PD2+BMC_LDO_PD2

1

CT28

1U_0201_6.3V6K

2

HV_GATE1 HV_GATE2

VOUT_3V3

LDO_1V8A LDO_1V8D

LDO_BMC

C_USB_TP C_USB_TN

C_USB_BP

C_USB_BN

BUSPOWER_N

GND

GNDL1GND

GND

SN1610042ZQZR BGA 96P

H8

G8

L11

1

RT111

@

0_0402_5%

2

+5VALW +5VALW_PD2

RT56 0_ 1206_5%

1 2

+3VALW

D D

+3.3V_LDO_PD2

C C

USB20_P39

USB20_N39

B B

RT84 0_ 0402_5%

+3V_LDO

1

RT85 0_ 0402_5%@

1 2

RT87 1 0K_0402_5%

1

@

RT86 1 0K_0402_5%

1

@

RT94 1 0K_0402_5%

1

@

RT67 1 0K_0402_5%@

1 2

RT64 1 0K_0402_5%@

1 2

RT62 1 0K_0402_5%

1 2

@

RT81 4 .7K_0201_5%

1

@

RT90 4 .7K_0201_5%

1 2

@

RT83 4 .7K_0201_5%

1

RT79 4 .7K_0201_5%

1 2

PVT-001.16 Remove co-layout

2

HCM1012GH900BP_4P

4

1 2

ML14

+3VALW_PD2

EMC@

I2C1_DAT_PD2_C I2C1_CLK_PD2_C

I2C1_INT#_PD2_C

I2C2_DAT_PD2

I2C2_CLK_PD2

I2C2_INT#_PD2

PD2_DEBUG1 PD2_DEBUG2

PD2_DEBUG_CTL1

PD2_DEBUG_CTL2

3

+5VALW_PD2

+3VALW_PD2

USB20_P3_R

USB20_N3_R

1

CT22

4.7U_0402_6.3V6M

2

1

CT29

10U_0402_6.3V6M

2

+3VALW_PD2

UPD2_TD2_USH_SMBDAT30,37,43

UPD2_TD2_USH_SMBCLK30,37,43

1

CT21

4.7U_0402_6.3V6M

2

1

CT33

1U_0201_6.3V6K

2

UPD2_I2C_ALERT#30

+3.3V_LDO_PD2

+VBUS2_PD_20V

1

CT23 1U_0402_25V6K

2

UPD2_TD2_USH_SMBDAT UPD2_TD2_USH_SMBCLK UPD2_I2C_ALERT#

PVT-003.34 0R turn to short pad

UART_MISO35 UART_MOSI35

UPD2_TD2_USH_SMBCLK

UPD2_TD2_USH_SMBDAT

PD2_USBC_AMSEL37 PD2_USBC_EN37

RT74 1 K_0201_5%

1 2

1

CT24 1U_0402_25V6K

2

PVT-003.33 0R turn to short pad

RT108

1

@

0_0603_5%

+5VALW_PD2

+3VALW_PD2

RT93 0_020 1_5%

1 2

@

RT92 0_020 1_5%

1

1 2

1

@

1

@

1

@

1 2

1

1 2

2

0_0201_5%

2

0_0201_5%

2

0_0201_5%

2

TC15

TC14

TC13

PD2_LSTX

@

RT95 0_020 1_5%

@

RT66

RT63

RT61

RT73 1 00K_0402_5%

RT70 1 00K_0402_5%

RT69 1 00K_0402_5%

RT72 3 .3K_0402_0.5%

RT82 1K_020 1_5%

RT91 1K_020 1_5%

RT80 0_040 2_5%

RT89 0_040 2_5%

RT77 0_040 2_5%

RT78 0_040 2_5%

1

CT30

2.2U_0402_6.3V6M

2

I2C1_DAT_PD2_C I2C1_CLK_PD2_C I2C1_INT#_PD2_C

I2C2_DAT_PD2 I2C2_CLK_PD2

I2C2_INT#_PD2

PD2_EE_CLK PD2_EE_MOSI

PD2_EE_MISO PD2_EE_CS#

USB20_P3_R USB20_N3_R

PD2_AUX_P PD2_AUX_N

PD2_LSTX

PD2_DEBUG_CTL1 PD2_DEBUG_CTL2

PD2_DEBUG1 PD2_DEBUG2

PD2_DEBUG3

PD2_DEBUG4

12

@

0_0402_5%

PD2_HWRST41

1

CT32

2.2U_0402_6.3V6M

2

PVT-012.02 Update CPN from SA00009W210 S IC TPS65982DAZQZR BGA 96P POWER SWITCH to SA0000AK400 S IC SN1610042ZQZR BGA 96P POWER SWITCH

UT2

A6

PP_HV

A7

PP_HV

A8

PP_HV

B7

PP_HV

A11

PP_5V0

C11

PP_5V0

B11

PP_5V0

D11

PP_5V0

H10

PP_CABLE

B1

VDDIO

H1

VIN_3V3

D1

I2C_SDA1

D2

I2C_SCL1

C1

I2C_IRQ1_N

A5

I2C_SDA2

B5

I2C_SCL2

B6

I2C_IRQ2_N

A3

SPI_CLK

B4

SPI_MOSI

A4

SPI_MISO

B3

SPI_SS_N

L5

USB_RP_P

K5

USB_RP_N

J1

AUX_P

J2

AUX_N

G4

SWD_CLK

F4

SWD_DATA

E2

UART_TX

F2

UART_RX

L4

LSTX/R2P

K4

LSRX/P2R

E4

DEBUG_CTL1

D5

DEBUG_CTL2

L2

DEBUG1

K2

DEBUG2

L3

DEBUG3

K3

DEBUG4

F1

I2C_ADDR

RT96

GND

A1

D6

12

A A

Security Classification

2041/09/08 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2041/09/08 2012/07/25

Compal Secret Data

Deciphered Date

2

For "-D" version only

Factory Set Device Configurations 7 Infinite boot retry from Flash to Host I/F cycles. DIV=RT106/(RT105+RT106) between 0.7~1.0

Title

Size Document Num ber Rev

C

Date: Sheet of

Date: Sheet

2

Compal Electronics, Inc.

P36-PD Controller TI

LA-D891P

1

1.0

36 65Tuesday, December 20, 2016

of

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

+3VS_MUX

12

RV60

PARADE@

1K_0201_5%

PARADE@

USB3RP1

USB3RN1

USB3TP1

USB3TN1

USB3RP3

USB3RN4

USB3TP4

USB3TN4

PCH_DDI2_AUXP

DDI2_AUXP

PCH_DDI2_AUXN

DDI2_AUXN

DDPC_HPD1

PCH_DP2_HPD

PCH

DDI1_AUXP

PCH_DDI1_AUXP

DDI1_AUXN PCH_DDI1_AUXN

DDPB_HPD0

PCH_DP1_HPD

+3VS_MUX

12

PARADE@

2

1

RV93 0_0201_5%@

5

3

4

QC3B DMN66D0LDW-7_SOT363-6

RV94 0_0201_5%@

+3VS_MUX

RV29 100_0402_5%

1 2

@

21

LED1 HT-191UD5_AMBER

A

for Debug for Debug

@

61

Q20A DMN2400UV-7_SOT-563-6

2

@

Placement order LED1 LED2 LED3

0.1u

PD 100k

PH 100k

0.1u

PD 100k

PVT-015.02

QC3A

reserve 0R on blocking MOSFET

UPD2_TD2_USH_SMBCLK

6

DMN66D0LDW-7_SOT363-6

1 2

UPD2_TD2_USH_SMBDAT

1

2

SSRXp

SSRXn

SSTXp

SSTXn

SSRXp

SSRXn

SSTXp

SSTXn

U24 PS8338B

PCH_DDI2_AUXP

PCH_DDI2_AUXN

IN_HPD

PD 100k

USBC1_RX1P

UV1

USBC1_RX1N

PS8743A

USBC1_TX1P

USBC1_TX1N

USBC1_RX1P

UV2

USBC1_RX1N

PS8743A

USBC1_TX1P

USBC1_TX1N

OUT1_AUXp_SCL

DDI2_P1_AUXN

OUT1_AUXn_SCL

OUT1_HPD IN_HPD

OUT2_AUXp_SCL

OUT2_AUXn_SCL

0R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION I T CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2

PH 100k

PCH_DP1_HPD_UV2

PCH_DP1_HPD_UT2

UPD2_TD2_USH_SMBCLK 30, 36,43

UPD2_TD2_USH_SMBDAT 30,36,43

+3VS_MUX +3VS_MUX

RV3 100_0402_5%

1 2

@

21

LED2 HT-191UD5_AMBER

A

@

3

Q20B DMN2400UV-7_SOT-563-6

5

4

@

EC_MUX1_FLIP41

2

5

Q21B no use

USB

USBC1_RX1P

JUSBC1

0.1u

PH 100k

USBC1_RX1N

USBC1_TX1P

USBC1_TX1N

USBC2_RX1P

USBC2_RX1N

USBC2_TX1P

USBC2_TX1N

JUSBC2

PH 100k

CABLE

@

0R

PD

@

100k

0R

PD 100k

AUXp

UV2 PS8743A

AUXn

IN_HPD

UT2 TPS65982

PD2_GPIO4

2041/09/08 2012/07/25

0R

WLAN_DP_DAT_AUXP

WIG_HPD

0R

SBU1

USBC2_SBU1

USBC2_SBU2

SBU2

Compal Secret Data

Deciphered Date

0.1u

0.1uWLAN_DP_DAT_AUXN

2M 2M

DDI2_P1_AUXP_CDDI2_P1_AUXP

SW_DP2_HPD_UV1SW_DP2_HPD

PD 100k

SW_DP2_HPD_UT1

ESD ESD

RV9 100_0402_5%

1 2

@

21

LED3 HT-191UD5_AMBER

A

@

for Debug

6

Q21A DMN2400UV-7_SOT-563-6

1

@

3

Q21B DMN2400UV-7_SOT-563-6

4

@

BME dock

AUXp

UV1

AUXnDDI2_P1_AUXN_C

PS8743A

DP_AUXP

JNGFF3

DP_AUXN

WLAN

WIG_HPDOUT2_HPD

UT1 TPS65982

PD1_GPIO4

USBC2_SBU1

JUSBC2

USBC2_SBU2

ESDESD

USBC1_SBU1

JUSBC1

USBC1_SBU2

37 65Tuesday, December 20, 2016

of

SBU1

SBU2

2M 2M

Compal Electronics, Inc.

Title

P37-MUX Re-Driver

Size Document Number Rev

D

LA-D891P

Date: Sheet of

Date: Sheet

Date: Sheet of

1

1.0

12

PARADE@

RV61

0_0402_5%

Parade : pop RV61 TI : pop RV19

1 2

RV19

1

CV61

2

1 2

+3VS_MUX

0_0402_5%

2

1 2

POP RV69,RV70 forTUSB546

+3VS_MUX

1

RV58

1K_0201_5%

0_0402_5%

2.2U_0402_6.3V6M

2

USBC1_RX1P40 USBC1_RX1N 40

USBC1_TX1P40 USBC1_TX1N 40

USBC1_RX2P40

USBC1_RX2N 40

USBC1_TX2P40 USBC1_TX2N 40

USBC1_SBU1 40

USBC1_SBU2 40

TUSB_MUX1_DPEQ1

+3VS_MUX

2

PARADE@

+3VS_MUX

TUSB1_USB_EQ0 TUSB1_USB_EQ1

PD1_USBC_POL35

PD1_USBC_EN35

PD1_USBC_AMSEL35

MUX1_REXT

+3VS_MUX

2

PARADE@

1

RV91 0_0201_5%@

5

34

QC2B DMN66D0LDW-7_SOT363-6

RV92 0_0201_5%@

TUSB1_USB_EQ0 TUSB1_USB_EQ1

PD1_USBC_POL

TUSB1_FLIP

PD1_USBC_EN

TUSB1_USB/AMSL

+3VS_MUX +3VS_MUX +3VS_MUX

POP RV75 forTUSB546

@

1K_0201_5%

1 2

@TI@

1K_0201_5%

1 2

0.1U_0201_10V6K

CV42

1

2

close to UV2

USBC2_RX1P 40 USBC2_RX1N 40

USBC2_TX1P 40 USBC2_TX1N 40

USBC2_RX2P 40 USBC2_RX2N 40

USBC2_TX2P 40 USBC2_TX2N 40

USBC2_SBU1 40 USBC2_SBU2 40

PD2_USBC_POL36

PD2_USBC_EN36

PD2_USBC_AMSEL36

PD2_USBC_POL

PD2_USBC_EN

MUX2_REXT MUX2_TUSB_DPEQ0

TUSB_MUX2_DPEQ1 TUSB_MUX2_SSEQ0TUSB_MUX2_DPEQ0

PVT-015.01 reserve 0R on blocking MOSFET

QC2A

UPD1_TD1_PS_SMBCLK

6

DMN66D0LDW-7_SOT363-6

1 2

UPD1_TD1_PS_SMBDAT

1 2

USBC1 MUX default H/W setting

CE_DP CE_USB FLIP

L L L L H H H H

MUX1_ADDR

TUSB_MUX1_SSEQ1

TUSB1_USB_EQ0

TUSB1_USB_EQ1

USBC1_SBU1

USBC1_SBU2

RV75

MUX1_TUSB_DPEQ0 MUX1_TUSB_SSEQ0

RV76

+1.2V_MUX

0.1U_0201_10V6K

CV60

1

2

USBC2 MUX default H/W setting

CE_DP CE_USB FLIP

L L L L H H H H

TUSB2_FLIP TUSB2_USB/AMSL

POP RV81 forTUSB546

RV81

@

1K_0201_5%

1 2

RV82

@TI@

1K_0201_5%

1 2

TUSB456 Configuration

L L

Power Down

L

H

Power Down

L

H

One Port USB 3.1 - No Flip

H

One Port USB 3.1 - With Flip

L

4 Lane DP - No Flip

L

H

4 Lane DP - With Flip

L

H

One Port USB 3.1 + 2Lane DP -No Flip

H

One Port USB 3.1 + 2Lane DP -With Flip

RV6

PARADE@

RV5

@TI@

RV27 1K_0402_5%@

RV20 1K_0402_5%@TI@

RV28 1K_0402_5%@

RV21 1K_0402_5%@TI@

RV18 2M_0201_5%

RV17 2M_0201_5%

POP RV77 forTUSB546

RV77

@

1K_0201_5%

1 2

TUSB_MUX1_SSEQ0TUSB_MUX1_DPEQ0

RV78

@TI@

1K_0201_5%

1 2

L L L

H L

H H

H

L

H L

H H

H

MUX2_ADDR

TUSB_MUX2_SSEQ1

TUSB2_USB_EQ0

TUSB2_USB_EQ1

PD2_USBC_AMSEL

USBC2_SBU1

USBC2_SBU2

+3VS_MUX +3VS_MUX+3VS_MUX

POP RV83 forTUSB546

@

1K_0201_5%

1 2

2

@TI@

1K_0201_5%

1

3

UPD1_TD1_PS_SMBCLK 30,31,35

UPD1_TD1_PS_SMBDAT 30,31,35

1 2

1

1 2

TUSB456 Configuration

Power Down Power Down One Port USB 3.1 - No Flip One Port USB 3.1 - With Flip 4 Lane DP - No Flip 4 Lane DP - With Flip One Port USB 3.1 + 2Lane DP -No Flip One Port USB 3.1 + 2Lane DP -With Flip

RV83

RV84

+3VS_MUX

4.7K_0402_5%

+3VS_MUX

2

+3VS_MUX

POP RV79 forTUSB546

RV79

@

1K_0201_5%

1 2

RV80

@TI@

1K_0201_5%

1 2

RV32

@

1 2

RV31

1

2

1 2

RV34 1K_0402_5%@

1 2

RV35 1K_0402_5%@TI@

1 2

RV37 1K_0402_5%@

1 2

RV38 1K_0402_5%@TI@

1 2

RV53 1K_0402_5%@

2

1

RV50 1K_0402_5%@TI@

RV47 2M_0201_5%

1

2

RV46 2M_0201_5%

1 2

POP RV85 forTUSB546

@

1K_0201_5%

MUX2_TUSB_SSEQ0

1 2

@TI@

1 2

1K_0201_5%

VESA DisplayPot Alt Mode DFP_D Configuration

+3VS_MUX

4.7K_0402_5%

+3VS_MUX

RV85

RV86

PVT-007.03 improve compatibility with dock

C and E C and E D and F D and F

RV59

PARADE@

1K_0201_5%

MUX2_CSCL

MUX2_CSDA

EC_MUX1_CE_DP41 EC_MUX1_CE_USB41

USB 3.0 AC Coupling Capacitor Topology

PCH

PVT-007.02 improve compatibility with dock

RV57

PARADE@

1K_0201_5%

D D

RV26 pop and RV14 de-pop f or PS8743A RV26 de-pop and RV14 pop f or PS8743B

C C

+3VS_MUX

B B

A A

+3VS_MUX

+1.2V_DDR

PARADE@

DDI2_P1_TXP038 DDI2_P1_TXN038

DDI2_P1_TXP138 DDI2_P1_TXN138

DDI2_P1_TXP238

DDI2_P1_TXN238

DDI2_P1_TXP338 DDI2_P1_TXN338

DDI2_P1_AUXP38 DDI2_P1_AUXN38

USB3RP19 USB3RN19

USB3TP19

USB3TN19

SW_DP2_HPD35,38,41

RV16 100K_0201_5%@

1 2

RV15 100K_0201_5%@

1 2

DDI1_P2_TXP05

DDI1_P2_TXN05

DDI1_P2_TXP15 DDI1_P2_TXN15

DDI1_P2_TXP25 DDI1_P2_TXN25

DDI1_P2_TXP35

DDI1_P2_TXN35

PCH_DDI1_AUXP5

PCH_DDI1_AUXN5

USB3RP49 USB3RN49

USB3TP49 USB3TN49

PCH_DP1_HPD5,36,41

RV45 100K_0201_5%

1 2

RV44 100K_0201_5%

1 2

RV26

1 2

0_0603_5%

+3VS_MUX

RV63 0_0201_5%

RV64 0_0201_5%

DDI2_P1_AUXN_C

DDI2_P1_AUXP_C

+3VS_MUX

12

PARADE@

RV71 0_0402_5%

dePOP RV71 pop RV72 forTUSB546

1

@TI@

RV72 0_0402_5%

2

PCH_DDI1_AUXN_C

PCH_DDI1_AUXP_C

+1.2V_MUX

12

PARADE@

RV73 0_0402_5%

dePOP RV73 pop RV74 forTUSB546

CV36

0.1U_0201_10V6K

1

12

@TI@

RV74

2

0_0402_5%

close to UV1 pin17

CV24 0.1U _0201_10V6K

1

2

CV25 0.1U _0201_10V6K

1 2

CV26 0.1U _0201_10V6K

1

2

CV28 0.1U_0201_10V6K

1

2

CV30 0.1U _0201_10V6K

1 2

CV32 0.1U _0201_10V6K

1

2

CV34 0.1U _0201_10V6K

1 2

CV35 0.1U_0201_10V6K

1 2

CV22 0.1U _0201_10V6K

1 2

CV23 0.1U_0201_10V6K

1 2

CV20 0.1U _0201_10V6K

1 2

CV21 0.1U _0201_10V6K

1 2

RV11 0_0201_5%

1

2

MUX1_REXT

1

2

PVT-017.01 DP PHY solution change 5.62k SD034562180 to8.2k SD000004100

CV57

0.1U_0201_10V6K

1

2

close to UV2 pin17

CV45 0.1U _0201_10V6K

1 2

CV47 0.1U_0201_10V6K

1 2

CV49 0.1U _0201_10V6K

1

2

CV50 0.1U _0201_10V6K

1 2

CV51 0.1U_0201_10V6K

1

2

CV52 0.1U _0201_10V6K

1 2

CV53 0.1U _0201_10V6K

1

2

CV55 0.1U_0201_10V6K

1 2

CV58 0.1U_0201_10V6K

2

1

CV59 0.1U _0201_10V6K

1 2

CV43 0.1U _0201_10V6K

1 2

CV44 0.1U_0201_10V6K

2

1

CV40 0.1U _0201_10V6K

1 2

CV41 0.1U _0201_10V6K

1 2

RV39 0_0201_5%

1 2

MUX2_REXT

12

PVT-017.02 DP PHY solution change 5.62k SD034562180 to 4.7k SD034470180

10U_0402_6.3V6M

CV17

12

+1.2V_MUX

DDI2_P1_TXP0_C

DDI2_P1_TXN0_C

DDI2_P1_TXP1_C DDI2_P1_TXN1_C

DDI2_P1_TXP2_C

DDI2_P1_TXN2_C

DDI2_P1_TXP3_C DDI2_P1_TXN3_C

DDI2_P1_AUXP_C

DDI2_P1_AUXN_C

USB3RP1_C USB3RN1_C

USB3TP1_C

USB3TN1_C

SW_DP2_HPD_UV1

PARADE@

RV7

8.2K +-1% 0402

PCH_DDI1_AUXP_C PCH_DDI1_AUXN_C

PCH_DP1_HPD_UV2

PARADE@

RV30

4.7K +-1% 0402

10U_0402_6.3V6M

CV18

12

DDI1_P2_TXP0_C DDI1_P2_TXN0_C

DDI1_P2_TXP1_C DDI1_P2_TXN1_C

DDI1_P2_TXP2_C DDI1_P2_TXN2_C

DDI1_P2_TXP3_C

DDI1_P2_TXN3_C

USB3RP4_C USB3RN4_C

USB3TP4_C

USB3TN4_C

RV2

1

2

0_0603_5%

PARADE@

UV1

9

ML0p

10

ML0n

12

ML1p

13

ML1n

15

ML2p

16

ML2n

18

ML3p

19

ML3n

24

AUXp

25

AUXn

5

SSRXp

4

SSRXn

8

SSTXp

7

SSTXn

32

IN_HPD

2

REXT

41

Thermal pad

PS8743AQFN40GTR-B0_QFN40_4X6

PARADE@

UV2

9

ML0p

10

ML0n

12

ML1p

13

ML1n

15

ML2p

16

ML2n

18

ML3p

19

ML3n

24

AUXp

25

AUXn

5

SSRXp

4

SSRXn

8

SSTXp

7

SSTXn

32

IN_HPD

2

REXT

41

Thermal pad

PS8743AQFN40GTR-B0_QFN40_4X6

+3VS_MUX+3VS

0.1U_0201_10V6K

CV19

1

2

close to UV1

28

17

VDD_DCI

+1.2V_MUX

28

17

VDD_DCI

+1.2V_MUX

RV14 0_0402_5%@TI@

1

MUX1_CEXT

6

20

1

VDD

RV43 de-pop for 8743A RV42 pop for PS8743B

1

20

VDD

SSDE/DCI_DATA

RX1p

VDD33

RX1n

RX2p RX2n

SBU1

SBU2

CE_USB

CE_DP

I2C_EN

DCICFG/ADDR

CDE/DCI_CLK

SSDE/DCI_DATA

DPEQ/CSCL

CEQ/CSDA

MUX1_I2C_EN

RV42 0_0402_5%@TI@

MUX2_CEXT

6

RX1p

VDD33

RX1n

RX2p RX2n

SBU1

SBU2

CE_USB

CE_DP

I2C_EN

DCICFG/ADDR

CDE/DCI_CLK

DPEQ/CSCL

CEQ/CSDA

30 31

33

TX1p

34

TX1n

40 39

37

TX2p

36

TX2n

27

26

38

FLIP

35

23

29

3

14

11

21 22

1 2

30 31

33

TX1p

34

TX1n

40 39

37

TX2p

36

TX2n

27

26

38

FLIP

35

23

29

3

14

11

21 22

MUX2_I2C_EN

USBC1_TX1P_C

USBC1_TX1N_C

USBC1_TX2P_C USBC1_TX2N_C

PARADE@

USBC2_TX1P_C USBC2_TX1N_C

USBC2_TX2P_C

USBC2_TX2N_C

TUSB2_USB_EQ0

TUSB2_USB_EQ1

1

2

MUX1_TUSB_DPEQ0

MUX1_TUSB_SSEQ0

MUX2_TUSB_DPEQ0 MUX2_TUSB_SSEQ0

PARADE@

MUX1_CSCL

0.1U_0201_10V6K

CV39

MUX1_CSDA

+1.2V_MUX

+3VS_MUX

MUX1_CEXT

@TI@

CV33 0.1U _0201_10V6K

1 2

CV31 0.1U _0201_10V6K

1

2

CV27 0.1U _0201_10V6K

2

1

CV29 0.1U _0201_10V6K

1

2

RV67 0_0201_5%@TI @

1 2

RV68 0_0201_5%@TI @

1

RV87 0_0201_5%PARADE@

1 2

RV88 0_0201_5%PARADE@

1 2

dePOP RV87,RV88

MUX1_I2C_EN

MUX1_ADDR

pop RV67,RV68 forTUSB546

ADDR=High

MUX1_CSCL MUX1_CSDA

RV13

RV12

@

1 2

RV65 0_0201_5%@TI@

RV66 0_0201_5%@TI@

4.7K_0402_5%

Deafult use I2C

+1.2V_MUX

+3VS_MUX

12

PARADE@

Parade : pop RV62 depop-RV43 TI : pop RV43 de-pop RV62

MUX2_CEXT

RV43

@TI@

CV62 2.2U_0402_6.3V6M@TI@

CV56 0.1U _0201_10V6K

1 2

CV54 0.1U_0201_10V6K

1 2

CV46 0.1U _0201_10V6K

1 2

CV48 0.1U_0201_10V6K

1

2

RV90 0_0201_5%PARADE@

RV89 0_0201_5%PARADE@

MUX2_I2C_EN

MUX2_ADDR

RV62 0_0402_5%

1 2

dePOP RV89,RV90 forTUSB546

ADDR=Low

MUX2_CSCL

MUX2_CSDA

RV41

2

1

1 2

4.7K_0402_5%

RV40

@

Deafult use I2C

12

1 2

1

RV69 0_0201_5%@TI@

RV70 0_0201_5%@TI@

5

4

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

2

DP_CFG0

PI0

100K_0201_5%@

DDI2_P1_AUXP37

DDI2_P1_AUXN37

WLAN_DP_CLK_AUXP24 WLAN_DP_DAT_AUXN24

+3VS

Auto test enable; Internal pull down at ~150K?, 3.3V I/O. L: Auto test disable & input offset cancellation enable (default) H: Auto test enable & input offset cancellation enable M: Auto test disable & input offset cancellation disable

Programmable input equalization levels; Internal pull down at ~150K?, 3.3V I/O.

L: default, LEQ, compensate channel loss up to 11.5dB @ HBR2 H: HEQ, compensate channel loss up to 14.5dB @ HBR2 M: LLEQ, compensate channel loss up to 8.5dB @ HBR2

AUX interception disable for Port y (y=1,2) Internal pull down at ~150K?, 3.3V I/O.

L: AUX interception enable, driver configuration is set by link training (default) H: AUX interception disable, driver output with fixed 800mv and 0dB M: AUX interception disable, driver output with fixed 400mv and 0dB

R176 4.7K_0201_5%

+3VS

Chip operational mode configuration;

DP_CFG0 H: Automatic switching mode

DP_CFG1 L: Automatic Power Down enable (default)

PI0

D D

PCH DDI2

L: Automatic EQ enable (default)

Default port

Type-C Port-A

U24

USB Type-C Port-A

MUX+Redriver UV1

USB-C Port-A

USB-C RECEPTACLE

DDI-MUX

WiGig DDI port

JNGFF3

Internal pull down at ~150K?, 3.3V I/O.

L: Control switching mode (default)

H: Automatic switching mode

+3VS

Automatic EQ disable; Internal pull down at ~150K?, 3.3V IO

L: Automatic EQ enable (default)

H: Automatic EQ disable

1 2

R175 4.7K_0201_5%

1

2

WLAN Module

PCH

USB-C Port-B

PCH DDI1 USB-C

MUX+Redriver UV2

C C

U24

R174 0_0402_5%

+3VS

3VS_R

0.01U_0201_10V6K

0.1U_0201_10V6K

1

C184

2

B B

0.01U_0201_10V6K

0.1U_0201_10V6K

C158

1

C187

2

0.01U_0201_10V6K

C157

C218

1

2

+3VS

PCH_DDI2_P05

PCH_DDI2_N05

PCH_DDI2_P15

PCH_DDI2_N15

PCH_DDI2_P25 PCH_DDI2_N25

PCH_DDI2_P35 PCH_DDI2_N35

PCH_DP2_HPD5

CPU_DP2_CTRL_CLK5 CPU_DP2_CTRL_DATA5

PCH_DDI2_AUXP5

PCH_DDI2_AUXN5

R169 4.7K_0201_5%

1 2

@

C162 0.1U_0201_10V6K

1 2

C164 0.1U_0201_10V6K

1

C166 0.1U_0201_10V6K

1

C168 0.1U_0201_10V6K

1 2

C170 0.1U_0201_10V6K

1

C171 0.1U_0201_10V6K

1 2

C173 0.1U_0201_10V6K

1

C181 0.1U_0201_10V6K

1 2

C185 0.1U_0201_10V6K

1

C186 0.1U_0201_10V6K

1 2

2

DP_CFG1

3VS_R

PCH_DDI2_P0_C PCH_DDI2_N0_C

PCH_DDI2_P1_C

PCH_DDI2_N1_C

PCH_DDI2_P2_C PCH_DDI2_N2_C

PCH_DDI2_P3_C PCH_DDI2_N3_C

PI1

PI0

PCH_DDI2_AUXP_C

PCH_DDI2_AUXN_C

DP_CFG0

DP_CFG1

PC10

PC11

PC20

PC21

5

VDD33

21

VDD33

30

VDD33

51

VDD33

57

VDD33

6

IN_D0p

7

IN_D0n

9

IN_D1p

10

IN_D1n

12

IN_D2p

13

IN_D2n

15

IN_D3p

16

IN_D3n

4

IN_CA_DET

3

IN_HPD

2

I2C_CTL_EN

1

Pl1/SCL_CTL

60

Pl0/SDA_CTL

22

IN_DDC_SCL

23

IN_DDC_SDA

24

IN_AUXp

25

IN_AUXn

59

CFG0

58

CFG1

56

PC10

55

PC11

54

PC20

53

PC21

11

GND

19

GND

52

GND

61

PAD(GND)

PS8338BQFN60GTR-A0_QFN60_5X9

USB-C Port-B

RECEPTACLE

OUT1_D0p

OUT1_D0n

OUT1_D1p

OUT1_D1n

OUT1_D2p OUT1_D2n

OUT1_D3p OUT1_D3n

OUT2_D0p

OUT2_D0n

OUT2_D1p OUT2_D1n

OUT2_D2p OUT2_D2n

OUT2_D3p

OUT2_D3n

OUT1_AUXp_SCL

OUT1_AUXn_SDA

OUT2_AUXp_SCL

OUT2_AUXn_SDA

OUT1_CA_DET

OUT1_HPD

OUT2_CA_DET

OUT2_HPD

PEQ

CEXT

REXT

50

49

47

46

45 44

42 41

40

39

37 36

35 34

32

31

26 27

28 29

43

48

33 38

18

SW

8

14

PD

17

20

DP_MUX_SEL pin (U24- pin18)

Port switching control or priority configuration; Internal pull down at ~150K?, 3.3V I/O.

H: Port2 is selected or with higher priority

L: Port1 is selected or with higher priority(default)

DDI2_P1_TXP037

DDI2_P1_TXN037

DDI2_P1_TXP137

PCH_DDI2_AUXP_R PCH_DDI2_AUXN_R

WLAN_DP_CLK_AUXP_R

WLAN_DP_DAT_AUXN_R

OUT1_CA_DET

OUT2_CA_DET

PEQ

C183 2.2U_0402_6.3V6M

CEXT

REXT

1

R191 4.99K_0201_1%

1 2

DDI2_P1_TXN137

DDI2_P1_TXP237

DDI2_P1_TXN237

DDI2_P1_TXP337 DDI2_P1_TXN337

WLAN_DDI2_P024 WLAN_DDI2_N024

WLAN_DDI2_P124 WLAN_DDI2_N124

WLAN_DDI2_P224

WLAN_DDI2_N224

WLAN_DDI2_P324 WLAN_DDI2_N324

R193

R194

R197

R198

SW_DP2_HPD 35,37,41

WIG_HPD_R 24

2

PVT-003.36 0R turn to short pad

1 2

@ 0 _0201_5%

1

2

@ 0 _0201_5%

1 2

@ 0 _0201_5%

1 2

@ 0 _0201_5%

R436

1

type-c Port-A

WIGig

R182 4.7K_0201_5%

1 2

+3VS

R183 4.7K_0201_5%

+3VS

R171 4.7K_0201_5%

+3VS

R178 4.7K_0201_5%

R173 4.7K_0201_5%

+3VS

R180 4.7K_0201_5%

Output swing adjusment for Port y (y=1,2). Internal pull down at ~150K?, 3.3V I/O.

L:default H: +20% M: -16.7%

R170 4.7K_0201_5%

+3VS

R177 4.7K_0201_5%

R172 4.7K_0201_5%

+3VS

R179 4.7K_0201_5%

@

1 2

@

R187 4.7K_0201_5%

1 2

R188 4.7K_0201_5%

1 2

@

1

2

@

1 2

@

2

1

@

1 2

@

1 2

@

1 2

@

1

2

@

PI1

PEQ

PC11

PC21

PC10

PC20

+3VS

PCH_DDI2_AUXN_R WLAN_DP_DAT_AUXN_R

R195

R441

1 2

1

100K_0201_5%

2

100K_0201_5%

AUX_N need Pull UP !! to enable internal AUX CH

PCH_DDI2_AUXP_R WLAN_DP_CLK_AUXP_R

A A

5

4

OUT1_CA_DET

OUT2_CA_DET

R440

R196

R189 1M_0201_5%

R190 1M_0201_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

1

100K_0201_5%

2

100K_0201_5%

1

2

1

2

Compal Secret Data

2015/10/22 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Num ber Rev

C

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P38-DDI WiGig MUX

LA-D891P

1

38 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

D D

4

USB20_P9_PS

USB20_N9_PS

PVT-001.17 Remove co-layout

ML6

4

1

DLW21HN900HQ2L_4P

EMC@

3

2

USB20_P9_CONN

USB20_N9_CONN

close to CONN

2

1

C111 0.1U_0201_10V6K

USB3TP39

USB3TN39

C C

USB3RP39

USB3RN39

1 2

C110 0.1U_0201_10V6K

1 2

+5VALW

10U_0402_6.3V6M

12

C29

USB3TP3_C

USB3TN3_C

1U_0402_6.3V6K

1

C27

2

ML5

1

CMMI21T-670Y-N_4P

EMC@

ML4

EMC@

1

4

CMMI21T-670Y-N_4P

2

34

2

3

2.1A / Channel

USB3TP3_CONN

USB3TN3_CONN

USB3RP3_CONN

USB3RN3_CONN

USB_DET#

USB Power Share

+5VALW

US1

1

IN

USB20_N99

USB20_P99

1 2

B B

USB3_PWR_SHR_VBUS_EN30

+5VALW

R54 10K_0402_5%

R51

1 2

+5VALW

USB_OC2#9

1M_0402_5%@

USB_PWR_SHR_EN#30

R50 100K_0402_5%

USB_ILIM_SEL1

12

2

DM_OUT

3

DP_OUT

13

FAULT#

4

ILIM_SEL

5

EN

6

CTL1

7

CTL2

8

CTL3

TPS2544RTER_W QFN16_3X3

OUT

DP_IN

DM_IN

ILIM_LO

ILIM_HI

GND

GNDP

CTL1 CTL2 CTL3 ILIM_SEL MODE

0 1 1 0 DCP_Auto 0 1 1 1 DCP_Auto

+5V_USB_P1

12

USB20_P9_PS

10

USB20_N9_PS

11

@

T42

15 16

9

NC

14 17

12

R56 30K_0402_1%

PAD~D

USB20_P9_CONN USB20_N9_CONN USB3RP3_CONN

USB3RN3_CONN USB3TP3_CONN USB3TN3_CONN

USB_DET#

close to JUSB1

2.0A

+5V_USB_P1

47U_0805_6.3V6M

C114

1

2

@

1

R449 100K_0402_5%

USB TYPE-A CONN

+5V_USB_P1

JUSB1

1

VBUS

3

D+

2

D-

6

SSRX+

5

SSRX-

9

SSTX+

8

SSTX-

10

DP

4

GND

7

GND

TAIWI_USB036-10B7CRL-TW

CONN@

For ESD request

USB3RN3_CONN

USB3RP3_CONN

USB3TN3_CONN

USB3TP3_CONN

MD1

1

R-

2

R+

3

T-

4

T+

AZ1065-06Q.RDG_MSOP8

EMC@

0.1U_0201_10V6K

C115

C113

1

2

+3VLDO_EC

2

11

GND

12

GND

13

GND

14

GND

+5V_USB_P1

8

VCC

7

GND

D-

D+

6

5

USB20_P9_CONN USB20_N9_CONN

1 1 1 0 SDP 1 1 1 1 CDP

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Num ber Rev

C

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P39-VUBS Provider-Type-A

LA-D891P

1

39 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

+VBUS1_PD_20V

0.1U_0402_25V6

10U_0603_25V6M

1

turn part EVT only DX07SA24XJ2R1000

JUSBC1

A1

GND

A2

SSTXP1

A3

SSTXN1

A4

VBUS

A5

CC1

A6

DP1

A7

DN1

A8

RFU1

A9

VBUS

A10

SSRXN2

A11

SSRXP2

A12

GND

1

GND

2

GND

JAE_DX07S024XJ2

CONN@

EMC@

2

EMC@

2

EMC@

2

EMC@

2

EMC@

TOP

USBC1_RX2N

USBC1_RX2P

USBC1_TX2N

USBC1_TX2P

USBC1_BOT_DP2

GND

SSRXP1

SSRXN1

VBUS

RFU2

DN2

DP2

CC2

VBUS

SSTXN2

Bottom

SSTXP2

GND

1

+VBUS1_PD_20V

2

D52

1 2

ESD8011MUT5G X3DFN2

D53

1

ESD8011MUT5G X3DFN2

D76

1

ESD8011MUT5G X3DFN2

D78

1

ESD8011MUT5G X3DFN2

D69

1 2

ESD8011MUT5G X3DFN2

D72

1

ESD8011MUT5G X3DFN2

D73

1 2

ESD8011MUT5G X3DFN2

D77

1 2

ESD8011MUT5G X3DFN2

D D

USBC1_TX1P37 USBC1_TX1N37

0.47U_0201_25V

USBC1_CC135

USBC1_SBU13 7

0.47U_0201_25V

USBC1_RX2N37 USBC1_RX2P3 7

1

CT2

EMC@

0.1U_0402_25V6

C C

USBC1_TX1P

USBC1_TX1N

USBC1_RX1P

USBC1_RX1N

USBC1_CC1 USBC1_SBU2

B B

USBC1_TOP_DP1 USBC1_BOT_DN2

USBC1_TOP_DN1

USBC1_SBU1 USBC1_CC2

2

D48

1 2

ESD8011MUT5G X3DFN2

D49

1 2

ESD8011MUT5G X3DFN2

D68

1

ESD8011MUT5G X3DFN2

D70

1 2

ESD8011MUT5G X3DFN2

D50

1

ESD8011MUT5G X3DFN2

D74

1 2

ESD8011MUT5G X3DFN2

D75

1 2

ESD8011MUT5G X3DFN2

D51

1 2

ESD8011MUT5G X3DFN2

USBC1_TX1P

USBC1_TX1N

C159

USBC1_CC1

USBC1_TOP_DP1 USBC1_TOP_DN1

USBC1_SBU1

C163

USBC1_RX2N USBC1_RX2P

1

LT1

EMC@

HCB2012KF-121T50_2P

2

EMC@

2

EMC@

2

EMC@

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

4

3

USBC1_BN2_L35

USBC1_BP2_L35

USBC1_TP1_L35

USBC1_TN1_L35

Pin1

+VBUS1_PD_20V

USBC1_RX1P

USBC1_RX1N

1

2

USBC1_SBU2

USBC1_BOT_DN2

USBC1_BOT_DP2

USBC1_CC2

12

USBC1_TX2N

USBC1_TX2P

JUSBC1_GNDJUSBC1_GND

2

C160

0.47U_0201_25V

C161

0.47U_0201_25V

PVT-001.18 Remove co-layout

PVT-001.19 Remove co-layout

USB Type-C Receptacle Interface (Front View)

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12

GND TX1+ TX1- VBUS CC1 D+ D- SBU1 VBUS RX2- RX2+ GND

C165

CT1

2

USBC1_RX1P 37

USBC1_RX1N 37

USBC1_SBU2 37

USBC1_CC2 35

USBC1_TX2N 37 USBC1_TX2P 37

ML9

1

MCM1012B900F06BP_4P

EMC@

ML10

1 2

MCM1012B900F06BP_4P

EMC@

+VBUS1_PD_20V +VBUS2_PD_20V

ESD218-B1-02ELS TSSLP-2-4

D71

12

EMC@

USBC2_TX1P37 USBC2_TX1N37

USBC2_CC136

USBC2_SBU137

USBC2_RX2N37 USBC2_RX2P3 7

CT3

EMC@

0.1U_0402_25V6

2

34

USBC1_BOT_DN2

USBC1_BOT_DP2

USBC1_TOP_DP1

USBC1_TOP_DN1

USBC2_TP1_L36

USBC2_TN1_L36

USBC2_BN2_L36

USBC2_BP2_L36

USBC2_TX1P USBC2_TX1N

0.47U_0201_25V

USBC2_CC1

USBC2_TOP_DP1 USBC2_TOP_DN1

USBC2_SBU1

0.47U_0201_25V

USBC2_RX2N USBC2_RX2P

12

1

2

C195

C192

LT2

HCB2012KF-121T50_2P

PVT-001.20 Remove co-layout

1 2

4

PVT-001.21 Remove co-layout

1 2

4

+VBUS2_PD_20V +VBUS2 _PD_20V

1 2

2

1

JUSBC2_GND

EMC@

ML12

MCM1012B900F06BP_4P

EMC@

ML11

MCM1012B900F06BP_4P

EMC@

turn part EVT only DX07SA24XJ2R1000

JUSBC2

A1

GND

A2

SSTXP1

A3

SSTXN1

A4

VBUS

A5

CC1

A6

DP1

A7

DN1

A8

RFU1

A9

3

VBUS

A10

SSRXN2

A11

SSRXP2

A12

GND

1

GND

2

GND

JAE_DX07S024XJ2

CONN@

USBC2_TOP_DP1

USBC2_TOP_DN1

USBC2_BOT_DN2

USBC2_BOT_DP2

Pin12

TOP

B12

GND

B11

SSRXP1

B10

SSRXN1

B9

VBUS

B8

RFU2

B7

DN2

B6

DP2

B5

CC2

B4

VBUS

B3

SSTXN2

Bottom

B2

SSTXP2

B1

GND

4

GND

3

GND

USBC2_TX1P

USBC2_TX1N

USBC2_RX1P

USBC2_RX1N

USBC2_CC1 USBC2_SBU2

USBC2_TOP_DP1

USBC2_TOP_DN1 USBC2_BOT_DP2

USBC2_SBU1 USBC2_CC2

USBC2_RX1P USBC2_RX1N

2

USBC2_SBU2

USBC2_BOT_DN2

USBC2_BOT_DP2

USBC2_CC2

USBC2_TX2N USBC2_TX2P

JUSBC2_GND

D55

1 2

ESD8011MUT5G X3DFN2

D56

1

ESD8011MUT5G X3DFN2

D80

1

ESD8011MUT5G X3DFN2

D81

1 2

ESD8011MUT5G X3DFN2

D54

1

ESD8011MUT5G X3DFN2

D85

1 2

ESD8011MUT5G X3DFN2

D86

1 2

ESD8011MUT5G X3DFN2

D57

1 2

ESD8011MUT5G X3DFN2

0.1U_0402_25V6

1

2

C199

1

0.47U_0201_25V

C197

12

0.47U_0201_25V

EMC@

+VBUS2_PD_20V

10U_0603_25V6M

1

C202

CT4

2

USBC2_RX1P 37

USBC2_RX1N 37

2

1

2

USBC2_SBU2 37

USBC2_CC2 36

USBC2_TX2N 37

USBC2_TX2P 37

D58

1 2

ESD8011MUT5G X3DFN2

D59

1 2

ESD8011MUT5G X3DFN2

D87

1

ESD8011MUT5G X3DFN2

D88

1 2

ESD8011MUT5G X3DFN2

D79

1

ESD8011MUT5G X3DFN2

D83

1

ESD8011MUT5G X3DFN2

D84

1 2

ESD8011MUT5G X3DFN2

D89

1 2

ESD8011MUT5G X3DFN2

ESD218-B1-02ELS TSSLP-2-4

EMC@

D82

EMC@

USBC2_RX2N

USBC2_RX2P

USBC2_TX2N

2

USBC2_TX2P

2

USBC2_BOT_DN2

2

GND RX1+ RX1- VBUS SBU2 D- D+ CC2 VBUS TX2- TX2+ GND

B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

Printed Circuit Board

Pin24

Pin13

A A

Security Classification

2015/10/22 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Num ber Rev

C

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P40-TYPE-C USBC1/2

LA-D891P

1

40 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

Tunnable IC

JANT7 EMI_Spring

D D

+3VALW +3V_RF

R82

1 2

+3V_RF

0_0201_5%

L80

1 2

C47

1 2

4.3P_0402_50V8

1

2

1.8NH +-0.1NH LQP03TN1N8B02D

R81

C48

0.1U_0201_10V6K

1 2

0_0201_5%

1

2

3

4

CONN@

U10

RF1

RF2

GND_01

VDD

1

10

L13 22NH_LQG15HS22NJ02D_5%@

9

RF3

COM

RF4

GND_02

GPIO1

GPIO0

5

EC646_LGA10_1P1X1P5

L16 BLM15AG121SN1D_L0402_2P

1 2

L14 22NH_LQG15HS22NJ02D_5%

8

1 2

7

L17 BLM15AG121SN1D_L0402_2P

1 2

6

ANTCTRL1_L

ANTCTRL0_L

+3V_RF

R87

1 2

R86

1 2

+3V_RF

0_0201_5%

RF conn for WWAN

L81

1 2

1.8NH +-0.1NH LQP03TN1N8B02D

@

C9

2P_0201_25V8B

12

50OHM traces50OHM traces

@

C1039

2P_0201_25V8B

12

ANTCTRL1 25

ANTCTRL0 25

JANT3

2

GND_2

3

GND_3

4

GND_4

BELLW_10093-1021

CONN@

1

JANT2

1

EMI_Spring

CONN@

Truth Table

C C

GPIO0 GPIO0 RF1 RF2 RF3 RF4

L L L H H H

H L

ON

OFF OFF OFF

ON

OFF OFF OFF

OFF OFF

ON

OFF

OFF OFF OFF

ON

ANTCTRL1_L

12

@

12

@

R83

0_0201_5%

R85

0_0201_5%

ANTCTRL0_L

12

@

12

@

R88

0_0201_5%

R84

0_0201_5%

I/O Expander

+3V_LDO +3V_LDO_ 23017

B B

+3V_LDO_23017

12

R474 10K_0402_5%

USH_DET_IOEXP

R480

USH_DET#5,43

220K_0201_5%

12

@

A A

2

B

E

3 1

R481 300K_0201_5%

C

MMBT3904WH_SOT323-3 Q31

USH_DET_IOEXP H = USH present L = USH not present

CHG_MCP23017_SMBDAT30,51 CHG_MCP23017_SMBCLK30,51

Device Address: b 0,1,0,0,A2,A1,A0,0 0x42

+3V_LDO_23017

EC_MUX1_CE_DP37

EC_MUX1_CE_USB37

EC_MUX1_FLIP37

m3042_PCIE#_SATA9

WWAN_OFF_EC#25

PD1_HWRST35 PD2_HWRST36

R422 0_0402_5%

R423 0_0402_5%

Ensure rise time within 66ms. (fast than 0.05V/ms)

R470 0_0402_5%@

1

R471 0_0402_5%@

1 2

RE74 10K_0402_5%

1 2

RE75 10K_0402_5%

1 2

RE76 10K_0402_5%

1 2

RE73 10K_0402_5%

R132 0_0402_5%

1 2

10U_0603_6.3V6M

12

CE33

USH_DET_IOEXP

2

UE2

4

GPB7

3

GPB6

2

GPB5

1

GPB4

28

GPB3

27

GPB2

26

GPB1

25

GPB0

9

SDA

8

SCL

16

INTA

15

INTB

11

A0

12

A1

13

A2

14

RESET

MCP23017T-E-ML_QFN28_6X6

5

VDD

GPA0 GPA1

GPA2 GPA3 GPA4

GPA5 GPA6 GPA7

NC/SO

ThermalPad

VSS(Ground)

0.1U_0402_25V6

12

CE35

CE34

PVT-010 Add HPD signal tie to EC

17 18

19 20 21

22 23 24

10

7

NC

29

6

for external monitor enable power button

R475 0_0402_5%

1

1 2

2

R476 0_0402_5%

R491 0_0402_5%@

PVT-013.01 add thermal pad for use

SATA_LED_EN42

SW_DP2_HPD 35,37,38

PCH_DP1_HPD 5,36,37 +VBUS1_ESD 51

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2011/06/02 2013/10/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P41-RF Tunable IC / I/O Expander

LA-D891P

1

41 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

A

smd.db-x7.ru

B

+3VLDO_EC

C

D

+3VLDO_EC

E

RE118 100K_0201_5%@

1 2

SCREW HOLE

KICKSTD_SW_DET#8,30

1

@

H_2P3

@

H_2P3

@

H_3P3

@

H_6P0N

1

FD3 FIDUCIAL

@

H2

H7

H11

H15

1

FD1 FIDUCAL

1 1

2 2

@

H1

H6

H10

H14

for WLAN/WWAN

CLIP1

EMI_Spring

CONN@

1

@

H_2P3

@

H_4P0

@

H_3P3

@

H_6P0N

FD2 FIDUCAL

@

H3

H8

H5

CLIP2

EMI_Spring

CONN@

1

@

H_2P3

@

H_4P0

@

H_3P3

1

@

1

FD4 FIDUCIAL

1

H4

H_2P3

1

H9

H_2P3

1

H13

H_3P3

1

@

CLIP13

EMI_Spring

CONN@

H12

1

@

H_3P6

1

H16

1

@

H_1P5N

H17

1

@

H_1P5N

KICKSTD_SW_DET#

EC_IN_VOLUMEUP#30

EC_IN_VOLUMEDOWN#30

Kickstand detect SW

KICKSTD_SW_DET#

R488

1 2

100K_0201_5%

Volume Up Button

Volume Down Button

R23 1K_0201_5%

1 2

0.1U_0201_10V6K

C19

1

2

ESD207-B1-02EL_TSLP-2-19-2

PU 10K resistor locate on EC side

R24 1K_0201_5%

1

0.1U_0201_10V6K

C20

1

2

ESD207-B1-02EL_TSLP-2-19-2

2

4

1

3

VOLUME_UP#

VOLUME_DOWN#

SW5 BTE-PQR2_4P

D20

EMC@

D21

EMC@

12

RE123 10K_0201_5%

R490

1 2

100K_0201_5%

@

SW1 TAFG3-12WQR_3P

2

SW2 TAFG3-12WQR_3P

2

7

6

Deafult

5

467

4

5

Close

High

POP RE123,R488

Open

Close

Open

1

3

1

3

de-pop RE118,R490

Low

de-POP RE123,R488 POP RE118,R490

High

for cable routing

CLIP3

1

EMI_Spring

CONN@

CLIP8

1

EMI_Spring

CONN@

3 3

for M.2 SSD/WLAN/WWAN shielding clip

+3.3V_TBAT_LDO

W=20mils

RTCD2

4 4

1 2

CLIP4

1

EMI_Spring

CONN@

CLIP9

1

EMI_Spring

CONN@

1

+3V_LDO +RTCBATT

W=20mils W=20mils

RTCD1

BAT54HT1G_SOD323-2

W=20mils

A

1 2

BAT54HT1G_SOD323-2

1

C112 1U_0402_6.3V6K

2

CLIP5

EMI_Spring

CONN@

CLIP10

EMI_Spring

CONN@

RTCR1

1.2K_0402_5%

1 2

1

CLIP6

1

EMI_Spring

CONN@

CLIP11

EMI_Spring

CONN@

1

+RTCVCC

CLIP7

1

EMI_Spring

CONN@

CLIP12

1

EMI_Spring

CONN@

1

CLIP14

EMI_Spring

CONN@

1

SATA LED

+3VS

12

@

RE108

100K_0402_5%

SATA_LED_EN41

G

2

RH502

RTC

+RTCBATT

B

JRTC1

1

2

3

G1

4

G2

ACES_50278-00201-001

CONN@

SSD_LED#23

SATA_LED#9

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2015/10/22 2013/10/28

Compal Secret Data

@

RH503

@

Deciphered Date

D

12

0_0201_5%

1

2

0_0201_5%

S

RH504

@

13

D

DII-DMN65D8LW-7 Q28

@

12

0_0201_5%

Title

P42-RTC, VOL SW, SCREWH

Size Document Num ber Rev

LA-D891P

Date: Sheet of

Date: Sheet

PWR_LED# 30,43

Compal Electronics, Inc.

42 65Tuesday, December 20, 2016

E

42 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

D D

+5VS

B+

USH_I2C_ALERT#30

USH_RST#30

USH_PWR_STATE#30

CONTACTLESS_DET#11

SUS_ON_EC30,32,45,54

FP_POA_WAKE#30 FP_POA_EN30 CHG_LED#30

PWR_LED#30,42

UPD2_TD2_USH_SMBCLK30,36,37

UPD2_TD2_USH_SMBDAT30,36 ,37

C C

UPD2_TD2_USH_SMBCLK UPD2_TD2_USH_SMBDAT

HOME_KEY#

10P_0201_25V8

1

2

+5VD

USH_I2C_ALERT# USH_RST#

USH_PWR_STATE#

CONTACTLESS_DET# SUS_ON_EC

FP_POA_WAKE# FP_POA_EN CHG_LED#

PWR_LED# UPD2_TD2_USH_SMBCLK UPD2_TD2_USH_SMBDAT

10P_0201_25V8

@EMC@

1

C220

C219

2

+3VALW+3VS

JIO1

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

GND141GND2

43

GND3

JAE_WP7B-S040VA1-R6000

CONN@

10P_0201_25V8

@EMC@

1

2

0.3A per pin follow 3/29 USH pin-define

C221

GND4

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

HOME_KEY# PWR_SW_IN#

LID_CL_SIO#

REM_DIODE3_N 30

REM_DIODE3_P30

HOME_KEY# 30 PWR_SW_IN#30,49

LID_CL_SIO#3 0

USB20_P10 9 USB20_N10 9

USH_DET# 5,41

Docking CONN

JIO2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

3030GND

ACES_51522-03001-P01

CONN@

BASE_SMBCLK30 BASE_SMBDAT30

+AC_DOCK_IN_20V

BASE_SMBCLK

BASE_SMBDAT

4/15 add pin2 to GND

DET_R

BASE_SMBCLK

BASE_SMBDAT

BASE_SMB_ALERT#

DET_L#

BASE_SMB_ALERT#3 0

+5V_DOCK

DET_R48

USB20_N29 USB20_P29

DET_L#30,48

2A

check current rating

10P_0201_25V8

1

2

@EMC@

1

C223

C222

2

GND

FAN CONN

+3VS

PVT-003.37 0R turn to short pad

R443

1 2

+3VALW

R444 0_0402_5%@

1 2

FAN1_PWM30

FAN1_TACH30

31

32

+3V_FAN

0_0402_1%@

+3V_FAN

R27

R28

10K_0402_5%~D

@

10K_0402_5%~D

1 2

RB751S40T1G_SOD523-2

D22

+5VS

PVT-003.38 0R turn to short pad

R445

1 2

+5VD

R446 0_0402_5%@

1 2

12

+5V_FAN

0_0402_1%@

+5V_FAN

0_0402_5%

10K_0402_5%~D

@

12

R29

1 2

R438

2

1

C21

0.1U_0402_25V6K~D

JFAN1

6

G2

5

G1

4

3

2

1

CONN@

ACES_50224-00401-001

USH CONN

UART

LPC

IR CAM CONN

2

0_0603_5%

+5VALW_IR

JIR1

1

2

3

4

5

6

7

8

9

10

11

12

13

GND

14

GND

ACES_50208-01201-P01

CONN@

PVT-003.40

+3VALW

B B

+3VS_IR

USB20_P59

A A

USB20_N59

DMG2301U-7_SOT23-3

2

C236

0.1U_0201_10V6K

1

0.1U_0201_10V6K

10U_0402_6.3V6M

1

C1035

2

PVT-001.22 Remove co-layout

ML3

1

4

DLW21HN900HQ2L_4P

QZ9

D

S

3

G

2

3.3V_IRCAM_EN#

0.1U_0201_10V6K

68P_0402_50V8J

1

12

C1037

C1036

2

EMC@

2

3

+3VS_IR_R

1

EMC@

C1034

PVT-003.39 0R turn to short pad

R223

1 2

@

0_0603_5%

3.3V_IRCAM_EN#10

USB20_P5_CONN

USB20_N5_CONN

+3VS_IR

+5VALW

CAM_CBL_DET#11

+3VS_IR

0R turn to short pad

R266

1

@

USB20_P5_CONN

USB20_N5_CONN

BIOS debug

JUART

UART2_RTS#8

UART2_TXD8

UART2_RXD8

UART2_CTS#8

1

2

3

4

5

GND

6

GND

CVILU_CI1804M1VRA-NH

CONN@

BIOS debug

+3VS

JLPDE1

1

2

LPC_AD07,30 LPC_AD17,30

LPC_AD27,30 LPC_AD37,30 LPC_FRAME#7,30

PLT_RST#10,22,23,24,25,27,30,31,34

CLK_LPC_DEBUG7

3

4

5

6

7

8

9

10

11

GND1

12

GND2

ACES_50521-01041-P01

CONN@

Security Classification

2015/10/22 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

P43-IOB CONN/IR CAM

LA-D891P

1

43 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

+5V RUN Touch Screen Load Switch

RUN_ON_P

C22

1U_0402_6.3V6K~D

12

100K_0402_5%~D@

R31

RUN_ON_P32,44,45,56,57

+5VALW

1 2

D D

Deeper Sleep, SSD Load Switch +5V Audio , 3V Run

C124

1U_0402_6.3V6K~D

12

PCH_PWR_EN_R

C C

SSD_PWR_EN11

R146

R151

SSD_PWR_EN

RUN_ON_P

1 2

PCH_PWR_EN30 SIO_SLP_SUS#10,30,32,44,55,56,57

R150

@

1

R149

100K_0402_5%~D

+5VALW

1 2

C132

R148 0_0402_5%

@

R147 0_0402_5%

0_0402_5%

2

12

1U_0402_6.3V6K~D

PCH_PWR_EN

SSD_PWR_EN

1 2

1

+5VD

U2

1

VIN

2

VIN

3

ON

4

VBIAS

TPS22967DSGR_SON8_2X2

RUN_ON_P

+3VALW +3V_PRIM

U21

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

AOZ1331_DFN_14P

2

PCH_PWR_EN_R

VOUT VOUT

CT

GND GND

VOUT1

CT1

GND

CT2

VOUT2

GPAD

7 8

6

5 9

14

13

12

11

10

9

8

15

PVT-003.41

0.01R turn to short pad

R30

0_0603_5%

1 2

@

C24

1 2

2200P_0402_25V7K~D

PVT-003.42

0.01R turn to short pad

R145

0_0805_5%

1 2

@

C127

1000P_0402_50V7K~D

1 2

C129 2200P_0402_25V7K~D

1 2

R152

0_0805_5%

1 2

@

PVT-003.43

0.01R turn to short pad

+5VS

+3.3VDX_SSD

Card Reader Load Switch

C203

1

2

C23

0.1U_0402_10V7K

1

2

+3V_PRIM

+3.3VDX_SSD

1

C503

0.1U_0402_10V7K

2

1

C126

0.1U_0402_10V7K

2

1

C131

0.1U_0402_10V7K

2

C504

0.1U_0402_10V7K

+3VS

R210

R209

R211

R117

+3VS

1 2

R110

R109

3.3V_TS_EN8

SD_PWR_EN11

12

AUD_PWR_EN30

RUN_ON_P32,44,45,56,57

C96

12

1U_0402_6.3V6K~D

+5VALW

100K_0402_5%~D

100K_0402_5%~D@

C90

1U_0402_6.3V6K~D

AUD_PWR_EN

RUN_ON_P

2

1

1U_0402_6.3V6K~D

100K_0402_5%~D@

12

100K_0402_5%~D

12

100K_0402_5%~D@

3.3V_TS_EN

SD_PWR_EN

+5VALW

+3VALW

SD_PWR_EN

3.3V_TS_EN

SD_PWR_EN

12

+3VALW

RUN_ON_P

AUD_PWR_EN AUD_PWR_EN

+5VALW

1

2

3

4

5

6

7

UZ4

VIN1

ON1

VBIAS

ON2

VIN2

AOZ1331_DFN_14P

1

2

3

4

5

6

7

VOUT1

CT1

GND

CT2

VOUT2

GPAD

U13

VIN1

ON1

VBIAS

ON2

VIN2

AOZ1331_DFN_14P

VOUT1

CT1

GND

CT2

VOUT2

GPAD

+3VS_TS

+3VS_CR

+5VS_AUDIO

+3VS

1

C194

0.1U_0402_10V7K

2

1

C198

0.1U_0402_10V7K

2

+5VS_AUDIO

1

C89

0.1U_0402_10V7K

2

+3VS

1

C95

0.1U_0402_10V7K

2

0_0603_5%

@

0_0603_5%

@

+3VS_TS

+3VS_CR

PVT-003.45

0.01R turn to short pad

14

13

12

11

10

9

8

15

14

13

12

11

10

9

8

15

R204

1 2

@

2200P_0402_25V7K~D

C200

1

C201 2200P_0402_25V7K~D

1

R205

1 2

@

PVT-003.46

0.01R turn to short pad

PVT-003.47

0.01R turn to short pad

1 2

C91

1 2

C92 2200P_0402_25V7K~D

1 2

PVT-003.48

0.01R turn to short pad

2

R114

220P_0402_50V8K

R119

WLAN/WWAN Load Switch 3V_Audio, 1.8V_Audio Load Switch

C117

1U_0402_6.3V6K~D

AUX_EN_WLAN30

3.3V_NGFF1_EN30

B B

NGFF_WWAN_PWREN11

BAT54CW-7-F_SOT323-3

R216

1

R139

1 2

D61

2

3

2

100K_0402_5%~D

AUX_EN_WLAN

+5VALW

WWAN_EN

1

C121

1U_0402_6.3V6K~D

WWAN_EN

AUX_EN_WLAN

+3VALW +3VS_WLAN

U17

12

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

AOZ1331_DFN_14P

+1.8VA

VOUT1

CT1

GND

CT2

VOUT2

GPAD

14

13

12

11

10

9

8

15

PVT-003.44

0.01R turn to short pad

R140

1 2

@

2200P_0402_25V7K~D

C119

1 2

C118 2200P_0402_25V7K~D

1 2

L31

1

BLM18SG221TN1D_2P

L32

1 2

BLM18SG221TN1D_2P

+1.8VA

0_0805_5%

2

+1.8VA Discharge

12

B+

12

R473

200K_0402_1%

A A

DMN66D0LDW-7_SOT363-6

6

SIO_SLP_SUS#10,30,32,44,55,56,57

5

2

1

5

QE13A

R472

80.6_0402_1%~D

DMN66D0LDW-7_SOT363-6

34

QE13B

1

C500

2

4

1

C501

0.1U_0402_10V7K

2

1

C502

0.1U_0402_10V7K

2

+3VS_WLAN

1

C120

0.1U_0402_10V7K

2

+3VS_WWAN+3VS_WWAN

1

C116

0.1U_0402_10V7K

2

+3VALW

1

@

1U_0402_6.3V6K~D

2

place close to

C205

C93

1U_0402_6.3V6K~D

12

AUD_PWR_EN

+5VALW

AUD_PWR_EN

C94

1U_0402_6.3V6K~D

2

1

+3VALW

U16 pin1

R218

AUD_PWR_EN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

3

@

1 2

0_0402_5%

2013/07/04 2013/10/28

1

C206

@

220P_0402_50V8K

2

Compal Secret Data

12

R217

@

100K_0402_5%~D

Deciphered Date

+3VALW +3VS_AUDIO

+1.8VA

U16

@

1

2

3

OUT

IN

GND

SHDN

SET

G916T1UF_SOT23-5

U14

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

AOZ1331_DFN_14P

5

4

@

VOUT1

CT1

GND

CT2

VOUT2

GPAD

R425

0.01_0603_1%

1 2

1

R215

@

49.9K_0402_1%

2

14

13

12

11

10

9

8

15

PVT-003.49

0.01R turn to short pad

R111

0_0603_5%

1 2

@

1000P_0402_50V7K~D

C84

2

1

2

1

C85 4700P_0402_25V7K

1 2

R112

0_0603_5%

1

PVT-003.50

0.01R turn to short pad

R214

@

10K_0402_1%

2

@

Vout = 1.25*(1+R214/R215)

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

P44-DC/DC Interface 1

Size Document Number Rev

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

LA-D891P

+1.8VS_AUDIO

+1.5VS_AUDIO

+3VS_AUDIO

1

C81

0.1U_0402_10V7K

2

+1.8VS_AUDIO

1

C82

0.1U_0402_10V7K

2

+1.5VS_AUDIO

4.7U_0402_6.3V6M

1

2

1

C207

@

1.0

44 65Tuesday, December 20, 2016

of

Vinaﬁx.com

A

smd.db-x7.ru

B

C

D

E

+1.0V_VCCST source

+1.0VA

UZ3

1

1 1

1U_0402_6.3V6K

1

CZ8

2

+5VALW

VCCST_EN32

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

VOUT

GND

PVT-003.51

0.01R turn to short pad

R118

1 2

6

5

@

0_0603_5%

+1.0V_VCCST

1

2

CZ5

0.1U_0402_10V7K

BEAVER CREEK:

4.4mohm/6A TR=12.5us@Vin=1.05V

+3V_PRIM

PVT-014.05

U4245

5

SUS_ON_EC30,32,43,54

XDP_PRSENT13

2 2

SUS_ON_EC

XDP_PRSENT

@XDP@

1

P

INB

2

INA

G

MC74VHC1G32DFT2G_SC70-5

3

de-pop debug XDP related resistor pop by using Memo

@

R427 0_0402_5%

4

O

1

+3VALW

2

VCCST_EN

5

1

SIO_SLP_S0#10,31,57

RUN_ON_P32,44,56,57

UC2

TC7SH08FU_SSOP5

P

B

2

A

G

3

+VCCPLL_OC source

+VCCPLL_OC

+1.2V_DDR

UZ1

1

VIN1

2

VIN2

1U_0402_6.3V6K

1

CZ3

2

VCCSTG_EN

3 3

+5VALW

RZ1

1 2

0_0402_5%

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

VOUT

GND

PVT-003.55

0.01R turn to short pad

6

5

R48

1 2

0_0603_5%

@

+VCCPLL_OC

+1.0V_MPHYGT source

+1.0V_MPHYGT

+1.0VA

1

2

PVT-003.52

0.01R turn to short pad

CZ7

1U_0402_6.3V6K

R120

0_0603_5%

1 2

@

RH32

+1.0V_MPHYGT

12

100K_0402_5%~D@

1

CZ10

2

0.1U_0402_10V7K

MPHYP_PWR_EN10

1

CZ2

2

+1.0V_MPHYGT

1

CZ9

2

@

0.1U_0402_10V7K

+5V_Dock source

+5VD

R74 100K_0201_5%

1

C39

1U_0402_6.3V6K~D

2

R73 100K_0201_5%

1 2

0.1U_0402_10V7K

1 2

DOCK_PWR_EN30

DOCK_PWR_EN

+1.0V_VCCSTG source

+1.0VA

UZ2

1

VIN1

2

+5VALW

1U_0402_6.3V6K

1

CZ6

2

VCCSTG_EN

4

O

1

2

U7

5

IN

3

FLAG

4

EN(#EN)

G517G1TO1U_TSOT23-5

0.1U_0402_10V7K

CZ4

1

@

2

RZ2

100K_0402_5%

1

OUT

2

GND

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

BEAVER CREEK:

4.4mohm/6A TR=12.5us@Vin=1.05V

VCCSTG_EN 57

SIO_SLP_S0#

RUN_ON_EC

PVT-003.54

0.01R turn to short pad

R72

1 2

@

0_0805_5%

PVT-003.53

0.01R turn to short pad

R26

0_0402_5%

1 2

VOUT

GND

6

5

@

+1.0V_VCCSTG

S0 S0Ix S3

low

high

1

C37

0.1U_0402_10V7K

2

high

1

C38 22U_0805_10V6M

2

+1.0V_VCCSTG

1

CZ1

2

0.1U_0402_10V7K

lowhigh

low

+5V_DOCK

4 4

DELL CONFIDENTIAL/PROPRIETARY

Security Classification

2013/07/04 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

A

B

2013/07/04 2013/10/28

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

P45-DC/DC Interface 2

Size Document Number Rev

Date: Sheet of

Date: Sheet

D

Date: Sheet of

Compal Electronics, Inc.

LA-D891P

1.0

45 65Tuesday, December 20, 2016

E

of

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

Pebble Creek Power Block - Tablet

+3V_LDO

D D

(RT9069)

2S/3S Battery

B+

LCD driver TPS61188

INV_PWM

IFB1~IFB8

EC

Type-C Port-A

Type-C Port-B

C C

Base Wireless Charger

PD1 Controller

PD2 Controller

B+

Power Path

B+

+VCC_CORE: 32A +VCC_GT: 31A +VCC_SA: 4.5A

(ISL95857)

Charger ISL88738 (NVDC)

B+

+3VALW TDC: 5.21A (NB680)

+5VALW TDC: 2.55A (NB679)

U8 SY6288

U21 AOZ1331

U17 AOZ1331

UZ4 AOZ1331

U21 AOZ1331

U11 APE8937

U13 AOZ1331

US1 TPS2544

ENVDD

PCH_PWR_EN_R

RUN_ON_P

AUX_EN_WLAN

WWAN_EN

3.3V_TS_EN

SD_PWR_EN

AUD_PWR_EN

3.3V_CAM_EN#

RUN_ON_P

AUD_PWR_EN

USB3_PWR_SHR_VBUS_EN

+LCDVDD

+3V_PRIM

+3.3VDX_SSD

+3VS_WLAN

+3VS_WW AN

+3VS_TS

+3VS_CR

+3VS_AUDIO

+3VS_CAM

+3VS

+5VS_AUDIO

+5V_USB_P1

B B

Vcore Power Rail

Audio Power Rail

A A

+1.0VS_VCCIO TDC 2.17A (TPS62134A)

+1.0V_PRIM TDC 1.79A (TPS62134D)

+1.8VU TDC 0.19A (TLV62150)

+1.8VA TDC 0.31A (TLV62150)

+1.2V_DDR TDC 3.2A (NB685)

+1.0VA TDC 2.87A (SY8286RAC)

VCCSTG_EN

SIO_SLP_SUS#

SUS_ON_P

SIO_SLP_SUS#

SUS_ON_EC

SIO_SLP_SUS#

+1.0VS_VCCIO

+1.0V_PRIM_CORE

+1.8VU

+1.8VA

+1.2V_DDR

+1.0VA

+5VD TDC 2.55A (NB679)

U21 AOZ1331

UZ1 TPS22961

UZ3 TPS22961

UZ2 TPS22961

ALWON

AUD_PWR_EN

VCCSTG_EN

VCCST_EN

VCCSTG_EN

+1.8VS_AUDIO

+VCCPLL_OC

+1.0V_VCCST

+1.0V_VCCSTG

5

4

3

UZ3 TPS22961

U2 APE8937

U7 G517G1

Security Classification

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION I T CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2

Issued Date

3.3V_CAM_EN#

RUN_ON_P

DOCK_PWR_EN

+1.0V_VCCST

+5VS+5VD

+5V_DOCK

Compal Secret Data

2014/08/20 2015/08/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

PWR_POWER BLOCK DIAGRAM

46 65Tuesday, December 20, 2016

of

1

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

Pebble Creek Power Path Block

D D

C C

B B

A A

Security Classification

5

4

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION I T CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2

2014/08/20 2015/08/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

PWR_POWER PATH DIAGRAM

47 65Tuesday, December 20, 2016

1

47 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

Function feild Power Path(37.1), EMC Part(47.1). 3VLDO(35.27/35.28)

Type C adapter input_1

+VBUS1_PD_20V

PT101

@

D D

PC100

EMC@

2200P_0402_50V7K

Type C adapter input_2

+VBUS2_PD_20V

C C

PC120

EMC@

2200P_0402_50V7K

B B

1

12

PC101

PC103

2

EMC@

0.1U_0402_25V6

0.01U_0402_25V7K

PT102

@

1

12

PC122

PC116

2

EMC@

0.1U_0402_25V6

0.01U_0402_25V7K

EMC@

HCB2012KF-121T50_0805

1 2

12

PC102

EMC@

100P_0402_50V8J

EMC@

HCB2012KF-121T50_0805

1 2

1

PC114

2

EMC@

100P_0402_50V8J

PD1_LPS2

12

PR111

499K_0402_1%

12

PC281

PR256

200K_0402_1%

PL100

EN_PD_HV130,35,48

PL101

EN_PD_HV236,48

12

PR255

10U_0402_6.3V6M

A A

SMART

SMARTSMART

Battery:

Battery:Battery:

12:GND

12:GND12:GND

11:GND

11:GND11:GND

10:GND

10:GND10:GND

09:GND

09:GND09:GND

08:CLK_SMB

08:CLK_SMB08:CLK_SMB

07:DAT_SMB

07:DAT_SMB07:DAT_SMB

06:TBAT_3V3

06:TBAT_3V306:TBAT_3V3

05:SYS_PRES#

05:SYS_PRES#05:SYS_PRES#

04:GND

04:GND04:GND

03:GND

03:GND03:GND

02:GND

02:GND02:GND

01:GND

01:GND01:GND

1

PC108

2

EMC@

2200P_0402_50V7K

+3V_LDO

12

PC117

EMC@

2200P_0402_50V7K

+3V_LDO

SDMK0340L-7-F_SOD323-2

12

PR183

221K_0402_1%

12

200K_0402_1%

14 13

5

+VBUS1_20V

12

PC104

PC105

EMC@

1000P_0402_50V7K

100P_0402_50V8J

PR217

@

1 2

0_0402_5%

AC2_OVP48

+VBUS2_20V

12

PC119

PC118

EMC@

1000P_0402_50V7K

100P_0402_50V8J

PR224

@

1

2

0_0402_5%

AC1_OVP48

+3.3V_LDO_PD2

PD110

1

PR163

1M_0402_1%

1 2

3

2

12

PC144

@

100P_0402_50V8J

1

D

2

1 2

G

S

PQ132

3

PC132

@EMC@

2200P_0402_50V7K

1 2

JT100

GND GND

12

11

10

9

8

7

6

5

4

3

2 1

ACES_50278-01201-001

CONN@

1

PC106

2

EMC@

0.1U_0402_25V6

PR215

200K_0402_1%

1 2

5

G

1 2

PR228

1M_0402_1%

12

PC121

EMC@

0.1U_0402_25V6

PR222

200K_0402_1%

1 2

5

G

1

PR229

1M_0402_1%

2

8

P

+

-

G

PU103A

LM393DMR2G_MICRO8

4

PR165

0_0402_5%

12

11

10

9

8

7

6

5

4

3

2 1

PC107

1U_0603_25V6K

EMC@

@

1

0_0402_5%

PC115

1U_0603_25V6K

EMC@

2

@

1 2

0_0402_5%

1

O

+BATT

12

1

PC133

2

10U_0603_25V6M

34

D

PQ134B

S

PR125

2

12

PC134

10U_0603_25V6M

34

D

PQ136B

S

PR146

EN_PD_HV1 30,35,48

12

2

G

2

G

12

PR218

@

1M_0402_1%

2

G

DCIN1_EN30

1

3

1

PR219

@

1M_0402_1%

2

G

DCIN2_EN30

1

3

PR182

47K_0402_1%

PC146

1200P_0402_50V7K

PR213

PR214

100K_0402_1%

1 2

D

S

PR220

PR221

100K_0402_1%

1

D

S

0_0402_5%

1

300K_0402_1%

2

PD1_LPS1

12

300K_0402_1%

6

D

PQ134A

S

1

PR216

PQ130

12

G

300K_0402_1%

2

PD2_LPS1

12

300K_0402_1%

6

D

PQ136A

S

1

PR225

2

PQ131

EN_PD_HV2 36,48

PR117

2

PC145

S

3

G

PQ133

D

1

SB000006O00 Use SB000004A0L footpin

PR122

@

1 2

0_0402_5%

PD1_LPS1

S

3

PQ135

D

1

S TR AO7401 1P SC70-3

PR132

@

1 2

0_0402_5%

PD2_LPS1

1

2

0.1U_0402_10V7K

S TR AO7401 1P SC70-3

1

2

12

PR166

PR128

PR172

AC1_OVP 48

+BAT_TABLET

PL102

EMC@

HCB2012KF-121T50_0805

2

1

PL103

EMC@

HCB2012KF-121T50_0805

1

2

For ISL88738

1

PR126

2

200K_0402_1%

PR152 100_0402_1%

1 2

PR154 100_0402_1%

1 2

PR157 0_0402_5%

2

1

12

PC126

@EMC@

1000P_0402_50V7K

CLK_SMB

DAT_SMB

TBAT_3V3

SYS_PRES# 49

1

PR100

2

499K_0402_1%

12

PC136

@

1M_0402_1%

1000P_0402_50V7K

12

499K_0402_1%

12

PC137

@

1M_0402_1%

1000P_0402_50V7K

1

2

3

4

S1a

PQ100 AON7405_DFN8-5

1

2

3

PC109

680P_0402_50V7K

PR106

49.9K_0402_1%

2

G

12

PD1_LPS2

5

4

12

13

D

PQ106

S

S2a

PQ113

AON7405 _DFN8-5

1

2 3 5

PC123

680P_0402_50V7K

PR133

49.9K_0402_1%

2

G

12

PD104

EMC@

TVNST52302AB0_SOT523-3

PD2_LPS2

4

1

2

1

D

PQ118

S

3

PD2_LPS2

12

PR113

499K_0402_1%

12

PC282

PR258

200K_0402_1%

1

PD105

2

3

EMC@

TVNST52302AB0_SOT523-3

+3.3V_TBAT_LDO

Tablet battery 3.3V output

4

PQ101 AON7405_DFN8-5

5

PQ114

AON7405 _DFN8-5

PR185

12

PR257

10U_0402_6.3V6M

S1b

PD108

2

3

4

12

PR109

49.9K_0402_1%

1

D

PQ108

S

3

1 2

1M_0402_1%

S2b

PD109

2

3

4

1

PR134

2

49.9K_0402_1%

1

D

PQ119

S

3

1 2

1M_0402_1%

SDMK0340L-7-F_SOD323-2

12

221K_0402_1%

1

2

200K_0402_1%

D

S

13

G

PR178

G

PR179

2

1

2

3

AC1_DISC#35,48

1

2 35

AC2_DISC#36,48

1 2

1M_0402_1%

1 2

PC148

@

G

PQ140

12

PC111

@

680P_0402_50V7K

PR114

@

1

0_0402_5%

1

PC124

2

@

680P_0402_50V7K

PR135

@

1

0_0402_5%

+3.3V_LDO_PD1

PD111

PR164

3

+

2

-

1

2

100P_0402_50V8J

PR167

0_0402_5%

2

1

PR103

2

499K_0402_1%

2

VBUS1_ECOK 30,48

PR123

@

1

2

0_0402_5%

12

PR130

499K_0402_1%

2

VBUS2_ECOK 30,48

PR136

@

1 2

0_0402_5%

8

P

1

O

G

PU1104A LM393DMR2G_MICRO8

4

2

PBAT_SMBCLK 30

PBAT_SMBDAT 30

S

PQ104

D

1 3

S TR AO7401 1P SC70-3

5

PR176

1M_0402_1%

1

S

3

PQ115

D

1

S TR AO7401 1P SC70-3

5

PR177

1M_0402_1%

1 2

12

EN_PD_HV2 36,48

G

PR184

G

2

+3V_LDO

2

G

2

+3V_LDO

47K_0402_1%

1

PC149

1200P_0402_50V7K

+CHG_VIN_20V

12

PR115

200K_0402_1%

3

D

PQ109B

S

4

DMN66D0LDW-7_SOT363-6

12

PR139

200K_0402_1%

34

D

PQ121B

S

DMN66D0LDW-7_SOT363-6

EN_PD_HV1 30,35,48

PR120

0_0402_5%

2

PC147

+VBUS1_20V

+VBUS2_20V

+AC_DOCK_20V

3

12

PR101

300K_0402_1%

1

PR107

2

300K_0402_1%

61

D

2

G

PQ109A

S

DMN66D0LDW-7_SOT363-6

+CHG_VIN_20V

1

PR129

2

300K_0402_1%

12

PR118

300K_0402_1%

61

D

2

G

PQ121A

S

DMN66D0LDW-7_SOT363-6

AC2_OVP 48

12

0.1U_0402_10V7K

SDMK0340L-7-F_SOD323-2

3

2

S3b

PD112

3

1

2

PQ102

2

G

12

PC112

@

680P_0402_50V7 K

1 2

1M_0402_1%

PR159

0_0402_5%

1 2

PR161

1

0_0402_5%

PR121

0_0402_5%

1

AON7405 _DFN8-5

1

2

3

4

12

PR112

49.9K_0402_1%

13

D

2

G

S

PR180

2

2.13V when docked

2

12

PR162 390K_0402_1%

PQ110

DMN65D8LW-7_SOT323-3

DET_L# 30,43

DET_R# 30

+CHG_VIN_20V

12

PR102

G

300K_0402_1%

+3V_LDO

12

PR249

200K_0402_1%

2

G

3

PR137

@

1

AC3_DISC#48

0_0402_5%

D

5

2

G

PQ107B

S

4

+3V_LDO

12

PR248

AC3_DISC#48

200K_0402_1%

13

D

PQ137

S

2

1

PR108

2

300K_0402_1%

61

D

PQ107A

S

+3V_LDO

1

PC139

2

0.1U_0402_10V7K

VCC

2

4

Y

G

PU102

74LVC1G32GW_TSSOP5

12

S

PR104

PQ105

D

1 3

VBUS3_ECOK30,48

5

B

A

3

499K_0402_1%

S TR AO7401 1P SC70-3

PR119

@

1 2

0_0402_5%

12

PR160

PR158

200K_0402_1%

1

2

13

D

PQ111

S

DMN65D8LW-7_SOT323-3

5

DET_R 43

S3a

PQ103

AON7405 _DFN8-5

5

PQ112

12

499K_0402_1%

2

G

+AC_DOCK_20V

S

3

PQ138

D

1

S TR AO7401 1P SC70-3

DCIN3_EN 30

+3V_LDO

12

PR252

200K_0402_1%

6

D

S

1

2 3

4

1

2

13

D

S

DMN65D8LW-7_SOT323-3

12

PR105

PC110

680P_0402_50V7K

PR110

49.9K_0402_1%

2

G

12

AC3_DISC#48

PR116

@

1 2

0_0402_5%

12

PC138

PR181

@

1M_0402_1%

1000P_0402_50V7K

PR253

@

1

0_0402_5%

1

Wireless charge from Base

+AC_DOCK_IN_20V

PL104

EMC@

HCB2012KF-121T50_0805

12

PR251

G

300K_0402_1%

2

1

PR250

2

300K_0402_1%

3

D

5

G

S

4

PQ139A

1 2

12

1

PC135

PR223

2

@

1M_0402_1%

EMC@

100P_0402_50V8J

PQ139B

1

PC113

2

EMC@

2200P_0402_50V7K

PT103

@

+3VALW

PR192

@

AC_DIS#

1

2

0_0402_5%

6

2

12

34

D

PQ127B

S

PR145

@

0_0402_5%

+3VALW

PR143

G

2

D

G

PQ122A

S

1

To EC

AC_DISC#30

1 2

61

0_0402_5%

D

2

G

PQ128A

S

1

2

200K_0402_1%

34

D

PQ120B

S

PR230

0_0402_5%

2

PR200

@

AC_DIS#

PR138

@

+3VALW

12

PR124

200K_0402_1%

61

D

S

VBUS2_ECOK30,48

PQ127A

@

0_0402_5%

1

1 2

0_0402_5%

5

G

PR203

+3VALW

PR142

200K_0402_1%

2

1

VBUS1_ECOK30,48

PR201

@

2

1

0_0402_5%

2

G

AC1_DISC#35,48

+3VALW

12

PR127

200K_0402_1%

5

61

PR144

@

AC2_DISC#36,48

1 2

0_0402_5%

D

2

G

PQ120A

S

PR204

@

0_0402_5%

1

+3VALW

12

PR174

PR202

200K_0402_1%

3

D

S

4

1 2

0_0402_5%

1 2

PQ122B

PR196

@

0_0402_5%

5

G

AC_DIS#

1

PC140

@

2

1000P_0402_50V7K

AC3_DISC#48

+3V_LDOP

1

PR150

10K_0402_1%

PD103

2

PD106

PD107

2

1

12

1

LDO_IN

PC128

1U_0603_25V6K

1 2

PU101

VCC1OUT

2

GND

3

NC

RT9069-33GB_SOT23-5

PR149

300K_0402_5%

2

1

PR153

5

4

EN

12

PC131

300K_0402_5%

1U_0402_16V6K

PR147

0_0805_5%

2

1

PC129

2

1U_0402_16V6K

13

D

2

G

S

PQ126 DMN65D8LW-7_SOT323-3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION I T CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

+3V_LDOP

3VALW_PG 30,48,53

Compal Secret Data

2011/06/02 2013/10/28

2

Compal Secret Data

Deciphered Date

3VALW_PG30,48,53

2

+3VALW

34

D

5

G

PQ125B

S

DMN66D0LDW-7_SOT363-6

PR151

@

1

2

0_0402_5%

G

12

PC130

0.1U_0402_25V6

12

PR175

200K_0402_1%

61

D

2

G

S

PR206

0_0402_5%

1 2

VBUS3_ECOK30,48

+3VALW

12

PR171

200K_0402_1%

6

D

2

G

S

1

PQ123

S TR AO7401 1P SC70-3

1 3

D

S

PR148

1M_0402_1%

G

2

1

PC125

0.01U_0402_16V7K

1 2

PQ124

S TR AO7401 1P SC70-3

D

S

1 3

PR155

G

2

100K_0402_1%

1 2

12

PR156

@

0_0402_5%

61

D

PQ125A

DMN66D0LDW -7_SOT363 -6

S

Title

Size Docum ent Number Rev

Date: Sh eet of

Date: Sh eet

Date: Sh eet of

PR208

0_0402_5%

1 2

12

PQ129A

PR207

0_0402_5%

1 2

PR195

@

0_0402_5%

34

D

5

G

PQ129B

S

5

G

+3VALW

12

PR173

200K_0402_1%

3

D

5

G

PQ117B

S

4

PQ117A

PR205

@

0_0402_5%

1 2

2

PR231

0_0805_5%

2

1

Compal Electronics, Inc.

PWR_DCIN/Power Path

LA-D891P

1

AC_DISC_OUT# 51

PR209

0_0402_5%

1 2

3

D

PQ128B

S

4

From Charger

PR170

@

1 2

0_0402_5%

+3V_LDO

To Charger

CHG_PROCHOT# 51

AC_DIS#

48 65T uesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

D D

+3.3V_TBAT_LDO

+3V_LDO

4

PD280

BAT54CW_SOT323-3

2

3

1

2

1

B+

1

PR280

1

C C

B B

PR283

100K_0402_5%

PR284

100K_0402_5%

2

1

2

100K_0402_5%

2

G

PWR_SW_IN#30,43

2

13

D

S

PR281

100K_0402_5%

PQ280

DMN65D8LW-7_SOT323-3

1

PU280

SN74LVC1G123DCUR_VSSOP8

1

2

A#

2

B

R/CEXT

3

CLR#

4

GND

VCC

CEXT

8

7

6

5

Q

1

PR282

549K_0402_1%

2

SYS_PRES# 48

12

PC280

4.7U_0402_6.3V6M

12

PR285

1M_0402_1%

A A

Security Classification

2014/08/20 2015/08/20

Issued Date

5

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/08/20 2015/08/20

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PWR_For bat ship mode

49 65Tuesday, December 20, 2016

1

49 65Tuesday, December 20, 2016

1.0

of

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

Battery low detect

+3VALW

B+

D D

+3VALW

12

PR293

232K_0402_1%

12

PC292

1000P_0402_50V7K

C C

12

PR288

84.5K_0402_1%

PC290

@

1

2

100P_0402_50V8J

BATT_VREF

12

PC291

@

0.01UF_0402_25V7K

8

3

+

2

-

4

PR299

2M_0402_5%

1

P

1

O

G

PU290A

LM393DMR2G_MICRO8

2

1

PR292

10K_0402_1%

2

PQ290A

DMN66D0LDW-7_SOT363-6

4

3

S

D

G

5

1

PR294

@

2

10K_0402_1%

1 2

74AHC1G00GW_SOT353-5

PU293

B A

GND3Y

FAST_COMP_OUT

Vcc

+3VALW+3VALW

5

4

PC296

0.1U_0402_10V7K

1

2

PR304

0_0402_5%

1

61

D

G

2

1

PC295

2

1U_0603_10V6K

PR291

22.6K_0402_1%

1 2

PQ290B

S

DMN66D0LDW-7_SOT363-6

2

H_PROCHOT# 11,30,51,54,58

+3VALW

PC297

0.1U_0402_10V7K

PU292

5

B+

+3VALW

PR295

1

PR297

2

232K_0402_1%

B B

12

PC293

0.1U_0402_25V6

1

PR289

2

84.5K_0402_1%

PR290

48.7K_0402_1%

PR296

42.2K_0402_1%

1

2

BATT_VREF

12

PC294

12

1U_0603_10V6K

2M_0402_5%

1 2

+3VALW

8

5

+

6

-

4

P

7

O

G

PU290B

LM393DMR2G_MICRO8

SLOW_COMP_OUT

+3VALW

12

PR298

10K_0402_1%

Vcc

4

Y

74AHC1G00GW_SOT353-5

GND

1

B

2

A

3

2

1

A A

Security Classification

5

4

Security Classification

2011/06/02 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/02 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

LA-D891P

Date: Sheet of

2

Date: Sheet of

LA-D891P

Compal Electronics, Inc. PWR_Battery low detect

PWR_Battery low detect

50 65Tuesday, December 20, 2016

1

50 65Tuesday, December 20, 2016

1.0

Vinaﬁx.com

A

smd.db-x7.ru

B

C

D

Charger controller(40.1), Support component(40.2)

PT100

+CHG_VIN_20V

PL302

1 1

EMC@

1UH_1277AS-H-1R0N-P2_3.3A_30%

1 2

@

PR300

1

2

3.3_0402_1%

0.01_1206_1%

4

3

PC312

4.7U_0603_25V6K

1 2

1

2

1

PR301

2

3.3_0402_1%

12

PC314

1U_0402_25V6K

CHG_VIN_20V

4.3V

1

PR305

2

442K_0402_1%

CHG_ACIN

12

1

PR307

PC331

2

100K_0402_1%

0.1U_0402_25V6

1

PC301

2

@

0.1U_0402_25V6

PR302

12

PC313

1U_0402_25V6K

+CHG_SRC_20V

PC303

@EMC@

0.1U_0402_25V6

1

12

PC306

@EMC@

1

PC307

PC302

2

@

10U_0603_25V6M

2200P_0402_50V7K

1

PC308

PC309

2

10U_0603_25V6M

1

12

PC304

10U_0603_25V6M

1

PC305

2

10U_0603_25V6M

PC310

2

10U_0603_25V6M

B+

1

PC318

2

10U_0603_25V6M

PC322

PR324

2.2_0402_1%

PC347

1U_0402_25V6K

1 2

12

10U_0603_25V6M

+8.4V_BATT+

1

2

10U_0603_25V6M

1

PC320

PC319

2

10U_0603_25V6M

1

2

PC323

10U_0603_25V6M

1

12

1

105K_0402_1%

13

ASGATE

PU300

CMOP

28

PC330

PR306

2

2.2_0603_5%

2

12

29

CHG_AMON

12

0.22U_0603_25V7K

CHG_LX1

CHG_BST1

BOOT1

I_ADP

PR329

PR328

11

CHG_PSYS

12

CHG_UG1

UGATE1

PSYS30VBAT

0_0402_5%

CHG_LG1

PR308

33

10

9

PAD

CHG_VDDP

8

LGATE1

PHASE1

VDDP

LGATE2

PHASE2

UGATE2

BOOT2

VSYS

CSOP

CSON

BGATE

31

32

CHG_VBAT1

CHG_BGATE

1

PR333

@

2

10K_0402_5%

30

B

CHG_LG2

7

CHG_LX2

6

CHG_UG2

5

CHG_BST2

4

3

CHG_CSOP

2

1

100_0402_1%

1

30,58

12

P_SYS

@

PC351

0.1U_0402_25V6

5V

CHG_CSON

PR330

4.7_0402_5%

1

PC334

1U_0402_6.3V6K

1

PR311

1 2

2.2_0603_5%

PC336

1

0.22U_0603_25V7K

PR318

0_0402_5%

1

12

PC341

@

0.1U_0402_25V6

+BAT_TABLET

2

VDD

2

B+

CHG_UG1

CHG_LX1

CHG_LG1

5

Main: ML, 2nd: CLSN

4

3

1

2

5

4

2

1

3

Package: 11.5 x 10.3 x 2 Idc=10A, Isat=11A

PQ302

Rdc=14mohm (Typ.)

AON6428L_DFN8-5

2.2UH_MMD-10BZN2R2M-M1L_10A_20%

PQ305

AON6508_DFN8-5

PL301

1

12

PR316

4.7_1206_5%

@EMC@

SNUB_CHG1

1

PC342

2

@EMC@

680P_0402_50V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMP AL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

CHG_UG2

2

1

PR317

4.7_1206_5%

2

CHG_LG2

@EMC@

SNUB_CHG2

1

PC343

2

@EMC@

680P_0402_50V7K

C

5

4

CHG_LX2

4

2014/10/24 2015/08/31

2

1

3

5

213

1U_0402_25V6K

PQ307

AON6508_DFN8-5

PQ306

AON6508_DFN8-5

1

2

PC345

1 2

Compal Secret Data

PR303

PC333

1

VDD

PR319

2

AC_DISC_OUT#48

2_1206_5%

2

1

CHG_DCIN

CHG_ACIN

CHG_CMIN

CHG_DAT

CHG_CLK

1

PR320

2

1M_0402_1%

1

+VBUS1_ESD 41

200K_0402_1%

PR325

12

PC332

1U_0603_25V6K

17

18

19

20

21

22

23

24

PR332

0_0402_5%

1 2

CHG_COMP

1

PR327

499_0402_1%

2

1

PC349

2

0.01U_0402_16V7K

CHG_ADP

CHG_CSIP

15

16

ADP

DCIN

VDD

ACIN

OTGEN/CMIN

SDA

SCL

PROCHOT#

ACOK

CSIP

ISL88738HRTZ-T_TQFN32_4X4

Change part number to MP

OTGPG/CMOUT26PROG27AMON/BMON

BATGONE

25

2

PR322

3-CELL

1

PC348

2

@

560P_0402_50V7K

PC350

CHG_CSIN

14

CSIN

SA00009VW0L

1

2

12

0.1U_0402_25V6

2 2

SDMK0340L-7-F_SOD323-2

+CHG_VIN_20V

B+

2

SDMK0340L-7-F_SOD323-2

2

5V

VDD

CHG_MCP23017_SMBDAT30,41

CHG_MCP23017_SMBCLK30,41

H_PROCHOT#11,30,50,54,58

CHG_PROCHOT#48

3 3

@

PD303

CHG_ACIN B+

SDMK0340L-7-F_SOD323-2

12

CHG_VIN_20V

12

PR338

PR337

@

10K_0402_5%

0_0402_5%

+VBUS1_20V

PR341

@

0_0402_5%

1 2

4 4

System short detection cirucit

1 2

1M_0402_1%

S ZEN DIO GLZ5.1B LL-34

PD304

2

1

SDMK0340L-7-F_SOD323-2

PR336

1

PD302

@EMC@

SC400001300

A

2

1

D

+CHG_VIN_20V

PD300

1

PD301

1

1U_0402_6.3V6K

1

PR331 0_0402_5%@

1

PR334 0_0402_5%1

1 2

PR313 0_0402_5%

PR314 0_0402_5%

1 2

PR315 75_0402_5%

1 2

VDD

ACAV_IN30

B+

1

PR339

@

0_0402_5%

PQ308

2

1

2

3

S

G

1

PR312

PR335

@

2

3M_0402_5%

100K_0402_1%

12

PR321

200K_0402_1%

1U_0603_25V6K

PR309

2_1206_5%

1 2

PC335

2

1

100K_0402_1%

PR340

@

0_0402_5%

1 2

For PD ESD function

PC316

PC315

10U_0603_25V6M

PR310

0.005_1206_1%

1

2

PR323

2.2_0402_1%

PC346

4.7U_0603_25V6K

1 2

Deciphered Date

PC317

2

4

3

1

2

12

1

PC324

PC325

2

@

10U_0603_25V6M

PC326

2

@

10U_0603_25V6M

PQ304

AON7405_DFN8-5

1

2 3 5

4

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet

1

PC321

2

@EMC@

10U_0603_25V6M

12

PC329

2

0.1U_0402_25V6

@EMC@

2200P_0402_50V7K

+BAT_TABLET

CHG_BGATE

12

PC339

4700P_0402_25V7K

Compal Electronics, Inc.

PWR_Charger (ISL88738)

D

1

PC340

2

2200P_0402_50V7K

1.0

51 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

LCD driver controller(35.31), Support component(35.32)

D D

Current: 11.1mA x 8 = 88.8mA Max Voltage: 6.2V x 6 = 37.2V

10UH_MLPS-5020-100M-E_1.5A_20%

+INV_PWR_SRC +LED_AN

PL400

1 2

LED_SW

12

PD400

DFLS160-7_POWERDI123-2

2

1

12

PC400

0.1U_0603_50V7K

C

PR407

10K_0402_1%

DISPOFF#22

INV_PWM22

B B

1 2

PR411

10K_0402_1%

1 2

12

PR408

1M_0402_1%

12

PR413

1M_0402_1%

LED_SD

12

PC411

@

100P_0402_50V8J

LED_PWM

12

PC416

@

100P_0402_50V8J

12

PC401

1U_0805_50V7K

PR406

43K_0201_1%

1 2

PR405

1 2

523K_0402_1%

PR409

LED_SD

+LED_AN

@

1

0_0402_5%

PR410

1M_0402_1%

1 2

1

Open for PWM mode No need EC control

PR401

@

LED_PWM

2

LED_SW

PR412

45.3K_0402_1%

PR420

0_0402_5%

1

1 2

28

27

26

25

24

23

22

12

2

0_0402_5%

@

0_0402_5%

2

PR403

1

2

3

PWM

SEL1

R_PWMIN

FSLCT

VIN

SD

SW1

SW2

TPS61188ARUYR_QFN28_4X4

OVP

21

PR414

SEL2

NC19PGND220PGND1

953K_0402_1%

PC402

0.1U_0402_25V6

1 2

4

5

6

SCL

SDA

VDDIO

ISETH17NC

R_FPWM

16

18

12

PR415

118K_0402_1%

PR400

@

PR402

0_0402_5%

1 2

@

PR404

1

0_0402_5%

7

PU400

IFB1

8

IFB2

9

IFB3

10

IFB4

11

AGND

12

IFB5

13

IFB6

14

IFB7

IFB8

TP

15

29

2

LED_IFB4 22

2

LED_IFB1 22

1

2

LED_IFB7 22

LED_IFB8 22

12

PC408

@

470P_0402_50V7K

12

PC412

@

470P_0402_50V7K

PR417

@

1

12

1

PC415

@

PC417

@

PR418

@

2

470P_0402_50V7K

12

PR419

@

470P_0402_50V7K

0_0402_5%

PR416

@

1

0_0402_5%

1

0_0402_5%

2

10_0603_5%

1

PC407

2

220P_0402_50V7K

LED_IFB3 22

PC410

@

470P_0402_50V7K

12

LED_IFB6 22

PC414

@

470P_0402_50V7K

12

PC409

@

470P_0402_50V7K

12

1

PC404

PC403

2

2.2U_0603_50V6K

LED_IFB2 22

PC413

@

470P_0402_50V7K

1

PC405

2

2.2U_0603_50V6K

LED_IFB5 22

1

PC418

2

PC406

2

0.1U_0603_50V7K

2.2U_0603_50V6K

C

A A

Security Classification

2011/06/02 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2011/06/02 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet of

Compal Electronics, Inc.

PWR_LCD driver (TPS61181A)

LA-D891P

1

52 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

A

smd.db-x7.ru

B

C

D

E

3V/5V controller(35.1), Support component(35.2)

Main: ML, 2nd: CLSN Package: 5.7 x 5.4 x 1.8

B+

1 1

For Ultra-Soni c mode

ALWON30,53

EE side 2.2K

PL500

EMC@

HCB2012KF-121T50_0805

1 2

@

PR504

1 2

0_0402_5%

12

PR505

2.2K_0402_1%

PU500

3V_VIN

12

PC502

PC501

@EMC@

0.1U_0402_25V6

@EMC@

1

12

PC503

2200P_0402_50V7K

12

PC504

2

10U_0603_25V6M

1 2

4.7U_0402_6.3V6M

3VALW_PG30,48

@

PR500 0_0402_5%

PC505

1 2

1

PR503

2

100K_0402_5%

+3VALW

3V_EN

12

PR516

@

100K_0402_1%

3V_EN

+3VLP

1

VIN

12

ENCLK

11

EN

6

LDO

3

PG

9

VCC

NB680GD-Z_QFN12_2X3

12

PC510

1U_0402_16V6K

CLK

BST

SW

VOUT

PGND

AGND

4

8

7

5

2

10

3.3_0603_1%

1

+3VALWP

PR501

0.22U_0402_16V7K

2

PC500

1 2

Idc=6.2A, Isat=8.4A DCR=29mohm (Typ.)

1.5UH_MMD-05AHN1R5M-M1L_6.2A_20%

12

PR502

4.7_0805_5%

@EMC@

1

PC511

2

@EMC@

680P_0603_50V7K

PL501

1

2

12

1

PC507

PC506

2

22U_0603_6.3V6M

1

PC509

PC508

2

22U_0603_6.3V6M

12

+3VALWP

PJP500

@

1 2

JUMP_43X118

+3VALW+3VALWP

3VALW TDC 5.21A Peak Current 7.45A

Main: ML, 2nd: CLSN

2 2

CPU_B+

ALWON30,53

PL502

EMC@

HCB2012KF-121T50_0805

1

@

PR510

1 2

0_0402_5%

2

12

PC515

PC514

0.1U_0402_25V6

@EMC@

2200P_0402_50V7K

Ultra-Sonic mo de

5VALW_EN

1

PR517

@

2

100K_0402_1%

PU501

5VALW_VIN

1

PC516

2

1

12

PC517

2

10U_0603_25V6M

@

PR506 0_0402_5%

1 2

PC518

4.7U_0402_6.3V6M

1

5VALW_PG30

@

100K_0402_5%

2

PR509

+5VALW_LP

12

5VALW_EN

1

VIN

12

ENCLK

11

EN

6

LDO

3

PG

9

VCC

NB679GD-Z_QFN12_2X3

12

PC523

1U_0402_16V6K

CLK

BST

SW

VOUT

PGND

AGND

4

8

7

5

2

10

3.3_0603_1%

1 2

+5VALWP

PR507

PC513

0.22U_0402_16V7K

1 2

Package: 5.7 x 5.4 x 1.8 Idc=6.2A, Isat=8.4A DCR=29mohm (Typ.)

1.5UH_MMD-05AHN1R5M-M1L_6.2A_20%

12

PR508

4.7_0805_5%

@EMC@

12

PC524

@EMC@

680P_0603_50V7K

PL503

1

2

12

PC521

PC520

PC519

22U_0603_6.3V6M

PC522

22U_0603_6.3V6M

+5VALWP +5VALW

1

2

+5VALWP

@

PJP501

1

JUMP_43X118

2

5VALW TDC 5.85A Peak Current 8.83A

3 3

Main: ML, 2nd: CLSN Package: 5.7 x 5.4 x 1.8

B+

ALWON30,53

4 4

PL504

EMC@

HCB2012KF-121T50_0805

1 2

@

PR515

2

1

0_0402_5%

12

PC528

PC527

0.1U_0402_25V6

@EMC@

2200P_0402_50V7K

Ultra-Sonic mo de

5VD_EN

12

PR518

@

100K_0402_1%

5VD_VIN

12

1

PC529

PC530

2

10U_0603_25V6M

@

PR511 0_0402_5%

1

PC531

4.7U_0402_6.3V6M

1

5VD_PG30

@

100K_0402_5%

2

PR514

2

5VD_EN

+5VD_LP

1

2

PU502

1

VIN

12

ENCLK

11

EN

6

LDO

3

PG

9

VCC

NB679GD-Z_QFN12_2X3

12

PC536

1U_0402_16V6K

CLK

BST

VOUT

PGND

AGND

PR512

4

3.3_0603_1%

1 2

8

7

SW

5

+5VDP

2

10

PC526

0.22U_0402_16V7K

1 2

Idc=6.2A, Isat=8.4A DCR=29mohm (Typ.)

1.5UH_MMD-05AHN1R5M-M1L_6.2A_20%

12

PR513

4.7_0805_5%

@EMC@

12

PC537

@EMC@

680P_0603_50V7K

PL505

1 2

+5VDP

12

PC533

PC532

22U_0603_6.3V6M

PC534

22U_0603_6.3V6M

1

12

PC535

2

22U_0603_6.3V6M

PJP502

@

+5VDP +5VD

1

2

JUMP_43X118

5VD TDC 2.55A Peak Current 3.62A

Security Classification

2011/06/02 2013/10/28

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMP AL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2011/06/02 2013/10/28

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

D

Date: Sheet of

Compal Electronics, Inc.

PWR_+3V(NB680)/+5V(NB679)

LA-D891P

53 65Tuesday, December 20, 2016

E

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

+1.2V_DDR controller(35.3), Support component(35.4)

Main: CYN, 2nd: CLSN

D D

Package: 5.4 x 5.7 x 1.5 Idc=6.5A, Isat=9A DCR=20mohm (Typ.)

PR601

2.2_0603_5%

1 2

PR600

75_0402_5%

H_PROCHOT#11,30,50,51,58

EMC@

HCB2012KF-121T50_0805

B+

C C

SM_PG_CTRL6

RUN_ON_EC30,32

B B

SUS_ON_EC30,32,43,45

PL601

1 2

PR605

@

0_0402_5%

1 2

PR608

@

0_0402_5%

1 2

@

1 2

0_0402_5%

PC607

PR611

12

10U_0603_25V6M

12

PC608

EMC@

0.1U_0402_25V6

12

PC609

EMC@

2200P_0402_25V7K

1.2V_DDR_PG30

12

PR607

1M_0402_1%

12

PC613

@

0.1U_0402_10V7K

12

PR612

1M_0402_1%

12

PC615

@

0.1U_0402_10V7K

1 2

EN_0.6V

EN_1.2V

12

PR606

@

100K_0402_5%

12

PR610

@

0_0402_5%

+3VALW

1.2V_DDR_OT

PU600

1

VIN

16

EN1

15

EN2

12

PG

11

OTW

NB685GQ-Z_QFN16_3X3

3V3

3

12

PC614

1U_0402_16V6K

10

BST

AGND

4

2

13

9

FB

SW

VTT

VTTS

PR609

150K_0402_1%

6

5

8

7

VDDQ

VTTREF

PGND

MODE

14

12

PC600

0.22U_0402_16V7K

1 2

+1.2V_DDRP

+0.6VSP

12

PC612

0.22U_0402_10V6K

12

1

PC610

PC611

2

10U_0402_6.3V6M

PR602

@EMC@

4.7_0805_5%

1 2

1UH_PCME051E-1R0MS_6.5A_20%

PL600

1 2

PC601

@EMC@

680P_0402_50V7K

1 2

12

PC602

220P_0402_50V8J

12

PR603

PC603

100K_0402_1%

22U_0603_6.3V6M

12

PR604

100K_0402_1%

+1.2V_DDRP

+1.2V_VDDR TDC 3.20A

12

PC604

22U_0603_6.3V6M

PJP600

@

112

JUMP_43X79

+1.2V_DDRP

12

PC605

22U_0603_6.3V6M

12

PC606

22U_0603_6.3V6M

+1.2V_DDR

2

Peak Current 4.58A

Mode EN1 EN2 VDDQ VTT S0 H H on on S3 L H on off

A A

5

S4/S5 L L off off

Note: S3 - sleep ; S5 - power off

Security Classification

2013/04/10 2014/05/01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2013/04/10 2014/05/01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet of

Compal Electronics, Inc.

PWR_+1.2V_DDR(NB685)

54 65Tuesday, December 20, 2016

of

1

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

Module Design

+1.0VA controller(35.5), Support component(35.6)

D D

+3VALW

Main: CLSN, 2nd: CYN

12

PR705

@

100K_0402_5%

PL700

EMC@

HCB2012KF-121T50_0805

B+

C C

SIO_SLP_SUS#10,30,32,44,56,57

1

PR700

75K_0402_1%

1 2

2

PC705

@EMC@

10U_0603_25V6M

12

PC706

10U_0603_25V6M

@

1 2

100K_0402_5%

PR708

1

0_0402_5%

1

PC703

2

EMC@

2200P_0402_50V7K

1

PR701

1M_0402_1%

2

1

PC700

2

0.22U_0402_10V6K

12

PC704

EMC@

0.1U_0402_25V6

+3VALW

Current limit set to 6A

+3VALW

B B

1

2

PR707

2

PR709

@

1 2

0_0402_5%

VIN_1.0VA

EN_1.0VA

ILMT_1.0VA

12

PU700

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND

18

GND

11

EN

13

ILMT

15

BYP

SY8286RAC_QFN20_3X3

PC713

4.7U_0603_6.3V6K

PG

BS

LX

FB

VCC

NC

PAD

9

1

6

19

20

14

17

10

12

16

21

PR703

0_0603_5%

1

LX_1.0VA

LDO_1.0VA

1.0VA_PG 30

0.1U_0603_25V7K

1

2

12

PC712

2.2U_0402_6.3V6M

PC702

2

Package: 4.2 x 4.75 x 2 Idc=4.2A, Isat=5.2A DCR=43mohm (Typ.)

@EMC@

PR702

4.7_0603_5%

1

1UH_MHCI04012-1R0M-R8EQ_4.2A_20%

1 2

680P_0402_50V7K

2

PL701

@EMC@

1

PC701

FB=1.02V

2

+1.0VAP

1

2

12

PR704

14K_0402_1%

PR706

20K_0402_1%

1

PC707

2

330P_0402_50V7K

1

PC708

2

22U_0603_6.3V6M

1

PC709

2

22U_0603_6.3V6M

1

PC710

PC711

2

22U_0603_6.3V6M

+1.0VA TDC 2.87A Peak Current 3.75A

PJP700

@

+1.0VAP

A A

Security Classification

2014/10/17 2014/12/05

Issued Date

5

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/10/17 2014/12/05

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

LA-D891P

Date: Sheet

Date: Sheet of

2

Date: Sheet

LA-D891P

Compal Electronics, Inc.

PWR_+1.0VA(SY8286RAC)

112

JUMP_43X79

2

1

+1.0VA

55 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

A

smd.db-x7.ru

Module Design

+1.8VS controller(35.13), Support component(35.14)

B

C

D

PR720

@

0_0402_5%

PC725

10U_0603_25V6M

1 2

@

0_0402_5%

1

PC720

@

0.1U_0402_25V6

1 2

12

PR721

2

VIN_1.8VA

Tss=1.65mS

PC726

3300P_0402_50V7-K

SS_1.8VA

1

2

EN_1.8VA

12

11

10

9

+1.8VAP

13

14

EN

VOS

PVIN

PU720 TLV62150RGTR_QFN16_3X3

AVIN

SS/TR

DEF

8

PR726

@

0_0402_5%

15

FSW

7

1

2

17

TP

PGND16PGND

AGND

6

1

SW

2

SW

3

SW

4

PG

12

FB

5

FB_1.8VA

PR725

@

100K_0402_5%

+3VALW

Fsw=1.25MHz

SUS_ON_P32,56

1 1

SIO_SLP_SUS#10,30,32 ,44,55,57

PL720

EMC@

HCB1608KF-121T30_0603

B+

2 2

1 2

12

PC723

EMC@

0.1U_0402_25V6

12

PC724

EMC@

2200P_0402_50V7K

Main: TOKO, 2nd: CLSN Package: 2.5 x 2.0 x 1.2 Idc=1.3A, Isat=1.7A DCR=96mohm (Typ.)

@EMC@

4.7_0603_5%

1

2.2UH_1239AS-H-2R2N-P2_1.3A_30%

SW_1.8VA

PR723

2

PL721

1

@EMC@

680P_0402_50V7K

FB=1.817V

1.8VA_PG 30

PC727

1

2

12

1

PR722

2

412K_0402_1%

PR724

324K_0402_1%

12

PC721

22P_0402_50V8J

PC722

22U_0603_6.3V6M

+1.8VAP

PJP720

@

112

JUMP_43X39

2

+1.8VA

+1.8VA TDC 0.31A Peak Current 0.45A

+1.8VAP

Module Design

+1.8VU controller(35.15), Support component(35.16)

PR727

@

0_0402_5%

1

SUS_ON_P32,56

RUN_ON_P32,44,45,57

3 3

EMC@

PL722

B+

HCB1608KF-121T30_0603

1

2

12

1

PC732

PC731

2

EMC@

0.1U_0402_25V6

2200P_0402_50V7K

PC733

0.1U_0402_25V6

1

2

10U_0603_25V6M

PR728

@

0_0402_5%

1 2

PC728

@

1

2

VIN_1.8VU

2

Tss=1.65mS

SS_1.8VU

1

PC734

2

3300P_0402_50V7-K

EN_1.8VU

12

11

10

9

+1.8VUP

13

14

EN

VOS

PVIN

PU721 TLV62150RGTR_QFN16_3X3

AVIN

SS/TR

DEF

8

7

12

PR733

@

0_0402_5%

15

FSW

17

TP

PGND16PGND

AGND

6

1

SW

2

SW

3

SW

4

PG

FB

5

FB_1.8VU

PR732

@

100K_0402_5%

+3VALW

Fsw=1.25MHz

4 4

+1.8VUP

Main: TOKO, 2nd: CLSN Package: 2.5 x 2.0 x 1.2 Idc=1.3A, Isat=1.7A DCR=96mohm (Typ.)

@EMC@

PR730

4.7_0805_5%

1 2

PL723

2.2UH_1239AS-H-2R2N-P2_1.3A_30%

SW_1.8VU

1 2

FB=1.817V

1.8VU_PG 30

12

PC735

@EMC@

680P_0402_50V7K

1

2

12

1

PR729

PR731

PC729

2

412K_0402_1%

324K_0402_1%

22P_0402_50V8J

12

PC736

PC730

@

22U_0603_6.3V6M

PJP721

@

2

+1.8VUP

112

JUMP_43X39

+1.8VU

+1.8VU TDC 0.19A Peak Current 0.27A

+1.8VUP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/10/17 2014/12/05

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Nu mber Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

PWR_+1.8VA/+1.8VU(TLV62150)

LA-D891P

D

56 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

+1.0VS_VCCIO controller(35.11), Support component(35.12)

4

3

2

1

14

PC809

100P_0402_50V8J

PR800

10K_0402_1%

1

15

LPM

SS

7

SS_VCCIO

12

2

16

PGND

AGND

6

17

TP

VOS

SW

PG

FBS

5

+3VALW

+1.0VS_VCCIOP

1

2

3

4

PR734

@

100K_0402_5%

+3VALW

LX_VCCIO

1

2

PR806

@EMC@

4.7_0603_5%

1

1UH_1277AS-H-1R0N-P2_3.3A_30%

+1.0VS_VCCIO_PG30

@EMC@

680P_0402_50V7K

2

PL801

1 2

PR807

@

100_0402_1%

PR812

@

100_0402_1%

1

2

1

2

PC808

2

PR810

@

0_0402_5%

1 2

1

@

PR811

0_0402_5%

Main: TOKO, 2nd: CLSN Package: 3.2 x 2.5 x 1.2 Idc=3.3A, Isat=4.6A DCR=48mohm (Typ.)

1

PC804

PC803

2

22U_0603_6.3V6M

VCCIO_SENSE16

2

VSSIO_SENSE16

+1.0VS_VCCIOP

12

PC805

22U_0603_6.3V6M

@

PJP800

2

+1.0VS_VCCIOP +1.0VS_VCCIO

+1.0VS_VCCIO TDC 2.17A Peak Current 3.10A

112

JUMP_43X79

PR801

@

0_0402_5%

SIO_SLP_S0#10,31,45,57

VCCSTG_EN45

D D

RUN_ON_P32,44,45,56

PL800

EMC@

HCB1608KF-121T30_0603

B+

+3VALW

1

12

PR804

PR805

@

10K_0402_1%

2

10K_0402_1%

1

PR808

@

PR809

10K_0402_1%

C C

2

12

Vout=0.95V

10K_0402_1%

VID0_VCCIO

VID1_VCCIO

1 2

12

PC806

EMC@

0.1U_0402_25V6

1 2

PR802

2

1

0_0402_5%

PR826

@

1

2

0_0402_5%

12

1

PC807

PC801

2

EMC@

2200P_0402_50V7K

1

PC802

2

10U_0603_25V6M

PR803

@

0_0402_5%

VIN_VCCIO

1

PC800

@

2

0.1U_0402_25V6

VID0_VCCIO

VID1_VCCIO

EN_VCCIO

12

13

PU800

EN

12

PVIN

11

PVIN

10

TPS62134ARGT_QFN16_3X3

AVIN

9

VID0

8

VID1

+1.0V_PRIM_CORE controller(35.7), Support component(35.8)

PR814

0_0402_5%

2

SIO_SLP_S0#10,31,45,57

SIO_SLP_SUS#10,30,32 ,44,55,56

B B

CPU_B+

+3VALW

12

PR817

PR818

10K_0402_1%

VID0_PRIM_CORE

VID1_PRIM_CORE

1

12

Vout=1.0V

PR820

PR821

@

2

10K_0402_1%

A A

10K_0402_1%

PL802

EMC@

HCB1608KF-121T30_0603

1 2

CORE_VID017

CORE_VID117

12

PC817

PC816

EMC@

0.1U_0402_25V6

1

PR815

1 2

130K_0402_1%

PR816

@

0_0402_5%

VIN_PRIM

12

PC811

2200P_0402_50V7K

1

12

PC812

2

10U_0603_25V6M

@

PR822

0_0402_5%

1

PR823

@

0_0402_5%

1 2

12

2

1

PC810

2

0.1U_0402_25V6

EN_PRIM_COREP

PU801

12

11

10

9

VID0_PRIM_CORE

13

EN

PVIN

TPS62134DRGT_QFN16_3X3

AVIN

VID0

VID1

8

VID1_PRIM_CORE

14

PC819

470P_0402_50V7K

@

10K_0402_1%

1

15

LPM

SS

7

SS_PRIM

12

PR813

2

+3VALW

+1.0V_PRIM_COREP

17

TP

PGND16PGND

AGND

6

1

VOS

2

SW

3

SW

4

PG

FBS

5

@EMC@

4.7_0603_5%

1

1UH_1277AS-H-1R0N-P2_3.3A_30%

LX_PRIM

1.0V_PRIM_CORE_PG30

12

PR735

@

100K_0402_5%

+3VALW

1

PR825

@

2

100K_0402_1%

PR819

2

PL803

1 2

1

@EMC@

680P_0402_50V7K

1

2

@

PR824

0_0402_5%

PC818

2

Main: TOKO, 2nd: CLSN Package: 3.2 x 2.5 x 1.2 Idc=3.3A, Isat=4.6A DCR=48mohm (Typ.)

12

1

PC814

PC813

2

22U_0603_6.3V6M

PC815

@

22U_0603_6.3V6M

+1.0V_PRIM_COREP

12

PJP801

@

2

+1.0V_PRIM_COREP +1.0V_PRIM_CORE

+1.0V_PRIM_CORE TDC 1.79A Peak Current 2.57A

112

JUMP_43X79

Security Classification

2014/10/17 2014/12/05

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2014/10/17 2014/12/05

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

PWR_VCCIO/PRIM(TPS62134*2)

LA-D891P

1

57 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

VCC_CORE controller(36.1), Support component(36.3)

+1.0V_VCCST

PR903

12

1

PR900

PR901

@

45.3_0402_1%

PCH_PWROK10

IMVP_VR_ON_P32

2

PR921

0_0402_5%

1 2

FCCM_GT60 PWM1_GT60

PWM2_GT60

470K_0402_5%_ TSM0B474J4702RE

D D

H_PROCHOT#11,30,50,51,54

PH900

470K_0402_5%_ TSM0B474J4702RE

1 2

2

1

PR919

27.4K_0402_1%

PC905

2200P_0402_50V7K

1

VCC_GT_SENSE15

C C

VSS_GT_SENSE15

ISUMP_GT60

10K_0402_5%_B25/50 4250K

ISUMN_GT60

B B

A A

PH901

PR925

2.61K_0402_1%

@

330P_0402_50V7K

0.01U_0402_50V7K

12

2

PC906

68P_0402_50V8J

1

PC908

1 2

PC911

1 2

12

PC926

.1U_0402_16V7K

3.92K_0402_1%

1 2

2

PR926

PR917

10K_0402_1%

1

PR920

12

PC910

@

0.082U_0402_16V7K

12

PC912

11K_0402_1%

PC922

0.022U_0402_16V7K

1 2

PC925

0.022U_0402_16V7K

1

ISEN1_GT60

ISEN2_GT60

2

220P_0402_50V7K

1200P_0402_50V7K

1 2

12

PC913

0.1U_0402_25V6

2

PC907

1 2

PC909

0.022U_0402_25V7K

VIDSCLK14

VIDALERT_N14

VIDSOUT14

1 2

PC903

47P_0402_50V8J~D

PR918

110K_0402_1%

1 2

PC904

330P_0402_50V8J

1

PR922

1K_0402_1%

1 2

PR923

1 2

2.87K_0402_1%

1

PR924

2K_0402_1%

PR930

1K_0402_1%

1 2

PR932

309_0402_1%

1 2

PR905

PR907

PR909

2

PC915

2200P_0402_50V7K

1 2

ISEN1_GT

ISEN2_GT

1

0_0402_5%

1 2

0_0402_5%

1 2

0_0402_5%

PR911

100_0402_1%

1 2

+3VALW

P_SYS30,51

VCCSENSE14

VSSSENSE14

2

1

2

PR902

75_0402_1%

100_0402_1%

PR912 1.91K_0402_1%

1

PR914

1 2

PR915

1 2

1

2

3

4

5

6

7

8

9

10

PH902

1 2

PR935

27.4K_0402_1%

PC923

2200P_0402_50V7K

1 2

2200P_0402_50V7K

PC900

0.1U_0402_25V6

1 2

PR906

49.9_0402_1%

1 2

PR908

0_0402_5%

1 2

PR910

10_0402_1%

2

0_0402_5%

37

38

39

40

41

PAD

VR_ENABLE

PSYS

IMON_B

NTC_B

COMP_B

FB_B

S IC ISL95857AHRTZ-TS2778 TQFN 40P PWM

RTN_B

ISUMP_B

ISUMN_B

ISEN1_B

ISEN2_B

PC914

330P_0402_50V7K

1

PR927

1 2

90.9K_0402_1%

1

10K_0402_1%

PC927

68P_0402_50V8J

1 2

PC929

1

2

1 2

1.5K_0402_1%

PC939

@

1 2

330P_0402_50V7K

PC941

0.01U_0402_50V7K

2

1

VR_HOT#

VR_READY

Change part number to MP

FCCM_B11PWM1_B12PWM2_B13IMON_A

2

PR933

PR939

5.49K_0402_ 1%

1 2

PR946

316_0402_1%

1

PR947

12

SCLK

SA0000A4A0L

14

IMON_IA

36

ALERT#

PU900

PC940

@

NTC_IA

0.082U_0402_16V7K

35

NTC_A15COMP_A

2

SDA

16

COMP_IA

PR948

PC936

34

VCC

FB_IA

1

2K_0402_1%

2

12

1200P_0402_50V7K

32

33

VIN

PROG1

FB_A17RTN_A18ISUMP_A

12

PC901

1U_0603_10V6K

78.7K_0402_1%

1

48.7K_0402_1%

1

31

PROG2

PWM_C

FCCM_C

ISUMN_C

ISUMP_C

RTN_C

COMP_C

IMON_C

PWM_A

FCCM_A

ISUMN_A

19

20

PR950

4.42K_0402_1%

1

0_0402_5%

1 2

1

PC902

2

0.22U_0603_25V7K

PR913

2

PR916

2

30

29

28

27

26

25

FB_C

24

23

22

21

PC931

@

0.01U_0402_16V7K

1 2

PC934

0.068U_0402_25V6K

1

PR949

11K_0402_1%

1

10K_0402_5%_B25/50 4250K

2

PR904

0_0402_5%

PWM_SA 59

FCCM_SA 59

FB_VSA

COMP_VSA

IMON_VSA

PWM_VCORE 59

FCCM_VCORE 59

12

PC917

2200P_0402_50V7K

12

PR940

1K_0402_1%

2

PH904

1 2

1

2

PR936

383_0402_1%

PC932

.1U_0402_16V7K

+5VALW

CPU_B+

PC916

10P_0402_50V8J

PC930

330P_0402_50V7K

1

2

ISUMN_VCORE 59

ISUMP_VCORE 59

PR929

768_0402_1%

1 2

PC918

2200P_0402_25V7K

PR938

316_0402_1%

1 2

12

PR928

7.32K_0402_1%

1

2

12

PC919

2200P_0402_25V7K

1

PR942

2

133K_0402_1%

12

PR943

2K_0402_1%

1

PC933

2

680P_0402_50V7K

2200P_0402_25V7K

PR941

1.69K_0402_1%

1

PC924

1 2

2

1 2

PR937

1K_0402_1%

12

1

PC937

2

@

0.082U_0402_16V7K

.1U_0402_16V7K

PC920

0.022U_0402_16V7K

0.01U_0402_50V7K

330P_0402_50V7K

PC928

1

2

PC935

1 2

@

1

2

PC921

PC938

ISUMN_SA 59

1

12

PR934

0.01U_0402_25V7K

2

11K_0402_1%

2

12

PR931

2.61K_0402_1%

VSA_SEN- 16

VSA_SEN+ 16

PH903

10K_0402_5%_B25/50 4250K

ISUMP_SA 59

Security Classification

2014/10/17 2014/12/05

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

5

4

3

2014/10/17 2014/12/05

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

PWR_ISL95857

LA-D891P

1

58 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

VCC_CORE/SA Dr. MOS (36.2), Support component(36.3)

4

3

2

1

D D

C C

B+ CPU_B+

PL1000

EMC@

HCB2012KF-121T50_0805

1 2

PL1002

EMC@

HCB2012KF-121T50_0805

1 2

1

+

PC1032

PC1030

2

@

47U_D3_20VM_R45M

1

+

PC1028

2

47U_D3_20VM_R45M

FCCM_VCORE58

1

+

PC1003

2

47U_D3_20VM_R45M

PWM_VCORE58

12

+

PC1005

PC1004

2

@

10U_0603_25V6M

12

PC1006

10U_0603_25V6M

PR1002

0_0402_5%

1 2

1

PR1004

0_0402_5%

1

PC1007

2

PC1008

2

EMC@

1000P_0402_50V7K

1 2

PC1002 0.1U_0603_25V7K

1

PR1005

0_0603_5%

12

PC1010

1000P_0402_50V7K

1 2

2.2U_0402_6.3V6K

2

+5VALW

GH_VCORE

PT1001

@

PU1103

13

NC

14

VCC

1

PWM

2

FCCM

3

BOOT

4

GH

5

VSWH

AOZ5049QI_QFN24_5X3P5

VIN

VSWH

PGND

6

12

+VCC_CORE

10

GL

9

GL

8

11

7

GL_VCORE

PT1002

@

1

PR1006

2

10_1206_5%

@EMC@

1

PC1009

2

33P_0603_50V8J

@EMC@

0.15UH_MMD-10BD-R15MEM2L_35A_20%

PR1007

3.65K_0603_1%

1 2

1

2

ISUMP_VCORE

PL1001

12

PR1128

0_0402_5%

58

ISUMN_VCORE

58

CPU_B+

12

1

PC1120

PC1119

2

EMC@

0.1U_0402_25V6

B B

1

PC1122

PC1121

2

0.1U_0402_25V6

10U_0603_25V6M

PWM_SA58

FCCM_SA58

12

1

PC1123

2

@

10U_0603_25V6M

PR1124

0_0402_5%

1

PR1123

0_0402_5%

2.2U_0402_6.3V6K

12

2

PC1118 0.1U_0603_25V7K

1 2

0_0603_5%

PC1124

1

1 2

PR1125

+5VALW

2

GH_SA

PT1003

@

PU1102

13

NC

14

VCC

1

PWM

2

FCCM

3

BOOT

4

GH

5

VSWH

AOZ5029QI_QFN24_5X3P5

VIN

VSWH

PGND

6

12

+VCC_SA

10

GL

9

GL

8

11

7

GL_SA

PT1004

@

1

PR1126

4.7_1206_5%

2

@EMC@

1

2

PC1126

680P_0603_50V7K

@EMC@

0.47UH_MHCI06015-R47MR8A7R45_10.8A_20%

PR1127

3.65K_0603_1%

1 2

1

2

PL1102

58

1

PR1129

0_0402_5%

2

58

ISUMP_SA

A A

ISUMN_SA

Security Classification

2011/06/02 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2011/06/02 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

PWR_VCORE, +VCCSA

LA-D891P

1

1.0

59 65Tuesday, Decembe r 20, 2016

of

Vinaﬁx.com

5

smd.db-x7.ru

VCC_GT Dr. MOS (36.2), Support component(36.3)

4

3

2

1

D D

C C

CPU_B+

12

PC1106

EMC@

1000P_0402_50V7K

12

PC1107

PC1104

@

EMC@

10U_0603_25V6M

1000P_0402_50V7K

12

PC1105

@

10U_0603_25V6M

PWM1_GT58

FCCM_GT58,60

12

PC1103

10U_0603_25V6M

PR1101

0_0402_5%

1

PR1103

0_0402_5%

2.2U_0402_6.3V6K

12

2

1

PC1102 0.1U_0603_25V7K

1

PR1105

0_0603_5%

PC1100

1 2

2

+5VALW

2

GH_GT1

PT1101

@

PU1100

13

NC

14

VCC

1

PWM

2

FCCM

3

BOOT

4

GH

5

VSWH

AOZ5029QI_QFN24_5X3P5

VIN

VSWH

PGND

6

12

+VCC_GT

10

GL

9

GL

8

11

7

GL_GT1

PT1100

@

1

PR1106

4.7_1206_5%

2

@EMC@

1

PC1108

2

680P_0603_50V7K

@EMC@

0.15UH_MHCB06024-R15M-C1R885_27A_20%

12

PR1107

3.65K_0603_1%

ISUMP_GT

1 2

12

PR1108

58,60

ISEN1_GT

100K_0402_1%

PL1100

58

12

PR1109

10_0402_1%

58,60

ISUMN_GT

CPU_B+

1

PC1115

EMC@

B B

12

PC1116

2

0.1U_0402_25V6

PC1112

@

EMC@

0.1U_0402_25V6

10U_0603_25V6M

A A

12

PC1113

@

10U_0603_25V6M

PWM2_GT58

FCCM_GT58,60

12

PC1114

10U_0603_25V6M

PR1114

0_0402_5%

1 2

PR1116

0_0402_5%

2.2U_0402_6.3V6K

12

1 2

PC1111 0.1U_0603_25V7K

1 2

PR1117

0_0603_5%

PC1109

1 2

+5VALW

GH_GT2

PT1103

@

PU1101

13

NC

14

VCC

1

PWM

2

FCCM

3

BOOT

4

GH

5

VSWH

AOZ5029QI_QFN24_5X3P5

VIN VIN

VSWH

PGND

6 12

+VCC_GT

10

GL

9

GL

8

11

7

GL_GT2

PT1102

@

12

PR1118

4.7_1206_5%

@EMC@

12

PC1117

680P_0603_50V7K

@EMC@

0.15UH_MHCB06024-R15M-C1R885_27A_20%

1

PR1119

2

3.65K_0603_1%

ISUMP_GT

12

PR1120

100K_0402_1%

ISEN2_GT

PL1101

1 2

58

58,60

12

PR1121

10_0402_1%

58,60

ISUMN_GT

Security Classification

2011/06/02 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2011/06/02 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet

2

Date: Sheet of

Compal Electronics, Inc.

PWR_+VCCGT

LA-D891P

1

1.0

60 65Tuesday, Decembe r 20, 2016

of

Vinaﬁx.com

A

smd.db-x7.ru

B

C

VCC_CORE output cap(36.4), VCC_GT output cap(36.5), VCC_SA output cap(36.6)

+VCC_CORE +VCC_GT

D

E

VCC_CORE 220uF_B2 X 2

1 1

2 2

1

+

PC1200

2

@

220U_B2_2.5VM_R15M

12

PC1237

47U_0805_6.3V6M

12

PC1259

1U_0201_6.3V6M

1

+

PC1201

2

220U_B2_2.5VM_R15M

12

PC1246

47U_0805_6.3V6M

1

PC1260

2

1U_0201_6.3V6M

1

+

PC1202

2

12

PC1230

2

@

22U_0603_6.3V6M

220U_B2_2.5VM_R15M

12

PC1222

PC1233

47U_0805_6.3V6M

12

PC1262

PC1261

1U_0201_6.3V6M

1

PC1231

2

@

22U_0603_6.3V6M

12

PC1234

47U_0805_6.3V6M

1

PC1263

2

1U_0201_6.3V6M

1

PC1241

2

12

1

2

PC1242

2

22U_0603_6.3V6M

12

1

PC1247

PC1220

2

47U_0805_6.3V6M

1

PC1265

PC1264

1U_0201_6.3V6M

2

1U_0201_6.3V6M

47uF_0805 X 17 1uF_0201 X 35

1

PC1251

2

47U_0805_6.3V6M

1

PC1266

2

1U_0201_6.3V6M

PC1239

PC1238

2

47U_0805_6.3V6M

12

PC1268

PC1267

1U_0201_6.3V6M

12

1

PC1243

PC1240

PC1252

2

47U_0805_6.3V6M

12

1

PC1270

PC1269

2

1U_0201_6.3V6M

47U_0805_6.3V6M

12

PC1271

1U_0201_6.3V6M

1

12

PC1244

PC1245

2

47U_0805_6.3V6M

1

12

PC1272

2

1U_0201_6.3V6M

PC1226

47U_0805_6.3V6M

12

PC1274

PC1273

1U_0201_6.3V6M

PC1275

1U_0201_6.3V6M

1

+

PC1208

PC1207

2

220U_B2_2.5VM_R15M

1

12

PC1353

PC1277

2

@

10U_0603_6.3V6M

22U_0603_6.3V6M

1

12

PC1318

2

PC1279

47U_0805_6.3V6M

1

+

PC1210

PC1209

2

1

2

1

2

@

220U_B2_2.5VM_R15M

1

PC1308

2

@

22U_0603_6.3V6M

12

PC1258

47U_0805_6.3V6M

PC1312

PC1321

2

@

22U_0603_6.3V6M

12

PC1348

PC1347

47U_0805_6.3V6M

VCC_GT 220uF_B2 X 2 47uF_0805 X 13 1uF_0201 X 18

1

PC1254

2

@

22U_0603_6.3V6M

12

PC1314

47U_0805_6.3V6M

1

PC1335

PC1331

2

12

@

22U_0603_6.3V6M

1

PC1350

PC1334

2

47U_0805_6.3V6M

1

PC1306

PC1253

2

22U_0603_6.3V6M

12

47U_0805_6.3V6M

@

22U_0603_6.3V6M

1

PC1330

PC1352

2

47U_0805_6.3V6M

1

PC1255

PC1313

2

12

@

22U_0603_6.3V6M

1

PC1332

PC1315

2

47U_0805_6.3V6M

1

PC1319

PC1337

2

12

@

22U_0603_6.3V6M

PC1333

47U_0805_6.3V6M

1

PC1351

PC1320

2

@

22U_0603_6.3V6M

1

PC1280

PC1310

2

@

22U_0603_6.3V6M

1

12

PC1289

PC1288

2

1U_0201_6.3V6M

3 3

+VCC_SA

1

+

PC1217

2

@

220U_B2_2.5VM_R15M

1

12

PC1364

PC1360

2

1U_0201_6.3V6M

12

PC1290

1U_0201_6.3V6M

1

PC1368

2

@

22U_0603_6.3V6M

12

PC1370

1U_0201_6.3V6M

12

1

PC1291

PC1292

PC1293

2

1U_0201_6.3V6M

1

12

PC1369

PC1361

PC1357

1

PC1365

2

47U_0805_6.3V6M

12

1U_0201_6.3V6M

47U_0805_6.3V6M

12

PC1362

PC1356

1U_0201_6.3V6M

12

PC1294

1U_0201_6.3V6M

1

PC1359

2

47U_0805_6.3V6M

1

PC1355

2

1U_0201_6.3V6M

12

PC1295

PC1296

1U_0201_6.3V6M

1

12

PC1366

2

47U_0805_6.3V6M

PC1297

1U_0201_6.3V6M

12

PC1358

PC1329

47U_0805_6.3V6M

VCC_SA 220uF_B2 X 0 47uF_0805 X 7 1uF_0201 X 7

1U_0201_6.3V6M

47U_0805_6.3V6M

1

12

PC1299

PC1298

2

1U_0201_6.3V6M

1

12

PC1301

PC1300

2

1U_0201_6.3V6M

1

PC1303

PC1302

2

1U_0201_6.3V6M

12

1

PC1305

PC1304

2

1U_0201_6.3V6M

1

PC1276

2

1U_0201_6.3V6M

1

12

PC1278

PC1323

2

1U_0201_6.3V6M

1

12

PC1309

PC1311

2

1U_0201_6.3V6M

1

12

PC1281

1U_0201_6.3V6M

1

PC1282

2

PC1283

2

1U_0201_6.3V6M

1

12

PC1284

PC1285

2

1U_0201_6.3V6M

12

1

PC1287

PC1286

2

1U_0201_6.3V6M

12

PC1338

1U_0201_6.3V6M

1

12

PC1339

PC1340

2

1U_0201_6.3V6M

PC1341

1U_0201_6.3V6M

12

PC1343

PC1342

1U_0201_6.3V6M

4 4

Security Classification

2011/06/02 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2011/06/02 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Rev

Date: Sheet

Date: Sheet of

D

Date: Sheet

Compal Electronics, Inc.

PWR-CPU DECOUPLING

LA-D891P

E

1.0

61 65Tuesday, December 20, 2016

of

Vinaﬁx.com

I2C

smd.db-x7.ru

I2C0

5

U6

U7

I2C0_SCL

I2C0_SDA

NC

4

3

2

1

NC

D D

+3V_PRIM

4.7K

U9

I2C1_SCK_TS

I2C1

U8

I2C1_SDA_TS

+1.8VA

PCH

AH10

SKYCAM_I2C_CLK

I2C2

AH9

SKYCAM_I2C_DATA

C C

AT7

PMIC_I2C_SCL

I2C3

AP5

PMIC_I2C_SDA

2.2K

NC

4.7K

PH RES on PCH page

0-ohm

2.2K

PH RES on SkyCAM page

G5

F5

Skycam PMIC

F6

WF_I2C_CLK

D6

WF_I2C_DATA

+1.8V_IO_OUT

2.2K

WF_I2C_CLK

WF_I2C_DATA

Touch Sensor

World Facing Camera

NC

+1.8VA

2.2K

AF12

UF_I2C_CLK

I2C4

AF11

UF_I2C_DATA

B B

2.2K

N3

ISH_I2C0_SCL

ISH_I2C0

ISH_I2C1

A A

M4

ISH_I2C0_SDA

N2

ALS_I2C1_SCL

N1

ALS_I2C1_SDA

2.2K

PH RES on UFCAM page

+3VS

2.2K

PH RES on Sensor page

+3VS

2.2K

PH RES on Sensor page

0-ohm

0-ohm 0-ohm

0-ohm

Front Camera

Gyro + Accelerometer

Compass

ALS Sensor

ISH_I2C2

AD12

ISH_I2C2_SCL

AD11

ISH_I2C2_SCL

5

NC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

2041/09/08 2013/10/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P62-PCH I2C Block Diagram

62 65Tuesday, December 20, 2016

1

62 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

A

smd.db-x7.ru

B

C

+3V_PRIM

D

E

2.2k

NC

W3

V3

1K

SMBUS Address [0x9a]

PCH

PD1

P-Sensor

0-ohm

BATTERY

DDR_XDP_SMBCLK

R8R7DDR_XDP_SMBDAT

R9W2SML0CLK

SML0DATA

[0x70]

[0x28]

MUX1

[0x16]

+3V_PRIM

1K

1 1

2

HEAD EC

D3

SML1_SMBCLK

A7

SML1_SMBDAT

B7

UPD1_TD1_PS_SMBCLK

D2

UPD1_TD1_PS_SMBDAT

C7D7PBAT_SMBCLK

PBAT_SMBDAT

+3VLDO_EC

1K

+3VLDO_EC

2.2K 2.2K

+3VLDO_EC

1K

SML1_SMBCLK

SML1_SMBDAT

1K

0-ohm

+3VS_MUX

1K

MOSFET

100-ohm

2.2k

[0x22]

DDR_XDP_SMBCLK

DDR_XDP_SMBDAT

XDP

2

2.2K 2.2K

B8C8CHG_MCP23017_SMBCLK

CHG_MCP23017_SMBDAT

+3VLDO_EC

2.2K

3 3

A9D8BASE_SMBCLK

BASE_SMBDAT

L12

UPD2_TD2_USH_SMBCLK

M12

UPD2_TD2_USH_SMBCLK

+3VLDO_EC

1K

2.2K

1K

4 4

MOSFET

0-ohm

+3VS_MUX

1K

Charger

I/O Expander

POGO conn

USH

PD2

0-ohm

[0x12]

[0x42]

[0x7E]

MUX2

[0x20]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2041/09/08 2013/10/28

D

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Nu mber Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P63-SMBus Block Diagram

63 6 5Tuesday, December 20 , 2016

E

63 6 5Tuesday, December 20 , 2016

of

1.0

Vinaﬁx.com

5

smd.db-x7.ru

4

3

2

1

+RTCVCC

SRTCRST#

[AC in] for VBUS1/VBUS2/VBUS3

+VBUS1_PD_20V

+3V_LDO

PD Output

D D

EC Output

EC Input

EC Output ALWON

EC Input

EC pay attention timing

C C

B B

EC Output

PCH Output

EC Output

PCH Output

EC Output

PCH Output

EC Output

PCH Output

EC Output

PCH Output

EC Output

PCH Output

EC Output RUN_ON_EC (Reserved)

EC Input

EC Output

A A

EC Output

PCH Output

EN_PD_HV1

AC1_DISC#

DCIN1_EN

VBUS1_ECOK

+CHG_VIN_20V

B+

ACAV_IN

+3VALW

+5VALW

3VALW_PG

PWR_SW_IN#

SUSCLKPCH Outpu t

PCH_DPWROK

SIO_SLP_SUS#

PCH_PWR_EN

+3V_PRIM (U21)

+1.8VA (PU720)

+1.0V_PRIM_CORE (PU801)

+1.0VA (PU700)

MPHYP_PWR_EN (EXT_PWR_GATE#)

+1.0V_MPHYGT

SIO_SLP_S0#

SUSACK#

PCH_RSMRST#

SUSWARN#

AC_PRESENT

SIO_SLP_S5#

SIO_SLP_A#PCH Output

SIO_SLP_WLAN#

AUX_EN_WLAN

+3VS_WLAN

SIO_PWRBTN# 16ms < T < 4s

SIO_SLP_S4# (SUS_ON_EC)

SUS_ON_EC (SUS_ON) Reserved

+1.2V_DDR

+1.0V_VCCST

SIO_SLP_S3# (RUN_ON_P) (AND with SIO_SLP_S0# o/p VCCSTG_EN)

+3.3VDX_SS

+1.0V_VCCST (SIO_SLP_S0# AND SIO_SLPS4# o/p VCCST-EN)

+1.8VA (SIO_SLP_SUS#)

+3VS

+5VS

RUNPWROK (ALL_SYS_PWRGD)

IMVP_VR_ON_P (IMVP_VR_ON AND with SIO_SLP_S3# o/p H_VCCST_PWRGD_P)

VCORE_PG (PCH_PWROK,PU900)

+VCC_SA

SYS_PWROK

PCH_PLTRST# (AND itself to PLT_RST#)

+VCC_CORE

+VCC_GT

T200

[Battery only, AC absent]

Ta

Tb

Tc

Td

Te

Tf +5VALW Tf

*Varies by different power path scenario

Tg Tg

Th

Ti

Tj

Tk

Tl

1ns < Th < 4s

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

EC Output

T15

T16

T17

T18

B+

PWR_SW_IN#

ALWON Td

EC Input

+3VALW

3VALW_PG

T19

T20

Minimum duration of PWRBTN # assertion = 16mS after SUSCLK stable

T21

T22

T23

T24

T25

T26

T27

T28

T29

T30

T31

T32

T33

1ns < Th < 4s

Te

T34

T35

T36

T37

T38

T39

Discrete Power On Sequence

[AC in]

+VBUS_PD_20V

Ta

3V_LDO

Tb

EN_PD_HV1

Tc

AC1_DISC#

Td Te

VBUS1_ECOK

Tf

+CHG_VIN_20V

Tg

B+

Th

ACAV_IN

Ti

ALWON

Tj

+3VALW

Tk

+5VALW

Tl

ITEM Measure Point

DSW_ON

T1

+3VALW_DSW

T2

+3VALW_DSW

T3

PCH_DPWROK

T4

SIO_SLP_SUS#

T5

PCH_PWR_EN

T6

PCH_PWR_EN

T7

PCH_PWR_EN

T8

PCH_PWR_EN

T9

PCH_PWR_EN

T10

PCH_PWR_EN

T11

EXT_PWR_GATE#

T12

PCH_PWR_EN

T13

PCH_PWR_EN

T14

PCH_RSMRST#

T15

PCH_RSMRST#

T16

PCH_RSMRST#

T17

SIO_SLP_S5#

T18

SIO_SLP_S5#

T19

SIO_SLP_WLAN#

T20

AUX_EN_WLAN

T21

SIO_PWRBTN#

T22

SIO_SLP_S4#

T23

SUS_ON_EC

T24

SUS_ON_EC

T25

SUS_ON_EC

T26

SIO_SLP_S4#

T27

SIO_SLP_S3#

T28

RUN_ON_EC

T29

RUN_ON_EC

T30

RUN_ON_EC

T31

RUN_ON_EC

T32

RUN_ON_EC

T33

RUN_ON_EC

T34

+3VS

T35

RUNPWROK

T36

VR_ON

T37

VCORE_PG

T38

VR_ON

T39

SYS_PWROK

T40

PCH_PLTRST#

T41

PCH_PLTRST#

T42

To To To To To To To To To To To To

To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To

+3V_LDO

EN_PD_HV1

AC1_DISC#

DCIN1_EN

VBUS1_ECOKDCIN1_EN

+CHG_VIN_20V

B+ ALWON

ACAV_IN

ALWON

+3VALW

+5VALW

3VALW_PG

+3VALW_DSW

SUSCLK

PCH_DPWROK

SIO_SLP_SUS#

PCH_PWR_EN

+3V_PRIM

+1.8V_PRIM

+0.95V_PRIM

+1.0V_PRIM

EXT_PWR_GATE#

SIO_SLP_S0#

+1.0VA_GATE

SUSACK#

PCH_RSMRST#

SUSWARN#

AC_PRESENT

SIO_SLP_S5#

SIO_SLP_A#

SIO_SLP_WLAN#

AUX_EN_WLAN

+3VS_WLAN

SIO_SLP_S4#

SUS_ON_EC

+1.8V_MEM

+1.2V_DDR

+1.0V_VCCST

SIO_SLP_S3#

RUN_ON_EC

+0.85VS_VCCIO

+1.0VS_VCCSTG

+1.2VS

+1.8VS

+3VS

+5VS

RUNPWROK

VR_ON

VCORE_PG

+VCC_SA

SYS_PWROK

PCH_PLTRST#

+VCC_CORE

+VCC_GT

TimeMeasure PointITEM

Time

Tc Th Td Te Tf Tg

update

[Battery only, AC absent]

Measure PointITEM Time

B+

POWER_SW_IN# Low pluse width

POWER_SW_IN#

ALWON +3VALW

+3VALW 3VALW _PG

To To To

To To To To

+3V_LDO

ALWON

+5VALW

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P64-Power Up Sequence

1

64 65Tuesday, December 20, 2016

of

1.0

Vinaﬁx.com

SUS_STAT#

smd.db-x7.ru

PCH_PLTRST#

H_CPUPWRGD

SIO_SLP_S3#

5

4

3

2

1

D D

C C

SYS_PWROK

IMVP_VR_ON (H_VCCST_PWRGD)

+VCC_CORE

+VCC_GT

+VCC_SA

VCORE_PG (PCH_PWROK)

RUN_ON_EC

+0.85VS_VCCIO

+1.0VS_VCCSTG

+1.2VS

+1.8VS

+3VS

+5VS

RUNPWROK (ALL_SYS_PWRGD)

SIO_SLP_S4#

SUS_ON_EC

+1.0V_VCCST

+1.2V_DDR

+1.8V_MEM

B B

SIO_SLP_S5#

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P65-Power Down Sequence

65 65Tuesday, December 20, 2016

1

65 65Tuesday, December 20, 2016

of

1.0

Compal LA-D891P Schematics Rev1.0

Specifications and Main Features

Frequently Asked Questions

User Manual