Compal LA-D891P Schematics Rev1.0

Vinafix.com

A

smd.db-x7.ru

B

C

D

E

MODEL NAME : LA-D891P

PCB NO : DAA000CK000

BOM P/N : 431A4E31L01

1 1

Dell/Compal Confidential

2 2

Schematic Document

Pebble Creek (Kabylake U)

3 3

2016-12-20

Rev: 1.0

ZZZ

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

Date: Sheet of

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

P01-Cover Page

P01-Cover Page

P01-Cover Page

LA-D891P

LA-D891P

LA-D891P

E

1 65Tuesday, December 20, 2016

1 65Tuesday, December 20, 2016

1 65Tuesday, December 20, 2016

of

of

1.0

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1.0

Vinafix.com

A

smd.db-x7.ru

12.3" 3:2
Samsung WUXGA+

ALS
AMS-TAOS TSL2591

Touch Cntrl
Wacom G12T-W9015

1 1

2 2

RFFEM

uSD Connector

USB3.0 / DP x 2lanes or DP x 4 lanes

VBUS

Port-A
USB Type-C
ALT mode
with PD

3 3

Port-B
USB Type-C
ALT mode
with PD

CC 2

USB (Top)

USB (Bottom)

p.40

USB3.0 / DP x 2lanes or DP x 4 lanes

VBUS

CC 2

USB (Top)

USB (Bottom)

p.40

Gyro + Accelerometer
ST LSM6DS3TR

Compass
ST LIS3MDLTR

Finger Print Reader
NB 2023-S

Smart Card Reader
NXP TDA8034HN

on IO board

SSD M.2 2280
Slot 3-Key-M

WWAN 4G LTE
M.2 3042 Slot 2-Key-B

Hardware Crypto Accelera tor

Module : EM7455

LTE Coex

WLAN / BT 4.1
M.2 2230 Slot 1-Key-A
WiGig (UI
3x3(UI)

Module :
8265NGW/QCNFA344A/18265NGW

SD4.0/SDXC

SD_WP

p.27

USB3.0 TypeA
BC1.2
with Power Share
TI TPS2546

MOSFET

VBUS PP_5V0
CC

TI-ACE 65982-D

VBUS PP_5V0
CC

TI-ACE 65982-D

I2C

p.35

MOSFET

I2C to EC

p.36

p.23

p.25

uSIM

p.26

p.24

CHRG_IN

From EC

5V_ALW

CHRG_IN

From EC

5V_ALW

p.22

p.31

p.22

p.31

p.31

SPI

0
8
2
2

2
4
0
3

0
3
2
2

GPIO
(BIOS Controlled)

p.39

to EC

to EC

to PCH

to PCH

on WF camera module

SPI ROM 16M (Main)

SPI ROM 4M(2nd)

NPCT650JBAYX

USH Control Vault
Broadcom 58102

RDIF/NFC
Antenna

A

RealTek
RTS5242 PCIe to SD

USB3.0

5V@1.5A

Parade
MUX
PS8743A

Parade
MUX
PS8743A

Kickstand Open /Close detect ion
(mechanical switch)

Module : DWRFID1603

BC1.2
TI TPS2546

p.39

p.39

A

SAR Proximity Sensor
Smtech SX9310

Hall Sensor
APX8132 or AH1806-W

p.7

p.31

IOB conn p.43

p.27

p.39

DP1.2
MUX

p.40

eDP x2 lanes

I2C

I2C

SPI SPI#2

I2C

SPI

USB 2.0

PCIe x 2lanes

GNSS I2C

PCIe x 2lanes

USB 3.0 / SSIC

USB 2.0

PCIe x 1lane

PCIe x 1lane

USB2.0

eLBS

CLINK

PCIe x 1lane

USB2.0

USB2.0

USB3.0

DP1.2 x 4lanes

USB3.0

USB3.0

DP1.2 x 4lanes

I2C 3

p.31

p.31

p.42 p.30

TABLET

B

eDP

ISH

I2C

I2C (iSH)

SPI#1

USB#7

Channel A

Channel B

CSI-2#2

CSI-02#0

USB2.0#5

KabyLake U

PCIe#7,8

I2C (iSH)

PCIe#11/PCIe#12

USB3 # 2 / SSIC

USB2 # 4

PCIe#5

PCIe#6

USB2#7

UART

CLINK

PCIe#9

USB2#9
UART

USB3#3

DDI#2

USB3.0#1

USB3.0#4

DDI#1

LPC

EC
MEC1641

USB2#2

I2C_CLK

I2C_DAT

I2C_INT

I2C

I2C

HDA

GPIO

Memory Bus

Memory Bus

MIPI CSI-2 x 2lanes

I2C

I2C

MIPI CSI-2 x 2lanes

D+/D-

4x DMIC

3DMIC on M/B
1DMIC on WFCAM

Dock_Detect

Channel A - 4GB

Channel A - 4GB
LPDDR3 1866
32Gb x 32 QDP

Channel B - 4GB

Channel B - 4GB
LPDDR3 1866
32Gb x 32 QDP

5MP FFC
5BF501T2/OV5670

8MP RFC
5BA802T2/OV8858

Face IR Module
LiteOn 5SF106N2B

HDA

1.5V

p.28

EC JTAG

SPI Programmer

USB PD Debug

DCI Debug

Audio Codec
ALC3253-CG

p.19

p.20

p.33

SKYCAM PMIC
TPS68470YFFR_DBSGA56

I2C

p.33

p.43

Universal
Headset Jack

p.28 p.29

2x
Speaker

p.29

XDP DEbug

LPC Debug

APS Debug

Coin Cell

I2C_INT

CHRG_IN

C

5V/2A

p.34

GND

DET_L

I2C1
CLK

I2C1
DAT

I2C1
INT

5V

D+

D-

12V

DET_R

GND

GND

DET_L

I2C1
CLK

I2C1
DAT

I2C1
INT

5V

D+

D-

12V

DET_R

GND

3.3V LDO Boost

VSW_3V3

SPI ROM 2MB

USB 2.0 D+
USB 2.0 D-

WCFW_EN

POGO_DET_R#

CHG_DICS(NC)

HEAD_DET# GPIO

VR_OUT

+VCC_EC

WC_DISC

I2C#1_INT

I2C#1_DAT

I2C#1_CLK

D

SPI

WC_OUT

GND

TPS61200

A/D

A/D

SPI

I2C_CLK

I2C_DAT

I2C_INT

VCC_EC
VSW_3V3

VCC

CSR1021

WC PRU Board

TX/RX

I2C_CLK

I2C_DAT

I2C_INT

GPIO
GPIO

KSO/KSI

GPIO

Pi-Matching i-pex conn

PTP_MODE#
PTP_SLP#

Keyboard Matrix

BT ON/OFF ButtonGPIO

I2C_CLK

I2C_DAT

I2C_INT

PTP_MODE#
EN

CLK

Charge/Low_BAT#

DAT

INT

I/O Expander
TI TCA6416

I2C_CLK

I2C_DAT

I2C_INT

E

USB_D-

KB_LED_PWM

KB_BL_DET#
MASK_LED#
MUTE_LED#

BT_LED#

Accelermeter
ST LNG2DMTR

USB 2.0 D+USB_D+
USB 2.0 D-

5V 5V

Keyboard

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Compal Secret Data

Compal Secret Data

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

P02-Block Diagram

P02-Block Diagram

P02-Block Diagram

Size Document Numb er Rev

Size Document Numb er Rev

Size Document Numb er Rev

LA-D891P

LA-D891P

LA-D891P

Date: Sheet of

Date: Sheet

Date: Sheet

E

2 65Tuesday, December 20, 2016

2 65Tuesday, December 20, 2016

2 65Tuesday, December 20, 2016

of

of

1.0

1.0

1.0

Vinafix.com

A

smd.db-x7.ru

B

Rear Camera + 4th DMIC

C

D

E

BTB FPC 34 pin

1 1

Front Camera + ALS sensor+ LED

BTB FPC 30 pin

JUFC1

p.33

PWR_BUTTON Board

JWFC1

p.33

LS-D896P

IOB

M/B

2 2

LA-D891P

JIOB1

p.43

BATT_CONN

p.47

LS-D891P

IOB Cable

BTB FPC 40pin

JIOB2 eDP+iTouch

p.43

3 3

p.22

Dock Board LS-D892P
(K/B + Bluetooth + Wireless Charge)

Base Board

BTB FPC 30pin

eDP+itouch Y-Cable
Coaxial cable 50P

iTouch

14pin

LCD Panel

40pin

LS-D893P

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

Date: Sheet of

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

P03-DaughterB block diagram

P03-DaughterB block diagram

P03-DaughterB block diagram

LA-D891P

LA-D891P

LA-D891P

LA-D891P

LA-D891P

LA-D891P

LA-D891PLA-D891P

LA-D891PLA-D891P

LA-D891PLA-D891P

E

3 65Tuesday, December 20, 2016

3 65Tuesday, December 20, 2016

3 65Tuesday, December 20, 2016

of

of

1.0

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Board ID Table

3.3V +/- 5%Vcc

RBoard ID

0
1
2
3
4
5
6
7

240K +/- 5% 4700p
130K +/- 5%
62K +/- 5%
33K +/- 5%

8.2K +/- 5%

4.3K +/- 5%
2K +/- 5%

NC

C

4700p
4700p
4700p
4700p
4700p
4700p

REV

EVT1
DVT1
DVT1.1
DVT2
PVT

Board ID

0
1
2
3
4
5
6
7

PCB Revision

0.1

0.2

0.3

0.4

0.5

1.0

SMBUS Control Table

SOURCE

No use

1 1

PCH_SML0CLK PCH
PCH_SML0DATA

PCH_SML1CLK
PCH_SML1DATA

SMBCLK
SMBDATA

EC_SMB00_CLK
EC_SMB00_DAT

EC_SMB01_CLK
EC_SMB01_DAT

EC_SMB03_CLK
EC_SMB03_DAT

EC_SMB04_CLK
EC_SMB04_DAT

EC_SMB05_CLK
EC_SMB05_DAT

EC_SMB07_DAT

PCH

PCH

MEC1641

MEC1641

MEC1641

MEC1641

MEC1641

MEC1641EC_SMB07_CLK

Base BATT

V

V

Charger

V

XDP

V

V V V

PD
Controller

V VV V

Trinity
Dock

MUXP-SensorUSH

Link

USB 3.0Board ID Table

Flexible I/O

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Interface DESTINATION

USB 3.0 #1

USB 3.0 #2/SSIC

USB 3.0 #3

USB 3.0 #4

PCI-E#1 / USB 3.0#5

PCI-E#2 / USB 3.0#6

PCI-E #3

PCI-E #4

PCI-E #5

PCI-E #6

PCI-E #7

PCI-E #8 /SATA #0

PCI-E #9

USB Type-C Port-A

NGFF (WWAN)

USB 3.0 Type-A

USB Type-C Port-B

Reserved for AR

Reserved for AR

Reserved for AR

Reserved for AR

NGFF (WLAN)

NGFF (WLAN-WiGig)

NGFF (SSD)

NGFF (SSD) #7/#8 2lane PCI-E

Card Reader

PCI-E #10

PCI-E #11

NGFF (WWAN/HCA/2nd SSD)

PCI-E #12 NGFF (WWAN/HCA/2nd SSD)

Port Mapping USB 2.0 CLK

DESTINATIONUSB 2.0 PORT#

1

2

3

4

5

7

Type-C Port-A

Dock

Type-C Port-B NGFF (WWAN)

WWAN

CLK

IR CAM

WLAN

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE5

DESTINATIONDIFFERENTIAL

WiGig

NGFF (WLAN)

SSD

Card Reader

Displayport

DDI PORT# DESTINATION

DDI

B

C

USB Type-C Port-B

DP MUX
(WiGig/type-c port-A)

FLEX CLOCKS DESTINATION

USB Type-A9

CLKOUT_LPC_0

USH10

CLKOUT_LPC_1

EC LPC

Debug

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Nu mber Rev

Size Document Nu mber Rev

Size Document Nu mber Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P04-Notes List

P04-Notes List

P04-Notes List

LA-D891P

LA-D891P

LA-D891P

Symbol Note :

@

: means de-pop

: means Digital Ground

: means Analog Ground

1.0

1.0

1.0

4 65Tuesday, December 20, 2016

4 65Tuesday, December 20, 2016

4 65Tuesday, December 20, 2016

of

Vinafix.com

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4

3

2

1

+3VS

UCPU1A

Functional Strap Definitions
GPP_E19 (Internal Pull Down): DDPB_CTRLDATA
0 = Port B is not detected.
1 = Port B is detected.
GPP_E21 (Internal Pull Down): DDPC_CTRLDATA

Type-C PortB

0 = Port C is not detected.
1 = Port C is detected.

D D

Type-C PortA / WiGig

+3VS

CPU_DP2_CTRL_C LK

RC43 2.2K_0402_5%

2

RC45 2.2K_0402_5%

2

RC178 2.2K_0402_5%

RC179 2.2K_0402_5%

+3V_PRIM

12

CPU_DP2_CTRL_D ATA

1

CPU_DP1_CTRL_CLK

1

CPU_DP1_CTRL_DATA

12

+1.0VS_VCCIO

CPU_DP2_CTRL_CLK38

CPU_DP2_CTRL_DATA38

DDI1_P2_TXN037

DDI1_P2_TXP037
DDI1_P2_TXN137
DDI1_P2_TXP137

DDI1_P2_TXN237
DDI1_P2_TXP237
DDI1_P2_TXN337

DDI1_P2_TXP337

PCH_DDI2_N038
PCH_DDI2_P038

PCH_DDI2_N138
PCH_DDI2_P138

PCH_DDI2_N238
PCH_DDI2_P238
PCH_DDI2_N338

PCH_DDI2_P338

CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA

CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA

1 2

RC108 24.9_0 402_1%

COMPENSATION PU FOR eDP

EDP_COMP

CAD Note:Trace width=20 mils, Isolation Spacing=25mil,

1 2

RC199

C C

UFCAM_CSI2_DN033
UFCAM_CSI2_DP033

UFCAM_CSI2_DN133
UFCAM_CSI2_DP133

WFCAM_CSI2_DN433

WFCAM_CSI2_DP433
WFCAM_CSI2_DN533
WFCAM_CSI2_DP533

WFCAM_CSI2_DN633
WFCAM_CSI2_DP633
WFCAM_CSI2_DN733

WFCAM_CSI2_DP733

B B

MEDIACARD_IRQ#

10K_0402_5%

UCPU1I

@

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKL-U_BGA1356

SKL_ULT

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1

GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5

GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

Max length=100 mils.

CSI2_CLKN0

CSI2_CLKP0
CSI2_CLKN1

CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3

CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

9 OF 20

C37

D37
C32

D32
C29
D29
B26

A26

CSI2_COMP

E13

RC197

@

B7

MEM_CONFIG0

AP2

MEM_CONFIG1

AP1

MEM_CONFIG2

AP3

MEM_CONFIG3

AN3
AN1

GNSS_OFF#

AN2

PCH_WWAN_WAKE#

AM4
AM1

USH_DET#

AM2

GNSS_IRQ

AM3

WWAN_PWR_OFF#

AP4

EMMC_RCOMP

AT1

UFCAM_CSI2_CLKN033

UFCAM_CSI2_CLKP033
WFCAM_CSI2_CLKN133
WFCAM_CSI2_CLKP133

RC114

1 2

0_0402_5%

RC66 200_0402_1%

1

1

GNSS_OFF# 25

PCH_WWAN_WAKE#25

USH_DET# 41,43

GNSS_IRQ 25

WWAN_PWR_OFF#25

2

2

MEDIACARD_IRQ#27

DDR Memory Configuratino Type Strap pin

+1.8VA

RH17

RH15 10K_0402_5%

@

@

@

2

RH12 10K_0402_5%

RH9 10K_0402_5%

12

10K_0402_5%@

1

12

12

MEM_CONFIG0

MEM_CONFIG1

MEM_CONFIG2

MEM_CONFIG3

RH18

RH16 10K_0402_5%

@

RH13 10K_0402_5%

@

@

2

RH10 10K_0402_5%

12

10K_0402_5%@

12

1

12

@

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKL-U_BGA1356

100_0402_1%

SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0

X76

X7669231L05

X7669231L07

X7669231L09

X7669231L06

X7669231L08

X7669231L10

X76_8G@

X768G
X76

X7669231L01

X7669231L01

X76_16G@

X7616G
X76

X7669231L02

X7669231L02

X76_32G@

X7632G

Samsung

A A

GPIO Pin

GPP_F13

GPP_F14

GPP_F15

GPP_F16 MEM_CONFIG3

5

Pin Name

MEM_CONFIG0

MEM_CONFIG1

MEM_CONFIG2

Micron

Micron
8G

0

16G

Mircon
32G

1

0 1

1866 Mbps

000

0 0 0 0 0 0 0

Hynix

Hynix

16G

8G

1

0 11

01

0

0 1

0

Hynix
32G

0

4

Samsung
8G

0

1

1

16G

Samsung
32G

1

0

1

0

1

0

0

1

X76

X7669231L03

X7669231L03

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SKL-U

DDI

DISPLAY SIDEBANDS

Issued Date

Issued Date

Issued Date

3

C47

C46

D46

C45

A45

B45

A47

B47

E45
F45

B52

G50
F50

E48

F48

G46
F46

L9

L7
L6
N9

L10

R12

R11

U13

PCH_DP1_HPD

PCH_DP2_HPD

I2C0_IRQ_TS

WLAN_RST#

EDP_HPD

eDP_TXN_P0 22
eDP_TXP_P0 22

eDP_TXN_P1 22

eDP_TXP_P1 22

eDP_AUXN 22
eDP_AUXP 22

PCH_DDI1_AUXN 37
PCH_DDI1_AUXP37

PCH_DDI2_AUXN 38
PCH_DDI2_AUXP38

PAD~D

PAD~D

PCH_DP1_HPD 36,37,41

PCH_DP2_HPD 38

I2C0_IRQ_TS 22

WLAN_RST# 24

EDP_HPD 22

PANEL_BKLEN 22
EDP_BIA_PWM 22

PCH_ENVDD 22

1 OF 20

EDP

EDP_TXN[0]

EDP_TXP[0]

EDP_TXN[1]

EDP_TXP[1]

EDP_TXN[2]

EDP_TXP[2]

EDP_TXN[3]

EDP_TXP[3]

EDP_AUXN
EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN
DDI1_AUXP

DDI2_AUXN

DDI2_AUXP

DDI3_AUXN
DDI3_AUXP

GPP_E13/DDPB_HPD0

GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

CPU Option

SR343@

UCPU1
i3 NVPro

SA0000A387L

SR342@

UCPU1
i5 NVPro

SA0000A377L

SR340@

UCPU1
i5 Vpro

SA0000ADO2L

DRAM Option (R1) , R3 check P08

Micron 8G/1866

MICRON_8G@

UD1

MT52L256M32D1PF-107WT

SA00009XU0L

Micron 16G/1866

MICRON_16G@

UD1

MT52L512M32D2PF-107WT

SA00009U70L

MICRON_8G@

UD2

MT52L256M32D1PF-107W T

SA00009XU0L

MICRON_16G@

UD2

MT52L512M32D2PF-107W T

SA00009U70L

Micron 32G/1866

MICRON_32G@

UD1

MT52L1G32D4PG-107WT

SA00009XV0L

MICRON_32G@

UD2

MT52L1G32D4PG-107W T

SA00009XV0L

Hynix 8G/1866

HYNIX_8G@

UD1

H9CCNNN8GTMLAR-NUD FBGA

SA00008G60L

Hynix 16G/1866

HYNIX_16G@

UD1

H9CCNNNBJTMLAR-NUD FBGA

SA00008FJ0L

Hynix 32G/1866

HYNIX_32G@

UD1

H9CCNNNCLTMLAR-NUD FBGA

SA00008YT0L

HYNIX_8G@

UD2

H9CCNNN8GTMLAR-NUD FBGA

SA00008G60L

HYNIX_16G@

UD2

H9CCNNNBJTMLAR-NUD FBGA

SA00008FJ0L

HYNIX_32G@

UD2

H9CCNNNCLTMLAR-NUD FBGA

SA00008YT0L

Samsung 8G/1866

SAMSUNG_8G@

UD1

K4E8E324EB-EGCF FBGA178P

SA00009XY0L

Samsung 16G/1866

SAMSUNG_16G@

UD1

K4E6E304EB-EGCF FBGA1 7

SA00008QV2L

Samsung 32G/1866

SAMSUNG_32G@

UD1

4EBE304EB-EGCF FBGA17 8

SA00008X10L

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

SAMSUNG_8G@

UD2

K4E8E324EB-EGCF FBGA178P

SA00009XY0L

SAMSUNG_16G@

UD2

K4E6E304EB-EGCF FBGA1 7

SA00008QV2L

SAMSUNG_32G@

UD2

4EBE304EB-EGCF FBGA17 8

SA00008X10L

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

MICRON_8G@

UD3

MT52L256M32D1PF-107WT

SA00009XU0L

MICRON_16G@

UD3

MT52L512M32D2PF-107WT

SA00009U70L

MICRON_32G@

UD3

MT52L1G32D4PG-107WT

SA00009XV0L

HYNIX_8G@

UD3

H9CCNNN8GTMLAR-NUD FBGA

SA00008G60L

HYNIX_16G@

UD3

H9CCNNNBJTMLAR-NUD FBGA

SA00008FJ0L

HYNIX_32G@

UD3

H9CCNNNCLTMLAR-NUD FBGA

SA00008YT0L

SAMSUNG_8G@

UD3

K4E8E324EB-EGCF FBGA178P

SA00009XY0L

SAMSUNG_16G@

UD3

K4E6E304EB-EGCF FBGA1 7

SA00008QV2L

SAMSUNG_32G@

UD3

4EBE304EB-EGCF FBGA17 8

SA00008X10L

2

2Lane eDP

@

T6

@

T5

SR33Z@

UCPU1
i7 VPro

SA0000ADP2L

MICRON_8G@

UD4

MT52L256M32D1PF-107WT

SA00009XU0L

MICRON_16G@

UD4

MT52L512M32D2PF-107WT

SA00009U70L

MICRON_32G@

UD4

MT52L1G32D4PG-107WT

SA00009XV0L

HYNIX_8G@

UD4

H9CCNNN8GTMLAR-NUD FBGA

SA00008G60L

HYNIX_16G@

UD4

H9CCNNNBJTMLAR-NUD FBGA

SA00008FJ0L

HYNIX_32G@

UD4

H9CCNNNCLTMLAR-NUD FBGA

SA00008YT0L

SAMSUNG_8G@

UD4

K4E8E324EB-EGCF FBGA178P

SA00009XY0L

SAMSUNG_16G@

UD4

K4E6E304EB-EGCF FBGA1 7

SA00008QV2L

SAMSUNG_32G@

UD4

4EBE304EB-EGCF FBGA17 8

SA00008X10L

I2C0_IRQ_TS

WLAN_RST#

GNSS_IRQ

USH_DET#

GNSS_OFF#

PCH_WWAN_WAKE#

EDP_HPD

PCH_DP1_HPD

PCH_DP2_HPD

DRAM Config Option

(Resistor pop location)

MEM_CONFIG0

X76_M8G@

RH18

10K_0402_5%

SD028100280

X76_M16G@

RH17

10K_0402_5%

SD028100280

X76_M32G@

RH18

10K_0402_5%

SD028100280

X76_H8G@

RH17

10K_0402_5%

SD028100280

X76_H16G@

RH18

10K_0402_5%

SD028100280

X76_H32G@

RH17

10K_0402_5%

SD028100280

X76_S8G@

RH18

10K_0402_5%

SD028100280

X76_S16G@

RH17

10K_0402_5%

SD028100280

X76_S32G@

RH18

10K_0402_5%

SD028100280

RC194 100K_0201_5%

2

RH505

1 2

RH8 10K_0201_5%

1

@

RH7 100K_0201_5%

1 2

RH5

1 2

RH6 100K_0201_5%

1 2

RC126 100 K_0402_5%

RC124 100K_0402_5%

RC46 100K_0402_5 %

MEM_CONFIG1 MEM_CONFIG2 MEM_CONFIG3

X76_M8G@

RH16

10K_0402_5%

SD028100280

X76_M16G@

RH16

10K_0402_5%

SD028100280

X76_M32G@

RH15

10K_0402_5%

SD028100280

X76_H8G@

RH15

10K_0402_5%

SD028100280

X76_H16G@

RH16

10K_0402_5%

SD028100280

X76_H32G@

RH16

10K_0402_5%

SD028100280

X76_S8G@

RH15

10K_0402_5%

SD028100280

X76_S16G@

RH15

10K_0402_5%

SD028100280

X76_S32G@

RH16

10K_0402_5%

SD028100280

1

2

12

12

12

X76_M8G@

RH13

10K_0402_5%

SD028100280

X76_M16G@

RH13

10K_0402_5%

SD028100280

X76_M32G@

RH13

10K_0402_5%

SD028100280

X76_H8G@

RH13

10K_0402_5%

SD028100280

X76_H16G@

RH12

10K_0402_5%

SD028100280

X76_H32G@

RH12

10K_0402_5%

SD028100280

X76_S8G@

RH12

10K_0402_5%

SD028100280

X76_S16G@

RH12

10K_0402_5%

SD028100280

X76_S32G@

RH13

10K_0402_5%

SD028100280

+3VS

10K_0201_5%

+1.8VA

10K_0201_5%

X76_M8G@

RH10

10K_0402_5%

SD028100280

X76_M16G@

RH10

10K_0402_5%

SD028100280

X76_M32G@

RH10

10K_0402_5%

SD028100280

X76_H8G@

RH10

10K_0402_5%

SD028100280

X76_H16G@

RH10

10K_0402_5%

SD028100280

X76_H32G@

RH10

10K_0402_5%

SD028100280

X76_S8G@

RH10

10K_0402_5%

SD028100280

X76_S16G@

RH10

10K_0402_5%

SD028100280

X76_S32G@

RH9

10K_0402_5%

SD028100280

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P05-MCP(1/14)DDI,EDP,CSI2,EMMC

P05-MCP(1/14)DDI,EDP,CSI2,EMMC

P05-MCP(1/14)DDI,EDP,CSI2,EMMC

1.0

1.0

LA-D891P

LA-D891P

LA-D891P

5 65Tuesday, December 20, 2016

5 65Tuesday, December 20, 2016

5 65Tuesday, December 20, 2016

1

of

1.0

Vinafix.com

5

smd.db-x7.ru

4

3

2

1

LPDDR3, Ballout for side by side(Non-Interleave)

DDR_A_DQS#[0..7]19

DDR_A_DQS[0..7]19

DDR_A_D[0..63]19

DDR_A_CA1_[0..9]19

D D

C C

B B

DDR_A_CA2_[0..9]19

UCPU1B

@

DDR_A_D0
DDR_A_D1

DDR_A_D2

DDR_A_D3

DDR_A_D4

DDR_A_D5

DDR_A_D6

DDR_A_D7

DDR_A_D8
DDR_A_D9

DDR_A_D10
DDR_A_D11

DDR_A_D12
DDR_A_D13

DDR_A_D14
DDR_A_D15
DDR_A_D32

DDR_A_D33
DDR_A_D34
DDR_A_D35

DDR_A_D36
DDR_A_D37

DDR_A_D38
DDR_A_D39
DDR_A_D40

DDR_A_D41
DDR_A_D42
DDR_A_D43

DDR_A_D44
DDR_A_D45

DDR_A_D46
DDR_A_D47
DDR_B_D0

DDR_B_D1
DDR_B_D2
DDR_B_D3

DDR_B_D4
DDR_B_D5
DDR_B_D6

DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_D10
DDR_B_D11

DDR_B_D12
DDR_B_D13
DDR_B_D14

DDR_B_D15
DDR_B_D32
DDR_B_D33

DDR_B_D34
DDR_B_D35

DDR_B_D36
DDR_B_D37
DDR_B_D38

DDR_B_D39
DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D44
DDR_B_D45

DDR_B_D46
DDR_B_D47

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKL-U_BGA1356

DDR_B_DQS#[0..7]20

DDR_B_DQS[0..7]20

DDR_B_D[0..63]20

DDR_B_CA1_[0..9]20

DDR_B_CA2_[0..9]20

SKL-U

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]

DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]

DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[0]

DDR0_DQSP[0]

DDR0_DQSN[1]

DDR0_DQSP[1]

DDR0_ALERT#

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

DDR CH - A

DDR0_DQSN[2]/DDR0_DQSN[4]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSP[3]/DDR0_DQSP[5]

DDR0_DQSN[4]/DDR1_DQSN[0]

DDR0_DQSP[4]/DDR1_DQSP[0]

DDR0_DQSN[5]/DDR1_DQSN[1]

DDR0_DQSP[5]/DDR1_DQSP[1]

DDR0_DQSN[6]/DDR1_DQSN[4]

DDR0_DQSP[6]/DDR1_DQSP[4]

DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_CKN[0]

DDR0_CKP[0]

DDR0_CKN[1]

DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]

DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1]

DDR0_ODT[0]

DDR0_ODT[1]

DDR0_MA[3]
DDR0_MA[4]

DDR0_PAR

2 OF 20

AU53

AT53

AU55

AT55

BA56
BB56
AW56

AY56

AU45

AU43

AT45

AT43

BA51

BB54

BA52

AY52

AW52

AY55

AW54
BA54

BA55
AY54

AU46

AU48

AT46

AU50

AU52

AY51

AT48

AT50

BB50
AY50

BA50
BB52

AM70

AM69

AT69

AT70

BA64

AY64

AY60

BA60

BA38

AY38

AY34

BA34

BA30

AY30

AY26

BA26

AW50

AT52

AY67
AY68
BA67

AW67

DDR_A_CLK#0

DDR_A_CLK0
DDR_A_CLK#1
DDR_A_CLK1

DDR_A_CKE0
DDR_A_CKE1

DDR_A_CKE2
DDR_A_CKE3

DDR_A_CS#0

DDR_A_CS#1

DDR_A_ODT0

DDR_VTT_CNTL

DDR_A_CLK#0 19

DDR_A_CLK0 19

DDR_A_CLK#1 19
DDR_A_CLK1 19

DDR_A_CKE0 19
DDR_A_CKE1 19

DDR_A_CKE2 19
DDR_A_CKE3 19

DDR_A_CS#0 19
DDR_A_CS#1 19

DDR_A_ODT0 19

DDR_A_CA1_0 19

DDR_A_CA1_1 19
DDR_A_CA1_2 19
DDR_A_CA1_3 19

DDR_A_CA1_4 19
DDR_A_CA1_5 19
DDR_A_CA1_6 19

DDR_A_CA1_7 19
DDR_A_CA1_8 19
DDR_A_CA1_9 19

DDR_A_CA2_0 19
DDR_A_CA2_1 19
DDR_A_CA2_2 19

DDR_A_CA2_3 19
DDR_A_CA2_4 19
DDR_A_CA2_5 19

DDR_A_CA2_6 19
DDR_A_CA2_7 19
DDR_A_CA2_8 19

DDR_A_CA2_9 19

DDR_A_DQS#0 19
DDR_A_DQS0 19

DDR_A_DQS#1 19
DDR_A_DQS1 19
DDR_A_DQS#4 19

DDR_A_DQS4 19
DDR_A_DQS#5 19
DDR_A_DQS5 19

DDR_B_DQS#0 20
DDR_B_DQS0 20
DDR_B_DQS#1 20

DDR_B_DQS1 20
DDR_B_DQS#4 20
DDR_B_DQS4 20

DDR_B_DQS#5 20
DDR_B_DQS5 20

+V_DDR_REF_CA 21

+V_DDR_REFA_R 21
+V_DDR_REFB_R 21

DDR_A_D16
DDR_A_D17

DDR_A_D18

DDR_A_D19

DDR_A_D20

DDR_A_D21

DDR_A_D22

DDR_A_D23
DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27
DDR_A_D28

DDR_A_D29
DDR_A_D30
DDR_A_D31

DDR_A_D48
DDR_A_D49
DDR_A_D50

DDR_A_D51
DDR_A_D52

DDR_A_D53
DDR_A_D54
DDR_A_D55

DDR_A_D56
DDR_A_D57
DDR_A_D58

DDR_A_D59
DDR_A_D60
DDR_A_D61

DDR_A_D62
DDR_A_D63

DDR_B_D16
DDR_B_D17
DDR_B_D18

DDR_B_D19
DDR_B_D20
DDR_B_D21

DDR_B_D22
DDR_B_D23

DDR_B_D24
DDR_B_D25
DDR_B_D26

DDR_B_D27
DDR_B_D28
DDR_B_D29

DDR_B_D30
DDR_B_D31
DDR_B_D48

DDR_B_D49
DDR_B_D50

DDR_B_D51
DDR_B_D52

DDR_B_D53
DDR_B_D54
DDR_B_D55

DDR_B_D56
DDR_B_D57
DDR_B_D58

DDR_B_D59
DDR_B_D60

DDR_B_D61
DDR_B_D62
DDR_B_D63

UCPU1C

@

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKL-U_BGA1356

SKL-U

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]

DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]

DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2]

DDR1_DQSP[0]/DDR0_DQSP[2]

DDR1_DQSN[1]/DDR0_DQSN[3]

DDR1_DQSP[1]/DDR0_DQSP[3]

DDR1_DQSN[2]/DDR0_DQSN[6]

DDR1_DQSP[2]/DDR0_DQSP[6]

DDR1_DQSN[3]/DDR0_DQSN[7]

DDR1_DQSP[3]/DDR0_DQSP[7]

DDR1_DQSN[4]/DDR1_DQSN[2]

DDR1_DQSP[4]/DDR1_DQSP[2]

DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

DDR1_CKN[0]
DDR1_CKN[1]

DDR1_CKP[0]
DDR1_CKP[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]

DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1]

DDR1_ODT[0]

DDR1_ODT[1]

DDR1_MA[3]
DDR1_MA[4]

DDR1_DQSN[6]

DDR1_DQSP[6]

DDR1_DQSN[7]

DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR

DRAM_RESET#

DDR_RCOMP[0]
DDR_RCOMP[1]

DDR_RCOMP[2]

3 OF 20

AN45
AN46

AP45
AP46

AN56
AP55
AN55

AP53

BB42

AY42

BA42

AW42

AY48

AP50

BA48

BB48

AP48

AP52

AN50
AN48

AN53
AN52

BA43

AY43

AY44

AW44

BB44

AY47

BA44

AW46

AY46
BA46

BB46
BA47

AH66

AH65

AG69

AG70

AR66

AR65

AR61

AR60

AT38

AR38

AT32

AR32

AR25

AR27

AR22

AR21

AN43

AP43

AT13

AR18
AT18

AU18

DDR_B_CLK#0

DDR_B_CLK#1

DDR_B_CLK0

DDR_B_CLK1

DDR_B_CKE0

DDR_B_CKE1

DDR_B_CKE2
DDR_B_CKE3

DDR_B_CS#0
DDR_B_CS#1

DDR_B_ODT0

SM_RCOMP0

SM_RCOMP1
SM_RCOMP2

DDR_B_CLK#0 20

DDR_B_CLK#1 20
DDR_B_CLK0 20

DDR_B_CLK1 20

DDR_B_CKE0 20
DDR_B_CKE1 20

DDR_B_CKE2 20
DDR_B_CKE3 20

DDR_B_CS#0 20
DDR_B_CS#1 20

DDR_B_ODT0 20

DDR_B_CA1_0 20

DDR_B_CA1_1 20
DDR_B_CA1_2 20
DDR_B_CA1_3 20

DDR_B_CA1_4 20
DDR_B_CA1_5 20
DDR_B_CA1_6 20

DDR_B_CA1_7 20
DDR_B_CA1_8 20
DDR_B_CA1_9 20

DDR_B_CA2_0 20
DDR_B_CA2_1 20
DDR_B_CA2_2 20

DDR_B_CA2_3 20
DDR_B_CA2_4 20
DDR_B_CA2_5 20

DDR_B_CA2_6 20
DDR_B_CA2_7 20

DDR_B_CA2_8 20
DDR_B_CA2_9 20

DDR_A_DQS#2 19
DDR_A_DQS2 19

DDR_A_DQS#3 19
DDR_A_DQS3 19

DDR_A_DQS#6 19
DDR_A_DQS6 19
DDR_A_DQS#7 19

DDR_A_DQS7 19
DDR_B_DQS#2 20
DDR_B_DQS2 20

DDR_B_DQS#3 20
DDR_B_DQS3 20
DDR_B_DQS#6 20

DDR_B_DQS6 20
DDR_B_DQS#7 20
DDR_B_DQS7 20

@

T36

PAD~D

+1.2V_DDR

@

UC1

1

DDR_VTT_CNTL

NC

2

A

3

GND

74AUP1G07GW_TSSOP5

A A

VCC

5

4

Y

1

@

CC15

0.1U_0402_10V7K

2

+3VS

1

@

R32
100K_0402_5%

2

SM_PG_CTRL 54

LPDDR3 COMPENSATION SIGNALS

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

CAD Note:
Trace width=12~15 mil, Spacing=20 mils

1

RC164 200_0402_1%

RC166 80.6_0402_1%

1 2

RC165 162_0402_1%

1

2

2

Max trace length= 500 mil

DELL CONFIDENTIAL/PROPRIETARY

Security Classification

Security Classification

Security Classification

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P06-MCP(2/14)LPDDR3

P06-MCP(2/14)LPDDR3

P06-MCP(2/14)LPDDR3

LA-D891P

LA-D891P

LA-D891P

1

1.0

1.0

1.0

6 65Tuesday, December 20, 2016

6 65Tuesday, December 20, 2016

6 65Tuesday, December 20, 2016

of

Vinafix.com

5

smd.db-x7.ru

4

3

2

1

SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236

change to 1k 5%
check it is XDP@

RC67 1K_0402_5%@XDP@

PCH_SPI_DO_XDP13
PCH_SPI_DO2_XDP13

D D

TPM_PIRQ#8,31

+3VS

1 2

RC73 10K_0402_5%

1

RC83 10K_0402_5%

C C

PCH_SPI_CS0#

SPI_SO_VROM1

SPI_IO2_VROM1

PCH_SPI_CS1#

SPI_SO_VROM2

SPI_IO2_VROM2

2

128Mb Flash ROM

UH1

1

2
3

4

PVT-002
depop UH2

32Mb Flash ROM

UH2

@

1
2

3
4

W25Q32FVZPIQ WSON 8P SPI ROM

PVT-014.01
de-pop debug XDP related resistor
pop by using Memo

SIO_RCIN#

IRQ_SERIRQ

CS#

HOLD#_RESET#

DO
WP#

GND

CS#
DO

WP#
GND

Themal Pad

W25Q128FVPIQ_WSON8

VCC

HOLD#

CLK

DI

Thermal_pad

1 2

RC69 1K_0402_5%@XDP@

1 2

RC198

@

1

8

VCC

7

6

CLK

5

DI

9

PVT-013.01
add thermal pad for use

+3.3V_SPI

8

SPI_IO3_VROM2

7

SPI_CLK_VROM2

6

SPI_SI_VROM2

5

9

PCH_SPI_CS2#31

TC1

2

0_0201_5%

SIO_RCIN#30

IRQ_SERIRQ30

+3.3V_SPI

0.1U_0402_25V6

SPI_IO3_VROM1

SPI_CLK_VROM1

SPI_SI_VROM1

CC89

2

1

0.1U_0402_25V6

CL_CLK24
CL_DATA24
CL_RST#24

CC90

1

2

PCH_SPI_CLK
PCH_SPI_SO

PCH_SPI_SI

PCH_SPI_IO2

PCH_SPI_IO3

PCH_SPI_CS0#

PCH_SPI_CS1#

SIO_RCIN#

IRQ_SERIRQ

PVT-001.01
Remove co-layout

AV2

AW3

AV3

AW2

AU4
AU3
AU2

AU1

M2
M3

M1

AW13

AY11

J4

V1

V2

G3

G2
G1

@

SKL-U_BGA1356

UCPU1E

SPI - FLASH

SPI0_CLK

SPI0_MISO
SPI0_MOSI
SPI0_IO2

SPI0_IO3
SPI0_CS0#
SPI0_CS1#

SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO

GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2

GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#

C LINK

CL_CLK

CL_DATA
CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

SKL-U

LPC

SMBUS, SMLINK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

PCH_SPI_CLK_TPM31
PCH_SPI_SI_TPM31

PCH_SPI_SO_TPM31

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1

GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

5 OF 20

SPI_SI_VROM1

SPI_CLK_VROM1

SPI_SO_VROM1

SPI_IO2_VROM1

SPI_IO3_VROM1

SPI_SI_VROM2
SPI_SO_VROM2
SPI_IO2_VROM2

SPI_IO3_VROM2

SPI_CLK_VROM2

DDR_XDP_SMBCLK

R7

DDR_XDP_SMBDAT

R8

PCH_SMB_ALERT#

R10

R9
W2

GPP_C5

W1

SML1_SMBCLK

W3

SML1_SMBDAT

V3

GPP_B23

AM7

AY13
BA13

BB13
AY12
BA12

BA11

PCI_CLK_LPC0

AW9

PCI_CLK_LPC1

AY9

AW11

CLKRUN#

RP2

1
2

3 6

4 5

33_0804_8P4R_5%

1 8

2 7
3

4 5

33_0804_8P4R_5%

1

2 7

3 6
4

33_0804_8P4R_5%

1 2

RH93 33_0201_1%

RP3

RP4

8

7

6

PCH_SPI_SI

8

PCH_SPI_SO
PCH_SPI_IO2
PCH_SPI_IO3

5

PCH_SPI_CLK

PCH_SPI_SO

PCH_SPI_IO2
PCH_SPI_IO3

DDR_XDP_SMBCLK 13

DDR_XDP_SMBDAT 13

SML1_SMBCLK 30

SML1_SMBDAT 30

LPC_AD0 30,43
LPC_AD1 30,43

LPC_AD2 30,43
LPC_AD3 30,43

LPC_FRAME# 30,43

1 2

RC71 22_0402_5%

1 2

RC70 22_0402_5%

CLKRUN# 30

PCH_SPI_SI

PCH_SPI_CLK

CLK_PCI_MEC

CLK_LPC_DEBUG

CLK_PCI_MEC 30
CLK_LPC_DEBUG 43

2

Reserve for RF

+3VS

DDR_XDP_SMBDAT

DDR_XDP_SMBCLK

CLKRUN#

SML1_SMBCLK

SML1_SMBDAT

1

@12P_0402_50V8J

CC78

12

@12P_0402_50V8J

CC21

1 2

RC55 1K_0402_5%

1 2

RC51 1K_0402_5%

PCH_SMB_ALERT#

12

RN12.2K_0402_5%

12

RN22.2K_0402_5%

12

RC828.2K_0402_5%

+3V_PRIM

change RC49 to 2.2k

1 2

RC49 2.2K_0402_5%

+3V_PRIM

TLS CONFIDENTIALITY

HIGH
LOW(DEFAULT)

GPP_C5

ENABLE
DISABLE

+3V_PRIM

1

RC58 10K_0402_5%@

2

+3V_PRIM

RH19 1K_0402_5%~D

1 2

B B

SPI debug conn

SPI_CLK_VROM1

33_0402_5%

RC169@

1 2

33P_0402_50V8J

CC91@

1 2

from CPU to SPI ROM

PCH_SPI_CS1#

PCH_SPI_SI

PCH_SPI_SO

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_IO2

PCH_SPI_IO3

+3.3V_SPI

A A

PCH SPI

PVT-003.01
0R turn to short pad

RC177

1 2

RC176

1

RC175

1

RC174

1

RC173

1 2

RC172

1 2

RC171

1 2

+3V_PRIM

RC170

1

0_0402_1%@

2

0_0402_1%@

2

0_0402_1%@

2

0_0402_1%@

0_0402_1%@

0_0402_1%@

0_0402_1%@

2

0_0402_1%@

SPI_PCH_CS1#

SPI_PCH_SI

SPI_PCH_SO

SPI_PCH_CLK

SPI_PCH_CS0#

SPI_PCH_IO2

SPI_PCH_IO3

SPI

JSPI1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

GND_1

22

GND_2

ACES_50696-0200M-P01

CONN@

9/5 MOW
Option 1: Implement a 1 kOhm pull-down resistor on the signal and de-populate
the
required 1 kOhm pull-up resistor(MOW WW5).
In this case, customers must ensure that the SPI
flash device on the platform has HOLD functionality disabled by default.

Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y platforms
with ES and SKL S/H platforms with pre-ES1/ES1 samples(MOW WW9).

@

RH20 1K_0402_5%~D

1 2

@

RH21 1K_0402_5%~D

1

@

2

PCH_SPI_IO2

PCH_SPI_IO3

PCH_SPI_IO3

EC interface

HIGH
LOW(DEFAULT)

GPP_B23

EXI BOOT STALL BYPASS

HIGH
LOW(DEFAULT)

ESPI
LPC

1 2

RC64 4.7K_0402_5%@

ENABLE
DISABLE

+3V_PRIM

DELL CONFIDENTIAL/PROPRIETARY

Security Classification

Security Classification

TPM

JSPI

5

4

Security Classification

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

P07-MCP(3/14)SPI,SMB,LPC

P07-MCP(3/14)SPI,SMB,LPC

P07-MCP(3/14)SPI,SMB,LPC

LA-D891P

LA-D891P

LA-D891P

1

7 65Tuesday, December 20, 2016

7 65Tuesday, December 20, 2016

7 65Tuesday, December 20, 2016

1.0

1.0

1.0

of

Vinafix.com

5

smd.db-x7.ru

4

3

2

1

+3VS

UCPU1F

+3VS

1 2

RC56

1

RH3 49.9K_0402_1%

D D

+3V_PRIM

+3VS_TS

C C

1 2

RH4 49.9K_0402_1%

1 2

RC190 49.9K_0402_1%

@

1

RC191 49.9K_0402_1%

1 2

RC180

1 2

RC181

1 2

RC149

HOST_SD_WP#

10K_0402_5%

UART2_TXD

2

UART2_RXD

UART2_RTS#

UART2_CTS#

2

TPM_PIRQ#7,31

10K_0201_5%

10K_0402_5%

10K_0402_5%

RC196

1

EDP_CAB_DET#

WWAN_RST#

SIO_EXT_SCI#

2

0_0201_5%

UART2_RTS#

EDP_CAB_DET#22

WLAN_ON24

SIO_EXT_SCI#30

3.3V_TS_EN44

DEBUG_UART0_TX30

BT_ON/OFF#24

HOST_SD_WP#27

UART2_RXD43
UART2_TXD43

UART2_RTS#43

PVT-016.01
ALS_CAL_I2C0_SDA change to TS_RST#

TS_RST#22
ALS_CAL_I2C0_SCL22

SKYCAM_I2C_DATA34
SKYCAM_I2C_CLK34

UART2_CTS#43

I2C1_SDA_TS22
I2C1_SCK_TS22

UF_I2C_DATA33

UF_I2C_CLK33

EDP_CAB_DET#

NRB_BIT

SIO_EXT_SCI#

GPP_B22

WWAN_RST#

HOST_SD_WP#

UART2_RXD

UART2_TXD

UART2_RTS#
UART2_CTS#

TS_RST#
ALS_CAL_I2C0_SCL

SKYCAM_I2C_DATA
SKYCAM_I2C_CLK

I2C1_SDA_TS
I2C1_SCK_TS

UF_I2C_DATA
UF_I2C_CLK

@

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

SKL-U_BGA1356

LPSS ISH

GPP F group

1.8V only

SKL-U

GPP_D9

GPP_D10

GPP_D11
GPP_D12

GPP_D5/ISH_I2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP F group

1.8V only

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_D15/ISH_UART0_RTS#

GPP_A18/ISH_GP0

GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3

GPP_A22/ISH_GP4

GPP_A12/BM_BUSY#/ISH_GP6

GPP_A23/ISH_GP5

6 OF 20

P2

P3

P4
P1

M4
N3

N1

N2

AD11

AD12

U1

U2
U3
U4

AC1
AC2
AC3

AB4

AY8

BA8
BB7
BA7

AY7
AW7

AP13

DDR_CHB_EN
DDR_CHA_EN

TS_ID0

ISH_I2C0_SDA 31

ISH_I2C0_SCL 3 1

ALS_I2C1_SDA33

ALS_I2C1_SCL 33

@

T15

PAD~D

ACCEL_INT1# 31
ACCEL_INT2# 31

TS_ID0 22

PCH_AUD_PW R_EN 30

3.3V_CAM_EN 34

ALS_I2C1_ALERT#33

DDR_CHA_EN

DDR_CHB_EN

DDR_CHA_EN

DDR_CHB_EN

2

RC184

@

@

ACCEL_INT1#

ACCEL_INT2#

TS_ID0

TS_RST#

ALS_CAL_I2C0_SCL

1

0_0402_5%

RH30 100K_0402_5%~D

1 2

RH29 100K_0402_5%~D

1 2

RH31 SHORT PADS

RH28 SHORT PADS

RC182

RC183

RC192 100K_0201_5%

RC205

RC206

1 2

2

1

1 2

1 2

1 2

1 2

1 2

KICKSTD_SW_DET#30,42

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

+3V_PRIM

+3VS

1

RC48 4.7K_0402_5%

1 2

RC50 4.7K_0402_5%

+3V_PRIM

RC63 4.7K_0402_5%@

NO REBOOT STRAP

HIGH

B B

LOW(DEFAULT)
Weak IPD

+3V_PRIM

2

1 2

I2C1_SDA_TS

I2C1_SCK_TS

NRB_BIT

No REBOOT
REBOOT ENABLE

I2C1_SDA_TS

I2C1_SCK_TS
SKYCAM_I2C_DATA

SKYCAM_I2C_CLK
UF_I2C_DATA
UF_I2C_CLK

X76

33P_0402_50V8J

12

33P_0402_50V8J

1

12

2

CC6@EMC@

CC12@EMC@

33P_0402_50V8J

33P_0402_50V8J

CC13@EMC@

1

1

2

2

CC11@EMC@

33P_0402_50V8J

33P_0402_50V8J

1

2

CC7@EMC@

X7669231L12

CC8@EMC@

DRAM Option (R3)

Micron 8G/1866

MICRON_8G_R3@

UD1

MT52L256M32D1PF-107WT

SA00009XU1L

MICRON_8G_R3@

UD2

MT52L256M32D1PF-107W T

SA00009XU1L

MICRON_8G_R3@

UD3

MT52L256M32D1PF-107WT

SA00009XU1L

MICRON_8G_R3@

UD4

MT52L256M32D1PF-107WT

SA00009XU1L

Micron 16G/1866

X7669231L15

X7669231L18

MICRON_16G_R3@

UD1

MT52L512M32D2PF-107WT

SA00009U71L

Micron 32G/1866

MICRON_32G_R3@

UD1

MT52L1G32D4PG-107WT

SA00009XV1L

MT52L512M32D2PF-107W T

MT52L1G32D4PG-107W T

MICRON_16G_R3@

UD2

SA00009U71L

MICRON_32G_R3@

UD2

SA00009XV1L

MICRON_16G_R3@

UD3

MT52L512M32D2PF-107WT

SA00009U71L

MICRON_32G_R3@

UD3

MT52L1G32D4PG-107WT

SA00009XV1L

MICRON_16G_R3@

UD4

MT52L512M32D2PF-107WT

SA00009U71L

MICRON_32G_R3@

UD4

MT52L1G32D4PG-107WT

SA00009XV1L

Hynix 8G/1866

X7669231L13

X7669231L16

HYNIX_8G_R3@

UD1

H9CCNNN8GTMLAR-NUD FBGA

SA00008G61L

Hynix 16G/1866

HYNIX_16G_R3@

UD1

H9CCNNNBJTMLAR-NUD FBGA

SA00008FJ1L

H9CCNNN8GTMLAR-NUD FBGA

H9CCNNNBJTMLAR-NUD FBGA

HYNIX_8G_R3@

UD2

SA00008G61L

HYNIX_16G_R3@

UD2

SA00008FJ1L

HYNIX_8G_R3@

UD3

H9CCNNN8GTMLAR-NUD FBGA

SA00008G61L

HYNIX_16G_R3@

UD3

H9CCNNNBJTMLAR-NUD FBGA

SA00008FJ1L

HYNIX_8G_R3@

UD4

H9CCNNN8GTMLAR-NUD FBGA

SA00008G61L

HYNIX_16G_R3@

UD4

H9CCNNNBJTMLAR-NUD FBGA

SA00008FJ1L

Hynix 32G/1866

12

RC65

@

8.2K_0402_5%

GPP_B22

X7669231L19

X76_8G_R3@

X768G3
X76

X7669231L11

X7669231L11

BOOT BIOS Destination(Bit

6)
HIGH

LOW(DEFAULT)

LPC
SPI

A A

X76_16G_R3@

X7616G3
X76

X7669231L14

X7669231L14

X76_32G_R3@

X7632G3
X76

X7669231L17

X7669231L17

HYNIX_32G_R3@

UD1

H9CCNNNCLTMLAR-NUD FBGA

SA00008YT1L

Samsung 8G/1866

SAMSUNG_8G_R3@

UD1

K4E8E324EB-EGCF FBGA178P

SA00009XY1L

Samsung 16G/1866

SAMSUNG_16G_R3@

UD1

K4E6E304EB-EGCF FBGA1 7

SA00008QV3L

Samsung 32G/1866

SAMSUNG_32G_R3@

UD1

4EBE304EB-EGCF FBGA17 8

SA00008X11L

HYNIX_32G_R3@

UD2

H9CCNNNCLTMLAR-NUD FBGA

SA00008YT1L

SAMSUNG_8G_R3@

UD2

K4E8E324EB-EGCF FBGA178P

SA00009XY1L

SAMSUNG_16G_R3@

UD2

K4E6E304EB-EGCF FBGA1 7

SA00008QV3L

SAMSUNG_32G_R3@

UD2

4EBE304EB-EGCF FBGA17 8

SA00008X11L

HYNIX_32G_R3@

UD3

H9CCNNNCLTMLAR-NUD FBGA

SA00008YT1L

SAMSUNG_8G_R3@

UD3

K4E8E324EB-EGCF FBGA178P

SA00009XY1L

SAMSUNG_16G_R3@

UD3

K4E6E304EB-EGCF FBGA1 7

SA00008QV3L

SAMSUNG_32G_R3@

UD3

4EBE304EB-EGCF FBGA17 8

SA00008X11L

HYNIX_32G_R3@

UD4

H9CCNNNCLTMLAR-NUD FBGA

SA00008YT1L

SAMSUNG_8G_R3@

UD4

K4E8E324EB-EGCF FBGA178P

SA00009XY1L

SAMSUNG_16G_R3@

UD4

K4E6E304EB-EGCF FBGA1 7

SA00008QV3L

SAMSUNG_32G_R3@

UD4

4EBE304EB-EGCF FBGA17 8

SA00008X11L

Security Classification

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet of

Compal Electronics, Inc.

P08-MCP(4/14)GSPI,I2C,UART,ISH

P08-MCP(4/14)GSPI,I2C,UART,ISH

P08-MCP(4/14)GSPI,I2C,UART,ISH

LA-D891P

LA-D891P

LA-D891P

1

8 65Tuesday, December 20, 2016

8 65Tuesday, December 20, 2016

8 65Tuesday, December 20, 2016

of

of

1.0

1.0

1.0

Security Classification

DELL CONFIDENTIAL/PROPRIETARY

Security Classification

Vinafix.com

5

smd.db-x7.ru

4

3

2

1

UCPU1H

@

PCIE/USB3/SATA

H13

D D

PCIE_PRX_WLANTX_N524

WLAN
PCIe Gen2 x 1

WLAN - WiGig
PCIe Gen2 x 1

PVT-011.01
rename P7 SATA -> PCIe

C C

rename P8 PCIe -> SATA

PCIe SSD

SATA SSD

Cardreader
PCIe Gen2 x 1

+3VS

1

RC72 10K_0402_5%

M.2 2242
WWAN 2nd
SSD SATA/PCIe 2 Lane ony 4/14

B B

PCIE_PRX_WLANTX_P524
PCIE_PTX_WLANRX_N524

PCIE_PTX_WLANRX_P524

PCIE_PRX_WLANTX_N624
PCIE_PRX_WLANTX_P624
PCIE_PTX_WLANRX_N624

PCIE_PTX_WLANRX_P624

PCIE_PRX_SSDTX_N723

PCIE_PRX_SSDTX_P723
PCIE_PTX_SSDRX_N723
PCIE_PTX_SSDRX_P723

SATA_PRX_SSDTX_N823

SATA_PRX_SSDTX_P823

SATA_PTX_SSDRX_N823
SATA_PTX_SSDRX_P823

PCIE_PRX_CARDTX_N927

PCIE_PRX_CARDTX_P927

PCIE_PTX_CARDRX_N927
PCIE_PTX_CARDRX_P927

1

RC113 100_0402_1%

2

PCIE_PRX_WWANTX_N1125

PCIE_PRX_WWANTX_P1125

PCIE_PTX_WWANRX_N1125
PCIE_PTX_WWANRX_P1125

PCIE_PRX_WWANTX_N1225

PCIE_PRX_WWANTX_P1225

PCIE_PTX_WWANRX_N1225
PCIE_PTX_WWANRX_P1225

2

CPU_XDP_PRDY#13
CPU_XDP_PREQ#13

PCIE_RCOMPN
PCIE_RCOMPP

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL-U_BGA1356

SKL-U

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN

USB3_2_RXP/SSIC_1_RXP

USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP

USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0#

GPP_E10/USB2_OC1#

GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0

GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0

GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

USB3_1_RXN
USB3_1_RXP

USB3_1_TXN

USB3_1_TXP

USB3_4_RXN
USB3_4_RXP

USB3_4_TXN

USB3_4_TXP

USB2N_1

USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4

USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7

USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10

USB2P_10

USB2_COMP

USB2_ID

8 OF 20

H8
G8

C13
D13

J6

H6
B13
A13

J10
H10
B15

A15

E10
F10

C15
D15

AB9

AB10

AD6
AD7

AH3
AJ3

AD9

AD10

AJ1
AJ2

AF6
AF7

AH1

AH2

AF8
AF9

AG1
AG2

AH7

AH8

AB6
AG3

AG4

A9
C9

D9
B9

J1

J2
J3

H2

H3
G4

H1

USB3RN1 37

USB3RP1 37
USB3TN1 37

USB3TP1 37

USB3RN2 25
USB3RP2 25

USB3TN2 25

USB3TP2 25

USB3RN3 39

USB3RP3 39
USB3TN3 39

USB3TP3 39

USB3RN4 37
USB3RP4 37
USB3TN4 37

USB3TP4 37

USBCOMP

OTG_ID

VBUSSENSE

USB_OC0#
USB_OC1#
USB_OC2#

USB_OC3#

SIO_EXT_WAKE#

GPP_E1

SATA_LED#

RC137 113_0402_1%

RC62 0_0402_5%~D

RC61 1K_0402_5%

RC41

USB20_N1 35

USB20_P1 35

USB20_N2 43

USB20_P2 43

USB20_N3 36
USB20_P3 36

USB20_N4 25
USB20_P4 25

USB20_N5 43
USB20_P5 43

USB20_N7 24
USB20_P7 24

USB20_N9 39
USB20_P9 39

USB20_N10 43
USB20_P10 43

1

1

1

USB_OC2# 39

1

SATA_LED# 42

2

2

2

2

0_0201_5%

Type-C PortA

WWAN

USB3.0 Type-A

Type-C PortB

Type-C PortA

Dock

Type-C PortB

NGFF (WWAN)

IR Camera

NGFF (WLAN)

USB Type-A

USH

SSD_DEVSLP 23

SIO_EXT_WAKE#30

WWAN_DEVSLP25

m2280_PCIE_SATA# 23

m3042_PCIE#_SATA 41

PD1_OTG_ID 35

PD1_VBUS_SENSE35

SIO_EXT_WAKE#

USB_OC0#

USB_OC1#

USB_OC2#

USB_OC3#

m2280_PCIE_SATA#

SATA_LED#

Type-C PortA

2

RC59 10K_0402_5%

1

RC13 10K_0402_5%

1

RC11 10K_0402_5%

1

RC14 10K_0402_5%

1

RC12 10K_0402_5%

1

RC195

1

RC201

1

2

2

2

2

2

10K_0201_5%

2

10K_0201_5%

+3V_PRIM

GPP_E1

OTG_ID

VBUSSENSE

@

RC204

RH90

RH91

2

1 2

1

1

10K_0402_5%

2

10K_0201_5%

100K_0201_5%

A A

Security Classification

Security Classification

Security Classification

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

P09-MCP(5/14)PCIE,USB,SATA

P09-MCP(5/14)PCIE,USB,SATA

P09-MCP(5/14)PCIE,USB,SATA

LA-D891P

LA-D891P

LA-D891P

1

9 65Tuesday, December 20, 2016

9 65Tuesday, December 20, 2016

9 65Tuesday, December 20, 2016

of

1.0

1.0

1.0

Vinafix.com

5

smd.db-x7.ru

WiGig--->

D D

WLAN--->

WWAN--->

SSD--->

Card Reader --->

+3VALW

C C

+1.0V_VCCST

+3V_PRIM

B B

1 2

RC90 1K_0402_5%

1 2

RC143 10K_0402_5%

1 2

RC84 8.2K_0402_5%

+3VS

1

RC97@ 8.2K_0402_5%

1 2

RC25 1K_0402_5%

1 2

RC162 10K_0402_5%@

1 2

RC189 10K_0402_5%

H_VCCST_PWRGD_P13,32

100P_0402_50V8J~D

CA4

1

2

2

CLK0_PCIE_WiGig#24

CLK0_PCIE_WiGig24

CLKREQ_PCIE#024

CLK1_PCIE_WLAN#24
CLK1_PCIE_WLAN24

CLKREQ_PCIE#124

CLK2_PCIE_WWAN#25

CLK2_PCIE_WWAN25
CLKREQ_PCIE#225

CLK_PCIE_SSD#23
CLK_PCIE_SSD23

CLKREQ_PCIE#323

CLK_PCIE_MMI#27
CLK_PCIE_MMI27

CLKREQ_PCIE#527

PCH_PCIE_WAKE#

LAN_WAKE#

BATLOW#

ME_RESET#

H_VCCST_PWRGD_P

SUSWARN #

PCH_RSMRST#

@

T7

PAD~D

H_VCCST_PWRGD_PH_CPUPWRGD

100P_0402_50V8J~D

CA3

1

2

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

3/31 check to here

H_CPUPWRGD_R

1 2

RC145 10K_0 402_5%

1

RC157 10K_0 402_5%

1 2

RC153 10K_0 402_5%

1 2

RC159 10K_0 402_5%

@

1 2

RC168 10K_0 402_5%

1 2

RC161 10K_0 402_5%

1 2

RC39 1K_0402_5%@

RC26 60.4_0402_1%

1 2

2

PLT_RST#22,23,24,25,27,30,31,34,43

PCH_RSMRST#13,30

SYS_PWROK13,30

PCH_PWROK58

PCH_DPWROK30

SUSWARN#30

SUSACK#30

PCH_PCIE_WAKE#30

LAN_WAKE#30

3.3V_IRCAM_EN#43

PCH_PLTRST#

SYS_RESET#

PCH_RSMRST#

H_CPUPWRGD

VCCST_PWRGDH_VCCST_PWRGD_P

PCH_DPWROK

SUSWARN#

PCH_PCIE_WAKE#

LAN_WAKE#

ESD Request:place near CPU side

RC215

POP
DE-POP

PCH_DPWROK

A A

0.01U_0402_16V7K

1

2

NO Support Deep sleep
Support Deep sleep

1

RC78 0_ 0402_5%@

100K_0402_5%~D

12

RC80

CC16

PCH_RSMRST#

2

XDP_DBRESET#13

if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)

5

4

UCPU1J

@

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKL-U_BGA1356

RC152

100K_0402_5%

4

CLOCK SIGNALS

RC150 0_0402_5%@

4

12

UCPU1K

@

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKL-U_BGA1356

XDP_DBRESET#

RC96@ 8.2K_0402_5%

O

SYSTEM POWER MANAGEMENT

ME_RESET#

12

SKL_ULT

1

2

+3VS

5

1

P

B

2

A

G

UC4

TC7SH08FU_SSOP5

3

SKL-U

1 2

RC34 0_0402_5%

+3VS

5

1

P

B

2

O

A

G

74AHC1G09GW _TSSOP5

3

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1
RTCX2

SRTCRST#

RTCRST#

10 OF 20

PCH_PLTRST#

2

RC154
10K_0402_5%

1

GPP_B11/EXT_PWR_GATE#

4

SYS_RESET#_R

UC3@

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CLK_ITPXDP_N_R

F43

CLK_ITPXDP_P_R

E43

BA17

E37
E35

E42

AM18
AM20

AN18
AM16

+RTCVCC

@

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B2/VRALERT#

11 OF 20

1

RC36 1K_0402_5%

Issued Date

Issued Date

Issued Date

3

SUSCLK

SUSCLK

XTAL24_IN
XTAL24_OUT

XCLK_BIASREF

PCH_RTCX1
PCH_RTCX2

SRTCRST#

RTC_RST#

RC31 2.7K_0402_1%

1U_0402_6.3V6K

1 2

RC89 20K_0201_5%

1 2

RC85

1U_0402_6.3V6K

AC_PRESENT

AT11

AP15
BA16
AY16

AN15
AW15
BB17

AN16

BA15
AY15

AU13

AU11
AP16

AM10
AM11

2

2

1 2

RC74 1K_0402_5%@

RC33 0_0402_5%

1 2

RC32 0_0402_5%

1 2

SUSCLK 23,24,25

1 2

RTC_RST# 30

12

@

1

CLRP1

CC25

20K_0201_5%

CC22

1 2

RC91 10 K_0402_5%

SIO_SLP_S0#
SIO_SLP_S3#
SIO_SLP_S4#

SIO_SLP_S5#

AC_PRESENT

BATLOW#

PME#

INTRUDER#

VRALERT#

+3VS

12

RC38

10K_0402_5%

@

SYS_RESET#

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

10K_0201_5%

2

1

2

SIO_SLP_SUS# 30,32,44,55,56,57

SIO_SLP_WLAN# 30

SIO_SLP_A# 30

SRTCRST#

PDG_An RC delay circuit with a time delay in the
range of 18–25 ms should be provided.
The circuit should be connected to VCCRTC.

+3VALW

SIO_SLP_S0# 31,45,57

SIO_SLP_S3# 30,32

SIO_SLP_S4# 30,32

@

T26

PAD~D

SIO_PWRBTN# 10,13,30

AC_PRESENT 30

@

T38

PAD~D

MPHYP_PWR_EN 45

Compal Secret Data

Compal Secret Data

Compal Secret Data

CLK_ITPXDP_N 13
CLK_ITPXDP_P 13

+1.0V_CLK

CMOS1

1

1

SHORT PADS~D

@

Deciphered Date

Deciphered Date

Deciphered Date

2

2

CMOS1 must take care
short & touch risk on layout placement

INTRUDER#

VRALERT#

SLP_S0# for support connect stand by mode

8/21 CRB1.0 change to 0603 1/10W

2

XTAL24_IN

XTAL24_OUT

PCH_RTCX1
PCH_RTCX2

RTC_RST#

RC88

1

1 2

RC60 10K_0402_5%

2

1M_0402_5%

1

CC2

1 2

1M_0402_1%

2

RC35

1

RC86
10M_0402_5%

1 2

1 2

RC87 0_0402_5%

+RTCVCC

+3V_PRIM

PCH_RTCX2_R

APS CONN

+3V_PRIM

+3VALW

+3VALW

SIO_PWRBTN#10,13,30

3

4

YC1
24MHZ_12PF_7M24090001

1

2

12

SIO_SLP_S3#

SIO_SLP_S5#

SIO_SLP_S4#

SIO_SLP_A#

RTC_RST#

SYS_RESET#

SIO_SLP_S0#

15P_0402_50V8J

CC1

1 2

15P_0402_50V8J

CC23

1 2

6.8P_0402_50V8J

YC2
9PF 20PPM 9H03280012

ESR MAX=50k ohm

CC24

1 2

6.8P_0402_50V8J

20
19
18

17

16

15
14
13

12
11
10

9
8

7
6

5
4
3

2
1

ACES_50506-01841-P01

JAPS1

GND
GND
18

17

16

15
14
13

12
11
10

9
8

7
6

5
4
3

2
1

CONN@

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P10-MCP(6/14)CLK,PM,RTC

P10-MCP(6/14)CLK,PM,RTC

P10-MCP(6/14)CLK,PM,RTC

LA-D891P

LA-D891P

LA-D891P

1

10 65Tuesday, December 20, 2016

10 65Tuesday, December 20, 2016

10 65Tuesday, December 20, 2016

1.0

1.0

1.0

of

of

Vinafix.com

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+1.0V_VCCST

1 2

RC7 49 .9_0402_1%@

1 2

RC20 1K_0402_5%

+1.0V_VCCSTG

1 2

RC28 1K_0402_5%

D D

+3VS

1 2

RC9 10K_0402_5%

1

RC163 10K_0402_5%@

+3V_PRIM

1 2

RC8 10K_0402_5%

1 2

RC68 10K_0402_5%

H_CATERR#

H_THERMTRIP#

H_PROCHOT#

TOUCH_SCREEN_PD#

2

EC_SLP_S0IX#

SIO_EXT_SMI#

NFC_DET#

H_PECI30

H_PROCHOT#3 0,50,51,54,58

H_PROCHOT#

4

1 2

RC27 499_0402_1%

XDP_OBS0_R13
XDP_OBS1_R13

@

T9

PAD~D

@

T10

PAD~D

SIO_EXT_SMI#30

TOUCH_SCREEN_PD#22

EC_SLP_S0IX#30

EDRAM_OPIO_RCOMP

12

1

RC160

2

49.9_0402_1%

12

RC167

49.9_0402_1%

H_CATERR#

H_PROCHOT#_R

H_THERMTRIP#

XDP_OBS2_R
XDP_OBS3_R

SIO_EXT_SMI#

TOUCH_SCREEN_PD#

NFC_DET#

CPU_POPIRCOMP
PCH_POPIRCOMP

EOPIO_RCOMP

12

RC123

RC122

49.9_0402_1%

49.9_0402_1%

@

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKL-U_BGA1356

UCPU1D

CPU MISC

SKL-U

3

JTAG

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_TRST#

JTAGX

4 OF 20

TCLK_XDP

B61

TDI_XDP

D60

TDO_XDP

A61

TMS_XDP

C60

TRST#_XDP

B59

PCH_JTAG_TCLK

B56

TDI_XDP

D59

TDO_XDP

A56

TMS_XDP

C59

TRST#_XDP

C61

TCLK_XDP

A59

TCLK_XDP 13
TDI_XDP 13
TDO_XDP 13

TMS_XDP 13
TRST#_XDP 13

PCH_JTAG_TCLK 13

1 2

RC3 1K_0402_5%@

2

+1.0V_VCCSTG

TDI_XDP

TDO_XDP

TMS_XDP

PCH_JTAG_TCLK

@

1

RC2 51_0402_5%

RC19 100_0402_5%

RC18 51_0402_5%

2

RC17 51_0402_5%

12

12

12

1

+1.0V_VCCSTG

+5VALW

Strap pin

1M_0201_5%

C C

ME_FWP#30

2

1

SKL-U

TPM@

@

SDIO/SDXC

CAM_CBL_DET#

GPP_G0/SD_CMD

GPP_G1/SD_DATA0
GPP_G2/SD_DATA1

GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#

GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

7 OF 20

+3V_PRIM

RH11

1

RH14

2

AB11

AB13
AB12

W12

CONTACTLESS_DET#

W11
W10

W8

EDP_ID0

W7

BA9

BB9

SD_RCOMP

AB7

AF13

RC140 200_04 02_1%

UCPU1G

@

AUDIO

SPKR28

HDA_SYNC_R
HDA_BLK_R

HDA_SDOUT_R

TPM_DET

SPKR

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

SKL-U_BGA1356

TPM_DET

TPM_DET

100K_0402_5 %

100K_0402_5 %

1 2

HDA_SYNC28
HDA_BLK28
HDA_SDOUT28

HDA_SDI028

HDA_BLK

1

CC17

B B

@

22P_0402_50V8J

Close to RC77

RF@

2P_0201_25V8B

12

CC93

2

12

HDA_SDOUT

HDA_SDI0

RF@

2P_0201_25V8B

CC94

HDA_SDOUT

HDA_SDI0

RC75 33_0402_5%

1

RC77 33_0402_5%

1 2

RC76 33_0402_5%

2

From EC, for
enable
ME code
programing

5

CAM_CBL_DET#43

SSD_PWR _EN 44
CONTACTLESS_DET# 43

WW AN_OFF# 25

SPK_ID 29
EDP_ID0 22

SD_PWR_ EN 44

NGFF_WW AN_PW REN 44

1 2

3

Q25B
DMN2400UV-7_SOT-563-6

4

SPK_DET# added on 4/15

+DVDDIO

DMN2400UV-7_SOT-563-6

CAM_CBL_DET#

WWAN_OFF#

CONTACTLESS_DET#

EDP_ID0

2

RC188

1

2

6 1

Q25A

RC53 100K_0402_5%~D

RC202 10K_0402_5%

RC200 100K_0402_5%~D

RC193

HDA_SDO

ME debug mode , this signal has
a weak internal PD
L=>security measures defined in
the Flash Descriptor will be in
effect (default)
H=>Flash Descriptor Security will
be overridden

1

1 2

1

1 2

RC92

1

1K_0402_5%

Low = Disabled

*

High = Enabled

2

2

+3V_PRIM

100K_0201_5%

+3VS

HDA_SDOUT

2

TPM BOM Optional

+3V_PRIM +3V_PRIM

A A

1

RC158 8.2K_0402_5%

@

TOP SWAP STRAP

HIGH
LOW(DEFAULT)

2

ENABLE
DISABLE

SPKR

5

Flash Descriptor Security override

HIGH
LOW(DEFAULT)

1 2

RC81 4.7K_0402_5%

@

HDA_SDOUT

DISABLE
ENABLE

4

TPM_DET

TPM

1 = W/TPM

0 = W/O TPM

Security Classification

Security Classification

Security Classification

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

P11-MCP(7/14)MISC,JTAG,HDA,SDIO

P11-MCP(7/14)MISC,JTAG,HDA,SDIO

P11-MCP(7/14)MISC,JTAG,HDA,SDIO

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

LA-D891P

LA-D891P

LA-D891P

1

1.0

1.0

1.0

11 65Tuesday, December 20, 2016

11 65Tuesday, December 20, 2016

11 65Tuesday, December 20, 2016

of

Vinafix.com

5

smd.db-x7.ru

D D

4

CFG[0..15]13

3

CFG0
CFG1

CFG2
CFG3
CFG4

CFG5
CFG6
CFG7

CFG8
CFG9
CFG10

CFG11
CFG12
CFG13

CFG14
CFG15

2

1

UCPU1S

@

1

RC29 10K_0402_1%

@

Stall reset sequence

HIGH(DEFAULT)
LOW

C C

1 2

RC40 10K_0402_1%

eDP enable

HIGH(DEFAULT)
LOW

B B

2

CFG0

No stall(Normal Operation)
stall

CFG4

Disabled
Enabled

RC37 10K_0402_1%

@

RC30 10K_0402_1%

@

+1.0VA_XDP

1

1

2

2

CFG1613
CFG1713

CFG1813

CFG1913

CFG_RCOMP

@

@

PAD~D

PAD~D

1

ITP_PMODE

1

2

RC112 49.9_0402_1%

2

RC10 1.5K_0402_5%

ITP_PMODE13

T31

T28

CFG0

CFG1

CFG2

CFG3
CFG4

CFG5

CFG6
CFG7
CFG8

CFG9
CFG10
CFG11

CFG12
CFG13
CFG14

CFG15

E68
B67

D65
D67

E70

C68

D68
C67

F71

G69

F70

G68
H70
G71

H69
G70

E63
F63

E66

F66

E60

AY2

AY1

K46
K45

AL25

AL27

C71

B70

F60

A52

BA70
BA68

J71
J68

F65

G65

F61
E61

E8

D1
D3

CFG[0]
CFG[1]

CFG[2]
CFG[3]
CFG[4]
CFG[5]

CFG[6]
CFG[7]

CFG[8]
CFG[9]

CFG[10]

CFG[11]
CFG[12]
CFG[13]

CFG[14]
CFG[15]

CFG[16]
CFG[17]

CFG[18]

CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2

RSVD_AY1

RSVD_D1
RSVD_D3

RSVD_K46
RSVD_K45

RSVD_AL25

RSVD_AL27

RSVD_C71
RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70
RSVD_TP_BA68

RSVD_J71
RSVD_J68

VSS_F65
VSS_G65

RSVD_F61
RSVD_E61

RESERVED SIGNALS-1

SKL-U

RSVD_TP_BB68

RSVD_TP_BB69

RSVD_TP_AK13
RSVD_TP_AK12

RSVD_BB2
RSVD_BA3

TP5
TP6

RSVD_D5

RSVD_D4
RSVD_B2
RSVD_C2

RSVD_B3

RSVD_A3

RSVD_AW1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4

RSVD_C4

TP4

RSVD_A69

RSVD_B69

RSVD_AY3

RSVD_D71
RSVD_C70

RSVD_C54

RSVD_D54

TP1
TP2

VSS_AY71

ZVM#

RSVD_TP_AW71
RSVD_TP_AW70

MSM#

PROC_SELECT#

BB68

BB69

AK13
AK12

BB2
BA3

AU5
AT5

D5

D4
B2
C2

B3

A3

AW1

E1
E2

BA4
BB4

A4

C4

BB5

A69

B69

AY3

D71
C70

C54

D54

AY4
BB3

AY71

AR56

AW71
AW70

AP56

C64

RC24 100K_0402_5%

PAD~D

PAD~D

PAD~D

PAD~D

PAD~D

PAD~D

PAD~D

PAD~D

PAD~D

1 2

@

T27

@

T30

@

T33

@

T34

@

T22

@

T37

@

T39

@

T40

@

T41

ZVM# for SKYLAKE-U 2+3e

Pebble Creek use 2+2e

@

T23

PAD~D

@

T29

PAD~D

MSM# for SKYLAKE-U 2+3e

+1.0V_VCCST

AW69
AW68

AU56

AW48

U12

U11
H11

C7

UCPU1T

@

RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48

RSVD_C7
RSVD_U12

RSVD_U11
RSVD_H11

SKL-U_BGA1356

SPARE

SKL-U

RSVD_F6

RSVD_E3
RSVD_C11
RSVD_B11

RSVD_A11
RSVD_D12
RSVD_C12

RSVD_F52

20 OF 20

F6

E3
C11
B11

A11
D12
C12

F52

SKL-U_BGA1356

19 OF 20

A A

Security Classification

Security Classification

Security Classification

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

P12-MCP(8/14)CFG,RSVD

P12-MCP(8/14)CFG,RSVD

P12-MCP(8/14)CFG,RSVD

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

LA-D891P

LA-D891P

LA-D891P

1

1.0

1.0

1.0

12 65Tuesday, December 20, 2016

12 65Tuesday, December 20, 2016

12 65Tuesday, December 20, 2016

of

Vinafix.com

5

smd.db-x7.ru

PVT-003.02

0.01R turn to short pad

+1.0VA

D D

RC130

1 2

@

0_0603_5%

Place
near
JXDP1

CFG[0..15]12

C C

CFG0

CFG1
CFG2
CFG3

CFG4
CFG5
CFG6

CFG7
CFG8
CFG9

CFG10
CFG11
CFG12

CFG13
CFG14
CFG15

0.1U_0402_10V7K

1

2

XDP_OBS0_R11
XDP_OBS1_R11

+1.0VA_XDP

+1.0VA_XDP

@

1

CC33

2

+1.0VS_VCCIO

+1.0V_VCCST

0.1U_0402_10V7K

@

CC37

+1.0VA_XDP

CFG3

RC141 1K_04 02_5%@XDP@

RC142 0_0402_5%@

PVT-014.04
de-pop debug XDP related resistor
pop by using Memo

RC138 0_0402_5%

@XDP@

RC136 0_0402_5%

@XDP@

1 2

RC119 150_0402_5 %@

1

RC109 150_0402_5 %@

1

RC111 10K_0402_5%@

1

RC151 51_0402_5%

@

1

2

CC26@ 0 .1U_0402_25 V6

Place near
JXDP1.47

PVT-014.02
de-pop debug XDP related resistor
pop by using Memo

2

2

1

1

1

1

2

2

RC5 need to close to JCPU1

1

H_VCCST_PW RGD_P10,32

PCH_RSMRST#10,30

FIVR_EN

PCH_SPI_DO_XDP7

SYS_PWROK10,30

B B

PCH_SPI_DO_XDP

PCH_SPI_DO2_XDP7

CFG0

XDP_PRSENT#

RC132 1K_04 02_5%@

1

RC131@XDP@

RC121 0_0402_5%

1

1

RC144

RC100 0_0402_5%

1

RC99 0_0402_5%

1

RC187 33_0201_1%@XDP@

1

1

2

@XDP@

@

@

@

2

2

1K_0402_5%

2

1K_0402_5%

2

2

2

2

+3V_PRIM

5

U44

@XDP@

P

NC

Y

A

G

NL17SZ14DFT2G_SOT353-5

3

4

4

FIVR_EN_R

FIVR_EN

2

FIVR_EN

2

CPU_XDP_PREQ#

2

RESET_OUT#_R

XDP_PRSNT_PIN1

XDP_OBS0
XDP_OBS1

H_VCCST_PWRGD_XDP

FIVR_EN_R

RESET_OUT#_R

XDP_PRSENT#

XDP_PRSENT 45

+3V_PRIM

1

RC107

2

1.5K_0402_5%

PCH_SPI_DO_XDP XDP_DBRESET#

Place near
JXDP1.48

CPU XDP

+1.0VA_XDP

XDP_PRSNT_PIN1

CPU_XDP_PREQ#9
CPU_XDP_PRDY#9

SIO_PWRBTN#10,30

DDR_XDP_SMBDAT7

DDR_XDP_SMBCLK7

PCH_JTAG_TCLK11

TCLK_XDP11

CPU_XDP_PREQ#

CFG0

CFG1

CFG2

CFG3

XDP_OBS0
XDP_OBS1

CFG4
CFG5

CFG6

CFG7

H_VCCST_PW RGD_XDP

SIO_PWRBTN#

FIVR_EN_R

RESET_OUT#_R

TCLK_XDP

3

+3VS

1K_0402_5%

1

RC120

2

0.1U_0402_25V6

@XDP@

12

CC31

PVT-014.03
de-pop debug XDP related resistor
pop by using Memo

JXDP1

1

1

3

3

5

5

7

7

9

9

111112

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

595960

61

61

GND62GND

JXT_FP270H-061G1AM

CONN@

2

4
6

8

10

14
16
18

20

22

24
26
28

30
32
34

36

38

40
42
44

46
48
50

52
54
56

58

Place near
JXDP1.41

2

4
6

8

10
12

14
16
18

20

22

24
26
28

30
32
34

36

38

40
42
44

46
48
50

52
54
56

58
60

63

SIO_PWRBTN#

+1.0VA_XDP

CFG17
CFG16

CFG8
CFG9

CFG10
CFG11

CFG19

CFG18

CFG12

CFG13

CFG14
CFG15

XDP_DBRESET#

TDO_XDP

TRST#_XDP

TDI_XDP

TMS_XDP

XDP_PRSENT#

+3VALW

1.5K_0402_5%

1

RC127

2

0.1U_0402_25V6

@

CC36

12

CFG17 12
CFG16 12

CFG8 12

CFG9 12

CFG10 12
CFG11 12

CFG19 12

CFG18 12

CFG12 12

CFG13 12

CFG14 12

CFG15 12

CLK_ITPXDP_P 10
CLK_ITPXDP_N 10

ITP_PMODE 12

XDP_DBRESET# 10

TDO_XDP 11

TRST#_XDP 11

TDI_XDP 11

TMS_XDP 11

2

TMS_XDP

TDI_XDP

TDO_XDP

TRST#_XDP

TCLK_XDP

51_0402_5%

51_0402_5%

100_0402_5%

51_0402_5%

51_0402_5%

1

+1.0V_VCCSTG

2

2

RC98

1

RC101

12

RC110

1

RC106

12

@

RC102

12

A A

Security Classification

Security Classification

Security Classification

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

P13-MCP(9/14)XDP

P13-MCP(9/14)XDP

P13-MCP(9/14)XDP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

LA-D891P

LA-D891P

LA-D891P

1

13 65Tuesday, December 20, 2016

13 65Tuesday, December 20, 2016

13 65Tuesday, December 20, 2016

of

of

1.0

1.0

1.0

Vinafix.com

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4

3

2

1

PSC(Primary side cap) : Place as close to the package as possible
BSC(Backside cap) : Place on secondary side, underneath the package

Component placement order:
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source

+VCC_CORE: 0.55~1.5V, 29A

D D

+VCC_EDRAM: 1V, 2.5A
+V1.8S_EDRAM: 1.8V, 50mA
+VCC_EOPIO: 0.8~1V, 2A

@

T8

PAD~D

@

T18

PAD~D

C C

+VCC_CORE +VCC_CORE

SKL-U

CPU POWER 1 OF 4

1.5V@29A

1V@2.5A

1V@0.05A

VCC_G32
VCC_G33

VCC_G35
VCC_G37
VCC_G38

VCC_G40
VCC_G42

VCC_J30

VCC_J33
VCC_J37

VCC_J40
VCC_K33
VCC_K35
VCC_K37

VCC_K38
VCC_K40

VCC_K42
VCC_K43

VCC_SENSE

VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

12 OF 20

G32
G33

G35
G37
G38

G40
G42
J30

J33
J37

J40
K33
K35
K37

K38
K40

K42
K43

E32

VCCSENSE

E33

VSSSENSE

H_CPU_SVIDALRT#

B63

VIDSCLK_R

A63

VIDSOUT_R

D64

G20

+1.0V_VCCSTG_R

+VCC_CORE_G0

+VCC_CORE_G1

@

A30

VCC_A30

A34

VCC_A34

A39

VCC_A39

A44

VCC_A44

AK33

VCC_AK33

AK35

VCC_AK35

AK37

VCC_AK37

AK38

VCC_AK38

AK40

VCC_AK40

AL33

VCC_AL33

AL37

VCC_AL37

AL40

VCC_AL40

AM32

VCC_AM32

AM33

VCC_AM33

AM35

VCC_AM35

AM37

VCC_AM37

AM38

VCC_AM38

G30

VCC_G30

K32

RSVD_K32

AK32

RSVD_AK32

AB62

VCCOPC_AB62

P62

VCCOPC_P62

V62

VCCOPC_V62

H63

VCC_OPC_1P8_H63

G61

VCC_OPC_1P8_G61

AC63

VCCOPC_SENSE

AE63

VSSOPC_SENSE

AE62

VCCEOPIO

AG62

VCCEOPIO

AL63

VCCEOPIO_SENSE

AJ62

VSSEOPIO_SENSE

SKL-U_BGA1356

UCPU1L

1V@2A

RC1

+VCC_CORE

1

2

12

1 2

Close CPU

RC5

100_0402_1%

RC6

100_0402_1%

0_0402_5%

VCCSENSE 58
VSSSENSE 58

+1.0V_VCCSTG

VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e
(w/ on package cache)

SVID ALERT

+1.0V_VCCST

56_0402_1%

1

RC94

CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 - 1500mils

2

VIDALERT_N58

SVID DATA

B B

VIDSOUT58

SVID CLK

+1.0V_VCCST

100_0402_1%

12

+1.0V_VCCST

100_0402_1%

12

RC93

CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 - 1500mils

@

RC95

CAD Note: Place the PU resistors close to CPU

H_CPU_SVIDALRT#

12

RC22220_0402_5%

12

RC230_0402_5%~D

VIDSOUT_R

RC208close to CPU 300 - 1500mils

VIDSCLK58

12

RC210_0402_5%~D

VIDSCLK_R

CDI#61280

10.2.7 SVID Topology

A A

Table 10-9. SVID Bus Routing Guidelines
need double pull high

Security Classification

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

P14-MCP(10/14)PWR-VCC CORE

P14-MCP(10/14)PWR-VCC CORE

P14-MCP(10/14)PWR-VCC CORE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

LA-D891P

LA-D891P

LA-D891P

1

1.0

1.0

1.0

14 65Tuesday, December 20, 2016

14 65Tuesday, December 20, 2016

14 65Tuesday, December 20, 2016

of

of

Security Classification

DELL CONFIDENTIAL/PROPRIETARY

Security Classification

Vinafix.com

5

smd.db-x7.ru

4

3

2

1

+VCCGT: 0.55~1.5V, 54A
+VCCGTX : 0.55~1.5V, 7A

+VCC_GT +VCC_GT

D D

C C

+VCC_GT

1

Close CPU

VCC_GT_SENSE58

VSS_GT_SENSE58

B B

RC44

100_0402_1%

2

VCC_GT_SENSE

VSS_GT_SENSE

1

A48

A53
A58
A62

A66
AA63
AA64

AA66
AA67
AA69

AA70
AA71
AC64

AC65
AC66
AC67

AC68
AC69
AC70

AC71

J43

J45

J46

J48

J50

J52

J53

J55

J56

J58

J60

K48

K50

K52

K53

K55

K56

K58

K60

L62

L63

L64

L65

L66

L67

L68

L69

L70

L71

M62

N63

N64
N66
N67

N69

J70

J69

UCPU1M

@

CPU POWER 2 OF 4

VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT

VCCGT
VCCGT
VCCGT
VCCGT

VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT

VCCGT_SENSE

VSSGT_SENSE

SKL-U_BGA1356

SKL-U

1.5V@54A

1.5V@7A

VCCGTX_SENSE

VSSGTX_SENSE

VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45

VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50

VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55

VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60

VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46

VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56

VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50

VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56

VCCGTX_AM58
VCCGTX_AU58

VCCGTX_AU63

VCCGTX_BB57

VCCGTX_BB66

13 OF 20

N70

N71
R63
R64

R65
R66
R67

R68
R69
R70

R71
T62
U65

U68
U71
W63

W64
W65
W66

W67
W68
W69

W70
W71
Y62

AK42
AK43
AK45

AK46
AK48
AK50

AK52
AK53
AK55

AK56
AK58
AK60

AK70
AL43
AL46

AL50
AL53
AL56

AL60
AM48
AM50

AM52
AM53
AM56

AM58
AU58

AU63
BB57
BB66

AK62
AL61

+VCC_GTUS

Reserve for soldering

VCCGTX for SKYLAKE-U 2+3e
Merged the GT and GTx rail

RC42

100_0402_1%

2

A A

Security Classification

Security Classification

Security Classification

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

P15-MCP(11/14)PWR-VCCGT

P15-MCP(11/14)PWR-VCCGT

P15-MCP(11/14)PWR-VCCGT

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

LA-D891P

LA-D891P

LA-D891P

1

15 65Tuesday, December 20, 2016

15 65Tuesday, December 20, 2016

15 65Tuesday, December 20, 2016

of

1.0

1.0

1.0

Vinafix.com

5

smd.db-x7.ru

4

3

2

1

+1.2V_DDR: 1.2V, 3.5A
+1.0V_VCCST: 1V, 120mA; VCCPLL: 1V, 120mA
+1.0V_VCCSTG: 1V, 40mA
+VCCPLL_OC: 1.2V, 260mA
+1.0VS_VCCIO: 0.85~0.95V, 3.1A
+VCC_SA: 1.15V, 5.1A

D D

+1.2V_MEM_CPUCLK+1.2V_DDR

+1.2V_MEM_CPUCLK

PSC

1

CC68

2

1U_0201_6.3V6M

+1.2V_MEM_CPUCLK

1

RC156 0_0402_5%

2

BSCPSC

1

2

+1.2V_MEM_CPUCLK (VDDQC) Place on CPU
Back Side (underneath the package):
1U_0201*1 pcs (@)
Primary Side (close to package):

C C

10U_0402 * 1 pcs

1

CC83

CC76

2

@

10U_0402_6.3V6M

1U_0201_6.3V6M

+1.0V_VCCST

close to package

1

2

PSC

CC35

+1.0V_VCCSTG

1U_0402_6.3V6K

BSC

underneath the package

1

2

+VCCPLL_OC +1.0V_VCCST

CC4

@

1U_0402_6.3V6K

+1.2V_DDR

1V@0.12A

1V@0.04A

1.2V@0.26A

1V@0.12A

PSC

close to packageclose to package

AU23
AU28

AU35
AU42
BB23

BB32
BB41
BB47

BB51

AM40

A18

A22

AL23

K20

K21

1

2

CC3

UCPU1N

@

CPU POWER 3 OF 4

VDDQ_AU23
VDDQ_AU28

VDDQ_AU35
VDDQ_AU42
VDDQ_BB23

VDDQ_BB32
VDDQ_BB41
VDDQ_BB47

VDDQ_BB51

VDDQC

VCCST

VCCSTG_A22

VCCPLL_OC

VCCPLL_K20

VCCPLL_K21

SKL-U_BGA1356

1U_0402_6.3V6K

SKL-U

0.95V@3.1A

1.2V@3.5A

1.15V@5.1A

+VCC_SA

VCCIO
VCCIO

VCCIO
VCCIO
VCCIO

VCCIO
VCCIO

VCCSA
VCCSA
VCCSA

VCCSA
VCCSA
VCCSA

VCCSA
VCCSA
VCCSA

VCCSA
VCCSA
VCCSA

VCCSA
VCCSA

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

14 OF 20

1 2

RC116 100_0402_1%

+1.0VS_VCCIO

AK28
AK30

AL30
AL42
AM28

AM30
AM42

AK23
AK25
G23

G25
G27
G28

J22
J23
J27

K23
K25
K27

K28
K30

AM23

AM22

H21
H20

+VCC_SA

VCCIO_SENSE
VSSIO_SENSE

+1.0VS_VCCIO

12

RC115

100_0402_1%

VSA_SEN- 58
VSA_SEN+ 58

12

12

Close CPU

RC147

100_0402_1%

VCCIO_SENSE 57
VSSIO_SENSE 5 7

RC155

100_0402_1%

+1.2_DDR Decoupling Requirment
Back Side (underneath the package):
10U_0402*2 pcs + 1U_0201*4 pcs (@)
Primary Side (close to package):
10U_0402*4 pcs + 22U_0603*3 pcs

B B

+1.2V_DDR

PSC

1

1

1

CC86

CC87

CC88

2

22U_0603_6.3V6M

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

CC82

CC19

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

CC20

CC84

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

BSC

1

1

CC85

2

CC18

2

@

@

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

CC77

CC80

2

2

@

@

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CC74

CC75

2

2

@

@

1U_0201_6.3V6M

1U_0201_6.3V6M

+1.0VS_VCCIO Decoupling Requirment
Back Side (underneath the package):
10U_0402*2 pcs + 1U_0201*4 pcs (@)
Primary Side (close to package):
1U_0402*4 pcs

+1.0VS_VCCIO

PSC

1

1

CC60

CC69

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CC63

2

2

1U_0402_6.3V6K

BSC

1

1

1

1

CC67

2

2

@

10U_0402_6.3V6M

CC71

CC62

2

@

10U_0402_6.3V6M

2

@

1U_0201_6.3V6M

CC61

1U_0402_6.3V6K

1

1

CC66

CC72

CC65

@

1U_0201_6.3V6M

2

2

@

@

1U_0201_6.3V6M

1U_0201_6.3V6M

A A

Security Classification

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

P16-MCP(12/14)PWR-VCCIO,MEM

P16-MCP(12/14)PWR-VCCIO,MEM

P16-MCP(12/14)PWR-VCCIO,MEM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

LA-D891P

LA-D891P

LA-D891P

1

1.0

1.0

1.0

16 65Tuesday, December 20, 2016

16 65Tuesday, December 20, 2016

16 65Tuesday, December 20, 2016

of

Security Classification

DELL CONFIDENTIAL/PROPRIETARY

Security Classification

Vinafix.com

5

smd.db-x7.ru

D D

C C

+3VALW +1 .8VA +1.0VA +1.0V_PRIM_CORE

1

CC73

2

47U_0805_6.3V6M

+1.0VA

+1.0V_MPHYGT

1

2

1 2

RC125 0_0603_5%

1 2

RC47 0_0 402_5%

1 2

RC133 0_0603_5%

1 2

RC128 0_0402_5%

CC47

47U_0805_6.3V6M

1

2

+1.0V_MPHYAON

+1.0V_SRAM

+1.0V_APLLEBB

CC29

+1.0V_DTS

1

CC52

2

47U_0805_6.3V6M

47U_0805_6.3V6M

+1.5VS_AUDIO

12

RC185

@

0_0603_5%

+3V_PRIM

12

RC186
0_0603_5%

L23

1 2

BLM18EG221SN1D_2P

CC53

2P_0201_25V8B

12

CDI#561280
3/23 follow PDG 5.76GHz
An EMI Filter Implementation to Isolate

5.76 GHz Noise Coming From VccHDA

4

1

CC32

2

1U_0402_6.3V6K

1

CC14

2

1U_0402_6.3V6K

close UC1.AL1 and <120mil

+1.0V_MPHYGT

close UC1.K17 and <120mil

close UC1.N15 and CC210 <400mil, CC211 <120mil

1

1

CC43

CC39

2

2

@

CC64

2P_0201_25V8B

12

1U_0402_6.3V6K

47U_0805_6.3V6M

close UC1.AJ19 and <400mil

+1.0V_SRAM

close UC1.AF20 and <400mil

1

2

@

CC44

+1.0V_APLLEBB

1U_0402_6.3V6K

1

CC54

2

@

1U_0402_6.3V6K

close UC1.AF18 and <400mil

+1.0V_AMPHYPLL

close UC1.N18 and <120mil

1

CC38

2

1U_0402_6.3V6K

+1.0VA+1.0V_PRIM_CORE+1.0V_MPHYAON

close UC1.AB19 and <400mil

1

CC51

2

@

1U_0402_6.3V6K

1.0V@0.696A

1.0V@2.57A

1.0V@0.022A

1.0V@2.1A

1.0V@0.088A

+1.0V_APLL

+1.0VA

+3VALW

1.0V@0.026A

3.3V@0.118A

1.5V@0.068A

+3.3V_SPI

3.3V@0.011A

1.0V@0.642A

+3V_PRIM

+1.0VA

3.3V@0.075A

1.0V@0.033A

3

PCH PWR

+1.8VA

UCPU1O

@

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

SKL-U_BGA1356

CPU POWER 4 OF 4

SKL-U

VCCPGPPA
VCCPGPPB

VCCPGPPC
VCCPGPPD

VCCPGPPE

VCCPGPPF

VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19
VCCRTC_BB14

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

15 OF 20

2

RC134 0_0603_5%

1 2

RC139 0_0603_5%

AK15

3.3V@0.085A

AG15

Y16
Y15
T16

AF16

1.8V@0.161A

AD15

V19

T1

AA1

1.8V@0.006A

AK17

3.3V@0.001A

AK19

3.0V@0.001A

BB14

BB10

A14

K19

L21

N20

L19

A10

AN11
AN13

close UC1.BB10 and <120mil

+VCCCLK1

1.0V@0.135A

+VCCCLK2

+VCCCLK3

+VCCCLK4

+VCCCLK5

+VCCCLK6

1 2

+1.8V_PGPP

+3.3V_PGPP

+1.8V_PGPP

+3.3V_PGPP

close UC1.V19 and <120mil

+1.0V_DTS

CORE_VID0 57

CORE_VID1 57

1

close UC1.AG15 and <120milclose UC1.Y16 and <400milclose UC1.T16 and <400mil

1

CC58

2

@

1U_0402_6.3V6K

+3V_PRIM +1.8VA

12

CC46

close UC1.AA1 and <400mil

1

CC50

2

@

1U_0402_6.3V6K

1

CC48

2

4.7P_0402_50V8C

1U_0402_6.3V6K

1

CC45

2

@

+3V_PRIM

1U_0402_6.3V6K

close UC1.AK17 and <120mil

close UC1.AK19 and <120mil

1

1

CC81

2

CC70

2

0.1U_0402_10V7K

+RTCVCC

1

CC79

2

1U_0402_6.3V6K

0.1U_0402_10V7K

1

1

CC57

CC56

2

2

1U_0402_6.3V6K

0.1U_0402_10V7K

+3.3V_PGPP+3V_PRIM

B B

+1.0V_AMPHYPLL+1.0V_MPHYGT

1 2

RC129 0_0402_5%

+1.0VA

close UC1.V15 and <100mil

12

A A

L30

1 2

BLM18EG221SN1D_2P

CC92

2P_0201_25V8B

1

2

12

close UC1.K15 and <120mil

1

CC34

2

@

+1.0V_APLL

R121
0_0201_5%

CC49
2P_0201_25V8B

RC103 0_0603_5%

1U_0402_6.3V6K

+3VALW

22U_0603_6.3V6M

22U_0603_6.3V6M

@

@

CC55

CC59

1

1

2

2

place near AD17,AD18,AJ17

2

1

+1.0V_CLK+1.0VA

close UC1.A10 and <120mil

1

CC28

2

1U_0402_6.3V6K

@

+1.0V_CLK

1

2

RC16

1 2

0_0402_5%

RC117

1

0_0603_5%

RC104

1

0_0603_5%

CC27
22U_0603_6.3V6M

+VCCCLK1

1

CC5

0.1U_0201_10V6K

2

Close to Pin A14 Close to Pin N20

2

2

+VCCCLK2

1

CC42

0.1U_0201_10V6K

2

+VCCCLK3

+1.0V_CLK

1

2

RC118

1 2

0_0603_5%

RC105

1

0_0603_5%

RC15

1

0_0402_5%

CC30
22U_0603_6.3V6M

+VCCCLK4

1

CC40

0.1U_0201_10V6K

2

2

+VCCCLK5

1

CC41

0.1U_0201_10V6K

2

Close to Pin L19Close to Pin K19

2

+VCCCLK6

DELL CONFIDENTIAL/PROPRIETARY

Security Classification

Security Classification

Security Classification

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

P17-MCP(13/14)PCH PWR

P17-MCP(13/14)PCH PWR

P17-MCP(13/14)PCH PWR

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

LA-D891P

LA-D891P

LA-D891P

1

17 65Tuesday, December 20, 2016

17 65Tuesday, December 20, 2016

17 65Tuesday, December 20, 2016

1.0

1.0

1.0

Vinafix.com

5

smd.db-x7.ru

4

3

2

1

Note1: VCCPRIM_CORE Implementation with PCH CORE_VID Recommendation

R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424

GND 2 OF 3

SKL-U

VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS

VSS

BA49

BA53
BA57
BA6

BA62
BA66
BA71

BB18
BB26
BB30

BB34
BB38
BB43

BB55
BB6
BB60

BB64
BB67
BB70

C1
C25
C5

D10
D11
D14

D18
D22
D25

D26
D30
D34

D39
D44
D45

D47
D48

D53
D58
D6

D62
D66
D69

E11
E15
E18

E21
E46
E50

E53
E56
E6

E65
E71
F1

F13
F2
F22

F23
F27
F28

F32
F33
F35

F37
F38
F4

F40
F42

BA41

UCPU1R

@

F8

VSS

G10

VSS

G22

VSS

G43

VSS

G45

VSS

G48

VSS

G5

VSS

G52

VSS

G55

VSS

G58

VSS

G6

VSS

G60

VSS

G63

VSS

G66

VSS

H15

VSS

H18

VSS

H71

VSS

J11

VSS

J13

VSS

J25

VSS

J28

VSS

J32

VSS

J35

VSS

J38

VSS

J42

VSS

J8

VSS

K16

VSS

K18

VSS

K22

VSS

K61

VSS

K63

VSS

K64

VSS

K65

VSS

K66

VSS

K67

VSS

K68

VSS

K70

VSS

K71

VSS

L11

VSS

L16

VSS

L17

VSS

SKL-U_BGA1356

GND 3 OF 3

SKL-U

VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

18 OF 20

L18
L2

L20
L4
L8

N10
N13
N19

N21
N6
N65

N68
P17
P19

P20
P21
R13

R6
T15
T17

T18
T2
T21

T4
U10
U63

U64
U66
U67

U69
U70
V16

V17
V18
W13

W6
W9
Y17

Y19
Y20
Y21

AT63

AT68
AT71

AU10

AU15
AU20
AU32

AU38

AV1

AV68

AV69
AV70
AV71

AW10
AW12
AW14

AW16
AW18
AW21

AW23
AW26
AW28

AW30
AW32
AW34

AW36
AW38
AW41

AW43
AW45
AW47

AW49
AW51
AW53

AW55
AW57

AW6

AW60
AW62

AW64
AW66

AW8

AY66

B10
B14

B18
B22
B30

B34
B39
B44

B48
B53
B58

B62
B66
B71

BA1
BA10
BA14

BA18

BA2
BA23

BA28
BA32
BA36

F68

BA45

UCPU1Q

@

VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS

VSS

GND 1 OF 3

SKL-U

VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS
VSS

VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS

AL65

AL66
AM13
AM21

AM25
AM27
AM43

AM45
AM46
AM55

AM60
AM61
AM68

AM71
AM8
AN20

AN23
AN28
AN30

AN32
AN33
AN35

AN37
AN38
AN40

AN42
AN58
AN63

AP10
AP18
AP20

AP23
AP28
AP32

AP35
AP38
AP42

AP58
AP63
AP68

AP70
AR11
AR15

AR16
AR20
AR23

AR28
AR35

AR42
AR43
AR45

AR46
AR48
AR5
AR50

AR52
AR53

AR55
AR58
AR63

AR8
AT2
AT20

AT23
AT28
AT35

AT4
AT42
AT56

AT58

UCPU1P

@

A5

VSS

A67

VSS

A70

VSS

AA2

VSS

AA4

D D

C C

B B

AA65

AA68
AB15
AB16

AB18
AB21

AB8

AD13
AD16
AD19

AD20
AD21
AD62

AD8
AE64
AE65

AE66
AE67
AE68

AE69

AF1
AF10

AF15
AF17

AF2

AF4
AF63

AG16

AG17
AG18
AG19

AG20
AG21
AG71

AH13

AH6

AH63

AH64
AH67

AJ15

AJ18
AJ20

AJ4

AK11
AK16
AK18

AK21
AK22
AK27

AK63
AK68

AK69

AK8

AL2

AL28

AL32
AL35

AL38

AL4

AL45

AL48
AL52
AL55

AL58
AL64

VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS

VSS
VSS
VSS
VSS

VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS

SKL-U_BGA1356

16 OF 20

SKL-U_BGA1356

17 OF 20

A A

Security Classification

Security Classification

Security Classification

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

P18-MCP(14/14)VSS

P18-MCP(14/14)VSS

P18-MCP(14/14)VSS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

LA-D891P

LA-D891P

LA-D891P

1

18 65Tuesday, December 20, 2016

18 65Tuesday, December 20, 2016

18 65Tuesday, December 20, 2016

of

1.0

1.0

1.0

Vinafix.com

5

smd.db-x7.ru

4

3

2

1

+1.8VU +1.8VU

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

DDR_A_DQS#[0..7]6

DDR_A_DQS[0..7]6

DDR_A_D[0..63]6

DDR_A_CA1_[0..9]6

DDR_A_CA2_[0..9]6

D D

+1.2V_DDR

10U_0603_6.3V6M~D

CD2

12

12

+1.2V_DDR

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD40

CD23

1

2

CD83

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD24

1

1

2

2

+1.8VU

CD36

1

2

+1.2V_DDR

CD18

+1.2V_DDR

+1.2V_DDR +1.2V_DDR +1.2V_DDR

Closed to UD19

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CD59

12

C C

1U_0402_6.3V6K~D

CD38

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD9

1

2

CD37

1

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

CD11

1

2

CD16

1

1

CD27

2

2

+1.2V_DDR +1.2V_DDR

+1.2V_DDR +1.2V_DDR

10U_0603_6.3V6M~D

CD31

12

B B

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD10

CD14

1

1

2

2

UD4

@

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1

A10

VDD1

U3

VDD1

U4

VDD1

U5

VDD1

U6

VDD1

U10

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

H12

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

K12

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

A11

VDDQ

C12

VDDQ

E8

VDDQ

E12

VDDQ

G12

VDDQ

H8

VDDQ

H9

VDDQ

H11

VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

K11

VDDQ

L12

VDDQ

N8

VDDQ

N12

VDDQ

R12

VDDQ

U11

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

A12

NC

A13

NC

B1

NC

B13

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

U12

NC

U13

NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

P12

VSSQ

N6

VSSQ

M12

VSSQ

M6

VSSQ

L9

VSSQ

K10

VSSQ

H10

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

D12

VSSQ

C6

VSSQ

B12

VSSQ

B6

VSSQ

H9CCNNN8JTMLAR-NTM_FBGA178~D

DQS0#

DQS1#

DQS2#

DQS3#

Vref_DQ

Vref_CA

DQ0

DQ1
DQ2

DQ3

DQ4

DQ5
DQ6
DQ7

DQ8
DQ9

DQ10
DQ11

DQ12

DQ13
DQ14

DQ15

DQ16
DQ17

DQ18
DQ19

DQ20

DQ21
DQ22
DQ23

DQ24

DQ25
DQ26
DQ27

DQ28
DQ29

DQ30
DQ31

CA0

CA1

CA2
CA3

CA4

CA5

CA6
CA7

CA8

CA9

DQS0

DQS1

DQS2

DQS3

DM0

DM1

DM2

DM3

ZQ0

ZQ1

CKE0
CKE1

CS0#
CS1#

CK#

ODT

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS
VSS

DDR_A_D27

P9

DDR_A_D29

N9

DDR_A_D25

N10

DDR_A_D31

N11

DDR_A_D28

M8

DDR_A_D24

M9

DDR_A_D30

M10

DDR_A_D26

M11

DDR_A_D20

F11

DDR_A_D17

F10

DDR_A_D22

F9

DDR_A_D18

F8

DDR_A_D21

E11

DDR_A_D16

E10

DDR_A_D23

E9

DDR_A_D19

D9

DDR_A_D51

T8

DDR_A_D55

T9

DDR_A_D49

T10

DDR_A_D53

T11

DDR_A_D50

R8

DDR_A_D54

R9

DDR_A_D48

R10

DDR_A_D52

R11

DDR_A_D56

C11

DDR_A_D61

C10

DDR_A_D62

C9

DDR_A_D59

C8

DDR_A_D60

B11

DDR_A_D57

B10

DDR_A_D63

B9

DDR_A_D58

B8

DDR_A_CA1_0

R2

DDR_A_CA1_1

P2

DDR_A_CA1_2

N2

DDR_A_CA1_3

N3

DDR_A_CA1_4

M3

DDR_A_CA1_5

F3

DDR_A_CA1_6

E3

DDR_A_CA1_7

E2

DDR_A_CA1_8

D2

DDR_A_CA1_9

C2

DDR_A_DQS3

L10

DDR_A_DQS2

G10

DDR_A_DQS6

P10

DDR_A_DQS7

D10

DDR_A_DQS#3

L11

DDR_A_DQS#2

G11

DDR_A_DQS#6

P11

DDR_A_DQS#7

D11

L8

G8

P8

D8

DDR_A0_ZQ0

B3

DDR_A0_ZQ1

B4

K3
K4

DDR_A_CS#0

L3

DDR_A_CS#1

L4

J3

CK

J2

DDR_A_ODT0

J8

J11

H4

B2

B5

C5

E4

E5

F5

H2

J12

K2

L6

M5

N4
N5

R4

R5

T2

T3
T4
T5

RD20 240_0402_1%

1 2

RD19 240_0402_1%

1 2

DDR_A_CKE0 6

DDR_A_CKE1 6

DDR_A_CS#0 6

DDR_A_CS#1 6

DDR_A_CLK0 6

DDR_A_CLK#06

DDR_A_ODT0 6

+VREFDQ_A

+VREFCA

Closed to DRAM Closed to DRAM

+VREFDQ_A

0.047U_0402_10V7K~D

CD21

1

2

0.047U_0402_10V7K~D

CD22

1

2

+1.2V_DDR +1.2V_ DDR +1.2V_DDR +1.2V_DDR

Closed to UD20

10U_0603_6.3V6M~D

CD80

12

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD79

1

2

All VREF traces should
have 10 mil trace width

+1.8VU

10U_0603_6.3V6M~D

12

+1.2V_DDR +1.2V_DDR

10U_0603_6.3V6M~D

CD12

12

1U_0402_6.3V6K~D

CD63

1

2

10U_0603_6.3V6M~D

CD3

12

+1.8VU

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD50

CD84

1

2

+1.8VU

CD54

1

2

+1.2V_DDR

1U_0402_6.3V6K~D

CD61

1

2

0.1U_0402_16V7K~D

1U_0402_6.3V6K~D

CD39

1

2

CD65

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD77

CD60

1

1

2

2

0.1U_0402_16V7K~D

1

2

1

CD74

CD57

2

+1.2V_DDR+1.2V_DDR

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD56

CD58

1

1

2

2

UD2

@

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1

A10

VDD1

U3

VDD1

U4

VDD1

U5

VDD1

U6

VDD1

U10

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

H12

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

K12

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

A11

VDDQ

C12

VDDQ

E8

VDDQ

E12

VDDQ

G12

VDDQ

H8

VDDQ

H9

VDDQ

H11

VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

K11

VDDQ

L12

VDDQ

N8

VDDQ

N12

VDDQ

R12

VDDQ

U11

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

A12

NC

A13

NC

B1

NC

B13

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

U12

NC

U13

NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

P12

VSSQ

N6

VSSQ

M12

VSSQ

M6

VSSQ

L9

VSSQ

K10

VSSQ

H10

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

D12

VSSQ

C6

VSSQ

B12

VSSQ

B6

VSSQ

H9CCNNN8JTMLAR-NTM_FBGA178~D

Vref_DQ

Vref_CA

DQ0

DQ1
DQ2

DQ3

DQ4

DQ5
DQ6
DQ7

DQ8
DQ9

DQ10
DQ11

DQ12

DQ13
DQ14

DQ15

DQ16
DQ17

DQ18
DQ19

DQ20

DQ21
DQ22
DQ23

DQ24

DQ25
DQ26
DQ27

DQ28
DQ29

DQ30
DQ31

CA0

CA1

CA2
CA3

CA4

CA5

CA6
CA7

CA8

CA9

DQS0

DQS1

DQS2

DQS3

DQS0#

DQS1#

DQS2#

DQS3#

DM0

DM1

DM2

DM3

ZQ0

ZQ1

CKE0
CKE1

CS0#
CS1#

CK#

ODT

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS
VSS

DDR_A_D12

P9

DDR_A_D8

N9

DDR_A_D10

N10

DDR_A_D14

N11

DDR_A_D13

M8

DDR_A_D9

M9

DDR_A_D15

M10

DDR_A_D11

M11

DDR_A_D7

F11

DDR_A_D1

F10

DDR_A_D0

F9

DDR_A_D5

F8

DDR_A_D3

E11

DDR_A_D6

E10

DDR_A_D4

E9

DDR_A_D2

D9

DDR_A_D40

T8

DDR_A_D45

T9

DDR_A_D43

T10

DDR_A_D47

T11

DDR_A_D44

R8

DDR_A_D41

R9

DDR_A_D46

R10

DDR_A_D42

R11

DDR_A_D33

C11

DDR_A_D37

C10

DDR_A_D34

C9

DDR_A_D39

C8

DDR_A_D36

B11

DDR_A_D32

B10

DDR_A_D35

B9

DDR_A_D38

B8

DDR_A_CA2_0

R2

DDR_A_CA2_1

P2

DDR_A_CA2_2

N2

DDR_A_CA2_3

N3

DDR_A_CA2_4

M3

DDR_A_CA2_5

F3

DDR_A_CA2_6

E3

DDR_A_CA2_7

E2

DDR_A_CA2_8

D2

DDR_A_CA2_9

C2

DDR_A_DQS1

L10

DDR_A_DQS0

G10

DDR_A_DQS5

P10

DDR_A_DQS4

D10

DDR_A_DQS#1

L11

DDR_A_DQS#0

G11

DDR_A_DQS#5

P11

DDR_A_DQS#4

D11

L8

G8

P8

D8

DDR_A1_ZQ0

B3

DDR_A1_ZQ1

B4

K3
K4

DDR_A_CS#0

L3

DDR_A_CS#1

L4

J3

CK

J2

DDR_A_ODT0

J8

J11

H4

B2

B5

C5

E4
E5

F5

H2

J12

K2

L6

M5

N4
N5

R4

R5

T2

T3
T4
T5

RD1 240_0402_1%

1 2

RD2 240_0402_1%

1 2

DDR_A_CKE2 6
DDR_A_CKE3 6

DDR_A_CLK1 6
DDR_A_CLK#1 6

+VREFDQ_A

+VREFCA

+VREFDQ_A+VREFCA +VREFCA

0.047U_0402_10V7K~D

CD71

1

2

1

2

0.047U_0402_10V7K~D

CD69

Decoupling per DRAM device
VDDQ 4x 0402 1uF 2x 0201 0.1uF 1x 0603 10uF
VDDCA 2x 0402 1uF 1x 0603 10uF
VDD2 3x 0402 1uF 1x 0603 10uF
VDD1 2x 0402 1uF 1x 0603 10uF

A A

intel uesd 0201 for 0.1uF

+1.2V_DDR

10U_0603_6.3V6M~D

12

+1.8VU

10U_0603_6.3V6M~D

CD32

CD41

12

DELL CONFIDENTIAL/PROPRIETARY

Security Classification

Security Classification

Security Classification

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P19-DDRIII Channel A

P19-DDRIII Channel A

P19-DDRIII Channel A

LA-D891P

LA-D891P

LA-D891P

1

19 65Tuesday, December 20, 2016

19 65Tuesday, December 20, 2016

19 65Tuesday, December 20, 2016

1.0

1.0

1.0

Vinafix.com

5

smd.db-x7.ru

4

3

2

1

DDR_B_DQS#[0..7]6

DDR_B_DQS[0..7]6

DDR_B_D[0..63]6

DDR_B_CA1_[0..9]6

DDR_B_CA2_[0..9]6

D D

10U_0603_6.3V6M~D

12

+1.2V_DDR

10U_0603_6.3V6M~D

CD17

1

2

+1.2V_DDR +1.2V_DDR +1.2V_DDR +1.2V_DDR

10U_0603_6.3V6M~D

CD1

12

C C

Closed to UD21

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD13

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD30

1

2

CD82

1

2

+1.2V_DDR

10U_0603_6.3V6M~D

CD73

1

2

B B

+1.8VU+1.8VU

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD49

CD35

1

2

+1.8VU +1.8VU

CD7

1

2

+1.2V_DDR

1U_0402_6.3V6K~D

CD51

1

2

0.1U_0402_16V7K~D

CD15

1

2

+1.2V_DDR

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD33

CD76

1

1

2

2

0.1U_0402_16V7K~D

1

2

1

CD28

CD6

2

+1.2V_DDR

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD29

1

2

CD5

1

2

UD3

@

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1

A10

VDD1

U3

VDD1

U4

VDD1

U5

VDD1

U6

VDD1

U10

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

H12

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

K12

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

A11

VDDQ

C12

VDDQ

E8

VDDQ

E12

VDDQ

G12

VDDQ

H8

VDDQ

H9

VDDQ

H11

VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

K11

VDDQ

L12

VDDQ

N8

VDDQ

N12

VDDQ

R12

VDDQ

U11

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

A12

NC

A13

NC

B1

NC

B13

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

U12

NC

U13

NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

P12

VSSQ

N6

VSSQ

M12

VSSQ

M6

VSSQ

L9

VSSQ

K10

VSSQ

H10

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

D12

VSSQ

C6

VSSQ

B12

VSSQ

B6

VSSQ

H9CCNNN8JTMLAR-NTM_FBGA178~D

DQS0#

DQS1#

DQS2#

DQS3#

Vref_DQ

Vref_CA

DQ0

DQ1

DQ2
DQ3

DQ4
DQ5
DQ6

DQ7

DQ8
DQ9

DQ10

DQ11

DQ12

DQ13
DQ14

DQ15

DQ16

DQ17
DQ18
DQ19

DQ20
DQ21
DQ22

DQ23

DQ24
DQ25

DQ26
DQ27

DQ28
DQ29
DQ30

DQ31

CA0

CA1

CA2

CA3

CA4

CA5

CA6

CA7

CA8

CA9

DQS0

DQS1

DQS2

DQS3

DM0

DM1

DM2

DM3

ZQ0

ZQ1

CKE0

CKE1

CS0#
CS1#

CK#

ODT

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS
VSS

VSS
VSS

VSS
VSS
VSS

VSS

12

1U_0402_6.3V6K~D

CD81

CD85

1

2

+1.2V_DDR

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

2

1U_0402_6.3V6K~D

12

DDR_B_D30

P9

DDR_B_D28

N9

DDR_B_D26

N10

DDR_B_D27

N11

DDR_B_D29

M8

DDR_B_D24

M9

DDR_B_D25

M10

DDR_B_D31

M11

DDR_B_D48

F11

DDR_B_D51

F10

DDR_B_D50

F9

DDR_B_D54

F8

DDR_B_D52

E11

DDR_B_D49

E10

DDR_B_D55

E9

DDR_B_D53

D9

DDR_B_D62

T8

DDR_B_D58

T9

DDR_B_D61

T10

DDR_B_D56

T11

DDR_B_D63

R8

DDR_B_D59

R9

DDR_B_D57

R10

DDR_B_D60

R11

DDR_B_D19

C11

DDR_B_D18

C10

DDR_B_D16

C9

DDR_B_D17

C8

DDR_B_D23

B11

DDR_B_D22

B10

DDR_B_D21

B9

DDR_B_D20

B8

DDR_B_CA1_0

R2

DDR_B_CA1_1

P2

DDR_B_CA1_2

N2

DDR_B_CA1_3

N3

DDR_B_CA1_4

M3

DDR_B_CA1_5

F3

DDR_B_CA1_6

E3

DDR_B_CA1_7

E2

DDR_B_CA1_8

D2

DDR_B_CA1_9

C2

DDR_B_DQS3

L10

DDR_B_DQS6

G10

DDR_B_DQS7

P10

DDR_B_DQS2

D10

DDR_B_DQS#3

L11

DDR_B_DQS#6

G11

DDR_B_DQS#7

P11

DDR_B_DQS#2

D11

L8

G8

P8

D8

DDR_B0_ZQ0

B3

DDR_B0_ZQ1

B4

K3

K4

DDR_B_CS#0

L3

DDR_B_CS#1 DDR_B_CS#1

L4

J3

CK

J2

DDR_B_ODT0

J8

J11

H4

B2

B5

C5

E4
E5

F5

H2

J12
K2

L6

M5

N4
N5

R4
R5

T2
T3
T4

T5

RD13 240_0402_1%

1

RD14 240_0402_1%

+VREFDQ_B

+VREFCA

2

1

2

DDR_B_CKE0 6

DDR_B_CKE1 6 DDR_B_CKE3 6

DDR_B_CS#0 6

DDR_B_CS#1 6

DDR_B_CLK0 6
DDR_B_CLK#0 6

DDR_B_ODT0 6

Closed to DRAM Closed to DRAM

+VREFDQ_B +VREFDQ_B+VREFCA

0.047U_0402_10V7K~D

CD19

1

2

0.047U_0402_10V7K~D

CD47

1

2

+1.2V_DDR +1.2V_DD R +1.2V_DDR

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

CD64

1

2

All VREF traces should
have 10 mil trace width

+1.2V_DDR+1.2V_DDR +1.2V_DDR

10U_0603_6.3V6M~D

Closed to UD22

1U_0402_6.3V6K~D

CD25

1

2

CD52

1

2

+1.8VU+1.8VU

1U_0402_6.3V6K~D

CD48

1U_0402_6.3V6K~D

1

2

CD75

1

2

CD55

1

2

1U_0402_6.3V6K~D

CD78

CD53

1

2

0.1U_0402_16V7K~D

1

CD26

2

+1.2V_DDR +1.2V_DDR

1U_0402_6.3V6K~D

CD62

CD8

1

2

UD1

1U_0402_6.3V6K~D

CD34

1

2

+1.2V_DDR

1U_0402_6.3V6K~D

CD68

1

2

A10

U10

H12

K12

+1.2V_DDR

A11

0.1U_0402_16V7K~D

1

CD4

2

1U_0402_6.3V6K~D

CD66

1

2

C12

E12

G12

H11

K11

N12

R12

U11

A12
A13

B13

U12
U13

P12

M12

K10

H10

D12

B12

@

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1
VDD1

U3

VDD1

U4

VDD1

U5

VDD1

U6

VDD1

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

VDDQ

VDDQ

E8

VDDQ

VDDQ

VDDQ

H8

VDDQ

H9

VDDQ
VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

VDDQ

L12

VDDQ

N8

VDDQ

VDDQ

VDDQ

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

NC
NC

B1

NC

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

NC
NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

VSSQ

N6

VSSQ

VSSQ

M6

VSSQ

L9

VSSQ

VSSQ

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

VSSQ

C6

VSSQ

VSSQ

B6

VSSQ

H9CCNNN8JTMLAR-NTM_FBGA178~D

DQS0

DQS1

DQS2

DQS3

DQS0#

DQS1#

DQS2#

DQS3#

Vref_DQ

Vref_CA

DQ0

DQ1

DQ2
DQ3

DQ4
DQ5
DQ6

DQ7

DQ8
DQ9

DQ10

DQ11

DQ12
DQ13

DQ14

DQ15

DQ16
DQ17
DQ18

DQ19

DQ20
DQ21

DQ22
DQ23

DQ24
DQ25
DQ26

DQ27

DQ28

DQ29
DQ30
DQ31

CA0

CA1

CA2

CA3

CA4

CA5

CA6

CA7

CA8

CA9

DM0

DM1

DM2

DM3

ZQ0

ZQ1

CKE0
CKE1

CS0#
CS1#

CK#

ODT

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

DDR_B_D9

P9

DDR_B_D15

N9

DDR_B_D13

N10

DDR_B_D12

N11

DDR_B_D14

M8

DDR_B_D10

M9

DDR_B_D8

M10

DDR_B_D11

M11

DDR_B_D39

F11

DDR_B_D38

F10

DDR_B_D37

F9

DDR_B_D33

F8

DDR_B_D34

E11

DDR_B_D35

E10

DDR_B_D32

E9

DDR_B_D36

D9

DDR_B_D1

T8

DDR_B_D5

T9

DDR_B_D7

T10

DDR_B_D2

T11

DDR_B_D0

R8

DDR_B_D4

R9

DDR_B_D3

R10

DDR_B_D6

R11

DDR_B_D41

C11

DDR_B_D45

C10

DDR_B_D42

C9

DDR_B_D47

C8

DDR_B_D44

B11

DDR_B_D40

B10

DDR_B_D43

B9

DDR_B_D46

B8

DDR_B_CA2_0

R2

DDR_B_CA2_1

P2

DDR_B_CA2_2

N2

DDR_B_CA2_3

N3

DDR_B_CA2_4

M3

DDR_B_CA2_5

F3

DDR_B_CA2_6

E3

DDR_B_CA2_7

E2

DDR_B_CA2_8

D2

DDR_B_CA2_9

C2

DDR_B_DQS1

L10

DDR_B_DQS4

G10

DDR_B_DQS0

P10

DDR_B_DQS5

D10

DDR_B_DQS#1

L11

DDR_B_DQS#4

G11

DDR_B_DQS#0

P11

DDR_B_DQS#5

D11

L8

G8

P8

D8

DDR_B1_ZQ0

B3

DDR_B1_ZQ1

B4

K3
K4

DDR_B_CS#0

L3
L4

J3

CK

J2

DDR_B_ODT0

J8

J11

H4

B2

B5

C5

E4
E5

F5

H2

J12
K2

L6

M5

N4
N5

R4
R5

T2
T3

T4
T5

RD8 240_0402_1%

1 2

RD7 240_0402_1%

1

2

DDR_B_CKE2 6

DDR_B_CLK1 6
DDR_B_CLK#1 6

+VREFDQ_B

+VREFCA

+VREFCA

0.047U_0402_10V7K~D

1

2

0.047U_0402_10V7K~D

CD70

CD72

1

2

Decoupling per DRAM device
VDDQ 4x 0402 1uF 2x 0201 0.1uF 1x 0603 10uF
VDDCA 2x 0402 1uF 1x 0603 10uF
VDD2 3x 0402 1uF 1x 0603 10uF
VDD1 2x 0402 1uF 1x 0603 10uF

A A

intel uesd 0201 for 0.1uF

DELL CONFIDENTIAL/PROPRIETARY

Security Classification

Security Classification

Security Classification

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

P20-DDRIII Channel B

P20-DDRIII Channel B

P20-DDRIII Channel B

LA-D891P

LA-D891P

LA-D891P

1

20 65Tuesday, December 20, 2016

20 65Tuesday, December 20, 2016

20 65Tuesday, December 20, 2016

of

1.0

1.0

1.0