Compal LA-D751P Schematics Rev1.0

A

B

C

D

E

MODEL NAME : BAP10(15")/BAP20(17")
PROJECT CODE : ANRBAP1000/ANRBAP2000
PCB NO :
DAC00004000 LA-D751P M/B(NV)
DAC00005000 LA-D751P M/B(NV_G3)
DA4002AV000 LS-D751P LOGO_15/B
DA80017I000 LS-D752P LOGO_17/B
DA4002B000S LS-D753P PWR_15/B

1 1

DA4002AW000 LS-D754P PWR_17/B
DA80017J000 LS-D755P IO_12L/B
DA4002AY000 LS-D757P TRON_LCD_15/B
DA4002AZ000 LS-D758P TRON_REAR_15/B
DA80017K000 LS-D759P IO_14L/B
DA4002D4000 LS-D75AP TRON_LCD_17/B
DA4002D5000 LS-D75BP TRON_REAR_17/B
DA4002D7000 LS-D75CP TRON_FRONT_15/B
DA4002D8000 LS-D75DP TRON_FRONT_17/B
DA30000W300 LF-D751P Head_15/B
DA30000W400 LF-D752P Head_17/B
DA30000W401 LF-D752P Head_17/B(For LOGO_15/B)
DA30000SY00 LF-D753P TRON_15/B
DA30000WX00 LF-D754P TRON_17/B

ZZZ

PCB@

BAP10/BAP20 Skylake/Kabylake-H 45W

2 2

PCB 1JM LA-D751P REV0 M/B NV 16

DAC00004000

ZZZ

PCBR1@

PCB 1JM LA-D751P REV1 M/B NV 16

DAC00004010

ZZZ

PCBR3@

Skylake/Kabylake PCH with nVidia N17P/N17E

REV : 1.0 (A00)

2016.08.15

@ : Nopop Component

PCB 1JM LA-D751P REV1 MB NV TRIP 16 A31!

DAC00004011

ZZZ

DAZR1@

PCB BAP10 LA-D751P LS-D751P-2P/D754P/D757P-DP 02

DAZ1JM00100

3 3

ZZZ

DAZR3@

PCB BAP10 LA-D751P LS-D751P-2P/D754P/D757P-DP 02 TRI A31 !

DAZ1JM00101

ROYALTY HDMI W/LOGOHDMI@

Part Number Description

HDMI W/Logo:RO0000003HM

RO0000003HM

@EMI@,@ESD@,@RF@ : Total debug Component

EMI@,ESD@,RF@ : EMI/ESD/RF part

CONN@ : Connector Component

Layout Dell logo

COPYRIGHT 2015

ALL RIGHT RESERVED
REV: X00

4 4

PWB: XXXXX
DATE: 1450-06

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cover Page

Cover Page

Cover Page

LA-D751P

LA-D751P

LA-D751P

E

1 82Friday, August 19, 2016

1 82Friday, August 19, 2016

1 82Friday, August 19, 2016

1.0

1.0

1.0

A

B

C

D

E

Block Diagram

eDP panel

1 1

2 2

Support G-SYNC

P . 2 5 P . 2 4

Mini DP
connector

HDMI
connector

P . 5 8

USB3.1
TypeC
connector

USB PD

MUX
PS8331B

P . 2 6

P . 2 7

CIO/USB3. 1

TPS65982

Caldera
connector

eDP 1.3

DP1.3

HDMI2.0

P . 5 8

P . 4 1

nVidia N17P/N17E GPU
N17PG1: 50W
N17EG1: 78W
N17EG2: 115W
6/8pcs GDDR5 256X32
4pcs GDDR5 128X32

Thunderbolt

I2C/USB2

Alpine Ridge-DP

eDP 1.3

P . 5 6 ~ 5 8

PCIe Re-driver
DS80PCI402

P . 4 1

P . 4 6 ~ 5 5

PEG(Gen3)x8
port8~port15

DP 1.2 (DDI 1)

DP 1.2 (DDI 2)
PEG(Gen3)x4

port0~port3

PEG(Gen3)x4

port4~port7

USB3.0 port3

USB2.0 port3

Intel
Skylake/Kabylake-H
BGA CPU
45W 1440 Pins

DMI x 4

P . 7 ~ 1 3

P . 1 6 ~ 2 2

FFS
KXCNL-1010

Memory Bus Dual Channel

1.2V DDR4 (X.M.P)
1866/2133/2400/2666 MHz

USB2.0 port4

USB2.0 port6

P . 3 0

RJ45
connector

3 3

LAN(Gigabit)
Killer E2400/E2500

NGFF (M.2)
WLAN+BT

NGFF (M.2)
SSD1 (2 lanes)

NGFF (M.2)
SSD2 (4 lanes)

NGFF (M.2)
SSD3 (4 lanes)

P . 3 0

P.2

P.2

P.2

P.2

PCI-E port5

PCI-E port6

USB2.0 port5

PCI-E port 13~14
SATA3.0 port 1

PCI-E port 17~20
SATA3.0 port 4

PCI-E port 9~12
SATA3.0 port 0

Intel
Skylake/Kabylake
BGA PCH CM236
837 Pins

USB2.0 port7

USB3.0 port1
USB2.0 port1

USB3.0 port4
USB2.0 port2

USB3.0 port2
USB3.0 port5
USB2.0 port8

USB2.0 port9

P.33 P.42

Fan control
NCT7718W
W83L771AWG- 2

DDR4-SODIMM x2

AlienFX / ELC , C8051F383

Touch screen

Digital camera(with digital MIC)

USB connector 1 , lef t si de

USB power share

USB connector 2 , right side
USB3.0 on D/B

USB connector 3 , right side
USB3.0 TypeC connector

Tobii (17" only)

P.14 15

P.37

P.25

P.35

P.35

P.36

P.34

IO/B

P.32

digital MIC

Headphone/MIC Global headset
combo JACK

Headphone/MIC Retaskable
combo JACK

Speaker

Subwoofer (17" Only) on D/B

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

LA-D751P

LA-D751P

LA-D751P

E

P.31

P.31

P.32

IO/B

2 82Tuesday, August 16, 2016

2 82Tuesday, August 16, 2016

2 82Tuesday, August 16, 2016

1.0

1.0

1.0

P.33

SATA3.0 port 3 ;

P.17

option:HDD

SPI

PS2/SMBu s

Touch pad KC3810

P.43

P.43

KC3810

C

Audio codec

HD Audio

Realtek
ALC326 6

LPC Bus

P.43

ENE KB9022

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Int. KBD +
Marco Key

Compal Secret Data

Compal Secret Data

Compal Secret Data

P.4P.3

Deciphered Date

Deciphered Date

Deciphered Date

D

30 pin connector with cable

2.5” HDD x1

DC in
Bat t er y

4 4

3V/5V

System

1.2V

A

1.00V

2.5V

CPU
Vcore

dGPU
Core

Charger

dGPU

1.35V

SPI ROM
128Mbit

B

P.31

AMP
ALC1309

AMP
ALC1309

A

B

C

D

E

PCB

LS-D75CP TRON_FRONT_15/B
LS-D75DP TRON_FRONT_17/B

Led x 1

1 1

Wire
12 Pin

Wire
12 Pin

LS-D758P TRON_REAR_15/B
LS-D75BP TRON_REAR_17/B

Led x 1

LS-D759P IO_14L/B
LS-D755P IO_12L/B

USB3.0 x 1

Lid Switch

Subwoofer (17" Only)

2.5" HDD

2 2

LS-D753P PWR_15/B
LS-D754P PWR_17/B

on / off SW

Led x 2

Coaxial/Wire
30 Pin

Coaxial/Wire
30 Pin

FFC
6 Pin

30 Pin

JHDD

M/B

LS-D75CP TRON_FRONT_15/B
LS-D75DP TRON_FRONT_17/B

Led x 1

LS-D758P TRON_REAR_15/B
LS-D75BP TRON_REAR_17/B

Led x 1

40 Pin

FFC
16 Pin

Coaxial/Wire
40 pin

TP module

Wire
4 Pin

Coaxial
23 Pin

Led x 6

Touch sensor
6 pin

eDP Panel
30 pin

FPC

Module

Wire

KSI/KSO
30 Pin

Backlight
20 Pin

Wire
16 Pin

KSI/KSO
10 Pin

Backlight
6 Pin

13 Pin

IR Camera
14 pin

3 3

Marco Key

LS-D757P TRON_LCD_15/B
LS-D75AP TRON_LCD_17/B

Led x 1

Keyboard

LS-D757P TRON_LCD_15/B
LS-D75AP TRON_LCD_17/B

Led x 1

Wire
12 Pin

LS-D751P LOGO_15/B
LS-D752P LOGO_17/B

Led x 2

FFC

Wire
12 Pin

6 Pin

LF-D753P TRON_15/B
LF-D754P TRON_17/B

Led x 1

4 4

A

B

FPC

LF-D751P Head_15/B
LF-D752P Head_17/B

Led x 2

Security Cl assification

Security Cl assification

Security Cl assification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Issued Date

Issued Date

FPC

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

C

LF-D753P TRON_15/B
LF-D754P TRON_17/B

Led x 1

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cable Routing Diagram

Cable Routing Diagram

Cable Routing Diagram

LA-D751P

LA-D751P

LA-D751P

E

1.0

1.0

3 82Tuesday, August 16, 2016

3 82Tuesday, August 16, 2016

3 82Tuesday, August 16, 2016

1.0

A

Board ID Table for AD channel

Vcc 3.3V +/- 1%

Board ID

0
1
2
3
4
5
6
7 56K +/- 1%
8
9
10
11
12
13
14
15 330K +/- 1%
16
17
18
19 NC

1 1

Voltage Rails

Power Plane Descript i on

VIN

BATT+
+19VB
+VCC_CORE
+VCC_GT Sliced graphics power rail
+0.6VS_VTT
+1VALW System +1VALW power rail ON*ONON

+1V_PRIM

+VCCIO +1.0VS IO power rail
+VGA_PCIE

+MEM_GFX +1.5VS power rail for GPU

+1VS_VCCST
+1VS_VCCSTG
+3VALW System +3VALW always on power rail
+3VLP
+3VALW_DSW +3VALW power for PCH DSW rails
+3V_LAN +3VALW power for LAN power rails

+3VS
+1.8VS +1.8VS power rail for GPU

+5VALW

+5VS

+3VL_RTC RTC power
+VCC_SA System Agent power rail
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF

100K +/- 1%Ra

Rb V mi n

0 0.000V
12K +/- 1%
15K +/- 1%
20K +/- 1%
27K +/- 1%
33K +/- 1%
43K +/- 1%

75K +/- 1% 1.398V
100K +/- 1%

160K +/- 1%
200K +/- 1%
240K +/- 1%
270K +/- 1%

430K +/- 1%
560K +/- 1%
750K +/- 1%

Adapter power supply
Bat t er y po wer suppl y
AC or bat t er y po wer r ail f or po wer ci rc ui t

Core voltage for CPU

DDR +0.6VS power rail for DDR terminator

System +1VALW power rail ON*

+1.0VS power rail for GPU

DDR-IV +1.2V power rail+1.2V_VDDQ
+1.0V power rail for CPU

+1.0VS power rail for CPU

+19VB to +3VLP power rail for suspend power

System +3VS power rail

+3VS power rail for GPU+3VGS

System +5VALW power rail
System +5VS power rail

AD_B ID

0.347V

0.423V 0.430V

0.541V

0.691V

0.807V

0.978V 0.992V

1.169V

1.634V

1.849V 1.865V

2.015V

2.185V

2.316V

2.395V 2.408V

2.521V

2.667V

2.791V

2.905V 2.912V

V typ

AD_B ID

0.000V 0.300V

0.354V

0.550V

0.702V

0.819V

1.185V

1.414V 1.430V

1.650V

2.031V

2.200V

2.329V

2.533V

2.677V 0xCA - 0xD4

2.800V

3.300V

S0

N/A
N/A
N/A

ON
ON
ON

ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON

V

AD_B ID

0.360V

0.438V

0.559V

0.713V

0.831V

1.006V

1.200V

1.667V

1.881V130K +/- 1%

2.046V

2.215V

2.343V

2.421V

2.544V

2.687V

2.808V

2.919V

3.300V

S3

N/A
N/A
N/A
OFF
OFF
OFF

ON

OFF
OFF
OFF

ON
ON

OFF

ON
ON
ON
ON

OFF
OFF
OFF

ON

OFF

ON

max

S4 / S5

N/A
N/A
N/A
OFF
OFF
OFF

OFF
OFF
OFF
OFF
OFF
OFF

ON*
ON
ON*
ON*

OFF
OFF
OFF

ON*

OFF

ON

OFFOFF

EC AD3

0x00 - 0x13
0x14 - 0x1E
0x1F - 0x25
0x26 - 0x30
0x31 - 0x3A
0x3B - 0x45
0x46 - 0x54
0x55 - 0x64
0x65 - 0x76
0x77 - 0x87
0x88 - 0x96
0x97 - 0xA4
0xA5 - 0xAF
0xB0 - 0xB7
0xB8 - 0xBF
0xC0 - 0xC9

0xD5 - 0xDD
0xDE - 0xF0
0xF1 - 0xFF3.000V

Board ID TABLE

SKL ID

NV

0

1

2

3

4

5

KBL ID

NV

1

6

7

8

9

NVIDIA
Graphic

AMD
Graphic

PCB Revision

EVT
DVT-1
DVT-1.1
DVT-2 / DVT-2.1
GC6

Pilot build

PCB Revision

EVT
DVT-1 / DVT-1.1
GC6
DVT-2

Pilot build

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

PCH-H CM236

Function

JUSB1,type A

JUSBC2,type C

Caldera

JIO,IO/B

JUSBC2,type C

LAN

WLAN

0

JSSD3

1

M.2 2280
SATA
PCIe x4

3

JSSD5/HDD SATA

1

JSSD1
SATA/PCIe x2

0

4

JSSD2

5

M.2 2280
SATA
PCIe x4

*

USB3HSIO PCIe SATA3

1

2

3

4

5

6

7

8

9

10

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

22

21

20

19

23

24

25

26

1

2

3

4

5

6

7

8

9

10

11

12

16

15

14

13

17

18

19

20

* PCIe 13~16 in "Lane Reversal Mode". (HSIO Port 19~22)

Compal Secret Data

Compal Secret Data

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1

2

3

4

5

6

7

8

9

Function

JUSB1(Powershare)1

JIO(IO/B)

Caldera

ELC

Bluetooth

Touch screen

Camera

JUSBC2

Tobii

USB2

10

11

12

13

14

Symbol Note :

Digital Ground

Analog Ground

CPU,C
DDR,D
GPU,DP,HDMI,EDP,V
LAN,L
AUDIO,A
NGFF,N
USB,U
CALDERA,M
HDD,S
ELC,E
FAN,F
TP,T
KBC,K
DC,O

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Notes List

Notes List

Notes List

LA-D751P

LA-D751P

LA-D751P

4 82Monday, August 22, 2016

4 82Monday, August 22, 2016

4 82Monday, August 22, 2016

1.0

1.0

1.0

5

4

3

2

1

SMBUS Address [0x9A]

PCH_SMBCLK

AW44

BB43

AY44

BB39

AW42
AW45

79

80

77

78

PCH_SMBDATA

SML0CLK
SML0 DATA

SML1CLK

EC_SMB_CK2
EC_SMB_DA2

EC_SMB_CK1
EC_SMB_DA1

D D

Kaby Lake

PCH-H

C C

B B

1K

1K

499

499

1K

1K

2.2K

2.2K

2.2K

2.2K

+3V S

+3V_PCH

+3V_PCH

+3V S

+3VALW

N-MO S
N-MO S

51

52

PS8331B

EC_SMB_CK2
EC_SMB_DA2SML1 DATA

SMBUS Address [0x66/67]

0 ohm
0 ohm

SCL
SDA

N-MO S
N-MO S

12

11

PU700
POWER
Charge r

10K

10K

10K

10K

1.8K

1.8K

+3V S

+3V S

+1V8_AON

VGA_SMB_CK2
VGA_SMB_DA2

SMBUS Address [0x12]

253

254

253

254

15

16

4

6

10

9

B5

A5

50

49

BJ8
BH8

DIMMA

DIMMB

JTP

Free Fall Sensor

U2407
Thermal sensor

UT4

TPS65982

UM8
PCIE redriver

UG9
GPU

SMBUS Address [0xA0]

SMBUS Address [0xA4]

SMBUS Address [0x2C]

SMBUS Address [0X1D]

SMBUS Address [0x9A]

SMBUS Address [0x70]

SMBUS Address [0xB2]

SMBUS Address [0x9E]

KBC
KB9022QD

100 ohm
100 ohm

4

PBATT1

5

SMBUS Address [0x16]

17

EC_ESB_CLK

18

EC_ESB_DAT

1K

1K

83

I2C0_SCL_EC

84

I2C0_SDA_EC

A A

0 ohm
0 ohm

I2C0_SCL_AMP_R
I2C0_SDA_AMP_R

0 ohm Subwoo fer
0 ohm

5

4

+3.3 V_1.8V_DV DD

UA4

ALC1309

ALC1309

SMBUS Address [0x20]

SMBUS Address [0x22]

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

UE6

1

KB3810

4

UE10

1

KB3810

4

SMBUS Address [0x00]

SMBUS Address [0x08]

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

SMBus Block Diagram

SMBus Block Diagram

SMBus Block Diagram

LA-D751P

LA-D751P

LA-D751P

1

1.0

1.0

5 82Tuesday, August 16, 2016

5 82Tuesday, August 16, 2016

5 82Tuesday, August 16, 2016

1.0

5

D D

4

3

2

1

JPCMC

+3V_PCH

1 2

+1VALW

RC9 1K_0402_5%CMC@

1 2

RC353 1K_0402_5%CMC@

RC35 51_0402_1%@

RC348 51_0402_1%CMC@

1 2

RH497 51_0402_5%CMC@

12

12

C C

B B

XDP_SPI_SI

XDP_ITP_PMODE

PCH_JTAG_TCK

XDP_TCK

CPU_XDP_TRST#

CFG3<9>

CFG0<9>
CFG1<9>
CFG2<9>

CFG4<9>
CFG5<9>
CFG6<9>
CFG7<9>

CFG17<9>
CFG16<9>

CFG8<9>
CFG9<9>
CFG10<9>
CFG11<9>
CFG12<9>
CFG13<9>
CFG14<9>
CFG15<9>

CFG19<9>
CFG18<9>

OBS DATA

1

DATA_0

3

DATA_1

5

DATA_2

7

DATA_3

9

DATA_4

11

DATA_5

13

DATA_6

15

DATA_7

17

DATA_CLK_1P

21

DATA_CLK_1N

2

DATA_8

4

DATA_9

6

DATA_10

8

DATA_11

10

DATA_12

12

DATA_13

14

DATA_14

16

DATA_15

18

DATA_CLK_2P

20

DATA_CLK_2N

INTEL_CMC_PRIMARY

CONN@

CMC_DEBUG_36P

JTAG/RC/HOOKS

VCCOBS_AB

XDP_TRST*

XDP_TDI

XDP_TMS
XDP_TCK0
XDP_TCK1

XDP_TDO

XDP_PREQ*

XDP_PRDY*

HOOK_0
HOOK_3
HOOK_6

XDP_PRSNT_PCH*
XDP_PRSNT_CPU*

GND

<MT> GND

+1VALW

22

28
29
30

PCH_JTAG_TCK

32

XDP_TCK

31
35

33
34

XDP_HOOK0

27

XDP_SPI_SI

25

XDP_ITP_PMODE

26

XDP_SPI_IO2

24
23

19
36

CPU_XDP_TRST# <9,22>
XDP_TDI <9,18>
XDP_TMS <9,18>
PCH_JTAG_TCK <9,18>
XDP_TCK <18>

XDP_PREQ# <9,22>
XDP_PRDY# <9,22>

1 2

RC355 1K_0402_1%CMC@

XDP_SPI_SI <17>
XDP_ITP_PMODE <18>

1 2

RC354 1K_0402_1%CMC@

XDP_TDO <9>

PCIRST# <28,29,30,43,56>

PCH_SPI_WP#_R <17>

A A

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

CMC Conn

CMC Conn

CMC Conn

LA-D751P

LA-D751P

LA-D751P

1

1.0

1.0

6 82Tuesday, August 16, 2016

6 82Tuesday, August 16, 2016

6 82Tuesday, August 16, 2016

1.0

5

S k y l a k e - H C P U
i 7 K : i 7 - 6 8 2 0 H K
i 7 H : i 7 - 6 7 0 0 H Q
i 5 H : i 5 - 6 3 0 0 H Q

CPU1

S IC CL8066202194730 SR2FL R0 2.7G BGA

SA000097D1L
Si7KR1@

D D

CPU1

S IC CL8066202194635 SR2FQ R0 2.6G FCBGA

SA000095Z1L
Si7HR1@

CPU1

T h u n d e r b o l t R X
< R e v e r s e >

C a l d e r a R X
< R e v e r s e >

S IC CL8066202194632 SR2FP R0 2.3G FCBGA

SA000096Q1L
Si5HR1@

CPU1

S IC CL8066202194730 SR2FL R0 2.7G A31!

SA000097D2L
Si7KR3@

CPU1

C C

S IC CL8066202194635 SR2FQ R0 2.6G A31!

SA000095Z2L
Si7HR3@

CPU1

G P U R X
< R e v e r s e >

PEG_RCOMP

S IC CL8066202194632 SR2FP R0 2.3G A31!

SA000096Q2L
Si5HR3@

K a b y l a k e - H C P U
i 7 K :
i 7 H :
i 5 H :

CPU1

Trace width=12 mils
Spacing=15 mils
Max length= 400 mils

+VCCIO

4

CPU1C

PEG_CRX_TTX_P15<56>
PEG_CRX_TTX_N15<56>

PEG_CRX_TTX_P14<56>
PEG_CRX_TTX_N14<56>

PEG_CRX_TTX_P13<56>
PEG_CRX_TTX_N13<56>

PEG_CRX_TTX_P12<56>
PEG_CRX_TTX_N12<56>

PEG_CRX_GTX_P11<41>
PEG_CRX_GTX_N11<41>

PEG_CRX_GTX_P10<41>
PEG_CRX_GTX_N10<41>

PEG_CRX_GTX_P9<41>
PEG_CRX_GTX_N9<41>

PEG_CRX_GTX_P8<41>
PEG_CRX_GTX_N8<41>

PEG_CRX_GTX_P7<46>
PEG_CRX_GTX_N7<46>

PEG_CRX_GTX_P6<46>
PEG_CRX_GTX_N6<46>

PEG_CRX_GTX_P5<46>
PEG_CRX_GTX_N5<46>

PEG_CRX_GTX_P4<46>
PEG_CRX_GTX_N4<46>

PEG_CRX_GTX_P3<46>
PEG_CRX_GTX_N3<46>

PEG_CRX_GTX_P2<46>
PEG_CRX_GTX_N2<46>

PEG_CRX_GTX_P1<46>
PEG_CRX_GTX_N1<46>

PEG_CRX_GTX_P0<46>
PEG_CRX_GTX_N0<46>

DMI_CRX_PTX_P0<19>
DMI_CRX_PTX_N0<19>

DMI_CRX_PTX_P1<19>
DMI_CRX_PTX_N1<19>

DMI_CRX_PTX_P2<19>
DMI_CRX_PTX_N2<19>

DMI_CRX_PTX_P3<19>
DMI_CRX_PTX_N3<19>

PEG_CRX_TTX_P15
PEG_CRX_TTX_N15

PEG_CRX_TTX_P14
PEG_CRX_TTX_N14

PEG_CRX_TTX_P13
PEG_CRX_TTX_N13

PEG_CRX_TTX_P12
PEG_CRX_TTX_N12

PEG_CRX_GTX_P11
PEG_CRX_GTX_N11

PEG_CRX_GTX_P10
PEG_CRX_GTX_N10

PEG_CRX_GTX_P9
PEG_CRX_GTX_N9

PEG_CRX_GTX_P8
PEG_CRX_GTX_N8

PEG_CRX_GTX_P7
PEG_CRX_GTX_N7

PEG_CRX_GTX_P6
PEG_CRX_GTX_N6

PEG_CRX_GTX_P5
PEG_CRX_GTX_N5

PEG_CRX_GTX_P4
PEG_CRX_GTX_N4

PEG_CRX_GTX_P3
PEG_CRX_GTX_N3

PEG_CRX_GTX_P2
PEG_CRX_GTX_N2

PEG_CRX_GTX_P1
PEG_CRX_GTX_N1

PEG_CRX_GTX_P0
PEG_CRX_GTX_N0 PEG_CTX_GRX_N0

PEG_RCOMP

1 2

RC2

24.9_0402_1%

DMI_CRX_PTX_P0
DMI_CRX_PTX_N0

DMI_CRX_PTX_P1
DMI_CRX_PTX_N1

DMI_CRX_PTX_P2
DMI_CRX_PTX_N2

DMI_CRX_PTX_P3
DMI_CRX_PTX_N3

E25
D25

E24
F24

E23
D23

E22
F22

E21
D21

E20
F20

E19
D19

E18
F18

D17
E17

F16
E16

D15
E15

F14
E14

D13
E13

F12
E12

D11
E11

F10
E10

G2

D8
E8

E6
F6

D5

E5

J8
J9

PEG_RXP[0]
PEG_RXN[0]

PEG_RXP[1]
PEG_RXN[1]

PEG_RXP[2]
PEG_RXN[2]

PEG_RXP[3]
PEG_RXN[3]

PEG_RXP[4]
PEG_RXN[4]

PEG_RXP[5]
PEG_RXN[5]

PEG_RXP[6]
PEG_RXN[6]

PEG_RXP[7]
PEG_RXN[7]

PEG_RXP[8]
PEG_RXN[8]

PEG_RXP[9]
PEG_RXN[9]

PEG_RXP[10]
PEG_RXN[10]

PEG_RXP[11]
PEG_RXN[11]

PEG_RXP[12]
PEG_RXN[12]

PEG_RXP[13]
PEG_RXN[13]

PEG_RXP[14]
PEG_RXN[14]

PEG_RXP[15]
PEG_RXN[15]

PEG_RCOMP

DMI_RXP[0]
DMI_RXN[0]

DMI_RXP[1]
DMI_RXN[1]

DMI_RXP[2]
DMI_RXN[2]

DMI_RXP[3]
DMI_RXN[3]

SKYLAKE _HALO

BGA1440

3 OF 14

3

SKL-H_BGA1440@

PEG_TXP[0]
PEG_TXN[0]

PEG_TXP[1]
PEG_TXN[1]

PEG_TXP[2]
PEG_TXN[2]

PEG_TXP[3]
PEG_TXN[3]

PEG_TXP[4]
PEG_TXN[4]

PEG_TXP[5]
PEG_TXN[5]

PEG_TXP[6]
PEG_TXN[6]

PEG_TXP[7]
PEG_TXN[7]

PEG_TXP[8]
PEG_TXN[8]

PEG_TXP[9]
PEG_TXN[9]

PEG_TXP[10]
PEG_TXN[10]

PEG_TXP[11]
PEG_TXN[11]

PEG_TXP[12]
PEG_TXN[12]

PEG_TXP[13]
PEG_TXN[13]

PEG_TXP[14]
PEG_TXN[14]

PEG_TXP[15]
PEG_TXN[15]

DMI_TXP[0]
DMI_TXN[0]

DMI_TXP[1]
DMI_TXN[1]

DMI_TXP[2]
DMI_TXN[2]

DMI_TXP[3]
DMI_TXN[3]

B25
A25

B24
C24

B23
A23

B22
C22

B21
A21

B20
C20

B19
A19

B18
C18

A17
B17

C16
B16

A15
B15

C14
B14

A13
B13

C12
B12

A11
B11

C10
B10

B8
A8

C6
B6

B5
A5

D4
B4

PEG_CTX_TRX_P15
PEG_CTX_TRX_N15

PEG_CTX_TRX_P14
PEG_CTX_TRX_N14

PEG_CTX_TRX_P13
PEG_CTX_TRX_N13

PEG_CTX_TRX_P12
PEG_CTX_TRX_N12

PEG_CTX_GRX_P11
PEG_CTX_GRX_N11

PEG_CTX_GRX_P10
PEG_CTX_GRX_N10

PEG_CTX_GRX_P9
PEG_CTX_GRX_N9

PEG_CTX_GRX_P8
PEG_CTX_GRX_N8

PEG_CTX_GRX_P7
PEG_CTX_GRX_N7

PEG_CTX_GRX_P6
PEG_CTX_GRX_N6

PEG_CTX_GRX_P5
PEG_CTX_GRX_N5

PEG_CTX_GRX_P4
PEG_CTX_GRX_N4

PEG_CTX_GRX_P3
PEG_CTX_GRX_N3

PEG_CTX_GRX_P2
PEG_CTX_GRX_N2

PEG_CTX_GRX_P1
PEG_CTX_GRX_N1

PEG_CTX_GRX_P0

DMI_CTX_PRX_P0
DMI_CTX_PRX_N0

DMI_CTX_PRX_P1
DMI_CTX_PRX_N1

DMI_CTX_PRX_P2
DMI_CTX_PRX_N2

DMI_CTX_PRX_P3
DMI_CTX_PRX_N3

PEG_CTX_TRX_P15 <56>
PEG_CTX_TRX_N15 <56>

PEG_CTX_TRX_P14 <56>
PEG_CTX_TRX_N14 <56>

PEG_CTX_TRX_P13 <56>
PEG_CTX_TRX_N13 <56>

PEG_CTX_TRX_P12 <56>
PEG_CTX_TRX_N12 <56>

1 2

CC24 0.22U_0201_6.3V

1 2

CC12 0.22U_0201_6.3V

1 2

CC23 0.22U_0201_6.3V

1 2

CC11 0.22U_0201_6.3V

1 2

CC22 0.22U_0201_6.3V

1 2

CC10 0.22U_0201_6.3V

1 2

CC21 0.22U_0201_6.3V

1 2

CC9 0.22U_0201_6.3V

1 2

CC20 0.22U_0201_6.3V

1 2

CC8 0.22U_0201_6.3V

1 2

CC19 0.22U_0201_6.3V

1 2

CC7 0.22U_0201_6.3V

1 2

CC18 0.22U_0201_6.3V

1 2

CC6 0.22U_0201_6.3V

1 2

CC17 0.22U_0201_6.3V

1 2

CC5 0.22U_0201_6.3V

1 2

CC16 0.22U_0201_6.3V

1 2

CC4 0.22U_0201_6.3V

1 2

CC15 0.22U_0201_6.3V

1 2

CC3 0.22U_0201_6.3V

1 2

CC14 0.22U_0201_6.3V

1 2

CC2 0.22U_0201_6.3V

1 2

CC13 0.22U_0201_6.3V

1 2

CC1 0.22U_0201_6.3V

DMI_CTX_PRX_P0 <19>
DMI_CTX_PRX_N0 <19>

DMI_CTX_PRX_P1 <19>
DMI_CTX_PRX_N1 <19>

DMI_CTX_PRX_P2 <19>
DMI_CTX_PRX_N2 <19>

DMI_CTX_PRX_P3 <19>
DMI_CTX_PRX_N3 <19>

2

T h u n d e r b o l t T X
< R e v e r s e >

PEG_CTX_C_GRX_P11

PEG_CTX_C_GRX_N11

PEG_CTX_C_GRX_P10

PEG_CTX_C_GRX_N10

PEG_CTX_C_GRX_P9

PEG_CTX_C_GRX_N9

PEG_CTX_C_GRX_P8

PEG_CTX_C_GRX_N8

PEG_CTX_C_GRX_P7

PEG_CTX_C_GRX_N7

PEG_CTX_C_GRX_P6

PEG_CTX_C_GRX_N6

PEG_CTX_C_GRX_P5

PEG_CTX_C_GRX_N5

PEG_CTX_C_GRX_P4

PEG_CTX_C_GRX_N4

PEG_CTX_C_GRX_P3

PEG_CTX_C_GRX_N3

PEG_CTX_C_GRX_P2

PEG_CTX_C_GRX_N2

PEG_CTX_C_GRX_P1

PEG_CTX_C_GRX_N1

PEG_CTX_C_GRX_P0

PEG_CTX_C_GRX_N0

PEG_CTX_C_GRX_P11 <41>
PEG_CTX_C_GRX_N11 <41>

PEG_CTX_C_GRX_P10 <41>
PEG_CTX_C_GRX_N10 <41>

PEG_CTX_C_GRX_P9 <41>
PEG_CTX_C_GRX_N9 <41>

PEG_CTX_C_GRX_P8 <41>
PEG_CTX_C_GRX_N8 <41>

PEG_CTX_C_GRX_P7 <46>
PEG_CTX_C_GRX_N7 <46>

PEG_CTX_C_GRX_P6 <46>
PEG_CTX_C_GRX_N6 <46>

PEG_CTX_C_GRX_P5 <46>
PEG_CTX_C_GRX_N5 <46>

PEG_CTX_C_GRX_P4 <46>
PEG_CTX_C_GRX_N4 <46>

PEG_CTX_C_GRX_P3 <46>
PEG_CTX_C_GRX_N3 <46>

PEG_CTX_C_GRX_P2 <46>
PEG_CTX_C_GRX_N2 <46>

PEG_CTX_C_GRX_P1 <46>
PEG_CTX_C_GRX_N1 <46>

PEG_CTX_C_GRX_P0 <46>
PEG_CTX_C_GRX_N0 <46>

1

C a l d e r a T X
< R e v e r s e >

G P U T X
< R e v e r s e >

S IC A31 CL8067702869810 QL2X A0 2.7G FCBGA 1440

SA0000A130L
Ki7KES@

CPU1

CPU_DP1_P0<56>

B B

S IC A31 CL8067702869811 QL3X A0 2.4G BGA 1440

SA0000A150L
Ki75ES@

A A

5

CPU_DP1_N0<56>
CPU_DP1_P1<56>
CPU_DP1_N1<56>
CPU_DP1_P2<56>
CPU_DP1_N2<56>
CPU_DP1_P3<56>
CPU_DP1_N3<56>

CPU_DP1_AUXP<56>

CPU_DP1_AUXN<56>

CPU_DP2_P0<56>
CPU_DP2_N0<56>
CPU_DP2_P1<56>
CPU_DP2_N1<56>
CPU_DP2_P2<56>
CPU_DP2_N2<56>
CPU_DP2_P3<56>
CPU_DP2_N3<56>

CPU_DP2_AUXP<56>

CPU_DP2_AUXN<56>

4

CPU_DP1_P0
CPU_DP1_N0
CPU_DP1_P1
CPU_DP1_N1
CPU_DP1_P2
CPU_DP1_N2
CPU_DP1_P3
CPU_DP1_N3

CPU_DP1_AUXP
CPU_DP1_AUXN

CPU_DP2_P0
CPU_DP2_N0
CPU_DP2_P1
CPU_DP2_N1
CPU_DP2_P2
CPU_DP2_N2
CPU_DP2_P3
CPU_DP2_N3

CPU_DP2_AUXP
CPU_DP2_AUXN

K36
K37

J35

J34
H37
H36

J37

J38

D27
E27

H34
H33
F37
G38
F34
F35
E37
E36

F26
E26

C34
D34
B36
B34
F33
E33
C33
B33

A27
B27

CPU1D

DDI1_TXP[0]
DDI1_TXN[0]
DDI1_TXP[1]
DDI1_TXN[1]
DDI1_TXP[2]
DDI1_TXN[2]
DDI1_TXP[3]
DDI1_TXN[3]

DDI1_AUXP
DDI1_AUXN

DDI2_TXP[0]
DDI2_TXN[0]
DDI2_TXP[1]
DDI2_TXN[1]
DDI2_TXP[2]
DDI2_TXN[2]
DDI2_TXP[3]
DDI2_TXN[3]

DDI2_AUXP
DDI2_AUXN

DDI3_TXP[0]
DDI3_TXN[0]
DDI3_TXP[1]
DDI3_TXN[1]
DDI3_TXP[2]
DDI3_TXN[2]
DDI3_TXP[3]
DDI3_TXN[3]

DDI3_AUXP
DDI3_AUXN

SKYLAKE _HALO

BGA1440

4 OF 14

EDP_TXP[0]
EDP_TXN[0]
EDP_TXP[1]
EDP_TXN[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXP
EDP_AUXN

EDP_DISP_UTIL

EDP_RCOMP

D29

CPU_EDP_TX0N

E29

CPU_EDP_TX1P

F28

CPU_EDP_TX1N

E28

CPU_EDP_TX2N

B29

CPU_EDP_TX2P

A29

CPU_EDP_TX3N

B28

CPU_EDP_TX3P

C28

CPU_EDP_AUX

C26

CPU_EDP_AUX#

B26

A33

T1 PAD~D TP@

EDP_RCOMP

D37

1 2

RC30

24.9_0402_1%

CPU_EDP_TX0P <24>
CPU_EDP_TX0N <24>
CPU_EDP_TX1P <24>
CPU_EDP_TX1N <24>
CPU_EDP_TX2N <24>
CPU_EDP_TX2P <24>
CPU_EDP_TX3N <24>
CPU_EDP_TX3P <24>

CPU_EDP_AUX <24>
CPU_EDP_AUX# <24>

+VCCIO

EDP_RCOMP
Trace width=20 mils

CPU_EDP_TX0P

Spacing=25 mils
Max length=100 mils

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

3

G27
G25

CPU_DISPA_SDI_R

G29

SKL-H_BGA1440@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

RC66
20_0402_5%

Compal Secret Data

Compal Secret Data

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

CPU_DISPA_BCLK <18>
CPU_DISPA_SDO <18>
CPU_DISPA_SDI <18>

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

CPU(1/7) DMI,PEG,DDI,EDP

CPU(1/7) DMI,PEG,DDI,EDP

CPU(1/7) DMI,PEG,DDI,EDP

Document Number Re v

Document Number Re v

Document Number Re v

LA-D751P

LA-D751P

LA-D751P

1

7 82Wednesday, August 24, 2016

7 82Wednesday, August 24, 2016

7 82Wednesday, August 24, 2016

1.0

1.0

1.0

5

D D

4

3

2

1

Interleave

DDR_A_D0
DDR_A_D1

DDR_A_D[0..63]<14>
DDR_A_MA[0..13]<14>
DDR_A_DQS#[0..7]<14>
DDR_A_DQS[0..7]<14>

DDR_B_D[0..63]<15>
DDR_B_MA[0..13]<15>
DDR_B_DQS#[0..7]<15>
DDR_B_DQS[0..7]<15>

C C

B B

DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

CPU1A

BR6

DDR0_DQ[0]

BT6

DDR0_DQ[1]

BP3

DDR0_DQ[2]

BR3

DDR0_DQ[3]

BN5

DDR0_DQ[4]

BP6

DDR0_DQ[5]

BP2

DDR0_DQ[6]

BN3

DDR0_DQ[7]

BL4

DDR0_DQ[8]

BL5

DDR0_DQ[9]

BL2

DDR0_DQ[10]

BM1

DDR0_DQ[11]

BK4

DDR0_DQ[12]

BK5

DDR0_DQ[13]

BK1

DDR0_DQ[14]

BK2

DDR0_DQ[15]

BG4

DDR0_DQ[16]/DDR0_DQ[32]

BG5

DDR0_DQ[17]/DDR0_DQ[33]

BF4

DDR0_DQ[18]/DDR0_DQ[34]

BF5

DDR0_DQ[19]/DDR0_DQ[35]

BG2

DDR0_DQ[20]/DDR0_DQ[36]

BG1

DDR0_DQ[21]/DDR0_DQ[37]

BF1

DDR0_DQ[22]/DDR0_DQ[38]

BF2

DDR0_DQ[23]/DDR0_DQ[39]

BD2

DDR0_DQ[24]/DDR0_DQ[40]

BD1

DDR0_DQ[25]/DDR0_DQ[41]

BC4

DDR0_DQ[26]/DDR0_DQ[42]

BC5

DDR0_DQ[27]/DDR0_DQ[43]

BD5

DDR0_DQ[28]/DDR0_DQ[44]

BD4

DDR0_DQ[29]/DDR0_DQ[45]

BC1

DDR0_DQ[30]/DDR0_DQ[46]

BC2

DDR0_DQ[31]/DDR0_DQ[47]

AB1

DDR0_DQ[32]/DDR1_DQ[0]

AB2

DDR0_DQ[33]/DDR1_DQ[1]

AA4

DDR0_DQ[34]/DDR1_DQ[2]

AA5

DDR0_DQ[35]/DDR1_DQ[3]

AB5

DDR0_DQ[36]/DDR1_DQ[4]

AB4

DDR0_DQ[37]/DDR1_DQ[5]

AA2

DDR0_DQ[38]/DDR1_DQ[6]

AA1

DDR0_DQ[39]/DDR1_DQ[7]

V5

DDR0_DQ[40]/DDR1_DQ[8]

V2

DDR0_DQ[41]/DDR1_DQ[9]

U1

DDR0_DQ[42]/DDR1_DQ[10]

U2

DDR0_DQ[43]/DDR1_DQ[11]

V1

DDR0_DQ[44]/DDR1_DQ[12]

V4

DDR0_DQ[45]/DDR1_DQ[13]

U5

DDR0_DQ[46]/DDR1_DQ[14]

U4

DDR0_DQ[47]/DDR1_DQ[15]

R2

DDR0_DQ[48]/DDR1_DQ[32]

P5

DDR0_DQ[49]/DDR1_DQ[33]

R4

DDR0_DQ[50]/DDR1_DQ[34]

P4

DDR0_DQ[51]/DDR1_DQ[35]

R5

DDR0_DQ[52]/DDR1_DQ[36]

P2

DDR0_DQ[53]/DDR1_DQ[37]

R1

DDR0_DQ[54]/DDR1_DQ[38]

P1

DDR0_DQ[55]/DDR1_DQ[39]

M4

DDR0_DQ[56]/DDR1_DQ[40]

M1

DDR0_DQ[57]/DDR1_DQ[41]

L4

DDR0_DQ[58]/DDR1_DQ[42]

L2

DDR0_DQ[59]/DDR1_DQ[43]

M5

DDR0_DQ[60]/DDR1_DQ[44]

M2

DDR0_DQ[61]/DDR1_DQ[45]

L5

DDR0_DQ[62]/DDR1_DQ[46]

L1

DDR0_DQ[63]/DDR1_DQ[47]

BA2

DDR0_ECC[0]

BA1

DDR0_ECC[1]

AY4

DDR0_ECC[2]

AY5

DDR0_ECC[3]

BA5

DDR0_ECC[4]

BA4

DDR0_ECC[5]

AY1

DDR0_ECC[6]

AY2

DDR0_ECC[7]

DDR CHANNEL A

SKYLAKE _HALO

BGA1440

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSN[7]/DDR1_DQSN[5]

1 OF 14

DDR0_CKP[0]
DDR0_CKN[0]
DDR0_CKN[1]

DDR0_CKP[1]
DDR0_CLKP[2]
DDR0_CLKN[2]
DDR0_CLKP[3]
DDR0_CLKN[3]

DDR0_CKE[0]

DDR0_CKE[1]

DDR0_CKE[2]

DDR0_CKE[3]

DDR0_CS#[0]
DDR0_CS#[1]
DDR0_CS#[2]
DDR0_CS#[3]

DDR0_ODT[0]

DDR0_ODT[1]

DDR0_ODT[2]

DDR0_ODT[3]

DDR0_MA[3]
DDR0_MA[4]

DDR0_PAR

DDR0_ALERT#

DDR0_DQSN[0]
DDR0_DQSN[1]

DDR0_DQSP[0]
DDR0_DQSP[1]

DDR0_DQSP[8]
DDR0_DQSN[8]

SKL-H_BGA1440@

AG1
AG2
AK1
AK2
AL3
AK3
AL2
AL1

AT1
AT2
AT3
AT5

AD5
AE2
AD2
AE5

AD3
AE4
AE1
AD4

AH5
AH1
AU1

AH4
AG4
AD1

AH3
AP4
AN4
AP5
AP2
AP1
AP3
AN1
AN3
AT4
AH2
AN2
AU4
AE3
AU2
AU3

AG3
AU5

BR5
BL3
BG3
BD3
AB3
V3
R3
M3

BP5
BK3
BF3
BC3
AA3
U3
P3
L3

AY3
BA3

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

M_CLK_DDR0 <14>
M_CLK_DDR#0 <14>
M_CLK_DDR#1 <14>
M_CLK_DDR1 <14>

DDR_CKE0_DIMMA <14>
DDR_CKE1_DIMMA <14>

DDR_CS0_DIMMA# <14>
DDR_CS1_DIMMA# <14>

M_ODT0 <14>
M_ODT1 <14>

DDR_A_BS0 <14>
DDR_A_BS1 <14>
DDR_A_BG0 <14>

DDR_A_RAS# <14>
DDR_A_WE# <14>
DDR_A_CAS# <14>

DDR_A_BG1 <14>
DDR_A_ACT# <14>

DDR_A_PAR <14>
DDR_A_ALERT# <14>

1 2

RH148 121_0402_1%

1 2

RH149 75_0402_1%

1 2

RH150 100_0402_1%

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_RCOMP0
DDR_RCOMP1
DDR_RCOMP2

CPU1B

BT11

DDR1_DQ[0]/DDR0_DQ[16]

BR11

DDR1_DQ[1]/DDR0_DQ[17]

BT8

DDR1_DQ[2]/DDR0_DQ[18]

BR8

DDR1_DQ[3]/DDR0_DQ[19]

BP11

DDR1_DQ[4]/DDR0_DQ[20]

BN11

DDR1_DQ[5]/DDR0_DQ[21]

BP8

DDR1_DQ[6]/DDR0_DQ[22]

BN8

DDR1_DQ[7]/DDR0_DQ[23]

BL12

DDR1_DQ[8]/DDR0_DQ[24]

BL11

DDR1_DQ[9]/DDR0_DQ[25]

BL8

DDR1_DQ[10]/DDR0_DQ[26]

BJ8

DDR1_DQ[11]/DDR0_DQ[27]

BJ11

DDR1_DQ[12]/DDR0_DQ[28]

BJ10

DDR1_DQ[13]/DDR0_DQ[29]

BL7

DDR1_DQ[14]/DDR0_DQ[30]

BJ7

DDR1_DQ[15]/DDR0_DQ[31]

BG11

DDR1_DQ[16]/DDR0_DQ[48]

BG10

DDR1_DQ[17]/DDR0_DQ[49]

BG8

DDR1_DQ[18]/DDR0_DQ[50]

BF8

DDR1_DQ[19]/DDR0_DQ[51]

BF11

DDR1_DQ[20]/DDR0_DQ[52]

BF10

DDR1_DQ[21]/DDR0_DQ[53]

BG7

DDR1_DQ[22]/DDR0_DQ[54]

BF7

DDR1_DQ[23]/DDR0_DQ[55]

BB11

DDR1_DQ[24]/DDR0_DQ[56]

BC11

DDR1_DQ[25]/DDR0_DQ[57]

BB8

DDR1_DQ[26]/DDR0_DQ[58]

BC8

DDR1_DQ[27]/DDR0_DQ[59]

BC10

DDR1_DQ[28]/DDR0_DQ[60]

BB10

DDR1_DQ[29]/DDR0_DQ[61]

BC7

DDR1_DQ[30]/DDR0_DQ[62]

BB7

DDR1_DQ[31]/DDR0_DQ[63]

AA11

DDR1_DQ[32]/DDR1_DQ[16]

AA10

DDR1_DQ[33]/DDR1_DQ[17]

AC11

DDR1_DQ[34]/DDR1_DQ[18]

AC10

DDR1_DQ[35]/DDR1_DQ[19]

AA7

DDR1_DQ[36]/DDR1_DQ[20]

AA8

DDR1_DQ[37]/DDR1_DQ[21]

AC8

DDR1_DQ[38]/DDR1_DQ[22]

AC7

DDR1_DQ[39]/DDR1_DQ[23]

W8

DDR1_DQ[40]/DDR1_DQ[24]

W7

DDR1_DQ[41]/DDR1_DQ[25]

V10

DDR1_DQ[42]/DDR1_DQ[26]

V11

DDR1_DQ[43]/DDR1_DQ[27]

W11

DDR1_DQ[44]/DDR1_DQ[28]

W10

DDR1_DQ[45]/DDR1_DQ[29]

V7

DDR1_DQ[46]/DDR1_DQ[30]

V8

DDR1_DQ[47]/DDR1_DQ[31]

R11

DDR1_DQ[48]

P11

DDR1_DQ[49]

P7

DDR1_DQ[50]

R8

DDR1_DQ[51]

R10

DDR1_DQ[52]

P10

DDR1_DQ[53]

R7

DDR1_DQ[54]

P8

DDR1_DQ[55]

L11

DDR1_DQ[56]

M11

DDR1_DQ[57]

L7

DDR1_DQ[58]

M8

DDR1_DQ[59]

L10

DDR1_DQ[60]

M10

DDR1_DQ[61]

M7

DDR1_DQ[62]

L8

DDR1_DQ[63]

AW11

DDR1_ECC[0]

AY11

DDR1_ECC[1]

AY8

DDR1_ECC[2]

AW8

DDR1_ECC[3]

AY10

DDR1_ECC[4]

AW10

DDR1_ECC[5]

AY7

DDR1_ECC[6]

AW7

DDR1_ECC[7]

G1

DDR_RCOMP[0]

H1

DDR_RCOMP[1]

J2

DDR_RCOMP[2]

DDR CHANNEL B

SKYLAKE _HALO

BGA1440

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSP[5]/DDR1_DQSP[3]

2 OF 14

DDR1_CKP[0]
DDR1_CKN[0]
DDR1_CKN[1]

DDR1_CKP[1]
DDR1_CLKP[2]
DDR1_CLKN[2]
DDR1_CLKP[3]
DDR1_CLKN[3]

DDR1_CKE[0]

DDR1_CKE[1]

DDR1_CKE[2]

DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1]
DDR1_CS#[2]
DDR1_CS#[3]

DDR1_ODT[0]

DDR1_ODT[1]

DDR1_ODT[2]

DDR1_ODT[3]

DDR1_MA[3]
DDR1_MA[4]

DDR1_PAR

DDR1_ALERT#

DDR1_DQSN[6]
DDR1_DQSN[7]

DDR1_DQSP[6]
DDR1_DQSP[7]

DDR1_DQSP[8]
DDR1_DQSN[8]

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

SKL-H_BGA1440@

AM9
AN9
AM8
AM7
AM11
AM10
AJ10
AJ11

AT8
AT10
AT7
AT11

AF11
AE7
AF10
AE10

AF7
AE8
AE9
AE11

AH10
AH11
AF8

AH8
AH9
AR9

AJ9
AK6
AK5
AL5
AL6
AM6
AN7
AN10
AN8
AR11
AH7
AN11
AR10
AF9
AR7
AT9

AJ7
AR8

BP9
BL9
BG9
BC9
AC9
W9
R9
M9

BR9
BJ9
BF9
BB9
AA9
V9
P9
L9

AW9
AY9

BN13
BP13
BR13

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

M_CLK_DDR2 <15>
M_CLK_DDR#2 <15>
M_CLK_DDR#3 <15>
M_CLK_DDR3 <15>

DDR_CKE2_DIMMB <15>
DDR_CKE3_DIMMB <15>

DDR_CS2_DIMMB# <15>
DDR_CS3_DIMMB# <15>

M_ODT2 <15>
M_ODT3 <15>

DDR_B_RAS# <15>
DDR_B_WE# <15>
DDR_B_CAS# <15>

DDR_B_BS0 <15>
DDR_B_BS1 <15>
DDR_B_BG0 <15>

DDR_B_BG1 <15>
DDR_B_ACT# <15>

DDR_B_PAR <15>
DDR_B_ALERT# <15>

+V_DDR_REFA_R

+V_DDR_REFB_R

DDR_RCOMP0 :
DDR_RCOMP1 :
DDR_RCOMP2 :
Trace width=12~15 mils

A A

Spacing=20 mils
Max length= 500 mils

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

CPU(2/7) DDR4

CPU(2/7) DDR4

CPU(2/7) DDR4

Document Number Re v

Document Number Re v

Document Number Re v

LA-D751P

LA-D751P

LA-D751P

1

8 82Tuesday, August 16, 2016

8 82Tuesday, August 16, 2016

8 82Tuesday, August 16, 2016

1.0

1.0

1.0

5

+VCCST

4

3

2

1

1 2

RH163 1K_0402_5%

1 2

RH156 51_0402_5%@

1 2

D D

RH164 1K_0402_5%

1 2

RH151 100_0402_1%

1 2

RH152 56.2_0402_1%

+VCCSTG

1 2

RH165 1K_0402_5%

PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS

CFG2

C C

1: Normal Operation; Lane # definition matches
socket pin map definition

0:Lane Reversed

*

1 2

CFG2

RH184 1K_0402_5%

H_THERMTRIP#

XDP_PREQ#

H_VCCST_PWRGD

VR_SVID_DATA

VR_SVID_ALERT#

H_PROCHOT#

BH31
BH32
BH29
BR30

BT13

BT31
BP35
BM34
BP31
BT34

BR33

BM30

B31
A32

D35
C36

E31
D31

H13

J31

BN1

PCH_CPU_BCLK_P<17>
PCH_CPU_BCLK_N<17>

PCH_CPU_PCIBCLK_P<17>
PCH_CPU_PCIBCLK_N<17>

CPU_24MHZ_P<17>
CPU_24MHZ_N<17>

VR_SVID_ALERT#<75>
VR_SVID_CLK<75>
VR_SVID_DATA<75>
H_PROCHOT#<43>

H_VCCST_PWRGD<43>

H_CPUPWRGD<18>
PLTRST_CPU#<16>
H_PM_SYNC_R<16>

H_PM_DOWN<16>

H_PECI<16,43>

H_THERMTRIP#<16>

PROC_DETECT#< 16>

VR_SVID_ALERT#

VR_SVID_DATA
H_PROCHOT#

H_VCCST_PWRGD

H_THERMTRIP#

1 2

RH153 220_0402_5%

1 2

RH158 499_0402_1%

1 2

RH154 60.4_0402_1%

1 2

RH155 20_0402_5%

1 2

RH519 0_0402_5%@

DDR_VTT_PG_CTRL

Display Port Presence Strap

CFG4

PCIE Port Bifurcation Straps

CFG[6:5]

B B

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

*

1 2

CFG4

RH185 1K_0402_5%

11: (Default) x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled

01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

*

1 2

CFG5

RH186 1K_0402_5%

1 2

CFG6

RH187 1K_0402_5%

+1.2V_DDR

1

@

CH197

0.1U_0402_10V7K

2

+3VS

12

RH525
330K_0402_5%

SM_PG_CTRL<64>

1 2

PCH_SPI_SI_R<17>

RH489 1K_0402_5%

RH489,RH493 close to UH4

+3V_PCH

RH493 2.2K_0402_5%

1 2

UC1

5

VCC

4

Y

74AUP1G07GW_TSSOP5

PCH_SYS_PWROK_XDP

PCH_SYS_PWROK_XDP

1

NC

DDR_VTT_PG_CTRL

2

A

3

GND

H_VCCST_PWRGD H_CPUPWRGD PLTRST_C PU#

1

CH193

0.1U_0402_16V7K~D

ESD@

2

PEG DEFER TRAINING

CFG7

1: (Default) PEG Train immediately following xxRESETB
de assertion

*

0: PEG Wait for BIOS for training

1 2

CFG7

@

RH188 1K_0402_5%

+VCCSTG

1 2

RH494 51_0402_5%CMC@

1 2

RH495 51_0402_5%CMC@

1 2

RH496 51_0402_5%@

XDP_TMS

XDP_TDI

XDP_TDO

CPU1E

BCLKP
BCLKN

PCI_BCLKP
PCI_BCLKN

CLK24P
CLK24N

VIDALERT#
VIDSCK
VIDSOUT
PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD

PROCPWRGD
RESET#
PM_SYNC
PM_DOWN
PECI
THERMTRIP#

SKTOCC#
PROC_SELECT#

CATERR#

SKYLAKE _HALO

BGA1440

5 OF 14

1

CH194

0.1U_0402_16V7K~D

ESD@

2

+3VALW

12

12

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]

CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[17]
CFG[16]
CFG[19]
CFG[18]

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]

PROC_TDO

PROC_TDI
PROC_TMS
PROC_TCK

PROC_TRST#
PROC_PREQ#
PROC_PRDY#

CFG_RCOMP

SKL-H_BGA1440@

RH2
10K_0402_5%

CH174

0.1U_0402_10V

BN25
BN27
BN26
BN28
BR20
BM20
BT20
BP20
BR23
BR22
BT23
BT22
BM19
BR19
BP19
BT19

BN23
BP23
BP22
BN22

BR27
BT27
BM31
BT30

BT28
BL32
BP28
BR28

BP30
BL30
BP27

BT25

CFG2

CFG4
CFG5
CFG6
CFG7

XDP_BPM#0
XDP_BPM#1

XDP_TDO
XDP_TDI
XDP_TMS
PCH_JTAG_TCK

CPU_XDP_TRST#
XDP_PREQ#
XDP_PRDY#

CFG_RCOMP

1

CH195

0.1U_0402_16V7K~D

ESD@

2

PBTN_OUT# <18,43> SYS_RESET# <18>

CFG0 <6>
CFG1 <6>
CFG2 <6>
CFG3 <6>
CFG4 <6>
CFG5 <6>
CFG6 <6>
CFG7 <6>
CFG8 <6>
CFG9 <6>
CFG10 <6>
CFG11 <6>
CFG12 <6>
CFG13 <6>
CFG14 <6>
CFG15 <6>

CFG17 <6>
CFG16 <6>
CFG19 <6>
CFG18 <6>

T112 PAD~D @
T113 PAD~D @

12

RH59

49.9_0402_1%

+3VS

12

RH5
1K_0402_5%

0.1U_0402_10V

CH175

12

XDP_TDO <6,18>
XDP_TDI <6,18>
XDP_TMS <6,18>
PCH_JTAG_TCK <6, 18>

CPU_XDP_TRST# <6,22>
XDP_PREQ# <6,22>
XDP_PRDY# <6,22>

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

CPU(3/7) CFG,XDP

CPU(3/7) CFG,XDP

CPU(3/7) CFG,XDP

Document Number Re v

Document Number Re v

Document Number Re v

LA-D751P

LA-D751P

LA-D751P

1

9 82Tuesday, August 16, 2016

9 82Tuesday, August 16, 2016

9 82Tuesday, August 16, 2016

1.0

1.0

1.0

5

D D

+VCC_CORE+VCC_CORE

SKYLAKE_HALO

CPU1G

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

BGA1440

7 OF 14

SKL-H_BGA1440@

AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37

AB38
AC13
AC14
AC29

C C

B B

AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38

AE13

AE14

AE30

AE31

AE32

AE35

AE36

AE37

AE38

AF35

AF36

AF37

AF38

K13
K14
L13
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC_SENSE
VSS_SENSE

V32
V33
V34
V35
V36
V37
V38
W13
W14
W29
W30
W31
W32
W35
W36
W37
W38
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
L14
P29
P30
P31
P32
P33
P34
P35
P36
R13
R31
R32
R33
R34
R35
R36
R37
R38
T29
T30
T31
T32
T35
T36
T37
T38
U29
U30
U31
U32
U33
U34
U35
U36
V13
V14
V31
P14

AG37
AG38

+VCC_CORE

12

RH197
100_0402_1%

12

RH466
100_0402_1%

4

D1
E1

BN35

BN33

BL34

AE29
AA14

BR35
BR31
BH30

E3
E2

BR1

BT2

J24

H24

N29
R14

A36
A37

H23

J23

F30
E30

B30
C30

G3
J3

T41PAD~D@

T43PAD~D@
T44PAD~D@

1 2

PCH_TRIGGER<22>

CPU_TRIGGER<22>

RH167 30_0402_5%

1 2

RH192 30_0402_5%

VCCSENSE <75>
VSSSENSE <75>

CPU1K

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD

PROC_TRIGIN
PROC_TRIGOUT

RSVD
RSVD

RSVD
RSVD

RSVD
RSVD

RSVD
RSVD
RSVD

3

SKYLAKE_HALO

BGA1440

11 OF 14

SKL-H_BGA1440@

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD
RSVD

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD
RSVD

RSVD
RSVD

RSVD_TP
RSVD_TP

RSVD
RSVD
RSVD

NCTF
NCTF
NCTF
NCTF
NCTF
NCTF

BM33
BL33

BJ14
BJ13

BK28
BJ28

BJ18

VSS

BJ16
BK16

BK24
BJ24

BK21
BJ21

BT17
BR17

BK18

VSS

BJ34
BJ33

G13
AJ8
BL31

B2
B38
BP1
BR2
C1
C38

2

T66 PAD~D @
T67 PAD~D @

T68 PAD~D @
T69 PAD~D @

T73 PAD~D @
T74 PAD~D @

T75 PAD~D @
T76 PAD~D @

T81 PAD~D @
T82 PAD~D @

T85 PAD~D @

T88 PAD~D @
T89 PAD~D @

RH166 49.9_0402_1%@

1 2
1 2

RH57 49.9_0402_1%@

1 2

RH58 49.9_0402_1%@

BJ17
BJ19
BJ20
BK17
BK19
BK20
BL16
BL17
BL18
BL19
BL20

BL21
BM17
BN17

BJ23

BJ26

BJ27

BK23

BK26

BK27

BL23

BL24

BL25

BL26

BL27

BL28
BM24

BL15
BM16

BL22
BM22

BP15
BR15

BT15

BP16
BR16

BT16

BN15
BM15

BP17
BN16

BM14

BL14

BJ35

BJ36

AT13
AW13

AU13

AY13

BT29
BR25

BP25

SKYLAKE_HALO

CPU1J

VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VCCOPC_SENSE
VSSOPC_SENSE

RSVD
RSVD

VCCEOPIO
VCCEOPIO
VCCEOPIO

RSVD
RSVD
RSVD

VCCEOPIO_SENSE
VSSEOPIO_SENSE

RSVD
RSVD

VCC_OPC_1P8
VCC_OPC_1P8

RSVD
RSVD

ZVM#
MSM#

ZVM2#
MSM2#

OPC_RCOMP
OPCE_RCOMP
OPCE_RCOMP2

BGA1440

1

10 OF 14

SKL-H_BGA1440@

A A

Security Classifi cation

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF C OMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF C OMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF C OMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

CPU(4/7) +VCC_CORE,RSVD

CPU(4/7) +VCC_CORE,RSVD

CPU(4/7) +VCC_CORE,RSVD

LA-D751P

LA-D751P

LA-D751P

10 82Tuesday, August 16, 2016

10 82Tuesday, August 16, 2016

10 82Tuesday, August 16, 2016

1

1.0

1.0

1.0

5

4

3

2

1

+VCCSTG

10U_0603_6.3V6M~D

D D

+VCCSA

SKYLAKE_H ALO

CPU1I

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

BGA1440

9 OF 14

VCCPLL_OC
VCCPLL_OC

VCCSA_SENSE
VSSSA_SENSE

VCCIO_SENSE
VSSIO_SENSE

SKL-H_BGA1440@

J30
K29
K30
K31
K32
K33
K34
K35
L31
L32
L35
L36
L37
L38
M29
M30
M31
M32
M33
M34

AG12

M35
M36

G15
G17
G19
G21
H15
H16
H17
H19
H20
H21
H26
H27

J15

J16

J17

J19

J20

J21

J26

J27

C C

B B

+VCCIO

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDQC

VCCST

VCCSTG

VCCSTG

VCCPLL
VCCPLL

+1.2V_DDR

AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6

Y12

BH13
G11

H30

H29

G30

H28
J28

M38
M37

H14
J14

+1.2V_DDR

1 2

RH530 0_0402_5%@

+VCCST

+VCCSTG

+VCCST

VCCIO_SENSE <79>
VSSIO_SENSE <79>

VCCPLL_OC is allowed to be turned of f
during S3 and DS3 if it is not powered directly from VDDQ

+1.2V_DDR+1.2V_VCCPLL_OC

+VCCSA

RH201
100_0402_1%

1 2

VCCSA_SENSE <75>

12

RH469
100_0402_1%

VSSSA_SENSE <75>

10U_0603_6.3V6M~D

CH102

1

2

10U_0603_6.3V6M~D

CH103

CH104

1

1

2

2

1U_0402_6.3V6K~D

CH105

1

1

2

2

1U_0402_6.3V6K~D

CH106

+1.2V_DDR

1

2

+VCCST+VCCIO

1U_0402_6.3V6K~D

1

2

22U_0805_6.3V6M~D

CH129

+1.2V_DDR

1U_0402_6.3V6K~D

CH107

CH108

1

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

1

CH130

CH131

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

CH118

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CH110

CH109

1

1

2

2

22U_0805_6.3V6M~D

1

CH132

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

22U_0603_6.3V6M

22U_0603_6.3V6M

CH120

CH124

CH121

1

2

CH119

1

2

1

1

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CH122

CH125

CH123

1

1

1

2

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CH126

CH128

CH127

1

1

2

2

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

CPU(5/7) +VCCSA,+VCCIO

CPU(5/7) +VCCSA,+VCCIO

CPU(5/7) +VCCSA,+VCCIO

LA-D751P

LA-D751P

LA-D751P

1

11 82Tuesday, August 16, 2016

11 82Tuesday, August 16, 2016

11 82Tuesday, August 16, 2016

1.0

1.0

1.0

5

4

3

2

1

+VCCGT

D D

C C

B B

BG34
BG35
BG36
BH33
BH34
BH35
BH36
BH37
BH38

BJ37

BJ38
BL36
BL37
BM36
BM37
BN36
BN37
BN38
BP37
BP38
BR37
BT37
BE38
BF13
BF14
BF29
BF30
BF31
BF32
BF35
BF36
BF37
BF38
BG29
BG30
BG31
BG32
BG33
BC36
BC37
BC38
BD13
BD14
BD29
BD30
BD31
BD32
BD33
BD34
BD35
BD36
BE31
BE32
BE37

CPU1H

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

SKYLAKE_H ALO

BGA1440

8 OF 14

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

SKL-H_BGA1440@

AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BE33
BE34
BE35
BE36

+VCCGT

+VCCGT

AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AL13
AL29
AL30
AL31
AL32
AL35
AL36
AL37

AL38
AM13
AM14
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36

AN13

AN14

AN31

AN32

AN33

AN34

AN35

AN36

AN37

AN38

AP13

AP14

AP29

AP30

AP31

AP32

AP35

AP36

AP37

AP38

AR29

AR30

AR31

AR32

AR33

AR34

AR35

AR36

AT14

AT31

AT32

AT33

AT34

AT35

AT36

AT37

AT38

AU14

AU29

AU30

AU31

AU32

AU35

AU36

AU37

AU38

CPU1N

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

SKYLAKE_H ALO

BGA1440

14 OF 14

VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX

VCCGT_SENSE

VSSGTX_SENSE

VSSGT_SENSE

VCCGTX_SENSE

SKL-H_BGA1440@

AF29
AF30
AF31
AF32
AF33
AF34
AG13
AG14
AG31
AG32
AG33
AG34
AG35
AG36
AH13
AH14
AH29
AH30
AH31
AH32
AJ13
AJ14

AH38
AH35
AH37
AH36

+VCCGT

12

12

RH203
100_0402_1%

RH472
100_0402_1%

VCCGT_SENSE <75>

VSSGT_SENSE <75>

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

CPU(6/7) +VCCGT

CPU(6/7) +VCCGT

CPU(6/7) +VCCGT

LA-D751P

LA-D751P

LA-D751P

1

12 82Tuesday, August 16, 2016

12 82Tuesday, August 16, 2016

12 82Tuesday, August 16, 2016

1.0

1.0

1.0

5

4

3

2

1

BT32
BT26
BT24
BT21
BT18
BT14
BT12

BR36
BR34
BR29
BR26
BR24
BR21
BR18
BR14
BR12

BP34
BP33
BP29
BP26
BP24
BP21
BP18
BP14
BP12

BN34
BN31
BN30
BN29
BN24
BN21
BN20
BN19
BN18
BN14
BN12

BM38
BM35
BM28
BM27
BM26
BM23
BM21
BM13
BM12

BM9
BM6

BM2
BL29
BK29
BK15
BK14

BJ32
BJ31
BJ25

BJ22
BH14
BH12

BH9
BH8
BH5
BH4

BH1
BG38
BG13
BG12
BF33
BF12
BE29

BD9
BC34
BC12
BB12

C17
C13

BT9
BT5

BR7

BP7

BN9
BN7
BN4
BN2

BE6

SKYLAKE_HAL O

CPU1L

BGA1440

VSS
VSS

C9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

12 OF 14

SKL-H_BGA1440@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS

C25
C23
C21
C19
C15
C11
C8
C5
BM29
BM25
BM18
BM11
BM8
BM7
BM5
BM3
BL38
BL35
BL13
BL6
BK25
BK22
BK13
BK6
BJ30
BJ29
BJ15
BJ12
BH11
BH10
BH7
BH6
BH3
BH2
BG37
BG14
BG6
BF34
BF6
BE30
BE5
BE4
BE3
BE2
BE1
BD38
BD37
BD12
BD11
BD10
BD8
BD7
BD6
BC33
BC14
BC13
BC6
BB30
BB29
BB6
BB5

C2
BT36
BT35
BT4
BT3
BR38

AW30
AW29
AW12

BB4
BB3
BB2

BB1
BA38
BA37
BA12
BA11
BA10

BA9

BA8

BA7

BA6

AY34
AY33
AY14
AY12

AW5
AW4
AW3
AW2

AW1
AV38
AV37
AU34
AU33
AU12
AU11
AU10

AU9
AU8
AU7

AU6
AT30
AT29

AT6

AR38
AR37
AR14
AR13

AR5

AR4

AR3

AR2

AR1

AP34
AP33
AP12
AP11
AP10

AP9

AP8

AN30
AN29
AN12

AN6

AN5

AM38
AM37
AM12

AM5
AM4
AM3
AM2

AM1
AL34
AL33
AL14
AL12
AL10

SKYLAKE_HAL O

CPU1M

BGA1440

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AL9

VSS

AL8

VSS

AL7

VSS

AL4

VSS

13 OF 14

SKL-H_BGA1440@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS

AK30
AK29
AK4
AJ38
AJ37
AJ6
AJ5
AJ4
AJ3
AJ2
AJ1
AH34
AH33
AH12
AH6
AG30
AG29
AG11
AG10
AG8
AG7
AG6
AF14
AF13
AF12
AF4
AF3
AF2
AF1
AE34
AE33
AE6
AD30
AD29
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AC38
AC37
AC12
AC6
AC5
AC4
AC3
AC2
AC1
AB34
AB33
AB6
AA30
AA29
AA12
A30
A28
A26
A24
A22
A20
A18
A16
A14
A12
A10
A9
A6

B37
B3
A34
A4
A3

SKYLAKE_HAL O

CPU1F

BGA1440

Y38

VSS

Y37

VSS

Y14

VSS

Y13

W34
W33
W12

U38
U37

R30
R29
R12

N34
N33
N12
N11
N10

M14
M13
M12

VSS

Y11

VSS

Y10

VSS

Y9

VSS

Y8

VSS

Y7

VSS
VSS
VSS
VSS

W5

VSS

W4

VSS

W3

VSS

W2

VSS

W1

VSS

V30

VSS

V29

VSS

V12

VSS

V6

VSS
VSS
VSS

U6

VSS

T34

VSS

T33

VSS

T14

VSS

T13

VSS

T12

VSS

T11

VSS

T10

VSS

T9

VSS

T8

VSS

T7

VSS

T5

VSS

T4

VSS

T3

VSS

T2

VSS

T1

VSS
VSS
VSS
VSS

P38

VSS

P37

VSS

P12

VSS

P6

VSS
VSS
VSS
VSS
VSS
VSS

N9

VSS

N8

VSS

N7

VSS

N6

VSS

N5

VSS

N4

VSS

N3

VSS

N2

VSS

N1

VSS
VSS
VSS
VSS

M6

VSS

L34

VSS

L33

VSS

L30

VSS

L29

VSS

K38

VSS

K11

VSS

K10

VSS

K9

VSS

K8

VSS

K7

VSS

K5

VSS

K4

VSS

K3

VSS

K2

VSS

6 OF 14

SKL-H_BGA1440@

D D

C C

B B

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NCTFVSS

K1
J36
J33
J32
J25
J22
J18
J10
J7
J4
H35
H32
H25
H22
H18
H12
H11
G28
G26
G24
G23
G22
G20
G18
G16
G14
G12
G10
G9
G8
G6
G5
G4
F36
F31
F29
F27
F25
F23
F21
F19
F17
F15
F13
F11
F9
F8
F5
F4
F3
F2
E38
E35
E34
E9
E4
D33
D30
D28
D26
D24
D22
D20
D18
D16
D14
D12
D10
D9
D6
D3
C37
C31
C29
C27

D38

A A

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

CPU(7/7) VSS

CPU(7/7) VSS

CPU(7/7) VSS

LA-D751P

LA-D751P

LA-D751P

1

1.0

1.0

13 82Tuesday, August 16, 2016

13 82Tuesday, August 16, 2016

13 82Tuesday, August 16, 2016

1.0

5

Layout Note:
Place near JDIMM1.257,259

+2.5V_MEM

D D

Layout Note:
Place near JDIMM1

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

CD9

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD3

CD4

1

1

2

1

CD10

2

2

Layout Note:
Place near JDIMM1.258

+0.6VS

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

CD13

CD12

1

1

2

1

2

2

+1.2V_DDR

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD1

CD2

1

1

2

2

C C

1U_0402_6.3V6K~D

CD75

CD74

1

1

2

2

1U_0402_6.3V6K~D

CD77

CD76

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD78

CD79

1

1

2

2

+1.2V_DDR

10U_0603_6.3V6M~D

1

CD7

2

1 2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

1

1

CD8

CD70

2

RD2
0_0402_5%

RD29
0_0402_5%

CD71

2

2

12

@

12

+1.2V_DDR

12

RH206

1K_0402_1%~D

+V_DDR_REFA

12

RH209

1K_0402_1%~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

1

CD6

CD5

2

2

B B

+3VS +3VS +3VS

12

RD1

@

0_0402_5%

12

RD28
0_0402_5%

+V_DDR_REFA_R

W=20mils

RH484 2_0402_1%

A A

1

CH101

0.022U_0402_25V7K

2

12

RH211

24.9_0402_1%

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

1

CD73

CD72

2

2

12

RD3

@

0_0402_5%

12

RD30
0_0402_5%

10U_0603_6.3V6M~D

CD14

1

2

1

+

CD11
220U_D7_2VM_R6M

2

4

DDR_A_D[0..63]<8>
DDR_A_MA[0..13]<8>
DDR_A_DQS#[0..7]<8>
DDR_A_DQS[0..7]<8>

CFG Straps for Processor

Layout Note:

10U_0603_6.3V6M~D

CD15

Place near JDIMM1.255

+3VS

0.1U_0402_16V7K~D

2.2U_0603_6.3V6K~D

CD16

1

1

2

2

DDR4_DRAMRST#DIMM_CHA_SA0 DIMM _CHA_SA1 DIMM_CHA_SA2

1 2

RD31 0_0402_5%

CD17

+1.2V_DDR

+2.5V_MEM

12

RD35
470_0402_1%

+3VS

DDR_CKE0_DIMMA<8>

M_CLK_DDR0<8>
M_CLK_DDR#0<8>

DDR_A_PAR<8>
DDR_A_BS1<8>

DDR_CS0_DIMMA#< 8>
DDR_A_WE#<8>

M_ODT0<8>
DDR_CS1_DIMMA#< 8>

0.1U_0402_16V7K~D

CD69

1

2

3

+1.2V_DDR

DDR_A_D1

DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D3

DDR_A_D7

DDR_A_D9

DDR_A_D8

DDR_A_D15

DDR_A_D10

DDR_A_D16

DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D19

DDR_A_D18

DDR_A_D24

DDR_A_D29

DDR_A_D26

DDR_A_D27

DDR_CKE0_DIMMA

PCH_SMBCLK<15,18,33,38>

DDR_A_BG1
DDR_A_BG0

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_PAR
DDR_A_BS1

DDR_CS0_DIMMA#
DDR_A_WE#

M_ODT0
DDR_CS1_DIMMA#

M_ODT1

+1.2V_DDR

+1.2V_DDR

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA6

DDR_A_MA3
DDR_A_MA1

DDR_A_D33

DDR_A_D37

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D38

DDR_A_D39

DDR_A_D44

DDR_A_D41

DDR_A_D43

DDR_A_D42

DDR_A_D48

DDR_A_D54

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D53

DDR_A_D55

DDR_A_D56

DDR_A_D60

DDR_A_D58

DDR_A_D62

PCH_SMBCLK

DDR_A_BG1<8>
DDR_A_BG0<8>

M_ODT1<8>

H_DRAMRST# <18>DDR4_DRAMRST#<15>

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229
231
233
235
237
239
241
243
245
247
249
251
253
255
257
259
261

JDIMM1

VSS1
DQ5
VSS3
DQ1
VSS5
DQS0_c
DQS0_t
VSS8
DQ7
VSS10
DQ3
VSS12
DQ13
VSS14
DQ9
VSS16
DM1_n/DBI _n
VSS17
DQ15
VSS19
DQ10
VSS21
DQ21
VSS23
DQ17
VSS25
DQS2_c
DQS2_t
VSS28
DQ23
VSS30
DQ19
VSS32
DQ29
VSS34
DQ25
VSS36
DM3_n/DBI 3_n
VSS37
DQ30
VSS39
DQ26
VSS41
CB5/NC
VSS43
CB1/NC
VSS45
DQS8_c
DQS8_t
VSS48
CB2/NC
VSS50
CB3/NC
VSS52
CKE0
VDD1
BG1
BG0
VDD3
A12
A9
VDD5
A8
A6
VDD7
A3
A1
VDD9
CK0_t
CK0_c
VDD11
PARITY
BA1
VDD13
CS0_n
WE_n/ A14
VDD15
ODT0
CS1_n
VDD17
ODT1
VDD19
C1, CS3_n ,NC
VSS53
DQ37
VSS55
DQ33
VSS57
DQS4_c
DQS4_t
VSS60
DQ38
VSS62
DQ34
VSS64
DQ44
VSS66
DQ40
VSS68
DM5_n/DBI 5_n
VSS69
DQ46
VSS71
DQ42
VSS73
DQ52
VSS75
DQ49
VSS77
DQS6_c
DQS6_t
VSS80
DQ55
VSS82
DQ51
VSS84
DQ61
VSS86
DQ56
VSS88
DM7_n/DBI 7_n
VSS89
DQ62
VSS91
DQ58
VSS93
SCL
VDDSPD
VPP1
VPP2
GND1

CONN@

4H , RVS

DEREN_40-42271-26001RHF

VSS2

VSS4

VSS6

DM0_n/DBI 0_n

VSS7

VSS9

VSS11

DQ12

VSS13

VSS15
DQS1_c
DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

DM2_n/DBI 2_n

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35
DQS3_c
DQS3_t

VSS38

DQ31

VSS40

DQ27

VSS42
CB4/NC

VSS44
CB0/NC

VSS46

DM8_n/DBI _n/NC

VSS47
CB6/NC

VSS49
CB7/NC

VSS51

RESET_n

CKE1
VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

EVENT_n/NF

VDD10
CK1_t/NF
CK1_c/NF

VDD12

A10/AP

VDD14

RAS_n/A1 6

VDD16

CAS_n/A1 5

VDD18

C0/CS2_n /NC

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI 4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c
DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI 6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c
DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

2

+1.2V_DDR

2
4

DQ4

6
8

DQ0

10
12
14
16

DQ6

18
20

DQ2

22
24
26
28

DQ8

30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120

A11

122

A7

124
126

A5

128

A4

130
132

A2

134
136
138
140
142
144

A0

146
148
150

BA0

152
154
156
158

A13

160
162
164
166

SA2

168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254

SDA

256

SA0

258

VTT

260

SA1

262

DDR_A_D0

DDR_A_D4

DDR_A_D6

DDR_A_D2

DDR_A_D12

DDR_A_D13

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D14

DDR_A_D11

DDR_A_D21

DDR_A_D20

DDR_A_D23

DDR_A_D22

DDR_A_D28

DDR_A_D25

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30

DDR_A_D31

DDR4_DRAMRST#
DDR_CKE1_DIMMA

DDR_A_ALERT#

DDR_A_MA11
DDR_A_MA7

DDR_A_MA5
DDR_A_MA4

DDR_A_MA2

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_MA0
DDR_A_MA10

DDR_A_BS0
DDR_A_RAS#

DDR_A_CAS#
DDR_A_MA13

DIMM_CHA_SA2

DDR_A_D36

DDR_A_D32

DDR_A_D35

DDR_A_D34

DDR_A_D40

DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D47

DDR_A_D46

DDR_A_D50

DDR_A_D52

DDR_A_D51

DDR_A_D49

DDR_A_D61

DDR_A_D57

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D59

DDR_A_D63

PCH_SMBDATA
DIMM_CHA_SA0

DIMM_CHA_SA1

DDR_CKE1_DIMMA <8>

DDR_A_ACT# <8>
DDR_A_ALERT# <8>

All VREF traces should
have 10 mil trace width

+1.2V_DDR

+1.2V_DDR

M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>

DDR_A_BS0 <8>
DDR_A_RAS# <8>

DDR_A_CAS# <8>

PCH_SMBDATA <15,18,33,38>

+V_DDR_REFA

+V_DDR_REFA

0.1U_0402_16V7K~D

CD18

1

2

+0.6VS

1

1

CD91

0.1U_0402_16V7K~D

@ESD@

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDR4 DIMMA,RVS

DDR4 DIMMA,RVS

DDR4 DIMMA,RVS

LA-D751P

LA-D751P

LA-D751P

1

14 82Tuesday, August 16, 2016

14 82Tuesday, August 16, 2016

14 82Tuesday, August 16, 2016

1.0

1.0

1.0

5

4

3

2

1

4H , STD

JDIMM2

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5

11

DQS0_c

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI _n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25

53

DQS2_c

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3_n/DBI 3_n

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45

95

DQS8_c

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/ A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n ,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI 5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI 7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

CONN@

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

DM0_n/DBI 0_n

DQS1_c

DQS1_t

DM2_n/DBI 2_n

DQS3_c

DQS3_t

CB4/NC

CB0/NC

DM8_n/DBI _n/NC

CB6/NC

CB7/NC

RESET_n

ALERT_n

EVENT_n/NF

VDD10
CK1_t/NF
CK1_c/NF

VDD12

A10/AP

VDD14

RAS_n/A1 6

VDD16

CAS_n/A1 5

VDD18

C0/CS2_n /NC

VREFCA

DM4_n/DBI 4_n

DQS5_c

DQS5_t

DM6_n/DBI 6_n

DQS7_c

DQS7_t

DEREN_40-42261-26001RHF

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

VSS2

VSS4

VSS6

VSS7

VSS9

VSS11

DQ12

VSS13

VSS15

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

VSS38

DQ31

VSS40

DQ27

VSS42

VSS44

VSS46

VSS47

VSS49

VSS51

CKE1
VDD2

ACT_n

VDD4

VDD6

VDD8

VSS54

DQ36

VSS56

DQ32

VSS58

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

+1.2V_DDR

2
4

DQ4

6
8

DQ0

10
12
14
16

DQ6

18
20

DQ2

22
24
26
28

DQ8

30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120

A11

122

A7

124
126

A5

128

A4

130
132

A2

134
136
138
140
142
144

A0

146
148
150

BA0

152
154
156
158

A13

160
162
164
166

SA2

168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254

SDA

256

SA0

258

VTT

260

SA1

262

2

DDR4_DRAMRST#
DDR_CKE3_DIMMB

DDR_B_ALERT#

DDR_B_MA11
DDR_B_MA7

DDR_B_MA5
DDR_B_MA4

DDR_B_MA2

M_CLK_DDR3
M_CLK_DDR#3

DDR_B_MA0
DDR_B_MA10

DDR_B_BS0
DDR_B_RAS#

DDR_B_CAS#

DDR_B_MA13

DIMM_CHB_SA2

DDR_B_D35

DDR_B_D34

DDR_B_D36

DDR_B_D37

DDR_B_D44

DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D47

DDR_B_D46

DDR_B_D54

DDR_B_D48

DDR_B_D53

DDR_B_D49

DDR_B_D59

DDR_B_D57

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D63

DDR_B_D58

PCH_SMBDATA
DIMM_CHB_SA0

DIMM_CHB_SA1

DDR_B_D5

DDR_B_D1

DDR_B_D2

DDR_B_D7

DDR_B_D8

DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D15

DDR_B_D11

DDR_B_D22

DDR_B_D18

DDR_B_D21

DDR_B_D20

DDR_B_D27

DDR_B_D30

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D29

DDR_B_D24

+1.2V_DDR

DDR_CKE3_DIMMB <8>

DDR_B_ACT# <8>
DDR_B_ALERT# <8>

M_CLK_DDR3 <8>
M_CLK_DDR#3 <8>

DDR_B_BS0 <8>
DDR_B_RAS# <8>

DDR_B_CAS# <8>

+V_DDR_REFB

0.1U_0402_16V7K~D

1

2

1

CD92

0.1U_0402_16V7K~D

@ESD@

2

CD29

+1.2V_DDR

+0.6VS

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDR4 DIMMB,STD

DDR4 DIMMB,STD

DDR4 DIMMB,STD

LA-D751P

LA-D751P

LA-D751P

1

DDR4_DRAMRST# <14>

15 82Tuesday, August 16, 2016

15 82Tuesday, August 16, 2016

15 82Tuesday, August 16, 2016

1.0

1.0

1.0

DDR_B_D[0..63]<8>
DDR_B_MA[0..13]<8>
DDR_B_DQS#[0..7]<8>

Layout Note:
Place near JDIMM2.258

+0.6VS

D D

Layout Note:
Place near JDIMM2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

CD32

1

1

CD90

2

2

10U_0603_6.3V6M~D

1

1

CD89

2

2

Layout Note:
Place near JDIMM2.257,259

+2.5V_MEM

CD88

1U_0402_6.3V6K~D

CD31

CD30

1

1

2

2

1

1

CD27

2

2

CD28

Layout Note:
Place near JDIMM2.255

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

DDR_B_DQS[0..7]<8>

+3VS

0.1U_0402_16V7K~D

2.2U_0603_6.3V6K~D

CD34

1

2

CD35

1

2

DDR_B_D0

DDR_B_D4

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6

DDR_B_D3

DDR_B_D10

DDR_B_D14

DDR_B_D12

DDR_B_D13

DDR_B_D16

DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D19

DDR_B_D23

DDR_B_D25

DDR_B_D28

DDR_B_D26

DDR_B_D31

+1.2V_DDR

+1.2V_DDR

1U_0402_6.3V6K~D

C C

1U_0402_6.3V6K~D

CD19

CD20

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD21

1

2

1U_0402_6.3V6K~D

CD22

1

2

1U_0402_6.3V6K~D

CD83

CD81

1

1

2

2

+1.2V_DDR

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

1

CD24

CD23

2

2

B B

+3VS +3VS +3VS

12

@

DIMM_CHB_SA0 DIMM_CHB_SA1 DIMM_CHB_SA2

12

+V_DDR_REFB_R

1

2

RD4
0_0402_5%

RD38
0_0402_5%

10U_0603_6.3V6M~D

1

CD25

CD26

2

W=20mils

A A

1 2

RH485 2_0402_1%

1

CH100

0.022U_0402_25V7K

2

12

RH212

24.9_0402_1%

5

1

2

10U_0603_6.3V6M~D

CD87

1

2

12

RD5
0_0402_5%

12

RD39

@

0_0402_5%

+1.2V_DDR

10U_0603_6.3V6M~D

CD85

12

1K_0402_1%~D

12

1K_0402_1%~D

1U_0402_6.3V6K~D

1

2

10U_0603_6.3V6M~D

1

2

RH207

+V_DDR_REFB

RH210

1U_0402_6.3V6K~D

CD82

CD80

1

2

10U_0603_6.3V6M~D

1

1

+

CD33

CD86

CD84

220U_D7_2VM_R6M

2

2

12

RD6

@

0_0402_5%

12

RD40
0_0402_5%

4

+3VS

+2.5V_MEM

DDR_CKE2_DIMMB<8>

DDR_B_BG1<8>
DDR_B_BG0<8>

M_CLK_DDR2<8>
M_CLK_DDR#2<8>

DDR_B_PAR<8>
DDR_B_BS1<8>

DDR_CS2_DIMMB#< 8>
DDR_B_WE#<8>

M_ODT2<8>
DDR_CS3_DIMMB#< 8>

M_ODT3<8>

DDR_CKE2_DIMMB

DDR_B_BG1
DDR_B_BG0

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA6

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_PAR
DDR_B_BS1

DDR_CS2_DIMMB#
DDR_B_WE#

M_ODT2
DDR_CS3_DIMMB#

M_ODT3

DDR_B_D38

DDR_B_D39

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D33

DDR_B_D32

DDR_B_D40

DDR_B_D41

+1.2V_DDR

DDR_B_D42

DDR_B_D43

DDR_B_D52

DDR_B_D51

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50

DDR_B_D55

DDR_B_D61

DDR_B_D62

+1.2V_DDR

DDR_B_D56

DDR_B_D60

PCH_SMBCLK<14,18,33,38> PCH_SMBDATA <14,18,33,38>

3

PCH_SMBCLK

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

UH1

S IC GLCM236 SR2CE D1 FCBGA 837P PCH-H

SA00009601L
PCHR1@

UH1

4

3

2

1

S IC GLCM236 SR2CE D1 FCBGA PCH-H A31!

D D

SA00009602L
PCHR3@

UH1

S IC A31 GLSSKU QJGE D1 FCBGA 837P PCH-H

SA00008RM1L
PCHES@

PCIE_PTX_DRX_P11_C

12

CPU_DDI1HPD<56>
CPU_DDI2HPD<56>

CH2020.22U_0201_6.3V

12

CH2030.22U_0201_6.3V

12

CH2040.22U_0201_6.3V

12

CH2050.22U_0201_6.3V

12

CH2060.22U_0201_6.3V

12

CH2070.22U_0201_6.3V

12

CH2080.22U_0201_6.3V

12

CH2090.22U_0201_6.3V

12

CH2180.22U_0201_6.3V

12

CH2190.22U_0201_6.3V

12

CH2200.22U_0201_6.3V

12

CH2210.22U_0201_6.3V

RH656
0_0201_5%

1 2

1 2

@

RH657
0_0201_5%

PCIE_PTX_DRX_N11_C
PCIE_PRX_DTX_P11
PCIE_PRX_DTX_N11

PCIE_PTX_DRX_N14_C
PCIE_PTX_DRX_P14_C
PCIE_PRX_DTX_N14
PCIE_PRX_DTX_P14

PCIE_PTX_DRX_N13_C
PCIE_PTX_DRX_P13_C
PCIE_PRX_DTX_N13
PCIE_PRX_DTX_P13

PCIE_PTX_DRX_P12_C
PCIE_PTX_DRX_N12_C

PCIE_PRX_DTX_P12

PCIE_PRX_DTX_N12

PCIE_PTX_DRX_P20_C
PCIE_PTX_DRX_N20_C
PCIE_PRX_DTX_P20

PCIE_PRX_DTX_N20

PCIE_PTX_DRX_P19_C
PCIE_PTX_DRX_N19_C

PCIE_PRX_DTX_P19

PCIE_PRX_DTX_N19

RH9

100K_0402_5%

M . 2 S S D S l o t # 3
P C I e / S A T A

M . 2 S S D S l o t # 1
P C I e / S A T A

C C

M . 2 S S D S l o t # 3
P C I e / S A T A

M . 2 S S D S l o t # 2
P C I e / S A T A

B B

PCIE_PTX_DRX_P11<29>
PCIE_PTX_DRX_N11<29>

PCIE_PRX_DTX_P11<29>
PCIE_PRX_DTX_N11<29>

PCIE_PTX_DRX_N14<29>
PCIE_PTX_DRX_P14<29>
PCIE_PRX_DTX_N14<29>
PCIE_PRX_DTX_P14<29>

PCIE_PTX_DRX_N13<29>
PCIE_PTX_DRX_P13<29>
PCIE_PRX_DTX_N13<29>
PCIE_PRX_DTX_P13<29>

PCIE_PTX_DRX_P12<29>
PCIE_PTX_DRX_N12<29>

PCIE_PRX_DTX_P12<29>

PCIE_PRX_DTX_N12<29>
PCIE_PTX_DRX_P20<29>
PCIE_PTX_DRX_N20<29>

PCIE_PRX_DTX_P20<29>

PCIE_PRX_DTX_N20<29>
PCIE_PTX_DRX_P19<29>
PCIE_PTX_DRX_N19<29>

PCIE_PRX_DTX_P19<29>

PCIE_PRX_DTX_N19<29>

EDP_HPD_CPU<24>

EDP_HPD<24,25,46>

SKL eDP_HPD pull down 100K

AV2
AV3

AW2

R44
R43
U39
N42

U43
U42
U41
M44
U36

P44
T45
T44

B33

C33

K31
L31

AB33
AB35
AA44
AA45

B38
C38
D39

E37

C36

B36
G35

E35

A35

B35
H33
G33

J45

K44
N38
N39
H44
H43

L39

L37

12

UH1C

CL_CLK
CL_DATA
CL_RST#

GPP_G8/FAN_PWM_0
GPP_G9/FAN_PWM_1
GPP_G10/FAN_PWM_2
GPP_G11/FAN_PWM_3

GPP_G0/FAN_TACH_0
GPP_G1/FAN_TACH_1
GPP_G2/FAN_TACH_2
GPP_G3/FAN_TACH_3
GPP_G4/FAN_TACH_4
GPP_G5/FAN_TACH_5
GPP_G6/FAN_TACH_6
GPP_G7/FAN_TACH_7

PCIE11_TXP
PCIE11_TXN
PCIE11_RXP
PCIE11_RXN

GPP_F10/SCLOCK
GPP_F11/SLOAD
GPP_F13/SDATAOUT0
GPP_F12/SDATAOUT1

PCIE14_TXN/SATA1B_TXN
PCIE14_TXP/SATA1B_TXP
PCIE14_RXN/SATA1B_RXN
PCIE14_RXP/SATA1B_RXP

PCIE13_TXN/SATA0B_TXN
PCIE13_TXP/SATA0B_TXP
PCIE13_RXN/SATA0B_RXN
PCIE13_RXP/SATA0B_RXP

PCIE12_TXP
PCIE12_TXN
PCIE12_RXP
PCIE12_RXN
PCIE20_TXP/SATA7_TXP
PCIE20_TXN/SATA7_TXN
PCIE20_RXP/SATA7_RXP
PCIE20_RXN/SATA7_RXN
PCIE19_TXP/SATA6_TXP
PCIE19_TXN/SATA6_TXN
PCIE19_RXP/SATA6_RXP
PCIE19_RXN/SATA6_RXN

SKL-H-PCH_BGA837

@

UH1E

AW4

GPP_I0/DDPB_HPD0

AY2

GPP_I1/DDPC_HPD1

AV4

GPP_I2/DDPD_HPD2

BA4

GPP_I3/DDPE_HPD3

BD7

GPP_I4/EDP_HPD

SKL-H-PCH_BGA837

@

SPT-H_PCH

CLINK

FAN

PCIe/SATA

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_F0/SATAXPCIE3/SATAGP3
GPP_F1/SATAXPCIE4/SATAGP4
GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6
GPP_F4/SATAXPCIE7/SATAGP7

HOST

3 OF 12 REV = 1.3

SPT-H_PCH

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I9/DDPD_CTRLCLK

GPP_I10/DDPD_CTRLDATA

5 OF 12 REV = 1.3

PCIE9_RXN/SATA0A_RXN
PCIE9_RXP/SATA0A_RXP
PCIE9_TXN/SATA0A_TXN

PCIE9_TXP/SATA0A_TXP

PCIE10_RXN/SATA1A_RXN

PCIE10_RXP/SATA1A_RXP
PCIE10_TXN/SATA1A_TXN
PCIE10_TXP/SATA1A_TXP

PCIE15_RXN/SATA2_RXN

PCIE15_RXP/SATA2_RXP
PCIE15_TXN/SATA2_TXN
PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN

PCIE16_RXP/SATA3_RXP
PCIE16_TXN/SATA3_TXN
PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN

PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_TXN
PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN

PCIE18_RXP/SATA5_RXP
PCIE18_TXN/SATA5_TXN
PCIE18_TXP/SATA5_TXP

GPP_E8/SATALED#

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THERMTRIP#

PECI

PM_SYNC

PLTRST_PROC#

PM_DOWN

BB3
BD6
BA5
BC4
BE5
BE6

Y44

GPP_F14

V44

GPP_F23

W39

GPP_F22

L43

GPP_G23

L44

GPP_G22

U35

GPP_G21

R35

GPP_G20

BD36

GPP_H23

PCIE_PRX_DTX_N9

G31

PCIE_PRX_DTX_P9

H31

PCIE_PTX_DRX_N9_C

C31

PCIE_PTX_DRX_P9_C

B31

PCIE_PRX_DTX_N10

G29

PCIE_PRX_DTX_P10

E29

PCIE_PTX_DRX_N10_C

C32

PCIE_PTX_DRX_P10_C

B32

F41
E41
B39
A39

SATA_PRX_DTX_N3

D43

SATA_PRX_DTX_P3

E42

SATA_PTX_DRX_N3

A41

SATA_PTX_DRX_P3

A40

PCIE_PRX_DTX_N17

H42

PCIE_PRX_DTX_P17

H40

PCIE_PTX_DRX_N17_C

E45

PCIE_PTX_DRX_P17_C

F45

PCIE_PRX_DTX_N18

K37

PCIE_PRX_DTX_P18

G37

PCIE_PTX_DRX_N18_C

G45

PCIE_PTX_DRX_P18_C

G44

PCH_SATADET#

AD44

SATA_GP0

AG36

SATA_GP1

AG35
AG39

SATA_GP3

AD35

SATA_GP4

AD31
AD38
AC43
AB44

IGPU_INV_PWM

W36

IGPU_ENBKL

W35

IGPU_ENVDD

W42

AJ3

PCH_PECI

AL3

H_PM_SYNC_R

AJ4

PLTRST_CPU#

AK2

H_PM_DOWN

AH2

PCH_SATADET# <33>
SATA_GP0 <29>
SATA_GP1 <29>

SATA_GP3 <33>
SATA_GP4 <29>

IGPU_INV_PWM <24>
IGPU_ENBKL <24>
IGPU_ENVDD <24>

1 2

RH79 620_0402_5%

1 2

RH73 12.1_0402_1%

CPU_DDC2CLK <56>
CPU_DDC2DATA <56>
CPU_DDC1CLK <56>
CPU_DDC1DATA <56>

PROC_DETECT# <9>

STRAP3_PCH <51>
STRAP5_PCH <51>

+3VS

RH584
10K_0402_5%

1 2

DET <25>

PCIE_PRX_DTX_N9 <29>

H_THERMTRIP#H_THERMTRIP#_R

PCIE_PRX_DTX_P9 <29>
PCIE_PTX_DRX_N9 <29>
PCIE_PTX_DRX_P9 <29>

PCIE_PRX_DTX_N10 <29>
PCIE_PRX_DTX_P10 <29>
PCIE_PTX_DRX_N10 <29>
PCIE_PTX_DRX_P10 <29>

SATA_PRX_DTX_N3 <33>
SATA_PRX_DTX_P3 <33>

SATA_PTX_DRX_N3 <33>

SATA_PTX_DRX_P3 <33>

PCIE_PRX_DTX_N17 <29>
PCIE_PRX_DTX_P17 <29>
PCIE_PTX_DRX_N17 <29>
PCIE_PTX_DRX_P17 <29>

PCIE_PRX_DTX_N18 <29>
PCIE_PRX_DTX_P18 <29>
PCIE_PTX_DRX_N18 <29>
PCIE_PTX_DRX_P18 <29>

H_THERMTRIP# <9>
H_PECI <9,43>
H_PM_SYNC_R <9>
PLTRST_CPU# <9>
H_PM_DOWN <9>

M . 2 S S D S l o t # 3
P C I e / S A T A

M . 2 S S D S l o t # 5
o r S A T A H D D

M . 2 S S D S l o t # 2
P C I e / S A T A

PCH_SATADET#

1 2

RH512 10K_0402_5%

+3VS

12

CH2100.22U_0201_6.3V

12

CH2110.22U_0201_6.3V

12

CH2120.22U_0201_6.3V

12

CH2130.22U_0201_6.3V

12

CH2140.22U_0201_6.3V

12

CH2150.22U_0201_6.3V

12

CH2160.22U_0201_6.3V

12

CH2170.22U_0201_6.3V

RH585
10K_0402_5%

@

1 2

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

PCH (1/7) SATA,DDC,PCIE

PCH (1/7) SATA,DDC,PCIE

PCH (1/7) SATA,DDC,PCIE

Document Number Re v

Document Number Re v

Document Number Re v

LA-D751P

LA-D751P

LA-D751P

1

16 82Tuesday, August 16, 2016

16 82Tuesday, August 16, 2016

16 82Tuesday, August 16, 2016

1.0

1.0

1.0

5

D D

+3VS

RP3

4 5
3 6
2 7
1 8

10K_0804_8P4R_5%

+3VS

4 5
3 6
2 7
1 8

10K_0804_8P4R_5%

C C

CLKREQ#_GPU
CLKREQ_PCIE#1
CLKREQ_PCIE#2
CLKREQ_PCIE#4

RP5

CLKREQ#_DGPU
CLKREQ_PCIE#5
FFS_INT2
FFS_INT1

0 . P E G
1 . S S D 1
2 . S S D 2

3 . T B T

4 . L A N
5 . W L A N
6 . C a l d e r a
7 . S S D 3

+1V_PCH

4

CPU_24MHZ_P<9>
CPU_24MHZ_N<9>

PCH_CPU_BCLK_P<9>
PCH_CPU_BCLK_N<9>

RH71 2.7K_0402_1%

1 2

CLKREQ#_GPU<46>
CLKREQ_PCIE#1<29>
CLKREQ_PCIE#2<29>
CLKREQ_PCIE#3<56>
CLKREQ_PCIE#4<30>
CLKREQ_PCIE#5<28>
CLKREQ#_DGPU<41,43>
CLKREQ_PCIE#7<29>

GPU_GC6_FB_EN_R<46>

XTAL24_OUT
XTAL24_IN

XCLK_BIASREF

PCH_RTCX1
PCH_RTCX2

UH1G

AR17

GPP_A16/CLKOUT_48

G1

CLKOUT_CPUNSSC_P

F1

CLKOUT_CPUNSSC_N

G2

CLKOUT_CPUBCLK_P

H2

CLKOUT_CPUBCLK_N

A5

XTAL24_OUT

A6

XTAL24_IN

E1

XCLK_BIASREF

BC9

RTCX1

BD10

RTCX2

BC24

GPP_B5/SRCCLKREQ0#

AW24

GPP_B6/SRCCLKREQ1#

AT24

GPP_B7/SRCCLKREQ2#

BD25

GPP_B8/SRCCLKREQ3#

BB24

GPP_B9/SRCCLKREQ4#

BE25

GPP_B10/SRCCLKREQ5#

AT33

GPP_H0/SRCCLKREQ6#

AR31

GPP_H1/SRCCLKREQ7#

BD32

GPP_H2/SRCCLKREQ8#

BC32

GPP_H3/SRCCLKREQ9#

BB31

GPP_H4/SRCCLKREQ10#

BC33

GPP_H5/SRCCLKREQ11#

BA33

GPP_H6/SRCCLKREQ12#

AW33

GPP_H7/SRCCLKREQ13#

BB33

GPP_H8/SRCCLKREQ14#

BD33

GPP_H9/SRCCLKREQ15#

R13

CLKOUT_PCIE_N15

R11

CLKOUT_PCIE_P15

P1

CLKOUT_PCIE_N14

R2

CLKOUT_PCIE_P14

W7

CLKOUT_PCIE_N13

Y5

CLKOUT_PCIE_P13

U2

CLKOUT_PCIE_N12

U3

CLKOUT_PCIE_P12

SKL-H-PCH_BGA837

@

SPT-H_PCH

CLKOUT_CPUPCIBCLK_N
CLKOUT_CPUPCIBCLK_P

7 OF 12 REV = 1.3

3

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5

CLKOUT_PCIE_N6
CLKOUT_PCIE_P6

CLKOUT_PCIE_N7
CLKOUT_PCIE_P7

CLKOUT_PCIE_N8
CLKOUT_PCIE_P8

CLKOUT_PCIE_N9
CLKOUT_PCIE_P9

CLKOUT_PCIE_N10
CLKOUT_PCIE_P10

CLKOUT_PCIE_N11
CLKOUT_PCIE_P11

L1
L2
J1
J2

N7
N8

L7
L5

D3
F2

E5
G4

D5
E6

D8
D7

R8
R7

U5
U7

W10
W11

N3
N2

P3
P2

R3
R4

PCH_XDP_CLK_N
PCH_XDP_CLK_P

CLK_PEG_GPU#
CLK_PEG_GPU

CLK_PCIE_N1
CLK_PCIE_P1

CLK_PCIE_N2
CLK_PCIE_P2

CLK_PCIE_N3
CLK_PCIE_P3

CLK_PCIE_N4
CLK_PCIE_P4

CLK_PCIE_N5
CLK_PCIE_P5

CLK_PCIE_N6
CLK_PCIE_P6

CLK_PCIE_N7
CLK_PCIE_P7

T49 PAD~D TP@
T50 PAD~D TP@

PCH_CPU_PCIBCLK_N <9>
PCH_CPU_PCIBCLK_P <9>

CLK_PEG_GPU# <46>
CLK_PEG_GPU <46>

CLK_PCIE_N1 <29>
CLK_PCIE_P1 <29>

CLK_PCIE_N2 <29>
CLK_PCIE_P2 <29>

CLK_PCIE_N3 <56>
CLK_PCIE_P3 <56>

CLK_PCIE_N4 <30>
CLK_PCIE_P4 <30>

CLK_PCIE_N5 <28>
CLK_PCIE_P5 <28>

CLK_PCIE_N6 <41>
CLK_PCIE_P6 <41>

CLK_PCIE_N7 <29>
CLK_PCIE_P7 <29>

2

P E G

S S D 1

S S D 2

T B T

L A N

W L A N

C a l d e r a

S S D 3

8.2P_0402_50V

15P_0402_50V

RH70
10M_0402_5%

1 2

32.768KHZ_X1A000141000300

1 2

1

CH45

2

RTC CRYSTAL
Max Crystal ESR
= 50k Ohm.

1 2

24MHZ 12PF +-10PPM 7M24090001

1

CH47

2

YH1

RH72
1M_0402_5%~D

YH2

123

4

1

PCH_RTCX1

PCH_RTCX2

1

CH46

8.2P_0402_50V

2

XTAL24_IN

XTAL24_OUT

1

CH48
15P_0402_50V

2

Metal Shielding Type

1

2

PCH_SPI_CS#
PCH_SPI_SO
PCH_SPI_WP#

+3VS

UH3

5

TC7SH08FU_SSOP5

P

B

A

G

3

1

CH201

0.1U_0201_6.3V6K

2

4

Y

UH4

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

W25Q128FVSIQ_SO8

12

RH199
100K_0402_5%

VCC

/HOLD(IO3)

CLK

DI(IO0)

PCIRST# <28,29,30,43,56>

+3V_PCH

1

CH49

0.1U_0402_16V7K

2

8

PCH_SPI_HOLD#

7

PCH_SPI_CLK

6

PCH_SPI_SI

5

UH1A

BD17

GPP_A11/PME#

AG15

RSVD

AG14

RSVD

AF17

RSVD

AE17

RSVD

RH1 close to UH4

1 2

XDP_SPI_SI<6>

+3V_PCH

1 2

RH74 3.3K_0402_5%@

1 2

RH75 1K_0402_5%

1 2

B B

RH78 1K_0402_5%

1 2

RH455 1K_0402_5%@

PCH_SPI_CS#

PCH_SPI_WP#_R

PCH_SPI_HOLD#_R

PCH_SPI_HOLD#_R

RH1 1K_0402_1%

PCH_SPI_WP#_R<6>

FFS_INT2<33>
FFS_INT1<33>

PCH_SPI_SI_R
PCH_SPI_SO_R
PCH_SPI_CS#
PCH_SPI_CLK_R

PCH_SPI_WP#_R
PCH_SPI_HOLD#_R

FFS_INT2
FFS_INT1

AR19
AN17

BB29

BE30
BD31
BC31
AW31

BC29
BD30

AT31
AN36

AL39
AN41
AN38
AH43
AG44

SKL-H-PCH_BGA837

@

TP2
TP1

SPI0_MOSI
SPI0_MISO
SPI0_CS0#
SPI0_CLK
SPI0_CS1#

SPI0_IO2
SPI0_IO3
SPI0_CS2#
GPP_D1/SPI1_CLK
GPP_D0/SPI1_CS#
GPP_D3/SPI1_MOSI
GPP_D2/SPI1_MISO
GPP_D22/SPI1_IO3
GPP_D21/SPI1_IO2

SPT-H_PCH

GPP_B13/PLTRST#

GPP_G16/GSXCLK

GPP_G12/GSXDOUT

GPP_G13/GSXSLOAD

GPP_G14/GSXDIN

GPP_G15/GSXSRESET#

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

GPP_H18/SML4ALERT#

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H15/SML3ALERT#

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H12/SML2ALERT#

GPP_H11/SML2DATA

GPP_H10/SML2CLK

INTRUDER#

REV = 1.31 OF 12

BB27

P43
R39
R36
R42
R41

AF41
AE44
BC23
BD24

BC36
BE34
BD39
BB36
BA35
BC35
BD35
AW35
BD34
BE11

PCH_PLTRST#

TBT_FORCE_PWR

INTRUDER#

+RTC_CELL

1 2

RH531
1M_0402_5%

PCH_PLTRST# <41,46>

TBT_FORCE_PWR <56>

PCH_PLTRST#

SPI ROM FOR ME ( 16MByte )

RPH5

4 5
3 6
2 7
1 8

15_0804_8P4R_5%

1 2

PCH_SPI_HOLD#_R
PCH_SPI_SO_R
PCH_SPI_SI_R
PCH_SPI_WP#_R

PCH_SPI_CLK_RPCH_SPI_CLK

PCH_SPI_SI_R <9>

PCH_SPI_HOLD#
PCH_SPI_SO
PCH_SPI_SI
PCH_SPI_WP#

RH104 15_0402_1%EMI@

A A

PN: SA00005VV10

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

PCH (2/7) CLK,SPI,PLTRST

PCH (2/7) CLK,SPI,PLTRST

PCH (2/7) CLK,SPI,PLTRST

Document Number Re v

Document Number Re v

Document Number Re v

LA-D751P

LA-D751P

LA-D751P

1

17 82Tuesday, August 16, 2016

17 82Tuesday, August 16, 2016

17 82Tuesday, August 16, 2016

1.0

1.0

1.0

5

D D

C C

PCH_AZ_CODEC_SDOUT<31>
PCH_AZ_CODEC_SYNC<31>
PCH_AZ_CODEC_RST#<31>
PCH_AZ_CODEC_BITCLK<31>

RP2

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

PCH_AZ_SDOUT
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_BITCLK

CPU_DISPA_SDO<7>

CPU_DISPA_SDI<7>

CPU_DISPA_BCLK<7>

ME_EN<43>

PCH to DDR, XDP, FFS

+RTC_CELL

1 2

RH83 20K_0402_5%~D

1U_0603_10V6K~D

CH52

PCH_SRTCRST#

1

2

4

PCH_AZ_CODEC_SDIN0<31>

1 2

RH16 1K_0402_1%

1 2

RH39 30_0402_5%

1 2

RH38 30_0402_5%

PCH_PWROK<43>
EC_RSMRST#<43>

PCH_DPWROK<43>

PCH_SMBCLK<14,15,33,38>
PCH_SMBDATA<14,15,33,38>

SML0CLK<24,41>
SML0DATA<24,41>

PCH_AZ_BITCLK
PCH_AZ_RST#

PCH_AZ_SDOUT
PCH_AZ_SYNC

CPU_DISPA_SDO_R

CPU_DISPA_BCLK_R

PCH_RTCRST#
PCH_SRTCRST#

EC_RSMRST#

PCH_DPWROK

PCH_SMBCLK
PCH_SMBDATA

SML0CLK
SML0DATA

SML1CLK
SML1DATA

UH1D

BA9

HDA_BCLK

BD8

HDA_RST#

BE7

HDA_SDI0

BC8

HDA_SDI1

BB7

HDA_SDO

BD9

HDA_SYNC

BD1

RSVD_BD1

BE2

RSVD_BE2

AM1

DISPA_SDO

AN2

DISPA_SDI

AM2

DISPA_BCLK

AL42

GPP_D8/I2S0_SCLK

AN42

GPP_D7/I2S0_RXD

AM43

GPP_D6/I2S0_TXD

AJ33

GPP_D5/I2S0_SFRM

AH44

GPP_D20/DMIC_DATA0

AJ35

GPP_D19/DMIC_CLK0

AJ38

GPP_D18/DMIC_DATA1

AJ42

GPP_D17/DMIC_CLK1

BC10

RTCRST#

BB10

SRTCRST#

AW11

PCH_PWROK

BA11

RSMRST#

AV11

DSW_PWROK

BB41

GPP_C2/SMBALERT#

AW44

GPP_C0/SMBCLK

BB43

GPP_C1/SMBDATA

BA40

GPP_C5/SML0ALERT#

AY44

GPP_C3/SML0CLK

BB39

GPP_C4/SML0DATA

AT27

GPP_B23/SML1ALERT#/PCHHOT#

AW42

GPP_C6/SML1CLK

AW45

GPP_C7/SML1DATA

SKL-H-PCH_BGA837

@

AUDIO

3

SPT-H_PCH

GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_A13/SUSWARN#/SUSPWRDNACK

SMBUS

JTAG

4 OF 12 REV = 1.3

GPP_A8/CLKRUN#

GPD11/LANPHYPC

GPD9/SLP_WLAN#

GPP_B2/VRALERT#

GPP_G17/ADR_COMPLETE

GPP_B12/SLP_S0#

GPP_A15/SUSACK#

GPD2/LAN_WAKE#
GPD1/ACPRESENT

DRAM_RESET#

GPP_B1
GPP_B0

GPP_B11

SYS_PWROK

WAKE#

GPD6/SLP_A#

SLP_LAN#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

SLP_SUS#

GPD3/PWRBTN#

SYS_RESET#

GPP_B14/SPKR

PROCPWRGD

ITP_PMODE

JTAGX
JTAG_TMS
JTAG_TDO

JTAG_TDI

JTAG_TCK

BB17
AW22

AR15

AV13

BC14
BD23
AL27
AR27
N44
AN24
AY1

BC13
BC15
AV15
BC26
AW15
BD15
BA13

AN15
BD13
BB19
BD19

BD11
BB15
BB13
AT13
AW1
BD26
AM3

AT2
AR3
AR2
AP1
AP2
AN3

CLKRUN#

WAKE#

RH4 0_0402_5%

PCH_BATLOW#

ME_SUS_PWR_ACK

WAKE_PCH#
AC_PRESENT

SYS_RESET#

2

H_DRAMRST# <14>

SYS_PWROK <43>

12

@

PM_SLP_S3# <37,43,45>
PM_SLP_S4# <43,45>
PM_SLP_S5# <37,43>

SUSCLK <29>
PCH_BATLOW# <56>
SUSACK# <43>
ME_SUS_PWR_ACK <43>

PM_SLP_SUS# <43>
PBTN_OUT# <9,43>

SYS_RESET# <9>
HDA_SPKR <31>
H_CPUPWRGD <9>

XDP_ITP_PMODE <6>
PCH_JTAG_TCK <6, 9>
XDP_TMS <6,9>

XDP_TDO <9>

XDP_TDI <6,9>
XDP_TCK <6>

WAKE#

PCH_BATLOW#

AC_PRESENT

WAKE_PCH#

ME_SUS_PWR_ACK

SYS_RESET#

CLKRUN#

PCIE_WAKE# <30,43>

12

DH1
RB751V-40_SOD323-2

1

1 2

RH453 10K_0402_5%

1 2

RH515 8.2K_0402_5%

1 2

RH533 8.2K_0402_5%

1 2

RH545 10K_0402_5%

1 2

RH506 1M_0402_5%@

1 2

RH571 8.2K_0402_5%@

1 2

RH85 8.2K_0402_5%

VCIN1_AC_IN <43,62>

+3VALW

+3V_PCH

+3VS

+RTC_CELL

1 2

RH84 20K_0402_5%~D

B B

+3V_PCH

+3VS

A A

5

1U_0603_10V6K~D

1 2

RH460 1K_0402_5%

1 2

RH461 1K_0402_5%

1 2

RH501 499_0402_1%

1 2

RH502 499_0402_1%

1 2

RH463 1K_0402_5%

1 2

RH462 1K_0402_5%

1 2

RH88 10K_0402_5%

1 2

RH90 100K_0402_5%

CH53

1

12

SHORT PADS

2

SML1CLK

SML1DATA

SML0CLK

SML0DATA

PCH_SMBCLK

PCH_SMBDATA

EC_RSMRST#

PCH_DPWROK

PCH_RTCRST#

CLRP1

PCH_RTCRST# <43>

CLRP1 in DIMM door

+3VS

2

SML1CLK

SML1DATA

4

5

3

QH5B

DMN66D0LDW-7

6 1

QH5A

DMN66D0LDW-7

4

EC_SMB_CK2 <41,42,43,46,58>

EC_SMB_DA2 <41,42,43,46,58>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

PCH (3/7) PM,HDA,SMB,JTAG

PCH (3/7) PM,HDA,SMB,JTAG

PCH (3/7) PM,HDA,SMB,JTAG

Document Number Re v

Document Number Re v

Document Number Re v

LA-D751P

LA-D751P

LA-D751P

1

18 82Tuesday, August 16, 2016

18 82Tuesday, August 16, 2016

18 82Tuesday, August 16, 2016

1.0

1.0

1.0

5

4

3

2

1

DMI_CTX_PRX_N0<7>
DMI_CTX_PRX_P0<7>

DMI_CRX_PTX_N0<7>

D D

C C

L A N

W L A N

DMI_CRX_PTX_P0<7>
DMI_CTX_PRX_N1<7>
DMI_CTX_PRX_P1<7>

DMI_CRX_PTX_N1<7>

DMI_CRX_PTX_P1<7>
DMI_CTX_PRX_N2<7>
DMI_CTX_PRX_P2<7>

DMI_CRX_PTX_N2<7>

DMI_CRX_PTX_P2<7>
DMI_CTX_PRX_N3<7>
DMI_CTX_PRX_P3<7>

DMI_CRX_PTX_N3<7>

DMI_CRX_PTX_P3<7>

1 2

RH193 100_0402_1%

PCIE_PRX_DTX_N5<30>
PCIE_PRX_DTX_P5<30>

PCIE_PTX_DRX_N5<30>
PCIE_PTX_DRX_P5<30>

PCIE_PRX_DTX_N6<28>
PCIE_PRX_DTX_P6<28>

PCIE_PTX_DRX_N6<28>
PCIE_PTX_DRX_P6<28>

DMI_CTX_PRX_N0
DMI_CTX_PRX_P0
DMI_CRX_PTX_N0
DMI_CRX_PTX_P0
DMI_CTX_PRX_N1
DMI_CTX_PRX_P1
DMI_CRX_PTX_N1
DMI_CRX_PTX_P1
DMI_CTX_PRX_N2
DMI_CTX_PRX_P2
DMI_CRX_PTX_N2
DMI_CRX_PTX_P2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
DMI_CRX_PTX_N3
DMI_CRX_PTX_P3

PCIECOMP#
PCIECOMP

PCIE_PRX_DTX_N5

PCIE_PRX_DTX_P5

PCIE_PTX_DRX_N5

PCIE_PTX_DRX_P5

PCIE_PRX_DTX_N6

PCIE_PRX_DTX_P6

PCIE_PTX_DRX_N6

PCIE_PTX_DRX_P6

UH1B

L27

DMI_RXN0

N27

DMI_RXP0

C27

DMI_TXN0

B27

DMI_TXP0

E24

DMI_RXN1

G24

DMI_RXP1

B28

DMI_TXN1

A28

DMI_TXP1

G27

DMI_RXN2

E26

DMI_RXP2

B29

DMI_TXN2

C29

DMI_TXP2

L29

DMI_RXN3

K29

DMI_RXP3

B30

DMI_TXN3

A30

DMI_TXP3

B18

PCIE_RCOMPN

C17

PCIE_RCOMPP

H15

PCIE1_RXN/USB3_7_RXN

G15

PCIE1_RXP/USB3_7_RXP

A16

PCIE1_TXN/USB3_7_TXN

B16

PCIE1_TXP/USB3_7_TXP

B19

PCIE2_TXN/USB3_8_TXN

C19

PCIE2_TXP/USB3_8_TXP

E17

PCIE2_RXN/USB3_8_RXN

G17

PCIE2_RXP/USB3_8_RXP

L17

PCIE3_RXN/USB3_9_RXN

K17

PCIE3_RXP/USB3_9_RXP

B20

PCIE3_TXN/USB3_9_TXN

C20

PCIE3_TXP/USB3_9_TXP

E20

PCIE4_RXN/USB3_10_RXN

G19

PCIE4_RXP/USB3_10_RXP

B21

PCIE4_TXN/USB3_10_TXN

A21

PCIE4_TXP/USB3_10_TXP

K19

PCIE5_RXN

L19

PCIE5_RXP

D22

PCIE5_TXN

C22

PCIE5_TXP

G22

PCIE6_RXN

E22

PCIE6_RXP

B22

PCIE6_TXN

A23

PCIE6_TXP

L22

PCIE7_RXN

K22

PCIE7_RXP

C23

PCIE7_TXN

B23

PCIE7_TXP

K24

PCIE8_RXN

L24

PCIE8_RXP

C24

PCIE8_TXN

B24

PCIE8_TXP

SKL-H-PCH_BGA837

@

SPT-H_PCH

DMI

USB 2.0

USB2N_10
USB2P_10
USB2N_11
USB2P_11

PCIe/USB 3

2 OF 12 REV = 1.3

USB2N_12
USB2P_12
USB2N_13
USB2P_13
USB2N_14
USB2P_14

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_F15/USB2_OCB_4
GPP_F16/USB2_OCB_5
GPP_F17/USB2_OCB_6
GPP_F18/USB2_OCB_7

USB2_COMP

USB2_VBUSSENSE

RSVD_AB13

GPD7/RSVD

USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9

USB2_ID

USB20_N1

AF5
AG7
AD5
AD7
AG8
AG10
AE1
AE2
AC2
AC3
AF2
AF3
AB3
AB2
AL8
AL7
AA1
AA2
AJ8
AJ7
W2
W3
AD3
AD2
V2
V1
AJ11
AJ13

AD43
AD42
AD39
AC44
Y43
Y41
W44
W43

AG3
AD10
AB13
AG2

BD14

USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

USB2_COMP

USB20_N1 <35>
USB20_P1 <35>
USB20_N2 <35>
USB20_P2 <35>
USB20_N3 <41>
USB20_P3 <41>
USB20_N4 <37>
USB20_P4 <37>
USB20_N5 <28>
USB20_P5 <28>
USB20_N6 <25>
USB20_P6 <25>
USB20_N7 <25>
USB20_P7 <25>
USB20_N8 <36>
USB20_P8 <36>
USB20_N9 <34>
USB20_P9 <34>

USB_OC0# <35>
USB_OC1# <35>

1 2

RH109 113_0402_1%

1 2

RH580 1K_0402_5%

RH581

1 2

1K_0402_5%

J U S B 1 l e f t s i d e ( P o w e r S h a r e , D e b u g P o r t )
J I O r i g h t s i d e ( I O / B )
C a l d e r a
A l i e n F X / E L C

W L A N + B T
T o u c h s c r e e n

D i g i t a l c a m e r a

J U S B C 2 r i g h t s i d e ( T y p e C )
T o b i i ( 1 7 " o n l y )

USB_OC0#
USB_OC1#
USB_OC3#
USB_OC2#

USB2_COMP
50ohm single-ended and as short as possible

10K_8P4R_5%

4 5
3 6
2 7
1 8

RPH6

+3V_PCH

Spacing=15 mils
Max length= 1000 mils

UH1F

4

C11

USB3_1_TXN

B11

USB3_1_TXP

B7

USB3_1_RXN

A7

USB3_1_RXP

B12

USB3_2_TXN/SSIC_1_TXN

A12

USB3_2_TXP/SSIC_1_TXP

C8

USB3_2_RXN/SSIC_1_RXN

B8

USB3_2_RXP/SSIC_1_RXP

B15

USB3_6_TXN

C15

USB3_6_TXP

K15

USB3_6_RXN

K13

USB3_6_RXP

B14

USB3_5_TXN

C14

USB3_5_TXP

G13

USB3_5_RXN

H13

USB3_5_RXP

D13

USB3_3_TXP/SSIC_2_TXP

C13

USB3_3_TXN/SSIC_2_TXN

A9

USB3_3_RXP/SSIC_2_RXP

B10

USB3_3_RXN/SSIC_2_RXN

B13

USB3_4_TXP

A14

USB3_4_TXN

G11

USB3_4_RXP

E11

USB3_4_RXN

SKL-H-PCH_BGA837

@

USB3TN1<35>

B B

J U S B 1

J U S B C 2

J U S B C 2
C a l d e r a

J I O

A A

5

USB3TP1<35>

USB3RN1<35>

USB3RP1<35>

USB3TN2<36>
USB3TP2<36>

USB3RN2<36>

USB3RP2<36>

USB3TN5<36>
USB3TP5<36>

USB3RN5<36>

USB3RP5<36>

USB3TP3<41>
USB3TN3<41>

USB3RP3<41>

USB3RN3<41>

USB3TP4<35>

USB3TN4<35>
USB3RP4<35>

USB3RN4<35>

SPT-H_PCH

LPC/eSPI

USB

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

SATA

6 OF 12 REV = 1.3

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A10/CLKOUT_LPC1

GPP_G19/SMI#

GPP_G18/NMI#

GPP_E6/DEVSLP2
GPP_E5/DEVSLP1
GPP_E4/DEVSLP0
GPP_F9/DEVSLP7
GPP_F8/DEVSLP6
GPP_F7/DEVSLP5
GPP_F6/DEVSLP4
GPP_F5/DEVSLP3

AT22
AV22
AT19
BD16

LPC_FRAME#

BE16
BA17

SERIRQ

AW17

KB_RST#

AT17
BC18

BC17

RH89 22_0402_5%

AV19

M45
N43

AE45
AG43
AG42
AB39
AB36
AB43
AB42
AB41

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Issued Date

Issued Date

Issued Date

LPC_AD0 <43>
LPC_AD1 <43>
LPC_AD2 <43>
LPC_AD3 <43>

LPC_FRAME# <43>
SERIRQ <43>

KB_RST# <43>

12

DEVSLP1 <29>
DEVSLP0 <29>

DEVSLP4 <29>
DEVSLP3 <33>

CLK_PCI_LPC < 43>

Compal Secret Data

Compal Secret Data

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

SERIRQ

KB_RST#

1 2

RH111 10K_0402_5%~D

1 2

RH518 10K_0402_5%~D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

PCH (4/7) DMI,PCIE,USB,LPC

PCH (4/7) DMI,PCIE,USB,LPC

PCH (4/7) DMI,PCIE,USB,LPC

Document Number Re v

Document Number Re v

Document Number Re v

LA-D751P

LA-D751P

LA-D751P

+3VS

1

1.0

1.0

19 82Tuesday, August 16, 2016

19 82Tuesday, August 16, 2016

19 82Tuesday, August 16, 2016

1.0

5

4

3

2

nVidia GPU_ID

N17EG3

N17EG2

N17EG1

N17PG1

N17_ID1

H

H

L

L

N17_ID0

H

L

H

L

1

RH25

N17EG3@

S RES 1/20W 10K +-5% 0201

SD043100280

RH25

N17EG2@

RH27

N17EG3@

S RES 1/20W 10K +-5% 0201

SD043100280

RH28

N17EG2@

+3V_PCH +3V_PCH

D D

UH1K

AT29

GPP_B22/GSPI1_MOSI

AR29

GPP_B21/GSPI1_MISO

AV29

GPP_B20/GSPI1_CLK

BC27

GPP_B19/GSPI1_CS#

BD28

GPP_B18/GSPI0_MOSI

BD27

GPP_B17/GSPI0_MISO

AW27

GPP_B16/GSPI0_CLK

AR24

GPP_B15/GSPI0_CS#

AV44

GPP_C9/UART0_TXD

BA41

GPP_C8/UART0_RXD

AU44

GPP_C11/UART0_CTS#

AV43

GPP_C10/UART0_RTS#

AU41

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AT44

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AT43

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU43

GPP_C12/UART1_RXD/ISH_UART1_RXD

AN43

GPP_C23/UART2_CTS#

AN44

GPP_C22/UART2_RTS#

AR39

GPP_C21/UART2_TXD

AR45

GPP_C20/UART2_RXD

AR41

GPP_C19/I2C1_SCL

AR44

GPP_C18/I2C1_SDA

AR38

GPP_C17/I2C0_SCL

AT42

GPP_C16/I2C0_SDA

AM44

GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA

AJ44

GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL

SKL-H-PCH_BGA837

@

JWDB

1

1

2

2

3

3

G1

4

4

G2

ACES_88266-04001

CONN@

BBS_BIT0

EC_SCI#
VROM_SEL

NRB_BIT

WL_OFF#
BT_OFF#

UART_2_CCTS_DRTS
UART_2_CTXD_DRXD
UART_2_CRXD_DTXD

DGPU_PWROK

5
6

+3VS

1 2

RH517 8.2K_0402_5%@

1 2

RH520 8.2K_0402_5%@

1 2

RH521 10K_0402_5%

RC62 49.9K_0402_1%

RC63 49.9K_0402_1%

RC65 49.9K_0402_1%@

RH516 10K_0402_5%

RH588 10K_0402_5%@

C C

B B

RH589 10K_0402_5%@

1 2

1 2

1 2

12

12

12

BT_OFF#

WL_OFF#

EC_SCI#

UART_2_CRXD_DTXD

UART_2_CTXD_DRXD

UART_2_CCTS_DRTS

DGPU_PWROK

VROM_SEL

VROM_SEL

UART_2_CTXD_DRXD
UART_2_CRXD_DTXD

EC_SCI#<43>

VROM_SEL<51>

GC6_FB_EN<43,46>

GC6_EVENT#<46>

EDP_SW<24,43>

WL_OFF#<28>

BT_OFF#<28>

HDMI_HPD_PCH<27>

DP_HPD_PCH<26>

EDP_MUX_PD<24>

TBT_CIO_PLUG_EVENT#<56>

RTD3_USB_PWR_EN<56>
RTD3_CIO_PWR_EN<56>

DGPU_PWROK<43>

+5VALW

SPT-H_PCH

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA

11 OF 12 REV = 1.3

BOARD_ID

CPU_ID N17_ID0

GPP_D16/ISH_UART0_CTS#
GPP_D15/ISH_UART0_RTS#

GPP_H20/ISH_I2C0_SCL
GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL
GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
GPP_A20/ISH_GP2
GPP_A19/ISH_GP1
GPP_A18/ISH_GP0
GPP_A17/ISH_GP7

1 2

RH21 10K_0201_5%NV@

1 2

RH22 10K_0201_5%

AMD@

1 2

RH23 10K_0201_5%SKL@

1 2

RH24 10K_0201_5%

KBL@

BOARD_ID

AL44

GPP_D9
GPP_D10
GPP_D11
GPP_D12

AL36
AL35
AJ39

AJ43
AL43
AK44
AK45

BC38
BB38

BD38
BE39

BC22
BD18
BE21
BD22
BD21
BB22
BC19

DGPU_HOLD_RST#
CPU_ID
DGPU_PWR_EN

N17_ID1
N17_ID0

GSYNC_ID

CLKDET#
DGPU_PRSNT#

N17_ID1

GSYNC_ID

DGPU_HOLD_RST# <46>

DGPU_PWR_EN <43,49>

XMP2 <64>
XMP1 <64>

RH135
10K_0402_5%

1 2

1 2

RH25 10K_0201_5%@

1 2

RH26 10K_0201_5%@

1 2

RH27 10K_0201_5%@

1 2

RH28 10K_0201_5%@

1 2

RH29 10K_0201_5%GSYNC@

1 2

RH30 10K_0201_5%

NGSYNC@

DGPU_PWR_EN

CLKDET#

+3V_PCH

RH130 4.7K_0402_5%~D@

+3V_PCH

RH524 4.7K_0402_5%~D@

Boot BIOS Strap Bit (inter nal PD)

HIGH
LOW(DEFAULT)

S RES 1/20W 10K +-5% 0201

SD043100280

RH26

S RES 1/20W 10K +-5% 0201

SD043100280

RH26

S RES 1/20W 10K +-5% 0201

SD043100280

1 2

RH537 10K_0201_5%

1 2

RH558 10K_0201_5%@

1 2

LPC
SPI

1 2

N17EG1@

N17PG1@

+3VS

+3V_PCH

BBS_BIT0

NRB_BIT

S RES 1/20W 10K +-5% 0201

SD043100280

RH27

N17EG1@

S RES 1/20W 10K +-5% 0201

SD043100280

RH28

N17PG1@

S RES 1/20W 10K +-5% 0201

SD043100280

NO REBOOT mode ( internal PD)

HIGH
LOW(DEFAULT)

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Enable
Disa ble

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

PCH (5/7) I2C,GPIO

PCH (5/7) I2C,GPIO

PCH (5/7) I2C,GPIO

Document Number Re v

Document Number Re v

Document Number Re v

LA-D751P

LA-D751P

LA-D751P

1

20 82Tuesday, August 16, 2016

20 82Tuesday, August 16, 2016

20 82Tuesday, August 16, 2016

1.0

1.0

1.0

5

4

3

2

1

+1VALW

@

D D

C C

JP1

1 2

PAD-OPEN 43x39

1 2

RH12 0_0805_5%

+1V_PCH+1VALW

+1V_MPHY

+3VALW

+1V_PCH

+3V_PCH

+1V_PCH_PRIM

+1V_MPHY

+1V_PCH

@

JP2

1 2

PAD-OPEN 43x39

1 2

RH196
0_0402_5%

@

RH6
0_0603_5%

RF@

1 2

RH7
0_0603_5%

RF@

1 2

0.1U_0402_10V7K

@RF@

+1V_VCCDSW

+1V_MPHY

CH4

1

2

+1V_PCH_PRIM

1

CH3

0.1U_0402_10V7K

@RF@

2

AA23
AA26
AA28
AC23
AC26
AC28
AE23
AE26

BA29

AC17

AN19
BA15

Y23
Y25

N17
R19
U20

V17

R17

K2
K3

U21
U23
U25
U26

V26
A43

B43
C44
C45

V28

AJ5

AL5

W15

UH1H

VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
DCPDSW_1P0

VCCCLK1
VCCCLK3
VCCCLK4
VCCCLK2
VCCCLK2

VCCCLK5
VCCCLK5

VCCMPHY_1P0
VCCMPHY_1P0
VCCMPHY_1P0
VCCMPHY_1P0
VCCMPHY_1P0
VCCMPHYPLL_1P0
VCCMPHYPLL_1P0
VCCPCIE3PLL_1P0
VCCPCIE3PLL_1P0

VCCAPLLEBB_1P0
VCCPRIM_1P0
VCCUSB2PLL_1P0
VCCUSB2PLL_1P0
VCCHDAPLL_1P0
VCCHDA

VCCDSW_3P3

SKL-H-PCH_BGA837

@

SPT-H_PCH

CORE

MPHY

USB

VCCGPI O

VCCPRIM_1P0

VCCDSW_3P3

VCCPGPPA
VCCPGPPBCH
VCCPGPPBCH

VCCPGPPEF
VCCPGPPEF

VCCPGPPG
VCCPRIM_3P3

VCCPRIM_1P0

VCCATS

VCCRTCPRIM_3P3

VCCRTC
DCPRTC

VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0

VCCSPI
VCCSPI
VCCSPI

VCCPGPPD

VCCPGPPD

VCCPGPPD

VCCPGPPD

VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3

REV = 1.38 OF 12

AL22

BA24

BA31
BC42
BD40
AJ41
AL41
AD41
AN5

AD15
AD13
BA20
BA22
BA26

1 2

CH70 0.1U_0402_10V7K

AJ20
AJ21
AJ23
AJ25

BE41
BE43
BE42

BC44
BA45
BC45
BB45

BD3
BE3
BE4

+1V_PCH

+1V_PCH

+RTC_CELL

+3VALW

+3VS

+1V_PCH_PRIM

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

Close to V28 < 100milClose to BA15 < 100mil

+1V_VCCDSW

1

2

+1V_PCH

1U_0402_6.3V6K~D

CH176

1U_0402_6.3V6K~D

CH185

1

2

+3V_PCH

0.1U_0402_10V7K

CH200

1

2

+3V_PCH +3V_PCH

0.1U_0402_10V7K

1

CH189

2

Close to BA29 Close to AC17 Close to BA15 Close to AN5 Close to AD13

+3VS

+3VALW

1U_0402_6.3V6K~D

CH188

1

2

1U_0402_6.3V6K~D

CH82

1

2

Close to W15

0.1U_0402_10V7K

1

CH190

2

Close to AD41 Close to BC42,BD40

+3V_PCH

0.1U_0402_10V7K

1

CH192

2

B B

A A

+1V_PCH

5

22U_0805_6.3V6M~D

1

2

1U_0402_6.3V6K~D

22U_0805_6.3V6M~D

1

1

CH177

CH178

2

2

+1V_MPHY +1V_MPHY

22U_0805_6.3V6M~D

CH179

22U_0805_6.3V6M~D

1

1

CH181

2

2

Close to A43,B43Close to K2,K3

+3V_PCH

1U_0402_6.3V6K~D

CH180

1

CH182

2

22U_0805_6.3V6M~D

1U_0402_6.3V6K~D

CH183

1

1

CH184

2

2

1U_0402_6.3V6K~D

0.1U_0402_10V7K

CH187

1

1

CH186

2

2

Close to BA20

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+RTC_CELL

1U_0402_6.3V6K~D

0.1U_0402_10V7K

CH80

1

1

CH173

2

2

Close to BA22Close to U21,U23,U25,U26,V26

Compal Secret Data

Compal Secret Data

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

+3V_PCH

0.1U_0402_10V7K

1

2

Close to AJ41,AL41

Deciphered Date

Deciphered Date

Deciphered Date

2

CH191

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

PCH (6/7) PWR

PCH (6/7) PWR

PCH (6/7) PWR

Document Number Re v

Document Number Re v

Document Number Re v

LA-D751P

LA-D751P

LA-D751P

1

21 82Tuesday, August 16, 2016

21 82Tuesday, August 16, 2016

21 82Tuesday, August 16, 2016

1.0

1.0

1.0

5

4

3

2

1

D D

UH1I

SPT-H_PCH

AC18

VSS

AN4

VSS

AN10

VSS

BE14

VSS

BE18

VSS

BE23

VSS

BE28

VSS

BE32

VSS

BE37

VSS

BE40

VSS

BE9

VSS

C10

VSS

C2

VSS

C28

VSS

C37

VSS

J7

VSS

K10

VSS

K27

VSS

K33

VSS

K36

VSS

K4

VSS

K42

VSS

K43

VSS

L12

VSS

L13

VSS

L15

VSS

L4

C C

B B

VSS

L41

VSS

L8

VSS

M35

VSS

M42

VSS

N10

VSS

N15

VSS

N19

VSS

N22

VSS

N24

VSS

N35

VSS

N36

VSS

N4

VSS

N41

VSS

N5

VSS

P17

VSS

P19

VSS

P22

VSS

P45

VSS

R10

VSS

R14

VSS

R22

VSS

R29

VSS

R33

VSS

R38

VSS

R5

VSS

T1

VSS

T2

VSS

T4

VSS

Y18

VSS

Y20

VSS

Y21

VSS

Y26

VSS

Y28

VSS

Y29

VSS

A18

VSS

A25

VSS

A32

VSS

A37

VSS

AA17

VSS

AA18

VSS

AA20

VSS

AA21

VSS

AA25

VSS

AA29

VSS

AA4

VSS

AA42

VSS

AB10

VSS

SKL-H-PCH_BGA837

@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AR5
AR7
U15
AL4
AE29
AE4
AE42
AF18
AF20
AF21
AF23
AF25
AF26
AF28
AF29
AG11
AG13
AG31
AG32
AG33
AG38
AG4
AH1
AH17
AH18
AH20
AH21
AH23
AH25
AH26
AH28
AH29
AH45
AJ10
AJ14
AJ15
AJ17
AJ18
AJ26
AJ28
AJ29
AJ31
AJ32
AJ36
AK4
AK42
AU7
AV17
AV24
AV27
AV31
AV33
AV6
AW13
AW19
AW29
AW37
AW9
AY38
AY45
B25
B3
B37
B40
B6
BA1
BB11
BB16
BB21
BB25
BB30
BB34
BC2
BD43

REV = 1.3

UH1L

C42

VSS

D10

VSS

D12

VSS

D15

VSS

D16

VSS

D17

VSS

D19

VSS

D21

VSS

D24

VSS

D25

VSS

D27

VSS

D29

VSS

D30

VSS

D31

VSS

D33

VSS

D35

VSS

D36

VSS

E13

VSS

E15

VSS

E31

VSS

E33

VSS

F44

VSS

F8

VSS

G42

VSS

G9

VSS

H17

VSS

H19

VSS

H22

VSS

H24

VSS

H27

VSS

H29

VSS

H3

VSS

H35

VSS

J10

VSS

J11

VSS

J3

VSS

J39

VSS

J5

VSS

T42

VSS

U10

VSS

U11

VSS

U14

VSS

U17

VSS

U18

VSS

U28

VSS

U29

VSS

U31

VSS

U32

VSS

U33

VSS

U38

VSS

U4

VSS

U8

VSS

V18

VSS

V20

VSS

V21

VSS

V23

VSS

V25

VSS

V29

VSS

V3

VSS

V45

VSS

W14

VSS

W31

VSS

W32

VSS

W33

VSS

W38

VSS

W4

VSS

W8

VSS

Y17

VSS

SKL-H-PCH_BGA837

@

SPT-H_PCH

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

REV = 1.3

AB11
AB7
AB14
AB31
AB32
AB38
AB4
AB5
AC1
AC20
AC21
AC25
AC29
AC45
AB8
AD11
AD14
AB15
AD32
AD33
AD36
AD4
AD8
AE18
AE20
AE21
AE25
AE28
AL10
AL11
AL13
AL17
AL19
AL24
AL29
AL32
AL33
AL38
AM15
AM17
AM19
AM22
AM24
AM27
AM29
AM45
AN11
AN22
AN27
AN31
AN39
AN7
AN8
AP11
AP4
AR33
AR34
AR42
AR9
AT10
AT15
AT36
AT9
AU1
AU35
AU36
AU39
AU45
C4

UH1J

BD2

VSS

BD45

VSS

BD44

VSS

BE44

VSS

D45

VSS

A42

VSS

B45

VSS

B44

VSS

A4

VSS

A3

VSS

B2

VSS

A2

VSS

B1

VSS

BB1

VSS

BC1

VSS

A44

VSS

C1

RSVD

D1

RSVD

SKL-H-PCH_BGA837

@

SPT-H_PCH

RSVD
RSVD
RSVD

RSVD
RSVD

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

PREQ#
PRDY#

CPU_TRST#

PCH_TRIGOUT

PCH_TRIGIN

REV = 1.3

AR22
W13
U13

P31
N31

P27
R27
N29
P29
AN29
R24
P24

AT3
AT4
AY5
AL2
AK1

XDP_PREQ# <6,9>
XDP_PRDY# <6,9>
CPU_XDP_TRST# <6,9>
PCH_TRIGGER <10>
CPU_TRIGGER <10>

A A

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (7/7) VSS

PCH (7/7) VSS

PCH (7/7) VSS

LA-D751P

LA-D751P

LA-D751P

1

1.0

1.0

22 82Tuesday, August 16, 2016

22 82Tuesday, August 16, 2016

22 82Tuesday, August 16, 2016

1.0

5

D D

C C

4

3

2

1

B B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R e v

Size Document Number R e v

Size Document Number R e v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

Reversed

Reversed

Reversed

LA-D751P

LA-D751P

LA-D751P

1

23 82Tuesday, August 16, 2016

23 82Tuesday, August 16, 2016

23 82Tuesday, August 16, 2016

1.0

1.0

1.0

5

D D

+3VS

Automat i c E Q di s abl e; I nt er nal pull do wn at ~150K Ω, 3. 3V I /O.
L: Automat i c E Q enabl e ( def ault)
H: Automat ic E Q di sa bl e

SML0CLK<18,41>
SML0DATA<18,41>

GPU_TX0P<47>
GPU_TX0N<47>
GPU_TX1P<47>
GPU_TX1N<47>

C C

G P U

C P U

+3VS

RV629

4.7K_0402_1%

1 2

IN1_PEQ#

12

RV628

4.7K_0402_1%

B B

+3VS

RV631

4.7K_0402_1%

1 2

IN2_PEQ#

12

RV630

4.7K_0402_1%

GPU_TX2P<47>
GPU_TX2N<47>
GPU_TX3P<47>
GPU_TX3N<47>

GPU_AUXP/DDC<47>
GPU_AUXN/DDC<47>

12
12

CPU_EDP_TX0P< 7>
CPU_EDP_TX0N<7>
CPU_EDP_TX1P< 7>
CPU_EDP_TX1N<7>
CPU_EDP_TX2P< 7>
CPU_EDP_TX2N<7>
CPU_EDP_TX3P< 7>
CPU_EDP_TX3N<7>

CPU_EDP_AUX<7>
CPU_EDP_AUX#<7>

Mount RV628,RV630 for vendor's recommend
M : LLEQ @01/11

Programmable input equalizat i on l evel s; I nt ernal pull do wn at ~150K Ω, 3. 3V I /O.
L: default, LEQ, compensate channel loss up to 11.5dB @ HBR2
H: HEQ, compensate channel loss up to 14.5dB @ HBR2
M: LLEQ, compensate channel loss up to 8.5dB @ HBR2

1

CV437

0.1U_0402_16V4Z

2

RV632 0_0402_5%@
RV633 0_0402_5%@
RV634 4.7K_0402_1%

+3VS

RV669100K_0201_1% NV@
RV670100K_0201_1% NV@

RV635 4.7K_0402_1%

0.1U_0402_16V4Z

DGPU_INV_PWM<46>
IGPU_INV_PWM<16>
DGPU_ENVDD<46>
IGPU_ENVDD<16>
DGPU_ENBKL<46>
IGPU_ENBKL<16>

1 2
1 2
1 2
1 2

EDP_HPD_GPU<46>
EDP_HPD_CPU<16>

CV484

12
12
12
12
12
12
12
12

12
12

12
12
12
12
12
12
12
12

12
12

+5VS

1

2

1

CV436

0.1U_0402_16V4Z

2

CV4160.1U_0201_6.3V6K
CV4170.1U_0201_6.3V6K
CV4180.1U_0201_6.3V6K
CV4190.1U_0201_6.3V6K
CV4200.1U_0201_6.3V6K
CV4210.1U_0201_6.3V6K
CV4220.1U_0201_6.3V6K
CV4230.1U_0201_6.3V6K

CV4240.1U_0201_6.3V6K
CV4250.1U_0201_6.3V6K

CV4260.1U_0201_6.3V6K
CV4270.1U_0201_6.3V6K
CV4280.1U_0201_6.3V6K
CV4290.1U_0201_6.3V6K
CV4300.1U_0201_6.3V6K
CV4310.1U_0201_6.3V6K
CV4320.1U_0201_6.3V6K
CV4330.1U_0201_6.3V6K

CV4340.1U_0201_6.3V6K
CV4350.1U_0201_6.3V6K

4

IN2_PEQ#
IN1_PEQ#

GPU_TX0P_C
GPU_TX0N_C
GPU_TX1P_C
GPU_TX1N_C
GPU_TX2P_C
GPU_TX2N_C
GPU_TX3P_C
GPU_TX3N_C

GPU_AUXP/DDC_C
GPU_AUXN/DDC_C

CPU_EDP_P0_C
CPU_EDP_N0_C
CPU_EDP_P1_C
CPU_EDP_N1_C
CPU_EDP_P2_C
CPU_EDP_N2_C
CPU_EDP_P3_C
CPU_EDP_N3_C

CPU_EDP_AUX_C
CPU_EDP_AUX#_C

UV22

16

Vcc

1A

2

1B1

2A

3

1B2

3A

5

2B1

4A

6

2B2

11

3B1

OE#

10

S

3B2

14

4B1

13

GND

4B2

SN74CBT3257CPWR_TSSOP16

UV21

21

VDD33

26

VDD33

35

VDD33

49

VDD33

60

VDD33

51

IN2_PEQ/ SCL_CTL

52

IN1_PEQ/ SDA_CTL

59

IN1_AEQ#

58

IN2_AEQ#

1

IN1_D0p

2

IN1_D0n

4

IN1_D1p

5

IN1_D1n

6

IN1_D2p

7

IN1_D2n

9

IN1_D3p

10

IN1_D3n

28

IN1_AUXp

27

IN1_AUXn

23

IN1_SCL

22

IN1_SDA

11

IN2_D0p

12

IN2_D0n

14

IN2_D1p

15

IN2_D1n

16

IN2_D2p

17

IN2_D2n

19

IN2_D3p

20

IN2_D3n

30

IN2_AUXp

29

IN2_AUXn

25

IN2_SCL

24

IN2_SDA

3

IN1_HPD

13

IN2_HPD

PS8331BQFN60GTR-A2 QFN

SA000060U10

4
7
9
12

15
1

8

OUT_AUXp_S CL
OUT_AUXn_S DA

INV_PWM <25>
ENVDD <25>
ENBKL <43>

EDP_SW

I2C_CTL_EN

CA_DET

OUT_D0p
OUT_D0n
OUT_D1p

OUT_D1n
OUT2_D2p
OUT2_D2n

OUT_D3p

OUT_D3n

OUT_HPD

REXT
CEXT

Epad

+3VS

1 2

32
31

53

56

PI0

38

PC0

55

PC1

48

46
45
43
42
40
39
37
36

54

SW

44

34
47

8

GND

18

GND

33

GND

41

GND

57

GND

61
50

PD

RV659
10K_0402_5%

I2C_CTL_EN

PI0
PC0
PC1

EDP_SW

1 2

1

2

3

+3VS

RV23
1M_0402_5%

12

RV26
499_0402_1%

@

CV439
1U_0402_6.3V6K

@

EDP_SW <20,43>

12

RV19
100K_0402_5%

12

RV20
100K_0402_5%

1

CV438

2.2U_0402_6.3V6M

2

+3VS

D

S

MUX_EDP_AUXN <25>
MUX_EDP_AUXP <25>

MUX_EDP_A0P <25>
MUX_EDP_A0N <25>
MUX_EDP_A1P <25>
MUX_EDP_A1N <25>
MUX_EDP_A2P <25>
MUX_EDP_A2N <25>
MUX_EDP_A3P <25>
MUX_EDP_A3N <25>

EDP_HPD <16,25,46>

12

RV24

4.99K_0402_1%

RV25
10K_0402_5%

@

1 2

13

2

G

QV95
SSM3K7002FU_SC70-3~D

@

T o e D P c o n n e c t o r

+3VS

RV658
10K_0402_5%

@

1 2

EDP_MUX_PD <20>

2

+3VS

RV21

4.7K_0402_1%

@

I2C_CTL_EN

PI0

Port switching control conf i gura t i on; I nterna l pul l d own
at ~150KΩ , 3.3 V I / O.
L: Input Port1 is selected (default)
H: I nput Port2 is selected

+3VS

RV625

4.7K_0402_1%

@

PC0

PC1

1 2

12

+3VS

1 2

12

RV624

4.7K_0402_1%

@

RV627

4.7K_0402_1%

@

RV626

4.7K_0402_1%

@

1 2

12

RV22

4.7K_0402_1%

+3VS

RV623

4.7K_0402_1%

@

1 2

12

RV622

4.7K_0402_1%

@

AUX intercept i on dis abl e f or Port y (y = 1, 2). I nter nal pull do wn at ~150K Ω, 3. 3V I /O;
L: AUX intercept i on enabl e, dri ver conf i gurat i on is set by l i nk tr ai ni ng (default)
H: AUX intercept i on di sabl e, dri v er out put wi t h f i xed 80 0mV and 0dB
M: AUX intercept i on di sabl e, dri v er out put wi t h f i xed 40 0mV and 0dB

Output swing adjustment for Port y (y = 1, 2). Internal pull down a t ~150KΩ , 3. 3 V I / O;
L: default
H: +20%
M: -16.7%

I2C Control Enable; Internal pull down at ~150KΩ , 3. 3 V I/ O.
H: I2C control is selected with default address 0x66/67
M: I2C control is selected with alternat i ve address 0xD8/D9

Auto test enable; Internal pull down at ~150KΩ , 3. 3V I / O.
L: Auto test disable & input of fs et c ancell at i on enabl e ( def aul t)
H: A uto test enable & input of fs et c ancell at i on enable
M: Auto test disable & input of f set cancell at i on di s able

1

A A

S1 OE output

X H

5

A=B1

A=B2

functi on

DGPU

IGPULLLH

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Date: Shee t o f

Date: Shee t o f

Date: Shee t o f

Compal Electronics, Inc.

eDP MUX PS8331B

eDP MUX PS8331B

eDP MUX PS8331B

LA-D751P

LA-D751P

LA-D751P

1

24 82Tuesday, August 16, 2016

24 82Tuesday, August 16, 2016

24 82Tuesday, August 16, 2016

1.0

1.0

1.0

A

B

C

D

E

1 1

2 2

3 3

+3VS

UV17

RV600
100K_0201_5%

1 2

5

IN

4

EN

SY6288C20AAC_SOT23-5

10P_0402_50V8J

12

ENVDD<24>

CV5

CV372

@RF@

1

2

USB20_P7<19>

USB20_N7<19>

USB20_N6<19>

USB20_P6<19>

W=60 mils W=60 mils

4.7U_0805_10V4Z

1

OUT

2

GND

3

OC

LV2

1 2

MCM1012B900F06BP_4P

EMI@

USB20_N6

USB20_P6

2

3

DV2
PESD5V0U2BT_SOT23-3

@ESD@

1

1 2

RV45
10K_0402_5%

34

+3VS

USB20_CAM_P7_R

USB20_CAM_N7_R

3

DV4

223

AZC199-02SPR7G_SOT23-3

@ESD@

1

1

1

2

LCD backlight power control

B+

6
5
2

S

D

1

W=60 mils

CV15

1000P_0402_50V7K

1

2

4 4

EN_INVPWR<43>

A

2

G

4

RV9

100K_0402_5%

12

PWR_SRC_ON

12

RV12
100K_0402_5%

13

D

QV2
2N7002W-T/R7_SOT323-3

S

G

QV1

3

SI3457CDV-T1-GE3_TSOP6

+INV_PWR_SRC

W=60 mils

B

0.1U_0402_10V7K

CV9

1

2

1

CV14

0.1U_0603_25V7K

2

4.7U_0805_10V4Z

+LCDVDD

CV10

10P_0402_50V8J

CV373

@RF@

12

MUX_EDP_A0P<24>
MUX_EDP_A0N<24>

MUX_EDP_A1P<24>
MUX_EDP_A1N<24>

MUX_EDP_A2P<24>

F r o m e D P M U X

MIC_CLK<31>

RV13

0_0402_5%

@EMI@

CV374

10P_0402_50V8J

@RF@

12

12

BKOFF#<43>

INV_PWM<24>

MUX_EDP_A2N<24>

MUX_EDP_A3P<24>
MUX_EDP_A3N<24>

MUX_EDP_AUXP<24>
MUX_EDP_AUXN<24>

RV8

100K_0201_5%

12

DV1
RB751V-40_SOD323-2

EDP_HPD<16,24,46>

G-SYNC#<46>
MIC_DATA<31>

+3VS_CAM

+LCDVDD

DET<16>

LCD_TEST<43>

+3VS_CAM

+VDD_TOUCH

TS_EN<43>

12

12

RV1
10K_0201_5%

+INV_PWR_SRC

DISPOFF#

EDP_TX0_C

12

CV10.1U_0201_6.3V6K

EDP_TX0#_C

12

CV20.1U_0201_6.3V6K

EDP_TX1_C

12

CV30.1U_0201_6.3V6K

EDP_TX1#_C

12

CV40.1U_0201_6.3V6K

EDP_TX2_C

12

CV80.1U_0201_6.3V6K

EDP_TX2#_C

12

CV60.1U_0201_6.3V6K

EDP_TX3_C

12

CV70.1U_0201_6.3V6K

EDP_TX3#_C

12

CV110.1U_0201_6.3V6K

EDP_AUX_C

12

CV120.1U_0201_6.3V6K

EDP_AUX#_C

12

CV130.1U_0201_6.3V6K

USB20_N6
USB20_P6
USB20_CAM_N7_R
USB20_CAM_P7_R

G-SYNC#
MIC_DATA

MIC_CLK

W=60 mils

DET

TS_EN
DISPOFF#

INV_PWM

W=60 mils

12

CV375
10P_0402_50V8J

@RF@

Touch screen panel power

+VDD_TOUCH+3VS

1 2

@

4.7U_0805_10V4Z

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

+3VS +3VS_CAM

C

1

CV21

RV81
0_0402_5%

1

CV19

0.1U_0402_10V7K

2

Camera power

1 2

@

RV47
0_0402_5%

Compal Secret Data

Compal Secret Data

2016/01/06 2017/01/06

2016/01/06 2017/01/06

2016/01/06 2017/01/06

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Place close to JEDP

+LCDVDD

0.1U_0402_10V7K

CV17

10U_0603_6.3V6M

CV18

1

1

2

2

Title

Title

Title

eDP/Camera/TS

eDP/Camera/TS

eDP/Camera/TS

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

LA-D751P

LA-D751P

LA-D751P

Date: Sheet of

Date: Sheet of

Date: Sheet of

eDP connector

JEDP

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

41

GND

42

GND

43

GND

44

GND

ACES_50473-0400M-P01

CONN@

IR camera pindef i ne :

IR_LED+
IR_LED+
IR_LED+/NC
IR_LED-/DET , connect to PCH GPIO
IR_LED­IR_LED­Diglog_loop , connect to PCH GPIO
DGND
D+
D­USB3V3
MIC_SIG
MIC_CLK
DGND

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

25 82Tuesday, August 16, 2016

25 82Tuesday, August 16, 2016

E

25 82Tuesday, August 16, 2016

1.0

1.0

1.0

LCD power control