Compal LA-D707P Schematic

1 1

2 2

Kabylake-U M/B Schematics Document

Intel ULV Processor with DDR4 SODIMMx2

Date : 2016/05/11

3 3

Project :

4 4

Version : 0.2

(PV phase)

Diner_Crepe1.1(15")

BDL50 : LA-D707P

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTYOF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTYOF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANYTHIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANYTHIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/29 2011/06/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet o f

Compal Electronics, Inc.

Cover Page

Document Number Re v

Cover Page

LA-D707P

1 60Wednesday, May 11, 2016

v0.2

Compal Confidential

Model Name : File Name :

1 1

2 2

3 3

iner_Crepe1.1(15")

LA-D707P

VRAM g

DDR3 x4pcs

25 6Mb x 16 ( 4Gb ) 51 2Mb x 16 ( 8Gb )

JL VD S1

eDP/LVDS

CONN

P. 20

FHD

CRT CONN

HDMI CONN

1Ch 64bits 1.5V

P. 4 0 ~42

P. 22

CRT

JH DM I1

HDMI

P. 21

NGFF WLAN+BT

(Key E)

AMD

R16M-M1-70 D3(R7) R16M-M1-30 D3(R5)

P. 36 ~40

LVDS @

U T1

eDP to LVDS Transmitter

RTD2132N

eDP@

P. 19

U 41 04JC RT 1

DP to VGA Transmitter

RTD2168

LAN

RT L8 111 HS H (G iga ) RT L8 166 EH( 1 0 / 10 0 )

JW LAN 1

P. 32

P. 22

UL 1

P. 23

U 66 6

PCIex4

Port #1~#4

PCIe 2.0:5Gb/s PCIe 3.0:8Gb/s

eDP

2.7Gb/s

eDPx2Lane

2.7Gb/s

DDI

x2Lane

DDI

x4Lane

297MHz

Port #5

PCIex1

PCIe Gen1:2.5Gb/s PCIe Gen2:5Gb/s

Port #6

PCIex1

PCIe 1.0:2.5Gb/s PCIe 2.0:5Gb/s

x1Lane

Port 2

Port 1

SMbus

1MHz

Kabylake-U

Skylake-U

1356P BGA

KBL-U 15W 2+2

SKL-U 15W 2+2

U C1

GEN1 1.5Gb/s GEN2 3Gb/s GEN3 6Gb/s

ual Channel

DDR4 2133MHz 1.2V

SATA 3.0

USB3.0

5Gb/s

USB2.0 480Mb/s

Interleaved

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

DDR4-SO-DIMM X 2

2.5" SATA HDD

ODD

USB3.0 port

(onboard-1)

USB2.0 port

(onboard-2)

USB2.0 Port

(sub board)

Bluetooth

Camera

Touch Screen

Card reader RTS5141

(sub board)

J H D D

P. 30

JO D D

P. 30

JU SB 1

P. 31

JU SB 2

P. 31

JI O1

P. 33

JW LAN 1

P. 32

JL VD S1

P. 20

JL VD S1

P. 20

JI O1

P. 33

P. 17 ~18

Port 1

U K 1

P. 2 6

TPM

P. 2 8

*default FWTPM

U 4

U C 2

P. 0 7

LPC 33MHz

SPI 50MHz

U A 1

24MHz

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/29 2011/06/29

HDA Aduio codec ALC3227

Compal Secret Data

Deciphered Date

P. 24

JS PK 1

Internal SPK

Combo Jack

J HP

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet of

Compal Electronics, Inc.

Block Diagrams

Document Number Re v

Block Diagrams

LA-D707P

v0.2

2 60Wednesday, May 11, 2016

v0.2

FAN

JK B 1

P. 2 7

J T P 1

PS2 HDA

EC ENE

KB 9 0 22Q D

P. 2 7

P. 3 4

JP W R

P. 3 3

U C 3

P. 1 0NC T 7 7 1 8 W

SL B 966 5 T T2. 0

SPI ROM 8MBytes

Int.KBD

TouchPad

Lid switch

(sub board)

4 4

Thermal sensor

AC Adapter 19.5V

P.45

D D

Charge

Charger BQ24725

+19.5VB

P.47

DC Battery 3S1P 4S1P

C C

P.46

Discharge

+2.5V_PG

SM_PG_CTRL

RT8243AZQW

ECON

Vin

Vout

+3VALW

PCH_PWR_EN

Vin

SY8032A

DC/DC (+5VALW/+3VALW)

Vout

+3VALW

PM_SLP_S4#

PGOOD

P.48

SPOK

Vout

Vin

EN S5

EN S3

DDR4 RT8027P

Vout

PGOOD

P.49

Vout

Vin

+1.0V_PRIM

+1.8V_PG +1.0V_VS_PG_PWR

SY8286

PGOOD

P.50

Vin

SY8032A

+0.6V_0.6VS

+1.2V_VDDQ

DDR_PWROK

+1.0V_PRIM

Vout

PGOOD

P.51

Vout

PGOOD

P.49

+1.8V_PRIM

+1.8V_PG

+2.5V

+2.5V_PG

CPU DC/DC NCP81206

INPUTS OUTPUTS

B+

SYSTEM DC/DC

T8243AZQW

INPUTS OUTPUTS

B+ +5VALW/+3VALW

SYSTEM DC/DC RT8207P / 8032

INPUTS OUTPUTS

B+

SYSTEM DC/DC SY8286

CC_SA VCC_GT VCC_VORE

+1.2V_VDDQ

+0.6V_0.6VS

INPUTS OUTPUTS

SYSTEM DC/DC SY8032A

INPUTS

+3VALW +1.8V_PRIM

SYSTEM DC/DC RT8880

+1.0V_PRIMB+

OUTPUTS

52~54

+2.5V

56~57

INPUTS OUTPUTS

Y8286

+VGA_CORE

B+

SYSTEM DC/DC S

INPUTS OUTPUTS

B+ +1.5VS_VGA

Vin

B B

VR_ON

NCP81206 DC/DC

VR_ON

(CPU_CORE)

Vout

PGOOD

Vout

+VCC_CORE

+VCC_GT

+VCC_SA

VR_PWRGD

P.52,53

Vin

RT8880

Vout

+VGA_CORE

DC/DC (VGA_CORE)

DGPU_PWR_EN

A A

DGPU_PWR_EN

Vin

SY8286 DC/DC (VGA_RAM)

PGOOD

P.56

Vout

PGOOD

P.55

GPU_PGD

+1.5VS_VGA

VRAM_PG

D D

0 ohm

CPU

PU801

+3VS

DGPU_PWR_EN

C C

GPIO78

U4103

1. +3VS_VGA

PU8

GPU_PWRGD

1.8V_PWRGD

DGPU_PWROK

GPIO77

PU801

NMOS

PXS_PWREN#

+1.05VS

B B

2. VGA_CORE

U4102

3. +1.05VS_VGA GPU_RST

GPU

0 ohm

DGPU_HOLD_RST#

PLT_RST#

CPU

GPIO80

4. +1.5VS_VGA

U4102

+1.5VS

EN_1.8V

PU8

5. +1.8VS_VGA

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date: Sheet of

RSVD

Document Number Rev

LA-D707P

43 60Wednesday, May 11, 2016

v0.2

Stuf f

Power rail

+RTCVCC

VIN

BATT+

B+

+VL

+3VL

+5VALW

+3VALW

+3VALW_EC

1 1

+3V_PCH

+1.2V_VDDQ

+5VS

+3VS

+1.5VS

+1.05VS

+0.6V_0.6VS

+VCC_CORE

Control (EC)

EC_ON

PCH_PWR_EN

SYSON

SUSP#

Source (CPU)

PM_SLP_S5#/PM_SLP_S4#

PM_SLP_S3#

VR12.5_VR_ON

BOM Structure Table (1/2)

C_SMB_DA1

Un-Stuf f

+3VS

R=1K

+3VS

R=499

+3VS

R=1K

+3VS

R=1K

+3VL_EC

R=2.2K

+3VS

2N7002

Touch Screen

QKKS@

UC1

ES_QKKS

S IC A32 FJ8067702739720 QKKS G0 2.4G

QS_i3@

UC1

i3_7100U_QS_QLDP

SA0000A3810 S IC A32 FJ8067702739738 QLDP H0 2.4G

R30@

U666

R16M-M1-30 FCBGA

SA000087T90 S IC A32 216-0867-071 R16M-M1-30 FCBGA

+3VS

2N7002

+3VS

2N7002

+3VS

R=2.2K

EC_SMB_CK2 EC_SMB_DA2

R=100

SA00009PJ10

+3VS

R=10K

+3VALW

R=2.2K

DGPU_PEX _RST#

2N7002

Thermal Sensor :NCT7718W_MSOP8

BAT

Charger

Funct i on

DGPU SKU

UMA SKU

SPI_IO3(MOW36)

Crystal (DIS) Crystal XTAL@

Green CLK(UMA)

Green CLK(DIS)

2 2

UCPU1

3 3

CPU

UK1:+3VALW_EC

4 4

(+3VL)

R7 R8

R9 W2

W3 V3

U6 U7

U9 U8

79 80

PX@

UMA@

ES@

XTALPX@

GCLK@

GCLKPX@

TPM@TPM

SMBCLK SMBDATA

SML0CLK SML0DATA

SML1CLK SML1DATA

I2C_0_SCL

I2C_0_SDA

I2C_1_SCL

I2C_1_SDA

EC_SMB_CK2 EC_SMB_DA2

EC_SMB_CK1

QKJW@

UC1

ES_QKJW

S IC A32 FJ8067702739718 QKJW G0 2.6G

QS_i5@

UC1

i5_7200U_QLDM

SA0000A3710 S IC A32 FJ8067702739739 QLDM H0 2.5G

R70@

U666

R16M-M1-70 FCBGA

SA000098V10 S IC A32 216-0864-032 R16M-M1-70 FCBGA

PCH_SMBCLK PCH_SMBDATA

TP_SMBCLK TP_SMBDAT

+3VGS_AON

R=2.2K

I2CS_SCL

I2CS_SDA

Address : 0x4C

SOC SMBUS Address Table

OC_SMBUS Net Name

SMBCLK S

MBDATA

SML0CLK SML0DATA

SML1CLK SML1DATA

SA00009UR00

SO-DIMM B

Touch Pad

dGPU

i7_7500U_QLDN

SA0000A3420 S IC A32 FJ8067702739740 QLDN H0 2.7G

Power Rail

+3VS

SKLPV2@

UC1

SA000092P60

SKY_i7_6500U_SR2EZ

S IC FJ8066201930408 SR2EZ D1 2.5G BGA

QS_i7@

UC1

(TBC)

Device

DIMM1

Address (7 bit)

TBC

Touch PAD T BC TBC TBC

ME FW

DGPU

x48/0x49

TBC

ddress (8bit)

Write Read

0xA2

TBC

0x90/0x92

TBC

BC TBC

TBCTBC

C SMBUS Address Table

C_SMBUS Port

SMBUS Port 1

SMBUS Port 2

PCH TBC T BC TB C

DAX

KBL

Part Number = DA6001LS000 PCB 1RU LA-D707P REV0 M/B 6

ROYALTY HDMI W/LOGO45@

Part Number Description

HDMI W/Logo:RO0000002HM

RO0000002HM

RO0000003HM

R30R1@

U666

R16M-M1-30 FCBGA

SA000087TC0 S IC A32 216-0867-071 R16M-M1-30 FCBGA

R30R3@

U666

R16M-M1-30 FCBGA

SA000087TB0 S IC A32 216-0867-071 R16M-M1-30 FCBGA

i3R1@

UC1

SA000092N70

ES_QKKS

S IC A32 FJ8067702739720 QKKS G0 2.4G

i3R3@

UC1

SA000092N80

ES_QKKS

S IC A32 FJ8067702739720 QKKS G0 2.4G

ZZZ

HY2@

MIC2@

2G HYNIX

2G MICRON

X7667032L01

X7667032L02

ZZZ

R3MIC2@

R3HY2@

2G MICRON

2G HYNIX

X7667032L24

X7667032L23

DAX

SKL

Part Number = DAZ1O200301 PCB BDL50 LA-D704P LS-C701P/C703P 02

SKL@

R70R1@

U666

R16M-M1-70 FCBGA

SA000098V30 S IC A32 216-0864-032 R16M-M1-70 FCBGA

R70R3@

U666

R16M-M1-70 FCBGA

SA000098V40 S IC A32 216-0864-032 R16M-M1-70 FCBGA

i5R1@

UC1

SA000092O70

ES_QKKS

S IC A32 FJ8067702739720 QKKS G0 2.4G

i5R3@

UC1

SA000092O80

ES_QKKS

S IC A32 FJ8067702739720 QKKS G0 2.4G

ZZZ

SAM2@

2G SAMSUNG

X7667032L05

ZZZ

R3SAM2@

2G SAMSUNG

X7667032L25

ZZZ

HY4@

4G Hynix

X7667032L03

ZZZ

R3HY4@

4G Hynix

X7667032L21

ZZZ

MIC4@

4G Micron

X7667032L04

ZZZ

R3MIC4@

4G Micron

X7667032L22

Power State

STATE

S0 (Full ON)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Sof t OFF)

i7R1@

UC1

SA000092P60

ES_QKKS

S IC A32 FJ8067702739720 QKKS G0 2.4G

i7R3@

UC1

SA000092P70

ES_QKKS

S IC A32 FJ8067702739720 QKKS G0 2.4G

SIGNAL

<PCI-E,SATA,USB3.0/CLK>

Lane#

Load BOM Opt i on Tabl e

BOM Number Load BOM Opt i on

4519YN32L01(UMA)

4519YN32L02(DIS)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/29 2011/06/29

Compal Secret Data

Deciphered Date

(TBC)

Power Rail Devi ce Address (7 bit)

+3VL_EC

+3VS

CHGR

dGPU

Thermal

Sensor

0x16

0x12

TBC

0x4C

PCH TBC

SLP_S4#

SLP_S3#

HIGH HIGH HIGH

HIGH

LOW

LOWLOW

LOW LOW LOW

+VALW

SLP_S5#

ON ON ON ON

HIGH

ONONON

HIGH

OFF

+VS Clock

OFF

<USB2.0 port>

USB2.0 port

1 2

USB 2.0 OFF BOARD

3 4 5 6 7 8 9 10

PCI-E

SATA

1 2 3 4 5

12 ODD

0 1

TOUCH SCREEN

USB3.0

1 2 3 4 5 6

DESTINATION

UMA

USB 2.0/3.0 USB 2.0/3.0 USB 2.0/3.0

WLAN WLAN

Camera Camera

CR CR

USB 2.0/3.0

USB 2.0 OFF BOARD

TOUCH SCREEN

DESTINATION

UMA

SB3.0

USB3.0 USB3.0

USB3.0(Charger) USB3.0(Charger)

USB3.0(IO Board)USB3.0(IO Board)

X X X X

LAN LAN

WLAN WLAN

2.5"HDD 2.5"HDD ODD

Card reader(PCI-E)

X X

Title

Size

Document Number Re v

Custom

Date: Sheet of

Dis

USB3.0

GPU(DIS only) GPU(DIS only) GPU(DIS only) GPU(DIS only)

Card reader(PCI-E)

Compal Electronics, Inc.

Notes List

LA-D707P

Dis

CLK

X X X X

CLK0

CLK1 CLK2

X X

CLK3 X X

X X X

3 60Wednesday, May 11, 2016

v0.2

[Diner-PWR Sequence_SKL-U22_DDR3L_Volume_NON CS]

G3->S0 S0->S3

+3VL_RTC

SOC_RTCRST#

19VB

+3VLP/+5VLP

D D

EC_ON

+5VALW/+3VALW/+ 3VALW_DSW

PM_BATLOW#

tPCH01_Min : 9 ms

PCH04_Min : 9 ms

Pull-up to DSW well if not implemented.

/DS3

->S0

DS3S0/

PCH_PWR_EN (SLP_SUS#)

+3V_PRIM

+1.8V_PRIM

EXT_PWR_GATE#

+1.0V_MPHYPLL

+1.0V_PRIM_CORE

+1.0V_PRIM

tPCH06_Min : 200 us

tPCH34_Max : 20 ms

SUSACK#

PCH_DPWROK

EC_RSMRST#

C C

AC_PRESENT

If EXT_PWR_GATE# Toffmin is too small, Pwr gate may choose to completely ignore it

tPCH02_Min : 10 ms

tPCH03_Min : 10 ms

tPLT02_Min : 0 ms Max : 90 ms

ON/OFF

PBTN_OUT#

PM_SLP_S5#

ESPI_RST#

Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

tPCH18_Min : 90 us

PM_SLP_S4#

SYSON

+1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC

PM_SLP_S3#

SUSP#

+1.0VS_VCCSTG

+1.0VS_VCCIO

B B

tCPU04 Min : 100 ns

tCPU10 Min : 1 ms

+5VS/+3VS/+1. 5VS/+1.05VS

EC_VCCST_PG

VR_ON

SM_PG_CTRL

+0.675VS_VTT

+VCC_SA

T4 = Min : 20ms Max : 30ms(EC Control)

tCPU19 Max : 100 ns

tCPU18 Max : 35 us

tCPU09 Min : 1 ms

+VCC_CORE

+VCC_GT

VR_PWRGD

PCH_PWROK

tCPU16 Min : 0 ns

H_CPUPWRGD

SYS_PWROK

A A

SUS_STAT#

SOC_PLTRST#

S0->S5

+3VL_RTC

SOC_RTCRST#

+19VB

+3VLP/+5VLP

EC_ON

+5VALW/+3VALW/+ 3VALW_DSW

PM_BATLOW#

PCH_PWR_EN (SLP_SUS#)

+3V_PRIM

+1.8V_PRIM

EXT_PWR_GATE#

+1.0V_MPHYPLL

+1.0V_PRIM_CORE

+1.0V_PRIM

SUSACK#

PCH_DPWROK

EC_RSMRST#

AC_PRESENT

ON/OFF

PBTN_OUT#

PM_SLP_S5#

ESPI_RST#

PM_SLP_S4#

SYSON

+1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC

PM_SLP_S3#

SUSP#

+1.0VS_VCCSTG

+1.0VS_VCCIO

+5VS/+3VS/+1. 5VS/+1.05VS

EC_VCCST_PG

VR_ON

SM_PG_CTRL

+0.675VS_VTT

+VCC_SA

+VCC_CORE

+VCC_GT

VR_PWRGD

PCH_PWROK

H_CPUPWRGD

SYS_PWROK

SUS_STAT#

SOC_PLTRST#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Document Number Rev

Custom

Date: Sheet o f

LA-D707P

HW Reserve

4 60Wednesday, May 11, 2016

v0.2

UC1A

AT16 AU16

D63 A54 C65 C63 A65

C55 D55 B54 C56

A7 BA5 AY5

H66 H65

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

GPP_E20/DDPC_CTRLCLK

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKL-U_BGA1356

UC1D

CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#

CPU MISC

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

SKL-U_BGA1356

SKL-U

4 OF 20

PCH_DPB_N2<21>

PCH_DPB_P2<21>

SOC_DP1_CTRL_DATA(Internal Pull Down):

isplay Port B Detected

1 1

0 = Port B is not detected.

1 = Port B is detected.

<HDMI>

PCH_DPB_N1<21>

PCH_DPB_P1<21>

PCH_DPB_N0<21>

PCH_DPB_P0<21>

PCH_DPB_N3<21>

PCH_DPB_P3<21>

PCH_DPC_N0<22>

PCH_DPC_P0<22>

PCH_DPC_N1<22>

PCH_DPC_P1<22>

SOC_DP2_CTRL_DATA(Internal Pull Down):

Display Port C Detected

0 = Port C is not detected.

1 = Port C is detected.

HDMI DDC (Port B)

PCH_DDPB_CLK<21> PCH_DDPB_DAT<21>

+3VS

<DB> DP port C enable

+1.0V_VCCST

H_THERMTRIP#

1 2

RC2 1K_0402_5%

2 2

COMPENSATION PU FOR eDP

+1.0VS_VCCIO

EDP_COMP

1 2

RC1

CAD note: Trace width=20 mils,Spacing=25mil,Max length=100mils

24.9_0402_1%

PROCHOT#<26>

+1.0VS_VCCIO

RC3 1K_0402_5%

RC4 499_0402_1%

DS11 CK0402101V05_0402-2

ESD@

SCV00001K00

T248 TP@

12 12 12 12

H_PECI<26>

T25 TP@

T270 TP@ T271 TP@ T250 TP@ T249 TP@

T30 TP@

T40 TP@

1 2

RC5 49.9_0402_1% RC6 49.9_0402_1% RC7 49.9_0402_1% RC8 49.9_0402_1%

PCH_DDPB_CLK PCH_DDPB_DAT

1 2

RC200 2.2K_0402_5%@

1 2

RC199 2.2K_0402_5%

CRT@

EDP_COMP

H_PECI

H_PROCHOT#_R H_THERMTRIP# SOC_OCC#

XDP_BPM#0 XDP_BPM#1

SOC_GPIOE3

SOC_GPIOB4

CPU_POPIRCOMP PCH_OPIRCOMP EDRAM_OPIO_RCOMP EOPIO_RCOMP

SKL-U

DDI

DISPLAY SIDEBANDS

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

1 OF 20

Rev_0.5 3

JTAGX

EDP

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

Rev_0.5 3

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

CPU_XDP_TCK0 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST#

PCH_JTAG_TCK1 SOC_XDP_TDI

SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST# CPU_XDP_TCK0

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52

G50 F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

DDI2_AUX_DN DDI2_AUX_DP

PCH_DDPB_HPD DDI2_HPD NMI_DBG#_CPU EC_SCI# EDP_HPD

ENBKL

ENVDD_CPU

T259TP@ T260TP@ T261TP@ T262TP@ T263TP@

T264TP@ T265TP@ T266TP@ T267TP@ T268TP@ T269TP@

EDP_CPU_LANE_N0_C <19> EDP_CPU_LANE_P0_C <19> EDP_CPU_LANE_N1_C <19> EDP_CPU_LANE_P1_C <19>

EDP_CPU_AUX#_C <19> EDP_CPU_AUX_C <19>

T228TP@

DDI2_AUX_DN <22> DDI2_AUX_DP <22>

PCH_DDPB_HPD <21> DDI2_HPD <22> NMI_DBG#_CPU <10,26> EC_SCI# <10,26> EDP_HPD <19>

ENBKL <26> BKL_PWM_CPU <20> ENVDD_CPU <20>

1 2

RC123 100K_0402_5%@

1 2

RC124 100K_0402_5%

<eDP >

From HDMI From eDP to CRT

From eDP

ENVDD_CPU

ENBKL

<DB> Check

XDP CONN

3 3

+1.0VS_VCCIO

RC11 51_0402_5%@

RC13 51_0402_5%@

RC15 51 +-1% 0402 SD000008H80

RC364 51_0402_5%@

+1.0V_PRIM

RC14 51_0402_5%@

RC31 1K_0402_5%@

4 4

RC365 51_0402_1%@

RC35 51_0402_1% SD000008H80

RC37 51_0402_5%@

RC366 0_0402_5%@

1 2

SOC_XDP_TMS

SOC_XDP_TDI

SOC_XDP_TDO

CPU_XDP_TCK0

XDP_PREQ#

XDP_ITP_PMODE

SOC_XDP_TRST#

CPU_XDP_TCK0

PCH_JTAG_TCK1

CFG3

XDP_PREQ# <11>

XDP_ITP_PMODE <16>

CFG3 <16>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet o f

Compal Electronics, Inc.

SKL-U(1/12)DDI,MSIC,XDP,EDP

Document Number Re v

LA-D707P

5 60Wednesday, May 11, 2016

v0.2

Interleaved Memory

D D

+1.2V_VDDQ

SB000008E10

RC904 100K_0402_5%@

SKL-U

DDR CH - A

2 OF 20

UC1B

DDR_A_D[0..15]<17>

DDR_A_D[16..31]<17>

C C

DDR_A_D[32..47]<17>

DDR_A_D[48..63]<17>

B B

A A

DDR_A_D0

AL71

DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

SB00000QJ00,S TR DRC5115E0L NPN SOT323-3

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKL-U_BGA1356

RC905

100K_0402_5%

RC906

100K_0402_5%

DDR_PG_CTRL SM_PG_CTRL

UC9 MMBT3904WH NPN SOT323-3

<Cocoa_1020> P

DG#543016, ODT: CPU side no connect, DRAM side connect to VDDQ(Memory down); FET+R(SO-DIMM)

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

DDR_A_CLK#0

AU53

DDR_A_CLK0

AT53

DDR_A_CLK#1

AU55

DDR_A_CLK1

AT55

DDR_A_CKE0

BA56

DDR_A_CKE1

BB56 AW56 AY56

DDR_A_CS#0

AU45

DDR_A_CS#1

AU43

DDR_A_ODT0

AT45

DDR_A_ODT1

AT43

DDR_A_MA5

BA51

DDR_A_MA9

BB54

DDR_A_MA6

BA52

DDR_A_MA8

AY52

DDR_A_MA7

AW52

DDR_A_BG0

AY55

DDR_A_MA12

AW54

DDR_A_MA11

BA54

DDR_A_ACT#

BA55

DDR_A_BG1

AY54

DDR_A_MA13

AU46

DDR_A_MA15_CAS#

AU48

DDR_A_MA14_WE#

AT46

DDR_A_MA16_RAS#

AU50

DDR_A_BA0

AU52

DDR_A_MA2

AY51

DDR_A_BA1

AT48

DDR_A_MA10

AT50

DDR_A_MA1

BB50

DDR_A_MA0

AY50

DDR_A_MA3

BA50

DDR_A_MA4

BB52

DDR_A_DQS#0

AM70

DDR_A_DQS0

AM69

DDR_A_DQS#1

AT69

DDR_A_DQS1

AT70

DDR_A_DQS#2

BA64

DDR_A_DQS2

AY64

DDR_A_DQS#3

AY60

DDR_A_DQS3

BA60

DDR_A_DQS#4

BA38

DDR_A_DQS4

AY38

DDR_A_DQS#5

AY34

DDR_A_DQS5

BA34

DDR_A_DQS#6

BA30

DDR_A_DQS6

AY30

DDR_A_DQS#7

AY26

DDR_A_DQS7

BA26

DDR_A_ALERT#

AW50

DDR_A_PAR

AT52

+0.6V_VREFCA

AY67 AY68

+0.6V_B_VREFDQ

BA67

DDR_PG_CTRL

AW67

For VTT power control

DDR_PG_CTRL

DDR_A_CLK#0 <17> DDR_A_CLK0 <17> DDR_A_CLK#1 <17> DDR_A_CLK1 <17>

DDR_A_CKE0 <17>

DDR_A_CKE1 <17>

T14TP@ T15TP@

DDR_A_CS#0 <17>

DDR_A_CS#1 <17>

DDR_A_ODT0 <17>

DDR_A_ODT1 <17> DDR_B_ODT0 <18>

DDR_A_MA5 <17>

DDR_A_MA9 <17>

DDR_A_MA6 <17>

DDR_A_MA8 <17>

DDR_A_MA7 <17>

DDR_A_BG0 <17>

DDR_A_MA12 <17>

DDR_A_MA11 <17>

DDR_A_ACT# <17>

DDR_A_BG1 <17>

DDR_A_MA13 <17>

DDR_A_MA15_CAS# <17>

DDR_A_MA14_WE# <17>

DDR_A_MA16_RAS# <17>

DDR_A_BA0 <17>

DDR_A_MA2 <17>

DDR_A_BA1 <17>

DDR_A_MA10 <17>

DDR_A_MA1 <17>

DDR_A_MA0 <17>

DDR_A_MA3 <17>

DDR_A_MA4 <17>

DDR_A_DQS#0 <17>

DDR_A_DQS0 <17>

DDR_A_DQS#1 <17>

DDR_A_DQS1 <17>

DDR_A_DQS#2 <17>

DDR_A_DQS2 <17>

DDR_A_DQS#3 <17>

DDR_A_DQS3 <17>

DDR_A_DQS#4 <17>

DDR_A_DQS4 <17>

DDR_A_DQS#5 <17>

DDR_A_DQS5 <17>

DDR_A_DQS#6 <17>

DDR_A_DQS6 <17>

DDR_A_DQS#7 <17>

DDR_A_DQS7 <17>

DDR_A_ALERT# <17>

DDR_A_PAR <17>

+0.6V_VREFCA

+0.6V_B_VREFDQ

+1.2V_VDDQ

NC1VCC

GND

CC570.1U_0201_10V6K

UC7

SN74AUP1G07DCKR_SC70-5

SA00007UR00

+3VS

RC394 100K_0402_5%

DDR_B_D[0..15]<18>

DDR_B_D[16..31]<18>

DDR_B_D[32..47]<18>

DDR_B_D[48..63]<18>

SM_PG_CTRL <49>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

UC1C

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKL-U_BGA1356

+1.2V_VDDQ

DDR_DRAMRST# DDR_DRAMRST#_R

SKL-U

DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR CH - B

3 OF 20

RC32 470_0402_5%

1 2

RC33 0_0402_5%

Rev_0.5 3Rev_0.5 3

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]

CC155

0.1U_0201_10V6K

@ESD@

DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

DDR_DRAMRST#_R <17,18>

9/8 Modify base on ESD Request

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32 AR25 AR27 AR22 AR21

AN43 AP43 AT13 AR18 AT18 AU18

DDR_B_CLK#0 DDR_B_CLK#1 DDR_B_CLK0 DDR_B_CLK1

DDR_B_CKE0 DDR_B_CKE1

DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0 DDR_B_ODT1

DDR_B_MA5 DDR_B_MA9 DDR_B_MA6 DDR_B_MA8 DDR_B_MA7 DDR_B_BG0 DDR_B_MA12 DDR_B_MA11 DDR_B_ACT# DDR_B_BG1

DDR_B_MA13 DDR_B_MA15_CAS# DDR_B_MA14_WE# DDR_B_MA16_RAS# DDR_B_BA0 DDR_B_MA2 DDR_B_BA1 DDR_B_MA10 DDR_B_MA1 DDR_B_MA0 DDR_B_MA3 DDR_B_MA4

DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7

DDR_B_ALERT# DDR_B_PAR DDR_DRAMRST# SM_RCOMP0

RC38 121_0402_1%

SM_RCOMP1

RC39 80.6_0402_1%

SM_RCOMP2

RC40 100_0402_1%

From ESD Team Request

T17TP@ T18TP@

DDR_PG_CTRL

PLACE NEAR TO SoC

DDR_B_CLK#0 <18> DDR_B_CLK#1 <18> DDR_B_CLK0 <18> DDR_B_CLK1 <18>

DDR_B_CKE0 <18> DDR_B_CKE1 <18>

DDR_B_CS#0 <18> DDR_B_CS#1 <18>

DDR_B_ODT1 <18>

DDR_B_MA5 <18> DDR_B_MA9 <18> DDR_B_MA6 <18> DDR_B_MA8 <18> DDR_B_MA7 <18> DDR_B_BG0 <18> DDR_B_MA12 <18> DDR_B_MA11 <18> DDR_B_ACT# <18> DDR_B_BG1 <18>

DDR_B_MA13 <18> DDR_B_MA15_CAS# <18> DDR_B_MA14_WE# <18> DDR_B_MA16_RAS# <18> DDR_B_BA0 <18> DDR_B_MA2 <18> DDR_B_BA1 <18> DDR_B_MA10 <18> DDR_B_MA1 <18> DDR_B_MA0 <18> DDR_B_MA3 <18> DDR_B_MA4 <18>

DDR_B_DQS#0 <18> DDR_B_DQS0 <18> DDR_B_DQS#1 <18> DDR_B_DQS1 <18> DDR_B_DQS#2 <18> DDR_B_DQS2 <18> DDR_B_DQS#3 <18> DDR_B_DQS3 <18> DDR_B_DQS#4 <18> DDR_B_DQS4 <18> DDR_B_DQS#5 <18> DDR_B_DQS5 <18> DDR_B_DQS#6 <18> DDR_B_DQS6 <18> DDR_B_DQS#7 <18> DDR_B_DQS7 <18>

DDR_B_ALERT# <18> DDR_B_PAR <18>

1 2 1 2 1 2

@ESD@

1 2

CC70 100P_0402_50V8J

8/10 Modify for DDR4

9/8 Modify

8/10 Modify for DDR4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date: Sheet of

SKL-U(2/12)DDRIII

Document Number Re v

LA-D707P

Wednesday, May 11, 2016

v0.2

PCH_SPI_CLK PCH_SPI_SO PCH_SPI_SI PCH_SPI_SIO2 PCH_SPI_SIO3 PCH_SPI_CS0#

D D

12/11_Delete TP

To TPM

C C

B B

A A

PCH_SPI_CS0#_R PCH_SPI_CS0#_R PCH_SPI_SO_R PCH_SPI_SO_R

PCH_SPI_SI_R PCH_SPI_SI_R EC_SPI_SI

SPI ROM ( 8MByte Only)

PCH_SPI_CS0#_R

PCH_SPI_WP#

EON SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P MXIC SA00006N100 S IC FL 64M MX25L6473EM2I-10G SOP 8P WINBOND SA000039A30 S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM Micron SA00005L100 S IC FL 64M N25Q064A13ESEC0F SO8W 8P

1 8 2 7 3 6 4 5

15_0804_8P4R_5%

1 8 2 7 3 6 4 5

15_0804_8P4R_5%

RC388 15_0402_5%

UC2

/CS

DO(IO1)

/WP(IO2)

GND

W25Q64FVSSIQ_SO8

PCB Footprint = ACES_91960-0084L_8P-T

Use socket footprint

RC368

15_0402_5%

EMI@

EC_KBRST#<26>

SERIRQ<26,28>

Source Fromto SPI ROM UC2

RPH11

EC_SPI_CS0# PCH_SPI_CS0# EC_SPI_SO PCH_SPI_SO

RPH12

PCH_SPI_SIO3PCH_SPI_HOLD# PCH_SPI_SI

PCH_SPI_SIO2PCH_SPI_WP#

+3V_SPI

VCC

PCH_SPI_HOLD#PCH_SPI_SO_R

/HOLD(IO3)

PCH_SPI_CLK_RPCH_SPI_CLK

CC9 10P_0402_50V8J

@EMI@

PCH_SPI_CLK_R

CLK

PCH_SPI_SI_R

DI(IO0)

SA000039A30

SPI ROM: Main:SA000039A30, S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM 2nd :SA00007LA10, S IC FL 64M GD25B64CSIGR SOP 8P SPI ROM 3rd :SA000099300, S IC FL 64M N25Q064A13ESEDFF SO8W 8P SPI

1 2

EC_KBRST#

SERIRQ

LPC Mode

EC_SPI_CS0# <26>

EC_SPI_SO <26>

EC_SPI_SI <26>

CC8

1 2

0.1U_0402_16V7K

PCH_SPI_CLK_R <26>

AV2

AW3

AV3

AW2

AU4 AU3 AU2 AU1

AW13

AY11

M2 M3

J4 V1 V2 M1

G3 G2 G1

UC1E

SPI - FLASH

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

C LINK

CL_CLK CL_DATA CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

SKL-U_BGA1356

QC1A

6 1

SMBCLK

2N7002DWH_SOT363-6

SB00000I700

SMBDATA

2N7002DWH_SOT363-6

SML1CLK

SML1DATA

SMBCLK

2N7002DWH_SOT363-6

SMBDATA

6 1

QC2A

SB00000I700

SKL-U

LPC

5 OF 20

+3VS +3VS

QC1B

2N7002DWH_SOT363-6

3 4

SB00000I700

3 4

QC2B

2N7002DWH_SOT363-6

SB00000I700

<DB> PWR Rail

SB00000I700

QC7A

QC7B

SB00000I700

2N7002DWH_SOT363-6

SMBUS, SMLINK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

RC215

RC216

10K_0402_5%

+3VS

10K_0402_5%

1 2

<Cocoa_1020> add level shift

EC_SMB_CK2 <10,19,22,26,37>

EC_SMB_DA2 <10,19,22,26,37>

+3VALW+3V_PRIM

RC81

RC82 10K_0402_5%

1 2

Rev_0.5 3

SMBCLK

SMBDATA

R10

SMBALERT#

SML0CLK

SML0DATA

SML0ALERT#

SML1CLK

SML1DATA

GPP_B23

AM7

LPC_AD0

AY13

LPC_AD1

BA13

LPC_AD2

BB13

LPC_AD3

AY12

LPC_FRAME#

BA12

SUS_STAT#

BA11

CLK_PCI0

AW9

CLK_PCI1

AY9

PM_CLKRUN#

AW11

<SI>un-mount RC53 11/28 CPU side delete EC_PCIE_WAKE#

PCH_SMBCLK <17,18,19,22>

PCH_SMBDATA <17,18,19,22>

TP_SMBCLK <27>

TP_SMBDATA <27>

T239TP@

1 2

SML1ALERT#

RC902

0_0201_5%

T234TP@

LPC_AD0 <26,28> LPC_AD1 <26,28> LPC_AD2 <26,28> LPC_AD3 <26,28> LPC_FRAME# <26,28>

T242TP@

1 2

RC387 22_0402_5%

1 2

RC53 22_0402_5%TPM@

PM_CLKRUN# <26>

SML0ALERT# (Internal Pull Down): eSPI or LPC 0 = LPC is selected for EC --> For KB9022/9032 Use 1 = eSPI is selected for EC --> For KB9032 Only.

SMB

(Link to XDP, DDR, TP)

SML1

(Link to EC,DGPU, LAN, Thermal Sensor)

CLK_PCI_LPC <26> CLK_PCI_TPM <28>

To EC

SML0ALERT#

SML1ALERT#

SML0ALERT#

SMBALERT#

EC_KBRST#

RC218 1K_0402_1%

RC903

150K_0402_1%

RC360 10K_0402_5%@

RPC19 10K_0804_8P4R_5%

11/28_Follow Intel check list, add PU res

11/28_Change PWR rail from +3VS to +3V_PRIM

+3V_PRIM

SML0CLK

SML0DATA

SML1CLK SML1DATA SMBDATA SMBCLK

PCH_SPI_SIO2

PCH_SPI_SIO3

PCH_SPI_CS0#_R

PCH_SPI_SIO3

From WW36 MOW for SKL-U ES sample

PM_CLKRUN#

SERIRQ

Follow 543016_SKL_U_Y_PDG_0_9

1 2

RC49 499_0402_1%

1 2

RC50 499_0402_1%

RPC7

1 8 2 7 3 6 4 5

1K_0804_8P4R_5%

1 2

RC390 1K_0402_1%@

1 2

RC391 1K_0402_1%

1 2

RC357 1K_0402_5%

1 2

RC51 1K_0402_1%ES@

1 2

RC107 8.2K_0402_5%

1 2

RC122 8.2K_0402_5%

+3V_SPI

+3VS_PGPPA

18 27 36 45

+3V_PRIM

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/12/11 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(3/12)SPI,ESPI,SMB,LPC

Size

Document Number Re v

Custom

LA-D707P

Date : Sheet o f

7 60Wednesday, May 11, 2016

v0.2

UC1G

D D

HDA_SDIN0<24>

T35 TP@

T38 TP@ T39 TP@

HDA_SPKR<10,24>

C C

HDA_SYNC HDA_BIT_CLK HDA_SDOUT

HDA_SDIN0

HDA_RST#

SOC_GPIOF1 SOC_GPIOF0

HDA_SPKR

BA22 AY22 BB22 BA21 AY21

AW22

AY20

AW20

AK7 AK6 AK9

AK10

AW5

H5 D7

D8 C8

AUDIO

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKL-U_BGA1356

SKL-U

7 OF 20

Rev_0. 53

SDIO/SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

VRAMCLK_SEL

PROJECT_ID

SD_RCOMP

RC76 200_0402_1%

SOC_GPIOF17

T235 TP@

+3V_PRIM

RC127 10K_0402_5%

PX@

RC128

10K_0402_5%

UMA@

PROJECT_ID

VRAM Clock

VRAMCLK_SEL

UMA

+3V_PRIM

X76@

RC900 10K_0402_5%

1 2

X76@

RC901 10K_0402_5%

1 2

1000M Hz900MH z

HDA for AUDIO

RPC9

1 8

@EMI@

2 7 3 6 4 5

HDA_SYNC_AUDIO<24> HDA_RST_AUDIO#<24> HDA_SDOUT_AUDIO<24>

HDA_BITCLK_AUDIO<24>

CC143 22P_0402_50V8J

EMI request

B B

A A

HDA_SYNC HDA_RST# HDA_SDOUT

33_0804_8P4R_5%

HDA_BIT_CLK

RC383 33_0402_5%

EMI@

A36 B36 C38 D38 C36 D36 A38 B38

C31 D31 C33 D33 A31 B31 A33 B33

A29 B29 C28 D28 A27 B27 C27 D27

UC1I

CSI-2

CSI2_DN0 CSI2_DP0 CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3

CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7

CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11

SKL-U_BGA1356

+3V_HDA

ME_FLASH_EN<26>

1 2

SKL_ULT

1K_0402_1%

9 OF 20

RC380

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

1 2

RC367 0_0402_5%

Rev_0. 53

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

HDA_SDOUT

QC380 MESS138W-G_SOT323-3

C37 D37 C32 D32 C29 D29 B26 A26

CSI2_COMP

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

EMMC_RCOMP

AT1

123

EMMC_RCOMP

HDA_SDOUT: ME Flash Descriptor Security Override Low : Disabled(Default) High : Enabled

T63 TP@

RC80 100_0402_1%

RC89 200_0402_1%

Security Classification

2014/05/19 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(4/12)HDA,EMMC,SDIO,CSI2

Size

Document Number Re v

Custom

LA-D707P

Date : Sheet o f

Wednesday, May 11, 2016

Date : Sheet o f

Wednesday, May 11, 2016

Date : Sheet o f

Wednesday, May 11, 2016

v0.2

+RTCVCC

RC91 20K_0402_5%

CC10 1U_0402_6.3V6K

CLRP1 SHORT PADS

RC93 20K_0402_5%

CC11 1U_0402_6.3V6K

CLRP2 SHORT PADS

D D

+3V_PRIM

C C

B B

A A

RC94 1M_0402_5%

PCH_RTCRST#

PCH_SRTCRST#

+3VS

RC165 10K_0402_5%

RC105 10K_0402_5%

RC109 10K_0402_5%

+3VALW_DSW

10K_0804_8P4R_5%

CLRP3 SHORT PADS

RC100 1K_0402_5%

RC101 100K_0402_5%

+3VALW_DSW

+3V_PRIM

+3VALW_DSW

RC111 100K_0402_5%

From EC(open-drain)

EC_VCCST_PG_R<26,35>

1 2

R10880_0402_5%

R10890_0402_5%

1 2

RPC10

18 27 36 45

10K_0804_8P4R_5%

1 2

RPC11

18 27 36 45

1 2

RC103 8.2K_0402_5%

1 2

RC104 1K_0402_5%

1 2

RC106 10K_0402_5%

1 2

RC115 10K_0402_5%

PCH_SRTCRST#

CLR ME

PCH_RTCRST#

CLR CMOS

SM_INTRUDER#

CLR_CMOS# <26>

Clear CMOS close to RAM door

JCMOS1

0_0603_5%

CLKREQ_PCIE#4

CLKREQ_PCIE#5

LAN_CLKREQ# MINI1_CLKREQ# CR_CLKREQ#

VGA_CLKREQ#

PCH_PWROK LAN_WAKE# PCH_RSMRST# SYS_RESET#

SYS_RESET#

SUSCLK

PCH_DPWROK

From 545659_SKL_PCH_U_Y_EDS_R0_7

<DB> unpop, PD at GPU side

PM_BATLOW#

WAKE#

AC_PRESENT_R

<DB> RC106 unpop , follow module design

SOC_VRALERT#

PBTN_OUT#

+1.0V_VCCST

RC113 1K_0402_5%

1 2

RC116 60.4_0402_1%

<Cocoa_1 027> check un-use GPIO for termination guidance

DS12

PCH_PWROK

CK0402101V05_0402-2

ESD@ SCV00001K00

Only For Power Sequence Debug

ESD@

DS13

SCV00001K00

1 2

CK0402101V05_0402-2

DS14

1 2

CK0402101V05_0402-2

DS15

1 2

CK0402101V05_0402-2

EC_VCCST_PG

SUSACK#<26>

H_CPUPWRGD

@ESD@ SCV00001K00

SUSACK#

@ESD@ SCV00001K00

SYS_PWROK

CLK_PEG_VGA#<36>

GPU

CLK_PEG_VGA<36>

VGA_CLKREQ#<37>

CLK_PCIE_LAN#<23>

LAN

CLK_PCIE_LAN<23>

LAN_CLKREQ#<23>

WLAN

CLK_PCIE_WLAN#<32> CLK_PCIE_WLAN<32>

MINI1_CLKREQ#<32>

CardRea der

T95 TP@

RC102 1K_0402_5%@

RC110 0_0402_5%

<DB> add ESD protection

PCH PLTRST Buf f er

PLT_RST#_PCH

SN74AHC1G08DCKR_SC70-5

T296 TP@

PCH_RSMRST#<26>

1 2

SYS_PWROK<26>

PCH_PWROK<26>

PCH_SUSWARN#<26>

WAKE#<32>

UC1J

CLK_PEG_VGA# CLK_PEG_VGA VGA_CLKREQ#

CLK_PCIE_LAN# CLK_PCIE_LAN LAN_CLKREQ#

CLK_PCIE_WLAN# CLK_PCIE_WLAN MINI1_CLKREQ#

CR_CLKREQ#

CLKREQ_PCIE#4

CLKREQ_PCIE#5

RC99 0_0402_5%

PLT_RST#_PCH SYS_RESET# PCH_RSMRST#

H_CPUPWRGD EC_VCCST_PG

SYS_PWROK PCH_PWROK PCH_DPWROK_R

PCH_SUSWARN# SUSACK#_R

WAKE# LAN_WAKE#

T94 TP@

PCH_RSMRST# PCH_PWROK

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKL-U_BGA1356

<DB> Romove PLT_RST# buf f er

1 2

+3VS

CC145

1 2

UC8

0.1U_0402_16V7K

IN1

IN2

UC1K

AN10

GPP_B13/PLTRST#

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKL-U_BGA1356

DC3

SCS00003500

CH751H-40PT_SOD323-2

2 1

DC4

SCS00003500

CH751H-40PT_SOD323-2

PCH_DPWROK<26>

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SYSTEM POWER MANAGEMENT

Issued Date

CLOCK SIGNALS

PLT_RST#PLT_RST#

RC112 0_0402_5%

SKL_ULT

10 OF 20

PLT_RST# <23,26,28,32,36>

SKL-U

GPP_B11/EXT_PWR_GATE#

11 OF 20

11/28 add RSMRST protect circuit

SPOK <48>

2014/05/19 2015/12/31

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

SRTCRST#

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B2/VRALERT#

PCH_DPWROK_R

Rev_0.5 3

F43 E43

BA17

SUSCLK

PCH_XTAL24_IN

E37

PCH_XTAL24_OUT

E35

XCLK_BIASREF

E42

PCH_RTCX1

AM18

RTCX1 RTCX2

RTCRST#

Rev_0.5 3

SLP_LAN#

Compal Secret Data

PCH_RTCX2

AM20

PCH_SRTCRST#

AN18

PCH_RTCRST#

AM16

PCH_XTAL24_IN

PCH_XTAL24_OUT PCH_RTCX1

PM_SLP_S0#

AT11

PM_SLP_S3#

AP15

PM_SLP_S4#

BA16

PM_SLP_S5#

AY16

PM_SLP_SUS#

AN15

SLP_LAN#

AW15

SLP_WLAN#

BB17

PM_SLP_A#

AN16

PBTN_OUT#

BA15

AC_PRESENT_R

AY15

PM_BATLOW#

AU13

EC_PCIE_WAKE#

AU11

SM_INTRUDER#

AP16

EXT_PWR_GATE#

AM10

SOC_VRALERT#

AM11

Deciphered Date

SUSCLK <32>

1 2

RC96 2.7K_0402_1%

+1.0V_CLK5_F24NS

XCLK_BIASREF

1 2

RC97 60.4_0402_1%

<DB> stuf f f or c annonl ake 60oh m 1 %

<SI> change to SJ10000Q300 , CL=9p

PCH_RTCX2

1 2

RC92 1M_0402_5%

YC1

SJ10000IZ00

24MHZ 12PF 20PPM X3G024000DC1H

CC12

22P_0402_50V8J

GND

<Coc oa_1 020 > 32M use these part (SJ10000NM00, SJ10000MH00) just can meet <50k ohm spec 24M: SJ10000DI00, SJ10000CS00

PM_SLP_SUS# <13,26>

T87TP@ T88TP@

RC108 0_0402_5%

EC_PCIE_WAKE# <26,32>

T298TP@

GND

PBTN_OUT# <26>

CC13

22P_0402_50V8J

T254TP@ T255TP@ T256TP@ T257TP@ T258TP@

PM_SLP_S3# <12,26,35> PM_SLP_S4# <12,26,35,49> PM_SLP_S5# <26>

ACIN <26,37>

Compal Electronics, Inc.

Title

SKL-U(5/12)CLK,GPIO

Size

Document Number Re v

Custom

LA-D707P

Date: Sheet of

1 2

RC98 10M_0402_5%

YC2

32.768KHZ 9PF 10PPM 9H03200055

1 2

SJ10000Q800

CC15

6.8P_0402_50V8J

<PV> change CC15,CC16 to 6.8p <MV> change CC15,CC16 to 8.2p

9 60Wednesday, May 11, 2016

CC16

6.8P_0402_50V8J

v0.2

1 2

SKL-U

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

6 OF 20

HDA_SPKR

GSPI0_MOSI

GSPI1_MOSI

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A12/BM_BUSY#/ISH_GP6

HDA_SPKR <8,24>

ev_0.53

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

P2 P3 P4 P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

DGPU_PWR_EN

AC1

DGPU_HOLD_RST#

AC2 AC3 AB4

AY8 BA8 BB7

ODD_PWR

BA7

ODD_DA#

AY7 AW7

SOC_GPIOA12

AP13

TS_GPIO_CPU <20>

12/11_Delete TP

DGPU_PWR_EN <26,38,55,56> DGPU_HOLD_RST# <36>

GPU_PGD <56>

ODD_PWR <30>

ODD_DA# <30>

T122 TP@

+3VS

RC45 33K_0402_5%

1105_Modify schematic

CC14

1 2

<Cocoa_1 027> Follow #544669 GPIO I/O setting

CPU THERMAL SENSOR

+3VS

0.1U_0402_16V7K CC127

2200P_0402_50V7K

Thermal sensor: Main:SA000067P00, S IC NCT7718W MSOP 8P THEMAL SENSOR(Nuvoton) 2nd : SA00007WP00, S IC F75397M MSOP 8P THEMAL SENSOR(Fintek) 3rd : SA007810140, S IC G781P8F MSOP 8P TEMP. SENSOR(GMT)

Thermal sensor SMBus address -->100-1_100xb : 0x4C (x=0)Write Address(0x98h) (x=1)Read Address(0x99h)

UC3

H_THERMDA

H_THERMDC

CPU_THERM#

VDD

D+

D-

THERM#4GND

NCT7718W_MSOP8

SA000067P00

SCLK

SDATA

ALERT#

NMI_DBG#_CPU<5,26>

EC_SCI#<5,26>

<Cocoa_1127> remove EC_LID_OUT# function

<Cocoa_1 020> Follow BDW

EC_SMB_CK2

EC_SMB_DA2

THERMAL_ALERT#

EC_SMB_CK2 <7,19,22,26,37>

EC_SMB_DA2 <7,19,22,26,37>

DGPU_PWR_EN

EC_SCI# ODD_PWR ODD_DA#

RC44 10K_0402_5%

SOC_GPIOB21

WL_OFF# NMI_DBG#_CPU

RC382 10K_0402_5%

<DB >

1 2

RPC14

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

RPC12

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

+3VS

UC1F

AN8 AP7

GSPI0_MOSI

D D

C C

<DB> add TP by BIOS

T129TP@ T128TP@

WL_OFF#<32>

T133TP@ T132TP@

R5194

0_0402_5%

SOC_GPIOB21 GSPI1_MOSI

UART_0_CRXD_DTXD UART_0_CTXD_DRXD

WL_OFF#

UART_2_CRXD_DTXD UART_2_CTXD_DRXD

UART_2_CTXD_DRXD

UART_2_CRXD_DTXD

AM5

AH10

AH11 AH12

AF11 AF12

AP8 AR7

AN7 AP5 AN5

AB1 AB2

AB3

AD1 AD2 AD3 AD4

U7 U6

U8 U9

AH9

Functional Strap Definitions

SPKR (Internal Pull Down):

TOP Swap Override

0 = Disable TOP Swap mode.---> AAX05 Use

1 = Enable TOP Swap Mode.

GSPI0_MOSI (Internal Pull Down):

No Reboot

LPSS ISH

GPP_B15/GSPI0_CS# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL

SKL-U_BGA1356

Strap Pin

+3VS

RC117 100K_0402_5%

RC118 4.7K_0402_5%

RC201 150K_0402_1%

<Cocoa_1 020> 1K ohm for 400kH z speed/ 0.5k ohm for 1MHz speed

+3VS

+3V_PRIM

+3VS

0 = Disable No Reboot mode. --> AAX05 Use

1 = Enable No Reboot Mode. (PCH will disable the TCO Timer system re boot feature). This function is useful when running ITP/XDP.

B B

GSPI1_MOSI (Internal Pull Down):

<DB> Delete Win7 debug port

Boot BIOS Strap Bit

0 = SPI Mode --> AAX05 Use

1 = LPC Mode

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(6/12)GPIO

Size

Document Number Re v

Custom

LA-D707P

Date: Sheet of

10 60Wednesday, May 11, 2016

v0.2

UC1H

DB> Change to 0.22uF for Gen3

PEG_PRX_C_DTX_N0<36> PEG_PRX_C_DTX_P0<36> PEG_PTX_C_DRX_N0<36>

D D

PEG

LAN

WLAN

HDD

C C

ODD

B B

A A

PEG_PTX_C_DRX_P0<36>

PEG_PRX_C_DTX_N1<36> PEG_PRX_C_DTX_P1<36> PEG_PTX_C_DRX_N1<36> PEG_PTX_C_DRX_P1<36>

PEG_PRX_C_DTX_N2<36> PEG_PRX_C_DTX_P2<36> PEG_PTX_C_DRX_N2<36> PEG_PTX_C_DRX_P2<36>

PEG_PRX_C_DTX_N3<36> PEG_PRX_C_DTX_P3<36> PEG_PTX_C_DRX_N3<36> PEG_PTX_C_DRX_P3<36>

PCIE_PRX_DTX_N5<23>

PCIE_PRX_DTX_P5<23> PCIE_PTX_C_DRX_N5<23> PCIE_PTX_C_DRX_P5<23>

PCIE_PRX_DTX_N6<32>

PCIE_PRX_DTX_P6<32> PCIE_PTX_C_DRX_N6<32> PCIE_PTX_C_DRX_P6<32>

SATA_PRX_DTX_N0<30>

SATA_PRX_DTX_P0<30>

SATA_PTX_DRX_N0<30>

SATA_PTX_DRX_P0<30>

SATA_PRX_DTX_N1<30>

SATA_PRX_DTX_P1<30>

SATA_PTX_DRX_N1<30>

SATA_PTX_DRX_P1<30>

CC119 0.22U 6.3V K X5R 0402 PX@ CC146 0.22U 6.3V K X5R 0402 PX@

CC128 0.22U 6.3V K X5R 0402 PX@ CC93 0.22U 6.3V K X5R 0402 PX@

CC124 0.22U 6.3V K X5R 0402 PX@ CC92 0.22U 6.3V K X5R 0402 PX@

CC129 0.22U 6.3V K X5R 0402 PX@ CC118 0.22U 6.3V K X5R 0402 PX@

CC18 0.1U_0402_16V7K

CC17 0.1U_0402_16V7K

CC20 0.1U_0402_16V7K

CC19 0.1U_0402_16V7K

1 2

RC120 100_0402_1%

T291 TP@

XDP_PREQ#<5>

T154 TP@

XDP_PRDY#

XDP_PREQ#

SOC_GPIOA7

PEG_PRX_C_DTX_N0 PEG_PRX_C_DTX_P0

PEG_PTX_DRX_N0

PEG_PTX_DRX_P0

PEG_PRX_C_DTX_N1 PEG_PRX_C_DTX_P1

PEG_PTX_DRX_N1

PEG_PTX_DRX_P1

PEG_PRX_C_DTX_N2 PEG_PRX_C_DTX_P2

PEG_PTX_DRX_N2

PEG_PTX_DRX_P2

PEG_PRX_C_DTX_N3 PEG_PRX_C_DTX_P3

PEG_PTX_DRX_N3

PEG_PTX_DRX_P3

PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5

PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6

PCIE_RCOMPN PCIE_RCOMPP

When PCIE8/SATA1A is used as SATA Port 1 (ODD), then PCIE11/SATA1B (M.2 SSD) cannot be used as SATA Port 1.

PCIE/U SB3/SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

PCIE_RCOMPN

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL-U_BGA1356

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

SKL-U

8 OF 20

GPI O

USB_ OC0#

USB_ OC1#

USB_ OC2#

USB_ OC3#

DEVSLP 0

DEVSLP 1

DEVSLP 2

SATA _GP0

SATA _GP1

SATA _GP2

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

DEVICE CONTROL

USB2 Port 1 and Port 2

USB2 Port 3

NGFF SSD KEY B

ODD_ PLU G#

Compal Secret Data

Deciphered Date

Rev_0. 53

USB3_1_RXN USB3_1_RXP USB3_1_TXN

USB3_1_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN

USB3_4_TXP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6 AG3 AG4

A9 C9 D9 B9

J1 J2 J3

H2 H3 G4

USB2_COMP USB2_ID USB2_VBUSSENSE

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

DEVSLP0 DEVSLP1 DEVSLP2

SATA_GP0 ODD_PLUG# SATA_GP2

SATA_LED#

USB3_RX1_N <31> USB3_RX1_P <31>

USB3_TX1_N <31> USB3_TX1_P <31>

USB20_N1 <31> USB20_P1 <31>

USB20_N2 <31> USB20_P2 <31>

USB20_N3 <33> USB20_P3 <33>

USB20_N4 <32> USB20_P4 <32>

USB20_N5 <20> USB20_P5 <20>

USB20_N6 <20> USB20_P6 <20>

USB20_N7 <33> USB20_P7 <33>

1 2

RC119 113_0402_1%

USB2.0/USB3.0

USB2.0

USB2.0 ( on small board )

WLAN

Camera

Touch Screen

Card Reader

<SI> follow EDS to add 1K ohm PD

USB2_ID

T243 TP@

T241 TP@

ODD_PLUG# <30>

SATA_LED# <33>

<DB> PU

DEVSLP1 SOC_GPIOA7

SATA_LED# SATA_GP0 SATA_GP2 ODD_PLUG#

USB_OC1# USB_OC3# USB_OC0# USB_OC2#

USB2_VBUSSENSE

RC362 10K_0402_5% RC361 10K_0402_5%

1128_Add pull high resistor

Compal Electronics, Inc.

Title

SKL-U(7/12)PCIE,USB,SATA

Size

Document Number Re v

Custom

LA-D707P

Date : Sheet o f

1 2

RC20 0_0402_5%

1 2

RC21 0_0402_5%

1 2 1 2

RPC13

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

RPC20

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

11 60Wednesday, May 11, 2016

+3VS

+3V_PRIM

v0.2

+1.0V_PRIM TO +1.0V_VCCSTU

+1.2V_VDDQ

1211_Delete jump RC147

D D

1 2

SYSON<26,35,49>

PM_SLP_S4#<9,26,35,49>

SUSP#<13,26,35,49>

PM_SLP_S3#<9,26,35>

C C

1210_Delete jump RC146

RC142 0_0402_5%

1 2

RC144 0_0402_5%@

1 2

RC168 0_0402_5%

1 2

RC194 0_0402_5%@

0.1U_0402_25V6

CC151

+5VALW

+1.8V_PRIM

CC98

CC99

1U_0402_6.3V6K

CC97

EN_1.0V_VCCSTU

EN_1.8VS

+1.0VS_VCCIO

R5188 0_0603_5%@

I (Max) : 0.04 A(+1.0V_VCCSTU)

ON(Max) : 25 mohm

R V drop : 0.001 V

UC5

VIN1

ON1

VBIAS

ON2

VIN2

EM5209VF_DFN14_2X3

SA00007PM00

I (Max) : 0.536 A(+1.8VS) RON(Max) : 25 mohm V drop : 0.013 V

VOUT1 VOUT1

CT1

GND

CT2

VOUT2 VOUT2

GPAD

14 13

CC95

10P_0402_50V8J

CC94

1000P_0402_50V7K

0.1U_0402_25V6

1 2

@ESD@

CC156

+1.0V_VCCSTU+1.0V_PRIM

+1.8VS

CC100

0.1U_0402_25V6

<DB> Delete RC145

0.1U_0402_25V6

CC96

+1.2V_VDDQC

+1.0V_VCCST

+1.0VS_VCCIO

+1.2V_VCCSFR_OC

+1.0V_VCCSFR

<Cocoa_1113> Per 543977_SKL_PDDG_Rev0_91, change CC95 value from 1000pf to 10pf for meet <= 65us timing for +1.0V_VCCSTU power rail.

+1.0V_VCCSTU +1.0V_VCCST

1 2

RC140 0_0402_5%

AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51

AM40

A18

A22

AL23

K20 K21

UC1N

VDDQ_AU23 VDDQ_AU28 VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51

VDDQC

VCCST

VCCSTG_A22

VCCPLL_OC

VCCPLL_K20 VCCPLL_K21

SKL-U_BGA1356

+1.0V_PRIM TO +1.0VS_VCCSTG / +1.0VS_VCCIO

+5VALW

+1.0V_PRIM

0.1U_0402_25V6

CC88

B B

EC_S0IX_EN<26>

For Verify S0IX

+1.0VS_VCCIO

SUSP#

<Cocoa_1027> connect to EC, check /w EC

10U_0402_6.3V6M

CC27

1 2

RC186 0_0402_5%

1 2

RC187 0_0402_5%

10U_0402_6.3V6M

CC28

1U_0201_6.3V6K

CC29

1U_0402_6.3V6K

Imax : 2.77 A

CC117

1U_0201_6.3V6K

CC30

CC31

I (Max) : 3 A(+1.0VS_VCCIO) RON(Max) : 6.2 mohm V drop : 0.019 V

UC6

VIN1

VIN2

VIN thermal

VBIAS

TPS22961DNYR_WSON8

Part Number = SA00007XR00

PSC SideBSC Side

1U_0402_6.3V6K

1U_0201_6.3V6K

CC32

1U_0402_6.3V6K

CC33

VOUT

GND

CC34

1U_0402_6.3V6K

CC35

<PV> change short pad

+1.0VS_VCCSTG_IO

RC189

1 2

Imax : 3 A

<DB> change +1.35V_VDDQ

RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev0_53

+1.2V_VDDQ

1U_0402_6.3V6K

CC36

CC47 Follow 543016_SKL_U_Y_PDG_0_9

+1.0VS_VCCIO

0_0805_5%

RC208

1 2

near pin A22

1 2

CC89 0.1U_0402_25V6

1 2

CC90 0.1U_0402_25V6

+1.2V_VDDQC

0_0603_5%

BSC Side

1U_0402_6.3V6K

CC47

1 2

RC143 0_0402_5%

<DB> change +1.35V_VDDQ

+1.2V_VDDQ

10U_0603_6.3V6M

CC37

CC38

CPU POWER 3 OF 4

14 OF 20

PSC Side

1U_0402_6.3V6K

+1.0V_VCCSFR

1U_0402_6.3V6K

10U_0603_6.3V6M

CC39

SKL-U

VSSSA_SENSE VCCSA_SENSE

CC48

Rev_0. 53

VCCIO_SENSE

VSSIO_SENSE

RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev1.0

CC55

10U_0603_6.3V6M

CC40

+1.0VS_VCCIO

AK28

VCCIO

AK30

VCCIO

AL30

VCCIO

AL42

VCCIO

AM28

VCCIO

AM30

VCCIO

AM42

VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

+VCC_SA

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE VCCSA_SENSE

<DB> change +1.35V_VDDQ

BSC SidePSC Side

10U_0603_6.3V6M

1U_0402_6.3V6K

10U_0603_6.3V6M

CC42

CC41

1U_0201_6.3V6K

CC43

T124 TP@ T125 TP@

VSSSA_SENSE <52> VCCSA_SENSE <52>

+1.0VS_VCCIO

1U_0402_6.3V6K

CC44

BSC SidePSC Side

1U_0402_6.3V6K

CC56

1U_0402_6.3V6K

CC46

CC45

A A

Security Classification

2014/12/11 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/12/11 2015/12/31

Compal Secret Data

Deciphered Date

+1.35V_VDDQ_CPU : 10UF/6.3V/0603 *6 1UF/6.3V/0402 * 4

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet o f

Compal Electronics, Inc.

SKL-U(8/12)Power

Document Number Re v

LA-D707P

v0.2

12 60Wednesday, May 11, 2016

+1.0V_PRIM

1 2

RC148 0_0603_5%

D D

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC152 0_0603_5%

1 2

RC190 0_0603_5%

C C

Imax : 2.57A

near pin AF18, AF19,V20 ,V21

+1.0V_APLL

22U_0603_6.3V6M

CC142

+1.0V_CLK5_F24NS

22U_0603_6.3V6M

CC135

+1.0V_CLK4_F100OC

22U_0603_6.3V6M

CC136

+1.0V_PRIM

+3V_PRIM

1 2

CC134

CC130

1U_0402_6.3V6K

CC67

CC137

1U_0402_6.3V6K

CC76

RC150 0_0402_5%

1U_0402_6.3V6K

CC72

+3V_PRIM

1 2

RC197 0_0402_5%

1 2

RC154 0_0402_5%

1 2

RC161 0_0402_5%

1 2

RC163 0_0402_5%

<Diner-DB> change to +3V_PRIM

+1.0V_MPHYAON

1 2

RC175 0_0402_5%

B B

1 2

RC169 0_0603_5%

1 2

RC162 0_0402_5%

+1.0V_CLK6_24TBT

1U_0402_6.3V6K

CC86

+1.0V_DTS

1U_0402_6.3V6K

CC87

22U_0603_6.3V6M

1U_0402_6.3V6K

CC75

CC139

CC138

1 2

RC172 0_0402_5%

1 2

RC167 0_0402_5%

1 2

RC171 0_0402_5%

Follow 543016_SKL_U_Y_PDG_0_9

+1.0V_PRIM +3V_PRIM +1.8V_PRIM

22U_0603_6.3V6M

A A

22U_0603_6.3V6M

CC112

CC111

22U_0603_6.3V6M

CC114

CC113

22U_0603_6.3V6M

CC115

CC116

+3VS

1 2

RC178 0_0402_5%

+3VALW

1 2

RC173 0_0603_5%

Follow 543016_SKL_U_Y_PDG_0_9

+3V_HDA

+3V_PGPPA

+3V_SPI

+3V_PGPPB

1U_0402_6.3V6K

+3V_PGPPC

1U_0402_6.3V6K

+3V_1.8V_PGPPD

1U_0402_6.3V6K

+3V_PGPPE

1U_0402_6.3V6K

+3V_PRIM_RTC

1U_0402_6.3V6K

CC63 1U_0201_6.3V6K

CC102

CC73

1 2

RC206 0_0402_5%@

CC103

CC74

CC77

+3VS_PGPPA

+3VALW_DSW

+1.8V_PRIM

near p in K15, L15

near pin N18

near pin AF20, AF21,T19, T20

near pin N15, N16, N17,P15, P16

+1.0V_PRIM

+1.0V_APLL

+1.0V_PRIM

+3VALW_DSW

+3V_HDA

+3V_SPI

+1.0V_PRIM

+3V_PRIM

+1.0V_PRIM

CC147

CC80

22U_0603_6.3V6M

CC148

+1.0V_PRIM

22U_0603_6.3V6M

CC81

1U_0402_6.3V6K

CC61

1U_0402_6.3V6K

CC68

1U_0201_6.3V6K

CC141

22U_0603_6.3V6M

CC82

+1.0VO_DSW

1U_0402_6.3V6K

+1.0V_MPHYAON

CC85

<DB>Check Power Rail

Per 543016_SKL_U_Y_PDG_0_9

VCCRTC does not exceed 3.2 V From PDG

22U_0603_6.3V6M

1U_0402_6.3V6K

Power Rail Vo ltag e

+CHG RTC

BAT5 4C(V F)

+3VL _RT C

3.38 3V(M AX)

240 mV

3.14 3V

Result : Pass

+1.0V_PRIM

1U_0201_6.3V6K

CC91

UC1O

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

SKL-U_BGA1356

1U_0201_6.3V6K

CC7

SKL-U

CPU POWER 4 OF 4

15 OF 20

RTC Battery

CC7 Close UC1.AK19.

+RTCVCC

15mils

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE VCCPGPPF VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

MAX. 8000mil

+RTCBATT_R

DC1

BAV70W 3P C/C_SOT-323

SC600000B00

Rev_0.5 3

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19

AA1

AK17

AK19 BB14

BB10

CC71 0.1U_0402_10V7K

A14

K19

L21

N20

L19

A10

PRIMCORE_VID0

AN11

PRIMCORE_VID1

AN13

<DB> RTC BAT Conn

JRTC1

LOTES_AAA-BAT-054-K01

SP07000H700

1K_0402_5%

RC19

15mils15mils

+3VL

1209

_follow G group GPIO

powe rail to +3V_PRIM

+3V_PGPPA +3V_PGPPB +3V_PGPPC +3V_1.8V_PGPPD +3V_PGPPE +1.8V_PRIM +3V_PRIM

+3V_PRIM

+1.0V_DTS

+1.8V_PRIM

+3V_PRIM_RTC

+RTCVCC

1 2

+1.0V_CLK6_24TBT

+1.0V_APLL

+1.0V_CLK4_F100OC

+1.0V_CLK5_F24NS

+1.0V_CLK6_24TBT

T130 TP@ T131 TP@

CONN@

+RTCBATT

For SD CARD

20mils

+RTCBATT

+3VALW TO +3V_PRIM

0.1U_0201_10V6K

0_0805_5%

0_0805_5%@

+3V_PRIM

13 60Wednesday, May 11, 2016

0.1U_0402_25V6

CC51

v0.2

I (Max) : 0.46 A(+3V_PRIM) RDS(Typ) : 65 mohm

+3VALW+5VALW

V drop : 0.03 V

1U_0402_6.3V6K

For DS3

0.1U_0201_10V6K

CC78

1 2

PCH_PWR_EN<26,35,51>

PM_SLP_SUS#<9,26>

SUSP#<12,26,35,49>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RC191 0_0402_5%

1 2

RC174 0_0402_5%@

1 2

RC392

Compal Secret Data

2014/12/11 2015/12/31

Compal Secret Data

0_0402_5%

Deciphered Date

CC52

+1.2V_VDDQ

1U_0402_6.3V6K

CC150

CC50

EN_3V_PRIM

UC4

VIN1

ON1

VBIAS

ON2

VIN2

EM5209VF_DFN14_2X3

SA00007PM00

1 2

RC141 0_0402_5%@

+3VALW

1 2

RC393

For NON-DS3

+3V_PRIMJP

1 2

RC159

CC53

CC149

1 2

For DS3

+1.2V_VCCSFR_OC

CC49

VOUT1

CT1

1000P_0402_50V7K

GND

CT2

1000P_0402_50V7K

VOUT2

GPAD

Compal Electronics, Inc.

Title

SKL-U(9/12)Power

Size

Document Number Re v

Custom

LA-D707P

Date: Sheet o f

UC1L

A30

VCC_A30

A34

VCC_A34

D D

T123 TP@

T121 TP@

For CPU2+3e SKU

C C

SVID ALERT

B B

A39

A44 AK33 AK35 AK37 AK38 AK40

AL33 AL37

AL40 AM32 AM33 AM35 AM37 AM38

G30

K32

AK32

AB62

P62 V62

H63

G61

AC63 AE63

AE62

AG62

AL63

AJ62

+1.0V_VCCST

RC179 56_0402_5%

VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RSVD_K32

RSVD_AK32

VCCOPC_AB62 VCCOPC_P62 VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE VSSOPC_SENSE

VCCEOPIO VCCEOPIO

VCCEOPIO_SENSE VSSEOPIO_SENSE

SKL-U_BGA1356

Place the PU resistors close to CPU

SKL-U

CPU POWER 1 OF 4

12 OF 20

Rev_0. 53

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VCC_SENSE VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

B63 A63 D64

G20

SOC_SVID_ALERT# SOC_SVID_CLK SOC_SVID_DAT

Trace Length < 25 mils

VCCSENSE <52> VSSSENSE <52>

SOC_SVID_CLK <52>

+1.0VS_VCCIO

VCCGT_SENSE<52> VSSGT_SENSE<52>

Trace Length < 25 mils

VCCGT_SENSE VSSGT_SENSE

+VCC_GT +VCC_GT+VCC_CORE +VCC_CORE

AA63 AA64 AA66 AA67 AA69 AA70

AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71

M62 N63 N64 N66 N67 N69

A48 A53 A58 A62 A66

K48 K50 K52 K53 K55 K56 K58 K60 L62 L63 L64 L65 L66 L67 L68 L69 L70 L71

J43 J45 J46 J48 J50 J52 J53 J55 J56 J58 J60

J70 J69

UC1M

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT_SENSE VSSGT_SENSE

SKL-U_BGA1356

CPU POWER 2 OF 4

SKL-U

13 OF 20

Rev_0. 53

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70 VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56

VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63

VCCGTX_BB57

VCCGTX_BB66

VCCGTX_SENSE

VSSGTX_SENSE

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

VCCGTX_SENSE

AK62

VSSGTX_SENSE

AL61

For CPU2+3e SKU

T155 TP@ T219 TP@

SOC_SVID_ALERT#

SVID DATA

A A

SOC_SVID_DAT

1 2

RC180 220_0402_5%

+1.0V_VCCST

RC181 100_0402_1%

SOC_SVID_ALERT#_R <52>

Place the PU resistors close to CPU

SOC_SVID_DAT <52>

(To VR)

Security Classification

2014/05/19 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet o f

SKL-U(10/12)Power,SVID

Document Number Re v

LA-D707P

14 60Wednesday, May 11, 2016

v0.2

D D

A5 A67 A70 AA2 AA4

AA65 AA68 AB15 AB16 AB18 AB21

AB8

AD13 AD16 AD19 AD20 AD21 AD62

AD8

AE64 AE65 AE66 AE67

C C

B B

AE68 AE69

AF1

AF10 AF15 AF17

AF2 AF4

AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71

AH13

AH6 AH63 AH64 AH67 AJ15 AJ18 AJ20

AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69

AK8

AL2 AL28 AL32 AL35 AL38

AL4 AL45 AL48 AL52 AL55 AL58 AL64

AJ4

UC1P

GND 1 OF 3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-U_BGA1356

SKL-U

Rev_0. 53 Rev_0. 53

AL65

VSS

AL66

VSS

AM13

VSS

AM21

VSS

AM25

VSS

AM27

VSS

AM43

VSS

AM45

VSS

AM46

VSS

AM55

VSS

AM60

VSS

AM61

VSS

AM68

VSS

AM71

VSS

AM8

VSS

AN20

VSS

AN23

VSS

AN28

VSS

AN30

VSS

AN32

VSS

AN33

VSS

AN35

VSS

AN37

VSS

AN38

VSS

AN40

VSS

AN42

VSS

AN58

VSS

AN63

VSS

AP10

VSS

AP18

VSS

AP20

VSS

AP23

VSS

AP28

VSS

AP32

VSS

AP35

VSS

AP38

VSS

AP42

VSS

AP58

VSS

AP63

VSS

AP68

VSS

AP70

VSS

AR11

VSS

AR15

VSS

AR16

VSS

AR20

VSS

AR23

VSS

AR28

VSS

AR35

VSS

AR42

VSS

AR43

VSS

AR45

VSS

AR46

VSS

AR48

VSS

AR5

VSS

AR50

VSS

AR52

VSS

AR53

VSS

AR55

VSS

AR58

VSS

AR63

VSS

AR8

VSS

AT2

VSS

AT20

VSS

AT23

VSS

AT28

VSS

AT35

VSS

AT4

VSS

AT42

VSS

AT56

VSS

AT58

VSS

16 OF 20

AT63 AT68

AT71 AU10 AU15 AU20 AU32 AU38

AV1 AV68 AV69 AV70 AV71 AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57

AW6 AW60 AW62 AW64 AW66

AW8 AY66

B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71

BA1 BA10 BA14 BA18

BA2 BA23 BA28 BA32 BA36

F68

BA45

UC1Q

GND 2 OF 3

SKL-U_BGA1356

SKL-U

17 OF 20

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

G10 G22 G43 G45 G48

G52 G55 G58

G60 G63 G66 H15 H18 H71

K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71

J11 J13 J25 J28 J32 J35 J38 J42

L11 L16 L17

UC1R

GND 3 OF 3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-U_BGA1356

SKL-U

18 OF 20

Rev_0. 53

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

A A

Security Classification

2014/05/19 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet o f

SKL-U(11/12)GND

Document Number Re v

LA-D707P

15 60Wednesday, May 11, 2016

v0.2

D D

T272 TP@ T273 TP@ T274 TP@

CFG3<5>

T275 TP@ T276 TP@ T277 TP@ T278 TP@ T279 TP@ T281 TP@ T280 TP@ T283 TP@ T282 TP@ T284 TP@ T285 TP@

T286 TP@ T287 TP@

T288 TP@

C C

XDP_ITP_PMODE<5>

B B

T289 TP@

T192 TP@

T194 TP@ T196 TP@

T198 TP@ T200 TP@

T205 TP@ T206 TP@

T209 TP@

T211 TP@

T213 TP@ T300 TP@

T217 TP@ T218 TP@

T220 TP@ T222 TP@

T224 TP@ T226 TP@

CFG_RCOMP

XDP_ITP_PMODE

CFG4

E68 B67 D65 D67 E70 C68 D68 C67

G69

G68 H70 G71 H69 G70

E63

E66

E60

AY2 AY1

K46 K45

AL25 AL27

C71 B70

A52

BA70 BA68

G65

E61

F71

F70

F63

F66

D1 D3

F60

J71 J68

F65

F61

UC1S

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2 RSVD_AY1

RSVD_D1 RSVD_D3

RSVD_K46 RSVD_K45

RSVD_AL25 RSVD_AL27

RSVD_C71 RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70 RSVD_TP_BA68

RSVD_J71 RSVD_J68

VSS_F65 VSS_G65

RSVD_F61 RSVD_E61

SKL-U_BGA1356

RESERVED SIGNALS-1

SKL-U

19 OF 20

Rev_0. 53

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4 RSVD_C4

RSVD_A69 RSVD_B69

RSVD_AY3

RSVD_D71 RSVD_C70

RSVD_C54 RSVD_D54

VSS_AY71

ZVM#

RSVD_TP_AW71 RSVD_TP_AW70

MSM#

PROC_SELECT#

TP5 TP6

TP4

TP1 TP2

BB68 BB69

AK13 AK12

BB2 BA3

AU5 AT5

D5 D4 B2 C2

B3 A3

AW1

E1 E2

BA4 BB4

A4 C4

BB5

A69 B69

AY3

D71 C70

C54 D54

AY4 BB3

AY71 AR56

AW71 AW70

AP56 C64

PM_ZVM#

PM_MSM# SKL_CNL#

T156 TP@ T157 TP@

T158 TP@ T159 TP@

T162 TP@ T163 TP@

T166 TP@ T167 TP@

T170 TP@ T252 TP@

T174 TP@

T179 TP@ T183 TP@

T195 TP@ T197 TP@

T201 TP@ T203 TP@

1 2

RC182 0_0402_5%

T207 TP@ T208 TP@

T210 TP@ T301 TP@

1 2

RC183 0_0402_5%

T225 TP@

T333 TP@ T223 TP@

T230 TP@

1 2

RC184 100K_0402_5%

+1.0V_VCCST

Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0

AW69 AW68

AU56

AW48

C7 U12 U11 H11

For 2+3e Solution PM_ZVM# PM_MSM#

UC1T

RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48 RSVD_C7 RSVD_U12 RSVD_U11 RSVD_H11

SKL-U_BGA1356

SPARE

SKL-U

20 OF 20

Rev_0. 53

RSVD_F6

RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12 RSVD_F52

F6 E3 C11 B11 A11 D12 C12 F52

T227 TP@

CFG_RCOMP

CFG4

A A

1 2

RC185 49.9_0402_1%

1 2

RC193 1K_0402_1%

Display Port Presence Strap

CFG4

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

Security Classification

2014/05/19 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet o f

SKL-U(12/12)RSVD

Document Number Re v

LA-D707P

16 60Wednesday, May 11, 2016

v0.2

+ 40 hidden pages

Compal LA-D707P Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual