Compal LA-D704P Schematic

A

1 1

2 2

B

C D E

Kabylake-U M/B Schematics Document

Intel ULV Processor with DDR4 SODIMMx2

Date : 2016/05/11

3 3

Project :Diner_Crepe1.1(15")

4 4

A

B

Version : 4.0

BDL50 : LA-D704P

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C D

2011/06/29 2011/06/29

Compal Secret Data

Deciphered Date

Tiiitllle

Siiize Document Number

Custom

LA-D704P

Compal Electronics,Inc.

Cover Page

Sheet 1 of 60Date: Wednesday, May 11, 2016

E

Rev

v0.2

A

B

C D E

Compal Confidential

Model Name :
File Name : LA-D704P

1 1

2 2

3 3

Diner_Crepe1.1(15")

VRAM

gDDR3 x4pcs

256Mbx16(4Gb)
512Mbx16(8Gb)

eDP/LVDS

CONN

CRT CONN

HDMI CONN

P.40~42

JL VD S1

P.20

FHD

JCR T 1

P. 22 CRT

JH DM I1

1Ch 64bits 1.5V

eDP to LVDS Transmitter

DP to VGA Transmitter

HDMI

P.21

RTL 8111HSH(Giga)
RTL8166EH(10/100)

NGFF WLAN+BT
(KeyE)

AMD

R16M-M1-70

R16M-M1-30

LVDS@

D3(R7)
D3(R5)

P.36~40

UT 1

RTD2132N P. 19

eDP@

eDP@

U410 4

RTD2168 P.22

LAN

JW LAN 1

P.32

UL1

P.23

U666

PCIex4

Port#1~#4

PCIe2.0:5Gb/s
PCIe3.0:8Gb/s

eDP x1Lane

2.7Gb/s

eDPx2Lane

2.7Gb/s

DDIx2Lane Port 2

DDIx4Lane Port 1

297MHz

PCIex1 Port #5
PCIeGen1:2.5Gb/s
PCIeGen2:5Gb/s

PCIex1 Port#6
PCIe1.0:2.5Gb/s
PCIe2.0:5Gb/s

Kabylake-U

Skylake-U

1356P BGA

KBL-U 15W2+2

SKL-U 15W 2+2

SMbus

1MHz

UC 1

Dual Channel Interleaved

DDR4 2133MHz 1.2V

SATA 3.0

GEN11.5Gb/s
GEN23Gb/s

GEN36Gb/s

USB3.0

5Gb/s

USB2.0
480Mb/s

Port0

Port1

Port1

Port2

Port3

Port4

Port5

Port6

Port7

DDR4-SO-DIMM X 2

2.5" SATA HDD

ODD

USB3.0 port

(onboard-1)

USB2.0 port

(onboard-2)

USB2.0 Port

(sub board)

Bluetooth

Camera

Touch Screen

Card reader
RTS5141

(sub board)

JHDD

P. 30

JO DD

P.30

JUS B1

P.31

JUS B2

P.31

JIO 1

P.33

JWLAN1

P.32

JL VD S1

P.20

JL VD S1

P.20

JIO 1

P.33

P.17~18

Port1

FAN

JK B1

P. 27

JT P1

P.27

P.34

JP WR

P.33

UC3

PS2

B

EC ENE

KB9022QD

SLB9665TT2.0

SPI ROM
8MBytes

Int.KBD

TouchPad

Lid switch

(sub board)

4 4

A

Thermal sensor

NCT7718W P.10

UK1

P.26

TPM

P.28

*default FWTP M

U4

UC 2

P. 07

LPC
33MHz

SPI
50MHz

UA1

HDA 24MHz

SecurityClassification

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS, IIINC... AND CONTAINS CONFIIIDENTIIIAL
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS, IIINC... NEITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS, IIINC...

C D

2011/06/29 2011/06/29

HDA Aduio codec

ALC3227

Compal Secret Data

Deciphered Date

P.24

Internal SPK

Combo Jack

Tiiitllle

Size Document Number

Custom

JSPK 1

JH P

Compal Electronics,Inc.

Block Diagrams

LA-D704P

E

Rev

v0.2

60Date: Wednesday, May 11, 2016 Sheet 2 of

5

D D

4

3

2

1

@ 0 ohm

R

CPU

PU801

+3VS

DGPU_PWR_EN

C C

GPIO78

U4103

EN

NMOS

B B

1. +3VS_VGA

PU801

PXS_PWREN#

+1.05VS

PU8

2. VGA_CORE

3. +1.05VS_VGA

U4102

GPU

GPU_PWRGD

1.8V_PWRGD

GPU_RST

@

R

0 ohm

DGPU_PWROK

GPIO77

CPU

DGPU_HOLD_RST#

GPIO80

PLT_RST#

4. +1.5VS_VGA

+1.5VS

EN_1.8V

R

C

U4102

5. +1.8VS_VGA

PU8

A A

SecurrriiitttyClllassiiifffiiicatttiiion

IIIssuedDate

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIDENTIAL AND
TRADE SECRET IIINFORMATION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATION IIIT CONTAIIINS

5

4

3

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,,IIINC...

2

Compalll SecretttDattta

Deciphered Date

Compal Electroni cs, Inc.

Tiiitttllle

Siiize DocumentttNumberrr

D

Dattte::: Wedne sday, M ay 11, 2016 Sheettt 43 o fff 60

1

LA-D707P

RSVD

Rev

v0.2

5

AC

Adapter 19.5V

P.45

D D

Charge

Charger

+19.5VB

BQ24725

P.47

DC
Battery
3S1P
4S1P

P.46

C C

Discharge

+2.5V_PG

SM_PG_C TRL

4

3

RT8243AZQW

ECON

EN

Vout

Vin

+3VALW

PCH_PWR _EN

Vin

EN

SY8032A

DC/DC

(+5VALW/+3VALW)

Vout

PGOOD

P.48

Vin DDR4

RT8027P

EN S5

EN S3

Vin +1.0V_PRIM

+1.8V_P G +1.0V_VS_PG_PWR

SY8286

EN

PGOOD

PGOOD

PM_SLP_ S4#

Vout

Vout

P.49

Vout

P.50

+3VALW

SPOK

Vin

SY8032A

EN

+0.6V_0.6VS

+1.2V_VDDQ

DDR_PWROK

+1.0V_P RIM

Vout

PGOOD

P.51

Vout

PGOOD

P.49

+1.8V_P RIM

+1.8V_P G

+2.5V

+2.5V_P G

2

CPU DC/DC
NCP81206 52~54

INPUTS OUTP UTS

B+

SYSTEM DC/DC
RT8243AZQW

INPUTS OUTPUTS

B+ +5VALW/+3VALW

SYSTEM DC/DC
RT8207P / 8032

INPUTS OUTPUTS

B+

SYSTEM DC/DC
SY8286

VCC_SA
VCC_GT
VCC_VORE

+1.2V_VDDQ
+0.6V_0.6

INPUTS OUTPUTS

B+ +1.0V_PRIM

SYSTEM DC/DC
SY8032A

INPUTS OUTPUTS

+3VALW +1.8V_PRIM

SYSTEM DC/DC
RT8880

+2.5V
VS

56~57

1

48

49

50

51

INPUTS OUTP UTS

B+ +VGA_CORE

SYSTEM DC/DC
SY8286

55

INPUTS OUTP UTS

B+ +1.5VS_VGA

Vin

Vout

B B

VR_ON

NCP81206 Vout

VR_ON

DC/DC

(CPU_CORE)

Vout

PGOOD

+VCC_CO RE

+VCC_GT

+VCC_SA

VR_PWRGD

P.52,53

Vin RT8880

Vout

+VGA_CO RE

DC/DC

(VGA_CORE)

DGPU_PWR_EN

A A

DGPU_PWR_EN

5

EN

Vin

SY8286

DC/DC

(VGA_RAM)

EN

4

P.56

PGOOD

Vout

PGOOD

P.55

GPU_PGD

+1.5VS_ VGA

VRAM_PG

3

2

1

[Diner-PWR Sequence_SKL-U22_DDR3L_Volume_NON CS]

5 4 3 2 1

G3->S0

+3VL_RTC

SOC_RTC RST#

+19VB

+3VL P/+ 5VLP

D D

EC_ON

+5VAL W/+ 3VALW/+3 VALW_ DSW

PM_ BATLOW #

PCH_PWR _EN (SLP_SU S#)

+3V_ PRIM

+1.8V_PRIM

EXT_PWR_GATE #

+1.0V_M PHYPL L

+1.0V_PRIM_C ORE

+1.0V_PRIM

SUSACK#

PCH_DPW ROK

EC_RSM RST#

C C

AC_PRESENT

ON/OFF

PBTN_OUT#

PM_ SLP_ S5#

ESPI_RST#

PM_ SLP_ S4#

SYSON

+1.0V_VCCST/ +1.0 V_VCC SFR

+1.35V_ VDDQ/ +1.3 5V_VC CSFR _OC

PM_ SLP_ S3#

SUSP #

+1. 0VS_ VCCS TG

+1.0VS_ VCCIO

B B

+5VS /+3 VS/+ 1.5VS/+ 1.05 VS

EC_VCCS T_PG

VR_ON

SM_PG_ CTRL

+0.675V S_VTT

+VCC_SA

+VCC_CORE

+VCC_G T

VR_P WRGD

PCH_PWR OK

H_CPUPW RGD

SYS_PW ROK

A A

SUS_ST AT#

SOC_PLT RST#

tPCH01_Min : 9 ms

tPCH06_Min : 200 us

tPCH04_Min : 9 ms

Pull-up to DS W w ell if notimp lement ed.

If EXT_PW R_GAT E# Tof fmin is too small, Pwr
gate m ay c hoose to completely ignore it

tPCH34_Max : 20 ms

tPCH02_Min : 10 ms

tPCH03_Min : 10 ms

tPLT02 _Min : 0 ms Max : 90 ms

Minim um duratio n of PWRBT N# assertio n = 16 mS. PWR BTN# can assert before or after RSMR ST#

tPCH18_Min : 90 us

tCPU04 Min : 100 ns

T4 = Min : 20ms Max : 3 0ms(E C Control)

tCPU19 Max : 100 ns

tCPU18 Max : 35 us

tCPU16 Min : 0 ns

tCPU10 Min : 1ms

tCPU09 Min : 1 ms

S0->S3/DS3

S0/DS3 ->S0

S0->S5

+3VL_RTC

SOC_RTC RST#

+19VB

+3VL P/+ 5VLP

EC_ON

+5VAL W/+ 3VALW/+3 VALW_ DSW

PM_ BATLOW #

PCH_PWR _EN (SLP_SUS#)

+3V_ PRIM

+1.8V_PRIM

EXT_PWR_GATE #

+1.0V_M PHYPL L

+1.0V_PRIM_C ORE

+1.0V_PRIM

SUSACK#

PCH_DPW ROK

EC_RSM RST#

AC_PRESENT

ON/OFF

PBTN_OUT#

PM_ SLP_ S5#

ESPI_RST#

PM_ SLP_ S4#

SYSON

+1.0V_VCCST/ +1.0 V_VCC SFR

+1.35V_ VDDQ/ +1.3 5V_VC CSFR _OC

PM_ SLP_ S3#

SUSP #

+1. 0VS_ VCCS TG

+1.0VS_ VCCIO

+5VS /+3 VS/+ 1.5VS/+ 1.05 VS

EC_VCCS T_PG

VR_ON

SM_PG_ CTRL

+0.675V S_VTT

+VCC_SA

+VCC_CORE

+VCC_G T

VR_P WRGD

PCH_PWR OK

H_CPUPW RGD

SYS_PW ROK

SUS_ST AT#

SOC_PLT RST#

SecuriiitttyClllassifffiiicatiiion

IIIssued Dattte

THIIIS SH EET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPER TY OF COMPAL ELECTRONIIICS, IIINC... AN D CONTAINS CONFIIIDENTIIIAL AND
TRADE SEC RET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPET ENT DIIIVISION OF R&D
DEPARTME NT EXC EPT A S AUTHORIIIZED BY COMPAL ELECTRONIIICS, IIINC... NEITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAINS

5 4 3 2 1

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY W IIITHOUT PRIIIOR WRIIITTEN CONSE NT OF COMPAL ELECTRONIIICS, IIINC...

Compalll Secret D ata

DeciiipheredDa ttte

Tiiitttllle

Siiize Documenttt Numberrr

Custom

LA-D707P

Compal Electronics,Inc.

HW Reserve

Sheettt 4 o fff60Dattte::: Wednesday, May 11, 2016

Rev

v0.2

A

Power rail
+RTCVCC
VIN

BATT+ X X
B+

+VL X X
+3VL X X
+5VALW
+3VALW
+3VALW_EC

1 1

+3V_PCH PCH_PWR_EN X
+1.2V_VDDQ
+5VS SUSP# PM_SLP_S3#
+3VS SUSP# PM_SLP_S3#
+1.5VS SUSP# PM_SLP_S3#
+1.05VS SUSP# PM_SLP_S3#
+0.6V_0.6VS SUSP#
+VCC_CORE

Control (EC)
X X
X X

X X

EC_O N
EC_O N
EC_O N

SYSON

X VR12.5_VR_ON

Source (CPU)

X
X
X

PM_SLP_S5#/PM_SLP_S4#

BOM Structure Table (1/2)

Funct i on

DGPU SKU

UMA SKU U MA@

SPI_IO3(MOW36)

Crystal (DIS) XTALPX@

Crystal XTAL@
GreenCLK(UMA) GCLK@
Green CLK(DIS) GCLKPX@

2 2

TPM T PM@

UCPU1

3 3

CPU

UK1:+3VALW_EC(+3VL)

4 4

EC

Stuf f Un-Stuff

PX@

ES@

SMBCLK

R7

SMBDATA

R8

SML0CLK

R9

SML0DATA

W2

SML1CLK

W3

SML1DATA

V3

I2C_0_SCL

I2C_0_ SDA

U6
U7

I2C_1_SCL

I2C_1_ SDA

U9
U8

EC_SMB_CK2
EC_SMB_DA2

79
80

EC_SMB_CK1

77

EC_SMB_DA1

78

A

+3VS

R=1K

+3VS

R=499

+3VS

R=1K

+3VS

R=1K

+3VL_EC

R=2.2K

+3VS

2N7002

Touch Screen

QKKS@

UC1

SA00009PJ10

ES_Q KKS

S IC A32 FJ8067702739720 QKKS G0 2.4G S IC A32 FJ8067702739718 QKJ W G0 2.6G

QS_i3@

UC1

i3_7100U_QS_QLDP

SA0000A3810
S IC A32 FJ8067702739738 QLDP H0 2.4G S IC A32 FJ8067702739739 QLDM H0 2.5G S IC A32 FJ8067702739740 QLDN H0 2.7G

R30@

U666

R16M-M1- 30 FCBG A R16M- M1-70 FCBG A

SA000087T90 SA000098V 10
S IC A32 216-0867-071 R16M-M1-30 FCBGA S IC A32 216-0864-032 R16M-M1-70FCBGA

+3VS

+3VS

R=10K

2N7002

+3VALW

+3VS

R=2.2K

2N7002

+3VS

R=2.2K

EC_SMB_CK2
EC_SMB_DA2

DGPU_PEX_RST#

2N7002

Thermal Sensor :NCT7718W_MSOP8

R=100

BAT

Charger

B

QKJW@

UC1

ES_Q KJW

QS_i5@

UC1

i5_7200U_QLDM

SA0000A3710

R70@

U666

PCH_SMBCLK
PCH_SMBDATA

TP_SMBCLK
TP_SMBDAT

+3VGS_AON

R=2.2K

I2CS_SCL
I2CS_SDA

B

SOC SMBUS Address Table

SOC_SMBUS NetName

SMBCLK
SMBDATA

SML0CLK
SML0DATA

SML1CLK
SML1DATA

SA00009UR00

SO-DIMM B

Touch Pad

dGPU

Address :0x4C

i7_7500U_QLDN

SA0000A3420

PowerwRail

+3VS

+3VS ME FW 0x48/0x49

+3VS

SKLPV2@

UC1

SA000092P60

SKY_ i7_ 6500 U_SR2EZ

S IC FJ8066201930408 SR2EZ D1 2.5G BGA

QS_i7@

UC1

C

( T B C )

w

Device Ad dress (7 bit)

DIM M1

Touch PAD T BC TBC TBC

EC TBC TBC TBC

DGPU

TBC TBC

TBC TBC TBC

Address (8bit)
Write Read

0xA2

0x90/0x92

TBC

D

EC SMBUS Address Table

EC_SMBUS Port Power Rail Device Address (7 bit)

SMB US Port 1

SMBUS Port 2 +3VS

PCH TBC TBC TBC

DAX

KBL

Part Number = DA6001LS000
PCB 1RU LA-D707P REV0 M/B6

ROYALTY HDMIW /LOGO45@

Part Number Descr ipti on

HDMI W/Log o:RO 0000 002HM

RO00 00002 HM

RO0000003HM

R30R1@

U666

R16M-M1- 30 FCBG A R16M- M1-70 FCBG A

SA000087TC0 SA000098V30
S IC A32 216-0867-071 R16M-M1-30 FCBGA S IC A32 216-0864-032 R16M-M1-70FCBGA

R30R3@

U666

R16M-M1- 30 F CBG A

SA000087TB0
S IC A32 216-0867-071 R16M-M1-30 FCBGA S IC A32 216-0864-032 R16M-M1-70FCBGA

i3R1@

UC1

SA000092N70

ES_Q KKS

S IC A32 FJ8067702739720 QKKS G0 2.4G S IC A32 FJ8067702739720 QKK S G0 2.4G
i3R3@

UC1

SA000092N80

ES_Q KKS

S IC A32 FJ8067702739720 QKKS G0 2.4G S IC A32 FJ8067702739720 QKK S G0 2.4G

ZZZ

ZZZ

HY2@ MIC2@ SAM2@ HY4@ MIC4@

2G HYN IX 2G MICRON 2G SAMSUNG 4G Hynix 4G Micr on

X7667032L01 X7667032L02 X7667032L05 X7667032L03 X7667032L04

ZZZ ZZZ ZZZ

R3HY2@ R3MIC2@ R3SAM2@ R3HY4@ R3MIC4@

2G HYN IX 2G MICRON 2G SAMSUNG 4G Hynix 4G Micr on

X7667032L23 X7667032L24 X7667032L25 X7667032L21 X7667032L22

DAX

SKL

Part Number = DAZ1O200301
PCB BDL50 LA-D704P LS-C701P/C703P02

SKL@

R70R1@

U666

R70R3@

U666

R16M-M1- 70 F CBG A

SA000098V40

i5R1@

UC1

SA000092O70

ES_Q KKS

i5R3@

UC1

SA000092O80

ES_Q KKS

ZZZ

ZZZ

ZZZ ZZZ

Power State

STATE

SIGNAL

S0 (Full ON)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Sof t OFF)

i7R1@

UC1

SA000092P60

ES_Q KKS

S IC A32 FJ8067702739720 QKK S G0 2.4G
i7R3@

UC1

SA000092P70

ES_Q KKS

S IC A32 FJ8067702739720 QKK S G0 2.4G

ZZZ

Load BOM Opt i on Table

BOM Number Load BOM Opt ion

4519YN32L01(UMA)

4519YN32L02(DIS)

Securiiity Clllassiiification

Issued Date

THIS SHEE T OF ENGINE ERING DRAW ING IS THE PROPRI ETARY PROPER TY OF COMPAL ELECTRONICS,,, INC. AND CONTAINS CO NFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHE ET MAY NOT B E TRANSFERE D FROM THE CUS TODY OF THE COMPETE NT DIVISION OF R& D
DEPARTMENT E XCEPT AS AUTHORI ZED BY C OMPAL ELECTRONICS,,, INC. NEITHER THI S SHEET NOR THE INFO RMATION IT CO NTAINS

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT P RIOR WRI TTEN CONSENT OF COMP AL ELECTRONICS,,,I NC.

2011/06/29

Compalll SecretData

Deciphered Date

D

E

( T B C )

+VALW

0x16

0x12

TBC
0x4C

+VS Clock

+V

OFF OFF
OFF OFF OFF
OFF OFF OFF

+3VL_EC

BAT

CHGR

dGP U

Thermal

Sensor

PCH TBC

SLP_S4#

SLP_S3#

SLP_S5#

HIGH HIGH HIGH ON ON ON ON

LOW HIGH HIGH ON ON
LOW LOW HIGH ON
LOW LOW LOW ON

<USB2.0port>

USB2.0port

1 USB 2.0/3.0 USB 2.0/3.0
2 USB 2.0/3.0 USB 2.0/3.0
3 USB 2.0 OFFBOARD USB 2.0 OFFBOARD
4 WLAN WLAN
5 Camera Camera
6 TOUCH SCREEN TOUCH SCREEN
7 CR CR
8
9
10

DESTINATION

UMA Dis

<PCI-E,SATA,USB3.0/CLK>

PCI-E

Lane#

1 1 USB3.0 USB3.0 X
2 2 USB3.0 USB3.0 X
3 3 USB3.0(Charger) USB3.0(Charger) X
4 4 USB3.0(IOBoard )USB3.0(IOBoard ) X
5 1 5 X GPU(DIS only)
6 2 6 X GPU(DIS only)
7 3 X GPU(DIS only)
8 4 X GPU(DIS only)
9 5 LAN LAN CLK1
10 6 WLAN WLAN CLK2
11 7 0 2.5"HDD 2.5"HDD X
12 8 1 ODD ODD X
13 9
14 10 X X X
15 11 1* X X X
16 12 2 X

SATA USB3.0

2011/06/29

DESTINATION

UMA Dis

Card reader(PCI-E) Card reader(PCI-E)

Tiiitttllle

Size Documenttt Number

Custom

Compal Electronics,Inc.

Notes List

LA-D707P

E

CLK

CLK0

CLK3

Rev

v0.2

60Dattte::: W ednesday, May 11, 2016 Sheettt 3 o fff

A

B

C D E

UC1A

UC1D

D63

CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#

C55

BPM#[0]
BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

GPP_E3/CPU_GP0

BA5

GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP

SKL-U_BGA1356

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKL-U_BGA1356

SKL-U

CPUMISC

4 OF20

<21> PCH_DPB_N2
<21> PCH_DPB_P2

SOC_DP1_CTRL_DATA(Internal Pull Down):

<HDMI>

Display Port B Detected

1 1

0 = Port B is not detected.
1 = Port B is detected.

<eDP to CRT>

<21> PCH_DPB_N1
<21> PCH_DPB_P1
<21> PCH_DPB_N0
<21> PCH_DPB_P0
<21> PCH_DPB_N3
<21> PCH_DPB_P3

<22> PCH_DPC_N0
<22> PCH_DPC_P0
<22> PCH_DPC_N1
<22> PCH_DPC_P1

SOC_DP2_CTRL_DATA(Internal Pull Down):
Display Port C Detected
0 = Port C is not detected.
1 = Port C is detected.

HDMI DDC (Port B)

<21> PCH_DDPB_CLK

<21> PCH_DDPB_DAT

+3VS

<DB> DP port C enable

+1.0V_VCCST

1

RC2

2 2

COMPENSATION PU FOR eDP

+1.0VS_VCCIO

RC1 1

CAD note:
Trace width=20 mils,Spacing=25mil,Maxlength=100mils

2 H_THERMTRIP#

1K_0402_5%

2EDP_COMP

24.9_0402_1%

<26> PROCHOT#

+1.0VS_VCCIO

2

1

1

RC3
1K_0402_5%

1 2

RC4

DS11
CK0402101V05_0402-2

ESD@

SCV00001K00

2

RC6 2
RC7 2
RC8 2

T248 TP@

<26> H_PECI

499_0402_1%

T25 TP@
T270 TP@

T271 TP@
T250 TP@
T249 TP@

T30 TP@

T40 TP@

1 49.9_0402_1% CPU_POPIRCOMP AT16RC5 2
1 49.9_0402_1% PCH_OPIRCOMP AU16

1 49.9_0402_1% EDRAM_OPIO_RCOMP H66

1 49.9_0402_1% EOPIO_RCOMP H65

@ RC200 1

RC199 1

PCH_DDPB_CLK
PCH_DDPB_DAT

2 2.2K_0402_5%
2 2.2K_0402_5%

CRT@

EDP_COMP

H_PECI A54

H_PROCHOT#_R C65
H_THERMTRIP# C63

SOC_OCC# A65

XDP_BPM#0

XDP_BPM#1 D55

SOC_GPIOE3 A6 A7

SOC_GPIOB4 AY5

SKL-U

DDI

DISPLA Y SIDE BANDS

JTAG

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST#

1 OF20

Rev_0. 53

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

JTAGX

EDP

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

B61
D60

A61
C60

B59

PCH_JTAG_TCK1

B56

SOC_XDP_TDI

D59
A56

C59
C61

A59

Rev_0. 53

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXN
EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

CPU_XDP_TCK0
SOC_XDP_TDI

SOC_XDP_TDO
SOC_XDP_TMS

SOC_XDP_TRST#

SOC_XDP_TDO
SOC_XDP_TMS

SOC_XDP_TRST#
CPU_XDP_TCK0

C47
C46
D46

C45
A45
B45
A47
B47

E45

F45
B52
G50

F50

DDI2_AUX_DN

E48
F48

DDI2_AUX_DP

G46
F46

L9 PCH_DDPB_HPD

DDI2_HPD

L7

NMI_DBG#_CPU

L6

EC_SCI#

N9

EDP_HPD

L10
R12

ENBKL

R11

ENVDD_CPU

U13

TP@ T259
TP@ T260
TP@ T261
TP@ T262
TP@ T263

TP@ T264
TP@ T265
TP@ T266
TP@ T267
TP@ T268
TP@ T269

EDP_CPU_LANE_N0_C <19>
EDP_CPU_LANE_P0_C <19>
EDP_CPU_LANE_N1_C <19>
EDP_CPU_LANE_P1_C <19>

EDP_CPU_AUX#_C <19>
EDP_CPU_AUX_C <19>

TP@ T228

DDI2_AUX_DN <22>
DDI2_AUX_DP <22>

PCH_DDPB_HPD <21>
DDI2_HPD <22>
NMI_DBG#_CPU <10,26>
EC_SCI# <10,26>
EDP_HPD <19>

ENBKL <26>
BKL_PWM_CPU <20>
ENVDD_CPU <20>

RC123 1 @ 2 100K_0402_5% ENVDD_CPU

RC124 1 2 100K_0402_5% ENBKL

<eDP>

From HDMI

From eDP to CRT

From eDP

<DB> Check

XDP CONN

3 3

+1.0VS_VCCIO

1 51_0402_5% SOC_XDP_TMSRC11 2 @

RC15 2 1 51 +-1% 0402 SOC_XDP_TDO
RC364 2 @ 1 51_0402_5% CPU_XDP_TCK0

+1.0V_PRIM

RC14 2 @ 1 51_0402_5% XDP_PREQ#

RC31 1 @ 2 1K_0402_5% XDP_ITP_PMODE

4 4

A

RC365 2 @ 1 51_0402_1% SOC_XDP_TRST#

RC35 2 1 51_0402_1% CPU_XDP_TCK0
RC37 2 @ 1 51_0402_5% PCH_JTAG_TCK1
RC366 1 @ 2 0_0402_5% CFG3

1 51_0402_5% SOC_XDP_TDIRC13 2 @

SD000008H80

XDP_PREQ# <11>

XDP_ITP_PMODE <16>

SD000008H80

CFG3 <16>

B

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C D

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Tiiitllle

Siiize Document Number

Custom

Compal Electronics, Inc.

SKL-U(1/12)DDI,MSIC,XDP,EDP

LA-D707P

Rev

Sheet 5 o f 60Date: Wednesday, May 11, 2016

E

v0.2

5

Interleaved Memory

4

3

2

1

Interleaved Memory

D D

UC1B

<17> DDR_A_D[0..15]

<17> DDR_A_D[16..31]

C C

<17> DDR_A_D[32..47]

<17> DDR_A_D[48..63]

B B

A A

AL71

DDR_A_D0

DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21

DDR_A_D22 BA63
DDR_A_D23 BB63
DDR_A_D24 BA61
DDR_A_D25 AW61
DDR_A_D26 BB59
DDR_A_D27 AW59
DDR_A_D28 BB61
DDR_A_D29 AY61
DDR_A_D30 BA59
DDR_A_D31 AY59
DDR_A_D32 AY39
DDR_A_D33 AW39
DDR_A_D34 AY37
DDR_A_D35 AW37
DDR_A_D36 BB39
DDR_A_D37 BA39
DDR_A_D38 BA37
DDR_A_D39 BB37
DDR_A_D40 AY35
DDR_A_D41 AW35
DDR_A_D42 AY33
DDR_A_D43 AW33
DDR_A_D44 BB35
DDR_A_D45 BA35
DDR_A_D46 BA33
DDR_A_D47 BB33
DDR_A_D48 AY31
DDR_A_D49 AW31
DDR_A_D50 AY29
DDR_A_D51 AW29
DDR_A_D52 BB31
DDR_A_D53 BA31
DDR_A_D54 BA29
DDR_A_D55 BB29
DDR_A_D56 AY27
DDR_A_D57 AW27
DDR_A_D58 AY25
DDR_A_D59 AW25
DDR_A_D60 BB27
DDR_A_D61 BA27
DDR_A_D62 BA25
DDR_A_D63 BB25

SB00000QJ00,S TR DRC5115E0L NPNSOT323-3

AL68
AN68
AN69
AL70
AL69
AN70
AN71
AR70
AR68
AU71
AU68
AR71
AR69
AU70
AU69

BB65
AW65
AW63

AY63

BA65

AY65

RC905

100K_0402_5%

DDR_PG_CTRL

DDR0_DQ[0]
DDR0_DQ[1]
DDR0_DQ[2]
DDR0_DQ[3]
DDR0_DQ[4]
DDR0_DQ[5]
DDR0_DQ[6]
DDR0_DQ[7]
DDR0_DQ[8]
DDR0_DQ[9]
DDR0_DQ[10]
DDR0_DQ[11]
DDR0_DQ[12]
DDR0_DQ[13]
DDR0_DQ[14]
DDR0_DQ[15]
DDR0_DQ[16]/DDR0_DQ[32]
DDR0_DQ[17]/DDR0_DQ[33]
DDR0_DQ[18]/DDR0_DQ[34]
DDR0_DQ[19]/DDR0_DQ[35]
DDR0_DQ[20]/DDR0_DQ[36]

DDR0_DQ[21]/DDR0_DQ[37]
DDR0_DQ[22]/DDR0_DQ[38]
DDR0_DQ[23]/DDR0_DQ[39]
DDR0_DQ[24]/DDR0_DQ[40]

DDR0_DQ[25]/DDR0_DQ[41]

DDR0_DQ[26]/DDR0_DQ[42]

DDR0_DQ[27]/DDR0_DQ[43]
DDR0_DQ[28]/DDR0_DQ[44]
DDR0_DQ[29]/DDR0_DQ[45]
DDR0_DQ[30]/DDR0_DQ[46]
DDR0_DQ[31]/DDR0_DQ[47]
DDR0_DQ[32]/DDR1_DQ[0]

DDR0_DQ[33]/DDR1_DQ[1]
DDR0_DQ[34]/DDR1_DQ[2]

DDR0_DQ[35]/DDR1_DQ[3]
DDR0_DQ[36]/DDR1_DQ[4]
DDR0_DQ[37]/DDR1_DQ[5]
DDR0_DQ[38]/DDR1_DQ[6]
DDR0_DQ[39]/DDR1_DQ[7]
DDR0_DQ[40]/DDR1_DQ[8]

DDR0_DQ[41]/DDR1_DQ[9]
DDR0_DQ[42]/DDR1_DQ[10]

DDR0_DQ[43]/DDR1_DQ[11]
DDR0_DQ[44]/DDR1_DQ[12]
DDR0_DQ[45]/DDR1_DQ[13]
DDR0_DQ[46]/DDR1_DQ[14]
DDR0_DQ[47]/DDR1_DQ[15]
DDR0_DQ[48]/DDR1_DQ[32]

DDR0_DQ[49]/DDR1_DQ[33]
DDR0_DQ[50]/DDR1_DQ[34]

DDR0_DQ[51]/DDR1_DQ[35]
DDR0_DQ[52]/DDR1_DQ[36]
DDR0_DQ[53]/DDR1_DQ[37]
DDR0_DQ[54]/DDR1_DQ[38]
DDR0_DQ[55]/DDR1_DQ[39]
DDR0_DQ[56]/DDR1_DQ[40]

DDR0_DQ[57]/DDR1_DQ[41]
DDR0_DQ[58]/DDR1_DQ[42]

DDR0_DQ[59]/DDR1_DQ[43]
DDR0_DQ[60]/DDR1_DQ[44]
DDR0_DQ[61]/DDR1_DQ[45]
DDR0_DQ[62]/DDR1_DQ[46]
DDR0_DQ[63]/DDR1_DQ[47]

SKL-U_BGA1356

@

2

1

1

RC906

100K_0402_5%

@

2

+1.2V_VDDQ

1

RC904

@

100K_0402_5%

2 2

@

UC9

SB000008 E10

MMBT3904WH NPN SOT323-3

DDRCH - A

2 OF 20

1 SM_PG_CTRL3

<Cocoa_1020>
PDG#543016, ODT: CPU side no connect, DRAM side connect to VDDQ(Memory down); FET+R(SO-DIMM)

RC32
470_0402_5%

1

RC33

SKL-U

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0 _DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0 _DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0 _DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0 _DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1 _DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1 _DQSP[3]

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]

DDR1_ALERT#

DRAM_RESET#
DDR_RCOMP[0]

DDRCH - B

3 OF 20

2 DDR_DRAMRST#_R

0_0402_5%

1

2

DDR_RCOMP[1]
DDR_RCOMP[2]

CC155

0.1U_0201_10V6K

@ESD@

9/8 Modify base on ESD Request

PLACE NEAR TO SoC

AN45 DDR_B_CLK#0

DDR1_CKN[0]

AN46 DDR_B_CLK#1

DDR1_CKN[1]

AP45 DDR_B_CLK0

DDR1_CKP[0]

AP46 DDR_B_CLK1

DDR1_CKP[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]

DDR1_MA[3]
DDR1_MA[4]

DDR1_PAR

DDR_DRAMRST#_R <17,18>

DDR_B_CKE0

AN56

AP55 DDR_B_CKE1

AN55

AP53

DDR_B_CS#0

BB42

DDR_B_CS#1

AY42

DDR_B_ODT0

BA42

AW42 DDR_B_ODT1

DDR_B_MA5

AY48

DDR_B_MA9

AP50

DDR_B_MA6

BA48

DDR_B_MA8

BB48

DDR_B_MA7

AP48

DDR_B_BG0

AP52

DDR_B_MA12

AN50
AN48 DDR_B_MA11

AN53 DDR_B_ACT#

AN52 DDR_B_BG1

BA43 DDR_B_MA 13
AY43 DDR_B_MA15_CAS#
AY44 DDR_B_MA14_WE#
AW44 DDR_B_MA16_RAS#

BB44 DDR_B_BA0

AY47 DDR_B_MA2

BA44 DDR_B_BA1

AW46 DDR_B_MA1 0

AY46 DDR_B_MA1

BA46 DDR_B_MA0

BB46 DDR_B_MA3
BA47 DDR_B_MA4

AH66 DDR_B_DQS#0

AH65 DDR_B_DQS0

AG69 DDR_B_DQS#1

AG70 DDR_B_DQS1

AR66 DDR_B_DQS#2

AR65 DDR_B_DQS2

AR61 DDR_B_DQS#3

AR60 DDR_B_DQS3

AT38 DDR_B_DQS#4

AR38 DDR_B_DQS4

AT32 DDR_B_DQS#5

AR32 DDR_B_DQS5

AR25 DDR_B_DQS#6
AR27 DDR_B_DQS6
AR22 DDR_B_DQS#7
AR21 DDR_B_DQS7

AN43 DDR_B_ALERT#

AP43 DDR_B_PAR
AT13 DDR_DRAMRST#
AR18 SM_RCOMP0 RC38 1
AT18 SM_RCOMP1 RC39 1
AU18 SM_RCOMP2 RC40 1 2 100_0402_1%

SKL-U

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0 _DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0 _DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1 _DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1 _DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1 _DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1 _DQSP[5]

Rev_0 .53 Rev_0 .53

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]

DDR0_MA[3]
DDR0_MA[4]

DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

AU53 DDR_A_CLK#0
AT53 DDR_A_CLK0
AU55 DDR_A_CLK#1
AT55 DDR_A_CLK1

DDR_A_CKE0

BA56

DDR_A_CKE1

BB56
AW56
AY56

DDR_A_CS#0

AU45

DDR_A_CS#1

AU43

DDR_A_ODT0

AT45

DDR_A_ODT1

AT43

DDR_A_MA5

BA51

DDR_A_MA9

BB54

DDR_A_MA6

BA52

DDR_A_MA8

AY52

DDR_A_MA7

AW52

DDR_A_BG0

AY55

DDR_A_MA12

AW54

DDR_A_MA11

BA54
BA55 DDR_A_ACT#

AY54 DDR_A_BG1

AU46 DDR_A_MA13
AU48 DDR_A_MA15_CAS#
AT46 DDR_A_MA14_WE#
AU50 DDR_A_MA16_RAS#

AU52 DDR_A_BA0

AY51 DDR_A_MA2

AT48 DDR_A_BA1

AT50 DDR_A_MA10

BB50 DDR_A_MA1

AY50 DDR_A_MA0

BA50 DDR_A_MA3
BB52 DDR_A_MA4

AM70 DDR_A_DQS#0
AM69 DDR_A_DQS0
AT69 DDR_A_DQS#1

AT70 DDR_A_DQS1
BA64 DDR_A_DQS# 2
AY64 DDR_A_DQS2
AY60 DDR_A_DQS# 3
BA60 DDR_A_DQS3
BA38 DDR_A_DQS# 4
AY38 DDR_A_DQS4
AY34 DDR_A_DQS# 5
BA34 DDR_A_DQS5
BA30 DDR_A_DQS# 6
AY30 DDR_A_DQS6
AY26 DDR_A_DQS# 7
BA26 DDR_A_DQS7

AW50 DDR_A_ALERT#

AT52 DDR_A_PAR

AY67 +0.6V_VREF CA

AY68

BA67 +0.6V_B_VREFDQ
AW67 DDR_PG_CTRL

For VTT power control

DDR_PG_CTRL 2

TP@ T 14
TP@ T 15

+0.6V_VREFCA
+0.6V_B_VREFDQ

0.1U_0201_10V6K 2 1 CC57
UC7

1

NC

A

3

GND

SN74AUP1G07DCKR_SC70-5

SA00007U R00

DDR_A_CLK#0 <17 >
DDR_A_CLK0 <17>
DDR_A_CLK#1 <17 >
DDR_A_CLK1 <17>

DDR_A_CKE0 < 17>
DDR_A_CKE1 < 17>

DDR_A_CS#0 < 17>
DDR_A_CS#1 < 17>
DDR_A_ODT0 <17>
DDR_A_ODT1 <17>

DDR_A_MA5 <17>
DDR_A_MA9 <17>
DDR_A_MA6 <17>
DDR_A_MA8 <17>
DDR_A_MA7 <17>
DDR_A_BG0 <17>
DDR_A_MA12 <17>
DDR_A_MA11 <17>
DDR_A_ACT# <17>
DDR_A_BG1 <17>

DDR_A_MA13 <17>
DDR_A_MA15_CAS# <17>
DDR_A_MA14_WE# <17>
DDR_A_MA16_RAS# <17>
DDR_A_BA0 <17>
DDR_A_MA2 <17>
DDR_A_BA1 <17>
DDR_A_MA10 <17>
DDR_A_MA1 <17>

DDR_A_MA0 <17>
DDR_A_MA3 <17>
DDR_A_MA4 <17>

DDR_A_DQS#0 <17>
DDR_A_DQS0 <17>
DDR_A_DQS#1 <17>
DDR_A_DQS1 <17>
DDR_A_DQS#2 <17>
DDR_A_DQS2 <17>
DDR_A_DQS#3 <17>
DDR_A_DQS3 <17>
DDR_A_DQS#4 <17>
DDR_A_DQS4 <17>
DDR_A_DQS#5 <17>
DDR_A_DQS5 <17>
DDR_A_DQS#6 <17>
DDR_A_DQS6 <17>
DDR_A_DQS#7 <17>
DDR_A_DQS7 <17>

DDR_A_ALERT# <17>
DDR_A_PAR <17 >

+1.2V_VDDQ

5

VCC

4

Y

<18> DDR_B_D[0..15]

<18> DDR_B_D[16..31]

<18> DDR_B_D[32..47]

<18> DDR_B_D[48..63]

+3VS

1

RC394
100K_0402_5%

2

SM_PG_CT RL <49>

DDR_B_D0 AF65
DDR_B_D1 AF64
DDR_B_D2 AK65
DDR_B_D3 AK64
DDR_B_D4 AF66
DDR_B_D5 AF67
DDR_B_D6 AK67
DDR_B_D7 AK66
DDR_B_D8 AF70
DDR_B_D9 AF68
DDR_B_D10 AH71
DDR_B_D11 AH68
DDR_B_D12 AF71
DDR_B_D13 AF69
DDR_B_D14 AH70
DDR_B_D15 AH69
DDR_B_D16 AT66
DDR_B_D17 AU66
DDR_B_D18 AP65
DDR_B_D19 AN65
DDR_B_D20 AN66
DDR_B_D21 AP66
DDR_B_D22 AT65
DDR_B_D23 AU65
DDR_B_D24 AT61
DDR_B_D25 AU61
DDR_B_D26 AP60
DDR_B_D27 AN60
DDR_B_D28 AN61
DDR_B_D29 AP61
DDR_B_D30 AT60
DDR_B_D31 AU60
DDR_B_D32 AU40
DDR_B_D33 AT40
DDR_B_D34 AT37
DDR_B_D35 AU37
DDR_B_D36 AR40
DDR_B_D37 AP40
DDR_B_D38 AP37
DDR_B_D39 AR37
DDR_B_D40 AT33
DDR_B_D41 AU33
DDR_B_D42 AU30
DDR_B_D43 AT30
DDR_B_D44 AR33
DDR_B_D45 AP33
DDR_B_D46 AR30
DDR_B_D47 AP30
DDR_B_D48 AU27
DDR_B_D49 AT27
DDR_B_D50 AT25
DDR_B_D51 AU25
DDR_B_D52 AP27
DDR_B_D53 AN27
DDR_B_D54 AN25
DDR_B_D55 AP25
DDR_B_D56 AT22
DDR_B_D57 AU22
DDR_B_D58 AU21
DDR_B_D59 AT21
DDR_B_D60 AN22
DDR_B_D61 AP22
DDR_B_D62 AP21
DDR_B_D63 AN21

UC1C

DDR1_DQ[0]/DDR0_DQ[16]
DDR1_DQ[1]/DDR0_DQ[17]
DDR1_DQ[2]/DDR0_DQ [18]
DDR1_DQ[3]/DDR0_DQ [19]
DDR1_DQ[4]/DDR0_DQ[20]
DDR1_DQ[5]/DDR0_DQ[21]
DDR1_DQ[6]/DDR0_DQ [22]
DDR1_DQ[7]/DDR0_DQ [23]
DDR1_DQ[8]/DDR0_DQ[24]
DDR1_DQ[9]/DDR0_DQ[25]

DDR1_DQ[10]/DDR0_DQ[26]
DDR1_DQ[11]/DDR0_DQ[27]
DDR1_DQ[12]/DDR0_DQ[28]
DDR1_DQ[13]/DDR0_DQ[29]
DDR1_DQ[14]/DDR0_DQ[30]
DDR1_DQ[15]/DDR0_DQ[31]
DDR1_DQ[16]/DDR0_DQ[48]
DDR1_DQ[17]/DDR0_DQ[49]
DDR1_DQ[18]/DDR0_DQ[50]
DDR1_DQ[19]/DDR0_DQ[51]
DDR1_DQ[20]/DDR0_DQ[52]
DDR1_DQ[21]/DDR0_DQ[53]
DDR1_DQ[22]/DDR0_DQ[54]
DDR1_DQ[23]/DDR0_DQ[55]
DDR1_DQ[24]/DDR0_DQ[56]
DDR1_DQ[25]/DDR0_DQ[57]
DDR1_DQ[26]/DDR0_DQ[58]
DDR1_DQ[27]/DDR0_DQ[59]
DDR1_DQ[28]/DDR0_DQ[60]
DDR1_DQ[29]/DDR0_DQ[61]
DDR1_DQ[30]/DDR0_DQ[62]
DDR1_DQ[31]/DDR0_DQ[63]
DDR1_DQ[32]/DDR1_DQ[16]
DDR1_DQ[33]/DDR1_DQ[17]
DDR1_DQ[34]/DDR1_DQ[18]
DDR1_DQ[35]/DDR1_DQ[19]
DDR1_DQ[36]/DDR1_DQ[20]
DDR1_DQ[37]/DDR1_DQ[21]
DDR1_DQ[38]/DDR1_DQ[22]
DDR1_DQ[39]/DDR1_DQ[23]
DDR1_DQ[40]/DDR1_DQ[24]
DDR1_DQ[41]/DDR1_DQ[25]
DDR1_DQ[42]/DDR1_DQ[26]
DDR1_DQ[43]/DDR1_DQ[27]
DDR1_DQ[44]/DDR1_DQ[28]
DDR1_DQ[45]/DDR1_DQ[29]
DDR1_DQ[46]/DDR1_DQ[30]
DDR1_DQ[47]/DDR1_DQ[31]

DDR1_DQ[48]
DDR1_DQ[49]
DDR1_DQ[50]

DDR1_DQ[51]
DDR1_DQ[52]

DDR1_DQ[53]

DDR1_DQ[54]
DDR1_DQ[55]
DDR1_DQ[56]

DDR1_DQ[57]

DDR1_DQ[58]
DDR1_DQ[59]

DDR1_DQ[60]
DDR1_DQ[61]
DDR1_DQ[62]

DDR1_DQ[63]

SKL-U_BGA1356

+1.2V_VDDQ

DDR_DRAMRST#

1

2

DDR_B_CLK#0 <18>
DDR_B_CLK#1 <18>
DDR_B_CLK0 < 18>
DDR_B_CLK1 < 18>

DDR_B_CKE0 < 18>

TP@ T17
TP@ T18

DDR_B_CKE1 < 18>

DDR_B_CS#0 < 18>
DDR_B_CS#1 < 18>
DDR_B_ODT0 <18>
DDR_B_ODT1 <18>

DDR_B_MA5 <18>
DDR_B_MA9 <18>
DDR_B_MA6 <18>
DDR_B_MA8 <18>
DDR_B_MA7 <18>
DDR_B_BG0 <18>
DDR_B_MA12 <18>
DDR_B_MA11 <188>
DDR_B_ACT# <18>
DDR_B_BG1 <18>

DDR_B_MA13 <18>
DDR_B_MA15_CAS# <18>
DDR_B_MA14_WE# <18>
DDR_B_MA16_RAS# <18>
DDR_B_BA0 <18>
DDR_B_MA2 <18>
DDR_B_BA1 <18>
DDR_B_MA10 <18>
DDR_B_MA1 <18>
DDR_B_MA0 <18>
DDR_B_MA3 <18>
DDR_B_MA4 <18>

DDR_B_DQS#0 <18>
DDR_B_DQS0 <18>
DDR_B_DQS#1 <18>
DDR_B_DQS1 <18>
DDR_B_DQS#2 <18>
DDR_B_DQS2 <18>
DDR_B_DQS#3 <18>
DDR_B_DQS3 <18>
DDR_B_DQS#4 <18>
DDR_B_DQS4 <18>
DDR_B_DQS#5 <18>
DDR_B_DQS5 <18>
DDR_B_DQS#6 <18>
DDR_B_DQS6 <18>
DDR_B_DQS#7 <18>
DDR_B_DQS7 <18>

DDR_B_ALERT# <18>
DDR_B_PAR <1 8>

2 121_0402_1%
2 80.6_0402_1%

DDR_PG_CTRL 1 2

CC70 100P_040 2_50V8J

From ESD Team Request

/10 Modify for DDR4

8/10 Modify for DDR4

9/8 Modify

8/10 Modify for DDR4

@ESD@

SecurityClllassiiifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING D RAWING IIIS THE PROPRIIIETARY P ROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRAD E SECRE T IIINFORMATIIION... THIIIS SHE ET MAY NOT BE TRA NSFERE D FROM THE CUSTODY OF THE COMPETE NT DIIIVIIISIIION OF R&D
DEPARTMENT E XCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NO R THE IIINFORMATIIION IIIT CONTAIIINS

5

4

MAY BE US ED BY OR DIIISCLOSED TO ANY THIIIRD PARTY W ITHOUT PRIIIOR WRIIITTEN CON SENT OF COMPAL ELECTRONIIICS,,, IIINC...

3

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Tiiitllle

Size Document Number

Custom

2

Date: Wednesday, May 11, 2016

SKL-U(2/12)DDRIII

LA-D707P

1

Sheet 6 o f

Rev

v0.2

60

5 4 3 2 1

UC1E

PCH_SPI_CLK
PCH_SPI_SO

PCH_SPI_SI

PCH_SPI_SIO2 AW2

PCH_SPI_SIO3

PCH_SPI_CS0# AU3

D D

AW3

AV2
AV3
AU4
AU2

AU1

12/11_Delete TP

<26> EC_KBRST#

To TPM

<26,28> SERIRQ

to SPI ROM UC2

C C

B B

A A

PCH_SPI_CS0#_R 1
PCH_SPI_CS0#_R 2

PCH_SPI_SO_R 3
PCH_SPI_SO_R 4

PCH_SPI_HOLD#
PCH_SPI_SI_R
PCH_SPI_SI_R

PCH_SPI_WP# 2 1 PCH_SPI_SIO2

SPI ROM ( 8MByte Only)

PCH_SPI_CS0#_R 1
PCH_SPI_SO_R 2
PCH_SPI_WP# 3

PCH_SPI_CLK 2

EON SA 000046 400 S IC FL 6 4M EN2 5Q64-1 04HIP SOP 8P
MXIC SA 00006N 100 S IC FL 6 4M MX25 L6473E M2I-10 G SOP 8P
WINBON D SA00 0039A3 0 S IC FL 64M W25Q64 FVSSI Q SOIC 8P SP I ROM
Micron SA000 05L100 S IC FL 64M N 25Q064 A13ES EC0F SO 8W 8P

15_0804_8P4R_5%

1
2

3
4

15_0804_8P4R_5%

RC388 15_0402_5%

UC2

/CS VCC
DO(IO1) /HOLD(IO3)
/WP(IO2) CLK

4

GND DI(IO0)

W25Q64FVSSIQ_SO8 SA000039A30

PCB Footpri nt = ACES_91960 -0084L_8P-T

Use socket footprint

RC368

15_0402_5%

1 PCH_SPI3_rCd LK:S_AR

EMI@

Source From

RPH11

8 EC_SPI_CS0#
7 PCH_SPI_CS0#
6 EC_SPI_SO
5 PCH_SPI_SO

RPH12

8 PCH_SPI_SIO3
7 PCH_SPI_SI
6 EC_SPI_SI
5

+3V_SPI

8

PCH_SPI_HOLD#

7
6

PCH_SPI_CLK_R

5

PCH_SPI_SI_R

SPI ROM:
Main:SA0 00039A3 0, S IC FL 64M W25Q64 FVSSIQ SOIC
8P SPI ROM
2nd :SA00 007LA10, S IC FL 64M GD25B64 CSIGR SOP
8P SPI ROM

000099300, S IC FL 64M N25 Q064A13E SEDFF

SO8W 8P SPI

1 2

CC9
10P_0402_50V8J

@EMI@

EC_KBRST#
SERIRQ

LPC Mode

EC_SPI_CS0# <26>
EC_SPI_SO <26>

EC_SPI_SI <26>

CC8

1 2 0.1U_0402_16V7K

PCH_SPI_CLK_R <26>

AW13

AY11

SPI0_CLK
SPI0_MISO
SPI0_MOSI

SPI0_IO2

SPI0_IO3

SPI0_CS0#

SPI0_CS1#
SPI0_CS2#

SPI - TOUCH

M2

GPP_D1/SPI1_CLK

M3

GPP_D2/SPI1_MISO

J4

GPP_D3/SPI1_MOSI

V1

GPP_D21/SPI1_IO2

V2

GPP_D22/SPI1_IO3

M1

GPP_D0/SPI1_CS#

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

GPP_A0/RCIN#
GPP_A6/SERIRQ

SKL-U_BGA1356

SPI - FLAS H

CL INK

SMBCLK

SMBDATA

2N7002DWH_SOT363-6

SML1CLK 6

SML1DATA

SMBCLK 1

2N7002DWH_SOT363-6

SMBDATA

SKL-U

LPC

2

QC1A

6 1

2N7002DWH_SOT363-6

SB00000I700

QC1B

3 4

2N7002DWH_SOT363-6

SB00000I700

2

QC2A

SB00000I700

QC2B

2N7002DWH_SOT363-6

SB00000I700

<DB> PWR Rail

2

SB00000I700

6

QC7A

QC7B SB00000I700

2N7002DWH_SOT363-6

SMBUS ,SMLINK

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

5 OF20

+3VS +3VS

RC216

10K_0402_5%

5

+3VS

1

5

3 4

+3V_PRIM +3VALW

RC81

10K_0402_5%

5

34

Rev_0. 53

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

RC215
10K_0402_5%

1 2

1 2

<Co coa_ 102 0>
add leve l shift

1 2

PCH_SMBCLK <17,18,19,22>

PCH_SMBDATA <17,18,19,22>

EC_SMB_CK2 <10,19,22,26,37>

EC_SMB_DA2 <10,19,22,26,37>

RC82
10K_0402_5%

1 2

TP_SMBCLK <27>

TP_SMBDATA <27>

R7

SMBCLK

R8

SMBDATA
SMBALERT#

R10
R9

SML0CLK

W2

SML0DATA

W1

SML0ALERT#

W3

SML1CLK

V3

SML1DATA

AM7 GPP_B23 1

AY13 LPC_AD0

LPC_AD1

BA13

LPC_AD2

BB13

LPC_AD3

AY12

LPC_FRAME#

BA12

SUS_STAT#

BA11

AW9 CLK_PCI0
AY9 CLK_PCI1 RC53 1 TPM@2 22_0402_5%

AW11 PM_CLKRUN#

<SI>un -mount RC53
11/2 8 CPU side delete EC_PCIE_ WAKE#

RC387

RC902@

0_0201_5%

TP@ T234

1

TP@ T239

2 SML1ALERT#

TP@ T242

LPC_AD0 <26,28>
LPC_AD1 <26,28>
LPC_AD2 <26,28>
LPC_AD3 <26,28>
LPC_FRAME# <26,28>

2 22_0402_5%

PM_CLKRUN# <26>

SML0ALERT# (Internal Pull Down):
eSPI or LPC
0 = LPC is selected for EC --> For KB9022/9032 Use
1 = eSPI is selected for EC --> For KB9032 Only.

SML1ALERT#

SML0ALERT#

SMBALERT#

EC_KBRST#

SML0ALERT#

1

2

2 @ 1

150K_0402_1%

2 @ 1 10K_0402_5%

RC360

8
7

6
5

RPC19 10K_0804_8P4R_5%

RC218
1K_0402_1%

RC903

SMB

(Link to XDP , DDR, TP)

SML1

(Link to EC, DGPU, LAN, T herm al

CLK_PCI_LPC <26>
CLK_PCI_TPM <28>

To EC

Sensor)

11/28_Fo llow I ntel check list, add PU res

11/28_Change PWR rail from +3VS to +3V_PRIM

+3V_PRIM

SML0CLK
SML0DATA

SML1CLK
SML1DATA
SMBDATA

SMBCLK

PCH_SPI_SIO2 RC3901 @ 2 1K_0402_1%
PCH_SPI_SIO3 RC3911 2 1K_0402_1%

PCH_SPI_CS0#_R

PCH_SPI_SIO3 RC51 1 ES@ 2 1K_0402_1%

From WW36 MOW for SKL-U ES sample

PM_CLKRUN#

SERIRQ

RC49 1 2 499_0402_1%
RC50 1 2 499_0402_1%

RPC7

1 8
2

7
6

3
4 5

1K_0804_8P4R_5%

@

@

2

1

RC357

RC107 8.2K_0402_5%

RC122 8.2K_0402_5%

1K_0402_5%

1 2

1 2

Follow 543016_SKL_U_Y_PDG_0_9

+3V_SPI

+3VS_PGPPA

+3V_PRIM

1
2
3
4

+3VS

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5 4 3 2 1

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/12/11 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Tiiitllle

SKL-U(3/12)SPI,ESPI,SMB,LPC

Siiize Document Number

Custom

LA-D707P

Rev

Sheet 7 o f 60Date: Wednesday, May 11, 2016

v0.2

5 4 3 2 1

UC1G

D D

<24> HDA_SDIN0

<10,24> HDA_SPKR

C C

T35 TP@

T38 TP@
T39 TP@

HDA forAUDIO

1 8

@EMI@

2
3
4

<24> HDA_SYNC_AUDIO
<24> HDA_RST_AUDIO#
<24> HDA_SDOUT_AUDIO

<24> HDA_BITCLK_AUDIO

CC143 22P_0402_50V8J

HDA_SYNC BA22

HDA_BIT_CLK AY22

HDA_SDOUT BB22

HDA_SDIN0

HDA_RST#

SOC_GPIOF1
SOC_GPIOF0

HDA_SPKR

RPC9

7 HDA_SYNC
6 HDA_RST#
5 HDA_SDOUT

33_0804_8P4R_5%

2

RC383

EMI@

BA21
AY21

AW22
AY20

AW20

AK7
AK6
AK9

AK10

AW5

1 HDA_BIT_CLK

33_0402_5%

J5

H5
D7

D8
C8

EMI request

A36

B B

A A

B36
C38
D38
C36
D36
A38
B38

C31
D31
C33
D33
A31
B31
A33
B33

A29
B29
C28
D28
A27
B27
C27
D27

AUDIO

HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD

GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0
GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1
GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKL-U_BGA1356

<26> ME_FLASH_EN

+3V_HDA

UC1I

CSI-2

CSI2_DN0
CSI2_DP0
CSI2_DN1
CSI2_DP1
CSI2_DN2
CSI2_DP2
CSI2_DN3
CSI2_DP3

CSI2_DN4
CSI2_DP4
CSI2_DN5

CSI2_DP5
CSI2_DN6

CSI2_DP6

CSI2_DN7

CSI2_DP7

CSI2_DN8
CSI2_DP8
CSI2_DN9
CSI2_DP9
CSI2_DN10
CSI2_DP10

CSI2_DN11

CSI2_DP11

SKL-U_BGA1356

SKL_ULT

SKL-U

SDIO/SDXC

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

7 OF20

RC367 1 2 0_0402_5%

2

2 RC380

1

1K_0402_1%

@

G

1

D

@

3 HDA_SDOUT

QC380

S

MESS138W-G_SOT323-3

Rev_0.5 3

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#
GPP_G6/SD_CLK

GPP_G7/SD_WP

SD_RCOMP

GPP_F23

AB11
AB13 VRAMCLK_SEL
AB12 PROJECT_ID
W12
W11
W10
W8
W7

BA9
BB9

AF13 SOC_GPIOF17

T235 TP@

+3V_PRIM

1

RC127
10K_0402_5%

PX@

2

1

RC128

10K_0402_5%

UMA@

2

1 200_0402_1%AB7 SD_RCOMP RC76 2

PROJECT_ID

VRAM Clock

VRAMCLK_SEL

UMA DIS

0

1

900MHz 1000MHz

X76@

2

RC900
10K_0402_5%

1

X76@

2

RC901
10K_0402_5%

1

1

0

+3V_PRIM

HDA_SDOUT:
ME Flash Descriptor Security Override

Low : Disabled(Default)
High : Enabled

Rev_0.5 3

C37

CSI2_CLKN0

D37

CSI2_CLKP0

C32

CSI2_CLKN1

D32

CSI2_CLKP1

C29

CSI2_CLKN2

D29

CSI2_CLKP2

B26

CSI2_CLKN3

A26

9 OF20

CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMM C

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

E13 CSI2_COMP RC80 2
B7

AP2

AP1

AP3
AN3
AN1

AN2
AM4
AM1

AM2
AM3
AP4

AT1

EMMC_RCOMP 2

T63 TP@

RC89

1 100_0402_1%

1

200_0402_1%

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5 4 3 2 1

2014/05/19 2015/12/31

Compal SecretData

Deciphered Date

Compal Electronics,Inc.

Title

SKL-U(4/12)HDA,EMMC,SDIO,CSI2

Siiize Document Number

Custom

LA-D707P

Date: Wednesday, May 11,2016

Sheet of

8

Rev

v0.2

60

+RTCVCC

RC91 1 2 20K_0402_ 5% PCH_SRT CRST#
CC10 1 2 1U_0402_6 .3V6K
CLRP1 1 2 SH ORT PAD S

RC93 1 2 20K_0402_5% PCH _RTCRST#
CC11 1 2 1U_0402_6.3V6K

CLRP2 1 2 SH ORT PAD S

D D

+3V_PRIM

C C

B B

A A

RC941 2 1M_0402_5% SM_INTRUDER#

PCH_RT CRST# 2 @ 1

0_0402_5% R1088

PCH_SRT CRST# 2 @ 1

0_0402_5% R1089

+3VS

RC165
RC105

RC109 10K_0 402_5%

+3VALW _DSW

10K_0804_8P4R_5%

CLRP3 SHORTPADS
RC100 1K_0402_5%
RC101

+3VALW _DSW

+3V_PRIM

+3VALW _DSW

RC111 2 1 100K_0402_5% PBTN_OU T#

From EC (open- drain)

<26,35> EC_VCCST_P G_R

5 4 3 2 1

RC112

SKL_ULT

CLO CK SIG NALS

10 OF 20

PLT_RST# <23 ,26,28,32,36>

SKL-U

11 OF 20

2

1 PCH_DPW ROK_R

0_0402_5%

Rev_0 .53

GPD8/SU SCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1
RTCX2

SRTCRST#

RTCRST#

Rev_0 .53

GPD4/SL P_S3#
GPD5/SL P_S4#

SLP_SUS#

SLP_LAN#

GPD6/SL P_A#

GPP_A11/PME#

INTRUD ER#

F43
E43

BA17 SUSCLK
E37 PCH_XT AL24_IN

E35 PCH_XTAL24_OUT
E42 XCLK_BIASR EF RC96 1 2 2.7K_0402_1%
AM18 PCH_RTCX1

AM20 PCH_R TCX2
AN18 PCH_S RTCRST #

AM16 PCH_RTCRST#

PCH_XT AL24_IN

PCH_XT AL24_OU T PCH_RT CX1

AT11 PM_S LP_S0#
AP15 PM_SLP_S3#
BA16 PM_SLP_S4#
AY16 PM_SLP_S5#

AN15 PM_SLP_SUS#

AW15 SLP_LAN#
BB17 SLP_W LAN#
AN16 PM_SLP_A#

BA15 PBTN_O UT#

AY15 AC_PRESENT_R 2

AU13 PM_BATLO W# RC108

AU11 EC_PC IE_WAKE#

AP16 SM_INTRUDER #

AM10 EXT_PW R_GAT E#

AM11 SOC_VRALERT#

SUSCLK <32>

RC92 1M_0402_5%

YC1 SJ10000IZ00

24MHZ 12PF 20PPM X3G02400 0DC1H

3

3 1

22P_0402_50V8J

CC12

<Cocoa _1020>
32M use these part (SJ10000NM00, SJ10 000MH00) just can meet <50k ohm spec
24M: SJ10000DI00, SJ10000CS00

PM_SLP_SUS# <13,26>
TP@T 87
TP@T 88

EC_PCIE_WAKE# <26,32>

TP@T 298

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

GPP_B12/SLP_S0#

GPD10/SLP_S5#

GPD9/SL P_WLA N#

GPD3/PW RBT N#

GPD1/AC PRESENT

GPD0/BATLOW #

GPP_B11/EXT_PW R_GATE#

GPP_B2/VRALERT #

11/28 add RSMRST protect circuit

SPOK <48>

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

1 2

GND GND

4 2

PBTN_O UT# <26>

1

1

0_0402_5%

PM_SLP_S3 # <12,2 6,35>
PM_SLP_S4 # <12,26,35,49>
PM_SLP_S5 # <26>

Tiiitllle

Size Document Number

Custom

Date: Wednesday, May 11, 2016

CLR ME

<36> CLK_PEG_VGA#

GPU

<36> CLK_PEG_VGA

CLR CMOS

CLR_CMOS# <26>

1

Clear CMOS close to RAM door

@

JCMOS1

0_0603_5%

2

CLKREQ_PCIE#4

1

2

10K_0402_5%

1

2 CLKREQ_PCIE#5

10K_0402_5%

RPC10

1 LAN_CLKREQ#

8

2 MINI1_CLKREQ#

7

3 CR_CLKREQ#

6

4

5

10K_0804_8P4R_5%

1 @ 2

RPC11

8

7
6
5

2 1 SYS_RESET#

1 @ 2 SUSCLK

2 1

RC103
RC104
RC106

RC1151 2 10K_0402_5% SOC_VRALERT#

VGA_CLKREQ#

1 PCH_PWROK
2 LAN_WAKE#
3 PCH_RSMRST #
4 SYS_RESET#

PCH_DPW ROK

100K_0402_5%

1

2

8.2K_0402_5%

1

2 W AKE#

1K_0402_5%

2 AC_PRESENT_R

1

10K_0402_5%

<DB> RC 106 unp op , f ollow m odule de sign

@

@

@

+1.0V_VCCST

5 4 3 2 1

545659_SKL_PCH_U_Y_EDS_R0_7

From

<Coc oa_10 27>
check u n-use G PIO fo r term ination guidan ce

<DB> un pop, PD at GP U si de

DS12

1 PCH_PW ROK2

CK0402101V05_0402-2

ESD@
SCV00001K00

PM_BATLOW#

Only Fo r Power Seque nce Debug

<26> SUSACK#

ESD@

DS13

SCV00001K00

1 2 H_CPUPWRGD

CK0402101V05_0402-2
DS14

1

CK0402101V05_0402-2

DS15

1

CK0402101V05_0402-2

1

RC113
1K_0402_5%

2

RC1161 2 60.4_0402_1% EC_VCCST _PG

@ESD@
SCV00001K00

2 SUSACK#

@ESD@
SCV00001K00

2 SYS_PW ROK

T95 TP@

<DB> ad d ESD p rotect ion

<37> VGA_CLKR EQ#

<23> CLK_PCIE_LAN#

LAN

<23> CLK_PCIE_LAN

<23> LAN_CLKREQ#

<32> CLK_PCIE_WLAN#

WLAN

<32> CLK_PCIE_WLAN
<32> MINI1_CLKR EQ#

CardReader

<26> PCH_RSMRST#

RC102 1 @ 2 1K_040 2_5% H_CPU PWRG D A68

<26> SYS_PW ROK

<26> PCH_PW ROK

<26> PCH_SUSW ARN#

1

2

RC110

0_0402_5%

<32> WAKE#

PCH PLTRST Buf f er<DB> Romove PLT_RST# buf fer

PLT_RST#_PCH

T296 TP@

CLK_PEG_VGA#
CLK_PEG_VGA
VGA_CLKREQ#

CLK_PCIE_LAN#
CLK_PCIE_LAN
LAN_CLKREQ#

CLK_PCIE_WLAN#
CLK_PCIE_WLAN
MINI1_CLKREQ#

CR_CLKREQ#

CLKREQ_PCIE#4 AU8

CLKREQ_PCIE#5 AU7

RC99 1 2 0_0402_5%

1

IN1

2

PLT_RST#_PCH
SYS_RESET#
PCH_RSMR ST#

EC_VCCST_PG B65

SYS_PW ROK
PCH_PW ROK

PCH_DPW ROK_R BB20

PCH_SUSWARN#
SUSACK#_ R

WAKE#
LAN_WAKE#

T94 TP@

<26> PCH_DPW ROK

IN2

SN74AHC1G08DCKR_SC70- 5

PCH_RSMR ST# PCH_PW ROK

UC1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

GPP_B10/SRCCLKR EQ5#

SKL-U_BGA1356

+3VS

CC145

@

1 2

@

5

UC8

0.1U_0402_16V7K

4

O

G P

3

UC1K

AN10

GPP_B13/PLTRST #

B5

SYS_RESET#

AY17

RSMRST#

PROCPW RGD

VCCST_PWRG D

B6

SYS_PW ROK

BA20

PCH_PW ROK

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKL-U_BGA1356

DC3 SCS00003500

CH751H-40PT_SOD323-2

1 2

1

2

SCS00003500

DC4
CH751H-40PT_SOD323-2

SecurityClllassiiifiiicatiiion

THIIIS SHEET OF ENGIIINEERIIING D RAWING IIIS THE PROPRIIIETARY P ROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRAD E SECRE T IIINFORMATIIION... THIIIS SHE ET MAY NOT BE TRA NSFERE D FROM THE CUSTODY OF THE COMPETE NT DIIIVIIISIIION OF R&D
DEPARTMENT E XCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NO R THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE US ED BY OR DIIISCLOSED TO ANY THIIIRD PARTY W ITHOUT PRIIIOR WRIIITTEN CON SENT OF COMPAL ELECTRONIIICS,,, IIINC...

PLT_RST#

SYS TEM POW ER MAN AGEME NT

Issued Date

+1.0V_C LK5_F24N S

XCLK_BIASREF

RC97 1 2 60.4_040 2_1%

<DB> stuf f f or cannonl ake 60oh m1 %
<SI> change to SJ10000Q300 , CL=9p

PCH_RT CX2

1 2

RC98 10M_0402_5%

YC2

32.768KHZ 9PF 10PPM 9H03200055

1 2

SJ10000Q800

6.8P_0402_50V8J

CC15

22P_0402_50V8J

TP@T254
TP@T255
TP@T256
TP@T257
TP@T 258

ACIN <26,37>

CC13

1

2

<PV> ch ange CC15,CC16 to 6.8p
<MV> change CC15,C C16 to 8.2p

Compal Electronics, Inc.

SKL-U(5/12)CLK,GPIO

LA-D707P

Sheet 9 o f 60

@

CC16

6.8P_0402_50V8J

1

2

Rev

v0.2

5 4 3 2 1

UC1F

LPSS ISH

AN8

GPP_B15/GSPI0_ CS#

AP7

GPP_B16/GSPI0_C LK

AP8

GSPI0_MOSI

D D

C C

<DB> add TP by BIOS

TP@T129
TP@T128

<32> WL_OF F#

TP@T133
TP@T132

12

R5194

@

0_0402_5%

SOC_GPIOB21
GSPI1_MOSI

UART_0_CRXD_DTXD
UART_0_CTXD_DRXD

WL_O FF#

UART_2_CRXD_DTXD
UART_2_CTXD_DRXD

UART_2_CTXD_DRXD

UART_2_CRXD_DTXD

Functional Strap Definitions

SPKR (Internal Pull Down):
TOP Swap Override

0 = Disable TOP Swap mode.---> AAX05 Use
1 = Enable TOP Swap Mode.

GSPI0_MOSI (Internal Pull Down):
No Reboot

GPP_B17/GSPI0_ MISO

AR7

GPP_B18/GSPI0_ MOSI

AM5

GPP_B19/GSPI1_C S#

AN7

GPP_B20/GSPI1_C LK

AP5

GPP_B21/GSPI1_ MISO

AN5

GPP_B22/GSPI1_ MOSI

AB1

GPP_C8/ UART0_ RXD

AB2

GPP_C9/ UART0_ TXD

W4

GPP_C10 /UART0 _RTS#

AB3

GPP_C11 /UART0 _CTS#

AD1

GPP_C20 /UART2 _RXD

AD2

GPP_C21 /UART2 _TXD

AD3

GPP_C22 /UART2 _RTS#

AD4

GPP_C23 /UART2 _CTS#

U7

GPP_C16 /I2C0_SDA

U6

GPP_C17 /I2C0_SCL

U8

GPP_C18 /I2C1_SDA

U9

GPP_C19 /I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

SKL-U_BGA1356

Strap Pin

+3VS

RC117 1 2 100K_0402_5% HDA_SPKR

RC118 1 2 4.7K_0402_5% GSPI0_MO SI

RC201 1 2 150K_0402_1% GSPI1_MOSI

<Coc oa_10 20>
1K oh m for 40 0kHz speed/ 0.5k ohm for 1MHz s peed

SKL-U

GPP_F10/I2C5_SDA/ISH_ I2C2_SDA

GPP_F11/I2C5_SCL/ISH_ I2C2_SCL

GPP_D13 /ISH_UART0_RXD/SML0BDATA/I2C 4B_SDA

GPP_D14 /ISH_UART0_TXD/SML0BCLK/I2C 4B_SCL

6 OF 20

@

@

@

GPP_D15 /ISH_UART0_RT S#

GPP_D16 /ISH_UART0_CT S#/SML0B ALERT #

GPP_C12 /UART1 _RXD/ISH_UART1_RXD

GPP_C13 /UART1 _TXD/ISH_UART1_TXD
GPP_C14 /UART1 _RTS#/ISH_UART 1_RTS#
GPP_C15 /UART1 _CTS#/ISH_UART 1_CTS#

GPP_A12/BM_BUSY#/ISH_GP6

Rev_0 .53

GPP_D9
GPP_D10
GPP_D11
GPP_D12

GPP_D5/ ISH_I2C0_SDA
GPP_D6/ ISH_I2C0_SCL

GPP_D7/ ISH_I2C1_SDA
GPP_D8/ ISH_I2C1_SCL

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

HDA_SPKR <8,24>

P2
P3
P4
P1

M4
N3

12/11_Delete TP

N1
N2

AD11
AD12

U1
U2
U3
U4

AC1 DGPU_PWR _EN

AC2 DGPU_HOLD_R ST#

AC3

AB4

AY8
BA8

BB7

BA7 ODD_PWR

AY7 ODD_DA#
AW7
AP13 SO C_GPIOA12

TS_GPIO_CPU <20>

DGPU_PWR_EN <26,38,55,56>
DGPU_HOLD_RST# <36>

GPU_PGD <56>

ODD_PW R <3 0>

ODD_DA# <30>

T122 TP@

+3VS

+3VS

CC14

1 2

2200P_0402_ 50V7K

1 2 CPU_THERM#

RC45 33K_0402_5%

1105_Mo dify sche matic

<Coc oa_10 27>
Follow #544669 GPIO I/O settin g

CPU THERMALSENSOR

0.1U_0402_16V7K
CC127

1

2

Thermalsensor:
Main:SA000067P00, S IC NCT7718W MSOP 8P THEMAL SENSOR(Nuvoton)
2nd : SA00007WP00,S IC F75397M MSOP8P THEMAL SENSOR(Fintek)
3rd : SA007810140, S IC G781P8F MSOP 8P TEMP. SENSOR(GMT)

Thermal sensor SMBus address -->100-1_100xb : 0x4C
(x=0)Write Address(0x98h)
(x=1)ReadAddress(0x99h)

UC3

1

H_THERMDA
H_THERMDC

VDD

2

D+

3 D- ALERT#
4 THERM# GND

NCT7718W_MSOP8

SA000067 P00

SCLK

SDATA

EC_SMB_CK 2

8

EC_SMB_DA 2

7

THERMAL _ALERT#

6

5

<5,26> NMI_DBG#_CPU

<5,26> EC_SCI#

<Cocoa_1127> remove EC_LID_OUT# function

<Cocoa_1020>
Follow BDW

EC_SMB_CK 2 <7,19,22,26,37>
EC_SMB_DA 2 <7,19,22,26,37>

DGPU_PWR_EN

SOC_GPIOB21
WL_O FF#

NMI_DBG#_CPU

EC_SCI#
ODD_PW R
ODD_DA#

2

RC44

<DB>

RC3821 2 10K_0402_ 5%

@

RPC14

1 8
2
3
4

10K_0804_8P4R_5%

RPC12

1
2
3
4 5

10K_0804_8P4R_5%

1

+3VS

10K_0402_5%

+3VS

+3V_PRIM

7
6
5

8
7
6

+3VS

0 = Disable No Reboot mode. --> AAX05 Use
1 = Enable No Reboot Mode. (PCH will disable the TCO

Timer system reboot feature). This function is useful
when running ITP/XDP.

B B

GSPI1_MOSI (Internal Pull Down):

<DB>
Delete Win7 de bug port

Boot BIOS Strap Bit
0 = SPI Mode --> AAX05 Use
1 = LPC Mode

A A

SecurityClllassiiifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING D RAWING IIIS THE PROPRIIIETARY P ROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRAD E SECRE T IIINFORMATIIION... THIIIS SHE ET MAY NOT BE TRA NSFERE D FROM THE CUSTODY OF THE COMPETE NT DIIIVIIISIIION OF R&D
DEPARTMENT E XCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NO R THE IIINFORMATIIION IIIT CONTAIIINS

5 4 3 2 1

MAY BE US ED BY OR DIIISCLOSED TO ANY THIIIRD PARTY W ITHOUT PRIIIOR WRIIITTEN CON SENT OF COMPAL ELECTRONIIICS,,, IIINC...

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Tiiitllle

SKL-U(6/12)GPIO

Size Document Number

Custom

LA-D707P

Date: Wednesday, May 11, 2016

Sheet 10 o f 60

Rev

v0.2

5 4 3 2 1

UC1H

<DB> Change to 0.22uF for Gen3

<36> PEG_PRX_C_DTX_N0
<36> PEG_PRX_C_DTX_P0
<36> PEG_PTX_C_DRX_N0

D D

PEG

LAN

WLAN

HDD

C C

ODD

B B

A A

<36> PEG_PTX_C_DRX_P0
<36> PEG_PRX_C_DTX_N1

<36> PEG_PRX_C_DTX_P1
<36> PEG_PTX_C_DRX_N1
<36> PEG_PTX_C_DRX_P1

<36> PEG_PRX_C_DTX_N2
<36> PEG_PRX_C_DTX_P2
<36> PEG_PTX_C_DRX_N2
<36> PEG_PTX_C_DRX_P2

<36> PEG_PRX_C_DTX_N3
<36> PEG_PRX_C_DTX_P3
<36> PEG_PTX_C_DRX_N3
<36> PEG_PTX_C_DRX_P3

<23> PCIE_PRX_DTX_N5
<23> PCIE_PRX_DTX_P5

<23> PCIE_PTX_C_DRX_N5

<23> PCIE_PTX_C_DRX_P5

<32> PCIE_PRX_DTX_N6
<32> PCIE_PRX_DTX_P6

<32> PCIE_PTX_C_DRX_N6

<32> PCIE_PTX_C_DRX_P6

<30> SATA_PRX_DTX_N0

<30> SATA_PRX_DTX_P0

<30> SATA_PTX_DRX_N0

<30> SATA_PTX_DRX_P0

<30> SATA_PRX_DTX_N1

<30> SATA_PRX_DTX_P1

<30> SATA_PTX_DRX_N1

<30> SATA_PTX_DRX_P1

CC119 0.22U 6.3V K X5R04022 1 PX@
CC146 0.22U 6.3V K X5R 0402 2 1 PX@ PEG_PTX_DRX_P0 A17

CC128 0.22U 6.3V K X5R 0402 2 1 PX@ PEG_PTX_DRX_N1 D16
CC93 0.22U 6.3V K X5R 04022 1 PX@ PEG_PTX_DRX_P1 C16

CC124 0.22U 6.3V K X5R 04022 1 PX@ PEG_PTX_DRX_N2 D17

CC92 0.22U 6.3V K X5R 0402 2 1 PX@ PEG_PTX_DRX_P2C17

CC129 0.22U 6.3V K X5R 04022
CC118 0.22U 6.3V K X5R 04022

1 0.1U_0402_16V7K

CC18 2

1 0.1U_0402_16V7K

CC17 2

1 0.1U_0402_16V7K

CC20 2

1 0.1U_0402_16V7K

CC19 2

RC1201

<5> XDP_PREQ#

2 100_0402_1% PCIE_RCOMPN

T291 TP@
T154 TP@

XDP_PRDY#

XDP_PREQ#

SOC_GPIOA7

PEG_PRX_C_DTX_N0 H13
PEG_PRX_C_DTX_P0 G13

PEG_PTX_DRX_N0 B17

PEG_PRX_C_DTX_N1 G11
PEG_PRX_C_DTX_P1 F11

PEG_PRX_C_DTX_N2 H16
PEG_PRX_C_DTX_P2 G16

PEG_PRX_C_DTX_N3 G15

PEG_PRX_C_DTX_P3 F15

1 PX@ PEG_PTX_DRX_N3 B19
1 PX@ PEG_PTX_DRX_P3 A19

PCIE_RCOMPP

When PCIE8/SATA1A is used
as SATA Port 1 (ODD), then
PCIE11/SATA1B (M.2 SSD)
cannot be used as SATA
Port 1.

PCIE2_TXN/USB3_6_TXN

PCIE2_TXP/USB3_6_TXP

PCIE_PRX_DTX_N5F16
PCIE_PRX_DTX_P5 E16
PCIE_PTX_DRX_N5 C19
PCIE_PTX_DRX_P5 D19

PCIE_PRX_DTX_N6 G18
PCIE_PRX_DTX_P6 F18
PCIE_PTX_DRX_N6 D20
PCIE_PTX_DRX_P6 C20

PCIE/USB3 /SATA

PCIE1_RXN/USB3_5_RXN

PCIE1_RXP/USB3_5_RXP

PCIE1_TXN/USB3_5_TXN
PCIE1_TXP/USB3_5_TXP

PCIE2_RXN/USB3_6_RXN
PCIE2_RXP/USB3_6_RXP

PCIE3_RXN

PCIE3_RXP

PCIE3_TXN
PCIE3_TXP

PCIE4_RXN

PCIE4_RXP

PCIE4_TXN
PCIE4_TXP

PCIE5_RXN

PCIE5_RXP
PCIE5_TXN

PCIE5_TXP

PCIE6_RXN

PCIE6_RXP
PCIE6_TXN

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL-U_BGA1356

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5 4 3 2

2014/05/19 2015/12/31

SKL-U

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

8 OF20

GPP_E8/SATALED#

GPIO DEVICE CONTROL

USB_OC0#

USB_OC1#

USB_OC2#

USB2 Port 1 and Port 2

USB2 Port 3

NA

USB_OC3# NA

DEVSLP0

NA

DEVSLP1 NGFF SSD KEY B

DEVSLP2

SATA_GP0

SATA_GP1

SATA_GP2

NA

NA

NA

ODD_PLUG#

Compal SecretData

Deciphered Date

Rev_0.5 3

USB3_1_RXN
USB3_1_RXP
USB3_1_TXN

USB3_1_TXP

USB3_4_RXN
USB3_4_RXP
USB3_4_TXN

USB3_4_TXP

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB2_COMP

USB2_ID

H8
G8
C13
D13

J6

H6

B13
A13

J10
H10
B15
A15

E10
F10
C15
D15

AB9
AB10

AD6

AD7

AH3

AJ3

AD9

AD10
AJ1

AJ2
AF6

AF7
AH1

AH2

AF8
AF9

AG1
AG2

AH7
AH8

AB6 USB2_COMP

AG3 USB2_ID

AG4 USB2_VBUSSENSE

A9 USB_OC0#

C9 USB_OC1#

D9 USB_OC2#

B9 USB_OC3#

DEVSLP0

J1

J2 DEVSLP1

DEVSLP2

J3

H2 SATA_GP0

H3 ODD_PLUG#

SATA_GP2

G4

H1 SATA_LED#

USB3_RX1_N <31>
USB3_RX1_P <31>

USB3_TX1_N <31>
USB3_TX1_P <31>

USB20_N1 <31>
USB20_P1 <31>

USB20_N2 <31>
USB20_P2 <31>

USB20_N3 <33>
USB20_P3 <33>

USB20_N4 <32>
USB20_P4 <32>

USB20_N5 <20>
USB20_P5 <20>

USB20_N6 <20>
USB20_P6 <20>

USB20_N7 <33>
USB20_P7 <33>

RC119 1 2 113_0402_1%

USB2.0/USB3.0

USB2.0/USB3.0
USB2.0
USB2.0 ( on small board )
WLAN
Camera
Touch Screen
Card Reader

<SI> follow EDS to add 1K ohm PD

USB2_ID RC20 1 2 0_0402_5%

T243 TP@
T241 TP@ <DB> PU

ODD_PLUG# <30>

SATA_LED# <33>

DEVSLP1
SOC_GPIOA7

SATA_LED# 1 8
SATA_GP0 2 7
SATA_GP2 3 6
ODD_PLUG# 4 5

USB_OC1#
USB_OC3#
USB_OC0#
USB_OC2#

1128_Add pull high resistor

Compal Electronics, Inc.

Title

SKL-U(7/12)PCIE,USB,SATA

Siiize

Document Number

Custom

LA-D707P

Date: Wednesday, May 11, 2016 Sheet111 of 60

USB2_VBUSSENSE1

RC21

2

1

RC3621

RC361 10K_0402_5%

2 10K_0402_5%

RPC13

10K_0804_8P4R_5%

RPC20

1

8

2

7

3

6

4

5

10K_0804_8P4R_5%

2

0_0402_5%

+3V_PRIM

+3VS

Rev

v0.2

5 4 3 2 1

+1.0V_PRIM TO +1.0V_VCCSTU

+1.2V_VDDQ

1211_Delete jump RC147

D D

<26,35,49> SYSON

<9,26,35,49> PM_SLP_S4#

<13,26,35,49> SUSP#

<9,26,35> PM_SLP_S3#

C C

1210_Delete jump RC146

RC142 1 2 0_0402_5%
RC144 1 @ 2 0_0402_5%
RC168 1 2 0_0402_5%
RC194 1 @ 2 0_0402_5%

1

2

@

CC151

+5VALW

0.1U_0402_25V6

+1.8V_PRIM

@

+1.0VS_VCCIO

@ 2 0_0603_5%

1U_0402_6.3V6K

1

CC98

2

1U_0402_6.3V6K

1

CC99

2

1U_0402_6.3V6K

1

CC97

I (Max) : 0.04 A(+1.0V _VCCSTU)
RON(Max) : 25 mohm

@

V drop : 0.001 V

2

UC5

1

VIN1

2

EN_1.0V_VCCSTU 3

EN_1.8VS

VIN1
ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

EM5209VF_DFN14_2X3

SA00007PM00

I (Max) : 0.53 6 A(+1.8VS)
RON(Max) : 25 mohm
V drop : 0.013 V

VOUT1
VOUT1

CT1

GND

CT2

VOUT2
VOUT2

GPAD

R51881

14

13

12

CC95

11

10P_0402_50V8J

10

@CC94

9 1000P_0402_50V7K

8
15

@ESD@

0.1U_0402_25V6

1 2

1 2

CC156

1

2

+1.0V_VCCSTU+1.0V_PRIM

+1.8VS

1

CC100

0.1U_0402_25V6

2

<DB> Delete RC145

0.1U_0402_25V6

1

CC96

2

+1.2V_VDDQC
+1.0V_VCCST

+1.0VS_VCCIO

+1.2V_VCCSFR_OC

+1.0V_VCCSFR

<Cocoa_1113>
Per
543977_SKL_PDDG_Rev0_91,
change CC95 value from

1000pf to 10pf for meet
<= 65us timing for
+1.0V_VCCSTU power rail.

+1.0V_VCCSTU +1.0V_VCCST

RC140 1 2 0_0402_5%

AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51

AM40

A18
A22

AL23

K20
K21

UC1N

VDDQ_AU23
VDDQ_AU28
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51

VDDQC
VCCST

VCCSTG_A22
VCCPLL_OC

VCCPLL_K20
VCCPLL_K21

SKL-U_BGA1356

+1.0V_PRIM TO +1.0VS_VCCSTG / +1.0VS_VCCIO

+5VALW

+1.0V_PRIM

0.1U_0402_25V6

1

CC88

2

@

B B

<26> EC_S0IX_EN

For Verify S0IX

+1.0VS_VCCIO

SUSP# RC186 1 2 0_0402_5%

RC187 1 2 0_0402_5%

<Cocoa_1027>

connect to EC, check /w EC

@

1U_0402_6.3V6K

Imax : 2.77A

1

CC117

2

I (Max) : 3 A(+1.0VS_VCCIO)
RON(Max) : 6.2 mohm
V drop : 0.019 V

UC6

1

VIN1

2

VIN2

7

VINthermal

3

VBIAS
ON GND

TPS22961DNYR_WSON8

Part Number = SA00007XR00

VOUT

PSC SideBSC Side

6

54

<PV> change shortpad

RC189

+1.0VS_VCCSTG_IO

1 2 0_0805_5%

Imax : 3A

<DB> change +1.35V_VDDQ

RC208 Follow 544669_SKL_U DDR3L_RVP7_Schematic_Rev0_53

+1.2V_VDDQ

+1.0VS_VCCIO

+1.0VS_VCCIO

RC208

1 2 0_0603_5%

near pin A22

CC89 1 2 0.1U_0402_25V6

CC90 1 2 0.1U_0402_25V6

@

+1.2V_VDDQC

BSC Side

RC143 1 2 0_0402_5%

<DB> change +1.35V_VDDQ

+1.2V_VDDQ

PSC Side

CPU POWER 3 OF4

PSC Side

1

2

+1.0V_VCCSFR

1

2

SKL-U

14 OF20

1U_0402_6.3V6K

VCCIO_SENSE
VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

CC48

Rev_0.5 3

RC208 Follow 544669_SKL_U DDR3L_RVP7_Schematic_Rev1.0

1U_0402_6.3V6K

CC55

+1.0VS_VCCIO

AK28

VCCIO

AK30

VCCIO

AL30

VCCIO

AL42

VCCIO

AM28

VCCIO

AM30

VCCIO

AM42

VCCIO

AK23

VCCSA

AK25

VCCSA

G23

VCCSA

G25

VCCSA

G27

VCCSA

G28

VCCSA

J22

VCCSA

J23

VCCSA

J27

VCCSA

K23

VCCSA

K25

VCCSA

K27

VCCSA

K28

VCCSA

K30

VCCSA

AM23 VCCIO_SENSE
AM22 VSSIO_SENSE

H21 VSSSA_SENSE
H20 VCCSA_SENSE

+VCC_SA

<DB> change +1.35V_VDDQ

BSC Side

T124 TP@
T125 TP@

VSSSA_SENSE <52>
VCCSA_SENSE <52>

+1.0VS_VCCIO

BSC SidePSC Side

1

2

1U_0402_6.3V6K

CC56

1

CC27

2

A A

1

CC28

2

2

5 4 3 2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1U_0201_6.3V6K

1U_0201_6.3V6K

1

CC29

2

1U_0201_6.3V6K

1

CC30

1

CC31

2

2

1U_0402_6.3V6K

1U_0201_6.3V6K

1

CC32

2

1U_0402_6.3V6K

1

CC33

1

CC34

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CC36

CC35

CC47 Follow 543016_SKL_U_Y_PDG_0_9

2

1U_0402_6.3V6K

1

CC47

2

10U_0603_6.3V6M

1

1

CC37

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CC38

2

10U_0603_6.3V6M

1

CC39

1

CC40

2

2

+1.35V_VDDQ_CPU : 10UF/6.3V/0603 *6

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/12/11 2015/12/31

Compal SecretData

Deciphered Date

10U_0603_6.3V6M

1U_0402_6.3V6K

10U_0603_6.3V6M

1

1

CC42

CC41

2

2

1U_0201_6.3V6K

1

CC43

1

CC44

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CC46

CC45

2

1UF/6.3V/0402 * 4

Title

Siiize

Custom
Date: Wednesday, May 11, 2016 Sheet112 of 60

Compal Electronics,Inc.

SKL-U(8/12)Power

Document Number

LA-D707P

Rev

v0.2

5 4 3 2 1

+1.0V_PRIM

RC148 1 2 0_0603_5%

D D

Follow

543016_SKL_U_Y_PDG_1_0

RC152 1 2 0_0603_5%

RC190 1 2 0_0603_5%

C C

Imax : 2.57A

near pi n AF18,
AF19 ,V20, V21

RC175 1 2 0_0402_5%

B B

RC169 1 2 0_0603_5%

RC162 1 2 0_0402_5%

+1.0V_APLL

22U_0603_6.3V6M

1

1

CC142

@

@

2

2

+1.0V_CLK5_F24NS

22U_0603_6.3V6M

1 1

CC135

@ @

2 2

+1.0V_CLK4_F100OC

22U_0603_6.3V6M

1

1

CC136

@

@

2

2

+1.0V_PRIM

+1.0V_MPHYAON

+1.0V_C LK6_24T BT

1U_0402_6.3V6K

1

@

2

+1.0V_DTS

+3V_PRIM

22U_0603_6.3V6M

CC134

22U_0603_6.3V6M

CC130

1U_0402_6.3V6K

1

CC67

@

2

22U_0603_6.3V6M

CC137

1U_0402_6.3V6K

1

CC76

2

RC150 1 2 0_0402_5%

1U_0402_6.3V6K

1

CC72

2

+3V_PRIM

RC197 1 2 0_0402_5%

RC154 1 2 0_0402_5%

RC161 1 2 0_0402_5%

RC163 1 2 0_0402_5%

<Diner-DB> change to +3V_PRIM

RC1721 2 0_0402_5%

1U_0402_6.3V6K

1

CC87

2

RC167 1 2 0_0402_5%

22U_0603_6.3V6M

22U_0603_6.3V6M

1U_0402_6.3V6K

1

CC86

@

2

1

1

CC139

CC138

CC75

@

@

2

2

RC171 1 2 0_0402_5%

+3V_HDA

+3V_PGPPA

+3V_SPI

+3V_PGPPB

1U_0402_6.3V6K

1

2

+3V_PGPPC

1U_0402_6.3V6K

1

2

+3V_1.8V_PGPPD

1U_0402_6.3V6K

1

@

2

+3V_PGPPE

1U_0402_6.3V6K

1

2

+3V_PRIM_RTC

1U_0402_6.3V6K

1

2

1

CC63
1U_0201_6.3V6K

2

CC102

CC73

RC2061 @ 2 0_0402_5%

CC103

CC74

0.1U_0201_10V6K

1

CC78

CC77

2

+1.8V_PRIM

near pi n K15,L 15

near pi n N18

near pi n AF20,
AF21,T1 9, T20

near pi n N15, N16,
N17, P15,P 16

+1.0V_PRIM

CC147

@

CC80

22U_0603_6.3V6M

1

CC148

2

@

+1.0V_PRIM

+1.0V_PRIM

+1.0V_PRIM

22U_0603_6.3V6M

1

CC81

2

1U_0402_6.3V6K

1

CC61

2

1U_0402_6.3V6K

CC68

1

2

1U_0201_6.3V6K

1

CC141

2

22U_0603_6.3V6M

1

CC82

2

@

1

2

1U_0402_6.3V6K

CC85

+1.0V_PRIM

+1.0V_MPHYAON

+1.0V_PRIM

+1.0V_PRIM

+1.0V_APLL
+1.0V_PRIM

+3VALW _DSW

+3V_HDA

+3V_SPI
+1.0V_PRIM

+3V_PRIM
+1.0V_PRIM
+1.0V_PRIM

+1.0VO_DSW

<DB>Che ck Powe r Rail

Per 543016_SKL_U_Y_PDG_0_9

VCCRTC does not exceed 3.2 V From PDG

22U_0603_6.3V6M

1

@

2

1U_0402_6.3V6K

1

2

Power Rail Vo ltage

+CHGRT C 3.38 3V(MAX)

BAT54C (VF) 240 mV

+3VL_R TC 3.143 V

Result : Pass

<26,35, 51> PCH_PWR_ EN

<9,26> PM_SLP_SUS#

<12,26, 35,49> SUSP#

RC191 1 2 0_0402_5%
RC174 1 @ 2 0_0402_5%

RC392 1

Follow 543016_SKL_U_Y_PDG_0_9

+1.0V_PRIM +3V_PRIM +1. 8V_PRIM

A A

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

CC112

CC111

@

@

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

CC114

CC113

@

@

2

2

5 4 3 2 1

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

CC115

CC116

@

@

2

2

+3VS

RC178 1 2 0_0402_5%

+3VALW

RC173 1 2 0_0603_5%

Follow 543016_SKL_U_Y_PDG_0_9

+3VS_PGPPA

+3VALW _DSW

SecurityClllassiiifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING D RAWING IIIS THE PROPRIIIETARY P ROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRAD E SECRE T IIINFORMATIIION... THIIIS SHE ET MAY NOT BE TRA NSFERE D FROM THE CUSTODY OF THE COMPETE NT DIIIVIIISIIION OF R&D
DEPARTMENT E XCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NO R THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE US ED BY OR DIIISCLOSED TO ANY THIIIRD PARTY W ITHOUT PRIIIOR WRIIITTEN CON SENT OF COMPAL ELECTRONIIICS,,, IIINC...

2014/12/11 2015/12/31

+1.0V_PRIM

1U_0201_6.3V6K

1

CC91

2

AB19
AB20

AF18
AF19

AB17

AD17
AD18

AJ17
AJ19
AJ16

AF20
AF21

AJ21

AK20

For DS3

2

0_0402_5%

Compal Secret Data

Deciphered Date

UC1O

VCCPRIM_1P0
VCCPRIM_1P0

P18

VCCPRIM_1P0

VCCPRIM_CORE
VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAO N_1P0

L1

VCCMPHYAO N_1P0

N15

VCCMPHYGT_1P0 _N15

N16

VCCMPHYGT_1P0 _N16

N17

VCCMPHYG T_1P0_N17

P15

VCCMPHYG T_1P0_P15

P16

VCCMPHYG T_1P0_P16

K15

VCCAMPHYP LL_1P0

L15

VCCAMPHYP LL_1P0

V15

VCCAPLL_1P0

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18
VCCDSW _3P3_AD17

VCCDSW _3P3_AD18
VCCDSW _3P3_AJ17

VCCHDA

VCCSPI

VCCSRAM_1P0
VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0
VCCPRIM_3P3_AJ21
VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

SKL-U_BGA1356

CC7 Close UC1.AK19.

+RTCVCC

CC7

1U_0201_6.3V6K

+3VALW+5VALW

1U_0402_6.3V6K

@

1

CC52

2

+1.2V_VDDQ

1U_0402_6.3V6K

CC150

15mils

SKL-U

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCRTCPRIM_3P3

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

15 OF 20

RTC Battery

MAX. 8000mil

DC1

1

BAV70W 3P C/C_SOT -323

SC600000B00

CPU P OWE R 4 OF 4

1

2

+3VALW TO +3V_PRIM

I (Max) : 0.46 A(+3V_PRIM)
RDS(Typ) : 65 mohm
V drop : 0.03 V

1U_0402_6.3V6K

@

1

CC50

2

UC4

1

VIN1

EN_3V_PR IM

1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

EM5209VF_DFN14_2X3

SA00007PM00

RC141 1 @ 2 0_0402_5%

Rev_0 .53

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG

VCCATS_1P8

VCCRTC_AK19
VCCRTC_BB14

DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6

AK15
AG15
Y16
Y15
T16
AF16
AD15

V19
T1

AA1

AK17

AK19
BB14

BB10

A14

K19
L21
N20
L19
A10

AN11 PRIMCORE_VID0
AN13 PRIMCORE_VID1

1209_follow G group GPI O
powe rail to +3V_PRIM

+3V_PGPPA
+3V_PGPPB
+3V_PGPPC
+3V_1.8V_PGPPD
+3V_PGPPE
+1.8V_PRIM
+3V_PRIM For SD CARD

+3V_PRIM
+1.0V_D TS
+1.8V_PRIM
+3V_PRIM_RTC
+RTCVCC

CC71 1 2 0.1U_0402_10V7K

+1.0V_C LK6_24T BT

+1.0V_APLL
+1.0V_C LK4_F100 OC
+1.0V_C LK5_F24N S
+1.0V_C LK6_24T BT

T130 TP@
T131 TP@

<DB> RTC BAT Conn

JRTC1

2

-

CONN@

LOTES_AAA-BAT-054-K01

SP07000H700

+RTCBATT_R

1K_0402_5%

RC19

2 2
3

+3VALW

14

VOUT1

132

VOUT1

12

CT1

1000P_0402_ 50V7K

11

GND

10

CT2

1000P_0402_ 50V7K

9

VOUT2

8

VOUT2

15

GPAD

Compal Electronics, Inc.

Tiiitllle

SKL-U(9/12)Power

Size Document Number

Custom

LA-D707P

Date: Wednesday, May 11, 2016 Sheet 13 o f 60

+RTCBATT

15mils15mils

1

+3VL

1

RC393

+3V_PRIMJ P 1 @ 2 0_0805_5% RC159

2 0_0805_5%

For NON-DS3

For DS3

@

CC53 1 2

CC1491 2

+1.2V_VCCSFR_OC

0.1U_0201_10V6K

1

CC49

2

+

+3V_PRIM

20mils

1

1

2

0.1U_0402_25V6

CC51

+RTCBATT

Rev

v0.2

5 4 3 2 1

UC1L

A30

VCC_A30

A34

VCC_A34

D D

T123 TP@
T121 TP@

For CPU2+3e SKU

C C

SVID ALERT

B B

A39

A44
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40

AM32
AM33
AM35
AM37
AM38

G30

K32
AK32
AB62

P62

V62

H63

G61
AC63

AE63
AE62

AG62

AL63
AJ62

+1.0V_VCCST

1

RC179
56_0402_5%

2

VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30

RSVD_K32
RSVD_AK32
VCCOPC_AB62

VCCOPC_P62
VCCOPC_V62

VCC_OPC_1P8_H63
VCC_OPC_1P8_G61
VCCOPC_SENSE

VSSOPC_SENSE
VCCEOPIO

VCCEOPIO
VCCEOPIO_SENSE

VSSEOPIO_SENSE

SKL-U_BGA1356

Place the PU
resistors close to CPU

SKL-U

CPU POWER 1 OF4

12 OF20

Rev_0.5 3

VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43

VCC_SENSE
VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43

E32
E33

B63 SOC_SVID_ALERT#
A63 SOC_SVID_CLK D64

SOC_SVID_DAT

G20

Trace Length < 25 mils

VCCSENSE <52>
VSSSENSE <52>

SOC_SVID_CLK <52>

+1.0VS_VCCIO

<52> VCCGT_SENSE
<52> VSSGT_SENSE

Trace Length < 25 mils

VCCGT_SENSE
VSSGT_SENSE

+VCC_GT +VCC_GT+VCC_CORE +VCC_CORE

A48
A53
A58
A62

A66
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71

J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60

K48
K50
K52
K53
K55
K56
K58
K60

L62
L63
L64
L65
L66
L67
L68
L69
L70

L71
M62
N63
N64
N66

VCCGT

N67

VCCGT

N69

J70

VCCGT_SENSE

J69

VSSGT_SENSE

UC1M

VCCGT
VCCGT
VCCGT

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGT

SKL-U_BGA1356

CPU POWER 2 OF4

SKL-U

13 OF20

Rev_0.5 3

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53

VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63

VCCGTX_BB57

VCCGTX_BB66

VCCGTX_SENSE

VSSGTX_SENSE

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK42

AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53

AL56

AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63

BB57

BB66

AK62 VCCGTX_SENSE
AL61 VSSGTX_SENSE

For CPU2+3e SKU

T155 TP@
T219 TP@

SOC_SVID_ALERT# 1

RC180

SVID DATA

A A

SOC_SVID_DAT

5 4 3 2

2

220_0402_5%

+1.0V_VCCST

1

RC181
100_0402_1%

2

SOC_SVID_ALERT#_R <52>

Place the PU
resistors close to CPU

SOC_SVID_DAT <52>

(To VR)

(To VR)

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

Compal SecretData

Deciphered Date

Compal Electronics, Inc.

Title

Siiize

Custom
Date: Wednesday, May 11, 2016 Sheet114 of 60

SKL-U(10/12)Power,SVID

Document Number

LA-D707P

Rev

v0.2

5 4 3 2 1

D D

A5
A67
A70
AA2
AA4

AA65
AA68
AB15
AB16
AB18
AB21

AB8

AD13
AD16
AD19
AD20
AD21
AD62

AD8
AE64
AE65
AE66
AE67
AE68

C C

B B

AE69

AF1
AF10
AF15
AF17

AF2

AF4
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13

AH6
AH63
AH64
AH67

AJ15
AJ18
AJ20

AJ4
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69

AK8

AL2

AL28
AL32
AL35
AL38

AL4

AL45
AL48
AL52
AL55
AL58
AL64

UC1P

GND 1 OF3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL-U_BGA1356

SKL-U

Rev_0.5 3 Rev_0.5 3

AL65

VSS

AL66

VSS

AM13

VSS

AM21

VSS

AM25

VSS

AM27

VSS

AM43

VSS

AM45

VSS

AM46

VSS

AM55

VSS

AM60

VSS

AM61

VSS

AM68

VSS

AM71

VSS

AM8

VSS

AN20

VSS

AN23

VSS

AN28

VSS

AN30

VSS

AN32

VSS

AN33

VSS

AN35

VSS

AN37

VSS

AN38

VSS

AN40

VSS

AN42

VSS

AN58

VSS

AN63

VSS

AP10

VSS

AP18

VSS

AP20

VSS

AP23

VSS

AP28

VSS

AP32

VSS

AP35

VSS

AP38

VSS

AP42

VSS

AP58

VSS

AP63

VSS

AP68

VSS

AP70

VSS

AR11

VSS

AR15

VSS

AR16

VSS

AR20

VSS

AR23

VSS

AR28

VSS

AR35

VSS

AR42

VSS

AR43

VSS

AR45

VSS

AR46

VSS

AR48

VSS

AR5

VSS

AR50

VSS

AR52

VSS

AR53

VSS

AR55

VSS

AR58

VSS

AR63

VSS

AR8

VSS

AT2

VSS

AT20

VSS

AT23

VSS

AT28

VSS

AT35

VSS

AT4

VSS

AT42

VSS

AT56

VSS

AT58

VSS

16 OF20

AT63
AT68

AT71
AU10
AU15
AU20
AU32
AU38

AV1
AV68
AV69
AV70
AV71

AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57

AW6
AW60
AW62
AW64
AW66

AW8

AY66

B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71

BA1
BA10
BA14
BA18

BA2
BA23
BA28
BA32
BA36

F68
BA45

UC1Q

GND 2 OF3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL-U_BGA1356

SKL-U

17 OF20

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41

G10
G22
G43
G45
G48

G52
G55
G58

G60
G63
G66

H15
H18
H71
J11
J13
J25
J28
J32
J35
J38
J42

K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71
L11
L16
L17

F8

G5

G6

J8

UC1R

GND 3 OF3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL-U_BGA1356

SKL-U

18 OF20

Rev_0.5 3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21

A A

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5 4 3 2

2014/05/19 2015/12/31

Compal SecretData

Deciphered Date

Compal Electronics,Inc.

Title

Siiize

Custom
Date: Wednesday, May 11, 2016 Sheet115 of 60

SKL-U(11/12)GND

Document Number

LA-D707P

Rev

v0.2

5 4 3 2 1

D D

UC1S

RESERVED SIGNALS- 1

SKL-U_BGA1356

CFG4 E70

E68
B67
D65
D67

C68
D68

C67
G69
G68

H70
G71

H69
G70

E63

E66

AY2
AY1

K46

K45

AL25

AL27

C71

B70

A52

BA70
BA68

G65

E61

F71
F70

F63

F66

D1
D3

F60

J71
J68

F65

F61

CFG[4]

ITP_PMODE

CFG[0]
CFG[1]
CFG[2]
CFG[3]

CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[16]
CFG[17]

CFG[18]

CFG[19]
CFG_RCOMP

RSVD_AY2
RSVD_AY1

RSVD_D1
RSVD_D3

RSVD_K46
RSVD_K45

RSVD_AL25

RSVD_AL27

RSVD_C71
RSVD_B70

RSVD_F60
RSVD_A52
RSVD_TP_BA70

RSVD_TP_BA68
RSVD_J71

RSVD_J68
VSS_F65

VSS_G65
RSVD_F61

RSVD_E61

T272 TP@
T273 TP@
T274 TP@

<5> CFG3

T275 TP@
T276 TP@
T277 TP@
T278 TP@
T279 TP@
T281 TP@
T280 TP@
T283 TP@
T282 TP@
T284 TP@
T285 TP@

T286 TP@
T287 TP@

T288 TP@

C C

<5> XDP_ITP_PMODE

B B

T289 TP@

T192 TP@
T194 TP@

T196 TP@
T198 TP@

T200 TP@

T205 TP@
T206 TP@

T209 TP@
T211 TP@
T213 TP@

T300 TP@
T217 TP@

T218 TP@
T220 TP@

T222 TP@
T224 TP@

T226 TP@

CFG_RCOMP E60

XDP_ITP_PMODE E8

SKL-U

19 OF20

Rev_0.5 3

RSVD_TP_BB68
RSVD_TP_BB69

RSVD_TP_AK13
RSVD_TP_AK12

RSVD_BB2
RSVD_BA3

TP5
TP6

RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2

RSVD_B3
RSVD_A3

RSVD_AW1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4
RSVD_C4

TP4

RSVD_A69

RSVD_B69

RSVD_AY3

RSVD_D71
RSVD_C70

RSVD_C54
RSVD_D54

TP1
TP2

VSS_AY71

ZVM#

RSVD_TP_AW71
RSVD_TP_AW70

MSM#

PROC_SELECT#

BB68
BB69

AK13
AK12

BB2
BA3

AU5
AT5

D5
D4
B2
C2

B3

A3

AW1

E1
E2

BA4
BB4

A4
C4

BB5

A69

B69

AY3

D71
C70

C54

D54
AY4

BB3

AY71

PM_ZVM#

AR56

AW71
AW70

AP56PM_MSM#
C64 SKL_CNL#

T156 TP@
T157 TP@

T158 TP@
T159 TP@

T162 TP@
T163 TP@

T166 TP@
T167 TP@

T170 TP@
T252 TP@

T174 TP@
T179 TP@

T183 TP@

T195 TP@
T197 TP@

T201 TP@
T203 TP@

RC182 1

T207 TP@
T208 TP@

T210 TP@
T301 TP@

1 RC183 2 0_0402_5%

T225 TP@
T333 TP@

T223 TP@
T230 TP@

1 @ 2

RC184 100K_0402_5%

2 0_0402_5%

+1.0V_VCCST

Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0

AW69

AW68

AU56
AW48

U12
U11
H11

For 2+3e Solution
PM_ZVM#
PM_MSM#

UC1T

RSVD_AW69
RSVD_AW68

RSVD_AU56

RSVD_AW48

C7

RSVD_C7
RSVD_U12
RSVD_U11

RSVD_H11

SKL-U_BGA1356

SPARE

SKL-U

20 OF20

Rev_0.5 3

RSVD_F6

RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52

E3
C11
B11

C12
F52

F6

A11
D12

T227 TP@

CFG_RCOMP 1

RC185

CFG4

RC193

A A

Display Port Presence Strap

CFG4

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

5 4 3 2

2

49.9_0402_1%

1

2

1K_0402_1%

SecurityClassification

Issued Date

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

Compal SecretData

Deciphered Date

Compal Electronics,Inc.

Title

Siiize

Custom
Date: Sheet116 of 60

SKL-U(12/12)RSVD

Document Number

LA-D707P

Wednesday, May 11,2016

Rev

v0.2

5 4 3 2 1

CHANNEL-A

Interleaved Memory

TOP: JDIMM1 CONN Non-ECC DIMM

D D

@

2

1

1

RD1

0_0402_5%

RD3
0_0402_5%

2

@

2

1

1

RD4

0_0402_5%

SA1_CHA_DIM1SA0_CHA_DIM1

RD5
0_0402_5%

2

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL A :
WRITE ADDRESS: 0XA0

READ ADDRESS: 0XA1

SA0 = 0; SA1 = 0; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S

C C

STRETCH GOAL IS 2133 MT/S

Layout Note:
Place n ear J DIMM1. 257,259

+2.5V +0.6V_0.6VS

10U_0603_6.3V6M

1

1

CD3

2

2

Layout Note:
PLACE T HE CAP near J DIMM1. 164

B B

+0.6V_D DR_VREFCA

2 2

CD11 CD12

0.1U_0402_10V 6K 12.2U_0402_6.3V6M

1

Layout Note:
Place n ear JD IMM1

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CD93

A A

CD16

2

2

10uF *2
1uF*2

10U_0603_6.3V6M

1U_0402_6.3V6K

1

CD4

CD5

2

10U_0603_6.3V6M

1

1

CD17

2

2

0.1U_0402_25V6

1U_0402_6.3V6K

1

1

2

10U_0603_6.3V6M

CD18

@ESD@

CC159

CD6

2

2.2u F*1

0.1u F*1

10uF *6
1uF*8
330u F*1

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CD19

2

2

5 4 3 2 1

+3VS+3VS+3VS

1

RD2

@

0_0402_5%

2

SA2_CHA_DIM1

1

RD6
0_0402_5%

2

+3V_PRIM_DA

2

1

8/26

0.1U_0402_10V6K

CD1

+1.2V_VDDQ

2.2U_0402_6.3V6M

2

1

PLACE NEAR TO PIN

Layout Note:
Place n ear JDIMM 1.258

10uF *2
1uF*1

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CD20

2

10U_0603_6.3V6M

1

1

CD21

CD22

CD23

2

2

@

1U_0402_6.3V6K

1

1

CD8

CD7

RD32 0_0402_5%

2

1 2

CD9

2

+3V_PRIM_DA+3V_PRIM

+1.2V_VDDQ+1.2V_VDDQ

10U_0603_6.3V6M

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

1

CD95

CD96

2

2

Part Number:LTCX0069GA0
Part Value:S SOCKET FOX AS0A827-H2RB-7H 260P DDR4

1U_0402_6.3V6K

1

1

CD25

CD24

2

2

+0.6V_D DR_VREFCA

CD2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CD26

CD27

2

<6> DDR_A_D[0..15]
<6> DDR_A_D[16..31]
<6> DDR_A_D[32..47]

<6> DDR_A_D[48..63]

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD29

CD28

2

2

JDIMM1B

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND GND

FOX_AS0 A827-H2 RB-7H

CONN@

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD30

2

2

STD

141

VDD11

142

VDD12

147

VDD13

148

VDD14

153

VDD15

154

VDD16

159

VDD17

160

VDD18

163

VDD19

258

VTT

257

VPP1

259

VPP2

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193
196

VSS

197

VSS

201

VSS

202

VSS

205

VSS
VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244
247

VSS

248

VSS
VSS

251

VSS

252

VSS

261

+1.2V_VDDQ

1U_0402_6.3V6K

1

CD31

CD94

2

C174

330U_2.5V_M

REVERSE TYPE

+1.2V_VDDQ

+0.6V_0.6VS

+2.5V

+1.2V_VDDQ

DDR_DRAMRST#_R

2

@

CD13

0.1U_0402_10V6K

1

1

+

Part Number = SF000006S00

2

SecurityClllassiiifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING D RAWING IIIS THE PROPRIIIETARY P ROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRAD E SECRE T IIINFORMATIIION... THIIIS SHE ET MAY NOT BE TRA NSFERE D FROM THE CUSTODY OF THE COMPETE NT DIIIVIIISIIION OF R&D
DEPARTMENT E XCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NO R THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE US ED BY OR DIIISCLOSED TO ANY THIIIRD PARTY W ITHOUT PRIIIOR WRIIITTEN CON SENT OF COMPAL ELECTRONIIICS,,, IIINC...

<6> DDR_A_CLK0
<6> DDR_A_CLK#0
<6> DDR_A_CLK1
<6> DDR_A_CLK#1

<6> DDR_A_CKE0
<6> DDR_A_CKE1

<6> DDR_A_CS#0
<6> DDR_A_CS#1

<6> DDR_A_ODT0
<6> DDR_A_ODT1

<6> DDR_A_BG0
<6> DDR_A_BG1
<6> DDR_A_BA0
<6> DDR_A_BA1

<6> DDR_A_MA0
<6> DDR_A_MA1
<6> DDR_A_MA2
<6> DDR_A_MA3
<6> DDR_A_MA4
<6> DDR_A_MA5
<6> DDR_A_MA6
<6> DDR_A_MA7
<6> DDR_A_MA8
<6> DDR_A_MA9
<6> DDR_A_MA10
<6> DDR_A_MA11
<6> DDR_A_MA12
<6> DDR_A_MA13

9/8 Modify

<6> DDR_A_MA14_WE#

<6> DDR_A_MA15_CAS#

<6> DDR_A_MA16_RAS#
<6> DDR_A_ACT#
<6> DDR_A_PAR

<6> DDR_A_ALERT#

RD7 2 1
240_0402_<1%

6,18> DDR_DRAMRST#_R

<7,18,1 9,22> PCH_SMBDAT A
<7,18,1 9,22> PCH_SMBCLK

+1.2V_VDDQ

2

CD10

0.1U_0402_10V6K

@ESD@

1

PLACE NEAR TO SODIMM

+1.2V_VDDQ

2

RD8
1K_0402_1%

1

2

RD10
1K_0402_1%

1

2015/08/03 2015/12/31

(5.2 mm)

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1

DDR_A_CKE0
DDR_A_CKE1

DDR_A_CS#0
DDR_A_CS#1

DDR_A_ODT0
DDR_A_ODT1

DDR_A_BG0
DDR_A_BG1
DDR_A_BA0
DDR_A_BA1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13 158
DDR_A_MA14_WE# 151
DDR_A_MA15_CAS# 156
DDR_A_MA16_RAS# 152

DDR_A_ACT# 114
DDR_A_PAR 143

DDR_A_ALERT# 116
DIMM1_CHA_EVENT# 134
DDR_DRAMRST#_R 108

PCH_SMBDATA 254
PCH_SMBCLK 253

SA2_CHA_DIM1
SA1_CHA_DIM1
SA0_CHA_DIM1

For ECC DIMM

9/8 Modify base on ESD Request

DIMM Side

+0.6V_D DR_VREFCA

1 RD9

2_0402_1%

2

CD14

0.1U_0402_10V6K

1

Compal Secret Data

Deciphered Date

JDIMM1A

137

CK0(T)

139

CK0#(C) DQ1

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12
A13
A14_W E#
A15_CAS#
A16_RAS#

ACT#

PARITY
ALERT #
EVENT #
RESET#

SDA
SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

97

CB7_NC

95

DQS8(T)
DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7# DQS6(T)

96

DM8#/DBI8# DQS6#(C)

FOX_AS0 A827-H2 RB-7H

CONN@

CPU Side

+0.6V_VREFCA

2

1

0.022U_0402_25V7K

2

RD11

24.9_0402_1%

1 2

STD

CD15

8 DDR_A_D0

DQ0

7 DDR_A_D4

20 DDR_A_D3

DQ2

21 DDR_A_D7

DQ3

4 DDR_A_D1

DQ4

3 DDR_A_D5

DQ5

16 DDR_A_D2

DQ6

17 DDR_A_D6

DQ7

13 DDR_A_DQS0

DQS0(T)

11 DDR_A_DQS#0

DQS0#(C)

28 DDR_A_D8

DQ8

29 DDR_A_D12

DQ9

41 DDR_A_D14
42 DDR_A_D10

DQ10

24 DDR_A_D9

DQ11

25 DDR_A_D13

DQ12

38 DDR_A_D11

DQ13

37 DDR_A_D15

DQ14

34 DDR_A_DQS1

DQ15

32 DDR_A_DQS#1

DQS1(T)

DQS1#(C)

50 DDR_A_D21

DQ16

49 DDR_A_D17

DQ17

62 DDR_A_D23

DQ18

63 DDR_A_D18

DQ19

46 DDR_A_D16

DQ20

45 DDR_A_D20

DQ21

58 DDR_A_D19

DQ22

59 DDR_A_D22

55 DDR_A_DQS2

DQ23

53 DDR_A_DQS#2

DQS2(T)

DQS2#(C)

70 DDR_A_D25

DQ24

71 DDR_A_D28

DQ25

83 DDR_A_D30

DQ26

84 DDR_A_D31

DQ27

66 DDR_A_D24

DQ28

67 DDR_A_D29
79 DDR_A_D27

DQ29

80 DDR_A_D26

DQ30

76 DDR_A_DQS3

DQ31

74 DDR_A_DQS#3

DQS3(T)

DQS3#(C)

174 DDR_A_D32

DQ32

173 DDR_A_D37

DQ33

187 DDR_A_D34
186 DDR_A_D39

DQ34

170 DDR_A_D36

DQ35

169 DDR_A_D33

DQ36

183 DDR_A_D35

DQ37

182 DDR_A_D38

DQ38

179 DDR_A_DQS4

DQ39

177 DDR_A_DQS#4

DQS4(T)

DQS4#(C)

195 DDR_A_D44
194 DDR_A_D45

DQ40

207 DDR_A_D42

DQ41

208 DDR_A_D43

DQ42

191 DDR_A_D41

DQ43

190 DDR_A_D40

DQ44

203 DDR_A_D46

DQ45

204 DDR_A_D47

DQ46

200 DDR_A_DQS5

DQ47

198 DDR_A_DQS#5

DQS5(T)

DQS5#(C)

216 DDR_A_D53
215 DDR_A_D48

DQ48

228 DDR_A_D54

DQ49

229 DDR_A_D50

DQ50

211 DDR_A_D52

DQ51

212 DDR_A_D49

DQ52

224 DDR_A_D55

DQ53

225 DDR_A_D51

DQ54

221 DDR_A_DQS6

DQ55

219 DDR_A_DQS#6

237 DDR_A_D60

DQ56

236 DDR_A_D57

DQ57

249 DDR_A_D59

DQ58

250 DDR_A_D62

DQ59

232 DDR_A_D56

DQ60

233 DDR_A_D61

DQ61

245 DDR_A_D58

DQ62

246 DDR_A_D63

242 DDR_A_DQS7

DQ63

240 DDR_A_DQS#7

DQS7(T)

DQS7#(C)

VREF traces should be at least 20 mils
wide with 20 mils spacing to other

signals

Tiiitllle

P18-DDRIV_CHA: DIMM0

Size Document Number

LA-D707P

Date: Wednesday, May 11, 2016 Sheet 17 o f 60

DDR_A_D QS0 < 6>

DDR_A_D QS#0 <6>

DDR_A_D QS1 < 6>

DDR_A_D QS#1 <6>

DDR_A_D QS2 < 6>

DDR_A_D QS#2 <6>

DDR_A_D QS3 < 6>

DDR_A_D QS#3 <6>

DDR_A_D QS4 < 6>

DDR_A_D QS#4 <6>

DDR_A_D QS5 < 6>

DDR_A_D QS#5 <6>

DDR_A_D QS6 < 6>

DDR_A_D QS#6 <6>

DDR_A_D QS7 < 6>

DDR_A_D QS#7 <6>

Compal Electronics, Inc.

Rev

v0.2

5 4 3 2 1

STD (5.2 mm)

CHANNEL-B

Interleaved Memory

8/26

0.1U_0402_10V6K

1

2

CD60

1U_0402_6.3V6K

<6> DDR_B_D[0..15]

<6> DDR_B_D[16..31]
<6> DDR_B_D[32..47]
<6> DDR_B_D[48..63]

+1.2V_VDDQ

2.2U_0402_6.3V6M

+0.6V_D DRB_VREF CA

2

CD61

1

1U_0402_6.3V6K

1

CD88

CD89

2

JDIMM2B

STD

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2
5 VSS

6 VSS

9 VSS
10 VSS
14 VSS
15 VSS
18 VSS
19 VSS
22 VSS
23 VSS
26 VSS
27 VSS
30 VSS
31 VSS
35 VSS
36 VSS
39 VSS
40 VSS
43 VSS
44 VSS
47 VSS
48 VSS
51 VSS
52 VSS
56 VSS
57 VSS
60 VSS
61 VSS
64 VSS
65 VSS
68 VSS
69 VSS
72 VSS
73 VSS
77 VSS
78 VSS
81 VSS
82 VSS
85 VSS
86 VSS
89 VSS
90 VSS
93 VSS
94 VSS

VSS

98

VSS

262

GND

FOX_AS0 A827-H2 SB-7H

Part Number:LTCX0069FA0
Part Value:S SOCKET FOX AS0A827-H2SB-7H 260P DDR4

CONN@

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19

VPP1
VPP2

GND

141
142
147
148
153
154
159
160
163

258

VTT

257

259

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

261

+1.2V_VDDQ

+0.6V_0.6VS
+2.5V

+1.2V_VDDQ

+1.2V_VDDQ

2

CD71

@

0.1U_0402_10V6K

1

1U_0402_6.3V6K

1

CD90

2

2

CD81

0.1U_0402_10V6K

1

9/8 Modify

+1.2V_VDDQ

DDR_DRAMRST#_R

2

RD26
1K_0402_1%

1

2

RD28
1K_0402_1%

1

TOP: JDIMM2 CONN Non-ECC DIMM

+3VS+3VS+3VS

CD64

CD74

10uF *2
1uF*2

1

2

2

1

1

2

12

1

@

2

1U_0402_6.3V6K

CD65

2.2u F*1

0.1u F*1

CD70

2.2U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CD75

CD76

2

RD20
0_0402_5%

RD23

0_0402_5%

10uF *6
1uF*8
330u F*1

10U_0603_6.3V6M

1

2

1

RD21

@

0_0402_5%

2

SA2_CHB_DIM2SA1_CHB_DIM2SA0_CHB_DIM2

1

RD24
0_0402_5%

2

+3V_PRIM_DB

2

1

PLACE NEAR TO PIN

Layout Note:
Place n ear JDIMM 2.258

+0.6V_0.6VS+2.5V

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CD77

2

1

CD79

CD78

2

2

@

10uF *2
1uF*1

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1

1

CD66

CD67

CD68

2

2

+3V_PRIM_DB+3V_PRIM

1 2

RD33 0_0402_5%

+1.2V_VDDQ+1.2V_VDDQ

10U_0603_6.3V6M

1U_0402_6.3V6K

1

CD80

@

1

CD83

2

2

1U_0402_6.3V6K

1

CD84

2

1U_0402_6.3V6K

1

1

CD86

CD85

CD87

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

D D

@

2

1

1

RD19

0_0402_5%

RD22
0_0402_5%

2

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL B :
WRITE ADDRESS: 0XA4
READ ADDRESS: 0XA3
SA0 = 0; SA1 = 1; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S
STRETCH GOAL IS 2133 MT/S

C C

Layout Note:
Place n ear J DIMM2. 257,259

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

Layout Note:
PLACE T HE CAP WITHIN 200 MI LS
FROM TH E JD IMM2

B B

+0.6V_D DRB_VREF CA

2

1

A A

1U_0402_6.3V6K

1

1

CD63

CD62

2

2

CD69

0.1U_0402_10V6K

Layout Note:
Place n ear JD IMM2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CD73

2

2

<6> DDR_B_CLK0
<6> DDR_B_CLK#0

<6> DDR_B_CLK1

<6> DDR_B_CLK#1
<6> DDR_B_CKE0

<6> DDR_B_CKE1
<6> DDR_B_CS#0

<6> DDR_B_CS#1

<6> DDR_B_ODT0
<6> DDR_B_ODT1

<6> DDR_B_BG0
<6> DDR_B_BG1
<6> DDR_B_BA0
<6> DDR_B_BA1

<6> DDR_B_MA0
<6> DDR_B_MA1
<6> DDR_B_MA2
<6> DDR_B_MA3
<6> DDR_B_MA4
<6> DDR_B_MA5
<6> DDR_B_MA6
<6> DDR_B_MA7
<6> DDR_B_MA8
<6> DDR_B_MA9
<6> DDR_B_MA10
<6> DDR_B_MA11
<6> DDR_B_MA12
<6> DDR_B_MA13

<6> DDR_B_MA14_WE#

<6> DDR_B_MA15_CAS#

<6> DDR_B_MA16_RAS#
<6> DDR_B_ACT#
<6> DDR_B_PAR

<6> DDR_B_ALERT#

RD25 2 1
240<_064,1072>_1%

DDR_DRAMRST#_R

<7,17,1 9,22> PCH_SMBDAT A
<7,17,1 9,22> PCH_SMBCLK

For ECC DIMM

2

CD92

0.1U_0402_10V6K

@ESD@

1

PLACE NEAR TO SODIMM

DIMM Side

+0.6V_D DRB_VREF CA

2

CD72

0.1U_0402_10V6K

1

1 RD27 2

2_0402_1%

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1

DDR_B_CKE0
DDR_B_CKE1

DDR_B_CS#0
DDR_B_CS#1

DDR_B_ODT0
DDR_B_ODT1

DDR_B_BG0
DDR_B_BG1
DDR_B_BA0
DDR_B_BA1

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14_WE#
DDR_B_MA15_CAS#
DDR_B_MA16_RAS#

DDR_B_ACT# 114
DDR_B_PAR 143

DDR_B_ALERT#
DIMM2_CHB_EVENT# 134
DDR_DRAMRST#_R

PCH_SMBDATA

PCH_SMBCLK

SA2_CHB_DIM2
SA1_CHB_DIM2
SA0_CHB_DIM2

1

CD82

0.022U_0402_25V7K

2

RD29

24.9_0402_1%

1 2

JDIMM2A

137

CK0(T)

139

CK0#(C) DQ1

138

CK1(T) DQ2

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_W E#

156

A15_CAS#

152

A16_RAS#

ACT#

PARITY

116

ALERT#

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8# DQS6#(C)

FOX_AS0 A827-H2 SB-7H

CONN@

STD

DQ0

DQ3
DQ4
DQ5
DQ6
DQ7

DQS0(T)

DQS0#(C)

DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQS1(T)

DQS1#(C)

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQS2(T)

DQS2#(C)

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS3(T)

DQS3#(C)

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS4(T)

DQS4#(C)

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQS5(T)

DQS5#(C)

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQS6(T)

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS7(T)

DQS7#(C)

DDR_B_D15

8

DDR_B_D10

7

DDR_B_D11

20
21 DDR_B_D12

DDR_B_D14

4

DDR_B_D 9

3
16 DDR_B_D8
17 DDR_B_D13
13 DD R_B_DQS1

11 DD R_B_DQS#1

28 DDR_B_D0
29 DDR_B_D5
41 DDR_B_D7
42 DDR_B_D6
24 DDR_B_D4
25 DDR_B_D1
38 DDR_B_D3
37 DDR_B_D2
34 DD R_B_DQS0

32 DD R_B_DQS#0

50 DDR_B_D20
49 DDR_B_D17
62 DDR_B_D19
63 DDR_B_D22
46 DDR_B_D21
45 DDR_B_D16
58 DDR_B_D18
59 DDR_B_D23

55 DDR_B_DQS2
53 DDR_B_DQS# 2

70 DDR_B_D25
71 DDR_B_D24
83 DDR_B_D31
84 DDR_B_D27
66 DDR_B_D28
67 DDR_B_D29
79 DDR_B_D30
80 DDR_B_D26

76 DDR_B_DQS3
74 DDR_B_DQS# 3

174 DDR_B_D37
173 DDR_B_D33
187 DDR_B_D35
186 DDR_B_D38
170 DDR_B_D32
169 DDR_B_D36
183 DDR_B_D34
182 DDR_B_D39

179 DDR_B_DQS4
177 DD R_B_DQS#4

195 DDR_B_D44
194 DDR_B_D45
207 DDR_B_D42
208 DDR_B_D47
191 DDR_B_D40
190 DDR_B_D41
203 DDR_B_D43
204 DDR_B_D46

200 DDR_B_DQS5
198 DD R_B_DQS#5

216 DDR_B_D48
215 DDR_B_D53
228 DDR_B_D54
229 DDR_B_D51
211 DDR_B_D52
212 DDR_B_D49
224 DDR_B_D55

225 DDR_B_D50
221 DDR_B_DQS6
219 DD R_B_DQS#6

237 DDR_B_D60
236 DDR_B_D57

249 DDR_B_D58

250 DDR_B_D62

232 DDR_B_D56

233 DDR_B_D61

245 DDR_B_D59

246 DDR_B_D63
242 DDR_B_DQS7
240 DD R_B_DQS#7

CPU Side

+0.6V_B_VREFDQ

VREF traces should be at least 20 mils
wide with 20 mils spacing to other
signals

DDR_B_DQS1 <6>

DDR_B_DQS#1 <6>

DDR_B_DQS0 <6>

DDR_B_DQS#0 <6>

DDR_B_DQS2 <6>

DDR_B_DQS#2 <6>

DDR_B_DQS3 <6>

DDR_B_DQS#3 <6>

DDR_B_DQS4 <6>

DDR_B_DQS#4 <6>

DDR_B_DQS5 <6>

DDR_B_DQS#5 <6>

DDR_B_DQS6 <6>

DDR_B_DQS#6 <6>

DDR_B_DQS7 <6>

DDR_B_DQS#7 <6>

SecurityClllassiiifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING D RAWING IIIS THE PROPRIIIETARY P ROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRAD E SECRE T IIINFORMATIIION... THIIIS SHE ET MAY NOT BE TRA NSFERE D FROM THE CUSTODY OF THE COMPETE NT DIIIVIIISIIION OF R&D
DEPARTMENT E XCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NO R THE IIINFORMATIIION IIIT CONTAIIINS

5 4 3 2 1

MAY BE US ED BY OR DIIISCLOSED TO ANY THIIIRD PARTY W ITHOUT PRIIIOR WRIIITTEN CON SENT OF COMPAL ELECTRONIIICS,,, IIINC...

2015/08/03 2015/12/31

Compal Secret Data

Deciphered Date

Tiiitllle

Size Document Number

Date: Wednesday, May 11, 2016 Sheet 18 o f 60

Compal Electronics, Inc.
P19-DDRIV_CHB: DIMM0
LA-D707P

Rev

v0.2

5

D D

C C

4

3

2

>

1

+3VS<5,6,7, 9,10,11, 13,17,18,20,21,22,23,24,26, 28,32,33,34 ,35,3 6,37, 38,52, 55,56

+3VS

<CPU CTRL>

<5> EDP_HPD

EDP_HPD

1

RT11
100K_0402_5%

2

RTD2132 SMBus revrse to PCH

<7,10,2 2,26,37> EC_SMB_CK2
<7,10,2 2,26,37> EC_SMB_DA2

<7,17,1 8,22> PCH_SMBCLK

<7,17,1 8,22> PCH_SMBDAT A

<5> EDP_CPU _AUX _C

B B

<CPU>

<5> EDP_CPU _AUX#_C
<5> EDP_ CPU_LANE_P 0_C
<5> EDP_ CPU_LANE_N 0_C

<5> EDP_CPU_ LANE _P1_C
<5> EDP_CPU_ LANE _N1_C

<RTS2132>

<EC CTRL>

A A

<26> EC_BKOFF #

100K_0402_5%

5

RT193 1 2 0_0201_5%
RT194 1 2 0_0201_5%

RT195 1 @ 2 0_0201_5% RT 196

1 @ 2 0_0201_5%

Layoutnotes

L

CC97~CC102 must closed to connector

CT102 1 2 .1U_0402_16V7K ED P_CPU_AUX
CT101 1 2 .1U_0402_16V7K
CT98 1 2 .1U_0402_16V7K
CT97 1 2 .1U_0402_16V7K

CT103 1
CT100 1

TS_BKO FF#
EC_BKOF F#

RT12

LVDS@

2 .1U_0402_16V7K EDP_CPU_L ANE_ P1

e

DP

2 .1U_0402_16V7K EDP_CPU_L ANE_N 1

@

eDP@

DB phase :
add eDP Lan1 for FHD

20141117

RT14 1 2 0_0402_5 %

+3VS

1

2

RT15 0_0402_5%

1

B

2

A

@

3 5

1 2

EDP_CPU_AUX#
EDP_CPU_LANE _P0
EDP_CPU_LANE _N0

CT24

1 2

0.1U_0402_16V7K

UT3

4

Y

G P

LVDS@

TC7SH08FUF_S SOP5

CIICSCL1
CIICSDA1

@

EDP_HPD RT34 1

Delete BKL_PWM_CPU and DP_INT_PWM
20141113

EC_TS_ BKOFF# <20>

PD 100K on LVDS page

4

2 0_0201_5% EDP_HPD_PANEL

<LVDSPanel>

EDP_CPU_LANE _N0
EDP_CPU_LANE _P0

EDP_CPU_AUX
EDP_CPU_AUX#

EDP_HPD_PANE L <20>

EDP_CPU_LANE _P1
EDP_CPU_LANE _N1

DB phase :
add eDP Lan1 for FHD

20141117

SecurityClassification

IssuedDate

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF C OMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE S ECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRA NSFERE D FROM THE CUSTODY OF THE C OMPETEN T DIIIVIIISIIION OF R&D
DEPAR TMENT EXCE PT AS AUTHORIIIZED BY COMPA L ELECTRONIIICS,,, IIINC...NEIIITHER THIIIS SHEET NO R THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE U SED B Y OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CON SENT OF CO MPAL ELECTRONIIICS,,,IIINC...

3

0_0804_8P4R_5%

8 EDP_LANE_N0

1

7

2
3

6

4

5

eDP@

SD309000080

RP6

2

1 2

RT16 0_0402_5%

1 2

RT17 0_0402_5%

L

Compal SecretData

EDP_LAN E_P0

EDP_AUX

EDP_AUX #

Layout notes

L

RP6 RP9 RP10 must closed to connector

LVDS_T XP1_LP1
LVDS_T XN1_LN1

Layoutnotes
RT16~RT19 must closed to connector

DeciiipheredDate

2

EDP_AUX 4 5

EDP_AUX # 3 6
EDP_LAN E_N0 2 7
EDP_LAN E_P0 1 8

LVDS_T XP1_LP1 <20 >
LVDS_T XN1_LN1 < 20>

2015/3/12013/3/1

<eDP to connector><CPU by PASS eDP>

RP9

SD309000080

eDP@

LCD_CLK
LCD_DAT A
LVDS_T XN2_LN0
LVDS_T XP2_LP0

0_0804_8P4R_5%

4

Compal Electronics, Inc.

Tiiitllle

LVDS Translator-RTD2132N

Siiize Document Numb er

LA-D707P

Date: Wednesday, May 11, 2016

LCD_CLK <20>
LCD_DAT A <20>
LVDS_T XN2_LN0 <20>
LVDS_T XP2_LP0 <20 >

Sheet

1

Rev

v0.2

60

19

of

LVDS Power

<5> ENVDD_CPU

D D

5 4 3 2 1

+3VS

1 2

R172 0_0402_5%

+3VS

RG1

<SI> change to standard par SA00006Y800 (Dif f er ent f oot print)

N6U@

UG1

5

VIN

4

EN

G524B1T11U_SOT23-5

SA00006Y800

0_0201_5%

1 @ 2

1500P_0402_50V7K

CG1

eDP@

VOUT

1

2

GND

3

/OC

1

2

1

CG2

4.7U_0603_6.3V6K

2 2

MainSA00006Y800
2nd SA00007U000

3rd SA000079400

UG1

6U@

G524B2T11U SOT -23

SA00007BW00

0.1U_0402_16V7

K

1

+LCDVDD

CG3

W=60mils

SM010014520 3000ma
220o hm@100mhz
DCR 0.04

@EMI@ C117

680P_0402_50V7K

INVPWR_B+

1

2

1

C118
68P_0402_50V8J

2

W=60mils

JPHW1@

1

2

1 2

JUMP_43X79

6U@

FU1 1 2
FUSE 0438.500WR 0.5A 32V UL/CSA FAST

SP040004X00

+19.5VB

<5,6,7,9,10,11,13,17,18,19,21,22,23,24,26,28,32,33,34,35, 36,37,38,52,55,56> +3VS

<38,47,48,49,50,53,55,56> +19.5VB

<7,13,23,26,27,30,33,35,4 8,49,50,51,55> +3VALW

+3VS
+19.5VB
+3VALW

Camera

1 2

R170 0_0402_5%

L12 @EMI@

<11> USB20_N5

<11> USB20_P5

C C

Part Number =SM070003Y00

1

1 2

4

4 3

WCM-2012-900T_4P

1 2

R171 0_0402_5%

USB20_N5_R

2

3 USB20_P5_R

USB20_P5_R
USB20_N5_R

<24> D_MIC_CLK

<24> D_MIC_DATA

Touch Screen

<DB> for 5V/3V TS option

TS@

QTS1

2N7002K_SOT23

+VCC_TOUCH_IN

+3VALW +5VALW

1

@

RTS2
100K_0402_5%

2

D

13

2

G

S

RG4 1 @ 2 0_0402_5%

RG5 1 TS@ 2 0_0402_5%

<11> USB20_N6

<11> USB20_P6

2

Part Number = SM070003Y00

1

TS@

RTS3
100K_0402_5%

TOUCH_ON# <26>

+3VS

+5VS

B B

+VCC_TOUCH_IN

TS@

1

CTS1

0.1U_0402_16V4Z

2

+VCC_TOUCH

A A

1 1

TS6U@ @

C5223 CTS3

4.7U 6.3V MX5R

SE00000SO00

2

0.1U 16V K X7R 2

2

Touch Screen Power

TS@

1

RTS1
1K_0402_5%

TS@CTS2

1 2

2 2

0.047U_0402_16V7K

1

3

DGS

TS@

QTS2
S TR LP2301ALT1G 1PSOT-23-3

2

1

@R36

JP@ JPHW3 1

1 2

JUMP_43X39

SA00004ZA00 FG2

3

OUT

GND

AP2330W-7_SC59-3

5 4 3 2 1

0_0603_5%

2

TS6U@

1

IN

@ESD@ SCA00000U10

D7

2

1

3

PESD5V0U2BT_SOT23-3

<DB>LA1/LA2 closed to Aduio codec

D_MIC_CLK 1 2 D_MIC_L_CLK

D_MIC_DATA 1 2 D_MIC_L_DATA

D_MIC_L_CLK 2
D_MIC_L_DATA3

<5> BKL_PWM_CPU

<10> TS_GPIO_CPU

<26> TS_GPIO_EC

2

1

L13

1 2

4 3

WCM-2012-900T_4P

1 2

0_0402_5%

R5175

1 @EMI@ 2

4 3

R173 0_0402_5%

EMI@ SM01000B600

LA1 FBMA-L10-160808-301LMT_2P

R175 0_0402_5%

@ESD@

D3

SCA00000U10

1

PESD5V0U2BT_SOT23-3

1

R259

2

TS_GPIO_CPU

TS_GPIO_EC

0_0402_5%

R260

1 @ 2

R5187

1 2

INVTPWM

<PV> Touch GPIO control by EC

USB20_N6_R

USB20_P6_R

2

0_0402_5%

0_0402_5%

1 220P_0402_50V7K INVTPWM

C593 2

1

220P_0402_50V7K DISPOFF#

C594 2

EDP_CP U_LANE_P1
EDP_CP U_LANE_N 1

EDP_CP U_LANE_P0
EDP_CP U_LANE_N 0

EDP_CP U_AUX
EDP_CP U_AUX#

LVDS@

R163
100K_0402_5%

1

USB20_P6_R
USB20_N6_R

<19> EC_TS_BKOFF#

TS_GPIO

D6

2

1

3

PESD5V0U2BT_SOT23-3

@ESD@ SCA00000U10

Securiiity Clllassifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

EC_TS_BKOFF# 1 2

2013/02/26 2015/07/08

R166 33_0402_5%

1

R5176
10K_0402_5%

2

+3VS

Compal SecretData

JP@ JPHW4 1

1 2

JUMP_43X39

6U@

FG3 SA00004ZA00

1

IN

AP2330W-7_SC59-3

Deciphered Date

<19> LVDS_TXP1_LP1
<19> LVDS_TXN1_LN1

<19> LVDS_TXP2_LP0

<19> LVDS_TXN2_LN0

<19> LCD_CLK

<19> LCD_DATA

<19> EDP_HPD_PANEL

DISPOFF#

INVPWR_B+

+VCC_TOUCH

+3VS_CAMERA

2

3

OUT

2

GND

Touch screen

Camera

+3VS_CAMERA

1

2

LCD/LED PANEL Conn.

+LCDVDD

USB20_P6_R

USB20_N6_R
DISPOFF#
INVTPWM

TS_GPIO

USB20_N5_R
USB20_P5_R

D_MIC_L_CLK
D_MIC_L_DATA

1

@

C5221

.1U_0402_16V7K 2 4.7U 6.3V M X5R

6U@

C5222

SE00000SO00

Tiiitttllle

LVDS Connector

Siiize Documenttt Number

LA-C707P

Compal Electronics,Inc.

CONN@

JLVDS1

1

1

2

2 G1

3

3 G2

4

4 G3

5

5 G4

6

6 G5

7

7 G6

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

STARC_107K40-000001­G2 SP01000XE00

41
42
43
44
45

46

Rev

Sheettt 20 offf 60Dattte::: W ednesday, May 11, 2016

v0.2

5 4 3 2 1

+3VS

1

2

2

1 6

QG1A

2N7002KDW_SOT363-6

SB00000I700

2.2K_0804_8P4R_5%

10P_0402_50V8J

1

CM27

2

5V Level

PCH_DDPB_CLK

PCH_DDPB_DAT

RG105

1
2
3

4

<20,24,26,27,30,34,35,52,53,56>+5VS

HP_DETECT

1

RG56

20K_0402_5%

2

8 HDMI_SDATA
7 HDMI_SCLK
6 PCH_DDPB_DAT
5 PCH_DDPB_CLK

HP_DETECT

+HDMI_CRT_5V

HDMI_SDATA
HDMI_SCLK

HDMI_R_CK­HDMI_R_CK+

HDMI_R_D0­HDMI_R_D0+

HDMI_R_D1­HDMI_R_D1+

HDMI_R_D2­HDMI_R_D2+

<22> +HDMI_CRT_5V

1

CM17

@

220P_0402_50V7K

2

+3VS

5

QG2B SB00000I700
2N7002DWH_SOT363-6

HDMI Conn.

CONN@

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Utility

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+ GND1

3

D2- GND2

2

D2_shield GND3

1

D2+ GND4

ACON_HMRBL-AK120D

DC232004700

21

3 HDMI_SCLK4

+3VS

2

QG2A SB00000I700
2N7002DWH_SOT363-6

23

22
20

+HDMI_CRT_5V
+3VS
+5VS

6 HDMI_SDATA1

3

2

2 CG27
2 CG28

2 CG29
2 CG30

2 CG31
2 CG32

2 CG33
2 CG34

567

8

432

1

RP3 RP4
470_0804_8P4R_5% 470_0804_8P4R_5%

2

CG71

0.47P_0402_50V

1

HDMI_R_CK-

HDMI_R_D0-PCH_DPB_N0_C

2

CG72

0.47P_0402_50V

1

HDMI_R_D0+

HDMI_R_D1+PCH_DPB_P1_C

2

CG73

0.47P_0402_50V

1

HDMI_R_D1-

HDMI_R_D2+PCH_DPB_P2_C

2

CG74

0.47P_0402_50V

1

HDMI_R_D2-

Layout notes

L

40 mils

W=40mils

+HDMI_CRT_5V

1

CG46

0.1U_0402_16V7K

2

567

432

8

1

PCH_DPB_P0_C
PCH_DPB_N0_C

PCH_DPB_P1_C
PCH_DPB_N1_C

PCH_DPB_P2_C
PCH_DPB_N2_C

PCH_DPB_P3_C
PCH_DPB_N3_C

QG1B SB00000I700
2N7002KDW_SOT363-6

3 4

+3VS

HDMI_R_CK+
HDMI_R_CK-

HDMI_R_D0+
HDMI_R_D0-

HDMI_R_D1­HDMI_R_D1+

HDMI_R_D2­HDMI_R_D2+

HP_DETECT
HDMI_SDATA
HDMI_SCLK 4

5

@ESD@

D21

1

1

2

2

4

4

5

5

3

3

8

L05ESDL5V0NA-4_SLP2510P8-10-9

SC300002C00

@ESD@

D22

1

1

2

2

4

4

5

5

3

3

8

L05ESDL5V0NA-4_SLP2510P8-10-9

SC300002C00

SC300002800

DG1

@ESD@

1

1

2

2

4

5

5

3

3

8

IP4292CZ10-TB

9 HDMI_R_CK+

10

8 HDMI_R_CK-

9

7 HDMI_R_D0+

7

6 HDMI_R_D0-

6

9 HDMI_R_D1-

10

8 HDMI_R_D1+

9

7 HDMI_R_D2-

7

6 HDMI_R_D2+

6

9 HP_DETECT

10

8 HDMI_SDATA

9

7 HDMI_SCLK

7

6

6

<5> PCH_DDPB_HPD

DB phase :
For ESD request
20141117

<5,6,7,9,10,11,13,17,18,19,20,22,23,24,26,28,32,33,34,35,36,37,38,52,55,56> +3VS

RG47

1M_0402_5%

<5> PCH_DDPB_CLK

<5> PCH_DDPB_DAT

+HDMI_CRT_5V

+3VS

@ @

10P_0402_50V8J

1

CM26

2

<5> PCH_DPB_P0
<5> PCH_DPB_N0

<5> PCH_DPB_P1

<CPU>

<5> PCH_DPB_N1
<5> PCH_DPB_P2

<5> PCH_DPB_N2

D D

<5> PCH_DPB_P3
<5> PCH_DPB_N3

PCH_DPB_P0 0.1U_0402_16V7K 1
PCH_DPB_N0 0.1U_0402_16V7K 1

PCH_DPB_P1 0.1U_0402_16V7K 1
PCH_DPB_N1 0.1U_0402_16V7K 1

PCH_DPB_P2 0.1U_0402_16V7K 1
PCH_DPB_N2 0.1U_0402_16V7K 1

PCH_DPB_P3 0.1U_0402_16V7K 1
PCH_DPB_N3 0.1U_0402_16V7K 1

<Diner SI> change to 8.2 ohm and parallel 0.47p by EMI request
<PV> change to 10 ohm by EMI request
<DB> Delete Choke add parallel 150ohm

PCH_DPB_P3_C HDMI_R_CK+

C C

PCH_DPB_N3_C

PCH_DPB_P0_C

PCH_DPB_N1_C

B B

PCH_DPB_N2_C

RG59 1 2 8.2_0402_1%

RG60 1 2 8.2_0402_1%

RG63 1 2 8.2_0402_1%

RG61 1 2 8.2_0402_1%

RG65 1 2 8.2_0402_1%

RG64 1 2 8.2_0402_1%

RG70 1 2 8.2_0402_1%

RG66 1 2 8.2_0402_1%

HDMI Chock 2nd : SM070003K00

FG1

+5VS

A A

1

IN

AP2330W-7_SC59-3

SA00004ZA00

OUT

GND

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5 4 3 2 1

2011/06/29 2011/06/29

Compal SecretData

Deciphered Date

Title

Siiize Document Number

Date: Sheet

Compal Electronics, Inc.

HDMI Conn/Level shift

LA-D707P

Rev

21 of 60Wednesday, May 11,2016

v0.2

5

DP to CRT converter

4

3

2

<5,6,7,9,10,11,13,17,18,19 ,20,21,23,24,26 ,28,32,33,34,35,36, 37,38,52,55,56> +3VS

<20,21,24,26,27,30,34,35, 52,53,56> +5VS

1

<21> +HDMI_CRT_5V

+5VS
+3VS
+HDMI_CRT_5V

CRT@ CRT@

C60

1

0.1U_0402_16V4Z

2

+3VS_CRT

2

2

1

1

+3VS_CRT

CRT@

R35

+3VS_CRT_DVDD

C61 +VCCK_1V2

10U_0603_6.3V6M

1

2

CRT@

R48

4.7K_0402_5%

@

R52

4.7K_0402_5%

@

C40

10U_0603_6.3V6M

1

2

2 1

100K_0402_5%

CRT@

C63

1

0.1U_0402_16V4Z

2

CRT@

CRT@

C41

0.1U_0402_16V4Z

1

2

+3VS_CRT

CRT@

R44

1

12K_0402_1%

2

CRT@ CRT @

C45 C46

1 1

0.1U_0402_16V4Z

2

1

2

1

27
26

29
30

31
32

19
24
25
28

11
13
14
16
33

CRT@

C42

C43

1

1U_0402_6.3V6K

0.1U_0402_25V6

2

0.1U_0402_16V4Z

2

CRT@

U4104

5

HPD

AUX_N

DVCC_33

AUX_P
LANE0P

LANE0N

LANE1P
LANE1N

VCCK_12
AVCC_33

AVCC_12

RRX

BLUE_N

GREEN_N
GND_DAC

RED_N

EPAD_GND

RTD2168-CG_QFN32

Part Number = SA000077U00

+3VS_CRT_DVDD

20

9

DVCC_33

VDD_DAC_ 33

1

2 2

VGA_SDA
VGA_SCL

HSYNC
VSYNC

RED_P

GREEN_P

BLUE_P

POL1_S DA
POL2_S CL

SMB_SCL
SMB_SDA

LDO_EN

XI/CKIN

CRT@ CRT @

C47 C48

1

0.1U_0402_16V4Z

6
4

8 HS YNC
7 VS YNC

15 VGA_RE D
12 VGA_ GRN
10 VGA_BLU
22 POL1_SDA

23 POL1_SCL

2 RTD2168_SMB_SCL

3 RTD2168_SMB_SDA

21 LDO_EN_1V2

18 XTALOUT_2168

XO

17 XTALIN_2168

10U_0603_6.3V6M

2.2K_0804_8P4R_5%

CRT_DATA
CRT_CLK

<SI> change to +HDMI_CRT_5V for SVTP test fail

+HDMI_CRT_5V

123

4

CRT@

R38

876

RTD2168_SMB_SCL
RTD2168_SMB_SDA

5

POL1_SDA POL1_SCL

R53 1

2 0_0402_5%

R54 1

2 0_0402_5%

R39 1 @ 2 0_0402_5%
R40 1 @ 2 0_0402_5%

+3VS_CRT +3VS_CRT

@ R42

2

2 1

1

4.7K_0402_5%

CRT@

R45

4.7K_0402_5%

2

@ R46

2 1

1

CRT@

R43

4.7K_0402_5%

4.7K_0402_5%

EC_SMB_ CK2 <7,10,19,26,37>
EC_SMB_ DA2 <7,10,19,26,37>

PCH_SMBC LK <7,17,18,19>
PCH_SMBD ATA <7,17,18,19>

2014-11-24
follow vendor suggest change 36 ohm

HSYNC

1 CRT@ 2

L5 36_0402_1%

VSYNC

1 CRT@ 2

L6 36_0402_1%

Layout notes

L

R61,R62 ,R58,R5 9 cl ose t o RTD2168
R55,R57 ,R60,R5 6 cl ose t o CONN

10P_0402_50V8J

HSYNC_R

VSYNC_R

1 1
CRT@ CRT@

C56 C57

2

<KB L SI> Change ES D d iode pa ckage

D4& D5 Only Pop f or 6U SKU India Country

10P_0402_50V8J

2

50 impedance

|←

VGA_RED

VGA_GRN

VGA_BLU VGA_BL

2 1

2 1

2 1

R49 75_0402_1%

R50 75_0402_1%

R51 75_0402_1%

CRT@ CRT@CR T@

CRT@ SM01000 LU00

L7 1 2 BLM15BA220SN1D0402

CRT@ SM01000 LU00

L8 1 2 BLM15BA220SN1D0402

CRT@ SM01000 LU00

L9 1 2 BLM15BA220SN1D 0402

C66 C67 C68 C69 C70 C71

1 1 1 1 1 1

22P_0402_50V8

22P_0402_50V8

2

2

CRT@ CRT@ C RT@

2

22P_0402_50V8

22P_0402_50V8

2

2

CRT@ CRT@ C RT@

+HDMI_CRT_5V

W=40mil s 1

22P_0402_50V8

22P_0402_50V8

2

+HDMI_CRT_5V

VGA_RE

+HDMI_CRT_5V

VGA_RE

VGA_GR

HSYNC_R 6

C72

0.1U_0201_10V6K

@

2

D4

SC300001G00

3 VSYNC_R

I/O4 I/O2

5

2

VDD

GND

4

1

I/O3 I/O1

AZC099-04S.R7G_SOT23-6

D5

SC300001G00

6

5

4

CRT Connector

CRT_DATA

HSYNC_R

VSYNC_R

CRT_CLK

I/O4

I/O2

VDD

GND

I/O1

I/O3

AZC099-04S.R7G_SOT23-6

→ |

3 VGA_GR

2

1 VGA_BL

CONN@

JCRT1

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

C-K_80454-5K1-152

DC060004S10

6UINDESD @

CRT_DATACRT_CLK

6UINDESD @

G

G

16

17

For Po wer consump tion
Measure ment

+3VS +3VS_CRT

D D

C C

B B

A A

JPHW2

1 2

1 2

JUMP_43X39

JP@

R47
1M_0402_5%

XTALOUT_2168 XTALIN_2168

X1

Cr@ystal

3

OUT GND

2

C64

GND IN

1

18P_0402_50V8J

27MHZ_10PF_X3G027000BA1H-U

2

@

@

4
1

+3VS

<5> DDI2_AUX_DN
<5> DDI2_AUX_DP

<5> PCH_DPC_P0
<5> P CH_DPC_N0

<5> PCH_DPC_P1
<5> P CH_DPC_N1

@

<PV> chang e sh ort pad

R34 1 2 0_0603_5%

CRT@

C58

1

2.2U_0402_6.3V6M

2

C65

18P_0402_50V8J

1

2

CRT@ C49 1
CRT@ C52 1

CRT@C50
CRT@C53 2

CRT@C51
CRT@C54 2

CRT@

C59

1

0.1U_0402_16V4Z

2

+3VS_CRT_DVDD

<5> DDI2_HPD

2

2

+VCCK_1V2

LDO_EN_1V2

2 0.1U_040 2_16V7K DDI2_AUX_DN_C
2 0.1U_040 2_16V7K DDI2_AUX_DP_C

1 0.1U_040 2_16V7K PCH_DPC_P0_C
1 0.1U_040 2_16V7K PCH_DPC_N0_C

1 0.1U_040 2_16V7K PCH_DPC_P1_C
1 0.1U_040 2_16V7K PCH_DPC_N1_C

Securiiittty Clllassifffiiicatiiion

IIIssued Dattte

THIIIS SH EET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPE RTY OF COMPAL ELECTRONIIICS, IIINC... A ND CONTAINS CONFIIIDENTIIIAL AND
TRADE SEC RET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPET ENT DIIIVISION OF R&D
DEPARTME NT EXC EPT A S AUTHORIIIZED BY COMPAL ELECTRONIIICS, IIINC... NEITHER THIIIS SHEET N OR THE IIINFORMATIIION IIIT CONTAINS

5

4

3

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY W IIITHOUT PRIIIOR WRIIITTEN CONSE NT OF COMPAL ELECTRONIIICS, IIINC...

2014/0 2/18

2

Compalll Secret D ata

DecipheredDattte

2015/0 2/20

Compal Electronics,Inc.

Tiiitttllle

DP to CRTRTD2168

Siiize Documenttt Numberrr

Custom

LA-D707P

1

Rev

Sheettt 22 o fff60Dattte::: Wednesday, May 11, 2016

v0.2

5 4 3 2 1

J1

JP@

1

2

1 2

+3VALW

RL35

1 @ 2

0_0201_5%

D D

1 1

CL20 @ CL19

2 2

4.7U_0603_6.3V6K

@giga8111@

CL9 & CL5 close to UL1: Pin 11,32
CL19 close to UL1: Pin 32

1500P_0402_50V7K

+LAN_VDD_3V3

CL9

4.7U_0603_6.3V6K

1

@CL28

2

1

1

CL5

2

2

0.1U_0402_16V7K

JUMP_43X79

@ UG5

5

4

0.1U_0402_16V7K

IN

SS

APL3512_SOT23-5

1

CL10

@

2 2

4.7U_0603_6.3V6K

OUT
GND

EN

+VDDREG

giga8111@

1

CL1

6

CL10& CL16 close to UL1: Pin 23

CL20 close to UL1: Pin 11

C C

SP050005L00Footprint

TSL1 100_8166@

+V_DAC 1

LAN_MDIN3 2

Swap P/N 08/16

2

CL1 CL4

0.01U_0402_16V7K2 0.1U_0402_16V7K

1

B B

11/17 reserver for ESD request

LAN_MDIP3 3

LAN_MDIN2 5
LAN_MDIP2 6

LAN_MDIN1

LAN_MDIP1 RJ45_RX1+

LAN_MDIN0 11
LAN_MDIP0 12

1

@EMI@

2016-03-03:Change SingleSource

LAN_MDIP0 4

LANGND
TCT1 MCT1
TD1+ MX1+
TD1- MX1-

4 21

TCT2 MCT2

20 RJ45_TX2-

TD2+ MX2+

TD2- MX2-

7 18

TCT3 MCT3

8

TD3+ MX3+

9

TD3- MX3-

10 15

TCT4 MCT4

14 RJ45_TX0-

TD4+ MX4+

13 RJ45_TX0+

TD4- MX4-

CAP_LAN-8700GS

SP050008V00

(SP050008V00)10/100
(SP050008Y00) Giga

@ESD@

DM12

4

powe rail need to check

+LAN_VDD_3V3

5

Vbus

GND

+LAN_VDD_3V3 Rising time

need>0.5mS and <100mS

1
2
3

1

@CL29

0.1U_0402_16V7K

2

0.1U_0402_16V7

K

<9> LAN_CLKREQ#

<9,26,28,32,36> PLT_RST# EC_PME# <26>

<9> CLK_PCIE_LAN
<9> CLK_PCIE_LAN#

<11> PCIE_PTX_C_DRX_P5
<11> PCIE_PTX_C_DRX_N5

<11> PCIE_PRX_DTX_P5
<11> PCIE_PRX_DTX_N5

XGND RL55 1 Rshort@20_0805_5%

25

24
23 RJ45_TX3- RP5

RJ45_TX3+

22

19 RJ45_TX2+

RJ45_RX1-

17

16

TSL1
S X'FORM_ LAN-8100G1G

SP050008Y00

3 LAN_MDIN0

3

+LAN_VDD_3V3

2 RL6Rsho1rt@0_0201_5%

PLT_RST#

CLK_PCIE_LAN
CLK_PCIE_LAN#

PCIE_PTX_C_DRX_P5
PCIE_PTX_C_DRX_N5

PCIE_PRX_DTX_P5 CR11 1 2 0.1U_0402_10V7K PCIE_PRX_C_DTX_P5 17

PCIE_PRX_DTX_N5 CR13 1 2 0.1U_0402_10V7K PCIE_PRX_C_DTX_N5 18

2.49K_0402_1%

128

7

346

5

75_0804_8P4R_1%

SD300002E80

DL1 ESD@

giga8111@ SCA00000U10

3

LAN_MDIP2

2

CL2

SE167100J80

10P_1808_3KV

1

1

LANGND

@ESD@

DM13

4

4

CL3 EMI@
120P_0402_50V8J

2

3

2

YSLC05CH_SOT23-3

1

+LAN_REGOUT

8151/8166 Co-Lay

LAN_MDIN0
LAN_MDIP1
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2
LAN_MDIP3

MDIP3

LAN_MDIN310

LAN_CLKREQ#_RLAN_CLKREQ#

RL11

3 LAN_MDIN2

2

1

12
19

15
16

13
14

HSOP

RSET 31

8/15 Change to LDO Mode

2.2UH +-5%NLC252018T-2R2J-N

1

@

CL21

2

0.1U_0402_16V7K

UL1

giga8111@

RTL8151GH

100_8166@

UL1

MDIP0

2

MDIN0

4

MDIP1

5

MDIN1

6

MDIP2

7

MDIN2

9

MDIN3

CLKREQB
PERSTB

REFCLK_P

REFCLK_N

HSIP
HSIN

HSON
RSET

SA000063500

(SA000063500) 8166GSH 10/100
(SA000084T00) 8111HSH-CG Giga

SA000084T00

RTL8111G

VDDREG(VDD33)

@

LL1 1

2 0_0603_5%

LL2

1

2

giga8111@

CL8

giga8111@

LL2, CL8, CL23 for 8161
CL8 & CL18 close LL2

+LAN_VDD_1V0

3LAN_MDIP0 1

AVDD10

8

AVDD10

30

AVDD10

22

DVDD10

11

AVDD33

32

AVDD33

REGOUT

LANWAKEB

ISOLATEB

LED1/GPO

LED2(LED1)

CKXTAL1
CKXTAL2

+VDDREG

23

24 +LAN_REGOUT

21 EC_PME#

20 EC_LAN_ISOLATEB#_R

27 LAN_ACT#

LED0

26

LED1/GPO

25 LAN_LINK#
28 XTLI

29 XTLO

33

GND

1

1

K CL23

2

2

4.7U_0603_6.3V6

giga8111@

+LAN_VDD_3V3

powe rail need to check

2

+LAN_VDD_3V3

5

Vbus

GND

2

LDO mode Switcing mode
LL1 SMT
CL21 SMT
LL2 @
CL8,CL23@

1

1

CL11

2

0.1U_0402_16V7K

CL13

CL12

2

0.1U_0402_16V7K

0.1U_0402_16V7K

Place CL11~CL12 close UL1 Pin 3,8

+LAN_VDD_3V3=40mil
+VDDREG=40mil

L

+LAN_REGOUT=60mil

+LAN_VDD_3V3

+LAN_VDD_3V3

RL10

1 2

0_0603_5%

2

EC control 08/17 Add 0ohm

TH1

LAN_ACT# LAN_ACT#_R

1

@

2

LAN_LINK# 2

1

@

2

@

@
SMT
SMT

1

2

RL15
10K_0402_5%

1

0.1U_0402_16V7K

CL14

giga8111@

+LAN_VDD_1V0

1

@

CL15

2

0.1U_0402_16V7K

CL13 & CL15 close UL1 Pin22

CL14 & CL27 close UL1Pin30

1U_0402_6.3V6K

1

1

2

@

CL26

CL27

2

0.1U_0402_16V7K

EC_LAN_ISOLATEB#_R 2 1

1M_0402_5%

2

10P_0402_50V8J

CL25

1

11/18 modify vendor review results

11/15 change CONN.

2

510_0402_5%

RL31

CL35

68P_0402_50V8J

RL30

CL34

68P_0402_50V8J

1

1

510_0402_5%

+LAN_VDD_3V3

LAN_LINK#_R

RJ45_TX3­RJ45_TX3+
RJ45_RX1­RJ45_TX2­RJ45_TX2+
RJ45_RX1+ 3
RJ45_TX0- 2
RJ45_TX0+

JLAN1

10

A2_AmberLED+

9

A1_AmberLED-

8

TX3-

7

TX3+

6

RX1-

5

TX2-

4

TX2+

RX1+

TX0-

1

TX0+

11

B2_WhiteLED+

12

B1_WhiteLED-

CONN@

1U_0402_6.3V6K

1

2

10P_0402_50V8J

2

CL24

1

LANGND

+3VS

XTLI

1K_0402_5% RM6

RM11
15K_0402_5%

1 2

0923 PV CNG from DP00 toE500

2

1 XTLO

RL7

1

3

YL1

GND OSC

GND OSC

2

4

25MHZ 10PF 5YEA25000102IF50Q3

SJ10000E500

13

GND1

14

GND2

LAN_MDIP3

LAN_MDIP1 6

A A

5 4 3 2 1

6

YSUSB2.0-5_SOT-23-6-6

SC300001400

1 LAN_MDIN1

1

6

6

YSUSB2.0-5_SOT-23-6-6

SC300001400

1 LAN_MDIN3

1

CR RTS5237S move to S/B

Securiiity Clllassifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2013/02/26 2015/07/08

Compal SecretData

Deciphered Date

Tiiitttllle

Siiize Documenttt Number

Dattte::: W ednesday, May 11, 2016 Sheettt 23 o fff60

Compal Electronics, Inc.

LAN 8151/8166_ CR RTS5238

LA-D707P

Rev

v0.2

5 4 3

HDA_RST_AUDIO#

1K_0402_5%
RA26

10K_0402_5%
RA11

+3VS
+1.8VS
+5VS

UA1

20

MIC1_R

19

MIC1_L

18

MIC2_R

17

MIC2_L

31

MIC1_VREFO_L

30

MIC1_VREFO_R

29

MIC2_VREFO

23

LINE2_R

24

LINE2_L

16

PC_BEEP

ALDO_CAP
ACPVEE

CPVDD
CBN
CBP

MONO_OUT

12

PCBEEP

10

SYNC

11

RESET#

7

LDO3-CAP

34

CPVEE

36

CPVDD

35

CBN

37

CBP

2

GPIO0/DMIC_DATA

3

GPIO1/DMIC_CLK LDO1_CAP

13

SENSE_A

14

SENSE_B

47

PDB Thermal Pad

ALC3227-CG_MQFN48P_6X6

Power down (PD#) power stage for save power
0V: Power down powerstage

3.3V: Power up power stage

DVDD_IO

SPK_OUT_R+
SPK_OUT_R-

SPK_OUT_L+

SPK_OUT_L-

HPOUT_R
HPOUT_L

SDATA_OUT

SDATA_IN

LINE1_R

SPDIFO/GPIO2

LDO2_CAP

1

DVDD

9
26

AVDD1

40

AVDD2

41

PVDD1

46

PVDD2

45 SPK_R+
44 SPK_R-

42 SPK_L+
43 SPK_L-

33 HPOUT_R RA4 1 2 30_0402_1% HP_OUT R
32 HPOUT_L RA5

5

SDATA_IN RA7 1 2 22_0402_5%

8

6

BCLK

22

LINE1_L

21

48 MIC_JD

15 JDREF RA9 2 1 20K_0402_1%

JDREF

28 AVREF CA16 2 1 .1U_0402_16V7K

VREF

27

39
25

AVSS1

38

AVSS2

4

DVSS

49

+DVDD
+DVDD_IO

+5VS_AVDD
+1.8VS_AVDD

+5VS_PVDD

Internal Speaker

1 2 30_0402_1% HP_OUTL

CA18 1 2 10U_0603_6.3V6M
CA19 1 2 10U_0603_6.3V6M

2 RA29 1 100K_0402_5%

add 100 k from v endor suggest
20141120

AVREFCA24 12 2.2U_0402_6.3V6M

GNDA

L

change 30 ohm f rom vendo r sugges t
20141120

GNDA

Headphone

HDA_SDOUT_AUDIO <8>
HDA_SDIN0 <8>

HDA_BITCLK_AUDIO <8>

GNDA

Reserve for ESD request.

INT_MIC_R

<5,6,7,9,10,11,13,17,18,19,20,21,22,23,26,28,32,33,34,35, 36,37,38,52,55,56> +3VS

<20,21,26,27,30,34,35,52,53,56> +5VS

D D

INT_MIC RA3 1 2 1K_0402_5%

<26> MUTE_LED_IN

11/24 modify mute LED that controled by EC

+3VS

2

CA17

4.7U_0603_6.3V6K

1

C C

<8> HDA_SYNC_AUDIO
<8> HDA_RST_AUDIO#

CPVDD

<20> D_MIC_DATA
<20> D_MIC_CLK

<SI> QA2 change from NMOS to BJT

<PV> QA2 change to QA1.

<26> EC_MUTE#

1 @ 2

+3VS

RA6

4.7K_0402_5%

HDA_RST_AUDIO# 3 1

Part Number = SB000008E10 @

<12> +1.8VS

CA1 1 2 4.7U_0402_6.3V6M INT_MICR_C
CA4 1 2 4.7U_0402_6.3V6M INT_MICL_C

10K_0402_5%

RA30

2

CA11 1 2 10U_0603_6.3V6M
CA14 1 2 2.2U_0402_6.3V6M

CA15 1 2 2.2U_0402_6.3V6M

PLUG_IN#

RA10 1 2 39.2K_0402_1% SENSEA

+1.8VS +DVDD

1

@

RA25

2.2K_0402_5%

B

2 2

E

C

QA1
MMBT3904WH_SOT323-3

1 2

DA3
CH751H-40PT_SOD323-2

@SCS00003500

+MIC2_VREFO

1

PD#

1

2

1

2

PC Beep

EC Beep

B B

SB Beep

<26> EC_BEEP#

<8,10> HDA_SPKR

L

Layout notes
Close chipPin12

1 2 PC_BEEP_R CA31

.1U_0402_16V7K RA19

1 2 1 2

CA33
.1U_0402_16V7K

47K_0402_5%

1

RA20
10K_0402_5%

2

1 2 PC_BEEP CA34

.1U_0402_16V7K

<PV> change short pad

+3VS +DVDD

RA21 Rshort@ 2 0_0603_5%

Layoutnotes
CA5 CA6 close Pin1
CA7 CA8 close Pin9
CA9 CA10 close Pin26
CA12 CA13 closePin40

<PV> change short pad

+5VS_AVDD

+5VS_PVDD

<PV> change short pad

RA13 1 Rshort@ 2 0_0603_5%

SPK_R-

RA14 1 Rshort@ 2 0_0603_5%

SPK_R+

RA15 1 Rshort@ 2 0_0603_5%

SPK_L-

RA16 1 Rshort@ 2 0_0603_5%

SPK_L+

HP_OUTR_R HP_OUTL_R

GNDA

2

3

DA4
YSLC05CH_SOT23-3

SCA00002900
ESD@

1

.1U_0402_16V7K

GNDA

.1U_0402_16V7K

2

LA4 1 Rshort@ 2 0_0603_5%

CA10

4.7U_0603_6.3V6K

CA9

2

1

1

2

CA22

10U_0603_6.3V6M

CA21

.1U_0402_16V7K

CA20

1

1

2 1

2

2

3

1

2

1

DA6
YSLC05CH_SOT23-3

SCA00000U10
@ESD@

+DVDD_IO

CA7

CA5

.1U_0402_16V7K

10U_0603_6.3V6

M

1 1

2

Need to check 20141110

LA6 SM01000NS00

1 2

TAI-TECH HCB2012VF-601T200805

CA23

10U_0603_6.3V6M

2

.1U_0402_16V7K

CA6

2

1

2

+5VS

+5VS

2

Internal SPK

wide 40 MIL

+1.8VS +3VS

1 @ 2

LA3

CA8

10U_0603_6.3V6

M

SUPPRE_ KC FBMA-10-100505-101T 0402

PCB Footprint =R_0402

1

1 2

LA7 0_0402_5%

2

<7/1>LA3/LA4/LA5/LA6 change to 0-ohm.

<9/1>LA3/LA4/LA5/LA6 change to 0-ohm short-pad

+1.8VS_AVDD +1.8VS

LA5 1 2 0_0402_5%

CA13

4.7U_0603_6.3V6K

CA12

.1U_0402_16V7K

1

2

2

1

GNDA

3

DA8
YSLC05CH_SOT23-3

SCA00002900

1

SPK_R-_CONN
SPK_R+_CONN
SPK_L-_CONN
SPK_L+_CONN

1

2

220P_0402_50V7K

Jack detect
Combo Mic = High
Normal HP = Low

MIC_JD INT_MIC

1

<DB> Change PWR Rail

<DB> Change PWR Rail

PCB Footprint = ACES_50278-00401-001_4P

<DB> change foorprint

1

1

2

2

220P_0402_50V7

K

220P_0402_50V7

K

@EMI@ C123

@EMI@ C124

@EMI@ C125

+MIC2_VREFO

1 2

RA18

CA32

10U_0603_6.3V6

M

22K_0402_5%

2

1

GNDA

Need to check 20141110

1
2
3
4

1

2

220P_0402_50V7

K

@EMI@ C126

1

RA17

2.2K_0402_5%

2

JSPK1

1
2

5

3 GND

6

4 GND

E-T_3703K-F04N-03R

CONN@

SP02000H310

COMBO AUDIO JACK

CONN@

GNDA

3
1

5
6

2
4
7

JHP

GND

YUQIU_PJ750-F07J1BE-A

DC2301411240

Rev

v0.2

RA27 1 2 0_0402_5%

RA28 1 2 0_0402_5%

1 2

CA40 @EMI@

.1U_0402_16V7K

1 2

CA38 @EMI@

.1U_0402_16V7K

A A

1 2

CA39 @EMI@

.1U_0402_16V7K

1 2

CA29 EMI@

.1U_0402_16V7K

1 2

CA30 EMI@

.1U_0402_16V7K

GNDA

5 4 3 2 1

INT_MIC
HP_OUTL

HP_OUTR

Securiiity Clllassifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

RA24

22K_0402_5%

RA21 1 2 0_0402_5%
RA22 1 2 0_0402_5%

RA23 1 2 0_0402_5%

2

1

100P_0402_50V8

J

2013/01/04 2015/01/04

HPR, HPL, 15mil Keep 30mil

CA37

10P_0402_50V8

J

CA36

10P_0402_50V8JCA35

1

1

1

2

2

2

@EMI@

@EMI@

@EMI@

GNDA GNDA GNDAGNDA

Compal SecretData

Deciphered Date

INT_MIC_R
HP_OUTL_R

PLUG_IN#

HP_OUTR_R

Pin6 an d Pin5
Normal OPE N

Tiiitttllle

Siiize Documenttt Number

C

Dattte::: W ednesday, May 11, 2016 Sheettt 24 o fff60

Compal Electronics,Inc.

AUDIO ALC3227-CG
LA-D707P

5

,9,10,11,13,17,18,19,20,21,22, 23,24 ,2 8,3 2,3 3, 34, 35, 36 ,3 7,3 8,52, 55, 56> + 3VS

ESD@

D D

<SI> un-mount RC , Internal PU in 9022

+3VA LW _EC

C C

<47> VC IN1_ ACO K

For Sol ve t PCH0 4(M in 9ms) Sequ enc e Timing

<DB> for le aka ge of LED lig ht

+5VS

B B

2

RK19 100K_ 0402 _5%

A A

CK4

2 1 PLT _RST#

0.1U_04 02_16V7 K

@

2

RK7

2

@ 1

0.1U_04 02_16V7 K

CK5

VCIN 1_AC _IN 1 @

<7,10,1 9,22 ,37 > E C_SMB_C K2
<7,10,1 9,22 ,37 > E C_SMB_D A2

RK28

1 MUT E_LED_O UT2

100K_0 402_ 5%

RK26

1 E51T XD_ P80D AT A

100K_0 402_ 5%

1 @ 2 PC H_DPWR OK
1 @ 2 P CH_PWR OK RK20

100K_0 402_ 5%

1 330 K_04 02_5% EC_RST#

R4958

R5094 0_0402 _5%

R4960

<45> + 3VAL W_ EC

<13,33, 46,4 7,4 8> + 3VL

@

2 VCIN 1_AC OK_R

1

0_0402_5%

1 2 V CIN1 _AC_ IN_R

2 VCIN 1_AC _IN_ R

0_0402_5%

<46,47> EC_S MB_C K1
<46,47> EC_S MB_D A1

2014-11-13:
Pin16 from MINI1_LED# to PM_SLP_SUS#
Pin29 from PM_SLP_SUS#remove
Pin25 from EC_INVT_PWMremove
Pin19 from EC_+1.05VS_PG to GPU_HOT#
Pin21 from GPU_HOT# toEC_+1.05VS_PG
Pin25 from EC_INVT_PWMremove
Pin122 from GPU_THERMAL_DET# to PBTN_OUT#
Pin123 from X to PM_SLP_S4#
Pin18 remove
Pin36 remove no support USB CHR

10K_04 02_5 %

NMI_DBG#

+3VA LW _EC

RK21

1

2

<5,10> EC_SCI#

<7> PM_CLKR UN#

<9,32> EC_P CIE_ WA KE#

<9,12,3 5> PM_ SLP _S3 #

1 2

DK2 SCS0000 3500

CH751H-40PT_ SOD323-2

+3VS

+3VA LW _EC

+3VL

<20> T OUC H_O N#

<7,28> LPC_FR AME#

<7> CLK_PCI_ LPC

<9,23,2 8,32 ,36 > PLT _RS T#

<27> KSI[0 ..7]

<27> KS O[0 ..17 ]

RK15 1
RK16 1

<9> PM_SLP_ S5 #

<9> SUSA CK#

<9,13> PM_S LP_ SUS #

<9> PCH_ SUSWAR N#

<27> W LAN_ON _LE D#

<37,56> GPU _PRO CHO T#

<24> MUTE_LED _IN

<34> F AN_SPEED 1

<32> E51TX D_P8 0DA TA

<32> E 51RX D_P 80C LK

<9> PCH_P WR OK

<27> MUTE_ LED_OUT

<9,12,3 5,49 > PM_SLP _S4#

<7> EC_K BRST #

<7,28> SER IRQ

<7,28> LPC _AD3
<7,28> LPC _AD2
<7,28> LPC _AD1
<7,28> LP C_AD0

<45> A C_LE D#

<9> PBTN_ OUT #

4

+3VL

<PV> change short pad

2

1

0_0603_5%

RK1

TOUCH_ ON#
EC_K BRST#
SERI RQ
LPC_ FRA ME#
LPC_AD3
LPC_ AD2
LPC_AD1
LPC_ AD0

CLK_PCI_LPC
PLT _RST #

PM_SLP_S 3#
PM_SLP_ S5#

SUSA CK#
PM_SLP_ SUS#
PCH_SUSWARN#

EC_R ST#

EC_S MB_C K2_ R
EC_S MB_D A2_ R

WL AN_O N_L ED#

FAN_SPEED1
VCIN 1_AC OK_R
E51T XD_ P80DAT A
E51R XD_ P80CLK
PCH_PW ROK

AC_L ED#

PBT N_OUT#
PM_SLP_ S4#

EC_S CI#

1 @ 2 P M_CL KRUN#_R

RK10 1 2 0_0402_5%
RK6 0_0402_5%

2 0_0402_5 %
2 0_0402_5 %

NMI_DBG# _CPU < 5,10>

1

2

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

0.1U_04 02_16V7 K

+3VA LW _EC

0.1U_04 02_16V7 K

CK1

1

2

KB90 22Q D_L QFP 128_1 4X1 4

+3VA LW _EC

CK2

UK1

1

GAT EA20/GP IO00

2

KBRS T#/ GPIO 01

3

SERI RQ

4

LPC_ FRA ME#

5

LPC_ AD3

7

LPC_ AD2

8

LPC_ADL1

10

PC & MISC

LPC_ AD0

12

CLK_ PCI_ EC

13

PCIR ST# /GPIO05

37

EC_R ST#

20

EC_S CI#/ GPIO 0E

38

CLKR UN# /GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GP IO20

40

KSO1/GP IO21

41

KSO2/GP IO22

42

KSO3/GP IO23

43

KSO4/GP IO24

44

KSO5/GP IO25

45

KSO6/GP IO26

46

KSO7/GP IO27

47

KSO8/GP IO28

48

KSO9/GP IO29

49

KSO10/G PIO 2A

50

KSO11/G PIO 2B

51

KSO12/G PIO 2C

52

KSO13/G PIO 2D

53

KSO14/G PIO 2E

54

KSO15/G PIO2 F

81

KSO16/G PIO4 8

82

KSO17/G PIO4 9

77

EC_S MB_C LK1 /GPIO 44

78

EC_S MB_D AT1/G PIO 45

79

EC_S MB_C LK2 /G PIO 46

80

EC_S MB_D AT2/G PIO 47

6

PM_SLP_S 3#/G PIO04

14

GPIO 07

15

GPIO 08

16

GPIO 0A

17

GPIO 0B

18

GPIO 0C

19

AC_P RESENT/GPIO0D

25

PW M2/G PIO1 1

28

FAN_SPEED1/GPIO1 4

29

FANFB1/ GPIO 15

30

EC_T X/GPIO 16

31

EC_R X/G PIO17

32

PCH_PW ROK /GPIO18

34

SUSP _LED #/GPI O19

36

NUM_ LED# /GP IO1A

122

PBT N_OUT# /GPIO5D

123

PM_SLP_ S4# /GP IO5E V18 R/VCC_IO2

LK1
S S UPPR E_ T AI-TECH HCB1005 KF-221T15 0402

1 2 + EC_VCCA

9223396111

VCC

VCC

VCC

VCC0

VCC_LPC

PWM Output

ADInput

DA Output

PS2Interface

Int. K/B
Matrix

SPI Device Interface

SPI Flash ROM

GPIO

SM Bus

VCIN 1_AD P_PROC HOT /GPXIO A0 5

VCOUT0 _MAIN _PW R_ ON/GPXIOA 07

GPIOGPO

GND

GND

GND

GND

112435

94

3

1

CK3

0.1U_04 02_16V7K

2

ECAGND

+3V_ EC_ VDD

1 RK3 2

0_0402_5%

125

67

VCC

AVCC

EC_V CCST_PG/GPIO 0F

BEEP #/GPIO10

EC_F AN_ PWM/GPIO12

AC_O FF/GPIO13

VCIN 1_BA TT _TE MP/AD0/G PIO38

VCIN 1_BA TT _DROP/A D1/GPIO 39

ADP_ I/AD 2/G PIO3 A

AD_B ID/A D3/GPIO 3B

AD4/ GPIO42
AD5/ GPIO43

DA0/ GPIO3C

EN_D FAN 1/DA1/G PIO 3D

DA2/ GPIO3E
DA3/GPI O3F

EC_M UTE #/PS CLK1/GPIO4A

USB_ EN#/PSD AT1 /GPIO4B

PSCL K2/GPIO4C
PSDA T2/ GPIO 4D

TP_ CLK/ GPIO4E

TP_ DAT A/GPIO4 F

ENKB L/G PXIOA0 0

WO L_EN/GP XIOA 01

ME_EN/GP XIO A0 2

VCIN 0_PH 1/G PXIO D00

MISO/GPIO5B
MOSI/GPIO5C

SPIC LK/G PIO5 8

SPIC S#/G PIO5 A

EC_C IR_RX/AD6/G PIO40

SYS_ PW ROK/AD7 /GP IO4 1

BAT T_C HG_ LED# /GP IO5 2

BAT T_L OW _LED#/G PIO5 5

EC_R SMRS T#/ GPX IOA03

VCOUT1 _PRO CHO T#/GPX IOA06

PCH_PW R_EN/GP XIOA 10

PW R_VC CST _PG /GPXIOA 11

VCIN 1_AC _IN/ GPX IOD0 1

GPI

GND

AGND

69

113

GPIO 50

CAPS _LED #/G PIO5 3

PW R_LE D#/GPIO 54

SYSO N/G PIO56
VR_O N/G PIO57

DPW ROK _EC/ GPIO 59

GPXIOA04

BKOFF#/ GPX IOA 08

GPXIOA0 9

EC_O N/G PXIO D02
ON/ OFF #/GPXIOD03
LID_ SW#/GPXIOD 04

SUSP #/G PXIO D0 5

GPXIOD06

PECI /GPX IOD07

20mil

LK2

ECAG ND 2 1

TAI-TE CH HCB1 005KF- 221T 15 0402

ECAG ND <45>

+3VA LW _EC

2

RK2
100K_0 402_ 1%

1

BOARD_ID

2

UMA@

PX@

+3VL

56K +-1%0402

SD03 456 0280

EC_V CCST_PG_R

21

23

26 E C_F AN_P WM1

EC_C LR_ CMOS

27

63 B/I#
64 VG A_AC _BAT T
65 ADP_I

66 BOARD _ID

75 ADP_ID

76

EC_P ME#_EC_ R R5178 1 2 0_0201_ 5%

68

NMI_DBG#

70

VR_P WR GD

71

EC_M UTE #

72

EC_S MB_C K3

83

EC_S MB_D A3

84

VR_O N

85

WL AN_O FF_ LED#

86

TP_ CLK

87

TP_ DAT A

88

97 ENBKL

98

ME_F las h_EN

99

VCIN 0_PH

109

119

120

126

128

73

74

89

90
91
92

93

95 SYSO N

121

127

100

101 US B_ON#

102 VC IN1_PH

103

104 MA INPW ON

105 EC_BKO FF#

106

107 PC H_P WR _EN

108 +1 .0V_ VS_ PG_ PW R

110 VCIN1_AC_ IN_R

112 EC _ON

114 O N/OFF#
115 LID_SW #
116 SUSP #

117 VCIN1_AC_IN

118 E C_PECI RK17 1

124

EC_S PI_C LK

SYS_ PW ROK
EC_S 0IX_EN
BAT _CHG_LE D

CAP_ LOC K#
PW R_LE D#
ACIN

BT_ ON_ EC
PCH_DPW RO K

PCH_RSMR ST#

H_PR OCH OT# _EC

RK25 1 2 0_0402_5%

+V18 R

1

2

RK4

1

CK8

4.7U_06 03_6.3V6 K

RK4

43K +-1%0402

SD03 443 0280

EC_V CCST_PG_R <9,35>

EC_B EEP # <24>

EC_F AN_ PWM1 <34>

ME_F las h_EN <8>

VCIN 0_PH <45>

TS_ GPIO _EC <20>

PCH_RSMR ST# <9>

EC_O N <4 8>
ON/ OFF # <33>
LID_ SW# <3 3>

SUSP # <12 ,13, 35, 49>

24 3_040 2_1%

2 1

EC Board ID (UMA, Dis, phase) control table

RK4

UMA
Dis 20Kohm 33Kohm 56Kohm 100Kohm

DB_UMA_15kohm:SD034150280, S RES 1/16W 15K +-1% 0402
DB_DIS_20kohm:SD034200280, S RES 1/16W 20K +-1%0402

SI_UMA_27kohm:SD034270280, S RES 1/16W 27K +-1% 040 2
SI_DIS_33kohm:SD0343302 80, S RES 1/16W 33K +-1%0402

PV_UMA_43kohm:SD034430280, S RES 116W 43K +-1% 0402
PV_DIS_56kohm:SD034560280, S RES 1/16W 56K +-1% 0402

MV_UMA_75kohm:SD034750280, S RES 1/16W 75K +-1% 0402
MV_DIS_100kohm:SD034100380, S RES 1/16W 100K +-1%0402

Board ID control

2014-11-13:
Pin64 from BOARD_ID to X no support KBL
Pin66 from X toBOARD_ID
Pin76 Pin97swap
Pin84 from PM_SLP_S4# toUSB_ON#
Pin68 from +1.05V_VS_PG_PWR to MINI1_LED#
Pin70 NC , nosupport
Pin72 NC , no support

B/I# <46>
VGA_AC_ BAT T <37 >
ADP_ I < 45,47>

MINI1 _LED # <32>

VR_P WR GD <52 >
EC_M UTE # <24 >

EC_S MB_C K3 <37>
EC_S MB_D A3 <37>
VR_O N < 35,52>

ENBK L <5>

EC_S PI_SO < 7>
EC_S PI_S I <7>

EC_S PI_C S0# <7 >

PW R_LE D# < 33>

ACIN <9,37>

SYSO N < 12, 35,4 9>
BT_ ON_ EC < 32>
PCH_DPW RO K <9>

USB_ ON# <31, 33>
VCIN 1_PH <45>

MAINP WO N < 48>
EC_B KOF F# <19>

+1.0V_VS_PG _P WR < 50>

+3VA LW _EC

Pin86 NC , no suppout

WL _PW REN _EC <30 >

SYS_ PW ROK <9 >

EC_S 0IX_EN <12>
BAT _CHG_LE D <45>
CAP_ LOC K# < 27>

DGPU_PW R_EN < 10,3 8,55,56 >

PCH_PW R_EN <13, 35,5 1>

H_PE CI < 5>

DB

SI PV

15Kohm 27Kohm 43Kohm 75Kohm

Current

EC_C LR_ CMOS

ADP_ ID <45>

EC_P ME# <23>

WL AN_O FF_ LED# <27>

TP_ CLK < 27>
TP_ DAT A <27>

2014-11-13:

Pin108 from USB_ON# to +1.05V_VS_PG_PWR

Pin106 NC , no support
2014-11-18
Pin108 from +1.05V_VS_PG_PWR to VGA_AC_BATT
2014-11-24

Pin108 from VGA_AC_BATT to 1.05V_VS_PG_PWR

2014-11-25
Reserve for co-lay N uvoton NPCE388N

<52> VR _HO T#

EC_S PI_C LK RC369 1 2 PCH_SP I_CLK_R

CC128 RC369 place near EC Side

MV

Reserve EC_CLR_CMOS for clear CMOS

(2016 -03-04 : Confirm intel platform not support E C
Clear CM OS function)

RK10 6 1 2 0_0402_5%

R483

@

10K_04 02_5 %

1

2

<SI> EC request to add RK9

VR_H OT # 1 2 0_040 2_5%

H_PR OCH OT# _EC 2

TP_ CLK

TP_ DAT A

RP12

PCH_PW R_EN 8
PLT _RST # 7
EC_O N 6

100K_0 804_ 8P4R _5%

PBT N_OUT# R2 95 1 @ 2 1K_040 2_5%

EC_C LR_ CMOS 1 @ 2

LID_ SW#

EC_S MB_C K1
EC_S MB_D A1
EC_S MB_C K2
EC_S MB_D A2

EC_S CI# 10 K_04 02_5% 2 @ 1 RK14

SYSO N

SUSP #

EMI@ 15_04 02_5 %

EMI request

Note

@

5

RK10 7 10 K_0402 _5%

@

1

D

2

Q51

G

2N7002 K_SOT 23-3

S

3

RK8

D

1

G

@QK1

2N7002 _SOT23-3

RK13 1 2 4.7K_ 0402 _5%

22P_04 02_5 0V8J

S

3

RK91 2 0_0402_5%

2

1
2
3
4

1 47K_040 2_5%RK18 2

8
7
6 3
5 4

2.2K_0804_ 8P4R _5%

RK23 100K_ 0402 _5%

1 @ 2

RK27 100K_ 0402 _5%

1 @ 2

CC144

@EMI@

CLR_CMO S# <9 >

4.7K_0402_ 5%RK12 1

+3VA LW _EC

1 RP11
2

PCH_SPI_ CLK_R < 7>

PROCHOT# <5 >

+3VA LW

+3VL

+3VS

Security Classification

Issued Date

THIIIS SHEET OF ENGINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS, IIINC... AND CONTAINS CONFIIIDENTIIIAL
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS, IIINC... NEITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAINS

5

4

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS, IIINC...

3 2

2011/06/29 2011/06/29

Compal SecretData

DecipheredDate

Compal Electronics,Inc.

Tiiitllle

ECENE-KB9022

Siiize Document Number

Custom

LA-D707P

Re v

v0.2

1

60Date: W ed nes day, May 11, 2016 Sheet 26 o f

TP Button BD Connector

<7,13,20,23,26,30,33,35,48,49,50,51,55> +3VALW

<12,13,20,30,31,33,35,38,48,49> +5VALW

+3VALW
+5VALW

<26> TP_CLK
<26> TP_DATA

<7> TP_SMBCLK
<7> TP_SMBDATA

PS2+SMBus

YSLC05CH_SOT23-3

DM5

SCA00000U10

ESD@

+3VALW

2

3

1

2

470P_0402_50V8J

1

@

C135

1

C136

2

470P_0402_50V8J

<SI> add 470p for EMI issue

@

+5VALW +5VALW

CONN@

JTP1

1

1

2

2

3

3

4

4

5

5

6

6

7

G1

8

G2

JXT_FP202DH-006M10M

SP01001YK00

1

@EMI@

C134
470P_0402_50V8J

2

2014-11-24
BOM control

Amber

1

R157

3.3K_0402_5%

2

1

White

R158

3.3K_0402_5%

2

<26> KSI[0..7]

<26> KSO[0..17]

<26> CAP_LOCK#

<26> MUTE_LED_OUT

1

CC122 CC123

100P_0402_50V8J 2 100P_0402_50V8J

2

ESD@ ESD@

1

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1

KSI0

KSO17
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10

KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1

KSO0

CAP_LOCK#

WLAN_OFF_LED#
WLAN_ON_LED#

CAP_LOCK#
MUTE_LED_OUT

R203 1
R207 1

Keyboard conn

KSI1
KSI7

KSI6
KSO9

KSI4
KSI5

KSO0
KSI2

KSI3
KSO5

KSO1
KSI0

KSO2
KSO4

KSO7
KSO8

KSO6
KSO3

KSO12
KSO13

KSO14
KSO11

KSO10
KSO15

KSO16

+5VS

+5VS

KSO17

2 3.3K_0402_5%
2 3.3K_0402_5%

JKB1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32 G2

G1

32

ACES_50690-0320N-P01

CONN@ SP01001RG00

33

34

<26> WLAN_OFF_LED# WLAN_ON_LED#<26>

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/02/26 2015/07/08

DecipheredDate

Compal Secret Data

KSI0

ESD@

C193 2 1 100P_0402_50V8J

Title

Size Document Number

B

Date:

Wednesday, May 11, 2016 Sheet 27 of 60

Compal Electronics, Inc.

KB/TP

LA-D707P

Rev

v0.2

5 4 3 2 1

H3

H_2P8

HOLEA

1

H10

H_5P0

HOLEA

1

+3VS

+3VS<5,6,7,9,10,11,13,17,18,19,20,21,22,23,24,26,32,33,34,35,36,37,38,52,55,56>

D D

TPM2.0

+3VS

R26 1 TPM@2 0_0402_5%

1

@

C34

C C

<7,26> LPC_AD0
<7,26> LPC_AD1
<7,26> LPC_AD2

<7,26> LPC_AD3

<7,26> LPC_FRAME#

<9,23,26,32,36> PLT_RST#

<7,26> SERIRQ

<7> CLK_PCI_TPM

+3VS_TPM

R27

B B

1 @ 2

4.7K_0402_5%

R29 1

TPM@

1

R31

4.7K_0402_5%

2

@ 2 4.7K_0402_5% 6

0.1U_0402_16V4Z

@

U4

26

LAD0

23

LAD1
LAD2

17

LAD3

22

LFRAME#

16

LRESET#

27

SERIRQ

21

LCLK
GPIO

7

PP

4

11

GND

18

GND

25

GND
GND

SLB9665TT2.0-FW-5.00_TSSOP28

VDD
VDD
VDD
VDD

2

5
10
1920
24

1

NC

2

NC

3
8

NC

9

NC

12

NC

13

NC

14

NC

15

NC

28

NC
NC

+3VS_TPM

0.1U_0402_16V4Z

R28 2

0_0402_5%

TPM@

C35

TPM@1

0.1U_0402_16V4Z

@

1

C36

2

PLT_RST#

1

2

@

1

C37

2

0.1U_0402_16V4Z

H4

H_2P5

HOLEA

@

1

H15

H_5P0

HOLEA

@

1

H19 H8

H_2P4X3P0N H_2P4N

HOLEA HOLEA

@

Screw Hole

H2

H1

H_2P5

H_2P5

HOLEA

HOLEA

@

@

1

H16

H_5P0

HOLEA

@

1

@

1

1

@

1

H17

H_5P0

HOLEA

@

1

H18 H7

H_2P4X3P0N H_2P5

HOLEA

@

1

H14

H_2P8

HOLEA

1

@

@

H11

H_5P0

HOLEA

1

@

H12

H_2P8

HOLEA

1

HOLEA

1

@

H6

H_2P5

HOLEA

1

@

H5

H_2P5

HOLEA

@

H9

H_5P0

HOLEA

1

@

1

@

FD3

SLB9665 (SA00007XU00 )-->TPM2.0

SLB9660 (SA00007AB00 ) -->TPM1.2

A A

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC.

5 4 3 2

2013/02/26 2015/07/08

Compal Secret Data

DecipheredDate

@

1

FIDUCIAL_C40M80

FD4

@

1

FIDUCIAL_C40M80

Title

Size Document Number

Date: Wednesday, May 11, 2016 Sheet

Compal Electronics, Inc.

TPM/Screw

LA-D707P

FD2

@

1

FIDUCIAL_C40M80

FD1

@

1

FIDUCIAL_C40M80

28 o f 60

1

Rev

v0.2

5 4 3 2 1

+5VS<20,21,24,26,27,34,35,52,53,56>

2.5" SATA HDD

D D

<7,13,20,23,26,27,33,35,48,49,50,51,55>+3VALW

<PV> change short pad

+5VS

R201 1 2 0_0603_5%
R202 1 2 0_0603_5%

+5VS_HDD1

<11> SATA_PTX_DRX_P0
<11> SATA_PTX_DRX_N0

<11> SATA_PRX_DTX_N0

<11> SATA_PRX_DTX_P0

C155 1
C156 1

C153 1
C154 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

+5VS_HDD1

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0

SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0

<SI> add 470p for EMI issue

C C

+5VALW<12,13,20,27,31,33,35,38,48,49>

<32> +3VS_WLAN_R

<DB> change JHDD pin define

CONN@

JHDD

1

1

2

2

3

3

4

4

5

5

6

6 G1

7

7 G2

8

2

C140

470P_0402_50V8J

1

EMI@

8

ACES_51524-0080N-001

SP01001A900

+5VS
+5VALW
+3VALW
+3VS_WLAN_R

9
10

2.5" SATA ODD

+5VS

+5VS_ODD

B B

+3VALW

C227

10U_0603_6.3V6

M

1

2

C228

10U_0603_6.3V6

M

1

2

10U_0603_6.3V6

M

1

@

C229

<10> ODD_PWR

2

+5VALW

<26> WL_PWREN_EC

U20

1

VIN1
VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

1

C224

1U_0402_10V4

Z

EM5209VF DFN 14P DUAL LOADSW

SA00007PM00

2

VOUT1
VOUT1

CT1

GND

CT2

VOUT2
VOUT2

GPAD

14
132

12
11
10
9

8
15

C226

1

2

560P_0402_50V7K
C230

2 1

100P_0402_50V8J

Z

1

2

1U_0402_10V4

C223

+3VS_WLAN_R

<11> ODD_PLUG#

<11> SATA_PTX_DRX_P1
<11> SATA_PTX_DRX_N1

<11> SATA_PRX_DTX_N1
<11> SATA_PRX_DTX_P1

1 @ 2

0_0201_5% R5192

2

CH751H-40PT_SOD323-2

SCS00003500

1

DC6

CS11
CS14

CS15
CS18

<10> ODD_DA#

2

1 0.01U_0402_16V7K

2

1 0.01U_0402_16V7K

2

1 0.01U_0402_16V7K

2

1 0.01U_0402_16V7K

SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1

SATA_PRX_C_DTX_N1
SATA_PRX_C_DTX_P1

+5VS_ODD

1 @ 2

0_0201_5% R5193

2 1

DC7

CH751H-40PT_SOD323-2

SCS00003500

1

ESD@

CS7

2

0.1U_0402_16V7K

CONN@

JODD

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_51524-0100N-001

SP01001AI00

A A

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC.

5 4 3 2

2013/02/26 2015/07/08

Compal Secret Data

DecipheredDate

Title

Size Document Number

B

Date: Wednesday, May 11, 2016 Sheet

Compal Electronics, Inc.

HDD/ODD Conn

LA-D707P

1

30 o f 60

Rev

v0.2

A B C D E

<11> USB3_TX1_N

1 1

2 2

<11> USB3_TX1_P

<11> USB3_RX1_N

<11> USB3_RX1_P

LM3 2nd :SM070002J00

USB3_TX1_N

0.1U_0402_16V7K

USB3_TX1_P

0.1U_0402_16V7K

2

2

1 2

RS6 0_0402_5%

1 2

RS3 0_0402_5%

<SI> change to 0504 choke

LM3SM070003Z00

<11> USB20_P1

<11> USB20_N1

4 3 USB20_P1_C

1

MCM1012B900F06BP_4P

2 USB20_N1_C

1 CS2

1 CS1

USB3_TX1_C_N

USB3_TX1_C_P

LM1,LM2 2nd : SM070003K00

USB3RXDN1_C

2

RG76

@ 150_0402_5%

1

USB3RXDP1_C

1 2

RS2 0_0402_5%

1 2

RS1 0_0402_5%

<DB> Delete Choke add parallel 150ohm

@ 150_0402_5%

1

USB3RXDN1_C
USB3RXDP1_C
USB3TXDN1_C_R 4

ESD@

USB3TXDP1_C_R5

USB3TXDN1_C_R

2

RG75

USB3TXDP1_C_R

<26,33> USB_ON#

DM2

1

1

2

2

4
5

3

3

8

TVWDF1004AD0 DFNESD

SC300002800

9 USB3RXDN1_C

10

8 USB3RXDP1_C

9

7 USB3TXDN1_C_R

7

6 USB3TXDP1_C_R

6

USB3.0 need support 3.5A
change USB PWR SW SA00007AO00

+5VALW

W=100mils

USB_ON# 1 2

RS4 0_0402_5%

ESD@

DM1 SCA00000U10

1

YSLC05CH_SOT23-3

low active

1

CS3

0.1U_0402_16V7K

2

2

USB20_N1_C

3 USB20_P1_C

<12,13,20,27,30,33,35,38,48,49> +5VALW

US1

5

IN

4

EN

SY6288D20AAC_SOT23-5

SA00007AO00

1

OUT

2

GND

3

OCB

USB20_N1_C
USB20_P1_C

USB3RXDN1_C
USB3RXDP1_C

USB3TXDN1_C_R
USB3TXDP1_C_R

+USB_VCCA

+USB_VCCA

@

CS4

W=100mils

1

2

1

CS5

2

1000P_0402_50V7K

0.1U_0402_16V7K

<DB> change JUSB1 footprint

USB2.0/USB3.0 port 1

JUSB1 CONN@

1

VBUS

2

D-

3

D+

4

GND

5

SSRX-

6

SSRX+ GND

7

GND GND

8

SSTX- GND

9

SSTX+ GND

TAITW_PUBAU1-09FNLS1NN4H0

+5VALW

1

1

2

@

+

CS6

CS22

2

47U_0805_6.3V6

M

DB Phase
add CS22 reserve

20141113

10
11
12

13

150U_B2_6.3VM_R45M

3 3

<11> USB20_N2

<11> USB20_P2

USB2.0 port x 1

<SI> change to 0504 choke

LM5SM070003Z00

4 3 USB20_N2_C

1

MCM1012B900F06BP_4P

2 USB20_P2_C

D29 ESD@

SCA00000U10

1

YSLC05CH_SOT23-3

2 USB20_N2_C
3 USB20_P2_C

+USB_VCCA

USB20_N2_C
USB20_P2_C

CONN@

JUSB2

1

VBUS

2

D-

3

D+

4

SHIELD

5

GND

6
7

GND

8

GND
GND

TAITW_PUBAU0-04FLBSCNN4H0

LM5 2nd :SM070002J00

4 4

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC.

A B C D

2013/02/26 2015/07/08

Compal Secret Data

DecipheredDate

Title

Size Document Number

B

Date: Wednesday, May 11, 2016 Sheet

Compal Electronics, Inc.

USB 3.0/2.0 conn

LA-D707P

E

31 o f 60

Rev

v0.2

5

4

3

2

1

100P_0402_50V8J

0.1U_0402_25V6

12

1 1

CN2
22U_0603_6.3V6K

2 2

+3VS

+5VALW
+3VALW
+3VS_WLAN_R

DBPhase
For RFrequest

12

20141117

0.1U_0402_25V6

0.1U_0402_16V7

K

CN3

100P_0402_50V8J

12

<5,6,7,9,10,11,13,17,18,19,20,21,22,23,24,26,28,33,34,35, 36,37,38,52,55,56>+3VS

<12,13,20,27,30,31,33,35,38,48,49> +5VALW

<7,13,20,23,26,27,30,33,3 5,48,49,50,51,55> +3VALW

D D

+3VS_WLAN

JWLAN1

1 2

1_GND 3.3V_2

<11> USB20_P4
<11> USB20_N4

+3VS_WLAN

1

RN3
10K_0402_5%

2

C C

<9,26> EC_PCIE_WAKE#

RN13 1 2 0_0201_5%

MC_WAKE#

<11> PCIE_PTX_C_DRX_P6

<11> PCIE_PTX_C_DRX_N6

<11> PCIE_PRX_DTX_P6

<11> PCIE_PRX_DTX_N6

<9> CLK_PCIE_WLAN

<9> CLK_PCIE_WLAN#

DB Phase
For RFrequest

20141117

<9> MINI1_CLKREQ#

@RF@

R5185

2 1

2 1

10P_0402_50V8J

10P_0402_50V8J

@RF@

R5186

3

3_USB_D+ 3.3V_4

5

5_USB_D- LED1#_6

7

7_GND N/C_8

9

9_N/C

11

11_N/C

13

13_N/C

15

15_N/C

17

17_N/C

19

19_N/C

21

21_N/C

23

23_N/C

33_GND
35_PERp0
37_PERn0
39_GND
41_PETp0
43_PETn0
45_GND
47_REFCLKP0
49_REFCLKN0

43

51_GND SUSCLK_50

45

53_CLKREK0# PERST0#_52

47

55_PEWake0# W_DISABLE2#_54

49

57_GND W_DISABLE1#_56

51

59_N/C N/C_58

53

61_N/C N/C_60

55

63_GND N/C_62

57

65_N/C RESERVED_64

59

67_N/C N/C_66

61

69_GND N/C_68

63

71_N/C N/C_70

65

73_N/C 3.3V_72

67

75_GND 3.3V_74

LOTES_APCI0019-P003H

CONN@ SP070010DA0

N/C_10
N/C_12
N/C_14

LED2#_16

GND_18

N/C_20
N/C_22

N/C_32
N/C_34

N/C_36
CLink Reset_38
CLink DATA_40

CLink CLK_42

COEX3_44
COEX2_46
COEX1_48

GND

GND
NC_70
NC_71

4
6
8
10

12
14
16

18
20

22

2425
2627

2829
3031
3233
3435
3637
3839
4041
42
44

46

48
50
52
54
56
58
60
62
64
66

68
69

70
71

RN14 1 2 0_0201_5%

+3VS_WLAN

100P_0402_50V8J

R5179 R5180

@RF@ @RF@

2 1

+3VS_WLAN

RN7

4.7K_0402_5%

1

2

0.1U_0402_25V6

2 1

E51TXD_P80DATA <26>
E51RXD_P80CLK <26>

SUSCLK <9>

PLT_RST# <9,23,26,28,36>

BT_ON_EC <26>

WL_OFF# <10>

<MV > connect to +3VS_WLAN

MINI1_LED# <26>

DBPhase
For RFrequest

20141117

<30> +3VS_WLAN_R

+3VS_WLAN

@RF@ @RF@ @RF@ @RF@

R5181 R5182 R5183 R5184

+3VS_WLAN_R +3VS_WLAN

R271

1 2

0_0805_5%

12

NGFF and WLAN

+3VS +3VS_WLAN

B B

2

G

<9> WAKE#

1 3

D

@

2N7002H_SOT23-3

S

QB8

Unpop QB4 and RL23 for not support OBFF

A A

5

@

RL25

100K_0402_5%

MC_WAKE#

2

1

Securiiity Clllassifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS

4

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

3

2013/02/26 2015/07/08

Compal SecretData

Deciphered Date

2

Tiiitttllle

WLAN-BT

Siiize Documenttt Number

LA-D707P

Compal Electronics,Inc.

Sheettt 32 offf 60Dattte::: W ednesday, May 11, 2016

1

Rev

v0.2

A B C D E

<13,26,46,47,48> +3VL

Powert Button Connector

1 1

@EMI@

C166

0.1U_0402_16V7K

<26> LID_SW#

<26> ON/OFF#

2 2

+3VL

1

ON/OFF# 2

@

PJ9

1

2

1 2

2

<DB> change JPWR footprint by DFB request

JPWR

1

1

2

2

3
4

SP01000TB10

PCB Footprint =HB_A090420-SAHR21_4P

Layout notes

L

PJ9 place Top layer, PJ6
place Bottom layer

5

3 G1

6

4 G2

E-T_6916K-Q04N-03R

CONN@

SHORTPADS

LID_SW#

CC125

100P_0402_50V8J

ESD@

R215

100K_0402_5%

@

PJ6

1 2

SHORTPADS

IO BD Connector ( USB2.0,Card reader,HDD & PWR LED )

+3VL

1

<5,6,7,9,10,11,13,17,18,19,20,21,22,23,24,26,28,32,34,35,36,37,38,52,55,56> +3VS

<SI> add 470p for EMI issue

Card reader

USB2.0 ( on small BD )

<26,31> USB_ON#

<11> SATA_LED#

DB phase :
modify pin define
20141114

<26> PWR_LED#

<SI> add 470p for EMI issue

<12,13,20,27,30,31,35,38,48,49> +5VALW

<7,13,20,23,26,27,30,35,48,49,50,51,55> +3VALW

C139

1 2

470P_0402_50V8J

470P_0402_50V8J

+5VALW

+3VS

+3VALW

EMI@

USB20_N7_C

USB20_P7_C
USB20_N3_C

USB20_P3_C

SATA_LED#

PWR_LED#

1 1

EMI@EMI@

C138 C137

2 2

470P_0402_50V8J

11/26 change CONN.

CONN@

JIO1

1

1

2

2

3

3

4

4

5

5

6

6

7

7
8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

G1
G2

CVILU_CF31181D0R4-10-NH

SP011411241

+3VL
+5VALW
+3VS
+3VALW

19
20

LM4 SM070003Z00

3 3

<11> USB20_N3

<11> USB20_P3

3.3P_0402_50V8J CC152

EMI@

<MV> add AC cap

<11> USB20_N7

<11> USB20_P7

4 4

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A B C D

Compal Secret Data

DecipheredDate

3.3P_0402_50V8J CC154

EMI@

2015/ 07/0 82013/02/ 26

4

1

MCM1012B900F06BP_4P

<SI> change to 0504 choke

LM6 SM070003Z00

4

1

MCM1012B900F06BP_4P

Title

Size Document Number Rev

B

Date: Wednesday, May 11, 2016 Sheet

3 USB20_N3_C

2 USB20_P3_C

3 USB20_N7_C

2 USB20_P7_C

Compal Electronics, Inc.

IO CON

LA-D707P

E

v0.2

33 of 60

A B C D E

+3VS<5,6,7,9,10,11,13,17,18,19,20,21,22,23,24,26,28,32,33,35,36,37,38,52,55,56>

+3VS

+5VS<20,21,24,26,27,30,35,52,53,56>

1 1

2 2

+5VS

<PV> change short pad

1A

R5177

1 2 +FAN1

0_0603_5%

10U_0603_10V6

M

40 mils

0.1U_0402_16V7

K

C4801

1

2

Layout notes

L

C4801 C5214 close to CONN

C5214

1

Close to Connector

2

<26> FAN_SPEED1

+FAN1

+3VS

1

RE50
10K_0402_5%

2

1

CE24

0.01U_0402_25V7K

2

RE51

1 @ 2

10K_0402_5%

<26> EC_FAN_PWM1

EC_FAN_PWM1

+FAN1

<DB> change FAN pin define

CONN@

JFAN1

6

GND2

5

GND1

4

4

3

3

2

2

1

1

ACES_50271-0040N-001

SP02000TS00

+5VS

3 3

4 4

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A B C D

Compal Secret Data

DecipheredDate

2015/ 07/0 82013/02/ 26

Title

Size Document Number Rev

B

Date: Wednesday, May 11, 2016 Sheet

Compal Electronics, Inc.

FAN

LA-D707P

E

v0.2

34 of 60

A

B

C D E

@RF@

10U_0603_6.3V6M

1

1

2

+5VALW

CC162

0.1U_0402_25V6

Q21

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

EM5209VF DFN 14P DUAL LOADSW

1

SA00007PM00

CC158

2

0.1U_0402_25V6

VOUT1
VOUT1

CT1

GND

CT2

VOUT2
VOUT2

GPAD

14
13

12

C554 1 2 100P_0402_50V8J

11
10

C557 1 2 680P_0402_50V7K

9
8

15

+3VALW

1 1

2 2

+5VALW

<12,13,26,49> SUSP#

SUSP#

SUSP#

1

1

CC160

CC161

2

0.1U_0402_25V6

@ESD@ @ESD@ @ESD@ @ESD@ @ESD@

1

CC157

2

2

0.1U_0402_25V6

0.1U_0402_25V6

2

22U_0805_6.3V6M

1

C575

1

2

CC140

2

+3VS

C570

10U_0603_6.3V6M

For +1.8V_PRIM Discharge

+5VALW +1.8V_PRIM

1

R5092
100K_0402_1%

2

PCH_PWR_EN# 5

6

3 3

<13,26,51> PCH_PWR_EN

2

1

Q5001A
DMN65D8LDW-7_SOT363-6

SB00000I700

1

R5093
22_0603_1%

3 2

Q5001B
DMN65D8LDW-7_SOT363-6

SB00000I700

4

+5VS

0.1U_0402_25V6

1

CC163

2

@ESD@

<9,12,26> PM_SLP_S3#

<9,12,26,49>PM_SLP_S4#

For meet tPLT17 & tCPU28 power down sequence.
tPLT17 : 1us (Max)
tCPU28 : 1us (Max)

+3VALW

1

R5096
100K_0402_1%

2

@

PM_SLP_S3_H

61

PM_SLP_S3#

For meet tPLT15 power down sequence(Un-Stuff)
tPLT15 : 1us (Max)

2

R5095

100K_0402_1%

5

@

Q5003A
DMN65D8LDW-7_SOT363-6

SB00000I700

+3VALW

1

2

@

PM_SLP_S4_H

@

3

Q5003B
DMN65D8LDW-7_SOT363-6

SB00000I700

4

6

2

@

Q5002A
DMN65D8LDW-7_SOT363-6

1

SB00000I700

@

3

Q5002B
DMN65D8LDW-7_SOT363-6

5

SB00000I700

4

61

@

2

Q5004A
DMN65D8LDW-7_SOT363-6

SB00000I700

3

@

Q5004B

5

DMN65D8LDW-7_SOT363-6

SB00000I700

4

VR_ON <26,52>

EC_VCCST_PG_R<9,26>

SUSP#

SYSON <12,26,49>

4 4

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2014/10/09 2015/12/31

C D

Compal SecretData

Deciphered Date

Title

Siiize Document Number

Custom

Date: Sheet

Compal Electronics, Inc.

DC Interface

LA-D707P

E

Rev

35 of 60Wednesday, May 11,2016

v0.2

1

2

3

4

5

U666A @

A A

<11> PEG_PT X_C_DR X_P0
<11> PEG_PT X_C_DR X_N0

<11> PEG_PT X_C_DR X_P1
<11> PEG_PT X_C_DR X_N1

<11> PEG_PT X_C_DR X_P2
<11> PEG_PT X_C_DR X_N2

<11> PEG_PT X_C_DR X_P3
<11> PEG_PT X_C_DR X_N3

B B

C C

<10> DGPU_H OLD_RST #

<9,23,2 6,28,32> P LT_RST #

D D

<9> CLK_PEG_VGA
<9> CLK_PEG_VG A#

R1400 1 PX@ 2 1K_0402_5%

DGPU_HOLD_RST # 2
PLT_RST# 1

MC74VHC1 G08DFT2G_SC70 -5

R1681

0_0402_5%

CLK_PEG_VGA
CLK_PEG_VGA#

GPU_RST#

+3VS_VG A +3V S

13 5 2

@

U6 PX@

B

Y

A

G P

AF30
AE31

AE29
AD28

AD30
AC31

AC29
AB28

AB30
AA31

AA29

AK30
AK32

AL27

1

R1691
0_0402_5%

SD028000080

2

SA0000 0OH00

4 G PU_RST #

PX@

1

R1631
100K_0402_5%

2

PCIE_RX 0P
PCIE_RX 0N

PCIE_RX 1P
PCIE_RX 1N

PCIE_RX 2P
PCIE_RX 2N

PCIE_RX 3P
PCIE_RX 3N

PCIE_RX 4P
PCIE_RX 4N

PCIE_RX 5P

Y28

PCIE_RX 5N

Y30

PCIE_RX 6P

W31

PCIE_RX 6N

W2 9

PCIE_RX 7P

V28

PCIE_RX 7N

V30

NC#V30

U31

NC#U31

U29

NC#U29

T28

NC#T28

T30

NC#T30

R31

NC#R31

R29

NC#R29

P28

NC#P28

P30

NC#P30

N31

NC#N31

N29

NC#N29

M28

NC#M28

M30

NC#M30

L31

NC#L31

L29

NC#L29

K30

NC#K30

CLO CK

PCIE_REFCLKP
PCIE_REFCLKN

N10

TEST_PG PCIE_C ALR_R X

PERSTB

216-0841018 A0 SUN PRO S3

SA000098 V10

PCI EXPRESSINTERFACE

CALIBRATION

PCIE_CA LR_TX

DC5 SCS00003500

1 2

R70@

CH751H-40PT_SOD323-2

R1146 1 R30@ 2 0_0402_5%

PCIE_TX 0P
PCIE_TX 0N

PCIE_TX 1P
PCIE_TX 1N

PCIE_TX 2P
PCIE_TX 2N

PCIE_TX 3P
PCIE_TX 3N

PCIE_TX 4P
PCIE_TX 4N

PCIE_TX 5P
PCIE_TX 5N

PCIE_TX 6P

PCIE_TX 6N

PCIE_TX 7P
PCIE_TX 7N

NC#W 24
NC#W 23

NC#V27
NC#U26

NC#U24
NC#U23

NC#T26
NC#T27

NC#T24
NC#T23

NC#P27
NC#P26

NC#P24
NC#P23

NC#M27

NC#N26

AC Coupling Capacitor

<DB> PCIe Gen3: Recommended value is 220 nF

PCIe Gen1 and Gen2 only : Recommended value is 100 nF

PEG_PRX _DTX_P0 0.22U 6.3V K X5R 0402 2

AH30

PEG_PRX _DTX_N0 0.22U 6.3V K X5R 0402 2

AG31

PEG_PRX _DTX_P1 0.22U 6.3V K X5R 0402 2

AG29

PEG_PRX _DTX_N1 0.22U 6.3V K X5R 0402 2

AF28

PEG_PRX _DTX_P2 0.22U 6.3V K X5R 0402 2

AF27

PEG_PRX _DTX_N2 0.22U 6.3V K X5R 0402 2

AF26

PEG_PRX _DTX_P3 0.22U 6.3V K X5R 0402 2

AD27

PEG_PRX _DTX_N3 0.22U 6.3V K X5R 0402 2

AD26

AC25
AB25

Y23
Y24

AB27

AB26

Y27
Y26

W2 4

W2 3

V27

U26

U24
U23

T26
T27

T24

T23

P27
P26

P24

P23

M27

N26

R5159 1 PX@ 2 1.69K_0402_1%

Y22

R717 1 PX@ 2 1K_0402_1%

AA22

VGA_PW RGD <56>

1 PX@ C5187
1 PX@ C5188

1 PX@ C5189
1 PX@ C5190

1 PX@ C5191
1 PX@ C5192

1 PX@ C5193
1 PX@ C5194

+1.0VS_ VGA

<DB> CHANGE TO +1.0VS_VGA

PEG_PRX _C_DT X_P0 <11>
PEG_PRX _C_DT X_N0 <11>

PEG_PRX _C_DT X_P1 <11>
PEG_PRX _C_DT X_N1 <11>

PEG_PRX _C_DT X_P2 <11>
PEG_PRX _C_DT X_N2 <11>

PEG_PRX _C_DT X_P3 <11>
PEG_PRX _C_DT X_N3 <11>

No Use GPU Display Port outpud

U666F @

AB11 R1676 1 R70@ 2 0_0402_5%

VARY_BL

AB12 R1675 1 R70@ 2 0_0402_ 5%

DIGON

AL15

TXCAP_DPA3P

AK14

TXCAM_D PA3N

NC_TXOUT_L3 P
NC_TXOUT_L3 N

TMDP

TXCBP_DPB3P

TXCBM_D PB3N

NC_TXOUT_U3P
NC_TXOUT_U3N

216-0841018 A0 SU?N PROS3

TX0P_D PA2P
TX0M_DPA2N

TX1P_D PA1P
TX1M_DPA1N

TX2P_D PA0P
TX2M_DPA0N

TX3P_D PB2P
TX3M_DPB2N

TX4P_D PB1P
TX4M_DPB1N

TX5P_D PB0P
TX5M_DPB0N

AL19
AK18

AJ23

AJ15

AK16

AJ17

AJ19

AK20

AH22
AJ21

AL23
AK22

AH16

AL17

AH18

AH20

AL21

AK24

+VGA_CORE

SecurityClassification

IssuedDate

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF C OMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE S ECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRA NSFERE D FROM THE CUSTODY OF THE C OMPETEN T DIIIVIIISIIION OF R&D
DEPAR TMENT EXCE PT AS AUTHORIIIZED BY COMPA L ELECTRONIIICS,,, IIINC...NEIIITHER THIIIS SHEET NO R THE IIINFORMATIIION IIIT CONTAIIINS

1

2

MAY BE U SED B Y OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CON SENT OF CO MPAL ELECTRONIIICS,,,IIINC...

3

2013/01/11 2013/12/31

Compal SecretData

DeciiipheredDate

Tiiitllle

Siiize Document Numbe r

Custom

4

Date: Wednesday, May 11, 2016 Sheet 36 o f 60

Compal Electronics, Inc.

SUN_PCIE/DP

LA-D707P

5

Rev

v0.2

1

EC_ SMB_ DA2 1 @ 2

R162 0_0402_5%

EC_ SMB_ CK2 1 @ 2

R164 0_0402_5%

<7,10 ,19,22,26> EC_S MB_D A2

A A

<7,10 ,19,22,26> EC_S MB_C K2

<26> VGA_AC_ BATT

B B

<26,5 6> GP U_P ROCHO T#

+3VS_ VGA

VGA _SM B_DA3

VGA _SM B_CK3

ME2N70 02D1KW -G 2N_ SOT363-6

ME2N70 02D1KW -G 2N_ SOT363-6

2

R1451

@

10K_0 402_5%

1

3

@Q16 B

5

4

ME2N70 02D1KW -G 2N_S OT363-6

1

R1463210K_0 402_5%

1 @ 2

R1464 10 K_0402_5%

SB000 00I700

R174 0_ 0402_5%

REAK CURRENT CONTROL ( Topaz only )

+3VS_ VGA +1 .8VS_V GA

10K_0 402_5%

GPU_VID 3
GPU_VID 1 R1 450 1 @R 30@ 2

GPU S ide

C C

D D

33_0402 _5%

R1449 1 @R3 0@ 2

33_0402 _5%

10K_0 402_5% 10K_0402_5 %

+3VS_ VGA

+3VS_ VGA

PX@

C341

8.2P_0 402_50V_NP O

R1454
10K_0 402_5%

1

1

GPU_VID 3_GPIO15 B1

GPU_VID 1_GPIO20 C1

2

2

@R3 0@ @

R1457 R1 456

1

1

2 @R30 @ 1

R1458

10K_0 402_5% C440

GPU_VID 3
GPU_VID 1

@RP 34

1

8 JTAG_ TRSTB

2

7 JTAG_TD I

3

6 JTAG_ TMS

4

5 JTAG_TC K

10K_8 P4R_5%

R1447 1 PX@ 2
R1448 1 PX@ 2

R1446 1 PX@ 2
R1443 1 PX@ 2 VGA_CLK REQ#
R1439 1 PX@ 2 TESTEN

XTALIN R349 1 2

2

1

10K_0 402_5%

10K_0 402_5%

10K_0 402_5%
10K_0 402_5%
1K_04 02_5%

PX@

10M_04 02_5%

PX@ Y6

4

3

NC O SC

1

2

OSC NC

27MHZ 10PF +-10PP M 7V2 7000050

SJ100 009700

1

2

2

R1455

@R3 0@

@

2

1

UV4 @R 30@

A1

C366

DIR

R1662 1 R 30@ 2 0 _0402_5% GP U_S VD R 1663 1

R30@ 2 0 _0402_5% GP U_S VC

XO_IN

XO_IN2

GPIO19_ CTF

XTAL OUT

+3VS_ VGA

10K_0 402_5%

2

PX@

6 1

Q2416A

PX@

354

Q2416B

SB000 00I700

6

@Q16 A

2

1

ME2N70 02D1KW -G 2N_S OT363-6

1 2

R1440 1 @ 2

1K_04 02_5%

@R3 0@

C439

0.1U_0 402_10V6K

@R3 0@

2 1

10U_060 3_6.3V6M

@R3 0@

1

2

0.1U_0 402_10V6K

PX@

2

C350

8.2P_0 402_50V_NP O

1

A2
B2 R1 452 1 @R 30@ 2
C2 R145 3 1 @R30 @ 2
D1D2

VCC A VCCB
A1 B1
A2 B2
DIR GN D

SN74LV C2T45YZP R_DSBGA 8

PX@R327

2

1

1

2

VGA_AC _BATT_R

GPU_GP IO6

@

C442

0.1U_0 402_10V6K

2

@R3 0@

C441

0.1U_0 402_10V6K

1

33_0402 _5%

33_0402 _5%

1

PX@R328

10K_0 402_5%

2

+3VS_ VGA+3V S_VGA

R1444 1 @ 2 100K_0402_5% ACIN
R1445 1 PX@ 2 4. 7K_0402_ 5% VG A_AC_B ATT_R

<9,26 > ACIN

<9> V GA_CLKR EQ#

GPU _SV D

GPU _SV C

PWR IC

2

+1.8V S_VGA

T292 1

+VG A_C ORE

ACIN

VGA_AC _BATT_R 1 2

+VG A_C ORE

+VG A_C ORE

R1442 1 R30 @ 2 10K_0402_5%

Enable MLPS

+1.8V S_VGA

L54 PX@ S M0100 09U00

1 2

BLM15 BD121S N1D_040 2

PX@C414 2 1 10 U_0603_6.3 V6M
PX@C421 2 1 1U_ 0402_6.3V 4Z
PX@C438 2 1 0.1U_0402 _10V6K

2

VGA _SM B_DA3

VGA _SM B_CK3

R1459 1 R7 0@ 2 4 .7K_040 2_5%
R1460 1 R7 0@ 2 4 .7K_040 2_5%

R169 1 @ 2 G PU_GPIO0

1

R5189 R70 @ 0_ 0402_5%

1 2 GPU_GPIO2

1 @ 2

R165 0_0402_5%

R1661 0_ 0402_5%

R177 R70@1 2 0_0402_5%

R178 1 R70 @ 2 0_ 0402_5%

11/15:
follow AMD check list R167 non-pop by vendor

@R1 6710_0402_ 5%

2

@C5 213

68P_0 402_50V8J

R179 1 R7 0@ 2 0_04 02_5%
R180 1 R7 0@ 2 0_04 02_5%

R181 1 R70 @ 2 0_ 0402_5%

13mA

T401
T302
T303
T304
T305
T306
T307
T308
T309
T310
T311
T312
T313
T314
T315
T316
T317

0_0402_ 5%

2 GPU_GPIO1

0_0402_ 5%R176 R70@

VGA_SM B_DA3
VGA _SM B_CK3
GPU_GP IO5
GPU_GP IO6 T8

GPU_VID 3
GPU_GP IO17

GPU_GP IO18
GPIO19_ CTF
GPU_VID 1

VGA _CLK REQ# _R N7
JTAG_TRS TB

1

JTAG_TD I
JTAG_TCK
JTAG_TMS

2

1 JTAG_TD O

T70

TESTEN

T318

T221

XTALIN
XTAL OUT

XO_IN
XO_IN2

THERM_D +
THERM_D -

GPIO28
+TSV DD

1
1

AE9

1

Y11

1

AE8

1

AD9

1
1 AC1 0

AD7

1

AC8

1

AC7

1

AB9

1

AB8

1

AB7

1
1
1
1
1

W6

AC6
AC5

AA5
AA6

W1

AA1

U10

T10

P10

M4

W1 0

M2

N8

GPIO _22 _ROM CSB

AK1 0

AM1 0

AF2 4

AB1 3

W8
W9
W7

AD1 0

AJ9
AL9

AC1 4

1 AB16

1 AC1 6

AM2 8

AK2 8

AC2 2

AB2 2

AD1 7
AC1 7

N9

L9

DBG_DA TA11

AB4
AB2

Y7

V6

U1
U3

Y6

R1
R3

U6

U8
U7
T9

T7
P4

P2
N6
N5
N3
Y9
N1

R6

P8
P7

CLKREQ B

L6

L5
L3

L1
K4
K7

PX_ EN

DBG_VR EFG

T4
T2

R5

U666B @

DBG_DA TA16

DBG_DA TA15
DBG_DA TA14

DBG_DA TA13

DBG_DA TA12
DBG_DA TA10

DBG_DA TA9

DVO

DBG_DA TA8
DBG_DA TA7
DBG_DA TA6

DBG_DA TA5

DBG_DA TA4
DBG_DA TA3
DBG_DA TA2

Y8

DBG_DA TA1

DBG_DA TA0

NC#W 6
NC#V6

NC#AC5

NC#AC6

NC#AA5
NC#AA6

NC#U1

NC#W 1

NC#U3

NC#Y6
NC#AA1

I2C

SCL

SDA

GENERAL PURPOSEI/O

GPIO _0

GPIO _1

GPIO _2
SMB DATA
SMB CLK

GPIO _5_ AC_B ATT

GPIO _6

GPIO _7_ BLON
GPIO _8_ ROMS O
GPIO _9_ ROMS I
GPIO _10 _ROM SCK
GPIO _11
GPIO _12
GPIO _13
GPIO _14 _HPD 2

GPIO _15 _PW RCNTL _0

GPIO _16

GPIO _17 _THE RMAL _INT

GPIO _18
GPIO _19 _CTF
GPIO _20 _PW RCNTL _1
GPIO _21

GPIO _29

GPIO _30

JTAG _TRS TB

JTAG _TDI

JTAG _TCK
JTAG _TMS
JTAG _TDO
TEST EN
NC#AF2 4

GEN ERIC A
GEN ERIC B

GEN ERIC C
GEN ERIC D
GEN ERIC E

NC#AJ 9

NC#AL9

HPD1

PLL/CLOCK

XTAL IN

XTAL OUT

XO_ IN

XO_ IN2

SEYMOUR/FutureASIC

DPLUS

THERMAL

DMINUS

GPIO 28_ FDO

TSVD D
TSVS S

216-0841018 A0 SUN PRO?S3

3

U?

DPA

DPB

DPC

AVS SN#A K26

AVS SN#A G25

DAC1

FutureASIC/SEYMOUR/PARK

GEN LK_V SYNC

SW APLO CKA
SW APLO CKB

DDC/AUX

DDCVGA DATA

3

AF2

NC#AF2

AF4

NC#AF4

AG3

NC#AG3

AG5

NC#AG5

AH3

NC#AH3

AH1

NC#AH1

AK3

NC#AK3

AK1

NC#AK1

AK5

NC#AK5

AM3

NC#AM3

AK6

NC#AK6

AM5

NC#AM5

AJ7

NC#AJ 7

AH6

NC#AH6

AK8

NC#AK8

AL7

NC#AL7

V4

NC#V4

U5

NC#U5

W3

NC# W3

V2

NC#V2

Y4

NC#Y4

W5

NC#W 5

AA3

NC#AA3

Y2

NC#Y2

J8

NC#J8

AM2 6

R

AK26

AL2 5

G

AJ25

AVS SN#A J25

AH2 4

B

AG2 5
AH2 6

HSYN C

AJ217

VSY NC

R5191

4.7K_0 402_5%

AD2 2 PX@

RSET

AG2 4

AVD D

AE2 2

AVSSQ

AE2 3

VDD 1DI

AD2 3

VSS 1DI

AM1 2

CEC_1

AK1 2

RSVD#A K12

AL1 1

RSVD#A L11

AJ11

RSVD#A J11

AL1 3

GEN LK_C LK

AJ13

AG1 3
AH12

AC1 9 PS _0

PS_ 0

AD1 9 PS _1

PS_ 1

AE1 7 P S_2

PS_ 2

AE2 0 P S_3

PS_ 3

AE1 9

TS_A

AE6

DDC1CL K

AE5

DDC1DA TA

AD2

AUX 1P

AD4

AUX 1N

AC1 1

DDC2CL K

AC1 3

DDC2DA TA

AD1 3

AUX 2P

AD1 1

AUX 2N

AD2 0 FB_ GND R1669 1 R7 0@ 2 0 _0402_5%

NC#AD2 0

AC2 0 FB_ VDD C R1670 1 R7 0@ 2 0_0 402_5%

NC#AC2 0

AE1 6

NC#AE1 6

AD1 6

NC#AD1 6

AC1

DDCVGA CLK

AC3

Security Clllassifiiicatiiion

THIIIS SHEET O F ENGIIINEERIIING DRAW ING IIIS TH E PROPRIIIETARY PROP ERTY OF COMP AL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRADE SEC RET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANS FERE D FROM THE CUS TODY OF THE C OMPE TENT DIIIVIIISIIION O F R &D
DEP ARTME NT EXC EPT AS AUTHORIIIZED B Y CO MPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHE ET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY B E USE D BY OR DIIISCLOSED TO AN Y THIIIRD PARTY WI THOUT PRIIIOR W RIIITTEN CONSEN T OF COM PAL ELECTRONIIICS,, ,IIINC...

4

Resistor Divider Lookup Lable

R_pd (ohm )R_pu (ohm )

Bitd [3:1]

NC

4.75k
2k
2k

4.99 k

4.99k

5.62k
10k
NC

000 <DB>
001
010
011
100
101
110
111

8.45k

4.53k

6.98k

4.53k

3.24k

3.4k

4.75k

0402 1% resistors are equired

Capacitor Divider Lookup Lable

Cap( nF) Bitd [5:4]

680nF 00
82nF 01
10nF 10

NC

PLL_A NALOG_OU T R1 469 1 @ 2

<56> +VGA_VD DIO

+1.8V S_VGA +3VS_ VGA

R1673 1 R70 @ 2
0_0402_ 5%

2

SVI2_S VD

R1664 R 70@

SVI2_S VT R1 665 1 R7 0@ 2 0_0402 _5%
SVI2_S VC R1 666 1 R7 0@ 2 0_04 02_5% GP U_S VC

2

PX@

R1461

10K_0 402_5%

1

GPU _SV D
GPU _SV C

2

R1467

@

10K_0 402_5%

1

1 2 0_0402_ 5%G PU_ SVD

16.2K_ 0402_1%

GPU _SV T

11

R1674 1 R30@ 2
0_0402_ 5%

2

@

R1462
10K_0 402_5%

1

2

R1468

PX@

10K_0402_ 5%

1

GPU _SV D < 56>
GPU _SV T <56>
GPU _SV C < 56>

(default)

Memo ry ID Memo ry Type Con f i gur at i no Siz e

SA00009H F00

000

SA00008D N00

001

SA00009I 400

010

011 S A00009IB00

SA000076 P80

100

101 3.24K 5.62K

110
111

+VG A_C ORE

R1667 1 R 70@ 2 0 _0402_5%
R1668 1 R 70@ 2 0_ 0402_5%

VGA _VS SSENS E R167 2 1 PX@ 2 10_0402_5%
VGA _VC CSENS E R167 7 1 P X@ 2 10_0402_5%

+3VS_ VGA

Issued Date

VGA _VS SSENS E <56>
VGA _VC CSENS E <5@6>

RV133 2.2K_ 0402_5%

2013/01/11 2013/12/31

PX@

2 1

CV271 0.1U_0402_ 16V4Z

+VG A_C ORE

@PX @

2

1

CV272

THER M_D + 1 2 THERM_ D-

2200P _0402_50V7K

@PX @

Compal Secret Data

Deciiiphered Date

4

THER M_D +

PS_0[3: 1]=001
PS_0[5: 4]=11

PS_0

use Gen3

PS_1[3: 1]=000
PS_1[5: 4]=11

PS_1

PS_2[3: 1]=000
PS_2[5: 4]=11

PS_2

0.082U _0402_16V6K 4 .75K_04 02_1%

PS_3[3: 1]=000
PS_3[5: 4]=11

PS_3

+1.8V S_VGA

1 2

C=NC

2

+1.8V S_VGA

11 2

C=NC

2

+1.8V S_VGA

R=NC

1

PX@ PX@

C5203 R5164

2

2

+1.8V S_VGA

C=NC

2 1 2

Micron MT41J256M16LY-091G:N

Hynix H 5TC4G63CFR-N 0C

Micron MT41K512M 16HA-107G:A

Hynix H 5TC8G63CMR-11C

Samsung K4W4 G1646E-BC1A

+3VS_ VGA+3VS

+3VS_ VGA

THERM_D -

8 1

6 3 E C_S MB_DA 3

@PX @ 2.2 K_0804_8P 4R_5%

UV13

1 V DD SCL

2 D+ SDA

3 D- A LER T#

4 T_C RIT# GND

NCT7718 W_MSOP8

SA000 067P00

Address:1001100xb (x is R/W bit)

1

PX@

R5165

8.45K_ 0402_1%

PX@

R5166
2K_04 02_1%

<DB> use Gen

PX@

R5167

8.45K_ 0402_1%

PX@

R5168
2K_04 02_1%

1

1

X76@

R5174

8.45K_ 0402_1%

X76@

R5169

4.75K_ 0402_1%

@PX @

RP13

2 THS_S DA7
4 E C_S MB_C K3

5

8

7

6

5

5

Strap Name :

PS_0[1] RO M_CONFIG[0]
PS_0[2] RO M_CONFIG[1]
PS_0[3] RO M_CONFIG[2]
PS_0[4] N/A
PS_0[5] AUD_PORT_CONN_P INSTRAP[0]

Strap Name :

3

PS_1[1] STRAP_BIF_GEN3_EN_A
PS_1[2] TRAP_BIF_CLK_PM_EN
PS_1[3] N/A
PS_1[4] STRAP_TX_CFG_DRV_FULL_ SWING
PS_1[5] STRAP_TX_DEEMPH_EN

Strap Name :

PS_2[1] N/A
PS_2[2] N/A
PS_2[3] STRA P_BIOS_R OM_EN
PS_2[4] STRAP_BIF_VGA_DIS
PS_2[5] N/A

Strap Name :

PS_3[1] BOARD_CONFIG[ 0] (Mem ory ID)
PS_3[2] BOARD_CONFIG[ 1] (Mem ory ID)
PS_3[3] BOARD_CONFIG[ 2] (Mem ory ID)
PS_3[4] AUD_PORT_CONN_PINSTRAP[1]
PS_3[5] AUD_PORT _CONN_PINSTRAP[2]

R5174 R5169

4.75K

NC

2GB

2GB

4GB

4GB

2GB

2K

8.45K
2K

4.53K

6.98K 4.99K

4.53K 4.99K

3.4K 10K

4.75K

NC

+3VS_ VGA

THS_SCL

THS_SCL
THS_ SDA

Tiiitttllle

Siiize Documenttt N umber

Custo m

Dattte::: Wednes day, May 11, 2016 Sheettt 37 o fff60

ME2N70 02D1KW -G 2N_S OT363-6

2

@PX @

6 EC_S MB_C K31

Q2415A

5

SB000 00I700

@PX @

4

3EC_ SMB_ DA3

Q2415B ME2N 7002D1K W-G 2N _SOT363 -6

SB000 00I700

@PX @

2

1

2.2K_0 402_5%

RV134

1 @ 2 GP U_GPIO17

R168 0_0402_5%

Compal Electronics, Inc.

SUN_MSIC

LA-D707P

5

X76 P/N

X7667032 L04

X7667032 L03

X7662732L03

EC_ SMB_ CK3 < 26>

EC_ SMB_ DA3 < 26>

+3VS_ VGA

Re v

v0.2

1 2 3 4 5

+1.5VS to +1.5VS_VGA (2.096A)

+1.5VS_ VGA

Delete +1.5VS to +1.5VS_VGA power switch

2

PX@

R4102

A A

B B

C C

+3VS to +3VS_VGA (25mA)

+1.8V_PRIM to +1.8VS_VGA (311mA)

+3VS +3VS_VG A

0.1U_04 02_16V7 K

1

C4111

DGPU_PWR_EN

+5VALW

2

PX@

DGPU_PWR_EN

+1.8V_PRIM +1.8VS_ VGA

0.1U_04 02_16V7 K

1

C4123

2

PX@

Main: SA00004MM00, TI, TPS22 966
2nd: SA00006FD00, A-Po wer, APE8 990 GN3B
3rd: AOS, AOZ1331 (engineering sample a vailable on 2013 /Ja n/18 )

PX@

U4103

1

VOUT1

VIN1

VOUT1

VIN1

3

5
6

7

CT1

ON1
VBIAS

GND

ON2

CT2

VIN2

VOUT2

VIN2

VOUT2

GPAD

TPS22966DPUR_SON 14_2X3

SA0000 7PM00

<Diner SI> change to NC & 470p

14
132

12 C4112
114
10 C4126
9

8
15

60mA

1 2 @PX@

470P_0402_5 0V7K

1 2 PX@

470P_0402_5 0V7K

818mA

10_0603_5%

31

5 PXS_PWREN#

QV4101 B PX@

4

ME2N700 2D1KW-G 2N_SOT 363-6

SB00000I7 00

JG3 JP@

1

2

1 2

0.1U_04 02_16V7 K

JUMP_43 X39

JG18 J P@

1

1

JUMP_43 X39

1

2

2

2

0.1U_04 02_25V6

1

2

0.1U_0402_25V6

1

C4124

CC164

PX@ 2@ESD@

C4125

2

PX@

R346

PX@ 10_0603_5%

D

1 1

2 PXS_PWREN #

G

PX@Q91

S

ME2N700 2D1W -G 1N_SC70- 3

SB00000Z 600

3

<DB> CHANGE TO +1.0VS_VGA

+1.8VS_ VGA

R319 1
0_0603_5%

+1.0VS_ VGA

R320 1 2
0_0603_5%

370mA (HDMI)
188mA (Display Port)

+DP_VDD R

2

1

1

2

2

@

@

1U_0402_6.3V4Z C446

0.1U_04 02_10V6 K C447

280mA

+DP_VDD C

1

1

2

2

@

@

1U_0402_6.3V4Z C450

0.1U_04 02_10V6 K C451

No Use GPU Display Port outpud

U666G @

AG15

DP_VDD R#AG15

AG16

DP_VDD R#AG16

AF16

DP_VDD R#AF16

AG17

DP_VDD R#AG17

AG18

DP_VDDR #AG18

AG19

DP_VDDR #AG19

AF14

DP_VDDR #AF14

AG20

DP_VDD C#AG20

AG21

DP_VDD C#AG21

AF22

DP_VDDC #AF22

AG22

DP_VDDC #AG22

AD14

DP_VDDC #AD14

AG14

DP_VSSR

AH14

DP_VSSR

AM14

DP_VSSR

AM16

DP_VSSR

AM18

DP_VSSR

AF23

DP_VSSR

AG23

DP_VSSR

AM20

DP_VSSR

AM22

DP_VSSR

AM24

DP_VSSR

AF19

DP_VSSR

AF20

DP_VSSR

AE14

DP_VSSR

AF17

DPAB_CAL R

216-0841018 A0 SUN PR?OS3

DPPOWER

U?

NC/DPPOWER

NC#AE11
NC#AF11
NC#AE13
NC#AF13

NC#AG8

NC#AG10

NC#AF6
NC#AF7
NC#AF8
NC#AF9

NC#AE1

NC#AE3
NC#AG1
NC#AG6
NC#AH5
NC#AF10
NC#AG9
NC#AH8
NC#AM6
NC#AM8

NC#AG7

NC#AG11

NC#AE10

AF11

AG8
AG10

AF7
AF8
AF9

AE3

AG1
AG6
AH5
AF10

AG9
AH8
AM6
AM8
AG7

AG11

AE11

AE13
AF13

AF6

AE1

AE10

U666E @

AA27

GND

AB24

GND

AB32

GND

AC24

GND

AC26

GND

AC27

GND

AD25

GND

AD32

GND

AE27

GND

AF32

GND

AG27

GND

AH32

GND

K28

GND

K32

GND

L27

GND

M32

GND

N25

GND

N27

GND

P25

GND

P32

GND

R27

GND

T25

GND

T32

GND

U25

GND

U27

GND

V32

GND

W2 5

GND

W2 6

GND

W2 7

GND

Y25

GND

Y32

GND

M6

GND

N13

GND

N16

GND

N18

GND

N21

GND

P6

GND

P9

GND

R12

GND

R15

GND

R17

GND

R20

GND

T13

GND

T16

GND

T18

GND

T21

GND

T6

GND

U15

GND

U17

GND

U20

GND

U9

GND

V13

GND

V16

GND

V18

GND

Y10

GND

Y15

GND

Y17

GND

Y20

GND

R11

GND

T11

GND

AA11

GND

M12

GND

N11

GND

V11

GND

216-0841018 A0 SUN ?PROS3

U?

A3

GND

A30

GND

AA13

GND

AA16

GND

AB10

GND

AB15

GND

AB6

GND

AC9

GND

AD6

GND

AD8

GND

AE7

GND

AG12

GND

AH10

GND

AH28

GND

B10

GND

B12

GND

B14

GND

B16

GND

B18

GND

B20

GND

B22

GND

B24

GND

B26

GND

B6

GND

B8

GND

C1

GND

C32

GND

E28

GND

F10

GND

F12

GND

F14

GND

F16

GND

F18

GND

F2

GND

F20

GND

F22

GND

F24

GND

F26

GND

F6

GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND

VSS_ MECH
VSS_ MECH
VSS_ MECH

F8
G10
G27

G8

H2
H20

K2
K22

K6

A32
AM32

G31

H14
H17

H6
J27
J31
K11

AM1

+1.0V_PRIM to +1.0VS_VGA (4.016A)

+1.0V_PRIM

PX@

U4102

AO4354 _SO8

8
7

0.1U_04 02_16V7 K

6
5

1

C4113

SB0000 0ZN00

2

PX@

+19.5VB

D D

1 2 3 4

1 PX@ 2

R4109 200K_0402_5 %

PXS_PW REN#

2

0.95VSG_GATE

1

61

@ R4104

1.5M_0402_5%

2

PX@

Q4102A
ME2N700 2D1KW-G 2N_SOT 363-6

SB00000I7 00

4

+1.0VS_ VGA

<DB> CHANGE TO +1.0VS_VGA

1
2
3

1

PX@C4122

0.01U_0402_25V7K

2

1U_0402_6.3V4Z

10U_0603_6.3V6 M

1

C4114

2

PX@

1

C4115

2

PX@

3 1

4

2

PX@

R4107
10_0603_5%

5 PXS_PW REN#

PX@

Q4102B
ME2N700 2D1KW-G 2N_SOT 363-6

SB00000I7 00

PX@

R4113
100K_0402_5%

PXS_PW REN#

<10,26, 55,56> DGPU_PWR _EN

SecurityClassification

IssuedDate

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF C OMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE S ECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRA NSFERE D FROM THE CUSTODY OF THE C OMPETEN T DIIIVIIISIIION OF R&D
DEPAR TMENT EXCE PT AS AUTHORIIIZED BY COMPA L ELECTRONIIICS,,, IIINC...NEIIITHER THIIIS SHEET NO R THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE U SED B Y OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CON SENT OF CO MPAL ELECTRONIIICS,,,IIINC...

2013/01/11 2013/12/31

DGPU_PWR_EN

PX@ R4115 SB00000I7 00

100K_0402_5%

2

Compal SecretData

DeciiipheredDate

3 1

2

5

PX@

Q4105B

1

4

ME2N700 2D1KW-G 2N_SOT 363-6

+VGA_CORE+5VALW

ME2N700 2D1KW-G 2N_SOT 363-6

PX@

2

R4114
470_0603_5%

6 11

2 PXS_PWR EN#
PX@

Q4105A

SB00000I7 00

Tiiitllle

Siiize Document Numbe r

Custom

Compal Electronics, Inc.

SUN_Power/GND

Date: Wednesday, May 11, 2016 Sheet 38o f 60

LA-D707P

5

Rev

v0.2

1 2 3 4 5

C422

0.1U_04 02_10V6 K

C433

0.1U_04 02_10V6 K

1

2

PX@

1

2

PX@

+3VS_VG A

+1.8VS_ VGA

+1.5VS_ VGA

C365

10U_0603_6.3V6 M

2

1

PX@ C3720

PX@ C3719

0.01U_0402_16V7K

0.01U_0402_16V7K

L24 PX@

1 2

BLM15BD 121S N1D_ 0402

SM010009U00

L48 PX@

1 2

BLM15BD 121S N1D_ 0402

SM010009U00

1

1

1

1

C367

2

2

PX@

PX@

10U_0603_6.3V6 M

2

2

1

1

PX@ C3721

0.01U_0402_16V7K

1

C408

2

PX@

10U_0603_6.3V6 M

C370

C375

2

2

PX@

PX@

10U_0603_6.3V6 M

2.2U_04 02_6.3V 5M

2

2

C389

1

1

PX@ C3722

PX@ C3723

0.01U_0402_16V7K

0.01U_0402_16V7K

0.1U_04 02_10V6 K

1

1

1

C428

C429

C410

2

2

2

@

PX@

PX@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_04 02_10V6 K

1

1

C434

C409

+1.0VS_ VGA

2

2

BLM15BD 121S N1D_ 0402

PX@

PX@

1U_0402_6.3V4Z

0.1U_04 02_10V6 K

1

1

1

C373

C371

C372

2

2

2

PX@

PX@

PX@

2.2U_04 02_6.3V 5M

2.2U_04 02_6.3V 5M

2.2U_04 02_6.3V 5M

1

1

1

C381

C390

C391

2

2

2

PX@

PX@

PX@

0.1U_04 02_10V6 K

0.1U_04 02_10V6 K

0.1U_04 02_10V6 K

1

C417

2

PX@

10U_0603_6.3V6 M

<DB> CHANGE TO +1.0VS_VGA

L53 PX@

1 2
SM010009U00

1

C374

2

1A

PX@

2.2U_04 02_6.3V 5M

1

1

C392

2

2

PX@

PX@

13mA

0.1U_04 02_10V6 K

+VDD_CT

25mA

+VDDR3

90mA

+MPLL_P VDD

75mA

+SPLL_PVDD

100mA

+SPLL_VDDC

1

1

1

C435

C412

C411

2

2

2

PX@

PX@

PX@

1U_0402_6.3V4Z

0.1U_04 02_10V6 K

10U_0603_6.3V6 M

U666D @

MEM I/O

H13

VDDR1

H16

VDDR1

H19

VDDR1

J10

VDDR1

J23

VDDR1

J24

VDDR1

J9

VDDR1

K10

VDDR1

K23

VDDR1

K24

VDDR1

K9

VDDR1

L11

VDDR1

L12

VDDR1

L13

VDDR1

L20

VDDR1

L21

VDDR1

L22

VDDR1

LEVEL
TRANSLATION

AA20

VDD_CT

AA21

VDD_CT

AB20

VDD_CT

AB21

VDD_CT

I/O

AA17

VDDR3

AA18

VDDR3

AB17

VDDR3

AB18

VDDR3

V12

VDDR4

Y12

VDDR4

U12

VDDR4

PLL

L8

MPLL_PVDD

H7

SPLL_P VDD

H8

SPLL_VD DC

J7

SPLL_P VSS

216-0841018 A0 SUN PRO S?3

U?

PCIE

PCIE_PVDD

NC#AB23
NC#AC23
NC#AD24
NC#AE24
NC#AE25
NC#AE26
NC#AF25

NC#AG26

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

CORE

POWE R

BIF_VDDC
BIF_VDDC

ISOLATED

CORE I/O

VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

VDDC
VDDC
VDDC
VDDC

+PCIE_PVDD:
50mA(PCIE2.0)
80mA (PCIE3.0)

AM30

AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26

L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22

AA15
N15
N17
R13
R16
R18
Y21
T12
T15
T17
T20
U13
U16
U18

V21
V15
V17
V20
Y13

Y16
Y18
AA12

M11
N12
U11

R21
U21

+VGA_CORE

M13
M15
M16
M17
M18
M20
M21
N20

+1.8VS_ VGA

C387

2

PX@

1U_0402_6.3V4Z

1 1 1 1 1

C398

2 2 2 2 2

@

PX@

1U_0402_6.3V4Z

1

C394

2

PX@

0.1U_04 02_10V6 K

C399

1U_0402_6.3V4Z

<DB> C HANGE TO+1.0VS_ VGA

+1.0VS_ VGA

C403

C383

PX@

PX@

PX@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1 1

C380

2

PX@

10U_0603_6.3V6 M

+PCIE_VDDC:

1.88A(PCIE2.0)

2.5A (PCIE3.0)

1 1

C386

C384

2 2

PX@

10U_0603_6.3V6 M

10U_0603_6.3V6 M

+VGA_CORE

21A (VDDC + VDDCI (Merged) - PRO S3 (DDR3))

1.4A

+BIF_VDD C

1

C415

C413

2

@

1U_0402_6.3V4Z

10U_0603_6.3V6 M

R398

1 2

0_0805_5%

1

1

C416

2

2

@

@

1U_0402_6.3V4Z

1 1

C388

C3724

2 2

@

PX@ C3725

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V4Z

<DB> C HANGE TO+1.0VS_ VGA

+1.0VS_ VGA

A A

+VGA_CORE 10uF 1uF

VDDC TBD 5 (1@) 10 (2@)

VDDCI 3.5A

1 3 0

+1.0VS_VGA 10uF 1uF

PCIE_VDDC 2.5A

BIF_VDDC 1.4A

SPLL_VDDC

100mA

2 (1@) 5 (1@)

0 0 0

1 1 1

+1.5VS_VGA 10uF 1uF

B B

VDDR1 1.5A 3 5 5

+1.8VS_VGA 10uF 1uF

PCIE_PVDD

MPLL_PVDD

SPLL_PVDD 75mA

VDDR4

VDD_CT 13mA

+TSVDD 13mA

C C

+DP_VDDR

+DP_VDDC

100mA

130mA

(300mA)

1 1 1

1 1 1

1 1 1

0 0 0

1 1 1

1 1 1

0 0 0

0 0 0

+3VS_VGA 10uF 1uF

VDDR3 25mA

0

2 (1@)

0.1uF

0

0.1uF

0

0.1uF

0.1uF

0.1uF

1

+1.8VS_ VGA

1 2

BLM15BD 121S N1D_ 0402

SM010009U00

+1.8VS_ VGA

1 2

0 +-5% 0603

SD013000080

L56 PX@

L47 PX@

1

1

C405

C404

2

2

PX@

PX@

1U_0402_6.3V4Z

10U_0603_6.3V6 M

1

1

C406

C407

2

2

PX@

PX@

1U_0402_6.3V4Z

10U_0603_6.3V6 M

D D

SecurityClassification

IssuedDate

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF C OMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE S ECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRA NSFERE D FROM THE CUSTODY OF THE C OMPETEN T DIIIVIIISIIION OF R&D
DEPAR TMENT EXCE PT AS AUTHORIIIZED BY COMPA L ELECTRONIIICS,,, IIINC...NEIIITHER THIIIS SHEET NO R THE IIINFORMATIIION IIIT CONTAIIINS

1 2 3 4

MAY BE U SED B Y OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CON SENT OF CO MPAL ELECTRONIIICS,,,IIINC...

2013/01/11 2013/12/31

Compal SecretData

DeciiipheredDate

Tiiitllle

Siiize Document Numbe r

Custom

Compal Electronics, Inc.

SUN_Power

Date: Wednesday, May 11, 2016 Sheet 39o f 60

LA-D707P

5

Rev

v0.2

1 2 3 4 5

C469

PX@

M_DA[63..0]
M_MA[15..0]
M_DQM[7..0]
M_DQS[7. .0]
M_DQS#[7 ..0]

40.2_0402_1%

100_0402_1%

PX@

R455
10_0402_1%

2 1

1

2

+1.5VS_ VGA+1.5VS_VGA

1

PX@

R365

2

1

PX@

R457

2

PX@

R5161

5.1K_0402_1%

+MVREFSA

1

PX@

C514
1U_0402_6.3V4Z

2

DRAM_RST

1

2

R5162 1 PX@ 2 120_0402 _1%

R460 @ 1
R373 @ 1

Route 50ohms single-ended/100ohm dif f and keep short
debug only, for clock observat i on,if not need, DNI.

2 51.1_0402_1% C542 @1
2 51.1_0402_1% C541 @1 2 L7

M_DA0
M_DA1
M_DA2
M_DA3
M_DA4
M_DA5
M_DA6
M_DA7
M_DA8
M_DA9
M_DA10
M_DA11
M_DA12
M_DA13
M_DA14
M_DA15
M_DA16
M_DA17
M_DA18
M_DA19
M_DA20
M_DA21
M_DA22
M_DA23
M_DA24
M_DA25
M_DA26
M_DA27
M_DA28
M_DA29
M_DA30
M_DA31
M_DA32
M_DA33
M_DA34
M_DA35
M_DA36
M_DA37
M_DA38
M_DA39
M_DA40
M_DA41
M_DA42
M_DA43
M_DA44
M_DA45
M_DA46
M_DA47
M_DA48
M_DA49
M_DA50
M_DA51
M_DA52
M_DA53
M_DA54
M_DA55
M_DA56
M_DA57
M_DA58
M_DA59
M_DA60
M_DA61
M_DA62
M_DA63

+MVREFDA
+MVREFSA

DRAM_RST L10

2 0.1U_0402_16V4Z K8

0.1U_0402_16V4Z

@

U666C

K27

DQA0_0

J29

DQA0_1

H30

DQA0_2

H32

DQA0_3

G29

DQA0_4

F28

DQA0_5

F32

DQA0_6

F30

DQA0_7

C30

DQA0_8

F27

DQA0_9

A28

DQA0_10

C28

DQA0_11

E27

DQA0_12

G26

DQA0_13

D26

DQA0_14

F25

DQA0_15

A25

DQA0_16

C25

DQA0_17

E25

DQA0_18

D24

DQA0_19

E23

DQA0_20

F23

DQA0_21

D22

DQA0_22

F21

DQA0_23

E21

DQA0_24

D20

DQA0_25

F19

DQA0_26

A19

DQA0_27

D18

DQA0_28

F17

DQA0_29

A17

DQA0_30

C17

DQA0_31

E17

DQA1_0

D16

DQA1_1

F15

DQA1_2

A15

DQA1_3

D14

DQA1_4

F13

DQA1_5

A13

DQA1_6

C13

DQA1_7

E11

DQA1_8

A11

DQA1_9

C11

DQA1_10

F11

DQA1_11

A9

DQA1_12

C9

DQA1_13

F9

DQA1_14

D8

DQA1_15

E7

DQA1_16

A7

DQA1_17

C7

DQA1_18

F7

DQA1_19

A5

DQA1_20

E5

DQA1_21

C3

DQA1_22

E1

DQA1_23

G7

DQA1_24

G6

DQA1_25

G1

DQA1_26

G3

DQA1_27

J6

DQA1_28

J1

DQA1_29

J3

DQA1_30

J5

DQA1_31

K26

MVREFDA

J26

MVREFSA

J25

NC#J25 CSA1B_1

K25

MEM_CALR P0

DRAM_RST
CLKTESTA

CLKTESTB

216-0841018 A0 SUN PROS3

U?

WCKA0_0/DQMA 0_0

WCKA0B_0/DQMA0_1

WCKA0_1/DQMA 0_2

WCKA0B_1/DQMA0_3

WCKA1_0/DQMA 1_0

MEMORY INTERFACE

WCKA1B_0/DQMA1_1

WCKA1_1/DQMA 1_2

WCKA1B_1/DQMA1_3

DDBIA0 _0/QSA 0_0B
DDBIA0 _1/QSA 0_1B
DDBIA0 _2/QSA 0_2B
DDBIA0 _3/QSA 0_3B
DDBIA1 _0/QSA 1_0B
DDBIA1 _1/QSA 1_1B
DDBIA1 _2/QSA 1_2B
DDBIA1_3/QSA1_3B

?

GDDR 5/D DR3G DDR5 /DDR 3

MAA0_0/MAA_ 0
MAA0_1/MAA_ 1
MAA0_2/MAA_ 2
MAA0_3/MAA_ 3
MAA0_4/MAA_ 4
MAA0_5/MAA_ 5
MAA0_6/MAA_ 6

MAA0_7/MAA_ 7
MAA0_8/MAA_ 13
MAA0_9/MAA_ 15

MAA1_0/MAA_ 8

MAA1_1/MAA_ 9
MAA1_2/MAA_ 10
MAA1_3/MAA_ 11
MAA1_4/MAA_ 12

MAA1_5/MAA_ BA2
MAA1_6/MAA_ BA0
MAA1_7/MAA_ BA1

MAA1_8/MAA_ 14

MAA1_9/RSVD

EDCA0 _0/Q SA0 _0
EDCA0 _1/Q SA0 _1
EDCA0 _2/Q SA0 _2
EDCA0 _3/Q SA0 _3
EDCA1 _0/Q SA1 _0
EDCA1 _1/Q SA1 _1
EDCA1 _2/Q SA1 _2
EDCA1_3 /QSA 1_3

ADBIA0/ODTA0
ADBIA1/ODTA1

CLKA0

CLKA0B

CLKA1

CLKA1B
RASA0B

RASA1B
CASA0B

CASA1B

CSA0B_0
CSA0B_1

CSA1B_0

CKEA0
CKEA1

WEA0B
WE A1B

K17 M_MA0
J20 M_MA1
H23 M_MA2
G23 M_MA3
G24 M_MA4
H24 M_MA5
J19 M_MA6
K19 M_MA7
G20 M_MA13
L17 M_MA15

J14 M_MA8
K14 M_MA9
J11 M_MA10
J13 M_MA11
H11 M_MA12
G11 M_BA2
J16 M_BA0
L15 M_BA1
G14 M_MA14
L16

E32 M_DQM0
E30 M_DQM1
A21 M_DQM2
C21 M_DQM3
E13 M_DQM4
D12 M_DQM5
E3 M_DQM6
F4 M_DQM7

H28 M_DQS0
C27 M_DQS1
A23 M_DQS2
E19 M_DQS3
E15 M_DQS4
D10 M_DQS5
D6 M_DQS6
G5 M_DQS7

H27 M_DQS#0
A27 M_DQS#1
C23 M_DQS#2
C19 M_DQS#3
C15 M_DQS#4
E9 M_DQS#5
C5 M_DQS#6
H4 M_DQS#7

L18 VR AM_ODT0
K16 VRAM_ODT1

H26 M_CLK0
H25 M_CLK#0

G9 M_CLK1
H9 M_CLK#1

M_RAS#0

G22

M_RAS#1

G17

M_CAS#0

G19

M_CAS#1

G16

M_CS#0

H22
J22

M_CS#1

G13
K13

K20 M_CKE0
J17 M_CKE1

M_WE#0

G25

M_WE#1

H10

M_BA2 <4 1,42>
M_BA0 <4 1,42>
M_BA1 <4 1,42>

VRAM_ODT 0 <41>
VRAM_ODT 1 <42>

M_CLK0 <41>
M_CLK#0 <41>

M_CLK1 <42>
M_CLK#1 <42>

M_RAS#0 <41>
M_RAS#1 <42>

M_CAS#0 <41>
M_CAS#1 <42>

M_CS#0 <41>
M_CS#0_ 1 <41>

M_CS#1 <42>
M_CS#1_ 1 <42>

M_CKE0 <41>
M_CKE1 <42>

M_WE#0 <41>
M_WE#1 <42>

For 512 VRAM 2Rank Colay

For 512 VRAM 2Rank Colay

<41,42> M_DA[63..0]
<41,42> M_MA[15..0]
<41,42> M_DQM[7..0]

40.2_0402_1%

R364

100_0402_1%

<41,42> M_DQS[7.. 0]
<41,42> M_DQS#[7. .0]

1

PX@

R363

2

+MVREFDA

1

1

PX@

PX@

C467
1U_0402_6.3V4Z

2

2

PX@

R5160

49.9_0402_1%

1 2

120P_0402_5 0V8J

Place close to GPU (within 25mm)
and place componment close to each other

A A

B B

<41,42> DRAM_RST#

C C

D D

SecurityClassification

IssuedDate

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF C OMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE S ECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRA NSFERE D FROM THE CUSTODY OF THE C OMPETEN T DIIIVIIISIIION OF R&D
DEPAR TMENT EXCE PT AS AUTHORIIIZED BY COMPA L ELECTRONIIICS,,, IIINC...NEIIITHER THIIIS SHEET NO R THE IIINFORMATIIION IIIT CONTAIIINS

1 2 3 4

MAY BE U SED B Y OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CON SENT OF CO MPAL ELECTRONIIICS,,,IIINC...

2013/01/11 2013/12/31

Compal SecretData

DeciiipheredDate

Tiiitllle

Siiize Document Numbe r

Custom

Compal Electronics, Inc.

SUN_MEM

Date: Wednesday, May 11, 2016 Sheet 40o f 60

LA-D707P

5

Rev

v0.2

1 2 3 4 5

Memory Partition A - Lower 32 bits

M_CLK0
M_CLK#0

2

C506

M_DA[63..0]
M_MA[15..0]
M_DQM[7..0]
M_DQS[7. .0]
M_DQS#[7 ..0]

PX@

R454

240_0402_1%

1

2

4.99K_0402_ 1%

4.99K_0402_ 1%

1

+1.5VS_ VGA

1

PX@

R452

2

+FBA_VREF0 +FBA_VREF1

1

C512

2

1U_0402_6.3V4Z

PX@

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
M_MA14
M_MA15

M_BA0
M_BA1
M_BA2

M_CLK0
M_CLK#0
M_CKE0

VRAM_ODT0 K1
M_CS#0 L2
M_RAS#0
M_CAS#0
M_WE#0

M_DQS2
M_DQS0

M_DQM2
M_DQM0

M_DQS#2 G3

M_DQS#0 B7

VRAM_ODT 0 J1

M_CKE0

1

C511

C519

2

PX@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

1

PX@

R453

0.1U_0402_10V6K

2

2

<40,42> M_BA0
<40,42> M_BA1
<40,42> M_BA2

<40> M_CLK0
<40> M_CLK#0
<40> M_CKE0

<40> VRAM_ODT 0
<40> M_CS#0
<40> M_RAS#0
<40> M_CAS#0
<40> M_WE#0

<40,42> DRAM_RST#

<40> M_CS#0_1

R465 2 PX@ 1 240_0402_1%

PX@

C472

1

C491

2

PX@

10U_0603_6.3V6 M

1

1

C510

2

2

PX@

1U_0402_6.3V4Z

U1406

M8

VREFCA

H1

VREF DQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

ODT/ODT0
CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

DQSL
DQSU

T2

RESET

L8

ZQ/ZQ 0

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

SDRAM DDR3

H5TC2G63FFR -11C_FBGA96

X76@

1

1

C532

C521

2

2

PX@

PX@

PX@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

E3 M_DA17

DQL0

F7 M_DA23

DQL1

F2 M_DA21

DQL2

F8 M_DA22

DQL3

H3 M_DA18

DQL4

H8 M_DA19

DQL5

G2 M_DA16

DQL6

H7 M_DA20

DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

1

1

C480

C520

2

2

@

1U_0402_6.3V4Z

0.1U_04 02_10V6 K

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U1406 side

C481

PX@

0.1U_04 02_10V6 K

D7
C3
C8
C2
A7
A2
B8
A3 M_ DA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

1

2

PX@

M_DA5

M_DA3
M_DA4
M_DA1
M_DA6
M_DA0
M_DA7

+1.5VS_ VGA

240_0402_1%

+1.5VS_ VGA

1

1

1

1

C485

C482

2

2

PX@

PX@

0.1U_04 02_10V6 K

0.1U_04 02_10V6 K

1

C531

C483

C486

2

2

2

@

PX@

PX@

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_04 02_10V6 K

4.99K_0402_ 1%

4.99K_0402_ 1%

1

PX@

R456

2

PX@

R463

PX@ PX@

R464

+1.5VS_ VGA

1

2

1

1

C540

0.1U_0402_10V6K

2

2

R466 2 PX@ 1 240_0402 _1%

U1407

M8

VREFCA

H1

1

1

C498

C499

2

2

PX@

PX@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

VREF DQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

DQSL
DQSU

RESET

L8

ZQ/ZQ 0

NC/ODT1
NC/CS1
NC/CE1

L9

NCZQ1

96-BALL

SDRAM DDR3

H5TC2G63FFR -11C_FBGA96

X76@

1

1

C533

C518

2

2

PX@

PX@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
M_MA14
M_MA15

M_BA0
M_BA1
M_BA2

M_CLK0
M_CLK#0
M_CKE0

VRAM_ODT0 K1
M_CS#0
M_RAS#0
M_CAS#0
M_WE#0

M_DQS3
M_DQS1

M_DQM3
M_DQM1

M_DQS#3 G3
M_DQS#1 B7

DRAM_RST# T2

VRAM_ODT 0 J1
M_CS#0_ 1 L1
M_CKE0 J9

1

1

1

C496

C490

C497

2

2

2

PX@

PX@

PX@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

10U_0603_6.3V6 M

E3 M_DA30

DQL0

F7 M_DA27

DQL1

F2 M_DA31

DQL2

F8 M_DA24

DQL3

H3 M_DA29

DQL4

H8 M_DA26

DQL5

G2 M_DA28

DQL6

H7 M_DA25

DQL7

D7 M_DA8

DQU0

C3 M_DA14

DQU1

C8 M_DA9

DQU2

C2 M_DA12

DQU3

A7 M_DA10

DQU4

A2 M_DA15

DQU5

B8 M_DA11

DQU6

A3

DQU7

M_DA13

PX@

+1.5VS_ VGA

+1.5VS_ VGA+1.5VS_ VGA

+1.5VS_ VGA

1

1

1

1

C477

C476

2

2

PX@

PX@

0.1U_04 02_10V6 K

0.1U_04 02_10V6 K

1

C534

C478

C479

2

2 2

@

PX@

PX@

0.1U_0402_10V6K

0.1U_04 02_10V6 K

0.1U_04 02_10V6 K

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

U1407 side

1

1

1

C516

C475

C474

2

2

2

@

PX@

1U_0402_6.3V4Z

0.1U_04 02_10V6 K

0.1U_04 02_10V6 K

<40,42> M_DA[63..0]

<40,42> M_MA[15..0]

<40,42> M_DQM[7..0]
<40,42> M_DQS[7..0]
<40,42> M_DQS#[7. .0]

A A

B B

C C

40.2_0402_1% 40.2_0402_1%

1

R5171 R5170

PX@ PX@

2

1

PX@

0.01U_0402_25V7K

2

D D

SecurityClassification

IssuedDate

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF C OMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE S ECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRA NSFERE D FROM THE CUSTODY OF THE C OMPETEN T DIIIVIIISIIION OF R&D
DEPAR TMENT EXCE PT AS AUTHORIIIZED BY COMPA L ELECTRONIIICS,,, IIINC...NEIIITHER THIIIS SHEET NO R THE IIINFORMATIIION IIIT CONTAIIINS

1 2 3 4

MAY BE U SED B Y OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CON SENT OF CO MPAL ELECTRONIIICS,,,IIINC...

2013/01/11 2013/12/31

Compal SecretData

DeciiipheredDate

Tiiitllle

Siiize Document Numbe r

Custom

Compal Electronics, Inc.

SUN_VRAM A Lower

Date: Wednesday, May 11, 2016 Sheet 41o f 60

LA-D707P

5

Rev

v0.2

1 2

Memory Partition A - Upper 32 bits

3 4 5

4.99K_0402_ 1%

4.99K_0402_ 1%

1

2

+1.5VS_ VGA

1

PX@

R461

2

1

1

PX@

PX@

R462

C539 M_MA2

0.1U_0402_10V6K M_MA3

2

2

R445 2 PX@ 1 240_040 2_1%

+FBA_VREF3

M_MA0
M_MA1

M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
M_MA14
M_MA15

M_BA0
M_BA1
M_BA2

M_CLK1
M_CLK#1
M_CKE1

VRAM_ODT 1 K1
M_CS#1 L2
M_RAS#1 J3
M_CAS#1
M_WE#1

M_DQS6
M_DQS7

M_DQM6
M_DQM7

M_DQS#6
M_DQS#7

DRAM_RST # T2

VRAM_ODT 1
M_CS#1_ 1
M_CKE1

U1409

M8

VREFCA

H1

VREF DQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

ODT/ODT0
CS/CS0
RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

RESET

L8

ZQ/ZQ 0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

SDRAM DDR3

H5TC2G63FFR -11C_FBGA96

X76@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E3 M_DA49
F7 M_DA53
F2 M_DA51
F8 M_DA54
H3 M_DA50
H8 M_DA55
G2 M_DA4 8
H7 M_DA52

D7 M_DA60
C3 M_DA59
C8 M_DA63
C2 M_DA56
A7 M_DA62
A2 M_DA57
B8 M_DA61
A3 M_DA58

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VS_ VGA

+1.5VS_ VGA

+1.5VS_ VGA

1

PX@

R458

A A

B B

C C

<40,41> M_DA[63..0]
<40,41> M_MA[15..0]
<40,41> M_DQM[7..0]
<40,41> M_DQS[7..0]
<40,41> M_DQS#[7. .0]

M_CLK1
M_CLK#1

1

1

R5173 R5172

40.2_0402_1% 40.2_0402_1%

PX@ PX@

2

2

1

PX@

C507

0.01U_0402_25V7K

2

M_DA[63..0]
M_MA[15..0]

M_DQM[7..0]

M_DQS[7. .0]

M_DQS#[7 ..0]

4.99K_0402_ 1%

4.99K_0402_ 1%

PX@

R410

240_0402_1%

PX@

R459

1

2

2

1

1

PX@

C473 M_MA2

0.1U_0402_10V6K M_MA3

2

2

<40,41> M_BA0
<40,41> M_BA1
<40,41> M_BA2

<40> M_CLK1
<40> M_CLK#1
<40> M_CKE1

<40> VRAM_ODT 1
<40> M_CS#1
<40> M_RAS#1
<40> M_CAS#1
<40> M_WE#1

<40,41> DRAM_RST#

<40> M_CS#1_ 1

R411 2 PX@

+FBA_VREF2

M_MA0
M_MA1

M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
M_MA14
M_MA15

M_BA0
M_BA1
M_BA2

M_CLK1
M_CLK#1
M_CKE1

VRAM_ODT 1 K1
M_CS#1
M_RAS#1
M_CAS#1
M_WE#1

VRAM_ODT 1
M_CKE1

1 240_0402_1%

M_DQS4
M_DQS5

M_DQM4
M_DQM5

M_DQS#4 G3
M_DQS#5 B7

DRAM_RST# T2

U1408

M8

VREFCA

H1

VREF DQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

DQSL
DQSU

RESET

L8

ZQ/ZQ 0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

SDRAM DDR3

H5TC2G63FFR -11C_FBGA96

X76@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E3 M_DA38
F7 M_DA36
F2 M_DA37
F8 M_DA35
H3 M_DA39
H8 M_DA32
G2 M_DA34
H7 M_DA33

M_DA41

D7

M_DA44

C3

M_DA43

C8

M_DA45

C2

M_DA42

A7

M_DA46

A2

M_DA40

B8
A3 M_DA47

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VS_ VGA

+1.5VS_ VGA

PX@

R444

240_0402_1%

U1408 side U1409 side

1

1

1

C525

C495

2

2

PX@

PX@

1U_0402_6.3V4Z

10U_0603_6.3V6 M

D D

1 2 3 4

1

1

C526

C513

C524

2

2

2

PX@

PX@

PX@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

1

C527

2

PX@

1U_0402_6.3V4Z

1

1

C528

C504

C536

2

2

2

@

PX@

PX@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_0402_10V6K

1

1

1

C509

C508

C505

2

2

2

PX@

PX@

0.1U_04 02_10V6 K

0.1U_04 02_10V6 K

0.1U_04 02_10V6 K

+1.5VS_ VGA +1.5VS_ VGA

1

1

1

C523

C500

2

2

PX@

PX@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

1

C538

2

PX@

1U_0402_6.3V4Z

1

C487

C522

C484

C488

2

2

2

@

PX@

PX@

1U_0402_6.3V4Z

0.1U_04 02_10V6 K

0.1U_04 02_10V6 K

0.1U_04 02_10V6 K

PX@

1

1

1

C530

C529

C535

2

2

2

@

PX@

PX@

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_04 02_10V6 K

SecurityClassification

IssuedDate

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF C OMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE S ECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRA NSFERE D FROM THE CUSTODY OF THE C OMPETEN T DIIIVIIISIIION OF R&D
DEPAR TMENT EXCE PT AS AUTHORIIIZED BY COMPA L ELECTRONIIICS,,, IIINC...NEIIITHER THIIIS SHEET NO R THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE U SED B Y OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CON SENT OF CO MPAL ELECTRONIIICS,,,IIINC...

2013/01/11 2013/12/31

1

C501

C492

2

PX@

1U_0402_6.3V4Z

10U_0603_6.3V6 M

1

1

1

C503

C502

2

2

2

PX@

PX@

PX@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

Compal SecretData

DeciiipheredDate

1

1

1

C489

2

0.1U_04 02_10V6 K

PX@

1

C493

C494

C537

2

2

2

@

PX@

PX@

0.1U_0402_10V6K

0.1U_04 02_10V6 K

0.1U_04 02_10V6 K

Tiiitllle

Siiize Document Numbe r

Custom

Compal Electronics, Inc.

SUN_VRAM A Upper

Date: Wednesday, May 11, 2016 Sheet 42o f 60

LA-D707P

5

Rev

v0.2

1

2

PX@

5 4 3 2 1

+19.5V_ADPIN

D D

C C

B B

@ PJP1

ACES_51483-00801-001

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

GND

10

GND

ADP_SIGNAL
Charge_LED
ACIN_LED

2

3

ESD@ PD1

L30ESD24VC3-2_SOT23-3

1

ADP_SIGNAL1 2

2

3

ESD@ PD2

L30ESD24VC3-2_SOT23-3

1

12

EMI@ PC1

PR3
10K_0402_5%

5A_Z120_25M_0805_2P

DISEMI@PL2

5A_Z120_25M_0805_2P

12

EMI@ PC2

100P_0402_50V8J

1

2

EMI@ PL1

1 2

1 2

1000P_0402_50V7K

1

PR5

2

10K_0402_5%

PD3

GLZ3.6B_LL34-2

+19.5V_VIN

@PR1

0_0402_5%

12

12

EMI@ PC4

EMI@ PC3

100P_0402_50V8J

1000P_0402_50V7K

<26> AC_LED#

ADP_ID <26>

12

12

PC6

@ PC5

100P_0402_50V8J

1000P_0402_50V7K

2014-10-06:

Change EC Power Rail Name

+3VALW_EC

1

PR7

16.2K_0402_1%

1 2

PH1
100K_0402_1%_NCP15WF104F03RC

2

<26> BAT_CHG_LED

ECAGND <26>

1 2

1

PR2
100K_0402_5%

2

PR4
2K_0402_5%

1 2 Charge_LED

1

PR6

100K_0402_5%

2

ADP_I <26,47>

1

PR8

5.9K_0402_1%

1 22

PR9
10K_0402_1%

ACIN_LED

VCIN1_PH <26>VCIN0_PH <26>

Initail Recovery

OTP 92 C 56 C

45W UMA 0.65V 0.45V

Initail Recovery

65W DIS 0.95V 0.67V

A A

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5 4 3 2

Compal SecretData

Deciphered Date

2018/10/092015/10/09

Compal Electronics, Inc.

Title

DC Conn

Document Number

Siiize

LA-D707P

Wednesday, May 11,2016

Date: Sheet

1

Rev

45

v0.2

60

of

5 4 3 2 1

EMI@ PL3

D D

@PJPB1

TAITW_PMPCR3-08MLBS1ZZ4H4

GND
GND

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

10

+14.8V_BATT+

PR10
100_0402_5%

1 2

PR11
100_0402_5%

1 2

5A_Z120_25M_0805_2P

5A_Z120_25M_0805_2P

1

EMI@ PC7

1000P_0402_50V7K

2

1 2

EMI@ PL4

1 2

1

EMI@ PC8

0.01U_0402_50V7K

2

EC_SMB_DA1 <26,47>

EC_SMB_CK1 <26,47>

12

+14.8V_BATT

12

1U_0603_25V6

@EMI@ PC9

@EMI@ PC10

1000P_0402_50V7K

+3VL

1

PR13

C C

2

3

ESD@ PD4

L30ESD24VC3-2_SOT23-3

1

PR12

100_0402_5%

1 2

100K_0402_5%

2

2

3

ESD@ PD5

L30ESD24VC3-2_SOT23-3

1

B/I# <26>

B B

A A

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5 4 3 2

Compal SecretData

Deciphered Date

2018/10/092015/10/09

Compal Electronics, Inc.

Title

BATT Conn

Document Number

Siiize

LA-D707P

Wednesday, May 11,2016

Date: Sheet

1

Rev

46

v0.2

60

of

Protection for reverse input

A B C D

Vgs = 20V

D

@ PQ201
2

G

1
2
3

CHG_ACDRV_R

@ PR202

3M_0402_5%

1 2

P1

1

2

@ PR201

1M_0402_5%

1 2

1 1

Need check the SOA for inrush

PQ202

+19.5V_VIN

MDU1512RH_POWERDFN56-8-5

5

4

PC201

2 1

2200P_0402_50V7K

2 2

3 3

0_0402_5%

@ PR204

Vds = 60V
Id = 250mA

S

2N7002KW_SOT323-3

3 1

PC202

2 1

0.1U_0402_25V6

1

PR208

2

2

4.12K_0603_1%

<26> VCIN1_ACOK

Rds(on) typ = 35mohm max max Power loss 0.22W for 90W;0.12W f or 65W syst em
Vgs = 20V
Vds = 30V
ID = 7.7A (Ta=70C)

PQ203

AON7506_DFN33-8-5

1
2
3

1

PR209

4.12K_0603_1%

4

5

+3VL

P2

PC208

PR214

+19.5V_VIN

CSR rating: 1W
VACP-VACN spec < 80.64mV

PR203

0.01_1206_1%

1
2

1

1 2

PC209

0.1U_0402_25V6

2

0.1U_0402_25V6

CHG_ACP

CHG_CMSRC

CHG_ACDRV

2

1

100K_0402_1%

PR218

422K_0402_1%

1 2

4
3

CHG_ACN

+19.5VB

2 1

2 1

1U_0603_25V6

@EMI@ PC226

+19.5V_VIN

3

1

PC210

0.1U_0402_25V6

2

PC212

1 2

1U_0603_25V6K

21

PAD

1

ACN

2

ACP

3

CMSRC

BQ24725ARGRR_QFN20_3P 5X3P5

4

ACDRV

5

ACOK

2 1

1U_0603_25V6

@EMI@ PC228

@EMI@ PC227

EMI@ PL201

1UH_2.8A_30%_4X4X2_F

1 2

Isat: 4A
DCR: 27 mohm

VF = 0.5 V

2

PD201
BAS40CW _SOT 323-3

1 1

0.047U_0402_25V7K

1 2

PR206

10_1206_1%

2

CHG_VCC

CHG_LX

19

20

VCC

PHASE

PU201

ACDET6IOUT7SDA

CHG_ACDET

CHG_IOUT

1U_0603_25V6

PC211

CHG_DH

18

HIDRV

8

2 1

PQ205

AON7408L_DFN8-5

CHG_LX

PQ206

AON7408L_DFN8-5

2 1

2 1

@EMI@ PC233

1000P_0402_50V7K

CHG_BATDRV

7X7X3
Isat: 6.5A

DCR: 30mohm

10UH_3.5A_20%_7X7X3_M

1

1 2

2

@EMI@ PC234

1000P_0402_50V7K

PL202

1 2 CHG 1

680P_0402_50V7K 4.7_1206_5%

@EMI@PC220 @EMI@ PR211

2 1

2 1

1U_0603_25V6

@EMI@ PC229

PR207

2

2.2_0603_5%

CHG_REGN

CHG_BST 2

1

16

17

BTST

BATDRV

SCL9ILIM

10

2

2 1

2 1

1U_0603_25V6

@EMI@ PC230

1

VF = 0.37V

1

PD202
RB751V-40_SOD323-2

1U_0603_25V6K

REGN

LODRV

GND

SRP

SRN

CHG_ILIM

1

PR217

100K_0402_1%

1U_0603_25V6

1U_0603_25V6

@EMI@ PC232

@EMI@ PC231

CHG_B+

PC204

PC203

2 1

10U_0805_25V6K

2

Rds(on) = 30mohm max
Vgs = 20V
Vds = 30V
ID = 7A (Ta =70C)

CHG_DH 1 2

1 2

PC213

15 DL_CHG

14

10_0603_1%

13 CHG1_SRP 2 CHG_CSOP1

6.8_0603_1%

12 CHG1_SRN 2 CHG_CSON1

11 CHG_BATDRV

620K_0402_1%

1 2

PC222

2 1

0.01U_0402_50V7K

2 1

10U_0805_25V6K

@PR215

0_0402_5%

PR212

PR213

PR216

2 1

EMI@ PC206

2200P_0402_50V7K

@EMI@PC205

4

4

2 1

PC221

.1U_0402_16V7K

+3VL

0.1U_0402_25V6

5

321

5

321

2 1

2 1

@EMI@ PC236

@EMI@ PC235

1000P_0402_50V7K

1000P_0402_50V7K

AON7506_DFN33-8-5

1 2CHG_BATDRV_R

PR205

4.12K_0603_1%

0.01_1206_1%

2

PC216

2 1CHG_CSOP1

0.1U_0402_25V6

2 1

2 1

@EMI@ PC239

@EMI@ PC238

@EMI@ PC237

1000P_0402_50V7K

Support max charge 3.5A
Power loss: 0.245W
CSR rating: 1W
VSRP-VSRN spec < 81.28mV

PR210

4

1000P_0402_50V7K

PQ204

4
3

1000P_0402_50V7K

1
2
35

PC207

2 1

0.01U_0402_50V7K

PC217

2 1CHG_CSON1

2 1

0.1U_0402_25V6

Rds(on) = 35mohm max
Vgs = 2 0V
Vds = 30V
ID = 7.7A (Ta=70C)

PC215

PC214

2 1

10U_0805_25V6K

10U_0805_25V6K

+14.8V_BATT

@ PR224

0_0402_5%

1 2

1

PC223

2 1

2200P_0402_50V7K

12

PC224

PR222

2

66.5K_0402_1%
100P_0402_50V8

J

PR223

0_0402_5%

1 2

Vin Dectector

4 4

L-->H
H-->L

VILIM = 20*ILIM* Rsr
ILIM = 3.3*100/(100+620)/20/0.01

A B C

Min. Typ Max.

17.16V 17.63V 18.12V

16.76V 17.22V 17.70V

= 2.29 A

Security Classification

IssuedDate

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROP ERTY OF COMPAL ELECTRONICS, INC. AN D CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSF ERED FRO M THE CUSTODY OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH OUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/09 2018/10/09

@ PR225

0_0402_5%

1 2

PC225 @

100P_0402_50V8J

2 1

Close EC chip

Compal Secret Data

DecipheredDate

EC_SMB_CK1 <26,46>

EC_SMB_DA1 <26,46>

ADP_I <26,45>

Tiiitllle

Siiize Docume nt Number

Date: Wednesday, May 11, 2016

Compal Electronics, Inc.

CHARGER(BQ24725)

D

Sheet 47 o f 60

Rev

v0.2

5 4 3 2 1

Module model information

RT8243A_V1.mdd

D D

+19.5VB_3V/5V

+19.5VB

C C

@PJB1

1

1 2

JUMP_43X79

+3VALWP

2

+3VALW

PC39

PC33

2 1

2 1

2 1

0.1U_0402_25V6

@EMI@ PC34

1

+

2

2 1

2200P_0402_50V7K

EMI@ PC35

4.7U_0805_25V6-K

PL9

3.3UH_6.3A_20%_7X7X3_M

1 2 LX_3V

PC40

220U 6.3VM_R15

4.7U_0805_25V6-K

4

D1

D110D2/S1

S2

5

2 1 2

680P_0402_50V7K 4.7_1206_5%

1

@EMI@ PC41 @EMI@ PR47

3

2

D1

D1

S2

S2

6

7

<9> SPOK

1

G1

9

G2

PQ7

AON7934_DFN3X3A8-10

8

1 2 1 2BST_3V 7

PC38

0.1U_0402_25V6

Vout=VFB * (1+(R1/R2))
VFB=2V

B B

Vout=2*(1+(13.3K(PR38)/20K(PR40)))
Vout=3.3V

ENLDO threshold ON: 1.2min 1.6typ 2max

<26> EC_ON

OFF: 0.9min 0.95typ 1max

B+ threshold ON: 5.19min 6.92typ 8.65max

VIN rising threshold: 5.1typ 5.5max

falling threshold: 3.5min 4.5max

+3.3VALWP Ipeak=4.26A ; Imax=3A
Delta I=1.92A=>1/2Delta I=0.96A
Rds(on)=15.8m ohm(max) ; Rds(on)=12.4m ohm(typical)
OCP = 5.1A

A A

TDC:4.31A Fsw:37 5KHz
H-MOS PD:0.3736W ∆ T:12℃
L-MOS PD:0.2713W ∆ T:7.9℃
Choke PD:1.5158W ∆ T:24℃
OVP margin for Vos:8% @ 330uF cap, 6% @ 220uF

OFF: 3.89min 4.11typ 4.33max

5 4 3 2 1

<26> MAINPWON

ENTRIPx adjustment range: 0.5V~3V,
floating or over 4.5V will shutdown ch annel.

PR38

13.3K_0402_1%

1 2

PR40

20K_0402_1%

1

PR111

2

10K_0402_1%

PR46

2.2_0603_5%

+19.5VB_3V/5V

1 2

FB=1.98V(Min)

2.006V(Typ)

2.03V(Max)

UG_3V 8

LX_3V

LG_3V 10

499K_0402_1%

1 2

6

BOOT2

9

PHASE2

LGATE2

PR49

2.2K_0402_5%

1 2

@ PR52

0_0402_5%

1 2

402K_0402_1%

PGOOD

UGATE2

PR51

FB_3V

5

FB2

RT8243AZQW_WQFN20_3X3

VIN11ENLDO

2 1

PC45 0.1U_0603_25V7K

PR50

150K_0402_1%

PR53

Security Classification

IssuedDate

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AN D CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSF ERED FRO M THE CUSTODY OF THE COMPET ENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

ENTRIP2

4

2

2

12

PR41 100K_0402_1%

ENTRIP2

PU2

1

ENM

1

1ENTRIP12

12

FB=1.98V(Min)

PR42 56K_0402_1%

PR44 113K_0402_1%

FB_5V

3

1

2

FB1

TON

ENTRIP1

BYP1

BOOT1

UGATE1

PHASE1

LGATE1

ENM13LDO514LDO3

15

ENM

4.7U_0603_10V6K

2 1

12

PC47

4.7U_0603_10V6K

PC48

2 1

4.7U_0603_10V6K

2015/10/09 2018/10/09

PR39
30K_0402_1%

1 2

PR43
20K_0402_1%

1 2

2.006V(Typ)

2.03V(Max)

21

PAD

20

19

18

17

16

+3VLP

PC46

+VLP

Compal Secret Data

PR45 PC37

2.2_0603_5% 0.1U_0402_25V6

BST_5V 1 21 2

UG_5V

LX_5V

LG_5V

@PJP10

JUMP_43X39

1

1

2

@ PJP11

JUMP_43X39

1

2

1 2

DecipheredDate

ENLDO (V)

Low Low X X Off Off Off Off

">1.6V"
=>High
">1.6V"

">2.3V"

=>High

=>High

">1.6V"

">2.3V"

=>High

=>High

">1.6V"

">2.3V"

=>High

=>High

">1.6V"

">2.3V"

=>High

=>High

+19.5VB_3V/5V

2 1

2

Trace width need

meet LDO5 demand

PC36

PC44

2 1

4.7U_0805_25V6-K

4.7U_0805_25V6-K

AON7934_DFN3X3A8-10

Typ: 175m A

+3VL

Rds(on):12.4mΩ ~15.8mΩ

Typ: 225mA

+VL

5V=375KHz 3V=400KHz
(By Rton= 56K ohm)

+5VALWP Ipeak=9.26A ; Imax=6.5A
Delta I=3.483A=>1/2Delta I=1.742A
Rds(on)=15.8m ohm(max) ; Rds(on)=12.4m ohm(ty pical)
OCP =11.11A

TDC:4.9A Fsw:321KHz
H-MOS PD:0.4173W ∆ T:13.4℃

L-MOS PD:0.3442W ∆ T:10℃
Choke PD:1.9613W ∆ T:30℃
OVP margin for Vos:9% @ 330uF cap, 8% @ 220uF

ENTRIP1

ENM (V)

Low X X On On Off Off

1

9

D2/S1

PQ8

8

(V)

ENTRIP2

LDO5 LDO3 +5VALW +3VALW

(V)

Off Off On On Off Off

Off On On On Off On

On On On On On On

On Off On On On Off

Vout=VFB * (1+(R1/R2))
VFB=2V
Vout=2*(1+(30K(PR39)/20K(PR43)))
Vout=5V

3

4

2

D1

D1

G1

G2

10

D1

S2D1S2

S2

7

6

5

+3VALWP +3VALW

+5VALWP +5VALW

PL8

2.2UH_7.8A_20%_7X7X3_M

LX_5V 1 2

1

2 12

@EMI@ PC42 @EMI@ PR48

680P_0402_50V7K 4.7_1206_5%

@PJP2

1

1 2

JUMP_43X118

@PJP3

1

1 2

JUMP_43X118

1

+

PC43

2

220U 6.3VM_R15

2

2

(Vin=12 ~ 25v)

Tiiitllle

Siiize Document Number

Custom

Date:

Compal Electronics, Inc.

3VALW/5VALW

Wedn es day, May 11, 2016

LA-D707P

Sheet 48 o f 60

+5VALWP

Rev

v0.2

5

4

3

2

1

Module model information

RT8207M_V1.mdd For Single layer
RT8207M_V2.mdd For Dual layer

D D

Pin19 need pull separate from +1.35VP.
If you have +1.35V and +0.675V sequence question,

@PJB 2

1

2

+19.5VB

1 2

JUMP_ 43X79

+1.2VP

1

V6M 1V6M 1V6M

2

C C

PC56

22U_0603_6.3

1

2

2

2

PC57

22U_0603_6.3

2 1

PC58

PC59

22U_0603_6.3

22U_0603_6.3V6M

+19.5VB_1.35VP

PC50

PC51

2 1

2200P_0402_50V7K

@EMI@ P C49

4.7_12 06_5%

2 1

10U_0805_25V6K

10U_0805_25V6K

10

2 1 2

1

0.1U_0 603_25V7K

4

1

3

2

D1

D1

D1

G1

9

D1 D2/S1

S2

S2

S2

G2

6

7

5

8

PQ11
AON793 4_DFN3X3A 8-10

Rds(on):12.4mΩ ~15.8mΩ

2 1

PL11

1UH_11 A_20%_7X7X3_ M

1 2LX_1 .35VP

@EMI@ PR5 6

2 1

PC61

PC62

@EMI@ P C64

22U_0603_6.3V6M

680P_ 0402_50V7K

22U_0603_6.3V6M

+1.35VP Ipeak=7.4A ; Im ax=6A
Delta I=2.2A=>1/2Delta I= 1.1A (F=521K Hz)
Rds(on)=15.8m ohm(max) ; Rds(on)=12.4m ohm(typical)

OCP = 8.88

Choke: 7x7x3
Rdc=8.3mohm(Typ), 10mohm(Max)

Switching Frequency: 285kHz
Ipeak=10A
Iocp~13A
OVP: 110%~120%
VFB=0.75V, Vout=1.3545V

2014/1 2/23
change from SUSP# to SM_PG_CTRL

PR54

2.2_06 03_5%

PAD

1U_0402 _6.3V6K

2 1

1 2

LG_1.3 5VP 15

PR55

11.5K_ 0402_1%

1 2CS_1.35VP 13

PC55

1U_0402 _6.3V6K

1 2

VDD_1. 35VP

PC63

PR65

5.1_06 03_5%

1 2

+19.5VB_1.35VP

+2.5V _PG

BST_1.3 5VP_R

PC52

2 1

PR57

5.1_06 03_5%

+5VALW +1.2VP

1 2

@DDR_PWROK

2.5V PG Enable 1.2V

<12,26, 35,4 9> S YSO N

<12,13, 26,3 5> S USP#

<6> SM_PG_CTRL

Mode Level +0.675VSP VTTREF_1.35V
S5 L off off
S3 L off on
S0 H on on

B B

Note: S3 - sleep ; S5 - power off

you can change from +1.35VP to +1.35VS.

BST_1.3 5VP

UG_1.35VP

LX_1.3 5VP

16

18

LGATE

14

PGND

CS

12

VDDP

11

VDD

PR59
470K_ 0402_1%

1 2

1 2

1 2

1 2

@ PR18 15

0_0402_ 5%

1 2

@ PR61

0_0402_ 5%

@ PR62

0_0402_ 5%

@ PR63

0_0402_ 5%

17

PHASE

UGATE

PGOOD

TON

9

10

TON_1.35VP

@

0.1U_0 402_10V7K

PC65

@PC6 6

20

19

21

PAD

VTT

BOOT

S5

8

EN_1.35VP

2 1

0.1U_0402_10V7 K

VLDOIN

VTTGND

VTTSNS

VTTREF

S3

FB

6

7

EN_0.675VSP

12

1

2

3

GND

4

5

VDDQ

PU3
RT8207PGQW_WQFN20_3X3

FB_1.35VP

+1. 2VP

+0. 6VSP

VTTREF_1 .35VP

6.04K_ 0402_1%

1

PR60
10K_0 402_1%

2

PR58

1 2

+1.2VP

2 1

VFB=0.75V

@ PJP4

JUMP_ 43X118

1

1 2

@ PJP5

JUMP_ 43X39

1

1

2

PC53

10U_0603_6.3V6M

2

2

PC54

2 1

10U_0603_6.3V6M

12

PC60

0.033U _0402_16V7K

+1.2VP

0.675Volt +/- 5%
TDC 0.7A
Peak Current 1A

+0.6VSP

Vout=Vref * (1+(R1/R2))
Vref=0.75V
Vout=0.7 5*(1+(6.04K(PR58)/10 K(PR60)))
Vout=1.2V

+1. 2V_V DDQ

+0.6V_0 .6VS

Module model information

SY803 2_V2.m dd

PCM23

PCM24

2 1

22U_0603_6.3V6M

Compal SecretData

JUMP_ 43X39

1

22U_0603_6.3V6M

@ PJM5

2

1 2

+2.5VP

Vout=0.6V * (1+(R1/R2))
Vout=0.6 *(1+(32.4K(PRM23)/10 K(PRM26)) )
Vout=2.5V

Imax= 2A, Ipeak= 3A
FB=0.6V

Vout=0.6V* (1+Rup/Rdown)

2

2018/10/09

Compal Electronics, Inc.

Tiiitttllle

Size Documenttt Number

Custom

1.2VP/0.6VSP/2.5VP(RT8207P/SY8032A)

We dne sd ay , M ay 11, 2016

Re v

Sheettt 49 o fff60Dattte:::

1

v0.2

Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage

+3VALW

@ PRM2 7

0_0402_ 5%

<9,12,26,35> PM_ SLP_S4#

<12,26,35,49> SYS ON

A A

5

1 2

@ PRM2 4

0_0402_ 5%

1 2

@ PJM4

JUMP_ 43X39

1

2

1 2

+3VALW

EN_2.5 V

PRM25

1M_040 2_1%

4

22U_060 3_6.3V6M

1 2

100K_ 0402_5%

Enable 1.2V

2

1

PCM21

1 2

PRM21

PCM25

2 1

@

+2.5V _PG

0.1U_0402_16V7 K

PUM2
SY8032 ABC_SOT23 -6

4

IN

5

PG

GND

6

FB EN

+2.5VP +2.5V

PLM3

LX_2.5V

3

LX

2
1

1UH_2. 3A_+-20%_2. 5X2X1.2_F

1 2

PCM22

@EMI@ P RM22

4.7_04 02_5%

@EMI@ P CM26

680P_ 0402_50V7K

2 1 2

1

3

PRM23

32.4K_ 0402_1%

FB_2.5 V

PRM26

10K_0 402_1%

Securiiity Clllassifiiicatiiion

Issued Date

THIIIS SHEET O F ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMP AL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE S ECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFER ED FRO M THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D
DEPARTMENT E XCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NO R THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD P ARTY WIIITHOUT PRIIIOR WRIIITTEN C ONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2 1

2 1

68P_0402_50V8J

Rup

1 2

1

Rdo wn

2

2015/10/09 DeciiipheredD ate

A

1 1

B

C

D

+3V_PRIM

1

2

BST_1V
LX_1V

FB_1V
LDO3V_1V

PR611
100K_0402_5%

EMI@ PL1207

5A_Z120_25M_0805_2P

+19.5VB

<51> +1.8V_PG

2 2

EN :H>0.8V ; L<0.4V

EN pin don't floati ng
If have pull down resistor at HW side,

please delete PR60 1.

3 3

1 2

@ PR603

0_0402_5%

1 2

PC606

2 1

2 1

0.1U_0402_25V6

EMI@ PC604

@EMI@ PC605

2200P_0402_50V7K

12

@PC601

PR601

0.1U_0402_25V6

2

1M_0402_1%

1

The current limit is set to 6A, 9A or 12A whe n this pin
is pull low, floating or pull high.

+3VALW

12

0_0402_5%

1

@ PR609

0_0402_5%

2

@ PR607

10U_0805_25V6K

2 1

+19VB_1V

PC607

2 1

10U_0805_25V6K

+3VALW

EN_1V
ILMT_1V 13

2

4 IN

5 IN
7

8
18
11

ILMT

15

12

PC614
1U_0402_6.3V6K

PU601

IN

IN

GND

GND
GND
EN

BYP

SY8286RAC_QFN20_3X3

VCC

PAD

PG

NC

NC

NC

9
13

BS

6

LX

19

LX

20

LX

14

FB

17

10

12

16

21

Confirm HW side

+1.0V_VS_PG_PWR <26>

@PR606

0_0402_5%

1 2

1

PC613

2.2U_0402_6.3V6M

2

BST_1V_R1 2

PC603

0.1U_0201_10V6K

+1.0V_PRIM

@EMI@ PR605

4.7_1206_5% 680P_0603_50V7K

1

2 SNUB_1V 1 2

(Common Part SH00000YE00)

PL602

3
4 1

1UH_11A_20%_7X7X3 _M

2

FB=0.6V

@EMI@ PC602

1

R1

PR608

14K_0402_1%

2

1

PR610

R2

20K_0402_1%

2

Vout=0.6V* (1+R1/R2)

1

PC615

PC616

2 1

@ @

2

22U_0603_6.3V6M

PC608

2 1

2 1

330P_0402_50V7K

PC610

PC609

2 1

2 1

22U_0603_6.3V6M

22U_0603_6.3V6M

PC617

2 1

@ @

22U_0603_6.3V6M

22U_0603_6.3V6M

PC611

PC612

2 1

22U_0603_6.3V6M

22U_0603_6.3V6M

=0.6*(1+(14K(PR608)/20K(PR610)))

Vout=1.0V

PC618

2 1

22U_0603_6.3V6M

4 4

Security Classification

IssuedDate

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROP ERTY OF COMPAL ELECTRONICS, INC. AN D CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSF ERED FRO M THE CUSTODY OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH OUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/09 2018/10/09

Compal Secret Data

DecipheredDate

C

Tiiitllle

Siiize Docume nt Number

Custom

Date: Wednesday, May 11, 2016

1.0VS(SY8286)

D

Sheet 50 o f 60

Rev

v0.2

5

D D

@PJB4

+3VALW

C C

2015/01/06
PGOOD from +3VS

change to +3V_PRIM

<13,26,35> PCH_PWR_EN

+3V_PRIM

<50> +1.8V_PG

1 2

@ PR94

0_0402_5%

2014/12/13
change net name to PCH_PWR_EN

JUMP_43X39

1

EN_1.8V

1 2

2

1

PC94

22U_0603_6.3V6M

1 2

2

1 2

PR1814

100K_0402_5%

1

PR9

2

5

1M_0402_1

%

4

PU6

SY8032ABC_SOT23-6

IN_1.8V 4

@ PC98

0.1U_0402_16V7

K

IN LX

5

PG GND

6 1

FB EN

LX_1.8V

3

2

3 2 1

Imax= 2A, Ipeak= 3A
FB=0.6V

PL15

1UH_2.8A_30%_4X4X2_F

1 2

@EMI@

1

PR93

4.7_0603_5%

2

SNUB_1.8V

@EMI@

PC99

680P_0402_50V7K

2 1

20K_0402_1%

FB_1.8V

10K_0402_1%

PR92

PR96

1

Rup

2

1

Rdown

2

+1.8VSP +1.8V_PRIM

+1.8VSP

1

1

12

PC97

PC96

PC95

68P_0402_50V8

J

2

2

22U_0603_6.3V6

22U_0603_6.3V6

M

M

Vout=0.6V * (1+(R1/R2))
Vout=0.6*(1+(20K(PR92)/10K(PR96)))

Vout=1.8V

@PJP9

1

1 2

JUMP_43X79

2

Note:
When design Vin=5V, please stuff snubber

B B

to prevent Vin damage

Vout=0.6V* (1+Rup/Rdown)

A A

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2015/10/09 2018/10/09

3 2

Compal Secret Data

DecipheredDate

B

Title

Size

Date:

Compal Electronics, Inc.

1.8VS(SY8032A)

Document Number

LA-D707P

Sheet 51 of

1

Rev

v0.2

60

1 2 3 4 5

PR1101=2*PR1106/(10*IOUTmax*Load line) RIccMAX2ph(PR1104)= (IccMAX2Ph+32)*200kohm / 127
U22 Iout@GT=31A
PR1101=25.5kohm

PR1106=Iout limit*Load line/10
U22 OCP@GT=40A
PR1106=12.4kohm

A A

program IccMax_2p h

DIFFOUT_GT

1

PR1104

100K_0402_1%

B B

<52,53> SW N1_GT

C C

D D

PR1103

2

1

2

649_0402_1

%

2 1 2

1

PC1102 PR1102

FB_GT

2 1

PC1103

2 1 2 1

PC1104 PR1105

COMP_GT

Place
close

3300P_0402_25V7K 4.7K_0402_1%

to PL1203

PH901

220K_0402_5%_B25/50 4700K

PR1109

84.5K_0603_1%

1 2

<52,53> SW N1_GT

<53> CSN1_GT

2014/12/24
PR1243 change to 1k ohm

472mV/120uA=3.933K
Act i ve Poi nt 110 degr eeC = 4. 206K

1 2 3 4 5

U22 IccM AX@GT= 31A
PR1104= 100K

Load line=(PR1108+(PR1107+PH901/(PR1107*PH901)))* Iout tltal*DCR/PR1109
U22 Load line@GT= 3.1m

PR1109 , PR1110@GT =84.5K

close to CPU

PR1154

470P_0402_50V7K49.9_0402_1%

15P_0402_50V8

J

12

CSCOMP_GT_R

Place
close
to PQ1201

<12> VSSSA_SENSE

<12> VCCSA_SENSE

<14> VCCGT_SENSE

<14> VSSGT_SENSE

1

PR1107
75K_0402_1%

1 2

PR1108
165K_0402_1%

2

PR1111

2K_0402_1%

1 2

PR1112Place close to PL1203

10_0402_1%

1 2

+5VS

PR1243

1K_0402_1%

1 2

PH1102

100K_0402_1%_B25/50

4250K

+VCC_SA

2 1

PC1108

33P_0402_50V8

1

PR1115

1.07K_0402_1%

2

TSENSE_GT_R

2 1

+VCC_GT

2 1

J

12

PC1110

0.1U_0402_25V6

TSENSE_GT

PR1116

61.9K_0402_1%

2

1

100_0402_1%

1 2

1 2

PR1153

100_0402_1%

close to CPU

PR1159
100_0402_1%

1 2

close to CPU

PR1160
100_0402_1%

1 2

close to CPU

1 2

PR1106

12.4K_0402_1%

7

PC1107

820P_0402_25V

2 1

PC1109

0.01U_0402_50V7

K

CSP1_GT

CSREF_GT

CSP2_GT

NCP81206 Operat i ng Fr equency Rosc=21. 5K I/A

and GT are around 450KHz and SA is 600KHz

IccMAX@SA= 5A

PR1123= 11K

Refer IccMAX table in datasheet

IccMAX@VCORE= 28A

RIccMAX@VCORE= 24.9K

Refer IccMAX table in datasheet

@ PR1152

0_0402_5%

1 2

1000P_0402_50V7K

1 2

@ PR1151

0_0402_5%

@ PR1157

0_0402_5%

1 2

1000P_0402_50V7K

1 2

@ PR1158

0_0402_5%

25.5K_0402_1%

1 2

470P_0402_50V8J

PC1112

0.1U_0402_25V

6

+19VB_CPU

1K_0402_1%

1 2

<53> BST1_GT

<53> UG1_GT
<53> LX1_GT
<53> LG1_GT

PC1137

PR1101

PC1101

1 2 IOUT_GT

2 1

PR1117

2200P_0402_50V7K

2 1

1000P_0402_50V7K

12

PC1139

DIFFOUT_GT
FB_GT
COMP_GT
ILIM_GT
CSCOMP_GT
CSSUM_GT
CSREF_GT
CSP2_GT
CSP1_GT
TSENSE_GT

PC1113

0.01U_0402_50V7

K

@ PC1136

1 2

PR1150

0_0402_5%

1 2

PR1149

1.78K_0402_1%

1 2

PC1135

1 2

PR1156

1.24K_0402_1%

1 2

1 2

PC1138

3300P_0402_50V7-K

VRMP

CPUcore_VCC

1 2

2 1

PC1114

1U_0603_10V6

K

PC1134

15P_0402_50V8

2 1 2 1

PC1133 PR1148

0.015U_0402_25V7K 1.5K_0402_1%

PR1155

20K_0402_1%

1 2

VSP_GT

1

IOUT_2ph

2

DIFFOUT_2ph/ICCMax_2ph

3

FB_2ph

4

COMP_2ph SDIO

5

ILIM_2ph

6

CSCOMP_2ph

7

CSSUM_2ph

8

CSREF_2ph

9

CSP2_2ph

10

CSP1_2ph

11

TSENSE_2ph

12

VRMP VSP_1a

13

VCC TSENSE_1ph

PSYS_MON

VSN_GT

A

VSP_S

53

52515049484746454443424140

h

EPAD

VSP_2p

VSN_2p

h PSYS

BST1 HG1

SW1

14151617181920212223242526

+5VS

1 2

PR1118

2.2_0603_5%

+5VS

PR1120

21.5K_0402_1

%

2 1

PC1116

1

2

2.2U_0603_10V6

K

RDRPSP(PR1149)= Load line*(PR1146+PH1105+P R1145)/(gm * DCR) /(PH1105+PR1145)
Load line@SA= 10.3m

gm=1mS
PR1149=1.78K

RLIMSP(PR1147)= 1.3V/(gm*(PH1105+PR1145)*Io utLIMIT*DCR/(PR1146+PH1105+PR1145))
OCP@SA = 9.6A
gm=1mS
PR1147=24 K

RIOUTSP(PR1144)= 2V/(gm*(PH1105+PR1145)*ICCMAX*DCR/(PR1146+PH1105+PR 1146))
IOUTSP@SA= 5A
gm=1mS
PR1144=69.8K

Place
close

to PL1206

11 2

PH1105

2 1

PR1145

12K_0402_1%

K

PC1119

BST_CORE <53>
UG_CORE <53>
LX_CORE <53>
LG_CORE <53>

100K_0402_1%_B25/50 4250K

CSN_SA_R

PR1146

7.5K_0603_1%

2

1 2

PR1143
10K_0402_1%

1 2

@ PR1142

0_0402_5%

1 2

PR1141=43.2k for debug

12

2 1

2 1

PR1147

PC1132

24K_0402_1

%

J

VSN_S

VSP_1b

LG1/ROSC

12

2 1

1000P_0402_50V7

K

A

VR_PWRGD_R

ILIM_SA

CSN_SA

CSP_SA

IOUT_S

A

COMP_SA

b

b

b

VSN_1

CSP_1

ILIM_1b

IOUT_1

CSN_1b

COMP_1

PVCC

LG2/ICCMAX_1

a SW2

HG2

BST2

LG3/ICCMAX_1

b SW3

HG3

BST3

1 2

PR1123

11K_0402_1%

N27484288

PR1121

29.4K_0402_1%

RDRPSP(PR1128)= Load line*(PR1136+PH1104+P R1135)/(gm * DCR) /(PH1104+PR1135)
Load line@VCORE= 2.1m

gm=1mS
PR1128=2.1K

RIOUTSP(PR1137)= 2V/(gm*(PH1104+PR1135)*ICCMAX*DCR/(PR1136+PH1104+PR 1135))
IOUTSP@VCORE= 28A
gm=1mS
PR1137=64.9K

RLIMSP(PR1134)= 1.3V/(gm*(PH1104+PR1135)*Io utLIMIT*DCR/(PR1136+PH1104+PR1135))
OCP@VCORE= 35A
gm=1mS
PR1134=33.2K

2 1

PC1130

PC1131

1000P_0402_50V7

K

0.01U_0402_50V7

PC1129

470P_0402_50V8J

1 2

PR1144

69.8K_0402_1%

1 2

VR_ON_R

b

Y EN

VR_RD

39

DRON

SCLK_CORE

38

SCLK

ALERT#_CORE

37

ALERT#

VR_HOT#

IOUT_1a

CSP_1a
CSN_1a

ILIM_1a

COMP_1a

VSN_1a

PU1101
NCP81206MNTXG_QFN52_6X6

SDIO_CORE

36

VR_HOT_CORE

35

PWM/ADDR_VBOOT

IOUT_CORE

34

CSP_CORE

33

CSN_CORE

32

ILIM_CORE

31

COMP_CORE

30

VSN_CORE

29

VSP_CORE

28

TSENSE_CORE

27

0.1U_0402_25V6

+3VS

PR1141

51.1K_0402_1%

1 2

PR1137

52.3K_0402_1%

1 2

PC1128

82P_0402_50V8J

1 2

CSN_SA <53>

SWN_SA <53>

VR_PWRGD <26>

VR_ON <26,35>

PWM_SA <53>
DRON <53>

1000P_0402_50V7K 2.1K_0402_1%

TSENSE_CORE

1.07K_0402_1%

PR1126

61.9K_0402_1%

+1.0V_VCCST

PR1139

PR1164

49.9_0402_1%

1 2

@ PR1165

0_0402_5%

1 2

PR1163

10_0402_1%

1 2

12

1 2 1 2

PC1124 PR1133

8200P_0402_25V7K2.49K_0402_1%

1 2

PC1123
15P_0402_50V8J

PC1120

2200P_0402_50V7K

1 2

1 2

PR1127

1K_0402_1% PC1122

PR1128

2.1K_0402_1%

1 2

1 2 1

PC1121 PR1242

1

PR1125

2

TSENSE_CORE_R

1

2

2

2 1

45.3_0402_1

%

2 1

@ PR1140

1 2

100_0402_1%

PC1126

0.01U_0402_50V7

K

2

PR1138

2

1

110_0402_1

%

PR1161

2 1

PC1127

0.022U_0402_25V7

1000P_0402_50V7K

2 1

100_0402_1

1 2

1 2

PC1105

499_0402_1

%

2

1

2 1

VR_HOT#

%

@ PR1162

SOC_SVID_CLK <14>

SOC_SVID_ALERT#_R <14>

SOC_SVID_DAT <14>

VR_HOT# <26>

1 2

PR1136

7.5K_0603_1%

PR1135

12K_0402_1%

CSN_CORE_R

1 2

1

PH1104
100K_0402_1%_B25/50 4250K

Place

K

close

2

to PL1205

1 2

PC1125

1000P_0402_50V7K

1 2

PR1134

28K_0402_1%

@ PR1129

0_0402_5%

@ PR1130

0_0402_5%

0.1U_0402_25V

6

2015/01/05
change PR1141 from 51.1k to

43.2k, to set the Vboot voltage
from 0V to 1.2V

SWN_CORE <53>

CSN_CORE <53>

PR1131

100_0402_1%

1 2

close to CPU

PR1132

100_0402_1%

1 2

+VCC_CORE

close to CPU

472mV/120uA=3.933K Act i ve Poi nt 110 degr eeC = 4. 206K

1

Place
close

PH1103

to PQ1205

100K_0402_1%_B25/50

4250K

Tiiitttllle

VCC_CORE_U22(NCP81206)

Siiize DocumentttNumber

Dattte::: Wednesday, May 11,2016 Sheettt 52 o fff60

VSSSENSE <14>

VCCSENSE <14>

Rev

v0.2

1 2 3 4 5

Input Capacitor:
10uF_0805_X5R_25V

5

A A

B B

C C

D D

<52> UG1_GT

PR1119

2.2_0603_5%

1

<52> BST1_GT

<52> LX1_GT

<52> LG1_GT

<52> UG_CORE

<52> BST_CORE

<52> LX_CORE

<52> LG_CORE

<52> PWM_SA

<52> DRON

+5VS

PC1242

2.2U_0603_10V6K

2014/12/31
change PU1502 VCC pin from +5VALW to +5VS

2 BST1_GT_R

0.22U_0603_25V7K

PR1124

2.2_0603_5%

1

2 BST_CORE_R

0.22U_0603_25V7K

2.2_0603_5%

1 2

NCP81253MNTBG_DFN8_2X2 0.22U_0603_25V7K

1 BST DRVH
2 PWM SW
3 EN GND

4

VCC DRVL

2 1

4

321

12

PC1115

5

4

321

5

4

321

12

PC1118

LX_CORE

5

4

321

PR1241

PU1502 PC1241

9

8

7
6

5 LG_SA

PAD

2 1

PQ1201

PQ1202

PQ1205

PQ1206

2 1

PC1201

10U_0805_25V6

MDU1516URH_POWERDFN56-8-5

LX1_GT

AON6794_DFN5X6-8-

5

2 1SNUB1_GT2

1

@EMI@ PC1210 @EMI@ PR1210

InputCapacitor:
10uF_0805_X5R_25V

2 1

MDU1516URH_POWERDFN56-8-5

1

AON6794_DFN5X6-8-

5

2 1SNUB_COR2E

680P_0603_50V7K

@EMI@ PC1230 @EMI@ PR1230

LG_SA8

UG_SA

LX_SA

K

2 1

2 1

PC1202

10U_0805_25V6

K

0.24UH_22A_+-20%_7X7X3_M

1 4
2 3

680P_0603_50V7K 4.7_1206_5%

K

2 1

PC1222

PC1221

10U_0805_25V6

10U_0805_25V6

0.24UH_22A_+-20%_7X7X3_M

1 4
2 3

4.7_1206_5

%

5

S2

6

S2

7

S2

G2

2 1

PC1204

PC1203

10U_0805_25V6

10U_0805_25V6

K

PL1203

K

2 1

2 1

PC1223

10U_0805_25V6

K

PL1205

10

4

D1

D1

3

D1

2

D1

1UG_SA

G1

D2/S1

PQ1207

9

AON7934_DFN3X3A8-10

2 1

K

0.24uH (DCR 1.19 +-5%)

PC1224

+19VB_CPU

1

+

2 1

PC1205

2

0.1U_0402_25V

6

EMI@ PC1385

2200P_0402_50V7

K

@EMI@ PC1384

+VCC_GT

Choke 0.24uH SH000010N00

K

2 1

2 1

0.1U_0402_25V

6

10U_0805_25V6

EMI@ PC1386

2200P_0402_50V7

K

@EMI@ PC1387

+VCC_CORE

0.24uH (DCR 1.19 +-5%)

Choke 0.24uH SH000010N00

Input Capacitor:
10uF_0805_X5R_25V

12

2 1

PC1231

10U_0805_25V6

K

Choke 0.47uH SH000015M00

0.47uH (DCR 6.2 +-5%)

2 1SNUB_S2A 1

680P_0603_50V7K 4.7_1206_5%

@EMI@PC1240 @EMI@PR1240

EMI@ PL1201

5A_Z120_25M_0805_2P

1 2

EMI@ PL1202

5A_Z120_25M_0805_2P

1 2

100U_25V_NC_6.3X

6

GT_CORE
FSW = 450kHz
DCR = 1.19 mohm +/- 5%
TDC@GT_CORE = 18A

H=5.8mm

H/S Rds(on) = 11.7 mohm , 14 m ohm
L/S Rds(on) = 2.7 mohm , 3.3 mo hm

CSN1_GT <52>

SWN1_GT <52>

+19VB_CPU

1

+

PC1225

2

CPU_CORE
FSW = 450kHz

100U_25V_NC_6.3X

6

DCR = 1.19 mohm +/- 5%

TDC@VCC_CORE = 21A

H/S Rds(on) = 11.7 mohm , 14 mohm
L/S Rds(on) = 2.7 mohm , 3.3 mohm

H=5.8mm

CSN_CORE <52>

SWN_CORE <52>

TYP MAX

+VCC_GT

1

+

PC2123

2

+VCC_CORE

1

+

PC1383

2

@

+19VB_CPU

K

2 1

PC1232

10U_0805_25V6

PL1206

0.47UH_MMD05CZR47M_12A_20%

1 4
2 3

Total VCORE Output Capacitor:
4 X 22uF_0603_X5R
4 X 22uF_0603_X5R on CPU back side

K

2 1

@EMI@ PC1389

0.1U_0402_25V6

EMI@ PC1388

+VCC_SA

2200P_0402_50V7

+19.5VB

1

2

1

390U_2.5V_ESR10M_6.3X

6

TYP

330U_D1_2VY_R9

M

MAX

1

+

PC2124

2

390U_2.5V_ESR10M_6.3X

6

SA_CORE
FSW = 450kHz
DCR = 6.2 mohm +/- 5%
TDC@SA_CORE = 4A

H/S Rds(on) = 12.4 mohm , 15.8 m ohm
L/S Rds(on) = 8.4 mohm , 10.3 mo hm

CSN_SA <52>

SWN_SA <52>

2

TYP

Total VCC_GT Output Capacitor:
13 X 22uF_0603_X5R + 1 X 330uF
13 X 22uF_0603_X5R on CPU back side

1

PC1302

PC1301

2

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

PC1311

PC1312

2

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

1

PC1351

2

2

@

22U_0603_6.3V6

M

1

1

PC1361

2

2

22U_0603_6.3V6

M

1

1

PC1303

2

22U_0603_6.3V6

M

1

2

@ PC1313

22U_0603_6.3V6

M

2014/12/25
add 7 pcs 22uF cap for primary side, total 20 pcs

1

PC1352

2

@

22U_0603_6.3V6

M

1

PC1362

2

@

22U_0603_6.3V6

M

1

PC1304

PC1305

2

2

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

1

PC1319

2

2

@ PC1317

22U_0603_6.3V6

M

22U_0603_6.3V6

M

Total VCORE Output Capacitor:
20 X 22uF_0603_X5R + 2 X 330uF
13 X 22uF_0603_X5R on CPU back side.

1

1

PC1353

PC1354

2

2

@

@

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

1

PC1364

PC1363

2

2

@

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

1

PC1307

PC1306

2

2

22U_0603_6.3V6

M

1

1

PC1314

PC1320

2

2

22U_0603_6.3V6

M

1

PC1355

PC1356

2

@

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

PC1366

PC1365

2

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

2

@ @ @ @

2015/5/19
ADD 5pcs cap on +Vcc_IA

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

PC1357

2

@

22U_0603_6.3V6

1

PC1367

2

@

22U_0603_6.3V6

PC2118

22U_0603_6.3V6

M

1

2

1

2

M

M

1

2

+VCC_GT

+VCC_GT <14,52,54>

1

1

PC1308

PC1309

2

2

22U_0603_6.3V6

M

PC1316

22U_0603_6.3V6

M

@ PC1310

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

1

PC1315

PC1318

2

2

22U_0603_6.3V6

M

22U_0603_6.3V6

M

+VCC_CORE

+VCC_CORE <14,52,54>

1

1

1

PC1358

PC1359

2

@

22U_0603_6.3V6

M

1

PC1368

2

22U_0603_6.3V6

M

1

PC2119

PC2120

2

22U_0603_6.3V6

M

22U_0603_6.3V6

M

PC1360

2

2

@

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

1

PC1369

PC1370

2

2

@

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

1

PC2122

PC2121

2

2

@

22U_0603_6.3V6

M

22U_0603_6.3V6

M

MAX

Total VCORE Output Capacitor:
8 X 22uF_0603_X5R
4 X 22uF_0603_X5R on CPU back side

1

1

PC1391

2

22U_0603_6.3V6

M

1

PC1392

PC1393

2

2

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

1

1

PC1396

PC1395

PC1394

2

22U_0603_6.3V6

M

2

2

@

22U_0603_6.3V6

M

2014/12/25
change 3pcs to un-mount

+VCC_SA

+VCC_SA <12,52,54>

1

1

PC1397

PC1398

2

2

@

22U_0603_6.3V6

M

@

22U_0603_6.3V6

M

22U_0603_6.3V6

M

Tiiitttllle

VCC_CORE_PowerStage

Siiize

DocumentttNumber

1 2 3 4 5

Dattte::: Wednesday, May 11,2016 Sheettt 53 o fff60

Rev

v0.2

A

B

C

D

Confirm HW side

1 1

@PJB7

1

2

+19.5VB

DIS@ PRW 5

0,26,38,56> DGPU_PWR_EN

2 2

EN :H>0.8V ; L<0.4V

EN pin don't floating
If have pull down resistor at HW side,

please delete PR601.

22K_0402_5%

1 2

DIS@ PRW 6

1M_0402_1%

1 2

JUMP_43X79

2 1

2 1

0.1U_0402_25V6

@DISEMI@ PCW3

12

@ PRW8

0_0402_5%

1

@DIS@ PRW 9

0_0402_5%

2

DIS@ PCW5

DISEMI@ PCW 2

2200P_0402_50V7K

12

DIS@ PCW12

1

0.1U_0402_25V6

2

The current limit is set to 6A, 9A or 12A when this pin
is pull low, floating or pull high.

+3VALW

10U_0805_25V6K

2 1

+19VB_1.5V

2 1

10U_0805_25V6K

DIS@PCW14

+3VALW

EN_1.5V 11
ILMT_1.5V 13

12

DIS@ PCW 13

1U_0402_6.3V6K

DIS@ PUW1

2

IN

IN

4 IN
5 IN

7

GND

8

18

GND

ILMT

15

BYP

GND

EN

<56> VRAM_PG

SY8286RAC_QFN20_3X3

PG
BS

LX
LX
LX

FB

VCC

NC
NC
NC

PAD

VRAM_PG

9

13
6
19
20

14

17

10
12
16

21

+3VS

BST_1.5V
LX_1.5V

FB_1.5V
LDO3V_1.5V

1

@DIS@ PRW 3

100K_0402_5%

2

@PRW 1

0_0402_5% 0.1U_0201_10V6K

1 2 BST_1.5V_R 1 2

1

DIS@ PCW 11

2.2U_0402_6.3V6M

2

DIS@ PCW 4

@DISEMI@PRW 2

4.7_1206_5% 680P_0603_50V7K

1 2 SNUB_1.5V 1 2

@DISEMI@PCW 1

(Common Part SH00000YE00)

DIS@ PLW 1

3
4 1

1UH_11A_20%_7X7X3_M

2

FB=0.6V

R1

1

DIS@ PRW4

2

1

R2

2

DIS@ PRW7

Vout=0.6 V* (1 +R1/R2)

=0.6*(1+ (15K(PRW4)/10K(PRW7)))

Vout=1.5 V

2 1

15K_0402_1%

10K_0402_1%

2 1

DIS@ PCW6

330P_0402_50V7K

+1.5VRAMP

DIS@ PCW7

22U_0603_6.3V6M

+1.5VRAMP

2 1

2 1

2 1

DIS@PCW10

DIS@ PCW9

DIS@ PCW8

22U_0603_6.3V6M

22U_0603_6.3V6M

@ PJW2

JUMP_43X118

1

2

1

22U_0603_6.3V6M

2

+1.5VS_VGA

3 3

4 4

Security Classification

IssuedDate

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/09 2018/10/09

Compal SecretData

Deciphered Date

C

Compal Electronics, Inc.

Tiiitllle

1.5VS_VGA(SY8286)

Siiize Document Number

LA-D707P

Date: Wednesday, May 11, 2016

D

Sheet

Rev

55

of

v0.2

60

A

<37> VGA_VSSSENSE <37> VGA_VCCSENSE

12

12

@ PRV28

0_0402_5%

1 1

DIS@ PCV87

270P_0402_50V7K

+VGA_VDDIO is pull high at HW Side

2 2

DIS@ PRV51

4.87K_0402_1%

1 2

DIS@ PHV2

100K_0402_1%_B25/50 4250K

PHV2 is next to PLV2

3 3

1

2

VGA_VREF

DIS@ PCV98

0.47U_0402_6.3V6K

<37> +VGA_VDDIO

<36> VGA_PWRGD

<37> GPU_SVC
<37> GPU_SVD
<37> GPU_SVT

2 1

DIS@ PRV47

28.7K_0402_1

%

1

DIS@ PRV55

21.5K_0402_1%

2

12

VGA_IMON

DIS@ PRV43

4.7K_0402_1%

DIS@ PRV73

11K_0402_1%

DIS@ PRV71

64.9K_0402_1%

VGA_SET1 VGA_SET2

DIS@ PRV75

8.66K_0402_1%

Vset1=5*2.8k/(1k+124k+2.8k)=110mV

1 2

1

2

@DIS@ PCV99

.1U_0402_16V7K

@ PRV29

0_0402_5%

DIS@ PRV33

10K_0402_1%

1 2

470P_0402_50V7K

DIS@ PCV93

2.2U_0603_10V7K

1 2

1

VGA_VCC

2

2

31.6K_0402_1%

1 2 1

1 2 1

2

2

1

1

DIS@ PCV88

1 2

2

DIS@ PRV74

1K_0402_1%

DIS@ PRV72

DIS@ PRV76

470_0402_1%

OCP_TDC (Respect to OCP_ SPIKE): 60%

DVID Compensation: 0

RSET:100%

DVID Boost Compensation:22.5mV

B

DIS@ PRV34

200K_0402_1%

1 2

DIS@ PCV89

68P_0402_50V8J

1 2

VGA_VREF 16

@ PRV45 0_0402_5%

1 2
1 2

@ PRV48 0_0402_5%

1 2

@ PRV50 0_0402_5%

VGA_SET1 25
VGA_SET2 26

<26,37> GPU_PROCHOT #

Pull high at HW side

APU_core
TDC 31A(1H1L) *2phase

Peak Current 46.5A
FSW=300kHz
DCR 0.98mohm +/-5%

14

RGND

15

IMON

V064

17 IMONA
18 VDDIO

19

PWROK

20

SVC

21

SVD

22

SVT

23 OFS
24 OFSA

SET1
SET2

LL=1m ohm

VGA_FB

VGA_COMP

13

12

FB

COMP

OCP_L

VCC

272829

VGA_VCC

11

1 VGA_IBIAS

2

VGA_ISEN1P

+5VS

10

987

VSEN

ISEN1P

ISEN3P

ISEN1N

ISEN3N

DIS@ PUV1

RT8880CGQW_WQFN52_6X6

VSENA

IBIAS

COMPA30FBA

ISENA2P

313233

DIS@ PRV60

100K_0402_1%

VGA_ISEN1N

VGA_ISEN2N

6

ISEN2N

ISENA2N ISENA1

34

+5VS

5

ISEN2

VGA_ISEN2P

4

P

363738

@DIS@ PCV102

C

Maximum Current: 28A(TDC)

load line:1m ohm

D

E

slew rate:50mV/uS

DIS@ PRV37

124K_0402_1%

1 2

+5VS

VGA_UGATE2

VGA_BOOT2

VGA_TONSET

1

2

3

PWM3

GND

BOOT2

UGATE2

TONSET

PHASE2
LGATE2

PVCC
LGATE1
PHASE1
UGATE1

BOOT1
LGATEA1
PHASEA1
UGATEA1

BOOTA1

PWMA2

TONSETA

EN

PGOODA

PGOOD

N35ISENA1P

39

1 2

@DIS@ PRV78

0_0402_5%

1 2

@ PRV79

0_0402_5%

2 1

0.1U_0402_25V

6

GPU_B+

VGA_UGATE1

FSW=400kHz

VGA_PHASE1

DIS@ PRV10

2.2_0603_1%

VGA_BOOT1 1 2 VGA_BOOT1-11 2

53
52 VGA_PHASE2

51 VGA_LGATE2

50 VGA_PVCC

49 VGA_LGATE1

48 VGA_PHASE1
47 VGA_UGATE1

46 VGA_BOOT1

45
44
43

42
41

40

<10> GPU_PGD

1 2

DIS@ PRV59

10K_0402_1%

VGA_PVCC

VGA_VCC

+5VS

DIS@ PCV94

2.2U_0603_10V7

K

+3VS

DGPU_PWR_EN <10,26,38,55>

VRAM_PG <55>

DIS@ PRV27

2.2_0603_1%

VGA_BOOT2 1 2 VGA_BOOT2-1

DIS@ PCV9

0.22U_0603_25V7K

2 1

2 1

DIS@ PCV95

DIS@ PRV61

10K_0402_1%

1 2

@ PRV6

0_0603_5%

1 2

DIS@ PQV20

AON6794_DFN5X6-8-5

VGA_LGATE1

DIS@

PRV41

2.2_0402_1%

1 2

1 2

PRV42

2.2_0603_5%

DIS@

2.2U_0603_10V7

K

+3VS

VGA_UGATE2 1 2 4

VGA_PHASE2

1 2

DIS@ PCV26

0.22U_0603_25V7K

5

4

321

5

4

321

+5VS

@PRV67

0_0603_5%

DIS@ PQV22

AON6794_DFN5X6-8-5

VGA_LGATE2 4

DIS@ PQV1

MDU1516URH_POWERDFN56-8-5

DIS@ PCV2

10U_0805_25V6

K

4.7_1206_5%

@DISEMI@ PRV9

VGA_SNB_APU1

1 2

1

2

680P_0603_50V7

K

@DISEMI@PCV12

VGA_ISEN1P

VGA_ISEN1N1 2

5

DIS@ PQV21

321

MDU1516URH_POWERDFN56-8-5

5

321

GPU_B+

2 1

2 1

DIS@ PCV3

10U_0805_25V6

K

DIS@ PLV2

0.22UH_24A_20%_7X7X4_M

1
2

DIS@ PRV44

3.4K_0603_1%

1 2 1 2

DIS@ PCV96

.1U_0402_16V7K

DIS@ PRV53

910_0402_1%

DIS@ PCV103

10U_0805_25V6

1

VGA_SNB_APU2

VGA_ISEN2P

2 1 2

680P_0603_50V7K 4.7_1206_5%

VGA_ISEN2N 1 2

@DISEMI@ PCV107 @DISEMI@ PRV70

@DISEMI@ PCV91

0.1U_0402_25V6

2 1

2 1

4

+VGA_CORE

3

VGA_ISEN1N-1

1

@DIS@ PCV97

0.1U_0402_25V6

2

APU_core
Peak Current 46.5A

FSW=400kHz

DCR 0.98mohm +/-5%

GPU_B+

H/S Rds(on) :8.3mohm ,

L/S Rds(on) :2.3mohm ,

2 1

2 1

DIS@ PCV100

10U_0805_25V6

K

K

DIS@ PLV3

0.22UH_24A_20%_7X7X4_M

1
2

DIS@ PRV69

3.4K_0603_1%

1 2

1 2

DIS@ PCV106

.1U_0402_16V7K

DIS@ PRV77

910_0402_1%

2 1

@PJB8

1

2

1 2

JUMP_43X79

@DISEMI@ PCV4

2200P_0402_50V7K

Maximum Current: 28A(TDC)

load line:1m ohm

1

+

DIS@ PCV1

100U_25V_NC_6.3X6

2

slew rate:50mV/uS

4

+VGA_CORE

3

VGA_ISEN2N-1

@DIS@ PCV108

0.1U_0402_25V6

+19.5VB

10mohm

2.8mohm

Vset2=5*470/(1K+31.6k+470)=71mV

4 4

QRTH (for VDD) :Disable

DVID Compensation : 0

NB OLL Setting :0

OCPTRGDELAY (for VDD/VDDNB) : 40ms

A

Securiiity Clllassifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

B

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,,IIINC...

C

2015/10/09 2018/10/09

Compal SecretData

Deciphered Date

D

Tiiitttllle

Siiize Documenttt Number

Compal Electronics,Inc.

VGA_CORE(RT8880A)

Rev

Sheettt 56 offf 60Dattte::: W ednesday, May 11, 2016

E

v0.2

5 4 3 2 1

VCC_CORE Place on CPU Back Side.
22U_0603 * 13 pcs + 1U_0201*35 pcs

VCC_GT Place on CPU Back Side.
22U_0603 * 13 pcs + 1U_0201*12 pcs

+VCC_GT+VCC_CORE

201 4/12 /25
add 1 pcs 1uF cap f or back side, tot al 13 p cs

D D

C C

B B

1

1

PC2001

PC2002

2

2

22U_0603_6.3V6M

PC2021

PC2022

2 1

2 1

1U_0201_6.3V6M

PC2031

PC2032

2 1

2 1

1U_0201_6.3V6M

PC2076

2 1

2 1

PC2077

1U_0201_6.3V6M

1

1

PC2003

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

2 1

2 1

PC2023

1U_0201_6.3V6M

1U_0201_6.3V6M

2 1

2 1

PC2033

1U_0201_6.3V6M

1U_0201_6.3V6M

2 1

2 1

PC2078

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

PC2004

2

22U_0603_6.3V6M

2 1

PC2024

1U_0201_6.3V6M

2 1

PC2034

1U_0201_6.3V6M

2 1

PC2079

1U_0201_6.3V6M

1

PC2006

PC2005

22U_0603_6.3V6M

PC2025

1U_0201_6.3V6M

PC2035

1U_0201_6.3V6M

PC2080

1U_0201_6.3V6M

PC2007

2

2

22U_0603_6.3V6M

2 1

2 1

PC2027

PC2026

1U_0201_6.3V6M

2 1

2 1

PC2037

PC2036

1U_0201_6.3V6M

2 1

2 1

PC2081

PC2082

1U_0201_6.3V6M

1

1

PC2008

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

PC2028

2 1

2 1

1U_0201_6.3V6M

1U_0201_6.3V6M

PC2038

2 1

2 1

1U_0201_6.3V6M

1U_0201_6.3V6M

PC2083

2 1

2 1

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

PC2009

PC2010

2

2

@

@

22U_0603_6.3V6M

22U_0603_6.3V6M

2 1

PC2030

PC2029

1U_0201_6.3V6M

1U_0201_6.3V6M

2 1

PC2040

PC2039

1U_0201_6.3V6M

1U_0201_6.3V6M

2 1

PC2085

PC2084

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

PC2011

PC2012

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

PC2013

2

@

PC2014

2

@

22U_0603_6.3V6M

22U_0603_6.3V6M

20150324
add 6 pcs cap for transient test

1

1

2

2 1

1

2

@ PC1321

1

PC2042

PC2041

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

2 1

2 1

PC2062

PC2061

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

PC1323

2

2

@ PC1322

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC2043

PC2044

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

2 1

2 1

PC2064

PC2063

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

PC1325

2

2

@ PC1324

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC2045

22U_0603_6.3V6M

PC2065

1U_0201_6.3V6M

22U_0603_6.3V6M

PC2047

PC2046

2

2

22U_0603_6.3V6M

PC2066

PC2067

2 1

2 1

1U_0201_6.3V6M

1

PC1326

2

22U_0603_6.3V6M

1

1

PC2048

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

2 1

2 1

PC2068

1U_0201_6.3V6M

1U_0201_6.3V6M

VCC_SA Place on CPU Back Side.
22U_0603 * 4 pcs + 1U_02 01 * 7 pcs

1

1

PC2049

2

22U_0603_6.3V6M

2 1

PC2069

1U_0201_6.3V6M

1

1

PC2051

PC2050

22U_0603_6.3V6M

PC2070

1U_0201_6.3V6M

PC2052

2

22U_0603_6.3V6M

2 1

PC2071

1U_0201_6.3V6M

PC2053

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

2 1

2 1

PC2072

PC2073

1U_0201_6.3V6M

1U_0201_6.3V6M

+VCC_SA

1

PC2101

2

1

1

PC2102

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

PC2103

PC2104

2

22U_0603_6.3V6M

22U_0603_6.3V6M

+VCC_SA

2 1

PC2086

PC2087

2 1

2 1

1U_0201_6.3V6M

1U_0201_6.3V6M

A A

5 4 3 2 1

2 1

2 1

PC2090

PC2089

PC2088

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/09 2018/10/09

Compal Secret Data

Deciphered Date

2 1

Tiiitllle

Siiize Document Number

Date: Wednesday, May 11, 2016 Sheet

2 1

2 1

PC2112

PC2111

1U_0201_6.3V6M

PC2113

2 1

1U_0201_6.3V6M

1U_0201_6.3V6M

2 1

PC2116

PC2115

PC2114

2 1

1U_0201_6.3V6M

1U_0201_6.3V6M

Compal Electronics, Inc.

VCC_CORE_PROCESSORDECOUPLING

LA-D707P

2 1

PC2117

1U_0201_6.3V6M

1U_0201_6.3V6M

Rev

54

v0.2

60

of

5

+VGA_CORE

4

3

2

1

1

+

DIS@ PCV51

560U_2. 5V_M

D D

2

1

+

DIS@ PCV52

560U_2. 5V_M

2

1

+

DIS@ PCV53

560U_2. 5V_M

2

+VGA_CORE

12

DIS@

PCV54

2.2U_04 02_6.3V6M

12

DIS@

PCV55

2.2U_04 02_6.3V6M

12

DIS@

PCV56

2.2U_04 02_6.3V6M

12

DIS@

PCV57

2.2U_04 02_6.3V6M

12

DIS@

PCV58

2.2U_04 02_6.3V6M

12

DIS@

PCV59

2.2U_04 02_6.3V6M

12

DIS@

PCV60

2.2U_04 02_6.3V6M

12

DIS@

PCV61

2.2U_04 02_6.3V6M

+VGA_CORE

12

C C

DIS@

PCV62

2.2U_04 02_6.3V6M

12

DIS@

PCV63

2.2U_04 02_6.3V6M

12

DIS@

PCV64

2.2U_04 02_6.3V6M

12

DIS@

PCV65

2.2U_04 02_6.3V6M

DIS@

PCV66

2.2U_04 02_6.3V6M122.2U_04 02_6.3V6M

12

DIS@

PCV67

12

DIS@

PCV68

2.2U_04 02_6.3V6M

12

DIS@

PCV69

2.2U_04 02_6.3V6M

+VGA_CORE

12

DIS@

PCV70

10U_0603_6.3V6M

12

DIS@

PCV71

10U_0603_6.3V6M

12

DIS@

PCV72

10U_0603_6.3V6M

12

DIS@

PCV73
10U_0603_6.3V6M

12

DIS@

PCV74

10U_0603_6.3V6M

12

DIS@

PCV75

10U_0603_6.3V6M

12

DIS@

PCV76

10U_0603_6.3V6M

12

DIS@

PCV84

10U_0603_6.3V6M

560u X 3

2.2u X 16
10u X 8
1u X 3

0.1u X 2

B B

+VGA_CORE

12

DIS@

PCV77

1U_0402_6.3V6K

12

DIS@

PCV78

1U_0402_6.3V6K

12

DIS@

PCV79

1U_0402_6.3V6K

12

@DIS@

PCV80
1U_0402_6.3V6K

+VGA_CORE +VGA_CORE

12

DIS@

PCV81

A A

0.1U_04 02_10V7K

12

DIS@

PCV82

0.1U_04 02_10V7K

5

12

@DIS@

PCV83

0.1U_04 02_10V7K

12

@DIS@

PCV85

22U_0603_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CO NTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. TH IS SHEET MAY NOT BE TRANSFERED FROM THE CUSTO DY OF THE COMPET ENT DIVISION OF R &D
DEPART MENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y W ITHOU T PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2015/10/09

3

Compal Secret Data

Deciphered Date

2018/10/09

2

Compal Electronics, Inc.

Tiiitllle

VGA_CORE_CHIPDECOUPLING

Size Document Number

LA-D707P

Date: Wednesday, May 11, 2016

Sheet

Rev

57

1

v0.2

60

of

5 4 3 2 1

D D

C C

B B

A A

Tiiitttllle

Power_PIR(PV)

Siiize

Documenttt Number
LA-D707P

C

Dattte::: Sheettt

5 4 3 2 1

60 o fff60Wednesday, May 11, 2016

Rev

v0.2

5 4 3 2 1

Page# TitleItem

1 52

D D

2 50 Change part number 11/06

3 55 Change part number 11/06

4 48

5 55

6 56

7 56

8 47

9 48

C C

10 49

11 50

12 53

13 55

14 56

15 55

16 53

Change Value

Add Jump

Add Net

pop tounpop
unpop to pop

Add Net and R

Change jump to
ISN choke

colay bead

colay bead

Change jump to
Bead

Change jump to
Bead

colay bead

colay bead

Change R Value
Change C unpop topop

Change Common part

Date

11/06

Request Owner

Power

Power

Power

11/18

11/18

11/18

11/18

11/24

11/24

11/24

11/24

11/24

11/24 Add Bead footprint PL1208

11/24

11/24

11/6

Power

EE

EE

EE

EMI

EMI

EMI

EMI

EMI

EMI

EMI

EE

Power

Issue
Description

(Set VR prochot# from 110C to 120C)

Change from 5x5 choke to 7x7
follow Candy design

Change from 5x5 choke to 7x7
follow Candy design

For easy debug

For VGA CORE sequence and VID error issue

For VGA CORE sequence and VID error issue

For VGA CORE sequence and VID error issue

EMI ISN issue

EMI power noise issue

EMI power noise issue

EMI power noise issue

EMI power noise issue

EMI power noise issue

EMI power noise issue

HW f i net une VRA Mpo wersequence

(Change to Common part)

Solution
Description

Change PR1115 and PR1125 Value 0 ohm to 1.07K ohm

Change PL602 part number from SH00000Z200 to SH00000YE00

Change PLW1 part number from SH00000Z200 to SH00000YE00

+3VL and +VL add Jump

Delete PG pin test point VRAM_PG
Add Net VRAM_PG

PRV61 from unpop to pop
PRV78 and PCV102 from pop to unpop

Add Net VRAM_PG
Add PRV79

Delete jump PJB9
Add ISN choke PL201

Add Bead footprint PL7

Add Bead footprint PL10

Delete jump PJB3
Add Bead PL1207

Delete jump PJB5
Add Bead PL1201 PL1202

Add Bead footprint PL1209 and PL1210

Change PRW5 value from 0 ohm to 22K ohm
Change PCW12 from unpop to pop

(VGA sequence)
Change PC1331 PC1383 PC1390 from SGA20331E10 toSGA00009S00

Rev.

B B

A A

Tiiitttllle

Power_PIR(SI)

Siiize

Documenttt Number
LA-D707P

C

Dattte:::

Wednesday, May 11, 2016

5 4 3 2 1

Sheettt 59 o fff 60

Rev

v0.2

5

4

3

2

1

BOM control

Plat f or m Silego P/N

D D

Intel ULT UMA SLG3NB3455VTR SA00008IQ00 1 1 1

Intel ULT Dis SLG3NB3456VTR SA00008J800 1 1 1 1

Compal PN

25MHz(A) 32.768KHz 24MHz(B) 27MHz 8MHz Remark

X X

X

GCLKUMA@

GCLKPX@

Base on A32 32.768KHz use 10ppm, G-CLK 25MHz X'TAL use 10ppm.

C C

B B

A A

Security Clllassifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

5

4

3

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2013/06/10 2014/07/01

Compal SecretData

Deciphered Date

2

Compal Electronics, Inc.

Tiiitttllle

GCLK

Siiize Document Number

LA-D707P

Dattte::: W ednesday, May 11, 2016

Rev

Sheettt 29 o fff 60

1

v0.2