Compal LA-D591P Schematics Rev2.0

1 1

2 2

Compal Confidential

B3ZMS MB Schematic Document

LA-D591P

3 3

Rev: 2.0

2016.02.24

4 4

DAX1

Part Number

DAA000C2000 PCB 1JL LA-D591P REV0 MB 1

B3ZMS_PCB_REV01

Description

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/21 2016/06/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Cover Sheet

Size Document Number Rev

Custom

B3ZMS LA-D591P

Date: Sheet of

1 45Wednesday, February 24, 2016

2.0

www.vinaﬁx.com

HDMI Conn.

eDP

page 21

1 1

HDMI PS8407A

page 22

DDI2 HDMI x 4 lanes

eDP

DDI

Intel Skylake U

Skylake U Skylake PCH-LP(MCP) (SKL-U_2+2)

NGFF

WLAN

2 2

USB port 5

page 26

PCIe 1.0

2.5GT/s

port 6

Flexible IO

PCIe 1.0

2.5GT/s

port 5

Card Reader

RTS5220

page 26

NGFF2280 SSD

SATA3.0

6.0 Gb/s

port 7 (SATA0)

page 23

Processor

Dual Core + GT2

15W 1356pin BGA

page 06~17

Memory Bus

1.2V lpddr3 1600MHz

USB 3.0 Type-C x1

USB port 3,4

page 25

USBx8

48MHz

HD Audio

SPI

3.3V 24MHz

CH_A CH_B

USB 3.0 conn x2

USB port 1,2

page 24

LPDDR3 Memory down

BlueTooth

USB port 5

page 26

HDA Codec

ALC255

page 26

P.18

P.19

CMOS Camera

USB port 7

page 21

Card Reader

2 in 1 (SD)

3 3

page 26

ENE KB9022/9032

LPC/eSPI BUS

CLK=24MHz

page 27

iTPM

SPI ROM x2

page 8

Int. Speaker UAJ

page 26

Int. MIC

page 26 page 26

on Sub/B

RTC CKT.

page 14

Power On/Off CKT.

page 39

DC/DC Interface CKT.

4 4

Power Circuit DC/DC

page 42

page 43~55

Sub Board

LS-D592P IO/B

page 26

Int.KBD

page 28

Touch Pad

PS2 (from EC) / I2C (from SOC)

Fan Control

page 28

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/21 2016/06/21

Compal Secret Data

Deciphered Date

page 29

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

B3ZMS LA-D591P

2 45Wednesday, February 24, 2016

2.0

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

1 1

100K +/- 5%Ra

0 1 2 3 4 5 6 7

0 0 V 12K +/- 1% 0.347 V 0.345 V 0.360 V 15K +/- 1% 20K +/- 1% 27K +/- 1% 33K +/- 1% 43K +/- 1% 56K +/- 1%

Rb V min

BID

0.423 V 0.430 V 0.438 V

V typ

BID

0 V 0.300 V

BID

max

EC AD3

0x00 - 0x0B 0x0C - 0x1C 0x1D - 0x26 0x27 - 0x300.541 V 0.550 V 0.559 V 0x31 - 0x3B0.691 V 0.702 V 0.713 V 0x3C - 0x460.807 V 0.819 V 0.831 V 0x47 - 0x540.978 V 0.992 V 1.006 V 0x55 - 0x641.169 V 1.185 V 1.200 V

Power State

STATE

S0 (Full ON) ON ON ON ONHIGH HIGH HIGH

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

LOW HIGH

LOWLOW

HIGH

ONONON

OFF

OFFLOW LOW LOW

OFF

BOARD ID Table

Board ID

0 1 2 3 4 5 6 7

PCB Revision

0.1(Skylake)

0.2(Skylake)

1.0(Skylake)

2.0(Skylake)

2.0(Kabylake)

BOM Structure Table

BOM Option Table

Item BOM Structure

Unpop @

CONN@Connector

BOM Option Table

Item BOM Structure

CODEC(ALC255) 255@

CODEC(ALC283) 283@

EMC@EMC requirement @EMC@EMC requirement depop

LPC MODE for EC LPC@

ESPI@ESPI MODE for EC

For Acer IOAC IOAC@ No Acer IOAC NIOAC@

2 2

For Skylake-U SKL@ For Kabylake-U KBL@

8M_SINGLE@SPI ROM 8M*1

TPM TPM@ DMIC*1 1DMIC@ For ES Sampel Only ES@ Keyboard backlight KB@ Finger Print FP@

DRAM BOM Select X76@/X7601@ ~

X7614@

CPU Code

QS:QJ8Q@,QJKK@, QJKR@,QJKP@

MP:SR2EU@,SR2EY@

I2C Address Table

BUS

Device

Address(7 bit)

I2C_0 (+3VS) Reserved (Touch Panel)

0x2CTM-P2969-001 (TP)I2C_1 (+3VS)

3 3

DIMM1

SOC_SMBCLK +3VS DIMM2

0x15SB8787-1200 (TP-ELAN) 0xA0 0xA4

LIS3DHTR(G-Sensor) 0x30

0x9ESOC_SML1CLK +3VS N16S-GT (VGA)

PCH-LP (SOC) 0x90

EC_SMB_CK1 +3VLP

BQ24780 (Charger IC) BATTERY PACK

0x12 0x16

43 level BOM table

431A1MBOL06 431A1MBOL07 431A1MBOL08 431A1MBOL09 431A1MBOL10 431A1MBOL11

4 4

PCBA MB AD591 B3ZMS I36100U SR2EU 4G HDMI PCBA MB AD591 B3ZMS I56200U SR2EY 4GHDMI PCBA MB AD591 B3ZMS I56200U SR2EY 8GHDMI PCBA MB AD591 B3ZMS I76500U SR2EZ 4GHDMI PCBA MB AD591 B3ZMS I76500U SR2EZ 8GHDMI 8M_SINGLE@/EMC@/SKL@/KB@/LPC@/IOAC@/SR2EZ@ SMT MB AD591 B3ZMS PMD4405USR2EX 4G 8M_SINGLE@/EMC@/SKL@/KB@/LPC@/IOAC@/SR2EX@

Address(8bit)

Write Read

BOM Structure43 Level Description

8M_SINGLE@/EMC@/SKL@/KB@/LPC@/IOAC@/SR2EU@ 8M_SINGLE@/EMC@/SKL@/KB@/LPC@/IOAC@/SR2EY@ 8M_SINGLE@/EMC@/SKL@/KB@/LPC@/IOAC@/SR2EY@ 8M_SINGLE@/EMC@/SKL@/KB@/LPC@/IOAC@/SR2EZ@

Voltage Rails

Power Plane Description +19V_VIN +17.4V_BATT Battery power supply N/A +19VB +VCC_CORE +VCC_GT Processor Graphics Power Rails +VCC_SA System Agent power rail +0.6VS_VTT DDR +0.675VS power rail for DDR terminator . +1.0VALW_PRIM +1.0V Always power rail ON +1.0V_VCCSTU Sustain voltage for processor in Standby modes ON +VCCIO CPU IO power rail ON +1.0VS_VCCSTG +1.0VALW_PRIM Gated version of VCCST ON

+1.8VALW_PRIM +1.8V Always power rail +1.5VS System +1.8V power rail ON +3VLP +19VB to +3VLP power rail for suspend power ON +3VALW System +3VALW always on power rail ON +3VS ONSystem +3V power rail +5VALW ON +5VS System +5V power rail +RTCVCC RTC Battery Power ON

Note : ON*1 means power plane is ON only when WOL enable and RTC wake at BIOS setting, otherwise it is OFF.

Adapter power supply

AC or battery power rail for power circuit. Processor IA Cores Power Rail

DDRIIIL +1.35V Power Rail ON+1.2V_VDDQ

+5V Always power rail

S0 N/A

N/A ON ON ON ON

S4/S5

N/AN/A

N/A N/A

N/AN/A OFF OFF OFF

OFF OFF OFF

OFFOFF ON ON*1

OFFON OFF OFF

OFFOFF ON OFF ON

ON*1 OFF

OFF ON

ON ON

ON*1 OFF

OFF ON

OFFOFF ON ON

Skylake CPU

UC1

PMD4405 QJ8Q D0 2.1G BGA

SR2EX@ SA000094270

Kabylake CPU

UC1

QKKQ G0 1.7G FCBGA

QKKQ@ SA00009QM10

UC1

i3-6100U SR2EU D1 2.3G BGA

SR2EU@ SA000092NB0

UC1

QKKS G0 2.4G BGA

QKKS@ SA00009PJ30

UC1

i5-6200U SR2EY D1 2.3G BGA

SR2EY@ SA000092OB0

UC1

i7-6500U SR2EZ D1 2.5G BGA

SR2EZ@ SA000092P90

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/21 2016/06/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Notes List

Size Document Number Rev

Custom

B3ZMS LA-D591P

Date: Sheet of

3 45Wednesday, February 24, 2016

2.0

D D

C C

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFID ENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFID ENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, IN C. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, IN C. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, IN C. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR D ISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELEC TRONICS, INC.

Compal Secret Data

2015/10/21 2016/06/21

Deciphered Date

Compal Electronics, Inc.

Title

Power Map

Size Document Number Rev

Custom

B3ZMS LA-D591P

Date: Sheet of

4 45Wednesday, February 24, 2016

2.0

PWR Sequence_SKL-U2+2_DDR3L_Value_NON CS

+RTCVCC SOC_RTCRST# +19VB

1 1

+3VLP EC_ON +5VALW/+3VALW(+3VALW_DSW...) SPOK tPCH06_Min : 200 us (+3VALW stable (@95% of full value) to +1.0VALW_PRIM starting to ramp) +1.8VALW_PRIM +1.8VALW_PG +VCCPRIM_CORE/+1.0VALW_PRIM EC_RSMRST# ON/OFF PBTN_OUT#

2 2

PM_SLP_S5# ESPI_RST# PM_SLP_S4# SYSON +1.0V_VCCSTU +1.2V_VDDQ PM_SLP_S3# SUSP# +1.0VS_VCCSTG +VCCIO

3 3

+5VS/+3VS/+1.5VS EC_VCCST_PG VR_ON SM_PG_CTRL +0.6VS_VTT +VCC_SA VR_PWRGD PCH_PWROK (SYS_PWROK) H_CPUPWRGD

4 4

PLT_RST# +VCC_CORE / +VCC_GT

tPCH01_Min : 9 ms

tPCH43_Min : 95 ms

tPCH04_Min : 9 ms

tPCH34_Max : 20 ms

tPCH03_Min : 10 ms

Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

tPCH18_Min : 90 us

tCPU04 Min : 100 ns

tCPU10 Min : 1 ms

tCPU00 Min : 1 ms

tCPU19 Max : 100 ns

tCPU18 Max : 35 us

tCPU09 Min : 1 ms

tCPU16 Min : 0 ns tPLT05 Min : Platform dependent

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/21 2016/06/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Power Sequence

Size Document Number Rev

Custom

B3ZMS LA-D591P

Date: Sheet of

5 45Wednesday, February 24, 2016

2.0

SOC_DP1_CTRL_DATA(Internal Pull Down): Display Port B Detected 0 = Port B is not detected. 1 = Port B is detected.

D D

SOC_DP2_CTRL_DATA(Internal Pull Down): Display Port C Detected 0 = Port C is not detected. 1 = Port C is detected.

<HDMI>

+1.0V_VCCST

1 2

RC1 1K_0402_5%

C C

H_THERMTRIP#

SOC_DP2_N0<22> SOC_DP2_P0<22> SOC_DP2_N1<22> SOC_DP2_P1<22> SOC_DP2_N2<22> SOC_DP2_P2<22> SOC_DP2_N3<22> SOC_DP2_P3<22>

SOC_DP2_CTRL_CLK<22>

SOC_DP2_CTRL_DATA<22>

SOC_DP2_N0 SOC_DP2_P0 SOC_DP2_N1 SOC_DP2_P1 SOC_DP2_N2 SOC_DP2_P2 SOC_DP2_N3 SOC_DP2_P3

SOC_DP2_CTRL_CLK SOC_DP2_CTRL_DATA

EDP_COMP

COMPENSATION PU FOR eDP

+1.0VS_VCCIO

1 2

RC3 24.9_0402_1%

CAD note: Trace width=20 mils,Spacing=25mil,Max length=100mils

+1.0VS_VCCSTG

RC6 51_0402_5%DCI@ RC7 51_0402_5%DCI@

B B

A A

RC8 100_0402_1%DCI@ RC10 1K_0402_5%@

+1.0V_PRIM

RC12 51_0402_5%@

RC13 1K_0402_5%@

RC18 51_0402_5%@

RC19 51_0402_1%DCI@

RC20 51_0402_5%@

RC21 0_0402_5%@

12 12 12 12

1 2

EDP_COMP

SOC_XDP_TMS SOC_XDP_TDI SOC_XDP_TDO CPU_XDP_TCK0

XDP_PREQ#

XDP_ITP_PMODE

SOC_XDP_TRST#

CPU_XDP_TCK0

PCH_JTAG_TCK1

CFG3

XDP_PREQ# <12>

XDP_ITP_PMODE <17>

CFG3 <17>

H_PROCHOT#<27>

+3VS

EC_TP_INT#<27,28>

RC42 100K_0402_5%

I2C_TS_INT#

RC47 100K_0402_5%

TP_INT#

+1.0VS_VCCSTG

RC9 1K_0402_5%

H_PROCHOT# H_PROCHOT#_R

CC2 10P_0402_50V8J

@ESD@

D22 RB751V-40_SOD323-2

1 2

RC11 499_0402_1%

1 2

RC149 0_0402_5%@

RC14 49.9_0402_1% RC15 49.9_0402_1% RC16 49.9_0402_1% RC17 49.9_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

UC1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

GPP_E20/DDPC_CTRLCLK

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22

N12

GPP_E23

E52

EDP_RCOMP

SKL-U_BGA1356

H_PECI<27>

I2C_TS_INT#<21>

12 12 12 12

H_PECI

DDI

DISPLAY SIDEBANDS

T3 TP@

T5 TP@ T6 TP@ T7 TP@ T8 TP@

T9 TP@

CC56 10P_0402_50V8J

@ESD@

2015/10/21 2016/06/21

CPU_POPIRCOMP PCH_OPIRCOMP EDRAM_OPIO_RCOMP EOPIO_RCOMP

ESD request

SKL-U

1 OF 20

H_PECI H_THERMTRIP#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3

I2C_TS_INT# TP_INT#

SOC_GPIOB4

Compal Secret Data

Deciphered Date

EDP

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

GPP_E3/CPU_GP0

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

EDP_DISP_UTIL

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

UC1D

CPU MISC

SKL-U_BGA1356

Rev_1.0

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN

EDP_AUXP

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP

RSVD RSVD

SKL-U

4 OF 20

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52 G50

F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

EDP_AUXN EDP_AUXP

SOC_DP2_HPD EC_SCI#

EDP_HPD ENBKL

SOC_BKL_PWM SOC_ENVDD

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

EDP_TXN0 <21> EDP_TXP0 <21> EDP_TXN1 <21> EDP_TXP1 <21> EDP_TXN2 <21> EDP_TXP2 <21> EDP_TXN3 <21> EDP_TXP3 <21>

EDP_AUXN <21> EDP_AUXP <21>

T1TP@

SOC_DP2_HPD <22> EC_SCI# <27>

EDP_HPD <21> ENBKL <27>

SOC_BKL_PWM <21> SOC_ENVDD <21>

RC159 10K_0402_5%@

1 2

@ESD@

1 2

EC_SCI#

RC2 100K_0402_5%

RC4 100K_0402_5%

RC5 100K_0402_5%

CC1 0.1U_0402_16V7K

Rev_1.0

B61

CPU_XDP_TCK0

D60

SOC_XDP_TDI

A61

SOC_XDP_TDO

C60

SOC_XDP_TMS

B59

SOC_XDP_TRST#

B56

PCH_JTAG_TCK1

D59

SOC_XDP_TDI

A56

SOC_XDP_TDO

C59

SOC_XDP_TMS

C61

SOC_XDP_TRST#

A59

JTAGX

Title

Size Document Number Rev

Custom

Date: Sheet of

CPU_XDP_TCK0

Compal Electronics, Inc.

SKL-U(1/12))DDI,MSIC,XDP,EDP

B3ZMS LA-D591P

<eDP>

From HDMI

From eDP

+3VS

SOC_ENVDD

ENBKL

EDP_HPD

SOC_XDP_TRST#

6 45Wednesday, February 24, 2016

2.0

non-Interleaved non-Interleaved

D D

DDR_A_D[0..15]<18>

DDR_A_D[32..47]<18>

C C

DDR_B_D[0..15]<19>

DDR_B_D[32..47]<19>

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47

UC1B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

Interleave / Non-Interleaved

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKL-U_BGA1356

SKL-U

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR3L / LPDDR3 / DDR4

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

Interleave / Non-Interleaved

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_ALERT#

DDR CH - A

2 OF 20

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

Rev_1.0

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_PAR

AU53

M_CLK_A_DDR#0

AT53

M_CLK_A_DDR0

AU55

M_CLK_A_DDR#1

AT55

M_CLK_A_DDR1

BA56

DDR_A_CKE0

BB56

DDR_A_CKE1

AW56

DDR_A_CKE2

AY56

DDR_A_CKE3

AU45

DDR_A_CS0#

AU43

DDR_A_CS1#

AT45

DDR_A_ODT0

AT43

BA51

DDR_A_CAA_0

BB54

DDR_A_CAA_1

BA52

DDR_A_CAA_2

AY52

DDR_A_CAA_3

AW52

DDR_A_CAA_4

AY55

DDR_A_CAA_5

AW54

DDR_A_CAA_6

BA54

DDR_A_CAA_7

BA55

DDR_A_CAA_8

AY54

DDR_A_CAA_9

AU46

DDR_A_CAB_0

AU48

DDR_A_CAB_1

AT46

DDR_A_CAB_2

AU50

DDR_A_CAB_3

AU52

DDR_A_CAB_4

AY51

DDR_A_CAB_5

AT48

DDR_A_CAB_6

AT50

DDR_A_CAB_7

BB50

DDR_A_CAB_8

AY50

DDR_A_CAB_9

BA50 BB52 AM70

DDR_A_DQS#0

AM69

DDR_A_DQS0

AT69

DDR_A_DQS#1

AT70

DDR_A_DQS1

BA64

DDR_A_DQS#4

AY64

DDR_A_DQS4

AY60

DDR_A_DQS#5

BA60

DDR_A_DQS5

BA38

DDR_B_DQS#0

AY38

DDR_B_DQS0

AY34

DDR_B_DQS#1

BA34

DDR_B_DQS1

BA30

DDR_B_DQS#4

AY30

DDR_B_DQS4

AY26

DDR_B_DQS#5

BA26

DDR_B_DQS5

AW50 AT52

AY67 AY68 BA67

AW67

+VREF_CA_C +V_DDR_REFA_C +V_DDR_REFB_C

DDR_PG_CTRL

T10TP@ T12TP@

Buffer with Open Drain output For VTT power control

RC25

100K_0402_5%

SM_PG_CTRL<36>

M_CLK_A_DDR#0 <18> M_CLK_A_DDR0 <18> M_CLK_A_DDR#1 <18> M_CLK_A_DDR1 <18>

DDR_A_CKE0 <18> DDR_A_CKE1 <18> DDR_A_CKE2 <18> DDR_A_CKE3 <18>

DDR_A_CS0# <18> DDR_A_CS1# <18> DDR_A_ODT0 <18>

DDR_A_CAA_0 <18> DDR_A_CAA_1 <18> DDR_A_CAA_2 <18> DDR_A_CAA_3 <18> DDR_A_CAA_4 <18> DDR_A_CAA_5 <18> DDR_A_CAA_6 <18> DDR_A_CAA_7 <18> DDR_A_CAA_8 <18> DDR_A_CAA_9 <18> DDR_A_CAB_0 <18> DDR_A_CAB_1 <18> DDR_A_CAB_2 <18> DDR_A_CAB_3 <18> DDR_A_CAB_4 <18> DDR_A_CAB_5 <18> DDR_A_CAB_6 <18> DDR_A_CAB_7 <18> DDR_A_CAB_8 <18> DDR_A_CAB_9 <18>

DDR_A_DQS#0 <18> DDR_A_DQS0 <18> DDR_A_DQS#1 <18> DDR_A_DQS1 <18>

DDR_A_DQS#4 <18> DDR_A_DQS4 <18> DDR_A_DQS#5 <18> DDR_A_DQS5 <18> DDR_B_DQS#0 <19> DDR_B_DQS0 <19> DDR_B_DQS#1 <19> DDR_B_DQS1 <19> DDR_B_DQS#4 <19> DDR_B_DQS4 <19> DDR_B_DQS#5 <19> DDR_B_DQS5 <19>

+VREF_CA_C +V_DDR_REFA_C +V_DDR_REFB_C

+1.2V_VDDQ

+3VS

SM_PG_CTRL

DDR_A_D[16..31]<18>

DDR_A_D[48..63]<18>

DDR_B_D[16..31]<19>

DDR_B_D[48..63]<19>

Trace width/Spacing >= 20mils

1 2

CC3 0.1U_0201_10V6K

UC2

VCC

74AUP1G07GW_TSSOP5

SA00007UR00

GND

DDR_PG_CTRL

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31

DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

UC1C

Interleave / Non-Interleaved

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKL-U_BGA1356

SKL-U

DDR3L / LPDDR3 / DDR4

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

Interleave / Non-Interleaved

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

3 OF 20

Rev_1.0

DDR1_CKN[0] DDR1_CKN[1]

DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7] DDR1_ALERT#

DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

AN45

M_CLK_B_DDR#0

AN46

M_CLK_B_DDR#1

AP45

M_CLK_B_DDR0

AP46

M_CLK_B_DDR1

AN56

DDR_B_CKE0

AP55

DDR_B_CKE1

AN55

DDR_B_CKE2

AP53

DDR_B_CKE3

BB42

DDR_B_CS0#

AY42

DDR_B_CS1#

BA42

DDR_B_ODT0

AW42

AY48

DDR_B_CAA_0

AP50

DDR_B_CAA_1

BA48

DDR_B_CAA_2

BB48

DDR_B_CAA_3

AP48

DDR_B_CAA_4

AP52

DDR_B_CAA_5

AN50

DDR_B_CAA_6

AN48

DDR_B_CAA_7

AN53

DDR_B_CAA_8

AN52

DDR_B_CAA_9

BA43

DDR_B_CAB_0

AY43

DDR_B_CAB_1

AY44

DDR_B_CAB_2

AW44

DDR_B_CAB_3

BB44

DDR_B_CAB_4

AY47

DDR_B_CAB_5

BA44

DDR_B_CAB_6

AW46

DDR_B_CAB_7

AY46

DDR_B_CAB_8

BA46

DDR_B_CAB_9

BB46 BA47

AH66

DDR_A_DQS#2

AH65

DDR_A_DQS2

AG69

DDR_A_DQS#3

AG70

DDR_A_DQS3

AR66

DDR_A_DQS#6

AR65

DDR_A_DQS6

AR61

DDR_A_DQS#7

AR60

DDR_A_DQS7

AT38

DDR_B_DQS#2

AR38

DDR_B_DQS2

AT32

DDR_B_DQS#3

AR32

DDR_B_DQS3

AR25

DDR_B_DQS#6

AR27

DDR_B_DQS6

AR22

DDR_B_DQS#7

AR21

DDR_B_DQS7

AN43 AP43 AT13

DDR3_DRAMRST#

AR18

SM_RCOMP0

AT18

SM_RCOMP1

AU18

SM_RCOMP2

@ESD@

CC4 0.1U_0402_16V7K

M_CLK_B_DDR#0 <19> M_CLK_B_DDR#1 <19> M_CLK_B_DDR0 <19> M_CLK_B_DDR1 <19>

DDR_B_CKE0 <19> DDR_B_CKE1 <19> DDR_B_CKE2 <19> DDR_B_CKE3 <19>

DDR_B_CS0# <19> DDR_B_CS1# <19> DDR_B_ODT0 <19>

DDR_B_CAA_0 <19> DDR_B_CAA_1 <19> DDR_B_CAA_2 <19> DDR_B_CAA_3 <19> DDR_B_CAA_4 <19> DDR_B_CAA_5 <19> DDR_B_CAA_6 <19> DDR_B_CAA_7 <19> DDR_B_CAA_8 <19> DDR_B_CAA_9 <19> DDR_B_CAB_0 <19> DDR_B_CAB_1 <19> DDR_B_CAB_2 <19> DDR_B_CAB_3 <19> DDR_B_CAB_4 <19> DDR_B_CAB_5 <19> DDR_B_CAB_6 <19> DDR_B_CAB_7 <19> DDR_B_CAB_8 <19> DDR_B_CAB_9 <19>

DDR_A_DQS#2 <18> DDR_A_DQS2 <18> DDR_A_DQS#3 <18> DDR_A_DQS3 <18> DDR_A_DQS#6 <18> DDR_A_DQS6 <18> DDR_A_DQS#7 <18> DDR_A_DQS7 <18> DDR_B_DQS#2 <19> DDR_B_DQS2 <19> DDR_B_DQS#3 <19> DDR_B_DQS3 <19>

DDR_B_DQS#6 <19> DDR_B_DQS6 <19> DDR_B_DQS#7 <19> DDR_B_DQS7 <19>

T11TP@ T13TP@ T14TP@

1 2

RC22 200_0402_1%

1 2

RC23 80.6_0402_1%

1 2

RC24 162_0402_1%

DDR3_DRAMRST#

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/21 2016/06/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

SLK-U(2/12)LPDDR3

B3ZMS LA-D591P

7 45Wednesday, February 24, 2016

2.0

www.vinaﬁx.com

UC1E

SOC_SPI_CLK SOC_SPI_SO

D D

EC_KBRST#_R<27>

To TPM

C C

EC_SERIRQ<27,28>

SOC_SPI_SI SOC_SPI_IO2 SOC_SPI_IO3

EC_KBRST#_R EC_SERIRQ

LPC Mode

AV2

AW3

AV3

AW2

AU4 AU3 AU2 AU1

AW13

AY11

M2 M3

J4 V1 V2

G3 G2 G1

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

CL_CLK CL_DATA CL_RST#

GPP_A0/RCIN# GPP_A6/SERIRQ

SKL-U_BGA1356

2015MOW06 no need PU1K on SPI_IO2/IO3

MOW36 add PD 1K depop PH 1K only for SKL U ES sample

SPI - FLASH

SPI - TOUCH

C LINK

SOC_SPI_IO2

SOC_SPI_IO3

1 2

RC37 1K_0402_1%@

1 2

RC39 1K_0402_1%@

1 2

RC40 1K_0402_1%ES@

SKL-U

LPC

SMBUS, SMLINK

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

5 OF 20

+3VALW _SPI

Rev_1.0

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

R7 R8 R10

R9 W2 W1

W3 V3 AM7

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9 AW11

SMBCLK SMBDATA SMBALERT#

SML0CLK SML0DATA SML0ALERT#

SOC_SML1CLK SOC_SML1DATA SML1ALERT#

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# ESPI_RST#

ESPI_CLK CLK_PCI1 PM_CLKRUN#

SML0ALERT# (Internal Pull Down): eSPI or LPC 0 = LPC is selected for EC --> For KB9022/9032 Use 1 = eSPI is selected for EC --> For KB9032 Only.

SMB

(Link to XDP, DDR, TP)

SML1

(Link to EC, Thermal Sensor)

ESPI_CLK_R <27> CK_LPC_TPM <28>

@RF@

CC6

22P_0201_25V8

1 2

RC31 22_0402_5%LPC@

1 2

RC32 22_0402_5%TPM@

PM_CLKRUN# <28>

T15TP@

SOC_SML1CLK <27> SOC_SML1DATA <27>

T16TP@

LPC_AD0 <27,28> LPC_AD1 <27,28> LPC_AD2 <27,28> LPC_AD3 <27,28> LPC_FRAME# <27,28> ESPI_RST# <27>

@RF@

CC5

22P_0201_25V8

SMBALERT# SML1ALERT# SML0ALERT#SOC_SPI_CS#0

EC_KBRST#_R

SML0CLK SML0DATA

SOC_SML1CLK SOC_SML1DATA SMBDATA SMBCLK

PM_CLKRUN#

EC_SERIRQ

1 2

RC26 10K_0402_5%@

1 2

RC27 150K_0402_1%@

1 2

RC28 10K_0402_5%@

1 2

RC29 1K_0402_5%

1 2

RC30 10K_0402_5%@

1 2

RC33 499_0402_1%

1 2

RC34 499_0402_1%

RPC1

1 8 2 7 3 6 4 5

2.2K_0804_8P4R_5%

1 2

RC36 8.2K_0402_5%

1 2

RC38 8.2K_0402_5%

Follow 543016_SKL_U_Y_PDG_0_9

+3VS

+3V_PRIM

+3VS

+3V_PRIM

+3VS

B B

A A

Single SPI ROM_CS0#

To SPI ROM

RPC3 and RC41 are close UC4

SPI ROM ( 8MByte )

SOC_SPI_CS#0

SOC_SPI_IO2_0_R

RPC3

1 8 2 7 3 6 4 5

1 2

RC41 15_0402_5%

8M_SINGLE@

UC4

/CS

DO(IO1)

/WP(IO2)

GND

W25Q64FVSSIQ_SO8

8M_SINGLE@

SOC_SPI_IO3SOC_SPI_IO3_0_R SOC_SPI_SISOC_SPI_SI_0_R SOC_SPI_CLKSOC_SPI_CLK_0_R SOC_SPI_SOSOC_SPI_SO_0_R

15_0804_8P4R_5%

8M_SINGLE@

SOC_SPI_IO2SOC_SPI_IO2_0_R

VCC

/HOLD(IO3)

CLK

DI(IO0)

+3VALW _SPI

8 7

SOC_SPI_IO3_0_RSOC_SPI_SO_0_R

SOC_SPI_CLK_0_R

SOC_SPI_SI_0_R

CC7

0.1U_0201_10V6K

1 2

RC43

SOC_SPI_CLK_0_R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

2015/10/21 2016/06/21

1 2

0_0402_5%@EMC@

CC9

@EMC@

10P_0402_50V8J

Compal Secret Data

Deciphered Date

SOC_SML1CLK

DMN66D0LDW-7_SOT363-6

SOC_SML1DATA

Title

Size Document Number Rev

Custom

Date: Sheet of

6 1

QC1A

DMN66D0LDW-7_SOT363-6

Compal Electronics, Inc.

SKL-U(3/12)SPI,ESPI,SMB,LPC

3 4

QC1B

B3ZMS LA-D591P

EC_SMB_CK2 <29>

EC_SMB_DA2 <29>

8 45Wednesday, February 24, 2016

2.0

UC1G

HDA_SYNC HDA_BIT_CLK HDA_SDOUT

HDA_SDIN0<26>

D D

T17 TP@

T18 TP@ T19 TP@

SPKR<11,26>

HDA_SDIN0 HDA_RST#

SOC_GPIOF1 SOC_GPIOF0

SPKR

BA22 AY22 BB22 BA21 AY21

AW22

AY20

AW20

AK7 AK6 AK9

AK10

AW5

H5 D7

D8 C8

AUDIO

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKL-U_BGA1356

SKL-U

7 OF 20

Rev_1.0

SDIO / SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD#

GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

SD_RCOMP

RC44 200_0402_1%

T20 TP@

HDA for AUDIO

C C

HDA_SYNC_R<26> HDA_SDOUT_R<26> HDA_RST#_R<26>

HDA_BIT_CLK_R<26>

RC54

RPC5

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

1 2

EMC@

33_0402_5%

HDA_SYNC HDA_SDOUT HDA_RST#

HDA_BIT_CLK

ME_EN<27>

ME_EN HDA_SDOUT

1 2

RC49 0_0402_5%@

UC1I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

B B

A A

C36 D36 A38 B38

C31 D31 C33 D33 A31 B31 A33 B33

A29 B29 C28 D28 A27 B27 C27 D27

CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3

CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7

CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11

SKL-U_BGA1356

SKL-U

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

9 OF 20

GPP_F12/EMMC_CMD

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CSI2_CLKN0

CSI2_CLKP0

CSI2_CLKN1

CSI2_CLKP1

CSI2_CLKN2

CSI2_CLKP2

CSI2_CLKN3

CSI2_CLKP3 CSI2_COMP

EMMC_RCOMP

Issued Date

Rev_1.0

C37 D37 C32 D32 C29 D29 B26 A26

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

CSI2_COMP

EMMC_RCOMP

RC63 100_0402_1%

T21 TP@

RC64 200_0402_1%

2015/10/21 2016/06/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

SKL-U(4/12)HDA,EMMC,SD

B3ZMS LA-D591P

9 45Wednesday, February 24, 2016

2.0

+RTCVCC

1 2

RC66 20K_0402_5%

1 2

CC11 1U_0402_6.3V6K

1 2

RC65 20K_0402_5%

1 2

D D

+3VALW_DSW

+3V_PRIM

C C

+3VALW_DSW

B B

+3V_PRIM

+3VALW_DSW

CC12 1U_0402_6.3V6K

1 2

CC120 10U_0603_6.3V6M@

1 2

RC67 1M_0402_5%

+3VS

From 545659_SKL_PCH_U_Y_EDS_R0_7

1 2 1 2

RPC6

RPC7

@ESD@

1 2

@ESD@

1 2 1 2 1 2

1 2

18 27 36 45

CLKREQ_PCIE#4 CLKREQ_PCIE#5

NGFF_CLKREQ# WLAN_CLKREQ# CLKREQ_PCIE#1 Card_CLKREQ#

PCH_PWROK LAN_WAKE# EC_RSMRST# SYS_RESET#

0.1U_0402_16V7K

RC69 10K_0402_5% RC70 10K_0402_5%

10K_0804_8P4R_5%

CC21 0.1U_0402_16V7K

CC22 0.1U_0402_16V7K

1 2

RC74 1K_0402_5% RC75 100K_0402_5%

RC77 8.2K_0402_5% RC78 1K_0402_5% RC79 10K_0402_5%@

RC80 10K_0402_5%@

RC82 100K_0402_5%@

From EC(open-drain)

A A

EC_VCCST_PG_R<27,30>

PCH_SRTCRST#

PCH_RTCRST#

SM_INTRUDER#

CC14

@ESD@

SYS_PWROK

SYS_RESET#

SUSCLK PCH_DPWROK

PM_BATLOW# WAKE#

AC_PRESENT_R

SOC_VRALERT#

PBTN_OUT#_R

+1.0V_VCCST

RC86 1K_0402_5%

RC87 60.4_0402_1%

CLR CMOS

CC15

0.047U_0402_16V7K

@ESD@

1 2

PCH PLTRST Buffer

0.1U_0402_16V7K

Only For Power Sequence Debug

@ESD@

CC23 0.1U_0402_16V7K

EC_VCCST_PG

NGFF SSD

WLAN

CardReader

PLT_RST#

CC20

@ESD@

H_CPUPWRGD

RC71 0_0402_5%@

T23 TP@

IN1

IN2

1 2

+3VS

RC76 1K_0402_5%@

CLK_PCIE_NGFF#<23> CLK_PCIE_NGFF<23>

NGFF_CLKREQ#<23>

CLK_PCIE_WLAN#<26> CLK_PCIE_WLAN<26>

WLAN_CLKREQ#<26>

CLK_PCIE_Card#<26>

CLK_PCIE_Card<26>

Card_CLKREQ#<26>

CC13

1 2

0.1U_0201_10V6K

UC6 SN74AHC1G08DCKR_SC70-5

PLT_RST#<27,28>

EC_RSMRST#<27>

1 2

SYS_PWROK<27,30> PCH_PWROK<27,30>

SUSPWRDNACK<27>

T28 TP@

PLT_RST_BUF#

CLK_PCIE_NGFF# CLK_PCIE_NGFF NGFF_CLKREQ#

CLKREQ_PCIE#1 CLK_PCIE_WLAN#

CLK_PCIE_WLAN WLAN_CLKREQ#

CLK_PCIE_Card# CLK_PCIE_Card Card_CLKREQ#

CLKREQ_PCIE#4

CLKREQ_PCIE#5

RC53 100K_0402_5%

PLT_RST# SYS_RESET# EC_RSMRST#

H_CPUPWRGD EC_VCCST_PG

SYS_PWROK PCH_PWROK PCH_DPWROK

SUSPWRDNACK SUSACK#_R

WAKE# LAN_WAKE#

PBTN_OUT#<27>

AC_PRESENT<27>

SUSACK#<27>

UC1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKL-U_BGA1356

PLT_RST_BUF# <23,26>

UC1K

SYSTEM POWER MANAGEMENT

AN10

GPP_B13/PLTRST#

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKL-U_BGA1356

PBTN_OUT# PBTN_OUT#_R

SUSACK# SUSACK#_R

SYS_PWROK

SKL-U

CLOCK SIGNALS

RC81 0_0402_5%@

RC83 0_0402_5%@

RC84 0_0402_5%@

RC85 0_0402_5%@

1 2

RC88 10K_0402_5%@

Rev_1.0

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XCLK_BIASREF

10 OF 20

PCH_XTAL24_IN

PCH_XTAL24_OUT PCH_RTCX1

SKL-U

GPP_B12/SLP_S0#

GPD9/SLP_WLAN#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPP_B11/EXT_PWR_GATE#

11 OF 20

GPP_B2/VRALERT#

PCH_DPWROKEC_RSMRST#

AC_PRESENT_RAC_PRESENT

F43 E43

BA17

SUSCLK

E37

XTAL24_IN

XTAL24_OUT

RTCX1 RTCX2

SRTCRST#

RTCRST#

CC16

15P_0402_50V8J

<Cocoa_1020> 32M use these part (SJ10000NM00, SJ10000MH00) just can meet <50k ohm spec 24M: SJ10000DI00, SJ10000CS00

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS# SLP_LAN#

GPD6/SLP_A#

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

PCH_XTAL24_IN

E35

PCH_XTAL24_OUT

E42

XCLK_BIASREF

AM18

PCH_RTCX1

AM20

PCH_RTCX2

AN18

PCH_SRTCRST#

AM16

PCH_RTCRST#

1 2

RC72 1M_0402_5%

YC1 24MHZ_12PF_7V24000020

GND

SJ10000DI00

Rev_1.0

AT11

PM_SLP_S0#

AP15

PM_SLP_S3#

BA16

PM_SLP_S4#

AY16

PM_SLP_S5#

AN15

PM_SLP_SUS#

AW15

SLP_LAN#

BB17

SLP_WLAN#

AN16

PM_SLP_A#

BA15

PBTN_OUT#_R

AY15

AC_PRESENT_R

AU13

PM_BATLOW#

AU11 AP16

SM_INTRUDER#

AM10

EXT_PWR_GATE#

AM11

SOC_VRALERT#

GND

SUSCLK <23>

1 2

RC68 2.7K_0402_1%

1 2

RC158 60.4_0402_1%

PCH_RTCX2

CC17

15P_0402_50V8J

PM_SLP_S0# <27> PM_SLP_S3# <27,30> PM_SLP_S4# <13,27,30>

T22TP@

PM_SLP_SUS# <14>

T24TP@ T25TP@ T113TP@

T26TP@

T27TP@

+1.0V_CLK5_F24NS

1 2

RC73 10M_0402_5%

YC2

1 2

32.768KHZ_9PF_CM7V-T1A9.0PF20PPM

SJ10000L000

CC18

8.2P_0402_50V

CC19

8.2P_0402_50V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/21 2016/06/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

SLK-U(5/12)CLK,GPIO

B3ZMS LA-D591P

10 45Wednesday, February 24, 2016

2.0

D D

TS_EN<21,27>

T29 TP@

T30 TP@

UART_2_CRXD_DTXD<26> UART_2_CTXD_DRXD<26>

C C

I2C_0_SDA<21> I2C_0_SCL<21>

I2C_1_SDA<28> I2C_1_SCL<28>

Functional Strap Definitions

TS_EN GC6_FB_EN

GSPI0_MOSI

EC_LID_OUT# GSPI1_MOSI

GPU_EVENT#

UART_2_CRXD_DTXD UART_2_CTXD_DRXD UART_2_CRTS_DCTS UART_2_CCTS_DRTS

I2C_0_SDA I2C_0_SCL

I2C_1_SDA I2C_1_SCL

UC1F

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA

GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

SKL-U_BGA1356

LPSS ISH

SKL-U

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6

6 OF 20

GPP_D15/ISH_UART0_RTS#

Rev_1.0

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

X76669BOL01

X76669BOL03

X76669BOL02

X76669BOL04

P2 P3 P4 P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

AC1 AC2 AC3 AB4

AY8 BA8 BB7 BA7 AY7 AW7 AP13

PLATFORM_ID PROJECT_ID0 PROJECT_ID1

RAM_ID0 RAM_ID1 RAM_ID2 RAM_ID3

DGPU_PWR_EN HDDHALT_LED#

ACCEL_INT#

SSD_DET#

SOC_GPIOA12

SAM 4GB

SAM 8GB

HYN 4GB

HYN 8GB

RAM_ID0

PROJECT_ID0 0 1

PROJECT_ID1 0 1

PLATFORM_ID

SSD_DET# <23>

T31 TP@

RAM_ID1

SKL-U KBL-U

0 1

RAM_ID2 RAM_ID3

0 0

0 1

+3V_PRIM +3V_PRIM +3V_PRIM

RC45 10K_0402_5%

PROJECT_ID0 PROJECT_ID1 PLATFORM_ID

+3V_PRIM +3V_PRIM +3V_PRIM +3V_PRIM

RC151 10K_0402_5%

RAM_ID0 RAM_ID1 RAM_ID2 RAM_ID3

X76@

RC155 10K_0402_5%

X76@

RC50 10K_0402_5%

RC150 10K_0402_5%

X76@

RC154 10K_0402_5%

X76@

PartNumber - Description

SA00005WX60 - S IC D3 8G/1600 K4E8E304EE-EGCE ABO!

SA00005ZQ50 - S IC D3 512M32/1600 K4E6E304EE-EGCE ABO!

SA00009GZ10 - S IC D3 8G/1866 H9CCNNN8JTBLAR-NUD ABO!1 0

SA00009H210 - S IC D3 16G/1866 H9CCNNNBLTBLAR-NUD ABO!1 1

RC46 10K_0402_5%

RC51 10K_0402_5%

RC153 10K_0402_5%

X76@

RC156 10K_0402_5%

X76@

KBL@

RC48 10K_0402_5%

SKL@

RC52 10K_0402_5%

RC152 10K_0402_5%

X76@

RC157 10K_0402_5%

X76@

SPKR (Internal Pull Down): TOP Swap Override 0 = Disable TOP Swap mode.---> AAX05 Use 1 = Enable TOP Swap Mode.

B B

GSPI0_MOSI (Internal Pull Down): No Reboot

Strap Pin

+3VS

RC100 100K_0402_5%

RC101 4.7K_0402_5%

RC102 150K_0402_1%

1 2

SPKR

GSPI0_MOSI

GSPI1_MOSI

SPKR <9,26>

DGPU_PWR_EN HDDHALT_LED# GPU_EVENT#

RPC8

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

+3VS

0 = Disable No Reboot mode. --> AAX05 Use 1 = Enable No Reboot Mode. (PCH will disable the TCO

Timer system reboot feature). This function is useful when running ITP/XDP.

ACCEL_INT#

1 2

RC91 10K_0402_5%

GSPI1_MOSI (Internal Pull Down): Boot BIOS Strap Bit 0 = SPI Mode --> AAX05 Use 1 = LPC Mode

<Cocoa_1027> Follow #544669 GPIO I/O setting

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/21 2016/06/21

Compal Secret Data

Deciphered Date

I2C_0_SDA I2C_0_SCL

I2C_1_SDA I2C_1_SCL

UART_2_CRXD_DTXD UART_2_CTXD_DRXD UART_2_CRTS_DCTS UART_2_CCTS_DRTS

1 2

RC92 1K_0402_5%@

1 2

RC93 1K_0402_5%@

1 2

RC94 2.2K_0402_5%

1 2

RC95 2.2K_0402_5%

1 2

RC96 49.9K_0402_1%

1 2

RC97 49.9K_0402_1%

1 2

RC98 49.9K_0402_1%

1 2

RC99 49.9K_0402_1%

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

SKL-U(6/12)GPIO

+3V_PRIM

+3V_PGPPC

+3VS

B3ZMS LA-D591P

2.0

11 45Wednesday, February 24, 2016

2.0

PCIE_CRX_DTX_N1<23>

PCIE_CRX_DTX_P1<23>

PCIE_CTX_C_DRX_N1<23>

PCIE_CTX_C_DRX_P1<23>

D D

WLAN

SATA SSD

C C

CardReader

When PCIE8/SATA1A is used as SATA Port 1 (ODD), then PCIE11/SATA1B (M.2 SSD) cannot be used as SATA Port 1.

B B

A A

PCIE_CRX_DTX_N2<23>

PCIE_CRX_DTX_P2<23>

PCIE_CTX_C_DRX_N2<23>

PCIE_CTX_C_DRX_P2<23>

PCIE_CRX_DTX_N3<23>

PCIE_CRX_DTX_P3<23>

PCIE_CTX_C_DRX_N3<23>

PCIE_CTX_C_DRX_P3<23>

PCIE_CRX_DTX_N4<23>

PCIE_CRX_DTX_P4<23>

PCIE_CTX_C_DRX_N4<23>

PCIE_CTX_C_DRX_P4<23>

PCIE_CRX_DTX_N6<26>

PCIE_CRX_DTX_P6<26>

PCIE_CTX_C_DRX_N6<26>

PCIE_CTX_C_DRX_P6<26>

SATA_CRX_DTX_N0<23> SATA_CRX_DTX_P0<23> SATA_CTX_DRX_N0<23> SATA_CTX_DRX_P0<23>

PCIE_CRX_DTX_N9<26>

PCIE_CRX_DTX_P9<26>

PCIE_CTX_C_DRX_N9<26>

PCIE_CTX_C_DRX_P9<26>

RC105 100_0402_1%

XDP_PREQ#<6>

1 2

12 12

XDP_PRDY# XDP_PREQ# SOC_GPIOA7

CC24 0.1U_0201_10V6K@ CC25 0.1U_0201_10V6K@

CC26 0.1U_0201_10V6K@ CC27 0.1U_0201_10V6K@

CC28 0.1U_0201_10V6K@ CC29 0.1U_0201_10V6K@

CC30 0.1U_0201_10V6K@ CC31 0.1U_0201_10V6K@

CC32 0.1U_0201_10V6K CC33 0.1U_0201_10V6K

CC34 0.1U_0201_10V6K CC35 0.1U_0201_10V6K

T32 TP@

PCIE_CRX_DTX_N1 PCIE_CRX_DTX_P1 PCIE_CTX_DRX_N1 PCIE_CTX_DRX_P1

PCIE_CRX_DTX_N2 PCIE_CRX_DTX_P2 PCIE_CTX_DRX_N2 PCIE_CTX_DRX_P2

PCIE_CRX_DTX_N3 PCIE_CRX_DTX_P3 PCIE_CTX_DRX_N3 PCIE_CTX_DRX_P3

PCIE_CRX_DTX_N4 PCIE_CRX_DTX_P4 PCIE_CTX_DRX_N4 PCIE_CTX_DRX_P4

PCIE_CRX_DTX_N6 PCIE_CRX_DTX_P6 PCIE_CTX_DRX_N6 PCIE_CTX_DRX_P6

SATA_CRX_DTX_N0 SATA_CRX_DTX_P0 SATA_CTX_DRX_N0 SATA_CTX_DRX_P0

PCIE_CRX_DTX_N9 PCIE_CRX_DTX_P9 PCIE_CTX_DRX_N9 PCIE_CTX_DRX_P9

PCIE_RCOMPN PCIE_RCOMPP

UC1H

PCIE / USB3 / SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

PCIE_RCOMPN

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL-U_BGA1356

GPIO

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

DEVSLP0 DEVSLP1

DEVSLP2

SATA_GP0

SATA_GP1 SATA_GP2

SKL-U

8 OF 20

DEVICE CONTROL

USB2 Port 1&2 USB2 Port 3

NA NA

NGFF SSD KEY B NA

NA NA

SSIC / USB3

USB3_2_RXN / SSIC_RXN USB3_2_RXP / SSIC_RXP

USB3_2_TXN / SSIC_TXN USB3_2_TXP / SSIC_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

Rev_1.0

USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_3_RXN USB3_3_RXP USB3_3_TXN USB3_3_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6 AG3 AG4

A9 C9 D9 B9

J1 J2 J3

H2 H3 G4

USB3_CRX_DTX_N1 USB3_CRX_DTX_P1 USB3_CTX_DRX_N1 USB3_CTX_DRX_P1

USB3_CRX_DTX_N2 USB3_CRX_DTX_P2 USB3_CTX_DRX_N2 USB3_CTX_DRX_P2

USB3_CRX_DTX_N3 USB3_CRX_DTX_P3 USB3_CTX_DRX_N3 USB3_CTX_DRX_P3

USB3_CRX_DTX_N4 USB3_CRX_DTX_P4 USB3_CTX_DRX_N4 USB3_CTX_DRX_P4

USB20_N1 USB20_P1

USB20_N2 USB20_P2

USB20_N3 USB20_P3

USB20_N4 USB20_P4

USB20_N5 USB20_P5

USB20_N6 USB20_P6

USB20_N7 USB20_P7

USB20_N8 USB20_P8

USB2_COMP USB2_ID USB2_VBUSSENSE

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

DEVSLP0 DEVSLP1 DEVSLP2

SATA_GP0 SATA_GP1 SATA_GP2

SATA_LED#

USB3_CRX_DTX_N1 <26> USB3_CRX_DTX_P1 <26> USB3_CTX_DRX_N1 <26> USB3_CTX_DRX_P1 <26>

USB3_CRX_DTX_N2 <24> USB3_CRX_DTX_P2 <24> USB3_CTX_DRX_N2 <24> USB3_CTX_DRX_P2 <24>

USB3_CRX_DTX_N3 <25> USB3_CRX_DTX_P3 <25> USB3_CTX_DRX_N3 <25> USB3_CTX_DRX_P3 <25>

USB3_CRX_DTX_N4 <25> USB3_CRX_DTX_P4 <25> USB3_CTX_DRX_N4 <25> USB3_CTX_DRX_P4 <25>

USB20_N1 <26> USB20_P1 <26>

USB20_N2 <24> USB20_P2 <24>

USB20_N3 <25> USB20_P3 <25>

USB20_N4 <25> USB20_P4 <25>

USB20_N5 <26> USB20_P5 <26>

USB20_N6 <21> USB20_P6 <21>

USB20_N7 <21> USB20_P7 <21>

USB20_N8 <29> USB20_P8 <29>

1 2

RC103 113_0402_1%

1 2

RC104 0_0402_5%@

1 2

RC106 0_0402_5%@

USB_OC1# <24>

DEVSLP0 <23>

T33 TP@ T34 TP@

SOC_GPIOA7

SATA_LED# SATA_GP1 SATA_GP2 SATA_GP0

USB_OC2# USB_OC1# USB_OC0# USB_OC3#

1 2

RC107 10K_0402_5%

RPC9

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

RPC10

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

USB2/3 Right

USB2/3 Left (Charger)

USB3 Type-C

USB2/3 Right USB2/3 Left (Charger)

USB3 Type-C

WLAN/BT TouchScreen Camera Finger Print

+3VS

+3V_PRIM

Security Classification

2015/10/21 2016/06/21

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/21 2016/06/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

SKL-U(7/12)PCIE,USB,SATA

B3ZMS LA-D591P

12 45Wednesday, February 24, 2016

2.0

+5VALW +1.0V_VCCSTU+1.0V_PRIM

1U_0402_6.3V6K

CC37

D D

1 2

SYSON<27,30,36>

PM_SLP_S4#<10,27,30>

For Power consumption Measurement

+1.0V_PRIM +1.0V_PRIM_JP

C C

1 2

RC110 0_0805_5%@

Imax : 2.77 A

RC108 0_0402_5%

1 2

RC109 0_0402_5%@

RC35 0_0402_5%

1 2

CC8

+1.8V_MEM_ONSYSON

.1U_0402_16V7K@

+1.8V_PRIM +1.8V_MEM

1U_0402_6.3V6K

CC38

EN_1.0V_VCCSTU

UC7

1 2

3 4 5 6

VOUT1

VIN1

VOUT1

VIN1 ON1 VBIAS ON2 VIN2

VOUT2

VIN2

VOUT2

EM5209VF_DFN14_2X3

CT1

GND

CT2

1000P_0402_50V7K

GPAD

14 13

12 11 10 9

8 15

1 2

CC39 470P_0402_50V7K

1 2

CC40

+1.8V_MEM_OUT

0.1U_0201_10V6K

CC36

Follow 543977 _SKL_PDDG_Rev0_91 CC95 10pf -> 22us (Spec:<= 65us)

J16

112

0.1U_0201_10V6K JUMP_43X118

CC51

+1.0VS_VCCSTG

BSC Side

1U_0402_6.3V6K

CC41

+1.0V_PRIM TO +1.0VS_VCCSTG / +1.0VS_VCCIO

+5VALW

+1.0V_PRIM_JP

+1.0V_PRIM TO +1.0V_VCCSTU

0.1U_0201_10V6K

CC46

B B

SUSP#<27,30,36,38>

EC_S0IX_EN<27>

For Verify S0IX

SUSP#

1 2

RC116 0_0402_5%

1 2

RC117 0_0402_5%@

1U_0402_6.3V6K

CC47

UC9

VIN1

VIN2

VIN thermal

VBIAS

TPS22961DNYR_WSON8

VOUT

GND

+1.0VS_VCCSTG_IO

RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev0_53 CC47,CC54 Follow 549914_SKL_U_LPDDR3_RVP5

1 2

RC113 0_0402_5%@

1 2

RC114 0_0805_5%@

+1.0VS_VCCSTG

+1.0VS_VCCIO

Imax : 2.73 A

CC44 0.1U_0201_10V6K

CC48 0.1U_0201_10V6K

+1.2V_VDDQ

+1.2V_VDDQC

+1.0V_VCCST

+1.0VS_VCCSTG

+1.0VS_VCCSTG_OC

+1.0V_VCCSFR

+1.0V_VCCSTU +1.0V_VCCST

RC111

1 2

0_0402_5%

RC115

1 2

0_0402_5%

PSC Side

+1.0V_VCCSFR

PSC Side

1U_0402_6.3V6K

120

UC1N

SKL-U

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

BB47

VDDQ_BB47

BB51

VDDQ_BB51

AM40

VDDQC

A18

VCCST

A22

VCCSTG_A22

AL23

VCCPLL_OC

K20

VCCPLL_K20

K21

VCCPLL_K21

SKL-U_BGA1356

CC42

CC50

CPU POWER 3 OF 4

14 OF 20

+5VALW

CC49

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

+1.2V_VDDQ

SUSP#

1U_0402_6.3V6K

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

Rev_1.0

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

1 2

RC112 0_0402_5%@

UC8

VIN

VBIAS

SA00006U600

AOZ1336_DFN8_2X2

+1.0VS_VCCIO

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE VCCSA_SENSE

VOUT VOUT

GND GND

3.1A

+VCC_SA

4.5A

+1.0VS_VCCSTG_OC

7 8

5 9

CC43

T35 TP@ T36 TP@

1000P_0402_50V7K

VSSSA_SENSE <39> VCCSA_SENSE <39>

BSC Side

0.1U_0201_10V6K CC45

+1.0VS_VCCIO

22U_0603_6.3V6M

CC52

A A

2.2U_0402_6.3V6M CC54

PSC SideBSC Side

1U_0402_6.3V6K

CC58

2.2U_0402_6.3V6M

1U_0402_6.3V6K

CC60

CC59

+1.2V_VDDQC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BSC Side BSC SidePSC Side

1 2

RC118 0_0603_5%@

1U_0402_6.3V6K

10U_0603_6.3V6M

CC62

CC63

2015/10/21 2016/06/21

+1.2V_VDDQ

10U_0603_6.3V6M

CC64

Compal Secret Data

22U_0603_6.3V6M

CC65

+1.2V_VDDQ : 10UF/6.3V/0603 *9 1UF/6.3V/0402 * 4

Deciphered Date

10U_0603_6.3V6M

CC67

22U_0603_6.3V6M

1U_0402_6.3V6K

CC69

CC70

Title

Size Document Number Rev

Custom

Date: Sheet of

1U_0402_6.3V6K

CC73

Compal Electronics, Inc.

SKL-U(8/12)POWER

B3ZMS LA-D591P

22U_0603_6.3V6M

CC74

10U_0603_6.3V6M

CC76

2.0

13 45Wednesday, February 24, 2016

+1.0V_PRIM

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC119 0_0603_5%@

D D

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC123 0_0603_5%@

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC126 0_0603_5%@

C C

Imax : 2.57A

1 2

RC131 0_0402_5%@

B B

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC133 0_0603_5%@

1 2

RC136 0_0402_5%@

1U_0402_6.3V6K

+1.0V_APLL

+1.0V_CLK5_F24NS

+1.0V_CLK4_F100OC

+1.0V_PRIM

+1.0V_MPHYAON

+1.0V_CLK6_24TBT

CC103

+1.0V_DTS

22U_0603_6.3V6M

CC79

22U_0603_6.3V6M

CC84

22U_0603_6.3V6M

CC93

1U_0402_6.3V6K

CC98

1U_0402_6.3V6K

CC100

10U_0603_6.3V6M

CC106

+3V_PRIM

RC122 0_0402_5%@

CC80 1U_0402_6.3V6K

RC124 0_0402_5%@

RC125 0_0402_5%@

RC127 0_0402_5%@

RC128 0_0402_5%@

RC129 0_0402_5%@

RC132 0_0402_5%@

RC134 0_0402_5%@

Follow 543016_SKL_U_Y_PDG_0_9

+3V_PRIM +1.8V_PRIM

A A

22U_0603_6.3V6M

CC115

22U_0603_6.3V6M

CC117

+3VALW

+3V_HDA

1 2

RC140 0_0603_5%@

+3V_1.8V_PGPPD

1 2

CC81 1U_0402_6.3V6K

+3V_PGPPA

+3VALW_SPI

+3V_PGPPB

1U_0402_6.3V6K

+3V_PGPPC

1U_0402_6.3V6K

RC130 0_0402_5%@

1U_0402_6.3V6K

+3V_PGPPE

1U_0402_6.3V6K

+3V_PRIM_RTC

1U_0402_6.3V6K

CC94

CC97

CC99

CC102

CC107

Follow 543016_SKL_U_Y_PDG_0_9

1 2

0.1U_0201_10V6K

CC108

+3VALW_DSW

+1.8V_PRIM

+1.0V_PRIM

1U_0402_6.3V6K

CC77

696

1U_0402_6.3V6K

+1.0V_PRIM

1U_0402_6.3V6K

CC91

1U_0402_6.3V6K

+1.0V_PRIM

+1.0V_MPHYAON

+1.0V_APLL +1.0V_PRIM

+3VALW_DSW

+3V_HDA

+3VALW_SPI

+3V_PRIM

+1.0V_PRIM

2.574A

836

118

642

+1.0VO_DSW

CC82

+1.0V_PRIM

22U_0603_6.3V6M

1U_0402_6.3V6K

CC89

CC88

CC87

+1.0V_PRIM

1U_0402_6.3V6K

CC95

+1.0V_PRIM

CC96

UC1O

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB_1P0

SKL-U_BGA1356

SKL-U

CPU POWER 4 OF 4

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE VCCPGPPF VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

15 OF 20

Per 543016_SKL_U_Y_PDG_0_9 VCCRTC does not exceed 3.2 V From PDG

Power Rail Voltage

+CHGRTC

BAT54C(VF)

+3VL_RTC

3.383V(MAX)

240 mV

3.143V

Result : Pass

Rev_1.0

DCPRTC VCCCLK1 VCCCLK2 VCCCLK3 VCCCLK4 VCCCLK5 VCCCLK6

+RTCBATT

W=20mils

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19 T1 AA1 AK17 AK19

BB14 BB10 A14 K19 L21 N20 L19 A10 AN11

AN13

+3V_PGPPA +3V_PGPPB +3V_PGPPC +3V_1.8V_PGPPD +3V_PGPPE +1.8V_PRIM +3V_PRIM

+1.0V_DTS

+3V_PRIM_RTC

+RTCVCC

1 2

CC90 0.1U_0201_10V6K

+1.0V_CLK6_24TBT

+1.0V_APLL

+1.0V_CLK4_F100OC

+1.0V_CLK5_F24NS

+1.0V_CLK6_24TBT

PRIMCORE_VID0 PRIMCORE_VID1

RTC Battery

+CHGRTC

DC1

W=10mil

BAS40-04_SOT23-3

cap Place close AK19.

T37 TP@ T38 TP@

W=20mils

+RTCVCC

EC LPC/ESPI

20 4 6 8 6 33 41

+1.8V_PRIM

CC101

0.1U_0201_10V6K

+3V_PRIM

+1.8V_PRIM+3VALW_1.8VALW_PGPPA

RC1200_0402_5% ESPI@

RC1210_0402_5%

+3V_PRIM

1U_0402_6.3V6K

CC83

1U_0402_6.3V6K

CC85

+3VALW TO +3V_PRIM

+3VALW+5VALW

1U_0402_6.3V6K

CC110

1 2

PCH_PWR_EN<27>

PM_SLP_SUS#<10>

1U_0402_6.3V6K

CC86

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RC138 0_0402_5%@

1 2

RC139 0_0402_5%@

Compal Secret Data

2015/10/21 2016/06/21

Compal Secret Data

1U_0402_6.3V6K

CC109

EN_3V_PRIM

Deciphered Date

UC10

VIN

VBIAS

SA00006U600

AOZ1336_DFN8_2X2

VOUT VOUT

GND GND

7 8

5 9

+3VALW

1 2

RC135 0_0805_5%@

For NON-DS3

+3V_PRIMJP

1 2

RC137 0_0805_5%@

For DS3

1 2

CC112

1000P_0402_50V7K

Title

Size Document Number Rev

Custom

Date: Sheet of

+3V_PRIM

0.1U_0201_10V6K

CC111

Compal Electronics, Inc.

SKL-U(9/12)Power

B3ZMS LA-D591P

14 45Wednesday, February 24, 2016

2.0

+ 31 hidden pages

Compal LA-D591P Schematics Rev2.0

Specifications and Main Features

Frequently Asked Questions

User Manual