Compal LA-D562P Schematics

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A

1 1

2 2

B

C

D

E

V330/V530/EX3

DIS M/B Schematics Document

Intel Kabylake RU Processor with DDR4

AMD R17M

2017-06-15

3 3

LA-F481P

R E V：0 . 2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size

C

Date: Sheet of

Cover Page

Document Number Re v

Document Number Rev

LA-D562P

E

1 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

A

B

C

D

E

Channel A

DDR4 2133/2400MHz (1.2V , 2.5V)

AMD Radeon 530M

1 1

VRAM GDDR5 x2

P21

eDP Conn.

FHD

P28

HDMI Conn. (HDMI 1.4)

RJ45 Conn.

2 2

LAN

RTL8111H-CG 100/1000

M.2 SSD

P29

P36

PCIe X4 / SATA X1

(TYPE M)

P32

PCIe X1 for WLAN

WLAN / BT

USB2.0 x1 for BT

P31

2nd Battery / USB2.0 conn. (Reserve)

P46

Card Reader

Realtek

3 3

LED

RTS5146

Finger Print

DC to DC

Touch Pad

APS

4 4

A

P37

P33

P46

B

PCIe X4

eDP X1 (2 Lanes)

DDI X1

PCIe X1

USB2.0 x1

SMBUS

TPM/TCM

Opt i on

Intel KBL-RU 15W/28W

I2C

EC

ENE KB9022

P27 P45

Int. KBD

SOC

1356pin BGA

SPILPC

SPI ROM

16MB

P33

C

Channel B

DDR4 2133/2400MHz (1.2V , 2.5V)

DDR4 support 2133/2400MHz on KBL-RU DDR4 support 2133MHz on SKL and KBL-U

USB3.0 x1 USB2.0 x1

USB3.0 x1

TypeC

RTS5448

CC+MUX

USB3.0 x1

DDI X1

DP MUX

PS8338B

P38

USB2.0 x1

SATA X1

HDA

Int. MIC Conn. Int. Speaker Conn.

P08

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

P28

Compal Secret Data

Deciphered Date

D

On board DDR4 X 4

DDR4 SO DIMM X1

Right USB3.0 x1

Left USB3.0 x1

With AOU

USB3.0 x1 USB2.0 x1

P42 P43

TypeC

RTL5455

PD+DP+MUX

CRT converter

RTD2166

Int. Camera

HDD Conn.

P28

P30

Audio Codec

CONEXANT CX11802

P35

P18

P19

P34

TypeC (CC)

USB3.0 x1 USB2.0 x1

P40 P41

P39

TypeC (CC+PD+DP)

CRT Conn.

Opt i on

Audio Combo Jack

P35

HP & MIC

P35

Compal Electronics, Inc.

Title

Size

Document Number Rev

C

Date: Sheet of

Block Diagram

LA-D562P

E

2 66Thursday, June 15, 2017

P39

1.0

Vinaﬁx.com

1

Voltage Rails

power

A A

B B

S5 and S4/Battery only

S5 and S4/AC&Battery don't exist(Only RTC )

plane

State

S0

S3

S5 and S4/AC

+RTCBAT T

O

+B

+5VL

+3VL

+5VALW

+3VALW

+1.8VAL W

+1VALW

O

X

EC SM Bus1 address

Device

Smart Battery

Address

0001 011x

PCH SM Bus address

Device

DDR_JDIMM1 GPU RTS5 455 RTD21 66

C C

APS

Address

1010 000x A0h 1000 001x A0h

1010 1100 A0h 1100 100 A0h 1111 0100 A0h

2

+1.0V_VC CST

+2.5V

+1.2V

O O

O

X

+5VS

+3VS

+3VGS

+1.8VGS

+1.0VS_V CCIO

+PCIE_VG S

+VGA_COR E

+1.35VS_ VRAM

+0.6VS

+VCCCOR E

+VCCGT

+VCCSA

X

XX

X

XXX

CPU

2+2

2+3

USB 2.0 Port Table

Port

1 2 3 4 5 6 7 8 9 10

3 External USB Port

USB 3.0 Port (AOU)

USB 3.0 Port

TYPE-C USB 3.0 Port TYPE-C USB 3.0 Port(FULL) Camera

M.2 BT

Card Reader

Finger Print

2nd Battery

USB 3.0 Port Table

1

USB 3.0 Port (AOU)

2

USB 3.0 Port

3

TYPE-C USB 3.0 Port

4

TYPE-C USB 3.0 Port(FULL)

5 6

SATA Port Table

Port

0

HDD

1

2

M.2 SATA SSD

SKL-U

UC1

CPU1@

SA000092P60

UC1

CPU5@

SA00009E620

i7-6500U

i7-6567U

UC1

CPU2@

i5-6300U

SA000092T40

UC1

CPU4@

i3-6006U

SA0000ACN10

UC1

CPU6@

i5-6267U

SA00009E530

3

UC1

CPU3@

i5-6200U

SA000092O70

KBL-U

UC1

CPU7@

i3-7100U

SA0000A38H0

UC1

CPU10@

i5-7300U

SA0000ADO20

UC1

CPU13@

i7-7567U

SA0000AW620

BOM Structure Table

PCIE Port Table

Port

Lane

1

2

3

4

4 5 6 7 8 9 10 11 12

i5-7200U

3865U

i5-7267U

UC1

CPU9@

i7-7500U

SA0000A34F0

UC1

CPU12@

4415U

SA0000ADV40

UC1

CPU8@

SA0000A37B0

UC1

CPU11@

SA0000ADL30

UC1

CPU14@

SA0000AKR20

4

GPU

LAN

M.2 WLAN+BT

M.2 PCIE*4 SSD

KBL-RU

UC1

CPU15@

KBL-R QN5D

SA0000AR010

UC1

CPU17@

KBL-R QNEF

SA0000AWB00

SKL only SKL@ For 2+2 For 2+3 For 4+2 For DIS

EMI Un-pop ESD pop ESD Un-pop

Finger Print Keyboard backlight KBL@

NONA OU NONA OU@

APS NOAP S 2nd Battery USB BATT 2@ NO 2nd Battery USB

Onboard RAM MICRON Onboard RAM SAMSUNG VRAM HYNIX VRAM MICRON VRAM SAMSUNG CardReader RTS5146 CardReader GL835 TPM TPM@ TCM TCM@ NO TPM/TCM NOTPM@

4+2

UC1

CPU16@

KBL-R QN5C

SA0000AQZ10

UC1

CPU18@

KBL-R QNBF

SA0000AWC00

BOM StructureItem

U22@ U23@ U42@ DIS@ UMA@For UMA CMOS @Came ra EMI@EMI pop @EMI @ ESD@ @ESD @ RF@RF pop @RF@RF unpop 8M@For SPI 8M 16M@For SPI 16M FP@

AOU@AOU

TYPE C@TYPEC FULL NONT YPEC @NONT YPEC APS@ NOAP S@

NOBA TT2@ X76D DRH@Onboard RAM HYNIX X76D DRM@ X76D DRS@ X76H 2G@ X76M 4G@ X76S 2G@ X76R T@ X76G L@

ME@Conn ecto r

5

SMBUS Control Table

ZZZ

X

V

+3VS

XX

X

ONONON

ON

SOC

X

V

+3VALW

X

ON

OFF

2

ON

OFF

ONON

LOW

OFF

X76DDR4H@

2G HYNIX

X7675138L01

On Board RAM

ZZZ

X76RT@

RTS5146

X7675138L61

CardReader

ZZZ

X4E@

X4E

X4EA8X38L01

SOURCE

SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 PCH_SMBCLK PCH_SMBDATA PCH_SML0CLK PCH_SML0DATA SML1CLK SML1DATA

D D

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

1

EC KB9022

+3VALW

EC KB9022

+3VS

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

SIGNAL

GPU

+3VALW

V

+3VGS

X

V

+3VGS

SLP_S1#

LOW

HIGH HIGH HIGH

LOW

LOW LOW LOW

LOWLOW

SODIMMNECP388BATT

VX X

X

XX

V

X X

+3VS

SLP_S4#SLP_S3# +V (RAM)+VALWSLP_S5# Cl ock+VS

HIGHHIGHHIGH

HIGH

LOWLOW

ZZZ

X76DDR4M@

2G MICRON

X7675138L02

ZZZ

X76GL@

GL835

X7675138L62

ZZZ

X76DDR4S@

2G SAMSUNG

X7675138L03

3

UV1

GPU1@

VGA

SA000098VB0

ZZZ

PCB

DA8001CE000

GPU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

Notes List

Size

Document Number Rev

C

Date: Sheet of

LA-D562P

5

3 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

[BIWB6/B7/E7/E8-PWR Sequence_SKL-U22_DDR3L_Volume_NON CS]

4

3

2

1

G3->S0 S0->S3 ->S0

+3VL_RTC

SOC_RTCRST#

B+

D D

+3VLP

EC_ON

+5VALW / +3VALW

tPCH01_Min : 9 ms

tPCH04_Min : 9 ms

Pull-up to DSW well if not implemented.

/DS3 DS3S3/

S0->S5

+3VL_RTC

SOC_RTCRST#

+19VB

+3VLP/+5VLP

EC_ON

+5VALW/+3VALW/+3 VALW_DSW

PM_BATLOW#

PCH_PWR_EN (SLP_SUS#)

+3V_PRIM

+1.8VALW

+1.0VALW

tPCH06_Min : 200 us

PCH_DPWROK

EC_RSMRST#

AC_PRESENT(VCIN1_AC_IN)

tPCH34_Max : 20 ms

tPCH02_Min : 10 ms

tPCH03_Min : 10 ms

tPLT02_Min : 0 ms Max : 90 ms

ON/OFF#

PBTN_OUT#

C C

PM_SLP_S5#

Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

PM_SLP_S4#

SYSON

+1.0V_VCCST

+1.2V

PM_SLP_S3#

SUSP#

+1.0VS_VCCIO

+5VS / +3VS / +1.05VS

EC_VCCST_PG(VCCST_PWRGD)

VR_ON

DDR_VTT_PG_CTRL

B B

+0.675VS

tCPU04 Min : 100 ns

T4 = Min : 20ms Max : 30ms(EC Control)

tCPU19 Max : 100 ns

tCPU18 Max : 35 us

+VCCSA

tCPU10 Min : 1 ms

tCPU09 Min : 1 ms

+VCCCORE

+VCCGT

VR_PWRGD

PCH_PWROK

tCPU16 Min : 0 ns

H_CPUPWRGD

SYS_PWROK

SOC_PLTRST#(PCIRST#)

+1.8V_PRIM

+1.0V_PRIM

SUSACK#

PCH_DPWROK

EC_RSMRST#

AC_PRESENT

ON/OFF

PBTN_OUT#

PM_SLP_S5#

PM_SLP_S4#

SYSON

+1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC

PM_SLP_S3#

SUSP#

+1.0VS_VCCIO

+5VS/+3VS/+1. 5VS/+1.05VS

EC_VCCST_PG

VR_ON

SM_PG_CTRL

+0.675VS_VTT

+VCC_SA

+VCC_CORE

+VCC_GT

VR_PWRGD

PCH_PWROK

H_CPUPWRGD

SYS_PWROK

SOC_PLTRST#

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2015/01/29 2016/01/29

Deciphered Date

2

Compal Electronics, Inc.

Title

Size

Date: Sheet of

Power Sequence

Document Number Rev

LA-D561P

1

4 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

4

3

2

1

M1-30 VRAM STRAP

Vendor

UV3, UV4, UV5, UV6

D D

X76H 2G@

X7667538L03

X76M 2G@

X7667538L04

X76S 2G@

X7667538L05

HYNIX 4096Mbits SA000076P80 TEMP 256MX16 K4W4G1646E-BC1A TEMP

Micron 4096Mbits SA00009HF00 TEMP 256Mx16 MT41J256M16LY-091G:N TEMP

SAMSUNG 4096Mbits SA00008DN00 TEMP 256MX16 H5TC4G63CFR-N0C TEMP

2GBy tes

ID

0 0

0

1

2

4

PS_3[ 1 ]PS_3[ 2 ]PS_3[ 3 ]

0

10 0

00 1

001 4.99 K4.53 K

X76@X76@

R_pu

RV22 RV27

NC 4.75K

8.45 K 2K

4.53 K 2K

R_pd

Power-Up/Down Sequence

"M1" has the following requirements with regards to power-supply sequencing to avoid damaging the ASIC:

All the ASIC supplies must reach their respective nominal voltages within 20ms

‧

of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred. The maximum slew rate on all rails is 50 mV/μ s.

It is recommended that the 3.3-V rail ramp up frist.

‧

It is recommended that the 0.95-V rail reach at least 90% of its nominal value no later

‧

than 2ms from the start of VDDC ramping up.

The power rails that are shared with other components on the system should be gated for

‧

the dGPU so that when dGPU is powered down (for example AMD PowerXpressTM idle state), all the power rails are removed from the dGPU. The gate circuits must meet the slew rate requirement (such as 50mV/us)

VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC

‧

should reach 90% before VDD_CT starts to ramp up (or vice versa).

For power down, reversing the ramp-up sequence is recommended.

‧

≦

5 11 0 3.24 K 5.62 K

6 10K3.4K011

ZZZ

C C

X76H2G@

2G HYNIX

X7675138L04

ZZZ

X76M2G@

2G MICRON

X7675138L05

ZZZ

X76S2G@

2G SAMSUNG

X7675138L06

VDDR3(+3VGS)

PCIE_VDDC(+0.95VGS)

VDD_CT(+1.8VGS)

VDDR1(+1.35VGS)

VDDC/VDDCI(+VGA_CORE)

DGPU_PWROK

PERSTb

REFCLK

Straps Reset

B B

Straps Valid

Global ASIC Reset

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/01/07 2016/01/07

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size

C

Date: Sheet of

Compal Electronics, Inc.

VGA Notes List

Document Number Rev

VGA Notes List

LA-D562P

1

5 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

A

1 1

B

C

D

E

DDI

DISPLAY SIDEBANDS

SKL-U

1 OF 20

EDP

Rev_1.0

EDP_TXN[0]

EDP_TXP[0]

EDP_TXN[1]

EDP_TXP[1]

EDP_TXN[2]

EDP_TXP[2]

EDP_TXN[3]

EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP

RSVD RSVD

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52

G50 F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

EDP_TXN0 [28] EDP_TXP0 [28] EDP_TXN1 [28] EDP_TXP1 [28]

EDP_AUXN [28] EDP_AUXP [28]

DDIP2_AUXN [38] DDIP2_AUXP [38]

TMDS_B_HPD [29] DDIP2_HPD [38]

EC_SCI# [10,45] EDP_HPD [28]

ENBKL [45] INVPWM [28] PCH_ENVDD [28]

From HDMI From DP

From eDP

<eDP>

UC1A

HDMI_TX2-_CK[29] HDMI_TX2+_CK[29] HDMI_TX1-_CK[29]

HDMI

DP MU X (Type-C/ VGA)

HDMI DDC

DP MUX DDC

2 2

+1.0VS_VCCIO

     ! "

EDP_COMP

1 2

RC1 24.9_0402_1%

HDMI_TX1+_CK[29] HDMI_TX0-_CK[29] HDMI_TX0+_CK[29] HDMI_CLK-_CK[29] HDMI_CLK+_CK[29]

DDI2_TX0-_CK[38] DDI2_TX0+_CK[38] DDI2_TX1-_CK[38] DDI2_TX1+_CK[38] DDI2_TX2-_CK[38] DDI2_TX2+_CK[38] DDI2_TX3-_CK[38] DDI2_TX3+_CK[38]

HDMICLK_NB[29] HDMIDAT_NB[29]

DDIP2_CTRLCLK[38] DDIP2_CTRLDATA[38]

EDP_COMP

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22

N12

GPP_E23

E52

EDP_RCOMP

SKL-U_BGA1356

@

 

+1.0VS_VCCIO

12

RC2 1K_0402_5%

H_PROCHOT#_R

H_PROCHOT#[45]

3 3

1 2

RC3 499_0402_1%

+1.0V_VCCST

1 2

RC7 1K_0402_5%

H_THERMTRIP#

H_PECI[45]

RC10 49.9_0402_1% RC11 49.9_0402_1% RC12 49.9_0402_1% RC14 49.9_0402_1%

H_PECI H_PROCHOT#_R H_THERMTRIP#

12 12 12 12

T1 TP@

T2 TP@

T3 TP@ T4 TP@ T5 TP@ T6 TP@

T7 TP@

T8 TP@

SOC_CATERR#

SOC_OCC#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3

SOC_GPIOE3

SOC_GPIOB4

CPU_POPIRCOMP PCH_OPIRCOMP EDRAM_OPIO_RCOMP EOPIO_RCOMP

AT16 AU16

D63 A54 C65 C63 A65

C55 D55 B54 C56

A6

A7 BA5 AY5

H66 H65

UC1D

SKL-U_BGA1356

@

CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

CPU MISC

SKL-U

4 OF 20

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

Rev_1.0

JTAGX

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

CPU_XDP_TCK0 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST#

PCH_JTAG_TCK1 SOC_XDP_TDI

SOC_XDP_TDO SOC_XDP_TMS PCH_XDP_TRST# CPU_XDP_TCK0

T9 TP@

#!$!%&"

SOC_XDP_TMS

SOC_XDP_TDI

SOC_XDP_TDO

CPU_XDP_TCK0

PCH_JTAG_TCK1

SOC_XDP_TRST#

RC4 51_0402_5%@

RC5 51_0402_5%@

RC6 51_0402_5%@

RC8 51_0402_5%@

RC9 51_0402_5%@

RC13 51_0402_5%

+1.0VS_VCCIO

1 2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

SKL-U(1/12)DDI,EDP,MISC,CMC

Document Number Re v

Custom

LA-D562P

E

6 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

4

3

2

1

'()

D D

DDR_A_D[0..15][18]

DDR_A_D[16..31][18]

C C

DDR_A_D[32..47][18]

DDR_A_D[48..63][18]

B B

UC1B

DDR_A_D0

AL71

DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

Interleave / Non-Interleaved

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKL-U_BGA1356

@

 *!+,"

DDR_VTT_CNTL to DDR VTT supplied ramped <35u S (tCPU 18)

DDR_PG_CTRL

NC1VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

SA00007WE00

SKL-U

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSP[3]/DDR0_DQSP[5]

DDR0_DQSN[4]/DDR1_DQSN[0]

DDR0_DQSP[4]/DDR1_DQSP[0]

DDR0_DQSN[5]/DDR1_DQSN[1]

DDR0_DQSP[5]/DDR1_DQSP[1]

DDR0_DQSN[6]/DDR1_DQSN[4]

DDR0_DQSP[6]/DDR1_DQSP[4]

DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

2 OF 20

1

CC1

0.1U_0201_10V6K

2

UC8

5

4

Y

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR3L / LPDDR3 / DDR4

DDR0_MA[3]

DDR0_MA[4] DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

Interleave / Non-Interleaved

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA

DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

+3VS+1.2V +3VALW

12

CRB ORB

RC19

@

220K_0402_5%

Rev_1.0

12

RC20 100K_0402_5%

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54 AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50

BA50 BB52 AM70 AM69 AT69 AT70

BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26

AW50 AT52

AY67 AY68 BA67

AW67

DDR_A_CLK#0 DDR_A_CLK0 DDR_A_CLK#1 DDR_A_CLK1

DDR_A_CKE0 DDR_A_CKE1

DDR_A_CS#0 DDR_A_CS#1 DDR_A_ODT0 DDR_A_ODT1

DDR_A_MA5 DDR_A_MA9 DDR_A_MA6 DDR_A_MA8 DDR_A_MA7 DDR_A_BG0 DDR_A_MA12 DDR_A_MA11 M_A_ACT# DDR_A_BG1 DDR_A_MA13 DDR_A_MA15 DDR_A_MA14 DDR_A_MA16 DDR_A_BA0 DDR_A_MA2 DDR_A_BA1 DDR_A_MA10 DDR_A_MA1 DDR_A_MA0

DDR_A_MA3 DDR_A_MA4 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1

DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7

+0.6V_VREFCA

+0.6V_B_VREFDQ

DDR_PG_CTRL

DDR_VTT_PG_CTRL [54]

DDR_A_CLK#0 [18] DDR_A_CLK0 [18]

T10@ T13@

DDR_A_CKE0 [18,20]

T11@

DDR_A_CS#0 [18,20]

T14@

DDR_A_ODT0 [18,20]

T12@

DDR_A_MA5 [18,20] DDR_A_MA9 [18,20] DDR_A_MA6 [18,20] DDR_A_MA8 [18,20] DDR_A_MA7 [18,20] DDR_A_BG0 [18,20] DDR_A_MA12 [18,20] DDR_A_MA11 [18,20] M_A_ACT# [18,20] DDR_A_BG1 [18] DDR_A_MA13 [18,20] DDR_A_MA15 [18,20] DDR_A_MA14 [18,20] DDR_A_MA16 [18,20] DDR_A_BA0 [18,20] DDR_A_MA2 [18,20] DDR_A_BA1 [18,20] DDR_A_MA10 [18,20] DDR_A_MA1 [18,20] DDR_A_MA0 [18,20]

DDR_A_MA3 [18,20] DDR_A_MA4 [18,20] DDR_A_DQS#0 [18] DDR_A_DQS0 [18] DDR_A_DQS#1 [18] DDR_A_DQS1 [18]

DDR_A_DQS#2 [18] DDR_A_DQS2 [18] DDR_A_DQS#3 [18] DDR_A_DQS3 [18] DDR_A_DQS#4 [18] DDR_A_DQS4 [18] DDR_A_DQS#5 [18] DDR_A_DQS5 [18] DDR_A_DQS#6 [18] DDR_A_DQS6 [18] DDR_A_DQS#7 [18] DDR_A_DQS7 [18]

DDR_A_ALERT# [18] DDR_A_PARITY [18,20]

+0.6V_VREFCA [18]

T16@

+0.6V_B_VREFDQ [19]

DDR_B_D[0..15][19]

DDR_B_D[16..31][19]

DDR_B_D[32..47][19]

DDR_B_D[48..63][19]

Trace width/Spacing >= 20mils Place componment near SODIMM

#543016 PDG0.9 P.163 RC place near SODIMM

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47

DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

UC1C

Interleave / Non-Interleaved

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKL-U_BGA1356

@

SKL-U

DDR3L / LPDDR3 / DDR4

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

Interleave / Non-Interleaved

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

3 OF 20

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

Rev_1.0

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52 BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46

BB46 BA47

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32

AR25 AR27 AR22 AR21 AN43 AP43 AT13 AR18 AT18 AU18

DDR_B_CLK#0 DDR_B_CLK#1 DDR_B_CLK0 DDR_B_CLK1

DDR_B_CKE0 DDR_B_CKE1

DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0 DDR_B_ODT1

DDR_B_MA5 DDR_B_MA9 DDR_B_MA6 DDR_B_MA8 DDR_B_MA7 DDR_B_BG0 DDR_B_MA12 DDR_B_MA11 M_B_ACT# DDR_B_BG1 DDR_B_MA13 DDR_B_MA15 DDR_B_MA14 DDR_B_MA16 DDR_B_BA0 DDR_B_MA2 DDR_B_BA1 DDR_B_MA10 DDR_B_MA1 DDR_B_MA0

DDR_B_MA3 DDR_B_MA4

DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5

DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_ALERT# DDR_B_PARITY DDR_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

#543016 PDG0.9 P.117 W=12-15 Space= 20/25 L=500mil

DDR_DRAMRST#

RC15 200_0402_1% RC16 80.6_0402_1% RC17 100_0402_1%

+1.2V

12

DDR_B_CLK#0 [19] DDR_B_CLK#1 [19] DDR_B_CLK0 [19] DDR_B_CLK1 [19]

DDR_B_CKE0 [19] DDR_B_CKE1 [19]

DDR_B_CS#0 [19] DDR_B_CS#1 [19] DDR_B_ODT0 [19] DDR_B_ODT1 [19]

DDR_B_MA5 [19] DDR_B_MA9 [19] DDR_B_MA6 [19] DDR_B_MA8 [19] DDR_B_MA7 [19] DDR_B_BG0 [19] DDR_B_MA12 [19] DDR_B_MA11 [19] M_B_ACT# [19] DDR_B_BG1 [19] DDR_B_MA13 [19] DDR_B_MA15 [19] DDR_B_MA14 [19] DDR_B_MA16 [19] DDR_B_BA0 [19] DDR_B_MA2 [19] DDR_B_BA1 [19] DDR_B_MA10 [19] DDR_B_MA1 [19] DDR_B_MA0 [19]

DDR_B_MA3 [19] DDR_B_MA4 [19]

DDR_B_DQS#0 [19] DDR_B_DQS0 [19] DDR_B_DQS#1 [19] DDR_B_DQS1 [19] DDR_B_DQS#2 [19] DDR_B_DQS2 [19] DDR_B_DQS#3 [19] DDR_B_DQS3 [19] DDR_B_DQS#4 [19] DDR_B_DQS4 [19] DDR_B_DQS#5 [19] DDR_B_DQS5 [19]

DDR_B_DQS#6 [19] DDR_B_DQS6 [19] DDR_B_DQS#7 [19] DDR_B_DQS7 [19] DDR_B_ALERT# [19] DDR_B_PARITY [19] DDR_DRAMRST# [18,19]

X76@

12 1 2 1 2

RC18 470_0402_5%

0606 : RC15 add X76@

!!!

- .  .

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/29 2016/01/29

2

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(2/12)DDR4

Size

Document Number Rev

Custom

Date: Sheet o f

Thursday, June 15, 2017

1

LA-D562P

7

0.1

66

Vinaﬁx.com

5

4

3

2

1

SMBALERT# (Internal Pull Down):

0 = Disable Intel ME TLS function ==> Default

1 = Enable Intel ME TLS function

SKL-U

LPC

5 OF 20

'-*01"

UC9

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

W25Q64FVSSIQ_SO8

/HOLD(IO3)

UC9

16M@

16M ROM

SA00005VV20

8M@

VCC

CLK

DI(IO0)

SMBUS, SMLINK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

8 7 6 5

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A10/CLKOUT_LPC1

+3VALW

CC2 0.1U_0201_10V6K

SOC_SPI_IO3_0_RSOC_SPI_SO_0_R SOC_SPI_CLK_0_R SOC_SPI_SI_0_R

Rev_1.0

GPP_C0/SMBCLK

GPP_C3/SML0CLK

GPP_C6/SML1CLK

GPP_A8/CLKRUN#

@

1 2

1

2

CC3 10P_0603_50V8-J

@EMI@

R7 R8 R10

R9 W2 W1

W3 V3 AM7

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9 AW11

SOC_SMBCLK SOC_SMBDATA SOC_SMBALERT#

SOC_SML0CLK SOC_SML0DATA

SOC_SML0ALERT#

SOC_SML1CLK SOC_SML1DATA

SOC_SML1ALERT#

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME#

LPC_CLK0

RC24 22_0402_1%EMI@

LPC_CLK1

RC102 22_0402_1%EMI@

1

@RF@

CC95 33P_0402_50V8J

2

SOC_SMBCLK [19] SOC_SMBDATA [19]

T17TP@

T18TP@

SOC_SML1CLK [22,39,45,46] SOC_SML1DATA [22,39,45,46]

LPC_AD0 [27,45] LPC_AD1 [27,45] LPC_AD2 [27,45] LPC_AD3 [27,45]

LPC_FRAME# [27,45]

1 2 1 2

CLKRUN#

SOC_SML1ALERT#

SOC_SML0CLK

SOC_SML0DATA

SOC_SMBCLK SOC_SMBDATA SOC_SML1DATA SOC_SML1CLK

CLKRUN#

RC26 150K_0402_5%@

RC27 499_0402_1%

RC28 499_0402_1%

RC30 8.2K_0402_5%

Follow 543016_SKL_U_Y_PDG_0_9

AV2 AW3 AV3 AW2 AU4 AU3 AU2 AU1

AW13

AY11

M2 M3

J4 V1 V2

M1

G3 G2 G1

UC1E

SKL-U_BGA1356

@

SPI - FLASH

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

C LINK

CL_CLK CL_DATA CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

D D

C C

+3VALW

1 2

RC21 10K_0402_5%

1 2

RC22 1K_0402_5%@

1 2

RC23 1K_0402_5%@

+1.8VS_3VS_PGPPA

1 2

RC25 8.2K_0402_5%

KB_RST#

SOC_SPI_IO2

SOC_SPI_IO3

SERIRQ

SOC_SPI_CLK SOC_SPI_SO SOC_SPI_SI SOC_SPI_IO2 SOC_SPI_IO3 SOC_SPI_CS#0

KB_RST#[45]

SERIRQ[27,45]

KB_RST#

SERIRQ

RPC1, RPC3 and RC30 are close to UC3

RPC1

SOC_SPI_IO2 SOC_SPI_SO SOC_SPI_SI



B B

EC_SPI_CS0#[45]

/

EC_SPI_MOSI[45] EC_SPI_CLK[45]

EC_SPI_MISO[45]

SOC_SPI_IO3

EC_SPI_CS0# SOC_SPI_CS#0 EC_SPI_MOSI SOC_SPI_SI_0_R EC_SPI_CLK SOC_SPI_CLK_0_R

+3VALW

RC110

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

1 2

RC29 33_0402_5%EMI@

RPC3

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

1 2

10K_0402_5%

EMI@

SOC_SPI_IO2_0_R SOC_SPI_SO_0_R SOC_SPI_SI_0_R SOC_SPI_IO3_0_R

SOC_SPI_CLK_0_RSOC_SPI_CLK

EMI@

SOC_SPI_SO_0_REC_SPI_MISO

SOC_SPI_CS#0

SOC_SPI_IO2_0_R

SML0ALERT# (Internal Pull Down):

eSPI or LPC

0 = LPC is selected for EC ==> Default

1 = eSPI is selected for EC

SMB

(Link to DDR)

SML1

(Link to EC,DGPU,CRT,APS,RTS5455)

CK_LPC_KBC [45] CK_LPC_TPM [27] CLKRUN# [45]

+3VS

12

1 2

RPC2

1 8 2 7 3 6 4 5

1K_0804_8P4R_5%

+1.8VS_3VS_PGPPA

1 2

@

For ENE auto load search code V12

A A

Security Classification

2014/05/19 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2014/05/19 2015/12/31

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

SKL-U(3/12)SPI,SMB,LPC,ESPI

Document Number Re v

LA-D562P

8 66Thursday, June 15, 2017

1

0.1

Vinaﬁx.com

5

4

3

2

1

2!3!'*"

RPC4

EMI@

HDA_BITCLK_AUDIO[35] HDA_SYNC_AUDIO[35] HDA_SDOUT_AUDIO[35]

D D

C C

HDA_RST_AUDIO#[35]

+3VS

RC32 2.2K_0402_5%

1 2

1 8 2 7 3 6 4 5

HDA_SPKR

@

SPKR (Internal Pull Down):

TOP Swap Override

B B

0 = Disable TOP Swap mode. ==> Default

1 = Enable TOP Swap Mode.

HDA_BIT_CLK HDA_SYNC ME_EN HDA_RST#

33_0804_8P4R_5%

/%/*("

UC1G

HDA_SYNC[44] HDA_BIT_CLK[44]

ME_EN[44,45]

HDA_SDIN0[35]

HDA_RST#[44]

DDI_PRIORITY[38]

HDA_SPKR[35]

HDA_SYNC HDA_BIT_CLK ME_EN

HDA_RST#

DDI_PRIORITY

HDA_SPKR

BA22 AY22 BB22 BA21 AY21

AW22

AY20

AW20

AK7 AK6 AK9

AK10

AW5

A36 B36 C38 D38 C36 D36 A38 B38

C31 D31 C33 D33 A31 B31 A33 B33

A29 B29 C28 D28 A27 B27 C27 D27

J5

H5 D7

D8 C8

AUDIO

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKL-U_BGA1356

@

UC1I

CSI-2

CSI2_DN0 CSI2_DP0 CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3

CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7

CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11

SKL-U_BGA1356

@

SKL-U

9 OF 20

GPP_A17/SD_PWR_EN#/ISH_GP7

7 OF 20

Rev_1.0

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

SDIO / SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

C37 D37 C32 D32 C29 D29 B26 A26

E13

RC33 100_0402_1%@

B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

RC34 200_0402_1%@

Rev_1.0

SD_RCOMP

GPP_F23

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

12

RC31 200_0402_1%@

12

A A

Security Classification

2014/05/19 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2014/05/19 2015/12/31

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

SKL-U(4/12)HDA,EMMC,SDIO,CSI2

Document Number Re v

Thursday, June 15, 2017

LA-D562P

66

9

1

66

0.1

Vinaﬁx.com

5

+3VS

RPC5

EC_SCI#

18

WLANCLK_REQ#

27

M2CLK_REQ#

36

LANCLK_REQ#

D D

RC36 10K_0402_5%UMA@

RC37 10K_0402_5%

+3VL_RTC

C C

+3VALW

45

10K_0804_8P4R_5%

1 2

GPUCLK_REQ#

DIS@

1 2

RC40 20K_0201_5%

1 2

CC6 1U_0402_6.3V6K

1 2

RC41 20K_0402_5%

1 2

CC7 1U_0402_6.3V6K

1 2

CLRP1 SHORT PADS

1 2

RC44 1M_0402_5%

RPC6

PCH_PWROK

18

EC_RSMRST#

27

LAN_WAKE#

36

SYS_RESET#

45

10K_0804_8P4R_5%

EC_SCI# [6,45]

SOC_SRTCRST#

SOC_RTCRST#

CLR CMOS

SM_INTRUDER#

RC42

1 2

0_0402_5%

/!

1 2

ESD@

CC11 100P_0402_50V8J

1 2

ESD@

CC12 100P_0402_50V8J

1 2

ESD@

CC13 100P_0402_50V8J

B B

1 2

RC107 10K_0402_5%

+3VALW

1 2

RC49 1K_0402_5%

SYS_RESET#

EC_RSMRST#

SYS_PWROK

WAKE#

EC_RSMRST# PCH_DPWROK

Only For Power Sequence Debug

4

DGPU

LAN

NGFF WL+BT(KEY E)

M.2 PCIE SSD

EC_CLEAR_CMOS# [45]

1 2

RC47 0_0402_5%

3

0606 change

UC1J

CLK_PCIE_GPU#[21] CLK_PCIE_GPU[21]

GPUCLK_REQ#[22]

CLK_PCIE_LAN#[36] CLK_PCIE_LAN[36] LANCLK_REQ#[36]

CLK_PCIE_WLAN#[31] CLK_PCIE_WLAN[31] WLANCLK_REQ#[31]

CLK_PCIE_M2#[32] CLK_PCIE_M2[32] M2CLK_REQ#[32 ]

GPUCLK_REQ#

LANCLK_REQ#

WLANCLK_REQ#

M2CLK_REQ#

2 4-5&$ $  "

SOC_PLTRST# SYS_RESET#

EC_RSMRST#[45]

PCH_PWROK[45]

T21 TP@

SYS_PWROK[45]

T24 TP@

EC_RSMRST#

H_CPUPWRGD EC_VCCST_PG

SYS_PWROK PCH_PWROK PCH_DPWROK

SUSWARN#

WAKE# LAN_WAKE#

D42 C42

AR10

B42 A42 AT7

D41 C41 AT8

D40 C40

AT10

B40 A40 AU8

E40 E38 AU7

SOC_PLTRST#

TC7SH08FUF_SSOP5

UC1K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKL-U_BGA1356

@

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 GPP_B5/SRCCLKREQ0#

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 GPP_B6/SRCCLKREQ1#

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 GPP_B7/SRCCLKREQ2#

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 GPP_B8/SRCCLKREQ3#

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 GPP_B9/SRCCLKREQ4#

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 GPP_B10/SRCCLKREQ5#

SKL-U_BGA1356

@

RC43

1 2

0_0402_5%

+3VS

5

UC11

1

P

B

2

A

G

3

@

SYSTEM POWER MANAGEMENT

SKL-U

CLOCK SIGNALS

10 OF 20

4

Y

12

RC46

100K_0402_5%

12

SKL-U

11 OF 20

PCIRST# [21,27,31,32,36,45]

CC8 100P_0402_50V8J

ESD@

GPP_B11/EXT_PWR_GATE#

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

Rev_1.0

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B2/VRALERT#

Rev_1.0

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

AM10 AM11

F43 E43

BA17

E37 E35

E42

AM18 AM20

AN18 AM16

2

SOC_XTAL24_IN

SOC_XTAL24_OUT

SUSCLK

SOC_XTAL24_IN SOC_XTAL24_OUT

XCLK_BIASREF

SOC_RTCX1 SOC_RTCX2

SOC_SRTCRST# SOC_RTCRST#

PM_SLP_S0# PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#

SLP_WLAN# PM_SLP_A#

PBTN_OUT# AC_PRESENT PM_BATLOW#

SM_INTRUDER#

SOC_VRALERT#

1 2

RC101 33_0201_1%

EMI@

1 2

RC100 33_0201_1%

EMI@

24MHZ_18PF_XRCGB24M000F2P51R0

SUSCLK [31]

T19TP@

PM_SLP_S3# [45] PM_SLP_S4# [45,54]

T20TP@

T22TP@

T23TP@

1 2

RC48 0_0402_5%

YC1

U23@

SJ10000UJ00

CC4

27P_0402_50V8J

U23@

SE071270J80

SOC_XTAL24_IN_R

SOC_XTAL24_OUT_R

YC1 24MHZ_18PF_XRCGB24M000F2P51R0

3

CC4

27P_0402_50V8J

1

U22@

2

YC1 need to be replaced by

38.4MHz (30ohm ESR) XTAL for Cannonlake-U

XCLK_BIASREF

1

U22@

1 2

RC35 1M_0402_5%

SJ10000UJ00U22@

NC

2

4

1 2

@

1

3

RC38 2.7K_0402_1%

RC39 60.4_0402_1%

RC35 1M_0402_5%

U23@ SD028100480

CC5

27P_0402_50V8J

1

U22@

2

+1.0V_CLK5_F24NS

Follow 546765_2014WW48_Skylake_MOW_Rev_1_0

Stuff 2.7k ohm(RC35) PU for Skylake-U

Stuff 60.4 ohm(RC110) PD for Cannonlake-U

SOC_RTCX2

SOC_RTCX1

PBTN_OUT# [45]

AC_PRESENT_R [45]

PM_BATLOW#

SOC_VRALERT#

1 2

RC45 10M_0402_5%

YC2

1 2

32.768KHZ 9PF 20PPM 9H03280012

1

CC9

4.7P_0402_50V8B

2

1 2

RC50 8.2K_0402_5%

1 2

@

RC51 10K_0402_5%

1

CC10

4.7P_0402_50V8B

2

+3VALW

CC5 27P_0402_50V8J

U23@ SE071270J80

/6*0!7

A A

VCCST_PWRGD[45]

5

+1.0V_VCCST

12

RC52 1K_0402_5%

1 2

RC53 60.4_0402_1%

EC_VCCST_PG

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(5/12)CLK,PM,GPIO

Size

Document Number Re v

Custom

Date: Sheet of

2

Date: Sheet of

LA-D562P

1

10 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

4

3

2

1





 

12

RC55 10K_0402_5%

X76@

12

RC57 10K_0402_5%

X76@

OBRAM_ID2 OBRAM_ID0 OBRAM_ID1 GSPI0_MOSI

GSPI1_MOSI

WLBT_OFF#

UART_2_CRXD_DTXDUART_2_CRXD_DTXD UART_2_CTXD_DRXD

I2C1_SDA_TP I2C1_SCL_TP

*5-39'!





AM5 AN7 AP5 AN5

AB1 AB2

AB3

AD1 AD2 AD3 AD4

AH9

AH10

AH11 AH12

AF11 AF12

12

RC54 10K_0402_5%

X76@

12

RC56 10K_0402_5%

X76@

UC1F

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL

SKL-U_BGA1356

@

LPSS ISH

SKL-U

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6

6 OF 20

GPP_D15/ISH_UART0_RTS#

Rev_1.0

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

P2 P3 P4 P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

DGPU_PWR_EN

AC1

DGPU_HOLD_RST#

AC2

DGPU_PWROK

AC3

DGPU_PRSNT#

AB4

AOU_STRAP

AY8

TPM_STRAP

BA8

TPM_STRAP2

BB7

APS_STRAP

BA7

PD_STRAP

AY7

ULTBY_STRAP

AW7 AP13

DGPU_PWR_EN [23,45,57,58] DGPU_HOLD_RST# [21] DGPU_PWROK [57,58]

RPC7

DGPU_HOLD_RST# DGPU_PWR_EN DGPU_PWROK DGPU_PRSNT#

DIS@ 1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

DGPU_PRSNT# PD for DIS SKU

&  

3

!'

+3VS

RC62 10K_0402_5%UMA@

89





1 2

+3VS

DGPU_PRSNT#

-3(

2)



*5-39'!

*5-39'!

  



&



D D

GSPI0_MOSI (Internal Pull Down):

No Reboot

0 = Disable No Reboot mode. ==> Default

1 = Enable No Reboot Mode. (PCH will disable the TCO Timer system reboot feature). This function is useful when running ITP/XDP.

GSPI1_MOSI (Internal Pull Down):

Boot BIOS Strap Bit

0 = SPI Mode ==> Default

+3VS

C C

+3VS

1 = LPC Mode

1 2

@

RC58 2.2K_0402_5%

1 2

@

RC59 2.2K_0402_5%

1 2

RC103 10K_0402_5%

1 2

RC106 10K_0402_5%

1 2

RC60 49.9K_0402_1%

1 2

RC61 49.9K_0402_1%

1 2

R469 2.2K_0201_ 5%

1 2

R470 2.2K_0201_ 5%

UART_2_CTXD_DRXD

GSPI0_MOSI

GSPI1_MOSI

WLBT_OFF#

DMIC_DET#

I2C1_SDA_TP

I2C1_SCL_TP

+3VS +3VS +3VS

-(

12

RC105 10K_0402_5%

X76@

OBRAM_ID2 OBRAM_ID1 OBRAM_ID0

12

RC104 10K_0402_5%

X76@

TP_INT#[33]

DMIC_DET#[28]

WLBT_OFF#[31]

UART_2_CRXD_DTXD[31] UART_2_CTXD_DRXD[31]

I2C1_SDA_TP[33] I2C1_SCL_TP[33]

B B

&  

8931

3* 

:*:3*

AOU_STRAP

&  

4-353? 

:*4-353?

ULTBY_STRAP PD_STRAP

A A

5

4



893>



12

RC11210K_0402_5% AOU@

12

RC11110K_0402_5% NONAOU@

+3VS +3VS

12

RC11410K_0402_5% BATT2@

12

RC11310K_0402_5% NOBATT2@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

&  

3 

:*3

APS_STRAP

&  

!

:*!

893

+3VS+3VS



TPM_STRAP

TPM_STRAP2

893

12

RC10810K_0402_5% APS@

12

RC10910K_0402_5% NOAPS@





12

RC11610K_0402_5% TYPEC@

12

RC11510K_0402_5% NONTYPEC@

Compal Secret Data

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

2

R3163

TCM@

10K_0402_5%

SD028100280

NOTPM@

TPM@

TCM@

NOTPM@

+3VS

12

R316310K_0402_5%

12

R316410K_0402_5%

+3VS

12

R316510K_0402_5%

12

R316610K_0402_5%

Title

Size

Document Number Re v

Custom

Date: Sheet of

&  

:*





R3165

TPM@

10K_0402_5%

SD028100280

Compal Electronics, Inc.

SKL-U(6/12)GPIO,I2C,GSPI

LA-D562P

1

29;8 38 3<=

93-

93-









11 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

4

3

2

1

UC1H

D D

PCIE_CRX_GTX_N1[21] PCIE_CRX_GTX_P1[21]

PCIE_CTX_C_GRX_N1[21] PCIE_CTX_C_GRX_P1[21]

PCIE_CRX_GTX_N2[21]

PCIE_CRX_GTX_P2[21]

PCIE_CTX_C_GRX_N2[21]

dGPU

LAN

C C

M.2 WLAN

HDD

M.2 SATA/PC IE*4

B B

When PCIE8/SATA1A is used as SATA Port 1 (ODD), then PCIE11/SATA1B (M.2 SSD) cannot be used as SATA Port 1.

PCIE_CTX_C_GRX_P2[21]

PCIE_CRX_GTX_N3[21] PCIE_CRX_GTX_P3[21]

PCIE_CTX_C_GRX_N3[21]

PCIE_CTX_C_GRX_P3[21]

PCIE_CRX_GTX_N4[21] PCIE_CRX_GTX_P4[21]

PCIE_CTX_C_GRX_N4[21] PCIE_CTX_C_GRX_P4[21]

PCIE_CRX_DTX_N5[36] PCIE_CRX_DTX_P5[36]

PCIE_CTX_C_DRX_N5[36]

PCIE_CTX_C_DRX_P5[36]

PCIE_CRX_DTX_N6[31]

PCIE_CRX_DTX_P6[31] PCIE_CTX_DRX_N6[31] PCIE_CTX_DRX_P6[31]

SATA_CRX_DTX_N0[30] SATA_CRX_DTX_P0[30] SATA_CTX_DRX_N0[30] SATA_CTX_DRX_P0[30]

PCIE_CRX_DTX_N9[32] PCIE_CRX_DTX_P9[32] PCIE_CTX_DRX_N9[32] PCIE_CTX_DRX_P9[32]

PCIE_CRX_DTX_N10[32] PCIE_CRX_DTX_P10[32] PCIE_CTX_DRX_N10[32] PCIE_CTX_DRX_P10[32]

PCIE_CRX_DTX_N11[32]

PCIE_CRX_DTX_P11[32] PCIE_CTX_DRX_N11[32] PCIE_CTX_DRX_P11[32]

PCIE_CRX_DTX_N12[32]

PCIE_CRX_DTX_P12[32] PCIE_CTX_DRX_N12[32] PCIE_CTX_DRX_P12[32]

0222 change net name

1 2

CC18 0.22U_0402_6.3V6KDIS@

1 2

CC19 0.22U_0402_6.3V6KDIS@

1 2

CC14 0.22U_0402_6.3V6KDIS@

1 2

CC15 0.22U_0402_6.3V6KDIS@

1 2

CC16 0.22U_0402_6.3V6KDIS@

1 2

CC17 0.22U_0402_6.3V6KDIS@

1 2

CC20 0.22U_0402_6.3V6KDIS@

1 2

CC21 0.22U_0402_6.3V6KDIS@

1 2

CC22 0.1U_0201_10V6K

1 2

CC23 0.1U_0201_10V6K

1 2

RC66 100_0402_1%

T25 TP@ T26 TP@

PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P1 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P1

PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P2

PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P3

PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P4 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P4

PCIE_CRX_DTX_N5 PCIE_CRX_DTX_P5 PCIE_CTX_DRX_N5 PCIE_CTX_DRX_P5

PCIE_CRX_DTX_N6 PCIE_CRX_DTX_P6 PCIE_CTX_DRX_N6 PCIE_CTX_DRX_P6

PCIE_RCOMPN PCIE_RCOMPP

XDP_PRDY# XDP_PREQ#

PCIE / USB3 / SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL-U_BGA1356

@

SKL-U

8 OF 20

SSIC / USB3

USB3_2_RXN / SSIC_RXN USB3_2_RXP / SSIC_RXP

USB3_2_TXN / SSIC_TXN USB3_2_TXP / SSIC_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

Rev_1.0

USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_3_RXN USB3_3_RXP USB3_3_TXN USB3_3_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

USB2N_5

USB2P_5

USB2N_6

USB2P_6

USB2N_7

USB2P_7

USB2N_8

USB2P_8

USB2N_9

USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

USB20_N1

AB9

USB20_P1

AB10

USB20_N2

AD6

USB20_P2

AD7

USB20_N3

AH3

USB20_P3

AJ3

USB20_N4

AD9

USB20_P4

AD10

USB20_N5

AJ1

USB20_P5

AJ2

USB20_N6

AF6

USB20_P6

AF7

USB20_N7

AH1

USB20_P7

AH2

USB20_N8

AF8

USB20_P8

AF9

USB20_N9

AG1

USB20_P9

AG2

AH7 AH8

USB2_COMP

AB6

USB2_ID

AG3

USB2_VBUSSENSE

AG4

USB_OC0#

A9

USB_OC1#

C9

USB_OC2#

D9

USB_OC3#

B9

J1 J2 J3

H2 H3 G4

PCH_SATALED#

H1

USB3_RX_N1 [34]

USB3_RX_P1 [34]

USB3_TX_N1 [34]

USB3_TX_P1 [34]

USB3_RX_N2 [34]

USB3_RX_P2 [34]

USB3_TX_N2 [34]

USB3_TX_P2 [34]

USB3_RX_N3 [42]

USB3_RX_P3 [42]

USB3_TX_N3 [42]

USB3_TX_P3 [42]

USB3_RX_N4 [40]

USB3_RX_P4 [40]

USB3_TX_N4 [40]

USB3_TX_P4 [40]

USB20_N1 [34] USB20_P1 [34]

USB20_N2 [34] USB20_P2 [34]

USB20_N3 [43] USB20_P3 [43]

USB20_N4 [41] USB20_P4 [41]

USB20_N5 [28] USB20_P5 [28]

USB20_N6 [31] USB20_P6 [31]

USB20_N7 [37] USB20_P7 [37]

USB20_N8 [33] USB20_P8 [33]

USB20_N9 [46] USB20_P9 [46]

1 2

RC64 113_0402_1%

1 2

RC65 1K_0402_5%

1 2

RC67 1K_0402_5%

USB_OC0# [34] USB_OC1# [34] USB_OC2# [46]

EC_WL_OFF# [31]

PCH_SATALED# [33]

USB3(AOU)

USB3(Type-A)

USB3(Type-C)

USB3(Type-C Full)

USB2(AOU)

USB2(Type-A)

USB2(Type-C)

USB2(Type-C Full)

Camera

M.2 BT

Card Reader

Finger Print

2nd Battery

USB_OC2# USB_OC1# USB_OC0# USB_OC3#

+3VS

12

R235 10K_0402_5%

RPC8

10K_0804_8P4R_5%

SATA_GP2 [32]

+3VALW

18 27 36 45

+3VS

A A

Security Classification

2014/05/19 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2014/05/19 2015/12/31

3

Compal Secret Data

Deciphered Date

Title

SKL-U(7/12)PCIE,USB,SATA

Size

Document Number Re v

Custom

Date : Sheet o f

2

Date : Sheet o f

PCH_SATALED#

Compal Electronics, Inc.

1 2

RC68 10K_0402_5%

LA-D562P

1

0.1

12 66Thursday, June 15, 2017

Vinaﬁx.com

5

+1.0VALW TO +1.0V_VCCST

D D

+5VALW +1.0V_VCCST+1.0VALW

RC69

SYSON[44,45,54]

C C

1 2

47K_0402_5%

EN_1.0V_VCCSTU

0.1U_0402_25V6 CC29

12

1U_0402_6.3V6K

CC24

1

2

CC25

1

2

4

I(Max) : 0.16 A(+1.0V_VCCST) RON(Max) : 25 mohm V drop : 0.004 V

UC12

1

VOUT

VIN

2

VOUT

VIN

3

4

1U_0402_6.3V6K

TPS22967DSGR_SON8_2X2

ON

VBIAS

GND GND

CT

3

Follow 543977_SKL_PDDG_Rev0_91 CC24 10PF ->22us(Spec:<= 65us)

+1.0VS_VCCIO

+1.0V_VCCST

7 8

6

5 9

10P_0402_50V8J

1

CC27

2

0.1U_0201_10V6K

CC26

1

2

+1.2V

AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51

AM40

A18

A22

AL23

K20 K21

2

SKL-U

UC1N

VDDQ_AU23 VDDQ_AU28 VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51

VDDQC

VCCST

VCCSTG_A22

VCCPLL_OC

VCCPLL_K20 VCCPLL_K21

SKL-U_BGA1356

@

+1.0VS_VCCIO

CPU POWER 3 OF 4

14 OF 20

Rev_1.0

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE VCCSA_SENSE

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

VSSSA_SENSE VCCSA_SENSE

Trace Length Match < 25 mils

+VCCSA

1

VSSSA_SENSE [59] VCCSA_SENSE [59]

+1.0VALW TO +1.0VS_VCCIO

+5VALW

@

SUSP#[44,45,54,63]

B B

A A

SUSP#

5

1 2

RC72 0_0402_5%

+1.0VALW

0.1U_0201_10V6K

CC33

1

2

1U_0402_6.3V6K

CC34

1

2

12

@

+1.0VS_VCCIO

1

@

2

I(Max) : 3.04 A(+1.0VS_VCCIO) RON(Max) : 6.2 mohm V drop : 0.019 V

UC13

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

CC39

10U_0603_6.3V6M

1

CC40

@

2

ON

TPS22961DNYR_WSON8

1U_0402_6.3V6K

CC42

CC41

1

@

2

4

0.1U_0402_25V6

10P_0402_25V8J

VOUT

GND

1

CC96

RF@

2

+1.0VS_VCCIO_STG

6

5

1

2

+1.0VS_VCCIO

RC71

1 2

0_0805_5%

PSC SideBSC Side BSC SidePSC Side

1U_0402_6.3V6K

1

CC43

2

1U_0402_6.3V6K

CC44

1

2

CC46

CC45

2

Close to CPUUnderneath CPU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

CC38

@

0.1U_0201_10V6K

2

+1.2V

BSC Side

1U_0402_6.3V6K

1

2

10U_0603_6.3V6M

1

CC47

2

22U_0603_6.3V6M

1

CC48

CC49

2

Close to CPUClose to AM40 Underneath CPUClose to AL23

Compal Secret Data

2014/05/19 2015/12/31

3

Compal Secret Data

Deciphered Date

+1.0V_VCCST

+1.0VS_VCCIO

BSC SidePSC Side

1U_0402_6.3V6K

1

2

1

CC36

CC35

2

1U_0402_6.3V6K

1

CC37

@

2

Close to A18 Close to K20 Close to A22

1U_0402_6.3V6K

22U_0603_6.3V6M

1

CC50

2

10U_0603_6.3V6M

1

CC51

2

10U_0603_6.3V6M

1

CC52

CC53

@

2

Title

Size

Document Number Re v

Custom

Date : Sheet o f

1U_0402_6.3V6K

CC54

CC55

1

@

2

Compal Electronics, Inc.

SKL-U(8/12)Power

LA-D562P

0.1

13 66Thursday, June 15, 2017

1

Vinaﬁx.com

5

4

3

2

1

D D

C C

B B

Follow 543016_SKL_U_Y_PDG_1_0

+1.0VALW

LC1

MURATA BLM15EG221SN1D

1 2

SM01000HC00

RF@

R_0402

Follow 543016_SKL_U_Y_PDG_1_0

RC75

1 2

0_0603_5%

Follow 543016_SKL_U_Y_PDG_1_0

RC76

1 2

0_0603_5%

Follow 543016_SKL_U_Y_PDG_1_0

RC78

1 2

0_0603_5%

Follow 543016_SKL_U_Y_PDG_1_0

RC82

1 2

0_0603_5%

+1.0V_APLL

1

CC59

0.1U_0201_10V K X5R

RF@

2

+1.0V_AMPHYPLL

1U_0402_6.3V6K

22U_0603_6.3V6M

CC62

1

@

2

+1.0V_CLK5_F24NS

22U_0603_6.3V6M

1

@

2

+1.0V_CLK4_F100OC

22U_0603_6.3V6M

1

@

2

+1.0V_CLK6_24TBT

22U_0603_6.3V6M

1U_0402_6.3V6K

1

CC74

@

2

+1.0VALW

RC73

1 2

0_0805_5%

'BCD3

RC74

1 2

0_0805_5%

+3VALW

'B>C3

RC77

RF@

MURATA BLM15EG221SN1D

1 2

SM01000HC00

R_0402

LPC 3.3V

RC80

1 2

0_0402_5%

CC63

CC67

CC72

+1.0V_PRIM_CORE

1

2

@

+3.3V_HDA

0.1U_0201_10V K X5R

1

2

+3V_1.8V_PGPPA

+1.8VS_3VS_PGPPA

1U_0402_6.3V6K

1

CC60

@

2

+1.0V_MPHYGT

1U_0402_6.3V6K

22U_0603_6.3V6M

CC66

CC65

1

2

HD Audio : 3.3V or 1.5V

CC68

RF@

I2S : 1.8V or 3.3V

+3VALW

2

@

CC69

1

Close to AJ21

+1.0VALW

2

@

CC70

1

1U_0402_6.3V6K

Close to AF20 Close to N18

1 2

CC58 1U_0402_6.3V6K

@

+1.0V_PRIM_CORE

1 2

CC56 1U_0402_6.3V6K

1 2

CC57 1U_0402_6.3V6K

Close to K17

+1.0V_MPHYGT

+1.0V_AMPHYPLL

+1.0V_APLL

+3VALW

+3.3V_HDA

+3VALW

CC71

1U_0402_6.3V6K

Follow 543016_SKL_U_Y_PDG_1_0

CC75

+3VS

LPC 3.3V

RC84

1 2

0_0402_5%

+1.0VALW +3VALW +1.8VALW

22U_0603_6.3V6M

CC76

1

@

2

22U_0603_6.3V6M

CC77

1

@

2

22U_0603_6.3V6M

CC78

CC79

1

@

2

1

@

2

22U_0603_6.3V6M

CC80

@

+1.0VALW

2

1

1U_0402_6.3V6K

22U_0603_6.3V6M

CC81

1

2

DCPDSW

UC1O

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB_1P0

SKL-U_BGA1356

@

+3VALW

!DD D1$!!-)&$)

1U_0402_6.3V6K

1

CC82

@

2

SKL-U

CPU POWER 4 OF 4

15 OF 20

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE

VCCPGPPF

VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

1U_0402_6.3V6K

1

CC83

2

Rev_1.0

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

0.1U_0201_10V6K

1

2

+1.8VALW

+3VALW

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19

T1

AA1

AK17

AK19 BB14

BB10

A14

K19

L21

N20

L19

A10

AN11 AN13

DCPRTC

+3V_1.8V_PGPPA

VCCPGPPF support 1.8V only

+1.0VALW

1 2

CC61 1U_0402_6.3V6K

+3VL_RTC

1 2

CC64 0.1U_0201_10V6K

+1.0V_CLK6_24TBT

+1.0V_APLL

+1.0V_CLK4_F100OC

+1.0V_CLK5_F24NS

+1.0V_CLK6_24TBT

- 5  )

+3VL_RTC +RTCBATT

W=20mil s

1 2

RC81 0_0402_5%

1

CC73 1U_0402_6.3V6K

2

$ ) &    ( //   @ A-  

CC84

3@DE?E 38

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(9/12)Power

Size

Document Number Re v

Custom

Date: Sheet of

2

Date: Sheet of

LA-D562P

14 66Thursday, June 15, 2017

1

14 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

4

3

2

1

VCCGT_SENSE VSSGT_SENSE

+VCCGT +VCCGT+VCCCORE +VCCCORE

AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71

M62 N63 N64 N66 N67 N69

A48 A53 A58 A62 A66

J43 J45 J46 J48 J50 J52 J53 J55 J56 J58 J60 K48 K50 K52 K53 K55 K56 K58 K60 L62 L63 L64 L65 L66 L67 L68 L69 L70 L71

J70 J69

UC1M

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT_SENSE VSSGT_SENSE

SKL-U_BGA1356

@

SKL-U

CPU POWER 2 OF 4

13 OF 20

Rev_1.0

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70

VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56

VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63 VCCGTX_BB57 VCCGTX_BB66

VCCGTX_SENSE VSSGTX_SENSE

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

1 2

SKL@

RC86 0_0402_5%

VCCGTX_SENSE VSSGTX_SENSE

For GT3 SKU

T29 TP@ T30 TP@

+VCCGT

UC1L

A30

VCC_A30

A34

VCC_A34

D D

+1.0VS_VCCOPC

+1.8VALW

U23@

VCCOPC_SENSE VSSOPC_SENSE

+1.8V_VCCOPC

1 2

For GT3 SKU

C C

RC85 0_0402_5%

VCCOPC_SENSE[63] VSSOPC_SENSE[63]

SVID ALERT

B B

A39

A44 AK33 AK35 AK37 AK38 AK40 AL33 AL37 AL40

AM32 AM33 AM35 AM37 AM38

G30

K32

AK32

AB62

P62

V62

H63

G61

AC63 AE63

AE62

AG62

AL63 AJ62

+1.0V_VCCST

12

RC88 56_0402_5%

VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RSVD

VCCOPC_AB62 VCCOPC_P62 VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE VSSOPC_SENSE

VCCEOPIO VCCEOPIO

VCCEOPIO_SENSE VSSEOPIO_SENSE

SKL-U_BGA1356

@

Place the PU resistors close to CPU

SKL-U

CPU POWER 1 OF 4

12 OF 20

Rev_1.0

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42 VCC_J30 VCC_J33 VCC_J37 VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VCC_SENSE VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

B63 A63 D64

G20

Trace Length Match < 25 mils

VCCCORE_SENSE [59]

SOC_SVID_ALERT# VR_SVID_CLK VR_SVID_DATA

VSSCORE_SENSE [59]

VR_SVID_CLK [59]

ALERT signal must be routed between CLK and DATA signals

+1.0VS_VCCIO

0309 K52 and AK52 KEEP NC 563377_KBL_MOW_ WW09_March_201 7

--------------- ------- --SLK will connection add structure

VCCGT_SENSE[59] VSSGT_SENSE[59]

Trace Length Match < 25 mils

+VCC_GT_+VCC_CORE +VCC_GT_+VCC_CORE

+VCCGT

1 2

RC87 0_0402_5%SKL@

SOC_SVID_ALERT#

SVID DATA

VR_SVID_DATA

A A

5

1 2

RC89 220_0402_5%

+1.0V_VCCST

12

RC90 100_0402_5%

VR_ALERT# [59]

Place the PU resistors close to CPU

VR_SVID_DATA [59]

4

(To VR)

For CPU GT3 SKU

+1.0VS_VCCOPC

BSC Side BSC Side

10U_0603_6.3V6M

1

CC85

2

U23@

(To VR)

Close to AE62,AG62 Close to AB62,P62,V62

Security Classification

2014/05/19 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

3

Compal Secret Data

Deciphered Date

1U_0402_6.3V6K

10U_0603_6.3V6M

1

CC86

2

U23@

1U_0402_6.3V6K

10U_0603_6.3V6M

1

CC88

CC87

2

U23@

2

1U_0402_6.3V6K

CC89

1

2

U23@

Title

Size

Custom

Date : Sheet o f

CC91

CC90

2

U23@

Compal Electronics, Inc.

SKL-U(10/12)Power,SVID

Document Number Re v

LA-D562P

0.1

15 66Thursday, June 15, 2017

1

Vinaﬁx.com

5

4

3

2

1

D D

C C

B B

A67 A70 AA2

AA4 AA65 AA68 AB15 AB16 AB18 AB21

AB8 AD13 AD16 AD19 AD20 AD21 AD62

AD8 AE64 AE65 AE66 AE67 AE68 AE69

AF1

AF10 AF15 AF17

AF2

AF4

AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13

AH6 AH63 AH64 AH67

AJ15 AJ18 AJ20

AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69

AK8

AL2

AL28 AL32 AL35 AL38

AL4

AL45 AL48 AL52 AL55 AL58 AL64

A5

AJ4

UC1P

SKL-U_BGA1356

@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-U

GND 1 OF 3

16 OF 20

Rev_1.0

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

AT63 AT68

AT71 AU10 AU15 AU20 AU32 AU38

AV1 AV68 AV69 AV70 AV71

AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57

AW6 AW60 AW62 AW64 AW66

AW8

AY66

B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71

BA1 BA10 BA14 BA18

BA2 BA23 BA28 BA32 BA36

BA45

F68

UC1Q

SKL-U_BGA1356

@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-U

GND 2 OF 3

17 OF 20

Rev_1.0

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

UC1R

F8

VSS

G10

VSS

G22

VSS

G43

VSS

G45

VSS

G48

VSS

G5

VSS

G52

VSS

G55

VSS

G58

VSS

G6

VSS

G60

VSS

G63

VSS

G66

VSS

H15

VSS

H18

VSS

H71

VSS

J11

VSS

J13

VSS

J25

VSS

J28

VSS

J32

VSS

J35

VSS

J38

VSS

J42

VSS

J8

VSS

K16

VSS

K18

VSS

K22

VSS

K61

VSS

K63

VSS

K64

VSS

K65

VSS

K66

VSS

K67

VSS

K68

VSS

K70

VSS

K71

VSS

L11

VSS

L16

VSS

L17

VSS

SKL-U_BGA1356

@

SKL-U

GND 3 OF 3

18 OF 20

Rev_1.0

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

A A

Security Classification

2014/05/19 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2014/05/19 2015/12/31

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet o f

2

Date : Sheet o f

SKL-U(11/12)GND

Document Number Re v

LA-D562P

16 66Thursday, June 15, 2017

1

0.1

Vinaﬁx.com

5

D D

T33 TP@ T34 TP@ T35 TP@ T36 TP@ T37 TP@ T38 TP@ T31 TP@ T39 TP@ T32 TP@ T40 TP@ T41 TP@ T42 TP@ T43 TP@ T44 TP@ T45 TP@ T46 TP@

T47 TP@ T48 TP@

T49 TP@

C C

B B

1 2

RC98 49.9_0402_1%

1 2

RC99 1K_0402_5%

CFG_RCOMP

T50 TP@

T51 TP@

CFG4

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG17

CFG18 CFG19

CFG_RCOMP

XDP_ITP_PMODE

Display Port Presence Strap

1 : Disabled; No Physical Display Port

CFG4

A A

attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

E68 B67 D65 D67 E70 C68 D68 C67

G69

G68 H70 G71 H69 G70

E63

E66

E60

AY2 AY1

K46 K45

AL25 AL27

C71 B70

A52

BA70 BA68

G65

E61

4

F71

F70

F63

F66

E8

D1 D3

F60

J71 J68

F65

F61

UC1S

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2 RSVD_AY1

RSVD_D1 RSVD_D3

RSVD_K46 RSVD_K45

RSVD_AL25 RSVD_AL27

RSVD_C71 RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70 RSVD_TP_BA68

RSVD_J71 RSVD_J68

VSS_F65 VSS_G65

RSVD_F61 RSVD_E61

SKL-U_BGA1356

@

SKL-U

RESERVED SIGNALS-1

19 OF 20

Rev_1.0

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

TP5 TP6

RSVD_D5 RSVD_D4

RSVD_B2

RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4

RSVD_C4

TP4

RSVD_A69 RSVD_B69

RSVD_AY3

RSVD_D71 RSVD_C70

RSVD_C54 RSVD_D54

TP1 TP2

VSS_AY71

ZVM#

RSVD_TP RSVD_TP

MSM#

PROC_SELECT#

3

UC1T

RSVD_U12 RSVD_U11

AW69

RSVD_AW69

AW68

RSVD_AW68

AU56

RSVD_AU56

AW48

RSVD_AW48

C7

RSVD_C7

U12

RSVD_U12

U11

RSVD_U11

H11

RSVD_H11

SKL-U_BGA1356

@

+1.0V_VCCST

BB68 BB69

AK13 AK12

BB2 BA3

AU5 AT5

D5 D4 B2 C2

B3 A3

AW1

E1 E2

BA4 BB4

A4 C4

BB5

A69 B69

AY3

D71 C70

C54 D54

AY4 BB3

AY71 AR56

AW71 AW70

AP56 C64

42E_SOC_XTAL24_OUT_R

LPM_ZVM#

PM_MSM# SKL_CNL#

T52 TP@

RC97 100K_0402_5%

LPM_ZVM# [63]

1 2

@

Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0

Stuff 100k(RC97) for Cannonlake.

Un-stuff 100k(RC97) for Skylake

2

SKL-U

SPARE

20 OF 20

42E_SOC_XTAL24_IN_R

42E_SOC_XTAL24_OUT_R

Rev_1.0

RSVD_F6

RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12 RSVD_F52

LPM_ZVM#

F> &  

49G,H

9H

RC94 33_0201_1%EMI@

RC95 33_0201_1%EMI@

F6

42E_SOC_XTAL24_IN_R

E3 C11 B11 A11 D12 C12 F52

RSVD_U12

RSVD_U11

1 2

U23@

RC93 10K_0402_5%

1 2

42E_SOC_XTAL24_IN

42E_SOC_XTAL24_OUT

1

1 2

RC91 0_0402_5%@

1 2

RC92 0_0402_5%@

+3VS

1 2

RC96 1M_0402_5%U42@

YC3 24MHZ_18PF_XRCGB24M000F2P51R0

3

CC93

27P_0402_50V8J

1

U42@

2

1U_0402_6.3V6K

SJ10000UJ00U42@

NC

2

4

CC92

1

+1.8VALW

@

1

2

1

CC94

27P_0402_50V8J

1

U42@

2

Security Classification

2014/05/19 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2014/05/19 2015/12/31

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

SKL-U(12/12)CFG,RSVD

Document Number Re v

LA-D562P

17 66Thursday, June 15, 2017

1

0.1

Vinaﬁx.com

5

4

3

2

1

+DDR_VREF_CA

U2

M1

DDR_A_MA0

12

DDR_A_MA1 DDR_A_MA2

CD1

DDR_A_MA3 DDR_A_MA4 DDR_A_MA5

0.047U_0402_25V7K

DDR_A_MA6 DDR_A_MA7

D D

DDR_A_BA0[7,18,20] DDR_A_BA1[7,18,20]

DDR_A_CLK0[7,18] DDR_A_CLK#0[7,18] DDR_A_CKE0[7,18,20]

DDR_A_ODT0[7,20]

DDR_A_CS#0[7,18,20]

C C

DDR_A_ALERT#[7]

DDR_A_PARITY[7,20]

DDR_A_MA[0..16][7,20]

DDR_A_DQS#[0..7][7]

DDR_A_DQS[0..7][7]

DDR_A_D[0..63][7]

B B

DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BA0 DDR_A_BA1 DDR_A_BA1

+1.2V

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CKE0

DDR_A_ODT0 DDR_A_CS#0 DDR_A_MA16 DDR_A_MA15

DDR_A_DQS#1 DDR_A_DQS1 DDR_A_DQS#0 DDR_A_DQS0

MEMRST#

1 2

240_0402_1%

M_A_ACT#

M_A_ACT#[7,20]

DDR_A_BG0

DDR_A_BG0[7,20]

DDR_A_ALERT# DDR_A_PARITY

+2.5V

VREFCA

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC

T8

A13

L2

A14/WE

N2

BA0

N8

BA1

E2

DMU/DBIU

E7

DML/DBIL

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

L8

RAS

M8

CAS

A7

DQSU_c

B7

DQSU_t

F3

DQSL_c

G3

DQSL_t

P1

RESET

F9

RD23

ZQ

L3

ACT

M2

BG0

N9

TEN

P9

ALERT

T3

PAR

T7

NC

B1

VPP

R9

VPP

96-BALL

SDRAM DDR4

K4A8G165WB-BCPB_FBGA96

X76@

CLOCK TERMINATION

DDR_DRAMRST#[7,19]

DDR_A_CLK0 DDR_A_CLK#0

RD18 36_0402_1% RD19 36_0402_1%

DDR_A_ALERT#

RD2 49.9_0402_1%

DDR_DRAMRST#

1 2 1 2

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS

DDR_A_D5

G2

DDR_A_D6

F7

DDR_A_D1

H3

DDR_A_D2

H7

DDR_A_D4

H2

DDR_A_D7

H8

DDR_A_D0

J3

DDR_A_D3

J7

DDR_A_D13

A3

DDR_A_D14

B8

DDR_A_D9

C3

DDR_A_D15

C7

DDR_A_D8

C2

DDR_A_D10

C8

DDR_A_D12

D3

DDR_A_D11

D7

B3 B9 D1 G7 J1 J9 L1 L9 R1 T9

A1 A9 C1 D9 F2 F8 G1 G9 J2 J8

B2 E1 E9 G8 K1 K9 M9 N1 T1

A2 A8 C9 D2 D8 E3 E8 F1 H1 H9

12

+1.2V

DDR_A_BG1_R DDR_A_BG1_R DDR_A_BG1_R

12

X76@

RD29 0_0402_5%

+1.2V

INTEL suggest 50ohm 1%

RD3

1 2

0_0402_5%

1

@

2

MEMRST#

CD5

0.1U_0201_10V6K

+DDR_VREF_CA

U3

M1

RD22

VREFCA

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC

T8

A13

L2

A14/WE

N2

BA0

N8

BA1

E2

DMU/DBIU

E7

DML/DBIL

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

L8

RAS

M8

CAS

A7

DQSU_c

B7

DQSU_t

F3

DQSL_c

G3

DQSL_t

P1

RESET

F9

ZQ

L3

ACT

M2

BG0

N9

TEN

P9

ALERT

T3

PAR

T7

NC

B1

VPP

R9

VPP

96-BALL

SDRAM DDR4

K4A8G165WB-BCPB_FBGA96

X76@

DDR_A_BG1[7]

DDR_A_MA0

12

DDR_A_MA1 DDR_A_MA2

CD2

DDR_A_MA3 DDR_A_MA4 DDR_A_MA5

0.047U_0402_25V7K

DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BA0[7,18,20] DDR_A_BA1[7,18,20]

DDR_A_CLK0[7,18] DDR_A_CLK#0[7,18] DDR_A_CKE0[7,18,20]

DDR_A_CS#0[7,18,20] DDR_A_CS#0[7,18,20]

12

X76@

RD35 0_0402_5%

DDR_A_BA0

+1.2V +1.2V

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CKE0

DDR_A_ODT0 DDR_A_CS#0 DDR_A_MA16 DDR_A_MA15

DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3

MEMRST# MEMRST#

1 2

240_0402_1%

M_A_ACT# DDR_A_BG0

DDR_A_ALERT# DDR_A_PARITY

+2.5V

+0.6VS

DDR_A_D25

G2

DQL0

DDR_A_D29

F7

DQL1

DDR_A_D27

H3

DQL2

DDR_A_D26

H7

DQL3

DDR_A_D24

H2

DQL4

DDR_A_D31

H8

DQL5

DDR_A_D28

J3

DQL6

DDR_A_D30

J7

DQL7

DDR_A_D16

A3

DQU0

DDR_A_D18

B8

DQU1

DDR_A_D17

C3

DQU2

DDR_A_D23

C7

DQU3

DDR_A_D20

C2

DQU4

DDR_A_D22

C8

DQU5

DDR_A_D21

D3

DQU6

DDR_A_D19

D7

DQU7

B3

VDD

B9

VDD

D1

VDD

G7

VDD

J1

VDD

J9

VDD

L1

VDD

L9

VDD

R1

VDD

T9

VDD

A1

VDDQ

A9

VDDQ

C1

VDDQ

D9

VDDQ

F2

VDDQ

F8

VDDQ

G1

VDDQ

G9

VDDQ

J2

VDDQ

J8

VDDQ

B2

VSS

E1

VSS

E9

VSS

G8

VSS

K1

VSS

K9

VSS

M9

VSS

N1

VSS

T1

VSS

A2

VSSQ

A8

VSSQ

C9

VSSQ

D2

VSSQ

D8

VSSQ

E3

VSSQ

E8

VSSQ

F1

VSSQ

H1

VSSQ

H9

VSSQ

0606 add

X76@

DDR_A_BG1 DDR_A_BG1_R

1 2

RD33

0_0402_5%

+1.2V

+DDR_VREF_CA

U4

M1

RD21

VREFCA

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC

T8

A13

L2

A14/WE

N2

BA0

N8

BA1

E2

DMU/DBIU

E7

DML/DBIL

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

L8

RAS

M8

CAS

A7

DQSU_c

B7

DQSU_t

F3

DQSL_c

G3

DQSL_t

P1

RESET

F9

ZQ

L3

ACT

M2

BG0

N9

TEN

P9

ALERT

T3

PAR

T7

NC

B1

VPP

R9

VPP

96-BALL

SDRAM DDR4

K4A8G165WB-BCPB_FBGA96

X76@

DDR_A_MA0

12

DDR_A_MA1 DDR_A_MA2

CD3

DDR_A_MA3 DDR_A_MA4 DDR_A_MA5

0.047U_0402_25V7K

DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

+2.5V

DDR_A_BG1_R [20]

DDR_A_BA0 DDR_A_BA1

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CKE0

DDR_A_ODT0 DDR_A_CS#0 DDR_A_MA16 DDR_A_MA15

DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5

1 2

240_0402_1%

M_A_ACT# DDR_A_BG0

DDR_A_ALERT# DDR_A_PARITY

DDR_A_BA0[7,18,20] DDR_A_BA1[7,18,20] DDR_A_BA0[7,18,20]

DDR_A_CLK0[7,18] DDR_A_CLK#0[7,18] DDR_A_CLK0[7,18] DDR_A_CKE0[7,18,20]

12

X76@

RD30

RD36

0_0402_5%

354/

!!

!

3

-!<

-!>

-!>

-!>

-!>>

-!>I

-!>

-!>E

-!>D

-!>1

3 3 3

:3

9. 9. 9. 9.

:3 :3 :3 :3

3

I>9. I>9. I>9. I>9.

G2

DQL0

F7

DQL1

H3

DQL2

H7

DQL3

H2

DQL4

H8

DQL5

J3

DQL6

J7

DQL7

A3

DQU0

B8

DQU1

C3

DQU2

C7

DQU3

C2

DQU4

C8

DQU5

D3

DQU6

D7

DQU7

B3

VDD

B9

VDD

D1

VDD

G7

VDD

J1

VDD

J9

VDD

L1

VDD

L9

VDD

R1

VDD

T9

VDD

A1

VDDQ

A9

VDDQ

C1

VDDQ

D9

VDDQ

F2

VDDQ

F8

VDDQ

G1

VDDQ

G9

VDDQ

J2

VDDQ

J8

VDDQ

B2

VSS

E1

VSS

E9

VSS

G8

VSS

K1

VSS

K9

VSS

M9

VSS

N1

VSS

T1

VSS

A2

VSSQ

A8

VSSQ

C9

VSSQ

D2

VSSQ

D8

VSSQ

E3

VSSQ

E8

VSSQ

F1

VSSQ

H1

VSSQ

H9

VSSQ

Data mapping

U2

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU4

DQU5

DQU6

DQU7

DDR_A_D40 DDR_A_D43 DDR_A_D44 DDR_A_D42 DDR_A_D41 DDR_A_D46 DDR_A_D45 DDR_A_D47

DDR_A_D37 DDR_A_D39 DDR_A_D32 DDR_A_D35 DDR_A_D34 DDR_A_D33 DDR_A_D36 DDR_A_D38

DQ

D3

D1

D2

D0

D7

D5

D6

D4

D10

D8

D11

D9

D14

D13

D15

D12

+DDR_VREF_CA

U5

M1

RD20

VREFCA

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC

T8

A13

L2

A14/WE

N2

BA0

N8

BA1

E2

DMU/DBIU

E7

DML/DBIL

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

L8

RAS

M8

CAS

A7

DQSU_c

B7

DQSU_t

F3

DQSL_c

G3

DQSL_t

P1

RESET

F9

ZQ

L3

ACT

M2

BG0

N9

TEN

P9

ALERT

T3

PAR

T7

NC

B1

VPP

R9

VPP

96-BALL

SDRAM DDR4

K4A8G165WB-BCPB_FBGA96

X76@

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU4

DQU5

DQU6

DQU7

DQ

D51

D49

D50

D48

D55

D53

D54

D52

D58

D56

D59

D57

D62

D61

D63

D60

DDR_A_MA0

12

DDR_A_MA1 DDR_A_MA2

CD4

DDR_A_MA3 DDR_A_MA4 DDR_A_MA5

0.047U_0402_25V7K

DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

+1.2V

12

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU4

DQU5

DQU6

DQU7

X76@

RD31 0_0402_5%

U3

DDR_A_CLK#0[7,18] DDR_A_CKE0[7,18,20]

12

X76@

RD37 0_0402_5%

DQ

D19

D17

D18

D16

D23

D21

D22

D20

D26

D24

D27

D25

D30

D29

D31

D28

DDR_A_BA1[7,18,20]

DDR_A_CS#0[7,18,20]

DDR_A_BA0 DDR_A_BA1

+1.2V

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CKE0

DDR_A_ODT0 DDR_A_CS#0 DDR_A_MA16 DDR_A_MA15

DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7

MEMRST#

1 2

M_A_ACT# DDR_A_BG0

+2.5V

U4 U5

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU4

DQU5

DQU6

DQU7

240_0402_1%

DDR_A_ALERT# DDR_A_PARITY

DQ

D35

D33

D34

D32

D39

D37

D38

D36

D42

D40

D43

D41

D46

D45

D47

D44

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

DDR_A_D56

G2

DDR_A_D58

F7

DDR_A_D57

H3

DDR_A_D59

H7

DDR_A_D61

H2

DDR_A_D62

H8

DDR_A_D60

J3

DDR_A_D63

J7

DDR_A_D52

A3

DDR_A_D55

B8

DDR_A_D53

C3

DDR_A_D54

C7

DDR_A_D49

C2

DDR_A_D50

C8

DDR_A_D48

D3

DDR_A_D51

D7

B3

VDD

B9

VDD

D1

VDD

G7

VDD

J1

VDD

J9

VDD

L1

VDD

L9

VDD

R1

VDD

T9

VDD

A1 A9 C1 D9 F2 F8 G1 G9 J2 J8

B2

VSS

E1

VSS

E9

VSS

G8

VSS

K1

VSS

K9

VSS

M9

VSS

N1

VSS

T1

VSS

A2 A8 C9 D2 D8 E3 E8 F1 H1 H9

+1.2V

DDR_A_BG1_R

X76@

RD32

0_0402_5%

12

X76@

RD38 0_0402_5%

+1.2V

RD4

1.8K_0402_1%

1 2

RD7

1.8K_0402_1%

1 2

+DDR_VREF_CA

3

RD5

2.7_0402_1%

A A

5

4

+0.6V_VREFCA[7]

CD6

0.022U_0402_16V7K

1

2

12

RD6

24.9_0402_1%

12

4*8'

LA-D301P

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/02/14 2015/02/14

2

Compal Secret Data

Deciphered Date

Title

DDR4 ON BOARD CHIPS

Size

Document Number Rev

Custom

Date: Sheet of

1

18 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

A

DDR_B_DQS#[0..7][7]

DDR_B_D[0..63][7]

DDR_B_DQS[0..7][7]

DDR_B_MA[0..16][7]

DDR_B_BA0[7]

DDR_B_BA1[7]

DDR_B_BG0[7] DDR_B_BG1[7]

DDR_B_CLK0[7]

1 1

Layout Note: Place near JDIMM1

+1.2V

2 2

+1.2V

DDR_B_CLK#0[7] DDR_B_CLK1[7]

DDR_B_CLK#1[7]

DDR_B_CKE0[7]

DDR_B_CKE1[7]

DDR_B_CS#0[7]

DDR_B_CS#1[7]

SOC_SMBDATA[8] SOC_SMBCLK[8]

DDR_B_ODT0[7] DDR_B_ODT1[7]

1U_0402_6.3V6K

1

CD8

CD9

2

4 as near side of the DIMM close to VDD pins

10U_0603_6.3V6M

CD18

CD17

1

2

DDR_B_BA0 DDR_B_BA1 DDR_B_BG0 DDR_B_BG1

DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1

DDR_B_CKE0 DDR_B_CKE1 DDR_B_CS#0 DDR_B_CS#1

SOC_SMBDATA SOC_SMBCLK

DDR_B_ODT0 DDR_B_ODT1

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

1U_0402_6.3V6K

1

CD10

2

10U_0603_6.3V6M

CD19

CD20

1

2

1

CD11

CD12

2

10U_0603_6.3V6M

CD23

CD22

CD21

1

2

1U_0402_6.3V6K

10U_0603_6.3V6M

1U_0402_6.3V6K

1

CD13

CD15

CD14

2

CD24

1

2

B

+1.2V

DDR_B_D14

DDR_B_D15

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D13

DDR_B_D12

DDR_B_D1

DDR_B_D5

DDR_B_D2

DDR_B_D3

DDR_B_D21

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D23

DDR_B_D22

DDR_B_D29

DDR_B_D25

DDR_B_D30

DDR_B_D26

@ 1 2 1 2

RD25 240_0402_1% RD24 240_0402_1%@

DDR_B_CKE0

DDR_B_BG1

DDR_B_BG0

DDR_B_MA12

DDR_B_MA9

DDR_B_MA8

DDR_B_MA6

DDR_B_MA3

DDR_B_MA1

DDR_B_CLK0

DDR_B_PARITY[7]

DDR_B_CLK#0

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143

C

JDIMM2 ME@

VSS1 DQ5 VSS3 DQ1 VSS5 DQS0_c DQS0_t VSS8 DQ7 VSS10 DQ3 VSS12 DQ13 VSS14 DQ9 VSS16 DM1_n/DBI_n VSS17 DQ15 VSS19 DQ10 VSS21 DQ21 VSS23 DQ17 VSS25 DQS2_c DQS2_t VSS28 DQ23 VSS30 DQ19 VSS32 DQ29 VSS34 DQ25 VSS36 DM3_n/DBI3_n VSS37 DQ30 VSS39 DQ26 VSS41 CB5/NC VSS43 CB1/NC VSS45 DQS8_c DQS8_t VSS48 CB2/NC VSS50 CB3/NC VSS52 CKE0 VDD1 BG1 BG0 VDD3 A12 A9 VDD5 A8 A6 VDD7 A3 A1 VDD9 CK0_t CK0_c VDD11 PARITY

DM0_n/DBI0_n

VSS11

VSS13

VSS15 DQS1_c DQS1_t

VSS18

VSS20

VSS22

VSS24

VSS26

DM2_n/DBI2_n

VSS27

VSS29

VSS31

VSS33

VSS35 DQS3_c DQS3_t

VSS38

VSS40

VSS42 CB4/NC

VSS44 CB0/NC

VSS46

DM8_n/DBI_n/NC

VSS47 CB6/NC

VSS49 CB7/NC

VSS51

RESET_n

ACT_n

ALERT_n

EVENT_n/NF

VDD10

CK1_t/NF

CK1_c/NF

VDD12

VSS2

DQ4

VSS4

DQ0

VSS6

VSS7

DQ6

VSS9

DQ2

DQ12

DQ8

DQ14

DQ11

DQ20

DQ16

DQ22

DQ18

DQ28

DQ24

DQ31

DQ27

CKE1 VDD2

VDD4

VDD6

VDD8

D

+1.2V

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120

A11

122

A7

124 126

A5

128

A4

130 132

A2

134 136 138 140 142 144

A0

DDR_B_D11

DDR_B_D10

DDR_B_D8

DDR_B_D9

DDR_B_D4

DDR_B_D0

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6

DDR_B_D7

DDR_B_D20

DDR_B_D19

DDR_B_D18

DDR_B_D28

DDR_B_D24

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D31

DDR_B_D27

DDR_B_CKE1

DDR_B_MA11 DDR_B_MA7

DDR_B_MA5 DDR_B_MA4

DDR_B_MA2

DDR_B_CLK1 DDR_B_CLK#1

DDR_B_MA0

DDR_DRAMRST#_R

M_B_ACT# [7]

DDR_B_ALERT# [7]

1

CD80

0.1U_0201_10V6K

@

2

+0.6V_B_VREFDQ[7]

Reverse Type

2-3A to 1 DIMMs/channel



CD7

0.022U_0402_16V7K

1

2

12

RD10

24.9_0402_1%

RD9 2_0402_1%

E

+1.2V

+DIMM_VREF_DQ

RD8 1K_0402_1%

1 2

12

RD11 1K_0402_1%

1 2

DDR_B_BA1

DDR_B_CS#0 DDR_B_MA14

DDR_B_ODT0 DDR_B_CS#1

DDR_B_ODT1

Place these caps on the VTT plane close to DIMM

+0.6VS

10U_0603_6.3V6M

CD29

10P_0402_25V8J

1

CD25

1U_0402_6.3V6K

2

3 3

4 4

2

10U_0603_6.3V6M

1

CD26

1U_0402_6.3V6K

+2.5V

CD28

CD27

1U_0402_6.3V6K

2

1

2

1

CD55

CD32

2

A

CD30

1

2

1U_0402_6.3V6K

1

CD81

@RF@

2

10P_0402_25V8J

1

CD82

@RF@

2

+3VS

1

2

CD54

2.2U_0402_6.3V6M

1

CD31

0.1U_0201_10V6K

2

close to DIMM

B

DDR_B_D37

DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D38

DDR_B_D34

DDR_B_D41

DDR_B_D40

DDR_B_D43

DDR_B_D42

DDR_B_D52

DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D55

DDR_B_D50

DDR_B_D61

DDR_B_D56

DDR_B_D59

DDR_B_D58

SOC_SMBCLK

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

DEREN_40-42272-26001RHF

JDIMM Connector PN SP070 01GK0 0

C0/CS2_n/NC

DM4_n/DBI4_n

DM6_n/DBI6_n

C

RAS_n/A16

CAS_n/A15

A10/AP

VDD14

VDD16

VDD18

VREFCA

VSS54

VSS56

VSS58

VSS59

VSS61

VSS63

VSS65

VSS67 DQS5_c DQS5_t

VSS70

VSS72

VSS74

VSS76

VSS78

VSS79

VSS81

VSS83

VSS85

VSS87 DQS7_c DQS7_t

VSS90

VSS92

VSS94

DQ36

DQ32

DQ39

DQ35

DQ45

DQ41

DQ47

DQ43

DQ53

DQ48

DQ54

DQ50

DQ60

DQ57

DQ63

DQ59

GND1 GND2

146 148 150

BA0

152 154 156 158

A13

160 162 164 166

SA2

168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254

SDA

256

SA0

258

VTT

260

SA1

261 262

DDR_B_MA10

DDR_B_BA0 DDR_B_MA16

DDR_B_MA15 DDR_B_MA13

DDR_B_D36

DDR_B_D32

DDR_B_D39

DDR_B_D35

DDR_B_D44

DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D47

DDR_B_D46

DDR_B_D53

DDR_B_D48

DDR_B_D54

DDR_B_D51

DDR_B_D60

DDR_B_D57

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D63

DDR_B_D62

SOC_SMBDATA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+DIMM_VREF_DQ

RD27

10K_0402_5%

RD26

0_0402_5%

@

Compal Secret Data

D

+3VS

1 2

12

Deciphered Date

+0.6VS+2.5V

2014/11/10 2016/11/10

DDR_DRAMRST#_R

RD15

1 2

0_0402_5%

0309 change 0ohm

Compal Electronics, Inc.

Title

Size

Date: Sheet of

DDR4_DIMM

Document Number Rev

Custom

LA-D562P

E

DDR_DRAMRST# [7,18]

19 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

DDR_A_MA[0..16][7,18]

D D

+1.2V

CD56

CD58

CD57

1U_0402_6.3V6K

1

2

CD60

CD59

1U_0402_6.3V6K

1

2

CD61

1U_0402_6.3V6K

1

2

3

10U_0603_6.3V6M

1

2

C C

+2.5V +0.6VS

CD64

1

2

10U_0603_6.3V6M

CD42

CD43

1

2

CD66

CD65

1U_0402_6.3V6K

1

2

2 as near each on board RAM device as possible

10U_0603_6.3V6M

CD44

1

2

CD67

1U_0402_6.3V6K

1

2

1

CD46

CD45

1

+

CD63 330U_D2_2V_Y

@

SGA00009S00

2

330U 2V H1.9 9mohm POLY

CD68

1

2

CD70

CD69

1U_0402_6.3V6K

1

2

4

CD36

CD62

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

CD35

CD34

CD33

CD37

1U_0402_6.3V6K

1

2

4 as near each on board RAM device as possible

CD71

1U_0402_6.3V6K

1

2

3

CD38

1U_0402_6.3V6K

CD40

CD39

1U_0402_6.3V6K

1

2

CD41

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

CD78

CD79

1U_0402_6.3V6K

1

2

CD76

CD77

1U_0402_6.3V6K

1

2

CD74

CD75

1U_0402_6.3V6K

1

2

CD72

CD73

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

2 as near each on board RAM device as possible

2

+0.6VS

RP1

DDR_A_MA1

1 8

DDR_A_MA5

2 7

DDR_A_MA7

3 6

DDR_A_MA9

4 5

36_0804_8P4R_5%

RP2

DDR_A_MA13

1 8

DDR_A_MA8

2 7

DDR_A_PARITY

DDR_A_PARITY[7,18]

DDR_A_CKE0[7,18]

DDR_A_ODT0[7,18]

M_A_ACT#[7,18]

DDR_A_BG1_R[18]

DDR_A_BG0[7,18]

DDR_A_BA1[7,18]

DDR_A_CS#0[7,18]

DDR_A_BA0[7,18]

DDR_A_MA11

DDR_A_CKE0 DDR_A_MA16 DDR_A_ODT0 M_A_ACT#

DDR_A_MA2

DDR_A_BG1_R

DDR_A_BG0 DDR_A_MA10 DDR_A_MA3 DDR_A_BA1

DDR_A_MA14 DDR_A_CS#0 DDR_A_MA15 DDR_A_MA12

DDR_A_MA4 DDR_A_BA0 DDR_A_MA0 DDR_A_MA6

3 6 4 5

36_0804_8P4R_5%

RP3

1 8 2 7 3 6 4 5

36_0804_8P4R_5%

1 2

RD28 36_0201_1%

1 2

RD34 36_0201_1%X76@

RP5

1 8 2 7 3 6 4 5

36_0804_8P4R_5%

RP6

1 8 2 7 3 6 4 5

36_0804_8P4R_5%

RP7

1 8 2 7 3 6 4 5

36_0804_8P4R_5%

1

10U_0603_6.3V6M

CD47

10U_0402_6.3V6M

CD48

10U_0402_6.3V6M

1

B B

A A

5

1

2

@

10U_0603_6.3V6M

CD49

1

2

@

CD51

CD50

1

2

4

10U_0603_6.3V6M

CD52

CD53

1

2

LA-D301P

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/02/14 2015/02/14

Compal Secret Data

2

Deciphered Date

Title

DDR4 ON BOARD CHIPS

Size

Document Number Rev

Custom

Date: Sheet of

1

20 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

1

2

3

4

5

A A

PCIE_CTX_C_GRX_P1[12] PCIE_CTX_C_GRX_N1[12]

PCIE_CTX_C_GRX_P2[12] PCIE_CTX_C_GRX_N2[12]

PCIE_CTX_C_GRX_P3[12] PCIE_CTX_C_GRX_N3[12]

PCIE_CTX_C_GRX_P4[12] PCIE_CTX_C_GRX_N4[12]

B B

C C

1 2

RV2 1K_0402_1%DIS@

CLK_PCIE_GPU CLK_PCIE_GPU#

PLT_RST_VGA#

CLK_PCIE_GPU[10]

+3VGS

5

PCIRST#[10,27,31 ,32,36,45]

DGPU_HOLD_RST#[11]

PCIRST#

DGPU_HOLD_RST#

MC74VHC1G08DFT2G_SC70-5

1

IN1

2

IN2

3

CLK_PCIE_GPU#[10]

UV3

DIS@

P

4

O

G

12

RV4 100K_0402_5%

DIS@

UV1A @

AF30

PCIE_RX0P

AE31

PCIE_RX0N

AE29

PCIE_RX1P

AD28

PCIE_RX1N

AD30

PCIE_RX2P

AC31

PCIE_RX2N

AC29

PCIE_RX3P

AB28

PCIE_RX3N

AB30

PCIE_RX4P

AA31

PCIE_RX4N

AA29

PCIE_RX5P

Y28

PCIE_RX5N

Y30

PCIE_RX6P

W31

PCIE_RX6N

W29

PCIE_RX7P

V28

PCIE_RX7N

V30

NC#V30

U31

NC#U31

U29

NC#U29

T28

NC#T28

T30

NC#T30

R31

NC#R31

R29

NC#R29

P28

NC#P28

P30

NC#P30

N31

NC#N31

N29

NC#N29

M28

NC#M28

M30

NC#M30

L31

NC#L31

L29

NC#L29

K30

NC#K30

CLOCK

AK30

PCIE_REFCLKP

AK32

PCIE_REFCLKN

N10

TEST_PG

AL27

PERSTB

2160856030-A0_FCBGA631

PCI EXPRESS INTERFACE

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

NC#W24 NC#W23

NC#V27

NC#U26

NC#U24 NC#U23

NC#T26 NC#T27

NC#T24 NC#T23

NC#P27 NC#P26

NC#P24 NC#P23

NC#M27 NC#N26

AH30 AG31

AG29 AF28

AF27 AF26

AD27 AD26

AC25 AB25

Y23 Y24

AB27 AB26

Y27 Y26

W24 W23

V27 U26

U24 U23

T26 T27

T24 T23

P27 P26

P24 P23

M27 N26

Y22

AA22

PCIE_CRX_C_GTX_P1 PCIE_CRX_C_GTX_N1

PCIE_CRX_C_GTX_P2 PCIE_CRX_C_GTX_N2

PCIE_CRX_C_GTX_P3 PCIE_CRX_C_GTX_N3

PCIE_CRX_C_GTX_P4 PCIE_CRX_C_GTX_N4

1 2

RV1 1.69K_0402_1%DIS@

1 2

RV3 1K_0402_1%DIS@

1 2

CV1 0.22U_0402_6.3V6KDIS@

1 2

CV3 0.22U_0402_6.3V6KDIS@

1 2

CV4 0.22U_0402_6.3V6KDIS@

1 2

CV2 0.22U_0402_6.3V6KDIS@

1 2

CV5 0.22U_0402_6.3V6KDIS@

1 2

CV6 0.22U_0402_6.3V6KDIS@

1 2

CV7 0.22U_0402_6.3V6KDIS@

1 2

CV8 0.22U_0402_6.3V6KDIS@

+PCIE_VGS

PCIE_CRX_GTX_P1 [12] PCIE_CRX_GTX_N1 [12]

PCIE_CRX_GTX_P2 [12] PCIE_CRX_GTX_N2 [12]

PCIE_CRX_GTX_P3 [12] PCIE_CRX_GTX_N3 [12]

PCIE_CRX_GTX_P4 [12] PCIE_CRX_GTX_N4 [12]

: 8 !)&&

UV1F

@

AB11

VARY_BL

AB12

DIGON

AL15 AK14

AH16 AJ15

AL17 AK16

AH18 AJ17

AL19 AK18

AH20 AJ19

AL21 AK20

AH22 AJ21

AL23 AK22

AK24 AJ23

TMDP

2160856030-A0_FCBGA631

TXCAP_DPA3P

TXCAM_DPA3N

TX0P_DPA2P TX0M_DPA2N

TX1P_DPA1P TX1M_DPA1N

TX2P_DPA0P TX2M_DPA0N

NC_TXOUT_L3P NC_TXOUT_L3N

TXCBP_DPB3P

TXCBM_DPB3N

TX3P_DPB2P TX3M_DPB2N

TX4P_DPB1P TX4M_DPB1N

TX5P_DPB0P TX5M_DPB0N

NC_TXOUT_U3P

NC_TXOUT_U3N

+VGA_CORE

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/12/05 2017/12/05

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

Size

Custom

Date: Sheet o f

Compal Electronics, Inc.

M30/M70_PCIE/DP

Document Number Re v

LA-E981P

5

21 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

1

2

3

4

5

WAKEB

1 2 1 2 1 2

PS_0

PS_1

PS_2

PS_3

VSSSENSE_VGA VCCSENSE_VGA

12

+3VGS

12

RV26 0_0402_5%DIS@ RV28 0_0402_5%DIS@ RV29 0_0402_5%DIS@

+VGA_CORE

-!(4J&4%

I.  K&

R_pd (ohm)R_pu (ohm)

NC

8.45k

4.53k

6.98k

4.53k

3.24k

3.4k

4.75k

!(4J&4%

Cap (nF) Bitd [5:4]

680nF

00

82nF

01

10nF 10

NC

11

RV14

16.2K_0402_1%

DIS@

RV20

4.7K_0402_5%

@

RV21

4.7K_0402_5%

DIS@

GPU_SVD GPU_SVT GPU_SVC

VSSSENSE_VGA [57] VCCSENSE_VGA [57]

Boot-VID Code

,

0 0 1 1

4.75k

2k

4.99k

5.62k

10k

NC

GPU_SVD [57] GPU_SVT [57] GPU_SVC [57]

,

,!

6,7

0 1 1.0 0 1 0.8

Bitd [3:1]

000

001

010

011

100

101

110

111

1.1

0.9

PS_0[3:1]=001

PS_0[5:4]=11

change to support gen3 11/24

PS_1[3:1]=001

PS_1[5:4]=11

PS_2[3:1]=000

PS_2[5:4]=11

PS_3[3:1]=000

PS_3[5:4]=11

UV1B

@

AF2

NC#AF2

AF4

+3VGS

12

DIS@

2

G

QV1A

L2N7002DW1T1G 2N SOT-363

@

GPIO19_CTF

12

RV15

10K_0402_5%

DIS@

1 2

@

JTAG_TDI_GPU JTAG_TMS_GPU JTAG_TCK JTAG_TRSTB

12

@

DIS@

12

RV72

10K_0402_5%

DIS@

6 1

TESTEN

JTAG_TDO_GPU

GPU_GPIO5#

A A

B B

SOC_SML1DATA[8,39,45,46]

SOC_SML1CLK[8,39,45,46]

+1.8VGS

RV13

10K_0402_5%

+3VGS

1 2

RV18 5.11K_0402_5%

1 2

DIS@

RV19 1K_0402_5%

+3VGS

1 8 2 7 3 6 4 5

RPV1 10K_8P4R_5%

@

RV25 10K_0402_5%

+3VGS

0608 change

S

D

3 4

47K_0402_5%

5

G

QV1B

DIS@

S

D

L2N7002DW1T1G 2N SOT-363

GPU_GPIO5# [64]

27MMHz CRYSTAL

RV30

DIS@

1M_0402_5%

XTALOUT XTALIN

YV1

SJ10000UI00

27MHZ_10PF_XRCGB27M000F2P18R0

1

C C

D D

0612 change

DIS@

CV13

12P_0402_50V8J

PCC_GPIO_6

0.1U_0402_10V7K

CV123

1

2

RV36 1K_0402_1%

2

@

1

DIS@

1 2

@

3

4

+3VGS

@

RV35 10K_0402_5%

1 2

GPU_VRHOT#

1

DIS@

CV14 12P_0402_50V8J

2

NC

2

Peak Current Control (Reversed)

DIS@

RV6

RV7 47K_0402_5%

GPU_PROHOT#[45]

1 2

RV23 0_0402_5%@

GPU_SVC

1 2

RV24 0_0402_5%@

M1-30/M1-70 colay level circuit M1-30 must implemented count

GPU_VRHOT# [57]

VGA_SMB_DA3

VGA_SMB_CK3

T70

T71

DV1

RB751V_SOD323

GPU_SVD_RGPU_SVD

GPU_SVC_R

+1.8VGS

1 2

BLM15BD121SN1D_0402

CV15 10U_0603_6.3V6M

CV16 1U_0402_6.3V4Z

CV17 0.1U_0201_10V6K

RV39 10K_0402_5%@

@

DIS@

GPUCLK_REQ#[10]

LV1

DIS@

1 2

FB_VDDCI

1

PLL_Analog_in

1

21

DIS@

12

Enable MLPS

+1.8VGS

RV10

4.7K_0402_5%

DIS@

1 2

+VGA_CORE

GPU_GPIO5#

GPU_SVD_R

GPIO19_CTF GPU_SVC_R

+VGA_CORE

T74

@

T75

1 2

RV31 10K_0402_5%

DIS@

1 2

RV32 10K_0402_5%

DIS@

>3

$      3 !

RV11

4.7K_0402_5%

DIS@

1 2

1

@

T56

@

T57

@

T58

@

T53

@

T59

@

T60

@

T61

@

T62

@

T63

@

T64

@

T65

@

T54

@

T55

@

T66

@

T67

@

T68

@

T69

@

T72

@

T73

VGA_SMB_DA3 VGA_SMB_CK3

PCC_GPIO_6

+VGA_CORE

JTAG_TRSTB JTAG_TDI_GPU JTAG_TCK JTAG_TMS_GPU JTAG_TDO_GPU TESTEN

PX_EN

XTALIN XTALOUT

GPIO28 +TSVDD

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

BP_0

BP_1

1 1

N9

DBG_DATA16

L9

DBG_DATA15

AE9

DBG_DATA14

Y11

DBG_DATA13

AE8

DBG_DATA12

AD9

DBG_DATA11

AC10

DBG_DATA10

AD7

DBG_DATA9

AC8

DBG_DATA8

AC7

DBG_DATA7

AB9

DBG_DATA6

AB8

DBG_DATA5

AB7

DBG_DATA4

AB4

DBG_DATA3

AB2

DBG_DATA2

Y8

DBG_DATA1

Y7

DBG_DATA0

W6

NC#W6

V6

NC#V6

AC6

NC#AC5

AC5

NC#AC6

AA5

NC#AA5

AA6

NC#AA6

U1

NC#U1

W1

NC#W1

U3

NC#U3

Y6

NC#Y6

AA1

NC#AA1

R1

SCL

R3

SDA

GENERAL PURPOSE I/O

U6

GPIO_0

U10

GPIO_1

T10

GPIO_2

U8

SMBDATA

U7

SMBCLK

T9

GPIO_5_AC_BATT

T8

GPIO_6

T7

GPIO_7_BLON

P10

GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N6

GPIO_11

N5

GPIO_12

N3

GPIO_13

Y9

GPIO_14_HPD2

N1

GPIO_15_PWRCNTL_0

M4

GPIO_16

R6

GPIO_17_THERMAL_INT

W10

GPIO_18

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNTL_1

P7

GPIO_21

N8

GPIO_22_ROMCSB

AK10

GPIO_29

AM10

GPIO_30

N7

CLKREQB

L6

JTAG_TRSTB

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS

K4

JTAG_TDO

K7

TESTEN

AF24

NC#AF24

AB13

GENERICA

W8

GENERICB

W9

GENERICC

W7

GENERICD

AD10

GENERICE

AJ9

NC#AJ9

AL9

NC#AL9

AC14

HPD1

AB16

PX_EN

AC16

DBG_VREFG

AM28

XTALIN

AK28

XTALOUT

AC22

XO_IN

AB22

XO_IN2

SEYMOUR/FutureASIC

T4

DPLUS

T2

DMINUS

R5

GPIO28_FDO

AD17

TSVDD

AC17

TSVSS

2160856030-A0_FCBGA631

DVO

I2C

PLL/CLOCK

THERMAL

NC#AF4

NC#AG3 NC#AG5

DPA

NC#AH3 NC#AH1

NC#AK3 NC#AK1

NC#AK5 NC#AM3

NC#AK6 NC#AM5

DPB

NC#AJ7 NC#AH6

NC#AK8 NC#AL7

DPC

NC#AA3

AVSSN#AK26

AVSSN#AJ25

AVSSN#AG25

DAC1

VDD1DI

FutureASIC/SEYMOUR/PARK

RSVD#AK12 RSVD#AL11 RSVD#AJ11

GENLK_CLK

GENLK_VSYNC

SWAPLOCKA SWAPLOCKB

DDC/AUX

DDC1CLK

DDC1DATA

DDC2CLK

DDC2DATA

NC#AD20 NC#AC20

NC#AE16 NC#AD16

DDCVGACLK

DDCVGADATA

NC#V4

NC#U5

NC#W3

NC#V2

NC#Y4

NC#W5

NC#Y2

NC#J8

HSYNC VSYNC

AVSSQ

VSS1DI

CEC_1

AUX1P AUX1N

AUX2P AUX2N

RSET

AVDD

PS_0

PS_1

PS_2

PS_3

TS_A

AG3 AG5

AH3 AH1

AK3 AK1

AK5 AM3

AK6 AM5

AJ7 AH6

AK8 AL7

V4 U5

W3 V2

Y4 W5

PLL_Analog_out

AA3 Y2

J8

AM26

R

AK26

AL25

G

AJ25

AH24

B

AG25

AH26 AJ27

AD22

AG24 AE22

AE23 AD23

AM12

AK12 AL11 AJ11

AL13 AJ13

AG13 AH12

AC19

AD19

AE17

AE20

AE19

AE6 AE5

AD2 AD4

AC11 AC13

AD13 AD11

AD20 AC20

AE16 AD16

AC1 AC3

PS_0

PS_1

PS_2

CV11

PS_3

+1.8VGS

CV9

CV10

@

CV12

GPU_SVD GPU_SVC

@

0.68U_0402_10V

@

0.68U_0402_10V

1

2

0.082U_0402_16V

@

0.68U_0402_10V

RV33

10K_0402_5%

DIS@

RV37

10K_0402_5%

@

+1.8VGS

1

2

+1.8VGS

1

2

+1.8VGS

1

2

12

RV5

8.45K_0402_1%

DIS@

12

RV8 2K_0402_1%

DIS@

12

DIS@

RV9

8.45K_0402_1%

12

DIS@

RV12 2K_0402_1%

12

@

RV16

8.45K_0402_1%

12

RV17

4.75K_0402_1%

DIS@

12

X76@

RV22

8.45K_0402_1%

12

X76@

RV27

4.75K_0402_1%

SD034475180

1 2

RV34 10K_0402_5%

@

RV38 10K_0402_5%

DIS@

Strap Name :

PS_0[1] ROM_CONFIG[0]

PS_0[2] ROM_CONFIG[1]

PS_0[3] ROM_CONFIG[2]

PS_0[4] N/A

PS_0[5] AUD_PORT_CONN_PINSTRAP[0]

Strap Name :

PS_1[1] STRAP_BIF_GEN3_EN_A

PS_1[2] TRAP_BIF_CLK_PM_EN

PS_1[3] N/A

PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING

PS_1[5] STRAP_TX_DEEMPH_EN

Strap Name :

PS_2[1] N/A

PS_2[2] N/A

PS_2[3] STRAP_BIOS_ROM_EN

PS_2[4] STRAP_BIF_VGA_DIS

PS_2[5] N/A

Strap Name :

PS_3[1] BOARD_CONFIG[0] (Memory ID)

PS_3[2] BOARD_CONFIG[1] (Memory ID)

PS_3[3] BOARD_CONFIG[2] (Memory ID)

PS_3[4] AUD_PORT_CONN_PINSTRAP[1]

PS_3[5] AUD_PORT_CONN_PINSTRAP[2]

VRAM Type

Need reference X76 Schemat i c

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/12/05 2017/12/05

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

M30/M70_MSIC

Size

Document Number Rev

Custom

LA-E981P

Date: Sheet of

5

22 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

4

3

2

1

+1.8VALW TO +1.8VGS +1.0VALW TO +PCIE_VGS

Load switch

UV1E

@

D D

+1.8VALW

1U_0402_6.3V6K

CV18

1

@

2

DIS@

RV40

47.5K_0402_1%

C C

DGPU_PWR_EN_RDGPU_PWR_EN

12

0.1U_0201_10V K X5R

CV23

+5VALW

1

+1.0VALW

DIS@

2

1U_0402_6.3V6K

CV28

1

@

2

UV10 DIS@

1

VOUT1

VIN1

2

VOUT1

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

VOUT2

7

VIN2

VOUT2

EM5209VF_DFN14_3X2

CT1

GND

CT2

GPAD

14 13

12

11

10

9

+PCIE_VGS_LS

8

15

+1.8VGS_LS

@

R_short

RV41 0_0603_5%

1 2

CV222200P_0402_50V7K

1 2

CV242200P_0402_50V7K

DIS@

RV42 0_0603_5%

R_short

DIS@

+PCIE_VGS

1 2

+1.8VGS

DIS@

CV21

0.1U_0201_10V7K

1 2

DIS@

CV25

0.1U_0201_10V7K

12

+1.8VGS

+PCIE_VGS

+DP_VDD R

1

CV2010U_0603_6.3V6M

CV191U_0402_6.3V4Z

@

2

+DP_VDD C

13

1

CV271U_0402_6.3V4Z

CV2610U_0603_6.3V6M

@

2

: 8 !)&&

UV1G

@

AG15

DP_VDDR#AG15

AG16

DP_VDDR#AG16

AF16

DP_VDDR#AF16

AG17

DP_VDDR#AG17

AG18

DP_VDDR#AG18

AG19

DP_VDDR#AG19

AF14

DP_VDDR#AF14

AG20

DP_VDDC#AG20

AG21

DP_VDDC#AG21

AF22

DP_VDDC#AF22

AG22

DP_VDDC#AG22

AD14

DP_VDDC#AD14

AG14

DP_VSSR

AH14

DP_VSSR

AM14

DP_VSSR

AM16

DP_VSSR

AM18

DP_VSSR

AF23

DP_VSSR

AG23

DP_VSSR

AM20

DP_VSSR

AM22

DP_VSSR

AM24

DP_VSSR

AF19

DP_VSSR

AF20

DP_VSSR

AE14

DP_VSSR

AF17

DPAB_CALR

2160856030-A0_FCBGA631

DP POWER

NC/DP POWER

NC#AE11 NC#AF11 NC#AE13 NC#AF13

NC#AG8

NC#AG10

NC#AF6 NC#AF7 NC#AF8 NC#AF9

NC#AE1 NC#AE3 NC#AG1 NC#AG6 NC#AH5

NC#AF10

NC#AG9

NC#AH8 NC#AM6 NC#AM8

NC#AG7

NC#AG11

NC#AE10

AE11 AF11 AE13 AF13 AG8 AG10

AF6 AF7 AF8 AF9

AE1 AE3 AG1 AG6 AH5 AF10 AG9 AH8 AM6 AM8 AG7 AG11

AE10

+3VALW to +3VGS

+3VGS+3VALW

B B

ME2301DC-G_SOT23-3

+5VALW

DGPU_PWR_EN#

RV44

DIS@

20K_0402_5%

DGPU_PWR_EN[11,45,57,58]

A A

DIS@

L2N7002WT1G 1N SC-70-3

13

D

2

G

QV4

S

DIS@

QV2

SB000013I00

DIS@

1 2

RV45 10K_0402_5%

S

G

2

3VGS_EN#

1

2

D

13

DIS@

CV31

0.1U_0201_10V7K

4.7U_0603_6.3V6K

DGPU_PWR_EN#[44]

1U_0402_6.3V6K

CV29

1

DIS@

@

2

12

CV30

@

RV43 680_0603_5%

QV3

@

13

D

L2N7002WT1G 1N SC-70-3

2

G

S

DGPU_PWR_EN#

DIS@

L2N7002WT1G 1N SC-70-3

+VGA_CORE

2

G

QV5

RV46 470_0603_5%

DIS@

1 2

13

D

S

+1.8VGS

RV47 470_0603_5%

@

1 2

61

D

S

QV6A L2N7002DW1T1G 2N SOT-363

1

2

AA27

GND

AB24

GND

AB32

GND

AC24

GND

AC26

GND

AC27

GND

AD25

GND

AD32

GND

AE27

GND

AF32

GND

AG27

GND

AH32

GND

K28

GND

K32

GND

L27

GND

M32

GND

N25

GND

N27

GND

P25

GND

P32

GND

R27

GND

T25

GND

T32

GND

U25

GND

U27

GND

V32

GND

W25

GND

W26

GND

W27

GND

Y25

GND

Y32

GND

M6

GND

N13

GND

N16

GND

N18

GND

AA11

N21

P6

P9 R12 R15 R17 R20 T13 T16 T18 T21

T6 U15 U17 U20

U9 V13 V16 V18 Y10 Y15 Y17 Y20 R11 T11

M12

N11 V11

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

2160856030-A0_FCBGA631

GND

VSS_MECH VSS_MECH VSS_MECH

+PCIE_VGS

RV48 470_0603_5%

@

1 2

34

DGPU_PWR_EN# DGPU_PWR_EN#

2

G

@

D

5

G

S

QV6B

@

L2N7002DW1T1G 2N SOT-363

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

A3 A30 AA13 AA16 AB10 AB15 AB6 AC9 AD6 AD8 AE7 AG12 AH10 AH28 B10 B12 B14 B16 B18 B20 B22 B24 B26 B6 B8 C1 C32 E28 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F6 F8 G10 G27 G31 G8 H14 H17 H2 H20 H6 J27 J31 K11 K2 K22 K6

A32 AM1 AM32

T216TP@ T217TP@ T218TP@

Title

<Title>

Size

Document Number Re v

Document Number Re v LA-E981P 0.1

Custom

LA-E981P 0.1

Custom

LA-E981P 0.1

Custom

Date: Sheet o f

5

4

3

2

Date: Sheet o f

1

23 66Thursday, June 15, 2017

Vinaﬁx.com

5

4

3

2

1

D D

F,839*-/

,!!

VDDC and VDDCI TDC 28A

,!!'

F'/9,8

'/9,!!

5' 9,!!

449,!!

FC>,9/98 M

C C

,!!-

3

FC1,8

'/9,!!

449,!!

449,!!

,!!9

F!9,!!-

F!9,!!

B B

F>,8

,!!->

&

I > 

 > >

& &

3



C13

3

C& C&

&



> 

&

3

<3

D3

 

>3

6L7

I3

6L7 6L7 6L7

&

 > 

3

&

 

6L7 6L7

&

D 

 

 

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



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C&

C&

C&

DIS@

1

CV5510U_0603_6.3V6M

DIS@

2

+VGA_CORE

+1.8VGS

1

CV451U_0402_6.3V4Z

DIS@

2

CV561U_0402_6.3V4Z

DIS@

1

CV460.1U_0201_10V6K

CV470.01U_0402_16V7K

DIS@

2

+PCIE_VGS

1

DIS@

2

1

CV571U_0402_6.3V4Z

CV581U_0402_6.3V4Z

CV591U_0402_6.3V4Z

DIS@

2

1

CV621U_0402_6.3V4Z

CV611U_0402_6.3V4Z

CV601U_0402_6.3V4Z

DIS@

2

UV1D

+1.35VS_VRAM

1

CV480.1U_0201_10V6K

DIS@

2

DIS@

CV330.1U_0201_10V6K

DIS@

2

1

CV490.1U_0201_10V6K

DIS@

2

CV500.1U_0201_10V6K

1

DIS@

2

DIS@

1

CV402.2U_0402_6.3V6M

CV3910U_0603_6.3V6M

DIS@

2

1

CV6310U_0603_6.3V6M

DIS@

2

1

CV3810U_0603_6.3V6M

CV3210U_0603_6.3V6M

DIS@

2

+1.8VGS

LV2

1 2

BLM15BD121SN1D_0402



CV412.2U_0402_6.3V6M

CV641U_0402_6.3V4Z

1

DIS@

2

1

2

DIS@

1

CV422.2U_0402_6.3V6M

DIS@

2

1

CV650.1U_0201_10V6K

2

CV432.2U_0402_6.3V6M

1

DIS@

2

CV442.2U_0402_6.3V6M

+3VGS

1

DIS@

2

LV3

1 2

BLM15BD121SN1D_0402



1

CV510.1U_0201_10V6K

DIS@

2

1

CV6610U_0603_6.3V6M

CV671U_0402_6.3V4Z

DIS@

2

CV520.01U_0402_16V7K

DIS@

2

1

CV681U_0402_6.3V4Z

2

DIS@

CV340.01U_0402_16V7K

DIS@

CV691U_0402_6.3V4Z

1

CV350.01U_0402_16V7K

DIS@

2

1

2

1

CV360.01U_0402_16V7K

DIS@

2

3

1

CV530.01U_0402_16V7K

2

H13 H16 H19 J10 J23 J24

J9 K10 K23 K24

K9 L11 L12 L13 L20 L21 L22

>3

+VDD_CT

AA20 AA21 AB20 AB21

3

AA17

+VDDR3

AA18 AB17 AB18

V12 Y12 U12



CIS SYMBOL

+1.8VGS

LV4

1 2

BLM15BD221SN1D_2P

DIS@

<3

1

CV7610U_0603_6.3V6M

DIS@

2

+MPLL_PVDD

1

CV771U_0402_6.3V4Z

DIS@

2

D3

+SPLL_PVDD

3

+SPLL_VDDC

1

CV780.1U_0201_10V6K

2

L8

H7

H8

J7

1

CV7010U_0603_6.3V6M

CV720.1U_0201_10V6K

CV711U_0402_6.3V4Z

DIS@

2

+1.8VGS

LV5

DIS@

1 2

BLM15BD121SN1D_0402

DIS@

CV7310U_0603_6.3V6M

1

DIS@

2

1

CV741U_0402_6.3V4Z

CV750.1U_0201_10V6K

DIS@

+PCIE_VGS

2

LV6

DIS@

1 2

BLM15BD121SN1D_0402

DIS@

@

MEM I/O

VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1

LEVEL TRANSLATION

VDD_CT VDD_CT VDD_CT VDD_CT

I/O

VDDR3 VDDR3 VDDR3 VDDR3

VDDR4 VDDR4 VDDR4

PLL

MPLL_PVDD

SPLL_PVDD

SPLL_VDDC

SPLL_PVSS

2160856030-A0_FCBGA631

PCIE

CORE

ISOLATED

CORE I/O

PCIE_PVDD

NC#AB23 NC#AC23 NC#AD24 NC#AE24 NC#AE25 NC#AE26 NC#AF25

NC#AG26

PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC

POWER

BIF_VDDC BIF_VDDC

VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC

VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI

3

AM30

+PCI E_PV DD

AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26

L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22

AA15 N15 N17 R13 R16 R18 Y21 T12 T15 T17 T20 U13 U16 U18 V21 V15 V17 V20 Y13 Y16 Y18 AA12 M11 N12 U11

R21 U21

M13 M15 M16 M17 M18 M20 M21 N20

1

CV3710U_0603_6.3V6M

2

3

1

CV5410U_0603_6.3V6M

DIS@

2

VGA_CORE Caps in power side sheet

C13

+BIF_VDDC

+VGA_CORE

VGA_CORE Caps in power side sheet

+PCIE_VGS

+BIF_VDDC

1

CV7910U_0603_6.3V6M

DIS@

2

A A

5

4

3

RV49

12

0_0805_5%

DIS@

2

CV811U_0402_6.3V4Z

CV801U_0402_6.3V4Z

DIS@

1

Title

<Title>

Size

Document Number Re v

Document Number Re v LA-E981P 0.1

Custom

LA-E981P 0.1

Custom

LA-E981P 0.1

Custom

Date: Sheet o f

2

Date: Sheet o f

1

24 66Thursday, June 15, 2017

Vinaﬁx.com

1

A A

2

3

4

5

DRAM_RST_G

1

@

CV85 68P_0402_50V8J

2

M_DA[63..0]

M0_MA[8..0]

M1_MA[8..0]

RV58 51.1_0402_1%@ RV59 51.1_0402_1%@

1 2 1 2

1 2

RV57 120_0402_1%DIS@

1 2

CV86 0.1U_0402_16V4Z@

1 2

CV87

@

M_DA0 M_DA1 M_DA2 M_DA3 M_DA4 M_DA5 M_DA6 M_DA7 M_DA8 M_DA9 M_DA10 M_DA11 M_DA12 M_DA13 M_DA14 M_DA15 M_DA16 M_DA17 M_DA18 M_DA19 M_DA20 M_DA21 M_DA22 M_DA23 M_DA24 M_DA25 M_DA26 M_DA27 M_DA28 M_DA29 M_DA30 M_DA31 M_DA32 M_DA33 M_DA34 M_DA35 M_DA36 M_DA37 M_DA38 M_DA39 M_DA40 M_DA41 M_DA42 M_DA43 M_DA44 M_DA45 M_DA46 M_DA47 M_DA48 M_DA49 M_DA50 M_DA51 M_DA52 M_DA53 M_DA54 M_DA55 M_DA56 M_DA57 M_DA58 M_DA59 M_DA60 M_DA61 M_DA62 M_DA63

+MVREFDA +MVREFSA

DRAM_RST_G

0.1U_0402_16V4Z

M_DA[63..0][26]

M0_MA[8..0][26]

M1_MA[8..0][26]

+1.35VS_VRAM+1.35VS_VRAM

12

B B

C C

40.2_0402_1%

100_0402_1%

DRAM_RST[26]

RV50

DIS@

+MVREFDA

12

1

CV82

RV52

1U_0402_6.3V4Z

2

DIS@

RV54

DIS@

49.9_0402_1%

1 2

1

CV84

120P_0402_50V8J

Place close to GPU (within 25mm) and place componment within (5mm) close to each other

DIS@

2

RV51

40.2_0402_1%

DIS@

RV53

100_0402_1%

DIS@

RV55

DIS@

10_0402_1%

5.1K_0402_1%

12

+MVREFSA

12

1

CV83 1U_0402_6.3V4Z

2

DIS@

12

RV56

DIS@

UV1C

K27

DQA0_0

J29

DQA0_1

H30

DQA0_2

H32

DQA0_3

G29

DQA0_4

F28

DQA0_5

F32

DQA0_6

F30

DQA0_7

C30

DQA0_8

F27

DQA0_9

A28

DQA0_10

C28

DQA0_11

E27

DQA0_12

G26

DQA0_13

D26

DQA0_14

F25

DQA0_15

A25

DQA0_16

C25

DQA0_17

E25

DQA0_18

D24

DQA0_19

E23

DQA0_20

F23

DQA0_21

D22

DQA0_22

F21

DQA0_23

E21

DQA0_24

D20

DQA0_25

F19

DQA0_26

A19

DQA0_27

D18

DQA0_28

F17

DQA0_29

A17

DQA0_30

C17

DQA0_31

E17

DQA1_0

D16

DQA1_1

F15

DQA1_2

A15

DQA1_3

D14

DQA1_4

F13

DQA1_5

A13

DQA1_6

C13

DQA1_7

E11

DQA1_8

A11

DQA1_9

C11

DQA1_10

F11

DQA1_11

A9

DQA1_12

C9

DQA1_13

F9

DQA1_14

D8

DQA1_15

E7

DQA1_16

A7

DQA1_17

C7

DQA1_18

F7

DQA1_19

A5

DQA1_20

E5

DQA1_21

C3

DQA1_22

E1

DQA1_23

G7

DQA1_24

G6

DQA1_25

G1

DQA1_26

G3

DQA1_27

J6

DQA1_28

J1

DQA1_29

J3

DQA1_30

J5

DQA1_31

K26

MVREFDA

J26

MVREFSA

J25

NC#J25

K25

MEM_CALRP0

L10

DRAM_RST

K8

CLKTESTA

L7

CLKTESTB

2160856030-A0_FCBGA631

@

MEMORY INTERFACE

GDDR5/DDR3GDDR5/DD R3

MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6

MAA0_7/MAA_7 MAA0_8/MAA_13 MAA0_9/MAA_15

MAA1_0/MAA_8

MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12

MAA1_5/MAA_BA2 MAA1_6/MAA_BA0 MAA1_7/MAA_BA1

MAA1_8/MAA_14

MAA1_9/RSVD

WCKA0_0/DQMA0_0

WCKA0B_0/DQMA0_1

WCKA0_1/DQMA0_2

WCKA0B_1/DQMA0_3

WCKA1_0/DQMA1_0

WCKA1B_0/DQMA1_1

WCKA1_1/DQMA1_2

WCKA1B_1/DQMA1_3

EDCA0_0/QSA0_0 EDCA0_1/QSA0_1 EDCA0_2/QSA0_2 EDCA0_3/QSA0_3 EDCA1_0/QSA1_0 EDCA1_1/QSA1_1 EDCA1_2/QSA1_2 EDCA1_3/QSA1_3

DDBIA0_0/QSA0_0B DDBIA0_1/QSA0_1B DDBIA0_2/QSA0_2B DDBIA0_3/QSA0_3B DDBIA1_0/QSA1_0B DDBIA1_1/QSA1_1B DDBIA1_2/QSA1_2B DDBIA1_3/QSA1_3B

ADBIA0/ODTA0 ADBIA1/ODTA1

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B RASA1B

CASA0B CASA1B

CSA0B_0 CSA0B_1

CSA1B_0 CSA1B_1

CKEA0 CKEA1

WEA0B WEA1B

M0_MA0

K17

M0_MA1

J20

M0_MA2

H23

M0_MA3

G23

M0_MA4

G24

M0_MA5

H24

M0_MA6

J19

M0_MA7

K19

M0_MA8

G20 L17

M1_MA0

J14

M1_MA1

K14

M1_MA2

J11

M1_MA3

J13

M1_MA4

H11

M1_MA5

G11

M1_MA6

J16

M1_MA7

L15

M1_MA8

G14 L16

M_WCKA0_0

E32

M_WCKA0_0#

E30

M_WCKA0_1

A21

M_WCKA0_1#

C21

M_WCKA1_0

E13

M_WCKA1_0#

D12

M_WCKA1_1

E3

M_WCKA1_1#

F4

M_EDC_0

H28

M_EDC_1

C27

M_EDC_2

A23

M_EDC_3

E19

M_EDC_4

E15

M_EDC_5

D10

M_EDC_6

D6

M_EDC_7

G5

M_DBI0#

H27

M_DBI1#

A27

M_DBI2#

C23

M_DBI3#

C19

M_DBI4#

C15

M_DBI5#

E9

M_DBI6#

C5

M_DBI7#

H4

M_ADBI0

L18

M_ADBI1

K16

M_CLK0

H26

M_CLK#0

H25

M_CLK1

G9

M_CLK#1

H9

M_RAS#0

G22

M_RAS#1

G17

M_CAS#0

G19

M_CAS#1

G16

M_CS0B#0

H22 J22

M_CS1B#0

G13 K13

M_CKE0

K20

M_CKE1

J17

M_WE#0

G25

M_WE#1

H10

M_WCKA0_0 [26] M_WCKA0_0# [26] M_WCKA0_1 [26] M_WCKA0_1# [26] M_WCKA1_0 [26] M_WCKA1_0# [26] M_WCKA1_1 [26] M_WCKA1_1# [26]

M_EDC_0 [26] M_EDC_1 [26] M_EDC_2 [26] M_EDC_3 [26] M_EDC_4 [26] M_EDC_5 [26] M_EDC_6 [26] M_EDC_7 [26]

M_DBI0# [26] M_DBI1# [26] M_DBI2# [26] M_DBI3# [26] M_DBI4# [26] M_DBI5# [26] M_DBI6# [26] M_DBI7# [26]

M_ADBI0 [26] M_ADBI1 [26]

M_CLK0 [26] M_CLK#0 [26]

M_CLK1 [26] M_CLK#1 [26]

M_RAS#0 [26] M_RAS#1 [26]

M_CAS#0 [26] M_CAS#1 [26]

M_CS0B#0 [26]

M_CS1B#0 [26]

M_CKE0 [26] M_CKE1 [26]

M_WE#0 [26] M_WE#1 [26]

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/12/05 2017/12/05

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

Size

Custom

Date: Sheet o f

Compal Electronics, Inc.

M30/M70_MEM

Document Number Re v

LA-E981P

5

25 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

4

3

2

1

Memory Partition A

MF=0 MF=0

UV7

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

K4G80325FB-HC03_FBGA170~D

+1.35VS_VRAM

1 2

RV60 60.4_0402_1%

1 2

RV61 60.4_0402_1%

+1.35VS_VRAM

1 2

RV62 60.4_0402_1%

1 2

RV69 60.4_0402_1%

+1.35VS_VRAM

2.37K_0402_1%

12

RV70

DIS@

5.49K_0402_1%

12

RV71

DIS@

M_DA[0..63]

M_CLK0

DIS@

M_CLK#0

DIS@

M_CLK1

DIS@

M_CLK#1

DIS@

+FBA_VREFC0

1U_0402_6.3V6K

W=16mils

CV89

1

DIS@

2

D D

C C

M_DA[0..63][25]

M_EDC_0

M_EDC_0[25] M_EDC_4[25]

M_EDC_1

M_EDC_1[25]

M_EDC_3

M_EDC_3[25]

M_EDC_2

M_EDC_2[25]

M_DBI0#

M_DBI0#[25]

M_DBI1#

M_DBI1#[25]

M_DBI3#

M_DBI3#[25]

M_DBI2#

M_DBI2#[25]

M_CLK0

M_CLK0[25]

M_CLK#0

M_CLK#0[25]

M_CKE0

M_CKE0[25] M_CKE1[2 5]

M0_MA2

M0_MA2[25]

M0_MA5

M0_MA5[25]

M0_MA4

M0_MA4[25]

M0_MA3

M0_MA3[25]

M0_MA7

M0_MA7[25]

M0_MA1

M0_MA1[25]

M0_MA0

M0_MA0[25]

M0_MA6

M0_MA6[25]

M0_MA8

M0_MA8[25]

RV63 1K_0402_1%DIS@ RV65 1K_0402_1%DIS@ RV67 121_0402_1%DIS@

M_ADBI0[25] M_RAS#0[25] M_CS0B#0[25] M_CAS#0[25] M_WE#0[25]

M_WCKA0_0#[25] M_WCKA0_0[25]

M_WCKA0_1#[25] M_WCKA0_1[25]

DRAM_RST[25]

+1.35VS_VRAM +1.35VS_VRAM

12 12 12

M_ADBI0 M_RAS#0 M_CS0B#0 M_CAS#0 M_WE#0

M_WCKA0_0# M_WCKA0_0

M_WCKA0_1# M_WCKA0_1

+FBA_VREFC0

DRAM_RST

Place near pin J14 of each vram

B B

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

X76@

M_DA2

A4

M_DA0

A2

M_DA3

B4

M_DA1

B2

M_DA6

E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1

VDDQ

D1

VDDQ

F1

VDDQ

M1

VDDQ

P1

VDDQ

T1

VDDQ

G2

VDDQ

L2

VDDQ

B3

VDDQ

D3

VDDQ

F3

VDDQ

H3

VDDQ

K3

VDDQ

M3

VDDQ

P3

VDDQ

T3

VDDQ

E5

VDDQ

N5

VDDQ

E10

VDDQ

N10

VDDQ

B12

VDDQ

D12

VDDQ

F12

VDDQ

H12

VDDQ

K12

VDDQ

M12

VDDQ

P12

VDDQ

T12

VDDQ

G13

VDDQ

L13

VDDQ

B14

VDDQ

D14

VDDQ

F14

VDDQ

M14

VDDQ

P14

VDDQ

T14

VDDQ

A1

VSSQ

C1

VSSQ

E1

VSSQ

N1

VSSQ

R1

VSSQ

U1

VSSQ

H2

VSSQ

K2

VSSQ

A3

VSSQ

C3

VSSQ

E3

VSSQ

N3

VSSQ

R3

VSSQ

U3

VSSQ

C4

VSSQ

R4

VSSQ

F5

VSSQ

M5

VSSQ

F10

VSSQ

M10

VSSQ

C11

VSSQ

R11

VSSQ

A12

VSSQ

C12

VSSQ

E12

VSSQ

N12

VSSQ

R12

VSSQ

U12

VSSQ

H13

VSSQ

K13

VSSQ

A14

VSSQ

C14

VSSQ

E14

VSSQ

N14

VSSQ

R14

VSSQ

U14

VSSQ

M_DA7 M_DA5 M_DA4 M_DA15 M_DA13 M_DA11 M_DA9 M_DA10 M_DA12 M_DA8 M_DA14 M_DA30 M_DA28 M_DA31 M_DA29 M_DA27 M_DA26 M_DA24 M_DA25 M_DA19 M_DA22 M_DA17 M_DA20 M_DA18 M_DA21 M_DA16 M_DA23

BYTE0

BYTE1

BYTE3

BYTE2

M_EDC_5[25] M_EDC_7[25] M_EDC_6[25]

M_DBI4#[25] M_DBI5#[25] M_DBI7#[25] M_DBI6#[25]

M_CLK1[25] M_CLK#1[25]

M1_MA2[2 5] M1_MA5[2 5] M1_MA4[2 5] M1_MA3[2 5]

M1_MA7[2 5] M1_MA1[2 5] M1_MA0[2 5] M1_MA6[2 5] M1_MA8[2 5]

RV64 1K_0402_1%DIS@ RV66 1K_0402_1%DIS@ RV68 121_0402_1%DIS@

M_ADBI1[25] M_RAS#1[25] M_CS1B#0[25] M_CAS#1[25] M_WE#1[25]

M_WCKA1_0#[25] M_WCKA1_0[25]

M_WCKA1_1#[25] M_WCKA1_1[25]

+FBA_VREFC0

1U_0402_6.3V6K

CV88

1

DIS@

2

M_EDC_4 M_EDC_5 M_EDC_7 M_EDC_6

M_DBI4# M_DBI5# M_DBI7# M_DBI6#

M_CLK1 M_CLK#1 M_CKE1

M1_MA2 M1_MA5 M1_MA4 M1_MA3

M1_MA7 M1_MA1 M1_MA0 M1_MA6 M1_MA8

M_ADBI1 M_RAS#1 M_CS1B#0 M_CAS#1 M_WE#1

M_WCKA1_0# M_WCKA1_0

M_WCKA1_1# M_WCKA1_1

+FBA_VREFC0

DRAM_RST

UV8

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

12 12 12

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

SGRAM GDDR5

170-BALL

K4G80325FB-HC03_FBGA170~D

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

X76@

M_DA38

A4

M_DA37

A2

M_DA36

B4

M_DA39

B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1

VDDQ

D1

VDDQ

F1

VDDQ

M1

VDDQ

P1

VDDQ

T1

VDDQ

G2

VDDQ

L2

VDDQ

B3

VDDQ

D3

VDDQ

F3

VDDQ

H3

VDDQ

K3

VDDQ

M3

VDDQ

P3

VDDQ

T3

VDDQ

E5

VDDQ

N5

VDDQ

E10

VDDQ

N10

VDDQ

B12

VDDQ

D12

VDDQ

F12

VDDQ

H12

VDDQ

K12

VDDQ

M12

VDDQ

P12

VDDQ

T12

VDDQ

G13

VDDQ

L13

VDDQ

B14

VDDQ

D14

VDDQ

F14

VDDQ

M14

VDDQ

P14

VDDQ

T14

VDDQ

A1

VSSQ

C1

VSSQ

E1

VSSQ

N1

VSSQ

R1

VSSQ

U1

VSSQ

H2

VSSQ

K2

VSSQ

A3

VSSQ

C3

VSSQ

E3

VSSQ

N3

VSSQ

R3

VSSQ

U3

VSSQ

C4

VSSQ

R4

VSSQ

F5

VSSQ

M5

VSSQ

F10

VSSQ

M10

VSSQ

C11

VSSQ

R11

VSSQ

A12

VSSQ

C12

VSSQ

E12

VSSQ

N12

VSSQ

R12

VSSQ

U12

VSSQ

H13

VSSQ

K13

VSSQ

A14

VSSQ

C14

VSSQ

E14

VSSQ

N14

VSSQ

R14

VSSQ

U14

VSSQ

M_DA33 M_DA35 M_DA32 M_DA34 M_DA41 M_DA43 M_DA40 M_DA42 M_DA44 M_DA45 M_DA46 M_DA47 M_DA62 M_DA61 M_DA63 M_DA60 M_DA57 M_DA58 M_DA56 M_DA59 M_DA55 M_DA48 M_DA52 M_DA51 M_DA54 M_DA50 M_DA53 M_DA49

BYTE4

BYTE5

BYTE7

BYTE6

+1.35VS_VRAM+1.35VS_VRAM

+1.35VS_VRAM

10U_0603_6.3V6M

CV90

1

DIS@

2

A A

5

1U_0402_6.3V6K

CV91

CV93

CV92

1

@

DIS@

2

0.1U_0201_10V K X5R

1U_0402_6.3V6K

CV96

CV94

CV95

1

@

DIS@

2

0.1U_0201_10V K X5R

CV97

CV98

1

DIS@

@

2

4

0.1U_0201_10V K X5R

CV99

CV101

CV100

1

DIS@

2

DIS@

2

0.1U_0201_10V K X5R

CV102

1

DIS@

2

0.1U_0201_10V K X5R

CV104

CV103

CV105

1

DIS@

@

2

+1.35VS_VRAM

0.1U_0201_10V K X5R

1U_0402_6.3V6K

CV106

1

2

10U_0603_6.3V6M

1U_0402_6.3V6K

10U_0603_6.3V6M

CV108

CV110

CV109

CV107

1

DIS@

2

DIS@

@

DIS@

2

DIS@

2

3

0.1U_0201_10V K X5R

1U_0402_6.3V6K

CV111

1

DIS@

2

CV114

CV113

CV112

1

@

2

0.1U_0201_10V K X5R

CV115

1

DIS@

2

0.1U_0201_10V K X5R

CV116

1

@

2

CV119

CV117

CV118

1

DIS@

@

2

0.1U_0201_10V K X5R

CV121

CV122

CV120

1

@

DIS@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

2016/12/05 2017/12/05

Deciphered Date

Compal Electronics, Inc.

Title

GDDR5_A0

Size

Document Number Rev

Date: Sh eet of

LA-E981P

26 66Thursday, June 15, 2017

1

26 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

C

Layout Rout i ng

LPC LPC

CPU

D D

C C

TPM

LPC_AD0[8,45] LPC_AD1[8,45] LPC_AD2[8,45] LPC_AD3[8,45]

CK_LPC_TPM[8]

LPC_FRAME#[8,45]

PCIRST#[10,21,31,32,36,45]

EC

R5

TPM@

0_0201_5%

SD043000080

+3VS +3VS_TPM

R5

TCM@

0_0201_5%

SD043000080

1 2

R5 0_0201_5%@

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 CK_LPC_TPM

LPC_FRAME# PCIRST#

1 2

R426 0_0201_5%TCM@

1

C489

27P_0402_50V8J @

2

4

U61

TPM@

TPM

SA00007XX30

U61

9

VDD

20

VDD

25

VDD

27

LAD0

24

LAD1

21

LAD2

19

LAD3

22

LCLK

23

LFRAME#

18

LRESET#

11

GND

16

GND

26

GND

32

GND

33

PGND

Z32H320TC-LPC-Q32401_QFN32_5X5

SA00009FM20 Z32H320TC-LPC-Q32-LC_QFN32_5X5

U61

TCM@

TCM

SA00009FM20

3

C462

C458

TPM@

SE00000SV00

TPM@

SE000000K80

0.1U_0201_10V6K

1U_0402_6.3V6K

+3VS_TPM

<  

C463

0.1U_0201_10V6K

C464

0.1U_0201_10V6K

1

2

TCM@

10U_0402_6.3V6M

C458

C462

0.1U_0201_10V6K

1

TCM@

2

TCM@

# )

Pin1 Pin2 Pin3 Pin4 Pin5 Pin6

@

1 2

1

R427 0_0201_5%TPM@

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

2 3 4 5 6 7 8 10 12 13 14 15 17 28 29 30 31

1 2

R3170 4.7K_0201_5%TPM@

1 2

R422 0_0201_5%TPM@

1 2

R424 0_0201_5%TPM@

1 2

R425 4.7K_0201_ 5%TPM@

+3VS_TPM

SERIRQ [8,45]

Pin7 Pin8 Pin9 Pin1 0 Pin1 1 Pin1 2 Pin1 3 Pin1 4 Pin1 5 Pin1 6

:  N 

NC NC NC NC NC NC NC NC VDD NC GND NC NC NC NC

2

'$   

VDD GPIO NC NC NC NC NC NC VDD VDD NC NC NC NC GND GNDG ND

Pin1 7 Pin1 8 Pin1 9 Pin2 0 Pin2 1 Pin2 2 Pin2 3 Pin2 4 Pin2 5 Pin2 6 Pin2 7 Pin2 8 Pin2 9 Pin3 0 Pin3 1 Pin3 2

:  N

'$  





NC N C

LRES ET#LR ESE T#

LAD3 LAD3 VDD VDD LAD2 LAD2 LCLK LCLK

LFRA ME#LF RAM E#

LAD1 LAD1 VDD VDD GND GND LAD0 LAD0 NC

SERI RQ

NC

PP

GND GND

1

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2016/06.23 2017/06/23

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

TPM/TCM

Document Number Re v

LA-E581P

1

27 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5



+3VS

A A

D D

C C

B B

0606 change

CMOS_ON#[45]

0428 SWAP

USB20_N5[12]

USB20_P5[12]

SKL@

1 2

R7

150K_0402_5%

CMOS@

1 2

R463 0_0402_5%

Q30

D

S

13

SKL@

LP2301ALT1G_SOT23-3

G

2

1

C7

@

0.1U_0201_10V6K

2

EMI@

EXC24CG900U_4P

4

1

L14

EMI@

12

3

2

@EMI@

12

3

2

R476 0_0402_5%

R477 0_0402_5%

C470

SKL@

+3VS_CMOS

1

0.1U_0201_10V6K

2

USB20_N5_R

USB20_P5_R

1

C3

@

10U_0603_6.3V6M

2

4

+3VS

1

C6

@

1U_0402_6.3V6K

2

PCH_ENVDD[6]

AE

100K_0402_5%

BKOFF#[45]

EDP_HPD[6]

R8

12

@

R12

100K_0402_5%

R15

100K_0402_5%

3

4!&

U59

5

4

G524B1T11U SOT-23-5

IN

EN

1 2

12

BKOFF#

OUT

GND

OC

1

C9 22P_0402_50V8J

2

1

2

3

EDP_HPD

EMI@

AE

R6

1 2

0_0603_5%

+LCDVDD_CONN+LCDVDD_CONN_R

eDP

Came ra

+LCDVDD_CONN

1

C5

2

4.7U_0603_6.3V6K

INVPWM[6]

EDP_AUXN[6] EDP_AUXP[6]

EDP_TXP0[6] EDP_TXN0[6]

EDP_TXP1[6] EDP_TXN1[6]

+3VS_CMOS

DMIC_DET#[11]

DMIC_CLK[35] DMIC_DAT[35]

B+ +LEDVDD

1 2

R10 0_0805_5%

R_short

EDP_HPD

AE

1 2

C10 0.1U_0201_10 V K X5R

1 2

C11 0.1U_0201_10 V K X5R

1 2

C12 0.1U_0201_10 V K X5R

1 2

C13 0.1U_0201_10 V K X5R

1 2

C14 0.1U_0201_10 V K X5R

1 2

C15 0.1U_0201_10 V K X5R

USB20_N5_R USB20_P5_R

150P_0402_50V8J

1

2

A

+LCDVDD_CONN

150P_0402_50V8J

C505

EMI@

C502

1

2

10P_0402_25V8J

EMI@

1

C497

@RF@

2

BKOFF#

EDP_AUXN_C EDP_AUXP_C

EDP_TXP0_C EDP_TXN0_C

EDP_TXP1_C EDP_TXN1_C

4.7U_0805_25V6-K

C8

1

2

1

eDP PANEL Conn.

JEDP1

ME@

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26 27 28 29 30

ACES_50406-03071-001

eDP Connector PN SP01 0015 L00

31

26

G1

32

27

G2

33

28

G3

34

29

G4

35

30

G5

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size

Date: Sheet of

Compal Electronics, Inc.

eDP/CAMERA

Document Number Re v

Custom

LA-D562P

1

28 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

D D

C C

:O2!'

HDMI_CLK-_CK[6]

HDMI_CLK+_CK[6]

HDMI_TX0-_CK[6]

HDMI_TX0+_CK[6]

HDMI_TX1-_CK[6]

HDMI_TX1+_CK[6]

HDMI_TX2-_CK[6]

HDMI_TX2+_CK[6]

+3VS

1 2

R30 2.2K_0402_5%

1 2

R31 2.2K_0402_5%

HDMIDAT_NB(Internal Pull Down):

Display Port C Detected

0 = Port C is not detected.

1 2

C17 0.1U_0201_10V6K

1 2

C20 0.1U_0201_10V6K

1 2

C21 0.1U_0201_10V6K

1 2

C22 0.1U_0201_10V6K

1 2

C23 0.1U_0201_10V6K

1 2

C24 0.1U_0201_10V6K

1 2

C25 0.1U_0201_10V6K

1 2

C26 0.1U_0201_10V6K

HDMIDAT_NB

HDMICLK_NB

HDMI_CLK-_CK_C

HDMI_CLK+_CK_C

HDMI_TX0-_CK_C

HDMI_TX0+_CK_C

HDMI_TX1-_CK_C

HDMI_TX1+_CK_C

HDMI_TX2-_CK_C

HDMI_TX2+_CK_C

HDMICLK_NB[6]

HDMIDAT_NB[6]

1 = Port C is detected.

+5V_DSP

1 2

B B

R32 2.2K_0402_5%

1 2

R33 2.2K_0402_5%

HDMIDAT_R

HDMICLK_R

/!

D1

9

10

8

9

7

6

SC300003Z00

ESD@

1

2

4

5

3

8

1

2

4

5

3

HDMIDAT_R

HDMICLK_R

HDMIDAT_R

HDMICLK_R

HDMI_DET HDMI_DET

L05ESDL5V0NA-4_SLP2510P8-10-9

4

/'

:O2!'

1 2

R16 0_0402_5%EMI@

HDMI_CLK-_CONN

HDMI_CLK+_CONN

1 2

R18 0_0402_5%EMI@

1 2

R19 0_0402_5%EMI@

HDMI_TX0-_CONN

HDMI_TX0+_CONN

1 2

R21 0_0402_5%EMI@

1 2

R22 0_0402_5%EMI@

HDMI_TX1-_CONN

HDMI_TX1+_CONN

1 2

R25 0_0402_5%EMI@

1 2

R27 0_0402_5%EMI@

HDMI_TX2-_CONN

HDMI_TX2+_CONN

1 2

R29 0_0402_5%EMI@

+3VS

Q3A

2

L2N7002DW1T1G 2N SC88-6

5

4

Q3B L2N7002DW1T1G 2N SC88-6

HDMI_CLK+_CONN HDMI_CLK+_CONN

HDMI_TX0-_CONN HDMI_TX0-_CONN

HDMI_TX0+_CONN HDMI_TX0+_CONN

61

3

D2

ESD@

9

10

8

9

7

6

L05ESDL5V0NA-4_SLP2510P8-10-9

SC300003Z00

1

2

4

5

3

8

3

2!'

U9

+5VS

12

R17

@EMI@

150_0402_5%

12

R20

@EMI@

150_0402_5%

12

R24

@EMI@

150_0402_5%

12

R28

@EMI@

150_0402_5%

HDMICLK_R

HDMIDAT_R

HDMI_CLK-_CONNHDMI_CLK-_CONN

1

2

4

5

3

HDMI_TX1-_CONN HDMI_TX1-_CONN

HDMI_TX1+_CONN HDMI_TX1+_CONN

HDMI_TX2-_CONN

HDMI_TX2+_CONN

TMDS_B_HPD[6]

D3

9

10

8

9

7

6

L05ESDL5V0NA-4_SLP2510P8-10-9

SC300003Z00

0.1U_0201_10V6K

R23

1M_0402_5%

ESD@

1

2

4

5

3

8

@

C19

HDMI_TX2-_CONN

HDMI_TX2+_CONN

1

2

1 2

1

IN

G5250Q1T73U SOT-23

+3VS

2

Q2

G

2N7002K_SOT23-3

13

D

S

HDMI_TX1-_CK_C HDMI_TX1+_CK_C HDMI_TX2-_CK_C HDMI_TX2+_CK_C

HDMI_CLK-_CK_C HDMI_CLK+_CK_C HDMI_TX0-_CK_C HDMI_TX0+_CK_C

OUT

GND

1 2

2

AI

3

2

R26 20K_0402_5%

0.1U_0201_10V6K

RP8

45 36 27 18

470 +-5% 8P4R

RP9

18 27 36 45

470 +-5% 8P4R

+5V_DSP

C18

1

2

+5V_DSP

HDMI_DET

HDMIDAT_R HDMICLK_R

HDMI_CLK-_CONN

HDMI_CLK+_CONN HDMI_TX0-_CONN

HDMI_TX0+_CONN HDMI_TX1-_CONN

HDMI_TX1+_CONN HDMI_TX2-_CONN

HDMI_TX2+_CONN

13

D

G

S

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

ACON_HMRA3-AK120C

HDMI Connector PN DC232003A00

+3VS

2

Q4 2N7002K_SOT23-3

1

ZZZ15

45@

HDMI Logo

RO0000003HM

ME@

20

GND

21

GND

22

GND

23

GND

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size

C

Date: Sheet o f

HDMI CONN

Document Number Rev

LA-D562P

1

29 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

A

2!!

1 1

2 2

B

C

D

E

F

G

H

SATA HDD Conn.

JHDD1

ME@

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12 V1222GND

SDAN_603006-022041

JHDD Connector PN DC01000CE00

DC01000CE00

24

GND

23

R227

1 2

0_0805_5%

SATA_CTX_DRX_P0_C SATA_CTX_DRX_N0_C

SATA_CRX_DTX_N0_C SATA_CRX_DTX_P0_C

10U_0603_6.3V6M

C37

1

2

+5VS_HDD

1U_0402_6.3V6K

1

2

100mils

C38

@

0.1U_0201_10V K X5R

10P_0402_25V8J

C39

1

C500

RF@

2

1 2

SATA_CTX_DRX_P0[12] SATA_CTX_DRX_N0[12]

SATA_CRX_DTX_N0[12] SATA_CRX_DTX_P0[12]

C29 0.01U_0402_16V7K

1 2

C31 0.01U_0402_16V7K

1 2

C33 0.01U_0402_16V7K

1 2

C35 0.01U_0402_16V7K

+5VS +5VS_HDD

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

F

Compal Electronics, Inc.

Title

HDD/ODD Connector

Size

Document Number Rev

C

Date: Sheet o f

G

LA-D562P

0.1

30 66Thursday, June 15, 2017

H

0.1

Vinaﬁx.com

A

B

C

D

E

1 1

:8 $A43:#56@)/7

&'6' )7

JWLAN1

1

GND

BT

2 2

A43:

'

USB20_P6[12] USB20_N6[12]

1 2

PCIE_CTX_DRX_P6[12] PCIE_CTX_DRX_N6[12]

PCIE_CRX_DTX_P6[12] PCIE_CRX_DTX_N6[12]

CLK_PCIE_WLAN[10]

CLK_PCIE_WLAN#[10]

WLANCLK_REQ#[10]

EC_PCIE_WAKE#[36,45]

C48 0.1U_0402_25V6

1 2

C49 0.1U_0402_25V6

1 2

R50 0_0402_5%

1 2

R52 0_0402_5%

PCIE_CTX_C_DRX_P6 PCIE_CTX_C_DRX_N6

WLANCLK_REQ#_R WAKE#_R

3

USB_D+

5

USB_D-

7

GND

9

SIDO_CLK

11

SDIO_CMD

13

SDO_DAT0

15

SDO_DAT1

17

SDO_DAT2

19

SDO_DAT3

21

SDIO_WAKE#

23

SDIO_RESET#

25

GND

27

PETP0

29

PETN0

31

GND

33

PERP0

35

PERN0

37

GND

39

REFCLKP0

41

REFCLKN0

43

GND

45

CLKEQ0#

47

PEWAKE0#

49

GND

51

RSRVD/PETP1

53

RSRVD/PETN1

55

GND

57

RSRVD/PERP1

59

RSRVD/PERN1

61

GND

63

RESERVED

65

RESERVED

67

GND

69

MTG77

CONCR_213EAAA32FA

WLAN NGFF Connector PN SP070011I00

3.3VAUX

3.3VAUX LED1#

PCM_CLK

PCM_SYNC

PCM_IN

PCM_OUT

LED2#

UART_WAKE#

UART_RX

UART_TX UART_CTS UART_RTS RESERVED RESERVED RESERVED

COEX3 COEX2 COEX1

SUSCLK

PERST0#

W_DISABLE2# W_DISABLE1#

I2C_DATA

I2C_CLK

ALERT RESERVED RESERVED RESERVED RESERVED

3.3VAUX

MTG76

+3VS_WLAN

ME@

2 4 6 8 10 12 14 16 18

GND

20 22

24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66

68

100K_0402_5%

R54

1 2

UART_2_CRXD_DTXD_R

UART_2_CTXD_DRXD_R

SUSCLK_R WL_RST# BT_DISABLE_R

:B%($59!'354/

59!'354/4*A5*

59!'354/2'825*:

1 2

R44 0_0402_5%

1 2

R45 0_0402_5%

1 2

R46 0_0402_5%

1 2

R47 0_0402_5%

1 2

R48 0_0402_5%

1 2

R49 0_0402_5%

1 2

R51 0_0402_5%

1 2

R53 0_0402_5%

+3VS +3VS_WLAN

1 2

R43 0_0603_5%

1

4.7U_0603_6.3V6K

2

UART_2_CRXD_DTXD [11]

UART_2_CTXD_DRXD [11]

EC_TX [45] EC_RX [45]

SUSCLK [10]

PCIRST# [10,21,27,32,36,45]

WLBT_OFF# [11]

EC_WL_OFF# [12]

C46

1

C47

0.1U_0201_10V6K@

2

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Mini-Card/NEW Card/SIM

Size

Document Number Rev

Date: Sheet o f

LA-D562P

E

31 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

A

M.2 mSATA Conn

B

C

D

+3VS_NGFF

E

12

R55 10K_0402_5%

+3VS+3VS_NGFF

J1

1 1

PCIE_CRX_DTX_N9[12] PCIE_CRX_DTX_P9[12]

PCIE_CTX_DRX_N9[12] PCIE_CTX_DRX_P9[12]

PCIE_CRX_DTX_N10[12] PCIE_CRX_DTX_P10[12]

PCIE_CTX_DRX_N10[12] PCIE_CTX_DRX_P10[12]

PCIE_CRX_DTX_N11[12]

PCIE_CRX_DTX_P11[12]

PCIE_CTX_DRX_N11[12] PCIE_CTX_DRX_P11[12]

PCIE_CRX_DTX_P12[12] PCIE_CRX_DTX_N12[12]

PCIE_CTX_DRX_N12[12] PCIE_CTX_DRX_P12[12]

CLK_PCIE_M2#[10] CLK_PCIE_M2[10]

2 2

PCIE_CRX_DTX_N9 PCIE_CRX_DTX_P9

PCIE_CTX_DRX_N9 PCIE_CTX_DRX_P9

PCIE_CRX_DTX_N10 PCIE_CRX_DTX_P10

PCIE_CTX_DRX_N10 PCIE_CTX_DRX_P10

PCIE_CRX_DTX_N11 PCIE_CRX_DTX_P11

PCIE_CTX_DRX_N11 PCIE_CTX_DRX_P11

PCIE_CRX_DTX_P12 PCIE_CRX_DTX_N12

PCIE_CTX_DRX_N12 PCIE_CTX_DRX_P12

CLK_PCIE_M2# CLK_PCIE_M2

1 2

C50 0.22U_0402_10V6K

1 2

C51 0.22U_0402_10V6K

1 2

C52 0.22U_0402_10V6K

1 2

C53 0.22U_0402_10V6K

1 2

C54 0.22U_0402_10V6K

1 2

C55 0.22U_0402_10V6K

1 2

C56 0.22U_0402_10V6K

1 2

C57 0.22U_0402_10V6K

PCIE9_L3_TXN_CONN PCIE9_L3_TXP_CONN

PCIE10_L2_TXN_CONN PCIE10_L2_TXP_CONN

PCIE11_L1_TXN_CONN PCIE11_L1_TXP_CONN

PCIE12_L0_SATA1_TXN_CONN PCIE12_L0_SATA1_TXP_CONN

PE_DTCT

JSSD1

1

GND

3

GND

5

PERn3

7

PERp3

9

GND

11

PETn3

13

PETp3

15

GND

17

PERn2

19

PERp2

21

GND

23

PETn2

25

PETp2

27

GND

29

PERn1

31

PERp1

33

GND

35

PETn1

37

PETp1

39

GND

41

PERn0/SATA-B+

43

PERp0/SATA-B-

45

GND

47

PETn0/SATA-A-

49

PETp0/SATA-A+

51

GND

53

REFCLKN

55

REFCLKP

57

GND

59

NC PEDET(NC-PCIE/GND-SATA)613P3VAUX

63

GND

65

GND

67

GND

BELLW_80159-3221

JSSD Connector PN SP070018L00

3P3VAUX 3P3VAUX

DAS/DSS#

3P3VAUX 3P3VAUX 3P3VAUX 3P3VAUX

DEVSLP

PERST#

CLKREQ#

PEWake#

SUSCLK(32kHz)

3P3VAUX 3P3VAUX

GND1 GND2

ME@

NC NC

NC NC NC NC NC NC NC NC NC

NC NC NC NC NC

NC NC

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58

60 62 64 66

68 69

JUMP_43X39

112

1

C58 10U_0603_6.3V6M

2

@

2

PEDET (PE_DTCT) SATA Device GND PCIe Device Open

PCIRST#

1

RF@

C59 10P_0402_25V8J

2

PCIRST# [10,21,27,31,36,45]

M2CLK_REQ# [10]

PE_DTCT

2

G

13

D

2N7002KW_SOT323-3 Q5

S

SB000009Q80

SATA_GP2

PEDET (SATA_CP0) L : PCIE H : SATA

SATA_GP2 [12]

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2015/03/06 2016/12/31

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

M.2 SSD

Size

Document Number Re v

Custom

Merlyn LA-D211P

Date: Sheet o f

E

32 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

:*,*5:

NOVO#[45]

L03ESDL5V0CC3-2_SOT23-3

SCA00002900

J

Click Pad Pin define(Module)

Pin1

VDD_3. 3V

Pin2

SCL

Pin3

SDA

Pin4

GND INT

Pin5

LID CLOSE

Pin6



FP Pin define(Module)

Pin1

NC

Pin2

NC

Pin3

NC

Pin4

NC

Pin5

GND

Pin6

D+

Pin7

D-

Pin8

3.3VCC

3:

@

1 2

@

21

@5

1 2

470_0402_5%

1 2

470_0402_5%

1 2

470_0402_5%

CAPS_LED#[45]

R67

R68

R69

H23 HOLEA

H_2P3

H22 HOLEA

H_2P3

+5VS

+3VS

KB_DEL#[45]

KSI[0..7]

KSO[0..15]

A43:

@

1

@

1

R56 100_0402_5%

1 2

R58

100_0402_5%

1

C61

ESD@

2

0.1U_0201_10V K X5R

KSI[0..7] [45]

KSO[0..15] [45]

+5VALW

+5VS



H18

H13

HOLEA

@

1

H_3P2

H_3P3

!

H26

H19 HOLEA

@

1

MB_SUP_BRK_25X5

H_3P2

JKB1

+KB_VCC

1

2

3

KSO15

3

4

KSO10

4

5

KSO11

5

6

KSO14

6

7

KSO13

7

8

KSO12

8

9

KSO3

9

10

KSO6

10

11

KSO8

11

12

KSO7

12

13

KSO4

13

14

KSO2

14

15

KSI0

15

16

KSO1

16

17

KSO5

17

18

KSI3

18

19

KSI2

19

20

KSO0

20

21

KSI5

21

22

KSI4

22

23

KSO9

23

24

KSI6

24

25

KSI7

25

26

KSI1

26

27

28

29

30

31

32

ACES_51510-0320N-P01

JKB Connector PN SP0100 2F900

FD1

@

1

43:

H20 HOLEA

@

1

LANGAN LANGAN

H_3P2

ME@

33

GND

34

GND

@)%5J

12

R64 0_0402_5%

KBL@

KB_BL_PWM[45]

4/!

H4 HOLEA

H_3P3

H_2P1N

@

1

H8 HOLEA

@

1

R70

1 2

470_0402_5%

R71

1 2

499_0402_1%

H5 HOLEA

@

1

H_3P3

H24 HOLEA

@

1

H_1P5N

Compal Secret Data

Deciphered Date

BATT_CHG_LED#[45]

BATT_LOW_LED#[45]

FD2

FD3

FD4

@

1

H21 HOLEA

@

1

H_3P2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BATT_CHG_LED#

BATT_LOW_LED#

H2 HOLEA

H_3P3

,83

H3 HOLEA

@

1

H_3P3



H1 HOLEA

H_3P3

@

1

:2

H6

H7

HOLEA

@

1

H_2P1X2P6N

2011/06/24 2012/07/12

12

R61

Q6

10K_0402_5%

S

KBL@

G

2

R63

1 2

0_0402_5%

KBL@

1

KBL@

1

2

OUT

2

IN

@

GND

Q7

DTC124EKAT146_SC59-3

3

+5VALW

12

R66 0_0402_5%

LED3

WHITE

ORANGE

LTW-326DSKF-5A_WHI-ORG

213

WHITE ORANGE

P/N:SC 500007 F00

H30

H25

HOLEA

@

1

H_2P5N

H_1P5N

+VCC_KB_LED+5VS+5VS

D

13

ME2301DC-G_SOT23-3

KBL@

0.01U_0402_16V7K

10U_0603_6.3V6M

C63

1

KBL@

@

2

C65

Title

KBD/PWR/CR/LED/TP Conn.

Size

Document Number Rev

Custom

Date: Sheet of

JKBL1

1

0.1U_0201_10V K X5R

1

2

3

4

C64

Compal Electronics, Inc.

4

5

GND

6

GND

CVILU_CF5004FD0RD-10-NH

LTCX007VP00

JKBL Connector PN SP0100 2F900

LA-D562P

ME@

0.1

33 66Thursday, June 15, 2017

+3VLP

R59

1 2

3

ESD@

I2C1_SCL_TP[11] I2C1_SDA_TP[11]

TP_DISABLE#[45]

SW1

100K_0402_5%

1

2

D4

TCHC2QR_2P

1

+TP_VCC

R468

4.7K_0402_5%

1 2

TP_INT#[11]

@ESD@

D6

PSOT24C_SOT23-3

2

43

+3VS

2

3

1

4'!

+3VALW

0.1U_0201_10V6K

/!

1 2

R65 0_0402_5%

I2C1_SCL_TP I2C1_SDA_TP

1 2

R467 0_0402_5%

@ESD@

+TP_VCC

C60

1

OUTPUT

2

TCS20DLR SOT-23F 3P

SA00008K800

TP_INT# TP_Disable#_R

2

VDD

GND

1

1 2

U11

C68

1

@

2

0.1U_0201_10V6K

R57 100K_0402_5%

3

C69

1

@

2

0.1U_0201_10V6K

LID_SW#

2

C62

10P_0402_50V8J

1

C67

1

@

2

JTP Connector PN

0.1U_0201_10V6K

SP0100 20S00

LID_SW# [45]

JTP1

1

2

3

4

5

6

7

GND

8

GND

ACES_50521-00641-P01

/!

+3VS

ACES_51580-00841-P01

USB20_N8 USB20_P8

USB20_P8USB20_N8

JFAN Connector PN SP0200 0CW00

+3VS_FP

1 2 3 4

6 7 8

JFP Connector PN SP0100 2GM00

JFAN1

1

2

3

4

5

G1

6

G2

ACES_85204-04001

ME@

1 2 3

9

4

GND

10

55GND 6 7 8

JFP1

ME@

+5VS

+3VS_FP

L30ESDL5V0C6-4_SOT23-6

1 2

R72

0_0603_5%

D7

4

5

6

SC300003V00

1 2

R447 0_0402_5%FP@

USB20_N8[12] USB20_P8[12]

ESD@

3

4

2

GND

Vbus

1

6

EC_FAN_PWM[45]

EC_FAN_SPEED[45]

+5VS_FAN

2

C70 10U_0603_6.3V6M

1

5:

+3VLP

R60 100K_0402_5%

SCA00002900

1 2

2

3

ESD@

1

ON/OFF#

ON/OFF#[45]

L03ESDL5V0CC3-2_SOT23-3

/!

ME@

ON TOP

D5

J2 SHORT PADS

1 2

Power BTN

SN100004Y00

SW2 SKQGPAE010_6P

5

ON/OFF#

6

ON BOTTOM

1 2

321

4

J3 SHORT PADS

4/!

LED1

PWR_LED#

CLIP7 HOLEA

CLIP12 HOLEA

PWR_LED#[45]

DCIN_LED#[45]

PCH_SATALED#[12]

H9 HOLEA

@

1

H_4P4

H14 HOLEA

CLIP8

@

1

HOLEA

@

1

@

1

CLIP13 HOLEA

H_2P3

1

H27 HOLEA

@

1

@

1

H_2P3

DCIN_LED#

PCH_SATALED#

H10 HOLEA

@

1

H_2P3

H15 HOLEA

@

1

H_2P3

H28 HOLEA

@

1

H_2P3

LTW-C193TS5-C_WHITE

SC50000BB10

LED2

LTW-270US5_WHITE

SC50000DD00

LED4

LTW-270US5_WHITE

SC50000DD00

H11 HOLEA

@

1

H_2P3

H16 HOLEA

@

1

H_2P3

H29 HOLEA

@

1

H_2P3

H12 HOLEA

H_4P4

H17 HOLEA

H_2P3

1

@

1



4

CLIP1

CLIP2

HOLEA

@

1



CLIP4

CLIP5

HOLEA

@

1

CLIP9

CLIP10

HOLEA

@

1

CLIP3 HOLEA

CLIP6 HOLEA

CLIP11 HOLEA

@

1

@

1

@

1

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+5VALWP

22U_0603_6.3V6M

C519

5

22U_0603_6.3V6M

C522

C520

C521

1

@

2

1

@

2

22U_0603_6.3V6M

C523

C524

C525

1

@

1

@

2

47U_0805_6.3V6M

10U_0603_6.3V6M

C528

C526

C527

1

@

2

For USB Charger to improve +5VALWP power ripple

4

,>>) :*:3*

USB_EN#[45,46]

NONAOU@

1 2

C71

0.1U_0201_10V K X5R

USB20_P1

USB20_N1 USB20_CH_N1

U55

NONAOU@

1

OUT

5

IN

2

GND

4

EN

3

OCB

SY6288D20AAC_SOT23-5

1 2

R232 0_0402_5%

NONAOU@

1 2

R233 0_0402_5%

NONAOU@

W=80milsW=80mils

+5V_CHGUSB+5VALW

USB20_CH_P1

R73 0_0402_5%

1 2

NONAOU@

3

USB_OC0# [12]

5>C

USB_EN#

5

4

2

C248

0.1U_0201_10V K X5R

1

U56

1

OUT

IN

2

GND

EN

3

OCB

SY6288D20AAC_SOT23-5

2

W=80milsW=80mils

+5V_USB+5VALW

R228 0_0402_5%

1 2

USB_OC1# [12]

1

0411

USB20_N2_L USB20_P2_L

USB3_RX_N2_R USB3_RX_P2_R

USB3_TX_N2_C_R USB3_TX_P2_C_R

+5V_USB

150U_B2_6.3VM_R35M

10P_0402_25V8J

1

C472

+

C499

RF@

2

JUSB2

ME@

1

VBUS

2

D-

3

D+

4

GND

5

SSRX-

6

10

SSRX+

GND

7

11

GND

8

12

SSTX-

GND

9

13

SSTX+

GND

ACON_TARAC-9U1U91

USB3.0 Connector PN DC2330 0AGB0

1

@

C471 470P_0402_50V7K

2

22U_0603_6.3V6M

0.1U_0201_10V K X5R

22U_0603_6.3V6M

C517

C518

1

AOU@

R74

10K_0402_5%

1 2

USB_CHG_STATUS#[45]

0606 add

USB_CHG_ILIM_SEL[45]

C C

USB_CHG_CTL1[45] USB_CHG_CTL2[45] USB_CHG_CTL3[45]

USB_CHG_STATUS#

R76

USB_CHG_EN

USB_CHG_EN[45]

USB_CHG_CTL1 USB_CHG_CTL2 USB_CHG_CTL3

0_0402_5%

@

2

USB_OC0#_U12USB_OC0#

12

@

C516

1

R89

10K_0402_5%

@

2

0.1U_0201_10V K X5R

12

R75

10K_0402_5%

AOU@

U12

1

IN

9

STATUS#

13

FAULT#

4

ILIM_SEL

5

EN

6

CTL1

7

CTL2

8

CTL3

1

AOU@

C76

TPS2546RTER QFN 16P

SA000064O00

2

+5V_CHGUSB+5VALW_USBCH+3VALW

80mil

AOU@

12

DM_OUT DP_OUT

ILIM_LO

DM_IN

ILIM_HI

T-PAD

OUT

DP_IN

GND

10 11 2 3 15 16 14 17

USB20_CH_P1 USB20_CH_N1 USB20_N1 USB20_P1

1 2

R77 20K_0402_1%AOU@

1 2

R78 24.9K_0402_1%

AOU@

USB20_N1 [12] USB20_P1 [12]

5>CA5C  

3V/5VALW_PG[40,45,52,53,55]

5>C9

JUSB1

ME@

1

USB20_N1_L

USB3_RX_N1[12]

B B

USB3_RX_P1[12]

USB3_TX_N1[12] USB3_TX_P1[12]

12

C75 0.1U_0201_10V K X5R

12

C74 0.1U_0201_10V K X5R

USB3_RX_N1 USB3_RX_P1

USB3_TX_N1_C USB3_TX_P1_C

USB20_P1_L

VBUS

2

D-

3

D+

4

GND

5

SSRX-

6

10

SSRX+

GND

7

11

GND

8

12

SSTX-

GND

9

13

SSTX+

GND

ACON_TARAC-9U1U91

0406 Change Conn

USB3.0 Connector PN DC2330 0AGB0

22U_0603_6.3V6M

+5VL

AOU@

C454

R446

AOU control

+5VL

+5VALW_USBCH

AOU@

12

R234

0_0603_5%

1

2

AOU@

1 2

100K_0402_5%

13

D

2

AOU@

G

Q29

2N7002K_SOT23-3

S

+5V_CHGUSB+5V_CHGUSB

150U_B2_6.3VM_R35M

10P_0402_25V8J

1

C247

+

2

+5VALW

@

12

R231

0_0603_5%

D

S

13

Q28

1

AOU@

G

C453

2

22U_0603_6.3V6M

2

ME2301DC-G_SOT23-3

1

AOU@

C466 .1U_0402_16V7K

2

1

@

C498

C246

RF@

470P_0402_50V7K

2

USB3_RX_N2[12]

USB3_RX_P2[12]

USB3_TX_N2

USB3_TX_N2[12]

USB3_TX_P2

USB3_TX_P2[12]

USB20_N2[12]

USB20_P2[12]

C481

0.1U_0201_10V K X5R

C480

0.1U_0201_10V K X5R

USB3_RX_N2

USB3_RX_P2

0614 swap L2002,L2003

USB3_TX_N2_C

12

USB3_TX_P2_C

12

L11

443

1

EXC24CG900U_4P

EMI@

2

R3188 0_0402_5%RF@

L2002

@RF@

2

3

DLW21HN900HQ2L_4P

R3189 0_0402_5%

RF@

R3190 0_0402_5%RF@

L2003

@RF@

2

3

DLW21HN900HQ2L_4P

R3191 0_0402_5%

RF@

USB20_N2_L

3

USB20_P2_L

2

12

1

443

12

1

443

12

/!

D38

4

5

Vbus

6

L30ESDL5V0C6-4_SOT23-6

SC300004W00

ESD@

3

2

GND

1

Title

<Title>

Size

Document Number Rev

Document Number Rev <Doc> <RevCode>

Custom

Custom

Custom

Date: Sh eet o f

1

34 66Thursday, June 15, 2017

D8

/!

D43

USB3_RX_N1

USB3_RX_P1

USB3_TX_N1_C

L13

EMI@

USB20_CH_P1

A A

USB20_CH_N1

1

443

EXC24CG900U_4P

5

USB20_P1_L

2

USB20_N1_L

3

USB3_TX_P1_C

ESD@

1

9

10

1

2

8

9

2

4

7

4

5

6

5

3

8

L05ESDL5V0NA-4_SLP2510P8-10-9

SC300003Z00

USB3_RX_N1

USB3_RX_P1

USB3_TX_N1_C

USB3_TX_P1_C

4

+5V_CHGUSB

USB20_N1_L USB20_P1_L

4

5

Vbus

6

L30ESDL5V0C6-4_SOT23-6

SC300004W00

ESD@

3

USB3_RX_P2_R

USB3_TX_N2_C_R

2

GND

1

3

USB3_TX_P2_C_R USB3_TX_P2_C_R

D39

ESD@

1

9

10

1

2

8

9

2

4

7

4

5

6

5

3

8

L05ESDL5V0NA-4_SLP2510P8-10-9

SC300003Z00

USB3_TX_N2_C_R

USB20_N2_L USB20_P2_L

USB3_RX_N2_RUSB3_RX_N2_R

USB3_RX_P2_R

+5V_USB

2

Vinaﬁx.com

12

C90 22P_0402_50V8J

@EMI@

1 2

R88 0_0402_5%

R91 10K_0402_5%@

DMIC_DAT[28]

DMIC_CLK[28]

1 2

+IOVDD_CODEC

D

12

C100

1U_0402_6.3V6K

A

+AVDD_CODEC

+3VDD_CODEC

+IOVDD_CODEC

1 2

R87

33_0402_5%

1

C99

2

0.1U_0201_10V6K

A

C88 4.7U_0603_6.3V6K

1 2

R82

33_0402_5%

@EMI@

HDA_SDIN0_AUDIO

PC_BEEP

1 2

R475

33_0402_5%

EMI@

SPK_L+

SPK_L-

SPK_R-

SPK_R+

R102 0_0603_5%

+3VS

1

12

C81

2

0.1U_0201_10V6K

24

DVDD33

AVDD_HP

1 2 1 2 1 2 1 2

2

27

28

29

AVDD_5V

FILT_1.65V

AVDD_3.3V

PORT_B_R_LINE

PORT_B_L_LINE

PORTD_B_MIC PORTD_A_MIC

EP_GND

41

CX11802-33Z_QFN40_5X5

wide 40MIL

2.2U_0402_6.3V6M

13

C82

16

LPWR5.0

MICBIASC MICBIASB

PORTA_R

RPWR5.0

PORTA_L

C79

C80

1U_0402_6.3V6K

12

2

3

7

18

U60

VDD_IO

VDDO33

FILT_1.8V

9

RESET#

CX11802-33Z

5

BIT_CLK

8

SYNC

6

SDATA_IN

4

SDATA_OUT

39

SPKR_MUTE#

10

PC_BEEP

1

DMIC_DAT/GPIO1

40

DMIC_CLK/MUSIC_REQ/GPIO0

37

GPIO1/PORTC_R_MIC

36

MUSIC_REQ/GPIO0/PORTC_L_MIC

12

LEFT+

14

LEFT-

15

RIGHT-

17

RIGHT+

Speaker

SPK_R+

R79 0_0603_5% R80 0_0603_5%

SPK_L+ SPK_L+_CONN

R421 0_0603_5% R420 0_0603_5%

/'

+3VDD_CODEC+AVDD_CODEC

1 2

1

12

C102

C101

2

1U_0402_6.3V6K

0.1U_0201_10V6K

1

2

0.1U_0201_10V6K

GNDAGNDA

C455

2

1

0.1U_0201_10V K X5R

C83

1

2

4.7U_0603_6.3V6K

11

CLASS_D_REF

PLUG_IN_R

38

JSENSE

35 34

33 32

26

HGNDB

25

HGNDA

31 30

23 22

21

AVEE

20

FLY_N

19

1 2

C95 1U_0402_6.3V6K

FLY_P

0405 Change net name

1

C87

C89

C456

2

1000P_0402_50V7K

EMI@

5

BEEP#[45]

HDA_SPKR[9]

2

C84

1

HGNDB HGNDA EXT_MIC_RING2 EXT_MIC_SLEEVE

HP_OUTR HP_OUTL

AVEE

SPK_R+_CONN SPK_R-_CONNSPK_R-

SPK_L-_CONNSPK_L-

1000P_0402_50V7K

CX11802

1 1

HDA_RST_AUDIO#[9]

HDA_BITCLK_AUDIO[9] HDA_SYNC_AUDIO[9]

HDA_SDIN0[9]

HDA_SDOUT_AUDIO[9]

EC_MUTE#[45]

2 2

+3VS → +I OVDD_CODEC

+3VALW

1 2

+3VLP

R98 0_0603_5%

1 2

R101 0_0603_5%

3 3

4 4

+5VS_AVDD

1

C85

2

4.7U_0603_6.3V6K

1

C457

2

1000P_0402_50V7K

EMI@

B

1 2

R81 0_0603_5%

1

C86

0.1U_0201_10V K X5R

2

1

C96

2.2U_0402_6.3V6M

2

Speaker Connector PN SP02000 RR00

2

3

D9

@ESD@

L03ESDL5V0CC3-2_SOT23-3

SCA00002900

1

2

3

D37

@ESD@

L03ESDL5V0CC3-2_SOT23-3

SCA00002900

/!

1

1 2

R97 4.7K_0402_5%

1 2

R99 4.7K_0402_5%

B

+5VS

JSPK1

ME@

1

2

3

4

5

G1

6

G2

ACES_50278-00401-001

1 2

C97 0.1U_0201_10V K X5R

1 2

C98 0.1U_0201_10V K X5R

C

12

R439 0_0402_5%

12

R440 0_0402_5%

12

R441 0_0402_5%

12

R442 0_0402_5%

GND

GNDA

Combo Jack

HGNDB HGNDA

EXT_MIC_SLEEVE

1 2

EXT_MIC_RING2 HP_OUTL HP_OUTR

+3VS

12

R94

5.11K_0402_1%

1 2

R96 13.3K_0402_1%

R83 100_0402_5%

1 2

R84 100_0402_5%

W=40mils W=40mils

place close audio codec

PLUG_IN_R PLUG_IN

Each Platform Power Net Support List

AMD Carrizo

AMD Carrizo-L

Intel Broadwell

Intel Braswell

Intel Skylake

Intel Bay trail-M

12

C91 1U_0402_10V6K

12

C92 1U_0402_10V6K

1 2

EMI@

1 2

EMI@

R85 47_0402_5% R86 47_0402_5%

+1.5VS +1.8VS +3VS +5VS +3VALW

1.5V(S0) 1.8V(S0) 3.3V(S0) 5V(S0) 3.3V(S0 ~S5)

VVVVV

V VV V V

/ P   2!3 4 J ,    &6   D7

PC_BEEP

AMD Carrizo

AMD Carrizo-L

Intel Broadwell

Intel Braswell

Intel Skylake

Intel Bay trail-M

C

HPOUT_L HPOUT_R

：

V V

V

V V VVV

V

3.3V 1.5V/1.8 V

V V

/'

HGNDB HPOUT_L

PLUG_IN HPOUT_R

HGNDA

D

3

D40

ESD@

PESD5V0U2BT_SOT23-3

1

wide 60MIL

/!

2

3

D41

ESD@

PESD5V0U2BT_SOT23-3

1

HPOUT_L1

1 2

R460

0_0402_5%

HPOUT_R1

1 2

R459

0_0402_5%

C504 470P_0402_50V7KEMI@

C485 10P_0603_50V8-JEMI@

C484 10P_0603_50V8-JEMI@

C482 10P_0603_50V8-JEMI@

C483 10P_0603_50V8-JEMI@

1

2

E

Combo Jack (Normal Open)

JHP1

DC23000GT00

SINGA_2SJ3127-019111F

ME@

1 4

5

6 3

2

Audio Connector PN DC2300 0GT00

GNDA

VV

VVVV

：

V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

Compal Secret Data

2014/09/01 2015/09/01

Deciphered Date

Compal Electronics, Inc.

Title

HD Audio Codec_ALC3240

Size

Document Number R ev

Custom

Date: Sh eet of

LA-D562P

E

35 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

4

3

2

1

R103

12

0_0603_5%

2

C103

1U_0402_6.3V6K

D D

1

-   6  .Q<.7 C   " F>,94 3:  

+3V_LAN

W=60mils

1

C114

2

0.1U_0201_10V K X5R

4 )1D/ 4!*&

C C

4> >

/'

1 2

R110 0_0402_5%EMI@

1 2

R111 0_0402_5%EMI@

1 2

B B

A A

C120 0.1U_0201_10V K X5R@EMI@

1 2

C121 0.1U_0201_10V K X5R@EMI@

1 2

10P_0402_50V8J

1 2

10P_0402_50V8J

C122

C125

+3V_LAN+3VALW

W=60mi l60mil

1

@

C116

C115

2

0.1U_0201_10V K X5R

LANGAN

4

1

Y1 25MHZ_10PF_5YEA25000102IF50Q3

NC

OSC

SJ10000E500

OSC3NC

2

XTLO

R104

12

0_0603_5%

+LAN_SROUT1.05

0.1U_0201_10V K X5R

+3V_LAN

1

@

C108

2

4.7U_0603_6.3V6K

+3V_LAN

LANCLK_REQ#[10] PCIE_CTX_C_DRX_P5[12] PCIE_CTX_C_DRX_N5[12]

CLK_PCIE_LAN[10]

CLK_PCIE_LAN#[10]

1

C104

2

R105

+LAN_VDDREG

12

0_0603_5%

C107

@

Close to Pin23

+LAN_VDD +LAN_VDD

LAN_MDIP0 LAN_MDIN0

LAN_MDIP1 LAN_MDIN1 LAN_MDIP2 LAN_MDIN2

LAN_MDIP3 LAN_MDIN3

L1

1 2

2.2UH +-5% NLC252018T-2R2J-N

@

444E 4D I

6&% 7

W=40mils

1

C113

@

2

4.7U_0603_6.3V6K

0.1U_0201_10V K X5R

U57

1

MDIP0

2

MDIN0

3

AVDD10

4

MDIP1

5

MDIN1

6

MDIP2

7

MDIN2

8

AVDD10

9

MDIP3

10

MDIN3

11

AVDD33

12

CLKREQB

13

HSIP

14

HSIN

15

REFCLK_P

16

REFCLK_N

RTL8111H-CG_QFN32_4X4

+LAN_VDD

W=60mils

@

C105

1

2

+LAN_VDD

1

C109

2

1

@

C106

2

4.7U_0603_6.3V6K

0.1U_0201_10V K X5R

1

C110

2

0.1U_0201_10V K X5R

RTL8111 H

Please refer to the table above when using different 1.0V supply source.

1

C117

0.1U_0201_10V K X5R

1

C111

2

0.1U_0201_10V K X5R

Pin3 Pin8 Pin22 Pin 30 Pi n22

HSOP HSON

PERSTB

ISOLATEB

LANWAKEB

DVDD10 VDDREG REGOUT

LED2

LED1/GPO

LED0 CKXTAL1 CKXTAL2

AVDD10

RSET

AVDD33

PCIE_CRX_C_DTX_P5

17

PCIE_CRX_C_DTX_N5

18 19 20

ISOLATE#

21 22

+LAN_VDDREG

23

+LAN_SROUT1.05

24 25

LED1_GPIO

26 27 28

XTLO

29

XTLI

30 31 32 33

GND

Close to Pin17 Pin18

1 2

C118 0.1U_0201_10V K X5R

1 2

C119 0.1U_0201_10V K X5R

1 2

@

R108 10K_0402_5%

(8'* 

12

R1092.49K_0402_1%

+3V_LAN

1.0V LL1 CL16,CL 17 CL9,CL1 0 RL11 CL15

Source

LDO

X X X O O

+3VS

12

R106

1K_0402_5%

15K_0402_5%

ISOLATE#

R107

C112

1

2

1U_0402_6.3V6K

Pin20

PCIE_CRX_DTX_P5 [12] PCIE_CRX_DTX_N5 [12]

PCIRST# [10,21,27,31,32,45]

+3V_LAN

EC_PCIE_WAKE# [31,45]

RJ45_TX3-

RJ45_TX3+

RJ45_RX1-

RJ45_TX2-

RJ45_TX2+

RJ45_RX1+

RJ45_TX0-

RJ45_TX0+

RJ-45 CONN.

JLAN1

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

SANTA_130460-3

LAN Connector PN DC23400DP00

GND

ME@

12

11

10

9

LANGAN

/!

D10

LAN_MDIN3

+3V_LAN

XTLI

LAN_MDIN1

+3V_LAN

4

5

LAN_MDIP3 LAN_MDIN2

6

L30ESDL5V0C6-4_SOT23-6

D12

4

5

4

Vbus

6

SC300003V00

4

Vbus

ESD@

GND

ESD@

GND

LAN_MDIP2

3

+V_DAC

2

1

LAN_MDIP0

3

2

C123

1 2

0.01U_0402_25V7K

EMI@

*-# $ >#1#D

/'

LAN_MDIP0

LAN_MDIN0

+V_DAC

LAN_MDIP1

LAN_MDIN1

+V_DAC

LAN_MDIP2

LAN_MDIN2

+V_DAC

LAN_MDIP3

LAN_MDIN3

TL1

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2

6

TD2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

TD4-12MX4-

NS892407

MCT1

MX1+

MX1-

MCT2

MX2+

MX2-

MCT3

MX3+

MX3-

MCT4

MX4+

24

RJ45_TX0+

23

RJ45_TX0-

22

21

RJ45_RX1+

20

RJ45_RX1-

19

18

RJ45_TX2+

17

RJ45_TX2-

16

15

RJ45_TX3+

14

RJ45_TX3-

13

/'

MCT

R112

1 2

75_0805_5%

EMI@

D11 BS4200N-C-LV_SMB-F2

SCV00001H00

C124

1 2

0.01U_0402_25V7K

EMI@

12

EMI@

LANGAN

/'

Security Classification

LAN_MDIP1 LAN_MDIN0

6

L30ESDL5V0C6-4_SOT23-6

SC300003V00

5

4

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size

C

Date: Sheet o f

LAN_RTL8111H / RTL8107E

Document Number Rev

LA-D061P

1

36 66Thursday, June 15, 2017

0.3

Vinaﬁx.com

-

5

4

3

2

1

U62-2

X76@

RTS5146 Cardreader

SA0000AW900

USB20_CR_N7 USB20_CR_P7

SD_CD#

SD_D1

R457

6.2K_0402_1%

1 2

U62

@

3

DM

4

DP

10

SD_CD#

15

MS_INS#

9

GPIO

12

SD_DAT1

2

RREF

5

3V3_IN1

6

3V3_IN2

8

3V3_IN3

24

48MHz_In

25

GND

RTS5146-GR_ QFN24_4X4

SA0000AW900

Cardreader RTS5146 PN SA0000AW900

AV18

CARD_3V3

SDREG

SP10

1 7

16

11

SP1

13

SP2

14

SP3

17

SP4

18

SP5

19

SP6

20

SP7

21

SP8

22

SP9

23

USB20_N7[12]

USB20_P7[12]

+CARD_3V3

12

R472 0_0402_5%

X76@

SDREG

SD_WP SD_D0

SD_CLK

SD_CMD

SD_D3 SD_D2

2

1U_0402_6.3V6K

1

EMI@

12

R455 0_0402_5%

L15

@EMI@

4

1

EXC24CG900U_4P

R456 0_0402_5%

EMI@

3

2

12

C475

2

C476

1U_0402_6.3V6K

1

USB20_CR_N7

USB20_CR_P7

+CARD_3V3

C474

1

0.1U_0201_10V K X5R

2

C473

1

4.7U_0603_6.3V6K

2

Close to connector

+CARD_3V3

SD_CMD SD_CLK

SD_D0 SD_D1 SD_D2 SD_D3

SD_WP SD_CD#

SD_CLK_R

1 2

EMI@

R471 0_0402_5%

JCR1

4

VDD

2

CMD

5

CLK

3

VSS1

6

VSS2

7

DAT0

8

DAT1

9

DAT2

1

CD/DAT3

11

W/P

10

CD

T-SOL_156-1001902605~D

C503

5P_0402_50V9

1

EMI@

2

Cardreader Connector PN SP07001AC10

ME@

12

GND

13

GND

14

GND

15

GND

R464

1 2

0_0402_5%

U62-1

X76@

GENSYS Cardreader

SA0000AVM00

+3VS_CR

2

C478

1

0.1U_0201_10V6K

4.7U_0402_6.3V6M

2

C477

1

D D

+3VS

C C

B B

A A

0329 move

Title

<Title>

Size

Document Number Re v

Document Number Re v <Doc> <RevCode>

Custom

Custom

Custom

Date: Sheet o f

5

4

3

2

Date: Sheet o f

1

37 66Thursday, June 15, 2017

Vinaﬁx.com

5

4

3

2

1

+3VS+3VS

2

1

0.1U_0201_6.3V6K

1 2

3

C129

OUT1_AUXp_SCL OUT1_AUXn_SDA

OUT2_AUXp_SCL OUT2_AUXn_SDA

1

C130

2

0.01U_0201_6.3V7K

OUT1_D0p OUT1_D0n

OUT1_D1p OUT1_D1n

OUT1_D2p OUT1_D2n

OUT1_D3p OUT1_D3n

OUT2_D0p OUT2_D0n

OUT2_D1p OUT2_D1n

OUT2_D2p OUT2_D2n

OUT2_D3p OUT2_D3n

OUT1_CA_DET

OUT1_HPD

OUT2_CA_DET

OUT2_HPD

CEXT REXT

50 49

47 46

45 44

42 41

40 39

37 36

35 34

32 31

26 27

28 29

43 48

33 38

18

SW

8

PEQ

14

PD

17 20

R119 1M_0201_5%

1 2

PS8338_PEQ

R121 1M_0201_5%

C141 2.2U_0402_6.3V6M

R120 4.99K_0201_1%

2

1

1 2

PI1 (INT PD)

Auto test EN & Offset cancellation EN

Auto test DIS & Offset cancellation DIS

Auto test DIS & Offset cancellation EN

PI0 (INT PD)

1 2

Auto EQ DIS

Auto EQ EN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

1

2

C126

C127

2

1

0.1U_0201_6.3V6K

0.01U_0201_6.3V7K

DDIP2_0P_C DDIP2_0N_C

DDIP2_1P_C DDIP2_1N_C

DDIP2_2P_C DDIP2_2N_C

DDIP2_3P_C DDIP2_3N_C

DDIP2_AUXP_C DDIP2_AUXN_C

PS8338_PEQ

PS8338_PC10

PS8338_PC11

PS8338_PC20

PS8338_PC21

PS8338_PI1

PS8338_PI0

2.2K_0201_5%

4*8'

+3VS

12

2.2K_0201_5%

4.7K_0201_5%

R115

R114

R116

1 2

C131 0.1U_0201_6.3V6K

1 2

C132 0.1U_0201_6.3V6K

1 2

C133 0.1U_0201_6.3V6K

1 2

C134 0.1U_0201_6.3V6K

1 2

C135 0.1U_0201_6.3V6K

1 2

C136 0.1U_0201_6.3V6K

1 2

C137 0.1U_0201_6.3V6K

1 2

C138 0.1U_0201_6.3V6K

PS8338_PI1

TP1@

PS8338_PI0

1 2

C139 0.1U_0201_6.3V6K

1 2

C140 0.1U_0201_6.3V6K

PS8338_PC10 PS8338_PC11 PS8338_PC20 PS8338_PC21

+3VS

1 2

R122 @ 4.7K_0201_5%

1 2

R124 @ 4.7K_0201_5%

1 2

R126 4.7K_0201_5%@

1 2

R128 @ 4.7K_0201_5%

1 2

R130 @ 4.7K_0201_5%

1 2

R132 @ 4.7K_0201_5%

1 2

R134 @ 4.7K_0201_5%

4

D D

DDI2_TX0+_CK[6] DDI2_TX0-_CK[6]

DDI2_TX1+_CK[6] DDI2_TX1-_CK[6]

DDI2_TX2+_CK[6] DDI2_TX2-_CK[6]

DDI2_TX3+_CK[6] DDI2_TX3-_CK[6]

DDIP2_HPD[6]

C C

PEQ (INT PD)

HEQ 14.5dB

LLEQ 8.5dB

LEQ 11.5dB

B B

ASM

NO_ASM

NO_ASMASM

NO_ASM

PC10 (INT PD)

R123R122

ASM

R124 R125

AUX interception DIS Output 800mV & 0dB

AUX interception DIS Output 400mV & 0dB

AUX interception EN

A A

Swing +20%

Swing -16.7%

Swing default NO_ASMNO_ASM

NO_ASM

R126

ASM

NO_ASM

PC11 (INT PD)

5

R127

NO_ASM

ASM

NO_ASM

ASM

NO_ASM

ASM

DDIP2_CTRLCLK[6]

DDIP2_CTRLDATA[6]

DDIP2_AUXP[6] DDIP2_AUXN[6]

4*8'

PC20 (INT PD)

R128 R129

ASM NO_ASM

ASM ASM

NO_ASM NO_ASM

PC21 (INT PD)

R131R130

NO_ASM

ASMASM

4*8'

2

C128

1

0.1U_0201_6.3V6K

U13

5

VDD33

21

VDD33

30

VDD33

51

VDD33

57

VDD33

6

IN_D0p

7

IN_D0n

9

IN_D1p

10

IN_D1n

12

IN_D2p

13

IN_D2n

15

IN_D3p

16

IN_D3n

4

IN_CA_DET

3

IN_HPD

2

I2C_CTL_EN

1

Pl1/SCL_CTL

60

Pl0/SDA_CTL

22

IN_DDC_SCL

23

IN_DDC_SDA

24

IN_AUXp

25

IN_AUXn

59

CFG0

58

CFG1

56

PC10

55

PC11

54

PC20

53

PC21

11

GND

19

GND

52

GND

61

PAD(GND)

PS8338BQFN60GTR-A0_QFN60_5X9

PS8338BQFN60GTR-A1_QFN60_5X9

R123 @ 4.7K_0201_5%

R125 @ 4.7K_0201_5%

R127 4.7K_0201_5%@

R129 @ 4.7K_0201_5%

R131 @ 4.7K_0201_5%

R133 @ 4.7K_0201_5%

R437 100K_0402_5%

R118 100K_0402_5%TYPEC@

1 2

R134

ASM

NO_ASM

Compal Secret Data

2

+3VS

12

TYPEC@

100K_0402_5%

R438

R113

DMUX_TYPEC_DP2_P0 [40] DMUX_TYPEC_DP2_N0 [40]

DMUX_TYPEC_DP2_P1 [40] DMUX_TYPEC_DP2_N1 [40]

DMUX_TYPEC_DP2_P2 [40] DMUX_TYPEC_DP2_N2 [40]

DMUX_TYPEC_DP2_P3 [40] DMUX_TYPEC_DP2_N3 [40]

DMUX_CRT_DP2_P0 [39] DMUX_CRT_DP2_N0 [39]

DMUX_CRT_DP2_P1 [39] DMUX_CRT_DP2_N1 [39]

0223 link to Type-C MUX

DMUX_TYPEC_DP2_AUXP [40] DMUX_TYPEC_DP2_AUXN [40]

DMUX_CRT_DP2_AUXP [39] DMUX_CRT_DP2_AUXN [39]

DMUX_TYPEC_DP2_HPD [40]

DMUX_CRT_DP2_HPD [39]

Type-C MUX

CTR MUX

+3VS

R117

@

4.7K_0201_5%

1 2

12

R415 150K_0402_5%

TABLE : Automatic Switching Mode (CFG0 = H)

SW (DDI_PRIORITY2)

L Port 1 has higher priority when both ports are plugged H Port 2 has higher priority when both ports are plugged

R132 R133

ASM NO_ASM

4*8'

ASM

NO_ASM

4*8'

Compal Electronics, Inc.

Title

DDI DEMULTIPLEXER

Size

Document Number Re v

Custom

LA-C581P

Date: Sheet o f

ASM

NO_ASM

Deciphered Date

DDI_PRIORITY [9]

1

0.5

38 66Thursday, June 15, 2017

0.5

Vinaﬁx.com

5

D D

4

3

2

1

+3VS +3VS_AVCC

1 2

R137 0_0402_5%

Pin 4 & 25 Need conect same

C C

DMUX_CRT_DP2_AUXP[38] DMUX_CRT_DP2_AUXN[38]

DMUX_CRT_DP2_P0[38] DMUX_CRT_DP2_N0[38] DMUX_CRT_DP2_P1[38] DMUX_CRT_DP2_N1[38]

DMUX_CRT_DP2_HPD[38]

B B

net name(VCCK12) for vendor suggest

12

C144 0.1U_0201_10V K X5R

1 2

C145 0.1U_0201_10V K X5R

1 2

C146 0.1U_0201_10V K X5R

1 2

C148 0.1U_0201_10V K X5R

1 2

C152 0.1U_0201_10V K X5R

1 2

C153 0.1U_0201_10V K X5R

1 2

C154 0.1U_0201_10V K X5R

+3VS

SOC_SML1CLK[8,22,45,46] SOC_SML1DATA[8,22,45,46]

+3VS +3VS

12

R143

4.7K_0402_5%

POL2_SCL

12

@

12

R142100K_0402_5% @

R144

4.7K_0402_5%

POL1_SDA

R444

4.7K_0402_5%

R139

1 2

+3VS_AVCC +3VS_VDD

+3VS

U14

1

12 12

4.7K_0402_5%@

R1400_0402_5% @ R1410_0402_5% @

VCCK_12

DP_CRT_AUXP DP_CRT_AUXN

DP_CRT_P0 DP_CRT_N0 DP_CRT_P1 DP_CRT_N1

POL1_SDA POL2_SCL

CRT_CLK CRT_DATA

CRT_SMB_CLK CRT_SMB_SDA

AVC33

4

AVCC_12

14

VCC_33

2

AUX_P

3

AUX_N

5

LANE0_P

6

LANE0_N

7

LANE1_P

8

LANE1_N

10

POL1/SPI_CEB

9

POL2

11

GPI1/SPI_CLK

12

GPI2/SPI_SI

13

GPI3/SPI_SO

15

VGA_SCL

16

VGA_SDA

30

SMB_SCL

29

SMB_SDA

32

HPD

+3VS

12

R445

LDO_EN:

4.7K_0402_5%

0: External 1.2V input

LDO_EN

1: Internal 1.2V input

RTD2166

VDD_DAC_33

HVSYNC_PWR

LDO_RSTB

EXT_CLK_IN

EXT1.2V_CTRL

EPAD_GND

RTD2166-CG_QFN32_4X4

R143+R144 : Flash Mode

R143+R444 : ROM Mode

A A

!$&

VCCK_12

PVCC_33

VSYNC

HSYNC

BLUE_P

GREEN_P

RED_P

+3VS_VDD

2

1

C142

0.1U_0201_10V K X5R

20

VCCK_12

25

26

17 18 19

21

22

23

LDO_EN

27 28 31

24

GND

33

VSYNC HSYNC

CRT_B

CRT_G

CRT_R

+3VS

+5V_DSP

+3VS

12

R1380_0402_5%

1 2

C1432.2U_0402_6.3V6M

1 2

C1490.1U_0201_10V K X5R

1 2

C1500.1U_0201_10V K X5R

1 2

C1474.7U_0805_25V6-K

1 2

C1510.1U_0201_10V K X5R

VSYNC

R3182 47_0402_5%

HSYNC

R3183 47_0402_5%

1 2

CRT_VSYNC

CRT_HSYNC

C536 2P_0201_25V8B

C537 2P_0201_25V8B

1

2

+5V_DSP

/!

CRT_CLK

+5V_DSP

VSYNC

CRT_R_2

+5V_DSP

D13

4

Vbus

6

SC300003V00

D14

4

Vbus

ESD@

4

5

6

L30ESDL5V0C6-4_SOT23-6

4

5

3

HSYNC

3

2

GND

CRT_B_2

1

CRT_DATA

3

2

GND

/'

L2

SM01000LU00

EMI@

10P_0603_50V8-J

EMI@

C156

1

2

MURATA BLM15BA220SN1D 0402

1 2

EMI@

L3

SM01000LU00

MURATA BLM15BA220SN1D 0402

1 2

EMI@

L4

SM01000LU00

MURATA BLM15BA220SN1D 0402

1 2

EMI@

10P_0603_50V8-J

C157

1

2

10P_0603_50V8-J

EMI@

C467

1

2

CRT_R

CRT_G

CRT_B CRT_B_2

R3155 75_0402_1%

R3157 75_0402_1%

R3156 75_0402_1%

12

10P_0603_50V8-J

EMI@

C155

1

2

CRT_R_2

CRT_G_2

10P_0603_50V8-J

EMI@

10P_0603_50V8-J

EMI@

C469

C468

1

2

CRT_DATA

CRT_HSYNC

CRT_VSYNC

CRT_CLK

1 2

-

R145 2.2K_0402_5%

R146 2.2K_0402_5%

JVGA1

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

CCM_070546HR015M28BZR

CRT Connector PN DC06 000C0 B0

ME@

G

16

G

17

Security Classification

CRT_G_2

6

L30ESDL5V0C6-4_SOT23-6

SC300003V00

5

4

1

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/08/16 2015/08/16

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

DP to VGA - RTD2168

Size

Document Number R ev

Custom

Date: Shee t o f

LA-D061P

1

39 66Thursday, June 15, 2017

0.3

Vinaﬁx.com

5

4

3

2

1

dead battery

+VBUS_5455

1 2

R149 0_0402_5%

TYPEC@

1M_0402_5%

TYPEC@

D D

3V/5VALW_PG[34,45,52,53,55]

L2N7002DW1T1G 2N SC88-6

+5VALW +VCON_IN_5455

Realtek RTS5455

10Gps 3:2 MUX

Low Speed MUX

BC1.2 Switch

3V/5VALW_PG

MGPIO10/

RTS5455-GR_QFN46_6P5X4P5

1 2

R147 0_0603_5%

TYPEC@

Close to Pin10

C C

From USB3.1

From DP MUX

TO SOC

B B

TYPEC@

4.7U_0603_6.3V6K

DMUX_TYPEC_DP2_P0[38] DMUX_TYPEC_DP2_N0[38]

DMUX_TYPEC_DP2_P1[38] DMUX_TYPEC_DP2_N1[38]

DMUX_TYPEC_DP2_P2[38] DMUX_TYPEC_DP2_N2[38]

DMUX_TYPEC_DP2_P3[38] DMUX_TYPEC_DP2_N3[38]

DMUX_TYPEC_DP2_AUXP[38] DMUX_TYPEC_DP2_AUXN[38]

DMUX_TYPEC_DP2_HPD[38]

10U_0402_6.3V6M

C158

C217

1

TYPEC@

2

+LDO_3V3_5455 +3.3V_IN_5455

C167

TYPEC@

12

USB3_RX_P4[12] USB3_RX_N4[12]

USB3_TX_P4[12]

USB3_TX_N4[12]

100K_0402_5%

TYPEC@

LP2301ALT1G_SOT23-3

GPIO9

TYPEC@

Support 3.3V IN version

TYPEC@

1 2

R156 0_0402_5%

C170 0.22U_0402_10V6KTYPEC@ C171 0.22U_0402_10V6KTYPEC@

C173 0.22U_0402_10V6KTYPEC@ C175 0.22U_0402_10V6KTYPEC@

C176 0.1U_0201_6.3V6KTYPEC@ C177 0.1U_0201_6.3V6KTYPEC@

C178 0.1U_0201_6.3V6KTYPEC@ C180 0.1U_0201_6.3V6KTYPEC@

C182 0.1U_0201_6.3V6KTYPEC@ C183 0.1U_0201_6.3V6KTYPEC@

C184 0.1U_0201_6.3V6KTYPEC@ C185 0.1U_0201_6.3V6KTYPEC@

C186 0.1U_0201_10V6KTYPEC@ C187 0.1U_0201_10V6KTYPEC@

12

R171

47K_0603_1%

1 2 1 2

EC_SMB_DA2[45]

EC_SMB_CK2[45]

PD_INT[45]

R219

TYPEC@

2

12

6.2K_0402_1%

Q1

G

TYPEC@

13

D

@

R220 0_0402_5%

S

1 2

+VCON_IN_1_5455

USB3_RX_P4_C USB3_RX_N4_C

USB3_TX_P4_C USB3_TX_N4_C

DMUX_TYPEC_DP2_P0_C DMUX_TYPEC_DP2_N0_C

DMUX_TYPEC_DP2_P1_C DMUX_TYPEC_DP2_N1_C

DMUX_TYPEC_DP2_P2_C DMUX_TYPEC_DP2_N2_C

DMUX_TYPEC_DP2_P3_C DMUX_TYPEC_DP2_N3_C

SOC_DP1_AUXP_C SOC_DP1_AUXN_C

DMUX_TYPEC_DP2_HPD

EC_SMB_DA2 EC_SMB_CK2 PD_INT

12

R164

U16

10

VCON_IN

25

5V_IN

26

LDO_3V3

39

SSRX_1P/2N

40

SSRX_1N/2P

41

SSTX_1P/2N

42

SSTX_1N/2P

35

DP0_1P/2N

36

DP0_1N/2P

43

DP1_1P/2N

44

DP1_1N/2P

45

DP2_1P/2N

46

DP2_1N/2P

37

DP3_1P/2N

38

DP3_1N/2P

1

AUX_P/MGPIO4

2

AUX_N/MGPIO5

34

HPD

5

H_DP/DCI_DATA/MGPIO2

6

H_DM/DCI_CLK/MGPIO3

31

SM_SDA/GPIO6

32

SM_SCL/GPIO5

33

SM_INT/GPIO4

24

REXT

47

E-PAD

SYMBO L

PD+MUX

2

Q32A

TYPEC@

+3VALW

5

TYPEC@

DB_CFG

C_TX2_1P/2N C_TX2_1N/2P

C_RX2_1P/2N C_RX2_1N/2P

C_TX1_1P/2N C_TX1_1N/2P

C_RX1_1P/2N C_RX1_1N/2P

SBU1/MGPIO6 SBU2/MGPIO7

C_DP/BB_DP

C_DM/BB_DM

I2C_SCL/GPIO7 I2C_SDA/GPIO8

I2C_INT/GPIO9

I2C_EN/GPIO10

MGPIO8/

IMON

MGPIO9/

VMON

LOC_PWR_MON

61

R3171 0_0402_5%

3

4

20

9

CC1

11

CC2

15 14

19 18

13 12

17 16

3 4

7 8

30 29 28 27

22 21 23

VBUS Discharge

+VBUS_5455

12

R168 100_2010_1%

12

@

13

D

2

G

S

Q9

@

IRLML2030TRPBF_SOT23-3

SB00001J300

A A

VBUS_DSCHG

R173

100K_0402_5%

@

Close to USB typeC(JTYPEC2)

5

4

PD VIN 3.3V LDO

+LDO_VIN

12

R150

1 2

TYPEC@

Q32B L2N7002DW1T1G 2N SC88-6

TYPEC@

Dead battery function Cfig. pin. Tie to GND to disable dead battery ‘ Rd’ . Floating to enable dead battery ‘ Rd’

DB_CFG

PD_CC1 PD_CC2

ISP Channel via CCs

USB3_DP_MTX_DRX_P2 USB3_DP_MTX_DRX_N2

USB3_DP_MRX_DTX_P2 USB3_DP_MRX_DTX_N2

USB3_DP_MTX_DRX_P1 USB3_DP_MTX_DRX_N1

USB3_DP_MRX_DTX_P1 USB3_DP_MRX_DTX_N1

AUX_SBU1 AUX_SBU2

VBUS_EN_5455

U22 TYPEC@

VIN1VOUT

2

GND

3

EN

AP2204K-3.3TRG1_SOT23-5

0.1U_0402_50V7K C162

TYPEC@

1

2

ME2301DC-G_SOT23-3

1 3

@

1 2

R157 0_0402_5%

TYPEC@

1 2

C168 220P_0402_25V8J

1 2

C169 220P_0402_25V8J

C172 0.22U_0402_16V7K C174 0.22U_0402_16V7K

C179 0.22U_0402_16V7K C181 0.22U_0402_16V7K

VBUS_DSCHG

SNK_PS_EN

FRS_5455

GPIO9

OCP_DET_5455

VMON_5455

LOC_PWR_MON

Q33

D

2 12

TYPEC@

AUX_SBU1 [41] AUX_SBU2 [41]

SNK_PS_EN [50]

ADJ/NC

TYPEC@

S

G

R3172 100_0402_5%

TYPEC@

PD_CC1 [41] PD_CC2 [41]

TYPEC@

3

12 12

AUX_SBU1

AUX_SBU2

5

4

+3.3V_IN_5455

R163

1M_0402_5%

10U_0402_6.3V6M

TYPEC@

1

2

12

R3173 200K_0402_1%

TYPEC@

USB3_DP_MTX_C_DRX_P2 USB3_DP_MTX_C_DRX_N2

USB3_DP_MTX_C_DRX_P1 USB3_DP_MTX_C_DRX_N1

ISP Channel via USB Billboard

12

R165 1M_0402_5%

@

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C165

TYPEC@

Issued Date

1

2

10U_0402_6.3V6M

C166

47K_0402_5%

100K_0402_5%

USB3_DP_MTX_C_DRX_P2 [41] USB3_DP_MTX_C_DRX_N2 [41]

USB3_DP_MRX_DTX_P2 [41] USB3_DP_MRX_DTX_N2 [41]

USB3_DP_MTX_C_DRX_P1 [41] USB3_DP_MTX_C_DRX_N1 [41]

USB3_DP_MRX_DTX_P1 [41] USB3_DP_MRX_DTX_N1 [41]

+VBUS_5455

12

R169 200K_0402_1%

TYPEC@

VMON_5455

12

R172 10K_0402_1%

TYPEC@

2014/05/19 2015/12/31

+5VALW

TYPEC@

1 2

R3175

0_0603_5%

R245

R244

+5VALW

12

@

12

@

TYPEC@

VBUS_EN_5455 VLIM_1114

12

R3176

100K_0402_5%

TYPEC@

+LDO_3V3_5455 +5VALW

R221

10K_0402_5%

R222 10K_0402_5%

TYPEC@

0314_Add Connect 'LOC_PWR' net to local power for F/W to decide if C port can become provider via PR_SWAP. Leave floating if no local power exists in the system or in the application that 545x can only be powered on by local power.

Compal Secret Data

Deciphered Date

2

1

2

12

@

12

C159

10U_0603_6.3V6M

FRS_5455FRS_5455

VBUS_DSCHG

0.1U_0402_50V7K

TYPEC@

1

2

LOC_PWR_MON

C533

U15

TYPEC@

1

IN

2

EN

3

FRS

6

DISC1

DV/DT

7

DISC2

IMON

5

VREG

FAULTB

4

GND

DPS1113FIA-13_QFN18_4X4

12

R224 590K_0402_1%

TYPEC@ SD034590380

R223 10K_0402_5%

TYPEC@

1 2

+VBUS_5455

C532

10U_0603_25V6M

2

TYPEC@

1

13

OUT

12

VLIM

ILIM_1113

11

ILIM

10

IMON_1113

9

OCP_DET_5455

8

14

SRC

Title

Size

Custom

Date: Sheet of

C535 100P_0402_25V8K

C534 1000P_0402_50V7K

12

TYPEC@

1

R3180

100K_0402_5%

TYPEC@

Compal Electronics, Inc.

Type-C_RTS5455

Document Number Re v

LA-E521P

1

2

1

OCP_DET_5455

12

TYPEC@

R3177 27K_0402_5%

TYPEC@

+3.3V_IN_5455

12

40 63Thursday, June 15, 2017

R3179 10K_0402_5%

TYPEC@

R3178

54.9K_0402_1%

TYPEC@

0.1

Vinaﬁx.com

5

+VBUS_5455_CONN +VBUS_5455_CONN

JUSBC1

A1

USB3_DP_MTX_C_DRX_P1[40]

USB3_DP_MTX_C_DRX_N1[40]

D D

USB3_DP_MRX_DTX_N2[40] USB3_DP_MRX_DTX_P2[40]

C C

+LDO_3V3_5455

USB3_DP_MTX_C_DRX_P1 USB3_DP_MTX_C_DRX_N1

1 2

C188 0.47U_0402_25V6K

TYPEC@

PD_CC1_CONN

USB20_P4_L USB20_N4_L

AUX_SBU1_CONN

1 2

C190 0.47U_0402_25V6K

TYPEC@

USB3_DP_MRX_DTX_N2 USB3_DP_MRX_DTX_P2

TYPEC@

PD_CC1

PD_CC2

AUX_SBU1

AUX_SBU2

PD_CC1[40]

PD_CC2[40]

AUX_SBU1[40]

AUX_SBU2[40]

1

C193

0.1U_0201_6.3V6K

2

TYPEC@

12

R174

12

10K_0201_5%

C1920.1U_0402_50V7K

GND

A2

SSTXP1

A3

SSTXN1

A4

VBUS

A5

CC1

A6

DP1

A7

DN1

A8

SBU1

A9

VBUS

A10 A11

A12

1 3 5

Type-C Connector PN TMP DC231703291

U64

12

CC1

11

CC2

15

SBU1

14

SBU2

3

VBIAS

10

VPWR

9

FLT

TOP

SSRXN2 SSRXP2

GND

GND GND GND

DRAPH_UB11126-A5A0B-1H

Bottom

TYPEC@

RPD_G1

RPD_G2

C_CC1

TPD8S300

C_CC2

C_SBU1

C_SBU2

TPD8S300_QFN20_3X3

GND1 GND2 GND3

PAD

D1

D2

D3

D4

GND

SSRXP1 SSRXN1

VBUS

SBU2

VBUS

SSTXN2 SSTXP2

GND

GND GND GND

ME@

DN2 DP2

CC2

7

6

4

5

1

2

20

19

17

16

18 8 13 21

4

B12

B11 B10

B9

B8

B7 B6

B5

B4

B3 B2

B1

2 4 6

AUX_SBU1_CONN

AUX_SBU2_CONN

PD_CC1_CONN

PD_CC2_CONN

USB3_DP_MRX_DTX_P1 USB3_DP_MRX_DTX_N1

1 2

C189 0.47U_0402_25V6K

AUX_SBU2_CONN

USB20_N4_L USB20_P4_L

PD_CC2_CONN

1 2

C191 0.47U_0402_25V6K

USB3_DP_MTX_C_DRX_N2 USB3_DP_MTX_C_DRX_P2

USB3_DP_MRX_DTX_P1 [40] USB3_DP_MRX_DTX_N1 [40]

TYPEC@

USB3_DP_MTX_C_DRX_N2 [40] USB3_DP_MTX_C_DRX_P2 [40]

+VBUS_5455_CONN

2

3

D25 PESD24VS2UT_SOT23-3

ESD@

1

3

USB20_P4[12]

USB20_N4[12]

USB20_P4 USB20_P4_L

USB20_N4

USB3_DP_MTX_C_DRX_P1 USB3_DP_MTX_C_DRX_P1

USB3_DP_MTX_C_DRX_N1 USB3_DP_MTX_C_DRX_N1

USB3_DP_MRX_DTX_N2 USB3_DP_MRX_DTX_N2

USB3_DP_MRX_DTX_P2 USB3_DP_MRX_DTX_P2

USB3_DP_MRX_DTX_P1 USB3_DP_MRX_DTX_P1

USB3_DP_MRX_DTX_N1 USB3_DP_MRX_DTX_N1

USB3_DP_MTX_C_DRX_N2 USB3_DP_MTX_C_DRX_N2

USB3_DP_MTX_C_DRX_P2 USB3_DP_MTX_C_DRX_P2

+5VALW

EXC24CG900U_4P

4

1

L5

ESD for USBC1 Lines and Control lines

4

5

6

L30ESDL5V0C6-4_SOT23-6

3

2

EMI@

D44

ESD@

1

2

4

5

3

1

2

4

5

3

D45

10

1

9

2

7

4

6

5

3

8

L05ESDL5V0NA-4_SLP2510P8-10-9

SC300003Z00

D46

ESD@

10

1

9

2

7

4

6

5

3

8

L05ESDL5V0NA-4_SLP2510P8-10-9

SC300003Z00

ESD@

4

GND

Vbus

6

SC300004W00

2

USB20_N4_L

9

8

7

6

9

8

7

6

3

0612 change

2

USB20_P4_LUSB20_N4_L

1

B B

A A

5

PD_CC1

PD_CC2

AUX_SBU1

AUX_SBU2

PD_CC1 PD_CC2

R3192 0_0201_5%@ESD@

R3193 0_0201_5%@ESD@

R3194 0_0201_5%@ESD@

R3195 0_0201_5%@ESD@

2

3

1

1 2

D50

ESD@

PESD5V0U2BT_SOT23-3

AUX_SBU1 AUX_SBU2

PD_CC1_CONN

PD_CC2_CONN

AUX_SBU1_CONN

AUX_SBU2_CONN

3

4

2

D51

ESD@

PESD5V0U2BT_SOT23-3

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/08 2015/07/08

Compal Secret Data

Deciphered Date

2

Title

Type-C_RTS5455_CONN

Size

Document Number Rev

C

Date: Sheet o f

1

41 63Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

4

3

2

1

+5VALW

1 2

R176 0_0603_5%

D D

CC1_5441 CC2_5441

1

C198 220P_0402_25V8J

2

USB3_MRX_DTX_P1[43] USB3_MRX_DTX_N0[43] USB3_MRX_DTX_P0[43]

USB3_RX_N3[12] USB3_RX_P3[12] USB3_TX_N3[12]

USB3_TX_P3[12] USB3_MTX_C_DRX_N0[43] USB3_MTX_C_DRX_P0[43] USB3_MTX_C_DRX_P1[43] USB3_MTX_C_DRX_N1[43]

C C

USB3_MRX_DTX_P1 USB3_MRX_DTX_N0 USB3_MRX_DTX_P0

USB3_TX_N3 USB3_TX_P3 USB3_MTX_C_DRX_N0 USB3_MTX_C_DRX_P0 USB3_MTX_C_DRX_P1 USB3_MTX_C_DRX_N1 CC1_5441

+LDO_3V3_5441 +LDO_3V3_5441

+VCON_IN_5441 +5VALW +5V_IN_5441

1 2

R177 0_0603_5%

1

C199 220P_0402_25V8J

2

1 2

C202 0.1U_0201_10V6K

1 2

C204 0.1U_0201_10V6K

1 2

C203 0.1U_0201_10V6K

1 2

C205 0.1U_0201_10V6K

1 2

C206 0.1U_0201_10V6K

1 2

C207 0.1U_0201_10V6K

1 2

C208 0.1U_0201_10V6K

1 2

C209 0.1U_0201_10V6K

0.1U_0201_10V K X5R

USB3_RX_N3_CUSB3_RX_N3 USB3_RX_P3_CUSB3_RX_P3 USB3_TX_N3_C USB3_TX_P3_C USB3_MTX_DRX_N0 USB3_MTX_DRX_P0 USB3_MTX_DRX_P1 USB3_MTX_DRX_N1

1

C196

2

U18

1

C_RX2_1N/2P

2

C_RX1_1P/2N

3

C_RX1_1N/2P

4

SSRX_1P/2N

5

SSRX_1N/2P

6

SSTX_1P/2N

7

SSTX_1N/2P

8

C_TX1_1P/2N

9

C_TX1_1N/2P

10

C_TX2_1N/2P

11

C_TX2_1P/2N

12

CC1

Change to RTS5448 for Customer request Pin to Pin with RTS5441 0419 B

13

20

19

CC2

5V_IN

VBUS_EN OCP_DET

LDO_3V3

VCON_IN

VMON

REXT

RP_SEL_M1 RP_SEL_M0

C_RX2_1P/2N

GND

RTS5448-GR QFN 24P TYPE-C

+LDO_3V3_5441+VCON_IN_5441

NC

1

C197

4.7U_0603_6.3V6K

2

14 15 16 17 18

21 22 23 24 25

+5V_IN_5441

1

C200 10U_0603_6.3V6M

2

VBUS_EN_5441 OCP_DET_5441

1 2

R178 6.2K_0402_1%

TYPEC_LIMIT_CTL1 TYPEC_LIMIT_CTL0

USB3_MRX_DTX_N1

1

2

CC2_5441

VMON_5441

C201

0.1U_0201_10V K X5R

CC2_5441 [43]

TYPEC_LIMIT_CTL1 [45] TYPEC_LIMIT_CTL0 [45]

USB3_MRX_DTX_N1 [43]CC1_5441[43]

0 0 OFF Mode

R185

10K_0402_5%

R226

4.7K_0402_5%

1 2

12

@

R225

4.7K_0402_5%

1 2

TYPEC_LIMIT_CTL1 TYPEC_LIMIT_CTL0

12

R184

@

10K_0402_5%

Rp configuration

+VBUS_5441

12

R186

5

200K_0402_1%

VMON_5441 VBUS_EN_5441 OCP_DET_5441

12

R189

10K_0402_5%

B B

A A

12

R187

@

10K_0402_5%

12

R190

10K_0402_5%

For C_VBUS power switch enab le pin

+5V_IN_5441+5V_IN_5441

12

R188

10K_0402_5%

12

@

R191

10K_0402_5%

For C_VBUS power switch enab le pin

4

+5VALW

U21

5

IN

OCP_DET_5441 VBUS_EN_5441

C210

10U_0603_6.3V6M

1

@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

OUT

3

FLAG

4

GND

EN(#EN)

G518A1TO1U TSOT-23 5P

SA0000AOU00

Compal Secret Data

Deciphered Date

2

+VBUS_5441

C529

22U_0603_6.3V6M

C211

0.1U_0603_16V7K

2

1

2

1

Compal Electronics, Inc.

Title

Type-C_RTS5441

Size

Document Number Re v

Custom

LA-C581P

Date: Sheet of

1

0.5

42 63Thursday, June 15, 2017

0.5

Vinaﬁx.com

5

+VBUS_5441 +VBUS_5441

JUSBC2

D D

C C

B B

USB3_MTX_C_DRX_P0[42] USB3_MTX_C_DRX_N0[42]

USB3_MRX_DTX_N1[42] USB3_MRX_DTX_P1[42]

ESD Diode structure should be located as close as possible to connector

CC1_5441[42]

CC2_5441[42]

+LDO_3V3_5441

1

C506

0.1U_0201_6.3V6K

2

USB3_MTX_C_DRX_P0 USB3_MTX_C_DRX_N0

1 2

C213 0.47U_0402_25V6K

C215 0.47U_0402_25V6K

1 2

CC1_5441

CC2_5441

CC1_5441_CONN

USB20_P3_L USB20_N3_L

USB3_MRX_DTX_N1 USB3_MRX_DTX_P1

12

R3158

12

10K_0201_5%

C5070.1U_0402_50V7K

A1

GND

A2

SSTXP1

A3

SSTXN1

A4

VBUS

A5

CC1

A6

DP1

A7

DN1

A8

SBU1

A9

VBUS

A10

SSRXN2

A11

SSRXP2

A12

GND

1

GND

3

GND

5

GND

DRAPH_UB11126-A5A0B-1H

Type-C Connector PN TMP DC231703291

U65

12

CC1

11

CC2

15

SBU1

14

SBU2

3

VBIAS

10

VPWR

9

FLT

TPD8S300_QFN20_3X3

TPD8S300

TOP

RPD_G1

RPD_G2

C_CC1

C_CC2

C_SBU1

C_SBU2

GND1 GND2 GND3

ME@

Bottom

D1

D2

D3

D4

PAD

SSRXP1

SSRXN1

VBUS

SBU2

VBUS

SSTXN2 SSTXP2

7

6

4

5

1

2

20

19

17

16

18 8 13 21

4

B12

GND

B11 B10

B9

B8

B7

DN2

B6

DP2

B5

CC2

B4

B3 B2

B1

GND

2

GND

4

GND

6

GND

CC1_5441_CONN

CC2_5441_CONN

USB3_MRX_DTX_P0 USB3_MRX_DTX_N0

1 2

C214 0.47U_0402_25V6K

USB20_N3_L USB20_P3_L

CC2_5441_CONN

1 2

C216 0.47U_0402_25V6K

USB3_MTX_C_DRX_N1 USB3_MTX_C_DRX_P1

+VBUS_5441

3

1

2

USB3_MRX_DTX_P0 [42] USB3_MRX_DTX_N0 [42]

USB3_MTX_C_DRX_N1 [42] USB3_MTX_C_DRX_P1 [42]

D32

ESD@

PESD5V0U2BT_SOT23-3

CC1_5441_CONN CC2_5441_CONN

3

2

3

D33

ESD@

PESD5V0U2BT_SOT23-3

1

2

L7

USB20_P3[12]

USB20_N3[12]

USB20_P3 USB20_P3_L

USB20_N3

USB3_MTX_C_DRX_P0

USB3_MTX_C_DRX_N0

USB3_MRX_DTX_N1 USB3_MRX_DTX_N1

USB3_MRX_DTX_P1 USB3_MRX_DTX_P1

USB3_MRX_DTX_P0 USB3_MRX_DTX_P0

USB3_MRX_DTX_N0 USB3_MRX_DTX_N0

USB3_MTX_C_DRX_N1 USB3_MTX_C_DRX_N1

ESD for USBC2 Lines and Control lines

+VBUS_5441

USB20_P3_L

EMI@

1

4

EXC24CG900U_4P

D47

1

2

4

5

3

8

L05ESDL5V0NA-4_SLP2510P8-10-9

SC300003Z00

1

2

4

5

3

4

5

6

L30ESDL5V0C6-4_SOT23-6

2

3

ESD@

9

10

8

9

7

6

D48

ESD@

9

10

1

2

4

5

3

8

L05ESDL5V0NA-4_SLP2510P8-10-9

SC300003Z00

D49

4

Vbus

6

SC300004W00

8

9

7

6

ESD@

GND

USB20_N3_L

USB3_MTX_C_DRX_P0

USB3_MTX_C_DRX_N0

USB3_MTX_C_DRX_P1USB3_MTX_C_DRX_P1

3

0612 change

2

USB20_N3_L

1

0614 add

CC1_5441

CC2_5441

A A

5

1 2

R3196 0_0201_5%@ESD@

1 2

R3197 0_0201_5%@ESD@

CC1_5441_CONN

CC2_5441_CONN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Type-C_RTS5441_CONN

Size

Document Number Rev

C

LA-C581P

Date: Sheet o f

1

43 63Thursday, June 15, 2017

0.5

Vinaﬁx.com

A

0.1U_0201_10V6K

SUSP#[13,45,54,63]

1 1

0.1U_0201_10V6K

C220

C226

B

+3VALW

10U_0603_6.3V6M

1

2

R3174 0_0402_5%

+5VALW

10U_0603_6.3V6M

1

2

C221

1

@

2

1 2

C227

1

@

2

+5VALW

F>,34AF>,

C515

0.1U_0402_10V6K

1

@

2

U19

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

EM5209VF_DFN14_2X3

VOUT1 VOUT1

VOUT2 VOUT2

GPAD

14 13

12

CT1

11

GND

10

CT2

9 8

15

F,34AF,

C

+3VALW_3VS

1 2

470P_0402_50V7K

1 2

220P_0402_50V7K

+5VALW_5VS

C223

C225

J4

2

JUMP_43X79

J5

2

JUMP_43X79

D

+3VS

112

10U_0603_6.3V6M

0.1U_0201_10V6K

C222

1

C224

@

2

+5VS

112

10U_0603_6.3V6M

0.1U_0201_10V6K

C228

1

C229

@

2

6.8P_0402_50V8B

10P_0402_25V8J

R194 470_0603_5%@

1

C492

@RF@

2

1

C493

@RF@

2

1 2

13

D

Q11

S

2N7002H_SOT23-3

2

SUSP

G

@

E

- K&

+5VS

0.1U_0402_10V6K

0.1U_0402_10V6K C509

C508

1

2

@RF@

2

+5VS

0.1U_0402_10V6K

0.1U_0402_10V6K C511

C510

1

2

@RF@

2

+3VS

+5VS

0.1U_0402_10V6K

C512

1

@RF@

2

0.1U_0402_10V6K

C513

1

2

C514

1

@RF@

2

2 2

470_0402_5%

SUSP

R196

Q13

2

G

+0.6VS

12

13

D

S

@

2N7002H_SOT23-3

+5VS

12

R195

Q12

2

G

@

13

D

@

S

2N7002H_SOT23-3

100K_0402_5%

SUSP

SUSP#

3 3

+5VALW

+3VS

C540

HDA_RST#[9]

HDA_BIT_CLK[9]

HDA_SYNC[9]

1 2

10P_0402_25V8J

C541

1 2

ME_EN[9,45]

10P_0402_25V8J

C542

1 2

10P_0402_25V8J

C543

1 2

10P_0402_25V8J

+VCCGT +5VS

@RF@

1

@RF@

C544 2P_0201_25V8B

2

+5VALW

+3VALW+1.0VALW

1

@RF@

C545 2P_0201_25V8B

2

+5VALW

@

R197 220K_0402_5%

SYSON#

DRC2124E0L NPN MINI3-G3-B

SYSON[13,45,54] DGPU_PWR_EN# [23]

1 2

Q14

@

1

OUT

2

IN

GND

3

+1.35VS_VRAM

12

R198 470_0603_5%

@

13

D

S

DGPU_PWR_EN#

2

G

Q15 2N7002H_SOT23-3

@

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size

C

Date: Sheet o f

Compal Electronics, Inc.

DC Interface

Document Number Rev

DC Interface

LA-D562P

E

44 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

+3VLP

+3VALW

:

+3VLP

L8

FBMA-L11-160808-601LMT_2P

1 2

0.1U_0201_10V6K

1 2

L9

FBMA-L11-160808-601LMT_2P

R206

1 2

R207

1 2

R448

1 2

4.7K_0402_5% R449

1 2

4.7K_0402_5%

SOC_SML1CLK[8,22,39,46]

SOC_SML1DATA[8,22,39,46]

C241 100P_0402_50V8J

R210 4.7K_0402_5%@

/!

12

EC_SMB_CK1

2.2K_0402_5%

EC_SMB_DA1

2.2K_0402_5%

EC_SMB_CK2

TYPEC@

EC_SMB_DA2

TYPEC@

SOC_SML1CLK

1 2

R208 1K_0402_5%

1 2

PCH_PWROK

ESD@

C243 100P_0402_50V8J

Thermal Decided

+EC_VCCA +EC_VCCA +EC_VCCA

CUST_TEMP1 CUST_TEMP2 CUST_TEMP3

+3VLP

4

EC_PCIE_WAKE#

VCIN1_AC_IN

+3VS

12

R416

16.5K_0402_1%

12

RTS1 100K +-1% 0402 B25/50 4250K

SL200002H00

1 2

R3168 0_0201_5% NONTYPEC@

1 2

R3169 0_0201_5% NONTYPEC@

+3VS

5

Q31B L2N7002DW1T1G 2N SC88-6

1 2

R215 10K_0402_5%

+EC_VCCA

1

C230

2

ECAGND

@

1 2

R203 330K_0402_5%

C239

0.1U_0402_10V6K

Q31A

TYPEC@

2

L2N7002DW1T1G 2N SC88-6

EC_SMB_CK2

61

3

TYPEC@

EC_SMB_DA2SOC_SML1DATA

EC_FAN_SPEED

Thermal Decided Thermal Decided

1

@

2

KSO[0..15][33]

KSI[0..7][33]

12

DIS@

R417

16.5K_0402_1%

12

RTS2 100K +-1% 0402 B25/50 4250K

EC_CLEAR_CMOS#[10]

USB_CHG_CTL3[34]

USB_CHG_STATUS#[34]

EC_FAN_SPEED[33]

SL200002H00

PD_INT[40] KB_RST#[8]

SERIRQ[8,27]

LPC_FRAME#[8,27]

LPC_AD3[8,27] LPC_AD2[8,27] LPC_AD1[8,27] LPC_AD0[8,27]

CK_LPC_KBC[8]

PCIRST#[10,21,27,31,32,36]

EC_SCI#[6,10]

CLKRUN#[8]

KSO[0..15]

KSI[0..7]

GPU_PROHOT#[22]

EC_SMB_CK1[49,51,65] EC_SMB_DA1[49,51,65] EC_SMB_CK2[40]

EC_SMB_DA2[40]

PM_SLP_S3#[10]

USB_CHG_CTL1[34]

USB_CHG_EN[34]

USB_CHG_CTL2[34]

KB_BL_PWM[33]

EC_TX[31] EC_RX[31]

PCH_PWROK[10]

NOVO#[33] VR_PWRGD[59]

PBTN_OUT#[10]

PM_SLP_S4#[10,54]

C233

0.1U_0201_10V6K

1

2

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

EC_RST# EC_SCI#

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

EC_SMB_CK1 EC_SMB_DA1

T219 TP@

EC_TX EC_RX PCH_PWROK

+3VLP

1 2

R199 0_0402_5%

C234

0.1U_0201_10V6K

1

2

U54

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCII#/GPIO0E

38

GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CK1/GPIO44

78

EC_SMB_DA1/GPIO45

79

EC_SMB_CK2/GPIO46

80

EC_SMB_DA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

GPIO0D

25

EC_INVT_PWM/GPIO11

28

FAN_SPEED1/GPIO14

29

EC_PME#/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

XCLKI/GPIO5D

123

XCLKO/GPIO5E

12

DIS@

R418

12

RTS3 100K +-1% 0402 B25/50 4250K

LPC & MISC

16.5K_0402_1%

DIS@

SL200002H00

Int. K/B

Matrix

SM Bus

+3VLP_EC

+EC_VCCA

9

22

33

96

111

125

EC_VDD0

EC_VDD/VCC

PWM Output

AD Input

DA Output

PS2 Interface

CPU1.5V_S3_GATE/GPXIOA00

SPI Device Interface

SPI Flash ROM

GPIO

H_PROCHOT#_EC/GPXIOA06

GPO

GPIO

GPI

GND/GND

GND0

11

24

35

94

113

67

21

GPIO0F

23

V18R

BEEP#

26 27

VCIN1_BATT_TEMP

63 64 65 66 75 76

68 70 71 72

83 84 85 86 87 88

97 98 99 109

119 120 126 128

73 74 89 90 91 92 93 95 121 127

100 101 102 103 104 105

BKOFF#

106 107 108

AC_IN

110

EC_ON

112 114

LID_SW#

115 116

SUSP#

117 118

PECI

124

+V18R

CUST_TEMP3

CUST_TEMP2

CUST_TEMP1

SYSON

C245

4.7U_0603_6.3V6K

BEEP#/GPIO10

EC_VDD/AVCC

GPIO12

ACOFF/GPIO13

BATT_TEMP/AD0/GPIO38

AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B AD4/GPIO42

IMON/AD5/GPIO43

DAC_BRIG/GPIO3C EN_DFAN1/GPIO3D

IREF/GPIO3E

CHGVADJ/GPIO3F

EC_MUTE#/GPIO4A

USB_EN#/GPIO4B CAP_INT#/GPIO4C

EAPD/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

WOL_EN/GPXIOA01

ME_EN/GPXIOA02

VCIN0_PH/GPXIOD00

SPIDI/GPIO5B

SPIDO/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A

ENBKL/AD6/GPIO40

PECI_KB930/AD7/GPIO41

FSTCHG/GPIO50

BATT_CHG_LED#/GPIO52

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

BATT_LOW_LED#/GPIO55

SYSON/GPIO56 VR_ON/GPIO57

PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04

PROCHOT_IN/GPXIOA05

VCOUT0_PH/GPXIOA07

BKOFF#/GPXIOA08

PBTN_OUT#/GPXIOA09

PCH_APWROK/GPXIOA10

SA_PGOOD/GPXIOA11

AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF/GPXIOD03

LID_SW#/GPXIOD04

SUSP#/GPXIOD05

GPXIOD06

PECI_KB9012/GPXIOD07

AGND/AGND

KB9022QA_LQFP128_14X14

69

ECAGND

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VCCST_PWRGD [10] BEEP# [35] EC_FAN_PWM [33]

T220TP@

VCIN1_BATT_TEMP [49] VCIN1_BATT_DROP [52] ADP_I [51]

ADP_ID [48]

CMOS_ON# [28] TP_DISABLE# [33]

DGPU_PWR_EN [11,23,57,58]

USB_EN# [34,46]

ACC_INT [46] BATT_SWITCH# [65] DCIN_LED# [33] AC_IN_TYPE [51] USB_CHG_ILIM_SEL [34]

T214TP@

ENBKL [6]

SYS_PWROK [10] ME_EN [9,44] VCIN0_PH1 [49]

EC_SPI_MISO [8] EC_SPI_MOSI [8] EC_SPI_CLK [8] EC_SPI_CS0# [8]

BATT_TEMP_S [65]KB_DEL#[33]

EC_MUTE# [35] BATT_CHG_LED# [33]

CAPS_LED# [33] PWR_LED# [33]

BATT_LOW_LED# [33]

SYSON [13,44,54]

VR_ON [59]

AC_PRESENT_R [10]

EC_RSMRST# [10] 3V/5VALW_PG [34,40,52,53,55]

AC_OFF [48] VCOUT1_PROCHOT# [51,64] VCOUT0_MAIN_PWR_ON [53]

BKOFF# [28]

TYPEC_LIMIT_CTL1 [42] TYPEC_LIMIT_CTL0 [42]

EC_PCIE_WAKE# [31,36]

1 2

R213 0_0402_5%

EC_ON [53]

ON/OFF# [33]

LID_SW# [33]

SUSP# [13,44,54,63]

5VLDO_EN [52]

1 2

R217 0_0402_5%

1

2

Compal Secret Data

2014/09/01 2015/09/01

Compal Secret Data

VCIN1_AC_IN

1 2

R214 43_0402_1%

+3VLP

Deciphered Date

VCOUT1_PROCHOT#

VR_HOT#[59]

VCIN1_AC_IN [51,64]

USB_EN#

KB_DEL#

PD_INT

VCIN1_BATT_TEMP

1 2

R200 10K_0402_5%

1 2

R466 10K_0402_5%

1 2

R450 4.7K_0402_5%

TYPEC@

1 2

C238 100P_0402_50V8J

/!

VCCST_PWRGD

SYSON

1 2

R211 0_0402_5%

1 2

R212 0_0402_5%

SUSP#

H_PECI [6]

1 2

Title

Size

Document Number Rev

C

Date: Sheet o f

1 2

C240 100P_0402_50V8J

ESD@

12

R209

@

100K_0402_5%

R443 100K_0402_5%@

Compal Electronics, Inc.

EC_NPCE388N

/!

1

2

1

@

C244 47P_0402_50V8J

2

LA-D562P

+5VALW

+3VS

+3VLP

C242

0.1U_0201_10V6K

@ESD@

H_PROCHOT# [6]

45 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

APS G-Sensor

+3VS

4

3

2

1

Kionix KX023-1025

Address

R/W

3Fh/ 3Eh

3Dh/ 3Ch

+3VS

SDO/ADDR

VDD

VSS

C395

D D

2nd Battery USB2_CONN

C C

W=80mil s W=80mi ls

+5VALW +5V_U2

5A-

USB_EN#[34,45]

USB20_P9[12]

USB20_N9[12]

B B

USB_EN#

U63

5

IN

4

EN

SY6288D20AAC_SOT23-5

2

C486

0.1U_0201_10V K X5R

1

BATT2@

L12

1

4

EXC24CG900U_4P

BATT2@

OUT

GND

OCB

EMI@

R408 0_0402_5%

@

1 2

R409 0_0402_5%

APS@

1 2

1

2

3

USB20_P9_L

2

3

USB20_N9_L

3

R462 0_0402_5%

1 2

BATT2@

SOC_SML1CLK[8,22,39,45] SOC_SML1DATA[8,22,39,45]

/!

D42

USB20_N9_L

+5V_U2

4

5

ESD@

USB20_P9_L

3

4

Vbus

3

2

GND

APS@

USB_OC2# [12]

1 2

0.1U_0201_10V6K

SOC_SML1CLK SOC_SML1DATA ACC2_SA0

USB20_N9_L USB20_P9_L

1

U58

APS@

8

NCS

4

SCLK/SCL SDI/SDA SDO/ADDR

NC5 NC4 NC3 NC1 NC2

IO VDD

GND2

GND1

KX023-1025_LGA16_3X3

5

12

1

+

C488

BATT2@

150U_B2_6.3VM_R35M

2

16 15 10

6 7

2 3

+5V_U2

0413

USB2.0 Connector PN DC23300H300

14

VDD

11

INT1

9

INT2

13

TRIG

JUSB3

ME@

1

VBUS

2

D-

3

D+

4

GND

5

GND

6

GND

7

GND

8

GND

PS_608013-004221

APS@

C396

1 2

ACC_INT ACC_INT2

1

C487 470P_0402_50V7K

2

0.1U_0201_10V6K

@

C397

1 2

@

10U_0603_6.3V6M

ACC_INT [45]

T205TP@

6

L30ESDL5V0C6-4_SOT23-6

A A

5

SC300004W00

1

Title

<Title>

Size

Document Number Re v

Document Number Re v <Doc> <RevCode>

C

C

C

Date: Sheet o f

4

3

2

Date: Sheet o f

1

46 66Thursday, June 15, 2017

Vinaﬁx.com

5

DRVON

ISL95808HRZ-T

PU1152

DRVON

CSD97396Q4M

PU1101

DRVON

CSD97396Q4M

PU1102

DRVON

CSD97396Q4M

PGOOD

S3：DDR_VTT_PG_ CTRL

S5 ：SYS ON

PU1151

ISL62771HRTZ-T

PU801

SY8286RAC

PU901

SY8288RAC

PU602

SY8210AQVC

PU501

D D

ADAPTER

DGPU_MAIN_EN

CHARGER

B+

5100mA

21000mA

18000mA

28000mA

3840mA

PJ902

10000mA

1000mA

8000mA

U42@

U23@

BATTERY

5V_3V_EN

SY8288CRAC

PU402

C C

ENLDO_3V5V

SY8288CRAC

PU402

ENLDO_3V5V

SY8286BRAC

PU401

5V_3V_EN

SY8286BRAC

PU401

1500mA

+LEDVDD

R10

B B

A A

5

11800mA

100mA

5000mA

+VCCSA

+VCCCORE

+VCCGT

+VGA_CORE

1.35VS_VRAM

+1VALWP

PJ604

+0.6VSP

PJ504

+1.2VP

PJ503

PJ405

+5VALWP

PJ407

+5VLP

PJ406

+3VL

PJ404

+3VALWP

PJ403

4

UC1

(AOU)

RC73

RC74

UC1

J5

1100mA

3000mA

1100mA

100mA

R148

PD2

25mA

611mA

5000mA

J4

1916mA

RV42

3140mA

RC71

240mA

5000mA

2000mA

+3.3V_IN_5455

+RTCBATT

+3VGS

+1.8VALWP

+PCIE_VGS

+1.0VS_VCCIO

+1.0V_VCCST

1916mA

DGPU_PWR_EN

3140mA

SUSP#

240mA

SYSON

2574mA

2124mA

2130mA

2000mA

6000mA

SUSP#

USB_CHG_EN

Q28

USB_EN#

VBUS_EN_5455

VBUS_EN_5441

USB_EN#

UV1

10000mA

1000mA

8000mA

11800mA

+1.0VALW

+0.6VS

+1.2V

+5VALW

R147

100mA 100mA

+5VL

+3VALW

PR10

PR8

D15

1000mA

R103

DGPU_PWR_EN

25mA

3V/5VALW_PG

611mA

SUSP#

5000mA

100mA 100mA 100mA 100mA

+3VLP

5000mA

EM5209VF UV10

TPS22961DNY UC13

EM5209VF UC12 UC1

+1.0V_PRIM_CORE

+1.0V_MPHYGT

+1.0VALW

+1.2V

JDIMM2,U2~U5

EM5209VF

5000mA

U19

PI5USB2546ZHEX

2000mA

SY6288D20AAC

500mA

1100mA

3000mA

1100mA

(Non-AOU)

U55

NX5P3290U K U15

NX5P3090U K U21

SY6288D20AAC U56

+VCON_IN_5455

AP2204K U22

+CHGRTC

+3V_LAN

ME2301DC-G QV2

RT9059GQW PU601

EM5209VF U19

+3VS

4

3

UV1

+5V_CHGUSB

MB-TYPE_A (U12)

+VBUS_5455

MB-TYPE_C (U15)

+VBUS_5441

MB-TYPE_C (U21)

+5V_USB

SB-TYPE_A(U56)

RC81

UV1

600mA

PJ603

500mA

R447

285mA

R65

1850mA

J1

25mA

R5

500mA

R43

200mA

R98

200mA

R101

200mA

R102

200mA

R137

200mA

R138

PCH_ENVDD

1500mA

CMOS_ON#

500mA

3

+3VL_RTC

+5VS

+3VS_FP

TP_VCC

+3VS_NGFF

+3VS_TPM

+3VS_WLAN

+IOVDD_CODEC

+AVDD_CODEC

+3VDD_CODEC

+3VS_AVCC

+3VS_VDD

G524B1T11U U59

LP2301ALT1G

Q30

1500mA

500mA

U9

2000mA

R227

500mA

R72U12

1000mA

R81

1000mA

Q6

+1.8VALW

Audio

CRT

+5V_DSP

+5VS_HDD

+FAN

+5VS_AVDD

+VCC_KB_L ED

DGPU_PWR_EN

+LCDVDD_CO NN

+3VS_CMOS

311mA

2

EM5209VF UV50

311mA

RV41

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

+1.8VGS

UV1

Compal Secret Data

2014/08/21 2015/08/21

Deciphered Date

1

Compal Electronics, Inc.

Title

Power Rail

Size

Document Number R ev

D

430!E

Date: Sh eet of

1

47 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

4

3

2

1

PL1

EMI@

5A_Z120_25M_0805_2P

PC2

100P_0402_50V8J

EMI@

1 2

PL2

EMI@

5A_Z120_25M_0805_2P

1 2

AC_OFF[45]

ADP_ID [45]

@Conn@

JDCIN1

1

1 2 3 4 5

GND GND

D D

ACES_50299-00501-003

+3VALW

C C

ADPIN

2 3 4 5

6 7

PR4

1 2

750_0402_1%

PF1

7A_32VDC_0437007.WRML

21

12

PC7

.1U_0402_16V7K

12

PC1

1000P_0402_50V7K

EMI@

12

PC8

680P_0603_50V7K

@EMI@

12

PC3

EMI@

12

PR7 100K_0402_5%

+19V_VIN+19V_ADPIN

1 2 3

12

PC4

100P_0402_50V8J

1000P_0402_50V7K

EMI@

+19V_VIN

12

PR5 154K_0402_1%

34

PQ2B

5

G

D

2N7002KDW_SOT363-6

S

12

PC9

0.1U_0402_25V6

12

PR6 24K_0402_1%

PQ2A

2

G

12

PR1

200K_0402_5%

12

PR3 100K_0402_5%

61

D

2N7002KDW_SOT363-6

S

AON7401_DFN8-5

4

12

PR2

100_0402_5%

PQ1

5

PC6

1 2

5600P_0402_25V7K

12

PC5

0.01U_0402_25V7K

PD1

2

3

1

SDT8A100P5-13D_POWERDI5-3

VIN_MUX

BOM Structure Table

BOM StructureIte m

For U23e U23@ For U42 U42@ For DIS

B B

For DIS of EMI VGA_EMI@ For U23e of EMI U23_EMI@ For U42 of EMI U42_EMI@ For RF

+CHGRTC

PR8

PR9

45.3K_0603_1%

1 2

1.5K_0603_5%

S SCH DIO BAS40CW SOT-323

+RTCBATT

A A

PD2

2

1

3

PR10

1 2

1K_0603_5%

@Conn@

JRTC1

1 2 3 4

CVILU_CI4402M1HRT-NH

12

1 2 G1 G2

+3VLP

For DIS of RF For U23e of RF For U42 of RF

U22@For U22

VGA@ PD@Support Type-C PD

EMI@For EMI

RF@ VGA_ RF@ U23_ RF@ U42_ RF@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/03/09 2018/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR-DCIN / Vin Detector

Size

Document Number Re v

Custom

VE

Date : Sheet o f

2

Date : Sheet o f

1

48 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

4

3

2

1

@Conn@

JBATT1

1

2

3

4

GND GND GND GND

4

5

6

7

8

9 10 11 12

D D

DRAPH_WS33081-S3201-1H

C C

EC_SMCA EC_SMDA

12

PR12

PR11

100_0402_1%

M_BATA

PF2

21

15A_32V_0501015.WR

100_0402_1%

EC_SMB_CK1 [45,51,65]

EC_SMB_DA1 [45,51,65]

1 2

PR14 200K_0402_1%

1 2

PR15 10K_0402_5%

M_VMB

EMI@

PL3 5A_Z120_25M_0805_2P

1 2

EMI@

PL4

1 2

5A_Z120_25M_0805_2P

12

PC10

EMI@

1000P_0402_50V7K

+3VLP

VCIN1_BATT_TEMP [45]

12

PC11

0.01U_0402_25V7K

EMI@

M_BATT_IN

PH201 under CPU botten side :

CPU thermal protection at 93 +-3 degree C

Recovery at 56 +-3 degree C

+EC_VCCA

12

PR13

VCIN0_PH1[45]

16.5K_0402_1%

12

PH1 100K +-1% 0402 B25/50 4250K

ECAGND

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/03/09 2018/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR-BATTERY CONN/OTP

Size

Document Number Re v

Custom

VE

Date : Sheet o f

2

Date : Sheet o f

1

49 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

4

3

2

1

PQ3

D D

C C

+VBUS_5455_CONN

ON -> SNK_PS_EN: 1 OFF -> SNK_PS_EN: 0

PD@

PF3

5A_32V_0438005.WR

SNK_PS_EN[40]

21

+VBUS_5455

12

PD@

PR19 100K_0402_5%

PD@

PR16

PD@

PQ4

2

AON7401_DFN8-5

1 2 3

12

PR17

200K_0402_5%

PD@

12

PR18 100K_0402_5%

1

3

LSK3541G1ET2L_VMT3

PD@

5

4

12

100_0402_5%

PD@

PC15

1 2

5600P_0402_25V7K

PD@

VGS(th)= 0.8V~1.5 V

PD3

PD@

2

3

PDS5100H-13_POWERDI5-3

1

12

PD@

PC12 10U_0603_25V6M

12

PD@

PC13 10U_0603_25V6M

12

PD@

PC14

0.01U_0402_25V7K

VIN_MUX

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/03/09 2018/06/30

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PWR- TYPE-C

Size

Document Number Rev

C

VE

Date: Sheet o f

1

50 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

A

B

C

D

Module model information

ISL9237_V1.mdd for dual layer

HG2_CHG

AON6994_DFN5X6D-8-7

PL102

2.2UH_PCMB103T-2R2MS_13A_20%

1 2

12

PR116

4.7_1206_5%

@EMI@

SNUB_CHG1

12

PC125

680P_0402_50V7K

@EMI@

LX2_CHG

12

PR117

4.7_1206_5%

@EMI@

SNUB_CHG2

12

PC126

680P_0402_50V7K

@EMI@

LG2_CHG

PQ102

B+

PC110

10U_0603_25V6M

1 2

PC114

10U_0603_25V6M

1 2

PC115

10U_0603_25V6M

1 2

PC116

10U_0603_25V6M

1 2

2

1

D1

G1

7

D2/S1

S24S2

S2

G2

5

3

6

PR111

0.005_1206_1%

1

2

+8.4V_BATT+

4

3

PC121

10U_0603_25V6M

12

PC122

10U_0603_25V6M

1 2 3

BGATE_ISL9238

PQ103 AON7401_DFN8-5

4

12

PC123 4700P_0402_25V7K

5

BATT+

12

PC103

10U_0603_25V6M

PR113

1 2

2.2_0603_5%

1 2

PC124 0.1U_0402_25V6@

PC127 1U_0402_25V6K@

1 2

PR124

1 2

1_0402_1%

1 2

PC131 0.22U_0402_25V6K@

PC104

PR126

12

10U_0603_25V6M

B+

+19V_CHG

12

PC105

10U_0603_25V6M

PC106

10U_0603_25V6M

HG1_CHG

12

PQ101

1

2

AON6962_DFN5X6D-8-7

D1

G1

LX1_CHG

7

D2/S1

S24S2

S23G2

5

6

LG1_CHG

CSOP_CHG_R

CSON_CHG_R

VIN_MUX

1 1

4.12V

12

PR104 392K_0402_1%

>0.8V

ACIN_ISL9238

12

PR106

PC111

2 2

100K_0402_1%

0.1U_0402_25V6

VIN_MUX

VCOUT1_PROCHOT#[45,64]

VDD_ISL9238

12

PR118 100K_0402_1%

VIN_MUX

VCIN1_AC_IN[45,64] AC_IN_TYPE[45]

3 3

12

PR119 200K_0402_1%

+19V_VIN

12

PR105 511K_0402_1%

CMIN_ISL9238

12

PR107

0.1U_0402_25V6

PD101

BAT54CW_SOT323-3

2

3

PR115 0_0402_5%

100K_0402_1%

PR110 2_1206_5%

1 2

1

PC117

1U_0603_25V6

1 2

12

PC119 1U_0402_6.3V6K

5V

1 2

PR112 0_0402_5%

1 2

PR114 0_0402_5%

1 2

VDD_ISL9238

H >0.9V --> Battery remove L <0.4V --> Battery present

12

PR122 100K_0402_5%

12

PR132 200K_0402_1%

6 V～2 3 V

DCIN_ISL9238

VDD_ISL9238

ACIN_ISL9238

CMIN_ISL9238

PROCHOT#_ISL9238

733kHz / 2 Cell

PC130

BATGONE

COMP_ISL9237

12

PR125

12

0.022U_0402_25V7K

PC112

B+

EC_SMB_DA1[45,49,65]

EC_SMB_CK1[45,49,65]

PR102

2.2_0402_1%

PC108

1U_0402_25V6K

17

18

19

20

21

22

23

24

1K_0402_1%

12

PC129

@

DCIN

VDD

ACIN

CMIN

SDA

SCL

PROCHOT#

ACOK

12

560P_0402_50V7K

PR101

1

2

0.01_1206_1%

CSIP_CHG_R

12

PR103

2.2_0402_1%

PC107

CSIP_ISL9237

4.7U_0603_25V6K

1 2

CSIP_ISL9237

CSIN_ISL9237

14

15

16

ADP

CSIP

CSIN

BATGONE

CMOUT26PROG27AMON/BMON29PSYS30VBAT

25

12

PR121

82.5K_0402_1%

12

PR127

1K_0402_1%

12

PC132

ADP_I[45]

4

3

12

13

ASGATE

COMP

28

AMON_ISL9237

0.1U_0402_25V6

CSIN_CHG_R

12

CSIN_ISL9237

PC113

0.22U_0603_25V7K

PR108

2.2_0603_5%

BST1_ISL9237

HG1_CHG

LX1_CHG

11

10

BOOT1

PHASE1

UGATE1

31

PSYS_ISL9237

VBAT1_ISL9237

0.1U_0402_25V6

12

PC109

1U_0402_25V6K

LG1_CHG

PU101

9

33

ISL9538HRTZ-T_TQFN32_4X4

PAD

8

LGATE1

VDDP

7

LGATE2

6

PHASE2

5

UGATE2

4

BOOT2

3

VSYS

2

CSOP

1

CSON

BGATE

32

BGATE_ISL9238

12

PR123

@

I_SYS[59]

PC133

@

1 2

VDDP_ISL9238

LG2_CHG

LX2_CHG

HG2_CHG

BST2_ISL9237

CSOP_ISL9237

CSON_ISL9237

0_0402_5%

12

PR109

4.7_0402_5%

5V

0.22U_0603_25V7K

PR128

1 2

100_0402_5%

12

PC101

0.1U_0402_25V6

@EMI@

VDD_ISL9238

1 2

PC120

1 2

1U_0603_25V6

12

PC102

2200P_0402_25V7K

EMI@

PC118

1U_0402_6.3V6K

PR120

0_0402_5%

1 2

12

PC128

BATT+

Close to EC ADP_I pin

+3VLP

12

PR129 10K_0402_5%

4 4

34

D

PQ104B

PR130 0_0402_5%

1 2

GM[65]

A

12

@

PC134

0.1U_0402_25V6

PQ104A

2

G

61

D

2N7002KDW_SOT363-6

S

5

G

S

12

@

PC135

0.1U_0402_25V6

BATGONE

PR131

0_0402_5%

1 2

B

GS [65]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/03/09 2018/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR- CHARGER

Size

Document Number Rev

Custom

VE

Date: Sheet of

D

51 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

4

3

2

1

Vfb= 2V

PR451

30K_0402_1%

1 2

PR452

20K_0402_1%

1 2

5V_B+

12

PC451

1 2

4.7U_0603_10V6K

PR453

39K_0402_1%

5V_FB1

CS1

PU402

2

1

3

13

0.1U_0603_25V7K

12

PC460

LDO3

LDO5

FB1

BYP1

14

4.7U_0603_10V6K

21

RT6575DGQW(2)_WQFN20_3X3

CS1

GND

20

EN1

19

VCLK

18

PHASE1

17

BOOT1

16

UGATE1

LGATE1

15

LG_5V

+5VALWP

+5VLP

Typ: 175mA Min: 100mA

LX_5V

BST_5V

UG_5V

PR454

2.2_0603_5%

1 2

5V_3V_EN [53]

0.1U_0402_25V6

BST_5V_1

PC456

1 2

PQ451

AON6994_DFN5X6D-8-7

7

2

1

D1

G1

D2/S1

S24S2

S2

G2

5

3

6

+5VLP +5VL

PL402

3.3UH_PIMB104T-3R3MS_10A_20%

LX_5V

1 2

12

RF@

LX_5V_2

4.7_1206_5%

PR406

RF@

12

PC428

680P_0603_50V7K

PJ407

@

112

JUMP_43X118

PJ405

@

112

JUMP_43X118

PJ406

@

JUMP_43X39

112

2

1

+

PC457 220U_6.3V_M

2

Fsw= 300KHz ESR= 18m

+5VALW+5VALWP

+5VALWP

12

PC417

10U_0603_25V6M

@

PR457 10K_0402_5%

PC418

EMI@

PQ453

2

5V_B+

12

2200P_0402_50V7K

PC419

0.1U_0402_25V6

@EMI@

12

1

3

12

5VLDO_EN[45]

LSK3541G1ET2L_VMT3

5V_B+

PR461 100K_0402_5%

Rising 4.6V 4.9V Falling 3.2V 3.7V

PR463

200K_0402_5%

1 2

@

+3VLP

12

1 2

0.1U_0402_25V6

3V/5VALW_PG [34,40,45,53,55]

AO3413_SOT23-3

PC463

2

4

5

FB2

CS2

6

EN2

7

PGOOD

8

PHASE2

9

BOOT2

10

UGATE2

VIN

PQ452

D

S

VIN_3V5V

13

G

2

12

PR462 100K_0402_5%

1

PQ455

3

LSK3541G1ET2L_VMT3

Vout = Vfb*[1+(Rt/Rb)] = 2*[1+(30K/20K)] =5V

+5VA LWP Imax=10.5A,Ipeak=12.4A ;Fsw=300KHz Iocp= (Rcs 1*Itr ip)/ Rdso n Rds : L/S --> typ:2.8mohm ; max: 3.5mohm Itrip=9~11 uA Iocp=16.49A Output Cap. ESR=18mohm Delta IL=[(Vin-Vo)/L]*[(Vout/Vin)*T]=2.04A

LGATE2

12

11

12

PC459

B+

PJ402

@

2

5V_B+

12

10K_0402_1%

112

JUMP_43X118

PJ408

@

112

JUMP_43X118

PR413

47.5K_0402_1%

PR414

2

12

PC431 1000P_0402_25V8J

12

PC416

PC462

PC461

10U_0603_25V6M

VCIN1_BATT_DROP[45]

D D

C C

5.75V

1V

B B

+5VALWP +3VLP +3VLP

PR459 100K_0402_5%

PQ454

2

12

1

3

LSK3541G1ET2L_VMT3

12

PR458 200K_0402_1%

12

PR460

A A

100K_0402_1%

12

PC464

0.1U_0402_25V6

Vth: 0.8V～1.5V

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/03/09 2018/06/30

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PWR- 5VALWP

Size

Document Number Rev

C

VE

Date: Sheet o f

1

52 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

A

B

C

D

E

1 1

B+

PJ401

@

112

JUMP_43X118

3V_B+

2

12

PC405

PC404

0.1U_0402_25V6

@EMI@

PC403

2200P_0402_50V7K

EMI@

12

PC406

10U_0603_25V6M

+3VLP

12

PR403

100K_0402_5%

3V/5VALW_PG[34,40,45,52,55]

2 2

EN1 and EN2 dont't be floating. EN :H>0.8V ; L<0.4V

LX_3V

6

7

8

9

10

ENLDO_3V5V

5V_3V_EN

PU401 SY8286BRAC_QFN20_3X3

5

LX

GND

PG

NC

IN3IN4IN

EN112EN2

FF13OUT14NC

11

3V_FB 3V_FB_1

Fsw : 600K Hz

2

IN

keep short pad, snubber is for EMI only.

PR401

BST_3V

1

BS

GND

LDO

NC

GND

15

3.3V LDO 150mA~300mA

PC414 1000P_0402_25V8J

1 2

0_0402_5%

1 2

20

LX

19

LX

18

17

12

16

21

1K_0402_1%

1 2

BST_3V_R

+3VL

PC412

4.7U_0603_6.3V6M

PR404

PC402

0.1U_0201_10V6K

1 2

LX_3V

RF@

Use 7x7x3 size when the layout space is enough.

PL401

1.5UH_6A_20%_5X5X3_M

1

2

12

PR402

4.7_1206_5%

3V_SN

12

0413

RF Request

PC413

680P_0603_50V7K

4

3

12

PC407

PC408

22U_0603_6.3V6M

Vout is 3.234V~3.366V

TDC= 6A

+3VALWP +3VALW

12

PC409

22U_0603_6.3V6M

+3VL

+3VALWP

12

PC410

22U_0603_6.3V6M

Iocp =8A

PJ403

@

2

112

JUMP_43X118

PJ404

@

JUMP_43X39

2

112

+3VLP

3 3

B+

4 4

PR407

499K_0402_1%

1 2

PR408

150K_0402_1%

VCOUT0_MAIN_PWR_ON[45]

A

ENLDO_3V5V

12

EC_ON[45]

12

PC426 1U_0402_16V6K

PR410 0_0402_5%

1 2

PR409

2.2K_0402_5%

1 2

12

5V_3V_EN

12

PR412

PC430

1M_0402_1%

4.7U_0402_6.3V6M

B

5V_3V_EN [52]

EN1 and EN2 dont't be floating. EN :H>0.8V ; L<0.4V

Fsw : 600K Hz

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/03/09 2018/06/30

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

PWR- 3VALWP

Size

Document Number Re v

Custom

VE

Date : Sheet o f

53 66Thursday, June 15, 2017

E

0.1

Vinaﬁx.com

5

4

3

2

1

DDR_B+

PJ501

+3VALW

1 2

@

112

JUMP_43X118

PR503

@

10K_0402_5%

ILMT_DDR

PR505

@

0_0402_5%

2

OCP 12A

12

PC502

0.1U_0402_25V6

@EMI@

DDR_VTT_PG_CTRL[7]

12

PC503

EMI@

2200P_0402_50V7K

SYSON[13,44,45,54]

12

PR504 0_0402_5%

1 2

PR509

@

0_0402_5%

1 2

PR511 0_0402_5%

1 2

12

PC506

12

PC507

1U_0402_6.3V6K

2.2U_0402_6.3V6M

ILMT_DDR

EN_DDR

12

PR506

1M_0402_5%

12

PC504

PC505

10U_0603_25V6M

SUSP#[13,44,45,63]

+3VALW

10

IN

13

BYP

14

VCC

4

VTTGND

9

PGND

15

SGND

17

ILMT

1

S5

2

S3

SY8210AQVC_QFN19_4X3

Fsw : 600K Hz

PC521

EN_0.6VSP

@

0.1U_0402_10V7K

EN :H>0.8V ; L<0.4V

12

PC522

PR510

@

1M_0402_5%

0.1U_0402_10V7K

PU501

VDDQSNS

VLDOIN

VTT

VTTSNS

VTTREF

19

OT

18

PG

12

BS

11

LX

16

FB

8

7

6

5

3

LX_DDR

+1.2VP

12

PC518

1U_0402_16V6K

0_0603_5%

1 2

PR501

BST_DDR_RBST_DDR

PC508 22U_0603_6.3V6M

+0.6VSP

12

PC519

22U_0603_6.3V6M

PC501

0.1U_0603_25V7K

1 2

FB_DDR

0.6V

1UH_11A_20%_7X7X3_M

12

RF@

PR502

4.7_1206_5%

12

RF@

PC517 680P_0402_50V7K

PC520 330P_0402_50V7K

1 2

PR507

12

102K_0402_1%

PR508 100K_0402_1%

PL501

1 2

0413

RF Request

12

PC509

22U_0603_6.3V6M

+1.2VP

12

+1.2VP +1.2V

B+

D D

C C

+0.6VSP +0.6VS

0.6V +/- 1.5% OCP 2A

12

PC510

PC511

22U_0603_6.3V6M

PJ503

@

112

JUMP_43X118

PJ504

@

112

JUMP_43X39

+1.2VP

12

PC514

PC513

PC512

22U_0603_6.3V6M

2

12

PC523

10U_0603_25V6M

+5VALW

12

PC524

2.5V_VIN

1U_0603_25V6K

EN :H>1.2V ; L<0.4V

12

PC526

@

.1U_0402_16V7K

4

RT9059GQW_WDFN10_3X3

10

9 8 7

2.5V_EN

6

11

VDD VIN VIN VIN EN

PAD

2

VOUT

3

VOUT

4

ADJ/NC

5

PGOOD

PU502

0.8V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

PC525

PR512

43K_0402_1%

12

PR514

10U_0603_25V6M

20K_0402_1%

2017/03/09 2018/06/30

3

+2.5VP

Compal Secret Data

Deciphered Date

+2.5VP +2.5V

2

1

VOUT

PJ505

@

Compal Electronics, Inc.

Title

PWR- 1.2VP/0.6VSP/2.5VP

Size

Document Number Re v

Custom

VE

Date : Sheet o f

112

JUMP_43X79

2

54 66Thursday, June 15, 2017

1

0.1

B B

+3VALW

SYSON[13,44,45,54]

PM_SLP_S4#[10,45]

A A

5

PJ502

@

2

112

JUMP_43X79

PR513 0_0402_5%

1 2

PR515 0_0402_5%@

1 2

Vinaﬁx.com

A

B

C

D

E

1 1

+3VALW

3V/5VALW_PG[34,40,45,52,53]

PJ601

@

112

JUMP_43X79

EN :H>1.2V ; L<0.4V

2 2

3 3

5F

1.8V_PGOOD

EN :H>0.8V ; L<0.4V

1 2

PR609 0_0402_5%

PR610

1M_0402_1%

@

JUMP_43X118

12

PJ602

112

,95F

2

12

PC607

PC608

2200P_0402_50V7K

+3VALW

12

PR612 10K_0402_5%

PC609

0.1U_0402_25V6

@EMI@

10U_0603_25V6M

EMI@

12

PC618

@

0.1U_0402_25V6

2

12

PC601

10U_0603_25V6M

1 2

12

PC620

10U_0603_25V6M

+3VALW

+5VALW

12

PR601

0_0402_5%

EN_1V

ILMT_1V

12

1.8V_VIN

1.8V_EN

PC602

1U_0603_25V6K

12

PU602

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND

18

GND

11

EN

13

ILMT

15

BYP

SY8286RAC_QFN20_3X3

PC619 1U_0402_6.3V6K

PC604

@

.1U_0402_16V7K

RT9059GQW_WDFN10_3X3

10

VOUT

VDD

9

VOUT

VIN

8

VOUT

VIN

7

ADJ/NC

VIN

6

PGOOD

EN

11

PAD

PU601

+1.8VALWP

PR604 100K_0402_5%

1 2

1.8V_PGOOD

9

PG

1

BS

LX_1V

6

LX

19

LX

20

LX

FB_1V

14

FB

LDO_3V

17

VCC

10

NC

12

NC

16

NC

21

PAD

1 2 3 4 5

0.8V

12

PR602

25.5K_0402_1%

12

PR603

20K_0402_1%

keep short pad, snubber is for EMI only.

PR607 0_0402_5%

1 2

12

PC617

2.2U_0402_6.3V6M

+1.8VALWP

12

PC603

10U_0603_25V6M

PC606

0.1U_0201_10V6K

BST_1V_RBST_1V

1 2

=0.6*(1+(14/20))

+1.8VALWP

0413

RF Request

PC605

RF@

PR606

4.7_1206_5%

1 2

SNUB_1V

RF@

680P_0603_50V7K

1 2

Use 7x7x3 size when the layout space is enough.

PL601

1

4

3

2

0.68UH_7.9A_20%_5X5X3_M

FB=0.6V

12

R1

PR608

12

PR611

20K_0402_1%

R2Vout=0.6V* (1+R1/R2)

12

PC610

14K_0402_1%

330P_0402_50V7K

Vout=1.02V

PJ603

112

@

JUMP_43X39

+1.8VALW

2

F,34A

12

PC612

PC611

22U_0603_6.3V6M

PC615

PC614

22U_0603_6.3V6M

PC616

PC613

@

22U_0603_6.3V6M

PJ604

@

JUMP_43X118

2

+1VALWP

112

+1.0VALW

Fsw : 500K Hz

4 4

A

OCP 12.5A

The current limit is set to 6A, 9A or 12A when this pin is pull low, floating or pull high.

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/03/09 2018/06/30

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

PWR- 1.8VALWP/1VALWP

Size

Document Number Rev

C

VE

Date: Sheet o f

E

55 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

A

1 1

2 2

B

C

D

E

BLANK

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/03/09 2018/06/30

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

BLANK

Size

Document Number Re v

Custom

VE

Date : Sheet o f

D

Date : Sheet o f

56 66Thursday, June 15, 2017

E

0.1

Vinaﬁx.com

5

D D

4

PR802

1 2

PR803

PR804

41.2K_0402_1%

VGA@

10K_0402_1%

1 2

+5VS

3

2

1

VGA@

PU801

PR805

GPU_SVC[22]

GPU_SVD[22]

VGA@

PR813

ISUMP_GFX

ISUMN_GFX_R

0.1U_0402_25V6

NTC_GFX_R

VGA@

100K_0402_1%

1 2

VGA@

1 2

100K_0402_1%

VGA@

1 2

0_0402_5%

ISUMN_GFX_R

PH802

PC821

PR806

VDDIO_VGA

PR810

ENABLE_GFX

DGPU_PWROK

VGA@

27.4K_0402_1%

1 2

12

PR820

ISUMP_GFX_NTC

2.61K_0402_1%

VGA@

12

PR814

12

IMON

PR822

11K_0402_1%

VGA@

1

NTC_NB

2

IMON_NB

3

SVC

4

VR_HOT_L

5

SVD

6

VDDIO

7

SVT

8

ENABLE

9

PWROK

10

IMON

NTC_GFX

PC811

VGA@

.22U_0402_6.3V6K

1 2

PC812

VGA@

.22U_0402_6.3V6K

1 2

12

PC818

VGA@

.022U_0402_25V4

@VGA@

100_0402_1%

1 2

VR_ON High > 1.6V Low < 1V

GPU_VRHOT#[22]

PR808

VGA@

0_0402_5%

+1.8VGS

1 2

C C

PH1002 near APU_CORE H/S mos

VRHOT Assert Threshold : 0.64V TSENSE Bias Current : 30uA PH1002=27.4K, 110C active Reset Threshold: 0.66V, 98C active 110C Assert Threshold: PR1031=27.4K 100C Assert Threshold: PR1031=16.9K

PR807

@VGA@

1 2

+3VS

100K_0402_1%

12

PC803

@VGA@

PH1003 near GFX_CORE choke

0.1U_0402_25V6K

DGPU_PWR_EN[11,23,45,58]

1 2

PR811

VGA@

133K_0402_1%

1 2

PC805

VGA@

1000P_0402_50V7K

GPU_SVT[22]

10.5K_0402_1%

1 2

VGA@

PH801

1 2

470K_0402_5%_B25/50 4700K

10K_0402_5%_B25/50 4250K

12

PC819

VGA@

PR829

38

39

40TP41

VSEN_NB

ISUMP_NB

ISUMN_NB

ISL62771HRTZ-T_TQFN40_5X5

13

11

ISEN1_GFX

ISEN2_GFX

0.15U_0402_10V6K

PR827

VGA@

562_0402_1%

1 2

@VGA@

1000P_0402_50V7K

1 2

37

FB_NB

ISUMP14ISEN212NTC

PC822

PR1046 set 750 ohm to OCP 43.75A

B B

PR1058=3.65K, PR1040=2.1K and PR1046=487 to set loadline -2.1mV/A while PR1046=487 to set OCP 56A for EDC 45A ap plication.

+VGA_CORE

12

PC833

PC832

VGA@

2.2U_0402_6.3V6M

12

PC849

PC850

10U_0603_6.3V6M

VGA@

A A

12

PC835

PC834

PC836

PC837

VGA@

2.2U_0402_6.3V6M

12

PC851

10U_0603_6.3V6M

VGA@

12

PC854

PC852

PC853

10U_0603_6.3V6M

VGA@

12

PC838

VGA@

2.2U_0402_6.3V6M

PC855

10U_0603_6.3V6M

VGA@

12

PC841

PC840

PC839

VGA@

2.2U_0402_6.3V6M

12

PC858

PC856

PC857

1U_0402_6.3V6K

VGA@

36

ISUMN_GFX

1U_0402_6.3V6K

COMP_NB

PC842

VGA@

12

35

PGOOD_NB

VSEN

16

VSEN_VGA

12

2.2U_0402_6.3V6M

PC859

VGA@

32

33

34

LGATE_NB

PHASE_NB

RTN17ISUMN15ISEN1

FB18PGOOD

19

FB_VGA

RTN_GFX

COMP_VGA

VGA@

1000P_0402_50V7K

PC815

@VGA@

330P_0402_50V7K

12

PC826

VGA@

0.01U_0402_50V7K

12

PC843

VGA@

2.2U_0402_6.3V6M

12

1U_0402_6.3V6K

31

BST2_GFX

30

BOOT_NB

BOOT2

UGATE_NB

COMP

PC844

VGA@

PC860

VGA@

20

PC813

1 2

2.2U_0402_6.3V6M

0.1U_0402_10V7K

12

UGATE2

PHASE2

LGATE2

VDDP

VDD

LGATE1

PHASE1

UGATE1

BOOT1

VGA@

1K_0402_1%

1 2

PC845

VGA@

2.2U_0402_6.3V6M

PC861

0.1U_0402_10V7K

VGA@

29

28

27

26

25

24

23

22

21

DGPU_PWROK

PR818

VGA@

301_0402_1%

1 2

PR823

VGA@

10_0402_5%

1 2

VGA@

0_0402_5%

1 2

VGA@

0_0402_5%

1 2

VGA@

10_0402_5%

12

PC846

VGA@

2.2U_0402_6.3V6M

12

PC862

0.1U_0402_10V7K

VGA@

UG2_GFX

LX2_GFX

LG2_GFX

LG1_GFX

LX1_GFX

UG1_GFX

BST1_GFX

@VGA@

PR830

PR831

12

PR812

100K_0402_1%

VGA@

PR824

137K_0402_1%

1 2

VGA@

PR826

2K_0402_1%

1 2

PR828

PR832

PC847

VGA@

2.2U_0402_6.3V6M

+5VS

1 2

VGA@

PR801 1_0603_5%

12

PC804

VGA@

1U_0603_10V6K

DGPU_PWROK [11,58]

@VGA@

32.4K_0402_1%

1 2

BST2_GFX

LX2_GFX

PR819

VGA@

2.2_0603_1%

1 2

PR833

PC802

VGA@

1U_0603_10V6K

VGA@

2.2_0603_1%

LX1_GFX

BST2_GFX_R

+3VS

12

PC814

VGA@

220P_0402_50V8J

1 2

VGA@

PC816

390P_0402_50V7K

1 2

VGA@

PC820

330P_0402_50V7K

1 2

PR1058=3.65K, PR1040=2.1K and PR1046=604 to set loadline -2.1mV/A

+VGA_CORE

VCCSENSE_VGA [22]

VSSSENSE_VGA [22]

PR815

1 2

BST1_GFX_RBST1_GFX

PC831

VGA@

0.22U_0603_25V7K

1 2

PC810

VGA@

0.22U_0603_25V7K

1 2

2

D1

D2/S1

S24S2

S23G2

5

2

D1

D2/S1

S24S2

S23G2

5

UG2_GFX

1

G1

LX2_GFX

7

AON6962_DFN5X6D-8-7

6

LG2_GFX

UG1_GFX

1

G1

7

AON6962_DFN5X6D-8-7

6

LG1_GFX

PQ803VGA@

0413

RF Request

LX1_GFX

PC827

VGA@

PQ802VGA@

10U_0603_25V6M

12

RF Request

VGA_B+

PC828

VGA@

10U_0603_25V6M

12

SNB_VGA2

12

PC807

PC806

12

VGA@

10U_0603_25V6M

0413

PC829

12

2200P_0402_50V7K

@VGA_EMI@

VGA_RF@

PR834

4.7_1206_5%

VGA_RF@

PC848

680P_0603_50V7K

VGA_B+

12

@VGA_EMI@

10U_0603_25V6M

VGA_RF@

12

PR816

4.7_1206_5%

SNB_VGA

12

VGA_RF@

PC817

680P_0603_50V7K

PC830

12

0.1U_0402_25V6K

VGA_EMI@

PC808

2200P_0402_50V7K

12

ISUMP_GFX

ISEN2_GFX

ISUMN_GFX_R

12

PC809

VGA_EMI@

0.1U_0402_25V6K

ISUMP_GFX

ISEN1_GFX

ISUMN_GFX_R

+VGA_CORE

VGA@

3.65K_0603_1%

1 2

VGA@

10K_0402_1%

1 2

VGA@

1_0402_1%

1 2

PJ801

@

2

112

JUMP_43X118

PJ802

@

2

112

JUMP_43X118

SH000011H00 (DCR:0.98mohm +/-5%)

134

2

PR817

VGA@

3.65K_0603_1%

1 2

PR821

VGA@

10K_0402_1%

1 2

VGA@

1_0402_1%

1 2

1

+

PC823

PC824

2

VGA@

330U_B2_2.5VM_R9M

SH000011H00 (DCR:0.98mohm +/-5%)

134

2

PR835

PR836

PR837

VGA@

0.24UH_22A_+-20%_ 7X7X3_M

PR825

1

+

PC825

2

VGA@

330U_B2_2.5VM_R9M

PL802

VGA@

0.24UH_22A_+-20%_ 7X7X3_M

PL801

B+

+VGA_CORE

GFX_c ore TDC 30(1H1L) Peak Current 45A OCP current > 56A Load line -2.1mV/A FSW=40 0kHz DCR 0.98mohm +/-5% TYP MAX H/S Rds(on) :11.7mohm , 14mohm L/S Rds(on) :2.7mohm , 3.3mohm

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

2017/03/09 2018/06/30

Deciphered Date

2

Compal Electronics, Inc.

Title

PWR- VGA_CORE

Size

Document Number Re v

Custom

VE

Date: Sheet of

1

57 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

D D

PR908

12

VGA@

0.1U_0402_10V7K

@VGA@

0_0402_5%

1 2

PR902

VGA@

88.7K_0402_1%

1 2

PC902

DGPU_PWROK [11,57]

DGPU_PWR_ENEN_1.35V

DGPU_PWR_EN [11,23,45,57]

C C

12

PR903

VGA@

1M_0402_1%

5F9C>,

PJ901

@

2

112

JUMP_43X118

12

PC904

2200P_0402_50V7K

VGA_EMI@

PC906

PC905

0.1U_0402_25V6

VGA@

@VGA_EMI@

LDO_3V_1.35V

@VGA@

PR906 0_0402_5%

1 2

ILMT_1.35V

5F

+3VALW

B B

OCP 9.5A

4

EN :H>0.8V ; L<0.4V

2

PC914

VGA@

10U_0603_25V6M

EN_1.35V

ILMT_1.35V

3

4

5

7

8

18

11

13

15

12

VGA@

1U_0402_6.3V6K

12

10U_0603_25V6M

PU901

VGA@

SY8286RAC_QFN20_3X3

IN

GND

EN

ILMT

BYP

PC913

Fsw : 500K Hz

9

PG

BST_1.35V BST_1.35V_R

1

BS

LX_1.35V

6

LX

19

LX

20

LX

FB_1.35V

14

FB

LDO_3V_1.35V

17

VCC

10

NC

12

NC

16

NC

21

PAD

12

VGA@

2.2U_0402_6.3V6M

3

keep short pad, snubber is for EMI only.

PR901

PC912

VGA@

0_0402_5%

1 2

VGA@

0.1U_0201_10V6K

Vout=0.6V* (1+R1/R2) =0.6*(1+(22.6/18))

Vout=1.353V

1 2

PR904

VGA_RF@

4.7_1206_5%

1 2

PC901

Use 7x7x3 size when the layout space is enough.

VGA@

1 2

1UH_6.6A_20%_5X5X3_M

SNUB_1.35V

PL901

FB=0.6V

R2

R1

VGA_RF@

680P_0603_50V7K

12

PR905

VGA@

12

VGA@

18K_0402_1%

22.6K_0402_1%

0413

RF Request

PC903

1 2

12

PR907

2

PJ902

@

12

PC907

330P_0402_50V7K

VGA@

12

PC908

22U_0603_6.3V6M

VGA@

12

PC910

PC909

22U_0603_6.3V6M

VGA@

PC911

22U_0603_6.3V6M

VGA@

22U_0603_6.3V6M

VGA@

FC>,8

+1.35VGSP

JUMP_43X118

112

1

2

+1.35VS_VRAM

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/03/09 2018/06/30

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PWR- 1.35VRAM

Size

Document Number Re v

Custom

VE

Date: Sheet of

1

58 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

PR1001

12.1K_0402_1%

1 2

PC1001

4700P_0402_25V7K

1 2

D D

C C

U22@

PR1007

90.9K_0402_1%

1 2

PC1005

330P_0402_50V7K

1 2

PC1007

47P_0402_50V8J

1 2

PC1008

8200P_0402_25V7K

VCCGT_SENSE[15]

VSSGT_SENSE[15]

ISUMP_GT[60,61]

ISUMN_GT[60,61]

1 2

PR1023

3.6K_0402_1%

+VCCGT

1 2

PR1062 100_0402_1%

PR1060 0_0402_5%

1 2

PR1061 0_0402_5%

1 2

PR1063 100_0402_1%

12

PR1034

2.61K_0402_1%

12

PH1003

10K_0402_5%_B25/50 4250K

12

PC1027

12

PR1038

11K_0402_1%

PH1001

470K_0402_5%_ TSM0B474J4702RE

1 2

PR1012

27.4K_0402_1%

1 2

FB to GND of GT

U22@

12

PC1021

PC1020

0.047U_0402_25V7K

PC1009

820P_0402_25V7

1 2

PC1010

680P_0402_50V7K

Droop of GT at 2.65mV/A

12

PC1015

0.01UF_0402_25V7K

12

0.033U_0402_16V7K

NTC of GT at 100 deg

1000P_0402_50V7K

2K_0402_1%

1 2

U22@

PR1031

1.91K_0402_1%

1 2

PR1013

10.2K_0402_1%

1 2

PC1006

1 2

PR1024

PR1025 1K_0402_1%

1 2

PR1040

1K_0402_1%

1 2

.1U_0402_16V7K

B B

A A

FCCM_GT[60,61]

PWM1_GT[61]

PWM2_GT[60]

12

U22@

PR1055

93.1K_0402_1%

PC1022

2200P_0402_50V7K

1 2

U22@

PR1042

374_0402_1%

1 2

OCP of GT at 66.71A

U23@

PC1028

0.022U_0402_25V7K

1 2

U23@

PC1030

0.022U_0402_25V7K

1 2

12

PC1039

330P_0402_50V7K

4

1_0402_5%

ISL95829_SVID_DATA

ISL95829_SVID_ALERT#

ISL95829_SVID_CLK

44

45

46

47

48

SCLK

VR_HOT#

VR_READY

VR_ENABLE

PWM2_B13NTC_A15COMP_A16FB_A17RTN_A18ISUMP_A19ISUMN_A

IMON_A

14

12

+5VS CPU_B+

12

PR1002

41

42

43

VIN

SDA

VCC

ALERT#

20

PR1057

2K_0402_1%

PC1043

680P_0402_50V7K

+1.0V_VCCST

+VCCST

12

+3VS

I_SYS[51]

P_SYS

U22@

PR1041 0_0402_5%

PC1040

68P_0402_50V8J

12

PR1005

45.3_0402_1%

PR1053

10.2K_0402_1%

1 2

12

PR1006

100_0402_1%

PR1008

10_0402_1%

1 2

PR1009

0_0402_5%

1 2

PR1011 49.9_0402_1%

1 2

PR1014 100_0402_1%

PR1015

1.91K_0402_1%

1 2

PR1020 0_0402_5%

1 2

PR1021

0_0402_5%

1 2

1 2 3 4 5 6 7 8

9 10 11 12

49

12

PR1059

2.26K_0402_1%

12

PC1042 2200P_0402_50V7K

Comp of IA

PSYS IMON_B NTC_B COMP_B FB_B RTN_B ISUMP_B ISUMN_B ISEN1_B ISEN2_B FCCM_B PWM1_B

EP

PC1002

0.1U_0402_10V7K

VR_SVID_DATA[15]

VR_ALERT#[15]

VR_SVID_CLK[15]

VR_HOT#[45]

VR_PWRGD[45]

VR_ON[45]

VR_ON

+5VS

12

ISEN2_GT [60,61]

ISEN1_GT [60,61]

NTC of CORE at 100 deg

12

PR1056

27.4K_0402_1%

PH1005

470K_0402_5%_ TSM0B474J4702RE

12

PR1003 0_0402_5%

PU1001 ISL95829AHRTZ-T_TQFN48_6X6

39

38

40

PROG2

PROG3

PROG437PROG1

PROG5 PWM_C

FCCM_C ISUMN_C ISUMP_C

RTN_C

COMP_C

IMON_C PWM3_A PWM2_A PWM1_A

ISEN1_A21ISEN2_A22ISEN3_A23FCCM_A

24

U22@

PR1049 383_0402_1%

1 2

PC1035

2200P_0402_50V7K

3

FB_C

1 2

PR1054

316_0402_1%

36 35 34 33 32 31 30 29 28 27 26 25

U22@

1 2

PC1003

1U_0402_16V6K

1 2

PC1004

0.22U_0603_16V7K

12

PR10450_0402_5%

PR10480_0402_5%

ISEN2_VCORE[60]

ISEN1_VCORE[60]

PR1050

1K_0402_1%

Comp of IA

1 2

U22@

PR1058

1.54K_0402_1%

Droop of CORE at 1.8mV/A

12

PR1017

PR1016

34K_0402_1%

165K_0402_1%

PR1014 ICCMAX of GT 70A for U23e 33A for U22 & U42

PR1027 34K_0402_1%

1 2

PWM3_VCOR E

+5VS

OCP of Vcore at 83.2A

1 2

PC1036

1500P_0402_50V7K

PR1015 ICCMAX of IA 70A for U42 33A for U22 & U23e

12

PR1019 110K_0402_1%

PR1018

150K_0402_1%

PR1023 ICCMAX of SA is 7A

PWM_SA [61]

FCCM_SA [61]

PWM2_VCORE [60]

PWM1_VCORE [60]

FCCM_VCORE [60]

U42@

1 2

PC1029 0.022U_0402_25V7K

1 2

PC1031 0.022U_0402_25V7K

U42@

12

PC1020

U22@

0.047U_0402_25V

PC1020

SE102104K00

0.1U_0402_10V7K

PC1020

SE00000MJ00

0.047U_0402_25V7K

IMON of SA Cn of GT

PR1039

115K_0402_1%

PC1037

0.01UF_0402_25V7K

U23@

U42@

12

PR1007

U22@

90.9k_0402_1%

PR1007

SD034887280

88.7K_0402_1%

PR1007

SD034909280

90.9K_0402_1%

OCP of SA at 10A

PR1022

665_0402_1%

1 2

PC1011

2200P_0402_50V7K

1 2

12

PC1023

PC1024

68P_0402_50V8J

330P_0402_50V7K

12

PC1032

.1U_0402_16V7K

PR1071 100_0402_1%

PR1070 100_0402_1%

2

U23@

U42@

12

Comp of SA

1 2

0_0402_5%

1 2

0_0402_5%

1 2

Cn of IA

PR1068

PR1069

PR1031

U22@

1.91k_0402_1%

PR1031

SD034255180

2.55K_0402_1%

PR1031

SD000009O80

1.91K_0402_1%

PR1028

1K_0402_1%

1 2

PC1014

.1U_0402_16V7K

12

PR1035

4.42K_0402_1%

PR1036

12

PC1025

PC1026

8200P_0402_25V7K

12

PC1033

0.033U_0402_16V7K

U23@

U42@

12

2K_0402_1%

12

680P_0402_50V7K

U22@

+VCCCORE

U22@ 374_0402_1%

PR1042

442_0402_1%

PR1042

374_0402_1%

12

PC1034

0.047U_0402_25V7K

VSSCORE_SENSE [15]

VCCCORE_SENSE [15]

SD034442080

SD034374080

U22@

0.047U_0402_25V

PC1034

U23@

SE00000MJ00

0.047U_0402_25V7K

PC1034

U42@

SE102104K00

0.1U_0402_10V7K

RC Match of SA

12

PC1012

PC1013

0.01UF_0402_25V7K

0.033U_0402_16V7K

1 2

PC1016

PR1033

1500P_0402_50V7K

316_0402_1%

1 2

PR1037

1.69K_0402_1%

set the LL of SA at 10.3mV/A

12

PR1051

11K_0402_1%

1

PR1055PC1034PR1042 PR1041

PR1058

U22@

1.54k_0402_1%

93.1k_0402_1%

U23@

U42@

12

PR1029

11K_0402_1%

12

10K_0402_5%_B25/50 4250K

12

PR1052

5.49K_0402_1%

RC Comp of IA

PR1055

U23@

SD034100380

100K_0402_1%

PR1055

U42@

SD034887280

88.7K_0402_1%

12

Comp of SA

PH1004

PR1058

U23@

SD034154180

1.54K_0402_1%

PR1058

U42@

SD00000J380

3.09K_0402_1%

12

PH1002 10K_0402_5%_B25/50 4250K

12

PR1032

2.61K_0402_1%

12

PC1017

0.01UF_0402_25V7K

ISUMN_VCORE [60]

ISUMP_VCORE [60]

ISUMP_SA [61]

PR1048

PR1049

U22@ 383_0402_1%

PR1048

PR1049

U23@

SD034383080

383_0402_1%

PR1049

U42@

SD034475080

475_0402_1%

ISUMN_SA [61]

1 2

PR1067 100_0402_1%

PR1064 0_0402_5%

1 2

PR1065 0_0402_5%

1 2

PR1066 100_0402_1%

U22@ 0_0402_5%

U23@

SD028000080

0_0402_5%

U22@ 0_0402_5%

PR1041

U42@

SD028000080

0_0402_5%

VSSSA_SENSE [13]

VCCSA_SENSE [13]

+VCCSA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/03/09 2018/06/30

2

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR- CPU Controller

Size

Document Number Rev

Custom

VE

Date: Shee t of

1

59 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

4

3

2

1

CPU_B++5VS

PU1101

13

NC

14

PWM1_VCORE[59]

FCCM_VCORE[59,60]

D D

PC1107

0.1U_0402_25V6

EMI@

PC1104 33U_25V_M

12

PC1108

2200P_0402_50V7K

EMI@

B+

PJ1001

@

JUMP_43X118

112

PJ1002

@

JUMP_43X118

112

2

PC1168

10U_0603_25V6M

CPU_B+

12

PC1105

10U_0603_25V6M

PC1103 33U_25V_M

12

PC1106

10U_0603_25V6M

1

+

2

12

PC1169

10U_0603_25V6M

1

+

2

12

PC1102

0.1U_0603_25V7M

PC1101

4.7U_0603_10V6K

12

PR1101

2.2_0603_1%

12

VCC

1

PWM

2

FCCM

3

BOOT

4

GH

5

VSWH

AOZ5048QI_QFN24_5X3P5

VSWH

PGND PGND

6

VIN

12

VIN

10

GL

9

GL

IA_LX1

8

11 7

ISEN1_VCORE[59]

ISUMP_VCORE[59]

ISUMN_VCORE[59]

12

PR1102

RF@

4.7_1206_5%

12

PC1111

RF@

680P_0603_50V7K

ISEN2_VCORE

0413

RF Request

DCR 0.9m ohm +-5% Idc = 37A Isat = 41A

PL1101

0.15UH_NA__35A_20%

1

2

12

PR1103

PR1104

U42@

100K_0402_1%

3.65K_0603_1%

4

3

12

PR1106

PR1105

U42@

2.2_0402_1%

+VCCCORE

12

100K_0402_1%

C C

PWM2_GT[59]

PWM2_VCORE[59]

FCCM_GT[59,61]

FCCM_VCORE[59,60]

12

PC1170

PC1171

10U_0603_25V6M

U42@

B B

PC1170

U23@

SE00000X200

10U_0603_25V6M

PC1112

U23@

SE00000MA00

4.7U_0603_10V6K

PC1117

U23_EMI@

A A

SE00000G880

0.1U_0402_25V6

PR1112

U23_RF@

SD001470B80

4.7_1206_5%

U23@

0_0402_5%

1 2

U42@

0_0402_5%

1 2

U23@

0_0402_5%

1 2

U42@

0_0402_5%

1 2

12

PC1116

PC1115

10U_0603_25V6M

U42@

PC1171

SE00000X200

10U_0603_25V6M

PR1110

SD014220B80

2.2_0603_1%

PC1118

SE074222K80

2200P_0402_50V7K

PC1114

SE025681K80

680P_0603_50V7K

5

PR1107

PR1108

PR1109

PR1111

U23@

U23_EMI@

U23_RF@

12

PC1117

0.1U_0402_25V6

U42_EMI@

PC1112

U42@

4.7U_0603_10V6K

12

PC1118

2200P_0402_50V7K

U42_EMI@

PC1115

U23@

SE00000X200

10U_0603_25V6M

PC1113

U23@

SE042104M80

0.1U_0603_25V7M

12

U42@

0.1U_0603_25V7M

PC1116

U23@

SE00000X200

10U_0603_25V6M

12

PC1113

U42@

2.2_0603_1%

13 14

1 2 3

12

4

PR1110

5

AOZ5048QI_QFN24_5X3P5

4

U42@

PU1102

NC VCC PWM FCCM BOOT GH

VSWH

PU1102

SA0000AWU00

U23@

VSWH

PGND PGND

CPU_B++5VS

6

VIN

12

VIN

10

GL

9

GL

8

11 7

U42_RF@

ISEN2_VCORE[59]

ISUMP_VCORE

ISUMN_VCORE

ISEN1_VCORE

ISUMP_GT[59,61]

PWM2_PH

12

PR1112

4.7_1206_5%

12

PC1114

0413

RF Request

680P_0603_50V7K

PWM2_PH

ISEN2_GT[59,61]

12

PR1113

100K_0402_1%

U42@

12

PR1117

U23@

3.65K_0603_1%

3

PL1105

U42@

0.15UH_NA__35A_20%

1 2

PL1103 & PL1107 change footprint to NEC_MPCH0730LR15_2P for co-lay

DCR 0.9m ohm +-5% Idc = 37A

12

PL1106

12

PR1115

PR1116

2.2_0402_1%

U42@

12

PR1120

PR1119

2.2_0402_1%

U23@

Isat = 41A

100K_0402_1%

+VCCGT

DCR 0.9m ohm +-5% Idc = 37A Isat = 41A

12

100K_0402_1%

Compal Secret Data

Deciphered Date

2017/03/09 2018/06/30

Deciphered Date

2

12

PR1114

U42@

3.65K_0603_1%

U23@

0.15UH_NA__35A_20%

1 2

12

PR1118

100K_0402_1%

U23@

ISUMN_GT[59,61]

ISEN1_GT[59,61]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

PWR- VCCCORE,VCCGT

Size

Document Number Rev

C

VE

Date: Sheet o f

1

60 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

5

4

3

2

1

VCC_GT (U-line 22) TDC 18A Peak Current 31A OCP current 37A

+5VS

D D

PU1151

13

NC

14

VCC

PWM1_GT[59] FCCM_GT[59,60]

12

PC1172

10U_0603_25V6M

C C

12

PC1154

PC1159

PC1173

10U_0603_25V6M

12

10U_0603_25V6M

PC1151

4.7U_0603_10V6K

12

PC1156

PC1155

0.1U_0402_25V6

EMI@

2200P_0402_50V7K

12

0.1U_0603_25V7M

1 2

PC1152

1 2

PR1151

2.2_0603_1%

1

PWM

2

FCCM

3

BOOT

4

GH

5

VSWH

AOZ5048QI_QFN24_5X3P5

VSWH

PGND PGND

CPU_B+

6

VIN

12

VIN

10

GL

9

GL

GT_LX1

8

11 7

RF Request

0413

12

PR1152

RF@

4.7_1206_5%

12

PC1157

RF@

680P_0603_50V7K

ISUMP_GT[59,60]

ISEN1_GT[59,60]

12

PR1153

3.65K_0603_1%

12

PR1154

U23@

100K_0402_1%

PL1151

0.15UH_NA__35A_20%

1

2

ISUMN_GT[59,60]

ISEN2_GT[59,60]

CPU_B+

12

PC1160

B B

0.1U_0402_25V6

@EMI@

12

PC1161

@EMI@

2200P_0402_50V7K

12

PC1163

PC1164

10U_0603_25V6M

FCCM_SA[59]

PWM_SA[59]

PC1165

1 2

1U_0603_10V6K

+5VS

PU1152

6

VCC

7

FCCM

3

PWM

GND4LGATE

1

UGATE

2

BOOT

8

PHASE

5

TP

ISL95808HRZ-T_DFN8_2X2

9

SA_HG

PR1157 2.2_0603_1%

SA_LX

SA_LG

12

PC1166

0.1U_0603_25V7K

4

3

D1

D110D2/S1

S2

6

5

VCC_GT Merged(GT+GTx)(U-line 23e) TDC 35A Peak Current 64A OCP current 74A

4

3

PQ1151

1

2

AON7934_DFN3X3A8-10

D1

G1

9

S2

G2

7

8

12

PR1155

2.2_0402_1%

DCR 0.9m ohm +-5% Idc = 37A Isat = 41A

12

PR1156

U23@

100K_0402_1%

12

PR1158

RF@

4.7_1206_5%

12

0413

PC1167

RF Request

RF@

ISUMP_SA[59]

680P_0603_50V7K

ISUMN_SA[59]

12

PR1159

3.65K_0603_1%

PL1153

0.47UH_NA__12.2A_20%

1 2

+VCCGT

+VCCSA

DCR 6.2m ohm +-5% Idc = 12.2A

12

Isat = 16A

PR1160

0_0402_5%

VCC_ SA TDC 5A Peak Current 5.1A OCP current 7A

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/03/09 2018/06/30

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size

Date: Sheet o f

Compal Electronics, Inc.

PWR- VCCGT,VCCSA

Document Number Rev

VE

1

61 66Thursday, June 15, 2017

0.1

Vinaﬁx.com

A A

B B

C C

D D

+VCCSA

12

PC1347

1U_0201_6.3V6M

12

PC1348

1U_0201_6.3V6M

12

5

4

PC1349

1U_0201_6.3V6M

PC1350

1U_0201_6.3V6M

PC1351

1U_0201_6.3V6M

PC1352

1U_0201_6.3V6M

PC1353

1U_0201_6.3V6M

PC1354

1U_0201_6.3V6M

12

VCCSA Place on CPU Back Side

22U_0603 * 9 pcs

1U_0201 * 8 pcs

2

PC1338

22U_0603_6.3V6M

2

PC1339

22U_0603_6.3V6M

2

PC1340

22U_0603_6.3V6M

2

PC1341

22U_0603_6.3V6M

2

PC1342

22U_0603_6.3V6M

2

PC1343

22U_0603_6.3V6M

2

PC1344

22U_0603_6.3V6M

2

PC1345

22U_0603_6.3V6M

2

PC1346

22U_0603_6.3V6M

PC1355

10P_0402_25V8J

RF@

RF Request0413

1

12

PC1331

1U_0201_6.3V6M

12

PC1332

1U_0201_6.3V6M

12

PC1333

1U_0201_6.3V6M

12

PC1334

1U_0201_6.3V6M

12

PC1335

1U_0201_6.3V6M

12

PC1336

1U_0201_6.3V6M

12

PC1337

1U_0201_6.3V6M

PC1306

1U_0201_6.3V6M

PC1307

1U_0201_6.3V6M

PC1308

1U_0201_6.3V6M

PC1309

1U_0201_6.3V6M

PC1310

1U_0201_6.3V6M

PC1311

1U_0201_6.3V6M

PC1312

1U_0201_6.3V6M

PC1313

1U_0201_6.3V6M

PC1314

1U_0201_6.3V6M

PC1315

1U_0201_6.3V6M

PC1316

1U_0201_6.3V6M

PC1317

1U_0201_6.3V6M

PC1318

1U_0201_6.3V6M

PC1319

1U_0201_6.3V6M

PC1320

1U_0201_6.3V6M

PC1321

1U_0201_6.3V6M

PC1322

1U_0201_6.3V6M

PC1323

1U_0201_6.3V6M

12

PC1274

1U_0201_6.3V6M

12

PC1275

1U_0201_6.3V6M

12

PC1276

1U_0201_6.3V6M

12

PC1277

1U_0201_6.3V6M

12

PC1278

1U_0201_6.3V6M

12

PC1279

1U_0201_6.3V6M

12

PC1280

1U_0201_6.3V6M

12

PC1281

1U_0201_6.3V6M

12

PC1282

1U_0201_6.3V6M

12

PC1283

1U_0201_6.3V6M

12

PC1284

1U_0201_6.3V6M

12

PC1285

1U_0201_6.3V6M

12

PC1286

1U_0201_6.3V6M

12

PC1287

1U_0201_6.3V6M

12

PC1288

1U_0201_6.3V6M

12

PC1289

1U_0201_6.3V6M

12

PC1290

1U_0201_6.3V6M

12

PC1291

1U_0201_6.3V6M

+VCCCORE

PC1255

22U_0603_6.3V6M

PC1256

22U_0603_6.3V6M

PC1257

22U_0603_6.3V6M

PC1258

22U_0603_6.3V6M

PC1259

22U_0603_6.3V6M

PC1260

22U_0603_6.3V6M

PC1261

22U_0603_6.3V6M

2

PC1253

330U_B2_2.5VM_R9M

2

PC1254

330U_B2_2.5VM_R9M

2

12

1

+

1

+

U42@

1

+

PC1658

220U_D7_2VM_R4.5M

@

PC1227

22U_0603_6.3V6M

PC1228

22U_0603_6.3V6M

PC1229

22U_0603_6.3V6M

PC1230

22U_0603_6.3V6M

PC1231

22U_0603_6.3V6M

PC1232

22U_0603_6.3V6M

PC1233

22U_0603_6.3V6M

PC1234

22U_0603_6.3V6M

PC1235

22U_0603_6.3V6M

PC1236

22U_0603_6.3V6M

PC1237

22U_0603_6.3V6M

PC1238

22U_0603_6.3V6M

+VCCCORE

12

330U_B2 * 2 pcs

22U_0603_6.3V6M

22U_0603 * 31 pcs

1U_0201 * 43 pcs

12

PC1201

12

PC1202

12

PC1203

12

PC1204

12

PC1205

12

PC1206

12

PC1207

12

PC1208

12

PC1209

12

PC1210

12

PC1211

12

PC1212

22U_0603 * 26 pcs

1U_0201 * 38 pcs

330U_B2 * 1 pcs

U42

+VCCCORE

5

4

VCCCORE Place on CPU Back Side

U22&U23