Compal LA-C901P Schematics Rev1.0

A

B

C

D

E

MODEL NAME : AAP01 PROJECT CODE : ANRAAP0100 PCB NO :

DAA000AK000 LA-C901P M/B

1 1

DA400237000 LS-C901P SSD/B DA40023X000 LS-C902P SSD/B (w/o redriver) DA40023Y000 LS-C904P LOGO/B

ZZZ

PCB@

PCB 1FU LA-C901P REV0 M/B MLK 3

DAA000AK000

ZZZ

PCBR1@

2 2

PCB 1FU LA-C901P REV1 M/B MLK 3

DAA000AK010

ZZZ

PCBR3@

PCB 1FU LA-C901P REV1 MB MLK TRIP 3 A31!

DAA000AK011

ZZZ

DAZR1@

Echo MLK 13" SKL-U

Skylake U-type (1 chip_DSC)

REV : 1.0 (A00)

2015.07.14

@ : Nopop Component

PCB AAP01 LA-C901P LS-A302P/A303P/C904P 02

DAZ1FU00100

ZZZ

DAZR3@

EMI@,ESD@ : EMI/ESD/RF part

CONN@ : Connector Component

PCB AAP01 LA-C901P LS-A302P/A303P/C904P 02 TRIPOD A31 !

DAZ1FU00101

3 3

ROYALTY HDMI W/LOGOHDMI@

Part Number Description

HDMI W/Logo:RO0000002HM

RO0000002HM

Layout Dell logo

4 4

REV: X00 PWB: XXXXX DATE: 1450-06

CMC@ : Total debug Component

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Cover page

Cover page LA-C901P

LA-C901P

E

1 63Tuesday, August 04, 2015

1.0

A

B

C

D

E

eDP

P.20

eDP 1.3

panel

1 1

P.47

USB3 TypeC

USB PD I2C/USB2

HDMI

TPS65982

P.21

P.46

ThunderBolt Alpine Ridge-SP

P.44,45

DP 1.2 (DDI1) DP 1.2 (DDI2)

PCI-E x2(port9,port10)

connector

HDMI 2.0

dGPU nVIDIA N16P-GX,50W 4pcs GDDR5

2 2

P.34

PCI-E x4 (Gen3)

PCIE MUX PERICOM PI3PCIE3415

PCI-E x4 (Gen3)

Video Docking Caldera

P.34P.22~29

USB3.0 port3 USB2.0 port3

PCI-E(Gen3)x4 po

rt1~port4

Skylake U

+

Skylake PCH-LP (MCP)

(SKL-U_2+2)

15W BGA 1356 balls

CDR_I2C

P.32

P.30P.30

P.08

PCI-E3.0 port5 USB2.0 port8

PCI-E3.0 port6

PCI-E3.0 port7,8 SATA3.0 port0,1

PC

I-E3.0 port11,12

SATA3.0 port1,2

SPI

NGFF (M.2)WLAN+BT QCA killer 1535(A Key)

RJ45 connector

3 3

Storage Option2 Dual M.2 DB

LAN(Gigabit) Killer E2400

NGFF (M.2) SSD 1

NGFF (M.2) SSD 2

SPI ROM 16MB

DC in

1.0V

Battery

3V/5V

System

4 4

1.35V

1.5V

CPU Vcore

dGPU Core

Charger

dGPU

1.35V

Int. KBD

ENE KC3810

P.40

P.41

LPC Bus

ENE KB9022

P.41

PS2

P.06~17

I2C(400KHz)

Touch pad

Memory Bus Dual Channel

35V,DDR3L,1600 MHz

1.

US

B3.0 port2

SB2.0 port2

U USB3.0 port1

USB2.0 port1

USB2.0 port5

USB2.0 port6

USB2.0 port7

SATA3.0 port0 ; option

HD Audio

P.38

FFS KXCNL-1010

CDR_I2C

Audio codec Realtek ALC3234

P.36 P.40 P.06

Fan control NCT7718W W83L771AWG-2

CMC connector (Reserve)

P.18,19

204pin SO-DIMM x2

P.38,39

LED SET

P.33

P.20

P.37

P.36

USB connector 1 , Left side USB power share

USB connector 2 , Right side 1

Touch screen

Digital camera(with digital MIC)

AlienFX / ELC , C8051F383-GQ

ELC PWM expander , TLC59116F

2.5”HDD

Storage Option1

P.31

digital MIC

Speaker

Headphone/MIC Global headset combo JACK

Headphone/MIC Retaskable combo JACK

P.31

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT C ONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT C ONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Block diagram

Block diagram LA-C901P

LA-C901P

E

2 63Tuesday, August 04, 2015

1.0

A

Power on sequence

DCACEC_ON

DCACVCCDSW(+3VALW)

DCACPCH_PWR_EN(SLP_SUS#)

+3V/+1.8V_PRIM

SUSACK#

DCAC

Power Button

DPWROK_EC

EC_RSMRST#

AC_Present

Power Button Out

1 1

PM_SLP_S4# (Input)

PM_SLP_S3# (Input)

SYSON

SUP#

VCCST_PG_EC

VR_ON

VR_PWRGD

PCH_PWROK

SYS_PWROK

T_RST#

PL

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

A

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Power on sequence

Power on sequence LA-C901P

LA-C901P

3 63Tuesday, August 04, 2015

1.0

A

Board ID Table for AD channel

Vcc 3.3V

Board ID

10 11 12 13 14 15 16 17 18 19

Board ID table and PCB version

ID

1 1

0 1 2 3 4 5 33K 6 7 56K

100K +/- 1%Ra

0 1

0

12K +/- 1% 0.354V

2

Rb V min

3

20K +/- 1%

4

27K +/- 1%

5

33K +/- 1%

6

43K +/- 1%

7

56K +/- 1%

8

75K +/- 1%

9

100K +/- 1% 130K +/- 1% 160K +/- 1% 200K +/- 1% 240K +/- 1% 270K +/- 1% 330K +/- 1% 430K +/- 1% 560K +/- 1% 750K +/- 1%

NC

AD_BID

0.347V

0.423V 0.430V

0.541V 0.559V

0.691V

0.807V

0.978V

1.169V

1.398V

1.634V

1.849V

2.015V

2.185V

2.316V

2.395V

2.521V

2.667V

2.791V

2.905V

3.000V 3.000V

Rb

0 12K 15K 20K 27K

EVT(R0.1) DVT-1(R0.2) DVT-1.1(R0.3) DVT-2(R0.4) Pilot(R1.0)

43K

V typ

AD_BID

V

AD_BID

0.000V 0.300V

0.360V

0.438V15K +/- 1%

0.550V

0.702V

0.819V

0.992V

1.185V

1.414V

1.650V

1.865V

2.031V

2.200V

2.329V

2.408V

2.533V

2.677V

2.800V

2.912V

0.713V

0.831V

1.006V

1.200V

1.430V

1.667V

1.881V

2.046V

2.215V

2.343V

2.421V

2.544V

2.687V

2.808V

2.919V

max

EC AD3

0x00 - 0x13 0x14 - 0x1E 0x1F - 0x25 0x26 - 0x30 0x31 - 0x3A 0x3B - 0x45 0x46 - 0x54 0x55 - 0x64 0x65 - 0x76 0x77 - 0x87 0x88 - 0x96 0x97 - 0xA4 0xA5 - 0xAF 0xB0 - 0xB7 0xB8 - 0xBF 0xC0 - 0xC9 0xCA - 0xD4 0xD5 - 0xDD 0xDE - 0xF0 0xF1 - 0xFF

ULT

Port1 Port2 Port3 Port4

Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port8

Lane 1~4 Lane 5 Lane 6

USB3.0

Right side 1 Left side (power share) Caldera

USB2.0

Right side 1 Left side (power share) Caldera

Touch screen Camera ELC BT

PCI EXPRESS

MUX for dGPU & Caldera WLAN(M.2 Card) 10/100/1000 LAN

Symbol Note :

: means Digital Ground

: means Analog Ground

CLOCK SIGNAL CLKOUT_PCIE0 CLKOUT_PCIE1 CLKOUT_PCIE2 CLKOUT_PCIE3 CLKOUT_PCIE4 CLKOUT_PCIE5

Lane 7~8 Lane 9~10

N16P-GX +Caldera

Lane 11~12

M.2 Card WLAN+BT Giga LAN M.2 NGFF SSD

SATA1

Thunderbolt

SATA2

M.2 NGFF SSD

SATA3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

M.2 SATA+PCIeX2 Alpine Ridge SP M.2 SATA+PCIeX2

SATA

HDD or SSD1SATA0 SSD2 SSD2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Notes list

Notes list LA-C901P

LA-C901P

4 63Tuesday, August 04, 2015

1.0

of

5

4

3

2

1

1K

D D

MEM_SMBCLK

R7

MEM_SMBDATA

R8

SKYLAKE ULT

C C

R9 W2

W3 V3

79 80

SOC_SML0CLK SOC_SML0DATA

SOC_SML1CLK

EC_SMB_CK2 EC_SMB_DA2

1K

2.2K

2.

1K

2.2K

+3V_PRIM

N-MOS N-MOS

+3VS

2K

CLK BUFFER

11 10

+3V_PRIM

N-MOS N-MOS

EC_SMB_CK2 EC_SMB_DA2SOC_SML1DATA

+3VS

KBC

B B

KB9022QD

77 78

EC_SMB_CK1 EC_SMB_DA1

2.2K

+3VALW_EC

10K

SOC_SMBCLK SOC_SMBDATA

N-MOS N-MOS

UF18

7

UF28

7

UF3

8

(On SSD/B)

7

0 ohm 0 ohm

+3VS

VGA_SMB_CK2 VGA_SMB_DA2T4T3

SMBUS Address [0x98]

SMBUS Address [0x9A]

SMBUS Address [0X98]

SCL SDA

1.8K

12 11

PU700 Charger

+3VS_VGA

UV1 GPU

SMBUS Address [0x12]

DIMMA

202 200

DIMMB

202 200

FFS

4 6

SMBUS Address [0x9E]

SMBUS Address [0x00]

SMBUS Address [0x01]

SMBUS Address [0x1D]

100 ohm 100 ohm

CLK_SMB DAT_SMB

EC_SMB_CK1 50 EC_SMB_DA1

0 ohm

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

0 ohm

TBTA_I2C_SCL1_R B5 TBTA_I2C_SDA1_R

2015/01/06 2016/01/06

PBATT1

7 6

PCI-E Re-Driver

49

Power Deliver

A5

Compal Secret Data

Deciphered Date

SMBUS Address [0x16]

SMBUS Address [RX:0xB2 / TX:0xB6]

SMBUS Address [0x70]

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SMBus block diagram

LA-C901P

1

1.0

of

5 63Tuesday, August 04, 2015

of

5 63Tuesday, August 04, 2015

of

5 63Tuesday, August 04, 2015

A

UC1

S IC A31 FJ8066201924932 QHMG C0 1.6G

SA00008M30L

1.6GES@

UC1

I5-6200U I7-6500U

1 1

S IC A31 FJ8066201930409 QJ8N D0 2.3G

SA000092O0L

i5QS@

UC1

I5-6200U I7-6500U

S IC A31 FJ8066201930409 QJKP D1 2.3G

SA000092O1L

i5QS'@

UC1

I5-6200U I7-6500U

S IC FJ8066201930409 SR2EY D1 2.3G A31!

SA000092O3L

i5R3@

+3VS

2 2

For BIOS Verify UMA/DIS SKU

1 2

RC212 10K_0402_5%

1 2

RC213 10K_0402_5%

UMA@ DIS@

DGPU_PRSNT#

GPP_E15

DIS,Optimus

UMA

UC1

S IC A31 FJ8066201924925 QHMF C0 2.3G

SA00008M40L

2.3GES@

UC1

S IC A31 FJ8066201930408 QJ8L D0 2.5G

SA000092P0L

i7QS@

UC1

S IC A31 FJ8066201930408 QJKK D1 2.5G

SA000092P1L

i7QS'@

UC1

S IC FJ8066201930408 SR2EZ D1 2.5G A31!

SA000092P3L

i7R3@

Pull High at TBT side

+1.0V_VCCST

+1.0VS_VCCSTG

DGPU_PRSNT#

0 1

Thunderbolt

+1.0VS_VCCIO

CAD note: Trace width=20 mils,Spacing=25mil,Max length=100mils

1 2

RC2 1K_0402_5%

1 2

RC3 1K_0402_5%

H_THERMTRIP#

H_PROCHOT#

RC1

SOC_DP1_CTRL_CLK<44> SOC_DP1_CTRL_DATA<44>

SOC_DP2_CTRL_CLK<44> SOC_DP2_CTRL_DATA<44>

1 2

B

SOC_DP1_N0<44> SOC_DP1_P0<44> SOC_DP1_N1<44> SOC_DP1_P1<44> SOC_DP1_N2<44> SOC_DP1_P2<44> SOC_DP1_N3<44> SOC_DP1_P3<44>

SOC_DP2_N0<44> SOC_DP2_P0<44> SOC_DP2_N1<44> SOC_DP2_P1<44> SOC_DP2_N2<44> SOC_DP2_P2<44> SOC_DP2_N3<44> SOC_DP2_P3<44>

24.9_0402_1%

H_PROCHOT#<41,51,52>

RC5 49.9_0402_1% RC6 49.9_0402_1% RC7 49.9_0402_1% RC8 49.9_0402_1%

SOC_DP1_CTRL_CLK SOC_DP1_CTRL_DATA

SOC_DP2_CTRL_CLK SOC_DP2_CTRL_DATA

EDP_COMP

T26 TP@

H_PECI<41>

1 2

RC4 499_0402_1%

T25 TP@ T16 TP@

T19 TP@ T10 TP@ T11 TP@

TS_INT# is not Used at Echo

PCH_TP_INT#<41>

T40 TP@

12 12 12 12

UC1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22

N12

GPP_E23

E52

EDP_RCOMP

H_CATERR# H_PECI H_PROCHOT#_R H_THERMTRIP# SOC_OCC#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3

DGPU_PRSNT# PCH_TP_INT#

SOC_GPIOB4

CPU_POPIRCOMP PCH_OPIRCOMP EDRAM_OPIO_RCOMP EOPIO_RCOMP

AT16 AU16

UC1D

D63 A54 C65 C63 A65

C55 D55 B54 C56

A6

A7 BA5 AY5

H66 H65

C

SKL-U

DDI

DISPLAY SIDEBANDS

1 OF 20

CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#

CPU MISC

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

EDP

SKL-U

4 OF 20

Rev_1.0

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP

RSVD

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

RSVD

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

L-U_BGA1356@

SK

Rev_1.0

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

JTAGX

L-U_BGA1356@

SK

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52 G50

F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

D

EDP_DISP_UTIL

SOC_DP1_HPD SOC_DP2_HPD HDMI_HPD EC_SCI# EDP_HPD

EDP_BKLTEN EDP_BKLT_PWM EDP_VDDEN

CPU_XDP_TCK0 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST#

PCH_JTAG_TCK1 SOC_XDP_TDI

SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST# CPU_XDP_TCK0

EDP_TXN0 <20> EDP_TXP0 <20> EDP_TXN1 <20> EDP_TXP1 <20>

EDP_AUXN <20> EDP_AUXP <20>

T9TP@

SOC_DP1_AUXN <44> SOC_DP1_AUXP <44> SOC_DP2_AUXN <44> SOC_DP2_AUXP <44>

T7TP@ T8TP@

SOC_DP1_HPD <44> SOC_DP2_HPD <44> HDMI_HPD <21> EC_SCI# <41> EDP_HPD <20>

EDP_BKLTEN <41> EDP_VDDEN <20>

SOC_XDP_TDO SOC_XDP_TDI SOC_XDP_TRST# CPU_XDP_TCK0

SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TRST# CPU_XDP_TCK0

eDP_FHD>

<

Thunderbolt

From dGPU

From eDP

12

RC10 0_0402_5%

As Short As Possible

1 2 1 2

CC64 0.1U_0402_16V7K@ESD@

1 2

CC65 0.1U_0402_16V7K@ESD@

1 2

CC69 0.1U_0402_16V7K@ESD@ CC70 0.1U_0402_16V7K@ESD@

EDP_TXN2 <20> EDP_TXP2 <20> EDP_TXN3 <20> EDP_TXP3 <20>

EDP_BIA_PWM <20>

EC_SCI# EDP_HPD EDP_VDDEN

E

RPC16

1 8 2 7 3 6 4 5

100K_8P4R_5%

<eDP_4K2K>

+3VS

+3V_PRIM

Change from +3VALW to +3V_PRIM to fix leakage on S5

APS CONN

3 3

PM_SLP_S3#<10,13,37,41> PM_SLP_S5#<10,37,41>

PM_SLP_S4#<10,13,37,41,54> PM_SLP_A#<10>

SOC_RTCRST#_R<10>

PBTN_OUT#<10,41> SYS_RESET#<10> PM_SLP_S0#<10,41>

4 4

+3VALW +3V_PRIM

A

JAPS1

1 2 3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19 20

ACES_50506-01841-P01

CONN@

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 GND GND

+1.0VS_VCCSTG

RC11 51_0402_5%CMC@ RC13 51_0402_5%CMC@ RC15 51_0402_5%CMC@

+1.0V_XDP

RC31 1K_0402_5%CMC@

RC32 1K_0402_5%@ RC43 0_0402_5%@ RC46 0_0402_5%@

RC35 51_0402_1%CMC@ RC37 51_0402_5%@

Place to CPU side

12 12 12

1 2 1 2

12 12

Place to CPU side

SOC_XDP_TMS SOC_XDP_TDI SOC_XDP_TDO

XDP_ITP_PMODE CFG0 XDP_PRSENT_CPU XDP_PRSENT_PCH

CPU_XDP_TCK0 PCH_JTAG_TCK1

B

XDP_SPI_IO2<8>

XDP_SPI_SI<8> XDP_ITP_PMODE<17>

EC_RSMRST#<10,41>

1 2

RC9 1K_0402_5%

SOC_XDP_TDO XDP_TDO SOC_XDP_TDI XDP_TDI SOC_XDP_TMS XDP_TMS CPU_XDP_TCK0 XDP_TCK0

SOC_XDP_TRST# PCH_JTAG_TCK1 CFG3 XDP_PRSENT_CPU XDP_SPI_IO2 XDP_PRSENT_PCH

XDP_SPI_SI XDP_ITP_PMODE

RC158 1K_0402_5%

CFG4

RC193 1K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

@

RPC2

1 8 2 7 3 6 4 5

0_0804_8P4R_5%

@

RPC4

1 8 2 7 3 6 4 5

0_0804_8P4R_5%

@

RPC15

1 8 2 7 3 6 4 5

0_0804_8P4R_5%

1 2

CMC@

1 2

C

XDP_SPI_SI

CFG0<17> CFG1<17> CFG2<17> CFG3<17>

XDP_TRST#

XDP_TCK1

XDP_HOOK3 XDP_HOOK6

XDP_HOOK0EC_RSMRST#

2015/01/06 2016/01/06

CFG4<17> CFG5<17> CFG6<17> CFG7<17>

CFG17<17> CFG16<17>

CFG8<17>

CFG9<17> CFG10<17> CFG11<17> CFG12<17> CFG13<17> CFG14<17> CFG15<17>

CFG19<17> CFG18<17>

Compal Secret Data

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7

CFG17 CFG16

CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG19 CFG18

Deciphered Date

PRIMARY CMC CONN

+1.0V_XDP+1.0V_PRIM

1 2

RC12 0_0603_1%@

T37TP@ T38TP@

T47TP@ T48TP@ T49TP@

T50TP@ T51TP@

T52TP@ T53TP@ T54TP@ T55TP@ T56TP@ T57TP@ T58TP@ T59TP@

T60TP@ T61TP@

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

T13 TP@ T20 TP@ T21 TP@ T24 TP@ T27 TP@ T28 TP@

T29 TP@ T30 TP@

T31 TP@ T32 TP@ T33 TP@

Compal Electronics, Inc.

SKL-U(1/12)DDI,MSIC,XDP,EDP

XDP_TRST# XDP_TDI XDP_TMS XDP_TCK0 XDP_TCK1 XDP_TDO

XDP_PREQ# XDP_PRDY#

XDP_HOOK0 XDP_HOOK3 XDP_HOOK6

LA-C901P

XDP_PREQ# <12> XDP_PRDY# <12>

of

6 63Tuesday, August 04, 2015

of

6 63Tuesday, August 04, 2015

of

E

6 63Tuesday, August 04, 2015

1.0

5

4

3

2

1

Non-Interleaved Memory

D D

DDR_A_D[0..15]<18>

DDR_A_D[32..47]<18>

C C

DDR_B_D[0..15]<19>

DDR_B_D[32..47]<19>

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47

UC1B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

Interleave / Non-Interleaved

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKL-U

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR3L / LPDDR3 / DDR4

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

Interleave / Non-Interleaved

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_ALERT#

DDR CH - A

2 OF 20

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

SK

Rev_1.0

DDR0_MA[3] DDR0_MA[4]

DDR0_PAR

L-U_BGA1356@

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54 AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50

BA50 BB52 AM70 AM69 AT69 AT70

BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26

AW50 AT52

AY67 AY68 BA67

AW67

DDR_A_CLK#0 DDR_A_CLK0 DDR_A_CLK#1 DDR_A_CLK1

DDR_A_CKE0 DDR_A_CKE1

DDR_A_CS#0 DDR_A_CS#1 DDR_A_ODT0 DDR_A_ODT1

DDR_A_MA5 DDR_A_MA9 DDR_A_MA6 DDR_A_MA8 DDR_A_MA7 DDR_A_BS2 DDR_A_MA12 DDR_A_MA11 DDR_A_MA15 DDR_A_MA14 DDR_A_MA13 DDR_A_CAS# DDR_A_WE# DDR_A_RAS# DDR_A_BS0 DDR_A_MA2 DDR_A_BS1 DDR_A_MA10 DDR_A_MA1 DDR_A_MA0

DDR_A_MA3 DDR_A_MA4 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1

DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5

+0.675V_VREFCA +0.675V_A_VREFDQ +0.675V_B_VREFDQ

T14TP@

T22TP@

+0.675V_VREFCA +0.675V_A_VREFDQ +0.675V_B_VREFDQ

DDR_A_CLK#0 <18> DDR_A_CLK0 <18> DDR_A_CLK#1 <18> DDR_A_CLK1 <18>

DDR_A_CKE0 <18> DDR_A_CKE1 <18>

DDR_A_CS#0 <18> DDR_A_CS#1 <18> DDR_A_ODT0 <18> DDR_A_ODT1 <18>

DDR_A_MA5 <18> DDR_A_MA9 <18> DDR_A_MA6 <18> DDR_A_MA8 <18> DDR_A_MA7 <18> DDR_A_BS2 <18> DDR_A_MA12 <18> DDR_A_MA11 <18> DDR_A_MA15 <18> DDR_A_MA14 <18> DDR_A_MA13 <18> DDR_A_CAS# <18> DDR_A_WE# <18> DDR_A_RAS# <18> DDR_A_BS0 <18> DDR_A_MA2 <18> DDR_A_BS1 <18> DDR_A_MA10 <18> DDR_A_MA1 <18> DDR_A_MA0 <18>

DDR_A_MA3 <18> DDR_A_MA4 <18> DDR_A_DQS#0 <18> DDR_A_DQS0 <18> DDR_A_DQS#1 <18> DDR_A_DQS1 <18>

DDR_A_DQS#4 <18> DDR_A_DQS4 <18> DDR_A_DQS#5 <18> DDR_A_DQS5 <18> DDR_B_DQS#0 <19> DDR_B_DQS0 <19> DDR_B_DQS#1 <19> DDR_B_DQS1 <19> DDR_B_DQS#4 <19> DDR_B_DQS4 <19> DDR_B_DQS#5 <19> DDR_B_DQS5 <19>

DDR_A_D[16..31]<18>

DDR_A_D[48..63]<18>

DDR_B_D[16..31]<19>

DDR_B_D[48..63]<19>

Trace width/Spacing >= 20mils

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31

DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

UC1C

Interleave / Non-Interleaved

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKL-U

DDR3L / LPDDR3 / DDR4

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

Interleave / Non-Interleaved

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

3 OF 20

Rev_1.0

DDR1_CKN[0] DDR1_CKN[1]

DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6]

DDR1_DQSP[6]

DDR1_DQSN[7]

DDR1_DQSP[7] DDR1_ALERT#

DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

L-U_BGA1356@

SK

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52 BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46

BB46 BA47

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32

AR25 AR27 AR22 AR21 AN43 AP43 AT13 AR18 AT18 AU18

DDR_B_CLK#0 DDR_B_CLK#1 DDR_B_CLK0 DDR_B_CLK1

DDR_B_CKE0 DDR_B_CKE1

DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0 DDR_B_ODT1

DDR_B_MA5 DDR_B_MA9 DDR_B_MA6 DDR_B_MA8 DDR_B_MA7 DDR_B_BS2 DDR_B_MA12 DDR_B_MA11 DDR_B_MA15 DDR_B_MA14 DDR_B_MA13 DDR_B_CAS# DDR_B_WE# DDR_B_RAS# DDR_B_BS0 DDR_B_MA2 DDR_B_BS1 DDR_B_MA10 DDR_B_MA1 DDR_B_MA0

DDR_B_MA3 DDR_B_MA4

DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3

DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7

DDR_DRAMRST #

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

DDR_B_CLK#0 <19> DDR_B_CLK#1 <19> DDR_B_CLK0 <19> DDR_B_CLK1 <19>

DDR_B_CKE0 <19>

DDR_B_CKE1 <19>

T17TP@ T18TP@T15TP@

DDR_B_CS#0 <19>

DDR_B_CS#1 <19>

DDR_B_ODT0 <19>

DDR_B_ODT1 <19>

DDR_B_MA5 <19>

DDR_B_MA9 <19>

DDR_B_MA6 <19>

DDR_B_MA8 <19>

DDR_B_MA7 <19>

DDR_B_BS2 <19>

DDR_B_MA12 <19>

DDR_B_MA11 <19>

DDR_B_MA15 <19>

DDR_B_MA14 <19>

DDR_B_MA13 <19>

DDR_B_CAS# <19>

DDR_B_WE# <19>

DDR_B_RAS# <19>

DDR_B_BS0 <19>

DDR_B_MA2 <19>

DDR_B_BS1 <19>

DDR_B_MA10 <19>

DDR_B_MA1 <19>

DDR_B_MA0 <19>

DDR_B_MA3 <19>

DDR_B_MA4 <19>

DDR_A_DQS#2 <18>

DDR_A_DQS2 <18>

DDR_A_DQS#3 <18>

DDR_A_DQS3 <18>

DDR_A_DQS#6 <18>

DDR_A_DQS6 <18>

DDR_A_DQS#7 <18>

DDR_A_DQS7 <18>

DDR_B_DQS#2 <19>

DDR_B_DQS2 <19>

DDR_B_DQS#3 <19>

DDR_B_DQS3 <19>

DDR_B_DQS#6 <19>

DDR_B_DQS6 <19>

DDR_B_DQS#7 <19>

DDR_B_DQS7 <19>

T23TP@

DDR_DRAMRST # <18,19>

1 2

RC38 121_0402_1%

1 2

RC39 80.6_0402_1%

1 2

RC40 100_0402_1%

Buffer with Open Drain Output

For VTT power control

+3VALW

+1.35V_VDDQ +3VS

12

DDR_PG_CTRL

CC570.1U_0201_10V6K

UC7

NC1VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

12

5

4

Y

RC123

100K_0402_5%

@

12

RC129

100K_0402_5%

0.675V_DDR_VTT_ON <54>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Custom Date: Sheet

Date: Sheet

2

Date: Sheet

SKL-U(2/12)DDRIII

LA-C901P

Tuesday, August 04, 2015

1

1.0

63

of

7

of

7

of

7

5

SOC_SMBALERT# SOC_SML0ALERT#

TLS CONFIDENTIALITY

HIGH LOW(DEFAULT)

UC1E

AV2

SPI0_CLK

AW3

SPI0_MISO

AV3

SPI0_MOSI

AW2

SPI0_IO2

AU4

SPI0_IO3

AU3

SPI0_CS0#

AU2

SPI0_CS1#

AU1

SPI0_CS2#

M2

GPP_D1/SPI1_CLK

M3

GPP_D2/SPI1_MISO

J4

GPP_D3/SPI1_MOSI

V1

GPP_D21/SPI1_IO2

V2

GPP_D22/SPI1_IO3

M1

GPP_D0/SPI1_CS#

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

AW13

GPP_A0/RCIN#

AY11

GPP_A6/SERIRQ

CMC@ CMC@

O2 pin for CMC

12 12

SOC_SPI_CLK SOC_SPI_SO SOC_SPI_SI SOC_SPI_IO2 SOC_SPI_IO3 SOC_SPI_CS#0 SOC_SPI_CS#1

FFS_INT1 FFS_INT2

EC_KBRST# SERIRQ

SERIRQ

SOC_SPI_SI SOC_SPI_IO2

C21/44 place to within 1100 mil of SPIO_MOSI/SPI0_I

R

XDP_SPI_SI<6> XDP_SPI_IO2<6>

+3VS

D D

RC32410K_0402_5% RC32510K_0402_5% RC32610K_0402_5% @

C C

+3VS

LPC Mode

12 12 12

FFS_INT2 FFS_INT1 EC_KBRST#

RC44 1K_0402_1% RC21 1K_0402_1%

T41 TP@

FFS_INT1<36> FFS_INT2<36>

T42 TP@ T43 TP@ T44 TP@

EC_KBRST#<41>

SERIRQ<41>

12

RC1228.2K_0402_5%

Follow 543016_SKL_U_Y_PDG_0_9

B B

SPI - FLASH

SPI - TOUCH

C LINK

4

EC interface

ENABLE DISABLE

SKL-U

LPC

5 OF 20

HIGH LOW(DEFAULT)

SMBUS, SMLINK

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

ESPI LPC

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

MEM_SMBCLK

MEM_SMBDATA

3

----->For KB9032 Only.

----->For KB9022/9032 Use

Rev_1.0

R7

MEM_SMBCLK

R8

MEM_SMBDATA

R10

SOC_SMBALERT#

R9

SOC_SML0CLK

W2

SOC_SML0DATA

W1

SOC_SML0ALERT#

W3

SOC_SML1CLK

V3

SOC_SML1DATA

AM7

SOC_SML1ALERT# SOC_SML1ALERT#

AY13

ESPI_IO0

BA13

ESPI_IO1

BB13

ESPI_IO2

AY12

ESPI_IO3

BA12

ESPI_CS#

BA11

SUS_STAT#

AW9

ESPI_CLK

AY9 AW11

PM_CLKRUN#

L-U_BGA1356@

SK

SMB Bus : DDR/WLAN/FFS

2

G

6 1

S

D

5

DMN66D0LDW-7_SOT363-6

3 4

SGD

QC3A

DMN66D0LDW-7_SOT363-6

LPC@

1 2

RC45 22_0402_5%

RC66

10K_0402_5%

QC3B

2

SML1 Bus : EC/dGPU/THERMAL

SOC_SML1CLK

SOC_SML1DATA

SMB -> DDR , WLAN , FFS SML0 -> PCIE CLK BUFFER

SOC_SML0CLK <34> SOC_SML0DATA <34>

RC202 4.7K_0402_5%

12

SML1 -> EC , dGPU , THERMAL , TBT

To EC

ESPI_CS# <41>

ESPI_CLK_R <41>

PM_CLKRUN# <41>

SUS_STAT#

+3VS+3VS

12

RC67 10K_0402_5%

SOC_SMBCLK <18,19,36>

SOC_SMBDATA <18,19,36>

SOC_SMBALERT#

MEM_SMBCLK MEM_SMBDATA SOC_SML1CLK SOC_SML1DATA

ESPI_IO0 ESPI_IO0_R ESPI_IO2 ESPI_IO2_R ESPI_IO1 ESPI_IO1_R ESPI_IO3

To EC

For TPM

1 2

@

RC36 10K_0402_5%

+3VS

2

G

6 1

S

D

QC2B

DMN66D0LDW-7_SOT363-6

1 2

RC130 8.2K_0402_5%

RPC12

1 8 2 7 3 6 4 5

1K_0804_8P4R_5%

RPC8

1 8 2 7 3 6 4 5

ESPI_IO3_R

0_0804_8P4R_5%

LPC@

+3V_PRIM

*****ONLY***** From WW36 MOW for SKL-U ES sample

1

5

3 4

SGD

QC2A

DMN66D0LDW-7_SOT363-6

+3V_PRIM

ESPI_IO0_R <41> ESPI_IO2_R <41> ESPI_IO1_R <41> ESPI_IO3_R <41>

RC45

15_0402_5%

ESPI@

EC_SMB_CK2 <22,40,41,46>

EC_SMB_DA2 <22,40,41,46>

1 2

RC41 150K_0402_1%@

ESPI / LPC Bus

ESPI : +1.8V LPC : +3.3V

RPC8

15_0804_8P4R_5%

ESPI@

Echo MLK use LPC

Reserve For EC Auto Load Code

SOC_SPI_IO2 SOC_SPI_IO3 SOC_SPI_CS#0 SOC_SPI_IO3

PM_CLKRUN#

1 2

RC47 1K_0402_1%@

1 2

RC48 1K_0402_1%@

1 2

RC53 1K_0402_1%@

1 2

RC51 1K_0402_1%@

1 2

RC107 8.2K_0402_5%

Follow TD team

+3VS

+3V_SPI

+3VS

Single SPI ROM_CS0#

To SPI ROM

A A

5

RPC5 and RC52 are close UC2

RPC5

1 8 2 7 3 6 4 5

SOC_SPI_SOSOC_SPI_SO_0_R SOC_SPI_SISOC_SPI_SI_0_R SOC_SPI_CLKSOC_SPI_CLK_0_R SOC_SPI_IO3SOC_SPI_IO3_0_R

15_0804_8P4R_5%

RC52

12

SOC_SPI_IO2SOC_SPI_IO2_0_R

15_0402_5%

16M SPI ROM(Support ISH)

UC2

SOC_SPI_CS#0 SOC_SPI_IO2_0_R

4

1

/CS

2

DO(IO1)

3 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

/HOLD(IO3) /WP(IO2) GND

W25Q128FVSIQ_SO8

+3V_SPI

1 2

CC8 0.1U_0201_10V6K

8

VCC

7

SOC_SPI_IO3_0_RSOC_SPI_SO_0_R

6

SOC_SPI_CLK_0_R

CLK

5

DI(IO0)

SOC_SPI_SI_0_R

2015/01/06 2016/01/06

3

1 2

CC9 10P_0402_50V8J

@EMI@

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(3/12)SPI,ESPI,SMB,LPC

Size Document Number Rev

LA-C901P

Date: Sheet

2

Date: Sheet

1

of

8 63Tuesday, August 04, 2015

of

8 63Tuesday, August 04, 2015

of

8 63Tuesday, August 04, 2015

1.0

5

4

3

2

1

#545659 SKL_PCH_EDS_R0.7 P.84

HDA for AUDIO

RPC9

CC53

UC1I

CSI-2

CSI2_DN0 CSI2_DP0 CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3

CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7

CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11

1 8 2 7 3 6 4 5

1

2

D D

HDA_BIT_CLK_R<31> HDA_RST#_R<31> HDA_SDOUT_R<31> HDA_SYNC_R<31>

HDA_SDIN0<31>

Functional Strap Definitions

SPKR / GPP_B14 (Internal Pull Down): (Sampled:Rising edge of PCH_PWROK)

TOP Swap Override 0 = Disable TOP Swap mode. -->AAX05 use 1 = Enable TOP Swap Mode.

TOP Swap Override

C C

+3VS

1 2

RC117 2.2K_0402_5%@

B B

SPKR

22P_0402_50V8J

Close to RPC9

A36 B36 C38 D38 C36 D36 A38 B38

C31 D31 C33 D33 A31 B31 A33 B33

A29 B29 C28 D28 A27 B27 C27 D27

HDA_BIT_CLK HDA_RST# HDA_SDOUT HDA_SYNC

33_0804_8P4R_5%

HDA_SDIN0

HDA_BIT_CLK_R

SKL-U

9 OF 20

SPKR<31>

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F12/EMMC_CMD

HDA_SYNC HDA_BIT_CLK HDA_SDOUT HDA_SDIN0

HDA_RST#

SPKR

Rev_1.0

CSI2_CLKN0

CSI2_CLKP0

CSI2_CLKN1

CSI2_CLKP1

CSI2_CLKN2

CSI2_CLKP2

CSI2_CLKN3

CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

GPP_F22/EMMC_CLK

EMMC_RCOMP

L-U_BGA1356@

SK

To Enable ME Override

TD Team Solution A

+3V_PRIM

C37 D37 C32 D32 C29 D29 B26 A26

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

UC1G

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

1 2

RC77 1K_0402_1%

CSI2_COMP

EMMC_RCOMP

RC80 100_0402_1%

RC89 200_0402_1%

AUDIO

ME_EN<9,41>

SKL-U

GPP_A17/SD_PWR_EN#/ISH_GP7

7 OF 20

eserve RC229 follow TD team dat.04/23

R

1 2

@

RC229 100K_0402_5%

2

G

12

1 3

QC1 BSS138W -7-F_SOT323-3

HDA_SDOUT

D

S

Rev_1.0

SDIO / SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

L-U_BGA1356@

SK

BO Solution

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

SD_RCOMP

AF13

ME_EN<9,41>

RC76 200_0402_1%

1 2

@

RC313 0_0402_5%

12

HDA_SDOUT

A A

Security Classification

2015/01/06 2016/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(4/12)HDA,EMMC,SDIO,CSI2

Size Document Number Rev

LA-C901P

Date: Sheet

Tuesday, August 04, 2015

2

Tuesday, August 04, 2015

1

of

9

of

9

of

9

1.0

63

5

DGPU

NGFF WALN+BT

D D

NG

LAN

FF SSD

Thunderbolt

NGFF SSD

+3VS

1 2

RC105 10K_0402_5%

RPC10

18 27

C C

From 545659_SKL_PCH_U_Y_EDS_R0_7

+3VALW _DSW

+3V_PRIM

CLRP3 SHORT PADS RC101 100K_0402_5%

+3VALW _DSW

B B

RC108 10K_0402_5%

36 45

10K_0804_8P4R_5%

RPC11

18 27 36 45

10K_0804_8P4R_5%

12

1 2

CLKREQ_PCIE#5

CLKREQ_PCIE#1 CLKREQ_PCIE#2 CLKREQ_PCIE#3 CLKREQ_PCIE#0

From 543016_SKL_PDG_UY_v1.0

PCH_PW ROK

LAN_WAKE#

EC_RSMRST#

SYS_RESET#

SYS_RESET# PCH_DPW ROK

WAKE_PCH#_R

CLK_PCIE_N0<34> CLK_PCIE_P0<34>

CLKREQ_PCIE#0<22,34> CLK_PCIE_N1<32>

CLK_PCIE_P1<32> CLKREQ_PCIE#1<32>

CLK_PCIE_N2<30> CLK_PCIE_P2<30> CLKREQ_PCIE#2<30>

CLK_PCIE_N3<36> CLK_PCIE_P3<36>

CLKREQ_PCIE#3<36>

CLK_PCIE_N4<44> CLK_PCIE_P4<44>

CLKREQ_PCIE#4<44>

CLK_PCIE_N5<36> CLK_PCIE_P5<36>

CLKREQ_PCIE#5<36>

XCLK_BIASREF

Follow 546765_2014WW48_Skylake_MOW_Rev_1_0 Stuff 2.7k ohm(RC96) PH for Skylake U Stuff 60.4 ohm(RC124) PD for Cannonlake U

EC_VCCST_PG H_CPUPWRGD SYS_RESET#

H_CPUPW RGD SYS_RESET#

100P_0402_50V8J

@ESD@

A A

VR_ON_EC<41>

For meet tPLT17 & tCPU28 power down sequence. tPLT17 : 1us (Max) tCPU28 : 1us (Max)

CC60

1

2

0.1U_0201_10V6K

PM_SLP_S3#

As Short As Possible

1

CC63

0.1U_0402_16V7K

@ESD@

2

+3V_PRIM

CC83

1 2

UC9

5

TC7SH08FU_SSOP5~D

1

P

B

4

O

2

A

G

3

1 2

@

RC127 0_0402_5%

5

SYS_RESET#<6>

EC_RSMRST#<6,41>

T95 TP@

Only For Power Sequence Debug

SYS_PWROK<41>

PCH_PW ROK<41>

DPWROK_EC<41>

SUSWARN#<41>

SUSACK#<41>

WAKE_PCH#<41>

VR_ON <58>

H_CPUPW RGD_R

EC_RSMRST#

1K_0402_5%

VCCST_PG_EC<41>

4

UC1J

CLK_PCIE_N0 CLK_PCIE_P0

CLKREQ_PCIE#0

CLK_PCIE_N1 CLK_PCIE_P1

CLKREQ_PCIE#1

CLK_PCIE_N2 CLK_PCIE_P2

CLKREQ_PCIE#2

CLK_PCIE_N3 CLK_PCIE_P3

CLKREQ_PCIE#3

CLK_PCIE_N4 CLK_PCIE_P4

CLKREQ_PCIE#4

CLK_PCIE_N5 CLK_PCIE_P5

CLKREQ_PCIE#5

RC102 1K_0402_5%@

RC112 0_0402_1% RC114 0_0402_5%

RC110 0_0402_1% RC100 1K_0402_5% RC68 0_0402_1%

+1.0V_VCCST

RC113

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

1 2

RC96 2.7K_0402_1%

1 2

RC124 60.4_0402_1%@

1 2

@

1 2

@

1 2

@

1 2

@

1 2

@

12

From EC(open-drain)

RC116

1 2

60.4_0402_1%

4

EC_VCCST_PG

1

CC54 100P_0402_50V8J

@ESD@

2

3

SKL-U

CLOCK SIGNALS

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

10 OF 20

+1.0V_CLK5_F24NS

SOC_SRTCRST#

CLR ME

SOC_RTCRST#

CL

SM_INTRUDER#

PCH PLTRST Buffer

SOC_PLTRST#<22,34>

SOC_PLTRST# SYS_RESET# EC_RSMRST#

H_CPUPW RGD EC_VCCST_PG

SYS_PWROK PCH_PW ROK PCH_DPW ROK

SUSWARN# SUSACK#_R

WAKE_PCH#_R LAN_WAKE#

T92 TP@ T94 TP@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SOC_PLTRST#

RC99 0_0402_5%@

UC1K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SYSTEM POWER MANAGEMENT

3

Rev_1.0

F43

CLK_CPU_ITP#

E43

CLK_CPU_ITP

BA17

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

L-U_BGA1356@

SK

R CMOS

+3VS

5

UC3

1

P

B

2

A

G

TC7SH08FU_SSOP5~D

3

1 2

2015/01/06 2016/01/06

SUSCLK

E37

SOC_XTAL24_IN

E35

SOC_XTAL24_OUT

E42

XCLK_BIASREF

AM18

SOC_RTCX1

AM20

SOC_RTCX2

AN18

SOC_SRTCRST#

AM16

SOC_RTCRST#

CC14

1 2

0.1U_0201_10V6K

4

O

SKL-U

11 OF 20

Compal Secret Data

RC104 0_0201_1%

12 12 12

CLRP1SHORT PADS

12 12 12

CLRP2SHORT PADS

12

RC941M_0402_5%

GPP_B11/EXT_PWR_GATE#

Deciphered Date

T89TP@ T90TP@

SUSCLK <32,36>

1 2

@

+3VL_RTC

RC9120K_0402_5% CC101U_0402_6.3V6K

RC9320K_0402_5% CC111U_0402_6.3V6K

PLT_RST# <30,32,36,41,44>

Rev_1.0

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B2/VRALERT#

L-U_BGA1356@

SK

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

AM10 AM11

2

**Avoid Sub-trace**

Closed to CPU

SOC_XTAL24_IN

SOC_XTAL24_OUT

SOC_RTCRST#_R <6>

Closed to CPU

SOC_RTCX2

SOC_RTCX1

PM_SLP_S0# PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#

SLP_SUS# SLP_LAN# SLP_WLAN# PM_SLP_A#

PBTN_OUT#_R AC_PRESENT_R PM_BATLOW#

SM_INTRUDER# EXT_PW R_GATE#

SOC_VRALERT#

2

RC109 0_0402_1%@

1

XTAL@

GND

1

2

4

3

1 2

CC13

YC1

XTAL@

24MHZ_12PF_7V24000020

XTAL@

1 2

CC1215P_0402_50V8J

RC92

1M_0402_5%

XTAL@

15P_0402_50V8J

1 2

**Avoid Sub-trace**

XTAL@

1 2

CC164.7P_0402_50V8C

RC98

10M_0402_5%

XTAL@

SOC_VRALERT#

PM_BATLOW# AC_PRESENT_R PBTN_OUT#_R

T87

TP@

T88TP@

1 2

12

DC2 RB751V-40_SOD323-2

T91

TP@

Compal Electronics, Inc.

Title

SKL-U(5/12)CLK,GPIO

Size Document Number Rev

LA-C901P

Date: Sheet

YC2

32.768KHZ 9PF 20PPM 9H03280012

1 2

XTAL@

1 2

CC154.7P_0402_50V8C

XTAL@

12

RC11510K_0402_5% @

+3VALW _DSW

12

RC1038.2K_0402_5%

12

1 2

RC10610K_0402_5% RC111100K_0402_5% @

PM_SLP_S0# <6,41> PM_SLP_S3# <6,13,37,41> PM_SLP_S4# <6,13,37,41,54> PM_SLP_S5# <6,37,41>

SLP_SUS# <14,41>

PM_SLP_A# <6>

PBTN_OUT# <6,41> ACIN <22,37,41,51,52> PM_BATLOW# <44>

EXT_PW R_GATE# <14>

1

+3V_PRIM

Follow Echo

of

10 63Tuesday, August 04, 2015

of

10 63Tuesday, August 04, 2015

of

10 63Tuesday, August 04, 2015

1.0

5

+3VS

RC203 10K_0402_5% RC205 10K_0402_5%

RC62 49.9K_0402_1% RC63 49.9K_0402_1%

D D

RC126 8.2K_0402_5%

C C

12 12

RPC7

18

I2C_1_SDA

27

I2C_1_SCL

36

I2C_0_SDA

45

I2C_0_SCL

10K_0804_8P4R_5%

12

WL_OFF#

@

PD_PWR_EN<41,46>

C10 for GC6_EVENT#

nsor

Se

Touch PAD/Panel

SOC_GPIOB21 EC_SMI#

UART_2_CRXD_DTXD UART_2_CTXD_DRXD

Echo13

RTD3_CIO_PWR_EN<44> RTD3_USB_PWR_EN<44>

B17 for GPU_GC6_FB_EN

PCIE_SEL<34>

WL_OFF#<32>

1 2

RC128 0_0201_5%

BT_OFF#<32>

UART_2_CRXD_DTXD<32> UART_2_CTXD_DRXD<32>

EC_SMI#<41>

TBT_CIO_PLUG_EVENT#<44>

I2C_1_SDA<38> I2C_1_SCL<38>

RTD3_CIO_PWR_EN RTD3_USB_PWR_EN SOC_GPIOB17 GSPI0_MOSI

PCIE_SEL SOC_GPIOB21 GSPI1_MOSI

WL_OFF#

@

PD_PWR_EN_R SOC_GPIOC10 BT_OFF#

UART_2_CRXD_DTXD UART_2_CTXD_DRXD EC_SMI# TBT_CIO_PLUG_EVENT#

I2C_0_SDA I2C_0_SCL

I2C_1_SDA I2C_1_SCL

NFC

Unus

ed

Unused

+3V_PRIM

4

RC207 100K_0402_5%@

AN8 AP7 AP8 AR7

AM5

AN7 AP5 AN5

AB1 AB2

W4

AB3 AD1

AD2 AD3 AD4

U7 U6

U8 U9

AH9

AH10 AH11

AH12 AF11

AF12

12

UC1F

GPP_B15/GSPI0_CS# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL

LPSS ISH

RTD3_USB_PWR_EN

SKL-U

3

VGA_ID

RANK_ID

VGA_ID

GL GM

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6

6 OF 20

GPP_D9

0 1

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_D15/ISH_UART0_RTS#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

+3V_1.8V_PGPPD +3V_1.8V_PGPPD

1 2

RC321 10K_0402_5%@

1 2

RC316 10K_0402_5%

1 2

RC320 10K_0402_5%SR@

1 2

RC317 10K_0402_5%DR@

RANK_ID

DR SR

GPP_D9 GPP_D10 GPP_D11 GPP_D12

L-U_BGA1356@

SK

Rev_1.0

GPP_D10

P2

VGA_ID

P3

RANK_ID

P4

PROJECT_ID0

P1

PROJECT_ID1

M4

ISH_I2C_0_SDA

N3

ISH_I2C_0_SCL

N1

ISH_I2C_1_SDA

N2

ISH_I2C_1_SCL

AD11

I2C_5_SDA

AD12

I2C_5_SCL

U1

SOC_GPIOD13

U2

SOC_GPIOD14

U3

SOC_GPIOD15

U4

SOC_GPIOD16

AC1

DGPU_PW R_EN

AC2

DGPU_HOLD_RST#

AC3

SOC_GPIOC14

AB4

SOC_GPIOC15

AY8

SOC_GPIOA18

BA8

SOC_GPIOA19

BB7

SOC_GPIOA20

BA7

SOC_GPIOA21

AY7

SOC_GPIOA22

AW7

SOC_GPIOA23

AP13

SOC_GPIOA12

0 1

2

T111 TP@ T112 TP@

T104 TP@ T103 TP@

T105 TP@ T106 TP@

T107 TP@ T108 TP@ T109 TP@ T110 TP@

T254 TP@ T256 TP@

T250 TP@ T251 TP@ T252 TP@ T253 TP@ T255 TP@ T120 TP@ T122 TP@

PROJECT_ID0

PROJECT_ID1

Project ID

*

Project code Reserved Reserved Reserved

Unused

RC318 10K_0402_5%@ RC315 10K_0402_5%

RC314 10K_0402_5%@ RC319 10K_0402_5%

DGPU_PW R_EN <24> DGPU_HOLD_RST# <22>

1

12

1 2

12

1 2

Project_ID0Project_ID1

GPP_D11GPP_D12 0 0 1

0 1 0

1 1

I2C for ISH sensor HUB

B B

Strap Pin

+3VS

RC118 2.2K_0402_5%@ RC201 2.2K_0402_5%@

1 2 1 2

GSPI0_MOSI GSPI1_MOSI

GSPI0_MOSI (Internal Pull Down): No Reboot 0 = Disable No Reboot mode. --> AAX05 Use 1 = Enable No Reboot Mode. (PCH will disable the TCO

Timer system reboot feature). This function is useful when running ITP/XDP.

GSPI1_MOSI (Internal Pull Down):

TO DGPU

Boot BIOS Strap Bit

A A

0 = SPI Mode --> AAX05 Use

ForGC62.0

SOC_GPIOC10 SOC_GPIOB17 GPU_GC6_FB_EN

1 2

RC204 0_0402_1%@

1 2

RC195 0_0402_1%@

GC6_EVENT#

GC6_EVENT# <22> GPU_GC6_FB_EN <22,25>

1 = LPC Mode--> AAP01 Use

Security Classification

2015/01/06 2016/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(6/12)GPIO

Size Document Number Rev

LA-C901P

Date: Sheet

2

Date: Sheet

1

of

11 63Tuesday, August 04, 2015

of

11 63Tuesday, August 04, 2015

of

11 63Tuesday, August 04, 2015

1.0

5

PCIE_CRX_GTX_N1<34> PCIE_CRX_GTX_P1<34>

PCIE_CTX_C_GRX_N1<34> PCIE_CTX_C_GRX_P1<34>

PCIE_CRX_GTX_N2<34> PCIE_CRX_GTX_P2<34>

PCIE_CTX_C_GRX_N2<34>

D D

**** Swap Port **** Follow Customer design (Different with TD Team)

For selected technology

lease use 100nF for PCIe Gen3.

p please use 10nF for SATA.

C C

For selected technology p

lease use 220nF for PCIe Gen3.

please use 10nF for SATA.

S

ATA Express

SATA Express

DGPU

(x4 Lane)

NGFF WLAN+BT

LAN

HDD

ThunderBolt

PCIE_CTX_C_GRX_P2<34>

PCIE_CRX_GTX_N3<34> PCIE_CRX_GTX_P3<34>

PCIE_CTX_C_GRX_N3<34> PCIE_CTX_C_GRX_P3<34>

PCIE_CRX_GTX_N4<34> PCIE_CRX_GTX_P4<34>

PCIE_CTX_C_GRX_N4<34> PCIE_CTX_C_GRX_P4<34>

PCIE_CRX_DTX_N5<32> PCIE_CRX_DTX_P5<32> PCIE_CTX_DRX_N5<32> PCIE_CTX_DRX_P5<32>

PCIE_CRX_DTX_N6<30> PCIE_CRX_DTX_P6<30> PCIE_CTX_C_DRX_N6<30> PCIE_CTX_C_DRX_P6<30>

SATA_CRX_DTX_N0<36> SATA_CRX_DTX_P0<36> SATA_CTX_DRX_N0<36> SATA_CTX_DRX_P0<36>

SATA_CRX_DTX_N1<36> SATA_CRX_DTX_P1<36> SATA_CTX_DRX_N1<36> SATA_CTX_DRX_P1<36>

PCIE_CRX_DTX_N9<44> PCIE_CRX_DTX_P9<44> PCIE_CTX_DRX_N9<44> PCIE_CTX_DRX_P9<44>

PCIE_CRX_DTX_N10<44> PCIE_CRX_DTX_P10<44> PCIE_CTX_DRX_N10<44> PCIE_CTX_DRX_P10<44>

XDP_PRDY#<6>

XDP_PREQ#<6>

PCIE_CRX_DTX_N11<36> PCIE_CRX_DTX_P11<36> PCIE_CTX_DRX_N11<36> PCIE_CTX_DRX_P11<36> PCIE_CRX_DTX_N12<36> PCIE_CRX_DTX_P12<36> PCIE_CTX_DRX_N12<36> PCIE_CTX_DRX_P12<36>

Follow 545659_SKL_PCH_LP_EDS_Rev1_0

B B

4

1 2

CC17 0.22U_0402_16V7KDIS@

1 2

CC21 0.22U_0402_16V7KDIS@

1 2

CC18 0.22U_0402_16V7KDIS@

1 2

CC19 0.22U_0402_16V7KDIS@

1 2

CC20 0.22U_0402_16V7KDIS@

1 2

CC22 0.22U_0402_16V7KDIS@

1 2

CC23 0.22U_0402_16V7KDIS@

1 2

CC24 0.22U_0402_16V7KDIS@

1 2

CC25 0.1U_0402_10V7K

1 2

CC26 0.1U_0402_10V7K

1 2

RC120 100_0402_1%

hen PCIE8/SATA1A is used

W as SATA Port 1 (ODD), then PCIE11/SATA1B (M.2 SSD) cannot be used as SATA Port 1.

PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P1 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P1

PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P2

PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P3

PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P4 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P4

PCIE_CRX_DTX_N5 PCIE_CRX_DTX_P5 PCIE_CTX_DRX_N5 PCIE_CTX_DRX_P5

PCIE_CRX_DTX_N6 PCIE_CRX_DTX_P6 PCIE_CTX_DRX_N6 PCIE_CTX_DRX_P6

PCIE_CRX_DTX_N9 PCIE_CRX_DTX_P9 PCIE_CTX_DRX_N9 PCIE_CTX_DRX_P9

PCIE_CRX_DTX_N10 PCIE_CRX_DTX_P10 PCIE_CTX_DRX_N10 PCIE_CTX_DRX_P10

PCIE_RCOMPN PCIE_RCOMPP

XDP_PRDY# XDP_PREQ#

UC1H

PCIE / USB3 / SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

3

SKL-U

USB2

8 OF 20

SSIC / USB3

USB3_2_RXN / SSIC_RXN USB3_2_RXP / SSIC_RXP USB3_2_TXN / SSIC_TXN USB3_2_TXP / SSIC_TXP

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

Rev_1.0

USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_3_RXN USB3_3_RXP USB3_3_TXN USB3_3_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E8/SATALED#

L-U_BGA1356@

SK

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6 AG3 AG4

A9 C9 D9 B9

J1 J2 J3

H2 H3 G4

H1

SATA_GP0

SATA_GP1

SA

TA_GP2

2

USB20_N1 USB20_P1

USB20_N2 USB20_P2

USB20_N3 USB20_P3

USB20_N5 USB20_P5

USB20_N6 USB20_P6

USB20_N7 USB20_P7

USB20_N8 USB20_P8

USB20_N9 USB20_P9

USB20_N10 USB20_P10

USB2_COMP USB2_ID USB2_VBUSSENSE

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

TBT_FORCE_PW R DEVSLP1 DEVSLP2

SATA_GP0 SATA_GP1 SATA_GP2

SOC_SATALED#

Default

1 IFDET_SATAEX0(HDD)

IFDET_SATAEX1

IFDET_SATAEX2

1

USB3_CRX_DTX_N1 <33>

USB3_CRX_DTX_P1 <33>

USB3_CTX_DRX_N1 <33>

USB3_CTX_DRX_P1 <33>

USB3_CRX_DTX_N2 <33>

USB3_CRX_DTX_P2 <33>

USB3_CTX_DRX_N2 <33>

USB3_CTX_DRX_P2 <33>

USB3_CRX_DTX_N3 <34>

USB3_CRX_DTX_P3 <34>

USB3_CTX_DRX_N3 <34>

USB3_CTX_DRX_P3 <34>

USB20_N1 <33> USB20_P1 <33>

USB20_N2 <33> USB20_P2 <33>

USB20_N3 <34> USB20_P3 <34>

USB20_N5 <20> USB20_P5 <20>

USB20_N6 <20> USB20_P6 <20>

USB20_N7 <37> USB20_P7 <37>

USB20_N8 <32>

T151 TP@ T150 TP@

T141 TP@ T143 TP@

T148 TP@ T238 TP@

USB20_P8 <32>

1 2

RC119 113_0402_1%

1 2

RC121 1K_0402_5%

1 2

RC125 1K_0402_5%

USB_OC0# <33> USB_OC1# <33>

TBT_FORCE_PW R <44>

DEVSLP1 <36> DEVSLP2 <36>

SATA_GP0 <36> SATA_GP1 <36> SATA_GP2 <36>

SOC_SATALED# <36,38>

USB3.0 MB_PORT1(Conn2 + OTG support)

U

3D CAMERA / Caldera

USB2.0 MB_PORT1 (Conn2)

USB2.0 MB_PORT2 (Conn1 + Power Share)

NC / Caldera

USB2.0 IO_PORT3 / NC

TOUCH SCREEN

USB2.0 Camera

ELC

NGFF WLAN+BT

SATA1 SATA2

IFDET_SATAEX0(Reserve) IFDET_SATAEX1 IFDET_SATAEX2

0=SATA

NA

0=SATA 1=PCI-E1

0=SATA 1=PCI-E

1

SB3.0 MB_PORT2(Conn1 + Charge)

NC port for 3D Camera sku

NC port for Gaming

**** Swap Port **** Follow Customer design (Different with TD Team)

SOC_SATALED#

DEVSLP1 DEVSLP2 USB_OC0# USB_OC1#

1 2

RC211

10K_0402_5%

RPC13

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

+3VS +3V_PRIM

Follow 545659_SKL_PCH_LP_EDS_Rev1_0

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(7/12)PCIE,USB,SATA

Size Document Number Rev

LA-C901P

Date: Sheet

2

Date: Sheet

1

12 63Tuesday, August 04, 2015

1.0

of

5

For P

ower consumption Measurement

+5VALW

1U_0402_6.3V6K

CC98

D D

1 2

SYSON<13,41,54>

PM_SLP_S4#<6,10,37,41,54>

SUSP#<41,42,44>

PM_SLP_S3#<6,10,37,41>

For Power consumption Measurement

C C

Imax : 2.77 A

RC142 0_0402_1%@

1 2

RC144 0_0402_5%@

1 2

RC168 0_0402_1%@

1 2

RC194 0_0402_5%@

1

@

2

+1.8V_PRIM

@

+1.0V_PRIM TO +1.0VS_VCCSTG / +1.0VS_VCCIO

+5VALW

+3V_PRIM

CC92

1 2

0.1U_0201_10V6K

PM_SLP_S3# SUSP#

B B

For meet tPLT18 power down sequence. tPLT18 : 1us (Max)

+1.0VS_VCCIO

1

2

5

UC12

1

P

B

4

O

2

A

G

TC7SH08FU_SSOP5~D

3

RC187 0_0402_5%@

10U_0402_6.3V6M

1

CC27

1

CC28

2

0.1U_0402_25V6

CC88

1

2

@

EN_VCCSTG_IO

1 2

1U_0201_6.3V6M

CC29

1U_0201_6.3V6M

1

2

+1.0V_PRIM

1

2

1

CC30

2

I (Max) : 3 A(+1.0VS_VCCIO) RON(Max) : 6.2 mohm

1U_0402_6.3V6K

V drop : 0.019 V

CC117

1U_0201_6.3V6M

CC31

1U_0201_6.3V6M

1

CC32

2

UC6

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

1U_0402_6.3V6K

1

CC33

2

4

+1.0V_PRIM TO +1.0V_VCCSTU

1U_0402_6.3V6K

CC97

1

I (Max) : 0.04 A(+1.0V_VCCSTU) RON(Max) : 25 mohm

2

V drop : 0.001 V

EN_1.0V_VCCSTU

EN_1.8VS

1U_0402_6.3V6K

CC99

1

2

UC5

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

EM5209VF_DFN14_2X3

I (Max) : 0.536 A(+1.8VS) RON(Max) : 25 mohm V drop : 0.013 V

VOUT1 VOUT1

CT1

GND

CT2

VOUT2 VOUT2

GPAD

14 13

12

CC95

11

10P_0402_50V8J

10

CC94

9

1000P_0402_50V7K

8 15

1 2

+1.8V_PRIM TO +1.8VS

max : 0.04 A

I

1 2

RC188 0_0402_1%@

6

GND

+1.0VS_VCCSTG_IO

5

RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev1.0 RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev0_53

VOUT

PSC SideBSC Side

1U_0402_6.3V6K

1

CC34

2

1U_0402_6.3V6K

1

CC35

CC36

2

MP@

1 2

RC189 0_0805_5%

Imax : 3 A

+1.35V_VDDQ_CPU

3

+1.0V_VCCSTU+1.0V_PRIM

0.1U_0402_25V6

CC96

1

2

ollow 543977_SKL_PDDG_Rev0_91

F CC95 10PF ->22us(Spec:<= 65us)

+1.0V_VCCSTU +1.0V_VCCST

@

1 2

@

1 2

+1.35V_VDDQC

BSC Side

+1.0VS_VCCSTG

+1.0VS_VCCIO

1 2

RC208 0_0603_1%@

+1.8VS

1

CC100

0.1U_0402_25V6

2

CC89 0.1U_0402_25V6

CC90 0.1U_0402_25V6

+1.35V_VDDQ

For Power consumption Measurement

1 2

RC140 0_0402_1%

1 2

RC143 0_0402_1%@

PSC Side

1U_0402_6.3V6K

1

2

1

CC47

2

1 2

RC145 0_0805_1%@

+1.0VS_VCCSTG

+1.35V_VCCSFR_OC

+1.0V_VCCSFR

@

PSC Side

+1.35V_VDDQ_CPU

10U_0603_6.3V6M

CC93

+1.35V_VDDQC +1.0V_VCCST

+1.0V_VCCSFR

10U_0603_6.3V6M

1

2

+1.35V_VDDQ_CPU

1U_0402_6.3V6K

1

CC48

2

1U_0402_6.3V6K

1

CC55

2

SC Side

10U_0603_6.3V6M

1

CC37

2

UC1N

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

BB47

VDDQ_BB47

BB51

VDDQ_BB51

AM40

VDDQC

A18

VCCST

A22

VCCSTG_A22

AL23

VCCPLL_OC

K20

VCCPLL_K20

K21

VCCPLL_K21

+5VALW +1.35V_VDDQ_CPU

+1.0VS_VCCSTG

10U_0603_6.3V6M

1

CC38

CC39

2

10U_0603_6.3V6M

SKL-U

SYSON<13,41,54>

CC40

CPU POWER 3 OF 4

14 OF 20

CC101

1

2

BSC Side

1U_0201_6.3V6M

1

CC56

2

10U_0603_6.3V6M

1

CC41

2

1U_0201_6.3V6M

1

2

Rev_1.0

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE VCCSA_SENSE

L-U_BGA1356@

SK

1 2

7 3 4

BSC SideP

10U_0603_6.3V6M

1

CC42

2

+1.0VS_VCCIO

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23

VCCIO_SENSE

AM22

VSSIO_SENSE

H21

VSA_SEN-

H20

VSA_SEN+

+1.35V_VDDQ_CPU

UC10

VIN1 VIN2

VIN thermal VBIAS ON

TPS22961DNYR_WSON8

1U_0402_6.3V6K

1U_0201_6.3V6M

1

CC43

CC44

2

1

+VCC_SA

1 2

VOUT

GND

1U_0402_6.3V6K

1

2

CC45

RC141

0_0402_5%@

6

5

1

2

T124 TP@ T125 TP@

VSA_SEN- <58> VSA_SEN+ <58>

+1.35V_VCCSFR_OC

BSC Side

0.1U_0201_10V6K

CC49

1

2

1U_0402_6.3V6K

CC46

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CC47 Follow 543016_SKL_U_Y_PDG_0_9 C

C93 Follow 543016_SKL UY PDG_rev1_3

Compal Secret Data

2015/01/06 2016/01/06

3

Compal Secret Data

Deciphered Date

+1.35V_VDDQ_CPU : 10UF/6.3V/0603 *6

2

1UF/6.3V/0402 * 4

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SKL-U(8/12)Power

LA-C901P

1.0

of

13 63Tuesday, August 04, 2015

of

13 63Tuesday, August 04, 2015

of

13 63Tuesday, August 04, 2015

1

5

+1.0V_PRIM

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC148 0_0603_1%@

D D

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC152 0_0603_1%@

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC190 0_0603_1%@

C C

Imax : 2.57A

1 2

RC175 0_0402_1%@

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC169 0_0603_1%@

B B

1 2

RC162 0_0402_1%@

1U_0402_6.3V6K

1

@

2

+1.0V_APLL

22U_0603_6.3V6M

CC123

1

@

2

+1.0V_CLK5_F24NS

22U_0603_6.3V6M

CC129

1

@

2

+1.0V_CLK4_F100OC

22U_0603_6.3V6M

CC127

1

@

2

+1.0V_PRIM

1

@

2

+1.0V_MPHYAON

1

2

+1.0V_CLK6_24TBT

1U_0402_6.3V6K

1

CC86

CC75

@

2

+1.0V_DTS

22U_0603_6.3V6M

CC124

+3V_PRIM

1 2

22U_0603_6.3V6M

CC130

22U_0603_6.3V6M

CC128

1U_0402_6.3V6K

CC76

1U_0402_6.3V6K

CC87

22U_0603_6.3V6M

CC125

1

@

2

RC197 0_0402_1%@

1 2

RC154 0_0402_1%@

1 2

RC161 0_0402_1%@

1 2

RC172 0_0402_1%@

CC126

1 2

RC171 0_0402_1%@

4

+3V_1.8V_PGPPA

+3V_SPI

+3V_PGPPBCE

1

@

2

+3V_1.8V_PGPPD

1

2

+3V_PRIM_RTC

1

2

1U_0402_6.3V6K

CC102

@

RC206 0_0402_5%@

1U_0402_6.3V6K

CC103

1U_0402_6.3V6K

1

CC77

2

1U_0402_6.3V6K

1

CC73

2

1 2

0.1U_0201_10V6K

CC78

3

+1.0V_AMPHYPLL+1.0V_MPHYPLL

1 2

RC149 0_0603_1%@

1 2

RC156 0_0402_1%@

1 2

1U_0402_6.3V6K

1

CC74

@

2

+1.8V_PRIM

RC176 0_0603_1%@

RC209 0_0603_1%@

+1.0VO_DSW

1

2

1 2

1U_0402_6.3V6K

CC85

+1.8V_PRIM

1

@

2

1

2

1U_0402_6.3V6K

1

CC72

@

2

1U_0402_6.3V6K

CC61

@

1U_0201_6.3V6M

CC80

+3V_PRIM

1

2

22U_0603_6.3V6M

CC118

1

@

2

+1.0V_APLLEBB

1

2

+1.0V_SRAM

1

@

2

+1.0V_MPHYGT

22U_0603_6.3V6M

CC81

1

2

@

+1.0V_PRIM

1U_0402_6.3V6K

CC67

@

22U_0603_6.3V6M

CC119

1U_0201_6.3V6M

CC68

1U_0402_6.3V6K

CC122

22U_0603_6.3V6M

CC82

+1.0V_PRIM

+1.0VO_DSW

+1.0V_MPHYAON

+1.0V_MPHYGT

+1.0V_AMPHYPLL

+1.0V_APLL +1.0V_PRIM

+3VALW_DSW

RC163 close to UC1 pinAJ19

+3V_PRIM

Per 543016_SKL_U_Y_PDG_0_9 VCCRTC does not exceed 3.2 V From PDG

1 2

RF@

RC163 0_0402_5%

+3V_SPI +1.0V_SRAM

+3V_PRIM +1.0V_PRIM

+1.0V_APLLEBB

Power Rail Voltage

+CHGRTC

3.383V(MAX)

BAT54C(VF)

240 mV

+3VL_RTC

3.143V

1U_0402_6.3V6K

1

CC91

2

Note : Stuff UC8 RC191,RC159,CC50,PR809 for meet energy star power consumption under AC S5 mode

PCH_PWR_EN<41,56> SLP_SUS#<10,41>

Result : Pass

1 2

RC191 0_0402_1%@

1 2

RC174 0_0402_5%@

+1.0V_PRIM

2

UC1O

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB_1P0

+RTCBATT

RC192 1K_0402_5%

+3VLP

+3VALW TO +3V_PRIM

+3VALW

I (Max) : 0.46 A(+3V_PRIM) RDS(Typ) : 65 mohm V drop : 0.03 V

1U_0402_6.3V6K

CC50

1

2

EN_3V_PRIM

12

RC167 100K_0402_5%

SKL-U

CPU POWER 4 OF 4

15 OF 20

W=20mils

1 2

W=20mils

UC8

5

IN

4

EN

SY6288C20AAC_SOT23-5

Rev_1.0

VCCPGPPA

VCCPGPPB VCCPGPPC VCCPGPPD

VCCPGPPE

VCCPGPPF VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

DCPRTC VCCCLK1 VCCCLK2 VCCCLK3 VCCCLK4 VCCCLK5 VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

L-U_BGA1356@

SK

RTC Battery

MAX. 8000mil

DC1

2

1

3

BAT54C-7-F_SOT23-3

RC153 0_0805_5%@

+3V_PRIMJP

RC159 0_0805_5%

1

OUT

2

GND

3

OC

3V_PRIM_OC

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19 T1 AA1 AK17 AK19

BB14 BB10

CC71 0.1U_0402_10V7K

A14 K19 L21 N20 L19 A10 AN11

PRIMCORE_VID0

AN13

PRIMCORE_VID1

C79.CC84 Close UC1.AK19.

C

W=20mils

1U_0201_6.3V6M

CC84

1

2

For NON-DS3

1 2

For DS3

1 2

@

RC166 10K_0402_5%

1

+3V_1.8V_PGPPA +3V_PGPPBCE

+3V_1.8V_PGPPD +3V_PGPPBCE +1.8V_PRIM +3V_PGPPBCE

+3V_PRIM +1.0V_DTS +1.8V_PRIM +3V_PRIM_RTC +3VL_RTC

1 2

+1.0V_CLK6_24TBT

+1.0V_APLL +1.0V_CLK4_F100OC +1.0V_CLK5_F24NS +1.0V_CLK6_24TBT

0.1U_0201_10V6K

CC79

1

2

+3V_PRIM+3VALW

+3VALW

T130 TP@ T131 TP@

1

2

+3VL_RTC

4.7U_0603_6.3V6K CC51

For SD CARD

Follow 543016_SKL_U_Y_PDG_0_9

+1.0V_PRIM +3V_PRIM +1.8V_PRIM

22U_0603_6.3V6M

1

@

2

A A

22U_0603_6.3V6M

CC112

CC111

@

CC113

1

@

2

5

22U_0603_6.3V6M

CC115

CC116

CC114

1

@

2

EXT_PWR_GATE#<10>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

3

RC210 0_0402_1%@

2015/01/06 2016/01/06

+5VALW

1

2

1 2

Compal Secret Data

Deciphered Date

0.1U_0402_25V6

CC52

+1.0V_PRIM

@

EXT_PWR_GATE#_R

12

2

+

1.0V_PRIM TO +1.0V_MPHYPLL

I (Max) : 2.766 A(+1.0V_MPHYPLL) RON(Max) : 6.2 mohm

1U_0402_6.3V6K

V drop : 0.017 V

CC59

1

@

UC4

1

2

RC170 100K_0402_5%

@

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

@

VOUT

GND

Title

Size Document Number Rev

Date: Sheet

For Premium

6

5

Compal Electronics, Inc.

LA-C901P

1 2

+1.0V_MPHYJP

+1.0V_PRIM

SKL-U(9/12)Power

@

RC164 0_0805_5%

Imax : 2.766A

For Volume

MP@

1 2

RC160 0_0805_5%

1

+1.0V_MPHYPLL

1

CC58

0.1U_0402_25V6

@

2

of

14 63Tuesday, August 04, 2015

of

14 63Tuesday, August 04, 2015

of

14 63Tuesday, August 04, 2015

1.0

5

4

3

2

1

+VCC_CORE +VCC_CORE

UC1L

A30

VCC_A30

A34

VCC_A34

D D

T123 TP@ T121 TP@

+1.0VS_VCCOPC

For CPU2+3e SKU

+1.8V_VCCOPC

C C

B B

T132 TP@ T133 TP@

T137 TP@ T139 TP@

SVID ALERT

VCCOPC_SENSE VSSOPC_SENSE

+1.0VS_VCCEOPIO

VCCEOPIO_SENSE VSSEOPIO_SENSE

+1.0V_VCCST

A39

VCC_A39

A44

VCC_A44

AK33

VCC_AK33

AK35

VCC_AK35

AK37

VCC_AK37

AK38

VCC_AK38

AK40

VCC_AK40

AL33

VCC_AL33

AL37

VCC_AL37

AL40

VCC_AL40

AM32

VCC_AM32

AM33

VCC_AM33

AM35

VCC_AM35

AM37

VCC_AM37

AM38

VCC_AM38

G30

VCC_G30

K32

RSVD

AK32

RSVD

AB62

VCCOPC_AB62

P62

VCCOPC_P62

V62

VCCOPC_V62

H63

VCC_OPC_1P8_H63

G61

VCC_OPC_1P8_G61

AC63

VCCOPC_SENSE

AE63

VSSOPC_SENSE

AE62

VCCEOPIO

AG62

VCCEOPIO

AL63

VCCEOPIO_SENSE

AJ62

VSSEOPIO_SENSE

Place the PU resistors close to CPU

12

RC179 56_0402_5%

SKL-U

CPU POWER 1 OF 4

12 OF 20

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VCC_SENSE

VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

L-U_BGA1356@

SK

Rev_1.0

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

B63 A63 D64

G20

SOC_SVID_ALERT# SOC_SVID_CLK SOC_SVID_DAT

Trace Length < 25 mils

VCCSENSE <58> VSSSENSE <58>

SOC_SVID_CLK <58>

VCCGT_SENSE<58> VSSGT_SENSE<58>

Trace Length < 25 mils

+1.0VS_VCCSTG

VCCGT_SENSE VSSGT_SENSE

+VCC_GT +VCC_GT

A48 A53 A58 A62

A66 AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71

K48

K50

K52

K53

K55

K56

K58

K60

M62

N63

N64

N66

N67

N69

J43 J45 J46 J48 J50 J52 J53 J55 J56 J58 J60

L62 L63 L64 L65 L66 L67 L68 L69 L70 L71

J70 J69

UC1M

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT_SENSE VSSGT_SENSE

For 2+3e Solution

BSC Side BSC Side

SOC_SVID_ALERT#

SVID DATA

A A

1 2

RC180 220_0402_5%

+1.0V_VCCST

12

RC181 100_0402_1%

SOC_SVID_ALERT#_R <58>

Place the PU resistors close to CPU

(To VR)

CC66

1

10U_0603_6.3V6M

2

23E@

CPU POWER 2 OF 4

+1.0VS_VCCOPC+1.0VS_VCCEOPIO

CC62

1U_0402_6.3V6K

SKL-U

13 OF 20

1

2

23E@

Rev_1.0

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70

VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56

VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58

VCCGTX_AU58 VCCGTX_AU63 VCCGTX_BB57 VCCGTX_BB66

VCCGTX_SENSE VSSGTX_SENSE

L-U_BGA1356@

SK

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

+VCC_GTX

VCCGTX_SENSE VSSGTX_SENSE

For CPU2+3e SKU

T155 TP@ T219 TP@

SOC_SVID_DAT

SOC_SVID_DAT <58>

5

4

(To VR)

Security Classification

2015/01/06 2016/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

SKL-U(10/12)Power,SVID

LA-C901P

1

of

15 63Tuesday, August 04, 2015

of

15 63Tuesday, August 04, 2015

of

15 63Tuesday, August 04, 2015

1.0

5

4

3

2

1

D D

C C

B B

A67

A70 AA2 AA4

AA65 AA68 AB15 AB16 AB18 AB21

AB8

AD13 AD16 AD19 AD20 AD21 AD62

AD8

AE64 AE65 AE66 AE67 AE68 AE69

AF1

AF10 AF15 AF17

AF2

AF4

AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13

AH6

AH63 AH64 AH67

AJ15 AJ18 AJ20

AJ4

AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69

AK8

AL2

AL28 AL32 AL35 AL38

AL4

AL45 AL48 AL52 AL55 AL58 AL64

UC1P

A5

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-U

GND 1 OF 3

16 OF 20

SK

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-U

GND 2 OF 3

17 OF 20

SK

Rev_1.0

BA49

VSS

BA53

VSS

BA57

VSS

BA6

VSS

BA62

VSS

BA66

VSS

BA71

VSS

BB18

VSS

BB26

VSS

BB30

VSS

BB34

VSS

BB38

VSS

BB43

VSS

BB55

VSS

BB6

VSS

BB60

VSS

BB64

VSS

BB67

VSS

BB70

VSS

C1

VSS

C25

VSS

C5

VSS

D10

VSS

D11

VSS

D14

VSS

D18

VSS

D22

VSS

D25

VSS

D26

VSS

D30

VSS

D34

VSS

D39

VSS

D44

VSS

D45

VSS

D47

VSS

D48

VSS

D53

VSS

D58

VSS

D6

VSS

D62

VSS

D66

VSS

D69

VSS

E11

VSS

E15

VSS

E18

VSS

E21

VSS

E46

VSS

E50

VSS

E53

VSS

E56

VSS

E6

VSS

E65

VSS

E71

VSS

F1

VSS

F13

VSS

F2

VSS

F22

VSS

F23

VSS

F27

VSS

F28

VSS

F32

VSS

F33

VSS

F35

VSS

F37

VSS

F38

VSS

F4

VSS

F40

VSS

F42

VSS

BA41

VSS

L-U_BGA1356@

G10 G22 G43 G45 G48

G52 G55 G58

G60 G63 G66 H15 H18 H71

J11 J13 J25 J28 J32 J35 J38 J42

K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71 L11 L16 L17

UC1R

F8

G5

G6

J8

SK

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L-U_BGA1356

SKL-U

GND 3 OF 3

18 OF 20

Rev_1.0

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

AT63 AT68 AT71 AU10 AU15 AU20 AU32 AU38

AV1 AV68 AV69 AV70 AV71

AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57

AW6 AW60 AW62 AW64 AW66

AW8

AY66

B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71

BA1 BA10 BA14 BA18

BA2 BA23 BA28 BA32 BA36

F68 BA45

UC1Q

Rev_1.0

AL65

VSS

AL66

VSS

AM13

VSS

AM21

VSS

AM25

VSS

AM27

VSS

AM43

VSS

AM45

VSS

AM46

VSS

AM55

VSS

AM60

VSS

AM61

VSS

AM68

VSS

AM71

VSS

AM8

VSS

AN20

VSS

AN23

VSS

AN28

VSS

AN30

VSS

AN32

VSS

AN33

VSS

AN35

VSS

AN37

VSS

AN38

VSS

AN40

VSS

AN42

VSS

AN58

VSS

AN63

VSS

AP10

VSS

AP18

VSS

AP20

VSS

AP23

VSS

AP28

VSS

AP32

VSS

AP35

VSS

AP38

VSS

AP42

VSS

AP58

VSS

AP63

VSS

AP68

VSS

AP70

VSS

AR11

VSS

AR15

VSS

AR16

VSS

AR20

VSS

AR23

VSS

AR28

VSS

AR35

VSS

AR42

VSS

AR43

VSS

AR45

VSS

AR46

VSS

AR48

VSS

AR5

VSS

AR50

VSS

AR52

VSS

AR53

VSS

AR55

VSS

AR58

VSS

AR63

VSS

AR8

VSS

AT2

VSS

AT20

VSS

AT23

VSS

AT28

VSS

AT35

VSS

AT4

VSS

AT42

VSS

AT56

VSS

AT58

VSS

L-U_BGA1356@

A A

Security Classification

2015/01/06 2016/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

SKL-U(11/12)GND

LA-C901P

1.0

of

16 63Tuesday, August 04, 2015

of

16 63Tuesday, August 04, 2015

of

16 63Tuesday, August 04, 2015

1

5

Display Port Presence Strap

CFG4

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is

onnected to the Embedded Display Port

c

4

3

2

1

D D

CFG0<6> CFG1<6> CFG2<6> CFG3<6> CFG4<6> CFG5<6> CFG6<6> CFG7<6>

CFG Signals

(For Strap & XDP)

C C

B B

CFG8<6> CFG9<6> CFG10<6> CFG11<6> CFG12<6> CFG13<6> CFG14<6> CFG15<6>

CFG16<6> CFG17<6>

CFG18<6> CFG19<6>

12

RC18549.9_0402_1%

XDP_ITP_PMODE<6>

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG17

CFG18 CFG19

CFG_RCOMP

XDP_ITP_PMODE

T213 TP@ T215 TP@

T220 TP@ T222 TP@

E68 B67 D65 D67 E70 C68 D68 C67

G69 G68

H70 G71 H69 G70

E63

E66

E60

AY2 AY1

K46 K45

AL25 AL27

C71 B70

A52

BA70 BA68

G65

E61

F71 F70

F63

F66

E8

D1 D3

F60

J71 J68

F65

F61

UC1S

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP ITP_PMODE RSVD_AY2

RSVD_AY1 RSVD_D1

RSVD_D3 RSVD_K46

RSVD_K45 RSVD_AL25

RSVD_AL27 RSVD_C71

RSVD_B70 RSVD_F60 RSVD_A52 RSVD_TP_BA70

RSVD_TP_BA68 RSVD_J71

RSVD_J68 VSS_F65

VSS_G65 RSVD_F61

RSVD_E61

L-U_BGA1356

SK

SKL-U

RESERVED SIGNALS-1

19 OF 20

Rev_1.0

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

TP5 TP6

RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4 RSVD_C4

TP4

RSVD_A69 RSVD_B69

RSVD_AY3 RSVD_D71

RSVD_C70 RSVD_C54

RSVD_D54

TP1 TP2

VSS_AY71

ZVM#

RSVD_TP RSVD_TP

MSM#

PROC_SELECT#

BB68 BB69

AK13 AK12

BB2 BA3

AU5 AT5

D5 D4 B2 C2

B3 A3

AW1 E1

E2 BA4

BB4 A4

C4 BB5 A69

B69 AY3 D71

C70 C54

D54 AY4

BB3 AY71

AR56 AW71

AW70 AP56

C64

PM_ZVM#

PM_MSM# SKL_CNL#

T156 TP@ T157 TP@

T158 TP@ T159 TP@

T162 TP@ T163 TP@

T199 TP@

1 2

RC182 0_0402_1%@

T214 TP@ T216 TP@

T225 TP@ T221 TP@

T223 TP@ T230 TP@

1 2

RC183 0_0402_1%@

RC184 100K_0402_5%@

+1.0V_VCCST

1 2

Follow 546765_2014WW48_Skylake_MOW_Rev_1_0 St

uff 100k(RC184) for Cannonlake.

Un-stuff 100k(RC184) for Skylake

For 2+3e Solution

PM_ZVM# Zero Voltage Mode: Control Signal to OPC VR, when low OPC VR output is 0V.

PM_MSM# Minimum Speed Mode: Control signal to VccEOPIO VR (connected only in 2 VR solution for OPC).

UC1T

AW69

RSVD_AW69

AW68

RSVD_AW68

AU56

RSVD_AU56

AW48

RSVD_AW48

C7

RSVD_C7

U12

RSVD_U12

U11

RSVD_U11

H11

RSVD_H11

A A

5

4

SKL-U_BGA1356

SKL-U

SPARE

20 OF 20

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev_1.0

RSVD_F6

RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12 RSVD_F52

F6 E3 C11 B11 A11 D12 C12 F52

Compal Secret Data

2015/01/06 2016/01/06

3

Compal Secret Data

Deciphered Date

PROC_SELECT# Processor Select: This pin is for compatibility with future platforms. It should NC with Skylake

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

SKL-U(12/12)RSVD

LA-C901P

of

17 63Tuesday, August 04, 2015

of

17 63Tuesday, August 04, 2015

of

17 63Tuesday, August 04, 2015

1

1.0

A

DDR_A_DQS#[0..7]<7>

DDR_A_D[0..63]<7>

DDR_A_DQS[0..7]<7>

DDR_A_MA[0..15]<7>

DDR_A_BS0<7>

DDR_A_BS1<7>

DDR_A_BS2<7>

DDR_A_WE#<7>

1 1

Layout Note: Place near JDIMM1

2 2

+1.35V_VDDQ

1

2

+1.35V_VDDQ

10U_0603_6.3V6M

1

3 3

4 4

2

Layout Note: Place near JDIMM1.203,204

+0.675VS_VTT

@

1

2

DDR_A_CAS#<7>

DDR_A_RAS#<7>

DDR_A_CLK0<7> DDR_A_CLK#0<7>

DDR_A_CLK1<7>

DDR_A_CLK#1<7>

DDR_A_CKE0<7>

DDR_A_CKE1<7>

DDR_A_CS#0<7> DDR_A_CS#1<7>

SOC_SMBDATA<8,19,36> SOC_SMBCLK<8,19,36>

DDR_A_ODT0<7>

DDR_A_ODT1<7>

M_THERMAL#<19,41>

1U_0402_6.3V6K

@

CD4

10U_0603_6.3V6M

CD10

1

2

0.1U_0402_25V6K

@

CD22

1U_0402_6.3V6K

1

CD5

2

10U_0603_6.3V6M

@

CD11

CD12

1

2

1U_0402_6.3V6K

0.1U_0402_25V6K CD23

1

2

A

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_WE# DDR_A_CAS# DDR_A_RAS#

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1

DDR_A_CKE0 DDR_A_CKE1 DDR_A_CS#0 DDR_A_CS#1

SOC_SMBDATA SOC_SMBCLK

DDR_A_ODT0 DDR_A_ODT1

M_THERMAL#

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

1U_0402_6.3V6K

1

@

CD6

1

2

CD24

@

CD7

CD8

2

10U_0603_6.3V6M

@

CD13

CD14

CD19

1

2

1U_0402_6.3V6K

1

CD25

2

D

/DQ Signals link to CPU

CMD Signals from CPU

Clock Signals from CPU

CTL Signals from CPU

SMBUS Signals link to CPU

From SOC ODT Signals to CH A

Thermal link to EC

1U_0402_6.3V6K

1

@

CD9

2

10U_0603_6.3V6M

CD15

1

2

Layout Note: Place near JDIMM1.199

+3VS

@

Address : 00

330U_D3_2.5VY_R6M

1

CD20

CD16

1

+

2

0.1U_0402_25V6K

1

12

CD27

CD26

2

2.2U_0402_6.3V6M

1 2

RC220 10K_0402_5%

1 2

RC221 10K_0402_5%

DDR_A_SA0 DDR_A_SA1

B

+0.675V_DDRA_VREFDQ

1

2

B

C

2.2U_0402_6.3V6M

10mils

0.1U_0402_25V6K

DDR_A_D29

CD1

DDR_A_D28

CD2

1

2

DDR_A_D30 DDR_A_D31

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D11 DDR_A_D10

DDR_A_D50 DDR_A_D51

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D49 DDR_A_D48

DDR_A_D45 DDR_A_D44

DDR_A_D42 DDR_A_D43

DDR_A_CKE0

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3

DDR_A_MA1 DDR_A_CLK0

DDR_A_CLK#0 DDR_A_MA10

DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# DDR_A_MA13

DDR_A_CS#1

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D3 DDR_A_D36

DDR_A_D32

DDR_A_D33 DDR_A_D39

DDR_A_D21 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D23

DDR_A_D56 DDR_A_D57

DDR_A_D63

+3VS+0.675VS_VTT +0.675VS_VTT

DDR_A_SA0 DDR_A_SA1

+0.675VS_VTT

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

FOX_AS0A621-J4RB-7H

CONN@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DQS0#

DQS0

DQ12 DQ13

DM1

RESET#

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3 DQ30

DQ31

CKE1

VDD

CK1#

VDD

RAS#

VDD

ODT0

VDD

ODT1

VDD

VREF_CA

DQ36 DQ37

DM4

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5 DQ46

DQ47 DQ52

DQ53

DM6

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7 DQ62

DQ63

EVENT#

SDA SCL

GND2

BOSS2

2

VSS DQ4 DQ5 VSS

VSS DQ6 DQ7 VSS

VSS

VSS VSS

VSS

A15 A14

A11

CK1

BA1

S0#

VSS

VSS VSS

VSS

VSS VSS

VSS

VTT

4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102 104 106 108 110 112 114 116 118 120 122

NC

124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

DDR_A_D24 DDR_A_D25

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D26 DDR_A_D27

DDR_A_D12 DDR_A_D13

DDR_DRAMRST# DDR_A_D14

DDR_A_D15 DDR_A_D52

DDR_A_D53

DDR_A_D54 DDR_A_D55

DDR_A_D40 DDR_A_D41

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D47 DDR_A_D46

+1.35V_VDDQ+1.35V_VDDQ

DDR_A_CKE1 DDR_A_MA15

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2

DDR_A_MA0 DDR_A_CLK1

DDR_A_CLK#1 DDR_A_BS1

DDR_A_RAS# DDR_A_CS#0

DDR_A_ODT0 DDR_A_ODT1

DDR_A_D0DDR_A_D5 DDR_A_D1DDR_A_D4

DDR_A_D2 DDR_A_D6DDR_A_D7

DDR_A_D37 DDR_A_D35

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D38

DDR_A_D20 DDR_A_D16

DDR_A_D22 DDR_A_D19

DDR_A_D61 DDR_A_D60

DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D58

DDR_A_D59DDR_A_D62 M_THERMAL#

SOC_SMBDATA SOC_SMBCLK +0.675VS_VTT

2015/01/06 2016/01/06

@

10mils

2.2U_0402_6.3V6M CD17

1

2

Compal Secret Data

Deciphered Date

D

0.1U_0402_25V6K CD3

1

CAD NOTE

2

PLACE THE CAP NEAR TO DIMM RESET PIN

1 2

RD8 0_0402_1%@

0.1U_0402_25V6K CD18

1

2

D

E

Reverse Type

2-3A to 1 DIMMs/channel

+1.35V_VDDQ

12

RD1 470_0402_5%

DDR_DRAMRST# <7,19>

+0.675V_DDR_VREFCA+0.675V_DDRA_VREFCA

+1.35V_VDDQ

1.8K_0402_1%

12

RD9

1 2

RD10 2_0402_1%

1.8K_0402_1%

12

RD11

From CPU to CHB

+0.675V_A_VREFDQ+0.675V_DDRA_VREFDQ

1

CD21

0.022U_0402_16V7K

2

12

RD12

24.9_0402_1%

Place near to SO-DIMM connector.

Non- Interleaved Memory

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDR3L_DIMMA

LA-C901P

E

18 63Tuesday, August 04, 2015

1.0

of

A

DDR_B_DQS#[0..7]<7> DDR_B_D[0..63]<7> DDR_B_DQS[0..7]<7>

DDR_B_MA[0..15]<7>

DDR_B_BS0<7>

DDR_B_BS1<7>

DDR_B_BS2<7> DDR_B_WE#<7>

1 1

Layout Note: Place near JDIMM2

2 2

+1.35V_VDDQ

3 3

Layout Note: Place near JDIMM2.203,204

+0.675VS_VTT

4 4

DDR_B_CAS#<7> DDR_B_RAS#<7>

DDR_B_CLK0<7> DDR_B_CLK#0<7> DDR_B_CLK1<7> DDR_B_CLK#1<7>

DDR_B_CKE0<7> DDR_B_CKE1<7> DDR_B_CS#0<7> DDR_B_CS#1<7>

SOC_SMBDATA<8,18,36> SOC_SMBCLK<8,18,36>

DDR_B_ODT0<7> DDR_B_ODT1<7>

M_THERMAL#<18,41>

1U_0402_6.3V6K

@

1

CD32

CD33

2

10U_0603_6.3V6M

@

CD39

CD38

1

2

0.1U_0402_25V6K

@

1

2

CD51

CD50

1

2

A

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_WE# DDR_B_CAS# DDR_B_RAS#

DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1

DDR_B_CKE0 DDR_B_CKE1

DDR_B_CS#0

DDR_B_CS#1

SOC_SMBDATA SOC_SMBCLK

DDR_B_ODT0 DDR_B_ODT1

M_THERMAL#

1U_0402_6.3V6K

1

2

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

1

2

@

1

CD35

CD34

2

10U_0603_6.3V6M

CD41

CD40

1

2

1U_0402_6.3V6K

1

CD52

CD53

2

D/DQ Signals link to CPU

CMD Signals from CPU

Clock Signals from CPU

CTL Signals from CPU

SMBUS Signals link to CPU

From SOC ODT Signals to CH B

Thermal link to EC

1U_0402_6.3V6K

@

1

CD36

CD37

2

10U_0603_6.3V6M

@

CD42

Layout Note: P

lace near JDIMM2.199

+3VS

10U_0603_6.3V6M

CD43

1

2

+3VS

0.1U_0402_25V6K

1

2

Address : 01

1 2

RD22 10K_0402_5%

1 2

RD23 10K_0402_5%

10U_0603_6.3V6M

CD44

CD45

1

2

CD54

12

@

2.2U_0402_6.3V6M

1

@

+

2

CD55

DDR_B_SA1 DDR_B_SA0

B

+0.675V_DDRB_VREFDQ

1

2

330U_D3_2.5VY_R6M

CD46

B

10mils

2.2U_0402_6.3V6M CD28

1

2

+0.675VS_VTT +3VS

0.1U_0402_25V6K

DDR_B_D8 DDR_B_D9

CD29

DDR_B_D10 DDR_B_D11

DDR_B_D29 DDR_B_D28

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D26 DDR_B_D27

DDR_B_D41 DDR_B_D40

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D43 DDR_B_D42

DDR_B_D56 DDR_B_D57

DDR_B_D59 DDR_B_D58

DDR_B_CKE0

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3

DDR_B_MA1 DDR_B_CLK0

DDR_B_CLK#0 DDR_B_MA10

DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDR_B_MA13

DDR_B_CS#1

DDR_B_D2 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D21 DDR_B_D20

DDR_B_D19 DDR_B_D18 DDR_B_D23

DDR_B_D36 DDR_B_DQS#4

DDR_B_DQS4 DDR_B_D33

DDR_B_D35

DDR_B_D49

DDR_B_D51 DDR_B_D50 DDR_B_D55

DDR_B_SA0 DDR_B_SA1

+0.675VS_VTT

C

JDIMM2

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

+1.35V_VDDQ

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205 207

C

VSS

CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT

GND1 BOSS1

FOX_AS0A621-J4RB-7H

CONN@

2015/01/06 2016/01/06

VSS DQ4 DQ5 VSS

DQS0#

DQS0

VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

RESET#

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

CKE1

VDD

VDD CK1#

VDD RAS#

VDD ODT0

VDD ODT1

VDD

VREF_CA

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

EVENT#

SDA

GND2

BOSS2

A15 A14

A11

CK1

BA1

S0#

SCL VTT

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102 104 106 108 110 112 114 116 118 120 122

NC

124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

DDR_B_D13 DDR_B_D12

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D15 DDR_B_D14

DDR_B_D25 DDR_B_D24

DDR_DRAMRST# DDR_B_D30

DDR_B_D31 DDR_B_D45

DDR_B_D44

DDR_B_D47 DDR_B_D46

DDR_B_D61 DDR_B_D60

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

+1.35V_VDDQ

DDR_B_CKE1 DDR_B_MA15

DDR_B_MA14 DDR_B_MA11

DDR_B_MA7 DDR_B_MA6

DDR_B_MA4 DDR_B_MA2

DDR_B_MA0 DDR_B_CLK1

DDR_B_CLK#1 DDR_B_BS1

DDR_B_RAS# DDR_B_CS#0

DDR_B_ODT0 DDR_B_ODT1

DDR_B_D0 DDR_B_D4

DDR_B_D3 DDR_B_D1

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D22

DDR_B_D32DDR_B_D37 DDR_B_D34

DDR_B_D39 DDR_B_D38

DDR_B_D53 DDR_B_D52DDR_B_D48

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D54

M_THERMAL# SOC_SMBDATA SOC_SMBCLK +0.675VS_VTT

Compal Secret Data

Deciphered Date

D

0.1U_0402_25V6K CD30

1

@

2

CAD NOTE PLACE THE CAP NEAR TO DIMM RESET PIN

10mils

2.2U_0402_6.3V6M

CD47

1

2

+0.675VS_VTT

D

DDR_DRAMRST# <7,18>

+1.35V_VDDQ

1.8K_0402_1%

12

1.8K_0402_1%

12

Place near to SO-DIMM connector.

1 2

RD17 0_0402_1%@

0.1U_0402_25V6K

CD48

1

2

+1.35V_VDDQ

1.8K_0402_1%

12

1.8K_0402_1%

12

Place near to SO-DIMM connector.

Non-Interleaved Memory

Date: Sheet

E

Reverse Type

2-3A to 1 DIMMs/channel

From CPU

RD13

+0.675V_B_VREFDQ+0.675V_DDRB_VREFDQ

1 2

RD14 2_0402_1%

RD15

+0.675V_DDR_VREFCA+0.675V_DDRB_VREFCA

RD18

1 2

RD19 2_0402_1%

RD20

Title

Size Document Number Rev

1

CD31

0.022U_0402_16V7K

2

12

RD16

24.9_0402_1%

+0.675V_VREFCA+0.675V_DDR_VREFCA

1

CD49

0.022U_0402_16V7K

2

12

RD21

24.9_0402_1%

Compal Electronics, Inc.

DDR3L_DIMMB

LA-C901P

E

19 63Tuesday, August 04, 2015

of

1.0

5

4

3

2

1

LCD power control

D D

4.7U_0805_10V4Z

EDP_VDDEN<6>

C C

+3VS

1

CV19

2

1 2

@

RV6 0_0402_1%

ENVDD_R

UV3

5

OUT

IN

GND

4

OC

EN

SY6288C20AAC_SOT23-5

LV1 FBMA-L11-201209-221LMA30T_0805

1

+LCDVDD

2

1 2

3

RV28 10K_0402_5%

1 2

+3VS

LCD backlight power control

QV6 SI3457CDV-T1-GE3_TSOP6

B+

W=60mils

1000P_0402_50V7K

1

2

6 5 2

S

D

1

4

RV12

100K_0402_5%

CV22

12

PWR_SRC_ON

RV15 100K_0402_5%

G

3

1

CV23

0.1U_0603_25V7K

2

W=60mils

W=60milsW=60mils

+INV_PWR_SRC

+LCDVDD_CONN

CV14

0.1U_0402_10V7K

1

2

CV21

4.7U_0805_10V4Z

1

2

BKOFF#<41>

USB20_P6<12>

USB20_N6<12>

USB20_N5<12> USB20_P5<12>

12

DV1 RB751V-40_SOD323-2

MCM1012B900F06BP_4P

1 2

LV2

EMI@

1 2

RV9 0_0402_5%

@EMI@

1 2

RV10 0_0402_5%

@EMI@

USB20_N5 USB20_P5

2

3

DV2 PESD5V0U2BT_SOT23-3

@ESD@

1

12

34

DISPOFF#

10K_0402_5% RV5

USB20_L_P6

USB20_L_N6

EDP_BIA_PWM<6>

EDP_TXP0<6> EDP_TXN0<6>

EDP_TXP1<6>

EDP_TXN1<6>

EDP_TXP2<6>

EDP_TXN2<6>

EDP_TXP3<6>

EDP_TXN3<6>

EDP_AUXP<6>

EDP_AUXN<6>

EDP_HPD<6>

MIC_DATA<31> LCD_TEST<41>

TS_EN<41>

For Camera

+VDD_TOUCH

+LCDVDD_CONN

MIC_DATA LCD_TEST

RV11

100K_0402_5%

+3VS

W=60mils

12

+INV_PWR_SRC

12

CV150.1U_0402_16V7K

12

CV120.1U_0402_16V7K

12

CV170.1U_0402_16V7K

12

CV160.1U_0402_16V7K

12

CV1980.1U_0402_16V7K

12

CV1990.1U_0402_16V7K

12

CV2000.1U_0402_16V7K

12

CV2010.1U_0402_16V7K

12

CV130.1U_0402_16V7K

12

CV180.1U_0402_16V7K

EDP_HPD CE_EN_R

DBC_EN_R

USB20_L_P6 USB20_L_N6

TS_EN

MIC_CLK_R MIC_GND

USB20_N5 USB20_P5

DISPOFF#

W=60mils

eDP connector

EDP_TXP0_C EDP_TXN0_C

EDP_TXP1_C EDP_TXN1_C

EDP_TXP2_C EDP_TXN2_C

EDP_TXP3_C EDP_TXN3_C

EDP_AUXP_C EDP_AUXN_C

+3VS +LCDVDD_CONN

0.1U_0402_10V7K CV24

CV25

1

2

Place close to JEDP

JEDP

1

2

G1

3

G2

4

G3

5

G4

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

ACES_50473-0400M-P01

CONN@

0.1U_0402_10V7K

10U_0805_10V6K

1

2

41 42 43 44

CV26

13

D

2

EN_INVPWR<41>

B B

A A

RV29

100K_0402_5%

5

12

G

QV7 2N7002KW_SOT323-3

S

Touch screen panel power control

+5VS +VDD_TOUCH

1

CV27

4.7U_0805_10V4Z

4

2

@

J512

112

JUMP_43X39

2

3

CV28

0.1U_0402_10V7K

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

DBC_EN<41>

MIC_CLK<31>

Compal Secret Data

DBC_EN DBC_EN_R

MIC_CLK MIC_CLK_R

Deciphered Date

2

1 2

@

RV20 0_0402_1%

0_0402_1%

1 2

@

RV21 0_0402_1%

RV16

CE_EN_R

12

@

RV17

@

0_0402_5%

1

CV420 15P_0402_50V8J

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

eDP/webcam/touch

eDP/webcam/touch LA-C901P

LA-C901P

1

20 63Tuesday, August 04, 2015

1.0

5

4

3

2

1

Place close to JHDMI

TMDS_TXCN

D D

TMDS_TXCP

TMDS_TX0N

Near Connector

12

DDI1_LANE_P0<23> DDI1_LANE_N0<23>

DDI1_LANE_P1<23>

From GPU

C C

DDI1_LANE_N1<23> DDI1_LANE_P2<23>

DDI1_LANE_N2<23> DDI1_LANE_P3<23>

DDI1_LANE_N3<23>

CV40 0.1U_0402_10V7K

12

CV39 0.1U_0402_10V7K

12

CV38 0.1U_0402_10V7K

12

CV37 0.1U_0402_10V7K

12

CV36 0.1U_0402_10V7K

12

CV35 0.1U_0402_10V7K

12

CV32 0.1U_0402_10V7K

12

CV31 0.1U_0402_10V7K

RV533

499_0402_1%

+3VS_VGA

RV535

499_0402_1%

RV536

499_0402_1%12RV537

12

499_0402_1%

100K_0402_5%

RV534

499_0402_1%

12

RV13

RV540

RV538

499_0402_1%

RV539

499_0402_1%

12

2

G

12

499_0402_1%

12

13

D

S

TMDS_TX2P TMDS_TX2N

TMDS_TX1P TMDS_TX1N

TMDS_TX0P TMDS_TX0N

TMDS_TXCP TMDS_TXCN

QV3 BSS138-G_SOT23-3

+VDISPLAY_VCC

TMDS_TX0P

TMDS_TX1N

TMDS_TX1P

TMDS_TX2N

TMDS_TX2P

1 2

RV23 5.1_0402_1%

EMI@

LV3

@EMI@

1 2

HCM1012GH900BP_4P

RV24 5.1_0402_1%

EMI@

RV26 5.1_0402_1%

EMI@

LV4

1 2

HCM1012GH900BP_4P

RV30 5.1_0402_1%

EMI@

RV32 5.1_0402_1%

EMI@

LV5

1 2

HCM1012GH900BP_4P

RV33 5.1_0402_1%

EMI@

RV43 5.1_0402_1%

EMI@

LV6

1 2

HCM1012GH900BP_4P

RV44 5.1_0402_1%

EMI@

34

1 2

@EMI@

34

1 2

@EMI@

34

1 2

@EMI@

34

1 2

TMDS_L_TXCN

RV22 150_0402_1%

EMI@

1 2

TMDS_L_TXCP

TMDS_L_TX0N

RV25 150_0402_1%

EMI@

1 2

TMDS_L_TX0P

TMDS_L_TX1N

RV31 150_0402_1%

EMI@

1 2

TMDS_L_TX1P

TMDS_L_TX2N

RV36 150_0402_1%

EMI@

1 2

TMDS_L_TX2P

TMDS_L_TXCN TMDS_L_TXCP

TMDS_L_TX0N TMDS_L_TX0P

TMDS_L_TX1N TMDS_L_TX1P

TMDS_L_TX2N TMDS_L_TX2P

+5VS

UV5

1

VIN

APL3517AI-TRG_SOT23-3

1 2

RV46

1 2

RV48 6.04_0402_1%

1 2

RV53

1 2

RV54 6.04_0402_1%

1 2

RV59

1 2

RV61 6.04_0402_1%

1 2

RV65

1 2

RV67 6.04_0402_1%

3

VOUT

GND

HDMI_HPLUG

HDMI_CTRLDAT HDMI_CTRLCLK

6.04_0402_1%

6.04_0402_1%%

6.04_0402_1%

TMDS_L_R_TXCN TMDS_L_R_TXCP

TMDS_L_R_TX0N TMDS_L_R_TX0P

TMDS_L_R_TX1N TMDS_L_R_TX1P

TMDS_L_R_TX2N TMDS_L_R_TX2P

W=60mils

2

+3VS

12

@

RV19 10K_0402_5%

JHDMI

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

FUTUR_061-HA18-0001

CONN@

ROYALTY HDMI W/LOGO CPN:RO0000002HM

0.1U_0402_16V7K

GND GND GND GND

+VDISPLAY_VCC

CV33

1

2

20 21 22 23

1

CV34

2

10U_0603_6.3V6M

21

+3VS_VGA

RV101

RV100

12

10K_0402_5%

B B

HDMI_SCL<23>

HDMI_SDA<23>

A A

5

HDMI_SCL HDMI_HPD

HDMI_SDA

10K_0402_5%

2

G

DMN66D0LDW-7_SOT363-6

S

DV3

RV543

5

QV89A

34

HDMI_SCLF

SGD

DMN66D0LDW-7_SOT363-6

QV89B

61

D

4

DV4

SDM10U45-7_SOD523-2~D

RV544

1 2

2K_0402_5%

LV14,LV15 follow Echo MLK 15/17 dat.02/11

2K_0402_5%

RV545

12

33_0402_1%

27NH_LQG15HS27NJ02D_300MA_5%

RV546

12

HDMI_SDARHDMI_SDAF

33_0402_1%

27NH_LQG15HS27NJ02D_300MA_5%

LV14

1 2

LV15

1 2

Place closed to JHDMI1

CV441

HDMI_CTRLCLKHDMI_SCLR

HDMI_CTRLDAT

10P_0402_50V8J

1

CV442

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDMI_DET<22>

2015/01/06 2016/01/06

HDMI_DET

RV18

100K_0402_5%

Compal Secret Data

1 2

Deciphered Date

2

RV14 0_0402_5%@

UV16

4

O

HDMI_HPD<6>

1 2

+3VS

CV3

1 2

0.1U_0402_16V7K

5

1

P

B

2

A

G

TC7SH08FU_SSOP5~D

3

HDMI_HPD DGPU_PEX_RST#

Size Document Number Rev

Date: Sheet of

+3VS

QV5

C

2

B

E

3 1

MMST3904-7-F_SOT323~D

12

RV553 100K_0402_5%

DGPU_PEX_RST# <22>

Compal Electronics, Inc.

Title

HDMI conn

LA-C901P

RV547

1 2

150K_0402_5%

1

HDMI_HPLUG

1

CV2

0.1U_0402_16V7K

2

21 63Tuesday, August 04, 2015

1.0

5

UV1

S IC CL8064701477802 SR1EF D0 1.7G A31!

SA000084Q0L

R1N16P@

D D

C C

1 2

@

RV58 10K_0402_5%

DGPU_HOLD_RST#<11>

SOC_PLTRST#<10,34>

DGPU_HOLD_RST#

B B

DGPU_HOLD_RST# SOC_PLTRST#

+3.3V_GFX_AON

1 2

RV69 10K_0402_5%

SYS_PEX_RST_MON#

GPU_PEX_RST_HOLD#

UV1

S IC CL8064701477802 SR1EF D0 1.7G A31!

SA000084Q1L

R3N16P@

+3VALW

1

CV212

2

@

0.1U_0402_10V7K

5

1

P

B

O

2

A

G

UV14

3

TC7SH08FU_SSOP5~D

DV8

2

3

BAT54A-7-F_SOT23-3

4

+3.3V_GFX_AON

12

1

10K_0402_5%

RV39

SYS_PEX_RST_MON#

12

0_0402_5%

12

RV208

@

RV187 10K_0402_5%

PEG_CRX_GTX_P0_GPU<34> PEG_CRX_GTX_N0_GPU<34> PEG_CRX_GTX_P1_GPU<34> PEG_CRX_GTX_N1_GPU<34> PEG_CRX_GTX_P2_GPU<34> PEG_CRX_GTX_N2_GPU<34> PEG_CRX_GTX_P3_GPU<34> PEG_CRX_GTX_N3_GPU<34>

DGPU_PEX_RST# <21>

GC6 2.0 function

2 1 2

1 3

D

RV56 10K_0402_5%

G

S

+3.3V_GFX_AON

1 2

RV57 10K_0402_5%

CLK_REQ

NVVDD_PWR_GD<56,57>

A A

CLKREQ_PCIE#0<10,34>

5

QV12

2N7002H 1N_SOT23-3

4

PEG_CTX_GRX_P0_GPU<34> PEG_CTX_GRX_N0_GPU<34> PEG_CTX_GRX_P1_GPU<34> PEG_CTX_GRX_N1_GPU<34> PEG_CTX_GRX_P2_GPU<34> PEG_CTX_GRX_N2_GPU<34> PEG_CTX_GRX_P3_GPU<34> PEG_CTX_GRX_N3_GPU<34>

1 2

CV54 0. 22U_0402_10V6K

1 2

CV55 0. 22U_0402_10V6K

1 2

CV56 0. 22U_0402_10V6K

1 2

CV57 0. 22U_0402_10V6K

1 2

CV58 0. 22U_0402_10V6K

1 2

CV59 0. 22U_0402_10V6K

1 2

CV60 0. 22U_0402_10V6K

1 2

CV61 0. 22U_0402_10V6K

CLK_PEG_N15P<34>

CLK_PEG_N15P#<34>

1 2

RV47 200_0402_1%

DGPU_PEX_RST#

4

1 2 1 2

RV40 0_0402_1% RV50 2.49K_0402_1%

VGA_SMB_CK2

VGA_SMB_DA2

@

2N7002DW-T/R7_SOT363-6 QV1A

PEG_CRX_GTX_C_P0 PEG_CRX_GTX_C_N0 PEG_CRX_GTX_C_P1 PEG_CRX_GTX_C_N1 PEG_CRX_GTX_C_P2 PEG_CRX_GTX_C_N2 PEG_CRX_GTX_C_P3 PEG_CRX_GTX_C_N3

CLK_REQ PEX_TSTCLK_OUT

PEX_TSTCLK_OUT# DGPU_PEX_RST#_R

PEX_TERMP

SYS_PEX_RST_MON#

5

4

2N7002DW-T/R7_SOT363-6 QV1B

2

61

AN12

AM12

AN14

AM14

AP14 AP15 AN15

AM15

AN17

AM17

AP17 AP18 AN18

AM18

AN20

AM20

AP20 AP21 AN21

AM21

AN23

AM23

AP23 AP24 AN24

AM24

AN26

AM26

AP26 AP27 AN27

AM27

AK14

AJ14 AH14 AG14 AK15

AJ15

AL16 AK16 AK17

AJ17 AH17 AG17 AK18

AJ18

AL19 AK19 AK20

AJ20 AH20 AG20 AK21

AJ21

AL22 AK22 AK23

AJ23 AH23 AG23 AK24

AJ24

AL25 AK25

AJ11

AL13 AK13 AK12

AJ26 AK26

AJ12 AP29

3

UV1A

PEX_RX0 PEX_RX0_N PEX_RX1 PEX_RX1_N PEX_RX2 PEX_RX2_N PEX_RX3 PEX_RX3_N PEX_RX4 PEX_RX4_N PEX_RX5 PEX_RX5_N PEX_RX6 PEX_RX6_N PEX_RX7 PEX_RX7_N PEX_RX8 PEX_RX8_N PEX_RX9 PEX_RX9_N PEX_RX10 PEX_RX10_N PEX_RX11 PEX_RX11_N PEX_RX12 PEX_RX12_N PEX_RX13 PEX_RX13_N PEX_RX14 PEX_RX14_N PEX_RX15 PEX_RX15_N

PEX_TX0 PEX_TX0_N PEX_TX1 PEX_TX1_N PEX_TX2 PEX_TX2_N PEX_TX3 PEX_TX3_N PEX_TX4 PEX_TX4_N PEX_TX5 PEX_TX5_N PEX_TX6 PEX_TX6_N PEX_TX7 PEX_TX7_N PEX_TX8 PEX_TX8_N PEX_TX9 PEX_TX9_N PEX_TX10 PEX_TX10_N PEX_TX11 PEX_TX11_N PEX_TX12 PEX_TX12_N PEX_TX13 PEX_TX13_N PEX_TX14 PEX_TX14_N PEX_TX15 PEX_TX15_N

NC PEX_REFCLK

PEX_REFCLK_N PEX_CLKREQ_N

PEX_TSTCLK_OUT PEX_TSTCLK_OUT_N

PEX_RST_N PEX_TERMP

N116P-GX_BGA908

@

EC_SMB_CK2 <8, 40,41,46>

EC_SMB_DA2 <8, 40,41,46>

3

Part 1 of 7

GPIO

DACs

PCI EXPRESS

CLK

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_HSYNC

DACA_VSYNC

DACA_VDD DACA_VREF DACA_RSET

I2CA_SCL I2CA_SDA

I2CB_SCL I2CB_SDA

I2CC_SCL I2CC_SDA

I2C

I2CS_SCL I2CS_SDA

PLLVDD

SP_PLLVDD

VID_PLLVDD

XTAL_IN

XTAL_OUT

XTAL_OUTBUFF

XTAL_SSIN

P6 M3 L6 P5 P7 L7 M7 N8 L3 M2 L1 M5 N3 M4 N4 P2 R8 M6 R1 P3 P4 P1

AK9 AL10 AL9

AM9 AN9

AG10 AP9 AP8

R4 R5

R7 R6

R2 R3

T4 T3

AD8 AE8 AD7

H3 H2

J4 H1

Internal Thermal Sensor

3

2

GPU_GC6_FB_EN

3V3_MAIN_EN GC6_EVENT#_D

SYS_PEX_RST_MON# THERMAL_ALERT# MEM_VREF NVVDD PWM_VID GPU_LEVEL NVVDD PSI

HDMI_DET

GPU_PEX_RST_HOLD#

VGA_CRT_CLK VGA_CRT_DATA

RV510 1.8K_0402_5%

RV511 1.8K_0402_5%

I2CB_SCL I2CB_SDA

RV512 1.8K_0402_5%

RV513 1.8K_0402_5%

VGA_EDID_CLK VGA_EDID_DATA

RV514 1.8K_0402_5%

RV515 1.8K_0402_5%

VGA_SMB_CK2 VGA_SMB_DA2

W=78mils

+PLLVDD

W=71mils W=41mils

XTALIN XTAL_OUT

XTALOUT

1 2

XTALSSIN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

GPU_GC6_FB_EN <11,25>

3V3_MAIN_EN <25,56,57>

NVVDD PWM_VID <57> NVVDD PSI <57>

HDMI_DET <21>

THERMAL_ALERT#

OVERT#<23>

1 2

RV4910K_0402_5%

OVERT#

1 2 1 2

@

RV45 0_0402_5%

+SP_PLLVDD

12

RV51

10K_0402_5%

1 2

RV52 10M_0402_5%

YV1 27MHZ_10PF_7V27000050

1

XTALIN XTAL_OUT

1

CV70 10P_0402_50V8J

3

GND

2

4

2015/01/06 2016/01/06

MEM_VREF <27,28>

RV27 100K_0402_5%~D

1 2

SYS_PEX_RST_MON#

5

3

4

2N7002DW-T/R7_SOT363-6 QV2B

SYS_PEX_RST_MON#

2

61

2N7002DW-T/R7_SOT363-6 QV2A

GPU_LEVEL

GPU_LEVEL GPU_PWR_LEVEL

3

Compal Secret Data

2

5

Y4VCC

G

3

1 2

RV71 0_0402_5%

CV71 10P_0402_50V8J

Deciphered Date

+3.3V_GFX_AON

12

@

RV70

1

B

2

A

UV15 MC74VHC1G09DFT2G_SC70-5

@

GC6_EVENT#_D

GPU_ALERT# <41>

GPU_OVERT# <41>

1

CV421

2

@

10K_0402_5%

0.1U_0402_10V7K

GPU_PWR_LEVEL

@

1 2

CV422 0.1U_0402_10V7K

LV7 BLM18PG181SN1D_2P

180 ohm (ESR=0.2) Bead

+PLLVDD

1 2

0.1U_0402_10V7K

CV72 under GPU CV73 near GPU

+1.05VS_VGA

GPU_PWR_LEVEL

1

2

1

2 1

GC6_EVENT#

DV9

SDM10U45-7_SOD523-2~D

THERMAL_ALERT# SYS_PEX_RST_MON# GPU_PEX_RST_HOLD# 3V3_MAIN_EN GC6_EVENT#_D GPU_LEVEL NVVDD PSI

GC6_EVENT# <11>

1 2

RV526 10K_0402_5%

1 2

@

RV532 10K_0402_5%

1 2

RV41 10K_0402_5%

1 2

RV55 10K_0402_1%

1 2

RV42 10K_0402_5%

12

@

RV60 100K_0402_5%~D

1 2

RV35 10K_0402_1%

<Dell's requirement>

VGA_SMB_CK2 VGA_SMB_DA2

GPU_GC6_FB_EN MEM_VREF

Low High

GPU_PWR_LEVEL <41> ACIN <10,37,41,51,52>

1 2

RV191 1.8K_0402_5%

1 2

RV192 1.8K_0402_5%

1 2

RV37 10K_0402_5% RV38 100K_0402_5%~D@

Low Performace High Performace

12

150mA

1

CV50

CV51

2

22U_0805_6.3V6M

4.7U_0402_6.3V6M

1 2

LV8

1

CV72

BLM18PG181SN1D_2P

CV73

2

30 ohm@100MHz (ESR=0.05)

22U_0805_6.3V6M

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

N16P_PCIE/DAC/GPIO

N16P_PCIE/DAC/GPIO LA-C901P

LA-C901P

1

CV52

CV53

2

0.1U_0402_10V7K

Under GPU (below 150mils)

+1.05VS_VGA

1

+3.3V_GFX_AON

+3VS_VGA

+SP_PLLVDD

22 63Tuesday, August 04, 2015

1.0

5

4

3

2

1

UV1D

AM6

IFPA_TXC

AN6

IFPA_TXC_N

AP3

IFPA_TXD0

D D

DDI1_LANE_P0<21> DDI1_LANE_N0<21> DDI1_LANE_P1<21> DDI1_LANE_N1<21> DDI1_LANE_P2<21> DDI1_LANE_N2<21> DDI1_LANE_P3<21>

C C

B B

DDI1_LANE_N3<21>

HDMI_SCL<21> HDMI_SDA<21>

HDMI_SCL

HDMI_SDA

AN3

IFPA_TXD0_N

AN5

IFPA_TXD1

AM5

IFPA_TXD1_N

AL6

IFPA_TXD2

AK6

IFPA_TXD2_N

AJ6

IFPA_TXD3

AH6

IFPA_TXD3_N

AJ9

IFPB_TXC

AH9

IFPB_TXC_N

AP6

IFPB_TXD4

AP5

IFPB_TXD4_N

AM7

IFPB_TXD5

AL7

IFPB_TXD5_N

AN8

IFPB_TXD6

AM8

IFPB_TXD6_N

AK8

IFPB_TXD7

AL8

IFPB_TXD7_N

AK1

IFPC_L0

AJ1

IFPC_L0_N

AJ3

IFPC_L1

AJ2

IFPC_L1_N

AH3

IFPC_L2

AH4

IFPC_L2_N

AG5

IFPC_L3

AG4

IFPC_L3_N

AM1

IFPD_L0

AM2

IFPD_L0_N

AM3

IFPD_L1

AM4

IFPD_L1_N

AL3

IFPD_L2

AL4

IFPD_L2_N

AK4

IFPD_L3

AK5

IFPD_L3_N

AD2

IFPE_L0

AD3

IFPE_L0_N

AD1

IFPE_L1

AC1

IFPE_L1_N

AC2

IFPE_L2

AC3

IFPE_L2_N

AC4

IFPE_L3

AC5

IFPE_L3_N

AE3

IFPF_L0

AE4

IFPF_L0_N

AF4

IFPF_L1

AF5

IFPF_L1_N

AD4

IFPF_L2

AD5

IFPF_L2_N

AG1

IFPF_L3

AF1

IFPF_L3_N

AG3

IFPC_AUX_I2CW_SCL

AG2

IFPC_AUX_I2CW_SDA_N

AK3

IFPD_AUX_I2CX_SCL

AK2

IFPD_AUX_I2CX_SDA_N

AB3

IFPE_AUX_I2CY_SCL

AB4

IFPE_AUX_I2CY_SDA_N

AF3

IFPF_AUX_I2CZ_SCL

AF2

IFPF_AUX_I2CZ_SDA_N

Part 4 of 7

3V3AUX_NC

VDD_SENSE

GND_SENSE

TEST

JTAG_TRST_N

SERIAL

LVDS/TMDS

GENERAL

MULTI_STRAP_REF0_GND

NC

TESTMODE

JTAG_TCK

JTAG_TDI JTAG_TDO JTAG_TMS

ROM_CS_N ROM_SCLK

ROM_SI

ROM_SO

BUFRST_N

OVERT

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

THERMDP

THERMDN

P8 AC6

NC

AJ28

NC

AJ4

NC

AJ5

NC

AL11

NC

C15

NC

D19

NC

D20

NC

D23

NC

D26

NC

H31

NC

T8

NC

V32

NC

L4

L5

AK11

TESTMODE

AM10

GPU_JTAG_TCK

AM11

GPU_JTAG_TDI

AP12

GPU_JTAG_TDO

AP11

GPU_JTAG_TMS

AN11

GPU_JTAG_TRST#

H6

ROM_CS

H4

ROM_SCLK

H5

ROM_SI

H7

ROM_SO

L2

RV64 10K_0402_5%

M1 J1

RV66 40.2K_0402_1%

J2 J7 J6 J5 J3

K3 K4

trace width: 16mils differential voltage sensing. differential signal routing.

VCCSENSE_VGA

VSSSENSE_VGA

OVERT#

1 2

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

1 2

12

VCCSENSE_VGA <57>

VSSSENSE_VGA <57>

T98PAD~D @ T99PAD~D @ T100PAD~D @ T101PAD~D @

RV63 10K_0402_5%

ROM_CS <29> ROM_SCLK <29> ROM_SI <29> ROM_SO <29>

STRAP0 <29> STRAP1 <29> STRAP2 <29> STRAP3 <29> STRAP4 <29>

12

RV62 10K_0402_5%

+3.3V_GFX_AON

RV34 10K_0402_5%

1 2

OVERT# <22>

N116P-GX_BGA908

@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

N16P_HDMI

N16P_HDMI LA-C901P

LA-C901P

1.0

of

23 63Tuesday, August 04, 2015

of

23 63Tuesday, August 04, 2015

of

23 63Tuesday, August 04, 2015

1

5

4

3

2

1

+1.35VS_VGA

D D

+1.35VS_VGA

1

CV100

2

1U_0402_6.3V6K

+1.35VS_VGA

C C

+1.05VS_VGA

+3.3V_GFX_AON

B B

LV16

BLM18PG181SN1D_0603

LV17

BLM18PG181SN1D_0603

For GDDR5 setting. Near GPU

1

CV75

CV74

2

4.7U_0603_6.3V6K

1

CV76

CV110

2

4.7U_0603_6.3V6K

Under GPU(below 150mils)

1

CV101

CV102

2

1U_0402_6.3V6K

1

CV103

CV112

2

1U_0402_6.3V6K

Under GPU(below 150mils)

1

CV211

2

1U_0402_6.3V6K

12

IFP_IOVDD

1

CV428

CV216

2

4.7U_0603_6.3V6K

12

1

CV430

CV217

2

4.7U_0603_6.3V6K

1

CV210

2

0.1U_0402_10V7K

1U_0402_6.3V6K

1

2

1

2

1

CV429

CV434

2

0.1U_0402_10V7K

1U_0402_6.3V6K

IFP_PLLVDD

1

CV432

CV431

2

1U_0402_6.3V6K

0.1U_0402_10V7K

1

2

CV77

2

4.7U_0603_6.3V6K

1

CV113

2

1U_0402_6.3V6K

1

CV209

2

0.1U_0402_10V7K

CV435

0.1U_0402_10V7K

CV433

0.1U_0402_10V7K

2

CV78

CV79

CV80

1

10U_0603_6.3V6M

1

CV104

2

0.1U_0402_10V7K

1

CV206

CV207

2

0.1U_0402_10V7K

1

CV437

CV436

2

0.1U_0402_10V7K

1

2

0.1U_0402_10V7K

1

CV106

CV105

2

0.1U_0402_10V7K

1

CV208

CV205

2

0.1U_0402_10V7K

1

CV438

2

0.1U_0402_10V7K

1

2

22U_0805_6.3V6M

1

2

0.1U_0402_10V7K

1

2

0.1U_0402_10V7K

+1.35VS_VGA

1

CV84

CV83

2

22U_0805_6.3V6M

1

CV107

CV108

2

0.1U_0402_10V7K

1

CV203

CV215

2

0.1U_0402_10V7K

1 2

RV77 40.2_0402_1%

1 2

RV78 40.2_0402_1%

1 2

RV79 60.4_0402_1%

Place near balls

1

CV85

CV86

2

22U_0805_6.3V6M

1

CV109

2

0.1U_0402_10V7K

1

CV204

2

0.1U_0402_10V7K

AA27 AA30 AB27 AB33 AC27 AD27 AE27 AF27 AG27

M27

W27 W30 W33

B13 B19 E13 E19 H10 H11 H12 H13 H14 H18 H19 H20 H21 H22 H23 H24

H8 H9

L27 N27

P27 R27 T27 T30 T33 Y27

B16 E16 H15 H16 V27

F1

F2

J27

H27

H25

@

UV1E

Part 5 of 7

FBVDDQ_0 FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_11 FBVDDQ_12 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37 FBVDDQ_38 FBVDDQ_43

FBVDDQ_AON FBVDDQ_AON FBVDDQ_AON FBVDDQ_AON FBVDDQ_AON FBVDDQ_AON FBVDDQ_AON FBVDDQ_AON

FB_VDDQ_SENSE

FB_GND_SENSE

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

PEX_IOVDD_0 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5

PEX_IOVDDQ_0 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8

PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13

PEX_PLL_HVDD

PEX_SVDD_3V3

PEX_PLLVDD

POWER

IFPAB_PLLVDD

IFPAB_RSET

IFPC_PLLVDD

IFPC_IOVDD

IFPD_PLLVDD

IFPD_IOVDD

IFPEF_PLVDD

IFPEF_RSET IFPE_IOVDD

IFPF_IOVDD

3V3_AON

3V3_AON 3V3_MAIN 3V3_MAIN

IFPA_IOVDD IFPB_IOVDD

IFPC_RSET

AG19 AG21 AG22 AG24 AH21 AH25

AG13 AG15 AG16 AG18 AG25 AH15 AH18 AH26 AH27 AJ27 AK27 AL27 AM28 AN28

AH12

AG12

AG26

150mA

+3.3V_GFX_AON

J8 K8

85mA

L8 M8

AH8

1 2

AJ8

1 2

AG8 AG9

1 2

AF7

IFP_PLLVDD

AF8

1 2

RV549 1K_0402_1%

AF6

IFP_IOVDD

AG7

IFP_PLLVDD

AN2

NC

AG6

IFP_IOVDD

AB8 AD6

1 2

RV550 1K_0402_1%@

AC7 AC8

3500mA

1

2

1U_0402_6.3V6K

1

2

22U_0805_6.3V6M

+3.3V_GFX_AON

+3VS_VGA

RV551

RV548 RV552

0_0402_5%

RV554

1 2

0_0402_5%

CV96

0_0402_5%@

@

CV87

1

2

22U_0805_6.3V6M

1K_0402_1%@

IFP_IOVDD

@

Under GPU

1

CV88

2

1U_0402_6.3V6K

1

CV97

CV98

2

22U_0805_6.3V6M

Near GPU

210mA

IFP_PLLVDD

IFP_IOVDD

22U_0805_6.3V6M

1

2

CV89

1

CV99

2

85mA

Near GPU

2

1

CV91

CV90

2

4.7U_0603_6.3V6K

1U_0402_6.3V6K

+1.05VS_VGA

2

1

CV93

CV92

1

2

10U_0603_6.3V6M

4.7U_0603_6.3V6K

+3.3V_GFX_AON

2

CV94

CV95

1

10U_0603_6.3V6M

+1.05VS_VGA

2

CV111

1

10U_0603_6.3V6M

+3.3V_GFX_AON

Place near balls Place near GPU

1

CV114

2

0.1U_0402_10V7K

1

CV116

CV115

2

4.7U_0603_6.3V6K

1

2

0.1U_0402_10V7K

+3VS_VGA

CV202

1

CV214

CV213

2

4.7U_0603_6.3V6K

1U_0402_6.3V6K

Place near balls Place near GPU

1

CV117

CV118

2

0.1U_0402_10V7K

1

CV119

CV120

2

4.7U_0603_6.3V6K

1U_0402_6.3V6K

+1.05VS_VGA

150mA

1

CV121

2

0.1U_0402_10V7K

1

CV122

CV123

2

1U_0603_10V6K

4.7U_0805_25V6-K

Place near balls

CALIBRATION PIN GDDR5 FB_CAL_x_PD_VDDQ FB_CAL_x_PU_GND FB_CAL_xTERM_GND

A A

5

4

40.2 ohm

60.4 ohm

+5VALW

+3VS

12

RV528 10K_0402_5%

DGPU_PWR_EN<11>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

2

RV68

100K_0402_5%

@

12

13

D

2

G

S

+3.3V_GFX_AON

+3VS

RV184 100K_0402_5%

DGPU_PWR_EN#

QV87 DMN65D8LW-7_SOT323-3

Title

N16P_Power

Size Document Number Rev

LA-C901P

Date: Sheet of

QV86

LP2301ALT1G_SOT23-3

Compal Electronics, Inc.

+3.3V_GFX_AON

D

S

123

G

0.1U_0402_25V6 CV363

12

24 63Tuesday, August 04, 2015

1

24 63Tuesday, August 04, 2015

1.0

5

58+30%A

+VGA_CORE

D D

C C

B B

+VGA_CORE

4.7U_0603_6.3V6K

UV1G

VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55

16P-GX_BGA908

N1

@

CV406

4.7U_0603_6.3V6K

1

2

Part 7 of 7

CV407

4.7U_0603_6.3V6K

1

2

AA12 AA14 AA16 AA19 AA21 AA23 AB13 AB15 AB17 AB18 AB20 AB22 AC12 AC14 AC16 AC19 AC21 AC23

M12 M14 M16 M19 M21 M23 N13 N15 N17 N18 N20 N22 P12 P14 P16 P19 P21 P23 R13 R15 R17 R18 R20 R22 T12 T14 T16 T19 T21 T23 U13 U15 U17 U18 U20 U22 V13 V15

CV419

CV405

4.7U_0603_6.3V6K

1

2

VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71

XVDD_1 XVDD_2 XVDD_3 XVDD_4 XVDD_5 XVDD_6 XVDD_7 XVDD_8

XVDD_9 XVDD_10 XVDD_11 XVDD_12 XVDD_13 XVDD_14 XVDD_15

POWER

XVDD_16

XVDD_17 XVDD_18 XVDD_19 XVDD_20 XVDD_21 XVDD_22

XVDD_23 XVDD_24 XVDD_25 XVDD_26 XVDD_27

22U_0805_6.3VAM

CV408

4.7U_0603_6.3V6K

CV409

4.7U_0603_6.3V6K

1

2

+VGA_CORE

V17 V18 V20 V22 W12 W14 W16 W19 W21 W23 Y13 Y15 Y17 Y18 Y20 Y22

U1 U2 U3 U4 U5 U6 U7 U8

V1 V2 V3 V4 V5 V6 V7 V8

W2 W3 W4 W5 W7 W8

Y1

NC

Y2

NC

Y3

NC

Y4 Y5 Y6 Y7 Y8

AA1

NC

AA2

NC

AA3

NC

AA4

NC

AA5

NC

AA6

NC

AA7

NC

AA8

NC

CV410

CV411

22U_0805_6.3VAM

1

2

CV413

22U_0805_6.3VAM

CV412

22U_0805_6.3VAM

1

2

1

2

4

3V3_MAIN_EN<22,56,57>

330U_D3_2.5VY_R6M

1

22U_0805_6.3VAM

1

2

1

2

NVVDD_PWR_GD<56,57>

GPU_GC6_FB_EN<11,22>

CV416

22U_0805_6.3VAM

CV415

22U_0805_6.3VAM

CV414

1

CV417

CV418

+

2

DV7

NVVDD_PWR_GD

3

2

BAT54CW-7-F SOT-323

1

+3VS

3V3_MAIN_EN

+5VS

200K_0402_5%

12

3

+3VS_VGA

UV11

1

VIN

2

VIN

3

ON

4

VBIAS

AOZ1336_DFN8_2X2

VOUT VOUT

CT

GND GND

+3VS_VGA

60mil

7 8

6

5 9

1

CV4

4.7U_0402_6.3V6M

@

2

+1.35VS_VGA

B+_BIAS

+5VALW

470K_0402_5%

@

12

RV183

+3VALW

100K_0402_5%

12

RV182

DGPU_PWR_ON#

DMN66D0LDW-7_SOT363-6

6

QV84A

2

1

RV209

RV529

DMN66D0LDW-7_SOT363-6

34

QV84B

5

DGPU_PWR_ON

2.2M_0402_5%

12

RV180

QV83 AON6508_SON8-5

5

0.047U_0402_25V CV366

1

2

4

2

UV1F

A2

GND_0

AA17

GND_1

AA18

GND_2

AA20

GND_3

AA22

GND_4

AB12

GND_5

AB14

GND_6

AB16

GND_7

AB19

GND_8

AB2

GND_9

AB21

GND_10

A33

GND_11

AB23

GND_12

AB28

GND_13

AB30

GND_14

AB32

GND_15

AB5

GND_16

AB7

GND_17

AC13

GND_18

AC15

GND_19

AC17

GND_20

AC18

GND_21

AA13

GND_22

AC20

GND_23

AC22

GND_24

AE2

GND_25

AE28

GND_26

AE30

GND_27

AE32

GND_28

AE33

GND_29

AE5

GND_30

AE7

GND_31

AH10

GND_32

AA15

GND_33

AH13

GND_34

AH16

GND_35

AH19

GND_36

AH2

GND_37

AH22

GND_38

AH24

GND_39

AH28

GND_40

AH29

GND_41

AH30

GND_42

AH32

GND_43

AH33

GND_44

AH5

GND_45

AH7

GND_46

AJ7

GND_47

AK10

GND_48

AK7

GND_49

AL12

GND_50

AL14

GND_51

AL15

GND_52

AL17

GND_53

AL18

GND_54

AL2

GND_55

AL20

GND_56

AL21

GND_57

AL23

GND_58

AL24

GND_59

AL26

GND_60

AL28

GND_61

AL30

GND_62

AL32

GND_63

AL33

GND_64

AL5

GND_65

AM13

GND_66

AM16

GND_67

AM19

GND_68

AM22

GND_69

AM25

GND_70

AN1

GND_71

AN10

GND_72

AN13

GND_73

AN16

GND_74

AN19

GND_75

AN22

GND_76

AN25

GND_77

AN30

GND_78

AN34

GND_79

AN4

GND_80

AN7

GND_81

AP2

+1.35VS_VGA+1.35V_VDDQ

1 2 3

20K_0402_5%

10U_0603_6.3V6M

12

RV181@

CV365

12

AP33

B1 B10 B22 B25 B28 B31 B34

B4

B7

C10 C13 C19 C22 C25 C28

C7

GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 GND_97 GND_98 GND_99

N116P-GX_BGA908

@

Part 6 of 7

1

GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153

GND

GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 GND_193 GND_194 GND_195 GND_196 GND_197 GND_198

GND_199 GND_OPT GND_OPT

D2 D31 D33 E10 E22 E25 E5 E7 F28 F7 G10 G13 G16 G19 G2 G22 G25 G28 G3 G30 G32 G33 G5 G7 K2 K28 K30 K32 K33 K5 K7 M13 M15 M17 M18 M20 M22 N12 N14 N16 N19 N2 N21 N23 N28 N30 N32 N33 N5 N7 P13 P15 P17 P18 P20 P22 R12 R14 R16 R19 R21 R23 T13 T15 T17 T18 T2 T20 T22 AG11 T28 T32 T5 T7 U12 U14 U16 U19 U21 U23 V12 V14 V16 V19 V21 V23 W13 W15 W17 W18 W20 W22 W28 Y12 Y14 Y16 Y19 Y21 Y23 AH11 C16 W32

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT C ONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT C ONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

N16P_VGA CORE/GND

LA-C901P

1

25 63Tuesday, August 04, 2015

1.0

5

4

3

2

1

FBA_D[0..63]<27>

30ohms (ESR=0.01) Bead

D D

C C

B B

A A

P/N;SM010007W00

+1.05VS_VGA +FB_PLLAVDD

1 2

300mA

LV13 PBY160808T-300Y-N_2P

+FB_PLLAVDD

22U_0805_6.3V6M~D

CV151

1

2

FBA_AVDD_1.05_3.3V

1 2

@

RV97 0_0402_1%

FBA_EDC[7..0]<27>

FBA_DBI0#<27>

FBA_DBI1#<27> FBA_DBI2#<27> FBA_DBI3#<27>

FBA_DBI4#<27>

FBA_DBI5#<27> FBA_DBI6#<27> FBA_DBI7#<27>

FBA_D[0..63]

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8

FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DBI0# FBA_DBI1# FBA_DBI2# FBA_DBI3# FBA_DBI4# FBA_DBI5# FBA_DBI6# FBA_DBI7#

FBA_EDC0 FBA_EDC1 FBA_EDC2 FBA_EDC3 FBA_EDC4 FBA_EDC5 FBA_EDC6 FBA_EDC7

AM29 AM31

AM30

AM33

AM32

AM34

AG28 AF29 AG29 AF28 AD30 AD29 AC29 AD28

AK29 AK28

AN29 AN31

AN32 AP30 AP32

AK33 AK32 AD34 AD32 AC30 AD33 AF31 AG34 AG32 AG33

AD31

AF34

AE31 AK30 AN33 AF33

AF30 AK31

AF32

L28

M29

L29

M28

N31 P29 R29 P28 J28 H29 J29 H28 G29 E31 E32 F30 C34 D32 B33 C33 F33 F32 H33 H32 P34 P32 P31 P33 L31 L34 L32 L33

AJ29 AJ30

AL31

P30 F31 F34

M32

AL29

M31

G31 E33

M33

M30

H30 E34

M34

UV1B

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

N116P-GX_BGA908

@

Part 2 of 7

MEMORY INTERFACE

FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31 FBA_CMD32 FBA_CMD33 FBA_CMD34 FBA_CMD35

FBA_CLK0_N FBA_CLK1_N

A

FBA_WCK01

FBA_WCK01_N

FBA_WCK23

FBA_WCK23_N

FBA_WCK45

FBA_WCK45_N

FBA_WCK67

FBA_WCK67_N

FB_DLL_AVDD

FBA_PLL_AVDD

U30 T31 U29 R34 R33 U32 U33 U28 V28 V29 V30 U34 U31 V34 V33 Y32 AA31 AA29 AA28 AC34 AC33 AA32 AA33 Y28 Y29 W31 Y30 AA34 Y31 Y34 Y33 V31 R28 AC28 R32 AC32

R30 R31 AB31 AC31

K31 L30 H34 J34 AG30 AG31 AJ34 AK34

J30

NC

J31

NC

J32

NC

J33

NC

AH31

NC

AJ31

NC

AJ32

NC

AJ33

NC

RV104 10K_0402_5%

E1

K27

U27

H26

FBA_CS#_L FBA_MA3_BA3_L FBA_MA2_BA0_L FBA_MA4_BA2_L FBA_MA5_BA1_L FBA_WE#_L FBA_MA7_MA8_L FBA_MA6_MA11_L FBA_ABI#_L FBA_MA12_RFU_L FBA_MA0_MA10_L FBA_MA1_MA9_L FBA_RAS#_L FBA_RST#_L FBA_CKE_L FBA_CAS#_L FBA_CS#_H FBA_MA3_BA3_H FBA_MA2_BA0_H FBA_MA4_BA2_H FBA_MA5_BA1_H FBA_WE#_H FBA_MA7_MA8_H FBA_MA6_MA11_H FBA_ABI#_H FBA_MA12_RFU_H FBA_MA0_MA10_H FBA_MA1_MA9_H FBA_RAS#_H FBA_RST#_H FBA_CKE_H FBA_CAS#_H

FBA_CLK0 FBA_CLK0# FBA_CLK1 FBA_CLK1#

CV152 0.1U_0402_10V7K

FBA_WCK0 FBA_WCK0_N FBA_WCK1 FBA_WCK1_N FBA_WCK2 FBA_WCK2_N FBA_WCK3 FBA_WCK3_N

1 2

12

FBA_CLK0 <27> FBA_CLK0# <27> FBA_CLK1 <27> FBA_CLK1# <27>

Place close to ball

1

CV154

2

0.1U_0402_10V7K

+FB_PLLAVDD

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9

FBA_CLK0 FBA_CLK1

FB_CLAMP

FB_VREF

Place close to ball Place close to BGA

FBA_RST#_L FBA_RST#_H

12

RV107 10K_0402_5%

FBA_CS#_L <27> FBA_MA3_BA3_L <27> FBA_MA2_BA0_L <27> FBA_MA4_BA2_L <27> FBA_MA5_BA1_L <27> FBA_WE#_L <27> FBA_MA7_MA8_L <27> FBA_MA6_MA11_L <27> FBA_ABI#_L <27> FBA_MA12_RFU_L <27> FBA_MA0_MA10_L <27> FBA_MA1_MA9_L <27> FBA_RAS#_L <27> FBA_RST#_L <27>

FBA_CAS#_L <27> FBA_CS#_H <27> FBA_MA3_BA3_H <27> FBA_MA2_BA0_H <27> FBA_MA4_BA2_H <27> FBA_MA5_BA1_H <27> FBA_WE#_H <27> FBA_MA7_MA8_H <27> FBA_MA6_MA11_H <27> FBA_ABI#_H <27> FBA_MA12_RFU_H <27> FBA_MA0_MA10_H <27> FBA_MA1_MA9_H <27> FBA_RAS#_H <27> FBA_RST#_H <27>

FBA_CAS#_H <27>

FBA_WCK0 <27> FBA_WCK0_N <27> FBA_WCK1 <27> FBA_WCK1_N <27> FBA_WCK2 <27> FBA_WCK2_N <27> FBA_WCK3 <27> FBA_WCK3_N <27>

50mA

PLL_AVDD

1

CV155

CV156

2

22U_0805_6.3V6M

1U_0402_6.3V6K

12

RV108 10K_0402_5%

+1.35VS_VGA

12

+1.35VS_VGA

12

FBC_EDC[7..0]<28>

120mA

FBC_RST#_L FBC_RST#_H

RV95 10K_0402_5%

FBA_CKE_L <27>

RV98 10K_0402_5%

FBA_CKE_H <27>

FBC_DBI0#<28>

FBC_DBI1#<28> FBC_DBI2#<28> FBC_DBI3#<28>

FBC_DBI4#<28>

FBC_DBI5#<28> FBC_DBI6#<28> FBC_DBI7#<28>

12

RV110 10K_0402_5%

FBC_D[0..63]<28>

12

RV111 10K_0402_5%

FBC_D0 FBC_D1 FBC_D2 FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7 FBC_D8

FBC_D9 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63

FBC_DBI0# FBC_DBI1# FBC_DBI2# FBC_DBI3# FBC_DBI4# FBC_DBI5# FBC_DBI6# FBC_DBI7#

FBC_EDC0 FBC_EDC1 FBC_EDC2 FBC_EDC3 FBC_EDC4 FBC_EDC5 FBC_EDC6 FBC_EDC7

FBC_D[0..63]

G9

FBB_D0

E9

FBB_D1

G8

FBB_D2

F9

FBB_D3

F11

FBB_D4

G11

FBB_D5

F12

FBB_D6

G12

FBB_D7

G6

FBB_D8

F5

FBB_D9

E6

FBB_D10

F6

FBB_D11

F4

FBB_D12

G4

FBB_D13

E2

FBB_D14

F3

FBB_D15

C2

FBB_D16

D4

FBB_D17

D3

FBB_D18

C1

FBB_D19

B3

FBB_D20

C4

FBB_D21

B5

FBB_D22

C5

FBB_D23

A11

FBB_D24

C11

FBB_D25

D11

FBB_D26

B11

FBB_D27

D8

FBB_D28

A8

FBB_D29

C8

FBB_D30

B8

FBB_D31

F24

FBB_D32

G23

FBB_D33

E24

FBB_D34

G24

FBB_D35

D21

FBB_D36

E21

FBB_D37

G21

FBB_D38

F21

FBB_D39

G27

FBB_D40

D27

FBB_D41

G26

FBB_D42

E27

FBB_D43

E29

FBB_D44

F29

FBB_D45

E30

FBB_D46

D30

FBB_D47

A32

FBB_D48

C31

FBB_D49

C32

FBB_D50

B32

FBB_D51

D29

FBB_D52

A29

FBB_D53

C29

FBB_D54

B29

FBB_D55

B21

FBB_D56

C23

FBB_D57

A21

FBB_D58

C21

FBB_D59

B24

FBB_D60

C24

FBB_D61

B26

FBB_D62

C26

FBB_D63

E11

FBB_DQM0

E3

FBB_DQM1

A3

FBB_DQM2

C9

FBB_DQM3

F23

FBB_DQM4

F27

FBB_DQM5

C30

FBB_DQM6

A24

FBB_DQM7

D10

FBB_DQS_WP0

D5

FBB_DQS_WP1

C3

FBB_DQS_WP2

B9

FBB_DQS_WP3

E23

FBB_DQS_WP4

E28

FBB_DQS_WP5

B30

FBB_DQS_WP6

A23

FBB_DQS_WP7

D9

FBB_DQS_RN0

E4

FBB_DQS_RN1

B2

FBB_DQS_RN2

A9

FBB_DQS_RN3

D22

FBB_DQS_RN4

D28

FBB_DQS_RN5

A30

FBB_DQS_RN6

B23

FBB_DQS_RN7

N116P-GX_BGA908

@

UV1C

Part 3 of 7

MEMORY INTERFACE B

FBB_PLL_AVDD

FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8

FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31 FBB_CMD32 FBB_CMD33 FBB_CMD34 FBB_CMD35

FBB_CLK0

FBB_CLK0_N

FBB_CLK1

FBB_CLK1_N

FBB_WCK01

FBB_WCK01_N

FBB_WCK23

FBB_WCK23_N

FBB_WCK45

FBB_WCK45_N

FBB_WCK67

FBB_WCK67_N

D13 E14 F14 A12 B12 C14 B14 G15 F15 E15 D15 A14 D14 A15 B15 C17 D18 E18 F18 A20 B20 C18 B18 G18 G17 F17 D16 A18 D17 A17 B17 E17 G14 G20 C12 C20

D12 E12 E20 F20

F8 E8 A5 A6 D24 D25 B27 C27

D6

NC

D7

NC

C6

NC

B6

NC

F26

NC

E26

NC

A26

NC

A27

NC

H17

FBC_CS#_L FBC_MA3_BA3_L FBC_MA2_BA0_L FBC_MA4_BA2_L FBC_MA5_BA1_L FBC_WE#_L FBC_MA7_MA8_L FBC_MA6_MA11_L FBC_ABI#_L FBC_MA12_RFU_L FBC_MA0_MA10_L FBC_MA1_MA9_L FBC_RAS#_L FBC_RST#_L FBC_CKE_L FBC_CAS#_L FBC_CS#_H FBC_MA3_BA3_H FBC_MA2_BA0_H FBC_MA4_BA2_H FBC_MA5_BA1_H FBC_WE#_H FBC_MA7_MA8_H FBC_MA6_MA11_H FBC_ABI#_H FBC_MA12_RFU_H FBC_MA0_MA10_H FBC_MA1_MA9_H FBC_RAS#_H FBC_RST#_H FBC_CKE_H FBC_CAS#_H

FBC_CLK0 FBC_CLK0# FBC_CLK1 FBC_CLK1#

FBC_CLK0 <28> FBC_CLK0# <28> FBC_CLK1 <28> FBC_CLK1# <28>

FBC_WCK0 FBC_WCK0_N FBC_WCK1 FBC_WCK1_N FBC_WCK2 FBC_WCK2_N FBC_WCK3 FBC_WCK3_N

FBA_AVDD_1.05_3.3V +3.3V_GFX_AON

RV210

0_0402_5%

PLL_AVDD

1

CV153

2

0.1U_0402_10V7K

Place close to ball

FBC_CS#_L <28> FBC_MA3_BA3_L <28> FBC_MA2_BA0_L <28> FBC_MA4_BA2_L <28> FBC_MA5_BA1_L <28> FBC_WE#_L <28> FBC_MA7_MA8_L <28> FBC_MA6_MA11_L <28> FBC_ABI#_L <28> FBC_MA12_RFU_L <28> FBC_MA0_MA10_L <28> FBC_MA1_MA9_L <28> FBC_RAS#_L <28> FBC_RST#_L <28>

FBC_CAS#_L <28> FBC_CS#_H <28> FBC_MA3_BA3_H <28> FBC_MA2_BA0_H <28> FBC_MA4_BA2_H <28> FBC_MA5_BA1_H <28> FBC_WE#_H <28> FBC_MA7_MA8_H <28> FBC_MA6_MA11_H <28> FBC_ABI#_H <28> FBC_MA12_RFU_H <28> FBC_MA0_MA10_H <28> FBC_MA1_MA9_H <28> FBC_RAS#_H <28> FBC_RST#_H <28>

FBC_CAS#_H <28>

FBC_WCK0 <28> FBC_WCK0_N <28> FBC_WCK1 <28> FBC_WCK1_N <28> FBC_WCK2 <28> FBC_WCK2_N <28> FBC_WCK3 <28> FBC_WCK3_N <28>

12

RV211

0_0402_5%

120mA

PU for X32 modePU for X32 mode

+1.35VS_VGA

12

RV96 10K_0402_5%

FBC_CKE_L <28>

+1.35VS_VGA

12

RV99 10K_0402_5%

FBC_CKE_H <28>

12

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

N16P_MEM Interface

N16P_MEM Interface LA-C901P

LA-C901P

1

of

26 63Tuesday, August 04, 2015

1.0

5

Memory Partition A - Lower 32 bits

FBA_D[0..63]<26>

FBA_EDC[7..0]<26>

S4G@

FBA_CLK0

FBA_CLK0#

MEM_VREF<22>

UV7

K4G41325FC-HC03

SA00007D800

UV9

K4G41325FC-HC03

SA00007D800

80.6_0402_1% RV123

1 2

Near to VRAM

+1.35VS_VGA

2

CV373

1

10U_0603_6.3V6M

S4G@

UV6

K4G41325FC-HC03

D D

SA00007D800

UV8

K4G41325FC-HC03

SA00007D800

C C

B B

A A

S4G@

2

G

10U_0603_6.3V6M

13

D

S

2N7002W-T/R7_SOT323-3

2

CV160

1

1U_0603_25V6

FBA_D[0..63] FBA_EDC[7..0]

FBA_DBI0#<26>

FBA_DBI1#<26>

FBA_DBI2#<26>

FBA_DBI3#<26>

FBA_CLK0< 26> FBA_CLK0#<26>

FBA_CKE_L<26> FBA_CKE_H<26>

FBA_MA2_BA0_L< 26>

FBA_MA5_BA1_L<26>

FBA_MA4_BA2_L< 26>

FBA_MA3_BA3_L<26>

FBA_MA7_MA8_L<26>

FBA_MA1_MA9_L<26>

FBA_MA0_MA10_L< 26>

FBA_MA6_MA11_L<26>

FBA_MA12_RFU_L<26>

RV120

121_0402_1%

FBA_ABI#_L<26>

FBA_RAS#_L<26>

FBA_CS#_L<26>

FBA_CAS#_L<26>

FBA_WE#_L<26>

FBA_WCK0_N<26>

FBA_WCK0<26>

FBA_WCK1_N<26>

FBA_WCK1<26>

+1.35VS_VGA

12

RV125

549_0402_1%

RV126

1 2

931_0402_1%

QV20

1

2

1.33K_0402_1%

CV161

1U_0603_25V6

RV127

RV129

1 2

931_0402_1%

1

CV162

2

1U_0603_25V6

12

+1.35VS_VGA

RV128

549_0402_1%

RV130

1.33K_0402_1%

1

CV163

2

1

2

820P_0402_25V7

1

2

1U_0603_25V6

FBA_EDC0 FBA_EDC1 FBA_EDC2 FBA_EDC3

FBA_DBI0# FBA_DBI1#

FBA_CLK0 FBA_CLK0#

FBA_CKE_L

FBA_MA2_BA0_L FBA_MA5_BA1_L FBA_MA4_BA2_L FBA_MA3_BA3_L

FBA_MA7_MA8_L

FBA_MA1_MA9_L FBA_MA0_MA10_L FBA_MA6_MA11_L

FBA_MA12_RFU_L

12

RV116

1K_0402_1%

12

RV118

12

1K_0402_1%

FBA_ABI#_L

FBA_RAS#_L

FBA_CS#_L

FBA_CAS#_L

FBA_WE#_L

FBA_WCK0_N FBA_WCK0

FBA_WCK1_N FBA_WCK1

+FBA_VREFD_L +FBA_VREFC0

FBA_RST#_L

+FBA_VREFC0

W=16mils

CV158

+1.35VS_VGA +1.35VS_VGA

12

+FBA_VREFD_L

12

1

CV159

2

820P_0402_25V7

1

CV164

CV165

2

0.1U_0402_10V7K

FBA_DBI2# FBA_DBI3#

1

CV166

2

UV6

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC 3

C13

EDC1 EDC 2

R13

EDC2 EDC 1

R2

EDC3 EDC 0

D2

DBI0# DBI 3#

D13

DBI1# DBI 2#

P13

DBI2# DBI 1#

P2

DBI3# DBI 0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WC K23

P5

WCK23# WCK01#

P4

WCK23 WC K01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

1

CV167

CV375

2

0.1U_0402_10V7K

1

2

0.1U_0402_10V7K

CV374

MF=0

1

2

0.1U_0402_10V7K

CV376

4

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

H5GC4H24MFR-T2CH4G@

1

CV378

2

0.1U_0402_10V7K

3

UV7

A4

FBA_D0

A2

FBA_D1

B4

FBA_D2

B2

FBA_D3

E4

FBA_D4

E2

FBA_D5

F4

FBA_D6

F2

FBA_D7

A11

FBA_D8

A13

FBA_D9

B11

FBA_D10

B13

FBA_D11

E11

FBA_D12

E13

FBA_D13

F11

FBA_D14

F13

FBA_D15

U11

FBA_D16

U13

FBA_D17

T11

FBA_D18

T13

FBA_D19

N11

FBA_D20

N13

FBA_D21

M11

FBA_D22

M13

FBA_D23

U4

FBA_D24

U2

FBA_D25

T4

FBA_D26

T2

FBA_D27

N4

FBA_D28

N2

FBA_D29

M4

FBA_D30

M2

FBA_D31

B1

VDDQ

D1

VDDQ

F1

VDDQ

M1

VDDQ

P1

VDDQ

T1

VDDQ

G2

VDDQ

L2

VDDQ

B3

VDDQ

D3

VDDQ

F3

VDDQ

H3

VDDQ

K3

VDDQ

M3

VDDQ

P3

VDDQ

T3

VDDQ

E5

VDDQ

N5

VDDQ

E10

VDDQ

N10

VDDQ

B12

VDDQ

D12

VDDQ

F12

VDDQ

H12

VDDQ

K12

VDDQ

M12

VDDQ

P12

VDDQ

T12

VDDQ

G13

VDDQ

L13

VDDQ

B14

VDDQ

D14

VDDQ

F14

VDDQ

M14

VDDQ

P14

VDDQ

T14

VDDQ

A1

VSSQ

C1

VSSQ

E1

VSSQ

N1

VSSQ

R1

VSSQ

U1

VSSQ

H2

VSSQ

K2

VSSQ

A3

VSSQ

C3

VSSQ

E3

VSSQ

N3

VSSQ

R3

VSSQ

U3

VSSQ

C4

VSSQ

R4

VSSQ

F5

VSSQ

M5

VSSQ

F10

VSSQ

M10

VSSQ

C11

VSSQ

R11

VSSQ

A12

VSSQ

C12

VSSQ

E12

VSSQ

N12

VSSQ

R12

VSSQ

U12

VSSQ

H13

VSSQ

K13

VSSQ

A14

VSSQ

C14

VSSQ

E14

VSSQ

N14

VSSQ

R14

VSSQ

U14

VSSQ

1

CV377

CV379

2

0.1U_0402_10V7K

2

0.1U_0402_10V7K

BYTE0

FBA_DBI7#<26>

FBA_DBI6#<26>

FBA_DBI5#<26>

BYTE1

BYTE2

BYTE3

FBA_CLK1

80.6_0402_1% RV175

1 2

FBA_CLK1#

Near to VRAM

+1.35VS_VGA

2

1

CV380

10U_0603_6.3V6M

1

CV168

CV381

CV169

1

2

1U_0603_25V6

10U_0603_6.3V6M

FBA_DBI4#<26>

FBA_CLK1< 26>

FBA_CLK1#<26>

+1.35VS_VGA

RV121

FBA_RST#_H<26>FBA_RST#_L<26>

CV171

12

121_0402_1%

1

CV172

2

1U_0603_25V6

FBA_MA4_BA2_H FBA_MA3_BA3_H FBA_MA2_BA0_H FBA_MA5_BA1_H

FBA_MA0_MA10_H FBA_MA6_MA11_H

FBA_MA7_MA8_H FBA_MA1_MA9_H

FBA_MA12_RFU_H

RV117

1K_0402_1%

RV119

1K_0402_1%

FBA_ABI#_H

FBA_CAS#_H

FBA_WE#_H

FBA_RAS#_H

FBA_CS#_H

FBA_WCK3_N

FBA_WCK3

FBA_WCK2_N

FBA_WCK2

+FBA_VREFD_L +FBA_VREFC0

1

CV173

2

0.1U_0402_10V7K

FBA_MA4_BA2_H<26>

FBA_MA3_BA3_H<26>

FBA_MA2_BA0_H<26>

FBA_MA5_BA1_H<26>

FBA_MA0_MA10_H<26>

FBA_MA6_MA11_H<26>

FBA_MA7_MA8_H<26>

FBA_MA1_MA9_H<26>

FBA_MA12_RFU_H<26>

FBA_ABI#_H<26 >

FBA_CAS#_H<26>

FBA_WE#_H<26 >

FBA_RAS#_H<26>

FBA_CS#_H<26>

FBA_WCK3_N<26>

FBA_WCK3<26>

FBA_WCK2_N<26>

FBA_WCK2<26>

1

CV170

2

1U_0603_25V6

FBA_EDC7 FBA_EDC6 FBA_EDC5 FBA_EDC4

FBA_DBI7# FBA_DBI6#

FBA_DBI5#

FBA_DBI4#

FBA_CLK1 FBA_CLK1# FBA_CKE_H

12

FBA_RST#_H

0.1U_0402_10V7K

1

2

CV174

C2 C13 R13

R2

D2 D13 P13

P2 J12

J11

J3

H11 K10 K11 H10

K4

H5

H4

K5

J5

A5

U5

J1 J10 J13

J4

G3

G12

L3 L12

D5 D4

P5 P4

A10 U10 J14

J2

H1 K1 B5 G5

L5

T5 B10 D10 G10 L10 P10 T10 H14 K14

G1

L1

G4

L4 C5 R5

C10 R10 D11 G11 L11 P11 G14 L14

1

CV175

2

0.1U_0402_10V7K

EDC0 EDC 3 EDC1 EDC 2 EDC2 EDC 1 EDC3 EDC 0

DBI0# DBI 3# DBI1# DBI 2# DBI2# DBI 1# DBI3# DBI 0#

CK CK# CKE#

BA0/A2 BA2/A4 BA1/A5 BA3/A3 BA2/A4 BA0/A2 BA3/A3 BA1/A5

A8/A7 A10/A0 A9/A1 A11/A6 A10/A0 A8/A7 A11/A6 A9/A1 A12/RFU/NC

VPP/NC VPP/NC

MF SEN ZQ

ABI# RAS# CAS# CS# WE# CAS# RAS# WE# CS#

WCK01# WCK23# WCK01 WC K23

WCK23# WCK01# WCK23 WC K01

VREFD VREFD VREFC

RESET#

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

170-BALL

SGRAM GDDR5

1

2

0.1U_0402_10V7K

MF=1

MF=0 MF=1 MF=0MF=1

1

CV383

CV384

2

0.1U_0402_10V7K

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

H5GC4H24MFR-T2CH4G@

1

CV387

CV382

2

0.1U_0402_10V7K

2

A4

FBA_D56

A2

FBA_D57

B4

FBA_D58

B2

FBA_D59

E4

FBA_D60 FBA_D61 FBA_D62 FBA_D63 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39

1

2

BYTE7

BYTE6

BYTE5

BYTE4

+1.35VS_VGA+1.35VS_VGA

CV388

E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1

VDDQ

D1

VDDQ

F1

VDDQ

M1

VDDQ

P1

VDDQ

T1

VDDQ

G2

VDDQ

L2

VDDQ

B3

VDDQ

D3

VDDQ

F3

VDDQ

H3

VDDQ

K3

VDDQ

M3

VDDQ

P3

VDDQ

T3

VDDQ

E5

VDDQ

N5

VDDQ

E10

VDDQ

N10

VDDQ

B12

VDDQ

D12

VDDQ

F12

VDDQ

H12

VDDQ

K12

VDDQ

M12

VDDQ

P12

VDDQ

T12

VDDQ

G13

VDDQ

L13

VDDQ

B14

VDDQ

D14

VDDQ

F14

VDDQ

M14

VDDQ

P14

VDDQ

T14

VDDQ

A1

VSSQ

C1

VSSQ

E1

VSSQ

N1

VSSQ

R1

VSSQ

U1

VSSQ

H2

VSSQ

K2

VSSQ

A3

VSSQ

C3

VSSQ

E3

VSSQ

N3

VSSQ

R3

VSSQ

U3

VSSQ

C4

VSSQ

R4

VSSQ

F5

VSSQ

M5

VSSQ

F10

VSSQ

M10

VSSQ

C11

VSSQ

R11

VSSQ

A12

VSSQ

C12

VSSQ

E12

VSSQ

N12

VSSQ

R12

VSSQ

U12

VSSQ

H13

VSSQ

K13

VSSQ

A14

VSSQ

C14

VSSQ

E14

VSSQ

N14

VSSQ

R14

VSSQ

U14

VSSQ

1

CV385

CV386

2

0.1U_0402_10V7K

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS S HEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS S HEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS S HEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDIS CLOSED TO ANY THIRD PARTY WITHOUT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY ORDIS CLOSED TO ANY THIRD PARTY WITHOUT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY ORDIS CLOSED TO ANY THIRD PARTY WITHOUT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

N16P_GDDR5_A

Size Document Number Rev

LA-C901P

Date: Sheet of

1

27 63Tuesday, August 04, 2015

1.0

5

Memory Partition A - Lower 32 bits

RV141

1 2

931_0402_1%

RV144

1 2

931_0402_1%

CV180

1U_0603_25V6

FBC_CAS#_L<26>

FBC_WE#_L<26>

FBC_WCK1< 26>

FBC_RST#_L<26>

1.33K_0402_1%

1

CV181

2

FBC_D[0..63]

FBC_EDC[7..0]

FBC_CLK0<26> FBC_CLK0#<26>

FBC_CKE_L<26>

FBC_MA2_BA0_L<26>

FBC_MA5_BA1_L<26>

FBC_MA4_BA2_L<26>

FBC_MA3_BA3_L<26>

FBC_MA7_MA8_L<26>

FBC_MA1_MA9_L<26>

FBC_MA0_MA10_L<26>

FBC_MA6_MA11_L<26>

FBC_MA12_RFU_L<26>

FBC_ABI#_L<26>

FBC_RAS#_L<26>

FBC_CS#_L<26>

FBC_WCK0_N< 26>

FBC_WCK0< 26>

FBC_WCK1_N< 26>

RV140

549_0402_1%

RV142

RV143

549_0402_1%

RV145

1

2

1U_0603_25V6

+1.35VS_VGA

12

+1.35VS_VGA

12

1

CV182

2

1U_0603_25V6

C2

FBC_EDC0

C13

FBC_EDC1

R13

FBC_EDC2

R2

FBC_EDC3

FBC_DBI1#<26> FBC_DBI3#<26>

RV136

FBC_DBI0#<26> FBC_DBI2#<26>

CV183

FBC_DBI0# FBC_DBI1# FBC_DBI2# FBC_DBI3#

FBC_CLK0 FBC_CLK0#

FBC_CKE_L

FBC_MA2_BA0_L FBC_MA5_BA1_L FBC_MA4_BA2_L FBC_MA3_BA3_L

FBC_MA7_MA8_L

FBC_MA1_MA9_L FBC_MA0_MA10_L FBC_MA6_MA11_L

FBC_MA12_RFU_L

RV132

1K_0402_1%

RV134

12

1K_0402_1%

121_0402_1%

FBC_ABI#_L

FBC_RAS#_L

FBC_CS#_L

FBC_CAS#_L

FBC_WE#_L

FBC_WCK0_N FBC_WCK0

FBC_WCK1_N FBC_WCK2

FBC_WCK1

+FBC_VREFD_H +FBC_VREFC1

FBC_RST#_L

+FBC_VREFC1

W=16mils

1

CV177

+1.35VS_VGA

2

820P_0402_25V7

+FBC_VREFD_H

1

CV178

2

820P_0402_25V7

1

CV184

2

0.1U_0402_10V7K

D2 D13 P13

P2

J12 J11

J3

H11 K10 K11 H10

K4

H5

H4

K5

J5

A5

U5

12

J1

12

J10 J13

J4

G3

G12

L3

L12

D5

D4

P5

P4

A10 U10

J14

J2

H1

K1

B5

G5

L5

T5 B10 D10 G10

L10 P10 T10 H14 K14

G1

L1

G4

L4 C5

R5 C10 R10 D11 G11

L11 P11 G14

L14

1

CV186

CV185

2

0.1U_0402_10V7K

FBC_D[0..63]<26>

FBC_EDC[7..0]<26>

D D

C C

B B

A A

FBC_CLK0

FBC_CLK0#

MEM_VREF<22>

80.6_0402_1% RV178

Near to VRAM

1 2

+1.35VS_VGA

10U_0603_6.3V6M

2

1

CV389

13

D

2

G

S

2N7002W-T/R7_SOT323-3

2

CV179

1

10U_0603_6.3V6M

QV21

1

2

1U_0603_25V6

4

UV8

EDC0 EDC 3 EDC1 EDC 2 EDC2 EDC 1 EDC3 EDC 0

DBI0# DBI 3# DBI1# DBI 2# DBI2# DBI 1# DBI3# DBI 0#

CK CK# CKE#

BA0/A2 BA2/A4 BA1/A5 BA3/A3 BA2/A4 BA0/A2 BA3/A3 BA1/A5

A8/A7 A10/A0 A9/A1 A11/A6 A10/A0 A8/A7 A11/A6 A9/A1 A12/RFU/NC

VPP/NC VPP/NC

MF SEN ZQ

ABI# RAS# CAS# CS# WE# CAS# RAS# WE# CS#

WCK01# WCK23# WCK01 WC K23

WCK23# WCK01# WCK23 WC K01

VREFD VREFD VREFC

RESET#

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

170-BALL

SGRAM GDDR5

CV392

0.1U_0402_10V7K

MF=0

MF=0 MF=1 MF=0MF=1

1

CV391

CV390

2

0.1U_0402_10V7K

1

2

CV395

0.1U_0402_10V7K

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9 DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

H5GC4H24MFR-T2CH4G@

1

CV393

2

0.1U_0402_10V7K

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

3

UV9

A4

FBC_D0

A2

FBC_D1

B4

FBC_D2

B2

FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7 FBC_D8 FBC_D9

+1.35VS_VGA

FBC_CLK1

FBC_CLK1#

BYTE0

BYTE1

BYTE2

BYTE3

1 2

+1.35VS_VGA

80.6_0402_1% RV138

2

1

10U_0603_6.3V6M

12

121_0402_1%

CV189

1U_0603_25V6

FBC_CLK1 FBC_CLK1#

FBC_CKE_H

FBC_MA4_BA2_H FBC_MA3_BA3_H FBC_MA2_BA0_H FBC_MA5_BA1_H

FBC_MA0_MA10_H FBC_MA6_MA11_H

FBC_MA7_MA8_H FBC_MA1_MA9_H

FBC_MA12_RFU_H

RV131

RV133

+FBC_VREFD_H +FBC_VREFC1

FBC_RST#_H

+1.35VS_VGA

1

CV190

2

1U_0603_25V6

FBC_DBI7# FBC_DBI6# FBC_DBI5# FBC_DBI4#

1K_0402_1%

1

2

FBC_DBI7#<26>

FBC_DBI6#<26>

FBC_DBI5#<26>

FBC_DBI4#<26>

FBC_CLK1<26>

FBC_CLK1#<26>

FBC_CKE_H<26>

FBC_MA4_BA2_H<26>

FBC_MA3_BA3_H<26>

FBC_MA2_BA0_H<26>

FBC_MA5_BA1_H<26>

FBC_MA0_MA10_H<26>

FBC_MA6_MA11_H<26>

FBC_MA7_MA8_H<26>

FBC_MA1_MA9_H<26>

FBC_MA12_RFU_H<26>

+1.35VS_VGA

RV135

FBC_ABI#_H<26>

FBC_CAS#_H<26>

FBC_WE#_H<26>

FBC_RAS#_H<26>

FBC_CS#_H<26>

FBC_WCK3_N< 26>

FBC_WCK3< 26>

FBC_WCK2_N< 26>

FBC_WCK2< 26>

FBC_RST#_H<26>

1

2

CV397

1

10U_0603_6.3V6M

1

CV188

CV187

2

1U_0603_25V6

E4 E2 F4 F2 A11 A13 B11

FBC_D10

B13

FBC_D11

E11

FBC_D12

E13

FBC_D13

F11

FBC_D14

F13

FBC_D15

U11

FBC_D16

U13

FBC_D17

T11

FBC_D18

T13

FBC_D19

N11

FBC_D20

N13

FBC_D21

M11

FBC_D22

M13

FBC_D23

U4

FBC_D24

U2

FBC_D25

T4

FBC_D26

T2

FBC_D27

N4

FBC_D28

N2

FBC_D29

M4

FBC_D30

M2

FBC_D31

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

1

CV396

CV394

2

0.1U_0402_10V7K

FBC_EDC7 FBC_EDC6 FBC_EDC5 FBC_EDC4

12

FBC_ABI#_H FBC_CAS#_H FBC_WE#_H FBC_RAS#_H FBC_CS#_H

FBC_WCK3_N

FBC_WCK3

FBC_WCK2_N

CV191

0.1U_0402_10V7K

1

CV192

2

C2

EDC0 EDC 3

C13

EDC1 EDC 2

R13

EDC2 EDC 1

R2

EDC3 EDC 0

D2

DBI0# DBI 3#

D13

DBI1# DBI 2#

P13

DBI2# DBI 1#

P2

DBI3# DBI 0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WC K23

P5

WCK23# WCK01#

P4

WCK23 WC K01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

1

CV193

2

0.1U_0402_10V7K

MF=1

MF=0 MF=1 MF=0MF=1

1

2

0.1U_0402_10V7K

1

CV194

CV399

2

0.1U_0402_10V7K

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9 DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

H5GC4H24MFR-T2CH4G@

CV400

0.1U_0402_10V7K

2

A4

FBC_D56

A2

FBC_D57

B4

FBC_D58

B2

FBC_D59

E4

FBC_D60 FBC_D61 FBC_D62 FBC_D63 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39

0.1U_0402_10V7K

+1.35VS_VGA

1

CV401

2

0.1U_0402_10V7K

1

2

BYTE7

BYTE6

BYTE5

BYTE4

CV404

E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1

VDDQ

D1

VDDQ

F1

VDDQ

M1

VDDQ

P1

VDDQ

T1

VDDQ

G2

VDDQ

L2

VDDQ

B3

VDDQ

D3

VDDQ

F3

VDDQ

H3

VDDQ

K3

VDDQ

M3

VDDQ

P3

VDDQ

T3

VDDQ

E5

VDDQ

N5

VDDQ

E10

VDDQ

N10

VDDQ

B12

VDDQ

D12

VDDQ

F12

VDDQ

H12

VDDQ

K12

VDDQ

M12

VDDQ

P12

VDDQ

T12

VDDQ

G13

VDDQ

L13

VDDQ

B14

VDDQ

D14

VDDQ

F14

VDDQ

M14

VDDQ

P14

VDDQ

T14

VDDQ

A1

VSSQ

C1

VSSQ

E1

VSSQ

N1

VSSQ

R1

VSSQ

U1

VSSQ

H2

VSSQ

K2

VSSQ

A3

VSSQ

C3

VSSQ

E3

VSSQ

N3

VSSQ

R3

VSSQ

U3

VSSQ

C4

VSSQ

R4

VSSQ

F5

VSSQ

M5

VSSQ

F10

VSSQ

M10

VSSQ

C11

VSSQ

R11

VSSQ

A12

VSSQ

C12

VSSQ

E12

VSSQ

N12

VSSQ

R12

VSSQ

U12

VSSQ

H13

VSSQ

K13

VSSQ

A14

VSSQ

C14

VSSQ

E14

VSSQ

N14

VSSQ

R14

VSSQ

U14

VSSQ

1

2

1

CV402

CV398

CV403

2

0.1U_0402_10V7K

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS S HEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS S HEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS S HEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDIS CLOSED TO ANY THIRD PARTY WITHOUT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY ORDIS CLOSED TO ANY THIRD PARTY WITHOUT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY ORDIS CLOSED TO ANY THIRD PARTY WITHOUT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

N16P_GDDR5_B

Size Document Number Rev

LA-C901P

Date: Sheet of

1

28 63Tuesday, August 04, 2015

1.0

5

ZZZ

HYNR1@

HYNIX 2GB R1

X7656331L81

ZZZ

D D

HYNR3@

HYNIX 2GB R3

X7656331L09

ZZZ

MICR3@

ZZZ

SAMR1@

SAMSUNG 2GB R1

X7656331L01

ZZZ

SAMR3@

SAMSUNG 2GB R3

X7656331L05

X7656331L01 : SAMR1@ X7656331L81 : HYNR1@

X7656331L05 : SAMR3@ X7656331L09 : HYNR3@

Micron 2GB R3

X7656331L82

4

STRAP0<23>

STRAP1<23>

STRAP2<23>

STRAP3<23>

STRAP4<23>

3

RV147

34.8K_0402_1%

@

1 2

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

RV146

49.9K_0402_1%

1 2

2

RV148 10K_0402_1%

@

1 2

RV149 15K_0402_1%

@

1 2

+3.3V_GFX_AON

RV150 20K_0402_1%

@

1 2

1

+3.3V_GFX_AON

C C

ROM_SI<23>

ROM_SO<23>

ROM_SCLK<23>

ROM_SI ROM_SO ROM_SCLK

RV157

4.99K_0402_1%

@

1 2

RV158

4.99K_0402_1%

@

1 2

RV159

4.99K_0402_1%

@

1 2

SA00007D800 S IC D5 128M32 K4G41325FC-HC03 FBGA 170P SA00007UZ1L S IC D5 128M32 EDW4032BABG-60-F-R A31!

RV152

49.9K_0402_1%

@

1 2

RV153

34.8K_0402_1%

@

1 2

RV154

4.99K_0402_1%

@

1 2

RV155

4.99K_0402_1%

@

1 2

RV156 20K_0402_1%

@

1 2

SA00008HQ0L S IC D5 128M32/3G H5GC4H24AJR-ROC FBGA

RV160

34.8K_0402_1%

@

1 2

B B

ROM_CS<23>

ROM_CS

+3VS_VGA

12

RV167 10K_0402_5%

RV161

4.99K_0402_1%

1 2

RV162 15K_0402_1%

1 2

SA00008HQ1L S IC D5 128M32/3G H5GC4H24AJR-ROC A31!

ROM_SO ROM_SCLK ROM_SI STRAP1GPU

PD

4.99K

PD

4.99K

PD

4.99K

PD

4.99K

PD 20K

PD

34.8K

PU

49.9K

PU

49.9K

NA

NA NA

N16P-GX

FB Memory GDDR5 STRAP2STRAP0

Samsung 2500MHz

K4G41325FC-HC03

256Mx16

Hynix 2500MHz

H5GC4H24AJR-R0C

256Mx16

NA NA

NA

STRAP4STRAP3

NA

W25X20CL 2M-Bit/256K-byte

A A

Security Classification

2015/01/06 2016/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2015/01/06 2016/01/06

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

N16P_MISC

LA-C901P

1.0

29 63Tuesday, August 04, 2015

of

1

of

5

4

3

2

1

XTLI XTLO

1

2

1U_0402_6.3V6K~D

UL1

30

TX_P

29

TX_N

35

RX_P

36

RX_N

33

REFCLK_P

32

REFCLK_N

4

CLKREQ#

2

PERST#

3

WAKE#

25

SMCLK

26

SMDATA

28

NC

27

TESTMODE

41

GND

8

XTLI

7

XTLO

5

ISOLAT#

38

LED_0

39

LED_1

23

LED_2

E2400-RIV 1-RL QFN 4 0P E-LAN CTRL

W=20mils

+AVDDL

1

CL18

CL19

2

1U_0402_6.3V6K~D

1

2

VDD33

AVDD33

AVDDL AVDDL AVDDL AVDDL

AVDDL_REG

AVDDH

AVDDH_REG

DVDDL_REG

TRXP0

TRXN0

TRXP1

TRXN1

TRXP2

TRXN2

TRXP3

TRXN3

RBIAS

0.1U_0402_16V7K~D

1

W=40mils

16

13

+AVDDL

19 31 34 6

22

+AVDDH

9

37

+DVDDL

11

LAN_MDIP0

12

LAN_MDIN0

14

LAN_MDIP1

15

LAN_MDIN1

17

LAN_MDIP2

18

LAN_MDIN2

20

LAN_MDIP3

21

LAN_MDIN3

40

LX

24

PPS

1 2

10

RL3

2.37K_0402_1%~D

+LAN_IO

+AVDDH

W=20mils

1

CL5

2

+DVDDL

W=20mils

1

CL4

CL3

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

close to UL1 pin37

1

CL6

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

1

CL7

2

0.1U_0402_16V7K~D

close to UL1 pin9 close to UL1 pin22

CL20

1

2

1

CL21

CL22

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

4.7U_0603_6.3V6K~D

CL23

1

2

0.1U_0402_16V7K~D

CL24

1

2

0.1U_0402_16V7K~D

CL25

1

2

0.1U_0402_16V7K~D

12

PCIE_CRX_ DTX_P6<12> PCIE_CRX_ DTX_N6<12>

+LAN_IO

12

D D

PCIE_W AKE#<41>

RL1

4.7K_0402_5%~D

PCIE_W AKE#

PCIE_CTX_C_ DRX_P6<12> PCIE_CTX_C_ DRX_N6<12> CLK_PCIE_P2<10> CLK_PCIE_N2<10> CLKREQ_P CIE#2<10 > PLT_RST#<10,32 ,41,44>

PCIE_CRX_ C_DTX_P6

CL1 0 .1U_0402_16V7K ~D

12

PCIE_CRX_ C_DTX_N6

CL2 0 .1U_0402_16V7K ~D

PCIE_CTX_C_ DRX_P6 PCIE_CTX_C_ DRX_N6 CLK_PCIE_P2 CLK_PCIE_N2 CLKREQ_P CIE#2 PLT_RST#

The pull-up resisters might not be necessory due to existence on PCH side.

4

GND2GND

OSC1OSC

YL1

3

2

CL8

CL12

1000P_0402_50V7K~D

1

15P_0402_50V8J

W=40mils

1

CL13

2

0.1U_0402_16V7K~D

CL14

1U_0402_6.3V6K~D

4.7U_080 5_10V4 Z

CL40

+3VALW

EN_WOL #

1

2

W=40mils

1

CL41

0.1U_040 2_16V7 K

2

1

CL26

0.1U_040 2_16V7 K

2

UL2

OUT

5

IN

GND

4

EN

OCB

SY6288D20AAC_SOT23-5

+3VS

CL11

+LAN_IO

1

2

1 2 3

1 2

RL5 10K_040 2_5%

C C

EN_WOL #<41>

+LAN_IO

25MHZ_10PF_7V25000014

2

CL9

1

15P_0402_50V8J

1A

1

CL15

2

10U_0603_6.3V6M~D

1 2

RL2 30K_0 402_5%

LAN_ACTIVITY# +RBIAS LAN_LINK#_R LAN_LED2 #_R

RL4

5.1K_0402_1%~D

1 2

1

CL17

CL16

2

0.1U_0402_16V7K~D

close to UL1 pin13 close to UL1 pin19close to UL1 pin31close to UL1 pin1 close to UL1 pin16 close to UL1 pin6 close to UL1 pin34

@EMI@

D

13

1 2

Issued Date

CL27

0.1U_040 2_16V7 K~D

1 2

+LAN_IO

LAN_LED2 #_R

RL15 1K_0402 _1%~D

JLAN

LAN_ACTIVITY#

12

RL8 330_0 402_5%

RJ45_MDI3RJ45_MDI3+ RJ45_MDI1RJ45_MDI2RJ45_MDI2+ RJ45_MDI1+ RJ45_MDI0RJ45_MDI0+

12

LAN_LINK#

CL28 0.1U_0402_16V 7K~DEMI @

1 2

LAN_LED2 #

CL29 0.1U_0402_16V 7K~DEMI @

1 2

LL1 BLM15AG121SN1D_ L0402_ 2P

12

RL13 130_0402 _1%~D

12

RL14 130_0402 _5%~D

2015/01/06 2016/01/06

10

Yellow LED-

9

Yellow LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

11

Green LED-

13

Orange LED-

12

Green-Orange LED+

SANTA_130 456-511

CONN@

2

@EMI@

CL31

0.1U_040 2_16V7 K~D

1

Compal Secret Data

Deciphered Date

2

17

GND

16

GND

15

GND

14

GND

Compal Electronics, Inc.

Title

Size Docum ent Number Rev

Date: Sheet of

Compal Electronics, Inc.

LAN E2400

LAN E2400 LA-C901P

LA-C901P

1

1.0

30 6 3Tuesday, Augu st 04, 2015

1.0

B B

A A

5

TIMAG: S X'FORM_ IH-160 LAN,SP050006F00 BOTHHAND: S X'FORM_ GST5009-D LF LAN,SP050006B00

2

CL32

1

+VDDCT_L

1000P_0402_50V7K~D

TL1

1 2

LAN_MDIN3

3

LAN_MDIP3

4 5

LAN_MDIN2

6

LAN_MDIP2

7 8

LAN_MDIN1

9

LAN_MDIP1

10 11

LAN_MDIN0

12

LAN_MDIP0

2

1

CL33

2

1

CL34

CL35

1

2

0.1U_0402_16V7K~D

1000P_0402_50V7K~D

TCT1

MCT1

TD1+

MX1+

TD1-

MX1-

TCT2

MCT2

TD2+

MX2+

TD2-

MX2-

TCT3

MCT3

TD3+

MX3+

TD3-

MX3-

TCT4

MCT4

TD4+

MX4+

TD4-

MX4-

350UH_GS T5009-CLF

2

1

CL36

CL37

1

2

0.1U_0402_16V7K~D

1000P_0402_50V7K~D

24 23 22

21 20 19

18 17 16

15 14 13

RJ45_CT3 RJ45_MDI3RJ45_MDI3+

RJ45_CT2 RJ45_MDI2RJ45_MDI2+

RJ45_CT1 RJ45_MDI1RJ45_MDI1+

RJ45_CT0 RJ45_MDI0RJ45_MDI0+

2

CL38

1

CL39

2

0.1U_0402_16V7K~D

1000P_0402_50V7K~D

4

RL9

1 2

75_0402 _1%~D

RL10

1 2

75_0402 _1%~D

RL11

1 2

75_0402 _1%~D

RL12

1 2

75_0402 _1%~D

2

EMI@

CL30 10P_180 8_3KV7 K~D

1

3

QL3 ME2N7002 E1-G 1N S OT-23-3 ESD 1KV

S

LAN_LINK#_R

G

+LAN_IO

2

Security Classification

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT C ONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT C ONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

1

+3.3V_1.8V_DVDD_IO

+3.3V_1.8V_DVDD

1

PC_BEEP

12

@

RA19 10K_0402_5%

1

CA29

2

EMI@

1

CA75 100P_0402_50V8J~D

2

1

CA76 100P_0402_50V8J~D

2

UA2 MAX9892ERT+T_UCSP6~D

INL INR

/MUTE

VDD

SET

GND

A2

LA13

1 2

BLM15AG121SN1D_L0402_2P

1 2

RA37 0_0603_1%@

LA16

1 2

BLM15AG121SN1D_L0402_2P

1 2

RA38 0_0603_1%@

ESD@

1 2

RA4 200K_0402_5%

Reserve for cancel Delay circutis

1

CA31

CA30

CA32

2

EMI@

1000P_0402_50V7K

2

3

DA16

AZ5125-02S.R7G_SOT23-3

1

+3VS

B2

HP2_D_L1_JK

HPOUT2-JD

HP2_D_R1_JK

1

2

12

Line1-VREFO-L

DA18 BAT54AW_SOT323-3~D

3

12

RA166

4.7K_0402_5%

Line-IN-L

Place on the moat between GND & GNDA.

EC Beep

MCU Beep

1 2

RA29 0_0603_5%

1 2

RA30 0_0603_5%

1 2

RA31 0_0603_5%

1 2

RA32 0_0603_5%

BEEP#<41>

SPKR<9>

Close to UA1 Pin42,43,44,45

INT-SPK-RINT-SPK-R+ INT-SPK-LINT-SPK-L+

Trace width for SPK-L+/SPK-L-/SPK-R+/SPK-RSpeaker 4 ohm : 40mil Speaker 8 ohm : 20mil

Line1-VREFO-R

1 2

HP2_D_R_C

+

CA3 100U_B2_6.3VM_LESR55M

1 2

HP2_D_L_C

+

CA4 100U_B2_6.3VM_LESR55M

JHP1

3

G

1

L

5

6 2

R

4

M

SINGA_2SJ3095-063111F

CONN@

7

G

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

1 2

LA3 BLM15PX121SN1D_2PEMI@

1 2

LA4 BLM15PX121SN1D_2PEMI@

1 2

LA5 BLM15PX121SN1D_2PEMI@

1 2

LA6 BLM15PX121SN1D_2PEMI@

DA17 BAT54AW_SOT323-3~D

3

1

2

12

HP2_D_R_R

HP2_D_L_R

HP_MUTE#

2015/01/06 2016/01/06

1 2

RA23

8.2_0402_5%~D

1 2

RA24

8.2_0402_5%~D

RA172

4.7K_0402_5%

Moat

GNDGNDA

DA8

2

3

BAT54C-7-F_SOT23-3

SPK_R-_CONN SPK_R+_CONN SPK_L-_CONN SPK_L+_CONN

RA173

4.7K_0402_5%

1 2

@

RA1 0_0603_1%

1 2

@

RA2 0_0603_1%

RA25 0_0402_1%

A1

1 2

@

A3

1 2

@

B1

RA26 0_0402_1%

B3

12

CA77

0.01U_0402_16V7K

Setting the Turn-Off Time: Ton (ms) = 0.02 x Cset (pF)

Compal Secret Data

Deciphered Date

2

CA53,CA55 change Value from 10U_0603_6.3V6M~D to

CA57,CA58 close to UA1 pin1

+3.3V_1.8V_DVDD

CA57

4.7U_0603_6.3V6K

CA58

0.1U_0402_16V7K

1

D D

+3.3V_1.8V_DVDD_IO

CA59,CA60 close to UA1 pin9

HDA_BIT_CLK_R<9> HDA_SDOUT_R<9> HDA_SYNC_R<9> HDA_SDIN0<9> HDA_RST#_R<9>

HDA_BIT_CLK_R

12

RA35 33_0402_1%

@EMI@

1

CA21

C C

22P_0402_50V8J

@EMI@

2

B B

A A

HDA_RST#_R

1

CA70

0.1U_0402_16V7K

@ESD@

2

CA70 close to UA1 pin11

+MIC2-VREFO

+3VL_RTC

RA167 100K_0402_5%ESD@

Setting the Turn-Off Time: Ton (ms) = 0.02 x Cset (pF)

5

1

2

0.1U_0402_16V7K

10U_0603_6.3V6M

CA60

CA59

1

2

HDA_BIT_CLK_R

1 2

RA130 22_0402_5%

HDA_RST#_R

LINE1-R LINE1-L Line1-VREFO-R Line1-VREFO-L HP2_D_R HP2_D_L

+MIC2-VREFO RING2 SLEEVE

12

MIC1-L

CA74 10U_0603_6.3V6M

RA55 15_0402_1%

1 2 1 2

RA56 15_0402_1%

PDB

EAPD#

RA20

2.2K_0402_5%

HP_MUTE#

1 2

CA62 10U_0603_6.3V6M

1 2

CA63 10U_0603_6.3V6M

1 2

CA64 10U_0603_6.3V6M

SLEEVE RING2 HPOUT-L AUD_HP_OUT_L_CN HPOUT-R

CA71,CA51 place close to pin26

UA1

1

DVDD

9

DVDD-IO

6

BCLK

5

SDATA-OUT

10

SYNC

8

SDATA-IN

11

RESETB

21

LINE1-R(PORT-C-R)

22

LINE1-L(PORT-C-L)

30

LINE1-VREFO-R

31

LINE1-VREFO-L

23

LINE2-R(PORT-E-R)

24

LINE2-L(PORT-E-L)

16

MONO-OUT

29

MIC2-VREFO

17

MIC2-L(PORT-F-L)/RING

18

MIC2-R(PORT-F-R)/SLEEVE

19

MIC_CAP

20

NC

47

PDB

27

LDO1-CAP

39

LDO2-CAP

7

LDO3-CAP

4

DVSS

49

GND

ALC3234-CG_MQFN48_6X6

+MIC2-VREFO

12

RA53

2.2K_0402_5%

LA7 BLM15PX330SN1D 0402 LA10 BLM15PX330SN1D 0402

Line-IN-L

LA8 FBMA-L11-160808-800LMT_2P

Line-IN-R

LA9 FBMA-L11-160808-800LMT_2P

RA21 100_0402_1%

1 2 1 2

RA22 100_0402_1%

12

CA78

0.1U_0402_16V4Z~D

SPDIFO/FRONT JD(JD3)/GPIO3

ESD@

12

ESD@

12

EMI@

12

EMI@

12

UA3 MAX9892ERT+T_UCSP6~D

A1

INL

A3

INR

B1

/MUTE

B3

SET

+5VA

CA51

0.1U_0402_16V7K

1

2

HP/LINE1 JD(JD1)

MIC2/LINE2 JD(JD2)

HPOUT-L(PORT-I-L)

HPOUT-R(PORT-I-R)

GPIO0/DMIC-DATA

GPIO1/DMIC-CLK

SPDIF-OUT/GPIO2

VDD

GND

A2

10U_0603_6.3V6M

1

2

AVDD1 AVDD2

CPVDD

PVDD1 PVDD2

SPK-OUT-L+

SPK-OUT-L-

SPK-OUT-R+

SPK-OUT-R-

VREF

PCBEEP

CPVEE

AVSS1 AVSS2

+3VS

B2

CA71

26 40

36 41 46

Moat

13 14 15

32 33

42 43 45 44

2 3 48

37

CBP

35

CBN

28 12 34

25 38

100P_0402_50V8J

1

2

4

4.7U_0603_6.3V6K

+CODEC_AVDD2

10U_0603_6.3V6M

+3.3V_1.8V_DVDD

CA61

1

2

1 2

RA168 100K_0402_5%ESD@

1 2

RA171 100K_0402_5%

1 2

RA170 100K_0402_5%ESD@

1 2

CA69 0.1U_0402_16V7K

HPOUT-L HPOUT-R

INT-SPK-L+ INT-SPK-LINT-SPK-R+ INT-SPK-R-

1 2

MIC_CLK_L

LA1

CA24

BLM15BB221SN1D_2P

1U_0402_6.3V6K

12

CA23 2.2U_0603_6.3V6K

12

CA65 0.1U_0402_16V7K

12

CA25 1U_0402_6.3V6K

EC_MUTE#<41>

CA39

CA38

680P_0402_50V8J

CA33

100P_0402_50V8J

1

EMI@

ESD@

EMI@

2

+5V_PVDD +5V_PVDD

0.1U_0402_16V7K CA54

CA53

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

CA79

1

2

JACK_SENSE# HPOUT2-JD

@

MIC_CLK

1

EMI@

EC_MUTE# PDB

@EMI@

CA22 22P_0402_50V8J

2

RA79 1K_0402_1%

12

RA174 10K_0402_5%

1 2

DA19

RB751V-40_SOD323-2

CA55

10U_0603_6.3V6M

CA56

0.1U_0402_16V7K

1

2

+3.3V_1.8V_DVDD 1 2

CA66 0. 1U_0402_16V7K

+3.3V_1.8V_DVDD

MIC_DATA <20> MIC_CLK <20>

12

PC_BEEP

Moat

+3.3V_1.8V_DVDD

12

RA183

100K_0402_5%

Universal Audio Jack(UAJ) Headphone/Speaker Out /iPhone or Nokia headset/Line-In/Microphone

CA40

680P_0402_50V8J

ESD@

W=40mils W=40mils

2

3

1

SLEEVE_R RING2_R

AUD_HP_OUT_R_CN

2

3

DA10

AZ5125-02S.R7G_SOT23-3

ESD@

DA12

AZ5123-02S SOT23

ESD@

Moat

1

RA165

CA67

4.7U_0805_25V6K

1 2 1 2

CA68

4.7U_0805_25V6K

SLEEVE_R AUD_HP_OUT_L_CN

JACK_PLUG#

AUD_HP_OUT_R_CN RING2_R

4.7K_0402_5%

RA80 1K_0402_1%

1 2 1 2

RA82 1K_0402_1%

HP2_D_R

HP2_D_L

Near to UA1

LINE1-L LINE1-R Line-IN-R

@

Change SLEEVE to Pin3, RING2 to Pin4 for Realtek's recommend at dat.04/07

3

+1.8VS

@

HP_MUTE#

2

1000P_0402_50V7K

1

HP2_D_R1_JK

HP2_D_L1_JK

ESD@

Moat

3

+3VS

+1.8VS

+3VS

+3VS +3VS

12

RA36 10K_0402_5%

1

2

DA13

AZ5125-02S.R7G_SOT23-3

@ESD@

Re-tasking port

RA33 0_0603_1%

+5VA

RA34 0_0603_1%

+CODEC_AVDD2 +1.8VS

BLM15AG121SN1D_L0402_2P

12

RA175 10K_0402_5%

2

EAPD#

3

DEPOP#_EC

DA15 BAT54AW_SOT323-3~D

JACK_SENSE#JACK_PLUG#

3

DA14

AZ5125-02S.R7G_SOT23-3

@ESD@

1

Headphone/Speaker Out /Line-In/Microphone

JHP2

3

G

1

L

5

6 2

R

4

M

SINGA_2SJ3095-063111F

CONN@

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Audio Codec ALC3234

Audio Codec ALC3234 LA-C901P

LA-C901P

1

1 2

@

1 2

@

Moat

LA15

1 2

JSPK

1

2

3

4

5

GND1

6

GND2

E-T_3806K-F04N-03R

CONN@

7

G

+5VS+5V_PVDD

+5VS

DEPOP#_EC <41>

31 63Tuesday, August 04, 2015

1.0

5

D D

4

3

2

1

+3VS_WLAN_NGFF

RN9

100K_0402_5%

RN3

12

NGFF(M.2)2230 slot(E Key)

LED1#

PCM_IN

LED2#

GND

COEX3 COEX2 COEX1

ALERT

MTG76

22U_0603_6.3V6M~D

CN6

2 4 6 8 10 12 14 16 18 20 22

24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66

68

0.1U_0402_10V7K~D

1

2

+3VS_WLAN_NGFF

RN11 0_0402_1% RN12 0_0402_1%

1

CN5

2

WLAN_LED

BT_LED

1 2 1 2

SUSCLK_R PLT_RST#_R BT_OFF#

22U_0603_6.3V6M~D

CN4

@ @

+3VS_WLAN_NGFF

10K_0402_5

BT_OFF#

0.1U_0402_10V7K~D

1

CN3

2

For EC to detect debug card insert.

1 2

RN7 100K_0402_5%

1 2

RN1 0_0402_1%@

1 2

RN2 0_0402_1%@

12

RN10

JNGFF

1

GND

USB20_P8<12> USB20_N8<12>

C C

1 2

PCIE_CTX_DRX_P5<12> PCIE_CTX_DRX_N5<12>

PCIE_CRX_DTX_P5<12> PCIE_CRX_DTX_N5<12>

CLK_PCIE_P1<10> CLK_PCIE_N1<10>

CLKREQ_PCIE#1<10> WLAN_WAKE#<41>

B B

UART_2_CTXD_DRXD<11> UART_2_CRXD_DTXD<11>

CN7 0.1U_0402_10V7K

1 2

CN8 0.1U_0402_10V7K

UART_2_CTXD_DRXD UART_2_CRXD_DTXD

+5VALW

PCIE_CTX_C_DRX_P5 PCIE_CTX_C_DRX_N5

CLKREQ_PCIE#1 WLAN_WAKE#

JWDB1

1

2

3

G1

4

G2

ACES_88266-04001

CONN@

5 6

3

USB_D+

5

USB_D-

7

GND

9

SIDO_CLK

11

SDIO_CMD

13

SDO_DAT0

15

SDO_DAT1

17

SDO_DAT2

19

SDO_DAT3

21

SDIO_WAKE#

23

SDIO_RESET#

25

GND

27

PETP0

29

PETN0

31

GND

33

PERP0

35

PERN0

37

GND

39

REFCLKP0

41

REFCLKN0

43

GND

45

CLKEQ0#

47

PEWAKE0#

49

GND

51

RSRVD/PETP1

53

RSRVD/PETN1

55

GND

57

RSRVD/PERP1

59

RSRVD/PERN1

61

GND

63

RESERVED

65

RESERVED

67

GND

69

MTG77

closed to pin 2, 4 closed to pin 72,74

3.3VAUX

PCM_CLK

PCM_SYNC

PCM_OUT

UART_WAKE#

UART_RX

UART_TX UART_CTS UART_RTS

RESERVED RESERVED RESERVED

SUSCLK

PERST0#

W_DISABLE2# W_DISABLE1#

I2C_DATA

I2C_CLK

RESERVED RESERVED RESERVED RESERVED

3.3VAUX

LOTES_APCI0019-P009ACONN@

+3VS_WLAN_NGFF +3VS_WLAN_NGFF

1

2

BT_LED

WLAN_LED

EC_TX <41> EC_RX <41>

SUSCLK <10,36> PLT_RST# <10,30,36,41,44> BT_OFF# <11>

1U_0402_6.3V6K

AOAC_WLAN<41>

CN2

100K_0402_5%~D

12

2

G

D

S

QN1

2

2N7002K_SOT23-3

G

13

D

S

QN3 2N7002K_SOT23-3

+3VS_WLAN_NGFF +3VS

12

RN5

10K_0402_5

WL_OFF#_R

1

CN9

0.1U_0402_10V7K

2

+3VALW +3VS_WLAN_NGFF

2

12

RN13 100K_0402_5%

UN1

5

OUT

IN

GND

4

OC

EN

SY6288C20AAC_SOT23-5

1 2 3

1

+5VALW

RN6

100K_0402_5%~D

12

13

WLAN_LED# <38>

Prevent backdriver from +3VS_WLAN_NGFF to +3VS

QN2

2

G

DMN65D8LW-7_SOT323-3

@

1 3

D

S

2

CN1 100U_1206_6.3V6M

1

RN8 10K_0402_5%

12

RN14 10K_0402_5

12

WL_OFF# <11>

+3VALW

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

205/01/06 2016/01/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

NGFF WLAN/BT

NGFF WLAN/BT LA-C901P

LA-C901P

1

32 63Tuesday, August 04, 2015

1.0

5

D D

LU1

USB3_CTX_DRX_P1<12>

USB3_CTX_DRX_N1<12>

C C

USB3_CTX_DRX_P2<12>

USB3_CTX_DRX_N2<12>

B B

USB3_CTX_DRX_P1

USB3_CTX_DRX_N1

USB3_CRX_DTX_P1<12>

USB3_CRX_DTX_N1<12>

USB3_CTX_DRX_P2

USB3_CTX_DRX_N2

USB3_CRX_DTX_P2<12>

USB3_CRX_DTX_N2<12>

12

CU4 0.1U_0402_10V7K

12

CU5 0.1U_0402_10V7K

USB20_P1<12>

USB20_N1<12>

12

CU12 0.1U_0402_10V7K

12

CU13 0.1U_0402_10V7K

USB3_CTX_C_DRX_N1 USB3_CTX_C_L_DRX_N1

USB3_CRX_DTX_P1

USB3_CRX_DTX_N1 USB3_CRX_L_DTX_N1

USB20_P1 USB20_P1_CONN

USB20_N1

USB3_CTX_C_DRX_P2

USB3_CTX_C_DRX_N2

USB3_CRX_DTX_P2

USB3_CRX_DTX_N2

SW_USB20_P2

SW_USB20_N2

EMI@

1 2

HCM1012GD670A05P

LU2

EMI@

1 2

HCM1012GD670A05P

LU3

EMI@

1 2

MCM1012B900F06BP_4P

HCM1012GD670A05P

1 2

LU4

EMI@

HCM1012GD670A05P

1 2

LU5

EMI@

MCM1012B900F06BP_4P

1 2

LU6

EMI@

USB3_CTX_C_L_DRX_P1USB3_CTX_C_DRX_P1

34

USB3_CRX_L_DTX_P1

34

USB20_N1_CONN

34

USB3_CTX_C_L_DRX_P2

USB3_CTX_C_L_DRX_N2

34

USB3_CRX_L_DTX_P2

USB3_CRX_L_DTX_N2

34

USB20_P2_CONN

USB20_N2_CONN

4

SDMK0340L-7-F_SOD323-2

220K_0402_5%

12

RU5

CU27

12

2.2U_0603_6.3V6K TC7SZ14FU_SSOP5~D

DU9

SDMK0340L-7-F_SOD323-2

CU28

0.1U_0402_16V7K

+5VALW

1

CU7

0.1U_0402_16V7K

2

USB_OC1#<12>

USB20_N2<12>

USB20_P2<12>

1 2

RU1 10K_0402_5

1 2

RU7 10K_0402_5

+5VALW

CU14

CTL1<41> CTL2<41>

1

2

1

CU15

0.1U_0402_16V7K

2

1

CU16

0.1U_0402_16V7K

2

USB20_N2 USB20_P2

USB_PWR_EN#<41>

RU4 100K_0402_5%

USBCHG_DET#

+3VLP

4.7U_0805_10V4Z

12

1

2

PWRSHARE_EN_EC#<41>

USB_PWR_EN#

+3VLP+3VLP+3VLP+3VLP

DU8

5

1

P

NC

2

A

G

UU5

3

12

Power share

UU1

1

IN

13

FAULT#

2

DM_OUT

3

DP_OUT

4

ILIM_SEL

5

EN

6

CTL1

7

CTL2

8

CTL3

TPS2546RTER_QFN16_3X3

UU3

5

IN

4

EN

SY6288D20AAC_SOT23-5

3

1

2

4

Y

1M_0402_5%

DM_IN DP_IN

OUT GND OCB

USB charge for DC S5

CU26

0.1U_0402_16V7K

USBCHG_DET_D <53>

USBCHG_DET_EC# <41>

+5V_USB_PWR1

W=80mils

SW_USB20_N2 SW_USB20_P2

RU2 19.1K_0402_1% RU3 19.1K_0402_1%

+5V_USB_PWR2

1

2

RU6

ILIM1 ILIM0

GPAD

OUT

NC

GND

1 2 3

12

1

CU29

0.1U_0402_16V7K

2

12 9 11

10 15

16

14 17

W=80mils

12 12

CU17

0.1U_0402_16V7K

USB20_N1_CONN USB20_P1_CONN

USB3_CRX_L_DTX_N1 USB3_CRX_L_DTX_P1

USB3_CTX_C_L_DRX_N1 USB3_CTX_C_L_DRX_P1

USB_OC0# <12>

2

Left side (power share)

+5V_USB_PWR1

USB20_N2_CONN USB20_P2_CONN USB3_CRX_L_DTX_N2 USB3_CRX_L_DTX_P2 USB3_CTX_C_L_DRX_N2 USB3_CTX_C_L_DRX_P2 USBCHG_DET#

Right side

+5V_USB_PWR2

JUSB2

1

VBUS

2

D-

3

D+

4

GND

5

StdA-SSRX -

6

StdA-SSRX +

7

GND-DRAIN

8

StdA-SSTX-

9

StdA-SSTX+

SANTA_377175-1

CONN@

2

3

DU4 L30ESDL5V0C3-2_SOT23-3

ESD@

1

JUSB1

1

VBUS

2

D-

3

D+

5

SSRX-

6

SSRX+

8

SSTX-

9

SSTX+

10

D1-DP

2

3

TAITW_USB011-107BRL-TW

CONN@

DU1 L30ESDL5V0C3-2_SOT23-3

ESD@

1

USB3_CRX_L_DTX_N2 USB3_CRX_L_DTX_N2

USB3_CRX_L_DTX_P2 USB3_CRX_L_DTX_P2 USB3_CTX_C_L_DRX_N2 USB3_CTX_C_L_DRX_N2 USB3_CTX_C_L_DRX_P2 USB3_CTX_C_L_DRX_P2

10

GND1

11

GND2

12

GND3

13

GND4

14

GND

13

GND

12

GND

11 4 7

DU2

1 2 4 5

3

TVWDF1004AD0_DFN9

ESD@

DU5

1 2 4 5

3

TVWDF1004AD0_DFN9

ESD@

150U_B15G_6.3VM_R70M

9 8 7 6

+5V_USB_PWR2

47U_0805_6.3V6M~D

CU10

12

GND GND GND

USB3_CRX_L_DTX_N1 USB3_CRX_L_DTX_N1

USB3_CRX_L_DTX_P1 USB3_CRX_L_DTX_P1 USB3_CTX_C_L_DRX_N1 USB3_CTX_C_L_DRX_N1 USB3_CTX_C_L_DRX_P1 USB3_CTX_C_L_DRX_P1

1

+5V_USB_PWR1

1

CU6

+

@

2

10U_0603_6.3V6M~D

CU11

1

2

9 8 7 6

10U_0603_6.3V6M~D

CU3

CU2

47U_0805_6.3V6M~D

1

12

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

USB 3.0/2.0 x2

Size Document Number Rev

LA-C901P

Date: Sheet

1

of

33 63Tuesday, August 04, 2015

of

33 63Tuesday, August 04, 2015

of

33 63Tuesday, August 04, 2015

1.0

5

@

1 2

+3VS

RM64 0_0603_1%

@

1 2

+3VALW

CM46 0.22U_0402_10V6K

PCIE_CRX_GTX_N1<12> PCIE_CRX_GTX_P1<12>

PEG_CRX_GTX_N0_DGPU<35>

PEG_CRX_GTX_P0_DGPU<35> PCIE_CRX_GTX_N4<12> PCIE_CRX_GTX_P4<12>

D D

From CPU RX

C C

From CPU TX

B B

CLK_PEG_N15P<22> CLK_PEG_N15P#<22>

A A

PCIE_CRX_GTX_N3<12> PCIE_CRX_GTX_P3<12>

PCIE_CRX_GTX_N2<12> PCIE_CRX_GTX_P2<12>

CLKREQ_PCIE#0<10,22>

RM37 0_0402_1%@

1 2

RM38 0_0402_1%@

1 2

5

PEG_CRX_GTX_N3_DGPU<35>

PEG_CRX_GTX_P3_DGPU<35>

PEG_CRX_GTX_N2_DGPU<35>

PEG_CRX_GTX_P2_DGPU<35>

PEG_CRX_GTX_N1_DGPU<35>

PEG_CRX_GTX_P1_DGPU<35>

HD3SS3415Pin Number

21

NC VDD

25

NC

31

NC

35

NC

39

NC

PCIE_CTX_C_GRX_P1<12> PCIE_CTX_C_GRX_N1<12>

PCIE_CTX_C_GRX_P2<12> PCIE_CTX_C_GRX_N2<12>

PCIE_CTX_C_GRX_P3<12> PCIE_CTX_C_GRX_N3<12>

PCIE_CTX_C_GRX_P4<12> PCIE_CTX_C_GRX_N4<12>

CLK_PCIE_P0<10>

CLK_PCIE_N0<10>

1 2 1 2

CM47 0.22U_0402_10V6K

1 2

CM48 0.22U_0402_10V6K CM49 0.22U_0402_10V6K

1 2

CM50 0.22U_0402_10V6K CM51 0.22U_0402_10V6K

1 2

CM52 0.22U_0402_10V6K

1 2 1 2

CM53 0.22U_0402_10V6K

PI3PCIE3415

GND VDD GND VDD

CTX_DRX_P0 CTX_DRX_N0

CTX_DRX_P1 CTX_DRX_N1

CTX_DRX_P2 CTX_DRX_N2

CTX_DRX_P3 CTX_DRX_N3

CLK_N15P_C CLK_N15P#_C

RM41

49.9_0402_1%

SOC_SML0DATA<8>

SOC_SML0CLK<8>

RM65 0_0603_5%

CM36 0.22U_0402_10V6K CM37 0.22U_0402_10V6K

CM34 0.22U_0402_10V6K CM35 0.22U_0402_10V6K

CM32 0.22U_0402_10V6K CM33 0.22U_0402_10V6K

CM30 0.22U_0402_10V6K CM31 0.22U_0402_10V6K

RM22 0_0402_1%@ RM23 0_0402_1%@

CLKREQ_PCIE#0

12

CLKREQ#_DGPU

DM1 RB751V-40_SOD323-2

RM39 33_0402_1% RM40 33_0402_1%

RM42

49.9_0402_1%

12

2.2K_0402_5%

1 2 1 2

12 12

+3VS

RM30

PEG_CRX_GTX_N0_C PEG_CRX_GTX_P0_C

PEG_CRX_GTX_N3_C PEG_CRX_GTX_P3_C

PEG_CRX_GTX_N2_C PEG_CRX_GTX_P2_C

PEG_CRX_GTX_N1_C PEG_CRX_GTX_P1_C

+3VS

CM18

RM31

2.2K_0402_5%

1 2

4

+3V_PCIE_MUX +3V_PCIE_MUX

UM1

1

AI+

2

AI-

3

AOb+

4

AOb-

5

BI+

6

BI-

7

BOb+

8

BOb-

9

VDD_1

10

CI+

11

CI-

12

COb+

13

COb-

14

DI+

15

DI-

16

DOb+

17

DOb-

18

GND_1

19

VDD_2

20

GND_2

21

VDD_3

HD3SS3415RUAR WQFN 42P

+3V_PCIE_MUX +3V_PCIE_MUX

UM2

1

AI+

2

AI-

3

AOb+

4

AOb-

5

BI+

6

BI-

7

BOb+

8

BOb-

9

VDD_1

10

CI+

11

CI-

12

COb+

13

COb-

14

DI+

15

DI-

16

DOb+

17

DOb-

18

GND_1

19

VDD_2

20

GND_2

21

VDD_3

HD3SS3415RUAR WQFN 42P

PCIE_CLK_BUFFER

+3VS

12

RM19

RM21

4.7K_0402_5% 1K_0402_1%

@

CLK_PEG_N15P_R CLK_PEG_N15P#_R

1

CM19

2

0.1U_0402_10V7K

1

2

0.1U_0402_10V7K

CLK+ CLK-

4

UM4

1

PLL_BW_SEL

2

SRCIN

3

SRCIN#

4

OE_0#

5

VDD

6

GND

7

CLK0

8

CLK0#

9

VDD

10

SDATA

PI6CEQ20200LIEX_TSSOP20

GND_9 VDD_8 GND_8 VDD_7 GND_7

GND_6 VDD_6

VDD_5 GND_5

VDD_4 GND_4

GND_3

HEATGND

GND_9 VDD_8 GND_8 VDD_7 GND_7

GND_6 VDD_6

VDD_5 GND_5

VDD_4 GND_4

GND_3

HEATGND

42 41 40 39 38 37

AOa+

36

AOa-

35 34 33

BOa+

32

BOa-

31 30

SEL

29 28

COa+

27

COa-

26 25 24

DOa+

23

DOa-

22 43

42 41 40 39 38 37

AOa+

36

AOa-

35 34 33

BOa+

32

BOa-

31 30

SEL

29 28

COa+

27

COa-

26 25 24

DOa+

23

DOa-

22 43

20

VDDA

19

GNDA

18

IRef

17

OE_1#

16

VDD

15

GND

14

CLK1

13

CLK1#

12

VDD

11

SCLK

1U_0402_6.3V4Z~D

0.1U_0402_16V7K

CM1

CM2

1

2

1U_0402_6.3V4Z~D

0.1U_0402_16V7K

CM4

CM5

1

2

PEG_CTX_GRX_P0_GPU_C PEG_CTX_GRX_N0_GPU_C

PEG_CTX_GRX_P1_GPU_C PEG_CTX_GRX_N1_GPU_C

PEG_CTX_GRX_P2_GPU_C PEG_CTX_GRX_N2_GPU_C

PEG_CTX_GRX_P3_GPU_C PEG_CTX_GRX_N3_GPU_C

1

RM18

CM16

CM15

2.2_0402_1%

2

0.1U_0402_10V7K

RM24 475_0402_1%

12

CLKREQ#_DGPU

12

RM26 33_0402_1% RM27 33_0402_1%

CM20

1U_0402_6.3V

+3VS

12 12

3

0.1U_0402_16V7K CM3

1

2

0.1U_0402_16V7K CM6

1

2

1 2

CM44 0.22U_0402_10V6K CM45 0.22U_0402_10V6K

1 2

CM42 0.22U_0402_10V6K

1 2 1 2

CM43 0.22U_0402_10V6K

CM40 0.22U_0402_10V6K

1 2 1 2

CM41 0.22U_0402_10V6K

1 2

CM38 0.22U_0402_10V6K CM39 0.22U_0402_10V6K

1 2

+3VS

12

CM17 22U_0603_6.3V6M

CLKREQ#_DGPU <41>

DGFX_CLK+_R

DGFX_CLK-_R

RM28

49.9_0402_1%

RM29

49.9_0402_1%

12

3

RM34 10K_0402_5%

1 2

CM62

0.01U_0402_25V7K

1 2

DGFX_CLK+

1 2

DGFX_CLK-

0.01U_0402_25V7K CM63

PEG_CRX_GTX_N0_GPU <22> PEG_CRX_GTX_P0_GPU <22>

PEG_CRX_GTX_N3_GPU <22> PEG_CRX_GTX_P3_GPU <22>

PEG_CRX_GTX_N2_GPU <22> PEG_CRX_GTX_P2_GPU <22>

PEG_CRX_GTX_N1_GPU <22> PEG_CRX_GTX_P1_GPU <22>

PCIE_SEL <11>

PEG_CTX_GRX_P0_GPU <22> PEG_CTX_GRX_N0_GPU <22>

PEG_CTX_GRX_P1_GPU <22> PEG_CTX_GRX_N1_GPU <22>

PEG_CTX_GRX_P2_GPU <22> PEG_CTX_GRX_N2_GPU <22>

PEG_CTX_GRX_P3_GPU <22> PEG_CTX_GRX_N3_GPU <22>

JCDRA

Caldera_PWRGD

CALDERA_PRSNT#

TE_2260531-1

CONN@

2

To N16P-GX TX

FunctionSEL Pin

Low

xI ---> xOa

High

xI ---> xOb

+3VALW

1

CM64

2

@

0.1U_0402_10V7K

5

1

+3VALW

12

B

2

A

RM4 10K_0402_5%

CDR_PRNT# <35,37,41>

CDR_BTN# <41>

RM17 100K_0402_5%

P

4

O

G

UM7

3

TC7SH08FU_SSOP5~D

CDR_ON <41>

PWGD_USBOC <41>

3 4

I2C_CLK <37,38,39> I2C_DAT <37,38,39>

CDR_TXRX_GOOD<41>

To N16P-GX RX

1

Caldera_ON

2 3

CTX_DRX_P0

4

CTX_DRX_N0

5 6

CTX_DRX_P1

7

CTX_DRX_N1

8 9

CTX_DRX_P2

10

CTX_DRX_N2

11 12

CTX_DRX_P3

13

CTX_DRX_N3

14 15 16 17 18 19 20 21 22

CDR_RST#

23 24 25 26

CDR_BTN#

27 28 29 30 31 32 33

DGFX_CLK+

34

DGFX_CLK-

35 36

CM9 0.1U_0402_10V6K

1 2 1 2

37

CM10 0.1U_0402_10V6K

38 39

USB20_P3_PCH

40

USB20_N3_PCH

41 42 43 44 45

CDR_I2C_CLK

RM67 0_0402_1%@

CDR_I2C_DAT

RM66 0_0402_1%@

46 47 48 49 50

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

PLTRST#

BUTTON#

LED_WHITE

LED_RED

REFCLK+

REFCLK-

SSTX+

SSTX-

USBD+

USBD-

SSRX+

SSRX-

I2C_CLK

I2C_DATA

T0+

T0-

GND

T1+

T1-

GND

T2+

T2-

GND

T3+

T3-

GND

R0+

R0-

GND

R1+

R1-

GND

R2+

R2-

GND

R3+

R3-

GND

GND GND GND GND

+3VALW

12

RM35 100K_0402_5%

12

RM36 470K_0402_5%

CRX_DGFX_CRXP0 <35> CRX_DGFX_CRXN0 <35>

CRX_DGFX_CRXP1 <35> CRX_DGFX_CRXN1 <35>

CRX_DGFX_CRXP2 <35> CRX_DGFX_CRXN2 <35>

CDR_LED_WHITE <41> CDR_LED_RED <41>

CRX_DGFX_CRXP3 <35> CRX_DGFX_CRXN3 <35>

USB3_CRX_DTX_N3 <12> USB3_CRX_DTX_P3 <12>

USB3_CTX_DRX_N3 <12>

2

USB3_CTX_DRX_P3 <12>

Compal Secret Data

Deciphered Date

1 2 1 2

2015/01/06 2016/01/06

CDR_ON_ELC <37>

1

2

LM1

EMI@

MCM1012B900F06BP_4P

1

+3VALW

12

CM11

@

0.1U_0402_10V7K

4

O

12

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

RM2 10K_0402_5%

5

1

P

B

2

A

G

3

UM3 TC7SH08FU_SSOP5~D

USB20_P3 <12>

USB20_N3 <12>

PCIE MUX/CLK_BUFFER

PCIE MUX/CLK_BUFFER LA-C901P

LA-C901P

CALDERA_RST# <41> SOC_PLTRST# <10,22>

Compal Electronics, Inc.

1

34 63Tuesday, August 04, 2015

1.0

of

5

D D

1 2

PEG_CRX_GTX_P0_DGPU<34> PEG_CRX_GTX_N0_DGPU<34> PEG_CRX_GTX_P1_DGPU<34> PEG_CRX_GTX_N1_DGPU<34> PEG_CRX_GTX_P2_DGPU<34> PEG_CRX_GTX_N2_DGPU<34> PEG_CRX_GTX_P3_DGPU<34> PEG_CRX_GTX_N3_DGPU<34>

C C

+3VS

1 2

RM7 1K_0402_1%

12

VGA_EN

@

RM8 1K_0402_1%

CM54 0.22U_0402_10V6K CM55 0.22U_0402_10V6K

1 2

CM56 0.22U_0402_10V6K

1 2 1 2

CM57 0.22U_0402_10V6K CM58 0.22U_0402_10V6K

1 2 1 2

CM59 0.22U_0402_10V6K CM60 0.22U_0402_10V6K

1 2

CM61 0.22U_0402_10V6K

1 2

+3VS

W=20mils

10U_0805_10V4Z

CM21

1

2

PEG_CRX_GTX_P0_DGPU_C PEG_CRX_GTX_N0_DGPU_C PEG_CRX_GTX_P1_DGPU_C PEG_CRX_GTX_N1_DGPU_C PEG_CRX_GTX_P2_DGPU_C PEG_CRX_GTX_N2_DGPU_C PEG_CRX_GTX_P3_DGPU_C PEG_CRX_GTX_N3_DGPU_C

1U_0603_10V4Z

10U_0805_10V4Z

CM22

1

2

CM23

4

2.5VOUT

1

CM8

CM7

CM12

2

0.1U_0402_10V7K

9

14

36

UM5

1

OUTB_0+

2

OUTB_0-

3

OUTB_1+

4

OUTB_1-

5

OUTB_2+

6

OUTB_2-

7

OUTB_3+

8

OUTB_3-

10

INA_0+

11

INA_0-

12

INA_1+

13

INA_1-

15

INA_2+

16

INA_2-

17

INA_3+

18

INA_3-

VGA_EN

1 2

RM6 10K_0402_5%

19 20 21 22

23 24 25 26 27

EQA1 EQA0 RATE RXDET

LPBK VIN VDD_SEL SD_TH/READ_EN ALL_DONE

DS80PCI402SQNOPB_WQFN54_10X5P5

EQA1 EQA0

1U_0603_10V4Z

CM24

1

2

51

VDD

VDD41VDD

VDD

45

INB_0+

44

INB_0-

43

INB_1+

42

INB_1-

40

INB_2+

39

INB_2-

38

INB_3+

37

INB_3-

35

OUTA_0+

34

OUTA_0-

33

OUTA_1+

32

OUTA_1-

31

OUTA_2+

30

OUTA_2-

29

OUTA_3+

28

OUTA_3-

54

DEMB1

DEMB1/AD0

53

DEMB0

DEMB0/AD1

52

PRSNT

50

DEMA1/SCL

49

DEMA0/SDA

48

ENSMB

47

EQB1

EQB1/AD2

46

EQB0

EQB0/AD3

55

DAP_GND

1

CM14

CM13

2

0.1U_0402_10V7K

12

RM61 20K_0402_5%

3

CRX_DGFX_CRXP0 <34> CRX_DGFX_CRXN0 <34> CRX_DGFX_CRXP1 <34> CRX_DGFX_CRXN1 <34> CRX_DGFX_CRXP2 <34> CRX_DGFX_CRXN2 <34> CRX_DGFX_CRXP3 <34> CRX_DGFX_CRXN3 <34>

CDR_PRNT# <34,37,41> EC_SMB_CK1 <40,41,51,52> EC_SMB_DA1 <40,41,51,52>

2

Tie 1KΩ to VDD = Register Access SMBus Slave mode FLOAT = Read External EEPROM (Master SMBUS Mode) Tie 1KΩ to GND = Pin Mode

+3VS

RM52 1K_0402_1%

ENSMB

1 2

12

@

RM53 1K_0402_1%

1

EQ Settings DEMA Settings Level control Settings

EQA1

EQA0

dB at

Level

EQB1

EQB0

0

1

0

R

2

0

B B

A A

F

3

1

R

4

0

R

5

R

6

R

F

7

R

1

8

0

F

9

R

F

10

F

11

F

1

12

0

1

13

R

1

14

F

1

15

1 1

16

2.5G

3.7 4.9

5.8 7.9

7.7 9.9

8.9 11

11.2 14.3

11.4 14.6

13.5 17 15 18.5

12.8 18

17.4 22

19.7 24.4

21.1 25.8

21.7 27.4

23.5 29.0

25.8 31.4

27.3 32.7

5

dB at 4G

Suggested Use

< 5 inch trace

5 inch 5–mil trace

5 inch 4–mil trace

10 inch 5–mil trace

10 inch 4–mil trace

15 inch 4–mil trace

20 inch 4–mil trace

25 to 30 inch 4–mil trace

30 inch 4–mil trace

35 inch 4–mil trace

10m, 30awg cable

10m – 12m cable

Level

DEMA1

DEMA0 DEMB0

0 0 0 0 R R R R F F F F 1 1 1 1 1

0 R F 1 0 R F 1 0 R F 1 0 R F

DEM dB Suggested Use

0

<5 inch 4–mil trace

0

<5 inch 4–mil trace

-3.5

10 inch 4–mil trace

0

<5 inch 4–mil trace

-3.5

10 inch 4–mil trace

-6

15 inch 4–mil trace

0

<5 inch 4–mil trace

-3.5

10 inch 4–mil trace

-6

15 inch 4–mil trace

0

<5 inch 4–mil trace

-3.5

10 inch 4–mil trace

-6

15 inch 4–mil trace

0

<5 inch 4–mil trace

-3.5

10 inch 4–mil trace

-6

15 inch 4–mil trace

-9

20 inch 4–mil trace

4

DEMB1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Level Pin Setting Description

1 2 3 4

1kΩ to GND

0

20kΩ to GND

R

Float

F

1kΩ to VDD

1

Suggested Use

<5 inch 4–mil trace

10 inch 4–mil trace

<5 inch 4–mil trace

3

1 2

RM10 1K_0402_1%

1 2

RM12 1K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

EQ*MB

2

1 2

RM20 1K_0402_1%

1 2

RM43 1K_0402_1%

Compal Secret Data

Deciphered Date

EQA1

EQA0

2015/01/06 2016/01/06

EQB1

EQB0

DEM*EGPU

+3VS

RM44 1K_0402_1%

1 2

RM47 1K_0402_1%

Title

PCIE re-driver

Size Document Number Rev

LA-C901P

Date: Sheet of

DEMB1

DEMB0

Compal Electronics, Inc.

35 63Tuesday, August 04, 2015

1

35 63Tuesday, August 04, 2015

1.0

A

B

C

D

E

F

G

H

1 1

+3VS

RS2

DET_SATA# port0

SATA_GP0<12> SATA_GP1<12>

DET_PCIE port7/8

2 2

SATA_GP2<12>

DET_PCIE port11/12

+3VS

0.1U_0402_16V4Z~D

1

3 3

SOC_SMBDATA<8,18,19>

SOC_SMBCLK<8,18,19>

CS7

2

FFS_INT1<8> FFS_INT2<8>

1 2

@

RS13 0_0201_1%

1 2

@

RS14 0_0201_1%

DMN65D8LW-7_SOT323-3

Free Fall Sensor for HDD

10U_0805_10V4Z~D

1

CS2

2

FFS_INT1 FFS_INT2

10K_0402_5%

1 2

RS3 0_0402_1%

13

D

QN7

@

S

+3VS

RS5 10K_0402_5%

1 2

RS6 0_0402_1%

13

D

QN6

@

S

US1

LNG3DM

1

VDD_IO

14

VDD

11

INT 1

9

INT 2

7

SDO/SA0

6

SDA / SDI / SDO

4

SCL/SPC

8

CS

KXCNL-1010_LGA16_3X3

1 2

@

2

G

1 2

@

2

G

GND GND

RES RES RES RES

NC NC

12

RS4 20K_0402_5%

@

12

RS7 20K_0402_5%

@

10 13 15 16

5 12

2 3

IFDET_SATAEX1

IFDET_SATAEX2

HDD/SSD1

SSD2

+5VS +5V_HDD

SATA_CRX_DTX_P0<12> SATA_CRX_DTX_N0<12>

SATA_CTX_DRX_P0<12> SATA_CTX_DRX_N0<12>

SATA_CRX_DTX_N1<12> SATA_CRX_DTX_P1<12>

PCIE_CTX_DRX_P11<12> PCIE_CTX_DRX_N11<12>

SATA_CTX_DRX_P1<12> SATA_CTX_DRX_N1<12>

PCIE_CTX_DRX_N12<12> PCIE_CTX_DRX_P12<12>

PCIE_CRX_DTX_P11<12> PCIE_CRX_DTX_N11<12>

DEVSLP1<12> PCIE_CRX_DTX_P12<12> PCIE_CRX_DTX_N12<12>

CLKREQ_PCIE#3<10>

CLK_PCIE_P3<10> CLK_PCIE_N3<10>

CLKREQ_PCIE#5<10>

CLK_PCIE_P5<10> CLK_PCIE_N5<10>

DEVSLP2<12> SOC_SATALED#<12,38>

SUSCLK<10,32>

PLT_RST#<10,32,41,44>

JP1

@

2

112

JUMP_43X118

1 2

RS12 0_0201_5%

1 2

RS11 0_0201_5%

1 2

RS10 0_0201_5%

1 2

RS9 0_0201_5%

1 2

RS15 0_0402_1%@

1 2

RS8 0_0402_1%@

+5V_HDD

0.1U_0402_25V6K~D

10U_0603_25V6M

1

CS6

CS1

2

SATA_CRX_R_DTX_P0 SATA_CRX_R_DTX_N0

SATA_CTX_R_DRX_P0 SATA_CTX_R_DRX_N0

SATA_CRX_DTX_N1 SATA_CRX_DTX_P1

PCIE_CTX_DRX_P11 PCIE_CTX_DRX_N11 FFS_INT2_CONN SATA_CTX_DRX_P1 SATA_CTX_DRX_N1

PCIE_CTX_DRX_N12 PCIE_CTX_DRX_P12

PCIE_CRX_DTX_P11 PCIE_CRX_DTX_N11

PCIE_CRX_DTX_P12 PCIE_CRX_DTX_N12

PCIELED# IFDET_SATAEX1 IFDET_SATAEX2 SUSCLK_HDD

+5V_HDD

DET_SATA#/PCI-E

1000P_0402_50V7K~D

1

CS5

2

Reserve for Legacy SATA

JHDD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36 37 38 39 40

41

36

G1

42

37

G2

43

38

G3

44

39

G4

45

40

G5

STARC_111H40-100100-G7-R

CONN@

Module Type 0 SATA 1 PCI-E

+5VS

+3VS

G

2

13

D

S

QS1

4 4

A

B

DMN65D8LW-7_SOT323-3

DS1 SDM10U45-7_SOD523-2~D

12

@

RS1 100K_0402_5%

21

C

FFS_INT2_CONNFFS_INT2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

F

Compal Electronics, Inc.

Title

SATA HDD/M2 cards

Size Document Number Rev

LA-C901P

Date: Sheet

Date: Sheet of

G

36 63Tuesday, August 04, 2015

H

1.0

of

5

4

3

2

1

D D

1 2

RE4 0_0603_1% RE6 0_0603_5%

0.1U_0402_16V4Z CE10

1

@

2

+3.3V_F383

D

2

G

S

+3.3V_F383

D

2

G

S

+3.3V_F383

D

2

G

S

1 2

12

100K_0402_5%

12

100K_0402_5%

12

100K_0402_5%

@ @

1U_0805_10V7

CE6

PCIE_GEN3#_GEN2<41>

RE16

SLP_S3

1

QE4 ME2N7002E1-G 1N SOT-23-3 ESD 1KV

3

RE18

ACIN#

1

QE7 ME2N7002E1-G 1N SOT-23-3 ESD 1KV

3

RE24

BATT_CHG_LED

1

QE9 ME2N7002E1-G 1N SOT-23-3 ESD 1KV

3

W=40mils

+3.3V_F383

0.1U_0402_16V4Z~D CE7

1

@

2

JELC

1

2

3

4

5

6

7

GND1

8

GND2

AMPHE_G846A06201EU

CONN@

+3.3V_F383

+5VALW +5VS

+3.3V_F383

C C

Close to JP1

B B

A A

PM_SLP_S3#<6,10,13,41>

ACIN<10,22,41,51,52>

BATT_CHG_LED#<41>

+3.3V_F383

1

2

1 2

RE8

1K_0402_1%~D

+3.3V_F383

1 2

RE21 1K_0402_1%~D

PM_SLP_S4#<6,10,13, 41,54>

PM_SLP_S5#<6,10,41>

BATT_LOW_LED#<41>

1U_0805_10V7

CE1

0.1U_0402_16V4Z~D CE2

1

@

2

USB20_P7<12> USB20_N7<12>

+3.3V_F383

PCIE_GEN3#_GEN2 AMD#_NV_R

CE13 0.1U_0402_16V4Z~D

1

2

G

2

G

2

G

22P_0402_50V8J~D

0.1U_0402_16V4Z~D CE4

CE3

2

1

2

USB20_P7 USB20_N7

@

CE16 0.1U_0402_16V4Z~D

CE15 0.1U_0402_16V4Z~D

CE14 0.1U_0402_16V4Z~D

CE17 0.1U_0402_16V4Z~D

1

2

+3.3V_F383

12

RE45

100K_0402_5%

SLP_S4

1

D

QE14 ME2N7002E1-G 1N SOT-23-3 ESD 1KV

S

3

+3.3V_F383

12

RE17

100K_0402_5%

SLP_S5

1

D

QE6 ME2N7002E1-G 1N SOT-23-3 ESD 1KV

S

3

+3.3V_F383

12

RE22

100K_0402_5%

BATT_LOW_LED

1

D

QE8 ME2N7002E1-G 1N SOT-23-3 ESD 1KV

S

3

10 18

17 16 15 14 13 12

@

CE18 0.1U_0402_16V4Z~D

1

2

UE1

6

P0.0

VDD

P0.1

4

P0.2

D+

5

P0.3

D-

P0.4

7

P0.5

REGIN

8

P0.6

VBUS

P0.7

9

RST#/C2CK

P1.0

P3.0/C2D

P1.1 P1.2

P2.0

P1.3

P2.1

P1.4

P2.2

P1.5

P2.3

P1.6

P2.4

P1.7

P2.5 P2.6 P2.711GND

C8051F383-GQ_LQFP32_7X7

+3.3V_F383

S5 ON OFF

1 2

12

RE24.7K_0402_5%~D

12

RE34.7K_0402_5%~D

SPI_MOSO

+3VS

LID_SW_IN# <38,41>

5

12

RE1015_0402_5%

6

12

RE1215_0402_5%

1 7 3 8

22P_0402_50V8J~D

1

CE20

2

@

J1

2

JUMP_43X118

UE9

5

IN

4

EN

SY6288C20AAC_SOT23-5

S0ONS3 ON

I2C_DAT I2C_CLK

UE2

SO

DI CLK CS HOLD WP VCC

VSS

W25Q80DVSSIG_SO8

112

1

OUT

2

GND

3

OC

S4

ON

OFF

2

RE11 15_0402_5%

4

1 2

RE19 10K_0402_5%

place RE5 as close as UE1

2

SPI_MOCLK

1

SPI_MOSO

32

SPI_MOSI

31

SPI_MOCS#

30

I2C_DAT

29

I2C_CLK

28 27

26

SLP_S3

25

BATT_CHG_LED

24

ACIN#

23

LID_SW_IN#_D

22

BATT_LOW_LED

21

SLP_S5

20

SLP_S4

19 3

1 2

@

RE5 0_0603_1%

I2C_DAT <34,38, 39>

I2C_CLK <34, 38,39> CDR_PRNT# <34,35,41> CDR_ON_ELC <34>

SDMK0340L-7-F_SOD323-2~D

1 2

CE8 0.1U_0402_16V4Z~D@

1 2

CE9 0.1U_0402_16V4Z~D@

SPI_MOSI

+3.3V_F383

SPI_MOCLK_R

3V_F383_ON<41>

SPI_MOCLK_R

12

RE910K_0402_5%

+3VALW_EC

12

LID_SW_IN#

DE1

1 2

RE13 10K_0402_5 RE14 10K_0402_5 RE15 10K_0402_5

+3.3V_F383

4.7U_0805_10V4Z

SPI_MOCS#

1 2 1 2

0.1U_0402_16V4Z~D CE19

1

2

+3VALW +3.3V_F383

1

CE21

2

+3.3V_F383 behavior

AC IN BATT only

AC mode battery full in S5:turn off ELC controller

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

ELC (1)C8051F383

Size Document Number Rev

Custom

LA-C901P

Date: Sheet

1

of

37 63Tuesday, August 04, 2015

of

37 63Tuesday, August 04, 2015

of

37 63Tuesday, August 04, 2015

1.0

5

4.7K_0402_1%~D

I2C_CLK<34,37,39> I2C_DAT<34,37,39>

RE1 10K_0402_5

+3VLP

RK1 100K_0402_5%

1 2

1

CK1

0.1U_0402_16V7K

2

RE26

12

RE37 10K_0402_5

+5VS

2

ON/OFF_BTN#

+3.3V_F383

12

100K_0402_5%

12

RE36

61

DMN66D0LDW-7_SOT363-6~D

LID_SW

I2C_CLK I2C_DAT

AD0_UE3 AD1_UE3 AD2_UE3 AD3_UE3

SATA_LED_ACT

QE3A

2

G

UE3

24

RESET

25

SCL

26

SDA

31

A0

32

A1

1

A2

2

A3

12

N.C.

13

N.C.

28

N.C.

29

N.C.

30

N.C.

7

GND

18

GND

TLC59116FIRHBR_VQFN32_5X5

1

D

QE13 ME2N7002E1-G 1N SOT-23-3 ESD 1KV

S

3

D D

C C

B B

A A

ON/OFF switch power button

+3.3V_F383

RE28

4.7K_0402_1%~D

RE27

4.7K_0402_1%~D

12

RE29

4.7K_0402_1%~D

RE38

4.7K_0402_1%~D

12

+3VS

12

@

SOC_SATALED#<12,36>

Remove SW2 for layout routing dat.05/06

Bottom Side pop only before MP

5

2

5

TP_EN

OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8

OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15

Vcc

GND GND

4

27 3

4 5 6 8 9 10 11 14 15 16 17 19 20 21 22

23 33

HDD_B

34

QE2B

HDD_B_7313# HDD_R

DMN66D0LDW-7_SOT363-6~D

61

QE2A

HDD_R_7313# HDD_G

34

DMN66D0LDW-7_SOT363-6~D

QE3B

HDD_G_7313#

DMN66D0LDW-7_SOT363-6~D

1

2

+3.3V_F383

ALIEN_LED_R_DRV# ALIEN_LED_G_DRV# ALIEN_LED_B_DRV# LOGO_LED_R_DRV# LOGO_LED_G_DRV# LOGO_LED_B_DRV# LED_R_7313# LED_G_7313# LED_B_7313# PWR_R_7313# PWR_G_7313# PWR_B_7313# HDD_R_7313# HDD_G_7313# HDD_B_7313#

+3VALW

470K_0402_5%~D

12

61

2

CT114

100P_0402_50V8J~D

RT88

RT90

8.2_0402_5%~D

QT2A

DMN66D0LDW-7_SOT363-6~D

1

2

CE24

0.1U_0402_16V4Z~D

12

CT113

0.047U_0402_25V7K

+3VS_TOUCH

10U_0603_6.3V6M~D

CT115

1

2

5

3

Power LED

+5VALW

100K_0402_5%

12

RE30

1

D

PWR_LED#<41>

2

G

QE11

S

ME2N7002E1-G 1N SOT-23-3 ESD 1KV

3

Power_LED

+5VALW

QE10

G

2

D

1 3

S

LP2301ALT1G 1P SOT-23-3

+LED_PWR

2

LOGO_LED_R_DRV# LOGO_LED_G_DRV# LOGO_LED_B_DRV#

ALIEN_LED_R_DRV# ALIEN_LED_G_DRV# ALIEN_LED_B_DRV#

1

+5VS

0.1U_0402_16V4Z

W=20mils

CE30

CE28

1

2

LID_SW

JSLIT

1

2

3

4

5

6

7

8

9

10

11

12

13

GND

14

GND

ACES_50208-01201-P01_12P

CONN@

Logic up LED board

+5VALW

12

RE34 100K_0402_5%

1

D

LID_SW_IN#<37,41>

LID_SW_IN#

2

G

S

3

LID_SW

QE12 ME2N7002E1-G 1N SOT-23-3 ESD 1KV

0.1U_0402_16V4Z

+3VALW

+LED_PWR

CAPS_LED<41>

WLAN_LED#<32>

ON/OFF_BTN#<41>

T97@

PTP pin define VDD I2C_DATA I2C_CLK GND ATTN PTP_DISABLE#(CLOSE LID)

+3VS_TOUCH I2C_1_SDA<11> I2C_1_SCL<11>

+3VS_TOUCH

TP_INT#<41>

PTP_DISABLE#<41>

TP_DATA<41>

TP_CLK<41>

PTP_KBBL#<41>

+3VS_TOUCH

1 2

CE25 1U_0402_6.3V6K~D

1 2

RE70 0_0402_5%@

1 2

RE71 0_0402_5%@

1 2

RE72 100K_0402_5%

1 2

RE73 10K_0402_5%

PS2_DATA PS2_CLK PTP_KBBL#(KB BL) NC

RT89

39_0402_5%~D

12

34

QT2B

DMN66D0LDW-7_SOT363-6~D

+3VALW

+3VS

1 2

@

RT81 0_0603_1%

1 2

@

RT82 0_0603_5%

TP_EN<41>

UT5

VOUT

VIN

VOUT

VIN

CT

ON

VBIAS

GND GND

AOZ1336_DFN8_2X2

7 8

6

5 9

1 2

TP_EN I2C_1_SDA_R

3

4

+3VS_TOUCH+V_TP

1

@

2

CT110

CT111

@

2

2200P_0402_25V7K

I2C_1_SDA

I2C_1_SCL I2C_1_SCL_R

0.1U_0402_10V6K

AOZ1336(SA00006U600)

+5VS

1

CE23

LED_R_7313# LED_B_7313# LED_G_7313# CAPS_LED WLAN_LED# HDD_R HDD_G HDD_B ON/OFF_BTN#

PWR_G_7313# PWR_R_7313# PWR_B_7313# LID_SW_IN#

I2C_1_SDA_R I2C_1_SCL_R

TP_INT# PTP_DISABLE# TP_DATA TP_CLK PTP_KBBL#

2

JPWR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

GND

32

GND

ACES_50506-03041-P01

CONN@

Logic low LED board

+3VS_TOUCH

+3VS

2

G

S

D

QT1B

5

DMN66D0LDW-7_SOT363-6

34

SGD

QT1A DMN66D0LDW-7_SOT363-6

10K_0402_5%

61

12

RT84

12

RT85 10K_0402_5%

TPS22967(SA000070S00)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

ELC (2)PTP/PWR SW

Size Document Number Rev

Custom

LA-C901P

Date: Sheet

1

of

38 63Tuesday, August 04, 2015

of

38 63Tuesday, August 04, 2015

of

38 63Tuesday, August 04, 2015

1.0

5

I2C address

+3.3V_F383

12

RE43

4.7K_0402_1%~D

12

UE1 (sheet 10 in Caldera board) UE4 (sheet 39) UE3 (sheet 38) 3rd LED drive (reserve)

4.7K_0402_1%~D

RE40

4.7K_0402_1%~D

I2C_CLK<34,37,38> I2C_DAT<34,37,38>

RE39

4.7K_0402_1%~D

12

+3.3V_F383

RE41

RE44 10K_0402_5

12

I2C_DAT AD0_UE4

AD1_UE4 AD2_UE4 AD3_UE4

D D

RE42

4.7K_0402_1%~D

12

C C

A3 A2 A1 A0 0 0

0

001

UE4

24

RESET

25

SCL

26

SDA

31

A0

32

A1

1

A2

2

A3

12

N.C.

13

N.C.

28

N.C.

29

N.C.

30

N.C.

7

GND

18

GND

TLC59116FIRHBR_VQFN32_5X5

0 1 1 0

4

Default use +3VS

1 0 1 0

27

Vcc

3

KB_LED_R1_DRV#

OUT0

4

KB_LED_G1_DRV#I2C_CLK

OUT1

5

KB_LED_B1_DRV#

OUT2

6

KB_LED_R2_DRV#

OUT3

8

KB_LED_G2_DRV#

OUT4

9

KB_LED_B2_DRV#

OUT5

10

KB_LED_R3_DRV#

OUT6

11

KB_LED_G3_DRV#

OUT7

14

KB_LED_B3_DRV#

OUT8

15

KB_LED_R4_DRV#

OUT9

16

KB_LED_G4_DRV#

OUT10

17

KB_LED_B4_DRV#

OUT11

19

OUT12

20

OUT13

21

OUT14

22

OUT15

23

GND

33

GND

1 2

+5VS +5V_3V_ELC +3VS

+3.3V_F383

1

CE29

0.1U_0402_16V4Z~D

2

@

RE7 0_0603_5%

1 2

@

RE20 0_0603_1%

100K_0402_5%

KB_LED_R1_DRV#

100K_0402_5%

KB_LED_G1_DRV#

100K_0402_5%

KB_LED_B1_DRV#

RE46

RE48

RE50

3

+5V_3V_ELC

+3VS

12

+3VS

12

+3VS

12

RE47 39K_0402_5%

KB_LED_R1_DRV

34

QE15B DMN66D0LDW-7_SOT363-6~D

5

+5V_3V_ELC

12

RE49 39K_0402_5%

KB_LED_G1_DRV

34

QE16B DMN66D0LDW-7_SOT363-6~D

5

+5V_3V_ELC

12

RE51 39K_0402_5%

KB_LED_B1_DRV

34

QE17B DMN66D0LDW-7_SOT363-6~D

5

61

2

QE15A DMN66D0LDW-7_SOT363-6~D

61

2

QE16A DMN66D0LDW-7_SOT363-6~D

61

QE17A DMN66D0LDW-7_SOT363-6~D

2

KB_LED_R1

KB_LED_G1

KB_LED_B1

2

KB_LED_R3_DRV#

KB_LED_G3_DRV#

KB_LED_B3_DRV#

RE58

100K_0402_5%

RE60

100K_0402_5%

RE62

100K_0402_5%

1

+5V_3V_ELC

+3VS

12

+3VS

12

+3VS

12

RE59 39K_0402_5%

KB_LED_R3_DRV

34

QE21B DMN66D0LDW-7_SOT363-6~D

5

+5V_3V_ELC

12

RE61 39K_0402_5%

KB_LED_G3_DRV

34

QE22B DMN66D0LDW-7_SOT363-6~D

5

+5V_3V_ELC

12

RE63 39K_0402_5%

KB_LED_B3_DRV

34

QE23B DMN66D0LDW-7_SOT363-6~D

5

61

2

QE21A DMN66D0LDW-7_SOT363-6~D

61

2

QE22A DMN66D0LDW-7_SOT363-6~D

61

2

QE23A DMN66D0LDW-7_SOT363-6~D

KB_LED_R3

KB_LED_G3

KB_LED_B3

+5V_3V_ELC

+3VS

JKBBL

1

2

3

KB_LED_R1 KB_LED_G1 KB_LED_B1 KB_LED_R2 KB_LED_G2 KB_LED_B2 KB_LED_R3 KB_LED_G3

B B

A A

5

KB_LED_B3 KB_LED_R4

+5VS

KB_LED_G4 KB_LED_B4

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

ACES_50552-02001-001

CONN@

KB_LED_R2_DRV#

21

GND

22

GND

KB_LED_G2_DRV#

KB_LED_B2_DRV#

4

RE52

100K_0402_5%

RE54

100K_0402_5%

RE56

100K_0402_5%

12

+3VS

12

+3VS

12

RE53 39K_0402_5%

KB_LED_R2_DRV

34

QE18B DMN66D0LDW-7_SOT363-6~D

5

+5V_3V_ELC

12

RE55 39K_0402_5%

KB_LED_G2_DRV

34

QE19B DMN66D0LDW-7_SOT363-6~D

5

+5V_3V_ELC

12

RE57 39K_0402_5%

KB_LED_B2_DRV

34

QE20B DMN66D0LDW-7_SOT363-6~D

5

3

KB_LED_R2

61

2

QE18A DMN66D0LDW-7_SOT363-6~D

KB_LED_G2

61

2

QE19A DMN66D0LDW-7_SOT363-6~D

KB_LED_B2

61

2

QE20A DMN66D0LDW-7_SOT363-6~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

2

100K_0402_5%

KB_LED_R4_DRV#

100K_0402_5%

KB_LED_G4_DRV#

100K_0402_5%

KB_LED_B4_DRV#

RE64

RE66

RE68

+5V_3V_ELC

+3VS

12

+3VS

12

+3VS

12

RE65 39K_0402_5%

KB_LED_R4_DRV

34

QE24B DMN66D0LDW-7_SOT363-6~D

5

+5V_3V_ELC

12

RE67 39K_0402_5%

KB_LED_G4_DRV

34

QE25B DMN66D0LDW-7_SOT363-6~D

5

+5V_3V_ELC

12

RE69 39K_0402_5%

KB_LED_B4_DRV

34

QE26B DMN66D0LDW-7_SOT363-6~D

5

Title

Size Document Number Rev

Custom

Date: Sheet

61

2

QE24A DMN66D0LDW-7_SOT363-6~D

61

2

QE25A DMN66D0LDW-7_SOT363-6~D

61

QE26A DMN66D0LDW-7_SOT363-6~D

2

Compal Electronics, Inc.

ELC (3)KBBL

LA-C901P

1

KB_LED_R4

KB_LED_G4

KB_LED_B4

1.0

of

39 63Tuesday, August 04, 2015

of

39 63Tuesday, August 04, 2015

of

39 63Tuesday, August 04, 2015

5

4

3

2

1

Main: NCT7718W(SA000067P00) Address:1001_100xb(0x98) Second: ADM1032ARMZ-REEL(SA010320110)

D D

Address:100_1100(0x4C)

1

@

CF3 100P_0402_50V8J

2

SENSOR_DIODE_P1

SENSOR_DIODE_N1

C

2

B

E

QF1

3 1

MMBT3904WT1G_SC70-3

Diode circuit s used for skin temp sensor (placed near CPU).

UF1

@

ADM1032ARMZ-REEL

SA010320110

1

CF4 470P_0402_50V7K

2

+3VS

1

2

1 2

RF4

4.7K_0402_5%

0.1U_0402_10V7K CF2

UF1

1

VDD

2

D+

3

DT_CRIT#4GND

NCT7718W_MSOP8

ALERT#

8

EC_SMB_CK2

SCL

7

EC_SMB_DA2

SDA

6 5

EC_SMB_CK2 <8,22,41,46> EC_SMB_DA2 <8,22,41,46>

CPU_FAN_PWM<41> CPU_FAN_FB<41>

Place CF3 close to QF1 as possible.

CPU FAN control circuit

+3VS

10K_0402_5%

RF1

1 2

SDMK0340L-7-F_SOD323-2

+5VS

1

10K_0402_5%

RF2

DF1

RF3

2

1 2

12

3 4

5 6

22U_0805_6.3VAM

CF1

JFAN1

1 2 3 4

GND1 GND2

E-T_3806K-F04N-03R

CONN@

Main: W83L771AWG-2(SA00003PU00) Address:1001_101xb(0x9A) Second: ADM1032ARMZ-2R(SA010320120)

C C

Address:100_1101(0x4D)

1

@

CF7 100P_0402_50V8J

2

SENSOR_DIODE_P2

SENSOR_DIODE_N2

C

2

B

E

QF2

3 1

MMBT3904WT1G_SC70-3

Diode circuit s used for skin temp sensor (placed between DIMM1 and DIMM2).

UF2

@

ADM1032ARMZ-2R

SA010320120

1

CF8 470P_0402_50V7K

2

+3VS

0.1U_0402_10V7K

1

2

1 2

RF8

6.8K_0402_5%~D

CF6

UF2

1

VDD

SCLK

2

D+

SDATA

3

ALERT#

DTHERM#4GND

W83L771AWG-2_TSSOP8

8 7 6 5

EC_SMB_CK2 EC_SMB_DA2

GPU_FAN_PWM<41> GPU_FAN_FB<41>

GPU FAN control circuit

+3VS

10K_0402_5%

RF5

1 2

SDMK0340L-7-F_SOD323-2

+5VS

RF6

1 2

12

DF2

22U_0805_6.3VAM

1

10K_0402_5%

RF7

2

1 2 3 4

5 6

CF5

JFAN2

1 2 3 4

GND1 GND2

E-T_3806K-F04N-03R

CONN@

Place CF7 close to QF2 as possible.

JTH

EC_SMB_CK1<35,41,51,52> EC_SMB_DA1<35,41,51,52>

B B

EC_SMB_CK1 EC_SMB_DA1

1

2

3

G1

4

G2

ACES_50271-00201-001

CONN@

INT_KBD Connector

JKB

3030GND

29

KSO7

29

28

KSO0

28

27

KSI1

27

26

KSI7

26

25

KSO9

25

24

KSI6

24

23

KSI5

KSI[0..7]<41>

KSO[0..17]<41>

KSI[0..7]

KSO[0..17]

KSO3 KSI4 KSI2 KSO1 KSI3 KSI0 KSO13 KSO5 KSO2 KSO4 KSO8 KSO6 KSO11 KSO10 KSO12 KSO14 KSO15 KSO16 KSO17

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_50552-03001-001

CONN@

31 32

GND

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

FAN/KB/Thermal sensor

Size Document Number Rev

LA-C901P

Date: Sheet of

1

40 63Tuesday, August 04, 2015

1.0

5

@EMI@

RK9 0_0402_5%

1 2

KSI[0..7]<40>

KSO[0..17]<40>

PM_CLKRUN#<8>

DSW_EN<42>

13

D

QV8 2N7002KW_SOT323-3

S

+3VALW_EC

1

CK3

0.1U_0402_10V7K

2

H_PROCHOT# <6,51,52>

1

CK2

0.1U_0402_10V7K

2

WLAN_WAKE#<32>

SERIRQ<8>

ESPI_CS#<8> ESPI_IO3_R<8> ESPI_IO2_R<8> ESPI_IO1_R<8> ESPI_IO0_R<8>

ESPI_CLK_R<8>

PLT_RST#<10,30,32,36,44>

EC_SCI#<6>

SLP_SUS#<10,14>

KSI[0..7]

KSO[0..17]

EC_SMB_CK1<35,40,51,52> PWR_LED# <38> EC_SMB_DA1<35,40,51,52> EC_SMB_CK2<8,22,40,46> EC_SMB_DA2<8,22,40,46>

PM_SLP_S3#<6,10,13,37> PM_SLP_S4#<6,10,13,37,54>

PS_ID<51>

WAKE_PCH#<10>

CPU_FAN_FB<40> GPU_FAN_FB<40>

EC_TX<32> EC_RX<32>

PCH_PWROK<10>

PM_SLP_S0#<6,10>

1 2

RK38 0_0402_5%@

1 2

RK39 0_0402_5%

+1.0V_PGOOD<55> VCCST_PG_EC<10>

1 2

+3VALW

D D

PLT_RST#

CK8

@ESD@

0.047U_0402_16V4Z

Place CK8 close to RC13.1

+3VALW_EC

1 2

RK20 4.7K_0402_5%

1 2

C C

RK22 4.7K_0402_5%

+3VALW_EC

+3VS

Please close to EC

B B

A A

TBT_RESET_N_EC<44>

RK35

10K_0402_5%

VCOUT1_PH

RK33

100K_0402_5%

EC_SMI#<11>

RK18 10K_0402_5%

+3VALW_EC

12

RM1 100K_0402_5%~D

CLKREQ#_DGPU

VR_HOT#<58>

+3VS

12

@

1 2

1

2

+3VALW_EC

RPK1

2.2K_0804_8P4R_5%

12

CK21

@ESD@

0.1U_0402_10V7K

12

CK17

@ESD@

0.1U_0402_10V7K

12

CK15

@ESD@

0.1U_0402_10V7K

12

CK18

@ESD@

0.1U_0402_10V7K

1 2

RK40 0_0402_5%

1 2

RK41 0_0402_5%

12

@

RK23

1 2

60.4K_0402_1%

+3VLP

RK8,CK10 follow Tulip BTM for 9022 setting dat.03/27

EC_ESB_CLK EC_ESB_DAT

45 36 27 18

PM_SLP_S0#

PM_SLP_S5#

PM_SLP_S3#

PM_SLP_S4#

@

PCH_PWROK

RK25 0_0402_1%

RK34 0_0402_5%

1

CK27

0.033U_0402_16V

2

5

@

RK4 0_0603_1%

1 2

@

RK6 0_0603_5%

@EMI@

CK9

0.1U_0402_10V7K

12

@

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

EC_SMI#_R

@

12

2

G

RK8 47K_0402_5%@ CK10 0.1U_0402_10V7K

CLKREQ#_DGPU <34>

1 2

4

2

1

+3VS_WLAN_NGFF

RK2 10K_0402_5%

1 2

EC_KBRST# SERIRQ ESPI_CS# ESPI_IO3_R ESPI_IO2_R ESPI_IO1_R ESPI_IO0_R

ESPI_CLK_R PLT_RST# EC_RST# EC_SCI# SLP_SUS#

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

PM_SLP_S3# PM_SLP_S4# EC_SMI#_R PS_ID EC_ESB_CLK EC_ESB_DAT CLKREQ#_DGPU WAKE_PCH# CPU_FAN_FB GPU_FAN_FB EC_TX EC_RX PCH_PWROK PM_SLP_S0# PM_CLKRUN#_R

+1.0V_PGOOD VCCST_PG_EC

@EMI@

CK4 1000P_0402_50V7K

122 123

+3VALW_EC

2

@EMI@

CK5 1000P_0402_50V7K

1

UK1

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CLK1/GPIO44

78

EC_SMB_DAT1/GPIO45

79

EC_SMB_CLK2/GPIO46

80

EC_SMB_DAT2/GPIO47

6

PM_SLP_S3#/GPIO04

14

GPIO07

15

GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

AC_PRESENT/GPIO0D

25

PWM2/GPIO11

28

FAN_SPEED1/GPIO14

29

FANFB1/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

PBTN_OUT#/GPIO5D PM_SLP_S4#/GPIO5E

LPC & MISC

Int. K/B Matrix

EMI@

LK1 FBMA-L11-160808-800LMT_0603

1 2

+3VLP

111

22

33

96

125

9

VCC

VCC0

VCC_LPC

PWM Output

VCIN1_BATT_TEMP/AD0/GPIO38 VCIN1_BATT_DROP/AD1/GPIO39

AD Input

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

GPIO

SM Bus

VCIN1_ADP_PROCHOT/GPXIOA05

VCOUT1_PROCHOT#/GPXIOA06

VCOUT0_MAIN_PWR_ON/GPXIOA07

GPIO

GPO

GPI

GND

11

24

35

94

113

+EC_VCCA

67

AVCC

EC_VCCST_PG/GPIO0F

BEEP#/GPIO10

EC_FAN_PWM/GPIO12

AC_OFF/GPIO13

ADP_I/AD2/GPIO3A

AD_BID/AD3/GPIO3B

AD4/GPIO42 AD5/GPIO43

DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

DA2/GPIO3E DA3/GPIO3F

EC_MUTE#/PSCLK1/GPIO4A

USB_EN#/PSDAT1/GPIO4B

PSCLK2/GPIO4C PSDAT2/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

ENKBL/GPXIOA00

WOL_EN/GPXIOA01

ME_EN/GPXIOA02

VCIN0_PH1/GPXIOD00

MISO/GPIO5B

MOSI/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A

EC_CIR_RX/AD6/GPIO40

SYS_PWROK/AD7/GPIO41 BATT_CHG_LED#/GPIO52

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

BATT_LOW_LED#/GPIO55

SYSON/GPIO56 VR_ON/GPIO57

DPWROK_EC/GPIO59

EC_RSMRST#/GPXIOA03

GPXIOA04

BKOFF#/GPXIOA08

GPXIOA09

PCH_PWR_EN/GPXIOA10

PWR_VCCST_PG/GPXIOA11

VCIN1_AC_IN/GPXIOD01

EC_ON/GPXIOD02 ON/OFF#/GPXIOD03 LID_SW#/GPXIOD04

SUSP#/GPXIOD05

GPXIOD06

PECI/GPXIOD07

V18R/VCC_IO2

AGND

KB9022QD_LQFP128_14X14

69

LK2

ECAGND

FBMA-L11-160808-800LMT_0603

W=20mils

ME_FWP PCH has internal 20K pulldown (suspend power rail)

ME_EN

12

@

RK24 1K_0402_5%

Reserve for abnormal shutdown

POK<51,53>

4

1 2

DK3 RB751V-40_SOD323-2

1 2

DK2 RB751V-40_SOD323-2

EC_RSMRST#

PCH_PWROK

1

CK6

0.1U_0402_10V7K

2

ECAGND

GPIO50

12

3

+3VALW

Ra

Rb

RK7

ID@

27K_0402_1%

SD034270280

21

CDRA_LED WHITE_T

23

BEEP#

26

CPU_FAN_PWM

27

GPU_FAN_PWM

63

BATT_TEMP

64

PCIE_WAKE#

65

ADP_I

66

AD_BID0

75

USBCHG_DET_EC#

76

EDP_BKLTEN

68

EN_INVPWR

70

TBT_PCIE_WAKE#

71

SUSWARN#

72

LCD_TEST

83

EC_MUTE#

84

PM_SLP_S5#

85

CDR_TXRX_GOOD

86

SYS_PWROK

87

TP_CLK

88

TP_DATA

97

SUSACK#

98

EN_WOL#

99

ME_EN

109

VCIN0_PH

119

PWRSHARE_EN_EC#

120

TP_INT#

126

CDRA_LED RED_T

128

3V_F383_ON

73

VR_PWRGD

74

CDR_BTN#

89

PD_IRQ#

90

BATT_CHG_LED#

91

CAPS_LED

92

PWR_LED#

93

BATT_LOW_LED#

95

SYSON

121

IMVP_VR_ON VR_ON_EC

127

100

EC_RSMRST#

101

PCIE_GEN3#_GEN2

102

VCIN1_PH

103

VCOUT1_PH

104

VCOUT0_PH#

105

BKOFF#

106

PBTN_OUT#

107 108

110 112 114 115 116 117 118

124

+V18R

N

3

1 2

RK17 43_0402_1%

ACIN EC_ON ON/OFF_BTN# LID_SW_IN# SUSP# USB_PWR_EN#

1 2

PECI_EC

RK21 43_0402_1%

1 2

RK31 0_0402_1%

ot support 1.8V

+3VALW_EC

47K_0402_5%

12

RK27

RST#

.1U_0402_16V7K~D

2

CK26

1

10K_0402_5%

Board ID

RK3 100K_0402_1%

1 2

AD_BID0

1

RK7 43K_0402_1%

@

1 2

CK7

0.1U_0402_10V7K

2

Pilot Build

BEEP# <31>EC_KBRST#<8> CPU_FAN_PWM <40> GPU_FAN_PWM <40>

12

CK11 100P_0402_50V8J

PCIE_WAKE# <30> ADP_I <51,52>

USBCHG_DET_EC# <33> EDP_BKLTEN <6>

EN_INVPWR <20>

TBT_PCIE_WAKE# <44> SUSWARN# <10>

LCD_TEST <20> EC_MUTE# <31>

PM_SLP_S5# <6,10,37> CDR_TXRX_GOOD <34> SYS_PWROK <10> TP_CLK <38> TP_DATA <38>

SUSACK# <10> EN_WOL# <30> ME_EN <9> VCIN0_PH <51>

PWRSHARE_EN_EC# <33> TP_INT# <38>

3V_F383_ON <37>

VR_PWRGD <58>

CDR_BTN# <34> PD_IRQ# <46> BATT_CHG_LED# <37> CAPS_LED <38>

BATT_LOW_LED# <37>

DPWROK_EC <10>

PCIE_GEN3#_GEN2 <37>

VCIN1_PH <51> VCOUT0_PH# <53>

BKOFF# <20> PBTN_OUT# <6,10>

CDR_ON <34>

ACIN <10,22,37,51,52> EC_ON <53> ON/OFF_BTN# <38> LID_SW_IN# <37,38> SUSP# <13,42,44> USB_PWR_EN# <33>

@

+3VS

12

RK26

M_THERMAL#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SD028000080 0_0402_5% SD034120280 12K_0402_1% SD034150280 15K_0402_1% SD028200280 20K_0402_1% SD034270280 27K_0402_1% SD034330280 33K_0402_1% SD034430280 43K_0402_1% SD034560280 56K_0402_1% SD034750280 75K_0402_1% SD034100380 100K_0402_1% SD034130380 130K_0402_1% SD034160380 160K_0402_1% SD034200380 200K_0402_1% SD000001B80 240K_0402_1% SD00000G280 270K_0402_1% SD034330380 330K_0402_1% SD028430380 430K_0402_1%

ECAGND

VR_ON_EC

Place CE12 between DK1 and RK14

VCCST_PG_EC

Place CK13 between DK1 and UK1

1 2

@

RK14 0_0402_1%

EC_RSMRST# <6,10>

1 2

RK16 10K_0402_5%

PCH_PWR_EN <14,56>

H_PECI <6>

+3VALW_EC

DEPOP#_EC<31>

CDR_PRNT#<34,35,37>

M_THERMAL#<18,19>

CTL1<33> CTL2<33>

GPU_PWR_LEVEL<22>

DBC_EN<20>

PTP_DISABLE#<38>

2015/01/06 2016/01/06

ECAGND <51> BATT_TEMP <51,52>

@ESD@

CK12

0.1U_0402_10V7K

@ESD@

CK13

220P_0402_50V8J

@

GPU_ALERT# GPU_OVERT#

EC_ESB_CLK DEPOP#_EC RST# EC_ESB_DAT

M_THERMAL#

DBC_EN

Compal Secret Data

2

221 ohm for white LED 316 ohm for red LED on dock cable side

1

2

1

2

RK15 10K_0402_5%

@

1 2

RK28 10K_0402_5% RK29 10K_0402_5%

UK2

1

ESB_CLK

2

GPIO00

3

RST#

4

ESB_DAT

5

GPIO01

6

GPIO02

7

GPIO03

8

GPIO04

9

GPIO05

10

GPIO06

11

GPIO07/CAS_CLK

12

GND

KC3810_QFN24_4X4

Deciphered Date

2

CDRA_LED WHITE_T

CDRA_LED RED_T

VR_ON_EC VCCST_PG_EC

@ESD@

DK1 L03ESDL5V0CG3-2_SOT-523-3

Place DK1 close to UK1

VR_ON_EC <10>

+3VS

12 12

PWGD_USBOC<34>

TEST_EN#

GPIO08/CAS_DAT

GPIO09 GPIO0A GPIO0B

GPIO0C/PWM0 GPIO0D/PWM1 GPIO0E/PWM2

GPIO0F/PWM3

GPIO10/ESB_RUN#

GPIO11/BaseAddOpt

GND

25

2

G

2

G

3

1

CK16

0.1U_0402_10V7K

2

TP_INT#

13 14 15 16 17 18 19 20 21 22 23 24

VCC

1

+5VALW

12

RK30 100K_0402_5%~D

1

D

QK2

S

ME2N7002E1-G 1N SOT-23-3 ESD 1KV

3

+5VALW

12

RK12 100K_0402_5%~D

1

D

QK4

S

ME2N7002E1-G 1N SOT-23-3 ESD 1KV

3

2

3

1

SYSON <13,54>

+3VS +3VS

2

1 3

D

QK5

2N7002K_SOT23-3

1 2

RC157 100K_0402_5%

PWGD_USBOC PWGD_USBOC_EC

PWGD_USBOC_EC

GPU_ALERT# TS_EN AOAC_WLAN GPU_OVERT# PD_PWR_EN

W=60mils

0.1U_0402_16V4Z CK25

1

2

Title

EC ENE-KB9022/KC3810

Size Document Number Rev

LA-C901P

Date: Sheet

Date: Sheet of

12

RK5 549_0402_1%

S

G

2

QK1 LP2301ALT1G 1P SOT-23-3

D

1 3

CDR_LED_WHITE <34>

+5VALW

12

RK19 100_0402_1%

S

G

2

QK3 LP2301ALT1G 1P SOT-23-3

D

1 3

CDR_LED_RED <34>

TP_CLK TP_DATA

CK14 100P_0402_50V8J

ACIN

@ESD@

PCH_PWROK

SYS_PWROK

1 2

CK19 0.1U_0402_10V7K

@ESD@

1 2

CK20 0.1U_0402_10V7K

Place CK17,CK19,CK20 close to UK1

RK32

1 2

@

1

10K_0402_5%

1 2

2

G

+3VALW

1 2 13

D

S

G

S

@

RK36 0_0402_1%

TP_EN <38>

CALDERA_RST# <34>

PTP_KBBL# <38>

GPU_ALERT# <22> TS_EN <20> AOAC_WLAN <32>

GPU_OVERT# <22>

PD_PWR_EN <11,46>

+3VALW_EC

Compal Electronics, Inc.

+3VS_TOUCH

12

RK104.7K_0402_5%

12

RK114.7K_0402_5%

12

PCH_TP_INT# <6>

RK37 10K_0402_5%

@

QK6 2N7002KW_SOT323-3

@

of

41 63Tuesday, August 04, 2015

1.0

A

B

C

D

E

1 1

RO7

W=10mils

SUSP#<13,41,44>

2 2

SUSP#

1 2

RO8

1 2

82K_0402_5%

470K_0402_5%

12

CO14

0.01U_0603_25V7K

5VS_GATE

3VS_GATE

12

CO15

0.01U_0603_25V7K

+5VS and +3VS switch

+5VALW

UO3

1

VOUT1

VIN1

2

VOUT1

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

+3VALW

CO18

+3VALW

10U_0603_6.3V6M

CO19

1

2

VOUT2

7

VIN2

VOUT2

AOZ1331 DFN 14P DUAL LOAD SW

10U_0603_6.3V6M

CO20

10U_0603_6.3V6M

1

2

CT1

GND

CT2

GPAD

+5VALW

+3VALW TO +3VALW_DSW

1 2

@

J510

5VS

1 2

3VS

220P_0402_50V8J

@

220P_0402_50V8J

@

2

JUMP_43X79

@

J511

2

JUMP_43X79

112

14 13

CO10

12 11

CO13

10 9

8 15

CO21

10U_0603_6.3V6M

1

2

+5VS

CO11

10U_0805_10V4Z

CO12

10U_0603_6.3V6M

1

@

2

+3VS

CO17

10U_0603_6.3V6M

CO16

10U_0603_6.3V6M

1

@

2

DSW_EN<41>

+3VALW+5VALW +3VALW_DSW

RO9 0_0805_5%@

UO4

1

VOUT

VIN

2

VOUT

VIN

3

CT

ON

4

VBIAS

GND GND

TPS22967DSGR_SON8_2X2

For Test, APE8937(SA000070L00) AOZ1336(SA00006U600) TPS22967(SA000070S00)

7 8

6

5 9

1

CO23

@

CT pin use 2200pf for s

CO22

@

2

2200P_0402_25V7K

0.1U_0402_10V6K

oft start tuning

3 3

+0.675VS_VTT

12

RO5 22_0603_5%

13

D

S

2

G

QO1 2N7002K_SOT23-3

SUSP#SUSP

RO6 100K_0402_5%

+5VALW

12

RO3

SUSP

12

100K_0402_5%

13

D

2

QO2

G

2N7002K_SOT23-3

S

For Intel S3 power reduction

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

DC/DC Interface

DC/DC Interface LA-C901P

LA-C901P

E

of

42 63Tuesday, August 04, 2015

1.0

5

4

3

2

1

Screw Hole

H10

H8

D D

1

H_3P0

@

H_3P0

@

1

H13

H12

H_3P0

@

1

H15

H14

H_3P0

H_2P9

@

1

H17

H16

H_3P0

@

1

H19

H18

H_3P0

@

1

H21

H_3P0

@

1

Echo MLK delete H24,H25

H9

1

H_2P7X3P0

@

H28

H_3P0

@

1

Add H28,H29 for USB3.1 type C

H11

H_2P7

@

1

H20

H_3P2

@

1

C C

B B

H26

H22

H23

H27

1

H_3P5

@

H_3P0

@

H_2P7X3P2

@

H_5P0N

@

H1

H_3P8

@

1

H5

H_4P4X3P8

@

1

FD1 FIDUCAL@

1

H2

H_4P4X3P8

@

1

H6

H_4P4X3P8

@

1

FD2 FIDUCIAL@

1

H29

H_3P3

@

1

H3

H7

FD3 FIDUCAL@

1

H_4P4X3P8

@

1

H_3P8

@

1

FD4 FIDUCIAL@

H4

H_4P2

@

1

FIDUCIAL MARK

1

CPU bracket

GPU bracket

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Screw Hole

Screw Hole LA-C901P

LA-C901P

1

43 63Tuesday, August 04, 2015

1.0

UT1

5

4

3

2

1

S IC DSL6340 SLKYB B0 FC-CSP I/O CONTROL

SA000090N0L

ARES2R1@

UT1

S IC A31 DSL6340 QSCX B0 THUNDERBOLT

D D

SA000090N2L

ARQSR1@

UT1

S IC DSL6340 SLL42 B1 FCCSP 337P THUNDERBOLT A31 !

SA000090N5L

ARQSR3@

Reserve for common DP design

CPU_DP1_AUXN_C CPU_DP2_AUXN_C CPU_DP1_AUXP_C CPU_DP2_AUXP_C CLKREQ_PCIE#4

+3.3V_LC +3.3V_LC

C C

10K_0201_5%

12

RT6

RT7

TBT@

TBTA_LSTX CLKREQ_PCIE#4_R

SOC_DP2_CTRL_CLK SOC_DP2_CTRL_DATA SOC_DP1_CTRL_CLK SOC_DP1_CTRL_DATA

B B

SOC_DP1_HPD SOC_DP2_HPD TBTA_LSTX TBTA_HPD TBTA_LSRX

A A

RT76 100K_0201_5%@ RT77 100K_0201_5%@ RT78 100K_0201_5%@ RT79 100K_0201_5%@ RT24 10K_0201_5%TBT@

10K_0201_5%

12

RT8

TBT@

1 2 1 2 1 2 1 2 1 2

10K_0201_5%

12

RT9

TBT@

10K_0201_5%

12

TBT_TDI TBT_TMS TBT_TCK TBT_TDO

RT21 10K_0201_5%@ RT20 10K_0201_5%TBT@

1 8 2 7 3 6 4 5

1 2

RT38 100K_0201_5%TBT@

1 2

RT39 100K_0201_5%TBT@

1 2

RT40 1M_0201_1%TBT@

1 2

RT41 100K_0201_5%TBT@

1 2

RT42 1M_0201_1%TBT@

+3VS_TBT

JTAG1

1

2

3

4

5

6

7

GND

8

GND

ACES_50228-0067N-001

CONN@

12 12

RPT1

2.2K_0804_8P4R_5%TBT@

PCIE X2 Bus

(Link to CPU Port 9~10)

PCIE CLK

(From PCH CLKOUT4)

C

PU DDI1

CPU DDI2

+3VS_TBT

PCIE_CTX_DRX_P10<12> PCIE_CTX_DRX_N10<12>

PCIE_CTX_DRX_P9<12> PCIE_CTX_DRX_N9<12>

CLK_PCIE_P4<10> CLK_PCIE_N4<10>

CLKREQ_PCIE#4<10>

SOC_DP1_P0<6> SOC_DP1_N0<6>

SOC_DP1_P1<6> SOC_DP1_N1<6>

SOC_DP1_P2<6> SOC_DP1_N2<6>

SOC_DP1_P3<6> SOC_DP1_N3<6>

SOC_DP1_AUXP<6>

SOC_DP1_AUXN<6>

SOC_DP1_HPD<6>

SOC_DP1_CTRL_CLK<6> SOC_DP1_CTRL_DATA<6>

SOC_DP2_P0<6> SOC_DP2_N0<6>

SOC_DP2_P1<6> SOC_DP2_N1<6>

SOC_DP2_P2<6> SOC_DP2_N2<6>

SOC_DP2_P3<6> SOC_DP2_N3<6>

SOC_DP2_AUXP<6>

SOC_DP2_AUXN<6>

SOC_DP2_HPD<6>

SOC_DP2_CTRL_CLK<6> SOC_DP2_CTRL_DATA<6>

USB3_A_TRX_DTX_P1<47> USB3_A_TRX_DTX_N1<47>

USB3_A_TTX_C_DRX_P1<47> USB3_A_TTX_C_DRX_N1<47>

USB3_A_TTX_C_DRX_P0<47> USB3_A_TTX_C_DRX_N0<47>

USB3_A_TRX_DTX_P0<47> USB3_A_TRX_DTX_N0<47>

TBT_A_AUX_P_C<46> TBT_A_AUX_N_C<46>

TBT_A_USB20_P<46> TBT_A_USB20_N<46>

TBTA_LSTX<46> TBTA_LSRX<46>

TBTA_HPD<46>

CLKREQ_PCIE#4

CT6 0.1U_0201_6.3V6KTBT@ CT7 0.1U_0201_6.3V6KTBT@

CT8 0.1U_0201_6.3V6KTBT@ CT9 0.1U_0201_6.3V6KTBT@

CT10 0.1U_0201_6.3V6KTBT @ CT23 0.1U_0201_6.3V6KTBT @

CT11 0.1U_0201_6.3V6KTBT @ CT24 0.1U_0201_6.3V6KTBT @

CT25 0.1U_0201_6.3V6KTBT @ CT26 0.1U_0201_6.3V6KTBT @

CT27 0.1U_0201_6.3V6KTBT @ CT28 0.1U_0201_6.3V6KTBT @

CT29 0.1U_0201_6.3V6KTBT @ CT30 0.1U_0201_6.3V6KTBT @

CT31 0.1U_0201_6.3V6KTBT@ CT32 0.1U_0201_6.3V6KTBT @

CT33 0.1U_0201_6.3V6KTBT @ CT34 0.1U_0201_6.3V6KTBT @

CT35 0.1U_0201_6.3V6KTBT @ CT36 0.1U_0201_6.3V6KTBT @

CT39 0.22U_0201_6.3V6MTBT@ CT40 0.22U_0201_6.3V6MTBT@

CT41 0.22U_0201_6.3V6MTBT@ CT42 0.22U_0201_6.3V6MTBT@

CT43 0.1U_0201_6.3V6KTBT @ CT44 0.1U_0201_6.3V6KTBT @

12 12

12

@

RT2 0_0201_5%

1 2 1 2

12

TBT@

RT19 14K_0402_1%

12

TBT@

RT25 4.75K_0402_0.5%

12 12

12

TBT@

RT43 499_0201_1%

PCIE_CTX_C_DRX_P10

CT30.22U_0201_6.3V6M TBT@

PCIE_CTX_C_DRX_N10

CT150.22U_0201_6.3V6M TBT@

PCIE_CTX_C_DRX_P9

CT10.22U_0201_6.3V6M TBT@

PCIE_CTX_C_DRX_N9 PCIE_CRX_C_DTX_N9

CT130.22U_0201_6.3V6M TBT@

CLKREQ_PCIE#4_R

CPU_DP1_P0_C CPU_DP1_N0_C

CPU_DP1_P1_C CPU_DP1_N1_C

CPU_DP1_P2_C CPU_DP1_N2_C

CPU_DP1_P3_C CPU_DP1_N3_C

CPU_DP1_AUXP_C CPU_DP1_AUXN_C

SOC_DP1_CTRL_CLK SOC_DP1_CTRL_DATA

CPU_DP2_P0_C CPU_DP2_N0_C

CPU_DP2_P1_C CPU_DP2_N1_C

CPU_DP2_P2_C CPU_DP2_N2_C

CPU_DP2_P3_C CPU_DP2_N3_C

CPU_DP2_AUXP_C CPU_DP2_AUXN_C

SOC_DP2_CTRL_CLK SOC_DP2_CTRL_DATA

DPSNK_RBIAS TBT_TDI

TBT_TMS TBT_TCK TBT_TDO

TBT_RBIAS TBT_RSENSE

USB3_A_TTX_DRX_P1 USB3_A_TTX_DRX_N1

USB3_A_TTX_DRX_P0 USB3_A_TTX_DRX_N0

TBT_A_AUX_P TBT_A_AUX_N

TBT_A_USB20_P TBT_A_USB20_N

TBTA_LSTX TBTA_LSRX TBTA_HPD

PA_USB2_RBIAS PB_USB2_RBIAS

UT1A

Y23

PCIE_RX0_P

Y22

PCIE_RX0_N

T23

PCIE_RX1_P

T22

PCIE_RX1_N

M23

PCIE_RX2_P

M22

PCIE_RX2_N

H23

PCIE_RX3_P

H22

PCIE_RX3_N

V19

PCIE_REFCLK_100_IN_P

T19

PCIE_REFCLK_100_IN_N

AC5

PCIE_CLKREQ_N

AB7

DPSNK0_ML0_P

AC7

DPSNK0_ML0_N

AB9

DPSNK0_ML1_P

AC9

DPSNK0_ML1_N

AB11

DPSNK0_ML2_P

AC11

DPSNK0_ML2_N

AB13

DPSNK0_ML3_P

AC13

DPSNK0_ML3_N

Y11

DPSNK0_AUX_P

W11

DPSNK0_AUX_N

AA2

DPSNK0_HPD

Y5

DPSNK0_DDC_CLK

R4

DPSNK0_DDC_DATA

AB15

DPSNK1_ML0_P

AC15

DPSNK1_ML0_N

AB17

DPSNK1_ML1_P

AC17

DPSNK1_ML1_N

AB19

DPSNK1_ML2_P

AC19

DPSNK1_ML2_N

AB21

DPSNK1_ML3_P

AC21

DPSNK1_ML3_N

Y12

DPSNK1_AUX_P

W12

DPSNK1_AUX_N

Y6

DPSNK1_HPD

Y8

DPSNK1_DDC_CLK

N4

DPSNK1_DDC_DATA

Y18

DPSNK_RBIAS

Y4

TDI

V4

TMS

T4

TCK

W4

TDO

H6

RBIAS

J6

RSENSE

A15

PA_RX1_P

B15

PA_RX1_N

A17

PA_TX1_P

B17

PA_TX1_N

A19

PA_TX0_P

B19

PA_TX0_N

B21

PA_RX0_P

A21

PA_RX0_N

Y15

PA_DPSRC_AUX_P

W15

PA_DPSRC_AUX_N

E20

PA_USB2_D_P

D20

PA_USB2_D_N

A5

PA_LS_G1

A4

PA_LS_G2

M4

PA_LS_G3

H19

PA_USB2_RBIAS

AC23

THERMDA

AB23

THERMDA

V18

PCIE_ATEST

AC1

TEST_EDM

L15

FUSE_VQPS_64

N15

FUSE_VQPS_128

C23

MONDC_CIO_0

C22

MONDC_CIO_1

Port A

POC

PCIe GEN3

SINK PORT 0

SOURCE PORT 0

LC GPIOPOC GPIO

SINK PORT 1

Misc

MISC

PORT B

TBT PORTS

DEBUG

PCIE_TX0_P PCIE_TX0_N

PCIE_TX1_P PCIE_TX1_N

PCIE_TX2_P PCIE_TX2_N

PCIE_TX3_P PCIE_TX3_N

PCIE_RBIAS

DPSRC_ML0_P DPSRC_ML0_N

DPSRC_ML1_P DPSRC_ML1_N

DPSRC_ML2_P DPSRC_ML2_N

DPSRC_ML3_P DPSRC_ML3_N

DPSRC_AUX_P DPSRC_AUX_N

DPSRC_HPD

DPSRC_RBIAS

POC_GPIO_0 POC_GPIO_1 POC_GPIO_2 POC_GPIO_3 POC_GPIO_4 POC_GPIO_5 POC_GPIO_6

TEST_PWR_GOOD

XTAL_25_IN

XTAL_25_OUT

PB_RX1_P PB_RX1_N

PB_TX1_P PB_TX1_N

PB_TX0_P PB_TX0_N

PB_RX0_P PB_RX0_N

PB_DPSRC_AUX_P PB_DPSRC_AUX_N

PB_USB2_D_P PB_USB2_D_N

PB_LS_G1 PB_LS_G2

POC

PB_LS_G3

PB_USB2_RBIAS

MONDC_SVR

USB2_ATEST MONDC_DPSNK_0 MONDC_DPSNK_1

MONDC_DPSRC

ALPINE-RIDGE_BGA337@

PERST_N

GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8

TEST_EN

RESET_N

EE_DI

EE_DO

EE_CS_N

EE_CLK

ATEST_P ATEST_N

V23

PCIE_CRX_C_DTX_P10

V22

PCIE_CRX_C_DTX_N10

P23

PCIE_CRX_C_DTX_P9

P22 K23

K22 F23

F22 L4

TBT_RST#_R

N16

PCIE_RBIAS

R2 R1

N2 N1

L2 L1

J2 J1

W19 Y19

G1

TBT_SRC_HPD

N6

DPSRC_RBIAS

U1 U2 V1

TBT_EE_WP_N

V2

TBT_TMU_CLK_OUT

W1

TBT_PCIE_WAKE_N

W2

TBT_CIO_PLUG_EVENT #

Y1

TBT_HDMI_DDC_DATA

Y2

TBT_HDMI_DDC_CLK

AA1

TBT_SRC_CFG1

J4

TBTA_I2C_INT

E2

TBTB_I2C_INT

D4

RTD3_USB_PW R_EN_R

H4

TBT_FORCE_PW R_R

F2

BATLOW#

D2

SUSP#_R

F1

RTD3_CIO_PWR_EN_R

E1

TBT_TEST_EN

AB5

TBT_TEST_PWG

F4

TBT_RESET_N

D22

TBT_XTAL_25_IN

D23

TBT_XTAL_25_OUT

AB3

TBT_EE_DI

AC4

TBT_EE_DO

AC3

TBT_EE_CS_N

AB4

TBT_EE_CLK

B7 A7

A9 B9

A11 B11

A13 B13

Y16 W16

E19 D19

B4

NC_B4

B5

NC_B5

G2

NC_G2

F19 D6 A23

B23 E18 W13 W18 AB2

RT1 0_0201_5%MP@ RT3 3.01K_0201_1%TBT @

12

1 2

RT4 1M_0201_1%T BT@

1 2

RT5 14K_0402_1%TBT@

1 2

RT10 0_0201_5%MP@

1 2

RT11 1M_0201_1%TBT@

1 2

RT12 0_0201_5%@

1 2

RT13 0_0201_5%MP@

1 2

RT14 0_0201_5%@

1 2

RT15 0_0201_5%MP@

1 2

RT16 0_0201_5%@

1 2

RT17 100_0201_5%TBT @

1 2

RT18 100_0201_5%TBT @

1 2

RT23 0_0201_5%

1 2

TBT@

RT44 499_0201_1%

RT105 0_0402_5%

1 2

RT50 3.3K_0402_5%TBT@

1 2

RT51 3.3K_0402_5%TBT@

1 2

RT48 3.3K_0402_5%TBT@

12

CT140.22U_0201_6.3V6M TBT@

12

CT160.22U_0201_6.3V6M TBT@

12

CT120.22U_0201_6.3V6M TBT@

12

CT20.22U_0201_6.3V6M TBT@

Closed to UT1

TBT_I2C_SDA <46> TBT_I2C_SCL <46>

T1@

TBT_CIO_PLUG_EVENT # <11>

T2@ T3@

TBTA_I2C_INT <46>

TBT_EE_DI TBT_EE_CLK TBT_EE_CS_N TBT_HOLD_N TBT_EE_WP_N

PCIE_CRX_DTX_P10 <12> PCIE_CRX_DTX_N10 <12>

PCIE_CRX_DTX_P9 <12> PCIE_CRX_DTX_N9 <12>

PLT_RST# <10,30,32,36,41>

TBT_I2C_SDA TBT_I2C_SCL TBT_PCIE_WAKE_N TBT_CIO_PLUG_EVENT # SUSP#_R BATLOW# TBTA_I2C_INT TBTB_I2C_INT TBT_RESET_N NC_B4 TBT_FORCE_PW R_R

TBT_PCIE_WAKE# <41>

RTD3_USB_PW R_EN <11> TBT_FORCE_PW R <12> PM_BATLOW# <10> SUSP# <13,41,42> RTD3_CIO_PWR_EN <11>

TBT_RESET_N <46> TBT_RESET_N_EC <41>

CT37

12P_0402_50V8J

TBT@

TBT_TMU_CLK_OUT TBT_FORCE_PW R_R RTD3_CIO_PWR_EN_R RTD3_USB_PW R_EN_R

NC_B4 NC_B5 NC_G2

TBT_EE_DI

RT98 0_0201_5%@

TBT_EE_DO

RT99 0_0201_5%@

TBT_EE_CS_N

RT100 0_0201_5%@

TBT_EE_CLK

RT101 0_0201_5%@

UT2

5

DI

6

CLK

1

CS

7

HOLD

3

WP

8

VCC

W25Q80DVSSIG_SO8

TBT@

2

SO

4

VSS

RT26 3.3K_0201_5%TBT@ RT27 3.3K_0201_5%TBT@ RT28 10K_0201_5%TBT@ RT29 10K_0201_5%TBT@ RT30 10K_0201_5%@ RT31 10K_0201_5%TBT@ RT32 10K_0201_5%TBT@ RT33 10K_0201_5%TBT@ RT80 10K_0201_5%TBT@ RT86 10K_0201_5%@ RT94 10K_0201_5%@

KB9022 To CPU pin AD4

From CPU pin AP7 From CPU pin J2 From CPU pin BD16 From EC pin 116 From CPU pin AN8

YT1 25MHZ_12PF_7V25000012

1

2

RT34 100K_0201_5%TBT@ RT35 100K_0201_5%TBT@ RT36 100K_0201_5%TBT@ RT37 100K_0201_5%TBT@

RT45 100K_0201_5%TBT@ RT46 100K_0201_5%TBT@ RT47 100K_0201_5%TBT@

Close to UT2

1 2 1 2 1 2 1 2

TBT_EE_DO

12 12 12 12 12 12 12 12 12 12 12

GND

TBT@

2

1 2 1 2 1 2 1 2

1 2 1 2 1 2

1 2

GND

4

3

+3.3V_LC+3.3V_FLASH

RT493.3K_0402_5% TBT@

+3.3V_TBT_SX

1

CT38 12P_0402_50V8J

2

TBT@

PD_EE_DI <46> PD_EE_DO <46> PD_EE_CS_N <46> PD_EE_CLK <46>

RT106 0_0402_5%

@

1 2

1

CT45

0.1U_0402_10V7K

2

TBT@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Thunderbolt (1/2)

LA-C901P

1

1.0

of

44 63Tuesday, August 04, 2015

of

44 63Tuesday, August 04, 2015

of

44 63Tuesday, August 04, 2015

5

4

3

2

1

VSS_ANA

ALPINE-RIDGE_BGA337@

1U_0201_6.3V6M

1

CT49

2

SVR_IND SVR_IND SVR_IND

SVR_VSS SVR_VSS SVR_VSS

VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

TBT@

1

2

A2 A3 B3

L9 M9 E12 E13 F11 F12 F13 F15 J9

C1 C2 D1

A1 B1 B2

F18 H18 J11 H11

V5 V6 V8 V9 V15 V16 V20 W5 W6 W8 W9 W20 W22 W23 Y9 Y13 Y20 AA22 AA23 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC6 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 D5 E4 E5 E6 F5 F6 H5 H8 J8 J12 J13 J15 L13 M11 M12 N8 N9 N11 N12 N13 T6 T8 T9 T13 T15 T16 T18 AB1 AC2

+3VS_TBT+3.3V_TBT_SX+3.3V_LC

1U_0201_6.3V6M

CT50

TBT@

CT63

TBT_SVR_IND

+0.9V_LVR_OUT

10U_0402_6.3V6M

1

CT51

TBT@

2

1U_0201_6.3V6M

1

TBT@

2

0.6UH_MND-04ABIR60M-XGL_20%

1

2

1

CT64

TBT@

2

LT1

TBT@

1 2

1

CT81

TBT@

2

CT52

TBT@

1U_0201_6.3V6M

10U_0402_6.3V6M

1

2

CT65

TBT@

CT82

TBT@

10U_0402_6.3V6M

CT53

TBT@

+0.9V_SVR

1U_0201_6.3V6M

1

2

CT73

TBT@

10U_0402_6.3V6M

1

2

CT66

CT83

TBT@

10U_0402_6.3V6M

1

2

1U_0201_6.3V6M

1

CT67

CT68

TBT@

2

47U_0603_6.3V6M

1

CT75

CT74

TBT@

2

1U_0201_6.3V6M

1

CT84

TBT@

2

1U_0201_6.3V6M

1

CT69

TBT@

2

47U_0603_6.3V6M

1

2

+3VS_TBT+3VS+3.3V_TBT_SX+3VALW +3VALW+3.3V_TBT_SX +3VS_TBT

1 2

@

RT104 0_0402_5%

1 2

RT97 0_0402_5%

Reserve RT104 follow E-team's design dat.04/07

D D

1U_0201_6.3V6M

1

2

+0.9V_USB

1U_0201_6.3V6M

CT56

TBT@

CT57

TBT@

1

2

1U_0201_6.3V6M

1

2

CT78

CT54

TBT@

CT77

TBT@

C C

B B

A A

1U_0201_6.3V6M

TBT@

CT58

TBT@

+0.9V_DP

1U_0201_6.3V6M

1

CT59

TBT@

2

1

CT55

TBT@

2

+0.9V_CIO

1U_0201_6.3V6M

1

CT79

CT80

TBT@

2

1U_0201_6.3V6M

TBT@

CT60

TBT@

CT70

TBT@

1U_0201_6.3V6M

1

2

CT85

1 2

@

RT52 0_0805_5%

1 2

RT95 0_0805_5%

1U_0201_6.3V6M

1

CT62

CT61

TBT@

2

+0.9V_PCIE

1U_0201_6.3V6M

1

CT72

CT71

TBT@

2

+3.3V_ANA_PCIE +3.3V_ANA_USB2

1U_0201_6.3V6M

1

CT86

TBT@

2

TBT@

1U_0201_6.3V6M

0.1U_0201_6.3V6K

1U_0201_6.3V6M

1

CT46

TBT@

UT1B

L8

1U_0201_6.3V6M

VCC0P9_DP

L11

VCC0P9_DP

L12

1

2

1

2

1U_0201_6.3V6M

VCC0P9_DP

M8

VCC0P9_DP

T11

VCC0P9_DP

T12

VCC0P9_DP

L6

VCC0P9_ANA_DPSRC

M6

VCC0P9_ANA_DPSRC

V11

VCC0P9_ANA_DPSNK

V12

VCC0P9_ANA_DPSNK

V13

VCC0P9_ANA_DPSNK

M13

VCC0P9_PCIE

M15

VCC0P9_PCIE

M16

VCC0P9_PCIE

L19

VCC0P9_ANA_PCIE_1

N19

VCC0P9_ANA_PCIE_1

L18

VCC0P9_ANA_PCIE_2

M18

VCC0P9_ANA_PCIE_2

N18

VCC0P9_ANA_PCIE_2

R15

VCC0P9_USB

R16

VCC0P9_USB

R8

VCC0P9_CIO

R9

VCC0P9_CIO

R11

VCC0P9_CIO

R12

VCC0P9_CIO

L16

VCC3P3_ANA_PCIE

J16

VCC3P3_ANA_USB2

A6

VSS_ANA

A8

VSS_ANA

A10

VSS_ANA

A12

VSS_ANA

A14

VSS_ANA

A16

VSS_ANA

A18

VSS_ANA

A20

VSS_ANA

A22

VSS_ANA

B6

VSS_ANA

B8

VSS_ANA

B10

VSS_ANA

B12

VSS_ANA

B14

VSS_ANA

B16

VSS_ANA

B18

VSS_ANA

B20

VSS_ANA

B22

VSS_ANA

D8

VSS_ANA

D9

VSS_ANA

D11

VSS_ANA

D12

VSS_ANA

D13

VSS_ANA

D15

VSS_ANA

D16

VSS_ANA

D18

VSS_ANA

E8

VSS_ANA

E9

VSS_ANA

E11

VSS_ANA

E15

VSS_ANA

E16

VSS_ANA

E22

VSS_ANA

E23

VSS_ANA

F9

VSS_ANA

F16

VSS_ANA

F20

VSS_ANA

G22

VSS_ANA

G23

VSS_ANA

H1

VSS_ANA

H2

VSS_ANA

H12

VSS_ANA

H13

VSS_ANA

H15

VSS_ANA

H16

VSS_ANA

H20

VSS_ANA

J5

VSS_ANA

J18

VSS_ANA

J19

VSS_ANA

J20

VSS_ANA

J22

VSS_ANA

J23

VSS_ANA

K1

VSS_ANA

K2

VSS_ANA

L5

VSS_ANA

L20

VSS_ANA

L22

VSS_ANA

L23

VSS_ANA

M1

VSS_ANA

M2

VSS_ANA

M5

VSS_ANA

M19

VSS_ANA

M20

VSS_ANA

N5

VSS_ANA

N20

VSS_ANA

N22

VSS_ANA

N23

VSS_ANA

1

CT47

TBT@

2

R6

VCC3P3_LC

VSS_ANAP1VSS_ANAP2VSS_ANAR5VSS_ANA

R18

F8

VCC3P3_SX

VSS_ANA

R19

R20

R22

CT48

R13

H9

VCC3P3_S0

VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA

VCC0P9_SVR_SENSE

VCC0P9_LVR_SENSE

GND VCC

VSS_ANA

VSS_ANAT1VSS_ANAT2VSS_ANAT5VSS_ANA

T20

R23

TBT@

VCC3P3_SVR VCC3P3_SVR VCC3P3_SVR

VCC3P3A

VCC0P9_SVR VCC0P9_SVR

VCC0P9_LVR VCC0P9_LVR VCC0P9_LVR

VSS_ANA

U23

U22

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Thunderbolt (2/2)

LA-C901P

1

1.0

of

45 63Tuesday, August 04, 2015

of

45 63Tuesday, August 04, 2015

of

45 63Tuesday, August 04, 2015

5

+3VALW

@

12

CT87 1U_0402_6.3V6K

PD_PWR_EN<11,41>

D D

C C

+3.3V_FLASH +3.3V_FLASH

UT6

PD_EE_DI

1 2

RT92 3.3K_0402_5%PD@

1 2

RT87 3.3K_0402_5%PD@

1 2

RT91 3.3K_0402_5%PD@

B B

A A

PD_EE_CLK PD_EE_CS_N PD_HOLD_N PD_EE_WP_N

5

DI

6

CLK

1

CS

7

HOLD

3

WP

8

VCC

VSS

W25Q80DVSSIG_SO8

PD@

SO

RT55

100K_0402_5%

EC_SMB_DA2<8,22,40,41> EC_SMB_CK2<8,22,40,41>

2

4

12

@

PD_EE_DO

+5VALW

1U_0402_6.3V6K

10K_0402_5%

1 2

PD_IRQ#

RT59 0_0402_5%MP@ RT60 0_0402_5%MP@

CT89

RT107

TBT_A_AUX_N_C<44>

@

TBT_A_AUX_P_C<44>

1

2

Follow TD team

12

1 2 1 2

RT933.3K_0402_5% PD@

100K_0402_5%

4

UT3

1

VIN

2

VIN

3

ON

4

VBIAS

AOZ1336_DFN8_2X2

@

RT57

10K_0402_5%

1

CT105

0.1U_0402_10V7K

2

PD@

+3.3V_TBT_SX

RT70

@

100K_0402_5%

CT90

1

CT101 1U_0402_6.3V6K

2

PD@

UT4

F1

I2C_ADDR

D1

I2C_SDA1

D2

I2C_SCL1

C1

I2C_IRQ1_N

A5

I2C_SDA2

B5

I2C_SCL2

B6

I2C_IRQ2_N

B2

GPIO0

C2

GPIO1

D10

GPIO2

G11

GPIO3

C10

GPIO4

E10

GPIO5

G10

GPIO6

D7

GPIO7

H6

GPIO8

A3

SPI_CLK

B4

SPI_MOSI

A4

SPI_MISO

B3

SPI_SS_N

L5

USB_RP_P

K5

USB_RP_N

E2

UART_TX

F2

UART_RX

F4

SWD_DATA

G4

SWD_CLK

E11

MRESET

L4

TBT_LSTX/R2P

K4

TBT_LSRX/P2R

L3

DIG_AUD_P/DEBUG3

K3

DIG_AUD_N/DEBUG4

L2

DEBUG1

K2

DEBUG2

J1

AUX_P

J2

AUX_N

F10

BUSPOWER_N

G2

R_OSC

3

Remove RT56 for layout routing dat.05/06

+5VALW +5VALW_PD

+5VALW_PD +TBTA_VBUS

22U_0603_6.3V6M

1

CT91

2

TBTA_LDO_BMC +1.8VD_TBTA_LDO +1.8VA_TBTA_LDO

1

CT100

4.7U_0603_10V6K

2

PD@

+3.3V_FLASH

H1

1

CT92

2

K1

B1

VDDIO

VIN_3V3

GND

A1

D6

1

CT93

2

0.6A

H10

A2

E1

LDO_BMC

LDO_1V8A

PP_CABLE

LDO_1V8D

GND

GNDE5GND

GNDH4GND

F5

E7

B8

E6

H5

G5

60mil 3A60mil 3A

RT22

0_0201_5%

@

1 2

A11

B11

C11

D11

PP_5V0

GND

GNDF6GNDF7GND

GND

F8

E8

D8

G6

PP_HVA6PP_HVA7PP_HVA8PP_HV

GND

GNDG7GND

GNDH7GNDL1GND

H8

G8

1

CT104

0.22U_0402_10V4Z

2

PD@

B10

B7

A10

SENSEP

L11

MP@

0_0402_5%

@

1 2

TBT_I2C_SDA<44> TBT_I2C_SCL<44>

TBTA_I2C_INT<44>

TBTA_I2C_SDA1_R TBTA_I2C_SCL1_R

TBTA_HPD<44>

12

TI's Request

12

12 12

1 2

@

+3VALW_PD

RT103

@

1

CT99

4.7U_0603_10V6K

2

PD@

PD_IRQ#

T64 TP@ T65 TP@ T66 TP@ T67 TP@

T68 TP@ T69 TP@ T70 TP@ T71 TP@

PD_EE_CLK PD_EE_DI PD_EE_DO PD_EE_CS_N

TBT_A_USB20_P TBT_A_USB20_N

PD_UART

T62 TP@ T63 TP@

TBTA_MRESET

TBTA_LSTX TBTA_LSRX

TBTA_DIG_AUD_P TBTA_DIG_AUD_N

TBTA_DEBUG1 TBTA_DEBUG2

TBT_A_AUX_P_C TBT_A_AUX_N_C

BUSPOWER#

TBTA_ROSC

12

RT75 15K_0402_1%

PD@

12

1

CT88

0.1U_0402_10V6K

PD@

2

+3VS_TBT

+3VALW_PD

+3VALW

1 2

RT53 0_0402_5%

7

VOUT

8

VOUT

6

CT

5

GND

9

GND

+3VS

12

@

12

RT73

@

+3VS_PD_R

RT58 10K_0402_5%

@

TBT_A_USB20_P<44> TBT_A_USB20_N<44>

RT62 100K_0402_5%PD@

RT63 100K_0402_5%PD@

RT68 100K_0402_5%PD@ RT69 100K_0402_5%PD@

RT71 100K_0402_5%PD@ RT72 100K_0402_5%PD@

+3.3V_FLASH

1 2

RT54 0_0402_5%

1

CT107

4.7U_0402_6.3V6M

@

2

12

CT98

2.2U_0603_16V6K

PD@

Master0:0 ohm Slave1:93.1K ohm

RT83 0_0402_5%

PD_IRQ#<41>

TI's Request

PD_EE_CLK<44> PD_EE_DI<44> PD_EE_DO<44> PD_EE_CS_N<44>

TBTA_LSTX<44>

TBTA_LSRX<44>

RT74 0_0402_1%

60mil 3A60mil 3A

12

CT106 1U_0603_25V6K

Close to UT4

A9

SENSEN

HV_GATE1B9HV_GATE2

VBUS VBUS VBUS VBUS

VOUT_3V3

LDO_3V3

C_USB_TP

C_USB_TN

C_USB_BP C_USB_BN

C_CC1 C_CC2

RPD_G1 RPD_G2

DEBUG_CTL1 DEBUG_CTL2

C_SBU1 C_SBU2

RESET_N

TPS65982_BGA96PD@

2

H11 J10 J11 K11

H2

G1

K6 L6

K7 L7

L9 L10

K9 K10

E4 D5

K8 L8

F11

Change DT1 and add DT15 follow E-team's design for DELL dat.04/07

2

3

1

+3.3V_FLASH

1

CT103 10U_0603_10V6M

2

PD@

TI's Requirement

Differential Signal

DT15 AZ4024-02S_SOT23-3~D

ESD@

TBTA_CC1 <47> TBTA_CC2 <47>

TBT_RESET_N <44>

RT96

1 2

@

0_0402_1%

TBT_A_USB20_PT TBT_A_USB20_NT

TBT_A_USB20_PB TBT_A_USB20_NB

TBTA_CC1 TBTA_CC2

RPD_G1 RPD_G2

DEBUG_CTL1 DEBUG_CTL2

TBTA_SBU1 TBTA_SBU2

DT1 SDM10U45-7_SOD523-2~D

ESD@

2 1

RT61

1 2

0_0402_5%

@

1

CT102 1U_0402_6.3V6K

2

PD@

TBT_A_USB20_PT <47> TBT_A_USB20_NT <47>

TBT_A_USB20_PB <47> TBT_A_USB20_NB <47>

1 2

RT64 10K_0402_5%PD@

1 2

RT65 10K_0402_5%PD@

TBTA_SBU1 <47>

TBTA_SBU2 <47>

1 2

RT102 0_0402_5%

TBT_RESET_NRESET_N

@

+3.3V_TBT_SX+3.3V_TBT_SX_R

RT66

10K_0402_5%

1

PD@

+3.3V_FLASH

12

RT67 10K_0402_5%

PD@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PD

LA-C901P

1

1.0

of

46 63Tuesday, August 04, 2015

of

46 63Tuesday, August 04, 2015

of

46 63Tuesday, August 04, 2015

5

4

3

2

1

USB3_A_TTX_C_DRX_P0

D D

+TBTA_VBUS +TBTA_VBUS

JUSBCx

A1

GND

USB3_A_TTX_C_DRX_P0<44> USB3_A_TTX_C_DRX_N0<44>

USB3_A_TRX_DTX_N1<44>

USB3_A_TRX_DTX_P1<44>

C C

TBT_A_USB20_PT<46>

TBT_A_USB20_NT<46> TBT_A_USB20_PB<46>

1 2

CT94 0.47U_040 2_25V6KTBT@

TBT_A_USB20_L_PT TBT_A_USB20_L_NT

CT95 0.47U_040 2_25V6KTBT@

1 2

TBTA_SBU1

MCM1012B900F06BP_4P

1 2

LT2

EMI@

TBTA_SBU1<46> TBTA_CC2 <46>

TBT_A_USB20_PT TBT_A_USB20_L_PT

TBT_A_USB20_NT

A2

SSTXP1

A3

SSTXN1

A4

VBUS

A5

CC1

A6

DP1

A7

DN1

A8

RFU1

A9

VBUS SSRXN2

SSRXP2 GND

GND GND

GND

TOP

JAE_DX07S024JJ2CONN'@

A10 A11

A12

1 2

5

5/6 New Connector

34

TBT_A_USB20_L_NT

GND

SSRXP1 SSRXN1

VBUS RFU2

DN2 DP2

CC2

VBUS

SSTXN2

Bottom

SSTXP2

GND

GND GND GND

TBT_A_USB20_NB<46>

B12 B11

B10 B9 B8 B7

B6 B5 B4 B3

B2 B1

4 6 3

TBTA_SBU2TBTA_CC1 TBT_A_USB20_L_NB

TBT_A_USB20_L_PB TBTA_CC2

TBT_A_USB20_NB

TBT_A_USB20_PB

1 2

CT96 0.47U_0402_25V 6KTBT@

1 2

CT97 0.47U_0402_25V 6KTBT@

USB3_A_TRX_DTX_P0 <44> USB3_A_TRX_DTX_N0 <44>

TBTA_SBU2 <46>TBTA_CC1<46>

USB3_A_TTX_C_DRX_N1 <44> USB3_A_TTX_C_DRX_P1 <44>

MCM1012B900F06BP_4P

1 2

LT3

34

EMI@

TBT_A_USB20_L_NB

TBT_A_USB20_L_PB

USB3_A_TTX_C_DRX_N0

USB3_A_TRX_DTX_P0

USB3_A_TRX_DTX_N0

USB3_A_TTX_C_DRX_P1

USB3_A_TTX_C_DRX_N1

USB3_A_TRX_DTX_P1

USB3_A_TRX_DTX_N1

TBTA_CC1

TBTA_CC2

TBTA_SBU1

TBTA_SBU2

TBT_A_USB20_L_PT TBT_A_USB20_L_NT TBT_A_USB20_L_NB TBT_A_USB20_L_PB

DT2

ESD@

ESD8011MUT5G X3DFN2 ESD DT3

ESD@

ESD8011MUT5G X3DFN2 ESD DT4

ESD@

ESD8011MUT5G X3DFN2 ESD DT5

ESD@

ESD8011MUT5G X3DFN2 ESD DT6

ESD@

ESD8011MUT5G X3DFN2 ESD DT7

ESD@

ESD8011MUT5G X3DFN2 ESD DT8

ESD@

ESD8011MUT5G X3DFN2 ESD DT9

ESD@

ESD8011MUT5G X3DFN2 ESD DT11

ESD@

ESD8011MUT5G X3DFN2 ESD DT12

ESD@

ESD8011MUT5G X3DFN2 ESD DT13

ESD@

ESD8011MUT5G X3DFN2 ESD DT14

ESD@

ESD8011MUT5G X3DFN2 ESD

DT10

1 2 4 5

3

TVWDF1004AD0_DFN9ESD@

1 2

9

TBT_A_USB20_L_PT

8

TBT_A_USB20_L_NT

7

TBT_A_USB20_L_NB

6

TBT_A_USB20_L_PB

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS S HEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS S HEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS S HEET MAY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDIS CLOSED TO ANY THIRD PARTY WITHOUT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY ORDIS CLOSED TO ANY THIRD PARTY WITHOUT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY ORDIS CLOSED TO ANY THIRD PARTY WITHOUT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Thunderbolt+USB3.1 TypeC

Size Document Number Rev

LA-C901P

Date: Sheet

Date: Sheet of

1

of

47 63Tuesday, August 04, 2015

1.0

5

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )

Request

Page# Title

Item

Item Issue Description

Page#Page#

ItemItem

1

D D

C C

B B

A A

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

Title

TitleTitle

5

Date

DateDate

RequestRequest Owner

Owner

OwnerOwner

4

Issue DescriptionDate

Issue DescriptionIssue Description

HW

4

3

Page 1

Page 1Page 1

Solution Description

Solution Description Rev.

Solution DescriptionSolution Description

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

2

Compal Secret Data

Deciphered Date

2

1

Rev.Page#

Rev.Rev.

Compal Electronics, Inc.

Title

HW-PIR Page.1

Size Document Number Rev

LA-C901P

Date: Sheet of

1

48 63Tuesday, August 04, 2015

1.0

5

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )

Request

Page# Title

Item

Item Issue Description

Page#Page#

ItemItem

43

D D

C C

B B

A A

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

Title

TitleTitle

5

Date

DateDate

RequestRequest Owner

Owner

OwnerOwner

4

Issue DescriptionDate

Issue DescriptionIssue Description

HW

4

3

Page 2

Page 2Page 2

Solution Description

Solution Description Rev.

Solution DescriptionSolution Description

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

2

Compal Secret Data

Deciphered Date

2

1

Rev.Page#

Rev.Rev.

Compal Electronics, Inc.

Title

HW-PIR Page.2

S

ize Document Number Rev

Size Document Number Rev

LA-C901P

Date: Sheet of

1

49 63Tuesday, August 04, 2015

1.0

5

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )

Request

Page# Title

Item

Item Issue Description

Page#Page#

ItemItem

85

D D

C C

86

87

88

89

90

91

92

93

94

95

96

97

98

Title

TitleTitle

Date

DateDate

RequestRequest Owner

Owner

OwnerOwner

4

Issue DescriptionDate

Issue DescriptionIssue Description

3

Page 3

Page 3Page 3

Solution Description

Solution Description Rev.

Solution DescriptionSolution Description

2

Rev.Page#

Rev.Rev.

1

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

HW-PIR Page.3

S

ize Document Number Rev

Size Document Number Rev

LA-C901P

Date: Sheet of

1

50 63Tuesday, August 04, 2015

1.0

A

VIN

ADPIN

@

PJPDC

1

2

3

4

5

6

1 1

7

8

GND

9

GND

ACES_50300-00701-001

PSID

12

PC1

EMI@

PC2

EMI@

1000P_0402_50V7K

100P_0402_50V8J

BATT+BATT+

12

PC3

EMI@

1000P_0402_50V7K

B

PC4

EMI@

100P_0402_50V8J

2

3

@

1

PD1 SM24_SOT23

C

PR4

1 3

D

PR6

1 2

100K_0402_1%

PSID-1

PR9

15K_0402_1%

1 2

2

B

E

33_0402_5%

1 2

S

PSID-3

PQ7 FDV301N_G 1N SOT23-3

G

2

PSID-2

C

PQ2 MMST3904-7-F_SOT323~D

3 1

D

+3VALW

PR3

2.2K_0402_5%

1 2

PR8

12

10K_0402_1%

PS_ID <41>

+5VALW

BATT+

12

2 2

Battery connector:

Battery connector: Battery connector:

1.GND

1.GND1.GND

2.GND

2.GND2.GND

3.BAT_ALERT

3.BAT_ALERT3.BAT_ALERT

3 3

4.SYS_PRES

4.SYS_PRES4.SYS_PRES

5.BATT_PRS

5.BATT_PRS5.BATT_PRS

6.DAT_SMB

6.DAT_SMB6.DAT_SMB

7.CLK_SMB

7.CLK_SMB7.CLK_SMB

8.BATT++

8.BATT++8.BATT++

9.BATT++

9.BATT++9.BATT++

10.GND

10.GND10.GND

11.GND

11.GND11.GND

PC16

@

10P_0402_50V8J

12

PC6

PC7

EMI@

0.01U_0402_25V7K

0.022U_0402_25V7K

@

ACES_51202-00901-001

11

10

9

8

7

6

5

4

3

2

1

PBATT

Erp lot6 Circuit

ACIN <10,22,37,41,52>

4 4

200K_0402_1%

0.1U_0402_25V6

CLK_SMB DAT_SMB BATT_PRS SYS_PRES

PR29

PC15

BATT+

12

PC9

PC8

EMI@

100P_0402_50V8J

1000P_0402_50V7K

1 2 1 2

PR22 100_0402_5%

1 2

PR21 100_0402_5% PR19 100_0402_5%

@

JRTC

1

2 G1 G2

ACES_50271-00201-001

1M_0402_1%

12

34

5

12

A

12

1 2 3 4

PR30

PQ9B

PQ3

PC17

1

@

10P_0402_50V8J

2

3

PD2 TVNST52302AB0_SOT523-3

EMI@

1

PD3 TVNST52302AB0_SOT523-3

EMI@

2

3

PR15

1 2

0_0402_5% @

1 2

0_0402_5% @

1 2

0_0402_5% @

PR18

PR20

PR16

10K_0402_1%

1 2

BATT_TEMP <41,51,52>

+3VALW

EC_SMB_CK1 <35,40,41,52>

EC_SMB_DA1 <35,40,41,52>

POK<41,53>

+5VALW

PR14

100K_0402_1%

1 2

PR17

1 2

0_0402_5% @

B+

VSB_N_002

12

@

SI3457CDV-T1-GE3_TSOP6

12

PR12

PC10

PR13

100K_0402_1%

1 2

VSB_N_003

13

D

2

PQ4 2N7002KW_SOT323-3

G

S

PC12

.1U_0402_16V7K

100K_0402_1%

0.22U_0603_25V7K

VSB_N_001

6 5 2

S

D

1

4

G

3

B+_BIAS

12

PC11

0.1U_0402_25V6

+RTCBATT

Adapter Proctection VCIN1_PH setting Trigger point : 0.730V Recovery point : 0.635V

VIN

12

61

1 2

2

PR31 1M_0402_1%

1 2

DMN66D0LDW-7_SOT363-6~D

Adapter protection:

if battery removed, adaptor only, then trigger the H_PROCHOT#, keep @ in BOM since battery can not be removed by end user

PR32

3.3K_1206_5%~D

PQ9A

BATT_TEMP<41,51,52>

DMN66D0LDW-7_SOT363-6~D

H_PROCHOT#<6,41,52>

1U_0603_25V6K

1 2

PC14

VCIN1_PH<41>

PR26

13

D

2

PQ8

G

S

PR28

10K_0402_1%

1 2

B

2N7002KW_SOT323-3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

100K_0402_1%

2015/01/06 2016/01/06

ADP_I <41,52>

PR23 110K_0402_1%

1 2

PC13 .1U_0402_16V7K

1 2

Compal Secret Data

@

Deciphered Date

C

CPU thermal protection at 93 +/- 3 degree C

CPU OTP VCIN0_PH setting Trigger point : 1V Recovery point : 2.21V

VCIN0_PH<41>

100K_0402_1%_TSM0B104F4251RZ

Title

PWR-DCIN/BATT CONN/OTP

Size Document Number Rev

LA-C901P

Date: Sheet of

PR24

16.2K_0402_1%

ECAGND<41>

Compal Electronics, Inc.

+3VLP+3VALW

PR25

@

12.1K_0402_1%

1 2

12

PH1

51 63Tuesday, August 04, 2015

D

51 63Tuesday, August 04, 2015

1.0

A

B

C

D

CC = 3.5A CV = 17.7V CP = 117W/19.5V = 6A Hyprid trigger point = CP x 1.07 =6.42A

PR700 1M_0402_5%

1 2

2

G

PR701 3M_0402_5%

1 2

13

D

PQ700 2N7002KW_SOT323-3

S

Iada=0~6.67A(130W)

1 1

2 2

3 3

PQ701

MDU1516URH_POWERDFN56-8-5

5

12

PC700

2200P_0402_50V7K

PR725

4.7_0603_5%

P1VIN

1 2 3

4 12

ACIN<10,22,37,41,51>

PQ702

MDV1526URH 1N PDFN33-8

1 2 3

12

4

PC701

0.1U_0402_25V6

12

PR706

PR705

4.12K_0603_1%

PR714

1 2

REGN_CHG ACDET_CHG

100K_0402_5%

P2

5

PC707

0.1U_0402_25V6

1 2

12

PR715

120K_0402_5%

PR719

49.9K_0402_1%

12

PR702

0.01_1206_1%

1 2

CSSP_1

12

PR703

0_0402_5%

0.1U_0402_25V6

VIN

12

PR716

324K_0402_1%

12

PC708

1 2

CSSP_2

AC Det Max:18.16V Typ :17.98V Min :17.8V

PC719

2200P_0402_50V7K

ADP_I = 40*Iadapter*Rsense

4 3

CSSN_1

12

BATT+

PR704

0_0402_5%

PC709

0.01U_0402_25V7K

1 2

S SCH DIO BAT54CW-7-F SOT-323 DII

CSSN_2

ADP_I<41,51>

VIN

CMSRC_CHG

ACDRV_CHG

1 2

2

3

1 2

PC711

1U_0603_25V6K

PU700

29

1

2

3

4

5

6

7

PC718

100P_0402_50V8J

1 2

PC720 100P_0402_50V8J

PD700

PWPD

ACN

ACP

CMSRC

ACDRV

ACOK

ACDET

IADP

1

12

PR707

10_1206_1%

LX_CHG

27

28

VCC

BQ24780SRUYR_WQFN28_4X4

IDCHG

8

9

@

PR7270_0402_5%

1 2

PC702

0.047U_0402_25V7K

1 2

12

PR708

2.2_0603_1%

BTST_CHG

DH_CHG

26

25

BTST

HIDRV

PHASE

PROCHOT#

PMON

SDA

10

11

12

PR720

B+

PC706

DH_CHG

LX_CHG

DL_CHG

10U_0805_25V6K

4

PR722 10_0402_5%

1 2

PR723 10_0402_5%

1 2

CHG_B+

5

PQ704

S TR MDV1528URH 1N PDFN33-8

123

3.3UH_PCMB053T-3R3MS_5A_20%

1 2

12

PR713

4.7_1206_5%

@EMI@

SNUB_CHG

12

PQ706

PC715 680P_0402_50V7K

@EMI@

123

S TR MDV1528URH 1N PDFN33-8

0.1U_0402_25V6

PL701

EMI@

1UH_PCMB041B-1R0MS_4.2A_20%

1 2

12

PC703

PC704

0.1U_0402_25V6

@EMI@

12

PR710

31.6K_0402_1%

PQ705

13

D

2N7002W-T/R7_SOT323-3

2

G

S

PR711

6.49K_0402_1%

12

PR718 10K_0402_5%

+3VALW

2200P_0402_50V7K

TB_STAT#_CHG

PC710

1 2

2.2U_0603_16V6K

REGN_CHG

DL_CHG

23

24

22

GND

REGN

LODRV

BATDRV

BATSRC

TB_STAT#

BATPRES#

SCL

CMPOUT

CMPIN

12

14

13

12

0_0402_5%

PR721

0_0402_5%

@

+3VALW

PR709

100K_0402_1%

1 2

21

ILIM

20

SRP

19

SRN

18

BATDRV_CHG

17

BATSRC_CHG

16

TB_STAT#_CHG

15

BATT_TEMP<41,51>

12

PC705

10U_0805_25V6K

MDV1526URH 1N PDFN33-8

5

4

12

BATDRV_CHG

PL700

1

CHG

2

CSOP_1

PC716

0.1U_0402_25V6

1 2

PQ703

1 2 3

PC722

0.022U_0402_25V7K

1 2

PR728

10K_0402_1%

PR712

0.01_1206_1%

PC717

1 2

4 3

CSON_1

0.1U_0402_25V6

12

BATSRC_CHG

PC721

1 2

PR729

10_0402_1%

BATT+

12

PC713

PC712

10U_0805_25V5K~D

<58>

I_SYS

H_PROCHOT#

4 4

A

B

<6,41,51>

<35,40,41,51>

EC_SMB_CK1

EC_SMB_DA1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT C ONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT C ONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR-Charger

PWR-Charger LA-C901P

LA-C901P

D

52 63Tuesday, August 04, 2015

1.0

A

B

C

D

E

+3VLP

PR115

PC101

1 2

4.7U_0603_6.3V6K

0_0603_5%~D

1 2

1 1

VFB=2V

PR102 15K_0402_1%

1 2

PR104 10K_0402_1%

1 2

PR101

6.49K_0402_1%

1 2

PR103

10K_0402_1%

1 2

VFB=2V

Output capacitor ESR need follow below equation to make sure feed back loop stability ESR=20mV*L*fsw/2V

FB_5V

2

3

VFB1

VREG3

VREG5

VO114DRVL1

13

VL

12

PC111

4.7U_0603_6.3V6K

PR106

12

CS1

1

CS1

VCLK

SW1

VBST1

DRVH1

15

68.1K_0402_1%

21

TP

20

EN1

19

18

17

16

+5VALWP

5V_EN

200_0402_1%

1 2

LX_5V

BST_5V

UG_5V

PR107

PR109

0_0603_5%

1 2

@

LG_5V

B+

PC106

0.1U_0402_25V6

1 2

PJ100@

112

JUMP_43X118

12

PC114

PC102

10U_0805_25V6K

2

5

4

+5VALW+5VALWP +3VALW+3VALWP

PQ102

123

MDV1525URH_PDFN33-8-5

LX_5V

5

PQ103

213

MDV1522URH_PDFN33-8-5

5VALWP TDC=9.5A Peak Current 13.5A OCP current 16.2A FSW=300kHz

H/S Rds(on) : 11.5mohm 14mohm L/S Rds(on) : 5.7mohm 6.8mohm

PL102

S COIL 1.5UH +-20% 9A 7X7X3

1 2

12

PR111

4.7_1206_5%

@EMI@

12

PC110

680P_0603_50V8J

@EMI@

TYP MAX

PJ102@

112

JUMP_43X118

+

PC108

220U_B2_6.3VM_R25M

2

+5VALWP

1

2

12

B+

2 2

+3VALWP

3.3VALWP TDC=5.6A Peak Current 8A OCP current 9.6A

3 3

FSW=355kHz H/S Rds(on) : 11.5mohm 14mohm

L/S Rds(on) : 7mohm 8.4mohm

EC_ON<41>

USBCHG_DET_D<33>

4 4

B+

12

PC100

0.1U_0402_25V6

@EMI@

12

PC103

PC104

10U_0805_25V6K

2200P_0402_50V7K

@EMI@

1

+

PC107

2

TYP MAX

PD100

2

1

3

BAS40CW_SOT323-3

VCOUT0_PH#<41>

12

PC113

10U_0805_25V6K

4.7UH_5.5A_20%_7X7X3_M

220U_B2_6.3VM_R25M

EN Rising=1.6~0.3V

3V_EN

5V_EN

2.2K_0402_5%

1 2

PL101

1 2

PR113

PR114 0_0402_5%

1 2

LX_3V

12

PR110

4.7_1206_5%

@EMI@

12

PC109

680P_0603_50V8J

@EMI@

PR100 0_0402_5%

1 2

PR112 0_0402_5%

1 2

POK need pull high, it

5

will pull high on VS transfer circuit

PQ100

PQ101

4

123

MDV1525URH_PDFN33-8-5

5

4

123

MDV1523URH 1N PDFN33-8

POK<41,51>

PC105

0.1U_0402_25V6

1 2

PR108

0_0603_5%

1 2

PU100

3V_EN

LX_3V

BST_3V

UG_3V

LG_3V

B+

OVP=Vout*(112.5%~117.5%) OCP=Vtrip/Rdson+Iripple/2

Vtrip=Ics(min)*Rcs/8+1mV Vcs=Ics*vcs should be in the range of 0.2~2V

Vout=VFB*(1+Rtop/Rbot) VFB=2V

PR105

CS2

5

CS2

6

EN2

7

PGOOD

8

SW2

TPS51225CRUKR_QFN20_3X3

9

VBST2

10

DRVH2

DRVL2

11

54.9K_0402_1%

FB_3V

4

VFB2

VIN

12

A

12

PR116

200K_0402_1%

PC112

4.7U_0603_6.3V6K

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

PWR-3.3VALWP/5VALWP

LA-C901P

E

of

53 63Tuesday, August 04, 2015

of

53 63Tuesday, August 04, 2015

of

53 63Tuesday, August 04, 2015

1.0

5

D D

1.35VP TDC=16.7A Ipeak=24A OCP=28.8A Switching Frequency: 285kHz

PJ203

@

B+

C C

112

JUMP_43X39

2

12

PC217

@

10P_0402_50V8J

+1.35VP

OVP: 110%~120% VFB=0.75V, Vout=1.35V

H/S Rds(on) : 11.7mohm 14mohm L/S Rds(on) : 2.7mohm 3.3mohm

B B

TYP MAX

Mode Level +0.675VSP VTTREF_1.35V S

5 L off off S3 L off on S0 H on on

1.35V_B+

12

PC202

PC201

PC200

0.1U_0402_25V6 2200P_0402_50V7K

@EMI@

PC209

330U_D2_2V_Y

ESR=9m ohm

PL201

1 2

@EMI@

680P_0402_50V7K

1UH_PCMB104T-1R0MH_18A_20%

1

+

2

12

10U_0805_25V6K

4.7_1206_5%

Note: S3 - sleep ; S5 - power off

A A

PC203

PR202

PC211

4

12

PC216

PC215

10U_0805_25V6K

12

10U_0805_25V6K

5

PQ200

MDU1516URH_POWERDFN56-8-5

PQ201

MDU1511RH_POWERDFN56-8-5

4

123

5

4

123

12

PC204

0.1U_0603_25V7K

+5VALW +1.35VP

1U_0402_10V6K

PR203

5.1_0603_5%

1 2

PC212

3

BST_1.35V

0.675V_DDR_VTT_ON<7>

10K_0402_1%

1 2

12

PM_SLP_S4#<6,10,13,37,41>

PR200

2.2_0603_5%

1 2

PR201

PC207

1U_0402_10V6K

1 2

VDD_1.35V

1.35V_B+

SYSON<13,41>

DL_1.35V

CS_1.35V

PR204

2.2_0603_5%

15

14

13

12

11

1 2

PR206

887K_0402_1%

1 2

2

Pin19 need pull separate from +1.35VP. If you have +1.35V and +0.675V sequence question, you can change from +1.35VP to +1.35VS.

BOOT_1.35V

DH_1.35V

SW_1.35V

16

PHASE

LGATE

PGND

CS

RT8207MZQW_WQFN20_3X3

VDDP

VDD

PGOOD

10

PR208

@

0_0402_5%

1 2

PR210

1 2

0_0402_5% @

PC213

@

0.1U_0402_10V7K

PR209

1 2

0_0402_5% @

17

19

18

UGATE

TON

8

9

TON_1.35V

12

20

PU200

21

VTT

BOOT

S5

EN_1.35V

PAD

VTTGND

VTTSNS

GND

VTTREF

VDDQ

FB

6

FB_1.35V

1

2

3

4

5

VTTREF_1.35V

8.06K_0402_1%

1 2

12

PR207 10K_0402_1%

VLDOIN

S3

7

EN_0.675VSP

+1.35VP +1.35V_VDDQ

12

PC214

@

0.1U_0402_10V7K

+0.675VSP +0.675VS_VTT

PR205

@

112

JUMP_43X118

@

112

JUMP_43X118

PJ202

112

JUMP_43X39

+1.35VP

PJ200

PJ201

1

0.675Volt +/- 5% TDC 0.7A Peak Current 1A

+0.675VSP

12

PC205

PC206

10U_0603_6.3V6M

12

PC210

0.033U_0402_16V7K

+1.35VP

2

@

2

+1.35VS_VGA

1

+

PC208

2

330U_D2_2V_Y

Security Classification

2015/01/06 2016/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PWR-1.35VP/0.675VSP

LA-C901P

1

1.0

of

54 63Tuesday, August 04, 2015

of

54 63Tuesday, August 04, 2015

of

54 63Tuesday, August 04, 2015

5

D D

+1.0V_PGOOD<41>

64.9K_0402_1%

+1.8V_PG<56>

C C

PR300

0_0402_5%

1 2

PC300

@

0.1U_0402_16V7K

1 2

12

PR303

12

PR308 10K_0402_1%

4

TRIP_+1.0VSP

EN_+1.0VSP FB_+1.0VSP RF_+1.0VSP

12

PR306

470K_0402_1%

4.32K_0402_1%

+3V_PRIM

12

PR301 10K_0402_5%

PR307

1 2

PU300

1 2 3 4 5

VBST

PGOOD TRIP

DRVH

EN

SW

V5IN

VFB

DRVL

TST

TPS51212DSCR_SON10_3X3

TP

10 9 8 7 6 11

BST_+1.0VSP UG_+1.0VSP SW_+1.0VSP

LG_+1.0VSP

PR302

2.2_0603_5%

1 2

12

PC308 1U_0603_6.3V6M

3

PC305

0.1U_0603_25V7K

1 2

+5VALW

4

+1.0VSP_B+

5

123

5

123

2

PJ301

@

2

112

12

PC301

PC302

0.1U_0402_25V6

@EMI@

PQ300

MDV1525URH_PDFN33-8-5

PQ301

MDV1523URH 1N PDFN33-8

1UH_6.6A_20%_5X5X3_M

12

4.7_1206_5%

12

680P_0402_50V7K

2200P_0402_50V7K

1 2

PR305

@EMI@

PC309

@EMI@

PC303

10U_0805_25V6K

PL300

JUMP_43X39

12

PC304

10U_0805_25V6K

PC306

220U_B2_2.5VM_R15M

Switching Frequency: 290kHz OVP: 120%-130% VFB=0.7V

H/S Rds(on) : 11.5mohm 14mohm L/S Rds(on) : 7mohm 8.4mohm

B+

1.0V TDC 7A Peak Current 10A OCP current 12A FSW=290kHz

1

+

PC307

2

220U_B2_2.5VM_R15M

TYP MAX

1

+1.0VALWP

PJ302

@

+1.0VALWP +1.0V_PRIM

B B

A A

Security Classification

2015/01/06 2016/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

3

Compal Secret Data

Deciphered Date

Title

PWR-1.0VALWP

Size Document Number Rev

LA-C901P

Date: Sheet

2

Date: Sheet

2

112

JUMP_43X39

PJ303

@

2

112

JUMP_43X39

Compal Electronics, Inc.

1

1.0

of

55 63Tuesday, August 04, 2015

of

55 63Tuesday, August 04, 2015

of

55 63Tuesday, August 04, 2015

5

D D

22U_0603_6.3V6M

1 2

PJ800

+3VALW

+3VS

PR812

62K_0402_5%

3V3_MAIN_EN<22,25,57>

NVVDD_PWR_GD<22,25,57>

C C

1 2

PR801

@

33K_0402_5%

1 2

PR802

1M_0402_5%

@

112

JUMP_43X39

+1.05VSP_ON

12

PC800

2 1 2

PR800

@

100K_0402_5%

12

PC801

4

IN

5

PG FB6EN

SY8032ABC_SOT23-6

0.047U_0402_25V7K

PU800

GND

3

LX

LX_1.05V

2 1

12

4.7_0603_5%

12

3

PL800

1 2

1UH_2.8A_30%_4X4X2_F

PR803

@EMI@

PC802

@EMI@

680P_0402_50V7K

7.5K_0402_1%

FB_1.05V

10K_0402_1%

PR804

PR805

12

Rup

12

Rdown

2

+1.05VSP

12

PC803

68P_0402_50V8J

12

PC804

PC805

22U_0603_6.3V6M

1.05VSP TDC 2A Peak Current 2.9A OCP current 3.5A FSW=1MHz

1

Note: When design Vin=5V, please stuff snubber to prevent Vin damage

+1.05VSP +1.05VS_VGA

Vout=0.6V* (1+Rup/Rdown)

PJ802

PR809

0_0402_5%

1 2

2

112

JUMP_43X39

@

4.7U_0603_6.3V6K

+3VALW

B B

PCH_PWR_EN<14,41>

A A

PC806

PR806

10K_0402_5%

+1.8V_VIN

12

PC810

@

12

PC808

@

10P_0402_50V8J

6 7 8 9

10

0.1U_0402_16V7K

+3V_PRIM

11

5

VOUT

VIN VIN VIN EN VCNTL

PU801 APL5930QBI-TRG_TDFN10_3X3

VOUT

GND

VOUT

FB

POK

PR810 10K_0402_5%

1 2

4 3 2 1

+1.8V_PG<55>

12

Rup

Rdown

PR808

PC809

@

12.7K_0402_1%

12

PR807

10K_0402_1%

0.01U_0402_25V7K

Vout=0.8V* (1+Rup/Rdown)

+1.8VALWP +1.8V_PRIM

+1.8VALWP

+1.8V_PRIM TDC 0.27A

12

PC807

10U_0603_6.3V6M

PJ801

@

112

JUMP_43X79

PJ803

112

JUMP_43X39@

2

Security Classification

2015/01/06 2016/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PWR-1.05VS_VGA/1.8V_PRIM

LA-C901P

1

of

56 63Tuesday, August 04, 2015

of

56 63Tuesday, August 04, 2015

of

56 63Tuesday, August 04, 2015

1.0

3V3_MAIN_EN

@

12

PC626

.01U_0402_16V7K

VSSSENSE_VGA

VCCSENSE_VGA

+VGA_CORE

12

1U_0402_6.3V6K

PC613

@

PR620

PR631

@

12

0_0402_5%~D

13

2

G

GPU_FBRTN

10K_0402_1%~D

PR622

0_0402_5%

1 2

PR624

100_0402_1%

1 2

PR627

0_0402_5%

1 2

PR629

100_0402_1%

GPU_REFIN

PR623

@

3K_0402_1%

D

S

PQ610

@

GPU_B+

2N7002KW_SOT323-3

PR616

1 2 12

PR618

PR650

340K_0402_1%

12

18K_0402_1%

0_0402_5%

GPU_FBRTN

PR611

2K_0402_1%

1 2

PC616

@

2700P_0402_50V7K

12

PR606

12

PC617

GPU_REFIN GPU_VREF

GPU_TON GPU_FBRTN

GPU_FB

20K_0402_1%

2700P_0402_50V7K

PR613

20K_0402_1%

1 2

7 8

9 10 11 12

PU600

REFIN VREF TON RGND VSNS SS

PJ600

B+

+3VS

12

PR600 0_0402_5%~D

@

PR610

1 2

12

0_0402_5% @ PR602 0_0402_5%~D

@

1 2

0_0402_5% @

12

PC614

@

47P_0402_50V8J~D

U2_BOOT1

GPU_PSI

GPU_REFADJ

GPU_EN

GPU_VID

U2_UGATE1U2_UGATE2

6

GND

13

25

2

1

3

5

4

EN

PSI

VID

REFADJ

TALERT/ISEN2

TSNS/ISEN3

14

BOOT1

UGATE1

PGOOD

VCC/ISNE1

17

16

15

24

PHASE1

23

LGATE1

22

GND/PWM3

21

PVCC

20

LAGTE2

19

PHASE2

BOOT218UGATE2

RT8813AGQW_WQFN24_4X4

@

112

JUMP_43X79

PL600

@EMI@

1 2

FBMA-L11-453215800LMA90T_2P

NVVDD PWM_VID <22>

PR607

+3VS

12

PR614

@

10K_0402_1%~D

12

PC618

@

0.047U_0402_25V7K

U2_PHASE1 U2_LGATE1

U2_PWM3

U2_LGATE2 U2_PHASE2

2

NVVDD PSI <22>

PR615

0_0402_5%

1 2

PR625

2.2 +-5% 0603

1 2

12

PC622

1U_0603_6.3V6M

+5VS

GPU_B+

U2_BOOT1

U2_PHASE1

U2_LGATE1

3V3_MAIN_EN <22,25,56,57>

U2_BOOT2

U2_PHASE2

PR601

2.2 +-5% 0603

1 2

PR617

2.2 +-5% 0603

1 2

PR649

12

PC634

PC600

10U_0805_25V6K

@EMI@

U2_UGATE1

1

12

.1U_0603_25V7K

10.5K_0402_1%

12

2

D1

PC612

PC619

.1U_0603_25V7K

G1

D2/S1

S24S2

S2

5

3

6

GPU_B+

U2_UGATE2

1

2

D1

D2/S1

S24S2

S2

5

3

2200P_0402_50V7K~D

PQ605 S TR AON6992 2N DFN5X6D

0.24UH_PCME063T-R24MS1R195_28A_20%

7

U2_PHASE1

G2

12

PC601

10U_0805_25V6K

PQ606 S TR AON6992 2N DFN5X6D

G1

0.24UH_PCME063T-R24MS1R195_28A_20%

7

U2_PHASE2

G2

6

U2_LGATE2

PL601

PL602

+VGA_CORE

12

VGA_CORE TDC 51.1A Peak Current 87A OCP=104A

H/S Rds(on):6.7mohm ,8.5mohm L/S Rds(on):1.8mohm ,2.3mohm

12

TYP MAX

1 2

PHASE3

PR638

+5VS

GPU_PGOOD1

GPU_TALERT/ISEN2

GPU_TSNS/ISEN3

GPU_DSBL/ISEN1

U2_BOOT2

NVVDD_PWR_GD<22,25,56>

+3VS

12

PR639

PR619

10K_0402_1%~D

10K_0402_1%

PR646

1 2

10K_0402_1%

U2_PHASE2

PC627

@

PR648

1 2

10K_0402_1%

U2_PHASE1

1 2

12

0_0402_5% @

U2_PWM3

.01U_0402_16V7K

PR643

2.2 +-5% 0603

PC629

.1U_0603_25V7K

PR642

1 2

0_0402_5% @

12

GPU_EN

PU601

8

UGATE

VCC

1

BOOT

EN

5

PWM

PHASE

6

LGATE

GND

TP

RT9610BZQW WDFN8 MOSFET DRIVER ET88

9

3 4 2 7

UG3

LG3

PR633

2.2 +-5% 0603

1 2

PHASE3

12

PC625

.1U_0603_25V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT C ONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT C ONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GPU_B+

2

D1

S2

3

12

PC602

10U_0805_25V6K

1

PQ607 S TR AON6992 2N DFN5X6D

G1

7

PHASE3

D2/S1

S24S2

G2

5

6

2015/01/06 2016/01/06

PL603

0.24UH_PCME063T-R24MS1R195_28A_20%

Compal Secret Data

12

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PWR-VGA_CORE

LA-C901P

of

57 63Tuesday, August 04, 2015

of

57 63Tuesday, August 04, 2015

of

57 63Tuesday, August 04, 2015

1.0

5

4

3

2

1

+1.0V_VCCST

PR501

12

Local sense put on HW site

D D

VR_HOT#<41>

470K_0402_5%_ TSM0B474J4702RE

PH500

1 2 1 2

PR516

27.4K_0402_1%

2200P_0402_50V7K

+VCC_GT

VCCGT_SENSE<15>

C C

VSSGT_SENSE<15>

ISUMP_GT<59>

20M_0402_5%

ISUMN_GT<59>

B B

PR572

@

1 2

330P_0402_50V7K

PC520

1 2

0.01U_0402_50V7K

1 2

PC500 47P_0402_50V8J~D@

PC514

3.6K_0402_1%

1 2

PC515 68P_0402_50V8J

1 2

PR586 100_0402_1%

PC517

PR585

100_0402_1%

1 2

12

PR529

4.42K_0402_1%

12

PH502

10K +-5% 0402 B25/50 4250K

12

PC541

.1U_0402_16V7K

1 2

PR514

10.5K_0402_1%

1 2

PR520

12

PR532

SOC_SVID_CLK<15>

SOC_SVID_ALERT#_R<15>

SOC_SVID_DAT<15>

PR511

0_0402_5%

1 2

PC516

1000P_0402_50V7K

1 2

PR523

1.96K_0402_1%

PC526

0.082U_0402_16V7K

0.1U_0402_25V6

PC521 680P_0402_50V7K

1 2

12

PC527

@

0.01U_0402_25V7K

1 2

12

PC519

@

12

11K_0402_1%

PR517

86.6K_0402_1%

1 2

PC513 330P_0402_50V8J

1 2

PR522

316_0402_1%

1 2

PR534

1K_0402_1%

1 2

274_0402_1%

1 2

PR505 0_0402_5% @

1 2

PR507 0_0402_5% @

1 2

PR509 0_0402_5% @

PR525 2K_0402_1%

PC529

2200P_0402_50V7K

1 2

PR538

PR500

@

45.3_0402_1%

+3VS

VR_PWRGD<41>

VR_ON<10>

I_SYS<52>

FCCM_GT<59> PWM1_GT<59>

470K_0402_5%_ TSM0B474J4702RE

+5VALW

+VCC_CORE

VCCSENSE<15>

A A

VSSSENSE<15>

Local sense put on HW site

5

4

12

PR503

PR502

75_0402_1%

100_0402_1%

1 2

PH501

1 2

27.4K_0402_1%

PR536

1 2

PC533

2200P_0402_50V7K

1 2

PC540

2200P_0402_50V7K

1 2

PR546

1 2

1.37K_0402_1%

PR581

100_0402_1%

1 2

PC551

@

1 2

330P_0402_50V7K

PC554

1 2

0.01U_0402_50V7K

PR582

100_0402_1%

1 2

12

PC501

0.1U_0402_25V6

1 2 1 2 1 2

1 2 1 2

PR5180_0402_5%

1 2

PR519 0_0402_5%

PU500

PR5210_0402_5%

1 2 3 4 5 6 7 8 9

10 41

PC524

330P_0402_50V7K

1 2

PR530

84.5K_0402_1%

1 2

PR541

3.6K_0402_1%

1 2

PC535

68P_0402_50V8J

1 2

PR545

316_0402_1%

1 2

PR50649.9_0402_1% PR5080_0402_5% PR51010_0402_1%

PR5151.91K_0402_1%

PSYS IMON_B NTC_B COMP_B FB_B RTN_B ISUMP_B ISUMN_B ISEN1_B ISEN2_B

AGND

PR533

10.5K_0402_1%

@

39

40

VR_ENABLE

FCCM_B11PWM1_B12PWM2_B13IMON_A14NTC_A15COMP_A

12

1 2

12

PC553

@

12

1 2

PR512

34K_0402_1%

1 2

PR513

48.7K_0402_1%

33

34

36

38

37

32

35

VIN

SDA

VCC

SCLK

PROG231PROG1

ALERT#

VR_HOT#

VR_READY

IMON_IA

2K_0402_1%

PR549

PC548

680P_0402_50V7K

0.082U_0402_16V7K

PWM_C

FCCM_C

ISUMN_C

ISUMP_C

RTN_C

FB_C

COMP_C

IMON_C

PWM_A

FCCM_A

FB_A

RTN_A18ISUMP_A19ISUMN_A

17

16

20

ISL95857HRTZ-T_TQFN40_5X5

FB_IA

COMP_IA

NTC_IA

PR552

4.42K_0402_1%

1 2

PR570

20M_0402_5%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1_0402_5%

1 2

PR504

0_0402_5%

1 2

12

PC502

PC503

1U_0402_10V6K

0.1U_0402_25V6

30

PWM_VSA

29

FCCM_VSA

28 27 26 25

FB_VSA

24

COMP_VSA

23

IMON_VSA

22 21

12

PC530

2200P_0402_50V7K

12

PR543

1K_0402_1%

PC543

@

0.01U_0402_25V7K

1 2

PC546

0.1U_0402_25V6

1 2

PR551

11K_0402_1%

1 2

PH504

10K +-5% 0402 B25/50 4250K

1 2

ISUMP_IA <59>

3

+5VALW

CPU_B+

PC504

@

PR528 0_0402_5%

1 2

FCCM_VSA

0.22U_0402_16V7K PC518

1 2

PR524

2.2_0603_5%

PWM_IA <59> FCCM_IA <59>

1000P_0402_50V7K

12

PR537

249_0402_1%

12

PC545

.1U_0402_16V7K

ISUMN_IA <59>

2015/01/06 2016/01/06

12

PC522

12

10P_0402_50V8J

12

330P_0402_50V7K

PC542

PR531

7.32K_0402_1%

12

1200P_0402_50V7K

PC531

12

PR548

133K_0402_1%

Deciphered Date

PC528

Compal Secret Data

12

@

PR550

12

@

1

+

PC505

2

33U_D2_25VM_R60M

1

ZCD_EN#

2

VCIN

3

CGND

4

BOOT

5

PHASE

6

VIN PGND7VSWH

1_0402_5% PR579

12

PR535 1.4K_0402_1%

1 2

PR547

1 2

1.69K_0402_1%

2

1

+

PC506

2

33U_D2_25VM_R60M

PU501

CGND

PWM VDRV PGND

GL

1_0402_5% PR580

+5VS

1 2

1K_0402_1%

PC539

1 2

2200P_0402_50V7K

PR540

+

2

SIC531CDT1GE3_POWERPAK22_4X3

12

PC523 1U_0402_10V6K

PC532 2200P_0402_50V7K

PR544

1 2

316_0402_1%

2K_0402_1%

PC547

680P_0402_50V7K

VCC_SA TDC 4A Peak Current 5A OCP current 6A Choke DCR 13 m ohm

CPU_B+

EMI@

1 2

@EMC@

12

PC512

2200P_0402_50V7K

1UH +-20% 6.6A

PL500

1 2

12

PR527

3.65K_0603_1%

ISUMP_VSA

12

PC537

1 2

6800P_0402_25V7K

100_0402_1%

1 2

0.01U_0402_50V7K

330P_0402_50V7K

1 2

100_0402_1%

FBMA-L11-453215800LMA90T_2P

ISUMN_VSA

PR542

1 2

PR584

PC549

1 2

@

PC552

1 2

PR583

1

@EMC@

12

PC509

PC508

10U_0805_25V6K

13 12 11 10 9 8

PWM_VSA

SA_SW

12

PC534 1U_0402_10V6K

Title

Size Document Number Rev

Date: Sheet of

12

PC510

PC511

10U_0805_25V6K

0.1U_0402_25V6K~D

PT1

TP@

12

@EMC@

PR526

4.7_1206_5%

SA_SNUB

12

PC525

680P_0603_50V7K

@EMC@

12

PC536

0.033U_0402_16V7K

PC544

.1U_0402_16V7K

1 2

PC550

@

0.082U_0402_16V7K

Compal Electronics, Inc.

PWR-CPU_VCC_SA

LA-C901P

PL501

12

PR539

2.61K_0402_1%

12

11K_0402_1%

+VCC_SA

58 63Tuesday, August 04, 2015

+VCC_SA

ISUMP_VSA

PR571 20M_0402_5%

1 2

PH503

10K +-5% 0402 B25/50 4250K

ISUMN_VSA

VSA_SEN- <13>

VSA_SEN+ <13>

B+

@

1.0

5

D D

CPU_B+ CPU_B+

4

VCC_core TDC 21A Peak Current 28A OCP current 34A Choke DCR 0.66 +-7%m ohm

3

2

VCC_GT TDC 18A Peak Current 31A OCP current 37A Choke DCR 0.66 +-7%m ohm

1

12

PC557

PC556

10U_0805_25V6K

PR573

1_0402_5%

1 2 12

PC567

1U_0402_10V6K

PC560

1 2

0.22U_0402_16V7K

1 2

PR553

4.7_0603_5%

12

PC559

PC558

2200P_0402_50V7K

0.1U_0402_25V6K~D

PWM_IA

FCCM_IA

@

PU502

PR556

1

0_0402_5%

1 2

2 3 4 5 6 7 8

9 10 11 12 13 14

SIC632CDT1GE3_POWERPAK31_5X5

<58>

PWM ZCD_EN# VCIN CGND BOOT NC PHASE VIN VIN PGND SW SW SW SW

CGND

DSBL#

THWn

VDRV

PGND

+5VS

12

PR575

PR577

1_0402_5%

10K_0402_5%

1 2

28 27

GL

26 25 24 23 22

GL

21

SW

20

SW

19

SW

18

SW

17

SW

16

SW

15

SW

TP@

1U_0402_10V6K

1 2

PT2

CORE_SW

PC569

PL503

0.15UH_PCME064T-R15MS_36A_20%

1

4 3

2

12

@EMC@

12

PR555

PR554

3.65K_0603_1%

4.7_1206_5%

CORE_SNUB

12

PC568

680P_0603_50V7K

@EMC@

<58>

ISUMP_IA

+VCC_CORE

12

PC579

1000P_0402_50V7K

<58>

ISUMN_IA

12

PC555

10U_0805_25V6K

+5VS

C C

12

PC561

1000P_0402_50V7K

B B

12

PC573

PC572

10U_0805_25V6K

PR574

1_0402_5%

1 2 12

PC580

1U_0402_10V6K

PC578

1 2

0.22U_0402_16V7K

1 2

PR564

4.7_0603_5%

12

PC574

10U_0805_25V6K

FCCM_GT

@

PR569

1 2

@EMC@

10 11 12 13 14

PC575

1 2 3 4 5 6 7 8 9

12

0.1U_0402_25V6K~D

<58>

PU503

PWM ZCD_EN# VCIN CGND BOOT NC PHASE VIN VIN PGND SW SW SW SW

12

PC576

2200P_0402_50V7K

<58>

CGND

GL

DSBL#

THWn

VDRV

PGND

GL SW SW SW SW SW SW SW

12

10U_0805_25V6K

PWM1_GT

0_0402_5%

SIC632CDT1GE3_POWERPAK31_5X5

12

PR576

PR578

1_0402_5%

1 2

10K_0402_5%

28 27 26 25 24 23 22 21 20 19 18 17 16 15

TP@

PT3

GT_SW

PC570

1U_0402_10V6K

1 2

12

@EMC@

PR565

4.7_1206_5%

GT_SNUB1

12

PC581

@EMC@

PL504

0.15UH_PCME064T-R15MS_36A_20%

1

4

+VCC_GT

3

2

GT1P

PR567

3.65K_0603_1%

1 2

<58>

680P_0603_50V7K

ISUMP_GT

<58>

ISUMN_GT

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PWR-CPU_VCC_CORE/GT

LA-C901P

59 63Tuesday, August 04, 2015

1

1.0

5

+VGA_CORE

D D

4

3

2

1

1U_0402_10V6K

PC927

12

22U_0805_6.3VAM

1

PC944

2

C C

4.7U_0603_6.3V PC954

12

B B

1U_0402_10V6K

PC928

12

1

2

12

PC929

12

4.7U_0805_6.3V6K

22U_0805_6.3VAM

12

PC946

PC945

4.7U_0603_6.3V

PC955

PC956

12

1U_0402_10V6K

PC930

12

4.7U_0805_6.3V6K

12

PC947

4.7U_0603_6.3V PC957

12

1U_0402_10V6K

PC931

12

PC932

12

4.7U_0805_6.3V6K

12

PC949

PC948

4.7U_0603_6.3V

PC958

PC959

12

1U_0402_10V6K

PC934

PC933

12

4.7U_0603_6.3V

4.7U_0805_6.3V6K

12

PC951

12

PC950

22U_0805_6.3VAM

4.7U_0603_6.3V PC960

1

PC961

2

4.7U_0603_6.3V

PC952

12

1

2

PC953

12

22U_0805_6.3VAM

1

PC963

PC962

2

22U_0805_6.3VAM

1

2

PC965

PC964

2

1

+

2

PC966

470U_D2_2VM_R4.5M~D

1

+

2

PC967

470U_D2_2VM_R4.5M~D

PC968

470U_D2_2VM_R4.5M~D

1

+

2

PC970

PC969

470U_D2_2VM_R4.5M~D

A A

Security Classification

2015/01/06 2016/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PWR-GPU DECOUPLING

LA-C901P

1

1.0

of

60 63Tuesday, August 04, 2015

of

60 63Tuesday, August 04, 2015

of

60 63Tuesday, August 04, 2015

A

B

C

D

E

+VCC_GT

1

PC1019

2

+VCC_CORE

1 1

2 2

3 3

1

PC1000

PC1001

PC1002

2

22U_0603_6.3V6M

1

PC1032

PC1031

2

10U_0402_6.3V6M

12

PC1056

PC1057

1U_0201_6.3V6M

12

PC1089

PC1088

1U_0201_6.3V6M

220U 2.5V Y D2 ESR9M H1.9 SX

1

PC1122

PC1121

+

2

PC1003

2

22U_0603_6.3V6M

1

2

12

1

PC1034

PC1033

2

10U_0402_6.3V6M

12

PC1058

PC1059

1U_0201_6.3V6M

12

PC1091

PC1090

1U_0201_6.3V6M

1

PC1005

PC1004

2

22U_0603_6.3V6M

1

PC1035

PC1036

2

10U_0402_6.3V6M

47U_0805_6.3V6M

12

PC1060

PC1061

1U_0201_6.3V6M

12

PC1092

PC1093

1U_0201_6.3V6M

1

PC1007

PC1006

2

22U_0603_6.3V6M

1

PC1037

PC1038

2

@

47U_0805_6.3V6M

12

PC1062

PC1063

1U_0201_6.3V6M

12

PC1094

PC1095

1U_0201_6.3V6M

1

PC1008

PC1009

2

22U_0603_6.3V6M

10U_0402_6.3V6M

1

PC1039

PC1040

2

47U_0805_6.3V6M

12

PC1065

PC1064

1U_0201_6.3V6M

12

PC1096

PC1097

1U_0201_6.3V6M

1

PC1011

PC1010

2

10U_0402_6.3V6M

1

PC1042

PC1041

2

@

47U_0805_6.3V6M

12

PC1067

PC1066

1U_0201_6.3V6M

12

PC1099

PC1098

1U_0201_6.3V6M

1

PC1013

PC1012

2

10U_0402_6.3V6M

PC1043

47U_0805_6.3V6M

12

PC1069

PC1068

1U_0201_6.3V6M

12

PC1100

PC1101

1U_0201_6.3V6M

1

PC1014

PC1015

2

10U_0402_6.3V6M

12

PC1071

PC1070

1U_0201_6.3V6M

12

PC1103

PC1102

1U_0201_6.3V6M

1

PC1018

PC1017

PC1016

2

10U_0402_6.3V6M

PC1072

1U_0201_6.3V6M

12

PC1104

PC1105

1U_0201_6.3V6M

2

22U_0603_6.3V6M

1

PC1044

2

10U_0402_6.3V6M

1

PC1151

2

10U_0402_6.3V6M

1

PC1163

2

10U_0402_6.3V6M

12

PC1073

1U_0201_6.3V6M

1

PC1021

PC1020

2

22U_0603_6.3V6M

1

PC1045

PC1046

2

10U_0402_6.3V6M

1

PC1153

PC1152

2

10U_0402_6.3V6M

1

PC1165

PC1164

2

10U_0402_6.3V6M

12

PC1075

PC1074

1U_0201_6.3V6M

1

PC1022

2

22U_0603_6.3V6M

1

PC1047

2

10U_0402_6.3V6M

1

PC1154

2

10U_0402_6.3V6M

1

PC1167

2

10U_0402_6.3V6M

12

PC1076

1U_0201_6.3V6M

1

PC1024

PC1023

2

22U_0603_6.3V6M

1

PC1048

PC1049

2

10U_0402_6.3V6M

1

PC1155

PC1156

2

10U_0402_6.3V6M

1

PC1169

PC1166

2

10U_0402_6.3V6M

12

PC1077

PC1078

1U_0201_6.3V6M

1

PC1025

PC1026

2

@

22U_0603_6.3V6M

47U_0805_6.3V6M

1

PC1050

PC1051

2

10U_0402_6.3V6M

1

PC1157

PC1158

2

10U_0402_6.3V6M

1

PC1171

PC1168

2

10U_0402_6.3V6M

12

PC1080

PC1079

1U_0201_6.3V6M

1

PC1027

2

@

47U_0805_6.3V6M

1

PC1052

2

10U_0402_6.3V6M

1

PC1159

2

10U_0402_6.3V6M

1

PC1170

2

10U_0402_6.3V6M

12

PC1081

1U_0201_6.3V6M

1

PC1029

PC1028

47U_0805_6.3V6M

PC1053

10U_0402_6.3V6M

PC1160

10U_0402_6.3V6M

PC1172

10U_0402_6.3V6M

PC1082

1U_0201_6.3V6M

PC1030

2

@

47U_0805_6.3V6M

1

PC1054

PC1055

2

10U_0402_6.3V6M

1

2

1

2

12

1

PC1162

PC1161

2

10U_0402_6.3V6M

1

PC1174

PC1173

2

10U_0402_6.3V6M

12

PC1083

PC1084

1U_0201_6.3V6M

1

PC1176

PC1175

10U_0402_6.3V6M

PC1178

10U_0402_6.3V6M

PC1085

1U_0201_6.3V6M

PC1177

2

10U_0402_6.3V6M

1

PC1180

PC1179

2

10U_0402_6.3V6M

12

PC1087

PC1086

1U_0201_6.3V6M

12

PC1106

+VCC_SA

1

PC1129

2

10U_0402_6.3V6M

4 4

12

PC1142

1U_0201_6.3V6M

A

1

PC1130

2

10U_0402_6.3V6M

12

PC1143

1U_0201_6.3V6M

1

PC1132

PC1131

2

10U_0402_6.3V6M

12

PC1144

PC1145

1U_0201_6.3V6M

1

PC1133

2

10U_0402_6.3V6M

12

PC1146

1U_0201_6.3V6M

1

PC1135

PC1134

2

10U_0402_6.3V6M

1

12

PC1147

PC1148

2

1U_0201_6.3V6M

1

PC1138

PC1137

PC1136

2

10U_0402_6.3V6M

1

PC1149

2

47U_0805_6.3V6M

B

2

10U_0402_6.3V6M

PC1150

47U_0805_6.3V6M

1

PC1139

10U_0402_6.3V6M

PC1141

PC1140

2

10U_0402_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2015/01/06 2016/01/06

Compal Secret Data

1U_0201_6.3V6M

12

PC1123

1U_0201_6.3V6M

Deciphered Date

PC1124

1U_0201_6.3V6M

12

PC1107

PC1108

1U_0201_6.3V6M

12

PC1125

PC1126

1U_0201_6.3V6M

D

12

PC1110

PC1109

1U_0201_6.3V6M

1

+

2

PC1111

1U_0201_6.3V6M

220U 2.5V Y D2 ESR9M H1.9 SX

1

PC1128

PC1127

+

2

12

PC1113

PC1112

1U_0201_6.3V6M

Title

PWR-CPU DECOUPLING

Size Document Number Rev

LA-C901P

Date: Sheet

12

PC1114

1U_0201_6.3V6M

Compal Electronics, Inc.

12

PC1116

PC1115

1U_0201_6.3V6M

12

PC1117

1U_0201_6.3V6M

E

12

PC1119

PC1118

1U_0201_6.3V6M

PC1120

1U_0201_6.3V6M

1.0

of

61 63Tuesday, August 04, 2015

of

61 63Tuesday, August 04, 2015

of

61 63Tuesday, August 04, 2015

5

4

3

2

1

Power block

CPU OTP

D D

B+

+3VALWP: TDC:5.6A +5VALWP: TDC:9.5A

DC IN

Input Switch

Page 52

TPS51225CRUKR

CHARGER CC:3.5A CV:17.7V

+1.35VP/+0.675VSP:TDC:16.7A/0.7A

T8207MZQW

R

BQ24780S

Page 52

C C

Battery

+1.0VALWP: TDC:7A TPS51212DSCR

+1.05VSP: TDC:2A S

Y8032ABC

+1.8VALWP: TDC:0.27A APL5930QBI

3V3_MAIN_EN

B B

+VGA_CORE TDC:51.1A RT8813AGQW

Page 57

Page 51

Turn Off

Always

Page 53

PM_SLP_S4#

Page 54

+1.8V_PG

Page 55

3V3_MAIN_EN

Page 56

PCH_PWR_EN

Page 56

+VCC_CORE T

DC: 21A

VR_ON

+VCC_GT TDC:18 +VCC_SA TDC:4A ISL95857HRTZ

Page 58,59

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PWR_POWER BLOCK DIAGRAM

LA-C901P

1

of

62 63Tuesday, August 04, 2015

of

62 63Tuesday, August 04, 2015

of

62 63Tuesday, August 04, 2015

1.0

5

Item

Item Issue Description

ItemItem

D D

Page# Title

Page#Page#

1 56 1.05VS_VGA 2015/3/6 Compal_PWR For EE request to fine tune power sequence. Change PR812 from 33k to 62k. X01

Title

TitleTitle

Date

DateDate

4

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )

Request

RequestRequest

Owner

OwnerOwner

Issue DescriptionDate

Issue DescriptionIssue Description

3

Page 1

Page 1Page 1

2

Solution Description

Solution Description Rev.

Solution DescriptionSolution Description

1

Rev.Page#

Rev.Rev.

2 57 VGA_CORE 2015/3/6 Compal_PWR For EE request to fine tune power sequence. X01

3 58,59 CPU 2015/4/1 Compal_PWR For CPU transient and DC/DC EA fine tune.

4 54 1.35VP 2015/4/7 Compal_PWR For EE request to fine tune power sequence. Add PR210 to connect with PM_SLP_S4# , non-pop PR208. X01

C C

5 54 1.35VP 2015/4/8 Compal_PWR For fine tune OCP. Change PR201 from 8.06kohm to 10kom. X01

6 55 1.0VALWP 2015/4/8 Compal_PWR Improve output ripple voltage. Add PC307. X01

7 51 Compal_PWR2015/5/20 For change CPU OTP point. Change PR24 from 12.1k to 16.2k. X04

8 51 DCIN/BATT CONN/OTP

9 57 VGA_CORE 2015/7/8 Compal_PWR Add PJ600For cost down change baed to jumper

B B

10 53 3.3VALWP 2015/7/8 Compal_PWR remove PL101

11 2015/7/8 Compal_PWR HW didn't need this. remove PR81156 1.8V_PRIM remove PR811

DCIN/BATT CONN/OTP

2015/7/8 Compal_PWR For cost down removed baed 1.0remove PL1,PL2,PL3

For cost down removed baed

Change PR615 from 33k to 0. Non-pop PC618.

Change PR550 from 2kOhm to @. Change PC547 from 680pF to @. Change PC543 from 0.01uF to @. Change PC527 from 0.01uF to @. Change PR552 from 2.61kOhm to 4.42kOhm. Change PR529 from 2.61kOhm to 4.42kOhm. Change PC516 from 2200pF to 1000pF. Change PR570 from @ to 20MOhm. Change PR553,PR564 from 2.2 to 4.7ohm

X01

1.0

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PWR-PIR

LA-C901P

1.0

of

63 63Tuesday, August 04, 2015

of

63 63Tuesday, August 04, 2015

of

63 63Tuesday, August 04, 2015

1