Compal LA-C901P Schematics Rev1.0

MODEL NAME : AAP01 PROJECT CODE : ANRAAP0100 PCB NO :

DAA000AK000 LA-C901P M/B

1 1

DA400237000 LS-C901P SSD/B DA40023X000 LS-C902P SSD/B (w/o redriver) DA40023Y000 LS-C904P LOGO/B

ZZZ

PCB@

PCB 1FU LA-C901P REV0 M/B MLK 3

DAA000AK000

ZZZ

PCBR1@

2 2

PCB 1FU LA-C901P REV1 M/B MLK 3

DAA000AK010

ZZZ

PCBR3@

PCB 1FU LA-C901P REV1 MB MLK TRIP 3 A31!

DAA000AK011

ZZZ

DAZR1@

Echo MLK 13" SKL-U

Skylake U-type (1 chip_DSC)

REV : 1.0 (A00)

2015.07.14

@ : Nopop Component

PCB AAP01 LA-C901P LS-A302P/A303P/C904P 02

DAZ1FU00100

ZZZ

DAZR3@

EMI@,ESD@ : EMI/ESD/RF part

CONN@ : Connector Component

PCB AAP01 LA-C901P LS-A302P/A303P/C904P 02 TRIPOD A31 !

DAZ1FU00101

3 3

ROYALTY HDMI W/LOGOHDMI@

Part Number Description

HDMI W/Logo:RO0000002HM

RO0000002HM

Layout Dell logo

4 4

REV: X00 PWB: XXXXX DATE: 1450-06

CMC@ : Total debug Component

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Cover page

Cover page LA-C901P

LA-C901P

1 63Tuesday, August 04, 2015

1.0

eDP

P.20

eDP 1.3

panel

1 1

P.47

USB3 TypeC

USB PD I2C/USB2

HDMI

TPS65982

P.21

P.46

ThunderBolt Alpine Ridge-SP

P.44,45

DP 1.2 (DDI1) DP 1.2 (DDI2)

PCI-E x2(port9,port10)

connector

HDMI 2.0

dGPU nVIDIA N16P-GX,50W 4pcs GDDR5

2 2

P.34

PCI-E x4 (Gen3)

PCIE MUX PERICOM PI3PCIE3415

PCI-E x4 (Gen3)

Video Docking Caldera

P.34P.22~29

USB3.0 port3 USB2.0 port3

PCI-E(Gen3)x4 po

rt1~port4

Skylake U

Skylake PCH-LP (MCP)

(SKL-U_2+2)

15W BGA 1356 balls

CDR_I2C

P.32

P.30P.30

P.08

PCI-E3.0 port5 USB2.0 port8

PCI-E3.0 port6

PCI-E3.0 port7,8 SATA3.0 port0,1

I-E3.0 port11,12

SATA3.0 port1,2

SPI

NGFF (M.2)WLAN+BT QCA killer 1535(A Key)

RJ45 connector

3 3

Storage Option2 Dual M.2 DB

LAN(Gigabit) Killer E2400

NGFF (M.2) SSD 1

NGFF (M.2) SSD 2

SPI ROM 16MB

DC in

1.0V

Battery

3V/5V

System

4 4

1.35V

1.5V

CPU Vcore

dGPU Core

Charger

dGPU

1.35V

Int. KBD

ENE KC3810

P.40

P.41

LPC Bus

ENE KB9022

P.41

PS2

P.06~17

I2C(400KHz)

Touch pad

Memory Bus Dual Channel

35V,DDR3L,1600 MHz

B3.0 port2

SB2.0 port2

U USB3.0 port1

USB2.0 port1

USB2.0 port5

USB2.0 port6

USB2.0 port7

SATA3.0 port0 ; option

HD Audio

P.38

FFS KXCNL-1010

CDR_I2C

Audio codec Realtek ALC3234

P.36 P.40 P.06

Fan control NCT7718W W83L771AWG-2

CMC connector (Reserve)

P.18,19

204pin SO-DIMM x2

P.38,39

LED SET

P.33

P.20

P.37

P.36

USB connector 1 , Left side USB power share

USB connector 2 , Right side 1

Touch screen

Digital camera(with digital MIC)

AlienFX / ELC , C8051F383-GQ

ELC PWM expander , TLC59116F

2.5”HDD

Storage Option1

P.31

digital MIC

Speaker

Headphone/MIC Global headset combo JACK

Headphone/MIC Retaskable combo JACK

P.31

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT C ONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT C ONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Block diagram

Block diagram LA-C901P

LA-C901P

2 63Tuesday, August 04, 2015

1.0

Power on sequence

DCACEC_ON

DCACVCCDSW(+3VALW)

DCACPCH_PWR_EN(SLP_SUS#)

+3V/+1.8V_PRIM

SUSACK#

DCAC

Power Button

DPWROK_EC

EC_RSMRST#

AC_Present

Power Button Out

1 1

PM_SLP_S4# (Input)

PM_SLP_S3# (Input)

SYSON

SUP#

VCCST_PG_EC

VR_ON

VR_PWRGD

PCH_PWROK

SYS_PWROK

T_RST#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Power on sequence

Power on sequence LA-C901P

LA-C901P

3 63Tuesday, August 04, 2015

1.0

Board ID Table for AD channel

Vcc 3.3V

Board ID

10 11 12 13 14 15 16 17 18 19

Board ID table and PCB version

1 1

0 1 2 3 4 5 33K 6 7 56K

100K +/- 1%Ra

0 1

12K +/- 1% 0.354V

Rb V min

20K +/- 1%

27K +/- 1%

33K +/- 1%

43K +/- 1%

56K +/- 1%

75K +/- 1%

100K +/- 1% 130K +/- 1% 160K +/- 1% 200K +/- 1% 240K +/- 1% 270K +/- 1% 330K +/- 1% 430K +/- 1% 560K +/- 1% 750K +/- 1%

AD_BID

0.347V

0.423V 0.430V

0.541V 0.559V

0.691V

0.807V

0.978V

1.169V

1.398V

1.634V

1.849V

2.015V

2.185V

2.316V

2.395V

2.521V

2.667V

2.791V

2.905V

3.000V 3.000V

0 12K 15K 20K 27K

EVT(R0.1) DVT-1(R0.2) DVT-1.1(R0.3) DVT-2(R0.4) Pilot(R1.0)

43K

V typ

AD_BID

0.000V 0.300V

0.360V

0.438V15K +/- 1%

0.550V

0.702V

0.819V

0.992V

1.185V

1.414V

1.650V

1.865V

2.031V

2.200V

2.329V

2.408V

2.533V

2.677V

2.800V

2.912V

0.713V

0.831V

1.006V

1.200V

1.430V

1.667V

1.881V

2.046V

2.215V

2.343V

2.421V

2.544V

2.687V

2.808V

2.919V

max

EC AD3

0x00 - 0x13 0x14 - 0x1E 0x1F - 0x25 0x26 - 0x30 0x31 - 0x3A 0x3B - 0x45 0x46 - 0x54 0x55 - 0x64 0x65 - 0x76 0x77 - 0x87 0x88 - 0x96 0x97 - 0xA4 0xA5 - 0xAF 0xB0 - 0xB7 0xB8 - 0xBF 0xC0 - 0xC9 0xCA - 0xD4 0xD5 - 0xDD 0xDE - 0xF0 0xF1 - 0xFF

ULT

Port1 Port2 Port3 Port4

Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port8

Lane 1~4 Lane 5 Lane 6

USB3.0

Right side 1 Left side (power share) Caldera

USB2.0

Right side 1 Left side (power share) Caldera

Touch screen Camera ELC BT

PCI EXPRESS

MUX for dGPU & Caldera WLAN(M.2 Card) 10/100/1000 LAN

Symbol Note :

: means Digital Ground

: means Analog Ground

CLOCK SIGNAL CLKOUT_PCIE0 CLKOUT_PCIE1 CLKOUT_PCIE2 CLKOUT_PCIE3 CLKOUT_PCIE4 CLKOUT_PCIE5

Lane 7~8 Lane 9~10

N16P-GX +Caldera

Lane 11~12

M.2 Card WLAN+BT Giga LAN M.2 NGFF SSD

SATA1

Thunderbolt

SATA2

M.2 NGFF SSD

SATA3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

M.2 SATA+PCIeX2 Alpine Ridge SP M.2 SATA+PCIeX2

SATA

HDD or SSD1SATA0 SSD2 SSD2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Notes list

Notes list LA-C901P

LA-C901P

4 63Tuesday, August 04, 2015

1.0

D D

MEM_SMBCLK

MEM_SMBDATA

SKYLAKE ULT

C C

R9 W2

W3 V3

79 80

SOC_SML0CLK SOC_SML0DATA

SOC_SML1CLK

EC_SMB_CK2 EC_SMB_DA2

2.2K

+3V_PRIM

N-MOS N-MOS

+3VS

CLK BUFFER

11 10

+3V_PRIM

N-MOS N-MOS

EC_SMB_CK2 EC_SMB_DA2SOC_SML1DATA

+3VS

KBC

B B

KB9022QD

77 78

EC_SMB_CK1 EC_SMB_DA1

2.2K

+3VALW_EC

10K

SOC_SMBCLK SOC_SMBDATA

N-MOS N-MOS

UF18

UF28

UF3

(On SSD/B)

0 ohm 0 ohm

+3VS

VGA_SMB_CK2 VGA_SMB_DA2T4T3

SMBUS Address [0x98]

SMBUS Address [0x9A]

SMBUS Address [0X98]

SCL SDA

1.8K

12 11

PU700 Charger

+3VS_VGA

UV1 GPU

SMBUS Address [0x12]

DIMMA

202 200

DIMMB

202 200

FFS

4 6

SMBUS Address [0x9E]

SMBUS Address [0x00]

SMBUS Address [0x01]

SMBUS Address [0x1D]

100 ohm 100 ohm

CLK_SMB DAT_SMB

EC_SMB_CK1 50 EC_SMB_DA1

0 ohm

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0 ohm

TBTA_I2C_SCL1_R B5 TBTA_I2C_SDA1_R

2015/01/06 2016/01/06

PBATT1

7 6

PCI-E Re-Driver

Power Deliver

Compal Secret Data

Deciphered Date

SMBUS Address [0x16]

SMBUS Address [RX:0xB2 / TX:0xB6]

SMBUS Address [0x70]

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SMBus block diagram

LA-C901P

1.0

5 63Tuesday, August 04, 2015

UC1

S IC A31 FJ8066201924932 QHMG C0 1.6G

SA00008M30L

1.6GES@

UC1

I5-6200U I7-6500U

1 1

S IC A31 FJ8066201930409 QJ8N D0 2.3G

SA000092O0L

i5QS@

UC1

I5-6200U I7-6500U

S IC A31 FJ8066201930409 QJKP D1 2.3G

SA000092O1L

i5QS'@

UC1

I5-6200U I7-6500U

S IC FJ8066201930409 SR2EY D1 2.3G A31!

SA000092O3L

i5R3@

+3VS

2 2

For BIOS Verify UMA/DIS SKU

1 2

RC212 10K_0402_5%

1 2

RC213 10K_0402_5%

UMA@ DIS@

DGPU_PRSNT#

GPP_E15

DIS,Optimus

UMA

UC1

S IC A31 FJ8066201924925 QHMF C0 2.3G

SA00008M40L

2.3GES@

UC1

S IC A31 FJ8066201930408 QJ8L D0 2.5G

SA000092P0L

i7QS@

UC1

S IC A31 FJ8066201930408 QJKK D1 2.5G

SA000092P1L

i7QS'@

UC1

S IC FJ8066201930408 SR2EZ D1 2.5G A31!

SA000092P3L

i7R3@

Pull High at TBT side

+1.0V_VCCST

+1.0VS_VCCSTG

DGPU_PRSNT#

0 1

Thunderbolt

+1.0VS_VCCIO

CAD note: Trace width=20 mils,Spacing=25mil,Max length=100mils

1 2

RC2 1K_0402_5%

1 2

RC3 1K_0402_5%

H_THERMTRIP#

H_PROCHOT#

RC1

SOC_DP1_CTRL_CLK<44> SOC_DP1_CTRL_DATA<44>

SOC_DP2_CTRL_CLK<44> SOC_DP2_CTRL_DATA<44>

1 2

SOC_DP1_N0<44> SOC_DP1_P0<44> SOC_DP1_N1<44> SOC_DP1_P1<44> SOC_DP1_N2<44> SOC_DP1_P2<44> SOC_DP1_N3<44> SOC_DP1_P3<44>

SOC_DP2_N0<44> SOC_DP2_P0<44> SOC_DP2_N1<44> SOC_DP2_P1<44> SOC_DP2_N2<44> SOC_DP2_P2<44> SOC_DP2_N3<44> SOC_DP2_P3<44>

24.9_0402_1%

H_PROCHOT#<41,51,52>

RC5 49.9_0402_1% RC6 49.9_0402_1% RC7 49.9_0402_1% RC8 49.9_0402_1%

SOC_DP1_CTRL_CLK SOC_DP1_CTRL_DATA

SOC_DP2_CTRL_CLK SOC_DP2_CTRL_DATA

EDP_COMP

T26 TP@

H_PECI<41>

1 2

RC4 499_0402_1%

T25 TP@ T16 TP@

T19 TP@ T10 TP@ T11 TP@

TS_INT# is not Used at Echo

PCH_TP_INT#<41>

T40 TP@

12 12 12 12

UC1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

GPP_E20/DDPC_CTRLCLK

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22

N12

GPP_E23

E52

EDP_RCOMP

H_CATERR# H_PECI H_PROCHOT#_R H_THERMTRIP# SOC_OCC#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3

DGPU_PRSNT# PCH_TP_INT#

SOC_GPIOB4

CPU_POPIRCOMP PCH_OPIRCOMP EDRAM_OPIO_RCOMP EOPIO_RCOMP

AT16 AU16

UC1D

D63 A54 C65 C63 A65

C55 D55 B54 C56

A7 BA5 AY5

H66 H65

SKL-U

DDI

DISPLAY SIDEBANDS

1 OF 20

CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#

CPU MISC

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

EDP

SKL-U

4 OF 20

Rev_1.0

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP

RSVD

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

RSVD

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

L-U_BGA1356@

Rev_1.0

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

JTAGX

L-U_BGA1356@

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52 G50

F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

EDP_DISP_UTIL

SOC_DP1_HPD SOC_DP2_HPD HDMI_HPD EC_SCI# EDP_HPD

EDP_BKLTEN EDP_BKLT_PWM EDP_VDDEN

CPU_XDP_TCK0 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST#

PCH_JTAG_TCK1 SOC_XDP_TDI

SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST# CPU_XDP_TCK0

EDP_TXN0 <20> EDP_TXP0 <20> EDP_TXN1 <20> EDP_TXP1 <20>

EDP_AUXN <20> EDP_AUXP <20>

T9TP@

SOC_DP1_AUXN <44> SOC_DP1_AUXP <44> SOC_DP2_AUXN <44> SOC_DP2_AUXP <44>

T7TP@ T8TP@

SOC_DP1_HPD <44> SOC_DP2_HPD <44> HDMI_HPD <21> EC_SCI# <41> EDP_HPD <20>

EDP_BKLTEN <41> EDP_VDDEN <20>

SOC_XDP_TDO SOC_XDP_TDI SOC_XDP_TRST# CPU_XDP_TCK0

SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TRST# CPU_XDP_TCK0

eDP_FHD>

Thunderbolt

From dGPU

From eDP

RC10 0_0402_5%

As Short As Possible

1 2 1 2

CC64 0.1U_0402_16V7K@ESD@

1 2

CC65 0.1U_0402_16V7K@ESD@

1 2

CC69 0.1U_0402_16V7K@ESD@ CC70 0.1U_0402_16V7K@ESD@

EDP_TXN2 <20> EDP_TXP2 <20> EDP_TXN3 <20> EDP_TXP3 <20>

EDP_BIA_PWM <20>

EC_SCI# EDP_HPD EDP_VDDEN

RPC16

1 8 2 7 3 6 4 5

100K_8P4R_5%

<eDP_4K2K>

+3VS

+3V_PRIM

Change from +3VALW to +3V_PRIM to fix leakage on S5

APS CONN

3 3

PM_SLP_S3#<10,13,37,41> PM_SLP_S5#<10,37,41>

PM_SLP_S4#<10,13,37,41,54> PM_SLP_A#<10>

SOC_RTCRST#_R<10>

PBTN_OUT#<10,41> SYS_RESET#<10> PM_SLP_S0#<10,41>

4 4

+3VALW +3V_PRIM

JAPS1

1 2 3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19 20

ACES_50506-01841-P01

CONN@

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 GND GND

+1.0VS_VCCSTG

RC11 51_0402_5%CMC@ RC13 51_0402_5%CMC@ RC15 51_0402_5%CMC@

+1.0V_XDP

RC31 1K_0402_5%CMC@

RC32 1K_0402_5%@ RC43 0_0402_5%@ RC46 0_0402_5%@

RC35 51_0402_1%CMC@ RC37 51_0402_5%@

Place to CPU side

12 12 12

1 2 1 2

12 12

Place to CPU side

SOC_XDP_TMS SOC_XDP_TDI SOC_XDP_TDO

XDP_ITP_PMODE CFG0 XDP_PRSENT_CPU XDP_PRSENT_PCH

CPU_XDP_TCK0 PCH_JTAG_TCK1

XDP_SPI_IO2<8>

XDP_SPI_SI<8> XDP_ITP_PMODE<17>

EC_RSMRST#<10,41>

1 2

RC9 1K_0402_5%

SOC_XDP_TDO XDP_TDO SOC_XDP_TDI XDP_TDI SOC_XDP_TMS XDP_TMS CPU_XDP_TCK0 XDP_TCK0

SOC_XDP_TRST# PCH_JTAG_TCK1 CFG3 XDP_PRSENT_CPU XDP_SPI_IO2 XDP_PRSENT_PCH

XDP_SPI_SI XDP_ITP_PMODE

RC158 1K_0402_5%

CFG4

RC193 1K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RPC2

1 8 2 7 3 6 4 5

0_0804_8P4R_5%

RPC4

1 8 2 7 3 6 4 5

0_0804_8P4R_5%

RPC15

1 8 2 7 3 6 4 5

0_0804_8P4R_5%

1 2

CMC@

1 2

XDP_SPI_SI

CFG0<17> CFG1<17> CFG2<17> CFG3<17>

XDP_TRST#

XDP_TCK1

XDP_HOOK3 XDP_HOOK6

XDP_HOOK0EC_RSMRST#

2015/01/06 2016/01/06

CFG4<17> CFG5<17> CFG6<17> CFG7<17>

CFG17<17> CFG16<17>

CFG8<17>

CFG9<17> CFG10<17> CFG11<17> CFG12<17> CFG13<17> CFG14<17> CFG15<17>

CFG19<17> CFG18<17>

Compal Secret Data

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7

CFG17 CFG16

CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG19 CFG18

Deciphered Date

PRIMARY CMC CONN

+1.0V_XDP+1.0V_PRIM

1 2

RC12 0_0603_1%@

T37TP@ T38TP@

T47TP@ T48TP@ T49TP@

T50TP@ T51TP@

T52TP@ T53TP@ T54TP@ T55TP@ T56TP@ T57TP@ T58TP@ T59TP@

T60TP@ T61TP@

Title

Size Document Number Rev

Date: Sheet

T13 TP@ T20 TP@ T21 TP@ T24 TP@ T27 TP@ T28 TP@

T29 TP@ T30 TP@

T31 TP@ T32 TP@ T33 TP@

Compal Electronics, Inc.

SKL-U(1/12)DDI,MSIC,XDP,EDP

XDP_TRST# XDP_TDI XDP_TMS XDP_TCK0 XDP_TCK1 XDP_TDO

XDP_PREQ# XDP_PRDY#

XDP_HOOK0 XDP_HOOK3 XDP_HOOK6

LA-C901P

XDP_PREQ# <12> XDP_PRDY# <12>

6 63Tuesday, August 04, 2015

1.0

Non-Interleaved Memory

D D

DDR_A_D[0..15]<18>

DDR_A_D[32..47]<18>

C C

DDR_B_D[0..15]<19>

DDR_B_D[32..47]<19>

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47

UC1B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

Interleave / Non-Interleaved

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKL-U

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR3L / LPDDR3 / DDR4

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

Interleave / Non-Interleaved

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_ALERT#

DDR CH - A

2 OF 20

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

Rev_1.0

DDR0_MA[3] DDR0_MA[4]

DDR0_PAR

L-U_BGA1356@

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54 AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50

BA50 BB52 AM70 AM69 AT69 AT70

BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26

AW50 AT52

AY67 AY68 BA67

AW67

DDR_A_CLK#0 DDR_A_CLK0 DDR_A_CLK#1 DDR_A_CLK1

DDR_A_CKE0 DDR_A_CKE1

DDR_A_CS#0 DDR_A_CS#1 DDR_A_ODT0 DDR_A_ODT1

DDR_A_MA5 DDR_A_MA9 DDR_A_MA6 DDR_A_MA8 DDR_A_MA7 DDR_A_BS2 DDR_A_MA12 DDR_A_MA11 DDR_A_MA15 DDR_A_MA14 DDR_A_MA13 DDR_A_CAS# DDR_A_WE# DDR_A_RAS# DDR_A_BS0 DDR_A_MA2 DDR_A_BS1 DDR_A_MA10 DDR_A_MA1 DDR_A_MA0

DDR_A_MA3 DDR_A_MA4 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1

DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5

+0.675V_VREFCA +0.675V_A_VREFDQ +0.675V_B_VREFDQ

T14TP@

T22TP@

+0.675V_VREFCA +0.675V_A_VREFDQ +0.675V_B_VREFDQ

DDR_A_CLK#0 <18> DDR_A_CLK0 <18> DDR_A_CLK#1 <18> DDR_A_CLK1 <18>

DDR_A_CKE0 <18> DDR_A_CKE1 <18>

DDR_A_CS#0 <18> DDR_A_CS#1 <18> DDR_A_ODT0 <18> DDR_A_ODT1 <18>

DDR_A_MA5 <18> DDR_A_MA9 <18> DDR_A_MA6 <18> DDR_A_MA8 <18> DDR_A_MA7 <18> DDR_A_BS2 <18> DDR_A_MA12 <18> DDR_A_MA11 <18> DDR_A_MA15 <18> DDR_A_MA14 <18> DDR_A_MA13 <18> DDR_A_CAS# <18> DDR_A_WE# <18> DDR_A_RAS# <18> DDR_A_BS0 <18> DDR_A_MA2 <18> DDR_A_BS1 <18> DDR_A_MA10 <18> DDR_A_MA1 <18> DDR_A_MA0 <18>

DDR_A_MA3 <18> DDR_A_MA4 <18> DDR_A_DQS#0 <18> DDR_A_DQS0 <18> DDR_A_DQS#1 <18> DDR_A_DQS1 <18>

DDR_A_DQS#4 <18> DDR_A_DQS4 <18> DDR_A_DQS#5 <18> DDR_A_DQS5 <18> DDR_B_DQS#0 <19> DDR_B_DQS0 <19> DDR_B_DQS#1 <19> DDR_B_DQS1 <19> DDR_B_DQS#4 <19> DDR_B_DQS4 <19> DDR_B_DQS#5 <19> DDR_B_DQS5 <19>

DDR_A_D[16..31]<18>

DDR_A_D[48..63]<18>

DDR_B_D[16..31]<19>

DDR_B_D[48..63]<19>

Trace width/Spacing >= 20mils

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31

DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

UC1C

Interleave / Non-Interleaved

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKL-U

DDR3L / LPDDR3 / DDR4

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

Interleave / Non-Interleaved

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

3 OF 20

Rev_1.0

DDR1_CKN[0] DDR1_CKN[1]

DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6]

DDR1_DQSP[6]

DDR1_DQSN[7]

DDR1_DQSP[7] DDR1_ALERT#

DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

L-U_BGA1356@

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52 BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46

BB46 BA47

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32

AR25 AR27 AR22 AR21 AN43 AP43 AT13 AR18 AT18 AU18

DDR_B_CLK#0 DDR_B_CLK#1 DDR_B_CLK0 DDR_B_CLK1

DDR_B_CKE0 DDR_B_CKE1

DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0 DDR_B_ODT1

DDR_B_MA5 DDR_B_MA9 DDR_B_MA6 DDR_B_MA8 DDR_B_MA7 DDR_B_BS2 DDR_B_MA12 DDR_B_MA11 DDR_B_MA15 DDR_B_MA14 DDR_B_MA13 DDR_B_CAS# DDR_B_WE# DDR_B_RAS# DDR_B_BS0 DDR_B_MA2 DDR_B_BS1 DDR_B_MA10 DDR_B_MA1 DDR_B_MA0

DDR_B_MA3 DDR_B_MA4

DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3

DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7

DDR_DRAMRST #

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

DDR_B_CLK#0 <19> DDR_B_CLK#1 <19> DDR_B_CLK0 <19> DDR_B_CLK1 <19>

DDR_B_CKE0 <19>

DDR_B_CKE1 <19>

T17TP@ T18TP@T15TP@

DDR_B_CS#0 <19>

DDR_B_CS#1 <19>

DDR_B_ODT0 <19>

DDR_B_ODT1 <19>

DDR_B_MA5 <19>

DDR_B_MA9 <19>

DDR_B_MA6 <19>

DDR_B_MA8 <19>

DDR_B_MA7 <19>

DDR_B_BS2 <19>

DDR_B_MA12 <19>

DDR_B_MA11 <19>

DDR_B_MA15 <19>

DDR_B_MA14 <19>

DDR_B_MA13 <19>

DDR_B_CAS# <19>

DDR_B_WE# <19>

DDR_B_RAS# <19>

DDR_B_BS0 <19>

DDR_B_MA2 <19>

DDR_B_BS1 <19>

DDR_B_MA10 <19>

DDR_B_MA1 <19>

DDR_B_MA0 <19>

DDR_B_MA3 <19>

DDR_B_MA4 <19>

DDR_A_DQS#2 <18>

DDR_A_DQS2 <18>

DDR_A_DQS#3 <18>

DDR_A_DQS3 <18>

DDR_A_DQS#6 <18>

DDR_A_DQS6 <18>

DDR_A_DQS#7 <18>

DDR_A_DQS7 <18>

DDR_B_DQS#2 <19>

DDR_B_DQS2 <19>

DDR_B_DQS#3 <19>

DDR_B_DQS3 <19>

DDR_B_DQS#6 <19>

DDR_B_DQS6 <19>

DDR_B_DQS#7 <19>

DDR_B_DQS7 <19>

T23TP@

DDR_DRAMRST # <18,19>

1 2

RC38 121_0402_1%

1 2

RC39 80.6_0402_1%

1 2

RC40 100_0402_1%

Buffer with Open Drain Output

For VTT power control

+3VALW

+1.35V_VDDQ +3VS

DDR_PG_CTRL

CC570.1U_0201_10V6K

UC7

NC1VCC

GND

74AUP1G07GW_TSSOP5

RC123

100K_0402_5%

RC129

100K_0402_5%

0.675V_DDR_VTT_ON <54>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Custom Date: Sheet

Date: Sheet

SKL-U(2/12)DDRIII

LA-C901P

Tuesday, August 04, 2015

1.0

SOC_SMBALERT# SOC_SML0ALERT#

TLS CONFIDENTIALITY

HIGH LOW(DEFAULT)

UC1E

AV2

SPI0_CLK

AW3

SPI0_MISO

AV3

SPI0_MOSI

AW2

SPI0_IO2

AU4

SPI0_IO3

AU3

SPI0_CS0#

AU2

SPI0_CS1#

AU1

SPI0_CS2#

GPP_D1/SPI1_CLK

GPP_D2/SPI1_MISO

GPP_D3/SPI1_MOSI

GPP_D21/SPI1_IO2

GPP_D22/SPI1_IO3

GPP_D0/SPI1_CS#

CL_CLK

CL_DATA

CL_RST#

AW13

GPP_A0/RCIN#

AY11

GPP_A6/SERIRQ

CMC@ CMC@

O2 pin for CMC

12 12

SOC_SPI_CLK SOC_SPI_SO SOC_SPI_SI SOC_SPI_IO2 SOC_SPI_IO3 SOC_SPI_CS#0 SOC_SPI_CS#1

FFS_INT1 FFS_INT2

EC_KBRST# SERIRQ

SERIRQ

SOC_SPI_SI SOC_SPI_IO2

C21/44 place to within 1100 mil of SPIO_MOSI/SPI0_I

XDP_SPI_SI<6> XDP_SPI_IO2<6>

+3VS

D D

RC32410K_0402_5% RC32510K_0402_5% RC32610K_0402_5% @

C C

+3VS

LPC Mode

12 12 12

FFS_INT2 FFS_INT1 EC_KBRST#

RC44 1K_0402_1% RC21 1K_0402_1%

T41 TP@

FFS_INT1<36> FFS_INT2<36>

T42 TP@ T43 TP@ T44 TP@

EC_KBRST#<41>

SERIRQ<41>

RC1228.2K_0402_5%

Follow 543016_SKL_U_Y_PDG_0_9

B B

SPI - FLASH

SPI - TOUCH

C LINK

EC interface

ENABLE DISABLE

SKL-U

LPC

5 OF 20

HIGH LOW(DEFAULT)

SMBUS, SMLINK

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

ESPI LPC

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

MEM_SMBCLK

MEM_SMBDATA

----->For KB9032 Only.

----->For KB9022/9032 Use

Rev_1.0

MEM_SMBCLK

MEM_SMBDATA

R10

SOC_SMBALERT#

SOC_SML0CLK

SOC_SML0DATA

SOC_SML0ALERT#

SOC_SML1CLK

SOC_SML1DATA

AM7

SOC_SML1ALERT# SOC_SML1ALERT#

AY13

ESPI_IO0

BA13

ESPI_IO1

BB13

ESPI_IO2

AY12

ESPI_IO3

BA12

ESPI_CS#

BA11

SUS_STAT#

AW9

ESPI_CLK

AY9 AW11

PM_CLKRUN#

L-U_BGA1356@

SMB Bus : DDR/WLAN/FFS

6 1

DMN66D0LDW-7_SOT363-6

3 4

SGD

QC3A

DMN66D0LDW-7_SOT363-6

LPC@

1 2

RC45 22_0402_5%

RC66

10K_0402_5%

QC3B

SML1 Bus : EC/dGPU/THERMAL

SOC_SML1CLK

SOC_SML1DATA

SMB -> DDR , WLAN , FFS SML0 -> PCIE CLK BUFFER

SOC_SML0CLK <34> SOC_SML0DATA <34>

RC202 4.7K_0402_5%

SML1 -> EC , dGPU , THERMAL , TBT

To EC

ESPI_CS# <41>

ESPI_CLK_R <41>

PM_CLKRUN# <41>

SUS_STAT#

+3VS+3VS

RC67 10K_0402_5%

SOC_SMBCLK <18,19,36>

SOC_SMBDATA <18,19,36>

SOC_SMBALERT#

MEM_SMBCLK MEM_SMBDATA SOC_SML1CLK SOC_SML1DATA

ESPI_IO0 ESPI_IO0_R ESPI_IO2 ESPI_IO2_R ESPI_IO1 ESPI_IO1_R ESPI_IO3

To EC

For TPM

1 2

RC36 10K_0402_5%

+3VS

6 1

QC2B

DMN66D0LDW-7_SOT363-6

1 2

RC130 8.2K_0402_5%

RPC12

1 8 2 7 3 6 4 5

1K_0804_8P4R_5%

RPC8

1 8 2 7 3 6 4 5

ESPI_IO3_R

0_0804_8P4R_5%

LPC@

+3V_PRIM

*****ONLY***** From WW36 MOW for SKL-U ES sample

3 4

SGD

QC2A

DMN66D0LDW-7_SOT363-6

+3V_PRIM

ESPI_IO0_R <41> ESPI_IO2_R <41> ESPI_IO1_R <41> ESPI_IO3_R <41>

RC45

15_0402_5%

ESPI@

EC_SMB_CK2 <22,40,41,46>

EC_SMB_DA2 <22,40,41,46>

1 2

RC41 150K_0402_1%@

ESPI / LPC Bus

ESPI : +1.8V LPC : +3.3V

RPC8

15_0804_8P4R_5%

ESPI@

Echo MLK use LPC

Reserve For EC Auto Load Code

SOC_SPI_IO2 SOC_SPI_IO3 SOC_SPI_CS#0 SOC_SPI_IO3

PM_CLKRUN#

1 2

RC47 1K_0402_1%@

1 2

RC48 1K_0402_1%@

1 2

RC53 1K_0402_1%@

1 2

RC51 1K_0402_1%@

1 2

RC107 8.2K_0402_5%

Follow TD team

+3VS

+3V_SPI

+3VS

Single SPI ROM_CS0#

To SPI ROM

A A

RPC5 and RC52 are close UC2

RPC5

1 8 2 7 3 6 4 5

SOC_SPI_SOSOC_SPI_SO_0_R SOC_SPI_SISOC_SPI_SI_0_R SOC_SPI_CLKSOC_SPI_CLK_0_R SOC_SPI_IO3SOC_SPI_IO3_0_R

15_0804_8P4R_5%

RC52

SOC_SPI_IO2SOC_SPI_IO2_0_R

15_0402_5%

16M SPI ROM(Support ISH)

UC2

SOC_SPI_CS#0 SOC_SPI_IO2_0_R

/CS

DO(IO1)

3 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

/HOLD(IO3) /WP(IO2) GND

W25Q128FVSIQ_SO8

+3V_SPI

1 2

CC8 0.1U_0201_10V6K

VCC

SOC_SPI_IO3_0_RSOC_SPI_SO_0_R

SOC_SPI_CLK_0_R

CLK

DI(IO0)

SOC_SPI_SI_0_R

2015/01/06 2016/01/06

1 2

CC9 10P_0402_50V8J

@EMI@

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(3/12)SPI,ESPI,SMB,LPC

Size Document Number Rev

LA-C901P

Date: Sheet

8 63Tuesday, August 04, 2015

1.0

#545659 SKL_PCH_EDS_R0.7 P.84

HDA for AUDIO

RPC9

CC53

UC1I

CSI-2

CSI2_DN0 CSI2_DP0 CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3

CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7

CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11

1 8 2 7 3 6 4 5

D D

HDA_BIT_CLK_R<31> HDA_RST#_R<31> HDA_SDOUT_R<31> HDA_SYNC_R<31>

HDA_SDIN0<31>

Functional Strap Definitions

SPKR / GPP_B14 (Internal Pull Down): (Sampled:Rising edge of PCH_PWROK)

TOP Swap Override 0 = Disable TOP Swap mode. -->AAX05 use 1 = Enable TOP Swap Mode.

TOP Swap Override

C C

+3VS

1 2

RC117 2.2K_0402_5%@

B B

SPKR

22P_0402_50V8J

Close to RPC9

A36 B36 C38 D38 C36 D36 A38 B38

C31 D31 C33 D33 A31 B31 A33 B33

A29 B29 C28 D28 A27 B27 C27 D27

HDA_BIT_CLK HDA_RST# HDA_SDOUT HDA_SYNC

33_0804_8P4R_5%

HDA_SDIN0

HDA_BIT_CLK_R

SKL-U

9 OF 20

SPKR<31>

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F12/EMMC_CMD

HDA_SYNC HDA_BIT_CLK HDA_SDOUT HDA_SDIN0

HDA_RST#

SPKR

Rev_1.0

CSI2_CLKN0

CSI2_CLKP0

CSI2_CLKN1

CSI2_CLKP1

CSI2_CLKN2

CSI2_CLKP2

CSI2_CLKN3

CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

GPP_F22/EMMC_CLK

EMMC_RCOMP

L-U_BGA1356@

To Enable ME Override

TD Team Solution A

+3V_PRIM

C37 D37 C32 D32 C29 D29 B26 A26

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

UC1G

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0

GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

1 2

RC77 1K_0402_1%

CSI2_COMP

EMMC_RCOMP

RC80 100_0402_1%

RC89 200_0402_1%

AUDIO

ME_EN<9,41>

SKL-U

GPP_A17/SD_PWR_EN#/ISH_GP7

7 OF 20

eserve RC229 follow TD team dat.04/23

1 2

RC229 100K_0402_5%

1 3

QC1 BSS138W -7-F_SOT323-3

HDA_SDOUT

Rev_1.0

SDIO / SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

L-U_BGA1356@

BO Solution

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

SD_RCOMP

AF13

ME_EN<9,41>

RC76 200_0402_1%

1 2

RC313 0_0402_5%

HDA_SDOUT

A A

Security Classification

2015/01/06 2016/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(4/12)HDA,EMMC,SDIO,CSI2

Size Document Number Rev

LA-C901P

Date: Sheet

Tuesday, August 04, 2015

1.0

DGPU

NGFF WALN+BT

D D

LAN

FF SSD

Thunderbolt

NGFF SSD

+3VS

1 2

RC105 10K_0402_5%

RPC10

18 27

C C

From 545659_SKL_PCH_U_Y_EDS_R0_7

+3VALW _DSW

+3V_PRIM

CLRP3 SHORT PADS RC101 100K_0402_5%

+3VALW _DSW

B B

RC108 10K_0402_5%

36 45

10K_0804_8P4R_5%

RPC11

18 27 36 45

10K_0804_8P4R_5%

1 2

CLKREQ_PCIE#5

CLKREQ_PCIE#1 CLKREQ_PCIE#2 CLKREQ_PCIE#3 CLKREQ_PCIE#0

From 543016_SKL_PDG_UY_v1.0

PCH_PW ROK

LAN_WAKE#

EC_RSMRST#

SYS_RESET#

SYS_RESET# PCH_DPW ROK

WAKE_PCH#_R

CLK_PCIE_N0<34> CLK_PCIE_P0<34>

CLKREQ_PCIE#0<22,34> CLK_PCIE_N1<32>

CLK_PCIE_P1<32> CLKREQ_PCIE#1<32>

CLK_PCIE_N2<30> CLK_PCIE_P2<30> CLKREQ_PCIE#2<30>

CLK_PCIE_N3<36> CLK_PCIE_P3<36>

CLKREQ_PCIE#3<36>

CLK_PCIE_N4<44> CLK_PCIE_P4<44>

CLKREQ_PCIE#4<44>

CLK_PCIE_N5<36> CLK_PCIE_P5<36>

CLKREQ_PCIE#5<36>

XCLK_BIASREF

Follow 546765_2014WW48_Skylake_MOW_Rev_1_0 Stuff 2.7k ohm(RC96) PH for Skylake U Stuff 60.4 ohm(RC124) PD for Cannonlake U

EC_VCCST_PG H_CPUPWRGD SYS_RESET#

H_CPUPW RGD SYS_RESET#

100P_0402_50V8J

@ESD@

A A

VR_ON_EC<41>

For meet tPLT17 & tCPU28 power down sequence. tPLT17 : 1us (Max) tCPU28 : 1us (Max)

CC60

0.1U_0201_10V6K

PM_SLP_S3#

As Short As Possible

CC63

0.1U_0402_16V7K

@ESD@

+3V_PRIM

CC83

1 2

UC9

TC7SH08FU_SSOP5~D

1 2

RC127 0_0402_5%

SYS_RESET#<6>

EC_RSMRST#<6,41>

T95 TP@

Only For Power Sequence Debug

SYS_PWROK<41>

PCH_PW ROK<41>

DPWROK_EC<41>

SUSWARN#<41>

SUSACK#<41>

WAKE_PCH#<41>

VR_ON <58>

H_CPUPW RGD_R

EC_RSMRST#

1K_0402_5%

VCCST_PG_EC<41>

UC1J

CLK_PCIE_N0 CLK_PCIE_P0

CLKREQ_PCIE#0

CLK_PCIE_N1 CLK_PCIE_P1

CLKREQ_PCIE#1

CLK_PCIE_N2 CLK_PCIE_P2

CLKREQ_PCIE#2

CLK_PCIE_N3 CLK_PCIE_P3

CLKREQ_PCIE#3

CLK_PCIE_N4 CLK_PCIE_P4

CLKREQ_PCIE#4

CLK_PCIE_N5 CLK_PCIE_P5

CLKREQ_PCIE#5

RC102 1K_0402_5%@

RC112 0_0402_1% RC114 0_0402_5%

RC110 0_0402_1% RC100 1K_0402_5% RC68 0_0402_1%

+1.0V_VCCST

RC113

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

1 2

RC96 2.7K_0402_1%

1 2

RC124 60.4_0402_1%@

1 2

From EC(open-drain)

RC116

1 2

60.4_0402_1%

EC_VCCST_PG

CC54 100P_0402_50V8J

@ESD@

SKL-U

CLOCK SIGNALS

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

10 OF 20

+1.0V_CLK5_F24NS

SOC_SRTCRST#

CLR ME

SOC_RTCRST#

SM_INTRUDER#

PCH PLTRST Buffer

SOC_PLTRST#<22,34>

SOC_PLTRST# SYS_RESET# EC_RSMRST#

H_CPUPW RGD EC_VCCST_PG

SYS_PWROK PCH_PW ROK PCH_DPW ROK

SUSWARN# SUSACK#_R

WAKE_PCH#_R LAN_WAKE#

T92 TP@ T94 TP@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SOC_PLTRST#

RC99 0_0402_5%@

UC1K

AN10

GPP_B13/PLTRST#

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SYSTEM POWER MANAGEMENT

Rev_1.0

F43

CLK_CPU_ITP#

E43

CLK_CPU_ITP

BA17

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

L-U_BGA1356@

R CMOS

+3VS

UC3

TC7SH08FU_SSOP5~D

1 2

2015/01/06 2016/01/06

SUSCLK

E37

SOC_XTAL24_IN

E35

SOC_XTAL24_OUT

E42

XCLK_BIASREF

AM18

SOC_RTCX1

AM20

SOC_RTCX2

AN18

SOC_SRTCRST#

AM16

SOC_RTCRST#

CC14

1 2

0.1U_0201_10V6K

SKL-U

11 OF 20

Compal Secret Data

RC104 0_0201_1%

12 12 12

CLRP1SHORT PADS

12 12 12

CLRP2SHORT PADS

RC941M_0402_5%

GPP_B11/EXT_PWR_GATE#

Deciphered Date

T89TP@ T90TP@

SUSCLK <32,36>

1 2

+3VL_RTC

RC9120K_0402_5% CC101U_0402_6.3V6K

RC9320K_0402_5% CC111U_0402_6.3V6K

PLT_RST# <30,32,36,41,44>

Rev_1.0

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B2/VRALERT#

L-U_BGA1356@

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

AM10 AM11

**Avoid Sub-trace**

Closed to CPU

SOC_XTAL24_IN

SOC_XTAL24_OUT

SOC_RTCRST#_R <6>

Closed to CPU

SOC_RTCX2

SOC_RTCX1

PM_SLP_S0# PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#

SLP_SUS# SLP_LAN# SLP_WLAN# PM_SLP_A#

PBTN_OUT#_R AC_PRESENT_R PM_BATLOW#

SM_INTRUDER# EXT_PW R_GATE#

SOC_VRALERT#

RC109 0_0402_1%@

XTAL@

GND

1 2

CC13

YC1

XTAL@

24MHZ_12PF_7V24000020

XTAL@

1 2

CC1215P_0402_50V8J

RC92

1M_0402_5%

XTAL@

15P_0402_50V8J

1 2

**Avoid Sub-trace**

XTAL@

1 2

CC164.7P_0402_50V8C

RC98

10M_0402_5%

XTAL@

SOC_VRALERT#

PM_BATLOW# AC_PRESENT_R PBTN_OUT#_R

T87

TP@

T88TP@

1 2

DC2 RB751V-40_SOD323-2

T91

TP@

Compal Electronics, Inc.

Title

SKL-U(5/12)CLK,GPIO

Size Document Number Rev

LA-C901P

Date: Sheet

YC2

32.768KHZ 9PF 20PPM 9H03280012

1 2

XTAL@

1 2

CC154.7P_0402_50V8C

XTAL@

RC11510K_0402_5% @

+3VALW _DSW

RC1038.2K_0402_5%

1 2

RC10610K_0402_5% RC111100K_0402_5% @

PM_SLP_S0# <6,41> PM_SLP_S3# <6,13,37,41> PM_SLP_S4# <6,13,37,41,54> PM_SLP_S5# <6,37,41>

SLP_SUS# <14,41>

PM_SLP_A# <6>

PBTN_OUT# <6,41> ACIN <22,37,41,51,52> PM_BATLOW# <44>

EXT_PW R_GATE# <14>

+3V_PRIM

Follow Echo

10 63Tuesday, August 04, 2015

1.0

+3VS

RC203 10K_0402_5% RC205 10K_0402_5%

RC62 49.9K_0402_1% RC63 49.9K_0402_1%

D D

RC126 8.2K_0402_5%

C C

12 12

RPC7

I2C_1_SDA

I2C_1_SCL

I2C_0_SDA

I2C_0_SCL

10K_0804_8P4R_5%

WL_OFF#

PD_PWR_EN<41,46>

C10 for GC6_EVENT#

nsor

Touch PAD/Panel

SOC_GPIOB21 EC_SMI#

UART_2_CRXD_DTXD UART_2_CTXD_DRXD

Echo13

RTD3_CIO_PWR_EN<44> RTD3_USB_PWR_EN<44>

B17 for GPU_GC6_FB_EN

PCIE_SEL<34>

WL_OFF#<32>

1 2

RC128 0_0201_5%

BT_OFF#<32>

UART_2_CRXD_DTXD<32> UART_2_CTXD_DRXD<32>

EC_SMI#<41>

TBT_CIO_PLUG_EVENT#<44>

I2C_1_SDA<38> I2C_1_SCL<38>

RTD3_CIO_PWR_EN RTD3_USB_PWR_EN SOC_GPIOB17 GSPI0_MOSI

PCIE_SEL SOC_GPIOB21 GSPI1_MOSI

WL_OFF#

PD_PWR_EN_R SOC_GPIOC10 BT_OFF#

UART_2_CRXD_DTXD UART_2_CTXD_DRXD EC_SMI# TBT_CIO_PLUG_EVENT#

I2C_0_SDA I2C_0_SCL

I2C_1_SDA I2C_1_SCL

NFC

Unus

Unused

+3V_PRIM

RC207 100K_0402_5%@

AN8 AP7 AP8 AR7

AM5

AN7 AP5 AN5

AB1 AB2

AB3 AD1

AD2 AD3 AD4

U7 U6

U8 U9

AH9

AH10 AH11

AH12 AF11

AF12

UC1F

GPP_B15/GSPI0_CS# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL

LPSS ISH

RTD3_USB_PWR_EN

SKL-U

VGA_ID

RANK_ID

VGA_ID

GL GM

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6

6 OF 20

GPP_D9

0 1

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_D15/ISH_UART0_RTS#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

+3V_1.8V_PGPPD +3V_1.8V_PGPPD

1 2

RC321 10K_0402_5%@

1 2

RC316 10K_0402_5%

1 2

RC320 10K_0402_5%SR@

1 2

RC317 10K_0402_5%DR@

RANK_ID

DR SR

GPP_D9 GPP_D10 GPP_D11 GPP_D12

L-U_BGA1356@

Rev_1.0

GPP_D10

VGA_ID

RANK_ID

PROJECT_ID0

PROJECT_ID1

ISH_I2C_0_SDA

ISH_I2C_0_SCL

ISH_I2C_1_SDA

ISH_I2C_1_SCL

AD11

I2C_5_SDA

AD12

I2C_5_SCL

SOC_GPIOD13

SOC_GPIOD14

SOC_GPIOD15

SOC_GPIOD16

AC1

DGPU_PW R_EN

AC2

DGPU_HOLD_RST#

AC3

SOC_GPIOC14

AB4

SOC_GPIOC15

AY8

SOC_GPIOA18

BA8

SOC_GPIOA19

BB7

SOC_GPIOA20

BA7

SOC_GPIOA21

AY7

SOC_GPIOA22

AW7

SOC_GPIOA23

AP13

SOC_GPIOA12

0 1

T111 TP@ T112 TP@

T104 TP@ T103 TP@

T105 TP@ T106 TP@

T107 TP@ T108 TP@ T109 TP@ T110 TP@

T254 TP@ T256 TP@

T250 TP@ T251 TP@ T252 TP@ T253 TP@ T255 TP@ T120 TP@ T122 TP@

PROJECT_ID0

PROJECT_ID1

Project ID

Project code Reserved Reserved Reserved

Unused

RC318 10K_0402_5%@ RC315 10K_0402_5%

RC314 10K_0402_5%@ RC319 10K_0402_5%

DGPU_PW R_EN <24> DGPU_HOLD_RST# <22>

1 2

Project_ID0Project_ID1

GPP_D11GPP_D12 0 0 1

0 1 0

1 1

I2C for ISH sensor HUB

B B

Strap Pin

+3VS

RC118 2.2K_0402_5%@ RC201 2.2K_0402_5%@

1 2 1 2

GSPI0_MOSI GSPI1_MOSI

GSPI0_MOSI (Internal Pull Down): No Reboot 0 = Disable No Reboot mode. --> AAX05 Use 1 = Enable No Reboot Mode. (PCH will disable the TCO

Timer system reboot feature). This function is useful when running ITP/XDP.

GSPI1_MOSI (Internal Pull Down):

TO DGPU

Boot BIOS Strap Bit

A A

0 = SPI Mode --> AAX05 Use

ForGC62.0

SOC_GPIOC10 SOC_GPIOB17 GPU_GC6_FB_EN

1 2

RC204 0_0402_1%@

1 2

RC195 0_0402_1%@

GC6_EVENT#

GC6_EVENT# <22> GPU_GC6_FB_EN <22,25>

1 = LPC Mode--> AAP01 Use

Security Classification

2015/01/06 2016/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(6/12)GPIO

Size Document Number Rev

LA-C901P

Date: Sheet

11 63Tuesday, August 04, 2015

1.0

PCIE_CRX_GTX_N1<34> PCIE_CRX_GTX_P1<34>

PCIE_CTX_C_GRX_N1<34> PCIE_CTX_C_GRX_P1<34>

PCIE_CRX_GTX_N2<34> PCIE_CRX_GTX_P2<34>

PCIE_CTX_C_GRX_N2<34>

D D

**** Swap Port **** Follow Customer design (Different with TD Team)

For selected technology

lease use 100nF for PCIe Gen3.

p please use 10nF for SATA.

C C

For selected technology p

lease use 220nF for PCIe Gen3.

please use 10nF for SATA.

ATA Express

SATA Express

DGPU

(x4 Lane)

NGFF WLAN+BT

LAN

HDD

ThunderBolt

PCIE_CTX_C_GRX_P2<34>

PCIE_CRX_GTX_N3<34> PCIE_CRX_GTX_P3<34>

PCIE_CTX_C_GRX_N3<34> PCIE_CTX_C_GRX_P3<34>

PCIE_CRX_GTX_N4<34> PCIE_CRX_GTX_P4<34>

PCIE_CTX_C_GRX_N4<34> PCIE_CTX_C_GRX_P4<34>

PCIE_CRX_DTX_N5<32> PCIE_CRX_DTX_P5<32> PCIE_CTX_DRX_N5<32> PCIE_CTX_DRX_P5<32>

PCIE_CRX_DTX_N6<30> PCIE_CRX_DTX_P6<30> PCIE_CTX_C_DRX_N6<30> PCIE_CTX_C_DRX_P6<30>

SATA_CRX_DTX_N0<36> SATA_CRX_DTX_P0<36> SATA_CTX_DRX_N0<36> SATA_CTX_DRX_P0<36>

SATA_CRX_DTX_N1<36> SATA_CRX_DTX_P1<36> SATA_CTX_DRX_N1<36> SATA_CTX_DRX_P1<36>

PCIE_CRX_DTX_N9<44> PCIE_CRX_DTX_P9<44> PCIE_CTX_DRX_N9<44> PCIE_CTX_DRX_P9<44>

PCIE_CRX_DTX_N10<44> PCIE_CRX_DTX_P10<44> PCIE_CTX_DRX_N10<44> PCIE_CTX_DRX_P10<44>

XDP_PRDY#<6>

XDP_PREQ#<6>

PCIE_CRX_DTX_N11<36> PCIE_CRX_DTX_P11<36> PCIE_CTX_DRX_N11<36> PCIE_CTX_DRX_P11<36> PCIE_CRX_DTX_N12<36> PCIE_CRX_DTX_P12<36> PCIE_CTX_DRX_N12<36> PCIE_CTX_DRX_P12<36>

Follow 545659_SKL_PCH_LP_EDS_Rev1_0

B B

1 2

CC17 0.22U_0402_16V7KDIS@

1 2

CC21 0.22U_0402_16V7KDIS@

1 2

CC18 0.22U_0402_16V7KDIS@

1 2

CC19 0.22U_0402_16V7KDIS@

1 2

CC20 0.22U_0402_16V7KDIS@

1 2

CC22 0.22U_0402_16V7KDIS@

1 2

CC23 0.22U_0402_16V7KDIS@

1 2

CC24 0.22U_0402_16V7KDIS@

1 2

CC25 0.1U_0402_10V7K

1 2

CC26 0.1U_0402_10V7K

1 2

RC120 100_0402_1%

hen PCIE8/SATA1A is used

W as SATA Port 1 (ODD), then PCIE11/SATA1B (M.2 SSD) cannot be used as SATA Port 1.

PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P1 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P1

PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P2

PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P3

PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P4 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P4

PCIE_CRX_DTX_N5 PCIE_CRX_DTX_P5 PCIE_CTX_DRX_N5 PCIE_CTX_DRX_P5

PCIE_CRX_DTX_N6 PCIE_CRX_DTX_P6 PCIE_CTX_DRX_N6 PCIE_CTX_DRX_P6

PCIE_CRX_DTX_N9 PCIE_CRX_DTX_P9 PCIE_CTX_DRX_N9 PCIE_CTX_DRX_P9

PCIE_CRX_DTX_N10 PCIE_CRX_DTX_P10 PCIE_CTX_DRX_N10 PCIE_CTX_DRX_P10

PCIE_RCOMPN PCIE_RCOMPP

XDP_PRDY# XDP_PREQ#

UC1H

PCIE / USB3 / SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

PCIE_RCOMPN

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL-U

USB2

8 OF 20

SSIC / USB3

USB3_2_RXN / SSIC_RXN USB3_2_RXP / SSIC_RXP USB3_2_TXN / SSIC_TXN USB3_2_TXP / SSIC_TXP

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

Rev_1.0

USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_3_RXN USB3_3_RXP USB3_3_TXN USB3_3_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E8/SATALED#

L-U_BGA1356@

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6 AG3 AG4

A9 C9 D9 B9

J1 J2 J3

H2 H3 G4

SATA_GP0

SATA_GP1

TA_GP2

USB20_N1 USB20_P1

USB20_N2 USB20_P2

USB20_N3 USB20_P3

USB20_N5 USB20_P5

USB20_N6 USB20_P6

USB20_N7 USB20_P7

USB20_N8 USB20_P8

USB20_N9 USB20_P9

USB20_N10 USB20_P10

USB2_COMP USB2_ID USB2_VBUSSENSE

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

TBT_FORCE_PW R DEVSLP1 DEVSLP2

SATA_GP0 SATA_GP1 SATA_GP2

SOC_SATALED#

Default

1 IFDET_SATAEX0(HDD)

IFDET_SATAEX1

IFDET_SATAEX2

USB3_CRX_DTX_N1 <33>

USB3_CRX_DTX_P1 <33>

USB3_CTX_DRX_N1 <33>

USB3_CTX_DRX_P1 <33>

USB3_CRX_DTX_N2 <33>

USB3_CRX_DTX_P2 <33>

USB3_CTX_DRX_N2 <33>

USB3_CTX_DRX_P2 <33>

USB3_CRX_DTX_N3 <34>

USB3_CRX_DTX_P3 <34>

USB3_CTX_DRX_N3 <34>

USB3_CTX_DRX_P3 <34>

USB20_N1 <33> USB20_P1 <33>

USB20_N2 <33> USB20_P2 <33>

USB20_N3 <34> USB20_P3 <34>

USB20_N5 <20> USB20_P5 <20>

USB20_N6 <20> USB20_P6 <20>

USB20_N7 <37> USB20_P7 <37>

USB20_N8 <32>

T151 TP@ T150 TP@

T141 TP@ T143 TP@

T148 TP@ T238 TP@

USB20_P8 <32>

1 2

RC119 113_0402_1%

1 2

RC121 1K_0402_5%

1 2

RC125 1K_0402_5%

USB_OC0# <33> USB_OC1# <33>

TBT_FORCE_PW R <44>

DEVSLP1 <36> DEVSLP2 <36>

SATA_GP0 <36> SATA_GP1 <36> SATA_GP2 <36>

SOC_SATALED# <36,38>

USB3.0 MB_PORT1(Conn2 + OTG support)

3D CAMERA / Caldera

USB2.0 MB_PORT1 (Conn2)

USB2.0 MB_PORT2 (Conn1 + Power Share)

NC / Caldera

USB2.0 IO_PORT3 / NC

TOUCH SCREEN

USB2.0 Camera

ELC

NGFF WLAN+BT

SATA1 SATA2

IFDET_SATAEX0(Reserve) IFDET_SATAEX1 IFDET_SATAEX2

0=SATA

0=SATA 1=PCI-E1

0=SATA 1=PCI-E

SB3.0 MB_PORT2(Conn1 + Charge)

NC port for 3D Camera sku

NC port for Gaming

**** Swap Port **** Follow Customer design (Different with TD Team)

SOC_SATALED#

DEVSLP1 DEVSLP2 USB_OC0# USB_OC1#

1 2

RC211

10K_0402_5%

RPC13

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

+3VS +3V_PRIM

Follow 545659_SKL_PCH_LP_EDS_Rev1_0

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(7/12)PCIE,USB,SATA

Size Document Number Rev

LA-C901P

Date: Sheet

12 63Tuesday, August 04, 2015

1.0

For P

ower consumption Measurement

+5VALW

1U_0402_6.3V6K

CC98

D D

1 2

SYSON<13,41,54>

PM_SLP_S4#<6,10,37,41,54>

SUSP#<41,42,44>

PM_SLP_S3#<6,10,37,41>

For Power consumption Measurement

C C

Imax : 2.77 A

RC142 0_0402_1%@

1 2

RC144 0_0402_5%@

1 2

RC168 0_0402_1%@

1 2

RC194 0_0402_5%@

+1.8V_PRIM

+1.0V_PRIM TO +1.0VS_VCCSTG / +1.0VS_VCCIO

+5VALW

+3V_PRIM

CC92

1 2

0.1U_0201_10V6K

PM_SLP_S3# SUSP#

B B

For meet tPLT18 power down sequence. tPLT18 : 1us (Max)

+1.0VS_VCCIO

UC12

TC7SH08FU_SSOP5~D

RC187 0_0402_5%@

10U_0402_6.3V6M

CC27

CC28

0.1U_0402_25V6

CC88

EN_VCCSTG_IO

1 2

1U_0201_6.3V6M

CC29

1U_0201_6.3V6M

+1.0V_PRIM

CC30

I (Max) : 3 A(+1.0VS_VCCIO) RON(Max) : 6.2 mohm

1U_0402_6.3V6K

V drop : 0.019 V

CC117

1U_0201_6.3V6M

CC31

1U_0201_6.3V6M

CC32

UC6

VIN1

VIN2

VIN thermal

VBIAS

TPS22961DNYR_WSON8

1U_0402_6.3V6K

CC33

+1.0V_PRIM TO +1.0V_VCCSTU

1U_0402_6.3V6K

CC97

I (Max) : 0.04 A(+1.0V_VCCSTU) RON(Max) : 25 mohm

V drop : 0.001 V

EN_1.0V_VCCSTU

EN_1.8VS

1U_0402_6.3V6K

CC99

UC5

VIN1

ON1

VBIAS

ON2

VIN2

EM5209VF_DFN14_2X3

I (Max) : 0.536 A(+1.8VS) RON(Max) : 25 mohm V drop : 0.013 V

VOUT1 VOUT1

CT1

GND

CT2

VOUT2 VOUT2

GPAD

14 13

CC95

10P_0402_50V8J

CC94

1000P_0402_50V7K

8 15

1 2

+1.8V_PRIM TO +1.8VS

max : 0.04 A

1 2

RC188 0_0402_1%@

GND

+1.0VS_VCCSTG_IO

RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev1.0 RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev0_53

VOUT

PSC SideBSC Side

1U_0402_6.3V6K

CC34

1U_0402_6.3V6K

CC35

CC36

MP@

1 2

RC189 0_0805_5%

Imax : 3 A

+1.35V_VDDQ_CPU

+1.0V_VCCSTU+1.0V_PRIM

0.1U_0402_25V6

CC96

ollow 543977_SKL_PDDG_Rev0_91

F CC95 10PF ->22us(Spec:<= 65us)

+1.0V_VCCSTU +1.0V_VCCST

1 2

+1.35V_VDDQC

BSC Side

+1.0VS_VCCSTG

+1.0VS_VCCIO

1 2

RC208 0_0603_1%@

+1.8VS

CC100

0.1U_0402_25V6

CC89 0.1U_0402_25V6

CC90 0.1U_0402_25V6

+1.35V_VDDQ

For Power consumption Measurement

1 2

RC140 0_0402_1%

1 2

RC143 0_0402_1%@

PSC Side

1U_0402_6.3V6K

CC47

1 2

RC145 0_0805_1%@

+1.0VS_VCCSTG

+1.35V_VCCSFR_OC

+1.0V_VCCSFR

PSC Side

+1.35V_VDDQ_CPU

10U_0603_6.3V6M

CC93

+1.35V_VDDQC +1.0V_VCCST

+1.0V_VCCSFR

10U_0603_6.3V6M

+1.35V_VDDQ_CPU

1U_0402_6.3V6K

CC48

1U_0402_6.3V6K

CC55

SC Side

10U_0603_6.3V6M

CC37

UC1N

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

BB47

VDDQ_BB47

BB51

VDDQ_BB51

AM40

VDDQC

A18

VCCST

A22

VCCSTG_A22

AL23

VCCPLL_OC

K20

VCCPLL_K20

K21

VCCPLL_K21

+5VALW +1.35V_VDDQ_CPU

+1.0VS_VCCSTG

10U_0603_6.3V6M

CC38

CC39

10U_0603_6.3V6M

SKL-U

SYSON<13,41,54>

CC40

CPU POWER 3 OF 4

14 OF 20

CC101

BSC Side

1U_0201_6.3V6M

CC56

10U_0603_6.3V6M

CC41

1U_0201_6.3V6M

Rev_1.0

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE VCCSA_SENSE

L-U_BGA1356@

1 2

7 3 4

BSC SideP

10U_0603_6.3V6M

CC42

+1.0VS_VCCIO

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23

VCCIO_SENSE

AM22

VSSIO_SENSE

H21

VSA_SEN-

H20

VSA_SEN+

+1.35V_VDDQ_CPU

UC10

VIN1 VIN2

VIN thermal VBIAS ON

TPS22961DNYR_WSON8

1U_0402_6.3V6K

1U_0201_6.3V6M

CC43

CC44

+VCC_SA

1 2

VOUT

GND

1U_0402_6.3V6K

CC45

RC141

0_0402_5%@

T124 TP@ T125 TP@

VSA_SEN- <58> VSA_SEN+ <58>

+1.35V_VCCSFR_OC

BSC Side

0.1U_0201_10V6K

CC49

1U_0402_6.3V6K

CC46

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CC47 Follow 543016_SKL_U_Y_PDG_0_9 C

C93 Follow 543016_SKL UY PDG_rev1_3

Compal Secret Data

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

+1.35V_VDDQ_CPU : 10UF/6.3V/0603 *6

1UF/6.3V/0402 * 4

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SKL-U(8/12)Power

LA-C901P

1.0

13 63Tuesday, August 04, 2015

+1.0V_PRIM

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC148 0_0603_1%@

D D

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC152 0_0603_1%@

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC190 0_0603_1%@

C C

Imax : 2.57A

1 2

RC175 0_0402_1%@

Follow 543016_SKL_U_Y_PDG_1_0

1 2

RC169 0_0603_1%@

B B

1 2

RC162 0_0402_1%@

1U_0402_6.3V6K

+1.0V_APLL

22U_0603_6.3V6M

CC123

+1.0V_CLK5_F24NS

22U_0603_6.3V6M

CC129

+1.0V_CLK4_F100OC

22U_0603_6.3V6M

CC127

+1.0V_PRIM

+1.0V_MPHYAON

+1.0V_CLK6_24TBT

1U_0402_6.3V6K

CC86

CC75

+1.0V_DTS

22U_0603_6.3V6M

CC124

+3V_PRIM

1 2

22U_0603_6.3V6M

CC130

22U_0603_6.3V6M

CC128

1U_0402_6.3V6K

CC76

1U_0402_6.3V6K

CC87

22U_0603_6.3V6M

CC125

RC197 0_0402_1%@

1 2

RC154 0_0402_1%@

1 2

RC161 0_0402_1%@

1 2

RC172 0_0402_1%@

CC126

1 2

RC171 0_0402_1%@

+3V_1.8V_PGPPA

+3V_SPI

+3V_PGPPBCE

+3V_1.8V_PGPPD

+3V_PRIM_RTC

1U_0402_6.3V6K

CC102

RC206 0_0402_5%@

1U_0402_6.3V6K

CC103

1U_0402_6.3V6K

CC77

1U_0402_6.3V6K

CC73

1 2

0.1U_0201_10V6K

CC78

+1.0V_AMPHYPLL+1.0V_MPHYPLL

1 2

RC149 0_0603_1%@

1 2

RC156 0_0402_1%@

1 2

1U_0402_6.3V6K

CC74

+1.8V_PRIM

RC176 0_0603_1%@

RC209 0_0603_1%@

+1.0VO_DSW

1 2

1U_0402_6.3V6K

CC85

+1.8V_PRIM

1U_0402_6.3V6K

CC72

1U_0402_6.3V6K

CC61

1U_0201_6.3V6M

CC80

+3V_PRIM

22U_0603_6.3V6M

CC118

+1.0V_APLLEBB

+1.0V_SRAM

+1.0V_MPHYGT

22U_0603_6.3V6M

CC81

+1.0V_PRIM

1U_0402_6.3V6K

CC67

22U_0603_6.3V6M

CC119

1U_0201_6.3V6M

CC68

1U_0402_6.3V6K

CC122

22U_0603_6.3V6M

CC82

+1.0V_PRIM

+1.0VO_DSW

+1.0V_MPHYAON

+1.0V_MPHYGT

+1.0V_AMPHYPLL

+1.0V_APLL +1.0V_PRIM

+3VALW_DSW

RC163 close to UC1 pinAJ19

+3V_PRIM

Per 543016_SKL_U_Y_PDG_0_9 VCCRTC does not exceed 3.2 V From PDG

1 2

RF@

RC163 0_0402_5%

+3V_SPI +1.0V_SRAM

+3V_PRIM +1.0V_PRIM

+1.0V_APLLEBB

Power Rail Voltage

+CHGRTC

3.383V(MAX)

BAT54C(VF)

240 mV

+3VL_RTC

3.143V

1U_0402_6.3V6K

CC91

Note : Stuff UC8 RC191,RC159,CC50,PR809 for meet energy star power consumption under AC S5 mode

PCH_PWR_EN<41,56> SLP_SUS#<10,41>

Result : Pass

1 2

RC191 0_0402_1%@

1 2

RC174 0_0402_5%@

+1.0V_PRIM

UC1O

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB_1P0

+RTCBATT

RC192 1K_0402_5%

+3VLP

+3VALW TO +3V_PRIM

+3VALW

I (Max) : 0.46 A(+3V_PRIM) RDS(Typ) : 65 mohm V drop : 0.03 V

1U_0402_6.3V6K

CC50

EN_3V_PRIM

RC167 100K_0402_5%

SKL-U

CPU POWER 4 OF 4

15 OF 20

W=20mils

1 2

W=20mils

UC8

SY6288C20AAC_SOT23-5

Rev_1.0

VCCPGPPA

VCCPGPPB VCCPGPPC VCCPGPPD

VCCPGPPE

VCCPGPPF VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

DCPRTC VCCCLK1 VCCCLK2 VCCCLK3 VCCCLK4 VCCCLK5 VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

L-U_BGA1356@

RTC Battery

MAX. 8000mil

DC1

BAT54C-7-F_SOT23-3

RC153 0_0805_5%@

+3V_PRIMJP

RC159 0_0805_5%

OUT

GND

3V_PRIM_OC

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19 T1 AA1 AK17 AK19

BB14 BB10

CC71 0.1U_0402_10V7K

A14 K19 L21 N20 L19 A10 AN11

PRIMCORE_VID0

AN13

PRIMCORE_VID1

C79.CC84 Close UC1.AK19.

W=20mils

1U_0201_6.3V6M

CC84

For NON-DS3

1 2

For DS3

1 2

RC166 10K_0402_5%

+3V_1.8V_PGPPA +3V_PGPPBCE

+3V_1.8V_PGPPD +3V_PGPPBCE +1.8V_PRIM +3V_PGPPBCE

+3V_PRIM +1.0V_DTS +1.8V_PRIM +3V_PRIM_RTC +3VL_RTC

1 2

+1.0V_CLK6_24TBT

+1.0V_APLL +1.0V_CLK4_F100OC +1.0V_CLK5_F24NS +1.0V_CLK6_24TBT

0.1U_0201_10V6K

CC79

+3V_PRIM+3VALW

+3VALW

T130 TP@ T131 TP@

+3VL_RTC

4.7U_0603_6.3V6K CC51

For SD CARD

Follow 543016_SKL_U_Y_PDG_0_9

+1.0V_PRIM +3V_PRIM +1.8V_PRIM

22U_0603_6.3V6M

A A

22U_0603_6.3V6M

CC112

CC111

CC113

22U_0603_6.3V6M

CC115

CC116

CC114

EXT_PWR_GATE#<10>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITH OUT PRIOR WRITT EN CONSENT OF C OMPAL ELECTRONICS, INC.

RC210 0_0402_1%@

2015/01/06 2016/01/06

+5VALW

1 2

Compal Secret Data

Deciphered Date

0.1U_0402_25V6

CC52

+1.0V_PRIM

EXT_PWR_GATE#_R

1.0V_PRIM TO +1.0V_MPHYPLL

I (Max) : 2.766 A(+1.0V_MPHYPLL) RON(Max) : 6.2 mohm

1U_0402_6.3V6K

V drop : 0.017 V

CC59

UC4

RC170 100K_0402_5%

VIN1

VIN2

VIN thermal

VBIAS

TPS22961DNYR_WSON8

VOUT

GND

Title

Size Document Number Rev

Date: Sheet

For Premium

Compal Electronics, Inc.

LA-C901P

1 2

+1.0V_MPHYJP

+1.0V_PRIM

SKL-U(9/12)Power

RC164 0_0805_5%

Imax : 2.766A

For Volume

MP@

1 2

RC160 0_0805_5%

+1.0V_MPHYPLL

CC58

0.1U_0402_25V6

14 63Tuesday, August 04, 2015

1.0

+VCC_CORE +VCC_CORE

UC1L

A30

VCC_A30

A34

VCC_A34

D D

T123 TP@ T121 TP@

+1.0VS_VCCOPC

For CPU2+3e SKU

+1.8V_VCCOPC

C C

B B

T132 TP@ T133 TP@

T137 TP@ T139 TP@

SVID ALERT

VCCOPC_SENSE VSSOPC_SENSE

+1.0VS_VCCEOPIO

VCCEOPIO_SENSE VSSEOPIO_SENSE

+1.0V_VCCST

A39

VCC_A39

A44

VCC_A44

AK33

VCC_AK33

AK35

VCC_AK35

AK37

VCC_AK37

AK38

VCC_AK38

AK40

VCC_AK40

AL33

VCC_AL33

AL37

VCC_AL37

AL40

VCC_AL40

AM32

VCC_AM32

AM33

VCC_AM33

AM35

VCC_AM35

AM37

VCC_AM37

AM38

VCC_AM38

G30

VCC_G30

K32

RSVD

AK32

RSVD

AB62

VCCOPC_AB62

P62

VCCOPC_P62

V62

VCCOPC_V62

H63

VCC_OPC_1P8_H63

G61

VCC_OPC_1P8_G61

AC63

VCCOPC_SENSE

AE63

VSSOPC_SENSE

AE62

VCCEOPIO

AG62

VCCEOPIO

AL63

VCCEOPIO_SENSE

AJ62

VSSEOPIO_SENSE

Place the PU resistors close to CPU

RC179 56_0402_5%

SKL-U

CPU POWER 1 OF 4

12 OF 20

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VCC_SENSE

VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

L-U_BGA1356@

Rev_1.0

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

B63 A63 D64

G20

SOC_SVID_ALERT# SOC_SVID_CLK SOC_SVID_DAT

Trace Length < 25 mils

VCCSENSE <58> VSSSENSE <58>

SOC_SVID_CLK <58>

VCCGT_SENSE<58> VSSGT_SENSE<58>

Trace Length < 25 mils

+1.0VS_VCCSTG

VCCGT_SENSE VSSGT_SENSE

+VCC_GT +VCC_GT

A48 A53 A58 A62

A66 AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71

K48

K50

K52

K53

K55

K56

K58

K60

M62

N63

N64

N66

N67

N69

J43 J45 J46 J48 J50 J52 J53 J55 J56 J58 J60

L62 L63 L64 L65 L66 L67 L68 L69 L70 L71

J70 J69

UC1M

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT_SENSE VSSGT_SENSE

For 2+3e Solution

BSC Side BSC Side

SOC_SVID_ALERT#

SVID DATA

A A

1 2

RC180 220_0402_5%

+1.0V_VCCST

RC181 100_0402_1%

SOC_SVID_ALERT#_R <58>

Place the PU resistors close to CPU

(To VR)

CC66

10U_0603_6.3V6M

23E@

CPU POWER 2 OF 4

+1.0VS_VCCOPC+1.0VS_VCCEOPIO

CC62

1U_0402_6.3V6K

SKL-U

13 OF 20

23E@

Rev_1.0

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70

VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56

VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58

VCCGTX_AU58 VCCGTX_AU63 VCCGTX_BB57 VCCGTX_BB66

VCCGTX_SENSE VSSGTX_SENSE

L-U_BGA1356@

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

+VCC_GTX

VCCGTX_SENSE VSSGTX_SENSE

For CPU2+3e SKU

T155 TP@ T219 TP@

SOC_SVID_DAT

SOC_SVID_DAT <58>

(To VR)

Security Classification

2015/01/06 2016/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

SKL-U(10/12)Power,SVID

LA-C901P

15 63Tuesday, August 04, 2015

1.0

D D

C C

B B

A67

A70 AA2 AA4

AA65 AA68 AB15 AB16 AB18 AB21

AB8

AD13 AD16 AD19 AD20 AD21 AD62

AD8

AE64 AE65 AE66 AE67 AE68 AE69

AF1

AF10 AF15 AF17

AF2

AF4

AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13

AH6

AH63 AH64 AH67

AJ15 AJ18 AJ20

AJ4

AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69

AK8

AL2

AL28 AL32 AL35 AL38

AL4

AL45 AL48 AL52 AL55 AL58 AL64

UC1P

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-U

GND 1 OF 3

16 OF 20

SKL-U

GND 2 OF 3

17 OF 20

Rev_1.0

BA49

VSS

BA53

VSS

BA57

VSS

BA6

VSS

BA62

VSS

BA66

VSS

BA71

VSS

BB18

VSS

BB26

VSS

BB30

VSS

BB34

VSS

BB38

VSS

BB43

VSS

BB55

VSS

BB6

VSS

BB60

VSS

BB64

VSS

BB67

VSS

BB70

VSS

C25

VSS

D10

VSS

D11

VSS

D14

VSS

D18

VSS

D22

VSS

D25

VSS

D26

VSS

D30

VSS

D34

VSS

D39

VSS

D44

VSS

D45

VSS

D47

VSS

D48

VSS

D53

VSS

D58

VSS

D62

VSS

D66

VSS

D69

VSS

E11

VSS

E15

VSS

E18

VSS

E21

VSS

E46

VSS

E50

VSS

E53

VSS

E56

VSS

E65

VSS

E71

VSS

F13

VSS

F22

VSS

F23

VSS

F27

VSS

F28

VSS

F32

VSS

F33

VSS

F35

VSS

F37

VSS

F38

VSS

F40

VSS

F42

VSS

BA41

VSS

L-U_BGA1356@

G10 G22 G43 G45 G48

G52 G55 G58

G60 G63 G66 H15 H18 H71

J11 J13 J25 J28 J32 J35 J38 J42

K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71 L11 L16 L17

UC1R

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L-U_BGA1356

SKL-U

GND 3 OF 3

18 OF 20

Rev_1.0

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

AT63 AT68 AT71 AU10 AU15 AU20 AU32 AU38

AV1 AV68 AV69 AV70 AV71

AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57

AW6 AW60 AW62 AW64 AW66

AW8

AY66

B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71

BA1 BA10 BA14 BA18

BA2 BA23 BA28 BA32 BA36

F68 BA45

UC1Q

Rev_1.0

AL65

VSS

AL66

VSS

AM13

VSS

AM21

VSS

AM25

VSS

AM27

VSS

AM43

VSS

AM45

VSS

AM46

VSS

AM55

VSS

AM60

VSS

AM61

VSS

AM68

VSS

AM71

VSS

AM8

VSS

AN20

VSS

AN23

VSS

AN28

VSS

AN30

VSS

AN32

VSS

AN33

VSS

AN35

VSS

AN37

VSS

AN38

VSS

AN40

VSS

AN42

VSS

AN58

VSS

AN63

VSS

AP10

VSS

AP18

VSS

AP20

VSS

AP23

VSS

AP28

VSS

AP32

VSS

AP35

VSS

AP38

VSS

AP42

VSS

AP58

VSS

AP63

VSS

AP68

VSS

AP70

VSS

AR11

VSS

AR15

VSS

AR16

VSS

AR20

VSS

AR23

VSS

AR28

VSS

AR35

VSS

AR42

VSS

AR43

VSS

AR45

VSS

AR46

VSS

AR48

VSS

AR5

VSS

AR50

VSS

AR52

VSS

AR53

VSS

AR55

VSS

AR58

VSS

AR63

VSS

AR8

VSS

AT2

VSS

AT20

VSS

AT23

VSS

AT28

VSS

AT35

VSS

AT4

VSS

AT42

VSS

AT56

VSS

AT58

VSS

L-U_BGA1356@

A A

Security Classification

2015/01/06 2016/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

SKL-U(11/12)GND

LA-C901P

1.0

16 63Tuesday, August 04, 2015

Display Port Presence Strap

CFG4

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is

onnected to the Embedded Display Port

D D

CFG0<6> CFG1<6> CFG2<6> CFG3<6> CFG4<6> CFG5<6> CFG6<6> CFG7<6>

CFG Signals

(For Strap & XDP)

C C

B B

CFG8<6> CFG9<6> CFG10<6> CFG11<6> CFG12<6> CFG13<6> CFG14<6> CFG15<6>

CFG16<6> CFG17<6>

CFG18<6> CFG19<6>

RC18549.9_0402_1%

XDP_ITP_PMODE<6>

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG17

CFG18 CFG19

CFG_RCOMP

XDP_ITP_PMODE

T213 TP@ T215 TP@

T220 TP@ T222 TP@

E68 B67 D65 D67 E70 C68 D68 C67

G69 G68

H70 G71 H69 G70

E63

E66

E60

AY2 AY1

K46 K45

AL25 AL27

C71 B70

A52

BA70 BA68

G65

E61

F71 F70

F63

F66

D1 D3

F60

J71 J68

F65

F61

UC1S

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP ITP_PMODE RSVD_AY2

RSVD_AY1 RSVD_D1

RSVD_D3 RSVD_K46

RSVD_K45 RSVD_AL25

RSVD_AL27 RSVD_C71

RSVD_B70 RSVD_F60 RSVD_A52 RSVD_TP_BA70

RSVD_TP_BA68 RSVD_J71

RSVD_J68 VSS_F65

VSS_G65 RSVD_F61

RSVD_E61

L-U_BGA1356

SKL-U

RESERVED SIGNALS-1

19 OF 20

Rev_1.0

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

TP5 TP6

RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4 RSVD_C4

TP4

RSVD_A69 RSVD_B69

RSVD_AY3 RSVD_D71

RSVD_C70 RSVD_C54

RSVD_D54

TP1 TP2

VSS_AY71

ZVM#

RSVD_TP RSVD_TP

MSM#

PROC_SELECT#

BB68 BB69

AK13 AK12

BB2 BA3

AU5 AT5

D5 D4 B2 C2

B3 A3

AW1 E1

E2 BA4

BB4 A4

C4 BB5 A69

B69 AY3 D71

C70 C54

D54 AY4

BB3 AY71

AR56 AW71

AW70 AP56

C64

PM_ZVM#

PM_MSM# SKL_CNL#

T156 TP@ T157 TP@

T158 TP@ T159 TP@

T162 TP@ T163 TP@

T199 TP@

1 2

RC182 0_0402_1%@

T214 TP@ T216 TP@

T225 TP@ T221 TP@

T223 TP@ T230 TP@

1 2

RC183 0_0402_1%@

RC184 100K_0402_5%@

+1.0V_VCCST

1 2

Follow 546765_2014WW48_Skylake_MOW_Rev_1_0 St

uff 100k(RC184) for Cannonlake.

Un-stuff 100k(RC184) for Skylake

For 2+3e Solution

PM_ZVM# Zero Voltage Mode: Control Signal to OPC VR, when low OPC VR output is 0V.

PM_MSM# Minimum Speed Mode: Control signal to VccEOPIO VR (connected only in 2 VR solution for OPC).

UC1T

AW69

RSVD_AW69

AW68

RSVD_AW68

AU56

RSVD_AU56

AW48

RSVD_AW48

RSVD_C7

U12

RSVD_U12

U11

RSVD_U11

H11

RSVD_H11

A A

SKL-U_BGA1356

SKL-U

SPARE

20 OF 20

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev_1.0

RSVD_F6

RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12 RSVD_F52

F6 E3 C11 B11 A11 D12 C12 F52

Compal Secret Data

2015/01/06 2016/01/06

Compal Secret Data

Deciphered Date

PROC_SELECT# Processor Select: This pin is for compatibility with future platforms. It should NC with Skylake

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

SKL-U(12/12)RSVD

LA-C901P

17 63Tuesday, August 04, 2015

1.0

DDR_A_DQS#[0..7]<7>

DDR_A_D[0..63]<7>

DDR_A_DQS[0..7]<7>

DDR_A_MA[0..15]<7>

DDR_A_BS0<7>

DDR_A_BS1<7>

DDR_A_BS2<7>

DDR_A_WE#<7>

1 1

Layout Note: Place near JDIMM1

2 2

+1.35V_VDDQ

10U_0603_6.3V6M

3 3

4 4

Layout Note: Place near JDIMM1.203,204

+0.675VS_VTT

DDR_A_CAS#<7>

DDR_A_RAS#<7>

DDR_A_CLK0<7> DDR_A_CLK#0<7>

DDR_A_CLK1<7>

DDR_A_CLK#1<7>

DDR_A_CKE0<7>

DDR_A_CKE1<7>

DDR_A_CS#0<7> DDR_A_CS#1<7>

SOC_SMBDATA<8,19,36> SOC_SMBCLK<8,19,36>

DDR_A_ODT0<7>

DDR_A_ODT1<7>

M_THERMAL#<19,41>

1U_0402_6.3V6K

CD4

10U_0603_6.3V6M

CD10

0.1U_0402_25V6K

CD22

1U_0402_6.3V6K

CD5

10U_0603_6.3V6M

CD11

CD12

1U_0402_6.3V6K

0.1U_0402_25V6K CD23

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_WE# DDR_A_CAS# DDR_A_RAS#

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1

DDR_A_CKE0 DDR_A_CKE1 DDR_A_CS#0 DDR_A_CS#1

SOC_SMBDATA SOC_SMBCLK

DDR_A_ODT0 DDR_A_ODT1

M_THERMAL#

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

1U_0402_6.3V6K

CD6

CD24

CD7

CD8

10U_0603_6.3V6M

CD13

CD14

CD19

1U_0402_6.3V6K

CD25

/DQ Signals link to CPU

CMD Signals from CPU

Clock Signals from CPU

CTL Signals from CPU

SMBUS Signals link to CPU

From SOC ODT Signals to CH A

Thermal link to EC

1U_0402_6.3V6K

CD9

10U_0603_6.3V6M

CD15

Layout Note: Place near JDIMM1.199

+3VS

Address : 00

330U_D3_2.5VY_R6M

CD20

CD16

0.1U_0402_25V6K

CD27

CD26

2.2U_0402_6.3V6M

1 2

RC220 10K_0402_5%

1 2

RC221 10K_0402_5%

DDR_A_SA0 DDR_A_SA1

+0.675V_DDRA_VREFDQ

2.2U_0402_6.3V6M

10mils

0.1U_0402_25V6K

DDR_A_D29

CD1

DDR_A_D28

CD2

DDR_A_D30 DDR_A_D31

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D11 DDR_A_D10

DDR_A_D50 DDR_A_D51

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D49 DDR_A_D48

DDR_A_D45 DDR_A_D44

DDR_A_D42 DDR_A_D43

DDR_A_CKE0

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3

DDR_A_MA1 DDR_A_CLK0

DDR_A_CLK#0 DDR_A_MA10

DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# DDR_A_MA13

DDR_A_CS#1

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D3 DDR_A_D36

DDR_A_D32

DDR_A_D33 DDR_A_D39

DDR_A_D21 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D23

DDR_A_D56 DDR_A_D57

DDR_A_D63

+3VS+0.675VS_VTT +0.675VS_VTT

DDR_A_SA0 DDR_A_SA1

+0.675VS_VTT

JDIMM1

VREF_DQ

VSS

DQ0

DQ1

VSS

DM0

VSS

DQ2

DQ3

VSS

DQ8

DQ9

VSS

DQS1#

DQS1

VSS

DQ10

DQ11

VSS

DQ16

DQ17

VSS

DQS2#

DQS2

VSS

DQ18

DQ19

VSS

DQ24

DQ25

VSS

DM3

VSS

DQ26

DQ27

VSS

CKE0

VDD

BA2

VDD

A12/BC#

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

FOX_AS0A621-J4RB-7H

CONN@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DQS0#

DQS0

DQ12 DQ13

DM1

RESET#

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3 DQ30

DQ31

CKE1

VDD

CK1#

VDD

RAS#

VDD

ODT0

VDD

ODT1

VDD

VREF_CA

DQ36 DQ37

DM4

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5 DQ46

DQ47 DQ52

DQ53

DM6

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7 DQ62

DQ63

EVENT#

SDA SCL

GND2

BOSS2

VSS DQ4 DQ5 VSS

VSS DQ6 DQ7 VSS

VSS

VSS VSS

VSS

A15 A14

A11

CK1

BA1

S0#

VSS

VSS VSS

VSS

VSS VSS

VSS

VTT

4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86

88 90

94 96

100 102 104 106 108 110 112 114 116 118 120 122

124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

DDR_A_D24 DDR_A_D25

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D26 DDR_A_D27

DDR_A_D12 DDR_A_D13

DDR_DRAMRST# DDR_A_D14

DDR_A_D15 DDR_A_D52

DDR_A_D53

DDR_A_D54 DDR_A_D55

DDR_A_D40 DDR_A_D41

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D47 DDR_A_D46

+1.35V_VDDQ+1.35V_VDDQ

DDR_A_CKE1 DDR_A_MA15

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2

DDR_A_MA0 DDR_A_CLK1

DDR_A_CLK#1 DDR_A_BS1

DDR_A_RAS# DDR_A_CS#0

DDR_A_ODT0 DDR_A_ODT1

DDR_A_D0DDR_A_D5 DDR_A_D1DDR_A_D4

DDR_A_D2 DDR_A_D6DDR_A_D7

DDR_A_D37 DDR_A_D35

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D38

DDR_A_D20 DDR_A_D16

DDR_A_D22 DDR_A_D19

DDR_A_D61 DDR_A_D60

DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D58

DDR_A_D59DDR_A_D62 M_THERMAL#

SOC_SMBDATA SOC_SMBCLK +0.675VS_VTT

2015/01/06 2016/01/06

10mils

2.2U_0402_6.3V6M CD17

Compal Secret Data

Deciphered Date

0.1U_0402_25V6K CD3

CAD NOTE

PLACE THE CAP NEAR TO DIMM RESET PIN

1 2

RD8 0_0402_1%@

0.1U_0402_25V6K CD18

Reverse Type

2-3A to 1 DIMMs/channel

+1.35V_VDDQ

RD1 470_0402_5%

DDR_DRAMRST# <7,19>

+0.675V_DDR_VREFCA+0.675V_DDRA_VREFCA

+1.35V_VDDQ

1.8K_0402_1%

RD9

1 2

RD10 2_0402_1%

1.8K_0402_1%

RD11

From CPU to CHB

+0.675V_A_VREFDQ+0.675V_DDRA_VREFDQ

CD21

0.022U_0402_16V7K

RD12

24.9_0402_1%

Place near to SO-DIMM connector.

Non- Interleaved Memory

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDR3L_DIMMA

LA-C901P

18 63Tuesday, August 04, 2015

1.0

DDR_B_DQS#[0..7]<7> DDR_B_D[0..63]<7> DDR_B_DQS[0..7]<7>

DDR_B_MA[0..15]<7>

DDR_B_BS0<7>

DDR_B_BS1<7>

DDR_B_BS2<7> DDR_B_WE#<7>

1 1

Layout Note: Place near JDIMM2

2 2

+1.35V_VDDQ

3 3

Layout Note: Place near JDIMM2.203,204

+0.675VS_VTT

4 4

DDR_B_CAS#<7> DDR_B_RAS#<7>

DDR_B_CLK0<7> DDR_B_CLK#0<7> DDR_B_CLK1<7> DDR_B_CLK#1<7>

DDR_B_CKE0<7> DDR_B_CKE1<7> DDR_B_CS#0<7> DDR_B_CS#1<7>

SOC_SMBDATA<8,18,36> SOC_SMBCLK<8,18,36>

DDR_B_ODT0<7> DDR_B_ODT1<7>

M_THERMAL#<18,41>

1U_0402_6.3V6K

CD32

CD33

10U_0603_6.3V6M

CD39

CD38

0.1U_0402_25V6K

CD51

CD50

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_WE# DDR_B_CAS# DDR_B_RAS#

DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1

DDR_B_CKE0 DDR_B_CKE1

DDR_B_CS#0

DDR_B_CS#1

SOC_SMBDATA SOC_SMBCLK

DDR_B_ODT0 DDR_B_ODT1

M_THERMAL#

1U_0402_6.3V6K

10U_0603_6.3V6M

1U_0402_6.3V6K

CD35

CD34

10U_0603_6.3V6M

CD41

CD40

1U_0402_6.3V6K

CD52

CD53

D/DQ Signals link to CPU

CMD Signals from CPU

Clock Signals from CPU

CTL Signals from CPU

SMBUS Signals link to CPU

From SOC ODT Signals to CH B

Thermal link to EC

1U_0402_6.3V6K

CD36

CD37

10U_0603_6.3V6M

CD42

Layout Note: P

lace near JDIMM2.199

+3VS

10U_0603_6.3V6M

CD43

+3VS

0.1U_0402_25V6K

Address : 01

1 2

RD22 10K_0402_5%

1 2

RD23 10K_0402_5%

10U_0603_6.3V6M

CD44

CD45

CD54

2.2U_0402_6.3V6M

CD55

DDR_B_SA1 DDR_B_SA0

+0.675V_DDRB_VREFDQ

330U_D3_2.5VY_R6M

CD46

10mils

2.2U_0402_6.3V6M CD28

+0.675VS_VTT +3VS

0.1U_0402_25V6K

DDR_B_D8 DDR_B_D9

CD29

DDR_B_D10 DDR_B_D11

DDR_B_D29 DDR_B_D28

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D26 DDR_B_D27

DDR_B_D41 DDR_B_D40

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D43 DDR_B_D42

DDR_B_D56 DDR_B_D57

DDR_B_D59 DDR_B_D58

DDR_B_CKE0

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3

DDR_B_MA1 DDR_B_CLK0

DDR_B_CLK#0 DDR_B_MA10

DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDR_B_MA13

DDR_B_CS#1

DDR_B_D2 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D21 DDR_B_D20

DDR_B_D19 DDR_B_D18 DDR_B_D23

DDR_B_D36 DDR_B_DQS#4

DDR_B_DQS4 DDR_B_D33

DDR_B_D35

DDR_B_D49

DDR_B_D51 DDR_B_D50 DDR_B_D55

DDR_B_SA0 DDR_B_SA1

+0.675VS_VTT

JDIMM2

VREF_DQ

VSS

DQ0

DQ1

VSS

DM0

VSS

DQ2

DQ3

VSS

DQ8

DQ9

VSS

DQS1#

DQS1

VSS

DQ10

DQ11

VSS

DQ16

DQ17

VSS

DQS2#

DQS2

VSS

DQ18

DQ19

VSS

DQ24

DQ25

VSS

DM3

VSS

DQ26

DQ27

+1.35V_VDDQ

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205 207

VSS

CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT

GND1 BOSS1

FOX_AS0A621-J4RB-7H

CONN@

2015/01/06 2016/01/06

VSS DQ4 DQ5 VSS

DQS0#

DQS0

VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

RESET#

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

CKE1

VDD

VDD CK1#

VDD RAS#

VDD ODT0

VDD ODT1

VDD

VREF_CA

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

EVENT#

SDA

GND2

BOSS2

A15 A14

A11

CK1

BA1

S0#

SCL VTT

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86

88 90

94 96

100 102 104 106 108 110 112 114 116 118 120 122

124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

DDR_B_D13 DDR_B_D12

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D15 DDR_B_D14

DDR_B_D25 DDR_B_D24

DDR_DRAMRST# DDR_B_D30

DDR_B_D31 DDR_B_D45

DDR_B_D44

DDR_B_D47 DDR_B_D46

DDR_B_D61 DDR_B_D60

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

+1.35V_VDDQ

DDR_B_CKE1 DDR_B_MA15

DDR_B_MA14 DDR_B_MA11

DDR_B_MA7 DDR_B_MA6

DDR_B_MA4 DDR_B_MA2

DDR_B_MA0 DDR_B_CLK1

DDR_B_CLK#1 DDR_B_BS1

DDR_B_RAS# DDR_B_CS#0

DDR_B_ODT0 DDR_B_ODT1

DDR_B_D0 DDR_B_D4

DDR_B_D3 DDR_B_D1

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D22

DDR_B_D32DDR_B_D37 DDR_B_D34

DDR_B_D39 DDR_B_D38

DDR_B_D53 DDR_B_D52DDR_B_D48

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D54

M_THERMAL# SOC_SMBDATA SOC_SMBCLK +0.675VS_VTT

Compal Secret Data

Deciphered Date

0.1U_0402_25V6K CD30

CAD NOTE PLACE THE CAP NEAR TO DIMM RESET PIN

10mils

2.2U_0402_6.3V6M

CD47

+0.675VS_VTT

DDR_DRAMRST# <7,18>

+1.35V_VDDQ

1.8K_0402_1%

Place near to SO-DIMM connector.

1 2

RD17 0_0402_1%@

0.1U_0402_25V6K

CD48

+1.35V_VDDQ

1.8K_0402_1%

Place near to SO-DIMM connector.

Non-Interleaved Memory

Date: Sheet

Reverse Type

2-3A to 1 DIMMs/channel

From CPU

RD13

+0.675V_B_VREFDQ+0.675V_DDRB_VREFDQ

1 2

RD14 2_0402_1%

RD15

+0.675V_DDR_VREFCA+0.675V_DDRB_VREFCA

RD18

1 2

RD19 2_0402_1%

RD20

Title

Size Document Number Rev

CD31

0.022U_0402_16V7K

RD16

24.9_0402_1%

+0.675V_VREFCA+0.675V_DDR_VREFCA

CD49

0.022U_0402_16V7K

RD21

24.9_0402_1%

Compal Electronics, Inc.

DDR3L_DIMMB

LA-C901P

19 63Tuesday, August 04, 2015

1.0

+ 44 hidden pages

Compal LA-C901P Schematics Rev1.0

Specifications and Main Features

Frequently Asked Questions

User Manual