Compal LA-C871P Schematics Rev1.0

smd.db-x7.ru

1 1

2 2

Compal Confidential

A4WAD MB Schematic Document

LA-C871P

3 3

Rev: 1.0

2015.07.13

DAX

Part Number

DA6001ED010 PCB 1DS LA-C871P REV1 MB 1

A4WAD_PCB_REV10

PCB@

4 4

DAZ

Part Number

DAZ1DS00100 PCB A4W AD LA-C871P LS-C341P

A4WAD_PCB_Panelization

Description

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/12/31 2016/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Cover Sheet

Size Document Number Re v

Custom

A4WAD M/B LA-C871P

Date: Sheet of

1 60Monday, July 13, 2015

1.0

VGA

smd.db-x7.ru

HDMI Conn.

eDP

Fan Control

page 42

page 33

1 1

DP to VGA Realtek RTD2168

page 32

HDMI PS8407A

page 31

page 30

eDP

Skylake H PROCESSOR

BGA1440

Memory BUS

Dual Channel

1.35V DDR3L 1333/1600

(42X28) (SKL-H_2+2)

DP x 2 lanes

HDMI x 4 lanes

DDI

Processor

page 06~13

PEG X8 8GT/s

Interleaved Memory

Nvidia N16x

204pin DDR3L-SO-DIMM X1

BANK 0, 1, 2, 3

page 14

204pin DDR3L-SO-DIMM X1

BANK 4, 5, 6, 7

page 15

with DDR3 x4

page 23~29

NGFF

WLAN

USB port 7

2 2

page 37

PCIe 2.0 5GT/s

port 3

Flexible IO

Skylake PCH - H

PCIe 2.0 5GT/s

port 4

LAN(GbE)/ Card Reader

Realtek 8411B

page 35

SATA3.0 SATA3.0

port 2

SATA HDD Conn.

6.0 Gb/s6.0 Gb/s

port 3

SATA CDROM Conn.

FCBGA(23X23)

837pin FCBGA

X4 DMI

USBx8

HD Audio

page 16~22

USB 3.0 conn x2

USB port 1,2

48MHz

page 38 page 30

3.3V 24MHz

USB 2.0 conn x1

(port 3)

USB/B

page 38

CMOS Camera

USB port 9

Touch Screen

Card Reader

2 in 1 (SD)

3 3

page 36

RTC CKT.

Power On/Off CKT.

DC/DC Interface CKT.

4 4

Power Circuit DC/DC

RJ45 conn.

page 36

page 21

page 40

page 43

page 44~58

page 37

Sub Board

LS-C341P USB+Audio/B

page 38

LPC/eSPI BUS

page 37

CLK=24MHz

ENE KB9022/9032

Touch Pad Int.KBD

PS2 / I2C

page 40

page 39

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

page 40

TPM

page 39

SPI

SPI ROM x2 SPI Touch

page 17

Compal Secret Data

2014/12/31 2016/12/31

Compal Secret Data

Deciphered Date

Int. Speaker

HDA Codec

ALC283/255

page 41

Int. MIC

page 41

Title

Size Document Number Re v

Custom

A4WAD M/B LA-C871P

Date: Sheet of

page 41 page 38

Compal Electronics, Inc.

Block Diagrams

I2C (PORT1)

USB port 8

page 30

UAJ

on Sub/B

2 61Monday, July 13, 2015

1.0

Vinaﬁx.com

smd.db-x7.ru

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

1 1

100K +/- 5%Ra

0 1 2 3 4 5 6 7

0 0 V 12K +/- 1% 0.347 V 0.345 V 0.360 V 15K +/- 1% 20K +/- 1% 27K +/- 1% 33K +/- 1% 43K +/- 1% 56K +/- 1%

Rb V min

BID

0.423 V 0.430 V 0.438 V

V typ

BID

0 V 0.300 V

BID

max

EC AD3

0x00 - 0x0B 0x0C - 0x1C 0x1D - 0x26 0x27 - 0x300.541 V 0.550 V 0.559 V 0x31 - 0x3B0.691 V 0.702 V 0.713 V 0x3C - 0x460.807 V 0.819 V 0.831 V 0x47 - 0x540.978 V 0.992 V 1.006 V 0x55 - 0x641.169 V 1.185 V 1.200 V

Power State

STATE

S0 (Full ON) ON ON ON ONHIGH HIGH HIGH

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

LOW HIGH

LOWLOW

HIGH

ONONON

OFF

OFFLOW LOW LOW

OFF

BOARD ID Table

Board ID

0 1 2 3 4 5 6 7

PCB Revision

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

BOM Structure Table

BOM Option Table

Item BOM Structure

Unpop

Connector EMC requirement EMC requirement depop

CODEC(ALC 283) 283@ SPI ROM 8M*2 SPI ROM 8M*1

2 2

UMA only TPM

CONN@ EMC@ @EMC@ 255@CODEC(ALC 255)

8M_DUAL@

8M_SINGLE@

UMA@

TPM@

BOM Option Table

Item BOM Structure

dGPU

N16S-GT N16V-GM Non GPU CG6 funct i on GPU CG6 funct i on GC6@ VRAM BOM Select DMIC*1 For Acer IOAC No Acer IOAC

VGA@ SGT@

VGM@

NGC6@

X76@

DMIC@ IOAC@ NIOAC@

CMC@CMC

Keyboard backlight LPC MODE for EC ESPI MODE for EC BA Serial

I2C Address Table

BUS

I2C_0 (+3VS) Touch Panel

3 3

PCH_SMBCLK (+3VALW)

PCH_SML1CLK (+3VALW)

EC_SMB_CK1 (+3VLP)

KB@

LPC@

ESPI@

BA@

(TBC)

Device

TM-P2969-001 (Touch Pad)I2C_1 (+3VS)

SB8787-1200 (Touch Pad)

DIMM1 DIMM2

LIS3DHTR(G-sensor)

N16S-GT (VGA) RTD2168 (CRT)

BQ24780 (Charger IC)

BATTERY PACK

Address(7 bit)

reserved

0x2C

0x15

0xA0 0xA4

0x30

0x9E

reserved

0x12 0x16

Address(8bit)

Write Read

Voltage Rails

Power Plane

+RTCVCC

VIN BATT+ Battery power supply

+19VB +3VLP +19VB to +3VLP power rail for suspend power +5VALW +3VALW System +3VALW always on power rail +3VALW_DSW +3VALW power for PCH DSW rails +3VALW_PCH +3VALW_SPI

+1.0VALW +1.0V Always power rail +1.35V_VDDQ

+1.0V_VCCSTU

+5VS System +5V power rail +3VS

+1.0VS_VCCSTG +1.0VALW_PRIM Gated version of VCCST

+0.675VS_VTT

+VCC_CORE +VCC_GT +VCCIO

+VCC_SA

+VGA_CORE

+1.8VSDGPU +1.8VS power rail for GPU +1.5VSDGPU +1.5VS power rail for GPU +1.05VSDGPU +1.05VS power rail for GPU

(TBC)

Description RTC Battery Power Adapter power supply

AC or battery power rail for power circuit.

+5V Always power rail

+3VALW power for PCH power rails

+3VALW_PRIM supply for the SPI IO

DDRIIIL/L-RS +1.35V power rail Sustain voltage for processor in Standby modes

System +3V power rail

DDR +0.675VS power rail for DDR terminator . Core voltage for CPU

Sliced graphics power rail

CPU IO power rail

System Agent power rail

+3VS power rail for GPU(AON rails)+3VSDGPU_AON +3VS power rail for GPU GC62.0+3VSDGPU_MAIN Core voltage for VGA

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

N/A N/A N/A

N/A N/A

N/A

ON ON ONON

ON ON ON ON

ON ON ON

OFF OFF OFF

OFF

OFF OFF OFF

ON ON

OFF OFF OFF

OFF

ON ON

OFF

OFF OFF OFF

OFF

ON ON

N/A N/A

ON ON ON ON ON ON ON ON

OFF OFF

OFF

OFF OFF

OFF

N/AN/AN/A

ON*

OFF OFF

OFF OFF OFF

OFFOFF

OFF OFF

OFF

43 level BOM table

4319YYBOL01 4319YYBOL02 4319YYBOL03 4319YYBOL04

4 4

SMT MB AC871 A4WAD QHR7 1.6G UMA HDMI SMT MB AC871 A4WAD QHR7 1.6G GM2G HDMI SMT MB AC871 A4WAD QHPW 2.2G GM2G HDMI SMT MB AC871 A4WAD QHPW 2.2G GT2G HDMI

QHR7@/1DMIC@/255@/8M_SINGLE@/BA@/EMC@/IOAC@/KB@/LPC@/PCB@/PCH@/TPM@/XDP@/ES@/UMA@ QHR7@/1DMIC@/255@/8M_SINGLE@/BA@/EMC@/IOAC@/KB@/LPC@/PCB@/PCH@/TPM@/XDP@/ES@/VGA@/VGM@/NGC6@/X7601@ QHPW@/1DMIC@/255@/8M_SINGLE@/BA@/EMC@/IOAC@/KB@/LPC@/PCB@/PCH@/TPM@/XDP@/ES@/VGA@/VGM@/NGC6@/X7601@ QHPW@/1DMIC@/255@/8M_SINGLE@/BA@/EMC@/IOAC@/KB@/LPC@/PCB@/PCH@/TPM@/XDP@/ES@/VGA@/SGT@/GC6@/X7603@/

BOM Structure43 Level Description

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/12/31 2016/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Notes List

Size Document Number Re v

Custom

A4WAD M/B LA-C871P

Date: Sheet of

3 60Monday, July 13, 2015

1.0

smd.db-x7.ru

DC_IN

PJP101

D D

C C

AC CONN.

PU301

CHARGER

PL101

+19V_VI N

+17.4V_B ATT

+19VB

PL201,PL202

IMVP8

+17.4V_BATT+

PL804,PL806

PU801

EN:VR_O N

PL803,PL805

PU806

EN:DRON

PU401

EN:3V_E N

PU501

EN:SYSO N

PJ501,PJ50 3

PU601

EN:+3VA LW

PU1201

EN:VGA_ EN

PL1202,PL12 03

PU1102 PJ1104

EN:1.5VS_D GPU_PWR_E N

PJP201

PL807

PJ401

PJ601

BATTERY

+VCCCOR E

+VCCGT

+VCCSA

+3VALW

+1.35V_V DDQ

+1.0VAL W

+VGA_CO RE

+1.5VSD GPU

+3VLP

CPU

EC,LID

GPU

U2012

CODEC

U27

HDMI REDRIVER

PU702

U11

R2600

U2504

RH135

RH89

RH136

U13

RC42

RC58

+VCCSFR_ OC_1

+VCCSFR_ OC_2

CPU

RH86

RH104

UC6

UC7

J37

+3VALW_ TPM

+3VS_WL AN

+3VALW_ DSW

+3VALW_PCH _PRI M

+3VALW_ HDA

+1.0VALW_ PRIM

+1.0VALW _PCH

RH137 RH138 LH3 RH113 LH1 LH2 RH140 RH141

JC1

RC44

+3VS

TPM

WLAN CARD

+3V_LAN

LAN

PCH

+3V_PTP

PCH

+1.0VALW_D CPDS W +1.0VALW_V CCCL K +1.0VALW_V CCCL K5 +1.0VALW_ MPHY +1.0VALW_A MPHYP LL +1.0VALW_AU SB_AZ PLL +1.0VALW_P RIMAL 22 +1.0VALW_P RIMAD 15

+1.0V_VC CST

+1.0VS_VC CSTG

PU1101

U12

U14

U2012

MIC1

U2600

JTP1

JHDD1

R212

RH87

PCH

CPU

+1.5VS

PJ704

PJ1102

G-SENSOR

CODEC

D-MIC

TPM

HDD

CRT

+1.05VSD GPU

+3VSDGPU _AON

+3VSDGPU_ MAIN

+3VS_WL AN

+LCDVDD

+3VS_VCC ATS

GPU

WLAN CARD

PANEL

PCH

B B

A A

+19VB

PU402

PJ402

L11

+5VALW

+INVPWR _B+

PANEL

UC7

PU501

U25

U26

JUSB3

U11

PJ502

TO USB/B

J36

+0.675VS _VTT

+USB3_V CCA

+USB3_V CCB

+5VS

CPU

DIMM

USB

JHDD1

JODD1

U31

FAN

U10

+VDDA

+5VS_BL

CODEC

KB BackLight

HDD

ODD

U66

U52

+5VS_OD D

+HDMI_5V _OUT

ODD

HDMI

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2014/12/31 2016/12/31

Deciphered Date

Compal Electronics, Inc.

Title

Power Map

Size

Document Number Rev

A4WAD M/B LA-C871P

Date: Sheet of

Date: Sheet o f

4 61Monday, July 13, 2015

+1.0VS_VC CSTG

RC44

1.0

Vinaﬁx.com

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PWR Sequence_SKL-H_DDR3

297.7u s

4.74us

948.5u s

262.9u s

SVID

5.863u s

tcpu22 :27.35u s

tplt18 :171.3u s

2.582m s

2.212m s

7.326u s

14.86u s

tcpu28 :24.37u s

tpch29 :7.457m s

7.874u s

10.61m s

7.229m s

tpch26 :212.4u s

POWER ON

+RTCVCC

PCH_RTCRST#

1 1

2 2

3 3

4 4

+3VALW_DSW

EC_RSMRST#

PM_BATLOW#

+3VALW

+1.0VALW

PM_SLP_S0#

SUSPWRDNACK

AC_PRESENT_R

PBTN_OUT#_R

ON/OFFBTN#

PM_SLP_S0#

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

+3VS_WLAN

PCH_THERMTRIP#

+1.0V_VCCST

+1.0V_VCCSTG

H_CPUPWRGD

+VCCIO

+1.35V_VDDQ

+VCCSA

+0.675VS_VTT

DDR_PG_CTRL

VR_PWRGD

EC_VCCST_PG

PCH_PWROK

VR_ON

CPU_SVID_DAT

SYS_PWROK

PLT_RST#

+VCCCORE

+VCCGT

DDR_DRAMRST#

CPU_BCLK

tPCH02 :160.4m s

tPCH03 :191.3m s

194.3m s

tPLT01 :140.7m s

tPLT02 :6.9us

tPCH43 :119.3m s

317.1m s

45ms

30ms

37.91u s

35.89u s

128.3m s

14.19m s tCPU04 :1.42ms

tCPU00 :761.4m s

tCPU10 :763.4m s

tCPU12 :765.4m s

tCPU09 :733.4m s

12.33m s

17.74u s

12.17m s

12.78m s

tCPU16 :38.48m s

10.82m s

29.82m s

120.7m s

tPLT15 :313.1m s

346.2m s

5.321s

2.433s

tpch25 :248.8n s

1.597s

S3 Resume

4.289m s

3.571m s

3.327m s

359.4m s

4.554m s

25.61m s

13.41m s

13.91m s

26.01m s

13.5ms

33.61m s

24.49m s

144.4m s

360.6m s

362.6m s

POWER OFF

SVID

3.914s

305.2u s

1.481s

3.993s

8.8us

110.15 us

172.4u s

109.1u s

121.2u s

988.9u s

211.6u s

1.559m s

7.38us

14.552 us

5.6us

9.370m s

15.39u s

1.508m s

11.05m s

10.01m s

107.4u s

8.582s

8.542s

8.442s

8.692s

8.242s

8.762s

8.692s

48.94m s

1.19ms

4.056m s

1.108m s

2.464m s

+RTCVCC

PCH_RTCRST#

+3VALW_DSW

EC_RSMRST#

PM_BATLOW#

+3VALW

+1.0VALW

PM_SLP_S0#

SLP_A#

SUSP#

SYSON

SUSPWRDNACK

AC_PRESENT_R

PBTN_OUT#_R

ON/OFFBTN#

PM_SLP_S0#

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

+3VS_WLAN

PCH_THERMTRIP#

+1.0V_VCCST

+1.0V_VCCSTG

H_CPUPWRGD

+VCCIO

+1.35V_VDDQ

+VCCSA

+0.675VS_VTT

DDR_PG_CTRL

VR_PWRGD

EC_VCCST_PG

PCH_PWROK

VR_ON

CPU_SVID_DAT

SYS_PWROK

PLT_RST#

+VCCCORE

+VCCGT

DDR_DRAMRST#

CPU_BCLK

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRETINFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRETINFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRETINFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BYOR DISCLOSEDTO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OFCOMPAL ELECTRONICS, INC.

MAY BE USED BYOR DISCLOSEDTO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OFCOMPAL ELECTRONICS, INC.

2014/12/31 2016/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Power Sequence

Size

Document Number Re v

A4WAD M/B LA-C871P

Date: Sheet of

5 61Monday, July 13, 2015

1.0

smd.db-x7.ru

UC1

+1.0VALW_XDP+1.0VALW_PRIM

JTAG/RC/HOOKS

QJJR

QJJR@

SA000095Z10

VCCOBS_AB

XDP_TRST*

XDP_TDI

XDP_TMS XDP_TCK0 XDP_TCK1

XDP_TDO

XDP_PREQ* XDP_PRDY*

HOOK_0 HOOK_3 HOOK_6

XDP_PRSNT_PCH* XDP_PRSNT_CPU*

GND

<MT> GND

QHR7

QHR7@

SA00008RP00

+1.0VALW_XDP

XDP_TRST#

XDP_TDI

XDP_TMS

XDP_TCK0

XDP_TCK1

XDP_TDO

XDP_PREQ#

XDP_PRDY#

XDP_HOOK0

XDP_HOOK3

XDP_HOOK6

XDP_PRSENT_PCH

XDP_PRSENT_CPU

23 19

QHPW

QHPW@

SA00008RQ00

XDP_PREQ# (9,22) XDP_PRDY# (9,22)

QJJQ

QJJQ@

SA000096Q00

SKYLAKE_HALO

1 1

CPU_DP1_P0(32)

CPU_DP1_AUXP(32) CPU_DP1_AUXN(32)

XDP_SPI_SI

CPU_XDP_TMS CPU_XDP_TDI

CFG0

CPU_DP1_N0(32) CPU_DP1_P1(32) CPU_DP1_N1(32)

CPU_DP1_AUXP CPU_DP1_AUXN

CPU_DP2_P0(31) CPU_DP2_N0(31) CPU_DP2_P1(31) CPU_DP2_N1(31) CPU_DP2_P2(31) CPU_DP2_N2(31) CPU_DP2_P3(31) CPU_DP2_N3(31)

CPU_XDP_TDO(9,18) CPU_XDP_TDI(9,18) CPU_XDP_TMS(9,18)

CPU_XDP_TCK0(9,18)

CPU_XDP_TRST#(9,22) PCH_JTAG_TCK1(18)

XDP_SPI_IO2(17)

XDP_SPI_SI(17)

XDP_ITP_PMODE(18)

EC_RSMRST#(18,39)

DP Aux (Port B for VGA)

<HDMI>

DDI Port2 Mapping

2 2

+3VALW_PCH_PRIM

1 2

RC2 1K_0402_5%

+1.0VS_VCCSTG

3 3

Place to CPU side

4 4

Place to CPU side

RC4 51_0402_5%CMC@ RC5 51_0402_5%CMC@ RC6 51_0402_5%CMC@ RC59 51_0402_5%CMC@

+1.0VALW_XDP

RC8 2.2K_0402_5%CMC@

RC10 0_0402_5%@ RC11 0_0402_5%@

RC13 51_0402_1%CMC@ RC15 51_0402_5%@ RC17 51_0402_5%@

RC60 1K_0402_5%@

1 2

12 12 12 12

12 12

12 12 12

CPU_XDP_TDO CPU_XDP_TDO

XDP_ITP_PMODE

XDP_PRSENT_CPU XDP_PRSENT_PCH

CPU_XDP_TCK0 PCH_JTAG_TCK1 CPU_XDP_TRST#

K36 K37 J35 J34 H37 H36 J37 J38

D27 E27

H34 H33 F37 G38 F34 F35 E37 E36

F26 E26

C34 D34 B36 B34 F33 E33 C33 B33

A27 B27

SKL-H_BGA1440

UC1D

DDI1_TXP[0] DDI1_TXN[0] DDI1_TXP[1] DDI1_TXN[1] DDI1_TXP[2] DDI1_TXN[2] DDI1_TXP[3] DDI1_TXN[3]

DDI1_AUXP DDI1_AUXN

DDI2_TXP[0] DDI2_TXN[0] DDI2_TXP[1] DDI2_TXN[1] DDI2_TXP[2] DDI2_TXN[2] DDI2_TXP[3] DDI2_TXN[3]

DDI2_AUXP DDI2_AUXN

DDI3_TXP[0] DDI3_TXN[0] DDI3_TXP[1] DDI3_TXN[1] DDI3_TXP[2] DDI3_TXN[2] DDI3_TXP[3] DDI3_TXN[3]

DDI3_AUXP DDI3_AUXN

BGA1440

4 OF 14

CPU_XDP_TDO CPU_XDP_TDI CPU_XDP_TMS CPU_XDP_TCK0

CPU_XDP_TRST# PCH_JTAG_TCK1

CFG3 XDP_SPI_IO2

XDP_SPI_SI XDP_ITP_PMODE XDP_HOOK6

EDP_TXP[0] EDP_TXN[0] EDP_TXP[1] EDP_TXN[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXP EDP_AUXN

EDP_DISP_UTIL

EDP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

CMC@

RPC1

1 8 2 7 3 6 4 5

0_0804_8P4R_5%

CMC@

RPC2

1 8 2 7 3 6 4 5

0_0804_8P4R_5%

CMC@

RPC3

1 8 2 7 3 6 4 5

0_0804_8P4R_5%

1 2

CMC@

RC56 1K_0402_5%

D29 E29 F28 E28 B29 A29 B28 C28

C26 B26

A33

D37

G27 G25 G29

?REV = 1

XDP_TDO XDP_TDI XDP_TMS XDP_TCK0

XDP_TRST#

XDP_TCK1 XDP_PRSENT_CPU XDP_PRSENT_PCH

XDP_HOOK3

XDP_HOOK0EC_RSMRST#

EDP_TXP0 (30) EDP_TXN0 (30) EDP_TXP1 (30) EDP_TXN1 (30) EDP_TXN2 (30) EDP_TXP2 (30) EDP_TXN3 (30) EDP_TXP3 (30)

EDP_AUXP (30)

EDP_AUXN (30)

EDP_COMP

CAD note: Trace width=20 mils,Spacing=25mil,Max length=100mils

CPU_DISPA_SDI

RC47 20_0402_1%

RC124.9_0402_1%

CFG0(9) CFG1(9) CFG2(9) CFG3(9) CFG4(9) CFG5(9) CFG6(9) CFG7(9)

CFG17(9) CFG16(9)

CFG8(9)

CFG9(9) CFG10(9) CFG11(9) CFG12(9) CFG13(9) CFG14(9) CFG15(9)

CFG19(9) CFG18(9)

<eDP>

+VCCIO

CPU_DISPA_BCLK_R (18) CPU_DISPA_SDO_R (18)

CPU_DISPA_SDI_R (18)

JPCMC1

CFG0

DATA_0

CFG1

DATA_1

CFG2

DATA_2

CFG3

DATA_3

CFG4

DATA_4

CFG5

DATA_5

CFG6

DATA_6

CFG7

DATA_7

CFG17

DATA_CLK_1P

CFG16

DATA_CLK_1N

CFG8

DATA_8

CFG9

DATA_9

CFG10

DATA_10

CFG11

DATA_11

CFG12

DATA_12

CFG13

DATA_13

CFG14

DATA_14

CFG15

DATA_15

CFG19

DATA_CLK_2P

CFG18

DATA_CLK_2N

INTEL_CMC_PRIMARY

CONN@

CMC CONN

RC3 0_0603_5%@

OBS DATA

CMC_DEBUG_36P

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/12/31 2016/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date: Sheet of

Compal Electronics, Inc.

SKL-H(1/9)DDI,EDP

Custom

A4WAD M/B LA-C871P

1.0

6 61Monday, July 13, 2015

1.0

Vinaﬁx.com

smd.db-x7.ru

Interleaved Memory

1 1

DDR_A_D[0..15](14)

DDR_A_D[16..31](14)

2 2

DDR_A_D[32..47](14)

DDR_A_D[48..63](14)

3 3

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

UC1A

BR6

DDR0_DQ[0]

BT6

DDR0_DQ[1]

BP3

DDR0_DQ[2]

BR3

DDR0_DQ[3]

BN5

DDR0_DQ[4]

BP6

DDR0_DQ[5]

BP2

DDR0_DQ[6]

BN3

DDR0_DQ[7]

BL4

DDR0_DQ[8]

BL5

DDR0_DQ[9]

BL2

DDR0_DQ[10]

BM1

DDR0_DQ[11]

BK4

DDR0_DQ[12]

BK5

DDR0_DQ[13]

BK1

DDR0_DQ[14]

BK2

DDR0_DQ[15]

BG4

DDR0_DQ[16]/DDR0_DQ[32]

BG5

DDR0_DQ[17]/DDR0_DQ[33]

BF4

DDR0_DQ[18]/DDR0_DQ[34]

BF5

DDR0_DQ[19]/DDR0_DQ[35]

BG2

DDR0_DQ[20]/DDR0_DQ[36]

BG1

DDR0_DQ[21]/DDR0_DQ[37]

BF1

DDR0_DQ[22]/DDR0_DQ[38]

BF2

DDR0_DQ[23]/DDR0_DQ[39]

BD2

DDR0_DQ[24]/DDR0_DQ[40]

BD1

DDR0_DQ[25]/DDR0_DQ[41]

BC4

DDR0_DQ[26]/DDR0_DQ[42]

BC5

DDR0_DQ[27]/DDR0_DQ[43]

BD5

DDR0_DQ[28]/DDR0_DQ[44]

BD4

DDR0_DQ[29]/DDR0_DQ[45]

BC1

DDR0_DQ[30]/DDR0_DQ[46]

BC2

DDR0_DQ[31]/DDR0_DQ[47]

AB1

DDR0_DQ[32]/DDR1_DQ[0]

AB2

DDR0_DQ[33]/DDR1_DQ[1]

AA4

DDR0_DQ[34]/DDR1_DQ[2]

AA5

DDR0_DQ[35]/DDR1_DQ[3]

AB5

DDR0_DQ[36]/DDR1_DQ[4]

AB4

DDR0_DQ[37]/DDR1_DQ[5]

AA2

DDR0_DQ[38]/DDR1_DQ[6]

AA1

DDR0_DQ[39]/DDR1_DQ[7]

DDR0_DQ[40]/DDR1_DQ[8]

DDR0_DQ[41]/DDR1_DQ[9]

DDR0_DQ[42]/DDR1_DQ[10]

DDR0_DQ[43]/DDR1_DQ[11]

DDR0_DQ[44]/DDR1_DQ[12]

DDR0_DQ[45]/DDR1_DQ[13]

DDR0_DQ[46]/DDR1_DQ[14]

DDR0_DQ[47]/DDR1_DQ[15]

DDR0_DQ[48]/DDR1_DQ[32]

DDR0_DQ[49]/DDR1_DQ[33]

DDR0_DQ[50]/DDR1_DQ[34]

DDR0_DQ[51]/DDR1_DQ[35]

DDR0_DQ[52]/DDR1_DQ[36]

DDR0_DQ[53]/DDR1_DQ[37]

DDR0_DQ[54]/DDR1_DQ[38]

DDR0_DQ[55]/DDR1_DQ[39]

DDR0_DQ[56]/DDR1_DQ[40]

DDR0_DQ[57]/DDR1_DQ[41]

DDR0_DQ[58]/DDR1_DQ[42]

DDR0_DQ[59]/DDR1_DQ[43]

DDR0_DQ[60]/DDR1_DQ[44]

DDR0_DQ[61]/DDR1_DQ[45]

DDR0_DQ[62]/DDR1_DQ[46]

DDR0_DQ[63]/DDR1_DQ[47]

BA2

DDR0_ECC[0]

BA1

DDR0_ECC[1]

AY4

DDR0_ECC[2]

AY5

DDR0_ECC[3]

BA5

DDR0_ECC[4]

BA4

DDR0_ECC[5]

AY1

DDR0_ECC[6]

AY2

DDR0_ECC[7]

DDR CHANNEL A

SKL-H_BGA1440

REV = 1

SKYLAKE_HALO

BGA1440

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSN[7]/DDR1_DQSN[5]

1 OF 14

DDR0_CKP[0] DDR0_CKN[0] DDR0_CKN[1]

DDR0_CKP[1]

DDR0_CLKP[2]

DDR0_CLKN[2]

DDR0_CLKP[3]

DDR0_CLKN[3]

DDR0_CKE[0]

DDR0_CKE[1]

DDR0_CKE[2]

DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1]

DDR0_CS#[2]

DDR0_CS#[3] DDR0_ODT[0]

DDR0_ODT[1] DDR0_ODT[2] DDR0_ODT[3]

DDR0_MA[3] DDR0_MA[4]

DDR0_PAR

DDR0_ALERT#

DDR0_DQSN[0] DDR0_DQSN[1]

DDR0_DQSP[0] DDR0_DQSP[1]

DDR0_DQSP[8] DDR0_DQSN[8]

AG1 AG2 AK1 AK2 AL3 AK3 AL2 AL1

AT1 AT2 AT3 AT5

AD5 AE2 AD2 AE5

AD3 AE4 AE1 AD4

AH5 AH1 AU1

AH4 AG4 AD1

AH3 AP4 AN4 AP5 AP2 AP1 AP3 AN1 AN3 AT4 AH2 AN2 AU4 AE3 AU2 AU3

AG3 AU5

BR5 BL3 BG3 BD3 AB3 V3 R3 M3

BP5 BK3 BF3 BC3 AA3 U3 P3 L3

AY3 BA3

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK#1 DDR_A_CLK1

DDR_A_CKE0 DDR_A_CKE1

DDR_A_CS#0 DDR_A_CS#1

DDR_A_ODT0 DDR_A_ODT1

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_RAS# DDR_A_WE# DDR_A_CAS#

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_CLK0 (14) DDR_A_CLK#0 (14) DDR_A_CLK#1 (14) DDR_A_CLK1 (14)

DDR_A_CKE0 (14) DDR_A_CKE1 (14)

DDR_A_CS#0 (14) DDR_A_CS#1 (14)

DDR_A_ODT0 (14) DDR_A_ODT1 (14)

DDR_A_BS0 (14) DDR_A_BS1 (14) DDR_A_BS2 (14)

DDR_A_RAS# (14) DDR_A_WE# (14) DDR_A_CAS# (14)

DDR_A_MA0 (14) DDR_A_MA1 (14) DDR_A_MA2 (14) DDR_A_MA3 (14) DDR_A_MA4 (14) DDR_A_MA5 (14) DDR_A_MA6 (14) DDR_A_MA7 (14) DDR_A_MA8 (14) DDR_A_MA9 (14) DDR_A_MA10 (14) DDR_A_MA11 (14) DDR_A_MA12 (14) DDR_A_MA13 (14) DDR_A_MA14 (14) DDR_A_MA15 (14)

DDR_A_DQS#0 (14) DDR_A_DQS#1 (14) DDR_A_DQS#2 (14) DDR_A_DQS#3 (14) DDR_A_DQS4 (14) DDR_A_DQS5 (14) DDR_A_DQS6 (14) DDR_A_DQS7 (14)

DDR_A_DQS0 (14) DDR_A_DQS1 (14) DDR_A_DQS2 (14) DDR_A_DQS3 (14) DDR_A_DQS#4 (14) DDR_A_DQS#5 (14) DDR_A_DQS#6 (14) DDR_A_DQS#7 (14)

DDR CHANNEL B

SKYLAKE_HALO

BGA1440

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSP[5]/DDR1_DQSP[3]

2 OF 14

DDR1_CKP[0] DDR1_CKN[0] DDR1_CKN[1]

DDR1_CKP[1] DDR1_CLKP[2] DDR1_CLKN[2] DDR1_CLKP[3] DDR1_CLKN[3]

DDR1_CKE[0]

DDR1_CKE[1]

DDR1_CKE[2]

DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1]

DDR1_CS#[2]

DDR1_CS#[3]

DDR1_ODT[0]

DDR1_ODT[1]

DDR1_ODT[2]

DDR1_ODT[3]

DDR1_MA[3] DDR1_MA[4]

DDR1_PAR

DDR1_ALERT#

DDR1_DQSN[6] DDR1_DQSN[7]

DDR1_DQSP[6] DDR1_DQSP[7]

DDR1_DQSP[8] DDR1_DQSN[8]

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

AM9 AN9 AM8 AM7 AM11 AM10 AJ10 AJ11

AT8 AT10 AT7 AT11

AF11 AE7 AF10 AE10

AF7 AE8 AE9 AE11

AH10 AH11 AF8

AH8 AH9 AR9

AJ9 AK6 AK5 AL5 AL6 AM6 AN7 AN10 AN8 AR11 AH7 AN11 AR10 AF9 AR7 AT9

AJ7 AR8

BP9 BL9 BG9 BC9 AC9 W9 R9 M9

BR9 BJ9 BF9 BB9 AA9 V9 P9 L9

AW9 AY9

BN13 BP13 BR13

DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK#1 DDR_B_CLK1

DDR_B_CKE0 DDR_B_CKE1

DDR_B_CS#0 DDR_B_CS#1

DDR_B_ODT0 DDR_B_ODT1

DDR_B_RAS# DDR_B_WE# DDR_B_CAS#

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

+0.675V_VREFCA +0.675V_A_VREFDQ +0.675V_B_VREFDQ

DDR_B_CLK0 (15) DDR_B_CLK#0 (15) DDR_B_CLK#1 (15) DDR_B_CLK1 (15)

DDR_B_CKE0 (15) DDR_B_CKE1 (15)

DDR_B_CS#0 (15) DDR_B_CS#1 (15)

DDR_B_ODT0 (15) DDR_B_ODT1 (15)

DDR_B_RAS# (15) DDR_B_WE# (15) DDR_B_CAS# (15)

DDR_B_BS0 (15) DDR_B_BS1 (15) DDR_B_BS2 (15)

DDR_B_MA0 (15) DDR_B_MA1 (15) DDR_B_MA2 (15) DDR_B_MA3 (15) DDR_B_MA4 (15) DDR_B_MA5 (15) DDR_B_MA6 (15) DDR_B_MA7 (15) DDR_B_MA8 (15) DDR_B_MA9 (15) DDR_B_MA10 (15) DDR_B_MA11 (15) DDR_B_MA12 (15) DDR_B_MA13 (15) DDR_B_MA14 (15) DDR_B_MA15 (15)

DDR_B_DQS#0 (15) DDR_B_DQS#1 (15) DDR_B_DQS#2 (15) DDR_B_DQS#3 (15) DDR_B_DQS#4 (15) DDR_B_DQS#5 (15) DDR_B_DQS#6 (15) DDR_B_DQS#7 (15)

DDR_B_DQS0 (15) DDR_B_DQS1 (15) DDR_B_DQS2 (15) DDR_B_DQS3 (15) DDR_B_DQS4 (15) DDR_B_DQS5 (15) DDR_B_DQS6 (15) DDR_B_DQS7 (15)

+0.675V_VREFCA +0.675V_A_VREFDQ +0.675V_B_VREFDQ

DDR_B_D[0..15](15)

DDR_B_D[16..31](15)

DDR_B_D[32..47](15)

DDR_B_D[48..63](15)

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

SM_RCOMP0

RC19121_0402_1%

SM_RCOMP1

RC2075_0402_1%

SM_RCOMP2

RC21100_0402_1%

UC1B

BT11

DDR1_DQ[0]/DDR0_DQ[16]

BR11

DDR1_DQ[1]/DDR0_DQ[17]

BT8

DDR1_DQ[2]/DDR0_DQ[18]

BR8

DDR1_DQ[3]/DDR0_DQ[19]

BP11

DDR1_DQ[4]/DDR0_DQ[20]

BN11

DDR1_DQ[5]/DDR0_DQ[21]

BP8

DDR1_DQ[6]/DDR0_DQ[22]

BN8

DDR1_DQ[7]/DDR0_DQ[23]

BL12

DDR1_DQ[8]/DDR0_DQ[24]

BL11

DDR1_DQ[9]/DDR0_DQ[25]

BL8

DDR1_DQ[10]/DDR0_DQ[26]

BJ8

DDR1_DQ[11]/DDR0_DQ[27]

BJ11

DDR1_DQ[12]/DDR0_DQ[28]

BJ10

DDR1_DQ[13]/DDR0_DQ[29]

BL7

DDR1_DQ[14]/DDR0_DQ[30]

BJ7

DDR1_DQ[15]/DDR0_DQ[31]

BG11

DDR1_DQ[16]/DDR0_DQ[48]

BG10

DDR1_DQ[17]/DDR0_DQ[49]

BG8

DDR1_DQ[18]/DDR0_DQ[50]

BF8

DDR1_DQ[19]/DDR0_DQ[51]

BF11

DDR1_DQ[20]/DDR0_DQ[52]

BF10

DDR1_DQ[21]/DDR0_DQ[53]

BG7

DDR1_DQ[22]/DDR0_DQ[54]

BF7

DDR1_DQ[23]/DDR0_DQ[55]

BB11

DDR1_DQ[24]/DDR0_DQ[56]

BC11

DDR1_DQ[25]/DDR0_DQ[57]

BB8

DDR1_DQ[26]/DDR0_DQ[58]

BC8

DDR1_DQ[27]/DDR0_DQ[59]

BC10

DDR1_DQ[28]/DDR0_DQ[60]

BB10

DDR1_DQ[29]/DDR0_DQ[61]

BC7

DDR1_DQ[30]/DDR0_DQ[62]

BB7

DDR1_DQ[31]/DDR0_DQ[63]

AA11

DDR1_DQ[32]/DDR1_DQ[16]

AA10

DDR1_DQ[33]/DDR1_DQ[17]

AC11

DDR1_DQ[34]/DDR1_DQ[18]

AC10

DDR1_DQ[35]/DDR1_DQ[19]

AA7

DDR1_DQ[36]/DDR1_DQ[20]

AA8

DDR1_DQ[37]/DDR1_DQ[21]

AC8

DDR1_DQ[38]/DDR1_DQ[22]

AC7

DDR1_DQ[39]/DDR1_DQ[23]

DDR1_DQ[40]/DDR1_DQ[24]

DDR1_DQ[41]/DDR1_DQ[25]

V10

DDR1_DQ[42]/DDR1_DQ[26]

V11

DDR1_DQ[43]/DDR1_DQ[27]

W11

DDR1_DQ[44]/DDR1_DQ[28]

W10

DDR1_DQ[45]/DDR1_DQ[29]

DDR1_DQ[46]/DDR1_DQ[30]

DDR1_DQ[47]/DDR1_DQ[31]

R11

DDR1_DQ[48]

P11

DDR1_DQ[49]

DDR1_DQ[50]

DDR1_DQ[51]

R10

DDR1_DQ[52]

P10

DDR1_DQ[53]

DDR1_DQ[54]

DDR1_DQ[55]

L11

DDR1_DQ[56]

M11

DDR1_DQ[57]

DDR1_DQ[58]

DDR1_DQ[59]

L10

DDR1_DQ[60]

M10

DDR1_DQ[61]

DDR1_DQ[62]

DDR1_DQ[63]

AW11

DDR1_ECC[0]

AY11

DDR1_ECC[1]

AY8

DDR1_ECC[2]

AW8

DDR1_ECC[3]

AY10

DDR1_ECC[4]

AW10

DDR1_ECC[5]

AY7

DDR1_ECC[6]

AW7

DDR1_ECC[7]

DDR_RCOMP[0]

DDR_RCOMP[1]

DDR_RCOMP[2]

SKL-H_BGA1440

REV = 1 ?

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/12/31 2016/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date: Sheet of

SKL-H(2/9)DDRIII

A4WAD M/B LA-C871P

Monday, July 13, 2015

1.0

smd.db-x7.ru

1 1

E25 D25

E24 F24

E23 D23

E22 F22

E21 D21

E20 F20

E19 D19

E18

2 2

3 3

PCIE_CRX_C_GTX_P7(23) PCIE_CRX_C_GTX_N7(23)

PCIE_CRX_C_GTX_P6(23) PCIE_CRX_C_GTX_N6(23)

PCIE_CRX_C_GTX_P5(23) PCIE_CRX_C_GTX_N5(23)

PCIE_CRX_C_GTX_P4(23) PCIE_CRX_C_GTX_N4(23)

PCIE_CRX_C_GTX_P3(23) PCIE_CRX_C_GTX_N3(23)

PCIE_CRX_C_GTX_P2(23) PCIE_CRX_C_GTX_N2(23)

PCIE_CRX_C_GTX_P1(23) PCIE_CRX_C_GTX_N1(23)

PCIE_CRX_C_GTX_P0(23) PCIE_CRX_C_GTX_N0(23)

CAD note: Trace width=12 mils,Spacing=15mil,Max length=400mils

CC49 0.22U_0402_16V7KVGM@ CC50 0.22U_0402_16V7KVGM@

CC51 0.22U_0402_16V7KVGM@ CC52 0.22U_0402_16V7KVGM@

CC57 0.22U_0402_16V7KVGM@ CC58 0.22U_0402_16V7KVGM@

CC59 0.22U_0402_16V7KVGM@ CC60 0.22U_0402_16V7KVGM@

CC61 0.22U_0402_16V7KVGA@ CC62 0.22U_0402_16V7KVGA@

CC63 0.22U_0402_16V7KVGA@ CC64 0.22U_0402_16V7KVGA@

CC65 0.22U_0402_16V7KVGA@ CC66 0.22U_0402_16V7KVGA@

CC67 0.22U_0402_16V7KVGA@ CC68 0.22U_0402_16V7KVGA@

1 2 1 2

+VCCIO

DMI_CRX_PTX_P0(16) DMI_CRX_PTX_N0(16)

DMI_CRX_PTX_P1(16) DMI_CRX_PTX_N1(16)

DMI_CRX_PTX_P2(16) DMI_CRX_PTX_N2(16)

DMI_CRX_PTX_P3(16) DMI_CRX_PTX_N3(16)

1 2

RC22 24.9_0402_1%

PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7

PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5

PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4

PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0

PEG_RCOMP

DMI_CRX_PTX_P0 DMI_CRX_PTX_N0

DMI_CRX_PTX_P1 DMI_CRX_PTX_N1

DMI_CRX_PTX_P2 DMI_CRX_PTX_N2

DMI_CRX_PTX_P3 DMI_CRX_PTX_N3

F18 D17

E17 F16

E16 D15

E15 F14

E14 D13

E13 F12

E12 D11

E11 F10

E10

D8 E8

E6 F6

D5 E5

J8 J9

SKL-H_BGA1440

UC1C

PEG_RXP[0] PEG_RXN[0]

PEG_RXP[1] PEG_RXN[1]

PEG_RXP[2] PEG_RXN[2]

PEG_RXP[3] PEG_RXN[3]

PEG_RXP[4] PEG_RXN[4]

PEG_RXP[5] PEG_RXN[5]

PEG_RXP[6] PEG_RXN[6]

PEG_RXP[7] PEG_RXN[7]

PEG_RXP[8] PEG_RXN[8]

PEG_RXP[9] PEG_RXN[9]

PEG_RXP[10] PEG_RXN[10]

PEG_RXP[11] PEG_RXN[11]

PEG_RXP[12] PEG_RXN[12]

PEG_RXP[13] PEG_RXN[13]

PEG_RXP[14] PEG_RXN[14]

PEG_RXP[15] PEG_RXN[15]

PEG_RCOMP

DMI_RXP[0] DMI_RXN[0]

DMI_RXP[1] DMI_RXN[1]

DMI_RXP[2] DMI_RXN[2]

DMI_RXP[3] DMI_RXN[3]

REV = 1

SKYLAKE_HALO

BGA1440

3 OF 14

PEG_TXP[0]

PEG_TXN[0] PEG_TXP[1]

PEG_TXN[1] PEG_TXP[2]

PEG_TXN[2] PEG_TXP[3]

PEG_TXN[3] PEG_TXP[4]

PEG_TXN[4] PEG_TXP[5]

PEG_TXN[5] PEG_TXP[6]

PEG_TXN[6] PEG_TXP[7]

PEG_TXN[7] PEG_TXP[8]

PEG_TXN[8] PEG_TXP[9]

PEG_TXN[9]

PEG_TXP[10] PEG_TXN[10]

PEG_TXP[11] PEG_TXN[11]

PEG_TXP[12] PEG_TXN[12]

PEG_TXP[13] PEG_TXN[13]

PEG_TXP[14] PEG_TXN[14]

PEG_TXP[15] PEG_TXN[15]

DMI_TXP[0]

DMI_TXN[0]

DMI_TXP[1]

DMI_TXN[1]

DMI_TXP[2]

DMI_TXN[2]

DMI_TXP[3]

DMI_TXN[3]

B25 A25

B24 C24

B23 A23

B22 C22

B21 A21

B20 C20

B19 A19

B18 C18

A17 B17

C16 B16

A15 B15

C14 B14

A13 B13

C12 B12

A11 B11

C10 B10

B8 A8

C6 B6

B5 A5

D4 B4

PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7

PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6

PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5

PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4

PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3

PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0

DMI_CTX_PRX_P0 DMI_CTX_PRX_N0

DMI_CTX_PRX_P1 DMI_CTX_PRX_N1

DMI_CTX_PRX_P2 DMI_CTX_PRX_N2

DMI_CTX_PRX_P3 DMI_CTX_PRX_N3

12 12

DMI_CTX_PRX_P0 (16) DMI_CTX_PRX_N0 (16)

DMI_CTX_PRX_P1 (16) DMI_CTX_PRX_N1 (16)

DMI_CTX_PRX_P2 (16) DMI_CTX_PRX_N2 (16)

DMI_CTX_PRX_P3 (16) DMI_CTX_PRX_N3 (16)

CC30.22U_0402_16V7K VGM@ CC40.22U_0402_16V7K VGM@

CC50.22U_0402_16V7K VGM@ CC60.22U_0402_16V7K VGM@

CC70.22U_0402_16V7K VGM@ CC80.22U_0402_16V7K VGM@

CC90.22U_0402_16V7K VGM@ CC100.22U_0402_16V7K VGM@

CC110.22U_0402_16V7K VGA@ CC120.22U_0402_16V7K VGA@

CC130.22U_0402_16V7K VGA@ CC140.22U_0402_16V7K VGA@

CC150.22U_0402_16V7K VGA@ CC160.22U_0402_16V7K VGA@

CC170.22U_0402_16V7K VGA@ CC180.22U_0402_16V7K VGA@

PCIE_CTX_C_GRX_P7 (23) PCIE_CTX_C_GRX_N7 (23)

PCIE_CTX_C_GRX_P6 (23) PCIE_CTX_C_GRX_N6 (23)

PCIE_CTX_C_GRX_P5 (23) PCIE_CTX_C_GRX_N5 (23)

PCIE_CTX_C_GRX_P4 (23) PCIE_CTX_C_GRX_N4 (23)

PCIE_CTX_C_GRX_P3 (23) PCIE_CTX_C_GRX_N3 (23)

PCIE_CTX_C_GRX_P2 (23) PCIE_CTX_C_GRX_N2 (23)

PCIE_CTX_C_GRX_P1 (23) PCIE_CTX_C_GRX_N1 (23)

PCIE_CTX_C_GRX_P0 (23) PCIE_CTX_C_GRX_N0 (23)

4 4

Security Classification

2014/12/31 2016/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/12/31 2016/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-H(3/9) PEG,DMI

Size Document Number Re v

Custom

A4WAD M/B LA-C871P

Date: Sheet of

8 61Monday, July 13, 2015

1.0

smd.db-x7.ru

SKYLAKE_HALO

BGA1440

5 OF 14

REV = 1 ?

+1.0V_VCCST

1 2

RC27 1K_0402_5%

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8]

CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[17] CFG[16] CFG[19] CFG[18]

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

PROC_TDO

PROC_TDI PROC_TMS PROC_TCK

PROC_TRST# PROC_PREQ# PROC_PRDY#

CFG_RCOMP

+1.0VS_VCCSTG

From EC(open-drain)

H_PROCHOT#(39,46)

BN25 BN27 BN26 BN28 BR20 BM20 BT20 BP20 BR23 BR22 BT23 BT22 BM19 BR19 BP19 BT19

BN23 BP23 BP22 BN22

XDP_BPM#0

BR27

XDP_BPM#1

BT27 BM31 BT30

CPU_XDP_TDO

BT28

CPU_XDP_TDI

BL32

CPU_XDP_TMS

BP28

CPU_XDP_TCK0

BR28

CPU_XDP_TRST#

BP30

XDP_PREQ#

BL30

XDP_PRDY#SKL_CNL_N

BP27

CFG_RCOMP

BT25

THERMTRIP#

RC31 1K_0402_5%

1 2

RC33 499_0402_1%

RC23 49.9_0402_1%

1 2

CFG0 (6) CFG1 (6) CFG2 (6) CFG3 (6) CFG4 (6) CFG5 (6) CFG6 (6) CFG7 (6) CFG8 (6) CFG9 (6) CFG10 (6) CFG11 (6) CFG12 (6) CFG13 (6) CFG14 (6) CFG15 (6)

CFG17 (6) CFG16 (6) CFG19 (6) CFG18 (6)

PAD

T3822

PAD

T3823

CPU_XDP_TDO (6,18) CPU_XDP_TDI (6,18) CPU_XDP_TMS (6,18) CPU_XDP_TCK0 (6,18)

CPU_XDP_TRST# (6,22) XDP_PREQ# (6,22) XDP_PRDY# (6,22)

PROCHOT

CFG4

CFG5

CFG2

ESD Reserve ,pleace close to cpu. 12/30

H_CPUPW RGD

PROCHOT

THERMTRIP#

1 2

RC24 1K_0402_1%

1 2

RC26 1K_0402_1%

1 2

RC29 1K_0402_1%

1 2

CH49 .1U_0402_16V7K

1 2

CH50 .1U_0402_16V7K

1 2

CH51 .1U_0402_16V7K

D35 C36

D31

BH31 BH32 BH29 BR30

BT13

H13

BT31 BP35 BM34 BP31

BT34

BR33

BN1

BM30

B31 A32

E31

J31

UC1E

BCLKP BCLKN

PCI_BCLKP PCI_BCLKN

CLK24P CLK24N

VIDALERT# VIDSCK VIDSOUT PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD PROCPWRGD

RESET# PM_SYNC PM_DOWN PECI THERMTRIP#

SKTOCC# PROC_SELECT#

CATERR#

SKL-H_BGA1440

CPU_SVID_ALERT# CPU_SVID_CLK CPU_SVID_DAT

PROCHOT

DDR_PG_CTRL

EC_VCCST_PG

H_CPUPW RGD PLTRST_CPU# H_PM_SYNC PM_DOW N H_PECI

THERMTRIP#

T4 PAD

EC_VCCST_PG

CPU_BCLK CPU_BCLK#

CPU_PCIBCLK CPU_PCIBCLK#

CPU_24M CPU_24M#

H_CATERR#

PM_DOW N

CPU_BCLK(19) CPU_BCLK#(19)

CPU_PCIBCLK(19) CPU_PCIBCLK#(19)

CPU_24M(19)

1 1

H_SKTOCC#(18)

2 2

From EC OD output

EC_VCCST_PG_R(39,43)

3 3

PM_DOW N_R(17)

H_SKTOCC# H_SKTOCC#_R

1 2

RC32 1K_0402_5%

CPU_24M#(19)

CPU_SVID_CLK(52)

H_CPUPW RGD(18) PLTRST_CPU#(17) H_PM_SYNC(17)

H_PECI(17,39)

THERMTRIP#(17)

1 2

RC57 0_0402_5%@

1 2

RC34 0_0402_5%@

FLOAT FOR SKL GND FOR CNL

+1.0V_VCCST

RC25 1K_0402_5%

RC28 60.4_0402_1%

RC30 20_0402_1%

1 2

Reference SKL EDS 0.85 Table 6-8CFG signals internal PH default value = 1

Description

Stall reset sequence after PCU PLL

CFG[0]

CFG[4]

CFG[7]

lock until de-asserted — 1 = (Default) Normal Operation;

No stall. — 0 = Stall.

Enable eDP — 1 = Disabled. — 0 = Enabled.

PEG Training: — 1 = (default) PEG Train immediately

following RESET# de assertion. — 0 = PEG Wait for BIOS for training

CFG[1] CFG[3]

Reserved configuration lane.

CFG[8:19]

PCIE pore assign

Config. Signals

1 x 16 1 x 16

reverse 2 x 8

2 x 8

reverse 1 x 8 + 2 x 4 1x8+2x4

@EMC@

reverse

CFG[2]CFG[5]CFG[6] 1 1 1 1 1 1 1 1

0 0 0 00

0 0 0

DDR_VTT_CNTL to DDR VTT supplied ramped

SVID ALERT

+1.0V_VCCST

CPU_SVID_ALERT#

1 2

RC35 56_0402_5%

1 2

RC37 220_0402_5%

Place the PU resistors close to CPU

CPU_SVID_ALERT#_R (52)

Follow PDG1.0 Table 12-16

(To VR)

4 4

SVID DATA

+1.0V_VCCST

CPU_SVID_DAT

1 2

RC39 100_0402_1%

Place the PU resistors close to CPU

CPU_SVID_DAT (52)

(To VR)

<35uS (tCPU18)

DDR_PG_CTRL

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NC1VCC

GND

74AUP1G07GW_TSSOP5

2014/12/31 2016/12/31

+1.35V_VDDQ

+3VS

CC19.1U_0402_16V7K

UC3

Compal Secret Data

Deciphered Date

RC36 220K_0402_5%

RC38 2M_0402_5%@

1 2

CRB 330K

SM_PG_CTRL (48)

Compal Electronics, Inc.

Title

SKL-H(4/9)CLK,GPIO

Size Document Number Re v

Custom

A4WAD M/B LA-C871P

Date: Sheet of

9 61Monday, July 13, 2015

1.0

smd.db-x7.ru

1 1

VCC 27A (U 15W Dual Core GT2)

+VCCCORE +VCCCORE

2 2

3 3

AA13 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AA38 AB29 AB30 AB31 AB32 AB35 AB36 AB37 AB38 AC13 AC14 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AC36 AD13 AD14 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AE13 AE14 AE30 AE31 AE32 AE35 AE36 AE37 AE38 AF35 AF36 AF37 AF38

K13 K14

N13 N14 N30 N31 N32 N35 N36 N37 N38 P13

L13

UC1G

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

SKL-H_BGA1440

SKYLAKE_HALO

BGA1440

VCC_SENSE

VSS_SENSE

7 OF 14

REV = 1 ?

V32

VCC

V33

VCC

V34

VCC

V35

VCC

V36

VCC

V37

VCC

V38

VCC

W13

VCC

W14

VCC

W29

VCC

W30

VCC

W31

VCC

W32

VCC

W35

VCC

W36

VCC

W37

VCC

W38

VCC

Y29

VCC

Y30

VCC

Y31

VCC

Y32

VCC

Y33

VCC

Y34

VCC

Y35

VCC

Y36

VCC

L14

VCC

P29

VCC

P30

VCC

P31

VCC

P32

VCC

P33

VCC

P34

VCC

P35

VCC

P36

VCC

R13

VCC

R31

VCC

R32

VCC

R33

VCC

R34

VCC

R35

VCC

R36

VCC

R37

VCC

R38

VCC

T29

VCC

T30

VCC

T31

VCC

T32

VCC

T35

VCC

T36

VCC

T37

VCC

T38

VCC

U29

VCC

U30

VCC

U31

VCC

U32

VCC

U33

VCC

U34

VCC

U35

VCC

U36

VCC

V13

VCC

V14

VCC

V31

VCC

P14

VCC

AG37 AG38

PH/PL on pwr side 10/07 Dan

Trace Length < 25 mils

VCCSENSE (52) VSSSENSE (52)

VCCGT / VCCGTX(2+3e o nly) 40A(need confi rm)

+VCCGT +VCCGT

BG34 BG35 BG36 BH33 BH34 BH35 BH36 BH37 BH38

BL36 BL37 BM36 BM37 BN36 BN37 BN38 BP37 BP38 BR37 BT37 BE38 BF13 BF14 BF29 BF30 BF31 BF32 BF35 BF36 BF37 BF38 BG29 BG30 BG31 BG32 BG33 BC36 BC37 BC38 BD13 BD14 BD29 BD30 BD31 BD32 BD33 BD34 BD35 BD36 BE31 BE32 BE37

SKYLAKE_HALO

UC1H

BGA1440

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

BJ37

VCCGT

BJ38

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

8 OF 14

SKL-H_BGA1440

REV = 1

Rev_0.53

AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36 AW14 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38 AY29 AY30 AY31 AY32 AY35 AY36 AY37 AY38 BA13 BA14 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BB13 BB14 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BC29 BC30 BC31 BC32 BC35 BE33 BE34 BE35 BE36

+VCCGT

UC1N

AJ29

VCCGT

AJ30

VCCGT

AJ31

VCCGT

AJ32

VCCGT

AJ33

VCCGT

AJ34

VCCGT

AJ35

VCCGT

AJ36

VCCGT

AK31

VCCGT

AK32

VCCGT

AK33

VCCGT

AK34

VCCGT

AK35

VCCGT

AK36

VCCGT

AK37

VCCGT

AK38

VCCGT

AL13

VCCGT

AL29

VCCGT

AL30

VCCGT

AL31

VCCGT

AL32

VCCGT

AL35

VCCGT

AL36

VCCGT

AL37

VCCGT

AL38

VCCGT

AM13

VCCGT

AM14

VCCGT

AM29

VCCGT

AM30

VCCGT

AM31

VCCGT

AM32

VCCGT

AM33

VCCGT

AM34

VCCGT

AM35

VCCGT

AM36

VCCGT

AN13

VCCGT

AN14

VCCGT

AN31

VCCGT

AN32

VCCGT

AN33

VCCGT

AN34

VCCGT

AN35

VCCGT

AN36

VCCGT

AN37

VCCGT

AN38

VCCGT

AP13

VCCGT

AP14

VCCGT

AP29

VCCGT

AP30

VCCGT

AP31

VCCGT

AP32

VCCGT

AP35

VCCGT

AP36

VCCGT

AP37

VCCGT

AP38

VCCGT

AR29

VCCGT

AR30

VCCGT

AR31

VCCGT

AR32

VCCGT

AR33

VCCGT

AR34

VCCGT

AR35

VCCGT

AR36

VCCGT

AT14

VCCGT

AT31

VCCGT

AT32

VCCGT

AT33

VCCGT

AT34

VCCGT

AT35

VCCGT

AT36

VCCGT

AT37

VCCGT

AT38

VCCGT

AU14

VCCGT

AU29

VCCGT

AU30

VCCGT

AU31

VCCGT

AU32

VCCGT

AU35

VCCGT

AU36

VCCGT

AU37

VCCGT

AU38

VCCGT

SKL-H_BGA1440

REV = 1

Change to 14/14 Loss 13 of 14

SKYLAKE_HALO

BGA1440

14 OF 14

VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX

VCCGT_SENSE

VSSGTX_SENSE

VSSGT_SENSE

VCCGTX_SENSE

AF29 AF30 AF31 AF32 AF33 AF34 AG13 AG14

EDS:Rail is unconnected for Proce ssors w ithout GT3/4.

AG31 AG32 AG33 AG34 AG35 AG36 AH13 AH14 AH29 AH30 AH31 AH32 AJ13 AJ14

VCCGT_SENSE

AH38 AH35 AH37 AH36

VSSGT_SENSE

VCCGT_SENSE (52)

VSSGT_SENSE (52)

Trace Length < 25 mils

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROP ERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROP ERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFORMATION. THIS SHE ET MAY NOT BE TRANSFEREDFROM THECUS TODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SE CRET INFORMATION. THIS SHE ET MAY NOT BE TRANSFEREDFROM THECUS TODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SE CRET INFORMATION. THIS SHE ET MAY NOT BE TRANSFEREDFROM THECUS TODY OF THE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT A S AUTHORIZED BY COMPAL ELECTRONICS, INC.NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT A S AUTHORIZED BY COMPAL ELECTRONICS, INC.NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT A S AUTHORIZED BY COMPAL ELECTRONICS, INC.NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYB E USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTENCONSE NT OF COMPAL ELECTRONICS, INC.

MAYB E USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTENCONSE NT OF COMPAL ELECTRONICS, INC.

2014/12/31 2016/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-H(5/9)Power,SVID

Size

Document Number Rev

Custom

A4WAD M/B LA-C871P

Date : Sheet o f

10 61Monday, July 13, 2015

1.0

smd.db-x7.ru

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

+1.35V_VDDQ_CPU

AA6 AE12 AF5 AF6 AG5 AG9 AJ12 AL11 AP6 AP7 AR12 AR6 AT12 AW6 AY6 J5 J6 K12 K6 L12 L6 R6 T6 W6

Y12 BH13

G11

H30 H29 G30 H28

J28

VCCSA_SENSE

M38

VSSSA_SENSE

M37

VCCIO_SENSE

H14

VSSIO_SENSE

J14

For Power consumption Measurement

JPC1

JUMP_43X118

+VDDQ_CLK

+VCCSFR_OC_1 +VCCSFR_OC_2

+1.0V_VCCST +1.0VS_VCCSTG

+1.0V_VCCSFR

JPC2

VCCSA_SENSE (52) VSSSA_SENSE (52)

VCCIO_SENSE (51) VSSIO_SENSE (51)

+1.35V_VDDQ

+1.0V_VCCST

1 2

RC40 0_0402_5%@

1 1

+1.0VS_VCCSTG

2 2

+1.35V_VDDQ_CPU

(1.0VS)

1U_0402_6.3V6K

CC21

RC41 0_0603_5%

1U_0402_6.3V6K

CC22

1 2

Place at Back Side

+1.35V_VDDQ

1 2

RC42 0_0402_5%

1 2

RC58 0_0402_5%

NOTE: VCCPLL_OC is allowed to be turned off during S3 & DS3 if it is not powered

3 3

directly from VDDQ

(1.35V)

+1.0V_VCCSFR

CC20 1U_0402_6.3V6K

+1.0V_VCCST

CC23 1U_0402_6.3V6K

Place at Back Side

+VDDQ_CLK

BSC Side

10U_0603_6.3V6M

CC24

+VCCSFR_OC_1

1U_0402_6.3V6K

CC25

1 2

+VCCSFR_OC_2

SKYLAKE_HALO

K29 K30 K31 K32 K33 K34 K35

M29 M30 M31 M32 M33 M34 M35 M36

AG12

G15 G17 G19 G21

J30

L31 L32 L35 L36 L37 L38

H15 H16 H17 H19 H20 H21 H26 H27 J15 J16 J17 J19 J20 J21 J26 J27

UC1I

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

SKL-H_BGA1440

REV = 1

BGA1440

9 OF 14

VDDQC

VCCPLL_OC VCCPLL_OC

VCCST VCCSTG VCCSTG

VCCPLL VCCPLL

VCCSA_SENSE VSSSA_SENSE

VCCIO_SENSE

VSSIO_SENSE

RVP11 47u*1,10u*7,1u*3 CAP place on PWR side.

RVP11 PWR NEED PROVIDE

0.95V FOR VCCIO

1U_0402_6.3V6K

CC26

+VCCSA

+VCCIO

Place at Back Side

+1.35V_VDDQ_CPU

10U_0603_6.3V6M

CC27

10U_0603_6.3V6M

CC28

CC29

10U_0603_6.3V6M

CC30

CC31

10U_0603_6.3V6M

CC33

CC32

10U_0603_6.3V6M

CC34

10U_0603_6.3V6M

CC35

CC36

22U_0603_6.3V6M

CC37

22U_0603_6.3V6M

CC38

22U_0603_6.3V6M

CC39

CC40

+VCCIO

10U_0603_6.3V6M

CC41

10U_0603_6.3V6M

CC42

22U_0603_6.3V6M

CC69

CC43

22U_0603_6.3V6M

CC70

22U_0603_6.3V6M

CC71

CC72

Place at Back SidePlace at Back Side Follow ORB 3/20

4 4

+1.35V_VDDQ_CPU : 10UF/6.3V/0603 *10 update CRB cap QTY

22UF/6.3V/0603 * 4

CPU_CORE/VCCGT/VCCSA decoupling capacitor place to PWR side

Security Classification

2014/12/31 2016/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/12/31 2016/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date: Sheet of

Compal Electronics, Inc.

SKL-H(6/9)POWER

A4WAD M/B LA-C871P

11 61Monday, July 13, 2015

1.0

smd.db-x7.ru

C17 C13

BT9 BT5

BR7

BP7

BN9 BN7 BN4 BN2

BM9 BM6 BM2

BH9 BH8 BH5 BH4 BH1

BE6 BD9

UC1L

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-H_BGA1440

REV = 1

SKYLAKE_HALO

BGA1440

12 OF 14

NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS

SKYLAKE_HALO

UC1J

REV = 1

BGA1440

10 OF 14

C25 C23 C21 C19 C15 C11 C8 C5 BM29 BM25 BM18 BM11 BM8 BM7 BM5 BM3 BL38 BL35 BL13 BL6 BK25 BK22 BK13 BK6 BJ30 BJ29 BJ15 BJ12 BH11 BH10 BH7 BH6 BH3 BH2 BG37 BG14 BG6 BF34 BF6 BE30 BE5 BE4 BE3 BE2 BE1 BD38 BD37 BD12 BD11 BD10 BD8 BD7 BD6 BC33 BC14 BC13 BC6 BB30 BB29 BB6 BB5

C2 BT36 BT35 BT4 BT3 BR38

T3824PAD @ T3825PAD @ T3826PAD @

EDRAM

CRB EDRAM

OPC_RCOMP OPCE_RCOMP OPCE_RCOMP2

BJ17 BJ19

BJ20 BK17 BK19 BK20

BL16

BL17

BL18

BL19

BL20

BL21 BM17 BN17

BJ23

BJ26

BJ27 BK23 BK26 BK27

BL23

BL24

BL25

BL26

BL27

BL28 BM24

BL15 BM16

BL22 BM22

BP15 BR15

BT15 BP16

BR16

BT16

BN15 BM15

BP17 BN16

BM14

BL14

BJ35

BJ36

AT13

AW13

AU13 AY13

BT29 BR25 BP25

VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VCCOPC_SENSE VSSOPC_SENSE

RSVD RSVD

VCCEOPIO VCCEOPIO VCCEOPIO

RSVD RSVD RSVD

VCCEOPIO_SENSE VSSEOPIO_SENSE

RSVD RSVD

VCC_OPC_1P8 VCC_OPC_1P8

RSVD RSVD

ZVM# MSM#

ZVM2# MSM2#

OPC_RCOMP OPCE_RCOMP OPCE_RCOMP2

SKL-H_BGA1440

SKYLAKE_HALO

UC1F

Y9 Y8 Y7

T9 T8 T7 T5 T4 T3 T2 T1

N9 N8 N7 N6 N5 N4 N3 N2 N1

K9 K8 K7 K5 K4 K3 K2

SKL-H_BGA1440

BGA1440

6 OF 14

NCTFVSS

K1 J36 J33 J32 J25 J22 J18 J10 J7 J4 H35 H32 H25 H22 H18 H12 H11 G28 G26 G24 G23 G22 G20 G18 G16 G14 G12 G10 G9 G8 G6 G5 G4 F36 F31 F29 F27 F25 F23 F21 F19 F17 F15 F13 F11 F9 F8 F5 F4 F3 F2 E38 E35 E34 E9 E4 D33 D30 D28 D26 D24 D22 D20 D18 D16 D14 D12 D10 D9 D6 D3 C37 C31 C29 C27

D38

?REV = 1

BA38 BA37 BA12 BA11 BA10

AY34 AY33 AY14

AY12 AW30 AW29 AW12

AW5 AW4 AW3 AW2

AW1 AV38 AV37 AU34 AU33 AU12 AU11 AU10

AT30 AT29

AR38 AR37 AR14 AR13

AP34 AP33 AP12 AP11 AP10

AN30 AN29 AN12

AM38 AM37 AM12

AL34

AL33

AL14

AL12

AL10

Y38 Y37 Y14

1 1

2 2

3 3

Y13 Y11 Y10

W34 W33 W12

V30 V29 V12

U38 U37

T34 T33 T14 T13 T12 T11 T10

R30 R29 R12

P38

P37

P12 N34

N33 N12

N11 N10

M14 M13 M12

L34

L33

L30

L29

K38

K11

K10

W5 W4 W3 W2 W1

BB4 BB3 BB2 BB1

BA9 BA8 BA7 BA6

AU9 AU8 AU7 AU6

AT6

AR5 AR4 AR3 AR2 AR1

AP9 AP8

AN6 AN5

AM5 AM4 AM3 AM2 AM1

AL9 AL8 AL7 AL4

SKYLAKE_HALO

UC1M

SKL-H_BGA1440

REV = 1

BGA1440

13 OF 14

NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS

AK30 AK29 AK4 AJ38 AJ37 AJ6 AJ5 AJ4 AJ3 AJ2 AJ1 AH34 AH33 AH12 AH6 AG30 AG29 AG11 AG10 AG8 AG7 AG6 AF14 AF13 AF12 AF4 AF3 AF2 AF1 AE34 AE33 AE6 AD30 AD29 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AC38 AC37 AC12 AC6 AC5 AC4 AC3 AC2 AC1 AB34 AB33 AB6 AA30 AA29 AA12 A30 A28 A26 A24 A22 A20 A18 A16 A14 A12 A10 A9 A6

B37 B3 A34 A4 A3

BT32 BT26 BT24 BT21 BT18 BT14 BT12

BR36 BR34 BR29 BR26 BR24 BR21 BR18 BR14 BR12

BP34 BP33 BP29 BP26 BP24 BP21 BP18 BP14 BP12

BN34 BN31 BN30 BN29 BN24 BN21 BN20 BN19 BN18 BN14 BN12

BM38 BM35 BM28 BM27 BM26 BM23 BM21 BM13 BM12

BL29 BK29 BK15 BK14

BJ32

BJ31

BJ25

BJ22 BH14 BH12

BG38 BG13 BG12

BF33

BF12 BE29

BC34 BC12 BB12

4 4

Security Classification

2014/12/31 2016/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/12/31 2016/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date: Sheet of

SKL-H(8/9)GND

A4WAD M/B LA-C871P

1.0

12 61Monday, July 13, 2015

smd.db-x7.ru

1 1

UC1K

RSVD_TP

BR1

RSVD_TP

BT2

RSVD_TP

BN35

RSVD

J24

RSVD

H24

RSVD

BN33

RSVD

BL34

RSVD

N29

RSVD

R14

RSVD

AE29

RSVD

2 2

PROC_TRIGIN_R(22)

PROC_TRIGOUT_R(22)

3 3

1 2

RC45 30_0402_1%

PROC_TRIGIN_R PROC_TRIGOUT

AA14

H23

C30

BR35 BR31 BH30

A36 A37

F30 E30

B30

J23

RSVD RSVD

RSVD PROC_TRIGIN

PROC_TRIGOUT RSVD

RSVD RSVD

RSVD

RSVD RSVD RSVD

SKL-H_BGA1440

SKYLAKE_HALO

BGA1440

11 OF 14

Rev_0 .53

RSVD_TP RSVD_TP

RSVD RSVD

VSS

RSVD_TP RSVD_TP

RSVD RSVD

VSS

RSVD_TP RSVD_TP

RSVD RSVD RSVD

NCTF NCTF NCTF NCTF NCTF NCTF

+1.0VALW

1U_0402_6.3V6K

CC45

EN_1.0V_VCCSTU

1U_0402_6.3V6K

CC44

1U_0402_6.3V6K

CC54

1U_0402_6.3V6K

CC56

+1.0VALW TO +1.0V_VCCST

UC6

VIN

VBIAS

APE8937GN2_DFN8_2X2

VOUT VOUT

GND GND

8 7

CC48

1000P_0402_50V7K

+1.0V_VCCST_L

1 2

+1.0VALW TO +1.0VS_VCCSTG

UC7

VIN1

VIN2

VIN thermal

VBIAS

TPS22961DNYR_WSON8

VCCSTG and VCCIO SLEW RATE <=65us

VOUT

GND

+1.0VS_VCCSTG_IO

1 2

RC44 0_0402_5%

1 2

JUMP_43X118

UNPOP Defult use POWER side

JC1

112

JUMP_43X79

JC2

+1.0V_VCCST

CC47 .1U_0402_16V7K

+1.0VS_VCCSTG

CC55 .1U_0402_16V7K

+VCCIO

1 2

BM33 BL33

BJ14 BJ13

BK28 BJ28

BJ18 BJ16

BK16

BK24 BJ24

BK21 BJ21

BT17 BR17

BK18 BJ34

BJ33

G13 AJ8 BL31

NCTF_0

NCTF_1

B38

NCTF_2

BP1

NCTF_3

BR2

NCTF_4

NCTF_5

C38

?REV = 1

SYSON(39,43,48)

+1.0V_VCCST: 60mA R ON = 22mΩ VDROP= 1.32mV Delay time: 270us

CC46 1U_0402_6.3V6K

RC43 0_0402_5%

T13 PAD@ T14 PAD@ T15 PAD@ T16 PAD@ T17 PAD@

.1U_0402_16V7K

T18 PAD@

SUSP#(39,43,46,48,50,51)

1 2

+5VALW

CC53

SUSP#

1 2

RC46 0_0402_5%

+5VALW

+1.0VS_VCCSTG: 60mA R ON = 4.4mΩ VDROP= 11mV Delay time: 9.3us

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/12/31 2016/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date: Sheet of

SKL-H(9/9)RSVD

A4WAD M/B LA-C871P

1.0

13 61Monday, July 13, 2015

smd.db-x7.ru

DDR_A_DQS#[0..7](7)

DDR_A_D[0..63](7)

DDR_A_DQS[0..7](7)

DDR_A_MA[0..15](7)

DDR_A_BS0(7)

DDR_A_BS1(7)

DDR_A_BS2(7)

1 1

Layout Note: Place near JDIMM1

2 2

+1.35V_VDDQ

10U_0603_6.3V6M

3 3

Layout Note: Place near JDIMM1.203,204

DDR_A_WE#(7) DDR_A_CAS#(7) DDR_A_RAS#(7)

DDR_A_CLK0(7) DDR_A_CLK#0(7) DDR_A_CLK1(7)

DDR_A_CLK#1(7)

DDR_A_CKE0(7)

DDR_A_CKE1(7)

DDR_A_CS#0(7)

DDR_A_CS#1(7)

PCH_SMBDATA_R(15,18,42) PCH_SMBCLK_R(15,18,42)

DDR_A_ODT0(7)

DDR_A_ODT1(7)

1U_0402_6.3V6K

CD5

10U_0603_6.3V6M

CD11

CD6

10U_0603_6.3V6M

CD12

+0.675VS_VTT

10U_0603_6.3V6M

CD13

1U_0402_6.3V6K

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_WE# DDR_A_CAS# DDR_A_RAS#

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1

DDR_A_CKE0 DDR_A_CKE1 DDR_A_CS#0 DDR_A_CS#1

PCH_SMBDATA_R PCH_SMBCLK_R

DDR_A_ODT0 DDR_A_ODT1

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

1U_0402_6.3V6K

CD7

CD8

10U_0603_6.3V6M

CD15

CD14

1U_0402_6.3V6K

CD22

CD23

CD9

10U_0603_6.3V6M

CD16

Layout Note: Place near JDIMM1.199

+0.675V_A_VREFDQ

RD2 2_0402_1%

CD3

0.022U_0402_16V7K

RD4

24.9_0402_1%

Place near to SO-DIMM connector.

1U_0402_6.3V6K

CD10

Follow Robin_SL

10U_0603_6.3V6M

CD18

CD19 330U_D2_2V_Y

SGA00009S00 330U 2V H1.9 9mohm POLY

+3VS

CD24 .1U_0402_16V7K

CD17

4 4

+1.35V_VDDQ

RD1

1K_0402_1%

RD3

1K_0402_1%

+0.675V_DDRA_VREFDQ

10mils

2.2U_0402_6.3V6M

CD1

CD2 .1U_0402_16V7K

+3VS+0.675VS_VTT

DDR_A_D6 DDR_A_D2

DDR_A_D13 DDR_A_D12

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D20 DDR_A_D21

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D29 DDR_A_D28

DDR_A_D30 DDR_A_D31

DDR_A_CKE0

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3

DDR_A_MA1 DDR_A_CLK0

DDR_A_CLK#0 DDR_A_MA10

DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# DDR_A_MA13

DDR_A_CS#1

DDR_A_D33 DDR_A_D37

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D35 DDR_A_D34

DDR_A_D40 DDR_A_D45

DDR_A_D46 DDR_A_D47

DDR_A_D48 DDR_A_D50

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D54 DDR_A_D51

DDR_A_D61 DDR_A_D56

DDR_A_D59 DDR_A_D63

DDR_A_D0 DDR_A_D5

Address : 00

JDIMM1

VREF_DQ1VSS1

VSS2

DQ0

DQ1

VSS4

DM0

VSS5

DQ2

DQ3

VSS7

DQ8

DQ9

VSS9

DQS#1 DQS129RESET#

VSS11

DQ10

DQ11

VSS13

DQ16

DQ17

VSS15

DQS#2

DQS2

VSS18

DQ18

DQ19

VSS20

DQ24

DQ25

VSS22

DM3

VSS23

DQ26

DQ27

VSS25

CKE0

VDD1

NC1

BA2

VDD3

A12/BC#

VDD5

VDD7

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

LCN_DAN06-K4406-0101

CONN@

SP07000PT00

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRETINFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODYOF THE COMPETENT DIVISION OF R&D

AND TRADE SECRETINFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODYOF THE COMPETENT DIVISION OF R&D

AND TRADE SECRETINFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODYOF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BYCOMPAL ELECTRONICS, INC. NEITHER THIS SHEETNOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BYCOMPAL ELECTRONICS, INC. NEITHER THIS SHEETNOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BYCOMPAL ELECTRONICS, INC. NEITHER THIS SHEETNOR THE INFORMATION IT CONTAINS MAYBE USEDBY ORDISCLOSED TOANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OFCOMPAL ELECTRONICS, INC.

MAYBE USEDBY ORDISCLOSED TOANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OFCOMPAL ELECTRONICS, INC.

DQ4 DQ5

VSS3

DQS#0

DQS0 VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

VSS12

DQ14 DQ15

VSS14

DQ20 DQ21

VSS16

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21 DQS#3

DQS3

VSS24

DQ30 DQ31

VSS26

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL

VTT2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

A14

82 84

A11

88 90

94 96

100 102 104 106 108 110 112 114

S0#

116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_D1 DDR_A_D4

+1.35V_VDDQ+1.35V_VDDQ

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D7 DDR_A_D3

DDR_A_D9 DDR_A_D8

DDR_DRAMRST# DDR_A_D15

DDR_A_D14 DDR_A_D16

DDR_A_D17

DDR_A_D22 DDR_A_D23

DDR_A_D24 DDR_A_D25

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D26 DDR_A_D27

DDR_A_CKE1 DDR_A_MA15

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2

DDR_A_MA0 DDR_A_CLK1

DDR_A_CLK#1 DDR_A_BS1

DDR_A_RAS# DDR_A_CS#0

DDR_A_ODT0 DDR_A_ODT1

+1.35V_VDDQ

RD5 470_0402_5%

CD4 .1U_0402_16V7K

CAD NOTE PLACE THE CAP NEAR TO DIMM RESET PIN

DIMM1 RVS H:4mm

<Address: 00>

10mils

DDR_A_D32 DDR_A_D36

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D41

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D42 DDR_A_D43

DDR_A_D52 DDR_A_D49

DDR_A_D55 DDR_A_D53

DDR_A_D60 DDR_A_D57

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D58

PCH_SMBDATA_R PCH_SMBCLK_R +0.675VS_VTT

Compal Secret Data

2014/12/31 2016/12/31

Compal Secret Data

2.2U_0402_6.3V6M

+0.675VS_VTT

Deciphered Date

CD20

From CPU to CHB

DDR_DRAMRST# (15,18)

1 2

RD6

CD21 .1U_0402_16V7K

Reverse Type

2-3A to 1 DIMMs/channel

+0.675V_DDR_VREFCA+0.675V_DDRA_VREFCA

0_0402_5%

Interleaved Memory

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date: Sheet o f

Compal Electronics, Inc.

DDR3L_DIMMA

A4WAD M/B LA-C871P

14 61Monday, July 13, 2015

1.0

smd.db-x7.ru

+1.35V_VDDQ

DDR_B_DQS#[0..7](7) DDR_B_D[0..63](7) DDR_B_DQS[0..7](7)

DDR_B_MA[0..15](7)

1 1

Layout Note: Place near JDIMM2

2 2

3 3

+1.35V_VDDQ

Layout Note: Place near JDIMM2.203,204

DDR_B_BS0(7)

DDR_B_BS1(7)

DDR_B_BS2(7) DDR_B_WE#(7) DDR_B_CAS#(7) DDR_B_RAS#(7)

DDR_B_CLK0(7) DDR_B_CLK#0(7) DDR_B_CLK1(7) DDR_B_CLK#1(7)

DDR_B_CKE0(7) DDR_B_CKE1(7) DDR_B_CS#0(7) DDR_B_CS#1(7)

PCH_SMBDATA_R(14,18,42) PCH_SMBCLK_R(14,18,42)

DDR_B_ODT0(7) DDR_B_ODT1(7)

1U_0402_6.3V6K

CD30

CD29

10U_0603_6.3V6M

CD35

+0.675VS_VTT

CD36

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_WE# DDR_B_CAS# DDR_B_RAS#

DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1

DDR_B_CKE0 DDR_B_CKE1

DDR_B_CS#0

DDR_B_CS#1

PCH_SMBDATA_R PCH_SMBCLK_R

DDR_B_ODT0 DDR_B_ODT1

1U_0402_6.3V6K

CD31

10U_0603_6.3V6M

CD37

1U_0402_6.3V6K

CD47

1U_0402_6.3V6K

CD32

CD33

10U_0603_6.3V6M

CD38

CD39

Layout Note: Place near JDIMM2.199

1U_0402_6.3V6K

CD48

+0.675V_B_VREFDQ

RD9 2_0402_1%

RD8

24.9_0402_1%

CD26

0.022U_0402_16V7K

Place near to SO-DIMM connector.

1U_0402_6.3V6K

CD34

CD41

+3VS

Follow Robin_SL

10U_0603_6.3V6M

CD42

CD43

330U_D2_2V_Y

SGA00009S00 330U 2V H1.9 9mohm POLY

CD49

2.2U_0402_6.3V6M

10U_0603_6.3V6M

CD40

4 4

RD7

1K_0402_1%

RD10

1K_0402_1%

+0.675V_DDRB_VREFDQ

CD27

2.2U_0402_6.3V6M

+3VS

RD16 10K_0402_5%

+0.675VS_VTT

VSS3

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

DQ23

VSS19

DQ29

VSS21

DQS3 DQ30

DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

VTT2

DDR_B_D5

DQ4 DQ5

DQ6 DQ7

A15 A14

A7 A6

A4 A2

CK1

BA1

S0#

SCL

DDR_B_D4

6 8

DDR_B_DQS#0

DDR_B_DQS0

12 14

DDR_B_D7

DDR_B_D2

18 20

DDR_B_D9

DDR_B_D8

24 26 28

DDR_DRAMRST#

30 32

DDR_B_D12

DDR_B_D13

36 38

DDR_B_D17

DDR_B_D16

42 44 46 48

DDR_B_D19

DDR_B_D23

52 54

DDR_B_D28

DDR_B_D25

58 60

DDR_B_DQS#3

DDR_B_DQS3

64 66

DDR_B_D26

DDR_B_D31

70 72

+1.35V_VDDQ+1.35V_VDDQ

DDR_B_CKE1

74 76

DDR_B_MA15

DDR_B_MA14

80 82

DDR_B_MA11

DDR_B_MA7

86 88

DDR_B_MA6

DDR_B_MA4

92 94

DDR_B_MA2

DDR_B_MA0

98 100

DDR_B_CLK1

102

DDR_B_CLK#1

104 106

DDR_B_BS1

108

DDR_B_RAS#

110 112

DDR_B_CS#0

114

DDR_B_ODT0

116 118

DDR_B_ODT1

120 122 124 126 128

DDR_B_D34

130

DDR_B_D35

132 134 136 138

DDR_B_D33

140

DDR_B_D32

142 144

DDR_B_D41

146

DDR_B_D40

148 150

DDR_B_DQS#5

152

DDR_B_DQS5

154 156

DDR_B_D43

158

DDR_B_D42

160 162

DDR_B_D51

164

DDR_B_D54

166 168 170 172

DDR_B_D53

174

DDR_B_D49

176 178

DDR_B_D59

180

DDR_B_D58

182 184

DDR_B_DQS#7

186

DDR_B_DQS7

188 190

DDR_B_D62

192

DDR_B_D56

194 196 198

PCH_SMBDATA_R

200

PCH_SMBCLK_R

202

+0.675VS_VTT

204 206

VREF_DQ1VSS1

DDR_B_D0 DDR_B_D1

CD25 .1U_0402_16V7K

DDR_B_D3

DDR_B_D6 DDR_B_D10

DDR_B_D14 DDR_B_DQS#1

DDR_B_DQS1 DDR_B_D15

DDR_B_D11 DDR_B_D18

DDR_B_D22 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D20

DDR_B_D21 DDR_B_D27

DDR_B_D30

DDR_B_D24 DDR_B_D29

DDR_B_CKE0

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3

DDR_B_MA1 DDR_B_CLK0

DDR_B_CLK#0 DDR_B_MA10

DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDR_B_MA13

DDR_B_CS#1

DDR_B_D39 DDR_B_D38

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D36 DDR_B_D37

DDR_B_D44 DDR_B_D45

DDR_B_D46 DDR_B_D47

DDR_B_D48 DDR_B_D52

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D55

DDR_B_D57 DDR_B_D61

DDR_B_D60 DDR_B_D63

+3VS +0.675VS_VTT

DDR_B_SA1

Address : 01

VSS2

DQ0

DQ1 VSS49DQS#0

DM0

VSS5

DQ2

DQ3

VSS7

DQ8

DQ9

VSS9

DQS#1 DQS129RESET# VSS1131VSS12

DQ10

DQ11 VSS1337VSS14

DQ16

DQ17 VSS1543VSS16

DQS#2 DQS247VSS17 VSS1849DQ22

DQ18

DQ19 VSS2055DQ28

DQ24

DQ25 VSS2261DQS#3

DM3 VSS2365VSS24

DQ26

DQ27 VSS2571VSS26

CKE0

VDD1

NC1

BA2

VDD3 A12/BC#83A11

VDD5

VDD7

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

LCN_DAN06-K4806-0101

CONN@

SP07000PU00

DDR_DRAMRST# (14,18)

CD28 .1U_0402_16V7K

CAD NOTE PLACE THE CAP NEAR TO DIMM RESET PIN

DIMM2 RVS H:8mm

+0.675V_DDRB_VREFCA

10mils

CD45

2.2U_0402_6.3V6M

Place near to SO-DIMM connector.

+0.675V_DDR_VREFCA

RD12 0_0402_5%

1 2

CD46 .1U_0402_16V7K

From PCH

Interleaved Memory

Reverse Type

2-3A to 1 DIMMs/channel

+1.35V_VDDQ

RD11

1K_0402_1%

RD13 2_0402_1%

RD14

1K_0402_1%

+0.675V_VREFCA

1 2

CD44

0.022U_0402_16V7K

RD15

24.9_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/12/31 2016/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

DDR3L_DIMMB

Size Document Number Re v

Custom

A4WAD M/B LA-C871P

Date: Sheet of

15 61Monday, July 13, 2015

1.0

smd.db-x7.ru

UH1

SKL-PCH_QJHT

1 1

PCH_QJHT@

SA000096J10

2 2

3 3

UH1

SKL-PCH_QHPU

PCH_QHPU@

SA00008RM30

#546884 P.231 PCIE_RCOMPN/PCIE_RCOMPP BO=4 W=12~15 S=12 R=100ohm

PCIE_PRX_DTX_N3(36)

NGFF WL+BT(KEY E)

GLAN+CR

PCIE_PRX_DTX_P3(36) PCIE_PTX_C_DRX_N3(36) PCIE_PTX_C_DRX_P3(36)

PCIE_PRX_DTX_N4(34)

PCIE_PRX_DTX_P4(34)

PCIE_PTX_C_DRX_N4(34) PCIE_PTX_C_DRX_P4(34)

USB3_PTX_DRX_N1(38) USB3_PTX_DRX_P1(38)

USB3 MB

USB3_PRX_DTX_N1(38) USB3_PRX_DTX_P1(38) USB3_PTX_DRX_N2(38) USB3_PTX_DRX_P2(38) USB3_PRX_DTX_N2(38) USB3_PRX_DTX_P2(38)

CHECK ACER DVR for port use

DMI_CTX_PRX_N0(8) DMI_CTX_PRX_P0(8)

DMI_CRX_PTX_N0(8)

DMI_CRX_PTX_P0(8) DMI_CTX_PRX_N1(8) DMI_CTX_PRX_P1(8)

DMI_CRX_PTX_N1(8)

DMI_CRX_PTX_P1(8) DMI_CTX_PRX_N2(8) DMI_CTX_PRX_P2(8)

DMI_CRX_PTX_N2(8)

DMI_CRX_PTX_P2(8) DMI_CTX_PRX_N3(8) DMI_CTX_PRX_P3(8)

DMI_CRX_PTX_N3(8)

DMI_CRX_PTX_P3(8)

RH5 100_0402_1%

1 2

CH3 .1U_0402_16V7K CH4 .1U_0402_16V7K

CH1 .1U_0402_16V7K

12 12

CH2 .1U_0402_16V7K

CHECK ACER DVR for port use 12/08 Change Port, follow DVR1044_R1.03

DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 DMI_CRX_PTX_N0 DMI_CRX_PTX_P0 DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 DMI_CRX_PTX_N1 DMI_CRX_PTX_P1 DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 DMI_CRX_PTX_N2 DMI_CRX_PTX_P2 DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI_CRX_PTX_P3

PCIE_RCOMPN PCIE_RCOMPP

PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3 PCIE_PRX_DTX_N4

PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4

UH1F

C11

USB3_1_TXN

B11

USB3_1_TXP

USB3_1_RXN

USB3_1_RXP

B12

USB3_2_TXN/SSIC_1_TXN

A12

USB3_2_TXP/SSIC_1_TXP

USB3_2_RXN/SSIC_1_RXN

USB3_2_RXP/SSIC_1_RXP

B15

USB3_6_TXN

C15

USB3_6_TXP

K15

USB3_6_RXN

K13

USB3_6_RXP

B14

USB3_5_TXN

C14

USB3_5_TXP

G13

USB3_5_RXN

H13

USB3_5_RXP

D13

USB3_3_TXP/SSIC_2_TXP

C13

USB3_3_TXN/SSIC_2_TXN

USB3_3_RXP/SSIC_2_RXP

B10

USB3_3_RXN/SSIC_2_RXN

B13

USB3_4_TXP

A14

USB3_4_TXN

G11

USB3_4_RXP

E11

USB3_4_RXN

SKL-H-PCH_BGA837

UH1B

L27

DMI_RXN0

N27

DMI_RXP0

C27

DMI_TXN0

B27

DMI_TXP0

E24

DMI_RXN1

G24

DMI_RXP1

B28

DMI_TXN1

A28

DMI_TXP1

G27

DMI_RXN2

E26

DMI_RXP2

B29

DMI_TXN2

C29

DMI_TXP2

L29

DMI_RXN3

K29

DMI_RXP3

B30

DMI_TXN3

A30

DMI_TXP3

B18

PCIE_RCOMPN

C17

PCIE_RCOMPP

H15

PCIE1_RXN/USB3_7_RXN

G15

PCIE1_RXP/USB3_7_RXP

A16

PCIE1_TXN/USB3_7_TXN

B16

PCIE1_TXP/USB3_7_TXP

B19

PCIE2_TXN/USB3_8_TXN

C19

PCIE2_TXP/USB3_8_TXP

E17

PCIE2_RXN/USB3_8_RXN

G17

PCIE2_RXP/USB3_8_RXP

L17

PCIE3_RXN/USB3_9_RXN

K17

PCIE3_RXP/USB3_9_RXP

B20

PCIE3_TXN/USB3_9_TXN

C20

PCIE3_TXP/USB3_9_TXP

E20

PCIE4_RXN/USB3_10_RXN

G19

PCIE4_RXP/USB3_10_RXP

B21

PCIE4_TXN/USB3_10_TXN

A21

PCIE4_TXP/USB3_10_TXP

K19

PCIE5_RXN

L19

PCIE5_RXP

D22

PCIE5_TXN

C22

PCIE5_TXP

G22

PCIE6_RXN

E22

PCIE6_RXP

B22

PCIE6_TXN

A23

PCIE6_TXP

L22

PCIE7_RXN

K22

PCIE7_RXP

C23

PCIE7_TXN

B23

PCIE7_TXP

K24

PCIE8_RXN

L24

PCIE8_RXP

C24

PCIE8_TXN

B24

PCIE8_TXP

SKL-H-PCH_BGA837

REV = 1.3

USB

SPT-H_PCH

LPC/eSPI

GPP_A14/SUS_STAT#/ESPI_RESET#

SATA

6 OF 12

SPT-H_PCH

DMI

PCIe/USB 3

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_G19/SMI#

GPP_G18/NMI#

GPP_E6/DEVSLP2 GPP_E5/DEVSLP1 GPP_E4/DEVSLP0 GPP_F9/DEVSLP7 GPP_F8/DEVSLP6 GPP_F7/DEVSLP5 GPP_F6/DEVSLP4 GPP_F5/DEVSLP3

USB2N_1 USB2P_1 USB2N_2 USB2P_2 USB2N_3 USB2P_3 USB2N_4 USB2P_4 USB2N_5 USB2P_5 USB2N_6 USB2P_6

USB 2.0

2 OF 12

USB2N_7 USB2P_7 USB2N_8 USB2P_8 USB2N_9 USB2P_9

USB2N_10

USB2P_10

USB2N_11

USB2P_11

USB2N_12

USB2P_12

USB2N_13

USB2P_13

USB2N_14

USB2P_14

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_F15/USB2_OCB_4 GPP_F16/USB2_OCB_5 GPP_F17/USB2_OCB_6 GPP_F18/USB2_OCB_7

USB2_COMP

USB2_VBUSSENSE

RSVD_AB13

USB2_ID

GPD7/RSVD

LPC_AD0

AT22

LPC_AD1

AV22

LPC_AD2

AT19

LPC_AD3

BD16

LPC_FRAME#

BE16

TPM_SERIRQ

BA17

LPC_PIRQA#

AW17

EC_KBRST#_R

AT17 BC18

LPC_CLK

BC17

CK_LPC_TPM_R

AV19 M45

N43

AE45 AG43 AG42 AB39 AB36 AB43 AB42 AB41

USB20_N1

AF5

USB20_P1

AG7

USB20_N2

AD5

USB20_P2

AD7

USB20_N3

AG8

USB20_P3

AG10 AE1 AE2 AC2 AC3 AF2 AF3

USB20_N7

AB3

USB20_P7

AB2

USB20_N8

AL8

USB20_P8

AL7

USB20_N9

AA1

USB20_P9

AA2 AJ8 AJ7 W2 W3 AD3

CHECK ACER DVR for port use

AD2

12/08 Change Port, follow DVR1044_R1.03

V2 V1 AJ11 AJ13

USB_OC0#

AD43

USB_OC1#

AD42 AD39

USB_OC3#

AC44

USB_OC4

Y43

USB_OC5

Y41

USB_OC6

W44

USB_OC7

W43

USB2_COMP

AG3

USB2_VBUSSENSE

AD10 AB13

USB2_ID

AG2

BD14

546765_2015WW10_Skylake_MOW_Rev_1_0 05/19 RH150

LPC_AD0 (39,40) LPC_AD1 (39,40) LPC_AD2 (39,40) LPC_AD3 (39,40)

LPC_FRAME# (39,40) TPM_SERIRQ (39,40)

EC_KBRST#_R (39)

ESPI_RST# (39)

RH2 22_0402_5% RH4 22_0402_5%TPM@

12 12

USB20_N1 (38) USB20_P1 (38) USB20_N2 (38) USB20_P2 (38) USB20_N3 (38) USB20_P3 (38)

USB20_N7 (36) USB20_P7 (36) USB20_N8 (30) USB20_P8 (30) USB20_N9 (30) USB20_P9 (30)

USB_OC0# (38) USB_OC1# (38)

1 2

RH6 113_0402_1%

1 2

RH149 0_0402_5%

1 2

RH150 0_0402_5%

LPC Bus

LPC : +3.3V

To TPM

LPC_CLK_R (39) CK_LPC_TPM (40)

USB3 MB USB3 MB

USB2/B

TS Camera

To EC

TPM_SERIRQ

DG requierment 8.2k PH +3VS CRB 10K PH +3vs

EC_KBRST#_R

check EC design needed pop RC118 or not

LPC_PIRQA#

1 2

RH1 10K_0402_5%

1 2

RH3 10K_0402_5%

RH122 10K_0402_5%

reference PDG1.0 50-30

USB_OC0# USB_OC1# USB_OC3# USB_OC2#USB_OC2#

USB_OC5 USB_OC4 USB_OC6 USB_OC7

RPH1

18 27 36 45

10K_0804_8P4R_5%

RPH2

18 27 36 45

10K_0804_8P4R_5%

+3VS

+3VALW_PCH_PRIM

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/12/31 2016/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCH(1/7)DMI,PCIE,USB

Size Document Number Re v

Custom

A4WAD M/B LA-C871P

Date: Sheet of

16 61Monday, July 13, 2015

1.0

smd.db-x7.ru

+3VS

1 2

RH11 100K_0402_5%

1 2

1 1

2 2

RH10 100K_0402_5%

EC_PME#(34,39)

PCH PLTRST Buf f er

PLT_RST#

MC74VHC1G08DFT2G_SC70-5

3 3

TP_INT#

I2C_TS_INT#

UH1A

1 2

UH5

PCH_SPI_SI PCH_SPI_SO PCH_SPI_CS#0 PCH_SPI_CLK PCH_SPI_CS#1 PCH_SPI_IO2 PCH_SPI_IO3

CH5

.1U_0402_16V7K

1 2

PLT_RST_BUF#

PCH_SPI_CS#0

EC_PME#_R

BD17 AG15

AG14 AF17 AE17

AR19 AN17

BB29 BE30 BD31 BC31

AW31

BC29 BD30 AT31

AN36

AL39 AN41 AN38 AH43 AG44

RH24 100K_0402_5%

1 2

RH120 4.7K_0402_5%

RPH3 and close UH6

RPH3

1 8 2 7 3 6 4 5

15_0804_8P4R_5%

8M_SINGLE@

1 2

RH30 15_0402_5%

8M_SINGLE@

GPP_A11/PME# RSVD

RSVD RSVD RSVD

TP2 TP1

SPI0_MOSI SPI0_MISO SPI0_CS0# SPI0_CLK SPI0_CS1# SPI0_IO2 SPI0_IO3 SPI0_CS2#

GPP_D1/SPI1_CLK GPP_D0/SPI1_CS# GPP_D3/SPI1_MOSI GPP_D2/SPI1_MISO GPP_D22/SPI1_IO3 GPP_D21/SPI1_IO2

SKL-H-PCH_BGA837

+3VALW_SPI

PCH_SPI_SOPCH_SPI_SO_0_R PCH_SPI_SIPCH_SPI_SI_0_R PCH_SPI_CLKPCH_SPI_CLK_0_R PCH_SPI_IO3PCH_SPI_IO3_0_R

PCH_SPI_IO2PCH_SPI_IO2_0_R

1 2

RH115 0_0402_5%

SPI ROM

RH19 0_0402_5%

+3VS

IN1

IN2

Single SPI ROM_CS0#

To SPI ROM To SPI ROM

SPT-H_PCH

REV = 1.3

PLT_RST_BUF# (34,36)

GPP_B13/PLTRST#

GPP_G16/GSXCLK

GPP_G12/GSXDOUT

GPP_G13/GSXSLOAD

GPP_G14/GSXDIN

GPP_G15/GSXSRESET#

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

GPP_H18/SML4ALERT#

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H15/SML3ALERT#

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H12/SML2ALERT#

GPP_H11/SML2DATA

GPP_H10/SML2CLK

1 OF 12

INTRUDER#

XDP_SPI_SI(6) XDP_SPI_IO2(6)

Dual SPI ROM_CS1#

PCH_SPI_SO_1_R PCH_SPI_SO PCH_SPI_SI_1_R PCH_SPI_SI PCH_SPI_CLK_1_R PCH_SPI_IO3_1_R PCH_SPI_IO3

PCH_SPI_IO2_1_R PCH_SPI_IO2

EC_SCI#_G3

PLT_RST#

BB27 P43

R39 R36 R42 R41

I2C_TS_INT#

AF41 AE44

TP_INT#

BC23 BD24

BC36 BE34 BD39 BB36 BA35

for server and WS use

BC35 BD35 AW35 BD34

SM_INTRUDER#

BE11

RH21,RH22 place to within 1100 mil of SPIO_MOSI/SPI0_IO2 pin for XDP

RPH15 and close UH7

RPH15

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

8M_DUAL@

1 2

RH118 33_0402_5%8M_DUAL@

Remove RPH4 05/18

SPI ROM ( 8MByte )

PCH_SPI_CS#0

PCH_SPI_IO2_0_R

4 4

ROM Socket

PCH_SPI_CS#0 PCH_SPI_IO2_0_R PCH_SPI_IO3_0_R

UH6

/CS

DO(IO1)

/WP(IO2)

GND

W25Q64FVSSIQ_SO8

8M_SINGLE@

@EMC@

1 2

RH35 0_0402_5%

JH1

CS#

WP#

HOLD#

GND

ACES_91960-0084N_MX25L3206EM2I

CONN@

+3VALW_SPI +3VALW_SPI

VCC

/HOLD(IO3)

CLK

DI(IO0)

@EMC@

CH7 10P_0402_50V8J

VCC

SCLK

SI/SIO0

SO/SIO1

1 2

PCH_SPI_IO3_0_RPCH_SPI_SO_0_R PCH_SPI_CLK_0_R PCH_SPI_SI_0_R

1 2

+3VALW_SPI

PCH_SPI_CLK_0_R PCH_SPI_SI_0_R PCH_SPI_SO_0_R

CH6 .1U_0402_16V7K

SPI ROM ( 2/4/8/16MByte )

PCH_SPI_CS#1 PCH_SPI_SO_1_R PCH_SPI_IO2_1_R PCH_SPI_CLK_1_R

RPH3

33_0804_8P4R_5%

8M_DUAL@

SD309330A80

1 2 3 4

PCH_SPI_CLK_1_RPCH_SPI_CLK_0_R

UH7

8M_DUAL@

/CS DO/IO1

/HOLD/IO3 /WP/IO2 GND

W25Q16DVSSIQ_SO8

@EMC@

1 2

RH119

0_0402_5%

RH30

33_0402_5%

8M_DUAL@

SD028330A80

DI/IO0

VCC CLK

DH1 RB751V-40_SOD323-2

1 2

RH148 0_0402_5%@

PAD

RH13 1M_0402_5%

RH21 1K_0402_1%CMC@

1 2

RH22 1K_0402_1%CMC@

1 2

PCH_SPI_CLK

PCH_SPI_IO3_1_R

7 6

PCH_SPI_SI_1_R

UH6

W25Q64FVSSIQ_SO8

8M_DUAL@

SA000039A30

3/17 PCH internal PU need confirm with BIOS

RH7 10K_0402_5%

1 2

RH8 0_0402_5%

PLT_RST# (23,39,40)

T11

1 2

I2C_TS_INT# (30)

EC_TP_INT# (39,40)

PCH_SPI_SI PCH_SPI_IO2

Follow MOW WW36 pull down with pre-ES1/ES1 samples

CH52 .1U_0402_16V7K

8M_DUAL@

1 2

@EMC@

1 2

CH53 10P_0402_50V8J

EC_SCI#

+RTCVCC

EC_SCI# (39)

EC_SCI#_G3

DGPU_PRSNT#

Follow MOW 2015WW09

PCH_SPI_IO2

PCH_SPI_IO3

RH28 1K_0402_1%@

1 2 1 2

RH29 1K_0402_1%@

RH32 1K_0402_1%ES2@

1 2 1 2

RH33 1K_0402_1%ES1@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CLINK

SPT-H_PCH

FAN

3 OF 12

PCIe/SATA

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2 GPP_F0/SATAXPCIE3/SATAGP3 GPP_F1/SATAXPCIE4/SATAGP4 GPP_F2/SATAXPCIE5/SATAGP5 GPP_F3/SATAXPCIE6/SATAGP6 GPP_F4/SATAXPCIE7/SATAGP7

HOST

DGPU_PRSNT#

UH1C

AV2

CL_CLK

AV3

CL_DATA

AW2

CL_RST#

R44

GPP_G8/FAN_PWM_0

R43

GPP_G9/FAN_PWM_1

U39

GPP_G10/FAN_PWM_2

N42

GPP_G11/FAN_PWM_3

U43

GPP_G0/FAN_TACH_0

U42

GPP_G1/FAN_TACH_1

U41

GPP_G2/FAN_TACH_2

M44

GPP_G3/FAN_TACH_3

U36

GPP_G4/FAN_TACH_4

P44

GPP_G5/FAN_TACH_5

T45

GPP_G6/FAN_TACH_6

T44

GPP_G7/FAN_TACH_7

B33

PCIE11_TXP

C33

PCIE11_TXN

K31

PCIE11_RXP

L31

PCIE11_RXN

AB33

GPP_F10/SCLOCK

AB35

GPP_F11/SLOAD

AA44

GPP_F13/SDATAOUT0

AA45

GPP_F12/SDATAOUT1

B38

PCIE14_TXN/SATA1B_TXN

C38

PCIE14_TXP/SATA1B_TXP

D39

PCIE14_RXN/SATA1B_RXN

E37

PCIE14_RXP/SATA1B_RXP

C36

PCIE13_TXN/SATA0B_TXN

B36

PCIE13_TXP/SATA0B_TXP

G35

PCIE13_RXN/SATA0B_RXN

E35

PCIE13_RXP/SATA0B_RXP

A35

PCIE12_TXP

B35

PCIE12_TXN

H33

PCIE12_RXP

G33

PCIE12_RXN

J45

PCIE20_TXP/SATA7_TXP

K44

PCIE20_TXN/SATA7_TXN

N38

PCIE20_RXP/SATA7_RXP

N39

PCIE20_RXN/SATA7_RXN

H44

PCIE19_TXP/SATA6_TXP

H43

PCIE19_TXN/SATA6_TXN

L39

PCIE19_RXP/SATA6_RXP

L37

PCIE19_RXN/SATA6_RXN

SKL-H-PCH_BGA837

+3VALW_SPI

REV = 1.3

DIS,Optimus10

UMA

Compal Secret Data

2014/12/31 2016/12/31

Compal Secret Data

Deciphered Date

PCIE9_RXN/SATA0A_RXN

PCIE9_RXP/SATA0A_RXP PCIE9_TXN/SATA0A_TXN

PCIE9_TXP/SATA0A_TXP

PCIE10_RXN/SATA1A_RXN

PCIE10_RXP/SATA1A_RXP PCIE10_TXN/SATA1A_TXN

PCIE10_TXP/SATA1A_TXP

PCIE15_RXN/SATA2_RXN PCIE15_RXP/SATA2_RXP PCIE15_TXN/SATA2_TXN

PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN PCIE16_RXP/SATA3_RXP PCIE16_TXN/SATA3_TXN

PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN PCIE17_RXP/SATA4_RXP PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN PCIE18_RXP/SATA5_RXP PCIE18_TXN/SATA5_TXN

PCIE18_TXP/SATA5_TXP

GPP_E8/SATALED#

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THERMTRIP#

PLTRST_PROC#

PM_DOWN

+3VALW_PCH_PRIM

RH31

UMA@

10K_0402_5%

RH34

VGA@

10K_0402_5%

GPP_F13

DGPU_PRSNT#

PECI

PM_SYNC

G31 H31 C31 B31

G29 E29 C32 B32

F41 E41 B39 A39

D43 E42 A41 A40

H42 H40 E45 F45

K37 G37 G45 G44

AD44 AG36 AG35 AG39 AD35 AD31 AD38 AC43 AB44

W36 W35 W42

AJ3 AL3 AJ4 AK2 AH2

CHECK ACER DVR for port use 12/08 Change Port, follow DVR1044_R1.03

SATA_PRX_DTX_N2 (37) SATA_PRX_DTX_P2 (37)

SATA_PTX_DRX_N2 (37) SATA_PTX_DRX_P2 (37)

SATA_PRX_DTX_N3 (37) SATA_PRX_DTX_P3 (37) SATA_PTX_DRX_N3 (37)

SATA_PTX_DRX_P3 (37)

1 2

RH14 10K_0402_5%

1 2 1 2

RH15 10K_0402_5% RH16 10K_0402_5%

1 2 1 2

RH17 10K_0402_5%

1 2

RH18 10K_0402_5% RH20 10K_0402_5%

FOR SERVER & WS ONLY

PCH_BKL_PWM ENBKL

PCH_ENVDD

PCH_THERMTRIP# PCH_PECI H_PM_SYNC_R PLTRST_CPU#

PCH_BKL_PWM ENBKL

PCH_PECI

@ @ @ @

RH23 620_0402_5%

1 2 1 2

RH121 12.1_0402_1%@ RH12 30_0402_1%

1 2

RH25 100K_0402_5%@ RH26 100K_0402_5%@

1 2 1 2

RH124 10K_0402_5%@

1 2

RH152 10K_0402_5%

check PDG 52.4.2 if DOC update 10/7 dan

update by PDG 15.1.2 11/6 dan

PCH_BKL_PWM (30) ENBKL (39) PCH_ENVDD (30)

PLTRST_CPU# (9)

PM_DOWN_R (9)

Functional Strap Definitions

SPI0_MOSI int. PH This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.

SPI0_MISO int. PH This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.

SPI0_IO2 int. PH This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.

SPI0_IO3 int. PH This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.

GPP_H12 int. PD This strap should sample LOW.

Compal Electronics, Inc.

Title

PCH(2/7)SPI,SATA,XDP

Size Document Number Re v

Custom

A4WAD M/B LA-C871P

Date: Sheet of

HDD

ODD

THERMTRIP# (9) H_PECI (9,39) H_PM_SYNC (9)

+1.0VALW_PRIM

17 61Monday, July 13, 2015

1.0

smd.db-x7.ru

HDA for AUDIO

ME_EN(39)

HDA_SDOUT_R(41) HDA_SYNC_R(41) HDA_RST#_R(41) HDA_BIT_CLK_R(41)

1 1

+3VALW_DSW

HDA_SDIN0(41)

+3VALW_PCH_PRIM

10K_0804_8P4R_5%

RPH6

18 27 36 45

Follow 543016_SKL_U_Y_PDG_0_9

+3VALW_DSW

EC_RSMRST#

2 2

+RTCVCC

CRB 8.2K

1 2

RH40 10K_0402_5%

1 2

RH41 10K_0402_5%

1 2

RH42 1K_0402_5%

PCH_DPWROK

RH44 0_0402_5%

RH45 0_0402_5%

JCMOS1 0_0603_5%@ JCMOS2 0_0603_5%@

PCH_PWROKSYS_PWROK

1 2

RH46 20K_0402_5%

1 2

CH8 1U_0402_6.3V6K

1 2

RH49 20K_0402_5%

1 2

CH9 1U_0402_6.3V6K

1 2 1 2

Place at RAM DOOR

3 3

Functional Strap Definitions

SMBALERT# / GPP_C2 int. PD 0 = Disable Intel ME (TLS) (Default) 1 = Enable Intel ME (TLS)

SML0ALERT# / GPP_C5 int. PD 0 = LPC Is selected for EC. (Default) 1 = eSPI Is selected for EC.

SML1ALERT# / PCHHOT# / GPP_B23 int. PD

SPKR / GPP_B14 int. PD 0 = Disable “ Top Swap” mode. ( Default ) 1 = Enable “ Top Swap” mode.

HDA_SDO

4 4

int. PD 0 = Enable security measures defined in the Flash Descriptor. (Default) 1 = Disable Flash Descriptor Security (override).

DDPB_CTRLDATA / GPP_I6 int. PD 0 = Port B is not detected. 1 = Port B is detected. (Default)

1 2

RH36 0_0402_5%

RPH5

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

SYS_RESET#

LAN_WAKE# EC_RSMRST# PCH_PWROK

PM_BATLOW# AC_PRESENT_R

WAKE#

PCH_SRTCRST#

PCH_RTCRST#

HDA_SDOUT HDA_SYNC HDA_RST# HDA_BIT_CLK

HDA_SDIN0

WAKE# (DSX wake event) 10 KΩ pull- up t o VccDS W3_3. The pull-up is required even if PCIe* interface is not used on the plat f or m.

CPU_DISPA_SDO_R(6)

CPU_DISPA_SDI_R(6)

CPU_DISPA_BCLK_R(6)

Remove CLR ME

CLR CMOS

+3VALW_PCH_PRIM

+3VS

DDPC_CTRLDATA / GPP_I8 int. PD 0 = Port C is not detected. 1 = Port C is detected. (Default)

DDPD_CTRLDATA / GPP_I10 int. PD 0 = Port D is not detected. (Default) 1 = Port D is detected.

VGA HDM I

(SO-DIMM,G-sensor)

PCH_DP1_HPD(32) PCH_DP2_HPD(31)

PCH_EDP_HPD(30)

RH116 RH117

PCH_DMIC_DATA0(41) PCH_DMIC_CLK0(41)

PCH_PWROK(39,43) EC_RSMRST#(6,39)

PCH_SML1CLK(23) PCH_SML1DATA(23)

(VGA, EC, RTD2168)

1 2

RH142 4.7K_0402_5%

1 2

RH50 499_0402_1%

1 2

RH51 499_0402_1%

PCH_SMBALERT#

PCH_SML0CLK PCH_SML0DATA

T3809

1 2

30_0402_1%

1 2

30_0402_1%

PCH_DP1_HPD PCH_DP2_HPD

EC_SCI#_I3

PAD@

PCH_EDP_HPD

HDA_BIT_CLK HDA_RST# HDA_SDIN0

HDA_SDOUT HDA_SYNC

CPU_DISPA_SDO CPU_DISPA_SDI_R CPU_DISPA_BCLK

PCH_DMIC_DATA0 PCH_DMIC_CLK0

PCH_RTCRST# PCH_SRTCRST#

PCH_PWROK EC_RSMRST#

PCH_DPWROK PCH_SMBALERT#

PAD

PCH_SMBCLK PCH_SMBDATA PCH_SML0ALERT#

PAD

PCH_SML0CLK PCH_SML0DATA PCH_SML1ALERT#

PAD

PCH_SML1CLK PCH_SML1DATA

UH1E

AW4

GPP_I0/DDPB_HPD0

AY2

GPP_I1/DDPC_HPD1

AV4

GPP_I2/DDPD_HPD2

BA4

GPP_I3/DDPE_HPD3

BD7

GPP_I4/EDP_HPD

SKL-H-PCH_BGA837

REV = 1.3

UH1D

BA9

HDA_BCLK

BD8

HDA_RST#

BE7

HDA_SDI0

BC8

HDA_SDI1

BB7

HDA_SDO

BD9

HDA_SYNC

BD1

RSVD_BD1

BE2

RSVD_BE2

AM1

DISPA_SDO

AN2

DISPA_SDI

AM2

DISPA_BCLK

AL42

GPP_D8/I2S0_SCLK

AN42

GPP_D7/I2S0_RXD

AM43

GPP_D6/I2S0_TXD

AJ33

GPP_D5/I2S0_SFRM

AH44

GPP_D20/DMIC_DATA0

AJ35

GPP_D19/DMIC_CLK0

AJ38

GPP_D18/DMIC_DATA1

AJ42

GPP_D17/DMIC_CLK1

BC10

RTCRST#

BB10

SRTCRST#

AW11

PCH_PWROK

BA11

RSMRST#

AV11

DSW_PWROK

BB41

GPP_C2/SMBALERT#

AW44

GPP_C0/SMBCLK

BB43

GPP_C1/SMBDATA

BA40

GPP_C5/SML0ALERT#

AY44

GPP_C3/SML0CLK

BB39

GPP_C4/SML0DATA

AT27

GPP_B23/SML1ALERT#/PCHHOT#

AW42

GPP_C6/SML1CLK

AW45

GPP_C7/SML1DATA

SKL-H-PCH_BGA837

REV = 1.3

+3VALW_PCH_PRIM

+3VS

+3VALW_PCH_PRIM

+3VS

SPT-H_PCH

AUDIO

2.2K_0804_8P4R_5%

PDG_0_71 requirement PH to +3V_PCH 10/14 Dan

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I9/DDPD_CTRLCLK

GPP_I10/DDPD_CTRLDATA

5 OF 12

SPT-H_PCH

SMBUS

RPH8

18 27 36 45

RPH9

18 27 36 45

GPP_F14 GPP_F23

GPP_F22 GPP_G23 GPP_G22 GPP_G21 GPP_G20

GPP_H23

GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_A13/SUSWARN#/SUSPWRDNACK

JTAG

4 OF 12

PCH_SML1CLK PCH_SML1DATA PCH_SML1CLK_R PCH_SML1DATA_R

PCH_SMBCLK PCH_SMBDATA PCH_SMBCLK_R PCH_SMBDATA_R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCH_DP2_CTRL_CLK

BB3

PCH_DP2_CTRL_DATA

BD6

PCH_DP1_CTRL_CLK

BA5

PCH_DP1_CTRL_DATA

BC4 BE5 BE6

Y44 V44 W39 L43 L44 U35 R35 BD36

GPP_A8/CLKRUN# GPD11/LANPHYPC GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_B1

GPP_G17/ADR_COMPLETE

GPP_B0

GPP_B11

SYS_PWROK

WAKE#

GPD6/SLP_A#

SLP_LAN#

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE# GPD1/ACPRESENT

SLP_SUS#

GPD3/PWRBTN#

SYS_RESET#

GPP_B14/SPKR

PROCPWRGD

ITP_PMODE

JTAGX JTAG_TMS JTAG_TDO

JTAG_TDI

JTAG_TCK

2014/12/31 2016/12/31

BB17 AW22

AR15 AV13 BC14

BD23 AL27 AR27 N44 AN24 AY1

BC13 BC15 AV15 BC26 AW15 BD15 BA13

AN15 BD13 BB19 BD19

BD11 BB15 BB13 AT13 AW1 BD26 AM3

AT2 AR3 AR2 AP1 AP2 AN3

PCH_SMBCLK_R(14,15,42)

PCH_SMBDATA_R(14,15,42)

PCH_SML1CLK_R(32,39)

PCH_SML1DATA_R(32,39)

(EC, RTD2168)

PCH_DP2_CTRL_CLK (31) PCH_DP2_CTRL_DATA (31)

T3808

PAD

1 2

RH37 2.2K_0402_5%

T10

PAD

H_SKTOCC# (9)

PM_CLKRUN#

SLP_WLAN# DDR_DRAMRST#

PCH_VRALERT#

SYS_PWROK

WAKE# PM_SLP_A#

SLP_LAN# PM_SLP_S0# PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#

SUSCLK PM_BATLOW#

1 2

RH52 0_0402_5%

LAN_WAKE# AC_PRESENT_R PM_SLP_SUS# PBTN_OUT#_R SYS_RESET# PCH_SPKR

H_CPUPWRGD

XDP_ITP_PMODE CPU_XDP_TCK0 CPU_XDP_TMS CPU_XDP_TDO CPU_XDP_TDI PCH_JTAG_TCK1

PCH_SML1CLK_R

PCH_SML1DATA_R

Compal Secret Data

Deciphered Date

HDM I

PM_CLKRUN# (40)

T3827

PAD

DDR_DRAMRST# (14,15)

SYS_PWROK (39,43)

PAD

T3828

PAD

PM_SLP_S0# (39) PM_SLP_S3# (39,43) PM_SLP_S4# (39,43)

PAD

SUSCLK (36)

T3810

PAD

PCH_SPKR (41)

H_CPUPWRGD (9)

XDP_ITP_PMODE (6) CPU_XDP_TCK0 (6,9) CPU_XDP_TMS (6,9) CPU_XDP_TDO (6,9) CPU_XDP_TDI (6,9) PCH_JTAG_TCK1 (6)

PCH_SMBCLK_R

PCH_SMBDATA_R

+3VS

T12

PAD

SUSPWRDNACK (39)

+3VS

QH1B DMN66D0LDW-7_SOT363-6

+3VS

QH2B DMN66D0LDW-7_SOT363-6

QH1A DMN66D0LDW-7_SOT363-6

QH2A DMN66D0LDW-7_SOT363-6

PCH_SMBCLK

PCH_SMBDATA

PCH_SML1CLK

PCH_SML1DATA

+3VS

PM_CLKRUN#

PCH_VRALERT#

PBTN_OUT#_R

AC_PRESENT_R

PM_SLP_S3#

PM_SLP_S4#

SYS_PWROK

SYS_RESET#

RH39 10K_0402_5%

RH43 10K_0402_5%

RH128 100K_0402_5%

1 2

RH47 0_0402_5%

1 2

RH48 0_0402_5%

1 2

RH130 10K_0402_5%

CH10 .1U_0402_16V7K

@EMC@

Compal Electronics, Inc.

Title

PCH(3/7)GPIO,SMBUS

Size Document Number Re v

Custom

A4WAD M/B LA-C871P

Date: Sheet o f

Date: Sheet of

1 2

PAD

CRB 8.2K

+3VALW_PCH_PRIM

T3806

T3807

+3VALW_DSW

PBTN_OUT# (39)

AC_PRESENT (39)

18 61Monday, July 13, 2015

1.0

smd.db-x7.ru

1 1

2 2

3 3

+3VS

RPH11

LAN_CLKREQ#

CLKREQ_PCIE#3

CLKREQ_PCIE#5

CLKREQ_PCIE#4

10K_0804_8P4R_5%

RPH12

CLKREQ_PCIE#12

CLKREQ_PCIE#7

CLKREQ_PCIE#10

WLAN_CLKREQ#

10K_0804_8P4R_5%

RPH13

CLKREQ_PCIE#8

CLKREQ_PCIE#9

CLKREQ_PCIE#6

CLKREQ_PCIE#13

10K_0804_8P4R_5%

RPH14

CLKREQ_PCIE#14

CLKREQ_PCIE#11

CLKREQ_PCIE#15

36 45

10K_0804_8P4R_5%

Follow PDG 0.71Table 52-17 10/13 Dan CHECK NEEDED IF UNUSE?

DGPU_PWROK(23,43,56,58)

Pull high @ VGA side

PEG_CLKREQ#(23)

RTCX1

1 2

RH71 10M_0402_5%

1 2

32.768KHZ_9PF_CM7V-T1A9.0PF20PPM 10P_0402_50V8J

CH13

RTCX2

YH1

CH14

REV = 1.3

SPT-H_PCH

CLKOUT_CPUPCIBCLK_N

CLKOUT_CPUPCIBCLK_P

7 OF 12

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

CLKOUT_PCIE_N6 CLKOUT_PCIE_P6

CLKOUT_PCIE_N7 CLKOUT_PCIE_P7

CLKOUT_PCIE_N8 CLKOUT_PCIE_P8

CLKOUT_PCIE_N9 CLKOUT_PCIE_P9

CLKOUT_PCIE_N10 CLKOUT_PCIE_P10

CLKOUT_PCIE_N11 CLKOUT_PCIE_P11

L1 L2 J1 J2

N7 N8

L7 L5

D3 F2

E5 G4

D5 E6

D8 D7

R8 R7

U5 U7

W10 W11

N3 N2

P3 P2

R3 R4

CLK_CPU_ITP# CLK_CPU_ITP CPU_PCIBCLK# CPU_PCIBCLK

CLK_PEG_VGA# CLK_PEG_VGA

CLK_PCIE_LAN# CLK_PCIE_LAN

CLK_PCIE_WLAN# CLK_PCIE_WLAN

PAD

T3820

PAD

T3821

CPU_PCIBCLK# (9) CPU_PCIBCLK (9)

CLK_PEG_VGA# (23)

CLK_PEG_VGA (23)

CLK_PCIE_LAN# (34)

CLK_PCIE_LAN (34)

CLK_PCIE_WLAN# (36)

CLK_PCIE_WLAN (36)

DGPU

GLAN

NGFF WL+BT(KEY E)

UH1G

AR17

GPP_A16/CLKOUT_48

CPU_24M(9) CPU_24M#(9)

CPU_BCLK(9) CPU_BCLK#(9)

XTAL24_OUT XTAL24_IN

+1.0VALW_VCCCLK5

+3VS

RH68

RH70

2.2K_0402_5%

GND

10K_0402_5%

VGA_CLKREQ#

XTAL24_IN

15P_0402_50V8J

CH12

VGA@

QH3L2N7002LT1G_SOT23-3

RH69

2.2K_0402_5%

XTAL24_OUT

1 2

RH72 1M_0402_5%

YH2 24MHZ_12PF_7V24000020

15P_0402_50V8J

GND

8.2P_0402_50V8D

CH11

FOLLOW RVP11

RH67

2.7K_0402_1%

PH at DGPU side

LAN_CLKREQ#(34) WLAN_CLKREQ#(36)

XCLK_BIASREF

RTCX1 RTCX2

VGA_CLKREQ# LAN_CLKREQ# WLAN_CLKREQ# CLKREQ_PCIE#3 CLKREQ_PCIE#4 CLKREQ_PCIE#5 CLKREQ_PCIE#6 CLKREQ_PCIE#7 CLKREQ_PCIE#8 CLKREQ_PCIE#9 CLKREQ_PCIE#10 CLKREQ_PCIE#11 CLKREQ_PCIE#12 CLKREQ_PCIE#13 CLKREQ_PCIE#14 CLKREQ_PCIE#15

CLKOUT_CPUNSSC_P

CLKOUT_CPUNSSC_N

CLKOUT_CPUBCLK_P

CLKOUT_CPUBCLK_N

XTAL24_OUT

XTAL24_IN

XCLK_BIASREF

BC9

RTCX1

BD10

RTCX2

BC24

GPP_B5/SRCCLKREQ0#

AW24

GPP_B6/SRCCLKREQ1#

AT24

GPP_B7/SRCCLKREQ2#

BD25

GPP_B8/SRCCLKREQ3#

BB24

GPP_B9/SRCCLKREQ4#

BE25

GPP_B10/SRCCLKREQ5#

AT33

GPP_H0/SRCCLKREQ6#

AR31

GPP_H1/SRCCLKREQ7#

BD32

GPP_H2/SRCCLKREQ8#

BC32

GPP_H3/SRCCLKREQ9#

BB31

GPP_H4/SRCCLKREQ10#

BC33

GPP_H5/SRCCLKREQ11#

BA33

GPP_H6/SRCCLKREQ12#

AW33

GPP_H7/SRCCLKREQ13#

BB33

GPP_H8/SRCCLKREQ14#

BD33

GPP_H9/SRCCLKREQ15#

R13

CLKOUT_PCIE_N15

R11

CLKOUT_PCIE_P15

CLKOUT_PCIE_N14

CLKOUT_PCIE_P14

CLKOUT_PCIE_N13

CLKOUT_PCIE_P13

CLKOUT_PCIE_N12

CLKOUT_PCIE_P12

SKL-H-PCH_BGA837

change YH1 PN to SJ10000L000

4 4

change CH13,CH14,CH11,CH12 value

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/12/31 2016/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCH(4/7)CLK

Size Document Number Re v

Custom

A4WAD M/B LA-C871P

Date: Sheet o f

Date: Sheet of

19 61Monday, July 13, 2015

1.0

+ 42 hidden pages

Compal LA-C871P Schematics Rev1.0

Specifications and Main Features

Frequently Asked Questions

User Manual