Compal LA-C791P Schematics Rev1.0

A

B

C

D

E

MODEL NAME : LA-C791P

PCB NO : DAA000AS000

BOM P/N :

1 1

Dell/Compal Confidential

2 2

ZZZ

MB_PCB

Schematic Document

Jayton 2 (Skylake Y)

3 3

2015-11-09

Rev: 1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2041/09/08 2013/10/28

Compal Secre t Data

Deciphered Date

D

Compal Electron ics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electron ics, Inc.

P01-Cover Page

LA-C791P

E

1 66Friday, Nove mber 27, 201 5

1.0

A

B

C

D

E

eDP Panel

10.8" FHD

Touch Screnn/Pen Cntrl

1 1

Wacom W9006

P.23

P.29

M2 2230-Key A Dual Band Wifi/BT

P.25

M2 3042 -Key B WWAN 4GLTE- Intel Telit

DB

uSIM Conn

P.26

iTouch

M2 2280 -Key M

2 2

SATA/PCIE SSD

P.27

e-Compass + Accelerometer +

eDP 1.3 (2 LANE)

P.28

I2C

PCIE *1

SMlink

USB2.0

USB 2.0

USB3.0/SSIC

SPI

SATA/PCIE*2

I2C

Intel

Sky Lake Y (4W)

Memory Bus (LPDDR3)

Dual Channel 1600MHz

PCIE 2.0

PCIE Re-Driver SN65LVPE501

USB3.0

CSIx4

CSIx2

HDA

DB

Digital MIC *4

Channel A LPDDR3, 16Gb/32Gb (x64 ) per package

Channel B LPDDR3, 16Gb/32Gb (x64 ) per package

Cardreader RTS5242

DS4 Camera

WF Camera

UF Camera

Iris Scan

Audio Codec ALC3266

P.29

Line Out

I2S

8MP

5MP

P.24

P.18

P.19

DB

P.39

P.30

P.29

Smart Amp ALC1006

PMIC (Power)

Headphone Jack

( iPhone & Nokia compatible)

P.38

Int. Speaker

P.29

P.38

Gyro DE9DS1TR

DB

P.31

ALS with PS CM36286

SPI ROM 16M+8M

TPM 2.0 NPCT650

P.07

P.28

USH Module : Smart Card Finger Print NFC

3 3

USB 3.0 + PS Type-A CONN.

USB 3.0 + AM Type C CONN.

4 4

5V VR

P.29

MUX for Win7 debug

P.30

TX/RX

HS MUX HDS3SS460

P.40, 41

GPIO

USB2.0/SMBus

CC

P.45 P.43

Vbus

PD Solution TPS65982

DP Re-Driver

USB Re-Driver

Charger

DC/DC Interface CKT.

A

Power Circuit DC/DC

P.36 ~ 48P.30, 31

B

SPI

USB2.0

UART

USB2.0

USB3.0

DP1.2

USB3.0

SMBus

USB2.0

LPC Bus

SMSC MEC1641

HP Amp TPA6132A2

USB3.0

USB2.0

DP1.2

USB switch TS3USB221

DP Re-Driver

P.28

PS8330

DP1.2 HDMI1.4

SMLink

Page 5 ~ 22

SMBus

P.35

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DP-MUX PS8338

A

2041/09/08 2013/10/28

P.38

Proximity SX9306

Compal Secre t Data

Deciphered Date

HDMI LS PS8407

P.27

D

P.38

40 Pin Base Docking Conn

B

A

Micro HDMI CONN.

NFC

USB2.0

B

Pogo 12pin

Compal Electron ics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electron ics, Inc.

P02-Block Diagram

LA-C791P

E

P.28

DB

P.30

1.0

2 66Friday, Nove mber 27, 201 5

1.0

A

1 1

B

C

D

E

LS-C791P Card Reader, Senso r, SIM Card PWR, Home Key Button, Speaker-R, LED

BTB FPC 50 pin

Camera Cable

Coaxial and Wire

Front & Rear Camera

eDP Cable

Coaxial and Wire

LS-C792P DOCK CONN

2 2

Wire 2 pin

CABLE

10 pin

Battery Pack

3 3

FPC 100 pin

LA-C791P M/B

FFC

26 pin

USH Module

FFC 8 pin

LCD Panel

Touch Panel Control Baor d

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

C

2041/09/08 2013/10/28

Compal Secre t Data

Deciphered Date

D

Compal Electron ics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electron ics, Inc.

P03-DaughterB block diagram

LA-C 791 P

E

3 66Friday, Nove mber 27, 201 5

1.0

A

Board ID Table

3.3V +/- 5%Vcc

0 1 2 3 4 5 6 7

SMBUS Control Table

PCH_SML0CLK PCH PCH_SML0DATA

PCH_SML1CLK PCH_SML1DATA

SMBCLK SMBDATA

EC_SMB00_CLK EC_SMB00_DAT

EC_SMB01_CLK EC_SMB01_DAT

EC_SMB03_CLK EC_SMB03_DAT

EC_SMB04_CLK EC_SMB04_DAT

EC_SMB05_CLK EC_SMB05_DAT

EC_SMB07_DAT

1 1

RBoard ID

240K +/- 5% 4700p 130K +/- 5% 62K +/- 5% 33K +/- 5%

8.2K +/- 5%

4.3K +/- 5% 2K +/- 5%

NC

SOURCE

PCH

MEC1641

MEC1641EC_SMB07_CLK

C

4700p 4700p 4700p 4700p 4700p 4700p

Base BATT

V

Charger

V

REV

XDP

V

NFC

V

USH

V

BOARD ID Table

Board ID

0 1 2 3 4 5 6 7

PD Controller

V V

Trinity Dock

PCB Revision

0.1

0.2

0.3

0.4

0.5

1.0

P-Sensor

V

Link

Flexible I/O

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Interface DESTINATION

USB 3.0 #1

USB 3.0 #2/SSIC

USB 3.0 #3

USB 3.0 #4

USB Type-C

NGFF (WWAN)

BASE

DS4 CAM

USB 3.0 #5 USB Type-A

PCI-E #7/SATA #0

PCI-E #8

PCI-E #9

NGFF (SSD)

NGFF (WLAN)

PCI-E #10 Card Reader

DESTINATIONUSB 2.0 PORT#

1

2

3

5

7

9

USB Type-C

BT

WWAN NGFF (SSD)

BASE

CLK

USH

USB Type-A

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

FLEX CLOCKS DESTINATION

CLKOUT_LPC_0

CLKOUT_LPC_1

DESTINATIONDIFFERENTIAL

Card Reader

NGFF (WLAN)

EC LPC

Debug

Symbol Note :

: means de-pop

@

DDI PORT# DESTINATION

DDI

B

USB Type-C

C DP MUX

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

A

2041/09/08 2013/10/28

Compal Secre t Data

Deciphered Date

Compal Electron ics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electron ics, Inc.

P04-Notes List

LA-C791P

: means Digital Ground

: means Analog Ground

4 66Friday, Nove mber 27, 201 5

1.0

5

+3VS

1 2

RC89 2.2K_020 1_5%

1 2

RC85 2.2K_020 1_5% RC124 2.2K_020 1_5%

1 2 1 2

RC128 2.2K_020 1_5%

1 2

RC76 100K_020 1_5%

RH129 100K_020 1_5%@

1 2 1 2

RC74 100K_020 1_5%

1 2

RC73 100K_020 1_5%

Functional Strap Definitions

D D

PCH_DDI1_CLK PCH_DDI1_DAT PCH_DDI2_CLK PCH_DDI2_DAT TS_PD#

PCH_DDI2_HPD eDP_HPD DP_USBC_HPD

PS8338B internal pull doewn

GPP_E19 (Internal Pull Down): DDPB_CTRLDATA

0 = Port B is not detected.

1 = Port B is detected.

GPP_E21 (Internal Pull Down): DDPC_CTRLDATA

0 = Port C is not detected.

1 = Port C is detected.

C C

+3VALW_DSW

1 2

RC114 1K_0402_ 5%XDP@

+3V_PRIM

1 2

RC107 100K_040 2_5%XDP@

+1.0VS_VCCSTG

1 2

RC123 51_0402 _5%@

+1.0V_XDP

B B

RC77 1K_0402_ 5%XDP@

1 2

XDP_HOOK3

XDP_PRSENT#

XDP_PREQ#

XDP_RST#

+1.0V_VCCST

To CPU J TAG

PU/PD for CPU JTAG signals

+1.0VS_VCCSTG

1 2

RC119 51_0402 _5%@

1 2

RC97 51_0402 _5%@

R1

R2

+1.0VS_VCCSTG

R5

A A

R4

R3

R6

RC95 51_0402 _5%

1 2

RC104 51_0402 _5%@

RC93 5 1_0402_5%

PU/PD for PCH JTAG signals

1 2

RC120 51_0402 _5%

1 2

RC98 51_0402 _5%

1 2

RC94 51_0402 _5%

1 2

RC69 51_0402 _5%@

1 2

RC84 51_0402 _5%@

CPU_XDP_TMS

CPU_XDP_TDI

CPU_XDP_TDO

CPU_XDP_TRST#

12

CPU_XDP_TCK

12

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAGX

PCH_JTAG_TCK

5

To PCH J TAG

4

USB Type-C

DP MUX

+0.85VS_VCCIO

+1.0VS_VCCSTG

12

RC118 1K_0402_ 5%

+3V_PRIM

1 2

H_THERMTRIP#

5

P

NC A

G

3

H_PROCHOT#

H_PROCHOT#45,51,54 ,56,60

R423 1K_04 02_1%

1 2

CPU_XDP_TDO CPU_XDP_TCK CPU_XDP_TDI CPU_XDP_TMS CPU_XDP_TRST#

PCH_JTAG_TDO PCH_JTAG_TDI PCH_JTAG_TMS PCH_JTAG_TRST# PCH_JTAGX PCH_JTAG_TCK

CFG3

PCH_SPI_SI7,30

PCH_SPI_IO27

XDP_BPM#0 XDP_OBS0 XDP_BPM#1 XDP_OBS1

SIO_PWRBTN#9,21,45

PM_SYS_RESET#9,21

ITP_PMODE17

PCH_RSMRST#9,45

XDP_PRSENT#

4

RC117 499_040 2_1%

1 2

RC116 0_0201_ 5%XDP@

1 2

RC92 0_0201_ 5%XDP@ RC109 0_0201_ 5%XDP@

1 2 1 2

RC105 0_0201_ 5%XDP@

1 2

RC101 0_0201_ 5%XDP@

RC115 0_0201_ 5%XDP@

1 2 1 2

RC110 0_0201_ 5%XDP@

1 2

RC106 0_0201_ 5%XDP@

1 2

RC100 0_0201_ 5%XDP@

1 2

RC86 0_0201_ 5%XDP@ RC111 0_0201_ 5%XDP@

1 2

Closed t o CPU

RC63 1K_0201_ 5%XDP@

1 2

RC49 33_0201 _1%XDP@

1 2

RC13 33_0201 _1%XDP@

1 2

RC126 0_0201_ 5%XDP@

1 2

RC125 0_0201_ 5%XDP@

1 2

RC121 0_0201_ 5%XDP@ RC34 0_0201_ 5%XDP@

1 2 1 2

RC75 0_0201_ 5%XDP@

1 2

RC122 1K_0201_ 5%XDP@

U44

XDP@

4

Y

NL17SZ14DFT2 G_SOT353- 5

XDP_PRSENT 39

1 2

3

PCH_DDI1_N040 PCH_DDI1_P040 PCH_DDI1_N140 PCH_DDI1_P140 PCH_DDI1_N240 PCH_DDI1_P240 PCH_DDI1_N340 PCH_DDI1_P340

PCH_DDI2_N032 PCH_DDI2_P032 PCH_DDI2_N132 PCH_DDI2_P132 PCH_DDI2_N232 PCH_DDI2_P232 PCH_DDI2_N332 PCH_DDI2_P332

PCH_DDI2_CLK32 PCH_DDI2_DAT32

DP_LANE_CNT_EC45 DP_LANE_CNT_PD42

RC1 Width 20 mils, Spacing 25 mils, Length < 100 mil

RC64 0_0402_ 5%

RC35 49.9_02 01_1% RC36 49.9_02 01_1%

XDP_TDO XDP_TCK0 XDP_TDI XDP_TMS XDP_TRST#

XDP_TDO XDP_TDI XDP_TMS XDP_TRST# XDP_TCK0 XDP_TCK1

XDP_PIN1

XDP_HOOK3 XDP_PRSENT#

XDP_PWRBTN# XDP_DBRESET# XDP_RST# PWRGD_XDP

PCH_DDI1_CLK PCH_DDI1_DAT

PCH_DDI2_CLK PCH_DDI2_DAT

12

RC7024.9_04 02_1%

TC65

H_PECI45

12

@

TC50 TC64

SIO_EXT_SMI#45

TS_PD#22

NFC_DET#36

B4_SLP_S0#45

12 12

XDP_PREQ#11 XDP_PRDY#11

SMBDATA7

Security Classification

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

+EDP_COM

H_CATERR

H_PROCHOT#_R H_THERMTRIP#

SKTOCC#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3

SIO_EXT_SMI# TS_PD# NFC_DET#

CPU_POPIRCOMP PCH_OPIRCOMP

CFG017 CFG117

CFG217 CFG317

CFG417 CFG517

CFG617 CFG717

SMBCLK7

Issued Date

UC1A

A46

DDI1_TXN[0]

C46

DDI1_TXP[0]

C48

DDI1_TXN[1]

A48

DDI1_TXP[1]

B45

DDI1_TXN[2]

D45

DDI1_TXP[2]

B47

DDI1_TXN[3]

D47

DDI1_TXP[3]

A42

DDI2_TXN[0]

C42

DDI2_TXP[0]

A44

DDI2_TXN[1]

C44

DDI2_TXP[1]

B41

DDI2_TXN[2]

D41

DDI2_TXP[2]

B43

DDI2_TXN[3]

D43

DDI2_TXP[3]

L6

GPP_E18/DDPB_C TRLCLK

H6

GPP_E19/DDPB_C TRLDATA

H4

GPP_E20/DDPC_ CTRLCLK

F4

GPP_E21/DDPC_ CTRLDATA

M5

GPP_E22/DDPD_ CTRLCLK

L4

GPP_E23/DDPD_ CTRLDATA

A50

EDP_RCOMP

SKYLAKE_ULX_EDS/BGA

@

H49

F49

J48 H47 B62

H51

J50

F51 G50

E11

M9

BD8

BC11

BN17 BP16

XDP_PIN1 XDP_PREQ#

RC127 1K_0201_ 5%XDP@

CFG3

XDP_OBS0 XDP_OBS1

PWRGD_XDP XDP_PWRBTN#

XDP_HOOK3

XDP_TCK1 XDP_TCK0

1

2

PDG_Processor strap CFG[4] should be pulled

SKYLAKE_ULX

DDI

<DDI1>

<DDI2>

DISPLAY SIDEBANDS

SKYLAKE_ULX

UC1D

CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#

BPM#[0] BPM#[1]

CPU MISC

BPM#[2] BPM#[3]

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

PROC_POPIRCOMP PCH_OPIRCOMP

SKYLAKE_ULX_EDS/BGA

@

+1.0V_XDP +1.0V_XDP

1

XDP@

CC120

0.1U_0201_ 10V6K

2

+1.0V_XDP +1.0V_XDP

1 2

XDP_PWRBTN#

XDP@

CC123

0.1U_0201_ 10V6K

2041/09/08 2015/12/31

low to enable embedded DisplayPort*

DISPLAY

eDP

<DDI1>

<DDI2>

<DDI1>

GPP_E13/DDPB_H PD0

<DDI2>

GPP_E14/DDPC_ HPD1 GPP_E15/DDPD_ HPD2 GPP_E16/DDPE_H PD3

1 OF 20

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

JTAG

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

4 OF 20

XDP CONN

RC103 0_0402_ 5%XDP@

JXDP1

112 334 556 778 9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 515152 535354 555556 575758 595960

61

62

GND

E-T_660 1K-Y61N-04L

CONN@

Compal Secre t Data

Deciphered Date

2

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP

GPP_E17/EDP_HPD

EDP_BKLEN

EDP_BKLCTL

EDP_VDDEN

D53 C54 G48 C59 F47

B53 C50 B51 A52 C52 B49

JTAGX

1 2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

63

GND

H45 F45 J44 G44 J46 G46 H43 F43

J42 G42

EDP_DISP

A40

H41 F41 J40 G40

C11 L10 M7 F6 A7

D4 B6 D3

CPU_XDP_TCK CPU_XDP_TDI CPU_XDP_TDO CPU_XDP_TMS CPU_XDP_TRST#

PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TRST# PCH_JTAGX

+1.0V_XDP+1.0V_PRIM

XDP_RST# XDP_DBRESET#

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS XDP_PRSENT#

1

2

DP_USBC_HPD PCH_DDI2_HPD SPI1_INT# WLAN_RST# eDP_HPD

XDP_DBRESET#

XDP@

CC90

0.1U_0201_ 10V6K

1

eDP_TXN_P0 22 eDP_TXP_P0 22 eDP_TXN_P1 22 eDP_TXP_P1 22

eDP_AUXN 22 eDP_AUXP 22

TC56

RC71 0_0201_ 5%@

12

PCH_DDI1_AUXN 40 PCH_DDI1_AUXP 40 PCH_DDI2_AUXN 32 PCH_DDI2_AUXP 32

DP_USBC_HPD 40 PCH_DDI2_HPD 32

WLAN_RST# 26

eDP_HPD 22

ENBKL 22

PCH_INV_PWM 22

PCH_ENVDD 22

WLAN_RST# SPI1_INT# SIO_EXT_SMI# NFC_DET#

1

XDP@

CC122

0.1U_0201_ 10V6K

2

CFG17 17 CFG16 17

CFG8 17 CFG9 17

CFG10 17 CFG11 17

CFG19 17 CFG18 17

CFG12 17 CFG13 17

CFG14 17 CFG15 17

CK_XDP 9 CK_XDP# 9

Compal Electronics, Inc.

Title

P05-SKL Y(1/13) DDI,MSIC,XDP

Size Document Number Rev

C

LA-C791P

Date: Sheet

Date: Sheet of

eDP

1

+3V_PRIM

12

RC8710K_02 01_5% RC8810K_0201_5%

12 12

RC8210K_02 01_5%

12

RC42100K_020 1_5%

of

5 66Friday, Nove mber 27, 201 5

1.0

5

4

3

2

1

Un-nterleaved Memory

D D

M_A_DQ_[0..6 3]18

C C

B B

M_A_DQ_0 M_A_DQ_1 M_A_DQ_2 M_A_DQ_3 M_A_DQ_4 M_A_DQ_5 M_A_DQ_6 M_A_DQ_7 M_A_DQ_8

M_A_DQ_9 M_A_DQ_10 M_A_DQ_11 M_A_DQ_12 M_A_DQ_13 M_A_DQ_14 M_A_DQ_15 M_A_DQ_16 M_A_DQ_17 M_A_DQ_18 M_A_DQ_19 M_A_DQ_20 M_A_DQ_21 M_A_DQ_22 M_A_DQ_23 M_A_DQ_24 M_A_DQ_25 M_A_DQ_26 M_A_DQ_27 M_A_DQ_28 M_A_DQ_29 M_A_DQ_30 M_A_DQ_31 M_A_DQ_32 M_A_DQ_33 M_A_DQ_34 M_A_DQ_35 M_A_DQ_36 M_A_DQ_37 M_A_DQ_38 M_A_DQ_39 M_A_DQ_40 M_A_DQ_41 M_A_DQ_42 M_A_DQ_43 M_A_DQ_44 M_A_DQ_45 M_A_DQ_46 M_A_DQ_47 M_A_DQ_48 M_A_DQ_49 M_A_DQ_50 M_A_DQ_51 M_A_DQ_52 M_A_DQ_53 M_A_DQ_54 M_A_DQ_55 M_A_DQ_56 M_A_DQ_57 M_A_DQ_58 M_A_DQ_59 M_A_DQ_60 M_A_DQ_61 M_A_DQ_62 M_A_DQ_63

UC1B

AG61

DDR0_DQ[0 ]

AH60

DDR0_DQ[1 ]

AK62

DDR0_DQ[2 ]

AK60

DDR0_DQ[3 ]

AH62

DDR0_DQ[4 ]

AG63

DDR0_DQ[5 ]

AL61

DDR0_DQ[6 ]

AL63

DDR0_DQ[7 ]

AM60

DDR0_DQ[8 ]

AM62

DDR0_DQ[9 ]

AT60

DDR0_DQ[1 0]

AR61

DDR0_DQ[1 1]

AN61

DDR0_DQ[1 2]

AN63

DDR0_DQ[1 3]

AR63

DDR0_DQ[1 4]

AT62

DDR0_DQ[1 5]

AT56

DDR1_DQ[0 ]/DDR0_DQ[16]

AR55

DDR1_DQ[1 ]/DDR0_DQ[17]

AN57

DDR1_DQ[2 ]/DDR0_DQ[18]

AN55

DDR1_DQ[3 ]/DDR0_DQ[19]

AR57

DDR1_DQ[4 ]/DDR0_DQ[20]

AT58

DDR1_DQ[5 ]/DDR0_DQ[21]

AM58

DDR1_DQ[6 ]/DDR0_DQ[22]

AM56

DDR1_DQ[7 ]/DDR0_DQ[23]

AL55

DDR1_DQ[8 ]/DDR0_DQ[24]

AL57

DDR1_DQ[9 ]/DDR0_DQ[25]

AH58

DDR1_DQ[1 0]/DDR0_DQ[26 ]

AH56

DDR1_DQ[1 1]/DDR0_DQ[27 ]

AK58

DDR1_DQ[1 2]/DDR0_DQ[28 ]

AK56

DDR1_DQ[1 3]/DDR0_DQ[29 ]

AG55

DDR1_DQ[1 4]/DDR0_DQ[30 ]

AG57

DDR1_DQ[1 5]/DDR0_DQ[31 ]

BE55

DDR0_DQ[1 6]/DDR0_DQ[32 ]

BC55

DDR0_DQ[1 7]/DDR0_DQ[33 ]

BG53

DDR0_DQ[1 8]/DDR0_DQ[34 ]

BE53

DDR0_DQ[1 9]/DDR0_DQ[35 ]

BC53

DDR0_DQ[2 0]/DDR0_DQ[36 ]

BG55

DDR0_DQ[2 1]/DDR0_DQ[37 ]

BD52

DDR0_DQ[2 2]/DDR0_DQ[38 ]

BF52

DDR0_DQ[2 3]/DDR0_DQ[39 ]

BC51

DDR0_DQ[2 4]/DDR0_DQ[40 ]

BE51

DDR0_DQ[2 5]/DDR0_DQ[41 ]

BC49

DDR0_DQ[2 6]/DDR0_DQ[42 ]

BE49

DDR0_DQ[2 7]/DDR0_DQ[43 ]

BG51

DDR0_DQ[2 8]/DDR0_DQ[44 ]

BG49

DDR0_DQ[2 9]/DDR0_DQ[45 ]

BF48

DDR0_DQ[3 0]/DDR0_DQ[46 ]

BD48

DDR0_DQ[3 1]/DDR0_DQ[47 ]

BJ55

DDR1_DQ[1 6]/DDR0_DQ[48 ]

BL55

DDR1_DQ[1 7]/DDR0_DQ[49 ]

BJ53

DDR1_DQ[1 8]/DDR0_DQ[50 ]

BL53

DDR1_DQ[1 9]/DDR0_DQ[51 ]

BN55

DDR1_DQ[2 0]/DDR0_DQ[52 ]

BN53

DDR1_DQ[2 1]/DDR0_DQ[53 ]

BM52

DDR1_DQ[2 2]/DDR0_DQ[54 ]

BK52

DDR1_DQ[2 3]/DDR0_DQ[55 ]

BL51

DDR1_DQ[2 4]/DDR0_DQ[56 ]

BJ51

DDR1_DQ[2 5]/DDR0_DQ[57 ]

BL49

DDR1_DQ[2 6]/DDR0_DQ[58 ]

BJ49

DDR1_DQ[2 7]/DDR0_DQ[59 ]

BN49

DDR1_DQ[2 8]/DDR0_DQ[60 ]

BN51

DDR1_DQ[2 9]/DDR0_DQ[61 ]

BK48

DDR1_DQ[3 0]/DDR0_DQ[62 ]

BM48

DDR1_DQ[3 1]/DDR0_DQ[63 ]

SKYLAKE_ULX_EDS/BGA

@

SKYLAKE_ULX

DDR0_MA[5]/DDR 0_CAA[0]/DDR0_MA[5 ] DDR0_MA[9]/DDR 0_CAA[1]/DDR0_MA[9 ] DDR0_MA[6]/DDR 0_CAA[2]/DDR0_MA[6 ] DDR0_MA[8]/DDR 0_CAA[3]/DDR0_MA[8 ] DDR0_MA[7]/DDR 0_CAA[4]/DDR0_MA[7 ]

DDR0_BA[2]/D DR0_CAA[5]/DDR0_ BG[0] DDR0_MA[12]/ DDR0_CAA[6]/DDR0_ MA[12] DDR0_MA[11]/ DDR0_CAA[7]/DDR0_ MA[11]

DDR0_MA[15]/ DDR0_CAA[8]/DDR0_ ACT# DDR0_MA[14]/ DDR0_CAA[9]/DDR0_ BG[1]

DDR0_MA[13]/ DDR0_CAB[0]/DDR0_ MA[13]

DDR0_CAS#/DDR 0_CAB[1]/DDR0_MA[1 5]

DDR0_WE#/DDR 0_CAB[2]/DDR0_MA[1 4]

DDR0_RAS#/DDR 0_CAB[3]/DDR0_MA[1 6]

DDR0_BA[0]/D DR0_CAB[4]/DDR0_ BA[0]

DDR0_MA[2]/DDR 0_CAB[5]/DDR0_MA[2 ]

DDR0_BA[1]/D DR0_CAB[6]/DDR0_ BA[1]

DDR0_MA[10]/ DDR0_CAB[7]/DDR0_ MA[10]

DDR0_MA[1]/DDR 0_CAB[8]/DDR0_MA[1 ] DDR0_MA[0]/DDR 0_CAB[9]/DDR0_MA[0 ]

DDR1_DQSN[0 ]/DDR0_DQSN[2] DDR1_DQSP[0 ]/DDR0_DQSP[2] DDR1_DQSN[1 ]/DDR0_DQSN[3] DDR1_DQSP[1 ]/DDR0_DQSP[3] DDR0_DQSN[2 ]/DDR0_DQSN[4] DDR0_DQSP[2 ]/DDR0_DQSP[4] DDR0_DQSN[3 ]/DDR0_DQSN[5] DDR0_DQSP[3 ]/DDR0_DQSP[5] DDR1_DQSN[2 ]/DDR0_DQSN[6] DDR1_DQSP[2 ]/DDR0_DQSP[6] DDR1_DQSN[3 ]/DDR0_DQSN[7] DDR1_DQSP[3 ]/DDR0_DQSP[7]

DDR CH - A

2 OF 20

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0 ] DDR0_CS#[1 ]

DDR0_ODT[0]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0 ] DDR0_DQSP[0 ] DDR0_DQSN[1 ] DDR0_DQSP[1 ]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

BC62 BC60 BA60 BA62

BB57 BC58 BE57 AW61

AW63 BJ57 BN61

AW59 AW55 BF62 AV56 AW57 AV58 BA56 BD59 BD61 BG61

BK59 BL62 BJ61 AV60 BN62 BB61 BL61 BM59 BN58 AV62

BB63 BL57

AJ61 AJ63 AP62 AP60 AP56 AP58 AJ57 AJ55 BD54 BF54 BF50 BD50 BM54 BK54 BK50 BM50

BG57 BM56

AR53 AN53 AW53

BN47

M_A_CA_0_[0. .9]18

M_A_CA_1_[0. .9]18

M_B_CA_0_[0. .9]19

M_B_CA_1_[0. .9]19

DDR_VTT_ CNTL

M_A_CK_DDR0_DN 18 M_A_CK_DDR0_DP 18 M_A_CK_DDR1_DN 18 M_A_CK_DDR1_DP 18

M_A_CKE0 18 M_A_CKE1 18 M_A_CKE2 18 M_A_CKE3 18

M_A_CS0_N 18 M_A_CS1_N 18 M_A_ODT0 18

M_A_CA_0_0 18 M_A_CA_0_1 18 M_A_CA_0_2 18 M_A_CA_0_3 18 M_A_CA_0_4 18 M_A_CA_0_5 18 M_A_CA_0_6 18 M_A_CA_0_7 18 M_A_CA_0_8 18 M_A_CA_0_9 18

M_A_CA_1_0 18 M_A_CA_1_1 18 M_A_CA_1_2 18 M_A_CA_1_3 18 M_A_CA_1_4 18 M_A_CA_1_5 18 M_A_CA_1_6 18 M_A_CA_1_7 18 M_A_CA_1_8 18 M_A_CA_1_9 18

M_A_DQS_DN_0 18 M_A_DQS_DP_0 18 M_A_DQS_DN_1 18 M_A_DQS_DP_1 18 M_A_DQS_DN_2 18 M_A_DQS_DP_2 18 M_A_DQS_DN_3 18 M_A_DQS_DP_3 18 M_A_DQS_DN_4 18 M_A_DQS_DP_4 18 M_A_DQS_DN_5 18 M_A_DQS_DP_5 18 M_A_DQS_DN_6 18 M_A_DQS_DP_6 18 M_A_DQS_DN_7 18 M_A_DQS_DP_7 18

+V_DDR_VREF_C A 20 +V_DDR_0_DQ _VREF 20 +V_DDR_1_DQ _VREF 20

M_B_DQ_[0..6 3]19

Trace width/Spacing >= 20mils

M_B_DQ_0 M_B_DQ_1 M_B_DQ_2 M_B_DQ_3 M_B_DQ_4 M_B_DQ_5 M_B_DQ_6 M_B_DQ_7 M_B_DQ_8

M_B_DQ_9 M_B_DQ_10 M_B_DQ_11 M_B_DQ_12 M_B_DQ_13 M_B_DQ_14 M_B_DQ_15 M_B_DQ_16 M_B_DQ_17 M_B_DQ_18 M_B_DQ_19 M_B_DQ_20 M_B_DQ_21 M_B_DQ_22 M_B_DQ_23 M_B_DQ_24 M_B_DQ_25 M_B_DQ_26 M_B_DQ_27 M_B_DQ_28 M_B_DQ_29 M_B_DQ_30 M_B_DQ_31 M_B_DQ_32 M_B_DQ_33 M_B_DQ_34 M_B_DQ_35 M_B_DQ_36 M_B_DQ_37 M_B_DQ_38 M_B_DQ_39 M_B_DQ_40 M_B_DQ_41 M_B_DQ_42 M_B_DQ_43 M_B_DQ_44 M_B_DQ_45 M_B_DQ_46 M_B_DQ_47 M_B_DQ_48 M_B_DQ_49 M_B_DQ_50 M_B_DQ_51 M_B_DQ_52 M_B_DQ_53 M_B_DQ_54 M_B_DQ_55 M_B_DQ_56 M_B_DQ_57 M_B_DQ_58 M_B_DQ_59 M_B_DQ_60 M_B_DQ_61 M_B_DQ_62 M_B_DQ_63

UC1C

BC41

DDR0_DQ[3 2]/DDR1_DQ[0]

BC39

DDR0_DQ[3 3]/DDR1_DQ[1]

BG41

DDR0_DQ[3 4]/DDR1_DQ[2]

BE39

DDR0_DQ[3 5]/DDR1_DQ[3]

BF42

DDR0_DQ[3 6]/DDR1_DQ[4]

BD42

DDR0_DQ[3 7]/DDR1_DQ[5]

BG39

DDR0_DQ[3 8]/DDR1_DQ[6]

BE41

DDR0_DQ[3 9]/DDR1_DQ[7]

BC43

DDR0_DQ[4 0]/DDR1_DQ[8]

BD46

DDR0_DQ[4 1]/DDR1_DQ[9]

BG43

DDR0_DQ[4 2]/DDR1_DQ[10 ]

BG45

DDR0_DQ[4 3]/DDR1_DQ[11 ]

BC45

DDR0_DQ[4 4]/DDR1_DQ[12 ]

BE43

DDR0_DQ[4 5]/DDR1_DQ[13 ]

BE45

DDR0_DQ[4 6]/DDR1_DQ[14 ]

BF46

DDR0_DQ[4 7]/DDR1_DQ[15 ]

BM28

DDR1_DQ[3 2]/DDR1_DQ[16 ]

BN27

DDR1_DQ[3 3]/DDR1_DQ[17 ]

BK28

DDR1_DQ[3 4]/DDR1_DQ[18 ]

BL25

DDR1_DQ[3 5]/DDR1_DQ[19 ]

BN25

DDR1_DQ[3 6]/DDR1_DQ[20 ]

BL27

DDR1_DQ[3 7]/DDR1_DQ[21 ]

BJ25

DDR1_DQ[3 8]/DDR1_DQ[22 ]

BJ27

DDR1_DQ[3 9]/DDR1_DQ[23 ]

BM24

DDR1_DQ[4 0]/DDR1_DQ[24 ]

BK24

DDR1_DQ[4 1]/DDR1_DQ[25 ]

BN21

DDR1_DQ[4 2]/DDR1_DQ[26 ]

BJ23

DDR1_DQ[4 3]/DDR1_DQ[27 ]

BL23

DDR1_DQ[4 4]/DDR1_DQ[28 ]

BN23

DDR1_DQ[4 5]/DDR1_DQ[29 ]

BJ21

DDR1_DQ[4 6]/DDR1_DQ[30 ]

BL21

DDR1_DQ[4 7]/DDR1_DQ[31 ]

BN45

DDR0_DQ[4 8]/DDR1_DQ[32 ]

BM46

DDR0_DQ[4 9]/DDR1_DQ[33 ]

BL43

DDR0_DQ[5 0]/DDR1_DQ[34 ]

BK46

DDR0_DQ[5 1]/DDR1_DQ[35 ]

BN43

DDR0_DQ[5 2]/DDR1_DQ[36 ]

BL45

DDR0_DQ[5 3]/DDR1_DQ[37 ]

BJ45

DDR0_DQ[5 4]/DDR1_DQ[38 ]

BJ43

DDR0_DQ[5 5]/DDR1_DQ[39 ]

BM42

DDR0_DQ[5 6]/DDR1_DQ[40 ]

BN41

DDR0_DQ[5 7]/DDR1_DQ[41 ]

BJ41

DDR0_DQ[5 8]/DDR1_DQ[42 ]

BN39

DDR0_DQ[5 9]/DDR1_DQ[43 ]

BK42

DDR0_DQ[6 0]/DDR1_DQ[44 ]

BL41

DDR0_DQ[6 1]/DDR1_DQ[45 ]

BL39

DDR0_DQ[6 2]/DDR1_DQ[46 ]

BJ39

DDR0_DQ[6 3]/DDR1_DQ[47 ]

BF28

DDR1_DQ[4 8]

BD28

DDR1_DQ[4 9]

BG25

DDR1_DQ[5 0]

BC27

DDR1_DQ[5 1]

BG27

DDR1_DQ[5 2]

BE27

DDR1_DQ[5 3]

BE25

DDR1_DQ[5 4]

BC25

DDR1_DQ[5 5]

BF24

DDR1_DQ[5 6]

BD24

DDR1_DQ[5 7]

BG21

DDR1_DQ[5 8]

BC23

DDR1_DQ[5 9]

BE23

DDR1_DQ[6 0]

BG23

DDR1_DQ[6 1]

BC21

DDR1_DQ[6 2]

BE21

DDR1_DQ[6 3]

SKYLAKE_ULX_EDS/BGA

@

SKYLAKE_ULX

DDR1_MA[5]/DDR 1_CAA[0]/DDR1_MA[5 ] DDR1_MA[9]/DDR 1_CAA[1]/DDR1_MA[9 ] DDR1_MA[6]/DDR 1_CAA[2]/DDR1_MA[6 ] DDR1_MA[8]/DDR 1_CAA[3]/DDR1_MA[8 ] DDR1_MA[7]/DDR 1_CAA[4]/DDR1_MA[7 ]

DDR1_BA[2]/D DR1_CAA[5]/DDR1_ BG[0] DDR1_MA[12]/ DDR1_CAA[6]/DDR1_ MA[12] DDR1_MA[11]/ DDR1_CAA[7]/DDR1_ MA[11]

DDR1_MA[15]/ DDR1_CAA[8]/DDR1_ ACT# DDR1_MA[14]/ DDR1_CAA[9]/DDR1_ BG[1]

DDR1_MA[13]/ DDR1_CAB[0]/DDR1_ MA[13]

DDR1_CAS#/DDR 1_CAB[1]/DDR1_MA[1 5]

DDR1_WE#/DDR 1_CAB[2]/DDR1_MA[1 4]

DDR1_RAS#/DDR 1_CAB[3]/DDR1_MA[1 6]

DDR1_BA[0]/D DR1_CAB[4]/DDR1_ BA[4]

DDR1_MA[2]/DDR 1_CAB[5]/DDR1_MA[2 ]

DDR1_BA[1]/D DR1_CAB[6]/DDR1_ BA[1]

DDR1_MA[10]/ DDR1_CAB[7]/DDR1_ MA[10]

DDR1_MA[1]/DDR 1_CAB[8]/DDR1_MA[1 ]

DDR1_MA[0]/DDR 1_CAB[9]/DDR1_MA[0 ]

DDR0_DQSN[4 ]/DDR1_DQSN[0] DDR0_DQSP[4 ]/DDR1_DQSP[0] DDR0_DQSN[5 ]/DDR1_DQSN[1] DDR0_DQSP[5 ]/DDR1_DQSP[1] DDR1_DQSN[4 ]/DDR1_DQSN[2] DDR1_DQSP[4 ]/DDR1_DQSP[2] DDR1_DQSN[5 ]/DDR1_DQSN[3] DDR1_DQSP[5 ]/DDR1_DQSP[3] DDR0_DQSN[6 ]/DDR1_DQSN[4] DDR0_DQSP[6 ]/DDR1_DQSP[4] DDR0_DQSN[7 ]/DDR1_DQSN[5] DDR0_DQSP[7 ]/DDR1_DQSP[5]

DDR CH - B

3 OF 20

DDR1_CKN[0] DDR1_CKP[0] DDR1_CKN[1] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0 ] DDR1_CS#[1 ] DDR1_ODT[0]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6 ] DDR1_DQSP[6 ] DDR1_DQSN[7 ] DDR1_DQSP[7 ]

DDR1_ALERT#

DDR1_PAR

DRAM_RESET#

DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

BK36 BM36 BD32 BF32

BN33 BK32 BG33 BH30

BM30 BJ33 BC35

BK30 BN31 BM32 BL37 BG31 BN37 BJ37 BJ35 BM34 BN35

BG37 BE37 BC37 BF34 BC33 BF30 BD36 BG35 BC31 BF36

BJ31 BK34

BD40 BF40 BD44 BF44 BK26 BM26 BM22 BK22 BK44 BM44 BM40 BK40 BD26 BF26 BF22 BD22

BD34 BD30

TP_DDR_DRAM_RST _N

BP20

DDR_RCOMP_0

BF64

DDR_RCOMP_1

BJ64

DDR_RCOMP_2

BC64

M_B_CK_DDR0_DN 19 M_B_CK_DDR0_DP 19 M_B_CK_DDR1_DN 19 M_B_CK_DDR1_DP 19

M_B_CKE0 19 M_B_CKE1 19 M_B_CKE2 19 M_B_CKE3 19

M_B_CS0_N 19 M_B_CS1_N 19 M_B_ODT0 19

M_B_CA_0_0 19 M_B_CA_0_1 19 M_B_CA_0_2 19 M_B_CA_0_3 19 M_B_CA_0_4 19 M_B_CA_0_5 19 M_B_CA_0_6 19 M_B_CA_0_7 19 M_B_CA_0_8 19 M_B_CA_0_9 19

M_B_CA_1_0 19 M_B_CA_1_1 19 M_B_CA_1_2 19 M_B_CA_1_3 19 M_B_CA_1_4 19 M_B_CA_1_5 19 M_B_CA_1_6 19 M_B_CA_1_7 19 M_B_CA_1_8 19 M_B_CA_1_9 19

M_B_DQS_DN_0 19 M_B_DQS_DP_0 19 M_B_DQS_DN_1 19 M_B_DQS_DP_1 19 M_B_DQS_DN_2 19 M_B_DQS_DP_2 19 M_B_DQS_DN_3 19 M_B_DQS_DP_3 19 M_B_DQS_DN_4 19 M_B_DQS_DP_4 19 M_B_DQS_DN_5 19 M_B_DQS_DP_5 19 M_B_DQS_DN_6 19 M_B_DQS_DP_6 19 M_B_DQS_DN_7 19 M_B_DQS_DP_7 19

TC29

RC46 200_040 2_1%

1 2 1 2

RC45 80.6_04 02_1%

1 2

RC47 162_040 2_1%

@

12

NC1VCC

A

GND

CC910.1U_0201_ 10V6K

Y

UC2

DDR_VTT_ CNTL

A A

5

4

2

3

74AUP1G07GW_ TSSOP5

+3VS+1.2V_DDR

12

5

4

RC14 100K_020 1_5%

SM_PG_CTRL 56

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

2041/09/08 2015/12/31

Compal Secre t Data

Deciphered Date

2

Compal Electronics, Inc.

Title

P06-SKL Y(2/13) DDRIII

Size Document Number Rev

C

LA-C791P

Date: Sheet of

Friday, Nove mber 27, 201 5

Date: Sheet of

Friday, Nove mber 27, 201 5

Date: Sheet of

Friday, Nove mber 27, 201 5

1

66

6

1.0

5

PCH_SPI_CLK30

D D

C C

SPI_PCH_CS0# SPI_SO_ROM1 SPI_IO3_RO M1 SPI_IO2_ROM1 SPI_CLK_ROM1

PCH_SPI_CLK PCH_SPI_CLK_R

CH7

0.1U_0201_ 10V6K

@EMI@

TC9 TC8 TC11 TC10 TC12 RC32 15_0402 _5%@ TC13

SPI_CLK_ROM1

SPI_SO_ROM1 SPI_IO2_ROM1 SPI_SI_ROM1 SPI_IO3_ROM1 SPI_PCH_IO3

+3.3V_SPI

RH93 33_0201 _1%

RH113 33_0201 _1% RH112 33_0201 _1% RH94 33_0201 _1% RH92 33_0201 _1%

SPI ROM FOR ME ( 16MByte ) ROM is Quad SPI

U39

1

CS#

2

DO

3

WP#

4

GND

W25Q128 FVPIQ_WSON8

RH56 1K_0201_5%@

1 2

RH48 1K_0201_5%@

RH49 1K_0201_5%@

1 2

Intel's issue, For ES only Refer MOW 2014WW36

1 2

RC16 0_0402_ 5%@

PCH_SPI_SO30

PCH_SPI_SI5,30

PCH_SPI_IO25

1

PCH_SPI_CS2#30

2

1 2

RC27 15_0402 _5%@

1 2

RC28 15_0402 _5%@ RC30 15_0402 _5%@

1 2 1 2

RC25 15_0402 _5%@

1 2 1 2

RC31 15_0402 _5%@

CL_CLK26 CL_DATA26 CL_RST#26

SIO_RCIN#45

IRQ_SERIRQ45

Closed to ROM

1 2

1 2 1 2 1 2 1 2

8

VCC

HOLD#_RESET#

7

6

CLK

5

DI

SPI_SI_ROM1

SPI_PCH_IO2

SPI_PCH_IO3

PCH_SPI_SO PCH_SPI_SI PCH_SPI_IO2 PCH_SPI_IO3 PCH_SPI_CS0# PCH_SPI_CS1#

PCH_SPI1_CLK PCH_SPI1_MISO PCH_SPI1_MOSI PCH_SPI1_IO2 PCH_SPI1_IO3 PCH_SPI1_CS#

SIO_RCIN#

IRQ_SERIRQ

SPI_PCH_CLK

SPI_PCH_SO SPI_PCH_IO2 SPI_PCH_SI

+3.3V_SPI

AU10 AU12

AT3 AV11 AV13

AU4

AU6

AU8

P9 N8

P3

W12

V7

N6

F12 D12 B12

BL10

BN8

1

CH13

0.1U_0201_ 10V6K

2

UC1E

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

GPP_D1/SPI1_ CLK GPP_D2/SPI1_ MISO GPP_D3/SPI1_ MOSI GPP_D21/SPI1 _IO2 GPP_D22/SPI1 _IO3 GPP_D0/SPI1_ CS#

CL_CLK CL_DATA CL_RST#

GPP_A0/RCIN# GPP_A6/SERIRQ

SKYLAKE_ULX_EDS/BGA

@

4

SKYLAKE_ULX

SPI - FLASH SMBUS, SMLINK

SPI - TOUCH

LPC

C LINK

5 OF 20

GPP_B23/SML1AL ERT#/PCHHOT#

GPP_A1/LAD0/ ESPI_IO0 GPP_A2/LAD1/ ESPI_IO1 GPP_A3/LAD2/ ESPI_IO2 GPP_A4/LAD3/ ESPI_IO3

GPP_A5/LFRAME#/ESPI_C S#

GPP_A14/SUS_STAT#/ESPI_ RESET#

GPP_A9/CLKOUT_ LPC0/ESPI_CLK

GPP_A10/CLKO UT_LPC1

from CPU to SPI R OM

1 2

RC8 0_0402_5%@

1 2

PCH_SPI_SO SPI_PCH_SO

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_IO2

+3.3V_SPI

RC5 0_0402_5%@

RC7 0_0402_5%@

RC6 0_0402_5%@

RC3 0_0402_5%@

RC4 0_0402_5%@

RC1 0_0402_5%@

RC2 0_0402_5%@

1 2

+3V_PRIM

1 2

SPI_PCH_CS1#PCH_SPI_CS1#

SPI_PCH_SIPCH_SPI_SI

SPI_PCH_CLK

SPI_PCH_CS0#

SPI_PCH_IO2

SPI_PCH_IO3PCH_SPI_IO3

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CL K

GPP_C4/SML0DATA

GPP_C5/SML0ALER T#

GPP_C6/SML1CL K

GPP_C7/SML1DATA

GPP_A8/CLKRUN#

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

21 22

ACES_50696- 0200M-P01

JSPI1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

GND_1 GND_2

CONN@

AC12 W6 W8

W4 AC10 AA6

AA4 W10 BB6

BK11 BJ8 BG10 BP5 BP7 BJ6

BJ10 BF5 BH11

3

SMBCLK SMBDATA SMBALERT#

SML0CLK SML0DATA SML0ALERT#

SML1_SMBCLK SML1_SMBDAT

SML1ALERT#

CLKOUT_LPC0 CLKOUT_LPC1

CLKRUN#

SMBCLK 5 SMBDATA 5

SML0CLK 36

SML0DATA 36

SML1_SMBCLK 45 SML1_SMBDAT 45

LPC_AD0 21,45 LPC_AD1 21,45 LPC_AD2 21,45 LPC_AD3 21,45 LPC_FRAME# 2 1,45

TC34

1 2

RH69 22_0201 _5%

1 2

RH27 22_0201 _5%

0.1U_0201_ 10V6K

@EMI@

2

1 2

Connect XDP

Connect NFC

Connect EC

CLK_PCI_MEC 45 CLK_LPC_DEBUG 21

CLKRUN# 45

1

CH6

CH12

0.1U_0201_ 10V6K

2

@EMI@

CLKRUN# SIO_RCIN# IRQ_SERIRQ

SML1ALERT#

SML1_SMBCLK SML1_SMBDAT

SML0CLK SML0DATA

SMBCLK SMBDATA

SML1ALERT#

PDG_SUS_STAT#, This signal is asserted by the PCH to indicate that the system will be entering a low power state soon. This can be monitored by devices with memory that need to switch from normal refresh to sus pend refresh mode. It can also be used by other peripherals as an indication that they s hould isolate their outputs that may be going to powered-off planes.

RH63 8.2K_020 1_5% RH61 10K_0201 _5%

1 2 1 2

RH65 8.2K_020 1_5%

1 2

RH80 150K_020 1_5%@

1 2

RH123 1K_0201_ 5% RH117 1K_0201_ 5%

1 2

RH54 499_040 2_1%@

1 2

RH53 499_040 2_1%@

RH95 1K_0201_ 5%

1 2 1 2

RH97 1K_0201_ 5%

1 2

RH83 150K_020 1_5%

+3VS

+3V_PRIM

1

Functional Strap Definitions

SMBALERT# / GPP_C2 (Internal Pull Down) :

TLS Confi-dentiality

0 = Disable Intel ME Crypto Transport Layer Security (TLS) cipher suite (no confidentiality).

1 = Enable Intel ME Crypto Transport Layer Security (TLS) cipher suite (with confidentiality). Must be pulled up to support Intel AMT with TLS and Intel SBA (Small Business Advantag e) with TLS.

+3V_PRIM

12

RH982 .2K_0201_5 %

+3V_PRIM

RH12810K_ 0201_5% @

SMBALERT#

SML0ALERT# / GPP_C5 (Internal Pull Down) :

0 = LPC Is selected for EC.

1 = eSPI Is selected for EC.

SML0ALERT#

B B

SPI_CLK_ROM2

SPI_SO_ROM2 SPI_IO2_ROM2 SPI_SI_ROM2 SPI_IO3_ROM2

SPI_PCH_CS1#

A A

11-1020

Closed to ROM

1 2

RH52 33_0201 _1%@

RH57 33_0201 _1%@

1 2 1 2

RH55 33_0201 _1%@

1 2

RH51 33_0201 _1%@

1 2

RH50 33_0201 _1%@

SPI ROM FOR ME ( 8MByte ) ROM is Quad SPI

U16

@

1

CS#

2

DO

3

WP#

4

GND

W25Q64F VZPIQ_WSON8

HOLD#_RESET#

5

VCC

CLK

DI

8 7 6 5

SPI_IO3_ROM2SPI_SO_ROM2 SPI_CLK_ROM2SPI_IO2_ROM2 SPI_SI_ROM2

SPI_PCH_CLK

SPI_PCH_SO SPI_PCH_IO2 SPI_PCH_SI SPI_PCH_IO3

+3.3V_SPI

1

@

CH8

0.1U_0201_ 10V6K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

2041/09/08 2015/12/31

Compal Secre t Data

Deciphered Date

2

Compal Electronics, Inc.

Title

P07-SKL Y(3/13) SPI,SMBus,LPC

Size Document Number Rev

C

LA-C791P

Date: Sheet of

Date: Sheet

1

of

7 66Friday, Nove mber 27, 201 5

1.0

5

4

3

2

1

AUDIO

<+3V_1.8V_PGPPD>

HDA_BIT_CLK_L23 HDA_RST#_L23 HDA_SYNC_L23 HDA_SDOUT_L2 3

SKYLAKE_ULX

7 OF 20

HDA for AUDIO

CSI-2

eMMC

9 OF 20

SDIO/SDXC

GPP_A17/SD_PWR _EN#/ISH_GP7

1

CH4

2

@EMI@

GPP_D4/FLASHTRIG

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

GPP_A16/SD_1 P8_SEL

1

CH3

2

0.1U_020 1_10V6K

@EMI@

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

EMMC_RCOMP

GPP_G0/SD_C MD GPP_G1/SD_D ATA0 GPP_G2/SD_D ATA1 GPP_G3/SD_D ATA2 GPP_G4/SD_D ATA3

GPP_G5/SD_C D# GPP_G6/SD_C LK

GPP_G7/SD_W P

SD_RCOMP

GPP_F23

1

CH1

2

0.1U_020 1_10V6K

@EMI@

H31 F31 D31 B31 C34 A34 D39 B39

CSI2_COMP

A11

PCH_STROBE_OUT

N4

AN12 AP9 AN10 AJ10 AM9 AL12 AJ12 AN8

AL10 AL8 AM11

BC1

AH9 AH11

SSD_RST#

AG12 AF9

CONTACTLESS_DET #

AF11

WWAN_OFF#

AG8 AG10 AE12

BL4 BN4

SDIO_RCOMP

BF1

GPP_F23

AJ8

RH5 33_0 201_1%

1 2 1 2

RH4 33_0 201_1%@

1 2

RH3 33_0 201_1%

1 2

RH8 33_0 201_1%

1

CH2

2

0.1U_020 1_10V6K

@EMI@

RC65 100_ 0201_1%

MEM_CONFIG0 MEM_CONFIG1 MEM_CONFIG2 MEM_CONFIG3

GNSS_OFF# PCH_WWAN_WAKE#

USH_DET# GNSS_IRQ

EMMC_RCOMP

RC41 200_0402_ 1%

TC79

WIN7_DEBUG# 44

SSD_PWR_EN 38

CONTACTLESS_DET # 37

WWAN_OFF# 27

TC80 TC81

SD_PWR_EN 38

NGFF_WWAN_PWREN 38

12

RC39 200_040 2_1%

TC1

HDA_BIT_CLK HDA_RST# HDA_SYNC HDA_SDOUT

SKYCAM_CSI_CLK_D# 29 SKYCAM_CSI_CLK_D 29

SKYCAM_USER_CSI_CLK_D# 29 SKYCAM_USER_CSI_CLK_D 29

12

PCH_STROBE_OUT 31

GNSS_OFF# 27

PCH_WWAN_WAKE# 27

USH_DET# 37

GNSS_IRQ 27 WWAN_PWR_OFF# 27

12

CONTACTLESS_DET #

WWAN_OFF# SSD_RST#

ME_FWP#45

PCH_STROBE_OUT

GNSS_IRQ

USH_DET#

GNSS_OFF#

PCH_WWAN_WAKE#

RH89 100K_020 1_5%

1 2

RH41 10K_0201 _5%

1 2

RH42 10K_0201 _5%

From EC, for enable ME code programing

3

Q7B DMN2400UV-7_SOT- 563-6

5

4

1 2

RH116 10K_0201 _5%@

1 2

RH38 10K_0201 _5%@

RH39 100K_020 1_5%

1 2

RH88 10K_0201 _5%

1 2

RH87 100K_020 1_5%

+3V_PRIM

+3VS

Strap pin

+3V_PRIM

+1.8V_PRIM

+3V_PRIM

R28

1M_0201_ 5%

6 1

DMN2400UV-7_SOT- 563-6 Q7A

+5VALW

1 2

2

HDA_SDO

ME debug mode , this signal has a weak internal PD L=>security measures defined in the Flash Descriptor will be in effect (default) H=>Flash Descriptor Security will be overridden

RH11

HDA_SDOUT

1 2

1K_0201_ 5%

Low = Disabled

*

High = Enabled

UC1G

BJ19

HDA_SYNC/I2S0_ SFRM

BK18

HDA_BLK/I2S0_ SCLK

BK16

HDA_SDO/I2S0 _TXD

BL15

HDA_SDI0/I2S0 _RXD

BL17

HDA_SDI1/I2S1 _RXD

BL19

HDA_RST#/I2S1_ SCLK

V5

GPP_D23/I2 S_MCLK

BL12

I2S1_SFRM

BK14

I2S1_TXD

AT13

GPP_F1/I2S2_ SFRM

AT11

GPP_F0/I2S2_ SCLK

AP11

GPP_F2/I2S2_ TXD

AT5

GPP_F3/I2S2_ RXD

V3

GPP_D19/DMIC_ CLK0

V11

GPP_D20/DMIC_ DATA0

U12

GPP_D17/DMIC_ CLK1

U8

GPP_D18/DMIC_ DATA1

AV3

GPP_B14/SPKR

SKYLAKE_ULX_EDS/BGA

@

TC41 TC42 TC43 TC44

TC45 TC5

TC4 TC6

HDA_SYNC HDA_BIT_CLK HDA_SDOUT

HDA_RST#

GPP_F1 GPP_F0 GPP_F2 GPP_F3

SPKR

SPKR23

internal pull down

PDG_internal pull down, series-resistors place as closed as codec

D D

internal pull down

HDA_SDI023

Functional Strap Definitions

SPKR / GPP_B14 (Internal Pull Down) :

TOP Swap Override

0 = Disable TOP Swap mode.

1 = Enable TOP Swap Mode.

C C

+3V_PRIM

1 2

RC43 1K_0201_ 5%@

B B

SPKR

UC1I

SKYCAM_CSI0_D#29 SKYCAM_CSI0_D2 9 SKYCAM_CSI1_D#29 SKYCAM_CSI1_D2 9 SKYCAM_CSI2_D#29 SKYCAM_CSI2_D2 9 SKYCAM_CSI3_D#29 SKYCAM_CSI3_D2 9

SKYCAM_USER_CSI0_D#29 SKYCAM_USER_CSI0_D29 SKYCAM_USER_CSI1_D#29 SKYCAM_USER_CSI1_D29

H29

CSI2_DN0

F29

CSI2_DP0

F33

CSI2_DN1

H33

CSI2_DP1

J30

CSI2_DN2

G30

CSI2_DP2

J32

CSI2_DN3

G32

CSI2_DP3

D29

CSI2_DN4

B29

CSI2_DP4

C32

CSI2_DN5

A32

CSI2_DP5

C30

CSI2_DN6

A30

CSI2_DP6

D33

CSI2_DN7

B33

CSI2_DP7

D35

CSI2_DN8

B35

CSI2_DP8

C36

CSI2_DN9

A36

CSI2_DP9

D37

CSI2_DN10

B37

CSI2_DP10

C38

CSI2_DN11

A38

CSI2_DP11

SKYLAKE_ULX_EDS/BGA

@

+1.8V_PRIM

A A

GPIO Pin

GPP_F13

GPP_F14

GPP_F15

GPIO Pin

GPP_F16 0 1

5

Pin Name

MEM_CONFIG0

MEM_CONFIG1

MEM_CONFIG2

Pin Name

MEM_CONFIG3

DDR Memory Configuratino Type Strap pin

Micron 4G SA00006ZS1L

0

MEM Speed 1600

12

Micron 8G SA000083Z0L

1

0 1

0

MEM Speed 1866

RH31 10K_0201 _5%@

RH29 10K_0201 _5%@

RH34 10K_0201 _5%@

RH36 10K_0201 _5%@

MEM_CONFIG0

MEM_CONFIG1

MEM_CONFIG2

MEM_CONFIG3

Hynix 4G SA00008GC0L

0 1

0

4

Hynix 8G SA00008J70L

1

0 11

RH32 10K_0201 _5%@

RH30 10K_0201 _5%@

RH35 10K_0201 _5%@

RH33 10K_0201 _5%@

Samsung 4G TBD

01

0

12

Samsung 8G TBD

Elpida 8G

Elpida 4G

TBD

0 1

1 1

0

1 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

2041/09/08 2015/12/31

Compal Secre t Data

Deciphered Date

2

Compal Electronics, Inc.

Title

P08-SKL Y(4/13) HDA,EMMC,SD,CSI

Size Document Number Rev

C

LA-C791P

Date: Sheet of

Friday, Nove mber 27, 201 5

Date: Sheet of

Friday, Nove mber 27, 201 5

Date: Sheet of

Friday, Nove mber 27, 201 5

1

66

8

1.0

5

4

3

SUSCLK

2

12

MC1

10P_0402 _50V8J@EMI@

1

Reserve for RF please close to UH1

UC1J

H35

CLKOUT_PCIE_N1

F35

CLKOUT_PCIE_P1

1

2

PCH_PLTRST# SYS_RESET#

H_CPUPWRGD_R H_VCCST_PWRGD

H_SYS_PWROK PCH_PWROK PCH_DPWROK_RPCH_DPWROK

SUSWARN#_R SUSACK#_R

WAKE# LAN_WAKE#_R

PCH_GPD11

AV9

GPP_B6/SRCCLKREQ 1#

J36

CLKOUT_PCIE_N2

G36

CLKOUT_PCIE_P2

BD10

GPP_B7/SRCCLKREQ 2#

J38

CLKOUT_PCIE_N3

G38

CLKOUT_PCIE_P3

AV5

GPP_B8/SRCCLKREQ 3#

H37

CLKOUT_PCIE_N4

F37

CLKOUT_PCIE_P4

AV7

GPP_B9/SRCCLKREQ 4#

H39

CLKOUT_PCIE_N5

F39

CLKOUT_PCIE_P5

BC5

GPP_B10/SRCCL KREQ5#

BB10

GPP_B5/SRCCLKREQ 0#

SKYLAKE_ULX_EDS/BGA

@

BB8

BJ12

A62 B61

BP14 BN15

BL6 BF9

BP9 BE15 BC15 BB16

T14 T34 T12 T29 T27 T25 T10 T19 T21 T18 T20 T13 T11 T9

H2

J1

D D

Cadreader

SSD

WLAN

+3V_PRIM

C C

+3VALW_DSW

B B

1 2

RH70 10K_0201 _5%@

1 2

RH106 10K_0201 _5%

RH105 10K_0201 _5%

1 2

RH64 100K_020 1_5%

1 2

RH15 10K_0201 _5%

1 2

RH59 10K_0201 _5% RH58 10K_0201 _5%

1 2 1 2

RH62 1K_0201_ 5%

1 2

RH17 1K_0201_ 5%

1 2

RH24 10K_0201 _5%

1 2

RH9 100K_ 0201_5%

C74 0.01U_040 2_16V7K

1 2

@

SYS_PWROK45

RUN_ON_EC12,34,38 ,39,45,56,5 7

SUSWARN#_R

SYS_RESET#

SYS_PWROK

PCH_PWROK

SN74AHC1G08DCKR_SC70 -5

VR_ON45,6 0

VCORE_PG60

SN74AHC1G08DCKR_SC70 -5

AC_PRESENT_R PCH_GPD11

BATLOW# PCIE_WAKE_O#

LAN_WAKE#_R

PCH_RSMRST#

PCH_DPWROK_R

+3VS

5

UH4

1

P

IN1

2

IN2

G

3

VR_ON

O

H_SYS_PWROK

4

1

IN1

2

IN2

+3VS

5

UH5

P

PCH_PWROK

4

O

G

3

TC82

CLK_PCIE2#47 CLK_PCIE247

CLK_REQ2#35,47 CLK_PCIE3#28 CLK_PCIE328

CLK_REQ3#28 CLK_PCIE4#26 CLK_PCIE426

CLK_REQ4#26

TC83

PM_SYS_RESET#5,21 PCH_RSMRST#5,45

TC55

PCH_DPWROK45

SUSWARN#45

SUSACK#45

PCIE_WAKE_O#45

LAN_WAKE#45

EN_CAM#38

PDG_DPWROK connect to VccDSW3_3 power rail monitoring circuit to support Deep Sx state.This signal can be tied to RSMRST# for platforms that do not support t he Deep Sx state.The DSW rails must b e stable for at least 10 ms before DPWROK is asserted to PCH .

PDG_SUSACK#, this signal is driven from t he platform EC to PCH to acknowledge that EC has received the SUSWARN# signals and it is preparing to go into DeepSx mode.for at least 10 ms before DPWROK is asserted to PCH.

RH66 10K_0201 _5%

+3VS

PCH_RSMRST# PCH_RSMRST#_R

SUSWARN#_R PCIE_WAKE_O#

1 2

RH44 10K_0201 _5%

1 2

RH43 10K_0201 _5%

PLT_RST#21,2 6,27,28,30, 31,37,45,4 7

12

RH67 100K_020 1_5%

RH111 0_0402_5%@ RH21 0_0402_5%@

RH107 10K_0201_5 %@

RH16 0_0402_5%@

RH77 0_0402_5%@ RH79 0_0402_5%@ RH78 0_0402_5%@ RH74 0_0402_5%@ RH18 0_0402_5%@

1 2

RH19 0_0402_ 5%@

1 2 1 2

1 2

1 2 1 2 1 2 1 2 1 2

4

RH82 0_0201_ 5%@

+3V_PRIM

O

PCH_DPWROK_RPCH_RSMRST#_R

1 2

5

P

IN1

IN2

G

3

UH3 SN74AHC1G08DCKR_SC70 -5

SKYLAKE_ULX

CLOCK SIGNALS

10 OF 2 0

+3V_PRIM

RH81

@

47K_0201 _5%

1 2

PCH_PLTRST#

@

RH73 10K_0201 _5%

1 2

UC1K

GPP_B13/PLTRST# SYS_RESET# RSMRST#

PROCPWRGD VCCST_PWRGD

SYS_PWROK PCH_PWROK DSW_PWROK

GPP_A13/SUSWARN# /SUSPWRDNACK GPP_A15/SUSACK#

WAKE# GPD2/LAN_WAKE# GPD11/LANPHYPC GPD7/RSVD

SKYLAKE_ULX_EDS/BGA

@

SYSTEM POWER MANAGEMENT

PLT_RST#

PM_SYS_RESET#

PCH_RSMRST#

H_VCCST_PWRGD

SYS_PWROK PCH_PWROK

PCH_DPWROK

SUSWARN#

SUSACK#

PCIE_WAKE_O#

RTC_RST#

PCH_SRTCRST#

SIO_PWRBTN# AC_PRESENT

SKYLAKE_ULX

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

11 OF 2 0

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

+RTCVCC

1U_0402_6. 3V6K

1 2

RH25 20K_0201 _5%

1 2

RH23 20K_0201 _5%

1U_0402_6. 3V6K

GPP_B11/EXT_PWR_ GATE#

J34 G34

BA15

XTAL24_IN

M1

XTAL24_OUT

L2

XCLK_BIASREF

P1

PCH_RTCX1

BN19

PCH_RTCX2

BP18

PCH_SRTCRST#

BH18

RTC_RST#

BN12

CH11

CH5

GPP_B12/SLP_ S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5 #

SLP_SUS# SLP_LAN#

GPD9/SLP_WL AN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B2/VRALERT#

RH26 0_0402_ 5%@

RH103 2.7K_020 1_1%

12

@

1

CLRP2 10K_0201 _5%

2

RTC_RST#

PCH_SRTCRST#

1

PDG_An RC delay circuit with a time delay in the range of 18–25 ms should be prov ided. The circuit

2

should be connected to VCCRTC.

BC9 AY14 BF16 BH14

BN10 BP11 BH16 BE17

BF14 BD14 BD16

BF7 BG19

BC7 BD6

SIO_SLP_S5# SIO_SLP_S4# SIO_SLP_S3# SIO_SLP_A# SIO_SLP_WLAN#

+3VALW_DSW

CK_XDP# 5 CK_XDP 5

1 2

RTC_RST# 21 ,45

SLP_S0# SIO_SLP_S3# SIO_SLP_S4# SIO_SLP_S5#

SIO_SLP_SUS#_L

SIO_SLP_WLAN# SIO_SLP_A#

PBTN_OUT#_R AC_PRESENT_R

BATLOW#

PME# SM_INTRUDER#

RH71 0_0402_ 5%@

RH68 0_0402_ 5%@

RH22 0_0201_ 5%@ RH14 0_0201_ 5%@

1 2

RH20 2.2K_020 1_5%

1 2

1 2 1 2

TC37

T22

T17 T16 T8 T5 T15

SUSCLK

+VCCCLK5

power on reset

EXT_PWR_GATE# 39

PBTN_OUT#_R

SUSCLK 26,27,28

XTAL24_IN

XTAL24_OUT

32.768KHZ_12. 5PF_9H032000 42

PDG_SLP_A#, This signal is used to control power to devices on the platform in conjunction with the IntelR ME sub-system. This s ignal will be asserted in M-off state. If M3 is not suppor ted then SLP_A# will have the same timings as SLP_S3#.

1 2

RH104 1M_0402_ 1%

YH2

24MHZ_12PF_7V24 000020

123

12

YH1

12

15P_0402 _50V8J

+RTCVCC

4

1

CH15 15P_0402 _50V8J

2

CH9 15P_0402_50 V8J

ESR must <50

CH10

far away hot spot

SIO_SLP_S0# 21,30,39 ,45,57,58 SIO_SLP_S3# 21,45 SIO_SLP_S4# 21,45 SIO_SLP_S5# 21

SIO_SLP_SUS# 45

SIO_SLP_WLAN# 38,45 SIO_SLP_A# 2 1,45

SIO_PWRBTN# 5,21,45 AC_PRESENT 45

12

RH71M_0402_ 5%

1

CH14 15P_0402 _50V8J

2

PCH_RTCX1

12

RH60 10M_0402 _5%

PCH_RTCX2

PDG_SLP_SUS#, a low on this signal indicates that PCH is in Deep Sx state and that EC/platform logic does not need to keep the Primary Rails ON.

PDG_ internal pull-up resistor, nterna 16 ms de-bounce on the input.

5

4

+3V_PRIM

+1.0V_VCCST

12

1K_0201_ 5% RH108

RC72

1 2

60.4_04 02_1%

4

H_VCCST_PWRGD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

2041/09/08 2015/12/31

Compal Secre t Data

Deciphered Date

2

Compal Electronics, Inc.

Title

P09-SKL Y(5/13) PM,CLK,GPIO

Size Document Number Rev

C

LA-C791P

Date: Sheet of

1

9 66Friday, Nove mber 27, 201 5

1.0

A A

U45

VR_ON

5

R412

@

1 2

0_0402_ 5%

NC1VCC

2

A

3

GND

74AUP1G07GW_ TSSOP5

Y

5

4

3

2

1

1.8V

GPP_B18

SKYLAKE_ULX

6 OF 20

ISHLPSS

GPP_D5/ISH_I 2C0_SDA GPP_D6/ISH_I 2C0_SCL

GPP_D7/ISH_I 2C1_SDA GPP_D8/ISH_I 2C1_SCL

GPP_F10/I2C5 _SDA/ISH_I2C2_SDA

1.8V

GPP_F11/I2C5 _SCL/ISH_I2C2_ SCL

GPP_D13/ISH_ UART0_RXD/SML0BDATA

GPP_D14/ISH_ UART0_TXD/SML0BCLK

GPP_D15/ISH_ UART0_RTS#

GPP_D16/ISH_ UART0_CTS#/SML0BALERT#

GPP_C12/UART1_ RXD/ISH_UART1_RXD

GPP_C13/UART1_ TXD/ISH_UART1_TXD GPP_C14/UART1_ RTS#/ISH_UART1_RTS# GPP_C15/UART1_ CTS#/ISH_UART1_CTS#

I2C0_SDA

I2C0_SCL

GPP_A18/ISH_ GP0 GPP_A19/ISH_ GP1 GPP_A20/ISH_ GP2 GPP_A21/ISH_ GP3 GPP_A22/ISH_ GP4 GPP_A23/ISH_ GP5

GPP_A12/BM_BUSY#/I SH_GP6

+3VS_AUDIO

6 1

DMN2400UV-7_SOT- 563-6

Q17A

+3VS_AUDIO

3

DMN2400UV-7_SOT- 563-6

Q17B

GPP_D10 GPP_D11 GPP_D12

2

5

GPP_D9

4

P11 T7 T5 T11

P7 P5

T9 T3

AM7 AT9

U10 U4 U6 V9

AC6 AC4 AB7 AB5

BF11 BD2 BJ1 BL3 BJ3 BD4 BJ4

GPP_D10

TS_INT#

ISH_I2C0_SDA ISH_I2C0_SCL

ISH_I2C1_SDA ISH_I2C1_SCL

GNSS_SDA GNSS_SCL

ISH_UART_RXD ISH_UART_TXD ISH_UART_RTS# ISH_UART_CTS#

DDR_CHA_EN

eDP_CAB_DET# DDR_CHB_EN

TS_ID1

TS_ID3

TS_ID2

I2C0_SDA_AUD 24

I2C0_SCL_AUD 24

TC7

TC47

NFC_EN 38 TS_INT# 22

ISH_I2C0_SDA 47 ISH_I2C0_SCL 47

GNSS_SDA 27 GNSS_SCL 27

ISH_UART_RXD 26 ISH_UART_TXD 26 ISH_UART_RTS# 26 ISH_UART_CTS# 26

DEBUG_UART_TX 4 5 eDP_CAB_DET# 22

ACCEL_INT1# 4 7 ACCEL_INT2# 4 7 TS_ID1 22

AUDIO_PWR_EN 38

TS_ID3 22

TC38

TS_ID2 22

Sensors

WWAN GNSS

GPP_D10 eDP_CAB_DET# TS_INT# HOST_SD_WP#

ISH_I2C0_SDA ISH_I2C0_SCL ISH_I2C1_SDA ISH_I2C1_SCL

DDR_CHA_EN DDR_CHB_EN

ISH_UART_RXD ISH_UART_TXD ISH_UART_RTS# ISH_UART_CTS# I2C0_SDA I2C0_SCL

GNSS_SDA GNSS_SCL

SIO_EXT_SCI# WWAN_RST#

TS_ID1 TS_ID2 TS_ID3

TS_I2C_SDA TS_I2C_SCL

1 2

RH124 10K_0201 _5%@ RH91 100K_020 1_5%

1 2 1 2

RH100 10K_0201 _5%

1 2

RH99 10K_0201 _5%

1 2

RH120 1K_0201_ 5% RH114 1K_0201_ 5%

1 2 1 2

RH102 1K_0201_ 5%

1 2

RH101 1K_0201_ 5%

1 2

RH40 100K_040 2_5% RH45 100K_040 2_5%

1 2

RH47 SHORT PADS@

1 2

RH46 SHORT PADS@

RC60 49.9K_02 01_1%

1 2 1 2

RC62 49.9K_02 01_1%

1 2

RC59 49.9K_02 01_1%

1 2

RC58 49.9K_02 01_1%

1 2

RH131 2.2K_020 1_5% RH132 2.2K_020 1_5%

1 2

RH86 1K_0201_ 5%

1 2 1 2

RH85 1K_0201_ 5%

1 2

RH130 10K_0201 _5%

1 2

RH127 100K_020 1_5%

1 2

RH72 100K_020 1_5% RH76 100K_020 1_5%

1 2 1 2

RH75 100K_020 1_5%

1 2

RC53 2.2K_020 1_5%

1 2

RC52 2.2K_020 1_5%

+3VS

+1.8VS

+3V_PRIM

+3VS_TS

UC1F

Strap Pin

BC3

GPP_B15/GSPI0 _CS#

AW10

GPP_B16/GSPI0 _CLK

AW6

GPP_B17/GSPI0 _MISO

BB4

GPP_B18/GSPI0 _MOSI

BB2

GPP_B19/GSPI1 _CS#

AW12

GPP_B20/GSPI1 _CLK

AW4

GPP_B21/GSPI1 _MISO

AW8

GPP_B22/GSPI1 _MOSI

AC8

GPP_C8/UART0_R XD

AA8

GPP_C9/UART0_TXD

AA10

GPP_C10/UART0_ RTS#

AA12

GPP_C11/UART0_ CTS#

AD5

GPP_C20/UART2_ RXD

AD7

GPP_C21/UART2_ TXD

AD3

GPP_C22/UART2_ RTS#

AD9

GPP_C23/UART2_ CTS#

AD11

GPP_C16/I2 C0_SDA

AB3

GPP_C17/I2 C0_SCL

AB9

GPP_C18/I2 C1_SDA

AB11

GPP_C19/I2 C1_SCL

AP3

GPP_F4/I2C2_ SDA

AP7

GPP_F5/I2C2_ SCL

AP5

GPP_F6/I2C3_ SDA

AT7

GPP_F7/I2C3_ SCL

AN4

GPP_F8/I2C4_ SDA

AN6

GPP_F9/I2C4_ SCL

SKYLAKE_ULX_EDS/BGA

@

DWL_REQ36

TC39 TC84 TC35

WLAN_ON26

SIO_EXT_SCI#45

TS_EN38

HOST_SD_WP#47

SIO_EXT_WAKE#4 5

TS_I2C_SDA22 TS_I2C_SCL2 2

SKYCAM_I2C_DATA3 1 SKYCAM_I2C_CLK31

UF_I2C_DATA29 UF_I2C_CLK29

UART2_RXD UART2_TXD SIO_EXT_WAKE# UART2_CTS#

TC2

WWAN_RST#27 PCH_MUTE#23 BT_ON/OFF #26

UART2_RXD44 UART2_TXD4 4

TC74

D D

Codec, AMP

Touch Screen

Skycam PMIC

UF CAM

C C

+3V_PRIM

1 2

RC54 49.9K_0201_ 1%

1 2

RC55 49.9K_0201_ 1%

1 2

RC113 10K_0201_5 % RC112 49.9K_0201_ 1%

1 2

WLAN_PWR_EN

GPP_B18

SIO_EXT_SCI#

GPP_B22

WWAN_RST#

HOST_SD_WP#

UART2_RXD UART2_TXD SIO_EXT_WAKE# UART2_CTS#

I2C0_SDA I2C0_SCL

TS_I2C_SDA TS_I2C_SCL

Functional Strap Definitions

GSPI0_MOSI / GPP_B18 (Internal Pull Down) :

No Reboot

0 = Disable No Reboot mode.

1 = Enable No Reboot Mode. (PCH will disable the TCO Timer system reboot fea ture). This function is useful when running ITP/XDP.

+3V_PRIM

1 2

RC11 150K_0402 _5%@

GSPI1_MOSI / GPP_B22 (Internal Pull Down) :

B B

Boot BIOS Strap Bit

0 = SPI Mode

+3V_PRIM

RC12 150K_0402 _5%@

1 2

GPP_B22

1 = LPC Mode

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

2041/09/08 2015/12/31

Compal Secre t Data

Deciphered Date

2

Compal Electronics, Inc.

Title

P10-SKL Y(6/13) GPIO,LPIO,I2C

Size Document Number Rev

C

LA-C791P

Date: Sheet

Date: Sheet of

1

of

10 66Friday, Nove mber 27, 201 5

1.0

5

4

3

2

1

UC1H

XDP_PRDY#

XDP_PREQ#

PCH_GPIOA7

T36@ T37@

C20

PCIE1_RXN/USB3_ 5_RXN

A20

PCIE1_RXP/USB3_5 _RXP

G20

PCIE1_TXN/USB3_5 _TXN

J20

PCIE1_TXP/USB3_5_ TXP

B19

PCIE2_RXN/USB3_ 6_RXN

D19

PCIE2_RXP/USB3_6 _RXP

F19

PCIE2_TXN/USB3_6 _TXN

H19

PCIE2_TXP/USB3_6_ TXP

C22

PCIE3_RXN

A22

PCIE3_RXP

G22

PCIE3_TXN

J22

PCIE3_TXP

B21

PCIE4_RXN

D21

PCIE4_RXP

F21

PCIE4_TXN

H21

PCIE4_TXP

C24

PCIE5_RXN

A24

PCIE5_RXP

G24

PCIE5_TXN

J24

PCIE5_TXP

B23

PCIE6_RXN

D23

PCIE6_RXP

F23

PCIE6_TXN

H23

PCIE6_TXP

C26

PCIE7_RXN/SATA0_RXN

A26

PCIE7_RXP/SATA0_RXP

G26

PCIE7_TXN/SATA0_TXN

J26

PCIE7_TXP/SATA0_TXP

B25

PCIE8_RXN/SATA1A_RXN

D25

PCIE8_RXP/SATA1A_RXP

F25

PCIE8_TXN/SATA1A_TXN

H25

PCIE8_TXP/SATA1A_TXP

C28

PCIE9_RXN

A28

PCIE9_RXP

G28

PCIE9_TXN

J28

PCIE9_TXP

B27

PCIE10_RXN

D27

PCIE10_RXP

F27

PCIE10_TXN

H27

PCIE10_TXP

A9

PCIE_RCOMPN

B10

PCIE_RCOMPP

D51

PROC_PRDY#

B55

PROC_PREQ#

BF3

GPP_A7/PIRQA#

SKYLAKE_ULX_EDS/BGA

@

+3VS

PCIE/USB3/SATA

USB3RN544

USB3RP544

USB3TN544

USB3TP544

D D

XDP_PRDY#5

XDP_PREQ#5

XDP_PRDY# XDP_PREQ#

PCIE_PRX_DTX_N7_R PCIE_PRX_DTX_P7_R PCIE_PTX_DRX_N7_C PCIE_PTX_DRX_P7_C

PCIE_PTX_DRX_N8_C PCIE_PTX_DRX_P8_C

PCIE_PTX_DRX_N9_C PCIE_PTX_DRX_P9_C

PCIE_PTX_DRX_N6_C PCIE_PTX_DRX_P6_C

PCIE_RCOMPN PCIE_RCOMPP

TC36

1 2

RC38 10K_0201_5 %

RH121 0_0201_ 5%@

PCIE_PRX_DTX_N728 PCIE_PRX_DTX_P72 8 PCIE_PTX_DRX_N728

NGFF SSD

WLAN

Cardreader

C C

PCIE_PTX_DRX_P72 8

PCIE_PRX_DTX_N828 PCIE_PRX_DTX_P82 8 PCIE_PTX_DRX_N828 PCIE_PTX_DRX_P82 8

PCIE_PRX_DTX_N926 PCIE_PRX_DTX_P92 6 PCIE_PTX_DRX_N926 PCIE_PTX_DRX_P92 6

PCIE_PRX_DTX_N635 PCIE_PRX_DTX_P63 5 PCIE_PTX_DRX_N635 PCIE_PTX_DRX_P63 5

1 2 1 2

RH125 0_0201_ 5%@

1 2

CH23 0.22U_0201_6.3 V6M

1 2

CH22 0.22U_0201_6.3 V6M

1 2

CH20 0.22U_0201_6.3 V6M

1 2

CH21 0.22U_0201_6.3 V6M

1 2

CH16 0.1U_0201_10 V6K

1 2

CH17 0.1U_0201_10 V6K

1 2

CH18 0.1U_0201_10 V6K

1 2

CH19 0.1U_0201_10 V6K

RC66 100_020 1_1%

1 2

closed MCP 1000 mils

PCH_GPIOA7

SKYLAKE_ULX

8 OF 20

SSIC / USB3

USB2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

USB3_2_RXN/SSIC _1_RXN

USB3_2_RXP/SSIC_ 1_RXP USB3_2_TXN/SSIC_ 1_TXN

USB3_2_TXP/SSIC_1 _TXP

USB3_3_RXN/SSIC _2_RXN

USB3_3_RXP/SSIC_ 2_RXP USB3_3_TXN/SSIC_ 2_TXN

USB3_3_TXP/SSIC_2 _TXP

USB2_VBUSSENSE

GPP_E9/USB2_O C0# GPP_E10/USB2_ OC1# GPP_E11/USB2_ OC2# GPP_E12/USB2_ OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E8/SATALED#

USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP

USB2N_1 USB2P_1

USB2N_5 USB2P_5

USB2N_7 USB2P_7

USB2N_3 USB2P_3

USB2N_9 USB2P_9

USB2N_2 USB2P_2

USB2_COMP

USB2_ID

C16 A16 G16 J16

B15 D15 F15 H15

C18 A18 G18 J18

B17 D17 F17 H17

AJ6 AJ4

AH5 AH3

AF5 AF3

AL6 AL4

AG6 AG4

AM3 AM5

USB2_COMP

N2

OTG_ID

AF7

VBUS_SENSE

AE6

USB_OC0#

N12

USB_OC1#

M11

USB_OC2#

F8

NFC_IRQ

B8

F10

TS_RST#

H10 L8

G11

PEDET GPP_E1

J11

TPM_IRQ#

N10

SOC_SATALED#

H8

USB3RN1 40 USB3RP1 4 0 USB3TN1 40

USB3TP1 40

USB3RN2 27 USB3RP2 2 7 USB3TN2 27

USB3TP2 27

USB3RN3 47 USB3RP3 4 7 USB3TN3 47

USB3TP3 47

USB3RN4 30 USB3RP4 3 0 USB3TN4 30

USB3TP4 30

USB20_N1 42 USB20_P1 42

USB20_N5 47 USB20_P5 47

USB20_N7 37 USB20_P7 37

USB20_N3 27 USB20_P3 27

USB20_N9 44 USB20_P9 44

USB20_N2 26 USB20_P2 26

1 2

RC61 113_0402_1 %

OTG_ID 42 VBUS_SENSE 42

USB_OC0# 42 USB_OC1# 44

NFC_IRQ 36

DEVSLP0 28 TS_RST# 22

NFC_RST# 36

PEDET 28

TPM_IRQ# 30

TC61

SATAXPCI Ex is s elected if the F lex I/O soft st rap PC IE_SATA_ Px_Flex = 11b.

Setting PCIE_SA TA_Px_Fl ex = 11b also e nables a n inter nal pull -up res istor in this pin to all ow Flexi ble I/O selecti on of SA TA Port x or PC Ie* Por t x to b e assigned based on the t ype of card in stalled and bas ed on th e SATAX PCIEx mu x selector with t he polar ity for SATA or PCIe*

When PSC PSP_Px_ STRP = 0 , PCIe wil l be se lected i f the sa mpled v alue is “0” and SATA wi ll be s elected if the s ampled value is “1”. When PSC PSP_Px_ STRP = 1 , SATA wil l be se lected i f the sa mpled v alue is “0” and PCIe wi ll be s elected if the s ampled value is “1”.

Use FITC to set the sof t straps of the PCIe/SA TA Comb o Port x Strap (PCIE_SA TA_Px_F lex) and Polarit y Selec t SATA/P CIe Com bo Port x (PSCPSP_ Px_STRP ), refer to Skyl ake-LP SPI Flas h Progr amming G uide fo r details.

USB Type-CUSB Type-A

WWAN

Base

DS4 camera

USB Type-C

Base

USH

WWAN

USB Type-A

BT

USB Type-C

USB Type-A

TS_RST#

USB_OC0# USB_OC1# USB_OC2# NFC_IRQ GPP_E1

TPM_IRQ#

PEDET

OTG_ID VBUS_SENSE

closed MCP 2000 mils

GPP_E1

RH118 10K_0201 _5%

RH122 10K_0201 _5% RH126 10K_0201 _5% RH110 10K_0201 _5% RH109 10K_0201 _5%@

RH119 10K_0201 _5%@

RH96 10K_0201 _5% RH115 10K_0201 _5%

RH90 10K_0201 _5% R210 10 0K_0201_5 %

USB_OC0# USB_OC1# USB_OC2# NFC_IRQ

RH133 0_0201_ 5%@

1 2

1 2 1 2 1 2 1 2 1 2

1 2 1 2

T32 T35 T30 T31

+3VS_TS

+3V_PRIM

PEDET

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

2041/09/08 2015/12/31

Compal Secre t Data

Deciphered Date

2

Compal Electronics, Inc.

Title

P11-SKL Y(7/13) PCIE,USB

Size Document Number Rev

C

LA-C791P

Date: Sheet of

Date: Sheet

1

of

11 66Friday, Nove mber 27, 201 5

1.0

5

4

3

2

1

+0.85VS_VCCIO

12

RC10 0_0201_ 5%

@

12

RC9 0_0201_ 5%

@

+0.85VS_VCCIO

CC50

0.1U_020 1_10V6K

1

2

VCCIO_SENSE 57 VSSIO_SENSE 57

1

2

CC45

0.1U_020 1_10V6K

CC22

0.1U_020 1_10V6K

1

2

+0.85VS_VCCIO

1

2

@

CC24

CC27

0.1U_020 1_10V6K

1

2

CC31

CC20

0.1U_020 1_10V6K

1

2

@

+0.85VS_VCCIO

Primary side cap

CC60

CC38

CC23

0.1U_020 1_10V6K

1

2

CC35

0.1U_020 1_10V6K

1

2

@

CC93

1U_0402 _6.3V6K

1

2

@

CC43

CC57

0.1U_020 1_10V6K

1

2

CC30

CC34

0.1U_020 1_10V6K

1

2

@

CC92

22U_060 3_6.3V6M

1

2

CC21

CC14

0.1U_020 1_10V6K

1

2

CC33

0.1U_020 1_10V6K

1

2

@

CC26

CC25

0.1U_020 1_10V6K

1

2

CC36

0.1U_020 1_10V6K

1

2

@

0.1U_020 1_10V6K

1

2

CC15

CC32

0.1U_020 1_10V6K

1

2

@

+1.2V_DDR

1

2

D D

1

2

C C

Backside cap Backside cap

CC12

CC96

CC9

CC18

0.1U_020 1_10V6K

1

2

CC107

CC95

0.1U_020 1_10V6K

1

2

CC10

CC16

0.1U_020 1_10V6K

1

2

CC97

CC98

0.1U_020 1_10V6K

1

2

CC8

CC19

0.1U_020 1_10V6K

1

2

CC94

CC104

0.1U_020 1_10V6K

1

2

CC7

CC17

0.1U_020 1_10V6K

1

2

CC99

0.1U_020 1_10V6K

1

2

CC11

0.1U_020 1_10V6K

1

2

VDDQC trace filter width = 6mm Total etch length = 186.94mils PDG P597

L10

1 2

1NH_LQG15HN1N0S02D_0.3NH

VCCST : Sustain voltage for processor standby modes

VCCSTG : Gated sustain voltage for processor standby modes

+VDDQ_CPU_CLK+1.2V_DDR

CC6

0.1U_0201_ 10V6K

1

2

+1.0VS_VCCSTG

BSC Side

1

2

0.1U_020 1_10V6K

+1.0V_VCCST

+1.0VS_VCCSTG

+1.2V_VCCPLL_ OC

+1.0V_VCCPLL

CC117

+1.0V_VCCST

1

2

0.1U_020 1_10V6K

UC1N

AH64

VDDQ

BA27

VDDQ

BA37

VDDQ

BA49

VDDQ

BP32

VDDQ

BP50

VDDQ

AK64

VDDQ

BA29

VDDQ

BA41

VDDQ

BA51

VDDQ

BP34

VDDQ

BP56

VDDQ

AT64

VDDQ

BA31

VDDQ

BA43

VDDQ

BN64

VDDQ

BP40

VDDQ

BP58

VDDQ

AV64

VDDQ

BA33

VDDQ

BA45

VDDQ

BP24

VDDQ

BP42

VDDQ

BP64

VDDQ

BA25

VDDQ

BA35

VDDQ

BA47

VDDQ

BP26

VDDQ

BP48

VDDQ

BA39

VDDQC

V26

VCCST

Y26

VCCST

R26

VCCSTG

T26

VCCSTG

AE27

VCCPLL_OC

AF27

VCCPLL_OC

R27

VCCPLL

T27

VCCPLL

SKYLAKE_ULX_EDS/BGA

@

1 2

RC67 0_0402_5%@

CC118

SKYLAKE_ULX

1.2V@2A

1.0V@100mA

1.0V@160mA

1.2V@350mA

1.0V@100mA

CPU POWER 3 OF 4

14 OF 2 0

+1.0V_VCCPLL

0.1U_020 1_10V6K

0.85V@3A

PSC Side

1

CC116

2

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR

VCCIO_SENSE

VSSIO_SENSE

AC23 AF24 AN26 AC24 AF26 AR26 AE23 AH26 AT26 AE24 AK26 AE26 AL26

AV26 AV36 AV46 AW31 AW41 AW51 AV28 AV38 AV48 AW33 AW43 AV30 AV40 AV50 AW35 AW45 AV32 AV42 AW27 AW37 AW47 AV34 AV44 AW29 AW39 AW49

AT24 AR24

+0.85VS_VCCIO+1.2V_DDR

VCCIO_SENSE VSSIO_SENSE

+0.85VS_VCCIO

B B

+0.85VS_VCCIO

+3V_PRIM

5

U38

@

1

P

NC

4

RUN_ON_EC9,34 ,38,39,45, 56,57

A A

5

4

2

Y

A

G

NL17SZ14DFT2 G_SOT353- 5

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

12

@

R406 0_0603_ 5%

13

D

@

2

Q18 AO7400_SC- 70-3

G

S

Compal Secre t Data

2041/09/08 2015/12/31

Compal Secre t Data

Deciphered Date

2

Compal Electronics, Inc.

Title

P12-SKL Y(8/13) Power

Size Document Number Rev

C

LA-C791P

Date: Sheet of

1

12 66Friday, Nove mber 27, 201 5

1.0

5

4

3

2

1

+1.0V_PRIM

D D

C C

B B

+0.95V_PRIM

+1.0VA_GATE

+1.0V_PRIM

+3V_PRIM

RC17

@

1 2

0_0603_ 5%

RC18

@

1 2

0_0603_ 5%

RC51

@

1 2

0_0603_ 5%

L15

1 2

2.2UH_LQM2MPN2R2NG0L_30%

L11

1 2

BLM18EG221SN1D_ 2P

RC50

@

1 2

0_0603_ 5%

RC40

@

1 2

0_0603_ 5%

1

CC48

0.1U_0201_ 10V6K

2

1

CC39

0.1U_0201_ 10V6K

2

@

1

CC113

0.1U_0201_ 10V6K

2

@

1

CC40

0.1U_0201_ 10V6K

2

Close to Pin AH18 Close to Pin V1Close to Pin AH13 Close to Pin AR21 Clos e to Pin AA15

1

CC54

0.1U_0201_ 10V6K

2

+VCCPRIM_CORE

1

CC49

0.1U_0201_ 10V6K

2

+1.0VA_GATE

RC19

@

1 2

0_0603_ 5%

Close to Pin AE18 and AR16

+1.0V_MPHYGT

1

CC114 22U_0603_6 .3V6M

2

1

CC115 1U_0201_6. 3V6K

2

1

CC80

0.1U_0201_ 10V6K

2

Close to Pin T1 and T15

+1.0V_MPHYPLL

1

CC89 22U_0603_6 .3V6M

2

1

CC88 22U_0603_6 .3V6M

2

1

CC76

0.1U_0201_ 10V6K

2

Close to Pin V15

+1.0VA_GATE

+1.0V_APLL

1

CC75 22U_0603_6 .3V6M

2

1

CC79 22U_0603_6 .3V6M

2

1

CC124

0.1U_0201_ 10V6K

2

Close to Pin AA18

@

1

CC66

0.1U_0201_ 10V6K

2

@

1

CC110

0.1U_0201_ 10V6K

2

1

CC62

0.1U_0201_ 10V6K

2

1

2

Close to Pin AH21 Close to Pin AK19Close to Pin AC2

+3.3V_VCCSPI

1

CC100

0.1U_0201_ 10V6K

2

+3VS_AUDIO

1 2

BLM18EG221SN1D_ 2P

+3V_1.8V_HDA

L24

1

CC13

0.1U_0201_ 10V6K

2

Close to Pin AT23Close to Pin AT15

+VCCPRIM_1P0

1

CC28

0.1U_0201_ 10V6K

2

+VCCSRAM_1P0

1

CC58

0.1U_0201_ 10V6K

2

1

2

Close to Pin AA21

RC102

@

1 2

0_0603_ 5%

+VCCAPLLEBB_1P0

1

CC83

0.1U_0201_ 10V6K

2

Close to Pin R15

+VCCPRIM_3P3

CC53

0.1U_0201_ 10V6K

1

CC61 1U_0201_6. 3V6K

2

PDG_place as close as ball PDG_VCCHDA design for HD Audio VCCHDA should be connected to 3.3V or 1.5V, or designed for I2S V CCHDA should be connected to 1.8V or 3.3V.

@

CC37 1U_0402_6. 3V6K

+3VALW_DSW

DCPDSW_1P0

1

CC108 1U_0402_6. 3V6K

2

Close to Pin AL2

1

CC64

0.1U_0201_ 10V6K

2

Close to Pin AL15

+3V_1.8V_HDA

+VCCPRIM_1P0

1.0V/0.599A

+VCCPRIM_CORE

1.1A

DCPDSW_1P0

3.3V/0.071A

+VCCPRIM_1P0

1.0V/0.022A

+1.0V_MPHYGT

1.0V/0.154A

+1.0V_MPHYPLL

1.0V/0.088A

+1.0V_APLL

1.0V/0.026A

+VCCPRIM_1P0

1.0V/0.599A

3.3V/0.071A

3.3V/0.068A

+3.3V_VCCSPI

3.3V/0.011A

+VCCSRAM_1P0

1.0V/0.565A

+VCCPRIM_3P3

3.3V/0.075A

+VCCPRIM_1P0

+VCCAPLLEBB_1P0

1.0V/0.033A

+3V_PRIM

AH18 AH19 AK18 AL18

AE18 AE19 AF18 AF19 AR16 AT16

AA18 AA19

AH13 AH15

AL15

AM13

AT23 AV22

AT15 AV15

AA21 AA23 AK23 AL23 AN23 AR23

AH21 AK21

AR21 AT21

RC44

@

1 2

0_0603_ 5%

RTC Logic Primary Well 3.3 V. This power supplies the RTC internal VRM. It will

UC1P

VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0

VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE

AL2

DCPDSW_1P0

AM1

DCPDSW_1P0

V1

VCCMPHYAON_1P0

W2

VCCMPHYAON_1P0

T1

VCCMPHYGT_1P0

T15

VCCMPHYGT_1P0

T16

VCCMPHYGT_1P0

U2

VCCMPHYGT_1P0

V15

VCCAMPHYPLL_1P0

V16

VCCAMPHYPLL_1P0

VCCAPLL_1P0 VCCAPLL_1P0

VCCPRIM_1P0 VCCPRIM_1P0

VCCDSW_3P3 VCCDSW_3P3

VCCHDA VCCHDA

VCCSPI VCCSPI

VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0

VCCPRIM_3P3 VCCPRIM_3P3

VCCPRIM_1P0 VCCPRIM_1P0

R15

VCCAPLLEBB

R16

VCCAPLLEBB

SKYLAKE_ULX_EDS/BGA

@

1

2

Primary Well 1.0 V : For I/O blocks, ungated ISH SRAM power, USB AFE Digital Logic, JTAG, Thermal Sensor and MIPI DPHY.

1.0V@

0.95V@1. 1A

Analog supply for OPI, USB2 and Audio PLL Primary 1.0V: Filtering required.

HD Audio Power 3.3 V, 1.8 V, 1.5 V. For Intel High Definition Audio

SPI Primary Well 3.3 V or 1.8 V

SRAM Primary Well 1.0 V. Dedicated SRAM rail and can have on board power down gate control.

SKYLAKE_ULX

DCPDSW_1P0 Deep Sx Well 1.0 V: This rail is generated by on die DSW low dropout (LDO) linear voltage regulator to supply DSW GPIOs, DSW core logic and DSW USB2 logic. Board needs to connect 1 uF capacitor to this rail and power should NOT be driven from the board. When primary well power is up, this rail is ypassed from VCCPRIM_1p0.

Mod PHY Always On Primary 1.0 V: Always on primary supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic

Mod PHY Externally Gated Primary 1.0 V: Externally gated primary supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic.

Analog supply for USB3, PCIe Gen 2/Gen 3, SATA3 and MIPI PLL 1.0V: This rail is from externally gated domain. Filtering required.

Deep Sx Well for GPD GPIOs and USB2

Primary Well 3.3 V

1.0V/0.599A

1

CC112

0.1U_0201_ 10V6K

CC102

0.1U_0201_ 10V6K

2

PCH POWER

16 OF 2 0

be off during Deep Sx mode.

RTC de-coupling capacitor only. This rail should NOT be driven.

1.0V/0.035A

Clock Buffers Primary 1.0 V

1.0V/0.029A

Clock Buffers Primary 1.0 V

1.0V/0.024A

Clock Buffers Primary 1.0 V

1.0V/0.033A

Clock Buffers Primary 1.0 V

1.0V/0.004A

Clock Buffers Primary 1.0 V

1.0V/0.010A

1

CC103

0.1U_0201_ 10V6K

2

VCCPGPPA VCCPGPPA VCCPGPPB VCCPGPPB VCCPGPPC VCCPGPPC VCCPGPPD VCCPGPPD VCCPGPPE VCCPGPPE VCCPGPPF

VCCPGPPF VCCPGPPG VCCPGPPG

VCCPRIM_3P3 VCCPRIM_3P3

VCCPRIM_1P0 VCCPRIM_1P0

VCCATS_1P8 VCCATS_1P8

VCCRTCPRIM_3P3 VCCRTCPRIM_3P3

VCCRTC VCCRTC

DCPRTC DCPRTC

VCC19P2_1P0 VCC19P2_1P0

VCCCLK2 VCCCLK2

VCCCLK3 VCCCLK3

VCCCLK4 VCCCLK4

VCCCLK5 VCCCLK5

VCCCLK6 VCCCLK6

GPP_B0/CORE_VI D0 GPP_B1/CORE_VI D1

1

CC101

0.1U_0201_ 10V6K

2

+3.3V_PCH_GPP

AT1 AU2

+3.3V_PCH_GPP

AV1 AW2

+3.3V_PCH_GPP

AH1 AJ2

+3.3V_PCH_GPP

AF1 AG2

+3.3V_PCH_GPP

AA2 AB1

+1.8V_PCH_GPP

AN2 AP1

+3.3V_PCH_GPP

AN15 AP13

+VCCPRIM_3P3

AC2 AD1

3.3V/0.075A

+VCCPRIM_1P0

AA15 AA16

1.0V/0.599A

Thermal Sensor Primary Well 1.8 V

+1.8V_PCH_GPP

AE15 AE16

1.0V/0.006A

+VCCPRIM_3P3

AK19 AL19

3.3V/0.001A

AR19 AT19

3.3V/0.001A

AT18

CC5 0.1U_0201_10 V6K

AV18

V18

+VCCCLK1

Y18

V19

+VCCCLK2

Y19

V23

+VCCCLK3

Y23

V21

+VCCCLK4

Y21

R21

+VCCCLK5

R23

R19

+VCCCLK6

T19

BA13 BB12

1

CC111

0.1U_0201_ 10V6K

2

Close to Pin AT1 Close to Pin AV1 Close to Pin AH1 Close to Pin AF1 Close to Pin AA 2 Close to Pin AN15

1 2

Close to Pin AT18

VCCPRIM_VID0 58 VCCPRIM_VID1 58

1

2

3.3V/0.020A

3.3V/0.004A

3.3V/0.006A

3.3V/0.008A

3.3V/0.006A

1.8V/0.161A

3.3V/0.041A

RTC Well Supply. This rail can drop to 2.0 V if all other planes are off. This power is not expected to be shut off unless the RTC battery is removed or drained.

+RTCVCC

+VCCCLK5

+3.3V_PCH_GPP

CC109

0.1U_0201_ 10V6K

+1.0V_PRIM

RC24

@

1 2

0_0603_ 5%

+VCCCLK1

1

CC85

0.1U_0201_ 10V6K

2

Close to Pin V18

RC26

@

1 2

0_0603_ 5%

A A

RC91

@

1 2

0_0603_ 5%

1

CC84 22U_0603_6 .3V6M

2

+VCCCLK2

1

CC86

0.1U_0201_ 10V6K

2

+VCCCLK3

5

+1.0V_PRIM

1

2

RC108

@

1 2

0_0603_ 5%

RC29

@

1 2

0_0603_ 5%

RC99

@

1 2

0_0603_ 5%

CC121 22U_0603_6 .3V6M

+VCCCLK4

1

CC119

0.1U_0201_ 10V6K

2

Close to Pin V21

+VCCCLK5

1

CC87

0.1U_0201_ 10V6K

2

Close to Pin R21Close to Pin V19

+VCCCLK6

4

3

+1.8V_PRIM

RC48

@

1 2

0_0603_ 5%

1

CC105

0.1U_0201_ 10V6K

2

Close to Pin AN2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

2041/09/08 2015/12/31

+1.8V_PCH_GPP

1

CC106 1U_0201_6. 3V6K

2

Close to Pin AE15

Compal Secre t Data

Deciphered Date

2

+RTCVCC

1

CC2 1U_0201_6. 3V6K

2

Close to Pin AR19

1

CC1

0.1U_0201_ 10V6K

2

Compal Electronics, Inc.

Title

P13-SKL Y(9/13) Power

Size Document Number Rev

C

LA-C791P

Date: Sheet

Date: Sheet of

1

of

13 66Friday, Nove mber 27, 201 5

1.0

5

4

3

2

1

VCCSENSE 60 VSSSENSE 60

RC80 0_0402_ 5%@

+VCC_GT

1 2

UC1M

AA53

VCCGT

AB62

VCCGT

AC47

VCCGT

AC55

VCCGT

AD54

VCCGT

AD64

VCCGT

AE61

VCCGT

AF47

VCCGT

AJ53

VCCGT

AK49

VCCGT

AN46

VCCGT

AT43

VCCGT

AT50

VCCGT

N50

VCCGT

T46

VCCGT

T54

VCCGT

U61

VCCGT

V60

VCCGT

W57

VCCGT

Y44

VCCGT

Y51

VCCGT

Y62

VCCGT

AB54

VCCGT

AB64

VCCGT

AC49

VCCGT

AC57

VCCGT

AD56

VCCGT

AE53

VCCGT

AE63

VCCGT

AF49

VCCGT

AK43

VCCGT

AK50

VCCGT

AN47

VCCGT

AT44

VCCGT

AT51

VCCGT

R51

VCCGT

T47

VCCGT

U53

VCCGT

U63

VCCGT

V62

VCCGT

W59

VCCGT

Y46

VCCGT

Y54

VCCGT

Y64

VCCGT

AB58

VCCGT

AC44

VCCGT

AC51

VCCGT

AC61

VCCGT

AD60

VCCGT

AE57

VCCGT

AF44

VCCGT

AF51

VCCGT

AK46

VCCGT

AB60

VCCGT

AC46

VCCGT

SKYLAKE_ULX_EDS/BGA

@

SKYLAKE_ULX

1.5V@20A

CPU POWER 2 OF 4

13 OF 2 0

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT_SENSE VSSGT_SENSE

AC53 AC63 AD62 AE59 AF46 AG53 AK47 AN44 AN51 AT49 N48 T44 T51 U59 V58 W55 Y43 Y50 Y60 AB56 AC43 AC50 AC59 AD58 AE55 AF43 AF50 AK44 AK51 AN49 AT46 N44 R53 T49 U55 V54 V64 W61 Y47 Y56 AN50 AT47 N46 T43 T50 U57 V56 W53 W63 Y49 Y58 AN43

N52 P52

+VCC_GT

12

1 2

RC56 100_020 1_1%

Close CPU

VCCGT_SENSE VSSGT_SENSE

100_020 1_1% RC57

Trace Length < 25 mils

VCCGT_SENSE 60 VSSGT_SENSE 60

+VCC_CORE

A64 AE32 AE40 AH41 AN32 AT33 AT41

J64

D D

C C

SVID ALERT

L48

M33

M43

M53

M64

N40

N59

P60

R57

T41 AA32 AE33 AE41 AK32 AN41 AT35

B64

L40

L50

M35

M45

M56

N32

N42

N61

P62

R59

V32 AA41 AE35 AF32 AK41 AR32 AT36

D64

L42

L52

M37

M47

R63

P56

R32

Y32

SOC_SVID_ALERT#

SKYLAKE_ULX_EDS/BGA

@

SVID DATA

B B

SOC_SVID_DAT

SKYLAKE_ULX

UC1L

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

RC78 0_0402_ 5%@

RC79

1 2

220_040 2_5%

1 2

1.5V@16A

CPU POWER 1 OF 4

12 OF 2 0

+1.0V_VCCST

Place the PU resistors close to CPU

12

RC90 56_0201 _5%

+1.0V_VCCST

Place the PU resistors close to CPU

RC96 100_020 1_1%

1 2

VCC_SENSE VSS_SENSE

+VCC_CORE

M58

VCC

N34

VCC

N54

VCC

N63

VCC

P64

VCC

R61

VCC

V41

VCC

AC41

VCC

AE38

VCC

AH32

VCC

AL41

VCC

AT32

VCC

AT40

VCC

H63

VCC

L46

VCC

L63

VCC

M41

VCC

M51

VCC

M62

VCC

N38

VCC

N57

VCC

P58

VCC

R41

VCC

T32

VCC

Y41

VCC

AC32

VCC

AE36

VCC

AF41

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG VCCSTG

VCC

AL32

VCC

AR41

VCC

AT38

VCC

F64

VCC

L44

VCC

L54

VCC

M39

VCC

M49

VCC

M60

VCC

N36

VCC

N55

VCC

L34 L32

B58 A56 A58

AA26 AC26

SVID_ALERT# 60

SOC_SVID_ALERT# SOC_SVID_CLK SOC_SVID_DAT

1 2

RC68 0_0402_ 5%@

(To VR)

+1.0VS_VCCSTG

+VCC_CORE

12

1 2

RC23 100_020 1_1%

Trace Length < 25 mils

100_020 1_1% RC22

SVID CLK

SVID_DAT 60 SVID_CLK 60

(To VR)

SOC_SVID_CLK

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

2041/09/08 2015/12/31

Compal Secre t Data

Deciphered Date

2

Compal Electronics, Inc.

Title

P14-SKL Y(10/13) Power

Size Document Number Rev

C

LA-C791P

Date: Sheet

Date: Sheet of

1

of

14 66Friday, Nove mber 27, 201 5

1.0

5

D D

4

3

2

1

+VCCCOREG0

CC73

+VCC_SA

AA29 AF30 AN29

L30

T30 AC29 AH29 AN30

+VCC_SA

1 2

RC33 0_0402_ 5%@

+VCC_SA

C C

VCCSA_SENSE60 VSSSA_SENSE60

B B

12

RC21 100_020 1_1%

RC20 100_020 1_1%

1 2

1

2

CC29

+VCC_SA_DDR

CC4

CC3

0.1U_020 1_10V6K

22U_060 3_6.3V6M

0.1U_020 1_10V6K

1

2

@

AC30 AK29 AR29

AE29 AK30

AL29

AT29 AT30

AF29

M31

V29

N30

Y29

R29

Y30

T29

M29 N28

SKYLAKE_ULX

UC1O

VCCSA VCCSA VCCSA

1.05V@4. 1A

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCSA_DDR VCCSA_DDR

VCCSA_SENSE VSSSA_SENSE

CPU POWER 4 OF 4

SKYLAKE_ULX_EDS/BGA

@

15 OF 2 0

VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0

VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1

AA35 R38 Y35 AA38 T35 Y38 AC35 T38 AC38 V35 R35 V38

AF35 AK38 AR35 AF38 AL35 AR38 AH35 AL38 AH38 AN35 AK35 AN38

+VCCCOREG0

+VCCCOREG1

1

2

+VCCCOREG1

1

2

CC59

0.1U_020 1_10V6K

1

2

0.1U_020 1_10V6K

1

2

CC81

CC56

CC70

0.1U_020 1_10V6K

1

2

CC46

0.1U_020 1_10V6K

1

2

Backside cap

CC67

1

2

CC69

CC71

0.1U_020 1_10V6K

1

2

Backside cap

CC42

1

2

CC41

CC52

0.1U_020 1_10V6K

1

2

CC82

CC68

0.1U_020 1_10V6K

1

2

CC63

0.1U_020 1_10V6K

1

2

CC74

0.1U_020 1_10V6K

1

2

CC51

CC55

0.1U_020 1_10V6K

1

2

CC72

CC78

0.1U_020 1_10V6K

1

2

CC65

0.1U_020 1_10V6K

1

2

CC77

0.1U_020 1_10V6K

1

2

CC44

CC47

0.1U_020 1_10V6K

1

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

2041/09/08 2015/12/31

Compal Secre t Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet

Date: Sheet of

P15-SKL Y(11/13) Power

LA-C791P

1

of

15 66Friday, Nove mber 27, 201 5

1.0

5

SKYLAKE_ULX

D D

C C

B B

UC1Q

A14

VSS

AA36

VSS

AA47

VSS

AA57

VSS

AC15

VSS

AC27

VSS

AE10

VSS

AE43

VSS

AE50

VSS

AF16

VSS

AF40

VSS

AF62

VSS

AH24

VSS

AH40

VSS

AH49

VSS

AK1

VSS

AK24

VSS

AK40

VSS

AL16

VSS

AL33

VSS

AL46

VSS

AL53

VSS

AN18

VSS

AN33

VSS

AP64

VSS

AR2

VSS

AR4

VSS

AR47

VSS

AR6

VSS

AU55

VSS

AV16

VSS

AW17

VSS

AY16

VSS

AY32

VSS

AY42

VSS

AY52

VSS

BA5

VSS

BA9

VSS

BB28

VSS

BB38

VSS

BB48

VSS

BC17

VSS

BD56

VSS

BE33

VSS

BF56

VSS

BG2

VSS

BG8

VSS

BH28

VSS

BH40

VSS

BH50

VSS

BJ29

VSS

BK56

VSS

BL35

VSS

BM16

VSS

BP36

VSS

BP54

VSS

D10

VSS

E14

VSS

E24

VSS

E34

VSS

E44

VSS

E54

VSS

J14

VSS

J9

VSS

AH47

VSS

AJ59

VSS

AK16

VSS

AK36

VSS

AK9

VSS

V24

VSS

SKYLAKE_ULX_EDS/BGA

@

GND 1 OF 3

17 OF 2 0

K23

VSS

K33

VSS

K43

VSS

K53

VSS

L61

VSS

N20

VSS

R10

VSS

R24

VSS

R40

VSS

R49

VSS

T13

VSS

T33

VSS

T60

VSS

V27

VSS

V43

VSS

V50

VSS

Y15

VSS

Y33

VSS

Y9

VSS

AA24

VSS

AA40

VSS

AA49

VSS

AA59

VSS

AC16

VSS

AC33

VSS

AE2

VSS

AE44

VSS

AE51

VSS

AF21

VSS

AF54

VSS

AF64

VSS

AH27

VSS

AH43

VSS

AH50

VSS

AK11

VSS

AK27

VSS

AK5

VSS

AL21

VSS

AL36

VSS

AL47

VSS

AL59

VSS

AN19

VSS

AN36

VSS

AR10

VSS

AR27

VSS

AR40

VSS

AR49

VSS

AR8

VSS

AU57

VSS

AV20

VSS

AW19

VSS

AY24

VSS

AY34

VSS

AY44

VSS

BA53

VSS

BB20

VSS

BB30

VSS

BB40

VSS

BB50

VSS

BC29

VSS

BD63

VSS

BE35

VSS

BF59

VSS

BG29

VSS

AL30

VSS

AL44

VSS

AL51

VSS

AN16

VSS

AN27

VSS

BA7

VSS

4

SKYLAKE_ULX

UC1R

BH20

VSS

BH32

VSS

BH42

VSS

BH52

VSS

BJ47

VSS

BL1

VSS

BL47

VSS

BM18

VSS

BN6

VSS

BP38

VSS

BP60

VSS

E16

VSS

E26

VSS

E36

VSS

E46

VSS

E56

VSS

J3

VSS

K15

VSS

K25

VSS

K35

VSS

K45

VSS

K55

VSS

M3

VSS

N22

VSS

R30

VSS

R43

VSS

R50

VSS

T18

VSS

T36

VSS

T62

VSS

V30

VSS

V44

VSS

V51

VSS

Y16

VSS

Y36

VSS

Y7

VSS

AA27

VSS

AA43

VSS

AA50

VSS

AA61

VSS

AC18

VSS

AC36

VSS

AE21

VSS

AE46

VSS

AE8

VSS

AF23

VSS

AF56

VSS

AG59

VSS

AH30

VSS

AH44

VSS

AH51

VSS

AK13

VSS

AK3

VSS

AK54

VSS

AL24

VSS

AL40

VSS

AL49

VSS

AM54

VSS

AN21

VSS

AN40

VSS

AR12

VSS

AR30

VSS

AR43

VSS

AP54

VSS

AR18

VSS

AR36

VSS

AR46

VSS

AR59

VSS

BA3

VSS

SKYLAKE_ULX_EDS/BGA

@

GND 2 OF 3

18 OF 2 0

AR50

VSS

AT27

VSS

AU59

VSS

AV24

VSS

AW21

VSS

AY26

VSS

AY36

VSS

AY46

VSS

BA1

VSS

BA58

VSS

BB22

VSS

BB32

VSS

BB42

VSS

BB52

VSS

BC47

VSS

BE12

VSS

BE47

VSS

BG12

VSS

BG4

VSS

BH22

VSS

BH34

VSS

BH44

VSS

BH54

VSS

BJ62

VSS

BL29

VSS

BL8

VSS

BM20

VSS

BP22

VSS

BP44

VSS

D6

VSS

E18

VSS

E28

VSS

E38

VSS

E48

VSS

E59

VSS

J5

VSS

K17

VSS

K27

VSS

K37

VSS

K47

VSS

L14

VSS

N14

VSS

N24

VSS

R33

VSS

R44

VSS

R55

VSS

T21

VSS

T40

VSS

T64

VSS

V33

VSS

V46

VSS

Y1

VSS

Y24

VSS

Y40

VSS

AA30

VSS

AA44

VSS

AA51

VSS

AA63

VSS

AC19

VSS

AC40

VSS

AE30

VSS

AE47

VSS

AF13

VSS

AU53

VSS

AU63

VSS

AV54

VSS

AW25

VSS

AY30

VSS

AY50

VSS

3

SKYLAKE_ULX

UC1S

AF33

VSS

AF58

VSS

AH16

VSS

AH33

VSS

AH46

VSS

AH54

VSS

AK15

VSS

AK33

VSS

AK7

VSS

AL27

VSS

AL43

VSS

AL50

VSS

AM64

VSS

AN24

VSS

AN59

VSS

AR15

VSS

AR33

VSS

AR44

VSS

AR51

VSS

AT54

VSS

AU61

VSS

AV52

VSS

AW23

VSS

AY28

VSS

AY38

VSS

AY48

VSS

BA11

VSS

BA64

VSS

BB24

VSS

BB34

VSS

BB44

VSS

BB54

VSS

BD20

VSS

BE29

VSS

BF20

VSS

BG15

VSS

BG6

VSS

BH24

VSS

BH36

VSS

BH46

VSS

BH56

VSS

BK20

VSS

BL31

VSS

BM11

VSS

BM38

VSS

BP28

VSS

BP46

VSS

C14

VSS

D62

VSS

E20

VSS

E30

VSS

E40

VSS

E50

VSS

F62

VSS

J62

VSS

K19

VSS

K29

VSS

K39

VSS

K49

VSS

L57

VSS

N16

VSS

N26

VSS

R18

VSS

R36

VSS

AY40

VSS

V49

VSS

Y13

VSS

AH36

VSS

V40

VSS

SKYLAKE_ULX_EDS/BGA

@

GND 3 OF 3

19 OF 2 0

VSS_BP62

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

R46 R6 T23 T56 V13 V36 V47 Y11 Y27 Y5 BB26 BB36 BB46 BB59 BD38 BE31 BF38 BG17 BG63 BH26 BH38 BH48 BH59 BK38 BL33 BM14 BN29 BP30 BP52 C40 D8 E22 E32 E42 E52 G14 J7 K21 K31 K41 K51 L59 N18 P54 R2 R4 R47 R8 T24 T58 Y3 AA33 AA46 AA55 AB13 AC21 AD13 AE4 AE49 AF15 AF36 AF60 AH23 BP1 A5 D1

BP62

2

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

2041/09/08 2015/12/31

Compal Secre t Data

Deciphered Date

2

Compal Electronics, Inc.

Title

P16-SKL Y(12/13) GND

Size Document Number Rev

C

LA-C791P

Date: Sheet of

1

16 66Friday, Nove mber 27, 201 5

1.0

5

D D

Functional Strap Definitions

CFG[4] : Display Port Presence strap

0 = Enabled - A Display Port device is connected to the Embedded Display Port. No connect for disable.

1 = Disabled - No Physical Display Port attached to Em bedded DisplayPort*. Pull-down to GND through a 1 K? ± 5% resistor to enable port.

1 2

RC83 1K_0201_ 5%

C C

CFG4

4

CRB : Re serve P H 10k?

CFG Sign als

(For Strap & XDP)

CFG05 CFG15 CFG25 CFG35 CFG45 CFG55 CFG65 CFG75 CFG85 CFG95 CFG105 CFG115 CFG125 CFG135 CFG145 CFG155

CFG165 CFG175

CFG185

RC81 49.9_04 02_1%

CFG195

12

ITP_PMODE5

TC68 TC69

TC53 TC62

TC57

TC66 TC59

TC67

TC76

CFG4

CFG_RCOMP

3

UC1T

G52

CFG[0]

F53

CFG[1]

J52

CFG[2]

H53

CFG[3]

H55

CFG[4]

D55

CFG[5]

C56

CFG[6]

F55

CFG[7]

D61

CFG[8]

G58

CFG[9]

D57

CFG[10]

F61

CFG[11]

J60

CFG[12]

J58

CFG[13]

H61

CFG[14]

H59

CFG[15]

J54

CFG[16]

G54

CFG[17]

G56

CFG[18]

J56

CFG[19]

A54

CFG_RCOMP

A60

ITP_PMODE

B4

RSVD

B3

RSVD

F3

RSVD

F1

RSVD

L36

RSVD

L38

RSVD

BA19

RSVD

BB18

RSVD

BC19

RSVD

BD18

RSVD

D49

RSVD

M21

RSVD

L20

RSVD

M19

RSVD

L26

RSVD

SKYLAKE_ULX_EDS/BGA

@

SKYLAKE_ULX

RESERVED SIGNALS

20 OF 2 0

RSVD_TP RSVD_TP

RSVD RSVD

RSVD RSVD RSVD RSVD

RSVD RSVD

RSVD

RSVD RSVD

RSVD

RSVD RSVD

2

BL64 BG47

BA17 AY18

BF18 BE19

BA23

TP5

AY22

TP6

R12 P13 M15 L16

L18 M17

AH7

K12 H12

BN3 BP3

L22 M23

BN1

TP4

AY20 BA21

BB14

M25 L24

L28 M27

BJ15

TP1

BJ17

TP2

RC37 0_0402_ 5%@

TC40

TC78

TC58 TC46 TC70 TC71

TC73 TC60

TC72 TC63

TC31 TC32

TC54

TC33

TC3

1 2

TC75 TC77

TC30

1

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

2041/09/08 2015/12/31

Compal Secre t Data

Deciphered Date

2

Compal Electronics, Inc.

Title

P17-SKL Y(13/13) RSVD

Size Document Number Rev

C

LA-C791P

Date: Sheet

Date: Sheet of

1

of

17 66Friday, Nove mber 27, 201 5

1.0

5

4

3

2

1

+1.2V_DDR

+1.8V_MEM

U35C

A15

VDD1_0

A16

VDD1_1

B2

VDD1_2

R1

VDD1_3

T1

VDD1_4

T16

VDD1_5

A7

VDD2_0

A11

VDD2_1

B17

VDD2_2

C3

VDD2_3

C17

VDD2_4

H1

VDD2_5

H16

VDD2_6

L1

VDD2_7

R15

VDD2_8

T8

VDD2_9

U2

VDD2_10

U3

VDD2_11

A1

NC0

A17

NC1

D8

NC2

D11

NC3

E4

NC4

H4

NC5

J12

NC6

M9

NC7

U1

NC8

U17

NC9

@

VDDCA0 VDDCA1 VDDCA2 VDDCA3 VDDCA4 VDDCA5

VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20

VREFCA_A VREFCA_B

VREFDQ_A VREFDQ_B

.047U_0402 _16V7K

M_A_DQ_[0..6 3]6

M_A_CA_0_[0. .9]6

M_A_CA_1_[0. .9]6

D D

C C

B B

240_020 1_1%

R392

12

M_A_ODT06

12

R367 240_020 1_1%

M_A_CA_1_0 M_A_CA_1_1 M_A_CA_1_2 M_A_CA_1_3 M_A_CA_1_4 M_A_CA_1_5 M_A_CA_1_6 M_A_CA_1_7 M_A_CA_1_8 M_A_CA_1_9

M_A_CA_0_0 M_A_CA_0_1 M_A_CA_0_2 M_A_CA_0_3 M_A_CA_0_4 M_A_CA_0_5 M_A_CA_0_6 M_A_CA_0_7 M_A_CA_0_8 M_A_CA_0_9

M_A_ODT0 M_A_ODT0

M_A_DQ_33 M_A_DQ_37 M_A_DQ_32 M_A_DQ_38 M_A_DQ_36 M_A_DQ_34 M_A_DQ_35 M_A_DQ_39 M_A_DQ_57 M_A_DQ_59 M_A_DQ_56 M_A_DQ_61 M_A_DQ_63 M_A_DQ_62 M_A_DQ_58 M_A_DQ_60 M_A_DQ_55 M_A_DQ_51 M_A_DQ_49 M_A_DQ_48 M_A_DQ_53 M_A_DQ_52 M_A_DQ_50 M_A_DQ_54 M_A_DQ_40 M_A_DQ_41 M_A_DQ_44 M_A_DQ_45 M_A_DQ_42 M_A_DQ_43 M_A_DQ_46 M_A_DQ_47

M_A_DQS_DN_46 M_A_DQS_DP_46

M_A_DQS_DN_76 M_A_DQS_DP_76

M_A_DQS_DN_66 M_A_DQS_DP_66

M_A_DQS_DN_56 M_A_DQS_DP_56

U35A

C11

NC

B11

ZQ_A

E3

NC

E2

ZQ_B

B5

CA0_A

C5

CA1_A

D5

CA2_A

B6

CA3_A

C6

CA4_A

C9

CA5_A

D9

CA6_A

B10

CA7_A

C10

CA8_A

D10

CA9_A

L2

CA0_B

L3

CA1_B

L4

CA2_B

K2

CA3_B

K3

CA4_B

G3

CA5_B

G4

CA6_B

F2

CA7_B

F3

CA8_B

F4

CA9_B

N8

ODT_A

H13

ODT_B

N4

DQ0_A

T5

DQ1_A

R5

DQ2_A

P5

DQ3_A

N5

DQ4_A

T6

DQ5_A

R6

DQ6_A

P6

DQ7_A

T9

DQ8_A

R9

DQ9_A

T10

DQ10_A

R10

DQ11_A

P10

DQ12_A

N10

DQ13_A

T11

DQ14_A

R11

DQ15_A

T2

DQ16_A

R2

DQ17_A

P2

DQ18_A

N2

DQ19_A

T3

DQ20_A

R3

DQ21_A

P3

DQ22_A

N3

DQ23_A

N11

DQ24_A

N12

DQ25_A

P12

DQ26_A

T13

DQ27_A

R13

DQ28_A

P13

DQ29_A

T14

DQ30_A

R14

DQ31_A

N7

DQS0_C_A

P7

DQS0_T_A

N9

DQS1_C_A

P9

DQS1_T_A

R4

DQS2_C_A

T4

DQS2_T_A

R12

DQS3_C_A

T12

DQS3_T_A

CK_C_A CK_T_A

CK_C_B CK_T_B

CKE0_A CKE1_A

CKE0_B CKE1_B

CS0_N_A CS1_N_A

CS0_N_B CS1_N_B

DM0_A DM1_A DM2_A DM3_A

DM0_B DM1_B DM2_B DM3_B

DQ0_B DQ1_B DQ2_B DQ3_B DQ4_B DQ5_B DQ6_B DQ7_B DQ8_B

DQ9_B DQ10_B DQ11_B DQ12_B DQ13_B DQ14_B DQ15_B DQ16_B DQ17_B DQ18_B DQ19_B DQ20_B DQ21_B DQ22_B DQ23_B DQ24_B DQ25_B DQ26_B DQ27_B DQ28_B DQ29_B DQ30_B DQ31_B

DQS0_C_B DQS0_T_B

DQS1_C_B DQS1_T_B

DQS2_C_B DQS2_T_B

DQS3_C_B DQS3_T_B

C8 B8

H2 H3

C7 D7

J3 J4

D6 B7

K4 J2

N6 P8 P4 P11

H14 F13 L14 D14

L15 L16 K13 K14 K15 K16 J15 J16 F14 F15 F16 E13 E14 E15 E16 D13 P15 P16 N14 N15 N16 M13 M14 L13 C13 C14 C15 C16 B13 B14 B15 B16

J13 J14

G13 G14

M15 M16

D15 D16

M_A_CS0_N M_A_CS1_N

M_A_DQ_5 M_A_DQ_0 M_A_DQ_6 M_A_DQ_7 M_A_DQ_1 M_A_DQ_4 M_A_DQ_3 M_A_DQ_2 M_A_DQ_16 M_A_DQ_20 M_A_DQ_21 M_A_DQ_18 M_A_DQ_19 M_A_DQ_22 M_A_DQ_23 M_A_DQ_17 M_A_DQ_30 M_A_DQ_31 M_A_DQ_29 M_A_DQ_27 M_A_DQ_26 M_A_DQ_24 M_A_DQ_28 M_A_DQ_25 M_A_DQ_10 M_A_DQ_11 M_A_DQ_12 M_A_DQ_8 M_A_DQ_15 M_A_DQ_14 M_A_DQ_13 M_A_DQ_9

M_A_DQS_DN_0 6 M_A_DQS_DP_0 6

M_A_DQS_DN_2 6 M_A_DQS_DP_2 6

M_A_DQS_DN_3 6 M_A_DQS_DP_3 6

M_A_DQS_DN_1 6 M_A_DQS_DP_1 6

M_A_CK_DDR0_DN 6 M_A_CK_DDR0_DP 6

M_A_CK_DDR1_DN 6 M_A_CK_DDR1_DP 6

M_A_CKE0 6 M_A_CKE1 6

M_A_CKE2 6 M_A_CKE3 6

M_A_CS0_N 6 M_A_CS1_N 6

+1.2V_DDR

A6 A9 B9 E1 G2 K1

A13 B12 C12 E17 G12 G17 U14 K12 K17 L17 M2 M3 M7 M10 M12 N1 P17 U5 U7 U10 U11

A10 J1

U8 H17

12

C71

12

C122 .047U_0402 _16V7K

DDR_VREF_CA

DDR_0_DQ_ VREF

U35B

A2

VSS0

A3

VSS1

A4

VSS2

A5

VSS3

A8

VSS4

A12

VSS5

A14

VSS6

B1

VSS7

B3

VSS8

B4

VSS9

C1

VSS10

C2

VSS11

C4

VSS12

D1

VSS13

D2

VSS14

D3

VSS15

D4

VSS16

D12

VSS17

D17

VSS18

E5

VSS19

E6

VSS20

E7

VSS21

E8

VSS22

E9

VSS23

E10

VSS24

E11

VSS25

E12

VSS26

F1

VSS27

F5

VSS28

F12

VSS29

F17

VSS30

G1

VSS31

G5

VSS32

G15

VSS33

@

VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67

G16 H5 H12 H15 J5 K5 L5 L12 M1 M4 M5 M6 M8 M11 M17 N13 N17 P1 P14 R7 R8 R16 R17 T7 T15 T17 U4 U6 U9 U12 U13 U15 U16 J17

@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

2041/09/08 2013/10/28

Compal Secre t Data

Deciphered Date

2

Compal Electron ics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electron ics, Inc.

P18-LPDDRIII Channel A

LA-C791P

1

of

18 66Friday, Nove mber 27, 201 5

1.0

5

4

3

2

1

M_B_DQ_[0..6 3]6

D D

M_B_CA_0_[0. .9]6

M_B_CA_1_[0. .9]6

C C

B B

240_020 1_1%

R341

12

R365 240_020 1_1%

M_B_ODT06

M_B_CA_0_0 M_B_CA_0_1 M_B_CA_0_2 M_B_CA_0_3 M_B_CA_0_4 M_B_CA_0_5 M_B_CA_0_6 M_B_CA_0_7 M_B_CA_0_8 M_B_CA_0_9

M_B_CA_1_0 M_B_CA_1_1 M_B_CA_1_2 M_B_CA_1_3 M_B_CA_1_4 M_B_CA_1_5 M_B_CA_1_6 M_B_CA_1_7 M_B_CA_1_8 M_B_CA_1_9

M_B_ODT0 M_B_ODT0

M_B_DQ_16 M_B_DQ_20 M_B_DQ_23 M_B_DQ_17 M_B_DQ_18 M_B_DQ_22 M_B_DQ_19 M_B_DQ_21 M_B_DQ_57 M_B_DQ_61 M_B_DQ_58 M_B_DQ_60 M_B_DQ_56 M_B_DQ_63 M_B_DQ_62 M_B_DQ_59 M_B_DQ_50 M_B_DQ_54 M_B_DQ_53 M_B_DQ_51 M_B_DQ_55 M_B_DQ_52 M_B_DQ_48 M_B_DQ_49 M_B_DQ_24 M_B_DQ_29 M_B_DQ_28 M_B_DQ_31 M_B_DQ_25 M_B_DQ_26 M_B_DQ_30 M_B_DQ_27

M_B_DQS_DN_26 M_B_DQS_DP_26

M_B_DQS_DN_76 M_B_DQS_DP_76

M_B_DQS_DN_66 M_B_DQS_DP_66

M_B_DQS_DN_36 M_B_DQS_DP_36

U33A

C11

NC

B11

ZQ_A

E3

NC

E2

ZQ_B

B5

CA0_A

C5

CA1_A

D5

CA2_A

B6

CA3_A

C6

CA4_A

C9

CA5_A

D9

CA6_A

B10

CA7_A

C10

CA8_A

D10

CA9_A

L2

CA0_B

L3

CA1_B

L4

CA2_B

K2

CA3_B

K3

CA4_B

G3

CA5_B

G4

CA6_B

F2

CA7_B

F3

CA8_B

F4

CA9_B

N8

ODT_A

H13

ODT_B

N4

DQ0_A

T5

DQ1_A

R5

DQ2_A

P5

DQ3_A

N5

DQ4_A

T6

DQ5_A

R6

DQ6_A

P6

DQ7_A

T9

DQ8_A

R9

DQ9_A

T10

DQ10_A

R10

DQ11_A

P10

DQ12_A

N10

DQ13_A

T11

DQ14_A

R11

DQ15_A

T2

DQ16_A

R2

DQ17_A

P2

DQ18_A

N2

DQ19_A

T3

DQ20_A

R3

DQ21_A

P3

DQ22_A

N3

DQ23_A

N11

DQ24_A

N12

DQ25_A

P12

DQ26_A

T13

DQ27_A

R13

DQ28_A

P13

DQ29_A

T14

DQ30_A

R14

DQ31_A

N7

DQS0_C_A

P7

DQS0_T_A

N9

DQS1_C_A

P9

DQS1_T_A

R4

DQS2_C_A

T4

DQS2_T_A

R12

DQS3_C_A

T12

DQS3_T_A

CK_C_A CK_T_A

CK_C_B CK_T_B

CKE0_A CKE1_A

CKE0_B CKE1_B

CS0_N_A CS1_N_A

CS0_N_B CS1_N_B

DM0_A DM1_A DM2_A DM3_A

DM0_B DM1_B DM2_B DM3_B

DQ0_B DQ1_B DQ2_B DQ3_B DQ4_B DQ5_B DQ6_B DQ7_B DQ8_B

DQ9_B DQ10_B DQ11_B DQ12_B DQ13_B DQ14_B DQ15_B DQ16_B DQ17_B DQ18_B DQ19_B DQ20_B DQ21_B DQ22_B DQ23_B DQ24_B DQ25_B DQ26_B DQ27_B DQ28_B DQ29_B DQ30_B DQ31_B

DQS0_C_B DQS0_T_B

DQS1_C_B DQS1_T_B

DQS2_C_B DQS2_T_B

DQS3_C_B DQS3_T_B

C8 B8

H2 H3

C7 D7

J3 J4

D6 B7

K4 J2

N6 P8 P4 P11

H14 F13 L14 D14

L15 L16 K13 K14 K15 K16 J15 J16 F14 F15 F16 E13 E14 E15 E16 D13 P15 P16 N14 N15 N16 M13 M14 L13 C13 C14 C15 C16 B13 B14 B15 B16

J13 J14

G13 G14

M15 M16

D15 D16

M_B_CS0_N M_B_CS1_N

M_B_DQ_35 M_B_DQ_38 M_B_DQ_34 M_B_DQ_33 M_B_DQ_32 M_B_DQ_37 M_B_DQ_36 M_B_DQ_39 M_B_DQ_6 M_B_DQ_4 M_B_DQ_5 M_B_DQ_1 M_B_DQ_3 M_B_DQ_2 M_B_DQ_7 M_B_DQ_0 M_B_DQ_14 M_B_DQ_15 M_B_DQ_12 M_B_DQ_8 M_B_DQ_11 M_B_DQ_10 M_B_DQ_9 M_B_DQ_13 M_B_DQ_42 M_B_DQ_43 M_B_DQ_41 M_B_DQ_40 M_B_DQ_47 M_B_DQ_46 M_B_DQ_45 M_B_DQ_44

M_B_CK_DDR1_DN 6 M_B_CK_DDR1_DP 6

M_B_CK_DDR0_DN 6 M_B_CK_DDR0_DP 6

M_B_CKE2 6 M_B_CKE3 6

M_B_CKE0 6 M_B_CKE1 6

M_B_CS0_N 6 M_B_CS1_N 6

M_B_DQS_DN_4 6

M_B_DQS_DP_4 6

M_B_DQS_DN_0 6

M_B_DQS_DP_0 6

M_B_DQS_DN_1 6

M_B_DQS_DP_1 6

M_B_DQS_DN_5 6

M_B_DQS_DP_5 6

+1.2V_DDR

+1.8V_MEM

U33C

A15

VDD1_0

A16

VDD1_1

B2

VDD1_2

R1

VDD1_3

T1

VDD1_4

T16

VDD1_5

A7

VDD2_0

A11

VDD2_1

B17

VDD2_2

C3

VDD2_3

C17

VDD2_4

H1

VDD2_5

H16

VDD2_6

L1

VDD2_7

R15

VDD2_8

T8

VDD2_9

U2

VDD2_10

U3

VDD2_11

A1

NC0

A17

NC1

D8

NC2

D11

NC3

E4

NC4

H4

NC5

J12

NC6

M9

NC7

U1

NC8

U17

NC9

@

VDDCA0 VDDCA1 VDDCA2 VDDCA3 VDDCA4 VDDCA5

VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20

VREFCA_A VREFCA_B

VREFDQ_A VREFDQ_B

.047U_0402 _16V7K

+1.2V_DDR

A6 A9 B9 E1 G2 K1

A13 B12 C12 E17 G12 G17 U14 K12 K17 L17 M2 M3 M7 M10 M12 N1 P17 U5 U7 U10 U11

A10 J1

U8 H17

12

C226

DDR_VREF_CA

DDR_1_DQ_ VREF

12

C268 .047U_0402 _16V7K

U33B

A2

VSS0

A3

VSS1

A4

VSS2

A5

VSS3

A8

VSS4

A12

VSS5

A14

VSS6

B1

VSS7

B3

VSS8

B4

VSS9

C1

VSS10

C2

VSS11

C4

VSS12

D1

VSS13

D2

VSS14

D3

VSS15

D4

VSS16

D12

VSS17

D17

VSS18

E5

VSS19

E6

VSS20

E7

VSS21

E8

VSS22

E9

VSS23

E10

VSS24

E11

VSS25

E12

VSS26

F1

VSS27

F5

VSS28

F12

VSS29

F17

VSS30

G1

VSS31

G5

VSS32

G15

VSS33

@

VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67

G16 H5 H12 H15 J5 K5 L5 L12 M1 M4 M5 M6 M8 M11 M17 N13 N17 P1 P14 R7 R8 R16 R17 T7 T15 T17 U4 U6 U9 U12 U13 U15 U16 J17

@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

2041/09/08 2013/10/28

Compal Secre t Data

Deciphered Date

2

Compal Electron ics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electron ics, Inc.

P19-LPDDRIII Channel B

LA-C791P

1

of

19 66Friday, Nove mber 27, 201 5

1.0

5

4

3

2

1

+1.2V_DDR

M3 M1

D D

All VREF traces should have 10 mil trace width

Place the VREF voltage divider as close as possible to the LPDDR3 x64 memory down DREM devices

+V_DDR_0_DQ _VREF6

1

C76

0.022U_040 2_16V7K~D

2

12

R77

24.9_02 01_1%

1 2

10_0201 _1%

R66

M3 M1

R75

+V_DDR_1_DQ _VREF6

C C

+1.8V_MEM

1

C243

10U_0402_6 .3V6M

2

1

C108

10U_0402_6 .3V6M

2

1

C67

10U_0402_6 .3V6M

2

1

C251 10U_0402_6 .3V6M

2

1

C86

0.022U_040 2_16V7K~D

2

12

R102

24.9_02 01_1%

1 2

10_0201 _1%

1

C270

10U_0402_6 .3V6M

2

12

+1.2V_DDR

12

R64

8.2K_020 1_1%

R71

8.2K_020 1_1%

R76

8.2K_020 1_1%

R74

8.2K_020 1_1%

1

C107 10U_0402_6 .3V6M

2

DDR_0_DQ_ VREF

DDR_1_DQ_ VREF

1

C120 10U_0402_6 .3V6M

2

1

C225

10U_0402_6 .3V6M

2

M3 M1

+V_DDR_VREF_C A6

1

C124

0.022U_040 2_16V7K~D

2

12

R125

24.9_02 01_1%

1 2

R120

4.99_04 02_1%

+1.2V_DDR

12

R119

8.2K_020 1_1%

R118

8.2K_020 1_1%

DDR_VREF_CA

B B

A A

5

+1.2V_DDR

1

C282

10U_0402_6 .3V6M

2

1

C246

10U_0402_6 .3V6M

2

1

C229

10U_0402_6 .3V6M

2

1

C254

10U_0402_6 .3V6M

2

1

C256

10U_0402_6 .3V6M

2

1

C227

10U_0402_6 .3V6M

2

4

1

C258 10U_0402_6 .3V6M

2

1

C252 10U_0402_6 .3V6M

2

1

C271

10U_0402_6 .3V6M

2

1

C276

10U_0402_6 .3V6M

2

1

C247 10U_0402_6 .3V6M

2

1

C240 10U_0402_6 .3V6M

2

1

C260 10U_0402_6 .3V6M

2

1

C285 10U_0402_6 .3V6M

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

1

C283

10U_0402_6 .3V6M

2

1

C269

10U_0402_6 .3V6M

2

2041/09/08 2013/10/28

1

C284 10U_0402_6 .3V6M

2

1

C259 10U_0402_6 .3V6M

2

Compal Secre t Data

Deciphered Date

2

1

C232

10U_0402_6 .3V6M

2

1

C244

10U_0402_6 .3V6M

2

1

C230 10U_0402_6 .3V6M

2

1

C245 10U_0402_6 .3V6M

2

1

C228 10U_0402_6 .3V6M

2

1

C253 10U_0402_6 .3V6M

2

Title

P20-DD R Vref/Decoupling

Size Document Number Rev

LA-C791P

Date: Sheet

Date: Sheet of

1

C248

10U_0402_6 .3V6M

2

1

C237

10U_0402_6 .3V6M

2

Compal Electron ics, Inc.

20 66Friday, Nove mber 27, 201 5

1

20 66Friday, Nove mber 27, 201 5

of

1.0

Compal LA-C791P Schematics Rev1.0

Specifications and Main Features

Frequently Asked Questions

User Manual