Compal LA-C581P Schematics Rev1.0

A

B

C

D

E

1

Compal Confidential

2

STORM M/B Schematic

LA-C581P

Rev: 1.0_D

3

2015.08.13

2

3

4

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

COVER PAGE

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet

E

1102Thursday, August 13, 2015

4

0.5

of

5

STORM Block-Diagram

4

3

2

1

eDP

DDI1

HDA

P.27

2 Lane

4 Lane

P.54

DMIC

P.51

Audio Codec

P.50

eDP Conn.

D

P.26

mDP Conn.

2-Ch. SPK Conn.

Combo Jack Conn.

One Channel

USB 2.0

USB3.0

SODIMM DDR4 2133MHz

USB 3.0 Conn AOU5

P.56

P.22

D

USB 3.0

USB 3.0 Conn.

P.32

ALS

Sub board

C

Mux

P.28

PCI-E

DDI2

Intel Skylake U-Processor

USB2.0

I2C

4 Lane

USB 2.0

C

Pro Link

HDMI Conn.

P.57

4 Lane

P.30

4 Lane

Mux

P.29

M.2 Conn.

WLAN & BT

PCIEx1 USB 2.0(BT)

P.46

PCIEx1

P.34

MDI

WiGig

Intel GLAN

USB3.0/SSIC

Micro SIM

B

P.46

Micro SD

Card Reader

Slot Conn.

P.48

M.2 Conn.

WWAN

Card Reader

USB 2.0

P.46

PCIEx1

P.47

Antenna

I2C

A

P-sensor

(WiGig)PCIEx1

(WLAN)

Accelerometer(2)

P.26

Think Engine

P.67 - 68

SPI

BIOS ROM

16M

P.21

P.56

LPC

I2C

EC

P.58 - 60

Click Pad

Track Point

P.62

P.61

P.3 - 18

SPI

Int.KBD

TPM

P.61

LID

P.56

USB2.0

P.65

SMBUS

DMIC

FPR

P.49

Touch Panel

P.26

Camera & DMIC

Smart Card

NFC

P.62

Accelerometer & Gyro

Accelerometer(1)

P.26

P.49

PCIEx3

SATA/PCIEx1

eCompass

P.26

B

P.56

M.2 Conn.

SSD [M.2 2280]

P.31

A

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

BLOCK DIAGRAM

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet

1

2102Thursday, August 13, 2015

0.5

of

5

www.vinaﬁx.vn

4

3

2

1

D

VCCCPUIO

2

R5

24.9_0201_1%

1

U58A

DDIP1_0N[27]

DDIP1_0P[27]

DDIP1_1N[27]

C

TAB LE : F u nc t i o nal Str a p

DDPB_CTRLDATA

DDIP1_1P[27]

DDIP1_2N[27]

DDIP1_2P[27]

DDIP1_3N[27]

DDIP1_3P[27]

DDIP2_0N[28]

DDIP2_0P[28]

DDIP2_1N[28]

DDIP2_1P[28]

DDIP2_2N[28]

DDIP2_2P[28]

DDIP2_3N[28]

DDIP2_3P[28]

DDIP1_CTRLCLK[27]

DDIP1_CTRLDATA[27]

DDIP2_CTRLCLK[28]

DDIP2_CTRLDATA[28]

HIGH Port B is detected.

DDIP1_0N

DDIP1_0P

DDIP1_1N

DDIP1_1P

DDIP1_2N

DDIP1_2P

DDIP1_3N

DDIP1_3P

DDIP2_0N

DDIP2_0P

DDIP2_1N

DDIP2_1P

DDIP2_2N

DDIP2_2P

DDIP2_3N

DDIP2_3P

DDIP1_CTRLCLK

DDIP1_CTRLDATA

DDIP2_CTRLCLK

DDIP2_CTRLDATA

EDP_COMP

LOW Port B is not detected.

CPU@

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKL-U_BGA1356

DDPC_CTRLDATA

B

HIGH Port C is detected.

SKL-U

DDI

DISPLAY SI DEBANDS

1 OF 20

EDP

EDP_TXN[0]

EDP_TXP[0]

EDP_TXN[1]

EDP_TXP[1]

EDP_TXN[2]

EDP_TXP[2]

EDP_TXN[3]

EDP_TXP[3]

EDP_AUXN

EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN

DDI1_AUXP

DDI2_AUXN

DDI2_AUXP

DDI3_AUXN

DDI3_AUXP

GPP_E13/DDPB_HPD0

GPP_E14/DDPC_HPD1

GPP_E15/DDPD_HPD2

GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

C47

C46

D46

C45

A45

B45

A47

B47

E45

F45

B52

G50

F50

E48

F48

G46

F46

L9

L7

L6

N9

L10

R12

R11

U13

R433

100K_0201_5%

2

1

R138

100K_0201_5%

EDP_TXN0

EDP_TXP0

EDP_TXN1

EDP_TXP1

EDP_AUXN

EDP_AUXP

DDIP1_AUXN

DDIP1_AUXP

DDIP2_AUXN

DDIP2_AUXP

DDIP1_HPD

DDIP2_HPD

2

R8 100K_0201_5%

1

EDP_TXN0 [26]

EDP_TXP0 [26]

EDP_TXN1 [26]

EDP_TXP1 [26]

EDP_AUXN [26]

EDP_AUXP [26]

DDIP1_AUXN [27]

DDIP1_AUXP [27]

DDIP2_AUXN [28]

DDIP2_AUXP [28]

DDIP1_HPD [27]

DDIP2_HPD [28]

EDP_HPD [26]

VGA_BLON [58]

PANEL_BKLT_CTRL [26]

PANEL_POWER_ON [68]

D

C

B

LOW Port C is not detected.

A

5

A

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU(1/16) : DDI/EDP

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet

1

3102Thursday, August 13, 2015

0.5

of

5

M_A_DQ[63:0][22]

D D

TAB LE

Interleave Non-Interleave

DDR0_DQ[0]

AL71

DDR0_DQ[1]

AL68

DDR0_DQ[2]

AN68

DDR0_DQ[3]

AN69

DDR0_DQ[4]

AL70

DDR0_DQ[5]

AL69

DDR0_DQ[6]

AN70

DDR0_DQ[7]

AN71

DDR0_DQ[8]

AR70

DDR0_DQ[9]

AR68

Block 0

C C

Block 2

Block 4

B B

Block 6

A A

AU71 AU68 AR71 AR69 AU70 AU69

BB65 AW65 AW63 AY6 3 BA65 AY6 5 BA63 BB63 BA61 AW61 BB59 AW59 BB61 AY6 1 BA59 AY5 9

AY3 9 AW39 AY3 7 AW37 BB39 BA39 BA37 BB37 AY3 5 AW35 AY3 3 AW33 BB35 BA35 BA33 BB33

AY3 1 AW31 AY2 9 AW29 BB31 BA31 BA29 BB29 AY2 7 AW27 AY2 5 AW25 BB27 BA27 BA25 BB25

DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15]

DDR0_DQ[16] DDR0_DQ[17] DDR0_DQ[18] DDR0_DQ[19] DDR0_DQ[20] DDR0_DQ[21] DDR0_DQ[22] DDR0_DQ[23] DDR0_DQ[24] DDR0_DQ[25] DDR0_DQ[26] DDR0_DQ[27] DDR0_DQ[28] DDR0_DQ[29] DDR0_DQ[30] DDR0_DQ[31]

DDR0_DQ[32] DDR0_DQ[33] DDR0_DQ[34] DDR0_DQ[35] DDR0_DQ[36] DDR0_DQ[37] DDR0_DQ[38]

for PE Old_Li

DDR0_DQ[39] DDR0_DQ[40] DDR0_DQ[41] DDR0_DQ[42] DDR0_DQ[43] DDR0_DQ[44] DDR0_DQ[45] DDR0_DQ[46] DDR0_DQ[47]

DDR0_DQ[48] DDR0_DQ[49] DDR0_DQ[50] DDR0_DQ[51] DDR0_DQ[52] DDR0_DQ[53] DDR0_DQ[54] DDR0_DQ[55] DDR0_DQ[56] DDR0_DQ[57] DDR0_DQ[58] DDR0_DQ[59] DDR0_DQ[60] DDR0_DQ[61] DDR0_DQ[62] DDR0_DQ[63]

DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15]

DDR0_DQ[32] DDR0_DQ[33] DDR0_DQ[34] DDR0_DQ[35] DDR0_DQ[36] DDR0_DQ[37] DDR0_DQ[38] DDR0_DQ[39] DDR0_DQ[40] DDR0_DQ[41] DDR0_DQ[42] DDR0_DQ[43] DDR0_DQ[44] DDR0_DQ[45] DDR0_DQ[46] DDR0_DQ[47]

DDR1_DQ[0] DDR1_DQ[1] DDR1_DQ[2] DDR1_DQ[3] DDR1_DQ[4] DDR1_DQ[5] DDR1_DQ[6] DDR1_DQ[7] DDR1_DQ[8] DDR1_DQ[9] DDR1_DQ[10] DDR1_DQ[11] DDR1_DQ[12] DDR1_DQ[13] DDR1_DQ[14] DDR1_DQ[15]

DDR1_DQ[32] DDR1_DQ[33] DDR1_DQ[34] DDR1_DQ[35] DDR1_DQ[36] DDR1_DQ[37] DDR1_DQ[38] DDR1_DQ[39] DDR1_DQ[40] DDR1_DQ[41] DDR1_DQ[42] DDR1_DQ[43] DDR1_DQ[44] DDR1_DQ[45] DDR1_DQ[46] DDR1_DQ[47]

4

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

TAB LE

AL71

AL68 AN68 AN69

AL70

AL69 AN70 AN71 AR70 AR68 AU71 AU68 AR71 AR69 AU70 AU69 BB65

AW65 AW63

AY63 BA65 AY65 BA63 BB63 BA61

AW61

BB59

AW59

BB61 AY61 BA59 AY59 AY39

AW39

AY37

AW37

BB39 BA39 BA37 BB37 AY35

AW35

AY33

AW33

BB35 BA35 BA33 BB33 AY31

AW31

AY29

AW29

BB31 BA31 BA29 BB29 AY27

AW27

AY25

AW25

BB27 BA27 BA25 BB25

Block 0

Block 2

Block 4

Block 6

U58B

CPU@

DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15] DDR0_DQ[16]/DDR0_DQ[32] DDR0_DQ[17]/DDR0_DQ[33] DDR0_DQ[18]/DDR0_DQ[34] DDR0_DQ[19]/DDR0_DQ[35] DDR0_DQ[20]/DDR0_DQ[36] DDR0_DQ[21]/DDR0_DQ[37] DDR0_DQ[22]/DDR0_DQ[38] DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQ[27]/DDR0_DQ[43] DDR0_DQ[28]/DDR0_DQ[44] DDR0_DQ[29]/DDR0_DQ[45] DDR0_DQ[30]/DDR0_DQ[46] DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQ[32]/DDR1_DQ[0] DDR0_DQ[33]/DDR1_DQ[1] DDR0_DQ[34]/DDR1_DQ[2] DDR0_DQ[35]/DDR1_DQ[3] DDR0_DQ[36]/DDR1_DQ[4] DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQ[61]/DDR1_DQ[45] DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQ[63]/DDR1_DQ[47]

SKL-U_BGA1356

AM70 AM69 AT6 9 AT7 0

BA64 AY6 4 AY6 0 BA60

BA38 AY3 8 AY3 4 BA34

BA30 AY3 0 AY2 6 BA26

SKL-U

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

2 OF 20

Interleave Non-Interleave

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_DQSN[2] DDR0_DQSP[2] DDR0_DQSN[3] DDR0_DQSP[3]

DDR0_DQSN[4] DDR0_DQSP[4] DDR0_DQSN[5] DDR0_DQSP[5]

DDR0_DQSN[6] DDR0_DQSP[6] DDR0_DQSN[7] DDR0_DQSP[7]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_DQSN[4] DDR0_DQSP[4] DDR0_DQSN[5] DDR0_DQSP[5]

DDR1_DQSN[0] DDR1_DQSP[0] DDR1_DQSN[1] DDR1_DQSP[1]

DDR1_DQSN[4] DDR1_DQSP[4] DDR1_DQSN[5] DDR1_DQSP[5]

3

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54

AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52

AM70 AM69 AT69 AT70 BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26

AW50 AT52

AY67 AY68 BA67

AW67

DDR_PG_CTRL

-M_A_DDRCLK0_933M M_A_DDRCLK0_933M

-M_A_DDRCLK1_933M M_A_DDRCLK1_933M

M_A_CKE0 M_A_CKE1

-M_A_CS0

-M_A_CS1 M_A_ODT0 M_A_ODT1

M_A_A5 M_A_A9 M_A_A6 M_A_A8 M_A_A7

M_A_A12 M_A_A11

-M_A_ACT M_A_BG1

M_A_A13 M_A_A15 M_A_A14 M_A_A16

M_A_A2

M_A_A10 M_A_A1 M_A_A0 M_A_A3 M_A_A4

-M_A_DQS0 M_A_DQS0

-M_A_DQS1 M_A_DQS1

-M_A_DQS2 M_A_DQS2

-M_A_DQS3 M_A_DQS3

-M_A_DQS4 M_A_DQS4

-M_A_DQS5 M_A_DQS5

-M_A_DQS6 M_A_DQS6

-M_A_DQS7 M_A_DQS7

1 2

@

R1858 10K_0201_5%

-M_A_DDRCLK0_933M [22] M_A_DDRCLK0_933M [22]

-M_A_DDRCLK1_933M [22] M_A_DDRCLK1_933M [22]

M_A_CKE0 [22] M_A_CKE1 [22]

-M_A_CS0 [22]

-M_A_CS1 [22] M_A_ODT0 [22] M_A_ODT1 [22]

VCC1R2A

M_A_BG0

M_A_BS0

M_A_BS1

-M_A_ALERT [22] M_A_PARITY [22]

M_A_VREF_CA_CPU [22]

VCC3M

R1838 100K_0201_5%

1 2

13

2

M_A_A[16:0] [22]

-M_A_DQS[7:0] [22]

M_A_DQS[7:0] [22]

DDR_VTT_PG_CTRL

Q170 DTC015TMT2L_VMT3

M_A_BG0 [22]

-M_A_ACT [22] M_A_BG1 [22]

M_A_BS0 [22]

M_A_BS1 [22]

DDR_VTT_PG_CTRL [83,84]

TAB LE

BA51 BB54 BA52 AY5 2 AW52 AY5 5 AW54 BA54 BA55 AY5 4

AU46 AU48 AT4 6 AU50 AU52 AY5 1 AT4 8 AT5 0 BB50 AY5 0 BA50 BB52

DDR3L LPDDR3

DDR0_MA[5] DDR0_MA[9] DDR0_MA[6] DDR0_MA[8] DDR0_MA[7] DDR0_BA[2] DDR0_MA[12] DDR0_MA[11] DDR0_MA[15] DDR0_MA[14]

DDR0_MA[13]

DDR0_CAS# DDR0_WE#

DDR0_RAS# DDR0_BA[0] DDR0_MA[2] DDR0_BA[1] DDR0_MA[10] DDR0_MA[1] DDR0_MA[0] DDR0_MA[3] DDR0_MA[4]

DDR0_CAA[0] DDR0_CAA[1] DDR0_CAA[2] DDR0_CAA[3] DDR0_CAA[4] DDR0_CAA[5] DDR0_CAA[6] DDR0_CAA[7] DDR0_CAA[8] DDR0_CAA[9]

DDR0_CAB[0] DDR0_CAB[1] DDR0_CAB[2] DDR0_CAB[3] DDR0_CAB[4] DDR0_CAB[5] DDR0_CAB[6] DDR0_CAB[7] DDR0_CAB[8] DDR0_CAB[9] Not Used Not Used

1

DDR4

DDR0_MA[5] DDR0_MA[9] DDR0_MA[6] DDR0_MA[8] DDR0_MA[7] DDR0_BG[0] DDR0_MA[12] DDR0_MA[11] DDR0_ACT# DDR0_BG[1]

DDR0_MA[13] DDR0_MA[15] DDR0_MA[14] DDR0_MA[16] DDR0_BA[0]

DDR0_MA[2] DDR0_BA[1] DDR0_MA[10] DDR0_MA[1] DDR0_MA[0] DDR0_MA[3] DDR0_MA[4]

LOGIC

5

LOGIC

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU(2/16) : DDR CHANNEL-A

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

Thursday, August 13, 2015

Date: Sheet of

Thursday, August 13, 2015

Date: Sheet of

Thursday, August 13, 2015

1

4

0.5

102

5

4

3

2

1

D

TAB LE

Interleave Non-Interleave

U58C

DDR1_DQ[0]

AF65

DDR1_DQ[1]

AF64

DDR1_DQ[2]

AK65

DDR1_DQ[3]

AK64

DDR1_DQ[4]

AF66

DDR1_DQ[5]

AF67

DDR1_DQ[6]

AK67

DDR1_DQ[7]

AK66

DDR1_DQ[8]

AF70

DDR1_DQ[9]

AF68

Block 1

C

Block 3

Block 5

B

Block 7

A

AH71 AH68 AF71 AF69 AH70 AH69

AT6 6 AU66 AP65 AN65 AN66 AP66 AT6 5 AU65 AT6 1 AU61 AP60 AN60 AN61 AP61 AT6 0 AU60

AU40 AT4 0 AT3 7 AU37 AR40 AP40 AP37 AR37 AT3 3 AU33 AU30 AT3 0 AR33 AP33 AR30 AP30

AU27 AT2 7 AT2 5 AU25 AP27 AN27 AN25 AP25 AT2 2 AU22 AU21 AT2 1 AN22 AP22 AP21 AN21

DDR1_DQ[10] DDR1_DQ[11] DDR1_DQ[12] DDR1_DQ[13] DDR1_DQ[14] DDR1_DQ[15]

DDR1_DQ[16] DDR1_DQ[17] DDR1_DQ[18] DDR1_DQ[19] DDR1_DQ[20] DDR1_DQ[21] DDR1_DQ[22] DDR1_DQ[23] DDR1_DQ[24] DDR1_DQ[25] DDR1_DQ[26] DDR1_DQ[27] DDR1_DQ[28] DDR1_DQ[29] DDR1_DQ[30] DDR1_DQ[31]

DDR1_DQ[32] DDR1_DQ[33] DDR1_DQ[34] DDR1_DQ[35] DDR1_DQ[36] DDR1_DQ[37] DDR1_DQ[38] DDR1_DQ[39] DDR1_DQ[40] DDR1_DQ[41] DDR1_DQ[42] DDR1_DQ[43] DDR1_DQ[44] DDR1_DQ[45] DDR1_DQ[46] DDR1_DQ[47]

DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63]

DDR0_DQ[16] DDR0_DQ[17] DDR0_DQ[18] DDR0_DQ[19] DDR0_DQ[20] DDR0_DQ[21] DDR0_DQ[22] DDR0_DQ[23] DDR0_DQ[24] DDR0_DQ[25] DDR0_DQ[26] DDR0_DQ[27] DDR0_DQ[28] DDR0_DQ[29] DDR0_DQ[30] DDR0_DQ[31]

DDR0_DQ[48] DDR0_DQ[49] DDR0_DQ[50] DDR0_DQ[51] DDR0_DQ[52] DDR0_DQ[53] DDR0_DQ[54] DDR0_DQ[55] DDR0_DQ[56] DDR0_DQ[57] DDR0_DQ[58] DDR0_DQ[59] DDR0_DQ[60] DDR0_DQ[61] DDR0_DQ[62] DDR0_DQ[63]

DDR1_DQ[16] DDR1_DQ[17] DDR1_DQ[18] DDR1_DQ[19] DDR1_DQ[20] DDR1_DQ[21] DDR1_DQ[22] DDR1_DQ[23] DDR1_DQ[24] DDR1_DQ[25] DDR1_DQ[26] DDR1_DQ[27] DDR1_DQ[28] DDR1_DQ[29] DDR1_DQ[30] DDR1_DQ[31]

DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63]

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKL-U_BGA1356

TAB LE

Block 1

Block 3

Block 5

Block 7

CPU@

AH66 AH65 AG69 AG70

AR66 AR65 AR61 AR60

AT3 8 AR38 AT3 2 AR32

AR25 AR27 AR22 AR21

LOGIC

SKL-U

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]

DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]

DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]

DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2]

DDR1_DQSP[0]/DDR0_DQSP[2]

DDR1_DQSN[1]/DDR0_DQSN[3]

DDR1_DQSP[1]/DDR0_DQSP[3]

DDR1_DQSN[2]/DDR0_DQSN[6]

DDR1_DQSP[2]/DDR0_DQSP[6]

DDR1_DQSN[3]/DDR0_DQSN[7]

DDR1_DQSP[3]/DDR0_DQSP[7]

DDR1_DQSN[4]/DDR1_DQSN[2]

DDR1_DQSP[4]/DDR1_DQSP[2]

DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[5]/DDR1_DQSP[3]

DRAM_RESET#

DDR_RCOMP[0]

DDR CH - B

3 OF 20

DDR_RCOMP[1]

DDR_RCOMP[2]

Interleave Non-Interleave

DDR1_DQSN[0] DDR1_DQSP[0] DDR1_DQSN[1] DDR1_DQSP[1]

DDR1_DQSN[2] DDR1_DQSP[2] DDR1_DQSN[3] DDR1_DQSP[3]

DDR1_DQSN[4] DDR1_DQSP[4] DDR1_DQSN[5] DDR1_DQSP[5]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR0_DQSN[2] DDR0_DQSP[2] DDR0_DQSN[3] DDR0_DQSP[3]

DDR0_DQSN[6] DDR0_DQSP[6] DDR0_DQSN[7] DDR0_DQSP[7]

DDR1_DQSN[2] DDR1_DQSP[2] DDR1_DQSN[3] DDR1_DQSP[3]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

LOGIC

DDR1_CKN[0]

DDR1_CKN[1]

DDR1_CKP[0]

DDR1_CKP[1]

DDR1_CKE[0]

DDR1_CKE[1]

DDR1_CKE[2]

DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1]

DDR1_ODT[0]

DDR1_ODT[1]

DDR1_MA[3]

DDR1_MA[4]

DDR1_DQSN[6]

DDR1_DQSP[6]

DDR1_DQSN[7]

DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR

AN45

AN46

AP45

AP46

AN56

AP55

AN55

AP53

BB42

AY42

BA42

AW42

AY48

AP50

BA48

BB48

AP48

AP52

AN50

AN48

AN53

AN52

BA43

AY43

AY44

AW44

BB44

AY47

BA44

AW46

AY46

BA46

BB46

BA47

AH66

AH65

AG69

AG70

AR66

AR65

AR61

AR60

AT38

AR38

AT32

AR32

AR25

AR27

AR22

AR21

AN43

AP43

AT13

AR18

AT18

AU18

1

R7 121_0201_1%

R84 80.6_0201_1%

R576 100_0201_1%

2

1

2

1

2

VCC1R2A

2

R1726 470_0201_5%

1

-DRAMRST

-DRAMRST [22]

TAB LE

AY4 8 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY4 3 AY4 4 AW44 BB44 AY4 7 BA44 AW46 AY4 6 BA46 BB46 BA47

DDR3L LPDDR3

DDR1_MA[5] DDR1_MA[9] DDR1_MA[6] DDR1_MA[8] DDR1_MA[7] DDR1_BA[2] DDR1_MA[12] DDR1_MA[11] DDR1_MA[15] DDR1_MA[14]

DDR1_MA[13]

DDR1_CAS# DDR1_WE#

DDR1_RAS# DDR1_BA[0] DDR1_MA[2] DDR1_BA[1] DDR1_MA[10] DDR1_MA[1] DDR1_MA[0] DDR1_MA[3] DDR1_MA[4]

DDR1_CAA[0] DDR1_CAA[1] DDR1_CAA[2] DDR1_CAA[3] DDR1_CAA[4] DDR1_CAA[5] DDR1_CAA[6] DDR1_CAA[7] DDR1_CAA[8] DDR1_CAA[9]

DDR1_CAB[0] DDR1_CAB[1] DDR1_CAB[2] DDR1_CAB[3] DDR1_CAB[4] DDR1_CAB[5] DDR1_CAB[6] DDR1_CAB[7] DDR1_CAB[8] DDR1_CAB[9] Not Used Not Used

LOGIC

DDR4

DDR1_MA[5] DDR1_MA[9] DDR1_MA[6] DDR1_MA[8] DDR1_MA[7] DDR1_BG[0] DDR1_MA[12] DDR1_MA[11] DDR1_ACT# DDR1_BG[1]

DDR1_MA[13] DDR1_MA[15] DDR1_MA[14] DDR1_MA[16] DDR1_BA[0]

DDR1_MA[2] DDR1_BA[1] DDR1_MA[10] DDR1_MA[1] DDR1_MA[0] DDR1_MA[3] DDR1_MA[4]

D

C

B

A

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU(3/16) : DDR CHANNEL-B

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet

Thursday, August 13, 2015

Date: Sheet

Thursday, August 13, 2015

Date: Sheet

Thursday, August 13, 2015

1

5

0.5

102

of

5

D D

4

3

2

1

C C

PECI[59]

-PROCHOT[59,71,75]

PECI

-PROCHOT

for PE Old_Li

B B

A A

VCCSTG VCCST VCC1R0_SUS

1 2

R9055 1K_0201_5%

AT16 AU16

D63 A54 C65 C63 A65

C55 D55 B54 C56

A6

A7 BA5 AY5

H66 H65

U58D

CPU@

CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#

CPU MISC

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

SKL-U_BGA1356

SKL-U

4 OF 20

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

JTAGX

1 2

51_0201_5%

R515

@

1 2

51_0201_5%

R541

@ B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

R471

R2

51_0201_5%

1 2

R64 1K_0201_5%

1 2

R85 510_0402_5%

1 2

R2126 49.9_0201_1%

1 2

R2127 49.9_0201_1%

1 2

R2128 49.9_0201_1%

1 2

R2129 49.9_0201_1%

SVT_C_EC002

1 2

51_0201_5%

R530

@

XDP_TCK0 XDP_TDI XDP_TDO XDP_TMS

-XDP_TRST

SVT_C_EC002

XDP_TCK0 [19] XDP_TDI [19] XDP_TDO [19] XDP_TMS [19]

-XDP_TRST [19]

PCH_TCK [19] PCH_TDI [19] PCH_TDO [19] PCH_TMS [19]

-PCH_TRST [19] JTAGX [19]

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU(4/16) : MISC/JTAG

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

Thursday, August 13, 2015

Date: Sheet of

Thursday, August 13, 2015

Date: Sheet of

Thursday, August 13, 2015

1

6

0.5

102

5

D D

TABLE : Funct i onal Stra p

SPI0_MOSI (Boot Halt)

HIGH

Disabled (Default)

Enabled

LOW

TABLE : Funct i onal Stra p

SPI0_MISO (JTAG ODT Diable)

HIGH

Enabled (Default)

Disabled

LOW

VCC3_SUS

C C

@

1 2

R9310 1K_0201_5%

R9311 1K_0201_5%

SPI_CLK[21,65] SPI_MISO_IO1[21,65] SPI_MOSI_IO0[21,65] SPI_IO2[21] SPI_IO3[21]

-SPI_CS0[21]

-SPI_CS2[65]

-NFC_DTCT[62]

for PE Old_Li

CL_CLK_WLAN[46] CL_DATA_WLAN[46]

-CL_RST_WLAN[46]

B B

-KBRC[58]

IRQSER[58,66]

CL_CLK_WLAN CL_DATA_WLAN

-CL_RST_WLAN

2

@RF@

C264 33P_0201_25V8J

1

8.2K_0201_5%

@

R9308 1K_0201_5%

1 2

4

TABLE : Funct i onal Stra p

GPP_C5/SML0ALERT # (LPC or eSPI)

HIGH

eSPI is selected

LOW

LPC is selected (Default) LOGIC

TABLE : Funct i onal Stra p

GPP_C2/SMBALERT# (TLS Conf i dent iali ty)

HIGH

Enable ME Crypto TLS with Conf i dent iali ty

Disable ME Crypto TLS (Default)

LOW

VCC3_SUSVCC3B

@

R272

1 2

10K_0201_5%

1 2

R860

@

R9305 1K_0201_5%

1 2

AW13

AY11

AV2

AW3

AV3

AW2

AU4 AU3 AU2 AU1

M2 M3

J4 V1 V2 M1

G3 G2 G1

U58E

CPU@

SPI - FLASH

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

C LINK

CL_CLK CL_DATA CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

SKL-U_BGA1356

SKL-U

LPC

5 OF 20

3

SMBUS, SMLINK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

2

LOGIC

VCC3_SUS VCC3B

R7 R8 R10

R9 W2 W1

W3 V3 AM7

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9 AW11

R226 1K_0201_5%

1 2

LPCCLK_0 LPCCLK_1

1 2

R107

R106

499_0201_1%

1 2

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

1 2

R193 22_0402_5%

1 2

R220 0_0402_5%@

R394

4.7K_0201_5%

1 2

R397

4.7K_0201_5%

1 2

LPC_AD[3:0] [58,66]

-LPC_FRAME [58,66]

-SUS_STAT [58,66]

LPCCLK_EC_24M [58] LPCCLK_DEBUG_24M [66]

SVT_EC004

2

@RF@

C8520 33P_0201_25V8J

1

8.2K_0201_5%

1 2

R28

SMB_CLK SMB_DATA

SML0_CLK SML0_DATA

EC_SCL2 EC_SDA2

SMB_CLK [66] SMB_DATA [66]

SML0_CLK [34] SML0_DATA [34]

EC_SCL2 [59] EC_SDA2 [59]

-CLKRUN [58,66]

1

TABLE : Funct i onal Stra p

SPI0_IO2 (Consent Strap)

HIGH

Enabled (Default)

Disabled

LOW

TABLE : Funct i onal Stra p

SPI0_IO3 (A0 Personality Strap)

HIGH

A A

5

4

LOW

Disabled (Default)

Enabled

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU(5/16) : LPC/SPI/SMBUS/C-LINK

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

7102Thursday, August 13, 2015

0.5

5

4

3

2

1

1K_0201_5%

1 2

R65

@

AN8 AP7 AP8 AR7

AM5 AN7 AP5 AN5

AB1 AB2

AB3

AD1 AD2 AD3 AD4

AH9

AH10

AH11 AH12

AF11 AF12

TABLE : Funct i onal Stra p

GPP_B22/GSPI1_MOSI (Boot BIOS Dest i nat i on)

HIGH

Boot BIOS from LPC

Boot BIOS from SPI (Default)

LOW

TABLE : Funct i onal Stra p

GPP_B18/GSPI0_MOSI (No Reboot)

HIGH

Enable "No Reboot" Mod e

LOW

Disable "No Reboot" Mod e (Default)

U58F

CPU@

LPSS ISH

GPP_B15/GSPI0_CS# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL

SKL-U_BGA1356

SKL-U

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

6 OF 20

LOGIC

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D15/ISH_UART0_RTS#

GPP_C13/UART1_TXD/ISH_UART1_TXD

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

P2 P3 P4 P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

AC1 AC2 AC3 AB4

AY8 BA8 BB7 BA7 AY7 AW7 AP13

VCC3B VCC3B

1K_0201_5%

1 2

R9263

R9261

R9257

R9262

ISH_I2C1_SDA ISH_I2C1_SCL

VCC3B VCC3B VCC3B

R154

1 2

ISH_GP0 ISH_GP1 ISH_GP2 ISH_GP3 ISH_GP4 ISH_GP5 ISH_GP6

4.7K_0201_5%

R155

1 2

4.7K_0201_5%

R9264 0_0201_5% R9265 0_0201_5%

R156

4.7K_0201_5%

1 2

ISH_I2C0_SCL ISH_I2C0_SDA ISH_I2C1_SCL ISH_I2C1_SDA

ISH_GP0 ISH_GP1 ISH_GP2 ISH_GP3

ISH_GP4 ISH_GP5 ISH_GP6

1 2 1 2

R9259

4.7K_0201_5%

1 2

R9260

1 2

4.7K_0201_5%

R9256

1 2

4.7K_0201_5%

VCC3B

R9258

1 2

4.7K_0201_5%

ISH_I2C0_SDA [26,56]

ISH_I2C0_SCL [26,56]

I2C_DATA_GSENSE_SH [60]

I2C_CLK_GSENSE_SH [60]

WWAN_CFG2 [46] WWAN_CFG3 [46]

ISH_GP0 [26] ISH_GP1 [26] ISH_GP2 [26,56]

JISH1

ME@

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

GND

20

GND

ACES_50506-01841-P01

-LID_CLOSE

2 1

D801 RB521CM-30T2R_SOD923-2

-TABLET_MODE

2 1

D802 RB521CM-30T2R_SOD923-2

-LID_CLOSE [26,56,59]

-TABLET_MODE [56,60]

10K_0201_5%

1 2

-MIC_HW_EN

1 2

10K_0201_5%

1 2

R884

R961 0_0201_5%

VCC3_SUS

R2340

D D

NFC_ON[62] NFC_INT[62]

C C

-EC_SCI[58]

-EC_WAKE[58]

-WWAN_RESET[46]

-INT_MIC_DTCT[26]

WWAN_CFG0[46] WWAN_CFG1[46]

for PE Old_Li

B B

A A

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU(6/16) : LPSS/ISH

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

8102Thursday, August 13, 2015

0.5

5

D D

C C

1 2

2

1

DDI_PRIORITY1 DDI_PRIORITY2

PCH_SPKR

C38 47P_0201_25V8J

R423 33_0201_5%

1 2

R9323 0_0201_5%RF@

1 2

R74 33_0201_5%

1 2

R456 33_0201_5%

HDA_SYNC[50] HDA_BCLK[50] HDA_SDO[50] HDA_SDIN0[50]

-HDA_RST[50]

DDI_PRIORITY1[29] DDI_PRIORITY2[28]

PCH_SPKR[55]

for PE Old_Li

B B

4

VCC3_SUS

1 2

R846

VCC3_SUS VCC3_SUS

R60 33_0201_5%

1K_0201_5%

1 2

R1009 1K_0201_5%

PLACE ON TOP SIDE

0_0603_5%

1 2

R566

@

TP901@TP900

TEST PAD

BOTTOM SIDE DO NOT MOVE AFTER FIX

@

3

TABLE : Funct i onal Stra p

HDA_SDO/I2S0_TXD Flash Descriptor Security Override

HIGH

Disable Flash Descriptor Security (Override)

LOW

Enable Flash Descriptor Security (Default)

U58G

CPU@

AUDIO

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

SKL-U_BGA1356

TABLE : Funct i onal Stra p

GPP_B14/SPKR (Top Swap Override)

HIGH

Enable "Top Swap" Mode

LOW

Disable "Top Swap" Mode (Default) LOGIC

SKL-U

7 OF 20

SDIO/SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

2

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

R2131

200_0201_1%

1 2

-SC_DTCT [49]

1

A A

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU : AUDIO/SDXC

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

9102Thursday, August 13, 2015

0.5

5

4

3

2

1

D D

C C

I/O

Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Port 16

for PE Old_Li

B B

A A

Flexible I/O Conf i gurat i on PCIe Port Assignment

High Speed Signals

USB3 1 USB3 2/SSIC USB3 3 USB3 4 USB3 5/PCIE 1 USB3 6/PCIE 2 PCIE 3 (GbE) PCIE 4 (GbE) PCIE 5 (GbE) PCIE 6 PCIE 7/SATA 0 PCIE 8/SATA 1A PCIE 9 (GbE) PCIE 10 (GbE) PCIE 11/SATA 1B PCIE 12/SATA 2

Conf i gura t i on Net Name

USB3 1

SSIC USB3 3 USB3 4 PCIE 1 USB3 6 PCIE 3 PCIE 4 PCIE 5 (x4) PCIE 6 (x4) PCIE 7 (x4) GPIO STRAP PCIE 9 (x4) PCIE 10 (x4) PCIE 11 (x4) PCIE 12 (x4)

PCIE4_L0_SATA1_RXN[31] PCIE4_L0_SATA1_RXP[31] PCIE4_L0_SATA1_TXN[31] PCIE4_L0_SATA1_TXP[31]

USB3P0

SSIC USB3P2 USB3P3 PCIE0 USB3P5 PCIE2 PCIE3 PCIE4_L3 PCIE4_L2 PCIE4_L1 PCIE4_L0_ SATA1 PCIE5_L0 NA NA NA

PCIE0_RXN[47] PCIE0_RXP[47] PCIE0_TXN[47] PCIE0_TXP[47]

PCIE2_RXN[46] PCIE2_RXP[46] PCIE2_TXN[46] PCIE2_TXP[46]

PCIE3_RXN[34] PCIE3_RXP[34] PCIE3_TXN[34] PCIE3_TXP[34]

PCIE4_L3_RXN[31] PCIE4_L3_RXP[31] PCIE4_L3_TXN[31] PCIE4_L3_TXP[31]

PCIE4_L2_RXN[31] PCIE4_L2_RXP[31] PCIE4_L2_TXN[31] PCIE4_L2_TXP[31]

PCIE4_L1_RXN[31] PCIE4_L1_RXP[31] PCIE4_L1_TXN[31] PCIE4_L1_TXP[31]

PCIE5_L0_RXN[46] PCIE5_L0_RXP[46] PCIE5_L0_TXN[46] PCIE5_L0_TXP[46]

-XDP_PRDY[19]

-XDP_PREQ[19]

-TPM_IRQ[65]

-XDP_PRDY

-XDP_PREQ

-TPM_IRQ

VCC3_SUS

1 2

R2341 10K_0201_5%

R8964

0 1 2 3 4 (x4) 5_L0

0 1A 1B 2

100_0201_1%

1 2

SATA Port Assignment

(PCIE 7) SATA SSD (PCIE 11) (PCIE 12)

Media Card Controller

(USB3 6) M.2 WLAN Slot Port 0 for WLAN GbE PHY PCIe SSD M.2 WLAN Slot Port 1 for WiGig

U58H

CPU@

PCIE/USB3/SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL-U_BGA1356

SKL-U

8 OF 20

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP

USB3_2_TXN/SSIC_1_TXN USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP

USB3_3_TXN/SSIC_2_TXN USB3_3_TXP/SSIC_2_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10

USB2P_10

USB2_COMP

USB2_ID

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6 AG3 AG4

A9 C9 D9 B9

J1 J2 J3

H2 H3 G4

H1

1K_0201_5%

R72

USBCOMP

1 2

R648 10K_0201_5%

@

R77 0_0201_5%

VCC3_SUS

R248 10K_0201_5%

@

1 2

R2308 10K_0201_5%

R2307 10K_0201_5%

113_0201_1%

1 2

R564

SVT_C_EC003

USB3P0_RXN [32] USB3P0_RXP [32] USB3P0_TXN [32] USB3P0_TXP [32]

SSIC_RXN [46] SSIC_RXP [46] SSIC_TXN [46] SSIC_TXP [46]

USB3P2_RXN [32] USB3P2_RXP [32] USB3P2_TXN [32] USB3P2_TXP [32]

USB3P3_RXN [57] USB3P3_RXP [57] USB3P3_TXN [57] USB3P3_TXP [57]

USBP0- [32] USBP0+ [32]

USBP1- [46] USBP1+ [46]

USBP2- [32] USBP2+ [32]

USBP3- [57] USBP3+ [57]

USBP4- [49] USBP4+ [49]

USBP6- [46] USBP6+ [46]

USBP7- [26] USBP7+ [26]

USBP8- [49] USBP8+ [49]

USBP9- [26] USBP9+ [26]

-USB_PORT0_OC0 [32]

-USB_PORT1_OC1 [32]

VCC3_SUS

1 2

R44 10K_0201_5%

-PE_DTCT

USB Port Assignment

USB 3.0 System Port (AOU)

0

M.2 WWAN Slot

1

USB 3.0 System Port

2

ProLink Dock

3

SMART CARD

4

(RESERVED)

5

M.2 WLAN Slot for BT

6

USB Camera

7

Fingerprint Reader

8

Tou ch Pan el

9

USB 3.0 Port Assignment

USB 3.0 System Port (AOU)

0

M.2 WWAN Slot (SSIC)

1

USB 3.0 System Port

2

ProLink Dock

3

(PCIE 1)

4

(RESERVED)

5

SATA1_DEVSLP [31]

-PE_DTCT [31]

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU : PCIE/USB/SATA

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

10 102Thursday, August 13, 2015

0.5

5

D D

C C

4

SKL_ULT

U58I

CPU@

CSI-2

A36 B36 C38 D38 C36 D36 A38 B38

C31 D31 C33 D33 A31 B31 A33 B33

A29 B29 C28 D28 A27 B27 C27 D27

CSI2_DN0 CSI2_DP0 CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3

CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7

CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11

SKL-U_BGA1356

9 OF 20

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

3

C37 D37 C32 D32 C29 D29 B26 A26

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

PLANARID1 PLANARID2 PLANARID3

PLANARID0

2

1

for PE Old_Li

B B

PLANARID0 PLANARID1 PLANARID2 PLANARID3

@

R47

R43

0_0201_5%

1 2

A A

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

@

R48

R113

0_0201_5%

2014/11/04 2016/12/31

1 2

SVT_EC002

Compal Secret Data

Deciphered Date

2

TAB LE

LEVEL

3210

R43 R47 R113 R48

1

NA NA NA NA

ASM ASM ASM ASM

0

TAB LE

PLANARID[3..0]

LEVEL

PDV

0001B

FVT

0010B

SIT

0011B

SIT-R

0100B

SVT

0101B

PLANAR ID

Compal Electronics, Inc.

Title

CPU : CSI-2/EMMC

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

11 102Thursday, August 13, 2015

0.5

5

D D

4

3

2

1

C C

-PCIE0_CLK_100M[47] PCIE0_CLK_100M[47]

-CLKREQ_PCIE0[47]

-PCIE2_CLK_100M[46] PCIE2_CLK_100M[46]

-CLKREQ_PCIE2[46]

-PCIE3_CLK_100M[34] PCIE3_CLK_100M[34]

-CLKREQ_PCIE3[34]

-PCIE4_CLK_100M[31] PCIE4_CLK_100M[31]

-CLKREQ_PCIE4[31]

-PCIE5_CLK_100M[46] PCIE5_CLK_100M[46]

-CLKREQ_PCIE5[46]

for PE Old_Li

B B

A A

U58J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKL-U_BGA1356

CPU@

SKL_ULT

CLOCK SIGNALS

10 OF 20

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

F43 E43

BA17

E37 E35

E42

AM18 AM20

AN18 AM16

SVT_EC003

2.74K_0201_1%

R609

1 2

VCC1R0_SUS

RTCX1 RTCX2

-SRTCRST [20]

-RTCRST [17,20]

SUSCLK_32K [46,58]

SVT_C_EC003

R351 10M_0402_5%

1 2

TXC 9H03280012 KDS 1TJF090DJ1A000B EPSON FC-135R (X1A0001410002)

R308 1M_0201_5%

1 2

R133

@

Y6

32.768KHZ_9PF_9H03280012

1 2

0_0201_5%

1 2

10P_0201_25V8D

1 2

C348

8P_0201_50V8D

1 2

C326

2

C205 9P_0402_50V8D

1

Y5

4

3

NC

OSC

1

2

OSC

24MHZ_8PF_1ZZCAA24000CC0B

KDS 1ZZCAA24000CC0B TXC 8Y24080002 Epson Q 22FA1280027100

NC

2

C206 9P_0402_50V8D

1

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU : CLOCK SIGNALS

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

12 102Thursday, August 13, 2015

0.5

5

4

3

2

1

33_0201_5%

2

C460 100P_0201_25V8J

1

R991

1 2

2

1

MPWRG

33_0201_5%

1 2

R993

C46 100P_0201_25V8J

-PLTRST_NEAR[47]

D D

CPUCORE_PWRGD

2

C8522

@ESD@

100P_0201_50V8J

1

C C

B B

MPWRG BPWRG

2

C8524

@ESD@

100P_0201_50V8J

1

-PLTRST_FAR[31,34,46,58,65,66,67]

-RSMRST

2

C8523

@ESD@

100P_0201_50V8J

1

2

C8525

@ESD@

100P_0201_50V8J

1

-XDP_DBR[17,19]

-RSMRST[19,59]

BPWRG[27,59,66,68]

CPUCORE_PWRGD[19,75]

MPWRG[59,68]

-PCIE_WAKE[46,67]

for PE Old_Li

-LANWAKE[34] LANPHYPC[34]

VCC3M

U73

-SUSWARN

1

NC

2

IN_A

3

GND

VCCST_PWRGD

R21 0_0201_5% R617 0_0201_5% R203 0_0201_5%

R1884 0_0201_5%

5

VCC

4

OUT_Y

TC7SG17FE_SON5

VCC3MVCC3M

1K_0201_5%

1 2

4.7K_0201_5%

1 2

R19

R612

VCC3_SUS VCC1R0_SUS

-PLTRST

1 2 1 2 1 2

1 2

U58K

CPU@

SYSTEM POWER MANAGEMENT

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKL-U_BGA1356

SKL-U

11 OF 20

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS# SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

S3

1

3

2

4

SPVR310100_4P

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

AM10 AM11

-PCH_SLP_SUS

-PCH_SLP_WLAN

-INTRUDER

1000P_0201_25V7K

R646

1M_0201_5%

1 2

2

@

C7

1

1 2

R10 0_0201_5%

VCC3MRTCVCC

10K_0201_5%

@

1 2

R614

-PCH_SLP_S0 [17,80,82,87]

-PCH_SLP_S3 [17,59,67,80]

-PCH_SLP_S4 [17,59,67,84]

-PCH_SLP_S5 [17,67]

-PCH_SLP_SUS [59]

-PCH_SLP_LAN [60]

-PCH_SLP_WLAN [59]

-PCH_SLP_M [17,67]

-PWRSW_EC [59] AC_PRESENT [59]

-BATLOW [60]

-EXT_PWR_GATE [16]

D5

1 2

RB520CM-30T2R VMN2

-INTRUDER_EC

-INTRUDER_EC [60]

R2324 10K_0201_5%

1 2

1

CPUCORE_ON[67,75]

A A

5

CPUCORE_ON

2

Q194 LSK3541G1ET2L_VMT3

3

4

2

R2325 10K_0201_5%

1 2

1

Q195 LSK3541G1ET2L_VMT3

3

VCCST_PWRGD

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU : SYSTEM PM

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

13 102Thursday, August 13, 2015

0.5

5

D D

4

3

2

1

VCCCPUCORE VCCCPUCORE

CPU@

SKL-U

CPU POWER 1 OF 4

12 OF 20

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37 VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VCC_SENSE VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

B63 A63 D64

G20

VCCSTG

VCCCPUCORE

R9 100_0201_5%

1 2

R70 100_0201_5%

1 2

R781

220_0201_5%

1 2

U58L

A30

VCC_A30

A34

VCC_A34

A39

VCC_A39

A44

VCC_A44

AK33

VCC_AK33

AK35

VCC_AK35

AK37

VCC_AK37

AK38

VCC_AK38

AK40

VCC_AK40

AL33

VCC_AL33

AL37

VCC_AL37

AL40

VCC_AL40

C C

AM32 AM33 AM35 AM37 AM38

AK32

AB62

AC63 AE63

AE62 AG62

G30

K32

P62 V62

H63

G61

AL63 AJ62

VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RSVD_K32

RSVD_AK32

VCCOPC_AB62 VCCOPC_P62 VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE VSSOPC_SENSE

VCCEOPIO VCCEOPIO

VCCEOPIO_SENSE VSSEOPIO_SENSE

SKL-U_BGA1356

R374 56_0201_5%

1 2

VCCST

@

R782 100_0201_5%

1 2

R9319 100_0201_5%

1 2

VCC_SENSE VSS_SENSE

-SVID_ALERT SVID_CLK SVID_DATA

VCC_SENSE [75] VSS_SENSE [75]

-SVID_ALERT [75] SVID_CLK [75]

SVID_DATA [75]

for PE Old_Li

B B

A A

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU : CPU POWER (1/2)

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

14 102Thursday, August 13, 2015

0.5

5

4

3

2

1

D D

VCCGFXCORE_I VCCGFXCORE_I

SKL-U

U58M

CPU@

CPU POWER 2 OF 4

A48

VCCGT

AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71

A53 A58 A62 A66

J43 J45 J46 J48 J50 J52 J53 J55 J56 J58 J60 K48 K50 K52 K53 K55 K56 K58 K60 L62 L63 L64 L65 L66 L67 L68 L69 L70

L71 M62 N63 N64 N66 N67 N69

J70

J69

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT_SENSE VSSGT_SENSE

SKL-U_BGA1356

13 OF 20

VCCGTX_SENSE VSSGTX_SENSE

C C

for PE Old_Li

B B

VCCGT_SENSE[75] VSSGT_SENSE[75]

VCCGT_SENSE VSSGT_SENSE

VCCGFXCORE_I

R2152 100_0201_5%

1 2

R2153 100_0201_5%

1 2

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70 VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56

VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58

VCCGTX_AU58

VCCGTX_AU63

VCCGTX_BB57

VCCGTX_BB66

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

VCCST VCCSTG VCCST VCC1R2A VCC1R2A VCC1R2AVCC1R2A

2

1

10U_0402_6.3V6M

VCCCPUIO

C838

C1832

@

VCCSA

R2291 100_0201_5%

1 2

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

C1831

@

22U_0603_6.3V6M

R2290 100_0201_5%

1 2

22U_0603_6.3V6M

C840

@

VCCSAVCCCPUIO

R2155 100_0201_5%

1 2

1

C842

@

R2154 100_0201_5%

1 2

VSSSA_SENSE VCCSA_SENSE

AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51

AL23

A18

A22

K20 K21

2

1

10U_0402_6.3V6M

U58N

VDDQ_AU23 VDDQ_AU28 VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51

VDDQC

VCCST

VCCSTG_A22

VCCPLL_OC

VCCPLL_K20 VCCPLL_K21

SKL-U_BGA1356

10U_0402_6.3V6M

C835

CPU@

CPU POWER 3 OF 4

2

1

10U_0402_6.3V6M

C1184

C1829

C1830

SKL-U

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE VCCSA_SENSE

14 OF 20

2

1

1U_0402_6.3V6K

2

1

1U_0402_6.3V6K

C2422

2

1

0.1U_0201_6.3V6K

C2423

C2424

C2425

VCC1R2A

VCCSTVCCSTG

AM40

VCCQC VCCPLL_OCVCCPLL

2

1

10U_0402_6.3V6M

22U_0603_6.3V6M

C844

@

VCCCPUIO_SENSE [80] VSSCPUIO_SENSE [80]

VSSSA_SENSE [75] VCCSA_SENSE [75]

2

1

0.1U_0201_6.3V6K 1U_0201_6.3V6K

C2426

C2427

C8536

A A

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU : CPU POWER (2/2)

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

15 102Thursday, August 13, 2015

0.5

5

SVT_C_EC005

Short Pattern: R2485, R2486, R2487

D D

C C

VCC3M VCC3M_PCH

VCC1R0_SUS VCC1R0_SUS_PRIM

VCCMPHY_GATE VCCMPHY_GATE_OUT

VCCMPHY_GATE

VCC1R0_SUS

1 2

BLM15EG221SN1D_2P

R2302

2MM

@

R2485

21

Short Pattern

@

R2486

21

Short Pattern

@

R2487

21

Short Pattern

@

VCCMPHY_GATE_PLL

21

@

2

C2447 22U_0603_6.3V6M

1

RF@

L1

VCC1R0_SUS_PLL

RF@

2

C2449

0.1U_0201_6.3V6K

1

@

2

C2446 22U_0603_6.3V6M

1

@

2

C2448 22U_0603_6.3V6M

1

@

2

C2437 1U_0402_6.3V6K

1

NEAR K15

-EXT_PWR_GATE[13]

for PE Old_Li

B B

2

1

VCC3_SUS

4

VCCMPHY_GATE_OUT

C620 1U_0402_6.3V6K

VCC3M_PCH

@

1 2

R796 0_0201_5%

2

C8530

0.1U_0201_6.3V6K

1

VCC3_SUS

1 2

@

R2293 20K_0201_5%

VCC1R0_SUS_PRIMVCC1R0_SUSVCCPCHCORE

SVT_C_EC004

VCC1R0_SUS

AB19 AB20

P18

AF18 AF19

V20 V21

AL1

K17

L1

N15 N16 N17 P15 P16

K15 L15

V15

AB17

Y18

AD17 AD18

AJ17

AJ19

AJ16

AF20 AF21

T19 T20

AJ21

AK20

N18

VCC3_SUS

@

R797 0_0201_5%

1 2

SLG59M1470VTR_FC-TDFN9_1P5X2

U58O

CPU@

CPU POWER 4 OF 4

VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0

VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE

DCPDSW_1P0

VCCMPHYAON_1P0 VCCMPHYAON_1P0

VCCMPHYGT_1P0_N15 VCCMPHYGT_1P0_N16 VCCMPHYGT_1P0_N17 VCCMPHYGT_1P0_P15 VCCMPHYGT_1P0_P16

VCCAMPHYPLL_1P0 VCCAMPHYPLL_1P0

VCCAPLL_1P0

VCCPRIM_1P0_AB17 VCCPRIM_1P0_Y18

VCCDSW_3P3_AD17 VCCDSW_3P3_AD18 VCCDSW_3P3_AJ17

VCCHDA

VCCSPI

VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0

VCCPRIM_3P3_AJ21

VCCPRIM_1P0_AK20

VCCAPLLEBB

SKL-U_BGA1356

U146

@

1

VDD

2

D

3

D

7

ON

15 OF 20

3

SVT_C_EC003

4

S

5

S

6

GND

SKL-U

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE VCCPGPPF VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

VCCMPHY_GATE

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19

T1

AA1

AK17

AK19 BB14

BB10

A14

K19

L21

N20

L19

A10

AN11 AN13

VCC3_SUS

R9325

2MM

@

21

VCC1R8_SUS

VCC1R0_SUS_PRIM

VCC1R0_SUS

1 2

C795

0.1U_0201_6.3V6K

2

VCC3_SUS VCC1R8_SUS VCC1R0_SUS VCCPCHCORE

2

C763

0.1U_0201_6.3V6K

1

2

1

2

1

RTCVCC

2

1

C832

0.1U_0201_6.3V6K

C731 1U_0402_6.3V6K

C2428 47U_0805_6.3V6M

VCC3_SUS

2

1

VCCPCHCORE_VID0 [87] VCCPCHCORE_VID1 [87]

2

1

C380 1U_0402_6.3V6K

@

C2429 47U_0805_6.3V6M

2

1

2

1

2

1

2

1

C2430 47U_0805_6.3V6M

@

C2450 22U_0603_6.3V6M

@

C2452 22U_0603_6.3V6M

@

C2454 22U_0603_6.3V6M

2

C2431 47U_0805_6.3V6M

1

@

2

C2451 22U_0603_6.3V6M

1

@

2

C2453 22U_0603_6.3V6M

1

@

2

C2455 22U_0603_6.3V6M

1

R2304

2MM

R2305

2MM

R2306

2MM

1

VCC1R0_SUS

21

@

VCC1R0_SUS

21

@

VCC1R0_SUS

21

@

VCC1R0_SUS_PRIM VCC1R0_SUS VCCPCHCORE VCC3_SUS VCCMPHY_GATE_OUT VCCMPHY_GATE_OUT VCC3_SUS VCC1R8_SUS VCC1R0_SUS

@

2

C2432 1U_0402_6.3V6K

1

A A

5

2

C2433 1U_0402_6.3V6K

1

@

2

C2434 1U_0402_6.3V6K

1

@

2

C821 1U_0402_6.3V6K

1

2

C2435 1U_0402_6.3V6K

1

4

@

2

C2436 47U_0805_6.3V6M

1

@

2

C2438 1U_0402_6.3V6K

1

2

C2439 1U_0402_6.3V6K

1

3

@

2

C2440 1U_0402_6.3V6K

1

Security Clas sification

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

@

2

C2441 1U_0402_6.3V6K

1

@

2

C2442 1U_0402_6.3V6K

1

2014/11/04 2016/12/31

@

2

C2443 1U_0402_6.3V6K

1

Compal Secret Data

Deciphered Date

2

C2444 1U_0402_6.3V6K

1

@

2

C2445 1U_0402_6.3V6K

1

NEAR A10NEAR AA1NEAR V19NEAR T16NEAR Y16NEAR AG15NEAR N18NEAR AF20NEAR N15NEAR N15NEAR AJ19NEAR AF18NEAR K17NEAR AB19

Compal Electronics, Inc.

Title

CPU : PCH POWER

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

0.5

16 102Thursday, August 13, 2015

0.5

5

D D

4

3

2

1

APS/PETS Interface

VCC3MVCC3_SUS

SKL-U

U58P

A5

VSS

A67

VSS

A70

VSS

AA2

VSS

AA4

VSS

AA65

VSS

AA68

VSS

AB15

VSS

AB16

VSS

AB18

VSS

AB21

VSS

AB8

VSS

C C

for PE Old_Li

B B

AD13 AD16 AD19 AD20 AD21 AD62

AE64 AE65 AE66 AE67 AE68 AE69

AF10 AF15 AF17

AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13

AH63 AH64 AH67

AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69

AD8

AF1

AF2 AF4

AH6

AJ15 AJ18 AJ20

AJ4

AK8

AL2 AL28 AL32 AL35 AL38

AL4 AL45 AL48 AL52 AL55 AL58 AL64

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-U_BGA1356

GND 1 OF 3

16 OF 20

CPU@

AL65

VSS

AL66

VSS

AM13

VSS

AM21

VSS

AM25

VSS

AM27

VSS

AM43

VSS

AM45

VSS

AM46

VSS

AM55

VSS

AM60

VSS

AM61

VSS

AM68

VSS

AM71

VSS

AM8

VSS

AN20

VSS

AN23

VSS

AN28

VSS

AN30

VSS

AN32

VSS

AN33

VSS

AN35

VSS

AN37

VSS

AN38

VSS

AN40

VSS

AN42

VSS

AN58

VSS

AN63

VSS

AP10

VSS

AP18

VSS

AP20

VSS

AP23

VSS

AP28

VSS

AP32

VSS

AP35

VSS

AP38

VSS

AP42

VSS

AP58

VSS

AP63

VSS

AP68

VSS

AP70

VSS

AR11

VSS

AR15

VSS

AR16

VSS

AR20

VSS

AR23

VSS

AR28

VSS

AR35

VSS

AR42

VSS

AR43

VSS

AR45

VSS

AR46

VSS

AR48

VSS

AR5

VSS

AR50

VSS

AR52

VSS

AR53

VSS

AR55

VSS

AR58

VSS

AR63

VSS

AR8

VSS

AT2

VSS

AT20

VSS

AT23

VSS

AT28

VSS

AT35

VSS

AT4

VSS

AT42

VSS

AT56

VSS

AT58

VSS

AT63 AT68 AT71 AU10 AU15 AU20 AU32 AU38

AV68 AV69 AV70

AV71 AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57

AW60 AW62 AW64 AW66

AY66

BA10

BA14

BA18

BA23

BA28

BA32

BA36

BA45

AV1

AW6

AW8

BA1

BA2

B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71

F68

U58Q

GND 2 OF 3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-U_BGA1356

SKL-U

17 OF 20

CPU@

SKL-U

U58R

BA49

VSS

BA53

VSS

BA57

VSS

BA6

VSS

BA62

VSS

BA66

VSS

BA71

VSS

BB18

VSS

BB26

VSS

BB30

VSS

BB34

VSS

BB38

VSS

BB43

VSS

BB55

VSS

BB6

VSS

BB60

VSS

BB64

VSS

BB67

VSS

BB70

VSS

C1

VSS

C25

VSS

C5

VSS

D10

VSS

D11

VSS

D14

VSS

D18

VSS

D22

VSS

D25

VSS

D26

VSS

D30

VSS

D34

VSS

D39

VSS

D44

VSS

D45

VSS

D47

VSS

D48

VSS

D53

VSS

D58

VSS

D6

VSS

D62

VSS

D66

VSS

D69

VSS

E11

VSS

E15

VSS

E18

VSS

E21

VSS

E46

VSS

E50

VSS

E53

VSS

E56

VSS

E6

VSS

E65

VSS

E71

VSS

F1

VSS

F13

VSS

F2

VSS

F22

VSS

F23

VSS

F27

VSS

F28

VSS

F32

VSS

F33

VSS

F35

VSS

F37

VSS

F38

VSS

F4

VSS

F40

VSS

F42

VSS

BA41

VSS

F8 G10 G22 G43 G45 G48

G5 G52 G55 G58

G6 G60 G63 G66 H15 H18 H71 J11 J13 J25 J28 J32 J35 J38 J42

J8 K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71 L11 L16 L17

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-U_BGA1356

GND 3 OF 3

18 OF 20

CPU@

L18

VSS

L2

VSS

L20

VSS

L4

VSS

L8

VSS

N10

VSS

N13

VSS

N19

VSS

N21

VSS

N6

VSS

N65

VSS

N68

VSS

P17

VSS

P19

VSS

P20

VSS

P21

VSS

R13

VSS

R6

VSS

T15

VSS

T17

VSS

T18

VSS

T2

VSS

T21

VSS

T4

VSS

U10

VSS

U63

VSS

U64

VSS

U66

VSS

U67

VSS

U69

VSS

U70

VSS

V16

VSS

V17

VSS

V18

VSS

W13

VSS

W6

VSS

W9

VSS

Y17

VSS

Y19

VSS

Y20

VSS

Y21

VSS

-PCH_SLP_S0[13,80,82,87]

-XDP_DBR[13,19]

-PWRSWITCH[57,62,66,67]

-RTCRST[12,20]

-PCH_SLP_M[13,67]

-PCH_SLP_S4[13,59,67,84]

-PCH_SLP_S5[13,67]

-PCH_SLP_S3[13,59,67,80]

JAPS1

20

GND

19

GND

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_50506-01841-P01

ME@

A A

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU : GND

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

17 102Thursday, August 13, 2015

0.5

5

D D

4

3

2

1

TAB LE

CFG0 : Stall Reset Sequence af t er PC U PLL L ock until de-asser t ed 1 : No Stall 0 : Stall

CFG3 : MSR Privacy Bi t Feature 1 : MSR (C80h) bit[0] set t i ng 0 : MSR (C80h) bit[0] overridden

CFG4 : eDP Enable 1 : Disabled 0 : Enabled

CFG9 : SVID Bus Communicat i on 1 : Enabled 0 : Disabled

RESERVED SIGNALS-1

SKL-U

19 OF 20

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4 RSVD_C4

RSVD_A69 RSVD_B69

RSVD_AY3

RSVD_D71 RSVD_C70

RSVD_C54 RSVD_D54

VSS_AY71

ZVM#

RSVD_TP_AW71 RSVD_TP_AW70

MSM#

PROC_SELECT#

BB68 BB69

AK13 AK12

BB2 BA3

AU5

TP5

AT5

TP6

D5 D4 B2 C2

B3 A3

AW1

E1 E2

BA4 BB4

A4 C4

BB5

TP4

A69 B69

AY3

R2287

D71 C70

C54 D54

AY4

TP1

BB3

TP2

AY71 AR56

R2288

AW71 AW70

AP56 C64

0_0201_5%

1 2

0_0201_5%

1 2

SVT_EC003

AW69 AW68

AU56

AW48

C7 U12 U11 H11

1 2

R2289 100K_0201_5%

U58S

CPU@

E68

CFG[0]

49.9_0201_1%

1 2

B67 D65 D67

E70 C68 D68 C67

F71 G69

F70 G68 H70 G71 H69 G70

E63

F63

E66

F66

E60

AY2 AY1

D1 D3

K46

K45

AL25 AL27

C71

B70

F60

A52

BA70 BA68

J71

J68

F65 G65

F61

E61

CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP

E8

ITP_PMODE

RSVD_AY2 RSVD_AY1

RSVD_D1 RSVD_D3

RSVD_K46 RSVD_K45

RSVD_AL25 RSVD_AL27

RSVD_C71 RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70 RSVD_TP_BA68

RSVD_J71 RSVD_J68

VSS_F65 VSS_G65

RSVD_F61 RSVD_E61

SKL-U_BGA1356

C C

CFG3[19]

1K_0201_5%

1 2

@

R1892

ITP_PMODE[19]

1 2

@

R1891

R8965

R8898

for PE Old_Li

B B

U58T

CPU@

RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48 RSVD_C7 RSVD_U12 RSVD_U11 RSVD_H11

SKL-U_BGA1356

VCCST

SPARE

SKL-U

20 OF 20

RSVD_F6

RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12 RSVD_F52

F6 E3 C11 B11 A11 D12 C12 F52

A A

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU : CFG/RESERVED

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

18 102Thursday, August 13, 2015

0.5

5

4

3

2

1

XDP_TCK0

JXDP1

28

GND

27

GND

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_51522-02601-001

ME@

VCC1R0_SUSVCC1R0_SUSVCC1R0_SUS

2

SVT_C_EC002SVT_C_EC002

@

51_0201_5%

1 2

R509

PCH_TCK

PCH_TMS PCH_TDI

PCH_TDO

-XDP_DBR

CPUCORE_PWRGD[13,75]

CPUCORE_PWRGD

R2499 0_0201_5%

1 2

@

R511 1K_0201_5%

1 2

@

SVT_C_EC002

R514 1K_0201_5%

Merged Port

ASMASM

NO_ASM

ASM

NO_ASM

ASM

1 2

@

DCI 2.0 w/o Connector

ASM

NO_ASM

ASM

NO_ASM

ASM

NO_ASM

ASM

NO_ASM

ASM

TAB LE

R2

R471

R541

R515

R530

R475

J8

C8320

R491

R588

R594

R2499

R509

J9

C2577

R511

R514

R2493

R2494

R2495

R2496

R2497

R2498

-RSMRST

Individual Port

ASM

NO_ASM

ASM

NO_ASM

1

C2577

@

0.1U_0201_6.3V6K JPCH1

28

GND

27

GND

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_51522-02601-001

ME@

51_0201_5%

1 2

@

1 2

R2493 0_0201_5%@

1 2

R2494 0_0201_5%@

1 2

R2495 0_0201_5%@

1 2

R2496 0_0201_5%@

1 2

R2497 0_0201_5%@

1 2

R2498 0_0201_5%@

@

R475

2

SVT_C_EC002

1

C8320

@

0.1U_0201_6.3V6K

JTAGX[6]

PCH_TCK[6]

PCH_TMS[6]

D D

XDP_TCK0[6]

XDP_TMS[6] XDP_TDI[6]

-XDP_TRST[6]

XDP_TDO[6]

-XDP_DBR[13,17]

ITP_PMODE[18]

C C

-RSMRST[13,59]

CFG3[18]

-XDP_PRDY[10]

-XDP_PREQ[10]

PCH_TDI[6]

-PCH_TRST[6]

PCH_TDO[6]

VCC1R0_SUS VCC3B VCCSTG VCC1R0_SUS

1.5K_0201_5%@1 2

XDP_TCK0

XDP_TCK1 XDP_TMS XDP_TDI

-XDP_TRST XDP_TDO

-XDP_DBR ITP_PMODE

-RSMRST

-XDP_PRDY

-XDP_PREQ

JTAGX

PCH_TCK XDP_TCK1

PCH_TMS XDP_TMS

PCH_TDI XDP_TDI

-PCH_TRST -XDP_TRST

PCH_TDO XDP_TDO

1K_0201_5%

1 2

R491

R588

SVT_C_EC002

R594 1K_0201_5%

for PE Old_Li

B B

A A

LOGIC

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

XDP CONNECTOR

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

19 102Thursday, August 13, 2015

0.5

5

D D

4

3

VCC3SWVCC3SW

2

1

@

PR237

1.5K_0201_5%

1 2

@

C C

PR4 1K_0201_5%

1 2

PJRTC

1

2

3

G1

4

G2

CVILU_CI4402M1HRT-NH

@

PR238 47K_0201_5%

1 2

PD3

12

RB520CM-30T2R_VMN2M2

for PE Old_Li

B B

PD7 RB520CM-30T2R_VMN2M2

1 2

PD6 RB520CM-30T2R_VMN2M2

1 2

PR620

PR250

RTCVCC

20K_0201_5%

1 2

20K_0201_5%

1 2

PC287 1U_0402_6.3V6K

1 2

PC459 1U_0402_6.3V6K

1 2

PC285 1U_0402_6.3V6K

1 2

-RTCRST

-SRTCRST

-RTCRST [12,17]

-SRTCRST [12]

A A

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

RTC BATTERY

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

20 102Thursday, August 13, 2015

0.1

5

D D

C C

-SPI_CS0[7]

SPI_MISO_IO1[7,65]

4

-SPI_CS0 -SPI_CS0_R SPI_MISO_IO1 SPI_MISO_IO1_0_R

1 2

R322 33_0201_5%

1 2

R694 33_0201_5%

VCC3_SUS

D12 RB520CM-30T2R_VMN2M2

1 2

@

1 2

10K_0201_5%

R2342

VCC3_SUS_SPI

U49

1

/CS

2

DO(IO1)

3

/WP(IO2) GND4DI(IO0)

W25Q128FVSIQ_SO8

3

0.1U_0201_6.3V6K

/HOLD(IO3)

2

Change R703 to ASM

2

C629

1 2

1

VCC

CLK

3.3K_0201_5%

8 7 6 5

2

1

1 2

3.3K_0201_5%

0.1U_0201_6.3V6K

R703

R706

C429

SPI_IO3_0_R

SPI_IO2_0_R

R8981 33_0402_5% R681 33_0201_5% R674 33_0201_5%

R8980 33_0402_5%

16MB SOIC8 WINBOND W25Q128FVSIQ MACRONIX MX2 5L12873FM2I-10G

1 2

12 12

1 2

SPI_MOSI_IO0SPI_MOSI_IO0_0_R

SPI_IO3 SPI_CLKSPI_CLK_0_R

SPI_IO2

SPI_IO3 [7] SPI_CLK [7,65] SPI_MOSI_IO0 [7,65]

SPI_IO2 [7]

1

for PE Old_Li

TAB LE

B B

A A

5

4

SF100 PIN HEADER INTERFACE (TOP VIEW)

1 VCC D12.1

3 CS# R322.2

5 MISO R694.2

7 (KEY) N/A

GND GND 2

R681.2 CLK 4

R674.2 MOSI 6

N/A (RESET) 8

3

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

SPI FLASH

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

21 102Thursday, August 13, 2015

0.5

A

M_A_DQ[63:0][4]

-M_A_DQS[7:0][4]

M_A_DQS[7:0][4]

M_A_A[16:0][4]

1 1

2 2

M_A_CKE0[4]

M_A_BG1[4] M_A_BG0[4]

M_A_DDRCLK0_933M[4]

-M_A_DDRCLK0_933M[4]

M_A_PARITY[4]

M_A_BS1[4]

-M_A_CS0[4]

M_A_ODT0[4]

-M_A_CS1[4]

M_A_ODT1[4]

M_A_CKE0

M_A_BG1 M_A_BG0

M_A_DDRCLK0_933M

-M_A_DDRCLK0_933M

M_A_PARITY

M_A_BS1

-M_A_CS0

M_A_ODT0

-M_A_CS1

M_A_ODT1

for PE Old_Li

3 3

VCC3B

VCC2R5A

4 4

VCC3B

2

C2117

2.2U_0402_6.3V6M

1

2

C2118

0.1U_0201_6.3V6K

1

A

SMB_CLK_3B[62,66]

SMB_CLK_3B

B

M_A_DQ5

M_A_DQ1

-M_A_DQS0 M_A_DQS0

M_A_DQ7

M_A_DQ3

M_A_DQ13

M_A_DQ9

M_A_DQ15

M_A_DQ10

M_A_DQ21

M_A_DQ17

-M_A_DQS2 M_A_DQS2

M_A_DQ23

M_A_DQ19

M_A_DQ29

M_A_DQ25

M_A_DQ30

M_A_DQ26

M_A_A12 M_A_A9

M_A_A8 M_A_A6

M_A_A3 M_A_A1

M_A_A14

M_A_DQ37

M_A_DQ33

-M_A_DQS4 M_A_DQS4

M_A_DQ38

M_A_DQ34

M_A_DQ44

M_A_DQ40

M_A_DQ46

M_A_DQ42

M_A_DQ52

M_A_DQ49

-M_A_DQS6 M_A_DQS6

M_A_DQ55

M_A_DQ51

M_A_DQ61

M_A_DQ56

M_A_DQ62

M_A_DQ58

B

C

VCC1R2A VCC1R2A

JDIMM1

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5

11

DQS0_C

13

DQS0_T

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1#/DBI1#/NC

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25

53

DQS2_C

55

DQS2_T

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3#/DBI3#/NC

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45

95

DQS8_C

97

DQS8_T

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_T

139

CK0_C

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0#

151

A14/WE#

153

VDD15

155

ODT0

157

CS1#

159

VDD17

161

ODT1

163

VDD19

165

C1/CS3#/NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_C

179

DQS4_T

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5#/DBI5#/NC

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_C

221

DQS6_T

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7#/DBI7#/NC

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND

FOX_ASAA85Y-SKSB0-4H

VSS2

VSS4

VSS6

DM0#/DBI0#/NC

VSS7

VSS9

VSS11

DQ12

VSS13

VSS15 DQS1_C DQS1_T

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

DM2#/DBI2#/NC

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35 DQS3_C DQS3_T

VSS38

DQ31

VSS40

DQ27

VSS42 CB4/NC

VSS44 CB0/NC

VSS46

DM8#/DBI8#/NC

VSS47 CB6/NC

VSS49 CB7/NC

VSS51 RESET#

CKE1 VDD2 ACT#

ALERT#

VDD4

VDD6

VDD8

EVENT#

VDD10

CK1_T

CK1_C VDD12

A10/AP

VDD14

A16/RAS#

VDD16

A15/CAS#

VDD18

C0/CS2#/NC

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

DM4#/DBI4#/NC

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67 DQS5_C DQS5_T

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6#/DBI6#/NC

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87 DQS7_C DQS7_T

VSS90

DQ63

VSS92

DQ59

VSS94

ME@

2 4

DQ4

6 8

DQ0

10 12 14 16

DQ6

18 20

DQ2

22 24 26 28

DQ8

30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120

A11

122

A7

124 126

A5

128

A4

130 132

A2

134 136 138 140 142 144

A0

146 148 150

BA0

152 154 156 158

A13

160 162 164 166

SA2

168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254

SDA

256

SA0

258

VTT

260

SA1

262

GND

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

M_A_DQ4

M_A_DQ0

M_A_DQ6

M_A_DQ2

M_A_DQ12

M_A_DQ8

-M_A_DQS1 M_A_DQS1

M_A_DQ14

M_A_DQ11

M_A_DQ20

M_A_DQ16

M_A_DQ22

M_A_DQ18

M_A_DQ28

M_A_DQ24

-M_A_DQS3 M_A_DQS3

M_A_DQ31

M_A_DQ27

M_A_A11 M_A_A7

M_A_A5 M_A_A4

M_A_A2

M_A_A0

M_A_A10

M_A_A16

M_A_A15 M_A_A13

M_A_DQ36

M_A_DQ32

M_A_DQ39

M_A_DQ35

M_A_DQ45

M_A_DQ41

-M_A_DQS5 M_A_DQS5

M_A_DQ47

M_A_DQ43

M_A_DQ53

M_A_DQ48

M_A_DQ54

M_A_DQ50

M_A_DQ60

M_A_DQ57

-M_A_DQS7 M_A_DQS7

M_A_DQ63

M_A_DQ59

M_A_DDRCLK1_933M

-M_A_DDRCLK1_933M

-DRAMRST M_A_CKE1

-M_A_ACT

-M_A_ALERT

M_A_BS0

SMB_DATA_3B

M_A_VREF_CA_CPU[4]

-DRAMRST [5] M_A_CKE1 [4]

-M_A_ACT [4]

-M_A_ALERT [4]

M_A_DDRCLK1_933M [4]

-M_A_DDRCLK1_933M [4]

M_A_BS0 [4]

SVT_C_EC004

SMB_DATA_3B [62,66]

SPD ADDRESS: 50H

SVT_C_EC003

Compal Secret Data

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

D

1 2

2

C2119

0.022U_0201_10V6K

1

R2074

24.9_0201_1%

1 2

M_A_VREF_CA

@

R108 0_0201_5%

R2073

VCC0R6B

E

VCC1R2A

R2069

1K_0201_1%

1 2

2_0201_1%

1 2

R2070

1K_0201_1%

1 2

M_A_VREF_CA

2

C2120

2.2U_0402_6.3V6M

1

VCC2R5A

2

C2122 10U_0402_6.3V6M

1

Title

Size

Document Number Rev

Custom

Date: Sheet of

2

C2121

0.1U_0201_6.3V6K

1

2

C2123 1U_0402_6.3V6K

1

Compal Electronics, Inc.

DDR4 SO DIMM CHANNEL-A (1/2)

LA-C581P

E

M_A_VREF_CA

22 102Thursday, August 13, 2015

0.5

5

VCC1R2A

D D

C2124 1U_0402_6.3V6K

1 2

VCC1R2A

C2125 1U_0402_6.3V6K

1 2

4

C2126 1U_0402_6.3V6K

1 2

C2127 1U_0402_6.3V6K

1 2

C2128 1U_0402_6.3V6K

1 2

C2129 1U_0402_6.3V6K

1 2

C2130 1U_0402_6.3V6K

1 2

3

C2131 1U_0402_6.3V6K

1 2

2

1

2

C2142

0.1U_0201_6.3V6K

1

2

C2135

10U_0402_6.3V6M

1

2

C2132

10U_0402_6.3V6M

C C

for PE Old_Li

B B

1

VCC0R6B

2

0.1U_0201_6.3V6K

1

VCC0R6B

2

C2144

10U_0402_6.3V6M

1

C2140

2

C2133

10U_0402_6.3V6M

1

2

C2141

0.1U_0201_6.3V6K

1

2

C2145

10U_0402_6.3V6M

1

2

C2134

10U_0402_6.3V6M

1

2

C2143

0.1U_0201_6.3V6K

1

2

C2136

10U_0402_6.3V6M

1

2

C2137

10U_0402_6.3V6M

1

2

C2138

10U_0402_6.3V6M

1

2

C2139

10U_0402_6.3V6M

1

A A

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

DDR4 SO DIMM CHANNEL-A (2/2)

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

23 102Thursday, August 13, 2015

0.5

5

D D

C C

4

3

2

1

BLANK

for PE Old_Li

B B

A A

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

BLANK

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

24 102Thursday, August 13, 2015

0.5

5

D D

C C

4

3

2

1

BLANK

for PE Old_Li

B B

A A

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

BLANK

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

25 102Thursday, August 13, 2015

0.5

5

4

3

2

1

8

72

6

54

2

1

C319 0.1U_0201_6.3V6K

USBP9-_CONN USBP9+_CONN

1 2 1 2

VCC3P

R361

47_0201_5%

1 2

21

D63

RB521CM-30T2R_SOD923-2

R714 47K_0201_5%

1 2

SVT_C_EC029

21

2

1

0467.500NRHF 0.5A 32V

F24

C314 0.1U_0201_6.3V6K

VCC3B_TOUCH_CN

ESD@

2

1

C8531

1000P_0201_25V7K

VCC3MVCC3B

ESD@

VBL20 VINT20

1.2A

F7

21

0438003.WR 3A 32V

1

C724

0.01U_0402_25V7K

2

SVT_C_EC029

MIC_VCCVCC3MVCC3B

F3

0438003.WR 3A 32V

2

C308

0.01U_0201_6.3V7K

1

R668 47K_0201_5%

EDP_TXP0_CONN EDP_TXN0_CONN

EDP_TXP1_CONN EDP_TXN1_CONN

2

@

C929 1000P_0201_25V7K

1

VCC3LCD

2

C315 1U_0402_6.3V6K

1

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

ARGOS_LVDFH-04008-TM00+

2

C311

0.1U_0201_6.3V6K

1

LCD CONNECTOR

JEDP1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

41

36

G1

42

37

G2

43

38

G3

44

39

G4

45

40

G5

ME@

VCC3P

21

0467.500NRHF 0.5A 32V

F29

1 2

VCC3M_WBTN_CN

2

1

C8532

1000P_0201_25V7K

NEAR JCMOS1

VCC3B MIC_VCC

@

1 2

RJ190

@

1 2

RJ189

MIC_GND

4

VCC3P

21

C307

0.01U_0402_25V7K

1 2

PESD5V0U2BT_SOT23-3

ESD@

3

0.9A

VBL20

C310

0.1U_0402_25V7K

1 2

2

3

D28

1

C313 1U_0603_25V7K

2

USBP7-[10] USBP7+[10]

Issued Date

-LED_LOGO

USBP7USBP7+

-INT_MIC_DTCT MIC_DATA MIC_CLK

SENSE_SCL SENSE_SDA

ISH_I2C0_SDA ISH_I2C0_SCL

-LED_LOGO[58]

-INT_MIC_DTCT[8] MIC_DATA[50]

MIC_CLK[50]

SENSE_SCL[56,59] SENSE_SDA[56,59]

ISH_GP0[8] ISH_GP1[8] ISH_GP2[8,56]

ISH_I2C0_SDA[8,56] ISH_I2C0_SCL[8,56]

-LED_LOGO

Security Clas sification

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

R102 680_0402_5%

1 2

R786 0_0201_5%

1 2

R785 0_0201_5%

2014/11/04 2016/12/31

USBP7-_CONN USBP7+_CONN

Compal Secret Data

Deciphered Date

2

21

2

1

F28

C322 0.1U_0201_6.3V6K

VCC3B_SENS_CN

2

@

1

C33

1000P_0201_25V7K

21

2

1

0467.500NRHF 0.5A 32V F34

C321 0.1U_0201_6.3V6K

VCC3M_SENS_CN

21

2

1

0467.500NRHF 0.5A 32V

F33

C320 0.1U_0201_6.3V6K

MIC_VCC_CN

JCMOS1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

31

26

G1

27

32

27

G2

28

33

28

G3

29

34

29

G4

30

35

30

G5

ARGOS_LVDFH-03001-TM00+

ME@

MIC_GND

Compal Electronics, Inc.

Title

LCD/LID/MIC/CAMERA

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

0.5

26 102Thursday, August 13, 2015

0.5

VCC3M

Q22

1

D D

VCC3P_DRV[68]

C C

PANEL_BKLT_CTRL[3] BACKLIGHT_ON[58]

B B

EDP_AUXN[3] EDP_AUXP[3]

EDP_TXP0[3] EDP_TXN0[3]

EDP_TXP1[3] EDP_TXN1[3]

EDP_TXP0_C

2

EDP_TXN0_C

1

A A

EDP_TXP1_C

2

EDP_TXN1_C

1

VCC3P_DRV

HSYNC PANEL_BKLT_CTRL BACKLIGHT_ON

for PE Old_Li

EDP_HPD[3]

-WIN_BTN[60]

-LID_CLOSE[8,56,59]

-TOUCH_DISABLE[67]

USBP9-[10] USBP9+[10]

1 2

C8289 0.1U_0201_6.3V6K

1 2

C8290 0.1U_0201_6.3V6K

1 2

C8299 0.1U_0201_6.3V6K

1 2

C8298 0.1U_0201_6.3V6K

1 2

C8296 0.1U_0201_6.3V6K

1 2

C8295 0.1U_0201_6.3V6K

FLJ21

2

1

MCF12102G900-T_4P

FLJ22

2

1

MCF12102G900-T_4P

-WIN_BTN

-TOUCH_DISABLE -TOUCH_STOP

USBP9USBP9+

HSYNC

@RF@

EDP_TXP0_CONN

3

EDP_TXN0_CONN

4

@RF@

EDP_TXP1_CONN

3

EDP_TXN1_CONN

4

5

3

TPCF8002_2-3U1A

R76 100_0201_5%

1 2

1

C603

0.1U_0402_25V7K

2

21

D6 RB521CM-30T2R_SOD923-2

1 2

R2078 0_0201_5%

1 2

R2079 0_0201_5%

EDP_AUXN_CONN EDP_AUXP_CONN

EDP_TXP0_C EDP_TXN0_C

EDP_TXP1_C EDP_TXN1_C

21

D4 RB521CM-30T2R_SOD923-2

RJ191 0_0402_5%RF@ RJ192 0_0402_5%RF@

RJ193 0_0402_5%RF@ RJ194 0_0402_5%RF@

5

4

3

2

1

20 19 14 6 4 13 8 7 1

21 22 23 24

5.1M_0201_5%

5

4

DP_DP3N_CONN DP_DP3P_CONN

DP_DP2N_CONN DP_DP2P_CONN

DP_DP1N_CONN DP_DP1P_CONN

DP_DP0N_CONN DP_DP0P_CONN

2

1 2

1

0.1U_0201_6.3V6K

R93

C139

U100

IN

EN

TPS2530DBVR

OUT GND

OC

1 2

1M_0201_5%

R97

DVI_DONGLE_DTCT

VCC3VIDEO_DP

1 2 3

2

C1112

0.1U_0201_6.3V6K

1

2

C991

4.7U_0402_6.3V6M

1

VCC3VIDEO_DP

2

C992 10U_0402_6.3V6M

1

1 2

DDIP1_3N[3] DDIP1_3P[3]

VCC3B VCC5B

2

U6

16

Vcc

2

1B1

3

1B2

5

2B1

6

2B2

11

3B1

10

3B2

14

4B1

13

4B2

VCC3VIDEO_DP

DP_DP1P_CONN

DP_DP1N_CONN

DP_DP2N_CONN

DP_DP2P_CONN

DP_DP3N_CONNDP_DP3N_CONN

C496

0.1U_0201_6.3V6K

1

1A 2A 3A 4A

OE

S

GND

T-PAD

4 7 9 12

15 1

8 17

R98

100K_0201_5%

DVI_DONGLE_DTCTDDIP1_CTRLDATA

VCC3B

R94 100K_0201_5%

1 2

D D

1 2

DDIP1_AUXP[3]

DDIP1_AUXN[3]

DDIP1_CTRLCLK[3]

DDIP1_CTRLDATA[3]

DDIP1_HPD[3]

C C

DDIP1_AUXP

DDIP1_AUXN

DDIP1_CTRLCLK

1 2

C468 0.1U_0201_6.3V6K

1 2

C659 0.1U_0201_6.3V6K

R1037

100K_0201_5%

1 2

DDIP1_AUXP_C

DDIP1_AUXN_C

DP_AUXN_CONN DP_HPD_CONN

DP_AUXP_CONN

DP_DP0P_CONN DP_DP0P_CONN

DP_DP0N_CONN DP_DP0N_CONN

DP_DP1P_CONN

DP_DP1N_CONN

for PE Old_Li

B B

DP_DP2N_CONN

DP_DP2P_CONN

DP_DP3P_CONN DP_DP3P_CONN

R1027@

2.2K_0201_5%

R1028

2.2K_0201_5%

1 2

D224

1

V I/O

Ground2V BUS

3

V I/O

PUSB2X4D_SO6-6

ESD@

D86

1

2

4

5

3

8

PUSB3F96_XSON10_2.5X1~D

ESD@

D88

1

2

4

5

3

8

PUSB3F96_XSON10_2.5X1~D

ESD@

CBT3257ABQ_DHVQFN16_2P5X3P5

6

5

4

10

9

7

6

10

9

7

6

DDIP1_2N[3] DDIP1_2P[3]

DDIP1_1N[3] DDIP1_1P[3]

DDIP1_0N[3] DDIP1_0P[3]

DP_HPD_CONN

DP_AUXP_CONN DP_AUXN_CONN

DP_DP3P_CONN DP_DP3N_CONN

DP_DP2P_CONN DP_DP2N_CONN

DP_DP1P_CONN DP_DP1N_CONN

DP_DP0P_CONN DP_DP0N_CONN

VCC3M

2

@

C21 10U_0402_6.3V6M

1

SVT_C_EC004

BPWRG[13,59,66,68]

C339 0.1U_0201_6.3V6K

1 2

C323 0.1U_0201_6.3V6K

1 2

C312 0.1U_0201_6.3V6K

1 2

C317 0.1U_0201_6.3V6K

1 2

C277 0.1U_0201_6.3V6K

1 2

C276 0.1U_0201_6.3V6K

1 2

C218 0.1U_0201_6.3V6K

1 2

C226 0.1U_0201_6.3V6K

JDP1

2

HOT PLUG

16

AUX_CH_P

18

AUX_CH_N

10

LANE3_P

12

LANE3_N

15

LANE2_P

17

LANE2_N

9

LANE1_P

11

LANE1_N

3

LANE0_P

5

LANE0_N

SINGA_2LB3001-000111F

2

@

C67

0.01U_0201_6.3V7K

1

2

@

C990

0.1U_0201_6.3V6K

1

1 2

R105 0_0201_5%

@

DP_PWR

CONFIG2 CONFIG1

GND1 GND2 GND3 GND4

ME@

GND GND

GND GND GND GND

SVT_C_EC003

A A

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

DISPLAY PORT CONNECTOR

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

27 102Thursday, August 13, 2015

0.5

5

4

VCC3BVCC3B

3

2

1

2

1

C2546

2

0.01U_0201_6.3V7K

1 2

C2522 0.1U_0201_6.3V6K

1 2

C2523 0.1U_0201_6.3V6K

1 2

C2524 0.1U_0201_6.3V6K

1 2

C2525 0.1U_0201_6.3V6K

1 2

C2526 0.1U_0201_6.3V6K

1 2

C2527 0.1U_0201_6.3V6K

1 2

C2528 0.1U_0201_6.3V6K

1 2

C2529 0.1U_0201_6.3V6K

PS8338_PI1

TP152@

PS8338_PI0

1 2

C2530 0.1U_0201_6.3V6K

1 2

C2531 0.1U_0201_6.3V6K

PS8338_PC10 PS8338_PC11 PS8338_PC20 PS8338_PC21

0.1U_0201_6.3V6K

C2544

1

DDIP2_0P_C DDIP2_0N_C

DDIP2_1P_C DDIP2_1N_C

DDIP2_2P_C DDIP2_2N_C

DDIP2_3P_C DDIP2_3N_C

DDIP2_AUXP_C DDIP2_AUXN_C

12

2.2K_0201_5%

R2378

VCC3B

12

2.2K_0201_5%

R2379

12

4.7K_0201_5%

R2514

D D

DDIP2_0P[3] DDIP2_0N[3]

DDIP2_1P[3] DDIP2_1N[3]

DDIP2_2P[3] DDIP2_2N[3]

DDIP2_3P[3] DDIP2_3N[3]

DDIP2_HPD[3]

C C

DDIP2_CTRLCLK[3]

DDIP2_CTRLDATA[3]

DDIP2_AUXP[3] DDIP2_AUXN[3]

TABLE : Automatic Switching Mode (CFG0 = H)

SW (DDI_PRIORITY2)

L Port 1 has higher priority when both ports are plugged H Port 2 has higher priority when both ports are plugged

PEQ (INT PD)

HEQ 14.5dB

LLEQ 8.5dB

LEQ 11.5dB

B B

AUX interception DIS Output 800mV & 0dB

AUX interception DIS Output 400mV & 0dB

for PE Old_Li

ASM

NO_ASM

AUX interception EN

PC11 (INT PD)

A A

Swing +20%

Swing -16.7%

Swing default NO_ASMNO_ASM

R2525

ASM

NO_ASM

5

R2522R2521

NO_ASMASM

ASM

NO_ASM

PC10 (INT PD)

R2523 R2524

ASM

NO_ASM

ASM

NO_ASM

R2526

NO_ASM

ASM

NO_ASM

LOGIC

PC20 (INT PD)

R2527 R2528

ASM NO_ASM

ASM ASM

NO_ASM NO_ASM

PC21 (INT PD)

R2530R2529

ASM

NO_ASM

VCC3B

1 2

R2521 @ 4.7K_0201_5%

1 2

R2523 @ 4.7K_0201_5%

1 2

R2525 4.7K_0201_5%@

1 2

R2527 @ 4.7K_0201_5%

1 2

R2529 @ 4.7K_0201_5%

1 2

R2532 @ 4.7K_0201_5%

1 2

R2531 @ 4.7K_0201_5%

PS8338_PEQ

PS8338_PC10

PS8338_PC11

PS8338_PC20

PS8338_PC21

PS8338_PI1

PS8338_PI0

LOGIC

ASMASM

LOGIC

4

2

C2576

1

0.1U_0201_6.3V6K

U147

5

VDD33

21

VDD33

30

VDD33

51

VDD33

57

VDD33

6

IN_D0p

7

IN_D0n

9

IN_D1p

10

IN_D1n

12

IN_D2p

13

IN_D2n

15

IN_D3p

16

IN_D3n

4

IN_CA_DET

3

IN_HPD

2

I2C_CTL_EN

1

Pl1/SCL_CTL

60

Pl0/SDA_CTL

22

IN_DDC_SCL

23

IN_DDC_SDA

24

IN_AUXp

25

IN_AUXn

59

CFG0

58

CFG1

56

PC10

55

PC11

54

PC20

53

PC21

11

GND

19

GND

52

GND

61

PAD(GND)

PS8338BQFN60GTR-A0_QFN60_5X9

R2522 @ 4.7K_0201_5%

R2524 @ 4.7K_0201_5%

R2526 4.7K_0201_5%@

R2528 @ 4.7K_0201_5%

R2530 @ 4.7K_0201_5%

R2533 @ 4.7K_0201_5%

2

1

1 2

3

C2543

OUT1_AUXp_SCL OUT1_AUXn_SDA

OUT2_AUXp_SCL OUT2_AUXn_SDA

1

C2545

2

0.01U_0201_6.3V7K

OUT1_D0p OUT1_D0n

OUT1_D1p OUT1_D1n

OUT1_D2p OUT1_D2n

OUT1_D3p OUT1_D3n

OUT2_D0p OUT2_D0n

OUT2_D1p OUT2_D1n

OUT2_D2p OUT2_D2n

OUT2_D3p OUT2_D3n

OUT1_CA_DET

OUT1_HPD

OUT2_CA_DET

OUT2_HPD

CEXT REXT

50 49

47 46

45 44

42 41

40 39

37 36

35 34

32 31

26 27

28 29

43 48

33 38

18

SW

8

PEQ

14

PD

17 20

1 2

Auto test EN & Offset cancellation EN

Auto test DIS & Offset cancellation DIS

Auto test DIS & Offset cancellation EN

Auto EQ DIS

Auto EQ EN

Priority 2

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R2516 1M_0201_5%

PI1 (INT PD)

PI0 (INT PD)

Priority 1

H

L

PS8338_PEQ

R2515

4.99K_0201_1%

1 2

2

C2587

2.2U_0402_6.3V6M

1

R2532 R2533

ASM NO_ASM

ASM

NO_ASM

R2531

ASM

NO_ASM

HL

HDMI WiGig

Prolink

2014/11/04 2016/12/31

Prolink

Compal Secret Data

Deciphered Date

2

1 2

LOGIC

R2517 1M_0201_5%

DOCK_DDIP2_0P [57] DOCK_DDIP2_0N [57]

DOCK_DDIP2_1P [57] DOCK_DDIP2_1N [57]

DOCK_DDIP2_2P [57] DOCK_DDIP2_2N [57]

DOCK_DDIP2_3P [57] DOCK_DDIP2_3N [57]

DMUX_DDIP2_0P [29] DMUX_DDIP2_0N [29]

DMUX_DDIP2_1P [29] DMUX_DDIP2_1N [29]

DMUX_DDIP2_2P [29] DMUX_DDIP2_2N [29]

DMUX_DDIP2_3P [29] DMUX_DDIP2_3N [29]

DOCK_DDIP2_AUXP [57] DOCK_DDIP2_AUXN [57]

DMUX_DDIP2_AUXP [29] DMUX_DDIP2_AUXN [29]

DOCK_DDIP2_HPD [57]

DMUX_DDIP2_CADET [29] DMUX_DDIP2_HPD [29]

ASM

NO_ASM

VCC3B

R2500

4.7K_0201_5%

1 2

DDI_PRIORITY2 [9]

LOGIC

Compal Electronics, Inc.

Title

DDI DEMULTIPLEXER

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

0.5

28 102Thursday, August 13, 2015

0.5

5

4

VCC3B

3

2

1

2

C1424

1

0.1U_0201_6.3V6K

VCC3B_PS8337B

2

C1425

1

0.1U_0201_6.3V6K

VCC3B_PS8337B

PS8337_DP_CFG0

DMUX_DDIP2_0P_C DMUX_DDIP2_0N_C

DMUX_DDIP2_1P_C DMUX_DDIP2_1N_C

DMUX_DDIP2_2P_C DMUX_DDIP2_2N_C

DMUX_DDIP2_3P_C DMUX_DDIP2_3N_C

PS8337_TMDS_DDCBUF

PS8337_PEQ

PS8337_MODE

U108

14

VDD33

28

VDD33

41

VDD33

56

VDD33

44

DP_CFG0/SCL_CTL

45

SW/SDA_CTL

38

I2C_CTL_EN

3

IN_D0p

4

IN_D0n

6

IN_D1p

7

IN_D1n

9

IN_D2p

10

IN_D2n

12

IN_D3p

13

IN_D3n

52

IN_AUXp

51

IN_AUXn

50

IN_DDC_SCL

49

IN_DDC_SDA

11

IN_CA_DET

5

IN_HPD

1

CEXT

2

TMDS_DDCBUF

8

PEQ

27

REXT

46

PD

53

MODE

PS8337BQFN56GTR2-A1_QFN56_7X7

1 2

R1876 @ 4.7K_0201_5%

1 2

R1875 @ 4.7K_0201_5%

1 2

R1877 4.7K_0201_5%

1 2

R146 4.7K_0201_5%

1 2

R2509 4.7K_0201_5%

1 2

R2510 @ 4.7K_0201_5%

40

DP_D0p

39

DP_D0n

37

DP_D1p

36

DP_D1n

34

DP_D2p

33

DP_D2n

31

DP_D3p

30

DP_D3n

55

DP_AUXp_SCL

54

DP_AUXn_SDA

32

DP_HPD

42

DP_CA_DET

29

DP_CFG1

19

TMDS_CH0p

18

TMDS_CH0n

22

TMDS_CH1p

21

TMDS_CH1n

25

TMDS_CH2p

24

TMDS_CH2n

16

TMDS_CLKp

15

TMDS_CLKn

48

TMDS_SCL

47

TMDS_SDA

17

TMDS_HPD

23

TMDS_RT

20

TMDS_PRE

26

GND

35

GND

43

GND

57

Thermal/GND

PS8337_TMDS_DDCBUF

PS8337_PEQ

PS8337_TMDS_PRE

PS8337_MODE

PS8337_TMDS_RT

PS8337_DP_CFG0

WIGIG_AUXP WIGIG_AUXN WIGIG_HPD

1 2

R2511 1M_0201_5%

PS8337_DP_CFG1

HDMI_DATA0P HDMI_DATA0N

HDMI_DATA1P HDMI_DATA1N

HDMI_DATA2P HDMI_DATA2N

HDMI_CLKP HDMI_CLKN

HDMI_DDC_CLK HDMI_DDC_DATA

PS8337_TMDS_RT PS8337_TMDS_PRE

1 2

R1898 @ 4.7K_0201_5%

1 2

R1897 @ 4.7K_0201_5%

1 2

R1899 4.7K_0201_5%

1 2

R147 4.7K_0201_5%

WIGIG_DP0P [46] WIGIG_DP0N [46]

WIGIG_DP1P [46] WIGIG_DP1N [46]

WIGIG_DP2P [46] WIGIG_DP2N [46]

WIGIG_DP3P [46] WIGIG_DP3N [46]

WIGIG_AUXP [46] WIGIG_AUXN [46] WIGIG_HPD [46]

TP918@

HDMI_DATA0P [30] HDMI_DATA0N [30]

HDMI_DATA1P [30] HDMI_DATA1N [30]

HDMI_DATA2P [30] HDMI_DATA2N [30]

HDMI_CLKP [30] HDMI_CLKN [30]

HDMI_DDC_CLK [30] HDMI_DDC_DATA [30]

HDMI_HPD_CONN

R2512

27K_0201_1%

1 2

HDMI_HPD_CONN [30]

TMDS DDCBUF (INT PD)

DDC Ative Buffer

DDC Pass Through w/ PU

DDC Pass Through w/o PU

PEQ (INT PD)

HEQ 15dB

LLEQ 5dB

LEQ 12dB

TMDS PRE (INT PD)

1.5dB

3.0dB

0dB

MODE (INT PD)

Auto HDMI ID disable

Auto HDMI ID enable

Control HDMI ID disable

R1898R1876

ASM NO_ASM

ASM

NO_ASM

ASM

NO_ASM

R1875 R1897

ASM NO_ASM

ASM

NO_ASM NO_ASM

R1899R1877

NO_ASMASM

ASMASM

NO_ASM NO_ASM

R146 R147

ASM NO_ASM

ASM ASM

NO_ASMNO_ASM

LOGIC

D D

SVT_C_EC005

Short Pattern: R2463

VCC3B VCC3B_PS8337B

R2463

21

Short Pattern

@

2

C993

1

4.7U_0402_6.3V6M

2

C1423

C1422

1

0.1U_0201_6.3V6K

TABLE : Automatic Switching Mode (MODE = H, M)

SW (DDI_PRIORITY1)

L DP Port has higher priority when both ports are plugged H TMDS Port has higher priority when both ports are plugged

VCC3B

C C

DDI_PRIORITY1[9]

DMUX_DDIP2_0P[28] DMUX_DDIP2_0N[28]

DMUX_DDIP2_1P[28] DMUX_DDIP2_1N[28]

DMUX_DDIP2_2P[28] DMUX_DDIP2_2N[28]

DMUX_DDIP2_3P[28] DMUX_DDIP2_3N[28]

DMUX_DDIP2_AUXP[28] DMUX_DDIP2_AUXN[28]

DMUX_DDIP2_CADET[28]

for PE Old_Li

B B

DMUX_DDIP2_HPD[28]

DDI_PRIORITY1

R2501

4.7K_0201_5%

1 2

C1405 0.1U_0201_6.3V6K

1 2

C1406 0.1U_0201_6.3V6K

1 2

C1407 0.1U_0201_6.3V6K

1 2

C1408 0.1U_0201_6.3V6K

1 2

C1409 0.1U_0201_6.3V6K

1 2

C1415 0.1U_0201_6.3V6K

1 2

C1418 0.1U_0201_6.3V6K

1 2

C1419 0.1U_0201_6.3V6K

2

C213

2.2U_0402_6.3V6M

1

R246 4.7K_0201_1%

1 2

SVT_C_EC026

TMDS RT (INT PD)

OD w/ termination

OD

A A

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

R2509

ASM

NO_ASM

Compal Electronics, Inc.

Title

DDI DEMUX/HDMI LEVEL SHIFT

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

LOGIC

29 102Thursday, August 13, 2015

0.5

5

D D

HDMI_DATA2P[29]

HDMI_DATA2N[29]

HDMI_DATA1P[29]

HDMI_DATA1N[29]

HDMI_DATA0P[29]

C C

HDMI_DATA0N[29]

HDMI_CLKP[29]

HDMI_CLKN[29]

HDMI_DATA2P

HDMI_DATA2N

HDMI_DATA1P

HDMI_DATA1N

HDMI_DATA0P

HDMI_DATA0N

HDMI_CLKP

HDMI_CLKN

4

FLJ10

EMI@

MCF12102G900-T_4P

FLJ11

EMI@

MCF12102G900-T_4P

FLJ12

EMI@

MCF12102G900-T_4P

FLJ13

EMI@

MCF12102G900-T_4P

3

VCC5B_HDMI

No need diode here because TPS2553 has reverse voltage protection function.

R1030

R1029

1.5K_0201_5%

1 2

1.5K_0201_5%

1 2

3

4

3

4

3

4

3

4

3

4

3

4

3

4

3

4

HDMI_DATA2P_CONN

HDMI_DATA2N_CONN

HDMI_DATA1P_CONN

HDMI_DATA1N_CONN

HDMI_DATA0P_CONN

HDMI_DATA0N_CONN

HDMI_CLKP_CONN

HDMI_CLKN_CONN

HDMI_DDC_CLK HDMI_DDC_DATA

HDMI_HPD_CONN

VCC5B_HDMI

2

1

2

1

2

1

2

1

HDMI_DDC_CLK[29] HDMI_DDC_DATA[29]

HDMI_HPD_CONN[29]

JHDMI1

ME@

1

D2+

2

D2_shield

3

D2-

4

D1+

5

D1_shield

6

D1-

7

D0+

8

D0_shield

GND0

9

D0-

GND1

10

CK+

GND2

11

CK_shield

GND3

12

CK-

13

CEC

14

Reserved

15

SCL

16

SDA

17

DDC/CEC_GND

18

+5V

19

HP_DET

LCN_AUF05-1967S10-0011

2

20 21 22 23

1

VCC5B_HDMI

for PE Old_Li

HDMI_DDC_CLK

B B

A A

HDMI_DDC_DATA

D227

1

V I/O

Ground2V BUS

3

V I/O

PUSB2X4D_SO6-6

ESD@

5

HDMI_HPD_CONN

6

V I/O

5

4

V I/O

HDMI_DATA1N_CONN

HDMI_DATA1P_CONN

HDMI_DATA2N_CONN

HDMI_DATA2P_CONN

HDMI_CLKP_CONN HDMI_CLKP_CONN

HDMI_CLKN_CONN HDMI_CLKN_CONN

HDMI_DATA0P_CONN HDMI_DATA0P_CONN

HDMI_DATA0N_CONN HDMI_DATA0N_CONN

D283

1

2

4

5

3

8

PUSB3F96_XSON10_2.5X1~D

ESD@

D284

1

2

4

5

3

8

PUSB3F96_XSON10_2.5X1~D

ESD@

10

9

7

6

10

9

7

6

4

HDMI_DATA1N_CONN

HDMI_DATA1P_CONN

HDMI_DATA2N_CONN

HDMI_DATA2P_CONN

VCC5B VCC5B_HDMI

1

2

C1426

1

0.1U_0201_6.3V6K

2

3

U110

6

IN

OUT

5

GND

ILIM

4

EN3FAULT#

TPS2553DBVR_SOT23-6

Current Limit Target : 400mA Requirement : 300mA HDMI Spec : 50mA - 500mA

2

R1119

61.9K_0201_1%

Security Clas sification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PRO PERTY OF COMPAL ELE CTRON ICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C994

1

4.7U_0402_6.3V6M

1 2

Compal Secret Data

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

HDMI CONNECTOR

Size

Document Number Rev

Custom

LA-C581P

Date: Sheet of

1

30 102Thursday, August 13, 2015

0.5

Compal LA-C581P Schematics Rev1.0

Specifications and Main Features

Frequently Asked Questions

User Manual