Compal LA-C461P Schematics

A

COMPAL CONFIDENTIAL

B

C

D

E

1 1

MODEL NAME : AAZ60
PCB NO : DAA0009Y000
BOM P/N :

GPIO MAP: Gen7 GPIO Master_1127

Beaver Creek 14" UMA

Skylake U

2 2

@ : Nopop Component

EMC@ : EMI, ESD and RF Component

@EMC@ : EMI, ESD and RF Nopop Component

CXDP@ : XDP Component

CONN@ : Connector Component

3 3

TCM@ : TPM & China TPM select

2015-09-25

REV : 1.0 (A00)

CT3@ : For 2+3 CPU HW Part
U23E@ : For 2+3 CPU Power Part

MB PCB

Part Number

DAZ1DL00100

4 4

COPYRIGHT 2014

ALL RIGHT RESERVED
REV: A00
PWB:

Description

PCB AAZ60 LA-C461P LS-C461P 02

Layout Dell logo

A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION O F DELL. IN ADDITION,
NEITHER THIS SHEET NOR TH E INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

B

PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

C

D

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

Cover Sheet

Cover Sheet

LA-C461P

LA-C461P

LA-C461P

161Tuesday, October 13, 2015

161Tuesday, October 13, 2015

161Tuesday, October 13, 2015

E

1.0

1.0

1.0

A

B

C

D

E

Reverse Type

Beaver Creek 14 Block Diagram

Memory BUS (DDR4)

1.2V DDR4 1866 MHz

1 1

EDP CONN

VGA

DP

DOCKING
CONN

2 2

DP

P38

DAI

LAN

P26

SYNATICS
VMM3320

mDP CONN

P25

DP DeMUX
PS8338

WIGIG DP

To M 2 W iG ig c ar d

P22

SATA1
DOCK_USB2.0[5]
DOCK_USB2.0[6]
DOCK_USB3.0[2]

PCIE[9] PCIE[5]

3 3

Intel Jacksonville
I219LM

Transf orm er

RJ45

P27

P27

P27

SD4.0

PCIE[3]

M.2,3042 Key B M.2,3030 Key A

WWAN/LTE/HCA

P29

USB2.0[10]

USB3.0[5]

eDP Lane x 4

HDMI 1.4b
CONN

P24

DP

Card reader
RTS5250

WLAN+BT/WIGIG

WIGIG_DP

DDI[1]

P22

DP DeMUX
PS8338

DDI[2]

P23

PCIE[10]

P28P28

PCIE[6]

SMSC SIO

P29 P31

USB2.0[8]

ECE5048

INTEL

SKYLAKE_U MCP

LPC

BC BUS

SMSC KBC
MEC5085

P32

PAG E 6 ~1 9

SPI

USB

HD Audio I/F

SATA[2]/PCIE[11],[12]

W25Q128FVSIQ

128M 4K sector

W25Q64CVSSIQ
(Reserve)

64M 4K sector

TPM1.2
NPCT650JA0YX

KB/TP CONN

FAN CONN

P39

P32

USB2.0[1]

P8

P8

P33

PI5USB2544
USB POWER SHARE

SATA/PCIE REPEATER X2

PS8558B

DDR4-SO-DIMM X2

BANK 0, 1, 2, 3

P20~21

USB2.0[1]_PS

P36

HDA Codec
ALC3235

USB2.0[9]

USB2.0[2]

USB3.0[1]

USB2.0[4]

USB3.0[4]

USB2.0[3]

USB3.0[3]

LCD Touch

Camera

USB3.0 Conn

PS(RIGHT)

USB3.0 Conn
(REAR Right)

USB3.0 Conn
(Rear LEFT)

INT.Speaker

Universal Jack

P30

Dig. MIC

M.2 2280 Key M

P34 P35

HDD Conn

P26

P26

Tro ugh e DP Ca ble

P36

P37

P37

P30

P30

Tro ugh e DP Ca ble

LID SWITCH

USH CONN

CPU&PCH XDP Port

AUTOMATIC POWER
SWITCH(APS)

P40

P33

P14

P11

DC/DC Interface

Smart Card

4 4

A

TDA8034HN

RFID/NFC

Fingerprint
CONN

SPI

SPI

USH TPM1.2
BCM58102

B

USB2.0[7]

USH board

P33

www.schematic-x.blogspot.com

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

C

D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

POWER ON/OFF

SW & LED

Block diagram

Block diagram

Block diagram

LA-C461P

LA-C461P

LA-C461P

E

261Tuesday, October 13, 2015

261Tuesday, October 13, 2015

261Tuesday, October 13, 2015

P41

P40

1.0

1.0

1.0

5

4

3

2

1

POWER STATES

State

S0 (Full ON) / M0

D D

S3 (Suspend to RAM) / M3 LOW

S4 (Suspend to DISK) / M3

S5 (SOFT OFF) / M3

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF

S5 (SOFT OFF) / M-OFF

Signal

SLP
S3#

HIGH

LOW

LOW

LOW LOW LOW

LOW LOW LOW LOW

SLP

SLP

S5#

S4#

HIGH HIGH

HIGH HIGH

HIGH HIGH

LOW

LOW

LOW

HIGH HIGH

HIGH

ALWAYS

SLP

PLANE

A#

HIGH

ON

HIGH

ON ON ON

ON ON

HIGH

ON ON

ON ON

LOW

ON

ON

M
PLANE

ON

OFF OFF OFF

OFF OFF OFF OFF

OFF OFF OFF OFF

RUN

SUS

PLANE

PLANE

ON ON ON

OFF

OFF

OFF

OFF

OFFLOW

CLOCKS

OFF

OFF

OFF

USB3.0

USB3.0-1

USB3.0-2

USB3.0-3

USB3.0-4

USB3.0-6

PM TABLE

C C

power
plane

State

S0

+5V_ALW

+3.3V_ALW

+3.3V_ALW_DSW

+3.3V_ALW_PCH +1.2V_MEM

+RTC_CELL

+1.8V_PRIM

+1.0V_PRIM

+1.0V_PRIM_CORE

+5V_ALW2

+3.3V_ALW2

+3.3V_RTC_LDO

+1.0V_MPHYGT

ON

+3.3V_CV2

+2.5V_MEM

+1.0V_VCC ST

ON ON

+5V_RUN

+3.3V_RUN

+0.6V_DDR_VTT

+1.5V_RUN

(M-OFF)

+3.3V_M +3.3V_M

ON

+VCC_CORE

+VCC_GT

+1.0VS_VCCIO

+VCC_SA

ON

SSIC

SSIC-1

SSIC-2

PCIE

PCIE-1

PCIE-2

PCIE-3

PCIE-4

PCIE-5

PCIE-6

PCIE-7

PCIE-8

PCIE-9

PCIE-10

PCIE-11

PCIE-12

SATA

SATA-0

SATA-1

SATA-1*

SATA-2

JUSB1-->Right

EDOCK PORT1

JUSB2-->Rear Lef t

JUSB3-->Rear Right

M2 3042(WWAN)USB3.0-5

NA

M.2 3042(HCA or QCA LTE)

NA

M.2 3030(WLAN)

M.2 3030(WIGIG)

NA

EDOCK E-SATA

LOM

Card Reader

M.2 2280 SSD(Reverse)
(PCIex2 or SATA)

USB PORT#DESTINATION

USH

DESTINATION

1

2

3

4

5

6

7

8

9

10

JUSB1-->Right

Camera

JUSB2-->Rear Lef t

JUSB3-->Rear Right

EDOCK PORT1

EDOCK PORT2

USH

M.2 3030(BT)

Tou c h S c re en

M2 3042(WWAN)

H

BIO

B B

A A

S3

S5 S4/AC

S5 S4/AC doesn't exist

ON

ON

ON

OFF

OFFOFF

OFF

OFF

OFF

ON

ON

OFF

OFF

OFFOFF

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DIS CLOSE D TO ANY THI RD
PART Y W ITH OU T D ELL 'S EXP RE SS WR ITT EN CO NSE NT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Port assignment

Port assignment

Port assignment

LA-C461P

LA-C461P

LA-C461P

361Tuesday, October 1 3, 2015

361Tuesday, October 1 3, 2015

361Tuesday, October 1 3, 2015

1

1.0

1.0

1.0

5

RT8207M
(PU201)

ADAPTER

D D

SYX198D

(PU301)

4

SIO_SLP_S4#

SIO_SLP_SUS#

+1.2V_MEM

TPS22961

(UZ26)

+1.0V_PRIM

LDOIN

SIO_SLP_SUS#
SIO_SLP_S4#

3

RT8207
(PU201)

0.6V_DDR_VTT_ON

+VCC_SFR_OC

+0.6V_DDR_VTT

2

TPS22961

@(UZ20)

TPS22961

(UZ19)

TPS22961

(UZ21)

MPHYP_PWR_EN

SIO_SLP_S3#
SIO_SLP_S0#

SIO_SLP_S4#

+1.0V_MPHYGT

+1.0V_VCCSTG

+1.0V_VCCST

1

CPU PWR

PCH PWR

GT3 PWR

Peripheral Device PWR

TPS62134A

CHARGER
BQ24777
(PU801)

+PWR_SRC

SYX198C

(PU100)

ALWON

+5V_ALW

+5V_ALW2

BATTERY

C C

SYX198B

(PU100)

ALWON

+3.3V_RTC_LDO

+3.3V_ALW2

+3.3V_ALW

ISL95857

(PU602)

IMVP_V R_ON

B B

IMVP_V R_ON

+VCC_GT+VCC_SA

IMVP_V R_ON

+VCC_CORE

AO6405

(QV1)

EN_INVPW R

+BL_PWR_SRC

TPS62134CRGT
(PU1200)

RUN_ON

+VCC_EDRAM

TPS62134CRGT
(PU1201)

SIO_SLP_SUS#

+VCC_EOPIO

(PU401)

TPS62134B

(PU402)

EM5209

(UZ4)

EM5209

(UZ5)

PI5USB2544

(UI3)

SY6288

(UI1)

SY6288

(UI2)

SY8032A

(PU501)

EM5209

(UZ2)

EM5209

(UZ3)

EM5209

(UZ4)

EM5209

(UZ5)

AOZ1336

@(UZ8)

TPS22967

(UZ22)

RUN_ON

SIO_SLP_SUS#

RUN_ON

AUD_PWR_EN

USB_PWR_SHR_EN#

USB_PWR_EN1#

USB_PWR_EN2#

SIO_SLP_SUS#

SIO_SLP_LAN#

AUX_EN_W OWL

@SIO_SLP_WLAN#

SIO_SLP_SUS#

@PCH_ALW_ON

RUN_ON

3.3V_WWAN_ EN

AUD_PWR_EN

A_ON

3.3V_HDD _EN

+1.0VS_VCCIO

+1.0V_PRIM_CORE

+5V_RUN

+5V_RUN_AUDIO

+5V_USB_CHG_PWR

+USB_LEFT_PW R

+USB_REAR_PWR

+1.8V_PRIM

+3.3V_LAN

+3.3V_W LAN

+3.3V_ALW_PCH

+3.3V_RUN

+3.3V_W WAN

+3.3V_RUN_AUDIO

+3.3V_M

+3.3V_HDD

TPS22961

@(UV28)

LP2301

(QV8)

EM5106VT

(UV29)

HUB_LP_EN

AP7175SP

(PU503)

APL5930

(PU502)

LP2301A

(QZ1)

3.3V_TS_EN

HUB_LP_EN

SIO_SLP_S4#

SIO_SLP_S3#

3.3V_CAM_EN#

+1.0V_RUN_VMM

+5V_TSP

+1.0V_RUN_VMM

+2.5V_MEM

+1.5V_RUN

+3.3V_CAM

TPS22967

3

(UZ18)

G524B1T11U
(UV24)

A A

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

5

4

CV2_ON

ENVCC_PC H

+3.3V_CV2

+LCDVDD

USH/B

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Power rails

Power rails

Power rails

LA-C461P

LA-C461P

LA-C461P

461Tuesday, October 13, 2015

461Tuesday, October 13, 2015

461Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

R7

R8

D D

SKL-U

R9

W2

MEM_SMBCLK

MEM_SMBDATA

SML0_SMBCLK

SML0_SMBDATA

V3W3

B4

A3

B5

A4

1K

1K

DOCK_SMB _CLK

DOCK_SMB_DAT

+3.3V_ALW_PCH

SML1_SMBDATA

SML1_SMBCLK

B6A5

3A

3A

1A

1A

C C

1B

1B

499

499

4

1K

1K

+3.3V_ALW_PCH

2N7002

2N7002

+3.3V_ALW_PCH

28

31

LOM

3

2

1

2.2K

2.2K

+3.3V_RUN

202

200

202

200

DIMMA

DIMMB

53

51

XDP

2.2K

2.2K

+3.3V_ALW

127

129

Dock

2.2K

KBC

A56

1C1CB59

PBAT_SMBCLK

PBAT_SMBDAT

2.2K

@2.2K

@2.2K

A50

B53

USH_SMBCL K

USH_SMBDAT

B B

MEC 5085

1E

1E

+3.3V_ALW

100 ohm

100 ohm

+3.3V_ALW

7

6

BATTERY

CONN

2.2K

2.2K

+3.3V_CV2

M9

L9

USH

USH/B

A49

2B

B52

2B

B50

A47

B7

A7

B48

B49

CHARGER_SMB CLK

CHARGE R_SMBDAT

GPU_SMBDAT

GPU_SMBCLK

1G

1G

A A

2D

2D

2A

2A

5

2.2K

2.2K

2.2K

2.2K

4

+3.3V_ALW

+3.3V_RUN

9

8

Charger

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

SMbus Block diagram

SMbus Block diagram

SMbus Block diagram

LA-C461P

LA-C461P

LA-C461P

561Tuesday, October 13, 2015

561Tuesday, October 13, 2015

561Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

4

3

2

1

+3.3V_RUN

CPU_DP1_CTRL_CLK

RC175 2.2K_0402_5%

RC178 2.2K_0402_5%

D D

RC176 2.2K_0402_5%

RC177 2.2K_0402_5%

C C

B B

12

CPU_DP1_CTRL_DATA

12

CPU_DP2_CTRL_CLK

12

CPU_DP2_CTRL_DATA

12

+1.0VS_VCCIO

CPU_DP1_N0<22>
CPU_DP1_P0<22>
CPU_DP1_N1<22>
CPU_DP1_P1<22>
CPU_DP1_N2<22>
CPU_DP1_P2<22>

CPU_DP1_N3<22>

CPU_DP1_P3<22>

CPU_DP2_N0<23>
CPU_DP2_P0<23>
CPU_DP2_N1<23>
CPU_DP2_P1<23>
CPU_DP2_N2<23>
CPU_DP2_P2<23>
CPU_DP2_N3<23>
CPU_DP2_P3<23>

CPU_DP1_CTRL_CLK<22>

CPU_DP1_CTRL_DATA<22> CPU_DP1_HPD <22>

CPU_DP2_CTRL_CLK<23>

CPU_DP2_CTRL_DATA<23>

@

T120

PAD~D

1 2

RC2 24.9_0402_1%

COMPENSATION PU FOR eDP

CAD Note:Trace width=20 mils , Spacing=25mil,
Max length=100 mils.

CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA

CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA

GPP_E23 CPU_DP1_HPD

EDP_COMP

UC1A

CPU@

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DD PB_CTRLCLK

L12

GPP_E19/DD PB_CTRLDATA

N7

GPP_E20/DD PC_CTRLCLK

N8

GPP_E21/DD PC_CTRLDATA

N11

GPP_E22/DD PD_CTRLCLK

N12

GPP_E23/DD PD_CTRLDATA

E52

EDP_RCOMP

SKL-U_BGA1356

SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0

UC1I

CPU@

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKL-U_BGA1356

SKL-U

DDI

DISPLAY SIDEBANDS

SKL_ULT

EDP

1 OF 20

GPP_F13/EM MC_DATA0
GPP_F14/EM MC_DATA1
GPP_F15/EM MC_DATA2
GPP_F16/EM MC_DATA3
GPP_F17/EM MC_DATA4
GPP_F18/EM MC_DATA5
GPP_F19/EM MC_DATA6
GPP_F20/EM MC_DATA7

GPP_F21/EM MC_RCLK

EDP_DISP_UTIL

GPP_E13/DD PB_HPD0
GPP_E14/DD PC_HPD1
GPP_E15/DD PD_HPD2
GPP_E16/DD PE_HPD3

GPP_E17/ED P_HPD

EDP_BKLTEN

EDP_BKLTCTL

CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3

CSI2_COMP

GPP_D4/FLA SHTRIG

EMMC

GPP_F22/EM MC_CLK

GPP_F12/EM MC_CMD

EMMC_RCOMP

9 OF 20

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXN
EDP_AUXP

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP

EDP_VDDEN

C37
D37
C32
D32
C29
D29
B26
A26

E13
B7

AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1

AM2
AM3
AP4

AT1

C47
C46
D46
C45
A45
B45
A47
B47

E45
F45

B52

G50
F50
E48
F48
G46
F46

L9
L7
L6
N9
L10

R12
R11
U13

CSI2_COMP

RC3

EMMC_RCOMP

EDP_TXN0 <26>
EDP_TXP0 <26>
EDP_TXN1 <26>
EDP_TXP1 <26>
EDP_TXN2 <26>
EDP_TXP2 <26>
EDP_TXN3 <26>
EDP_TXP3 <26>

CPU_DP1_AUXN
CPU_DP1_AUXP

CPU_DP3_AUXN
CPU_DP3_AUXP

CPU_DP2_HPD <23>

EDP_HPD <26>

PANEL_BKLEN <26>
EDP_BIA_PWM <26>
ENVDD_PCH <26,32>

1 2

100_0402_1%

1 2

RC4 200_0402_1%

Support QHD

EDP_AUXN <26>
EDP_AUXP <26>

CPU_DP2_AUXN <23>
CPU_DP2_AUXP <23>

@

T1

PAD~D

@

T2

PAD~D

CPU_DP1_AUXN

CPU_DP2_AUXN

CPU_DP2_AUXP

CPU_DP1_AUXP

EDP_HPD

CPU_DP2_HPD

+3.3V_RUN

12

RC179100K_0402_5%

12

RC181100K_0402_5%

12

RC182100K_0402_5%

12

RC180100K_0402_5%

12

RC1100K_0402_5%

12

RC312100K_0402_5%

12

@

RC242100K_0402_5%

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (1/14)

CPU (1/14)

CPU (1/14)

LA-C461P

LA-C461P

LA-C461P

661Tuesday, October 13, 2015

661Tuesday, October 13, 2015

661Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

DDR4, Ballout for side by side(Non-Interleave)

UC1B

CPU@

DDR_A_D0

AL71

DDR_A_D1
DDR_A_D2

D D

C C

B B

DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKL-U_BGA1356

SKL-U

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR CH - A

4

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]

DDR0_MA[3]
DDR0_MA[4]

DDR0_DQSN[0]

DDR0_DQSP[0]

DDR0_DQSN[1]

DDR0_DQSN[2]/DDR0_DQSN[4]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSP[3]/DDR0_DQSP[5]

DDR0_DQSN[4]/DDR1_DQSN[0]

DDR0_DQSP[4]/DDR1_DQSP[0]

DDR0_DQSN[5]/DDR1_DQSN[1]

DDR0_DQSP[5]/DDR1_DQSP[1]

DDR0_DQSN[6]/DDR1_DQSN[4]

DDR0_DQSP[6]/DDR1_DQSP[4]

DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

2 OF 20

3

DDR_A_DQS#[0..7]<20>

DDR_A_D[0..63]<20>

DDR_A_DQS[0..7]<20>

DDR_A_MA[0..16]<20>

DDR_A_CLK#0

AU53

DDR_A_CLK0

AT53

DDR_A_CLK#1

AU55

DDR_A_CLK1

AT55

DDR_A_CKE0

BA56

DDR_A_CKE1

BB56

DDR_A_CKE2

AW56

DDR_A_CKE3

AY56

DDR_A_CS#0

AU45

DDR_A_CS#1

AU43

DDR_A_ODT0

AT45

DDR_A_ODT1 DDR_B_ODT0

AT43

DDR_A_MA5

BA51

DDR_A_MA9

BB54

DDR_A_MA6

BA52

DDR_A_MA8

AY52

DDR_A_MA7

AW52

DDR_A_BG0

AY55

DDR_A_MA12

AW54

DDR_A_MA11

BA54

DDR_A_ACT#

BA55

DDR_A_BG1

AY54

DDR_A_MA13

AU46

DDR_A_MA15

AU48

DDR_A_MA14 DDR_B_MA15

AT46

DDR_A_MA16

AU50

DDR_A_BA0

AU52

DDR_A_MA2

AY51

DDR_A_BA1

AT48

DDR_A_MA10

AT50

DDR_A_MA1

BB50

DDR_A_MA0

AY50

DDR_A_MA3

BA50

DDR_A_MA4

BB52

DDR_A_DQS#0

AM70

DDR_A_DQS0

AM69

DDR_A_DQS#1

AT69

DDR_A_DQS1

AT70

DDR_A_DQS#4

BA64

DDR_A_DQS4

AY64

DDR_A_DQS#5

AY60

DDR_A_DQS5

BA60

DDR_B_DQS#0

BA38

DDR_B_DQS0

AY38

DDR_B_DQS#1

AY34

DDR_B_DQS1

BA34

DDR_B_DQS#4

BA30

DDR_B_DQS4

AY30

DDR_B_DQS#5

AY26

DDR_B_DQS5

BA26

DDR_A_ALERT#

AW50

DDR_A_PARITY

AT52

AY67

+DDR_VREF_A_DQ

AY68
BA67

AW67

DDR_A_CLK#0 <20>
DDR_A_CLK0 <20>
DDR_A_CLK#1 <20>
DDR_A_CLK1 <20>

DDR_A_CKE0 <20>
DDR_A_CKE1 <20>

@

PAD~D

@

PAD~D

DDR_A_CS#0 <20>
DDR_A_CS#1 <20>
DDR_A_ODT0 <20>
DDR_A_ODT1 <20>

DDR_A_BG0 <20>

DDR_A_ACT# <20>
DDR_A_BG1 <20>

DDR_A_BA0 <20>

DDR_A_BA1 <20>

DDR0_PAR,DDR0_ALERT# for DDR4

DDR_A_ALERT# <20>

+DDR_VREF_CA

@

PAD~D

+DDR_VREF_B_DQ

DDR_VTT_CTRL <20>

T3
T4

Check ODT schematic 0918

T132

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

UC1C

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKL-U_BGA1356

CPU@

2

SKL-U

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR CH - B

DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]

DDR1_MA[3]

DDR1_DQSN[0]/DDR0_DQSN[2]

DDR1_DQSP[0]/DDR0_DQSP[2]

DDR1_DQSN[1]/DDR0_DQSN[3]

DDR1_DQSP[1]/DDR0_DQSP[3]

DDR1_DQSN[2]/DDR0_DQSN[6]

DDR1_DQSP[2]/DDR0_DQSP[6]

DDR1_DQSN[3]/DDR0_DQSN[7]

DDR1_DQSP[3]/DDR0_DQSP[7]

DDR1_DQSN[4]/DDR1_DQSN[2]

DDR1_DQSP[4]/DDR1_DQSP[2]

DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[5]/DDR1_DQSP[3]

DDR1_MA[4]

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]

3 OF 20

DDR_B_DQS#[0..7]<21>

DDR_B_D[0..63]<21>

DDR_B_DQS[0..7]<21>

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW42

AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52

BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47

AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21

AN43
AP43
AT13
AR18
AT18
AU18

DDR_B_MA[0..16]<21>

DDR_B_CLK#0
DDR_B_CLK#1
DDR_B_CLK0
DDR_B_CLK1

DDR_B_CKE0
DDR_B_CKE1
DDR_B_CKE2
DDR_B_CKE3

DDR_B_CS#0
DDR_B_CS#1

DDR_B_ODT1

DDR_B_MA5
DDR_B_MA9
DDR_B_MA6
DDR_B_MA8
DDR_B_MA7
DDR_B_BG0
DDR_B_MA12
DDR_B_MA11
DDR_B_ACT#
DDR_B_BG1

DDR_B_MA13

DDR_B_MA14
DDR_B_MA16
DDR_B_BA0
DDR_B_MA2
DDR_B_BA1
DDR_B_MA10
DDR_B_MA1
DDR_B_MA0
DDR_B_MA3
DDR_B_MA4

DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS7

DDR_B_ALERT#
DDR_B_PARITY
DDR_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

1

DDR_B_CLK#0 <21>
DDR_B_CLK#1 <21>
DDR_B_CLK0 <21>
DDR_B_CLK1 <21>

DDR_B_CKE0 <21>
DDR_B_CKE1 <21>

@

T5

PAD~D

@

T6

PAD~D

DDR_B_CS#0 <21>
DDR_B_CS#1 <21>
DDR_B_ODT0 <21>
DDR_B_ODT1 <21>

Check ODT schematic 0918

DDR_B_BG0 <21>

DDR_B_ACT# <21>
DDR_B_BG1 <21>

DDR_B_BA0 <21>

DDR_B_BA1 <21>

DDR1_PAR,DDR1_ALERT# for DDR4

DDR_B_ALERT# <21>DDR_A_PARITY <20>
DDR_B_PARITY <21>
DDR_DRAMRST# <20>

DDR4 COMPENSATION SIGNALS

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil

A A

1 2

RC5 121_0402_1%

1 2

RC6 80.6_0402_1%

1 2

RC7 100_0402_1%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (2/14)

CPU (2/14)

CPU (2/14)

LA-C461P

LA-C461P

LA-C461P

761Tuesday, October 13, 2015

761Tuesday, October 13, 2015

761Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236

PCH_SPI_CLK
PCH_SPI_D1

1 2

PCH_SPI_DO_XDP<14>
PCH_SPI_DO2_XDP<14>

D D

+3.3V_RUN

10K_0402_5%

12

RC267@

10K_0402_5%

12

RC268

DIMM Detect

HIGH
LOW

C C

PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R

33_0402_5%

1 2

1 2

B B

A A

RC10 1K_0402_1%
RC11 1K_0402_1%

ONE_DIMM#

1 DIMM
2 DIMM

RC28

@EMC@

33P_0402_50V8J

CC7

@EMC@

1 2

PCH_SPI_CS#2<33>

+3.3V_RUN

12

SIO_RCIN#<32>

+3.3V_RUN

33_0402_5%

RC29

@EMC@

1 2

33P_0402_50V8J

CC8

@EMC@

1 2

PCH_SPI_CS#0_R1

PCH_SPI_D2_R1 PCH_SPI_CLK_0_R

PCH_SPI_CS#1_R1

PCH_SPI_D2_R1

MEDIACARD_IRQ#<28>

PCH_CL_DATA1<29>

RC13

10K_0402_5%

IRQ_SERIRQ<31,32>

RC21 10K_0402_1%

+3.3V_SPI

@

@

@

RC37 0_0402_5%

@

RC39 33_0402_5%

RC42 0_0402_5%

@

RC43 33_0402_5%

@

PCH_SPI_D0
PCH_SPI_D2
PCH_SPI_D3
PCH_SPI_CS#0
PCH_SPI_CS#1
PCH_SPI_CS#2

TPM_PIRQ#<33>

PCH_CL_CLK1<29>

PCH_CL_RST1#<29>

1 2

RC30 1K_0402_5%

RC31 1K_0402_5%

RC316 1K_0402_5%

1 2

1 2

1 2

1 2

ONE_DIMM#

PCH_SPI_D2_R1

1 2

PCH_SPI_D3_R1

1 2

PCH_SPI_D3_R1

1 2

03/02:follow Intel MOW_2015WW 06

4

UC1E

AV2

SPI0_CLK

AW3

SPI0_MISO

AV3

SPI0_MOSI

AW2

SPI0_IO2

AU4

SPI0_IO3

AU3

SPI0_CS0#

AU2

SPI0_CS1#

AU1

SPI0_CS2#

M2

GPP_D1/SPI1 _CLK

M3

GPP_D2/SPI1 _MISO

J4

GPP_D3/SPI1 _MOSI

V1

GPP_D21/SP I1_IO2

V2

GPP_D22/SP I1_IO3

M1

GPP_D0/SPI1 _CS#

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

AW13

GPP_A0/RCIN #

AY11

GPP_A6/SER IRQ

SKL-U_BGA1356

PCH_SPI_CS#0_R2
PCH_SPI_D1_0_R
PCH_SPI_D2_0_R

PCH_SPI_CS#1_R2
PCH_SPI_D1_1_R
PCH_SPI_D2_1_R

CPU@

SPI - FLASH

SPI - TOUCH

C LINK

PCH_SPI_D1_R1<33>

PCH_SPI_D0_R1<33>

PCH_SPI_CLK_R1<33>

128Mb Flash ROM

1

/CS

2

IO1

3

IO2

4

GND

W25Q128FVSIQ_SO8

64Mb Flash ROM

@

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

W25Q64FVSSIQ_SO8

UC5

UC6

SKL-U

PCH_SPI_D1_R1
PCH_SPI_D0_R1
PCH_SPI_CLK_R1
PCH_SPI_D3_R1

PCH_SPI_D3_R1
PCH_SPI_CLK_R1
PCH_SPI_D0_R1
PCH_SPI_D1_R1

VCC

IO3

CLK

IO0

VCC

/HOLD(IO3)

CLK

DI(IO0)

SMBUS, SMLINK

GPP_B23/SM L1ALERT#/PCHH OT#

LPC

GPP_A14/SU S_STAT#/ESPI_RE SET#

GPP_A9/CLK OUT_LPC0/ESPI_CL K

SOFTWARE TAA

RPC1

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

RPC2

@

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

+3.3V_SPI

1 2

0.1U_0201_10V6K

8

PCH_SPI_D3_0_R

7
6

PCH_SPI_D0_0_R

5

+3.3V_SPI

@

1 2

0.1U_0201_10V6K

8

PCH_SPI_D3_1_R

7

PCH_SPI_CLK_1_R

6

PCH_SPI_D0_1_R

5

3

GPP_C0/SMB CLK

GPP_C1/SMB DATA

GPP_C2/SMB ALERT#

GPP_C3/SML 0CLK

GPP_C4/SML 0DATA

GPP_C5/SML 0ALERT#

GPP_C6/SML 1CLK

GPP_C7/SML 1DATA

GPP_A1/LAD 0/ESPI_IO0
GPP_A2/LAD 1/ESPI_IO1
GPP_A3/LAD 2/ESPI_IO2
GPP_A4/LAD 3/ESPI_IO3

GPP_A5/LFR AME#/ESPI_CS#

GPP_A10/CLK OUT_LPC1

GPP_A8/CLK RUN#

PCH_SPI_D1_0_R
PCH_SPI_D0_0_R
PCH_SPI_CLK_0_R
PCH_SPI_D3_0_R

PCH_SPI_D3_1_R
PCH_SPI_CLK_1_R
PCH_SPI_D0_1_R
PCH_SPI_D1_1_R

CC9

CC10

5 OF 20

+3.3V_SPI

MEM_SMBCLK

R7

MEM_SMBDATA

R8

PCH_SMB_ALERT#

R10

SML0_SMBCLK

R9

SML0_SMBDATA

W2

GPP_C5

W1

SML1_SMBCLK

W3

SML1_SMBDATA

V3

GPP_B23

AM7

LPC_AD0

AY13

LPC_AD1

BA13

LPC_AD2

BB13

LPC_AD3

AY12

LPC_FRAME#

BA12

SUS_STAT#

BA11

PCI_CLK_LPC0

AW9

PCI_CLK_LPC1

AY9
AW11

CLKRUN# <31,32>

RC32 0_0402_5%

@

RC33 0_0402_5%

RC34 0_0402_5%

RC35 0_0402_5%

RC36 0_0402_5%

RC38 0_0402_5%

RC40 0_0402_5%

+3.3V_ALW_PCH

RC41 0_0402_5%

Reserve

12

12

12

12

12

12

12

RC289 0_0402_5%

@

+3.3V_M

RC276 0_0402_5%

@

12

SML0_SMBCLK <27>

SML0_SMBDATA <27>

SML1_SMBCLK <32>

SML1_SMBDATA <32>

LPC_AD0 <31,32>
LPC_AD1 <31,32>
LPC_AD2 <31,32>
LPC_AD3 <31,32>

LPC_FRAME# <31,32>

1 2

RC16EMC@ 22_0402_5%

1 2

RC18EMC@ 22_0402_5%

1 2

RC22EMC@ 22_0402_5%

1 2

RC24EMC@ 22_0402_5%

CLK_PCI_5048

CLK_PCI_MEC

CLK_PCI_LPDEBUG

CLK_PCI_DOCK

Reserve for RF

PCH_SPI_CS#1_R1
PCH_SPI_CS#1
PCH_SPI_D0_R1
PCH_SPI_D0
PCH_SPI_D1_R1
PCH_SPI_D1
PCH_SPI_CLK_R1
PCH_SPI_CLK
PCH_SPI_CS#0_R1
PCH_SPI_CS#0
PCH_SPI_D2_R1
PCH_SPI_D2
PCH_SPI_D3_R1
PCH_SPI_D3

12

8/27 sch review

12

+3.3V_SPI_R

2

12

EMC@27P_0402_50V8J

CC3

12

@EMC@27P_0402_50V8J

CC4

12

EMC@27P_0402_50V8J

CC5

12

EMC@27P_0402_50V8J

CC6

E-T_6705K-Y20N-00L

22

GND2

21

GND1

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

JSPI1

CONN@

MEM_SMBCLK

MEM_SMBDATA

3 4

DMN65D8LDW-7_SOT363-6

CLK_PCI_5048 <31>

CLK_PCI_MEC <32>

CLK_PCI_LPDEBUG <32>

CLK_PCI_DOCK <38>

GPP_B23 GPP_B23_Q

SIO_SLP_A#<11,32>

SIO_SLP_SUS#<11,17,18,32,41,45,46,47,53>

1

+3.3V_RUN

2

1

6

5

DMN65D8LDW-7_SOT363-6

QC2B

DDR_XDP_WAN_SMBCLK <14,20,21>

QC2A

DDR_XDP_WAN_SMBDAT <14,20,21>

DDR_XDP_WAN_SMBDAT

DDR_XDP_WAN_SMBCLK

MEM_SMBCLK

MEM_SMBDATA

SML1_SMBCLK

SML1_SMBDATA

SML0_SMBCLK

SML0_SMBDATA

SUS_STAT#

Reserve

SML0_SMBCLK

SML0_SMBDATA

CLKRUN#

PCH_SMB_ALERT#

1 2

RC12 1K_0402_5%

1 2

RC14 1K_0402_5%

1 2

RC15 1K_0402_5%

1 2

RC17 1K_0402_5%

1 2

RC347 499_0402_1%

1 2

RC348 499_0402_1%

1 2

RC26@ 10K_0402_5%

11/2 0 IN TE L R EV IE W

1 2

RC19 499_0402_1%

@

1 2

RC20 499_0402_1%

@

8/5 CKLT0.9

1 2

RC27 8.2K_0402_5%

1 2

RC23 2.2K_0402_5%

TLS C ONFIDENTIALITY

RC25 10K_0402_5%@

ENABLE
DISABLE

1 2

HIGH
LOW(DEFAULT)

WEAK INTERNAL PD

GPP_C5

EC interfac e

HIGH
LOW(DEFAULT)

WEAK INTERNAL PD

+3.3V_RUN +3.3V_ALW_PCH

11/2 9 ,M OW f or D CI

1 2

@

RC339

0_0402_5%

@

RC340

0_0402_5%

150K_0402_5%

@

RC326

12

12

RC327

@

0_0402_5%

S

G

EXI BOOT STALL BYPASS

HIGH
LOW(DEFAULT)

WEAK INTERNAL PD

ESPI

LPC

12

D

13

QC3

@

L2N7002WT1G_SC-70-3

2

ENABLE D
DIABLED

+3.3V_RUN

12

RC3182.2K_0402_5%

12

RC3192.2K_0402_5%

+3.3V_ALW_PCH

+3.3V_LAN

+3.3V_RUN

+3.3V_ALW_PCH

+3.3V_ALW_PCH

02/25 ,INTEL mail for DCI

150K_0402_5%

RC317

1 2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (3/14)

CPU (3/14)

CPU (3/14)

LA-C461P

LA-C461P

LA-C461P

861Tuesday, October 13, 2015

861Tuesday, October 13, 2015

861Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

4

3

2

1

+3.3V_ALW_PCH

+3.3V_RUN

UC1F

CPU@

LPSS ISH

AN8

D D

C C

RC270 10K_0402_5%

RC282 100K_0402_5%

RC279 10K_0402_5%

RC292 10K_0402_5%

RC237 10K_0402_5%

+3.3V_ALW_PCH

RC283 10K_0402_5%

1 2

RC330 49.9K_0402_1%@

1 2

RC331 49.9K_0402_1%@

+3.3V_ALW_PCH

1 2

1 2

1 2

1 2

12

1 2

1 2

RC186 4.7K_0402_5%

@

3.3V_TS_EN

AUD_PWR_EN

HOST_SD_WP#

SIO_EXT_SCI#

SIO_EXT_WAKE#

UART2_RXD

UART2_TXD

NRB_BIT

Reserve

8/20

NRB_BIT

3.3V_TP_EN

Reserve

SIO_EXT_SCI#<32>

3.3V_TS_EN<26>

3.3V_HDD_EN<41>

UART0_TXD<32>

HOST_SD_WP#<28>

SIO_EXT_WAKE#<32>

I2C_1_SDA<39>

3.3V_HDD_EN

UART2_RXD
UART2_TXD

Reserve

I2C_1_SCL<39>

3.3V_TP_EN

GPP_B15/GSPI0 _CS#

AP7

GPP_B16/GSPI0 _CLK

AP8

GPP_B17/GSPI0 _MISO

AR7

GPP_B18/GSPI0 _MOSI

AM5

GPP_B19/GSPI1 _CS#

AN7

GPP_B20/GSPI1 _CLK

AP5

GPP_B21/GSPI1 _MISO

AN5

GPP_B22/GSPI1 _MOSI

AB1

GPP_C8/UAR T0_RXD

AB2

GPP_C9/UAR T0_TXD

W4

GPP_C10/UA RT0_RTS#

AB3

GPP_C11/UA RT0_CTS#

AD1

GPP_C20/UA RT2_RXD

AD2

GPP_C21/UA RT2_TXD

AD3

GPP_C22/UA RT2_RTS#

AD4

GPP_C23/UA RT2_CTS#

U7

GPP_C16/I2C 0_SDA

U6

GPP_C17/I2C 0_SCL

U8

GPP_C18/I2C 1_SDA

U9

GPP_C19/I2C 1_SCL

AH9

GPP_F4/I2C2_ SDA

AH10

GPP_F5/I2C2_ SCL

AH11

GPP_F6/I2C3_ SDA

AH12

GPP_F7/I2C3_ SCL

AF11

GPP_F8/I2C4_ SDA

AF12

GPP_F9/I2C4_ SCL

SKL-U_BGA1356

NO REBOOT STRAP

HIGH
LOW(DEFAULT)

Weak IPD

No REBOOT

REBOOT ENABLE

SKL-U

GPP_D9
GPP_D10
GPP_D11
GPP_D12

GPP_D5/ISH_ I2C0_SDA
GPP_D6/ISH_ I2C0_SCL

GPP_D7/ISH_ I2C1_SDA
GPP_D8/ISH_ I2C1_SCL

GPP_F10/I2C5 _SDA/ISH_I2C2_SD A

GPP_F11/I2C5 _SCL/ISH_I2C2_SC L

GPP_D13/ISH _UART0_RXD/SM L0BDATA/I2C4B_ SDA

GPP_D14/ISH _UART0_TXD/SM L0BCLK/I2C4B_SC L

GPP_D15/ISH _UART0_RTS#

GPP_D16/ISH _UART0_CTS#/SM L0BALERT#

GPP_C12/UA RT1_RXD/ISH_UA RT1_RXD

GPP_C13/UA RT1_TXD/ISH_UA RT1_TXD
GPP_C14/UA RT1_RTS#/ISH_U ART1_RTS#
GPP_C15/UA RT1_CTS#/ISH_U ART1_CTS#

GPP_A18/ISH _GP0
GPP_A19/ISH _GP1
GPP_A20/ISH _GP2
GPP_A21/ISH _GP3
GPP_A22/ISH _GP4
GPP_A23/ISH _GP5

GPP_A12/BM _BUSY#/ISH_GP6

6 OF 20

P2
P3
P4
P1

M4
N3

N1
N2

AD11
AD12

U1
U2
U3
U4

AC1
AC2
AC3
AB4

AY8
BA8
BB7
BA7
AY7
AW7
AP13

DIMM_TYPE

CLKDET#

TPM_TYPE

DIMM_TYPE

9/24: Reserve for embedded locat i on ,r ef er I nt el P DG 0 . 9

ISH_I2C2_SD A <29>
ISH_I2C2_SC L < 29>

ISH_UART0 _RXD <29>

ISH_UART0 _TXD < 29>
ISH_UART0 _RTS# <29>

ISH_UART0 _CTS# <29>

LCD_CBL_DET# <26>

@

T121

PAD~D

VMM3320_LPM_DIS <25>

KB_DET# <39>
AUD_PWR_EN <30>

IR_CAM_D ET# <26>

+3.3V_ALW_PCH

RC341

@

10K_0402_5%

1 2

WWAN

WLAN

8/21

KB_DET#

LCD_CBL_DET#

IR_CAM_D ET#

TPM_TYPE

1 2

RC288 10K_0402_5%

1 2

RC287 100K_0402_5%

1 2

RC345 100K_0402_5%

1 2

RC349 100_0402_1%TCM@

RC349

POP

DEPOP

+3.3V_RUN

China TPM

TPM

B B

+3.3V_ALW_PCH

12

RC184

@

8.2K_0402_5%

3.3V_HDD_EN

RC342
10K_0402_5%

1 2

DIMM TYPE

HIGH

DDR3L

LOW DDR4

BOOT BIOS Dest i nat i on(Bi t 10)

HIGH
LOW(DEFAULT)

A A

LPC
SPI

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (4/14)

CPU (4/14)

CPU (4/14)

LA-C461P

LA-C461P

LA-C461P

961Tuesday, October 13, 2015

961Tuesday, October 13, 2015

961Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

4

3

2

1

UC1H

CPU@

PCIE/USB3/SATA

D D

WWAN ----->

WWAN --->

WIGIG--->

C C

E DOCK ESATA--->

10/100/1G LAN --->

Card Reader --->

+3.3V_RUN

8/5 CKLT0.9

RC245 10K_0402_5%

M2 2280 SSD(Reverse) --->

B B

USB3_PRX_DTX_N5<29>

USB3_PRX_DTX_P5<29>
USB3_PTX_DRX_N5<29>
USB3_PTX_DRX_P5<29>

PCIE_PRX_DTX_N3<29>

PCIE_PRX_DTX_P3<29>
PCIE_PTX_DRX_N3<29>
PCIE_PTX_DRX_P3<29>

PCIE_PRX_DTX_N5<29>

PCIE_PRX_DTX_P5<29>
PCIE_PTX_DRX_N5<29>
PCIE_PTX_DRX_P5<29>

PCIE_PRX_DTX_N6<29>

PCIE_PRX_DTX_P6<29>
PCIE_PTX_DRX_N6<29>
PCIE_PTX_DRX_P6<29>

SATA_PRX_DTX_N1<38>

SATA_PRX_DTX_P1<38>
SATA_PTX_DRX_N1<38>
SATA_PTX_DRX_P1<38>

PCIE_PRX_DTX_N9<27>

PCIE_PRX_DTX_P9<27>
PCIE_PTX_DRX_N9<27>
PCIE_PTX_DRX_P9<27>

PCIE_PRX_DTX_N10<28>

PCIE_PRX_DTX_P10<28>
PCIE_PTX_DRX_N10<28>
PCIE_PTX_DRX_P10<28>

1 2

RC45 100_0402_1%

1 2

PCIE_PRX_DTX_N11<34>
PCIE_PRX_DTX_P11<34>
PCIE_PTX_DRX_N11<34>
PCIE_PTX_DRX_P11<34>
PCIE_PRX_DTX_N12<34>
PCIE_PRX_DTX_P12<34>
PCIE_PTX_DRX_N12<34>
PCIE_PTX_DRX_P12<34>

PCIE_RCOMPN
PCIE_RCOMPP

CPU_XDP_PRDY#<14>

CPU_XDP_PREQ#<14>

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA #

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL-U_BGA1356

SKL-U

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB 2_OC0#
GPP_E10/US B2_OC1#
GPP_E11/US B2_OC2#
GPP_E12/US B2_OC3#

GPP_E4/DEV SLP0
GPP_E5/DEV SLP1
GPP_E6/DEV SLP2

GPP_E0/SAT AXPCIE0/SATAGP0
GPP_E1/SAT AXPCIE1/SATAGP1
GPP_E2/SAT AXPCIE2/SATAGP2

GPP_E8/SAT ALED#

USB3_1_RXN
USB3_1_RXP

USB3_1_TXN
USB3_1_TXP

USB3_4_RXN
USB3_4_RXP

USB3_4_TXN
USB3_4_TXP

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB2_COMP

USB2_ID

8 OF 20

H8
G8
C13
D13

J6
H6
B13
A13

J10
H10
B15
A15

E10
F10
C15
D15

AB9
AB10

AD6
AD7

AH3
AJ3

AD9
AD10

AJ1
AJ2

AF6
AF7

AH1
AH2

AF8
AF9

AG1
AG2

AH7
AH8

AB6
AG3

USB2_VBUSSENSE

AG4

A9
C9
D9

USB_OC3#

B9

J1
J2
J3

H2

SATAGP0

H3

SATAGP1

G4

H1

USBCOMP
USB2_ID

USB3_PRX_DTX_N1 <36>

USB3_PRX_DTX_P1 <36>
USB3_PTX_DRX_N1 <36>

USB3_PTX_DRX_P1 <36>

USB3_PRX_DTX_N2 <38>

USB3_PRX_DTX_P2 <38>
USB3_PTX_DRX_N2 <38>

USB3_PTX_DRX_P2 <38>

USB3_PRX_DTX_N3 <37>

USB3_PRX_DTX_P3 <37>
USB3_PTX_DRX_N3 <37>

USB3_PTX_DRX_P3 <37>

USB3_PRX_DTX_N4 <37>

USB3_PRX_DTX_P4 <37>
USB3_PTX_DRX_N4 <37>

USB3_PTX_DRX_P4 <37>

USB20_N1 <36>
USB20_P1 <36>

USB20_N2 <26>
USB20_P2 <26>

USB20_N3 <37>
USB20_P3 <37>

USB20_N4 <37>
USB20_P4 <37>

USB20_N5 <38>
USB20_P5 <38>

USB20_N6 <38>
USB20_P6 <38>

USB20_N7 <33>
USB20_P7 <33>

USB20_N8 <29>
USB20_P8 <29>

USB20_N9 <26>
USB20_P9 <26>

USB20_N10 <29>
USB20_P10 <29>

1 2

RC44 113_0402_1%

1 2

RC337 0_0402_5%

@

1 2

RC338 1K_0402_5%

USB_OC0# <36>
USB_OC1# <37>
USB_OC2# <37>

Reserve

M2_DEVSLP <35>

Reserve
Reserve

IFDET_SAT A#_PCIE <12,34,3 5>

PCH_SATA_LED# <40>

-----> Ext USB3 Port 1 Charge(RIGHT)

-----> EDOCK

-----> Ext USB3 Port 2(REAR LEFT)

-----> Ext USB3 Port 3(REAR RIGHT)

-----> Ext USB Port 1 Charge(RIGHT)

-----> CameraWLAN --->

-----> Ext USB Port 2(REAR LEFT)

-----> Ext USB Port 3(REAR RIGHT)

-----> EDOCK PORT1

-----> EDOCK PORT2

-----> USH

-----> BT

-----> LCD Touch

-----> M2 3042(WWAN)

2/5 for DCI,#545659 SKL_PCH-LP EDS Rev1.2.
(Rev1.0 doesn’ t wit h bel ow not es)

8/19 for layout routing change

USB_OC3#
USB_OC0#
USB_OC1#
USB_OC2#

RPC3

4 5
3
2
1

10K_8P4R_5%

6
7
8

+3.3V_ALW_PCH

+3.3V_RUN

CAM_MIC_CBL_DET#<12,26>

A A

CAM_MIC_CBL_DET#
PCH_SATA_LED#

SATAGP0
SATAGP1

RPC4

4 5
3
2
1

10K_8P4R_5%

6
7
8

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (5/14)

CPU (5/14)

CPU (5/14)

LA-C461P

LA-C461P

LA-C461P

10 61Tuesday, October 13, 2015

10 61Tuesday, October 13, 2015

10 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

CLK_PCIE_N0<29>

WWAN

D D

WLAN--- >

WIGIG--->

SATA EXPRESS HDD--->

LAN--->

MMI --->

C C

11/2 0 IN TE L R EV IE W

+3.3V_LAN

1 2

RL70 10K_0402_5%

@

+3.3V_ALW_DSW

+1.0V_VCCST

+3.3V_ALW_PCH

B B

1 2

RC323 10K_0402_5%

1 2

RC71 1K_0402_5%

1 2

RC74 10K_0402_5%@

10/6 depop, prevent singal step.

@

T9

PAD~D

H_CPUPWRGD H_VCCST_PWRGD

100P_0402_50V8J

12

12

CC300EMC@

ESD Request:place near CPU side

CLK_PCIE_P0<29>

CLKREQ_PCIE#0<29>

CLK_PCIE_N1<29>

CLK_PCIE_P1<29>

CLKREQ_PCIE#1<29>

CLK_PCIE_N2<29>

CLK_PCIE_P2<29>

CLKREQ_PCIE#2<29>

CLK_PCIE_N3<35>

CLK_PCIE_P3<35>

CLKREQ_PCIE#3<35>

CLK_PCIE_N4<27>

CLK_PCIE_P4<27>

CLKREQ_PCIE#4<27>

CLK_PCIE_N5<28>
CLK_PCIE_P5<28>

CLKREQ_PCIE#5<28>

LAN_WAKE#

H_VCCST_PWRGD

ME_SUS_PWR_ACK

H_VCCST_PWRGD<14,32>

100P_0402_50V8J

CC301EMC@

1 2

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_ALW_DSW

+3.3V_RUN

RC75 10K_0402_5%

RC189 10K_0402_5%

1 2

RC47 10K_0402_5%

1 2

RC50 10K_0402_5%

1 2

RC59 10K_0402_5%

1 2

RC51 10K_0402_5%

1 2

RC190 10K_0402_5%

PCH_PLTRST#

1 2

RC67 1K_0402_5%

1 2

RC225@ 8.2K_0402_5%

PCH_RSMRST#_Q<14,39>

1 2

1 2

RC77 1K_0402_5%@

1 2

RC78 60.4_0402_1%

RESET_OUT#<14,32>
PCH_PWROK<48>

PCH_DPWROK<32> POWER_SW#_MB<32,40>

ME_SUS_PWR_ACK<32>

PCH_PCIE_WAKE#<31,32>

PM_LANPHY_ENABLE<27>

3.3V_CAM_EN#<26>

UC7

TC7SH08FU_SSOP5~D

PCH_PCIE_WAKE#

ME_RESET#

PCH_PLTRST#
SYS_RESET#

PCH_RSMRST#_Q

H_CPUPWRGDH_CPUPWRGD_R
VCCST_PWRGD

SUSACK#<32>

LAN_WAKE#<27,32>

1 2

RC311 10K_0402_5%

8/28 schematic review

1

2

RC215

POP

NO Support Deep sleep

DE-POP

0.01UF_0402_25V7K

12

CC266

Support Deep sleep

1 2

RC215 0_0402_5%@

100K_0402_1%

RC220

XDP_DBRESET#<14>

XDP_DBRESET#

RC227@ 8.2K_0402_5%

PCH_DPWROK PCH_RSMRST#_Q

A A

1

2

if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)

5

4

UC1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRC CLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRC CLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRC CLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRC CLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRC CLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SR CCLKREQ5#

SKL-U_BGA1356

12

RC610_0402_5%

12

RC62 @0_0402_5%

12

RC64 @0_0402_5%

12

RC244 @0_0402_5%

+3.3V_ALW_PCH

5

P

B

PCH_PLTRST#_AND

4

O

A

G

3

UC1K

AN10

GPP_B13/PLT RST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SU SWARN#/SUSP WRDNACK

AP11

GPP_A15/SU SACK#

BB15

WAKE#

AM15

GPD2/LAN_W AKE#

AW17

GPD11/LANP HYPC

AT15

GPD7/RSVD

SKL-U_BGA1356

RC290 0_0402_5%

@

ME_RESET#

12

4

CPU@

@

12

RC65

@

100K_0402_5%

CPU@

1 2

+3.3V_RUN

5

1

P

B

2

A

G

74AHC1G09GW_TSSOP5

3

SKL_ULT

CLOCK SIGNALS

PLTRST_VMM2320# <25>
PLTRST_LAN# <27>

PLTRST_5048# <31>
PCH_PLTRST#_EC <32>

PCH_PLTRST#_AND <28,29,33,35>

SYSTEM POWER MANAGEMENT

SYS_RESET#_R

4

O

UC12@

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

SKL-U

GPP_B11/EXT _PWR_GATE#

1 2

RC224 1K_0402_5%

3

1 2

SUSCLK

RC48 1K_0402_5%@

CLK_ITPXDP_N

F43

CLK_ITPXDP_P

E43

XTAL24_IN

RTCX1
RTCX2

SRTCRST#

RTCRST#

10 OF 20

BA17

E37
E35

E42

AM18
AM20

AN18
AM16

XTAL24_IN
XTAL24_OUT

XCLK_BIASREF

PCH_RTCX1
PCH_RTCX2

SRTCRST#

PCH_RTCRST#

GPD8/SUSC LK

XTAL24_OUT

XCLK_BIASREF

CMOS1 must take care sh ort & touch risk on layout placement

PCH_PLTRST#

PCH_PLTRST#_AND

8/21 can change to 10K for merge to RP

GPP_B12/SLP _S0#

GPD4/SLP_S 3#
GPD5/SLP_S 4#

GPD10/SLP_S 5#

SLP_SUS#

SLP_LAN#

GPD9/SLP_W LAN#

GPD6/SLP_A #

GPD3/PWR BTN#

GPD1/ACPR ESENT

GPD0/BATLOW #

GPP_A11/PM E#

INTRUDER #

GPP_B2/VRA LERT#

11 OF 20

+3.3V_RUN

12

RC291

10K_0402_5%

@

SYS_RESET#

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

RC60 0_0402_5%

@

@

SIO_SLP_LAN#

PCH_BATLOW#

AC_PRESENT

SIO_SLP_S0#

AT11
AP15
BA16
AY16

AN15
AW15
BB17
AN16

BA15
AY15

PCH_BATLOW#

AU13

AU11

PME#

AP16

INTRUDER #

AM10
AM11

VRALERT#

3

RC325 0_0402_5%

1 2

RC297 0_0402_5%

@

1 2

RC298 0_0402_5%

@

SUSCLK <29,35>

1 2

RC52 2.7K_0402_1%

1 2

@

RC324 59_0402_1%

546765_546765_2014WW48_Skylake_M OW_Rev_1_ 0

1 2

RC56 20K_0402_5%

1 2

CC24 1U_0402_6.3V6K

1 2

RC57 20K_0402_5%

1 2

CC25 1U_0402_6.3V6K

1

1

2

SHORT PADS~D

@

CMOS1

12

12

1 2

RC344 10K_0402_5%

@

1 2

RC68 10K_0402_5%

@

1 2

RC72 8.2K_0402_5%

1 2

RC243 10K_0402_5%

SIO_SLP_S0# <17,33,46>
SIO_SLP_S3# <17,32,47>
SIO_SLP_S4# <17,32,44,54>
SIO_SLP_S5# <32>

SIO_SLP_SUS# <8,17,18,32,41,45,46,47,53>
SIO_SLP_LAN# <32,41>
SIO_SLP_WLAN# <31,41>
SIO_SLP_A# <8,32>

SIO_PWRBTN# <14,32>

AC_PRESENT <32>

PAD~D

MPHYP_PWR_EN <18,45>

connect to VCCMPHYGTAON_1P0 enable pin

+3.3V_ALW

+3.3V_ALW_DSW

SLP_S0# for support connect stand by mode

@

T115

CLK_ITPXDP_N_R <14>
CLK_ITPXDP_P_R <14>

+1.0V_CLK5

For Skylake, pop RC52,depop RC324
For Cannonlake, pop RC324,depop RC52

2

PLTRST_TPM# <33>

+3.3V_ALW_PCH

8/21 CRB1.0 change to 0603 1/10W
10/30 move to EC side

2

1M_0402_1%

RC46

XTAL24_IN
XTAL24_OUT XTAL24_OUT_R

PCH_RTCX1
PCH_RTCX2

+RTC_CELL

INTRUDER #

VRALERT#

1 2

RC69 1M_0402_5%

1 2

RC73 10K_0402_5%

SYS_RESET#

0.1U_0402_25V6

12

ESD Request:place near CPU side

1 2

1 2

RC295 0_0402_5%

@

For Skylake,YC1 24 MHz (50 Ohm ESR)
For Cannonlake,YC1 38.4 MH z (30 Ohm ESR)

546765_546765_2014WW48_Skylake_M OW_Rev_1_ 0

RC54
10M_0402_5%

1 2

1 2

RC296 0_0402_5%

@

+RTC_CELL

+3.3V_ALW_PCH

+3.3V_ALW_PCH

+3.3V_ALW_DSW

+3.3V_ALW_DSW

@EMC@

CC302

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

1

CC21

1 2

3

1

PCH_RTCX2_R

YC2 c hange SJ1 0000LV 00 as main

SIO_SLP_S3#

SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#

PCH_RTCRST#

SYS_RESET#

SIO_SLP_S0#

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

CPU (6/14)

CPU (6/14)

CPU (6/14)

LA-C461P

LA-C461P

LA-C461P

15P_0402_50V8J

4

YC1
24MHZ_12PF_X3G024000DC1H

2

12

CC22

1 2

15P_0402_50V8J

CC23

1 2

15P_0402_50V8J

YC2

32.768KHZ_12.5PF_9H03200042

ESR MAX=50k ohm

CC26

1 2

12P_0402_50V8J

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

ACES_50506-01841-P01

1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GND
GND

CONN@

11 61Tuesday, October 13, 2015

11 61Tuesday, October 13, 2015

11 61Tuesday, October 13, 2015

JAPS1

1.0

1.0

1.0

5

+1.0V_VCCST

11/2 7 D G1 .0

1 2

RC79 49.9_0402_1%

@

1 2

RC80 1K_0402_5%

+1.0V_VCCSTG

8/19 DG0.9

1 2

RC83 1K_0402_5%

+3.3V_RUN

D D

+3.3V_RUN

+3.3V_ALW_PCH

C C

+3.3V_RUN

B B

+3.3V_ALW_PCH +3.3V_ALW_PCH

1 2

RC272 10K_0402_5%

RPC5

4 5
3
2
1

10K_8P4R_5%

1 2

RC346 10K_0402_5%

1 2

RC278 10K_0402_5%

1 2

RC183 8.2K_0402_5%@

H_CATERR#

H_THERMTRIP#

H_PROCHOT#

TOUCHPAD_INTR#

IFDET_SAT A#_PCIE

6

TOUCH_SCREEN_PD#

7
8

SIO_EXT_SMI#

CONTACTLESS_DET#

SPKR

HDA_SYNC_R<30>

HDA_BIT_CLK_R<30>

HDA_SDOUT_R<30>

22P_0402_50V8J

Close to RC93

H_PROCHOT#<32,48,50>

H_THERMTRIP#<20,21,32>

IFDET_SAT A#_PCIE <10,34,3 5>

RC92 33_0402_5%
RC93 33_0402_5%EMC@
RC94 33_0402_5%

ME_FWP

RC223 1K_0402_5%

HDA_RST#_R<30>

HDA_BIT_CLK_R

1

CC27

2

RC187 4.7K_0402_5%@

PECI_EC<32>

8/19 DG0.9

1 2

RC84 499_0402_1%

SIO_EXT_SMI#<32>
TOUCH_SCREEN_PD#<26>
TOUCHPAD_INTR#<39>

TOUCH_SCREEN_DET#<26>

12

RC88

1 2
1 2
1 2
1 2

1 2

RC95 33_0402_5%

SPKR<30>

HDA_SDOUT

1 2

XDP_OBS0_R<14>
XDP_OBS1_R<14>

@

T10

@

T11

12

RC89

49.9_0402_1%

HDA_SDIN0<30>

4

H_PROCHOT#_R
H_THERMTRIP#

PAD~D
PAD~D

TOUCHPAD_INTR#

CPU_POPIRCOMP
PCH_POPIRCOMP

EDRAM_OPIO_RCOMP

12

RC90

49.9_0402_1%

49.9_0402_1%

HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT

HDA_RST#

H_CATERR#

XDP_OBS2_R
XDP_OBS3_R

EOPIO_RCOMP

12

RC91

49.9_0402_1%

BA22
AY22
BB22
BA21
AY21

AW22

AY20

AW20

AK10

D63
A54
C65
C63
A65

C55
D55
B54
C56

A6

A7
BA5
AY5

AT16

AU16

H66
H65

UC1G

HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_ MCLK
I2S1_SFRM
I2S1_TXD

AK7

GPP_F1/I2S2_ SFRM

AK6

GPP_F0/I2S2_ SCLK

AK9

GPP_F2/I2S2_ TXD
GPP_F3/I2S2_ RXD

H5

GPP_D19/DM IC_CLK0

D7

GPP_D20/DM IC_DATA0

D8

GPP_D17/DM IC_CLK1

C8

GPP_D18/DM IC_DATA1

AW5

GPP_B14/SPK R

SKL-U_BGA1356

UC1D

CPU@

CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]

GPP_E3/CPU _GP0
GPP_E7/CPU _GP1
GPP_B3/CPU _GP2
GPP_B4/CPU _GP3

PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOM P
OPC_RCOMP

SKL-U_BGA1356

CPU@

AUDIO

CPU MISC

SKL-U

SKL-U

3

JTAG

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST#

JTAGX

4 OF 20

SDIO/SDXC

GPP_A17/SD _PWR_EN#/ISH _GP7

CPU_XDP_TCLK

B61

CPU_XDP_TDI

D60

CPU_XDP_TDO

A61

CPU_XDP_TMS

C60

CPU_XDP_TRST#

B59

PCH_JTAG_TCK

B56

PCH_JTAG_TDI

D59

PCH_JTAG_TDO

A56

PCH_JTAG_TMS

C59

CPU_XDP_TRST#

C61

XDP_JTAGX

A59

RC87 1K_0402_5%@

GPP_G0/SD_C MD
GPP_G1/SD_D ATA0
GPP_G2/SD_D ATA1
GPP_G3/SD_D ATA2
GPP_G4/SD_D ATA3

GPP_G5/SD_C D#
GPP_G6/SD_C LK

GPP_G7/SD_W P

GPP_A16/SD _1P8_SEL

SD_RCOMP

GPP_F23

CPU_XDP_TCLK XDP_JTAGX

RC328 0_0402_5%

@

CPU_XDP_TCLK <14>
CPU_XDP_TDI <14>
CPU_XDP_TDO <14>
CPU_XDP_TMS <14>
CPU_XDP_TRST# <14>

PCH_JTAG_TCK <14>

PCH_JTAG_TDI <14>
PCH_JTAG_TDO <14>
PCH_JTAG_TMS <14>

1 2

AB11
AB13
AB12
W12

CONTACTLESS_DET#

W11
W10
W8
W7

BA9
BB9

SD_RCOMP

AB7

AF13

7 OF 20

12

2/5 for DCI

RC86 51_0402_5%@

+1.0V_VCCSTG

CAM_MIC_CBL_DET# <10,26>

1 2

RC96 200_0402_1%

PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX

0.1U_0402_25V6

@EMC@

12

CC303

2

PCH_JTAG_TDI

51_0402_5%

PCH_JTAG_TDO

100_0402_1%

PCH_JTAG_TMS

51_0402_5%

12

Service Mode Switch:
Add a switch to ME_FWP sign al to unlo ck the ME region and
allow the ent i re r egi on of t he SPI f l ash to be updated using FPT.

+3.3V_ALW_PCH

12

ME_FWP PCH has internal 20K PD.
(suspend power rail)

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = ENAB LE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short

CONTACTLESS_DET# <33>

0.1U_0402_25V6

@EMC@

12

CC304

ESD request,Place near CPU side.

12

RC81

12

RC82

12

RC130

RC221 0_0402_5%

@

PT,ST pop RC222 and SW1; MP pop RC221

RC222

@

1K_0402_5%

ME_FWP_EC<31>

0.1U_0402_25V6

@EMC@

12

CC305

+1.0V_VCCSTG

ME_FWPME_FWP_EC

12

SW1

@

1

A

2

ME_FWP

12

B

3

C

4

G1

5

G2

SS3-CMFTQR9_3P

H_THERMTRIP# H_PROCHOT#

0.1U_0402_25V6

@EMC@

12

CC312

1

0.1U_0402_25V6

@EMC@

CC310

TOP SWAP STRAP

A A

HIGH
LOW(DEFAULT)

ENABLE
DISABLE

Flash Descriptor Security override

HIGH
LOW(DEFAULT)

DISABLE

ENABLE

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (7/14)

CPU (7/14)

CPU (7/14)

LA-C461P

LA-C461P

LA-C461P

12 61Tuesday, October 13, 2015

12 61Tuesday, October 13, 2015

12 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

D D

4

CFG[0..19]<14>

3

2

1

CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin

1 2

RC113 10K_0402_1%@

Stall reset sequence

HIGH(DEFAULT)
LOW

C C

1 2

RC109 1K_0402_5%

eDP enable

HIGH(DEFAULT)
LOW

B B

CFG0

No stall(Normal Operat i on)
stall

CFG4

Disabled
Enabled

+1.0V_PRIM_XDP

1 2

RC112 10K_0402_1%@

1 2

RC110 10K_0402_1%@

RC114 49.9_0402_1%

RC115 1.5K_0402_5%

ITP_PMODE<14>

@

T16

PAD~D

@

T17

PAD~D

CFG_RCOMP

12

ITP_PMODE

12

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG16
CFG17

CFG18
CFG19

AL25
AL27

BA70
BA68

E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70

E63
F63

E66
F66

E60

E8

AY2
AY1

D1
D3

K46
K45

C71
B70

F60

A52

J71
J68

F65

G65

F61
E61

UC1S

CPU@

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[16]
CFG[17]

CFG[18]
CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2
RSVD_AY1

RSVD_D1
RSVD_D3

RSVD_K46
RSVD_K45

RSVD_AL25
RSVD_AL27

RSVD_C71
RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70
RSVD_TP_BA68

RSVD_J71
RSVD_J68

VSS_F65
VSS_G65

RSVD_F61
RSVD_E61

SKL-U_BGA1356

RESERVED SIGNALS -1

SKL-U

RSVD_TP_BB68
RSVD_TP_BB69

RSVD_TP_AK13
RSVD_TP_AK12

RSVD_BB2
RSVD_BA3

RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2

RSVD_B3
RSVD_A3

RSVD_AW1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4
RSVD_C4

RSVD_A69
RSVD_B69

RSVD_AY3

RSVD_D71
RSVD_C70

RSVD_C54
RSVD_D54

VSS_AY71

ZVM#

RSVD_TP_AW71
RSVD_TP_AW70

MSM#

PROC_SELECT#

19 OF 20

SPARE

SKL-U

RSVD_F6

RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52

20 OF 20

F6
E3
C11
B11
A11
D12
C12
F52

UC1T

BB68
BB69

AK13
AK12

BB2
BA3

AU5

TP5

AT5

TP6

D5
D4
B2
C2

B3
A3

AW1

E1
E2

BA4
BB4

A4
C4

BB5

TP4

A69
B69

AY3

D71
C70

C54
D54

AY4

TP1

BB3

TP2

AY71
AR56

AW71
AW70

AP56
C64

@

@

T12

PAD~D

@

T13

PAD~D

@

T14

PAD~D

@

T15

PAD~D

@

T128

PAD~D

@

T129

PAD~D

@

T130

PAD~D

@

T126

PAD~D

@

T127

PAD~D

LPM_ZVM_N <53>

@

T113

PAD~D

@

T114

PAD~D

MSM_N <53>

1 2

RC120 100K_0402_5%

For Skylake , RC120 depop
For Cannonlake, RC120 pop

546765_546765_2014WW48_Skylake_M OW_Rev_1_ 0

1/5 2014W W52 M OW reserve to support
Cannonlake-U PCH compatibility

close UC1.U11/U12 and <400mil

1 2

RC313 0_0402_5%

@

+VCC_1P8+1.8V_PRIM

ZVM# for SKYLA KE-U 2+3e

MSM# for SKYLAKE-U 2+3e

+1.0V_VCCST

AW69

RSVD_AW69

AW68

RSVD_AW68

AU56

RSVD_AU56

AW48

RSVD_AW48

C7

RSVD_C7

U12

RSVD_U12

U11

RSVD_U11

H11

1

2

@

RSVD_H11

SKL-U_BGA1356

CC222

1U_0402_6.3V6K

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (8/14)

CPU (8/14)

CPU (8/14)

LA-C461P

LA-C461P

LA-C461P

13 61Tuesday, October 13, 2015

13 61Tuesday, October 13, 2015

13 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

CC29

5

+1.0V_PRIM_XDP

XDP_OBS0_R<12>
XDP_OBS1_R<12>

RC123 1K_0402_5%@

RC124

CXDP@ 1K_0402_5%

PCH_SPI_DO_XDP<8>

RESET_OUT#<11,32>

RC239 0_0402_5%

CXDP@

RC240 0_0402_5%

CXDP@

RC5 n eed to close to JCPU1

1 2

1 2

FIVR_EN
CFG0

CXDP@

1 2

RC217 0_0402_5%

@

1 2

RC126 1K_0402_5%

@

1 2

RC128 0_0402_5%

1 2

RC129 0_0402_5%

@

DDR_XDP_WAN_SMBDAT<8,20,21>

DDR_XDP_WAN_SMBCLK<8,20,21>

CPU_XDP_PREQ#<10>

CPU_XDP_PRDY#<10>

1 2
1 2

PCH_JTAG_TCK<12>

CPU_XDP_TCLK<12>

CPU XDP

H_VCCST_PWRGD_XDP

SIO_PWRBTN#<11,32>

CPU_XDP_PREQ#
CPU_XDP_PRDY#

RESET_OUT#_R

CPU_XDP_TCLK

+1.0V_PRIM

1 2

RC216 0_0603_1%

@

+1.0V_PRIM_XDP

0.1U_0201_10V6K

0.1U_0201_10V6K

@

@

CC28

1

1

2

2

D D

Place near
JXDP1

H_VCCST_PWRGD<11,32>

PCH_RSMRST#_Q<11,39>

+1.0V_PRIM_XDP

CFG0
CFG1

CFG2
CFG3

XDP_OBS0
XDP_OBS1

CFG4
CFG5

CFG6
CFG7

FIVR_EN_R

4

XDP_PRSNT_PIN1

1 2

RC121 1K_0402_5%

1 2

RC122 0_0402_5%@

JXDP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A 0

11

OBSDATA_A 1

13

GND4

15

OBSDATA_A 2

17

OBSDATA_A 3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B 0

29

OBSDATA_B 1

31

GND10

33

OBSDATA_B 2

35

OBSDATA_B 3

37

GND12
PWRGOOD/HOOK039ITPCLK/HOOK4

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

CXDP@

CFG3

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C 0
OBSDATA_C 1

GND5

OBSDATA_C 2
OBSDATA_C 3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D 0
OBSDATA_D 1

GND11
OBSDATA_D 2
OBSDATA_D 3

GND13

ITPCLK#/HOOK 5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

TMS

GND17

CONN@SAMTE_BSH-030-01-L-D-A

TD0

TDI

+1.0V_PRIM_XDP

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

CFG17
CFG16

CFG8
CFG9

CFG10
CFG11

CFG19
CFG18

CFG12
CFG13

CFG14
CFG15

ITP_PMODE
XDP_DBRESET#

TDO_XDP
TRST#_XDP
TDI_XDP
XDP_TMS

3

CFG[0..19]<13>

CLK_ITPXDP_P_R <11>
CLK_ITPXDP_N_R <11>

ITP_PMODE <13 >

XDP_DBRESET# <11>

PCH_SPI_DO2_XDP <8>

2

+3.3V_RUN

CC30

1 2

0.1U_0201_10V6K

TDO_XDP

TDI_XDP

XDP_TMS

TRST#_XDP

RUNPWROK<31,32>

UC8

14

VCC

2

1A

1

1OE

5

2A

4

2OE

9

3A

10

3OE

12

4A

13

4OE

74CBTLV3126BQ_DHVQFN14_2P5X3

GND

GND PAD

1

3

1B

6

2B

8

3B

11

4B

7

15

CPU_XDP_TDO <12>

CPU_XDP_TDI <12>

CPU_XDP_TMS <12>

CPU_XDP_TRST# <12>

+1.0VS_VCCIO

C C

B B

+1.0V_VCCST

+3.3V_RUN

+1.0V_PRIM_XDP

1 2

RC132 150_0402_5%

1 2

RC218 150_0402_5%

@

1 2

RC219 10K_0402_5%

@

1 2

RC137

1 2

RC138

@

FIVR_EN_R

FIVR_EN

FIVR_EN

XDP_DBRESET#

1K_0402_5%

CPU_XDP_PREQ#

51_0402_5%

11/0 6: CR B is NC

CKLT0.9

+3.3V_ALW_PCH

0.1U_0402_25V6

CC33@

Place near JXDP1.47

12

RC133

1.5K_0402_5%

CXDP@

PCH_SPI_DO_XDP

RESET_OUT#_R

12

9/1 follow SPI PWR rail

Place near JXDP1.48

XDP_DBRESET#

CPU_XDP_TMS

51_0402_5%

+3.3V_ALW_DSW

0.1U_0402_25V6

CC32

CXDP@

12

SIO_PWRBTN#

12

12

1.5K_0402_5%
RC241

@

0.1U_0402_25V6

CC269

@

EDS0.7

Place near JXDP1.41

TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#

0.1U_0402_25V6

@EMC@

12

CC306

ESD request,Place near JXDP1 side. ESD request,Place near UC8 side.

12

CPU_XDP_TDI

CPU_XDP_TDO

CPU_XDP_TRST#

CPU_XDP_TCLK

XDP_TMS

TDI_XDP

TDO_XDP

9/1 correct typo netname

0.1U_0402_25V6

@EMC@

CC307

51_0402_5%

100_0402_1%

51_0402_5%

51_0402_5%

1 2

RC228 0_0402_5%

@

1 2

RC229 0_0402_5%

@

1 2

RC230 0_0402_5%

@

0.1U_0402_25V6

@EMC@

12

CC308

12

RC131

12

RC134

12

RC135

12

RC136@

12

RC139

+1.0V_VCCSTG

PCH_JTAG_TMS <12>

PCH_JTAG_TDI <12>

PCH_JTAG_TDO <12>

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (9/14)

CPU (9/14)

CPU (9/14)

LA-C461P

LA-C461P

LA-C461P

14 61Tuesday, October 13, 2015

14 61Tuesday, October 13, 2015

14 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

4

3

2

1

+VCC_CORE: 0.3~1.35V

D D

@

T122

PAD~D

@

T123

+VCC_EDRAM

+1.8V_PRIM

+VCC_EOPIO

C C

VCCOPC,VCC OPC_1P8,VCCEOP IO f or SKYLAKE-U 2+3 e

(w/ on package cache)

PAD~D

1 2

RC232 0_0603_5%@

VCC_EDRAM_SENSE<53>
VSS_EDRAM_SENSE<53>

VCCEOPIO_SENSE<53>
VSSEOPIO_SENSE<53>

+VCC_EDRAM +VCC_EOPIO

+VCC_CORE +VCC_CORE

+VCC_CORE_G0

+VCC_CORE_G1

+1.8V_PRIM_R

1

1

CC180

2

CC183

2

GT3@

GT3@

10U_0402_6.3V6M

1U_0402_6.3V6K

A30

VCC_A30

A34

VCC_A34

A39

VCC_A39

A44

VCC_A44

AK33

VCC_AK33

AK35

VCC_AK35

AK37

VCC_AK37

AK38

VCC_AK38

AK40

VCC_AK40

AL33

VCC_AL33

AL37

VCC_AL37

AL40

VCC_AL40

AM32

VCC_AM32

AM33

VCC_AM33

AM35

VCC_AM35

AM37

VCC_AM37

AM38

VCC_AM38

G30

VCC_G30

K32

RSVD_K32

AK32

RSVD_AK32

AB62

VCCOPC_AB62

P62

VCCOPC_P62

V62

VCCOPC_V62

H63

VCC_OPC_1P8_H63

G61

VCC_OPC_1P8_G61

AC63

VCCOPC_SENSE

AE63

VSSOPC_SENSE

AE62

VCCEOPIO

AG62

VCCEOPIO

AL63

VCCEOPIO_SENSE

AJ62

VSSEOPIO_SENSE

SKL-U_BGA1356

1

CC289

2

GT3@

1U_0402_6.3V6K

UC1L

CPU@

1

CC290

2

GT3@

CPU POW ER 1 OF 4

1

CC291

2

GT3@

1U_0402_6.3V6K

SKL-U

VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42

VCC_J30
VCC_J33
VCC_J37

VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43

VCC_SENSE

VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

12 OF 20

1

1

CC292

CC293

2

2

GT3@

1U_0402_6.3V6K

GT3@

1U_0402_6.3V6K

1U_0402_6.3V6K

G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43

E32

VCCSENSE

E33

VSSSENSE

H_CPU_SVIDALRT#

B63
A63

VIDSCLK

D64

VIDSOUT

G20

+1.0V_VCCSTG_R

1

2

CC184

GT3@

10U_0402_6.3V6M

+VCC_CORE

VIDSCLK <48>

1 2

RC143 0_0603_5%@

1

CC187

2

GT3@

10U_0402_6.3V6M

12

12

RC140

100_0402_1%

RC141

100_0402_1%

VCCSENSE <48>
VSSSENSE <48>

+1.0V_VCCSTG

PSC(Primary side cap) : Place as close to the package as possible
BSC(Backside cap) : Place on seco ndary side, underneath the package

Component placement order:
Package edge > 040 2 caps > 0805 ca ps > Bul k caps >Power source

ESD Request

+VCC_CORE +1.2V_MEM

+1.0V_PRIM +VCC_CORE

CC282

CC283

CC284

CC285

CC286

CC287

1 2

1 2

1 2

1 2

1 2

1 2

22U_0603_6.3V6M@EMC@

22U_0603_6.3V6M@EMC@

22U_0603_6.3V6M@EMC@

+3.3V_RUN+1.0V_PRIM

22U_0603_6.3V6M@EMC@

+1.2V_MEM+1.0V_PRIM

22U_0603_6.3V6M@EMC@

+3.3V_RUN+VCC_CORE

22U_0603_6.3V6M@EMC@

INTEL PDG 1.0

B B

8/21 CR B1.0 , DG0.9

SVID ALERT

VIDALERT_N<48>

SVID DATA

A A

VIDSOUT<48>

+1.0V_VCCST

12

+1.0V_VCCST

12

56_0402_1%

RC152

100_0402_1%

RC157

CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 - 1500mils

H_CPU_SVIDALRT#

12

RC153220_0402_5%

CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 - 1500mils

VIDSOUT

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (10/14)

CPU (10/14)

CPU (10/14)

LA-C461P

LA-C461P

LA-C461P

15 61Tuesday, October 13, 2015

15 61Tuesday, October 13, 2015

15 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

4

3

2

1

+VCCGT: 0.3~1.35V
+VCCGTX : 0.3~1.35V

+VCC_GT +VCC_GT

D D

C C

+VCC_GT

12

RC161

100_0402_1%

VCC_GT_SENSE<48>

VSS_GT_SENSE<48>

B B

VCC_GT_SENSE
VSS_GT_SENSE

12

RC163

100_0402_1%

AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71

A48
A53
A58
A62
A66

K48
K50
K52
K53
K55
K56
K58
K60

M62
N63
N64
N66
N67
N69

J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60

L62
L63
L64
L65
L66
L67
L68
L69
L70
L71

J70
J69

UC1M

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGT_SENSE
VSSGT_SENSE

SKL-U_BGA1356

CPU@

CPU POW ER 2 OF 4

SKL-U

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56

VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58

VCCGTX_AU58

VCCGTX_AU63

VCCGTX_BB57

VCCGTX_BB66

VCCGTX_SENSE

VSSGTX_SENSE

13 OF 20

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50

VCCGTX for SKYLAKE-U 2+3e

AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66

AK62
AL61

+VCC_GT

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (11/14)

CPU (11/14)

CPU (11/14)

LA-C461P

LA-C461P

LA-C461P

16 61Tuesday, October 13, 2015

16 61Tuesday, October 13, 2015

16 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

4

3

2

1

+5V_ALW

CZ115

@

1 2

4

O

CC182

@

CC253

+1.2V_MEM

1 2

@

RZ119 0_0402_5%

UZ26

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

UC14

INTEL PDG 1.0

1

1

2

2

CC185

CC186

@

@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

2

2

CC250

1U_0402_6.3V6K

SIO_SLP_S0#

CC251

SIO_SLP_S3#

1U_0402_6.3V6K

AND

+VCCPLL_OC source

8/14 CRB1.0

1 2

RC231 0_0402_5%

@

D D

BSC

1

2

BSC

1

2

CC256

@

1U_0402_6.3V6K

C C

B B

PSC

1

CC174

2

@

@

10U_0402_6.3V6M

1

1

2

2

CC257

@

1U_0402_6.3V6K

1

1

2

1

2

1U_0402_6.3V6K

CC176

2

10U_0402_6.3V6M

1

2

CC255

@

1U_0402_6.3V6K

+1.0V_VCCST

CC177

22U_0603_6.3V6M

1

2

CC175

10U_0402_6.3V6M

CC254

@

+1.2V_MEM+1.2V_MEM_CPUCLK

VDDQ: 8.45A

DG0.9

1

1

CC179

CC178

2

2

10U_0402_6.3V6M

22U_0603_6.3V6M

1

2

1U_0402_6.3V6K

10U_0402_6.3V6M

22U_0603_6.3V6M

CC296

CC295

1

2

PSC

+1.0V_VCCSTG

BSC

1

CC199

2

@

1

CC297

2

1U_0402_6.3V6K

10U_0402_6.3V6M

+VCC_SFR_OC

+1.2V_MEM_CPUCLK

BSC

1

CC194

2

@

1

2

10U_0402_6.3V6M

CC294

PSC

PSC

DG1.0

CC195

+1.0V_VCCST source

+1.2V_MEM

1U_0402_6.3V6K

CC288

1U_0402_6.3V6K

1.35V in DDR3L,

1.2V in LPDDR3 and DDR4

UC1N

CPU@

CPU POW ER 3 OF 4

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

BB47

VDDQ_BB47

BB51

VDDQ_BB51

AM40

VDDQC

A18

VCCST

A22

VCCSTG_A22

AL23

VCCPLL_OC

K20

VCCPLL_K20

K21

VCCPLL_K21

SKL-U_BGA1356

+1.0V_VCCST

PSC

1

2

CC202

1U_0402_6.3V6K

SKL-U

+VCC_SA

DG0.9

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

14 OF 20

1 2

RC168 100_0402_1%

AK28
AK30
AL30
AL42
AM28
AM30
AM42

AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30

AM23
AM22

H21
H20

+1.0VS_VCCIO

VCCIO_SENSE
VSSIO_SENSE

+VCC_SA

+1.0VS_VCCIO

12

12

12

RC166

100_0402_1%

VSA_SEN- <48>
VSA_SEN+ <48>

8/14 PWR request

RC165

100_0402_1%

VCCIO_SENSE <46>
VSSIO_SENSE <46>

RC167

100_0402_1%

12

CZ113 1U_0402_6.3V6K

SIO_SLP_S3#<11,17,32,47>

SIO_SLP_SUS#<8,11,18,32,41,45,46,47,53>

SIO_SLP_S4#<11,17,32,44,54>

1 2

RZ120 0_0402_5%

@

+3.3V_ALW

1

2

+1.0VS_VCCIO

1

2

@

5

0.1U_0402_10V7K

P

B

A

G

3

TC7SH08FU_SSOP5~D

1

2

CC181

1U_0402_6.3V6K

PSC

1

1

2

2

CC252

1U_0402_6.3V6K

+1.0V_VCCSTG source

+VCC_SFR_OC

6

VOUT

5

GND

BSCBSC

1

2

@

S0

HIGH

HIGH

HIGH LOW LOW

S0Ix

LOW

HIGH

S3

LOW

LOW

@

CZ114 0.1U_0201_10V6K

1

CC248

CC249

2

@

10U_0402_6.3V6M

10U_0402_6.3V6M

1 2

+1.0V_VCCST+1.0V_VCCSTG

1 2

RC238 0_0603_5%@

+1.0V_PRIM

12

CZ95 1U_0402_6.3V6K

SIO_SLP_S4#<11,17,32,44,54>

A A

5

+1.0V_PRIM

+5V_ALW

UZ21

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm/6 A
TR=12.5us@Vin=1.05 V

VOUT

GND

6

5

4

+1.0V_VCCST_C

PJP27

12

PAD-OPEN1x1m

1 2

@

CZ78 0.1U_0201_10V6K

+1.0V_VCCST

SIO_SLP_S0#<11,33,46>

SIO_SLP_S3#<11,17,32,47>

TC7SH08FU_SSOP5~D

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

3

12

CZ87 1U_0402_6.3V6K

@

+5V_ALW

+3.3V_ALW

5

1

P

B

O

2

A

G

UC13

3

1 2

RC320 0_0402_5%

4

UZ19

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm/6 A
TR=12.5us@Vin=1.05 V

2

VOUT

GND

12

PJP32
PAD-OPEN1x1m

+1.0V_VCCSTG_C

6

5

DELL CONFIDENTIAL/PROPRIETARY

pop option with UZ19

1 2

@

CZ82 0.1U_0201_10V6K

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (12/14)

CPU (12/14)

CPU (12/14)

LA-C461P

LA-C461P

LA-C461P

17 61Tuesday, October 13, 2015

17 61Tuesday, October 13, 2015

17 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

+1.0V_PRIM

1 2

RC194 0_0805_5%

@

Imax : 2.57A

1 2

D D

C C

B B

RC299 0_0603_5%@

1 2

@

RC300 0_0402_5%

1 2

RC301 0_0402_5%

@

1 2

RC302 0_0402_5%

@

1 2

RC303 0_0402_5%

@

+1.8V_PRIM

+3.3V_ALW_PCH

+1.8V_PRIM

1 2

RC304 0_0402_5%

@

1 2

@

RC234 0_0402_5%

1 2

RC235 0_0402_5%

@

1 2

RC211 0_0402_5%

@

1 2

@

RC212 0_0402_5%

1 2

RC305 0_0402_5%

@

1 2

RC306 0_0402_5%

@

1 2

RC307 0_0402_5%

@

1 2

RC308 0_0402_5%

@

+3.3V_ALW_PCH +3.3V_VCCHDA

1 2

LC1 BLM15HG601SN1D_2P

1

CC215

2

@

1U_0402_6.3V6K

+1.0V_PRIM_CORE

+1.0V_MPHYAON

8/28 schematic review

+1.0V_CLK6

+1.0V_DTS

+1.0V_CLK1

+1.0V_CLK3

+1.8V_PGPPF

+3.3V_1.8V_PGPPG

close UC1.AF20 and <40 0mil

+3.3V_1.8V_PGPPA

+3.3V_PGPPB+3.3V_ALW_PCH

+3.3V_PGPPC

+3.3V_PGPPD

+3.3V_PGPPE

8/28 schematic review Pop PJP35 & Depop UZ20/RZ83/CZ84

close UC1.V15 and <100mil

1

CC313

2

0.1U_0402_25V6

8/26 vender suggest depop

LC2 BLM15HG601SN1D_2P

+1.0V_MPHYAON

1

2

CC203

1U_0402_6.3V6K

+1.0V_MPHYGT

close UC1.N15 and CC210 <400m il, CC 211 <120mil

1

2

+1.0V_SRAM

close UC1.K15, UC1.L15 and <100mil

1 2

RC169 0_0603_5%@

1

2

CC281

@

0.1U_0201_10V6K

1 2

CC210

@

1

2

close UC1.AJ19 an d <400mil

+3.3V_ALW +3.3V_ALW_DSW

A A

1 2

RC214 0_0402_5%

@

22U_0603_6.3V6M

@

CC279

1

2

5

22U_0603_6.3V6M

@

CC280

1

2

8/26 vender suggest depop

+3.3V_ALW +1.8V_PRIM +1.0V_PRIM

1

CC271

2

47U_0805_6.3V6M

4

close UC1.AL1 and <12 0mil

1

2

CC204

1U_0402_6.3V6K

close UC1.AF18 and <40 0mil

1

2

CC211

1U_0402_6.3V6K

47U_0805_6.3V6M

CC217

+1.0V_APLLEBB

@

1U_0402_6.3V6K

1

2

CC218

+1.0V_AMPHYPLL+1.0V_MPHYGT

1

CC219

2

@

47U_0805_6.3V6M

+1.0V_APLL+1.0V_PRIM

1

2

1

CC225

@

1

2

CC314

2

47U_0805_6.3V6M

1

CC273

2

4

0.1U_0402_25V6

+1.0V_PRIM_CORE

47U_0805_6.3V6M

47U_0805_6.3V6M

CC272

+1.0V_PRIM_CORE+1.0VO_DSW

1

2

+1.0V_PRIM

close UC1.AB19 and <4 00milclose UC1.K17 an d <120mil

CC205

@

1U_0402_6.3V6K

+1.0V_AMPHYPLL

+1.0V_APLL

+1.0V_PRIM

+3.3V_ALW_DSW

+3.3V_VCCHDA

+3.3V_SPI

+3.3V_ALW_PCH

1

2

close UC1.N18 and <120mil

1U_0402_6.3V6K

close UC1.K15 an d <120mil

1

2

CC264

@

1U_0402_6.3V6K

close UC1.N20 and <100mil

1

2

8/26 vender suggestion

CC274

47U_0805_6.3V6M

+1.0V_PRIM

CC206

@

AB19

1U_0402_6.3V6K

AB20

P18

AF18
AF19

V20
V21

AL1

K17

L1

N15
N16
N17
P15
P16

K15
L15

V15

AB17

Y18

AD17
AD18

AJ17

AJ19

AJ16

AF20
AF21

T19
T20

AJ21

AK20

N18

1 2

RC170 0_0402_5%

@

close UC1.K19 an d <100mil

RC173 0_0402_5%

@

3

PCH PWR

close UC1.AG15 and <120mil

UC1O

CPU@

CPU POW ER 4 OF 4

VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0

VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE

DCPDSW_1P0

VCCMPHYAON_1P0
VCCMPHYAON_1P0

VCCMPHYGT_1P0_N15
VCCMPHYGT_1P0_N16
VCCMPHYGT_1P0_N17
VCCMPHYGT_1P0_P15
VCCMPHYGT_1P0_P16

VCCAMPHYPLL_1P0
VCCAMPHYPLL_1P0

VCCAPLL_1P0

VCCPRIM_1P0_AB17
VCCPRIM_1P0_Y18

VCCDSW_3P3_AD17
VCCDSW_3P3_AD18
VCCDSW_3P3_AJ17

VCCHDA

VCCSPI

VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0

VCCPRIM_3P3_AJ21

VCCPRIM_1P0_AK20

VCCAPLLEBB

SKL-U_BGA1356

1 2

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

SKL-U

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19
VCCRTC_BB14

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/CORE _VID0
GPP_B1/CORE _VID1

AK15
AG15
Y16
Y15
T16
AF16
AD15

V19

T1

AA1

AK17

AK19
BB14

BB10

A14

K19

L21

N20

L19

A10

AN11
AN13

+3.3V_1.8V_PGPPA

+3.3V_PGPPD

+1.8V_PGPPF
+3.3V_1.8V_PGPPG

+1.0V_DTS

+3.3V_ALW_PCH

close UC1.AK19 and <120mil

+DCPRTC

close UC1.BB10 and <120mil

+1.0V_CLK1

+1.0V_CLK2

+1.0V_CLK3

+1.0V_CLK4

+1.0V_CLK5

CORE_VID0 <46>
CORE_VID1 <46>

Tak e c ar e! !! N ot e1 on P ag e 1 9

15 OF 20

+1.0V_CLK2+1.0V_PRIM

1 2

RC171 0_0402_5%

@

1

CC220

2

@

47U_0805_6.3V6M

+1.0V_CLK4+1.0V_PRIM

1

CC226

2

@

47U_0805_6.3V6M

3

close UC1.L19 an d <100mil

SIO_SLP_SUS#<8,11,17,32,41,45,46,47,53>

MPHYP_PWR_EN<11,45>

2

close UC1.Y16 and <4 00mil

+3.3V_PGPPB

1

CC265

2

@

close UC1.AA1 and <400mil

1

2

+1.0V_CLK6

1

CC221

2

@

47U_0805_6.3V6M

+3.3V_PGPPC

1U_0402_6.3V6K

CC214

0.1U_0201_10V6K

1

2

+3.3V_PGPPE

close UC1.T16 and <4 00mil

1

2

+RTC_CELL

1

2

DG0.9

1

CC207

2

@

1U_0402_6.3V6K

1

2

CC270

CC213

1U_0402_6.3V6K

0.1U_0201_10V6K

close UC1.A10 and <1 20mil

CC216

@

1U_0402_6.3V6K

DG0.9

CC208

@

1U_0402_6.3V6K

+3.3V_ALW_PCH+1.0V_CLK5+1.0V_PRIM

+1.0V_MPHYGT source

11/0 c ha nge p ower s ou rce

CZ84 1U_0402_6.3V6K@

RZ82 0_0402_5%

@

RZ83 0_0402_5%

@

+1.0V_PRIM

12

+5V_ALW

12

12

UZ20 @

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm/6 A
TR=12.5us@Vin=1.05 V

DELL CONFIDENTIAL/PROPRIETARY

2

1

+1.0V_MPHYGT

+1.0V_SRAM

+1.0V_APLLEBB

+1.8V_PRIM

1

2

+3.3V_ALW_PCH

1

2

CC212

1U_0402_6.3V6K

1 2

RC309 0_0603_5%@

1 2

RC310 0_0603_5%@

8/28 schematic review

close UC1.V19 and <120mil

CC209

@

1U_0402_6.3V6K

close UC1.AK17 and <120mil

1

1

CC223

2

2

CC224

1U_0402_6.3V6K

0.1U_0201_10V6K

+1.0V_MPHYGT+1.0V_PRIM

PJP35

1 2

PAD-OPEN1x3m

+1.0V_MPHYGT

6

VOUT

5

GND

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

1

2

@

CPU (13/14)

CPU (13/14)

CPU (13/14)

LA-C461P

LA-C461P

LA-C461P

1

CZ85

0.1U_0201_10V6K

18 61Tuesday, October 13, 2015

18 61Tuesday, October 13, 2015

18 61Tuesday, October 13, 2015

1.0

1.0

1.0

5

4

3

2

1

Note1: VCCPRIM_CORE Implementat i on wit h PC H C ORE_VI D R e c o m me n d a t i on

CPU@

SKL-U

UC1P

GND 1 OF 3

A5

VSS

A67

VSS

A70

VSS

AA2

VSS

AA4

D D

C C

B B

AA65
AA68
AB15
AB16
AB18
AB21

AD13
AD16
AD19
AD20
AD21
AD62

AE64
AE65
AE66
AE67
AE68
AE69

AF10
AF15
AF17

AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13

AH63
AH64
AH67

AJ15
AJ18
AJ20

AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69

AL28
AL32
AL35
AL38

AL45
AL48
AL52
AL55
AL58
AL64

AB8

AD8

AF1

AF2
AF4

AH6

AJ4

AK8
AL2

AL4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL-U_BGA1356

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

16 OF 20

AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58

AT63
AT68

AT71
AU10
AU15
AU20
AU32
AU38

AV68
AV69
AV70
AV71

AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57

AW6

AW60
AW62
AW64
AW66

AW8

AY66

BA10
BA14
BA18

BA23
BA28
BA32
BA36

BA45

AV1

B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1

BA2

F68

CPU@

UC1Q

GND 2 OF 3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL-U_BGA1356

SKL-U

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

17 OF 20

BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41

F8

VSS

G10

VSS

G22

VSS

G43

VSS

G45

VSS

G48

VSS

G5

VSS

G52

VSS

G55

VSS

G58

VSS

G6

VSS

G60

VSS

G63

VSS

G66

VSS

H15

VSS

H18

VSS

H71

VSS

J11

VSS

J13

VSS

J25

VSS

J28

VSS

J32

VSS

J35

VSS

J38

VSS

J42

VSS

J8

VSS

K16

VSS

K18

VSS

K22

VSS

K61

VSS

K63

VSS

K64

VSS

K65

VSS

K66

VSS

K67

VSS

K68

VSS

K70

VSS

K71

VSS

L11

VSS

L16

VSS

L17

VSS

SKL-U_BGA1356

CPU@

UC1R

GND 3 OF 3

SKL-U

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

18 OF 20

L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21

R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (14/14)

CPU (14/14)

CPU (14/14)

LA-C461P

LA-C461P

LA-C461P

19 61Tuesday, October 13, 2015

19 61Tuesday, October 13, 2015

19 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

4

3

2

1

DDR_A_DQS#[0..7]<7>

DDR_A_D[0..63]<7>

DDR_A_DQS[0..7]<7>

DDR_A_MA[0..16]<7>

+1.2V_MEM

12

+1.2V_MEM

12

1U_0402_6.3V6K

CD7

10U_0603_10V6M

CD12

Layout Note:
Place near JDIMM1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

12

CD3

CD2

10U_0603_10V6M

10U_0603_10V6M

10U_0603_10V6M

CD14

CD13

12

12

12

Layout Note:
Place near
JDIMM1.203,204

+0.6V_DDR_VTT

1U_0402_6.3V6K

CD24

1

2

DIMM Select

SA01SA1

0

DIMM1

DIMM2

1

0

DIMM3

1

DIMM4

5

CD8

CD15

12

12

1

2

0

0

1

1U_0402_6.3V6K

CD9

10U_0603_10V6M

CD16

1U_0402_6.3V6K

CD25

SA2

12

12

0

0

0

0

1U_0402_6.3V6K

CD4

10U_0603_10V6M

CD17

1U_0402_6.3V6K

CD26

1

2

1U_0402_6.3V6K

12

10U_0603_10V6M

12

1

2

12

12

12

CD10

CD18

12

1U_0402_6.3V6K

CD27

@

0_0402_5%

@

0_0402_5%

1U_0402_6.3V6K

CD11

10U_0603_10V6M

CD19

12

RD62

RD66

1U_0402_6.3V6K

12

CD78

10U_0603_10V6M

CD86

12

10U_0603_10V6M

12

CD28

12

RD63

@

0_0402_5%

12

RD67

@

0_0402_5%

1U_0402_6.3V6K

12

CD79

10U_0603_10V6M

CD87

12

10U_0603_10V6M

@

CD29

+3.3V_RUN+3.3V_RUN+3.3V_RUN

1U_0402_6.3V6K

12

10U_0603_10V6M

12

12

@

0_0402_5%

DIMM1_SA0
DIMM1_SA1
DIMM1_SA2

12

@

0_0402_5%

12

CD80

CD88

12

+2.5V_MEM

1

2

RD64

RD68

1U_0402_6.3V6K

12

CD81

10U_0603_10V6M

CD89

12

1U_0402_6.3V6K

1

CD70

2

1U_0402_6.3V6K

12

CD82

10U_0603_10V6M

CD90

12

1U_0402_6.3V6K

1

CD71

2

+3.3V_RUN

12

@

1

2

1U_0402_6.3V6K

12

CD83

10U_0603_10V6M

CD91

12

10U_0603_10V6M

1

CD72

2

RD65

0_0603_5%

2.2U_0402_6.3V6M

CD31

4

1U_0402_6.3V6K

1U_0402_6.3V6K

12

CD84

CD85

10U_0603_10V6M

10U_0603_10V6M

CD92

CD93

12

10U_0603_10V6M

CD73

+3.3V_RUN_DIMM1

0.1U_0201_10V6K

CD32

1

2

330U_D3_2.5VY_R6M

12

@

CD20

+

DDR_A_CKE0<7>

DDR_A_BG1<7>
DDR_A_BG0<7>

DDR_A_CLK0<7>
DDR_A_CLK#0<7>

DDR_A_PARITY<7>

DDR_A_BA1<7>

DDR_A_CS#0<7>

DDR_A_MA14<7>

DDR_A_ODT0<7>

DDR_A_CS#1<7>

DDR_A_ODT1<7>

T51PAD~D @

+2.5V_MEM

D D

C C

B B

A A

JDIMM1 REV Type H=9.2

JDIMM1

1

DDR_A_D1 DDR_A_D4

DDR_A_D0

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D6

DDR_A_D2

DDR_A_D13

DDR_A_D12

DDR_A_D15

DDR_A_D14

DDR_A_D35

DDR_A_D37

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D38

DDR_A_D34

DDR_A_D44

DDR_A_D45

DDR_A_D42

DDR_A_D46

DDR_A_CKE0

DDR_A_BG1
DDR_A_BG0

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA6

DDR_A_MA3
DDR_A_MA1

DDR_A_CLK0
DDR_A_CLK#0

DDR_A_PARITY

DDR_A_BA1

DDR_A_CS#0
DDR_A_MA14

DDR_A_ODT0
DDR_A_CS#1

DDR_A_ODT1

DDR_A_D30

DDR_A_D26

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D27

DDR_A_D29

DDR_A_D21

DDR_A_D17

DDR_A_D19

DDR_A_D22

DDR_A_D48

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50

DDR_A_D51

DDR_A_D56

DDR_A_D57

DDR_A_D63

+3.3V_RUN_DIMM1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5
DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25
DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3_n/DBI3_n

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45
DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

LOTES_ADDR0107-P005A

CONN@

LINK LOTES_ADDR0107-P005A DONE

DM4_n/DBI4_n

DM6_n/DBI6_n

3

RESET_n

ALERT_n

EVENT_n/NF

CK1_t/NF
CK1_c/NF

RAS_n/A16

CAS_n/A15

C0/CS2_n/NC

+1.2V_MEM+1.2V_MEM

2

VSS2

4

DQ4

6

VSS4

VSS6

VSS7

VSS9

VSS11

DQ12

VSS13

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

DQS3_t

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

CKE1
VDD2

ACT_n

VDD4

VDD6

VDD8

VDD10

VDD12

A10/AP

VDD14

VDD16

VDD18

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

DQ0

DQ6

DQ2

DQ8

A11

A7

A5
A4

A2

A0

BA0

A13

SA2

SDA

SA0
VTT
SA1

DDR_A_D5

8
10
12
14

DDR_A_D3

16
18

DDR_A_D7

20
22

DDR_A_D9

24
26

DDR_A_D8

28
30

DDR_A_DQS#1

32

DDR_A_DQS1

34
36

DDR_A_D10

38
40

DDR_A_D11

42
44

DDR_A_D32

46
48

DDR_A_D36

50
52
54
56

DDR_A_D39

58
60

DDR_A_D33

62
64

DDR_A_D40

66
68

DDR_A_D41

70
72

DDR_A_DQS#5

74

DDR_A_DQS5

76
78

DDR_A_D47

80
82

DDR_A_D43

84
86
88
90
92
94
96
98
100
102
104
106

DDR_DRAMRST#_R

108

DDR_A_CKE1

110
112

DDR_A_ACT#

114

DDR_A_ALERT#

116
118

DDR_A_MA11

120

DDR_A_MA7

122
124

DDR_A_MA5

126

DDR_A_MA4

128
130

DDR_A_MA2

132

JDIMM1_EVENT#

134
136

DDR_A_CLK1

138

DDR_A_CLK#1

140
142

DDR_A_MA0

144

DDR_A_MA10

146
148

DDR_A_BA0

150

DDR_A_MA16

152
154

DDR_A_MA15

156

DDR_A_MA13

158
160
162
164

DIMM1_SA2

166
168

DDR_A_D31

170
172

DDR_A_D25

174
176
178
180

DDR_A_D28

182
184

DDR_A_D24

186
188

DDR_A_D20

190
192

DDR_A_D16

194
196

DDR_A_DQS#2

198

DDR_A_DQS2

200
202

DDR_A_D18

204
206

DDR_A_D23

208
210

DDR_A_D53

212
214

DDR_A_D52

216
218
220
222

DDR_A_D54

224
226

DDR_A_D55

228
230

DDR_A_D61

232
234

DDR_A_D60

236
238

DDR_A_DQS#7

240

DDR_A_DQS7

242
244

DDR_A_D58

246
248

DDR_A_D59DDR_A_D62

250
252
254

DIMM1_SA0

256
258

DIMM1_SA1

260
262

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE U SED BY OR DIS CLOSED TO ANY THIRD
PART Y WI TH OUT DE LL 'S E XP RES S WR IT TE N CO NSE NT.

DDR_A_CKE1 <7>

DDR_A_ACT# <7>
DDR_A_ALERT# <7>

DDR_A_CLK1 <7>
DDR_A_CLK#1 <7>

DDR_A_BA0 <7>

T50 PAD~D@

+DDR_VREF_A_CA

DDR_XDP_WAN_SMBDAT <8,14,21>DDR_XDP_WAN_SMBCLK<8,14,21>

+0.6V_DDR_VTT

+DDR_VREF_A_CA

DDR_VTT_CTRL<7>

1

2

2

CD6

@

0.1U_0402_25V6

+1.2V_MEM

1 2

RD29 0_0402_5%@

+1.2V_MEM

1K_0402_1%

12

RD18

1K_0402_1%

12

RD20

follow I NTEL PDG1.0 page167

JDIMM1_EVENT#

RD61 1K_0402_5%@

1 2

DDR3L SODIMM ODT GENERATION

9/17 delete ODT Genertation, connect directly to CPU
refer 546765_2014W W37_SkylakeU_Y_MOW_Rev_1_0

+1.2V_MEM

UD1

1

NC

2

A

3

GND

74AUP1G07GW_TSSOP5

VCC

Y

5

CD30@0.1U_0201_10V6K

4

DELL CONFIDENTIAL/PROPRIETARY

Titl e

Titl e

Titl e

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

470_0402_1%

12

RD2

DG0.9 470ohm+/-1%

DDR_DRAMRST#

1 2

RD19 2_0402_1%

H_THERMTRIP# < 12,21,32>

1 2

1 2

RD30 100K_0402_5%

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

LA-C461P

LA-C461P

LA-C461P

DDR_DRAMRST# <7>DDR_DRAMRST#_R<21>

+DDR_VREF_CA+DDR_VREF_A_CA

0.022U_0402_16V7K

CD36

12

24.9_0402_1%

12

RD21

0.6V_DDR_VTT_ON <44>

+3.3V_ALW

DDR4

DDR4

DDR4

20 61Tuesday, Oct ober 13, 2015

20 61Tuesday, Oct ober 13, 2015

1

20 61Tuesday, Oct ober 13, 2015

1.0

1.0

1.0

5

4

3

2

1

DDR_B_DQS#[0..7]<7>

DDR_B_D[0..63]<7>

DDR_B_DQS[0..7]<7>

DDR_B_MA[0..16]<7>

12

CD37

CD45

12

0

1

0

1

+0.6V_DDR_VTT

Layout Note:
Place near JDIMM2

1U_0402_6.3V6K

1U_0402_6.3V6K

12

CD39

CD38

10U_0603_10V6M

10U_0603_10V6M

CD47

CD46

12

1U_0402_6.3V6K

CD57

1

2

SA2

0

0

0

0

0

0

1

5

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

CD41

CD40

10U_0603_10V6M

10U_0603_10V6M

CD48

12

12

Layout Note:
Place near
JDIMM2.203,204

1U_0402_6.3V6K

1U_0402_6.3V6K

CD58

1

1

2

2

12

12

12

CD49

12

CD59

1

2

RD69

@

0_0402_5%

RD72

@

0_0402_5%

1U_0402_6.3V6K

12

CD42

10U_0603_10V6M

CD50

12

1U_0402_6.3V6K

CD60

12

1U_0402_6.3V6K

12

CD43

10U_0603_10V6M

CD51

12

10U_0603_10V6M

CD61

12

12

RD70

@

0_0402_5%

12

RD73

@

0_0402_5%

1U_0402_6.3V6K

12

CD44

10U_0603_10V6M

CD52

12

10U_0603_10V6M

@

CD62

+3.3V_RUN+3.3V_RUN+3.3V_RUN

12

12

1U_0402_6.3V6K

12

CD102

10U_0603_10V6M

CD94

12

RD71

@

0_0402_5%

DIMM2_SA0
DIMM2_SA1
DIMM2_SA2

RD74

@

0_0402_5%

1U_0402_6.3V6K

12

CD103

10U_0603_10V6M

CD95

12

+2.5V_MEM

1U_0402_6.3V6K

12

CD104

10U_0603_10V6M

CD96

12

1U_0402_6.3V6K

1

CD74

2

+3.3V_RUN

1U_0402_6.3V6K

12

CD105

10U_0603_10V6M

CD97

12

1U_0402_6.3V6K

1

CD75

2

12

RD60

@

0_0603_5%

2.2U_0402_6.3V6M

12

CD63

1U_0402_6.3V6K

1U_0402_6.3V6K

12

CD106

10U_0603_10V6M

10U_0603_10V6M

CD98

12

10U_0603_10V6M

1

CD76

2

+3.3V_RUN_DIMM2

0.1U_0201_10V6K

CD64

1

2

4

12

CD107

CD99

12

10U_0603_10V6M

1

CD77

2

1U_0402_6.3V6K

12

CD108

10U_0603_10V6M

CD100

12

1U_0402_6.3V6K

CD109

10U_0603_10V6M

12

CD101

+

330U_D3_2.5VY_R6M

@

CD53

DDR_B_CKE0<7>

DDR_B_BG1<7>
DDR_B_BG0<7>

DDR_B_CLK0<7>
DDR_B_CLK#0<7>

DDR_B_PARITY<7>

DDR_B_BA1<7>

DDR_B_CS#0<7>

DDR_B_MA14<7>

DDR_B_ODT0<7>

DDR_B_CS#1<7>

DDR_B_ODT1<7>

T55PAD~D @

+2.5V_MEM

D D

+1.2V_MEM

1U_0402_6.3V6K

12

+1.2V_MEM

10U_0603_10V6M

12

C C

B B

DIMM Select

SA01SA1

DIMM1

DIMM2

DIMM3

*

A A

DIMM4

JDIMM2 REV Type H=5.2

JDIMM2

1

DDR_B_D1

DDR_B_D4

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D7

DDR_B_D6

DDR_B_D13

DDR_B_D12

DDR_B_D14

DDR_B_D15

DDR_B_D33

DDR_B_D36

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D39

DDR_B_D38

DDR_B_D42

DDR_B_D43

DDR_B_D44

DDR_B_D45

DDR_B_CKE0

DDR_B_BG1
DDR_B_BG0

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA6

DDR_B_MA3
DDR_B_MA1

DDR_B_CLK0
DDR_B_CLK#0

DDR_B_PARITY

DDR_B_BA1

DDR_B_CS#0
DDR_B_MA14

DDR_B_ODT0
DDR_B_CS#1

DDR_B_ODT1

DDR_B_D21

DDR_B_D20

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D23

DDR_B_D22

DDR_B_D24

DDR_B_D25

DDR_B_D26

DDR_B_D27

DDR_B_D52

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D55

DDR_B_D54

DDR_B_D56

DDR_B_D57

DDR_B_D58

DDR_B_D59

+3.3V_RUN_DIMM2

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5
DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25
DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3_n/DBI3_n

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45
DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

LOTES_ADDR0107-P005A

CONN@

LINK LOTES_ADDR0107-P005A DONE

3

+1.2V_MEM+1.2V_MEM

2

VSS2

DQ4

VSS4

DQ0

VSS6

VSS7

DQ6

VSS9

DQ2

VSS11

DQ12

VSS13

DQ8

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

DQS3_t

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1
VDD2

ACT_n

ALERT_n

VDD4

A11

A7

VDD6

A5
A4

VDD8

A2

EVENT_n/NF

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A0

A10/AP

VDD14

BA0

RAS_n/A16

VDD16

CAS_n/A15

A13

VDD18

C0/CS2_n/NC

VREFCA

SA2

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

SDA

SA0
VTT
SA1

GND2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE U SED BY OR DIS CLOSED TO ANY THIRD
PART Y WI TH OUT DE LL 'S E XP RES S WR IT TE N CO NSE NT.

DDR_B_D5

4
6

DDR_B_D0

8
10
12
14

DDR_B_D2

16
18

DDR_B_D3

20
22

DDR_B_D9

24
26

DDR_B_D8

28
30

DDR_B_DQS#1

32

DDR_B_DQS1

34
36

DDR_B_D11

38
40

DDR_B_D10

42
44

DDR_B_D37

46
48

DDR_B_D32

50
52
54
56

DDR_B_D34

58
60

DDR_B_D35

62
64

DDR_B_D40

66
68

DDR_B_D41

70
72

DDR_B_DQS#5

74

DDR_B_DQS5

76
78

DDR_B_D46

80
82

DDR_B_D47

84
86
88
90
92
94
96
98
100
102
104
106

DDR_DRAMRST#_R

108

DDR_B_CKE1

110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260
262

DDR_B_ACT#
DDR_B_ALERT#

DDR_B_MA11
DDR_B_MA7

DDR_B_MA5
DDR_B_MA4

DDR_B_MA2
JDIMM2_EVENT#

DDR_B_CLK1
DDR_B_CLK#1

DDR_B_MA0

DDR_B_MA10

DDR_B_BA0
DDR_B_MA16

DDR_B_MA15
DDR_B_MA13

DIMM2_SA2

DDR_B_D16

DDR_B_D17

DDR_B_D18

DDR_B_D19

DDR_B_D28

DDR_B_D29

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D31

DDR_B_D30

DDR_B_D53

DDR_B_D48

DDR_B_D50

DDR_B_D51

DDR_B_D61

DDR_B_D60

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62

DDR_B_D63

DIMM2_SA0

DIMM2_SA1

DDR_B_CKE1 <7>

DDR_B_ACT# <7>
DDR_B_ALERT# <7>

DDR_B_CLK1 <7>
DDR_B_CLK#1 <7>

DDR_B_BA0 <7>

T54 PAD~D@

+DDR_VREF_B_CA

DDR_XDP_WAN_SMBDAT <8,14,20>DDR_XDP_WAN_SMBCLK<8,14,20>

+0.6V_DDR_VTT

+DDR_VREF_B_CA

2

JDIMM2_EVENT#

RD4 1K_0402_5%@

1

CD35

0.1U_0402_25V6

2

+DDR_VREF_B_CA

1 2

@

DDR_DRAMRST#_R <20>

+1.2V_MEM

1K_0402_1%

12

RD22

1K_0402_1%

12

RD24

H_THERMTRIP# < 12,20,32>

1 2

RD75 2_0402_1%

follow I NTEL PDG1.0 page167

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Titl e

Titl e

Titl e

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDR4

DDR4

DDR4

LA-C461P

LA-C461P

LA-C461P

1

12

24.9_0402_1%

12

RD25

+DDR_VREF_B_DQ

0.022U_0402_16V7K

CD54

21 61Tuesday, Oct ober 13, 2015

21 61Tuesday, Oct ober 13, 2015

21 61Tuesday, Oct ober 13, 2015

1.0

1.0

1.0

5

CPU_DP1_P0<6>

CPU_DP1_N0<6>

D D

CPU_DP1_P1<6>

CPU_DP1_N1<6>

CPU_DP1_P2<6>

CPU_DP1_N2<6>

CPU_DP1_P3<6>

CPU_DP1_N3<6>

C C

CPU_DP1_CTRL_CLK<6>

CPU_DP1_CTRL_DATA<6>

12

0.1U_0402_25V6

CV17

12

0.1U_0402_25V6

CV18

12

0.1U_0402_25V6

CV21

12

0.1U_0402_25V6

CV22

12

0.1U_0402_25V6

CV28

12

0.1U_0402_25V6

CV29

12

0.1U_0402_25V6

CV13

12

0.1U_0402_25V6

CV14

+3.3V_RUN

2

1

5

34

QV3B

DMN65D8LDW-7_SOT 363-6

HDMI_TX_P2

HDMI_TX_N2

HDMI_TX_P1

HDMI_TX_N1

HDMI_TX_P0

HDMI_TX_N0

HDMI_CLKP

HDMI_CLKN

QV3A

DMN65D8LDW-7_SOT 363-6

HDMI_CTRL_CLK

6

HDMI_CTRL_DATA

4

1 2

RV647 5.6_0402_5%EMC@

HCM1012GH900BP_4P

2

2

1

1

LV3

@EMC@

1 2

RV649 5.6_0402_5%EMC@

1 2

RV650

HCM1012GH900BP_4P

2

2

1

1

LV6

@EMC@

1 2

RV652

RV653 5.6_0402_5%EMC@

1 2

HCM1012GH900BP_4P

2

2

1

1

LV9

@EMC@

1 2

RV655

1 2

RV656

HCM1012GH900BP_4P

2

2

1

1

LV12

@EMC@

1 2

RV658 5.6_0402_5%EMC@

1 2

RV21 2.2K_0402_5%

1 2

RV18 2.2K_0402_5%

HDMI_L_TX_P2

3

3

4

4

5.6_0402_5%EMC@

3

3

4

4

5.6_0402_5%EMC@

3

3

4

4

5.6_0402_5%EMC@

5.6_0402_5%EMC@

3

3

4

4

EMC@

RV648
200_0402_5%

1 2

HDMI_L_TX_N2

HDMI_L_TX_P1

EMC@

RV651
200_0402_5%

1 2

HDMI_L_TX_N1

HDMI_L_TX_P0

EMC@

RV654
200_0402_5%

1 2

HDMI_L_TX_N0

HDMI_L_CLKP

EMC@

RV657
200_0402_5%

1 2

HDMI_L_CLKN

+VHDMI_VCC

DFB request:
main source:SM070003V00(INPAQ_HCM1012GH900BP)
Footprint use 2nd source SM070004000(TAIYO_MCF12102G900-T_4P)
Pitch change from 0.5mm to 0.55mm

3

+3.3V_RUN

1M_0402_5%

RV22

CPU_DP1_HPD<6>

1 2

G

123

D

S

QV5

L2N7002WT1G_SC-70-3

HDMI_HPD

HDMI_TX_P2
HDMI_TX_N2
HDMI_TX_P1
HDMI_TX_N1
HDMI_TX_P0
HDMI_TX_N0
HDMI_CLKP
HDMI_CLKN

+5V_RUN

2

0.1U_0201_10V6K

1

@

CV23

RV20 20K_0402_5%

1

2

IN

GND2OUT

+3.3V_RUN

1 2

RV10 47 0_0402_1%
RV11 47 0_0402_1%
RV12 47 0_0402_1%
RV13 47 0_0402_1%
RV14 47 0_0402_1%
RV15 47 0_0402_1%
RV16 47 0_0402_1%
RV17 47 0_0402_1%

RV19 10K_0402_5%

+3.3V_RUN

3

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

AP2330W-7_SC59- 3

UV2

1 2

1

+VHDMI_VCC

0.1U_0201_10V6K

10U_0603_10V6M

1

2

CV27

12

@

CV26

HDMI connector

JHDMI1

HDMI_HPD

HDMI_CTRL_DATA
HDMI_CTRL_CLK

12

RV8@10K_0402_5%

HDMI_CEC
HDMI_L_CLKN

HDMI_L_CLKP
HDMI_L_TX_N0

HDMI_L_TX_P0
HDMI_L_TX_N1

HDMI_L_TX_P1
HDMI_L_TX_N2

HDMI_L_TX_P2

LINK 099BKAC19YBLCNF DONE

HDMI_OB

1

D

2

QV4

G

L2N7002WT1G_SC-70-3

S

3

CONN@

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11
10

GND

CK_shield

GND

CK+

GND

9

D0-

GND

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

CONCR_099BKAC19YBL CNF

20
21
22
23

SW1_DP2_P3_C

SW1_DP2_P3<23>

SW1_DP2_N3<23>

B B

SW1_DP2_P2<23>

SW1_DP2_N2<23>

SW1_DP2_P1<23>

SW1_DP2_N1<23>

SW1_DP2_P0<23>

SW1_DP2_N0<23>

9/29 vender request remove HPD Passgate Design

CV501

CV502

CV503

CV504

CV505

CV506

CV507

CV508

12

0.1U_0402_25V6

SW1_DP2_N3_C

12

0.1U_0402_25V6

SW1_DP2_P2_C

12

0.1U_0402_25V6

SW1_DP2_N2_C

12

0.1U_0402_25V6

SW1_DP2_P1_C

12

0.1U_0402_25V6

SW1_DP2_N1_C

12

0.1U_0402_25V6

SW1_DP2_P0_C

12

0.1U_0402_25V6

SW1_DP2_N0_C

12

0.1U_0402_25V6

+3.3V_RUN

1 2

RV501 100K_0402_5%

1 2

RV622 10K_ 0402_5%

1 2

RV502 100K_0402_5%

1 2

RV503 5.1 M_0402_5%

A A

+3.3V_RUN +VDISPLAY_VCC

UV27

0.1U_0201_10V6K

1

@

CV510

2

SW1_DP2_AUXN

DP_OCB#

SW1_DP2_AUXP

SW1_DP2_P14

5

4

1

OUT

IN

2

GND

EN

3

OCB

SY6288D20AAC_SOT23-5

DP_OCB#

+VDISPLAY_VCC

0.01UF_0402_25V7K

1

CV509

2

SW1_DP2_AUXN<23>

SW1_DP2_AUXP<23>

SW1_DP2_CADET<23>

SW1_DP2_HPD<23>

SW1_DP2_AUXN
SW1_DP2_N2_C
SW1_DP2_AUXP
SW1_DP2_P2_C

SW1_DP2_N3_C
SW1_DP2_N1_C
SW1_DP2_P3_C
SW1_DP2_P1_C

SW1_DP2_P14
SW1_DP2_N0_C

SW1_DP2_P0_C

mDP connector

JmDP1

CONN@

GND3
GND2
GND1

24
23
22
21

DP_PWR20GND4

19

GND

18

AUX_CH_N

17

LANE2_N

16

AUX_CH_P

15

LANE2_P

14

GND

13

GND

12

LANE3_N

11

LANE1_N

10

LANE3_P

9

LANE1_P

8

GND

7

GND

6

CONFIG2

5

LANE0_N

4

CONFIG1

3

LANE0_P

2

HPD

1

GND

ACON_MAR2E-2061800~D

LINK MAR2E-2061800 DONE

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF E NGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRI ETARY INF ORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHOR IZATION OF DEL L. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR D ISCLO SED TO ANY TH IRD
PART Y W IT HO UT D EL L' S E XP RE SS WR IT TEN C ON SE NT.

Titl e

Titl e

Titl e

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

HDMI CONN

HDMI CONN

HDMI CONN

LA-C461P

LA-C461P

LA-C461P

22 61Tuesday, October 13, 2015

22 61Tuesday, October 13, 2015

22 61Tuesday, October 13, 2015

1.0

1.0

1.0

5

4

3

2

1

+3.3V_RUN

SW1_PS8338_CFG0

1 2

RV51 4.7K_0402_5%

RV52 4.7K_0402_5%

@

RV60 4.7K_0402_5%

@

D D

C C

RV69 100K_0402_5%

RV67 1M_0402_5%

RV68 1M_0402_5%

@

RV70 100K_0402_5%

+3.3V_RUN

12

12

RV54

RV55

@

@

4.7K_0402_5%

4.7K_0402_5%

12

12

RV62

RV61

@

@

4.7K_0402_5%

4.7K_0402_5%

1 2

1 2

1 2

1 2

1 2

1 2

12

RV56

@

4.7K_0402_5%

12

RV64

@

4.7K_0402_5%

SW1_PS8338_SW

SW1_PS8338_P0

SW1_DP1_AUXN

SW1_DP1_CADET

SW1_DP2_CADET

SW1_DP1_AUXP

12

RV58

RV57

@

@

4.7K_0402_5%

12

RV63

RV65

@

@

4.7K_0402_5%

12

@

4.7K_0402_5%

12

@

4.7K_0402_5%

12

RV53

4.7K_0402_5%

12

RV100

4.7K_0402_5%

CPU_DP2_P0<6>
CPU_DP2_N0<6>

CPU_DP2_P1<6>
CPU_DP2_N1<6>

CPU_DP2_P2<6>
CPU_DP2_N2<6>

CPU_DP2_P3<6>

CPU_DP2_N3<6>

for support TMDS signal need contact SCL/SDA to P22,23

CPU_DP2_CTRL_CLK<6>
CPU_DP2_CTRL_DATA<6>

CPU_DP2_AUXP<6>

SW1_PS8338_P1

SW1_PS8338_PC10

SW1_PS8338_PC11

SW1_PS8338_PC20

SW1_PS8338_PC21

SW1_PS8338_PEQ

Port switching control or priority configuration. Internal pull down ~150KΩ , 3. 3V I/ O
For Control Switching Mode (CFG0 = L):
SW = L: Port1 is selected (default)
SW = H: Port2 is selected
For Automatic Switching Mode (CFG0 = H):
SW = L: Port1 has higher priority when both ports are plugged (default)
SW = H: Port2 has higher priority when both ports are plugged

vender sugguest MUX use LLEQ PEQ=M and PIO=H !!

Programmable input equalization levels, Internal pull down at ~ 150Kohm,3.3V I/O
PEQ =
L: default,LEQ, compensate channel loss up to 11.5dB @HBR2
H: HEQ, compensate channel loss up to 14.5dB @HBR2
M:LLEQ, compensate channel loss up to 8.5dB @HBR2

CPU_DP2_AUXN<6>

CV62 CV61 close to pin30 &57
CV66,CV69,CV70 close to pin5,21,51

0.01UF_0402_25V7K

12

CV61

CV71 0.1U_0402_25V6
CV72 0.1U_0402_25V6

CV73 0.1U_0402_25V6
CV74 0.1U_0402_25V6

CV75 0.1U_0402_25V6
CV76 0.1U_0402_25V6

CV77 0.1U_0402_25V6
CV78 0.1U_0402_25V6

CV79 0.1U_0402_25V6
CV80 0.1U_0402_25V6

0.01UF_0402_25V7K

12

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

CPU_DP2_HPD<6>

1 2
1 2

0.1U_0201_10V6K

CV66

1

1

CV62

2

2

+3.3V_RUN

0.1U_0201_10V6K

0.1U_0201_10V6K

CV70

CV69

1

2

CPU_DP2_P0_C
CPU_DP2_N0_C

CPU_DP2_P1_C
CPU_DP2_N1_C

CPU_DP2_P2_C
CPU_DP2_N2_C

CPU_DP2_P3_C
CPU_DP2_N3_C

SW1_PS8338_P1
SW1_PS8338_P0

CPU_DP2_AUXP_C
CPU_DP2_AUXN_C

SW1_PS8338_CFG0

SW1_PS8338_PC10
SW1_PS8338_PC11
SW1_PS8338_PC20
SW1_PS8338_PC21

Dock has high priority when both ports plugged

UV7

5

VDD33

21

VDD33

30

VDD33

51

VDD33

57

VDD33

6

IN_D0p

7

IN_D0n

9

IN_D1p

10

IN_D1n

12

IN_D2p

13

IN_D2n

15

IN_D3p

16

IN_D3n

4

IN_CA_DET

3

IN_HPD

2

I2C_CTL_EN

1

Pl1/SCL_CTL

60

Pl0/SDA_CTL

22

IN_DDC_SC L

23

IN_DDC_SD A

24

IN_AUXp

25

IN_AUXn

59

CFG0

58

CFG1

56

PC10

55

PC11

54

PC20

53

PC21

11

GND

19

GND

52

GND

61

PAD(GND)

PS8338BQFN60GTR-A0_QFN60_5X9

OUT1_AUXp_S CL

OUT1_AUXn _SDA

OUT2_AUXp_S CL

OUT2_AUXn _SDA

OUT1_CA_D ET

OUT2_CA_D ET

OUT1_D0p
OUT1_D0n

OUT1_D1p
OUT1_D1n

OUT1_D2p
OUT1_D2n

OUT1_D3p
OUT1_D3n

OUT2_D0p
OUT2_D0n

OUT2_D1p
OUT2_D1n

OUT2_D2p
OUT2_D2n

OUT2_D3p
OUT2_D3n

OUT1_HPD

OUT2_HPD

PEQ

CEXT
REXT

SW

PD

50
49

47
46

45
44

42
41

40
39

37
36

35
34

32
31

26
27

28
29

SW1_DP1_CADET

43
48

SW1_DP2_CADET

33
38

SW1_PS8338_SW

18

SW1_PS8338_PEQ

8
14
17
20

RV50

12

4.99K_0402_1%

SW1_DP1_P0 <24>
SW1_DP1_N0 <24>

SW1_DP1_P1 <24>
SW1_DP1_N1 <24>

SW1_DP1_P2 <24>
SW1_DP1_N2 <24>

SW1_DP1_P3 <24>
SW1_DP1_N3 <24>

SW1_DP2_P0 <22>
SW1_DP2_N0 <22>

SW1_DP2_P1 <22>
SW1_DP2_N1 <22>

SW1_DP2_P2 <22>
SW1_DP2_N2 <22>

SW1_DP2_P3 <22>
SW1_DP2_N3 <22>

SW1_DP1_AUXP <24>

SW1_DP1_AUXN <24>

SW1_DP2_AUXP <22>

SW1_DP2_AUXN <22>

SW1_DP1_CADET <24>
SW1_DP1_HPD <24>

SW1_DP2_CADET <22>
SW1_DP2_HPD <22>

2.2U_0402_6.3V6M

12

CV60

PS8338

mDP

PI0:Automatic EQ disable, Internal pull down ~150K ohm, 3.3 V I/O
PI0 = L: Automatic EQ enable(default)

B B

A A

H: Automatic EQ disable

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DP SW

DP SW

DP SW

LA-C461P

LA-C461P

LA-C461P

23 61Tuesday, October 13, 2015

23 61Tuesday, October 13, 2015

23 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

+3.3V_RUN

1 2

RV601 4.7K_0402_5%

1 2

RV602 4.7K_0402_5%

1 2

RV604 100K_0402_5%

1 2

D D

C C

RV605 100K_0402_5%

1 2

RV606 1M_0402_5%

1 2

RV607 1M_0402_5%

1 2

RV608 100K_0402_5%

1 2

RV609 100K_0402_5%

+3.3V_RUN

12

12

RV612

RV611

RV610

@

4.7K_0402_5%

RV616

@

4.7K_0402_5%

@

@

4.7K_0402_5%

4.7K_0402_5%

12

12

RV617

RV618

@

@

4.7K_0402_5%

4.7K_0402_5%

12

12

4

SW2_PS8338_CFG0

SW2_PS8338_SW

SW2_DP2_AUXN

SW2_DP1_AUXN

SW2_DP1_CADET

SW2_DP2_CADET

SW2_DP2_AUXP

SW2_DP1_AUXP

12

12

RV614

RV613

@

@

4.7K_0402_5%

4.7K_0402_5%

12

12

RV619

RV620

@

@

4.7K_0402_5%

4.7K_0402_5%

RV603

@

4.7K_0402_5%

RV621

@

4.7K_0402_5%

12

12

RV615

@

4.7K_0402_5%

12

SW1_DP1_P0<23>
SW1_DP1_N0<23>

SW1_DP1_P1<23>
SW1_DP1_N1<23>

SW1_DP1_P2<23>
SW1_DP1_N2<23>

SW1_DP1_P3<23>
SW1_DP1_N3<23>

SW2_PS8338_P0

SW2_PS8338_P1

SW2_PS8338_PC10

SW2_PS8338_PC11

SW2_PS8338_PC20

SW2_PS8338_PC21

SW2_PS8338_PEQ

0.01UF_0402_25V7K

0.01UF_0402_25V7K

12

CV604

CV606 0.1U_0402_25V6
CV607 0.1U_0402_25V6

CV608 0.1U_0402_25V6
CV609 0.1U_0402_25V6

CV610 0.1U_0402_25V6
CV611 0.1U_0402_25V6

CV612 0.1U_0402_25V6
CV613 0.1U_0402_25V6

12

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

SW1_DP1_CADET<23>
SW1_DP1_HPD<23>

0.1U_0201_10V6K

CV602

1

CV603

2

SW1_DP1_AUXP<23>
SW1_DP1_AUXN<23>

3

0.1U_0201_10V6K

CV601

1

1

2

2

SW1_DP1_P0_C
SW1_DP1_N0_C

SW1_DP1_P1_C
SW1_DP1_N1_C

SW1_DP1_P2_C
SW1_DP1_N2_C

SW1_DP1_P3_C
SW1_DP1_N3_C

SW2_PS8338_P1
SW2_PS8338_P0

SW2_PS8338_CFG0

SW2_PS8338_PC10
SW2_PS8338_PC11
SW2_PS8338_PC20
SW2_PS8338_PC21

0.1U_0201_10V6K

CV600

+3.3V_RUN

2

Dock has high priority when both ports plugged

UV26

5

VDD33

21

VDD33

30

VDD33

51

VDD33

57

VDD33

6

IN_D0p

7

IN_D0n

9

IN_D1p

10

IN_D1n

12

IN_D2p

13

IN_D2n

15

IN_D3p

16

IN_D3n

4

IN_CA_DET

3

IN_HPD

2

I2C_CTL_EN

1

Pl1/SCL_CTL

60

Pl0/SDA_CTL

22

IN_DDC_SC L

23

IN_DDC_SD A

24

IN_AUXp

25

IN_AUXn

59

CFG0

58

CFG1

56

PC10

55

PC11

54

PC20

53

PC21

11

GND

19

GND

52

GND

61

PAD(GND)

PS8338BQFN60GTR-A0_QFN60_5X9

OUT1_AUXp_S CL

OUT1_AUXn _SDA

OUT2_AUXp_S CL

OUT2_AUXn _SDA

OUT1_CA_D ET

OUT2_CA_D ET

OUT1_D0p

OUT1_D0n

OUT1_D1p

OUT1_D1n

OUT1_D2p

OUT1_D2n

OUT1_D3p

OUT1_D3n

OUT2_D0p

OUT2_D0n

OUT2_D1p

OUT2_D1n

OUT2_D2p

OUT2_D2n

OUT2_D3p

OUT2_D3n

OUT1_HPD

OUT2_HPD

PEQ

CEXT
REXT

SW

PD

50
49

47
46

45
44

42
41

40
39

37
36

35
34

32
31

SW2_DP1_AUXP

26

SW2_DP1_AUXN

27

SW2_DP2_AUXP

28

SW2_DP2_AUXN

29

SW2_DP1_CADET

43
48

SW2_DP2_CADET

33
38

SW2_PS8338_SW

18

SW2_PS8338_PEQ

8
14
17
20

RV600

12

4.99K_0402_1%

SW2_DP1_P0 <29>
SW2_DP1_N0 <29>

SW2_DP1_P1 <29>
SW2_DP1_N1 <29>

SW2_DP1_P2 <29>
SW2_DP1_N2 <29>

SW2_DP1_P3 <29>
SW2_DP1_N3 <29>

SW2_DP2_P0 <25>
SW2_DP2_N0 <25>

SW2_DP2_P1 <25>
SW2_DP2_N1 <25>

SW2_DP2_P2 <25>
SW2_DP2_N2 <25>

SW2_DP2_P3 <25>
SW2_DP2_N3 <25>

SW2_DP1_AUXP <29>

SW2_DP1_AUXN <29>

SW2_DP2_AUXP <25>

SW2_DP2_AUXN <25>

SW2_DP1_HPD <29>

SW2_DP2_HPD <25>

Port switc hing contro l o r p riority co nf i g ur at i on. I nter nal pul l d own ~150 KΩ , 3. 3V I /O

2.2U_0402_6.3V6M

For Contro l Switching Mode (CFG0 = L):
SW = L: Port1 is selected (default)

12

CV605

SW = H: Port2 is selected

For Autom at i c S wi tc hi ng Mode ( CF G0 = H):
SW = L: Port1 has higher priority when both ports are plug ged ( default)
SW = H: Port2 has higher priority when both ports are plug ged

1

WIGI

VMM3320

14
13

12

11
10

9

8

001

+3.3V_RUN_VMM

HDMI

1

AUX/DDC SW for DPB to E-DOCK AUX/DDC SW for DPC to E-DOCK

UV11

1

BE0

HUB_DP1_AUXP_C

HUB_DP1_AUXP<25>

B B

A A

HUB_SW2_AUXP<38>

HUB_DP1_AUXN<25>

HUB_SW2_AUXN<38>

HUB_DP1_CADET<25,38>

12

0.1U_0402_25V6

CV119

HUB_DP1_AUXN_C

12

0.1U_0402_25V6

CV120

HUB_DP1_CADET

1 2

RV508 1M_0402_5%

1 2

RV509 1M_0402_5%

HUB_DP1_CADET

HUB_DP0_CADET

2

3

4
5

6

7

+3.3V_RUN_VMM

2

G

DPB_CA_DET

DPC_CA_DET

5

VCC

A0

BE3

B0

BE1
A1

B1

GND

PI3C3125LEX_TSSOP14~D

12

13

100K_0402_5%

RV90

L2N7002WT1G_SC-70-3

D

S

A3

B3

BE2

A2

B2

HUB_DP1_CADETN

QV9

DP

4

CV118

1 2

0.1U_0201_10V6K

HUB_DP1_SCL <25>

HUB_DP1_SDA <25>

2

1
2

3

4
5

6

7

+3.3V_RUN_VMM

2

G

HUB_DP0_AUXP<25>

HUB_SW1_AUXP<38>

HUB_DP0_AUXN<25>

HUB_SW1_AUXN<38>

HUB_DP0_CADET<25,38>

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

3

CV122

CV123

12

0.1U_0402_25V6

HUB_DP0_AUXN_C

12

0.1U_0402_25V6

HUB_DP0_CADET

HUB_DP0_AUXP_C

UV12

BE0

VCC

A0

BE3

B0

BE1
A1

B1

GND

PI3C3125LEX_TSSOP14~D

100K_0402_5%

12

13

D

S

RV91

HUB_DP0_CADETN

L2N7002WT1G_SC-70-3

QV10

A3

B3

BE2

A2

B2

DELL CONFIDENTIAL/PROPRIETARY

+3.3V_RUN_VMM

14
13

12

11
10

9

8

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

CV121

1 2

0.1U_0201_10V6K

HUB_DP0_SCL <25>

HUB_DP0_SDA <25>

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DP SW

DP SW

DP SW

LA-C461P

LA-C461P

LA-C461P

24 61Tuesday, October 13, 2015

24 61Tuesday, October 13, 2015

24 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

2

1

+1.0V_RUN_VMM

LV22

1 2

BLM15PX181SN1D_2P

+1.0V_RUN_VMM

1 2

B B

A A

BLM15PX181SN1D_2P

+3.3V_RUN_VMM

LV24

1 2

BLM15PX181SN1D_2P

+1.0VS_VCCIO +1.0V_RUN_VMM

1 2

PAD-OPEN 1x1m

@

+3.3V_RUN +3.3V_RUN_VMM

1 2

PAD-OPEN 1x1m

LV23

PJP24

PJP25

+1.0V_VMM_VDD

12

12

+1.0V_VMM_VDDTX

12

+3.3V_RUN_VDDIO

12

+1.0V_RUN_VMM_UV29

12

12

10U_0603_10V6M

1

CV82

2

1U_0603_10V6K

1

CV87

2

10U_0603_10V6M

CV90

1

2

10U_0603_10V6M

1

CV94

2

RV659

27.4K_0402_1%

RV660

88.7K_0402_1%

0.1U_0201_10V6K

CV83

1

2

0.1U_0201_10V6K

CV88

12

0.1U_0201_10V6K

CV91

12

0.1U_0201_10V6K

CV95

12

+3.3V_RUN_VDDA

ADJ

0.1U_0201_10V6K

0.01UF_0402_25V7K

CV84

12

CV85

0.01UF_0402_25V7K

+1.0VS_VCCIO

CV89

0.01UF_0402_25V7K

0.01UF_0402_25V7K

CV92

CV93

12

0.01UF_0402_25V7K

0.01UF_0402_25V7K

12

CV96

CV97

0.786A

74mA

+5V_ALW

CV619 1U_0402_6.3V6K

CV618 10U_0603_10V6M

0.01UF_0402_25V7K

12

Low Power Mode by external Load switch

CV86

1 2

12

UV8B

E6

VDD

E7

VDD

E8

VDD

E9

VDD

H6

VDD

H7

VDD

H8

VDD

H9

VDD

E3

VDDRX

G3

VDDRX

C8

VDDTX0

C9

VDDTX0

F12

VDDTX1

G12

VDDTX1

J3

VDDLP

E5

VDDLP

H3

NC

F3

VDDRXA1

D3

VDDRX

E10

NC

C7

VDDTX0A1

C6

VDDTX0A2

H11

NC

E12

VDDTX1A1

D12

VDDTX1A2

J10

VGA_AVDD

K8

VGA_AVDD

K9

VGA_AVDD

K10

VGA_AVDD

J2

VDDSA

C3

VDDHRX_33

C4

VDDHRX_33

C11

VDDHTX0_33

C12

VDDIO

K3

VDDIO

K4

VDDIO

K11

VDDIO

K12

VDDIO

J4

VDDXT3V

VMM332 0BJGR_ BGA168

12

HUB_LP_EN

+1.8V_PRIM

RV6620_0402_5% @

3.3V Analog

1V Digital 1 V Analog

3.3V IO

UV29

10

POK

VCNTL

9

FB

EN

8

VOUT

VIN

7

VOUT

VIN

6

VOUT

VIN

GND

EM5106VT_DFN10_3X3

11

VDDRX_33
VDDTX0_33
VDDTX1_33

VGA_AVDD33
VGA_AVDD33

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS

VSS
VGA_AVSS
VGA_AVSS
VGA_AVSS
VGA_AVSS
VGA_AVSS

1
2

ADJ

3
4
5

Footpri nt is
APL5930QBI-TRG_TDFN10_3X3
main use EM5106VT
2nd use APL5930QBI-TRG

Pop U V29 &PJP37, depop PJP24&UV28 &PJP33

+3.3V_RUN_VDDA +3.3V_RUN_VMM

H5
C10
H12
K6

12

K7

C5
D5
D6
D7
D8
D9
D10
D11
E4
E11
F4
F5
F6
F7

F8
F9
F10
F11
G4
G5

G6
G7
G8
G9
G10
G11
H4
D4

J5
J11
J12
K5
H10
J6
J7
J8
J9

PAD-OPEN 1x1m

+1.0V_RUN_VMM_UV29

12

PJP37

0.01UF_0402_25V7K

12

CV98

12

RV661100K_0402_5%

0.1U_0201_10V6K

0.01UF_0402_25V7K

CV100

1

CV99

2

27MHZ_12PF_X1E000021042600

18P_0402_50V8J

CV115

+1.0V_RUN_VMM

12

12

CV61710U_0603_10V6M

1 2

BLM15PX181SN1D_2P

10U_0603_10V6M

12

CV101

+3.3V_RUN_VMM

YV2

1

IN

2

GND

LV25

1 2

CV114

UV8A

G1

RxP0

G2

RxN0

F1

RxP1

F2

RxN1

E1

RxP2

E2

RxN2

D1

RxP3

D2

RxN3

H1

RxAUXP

H2

RXAUXN

C2

RxSRCDET

J1

RxHPD

A13

RSTN_IN

B5

VDDIO

B6

VDDIO

B1

NC

A4

SPICS

B3

SPICLK

B4

SPIDI

A3

SPIDO

D14

GPIO0

D13

GPIO1

C14

GPIO2

C13

GPIO3

B14

GPIO4

B13

GPIO5

C1

GPIO6

M12

GPIO7

M13

NC

L3

NC

B2

LP_CTL

A5

LP_EN

K2

RX_STS

L2

TX0_S TS

M1

TX1_S TS

M2

TX2_S TS

K1

XIN

L1

XOUT

VMM332 0BJGR_ BGA168

B7

Tx0P0

A7

Tx0N0

B8

Tx0P1

A8

Tx0N1

B9

Tx0P2

A9

Tx0N2

B10

Tx0P3

A10

Tx0N3

A14

CAD0

B11

Tx0AUXP

A11

Tx0AUXN

B12

Tx0DDCS CL

A12

Tx0DDCS DA

A6

Tx0HPD

E13

Tx1P0

E14

Tx1N0

F13

Tx1P1

F14

Tx1N1

G13

Tx1P2

G14

Tx1N2

H13

Tx1P3

H14

Tx1N3

M14

CAD1

J13

Tx1AUXP

J14

Tx1AUXN

K13

Tx1DDCS CL

L14

Tx1DDCS DA

K14

Tx1HPD

L9

VGA_VSYNC

M9

VGA_HSYNC

M6

VGA_RP

L6

VGA_RN

M7

VGA_GP

L7

VGA_GN

M8

VGA_BP

L8

VGA_BN

L4

VGA_SCL

M4

VGA_SDA

M3

VGA_DET

M5

VGA_IREF

L5

NC

A1

SSDA

A2

SSCL

M11

NC

M10

RxDDCSDA

L12

NC

L13

NC

L11

NC

L10

RxDDCSCL

8/21 for layout routing

HUB_DP0_AUXP
HUB_DP0_AUXN
HUB_DP0_SCL
HUB_DP0_SDA

HUB_DP1_AUXP
HUB_DP1_AUXN
HUB_DP1_SCL
HUB_DP1_SDA

HUB_VGA_DET
HUB_VGA_IREF
HUB_VGA_NC

I2C_HUB_SDA
I2C_HUB_SCL

HUB_DP1_AUXN

HUB_GPIO6

HUB_SRCDET

HUB_SPI_WP#

HUB_GPIO4

HUB_GPIO5

HUB_DP1_SCL
HUB_DP1_SDA
HUB_GPIO8
HUB_GPIO7

I2C_HUB_SCL
I2C_HUB_SDA
HUB_DP0_SCL
HUB_DP0_SDA

HUB_DP0_AUXN

HUB_SPI_CS#

HUB_SPI_HOLD

HUB_VGA_DET

HUB_VGA_IREF

HUB_DP0_P0 < 38>
HUB_DP0_N0 <38>
HUB_DP0_P1 < 38>
HUB_DP0_N1 <38>
HUB_DP0_P2 < 38>
HUB_DP0_N2 <38>
HUB_DP0_P3 < 38>
HUB_DP0_N3 <38>
HUB_DP0_CADET <24,38 >
HUB_DP0_AUXP <24 >
HUB_DP0_AUXN <24>
HUB_DP0_SCL <24>
HUB_DP0_SDA <24>
HUB_DP0_HPD <38>

HUB_DP1_P0 < 38>
HUB_DP1_N0 <38>
HUB_DP1_P1 < 38>
HUB_DP1_N1 <38>
HUB_DP1_P2 < 38>
HUB_DP1_N2 <38>
HUB_DP1_P3 < 38>
HUB_DP1_N3 <38>
HUB_DP1_CADET <24,38 >
HUB_DP1_AUXP <24 >
HUB_DP1_AUXN <24>
HUB_DP1_SCL <24>
HUB_DP1_SDA <24>
HUB_DP1_HPD <38>

HUB_VGA_VSYNC < 38>
HUB_VGA_HSYNC <38>
HUB_VGA_RED <38>

HUB_VGA_GREEN <38>

HUB_VGA_BLUE <38>

HUB_VGA_SCL < 38>

HUB_VGA_SDA < 38>

T108@ PAD ~D

1 2

1 2

1 2

12

12

12

RPV1

1

8

2

7

3

6

4 5

2.2K_0804_8P4R_5%
RPV2

1

8

2

7

3

6

4 5

2.2K_0804_8P4R_5%

1 2

12

12

12

1 2

+3.3V_RUN_VMM

RV821M_0402_5%

RV832.2K_0402_5%

RV841M_0402_5%

RV517@2.2K_0402_5%

RV518@2.2K_0402_5%

RV519@2.2K_0402_5%

RV851M_0402_5%

RV8610K_0402_5%

RV872.2K_0402_5%

RV8810K_0402_5%

RV893.74K_0402_1%

VCC

CLK

CV1020.1U_0402_25V6
CV1030.1U_0402_25V6
CV1040.1U_0402_25V6
CV1050.1U_0402_25V6
CV1060.1U_0402_25V6
CV1070.1U_0402_25V6
CV1080.1U_0402_25V6
CV1090.1U_0402_25V6
CV1100.1U_0402_25V6
CV1110.1U_0402_25V6

+3.3V_RUN_VMM

8

HUB_SPI_HOLD

7

HUB_SPI_CLK

6

HUB_SPI_DO

5

SW2_DP2_P0_C
SW2_DP2_N0_C
SW2_DP2_P1_C
SW2_DP2_N1_C
SW2_DP2_P2_C
SW2_DP2_N2_C
SW2_DP2_P3_C
SW2_DP2_N3_C
SW2_DP2_AUXP_C
SW2_DP2_AUXN_C
HUB_SRCDET

HUB_SPI_WP#

HUB_SPI_CS#
HUB_SPI_CLK
HUB_SPI_DIN
HUB_SPI_DO

HUB_GPIO4
HUB_GPIO5
HUB_GPIO6
HUB_GPIO7
HUB_GPIO8
HUB_GPIO9
VMM332 0_LPM_D IS
HUB_LP_EN

CLK_27M_IN

CLK_27M_OUT

0.1U_0201_10V6K

1M_0402_5%

12

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

SW2_DP2_HPD<24>

PLTRST_VM M2320 #<11>

VMM332 0_LPM_D IS<9>

RV80

SW2_DP2_P0<24>
SW2_DP2_N0<24>
SW2_DP2_P1<24>
SW2_DP2_N1<24>
SW2_DP2_P2<24>
SW2_DP2_N2<24>
SW2_DP2_P3<24>

SW2_DP2_N3<24>

SW2_DP2_AUXP<24>

SW2_DP2_AUXN<24>

HUB_GPIO9

12

RV731M_0402_5% @

HUB_DP0_AUXP

12

RV741M_0402_5%

HUB_DP1_AUXP

12

RV751M_0402_5%

HUB_VGA_RED

12

RV76150_0402_1%

HUB_VGA_GREEN

12

RV77150_0402_1%

HUB_VGA_BLUE

12

RV78150_0402_1%

VMM332 0_LPM_D IS

12

RV79@100K_0402_5%

HUB_LP_EN

12

RV69810K_0402_5%

VMM332 0_LPM_D IS

12

RV5162.2K_0402_5% @

CLK_27M_OUT_R

3

OUT

GND

18P_0402_50V8J

4

RV81 2.2K_0402_5%

CV113

12

+3.3V_RUN_VDDIO

1 2

EEPROM

HUB_SPI_CS#
HUB_SPI_DIN
HUB_SPI_WP#

UV9

1

CS#

2

DO(IO1)

3

WP#(IO2)
GND4DI(IO0)

W25X10CVSNIG_SO8

HOLD#(IO3)

12

CV616 1U_0402_6.3V6K

@

+5V_ALW

+1.0V_RUN_VMM

12

PJP33

@

+1.0VS_VCCIO

HUB_LP_EN

UV28 @

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_W SON8

4.4mohm/6A
TR=12.5us@Vi n=1.05V

VOUT

GND

+1.0V_RUN_VMM_P

6

5

PAD-OPEN 1x1m

CV615 0.1U_0201_10V6K@

1 2

VMM2320 Operation power consumption for 1.0V=1.464A (Max)

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE U SED BY OR DIS CLOSED TO ANY THIRD
PART Y WI TH OUT DE LL 'S E XP RES S WR IT TE N CO NSE NT.

1

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Titl e

Titl e

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DP 1.2 MST HUB

DP 1.2 MST HUB

DP 1.2 MST HUB

LA-C461P

LA-C461P

LA-C461P

25 61Tuesday, Oct ober 13, 2015

25 61Tuesday, Oct ober 13, 2015

25 61Tuesday, Oct ober 13, 2015

1.0

1.0

1.0

5

LINK 50398-04041-001 DONE

JEDP1

D D

41
42
43
44
45

ACES_50398-04041-001

C C

+BL_PWR_SRC +5V_RUN+5V_RUN +5V_TSP

CONN@

0.1U_0603_50V7K

12

@

CV7

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

G1

37

37

G2

38

38

G3

39

39

G4

40

40

G5

+LCDVDD

1

2

USB20_N2_R
USB20_P2_R

LV1

EMC@

DISP_ON

EDP_AUXN_C
EDP_AUXP_C
EDP_TXP0_C
EDP_TXN0_C
EDP_TXP1_C
EDP_TXN1_C
EDP_TXP2_C
EDP_TXN2_C
EDP_TXP3_C
EDP_TXN3_C

0.1U_0201_10V6K

@

CV8

+3.3V_RUN
+3.3V_CAM

CAM_MIC_CBL_DET# <10,12>

Pin15: LOOP_BACK

+BL_PWR_SRC

1 2

EDP_HPD <6>

LCD_TST <31>

+LCDVDD

LCD_CBL_DET# <9>

BIA_PWM

BLM15BB221SN1D_2P

CV1 0.1U_0402_25V6
CV2 0.1U_0402_25V6
CV3 0.1U_0402_25V6
CV4 0.1U_0402_25V6
CV5 0.1U_0402_25V6

CV6 0.1U_0402_25V6
CV220 0.1U_0402_25V6
CV221 0.1U_0402_25V6
CV222 0.1U_0402_25V6
CV223 0.1U_0402_25V6

+3.3V_CAM +5V_TSP

0.1U_0201_10V6K

1

@

CZ1

2

4

DMIC0 <30>

DMIC_CLK0 <30>

100P_0402_50V8J

100P_0402_50V8J

12

12

CA5@EMC@

CA6@EMC@

CONN@

E-T_4260K-Q06N-23L

Link E-T_4260K-Q06N-23L DONE

3

Due to BC12/14, PC12 Mic. receive path is dif f er ent bet ween Touch
and Non-Touch Panel, so add TOUCH_SCREEN_DET# pin for dif f er ent

GND
GND

JTS1

verb table

1

1

2

2

3

3

4

4

5

5

6

6

7
8

TOUCH_SCREEN_DET#

+5V_TSP

TOUCH_SCREEN_DET# <12>
TOUCH_SCREEN_PD# <12>

TOUCH_SCREEN_DET#

+3.3V_RUN

10K_0402_5%

12

2

223

1

3

1

TOUCH_PANEL_PD# :

USB20_N9_R
USB20_P9_R

AZC199-02SPR7G_SOT23-3

@EMC@

DV4

Close lid >> TP_EN = 0 >> Disable touch events
Open lid >> TP_EN = 1 > > Enable touc h events

RV623

EXC24CQ900U_4P

1 2

LV27

EMC@

1

34

USB20_N9 <10>

USB20_P9 <10>

ESD depop locat i on

12
12
12
12
12
12
12
12
12
12

1

2

0.1U_0201_10V6K

@

CZ2

EDP_AUXN <6>

EDP_AUXP <6>
EDP_TXP0 <6>
EDP_TXN0 <6>
EDP_TXP1 <6>
EDP_TXN1 <6>
EDP_TXP2 <6>
EDP_TXN2 <6>
EDP_TXP3 <6>
EDP_TXN3 <6>

+3.3V_RUN

1

2

JIR1

CONN@

ACES_50209-0060N-P01

Link SP010023D00 done

0.1U_0201_10V6K

@

CA7

GND
GND

1
2
3
4
5
6
7
8

IR_CAM_D ET# <9>

+PWR_SRC

1
2
3
4
5
6

For Touchscreen

QV8

47K_0402_5%

12

RV6

LP2301ALT1G_SOT23-3

123

D

S

G

Close to JEDP1.17~19

BIA_PWM

4.7K_0402_5%

12

RV1

B B

WebCAM

3.3V_CAM_EN#<11>

USB20_P2<10>

A A

Close to JEDP1.30~31 Close to JEDP1.11 Close t o JEDP1.1 Close to JEDP1.10

DV1

EDP_BIA_PWM

3

1

2

BAT54CW_SOT323-3

BIA_PWM_EC

EDP_BIA_PWM <6>

BIA_PWM_EC <32>

DISP_ON

4.7K_0402_5%

12

RV2

Backlight POWER

+3.3V_CAM +3.3V_RUN

EXC24CQ900U_4P

1 2

LZ1

EMC@

QZ1

LP2301ALT1G_SOT23-3

123

D

S

G

USB20_P2_R

34

USB20_N2_R

+PWR_SRC

1000P_0402_50V7K

12

CV11

0.01U_0402_50V7K

1

CV374

2

DV2

1

BAT54CW_SOT323-3

S

4 5

270K_0402_5%

12

RV4

BL_PWR_SRC_ON

1 2

RV5 47K_0402_5%

EN_INVPWR<32>USB20_N2<10>

3

2

QV1

D

6

2
1

G

AO6405_TSOP6

3

QV2

L2N7002WT1G_SC-70-3

123

D

S

G

PANEL_BKLEN <6>

PANEL_BKEN_EC <31>

+BL_PWR_SRC

0.1U_0603_50V7K

12

CV12

LCDVDD POWER

10U_0603_10V6M

3.3V_TS_EN<9>

CV9

@

12

LCD_VCC_TEST_EN<31>

ENVDD_PCH<6,32>

2

G

+LCDVDD +EDP_VDD

L2N7002WT1G_SC-70-3

13

D

QV7

S

PJP29

1 2

PAD-OPEN1x1m

BAT54CW_SOT323-3

+3.3V_ALW

5

100K_0402_5%

RV3

0.01UF_0402_25V7K

@

CV10

12

4

1 2

VOUT

GND

/OC

EN_LCDPWR

UV24

VIN

EN

1

2

3

DV3

2

3

G524B1T11U _SOT23-5

1

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

eDP CONN & Touch screen

eDP CONN & Touch screen

eDP CONN & Touch screen

LA-C461P

LA-C461P

LA-C461P

26 61Tuesday, October 13, 2015

26 61Tuesday, October 13, 2015

26 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

+3.3V_LAN

RL1@ 10K_0402_5%

RL2@ 10K_0402_5%

RL4 4.7K_0402_5%@

D D

PM_LANPHY_ENABLE<11>

+0.9V_LAN

22U_0603_6.3V6M

0.1U_0201_10V6K

1

12

CL12

2

Note:
+1.0V_LAN will work at 0.95V to 1.15V

C C

1 2

1 2

CL9

1

2

12

0.1U_0201_10V6K

CL10

1

2

TP_LAN_JTAG_TMS

TP_LAN_JTAG_TCK

CLKREQ_PCIE#4

1 2

RL7 0_0402_5%

@

LAN CKLT0.7

0.1U_0201_10V6K

0.1U_0201_10V6K

CL11

CL8

1

2

+3.3V_LAN

XTALO_R

27P_0402_50V8J

CL13

1 2

10K_0402_5%

12

RL5@

10K_0402_5%

12

RL9@

8/28 schematic review

1 2

RL34 0_0402_5%

@

YL1

3

OUT

4

GND

25MHZ_18PF_7V25000034

CLKREQ_PCIE#4<11>

PLTRST_LAN#<11>

CLK_PCIE_P4<11>
CLK_PCIE_N4<11>

PCIE_PRX_DTX_P9<10>

PCIE_PRX_DTX_N9<10>

PCIE_PTX_DRX_P9<10>

PCIE_PTX_DRX_N9<10>

SML0_SMBCLK<8>

SML0_SMBDATA<8>

LAN_WAKE#<11,32>

SMBus Device Address 0xC8

IN

GND

LAN_DISABLE#_R<31>

T88@ PAD~D
T89@ PAD~D

12

RL11

1

2

1M_0402_5%

1 2

12

CL1 0.1U_0402_25V6

12

CL2 0.1U_0402_25V6

1 2

CL5 0.1U_0402_25V6

1 2

CL6 0.1U_0402_25V6

27P_0402_50V8J

CL14

4

CLKREQ_PCIE#4

PCIE_PRX_C_DTX_P9

PCIE_PRX_C_DTX_N9

PCIE_PTX_C_DRX_P9

PCIE_PTX_C_DRX_N9

LAN_DISABLE#_R

LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#

TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK

LAN_TEST_EN

3.01K_0402_1%

1K_0402_5%

12

12

RL12

UL1

48

CLK_REQ_N

36

PE_RST_N

44

PE_CLKP

45

PE_CLKN

38

PETp

39

PETn

41

PERp

42

PERn

28

SMB_CLK

31

SMB_DATA

2

LANWAKE_N

3

LAN_DISABLE_N

26

LED0

27

LED1

25

LED2

32

JTAG_TDI

34

JTAG_TDO

33

JTAG_TMS

35

JTAG_TCK

9

XTALO

XTAL_OUT

10

XTALI

XTAL_IN

30

TEST_EN

12

RBIAS

RL13

WGI219LM-QREF- A0_QFN48_6X6~D

change to SA000081G0L, S IC A32 W GI219LM QREF A0 QFN 48P PHY

PCIE

SMBUS

JTAG LED

MDI_PLUS 0

MDI_MINUS 0

MDI_PLUS 1

MDI_MINUS 1

MDI_PLUS 2

MDI

MDI_MINUS 2

MDI_PLUS 3

MDI_MINUS 3

SVR_EN_N

RSVD_VCC3P3_1

VDD3P3_IN

VDD3P3_15
VDD3P3_19
VDD3P3_29

VDD0P9_47
VDD0P9_46
VDD0P9_37

VDD0P9_43

VDD0P9_11

VDD0P9_40
VDD0P9_22
VDD0P9_16

VSS_EPAD

3

LAN_MDIP0

13

LAN_MDIN0

14

LAN_MDIP1

17

LAN_MDIN1

18

LAN_MDIP2

20

LAN_MDIN2

21

LAN_MDIP3

23

LAN_MDIN3

24

VCT_LAN_R1

6

+RSVD_VCC3P3_1

1

5

4

VDD3P3_4

15
19
29

47
46
37

43

11

40
22
16
8

VDD0P9_8

CTRL0P9

8/28 schematic review

+REGCTL_PNP10RES_BIAS

7

49

Place CL3 , CL4 and LL1 close t o UL1

EMC LL2~LL9 main change from SHI00005I00 to SHI0000CB00

Layout Not i ce : Pl ace bead as
close UL4 as possible

1 2

RL71 2.2_0603_5%EMC@

1 2

RL72 2.2_0603_5%EMC@

1 2

RL73 2.2_0603_5%EMC@

1 2

RL74 2.2_0603_5%EMC@

1 2

RL75 2.2_0603_5%EMC@

1 2

RL76 2.2_0603_5%EMC@

1 2

RL77 2.2_0603_5%EMC@

1 2

RL78 2.2_0603_5%EMC@

RL3 0_0402_5%@

+3.3V_LAN_OUT

+0.9V_LAN

1 2

Idc_mi n=5 00m A
DCR=100mo hm

12

0.1U_0201_10V6K

12

LAN CKLT0.7

LL14.7UH_BRC2012T4R7MD_20%

12

CL7

22U_0805_6.3V6M

RL8@ 0_0603_5%

1

CL28

2

+0.9V_LAN

0.1U_0201_10V6K

CL3

1

12

2

11/2 0 I NTE L R EVI EW

RL6 4.7K_0402_5%

Place CL28 close to UL1.5

10U_0603_10V6M

@

CL4

+3.3V_LAN

12

LAN_MDIP0_L
LAN_MDIN0_L

LAN_MDIP1_L
LAN_MDIN1_L

LAN_MDIP2_L
LAN_MDIN2_L

LAN_MDIP3_L
LAN_MDIN3_L

+3.3V_LAN

2

+3.3V_LAN

1

2

LAN_MDIN3_L

LAN_MDIP3_L

LAN_MDIN2_L

LAN_MDIP2_L SW_LAN0_MDIN0

LAN_MDIN1_L

LAN_MDIP1_L

LAN_MDIN0_L

LAN_MDIP0_L

DOCKED<31>

LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#

LAN ANALOG SWITCH

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

CL25

CL26

1

2

CL27

1

2

UL4

2

A0+

3

A0-

6

A1+

7

A1-

9

A2+

10

A2-

11

A3+

12

A3-

13

SEL

15

LEDA0

16

LEDA1

42

LEDA2

5

PD

43

PAD_GND

PI3L720ZHEX_TQFN42_9X3P5

1

4

8

14

21

30

39

VDD

VDD

VDD

VDD

VDD

VDD

VDD

LEDB0
LEDB1
LEDB2

LEDC0
LEDC1
LEDC2

B0+

B0-

B1+

B1-

B2+

B2-

B3+

B3-

C0+

C0-

C1+

C1-

C2+

C2-

C3+

C3-

For Layout rou t i ng , c hange port ma ppi ng

+3.3V_LAN

1

DOCKED

SW_LAN0_MDIN3

38

SW_LAN0_MDIP3

37

SW_LAN0_MDIN2

34

SW_LAN0_MDIP2

33

SW_LAN0_MDIN1

29

SW_LAN0_MDIP1

28

25

SW_LAN0_MDIP0

24

SW_LAN0_ACT LED_YEL#

17

SW_LAN0_100_O RG#

18

SW_LAN0_10_G RN#

41

36

SW_LAN1_MDIN3 <38>

35

SW_LAN1_MDIP3 <38>

32

SW_LAN1_MDIN2 <38>

31

SW_LAN1_MDIP2 <38>

27

SW_LAN1_MDIN1 <38>

26

SW_LAN1_MDIP1 <38>

23

SW_LAN1_MDIN0 <38>

22

SW_LAN1_MDIP0 <38>

19

SW_LAN1_ACT LED_YEL# <38>

20

SW_LAN1_100_O RG# <38>

40

SW_LAN1_10_G RN# <38>

1: TO DOCK

0: TO RJ45

470P_0402_50V7K

0.1U_0201_10V6K

1

12

CL18

CL19

2

TL1

SW_LAN0_MDIN3

When LAN & WLAN are exist at the same time, WLAN will disable

B B

LOM_SPD100LED_ORG#

LOM_SPD10LED_GRN#

SW_LAN0_ACT LED_YEL#

+3.3V_LAN

12

RL29
1M_0402_5%

SW_LAN0_100_O RG#

+3.3V_LAN

12

RL30

A A

1M_0402_5%

SW_LAN0_10_G RN#

For WLAN can't recognize during enable
Unobtrusive m ode(BITS152312)

+3.3V_LAN

5

1

P

B

2

A

G

TC7SH08FU_SSOP5~D

3

QL1A

DMN65D8LDW-7_SOT363-6

1

6

2

SYS_LED_MASK#

QL1B

DMN65D8LDW-7_SOT363-6

DMN65D8LDW-7_SOT363-6

DMN65D8LDW-7_SOT363-6

5

1

2

5

5

34

SYS_LED_MASK#

QL2A

6

SYS_LED_MASK#

QL2B

34

LED_100_ORG#

@

CL15

1 2

0.1U_0201_10V6K

4

O

UL2

LAN_ACTLED_YEL#

LED_10_GRN#

WLAN_DISBL# <31>

SYS_LED_MASK# <31,40 >

0.1U_0201_10V6K

12

CL16

0.1U_0201_10V6K

CL20

SW_LAN0_MDIP3

0.1U_0201_10V6K

SW_LAN0_MDIN1

12

CL17

SW_LAN0_MDIP1

SW_LAN0_MDIN2

SW_LAN0_MDIP2

0.1U_0201_10V6K

SW_LAN0_MDIN0

12

12

CL21

SW_LAN0_MDIP0

4

1

TD1+

2

TD1-

3

TDCT1

4

TDCT2

5

TD2+

6

TD2-

7

TD3+

8

TD3-

9

TDCT3

10

TDCT4

11

TD4+

12

TD4-

MHPC_NS692417

GND

GND

CHASSIS

CHASSIS

1:1

1:1

1:1

1:1

1 2

EMC@

CL22

150P_1808_2.5KV8J

12/17:INTEL request 1500PF/3KV, EMI ask pop 150pF first,1500PF wait EA result

RJ45_MDIN3

24

TX1+

RJ45_MDIP3

23

TX1-

22

TXCT1

21

TXCT2

20

TX2+

19

TX2-

18

TX3+

17

TX3-

16

TXCT3

15

TXCT4

14

TX4+

13

TX4-

use 40mil trace if necessary

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT M AY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

RJ45_MDIN1

RJ45_MDIP1

RJ45_MDIN2

RJ45_MDIP2

RJ45_MDIN0

RJ45_MDIP0

+GND_CHASSIS

Z2808

Z2806

Z2807

Z2805

12

12

12

12

RL17 75_0402_1%

RL16 75_0402_1%

RL15 75_0402_1%

RL18 75_0402_1%

LAN_ACTLED_YEL# LAN_ACTLED_YEL_R#

LED_10_GRN# LED_10_GRN_R#

LED_100_ORG# LED_100_ORG_R#

2

1 2

RL14 150_0402_5%

RJ45_MDIN3

RJ45_MDIP3

RJ45_MDIN1

RJ45_MDIN2

RJ45_MDIP2

RJ45_MDIP1

RJ45_MDIN0

RJ45_MDIP0

1 2

RL19 150_0402_5%

1 2

RL20 150_0402_5%

DELL CONFIDENTIAL/PROPRIETARY

Titl e

Titl e

Titl e

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

RJ45 LOM circuit

+3.3V_LAN:20mils

JLOM1

CONN@

10

Yellow LED-

9

Yellow LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

11

Green LED-

13

Orange LED-

12

Green-Orange LED+

SANTA_130456-511

Link 130456-511 DON E

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

LAN

LAN

LAN

LA-C461P

LA-C461P

LA-C461P

1

27 61Tuesday, October 13, 2015

27 61Tuesday, October 13, 2015

27 61Tuesday, October 13, 2015

17

GND

16

GND

15

GND

14

GND

1.0

1.0

1.0

A

+3.3V_MMI_IN+3.3V_RUN

PJP26

1 2

1 1

+3.3V_MMI_AUX

2 2

PAD-OPEN1x2m

+3.3V_MMI_AUX+3.3V_MMI_IN

12

R274 0_0603_5%@

MEDIACAR D_IRQ#

1 2

RR19 10K_0402_5%

support D3 Hot(if D3 cold PIN11,PIN27 need Add MOS on/of f 3 V3AUX)

7/18 Vender suggest.

PCIE_PTX_DRX_P10<10>

PCIE_PTX_DRX_N10<10>
PCIE_PRX_DTX_P10<10>
PCIE_PRX_DTX_N10<10>

+1.2V_LDO

12

B

PCH_PLTRST#_AND<11,29,33,35>

CLKREQ_PCIE#5<11>

CLK_PCIE_P5<11>

1

2

1 2
1 2
1 2
1 2

0.1U_0201_10V6K

CR10

CLK_PCIE_N5<11>

MEDIACAR D_IRQ#<8>

0.1U_0201_10V6K

1

CR13

2

CR24 0.1U_0402_25V6
CR25 0.1U_0402_25V6
CR26 0.1U_0402_25V6
CR27 0.1U_0402_25V6

CR13 close to UR2.10
CR9 CR10 close to UR2.14

4.7U_0603_6.3V6K

CR9

PCIE_PTX_C_DRX_P10
PCIE_PTX_C_DRX_N10
PCIE_PRX_C_DTX_P10
PCIE_PRX_C_DTX_N10

+1.8V_RUN_CARD

SD/MMCCD#

+RREF

12

+3.3V_MMI_AUX +3.3V_MMI_IN

0.1U_0201_10V6K

10U_0402_6.3V6M

1

1

CR42

CR8

2

2

11

27

UR2

1

PERST#
CLK_REQ#

REFCLKP
REFCLKN

HSIP
HSIN
HSOP
HSON

WAKE#
MS_INS#
SD_CD#

AV12
DV12S

SD_VDD2

RREF

3V3aux

RTS5242

E-PAD

33

RR20

6.2K_0402_1%

2

5
6

3
4
7
8

32
31
30

10
14

13

9

C

10U_0402_6.3V6M

0.1U_0201_10V6K

1

1

CR36

2

2

CARD_3V3

3V3_IN

DV33_18

SP1
SP2
SP3
SP4
SP5
SP6
SP7

SD_LN1_P

SD_LN1_M

SD_LN0_P

SD_LN0_M

SDREG2

GPIO

RTS5242-GR_QFN32_4X4

CR43

12

+DV33_18

18

15

SD/MMCDAT1/RCLK-

16

SD/MMCDAT0/RCLK+

17

SD/MMCCLK

19

SD/MMCCMD

20

SD/MMCDAT3

21

SD/MMCDAT2

29

SDWP

SD_UHS2_D1P

22

SD_UHS2_D1N

23

SD_UHS2_D0P

26

SD_UHS2_D0N

25

24

+SDREG2

28

SD_GPIO

+3.3V_RUN_CARD

RR21 0_0402_5%@
RR22 0_0402_5%@
RR1EMC@ 10_0402_5%
RR23 0_0402_5%@
RR17 0_0402_5%@EMC@
RR18 0_0402_5%@EMC@

7/18 Vender s uggest

1 2

CR35 1U_0402_6. 3V6K

12

RR1610K_0402_5%

1 2

CR37 1U_0402_6. 3V6K

1 2
1 2
1 2
1 2
1 2
1 2

+3.3V_MMI_AUX

D

SD/MMCDAT1/RCLK-_R
SD/MMCDAT0/RCLK+_R

SD/MMCCLK_R
SD/MMCCMD_R
SD/MMCDAT3_R
SD/MMCDAT2_R

@EMC@

5P_0402_50V8C

12

CR23

EMI depop locati on

E

HOST_SD _WP#

3 3

4 4

High

Low

SDWP_Q SDWP

High

High

Low

Low

High

High

Low

High

STATUS

Write Protect(SD LOCK)

Write Enable

Write Protect(SD& FW LOCK)

Write Protect(FW LOCK)

QR1

L2N7002WT1G_SC-70-3

SDWP

HOST_SD_WP #<9>

+3.3V_RUN_CARD +1.8V_RUN_CARD

CR38,CR39 near JSD1.4 CR40,CR41 near JSD1.14

1 3

D

2

2

1

SDWP_Q

S

G

CR39

1 2

CR38

0.1U_0201_10V6K

4.7U_0603_6.3V6K

+3.3V_RUN_CARD
+1.8V_RUN_CARD

2

CR40

CR41

1 2

1

0.1U_0201_10V6K

4.7U_0603_6.3V6K

SD/MMCCMD_R
SD/MMCCLK_R

SD/MMCCD#
SDWP_Q

SD/MMCDAT0/RCLK+_R
SD/MMCDAT1/RCLK-_R
SD/MMCDAT2_R
SD/MMCDAT3_R
SD_UHS2_D0P
SD_UHS2_D0N
SD_UHS2_D1P
SD_UHS2_D1N

JSD1

CONN@

4

VDD/VDD1

14

VDD2

2

CMD

5

CLK

18

CARD DETECT

19

WRITE PROTEC

7

DAT0/RCLK+

8

DAT1/RCLK-

9

DAT2

1

CD/DAT3

11

D0+

12

DO-

16

D1+

15

D1-

3

VSS1

6

VSS2

10

VSS3

13

VSS4
VSS517GND7

T-SOL_156-2000302608_NR

GND1
GND2
GND3
GND4
GND5
GND6

20
21
22
23
24
25
26

LINK SP070011U00 DONE

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Titl e

Titl e

PROPRIETARY NOTE: THIS SHEET OF E NGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRI ETARY INF ORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHOR IZATION OF DEL L. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR D ISCLO SED TO ANY TH IRD
PART Y W IT HO UT D EL L' S E XP RE SS WR IT TEN C ON SE NT.

A

B

C

D

Titl e

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Card Reader

Card Reader

Card Reader

LA-C461P

LA-C461P

LA-C461P

E

28 61Tuesday, October 13, 2015

28 61Tuesday, October 13, 2015

28 61Tuesday, October 13, 2015

1.0

1.0

1.0

5

+3.3V_WWAN

WWAN_PWR_EN

1 2

RZ43@ 0_0402_5%

SLOT2_CONFIG_3<31>

USB20_P10<10>
USB20_N10<10>

D D

PCIE_PTX_DRX_N3<10>
PCIE_PTX_DRX_P3<10>

Reserve for RF tunable

C C

+3.3V_WWAN

12

CZ58 0.1U_0402_25V6
CZ59 0.1U_0402_25V6

@EMC@

CZ79 .047U_0402_16V7K

@EMC@

CZ80 .047U_0402_16V7K

@EMC@

CZ81 .047U_0402_16V7K

@EMC@

CZ83 .047U_0402_16V7K

.047U_0402_16V7K

.047U_0402_16V7K

12

12

CZ51

CZ52

SLOT2_CONFIG_0<31>
WWAN_WAKE#<31>

1 2
1 2

1 2
1 2
1 2
1 2

SLOT2_CONFIG_1<31>

SLOT2_CONFIG_2<31>

33P_0402_50V8J

USB3_PRX_L_DTX_N5
USB3_PRX_L_DTX_P5

USB3_PTX_L_DRX_N5
USB3_PTX_L_DRX_P5

PCIE_PRX_DTX_N3<10>
PCIE_PRX_DTX_P3<10>

CLK_PCIE_N0<11>
CLK_PCIE_P0<11>

33P_0402_50V8J

22U_0603_6.3V6M

1

12

12

CZ53

+

CZ54

CZ55

2

NGFF slot B Key B

JNGFF2

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_P3

ANTCTL0
ANTCTL1
ANTCTL2
ANTCTL3

150U_B2_6.3VM_R35M

@

CZ57

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

GND

BELLW_80149-3221

WWAN_RADIO_DIS#<31>

HW_GPS_DISABLE#<31>

CONN@

4

3

2

1

NGFF slot A Key A

JNGFF1

CONN@

+3.3V_WWAN

2

2

4

WWAN_PWR_EN

4

6

WWAN_RADIO_DIS#_R

6

8

8

10

10

12

12

14

14

16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66

68

HW_GPS_DISABLE#_R

UIM_RESET
UIM_CLK
UIM_DATA

ISH_I2C2 _SCL_R
ISH_I2C2 _SDA_ R

RZ76 0_0402_5%

@

RZ77 0_0402_5%

@

PCH_PLTRST#_AND

PCIE_WAKE#

SIM_DET

1 2

DZ5

RB751S40T1G_SOD523-2

1 2

DZ6

RB751S40T1G_SOD523-2

+SIM_PWR

12
12

9/24: Reserve for embedded locat i on ,refer Intel P DG 0. 9

CLKREQ_PCIE#0 <11>

WLAN

ISH_I2C2 _SCL <9>
ISH_I2C2 _SDA <9>

WIGI

WWAN_RADIO_DIS#_R

HW_GPS_DISABLE#_R

16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66

GND

SW2_DP1_N3<24>
SW2_DP1_P3<24>

SW2_DP1_N2<24>
SW2_DP1_P2<24>

PCIE_PTX_DRX_P5<10>
PCIE_PTX_DRX_N5<10>

PCIE_PTX_DRX_P6<10>
PCIE_PTX_DRX_N6<10>

WLAN_WIGIG60GHZ_DIS#<31>

USB20_P8<10>
USB20_N8<10>

1 2
1 2

CV145 0.1U_0402_25V6
CV146 0.1U_0402_25V6

1 2
1 2

CV148 0.1U_0402_25V6
CV147 0.1U_0402_25V6

SW2_DP1_HPD<24>

1 2

CZ13 0.1U_0402_25V6

1 2

CZ14 0.1U_0402_25V6

PCIE_PRX_DTX_P5<10>
PCIE_PRX_DTX_N5<10>

CLK_PCIE_P1<11>
CLK_PCIE_N1<11>

CLKREQ_PCIE#1<11>

PCIE_WAKE#<31,35>

1 2

CZ21 0.1U_0402_25V6

1 2

CZ22 0.1U_0402_25V6

PCIE_PRX_DTX_P6<10>
PCIE_PRX_DTX_N6<10>

CLK_PCIE_P2<11>
CLK_PCIE_N2<11>

1 2

DZ1

RB751S40T1G_SOD523-2

SW2_DP1_N3_C
SW2_DP1_P3_C

SW2_DP1_N2_C
SW2_DP1_P2_C

PCIE_PTX_C_DRX_P5
PCIE_PTX_C_DRX_N5

PCIE_WAKE#

PCIE_PTX_C_DRX_P6
PCIE_PTX_C_DRX_N6

WLAN_WIGIG60GHZ_DIS#_R

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

GND

CONCR_213AAAA32FA

+3.3V_WLAN

2

2

4

4

6

6

8

8

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66

68

+3.3V_WLAN

1

2

SW2_DP1_AUXN_C
SW2_DP1_AUXP_C

SW2_DP1_N1_C
SW2_DP1_P1_C

SW2_DP1_N0_C
SW2_DP1_P0_C

WIGIG_32KHZ
PCH_PLTRST#_AND
BT_RADIO_DIS#_R

WLAN_WIGIG60GHZ_DIS#_R

ISH_UAR T0_RXD_ R
ISH_UAR T0_TXD_R

@

ISH_UAR T0_CTS#_ R

@

ISH_UAR T0_RTS#_ R

@

PCH_PLTRST#_AND

@

PCIE_WAKE#

12
12

CV1500.1U_0402_25V6
CV1490.1U_0402_25V6

12
12

CV1520.1U_0402_25V6
CV1530.1U_0402_25V6

12
12

CV1560.1U_0402_25V6
CV1570.1U_0402_25V6

PCH_CL_RST1# <8>

PCH_CL_DATA1 <8>

PCH_CL_CLK1 <8>

12

RZ560_0402_5%

@

PCH_PLTRST#_AND <11,28,33,35>

12
12

RZ78 0_0402_5%

12

RZ79 0_0402_5%

12

RZ80 0_0402_5%
RZ81 0_0402_5%

CLKREQ_PCIE#2 <11>

9/24: Reserve for embedded locat i on ,refer Intel P DG 0. 9

.047U_0402_16V7K

0.1U_0201_10V6K

12

@

CZ20

CZ15

0.1U_0201_10V6K

.047U_0402_16V7K

12

CZ16

0.1U_0201_10V6K

1

1

CZ17

CZ18

2

2

SW2_DP1_AUXN <24>
SW2_DP1_AUXP <24>

SW2_DP1_N1 <24>
SW2_DP1_P1 <24>

SW2_DP1_N0 <24>
SW2_DP1_P0 <24>

SUSCLK <11,35>

ISH_UAR T0_RXD <9>
ISH_UAR T0_TXD <9 >
ISH_UAR T0_CTS# <9>
ISH_UAR T0_RTS# <9>

4.7U_0603_6.3V6K

12

CZ19

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66

GND

BT_RADIO_DIS#_R

Power Rating TBD

Voltage

PWR

Tolerance

Rail

+3.3V

Primary Power Aux Power

Peak Norma l Normal

1 2

1 2

USB3_PRX_L_DTX_P5

USB3_PRX_L_DTX_N5

USB3_PTX_L_DRX_N5

BT_RADIO_DIS#<31>

DI7

USB3_PRX_L_DTX_N5 USB3_PRX _L_DTX_N5

USB3_PRX_L_DTX_P5 USB 3_PRX_L_DTX_P5

USB3_PTX_L_DRX_N5 USB3_PTX_L_DRX_N5

USB3_PTX_L_DRX_P5 USB 3_PTX_L_DRX_P5

EMC@

1

1

2

2

4

4

5

5

3

3

8

L05ESDL5V0NA-4_SLP2510P8-10-9

9

10

8

9

7

7

6

6

USB3_PRX_DTX_P5<10>

USB3_PRX_DTX_N5<10>

USB3_PTX_C_DRX_P5 USB3_PTX_L_DRX_P5

USB3_PTX_DRX_P5<10>

B B

SIM Card Push-Push

+SIM_PWR

C263

A A

USB3_PTX_DRX_N5<10>

1U_0402_6.3V6K

UIM_RESET

12

UIM_CLK

JSIM1

1

VCC

2

RST

3

CLK

4

RFU1

10

GND

11

GND

12

GND

13

GND

T-SOL_5-991503004000-6

UIM_RESET

UIM_CLK

UIM_DATA

12

CI30 0.1U_0402_25V6

USB3_PTX_C_DRX_N5

12

CI29 0.1U_0402_25V6

CONN@

5

GND

6

UIM_DATA

VPP

7

I/O

8

RFU2

SIM_DET_R SIM_DET

9

DTSW

GND
GND
GND

@

14
15
16

33P_0402_50V8J

@EMC@

33P_0402_50V8J

@EMC@

12

12

CZ65

CZ66

1 2

RI27 0_0402_5%

@EMC@

1 2

RI28 0_0402_5%

@EMC@

RI29 0_0402_5%

@EMC@

RI30 0_0402_5%

@EMC@

1 2

RI31 0_0402_5%

33P_0402_50V8J

@EMC@

12

CZ67

1 2

DZ2

RB751S40T1G_SOD523-2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

For RF team req uest

5

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

3

2

Tit le

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

NGFF Card

NGFF Card

Document Number Rev

Document Number Rev

Document Number Rev

NGFF Card

LA-C461P

LA-C461P

LA-C461P

1

29 61Tuesd ay, O ctob er 13 , 20 15

29 61Tuesd ay, O ctob er 13 , 20 15

29 61Tuesd ay, O ctob er 13 , 20 15

1.0

1.0

1.0

2

1

SWAP PIN d efine, because pin1 of Footprint is difference with BC12

1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two trans ducer units in one speaker box.)

Internal Speakers Header

INT_SP K_L+
INT_SP K_L­INT_SP K_R+
INT_SP K_R-

B B

40 mils trace keep 20 mi l spaci ng

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

12

12

12

CA19@EMC@

CA22@EMC@

CA23@EMC@

Close to UA1

LA6 BLM15PX330SN1D_2PEMC@
LA7 BLM15PX330SN1D_2PEMC@
LA8 BLM15PX330SN1D_2PEMC@
LA9 BLM15PX330SN1D_2PEMC@

1000P_0402_50V7K

12

1 2
1 2
1 2
1 2

CA24@EMC@

INT_SP KR_L+
INT_SP KR_L­INT_SP KR_R+
INT_SP KR_R-

L03ESDL5V0CC3-2_SOT23-3

2

2

3

3

@EMC@

DA6

1

1

Close t o UA1 pin6

HDA_BIT_CLK_R

33_0402_5%

12

RA17@EMC@

10P_0402_50V8J

12

CA33@EMC@

Verb t able conf i g ures as 1 J D mod e wi t h
internal 47K pull high to save external rBOM.

13

D

2

0.1U_0402_25V6

G

QA1

100K_0402_5%

12

6

1

L2N7002WT1G_SC-70-3

RA28

S

RA38 100K_0402_5%

200K_0402_5%

12

RA27

34

5

QA3B

DMN65D8LDW-7_SOT363-6

12

CA41

1 2

100K_0402_5%

12

RA26

@

12

QA3A

AUD_SENSE_A

100K_0402_5%

RA29

AUD_SENSE_B

2

Place clo sely to Pin 13.

Place clo sely to Pin 14 for DOCK only

A A

DMN65D8LDW-7_SOT363-6

Power sequ ence +5V_RUN _AUDIO(5 01us) > + 3.3V_RU N_AUDIO(1204 us) > +1.5V_RUN

Reserve for support D3 cold

+5V_RUN

AUD_PWR_EN<9>

+5V_ALW

+3.3V_RUN

UZ5

@

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2
VIN27VOUT2

EM5209VF_SON14_2X3

VOUT1
VOUT1

VOUT2

GPAD

GND

14
13

12

CT1

11

10

CT2

9
8

15

+5V_RUN_AUDIO_UZ5

+3.3V_RUN_AUDIO_UZ5

ACES_50271-0040N-001

6

GND2

5

GND1

4

4

3

3

2

2

1

L03ESDL5V0CC3-2_SOT23-3

@EMC@

DA7

+3.3V_RUN_AUDIO

AUD_HP_NB_SENSE <31>

DOCK_MIC_DET <31>DOCK_HP_DET<31>

+5V_RUN_AUDIO

1

JSPK1

CONN@

Link 50 271-0040N-001 DONE

BCLK: Audio serial data bus bit clock input/output
LRCK: Audio serial data bus word clock input/output

AUD_NB_MUTE#<31>

1 2

RA18 10K_0402_5%

Add for solve
pop noise and
detect issue

+3.3V_RUN_AUDIO

+5V_RUN

12

PJP31@

+3.3V_RUN +3.3V_RUN_AUDIO

PAD-OPEN1x1m

1 2

@

CZ89 0.1U_0201_10V6K

1 2

220P_0402_50V7K

CZ90

@

1 2

1000P_0402_50V7K

CZ91

@

PJP30@

1 2

PAD-OPEN1x1m

1 2

@

CZ92 0.1U_0201_10V6K

2

+3.3V_RUN_AUDIO

HDA_BIT_CLK_R<12>

HDA_SDOUT_R<12>

HDA_SYNC_R<12>

HDA_SDIN0<12>

HDA_RST#_R<12>

DAI_12MHZ#<38>

DAI_BCLK#<38>

DAI_DO#<38>

DAI_LRCK#<38>

DAI_DI<38>

PJP9

1 2

PAD-OPEN1x1m

PJP10

1 2

PAD-OPEN1x1m

+3.3V_RUN_AUDIO

CA11 close to pin9
CA10 close to pin3

4.7U_0603_6.3V6K

12

AUD_NB_MUTE#

place at AGND and DGND plane

RA35 0_0402_5%

@

RA36 0_0402_5%

@

RA37 0_0402_5%

@

0.1U_0201_10V6K

0.1U_0201_10V6K

CA10

CA11

1

1

2

2

Place R A9 close to codec

1 2

RA9 33_0402_5%

1 2

RA30EMC@ 22_0402_5%

1 2

RA31EMC@ 22_0402_5%

1 2

RA32 33_0402_5%

1U_0603_10V6K

12

CA31

1 2

1 2

1 2

+5V_RUN_AUDIO

CA50

2.5A

500mA

EN_I2S_NB_CODEC#<31>

HDA_BIT_CLK_R

HDA_SDOUT_R

HDA_SDIN0_R

HDA_RST#_R

I2S_MCLK

I2S_BCLK

I2S_DO

Place RA32 c lose to codec

100K_0402_5%

12

RA44

8/4

CA52

4.7U_0603_6.3V6K

CA51

4.7U_0603_6.3V6K

12

12

1 2

PAD-OPEN1x2m

SLEEVE

34

5

QA2B

DMN65D8LDW-7_SOT363-6

Realtek feedback
Prevent the Noise from Combo Jack
while system entry into S3 / S4 /S5

MIC1_L

MIC1_R

4.7U_0603_6.3V6K

12

PJP6

+RTC_CELL

100K_0402_5%

12

6

1

QA2A

DMN65D8LDW-7_SOT363-6

CA53

RA21

2

UA1

1

I2S I/F Float

3

DVDD_IO

9

DVDD

6

BCLK

5

SDATA-OUT

10

SYNC

8

SDATA-IN

11

RESET#

15

I2S_MCLK

16

I2S_SCLK

17

I2S_DOU T

18

I2S_LRC K

24

I2S_DIN

19

MIC1-L( PORT -B-L)

20

MIC1-R( PORT -B-R)

48

EAPD+PD

21

LDO1-CAP

39

LDO2-CAP

7

LDO3-CAP

49

GND

ALC3235-CG_MQFN48_6 X6

RING2
AUD_HP_OUT_L

AUD_HP_OUT_R
SLEEVE

AUD_NB_MUTE#

AVDD1
AVDD2

CPVDD

PVDD1
PVDD2

HP/MIC1 JD(JD1)
I2S_IN/I2 S_OUT JD(JD 2)
TV Mode/LINE1-JD (JD3)

LINE1-L(PORT-C-L)/RING2

LINE1-R(PORT-C-R)/SLEEVE

LINE1-VREFO

MIC-CAP

HPOUT-L(PORT-A-L)

HPOUT-R(PORT-A-R)

SPK-OUT-L+

SPK-OUT-L-

SPK-OUT-R+

SPK-OUT-R-

PCBEEP

GPIO0/DMIC-CLK

GPIO1/DMIC-DATA12

SPDIF-OUT/DMIC-DAT A34/GPIO2

CBN

CBP

CPVEE

VREF

MIC1-VR EFO

AVSS1
AVSS2

CA43

MIC1_L

1 2

CA44

MIC1_R

1 2

LA10 BLM15PX330SN1D_2PEMC@

1 2

LA2 BLM15BD601SN1D_2PEMC@

1 2

LA3 BLM15BD601SN1D_2PEMC@

1 2

LA11 BLM15PX330SN1D_2PEMC@

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT M AY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4.7U_0603_6.3V6K

1 2

4.7U_0603_6.3V6K

place close to pin27

+VDDA_AVDD1

0.1U_0201_10V6K

CA8

1

2

27
40

+VDDA_PVDD

38
41

+5V_RUN_PVDD

46

AUD_SENSE_A

13

AUD_SENSE_B

14

1 2

22

RA45 0_0402_5%

@

28

RING2

29

SLEEVE

23

31
33
32

42
43

45
44

12

2
4

47

35

36

34
25

30
26
37

1 2

CA25 10U_0603_10V6M

AUD_OUT_L
AUD_OUT_R

RA7 24.9_0402_1%
RA8 24.9_0402_1%

INT_SP K_L+
INT_SP K_L-

INT_SP K_R+
INT_SP K_R-

AUD_PC_BEEP

DMIC_CLK_CODEC

Place CA29 close to Codec

12

CA29 1U_0603_10V6K

12
12

CA49 1U_0603_10V6K
CA35 2.2U_0402_6.3V6M

+MIC1_VREF_OUT

RING2_R
AUD_HP_OUT_L1

AUD_HP_OUT_R1
SLEEVE_R

EMC@

680P_0402_50V7K

1

CA1

2

1 2

10U_0603_10V6M

BLM15PX600SN1D_2P

12

CA9

place close to pin40

+3.3V_RUN_AUDIO

SLEEVE/RING2 please keep 40 mils trace width

1 2
1 2

12

CA27 0.1U_0402_25V6

12

CA28 0.1U_0402_25V6

1 2

RA14EMC@ 33_0402_5%

RB751S40T1G_SOD523-2

21

21

DA4

4.7K_0402_5%

4.7K_0402_5%

RA25

RA24

1 2

1 2

AUD_HP_OUT_L

AUD_HP_OUT_R

@EMC@

@EMC@

220P_0402_50V7K

220P_0402_50V7K

1

1

2

1

CA3

CA2

2

2

DMIC_CLK0

RB751S40T1G_SOD523-2

+3.3V_RUN_AUDIO+3.3V_RUN_AUDIO +3.3V_RUN_AUDIO

680P_0402_50V7K

+5V_RUN_AUDIO +1.5V_RUN

LA5

+1.5V_RUN_AUDIO

4.7U_0603_6.3V6K

place close to pin38

1

CA16

2

+VREFOUT

AUD_HP_OUT_L
AUD_HP_OUT_R

AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width

DMIC0 <26>

DA5

12

RA1
10K_0402_5%

EMC@

3

CA4

1

0.1U_0201_10V6K

1

2

1 2

RA12 1K_0402_5%

1 2

RA13 1K_0402_5%

DMIC_CLK0 <26>

EMC@

2

2

3

DA1

AZ5123-02S.R7G_SOT 23-3

1

CA17

1

2

680P_0402_50V7K

1

2

AUD_HP_NB_SENSE

EMC@

DA2

L03ESDL5V0CC3-2_SOT23-3

4.7U_0603_6.3V6K

CA18

@EMC@

CA13

3

DELL CONFIDENTIAL/PROPRIETARY

Titl e

Titl e

Titl e

Size

Size

Size

Date: Sheet of

Date: Sheet of

1

Date: Sheet of

12

SPKR <12>

BEEP <32>

HP-Out-Lef t

EMC@

2

DA3

AZ5123-02S.R7G_SOT 23-3

1

Document Number Rev

Document Number Rev

Document Number Rev

+3.3V_RUN_AUDIO

1

2

DMIC_CLK0

12

0_0603_5%

RA4@

0.1U_0201_10V6K

CA45

0.1U_0201_10V6K

10U_0603_10V6M

CA47

1

1

CA46

2

2

1 2

RING2

1 2

SLEEVE

+VREFOUT

22P_0402_50V8J

12

@EMC@

CA54

0_0603_5%

RA3@

place close to pin41 place close to pin46

place close to UA1 pin2

HP-Out-Right

Nokia-MIC

Global Headset

Universal Jack

JHP1

7

GND

4

#4 G/M

1

#1 L/R

5

#5

6

#6 AGND

2

#2 R/L

3

#3 M/G

SINGA_2SJ3095-022111F

RA2 100K_0402_5%

680P_0402_50V7K

@EMC@

12

Link 2SJ3 095-022111F DO NE

1

CA12

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Codec ALC3235

Codec ALC3235

Codec ALC3235

LA-C461P

LA-C461P

LA-C461P

+5V_RUN_AUDIO

0_0805_5%

12

RA39@

10U_0603_10V6M

1

CA48

2

1U_0603_10V6K

12

iPhone-MIC

30 61Tuesday, October 13, 2015

30 61Tuesday, October 13, 2015

30 61Tuesday, October 13, 2015

+VREFOUT

RA52. 2K_0402_5%

RA62. 2K_0402_5%

@

CA26

Normal
Open

1.0

1.0

1.0

5

4

3

2

1

+3.3V_ALW

RPE9

USB_PWR_S HR_VBUS_EN

1

8
7
6

100K_0804_8P4R_5%

D D

C C

B B

1 2

RE5 100K_0402_5%

1 2

RE10 100K _0402_5%

1 2

RE8 100K_0402_5%

1 2

RE9 100K_0402_5%

8
7
6

100K_0804_8P4R_5%

1 2

RE11 100K _0402_5%

1 2

RE12 100K _0402_5%

+3.3V_RUN

RC281 10K_0402_5%

1 2

RE21 10K_ 0402_5%

1 2

RE20 100K _0402_5%

Discrete

UMA

RPE11

1 2

VGA_ID

VGA_ID

@

CPU_ID

CPU_ID

USB_PWR_E N1#

2

USB_PWR_E N2#

3
45

SLICE_BAT_PRES#

WWAN_RADIO_DIS#

WLAN_WIGIG60GHZ_DIS#

DOCK_SMB_ALERT#

SLOT2_CONFIG_0

1

SLOT2_CONFIG_1

2

SLOT2_CONFIG_2

3

SLOT2_CONFIG_3

45

BT_RADIO_DIS#

HW_GPS_DI SABLE#

USH_DET#

SYS_LED_MASK#

LCD_TST

1 2

RE84100K _0402_5%

1 2

RE85100K _0402_5%

VGA_ID0

0

1

+3.3V_ALW

1 2

RE298100K_0402_5%@

1 2

RE299100K_0402_5%

USB_PWR_S HR_EN# <31,36>

+3.3V_ALW

Reserve
Reserve

WLAN_WIGIG60GHZ_DIS#<29>

Reserve

USB_PWR_S HR_VBUS_EN<36>

EN_I2S_NB_CODEC#<30>

EN_DOCK_PWR_BAR<51>

HW_GPS_DI SABLE#<29>

AUD_HP_NB_SENSE<30>

WWAN_RADIO_DIS#<29>

DOCK_SMB_ALERT#<38,42>

USH_PWR_ST ATE#<33>

LCD_VCC_TEST_EN<26>

SLICE_BAT_PRES#<38,42,51>

LAN_DISABLE#_R<27>

USB_PWR_E N2#<37>

PANEL_BKEN_EC<26>

PSID_DISABLE#<42>

AUD_NB_MUTE#<30>

3.3V_WW AN_EN<41>

WWAN_WAKE#<29>

USB_PWR_E N1#<37>

SLICE_BAT_ON<51>

T97@ PAD~D
T99@ PAD~D

T98@ PAD~D

BCM5882_ALERT#<33>

SYS_LED_MASK#<27,40>

BT_RADIO_DIS#<29>

SIO_SLP_WLAN#<11,41>

AC_DIS<42,50,51>

LCD_TST<26>

DOCKED<27>

DOCK_DET#<38,51>

USH_DET#<33>

EC5048_TX<32>

LID_CL_SIO#
DOCK_SMB_ALERT#

USB_PWR_E N2#

HW_GPS_DI SABLE#

LCD_TST

WWAN_WAKE#

USB_PWR_E N1#

SLICE_BAT_ON
SLICE_BAT_PRES#

GPIOD4
GPIOD5

WLAN_WIGIG60GHZ_DIS#

GPIOE2

VGA_ID

SYS_LED_MASK#

USB_PWR_S HR_VBUS_EN

BT_RADIO_DIS#
WWAN_RADIO_DIS#

CPU_ID0

U CPU

H_CPU

0

1

+3.3V_ALW +3.3V_ALW_UE1

B52
A49
B53
A50
B54
A51
B55
A52

A33
B36
A34
B37
A35
B38
A36
A37
B40
A38
B41
A39
B42
A40
B43
A41
B44

B32
A31
B33
B15
A15
B16
A16

A1
B2
A2
B3

A3
B45
A42

B4

A59
B62
A58
B61
A56
B59
A55
B58

B47
A45
B48
A46
B49
A47
B50
A48

B13
A13
A53
B57
B14
A14
B17
B18

10U_0603_10V6M

12

CE1

UE1

GPIOA0
GPIOA1
GPIOA2
GPIOA3
GPIOA4
GPIOA5
GPIOA6
GPIOA7

GPIOB0
GPIOB1
GPOC2
GPOC3
GPOC4
GPOC5
GPOC6/TACH4
GPIOC7
GPIOD0
GPIOC1
GPIOC0
GPIOB7
GPIOB6
GPIOB5
GPIOB4
GPIOB3
GPIOB2

GPIOD1
GPIOD2
GPIOD3
GPIOD4
GPIOD5
GPIOD6
GPIOD7

GPIOE0/RXD
GPIOE1/TXD
GPIOE2/RTS#
GPIOE3/DSR#
GPIOE4/CTS#
GPIOE5/DTR#
GPIOE6/RI#
GPIOE7/DCD#

GPIOF0
GPIOF1
GPIOF2
GPIOF3/TACH8
GPIOF4/TACH7
GPIOF5
GPIOF6
GPIOF7

GPIOG0/TACH5
GPIOG1
GPIOG2
GPIOG3
GPIOG4
GPIOG5
GPIOG6
GPIOG7/TACH6

GPIOH0
GPIOH1
SYSOPT1/GPIOH2
SYSOPT0/GPIOH3
GPIOH4
GPIOH5
GPIOH6
GPIOH7

PJP14

1 2

PAD-OPEN1x1m

B5

A17

B30

A43

A54

VCC1

VCC1

VCC1

VCC1

VCC1

ECE5048-LZY_DQFN132_11X11~D

0.1U_0201_10V6K

CE2

1

1

2

2

GPIOI0
GPIOI1

GPIOI2/TACH0

GPIOI3
GPIOI4
GPIOI5
GPIOI6
GPIOI7

GPIOJ0
GPIOJ1/TACH1
GPIOJ2/TACH2

GPIOJ3

GPIOJ4

GPIOJ5

GPIOJ6

GPIOJ7

GPIOK0

GPIOK1/TACH3

GPIOK2
GPIOK3
GPIOK4
GPIOK5
GPIOK6
GPIOK7

GPIOL0/PWM7
GPIOL1/PWM8
GPIOL2/PWM0
GPIOL3/PWM1
GPIOL4/PWM3
GPIOL5/PWM2

GPIOL6

GPIOL7/PWM5

GPIOM1
GPIOM3/PWM4
GPIOM4/PWM6

LAD0
LAD1
LAD2

LAD3
LFRAME#
LRESET#

PCICLK

CLKRUN#

LDRQ1#

SER_IRQ

14.318MHZ/GPIOM0
CLK32/GPIOM2

DLAD0
DLAD1
DLAD2

DLAD3
DLFRAME#
DCLKRUN#

DLDRQ1#

DSER_IRQ

BC_INT#

BC_DAT
BC_CLK

PWRGD

OUT65

TEST_PIN

CAP_LDO

DB Version 0.4

12

RE3510K_0402_5%

12

RE3810K_0402_5%

8
7
6

1 2

12

12

+3.3V_ALW

+3.3V_RUN

PCIE_WAKE# <29,35>

PCH_PCIE_WAKE# <11,32>

RE2740_0402_5% @

LID_CL# <40>

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

CE3

CE4

1

2

A23
B63
A60
A61
B65
A62
B66
A63

B67
A64
A5
B6
A6
B7
A7
B8

A8
B9

PCIE_WAKE#_R

B10
A10
B11
A11
B12
A12

B60
A57
B64
B68
A9
B1
A18
A44

B34
B39
B51

A27
A26
B26
B25
A21
B22

CLK_PCI_5048

A28
B20

CLKRUN#

LPC_LDRQ1#

A22
B21
A32
B35

B29
B28
A25
A24
B23

D_CLKRUN#

A19

D_DLDRQ1#

B24

D_SERIRQ

A20

A29
B31
A30

A4

RUNPWROK

B56

B19

RE24 10K_0402_5%

+CAP_LDO

B46

B27

VSS

C1

EP

CE5

1

1

2

2

SLOT2_CONFIG_0

CPU_ID

SLOT2_CONFIG_1
SLOT2_CONFIG_2

SLOT2_CONFIG_3

1 2

4.7U_0603_6.3V6K

12

0.1U_0201_10V6K

CE6

USH_RST# <33>

DOCK_AC_OFF_EC <51>

AUX_EN_WOWL <41>

ME_FW P_EC <12>

GPIO_PSID_SELECT <42>

DOCK_HP_DET <30>
DOCK_MIC_DET <30>

USB_PWR_S HR_EN# <31, 36>
MASK_SA TA_LED# <4 0>

LED_SATA_DIAG_OUT# <40>

SLOT2_CONFIG_0 <29>

WLAN_DISBL# <27>

SLOT2_CONFIG_1 <29>
SLOT2_CONFIG_2 <29>

SLOT2_CONFIG_3 <29>

DIS_BAT_PROCHOT# <51>

LPC_AD0 <8,32>
LPC_AD1 <8,32>
LPC_AD2 <8,32>
LPC_AD3 <8,32>
LPC_FRAME# <8,32>
PLTRST_5048# <11>
CLK_PCI_5048 <8>
CLKRUN# <8,32>

IRQ_SERIRQ <8,32>

EC_32KHZ_ECE5048 <32>

D_LAD0 <38>
D_LAD1 <38>
D_LAD2 <38>
D_LAD3 <38>
D_LFRAME# <38>
D_CLKRUN# < 38>
D_DLDRQ1# <38>
D_SERIRQ <38>

BC_INT#_ECE5048 <32>
BC_DAT_ECE5048 <32>
BC_CLK_ECE5048 <32>

RUNPWROK <14,3 2>

CE7

+CAP_LDO trace width 20 mils

CLK_PCI_5048

33_0402_5%

12

RE27@EMC@

33P_0402_50V8J

12

PCIE_WAKE#_R

WWAN_WAKE#

LPC_LDRQ1#
D_DLDRQ1#
D_SERIRQ
D_CLKRUN#

PCIE_WAKE#_R

RE275 0_0402 _5%@

Stuff RE275 and no stuff RE274 keep E5 design
Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)

CE9@EMC@

LID_CL_SIO#

12

SLICE_BAT_ON

+3.3V_ALW

100K_0402_5%

12

12

RPE8

1
2
3
4 5

100K_0804_8P4R_5%

RE17 100K_0402_5%

RE25

RE26 10_0402_5%

.047U_0402_16V7K

CE8

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Titl e

Titl e

PROPRIETARY NOTE: THIS SHEET OF E NGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

TRADE SECRET AND OTHER PROPRI ETARY INF ORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHOR IZATION OF DEL L. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR D ISCLO SED TO ANY TH IRD
PART Y W IT HO UT D EL L' S E XP RE SS WR IT TEN C ON SE NT.

5

4

3

2

Titl e

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

ECE5048

ECE5048

ECE5048

LA-C461P

LA-C461P

LA-C461P

1

31 61Tuesday, October 13, 2015

31 61Tuesday, October 13, 2015

31 61Tuesday, October 13, 2015

1.0

1.0

1.0

BC_DAT_ECE5048

FAN1_PWM

FAN1_TACH

EN_INVPWR

RESET_OUT#

CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE

MSDATA

DOCK_POR_RST#

RUN_ON
CV2_ON
A_ON
PCH_ALW_ON

+3.3V_ALW

1U_0402_6.3V6K

12

CE30

+3.3V_ALW

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

+3.3V_RUN

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

100K_0402_5%

12

RE63

100_0402_1%

12

RE65@

49.9_0402_1%

12

RE71

MSCLK
MSDATA

HOST_DE BUG_TX
EC5048_TX_R

PCH_PLTRST#_EC

5

JTAG_RST#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

5

10K_8P4R_5%

678

RPE7

123

4 5

Pin8 5085_TXD for EC Debug
pin9 5048_TXD for SBIOS
debug

CLK_PCI_LPDEBUG <8>

JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO

+3.3V_ALW

12

10K_0402_5%

RE72

32 KHz Clock

MEC_XTAL1

33P_0402_50V8J

32.768KHZ_12.5PF_Q13FC135000040

12

CE28

10K_0402_5%

10K_0402_5%

100K_0402_5%

12

12

12

RE73

RE74

RE75@

RE305 0_0402_5%

@

RE306 0_0402_5%

@

+3.3V_ALW +3 .3V_ALW_UE2

12

MEC_XTAL2_R

MEC_XTAL2

1 2

YE1

12

EC5048_TX <31>

12

UART0_TX D <9 >

1 2

10U_0603_10V6M

CE21

12

@

0_0402_5%

8/28 s chematic review

33P_0402_50V8J

12

PAD-OPEN1x1m

RE290

CE29

+3.3V_ALW

1 2

RE36 1 00K_0402_5%

D D

+3.3V_RUN

1 2

RE48 10K_0402_5%

1 2

RE51 10K_0402_5%

1 2

RE55 100K_0402_5%

1 2

RE56 10K_0402_ 5%

+5V_RUN

RPE2

1

8

2

7

3

6

4 5

4.7K_8P4R_5%

1 2

RE86 10K_040 2_5%

1 2

RE277 100 K_0402_5%

RPE10

1

8

2

7

3456

100K_0804_8P4R_5%

C C

B B

A A

@SHORT PADS~D

JTAG1 @

1

1

2

2

11
12

ACES_50521-01041-P01

11
12

HB_A53 1015 -SCHR2 1

G1
G2

G1
G2

CONN@

JDEG1

CONN@

JLPDE1

4

+RTC_CELL

1 2

RE32@ 0_0402_5%

+3.3V_ALW_UE2

+3.3V_ALW_UE2

PJP15

0.1U_0201_10V6K

0.1U_0201_10V6K

@

CE17

CE16

1

1

1

2

2

2

trace width 20 mils
trace width 20 mils

CLK_PCI_MEC

@EMC@

10_0402_5%

12

RE66

@EMC@

4.7P_0402_50V8C

12

CE34

Place close pin A29

RE79 CE40

4700p240K
4700p130K
4700p

33K

4700p

4.3K
4700p

2K

62K 4700p X06

4700p

*

0.1U_0201_10V6K

0.1U_0201_10V6K

CE18

CE22

1

2

EMI depop location

REV

X00
X01
X02
X03
X04
X054700p8.2K

A001K

0.1U_0201_10V6K

1

2

SML1_SMBDATA<8>

DOCK_POR_RST#<38>

BC_CLK_ECE5048<31>
BC_DAT_ECE5048<31>
BC_INT#_ECE5048<31>

BC_CLK_ECE1117<39>
BC_DAT_ECE1117<39>
BC_INT#_ECE1117<39>

BOARD_ID rise t i me i s measured fr o m 5 %~68 %.

4

3

+RTC_CELL_VBAT

0.1U_0201_10V6K

CE11

1

2

1U_0402_6.3V6K

0.1U_0201_10V6K

CE13

1

12

CE14

2

0.1U_0201_10V6K
1U_0402_6.3V6K

CE20

1

12

CE15

2

0.1U_0201_10V6K

CE19

CE23

1

2

SML1_SMBCLK<8 >

CLK_TP_SIO<39>
DAT_TP_SIO<39>

PBAT_SMBDAT<42>
PBAT_SMBCLK<42>

BIA_PWM_EC<26>

ACAV_IN_NB<50,51>
SIO_SLP_S5#<11>

SIO_EXT_SMI#<12>

IRQ_SERIRQ<8,31>
PCH_PLTRST#_EC<11>
CLK_PCI_MEC<8>

LPC_FRAME#<8,31>

SIO_EXT_SCI#<9>

CLK_KBD
DAT_KBD

CLK_KBD<38>
DAT_KBD<38>

CLK_MSE

CLK_MSE<38>

DAT_MSE

DAT_MSE<38>

PBAT_SMBDAT
PBAT_SMBCLK

JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#

FAN1_TACH
DOCK_POR_RST#

PS_ID<42>

FAN1_PWM

BEEP<3 0>

SIO_RCIN#<8>

CLK_PCI_MEC
LPC_FRAME#
LPC_AD0

LPC_AD0<8,31>

LPC_AD1

LPC_AD1<8,31>

LPC_AD2

LPC_AD2<8,31>

LPC_AD3
LPC_AD3<8,31>
CLKRUN#<8,31>

MEC_XTAL1

MEC_XTAL2_R

UE2

B64

VBAT

A22

H_VTR

A58

VTR_ADC

B3

VTR

A11

VTR

A26

VTR

B35

VTR

A41

VTR

A52

VTR

A5

GPIO007/I2C1D_ DATA/PS2_CLK0B/I2C 3A_DATA

B6

GPIO010/I2C1D_ CLK/PS2_DAT0B/I2 C3A_CLK/GANG_DATA0

A37

GPIO110/PS2_CLK2/GPTP-IN6

B40

GPIO111/PS2_DAT2/GPTP-OUT6

A38

GPIO112/PS2_CL K1A

B41

GPIO113/PS2_DAT1A

A39

GPIO114/PS2_CL K0A

B42

GPIO115/PS2_DAT0A

B59

GPIO154/I2C1C_ DATA/PS2_CLK1B/GANG_DATA5

A56

GPIO155/I2C1C_ CLK/PS2_DAT1B/GANG_DATA6

A51

GPIO145/I2C1K _DATA/JTAG_TDI

B55

GPIO146/I2C1K _CLK/JTAG_TDO

B56

GPIO147/I2C1J _DATA/I2C2C_DATA/JTAG_CLK

A53

GPIO150/I2C1J _CLK/I2C2C_ CLK/JTAG_TMS

B47

JTAG_RST#

B22

GPIO050/FAN_TACH1/GTACH0/GANG_START

A21

GPIO051/FAN_TACH2/GANG _MODE

B23

GPIO052/FAN_TACH3/GTACH1/GANG_ERROR

B24

GPIO053/PWM0

A23

GPIO054/PWM1 /GPWM1

B25

GPIO055/PWM2

A24

GPIO056/PWM3 /GPWM0

A43

GPIO123/BCM_A_CLK

B45

GPIO122/BCM_A_DAT

A42

GPIO121/BCM_A_INT#

B20

GPIO032/BCM_E_C LK

A18

GPIO031/GPTP-OUT2/BCM_E_DAT

B19

GPIO030/GPTP-IN2/BCM_E_INT#/GANG_DATA7

A20

GPIO047/LSBCM_D _CLK

B21

GPIO046/LSBCM_D _DAT/GANG_STROBE

A19

GPIO045/LSBCM_D _INT#

A6

GPIO011/nSMI

A27

GPIO061/LPCPD#

A28

SER_IRQ

B30

LRESET#

A29

PCI_CLK

B31

LFRAME#

A30

LAD0

B32

LAD1

A31

LAD2

B33

LAD3

A32

CLKRUN#

A33

GPIO100/NEC_SCI

A61

XTAL1

A62

XTAL2

POWER_SW_IN#

15mil

AGND

B66

+RTC_CELL

100K_0402_5%

12

RE31

RE33 10K_0402_5%

1U_0402_6.3V6K

12

CE12

VSS

VSS_ADC

B11

B60

+VR_CAP

CE10@

1 2

1U_0402_6.3V6K

1 2

GPIO120/UART_TX/V2P_COUT_HI1

GPIO124/GPTP-OUT5/UART_RX/V2P_COUT_LO1

GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_ STRAP

GPIO117/MSCLK/V2P _COUT_HI

GPIO001/ECSPI_ CS1/32KHZ_OUT

GPIO125/GPTP-IN5/PECI_REQUEST#/GANG_BUSY

GPIO151/GPTP-IN4/GANG_DATA2

GPIO005/I2C1B _DATA/BCM_B_DAT

GPIO006/I2C1B _CLK/BCM_B_CLK

GPIO012/I2C1H_DATA/I2C2 D_DATA

GPIO013/I2C1H_CL K/I2C2D_CLK/ GANG_DATA3

GPIO130/I2C2A_DATA/BCM_C_ DAT

GPIO131/I2C2A_CL K/BCM_C_CLK

GPIO141/I2C1F _DATA/I2C2B_DATA

GPIO142/I2C1F _CLK/I2C2B_ CLK

VR_CAP

B12

4.7U_0603_6.3V6K

12

CE31

PROCHOT_IN#/PROCHOT_IO#

VSS_RO

H_VSS

EP

C1

B54

B18

POWER_SW#_MB <11,40>

GPIO021/RC_ID1
GPIO020/RC_ID2

GPIO014/GPTP-IN7/RC_ID3

GPIO025/UART_CLK

VCC_PW RGD

GPIO060/KBRST/BCM_ B_INT#

GPIO101/ECGP_SCL K

GPIO103/ECGP_MIS O
GPIO105/ECGP_MOSI

GPIO102/BCM_C_I NT#

GPIO104/SLP_S 0#

GPIO106

GPIO127/A20M

GPIO156/LED1/ GANG_DATA1

GPIO157/LED0

GPIO153/LED2/ GANG_DATA4

GPIO027/GPTP-OUT1

GPIO026/GPTP-IN1

GPIO015/GPTP-OUT7

GPIO016/GPTP-IN8

GPIO017/GPTP-OUT8

GPIO107/NRESET_OUT

GPIO152/GPTP-OUT4

GPIO003/I2C1A_DATA

GPIO004/I2C1A_CL K

GPIO132/I2C1G_ DATA

GPIO140/I2C1G_ CLK

GPIO143/I2C1E _DATA

GPIO144/I2C1E _CLK

SYSPWR_PRES

VCI_OVRD _IN

VCI_OUT
VCI_IN0 #
VCI_IN1 #
VCI_IN2 #
VCI_IN3 #

VREF_PE CI

PECI_DAT

DN1_DP1A/THERM

DP1_DN1A/VREF_T

DN2_DP2A
DP2_DN2A
DN3_DP3A
DP3_DN3A
DN4_DP4A
DP4_DN4A

THERMTRIP2#

GPIO002/THERMTRIP3#

GPIO024/THSEL_STRAP

V_ISYS0
V_ISYS1

MEC5085-LZY_DQFN132_11X11

A10
B10
B8
B27
B44
B46
B26
A25
B36
B37
B38
A34
A35
A36
A40
B43
A45
B65

nFWP

B57
B1
A55
A1
B28
B2
A8
B9
A9
B39
A44

A54
B58

A3
B4
A4
B5
B7
A7
B48
B49
A47
B50
B52
A49
B53
A50

A59

B62

BGP0

A64
A60
B67
A63
B63
B68

B51
A48

B13
A13
B14
A14
A15
B16
A16
B17
B15

VIN

A17

VSET

A12

VCP

B34
A2
B29
A46
B61

RE64 4.7K_0402_5%

A57

REM_DIODE1_N
REM_DIODE1_P
REM_DIODE2_N
REM_DIODE2_P

REM_DIODE4_N
REM_DIODE4_P

H_PROCHO T#_R 1

ESR <2ohms

+3.3V_RUN

10K_0402_5%

12

BOARD_ID

+3.3V_ALW

12

12

1K_0402_5%

RE79

4700P_0402_25V7K

CE40

+3.3V_ALW

100K_0402_5%

12

RE68

RUN_ON#

DMN65D8LDW-7_SOT363-6

6

QE2A

PANEL_ID

2

1

+3.3V_ALW

130K_0402_5%

12

RE300

4700P_0402_25V7K

12

CE47

PAN EL _I D r i se t i me i s meas ur e d fr o m 5 %~68 %.

3

RUN_ON<3 2,41,46,53 >

+3.3V_ALW

10K_0402_5%

12

RE81

FWP#

10K_0402_5%

RE82@

1 2

*

RUNPWROK

RE300 CE47

33K

RE67

DMN65D8LDW-7_SOT363-6

34

QE2B

5

PANE L S IZE

12"

4700p240K

14"

4700p130K
4700p

15"
17"

4700p4.3K

DOCK_PWR_SW#

PANEL_ID
BOARD_ID
mCARD_ PCI E#_ SATA

HOST_DE BUG_TX

RUNPWROK
EN_INVPWR

PCH_ALW_ON
SIO_SLP_S3#

MSDATA
MSCLK

PCH_RSMRST#

FWP#

IMVP_VR_ON_EC

RUN_ON_EC
CV2_ON
RESET_OUT#
VCCST_PW RGD_ EC

SIO_PWRBTN#

DOCK_SMB_DAT
DOCK_SMB_CLK
A_ON

GPU_SMBDAT
GPU_SMBCLK
CHARGER_SMBDAT
CHARGER_SMBCLK
SIO_SLP_SUS#_R

POWER_SW_IN#
DOCK_PWR_SW#
VCI_IN2 #
POA_WAKE#

+PECI_VREF
PECI_EC_R

VSET_50 85

THERMATRIP2#
THERMATRIP3#

THSEL_STRAP

1 2

I_SYS_R

10K_0402_5%

12

RE313@

+RTC_CELL

12

12

Reserv e
Reserv e

Reserv e

1 2

RE60 43_0402_5%

1 2

CE24 2200P_0 402_50V7K

1 2

CE26 2200P_0 402_50V7K

1 2

CE27 2200P_0 402_50V7K

CE24, CE26, CE27 Plac e near UE2

1 2

RE288 100_0402_5%

RE312 0_0402_5%

@

Thermal diode mapping

5085 Channel

DP1/DN1

DP2/DN2

DN2a/DP2a WiGig

DP4/DN4

Place under CPU
Place CE35 close to the QE3 as possible

100P_0402_50V8J

CE35@

1 2

DP2/DN2 for DIMM on QE5, place QE5 close
to DIMM and CE37 close to QE5

DN2a/DP2a for WiGig on QE7, place QE7 clo se
to WiGig and CE46 close to QE7

100P_0402_50V8J

12

CE46@

DP4/DN4 for Skin on QE 6, place QE6 close to Vcore VR choke.

100P_0402_50V8J

@

CE39

1 2

2

100K_0402_5%

RE62

1 2

RE42 10K_0402_5%

1U_0402_6.3V6K

CE45

LAN_WAKE# <11,27>

PCH_PCIE_WAKE# <11,31>
RUNPWROK <14,31>
EN_INVPWR <26>
SIO_SLP_S4# <11,17,44,54>
SIO_SLP_LAN# <11,41>

PCH_ALW_ON <41>
SIO_SLP_S3# <11,17,47>

PCH_DPWROK <11>

PCH_RSMRST# <39>

BREATH_LED# <38,40>
BAT1_LED# <40>
BAT2_LED# <40>

SIO_SLP_A# <8,11>
EC_32KHZ_ECE5048 <31>
ME_SUS_PWR_ ACK <11>

CV2_ON <33>

RESET_OUT# <11,14>

AC_PRES ENT <11>
SIO_PWRBTN# <11,14>

DOCK_SMB_DAT <38>
DOCK_SMB_CLK <38 >

A_ON < 41>
SIO_EXT_WAKE# <9>
SUSACK# <11>
ENVDD_PCH <6,26>

CHARGER_SMBDAT <50>

CHARGER_SMBCLK <50>

PBAT_PRES# <42,50,51>
USH_SMB DAT <33>

USH_SMB CLK <33 >

EC_FPM_EN <33>

ACAV_IN <5 0,51 >

ALWON <43>

POA_WAKE# <33>

I_ADP <50>

I_BATT <50>

12

T131 @PAD~D

12

RE3080_0402_5%

@

CE44@

1 2

1U_0402_6.3V6K

8/11

H_VCCST_ PWR GD <1 1,1 4>

Reserv e

1 2

RC76 43K_0402_1%

1 2

RE57 1K_0402_5%

100K_0402_5%

12

RE58

PECI_EC <12>

H_PROCHO T# <1 2,48 ,50 >

8/19 DG0.9, CRB1.0

I_SYS <48,50>

DOCK_PWR_BTN# <38>

IMVP_VR_ON_EC

SIO_SLP_S3#

TC7SH08F U_SSOP5 ~D

8/21 CRB1.0 change to 0603 1/10W
10/30 move to EC side

RE59 close to UE2 at least 250mils

RE59 0_0402_5%@

0.1U_0201_10V6K

CE25

12

12

RE3040_0402_5%

@

+3.3V_ALW

5

1

P

B

O

2

A

G

UE3

3

SIO_SLP_S3#

RUN_ON_EC

SIO_SLP_SUS# <8,11,17,18,41 ,45,46,47,53>

+3.3V_ALW2

1 2

+1.0VS_VCCIO

Locat i on

CPU

DIMM

V.R

2

B

QE3

MMBT3904WT1G_SC70-3~D

100P_0402_50V8J

B

2

2

B

QE6

MMBT3904WT1G_SC70-3~D

2

REM_DIODE1_P

REM_DIODE1_N

12

CE37@

REM_DIODE4_P

REM_DIODE4_N

C

2

B

E

QE5

3 1

MMBT3904WT1G_SC70-3~D

C

E

3 1

MMBT3904WT1G_SC70-3~D

E

31

C

QE7

C

E

3 1

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL ") THIS DO CUMENT MAY NOT

BE TRA NSFERRE D OR COPIE D WIT HOUT T HE E XPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY B E U SED BY O R DISCLOSE D TO ANY THI RD
PART Y WIT HO UT DE LL 'S E XP RE SS W R ITT E N CO NS EN T.

+1.0VS_VCCIO

L2N7002WT1G_SC-70-3

RE90 0_04 02_5%

@

REM_DIODE2_P

REM_DIODE2_N

SIO_SLP_S3#

2

G

1 3

D

S

QE11

1 2

0.1U_0402_25V6

12

CE38

Rest=1 .58K , Tp= 96 degr ee

IMVP_VR_ON

4

IMVP_VR_ON <48>

1 2

1 2

8/28 s chematic review

+3.3V_ALW

1

B

2

A

UE5

TC7SH08F U_SSOP5 ~D

Reserv e
Reserv e

Reserv e

Link 50271-0040N-001 DONE

JFAN1

GND1
GND2

ACES_5 0271- 0040 N-001

CONN@

1 2

RE70 2.2K_040 2_5%

H_THERMTR IP#<1 2,20,21>

VSET_50 85

1.58K_0402_1%

12

RE77

1

+3.3V_ALW

UE4

1

5

NC

VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

RE2800_0402_5%

@

RE2920_0402_5%

@

@

CE52

1 2

0.1U_0402_25V6

5

P

4

O

G

3

DOCK_SMB_DAT
DOCK_SMB_CLK
GPU_SMBDAT
GPU_SMBCLK

BC_DAT_ECE1117
POA_WAKE#
VCI_IN2 #

THERMATRIP3#

CHARGER_SMBDAT
CHARGER_SMBCLK
PBAT_SMBDAT
PBAT_SMBCLK

PCH_RSMRST#

1

FAN1_PWM

1

2

FAN1_TACH

2

3

3

4

4

5
6

12

reserve for DC fan

2

B

THSEL_STRAP

RE78 1K_0402_5%

Channel 1
Thermal Monitoring Interface Strap Opt i on

HIGH
LOW

DELL CONFIDENTIAL/PROPRIETARY

Titl e

Titl e

Titl e

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

H_VCCST_ PWR GD

4

Y

RUN_ON <32,41,46,53>

+3.3V_ALW

RPE3

1

8

2

7

3

6

4 5

2.2K_0804_8P4R_5%

+3.3V_ALW

RPE5

1

8
7
6

8
7
6

RE8810K_0402_5%

0.1U_0402_25V6

CE36

12

MEC5085

MEC5085

MEC5085

LA-C461P

LA-C461P

LA-C461P

+RTC_CELL

+3.3V_ALW

2
3
4 5

100K_0804_8P4R_5%

1 2

RE301 10K_0402_5%

RPE6

1
2
3
4 5

2.2K_0804_8P4R_5%

1 2

12/02:follow intel PDG 1.0

+5V_RUN

10U_0603_10V6M

RB751S40T1G_SOD523-2

@

CE32

DE1

2 1

+3.3V_ALW

8.2K_0402_5%

12

RE69

THERMATRIP2#

MMBT3904WT1G_SC70-3~D

C

QE4

E

3 1

1 2

Thermistor Readings
Diode Readings

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Document Number Rev

Document Number Rev

Document Number Rev

1

+3.3V_RUN

32 61Tuesday, October 13, 2 015

32 61Tuesday, October 13, 2 015

32 61Tuesday, October 13, 2 015

1.0

1.0

1.0

5

4

3

2

1

power rail opt i on: T P M po wer r ail must s a me as + 3. 3 V_S PI ( S PI R O M)

TPM_PIRQ#

33_0402_5%
33_0402_5%

TPM_PIRQ#<8>

33_0402_5%

PLTRST_TPM#<11>

+3.3V_M_TPM+3.3V_M

+3.3V_M_TPM+3.3V_ALW_PCH

7/18 vender suggest.

+3.3V_RUN

12

RZ90

@

10K_0402_5%

PCH_SPI_D1_2_R
PCH_SPI_D0_2_R

PCH_SPI_CLK_2_R
PCH_SPI_CS#2_R

10K_0402_5%

12

RZ62

PCH_SPI_CS#2_R

UZ12

29

GPIO0/SDA/XOR_ OUT

30

RZ110 10K_0402_5%@

1 2

100

3
6

24
21
18
15

19
20
17
27
13
28

4
5

1 2

RZ111

GPIO1/SCL
GPIO2/GPX
GPIO3/BADD

LAD0/MISO
LAD1/MOSI
LAD2/SPI_IRQ#
LAD3

LCKL/SCLK
LFRAME#/SCS#
LRESET#/SPI_RST#/SRESET#
SERIRQ
CLKRUN#/GPIO4/SINT#
LPCPD#

PP
TEST

NPCT650JA0YX_QFN32_5X5

1K

10K

TPM_LPM#

TPM_GPIO4

RZ113 100_0402_5%

RZ113

1K

TPM_GPIO4PCH_SPI_CS#2_R

+3.3V_M_TPM

3

G

2

1

POP

MMBT390 6

LP2301A

+3.3V_M_TPM

Reserved

S

LP2301ALT1G_SOT23-3

QZ9

D

TPM_LPM#

+3.3V_RUN

VSB

VDD
VDD
VDD

NC
NC
NC
NC
NC
NC
NC

GND
GND
GND
GND

PGND

12

10K_0402_5%

1 2

RZ88 0_0402_5%

@

1 2

RZ89 0_0402_5%

@

+3.3V_ALW

1

+UZ12_TPM

8
14
22

2
7
10
11
25
26
31

9
16
23
32
33
12

RZ111

+UZ12_TPM

10U_0603_10V6M

0.1U_0201_10V6K

1

CZ71

2

place CZ71,CZ72 as close as UZ12.1

1

CZ72

2

place CZ73 as close as UZ12.8
CZ74,CZ76 as close as UZ12.14
CZ75 as close as UZ12.22

+3.3V_M_TPM

0.1U_0201_10V6K

0.1U_0201_10V6K

1

1

CZ74

2

2

1

CZ73

0.1U_0201_10V6K

2

10U_0603_10V6M

1

CZ76

CZ75

2

place CZ73 as close as UZ12.8

PCH_PLTRST#_AND<11,28,29,35>

USH_RST#<31>

+PWR_SRC
+3.3V_ALW2

+5V_ALW2

+3.3V_ALW

1 2

RZ8 2.2K_0402_5%

@

1 2

RZ9 2.2K_0402_5%

@

1 2

RZ10 1M_0402_5%

1 2

RZ85 0_0402_5%

@

1 2

RZ84 0_0402_5%

@

1 2

RZ86 0_0402_5%

@

1 2

RZ114 0_0402_5%

@

1 2

RZ115 0_0402_5%

@

RZ87 0_0402_5%

USH_DET#<31>

@

RB751S40T1G_SOD523-2

POA_WAKE#<32>

USH_SMBCLK<32>
USH_SMBDAT<32>

BCM5882_ALERT#<31>

USH_PWR_STATE#<31>

CONTACTLESS_DET#<12>

1 2

DZ7

USH_SMBCLK

USH_SMBDAT

USH_PWR_STATE#

+PWR_SRC_R
+3.3V_ALW2_R

CV2_ON<32>

EC_FPM_EN<32>

USB20_N7<10>
USB20_P7<10>

+3.3V_ALW

+5V_ALW2_R

+5V_ALW
+3.3V_RUN

+5V_RUN

12

USH_RST#_R

USH_DET#_R

USH CONN

E-T_6705K-Y26N-00L

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

GND

28

GND

JUSH1

CONN@

Link 6705K-Y26N-00L DONE

PCH_PLTRST#_AND

.047U_0402_ 16V7K

EMC@

12

CZ68

For ESD solution

+5V_ALW

1

2

0.1U_0201_10V6K

@

CZ94

+3.3V_ALW2

0.1U_0201_10V6K

1

2

0.1U_0201_10V6K

1

@

CZ24

@

CZ10

2

Close to JUSH1

+3.3V_ALW+3.3V_RUN+5V_RUN

0.1U_0201_10V6K

1

2

0.1U_0201_10V6K

1

@

@

CZ11

CZ12

2

D D

+3.3V_M_TPM

SIO_SLP_S0#<11,17,46>

C C

PCH_SPI_D1_R1<8>

PCH_SPI_D0_R1<8>

PCH_SPI_CLK_R1<8>

PCH_SPI_CS#2<8>

PCH_SPI_CLK_2_R

33_0402_5%

B B

@EMC@

RZ63

0.1U_0402_25V6

1 2

@EMC@

12

CZ77

1 2

RZ72 0_0603_5%@

PJP11

1 2

PAD-OPEN1x1m

1 2

RZ69 10K_0402_5%

1 2

RZ112 0_0402_5%

@

1 2

RZ58

1 2

RZ59

1 2

RZ60

1 2

RZ61 0_0402_5%

@

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

USH & TPM

USH & TPM

USH & TPM

LA-C461P

LA-C461P

LA-C461P

33 61Tuesday, October 13, 2015

33 61Tuesday, October 13, 2015

33 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

+3.3V_HDD +3.3V_HDD +3.3V_HDD

10K_0402_5%

@

12

RN26

10K_0402_5%

12

RN39

10K_0402_5%

10K_0402_5%

@

@

12

12

RN28

RN27

RD1_A_DE0

RD1_A_DE1

RD1_B_DE0

RD1_B_DE1 RD1_A_EQ2

10K_0402_5%

10K_0402_5%

@

@

12

12

RN40

RN41

10K_0402_5%

@

12

RN42

10K_0402_5%

@

12

RN45

10K_0402_5%

@

12

RN43

10K_0402_5%

@

12

RN46

10K_0402_5%

@

12

RN44

10K_0402_5%

@

12

RN47

RD1_A_EQ0

RD1_A_EQ1

10K_0402_5%

12

10K_0402_5%

12

10K_0402_5%

@

12

RN25

D D

10K_0402_5%

12

RN38

@

RN49

@

RN52

10K_0402_5%

@

12

RN50

10K_0402_5%

@

12

RN53

4

10K_0402_5%

@

12

RN51

10K_0402_5%

@

12

RN54

RD1_B_EQ0

RD1_B_EQ1

RD1_B_EQ2

3

IFDET_SATA#_PCIE DEVICE interface

0

1

+3.3V_HDD

0.1U_0201_10V6K

CN19

1

2

SATA

PCIE

0.01UF_0402_25V7K

1

CN20

2

2

1

PCIE/SATA Repeater

UN4

12

VDD_3.3

24

VDD_3.3

1

A_INP

A_OUTP

2

A_INN

A_OUTN

5

B_OUTP

B_INP

4

B_OUTN

B_INN

23

A_DE0

A_EQ0

22

A_DE1

A_EQ1

19

A_EQ2

11

B_EQ0

B_DE0

21

B_DE1

B_EQ1

16

B_EQ2

PWD

7

GND

25

REXT

EPAD

MODE

PS8558BTQFN24GTR2-A_TQFN24_4X4

PCIE/SATA Repeater

UN5

12

VDD_3.3

24

VDD_3.3

1

A_INP

A_OUTP

2

A_INN

A_OUTN

5

B_OUTP

4

B_OUTN

23

A_EQ0

22

A_EQ1

19

A_EQ2

11

B_EQ0

21

B_EQ1

16

B_EQ2

7

GND

25

EPAD

PS8558BTQFN24GTR2-A_TQFN24_4X4

1 2
1 2

1 2
1 2

CN210.22U_0402_10V6K
CN220.22U_0402_10V6K

CN230.22U_0402_10V6K
CN240.22U_0402_10V6K

PCIE_PTX_C_RD_DRX_P12
PCIE_PTX_C_RD_DRX_N12

PCIE_PRX_C_RD_DTX_P12
PCIE_PRX_C_RD_DTX_N12

+3.3V_HDD

0.1U_0201_10V6K

CN29

1

1

2

2

PCIE_PTX_C_RD_DRX_P11

CN320.22U_0402_10V6K

PCIE_PTX_C_RD_DRX_N11

CN310.22U_0402_10V6K

PCIE_PRX_C_RD_DTX_P11

CN330.22U_0402_10V6K

PCIE_PRX_C_RD_DTX_N11

CN340.22U_0402_10V6K

0.01UF_0402_25V7K

CN30

RD1_A_EQ0
RD1_A_EQ1
RD1_A_EQ2

RD1_B_EQ0
RD1_B_EQ1
RD1_B_EQ2

RD2_A_EQ0
RD2_A_EQ1
RD2_A_EQ2

RD2_B_EQ0
RD2_B_EQ1
RD2_B_EQ2

Programmable output de-emph asis level
set t i ng for cha nnel A .
A_DE0: internally pu lled up at ~1 50K;
A_DE1 internally pul led down at ~150K

[A_DE1,A_DE0] ==

C C

LL: -2dB
HL: -7.5dB
LH: -3.5dB (default)
HH: -6dB

Programmable output de-emph asis level
set t i ng f or channel B.
B_DE0: internally pulled up at ~150K;
B_DE1 internally pulled down at ~150K

[B_DE1,B_DE0] ==
LL: -2dB
HL: -7.5dB
LH: -3.5dB (default)
HH: -6dB

+3.3V_HDD +3.3V_HDD +3.3V_HDD

B B

10K_0402_5%

@

12

RN55

10K_0402_5%

@

12

RN59

10K_0402_5%

@

12

RN56

10K_0402_5%

@

12

RN60

10K_0402_5%

10K_0402_5%

@

@

12

12

RN57

RN58

RD2_A_DE0

RD2_A_DE1

RD2_B_DE0

RD2_B_DE1 RD2_A_EQ2

10K_0402_5%

10K_0402_5%

@

@

12

12

RN61

RN62

Equalizer co ntrol and program for cha nnel A.
A_EQ0, A_EQ1 and A_EQ2: internally p ulled down at ~150K

[A_EQ2,A_EQ1,A_EQ0] ==
LLL: For channel loss up to 17dB (default)
LHL: For channel loss up to 14dB
HLL: For channel loss up to 19dB
HHL: For channel loss up to 21dB
LLH: For channel loss up to 18dB
LHH: For channel loss up to 10dB
HLH: For channel loss up to 16dB
HHH: For channel loss up to 20dB

Equalizer co ntrol and program for ch annel B.
B_EQ0, B_EQ1 and B_EQ2: internally pulled down at ~150K

[B_EQ2,B_EQ1,B_EQ0] ==
LLL: For channel loss up to 17dB (default)
LHL: For channel loss up to 14dB
HLL: For channel loss up to 19dB
HHL: For channel loss up to 21dB
LLH: For channel loss up to 18dB
LHH: For channel loss up to 10dB
HLH: For channel loss up to 16dB
HHH: For channel loss up to 20dB

10K_0402_5%

@

12

RN63

10K_0402_5%

@

12

RN66

10K_0402_5%

@

12

RN64

10K_0402_5%

@

12

RN67

10K_0402_5%

@

12

RN65

10K_0402_5%

@

12

RN68

RD2_A_EQ0

RD2_A_EQ1

10K_0402_5%

@

12

RN69

10K_0402_5%

@

12

RN72

10K_0402_5%

@

12

RN70

10K_0402_5%

@

12

RN73

10K_0402_5%

@

12

RN71

10K_0402_5%

@

12

RN74

RD2_B_EQ0

RD2_B_EQ1

RD2_B_EQ2

PCIE_PTX_DRX_P12<10>
PCIE_PTX_DRX_N12<10>

PCIE_PRX_DTX_P12<10>
PCIE_PRX_DTX_N12<10>

if signal is PCIE GEN3/SATA GEN3 maybe change C value
or no need for DG0.9 SATA EXPRESS HDD

PCIE_PTX_DRX_P11<10>
PCIE_PTX_DRX_N11<10>

PCIE_PRX_DTX_P11<10>
PCIE_PRX_DTX_N11<10>

if signal is PCIE GEN3/SATA GEN3 maybe change C value
or no need for DG0.9 SATA EXPRESS HDD

1 2
1 2

1 2
1 2

B_INP
B_INN

A_DE0
A_DE1

B_DE0
B_DE1

PWD

REXT

MODE

18
17

14
15

6
8

13
9

3
10
20

8/25

PCIE_PTX_RD_DRX_P12
PCIE_PTX_RD_DRX_N12

PCIE_PRX_RD_DTX_P12
PCIE_PRX_RD_DTX_N12

RD1_A_DE0
RD1_A_DE1

RD1_B_DE0
RD1_B_DE1

RD1_REXT
IFDET_SAT A#_PCIE

PCIE_PTX_RD_DRX_P11

18

PCIE_PTX_RD_DRX_N11

17

PCIE_PRX_RD_DTX_P11

14

PCIE_PRX_RD_DTX_N11

15

RD2_A_DE0

6

RD2_A_DE1

8

RD2_B_DE0

13

RD2_B_DE1

9

3

RD2_REXT

10

IFDET_SAT A#_PCIE

20

if signal is PCIE GEN3/SATA GEN3 maybe change C value
or no need for DG0.9 SATA EXPRESS HDD

12

CN25 0.22U_0402_10V6K

12

CN26 0.22U_0402_10V6K

RN77 0_0402_5%

@

RN78 0_0402_5%

@

12
12

PCIE_PTX_C_DRX_P12 <35>

PCIE_PTX_C_DRX_N12 <35>

PCIE_PRX_C_DTX_P12 <35>
PCIE_PRX_C_DTX_N12 <35>

PWD Funtion

1 2

RN30 4.99K_0402_1%

IFDET_SAT A#_PCIE <10,1 2,35>

12

CN35 0.22U_0402_10V6K

12

CN36 0.22U_0402_10V6K

RN81 0_0402_5%

@

RN82 0_0402_5%

@

1 2

RN31 4.99K_0402_1%

12
12

Normal mode(default)

0

1

PCIE_PTX_C_DRX_P11 <35>

PCIE_PTX_C_DRX_N11 <35>

PCIE_PRX_C_DTX_P11 <35>
PCIE_PRX_C_DTX_N11 <35>

power down mode

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Mini Card-2/2

Mini Card-2/2

Mini Card-2/2

LA-C461P

LA-C461P

LA-C461P

34 61Tuesday, October 13, 2015

34 61Tuesday, October 13, 2015

34 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

4

3

2

1

+3.3V_HDD

0.1U_0201_10V6K

EMC@

D D

1

CN100

2

+3.3V_HDD_P

0.1U_0201_10V6K

@

1

2

0.1U_0201_10V6K
22U_0603_6.3V6M

CN41

CN42

1

2

22U_0603_6.3V6M

12

12

CZ60

CZ61

2280 SSD

NGFF slot C Key M

ESD request

+3.3V_HDD

1 2

RN37@ 10K_0402_5%

C C

B B

Place near HDD CONN

8/5 CKLT0.9

M2_DEVSLP

Double check P/N

+3.3V_HDD_P

JNGFF3

GND
GND
PERn3
PERp3
GND
PETp3
PETn3
GND
PERn2
PERp2
GND
PETp2
PETn2
GND
PERn1
PERp1
GND
PETn1
PETp1
GND
PERn0/SATA B+
PERp0/SATA B­GND
PETn0/SATA A­PETp0/SATA A+
GND
REFCLKn
REFCLKp
GND

N/C
PEDET
GND
GND
GND

MTG77

BELLW_80159-2242

CONN@

3.3VAUX

3.3VAUX

DAS/DSS#

3.3VAUX

3.3VAUX

3.3VAUX

3.3VAUX

DEVSLP

PERST#

CLKREQ#

PEWake#

SUSCLK

3.3VAUX

3.3VAUX

3.3VAUX

MTG76

2
4
6

N/C

8

N/C

10
12
14
16
18
20

N/C

22

N/C

24

N/C

26

N/C

28

N/C

30

N/C

32

N/C

34

N/C

36

N/C

38
40

N/C

42

N/C

44

N/C

46

N/C

48

N/C

50
52
54
56

N/C

58

N/C

60
62
64
66

68

PCIE_WAKE#

SUSCLK_R

NVME_LED# <40>

1 2

RN99 0_0402_5%

@

1
3
5
7

9
11
13
15
17
19
21
23
25
27

PCIE_PRX_C_DTX_N11<34>
PCIE_PRX_C_DTX_P11<34>

PCIE_PTX_C_DRX_N11<34>
PCIE_PTX_C_DRX_P11<34>

PCIE_PRX_C_DTX_P12<34>
PCIE_PRX_C_DTX_N12<34>

PCIE_PTX_C_DRX_N12<34>
PCIE_PTX_C_DRX_P12<34>

CLK_PCIE_N3<11>
CLK_PCIE_P3<11>

IFDET_SAT A#_PCIE<10,12,34>

29
31
33
35
37
39
41
43
45
47
49
51
53
55
57

59
61
63
65
67

69

2A

PJP34

1 2

PAD-OPEN1x2m

M2_DEVSLP <10>

PCH_PLTRST#_AND <11,28,29,33>

CLKREQ_PCIE#3 <11>

PCIE_WAKE# <29,31>

+3.3V_HDD

SUSCLK <11,29>

Link BELLW_80159-2242 DONE

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

HDD CONN

HDD CONN

HDD CONN

LA-C461P

LA-C461P

LA-C461P

35 61Tuesday, October 13, 2015

35 61Tuesday, October 13, 2015

35 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

4

3

2

1

USB3_PRX_DTX_P1<10>

USB3_PTX_DRX_P1<10>

USB3_PTX_DRX_N1<10>

USB3_PRX_DTX_N1<10>

ILIM_SEL

12

10K_0402_5%

CI16 0.1U_0402_25V6

CI13 0.1U_0402_25V6

USB3_PTX_C_DRX_N1

12

USB_PWR_SHR_VBUS_EN<31>

USB_PWR_SHR_EN#<31>

+5V_ALW

1

2

USB20_N1<10>
USB20_P1<10>

USB_OC0#<10>

47U_0603_6.3V6M

@

CI34

USB3_PTX_C_DRX_P1

12

D D

C C

+5V_ALW

RI13

1 2

RI15 0_0402_5%

@EMC@

1 2

RI16 0_0402_5%

@EMC@

1 2

RI17 0_0402_5%

@EMC@

1 2

RI18 0_0402_5%

@EMC@

ILIM_SEL

47U_0603_6.3V6M

@

1

1

CI33

2

2

10U_0402_6.3V6M

+5V_ALW

@

CI31

USB3_PRX_L_DTX_P1

USB3_PRX_L_DTX_N1

USB3_PTX_L_DRX_P1

USB3_PTX_L_DRX_N1

UI3

1

IN

2

DM_OUT

3

DP_OUT

13

FAULT#

4

ILIM_SEL

5

EN

6

CTL1

7

CTL2

8

CTL3

PI5USB2544ZHEX_TQFN16_3X3

OUT

DP_IN

DM_IN

ILIM_LO

ILIM_HI

GND

GNDP

NC

Link Pericom PI5USB2544 Done

0.1U_0201_10V6K

CI19

1

2

+5V_USB_CHG_PWR

12

SW_USB20_P1

10

SW_USB20_N1

11

15
16

RI14

9
14
17

DI4

USB3_PRX_L_DTX_N1 USB3_PRX_L_DTX_N1

USB3_PRX_L_DTX_P1

USB3_PTX_L_DRX_N1

USB3_PTX_L_DRX_P1

12

22.1K_0402_1%

EMC@

1

1

2

2

4

4

5

5

3

3

8

L05ESDL5V0NA-4_SLP2510P8-10-9

9

10

8

9

7

7

6

6

SW_USB20_N1

SW_USB20_P1

USB3_PRX_L_DTX_P1

USB3_PTX_L_DRX_N1

USB3_PTX_L_DRX_P1

1 2

EMC@

LI7

EXC24CQ900U_4P

+5V_USB_CHG_PWR

150U_B2_6.3VM_R35M

100U_1206_6.3V6M

@

1

1

CI32

+

2

2

34

1

CI14

2

USB20_N1_R

USB20_P1_R

JUSB3

1

VBUS

2

D-

3

D+

4

GND

5

SSRX-

6

SSRX+

7
8
9

GND

GND

GND

SSTX-

GND

SSTX+

GND

SINGA_2UB4008-900101F

CONN@

10
11
12
13

AZC199-02SPR7G_SOT23-3

EMC@

223

DI5

USB20_N1_R
USB20_P1_R

USB3_PRX_L_DTX_N1
USB3_PRX_L_DTX_P1

USB3_PTX_L_DRX_N1
USB3_PTX_L_DRX_P1

0.1U_0201_10V6K

CI17

3

1

1

LINK SUB4008-90010F DONE

B B

A A

Place near UI3.1

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

USB SW

USB SW

USB SW

LA-C461P

LA-C461P

LA-C461P

36 61Tuesday, October 13, 2015

36 61Tuesday, October 13, 2015

36 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

USB3_PTX_DRX_P 3

USB3_PTX_DRX_N3

USB3_PRX_DTX_P 3

USB3_PRX_DTX_N3

USB3_PTX_C_DRX_P 3

12

CI4 0. 1U_0402_25V6

USB3_PTX_C_DRX_N3

12

CI5 0. 1U_0402_25V6

USB3_PRX_DTX_P 3<10>

USB3_PRX_DTX_N3<10>

D D

USB3_PTX_DRX_P 3<10>

USB3_PTX_DRX_N3<10>

RI19 0_0402_5%

@EMC@

RI20 0_0402_5%

@EMC@

@EMC@

@EMC@

1 2

1 2

1 2

RI21 0_0402_5%

1 2

RI22 0_0402_5%

4

USB3_PRX_L_DTX_ P3

USB3_PRX_L_DTX_ N3

USB3_PTX_L_DRX_ P3

USB3_PTX_L_DRX_ N3

3

DI1

USB3_PRX_L_DTX_ N3 USB3_PRX_L_DTX_ N3

USB3_PRX_L_DTX_ P3 USB3_PRX_L _DTX_P3

USB3_PTX_L_DRX_ N3 USB3_PTX_L_DRX_ N3

USB3_PTX_L_DRX_ P3 USB3_PTX _L_DRX_P3

USB20_P3<10>

USB20_N3<10>

USB20_P3

USB20_N3

EMC@

1

1

2

2

4

4

5

5

3

3

8

L05ESDL5V0NA-4_SLP2510P8-10-9

LI3

1 2

EXC24CQ900U_4P

EMC@

9

10

8

9

7

7

6

6

34

USB20_P3_R

USB20_N3_R

+USB_LEFT_PWR

100U_1206_6.3V6M

12

CI1

2

JUSB1

CONN@

1

USB20_N3_R

223

1

1

USB20_P3_R

USB3_PRX_L_DTX_ N3
USB3_PRX_L_DTX_ P3

AZC199-02SPR7G_SOT23-3

USB3_PTX_L_DRX_ N3

EMC@

USB3_PTX_L_DRX_ P3

DI2

0.1U_0201_10V6K

CI3

1

3

2

VBUS

2

D-

3

D+

4

GND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

ACON_TARAV-9R1U91

GND
GND
GND
GND

1

10
11
12
13

Link TARAV-9R1U91 DONE

8/19 for layout routing change

DFB request:
main SM070003Z00 (INPAQ_MCM1012B900F06BP_4P)
Footprint use 2nd source SM070004400 (PANAS_EXC24CQ900U_4P)
Pitch change from 0.5mm to 0.55mm

C C

B B

A A

USB3_PRX_DTX_P 4<10>

USB3_PRX_DTX_N4<10>

USB3_PTX_C_DRX_P 4

USB3_PTX_DRX_P 4<10>

USB3_PTX_DRX_N4<10>

12

CI28 0.1U_0402_25V6

CI27 0.1U_0402_25V6

USB3_PTX_C_DRX_N4

12

RI23 0_0402_5%

@EMC@

RI24 0_0402_5%

@EMC@

@EMC@

@EMC@

1 2

1 2

1 2

RI25 0_0402_5 %

1 2

RI26 0_0402_5 %

USB3_PRX_L_DTX_ P4

USB3_PRX_L_DTX_ N4

USB3_PTX_L_DRX_ P4

USB3_PTX_L_DRX_ N4

DI6

USB3_PRX_L_DTX_ N4 USB3_PRX_L_DTX_N4

USB3_PRX_L_DTX_ P4 USB3_PRX_L_DTX _P4

USB3_PTX_L_DRX_ N4 USB3_PTX_L_DRX_N4

USB3_PTX_L_DRX_ P4 USB3_PTX_L_DRX _P4

USB20_P4<10>

USB20_N4<10>

USB20_P4

USB20_N4

EMC@

1

2

4

5

3

8/19 for layout routing change

10

1

9

2

7

4

6

5

3

8

L05ESDL5V0NA-4_SLP2510P8-10-9

EMC@

LI4

1 2

EXC24CQ900U_4P

9

8

7

6

34

USB20_P4_R

USB20_N4_R

+5V_ALW

10U_0603_10V6M

12

+USB_REAR_PWR

100U_1206_6.3V6M

12

+5V_ALW

10U_0603_10V6M

@

CI11

12

UI1

5

0.1U_0201_10V6K

@

1

CI6

2

1

CI8

2

0.1U_0201_10V6K

CI12

1

2

USB_PWR_ EN1#<31>

CI7

USB20_N4_R

223

1

1

USB_PWR_ EN2#<31>

USB20_P4_R

USB3_PRX_L_DTX_ N4
USB3_PRX_L_DTX_ P4

USB3_PTX_L_DRX_ N4
USB3_PTX_L_DRX_ P4

0.1U_0201_10V6K

CI10

AZC199-02SPR7G_SOT23-3

3

EMC@

DI3

IN

4

EN

SY6288D20AAC_SOT23-5

UI2

5

IN

4

EN

SY6288D20AAC_SOT23-5

+USB_LEFT_PWR

1

OUT

2

GND

3

OCB

9/3 change t o SOT23 package

JUSB2

1

VBUS

2

D-

3

D+

4

GND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

ACON_TARAV-9R1U91

CONN@

GND
GND
GND
GND

USB_OC1# <10>

10
11
12
13

Link TARAV-9R1U91 DONE

+USB_REAR_PWR

1

OUT

2

GND

3

OCB

9/3 change t o SOT23 package

USB_OC2# <10>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Titl e

Titl e

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. I N ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCL OSED TO ANY THIRD
PART Y W IT HOU T DE LL ' S EX PR ES S W RI TTE N C ON SEN T.

5

4

3

2

Titl e

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

USB3.0

USB3.0

USB3.0

LA-C461P

LA-C461P

LA-C461P

1

37 61Tuesday, October 13, 2015

37 61Tuesday, October 13, 2015

37 61Tuesday, October 13, 2015

1.0

1.0

1.0

5

12

HUB_DP0_P0<25>

HUB_DP0_N0<25>

D D

C C

B B

HUB_DP0_P1<25>

HUB_DP0_N1<25>

HUB_DP0_P2<25>

HUB_DP0_N2<25>

HUB_DP0_P3<25>

HUB_DP0_N3<25>

HUB_DP0_HPD

C302 0.1U_0402_25V6

12

C295 0.1U_0402_25V6

12

C297 0.1U_0402_25V6

12

C299 0.1U_0402_25V6

12

C304 0.1U_0402_25V6

12

C306 0.1U_0402_25V6

12

C300 0.1U_0402_25V6

12

C301 0.1U_0402_25V6

HUB_DP0_HPD<25> HUB_DP1_HPD <25>

Close to DOCK
Its for Enhance ESD on
dock issue.

100K_0402_5%

12

R268

HUB_DP0_P0_C
HUB_DP0_N0_C

HUB_DP0_P1_C
HUB_DP0_N1_C

HUB_DP0_P2_C
HUB_DP0_N2_C

HUB_DP0_P3_C
HUB_DP0_N3_C

0.033U_0402_16V7K

12

C310

+DOCK_PWR_BAR +DOCK_PWR_BAR

4

CONN@

SW_LAN1_10_GRN#<27>

1 2

R259 33_0402_5%EMC@

1 2

R252 33_0402_5%EMC@

1 2

R253 33_0402_5%EMC@

1 2

R255 33_0402_5%EMC@

1 2

R257 33_0402_5%EMC@

1 2

R263 33_0402_5%EMC@

1 2

R265 33_0402_5%EMC@

1 2

R266 33_0402_5%EMC@

HUB_SW1_AUXP<24>
HUB_SW1_AUXN<24>

HUB_DP0_HPD

+NBDOCK_DC_IN_SS

@EMC@

HUB_VGA_BLUE<25>

HUB_VGA_RED<25>

HUB_VGA_GREEN<25>

HUB_VGA_HSYNC<25>
HUB_VGA_VSYNC<25>

CLK_MSE<32>
DAT_MSE<32>

DAI_BCLK#<30>
DAI_LRCK#<30>

DAI_DI<30>

DAI_DO#<30>

DAI_12MHZ#<30>

D_LAD0<31>
D_LAD1<31>

D_LAD2<31>
D_LAD3<31>

D_LFRAME#<31>

D_CLKRUN#<31>

D_SERIRQ<31>

D_DLDRQ1#<31>

CLK_PCI_DOCK<8>

DOCK_SMB_CLK<32>

DOCK_SMB_DAT<32>

DOCK_SMB_ALERT#<31,42>

DOCK_PSID<42>

DOCK_PWR_BTN#<32>

SLICE_BAT_PRES#<31,42,51> DOCK_DET# <31,51>

12

DOCK_DET_1

HUB_DP0_P0_R
HUB_DP0_N0_R

HUB_DP0_P1_R
HUB_DP0_N1_R

HUB_DP0_P2_R
HUB_DP0_N2_R

HUB_DP0_P3_R
HUB_DP0_N3_R

0.1U_0603_50V7K

4.7U_0805_25V6-K

@

12

C33

L30ESD24VC3-2_SOT23-3

2

3

C317

D20 @EMC@

1

JDOCK1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

69

71

71

73

73

75

75

77

77

79

79

81

81

83

83

85

85

87

87

89

89

91

91

93

93

95

95

97

97

99

99

101

101

103

103

105

105

107

107

109

109

111

111

113

113

115

115

117

117

119

119

121

121

123

123

125

125

127

127

129

129

131

131

133

133

135

135

137

137

139

139

141

141

143

143

145

GND1

146

PWR1

147

PWR1

151

Shield_G

152

Shield_G

153

Shield_G

154

Shield_G

155

Shield_G

156

Shield_G

JAE_WD2F144W BHR500-DT~D

3

GND2
PWR2
PWR2

Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G

WD2F144 WBHR500- DT

2

DOCK_AC_OFF

2

2

4

4

6

6

8

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

148
149
150

157
158
159
160
161
162

HUB_DP1_P0_R
HUB_DP1_N0_R

HUB_DP1_P1_R
HUB_DP1_N1_R

HUB_DP1_P2_R
HUB_DP1_N2_R

HUB_DP1_P3_R
HUB_DP1_N3_R

HUB_DP1_HPD

SATA_PRX_C_DTX_P1
SATA_PRX_C_DTX_N1

SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1

DOCK_DET_R#

0.1U_0603_50V7K
C318

12

DOCK_AC_OFF <51>
SW_LAN1_100_ORG# <27>

HUB_DP1_CADET <24,25>HUB_DP0_CADET<24,25>

1 2

R260 33_0402_5%EMC@

1 2

R261 33_0402_5%EMC@

1 2

R254 33_0402_5%EMC@

1 2

R256 33_0402_5%EMC@

1 2

R262 33_0402_5%EMC@

1 2

R264 33_0402_5%EMC@

1 2

R258 33_0402_5%EMC@

1 2

R267 33_0402_5%EMC@

HUB_SW2_AUXP <24>
HUB_SW2_AUXN <24>

ACAV_DOCK_SRC# <51>

HUB_VGA_SDA <25>

HUB_VGA_SCL <25>

12
12

C312 0.01UF_0402_25V7K
C313 0.01UF_0402_25V7K

1 2
1 2

C314 0.01UF_0402_25V7K
C315 0.01UF_0402_25V7K

USB20_P6 <10>

USB20_N6 <10>

USB20_P5 <10>

USB20_N5 <10>

CLK_KBD <32>
DAT_KBD <32>

USB3_PRX_DTX_N2 <10>

USB3_PRX_DTX_P2 <10>

USB3_PTX_DRX_N2 <10>

USB3_PTX_DRX_P2 <10>

BREATH_LED# <32,40>
SW_LAN1_ACTLED_YEL# <27>

SW_LAN1_MDIP0 <27>

SW_LAN1_MDIN0 <27>

SW_LAN1_MDIP1 <27>

SW_LAN1_MDIN1 <27>

+LOM_VCT

SW_LAN1_MDIP2 <27>
SW_LAN1_MDIN2 <27>

SW_LAN1_MDIP3 <27>
SW_LAN1_MDIN3 <27>

DOCK_DCIN_IS+ <50>
DOCK_DCIN_IS- <50>

DOCK_POR_RST# <32>

10_0402_5%

12

EMC@

R41

D19

1 2

RB751S40T1G_SOD523-2

10_0402_5%

12

EMC@

R6

HUB_DP1_P0_C
HUB_DP1_N0_C

HUB_DP1_P1_C
HUB_DP1_N1_C

HUB_DP1_P2_C
HUB_DP1_N2_C

HUB_DP1_P3_C
HUB_DP1_N3_C

SATA_PRX_DTX_P1 <10>
SATA_PRX_DTX_N1 <10>

SATA_PTX_DRX_P1 <10>
SATA_PTX_DRX_N1 <10>

+LOM_VCT

12

12

C294 0.1U_0402_25V6

12

C296 0.1U_0402_25V6

12

C298 0.1U_0402_25V6

12

C303 0.1U_0402_25V6

12

C305 0.1U_0402_25V6

12

C307 0.1U_0402_25V6

12

C308 0.1U_0402_25V6

12

C309 0.1U_0402_25V6

1U_0402_6.3V6K

@

C316

12

10_0402_5%

DOCK_DET#

CLK_PCI_DOCKDAI_12MHZ# DAI_BCLK#

R273

EMC@

HUB_DP1_P0 <25>
HUB_DP1_N0 <25>

HUB_DP1_P1 <25>
HUB_DP1_N1 <25>

HUB_DP1_P2 <25>
HUB_DP1_N2 <25>

HUB_DP1_P3 <25>
HUB_DP1_N3 <25>

0.033U_0402_16V7K

@EMC@

12

C311

Close to DOCK
Its for Enhance ESD on dock
issue.

HUB_DP1_HPD

1 2

+3.3V_ALW2

R272100K_0402_5%

1

100K_0402_5%

12

R271

4.7P_0402_50V8C

12

C43

EMC@

A A

4.7P_0402_50V8C

12

C42

EMC@

4.7P_0402_50V8C

12

C319

EMC@

EMI depop location

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

E-Dock

E-Dock

E-Dock

LA-C461P

LA-C461P

LA-C461P

38 61Tuesday, October 13, 2015

38 61Tuesday, October 13, 2015

38 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

4

3

2

1

To uc h Pa d

+3.3V_TP

4.7K_0402_5%

4.7K_0402_5%

12

D D

DAT_TP_SIO<32>

CLK_TP_SIO<32>

+3.3V_TP +3.3V_TP

C C

I2C_1_SDA<9>

I2C_1_SCL<9>

Reserve for future use

B B

RZ18

330P_0402_50V8J

12

4.7K_0402_5%

12

RZ20

12

RZ19

DAT_TP_SIO_R

CZ31

@

1 2

RZ26 0_0402_5%

@

1 2

RZ29 0_0402_5%

@

330P_0402_50V8J

12

CZ30

4.7K_0402_5%

12

RZ21

RZ22 0_0402_5%

@

RZ23 0_0402_5%

12

CLK_TP_SIO_R

12

I2C_1_SDA_ R

I2C_1_SCL_ R

10K_0402_5%

12

RZ116

10K_0402_5%

12

RSMRST circuit

+3.3V_ALW

@

CZ34

1 2

0.1U_0201_10V6K

5

1

PCH_RSMRST#<32>

ALW_PWRGD_3V_5V<43>

P

B

2

A

G

3

4

O

UZ6

TC7SH08FU_SSOP5~D

+3.3V_RUN +3.3V_TP

RZ117

PCH_RSMRST#_Q <11,14>

PJP16

1 2

PAD-OPEN1x1m

Keyboard

KB_DET#<9>

+5V_RUN
+3.3V_ALW

BC_INT#_ECE1117<32>

BC_DAT_ECE1117<32>

BC_CLK_ECE1117<32>

+3.3V_TP

TOUCHPAD_INTR#<12>

Reserve for future use

DAT_TP_SIO_R

CLK_TP_SIO_R

I2C_1_SDA_ R
I2C_1_SCL_ R

Link 50506-02041-P0 DONE

eDP Cable W CAM@

Part Number

DC02C00 7600 H-CONN SET 13D MB-EDP-CAMERA

eDP TS Cable W CAM@

Part Number

DC02C00 7C00 H-CONN SET 13D MB-EDP-CAMERA-TS

eDP Cable W /O CAM@

Part Number

DC02C00 7D00 H-CONN SET 13D MB-EDP

SATA SPINDLE Cable@

Part Number

DC02C00 7500 H-CONN SET 13D MB-SPINDLE HDD

SATA Cable@

Part Number

DC02C00 7400 H-CONN SET 13D MB-MSATA HDD

DC-IN Cable@

Part Number

DC30100 Q100 CONN SET 13F DCJACK-MB 2DW1003-041110F

BATT Cable@

Part Number

DC02001 X800 H-CONN SET 13D MB-BATT CABLE

Descrip tion

Descrip tion

Descrip tion

Descrip tion

Descrip tion

Descrip tion

Descrip tion

ACES_50506-02041-P01

22

GND2

21

GND1

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

JKBTP1

CONN@

CHECK PIN DEFINE

LED FFC@

Part Number

NBX0001 JG00 FFC 10P F P0.5 PAD0.3 172MM MB-LED/B 13D

FP FFC@

Part Number

NBX0001 JK00 FFC 8P F P0.5 PAD.3 123MM MB-FP VALIDITY

TP FFC@

Part Number

NBX0001 JI00 FFC 16P F P0.5 PAD=0.3 119MM MB-TP 13D

USH Board FFC@

Part Number

NBX0001 JJ00 FFC 26P G P0.5 PAD.3 88MM MB-USH/B 13D

RTC BATT@

Part Number

GC02001 DS00 BATT CR2032 3V 225MAH PA 5 W/C 30MM

@FAN

Part Number Descr iption

DC28A00 0800

@Speak

Part Number Descr iption

PK23000 3Q0L

+5V_RUN+3.3V_ALW+3.3V_TP

0.1U_0201_10V6K

0.1U_0201_10V6K

1

@

CZ27

2

0.1U_0201_10V6K

1

1

@

CZ28

CZ29

2

2

Place close to JKBTP1

Descrip tion

Descrip tion

Descrip tion

Descrip tion

Descrip tion

FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA

SPK PACK ZJX 2.0W 4 OHM FG

@

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEE T OF ENGI NEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFER RED OR COPIED WIT HOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THI S SHEET NOR THE I NFORMATION IT CONTAINS WAY BE USE D BY OR DIS CLO SED TO AN Y THI RD
PAR TY WI TH O UT DE LL 'S E XP RE S S W RI T TE N C ON S EN T.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Keyboard

Keyboard

Keyboard

LA-C461P

LA-C461P

LA-C461P

39 61Tuesday, October 13, 2015

39 61Tuesday, October 13, 2015

39 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

4

3

2

1

HDD LED solut i on f or Whi t e LE D

+3.3V_ALW

10K_0402_5%

12

RZ24

QZ3B

RZ118 0_0402_5%@

1 2

DMN65D8LDW-7_SOT363-6

5

D D

PCH_SATA _LED#<10>

NVME_LED#<35>

MASK_SATA_LED#<31>

LED_SATA_DIAG_OUT#<31>

DZ3

1 2

34

RB751S40T1G_SOD523-2

DZ4

1 2

RB751S40T1G_SOD523-2

SYS_LED_MASK#

QZ3A

DMN65D8LDW-7_SOT363-6

126

SATA_LED#

2

SATA_LED

QZ4

DDTA114EUA-7-F_SOT323-3

1 3

1 2

RZ27 150_0402_5%

Bat t er y LED

BAT2_LED#<32>

BAT1_LED#<32>

1 2

RZ25 150_0402_5%

1 2

RZ28 330_0402_5%

BATT_WHITE#

BATT_YELLOW#

LED P/N c hange to SC50000FL00 from SC50000BA00

Breath LED

C C

BREATH_LED#<32,38>

+3.3V_ALW

@

CZ48

1 2

0.1U_0201_10V6K

5

1

SYS_LED_MASK#<27,31>

LID_CL#<31,40>

B

2

A

3

P

MASK_BASE_LEDS#

4

O

G

UZ10

TC7SH08FU_SSO P5~D

QZ7B

DMN65D8LDW-7_SOT363-6

34

5

MASK_BASE_LEDS#

BREATH_LED#_Q BREATH_WHITE_LED_SNIFF#

1 2

RZ32 330_0402_5%

1 2

RZ34 150_0402_5%

BREATH_WHITE_LED#

LED3

LTW-C193DC-C_W HITE

Place LED3 close to SW3

+5V_ALW

21

POWER & INSTANT ON SWITCH

SW3

1

POWER _SW #_MB<11,32>

B B

2

4

SKRBAAE010_4P

3

Place CZ1 near UZ1.

LID SWITCH

+3.3V_ALW

0.1U_0201_10V6K

1

@

CZ93

2

2

UZ1

VDD

3

VOUT

GND

AH1806-W-7_SC59-3

1

LID_CL#

LID_CL# <31,40>

Hall sensor: SA000058600

Fiducial Mark

FD1@

1

FIDUCIAL MARK~D

FD2@

1

FIDUCIAL MARK~D

FD3@

1

FIDUCIAL MARK~D

FD4@

A A

1

FIDUCIAL MARK~D

Mask All LEDs (Unobtrusive mode)
Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened) 11

CPU NGFF

H3@

H4@

H2@

H_3P8

H_3P8

1

1

5

H_3P8

H1@

H_3P8

1

LED Circuit Control Table

H5@

H6@

H_1P1N

H_1P1N

1

1

1

SYS_LED_MASK # LID_CL #

H_2P3

X

H12@

H_2P3

1

H26@

H25@

1

1

4

0
10

H10@

H9@

H8@

H_3P2

H7@

H_3P2

1

H_2P3

H_2P3

1

1

1

H23@

H24@

H_2P5

H_2P5

1

1

H_2P5

For JAE JSIM1 boss hole

H16@

H15@

H14@

H_2P3

H_2P5

H_2P5

1

1

H29@

H28@

H27@

H_2P3

H_2P5

H_2P5X3P0

1

1

1

H18@

H17@

H_2P5

H_4P0

1

1

1

H30@

H31@

H_4P5

H_2P5

1

1

H21@

H22@

H20@

H_3P3

H_3P3

H_2P3

1

1

1

H33@

H32@

H_2P5

1

H37@

H_2P5

H_2P5

1

1

3

H35@

H34@

H_0P9N

H_0P7N

1

1

H38@

1

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE U SED BY OR DIS CLOSED TO ANY THIRD
PART Y WI TH OUT DE LL 'S E XP RES S WR IT TE N CO NSE NT.

2

LED board CONN

+5V_ALW

BREATH_WHITE_LED#
SATA_LED
BATT_YELLOW#
BATT_WHITE#

Link E-T_4251K-F06N-40L DONE

DELL CONFIDENTIAL/PROPRIETARY

Title

Titl e

Titl e

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

JLED1

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

GND1

8

GND2

E-T_6705K-Y06N-00L

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PAD, LED

PAD, LED

PAD, LED

LA-C461P

LA-C461P

LA-C461P

1

1.0

1.0

40 61Tuesday, Oct ober 13, 2015

40 61Tuesday, Oct ober 13, 2015

40 61Tuesday, Oct ober 13, 2015

1.0

5

4

3

2

1

+3.3V_M source+3.3V_WLAN/+3.3V_LAN source

PJP19

1 2

1 2

1 2

1 2

PJP22

2A

+3.3V_WLAN

+3.3V_LAN

1A

0.63A

+3.3V_ALW_PCH

3.435A

+3.3V_RUN

A_ON<32>

+5V_ALW

+3.3V_HDD source

3.3V_HDD_EN<9>

+3.3V_ALW

+5V_ALW

+3.3V_ALW

UZ8 @

1

VOUT

VIN

2

VOUT

VIN

3

ON

4

VBIAS

AOZ1336_DFN8 _2X2

UZ22 @

1

VIN

2

VIN

3

ON

4

VBIAS

AOZ1336_DFN8 _2X2

GND
GND

1 2

7

+3.3V_M_UZ8

8

6

CT

5
9

+3.3V_HDD_UZ22

7

VOUT

8

VOUT

6

CT

5

GND

9

GND

PAD-OPEN1x1m

1 2

CZ43 0.1U_0201_10V6K@

1 2

CZ42 470P_0402_50V7K

@

PJP36

1 2

PAD-OPEN1x2m

1 2

CZ64 0.1U_0201_10V6K@

CZ69 470P_0402_50V7K

@

PJP18

@

PAD-OPEN1x2m

1 2

1 2

+3.3V_M

+3.3V_HDD+3.3V_RUN

2A

+3.3V_HDD

0.013A

PJP20

@

PJP12

1 2

PAD-OPEN1x2m

1 2

@

CZ36 0.1U_0201_10V6K

1 2

CZ37 470P_0402_50V7K

1 2

CZ23 470P_0402_50V7K

1 2

@

CZ50 0.1U_0201_10V6K

PJP13

1 2

PAD-OPEN1x1m

+5V_ALW

+3.3V_ALW

UZ2

1

VIN1

VOUT1

2

VIN1

VOUT1

3

ON1

4

VBIAS

5

6

EM5209VF_SON14 _2X3

GND

ON2

VIN2

VOUT2

VIN27VOUT2

GPAD

CT1

CT2

+3.3V_WLAN_UZ2

14
13

12

11

10

9

+3.3V_LAN_UZ2

8

15

8/5 CKLT0.9

D D

SIO_SLP_WLAN#<11,31>

AUX_EN_WOW L<31>

1 2

RZ38 1 00K_0402_5%

1 2

RZ71 0_0402_ 5%

@

1 2

RZ70 0_0402_ 5%

@

SIO_SLP_LAN#<11,32>

AUX_EN_WOW L

+3.3V_ALW_PCH/+3.3V_RUN source

C C

+3.3V_ALW

UZ3

1

VIN1

2

RZ65 0_0402_5%

@

PCH_ALW_ON<32>

SIO_SLP_SUS#<8,11,17,18,32,45,46,47,53>

1 2
1 2

RZ64 0_0402_5%

@

+5V_ALW

RUN_ON

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2
VIN27VOUT2

EM5209VF_SON14 _2X3

VOUT1
VOUT1

GND

VOUT2

GPAD

CT1

CT2

+3.3V_ALW_PCH_UZ3

14
13

12

11

10

9

+3.3V_RUN_UZ3

8

15

1 2

PAD-OPEN1x1m

@

CZ40 0.1U_0201_10V6K

CZ41 470P_0402_50V7K

CZ46 1000P_0402_50V7K

@

CZ47 0.1U_0201_10V6K

1 2

PAD-OPEN1x3m

B B

+3.3V_SUS source+5V_RUN/+3.3V_WWAN source

PJP21

+5V_ALW

RUN_ON<32,46,53>

3.3V_WWAN_EN<31>

3.3V_WWAN_EN

1 2

RZ40 1 00K_0402_5%

A A

5

3.3V_WWAN_EN

+3.3V_ALW

UZ4

1

VIN1

VOUT1

2

VIN1

VOUT1

3

ON1

4

VBIAS

5

ON2

6

VIN2

VOUT2

VIN27VOUT2

EM5209VF_SON14 _2X3

CT1

GND

CT2

GPAD

+5V_RUN_UZ4

14
13

12

11

10

+3.3V_WWAN_UZ4

9
8

15

4

1 2

PAD-OPEN1x2m

1 2

@

CZ44 0.1U_0201_10V6K

1 2

CZ45 470P_0402_50V7K

1 2

CZ38 470P_0402_50V7K

1 2

@

CZ39 0.1U_0201_10V6K

PJP23

1 2

PAD-OPEN1x3m

2A

+5V_RUN

+3.3V_WWAN

2.5A

Move to USH/B

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET A ND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USE D BY OR DI SC LOSE D TO ANY T HIR D
PAR TY W ITH OU T DE LL 'S E XP RE SS W RIT TE N C ON SEN T.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Nu mber Rev

Size Document Nu mber Rev

Size Document Nu mber Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Power control

Power control

Power control

LA-C461P

LA-C461P

LA-C461P

1

41 61Tu esday, October 13, 201 5

41 61Tu esday, October 13, 201 5

41 61Tu esday, October 13, 201 5

1.0

1.0

1.0

5

4

3

2

1

+COINCELL

COIN RTC Battery

12

PR2

PD1

PQ2

1 3

D

2

12

3

PBAT_PRES# <32,50,51>PBAT_SMBCLK <32>

S

G

PC4

1500P_0402_50V7K

1

2

1K_0402_5%

+Z4012

2

+RTC_CELL

1

1

PC2
1U_0603_10V6K

2

DOCK_SMB_ALERT# <31,38>

PU1

NO

GND

NC3COM

TS5A63157DCKR_SC70-6~D

6

IN

5

V+

4

+COINCELL

GPIO_PSID_SELECT <31>

+5V_ALW

PS_ID <32>

JRTC1

@

1

3

1

G

4

22G

TYCO_2-1775293-2~D

+3.3V_RTC_LDO

D D

1

1

PD2

EMC@

TVNST52302AB0_SOT523-3

2

Primary Battery Connector

PBATT1

@

1

1

2

2

3

3

4

4

5

5

12

PC3

EMC@

2200P_0402_50V7K

C C

B B

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

DEREN_40-42251-01001RHF

NB_PSID

PBAT_SMBCLK_C
PBAT_SMBDAT_C
PBAT_PRES#_C

GND

2

3

1

PL4

EMC@

BLM15AG102SN1D_2P

12

EMC@

PD6
PESD5V0U2BT_SOT 23-3

3

PRP1

18
27
36
45

100_0804_8P4R_5%

PR8

100K_0402_1%

PR10

15K_0402_1%

EMC@

TVNST52302AB0_SOT523-3

2

3

1 2

1 2

PD3

PBAT_SMBDAT <32>

PR5

@

1 2

0_0402_5%

D

1 3

2

B

E

PBATT+_C

33_0402_5%

S

1 2

PQ3
FDV301N-G_SOT23-3

G

2

C

PQ4
MMBT390 4WT 1G NP N SC70- 3

3 1

FBMJ4516HS720NT_2P

FBMJ4516HS720NT_2P

PR7

PL2

EMC@

1 2

PL3

EMC@

1 2

+5V_ALW

12

PR9
10K_0402_1%

PR11

@

1 2

10K_0402_5%

+PBATT

SLICE_BAT_PRES#<31,38,51>

+3.3V_ALW

PR6

2.2K_0402_5%

1 2

+3.3V_ALW

12

PR3

100K_0402_5%

PD4

1 2

SDMK0340L-7-F_SOD323- 2~D

DOCK_PSID<38>

EMC@

PESD5V0U2BT_SOT 23-3

PD7

NB_PSID_TS5A63157

PSID_DISABLE# <31>

BAS40CW SOT -323

@

PR4

1 2

0_0402_5%

3

LP2301ALT1G_SOT23-3

2

1

DC_IN+ Source

+DC_IN

PL1

EMC@

FBMJ4516HS720NT_2P

1 2

PQ1B

@

PJPDC1

@

7

GND

6

GND

-DCIN_JACK-DC IN_JACK

5

5

4

4

+DCIN_JACK

3

3

A A

2

2

1

1

CVILU_CI0805M1HRC-NH

12

PC1

EMC@

1000P_0603_50V7K

PJP1

1 2

PAD-OPEN 1x3m

5

12

PC6

0.1U_0603_25V7K

@EMC@

2

12

16

PR13

4.7K_0805_5%

@

DCX124EK-7-F PNP/NPN_SC74-6~D

@

PQ1A

4 3

5

DCX124EK-7-F PNP/NPN_SC74-6~D

AC_DIS <31,50,51>

12

PR1

PC5

1 2

1M_0402_5%

0.022U_0805_50V7K

4

AON7401 1P DFN3*3

1
2
3 5

PR14

1 2

10K_0402_5%

12

PR15

1M_0402_5%

PQ5

4

SOFT_START _GC <51>

12

PR12

+DC_IN_SS

12

PC7

100K_0402_5%

10U_0805_25V6K

THIS SHE ET OF ENGIN EERI NG DRAW ING IS THE P ROPR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR W RITTEN CONSENT OF COM PAL ELECTRONICS, INC.

3

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Titl e

Titl e

Titl e

Size

Size

Size

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

+DCIN

+DCIN

+DCIN

Document Number Rev

Document Number Rev

Document Number Rev

LA-C461P

LA-C461P

LA-C461P

1

42 61Tuesday, October 13, 2015

42 61Tuesday, October 13, 2015

42 61Tuesday, October 13, 2015

1.0

1.0

1.0

A

1 1

+PWR_SRC

PJP100

21

PAD-OPEN 1x2m~D

PC100

0.1U_0402_25V6

@EMC@

2 2

+3.3V_ALW

12

PC103

2200P_0402_50V7K

EMC@

PR107
100K_0402_5%

1 2

PGOOD_3V

12

3V_VIN

PC105

12

PC104

@

10U_0805_25V6K

10U_0805_25V6K

+PWR_SRC

PJP101

21

PAD-OPEN 1x2m~D

3 3

@

PR114

0_0402_5%

ALWON<32>

4 4

1 2

12

5V_VIN

PC116

2200P_0402_50V7K

EMC@

3V5V_EN

PC128

4.7U_0402_6.3V6M

12

12

PC117

PC118

10U_0805_25V6K

10U_0805_25V6K

PR113
100K_0402_5%

1 2

PGOOD_5V

PC115

0.1U_0402_25V6

@EMC@

PR116

1M_0402_1%

12

+3.3V_ALW

12

EN1 and EN2 dont't floating

12

B

0.1U_0402_10V7K

PGOOD_3V

PGOOD_5V

BST_3V

2

EN112EN2

EN112EN2

IN

IN3IN4IN

FF13OUT14NC

PC113
1000P_0402_50V7K

3V_FB

2

1

IN

IN3IN4IN

FF13OUT14LDO

15

12

BS

GND

VCC

GND

1

BS

GND

GND

15

LX

LX

NC

5V_FB

20

LX

19

LX

18

LDO

NC

1 2

17

16

21

BST_5V

20

19

18

17

16

21

12

PR108

1K_0402_5%

1 2

0_0603_5%

1 2

PC119

1 2

4.7U_0603_6.3V6K

1 2

1 2

@

PC111

4.7U_0603_6.3V6K

@

+5V_ALW2

5V LDO 150mA~300mA

PC126

4.7U_0603_6.3V6K

PC127
1000P_0402_50V7K

1 2

1K_0402_5%

1 2

5

12

LX_3V

3V5V_EN

LX_5V

PU102

6

7

8

9

10

PU100

6

LX

7

GND

8

SY8288BRAC_QFN20_3X3

GND

9

PG

10

NC

11

ENLDO_3V5V

5

LX

GND

SY8286CRAC_QFN20_3X3

GND

PG

NC

11

3V5V_EN

ENLDO_3V5V

C

+3.3V_ALW

@

PC101

1 2

5

1

P

B

4

O

2

A

G

3

@

PU101

TC7SH08FU_SSOP5~D

@

PR100

0_0603_5%

1 2

LX_3V

@

PR104

0_0402_5%

PR105 0_0402_5%

PC102

1 2

0.1U_0603_25V7K

+3.3V_ALW2

+3.3V_RTC_LDO

3.3V LDO 150mA~300mA

PR111

LX_5V

PR117

PC114

1 2

0.1U_0603_25V7K

@

PR120

0_0402_5%

1 2

@

PR101

0_0402_5%

1 2

@

PR119

0_0402_5%

1 2

12

PR112

@EMC@

5V_SN

12

PC125

@EMC@

ALW_PWRGD_3V_5V <39>

PL100

1.5UH_PCMC063T-1R5MN_9A_20%

1 2

PR106

12

Update PH401 change
to Common Part
SH000016800 20141202

4.7_1206_5%

@EMC@

3V_SN

12

PC112

680P_0603_50V7K

@EMC@

12

PR109

@

150K_0402_1%

12

PR110

@

150K_0402_1%

PL101

2.2UH +-20% 7.8A 7X7X3 MOLDING

1 2

Update PH401 change
to Common Part
SH000016800 20141202

4.7_1206_5%

680P_0603_50V7K

ENLDO_3V5V

12

PR115

@

150K_0402_1%

12

PR118

@

150K_0402_1%

D

PR102
499K_0402_1%

1 2

12

PR103

499K_0402_1%

12

12

PC106

22U_0805_6.3V6M

12

12

PC107

PC108

22U_0805_6.3V6M

22U_0805_6.3V6M

Vout is 3.234V~3.366V

+3.3V_ALWP +3.3V_ALW

12

12

12

PC120

PC121

22U_0805_6.3V6M

22U_0805_6.3V6M

5VALWP
TDC 4.5 A
Peak Current 6.3 A
OCP Current 9 A f i x by I C

+PWR_SRC

+3.3V_ALWP

12

PC109

PC110

@

22U_0805_6.3V6M

22U_0805_6.3V6M

12

PC123

PC122

22U_0805_6.3V6M

22U_0805_6.3V6M

3VALWP
TDC 7.087 A
Peak Current 8.504 A
OCP Current 9 A f i x by I C

PJP102

112

JUMP_43X118

PJP103

112

JUMP_43X118

+5V_ALWP

12

PC124

@

22U_0805_6.3V6M

E

2

2

+5V_ALW+5V_ALWP

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

+5V_ALW/3.3V_ALW

+5V_ALW/3.3V_ALW

+5V_ALW/3.3V_ALW

LA-C461P

LA-C461P

LA-C461P

43 61Tuesday, October 13, 2015

43 61Tuesday, October 13, 2015

43 61Tuesday, October 13, 2015

E

1.0

1.0

1.0

5

4

3

2

1

0.6Volt +/- 5%
TDC 0.7 A
Peak Current 1.0 A
OCP Current 2.6 A f i x by I C

+PWR_SRC

D D

+1.2V_MEN_P

For RT8207P

12

C C

PC220

B B

12

12

PC218

22U_0603_6.3V6M

22U_0603_6.3V6M

PJP202

PAD-OPEN 1x2m~D

12

PC217

PC216

22U_0603_6.3V6M

22U_0603_6.3V6M

12

21

1UH_11A_20%

1 2

12

PC215

22U_0603_6.3V6M

1.2V_B+

12

PL201

PC219

22U_0603_6.3V6M

PR202

1 2

2.2_0603_5%

12

12

PC201

PC202

@

10U_0805_25V6K

10U_0805_25V6K

12

PC203

PC204

0.1U_0402_25V6

2200P_0402_50V7K

@EMC@

@EMC@

12

PC205

0.22U_0603_16V7K

Footprint use AON6932A

7

12

PR204

4.7_1206_5%

@EMC@

SNUB_1.2V

12

PC211

680P_0603_50V7K

@EMC@

SIO_SLP_S4#<11,17,32,54>

PQ201

AON6932A_DFN5X6-8-7

S2

3

@

PR208

0_0402_5%

1 2

1D12

G1

S1/D2

S2

G26S2

4

5

PR205

1 2

5.1_0603_5%

+5V_ALW

S5_1.2V

12

PC214

@

.1U_040 2_16V7K

BOOT_1.2V

PR203

5.1K_0402_1%

1 2

1U_0603_10V6K

PC209

1U_0603_10V6K

DH_1.2V

SW_1.2V

DL_1.2V

PC207

VDD_1.2V

0.6V_DDR_VTT_ON<20>

CS_1.2V

12

+5V_ALW

1.2V_B+

PU201

15

LGATE

14

PGND

13

CS

12

VDDP

11

VDD

PR201

2.2_0603_5%

For RT8207P

1 2

453K_0402_1%

1 2

16

18

17

BOOT

PHASE

UGATE

RT8207PGQW_W QFN20_3X3

S5

PGOOD

TON

8

9

10

PR207

@

PR210

0_0402_5%

+VLDOIN_1.2V

20

19

VLDOIN

VTTGND

VTTSNS

VTTREF

S3

6

7

VTT

GND

VDDQ

FB

1.2V_FB

PAD

PJP203

1 2

PAD-OPEN1x1m

21

1

2

3

+V_DDR_REF

4

5

+1.2V_MEN_P

12

PC206

22U_0603_6.3V6M

+1.2V_MEN_P

FB sense trace
when FB pull down to GND

PR206

12K_0402_1%

1 2

PC212

100P_0402_50V8J

1 2

12

PR209
20K_0402_1%

12

PC213

@

.1U_040 2_16V7K

+0.6V_P

+V_DDR_REF

PC210

0.033U_0402_16V7K

Mode S3 S5 +1.2V_MEN +V_DDR_REF +0.6V_P

+1.2V_MEN_P

S5 L L of f off off
S3 L H on on of f
S0 H H on on on

+1.2V_MEM
TDC 7.35 A
Peak Current 8.82 A
OCP Current 10.6 A
TYP MAX
H/S Rds(on) 6.7mohm , 8.5mohm
L/S Rds(on) 2.4mohm , 3.2mohm

A A

Choke DCR 3.0mohm , 3.5mohm
CAP ESR 17mohm

5

+1.2V_MEN_P

4

@

PJP204

112

JUMP_1x3m

@

PJP201

112

JUMP_1x3m

2

2

+1.2V_MEM

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOS ED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+0.6V_P

3

FB sense trace

@

PJP205

1 2

PAD-OPEN1x1m

+0.6V_DDR_VTT

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

+1.2V_MEN/+0.6V_DDR_VTT

+1.2V_MEN/+0.6V_DDR_VTT

+1.2V_MEN/+0.6V_DDR_VTT

LA-C461P

LA-C461P

LA-C461P

44 61Tuesday, October 13, 2015

44 61Tuesday, October 13, 2015

44 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

4

3

2

1

D D

EN_+1VALWP

+PWR_SRC

C C

+3.3V_ALW

12

PR307

@

0_0402_5%

ILMT_ +1VAL WP

12

PR310

@

0_0402_5%

B B

@

PJP301

PAD-OPEN 1x2m~D

21

12

12

PC301

0.1U_0402_25V6

@EMC@

@EMC@

+1.0V_PRIM
TDC 4.3 A
Peak Current 6.0 A
OCP Current 8.0 A Fix by IC
TYP MAX
Choke DCR 11.0mohm , 12.0mohm

12

PC305

PC303

2200P_0402_50V7K

10U_0805_25V6K

+1VALWP_B+

12

PC306

@

10U_0805_25V6K

ILMT_ +1VAL WP

PU301

8

IN

EN

GND

ILMT

PG

BS

LX

FB

BYP

LDO

9

3

2

SYX196DQNC_QFN10_3X3

1

BST_+1VALWP

6

10

4

7

5

12

PC304

0.1U_0603_25V7K

1 2

SW_+1VALW P

12

PC312

PC313

4.7U_0603_6.3V6K

BST_+1VALWP_C

+3.3V_ALW

4.7U_0603_6.3V6K

12

1M_0402_1%
PR302

@

PR304

0_0603_5%

1 2

@EMC@

0.68UH +-20% 7.9A

FB_+1VALWP

@

PR312

0_0402_5%

1 2

@

PR301

0_0402_5%

1 2

PR303

4.7_1206_5%

1 2

PL301

1 2

@EMC@

SNB_+1VALWP

12

PR306

6.65K_0402_1%

12

PR311
10K_0402_1%

SIO_SLP_SUS# <8,11,18,32,41,46,47,53>

MPHYP_PWR_EN <11,18>

+1VALWP

PC302

680P_0603_50V7K

1 2

PR308

1K_0402_5%

12

PC307

12

330P_0402_50V7K

12

12

PC309

PC308

@

47U_0805_6.3V6M

47U_0805_6.3V6M

12

PC310

22UF_0805_6.3V6M

@

PJP302

112

JUMP_43X118

12

PC311

22UF_0805_6.3V6M

2

+1VALWP

+1.0V_PRIM

The current limit is set to 6A, 9A or 12A when this pin
is pull low, floating or pull high

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

2

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

+1VALWP

+1VALWP

+1VALWP

LA-C461P

LA-C461P

LA-C461P

45 61Tuesday, October 13, 2015

45 61Tuesday, October 13, 2015

45 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

4

3

2

1

+3.3V_ALW

PU401

PVIN

PVIN

AVIN

VID0

PR427

EN_1VS_VCCIO

13

EN

SY8057QDC QFN

VID1

8

12

12

14

PR404
0_0402_5%

LPM

7

SS_1VS_VCCIO

12

@

PJP401

@

JUMP_43X79

2

15

17

TP

PGND16PGND

1

VOS

2

SW

3

SW

4

PG

FBS5AGND6SS

PC410

470P_0402_50V7K

LX_1VS_VCCIO

+1VS_VCCIOP

PL402

1UH_1277AS-H-1R0N-P2_3.3A_30%

1 2

12

PR405

@EMC@

4.7_0603_5%

SNUB_1VS_VCCIO

12

PC401

@EMC@

470P_0402_50V7K

@

PR412

0_0402_5%

1 2

+1VS_VCCIOP

12

PR421

100_0402_1%

1 2

@

PR422

0_0402_5%

12

12

PC406

PC407

22U_0603_6.3V6M

22U_0603_6.3V6M

VCCIO_SENSE <17>

VSSIO_SENSE <17>

12

PC422

@

+1VS_VCCIOP

22U_0603_6.3V6M

+1VS_VCCIOP +1.0VS_VCCIO

+1.0VS_VCCIO
TDC 2.1 A
Peak Current 2.9 A
OCP Cur rent 4.2 A Fi x by IC
TYP MAX
Choke DCR 48.0mohm

112

@

PR425

PR402

PR403

1M_0402_1%

1 2

0_0402_5%

12

VIN_1VS_VCCIO

VID0_VCCIO

VID1_VCCIO

PC402

@

0.1U_0402_25V6

0_0402_5%

12

12

11

10

9

@

SIO_SLP_S0#<11,17,33,46>

@

0_0402_5%

RUN_ON<32,41,53>

D D

Vin=3~17V

+5V_ALW

+3.3V_ALW

@

PR413

10K_0402_1%

PR415

10K_0402_1%

12

10K_0402_1%

12

@

PR416

10K_0402_1%

PR414

VID0_VCCIO

VID1_VCCIO

12

12

C C

@

PJP403

1 2

PAD-OPEN1x1m

12

PC408

0.1U_0402_25V6

@EMC@

12

PC409

2200P_0402_50V7K

EMC@

1 2

12

12

PC404

PC403

10U_0603_10V6M

10U_0603_10V6M

"R" for SILERGY

+3.3V_ALW

PU402

PVIN

PVIN

AVIN

VID0

EN_1.0V_PRIM_COREP

13

EN

SY8057QDC QFN

VID1

8

VID1_PRIM_CORE

12

14

PR410
0_0402_5%

LPM

7

SS_1V_PRIM

12

@

15

PC420

12

470P_0402_50V7K

17

TP

PGND16PGND

FBS5AGND6SS

@

PR428

1M_0402_1%

PJP402

@

JUMP_43X79

2

+1.0V_PRIM_COREP +1.0V_PRIM_CORE

1

VOS

SW

SW

PG

+1.0V_PRIM_COREP

1UH_1277AS-H-1R0N-P2_3.3A_30%

LX_1V_PRIM

2

3

12

100K_0402_1%

12

SNUB_1V_PRIM

12

@

PR424

4

PL404

1 2

PR409

@EMC@

4.7_0603_5%

PC419

@EMC@

470P_0402_50V7K

@

PR423

0_0402_5%

1 2

Rup

+1.0V_PRIM_COREP

12

12

PC424

12

PC415

PC416

@

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

+1.0V_PRIM_ CORE
TDC 1.8 A
Peak Current 2.5 A
OCP Cur rent 4.2 A Fi x by IC
TYP MAX
Choke DCR 48.0mohm

112

@

PR426

@

PR406

0_0402_5%

PR407

1M_0402_1%

PR408

@

0_0402_5%

1 2

PR411

@

0_0402_5%

1 2

1 2

0_0402_5%

12

VIN_1V_PRIM

12

PC411

@

0.1U_0402_25V6

12

11

10

9

VID0_PRIM_CORE

"R" for SILERGY

SIO_SLP_S0#<11,17,33,46>

SIO_SLP_SUS#<8,11,18,32,41,45,47,53>

VID0_PRIM_CORE

VID1_PRIM_CORE

Vin=3~17V

+5V_ALW

@

PJP404

1 2

PAD-OPEN1x1m

12

PC417

0.1U_0402_25V6

@EMC@

CORE_VID0<18>

CORE_VID1<18>

12

PC418

2200P_0402_50V7K

EMC@

B B

+3.3V_ALW

12

10K_0402_1%

12

@

10K_0402_1%

A A

PR417

PR419

12

PR418

10K_0402_1%

12

PR420

@

10K_0402_1%

1 2

12

12

PC412

PC413

10U_0603_10V6M

10U_0603_10V6M

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Titl e

Titl e

THIS SHE ET OF ENGIN EERI NG DRAW ING IS THE P ROPR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

2

Titl e

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

+1VS_VCCIOP/+1.0V_PRIM_COREP

+1VS_VCCIOP/+1.0V_PRIM_COREP

+1VS_VCCIOP/+1.0V_PRIM_COREP

Document Number Rev

Document Number Rev

Document Number Rev

LA-C461P

LA-C461P

LA-C461P

1

46 61Tuesday, October 13, 2015

46 61Tuesday, October 13, 2015

46 61Tuesday, October 13, 2015

1.0

1.0

1.0

5

D D

4

3

2

PJP502

@

JUMP_43X79

+1.8VALWP

112

1

2

+1.8V_PRIM

PC502

22U_0603_6.3V6M

1 2

PJP501

@

JUMP_43X79

PR505

1M_0402_1%

112

12

+3.3V_ALW

@

PR504

0_0402_5%

SIO_SLP_SUS#<8,11,18,32,41,45,46,53>

C C

1 2

Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage

2

12

@

0.1U_0402_16V7K

VIN_1.8VALW

EN_1.8VALW

PC505

PU501

SY8032ABC_SOT23-6

4

IN

LX

5

PG

GND

FB6EN

3

2

1

LX_1.8VALW

Imax= 2A, Ipeak= 3A
FB=0.6V

PL501

1UH_1277AS-H-1R0N-P2_3.3A_30%

1 2

12

@EMC@

4.7_0603_5%

PR502

PR501

20K_0402_1%

12

Rup

FB_1.8VALW

SNUB_1.8VALW

12

@EMC@

680P_0402_50V7K

PC506

PR506

10K_0402_1%

12

Rdown

Vout=0.6V* (1+Rup/Rdown)

+1.8VALWP

12

PC503

68P_0402_50V8J

12

12

PC504

PC501

22U_0603_6.3V6M

22U_0603_6.3V6M

+1.8V_PRIM
TDC 0.7 A
Peak Current 1.0 A
OCP Cur rent 3.5A f i x by I C

+3.3V_RUN

+5V_ALW

PAD-OPEN1x1m

12

PC507
1U_0402_6.3V6K

B B

SIO_SLP_S3#<11,17,32>

+3.3V_RUN

47K_0402_5%

1 2

@

PR507

1 2

100K_0402_5%

47K_0402_5%

PR511

PR509

6

PU502

7

POK

8

EN

12

12

@EMC@

PC510

.1U_0402_16V7K

5

VIN

4

VOUT

VCNTL

3

VOUT

2

FB

9

VIN

GND

AP7175SP-13_SO-8EP-8

1

12

@

PJP503

+1.5V_VIN

12

PC508

4.7U_0805_6.3V6K

PR508

8.87K_0402_1%

12

12

PR510

10.2K_0402_1%

1.5VSP

12

0.01U_0402_25V7K

PC509

PAD-OPEN1x1m

12

PC511

22U_0805_6.3V6M

@

PJP504

1 2

+1.5V_RUN

+1.5V_RUN
TDC 0.4 A
Peak Current 0.6 A
OCP Cur rent 5.7 A f i x by I C

A A

Security Classification

Security Classification

Security Classification

Issued D ate

Issued D ate

Issued D ate

THIS SHE ET OF ENGIN EERI NG DRAW ING IS THE P ROPR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL

THIS SHE ET OF ENGIN EERI NG DRAW ING IS THE P ROPR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL

THIS SHE ET OF ENGIN EERI NG DRAW ING IS THE P ROPR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR W RITTEN CONSENT OF COM PAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR W RITTEN CONSENT OF COM PAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR W RITTEN CONSENT OF COM PAL ELECTRONICS, INC.

3

<Issued_Date>

<Issued_Date>

<Issued_Date>

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

<Deciphered_Date>

<Deciphered_Date>

<Deciphered_Date>

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Titl e

Titl e

Titl e

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C

C

C

Tuesday, October 13, 2015

Tuesday, October 13, 2015

Tuesday, October 13, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

SY8032

SY8032

SY8032

47 61

47 61

47 61

1.0

1.0

1.0

5

4

3

2

1

+1.0V_VCCST

@

PR602

12

12

Local sense put on HW site

PR613

90.9K_0402_1%

1 2

PC613
330P_0402_50V7K

1 2

@

1K_0402_1%

1 2

PR622

1 2

@

PR638

470_0402_1%

1 2

ISEN1_GT

@U22

1 2

@

PR606 0_0402_5%

1 2

@

PR607 0_0402_5%

1 2

@

PR609 0_0402_5%

PR621

PR623
2K_0402_1%

PC627

2200P_0402_50V7K

1 2

PR634

0_0402_5%

1 2

1 2

@U22

PR615

0_0402_5%

D D

H_PROCHOT#<12,32,50>

@

PR658

PH601

1 2

1 2

PR631

27.4K_0402_1%

2200P_0402_50V7K

@

1 2

330P_0402_50V7K

PC619

1 2

0.01U_0402_50V7K

12

1 2

12

PH602

10K_0402_5%_ERTJ0ER103J

470K_0402_5%_ TSM0B474J4702RE

VCC_GT_SENSE<16>

C C

VSS_GT_SENSE<16>

ISUMP_GT<49>

20M_0402_5%

ISUMN_GT<49>

B B

A A

PC614

1 2

PC618

PR628

@

PC641

2.61K_0402_1%~N

12

12

.1U_0402_16V7K

68P_0402_50V8J

1 2

PR633

@U23E

0.022U_0402_16V7K

@U23E

0.022U_0402_16V7K

1 2

1 2

PC605 47P_0402_50V8J~D

PR610
10K_0402_1%

1 2

PR617

4.3K_0402_1%

1 2

@

PC616

12

@

11K_0402_1%

PC635

1 2

PC638

ISEN2_GT

PC624

@

ISEN1_GT<49>

ISEN2_GT<49>

12

PC620

0.1U_0402_25V6

VIDSCLK<15>

VIDALERT_N<15>

VIDSOUT<15>

PR678

100_0402_1%

1 2

@

220P_0402_50V7K

1 2

PC621
680P_0402_50V7K

1 2

0.082U_0402_16V7K

12

PC626

0.047U_0402_25V7K

PC617

@

2.49K_0402_1%

1 2

PR632

1K_0402_1%

1 2

PR601

45.3_0402_1%

+3.3V_RUN

I_SYS<32, 50>

+5V_ALW

VCCSENSE<15>

VSSSENSE<15>

PCH_PWROK<11>

@

IMVP_VR_ON<32>

470K_0402_5%_ TSM0B474J4702RE

2200P_0402_50V7K

12

PR605

PR604

75_0402_1%

100_0402_1%

@

PR620 0_0402_5%

1 2

FCCM_GT<49>
PWM1_GT<49>
PWM2_GT<49>

PH603

1 2

27.4K_0402_1%

PR647

1 2

PC629

1 2

@

PC639

2200P_0402_50V7K

1 2

@

PR648

1 2

1.65K_0402_1%

PC651

@

1 2

330P_0402_50V7K

PC654

1 2

0.01U_0402_50V7K

12

PC602

0.1U_0402_25V6

1 2

1 2

@

PR625 0_0402_5%

1 2

1 2

1 2

@

PR614 0_0402_5%

1 2

@

PR616 0_0402_5%

PU602

1

PSYS

2

IMON_B

3

NTC_B

4

COMP_B

5

FB_B

6

RTN_B

7

ISUMP_B

8

ISUMN_B

9

ISEN1_B

10

ISEN2_B

41

AGND

PC625

330P_0402_50V7K

1 2

@

PR629

93.1K_0402_1%

1 2

1 2

PR635

10K_0402_1%

@

PR639

3.6K_0402_1%

1 2

PC636

33P_0402_50V8J

1 2

PR645

316_0402_1%

1 2

100K_0402_1%

48.7K_0402_1%

32

33

34

35

VIN

SDA

VCC

PROG231PROG1

PWM_C

FCCM_C
ISUMN_C
ISUMP_C

COMP_C

IMON_C
PWM_A

FCCM_A

FB_A

RTN_A18ISUMP_A19ISUMN_A

17

16

20

ISL95857HRTZ-T_TQFN40_5X5

FB_IA

4.42K_0402_1%

1 2

@

20M_0402_5%

12

PC603

1 2

@

PR608

1 2

PR611

RTN_C

FB_C

0.047U_0402_25V7K

PR657

PR653

ISUMP_IA <49>

PR61849.9_0402_1%

PR62610_0402_1%

PR6121.91K_0402_1%

36

37

38

39

40

SCLK

ALERT#

VR_HOT#

VR_READY

VR_ENABLE

FCCM_B11PWM1_B12PWM2_B13IMON_A14NTC_A15COMP_A

IMON_IA

NTC_IA

COMP_IA

12

2K_0402_1%

PR650

PC647

1 2

680P_0402_50V7K

12

PC653

@

0.082U_0402_16V7K

Local sense put on HW site

THIS S HEET OF ENGINEE RING D RAWING IS THE PROPR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0_0402_5%

1 2

@

PR603

0_0402_5%

1 2

12

PC604

1U_0603_10V6K

0.22U_0603_25V7K

PWM_VSA

30

FCCM_VSA

29
28
27
26

FB_VSA

25

COMP_VSA

24

IMON_VSA

23
22

PWM_IA <49>

21

FCCM_IA <49>

12

PC630

2200P_0402_50V7K

12

PR644

1K_0402_1%

PC642

0.033U_0402_16V7K

1 2

PC646

1 2

PR656

11K_0402_1%

1 2

PH605

10KB_0402_5%_ERTJ0ER103J

1 2

12

3

+5V_ALW

CPU_B+

PR619

1 2

2.2_0603_5%

1

PC611

1 2

12

10P_0402_50V8J

330P_0402_50V7K

PC643

PWM_VSA

12

@

1200P_0402_50V7K

PC631

PR651

82K_0402_1%

2

3

12

PR630

12

12

12

PR640

@

PC645

412_0402_1%

.1U_0402_16V7K

0.22U_0603_16V7K

PC628

12

ISUMN_IA <49>

DELL CONFIDENTIAL/PROPRIETARY

VCC_SA
TDC 3.7A
Peak Current 4.5A
OCP current 5.4A
Choke DCR 13 m ohm

PU606
ISL95808HRZ-TS2378_DFN8_2X2

UGATE

BOOT

PWM

GND4LGATE

8

PHASE

7

FCCM

6

VCC

5

TP

9

+5V_RUN

1 2

PC632
2200P_0402_25V7K

PR646

1 2

316_0402_1%

1 2

1.62K_0402_1%

PR652

2K_0402_1%

@U22

PC601

@U22

680P_0402_50V7K

2

1 2

PR636 1.24K_0402_1%

2200P_0402_50V7K

PR649

7.32K_0402_1%

12

12

PC685

12

1U_0402_10V6K

PC640

1 2

PJP603

VCCSA_B+ CPU_B+

1 2

PAD-OPEN1x1m

VCCSA_B+

12

12

PC612

PC608

@

10U_0805_25V6K

10U_0805_25V6K

AON7934_DFN3X3A-8-10

1

3

2

PQ501

D1

D1

D1

G1

SA_SW

9

S2

S2

S2

G2

6

7

8

Titl e

Titl e

Titl e

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

@EMC@

PR627

4.7_1206_5%

SA_SNUB

ISUMP_VSA

12

PC622

680P_0603_50V7K

@EMC@

12

12

PC637

0.033U_0402_16V7K

PC644

.1U_0402_16V7K

1 2

PC650

1 2

@

0.082U_0402_16V7K

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PWR_VCORE_ISL95812 for QC

PWR_VCORE_ISL95812 for QC

PWR_VCORE_ISL95812 for QC

LA-C461P

LA-C461P

LA-C461P

12

PR679

@

FCCM_VSA

0_0402_5%

1 2

PR641

1K_0402_1%

4

D110D2/S1

5

PL601

1UH +-20% 6.6A

1 2

12

PR624

3.65K_0603_1%

PC633

6800P_0402_25V7K

PC649

0.01U_0402_50V7K

1 2

@

330P_0402_50V7K

1 2

1

1 2

PC652

ISUMN_VSA

PR642

PR643

11K_0402_1%

+VCC_SA

ISUMP_VSA

12

1 2

2.61K_0402_1%

12

PH604

10KB_0402_5%_ERTJ0ER103J

ISUMN_VSA

VSA_SEN- <17>

VSA_SEN+ <17>

48 61Tuesday, October 13, 2015

48 61Tuesday, October 13, 2015

48 61Tuesday, October 13, 2015

PR654

@

20M_0402_5%

1.0

1.0

1.0

5

4

3

2

1

U23E

PR628 @U23E

PR651 @U23E

PR639 @U23E

PR621 @U23E

PR608 @U23E

PR648 @U23E

PR622 @U23E

1.65K +-1% 0402

PC617 @U23E

220P 50V 0402

PR648 @U22

1.37K +-1% 0402

PC617 @U22

1200P 50V 0402

21

CPU_B+GPU_B+

@U23E

PR667

3.65K_0603_1%

1 2

ISEN2_GT<48>

GT1N

ISUMP_GT

Titl e

Titl e

Titl e

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

2.49K +-1% 0402

PC639 @U23E

2200P 50V 0402

PR622 @U22

1.96K +-1% 0402

PC639 @U22

1500P 50V K 0402

VCC_GT (GT+GTUS)
TDC 36A
Peak Current 66A
OCP current 79A
Choke DCR 0.9 +-7%m ohm

@U23E

PL604

0.15UH_MMD06CZER15MG_37A_20%

1

4

3

2

GT2P

@U23E

PR668

100K_0603_1%

1 2

PR670

@

1 2

100K_0402_1%

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PWR_VCORE_ISL95812 for QC

PWR_VCORE_ISL95812 for QC

PWR_VCORE_ISL95812 for QC

LA-C461P

LA-C461P

LA-C461P

12

GT2N

@U23E

10_0402_1%

ISUMN_GT

1

+VCC_GT

PR666

<48,49>

1.0

1.0

49 61Tuesday, October 13, 2015

49 61Tuesday, October 13, 2015

49 61Tuesday, October 13, 2015

1.0

PJP602

@

PAD-OPEN 1x2m~D

@EMC@

PR669

<48,49>

+5V_RUN

PC670

@EMC@

100K +-1% 0402

PC616 @U23E

68P 50V J 0402

PR608 @U22

78.7K +-1% 0402

PC616 @U22

33P 50V J 0402

12

4.7_1206_5%

GT_SNUB2

12

680P_0603_50V7K

<48,49>

PU604

VSW

PGND1

SKIP#

VDD

3.6K +-1% 0402

PR629 @U23E

93.1K +-1% 0402

PR639 @U22

5.49K +-1% 0402

PR629 @U22

88.7K +-1% 0402

4
3
2
1

12

PR664

@

0_0402_5%

FCCM_GT

PC669

@U23E

1K +-1% 0402

PC624 @U23E

0.1U 25V 0402

PR621 @U22

316 +-1% 0402

PC624 @U22

.033U 16V 0402

GT_SW2

12

1U_0402_10V6K

2

2.61K +-1% 0402

PR640 @U23E

D D

+PWR_SRC

@

PJP601

12

2200P_0402_50V7K

PGND2
PWM
BOOT

BOOT_R
VIN

1

+

PC606

2

@

100U_D_20VM_R55M

PU603

VSW

PGND1

VDD

SKIP#

<48>

1 2

PAD-OPEN 4x4m

PL602

@EMC@

1 2

FBMA-L11-453215800LMA90T_2P

4
3
2
1

PR659

@

0_0402_5%

FCCM_IA

12

CORE_SW

12

PC661

1U_0402_10V6K

CPU_B+

@EMC@

12

12

PC656

10U_0805_25V6K

PWM_IA<48>

C C

12

PC686

10P_0402_50V8J

PC657

PR662

5.11K_0402_1%

10U_0805_25V6K

0.22U_0603_16V7K

12

PC658

2.2_0603_5%

12

PC659

10U_0805_25V6K

0.1U_0402_25V6K~D

PC655

1 2

1 2

PR660

12

PC680
1000P_0402_50V7K

12

@EMC@

PC660

9
8
7

6
5

CSD97374CQ4M_SON8_3P5X4 P5

GPU_B+

B B

12

12

PC673

PC672

@

10U_0805_25V6K

10U_0805_25V6K

PU605

9

PGND2

8

12

PR680

5.11K_0402_1%

5

PC671

1 2

0.22U_0603_16V7K

1 2

PR672

2.2_0603_5%

12

PC679
1000P_0402_50V7K

PWM

7

BOOT

6

BOOT_R

5

VIN

CSD97374CQ4M_SON8_3P5X4 P5

<48,49>

VSW

PGND1

SKIP#

VDD

4
3
2
1

PR671

@

0_0402_5%

FCCM_GT

12

12

PC677

PWM1_GT<48>

12

PC688

10P_0402_50V8J

A A

VCC_core
TDC 21A
Peak Current 28A
OCP current 34A
Choke DCR 0.9 +-7%m ohm

0.15UH_MMD06CZER15MG_37A_20%

4

3

12

@EMC@

12

PR661

4.7_1206_5%

CORE_SNUB

12

12

@EMC@

PR676

4.7_1206_5%

GT_SNUB1

12

4

PC662

680P_0603_50V7K

@EMC@

PC678

@EMC@

3.65K_0603_1%

ISUMP_IA

3.65K_0603_1%

1 2

ISEN1_GT<48>

ISUMP_GT

680P_0603_50V7K

+5V_RUN

GT_SW1

1U_0402_10V6K

PR663

+5V_RUN

PL603

1

2

<48>

ISUMN_IA

0.15UH_MMD06CZER15MG_37A_20%

4

3

GT1P

GT2N

<48,49>

@U23E

100K_0603_1%

1 2

@

100K_0402_1%

PR674

+VCC_CORE

<48>

PL605

1

2

PR675

PR677

12

PC664

@U23E

PWM2_GT<48>

12

PC687

@U23E

+VCC_GT

GT1N

12

PR673
10_0402_1%

<48,49>

ISUMN_GT

THIS S HEET OF ENGINEE RING D RAWING IS THE PROPR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

412 +-1% 0402

U22

PR628 @U22

4.42K +-1% 0402

PR640 @U22

340 +-1% 0402

GPU_B+

12

12

PC665

@

10U_0805_25V6K

10U_0805_25V6K

@U23E

1 2

0.22U_0603_16V7K

1 2

2.2_0603_5%

12

12

PR681

10P_0402_50V8J

@U23E

5.11K_0402_1%

DELL CONFIDENTIAL/PROPRIETARY

9

PC663

8
7

6
5

PR665

@U23E

CSD97374CQ4M_SON8_3P5X 4P5

@U23E

PC681

1000P_0402_50V7K

82K +-1% 0402

PR638 @U23E

470 +-1% 0402

PR651 @U22

133K +-1% 0402

PR638 @U22

374 +-1% 0402

@U23E

PGND2
PWM
BOOT

BOOT_R
VIN

A

PQ802

SI4835DDY-T1-GE3_SO 8

8

PR801

100K_0402_1%

13

D

PQ809
L2N7002WT1G_SC70-3

S

PR817

154K_0402_1%

7

5

BQ24770_REGN

12

12

+DC_IN_SS

1 1

CHARGER_SM BCLK
CHARGER_SM BDAT
pull up 10K in HW side (R827 R828)

2 2

ACAV_IN<32,51>

AC_DIS<31,42,51>

12

PR837

1M_0402_1%

PR827

1K_0402_5%

PR829

@

154K_0402_1%

2

G

BQ24770_REGN

12

12

1
2
36

4

PR803

1 2

0_0402_5%

I_ADP<32>

I_BATT<32>

I_SYS<32,48>

H_PROCHOT#<12,32,48>

PBAT_PRES#<32,42,51>

AC Det
Max:16.82V
Typ :1 6.54 V
Min :16.26V

6.49K_0402_1%

CHARGER_SMBDAT<32>

CHARGER_SMBCLK<32>

@

PR816 0_0402_5%

1 2

@

PR819 0_0402_5%

1 2

@

PR820 0_0402_5%

1 2

DC_BLOCK_GC <51>

+DOCK_PWR_BAR

+SDC_IN

PR812

34K_0402_1%

PR813

1 2

12

PC815

12

0.1U_0402_25V6

PC823

PC824

1 2

1 2

100P_0402_50V8J

100P_0402_50V8J

@

PR828

0_0402_5%

1 2

CSS_GC<51>

SDMK0340L-7-F_SOD323- 2~D

+DC_IN_SS

SDMK0340L-7-F_SOD323- 2~D

SDMK0340L-7-F_SOD323- 2~D

PR822

31.6K_0402_1%

1 2

B

@

PR804

1 2

0_0402_5%

PD802

PD801

PD803

10_1206_5%

PC814

10U_0805_25V6K

1 2

@

PR836 0 _0402_5%

1 2

@

PR835 0 _0402_5%

1 2

@

PR815 0 _0402_5%

PR818 100_0402_1%

/BATPRES<51>

12

12

12

PR811

12

1 2

@

12

PC802

0.1U_0603_25V7K

PQ801

DMP3056L-7 1P SOT23-3

@

0_0402_5%

PC808

12

1U_0603_25V6K

1 2

28

+DCIN

3

6

11

12

5

7

8

9

10

13

CMPIN

14

CMPOUT

15

16

29

PR802

0.01_1206_1%

4

3

13

D

2

G

S

PR805

CSSP_1

100_0402_1%

12

PR806

@

0_0402_5%

PC809

0.1U_0402_25V6

1 2

4

2

PU801

ACP

VCC

ACDRV

CMSRC

ACDET

SDA

SCL

ACOK

IADP

IDCHG

ISYS

/PROCHOT

CMPIN

CMPOUT

/BATPRES

CELL

PWPD

BQ24777RUYR_WQFN28_4x4

2

G

12

PR807

0.1U_0402_25V6

1

ACN

REGN

BTST

HIDRV

PHASE

LODRV

GND

SRN

/BATDRV

1

2

13

D

PQ803
DMP3056L-7 1P SOT23-3

S

CSSN_1

12

1 2

PC810

24

2.2_0603_5%

1 2

25

26

27

23

22

21

1 2

NC

10K_0402_1%

20

SRP

19

18

17

BAT

PQ804

DMP3056L-7 1P SOT23-3

S

G

2

12

PR808

100K_0402_1%

BQ24770_REGN

PC821

PR814

0.047U_0603_16V7K

PR821

PR825

4.02K_0402_1%

1 2

1 2

PR826

10_0603_1%

1 2

PC828

1U_0603_25V6K

EMC@

1UH +-20% 6.6A

D

13

PQ805

DMP3056L-7 1P SOT23-3

S

G

12

PR809

100K_0402_1%

12

CHG_LGATE

BQ24770_REGN

C

PL802

@

PJP801

1 2

PAD-OPEN 4x4m

D

13

2

@

PR810

0_0402_5%

1 2

PC813

1 2

1U_0603_10V6K

CHG_UGATE

CHG_SW

12

CHAGER_SRC+PWR_SRC_AC+SDC_IN

DOCK_DCIN_IS+ <38>

DOCK_DCIN_IS- <38>

DK_CSS_GC <51>

7

1D12

G1

S1/D2

S2

G26S2

S2

4

5

3

PC817

@EMC@

PQ808

AON6992 2N DFN5X6D

PR824

1 2

4.7_1206_5%

@EMC@

CHG_SNUB

12

PC832

1000P_0603_50V7K

@EMC@

TYP MAX
H/S Rds(on) 7. 4mohm , 8.8mohm
L/S Rds(on) 2.6mohm , 3.1mohm
Choke DCR 5.8mohm , 7.0mohm

12

12

0.1U_0402_25V6

12

12

PC816

PC818

22U_0805_25V6M

2200P_0402_50V7K

@EMC@

12

PC819

PC820

PC822

22U_0805_25V6M

22U_0805_25V6M

+PWR_SRC

PL801

3.3UH_10A_20%

PC829

0.1U_0402_25V6

1 2

12

PR823

0.01_1206_1%

4

3

PC830

0.1U_0402_25V6

1 2

1

2

12

22U_0805_25V6M

PC831

@

0.1U_0402_25V6

1 2

D

+VCHGR

Near PL701

+PWR_SRC

12

12

PC803

PC804

10U_0805_25V6K

10U_0805_25V6K

+PWR_SRC+PWR_SRC

12

12

PC812

PC835

10U_0805_25V6K

22U_0805_25V6M

@EMC@

12

12

PC825

PC826

10U_0805_25V6K

0.1U_0603_25V7K

@EMC@

12

PC806

10U_0805_25V6K

12

PC836

0.1U_0402_25V6

RF require

12

PC827

10U_0805_25V6K

12

PC807

10U_0805_25V6K

12

PC805

10U_0805_25V6K

12

PC811

22U_0805_25V6M

@EMC@

12

PC801

10U_0805_25V6K

@

3 3

+DC_IN

12

PR830

649K_0402_1%

PR831

100K_0402_1%

1 2

@

ACAV_IN_NB<32,51>

PR833

1 2

0_0402_5%

PR832

3M_0402_5%

12

PR834
10K_0402_1%

12

100P_0402_50V8J

PC833

12

CMPIN

CMPOUT

PC834

100P_0402_50V8J

1 2

BATDRV# <51>

+3.3V_ALW

4 4

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Titl e

Titl e

THIS SHE ET OF ENGIN EERI NG DRAW ING IS THE P ROPR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR W RITTEN CONSENT OF COM PAL ELECTRONICS, INC.

C

Titl e

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Charger

Charger

Charger

Document Number Rev

Document Number Rev

Document Number Rev

LA-C461P

LA-C461P

LA-C461P

D

50 61Tuesday, October 13, 2015

50 61Tuesday, October 13, 2015

50 61Tuesday, October 13, 2015

1.0

1.0

1.0

5

PD902

D D

C C

ACAVIN
P33ALW2

1
2
3
4
5
6
7
8
9

37

DK_CSS_GC<50>

PR935
100_0603_1%

1 2

PU901

DC_IN
SS_GC
ERC1
ACAVDK_SRC
GND
SDC_IN
DC_BLK_GC
ACAV_IN
P33ALW2

TP

CSS_GC<50>

PC907

0.047U_0603_25V7M

ERC3

12

B B

PR921

ACAV_IN<32,50,51>

PR920

SOFT_START_GC<42>

1 2

100K_0402_5%

DC_BLOCK_GC<50>

1 2

47_0805_5%~D

0.1U_0603_25V7K

PR928
100_0603_1%

1 2

@

PR918

1 2

0_0402_5%

@

PR932

1 2

0_0402_5%

+DC_IN

+3.3V_ALW2

ACAV_DOCK_ SRC#<38>

+SDC_IN

+3.3V_ALW2

A A

PC906

@

PR923
0_0402_5%

1 2

5

+DC_IN_SS

CD3301_DCIN

12

ACAVDK_SRCACAVDK_SRC

12

PC908

0.1U_0603_25V7K

ERC1

+VCHGR

+3.3V_ALW

DK_PWRBAR

DC_IN_SS

33

34

35

36

NC

DC_IN_SS

DK_PWRBAR

CHARGERVR_DCIN

CSS_GC10DK_CSS_GC11ERC312ERC213GND14PWR_SRC

ERC2

12

PC901

@

0.1U_0402_25V4Z~D

PDS5100H-13_POWERDI5-3

SI4835DDY-T1-GE3_SO 8

BATDRV#<50>

28

29

30NC31

32

GND

PBatt+

PBATT_OFF

BLK_MOSFET_GC

DK_AC_OFF_EN

ACAV_IN_NB

DSCHRG_MOSFET_GC

DK_AC_OFF_EN

SL_BAT_PRES#

BLKNG_MOSFET_GC

NBDK_DCINSS

SS_DCBLK_GC

EN_DK_PWRBAR17P33ALW

16

15

18

P33ALW

EN_DK_PWRBAR

STSTART_DCBLOCK_GC

3301_PWRSRC

1

PQ903

1
2
3 6

4

0_0402_5%

1 2

AC_DIS<31,42,50>

PR924
100_0603_1%

1 2

PR933

100_0603_1%

1 2

27

P50ALW

26
25
24
23

GND

22
21
20
19

CD3301BRHHR_QFN36_6X6~D

@

PR931

1 2

0_0402_5%

PR939
100_0603_1%

1 2

+PBATT

3

2

8
7

5

@

PR913

PR915

100K_0402_5%

PR916

1 2

10K_0402_5%

+DOCK_PWR_BAR

+PBATT

@

PR937
0_0402_5%

1 2

P50ALW

@

PR930

1 2

CD_PBATT_OFF

0_0402_5%

DK_AC_OFF

DK_AC_OFF_ENCD3301_SDC_IN
SL_BAT_PRES#

+3.3V_ALW

PR934

1 2

1M_0402_5%

4

LP2301ALT1G_SOT23-3

12

13

D

PQ906

2

G

L2N7002WT1G_SC70-3

S

+5V_ALW

SLICE_BAT_ON <31>

3301_ACAV_IN_NB

@

PR938 0_0402_5%

@

PR926

0_0402_5%

1 2

@

PR927

0_0402_5%

1 2

+PWR_SRC_AC

4

PQ909

S

G

2

@

0_0402_5%

1 2

1 2

PR922

D

13

@

+DOCK_PWR_BAR

S TR DMN65D8LDW-7 2N SOT363-6

PD901

2

1

3

BAT54CW_SOT323-3

PR929

1 2

1M_0402_5%

SLICE_BAT_PRES# <31,38,42>

+NBDOCK_DC_IN_SS

1 2

PR901 0_0402_5%

PDS5100H-13_POWERDI5-3

S TR DMN65D8LDW-7 2N SOT363-6

PQ911B

4

5

12

@

PR919

0_0402_5%

DOCK_DET#<31,38,51>

DOCK_AC_OFF <38>

12

PR925

10K_0402_5%

ACAV_IN_NB <32, 50>

DOCK_AC_OFF_EC <31>

EN_DOCK_PWR_BAR <31>

PD903

FDS6679AZ-G_SO8

PQ911A

2

3

100K_0402_5%

+PWR_SRC_AC

1

2

3

PQ901

SDMK0340L-7-F_SOD323-2~D

PR936

12

61

100K_0402_5%

PR917

12

+3.3V_ALW2

3

PC902

1 2

0.47U_0805_25V6K

36

241

PQ904
FDS6679AZ-G_SO8

578

330K_0402_5%

5

PQ905

AON7401 1P DFN 3*3

4

123

1500P_0402_50V7K

36

241

578

PD904

PR911

1 2

100K_0402_5%

3

PR908

2

G

@

PR906

1 2

0_0402_5%

12

@

12

PC904

12

13

D

PQ910
DMP3099L-7_SOT23-3

S

STSTART_DCBLOCK_GC

PR910

1 2

12

PR912

13

D

PQ908

S

L2N7002WT1G_SC70-3

PD905

1

BAT54CW_SOT323-3

Purpose: Trigger PROCHOT# when
active battery is removed from
system.
Allows EC to re-establish
system performance for battery
next in line.

+3.3V_ALW

12

DIS_BAT_PROCHOT#<31>

100K_0402_5%

10K_0402_5%

2

G

TC7SH08FU_SSO P5~D

Vth=0.5-1.5V

3

+DC_IN_SS

2

+NBDOCK_DC_IN_SS

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

PR905
100K_0402_5%

+3.3V_ALW2

PU903

4

O

PBAT_PRES#<32,42,50>

PC905

0.1U_0402_10V7K

5

1

P

B

2

A

G

3

2

1

+3.3V_ALW

12

PR903
100K_0402_5%

PQ902B

5

61

S TR DMN65D8LDW-7 2N SOT363-6

+3.3V_ALW2

DOCK_DET# <31,38,51>

12

PR902
100K_0402_5%

PR904

@

0_0402_5%

1 2

3

4

S TR DMN65D8LDW-7 2N SOT363-6

Purpose: Turn on the PQ817
for primary or module bay
battery to provide power to
dock side without AC exist.

/BATPRES <50>

0_0402_5%

1 2

12

@

PR907

PC903

0.1U_0402_10V7K

1 2

ACAV_IN#

+3.3V_ALW

5

1

P

B

O

2

A

G

PU902

3

TC7SH08FU_SSO P5~D

1 2

100K_0402_5%

61

S TR DMN65D8LDW-7 2N SOT363-6

2

4

PR909

PQ907A

+3.3V_ALW

PQ902A

2

+3.3V_ALW2

12

PR914

100K_0402_5%

ACAV_IN#

3

PQ907B

ACAV_IN<32,50,51>

5

4

S TR DMN65D8LDW-7 2N SOT363-6

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Titl e

Titl e

Titl e

Size

Size

Size

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Selector

Selector

Selector

Document Number Rev

Document Number Rev

Document Number Rev

LA-C461P

LA-C461P

LA-C461P

1

51 61Tuesday, October 13, 2015

51 61Tuesday, October 13, 2015

51 61Tuesday, October 13, 2015

1.0

1.0

1.0

A

VCC_CORE Place on CPU
Back Side.
22U_0603 * 13 pcs +1U_0201*35 pcs
Primary Side.
22U_0603 * 20 pcs+330u_D2*2 pcs

B

C

VCC_GT Place on CPU (U23E)
Back Side.
22U_0603 * 23 pcs +1U_0201*12 pcs
Primary Side.
22U_0603 * 13 pcs +330u_D2*4 pcs

+VCC_CORE +VCC_GT

D

VCC_GT Place on CPU (U22)
Back Side.
22U_0603 * 13 pcs +1U_0201*12 pcs
Primary Side.
22U_0603 * 13 pcs +330u_D2*2 pcs

E

1 1

2 2

3 3

1

2

12

12

330U_D2_2.5VM_R9M

1

+

2

1

1

PC1078

PC1076

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1081

2

2

22U_0603_6.3V6M

12

12

PC1083

PC1030

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1099

PC1095

1U_0201_6.3V6M

1U_0201_6.3V6M

330U_D2_2.5VM_R9M

1

PC1127

PC1062

12

+

2

1

1

PC1077

2

22U_0603_6.3V6M

1

PC1080

2

22U_0603_6.3V6M

12

PC1031

1U_0201_6.3V6M

12

PC1094

1U_0201_6.3V6M

12

PC1170

@

22U_0603_6.3V6M

1

PC1001

PC1079

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1067

PC1082

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1032

PC1033

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1090

PC1096

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1171

PC1172

@

@

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1003

PC1002

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1072

PC1069

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1035

PC1034

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1093

PC1091

1U_0201_6.3V6M

1U_0201_6.3V6M

12

PC1174

PC1173

@

@

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1004

PC1005

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1070

PC1074

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1037

PC1036

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1097

PC1092

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

PC1006

PC1007

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1061

PC1071

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1038

PC1039

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1098

PC1050

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

PC1008

PC1009

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1073

PC1066

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1086

PC1084

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1052

PC1051

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

PC1010

2

22U_0603_6.3V6M

1

PC1068

2

22U_0603_6.3V6M

12

PC1085

1U_0201_6.3V6M

12

PC1053

1U_0201_6.3V6M

1

PC1012

PC1011

22U_0603_6.3V6M

PC1075

22U_0603_6.3V6M

PC1088

1U_0201_6.3V6M

PC1054

1U_0201_6.3V6M

PC1013

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1065

PC1064

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1089

PC1087

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

12

PC1126

1U_0201_6.3V6M

PC1125

PC1164

1U_0201_6.3V6M

1U_0201_6.3V6M

1

+

2

@U23E

1

2

@U23E

1

2

12

330U_D2_2.5VM_R9M

330U_D2_2.5VM_R9M

1

PC1128

+

2

@U23E

+VCC_SA

VCC_SA Place on CPU
Back Side.
22U_0603 * 4 pcs + 1U_0201*7 pcs
Primary Side.
22U_0603 * 8 pcs

1

1

PC1014

2

@U23E

22U_0603_6.3V6M

1

PC1133

2

@U23E

22U_0603_6.3V6M

12

PC1040

1U_0201_6.3V6M

330U_D2_2.5VM_R9M

1

PC1063

+

2

1

PC1016

PC1015

2

2

@U23E

@U23E

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1137

PC1129

2

2

@U23E

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1042

PC1041

1U_0201_6.3V6M

1U_0201_6.3V6M

330U_D2_2.5VM_R9M

1

PC1101

PC1100

12

+

2

1

PC1057

2

22U_0603_6.3V6M

1

1

1

PC1017

PC1018

2

2

@U23E

@U23E

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1136

PC1132

2

2

@U23E

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1044

PC1043

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1180

PC1181

@U23E

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1059

PC1058

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

PC1019

PC1020

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1134

PC1135

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1045

PC1046

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1179

PC1177

@U23E

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1060

PC1139

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1021

PC1022

2

2

@U23E

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1027

PC1138

2

2

@U23E

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1047

PC1048

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1178

PC1176

@U23E

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1141

PC1140

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1023

2

22U_0603_6.3V6M

1

PC1028

2

22U_0603_6.3V6M

12

PC1049

1U_0201_6.3V6M

12

PC1175

22U_0603_6.3V6M

1

PC1142

2

22U_0603_6.3V6M

1

PC1025

12

12

@U23E

@U23E

PC1143

PC1026

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1029

PC1131

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

PC1056

1U_0201_6.3V6M

12

PC1183

PC1184

@U23E

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

22U_0603_6.3V6M

1

PC1145

PC1144

22U_0603_6.3V6M

PC1146

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

PC1024

22U_0603_6.3V6M

PC1130

22U_0603_6.3V6M

PC1055

1U_0201_6.3V6M

PC1182

22U_0603_6.3V6M

1

2

+VCC_GT

1

2

@U23E

1

1

1

PC1222

PC1221

2

2

@U23E

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1223

PC1224

2

2

@U23E

22U_0603_6.3V6M

22U_0603_6.3V6M

1

PC1162

PC1158

2

2

@U23E

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1154

PC1159

2

2

@U23E

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PC1161

2

22U_0603_6.3V6M

1

PC1155

PC1163

22U_0603_6.3V6M

PC1156

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

12

PC1147

PC1153

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1148

PC1149

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1150

1U_0201_6.3V6M

PC1152

PC1151

1U_0201_6.3V6M

1U_0201_6.3V6M

4 4

A

Merged VR
VCC_GTX Place on CPU
22U_0603 * 12 pcs

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

For GTX

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR DECOUPLING

PROCESSOR DECOUPLING

PROCESSOR DECOUPLING

LA-C461P

LA-C461P

LA-C461P

52 61Tuesday, October 13, 2015

52 61Tuesday, October 13, 2015

52 61Tuesday, October 13, 2015

E

1.0

1.0

1.0

5

4

3

2

1

+3.3V_ALW

LPM_ZVM_N<13,53>

@

PR1200

0_0402_5%

RUN_ON<32,41,46>

D D

Vin=3~17V

+PWR_SRC

+3.3V_ALW

PR1205
10K_0402_1%

@

PR1207

10K_0402_1%

@U23E

12

@

PR1203

10K_0402_1%

12

PR1208
10K_0402_1%

VID0_EDRAM_VR

VID1_EDRAM_VR

@U23E

12

12

C C

@

PJP1202

1 2

PAD-OPEN1x1m

PC1208

@EMC@

12

12

PC1209

0.1U_0402_25V6
2200P_0402_50V7K

@U23E

1 2

@U23E

PR1202

1M_0402_1%

12

12

PC1202

PC1201

10U_0603_25V6M

10U_0603_25V6M

@U23E

@U23E

12

VIN_VCC_EDRAM

VID0_EDRAM_VR

VID1_EDRAM_VR

@

PR1222

0_0402_5%

PC1200

@

0.1U_0402_25V6

12

11

10

12

9

12

EN_VCC_EDRAM

@U23E

13

PU1200

EN

PVIN

PVIN

TPS62134CRGT_QFN16_3X3

AVIN

VID0

VID1

8

12

14

PR1201
0_0402_5%

LPM

7

SS_VCC_EDRAM

12

@U23E

@

PJP1200

JUMP_43X79

2

15

17

TP

PGND16PGND

1

VOS

2

SW

3

SW

4

PG

FBS5AGND6SS

PC1211

470P_0402_50V7K

LX_VCC_EDRAM

+VCC_EDRAM_P

@U23E

PL1200

1UH_1277AS-H-1R0N-P2_3.3A_30%

1 2

12

@EMC@

PR1204

4.7_0603_5%

SNUB_VCC_EDRAM

12

@EMC@

PC1210

470P_0402_50V7K

0_0402_5%

1 2

+VCC_EDRAM_P

12

@U23E

PR1206

100_0402_1%

1 2

@

PR1210

@

PR1209

0_0402_5%

12

PC1203

@U23E

VCC_EDRAM_SENSE <15>

VSS_EDRAM_SENSE <15>

12

12

PC1204

22U_0603_6.3V6M

22U_0603_6.3V6M

@U23E

+VCC_EDRAM_P

PC1205

@

22U_0603_6.3V6M

+VCC_EDRAM_P +VCC_EDRAM

+VCC_EDRAM
TDC 2.1 A
Peak Current 2.9 A
OCP Cur rent 4.2 A Fi x by IC
TYP MAX
Choke DCR 48.0mohm

112

+3.3V_ALW

12

PR1211

LPM_ZVM_N<13,53>

@

PR1212

0_0402_5%

SIO_SLP_SUS#<8,11,18,32,41,45,46,47>

MSM_N <13>

VID0_EOPIO_VR

VID1_EOPIO_VR

@U23E

Vin=3~17V

+PWR_SRC

@

PJP1203

1 2

PAD-OPEN1x1m

12

PC1217

0.1U_0402_25V6

@EMC@

12

PC1218

2200P_0402_50V7K

@U23E

B B

12

PR1214
10K_0402_1%

12

@

10K_0402_1%

A A

PR1217

@U23E

12

@

10K_0402_1%

12

PR1218
10K_0402_1%

PR1215

1 2

@U23E

PR1213

1M_0402_1%

VIN_VCC_EOPIO

12

12

PC1213

PC1214

10U_0603_25V6M

10U_0603_25V6M

@U23E

@U23E

12

VID0_EOPIO_VR

VID1_EOPIO_VR

@

PR1223

0_0402_5%

PC1212

@

0.1U_0402_25V6

12

11

10

12

12

@U23E

PU1201

PVIN

PVIN

AVIN

9

VID0

0_0402_5%

EN_VCC_EOPIO

13

15

14

EN

LPM

TPS62134CRGT_QFN16_3X3

VID1

8

7

SS_VCC_EOPIO

12

@U23E

PC1220

470P_0402_50V7K

@

PJP1201

JUMP_43X79

17

TP

PGND16PGND

1

VOS

SW

SW

PG

FBS5AGND6SS

2

3

4

LX_VCC_EOPIO

+VCC_EOPIO_P

@U23E

PL1201

1UH_1277AS-H-1R0N-P2_3.3A_30%

1 2

12

@EMC@

PR1216

4.7_0603_5%

SNUB_VCC_EOPIO

12

@EMC@

PC1219

470P_0402_50V7K

@

0_0402_5%

1 2

Rup

PR1221

+VCC_EOPIO_P

12

@U23E

@

PR1219

100_0402_1%

0_0402_5%

1 2

PR1220

12

12

PC1215

22U_0603_6.3V6M

@U23E

VCCEOPIO_SENSE <15>

VSSEOPIO_SENSE <15 >

12

PC1216

@

22U_0603_6.3V6M

@U23E

+VCC_EOPIO_P

PC1225

22U_0603_6.3V6M

+VCC_EOPIO_P +VCC_EOPIO

+VCC_EOPI O
TDC 1.8 A
Peak Current 2.5 A
OCP Cur rent 4.2 A Fi x by IC
TYP MAX
Choke DCR 48.0mohm

112

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Titl e

Titl e

THIS SHE ET OF ENGIN EERI NG DRAW ING IS THE P ROPR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

2

Titl e

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PWR-VCCEDRAM/EOPIO

PWR-VCCEDRAM/EOPIO

PWR-VCCEDRAM/EOPIO

Document Number Rev

Document Number Rev

Document Number Rev

LA-C461P

LA-C461P

LA-C461P

1

53 61Tuesday, October 13, 2015

53 61Tuesday, October 13, 2015

53 61Tuesday, October 13, 2015

1.0

1.0

1.0

A

1 1

B

C

D

+3.3V_ALW

+5V_ALW

PAD-OPEN1x1m

12

2 2

PU1500

7

POK

PR1500

SIO_SLP_S4#<11,17,32,44>

3 3

1 2

100K_0402_5%

@

47K_0402_5%

12

PR1502

12

PC1504

.1U_0402_1 6V7K

8

EN

@EMC@

PC1500

1U_0402_6.3V6K

6

5

VIN

4

VOUT

VCNTL

3

VOUT

2

FB

9

VIN

GND

1

AP7175SP-13_SO-8EP-8

PJP1501

12

+2.5V_VIN

12

21.5K_0402_1%

PC1501

4.7U_0805_6.3V6K

12

PR1501

12

2.5VSP

PR1503

10.2K_0402_1%

12

PC1502

0.01U_0402_25V7K

1 2

PAD-OPEN1x1m

12

PC1503

22U_0805_6.3V6M

PJP1500

+2.5V_MEM
TDC 0.45 A
Peak Current 0.6 A
OCP Current 5.7 A f i x by I C

+2.5V_MEM

4 4

Compal Electronics, Inc.

Compal Electronics, Inc.

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

+2.5V_MEM

+2.5V_MEM

+2.5V_MEM

LA-C461P

LA-C461P

LA-C461P

D

54 61Tuesday, October 13, 2015

54 61Tuesday, October 13, 2015

54 61Tuesday, October 13, 2015

1.0

1.0

1.0

5

Timing Diagram for S5 to S0 mode

D D

5

C C

VCCST_PWR GD

12

H_CPUPWRGD

15

PCH_PLTRST#

17

0.675V_DDR _VTT_ ON

12

+1.0V_P RIM_CORE

+1.8V_PR IM

5

CPU

VCCST_PWR GD

PROCPWR GD

PLTRST#

DDR_VTT_CNTL

+PWR_SRC

TLV62130

+3.3V_ALW

TLV62130

VCC

VCCIO

VCCGT

VDDQ
VDDQC
VCCPLL_OC

VCCST
VCCSTG
VCCPLL

VCCSA

SIO_SLP_SUS#

4

6

+1.0V_PR IM SYX1 98

+VCC_CORE

+1.0VS_ VCCIO

+VCC_GT

+1.35V_ME M

+1.0V_VCCST

10

+VCC_SA

+PWR_SRC

+1.0V_PR IM

TPS22961

11

+LCDVDD

+5V_TSP

3

SIO_SLP_S4#

6

+3.3V_ALW

+3.3V_SP I

3

TPS22961

+1.0V_MPHY GT

+3.3V_ALW_DSW

+3.3V_ALW_PCH

5

5

+1.0V_P RIM_CORE

5

17

4

+3.3V_ALW

AP28 21K

+3.3V_ALW

EM5209VF+3.3 V_LAN

+5V_RUN

LP2301ALT1G

+3.3V_RUN

LP2301ALT1G+3.3V _CAM

+1.0V_PR IM

EXT_PWR_GATE#

+1.8V_PR IM

+RTC_CELL

PCH_PLTRST#

PCH_DPW ROK

ENVDD_ PCH

SIO_SLP_ LAN#

3.3V_TS_ EN

3.3V_CAM_E N#

VCCPRIM_1 P0
VCCPRIM_CO RE
DCPDSW_1 P0
VCCMPHYAON_1P 0
VCCAPLL _1P0
VCCCL K1~6
VCCMPHYGT_1P 0
VCCSRAM_1P 0
VCCAMPHYPLL_ 1P0
VCCAPLLEB B

EXT_PWR_GATE#

VCCDSW _3P3

VCCHDA
VCCSPI
VCCPRIM_3 P3
VCCPGPPA~E
VCCRTCPRIM

VCCPGPPG
VCCATS

VCCRTC

VCCPRIM_CO RE

PLTRST#

DSW_PWROK

EDP_VDD EN

SLP_LAN#

GPP_B21

GPD7

PCH

PWRBTN#

RSMRST#

SLP_SUS#

SLP_S5#

SLP_S4#

SLP_S3#

SLP_LAN#

SLP_WLAN# /GPD9

SYS_PWROK

PCH_PW ROK

VCCST_PWR GD

PROCPWR GD

SLP_A#

2

SIO_PWRBT N#

PCH_RSMR ST#

SIO_SLP_SUS#

SIO_SLP_S5#

SIO_SLP_S4#

SIO_SLP_S3#

SIO_SLP_A #

SIO_SLP_ LAN#

SIO_SLP_W LAN#

RESET_OUT#

PCH_PW ROK

VCCST_PWR GD

H_CPUPWRGD

16

15

10

11

14

12

1

8

7

5

9

Power Button

SIO_SLP_W LAN#

SIO 5048

11

11

RUN_ON

+5V_ALW

EM5209VF

+5V_RUN

+5V_HDD

+3.3V_ALW

EM5209VF

B B

@SIO_SLP_W LAN#

+3.3V_ALW

+3.3V_W LAN EM5209VF

11

A A

AUX_EN_WOW L

+PWR_SRC

TLV62130

+3.3V_RUN

+3.3V_HDD

+3.3V_RUN

APL5 930 +1.5V_RUN

+1.0VS_ VCCIO

+VCC_CORE

13

BC BUS

11

+VCC_SA

+VCC_GT

10

+PWR_SRC

ISL95857

PCH_PW ROK

14

ADAP TER

BATTERY

7

4

16

5

9

11

PCH_RSMR ST#

PCH_DPW ROK

RESET_OUT#

SIO_SLP_SUS#

SIO_SLP_S4#

SIO_SLP_S5#

SIO_SLP_ LAN#

SIO_SLP_S3#

SIO_SLP_A #

12

IMVP_VR_ ON

2AC1BAT

ALWON

SIO_SLP_SUS#

@PCH_ALW _ON

11

A_ON

10

SUS_ON

EN_INVPWR

10

SUS_ON

0.675V_DDR _VTT_ ON

+PWR_SRC

+PWR_SRC

5

SYX198EC 5085

SYX198

+3.3V_ALW

EM5209VF

+3.3V_ALW

+3.3V_ALW

EM5209VF

+PWR_SRC

AO640 5

+5V_ALW2
+5V_ALW

+3.3V_ALW2
+3.3V_ALW

+PWR_SRC

RT8207MZ

+3.3V_RTC_LDO

+3.3V_ALW_PCH

+3.3V_MEM5209VF

+3.3V_ SUS

+BL_PWR_SRC

+1.35V_ME M

+0.675V_DDR_VTT

12

1BAT

2AC

5

Pop option

+3.3V_SP I

18

VDDQ

VTT

DDR

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

LA-C461P

LA-C461P

LA-C461P

Power Sequence

Power Sequence

Power Sequence

1

55 61Tuesday, October 13, 2015

55 61Tuesday, October 13, 2015

55 61Tuesday, October 13, 2015

1.0

1.0

1.0

5

4

Version Change List ( P. I. R. List )

3

2

1

Request

Item Issue DescriptionDate

D D

1 12/29 Compal

2

3 X01

C C

4

5

48 +VCCSA

49

47 +1.5V_RUN 05/25 Compal +1.5V_RUN enable chnage to SIO_SLP_S3#

Title

+5V/+3.3V43

+VCC_CORE/GT

12/29

12/29

Owner

Compal

Compal

Compal09/07VCCIO46

change PWR IC for 3V and 5v power rail
5V and 3V change form TPS51285B to SY8286CRAC
and SY8286BRAC.

change VCC_GT to one phase.

change VCC_GT to one phase. change PC663, PC664, PC665, PC669, PC670, PC681, PC687

VCCIO change to 0.95V X06

Remove PQ100, PQ101, PQ102, PQ103 (H-L side Mosfet)
PC113, PC115 (Polymar)
Change PL100 to 1.5UH_PCMC063T-1R5MN_9A_20%
PL101 to 2.2UH +-20% 7.8A 7X7X3 MOLDING
Add PU100 SY8286BRAC_QFN20_3X3
PU102 SY8286CRAC_QFN20_3X3

change PC635 PC638 to de-pop
PU602 Pin9 and Pin10 contect to +5V_ALW

PL605, PR664, PR665, PR666, PR667, PR668, PR669,
PR670, PR681, PU604 to de-pop

Turn PR507 to de-pop
Add PR511 47k_0402 to contact SIO_SLP_S3#

remove PR413 PR416
add PR414 PR415

6

7

8

Solution Description

Rev. 0.1Page#

X01

X01

9

B B

10

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PWR P.I.R (1/1)

PWR P.I.R (1/1)

PWR P.I.R (1/1)

LA-C461P

LA-C461P

LA-C461P

1

56 61Tuesday, October 13, 2015

56 61Tuesday, October 13, 2015

56 61Tuesday, October 13, 2015

1.0

1.0

1.0

5

4

Version Change List ( P. I. R. List )

3

2

1

Item

D D

Page# Rev.

Title

Date

HW 2014/11/1717,17,20,21 COMPAL 0.2(X01)Change DDR3L to DDR4 schematic 1. JDIMM1&JDIMM2 change from DDR3L to DDR4 connector

COMPAL2014/11/17HW10,32,342 EC MCARD_PCIE#_SATA pin is for WWAN

slot, not KEY M SSD slot

Request Owner

Issue

Description

2. change +1.35V_MEM to +1.2V_MEM

3. change +0.675V_DDR_VTT to +0.6V_DDR_VTT

4. add +2.5V_MEM

1. QN2.1&UC1.H2&RC174.1 change from MCARD_PCIE#_SATA to IFDET_SATA_PCIE# 0.2(X01)

39HW2014/11/17COMPALFor reduce power comsupition RC287 change from 10k to 100k ohm

COMPAL344 Delete QN2/RN48/RN24, IFDET_SATA#_PCIE connect to PCH directly

5

8,11,27 HW 2014/11/20 COMPAL Follow Intel LAN Review result 1.RC19&RC20 PH change from +3.3V_ALW_PCH to +3.3V_LAN

C C

6

7

8

10

36 HW 2014/11/20 COMPAL Follow Pericom Review result Reserve CI31

31,32 HW 2014/11/21 COMPAL Follow Gen7 GPIO Master_1122 1.AC_DIS change from UE2.A10 to UE1.A50

27 HW 2014/11/259COMPAL Follow Intel LAN Review result 1.CL22 change from 150P to 1500P 2KV(SE00000WQ00)

30 HW

2014/11/25 COMPAL Follow Intel WOV(Wake on Voice) suggest 1.Delete RA15/RA41/RA42

34 HW 2014/11/25 COMPAL Remove co-lay schematic with PS8558B 1.Delete CN43~CN46,RN85,RN86,UN89~RN98

For key M slot PCIE/SATA Detect2014/11/19HW

(BIOS need setup SATA=0;PCIE=1 by PSCPSP_Px_STRP bit=1)

2.CL7 change from 1uF to 0.1uF

3.CL4 add @

4.CL16&CL17&CL20&CL21 change from 0.47uF to 0.1uF

5.RC70 PH change from +3.3V_ALW_DSW to +3.3V_LAN

2.Add PANEL_ID at UE2.A10 and RE300&CE47

3.Delete RE291 & RE281,and change SUS_ON to CV2_ON

Solution
Description

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

11 32 HW 2014/11/25 COMPAL For separate +1.2V_MEM&+3.3V_CV2 enable pin 1.Delete RE291&RE281

B B

12 11,12,14 HW 2014/11/25 COMPAL For ESD request 1.Add CC300 100P at H_VCCST_PWRGD

13 20,21 HW 2014/11/25 COMPAL Follow Intel DDR4 Review result 1.CD24~CD27,CD57~CD60 change from 0.1uF to 1uF

2.Add CC301 100P at H_CPUPWRGD

3.Reserve CC302 0.1u at SYS_RESET#

4.Reserve CC303 0.1u at PCH_JTAG_TDO

5.Reserve CC304 0.1u at PCH_JTAG_TDI

6.Reserve CC305 0.1u at XDP_JTAGX

7.Reserve CC306 0.1u at TDD_XDP

8.Reserve CC307 0.1u at H_VCCST_PWRGD_XDP

9.Reserve CC308 0.1u at CPU_XDP_TRST#

2.CD29,CD62 add @

3.+2.5V_MEM add CD70,CD71,CD74,CD75(1UF) & CD72,CD73,CD76,CD77(10UF)

3.+1.2V_MEM add CD78~CD85,CD102~CD109(1UF)&CD86~CD101(10UF)

14 40 HW 2014/11/25 COMPAL Follow ME drawing H13 change from H_3P2 to H_3P8

14 38 HW 2014/12/01 COMPAL For sync up with PARK CITY DSC port mapping Swap USB2.0 port5 & port6 at JDOCK1 0.2(X01)

A A

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

15 Board ID for X01COMPAL2014/12/01HW32 0.2(X01)RE79 change from 240k ohm to 130k ohm

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

EE P.I.R (1/6)

EE P.I.R (1/6)

EE P.I.R (1/6)

LA-C461P

LA-C461P

LA-C461P

57 61Tuesday, October 13, 2015

57 61Tuesday, October 13, 2015

57 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

4

Version Change List ( P. I. R. List )

3

2

1

Item

D D

Page# Rev.

16 31,32

Title

Date

Owner

HW 2014/12/01 COMPAL Follow Gen7 GPIO Master_1127

Request

Issue

Description

1.Delete RE294/RE295/RE296/RE297

2.5085 GPIO116 change from PCH_PCIE_WAKE# to MSDATA

3.5085 GPIO124 change from ME_FWP_EC to PCH_PCIE_WAKE#

4.5048 GPIOJ1 add ME_FWP_EC

5.5085 GPIO117 change from USB_PWR_SHR_EN# to MSCLK

6.5048 GPIOK0 add USB_PWR_SHR_EN#

HW 2014/12/0217 32 COMPAL Follow INTEL PDG 1.0 Charger SMBUS PU resistor change from 10k to 2.2k

HW Follow INTEL PDG 1.0COMPAL2014/12/023218 RE88 change from 47k to 10k

Follow Dell ARD Rev1.3COMPALHW 2014/12/053919 1.Reserve RZ26/RZ29 for I2C_1_SDA/I2C_1_SCL

HW 2014/12/05 COMPAL20 13

C C

34,38

HW 2014/12/09 COMPAL For Port Mapping update21 10,26,29,

Follow
546765_546765_2014WW48_Skylake_MOW_Rev_1_0

HW 2014/12/27 COMPAL22 11 For PLTRST glitch issue 1.UC7.5 change from +3.3V_RUN to +3.3V_ALW_PCH

2.Add RZ22/RZ23 for DAT_TP_SIO/CLK_TP_SIO

RC120 add @

1.For USB2,
Camera change from port 10 to port 2
WWAN change form port 2 to port 10

2.For USB3,
EDOCK change from port 5 to port 2
WWAN change from port 2 to port 5

3.For SATA, EDOCK change from SATA1B to SATA1A

4.For PCIE/SATA,
M2 SSD PCIE lane 0 change from port 7 to port 12,
M2 SSD PCIE lane 1 change from port 8 to port 11

2.Pop RC325,depop RC60

Solution
Description

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.3(X02)

HW 2014/12/29 COMPAL23 11 For DIMM Select Issue Pop RD63,RD66;Depop RD62,RD67 0.3(X02)

B B

HW 2014/12/2924 22 COMPAL For HDMI EMI solution 0.3(X02)1.add RV647~RV658

HW 2014/12/2925 32 COMPAL For Power down sequence 0.3(X02)1.Reserve QE3,Add UE4,RE304,RE305

26 8 HW 2014/12/31 COMPAL For Support DCI 1.Reserve RC326,QC3, Add RC327 0.3(X02)

27 13 HW 2014/12/31 COMPAL 1.Reserve CC222 and RC313Follow

28 33 HW For TPM issue 1.UZ12.29 reserve RZ90(10K) PU to +3.3V_RUN

A A

2015/02/06 COMPAL

546765_546765_2014WW52_Skylake_MOW_Rev_1_0

2.UZ12.3 add TPM_LPM# signal & QZ9,RZ111

3.UZ12.13 add TPM_GPIO4 signal &Reserve RZ110

4.Add RZ88(+3.3V_M_TPM), Reserve RZ89(+3.3V_RUN)

1.add RC328 between CPU_XDP_TCLK & XDP_JTAG

2.Reserve RC339/RC340

For fix DCI warmboot hang up issueHW COMPAL2015/02/061030 1.USB2_ID add RC337(10K) to GND

2.USB2_VBUSSENSE add RC338(10K) to GND

0.3(X02)

0.4(X03)

0.4(X03)HW1229 For support DCI2015/02/06 COMPAL

0.4(X03)

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

EE P.I.R (2/6)

EE P.I.R (2/6)

EE P.I.R (2/6)

LA-C461P

LA-C461P

LA-C461P

58 61Tuesday, October 13, 2015

58 61Tuesday, October 13, 2015

58 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

4

Version Change List ( P. I. R. List )

3

2

1

Item

D D

Page# Rev.

31 32 HW 2015/02/06 COMPAL For Power down sequence Depop RE304,RE305,pop UE3 0.4(X03)

Title

Date

Owner

Request

Issue

Description

Solution
Description

32 11 HW 2015/02/06 COMPAL For auto power on issue Depop RC70, depop RC323 0.4(X03)

33 26 HW 2015/02/06 COMPAL BOM changed,follow PC UV24 from SA00006EE00(AP2821KTR-G1) to SA00006Y800(G524B1T114) 0.4(X03)

Intel MOW_2015WW06:Intel recommendation for
DCI tool consulting,

RC317 change from 4.7k to 150k ohm34 8 HW 2015/03/02 COMPAL 0.4(X03)

For X03 Board ID35 32 HW RE79 change from 130k to 4.3k2015/03/02 COMPAL 0.4(X03)

36 8 HW Intel MOW_2015WW06:Pull-up Resistors on

37 33 HW 2015/03/02 for allow further reducing power in TPM

C C

SPI_IO2 and SPI_IO3 Requirement Update

2.0 F/W,when system is in S3/4/5 and main
power is off.

de-pop RC30, RC3162015/03/02 COMPAL

Pop RZ90COMPAL

0.4(X03)

0.4(X03)

38 34 HW 2015/03/02 COMPAL Follow SATA EA result pop RN38 &RN39 0.4(X03)

39 20,21 HW 2015/03/02 COMPAL Intel MOW_2015WW02 Depop CD6,CD35 0.4(X03)

40 35,12 HW 2015/03/02 COMPAL For ESD request 1.+3.3V_HDD add CN100 0.1uF to GND

2.H_THERMTRIP# reserve CC309 0.1uF to GND

3.H_PROCHOT# reserve CC310 0.1uF to GND

0.4(X03)

2015/03/02HW20,2141 CC3~CC6 change from 12pF to 27pF & pop 0.4(X03)For RF requestCOMPAL

Reserve for IR camera26 HW 2015/03/02 COMPAL42 Reserve JIR1 0.4(X03)

2015/03/0443 33 HW UZ12.29 reserve RZ112 to SIO_SLP_S0#COMPAL For TPM vender review result 0.4(X03)

B B

2015/03/0444 9 HW COMPAL UC1.P2 add DIMM_TYPE signal;Low(RC342)=DDR4,High(RC341)=DDR3LFor support DDR3L & DDR4 0.4(X03)

45 40 2015/03/04HW COMPAL For ME request Delete H13 0.4(X03)

46 36 HW 2015/03/04 COMPAL For USB charger issue UI3 change from SA00007TJ00(Pericom) to SA00008DH00(Selegro) as main

11,3247 For Crystal EACOMPAL2015/03/06HW CC21/CC22 change to 15pF

source

CE28/CE29 change to 33pF

0.4(X03)

0.4(X03)

Follow INTEL CRB848 COMPAL2015/03/06HW RC23 change from 8.2k to 2.2k 0.4(X03)

49 33 HW 2015/04/17 NUVOTON For support modern standby

A A

For TPM schematic reviewNUVOTON2015/04/17HW3350

1. Pop RZ112(0 ohm) & Depop RZ90(10k ohm)

1. Pop RZ89(0 ohm) & Depop RZ88(0 ohm)

2. Add RZ113(100 ohm)

0.5(X04)

0.5(X04)

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

EE P.I.R (3/6)

EE P.I.R (3/6)

EE P.I.R (3/6)

LA-C461P

LA-C461P

LA-C461P

59 61Tuesday, October 13, 2015

59 61Tuesday, October 13, 2015

59 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

4

Version Change List ( P. I. R. List )

3

2

1

Item

D D

Page# Rev.

9,1151

9,2652 COMPALHW

Title

Date

Owner

For IR camera design 1. add IR_CAM_DET# connect between GPP_A23(UC1.AW7) & JIR1.1

Request

Issue

Description

2. VRALERT# PU change from +3.3V_ALW to +3.3V_ALW_PCH

2. JIR1.4 change from +PWR_SRC to NC

Solution
Description

0.5(X04)For backdrive issueCOMPAL2015/04/17HW 1. DIMM_TYPE PU change from +3.3V_ALW to +3.3V_ALW_PCH

0.5(X04)2015/04/17

53 2015/04/17HW Broadcom Reserve for USH RESET UE1.A62 add USH_RST#, and reserve RZ114&RZ115 on JUSH1.21 0.5(X04)31,33

For wake up system when non-deep S3 2015/04/17HW COMPAL54 12 SIO_EXT_SMI# PU change from +3.3V_RUN to +3.3V_ALW_PCH 0.5(X04)

2015/04/17HW1055 INTEL For DCI function RC337 change from 1k to 0 ohm

2015/04/17HW2956 SIM detect

2015/04/1757 29 HW ME request

C C

58 2015/04/1741 HW COMPAL For +3.3V_HDD power solution 0.5(X04)Depop PJP18,UZ22,CZ69; Pop PJP36

COMPAL

COMPAL JSIM1 change from JAE_SF51S006V4B to T-SOL_5-991503004000-6 0.5(X04)

0.5(X04)

0.5(X04)Add RI31 connecting with JSIM1.9 and NGFF2.58

59 39 HW 2015/04/17 COMPAL For new U1 TP module Add RZ116 and RZ117 PU on I2C._1_SDA_R/I2C_1_SCL_R 0.5(X04)

60 40 HW 2015/04/17 COMPAL Base on LED measure result RZ32 change from 150 ohm to 330 ohm 0.5(X04)

61 8 HW 2015/04/21 COMPAL For LAN backdrive 1. Add RC347 and RC348 PU to +3.3V_ALW_PCH

2. Depop RC19,RC20

0.5(X04)

COMPAL2015/04/21HW3262 For Board ID RE79 change from 4.3k to 2k 0.5(X04)

63 14 HW 2015/04/23 COMPAL For DCI function

64 22 HW 2015/04/24 COMPAL Pop LV3/LV6/LV9/LV12

B B

66 36 HW

HW3967 COMPAL

2015/05/04

2015/05/06

COMPAL

Base on HDMI EE/EMI measure result

For JAE JSIM1 boss hole Add H34 H_0P7N & H35 H_0P9N65 40 HW 2015/04/30 COMPAL

For s hut d own iss ue

For TP sometimes can't work in BIOS or OS Pop CZ30/CZ31 330pF

2015/05/12HW68 29,40 COMPAL For NVME SSD LED issue

69 36 HW 2015/03/04 COMPAL For USB charger issue UI3 main source change from SA00008DH00(Selegro) to

70 COMPAL2015/05/12HW40 RZ25/RZ27/RZ34 change from 220 to 150 ohm

Base on LED EA result

71 18 HW 2015/05/28 INTEL For RF 5.76GHz noise issue 1. add RC349,CC313,CC314

72 27 HW 2015/06/02 COMPAL For LAN EA result Change LL2~LL9(12nH) to RL71~RL78(2.2ohm)

73 For HDMI EA resultCOMPAL2015/06/02HW22 0.5(X04)1.RV647/RV649/RV650/RV652/RV653/RV655/RV656/RV658 change from 8.2ohm to

A A

UC8 & CC30 remove CXDP@ 0.5(X04)

Depop RV647~RV658

0.5(X04)

0.5(X04)

Add CZ32 (150U_B2_6.3VM_R35M)

0.5(X04)

0.5(X04)

JNGFF3.10 add NVME_LED#, thought RZ118(0 ohm) connect to PCH_SATA_LED# 0.5(X04)

SA00007TJ00(Pericom)

0.5(X04)

0.5(X04)

2. change 0603 to 0402

0.5(X04)

0.5(X04)

5.6 ohm

2.RV648/RV651/RV653/RV657 change from 150 ohm to 200 ohm

3.Depop LV3/LV6/LV9/LV12;Pop RV647~RV658

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

EE P.I.R (4/6)

EE P.I.R (4/6)

EE P.I.R (4/6)

LA-C461P

LA-C461P

LA-C461P

60 61Tuesday, October 13, 2015

60 61Tuesday, October 13, 2015

60 61Tuesday, October 13, 2015

1

1.0

1.0

1.0

5

4

Version Change List ( P. I. R. List )

3

2

1

Item

D D

Page# Rev.

2574 0.5(X04)For DP hub display flicker issueCOMPAL2015/06/03HW 1.Add UV29,CV617,CV618,CV619,PJP37,RV659,RV650,RV661

Title

Date

Owner

Request

Issue

Description

2.Depop UV28,PJP33

Solution
Description

Sink up with Park CityCOMPAL2015/06/04HW75 9 Reserve RC330,RC331 0.5(X04)

76 DELL2015/07/13 IC change from TPM2.0 to TPM1.2HW33 UZ12 change from SA000082D00(TPM2.0) to SA000082D20(TPM1.2) 0.6(X05)

77 2015/07/13 NUVOTON33 HW For TPM Deep S3 issue UZ12.1 change from +3.3V_ALW_PCH to +3.3V_ALW 0.6(X05)

78 32 HW 2015/07/13 COMPAL For Global Reset issue 1.Add UE5,QE11 & Reserve CE52,RE90

2.RE292 footprint change from 0ohm-short to 0 ohm(@)

0.6(X05)

79 32 HW 2015/07/13 COMPAL For Board ID RE79 change from 2k to 8.2k 0.6(X05)

80 18 HW 2015/07/17 COMPAL For RF request 1.Change RC349/RC172(0 ohm) to LC1/LC2(BLM15HG601SN1D)

C C

2.Pop CC313/CC314

0.6(X05)

2015/07/17HW3681 COMPAL For Sourcer request CI32 change from SGA00002N80 to SGA00004E10 0.6(X05)

82 17 2015/08/17HW INTEL Follow Intel DG1.5 Add load switch (UZ26) control to +VCCPLL_OC power rail 0.7(X06)

2015/08/171783 Follow Park City for DC mode CPU trubo issueCOMPALHW Reserved RE313 pull down path on I_SYS 0.7(X06)

84 17 2015/08/17 COMPALHW Change design soluiton for prevent thermal

too high

85 32 HW 2015/08/19 COMPAL For Board ID RE79 change from 8.2k to 62k

86 36 HW 2015/08/27 COMPAL

For & D ell USB HDD is sue at Low

battery on 3 cell battery

UV29 change from APL5930QBI-TRG_TDFN10_3X3 to
G9661-25ADJRE1U_TDFN10_3X3 & VIN change from +3.3V_RUN to +1.8V_PRIM

1.Pop CI14; depop CI32
2,UI3 change from SA00007TJ00 to SA000097E00

3.Reserve CI33,CI34

0.7(X06)

0.7(X06)

0.7(X06)

87 Add GPIO for China TPM & TPM option add TPM_TYPE signal &RC349COMPAL2015/09/09HW9 1.0(A00)

B B

88 2015/09/09 COMPAL8HW For TP issue Depop CC4 1.0(A00)

89 2015/09/09 COMPAL32 HW For Board ID RE79 change from 62k to 1k

90 12,28,32,27 HW 2015/09/09 COMPAL For MP 1.Depop SW1, RC221 change to 0 ohm short pad

2.UR2 change from SA000089Q00 to SA000089Q10

3.UE2 change from SA00006YH30 to SA00006YH90

4.UL1 change from SA000081G0L to SA000081G1L

1.0(A00)

1.0(A00)

91 12,28,32,27 HW 2015/09/17 COMPAL For ME request H21 & H22 change from H_3P2 to H_3P3 1.0(A00)

92 12,14 HW 2015/09/24 COMPAL For INTEL PDG 2.0 RC135,RC82 change from 51 ohm to 100 ohm 1.0(A00)

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

EE P.I.R (5/6)

EE P.I.R (5/6)

EE P.I.R (5/6)

LA-C461P

LA-C461P

LA-C461P

61 61Tuesday, October 13, 2015

61 61Tuesday, October 13, 2015

61 61Tuesday, October 13, 2015

1

1.0

1.0

1.0