Compal LA-C361P Schematics Rev0.1

A

B

C

D

E

MODEL NAME : PCB NO :

AAM00

LA-C361P

BOM P/N :

1 1

Dell/Compal Confidential

Schematic Document

SKYLAKE-H

2014-05-22

Rev: 0.0 (M00)

2 2

CONN@ : Connector Component

R1@ / R3@ : R1/R3 CPN for CPU, GPU, PCB

PCH

UH1

R1@

PCB 1BG LA-C361P REV0 MB

3 3

R1@ZZZ

SKL-H_BGA1440

UH2

SKY-H-PCH_BGA837

Samsung 2G

UV5

K4G41325FC-HC03_FBGA170P~D

VRAMS@

UV9

UV6

K4G41325FC-HC03_FBGA170P~D

VRAMS@

UV10

GPUCPUPCB

UV1

BC@

N16P-Q1-A2

R1@

UV1

GX@

N16P-GX-A2

RV312

20K_0402_1%

VRAMS@

VRAMS@ : Samsung GDDR5 for GPU VRAMH@ : Hynix GDDR5 for GPU

VRAMM@ : Micron GDDR5 for GPU

BreakDown@ : for measure power consumption

CSMB@ : CSMB sku

UMA@ / DIS@ : UMA/DIS

@ : Nopop Component

TPM@ : TPM function EMC@ : Pop of EMI parts

BC@ : BC sku (GPU N16P-Q1) GX@ : GPU N16P-GX

K4G41325FC-HC03_FBGA170P~D

VRAMS@

Hynix 2G

UV5

4 4

H5GC4H24AJR-R0C_FBGA170P~D

VRAMH@

UV9

H5GC4H24AJR-R0C_FBGA170P~D

VRAMH@

K4G41325FC-HC03_FBGA170P~D

VRAMS@

UV6

H5GC4H24AJR-R0C_FBGA170P~D

VRAMH@

UV10

H5GC4H24AJR-R0C_FBGA170P~D

VRAMH@

A

RV312

34.8K_0402_1%

VRAMH@

Micron 2G

UV5

EDW4032BABG-60-F_FBGA170P~D

VRAMM@

UV9

EDW4032BABG-60-F_FBGA170P~D

VRAMM@

B

RV312

UV6

EDW4032BABG-60-F_FBGA170P~D

VRAMM@

UV10

EDW4032BABG-60-F_FBGA170P~D

VRAMM@

24.9K_0402_1%

VRAMM@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONIC S, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONIC S, INC.

C

2011/08/25 2011/08/25

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Cover Page

Cover Page LA-C361P

LA-C361P

E

1 71Thursday, August 06, 2015

0.1(X00)

A

www.vinaﬁx.com

128M*32 x4 =2G

VRAM * 4 GDDR5

P.28~31

B

C

D

E

GB4-128

1 1

GPU N16P-GX

P.23~27

PEG 3.0 x16

Intel

Skylake-H

Memory Bus (DDR4)

Dual Channel

Processor

35W/45W QC

UHD 3840*2160 (4K*2K, eDP 1.3)

P.35

eDP *4 lane

PCI-E x1

Port 3 Port 4

2 2

M.2 Slot A Key-E

(WLAN+BT4.0)

USB2.0

Port 4

USB 3.0 Conn.

( USB Charger )

P.43

P.47

Digital Camera Conn.

P.35

Card Reader RTS5242

USB Powershare TPS2546

Port 12

USB2.0

3 in 1 Socket

P.51

P.46

Port 4

Port 2

USB 3.0

USB2.0

BGA 1440

Intel

SLK-H-PCH BGA 837 Balls

P.7~13

DMI x4

100MHz 5GB/s

DDI x 2

SATA3.0

PCI-E x4

USB 3.0

USB2.0

Port 0

Port 1

Port 2

Port 1

Port 9

DDRIV-DIMM X2

1.2V DDR4 2133 MHz

32GB Max

PCI-E x2

Port 5,6

M.2 Slot C Key-M

(SATA/PCIe SSD)

USB 3.0 Re-driver

P.47

Touch Panel Conn.

P.35

P.14~15

Intel Alpine Ridge

P.44

P.37~38

P.39~41

PD controller

HDD Conn.

P.45

USB Powershare TPS2546

Audio board

P.46

CPU XDP Conn.

P.6

HDMI Conn.

P.36

USB Type C Conn.

P.41

DC-in Conn.

P.54

USB 3.0 Conn.

( USB Charger )

P.47

3 3

Power On/Off CKT.

DC/DC Interface CKT.

4 4

P.42

P.32~34

A

SPI Flash (BIOS 16MB)

FFS LNG3DMTR

MCP 23017

GPIO Expander

P.17

P.45

SMBus

P.49

SPI

SMBus

TPM NPCT650JAAYX

P.42

PWM

Fan Control

P.42

B

SPI

PS/2 I2C

Touch Pad

P.42

MEC 5085

SIO

LPC Bus

33MHz

P.48

HD Audio

P16~22

Audio Codec ALC3266

AMP TAS5768

Int. Speaker x2

KB Board

KBC ECE1117

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

Digital MIC Conn.

KSIOBCBUS

Int.KBD

Compal Secret Data

2011/08/25 2011/08/25

Compal Secret Data

Deciphered Date

D

Headphone / Mic. Jack

( Combo )

Title

Block diagram

Size Document Number Rev

LA-C361P

Date: Sheet of

Compal Electronics, Inc.

2 71Thursday, August 06, 2015

E

2 71Thursday, August 06, 2015

0.1(X00)

A

B

C

D

E

Compal Confidential

Project Code : AAM00 File Name :

1 1

LA-C361P M/B

LS-C361P Audio Board

2 2

JAUDIO BtB Conn.

JTPJKB

15 pin

FFC

8 pin

FFC

Issued Date

Touch Pad

Compal Secret Data

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DB block diagram

E

3 71Thursday, August 06, 2015

0.1(X00)

LS-C362P KB controller Board

JLED

3 3

FFC

4 pin

4 4

A

B

Front Side LED/B

Security Classification

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

A

Board ID X00 X01 X02 X03 A00

PCI EXPRESS

1 1

Resistor

N/A

DESTINATION Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6 Lane 7

NGFF-1 WLAN + BT CARD READER None None None None

None Lane 8 None Lane 9

SSD Lane 10 Lane 11 Lane 12 Lane 13 Lane 14 Lane 15 Lane 16

SSD

None

Alpine Ridge

USB31DESTINATION

USB Conn 1 (Right Side) 2 3 4 5 6

USB Conn 2 (Left Side)

None

DESTINATIONUSB3 7 8 9 10

SATA

0A 1A N/A N/A 0B

None

DESTINATION

SSD

N/ASSD

N/A

None

HDD1B

2 3

None

USB 2.0 DESTINATION

1 2 3 4 5 6 7 8 9 10 11 12

USB Conn 1 (Right Side) USB Conn 2 (Left Side) None None NGFF-1 WLAN + BT None None None None Touch screen None None CAMERA

DESTINATIONCLKOUT_PCIE 0 1 2 3 4

None

NGFF-1 WLAN

CARD READER

Thunderbolt5 6 7 8 9

NGFF-2 SSD

GPU

None

DDI

1 2 3

LPC

LPC1

CLKOUT_PCIE

10 11 12 13 14 15

DESTINATION Alpine Ridge Alpine Ridge

DESTINATION MEC5085LPC0 DEBUG PORT

DESTINATION None None None None None None

Symbol Note :

: means Digital Ground : means Analog Ground

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

A

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Notes List

Notes List LA-C361P

LA-C361P

4 71Thursday, August 06, 2015

0.1(X00)

5

4

3

2

1

SMBUS Address [0x9a]

AW44 BB43

D D

PCH

AR38

AT42

SMBCLK SMBDATA

I2C0_SCK I2C0_SDA

1K

5.1K

+3V_PCH

+3VS

DMN66D0 DMN66D0

0 ohm

10K

AR41 AR44

I2C1_SCK_TP I2C1_SDA_TP

10K

AW42AW45

1K

SML1CLK

SML1DATA

C C

1K

+3V_PCH

+3VS

DMN66D0 DMN66D0

1K

Codec

10K

+3VS

DIMMA

DIMMB

FFS

XDP

+3VS_TP

TP

2.2K

A5 B6

A56 B59

PBAT_SMBCLK PBAT_SMBDAT

2.2K

+3VALW_EC

100 ohm

BATT

0x16

10K

+3VALW_EC

0 ohm

CHARGER

0x12

MEC5085

B50 A47

CHARGER_SMBCLK CHARGER_SMBDAT

10K

B B

10K

+3VALW_EC

B49 B48

UPD_GPU_SMBCLK UPD_GPU_SMBDAT

10K

2.2K

A A

5

B4 A3

MCP23017_SMBCLK MCP23017_SMBDAT

2.2K

4

+3VALW_EC

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DGPU_PEX_RST#

0 ohm

Issued Date

3

DMN66D0 DMN66D0

+3VALW

DMN66D0 DMN66D0

DMN66D0

0 ohm

Codec

10K

+3V_PD

PD Controller

5.1K

Compal Secret Data

2011/08/25 2012/07/15

Compal Secret Data

+3.3V_GFX_AON

GPU

MCP23017

Deciphered Date

0x9E

0x42

2

Compal Electronics, Inc.

Title

SMBus Block Diagram

Size Document Number Rev

Custom

Date: Sheet of

5 71Thursday, August 06, 2015

1

0.1(X00)

+3VS

5

+1V_PCH

1

XDP@

+1V_PCH

+3V_PCH

D D

+VCCST

+VCCSTG

C C

PCH_ITP_PMODE[18]

H_VCCST_PWRGD[9,34]

B B

JTAG

1 2

RH492

1 2

RH493

1 2

RH97

1 2

RH98

1 2

RH100

1 2

RH494

1 2

RH495

1 2

RH496

1 2

RH95

1 2

RH498

1 2

RH497

PLTRST_CPU#[9,16]

PCH_SPI_SI_R[17] RESET_OUT#[18,48]

PCH_RSMRST#[18,48]

XDP_PLTRST#

2.2K_0402_5%

PCH_SYS_PWROK_XDP

2.2K_0402_5%

PCH_JTAG_TDO

@

51_0402_5%

PCH_JTAG_TMS

@

51_0402_5%

PCH_JTAG_TDI

@

51_0402_5%

CPU_XDP_TMS

51_0402_5%

CPU_XDP_TDI

51_0402_5%

CPU_XDP_TDO

51_0402_5%

PCH_JTAG_TCK

51_0402_5%

CPU_XDP_TCK

51_0402_5%

CPU_XDP_TRST#

51_0402_5%

1 2

RH479 0_0402_5%XDP@

1 2

@

RH480 1K_0402_5%

1 2

RH489 1K_0402_5%XDP@

1 2

RH490 0_0402_5%@

1 2

RH481 1K_0402_5%XDP@

1 2

RH482 1K_0402_5%@

+VCCIO

12

RH483 150_0402_5%

1 2

RH488 1K_0402_5%

CH3

0.1U_0402_25V6

2

XDP_PLTRST#

PCH_SYS_PWROK_XDP

XDP_PWRGOOD

CFG0PWR_DEBUG#_XDP

X06.13

4

3

2

1

CPU

1 2

CFG3

XDP@

RH474 1K_0402_5%

+1V_PCH +1V_PCH

XDP_PREQ#[9,22] XDP_PRDY#[9,22]

XDP_BPM#0[9] XDP_BPM#1[9]

PCH_SMBDATA[14,15,18,45] PCH_SMBCLK[14,15,18,45]

PCH_JTAG_TCK[18]

CPU_XDP_TCK[9]

PCH_JTAGX[18]

CFG0[9] CFG1[9]

CFG2[9] CFG3[9]

CFG4[9] CFG5[9]

CFG6[9] CFG7[9]

CFG0

CFG3

XDP_PWRGOOD PWRBTN#_XDP

PWR_DEBUG#_XDP PCH_SYS_PWROK_XDP

PCH_JTAG_TCK CPU_XDP_TCK

1 2

@

RH491 0_0402_5%

PWRBTN#_XDP

+3V_PCH_DSW

12

XDP@

RH2 1K_0402_5%

0.1U_0402_25V6 CH174

12

RH475 0_0402_5%

JXDP

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

CONN@

1 2

RH6 0_0402_5%XDP@

XDP@

1 2

@

GND1 OBSFN_C0 OBSFN_C1

GND3

OBSDATA_C0 OBSDATA_C1

GND5

OBSDATA_C2 OBSDATA_C3

GND7 OBSFN_D0 OBSFN_D1

GND9

OBSDATA_D0 OBSDATA_D1

GND11 OBSDATA_D2 OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

GND17

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46

XDP_PLTRST#

48

XDP_DBRESET#

50 52 54 56 58 60

XDP_TDO

XDP_TRST#

XDP_TDI

XDP_TMS

RH573 1K_0402_5%

TD0

TDI

TMS

SIO_PWRBTN# [18,48]

CFG17 [9] CFG16 [9]

CFG8 [9] CFG9 [9]

CFG10 [9] CFG11 [9]

CFG19 [9] CFG18 [9]

CFG12 [9] CFG13 [9]

CFG14 [9] CFG15 [9]

PCH_XDP_CLK_P [17] PCH_XDP_CLK_N [17]

1 2

XDP@

XDP_DBRESET#

PCH_SPI_WP#_R [17]

+3VS

12

RH5 1K_0402_5%

RH8 0_0402_5%

0.1U_0402_25V6 CH175

XDP@

12

1 2

XDP_TDO

XDP_TDI

XDP_TMS

XDP_TRST#

XDP_TMS

XDP_TDI

XDP_TDO

X06.13

@

SYS_RESET# [18,52]

RH540 0_0402_5%@

RH541 0_0402_5%@

RH542 0_0402_5%@

RH543 0_0402_5%@

1 2

RH12 0_0402_5%@

1 2

RH477 0_0402_5%@

1 2

RH478 0_0402_5%@

1 2

X06.13

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

CPU_XDP_TDO [9]

CPU_XDP_TDI [9]

CPU_XDP_TMS [9]

CPU_XDP_TRST# [9,22]

PCH

PCH_JTAG_TMS [18]

PCH_JTAG_TDI [18]

PCH_JTAG_TDO [18]

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

XDP CONN

1

6 71Thursday, August 06, 2015

0.1(X00)

5

PEG_HTX_C_GRX_P[0..15][23] PEG_HTX_C_GRX_N[0..15][23] PEG_GTX_C_HRX_P[0..15][23] PEG_GTX_C_HRX_N[0..15][23]

D D

C C

PEG_HTX_C_GRX_P[0..15] PEG_HTX_C_GRX_N[0..15] PEG_GTX_C_HRX_P[0..15] PEG_GTX_C_HRX_N[0..15]

+VCCIO

RH24 24.9_0402_1%

DMI_CRX_PTX_P0[19] DMI_CRX_PTX_N0[19]

DMI_CRX_PTX_P1[19] DMI_CRX_PTX_N1[19]

DMI_CRX_PTX_P2[19] DMI_CRX_PTX_N2[19]

DMI_CRX_PTX_P3[19] DMI_CRX_PTX_N3[19]

PEG_GTX_C_HRX_P15 PEG_GTX_C_HRX_N15

PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_N14

PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_N13

PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_N12

PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_N11

PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_N10

PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_N9

PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_N8

PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_N7

PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_N6

PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_N5

PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_N4

PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_N3

PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_N2

PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_N1

PEG_GTX_C_HRX_P0 PEG_GTX_C_HRX_N0

1 2

4

UH1C

E25

PEG_RXP[0]

D25

PEG_RXN[0]

E24

PEG_RXP[1]

F24

PEG_RXN[1]

E23

PEG_RXP[2]

D23

PEG_RXN[2]

E22

PEG_RXP[3]

F22

PEG_RXN[3]

E21

PEG_RXP[4]

D21

PEG_RXN[4]

E20

PEG_RXP[5]

F20

PEG_RXN[5]

E19

PEG_RXP[6]

D19

PEG_RXN[6]

E18

PEG_RXP[7]

F18

PEG_RXN[7]

D17

PEG_RXP[8]

E17

PEG_RXN[8]

F16

PEG_RXP[9]

E16

PEG_RXN[9]

D15

PEG_RXP[10]

E15

PEG_RXN[10]

F14

PEG_RXP[11]

E14

PEG_RXN[11]

D13

PEG_RXP[12]

E13

PEG_RXN[12]

F12

PEG_RXP[13]

E12

PEG_RXN[13]

D11

PEG_RXP[14]

E11

PEG_RXN[14]

F10

PEG_RXP[15]

E10

PEG_RXN[15]

G2

PEG_RCOMP

D8

DMI_RXP[0]

E8

DMI_RXN[0]

E6

DMI_RXP[1]

F6

DMI_RXN[1]

D5

DMI_RXP[2]

E5

DMI_RXN[2]

J8

DMI_RXP[3]

J9

DMI_RXN[3]

SKL-H_BGA1440

@

REV = 1

SKYLAKE_HALO

BGA1440

?

3 OF 14

PEG_TXP[0] PEG_TXN[0]

PEG_TXP[1] PEG_TXN[1]

PEG_TXP[2] PEG_TXN[2]

PEG_TXP[3] PEG_TXN[3]

PEG_TXP[4] PEG_TXN[4]

PEG_TXP[5] PEG_TXN[5]

PEG_TXP[6] PEG_TXN[6]

PEG_TXP[7] PEG_TXN[7]

PEG_TXP[8] PEG_TXN[8]

PEG_TXP[9] PEG_TXN[9]

PEG_TXP[10] PEG_TXN[10]

PEG_TXP[11] PEG_TXN[11]

PEG_TXP[12] PEG_TXN[12]

PEG_TXP[13] PEG_TXN[13]

PEG_TXP[14] PEG_TXN[14]

PEG_TXP[15] PEG_TXN[15]

DMI_TXP[0] DMI_TXN[0]

DMI_TXP[1] DMI_TXN[1]

DMI_TXP[2] DMI_TXN[2]

DMI_TXP[3] DMI_TXN[3]

B25 A25

B24 C24

B23 A23

B22 C22

B21 A21

B20 C20

B19 A19

B18 C18

A17 B17

C16 B16

A15 B15

C14 B14

A13 B13

C12 B12

A11 B11

C10 B10

B8 A8

C6 B6

B5 A5

D4 B4

?

3

PEG_HTX_GRX_P15 PEG_HTX_GRX_N15

PEG_HTX_GRX_P14 PEG_HTX_GRX_N14

PEG_HTX_GRX_P13 PEG_HTX_GRX_N13

PEG_HTX_GRX_P12 PEG_HTX_GRX_N12

PEG_HTX_GRX_P11 PEG_HTX_GRX_N11

PEG_HTX_GRX_P10 PEG_HTX_GRX_N10

PEG_HTX_GRX_P9 PEG_HTX_GRX_N9

PEG_HTX_GRX_P8 PEG_HTX_GRX_N8

PEG_HTX_GRX_P7 PEG_HTX_GRX_N7

PEG_HTX_GRX_P6 PEG_HTX_GRX_N6

PEG_HTX_GRX_P5 PEG_HTX_GRX_N5

PEG_HTX_GRX_P4 PEG_HTX_GRX_N4

PEG_HTX_GRX_P3 PEG_HTX_GRX_N3

PEG_HTX_GRX_P2 PEG_HTX_GRX_N2

PEG_HTX_GRX_P1 PEG_HTX_GRX_N1

PEG_HTX_GRX_P0 PEG_HTX_GRX_N0

1 2

CH5 0.22U_0201_6.3V6MDIS@

1 2

CH6 0.22U_0201_6.3V6MDIS@

1 2

CH7 0.22U_0201_6.3V6MDIS@

1 2

CH8 0.22U_0201_6.3V6MDIS@

1 2

CH9 0.22U_0201_6.3V6MDIS@

1 2

CH10 0.22U_0201_6.3V6MDIS@

1 2

CH11 0.22U_0201_6.3V6MDIS@

1 2

CH12 0.22U_0201_6.3V6MDIS@

1 2

CH13 0.22U_0201_6.3V6MDIS@

1 2

CH14 0.22U_0201_6.3V6MDIS@

1 2

CH15 0.22U_0201_6.3V6MDIS@

1 2

CH16 0.22U_0201_6.3V6MDIS@

1 2

CH17 0.22U_0201_6.3V6MDIS@

1 2

CH18 0.22U_0201_6.3V6MDIS@

1 2

CH19 0.22U_0201_6.3V6MDIS@

1 2

CH20 0.22U_0201_6.3V6MDIS@

1 2

CH21 0.22U_0201_6.3V6MDIS@

1 2

CH22 0.22U_0201_6.3V6MDIS@

1 2

CH23 0.22U_0201_6.3V6MDIS@

1 2

CH24 0.22U_0201_6.3V6MDIS@

1 2

CH25 0.22U_0201_6.3V6MDIS@

1 2

CH26 0.22U_0201_6.3V6MDIS@

1 2

CH27 0.22U_0201_6.3V6MDIS@

1 2

CH28 0.22U_0201_6.3V6MDIS@

1 2

CH29 0.22U_0201_6.3V6MDIS@

1 2

CH30 0.22U_0201_6.3V6MDIS@

1 2

CH31 0.22U_0201_6.3V6MDIS@

1 2

CH32 0.22U_0201_6.3V6MDIS@

1 2

CH33 0.22U_0201_6.3V6MDIS@

1 2

CH34 0.22U_0201_6.3V6MDIS@

1 2

CH35 0.22U_0201_6.3V6MDIS@

1 2

CH36 0.22U_0201_6.3V6MDIS@

DMI_CTX_PRX_P0 [19] DMI_CTX_PRX_N0 [19]

DMI_CTX_PRX_P1 [19] DMI_CTX_PRX_N1 [19]

DMI_CTX_PRX_P2 [19] DMI_CTX_PRX_N2 [19]

DMI_CTX_PRX_P3 [19] DMI_CTX_PRX_N3 [19]

PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_N15

PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_N14

PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_N13

PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_N12

PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_N11

PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_N10

PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_N9

PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_N8

PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_N7

PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_N6

PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_N5

PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_N4

PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_N3

PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N2

PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1

PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0

2

1

UH1D

DDI1_HTX_TBRX_P0[37]

B B

A A

5

DDI1_HTX_TBRX_N0[37] DDI1_HTX_TBRX_P1[37] DDI1_HTX_TBRX_N1[37] DDI1_HTX_TBRX_P2[37] DDI1_HTX_TBRX_N2[37] DDI1_HTX_TBRX_P3[37] DDI1_HTX_TBRX_N3[37]

DDI1_CPU_AUXP[37] DDI1_CPU_AUXN[37]

DDI2_HTX_TBRX_P0[37] DDI2_HTX_TBRX_N0[37] DDI2_HTX_TBRX_P1[37] DDI2_HTX_TBRX_N1[37] DDI2_HTX_TBRX_P2[37] DDI2_HTX_TBRX_N2[37] DDI2_HTX_TBRX_P3[37] DDI2_HTX_TBRX_N3[37]

DDI2_CPU_AUXP[37] DDI2_CPU_AUXN[37]

K36

DDI1_TXP[0]

K37

DDI1_TXN[0]

J35

DDI1_TXP[1]

J34

DDI1_TXN[1]

H37

DDI1_TXP[2]

H36

DDI1_TXN[2]

J37

DDI1_TXP[3]

J38

DDI1_TXN[3]

D27

DDI1_AUXP

E27

DDI1_AUXN

H34

DDI2_TXP[0]

H33

DDI2_TXN[0]

F37

DDI2_TXP[1]

G38

DDI2_TXN[1]

F34

DDI2_TXP[2]

F35

DDI2_TXN[2]

E37

DDI2_TXP[3]

E36

DDI2_TXN[3]

F26

DDI2_AUXP

E26

DDI2_AUXN

C34

DDI3_TXP[0]

D34

DDI3_TXN[0]

B36

DDI3_TXP[1]

B34

DDI3_TXN[1]

F33

DDI3_TXP[2]

E33

DDI3_TXN[2]

C33

DDI3_TXP[3]

B33

DDI3_TXN[3]

A27

DDI3_AUXP

B27

DDI3_AUXN

SKL-H_BGA1440

@

4

REV = 1

BGA1440

4 OF 14

EDP_TXP[0] EDP_TXN[0] EDP_TXP[1] EDP_TXN[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXP EDP_AUXN

EDP_DISP_UTIL

EDP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

D29 E29 F28 E28 B29 A29 B28 C28

C26 B26

A33

EDP_DISP_UTIL

D37

EDP_COMP

G27 G25 G29

?

EDP_TXP0 [35] EDP_TXN0 [35] EDP_TXP1 [35] EDP_TXN1 [35] EDP_TXN2 [35] EDP_TXP2 [35] EDP_TXN3 [35] EDP_TXP3 [35]

EDP_AUXP [35] EDP_AUXN [35]

1 2

RH456 0_0402_5%@

1 2

RH30 24.9_0402_1%

EDP_COMP CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils.

BIA_PWM_PCH [16,35]

+VCCIO

Close to CPU

AUD_AZA_CPU_SCLK [18]

1 2

RH145 20_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

AUD_AZA_CPU_SDO [18] AUD_AZA_CPU_SDI_R [18]

Compal Secret Data

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number Rev

C

Date: Sheet of

1

7 71Thursday, August 06, 2015

0.1(X00)

?

SKYLAKE_HALO

Interleave

5

4

3

2

1

?

REV = 1

SKYLAKE_HALO

BGA1440

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSN[7]/DDR1_DQSN[5]

1 OF 14

DDR0_CKP[0] DDR0_CKN[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CLKP[2] DDR0_CLKN[2] DDR0_CLKP[3] DDR0_CLKN[3]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1]

DDR0_CS#[2]

DDR0_CS#[3] DDR0_ODT[0]

DDR0_ODT[1] DDR0_ODT[2] DDR0_ODT[3]

DDR0_MA[3] DDR0_MA[4]

DDR0_PAR

DDR0_ALERT#

DDR0_DQSN[0] DDR0_DQSN[1]

DDR0_DQSP[0] DDR0_DQSP[1]

DDR0_DQSP[8] DDR0_DQSN[8]

?

AG1 AG2 AK1 AK2 AL3 AK3 AL2 AL1

AT1 AT2 AT3 AT5

AD5 AE2 AD2 AE5

AD3 AE4 AE1 AD4

AH5 AH1 AU1

AH4 AG4 AD1

AH3 AP4 AN4 AP5 AP2 AP1 AP3 AN1 AN3 AT4 AH2 AN2 AU4 AE3 AU2 AU3

AG3 AU5

BR5 BL3 BG3 BD3 AB3 V3 R3 M3

BP5 BK3 BF3 BC3 AA3 U3 P3 L3

AY3 BA3

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

UH1B

BT11

1 2 1 2 1 2

DDR_B_D0 DDR_B_D1 DDR_B_D6 DDR_B_D2 DDR_B_D4 DDR_B_D5 DDR_B_D3 DDR_B_D7 DDR_B_D12

DDR_B_D9 DDR_B_D10 DDR_B_D14 DDR_B_D11 DDR_B_D13 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D21 DDR_B_D19 DDR_B_D18 DDR_B_D22 DDR_B_D20 DDR_B_D23 DDR_B_D26 DDR_B_D24 DDR_B_D31 DDR_B_D25 DDR_B_D28 DDR_B_D30 DDR_B_D29 DDR_B_D27 DDR_B_D34 DDR_B_D38 DDR_B_D32 DDR_B_D36 DDR_B_D35 DDR_B_D39 DDR_B_D37 DDR_B_D33 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D47 DDR_B_D46 DDR_B_D48 DDR_B_D51 DDR_B_D50 DDR_B_D52 DDR_B_D53 DDR_B_D55 DDR_B_D49 DDR_B_D54 DDR_B_D58 DDR_B_D57 DDR_B_D59 DDR_B_D61 DDR_B_D62 DDR_B_D60 DDR_B_D56 DDR_B_D63

DDR1_DQ[0]/DDR0_DQ[16]

BR11

DDR1_DQ[1]/DDR0_DQ[17]

BT8

DDR1_DQ[2]/DDR0_DQ[18]

BR8

DDR1_DQ[3]/DDR0_DQ[19]

BP11

DDR1_DQ[4]/DDR0_DQ[20]

BN11

DDR1_DQ[5]/DDR0_DQ[21]

BP8

DDR1_DQ[6]/DDR0_DQ[22]

BN8

DDR1_DQ[7]/DDR0_DQ[23]

BL12

DDR1_DQ[8]/DDR0_DQ[24]

BL11

DDR1_DQ[9]/DDR0_DQ[25]

BL8

DDR1_DQ[10]/DDR0_DQ[26]

BJ8

DDR1_DQ[11]/DDR0_DQ[27]

BJ11

DDR1_DQ[12]/DDR0_DQ[28]

BJ10

DDR1_DQ[13]/DDR0_DQ[29]

BL7

DDR1_DQ[14]/DDR0_DQ[30]

BJ7

DDR1_DQ[15]/DDR0_DQ[31]

BG11

DDR1_DQ[16]/DDR0_DQ[48]

BG10

DDR1_DQ[17]/DDR0_DQ[49]

BG8

DDR1_DQ[18]/DDR0_DQ[50]

BF8

DDR1_DQ[19]/DDR0_DQ[51]

BF11

DDR1_DQ[20]/DDR0_DQ[52]

BF10

DDR1_DQ[21]/DDR0_DQ[53]

BG7

DDR1_DQ[22]/DDR0_DQ[54]

BF7

DDR1_DQ[23]/DDR0_DQ[55]

BB11

DDR1_DQ[24]/DDR0_DQ[56]

BC11

DDR1_DQ[25]/DDR0_DQ[57]

BB8

DDR1_DQ[26]/DDR0_DQ[58]

BC8

DDR1_DQ[27]/DDR0_DQ[59]

BC10

DDR1_DQ[28]/DDR0_DQ[60]

BB10

DDR1_DQ[29]/DDR0_DQ[61]

BC7

DDR1_DQ[30]/DDR0_DQ[62]

BB7

DDR1_DQ[31]/DDR0_DQ[63]

AA11

DDR1_DQ[32]/DDR1_DQ[16]

AA10

DDR1_DQ[33]/DDR1_DQ[17]

AC11

DDR1_DQ[34]/DDR1_DQ[18]

AC10

DDR1_DQ[35]/DDR1_DQ[19]

AA7

DDR1_DQ[36]/DDR1_DQ[20]

AA8

DDR1_DQ[37]/DDR1_DQ[21]

AC8

DDR1_DQ[38]/DDR1_DQ[22]

AC7

DDR1_DQ[39]/DDR1_DQ[23]

W8

DDR1_DQ[40]/DDR1_DQ[24]

W7

DDR1_DQ[41]/DDR1_DQ[25]

V10

DDR1_DQ[42]/DDR1_DQ[26]

V11

DDR1_DQ[43]/DDR1_DQ[27]

W11

DDR1_DQ[44]/DDR1_DQ[28]

W10

DDR1_DQ[45]/DDR1_DQ[29]

V7

DDR1_DQ[46]/DDR1_DQ[30]

V8

DDR1_DQ[47]/DDR1_DQ[31]

R11

DDR1_DQ[48]

P11

DDR1_DQ[49]

P7

DDR1_DQ[50]

R8

DDR1_DQ[51]

R10

DDR1_DQ[52]

P10

DDR1_DQ[53]

R7

DDR1_DQ[54]

P8

DDR1_DQ[55]

L11

DDR1_DQ[56]

M11

DDR1_DQ[57]

L7

DDR1_DQ[58]

M8

DDR1_DQ[59]

L10

DDR1_DQ[60]

M10

DDR1_DQ[61]

M7

DDR1_DQ[62]

L8

DDR1_DQ[63]

AW11

DDR1_ECC[0]

AY11

DDR1_ECC[1]

AY8

DDR1_ECC[2]

AW8

DDR1_ECC[3]

AY10

DDR1_ECC[4]

AW10

DDR1_ECC[5]

AY7

DDR1_ECC[6]

AW7

DDR1_ECC[7]

G1

DDR_RCOMP[0]

H1

DDR_RCOMP[1]

J2

DDR_RCOMP[2]

SKL-H_BGA1440

@

DDR CHANNEL B

M_CLK_DDR0 [14] M_CLK_DDR#0 [14] M_CLK_DDR#1 [14] M_CLK_DDR1 [14]

DDR_CKE0_DIMMA [14] DDR_CKE1_DIMMA [14]

DDR_CS0_DIMMA# [14] DDR_CS1_DIMMA# [14]

M_ODT0 [14] M_ODT1 [14]

DDR_A_BS0 [14] DDR_A_BS1 [14] DDR_A_BG0 [14]

DDR_A_RAS# [14] DDR_A_WE# [14] DDR_A_CAS# [14]

DDR_A_BG1 [14] DDR_A_ACT# [14] DDR_B_ACT# [15]

DDR_A_PAR [14] DDR_A_ALERT# [14]

RH148 121_0402_1% RH149 75_0402_1% RH150 100_0402_1%

DDR_A_D0 DDR_A_D1

DDR_A_D[0..63][14] DDR_A_MA[0..13][14] DDR_A_DQS#[0..7][14] DDR_A_DQS[0..7][14]

D D

C C

B B

DDR_B_D[0..63][15] DDR_B_MA[0..13][15] DDR_B_DQS#[0..7][15] DDR_B_DQS[0..7][15]

DDR_A_D2 DDR_A_D7 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D3 DDR_A_D9 DDR_A_D13 DDR_B_D8 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D8 DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D16 DDR_A_D23 DDR_A_D19 DDR_A_D21 DDR_A_D17 DDR_A_D22 DDR_A_D18 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D45 DDR_A_D43 DDR_A_D47 DDR_A_D41 DDR_A_D40 DDR_A_D42 DDR_A_D46 DDR_A_D53 DDR_A_D51 DDR_A_D49 DDR_A_D55 DDR_A_D52 DDR_A_D54 DDR_A_D48 DDR_A_D50 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D63 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D59

DDR0_DQ[0]

BT6

DDR0_DQ[1]

BP3

DDR0_DQ[2]

BR3

DDR0_DQ[3]

BN5

DDR0_DQ[4]

BP6

DDR0_DQ[5]

BP2

DDR0_DQ[6]

BN3

DDR0_DQ[7]

BL4

DDR0_DQ[8]

BL5

DDR0_DQ[9]

BL2

DDR0_DQ[10]

BM1

DDR0_DQ[11]

BK4

DDR0_DQ[12]

BK5

DDR0_DQ[13]

BK1

DDR0_DQ[14]

BK2

DDR0_DQ[15]

BG4

DDR0_DQ[16]/DDR0_DQ[32]

BG5

DDR0_DQ[17]/DDR0_DQ[33]

BF4

DDR0_DQ[18]/DDR0_DQ[34]

BF5

DDR0_DQ[19]/DDR0_DQ[35]

BG2

DDR0_DQ[20]/DDR0_DQ[36]

BG1

DDR0_DQ[21]/DDR0_DQ[37]

BF1

DDR0_DQ[22]/DDR0_DQ[38]

BF2

DDR0_DQ[23]/DDR0_DQ[39]

BD2

DDR0_DQ[24]/DDR0_DQ[40]

BD1

DDR0_DQ[25]/DDR0_DQ[41]

BC4

DDR0_DQ[26]/DDR0_DQ[42]

BC5

DDR0_DQ[27]/DDR0_DQ[43]

BD5

DDR0_DQ[28]/DDR0_DQ[44]

BD4

DDR0_DQ[29]/DDR0_DQ[45]

BC1

DDR0_DQ[30]/DDR0_DQ[46]

BC2

DDR0_DQ[31]/DDR0_DQ[47]

AB1

DDR0_DQ[32]/DDR1_DQ[0]

AB2

DDR0_DQ[33]/DDR1_DQ[1]

AA4

DDR0_DQ[34]/DDR1_DQ[2]

AA5

DDR0_DQ[35]/DDR1_DQ[3]

AB5

DDR0_DQ[36]/DDR1_DQ[4]

AB4

DDR0_DQ[37]/DDR1_DQ[5]

AA2

DDR0_DQ[38]/DDR1_DQ[6]

AA1

DDR0_DQ[39]/DDR1_DQ[7]

V5

DDR0_DQ[40]/DDR1_DQ[8]

V2

DDR0_DQ[41]/DDR1_DQ[9]

U1

DDR0_DQ[42]/DDR1_DQ[10]

U2

DDR0_DQ[43]/DDR1_DQ[11]

V1

DDR0_DQ[44]/DDR1_DQ[12]

V4

DDR0_DQ[45]/DDR1_DQ[13]

U5

DDR0_DQ[46]/DDR1_DQ[14]

U4

DDR0_DQ[47]/DDR1_DQ[15]

R2

DDR0_DQ[48]/DDR1_DQ[32]

P5

DDR0_DQ[49]/DDR1_DQ[33]

R4

DDR0_DQ[50]/DDR1_DQ[34]

P4

DDR0_DQ[51]/DDR1_DQ[35]

R5

DDR0_DQ[52]/DDR1_DQ[36]

P2

DDR0_DQ[53]/DDR1_DQ[37]

R1

DDR0_DQ[54]/DDR1_DQ[38]

P1

DDR0_DQ[55]/DDR1_DQ[39]

M4

DDR0_DQ[56]/DDR1_DQ[40]

M1

DDR0_DQ[57]/DDR1_DQ[41]

L4

DDR0_DQ[58]/DDR1_DQ[42]

L2

DDR0_DQ[59]/DDR1_DQ[43]

M5

DDR0_DQ[60]/DDR1_DQ[44]

M2

DDR0_DQ[61]/DDR1_DQ[45]

L5

DDR0_DQ[62]/DDR1_DQ[46]

L1

DDR0_DQ[63]/DDR1_DQ[47]

BA2

DDR0_ECC[0]

BA1

DDR0_ECC[1]

AY4

DDR0_ECC[2]

AY5

DDR0_ECC[3]

BA5

DDR0_ECC[4]

BA4

DDR0_ECC[5]

AY1

DDR0_ECC[6]

AY2

DDR0_ECC[7]

DDR CHANNEL A

SKL-H_BGA1440

@

UH1A

BR6

REV = 1

?

SKYLAKE_HALO

BGA1440

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSP[5]/DDR1_DQSP[3]

2 OF 14

DDR1_CKP[0] DDR1_CKN[0] DDR1_CKN[1]

DDR1_CKP[1] DDR1_CLKP[2] DDR1_CLKN[2] DDR1_CLKP[3] DDR1_CLKN[3]

DDR1_CKE[0]

DDR1_CKE[1]

DDR1_CKE[2]

DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1]

DDR1_CS#[2]

DDR1_CS#[3]

DDR1_ODT[0]

DDR1_ODT[1]

DDR1_ODT[2]

DDR1_ODT[3]

DDR1_MA[3] DDR1_MA[4]

DDR1_PAR

DDR1_ALERT#

DDR1_DQSN[6] DDR1_DQSN[7]

DDR1_DQSP[6] DDR1_DQSP[7]

DDR1_DQSP[8] DDR1_DQSN[8]

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

?

AM9 AN9 AM8 AM7 AM11 AM10 AJ10 AJ11

AT8 AT10 AT7 AT11

AF11 AE7 AF10 AE10

AF7 AE8 AE9 AE11

AH10 AH11 AF8

AH8 AH9 AR9

AJ9 AK6 AK5 AL5 AL6 AM6 AN7 AN10 AN8 AR11 AH7 AN11 AR10 AF9 AR7 AT9

AJ7 AR8

BP9 BL9 BG9 BC9 AC9 W9 R9 M9

BR9 BJ9 BF9 BB9 AA9 V9 P9 L9

AW9 AY9

BN13 BP13 BR13

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

M_CLK_DDR2 [15] M_CLK_DDR#2 [15] M_CLK_DDR#3 [15] M_CLK_DDR3 [15]

DDR_CKE2_DIMMB [15] DDR_CKE3_DIMMB [15]

DDR_CS2_DIMMB# [15] DDR_CS3_DIMMB# [15]

M_ODT2 [15] M_ODT3 [15]

DDR_B_RAS# [15] DDR_B_WE# [15] DDR_B_CAS# [15]

DDR_B_BS0 [15] DDR_B_BS1 [15] DDR_B_BG0 [15]

DDR_B_BG1 [15]

DDR_B_PAR [15] DDR_B_ALERT# [15]

+V_DDR_REFA_R +V_DDR_REFB_R

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Title

PROCESSOR(3/7) DDRIII

Size Document Number Rev

C

Date: Sheet of

1

8 71Thursday, August 06, 2015

0.1(X00)

5

CFG Straps for Processor

4

+VCCST

3

2

1

Stall reset sequence after PCU PLL lock until de-asserted

CFG0

D D

1 = (Default) Normal Operation; No stall.

*

0 = Stall.

1 2

CFG0

@

RH183 1K_0402_5%

PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS

CFG2

Display Port Presence Strap

C C

CFG4

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

*

1 2

CFG2

RH184 1K_0402_5%

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

*

1 2

CFG4

RH185 1K_0402_5%

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

CFG[6:5]

B B

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

1 2

CFG5

@

RH186 1K_0402_5%

1 2

CFG6

@

RH187 1K_0402_5%

1 2

RH163 1K_0402_5%

1 2

RH156 51_0402_5%

1 2

RH164 1K_0402_5%

1 2

RH151 100_0402_5%

1 2

RH152 56.2_0402_1%

1 2

RH570 49.9_0402_1%

+VCCSTG

1 2

RH165 1K_0402_5%

SM_PG_CTRL[59]

PEG DEFER TRAINING

CFG7

1: (Default) PEG Train immediately following xxRESETB de assertion

*

0: PEG Wait for BIOS for training

1 2

CFG7

A A

@

RH188 1K_0402_5%

H_THERMTRIP#_R

XDP_PREQ#

@

H_VCCST_PWRGD

VR_SVID_DATA

VR_SVID_ALERT#

H_CATERR#

@

1 2

RH153 220_0402_5%

1 2

RH158 499_0402_1%

1 2

RH154 60.4_0402_1%

1 2

RH155 20_0402_5%

1 2

RH190 0_0402_5%@

1 2

RH519 0_0402_5%@

1 2

RH167 30_0402_5%

1 2

RH192 30_0402_5%

H_PROCHOT#

+1.2V_DDR

1

2

+3VS

12

X06.26

@

CH197

0.1U_0402_10V7K

RH525 220K_0402_5%

VR_SVID_ALERT#[64]

VR_SVID_CLK[64] VR_SVID_DATA[64] H_PROCHOT#[48,56,64]

H_VCCST_PWRGD[6,34]

H_CPUPWRGD[18] PLTRST_CPU#[6,16]

H_PM_SYNC_R[16]

H_PM_DOWN[16]

H_PECI[16,48]

H_THERMTRIP#_R[16,48] PROC_DETECT#[16]

UC1

5

VCC

4

Y

GND

74AUP1G07GW_TSSOP5

PCH_TRIGGER[22] CPU_TRIGGER[22]

VR_SVID_ALERT# VR_SVID_DATA

H_VCCST_PWRGD

H_PM_DOWN

1

NC

2

DDR_VTT_PG_CTRL

A

3

PCH_TRIGGER PCH_TRIGGER_R CPU_TRIGGER CPU_TRIGGER_R

PCH_CPU_BCLK_P[17] PCH_CPU_BCLK_N[17]

PCH_CPU_PCIBCLK_P[17] PCH_CPU_PCIBCLK_N[17]

CPU_24MHZ_P[17] CPU_24MHZ_N[17]

VR_SVID_ALERT#_R

H_PROCHOT#_RH_PROCHOT# DDR_VTT_PG_CTRL

VCCST_PWRGD_CPU

PLTRST_CPU# H_PM_SYNC_R H_PM_DOWN_R H_PECI_R H_THERMTRIP#_R

H_CATERR#

BN35

BN33

AE29 AA14

BR35 BR31 BH30

BL34

D1 E1 E3 E2

BR1 BT2

J24

H24

N29 R14

A36 A37

H23

J23 F30

E30 B30

C30

G3 J3

T39PAD~D@ T40PAD~D@ T41PAD~D@ T42PAD~D@ T68 PAD~D @

T43PAD~D@

T45PAD~D@ T46PAD~D@

T47PAD~D@ T48PAD~D@ T49PAD~D@

T50PAD~D@ T75 PAD~D @ T51PAD~D@ T52PAD~D@ T53PAD~D@

T57PAD~D@ T58PAD~D@

T59PAD~D@ T60PAD~D@

T61PAD~D@ T62PAD~D@

T63PAD~D@ T64PAD~D@ T65PAD~D@

B31 A32

D35 C36

E31 D31

BH31 BH32 BH29 BR30

BT13

H13

BT31 BP35

BM34

BP31 BT34

J31

BR33

BN1

BM30

UH1K

RSVD_TP RSVD_TP RSVD_TP RSVD_TP

RSVD_TP RSVD_TP

RSVD RSVD

RSVD RSVD RSVD

RSVD RSVD RSVD RSVD

RSVD RSVD

PROC_TRIGIN PROC_TRIGOUT

RSVD RSVD

RSVD RSVD RSVD

SKL-H_BGA1440

@

UH1E

BCLKP BCLKN

PCI_BCLKP PCI_BCLKN

CLK24P CLK24N

VIDALERT# VIDSCK VIDSOUT PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD PROCPWRGD

RESET# PM_SYNC PM_DOWN PECI THERMTRIP#

SKTOCC# PROC_SELECT#

CATERR#

SKL-H_BGA1440

@

SKYLAKE_HALO

BGA1440

REV = 1

SKYLAKE_HALO

BGA1440

5 OF 14

?

11 OF 14

?

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8]

CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[17] CFG[16] CFG[19] CFG[18]

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

PROC_TDO

PROC_TDI PROC_TMS PROC_TCK

PROC_TRST# PROC_PREQ# PROC_PRDY#

CFG_RCOMP

?

RSVD_TP RSVD_TP

RSVD RSVD

RSVD RSVD RSVD

NCTF NCTF NCTF NCTF NCTF NCTF

BN25 BN27 BN26 BN28 BR20 BM20 BT20 BP20 BR23 BR22 BT23 BT22 BM19 BR19 BP19 BT19

BN23 BP23 BP22 BN22

BR27 BT27 BM31 BT30

BT28 BL32 BP28 BR28

BP30 BL30 BP27

BT25

VSS

?REV = 1

BM33 BL33

BJ14 BJ13

BK28 BJ28

BJ18 BJ16

BK16

BK24 BJ24

BK21 BJ21

BT17 BR17

BK18 BJ34

BJ33

G13 AJ8 BL31

B2 B38 BP1 BR2 C1 C38

CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG17 CFG16 CFG19 CFG18

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9

CPU_XDP_TDO CPU_XDP_TDI CPU_XDP_TMS CPU_XDP_TCK

CPU_XDP_TRST# XDP_PREQ# XDP_PRDY#

CFG_RCOMP

CFG0 [6] CFG1 [6] CFG2 [6] CFG3 [6] CFG4 [6] CFG5 [6] CFG6 [6] CFG7 [6] CFG8 [6] CFG9 [6] CFG10 [6] CFG11 [6] CFG12 [6] CFG13 [6] CFG14 [6] CFG15 [6]

CFG17 [6] CFG16 [6] CFG19 [6] CFG18 [6]

XDP_BPM#0 [6] XDP_BPM#1 [6]

12

RH59

49.9_0402_1%

T66 PAD~D @ T67 PAD~D @

T69 PAD~D @ T70 PAD~D @T44PAD~D@

T71 PAD~D @

T73 PAD~D @ T74 PAD~D @

T76 PAD~D @ T77 PAD~D @

T78 PAD~D @ T79 PAD~D @

T80 PAD~D @

T81 PAD~D @ T82 PAD~D @

T83 PAD~D @ T84 PAD~D @

T85 PAD~D @ T86 PAD~D @ T87 PAD~D @ T88 PAD~D @ T89 PAD~D @ T90 PAD~D @

CPU_XDP_TDO [6] CPU_XDP_TDI [6] CPU_XDP_TMS [6] CPU_XDP_TCK [6]

CPU_XDP_TRST# [6,22] XDP_PREQ# [6,22] XDP_PRDY# [6,22]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PROCESSOR(4/7) RSVD,CFG

Size Document Number Rev

C

Date: Sheet of

1

9 71Thursday, August 06, 2015

0.1(X00)

5

D D

SKYLAKE_HALO

UH1G

AA13 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AA38 AB29 AB30 AB31 AB32 AB35 AB36 AB37 AB38 AC13 AC14 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AC36 AD13

C C

B B

AD14 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AE13 AE14 AE30 AE31 AE32 AE35 AE36 AE37 AE38

AF35 AF36 AF37 AF38

K13 K14 L13 N13 N14 N30 N31 N32 N35 N36 N37 N38

P13

BGA1440

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

SKL-H_BGA1440

REV = 1 ?

@

7 OF 14

?

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCC_SENSE

VSS_SENSE

4

+VCC_CORE+VCC_CORE

V32 V33 V34 V35 V36 V37 V38 W13 W14 W29 W30 W31 W32 W35 W36 W37 W38 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 L14 P29 P30 P31 P32 P33 P34 P35 P36 R13 R31 R32 R33 R34 R35 R36 R37 R38 T29 T30 T31 T32 T35 T36 T37 T38 U29 U30 U31 U32 U33 U34 U35 U36 V13 V14 V31 P14

AG37 AG38

+VCC_CORE

12

RH197 100_0402_1%

1 2

RH198 0_0402_5%@

1 2

RH465 0_0402_5%@

RH466 100_0402_1%

3

VCC_SENSE [64]

VSS_SENSE [64]

X06.26

1 2

RH166 49.9_0402_1%@ RH57 49.9_0402_1%@

1 2 1 2

RH58 49.9_0402_1%@

2

UH1J

BJ17

VCCOPC

BJ19

VCCOPC

BJ20

VCCOPC

BK17

VCCOPC

BK19

VCCOPC

BK20

VCCOPC

BL16

VCCOPC

BL17

VCCOPC

BL18

VCCOPC

BL19

VCCOPC

BL20

VCCOPC

BL21

VCCOPC

BM17

VCCOPC

BN17

VCCOPC

BJ23

RSVD

BJ26

RSVD

BJ27

RSVD

BK23

RSVD

BK26

RSVD

BK27

RSVD

BL23

RSVD

BL24

RSVD

BL25

RSVD

BL26

RSVD

BL27

RSVD

BL28

RSVD

BM24

RSVD

BL15

VCCOPC_SENSE

BM16

VSSOPC_SENSE

BL22

RSVD

BM22

RSVD

BP15

VCCEOPIO

BR15

VCCEOPIO

BT15

VCCEOPIO

BP16

RSVD

BR16

RSVD

BT16

RSVD

BN15

VCCEOPIO_SENSE

BM15

VSSEOPIO_SENSE

BP17

RSVD

BN16

RSVD

BM14

VCC_OPC_1P8

BL14

VCC_OPC_1P8

BJ35

RSVD

BJ36

RSVD

AT13

ZVM#

AW13

MSM#

AU13

ZVM2#

AY13

MSM2#

BT29

OPC_RCOMP

BR25

OPCE_RCOMP

BP25

OPCE_RCOMP2

SKL-H_BGA1440

REV = 1

@

SKYLAKE_HALO

BGA1440

1

?

10 OF 14

?

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Title

PROCESSOR(5/7) PWR,BYPASS

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

10 71Thursday, August 06, 2015

1

0.1(X00)

5

4

3

2

1

+VCCSTG

D D

+VCCSA

?

SKYLAKE_HALO

UH1I

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

BGA1440

VCCPLL_OC VCCPLL_OC

VCCSA_SENSE

VSSSA_SENSE VCCIO_SENSE

VSSIO_SENSE

J30 K29 K30 K31 K32 K33 K34 K35 L31 L32 L35 L36 L37 L38 M29 M30 M31 M32 M33 M34

AG12

M35 M36

G15 G17 G19 G21 H15 H16 H17 H19 H20 H21 H26 H27 J15 J16 J17 J19 J20 J21 J26 J27

C C

+VCCIO

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VDDQC

VCCST VCCSTG VCCSTG

VCCPLL VCCPLL

+1.2V_DDR

AA6 AE12 AF5 AF6 AG5 AG9 AJ12 AL11 AP6 AP7 AR12 AR6 AT12 AW6 AY6 J5 J6 K12 K6 L12 L6 R6 T6 W6

Y12 BH13

G11

H30 H29 G30 H28

J28

M38 M37

H14 J14

+1.2V_DDR

12

X06.26

RH473

@

0_0402_5%

+VCCST

RH201 100_0402_1% RH202 0_0402_5%@ RH470 0_0402_5%@ RH469 100_0402_1%

1 2

RH530 0_0402_5%@

+VCCSTG

+VCCST

1 2 1 2 1 2 1 2

+1.2V_DDR+1.2V_VCCPLL_OC

+VCCSA

VCCSA_SENSE [64]

VSSSA_SENSE [64]

X06.26

VCCIO_SENSE [61]

VSSIO_SENSE [61]

10U_0603_6.3V6M

CH102

1

2

10U_0603_6.3V6M

CH104

CH103

1

2

1U_0402_6.3V6K

CH105

1

2

1U_0402_6.3V6K

CH106

+VCCST+VCCIO

+1.2V_DDR

1

2

1U_0402_6.3V6K

CH107

1

2

22U_0603_6.3V6M

1

CH129

2

+1.2V_DDR

1U_0402_6.3V6K

CH108

CH109

1

2

22U_0603_6.3V6M

1

CH132

CH131

CH130

2

22U_0603_6.3V6M

1

2

22U_0603_6.3V6M

CH121

CH118

CH124

1

2

+VCCSA

10U_0603_6.3V6M

1U_0402_6.3V6K

CH110

1

2

+VCCSA +VCCSA

1U_0402_6.3V6K

1

2

10U_0603_6.3V6M

22U_0603_6.3V6M

CH119

CH120

1

2

1

2

10U_0603_6.3V6M

CH111

CH112

CH113

1

2

1U_0402_6.3V6K

CH133

CH134

1

2

10U_0603_6.3V6M

CH122

CH123

1

2

10U_0603_6.3V6M

CH114

CH115

CH116

1

2

1U_0402_6.3V6K

CH135

CH117

1

2

330U_B2_2.5VM_R9M

47U_0603_6.3V6M

1

CH138

CH136

1

+

2

X06.08

10U_0603_6.3V6M

CH125

1

2

10U_0603_6.3V6M

CH127

CH126

CH128

1

2

B B

A A

SKL-H_BGA1440

@

5

9 OF 14

?REV = 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PROCESSOR(6/7) PWR

Size Document Number Rev

Custom

Date: Sheet of

1

11 71Thursday, August 06, 2015

0.1(X00)

5

4

3

2

1

+VCCGT

?

SKYLAKE_HALO

UH1H

D D

C C

B B

BG34 BG35 BG36 BH33 BH34 BH35 BH36 BH37 BH38

BJ37 BJ38 BL36

BL37 BM36 BM37 BN36 BN37 BN38 BP37 BP38 BR37 BT37 BE38 BF13 BF14 BF29 BF30 BF31 BF32 BF35 BF36 BF37 BF38 BG29 BG30 BG31 BG32 BG33

BC36

BC37

BC38

BD13

BD14

BD29

BD30

BD31

BD32

BD33

BD34

BD35

BD36

BE31

BE32 BE37

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

SKL-H_BGA1440

@

BGA1440

REV = 1

8 OF 14

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

+VCCGT +VCCGT

AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36 AW14 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38 AY29 AY30 AY31 AY32 AY35 AY36 AY37 AY38 BA13 BA14 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BB13 BB14 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BC29 BC30 BC31 BC32 BC35 BE33 BE34 BE35 BE36

?

AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 AJ36 AK31 AK32 AK33 AK34 AK35 AK36 AK37 AK38 AL13 AL29 AL30 AL31 AL32 AL35 AL36 AL37

AL38 AM13 AM14 AM29 AM30 AM31 AM32 AM33 AM34 AM35 AM36

AN13

AN14

AN31

AN32

AN33

AN34

AN35

AN36

AN37

AN38

AP13

AP14

AP29

AP30

AP31

AP32

AP35

AP36

AP37

AP38

AR29

AR30

AR31

AR32

AR33

AR34

AR35

AR36

AT14

AT31

AT32

AT33

AT34

AT35

AT36

AT37

AT38

AU14

AU29

AU30

AU31

AU32

AU35

AU36

AU37

AU38

UH1N

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

SKL-H_BGA1440

REV = 1 @

?

SKYLAKE_HALO

BGA1440

14 OF 14

VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX

VCCGT_SENSE

VSSGTX_SENSE

VSSGT_SENSE

VCCGTX_SENSE

AF29 AF30 AF31 AF32 AF33 AF34 AG13 AG14 AG31 AG32 AG33 AG34 AG35 AG36 AH13 AH14 AH29 AH30 AH31 AH32 AJ13 AJ14

+VCCGT

12

RH203 100_0402_1%

AH38 AH35 AH37 AH36

?

1 2

RH204 0_0402_5%@

1 2

RH471 0_0402_5%@

12

RH472 100_0402_1%

VCCGT_SENSE [64] VSSGT_SENSE [64]

X06.26

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

PROCESSOR(2/7) PM,XDP,CLK

12 71Thursday, August 06, 2015

1

12 71Thursday, August 06, 2015

0.1(X00)

5

4

3

2

1

?

SKYLAKE_HALO

UH1F

BGA1440

Y38

VSS

Y37

VSS

Y14

VSS

Y13

W34 W33 W12

M14 M13 M12

Y11

Y10

Y9 Y8 Y7

W5 W4 W3 W2

W1 V30 V29

V12

V6 U38 U37

U6

T34 T33 T14 T13 T12

T11 T10

T9 T8 T7 T5 T4 T3 T2

T1 R30 R29 R12 P38 P37

P12

P6 N34 N33 N12 N11 N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

M6

L34 L33 L30

L29 K38 K11 K10

K9 K8 K7 K5 K4 K3 K2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-H_BGA1440

REV = 1

@

6 OF 14

D D

C C

B B

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NCTFVSS

K1 J36 J33 J32 J25 J22 J18 J10 J7 J4 H35 H32 H25 H22 H18 H12 H11 G28 G26 G24 G23 G22 G20 G18 G16 G14 G12 G10 G9 G8 G6 G5 G4 F36 F31 F29 F27 F25 F23 F21 F19 F17 F15 F13 F11 F9 F8 F5 F4 F3 F2 E38 E35 E34 E9 E4 D33 D30 D28 D26 D24 D22 D20 D18 D16 D14 D12 D10 D9 D6 D3 C37 C31 C29 C27

D38

?

BT32 BT26 BT24 BT21 BT18 BT14 BT12

BR36 BR34 BR29 BR26 BR24 BR21 BR18 BR14 BR12

BR7 BP34 BP33 BP29 BP26 BP24 BP21 BP18 BP14 BP12

BN34 BN31 BN30 BN29 BN24 BN21 BN20 BN19 BN18 BN14 BN12

BN9

BN7

BN4

BN2

BM38 BM35 BM28 BM27 BM26 BM23 BM21 BM13 BM12

BM9

BM6

BM2

BL29 BK29 BK15 BK14

BJ32

BJ31

BJ25

BJ22 BH14 BH12

BH9 BH8 BH5 BH4

BH1 BG38 BG13 BG12 BF33 BF12 BE29

BD9 BC34 BC12 BB12

C17 C13

C9

BT9 BT5

BP7

BE6

REV = 1 @

SKYLAKE_HALO

UH1L

BGA1440

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-H_BGA1440

?

12 OF 14

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS

SKYLAKE_HALO

UH1M

AW5 AW4 AW3 AW2 AW1

AM5 AM4 AM3 AM2 AM1

BB4 BB3 BB2 BB1

BA9 BA8 BA7 BA6

AU9 AU8 AU7 AU6

AT6

AR5 AR4 AR3 AR2 AR1

AP9 AP8

AN6 AN5

AL9 AL8 AL7 AL4

B9

BGA1440

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-H_BGA1440

REV = 1

@

?

13 OF 14

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS

AK30 AK29 AK4 AJ38 AJ37 AJ6 AJ5 AJ4 AJ3 AJ2 AJ1 AH34 AH33 AH12 AH6 AG30 AG29 AG11 AG10 AG8 AG7 AG6 AF14 AF13 AF12 AF4 AF3 AF2 AF1 AE34 AE33 AE6 AD30 AD29 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AC38 AC37 AC12 AC6 AC5 AC4 AC3 AC2 AC1 AB34 AB33 AB6 AA30 AA29 AA12 A30 A28 A26 A24 A22 A20 A18 A16 A14 A12 A10 A9 A6

B37 B3 A34 A4 A3

?

C25 C23 C21 C19 C15 C11 C8 C5 BM29 BM25 BM18 BM11 BM8 BM7 BM5 BM3 BL38 BL35 BL13 BL6 BK25 BK22 BK13 BK6 BJ30 BJ29 BJ15 BJ12 BH11 BH10 BH7 BH6 BH3 BH2 BG37 BG14 BG6 BF34 BF6 BE30 BE5 BE4 BE3 BE2 BE1 BD38 BD37 BD12 BD11 BD10 BD8 BD7 BD6 BC33 BC14 BC13 BC6 BB30 BB29 BB6 BB5

C2 BT36 BT35 BT4 BT3 BR38

?

BA38 BA37 BA12 BA11 BA10

AY34 AY33 AY14

AY12 AW30 AW29 AW12

AV38 AV37 AU34 AU33 AU12 AU11 AU10

AT30

AT29

AR38 AR37 AR14 AR13

AP34 AP33 AP12 AP11 AP10

AN30 AN29 AN12

AM38 AM37 AM12

AL34

AL33

AL14

AL12

AL10

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(7/7) VSS

1

0.1(X00)

13 71Thursday, August 06, 2015

0.1(X00)

5

Layout Note: Place near JDIMM1.257,259

+2.5V_MEM

D D

Layout Note: Place near JDIMM1

10U_0603_6.3V6M

1

CD10

CD9

2

1U_0402_6.3V6K

CD4

CD3

1

2

Layout Note: Place near JDIMM1.258

+0.6VS

10U_0603_6.3V6M

1U_0402_6.3V6K

CD12

CD13

1

2

+1.2V_DDR

1U_0402_6.3V6K

CD1

1

2

C C

1U_0402_6.3V6K

CD2

1

2

1U_0402_6.3V6K

CD75

CD74

1

2

1U_0402_6.3V6K

CD76

CD77

1

2

1U_0402_6.3V6K

CD78

CD79

1

2

+1.2V_DDR

10U_0603_6.3V6M

1

CD5

CD6

2

B B

+3VS +3VS +3VS

12

RD1

@

0_0402_5%

12

RD28

@

0_0402_5%

+V_DDR_REFA_R

1

CD7

CD8

CD70

2

12

RD2

@

0_0402_5%

12

RD29

@

0_0402_5%

+1.2V_DDR

20mil

1 2

RH484 2_0402_1%

A A

1

CH101

0.022U_0402_25V7K

2

12

RH211

24.9_0402_1%

1

2

12

1K_0402_1%

12

1K_0402_1%

10U_0603_6.3V6M

CD71

RH206

RH209

10U_0603_6.3V6M

1

2

+V_DDR_REFA

10U_0603_6.3V6M

1

CD72

CD73

2

12

RD3

@

0_0402_5%

12

RD30

@

0_0402_5%

10U_0603_6.3V6M

CD14

X06.16

10U_0603_6.3V6M

CD15

1

2

1

+

CD11 220U_D7_2VM_R6M

2

4

DDR4_DRAMRST#DIMM_CHA_SA0 DIMM_CHA_SA1 DIMM_CHA_SA2

DDR_A_D[0..63][8] DDR_A_MA[0..13][8] DDR_A_DQS#[0..7][8] DDR_A_DQS[0..7][8]

Layout Note: Place near JDIMM1.255

+3VS

.1U_0402_16V7K

CD16

1

CD17

2.2U_0402_6.3V6M

2

0_0402_5%

1 2

RD31

@

X06.12

+1.2V_DDR

12

RD35 470_0402_1%

@

+3VS

3

+1.2V_DDR

DDR_A_D5 DDR_A_D1

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D7 DDR_A_D3 DDR_A_D13 DDR_A_D9

DDR_A_D15 DDR_A_D10 DDR_A_D21 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D23 DDR_A_D19 DDR_A_D29 DDR_A_D25

DDR_A_D30 DDR_A_D26

DDR_CKE0_DIMMA[8]

DDR_A_BG1[8] DDR_A_BG0[8]

M_CLK_DDR0[8] M_CLK_DDR#0[8]

DDR_A_PAR[8] DDR_A_BS1[8]

DDR_CS0_DIMMA#[8]

DDR_A_WE#[8] M_ODT0[8]

DDR_CS1_DIMMA#[8]

M_ODT1[8]

H_DRAMRST# [18]DDR4_DRAMRST#[15]

.1U_0402_16V7K

CD69

1

2

DDR_CKE0_DIMMA DDR_A_BG1

DDR_A_BG0

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA6

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_PAR DDR_A_BS1

DDR_CS0_DIMMA# DDR_A_WE#

M_ODT0 DDR_CS1_DIMMA#

M_ODT1

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D38 DDR_A_D34 DDR_A_D44 DDR_A_D40

+1.2V_DDR

DDR_A_D46 DDR_A_D47 DDR_A_D42 DDR_A_D43

DDR_A_D49 DDR_A_D48 DDR_A_DQS#6

DDR_A_DQS6 DDR_A_D55 DDR_A_D51 DDR_A_D61 DDR_A_D56

+1.2V_DDR

DDR_A_D62 DDR_A_D63

PCH_SMBCLK[6,15,18,45] PCH_SMBDATA [6,15,18,45]

DDR_A_D58 DDR_A_D59

JDIMM1

JP?

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5 DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25 DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3_n/DBI3_n

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45 DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n ,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

BELLW_SD-80886-1021

VSS2 VSS4 VSS6 VSS7 VSS9

VSS11

DQ12

VSS13 VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26 VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

DQS3_t

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46 VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

EVENT_n/NF

VDD10 CK1_t/NF CK1_c/NF

VDD12

A10/AP

VDD14

RAS_n/A1 6

VDD16

CAS_n/A1 5

VDD18

C0/CS2_n/NC

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

CONN@

2

+1.2V_DDR

2 4

DQ4

6 8

DQ0

10 12 14 16

DQ6

18 20

DQ2

22 24 26 28

DQ8

30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120

A11

122

A7

124 126

A5

128

A4

130 132

A2

134 136 138 140 142 144

A0

146 148 150

BA0

152 154 156 158

A13

160 162 164 166

SA2

168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254

SDA

256

SA0

258

VTT

260

SA1

262

DDR_A_D4 DDR_A_D0

DDR_A_D6 DDR_A_D2 DDR_A_D12 DDR_A_D8 DDR_A_DQS#1

DDR_A_DQS1 DDR_A_D14 DDR_A_D11 DDR_A_D20 DDR_A_D16

DDR_A_D22 DDR_A_D18 DDR_A_D28 DDR_A_D24

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D31 DDR_A_D27

DDR4_DRAMRST# DDR_CKE1_DIMMA

DDR_A_ALERT#

DDR_A_MA11 DDR_A_MA7

DDR_A_MA5 DDR_A_MA4

DDR_A_MA2

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_MA0 DDR_A_MA10

DDR_A_BS0 DDR_A_RAS#

DDR_A_CAS# DDR_A_MA13

DIMM_CHA_SA2 DDR_A_D36DDR_A_D37

DDR_A_D32DDR_A_D33

DDR_A_D39

DDR_A_D35

DDR_A_D45

DDR_A_D41

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D53DDR_A_D52

DDR_A_D54

DDR_A_D50

DDR_A_D60

DDR_A_D57

DDR_A_DQS#7 DDR_A_DQS7

PCH_SMBDATAPCH_SMBCLK DIMM_CHA_SA0

DIMM_CHA_SA1

+1.2V_DDR

DDR_CKE1_DIMMA [8] DDR_A_ACT# [8]

DDR_A_ALERT# [ 8]

M_CLK_DDR1 [8] M_CLK_DDR#1 [8]

DDR_A_BS0 [8] DDR_A_RAS# [8]

DDR_A_CAS# [8]

+V_DDR_REFA

.1U_0402_16V7K

CD18

1

2

1

All VREF traces should have 10 mil trace width

+0.6VS+2.5V_MEM

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONIC S, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONIC S, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONIC S, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMA

DDRIII DIMMA LA-C361P

LA-C361P

1

14 71Thursday, August 06, 2015

0.1(X00)

5

4

3

2

1

JDIMM2

JP?

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5 DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25 DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3_n/DBI3_n

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45 DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n ,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

BELLW_SD-80886-1021 CONN@

2011/08/25 2012/07/25

EVENT_n/NF

C0/CS2_n/NC

DM4_n/DBI4_n

DM6_n/DBI6_n

Compal Secret Data

VSS2

DQ4

VSS4

DQ0

VSS6 VSS7

DQ6

VSS9

DQ2

VSS11

DQ12

VSS13

DQ8

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26 VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

DQS3_t

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46 VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A10/AP

VDD14

BA0

RAS_n/A1 6

VDD16

CAS_n/A1 5

VDD18

VREFCA

SA2

VSS54

DQ36

VSS56

DQ32

VSS58 VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78 VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

SDA SA0

SA1

GND2

Deciphered Date

+1.2V_DDR

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120

A11

122

A7

124 126

A5

128

A4

130 132

A2

134 136 138 140 142 144

A0

146 148 150 152 154 156 158

A13

160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258

VTT

260 262

2

DDR_B_D4 DDR_B_D0

DDR_B_D6 DDR_B_D2 DDR_B_D12 DDR_B_D8 DDR_B_DQS#1

DDR_B_DQS1 DDR_B_D14 DDR_B_D11 DDR_B_D20 DDR_B_D16

DDR_B_D22 DDR_B_D18 DDR_B_D28 DDR_B_D24

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D31 DDR_B_D27

DDR4_DRAMRST# DDR_CKE3_DIMMB

DDR_B_ALERT#

DDR_B_MA11 DDR_B_MA7

DDR_B_MA5 DDR_B_MA4

DDR_B_MA2

M_CLK_DDR3 M_CLK_DDR#3

DDR_B_MA0 DDR_B_MA10

DDR_B_BS0

DDR_B_RAS#

DDR_B_CAS#

DDR_B_MA13

DIMM_CHB_SA2 DDR_B_D36DDR_B_D37

DDR_B_D32DDR_B_D33

DDR_B_D39

DDR_B_D35

DDR_B_D45

DDR_B_D41

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D53

DDR_B_D48

DDR_B_D54

DDR_B_D50

DDR_B_D60

DDR_B_D57

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D63

PCH_SMBDATAPCH_SMBCLK DIMM_CHB_SA0

DIMM_CHB_SA1

+1.2V_DDR

DDR4_DRAMRST# [14] DDR_CKE3_DIMMB [8]

DDR_B_ACT# [8] DDR_B_ALERT# [ 8]

All VREF traces should

M_CLK_DDR3 [8] M_CLK_DDR#3 [8]

DDR_B_BS0 [8] DDR_B_RAS# [8]

DDR_B_CAS# [8]

+V_DDR_REFB

.1U_0402_16V7K

CD29

1

2

+0.6VS+2.5V_MEM

Title

DDRIII DIMMB

Size Document Number Rev

LA-C361P

Date: Sheet of

have 10 mil trace width

Compal Electronics, Inc.

1

0.1(X00)

15 71Thursday, August 06, 2015

0.1(X00)

DDR_B_D[0..63][8] DDR_B_MA[0..13][8] DDR_B_DQS#[0..7][8]

+2.5V_MEM

.1U_0402_16V7K

1

2

DDR_B_DQS[0..7][8]

CD34

1

CD35

2.2U_0402_6.3V6M

2

Layout Note: Place near JDIMM1.258

+0.6VS

D D

1U_0402_6.3V6K

CD32

1

2

Layout Note: Place near JDIMMB

10U_0603_6.3V6M

1

CD90

2

10U_0603_6.3V6M

1

CD89

2

Layout Note: Place near JDIMM2.257,259

+2.5V_MEM

CD88

10U_0603_6.3V6M

1U_0402_6.3V6K

CD30

1

2

10U_0603_6.3V6M

1U_0402_6.3V6K

CD31

1

2

1

CD27

2

CD28

Layout Note: Place near JDIMM2.255

DDR_B_D5 DDR_B_D1

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D7 DDR_B_D3 DDR_B_D13 DDR_B_D9

DDR_B_D15 DDR_B_D10 DDR_B_D21 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D23 DDR_B_D19 DDR_B_D29 DDR_B_D25

DDR_B_D30 DDR_B_D26

+1.2V_DDR

1U_0402_6.3V6K

C C

1U_0402_6.3V6K

CD19

1

2

CD21

CD20

1

2

1U_0402_6.3V6K

CD22

1

2

CD81

CD83

1

2

+1.2V_DDR

10U_0603_6.3V6M

1

CD24

CD23

2

B B

+3VS +3VS +3VS

12

@

DIMM_CHB_SA0 DIMM_CHB_SA1 DIMM_CHB_SA2

A A

12

+V_DDR_REFB_R

12

10U_0603_6.3V6M

1

CD26

CD25

2

RD4 0_0402_5%

RD38 0_0402_5%@

20mil

1 2

RH485 2_0402_1%

1

CH100

0.022U_0402_25V7K

2

RH212

24.9_0402_1%

5

1

2

10U_0603_6.3V6M

CD87

1

2

12

RD39

@

0_0402_5%

+1.2V_DDR

10U_0603_6.3V6M

X06.12

RD5 0_0402_5%@

12

CD85

1K_0402_1%

1U_0402_6.3V6K

1

2

10U_0603_6.3V6M

1

2

RH207

+V_DDR_REFB

RH210

1U_0402_6.3V6K

CD82

CD80

1

2

10U_0603_6.3V6M

1

+

CD84

2

CD33

CD86

220U_D7_2VM_R6M

2

12

RD6

@

0_0402_5%

12

X06.12X06.12

RD40 0_0402_5%@

4

DDR_CKE2_DIMMB[8]

DDR_B_BG1[8] DDR_B_BG0[8]

M_CLK_DDR2[8] M_CLK_DDR#2[8]

DDR_B_PAR[8] DDR_B_BS1[8]

DDR_CS2_DIMMB#[8]

DDR_B_WE#[8] M_ODT2[8]

DDR_CS3_DIMMB#[8]

M_ODT3[8]

+3VS

DDR_CKE2_DIMMB DDR_B_BG1

DDR_B_BG0

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA6

DDR_B_MA3 DDR_B_MA1

M_CLK_DDR2 M_CLK_DDR#2

DDR_B_PAR DDR_B_BS1

DDR_CS2_DIMMB# DDR_B_WE#

M_ODT2 DDR_CS3_DIMMB#

M_ODT3

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D38 DDR_B_D34 DDR_B_D44 DDR_B_D40

+1.2V_DDR

DDR_B_D46 DDR_B_D47 DDR_B_D42 DDR_B_D43 DDR_B_D52 DDR_B_D49 DDR_B_DQS#6

DDR_B_DQS6 DDR_B_D55 DDR_B_D51 DDR_B_D61 DDR_B_D56

+1.2V_DDR

DDR_B_D62

PCH_SMBCLK[6,14,18,45] PCH_SMBDATA [6,14,18,45]

3

DDR_B_D58 DDR_B_D59

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONIC S, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONIC S, INC.

5

4

3

2

1

CLINK

REV = 1.3

SKY-S-PCH_BGA837

FAN

HOST

3 OF 12REV = 1.3

SKY-S-PCH_BGA837

5 OF 12

PCIE9_RXN/SATA0A_RXN PCIE9_RXP/SATA0A_RXP PCIE9_TXN/SATA0A_TXN PCIE9_TXP/SATA0A_TXP

PCIE10_RXN/SATA1A_RXN

PCIE10_RXP/SATA1A_RXP PCIE10_TXN/SATA1A_TXN PCIE10_TXP/SATA1A_TXP

PCIE15_RXN/SATA2_RXN PCIE15_RXP/SATA2_RXP PCIE15_TXN/SATA2_TXN

PCIE15_TXP/SATA2_TXP

PCIe/SATA

PCIE16_RXN/SATA3_RXN PCIE16_RXP/SATA3_RXP PCIE16_TXN/SATA3_TXN

PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN PCIE17_RXP/SATA4_RXP PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN PCIE18_RXP/SATA5_RXP PCIE18_TXN/SATA5_TXN

PCIE18_TXP/SATA5_TXP

GPP_E8/SATALED#

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2 GPP_F0/SATAXPCIE3/SATAGP3 GPP_F1/SATAXPCIE4/SATAGP4 GPP_F2/SATAXPCIE5/SATAGP5 GPP_F3/SATAXPCIE6/SATAGP6 GPP_F4/SATAXPCIE7/SATAGP7

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

PLTRST_CPU#

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I9/DDPD_CTRLCLK

GPP_I10/DDPD_CTRLDATA

GPP_F14 GPP_F23 GPP_F22

GPP_G23 GPP_G22 GPP_G21 GPP_G20 GPP_H23

THERMTRIP#

PM_SYNC

PM_DOWN

BB3 BD6 BA5 BC4 BE5 BE6

Y44 V44 W39

L43 L44 U35 R35 BD36

G31 H31 C31 B31

G29 E29 C32 B32

F41 E41 B39 A39

D43 E42 A41 A40

H42 H40 E45 F45

K37 G37 G45 G44

AD44 AG36

AG35 AG39 AD35 AD31 AD38 AC43 AB44

W36 W35 W42

AJ3 AL3

PECI

AJ4 AK2 AH2

DDI2_DDPC_CTRLCLK DDI2_DDPC_CTRLDAT DDI1_DDPB_CTRLCLK DDI1_DDPB_CTRLDAT

PCH_SATA_LED#

T182 PAD~D @

HDD_DET#

T104 PAD~D @ T105 PAD~D @ T106 PAD~D @ T107 PAD~D @ T108 PAD~D @

H_THERMTRIP#

PCH_PECI

T2 PAD~D @

T4 PAD~D @

T8 PAD~D @

SATA_PRX_SSDTX_N0A [44] SATA_PRX_SSDTX_P0A [44]

SATA_PTX_SSDRX_N0A [44] SATA_PTX_SSDRX_P0A [44]

PCIE_PRX_SSDTX_N10 [44] PCIE_PRX_SSDTX_P10 [44]

PCIE_PTX_SSDRX_N10 [44] PCIE_PTX_SSDRX_P10 [44]

PCIE_PRX_TBTX_N15 [37] PCIE_PRX_TBTX_P15 [37] PCIE_PTX_TBRX_N15 [37] PCIE_PTX_TBRX_P15 [37]

PCIE_PRX_TBTX_N16 [37] PCIE_PRX_TBTX_P16 [37] PCIE_PTX_TBRX_N16 [37] PCIE_PTX_TBRX_P16 [37]

mCARD_PCIE#_SATA [44] HDD_DET# [45]

BIA_PWM_PCH [7,35] PANEL_BKEN_PCH [35] ENVDD_PCH [33,48]

1 2

RH191 620_0402_5%

1 2

RH539 13_0402_5% RH189

1 2

30_0402_5%

PLTRST_CPU# [6,9]

H_PM_DOWN [9]

DDI2_DDPC_CTRLCLK [37]

DDI2_DDPC_CTRLDAT [37]

DDI1_DDPB_CTRLCLK [37]

DDI1_DDPB_CTRLDAT [37]

PROC_DETECT# [9]

LCD_DBC

SSD

Thunderbolt

H_THERMTRIP#_R [9,48]

H_PECI [9,48]

H_PM_SYNC_R [9]

LCD_DBC

DDI2_DDPC_CTRLCLK DDI2_DDPC_CTRLDAT DDI1_DDPB_CTRLCLK DDI1_DDPB_CTRLDAT

mCARD_PCIE#_SATA

CAM_CBL_DET#

PCH_SATA_LED#

HDD_DET#

1 2

RH527 10K_0402_5%

1 2

RH528 10K_0402_5%

@

RP1

1 8 2 7 3 6 4 5

2.2K_8P4R_5%

1 2

RH508 10K_0402_5%

1 2

RH511 10K_0402_5%

1 2

RH512 10K_0402_5%

1 2

RH513 10K_0402_5%

+3VS

UH2C

T91PAD~D@ T92PAD~D@

T94PAD~D@

DDI1_PCH_HPD DDI2_PCH_HPD

AV2

CL_CLK

AV3

CL_DATA

AW2

CL_RST#

R44

GPP_G8/FAN_PWM_0

R43

GPP_G9/FAN_PWM_1

U39

GPP_G10/FAN_PWM_2

N42

GPP_G11/FAN_PWM_3

U43

GPP_G0/FAN_TACH_0

U42

GPP_G1/FAN_TACH_1

U41

GPP_G2/FAN_TACH_2

M44

GPP_G3/FAN_TACH_3

U36

GPP_G4/FAN_TACH_4

P44

GPP_G5/FAN_TACH_5

T45

GPP_G6/FAN_TACH_6

T44

GPP_G7/FAN_TACH_7

B33

PCIE11_TXP

C33

PCIE11_TXN

K31

PCIE11_RXP

L31

PCIE11_RXN

AB33

GPP_F10/SCLOCK

AB35

GPP_F11/SLOAD

AA44

GPP_F13/SDATAOUT0

AA45

GPP_F12/SDATAOUT1

B38

PCIE14_TXN/SATA1B_TXN

C38

PCIE14_TXP/SATA1B_TXP

D39

PCIE14_RXN/SATA1B_RXN

E37

PCIE14_RXP/SATA1B_RXP

C36

PCIE13_TXN/SATA0B_TXN

B36

PCIE13_TXP/SATA0B_TXP

G35

PCIE13_RXN/SATA0B_RXN

E35

PCIE13_RXP/SATA0B_RXP

A35

PCIE12_TXP

B35

PCIE12_TXN

H33

PCIE12_RXP

G33

PCIE12_RXN

J45

PCIE20_TXP

K44

PCIE20_TXN

N38

PCIE20_RXP

N39

PCIE20_RXN

H44

PCIE19_TXP

H43

PCIE19_TXN

L39

PCIE19_RXP

L37

PCIE19_RXN

SKY-H-PCH_BGA837

@

AW4

AY2 AV4 BA4

BD7

@

UH2E

GPP_I0/DDPB_HPD0 GPP_I1/DDPC_HPD1 GPP_I2/DDPD_HPD2 GPP_I3/DDPE_HPD3

GPP_I4/EDP_HPD

SKY-H-PCH_BGA837

CLINK_CLK[43] CLINK_DATA[43] CLINK_RST#[43]

D D

SSD

HDD

SSD

C C

B B

CAM_CBL_DET#[35] TBT_CIO_PLUG_EVENT#[37]

SSD_PWR_EN[33]

PCIE_PTX_SSDRX_P11[44] PCIE_PTX_SSDRX_N11[44]

PCIE_PRX_SSDTX_P11[44] PCIE_PRX_SSDTX_N11[44]

SATA_PTX_DRX_N1B[45] SATA_PTX_DRX_P1B[45]

SATA_PRX_DTX_N1B[45] SATA_PRX_DTX_P1B[45]

PCIE_PTX_SSDRX_P12[44] PCIE_PTX_SSDRX_N12[44]

PCIE_PRX_SSDTX_P12[44] PCIE_PRX_SSDTX_N12[44]

DDI1_PCH_HPD[37] DDI2_PCH_HPD[37]

EDP_HPD[35]

CAM_CBL_DET#

PCH Strap PIN

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2011/08/25 2012/07/25

SSD

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (1/8) SATA,HDA

PCH (1/8) SATA,HDA LA-C361P

LA-C361P

1

16 71Thursday, August 06, 2015

0.1(X00)

5

4

3

2

1

UH2G

AR17

GPP_A16/CLKOUT_48

XTAL24_OUT XTAL24_IN

PCH_RTCX1 PCH_RTCX2

T17PAD~D@

PCH_SPI_SI_R PCH_SPI_SO_R PCH_SPI_CS# PCH_SPI_CLK_R PCH_SPI_CS1#

PCH_SPI_WP#_R PCH_SPI_HOLD#_R

X06.27

1 2

@

G1

CLKOUT_CPUNSSC_P

F1

CLKOUT_CPUNSSC

G2

CLKOUT_CPUBCLK_P

H2

CLKOUT_CPUBCLK

A5

XTAL24_OUT

A6

XTAL24_IN

E1

XCLK_BIASREF

BC9

RTCX1

BD10

RTCX2

BC24

GPP_B5/SRCCLKREQ0#

AW24

GPP_B6/SRCCLKREQ1#

AT24

GPP_B7/SRCCLKREQ2#

BD25

GPP_B8/SRCCLKREQ3#

BB24

GPP_B9/SRCCLKREQ4#

BE25

GPP_B10/SRCCLKREQ5#

AT33

GPP_H0/SRCCLKREQ6#

AR31

GPP_H1/SRCCLKREQ7#

BD32

GPP_H2/SRCCLKREQ8#

BC32

GPP_H3/SRCCLKREQ9#

BB31

GPP_H4/SRCCLKREQ10#

BC33

GPP_H5/SRCCLKREQ11#

BA33

GPP_H6/SRCCLKREQ12#

AW33

GPP_H7/SRCCLKREQ13#

BB33

GPP_H8/SRCCLKREQ14#

BD33

GPP_H9/SRCCLKREQ15#

R13

CLKOUT_PCIE_N15

R11

CLKOUT_PCIE_P15

P1

CLKOUT_PCIE_N14

R2

CLKOUT_PCIE_P14

W7

CLKOUT_PCIE_N13

Y5

CLKOUT_PCIE_P13

U2

CLKOUT_PCIE_N12

U3

CLKOUT_PCIE_P12

SKY-H-PCH_BGA837

@

BD17

GPP_A11/PME#

AG15

RSVD_AG15

AG14

RSVD_AG14

AF17

RSVD_AF17

AE17

RSVD_AE17

AR19

TP5

AN17

TP4

BB29

SPI0_MOSI

BE30

SPI0_MISO

BD31

SPI0_CS0#

BC31

SPI0_CLK

AW31

SPI0_CS1#

BC29

SPI0_IO2

BD30

SPI0_IO3

AT31

SPI0_CS2#

AN36

GPP_D1/SPI1_CLK

AL39

GPP_D0/SPI1_CS#

AN41

GPP_D3/SPI1_MOSI

AN38

GPP_D2/SPI1_MISO

AH43

GPP_D22/SPI1_IO3

AG44

GPP_D21/SPI1_IO2

@

UH2A

SKY-H-PCH_BGA837

+3VS

RP2

4 5 3 6 2 7 1 8

D D

C C

9/5 MOW Option 1: Implement a 1 kOhm pull-down resistor on the signal and de-populate the

B B

required 1 kOhm pull-up resistor. In this case, customers must ensure that the SPI flash device on the platform has HOLD functionality disabled by default.

Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y platforms with ES and SKL S/H platforms with pre-ES1/ES1 samples.

PCH_TPM_SO[42]

PCH_TPM_SI[42] PCH_TPM_CLK[42]

10K_0804_8P4R_5%

+3VS

1 2

RH548 10K_0402_5%@

1 2

RH549 10K_0402_5%@

1 2

RH550 10K_0402_5%@

1 2

RH551 10K_0402_5%

+3VS

RP22

4 5 3 6 2 7 1 8

10K_0804_8P4R_5%

+3VS

RP23

4 5 3 6 2 7 1 8

10K_0804_8P4R_5%

+3V_ROM

RH74 3.3K_0402_5%@

RH75 1K_0402_5%

RH78 1K_0402_5%

RH455 1K_0402_5%@

PCH_SPI_CLK PCH_SPI_SI PCH_SPI_SO PCH_SPI_WP#

PCH_SPI_HOLD#

PCH_TPM_SO

PCH_TPM_SI

PCH_TPM_CLK

@

1 2 1 2 1 2

1 2

WLAN_CLK_REQ# CR_CLK_REQ# TBT_CLK_REQ# SSD_CLK_REQ#

SRCCLKREQ15# SRCCLKREQ9# SRCCLKREQ8# SRCCLKREQ10#

SRCCLKREQ12# SRCCLKREQ13# SRCCLKREQ14# SRCCLKREQ11#

RP4

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

RH576 0_0402_5%@ RH577 0_0402_5%@ RH578 0_0402_5%@ RH579 0_0402_5%@

CLKREQ_PCIE#0 SRCCLKREQ1# SRCCLKREQ2# VGA_CLK_REQ#

PCH_SPI_CLK_R PCH_SPI_SI_R PCH_SPI_SO_R PCH_SPI_WP#_R

1 2 1 2 1 2 1 2

PCH_SPI_CS# PCH_SPI_WP#_R PCH_SPI_HOLD#_R

PCH_SPI_HOLD#_R

PCH_SPI_SI_R [6] PCH_SPI_WP#_R [6]

PCH_SPI_HOLD#_R PCH_SPI_SO_R PCH_SPI_SI_R PCH_SPI_CLK_R

+1V_PCH

WLAN_CLK_REQ#[43] CR_CLK_REQ#[51] TBT_CLK_REQ#[37] SSD_CLK_REQ#[44] VGA_CLK_REQ#[23]

PCH_SPI_CS2#[42]

MEDIACARD_IRQ#[51]

TPM_PIRQ#[42]

X06.27

CPU_24MHZ_P[9] CPU_24MHZ_N[9]

PCH_CPU_BCLK_P[9] PCH_CPU_BCLK_N[9]

RH71 2.7K_0402_1%

1 2

CLKREQ_PCIE#0 SRCCLKREQ1# SRCCLKREQ2# WLAN_CLK_REQ# CR_CLK_REQ# TBT_CLK_REQ# SSD_CLK_REQ# VGA_CLK_REQ# SRCCLKREQ8# SRCCLKREQ9# SRCCLKREQ10# SRCCLKREQ11# SRCCLKREQ12# SRCCLKREQ13# SRCCLKREQ14# SRCCLKREQ15#

T18PAD~D @

FFS_INT2[45]

MEDIACARD_IRQ#

+3V_ROM +3V_PCH

RH585 0_0603_5%

SPI ROM FOR ME ( 16MByte )

SKY-S-PCH_BGA837

7 OF 12REV = 1.3

SKY-S-PCH_BGA837

1 OF 12 REV = 1.3

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

CLKOUT_PCIE_N6 CLKOUT_PCIE_P6

CLKOUT_PCIE_N7 CLKOUT_PCIE_P7

CLKOUT_PCIE_N8 CLKOUT_PCIE_P8

CLKOUT_PCIE_N9 CLKOUT_PCIE_P9

CLKOUT_PCIE_N10 CLKOUT_PCIE_P10

CLKOUT_PCIE_N11 CLKOUT_PCIE_P11

GPP_B13/PLTRST#

GPP_G16/GSXCLK

GPP_G12/GSXDOUT

GPP_G13/GSXSLOAD

GPP_G14/GSXDIN

GPP_G15/GSXSRESET#

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

GPP_H18/SML4ALERT#

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H15/SML3ALERT#

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H12/SML2ALERT#

GPP_H11/SML2DATA

GPP_H10/SML2CLK

INTRUDER#

TOUCHPAD_INTR#

L1 L2

J1 J2

N7 N8

L7 L5

D3 F2

E5 G4

D5 E6

D8 D7

R8 R7

U5 U7

W10 W11

N3 N2

P3 P2

R3 R4

BB27

PCH_PLTRST#

P43 R39 R36 R42 R41

AF41

SIO_EXT_SMI#

AE44

TOUCH_SCREEN_PD#

BC23

TOUCHPAD_INTR#

BD24

EC_SLP_S0IX#

BC36 BE34 BD39 BB36 BA35 BC35 BD35 AW35 BD34

BE11

INTRUDER#

DH1

RB751S40T1G_SOD523-2

PCH_XDP_CLK_N [6] PCH_XDP_CLK_P [6]

PCH_CPU_PCIBCLK_N [9] PCH_CPU_PCIBCLK_P [9]

CLK_PCIE_WLAN# [43] CLK_PCIE_WLAN [43]

CLK_PCIE_CR# [51] CLK_PCIE_CR [51]

CLK_PCIE_TBT# [37] CLK_PCIE_TBT [37]

CLK_PCIE_SSD# [44] CLK_PCIE_SSD [44]

CLK_PEG_VGA# [23] CLK_PEG_VGA [23]

TBT_FORCE_PWR [37] RTD3_CIO_PWR_EN [37]

SIO_EXT_SMI# [48]

TOUCH_SCREEN_PD# [35]

EC_SLP_S0IX# [48]

12

PTP_INT# [42,48]

PCH_PLTRST#_EC[23,37,42,43,44,48,51]

NGFF - WLAN

Card Reader

Thunderbolt

NGFF - SSD

GPU - N16P-GX

UH7

4

12

MC74VHC1G08DFT2G_SC70-5

RH77 100K_0402_5%

OUT

RH586 0_0402_5%@

X06.27

RH587 0_0402_5%@

5

VCC

IN1 IN2

GND

3

1 2

PCH_PLTRST#

RTC CRYSTAL

RH70 10M_0402_5%

32.768KHZ_X1A000141000300

Max Crystal ESR = 50k Ohm.

1

CH45

8.2P_0402_50V8D

2

RH72 1M_0402_5%

24MHZ_12PF_X3G024000DC1H

1

CH47 15P_0402_50V8J

2

TOUCH_SCREEN_PD# TOUCHPAD_INTR# EC_SLP_S0IX#

SIO_EXT_SMI# MEDIACARD_IRQ#

INTRUDER#

+3V_PCH

+3VS

1 2

YH1

1 2

1

CH46

8.2P_0402_50V8D

2

XTAL24_IN

1 2

YH2

123

RH510 10K_0402_5% RH547 10K_0402_5% RH535 10K_0402_5%@

RH110 10K_0402_5% RH546 10K_0402_5%

RH531 330K_0402_5%

4

1 2 1 2 1 2

1 2 1 2

1 2

XTAL24_OUT

1

2

PCH_RTCX1

PCH_RTCX2

CH48 18P_0402_50V8J

+3VS

+3V_PCH

+RTCVCC

A A

5

PCH_SPI_CS# PCH_SPI_SO PCH_SPI_WP#

UH8

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

W25Q128FVSIQ_SO8

/HOLD(IO3)

DI(IO0)

8

VCC

7

PCH_SPI_HOLD#

6

PCH_SPI_CLK

CLK

5

PCH_SPI_SI

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (2/8) SMBUS, CLK, SPI, LPC

PCH (2/8) SMBUS, CLK, SPI, LPC LA-C361P

LA-C361P

1

17 71Thursday, August 06, 2015

0.1(X00)

5

RP15

HDA_BITCLK_AUDIO[52] HDA_SYNC_AUDIO[52]

HDA_RST#_AUDIO[52]

D D

C C

B B

HDA_SDOUT_AUDIO[52]

+RTCVCC

1 2

RH83 20K_0402_5%

+RTCVCC

1 2

RH84 20K_0402_5%

+3V_PCH

1 2

RH458 1K_0402_5%

1 2

RH459 1K_0402_5%

1 2

RH460 1K_0402_5%

1 2

RH461 1K_0402_5%

1 2

RH501 499_0402_1%

1 2

RH502 499_0402_1%

+3VS

1 2

RH463 1K_0402_5%

1 2

RH462 1K_0402_5%

1 2

RH516 10K_0402_5%

1 2

RH91 100K_0402_5%

1 2

RH88 47K_0402_5%

1 2

RH401 100K_0402_5%

Service Mode Switch: Add a switch to ME_FWP signal to unlock the ME region and allow the entire region of the SPI flash to be updated using FPT.

HDA_SDOUT

ME_FWP_EC[48]

ME_FWP PCH has internal 20K PD.

A A

1 8 2 7 3 6 4 5

CH52

1U_0402_6.3V6K

CH53

1U_0402_6.3V6K

FLASH DESCRIPTOR SECURITY OVERRIDE

Disable ME Protect (ME can be updated) ----> Pin1 & Pin2 short Enable ME Protect (ME cannot be updated)-->Pin3 & Pin2 short(Default position)

33_8P4R_5%

PCH_SRTCRST#

12

PCH_RTCRST#

12

CLRP1

SHORT PADS

SMBCLK SMBDATA SML1_SMBCLK SML1_SMBDAT SML0_SMBCLK SML0_SMBDATA

PCH_RSMRST#_R

PCH_DPWROK_R

X06.34

HDA_BITCLK HDA_SYNC HDA_RST# HDA_SDOUT

PCH_SMBCLK PCH_SMBDATA DGPU_PWROK

RESET_OUT#

12

RH4541K_0402_5%

12

RH4870_0402_5% @

ME_EN

+3V_PCH

12

AUD_AZA_CPU_SDO[7]

AUD_AZA_CPU_SDI_R[7]

AUD_AZA_CPU_SCLK[7]

RH536 1K_0402_5%

SW4

1 2 3

4

G

5

G

SSAL120100_3P

@

HDA_SDIN0_AUDIO[52]

PCH_RSMRST#[6,48]

PCH_DPWROK[48]

DMN65D8LDW-7_SOT363-6

SMBCLK

SMBDATA

X06.20

4

1 2

RH96 0_0402_5%@

Close to PCH

1 2

RH146 30_0402_5%

1 2

RH147 30_0402_5%

DGPU_PWROK[63]

PCH_RTCRST#[52]

1 2

RH133 0_0402_5%@

1 2

RH309 0_0402_5%@

SML1_SMBCLK[48] SML1_SMBDAT[48]

QH4A

2

6 1

3 4

DMN65D8LDW-7_SOT363-6

X06.20

+3VS

5

QH4B

AUD_AZA_CPU_SDO_R AUD_AZA_CPU_SDI_R AUD_AZA_CPU_SCLK_R

BA9

HDA_BITCLK

BD8

HDA_RST#

BE7

HDA_SDIN0

BC8 BB7

HDA_SDOUT

BD9

HDA_SYNC

BD1 BE2

AM1

AN2

AM2

AL42

T120PAD~D@

AN42

T121PAD~D@

AM43

T122PAD~D@

AJ33

T123PAD~D@

AH44

T124PAD~D@

AJ35

DGPU_PWROK

PCH_RTCRST# PCH_SRTCRST#

PCH_PWROK PCH_RSMRST#_R

PCH_DPWROK_R SMBALERT# SMBCLK SMBDATA SML0ALERT# SML0_SMBCLK SML0_SMBDATA SML1ALERT# SML1_SMBCLK SML1_SMBDAT

AJ38 AJ42

T127PAD~D@

BC10 BB10

AW11

BA11

AV11 BB41

AW44

BB43 BA40 AY44 BB39

AT27 AW42 AW45

@

PCH to DDR, XDP, FFS

PCH_SMBCLK

PCH_SMBDATA

UH2D

HDA_BCLK HDA_RST# HDA_SDI0 HDA_SDI1

HDA_SDO HDA_SYNC

RSVD_BD1 RSVD_BE2

DISPA_SDO DISPA_SDI DISPA_BCLK

GPP_D8/SSP0_SCLK GPP_D7/SSP0_RXD GPP_D6/SSP0_TXD GPP_D5/SSP0_SFRM GPP_D20/DMIC_DATA0 GPP_D19/DMIC_CLK0 GPP_D18/DMIC_DATA1 GPP_D17/DMIC_CLK1

RTCRST# SRTCRST#

PCH_PWROK RSMRST#

DSW_PWROK GPP_C2/SMBALERT# GPP_C0/SMBCLK GPP_C1/SMBDATA GPP_C5/SML0ALERT# GPP_C3/SML0CLK GPP_C4/SML0DATA GPP_B23/SML1ALERT#/PCHHOT# GPP_C6/SML1CLK GPP_C7/SML1DATA

SKY-H-PCH_BGA837

AUDIO

PCH_SMBCLK [6,14,15,45]

PCH_SMBDATA [6,14,15,45]

3

SKY-S-PCH_BGA837

GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_A13/SUSWARN#/SUSPWRDNACK

SMBUS

JTAG

4 OF 12REV = 1.3

GPP_A8/CLKRUN# GPD11/LANPHYPC GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_B1

SYS_PWROK

GPD6/SLP_A#

SLP_LAN#

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE# GPD1/ACPRESENT

SLP_SUS#

GPD3/PWRBTN#

SYS_RESET#

GPP_B14/SPKR

PROCPWRGD

ITP_PMODE

JTAG_TMS JTAG_TDO

JTAG_TDI

JTAG_TCK

IMVP_VR_PG[64] RUNPWROK[48]

MC74VHC1G08DFT2G_SC70-5

GPP_B0

GPP_B11

WAKE#

JTAGX

GPP_G17/ADR_COMPLETE

BB17 AW22

AR15 AV13 BC14

BD23 AL27 AR27 N44 AN24 AY1

BC13 BC15 AV15 BC26 AW15 BD15 BA13

AN15 BD13 BB19 BD19

BD11 BB15 BB13 AT13 AW1 BD26 AM3

AT2 AR3 AR2 AP1 AP2 AN3

CLKRUN#

RESET_OUT# PCH_PCIE_WAKE#

PCH_BATLOW# ME_SUS_PWR_ACK

AC_PRESENT

SYS_RESET# SPKR

PCH_ITP_PMODE PCH_JTAGX PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI PCH_JTAG_TCK

+3VS

5

1

VCC

IN1

2

IN2

GND

3

2

UH14

4

OUT

CLKRUN# [48]

SIO_SLP_WLAN# [48]

H_DRAMRST# [14]

RESET_OUT# [6,48]

PCH_PCIE_WAKE# [48]

SIO_SLP_A# [48,52] SIO_SLP_S0# [34,42,52]

SIO_SLP_S3# [34,37,48,52] SIO_SLP_S4# [34,48,52] SIO_SLP_S5# [34,48,52]

ME_SUS_PWR_ACK [48]

SIO_SLP_SUS# [48]

H_CPUPWRGD [9]

T20 PAD~D @

SUSCLK [43,44]

SUSACK# [48]

LAN_WAKE# [48] AC_PRESENT [48]

SIO_PWRBTN# [6,48]

SYS_RESET# [6,52]

SPKR [52]

PCH_ITP_PMODE [6] PCH_JTAGX [6] PCH_JTAG_TMS [6] PCH_JTAG_TDO [6] PCH_JTAG_TDI [6] PCH_JTAG_TCK [6]

PCH_PWROK

12

RH529 100K_0402_5%

1

PCH_PCIE_WAKE# PCH_BATLOW# AC_PRESENT LAN_WAKE#

ME_SUS_PWR_ACK SYS_RESET#

CLKRUN#

+3V_PCH

1 2

RH453 1K_0402_5%

1 2

RH515 8.2K_0402_5%

1 2

RH533 8.2K_0402_5%

1 2

RH545 10K_0402_5%

1 2

RH506 1M_0402_5%@

1 2

RH571 8.2K_0402_5%@

1 2

RH85 8.2K_0402_5%

1 2

RH82 4.7K_0402_5%@

Top Swap Override (internal PD)

HIGH LOW(DEFAULT)

1 2

RH505 4.7K_0402_5%TPM@

TLS CONFIDENTIALITY

HIGH LOW(DEFAULT)

1 2

RH503 4.7K_0402_5%@

EC interface

HIGH LOW(DEFAULT)

RH504 150K_0402_5%

PCHHOT#

HIGH LOW(DEFAULT)

1 2

ENABLE DISABLE

vPRO non-vPRO

ESPI LPC

Enable Disable

Reserve for EMI

1 2

CH50 10P_0402_25V8J

EMC@

1 2

CH51 10P_0402_25V8J@

Reserve for RF please close to UH1

+3V_PCH_DSW

+3V_PCH

+3VS

SPKRLAN_WAKE#

SMBALERT#

SML0ALERT#

SML1ALERT#

HDA_BITCLK

HDA_SDOUT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

PCH (3/8) DMI,FDI,PM,GFX,DP LA-C361P

LA-C361P

1

18 71Thursday, August 06, 2015

0.1(X00)

5

4

3

2

1

UH2B

DMI_CTX_PRX_N0[7] DMI_CTX_PRX_P0[7]

D D

NGFF

CARD_READER

C C

DMI_CRX_PTX_N0[7] DMI_CRX_PTX_P0[7]

DMI_CTX_PRX_N1[7]

DMI_CTX_PRX_P1[7] DMI_CRX_PTX_N1[7] DMI_CRX_PTX_P1[7]

DMI_CTX_PRX_N2[7]

DMI_CTX_PRX_P2[7] DMI_CRX_PTX_N2[7] DMI_CRX_PTX_P2[7]

DMI_CTX_PRX_N3[7]

DMI_CTX_PRX_P3[7] DMI_CRX_PTX_N3[7] DMI_CRX_PTX_P3[7]

PCIE_PRX_WLANTX_N1[43]

PCIE_PRX_WLANTX_P1[43] PCIE_PTX_WLANRX_N1[43] PCIE_PTX_WLANRX_P1[43] PCIE_PTX_CARDRX_N2[51] PCIE_PTX_CARDRX_P2[51]

PCIE_PRX_CARDTX_N2[51]

PCIE_PRX_CARDTX_P2[51]

1 2

RH108 100_0402_1%

L27

DMI_RXN0

N27

DMI_RXP0

C27

DMI_TXN0

B27

DMI_TXP0

E24

DMI_RXN1

G24

DMI_RXP1

B28

DMI_TXN1

A28

DMI_TXP1

G27

DMI_RXN2

E26

DMI_RXP2

B29

DMI_TXN2

C29

DMI_TXP2

L29

DMI_RXN3

K29

DMI_RXP3

B30

DMI_TXN3

A30

DMI_TXP3

B18

PCIE_RCOMPN

C17

PCIE_RCOMPP

H15

PCIE1_RXN/USB3_7_RXN

G15

PCIE1_RXP/USB3_7_RXP

A16

PCIE1_TXN/USB3_7_TXN

B16

PCIE1_TXP/USB3_7_TXP

B19

PCIE2_TXN/USB3_8_TXN

C19

PCIE2_TXP/USB3_8_TXP

E17

PCIE2_RXN/USB3_8_RXN

G17

PCIE2_RXP/USB3_8_RXP

L17

PCIE3_RXN/USB3_9_RXN

K17

PCIE3_RXP/USB3_9_RXP

B20

PCIE3_TXN/USB3_9_TXN

C20

PCIE3_TXP/USB3_9_TXP

E20

PCIE4_RXN/USB3_10_RXN

G19

PCIE4_RXP/USB3_10_RXP

B21

PCIE4_TXN/USB3_10_TXN

A21

PCIE4_TXP/USB3_10_TXP

K19

PCIE5_RXN

L19

PCIE5_RXP

D22

PCIE5_TXN

C22

PCIE5_TXP

G22

PCIE6_RXN

E22

PCIE6_RXP

B22

PCIE6_TXN

A23

PCIE6_TXP

L22

PCIE7_RXN

K22

PCIE7_RXP

C23

PCIE7_TXN

B23

PCIE7_TXP

K24

PCIE8_RXN

L24

PCIE8_RXP

C24

PCIE8_TXN

B24

PCIE8_TXP

SKY-H-PCH_BGA837

@

SKY-S-PCH_BGA837

DMI

PCIe/USB 3

2 OF 12REV = 1.3

USB 2.0

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_F15/USB2_OCB_4 GPP_F16/USB2_OCB_5 GPP_F17/USB2_OCB_6 GPP_F18/USB2_OCB_7

USB2_COMP

USB2_VBUSSENSE

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

USB2N_5

USB2P_5

USB2N_6

USB2P_6

USB2N_7

USB2P_7

USB2N_8

USB2P_8

USB2N_9

USB2P_9 USB2N_10 USB2P_10 USB2N_11 USB2P_11 USB2N_12 USB2P_12 USB2N_13 USB2P_13 USB2N_14 USB2P_14

RSVD_AB13

USB2_ID

GPD7/RSVD

AF5 AG7 AD5 AD7 AG8 AG10 AE1 AE2 AC2 AC3 AF2 AF3 AB3 AB2 AL8 AL7 AA1 AA2 AJ8 AJ7 W2 W3 AD3 AD2 V2 V1 AJ11 AJ13

AD43 AD42 AD39 AC44 Y43 Y41 W44 W43

AG3 AD10 AB13 AG2

BD14

USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7#

1 2

RH109 113_0402_1%

1 2

RH580 0_0402_5%@

1 2

RH581 0_0402_5%@

USB20_N1 [46] USB20_P1 [46] USB20_N2 [46] USB20_P2 [46]

USB20_N4 [43] USB20_P4 [43]

USB20_N9 [35] USB20_P9 [35]

USB20_N12 [35] USB20_P12 [35]

USB_OC0# [46] USB_OC1# [46]

X06.27

3.3V_CAM_EN# [35]

USB Conn 1 (Right side) USB Conn 2 (Left side)

Mini Card(WLAN)

Touch Screen

Camera

USB_OC3#

RH555 10K_0402_5%

USB_OC2#

RH554 10K_0402_5%

USB_OC1#

RH553 10K_0402_5%

USB_OC0#

RH552 10K_0402_5%

USB_OC5# USB_OC4# USB_OC6# USB_OC7#

1 2 1 2 1 2 1 2

RP8

4 5 3 6 2 7 1 8

10K_0804_8P4R_5%

+3V_PCH

UH2F

4

C11

USB3_1_TXN

B11

USB3_1_TXP

B7

USB3_1_RXN

A7

USB3_1_RXP

B12

USB3_2_TXN/SSIC_1_TXN

A12

USB3_2_TXP/SSIC_1_TXP

C8

USB3_2_RXN/SSIC_1_RXN

B8

USB3_2_RXP/SSIC_1_RXP

B15

USB3_6_TXN

C15

USB3_6_TXP

K15

USB3_6_RXN

K13

USB3_6_RXP

B14

USB3_5_TXN

C14

USB3_5_TXP

G13

USB3_5_RXN

H13

USB3_5_RXP

D13

USB3_3_TXP/SSIC_2_TXP

C13

USB3_3_TXN/SSIC_2_TXN

A9

USB3_3_RXP/SSIC_2_RXP

B10

USB3_3_RXN/SSIC_2_RXN

B13

USB3_4_TXP

A14

USB3_4_TXN

G11

USB3_4_RXP

E11

USB3_4_RXN

SKY-H-PCH_BGA837

@

USB3TN1[47]

B B

USB Conn 1 (Right Side)

USB Conn 2 (Left Side)

A A

5

USB3TP1[47] USB3RN1[47] USB3RP1[47]

USB3TN2[47] USB3TP2[47] USB3RN2[47] USB3RP2[47]

SKY-S-PCH_BGA837

LPC/eSPI

USB

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_E6/DEVSLP2 GPP_E5/DEVSLP1 GPP_E4/DEVSLP0

6 OF 12REV = 1.3

GPP_F9/DEVSLP7 GPP_F8/DEVSLP6 GPP_F7/DEVSLP5 GPP_F6/DEVSLP4 GPP_F5/DEVSLP3

SATA

GPP_A6/SERIRQ

GPP_G19/SMI# GPP_G18/NMI#

AT22 AV22 AT19 BD16

BE16 BA17 AW17 AT17 BC18

BC17 AV19

M45 N43

AE45 AG43 AG42 AB39 AB36 AB43 AB42 AB41

IRQ_SERIRQ

SIO_RCIN#

LPC_AD0 [48] LPC_AD1 [48] LPC_AD2 [48] LPC_AD3 [48]

LPC_FRAME# [48] IRQ_SERIRQ [48] FFS_INT1 [45] SIO_RCIN# [48]

1 2

RH168 22_0402_5%

1 2

RH428 22_0402_5%

mSATA_DEVSLP [44]

CLK_PCI_MEC [48] PCI_CLK_LPC1 [48]

PCI_CLK_LPC1 CLK_PCI_MEC

CH198

@

15P_0402_50V8J

1

2

1

CH199 15P_0402_50V8J

2

@

RF Reserved.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

IRQ_SERIRQ SIO_RCIN#

1 2

RH111 10K_0402_5%

1 2

RH518 10K_0402_5%

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (4/8) PCI, USB

PCH (4/8) PCI, USB LA-C361P

LA-C361P

+3VS

19 71Thursday, August 06, 2015

1

19 71Thursday, August 06, 2015

0.1(X00)

5

4

3

2

1

UH2K

BBS_BIT0 SIO_EXT_SCI#

NGFF_PWREN NRB_BIT

3.3V_mSATA_EN

BID_DIS HOST_SD_WP#

BID_BC

TBT_PWR_EN

SIO_EXT_WAKE# UART2_TXD UART2_RXD

I2C1_SCK_TP I2C1_SDA_TP I2C0_SCK I2C0_SDA

1 2

RH521 0_0402_5%@

1 2

RH522 0_0402_5%@

3.3V_TS_EN[33] SIO_EXT_SCI#[48] NGFF_PWREN[33]

GC6_FB_EN[23] GPU_EVENT#[23]

UARTT0_TX[48] BID_DIS[48] HOST_SD_WP#[51]

SIO_EXT_WAKE#[48]

UART2_TXD[52] UART2_RXD[52]

EDP_PANEL_DAT_PCH[35]

EDP_PANEL_CLK_PCH[35]

+3VS

1 2

D D

C C

RH424 5.1K_0402_1%@

1 2

RH425 5.1K_0402_1%@

1 2

RH383 10K_0402_5%

1 2

RH561 49.9K_0402_1%

1 2

RH562 49.9K_0402_1%

1 2

RH563 10K_0402_5%

1 2

RH520 100K_0402_5%

+3V_PCH

1 2

RH119 4.7K_0402_5%

1 2

RH120 4.7K_0402_5%

1 2

RH523 10K_0402_5%

1 2

RH556 10K_0402_5%

UMA@

DIS@

1 2

RH423 100K_0402_5%@

3.3V_mSATA_EN

+3V_PCH +3V_PCH

12

RH564 100K_0402_5%

BID_DIS BID_BC

12

RH565 100K_0402_5%

I2C0_SCK I2C0_SDA SIO_EXT_SCI# UART2_TXD UART2_RXD

HOST_SD_WP#

NGFF_PWREN

I2C1_SCK_TP I2C1_SDA_TP

SIO_EXT_WAKE#

TBT_PWR_EN

12

RH566 100K_0402_5%

12

RH567 100K_0402_5%

BC@

CSMB@

I2C1_SCK_TP[42]

I2C1_SDA_TP[42]

I2C0_SCK_DSP[48,52]

I2C0_SDA_DSP[48,52]

AT29

GPP_B22/GSPI1_MOSI

AR29

GPP_B21/GSPI1_MISO

AV29

GPP_B20/GSPI1_CLK

BC27

GPP_B19/GSPI1_CS#

BD28

GPP_B18/GSPI0_MOSI

BD27

GPP_B17/GSPI0_MISO

AW27

GPP_B16/GSPI0_CLK

AR24

GPP_B15/GSPI0_CS#

AV44

GPP_C9/UART0_TXD

BA41

GPP_C8/UART0_RXD

AU44

GPP_C11/UART0_CTS#

AV43

GPP_C10/UART0_RTS#

AU41

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AT44

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AT43

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU43

GPP_C12/UART1_RXD/ISH_UART1_RXD

AN43

GPP_C23/UART2_CTS#

AN44

GPP_C22/UART2_RTS#

AR39

GPP_C21/UART2_TXD

AR45

GPP_C20/UART2_RXD

AR41

GPP_C19/I2C1_SCL

AR44

GPP_C18/I2C1_SDA

AR38

GPP_C17/I2C0_SCL

AT42

GPP_C16/I2C0_SDA

AM44

GPP_D4/ISH_I2C2_SDA

AJ44

GPP_D23/ISH_I2C2_SCL

SKY-H-PCH_BGA837

@

SKY-S-PCH_BGA837

11 OF 12REV = 1.3

GPP_D9 GPP_D10 GPP_D11

GPP_D16/ISH_UART0_CTS# GPP_D15/ISH_UART0_RTS#

GPP_D12

GPP_D14/ISH_UART0_TXD GPP_D13/ISH_UART0_RXD

GPP_H20/ISH_I2C0_SCL GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5 GPP_A22/ISH_GP4 GPP_A21/ISH_GP3 GPP_A20/ISH_GP2 GPP_A19/ISH_GP1 GPP_A18/ISH_GP0 GPP_A17/ISH_GP7

AL44 AL36 AL35 AJ39

AJ43 AL43 AK44 AK45

BC38 BB38

BD38 BE39

BC22 BD18 BE21 BD22 BD21 BB22 BC19

DGPU_PWR_EN

AUD_PWR_EN KB_DET# SPK_DET# CLKDET# USB_PWR_EN

DGPU_HOLD_RST# [23] DGPU_PWR_EN [32]

AUD_PWR_EN [52,54]

KB_DET# [52] SPK_DET# [48,52]

USB_PWR_EN [46]

SPK_DET# AUD_PWR_EN DGPU_PWR_EN

AUD_PWR_EN USB_PWR_EN

KB_DET# CLKDET#

+3V_PCH

RH572 100K_0402_5% RH569 100K_0402_5% RH537 10K_0402_5%@ RH538 10K_0402_5% RH568 100K_0402_5%@ RH544 10K_0402_5%

RH557 10K_0402_5% RH558 10K_0402_5%@

1 2

RH130 4.7K_0402_5%@

Boot BIOS Strap Bit (internal PD)

HIGH LOW(DEFAULT)

1 2

RH524 4.7K_0402_5%@

NO REBOOT mode (internal PD)

HIGH LOW(DEFAULT)

1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2

LPC SPI

ENABLE DISABLE

+3VS

+3V_PCH

BBS_BIT0

NRB_BIT

SYSTEM ID 1 (UMA/DIS)

HIGH = UMA LOW = DIS

B B

A A

5

SYSTEM ID 2 (BC/CSMB)

HIGH = BC LOW = CSMB

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (5/8) GPIO, CPU, MISC

PCH (5/8) GPIO, CPU, MISC LA-C361P

LA-C361P

1

20 71Thursday, August 06, 2015

0.1(X00)

5

@

PJP1302

1 2

PAD-OPEN 43x39

1 2

RZ70 0_0805_5%

@

1 2

@

D D

C C

RH137 0_0603_5%

RH196 0_0402_5%

+1V_MPHY

RH582 0_0603_5%

+1VALW

RH583 0_0603_5%

+1VALW

LH2 BLM15PX221SN1D_2P

1 2

@

X06.27

1 2

@

1 2

@

1 2

LH1 BLM15PX221SN1D_2P

X06.27

1 2

@

RH584 0_0603_5%

+1V_PCH_CLK5

+1V_MPHY_MPHYPLL +1V_PCH_USBPLL

X06.27

+1V_PCH+1VALW

+1V_MPHY

+3V_PCH_DSW+3VALW

+1V_VCCDSW+1V_PCH

+1V_MPHY_MPHYPLL

+1V_PCH_USBPLL

+1V_PCH_AZPLL

X06.05

+3V_PCH_AZIO+3V_PCH

X06.06

+1V_PCH_CLK5+1V_PCH

+3V_PCH_DSW

+1V_MPHY

Close to K2,K3 Close to A43,B43 Close to U21,U23

1U_0402_6.3V6K

22U_0603_6.3V6M

1

CH178

CH177

@

2

B B

22U_0603_6.3V6M

CH179

1

@

2

1U_0402_6.3V6K

22U_0603_6.3V6M

CH180

1

CH181

CH182

@

2

1U_0402_6.3V6K

22U_0603_6.3V6M

CH183

1

CH184

2

4

X06.06

+3V_PCH_AZIO

X06.06

Close to AJ5,AL5

22U_0603_6.3V6M

1

CH201

@

2

X06.05

+1V_PCH_AZPLL

+1VALW

X06.06

+1V_PCH_USBPLL

1 2

PAD-OPEN 43x39

+1V_MPHY

+1V_PCH

@

PJP1303

+1V_PCH_PRIM

+1V_PCH

+1V_PCH_CLK5

+1V_MPHY_MPHYPLL

+1V_VCCDSW

+1V_MPHY

3

UH2H

AA23

VCCPRIM_1P0_AA23

AA26

VCCPRIM_1P0_AA26

AA28

VCCPRIM_1P0_AA28

AC23

VCCPRIM_1P0_AC23

AC26

VCCPRIM_1P0_AC26

AC28

VCCPRIM_1P0_AC28

AE23

VCCPRIM_1P0_AE23

AE26

VCCPRIM_1P0_AE26

Y23

VCCPRIM_1P0_Y23

Y25

VCCPRIM_1P0_Y25

BA29

DCPDSW_1P0

N17

VCCCLK1

R19

VCCCLK3

U20

VCCCLK4

V17

VCCCLK2

R17

VCCCLK6

K2

VCCCLK5_K2

K3

VCCCLK5_K3

U21

VCCMPHY_1P0_U21

U23

VCCMPHY_1P0_U23

U25

VCCMPHY_1P0_U25

U26

VCCMPHY_1P0_U26

V26

VCCMPHY_1P0_V26

A43

VCCMPHYPLL_1P0_A43

B43

VCCMPHYPLL_1P0_B43

C44

VCCPCIE3PLL_1P0_C44

C45

VCCPCIE3PLL_1P0_C45

V28

VCCAPLLEBB_1P0

AC17

VCCPRIM_1P0_AC17

AJ5

VCCUSB2PLL_1P0_AJ5

AL5

VCCUSB2PLL_1P0_AL5

AN19

VCCHDAPLL_1P0

BA15

VCCHDA

W15

VCCDSW_3P3_W15

SKY-H-PCH_BGA837

@

SKY-S-PCH_BGA837

CORE

MPHY

USB

REV = 1.3

VCCGPIO

8 OF 12

VCCPRIM_1P0_AL22 VCCDSW_3P3_BA24

VCCPGPPBH_BC42 VCCPGPPBH_BD40

VCCPGPPEF_AJ41 VCCPGPPEF_AL41

VCCPRIM_3P3_AN5

VCCPRIM_1P0_AD15

VCCRTCPRIM_3P3

VCCPRIM_1P0_AJ20 VCCPRIM_1P0_AJ21 VCCPRIM_1P0_AJ23 VCCPRIM_1P0_AJ25

VCCPGPPCD_BC44

VCCPGPPCD_BA45

VCCPGPPCD_BC45

VCCPGPPCD_BB45 VCCPRIM_3P3_BD3

VCCPRIM_3P3_BE3 VCCPRIM_3P3_BE4

VCCPGPPA

VCCPGPPG

VCCATS

VCCRTC DCPRTC

VCCSPI_BE41 VCCSPI_BE43 VCCSPI_BE42

2

AL22 BA24

BA31 BC42

BD40 AJ41 AL41 AD41 AN5

AD15 AD13 BA20 BA22 BA26

AJ20 AJ21 AJ23 AJ25

BE41 BE43 BE42

BC44 BA45 BC45 BB45

BD3 BE3 BE4

+1V_PCH

+RTCVCC +DCPRTC

+1V_PCH_PRIM

+3V_PCH_SPI

+3V_PCH_DSW

+3VS

X06.27

@

+3V_PCH

12

RH1360_0603_5%

1

+3V_PCH

X06.06

+1V_PCH_AZPLL

Close to AN19

0.1U_0402_10V7K CH203

1

2

+1V_VCCDSW

Close to BA29

1U_0402_6.3V6K

CH176

1

2

+3V_PCH_AZIO

0.1U_0402_10V7K

Close to BA15

1

2

+DCPRTC

0.1U_0402_10V7K

CH200

Close to BA26

CH70

1

2

+3VS

Close to AD13

1U_0402_6.3V6K

CH188

1

2

X06.05

22U_0603_6.3V6M

1

CH202

2

0.1U_0402_10V7K

1

@

2

+3V_PCH_DSW

Close to W15

1U_0402_6.3V6K

CH190

1

@

2

CH82

+3V_PCH+3V_PCH +3V_PCH+3V_PCH

Close to AN5Close to AD41 Close to AJ41,AL41Close to BC42,BD40

0.1U_0402_10V7K

1

CH189

@

2

0.1U_0402_10V7K

1

CH192

@

2

0.1U_0402_10V7K

1

CH191

@

2

+RTCVCC

+3V_PCH

Close to BA22 Close to BA20

1U_0402_6.3V6K

0.1U_0402_10V7K

CH80

1

CH173

2

A A

5

1U_0402_6.3V6K

0.1U_0402_10V7K

CH187

1

CH186

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (6/8) PWR

PCH (6/8) PWR LA-C361P

LA-C361P

1

21 71Thursday, August 06, 2015

0.1(X00)

5

UH2I

SKY-S-PCH_BGA837

AC18

VSS

AN4

VSS

AN10

VSS

BE14

VSS

BE18

VSS

BE23

D D

C C

B B

BE28 BE32 BE37 BE40

AA17 AA18 AA20 AA21 AA25 AA29

AA42 AB10

BE9 C10

C28 C37

K10 K27 K33 K36

K42 K43

M35 M42 N10 N15 N19 N22 N24 N35 N36

N41 P17

P19 P22 P45 R10 R14 R22 R29 R33 R38

A18 A25 A32 A37

AA4

C2

J7

K4

L12 L13 L15

L4

L41

L8

N4 N5

R5 T1 T2

T4 Y18 Y20 Y21 Y26 Y28 Y29

@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKY-H-PCH_BGA837

AR5

VSS

AR7

VSS

U15

VSS

AL4

VSS

AE29

VSS

AE4

VSS

AE42

VSS

AF18

VSS

AF20

VSS

AF21

VSS

AF23

VSS

AF25

VSS

AF26

VSS

AF28

VSS

AF29

VSS

AG11

VSS

AG13

VSS

AG31

VSS

AG32

VSS

AG33

VSS

AG38

VSS

AG4

VSS

AH1

VSS

AH17

VSS

AH18

VSS

AH20

VSS

AH21

VSS

AH23

VSS

AH25

VSS

AH26

VSS

AH28

VSS

AH29

VSS

AH45

VSS

AJ10

VSS

AJ14

VSS

AJ15

VSS

AJ17

VSS

AJ18

VSS

AJ26

VSS

AJ28

VSS

AJ29

VSS

AJ31

VSS

AJ32

VSS

AJ36

VSS

AK4

VSS

AK42

VSS

AU7

VSS

AV17

VSS

AV24

VSS

AV27

VSS

AV31

VSS

AV33

VSS

AV6

VSS

AW13

VSS

AW19

VSS

AW29

VSS

AW37

VSS

AW9

VSS

AY38

VSS

AY45

VSS

B25

VSS

B3

VSS

B37

VSS

B40

VSS

B6

VSS

BA1

VSS

BB11

VSS

BB16

VSS

BB21

VSS

BB25

VSS

BB30

VSS

BB34

VSS

BC2

VSS

BD43

VSS

9 OF 12REV = 1.3

W14 W31 W32 W33 W38

4

C42

VSS

D10

VSS

D12

VSS

D15

VSS

D16

VSS

D17

VSS

D19

VSS

D21

VSS

D24

VSS

D25

VSS

D27

VSS

D29

VSS

D30

VSS

D31

VSS

D33

VSS

D35

VSS

D36

VSS

E13

VSS

E15

VSS

E31

VSS

E33

VSS

F44

VSS

F8

VSS

G42

VSS

G9

VSS

H17

VSS

H19

VSS

H22

VSS

H24

VSS

H27

VSS

H29

VSS

H3

VSS

H35

VSS

J10

VSS

J11

VSS

J3

VSS

J39

VSS

J5

VSS

T42

VSS

U10

VSS

U11

VSS

U14

VSS

U17

VSS

U18

VSS

U28

VSS

U29

VSS

U31

VSS

U32

VSS

U33

VSS

U38

VSS

U4

VSS

U8

VSS

V18

VSS

V20

VSS

V21

VSS

V23

VSS

V25

VSS

V29

VSS

V3

VSS

V45

VSS VSS VSS VSS VSS VSS

W4

VSS

W8

VSS

Y17

VSS

@

SKY-S-PCH_BGA837

UH2L

SKY-H-PCH_BGA837

12 OF 12 REV = 1.3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AB11 AB7 AB14 AB31 AB32 AB38 AB4 AB5 AC1 AC20 AC21 AC25 AC29 AC45 AB8 AD11 AD14 AB15 AD32 AD33 AD36 AD4 AD8 AE18 AE20 AE21 AE25 AE28 AL10 AL11 AL13 AL17 AL19 AL24 AL29 AL32 AL33 AL38 AM15 AM17 AM19 AM22 AM24 AM27 AM29 AM45 AN11 AN22 AN27 AN31 AN39 AN7 AN8 AP11 AP4 AR33 AR34 AR42 AR9 AT10 AT15 AT36 AT9 AU1 AU35 AU36 AU39 AU45 C4

3

SKY-S-PCH_BGA837

BD2 BD45 BD44 BE44

BB1

BC1

D45 A42 B45 B44

A4 A3 B2 A2 B1

A44

C1 D1

@

UH2J

VSS_BD2 VSS_BD45 VSS_BD44 VSS_BE44 VSS_D45 VSS_A42 VSS_B45 VSS_B44 VSS_A4 VSS_A3 VSS_B2 VSS_A2 VSS_B1 VSS_BB1 VSS_BC1 VSS_A44

RSVD_C1 RSVD_D1

SKY-H-PCH_BGA837

RSVD_AR22

RSVD_W13

RSVD_U13 RSVD_P31

RSVD_N31 RSVD_P27

RSVD_R27 RSVD_N29 RSVD_P29

RSVD_AN29

RSVD_R24 RSVD_P24

PREQ#

PRDY#

CPU_TRST#

PCH_TRIGOUT

PCH_TRIGIN

10 OF 12REV = 1.3

2

AR22 W13 U13

P31 N31

P27 R27 N29 P29 AN29 R24 P24

AT3 AT4 AY5 AL2 AK1

XDP_PREQ# [6,9] XDP_PRDY# [6,9] CPU_XDP_TRST# [6,9] PCH_TRIGGER [9] CPU_TRIGGER [9]

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (8/8) VSS

PCH (8/8) VSS LA-C361P

LA-C361P

1

0.1(X00)

22 71Thursday, August 06, 2015

0.1(X00)

Compal LA-C361P Schematics Rev0.1

Specifications and Main Features

Frequently Asked Questions

User Manual