Compal LA-B972P Schematic

A

1 1

B

C D

E

Compal Confidential

2 2

Hasswell M/B Schematics Document

Intel ULV Processor with DDRIIIL

Date : 2014/02/08

3 3

VER 1.0

4 4

Security Classification

Issued Date

TH IS SH E ET OF ENG I NEE RI N G DR A W IN G IS TH E P ROP R IE T AR Y P ROP ERT Y O F COM PAL E L EC T RON I CS , IN C. A N D C ON TAI NS CONFIDENTISSAiL
AN D T RAD E S ECR ET IN FO RMATI ON . THIS S HEE T MAY N O T BE T R AN S FER ED FR O M TH E CU S TOD Y OF T H E COM PET E NT DIVI SION OF R&D
DE P ART MEN T EX CEP T AS A U THO R IZE D BY C O MP A L EL E CT R ONI CS, IN C. N EIT HE R THI S SH E ET N O R T HE I N FO R MAT ION IT CO NT AIN S

A

B

MA Y BE US ED BY OR D IS CLOSE D TO AN Y TH IRD P ART Y W IT H OUT PRI O R WRI TTE N CON SEN T OF C O MP A L EL E CT R ONI CS, IN C.

2011/06/29 2011/06/29

C D

Compal Secret Data

Deciphered Date

Title

ze Document Number

B

Compal Electronics,Inc.

Cover Page

LA-B972P

Sheet

E

Rev

of

1 54Date: Thursday, March 20, 2014

0.1

A

CompalConfidential

Model Name : Haswell

B

C D

E

PCI-Ex4
Lane7-Lane10
PCIe2.0:5Gb/s
PCIe3.0:8Gb/s

P18

P29

eDPx2

2.7Gb/s

DDI

Haswell

Ultra Light & Thin

DualChannel

DDR3L 1600MHz1.35V

SATA3.0

GEN11.5Gb/s
GEN23Gb/s
GEN36Gb/s

Port 0

Port 1

DDR3-SO-DIMM X2

2.5" SATAHDD

ODD

P15,16

P22

P22

File Name :

1 LA-B972PR10

VRAM*4

SingleRank

P37~P40

LVDS panel

CRT Conn

P20

P29

Nvidia
N15V-GM
17W

P32~P36

RTD2132R

IT6513

1168P BGA

HDMI Conn

DDPB port P19 222.75MHz

2 2

PCI-E Card reader
RTS5239

10/100 1GLAN
8151/8166Option

WLAN(MiniPCIe slot)

Port 3

3 3

P23

Lane4

P25

Lane5

P24

Lane 11 PCIe1.0:2.5Gb/s

Port 3 (Reserved) USB2.0

HDMI

(USW ULT)

PCI-E

PCIe 1.0:2.5Gb/s

PCIe 2.0:5Gb/s

PCIe2.0:5Gb/s

PCI-E

480Mb/s

SMBUS

1MHz

USB3.0
5Gb/s
USB2.0
480Mb/s

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

USB3.0port

USB2.0port

USB2.0Port

WLAN

Camera

TouchScreen

Port 0

P26

P26

P27

P20

P19

P19

1

Int.KBD

TouchPad

PS2

FAN
Lidswitch

4 4

ENEKB9012

TPM 1.2@

SLB 9656

P28

P30

LPC
33MHz

SPI
50MHz

HDA 24MHz

HDA Aduiocodec
ALC3227

P25

InternalSPK

Combo Jack

SPIROM
8M

A

B

P7

Security Classification

Issued Date

THI S SH EET O F E NGIN EERING DR AW ING IS T HE PROPRIET ARY PROP ERT Y OF COMPAL ELECTRONICS, INC. AND C ONT AINS CONFIDENTSSIAizL
AND TR ADE SECRET INFORMAT ION. T HIS SHEET MAY NOT BE T RANS FERED FROM TH E CU STO DY OF TH E C OMPET ENT DIVIS ION OF R &D
DEPA RTMENT EXC EPT A S A UTH ORIZ ED BY COMP AL ELE CTR ONIC S, IN C. NEIT HER THIS SH EET NO R T HE I NFORMAT ION IT CONTAI NS
MAY BE USED BY OR D ISCLOSED TO ANY T HIR D PARTY W ITH OUT PRIOR W RITTEN C ONSE NT OF COMPAL ELE CTR ONIC S, INC .

C D

2011/06/29 2011/06/29

Compal SecretData

Deciphered Date

Titl e

eDo cum ent N umb er

Cus tom

Compal Electronics,Inc.

Block Diagrams

LA-B972P

Shee t 2 of 54Date: Thurs day, Marc h 20, 2014

E

Rev

0.1

5

4

3 2

1

CMSRC ACDRV

DC IN

D D

Battery

C C

B B

ACFET RBFET

BATDRV

RBFET

BATT

Charger
BQ24738

B+

Jumper

+3VALW

Jumper

+5VALW

+1.35V_VDDQ

Jumper

+0.6V_0.675VS

umper

Jumper

+1.05VS

SUSP#

SY8003 UMA only

EN

+1.5VSP

Jumper

+1.5VS

EC_ON

SYSON

SUSP#

SUSP#

VR12.5_VR_ON

RT8243

EN

RT8207M

EN

SY8208D

EN

TPS51622

EN

+3VALWP

+5VALWP

+1.35V_VDDQP

+0.6V_0.675VSJP

+1.05VSP

+VCC_CORE

RT8813 DIS only

GPU_PWR_EN

EN

SY8208D DIS only

SUSP#

A A

5

EN

4

+VGA_CORE

Jumper

+1.5VDIS

Security Classification

IssuedDate

THIS SHEET OF ENGINEERING DR AWING IS T HE PRO PRIETAR Y PROPERTY OF COMPAL ELECT RONICS, I NC. AND CO NTAINS CONFIDENTIASL
AND TRADE SECRET INFORMAT ION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUS TOD Y OF TH E COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RON ICS, INC. NEITHER TH IS SHEET NOR T HE INFORMATI ON IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WIT HOU T PRIOR WRITTEN CONSENT OF C OMPAL ELECTRONIC S, INC.

+1.5VS

Compal Secret Data

2013/08/07 2016/08/06

3 2

DecipheredDate

Compal Electronics, Inc.

Title

Power Block Diagram

ize DocumentNumber

LA-B972P

Thursday, March 20,2014

Date: Sheet of

1

Rev

0.4

5543

A

Power rail Control (EC) Source (CPU)
+RTCVCC X X
VIN X X
BATT+ X X
B+ X X
+VL X X
+3VL X X
+5VALW EC_ON X

1 1

+3VALW EC_ON X
+3VALW_EC EC_ON X
+3V_PCH PCH_PWR_EN X
+1.35V_VDDQ SYSON PM_SLP_S5#/PM_SLP_S4#
+5VS SUSP# PM_SLP_S3#
+3VS SUSP# PM_SLP_S3#
+1.5VS SUSP# PM_SLP_S3#
+1.05VS SUSP# PM_SLP_S3#
+0.6V_0.675VS SUSP#
+VCC_CORE X VR12.5_VR_ON

@ is NO SMT part (empty)
short@ : short pad , don't pop.

@EMI@,@ESD@,@RF@ : Reserve , don't pop.

RF@ : RF team request, must add.
EMI@ : EMI team request, must add.
ESD@ : ESD team request, must add.

LVDS@ : Support LVDS panel.

GCLK@ : Support GCLK
CRT@,CRTEMI@ : Support CRT port
eDP@,eDPEMI@ : Support eTP panel

B

C

DAX

<BOM Structure>

PCB

Part Number = DAZ14Z00100
PCB 14Z LA-B972P REV0 M/B 3

45@

ZZZ1

ROYALTY HDMIW/LOGO+HDCP

Part Number = RO0000003HM
ROYALTY HDMI W/LOG O+HDCP

D

<USB2.0 port>

USB2.0 port

E

DESTINATION

UMA Dis

0 USB 2.0/3.0(leftside) USB 2.0/3.0(leftside)

ZSO40@,ZSO56@ : Board ID config.

DIS@ : GPU BOM config.

1 USB 2.0(rightside) USB 2.0(right side)

2 USB 2.0(rightside) USB 2.0(right side)

3 WLAN/BT

WLAN/BT

4 Camera Camera

5

Touch screen(Options) Touch screen(Options)

6 X X

7 X X

2 2

3 3

UCPU1

CPU

UK1:+3V ALW_EC

EC

AP2 SMBCLK

SMBDATA

AH1

SML0CLK

AN1

SML0DATA

AK1

AU3 SML1CLK

SML1DATA

AH3

79 EC_SMB_CK2

EC_SMB_DA2

80

77 EC_SMB_CK1

EC_SMB_DA1

78

+3V_PCH

R=2.2K

+3V_PCH

R=1K

+3V_PCH

R=2.2K

+3VL

R=2.2K

2N7002

2N7002

+3VS

R=2.2K

EC_SMB_CK2
EC_SMB_DA2

R=100

+3VS

R=10K

PCH_SMBCLK
PCH_SMBDATA

+3VS

Thermal Sensor @

+3VS

eDP to LVDS bridge RTD2132R

BAT

SO‐DIMM A

SO‐DIMM B

<PCI-E,SATA,USB3.0>

Lane# PCI-E SATA USB3.0

1 1 USB3.0 USB3.0
2 2 X X
3 1 3 X X
4 2 4
5 3 10/100/1000LAN10/100/1000LAN
6 4
7
8 GPU(DISonly)

5

9 GPU(DISonly)
10 GPU(DISonly)
116L3 3 WLAN WLAN
12 L2 2 X X
13 L1 1 ODD ODD
14 L0 0 2.5"HDD 2.5"HDD

DESTINATION

UMA Dis

Cardreader(PCI-E) Cardreader(PCI-E)

GPU(DISonly)

Charger

4 4

G‐Sensor @

Security Classification

Issued Date

THI S SH EE T OF E NG INE ER ING DR AW IN G IS TH E PR OPR IE TAR Y PRO PE R TY OF COM PA L EL EC TRO NIC S, IN C. AN D CO NTA INS CONFIDENTISSAiL
AN D T RA DE S EC RE T IN FO RMA TI ON . TH IS SH EET M AY NOT BE TR A NS FE RE D F R OM THE CU STO DY OF THE COM PE TEN T DIV IS ION OF R &D
DE PA RTM ENT EX CE PT AS A UT HOR IZ ED BY CO MPA L EL EC TRO NIC S, IN C. NE ITH ER TH IS S HE ET N OR T HE I NFO RM ATI ON IT CO NTA IN S

A

B

MA Y BE USE D BY OR D IS CLO SE D TO AN Y T HIR D PAR TY WI THO UT P RIO R WR ITTE N CO NSE NT OF C OM PAL EL EC TRO NIC S, I NC .

C

2011/06/29 2011/06/29

Compal Secret Data

DecipheredDate

D

Title

ze Document Number

Custom

Compal Electronics, Inc.

Notes List

LA-B972P

Sheet 3 of 54Date: Thursday, March 20, 2014

E

Rev

0.1

5

4

UCPU1A

HASW ELL _MCP _E

3

CC97~CC102 must closed to connector not CPU

L

2

1

C45

EDP_TXN0

B46

EDP_TXP0

A47

EDP_TXN1

B47

EDP_TXP1

C47

EDP_TXN2

C46

EDP_TXP2

A49

EDP_TXN3

B49

EDP_TXP3

A45

EDP_AUXN

B45

EDP_AUXP

D20

EDP_RCO MP

A43

PRDY

PREQ
PROC_T CK
PROC_T MS

PROC_T RST

PROC_T DI
PROC_T DO

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

UC10

5

VCC

4

Y

74AUP1G07GW_TSSOP5

GND

J62
K62
E60
E61
E59
F63
F62

J60
H60
H61
H62
K59
H63
K60
J61

NC

A

RC1 1 @ 2 0_0201_5%
RC2 1 @ 2 0_0201_5%

XDP_PRDY#
XDP_PREQ #
XDP_TC K
XDP_TMS_CPU
XDP_TR ST#_CPU
XDP_TD I_CPU
XDP_TD O_CPU

XDP_OBS0_R
XDP_OBS1_R
XDP_OBS2_R
XDP_OBS3_R
XDP_OBS4_R
XDP_OBS5_R
XDP_OBS6_R
XDP_OBS7_R

1
2

DDR_PG_CNTL

3

EDP_CPU_LANE_N0_ C <18>
EDP_CPU_LANE_P0_C <18>

EDP_CPU_AUX#_C <18>
EDP_CPU_AUX_C <18>

EDP_COMP

COMPENSATION PU FOR eDP

EDP_COMP 2

24.9_0402_1%

T58 @ PAD

XDP_TC K <6>

XDP_TMS_CPU <6>
XDP_TD I_CPU <6>

XDP_TD O_CPU <6>

T80 @ PAD
T79 @ PAD
T52 @ PAD
T53 @ PAD
T54 @ PAD
T55 @ PAD
T56 @ PAD
T57 @ PAD

<eDP>

<eDP>

BKL_PW M_CPU <18,8>

+VCCIOA_OUT

1

RC3

DG V0.9 PEG_COMP

L

Trace width=20mil and spacing=25mil
Max length=100mil

XDP_TD I_CPU @ RC12 2
XDP_PREQ # @ RC13 2

XDP_TR ST#_CPU

1

@ESD@

CC99

0.1U_0402_16V7K

2

XDP_TR ST#_CPU <6>

+1.05VS_VCCST

1 51_0402_1%
1 51_0402_1%

RC234
10K_0402_5%

PROC_DETECT# D61

+1.35V_VDDQ

1 2

RC308
470_0402_5%

1

0.1U_0402_16V7K

2

C54

DDI1_TXN0

C55

DDI1_TXP0

B58

DDI1_TXN1

C58

DDI1_TXP1

B55

DDI1_TXN2

A55

DDI1_TXP2

A57

DDI1_TXN3

B57

DDI1_TXP3

C51

DDI2_TXN0

C50

DDI2_TXP0

C53

DDI2_TXN1

B54

DDI2_TXP1

C49

DDI2_TXN2

B50

DDI2_TXP2

A53

DDI2_TXN3

B53

DDI2_TXP3

UCPU1B

PROC_D ETECT

K61

CATERR

N62

PECI

PROCHO T

PROCPW RGD

AU60

SM_RCOMP0

AV60

SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CN TL1

DDR3_DRAMRST# <15,16>

DDI EDP

1 OF19

HASW ELL _MCP _E

MIS C

THER MAL

PW R

DDR3

2 OF19

<15> SM_PG_CTRL

EDP_DISP_ UTIL

JTAG

+1.35V_VDDQ

<20> PC H_DPB_N2
<20> PC H_DPB_P2
<20> PC H_DPB_N1
<20> PC H_DPB_P1

<30> H_PECI

1

1K_0402_1%

RC7 1

<20> PC H_DPB_N0
<20> PC H_DPB_P0
<20> PC H_DPB_N3
<20> PC H_DPB_P3

<29> PC H_DPC_N0
<29> PC H_DPC_P0
<29> PC H_DPC_N1
<29> PC H_DPC_P1

+3V_PCH

1 2

PAD T51@

2 56_0402_5% H_PROCHOT #_R K63

@

2 H_CPUPWRGD_R C61

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2 AU61
DDR3_DRAMRST# AV15
DDR_PG_CNTL AV61

DDR3_DRAMRST#

@ESD@ CC88

D D

<HDMI>

<DP TOCRT>

RC11 2 1 10K_0402_5% H_CPUPW RGD_R

+VCCIO_OUT

1 2

C C

<30,44> PROC HOT#

DG V0.5 Trace width=12~15 mil

L

DDR3 COMPENSATION SIGNALS

200_0402_1% 2 1 RC18 SM_RCOMP0
120_0402_1% 2
100_0402_1% 2

B B

PROCHO T#

Max length=500mil

1 RC19 SM_RCOMP1
1 RC20 SM_RCOMP2

62_0402_5%

@ESD@

10P_0402_50V8J

RC4

C295

1

2

RC6

<11,6> +1.05VS_PG

A A

Security Classification

Issued Date

THI S SH EE T OF E NG INE ER ING DR AW IN G IS TH E PR OPR IE TAR Y PRO PE R TY OF COM PA L EL EC TRO NIC S, IN C. AN D CO NTA INS CONFIDENTISSAiL
AN D T RA DE S EC RE T I NFO RM AT ION . TH IS SH EET M AY NOT BE TR A NS FE RE D FRO M THE CU STO DY OF T HE COM PE TE NT DI VIS ION OF R &D
DE PA RTM ENT EX CE PT AS A UT HOR IZ ED BY CO MPA L EL EC TRO NIC S, IN C. NE ITH ER TH IS S HE ET N OR T HE I NFO RM ATI ON IT CO NTA IN S

5

4

MA Y BE USE D BY OR DISC LO SE D TO AN Y TH IR D PA RTY W ITHO UT P RIO R WR ITT EN CO NS ENT OF COMP AL EL EC TRO NIC S, I NC .

3

2011/06/29 2011/06/29

Compal Secret Data

DecipheredDate

2

Title

DDI,MSIC,XDP

ze Document Number

Custom

Date:

LA-B972P

Rev

Sheet 4 of 54Thursday, March 20, 2014

1

0.1

Compal Electronics,Inc.

5

4

3

2

1

<15> DDR_A_D[0..63]

UCPU1C

D D

C C

B B

DDR_A_ D0
DDR_A_ D1
DDR_A_ D2
DDR_A_ D3
DDR_A_ D4
DDR_A_ D5
DDR_A_ D6
DDR_A_ D7
DDR_A_ D8
DDR_A_ D9
DDR_A_ D10
DDR_A_ D11
DDR_A_ D12
DDR_A_ D13
DDR_A_ D14
DDR_A_ D15
DDR_A_ D16
DDR_A_ D17
DDR_A_ D18
DDR_A_ D19
DDR_A_ D20
DDR_A_ D21
DDR_A_ D22
DDR_A_ D23
DDR_A_ D24
DDR_A_ D25
DDR_A_ D26
DDR_A_ D27
DDR_A_ D28
DDR_A_ D29
DDR_A_ D30 AR54
DDR_A_ D31 A N54
DDR_A_ D32 AY58
DDR_A_ D33A W58
DDR_A_ D34 AY56
DDR_A_ D35A W56
DDR_A_ D36 AV58
DDR_A_ D37 AU58
DDR_A_ D38 A V56
DDR_A_ D39 AU56
DDR_A_ D40 A Y54
DDR_A_ D41 AW54
DDR_A_ D42 AY52
DDR_A_ D43A W52
DDR_A_ D44 AV54
DDR_A_ D45 AU54
DDR_A_ D46 AV52
DDR_A_ D47 AU52
DDR_A_ D48 A K40
DDR_A_ D49 AK42
DDR_A_ D50 AM 43
DDR_A_ D51 AM4 5
DDR_A_ D52 AK45
DDR_A_ D53 A K43
DDR_A_ D54 AM40
DDR_A_ D55 AM 42
DDR_A_ D56 AM4 6
DDR_A_ D57 AK46
DDR_A_ D58 AM 49
DDR_A_ D59 AK49
DDR_A_ D60 AM 48
DDR_A_ D61 AK48
DDR_A_ D62 AM51
DDR_A_ D63 A K51

AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ1 0
SA_DQ1 1
SA_DQ1 2
SA_DQ1 3
SA_DQ1 4
SA_DQ1 5
SA_DQ1 6
SA_DQ1 7
SA_DQ1 8
SA_DQ1 9
SA_DQ2 0
SA_DQ2 1
SA_DQ2 2
SA_DQ2 3
SA_DQ2 4
SA_DQ2 5
SA_DQ2 6
SA_DQ2 7
SA_DQ2 8
SA_DQ2 9
SA_DQ3 0
SA_DQ3 1
SA_DQ3 2
SA_DQ3 3
SA_DQ3 4
SA_DQ3 5
SA_DQ3 6
SA_DQ3 7
SA_DQ3 8
SA_DQ3 9
SA_DQ4 0
SA_DQ4 1
SA_DQ4 2
SA_DQ4 3
SA_DQ4 4
SA_DQ4 5
SA_DQ4 6
SA_DQ4 7
SA_DQ4 8
SA_DQ4 9
SA_DQ5 0
SA_DQ5 1
SA_DQ5 2
SA_DQ5 3
SA_DQ5 4
SA_DQ5 5
SA_DQ5 6
SA_DQ5 7
SA_DQ5 8
SA_DQ5 9
SA_DQ6 0
SA_DQ6 1
SA_DQ6 2
SA_DQ6 3

HASWELL_MCP_E

DDR CHANNELA

3 OF19

SA_CL K#0

SA_CL K0

SA_CL K#1

SA_CL K1

SA_CK E0
SA_CK E1
SA_CK E2
SA_CK E3

SA_CS #0
SA_CS #1

SA_ODT0

SA_RA S

SA_W E

SA_CA S

SA_BA0
SA_BA1
SA_BA 2

SA_MA 0
SA_MA 1
SA_MA 2
SA_MA 3
SA_MA 4
SA_MA 5
SA_MA 6
SA_MA 7
SA_MA 8

SA_MA 9
SA_MA 10
SA_MA 11
SA_MA 12
SA_MA 13
SA_MA 14
SA_MA 15

SA_DQS N0
SA_DQS N1
SA_DQS N2
SA_DQS N3
SA_DQS N4
SA_DQS N5
SA_DQS N6
SA_DQS N7

SA_DQS P0
SA_DQS P1
SA_DQS P2
SA_DQS P3
SA_DQS P4
SA_DQS P5
SA_DQS P6
SA_DQS P7

SM_VR EF_CA
SM_VR EF_DQ0
SM_VR EF_DQ1

<DDR3L>

AU37AH63
AV37
AW3 6
AY36

AU43
AW4 3
AY42
AY43

AP33
AR32

AP32
AY34

AW3 4
AU34

AU35
AV35
AY41

AU36

DDR_A_ MA0
DDR_A_ MA1

AY37

DDR_A_ MA2

AR38

DDR_A_ MA3

AP36

DDR_A_ MA4

AU39

DDR_A_ MA5

AR36

DDR_A_ MA6

AV40
AW3 9 DDR_A_ MA7
AY39 DDR_A_MA8
AU40 D DR_A_M A9
AP35 DDR_A_MA 10
AW4 1 DDR_A_M A11
AU41 DDR _A_MA12
AR35 DDR _A_MA13
AV42 DDR_A_MA 14
AU42 DDR _A_MA15

AJ61 DD R_A_DQS# 0
AN62 DDR_A_D QS#1
AM58DD R_A_DQS#2
AM55DD R_A_DQS#3
AV57 DDR_A_ DQS#4
AV53 DDR_A_ DQS#5
AL43 DDR_A _DQS#6
AL48 DDR_A _DQS#7

AJ62 DD R_A_DQS0
AN61 DDR_A_ DQS1
AN58 DDR_ A_DQS2
AN55 DDR_A_ DQS3
AW5 7DDR_A_DQS4
AW5 3DDR_A_DQS5
AL42 DD R_A_DQS6
AL49 DDR_A_DQS 7

AP49 +V_SM_ VREF_CN T
AR51 + V_DDR_ REFA_R
AP51 +V_DD R_REFB_ R

M_CLK_ DDR#0 <15>
M_CLK_ DDR0 <15>
M_CLK_ DDR#1 <15>
M_CLK_ DDR1 <15>

DDR_CK E0_DIMMA <15>
DDR_CK E1_DIMMA <15>

DDR_CS 0_DIMMA# <15>
DDR_CS 1_DIMMA# <15>

DDR_A_ RAS# < 15>

DDR_A_W E# < 15>

DDR_A_ CAS# < 15>

DDR_A_ BS0 <15 >
DDR_A_ BS1 <15 >
DDR_A_ BS2 <15 >

DDR_A_MA[0..15] <15>

DDR_A_DQS#[0..7] <15>

DDR_A_DQS[0..7] <15>

+V_SM _VREF_C NT

+V_DD R_REFA_ R
+V_DD R_REFB_ R

<16> DDR_B_D[0..63]

DDR_B_ D0 AY31
DDR_B_ D1 AW 31
DDR_B_ D2 A Y29
DDR_B_ D3 AW29
DDR_B_ D4 AV 31
DDR_B_ D5 AU31
DDR_B_ D6 AV 29
DDR_B_ D7 AU2 9
DDR_B_ D8 AY27
DDR_B_ D9 AW 27
DDR_B_ D10 AY25
DDR_B_ D11A W25
DDR_B_ D12 AV27
DDR_B_ D13 AU27
DDR_B_ D14 A V25
DDR_B_ D15 AU25
DDR_B_ D16 AM 29
DDR_B_ D17 AK29
DDR_B_ D18 AL28
DDR_B_ D19 A K28
DDR_B_ D20 AR29
DDR_B_ D21 AN29
DDR_B_ D22 A R28
DDR_B_ D23 AP28
DDR_B_ D24 AN26
DDR_B_ D25 AR26
DDR_B_ D26 AR25
DDR_B_ D27 AP25
DDR_B_ D28 AK26
DDR_B_ D29 AM 26
DDR_B_ D30 AK25
DDR_B_ D31 AL2 5
DDR_B_ D32 AY23
DDR_B_ D33 AW23
DDR_B_ D34 A Y21
DDR_B_ D35 AW21
DDR_B_ D36 A V23
DDR_B_ D37 A U23
DDR_B_ D38 AV21
DDR_B_ D39 AU21
DDR_B_ D40 AY19
DDR_B_ D41A W19
DDR_B_ D42 AY17
DDR_B_ D43 AW17
DDR_B_ D44 A V19
DDR_B_ D45 AU19
DDR_B_ D46 A V17
DDR_B_ D47 A U17
DDR_B_ D48 AR21
DDR_B_ D49 AR22
DDR_B_ D50 AL21
DDR_B_ D51 AM 22
DDR_B_ D52 A N22
DDR_B_ D53 AP21
DDR_B_ D54 A K21
DDR_B_ D55 AK22
DDR_B_ D56 AN20
DDR_B_ D57 A R20
DDR_B_ D58 AK18
DDR_B_ D59 AL1 8
DDR_B_ D60 AK20
DDR_B_ D61 AM 20
DDR_B_ D62 AR18
DDR_B_ D63 A P18

UCPU1D

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ1 0
SB_DQ1 1
SB_DQ1 2
SB_DQ1 3
SB_DQ1 4
SB_DQ1 5
SB_DQ1 6
SB_DQ1 7
SB_DQ1 8
SB_DQ1 9
SB_DQ2 0
SB_DQ2 1
SB_DQ2 2
SB_DQ2 3
SB_DQ2 4
SB_DQ2 5
SB_DQ2 6
SB_DQ2 7
SB_DQ2 8
SB_DQ2 9
SB_DQ3 0
SB_DQ3 1
SB_DQ3 2
SB_DQ3 3
SB_DQ3 4
SB_DQ3 5
SB_DQ3 6
SB_DQ3 7
SB_DQ3 8
SB_DQ3 9
SB_DQ4 0
SB_DQ4 1
SB_DQ4 2
SB_DQ4 3
SB_DQ4 4
SB_DQ4 5
SB_DQ4 6
SB_DQ4 7
SB_DQ4 8
SB_DQ4 9
SB_DQ5 0
SB_DQ5 1
SB_DQ5 2
SB_DQ5 3
SB_DQ5 4
SB_DQ5 5
SB_DQ5 6
SB_DQ5 7
SB_DQ5 8
SB_DQ5 9
SB_DQ6 0
SB_DQ6 1
SB_DQ6 2
SB_DQ6 3

HASWELL_MCP_E

DDR CHANNELB

4 OF19

SB_CK #0

SB_CK 0

SB_CK #1

SB_CK 1

SB_CK E0
SB_CK E1
SB_CK E2
SB_CK E3

SB_CS #0
SB_CS #1

SB_ODT0

SB_RA S

SB_W E

SB_CA S
SB_BA0

SB_BA1
SB_BA 2

SB_MA 0
SB_MA 1
SB_MA 2
SB_MA 3
SB_MA 4
SB_MA 5
SB_MA 6
SB_MA 7
SB_MA 8

SB_MA 9
SB_MA 10
SB_MA 11
SB_MA 12
SB_MA 13
SB_MA 14
SB_MA 15

SB_DQS N0
SB_DQS N1
SB_DQS N2
SB_DQS N3
SB_DQS N4
SB_DQS N5
SB_DQS N6
SB_DQS N7

SB_DQS P0
SB_DQS P1
SB_DQS P2
SB_DQS P3
SB_DQS P4
SB_DQS P5
SB_DQS P6
SB_DQS P7

AM38
AN38
AK38
AL38

AY49
AU50
AW4 9
AV50

AM32
AK32

AL32
AM35

AK35
AM33

AL35
AM36
AU49

AP40 DDR_B_MA 0
AR40 DDR _B_MA1
AP42 DDR_B_MA 2
AR42 DDR _B_MA3
AR45 DDR _B_MA4
AP45 DDR_B_MA 5
AW4 6 DDR_B_ MA6
AY46 DDR_B_MA 7
AY47 DDR_B_MA 8
AU46 DDR _B_MA9
AK36 DDR_B_MA 10
AV47 DDR_B_MA 11
AU47 D DR_B_M A12
AK33 DDR_B_MA 13
AR46 D DR_B_M A14
AP46 DDR_B_MA 15

AW3 0DDR_B_DQS#0
AV26 DDR_B _DQS#1
AN28 DDR_ B_DQS#2
AN25 DDR_B_ DQS#3
AW2 2DDR_B_DQS#4
AV18 DDR_B _DQS#5
AN21 DDR_B_ DQS#6
AN18 DDR_ B_DQS#7

AV30 DDR_ B_DQS0
AW2 6DDR_B_DQS1
AM28 DDR_B_DQS 2
AM25 DDR_B_ DQS3
AV22 DDR_B _DQS4
AW1 8DDR_B_DQS5
AM21 DDR_B_DQS 6
AM18 DDR_B_DQS 7

<DDR3L>

M_CLK_ DDR#2 <16>
M_CLK_ DDR2 <16>
M_CLK_ DDR#3 <16>
M_CLK_ DDR3 <16>

DDR_CK E0_DIMMB <16>
DDR_CK E1_DIMMB <16>

DDR_CS 0_DIMMB# <16>
DDR_CS 1_DIMMB# <16>

DDR_B_ RAS# < 16>

DDR_B_W E# < 16>

DDR_B_ CAS# < 16>

DDR_B_ BS0 <16 >
DDR_B_ BS1 <16 >
DDR_B_ BS2 <16 >

DDR_B_MA[0..15] <16>

DDR_B_DQS#[0..7] <16>

DDR_B_DQS[0..7] <16>

A A

Security Classification

Issued Date

THI S S HE ET O F E NG INE E RI NG D RA WI NG I S T HE P R OP RI ET AR Y P RO PE R TY O F C OM PA L EL EC TR ON IC S, IN C. AN D C ONT AIN S CONFIDENSSTiIzAeL
AN D T RA DE SE CR E T I NF OR MA TI ON . T HIS S HE ET MA Y N OT BE T RAN SF E RE D F R OM TH E C US TO DY OF T HE CO MP E TEN T D IVI SI ON OF RC&uD
DE PA RT ME NT EXC E PT AS A UT HOR I ZE D BY COM PA L E L EC TR ONI C S, I NC . NEI THE R THIS S HE ET NOR T HE IN FO RM AT IO N I T CON TAI NS

5

4

3

MA Y BEU SE D BY ORD IS CLO SE D TO ANY TH IR D P AR TY W IT HOU T PR IO R W R IT TE N CO NS EN T OF COM PA L E L EC TR ON IC S, I NC.

2011/06/29 2011/06/29

Compal Secret Data

Deciphered Date

2

Title

Docum ent Number

stom

DDRIII

LA-B972P

Rev

Sheet 5 of 54Date: Thurs day, Mar ch 20,2014

1

0.1

Compal Electronics,Inc.

5

+RTCVCC

330K_ 0402_5% 1 2 RC23 6 PCH_ INTVRMEN

INTVRMEN

H：Integrated VRM enable

*

L：Integrated VRM disable

D D

HDA_SY NC_R HDA_SY NC

Intel ME update

<30> HDA_SDO

C C

B B

+3V_P CH

12

RC283 @

210_0402_5%

R3d

12

RC304 @

100_0402_1%

+3V_P CH +3V_P CH

12

RC41 @

210_0402_5%

R4

12

RC301 @

100_0402_1%

<XDP>

<PCH site>
<XDP>

<PCH site>

<XDP>

<PCH site>

<XDP>

A A

<PCH site>

<PCH site>

<PCH site>

RC353 short@

1 2

0_0402_5%

short@
RC356 1 20_0201_5% HDA_SDOUT

PCH_J TAG_TDO

PCH_J TAG_TDI

Contact ok

R8

XDP_TRS T# 1

PCH_J TAG_TMS

XDP_TMS

XDP_TDI_ SWITCH RC1 99 1 @ 2 0_0201_5% XDP_TDI_C PU

PCH_J TAG_TDO RC307 1 @ 2 0_0201_5% XD P_TDI_SW ITCH

XDP_TDI

PCH_J TAG_TDI

XDP_TDO

XDP_TCK:XDP contact with CPU No 0ohm(RS5)

PCH_J TAG_TCK

XDP_TCK _JTAGX

XDP_TCK _JTAGX RC30 6 1 @ 2 0_0201_5% XD P_TDO

5

9/17 add RF solution

12

RC46

210_0402_5%

@

12

RC302

100_0402_1%

RC37 @

RC196 1 @ 2 0_0201_5% XDP_ TMS_CPU

RC200 1 2 0_0201_5% X DP_TDI_S WITCH

short@

RC195 1 2 0_0201_5% XDP_TDI

short@

RC198 1 @ 2 0_0201_5% X DP_TDO_C PU

RC194 1 2 0_0201_5% PCH_JTAG_TDO

short@

J1S

RC197 1 @ 2 0_0201_5% XDP _TCK

J2D

RC193 1 2 0_0201_5%

short@

J2S

<25> HDA_BITCL K_AUDIO

<25> HDA_R ST_AUDIO#

<25> HDA_SY NC_AUDIO

<25> HDA_S DOUT_AUDIO

CM28

@

2 HD A_BITCLK_ AUDIO

1

22P_0 402_50V8J

CM29

@

2

1

22P_0 402_50V8J

XDP_TCK _JTAGX

@

S1

2 0_0201_5%

S2

S3
J3S
J4d

S4

J3D

+RTCVCC

RC32 20K _0402_ 5%

RC34 20K _0402_ 5%

HDA_RS T_AUDIO#

PCH_J TAG_RST#

4

1

12

CC2

1U_0402 _6.3V6K
1 2
1 2

1U_0402 _6.3V6K

R5

XDP_TRS T#_CPU

2

1

12

CC5

2

EMI@ R C367

HDA_BITC LK_AUDIO 2 1 HDA_ BIT_CLK

33_0402_5%

HDA_RS T_AUDIO# 2

+3V_P CH

12

RC45 @

210_0402_5%

12

RC303 @

100_0402_1%

Contact ok

<CPU site>

XDP_TCK <4>

4

JCMOS1

SHORT PADS

PCH_RTC RST#
PCH_SR TCRST#

JME1

SHORT PADS

RP1

1

8
7 HD A_RST#

3

6 HDA _SYNC_R
5 HDA_S DOUT

4

33_0804_8P4R_5%

PCH_J TAG_TMS

XDP_TDI_ CPU <4>

XDP_TDO _CPU <4 >

<PCH site>

<CPU andXDP>

<XDP>

CMOS

XTAL@

CC3

18P_0 402_50V8J

MECMOS

+RTCVCC

<25> HDA_SDIN 0

2

RC35 1

SI# 2012.1 1.1 Add RC367 EMI@ toisolate
Audio Clock by EM Irequest

<CPU site>
<PCH site>

<CPU>

XDP_TRS T#_CPU RC16 2 @ 1 51_0402_1%

<XDP>

XDP_TDO _CPU RC10 2 1 51_0402_1%

XDP_TDO RC14 2

XDP_TCK R C15 2

XTAL@

1 2

RC31 10M_0402_5%

XTAL@

YC1

1 2

32.768 KHZ Q13FC13501000500

1

2

1M_0402_5%

PCH_J TAG_RST#
PCH_J TAG_TCK
PCH_J TAG_TDI
PCH_J TAG_TDO
PCH_J TAG_TMS

T156PAD

XDP_TCK _JTAGX

T157PAD

<CPU site>

<4> XDP_TRST#_ CPU

R1d

R7

R2

PCH_RTC X1

PCH_RTC X1
PCH_RTC X2
SM_INTRU DER#
PCH_INTV RMEN
PCH_SR TCRST#
PCH_RTC RST#

HDA_BIT_CLK
HDA_SY NC
HDA_RS T#
HDA_SD IN0

HDA_SD OUT

<4> XDP_TMS_C PU

R6

51_0402_5%PCH_JTAG_TCK
1 @

R9

@

1 51_0402_1%

1 51_0402_1%

3

PCH_RTC X1
PCH_RTC X2

CC4 XTAL @
18P_0 402_50V8J

2

EC_+1 .05VS_P G

XDP_TDO _CPU

XDP_TDI_ CPU

2 RC38

+1.05 VS_VCCS T

+1.05 VS_VCCS T

3

+RTCVCC

CC6

1U_0402 _6.3V6K

PCH_RTC X1 <31>

UCPU1E

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER

AV7

INTVRMEN

AV6

SRTCRST

AU7

RTCRST

AW8

HDA_BC LK/I2S0_SC LK

AV11

HDA_SY NC/I2S0_SF RM

AU8

HDA_RS T/I2S_MC LK

AY10

HDA_SD I0/I2S0_R XD

AU12

HDA_SD I1/I2S1_R XD

AU11

HDA_SD O/I2S0_TX D

AW10

DOCKEN /I2S1_TX D

AV10

HDA_DOCK _RST/I2S1 _SFRM

AY8

I2S1_S CLK

AU62

PCH_TRS T

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

TP5

AC4

TP6

AE63

JTAGX

AV2

RSVD

XDP_TRS T#_CPU

<EC output>

Topolog

Default Setting: Dual
TCK S ca n Chains
(also kn own as
"Shared JTAG" in
other do cum ent)

Single T CK scan chain
(also kn own as "Com m on
JTAG" in other docum
ent)

Security Classification

THI S SHE ET OF E NG IN EE RI NG DR AW I NG IS THE PR OP R IE TA RY P RO P ER TY OF C OM PA L EL EC TR ONI C S, I NC . A ND CON TAI NS CO NF IDE NTI AL
AN D T RA DE SE CR E T I NF OR MA TI ON. TH IS SH EE T M A Y N OT BE T RA NS FE RE D FR OM TH E C US TO DY OF T HE CO MP ET EN T D IVI SI ON OF R& D
DE PA RT ME NT E X CE PT AS AU TH OR IZ ED BY C OM PA L E L EC TR ONI C S, I NC . NE IT HER TH IS SH EE T NOR TH E INF O RM ATI ON IT C ONT AIN S
MA Y BE US ED BY OR D IS CL OSE D TO ANY TH IR D PAR TY WI TH OU T PR IO R W R IT TE N CO NS EN T OF COM PA L E L EC TR ON IC S, INC.

15mils

1

2

RTC

AUDIO

JTAG

2 1

10K_0 402_5%

@ UC5

2

1OE V CC

3

1A 1B

5

2OE

6

2A

12

3OE

11

3A

15

4OE

14

4A

8

GND

74CBTLV 3126DS _SSOP16

Issued Date

1

BAV70 W 3PC/ C_SOT-323

HASWELL_MCP_E

5 OF19

RC240

@

2B

3B

4B
NC
NC

<30> EC_+1.05 VS_PG

+RTCBATT_ R

1K_04 02_5%

3

SATA

+3VS

XDP_TDO

XDP_TDI_ SWITCH

XDP_TMS

XDP_TRS T#

RC33

12 2

+3VL

SATA_ RN0/PER N6_L3
SATA_ RP0/PE RP6_L3
SATA_ TN0/PE TN6_L3
SATA_TP 0/PETP6 _L3

SATA_ RN1/PER N6_L2
SATA_ RP1/PE RP6_L2
SATA_ TN1/PE TN6_L2
SATA_TP 1/PETP6 _L2

SATA_ RN2/PER N6_L1
SATA_ RP2/PE RP6_L1
SATA_ TN2/PE TN6_L1
SATA_TP 2/PETP6 _L1

SATA_ RN3/PER N6_L0
SATA_ RP3/PE RP6_L0
SATA_ TN3/PE TN6_L0
SATA_TP 3/PETP6 _L0

SATA0 GP/GP IO34
SATA1 GP/GP IO35
SATA2 GP/GP IO36
SATA3GP /GPIO37

@CC8 6

1 2

.1U_04 02_16V7K

EC_+1 .05VS_P G

DC1

16
4

7

10

13
1
9

Description

In this topology, the
CPU JTAG chain will be
controlled by TCK0 and
TCK1 wil l control
the PCH JTAG chain.

In th is topolog y, PCH
TDI- TD O and CPU TDI-TDO
will be chained to form
one JTAG scan chain
controlled by TCK0

2011/06/29

Compal Secret Data

2

+RTCBATT

15mils15mils

SATA_IR EF

SATA_RCOMP

SATALE D

Deciphered Date

2

RTC BAT conn

J5
H5
B15
A15

J8
H8
A17
B17

J6
H6
B14
C15

F5
E5
C17 PCIE _PTX_DRX _N6 CC71
D17 PCIE _PTX_DRX _P6 CC81

V1
U1 ODD_PL UG#
V6 PC H_GPIO36 T159
AC1 mSATA_DE T#

A12
L11

TP7

K10

TP8

C12

SATA_C OMP 1

U3

SATA_L ED#

U16

1 5

NC V CC

2

A

3

GND

74AUP 1G07GW _TSSOP5

2

-

JRTC1
LOTES_A AA-BAT-054-K01
CONN@

<9> MPHY_PW REN

2 0.1U_040 2_16V7K
2 0.1U_040 2_16V7K

ODD_PL UG# <22>

PAD

mSATA _DET# <7>

SATA_L ED# <27,9>

+1.05 VS_VCCS T

12

R511
10K_0 402_5%

+1.05 VS_VCCS ATA3PLL <Page 12>

RC39

3K_04 02_1%

4

Y

2

+3V_P CH

Be st Us e for

- Run control oper.

- ME/S x debug

-B oundary Scan/
Manufacturing est

Compal Electronics, Inc.

2011/06/29 Title

Siz e Do cument Num ber
Custo m

1

+RTCBATT

15mils

1

+

MPHY_P WREN RC217 1 2 1 0K_0402 _5%

ODD_PL UG# R C218 1 2 1 00K_040 2_5%

SATA_P RX_DTX_N 0 <2 2>
SATA_P RX_DTX_P 0 <22>
SATA_P TX_DRX_N 0 <2 2>
SATA_P TX_DRX_P 0 <22>

SATA_P RX_DTX_N 1 <2 2>
SATA_P RX_DTX_P 1 <22>
SATA_P TX_DRX_N 1 <2 2>
SATA_P TX_DRX_P 1 <22>

PCIE_P RX_DTX_N 6 <21>
PCIE_P RX_DTX_P 6 < 21>
PCIE_P TX_C_DRX _N6 <21>
PCIE_P TX_C_DRX _P6 <21>

DG V0.9 SATA_COMP

L

Width=12mil
Max length=500mil

+1.05 VS_PG <11,4> <CPU,XDP,XDP Switch>

Resistors
Stuffed

R1d,R2,R3d,
R4,R5,J1d
J2d,J3d*
J4d and Rs5*

J1s,J2s,J3s**
R2,R4,R5,R5s**

2.5" HDD

ODD

WLAN

Resistors
ufStuffed

J1s, J2s,
J3s
R6,R7,R8,R9

R1d,r3 d,J1d,J2 d

J3d**,J 4d,

R6,R7, R8,R9

RTC,SATA,HDA,JTAG

LA-B972P

Sheet 6 of 54Date: Thurs day, Mar ch 20, 2014

1

+3VS

Rev

0.1

5

PCIELAN

D

PCIE Cardreader

WLAN

GPU

+3VS

4 5
3 6 SYS_RESET#
2 7 EC_KBRST#
1 8 MSATA_DET#

+3VS

4 5 PCIECLKREQ0#
3 6 MINI1_CLKREQ#
2 7 PCI_PIRQB#

C C

1 8 PCH_GPIO33

DB# 2013.08.27 RC368 place near CPU

<30> EC_SPI_SI

<30> EC_SPI_SO

<30> EC_SPI_CS0#

<30> EC_SPI_CLK

B B

+3V_PCH

RC85

<23> CLK_PCIE_LAN#
<23> CLK_PCIE_LAN

<23> CLK_PCIE_CR#
<23> CLK_PCIE_CR

<23,9> CR_CLKREQ#

<21> CLK_PCIE_MINI1#
<21> CLK_PCIE_MINI1

<32> CLK_PCIE_GPU#
<32> CLK_PCIE_GPU
<32,8> GPU_CLKREQ#

RPH11

LAN_CLKREQ#

10K_0804_8P4R_5%
RPH12

10K_0804_8P4R_5%

PCH_SPI_CS0#
PCH_SPI_SO 7 2 PCH_SPI_SO_R
PCH_SPI_SI 6 3 PCH_SPI_SI_R
PCH_SPI_HOLD# 5 4 PCH_SPI_SIO3

PCH_SPI_CLK RC368 1 2 PCH_SPI_CLK_R

EMI@ 15_0402_5%

PCH_SPI_SIO2 5

1

2

3.3K_0402_5%

SYS_RESET# <8>
EC_KBRST# <30,9>

MSATA_DET# <6>

PCI_PIRQB# <8>
PCH_GPIO33 <9>

RPH19

1 PCH_SPI_CS0#_R

8

15_0804_8P4R_5%

RPH20

18
2

7

3

6

15_0804_8P4R_5%

EMI@ RC369 1 2 short@ RC56 1 2 0_0402_5% PCH_SPI_CLK_R

DB# 2013.08.27 RC369 place near SPI ROM

+3V_PCH

@

RC80

3.3K_0402_5%

1 2

4

15_0402_5%

PCH_SPI_CS0#_R 1
PCH_SPI_SO_R 2
PCH_SPI_WP# 3

SPI ROM8M

4

<23> LAN_CLKREQ#

<9> PCIECLKREQ4#

<21> MINI1_CLKREQ#

<28,30> LPC_AD0
<28,30> LPC_AD1
<28,30> LPC_AD2
<28,30> LPC_AD3

<28,30> LPC_FRAME#

PCH_SPI_SI_R PCH_SPI_SIO3 AF1
PCH_SPI_SO_R

PCH_SPI_CS0#_R

PCH_SPI_WP#

UC2

CS# VCC
SO/SIO1 HOLD#
WP# SCLK
GND SI/SIO0

EN25Q64-104HIP

SI# 2012.11.1 Add RC368 ,RC369to

Isolate SPI Clock by EMI request

8
7
6
5

4

UCPU1F

CLK_PCIE_LAN# C43
CLK_PCIE_LAN
PCIECLKREQ0#

CLK_PCIE_CR# B41
CLK_PCIE_CR
CR_CLKREQ#

CLK_PCIE_MINI1# C41
CLK_PCIE_MINI1 B42
LAN_CLKREQ#

CLK_PCIE_GPU# B38
CLK_PCIE_GPU
GPU_CLKREQ#

PCIECLKREQ4# U5

MINI1_CLKREQ#

LPC_AD0
LPC_AD1
LPC_AD2 AY12
LPC_AD3 AW 11

LPC_FRAME# AV12

PCH_SPI_CLK AA3
PCH_SPI_CS0# Y7

PCH_SPI_SI
PCH_SPI_SO

PCH_SPI_SIO2

EON SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P MXIC

SA00006N100 S IC FL 64M MX25L6473EM2I-10G SOP 8P

WINBOND SA000039A30 S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM
Micron SA00005L100 S IC FL 64M N25Q064A13ESEC0F SO8W 8+P3V_PCH

PCH_SPI_HOLD# 2
PCH_SPI_CLK_R

PCH_SPI_SI_R

C42

U2

A41

Y5

CLKOUT_PCIE_N2

CLKOUT_PCIE_P2

AD1

CLKOUT_PCIE_N3

C37

N1

A39
B39

CLKOUT_PCIE_P4

B37
A37

T2

AU14

LAD0

AW12

LAD1

LAD2

LAD3

LFRAME

SPI_CLK

SPI_CS0

Y4

SPI_CS1

AC2

SPI_CS2

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

SPI_IO3

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0

PCIECLKRQ0/GPIO18

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1

PCIECLKRQ1/GPIO19

PCIECLKRQ2/GPIO20

CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21

CLKOUT_PCIE_N4

PCIECLKRQ4/GPIO22

CLKOUT_PCIE_N5

CLKOUT_PCIE_P5

PCIECLKRQ5/GPIO23

UCPU1G

LPC

SPI C-LINK

3.3K_0402_5%1 RC84

HASW ELL_MCP_E

7 OF19

HASW ELL_MCP_E

CLOCK
SIGNALS

6 OF19

SMBUS

3 2

XTAL24_IN

XTAL24_OUT

DIFFCLK_BIASREF

CLKOUT_LPC_0
CLKOUT_LPC_1

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

SMBALERT/GPIO11

SMBCLK

SMBDATA

SML0ALERT/GPIO60

SML0CLK

SML1ALERT/PCHHOT/GPIO73

1

CC11

0.1U_0402_16V7K

2

@

SML0DATA

SML1CLK/GPIO75

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST

A25

CPU_XTAL24_IN

B25

CPU_XTAL24_OUT

K21

TP15

M21

TP16

C26 PCH_CLK_BIASREF

C35 TESTLOW1

TP19

C34 TESTLOW2

TP20

AK8 TESTLOW 3

TP21

AL8 TESTLOW4

TP22

AN15 CLK_PCI0
AP15 CLK_PCI1

B35

CLK_CPU_ITP#

A35

CLK_CPU_ITP

AN2 SMBALERT#
AP2 SMBCLK
AH1 SMBDATA
AL2 USB_CR_PWREN
AN1 SML0CLK
AK1 SML0DATA
AU4 SML1ALERT#
AU3 SML1CLK
AH3 SML1DATA

AF2
AD2
AF4

3K_0402_1%

1

EMI@ RC61 1
EMI@ RC62 1

CPU_XTAL24_IN

RC52

2

4

5 RPH22

3

6

217

8
2 22_0402_5% CLK_PCI_LPC

2 22_0402_5% CLK_PCI_TPM

SMBALERT# <9>

USB_CR_PWREN <8>

SML1ALERT# <9>

+1.05VS_AXCK_LCPLL

10K_0804_8P4R_5%

T82 @ PAD
T81 @ PAD

9/17 add RFsolution

2N7002DWH_SOT363-6

SML1CLK 6

SML1DATA

CPU_XTAL24_IN <31>

<Page12>

<PV>PRH13 change to RPH22.

CLK_PCI_LPC <30>
CLK_PCI_TPM <28>

<XDP CLK reserveTP>

@RF@

CM30

1

2 CLK_PCI_LPC

22P_0402_50V8J

@RF@

CM31

1 2 CLK_PCI_TPM

22P_0402_50V8J

@RF@

CM33

1

2 PCH_SPI_CLK_R

22P_0402_50V8J

2

QC2A 2N7002DWH_SOT363-6

6 1

SMBCLK

QC2B

SMBDATA

QC6A

3 4

2

1

3 4

2N7002DWH_SOT363-6

QC6B

CPU_XTAL24_IN
CPU_XTAL24_OUT

XTAL@

CC9

18P_0402_50V8J

1

XTAL@

2

1M_0402_5%

3

3 1

GND GND

1

4

2

XTAL@

24MHZ 12PF 5YEA24000122IF240Q3

<EC>

SML0CLK 1K_0402_5% 1 2 RC72
SML0DATA 1K_0402_5% 1 2 RC73

SMBCLK
SMBDATA
SML1CLK
SML1DATA

+3VS +3VS

10K_0402_5%

5

2N7002DWH_SOT363-6

+3VS

5

RC78

RC79
10K_0402_5%

1 2

1 2

EC_SMB_CK2 <18,30,32>

EC_SMB_DA2 <18,30,32>

1
RC48

1

1

2

YC2

RP2 1

2
3
4

PCH_SMBCLK <15,16>

PCH_SMBDATA <15,16>

XTAL@

CC10
18P_0402_50V8J

+3V_PCH

8 2.2K_0804_8P4R_5%
7
6
5

D

A A

remove thernal sensor 10/14

Security Classification

Issued Date

THI S SHE ET O F ENG IN EER ING DR AW IN G IS T HE PR OP RIE TA RY P ROPER TY O F CO MPA L EL ECT RO NI CS, INC. AN D CO NTA INS CONFIDENTIASSL
AND T RADE SECRE T INF ORMAT ION . THI S SHEE T MAY NOT BE T RANSF ERED FRO M THE CUST OD Y OF T HE COMPETEN T DIVIS ION OF R&D
DEPAR TMENT EX CEPT AS A UT HO RIZ ED BY C OMPAL E LEC TR ON ICS , INC. NEIT HER THIS SH EET N OR TH E INFO RM ATION IT CONTAIN S

5

4

MAY BE USE D BY OR DI SCLOSE D TO A NY TH IRD PA RT Y WITHOUT PRIO R WR IT TEN CON SE NT OF CO MPAL ELE CT RO NIC S, INC.

3 2

2011/06/29 2011/06/29

Compal Secret Data

DecipheredDate

Compal Electronics, Inc.

Title

CLK,SPI,SMB,LPC

ize Document Number

Custom

LA-B972P

Rev

Sheet 7 of 54Date: Thursday, March 20, 2014

1

0.1

5 4 3 2 1

T83

Non Deep S3RC91-->SMT
Deep S3 RC93-->SMT

<9> SUSWARN#_R

D D

<30> PCH _PW ROK

Deep S3

C C

<30> SUSACK#

<30> SYS_PWROK

<30> P CH_RSMRST#

<30> PCH_SUSWARN#

<30> PBT N_O UT#

<30,44,45,46> AC IN

C70 ES D@

1 2 PCH_PWROK

0.047U_0402_16V7K

1 100K_0402_5% SYS_PWROKRC112 2

SUSW ARN#_R RC91 1

short@ RC93 1

PCH_PW ROK short@ RC1001 2 0_0402_5%

short@ RC99 1

short@ RC1041
short@ RC1031

@

2 0_0201 _5%

20_0201_5%

<7> SYS _RESET#

2 0_0402_5%

2 0_0402_ 5%
2 0_0402_ 5%

2 DC2

1

SUSACK#_R AK2
SYS_RESE T# AC3
SYS_PWR OK AG2

PM_P WROK_R AY7
APW ROK_R AB5

PLT_RST #_PCH AG7

PCH_RSMRST# A W6
SUSWARN#_R AV4
PBTN_OUT#_R AL7
ACIN_R AJ8
PM_B ATLOW# AN4
PM_S LP_S0#_R AF3
PCH_SLP_WLAN# AM5

short@ RC268 1 20_0201_5%

PAD

RC269 1 2 0_0201_5%

@

UCPU1H

SUSACK
SYS_RESE T
SYS_PWROK
PCH_PW ROK
APWR OK
PLTRST

RSMRST
SUSW ARN/SUSPW RDN ACK/GPIO30

PW RB TN SLP_ S4
ACPRESENT/GPI O31 SLP_ S3
BATLOW /GP IO72 SLP_ A
SLP_ S0 SLP_S US
SLP_ WLAN/G PIO29 SLP_ LAN

UCPU1I

HASWELL_MCP_E

SYSTEM POWERMANAGEMENT

8 OF 19

PCH_RSMRST#

PCH_DPW ROK_R RC316 1

short@

HASWELL_MCP_E

PANEL_BKEN_CPU PD 100K on Page20

<18,4> BKL_PWM_CPU

<30> E NBKL
<19> ENVDD _CPU

<30> AOAC_PME#

RC120 1 2 100K_0402_5% ENVDD _CPU

B B

short@ RC114 1 2 0_0402_5% BKL_PW M_CPU_R B8
short@ RC115 1

ENVDD_CPU RC116 1

short@

AOAC_PME# 1 2 AOAC_PME#_R AD4

<9> EC_SMI#
<7> PCI_PIRQB#
<9> PCI_PIRQC#

RC305 0_0402_5%

PAD T146
PAD T154

2 0_0402_5% ENBKL_CPU
2 0_0402_5% ENVDD_CPU_R

PCI_PIRQB# P4
PCI_PIRQC# N4

@ P CH_GPIO 80 N2

TS_RST#

@

PCH_MC_WAKE#
PCH_MIC_DET

@

PCH_HP_DET

EC_SMI# U6

EDP_BKLCTL

A9

EDP_BKLEN

C6

EDP_VDDEN

PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/G PIO79
PIRQD/G PIO80

PME

U7

GPIO55

L1

GPIO52

L3

GPIO54

R5

GPIO51

L4

GPIO53

eDPSIDEBAND

GP IO

9 OF 19

PM_S LP_S0#_R

PM_S LP_S3#

SUS_STA T/GPIO61

CH751H-40PT_SOD323-2

1

CH751H-40PT_SOD323-2

DC4 2 1

DDPB_CT RLCLK

DDPB_CT RLDATA

DDPC_CT RLCLK

DDPC_CT RLDATA

DDPB_AUXN

DISPLAY

DDPC_AUXN
DDPB_AUXP
DDPC_AUXP

DDPC_HPD

DPWROK

WAKE

PAD PAD

B9 PCH_DDPB _CLK
C9 P CH_DDPB _DAT
D9 @ 1RC107
D11 1

C5
B6
B5
A6

C8
A8

D6

AW 7 D SWODVRE N
AV5 PCH_DPW ROK_R
AJ5 WAKE#

V5 PM_CLKRUN #
AG4 SU S_ST AT#
AE6
AP5

AJ6
AT4
AL5
AP4
AJ7

T142 T143

@ @

RC102 2.2K_0402_5%

DDI1_AUX_DN

DDI1_AUX_DP

DSW VRMEN

CLKRUN/GPIO32
SUSCLK/GPIO 62

SLP_ S5/G PIO63

2 DC3 PCH_P WROK

20_0201_5%

DDPB_HPD

EDP_HPD

RC371 1
short@

T147

PAD
@

PM_S LP_S3#

T145PAD @CH751H-40PT_SOD323-2

1

short@ RC286

Non Deep S3RC286-->@

Deep S3 RC286-->SMT

PCH_DPW ROK <30>

2 2.2K_0402_5%
2

2 0_0201_5%

SPOK <47>

PCH_DDPB_CL K <20>

PCH_DDPB_DA T <20>

T144

2 0_0402_5%

WAKE# <41>

PM_C LKRUN# <30>

PM_S LP_S5# <30>

PAD

@

<7> USB_CR_PWREN

+3VS

<SI>Displayport Port C Enable pin RC102 pull high +3VS

DDI1_AUX_DN <29>

DDI1_AUX_DP <29>

PCH_DDPB_HP D <20>

DDI1_HPD <29>

EDP_HPD <18>

<DP TO CRT HPD>

<HDMI>

<DP TO CRT HPD>
<eDP HPD>

DSWODVREN - On Die DSW VR Enable
H：Enable

*

L：Disable

AOAC_PME#

WAKE# RC98 1 2 1K_0402_5%

PM_S LP_S4# <30>

PM_S LP_S3# <30>

PM_S LP_SUS# <30>

Deep S3:DSW power choose onpage12

PM_B ATLOW#
USB_CR_PWREN

PCH_SLP_WLAN# 4

<HDMI>

ACIN_R RC101 1 2 10K_0402_5%

@

RPH15
1 8
2

7

3

6
5

10K_0804_8P4R_5%

1 8.2K_0402_5%PM_C LKRUN# RC110 2

+RTCVCC

1 330K_0402_5%DSW ODVREN RC254 2

1 330K_0402_5%DSW ODVREN RC255 2

+3V_DSW _P

1 10K_0402_5%PCH_RSMRST# RC106 2

+3V_DSW _P

+3VS

+3VS

@

1

2

RC300

UC9

O

Issued Date

+3VS

5

3

0_0402_5%

1

IN1

IN2

G P

SN74AHC1G08DCKR _SC70-5

PLT_RST #_PCH

2

2011/06/29 2011/06/29

<CPU>

Compal Secret Data

Deciphered Date

Title

PM,GPIO,DDI

ize Document Number

Custom

LA-B972P

Sheet

Rev

0.1

8 of 54Date: T hursday, March 20, 2014

1 10K_0402_5% PCH_MC_WAKE#RC125 2

RPH27 4

3
2
1

5
6
7
8

10K_0804_8P4R_5%

GPU_CLKREQ#
PCH_GPIO80
PCH_HP_DET
DEVSLP1

GPU_CLKREQ# <32,7>

DEVSLP1 <22,9>

<21,23,28,30,32> PLT_RST#

PLT_RST # 4

<PV>PRH18 change to RPH27.

A A

5 4 3 2 1

PD on KBCpage

Security Classification

TH IS S H EE T O F EN GI NE ER IN G DR AW ING I S T HE P R OPR IE T A RY P R O PE R TY OF CO MPA L E LE CT R ON IC S, I NC. AN D C ONT AI NS CONFIDENTIASL
AN D T RA D E SE CR E T INF O RM AT IO N. TH IS S HE E T MA Y NOT BE TR AN S FER ED F R OM T H E CU STO D Y OFT H E CO MP ET EN T D IVI SION OF R& D
DE PA RT ME NT EXC EPT AS AU T HO R IZ E D BY C O MP AL ELEC TR ONICS, IN C. N EITH ER T HI S SH EE T N O R TH E INF O RM AT IO N IT CO NT A IN S
MA Y BE U S ED BY OR D IS CL OS ED TO AN Y THIR D PAR T Y WI T HO UT PR IO R W R IT T EN CON S EN T OF COM PAL E LE CT RON IC S, INC.

5 4 3 2 1

GPIO

HASWELL_MCP_E

10 OF19

CPU/
MISC

LPIO

THRMTRIP

RCIN/GPIO82

SERIRQ

OPI_COMP2

RSVD
RSVD

GSPI0_CS/GPIO83

GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86

GSPI1_CS/GPIO87

GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90

UART0_RXD/GPIO91

UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3

I2C0_SDA/GPIO4

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69

short@RC129

D60 H_THERMTRIP#_C 1 2 H_THEMTRIP#

V4 EC_KBRST#

SERIRQ

T4
AW15PCH_OPIRCOMP
AF20
AB21

R6

NGFF_WIFI_3.3_PWREN

WWAN_PWREN

L6

N6

PCH_GPIO85RC1081@ 2

MSATA_SSD_PWREN

L8

R7

L5

N7 TOUCH_PANEL_PWREN

K2 SATA1_PWREN
J1 PCH_LAN_RST#
K3 PCH_LAN_WAKE#

J2 PCH_CR_RST#

G1PCH_CR_WAKE#
K4
G2
J3

J4 ODD_DA#

I2C_0_SDA

F2

I2C_0_SCL

F3

I2C_1_SDA

G4

I2C_1_SCL

F1
E3
F4
D3
E4

ODD_PWR

C3
E2

0_0402_5%

2 1

RC131

49.9_0402_1%

ODD_DA# <22>

ODD_PWR <22>

EC_KBRST#<30,7>
SERIRQ <28,30>

0_0201_5%

UCPU1J

PCH_AUDIO_PWREN P1

<23> LAN_PWR_EN
<30> EC_LID_OUT#

D D

C C

+3V_PCH

<30> EC_FB_CLAMP_TGL_REQ#

<34> DGPU_GC6_EN

<23,30> EC_PME#

<30,32>DGPU_HOLD_RST#

<10,21>WL_OFF#

<30> NMI_DBG#_CPU

+3VS

RC1221@
RC1231@

EC_PME#
PAD
PAD

RC1191@

PAD T150

<6> MPHY_PWREN

<19> TS_GPIO_CPU
<28> ACCEL_INT#

<30> EC_SCI#

<7> PCH_GPIO33

<22,8> DEVSLP1

<25> HDA_SPKR

LAN_PWR_EN

EC_LID_OUT#
2 0_0201_5% PCH_GPIO16
2 0_0201_5% PCH_GPIO17

UART_WAKE#

T148
T149

BT_ON

2 PCH_GPIO58

0_0201_5% WL_OFF#

NMI_DBG#_CPU
LPDDR3_ID1
LPDDR3_ID2
LPDDR3_ID3

MPHY_PWREN
USB32_P0_PWREN_R# AT3

USB_CAM_PWREN
TS_GPIO_CPU
ACCEL_INT#

PCH_GPIO9
EC_SCI#
PCH_GPIO33

PAD T158

DEVSLP1
HDA_SPKR

Dummy

BMBUSY/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

GPIO15

Y1

GPIO16

T3

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN/GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

<SI> PRH14.4 change from +3V_PCH to +3VS for S3 leakage

3
2
1

3
2
1

3 6
2
1

RPH13
4
3
2
1

10K_0804_8P4R_5%

3
2
1

3

2

1

+3V_DSW_P

5
6
7
8

10K_0804_8P4R_5%

5
6
7
8

10K_0804_8P4R_5%
5
7

8

10K_0804_8P4R_5%

<PV>PRH14 change to RPH23.

5
6 CR_CLKREQ#
7 SERIRQ
8 SATA_LED#

5
6
7
8

10K_0804_8P4R_5%
5

6
7
8

10K_0804_8P4R_5%

ODD_DA#
EC_LID_OUT#
UART_WAKE#
BT_ON

USB_OC2#
ACCEL_INT#

PCH_GPIO58

USB_OC0#
USB32_P0_PWREN_R#
PCH_GPIO9
NMI_DBG#_CPU

PRH15 change to RPH24.
PRH16 change toRPH25.

PCH_GPIO17
EC_SMI#
PCIECLKREQ4#
PCI_PIRQC#

SATA1_PWREN
PCH_AUDIO_PWREN
USB_CAM_PWREN
LAN_PWR_EN

CR_CLKREQ#<23,7>
SATA_LED#<27,6>

<PV>PRH10 change to RPH10.

+3V_PCH +3VS +3VS

12

USB_OC2# <10>

LPDDR3_ID1
LPDDR3_ID2
LPDDR3_ID3

USB_OC0# <10,24>

EC_SMI# <8>
PCIECLKREQ4# <7>
PCI_PIRQC#<8>

RC135
10K_0402_5%

@

12

@RC263
10K_0402_5%

PRH17 change toRPH26.

12

RC261 RC262

10K_0402_5%10K_0402_5%

12

@RC264 @RC265
10K_0402_5%10K_0402_5%

+3V_PCH

RPH14 4

12

@ @

12

5
6

3

7

2

8

1

10K_0804_8P4R_5%

SUSWARN#_R

SML1ALERT#

SMBALERT#

EC_SCI#

SUSWARN#_R<8>
SML1ALERT# <7>
SMBALERT# <7>

RPH23 4

RPH24 4

RPH25 4

+3VS

B B

RPH26 4

RPH10 4

+1.05VS_VCCST

12

RC242
1K_0402_5%

DG V0.9 PCH_OPIRCOMP
Width=12mil,spacing=12mil

L

Max length=500mil

DGPU_PWR_EN <30,35,53>

Boot BIOS Strap

PCH_GPIO86 Boot BIOSLocation

SPI

0

*

9/12 reserve DGPU_PWR_EN on GPIO85

NGFF_WIFI_3.3_PWREN 4 5 RPH21
WWAN_PWREN 3 6
MSATA_SSD_PWREN 2 7
TOUCH_PANEL_PWREN 1 8

10K_0804_8P4R_5%

<PV>PRH12 change to RPH21.

<PV>PRH19 change to RPH28.

PCH_CR_WAKE#
PCH_CR_RST#
PCH_LAN_WAKE#
PCH_LAN_RST#

I2C_1_SDA
I2C_0_SCL
I2C_0_SDA
I2C_1_SCL

10K_0804_8P4R_5%

4

5 RPH28
3 6
2

7
1

8

@

8

1 RPH18
7

2

3

6

4

5

1K_0804_8P4R_5%

@

+3VS

DSW power choose onpage12

*

GPIO27

A A

RC277 1 2 10K_0402_5% EC_PME#

PCH_GPIO27 (Have internal Pull-High)
High: VCCVRM VR Enable
Low: VCCVRM VR Disable

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS T HE PRO PRIETAR Y PR OPERTY OF COMPAL ELECT RONICS, I NC. AND CO NTA INS CONFIDENTIASL
AND TRADE SECRET INFORMAT ION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUS TOD Y OF TH E COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER TH IS SHEET NOR T HE INFORMATI ON IT CONTAINS

5 4 3 2 1

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WIT HOUT PRIOR WRITTEN CONSENT OF C OMPAL ELECTRONIC S, INC.

2011/06/29 2011/06/29

Compal Secret Data

DecipheredDate

Title

GPIO,UART,I2C

ize DocumentNumber

Custom

LA-B972P

Sheet

Rev

9 of 54Date: Thursday, March 20,2014

0.1

5

USB2N4

USB2N5

USB2N6

USB2N7

USB3RN0

USB3RN1

USB3TN1

USBRBIAS

4

3 2

1

HASWELL_MCP_ E

PC Ie

11 OF19

AN8

USB2N0

AM8

USB2P0

AR7

USB2N1

AT7

USB2P1

AR8

USB2N2

AP8

USB2P2

AR10

USB2N3

AT10

USB2P3

AM15
AL15

USB2P4

AM13
AN13

USB2P5

AP11
AN11

USB2P6

AR13
AP13

USB2P7

G20
H20

USB3RP0

USB

USBRBIAS

OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43

USB3TN0
USB3TP0

USB3RP1

USB3TP1

TP13
TP14

C33
B34

E18
F18

B33
A33

USBRBIAS

AJ10
AJ11

AN10
AM10

AL3 USB_OC0#
AT1 USB_OC1#
AH2 USB_OC2#
AV3 USB1_PWR_EN

<21,9> WL_OFF#

USB20_N0 <24>
USB20_P0 <24>

USB20_N1 <24>
USB20_P1 <24>

USB20_N2 <24>
USB20_P2 <24>

USB20_N3 <21>
USB20_P3 <21>

USB20_N4 <19>
USB20_P4 <19>

USB20_N5 <19>
USB20_P5 <19>

USB3_RX0_N <24>

USB3_RX0_P <24>

USB3_TX0_N <24>
USB3_TX0_P<24>

USB2.0/USB3.0

USB2.0

USB2.0

WLAN/BT

Camera

Touch screen

USB2.0/USB3.0

L

RC148 1 2 22.6_0402_1%

USB_OC0# <24,9>
USB_OC1# <24>
USB_OC2# <9>

USB_OC1# 3 6
WL_OFF# 2 7

USB1_PWR_EN 1 8

DG V0.9 USBRBIAS
Trace width=50ohm and spacing=15mil

Max length=500mil

+3V_PCH

RPH17

4 5

10K_0804_8P4R_5%

PERN5_L0
PERP5_L0

PETN5_L0
PETP5_L0

F8

PERN5_L1

E8

PERP5_L1

PETN5_L1
PETP5_L1

PERN5_L2
PERP5_L2

PETN5_L2
PETP5_L2

PERN5_L3
PERP5_L3

PETN5_L3
PETP5_L3

PERN3
PERP3

PETN3
PETP3

F13

G13

PERN4
PERP4

B29
A29

PETN4
PETP4

G17

F17

PERN1/USB3RN
2

C30
C31

PERP1/USB3RP2
PETN1/USB3TN

2
PETP1/USB3TP2

PERN2/USB3RN
3
PERP2/USB3RP3

PETN2/USB3TN
3
PETP2/USB3TP3

B27

TP3
TP4

PCIE_RCOMP
PCIE_IREF

UCPU1K

<DB>change AC cap to 0.22uF review by Nvidia

D D

C C

10/100/1G LAN

PCI-E Cardreader

B B

<32> PEG_GTX_C_HRX_N7
<32> PEG_GTX_C_HRX_P7

<32> PEG_HTX_C_GRX_N7
<32> PEG_HTX_C_GRX_P7

<32> PEG_GTX_C_HRX_N8
<32> PEG_GTX_C_HRX_P8

<32> PEG_HTX_C_GRX_N8
<32> PEG_HTX_C_GRX_P8

<32> PEG_GTX_C_HRX_N9
<32> PEG_GTX_C_HRX_P9

<32> PEG_HTX_C_GRX_N9
<32> PEG_HTX_C_GRX_P9

<32> PEG_GTX_C_HRX_N10
<32> PEG_GTX_C_HRX_P10

<32> PEG_HTX_C_GRX_N10
<32> PEG_HTX_C_GRX_P10

<23> PCIE_PRX_DTX_N3
<23> PCIE_PRX_DTX_P3

<23> PCIE_PTX_C_DRX_N3
<23> PCIE_PTX_C_DRX_P3

<23> PCIE_PTX_C_DRX_N2

<23> PCIE_PTX_C_DRX_P2

<23> PCIE_PRX_DTX_N2
<23> PCIE_PRX_DTX_P2

<Page12>

0.22U_0402_6.3V6K DIS@ 1

0.22U_0402_6.3V6K DIS@ 1

0.22U_0402_6.3V6K DIS@ 1

0.22U_0402_6.3V6K DIS@ 1

0.22U_0402_6.3V6K DIS@ 1

0.22U_0402_6.3V6K DIS@ 1

0.22U_0402_6.3V6K DIS@ 1

0.22U_0402_6.3V6K DIS@ 1

CC12 2 1 PCIE_PTX_DRX_N3 C29
CC13 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_P3 B30

CC16 2
CC17 2

+1.05VS_VCCUSB3PLL

DG V0.9 PCIE_RCOMP

L

Width=12mil,spacing=12mil

0.1U_0402_16V7K

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

3K_0402_1% E13

PEG_GTX_C_HRX_N7 F10
PEG_GTX_C_HRX_P7 E10

2 CC90
2 CC91

2 CC89
2 CC92

2 CC93
2 CC94

2 CC95
2 CC96

RC151 E15

1 2 PCH_PCIE_RCOMP A27

PEG_HTX_GRX_NC723
PEG_HTX_GRX_PC722

PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_P8

PEG_HTX_GRX_NB823
PEG_HTX_GRX_PA823

PEG_GTX_C_HRX_N9 H10
PEG_GTX_C_HRX_P9 G10

PEG_HTX_GRX_N9 B21
PEG_HTX_GRX_P9 C21

PEG_GTX_C_HRX_N10 E6
PEG_GTX_C_HRX_P10 F6

PEG_HTX_GRX_N10 B22
PEG_HTX_GRX_P10 A21

PCIE_PRX_DTX_N3 G11
PCIE_PRX_DTX_P3 F11

PCIE_PRX_DTX_N2 F15
PCIE_PRX_DTX_P2 G15

PCIE_PTX_DRX_N2 B31
PCIE_PTX_DRX_P2 A31

Max length=500mil

<PV>PRH11 change to RPH17.

A A

Security Classification

Issued Date

TH IS SH E ET OF ENG I NEE RI N G DR A W IN G IS TH E P ROP R IE T AR Y P ROP ERT Y O F COM PAL E L EC T RON I CS , IN C. A N D C ON TAI NS CONFIDENTISSAiL
AN D T RAD E S ECR ET IN FO RMATI ON . TH IS S H EE T MAY N O T BE T R AN S FER ED FRO M TH E CUS T OD Y OF TH E CO M PE T ENT D IVISI ON OF R& D
DE P ART MEN T EXC EPT AS A U THO R IZE D BY CO MPA L E LEC T RON ICS , IN C. NE IT HE R T HIS S H EE T N O R T H E IN F ORM ATI O N IT C ONT AI NS

5

4

MA Y BE US ED BY OR D ISC LO SE D TO AN Y T HI RD PA RT Y W ITH OUT P R IO R W RI T TEN C ONS EN T OF CO MP A L EL E CT R O NI C S, IN C.

2011/06/29 2011/06/29

3 2

Compal Secret Data

Deciphered Date

Title

PCIE,USB

ze Document Number

B

LA-B972P

Sheet of

10 54Date: Thursday, March 20, 2014

1

Rev

0.1

5

4

3 2

1

+VCC_CORE@10000mA

VCC

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31

G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57

+VCC_CORE

G33

RC288
10K_0402_5%

HASWELL_MCP_E

HSW ULT POWE R

12 OF19

VR12.6PG_MCP

+1.35V_VDDQ

+VCC_CORE

D D

<PWR VR12.6>

SVID ALERT

<50> VR_SVID_ALRT#

SVID DATA

RC1551

+1.05VS_VCCST

12

RC156
110_0402_1%

43_0402_1%

+1.05VS_VCCST

12

RC154
75_0402_5%

2

DG V0.5 H_CPU_SVIDALRT#

L RC154 close to CPU<300mil

Max length=1000~2000mil

H_CPU_SVIDALRT#

VCC_SENSE

<PWR VR12.6>

<VR IV and CPU>

<EDP_COMP power rail>

<50> VR12.5_VR_ON

PH on power page

<50> VCCSENSE

+VCCIO_OUT
+VCCIOA_OUT

<50> VR_SVID_CLK

<4,6> +1.05VS_PG

<PWR VR12.6>

C C

B B

<CPU>

<50> VR_SVID_DAT

L

+1.05VS

DG V0.5 VIDSOUT
RC156 close to CPU<500mil
Max length=1000~2000mil

VR_SVID_DAT

RC294 1 2 0_0402_5%

+1.05VS_VCCST

150_0402_5

%

12 1 2

RC166

CPU_PWR_DEBUG

7

10K_0402_5

%

@

RC16

@

+VCCIO_OUT

+1.05VS +1.05VS_VCCST

short@

RC223

1 2

0_0805_5%

1

1

CC7

CC72

2

2

1U_0402_6.3V6

K

1

22U_0805_6.3V6

M

<50> VGATE

@

+1.05VS_VCCST

+VCC_CORE

2500mA

VCCSENSE

H_CPU_SVIDALRT# L62
VR_SVID_CLK

VR_SVID_DAT

VR12.6PG_MCP

CPU_PWR_DEBUG H59

600mA

UC8

NC1VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

L59

RSVD

J58

RSVD

AH26

VDDQ

AJ31

VDDQ

AJ33

VDDQ

AJ37

VDDQ

AN33

VDDQ

AP43

VDDQ

AR48

VDDQ

AY35

VDDQ

AY40

VDDQ

AY44

VDDQ

AY50

VDDQ

F59
N58

RSVD

AC58

RSVD

E63

VCC_SENSE

AB23

A59

VCCIO_OUT

E20

VCCIOA_OUT

AD23

RSVD

AA23

RSVD

AE59

RSVD

N63

VIDSCLK

L63

VIDSOUT

B59

VCCST_PWRGD

F60

VR_EN

C59

VR_READY

D63

VSS

PWR_DEBUG

P62

VSS

P60

RSVD_TP

P61

RSVD_TP

N59

RSVD_TP

N61

RSVD_TP

T59

VSS

AD60
AD59
AA59
AE60
AC59
AG58

U59

VSS

V59

AC22

VCCST

AE22

VCCST

AE23
AB57

VCC

AD57

VCC

AG57

VCC

C24

VCC

C28

VCC

C32

+3V_PCH

5

4

Y

UCPU1L

VCCIN

RSVD

VIDALERT

VSS
VSS
VSS
VSS
VSS

VSS

VSS

VCCST

VCC

+1.05VS_VCCST

12

+1.35V_VDDQ+1.35V_VDDQ

10U_0603_6.3V6

CC20

2.2U_0402_6.3V6

M
1

2

A A

Security Classification

Issued Date

THI S SH EET OF E NGIN EERING DR AWING IS T HE PROPRIET ARY PROP ERT Y OF COMPAL ELECTRO NICS, INC. AND C ONT AINS CONFIDENTIAL
AND TR ADE SECRET INFO RMAT ION. T HIS SHEET MAY NOT BE TRANS FERE D FROM THE CU STO DY OF T HE COMPETENT DIVISION OF R&D
DEPA RTMENT EXC EPT A S A UTH ORIZ ED BY COMP AL ELE CTR ONIC S, IN C. NEIT HER THIS SH EET NO R T HE I NFORMAT ION IT CONTAI NS

5

4

MAY BE USED BY OR D ISCLOSED TO ANY T HIR D PARTY W ITH OUT PRIOR W RITT EN C ONSE NT OF COMPAL ELE CTR ONIC S, INC .

3 2

CC21

2.2U_0402_6.3V6

M

1

2

2011/06/29 2011/06/29

2.2U_0402_6.3V6

M

1

@

2

Compal SecretData

CC22

1

2

Deciphered Date

CC23

2.2U_0402_6.3V6

M

CC24

330U_2.5V_M 330U_2.5V_M

CC25

1

+

2

@

1

+

2

M

10U_0603_6.3V6

M

@

1

1

CC26

2

1

CC27

2

2

Compal Electronics, Inc.

Title

Power

Size DocumentNumber

Custom

Date:

10U_0603_6.3V6

M

CC28

LA-B972P

10U_0603_6.3V6

M

@

1

2

10U_0603_6.3V6

M

1

CC29

2

10U_0603_6.3V6

M

@

1

CC30

CC31

2

Rev

Sheet 11 of 54Thursday, March 20, 2014

1

0.1

5

+1.05VS_VCCUSB3PLL

RC170

+1.05VS_MODPHY

2.2UH_LQM2MPN2R2NG0L_30%

D D

+1.05VS_MODPHY

C C

+1.05VS

2.2UH_LQM2MPN2R2NG0L_30%

B B

+1.05VS

2.2UH_LQM2MPN2R2NG0L_30%

A A

1 2

+1.05VS_VCCSATA3PLL

RC171

2.2UH_LQM2MPN2R2NG0L_30%

1 2

<DB>Aduio code powerrail

RC176

2

1

1

2

+1.05VS

1 2

1 RC280 2

0_0603_5%

RC179

1

2

5

CC57

CC63

1

CC35

2

1

CC42

2

+1.05VS_APPLOPI

1

CC58

2

22U_0805_6.3V6M

1U_0402_6.3V6K

+1.05VS_AXCKDCB

1

CC64

2

47U_0805_6.3V6M

+1.05VS_VCCUSB3PLL

41mA

1

CC36

2

47U_0805_6.3V6M

1U_0402_6.3V6K

+1.05VS_VCCSATA3PLL

42mA

1

CC43

2

47U_0805_6.3V6M

1U_0402_6.3V6K

57mA

+V1.05S_SSCF100

62mA

1

CC61

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+1.05VS

2.2UH_LQM2MPN2R2NG0L_30%

+1.05VS_MODPHY

Use+1.05V

RC172 1 2 0_0402_5%

+1.5VS

+1.05VS

RC181

1

short@

2

1

2

+1.05V

+3V_PCH

RC281

1 2

short@

0_0603_5%

+1.05VS_AXCK_LCPLL

+1.05VS_AXCK_LCPLL

1

CC68

2

47U_0805_6.3V6M

short@

RC1681 2

0_0805_5%

+1.05VS

10U_0603_6.3V6M
1U_0402_6.3V6K

CC5

5

1

CC62

2

1U_0402_6.3V6K

31mA

CC69

1U_0402_6.3V6K

4

1.838A

1

CC33

2

1

CC41

2
RC173
0_0402_5% 1 @

1

2

1

+3VS

2

22U_0805_6.3V6M

2
2

CC51

1U_0402_6.3V6K

CC5

+V1.05S_SSCFF

124mA

1U_0402_6.3V6K

9

Deep S3 and Non Deep S3

4

1U_0402_6.3V6K

1

CC45

1

CC46

1

2

22U_0805_6.3V6M

1

CC34

2

2

+3VALW
+3V_PCH

+1.05VS_VCCHSIO

1U_0402_6.3V6K

+1.05VS_APPLOPI

+1.05V_DCPSUS

+VCCSUSHDA

+1.05VS_AXCKDCB
+1.05VS_AXCK_LCPLL

+V1.05S_SSCF100
+V1.05S_SSCFF

+3V_PCH

+1.05VS_VCCUSB3PLL
+1.05VS_VCCSATA3PLL B11

+3V_DSW_P

short@

RC285 1 2 0_0402_5%

RC182 1

@

3 2

65mA

+3V_DSW_PRTCSUS

UCPU1M

K9

VCCHSIO

L10

VCCHSIO

M9

VCCHSIO

N8

VCCIO

P9

VCCIO

B18

VCCUSB3PLL

VCCSAT A3PLL

Y20

VCCAPLL

AA21

VCCAPLL

W21

VCCAPLL

J13

DCPSUS3

AH14

VCCSUSHDA

AH13

DCPSUS2

AC9

VCCSUS3_3

AA9

VCCSUS3_3

AH10

VCCDSW 3_3

V8

VCC3_3

W9

VCC3_3

J18

VCC1P05

K19

VCC1P05

A20

VCCACLKPLL

J17

VCCCLK

R21

VCCCLK

T21

VCCCLK

K18

VCCCLK

M20

VCCCLK

V21

VCCCLK

AE20

VCCSUS3_3

AE21

VCCSUS3_3

2 0_0402_5% +3V_DSW_P

1

CC70

2

1U_0402_6.3V6K

HASW ELL_MCP_E

mPHY

OPI

USB3

AXALIA /HDA

VRM/US B2/AZA LIA

GPIO/LCC

ICC

LPT LP POW ER

+3V_DSW_P

Deep S3RC285-->SMT
Non Deep S3 RC182-->SMT

13 OF 19

RTC

SPI

CORE

THERMAL SENSOR

SDIO/PL SS

SUS OSCILL ATOR

USB2

AH11

VCCSUS3

AG10

VCCRTC

AE7 CC40 1 2 0.1U_0402_16V7K

DCPRTC

Y8

VCCSPI

AG14

VCCASW

AG13

VCCASW

J11

VCC1P05

H11

VCC1P05

H15

VCC1P05

AE8

VCC1P05

AF22

VCC1P05

AG19

DCPSUSBYP

AG20

DCPSUSBYP

AE9

VCCASW

AF9

VCCASW

AG8

VCCASW

AD10

DCPSUS1

AD8

DCPSUS1

J15

VCCTS1_5

K14

VCC3_3

K16

VCC3_3

CC76

U8

VCCSDIO

T9

VCCSDIO

+1.05V_AOSCSUS

AB8

DCPSUS4

AC20

VCCAPLL

AG16

VCCIO

AG17

VCCIO

Total1.05VS=1838+2274=4111mA
Total 1.5VS=3mA
Total 1.8VS=7mA
Total3VS=0mA

Total3VALW=200+62=262mA
Total3V_PCH=99mA

+RTCVCC

18mA

+1.05VS

+1.05VS_VCCASW

+1.05V_DCPSUS

+1.5VS
+3VS

2

1

0.1U_0402_16V7K

1

2

RC174 CC52

5.11_0402_1% 1U_0402_6.3V6K

2

1 1 2

+3V_1V8_SDIO

1

CC65

2

1U_0402_6.3V6K

Total1.05V=540+109=649mA

Security Classification

Issued Date

THI S SHE ET O F ENG IN EER ING DR AW IN G IS T HE PR OP RIE TA RY P ROPER TY O F CO MPA L EL ECT RO NI CS, INC. AN D CO NTA INS CONFIDENTIASSL
AND T RADE SECRE T INF ORMAT ION . THI S SHEE T MAY NOT BE T RANSF ERED FRO M THE CUST OD Y OF T HE COMPETEN T DIVIS ION OF R&D
DEPAR TMENT EX CEPT AS A UT HO RIZ ED BY C OMPAL E LEC TR ON ICS , INC. NEIT HER THIS SH EET N OR TH E INFO RM ATION IT CONTAIN S
MAY BE USE D BY OR DI SCLOSE D TO A NY TH IRD PA RT Y WITHOUT PRIO R WR IT TEN CON SE NT OF CO MPAL ELE CT RO NIC S, INC.

3 2

2011/06/29 2011/06/29

Compal Secret Data

DecipheredDate

1

CC32

2

1

2

CC44@

0.1U_0402_16V7K

1

CC60

2

+1.05VS

+1.05V_AOSCSUS

short@

RC1692 1 0_0402_5%

1U_0402_6.3V6K

0.1U_0402_16V7K
CC37

@

+3V_PCH

1

CC39

2

1.6A

0.658A

1

CC5

CC53

2

1U_0402_6.3V6K

4

RC178 short@

1 2 0_0603_5%

1U_0402_6.3V6K

@

1U_0402_6.3V6K

Title

ize Document Number

Custom

+3V_PCH

+RTCVCC

1U_0402_6.3V6K

SPI ROM powerrail

1

1

CC48

CC49

2 2

1U_0402_6.3V6K

1U_0402_6.3V6K

short@

2

0_0805_5%

1

1

CC67

100U_1206_6.3V6K

1

2

22U_0805_6.3V6M

CC66

RC1751

1

2 2

Power

LA-B972P

1

+1.05VS

1

CC50

2

10U_0603_6.3V6M

+1.05VS

+3VS

@

RC180

2

2.2UH_LQM2MPN2R2NG0L_30%

@

1

+1.05V

Sheet 12 of 54Date: Thursday, March 20, 2014

Rev

0.1

5 4 3 2 1

HASWELL_MCP_E

UCPU1N

A11

VSS

A14

VSS

A18

VSS

A24

VSS

A28

VSS

A32

VSS

A36

D D

C C

B B

A40
A44
A48
A52
A56

AA1
AA58
AB10
AB20
AB22

AB7

AC61
AD21

AD3

AD63

AE10

AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18

AG1

AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57

AJ13
AJ14
AJ23
AJ25
AJ27
AJ29

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

14 OF19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AJ35
AJ39
AJ41

AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17

AP20

AP23
AP26
AP29

AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49

AR5

AR52

AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63

AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

UCPU1O

HASWELL_MCP_ E

15 OF19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AV59AP22

AV8
AW16
AW24
AW33
AW35
AW37

AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33

AY4
AY51
AY53
AY57
AY59

AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31

D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49

D50
D51
D53
D54
D55
D57
D59
D62

E11
E17

F20
F26
F30
F34
F38
F42
F46
F50
F54
F58

F61
G18
G22

H13

HASWELL_MCP_ E

UCPU1P

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

D5

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

D8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

G3

VSS

G5

VSS

G6

VSS

G8

VSS

VSS

16 OF19

VSS_SENSE

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS

VSS

H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63

AH46

V23

E62

AH16

H17

V58

VSSSENSE <50>

<PWR VR12.6>

A A

Security Classification

IssuedDate

TH IS SH EET OF EN G IN E ERI NG DR AW I NG IS T H E PR O PRI ETA RY PROP E RT Y OF CO M PA L E LE C TRO N ICS , INC . AND C ONT AI NS CONFIDENTISSAiL
AN D T RAD E S ECR ET IN FO RMATI ON . TH IS S H EE T MAY N O T BE T R ANS FER E D FRO M TH E CUS T OD Y OF TH E CO M PE T ENT DI VISIO N OF R&D
DE P ART MEN T EXC EPT AS A U THO R IZE D BY CO MPA L E LEC T RON ICS , IN C. NE IT HE R T HIS S H EE T N O R T H E INF ORM ATIO N IT C ONT AI NS

5 4 3 2

MA Y BE USED BY OR D IS CLOSE D TO ANY TH IR D P AR T Y WIT H OU T PR I OR W R ITT E N CO N SE N T OF C O MP A L EL ECT R ONI C S, INC.

2010/05/27 2011/05/11

Compal Secret Data

Deciphered Date

Title

ze

Date:

DocumentNumber

Compal Electronics, Inc.

GND/VSSSEN

LA-B972P

Thursday, March 20, 2014

Sheet113 of 54

Rev

0.1

5 4 3 2 1

UCPU1Q

DC_TEST_AY2_AW2
DC_TEST_AY3_AW3

DC_TEST_AY61_AW61 AY61
DC_TEST_AY61_AW62AY62

TP_DC_TEST_A3_B3

D D

C C

DC_TEST_A61_B61
DC_TEST_B62_B63 B62

DC_TEST_C1_C2 C1

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60
DAISY_CHAIN_NCTF_AY61
DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61
DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63
DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

UCPU1R

AT2

RSVD

AU44

RSVD

AV44

RSVD

D15

RSVD

F22

RSVD

H22

RSVD

J21

RSVD

HASWELL_MCP_ E

17 OF19

HASWELL_MCP_ E

18 OF19

UCPU1S

DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63

RSVD
RSVD

RSVD
RSVD

RSVD
RSVD

RSVD
RSVD
RSVD

HASWELL_MCP_ E

A3 TP_DC_TEST_A3_B3
A4

A60
A61 DC_TEST_A61_B61
A62

AV1
AW1
AW2 DC_TEST_AY2_AW2
AW3DC_TEST_AY3_AW3

AW61DC_TEST_AY61_AW61
AW62DC_TEST_AY61_AW62

AW63

N23
R23

T23

U10

AL1
AM11

AP7
AU10
AU15
AW14

TP2

AY14

TP1

CFG4

CFG4

12

RC185

1K_0402_1%

Display Port Presence Strap

1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is

*

connected to the Embedded Display Port

PAD @ T59
PAD @ T60
PAD @ T61
PAD @ T63

PAD @ T64
PAD @ T65
PAD @ T66
PAD @ T67
PAD @ T68
PAD @ T69

B B

A A

PAD @ T70
PAD @ T71
PAD @ T72
PAD @ T73
PAD @ T74

PAD @ T75
PAD @ T76
PAD @ T77
PAD @ T78

RC188

RC191

2

1

CFG0
CFG1

CFG2
CFG3

CFG4
CFG5

CFG6
CFG7

CFG8
CFG9

CFG10
CFG11

CFG12
CFG13

CFG14
CFG15

1 CFG_RCOMP V63

49.9_0402_1%

2 TD_IREF

8.2K_0402_5%

AC60
AC62

AC63
AA63

AA60

Y62
Y61

Y60
V62

V61
V60

U60
T63

T62
T61

T60

CFG16 AA62
CFG18 U63

CFG17 AA61
CFG19 U62

D1
J20
H18
B12

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG16
CFG18
CFG17
CFG19

CFG_RCOMP

A5

RSVD

E1

TP9 HVM_CLK_P
TP10
TP11
TP12
TD_IREF

RESE RVED

19 OF19

EDP_SPARE

OPI_COMP1

Security Classification

IssuedDate

TH IS SH EET OF EN G IN E ERI NG DR AW I NG IS T H E PR O PRI ETA RY PROP E RT Y OF CO M PA L E LE C TRO N ICS , INC . AND C ONT AI NS CONFIDENTISSAiL
AN D T RAD E S ECR ET IN FO RMATI ON . TH IS S H EE T MAY N O T BE T R ANS FER E D FRO M TH E CUS T OD Y OF TH E CO M PE T ENT DI VISIO N OF R&D
DE P ART MEN T EXC EPT AS A U THO R IZE D BY CO MPA L E LEC T RON ICS , IN C. NE IT HE R T HIS S H EE T N O R T H E INF ORM ATIO N IT C ONT AI NS

5 4 3 2

MA Y BE USED BY OR D IS CLOSE D TO ANY TH IR D P AR T Y WIT H OU T PR I OR W R ITT E N CO N SE N T OF C O MP A L EL ECT R ONI C S, INC.

2011/06/29 2011/06/29

AV63

RSVD_TP

AU63

RSVD_TP

C63

RSVD_TP

C62

RSVD_TP

B43
A51

RSVD_TP

B51

RSVD_TP

L60

RSVD_TP

N60

RSVD

W23

RSVD

Y22 MCP_RSVD_29 RC296 2

RSVD

AY15 PROC_OPI_COMP RC186 2
AV62

RSVD

D58

RSVD

P22

VSS

N21

VSS

P20

HVM_CLK

R20

Compal Secret Data

Deciphered Date

@ 1 49.9_0402_1%

1 49.9_0402_1%

DG V0.9 PROC_OPI_COMP

L

Width=12mil,spacing=12mil
Max length=500mil

Title

ze

Date:

Compal Electronics, Inc.

RSVD/CFG

DocumentNumber

LA-B972P

Thursday, March 20, 2014

Sheet114 of 54

Rev

0.1

5 4 3 2 1

+V_VDDR_REFA_DQ

D D

C C

B B

A A

<5> DDR_A_D[0..63]
<5> DDR_A_DQS[0..7]
<5> DDR_A_DQS#[0..7]
<5> DDR_A_MA[0..15]

+1.35V_VDDQ

10U_0603_6.3V6

M

CD6

1

@

2

+1.35V_VDDQ

1U_0402_6.3V6

K

1

CD55

2

10U_0603_6.3V6

M

1

2

1U_0402_6.3V6

K

1

2

@ @

<5> DDR_CKE0_DIMMA

<5> DDR_CS1_DIMMA#

10U_0603_6.3V6

10U_0603_6.3V6

10U_0603_6.3V6

M

10U_0603_6.3V6

M

CD7

CD56

CD9

CD8

1

1

@

2

2

1U_0402_6.3V6

K

1U_0402_6.3V6

K

1

1

CD58

CD57

2

2

@

M

10U_0603_6.3V6

M

CD11

CD10

1

1

@

2

2

1U_0402_6.3V6

K

1U_0402_6.3V6

K

1

1

CD63

CD64

2

2

M

10U_0603_6.3V6

M

CD13

CD12

1

1

@

2

2

1U_0402_6.3V6

K

1U_0402_6.3V6

K

1

1

CD65

CD66

2

2

0.1U_0402_16V7

K

CD1

1

2

<5> DDR_A_BS2

<5> M_CLK_DDR0
<5> M_CLK_DDR#0

<5> DDR_A_BS0
<5> DDR_A_WE#

<5> DDR_A_CAS#

+3VS

+V_VDDR_REFA_DQ

0.1U_0402_16V7

K

1

2

+1.35V_VDDQ +1.35V_VDDQ

JDIMM1

1 2

VREF_DQ VSS1

3

VSS2 DQ4

DDR_A_D13
DDR_A_D8

DDR_A_D14
DDR_A_D10

DDR_A_D29
DDR_A_D28

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_A_D44
DDR_A_D41

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D43
DDR_A_D47

DDR_A_D51
DDR_A_D50

DDR_A_D49
DDR_A_D48

DDR_CKE0_DIMMA

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3

DDR_A_MA1
M_CLK_DDR0

M_CLK_DDR#0
DDR_A_MA10

DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D6

DDR_A_D21
DDR_A_D20

DDR_A_D17
DDR_A_D16

DDR_A_D36
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D38

DDR_A_D62
DDR_A_D58

DDR_A_D60
DDR_A_D61

CD17

5

DQ0 DQ5

7

DQ1 VSS3

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3 DQ7

19

VSS7 VSS8

21

DQ8 DQ12

23

DQ9 DQ13

25

VSS9

27

DQS#1

29

DQS1

31

VSS11 VSS12

33

DQ10 DQ14

35

DQ11 DQ15

37

VSS13 VSS14

39

DQ16 DQ20

41

DQ17 DQ21

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18 DQ23

53

DQ19 VSS19

55

VSS20 DQ28

57

DQ24 DQ29

59

DQ25 VSS21

61

VSS22

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0 CKE1

75

VDD1 VDD2

77

NC1 A15

79

BA2 A14

81

VDD3 VDD4

83

A12/BC# A11

85

A9 A7

87

VDD5 VDD6

89

A8 A6

91

A5 A4

93

VDD7 VDD8

95

A3 A2

97

A1 A0

99

VDD9 VDD10

101

CK0 CK1

103

CK0# CK1#

105

VDD11 VDD12

107

A10/AP

109

BA0

111

VDD13 VDD14

113

WE# S0#

115

CAS# ODT0

117

VDD15 VDD16

119

A13

121

S1# NC2

123

VDD17 VDD18

125

NCTEST VREF_CA

127

VSS27 VSS28

129

DQ32 DQ36

131

DQ33 DQ37

133

VSS29 VSS30

135

DQS#4

137

DQS4 VSS31

139

VSS32 DQ38

141

DQ34 DQ39

143

DQ35 VSS33

145 146

VSS34 DQ44

147

DQ40 DQ45

149

DQ41 VSS35

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43 DQ47

161

VSS39 VSS40

163

DQ48 DQ52

165

DQ49 DQ53

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50 DQ55

177

DQ51 VSS45

179

VSS46 DQ60

181

DQ56 DQ61

183

DQ57 VSS47

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59 DQ63

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1 G2

FOX_AS0A626-U4R6-7H

CONN@

DQS#0

DQS0
VSS6

DQ6

VSS10

DM1

RESET#

VSS16

DM2

VSS17

DQ22

DQS#3

DQS3

VSS24

DQ30
DQ31

VSS26

BA1

RAS#

ODT1

DM4

DQS#5

DQS5

VSS38

DQ46

VSS42

DM6

VSS43

DQ54

DQS#7

DQS7

VSS50

DQ62

VSS52

EVENT#

SDA
SCL

VTT2

4

DDR_A_D9

6

DDR_A_D12
8
10

DDR_A_DQS#1
12

DDR_A_DQS1
14
16

DDR_A_D15
18

DDR_A_D11
20
22

DDR_A_D25
24

DDR_A_D24
26

28

30

DDR3_DRAMRST#

32

34

DDR_A_D27
36

DDR_A_D26
38
40

DDR_A_D45
42

DDR_A_D40
44

46

48

50

DDR_A_D42

52

DDR_A_D46
54
56

DDR_A_D52
58

DDR_A_D53
60
62

DDR_A_DQS#6
64

DDR_A_DQS6
66
68

DDR_A_D54
70

DDR_A_D55
72

DDR_CKE1_DIMMA

74
76
78

DDR_A_MA15
80

DDR_A_MA14
82
84

DDR_A_MA11
86

DDR_A_MA7
88
90

DDR_A_MA6
92

DDR_A_MA4
94
96

DDR_A_MA2
98

DDR_A_MA0
100
102

M_CLK_DDR1
104

M_CLK_DDR#1
106
108

DDR_A_BS1
110

DDR_A_RAS#
112
114

DDR_CS0_DIMMA#
116

M_ODT0
118

M_ODT1

120
122
124

+V_VDDR_REFA_CA

126
128
130

DDR_A_D5
132

DDR_A_D4
134
136
138
140

DDR_A_D3
142

DDR_A_D7
144

DDR_A_D18
148

DDR_A_D19
150
152

DDR_A_DQS#2
154

DDR_A_DQS2
156
158

DDR_A_D22
160

DDR_A_D23
162
164

DDR_A_D37
166

DDR_A_D32
168

170

172

174

DDR_A_D35

176

DDR_A_D39
178
180

DDR_A_D63
182

DDR_A_D59
184
186

DDR_A_DQS#7
188

DDR_A_DQS7
190
192

DDR_A_D56
194

DDR_A_D57
196

198

200

PCH_SMBDATA

202

PCH_SMBCLK
204

206

+0.6V_0.675VS

1

@ESD@

CD99

0.1U_0402_16V7K

2

DDR_CKE1_DIMMA <5>

M_CLK_DDR1 <5>
M_CLK_DDR#1 <5>

DDR_A_BS1 <5>
DDR_A_RAS# <5>

DDR_CS0_DIMMA# <5>

0.1U_0402_16V7

K

CD3

1

2

DDR3_DRAMRST#<16,4>

PCH_SMBDATA <16,7>
PCH_SMBCLK <16,7>

+1.35V_VDDQ

+5VALW

RD21
220K_0402_5%

1 2 12

@
RD25

2M_0402_5%

+V_VDDR_REFA_CA

QD1

BSS138_NL_SOT23-3

1 3

D

S

G

2

SM_PG_CTRL

+0.6V_0.675VS

RD20 1 2 66.5_0402_1% M_ODT0
RD221 2 66.5_0402_1% M_ODT1
RD23 1
RD24 1

0.1U_0402_16V7

K

1

2

CD19

2 66.5_0402_1% M_ODT2
2 66.5_0402_1% M_ODT3

SM_PG_CTRL <4>

0.1U_0402_16V7

K

CD21

1

2

M_ODT2 <16>
M_ODT3 <16>

10U_0603_6.3V6M

CD24

1

2

Security Classification

Issued Date

THIS SH EET OF ENG INEE RING D RAW ING IS THE PR OPRI ETAR Y PROP ERTY OF CO MPA L EL ECTRO NICS , INC. AND CON TAIN S CONF IDENTIAL
AND TRA DE SECR ET INFO RMATI ON. THIS SH EET MA Y NO T BE TRA NSF ERE D FR OM THE CUS TODY OF THE CO MPET ENT D IVISION OF R& D
DEP ARTM ENT E XCEP T A S A UTHOR IZED B Y C OMP AL EL ECTR ONICS , INC. NE ITHER THIS SH EET NOR THE IN FORM ATIO N IT CONT AINS

5 4 3 2 1

MAY BE U SED BY OR DISCL OSE D TO A NY TH IRD PARTY WITH OUT PRIO R W RIT TEN CONS ENT OF COMPA L ELE CTRO NICS , INC.

2011/06/29 2011/06/29 T itle

Compal Secret Data

Deciphered Date

DDR3L DIMM0

Size Document Number

C

LA-B972P

Date: Thursday, March 20, 2014 Sheet 15 of 54

Rev

0.1

5 4 3 2 1

+V_VDDR_REFB_DQ

0.1U_0402_16V7

<5> DDR_B_D[0..63]

D D

C C

B B

A A

<5>DDR_B_DQS#[0..7]

+1.35V_VDDQ

10U_0603_6.3V6

M

1

2

+1.35V_VDDQ

1U_0402_6.3V6

K

1

2

<5> DDR_B_DQS[0..7]

<5> DDR_B_MA[0..15]

10U_0603_6.3V6

M

CD34

CD33

1

@

2

1U_0402_6.3V6

K

1

CD60

CD59

2 2

10U_0603_6.3V6

10U_0603_6.3V6

M

10U_0603_6.3V6

M

CD35

CD36

1

1

@

2

2

1U_0402_6.3V6

K

1U_0402_6.3V6

K

1

1

CD61

CD62

2

@

M

10U_0603_6.3V6

M

CD37

1

2

1U_0402_6.3V6

K

1

CD67

2

@

10U_0603_6.3V6

M

10U_0603_6.3V6

CD39

1

2

1U_0402_6.3V6

K

1

CD69

2 2

M

CD40

1

@

2

1U_0402_6.3V6

K

1

CD70

CD38

1

@

2

1U_0402_6.3V6

K

1

CD68

2

@

K

CD27

1

2

<5> DDR_CKE0_DIMMB

<5> DDR_B_BS2

<5> M_CLK_DDR2
<5> M_CLK_DDR#2

<5> DDR_B_BS0
<5> DDR_B_WE#

<5> DDR_B_CAS#

<5> DDR_CS1_DIMMB#

+3VS

0.1U_0402_16V7

K

1

2

+1.35V_VDDQ +1.35V_VDDQ

+V_VDDR_REFB_DQ
DDR_B_D8

DDR_B_D14

DDR_B_D10
DDR_B_D11

DDR_B_D28
DDR_B_D29

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D26
DDR_B_D27

DDR_B_D40
DDR_B_D41

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D42

DDR_B_D56
DDR_B_D57

DDR_B_D59
DDR_B_D58

DDR_CKE0_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3

DDR_B_MA1
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_MA10

DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_B_MA13

DDR_CS1_DIMMB#

DDR_B_D4
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D3
DDR_B_D7

DDR_B_D21
DDR_B_D20

DDR_B_D22
DDR_B_D23

DDR_B_D36
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D35
DDR_B_D39

DDR_B_D52
DDR_B_D49

DDR_B_D48
DDR_B_D53

CD44

+3VS

%

12

JDIMM2

1

VREF_DQ VSS1

3

VSS2 DQ4

5

DQ0 DQ5

7

DQ1 VSS3

9

VSS4 DQS#0

11 12

DM0 DQS0

13

VSS5 VSS6

15

DQ2 DQ6

17

DQ3 DQ7

19

VSS7 VSS8

21

DQ8 DQ12

23

DQ9 DQ13

25

VSS9

27

DQS#1

29

DQS1

31

VSS11 VSS12

33

DQ10 DQ14

35

DQ11 DQ15

37

VSS13 VSS14

39

DQ16 DQ20

41

DQ17 DQ21

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18 DQ23

53

DQ19 VSS19

55

VSS20 DQ28

57

DQ24 DQ29

59

DQ25 VSS21

61

VSS22

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0 CKE1

75

VDD1 VDD2

77

NC1 A15

79

BA2 A14

81

VDD3 VDD4

83

A12/BC# A11

85

A9 A7

87

VDD5 VDD6

89

A8 A6

91

A5 A4

93

VDD7 VDD8

95

A3 A2

97

A1 A0

99

VDD9 VDD10

101

CK0 CK1

103

CK0# CK1#

105

VDD11 VDD12

107

A10/AP

109

BA0

111

VDD13 VDD14

113

WE# S0#

115

CAS# ODT0

117

VDD15 VDD16

119

A13

121

S1# NC2

123

VDD17 VDD18

125

NCTEST VREF_CA

127

VSS27 VSS28

129

DQ32 DQ36

131

DQ33 DQ37

133

VSS29 VSS30

135

DQS#4

137

DQS4 VSS31

139

VSS32 DQ38

141

DQ34 DQ39

143

DQ35 VSS33

145

VSS34 DQ44

147

DQ40 DQ45

149

DQ41 VSS35

151

VSS36 DQS#5

153

DM5

155 156

VSS37 VSS38

157

DQ42 DQ46

159

DQ43 DQ47

161

VSS39 VSS40

163

DQ48 DQ52

165

DQ49 DQ53

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50 DQ55

177

DQ51 VSS45

179

VSS46 DQ60

181

DQ56 DQ61

183

DQ57 VSS47

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59 DQ63

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

RD4

10K_0402_5

VTT1

205

G1 G2

FOX_AS0A626-U4R6-7H

CONN@

VSS10

RESET#

VSS16

DM2

VSS17

DQ22

DQS#3

DQS3

VSS24

DQ30
DQ31

VSS26

BA1

RAS#

ODT1

DM4

DQS5

VSS42

DM6

VSS43

DQ54

DQS#7

DQS7

VSS50

DQ62

VSS52

EVENT#

SDA
SCL

VTT2

2
4

DDR_B_D12

6

DDR_B_D9
8
10

DDR_B_DQS#1

DDR_B_DQS1
14
16

DDR_B_D13
18

DDR_B_D15
20
22

DDR_B_D25
24

DDR_B_D24
26

28

DM1

30

DDR3_DRAMRST#

32

34

DDR_B_D30
36

DDR_B_D31
38
40

DDR_B_D45
42

DDR_B_D44
44
46

48
50

DDR_B_D47

DDR_B_D43

52
54
56

DDR_B_D61

58

DDR_B_D60
60
62

DDR_B_DQS#7
64

DDR_B_DQS7
66
68

DDR_B_D63
70

DDR_B_D62
72

DDR_CKE1_DIMMB

74
76
78

DDR_B_MA15
80

DDR_B_MA14
82
84

DDR_B_MA11
86

DDR_B_MA7
88
90

DDR_B_MA6
92

DDR_B_MA4
94
96

DDR_B_MA2
98

DDR_B_MA0
100
102

M_CLK_DDR3
104

M_CLK_DDR#3
106
108

DDR_B_BS1
110

DDR_B_RAS#
112
114

DDR_CS0_DIMMB#
116

M_ODT2
118

M_ODT3

120
122
124

+V_VDDR_REFA_CA

126
128
130

DDR_B_D5
132

DDR_B_D0
134
136
138
140

DDR_B_D2
142

DDR_B_D6
144
146

DDR_B_D16
148

DDR_B_D17
150
152

DDR_B_DQS#2
154

DDR_B_DQS2
158

DDR_B_D19
160

DDR_B_D18
162
164

DDR_B_D37
166

DDR_B_D32
168
170

172

174

DDR_B_D34

DDR_B_D38

176
178
180

DDR_B_D51

182

DDR_B_D55
184
186

DDR_B_DQS#6
188

DDR_B_DQS6
190
192

DDR_B_D54
194

DDR_B_D50
196

198

200

PCH_SMBDATA

202

PCH_SMBCLK
204

206

+0.6V_0.675VS

DDR3_DRAMRST#<15,4>

DDR_CKE1_DIMMB <5>

M_CLK_DDR3 <5>
M_CLK_DDR#3 <5>

DDR_B_BS1 <5>
DDR_B_RAS# <5>

DDR_CS0_DIMMB# <5>
M_ODT2 <15>

M_ODT3 <15>

0.1U_0402_16V7

K

CD29

1

2

PCH_SMBDATA <15,7>
PCH_SMBCLK <15,7>

+V_VDDR_REFA_CA

+0.6V_0.675VS

K

1

2

CD50

0.1U_0402_16V7

K

0.1U_0402_16V7
CD46

CD45

1

2

10U_0603_6.3V6M

1

2

Security Classification

Issued Date

THIS SH EET OF ENG INEE RING D RAW ING IS THE PR OPRI ETAR Y PROP ERTY OF CO MPA L EL ECTRO NICS , INC. AND CON TAIN S CONF IDENTIAL
AND TRADE SEC RET INFOR MATIO N. THIS SHE ET MAY N OT BE TRANS FERE D FR OM THE C USTO DY OF THE COMPE TENT DIVISION OF R &D
DEP ARTM ENT E XCEP T A S A UTHOR IZED B Y C OMP AL EL ECTR ONICS , INC. NE ITHER THIS SH EET NOR THE IN FORM ATIO N IT CONT AINS

5 4 3 2 1

MAY BE U SED BY OR DISCL OSE D TO A NY TH IRD PARTY WITH OUT PRIO R W RIT TEN CONS ENT OF COMPA L ELE CTRO NICS , INC.

2010/05/27 2011/05/11 T itle

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Size Document Number

LA-B972P

Date: Thursday, March 20, 2014 Sheet 16 of 54

DDR3L DIMM1

Rev

0.1

5

4

3 2

1

DDR3L VREF

<CPU>

+V_SM_VREF_CNT

0.022U_0402_25V7K

CD53

24.9_0402_1%

RD12

@

@

1

2

12

RD8

1 2

2_0402_1%

2

+1.35V_VDDQ

12

RD5

1.8K_0402_1%

12

RD9

1.8K_0402_1%

+1.35V_VDDQ

12

RD13

1.8K_0402_1%

12

RD17

1.8K_0402_1%

+V_VDDR_REFA_DQ <DDR3L_A>

+V_VDDR_REFB_DQ <DDR3L_B>

D D

RD7

@

@

@

@

1

2

12

1

2

12

1

2_0402_1%

RD15

1 2

2_0402_1%

<CPU> +V_DDR_REFA_R

0.022U_0402_25V7K

C C

<CPU>

B B

+V_DDR_REFB_R

CD52

RD11

24.9_0402_1%

0.022U_0402_25V7K

CD54

RD19

24.9_0402_1%

+1.35V_VDDQ

12

RD6

1.8K_0402_1%

12

RD10

1.8K_0402_1%

+V_VDDR_REFA_CA

<DDR3L_A_CA>
<DDR3L_B_CA>

A A

Security Classification

Issued Date

TH IS SH E ET OF ENG I NEE RI N G DR A W IN G IS TH E P ROP R IE T AR Y P ROP ERT Y O F COM PAL E L EC T RON I CS , IN C. A N D C ON TAI NS CONFIDENTISSAiL
AN D T RAD E S ECR ET IN FO RMATI ON . TH IS S H EE T MAY N O T BE T R AN S FER ED FRO M TH E CUS T OD Y OF TH E CO M PE T ENT D IVISI ON OF R& D
DE P ART MEN T EX CEP T AS A U THO R IZE D BY C O MP A L EL E CT R ONI CS, IN C. N EIT HE R THI S SH E ET N O R T HE I N FO R MAT ION IT CO NT AIN S

5

4

MA Y BE US ED BY OR D IS CLOSE D TO AN Y TH IRD P ART Y W IT H OUT PRI O R WRI TTE N CON SEN T OF C O MP A L EL E CT R ONI CS, IN C.

2011/06/29 2011/06/29

3 2

Compal Secret Data

Deciphered Date

Title

DDR3L VREF

ze Document Number

LA-B972P

Compal Electronics, Inc.

Sheet

17 of 54Date: Thursday, March 20, 2014

1

Rev

0.1

5

JPHW7 need to short

+3VS

80mil 80mil

@J PHW7

1

1 2

JUMP_43X 79

2

Layout note

Close to Pin3

D D

10U_0603_6.3V6M

1

CT16

2

LVDS@

0.1U_0402_16V4Z

LVDS@

0.1U_0402_16V4Z

1

CT17

2

LVDS@

SWR / LDO Mode select

LDO SWR

2132S Do notsupport mount LT7

+3VS_RT

+DP_V33

1

CT18

2

Layout note
Close to LT5

10U_0603_6.3V6M

1

2

LVDS@ LVDS@

+3VS_RT

+SWR _V12

Close to Pin18 Close toPin13

22U_0603_6.3V6M

0.1U_0402_16V4Z
1

CT8

CT7

2

LVDS@

LT6 2 1 +DP_V33
FBMA-L11-201209-221LMA30T _0805

2 1 +SWR_ VDD

LT5

80mil

FBMA-L11-201209-221LMA30T _0805

2 1 +SW R_LX

@ LT7 0_1206_5%

<SI> LT7 change to 0 ohm short pad

use LDO mode translator only

2132R Use 0 ohm mount LT7

C C

※ If use 2132R, please select LDO mode asdefault.

<CPU CTRL>

<8> EDP_HPD

<30,32,7> EC_SMB_CK2
<30,32,7> EC_SMB_DA2

EDP_HPD 1 2 RT192

12

RT11
100K_0402_5%

1

2

LVDS@

LVDS@

12K_0402_1%

CT9

4

0.1U_0402_16V4Z
1

CT10

2

LVDS@

EDP_CPU_AUX
EDP_CPU_AUX#

EDP_CPU_LANE_P0
EDP_CPU_LANE_N0

LVDS@

1K_0402_1%

RT8

LVDS@

1 2

+SWR _VDD

0.1U_0402_16V4Z
1

CT11

2

LVDS@

UT1

3

40mil

DP_V33

13

100mil

SWR_VDD

18

40mil

PVCC

12

40mil

SW R_LX

11

40mil

27

SWR_VCCK

40mil

VCCK

7

40mil

DP_V12

2

AUX_P

1

AUX_N

5

LANE0P

6

LANE0N

9

CIICSCL1

10

CIICSDA1

32

HPD

8

DP_REXT

4

DP_GND

LVDS@ RTD2132R-CG Q FN32

Layout note
Close to Pin11 Pin27

10U_0603_6.3V6M

LVDS@

Powe r

LVDS

RTD2132S

DP-IN

GPIO (PW M OUT )

GPIO(Pa nel_VCC)

GPIO(PW M IN)

GPIO

LVDS

Othe r

EDID MIICDA1

ROM

SA000069200

1

CT12

2

LVDS@ LVDS@

TXEC+

TXEC­TXE2+

TXE2-

TXE1+

TXE1-

TXE0+

TXE0-

GPIO(BL _EN)

MIICSCL1

MIICSCL0

MIICSDA0

GND

0.1U_0402_16V4Z
1

CT13

2

19
20

21
22

23
24

25
26

14 DP_INT_PWM
15 +DP_EN VDD
16 BK L_PWM_CPU
17 T S_BKOFF #

29 LCD_EDID_CLK
28 LCD_EDID_D ATA

31 MIIC_SCL
30 MIIC_SDA

33

Close to

0.1U_0402_16V4Z
1

2

LVDS_CLKP
LVDS_CLKN

LVDS_TXP2
LVDS_TXN2

LVDS_TXP1
LVDS_TXN1

LVDS_TXP0
LVDS_TXN0

3

CT14

Close to Pin7

+SWR _V12

0.1U_0402_16V4Z
1

CT15

2

LVDS@

LVDS_CLKP <19>
LVDS_CLKN <19>

LVDS_TXP1 <19>
LVDS_TXN1 <19>

LVDS_TXP0 <19>
LVDS_TXN0 <19>

DP_INT_PWM <19>

+DP_ENVDD <19>

BKL_PW M_CPU <4,8>

<CONN>

<CONN>

<CPU>

2

※R OM only mode : PIN 30 4.7k pull low, Pin 31 4.7k pull high.

EP mode : PIN 30 4.7k pull high, Pin 31 4.7k pull low.
EEPROM : PIN 30 4.7k pull high, Pin 31 4.7k pull high.

〈 ※De fault mode 〉

+3VS_RT

2132S@

@

RT2

4.7K_0402_5%

MIIC_SDA MIIC_SCL

2 1 2

RT4

PIN30 PIN31

LVDS@ 4.7K_0402_5%

1

LCD_EDID_CLK RT6 1 2 4.7K_0402_5%
LCD_EDID_DATA RT7 1 2 4.7K_0402_5%

LVDS@
LVDS@

PIN15

2132S TL_ENVDD

2132R +LCD_VDD *

* Version R internal Power Switch, can

output 1A, Rds(on)=0.2 ohm

+3VS_RT

2

RT3

LVDS@

4.7K_0402_5%

2132S@

@

RT5

4.7K_0402_5%

1 2 1

+3VS_RT

PIN16 Accept voltage input (highlevel)

2132S 3.3V

2132R 1.5~3.3V

* Version R has internal level shifter, remove

level shifter circuit on AMDplatform

Different between 2132S and 2132R

1

2132S 2132R

Layout note

Close to Pin8

2 .1U_0402_16V7K EDP_CPU_AUX

<CPU>

B B

<4> EDP_CPU_AUX_C

<4> EDP_CPU_AUX#_C
<4> EDP_CPU _LANE_P0_C
<4> EDP_CPU_L ANE_N0_C

CC102 1
CC101
CC98
CC97

2

.1U_0402_16V7K

1

2

.1U_0402_16V7K EDP_CPU_LANE_P0

1

2

.1U_0402_16V7K EDP_CPU_LANE_N0

1

EDP_CPU_AUX#

+DP_ENVDD 1

80ml trace width

RT9

0_0805_5%

LVDS@

Close toPin15

2

CT23

4.7U_0603_6.3V6K
LVDS@

Close to Panelconn.

2

1

10/9 colay eDP use close Connector

@

<RTS2132>

<EC CTRL>

A

<30> EC_BKOFF#

<PV> Add RT12

RT14 1 2 0_0402_5%

+3VS

TS_BKO FF#
EC_BKOF F#

TC7SH08FUF_SSOP5

12

RT12
100K_0402_5%
LVDS@

5

1
2

LVDS@

RT15 1 2 0_0402_5%

B
A

5

3

eDP@

UT3

P

G

CT24

1 2

0.1U_0402_16V7K

4

Y

@

<SI> Update UT3 footprint (As UV11)

EC_TS_ BKOFF# <19>

PD 100K on LVDS page

4

<LVDS Panel>

+LCDVDD

12

RT10
100K_0402_5%
LVDS@

EDP_CPU_LANE_N0 1 8 EDP_LANE_N0
EDP_CPU_LANE_P0 2 7 EDP_LANE_P0

EDP_CPU_AUX 3 6 EDP_AUX
EDP_CPU_AUX# 4 5 EDP_AUX#

Security Classification

Issued Date

THI S SH EE T OF E NG INE ER ING DR AW IN G IS TH E PR OPR IE TAR Y PRO PE R TY OF COM PA L EL EC TRO NIC S, IN C. AN D CO NTA INS CONFI DENT IAL
AN D T RA DE S EC RE T I NFO RM AT ION . TH IS SH EET M AY NOT BE TR A NS FE RE D FRO M THE CU STO DY OF T HE COM PE TE NT DI VIS ION OF R &D
DE PA RTM ENT EX CE PT AS A UT HOR IZ ED BY CO MPA L EL EC TRO NIC S, IN C. NE ITH ER TH IS S HE ET N OR T HE I NFO RM ATI ON IT CO NTA IN S
MA Y BE USE D BY OR D ISC LO SE D TO AN Y TH IRD P AR TY W ITHO UT P RIO R WRI TTE N CON SE NT OF C OMP AL EL EC TRO NIC S, I NC.

3

1. Support SWR mode 1. Support LDO mode and SWR mode

2. Internal ROM

3. Support LCD_VDD(internal Power switch)

4. Integrates Level shifter

<CPU by PASS eDP>

0_0804_8P4R_ 5%

eDP@

SD309000080

RP6

EDP_AUX 4 5 LCD_CLK

EDP_AUX# 3 6 LCD_DATA
EDP_LANE_N0 2 7 LVDS_TXN2_LN0
EDP_LANE_P0 1 8 LVDS_TXP2_LP0

2

EDP_HPD RT34 1 eDP@ 2 0_0201 _5% EDP_HPD_PAN EL
BKL_PW M_CPU RT35 1 eDP@ 2 0_0201_5% DP_INT_PWM

<LVDS toconnector>

2

0_0804_8P4R_ 5%

LVDS@

RP10

SD309000080

LCD_EDID_CLK 1 8 LCD_CLK
LCD_EDID_DATA 2 7 LCD_DATA
LVDS_TXN2 3 6 LVDS_TXN2_LN0
LVDS_TXP2 4 5 LVDS_TXP2_LP0

2013/3/1 2015/3/1

Compal Secret Data

DecipheredDate

<PV>Change PR37 pin define , Add PR38.
<PV>PR36 Change to RP6.

<eDP toconnector>

RP9

SD309000080

eDP@

0_0804_8P4R_ 5%

4

EDP_HPD_PANEL <19>

PR37 change to RP9.
PR38 change to RP10.

Compal Electronics, Inc.

Title

LVDS Translator-RTD2132R

Siz e Document Number

LA-B972P

Date: Thursday, March 20, 2014

LCD_CLK <19>
LCD_DATA <19>
LVDS_TXN2_LN0 <19>
LVDS_TXP2_LP0 <19>

Sheet

1

Rev

18

0.1

54

of

A

5

LVDSPower

+3VS

0_0201_5%

RG1 1 eDP@2

D D

2132S@

1500P_0402_50V7K

<18> +DP_ENVDD

<8> ENVDD_CPU

CG1
eDP@

1

2

RG3 1 @ 2 0_0402_5%

R172 1 2 0_0402_5%

2132S@

5

IN OUT

4

SS

APL3512_SOT23-5

eDP@

eDP@

GND

UG1

EN

1
2
3

<PV>Change BOMstructure

2132S@

eDP@

1

CG2

4.7U_0603_6.3V6K

2

4

+LCDVDD

2132S@

0.1U_0402_16V7K
CG3

@

1

2

3 2

+3VALW

+VCC_TOUCH

eDP@

1

CTS1

0.1U_0402_16V4Z

2

Touch ScreenPower

12 2

eDP@

RTS1
1K_0402_5%

CTS2

1 2

eDP@

1 3

DGS

QTS2

0.047U_0402_16V7K
+3VS

eDP@

S TR LP2301ALT1G 1PSOT-23-3

2N7002K_SOT23

1

1 23

D

eDP@

QTS1

S

<PV>Change Touch power to3V

eDP@

RTS2
100K_0402_5%

2

G

TOUCH_ON# <30>

@EMI@ C117

680P_0402_50V7K

1

INVPWR_B+ B+

1

2

0_0805_5% 2

1

2

2 1 L2

C118
68P_0402_50V8J

@EMI@

1 L1

@EMI@ 0_0805_5%

SM0100145203000ma
220ohm@100mhz
DCR 0.04

W=60milsW=60mils

Camera

<10> USB20_N4

C C

EC_TS_BKOFF#

12

2

0_0402_5%

R167
10K_0402_5%

<30> EC_INVT_PWM

<18> DP_INT_PWM

<18> EC_TS_BKOFF#

B B

R2591 @

R258 1 @ 2 0_0402_5%

INVTPWM

12

R163
10K_0402_5%

R166 33_0402_5%

1 2 DISPOFF#

<10> USB20_P4

@

D_MIC_L_CLK 2
D_MIC_L_DATA 3

Part Number = SM070003Y00

D3

PESD5V0U2BT_SOT23-3

@ESD@ SCA00000U10

<PV>Remove R168,R169.

USB20_P5_R
USB20_N5_R USB20_N5_R

A A

5

4

@

R170 1

L12 EMI@

1

1

4

4 3

WCM-2012-900T_4P

1 R171 2 0_0402_5%

@

<PV>L12 changePN.

1

<25> D_MIC_CLK
<25> D_MIC_DATA

D6

2
3

PESD5V0U2BT_SOT23-3

@ESD@ SCA00000U10

2 0_0402_5%

2

1

2

USB20_N4_R

USB20_P4_R

3

USB20_P4_R
USB20_N4_R

<DB>LA1/LA2 closed to Aduiocodec

D_MIC_CLK 1

D_MIC_DATA 1 @

LA2 0_0603_5%

<PV>LA1,LA2 change PN, LA2 change to 0ohm.
<MV>LA2 change to short pad.

<9> TS_GPIO_CPU

<30> TS_GPIO_EC

TouchScreen

<10> USB20_P5

<10> USB20_N5

Part Number = SM070003Y00

Security Classification

Issued Date

THI S SHEET OF E NG INE ER ING D RA WI NG IS T HE PROPR IET AR Y PRO PE RT Y OF C OMP AL EL EC TR ONICS , INC. AN D CONT AINS C ONF IDEN TIA L
AND T RADE SECRE T INF ORMAT ION . THIS S HE ET MAY N OT BE T RA NS FER ED FR OM TH E C US TO DY OF T HE CO MPE TE NT DIVISION OF R&D
DEPAR TMENT EX CEPT AS A UT HO RIZ ED BY C OMPAL ELEC TR ON ICS , INC. NEIT HER THIS SH EET NOR TH E INFO RM ATION IT CONT AIN S
MAY BE USE D BY OR DI SCLOSE D TO A NY TH IRD PA RT Y WITHOUT PRIO R WR IT TEN CON SE NT OF CO MPAL ELE CT RO NIC S, INC.

3 2

D5

2

1

3

PESD5V0U2BT_SOT23-3

@ESD@ SCA00000U10

<18> LCD_CLK

<18> LCD_DATA

<18> LVDS_TXP0

<18> LVDS_TXN0

<18> LVDS_TXP1

<18> LVDS_TXN1

EMI@

FBMA-L10-160808-301LMT_2P

LA1

2 D_MIC_L_CLK

2 D_MIC_L_DATA

R260TS_GPIO_CPU

TS_GPIO_EC R2611 @

<PV>L13 change PN,BS.

1 @ 2

@

R173 1 2 0_0402_5%

L13 eDPEMI@

1

1

4

4 3

WCM-2012-900T_4P

1 R174 2 0_0402_5%

@

2

2013/02/26 2015/07/08

<18> LVDS_TXP2_LP0

<18> LVDS_TXN2_LN0

<18> LVDS_CLKP

<18> LVDS_CLKN

TS_GPIO

0_0402_5%

0_0402_5%

2

USB20_P5_R

2

3

Compal Secret Data

DecipheredDate

INVPWR_B+

+VCC_TOUCH

+3VS

<18> EDP_HPD_PANEL

DISPOFF#
INVTPWM
TS_GPIO

LCD/LED PANELConn.

+LCDVDD

CONN@
JLVDS1

1

1

2

2

LCD_CLK
LCD_DATA

USB20_N4_R
USB20_P4_R

USB20_P5_R
USB20_N5_R

D_MIC_L_CLK
D_MIC_L_DATA

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

STARC_107K40-000001-G2

<PV>JLVDS1 pin40 change toNC.

Title

LVDS Connector

SSize Document Number

1 220P_0402_50V7K INVTPWM

C121 2

1

C122 2

220P_0402_50V7K DISPOFF#

41

G1

42

G2

43

G3

44

G4

45

G5

46

G6

Compal Electronics,Inc.

LA-B972P

1

Rev

0.1

54Date: Thursday, March 20, 2014 Sheet 19 of

5

4

3 2

1

12

10P_0402_50V8J

1

CM27

2

+3VS

2

61

QG1A
2N7002KDW_SOT363-6

5VLevel

PCH_DDPB_CLK

PCH_DDPB_DAT

12

RG56

20K_0402_5%

HP_DETECT

+HDMI_5V_OUT

HDMI_SDATA
HDMI_SCLK

HDMI_R_CK­HDMI_R_CK+

HDMI_R_D0­HDMI_R_D0+

HDMI_R_D1­HDMI_R_D1+

HDMI_R_D2­HDMI_R_D2+

HP_DETECT

1

CM17

@

220P_0402_50V7K

2

+3VS

5

QG2B

4

2N7002DWH_SOT363-6

SB00000DH00

HDMI Conn.

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK- GND

11

CK_shield GND

10

9
8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

CONCR_099AKAC19NBLCNF
CONN@

CK+ GND

D0- GND

21

3 HDMI_SCLK

+3VS

2

1
2N7002DWH_SOT363-6

SB00000DH00QG2A

20

22
23

6 HDMI_SDATA

<4> PCH_DPB_P0
<4> PCH_DPB_N0

<4> PCH_DPB_P1

<CPU>

<4> PCH_DPB_N1
<4> PCH_DPB_P2

<4> PCH_DPB_N2

D D

C C

B B

<4> PCH_DPB_P3
<4> PCH_DPB_N3

SM070003K00

PCH_DPB_N3_C

SM070003K00CMMI21T-900Y-N

PCH_DPB_P0_C HDMI_R_D0+

SM070003K00

PCH_DPB_N1_C

SM070003K00

PCH_DPB_N2_C

PCH_DPB_P0 0.1U_0402_16V7K 1
PCH_DPB_N0 0.1U_0402_16V7K 1

PCH_DPB_P1 0.1U_0402_16V7K
PCH_DPB_N1 0.1U_0402_16V7K 1

PCH_DPB_P2 0.1U_0402_16V7K
PCH_DPB_N2 0.1U_0402_16V7K 1

PCH_DPB_P3 0.1U_0402_16V7K
PCH_DPB_N3 0.1U_0402_16V7K 1

CMMI21T-900Y-N

EMI@

LM13

EMI@ LM14

CMMI21T-900Y-N

EMI@

LM15

CMMI21T-900Y-N

EMI@

LM16

+5VS

@

RG59 1 2 0_0402_5%

4

1

1 2

RG60 1 2 0_0402_5%

@
@

RG61 1 2 0_0402_5%

1

1 2

4

RG63 1 2 0_0402_5%

@

RG64 1 @ 2 0_0402_5%

4

4

1

1 2

RG65 1 2 0_0402_5%

RG66 1 @ 2 0_0402_5%

1

@

4

1

1 2

RG70 1 2 0_0402_5%

@

FG1

IN

AP2330W-7_SC59-3

A A

OUT

GND

1

1

1

34

3

2

2

34

3

3

2

34

3

2

3

2

2 CG27
2 CG28

2 CG29
2 CG30

2 CG31
2 CG32

2 CG33
2 CG34

3

W=40mils

0.1U_0402_16V7K

567

8

432

1

RP3
470_0804_8P4R_5%

HDMI_R_CK+PCH_DPB_P3_C

HDMI_R_CK-

HDMI_R_D0-PCH_DPB_N0_C

HDMI_R_D1+PCH_DPB_P1_C

HDMI_R_D1-

HDMI_R_D2+PCH_DPB_P2_C

HDMI_R_D2-

+HDMI_5V_OUT

1

CG46

2

567

8

432

1

RP4
470_0804_8P4R_5%

+3VS

PCH_DPB_P0_C
PCH_DPB_N0_C

PCH_DPB_P1_C
PCH_DPB_N1_C

PCH_DPB_P2_C
PCH_DPB_N2_C

PCH_DPB_P3_C
PCH_DPB_N3_C

2N7002KDW_SOT363-6

QG1B

3 4

5

+HDMI_5V_OUT

+3VS

@ESD@

HP_DETECT
HDMI_SDATA
HDMI_SCLK

DG1

1 1
2 2
4 4
5 5
3 3

8

RG105
1
2
3

4

2.2K_0804_8P4R_5%

SC300002800

IP4292CZ10-TB

<8> PCH_DDPB_HPD

8 HDMI_SDATA
7 HDMI_SCLK
6 PCH_DDPB_DAT
5 PCH_DDPB_CLK

109 HP_DETECT

9 8 HDMI_SDATA
7 7 HDMI_SCLK
6 6

RG47

1M_0402_5%

<8> PCH_DDPB_CLK

<8> PCH_DDPB_DAT

@

@

10P_0402_50V8J

1

CM26

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECT RONICS, I NC. AND CO NTAINS CONFIDENTIASL
AND TRADE SECRET INFORMAT ION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUS TOD Y OF TH E COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RON ICS, INC. NEITHER TH IS SHEET NOR T HE INFORMATI ON IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WIT HOU T PRIOR WRITTEN CONSENT OF C OMPAL ELECTRONIC S, INC.

2011/06/29 2011/06/29

3 2

Compal Secret Data

DecipheredDate

Title

ize DocumentNumber

Compal Electronics, Inc.

HDMI Conn/Level shift

LA-B972P

Sheet

1

Rev

20 of 54Date: Thursday, March 20,2014

0.1

5 4 3 2 1

+3VS_WLAN

D D

C C

<30> BT_ON_EC

<41> MC_WAKE#

short@

<30> EC_PCIE_WAKE#

<30> E51TXD_P80DATA

<30> E51RXD_P80CLK

BT_ON_EC 1 RC160 2 E51RXD_P80CLK

1K_0402_1%

RN13 1

<6> PCIE_PRX_DTX_N6
<6> PCIE_PRX_DTX_P6

<6> PCIE_PTX_C_DRX_N6
<6> PCIE_PTX_C_DRX_P6

0_0201_5%

2

<7> MINI1_CLKREQ#

<7> CLK_PCIE_MINI1#

<7> CLK_PCIE_MINI1

E51TXD_P80DATA
E51RXD_P80CLK

+3VS_WLAN

BT_ON_EC

R216
100K_0402_5%

1 2

12

RN3
10K_0402_5%

JMINI1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51 52

53

GND1 GND2

BELLW_80053-1021
CONN@

+3VS_WLAN+1.5VS_WLAN

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

54

12

RN7

4.7K_0402_5%

+3VS_WLAN

WL_OFF#

WL_OFF# <10,9>
PLT_RST# <23,28,30,32,8>

+3VS_WLAN

USB20_N3 <10>
USB20_P3 <10>

MINI1_LED# <30>

+1.5VS +1.5VS_WLAN

B B

+3VS_WLAN_R

R271 @

1 2

0_0805_5%

<PV>R271 change to 0805

RN1 @

1 2

0_0603_5%

+3VS_WLAN

@

1

CN2

4.7U_0603_6.3V6K

2

1

CN1

4.7U_0603_6.3V6K

2

@

0.1U_0402_16V7K
CN3

1

2

<30> WL_PWREN_EC

+5VALW

WL_PWREN_EC 3

+3VALW

<PV>Change WLAN power to single load switch.

Q23

GND
GND

7
8

6

5
9

1
J

2

1

C571

10U_0603_6.3V6M

C558

100P_0402_50V8

2

1

VIN VOUT

2

VIN VOUT
ON CT

4

VBIAS

TPS22967DSGR_SON8_2X2

+3VS_WLAN_R

<PV>C558 change to 100pf for SVTP spec.

A A

Security Classification

Issued Date

TH IS SH E ET OF ENG I NEE RI N G DR A W IN G IS TH E P ROP R IE T AR Y P ROP ERT Y O F COM PAL E L EC T RON I CS , IN C. A N D C ON TAI NS CONFIDENTISSAiL
AN D T RAD E S ECR ET IN FO RMATI ON . TH IS S H EE T MAY N O T BE T R AN S FER ED FRO M TH E CUS T OD Y OF TH E CO M PE T ENT D IVISI ON OF R& D
DE P ART MEN T EX CEP T AS A U THO R IZE D BY C O MP A L EL E CT R ONI CS, IN C. N EIT HE R THI S SH E ET N O R T HE I N FO R MAT ION IT CO NT AIN S

5 4 3 2

MA Y BE US ED BY OR D IS CLOSE D TO AN Y TH IRD P ART Y W IT H OUT PRI O R WRI TTE N CON SEN T OF C O MP A L EL E CT R ONI CS, IN C.

2013/02/26 2015/07/08

Compal Secret Data

Deciphered Date

Title

ze Document Number

Date: Thursday, March 20, 2014 Sheet121 of 54

Compal Electronics, Inc.

WLAN

LA-B972P

Rev

0.1

5 4 3 2 1

2.5" SATA HDD connector

+5VS

D D

R201 1

R212 1

@

0_0603_5%@

2

0_0603_5%

2

+5VS_HDD1

+5VS_HDD1

1

2

<6> SATA_PTX_DRX_P0
<6> SATA_PTX_DRX_N0

10U_0603_6.3V6M

C149

0.1U_0402_16V7K
C150

1

2

<6> SATA_PRX_DTX_N0

<6> SATA_PRX_DTX_P0

C155 1
C156 1

C153 1
C154 1

<8,9> DEVSLP1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0

<SI>RS11 change to un pop

+3VS

RS11 1 @ 2 0_0402_5%

+5VS_HDD1

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0

SATA_PRX_C_DTX_N0

RS12 1

@ 2 0_0402_5%

JHDD_P10

JHDD1

1

GND

2

A+

3

A-

4

GND

5

B-

6
7

B+
GND

8

VCC3.3

9

VCC3.3

10

VCC3.3

11

GND

12

GND

13

GND

14

VCC5

15

VCC5

16

VCC5

17

GND

18

RESERVED

19

GND

20

VCC12

21

VCC12

22

VCC12

SANTA_193202-1
CONN@

GND
GND

23
24

Change to dual load switch for ODD and WLAN

C C

<9> ODD_PWR

B B

<PV>Q22 change to single load switch.

+5VALW +5VS

ODD_PWR

Q22

GND
GND

7
8

6

5
9

1

VIN VOUT

2

VIN VOUT

3

ON CT

4

VBIAS

TPS22967DSGR_SON8_2X2

C555 1 2
100P_0402_50V8J

+5VS_ODD

10U_0603_6.3V6M

1

2

22U_0805_6.3V6M

1

C576

CC73

<MV>Add 22UF for RF suggestion ,4/10.

2

@

<6> SATA_PTX_DRX_P1
<6> SATA_PTX_DRX_N1

<6> SATA_PRX_DTX_N1

<6> SATA_PRX_DTX_P1

CS11 2
CS14 2

CS15

2

CS18 2

<6> ODD_PLUG#

<9> ODD_DA#

1 0.01U_0402_16V7K
1 0.01U_0402_16V7K

1 0.01U_0402_16V7K
1 0.01U_0402_16V7K

SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1

SATA_PRX_C_DTX_N1
SATA_PRX_C_DTX_P1

ODD_DA#

+5VS_ODD

<SI> Delete Q84, R954

1

CS17

0.1U_0402_25V6K
ESD@

2

Pleace near ODD Connector

0.1U

1000P_0402_50V7K

1

CS16

2

JODD1

1

GND

2

RX+

3

RX-

4

GND

5

TX-

6

TX+

7

GND

8

DP

9

+5V

10

+5V

11

MD

12

GND

13

GND GND2

OCTEK_SLS-13HCAB

CONN@

0.1U_0402_25V6K

1

2

CS13

GND1

10U_0805_10V6

K

1

CS12

2

14
15

Place CS17 close to JODD

A A

Security Classification

Issued Date

TH IS SH E ET OF ENG I NEE RI N G DR A W IN G IS TH E P ROP R IE T AR Y P ROP ERT Y O F COM PAL E L EC T RON I CS , IN C. A N D C ON TAI NS CONFIDENTISSAiL
AN D T RAD E S ECR ET IN FO RMATI ON . THIS S HEE T MAY N O T BE T R AN S FER ED FR O M TH E CU S TOD Y OF T H E COM PET E NT DIVI SION OF R&D
DE P ART MEN T EX CEP T AS A U THO R IZE D BY C O MP A L EL E CT R ONI CS, IN C. N EIT HE R THI S SH E ET N O R T HE I N FO R MAT ION IT CO NT AIN S

5 4 3 2

MA Y BE US ED BY OR D IS CLOSE D TO AN Y TH IRD P ART Y W IT H OUT PRI O R WRI TTE N CON SEN T OF C O MP A L EL E CT R ONI CS, IN C.

2013/02/26 2015/07/08

Compal Secret Data

Deciphered Date

Title

ze Document Number

B

Date: Thursday, March 20, 2014 Sheet122 of 54

Compal Electronics,Inc.

ODD/SATA Conn

LA-B972P

Rev

0.1

5

JHW1 need to short

JHW1

@

1

2

1 2

+3VALW

1@ RL35 20_0201_5%

D D

<9> LAN_PWR_EN

1
@8161@
CL20

CL9 & CL5 close to UL1: Pin 11,32
CL19 close to UL1: Pin 32

1

@

CL9

CL19

2

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

@CL28

1500P_0402_50V7K

+LAN_VDD_3V3

1

2

0.1U_0402_16V7K

1

2

RL29 2

1

CL5

2

@

JUMP_43X79

@ UG5

5

4

@

0.1U_0402_16V7K

IN OUT

SS EN

1 10K_0402_5%LAN_PWR_EN_R

1

@

2

GND

APL3512_SOT23-5

+VDDREG

1

CL10

CL16

@

2

4.7U_0603_6.3V6K

1
2

0.1U_0402_16V7

K

CL10& CL16 close to UL1: Pin 23

CL20 close to UL1: Pin 11

C C

SP050005L00Footprint

+V_DAC 1

LAN_MDIN3 2
LAN_MDIP3 3

LAN_MDIN2 5
LAN_MDIP2 6

LAN_MDIN1 8
LAN_MDIP1 9

LAN_MDIN0 11
LAN_MDIP0 12

2 1

@

CL1

0.01U_0402_16V7K 20.1U_0402_16V7K

1

B B

RR1

1 2

+3VS +3VS_CR

0_0603_5%

short@

4.7U_0402_6.3V6M

@EMI@

CL4

1

CR9

2

Close to Chip

A A

+DVDD12

+DVDD12

4.7U_0603_6.3V6M

12

CR2

CR1

5

+AVDD12

0.1U_0402_16V7K

1

2

TSL1 8161@

TCT1 MCT1
TD1+ MX1+
TD1- MX1-

4

TCT2 MCT2
TD2+ MX2+
TD2- MX2-

7

TCT3 MCT3
TD3+ MX3+
TD3- MX3-

10

TCT4 MCT4
TD4+ MX4+
TD4- MX4-

LANKO_LG-2446S-1
SP050006800
S X’FORM_ LG-2446S-1 100/1000BASE-TX LAN

TSL1 8166@

SP050003P00
S X'FORM_ NS892404 ETHERNET 10/100

(SP050003P00) 10/100 8166@
(SP050006800) Giga 8161@

+3VS_CR

1

CR10

2

0.1U_0402_16V7K

<10> PCIE_PTX_C_DRX_P2
<10> PCIE_PTX_C_DRX_N2

<10> PCIE_PRX_DTX_P2
<10> PCIE_PRX_DTX_N2

+AVDD12

4.7U_0603_6.3V6M

12

CR3

+LAN_VDD_3V3 Rising time

need>0.5mS and <100mS

3

1

@CL29

0.1U_0402_16V7K

2

<21,28,30,32,8> PLT_RST#

<7> CLK_PCIE_LAN
<7> CLK_PCIE_LAN#

<10> PCIE_PTX_C_DRX_P3
<10> PCIE_PTX_C_DRX_N3

<10> PCIE_PRX_DTX_P3
<10> PCIE_PRX_DTX_N3

24
23

RJ45_TX3-

22

RJ45_TX3+

21
20

RJ45_TX2-

19

RJ45_TX2+

18
17

RJ45_RX1-

16

RJ45_RX1+

15
14

RJ45_TX0-

13

RJ45_TX0+

<7> CLK_PCIE_CR
<7> CLK_PCIE_CR#

0.1U_0402_16V7K

1

CR4

2

<7> LAN_CLKREQ#

CLK_PCIE_CR
CLK_PCIE_CR#

CL17 1
CL18 1

<7,9>CR_CLKREQ#

+3VS_CR

4.7U_0402_6.3V6M

4

+LAN_VDD_3V3

LAN_CLKREQ#2 @ RL6 1 0_0201_5%

PLT_RST#

CLK_PCIE_LAN
CLK_PCIE_LAN#

PCIE_PTX_C_DRX_P3

PCIE_PTX_C_DRX_N3
PCIE_PRX_DTX_P3 CR11 1
PCIE_PRX_DTX_N3 CR13 1

RP5
1 8
2 7
3 6
4 5

75_0804_8P4R_1%
SD300002E80

2

3

YSLC05CH_SOT23-3

ESD@

DL1

1

SCA00000U10

PCIE_PTX_C_DRX_P2
PCIE_PTX_C_DRX_N2

2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P2
2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N2

+3VS_CR 1

10K_0402_5%

6.2K_0402_1% 1 2 RR9

RR9 close to chip

Close to Chip

0.1U_0402_16V7K

1

1

CR6

CR5

@

2

2

4

8151/8166 Co‐Lay

LAN_MDIP0

LAN_MDIN0

LAN_MDIP1

LAN_MDIN1

LAN_MDIP2

LAN_MDIN2

LAN_MDIP3

LAN_MDIN3

LAN_CLKREQ#_R

2 0.1U_0402_10V7K PCIE_PRX_C_DTX_P3 17
2 0.1U_0402_10V7K PCIE_PRX_C_DTX_N3 18

RL11

2.49K_0402_1%

2

CL2
SE167100J80
10P_1808_3KV

1

12

EMI@

LANGND

CL3

120P_0402_50V8

RTS5239

UR1

1

HSIP

2

HSIN

3

REFCLKP

4

REFCLKN

5

HSOP

6

HSON

CR_CLKREQ#
PLT_RST#

SD_CD#

24

CLKREQ#

23

PERST#

22

MS_INS#

21

SD_CD#

19

2

RR8

RREF 8

GPIO

RREF

RTS5239-GR_QFN24_4X4

3

RTL8151G (LDOmode)

+LAN_REGOUT

CL21

8161@
UL1

MDIP0

2

MDIN0

4

MDIP1

5

MDIN1

6

MDIP2

7

MDIN2

9

MDIP3

10

MDIN3

12
19

15
16

13
14

HSIN

HSOP

RSET 31

RSET

1 2

CLKREQB

PERSTB

REFCLK_P

REFCLK_N

HSIP

HSON

SA00005YT00

RTL8111G

(SA000063500) 10/100 8166@
(SA00005YT00) Giga 8151@

12 SD_D1

SP1

13 SD_D0

SP2

14 SD_CLK EMI@ 1 RR5 2 33_0402_5%

SP3

16 SD_CMD @EMI@ 1 RR3 2 0_0402_5%

SP4

17 SD_D3

SP5

18 SD_D2

SP6

20 SD_WP

SP7

15

DV33_18

11

DV12_S

3V3_IN

CARD_3V3

+DVDD12

+3VS_CR

9

7

+AVDD12

AV12

10

25

GND

Security Classification

THIS SH EET OF ENG INEE RING D RAW ING IS THE PR OPRI ETAR Y PROP ERTY OF CO MPA L EL ECTRO NICS , INC. AND CON TAIN S CONF IDENTIAL
AND TRA DE SECR ET INFO RMATI ON. THIS SH EET MA Y NO T BE TRA NSF ERE D FR OM THE CU STODY OF THE CO MPET ENT D IVISION OF R& D
DEP ARTM ENT E XCEP T A S A UTHOR IZED B Y C OMP AL EL ECTR ONICS , INC. NE ITHER THIS SH EET NOR THE IN FORM ATIO N IT CONT AINS
MAY BE U SED BY OR DISCL OSED TO AN Y THIR D P ARTY WITH OUT PRIO R W RITTE N CONSE NT OF C OMPA L EL ECTR ONICS , INC.

3

LL1 1 20_0603_5%

@LL2

1 2

2.2UH +-5% NLC252018T-2R2J-N

1

2

0.1U_0402_16V7K

LL2, CL8, CL23 for8161
CL8 & CL18 closeLL2

31

AVDD10

8

AVDD10

30

AVDD10

22

DVDD10

11

AVDD33

32

AVDD33

REGOUT

LANWAKEB

ISOLATEB

LED0

LED1/GPO

LED2(LED1)

CKXTAL1
CKXTAL2

GND

+CR_VDD_3V3

23

24

21

20

27
26
25

28
29

33

2 0_0402_5%
2 0_0402_5%

1 2

CR141U_0402_6.3V4Z

VDDREG(VDD33)

UL1 8166@
SA000063500

RTL8166EH-CG QFN 32P E-LAN CTRL

RR4-RR9 close to chip
CR12-CR13 close to chip or socket

@EMI@ 1 RR2 2 0_0402_5%
@EMI@ 1 RR4 2 0_0402_5%

@EMI@ 1 RR6
@EMI@ 1 RR7

Issued Date

2

LDO mode Switcing mode
LL1 SMT @
CL21 SMT @
LL2 @ SMT
CL8 @ SMT

1

1

CL8

CL23

@

@

2

2

4.7U_0603_6.3V6K

1

CL12

@

CL11

2

0.1U_0402_16V7K

0.1U_0402_16V7K

1

1

CL13

2

2

0.1U_0402_16V7K

+LAN_VDD_1V0

1

1

CL15

CL14

@8161@

8161@

0.1U_0402_16V7K

2

2

0.1U_0402_16V7K

Place CL11~CL13 close UL1 Pin 3, 8 , 22

+LAN_VDD_1V0

+LAN_VDD_3V3

+VDDREG RL10 1
+LAN_REGOUT 0_0603_5%

LANWAKEB
EC_LAN_ISOLATEB#

LED0
LED1/GPO
LED2

XTLI
XTLO

+LAN_VDD_3V3=40mil
+VDDREG=40mil

L

+LAN_REGOUT=60mil

+LAN_VDD_3V3

2

TH2
TH1
TH3

+LAN_VDD_3V3

12

@
RL15
10K_0402_5%

RJ45_TX3­RJ45_TX3+
RJ45_RX1­RJ45_TX2­RJ45_TX2+
RJ45_RX1+
RJ45_TX0­RJ45_TX0+

EC_PME# <30,9>

SANTA_130456-291

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

Card ReaderConnector

208MHz

SD_D1_R
SD_D0_R

@CR12

SD_CLK_R 1 2

SD_CMD_R

SD_D3_R 6.8P_0402_50V8C
SD_D2_R

Close to Chip

2013/02/26 2015/07/08 T itle

Compal Secret Data

Deciphered Date

2

+CR_VDD_3V3

CR7

2 1

Close t o Conn

4.7U_0603_6.3V6M
1

CR8

2

0.1U_0402_16V7K

Size Document Number

CL14 & CL15 close UL1 Pin22
CL26 & CL27 close UL1Pin30

1U_0402_6.3V6K

CL26
8166@

JLAN1CONN@

XTAL@
CL25

1U_0402_6.3V6K

1

1

CL27

@8166@

2

2

0.1U_0402_16V7K
EC_LAN_ISOLATEB# 2

1K_0402_5%

RL8
15K_0402_5%

1 2

2 1 XTLO

1M_0402_5% RL7

XTAL@

1

10P_0402_50V8J

1

2

GND OSC

2

25MHZ 10PF 5YEA25000102IF50Q3

10

GND

9

GND

LANGND

SD_D3_R
SD_CMD_R

+CR_VDD_3V3
SD_CLK_R

SD_D0_R
SD_D1_R
SD_D2_R

SD_CD#
SD_WP

TAITW_PSDAT0-09GLBS1ZZ4H1

Compal Electronics, Inc.

LAN 8111G

LA-B972P

1

1

+3VS

RL5

XTLO

XTLO <31>

XTLI

XTAL@

3

YL1

10P_0402_50V8J

XTAL@

1

CL24

2

GND OSC

4

<PV>CL24,CL25 change to10pf.

CONN@
JREAD1

1

DAT3

2

CMD

3 VSS1
4 VDD

5

CLK

6

VSS2

7

DAT0

8

DAT1

9

DAT2

10

CD

11

WP

1

12

G1

13

G2

Sheet 23 of 54Date: Thursday, March 20, 2014

Rev

0.1

A

<10> USB3_TX0_P

1 1

2 2

<10> USB3_TX0_N

<10> USB3_RX0_P

<10> USB3_RX0_N

<10> USB20_P0

<10> USB20_N0

USB3_TX0_P USB3TXDP0_C_R

0.1U_0402_16V7K

USB3_TX0_N

0.1U_0402_16V7K

EMI@

EMI@

2

1 CS1USB3_TX0_C_P

2

1 CS2USB3_TX0_C_N

RS3 @ 0_0402_5% 1

CMMI21T-900Y-N

4

4 3

1

LM2
RS62@0_0402_5%

RS7 @ 0_0402_5% 1

LM3

1

1

4

WCM-2012-900T_4P
RS82@0_0402_5%

2

1 2

SM070003K00

1

2

4 3

1

<PV>LM3 change PN.

B

USB3RXDP0_C

3

2

USB3RXDN0_C

USB20_P0_C

2

2

Part Number = SM070003Y00

3

USB20_N0_C

EMI@

4

1

RS1 @ 0_0402_5% 1

CMMI21T-900Y-N

1

LM1

RS2 @ 0_0402_5%

2

4 3

SM070003K00

1

2

3

2

2

C D

USB3TXDN0_C_R

<EC>

<30> USB_ON#

USB3RXDN0_C 1 1
USB3RXDP0_C 2 2
USB3TXDN0_C_R 4 4
USB3TXDP0_C_R 5 5

+5VALW

W=100mils

USB_ON# 1 2 RS4

@ESD@
DM1 SCA00000U10

1

YSLC05CH_SOT23-3

SC300002800

DM2

ESD@

3 3

8

IP4292CZ10-TB

1

CS3

0.1U_0402_16V7K

2

@

0_0402_5%

2 USB20_N0_C
3 USB20_P0_C

109 USB3RXDN0_C

9 8 USB3RXDP0_C
7 7 USB3TXDN0_C_R
6 6 USB3TXDP0_C_R

USB3.0 need support 2.5A
change USB PWR SW SA00005VN00
low active

1
2
3
4

US1

8

GND VOUT

7

VIN VOUT

6

VINVOUT

G547I2P81U_MSOP8

EN FLG

5

+USB_VCCA

RS5 1 @2 USB_OC0# 0_0402_5%

USB2.0/USB3.0 port 1

+USB_VCCA

USB3TXDP0_C_R
USB3TXDN0_C_R

USB20_P0_C
USB20_N0_C

USB3RXDP0_C
USB3RXDN0_C

W=100mils

1

@

CS4

2

1000P_0402_50V7K

JUSB1

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND

2

D- GND

6

SSRX+ GND

4

GND GND

5

SSRX- GND

ACON_TARA4-9K1311
CONN@

CS5

E

1

1

0.1U_0402_16V7K

10
11
12
13

CS6

2

47U_0805_6.3V6M

USB_OC0# <10,9>

2

USB2.0 port x 2

3 3

+5VALW

W=100mils

1

CS10

0.1U_0402_16V7K

2

USB_ON#

4 4

@RS101

0_0402_5%

2

US2

1

GND VOUT

2

VIN VOUT

3 6

VIN VOUT

4

EN FLG

G547I2P81U_MSOP8

+USB_VCCB

8
7

5

W=100mils

RS9 1 @ 2 USB_OC1#

0_0402_5%

Security Classification

Issued Date

TH IS SH E ET OF ENG I NEE RI N G DR A W IN G IS TH E P ROP R IE T AR Y P ROP ERT Y O F COM PAL E L EC T RON I CS , IN C. A N D C ON TAI NS CONFIDENTISSAiL
AN D T RAD E S ECR ET IN FO RMATI ON . THIS S HEE T MAY N O T BE T R AN S FER ED FR O M TH E CU S TOD Y OF T H E COM PET E NT DIVI SION OF R&D
DE P ART MEN T EX CEP T AS A U THO R IZE D BY C O MP A L EL E CT R ONI CS, IN C. N EIT HE R THI S SH E ET N O R T HE I N FO R MAT ION IT CO NT AIN S

A

B

MA Y BE US ED BY OR D IS CLOSE D TO AN Y TH IRD P ART Y W IT H OUT PRI O R WRI TTE N CON SEN T OF C O MP A L EL E CT R ONI CS, IN C.

<10> USB20_N2

<10> USB20_P2

<10> USB20_N1

USB_OC1# <10>

<10> USB20_P1

Compal Secret Data

2013/02/26 2015/07/08

C D

@RS13

1

EMI@

4

@RS14
@RS15

1

EMI@

4

@RS16 0_0402_5%

Deciphered Date

0_0402_5%

1

LM4

WCM-2012-900T_4P

LM5

WCM-2012-900T_4P

2

1

4 3

2

1

0_0402_5%
0_0402_5%

2

1

1

4 3

1 2

2

2

Part Number = SM070003Y00

3

2

2

Part Number = SM070003Y00

3

<PV>LM4,LM5 change PN.

USB20_N2_C

USB20_P2_C

USB20_N1_C

USB20_P1_C

USB20_P2_C
USB20_N2_C

USB20_P1_C
USB20_N1_C

Title

USB 3.0/2.0 conn

ze Document Number

B

+USB_VCCB

E-T_6916K-Q12N-00L

12

11
10

9
8
7
6
5
4
3
2
1

Compal Electronics, Inc.

LA-B972P

Sheet

E

12
11
10

9
8
7
6
5
4
3
2
1

JUSB2

14

G2

13

G1

Rev

24 of 54Date: Thursday, March 20, 2014

0.1

5

CA1 1

INT_MIC RA3 1

D D

+3VS

CPVDD

2

CA17

4.7U_0603_6.3V6K

1

C C

<6> HDA_SYNC_AUDIO
<6> HDA_RST_AUDIO#

+3VS

<19> D_MIC_DATA
<19> D_MIC_CLK

<SI> QA2 change from NMOS to BJT
<PV> QA2 change toQA1.

HDA_RST_AUDIO# 3 1

Part Number = SB000008E10

<30> EC_MUTE#

2 1K_0402_5% CA4 1

+MIC2_VREFO

2

1 @

RA6

4.7K_0402_5%

CA11 1 2 10U_0603_6.3V6M
CA14 1 2 2.2U_0402_6.3V6M

CA15 1 2 2.2U_0402_6.3V6M

PLUG_IN# RA101 2 39.2K_0402_1% SENSEA

+1.5VS +DVDD

1

RA25

2.2K_0402_5%

B

2 2

E

C

QA1

MMBT3904WH_SOT323-3

1 2

DA3
CH751H-40PT_SOD323-2

2 4.7U_0402_6.3V6M INT_MICR_C
2 4.7U_0402_6.3V6M INT_MICL_C

12

PD#

12

PCBeep

ECBeep

B B

SBBeep

<30> EC_BEEP#

<9> HDA_SPKR

Close to Codec pin12

MUTE_LED_CTR

HDA_RST_AUDIO#

1K_0402_5%
RA26

10K_0402_5%
RA11

1

2 PC_BEEP_R
CA31
.1U_0402_16V7K

1 2
CA33
.1U_0402_16V7K

4

UA1

20

MIC1_R

19

MIC1_L

18

MIC2_R

17

MIC2_L

31

MIC1_VREFO_L

30

MIC1_VREFO_R

29

MIC2_VREFO

23

LINE2_R

24

LINE2_L

16

MONO_OUT

12

PC_BEEP

ALDO_CAP
ACPVEE

CPVDD
CBN
CBP

PCBEEP

10

SYNC

11

RESET#

7

LDO3-CAP

34

CPVEE

36

CPVDD

35

CBN

37

CBP

2

GPIO0/DMIC_DATA

3

GPIO1/DMIC_CLK LDO1_CAP

13

SENSE_A AVSS1

14

SENSE_B AVSS2

47

PDB Thermal Pad

ALC3227-CG_MQFN48P_6X6

Power down (PD#) power stage for save power
0V: Power down power stage

3.3V: Power up power stage

RA19
47K_0402_5%
1 2

12

RA20
10K_0402_5%

DVDD_IO

SPK_OUT_R+

SPK_OUT_R-

SPK_OUT_L+

SPK_OUT_L-

HPOUT_R

HPOUT_L

SDATA_OUT

SDATA_IN

LINE1_L
LINE1_R

SPDIFO/GPIO2

LDO2_CAP

1 2 PC_BEEP CA34

.1U_0402_16V7K

DVDD

AVDD1
AVDD2

PVDD1
PVDD2

BCLK

JDREF

VREF

27

DVSS

1
9

26
40

41
46

45 SPK_R+
44 SPK_R-

42 SPK_L+

43 SPK_L-

33 HPOUT_RRA4
32 HPOUT_LRA5

5

SDATA_IN RA7

8
6
22

21

48
15 JDREF RA9 2

28 AVREF CA16 2
39
25

38

4

49

CA18 1
CA19 1

GNDA

MIC_JD

3

+DVDD
+DVDD_IO

+5VS_AVDD
+1.5VS_AVDD

+5VS_PVDD

InternalSpeaker

1

2 75_0402_1% HP_OUTR

1

2 75_0402_1% HP_OUTL

1

2 22_0402_5%

1 20K_0402_1%

1 .1U_0402_16V7K

2 10U_0603_6.3V6M
2 10U_0603_6.3V6M

2 RA29 1 100K_0402_5%

@

AVREF

GNDA

CA24 1 2 2.2U_0402_6.3V6M

INT_MIC_R

1 @ 2

RA2

0_0603_5%

Place near Pin1 Place near Pin9

Headphone

HDA_SDOUT_AUDIO <6>
HDA_SDIN0 <6>

HDA_BITCLK_AUDIO <6>

GNDA

SPK_R- EMI@ RA13 1
SPK_R+ EMI@ RA14 1
SPK_L- EMI@ RA15 1
SPK_L+ EMI@ RA161

CA10

4.7U_0603_6.3V6K

CA9

.1U_0402_16V7K

2 600ohms @100MHz 1A

1

1

2

Place near Pin26

GNDA

+5VS_PVDD

10U_0603_6.3V6

M

CA20

.1U_0402_16V7K

CA21

.1U_0402_16V7K

1

1

2

2 1

Internal SPK

<DB>Relace RA13/RA14/RA15/RA16 close to UA1
<PV>RA13~RA16 change to SM010008A00, 30-ohm.

2
2
2
2

wide 40 MIL

SPK_R-_CONN
SPK_R+_CONN

2

3

DA1@ESD@
SCA00002900
L03ESDL5V0CC3-2_SOT23-3

1

Reserve for ESD request.

2

3

1

GNDA

DA4
YSLC05CH_SOT23-3
SCA00002900
ESD@

SPK_L-_CONN

SPK_L+_CONN

2

3

DA2@ESD@
SCA00002900
L03ESDL5V0CC3-2_SOT23-3

1

HP_OUTR_R HP_OUTL_R

2

3

1

2

CA5

.1U_0402_16V7K

CA6

10U_0603_6.3V6

M

1

1

2 2

LA4

1 2

FBMA-L11160808601LMA10T_2P

Main:SM010007Z00
2nd:SM01000BU00

Place near Pin40

LA6

1 2

FBMA-L11-201209601LMA20T_2P

CA23

10U_0603_6.3V6MCA22

2

2

1

PBY160808T-300Y-N_2P
PBY160808T-300Y-N_2P
PBY160808T-300Y-N_2P
PBY160808T-300Y-N_2P

DA6
YSLC05CH_SOT23-3
SCA00000U10
@ESD@

CA7

.1U_0402_16V7K

CA8

10U_0603_6.3V6

M

1

1

2

2

+5VS+5VS_AVDD

CA12

.1U_0402_16V7K

1

2

+5VS

600ohms @100MHz 2A
Main:SM01000NS00
2nd:SM01000EE00

2

3

DA8
YSLC05CH_SOT23-3
SCA00002900

1

Delete ESD Diode

Jack detect
Combo Mic = High
Normal HP = Low

+1.5VS+DVDD_IO+DVDD+3VS

1 2

LA3
SUPPRE_ KC FBMA-10-100505-101T 0402
PCB Footprint =R_0402

+1.5VS+1.5VS_AVDD

1 2

LA5

CA13

4.7U_0603_6.3V6K
SUPPRE_ KC FBMA-10-100505-101T 0402

PCB Footprint =R_0402

2

1

GNDA

MUTE_LED_CTR

10K_0402_5%

RA12

SPK_R-_CONN
SPK_R+_CONN
SPK_L-_CONN
SPK_L+_CONN

1

1

2

2

220P_0402_50V7K

220P_0402_50V7

K

@EMII@ C123

@EMII@ C124

MIC_JD INT_MIC

1 2

RA18

CA32

10U_0603_6.3V6

M

22K_0402_5%

2

1

GNDA

12

220P_0402_50V7

1

5

1

2

K

+MIC2_VREFO

3

4

1

2

220P_0402_50V7

K

@EMII@ C125

12

MUTE_LED <26>

Q4B
2N7002KDW_SOT363-6

JSPK1

1

1

2

2

345

3 GND
4 GND

E-T_3703-Q04N-11R

CONN@

@EMII@ C126

RA17

2.2K_0402_5%

6

COMBO AUDIO JACK

RA27 1 @ 2 0_0402_5%

RA28 1 @ 2 0_0402_5%

1
CA402@EMI@
.1U_0402_16V7K

1 2

CA38 @EMI@

A A

.1U_0402_16V7K

1
CA392@EMI@
.1U_0402_16V7K

1 2
CA29 EMI@
.1U_0402_16V7K

1
CA302EMI@
.1U_0402_16V7K

GNDA

5

Delete ESD Diode

4

3

INT_MIC

HP_OUTL

HP_OUTR

RA24

22K_0402_5%

Security Classification

Issued Date

THIS SH EET OF ENG INEE RING D RAW ING IS THE PR OPRI ETAR Y PROP ERTY OF CO MPA L EL ECTRO NICS , INC. AND CON TAIN S CONF IDENTIAL
AND TRA DE SECR ET INFO RMATI ON. THIS SH EET MA Y NO T BE TRA NSF ERE D FR OM THE CUS TODY OF THE CO MPET ENT D IVISION OF R& D
DEP ARTM ENT E XCEP T A S A UTHOR IZED B Y C OMP AL EL ECTR ONICS , INC. NE ITHER THIS SH EET NOR THE IN FORM ATIO N IT CONT AINS
MAY BE U SED BY OR DISCL OSE D TO A NY TH IRD PARTY WITH OUT PRIO R W RIT TEN CONS ENT OF COMPA L ELE CTRO NICS , INC.

EMI@

RA21 1 2 BLM15AG601SN1D_2P

EMI@

RA221 2 BLM15AG601SN1D_2P

EMI@

RA23 1 2 BLM15AG601SN1D_2P

<PV>RA21~23 change to
Main : SM01000II00

12

2nd : SM01000I000

J

2013/01/04 2015/01/04 T itle

HPR, HPL, 15mil Keep30mil

CA35

100P_0402_50V8

CA37

10P_0402_50V8JCA36

10P_0402_50V8

J

1

1

1

2

2

2

@EMII@

@EMII@

@EMII@

GNDA GNDAGNDAGNDA

Compal Secret Data

Deciphered Date

JHP1

GNDA

3
6
1
2

4

5

SINGA_2SJ-E960-001F

CONN@

INT_MIC_R

HP_OUTL_R

HP_OUTR_R
PLUG_IN#

Pin6 an d Pin5
Normal OPEN

Compal Electronics,Inc.

Size Document Number

C

2

AUDIO ALC3227-CG
LA-B972P

Sheet 25 of 54Date: Thursday, March 20, 2014

1

Rev

0.1

Touch pad conn

KSI0

ESD@

<30> KSI[0..7]

<30> KSO[0..17]

1 100P_0402_50V8JC193 2

<30> CAP_LOCK#

<25> MUTE_LED

KSI7
KSI6
KSI5

KSI4
KSI3
KSI2

KSI1
KSI0

KSO17
KSO16
KSO15

KSO14
KSO13
KSO12
KSO11
KSO10

KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1

KSO0

CAP_LOCK#R203
MUTE_LED R207 1

WL_WHIT
WL_AMBER

+5VS

1

+5VS

Keyboard conn

KSI1
KSI7

KSI6
KSO9

KSI4
KSI5

KSO0
KSI2

KSI3
KSO5

KSO1
KSI0

KSO2
KSO4

KSO7
KSO8

KSO6
KSO3

KSO12
KSO13

KSO14
KSO11

KSO10
KSO15

KSO16

2 3.3K_0402_5%
2 3.3K_0402_5%

KSO17

CONN@ JKB1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

ACES_50690-0320N-P01

G1
G2

33
34

<30> TP_CLK
<30> TP_DATA

TP_CLK
TP_DATA

2

3

1

+3VALW

DM5
YSLC05CH_SOT23-3
SCA00000U10

@ESD@

JTP1

1

1

2

2

3
4

5

3 G1

6

4 G2

HB_A090420-SAHR21
CONN@

+5VALW+5VALW

1

@EMI@
C134
470P_0402_50V8J

2

Q20B

2N7002KDW_SOT363-6

13 2

White

R158

3.3K_0402_5%

5

4

WLAN_ON_LED# <30><30> WLAN_OFF_LED#

Amber

WL_AMBER WL_WHIT

Security Classification

Issued Date

TH IS SH E ET OF E NG I NEE RIN G DR A W IN G IS TH E P ROP R IE T ARY P ROP ERT Y O F COM PAL E L EC T R ON I CS , INC. A N D C ON T AI NS CONFIDENTISSAiL
AN D T RAD E S ECR ET IN FO RMATI ON . TH IS S HEE T MAY N O T BE T R AN S FER ED FR O M TH E CU S TOD Y OF TH E CO MPE T ENT DI VISIO N OF R& D
DE P ART MEN T EX CEP T AS A U THO R IZ E D BY C O MP A L EL ECT R ONI CS, IN C. N EIT HE R THI S SH E ET N O R THE I N FO R MA T ION IT CO NT AINS
MA Y BE US ED BY OR D IS CLOSE D TO AN Y TH IRD P ART Y W IT H OUT PRI O R WRI TTE N CON SEN T OF C O MP A L EL ECT R ONI CS, INC.

2013/02/26 2015/07/08

16 2

R157

3.3K_0402_5%

Q20A

2

1

2N7002KDW_SOT363-6

Compal Secret Data

Deciphered Date

Title

ze Document Number

B

LA-B972P

1

CC122 CC123

100P_0402_50V8J 2 100P_0402_50V8J

2

ESD@ ESD@

Compal Electronics,Inc.

KB/TP

Sheet

CAP_LOCK#
MUTE_LED

1

Rev

26 of 54Date: Thursday, March 20, 2014

0.1

A

B

C D

E

Powert Button Connector

+3VL

1 1

remove at SI phase

2 2

@EMI@

1

C166

2

<30> LID_SW#

<30> ON/OFF#

0.1U_0402_16V7K

LID_SW# 2
ON/OFF# 3

JPWR1

1

1
2

5

3 G1

4

6

4 G2

HB_A090420-SAHR21
CONN@

1

2

ON/OFF# 2

LID_SW#

CC124

100P_0402_50V8J

ESD@

R215

100K_0402_5%

<30> PWR_LED#

remove at SI phase

+3VL

1

<6,9> SATA_LED#

remove at SI phase

PWR_LED#

SATA_LED#

@ESD@

CS20

@ESD@

CS19

1

0.1U_0402_16V7K

2

220_0402_5%

1

0.1U_0402_16V7K

2

R2744220_0402_5%

2

R2743

2

1 1

<SI> Del New Lid SWconn

White

LTW-110DC5-C_WHITE

White

LTW-110DC5-C_WHITE

LED10

3

LED9

3

+3VALW

21 1

+3VS

2

3 3

+FAN_POWER

40mil

1

2

2.2U_0603_6.3V6K

<30> EN_DFAN1

4 4

A

CE22

+5VS

B

CE25

2.2U_0603_6.3V6K

1 2

UE3

1

VEN

2

VIN

3

VO

4

VSET

APE8873M SOP8P

8

GND

7

GND

6

GND

5

GND

Security Classification

Issued Date

TH IS SH E ET OF ENG I NEE RI N G DR A W IN G IS TH E P ROP R IE T AR Y P ROP ERT Y O F COM PAL E L EC T RON I CS , IN C. A N D C ON TAI NS CONFIDENTISSAiL
AN D T RAD E S ECR ET IN FO RMATI ON . THIS S HEE T MAY N O T BE T R AN S FER ED FR O M TH E CU S TOD Y OF T H E COM PET E NT DIVI SION OF R&D
DE P ART MEN T EX CEP T AS A U THO R IZE D BY C O MP A L EL E CT R ONI CS, IN C. N EIT HE R THI S SH E ET N O R T HE I N FO R MAT ION IT CO NT AIN S
MA Y BE US ED BY OR D IS CLOSE D TO AN Y TH IRD P ART Y W IT H OUT PRI O R WRI TTE N CON SEN T OF C O MP A L EL E CT R ONI CS, IN C.

2013/02/26 2015/07/08

C D

FAN conn

<30> FAN_SPEED1

Compal Secret Data

Deciphered Date

+3VS

12

RE50
10K_0402_5%

1

CE24

0.01U_0402_16V7K

2

+FAN_POWER

40mil

Title

ze Document Number

B

CONN@ JFAN1

1

1

2

2

3

3

4

GND

5

GND

ACES_85204-0300N

Compal Electronics, Inc.

PWRBTN/FAN

LA-B972P

Sheet

E

Rev

27 of 54Date: Thursday, March 20, 2014

0.1

5

OF R& D

4

3

2

1

+3VS +3VS

TPM1.2

D D

Screw Hole

H3 H4
H_2P8 H_ 2P8

HOLEA HOLEA

C

@

@

1

1

<7> CLK_P CI_TPM
<30,7> LPC _FRAM E#

<21,23, 30,32,8> PLT_RST#

<30,9> SERIRQ

H5
H_2P8

HOLEA

@

@

1

H14 H1
H_2P8 H_ 2P8

HOLEA HOLEA

@

@

1

1

<30,7> LPC_AD0
<30,7> LPC_AD1
<30,7> LPC_AD2
<30,7> LPC_AD3

H6 H7
H_2P8 H_ 2P8

HOLEA HOLEA

1

0.1U_0402 _16V4Z

1 @ 2

+3VS

R1383

@

H2
H_2P8

HOLEA

@

0.1U_0402 _16V4Z
@

@

@

1

1

1

C1060

2

1

1

LPC_AD0 26
LPC_AD1 23
LPC_AD2 20
LPC_AD3 17

LPC_ FRAME # 22
PLT_RST# 16
SERIRQ 27

4.7K_0402 _5%

H12 H17
H_2P8 H_ 2P8

HOLEA HOLEA

@

1

C1059

2

2 1

@

0.1U_0402 _16V4Z
2

@

R1414
0_0402_5%

1

C1058

@
U70

19

VDD24VDD

LAD0
LAD1
LAD2
LAD3

SLB 9656 T T1.2

21

LFRAM E# GPIO2
LRESET#
SERIRQ

15

CLKRUN#

7

PP

GND

4

11

H18
H_2P0

HOLEA

@

1

1

@
C1061

*

0.1U_0402 _16V4Z

VDD

10

TPM

GND18GND25GND

H19
H_2P0X2P 5

HOLEA

@

1

5

VSB

TESTB1/B ADD

XTALI

2

28

LPCPD#

9 BADD 1
8

TEST1

@R141 3 0_0402 _5%

14

XTALO

13

LCLK

@
2 T48 PAD
6

GPIO

T47 PAD

@
1

NC

3

NC

12

NC

SLB 9656 TT 1.2

H9
H_5P0

HOLEA

@

1

Securi ty Class ification

Issue d Date

THIS S HEET OF ENGI NEERING DRAW ING I S THE PROPRI ETARY PR OPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONFIDE NTI
AND TRADE SE CRET INFORMATIO N. THIS S HEET MAY NOT BE TRANSF ERED F ROM TH E CUSTOD Y OF THE COMPETE NT DIVISION
DEPARTME NT EXCE PT AS AUTHO RIZED B Y COMPAL ELECT RONICS, INC. NEITHER THIS SHE ET NOR THE INFORMA TION IT CONT AINS
MAY BE US ED BY OR DI SCLOSED TO A NY THIRD P ARTY W ITHOUT PRI OR WRI TTEN CONSEN T OF COMPAL ELE CTRONICS, INC.

2PLT_R ST#

@

H10
H_5P0

HOLEA

1

2013/ 02/26

<30,45, 46> EC_S MB_CK 1
<30,45, 46> EC_S MB_DA 1

H11
H_5P0

HOLEA

@

1

+3V_ GSEN

@

Compa l Secret Data

ACCELEROMETER

RH411 1 @ 2

+3VL

SI# 2012.04.10 Change ACCEL_INT# to INT1

+3V_ GSEN

EC_S MB_CK 1 4
EC_S MB_DA 1 6

2 @ R208 1

10K_0402_ 5%

1

@ R227

0_0402_5%

@R209

0_0402_5%

21 2

@

Deciphe red Date

H16

H15

H_5P0

H_5P0

HOLEA

HOLEA

@

1

1

2015/ 07/08

H13
H_5P0

HOLEA

1

0_0402_5%

@
U25

1

Vdd_IO

SCL/SPC
SDA/SDI /SDO

7

SDO/SA0

8

CS

2

NC

3

NC

HP3D C2TR

FD3

1

FIDUCIAL_ C40M80 FID UCIAL_C4 0M80 FIDUCIAL_ C40M80 FIDUCIA L_C40M8 0

+3V_ GSEN

+3V_ GSEN

@ RH503
0_0402_5%

2 1

@

DH8

1 2

ACCEL_IN T#_R

CH751H-4 0PT_SOD 323-2

0.1U_0402 _16V7K

FD2

1

+3V_ GSEN

1

C231

2

@

@

9

INT2

11

INT1

14

VDD

5

GND

12

GND

10

RES

13

RES

15

RES

16

RES

FD4

@ @ @ @

1

Compal Electronics, Inc.

Title

LED/Screwhole

ASL

Document Number

ize

LA-B972P

Date: Thursday , Ma rch 20, 2014 Sheet 28 of 54

ACCEL_IN T# <9>

1

C232
10U_0603_ 6.3V6M

2

FD1

1

Rev

0.1

C

B B

A A

5

4

3

2

1

5

Use 0 ohm for m aterial shortage

If Vp-p small tha n 50mV
change L4106 to 0 ohm

+IVDDO_1 .8V

L4106

BLM15P D600SN1D_2P

1 2

1

2

10U_0603_6.3V6M

CRT@ C4111

VGA_HPD

1 0.1U_ 0402_16V7K PCH_DPC_C_P0 26
1 0.1U_ 0402_16V7K P CH_DPC_C_N0

1 0.1U_ 0402_16V7K PCH_DPC_C_P1 29
1 0.1U_ 0402_16V7K PCH_DPC_C_N1 30

C4121 CRT@

0.1U_0 402_16V7K

2

1 DDI1_ AUX_C_DP 20

2

1 DDI1_ AUX_C_DN 19

C4122 CRT@

0.1U_0 402_16V7K
DDI1_AUX _DP
DDI1_AUX _DN

+RXIVDD_ 1.8V +RX VCC_1.8V

PCSDA

PCSCL

<PV> Add R4121 by vend er r eco mmand.

1

2

18P_0402_50V8J

CRT@

1

1

2

2

CRT@ C4115

1U_0402_6.3V6K

Note: Place c lose pin 2 2,15,31,32

CRT@ CRT@

22_0402_5%

+3VS

R4102

4.7K_ 0402_5%
1 @ 2
1 @ 2

R4103

4.7K_ 0402_5%

UT5

40

HPD

RX0P

27

RX0N

RX1P
RX1N

RXAUXP
RXAUXN

18

DCAUXP

17

DCAUXN

25

AVCC

31

AVCC

22

41.6mA

PVCC

24

47.3mA

DVDD18

32

6.158mA

ASPVCC

43

PCSDA

42

PCSCL

+HDMI_5 V_OUT

1 2

R4121 10 K_0402_5%

CRT@

0.1U_0402_16V4Z

CRT@ C4103

1

1

R4100

2

2

1

2

DDCSCL

DDCSDA

PWDNB

37

1

1

2

2

1U_0402_6.3V6K

CRT@ C410 8

LDO input

+3VS

<8> DDI 1_AUX_DP
<8> DDI 1_AUX_DN

+3VS

XTALOUT_6 513 @ XTALIN_6 513

1

@

C4134

2

18P_0402_50V8J

+3VS_OVD D+3VS

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CRT@ C4101

CRT@ C4110

+3VS_IVD D33

R4108 2 CRT@ 1 1M_ 0402_5%
R4104 2@ 1 100K_ 0402_5%

R4113 2@ 1 100K_0402_ 5%

R4114 2 1 1M_ 0402_5% CR T@

PCSDA
PCSCL

R4120 1 2 0 _0402_5%

L2N700 2LT1G_SOT23 -3 4.7K_0 402_5%

R4127
1M_04 02_5%

X4100 @

27MHZ_1 0PF_X3G027 000BA1H-U

3

OUT GND

2

GND IN

Note: Place c lose pin 38, 39

1

2

10U_0603_6.3V6M

CRT@ C4100

CRT@ C4 123 2
CRT@ C4 119 2

CRT@ C4 120 2
CRT@ C4 124 2

+HDMI_5 V_OUT

12

12

CRT@ CRT@
R4123 R41 26

4.7K_ 0402_5% 4.7K_0402_ 5%

Note: need ex ternal PU to 2K ~ 10K

CRT@

+5VS

G

2

3 1 VGA_HP D

D

S

12

Q4100 R4122

@ CRT@

Crystal

4
1

@

C4135

1 0_06 03_5%R4110 2

short@

D D

CPU DDI1

(2-Lane only)

C C

B B

R4109 2

short@

1 0_06 03_5%

<4> PCH_D PC_P0
<4> PCH_D PC_N0

<4> PCH_D PC_P1
<4> PCH_D PC_N1

<8> DDI 1_HPD

+RXVCC_1 .8V

1

1

2

2

0.1U_0402_16V4Z

CRT@ C4104

CRT@ C4112

ISPSCL _R
ISPSDA_ R

+3VS_IVD D33

22_0402_5%

R4101

+3VS_OVD D

13

48

OVDD

OVDD

4.2mA 100.5mA

IT6513FN

0.1U_0402_16V4Z

36

IVDD3335IVDD33

4

+IVDDO_1 .8V

+IVDDO_1 .8V

Note: Depend on
Project, if Vp-p small
the 50mV chan ge to 0
ohm

+RXIVDD_ 1.8V

Pin38,39 LDO output +IV DDO_ 1.8 V.

12

46

44

39

1.52mA

IVDD

IVDD14IVDD

IVDD

IVDDO38IVDDO

MCUVDDH

MCURSTN

URDBG
ISPSCL

ISPSDA

VGADDCCLK
VGADDCSDA

VSYNC
HSYNC

65.5mA56.95mA

VDDC

IORP

IOGP

IOBP

NC/VGADETEC T

RSET

0.293mA

VDDA

COMP

XTALIN

XTALOUT

PAD

IT6513 FN_QFN48_6X6

49

CRT@

3

Use 0 ohm for m aterial s hortag e

BLM15P D600SN1D_2P

1 2

Rated current 500mA, DC0.1ohm Rated current 500mA, DC0.1ohm

+RXIVDD_ 1.8V +IVDDO_1 .8V +DAC_1. 8V

L4107

CRT@

1

1

2

2

C4106 CRT@

C4105

0.1U_0402_16V4Z

@

4.7U_0603_6.3V6K

L4108

BLM15P D600SN1D_2P

1 2

CRT@

Note: Depend on
Project, if Vp-p small
the 50mV chan ge to 0
ohm

Note: Place c lose pin 24

1

1

1

2

2

2

C4113 CRT@

C4125 CRT@

C4114 CRT@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Note: Place c lose pin 1 2,14,44, 46

+HDMI_5 V_OUT

1

MCURSTN

@ T 4101
ISPSCL _R

ISPSDA_ R

VSYNC
HSYNC

+DAC_1. 8V

1

R4118 CRT@ 100_0402 _1%

CRT@

1 2C4 133

0.1U_0 402_16V4Z

C4116 @

2 0. 1U_0402_1 6V4Z

@ T 4102

RP410 2

CRT@

1 8

7

2
3

6 CR T_CLK

4 5

CRT_DATA

22_080 4_8P4R_5%

Note: ISPSCL/ISPSDA for F/W update

R_out & B_out can bes wapped .

CRT_R

CRT_G

CRT_B

@ T4104

2

+DAC_1. 8V

1

Pin 41_V GADE TEC T is n ot us ein IT651 3.

2

C4137 CRT@

0.1U_0402_16V4Z

+HDMI_5 V_OUT

2.2K_0402_5%

2.2K_0402_5%

12

12

CRT@

R4125

CRT@

R4124

CRT_CLK
CRT_DATA

CRT_G

CRT_B

876

5

CRT@

RP410 0
75_080 4_8P4R_1%

123

4

1

2

CRTEMI@

<MV > EM I fi ne t une Pi - filiter to 60- ohm and 6.8pf .

1 2 CRT@

CT27 0 .1U_04 02_16V4Z

HSYNC

CT25 1 2 0.1U_0 402_16V4Z

VSYNC

45

47

28
15

16
23

21
3

4

10

11

9

8

41 VGAD ETECT

5

7

6

34 X TALIN_651 3

33 XTALO UT_6513

1

1

2

2

C4107 CRT@

1U_0402_6.3V6K

Note: Place c lose pin 10

RGB Tr ace mus t less than 2 000mils.
CRB1.0 use 33o hm@100Mhz Bea d

PBY160 808T-600Y- N

1

PBY160 808T-600Y- N

1 2 CRTEMI@

PBY160 808T-600Y- N

1 2 CRTEMI@

6.8P_0402_50V8C

6.8P_0402_50V8C

6.8P_0402_50V8C
1

1

C4126

C4127

2

2

CRTEMI@

CRTEMI@

+HDMI_5 V_OUT

1

UT2 CRT@
74AHCT1G1 25GW_SO T353-5

2

4

A Y

OE#

5

G P

3

CRT@

1

2

C4109 CRT@

0.1U_0402_16V4Z

L4103

L4104

L4105

C4128

SM010 005N00

+HDMI_5 V_OUT

2

A

2

C4136 CRT@

0.1U_0402_16V4Z

@ESD@

DT4

SC300 001G00

6

CRT_B_2

6.8P_0402_50V8C

1

C4130

2

CRTEMI@

CRT_HSYNC_ 1

I/O4

5

VDD

4

I/O3 I/O1

AZC099 -04S.R7G_ SOT23-6

DT3

6

I/O4 I/O2

5

VDD

4

I/O3 I/O1

AZC099 -04S.R7G_ SOT23-6

CRT_R_2CRT_R

CRT_G_2

6.8P_0402_50V8C

1

C4131

2

CRTEMI@

@ESD@

SC300 001G00

+HDMI_5 V_OUT

+HDMI_5 V_OUT

CRT_DATA

CRT_R_2 CRT_G_2

+HDMI_5 V_OUT

2 CRTEMI @

6.8P_0402_50V8C

1

C4129

2

CRTEMI@

CRT@
RT26

2 1

10K_0 402_5%

5

1

4 CRT_ VSYNC_1

Y

OE#

G P

UT4 CRT@
74AHCT1G1 25GW_SO T353-5

3

3

I/O2

2

GND

1

3

2

GND

1

W=40 mil s

1 CRT@ 2

LT14 3 3_0402_5 %

1 CRT@ 2

LT15 3 3_0402_5 %

CRT_VSYNC _2CRT_HSYNC_ 2

CRT_CLK

CRT_B_2

CRT Connector

T4103

@

CRT_DATA

CRT_HSYNC_ 2
+HDMI_5 V_OUT

CRT_VSYNC _2

1

CRT_CLK

0.1U_0402_16V4Z

C4132

@

2

10P_0 402_50V8J

1

JCRT1

6

11

1
7

12

2
8

13

3
9

14

4

10

16

G

17

15

G

5

C-H_13 -12201560C P
CONN@

DC06000 6E00

CRT_HSYNC_ 2

CRT_VSYNC _2

1

1

@

@

CT28

CT26

2

2

10P_040 2_50V8J

A A

Secur ityCl assification

Issued D ate

THIS SHEE T OF ENG INEE RING D RAWI NG IS T HE PROPRI ETA RY PROP ERTY OF C OMPAL ELEC TRONIC S, INC. AND CONTA INS CONFI DENTI AL
AND TRAD E SECRE T INFOR MATION. THI S S HEET MAY NOT BE TRANS FER ED FROM THE C USTODY OF THE COM PETENT DI VISION O F R& D
DEPA RTMENT EXCEPT AS A UTHORI ZED BY C OMPAL E LECTRO NICS, INC. NEI THER THIS SHEE T NOR TH E INF ORMATI ON IT CONTAI NS

5

4

3

MAY BE USE D BY OR D ISCL OSED TO AN Y THIRD PARTY WITHOU T PRI OR W RITTEN CONSE NT OF COMP AL ELE CTRONI CS, I NC.

2011/06/30

2

Compal Secret Data

Decip hered Date

2013/0 6/30

Compal Electronics,Inc.

Title

eDP toCRT

Size Document Number

Custom

LA-B972P

1

Sheet 29 of 54Date: Thurs day, Mar ch 20, 2014

Rev

0.1

5

PV# 2013.01.29 Add CK4 for ESD protection

ESD@

D D

+3VA LW _EC

+3VA LW _EC

+3VS

RP7 1

C C

RK36 1

+3VS

B B

A A

CK4

2 1 PLT_RST #

0.1U_04 02_16V7 K

2

RK15

1

CK9

8
7

2

346

5

2.2K_0804_8P4R _5%

@

1 330K_0 402_5%

2

0.1U_04 02_16V7 K

EC_SMB_C K1
EC_SMB_D A1
EC_SMB_C K2
EC_SMB_D A2

2 10K_04 02_5% EC_SCI#

<28,45, 46> EC_S MB_CK 1
<28,45, 46> EC_S MB_DA 1

<18,32, 7> EC_SMB _CK2
<18,32, 7> EC_SMB _DA2

EC_RST #

@RK49
@RK50

<8> PM_ CLKR UN#

<21> EC _PCIE_W AKE#

EC_SMB_C K1
EC_SMB_D A1

EC_S MB_C K2 RK39 1 short @ 2 0_0402_5%
EC_S MB_D A2 RK40 1 2 0_0402_5%

<8> PM_SLP_S3#
<8> PM_SLP_S5#

<8> SU SACK #
<21> MINI1_ LED#

<8> PCH_SUSW ARN #

<32> GP U_T HERMAL_DET#

100K_0402_5%

2 PC H_DPWROK

1

100K_0402_5%

2 PC H_PWRO K

1

<35,53, 9> DGPU_PW R_EN

<7,9> EC_KBRST#

<28,7> LPC_FRAME#

<28,7> LPC_AD3
<28,7> LPC_AD2
<28,7> LPC_AD1
<28,7> LPC_AD0

<7> CLK_PCI_LPC

<21,23, 28,32,8> PLT_RST#

<26> KSI[0..7]

<26> KSO[0..17]

short@

<6> EC_+1.05VS_ PG
<19> EC_INVT_PW M

<27> FAN _SPEED1

<8> PM_SLP _SUS#

<21> E51TXD_P8 0DAT A

<21> E51RXD_P8 0CLK

<8> PCH_PWR OK

<44> AC_LED #

4

+3VL

short@ RK57

1 2

0_0603_5%

<28,9> SERIRQ

<9> EC_SCI#

1 @ 2 PM_CLKRUN#_ R
RK59 1 2 0_0402_5%
RK61 short@ 0_0402_5%

PM_SLP_ S3#
PM_SLP_ S5#
SUSA CK#

PCH_SUSWAR N#

GPU_THERMAL _DET #

10K_0402_5%

0.1U_0402_16V7K
CK2

1

2

EC_KBRST #
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_PCI_LPC
PLT_RST#
EC_RST #
EC_SCI#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

EC_SMB_C K2_R
EC_SMB_D A2_R

FAN_SPE ED1
PM_SLP_ SUS#
E51TXD _P80D ATA
E51RXD_ P80CLK
PCH_PW ROK

AC_LED#

+3VA LW _EC

12

RK18

+3VA LW _EC

0.1U_0402_16V7K

1

2

KB9012QF-A3 _LQFP 128_ 14X1 4
Part Number = SA00004O B30

CK3

UK1

1

GAT EA20 /GP IO00

2

KBRS T#/ GPIO 01

3

SERI RQ

4

LPC_ FRAME#

5

LPC_ AD3

7

LPC_ AD2

8

LPC_ AD1

10

PC & MISC

LPC_ADLL0

12

CLK_ PCI_ EC

13

PCIR ST#/GPIO05

37

EC_R ST#

20

EC_S CII#/GPIO 0E

38

GPIO 1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GP IO20

40

KSO1/GP IO21

41

KSO2/GP IO22

42

KSO3/GP IO23

43

KSO4/GP IO24

44

KSO5/GP IO25

45

KSO6/GP IO26 Matrix

46

KSO7/GP IO27

47

KSO8/GP IO28

48

KSO9/GP IO29

49

KSO10/G PIO 2A

50

KSO11/G PIO 2B

51

KSO12/G PIO 2C

52

KSO13/G PIO 2D

53

KSO14/G PIO 2E

54

KSO15/G PIO2 F

81

KSO16/G PIO4 8

82

KSO17/G PIO 49

77

EC_S MB_C K1/ GPI O44

78

EC_S MB_D A1/ GPI O45

79

EC_SMB_CK2/GPIOSS46

80

EC_S MB_D A2/ GPI O47

6

PM_SLP_S 3#/ GPIO04

14

PM_SLP_S 5#/ GPIO07

15

EC_S MI#/ GPI O08

16

GPIO 0A

17

GPIO 0B

18

GPIO 0C

19

GPIO 0D

25

EC_I NVT_PW M/GP IO1 1

28

FAN_SPEE D1/ GPIO14

29

EC_P ME#/ GPIO15

30

EC_T X/G PIO1 6

31

EC_R X/G PIO1 7

32

PCH_PW ROK/ GPIO 18

34

SUSP _LED #/G PIO 19

36

NUM_ LED# /GPIO1A

122

XCLK I/GP IO5 D

123

XCLK O/G PIO5 E

+3VA LW _EC

LK1
FBMA-L1 1-160808-800LMT_ 0603

1 2 + EC_VCCA

9223396111

EC_VDD/VCC

EC_VDD/VCC

PS2 Interface

Int.K/B

M Bus

GND/GND

112435

+3V_EC_ VDD

67

125

EC_VDD0

EC_VDD/VCC

EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC

PWMOutput

BAT T_T EMP/ AD0/ GPIO 38

ADP_ I/AD 2/G PIO 3A

ADInput

IMON /AD5 /GP IO4 3

DAOutput

SPI Device InteVrCfaINce

DAC_BRIG /GPIO3C

EN_D FAN 1/GP IO3D

CHG VADJ /GPIO3F

EC_M UTE#/GP IO4 A

CAP_ INT#/GP IO4C

CPU1.5V_S3_GATE/GP XIOA00

WO L_EN /GPXIOA0 1

ME_EN/GP XIO A02

SPI Flash ROM

ENBK L/AD 6/G PIO 40

PECI _KB9 30/ AD7/GPIO41

BAT T_C HG_LED#/GPIO52

CAPS _LED #/GPIO53

GPIO

PW R_LE D#/G PIO5 4

BAT T_L OW_LED #/GP IO55

PM_SLP_S4# /GP IO59

EC_R SMRS T#/ GPX IOA 03
EC_L ID_O UT# /GP XIO A04
PROCHOT _IN /GPX IOA 05

H_PR OCH OT# _EC/ GPXIOA06

VCOUT 0_PH/GPXIOA0 7

GPO

GPIO

GND/GND

GND/GND

94

BKOFF#/ GPX IOA0 8

PBT N_OUT#/GPXIOA0 9

PCH_APW ROK /GPXIOA 10

SA_P GOO D/GPXIO A11

EC_O N/G PXIO D02

ON/ OFF/GPX IOD0 3

GPI

LID_ SW#/GP XIOD04

PECI _KB9 01 2/G PXIO D0 7

AGND/AGND

GND/GND

GND 0

69

20mil

113

ECAG ND 2 1

FBMA-L1 1-160808-800LMT_ 0603

3 2

15"
UMA
RK13

DIS
RK13

Board ID control
<DB>RK13 change to 160K ==>for 15"DIS
<DB>RK13 change to 12K ===>for 15"UMA

EN_D FAN 1 <27>
DGPU_HOLD_RST# <32,9>
SYS_ PWROK < 8>

EC_M UTE# <25>

PM_SLP_ S4# <8>

WL AN_O FF_L ED# <26>
TP_CLK <26>

TP_DAT A <26>

EC_P ME# <23,9>

WL _PWR EN_E C <21>

EC_SPI_SO <7>
EC_SPI_SI <7>
EC_SPI_CLK <7>
EC_SPI_CS0# <7>

PW R_LE D# <27>
WL AN_O N_LE D# <26>
SYSO N <40,48>
BT_ ON_EC <21>
PCH_DPW ROK <8>

<SI> Update Pin119 and Pin120 net name

TOUCH_O N# <19>

EC_FB_C LAMP_TGL_R EQ# <9>

AOAC_PME # <8>
BAT _CHG _LED <44>
CAP_LOC K# <26>

CK10 2 1 100P_0402 _50V8J ECA GND

H_PECI <4>

1

CK7

0.1U_04 02_16V7 K

2

ECAGND

RK12 sh ort@

2 1

0_0402_5%

GPIO 0F

BEEP #/G PIO 10

GPIO 12

ACOFF/G PIO1 3

AD1/ GPIO 39

AD3/ GPIO 3B
AD4/ GPIO 42

IREF /GPIO3E

USB_ EN#/ GPIO 4B

EAPD /GPIO4D

TP_ CLK/ GPIO 4E

TP_ DAT A/GP IO4F

0_PH/GPXIOD00

SPID I/GPIO5B

SPID O/GPIO5 C

SPIC LK/G PIO 58

SPIC S#/G PIO 5A

FST CHG /GPIO50

SYSO N/G PIO5 6
VR_O N/G PIO5 7

AC_I N/GPXIOD01

SUSP #/GPXIO D05

GPXIOD06

V18R

LK2

ECAG ND <44>

21
23
26
27

63
64
65
66
75
76

68

70

71
72

83

84
85
86

87

88

97

98

99

109

119

120

126

128

73
74
89
90
91

92

93
95
121
127

100
101
102
103

104
105

106
107
108

110
112
114
115

116

117
118

124

+3VA LW _EC

1 2

DIS@

+3VL

RK13

560K_0402_1%

SD034560380

B/I#
BOARD_ID
ADP_I

ADP_ID
ENBKL

+1.05V_ VS_PG _PW R

PM_SLP_ S4#
WL AN_O FF_L ED#

TP_CLK
TP_DAT A

EC_P ME#
HDA_SDO

VCIN0_PH

TOUCH_O N#
EC_FB_C LAMP_TGL_R EQ#
AOAC_PME #

CAP_LOC K#
PW R_LE D#

SYSO N
BT_ ON_EC
PCH_DPW ROK

PCH_RSMR ST#
VCIN1_PH

H_PROCHOT#_EC
MAINPWON
EC_BKOF F#
PBT N_OUT#
PCH_PW R_EN
USB_ON#

EC_ACIN
EC_O N
ON/OFF#
LID_SW #
SUSP #
NMI_DBG#
EC_PECI RK34 1

+V18R

1

CK17

4.7U_06 03_6.3V6K

2

1 2

RK6
100K_0402_5%

BOARD_ID

UMA@
RK13

56K_0402_1%
SD034560280

GPU_HOT # <53>
EC_BEEP # <25>
TS_GPIO_EC <19>
AC_A ND_CHAG <45>

B/I# <44,45>

ADP_I <44,46>

ADP_ID <44>

ENBK L <8>

short@ RK53 1 2 0_0201_5%

HDA_SDO <6>

VCIN0_PH <44 >

PCH_RSMR ST# <8>

VCIN1_PH <44 >

MAINP WO N <47>
EC_BKOF F# <18>
PBT N_OUT# <8>

PCH_PW R_EN <42>
USB_ON# <24>

EC_O N <47>

ON/OFF# <27>
LID_SW # <27>

SUSP # <40,48,49, 52,5 5>

2

43_0402_1%

DB SI PV

12k ohm 20K ohm

160k ohm

240k ohm 330k ohm 560kohm

EC_ACIN 2

<44> H_PROCHOT#_EC

+1.05V_ VS_PG _PW R <49>

EC_LID_ OUT# <9>

1

14"

DB

15K ohm

ACIN <44,45, 46,8>

D

13

G

S

1
2
3
4

SI PV

PROCHOT # <4,44>

+3VA LW

1 47K_0402_5%LID_SW # RK44 2

MV

33K ohm

56K ohm

DK1

<50> VR_ HOT #

<PWR>

EC_FB_C LAMP_TGL_R EQ# R K60 1 @DIS@ 2 10 K_0402_5%

<PV>N15 V don,t support GC6,RK60 c hange to @DIS@.

TP_CLK RK2 1 2 4.7K_0402_5%

TP_DAT A RK4 1 2 4.7K_04 02_5%

UMA

RK13

DIS

RK13

CH751H-40PT_SOD323-2

1

VR_H OT# 1 2

H_PROCHOT#_EC 2

PCH_PW R_EN 8
PLT_RST# 7
EC_O N 6
EC_ACIN 5

100K_0804_8P4R _5%

0ohm

130k ohm 200k ohm 270k ohm 430k ohm

1 100P_0 402_50V 8JCK8 2

short@ RK17

0_0402_5%

QK1

2N7002_SOT23- 3

RP8

27K ohm

+3VA LW _EC

MV

43Kohm

+3VL

+3VA LW _EC

NMI_DBG#

5

4

1 2

DK2

CH751H-40PT_SOD323-2

NMI_DBG#_CPU <9>

SecurityClassification

Issued Date

THIS SHEE T OF ENGIN EERING DRAWING IS THE PROPRIETARY PROPER TY O F CO MPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRAD E SEC RET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED F ROM T HE C USTODY OF T HE COMPETENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR T HE INFORMATIO N IT CONTAINS
MAY BE USED BY OR DISCLO SED TO AN Y T HIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRO NICS, INC.

3 2

2011/06/29 2011/06/29

Compal SecretData

Deciphered Date

Compal Electronics, Inc.

Titl e

EC ENE-KB9012

Size Docume nt Numb er

Custom

LA-B972P

Rev

Sheet 30 of 54Date: T hursda y, March 20,2014

1

0.1

5

4

3

2

1

BOM control

Platform Silego P/N CompalPN 25MHz(A) 32.768KHz 24MHz(B) 27MHz 8MHz Remark

D D

Intel ULTUMA SLG3NB3375V SA00006RE00 1 1 1 X X GCLKUMA@

Intel ULT Dis SLG3NB3374V SA00006RD00 1 1 1 1 X GCLKDIS@

Base on A32 32.768KHz use 10ppm, G‐CLK 25MHz X'TAL use10ppm.

+RTCBATT

RG106GCLK@

+1.05VS+3VGS +LAN_VDD_3V3 +3VL +3VALW

GCLKDIS@

Depop if GCLK

C C

B B

with UMA

0.1U_0402_10V7K

1

1

CG47

2

2

0.1U_0402_10V7K

GCLK@
CG48

GCLK@

1

CG49

2

0.1U_0402_10V7K

Place close
to UG2.8

GCLK@ 1GCLK@

1

CG50 CG51

CLK_X1

2 2

0.1U_0402_10V7K

2

GCLK@ 1

CG59

18P_0402_50V8J

1

0.1U_0402_10V7K

Check PowerRail

S CRYSTAL 25MHZ 12PF +-10PPM FL2500048
SJ10000G600

YG1GCLK@

4

3

GND OUT

IN

2

GND

22U_0805_6.3V6M

CLK_X2

2

GCLK@

CG58

18P_0402_50V8J

1

+LAN_VDD_3V3

<SI> Ch ange CG58, CG5 9 to 18pf reco mmend by vender

330_0402_5%

2 1

1

CG52

2

GCLK@

+3VL
+3VALW

+3VGS

+1.05VS

S IC SLG3NB3374VTR TQFN 16PCRYSTAL

GCLKDIS@

GCLK_VRTC 10

CLK_X1 1
CLK_X2 16

UG2

VBAT VDD_RTC_OUT

15

+V3.3A

2

VDD

11

VDDIO_27M 27MHz

8

VDDIO_25M_A 25MHz_A

3

VDDIO_25M_B 25MHz_B
XTAL_IN

XTAL_OUT

SA00006RD00

UG2 GCLKUMA@
SA00006RE00

S IC SLG3NB3375VTR TQFN 16P CRYSTAL

GND1GND2GND

4

7

13

14

9

32kHz

12 VGA_X1_R
6 LAN_X1_R
5 PCH_X1_R

3

GND4

17

Reserve CG57 for vendor
Place close to RG109

RTC_VOUT

PCH_RTCX1_R

2 1

+RTCVCC

12

RG107 @
0_0402_5%

2.2U_0603_6.3V6

1

K CG53

2

CPU 32.768M(P.6)
Place RG114 close to YC1

@

1 2

RG114 0_0402_5%

GCLKDIS@

RG109 1 2 33_0402_5%

RG1111 2 33_0402_5%

GCLK@

RG1131 2 0_0402_5%

GCLK@

CG54
5P_0402_50V8C

2 1

GCLK@

VGA_X1_R

CG57
5P_0402_50V8C

@

GCLK@

PCH_RTCX1 <6>

XTALIN_R
XTLI_R

CPU_CLK 24M(P.7)
Place RG113 close to YC2

CPU_XTAL24_IN <7>

<SI> Ch ange RG109 to 33 ohm recom mend by vender

VGA 27M(P.32)
Place RG110 close to YV1

GCLKDIS@

1 2

RG110 0_0402_5%

1 2

RG112 GCLK@ 0_0402_5%

LAN 25M(P.23)
Place RG112 close to YL1

RG3, RG7,RG 8, RG6 0ohm_0402
for isolat ed CLK tail

XTALIN <32>
XTLO <23>

<CPURTC>
<GPU>
<LAN>
<CPU>

A A

Security Classification

Issued Date

THI S SHE ET OF E NG INE ER ING DRA WI NG I S THE P ROP RI ETA RY P RO PE RTY OF COM PA L EL EC TRO NIC S, I NC. AN D C ON TAI NS CONFIDENTISSAiL
AN D TR AD E S EC RET INF ORM ATI ON . TH IS SHE ET MAY NOT BE T RAN SF ER ED FROM THE CU ST ODY OF T HE COM PE TEN T DIV ISIO N OF R&D
DE PA RTME NT EX CEP T A S AU THO RIZ ED BY CO MPA L E LE CTR ONI CS, INC . N EITHE R THI S SHE ET NO R THE I NFO RM ATI ON IT CONTA INS

5

4

3

MA Y BE U SE D BY OR DISCL OSE D TO ANY THIR D PAR TY W IT HOU T PRI OR W RI TTE N CO NS EN T OF CO MP AL E LE CTR ON ICS , INC.

2013/06/10 2014/07/01

Compal SecretData

Deciphered Date

2

Compal Electronics, Inc.

Title

GCLK

ze Document Number

LA-B972P

Date: Thursday, March 20,2014

1

Sheet 31 of 54

Rev

0.1

1

2

3

4

5

+3VGS

UV1A

<10> PEG_HTX_C_GRX_P7
<10> PEG_HTX_C_GRX_N7
<10> PEG_HTX_C_GRX_P8

<CPU>

A A

<10> PEG_GTX_ C_HRX_P7
<10> PEG_GTX_ C_HRX_N7
<10> PEG_GTX_ C_HRX_P8

<CPU>

B B

<10> PEG_GTX_ C_HRX_N8
<10> PEG_GTX_ C_HRX_P9
<10> PEG_GTX_ C_HRX_N9
<10> PEG_GTX_ C_HRX_P10
<10> PEG_GTX_ C_HRX_N1 0

<CPU>

<7> CLK_PCIE _GPU
<7> CLK_PCIE_ GPU#

Differential signal

C C

<21,23,28,30,8> PLT_RST#

<30,9> DGPU_HOLD_RST#

EC or CPU control

D D

<10> PEG_HTX_C_GRX_N8
<10> PEG_HTX_C_GRX_P9
<10> PEG_HTX_C_GRX_N9
<10> PEG_HTX_C_GRX_P10
<10> PEG_HTX_C_GRX_N1 0

PEG_GT X_C_HRX_P7 CV1 DIS@ 1
PEG_GT X_C_HRX_N7 CV2 DIS@ 1
PEG_GT X_C_HRX_P8 CV3 DIS@ 1
PEG_GT X_C_HRX_N8 CV4 DIS@ 1
PEG_GT X_C_HRX_P9 CV5 DIS@ 1
PEG_GT X_C_HRX_N9 CV6 DIS@ 1

PEG_GTX_C_HRX_P10 CV7 DIS@ 1
PEG_GTX_C_HRX_N10 CV8 DIS@ 1

DGPU_HOLD_RST# 2

1 DIS@ 2 PEX_T STCLK_OUT

RV26 200_0402_1% PEX_TSTCLK_OUT#

1 2 PEX_TE RMP

RV27 DIS@ 2.49K_0402_1%

RV183 1

PLT_RST# 1

TC7SH08FUF_SSOP5

PEG_HT X_C_GRX_P7
PEG_HT X_C_GRX_N7
PEG_HT X_C_GRX_P8
PEG_HT X_C_GRX_N8
PEG_HT X_C_GRX_P9
PEG_HT X_C_GRX_N9
PEG_HT X_C_GRX_P10
PEG_HT X_C_GRX_N10

2 0.22U_0402_6.3V6K PEG_GTX_HR X_P7 AC9
2 0.22U_0402_6.3V6K PEG_ GTX_HR X_N7 AB9
2 0.22U_0402_6.3V6K PEG_ GTX_HR X_P8 AB10
2 0.22U_0402_6.3V6K PEG_ GTX_HR X_N8 AC10
2 0.22U_0402_6.3V6K PEG_ GTX_HR X_P9 AD11
2 0.22U_0402_6.3V6K PEG_ GTX_HR X_N9 AC11
2 0.22U_0402_6.3V6K PEG_ GTX_HR X_P10 AC12
2 0.22U_0402_6.3V6K PEG_ GTX_HR X_N10 AB12

PLT_RST_VGA#
GPU_CLKREQ#_R

+3VGS +3VGS

2

@ 0_0402_5%

5

UV11

P

B

4

Y

A

G

3

DIS@

12

RV184
10K_0402_5%
@

12

RV186
10K_0402_5%
DIS@

AG6
AG7

AF7

PEX_RX1

AE7

PEX_RX1 _N

AE9

PEX_RX2

AF9

PEX_RX2 _N

AG9

AG10

PEX_RX3 _N

AF10

PEX_RX4

AE10

PEX_RX4 _N

AE12

PEX_RX5

AF12

PEX_RX5 _N

AG12

PEX_RX6

AG13

PEX_RX6 _N

AF13

PEX_RX7

AE13

PEX_RX7 _N

AE15

AF15
AG15
AG16

AF16
AE16
AE18

AF18
AG18
AG19

AF19
AE19
AE21

AF21
AG21

AG22

PEX_TX0

AB13

PEX_TX4

AC13

PEX_TX4_N

AD14

PEX_TX5

AC14

PEX_TX5_N

AC15

PEX_TX6

AB15

PEX_TX6_N

AB16

PEX_TX7

AC16

PEX_TX7_N

AD17
AC17
AC18
AB18
AB19
AC19
AD20
AC20
AC21
AB21
AD23
AE23

AF24
AE24
AG24
AG25

AE8

PEX_REFCLK

AD8

PEX_REFCLK_N

AF22

PEX_TSTCLK_O UT

AE22

AF25

AC7

PEX_RST _N

AC6

PLT_RST_VGA#

PEX_RX0
PEX_RX0 _N

PEX_RX3

NC
NC
NC
NC
NC
NC
NC
NC

NC

NC
NC
NC
NC
NC
NC

NC

PEX_TX0_N

PEX_TX1

PEX_TX1_N

PEX_TX2

PEX_TX2_N

PEX_TX3

PEX_TX3_N

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

PEX_TSTCLK_O UT_N
PEX_ TER MP

PEX_ CLKR EQ_N

N15V-GM
DIS@

Part 1 of 5

GPIO

PCIEXPRESS

TESTCLK

I2C DACA

XTAL_O UTBUFF

SI 11/05 change RV182.1
change to +3VGS from GPU_PWR_EN

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

DACA_HSYNC

DACA_VSYNC

DACA_RED

DACA_BLUE

DACA_GREEN

DACA_VREF
DACA_RSET

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

JTAG_TRST_N

TES TMODE

I2CA_SC L
I2CA_SD A

I2CB_SC L
I2CB_SD A

I2CC_SC L

I2CC_SD A

I2CS_SC L
I2CS_SD A

XTAL_SSIN

XTAL_O UT

XTAL_IN

NC
NC
NC

<7,8> GPU_C LKREQ#

C6
B2
D6
C7
F9
A3
A4
B6
A6
F8
C5
E7
D7
B4
B3
C3
D5
D4
C2
F7
E6
C4

AE3
AE4

AG3
AF3
AF4

AE2
AF2

AE5 GPU_JTAG_TCK
AE6
AF6
AD6
AG4 GPU_JTAG_TRST

AD9 T ESTMODE

B7
A7

C9
C8

A9
B9

D9
D8

A10

C10 XTALOUT RV25 1 DIS@ 2 10K_0402_5%
B10
C11

AB6
D10

E9

GPU_GPIO0

GPU_GPIO6
GPU_GPIO8

GPU_GPIO9
NVVDD_PWM_VID

GPU_PW R_LEVEL# RV191 1 DIS@ 2 0_0402_5%
NVVDD_PSI

T1402
T1403
T1404

RV14 1 DIS@ 2 2.2K_0402_5%

I2CA_SCL

RV15 1 DIS@ 2 2.2K_0402_5%

I2CA_SDA
I2CB_SCL

I2CB_SDA
I2CC_SCL

I2CC_SDA
I2CS_SCL

RV21 1 DIS@ 2 2.2K_0402_5%

I2CS_SDA

RV22 1 DIS@ 2 2.2K_0402_5%

Interna l Therm al Sen sor

XTALSSIN RV23 1 DIS@ 2 10K_0402_5%

XTAL_O UT
XTALIN

RV58 1 DIS@ 2 10K_0402_5%

+3VGS

RV182

1 2

@ CV17

0.1U_0402_16V7K

#9/2 , Add RV191 between.

GPU_PWR_LEVEL# and GPU_THERMAL_DET#

NVVDD_PWM_VID <53>

GPU_T HERMAL_DET# <30>

NVVDD_PSI <53>

#8/19 ,N15V-GM didn't support GC6,
unpop QV13 ,QV14.

#08/22,u nused I 2C change to pull‐down .

+3VGS

10K_0402_5%
DIS@

CV12

0.01U_0402_16V7K

1

DIS@

2

2

G

1

2

1 3

D

QV10 DIS@
2N7002K_SOT23-3

1 @ 2

RV188 0_0402_5%

S

GPU_CLKREQ#_R

12

RV187
10K_0402_5%
@

CHECK!!

DIS@ RV36
GPU_JT AG_TCK 1
TESTMODE 2
GPU_JT AG_TRST 3
GPU_CLKREQ#_R 4

10K_0804_8P4R_5%

8
7
6
5

I2CS_SCL

I2CS_SDA

XTALIN

+3VGS

CV9

XTALDIS@

XTALIN <31>

GPU_PW R_LEVEL# RV62 1 DIS@
GPU_GPIO6 RV43 1 DIS@

NVVDD_PSI RV44 1 DIS@
GPU_GPIO8 RV46 1 DIS@

GPU_GPIO9 RV48 1 DIS@

GPU_GPIO0 RV49 1 DIS@ 2 10K_0402_5%

DIS@ RV16

I2CB_SDA 1 8
I2CB_SCL 2 7
I2CC_SDA 3 6
I2CC_SCL 4 5

2

1 6

2N7002KDWH_SOT363-6
RV20 1 @ 2 0_0402_ 5%

1

XTALIN
10P_0402_50 V8J

1

2

27MHZ 10PF 5YEA27000102IF50Q3

1

2.2K_0804_8P4R_5%

#08/22,u nused I 2C change to pull‐down .

+3VGS

5

QV2B DIS@

4 3

2N7002KDWH_SOT363-6

RV13 1 @ 2 0_0402_5%

QV2A DIS@

PU AT EC SIDE, +3VS AND 4.7K

XTALDIS@

RV24 1 2 10M_0402_5%

XTALDIS@
YV1

3

GND

GND

2 4

3 XTAL_OUT

XTALDIS@

CV10

2

100K_0402_5%

2

10K_0402_5%

2

10K_0402_5%

2

10K_0402_5%

2

10K_0402_5%

1

2

EC_SMB_CK 2 <18,30,7>

EC_SMB_DA 2 <18,30,7>

10P_0402_50 V8J

<PV>CV9,CV10 change to 10pf.

Security Classification

IssuedDate

THI S SH EE T OF E NG INE ER ING DR AW IN G IS TH E PR OPR IE TAR Y PRO PE R TY OF COM PA L EL EC TRO NIC S, IN C. AN D CO NTA INS CONFI DENT IAL
AN D T RA DE S EC RE T I NFO RM AT ION . TH IS SH EET M AY NOT BE T RA NS FE R ED FRO M THE CU STO DY OF T HE COM PE TE NT DI VIS ION OF R &D
DE PA RTM ENT EX CE PT AS A UT HOR IZ ED BY CO MPA L EL EC TRO NIC S, IN C. NE ITH ER TH IS S HE ET N OR T HE I NFO RM ATI ON IT CO NTA IN S

1

2

MA Y BE USE D BY OR D IS CLO SE D TO AN Y T HIR D PAR TY W ITHO UT P RIO R WR ITTE N CO NSE NT OF C OM PAL EL EC TRO NIC S, I NC .

3

2011/07/12 2012/07/01

Compal Secret Data

DecipheredDate

Title

Siz e Document Number

Custom

4

Date: Thursday, March 20, 2014 Sheet 32 of 54

Compal Electronics, Inc.

N15V-GM PCIE/DAC/GPIO

LA-B972P

5

Rev

0.1

1

2

3 4

5

UV1C

AC3

IFPA_TXC

AC4

IFPA_TXC_N

Y4

IFPA_TXD0

Y3

A A

B B

C C

D D

IFPA_TXD0_N

AA3

IFPA_TXD1

AA2

IFPA_TXD1_N

AB1

IFPA_TXD2

AA1

IFPA_TXD2_N

AA4

IFPA_TXD3

AA5

IFPA_TXD3_N

AB5

IFPB_TXC

AB4

IFPB_TXC_N

AB3

IFPB_TXD4

AB2

IFPB_TXD4_N

AD3

IFPB_TXD5

AD2

IFPB_TXD5_N

AE1

IFPB_TXD6

AD1

IFPB_TXD6_N

AD4

IFPB_TXD7

AD5

IFPB_TXD7_N

N4

IFPC_AUX_I2CW_SCL

N5

IFPC_AUX_I2CW_SDA_N

T2

IFPC_L0

T3

IFPC_L0_N

T1

IFPC_L1

R1

IFPC_L1_N

R2

IFPC_L2

R3

IFPC_L2_N

N2

IFPC_L3

N3

IFPC_L3_N

P3

IFPD_AUX_I2CX_SCL

P4

IFPD_AUX_I2CX_SDA_N

V3
V4

IFPD_L0

U3

IFPD_L0_N

U4

IFPD_L1
IFPD_L1_N

T4

IFPD_L2

T5
R4

IFPD_L2_N

R5

IFPD_L3
IFPD_L3_N

J2
J3

IFPE_AUX_I2CY_SCL

N1

IFPE_AUX_I2CY_SDA_N

M1

NC

M2

NC

M3

NC

K2

NC

K3

NC

K1

NC

J1

NC

NC

H3
H4

M4

IFPF_AUX_I2CZ_SCL

M5

IFPF_AUX_I2CZ_SDA_N

L3

NC

L4

NC

K4

NC

K5

NC

NC

J4
J5

NC

NC

NC

N15V-GM

Part 3 of5

LVDS / TMDS

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

BUFRST_N

THERMDN

THERMDP

GENERAL STRAPSERIAL

ROM_CS_N

ROM_SCLK

ROM_SI

ROM_SO

IFPAB_RSET

IFPC_RSET
IFPD_RSET

NC_G1
NC_G2
NC_G3
NC_G4
NC_G5
NC_G6
NC_G7

NC_V1
NC_V2
NC_V5
NC_V6

NC_W1
NC_W2
NC_W3
NC_W4

D1 STRAP0
D2 STRAP1

E4 STRAP2
E3 STRAP3

D3 STRAP4
C1

NC

D11 RV28 1 2 100K_0402_5%
E12

F12

D12 ROM_CS RV29 1
C12 ROM_SCLK
B12 ROM_SI
A12 ROM_SO

AA6
T6
U6
K6

NC

AD10

NC

AD7

NC

B19

NC

G1
G2
G3
G4
G5
G6
G7

V1
V2
V5
V6

W1
W2
W3
W4

E10

NC

F10

NC

DIS@

DIS@

STRAP0 <39>
STRAP1 <39>
STRAP2 <39>

STRAP3 <39>
STRAP4 <39>

2 10K_0402_5%

ROM_SCLK<39>
ROM_SI<39>
ROM_SO <39>

+3VGS

Security Classification

IssuedDate

TH IS SH E ET OF ENG I NEE RI N G DR A W IN G IS TH E P ROP R IE T AR Y P ROP ERT Y O F COM PAL E L EC T RON I CS , IN C. A N D C ON TAI NS CO NF IDENT IA L
AN D TR A DE SEC RET IN FORMA TI ON. THIS SHE E T MAY NOT B E T R ANS F ER E D F R OM T H E C US T ODY O F TH E C O MP E TEN T DI VISIO N O F R&D
DE P ART MEN T EXC EPT AS A U THO R IZE D BY CO MPA L E LEC T RON ICS , IN C. NE IT HE R T HIS S H EE T N O R T H E IN F ORM ATI O N IT C ONT AI NS

1

2

MA Y BE US ED BY OR D ISC LO SE D TO AN Y T HI RD PA RT Y W ITH OUT P R IO R W RI T TEN C ONS EN T OF CO MP A L EL E CT R O NI C S, IN C.

2011/07/12 2012/07/01

3 4

Compal Secret Data

Deciphered Date

Title

N15V-GM LVDS/HDMI/DP/THM

SizeDocument Number

B

Compal Electronics,Inc.

LA-B972P

5

Rev

0.1

33 of 54Date: Thursday, March 20, 2014 Sheet

1 2 3 4 5

+1.5VGS

B26

AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25

AF26
AF27

AA22
AB23
AC24
AD25
AE26
AE27

AA14
AA15

C25
E23
E26
F14
F21
G13
G14
G15
G16
G18
G19
G20
G21
H24
H26

J21
K21
L22
L24
L26

M21

N21
R21
T21
V21

W2 1

AA8
AA9

N6
M6

L6
F16
P22
H22

W5

F3

0.1U_0402_10V7K

CV28 DIS@

1

2

A A

+1.05VGS

Referen ce circ uit:
1uF *2

4.7uF*1
10uF*2
22uF*2

Referen ce circ uit:
1uF *2

short@

short@

RV34 1

RV45 1

4.7uF*1
10uF*2
22uF*2

2 0_0402_5%

CV70 DIS@

1

2

2 0_0402_5%

0.1U_0402_10V7K

CV75 DIS@

1

2 2

+PEX_3V3_NV

CV71 DIS@

4.7U_0603_6.3V6K

CV72 DIS@

4.7U_0603_6.3V6K

0.1U_0402_10V7K
1

1

2

2

+PEXPLL_VDD

CV76 DIS@

4.7U_0603_6.3V6K

CV77 DIS@

1U_0402_6.3V6K

1

1

2

B B

+3VGS

+1.05VGS

C C

1U_0402_6.3V6K

CV52 DIS@

4.7U_0603_6.3V6K

CV53 DIS@

1U_0402_6.3V6K

CV51 DIS@

1

1

2

CV58 DIS@

1

2

1

2

2

CV60 DIS@

CV59 DIS@

1

2 2

4.7U_0603_6.3V6K

1U_0402_6.3V6K

1

+1.05VGS

1U_0402_6.3V6K

1U_0402_6.3V6K

CV21 DIS@

0.1U_0402_10V7K

CV20 DIS@

1

2

10U_0805_6.3V6M

CV54 DIS@

1

2

10U_0805_6.3V6M

CV61 DIS@

1

2

<SI> LV1 use R_040 2foot print

#8/19,LV 1 chang e to
Z=30 oh m , RDC=0 .05
SM01000F 100

PCB Footprint = R_0402

<9> DGPU_GC6_EN

1U_0402_6.3V6K

CV22 DIS@

1

1

2

2

Referen ce circ uit:

0.1u F *2
1 uF*2

4.7uF*2
10uF*1
22uF*1

10U_0805_6.3V6M

CV55 DIS@

22U_0805_6.3V6M

CV56 DIS@

1

1

2

2

22U_0805_6.3V6M

CV63 DIS@

10U_0805_6.3V6M

CV62 DIS@

1

1

2

2

DIS@
LV1
BLM18PG121SN1D_060
3

1 2

4.7U_0603_6.3V6K

CV24 DIS@

4.7U_0603_6.3V6K

CV23 DIS@

1

1

2

2

22U_0805_6.3V6M

CV57 DIS@

1

2

22U_0805_6.3V6M

CV69 DIS@

1

2

RV47 1

short@

CV73

DIS@

CV29 DIS@

1

2

10U_0603_6.3V6M

1

2

0.1U_0402_10V7K

2 0_0402_5%

22U_0805_6.3V6M

CV26 DIS@

1

2

+PEX_3V3_NV

+PEXPLL_VDD
+GPU_SP_PLLVDD
+GPU_PLLVDD

22U_0805_6.3V6M

CV74 DIS@

1

2

+FB_PLLAVDD

+FB_CAL _PD_VDDQ D22

FB_CLAMP

FBVD DQ
FBVD DQ
FBVD DQ
FBVD DQ
FBVD DQ
FBVD DQ
FBVD DQ
FBVD DQ
FBVD DQ
FBVD DQ
FBVD DQ
FBVD DQ
FBVD DQ
FBVD DQ
FBVD DQ
FBVD DQ
FBVD DQ

FBVD DQ
FBVD DQ
FBVD DQ
FBVD DQ
FBVD DQ

FBVD DQ

FBVD DQ

FBVD DQ

FBVD DQ

FBVD DQ
PEX_IOVDDQ

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD

PEX_PLL _HVDD
PEX_PLL _HVDD

PEX_PL LVDD
PEX_PL LVDD

VID_PLLVDD
SP_PLL VDD

CORE_PLLVDD
FB_PLLA VDD
FB_PLLAVDD

FB_DLLA VDD

DACA_VDD
FB_CAL_PD_VDDQ

FB_CLAMP

Part 4 of 5

POWER

VDD_SENSE

VDD33
VDD33
VDD33
VDD33

PEX_SVDD_3V 3

IFPA_IO VDD
IFPB _IOVDD
IFPC_IOVDD
IFPD_IOVDD

IFPAB_PLLVDD
IFPAB_PLLVDD

IFPC_PL LVDD
IFPC_PL LVDD

IFPD_PL LVDD
IFPD_PL LVDD

N15V-GM

DIS@

UV1D

K10

VDD

K12

VDD

K14

VDD

K16

VDD

K18

VDD

L11

VDD

L13

VDD

L15

VDD

L17

VDD

M10

VDD

M12

VDD

M14

VDD

M16

VDD

M18

VDD

N11

VDD

N13

VDD

N15

VDD

N17

VDD

P10

VDD

P12

VDD

P14

VDD

P16

VDD

P18

VDD

R11

VDD

R13

VDD

R15

VDD

R17

VDD

T10

VDD

T12

VDD

T14

VDD

T16

VDD

T18

VDD

U11

VDD

U13

VDD

U15

VDD

U17

VDD

V10

VDD

V12

VDD

V14

VDD

V16

VDD

V18

VDD

F2
G10

G12
G8
G9

F11

NC

AB8 +PEX_3V3_NV

W6

Y6

P6
R6

H6

NC

J6

NC

V7

W7

M7

N7

R7

T7

J7

NC

K7

NC

+VGA_CORE

Power :VDD_SENSE & GND_SENSE

CV66 DIS@

CV67 DIS@

0.1U_0402_10V7K

1

2

Differential signal

4.7U_0603_6.3V6K

CV68 DIS@

1U_0402_6.3V6K

1

1

2

2

VCCSENSE_VGA

Remove IFPC_PLLVDD,IFPD_PLLVDD,IFPC_IOVDD,IFPD_IOVDD,IFPAB_PLLVDD,+DACA_VDD,IFPA_IOVDD

VCCSENSE_VGA <53>

CV65 DIS@

CV64

0.1U_0402_10V7K
1

1

DIS@

2

2

0.1U_0402_10V7K

short@1 RV30 2

0_0603_5%

+3VGS

DIS@
LV3
BLM18PG121SN1D_060
3

+1.05VGS

DG : LV3 ‐>Z=180 ohm , RDC=0.2 ohm.0603

<PV>LV3,LV4 changePN.
Main:SM01000BW00

1 2

CV82 DIS@

1

2

2nd:SM01000CC00

DG:LV4‐>Z=30 ohm , RDC=0.01ohm.0603

D D

+1.05VGS

LV4 DIS@
BLM18PG121SN1D_060

1 2

3

CV90 DIS@

0.1U_0402_10V7K

CV91 DIS@

1

2

1 2 3 5

+GPU_SP_PLLVDD

CV83 DIS@

4.7U_0603_6.3V6K

CV84 DIS@

0.1U_0402_10V7K

0.1U_0402_10V7K
1

2

+FB_PLLAVDD

CV88 DIS@

0.1U_0402_10V7K
1

1

2 2

2

22U_0805_6.3V6M

CV85 DIS@

1

1

2

2

0.1U_0402_10V7K

22U_0805_6.3V6M

CV89 DIS@

1

+1.5VGS

#7/27 Follow DG to chenge

R1591 to 40.2 ohm

DIS@

1 2 +FB_CAL_PD_VDDQ

RV50 40.2_0402_ 1%

Security Classification

IssuedDate

THI S SH EE T OF E NG INE ER ING DR AW IN G IS TH E PR OPR IE TAR Y PRO PE R TY OF COM PA L EL EC TRO NIC S, IN C. AN D CO NTA INS CONFI DENT IAL
AN D T RA DE S EC RE T I NFO RM AT ION . TH IS SH EET M AY NOT BE T RA NS FE R ED FRO M THE CU STO DY OF T HE COM PE TE NT DI VIS ION OF R &D
DE PA RTM ENT EX CE PT AS A UT HOR IZ ED BY CO MPA L EL EC TRO NIC S, IN C. NE ITH ER TH IS S HE ET N OR T HE I NFO RM ATI ON IT CO NTA IN S
MA Y BE USE D BY OR D IS CLO SE D TO AN Y T HIR D PAR TY W ITHO UT P RIO R WR ITTE N CO NSE NT OF C OM PAL EL EC TRO NIC S, I NC .

2011/07/12 2012/07/01

Compal Secret Data

DecipheredDate

4

Title

Siz e Document Number

Custom

Date: Thursday, March 20, 2014 Sheet 34 of 54

Compal Electronics, Inc.

N15V-GM POWER

LA-B972P

Rev

0.1

1 2 3 4 5

UV1E

GND
GND
GND

GND

N15V-GM
DIS@

Part 5 of 5

MULTI_ST RAP_REF0_GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND

GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

FB_CAL_PU_G ND

FB_CAL_TERM_GND

GND _SEN SE

Power on

40us < Rt < 2ms

L10
L12
L14
L16
L18
L2
L23
L25
L5
M11
M13
M15
M17
N10
N12
N14
N16
N18
P11
P13
P15
P17
P2
P23
P26
P5
R10
R12
R14
R16
R18
T11
T13
T15
T17
U10
U12
U14
U16
U18
U2
U23
U26
U5
V11

V13
V15
V17
Y2
Y23
Y26
Y5
AB7

GND

C24

B25

F6

F4

NC

F5

NC

F1 VSSSENSE_VGA

1 DIS@ 2

42.2_0402_1%

RV67

2

1 DIS@

51.1_0402_1%

RV68

2 40.2K_0402_1%

1

RV70 @

VSSSENSE_ VGA <53>

Power :VDD_SENSE & GND_SENSE

Differential signal

<53> DGPU_PWROK

#08/20 Don't support GC6,Add RV66.
Unpo p QV16,R V41,RV4 2,CV78 .

#8/19.RV70 unpop , N15V‐GM use binary mode.

Contrl by power

+1.5VGS_GPU

+1.5VS

1

DIS@ CV81

DGPU_PWROK RV66 1

10U_0603_6.3V6M

DIS@

47K_0402_5%

2

2

1

CV78 @

0.01U_0603_50V7K

2

+1.5VGS=3.6A,8vias.

J3 @

2

2

JUMP_43X 118

1

1

#8/19.QV15 change to TPS22967

+1.5V to +1.5VGS

+5VALW

QV15

1

VIN

2

3

ON

4

VBIAS

TPS22967DSGR_SON8_2X2

7

VOUT

8

VOUT

VIN

6

CT

5

GND

9

GND

<30,53,9> DGPU_PWR_EN

+1.5VGS

+1.5VGS_GPU

1

CV183

2

DIS@

100P_0402_5 0V8J

1

2

CV80
DIS@

#8/20 : N15V‐GM don't support GC6 function. UV20 unpop.

+1.05VGS=1.6A,4vias.

+1.05V_GPU

J2 @

2 1

2 1

JUMP_43X 79

+1.05VGS

+3VALW to+3VGS

+1.05V_GPU

DIS@

DIS@

+3VGS

DGPU_PWROK DIS@

+5VALW
DGPU_PWR_EN

20K_0402_5%

RV92

+1.05V to +1.05VGS

+1.05V

+3VALW

DIS@
QV12

1

VOUT1

VIN1

2

VOUT1

VIN1

3
4
5
6

7

CT1

ON1

GND

VBIAS
ON2

CT2

VIN2

VOUT2

VIN2

VOUT2

GPAD

TPS22966DPUR_SON14_2X3-D

14
13

12

CV1811 2 680P_0402_50V7K

11

CV1821 2 100P_0402_50V8J

10
9

8
15

+3VGS=0.5A,2vias.

+1.05VGS

RC370 DIS@
18_0402_5%

1 2

34

DIS@

5 Q V17B

DMN66D0LDW-7_SOT363-6

SD028180A80

RV210

DIS@

100K_0402_5%

+3VALW

12

DIS@

DMN66D0LDW-7_SOT363-6

1 6

DIS@

1

CV79

1U 6.3V K X5R 0402

10U_0603_6.3V6M

2

DGPU_PWROK 2 QV17A

AA7

GND

A2

GND

A26

GND

AB11

GND

AB14

GND

AB17

GND

AB20

GND

AB24

GND

AC2

GND

AC22

GND

AC26

GND

A A

B B

AC5

AC8
AD12
AD13
AD15
AD16
AD18
AD19
AD21
AD22
AE11
AE14
AE17
AE20

AF11
AF14
AF17
AF20
AF23

AG2
AG26

AF1

AF5
AF8

B11
B14
B17
B20
B23
B27

E11
E14
E17

E20
E22
E25

H23
H25

K11
K13
K15
K17

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND

B1

GND
GND
GND
GND
GND
GND
GND

B5

GND

B8

GND
GND

GND
GND

E2

GND
GND
GND
GND

E5

GND

E8

GND

H2

GND
GND
GND

H5

GND

DGPU_PWR_EN
+3VGS

+VGA_CORE

C C

DGPU_PWROK

+1.05VGS
+1.5VGS

D D

PV# 2013.01.08 Add +1.05VG S disc harge circu it

Security Classification

IssuedDate

THI S SH EE T OF E NG INE ER ING DR AW IN G IS TH E PR OPR IE TAR Y PRO PE R TY OF COM PA L EL EC TRO NIC S, IN C. AN D CO NTA INS CONFI DENT IAL
AN D T RA DE S EC RE T I NFO RM AT ION . TH IS SH EET M AY NOT BE T RA NS FE R ED FRO M THE CU STO DY OF T HE COM PE TE NT DI VIS ION OF R &D
DE PA RTM ENT EX CE PT AS A UT HOR IZ ED BY CO MPA L EL EC TRO NIC S, IN C. NE ITH ER TH IS S HE ET N OR T HE I NFO RM ATI ON IT CO NTA IN S

1 2 3 5

MA Y BE USE D BY OR D IS CLO SE D TO AN Y T HIR D PAR TY W ITHO UT P RIO R WR ITTE N CO NSE NT OF C OM PAL EL EC TRO NIC S, I NC .

2011/07/12 2012/07/01

Compal Secret Data

DecipheredDate

4

Title

Siz e Document Number

Custom

Date: Thursday, March 20, 2014 Sheet 35 of 54

Compal Electronics, Inc.

N15V-GM VGA CORE,GND

LA-B972P

Rev

0.1

1 2 3 4 5

PU for X16 mode

UV1B

E18

T1405

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8

MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

CLKA0#

CLKA1# M22

AA24
AA23

AD27
AB25
AD26
AC25
AA27
AA26

CLKA0 D24

CLKA1 N22

F18
E16

F17
D20
D21

F20

E21

E15
D15

F15

F13
C13

B13

E13
D13

B15
C16

A13

A15

B18

A18

A19
C19

B24
C23

A25

A24

A21

B21
C20
C21
R22
R24

T22
R23
N25
N26
N23
N24

V23

V22

T23
U22

Y24

Y22

W26

Y25
R26

T25
N27
R27

V26

V27

W27
W2 5

D23

D25

A A

B B

C C

<37> MDA0
<37> MDA1
<37> MDA2
<37> MDA3
<37> MDA4
<37> MDA5
<37> MDA6
<37> MDA7
<37> MDA8
<37> MDA9
<37> MDA10
<37> MDA11
<37> MDA12
<37> MDA13
<37> MDA14
<37> MDA15
<37> MDA16
<37> MDA17
<37> MDA18
<37> MDA19
<37> MDA20
<37> MDA21
<37> MDA22
<37> MDA23
<37> MDA24
<37> MDA25
<37> MDA26
<37> MDA27
<37> MDA28
<37> MDA29
<37> MDA30
<37> MDA31
<38> MDA32
<38> MDA33
<38> MDA34
<38> MDA35
<38> MDA36
<38> MDA37
<38> MDA38
<38> MDA39
<38> MDA40
<38> MDA41
<38> MDA42
<38> MDA43
<38> MDA44
<38> MDA45
<38> MDA46
<38> MDA47
<38> MDA48
<38> MDA49
<38> MDA50
<38> MDA51
<38> MDA52
<38> MDA53
<38> MDA54
<38> MDA55
<38> MDA56
<38> MDA57
<38> MDA58
<38> MDA59
<38> MDA60
<38> MDA61
<38> MDA62
<38> MDA63

<37> CLKA0

<37> CLKA0#

<38> CLKA1

<38> CLKA1#

Part 2 of 5

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FB_VREF_PRO BE FBA_W CK4 5
FBA_CLK 0 FBA_W CK67

FBA_CLK 0_N FBA_WC K67_ N

FBA_CLK 1
FBA_CLK 1_N

N15V-GM

DIS@

FBA_CMD1 0
FBA_CMD1 1
FBA_CMD1 2
FBA_CMD1 3
FBA_CMD1 4
FBA_CMD1 5
FBA_CMD1 6
FBA_CMD1 7
FBA_CMD1 8
FBA_CMD1 9
FBA_CMD2 0
FBA_CMD2 1
FBA_CMD2 2
FBA_CMD2 3
FBA_CMD2 4
FBA_CMD2 5
FBA_CMD2 6
FBA_CMD2 7
FBA_CMD2 8
FBA_CMD2 9
FBA_CMD3 0
FBA_CMD3 1

MEMORY INTERFACE

FBA_D QS_RN 0
FBA_D QS_RN 1
FBA_D QS_RN 2
FBA_D QS_RN 3
FBA_D QS_RN 4
FBA_D QS_RN 5
FBA_D QS_RN 6
FBA_DQS_RN7

FBA_D QS_W P0
FBA_D QS_W P1
FBA_D QS_W P2
FBA_D QS_W P3
FBA_D QS_W P4
FBA_D QS_W P5
FBA_D QS_W P6
FBA_DQS_WP7

FBA_W CK01

FBA_W CK01_N

FBA_W CK23

FBA_W CK23_N

FBA_ WC K45_ N

FBA_DEBUG0
FBA_DEBUG1

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9

FBA_D QM0
FBA_D QM1
FBA_D QM2
FBA_D QM3
FBA_D QM4
FBA_D QM5
FBA_D QM6
FBA_DQM7

C27 CMDA0
C26

Dummy

E24

CMDA2

F24

CMDA3

D27

CMDA4

D26

CMDA5

F25

CMDA6

F26

CMDA7

F23

CMDA8
G22 CMDA9
G23 CMDA10
G24

CMDA11
F27

CMDA12
G25

CMDA13
G27

Dummy

G26 CMDA15
M24 CMDA16
M23

Dummy

K24 CMDA18
K23 CMDA19
M27 CMDA20
M26 CMDA21
M25 CMDA22
K26

CMDA23
K22

CMDA24
J23

CMDA25
J25

CMDA26
J24

CMDA27
K27

CMDA28
K25

CMDA29
J27

CMDA30
J26

D19

DQMA0
D14

DQMA1
C17

DQMA2
C22

DQMA3
P24 DQMA4
W2 4 DQMA5
AA25 DQMA6
U25 DQMA7

F19 DQSA#0
C14 DQSA#1
A16 DQSA#2
A22 DQSA#3
P25 DQSA#4
W2 2 DQSA#5
AB27 DQSA#6
T27 DQSA#7

E19 DQSA0
C15 DQSA1
B16 DQSA2
B22 DQSA3
R25 DQSA4
W2 3 DQSA5
AB26 DQSA6
T26 DQSA7

D18
C18
D17
D16
T24
U24
V24
V25

F22

RV137 1 @ 2 60.4_0402_1%

J22

RV138 1 @ 2 60.4_0402_1%

CMDA0 <37>
CMDA2 <37>

CMDA3 <37>
CMDA4 <37,38>
CMDA5 <37,38>
CMDA6 <37,38>
CMDA7 <37,38>
CMDA8 <37,38>
CMDA9 <37,38>
CMDA10 <37,38>
CMDA11 <37,38>
CMDA12 <37,38>
CMDA13 <37,38>

CMDA15 <37,38>
CMDA16 <38>

CMDA18 <38>
CMDA19 <38>
CMDA20 <37,38>
CMDA21 <37,38>
CMDA22 <37,38>
CMDA23 <37,38>
CMDA24 <37,38>
CMDA25 <37,38>
CMDA26 <37,38>
CMDA27 <37,38>
CMDA28 <37,38>
CMDA29 <37,38>
CMDA30 <37,38>

DQMA0 <37>
DQMA1 <37>
DQMA2 <37>
DQMA3 <37>
DQMA4 <38>
DQMA5 <38>
DQMA6 <38>
DQMA7 <38>

DQSA#0 <37>
DQSA#1 <37>
DQSA#2 <37>
DQSA#3 <37>
DQSA#4 <38>
DQSA#5 <38>
DQSA#6 <38>
DQSA#7 <38>

DQSA0 <37>
DQSA1 <37>
DQSA2 <37>
DQSA3 <37>
DQSA4 <38>
DQSA5 <38>
DQSA6 <38>
DQSA7 <38>

+1.5VGS

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

Note: DG use 1%

DIS@

2 RV169 1 CMDA2

DIS@

2

RV170 1 CMDA18
DIS@

2

RV185 1 CMDA3
DIS@

2

RV189 1 CMDA19
DIS@

2

RV190 1 CMDA5

Mode D Command Mapping

RANK 0

Address 0..31 32..63

FBx_CMD 0 CS0#

FBx_CMD 1

FBx_CMD 2 ODT

FBx_CMD 3 CKE

FBx_CMD 4 A14 A14

FBx_CMD 5 RST RST

FBx_CMD 6 A9 A9

FBx_CMD 7 A7 A7

FBx_CMD 8 A2 A2

FBx_CMD 9 A0 A0

FBx_CMD 10 A4 A4

FBx_CMD 11 A1 A1

FBx_CMD 12 BA0 BA0

FBx_CMD 13 WE# WE#

FBx_CMD 14

FBx_CMD 15 CAS# CAS#

FBx_CMD 16 CS0#

FBx_CMD 17

FBx_CMD 18 ODT

FBx_CMD 19 CKE

FBx_CMD 20 A13 A13

FBx_CMD 21 A8 A8

FBx_CMD 22 A6 A6

FBx_CMD 23 A11 A11

FBx_CMD 24 A5 A5

FBx_CMD 25 A3 A3

FBx_CMD 26 BA2 BA2

FBx_CMD 27 BA1 BA1

FBx_CMD 28 A12 A12

FBx_CMD 29 A10 A10

FBx_CMD 30 RAS# RAS#

D D

Security Classification

IssuedDate

THI S SH EE T OF E NG INE ER ING DR AW IN G IS TH E PR OPR IE TAR Y PRO PE R TY OF COM PA L EL EC TRO NIC S, IN C. AN D CO NTA INS CONFI DENT IAL
AN D T RA DE S EC RE T I NFO RM AT ION . TH IS SH EET M AY NOT BE T RA NS FE R ED FRO M THE CU STO DY OF T HE COM PE TE NT DI VIS ION OF R &D
DE PA RTM ENT EX CE PT AS A UT HOR IZ ED BY CO MPA L EL EC TRO NIC S, IN C. NE ITH ER TH IS S HE ET N OR T HE I NFO RM ATI ON IT CO NTA IN S

1 2 3 5

MA Y BE USE D BY OR D IS CLO SE D TO AN Y T HIR D PAR TY W ITHO UT P RIO R WR ITTE N CO NSE NT OF C OM PAL EL EC TRO NIC S, I NC .

2011/07/12 2012/07/01

Compal Secret Data

DecipheredDate

4

Title

Siz e Document Number

Custom

Date: Thursday, March 20, 2014 Sheet 36 of 54

Compal Electronics, Inc.

N15V-GM MEM Interface

LA-B972P

Rev

0.1

1

Memory Partition A RANK 0

+1.5VGS

RV139

1.33K_0402_1%
DIS@

A A

RV140

1.33K_0402_1%
DIS@

CLKA0

12

RV141
162_0402_1%
DIS@

CLKA0#

#8/19 , change CLK
termination to 162 ohm.

B B

160 ohm:SD00000XP00

C C

12

12

H:Group 1
L:Group 2

+FBA_VREF0

0.01U_0402_16V7K

CV96 DIS@

1

2

<36> CLKA0
<36> CLKA0#

<36> DQSA2
<36> DQSA1

<36> DQMA2
<36> DQMA1

<36> DQSA#2
<36> DQSA#1

+FBA_VREF0

RV145
243_0402_1%
DIS@

CMDA9
CMDA11

CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4

CMDA12
CMDA27

CMDA26

CLKA0
CLKA0#

CMDA3

CMDA2
CMDA0
CMDA30
CMDA15

CMDA13

DQSA2
DQSA1

DQMA2
DQMA1

DQSA#2
DQSA#1

CMDA5

12

Rank 0

UV12 X76@

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

M7

A14
A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL
SDRAMDDR3

H5TQ2G63BFR-11C_FBGA96

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

3 4

5

MDA[0..63] <36,38>

CMDA[30..0] <36,38>

Data0~Data31

Rank 0

UV14 X76@

CMDA9
CMDA11

CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4

CMDA12
CMDA27

CMDA26

CLKA0
CLKA0#

CMDA3

CMDA2
CMDA0
CMDA30
CMDA15

CMDA13

DQSA0
DQSA3

DQMA0
DQMA3

DQSA#0
DQSA#3

12

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

M7

A14
A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL
SDRAMDDR3

H5TQ2G63BFR-11C_FBGA96

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

MDA4

E3

MDA0

F7
F2

MDA5

F8

MDA2

H3

MDA7
MDA1

H8

MDA6

G2
H7

MDA3

D7

MDA31

C3

MDA27

C8

MDA30

C2

MDA25

A7

MDA28

A2

MDA26

B8

MDA29

A3

MDA24

+1.5VGS

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

Group 0

Group 3

Mode D Command Mapping

Address

FBx_CMD0 CS0#

FBx_CMD1

FBx_CMD2 ODT

FBx_CMD3 CKE

FBx_CMD4 A14 A14

FBx_CMD5 RST RST

FBx_CMD6 A9 A9

FBx_CMD7 A7 A7

FBx_CMD8 A2 A2

FBx_CMD9 A0 A0

FBx_CMD10 A4 A4

FBx_CMD11 A1 A1

FBx_CMD12 BA0 BA0

FBx_CMD13 WE# WE#

FBx_CMD14

FBx_CMD15 CAS# CAS#

FBx_CMD16 CS0#

FBx_CMD17

FBx_CMD18 ODT

FBx_CMD19 CKE

FBx_CMD20 A13 A13

FBx_CMD21 A8 A8

FBx_CMD22 A6 A6

FBx_CMD23 A11 A11

FBx_CMD24 A5 A5

FBx_CMD25 A3 A3

FBx_CMD26 BA2 BA2

RANK 0

0..31 32..63

FBx_CMD27 BA1 BA1

FBx_CMD28 A12 A12

MDA19

E3

MDA21

F7
F2

MDA16

F8

MDA22

H3

MDA18
MDA23

H8

MDA17

G2
H7

MDA20

D7

MDA10

C3

MDA13

C8

MDA11

C2

MDA14

A7

MDA8

A2

MDA15

B8

MDA9

A3

MDA12

+1.5VGS

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

Group 2

Group 1

L:Group 0
H:Group 3

<36> DQSA0
<36> DQSA3

<36> DQMA0
<36> DQMA3

<36> DQSA#0
<36> DQSA#3

+FBA_VREF0

RV150

243_0402_1%

DIS@

CMDA5

FBx_CMD29 A10 A10

+1.5VGS

0.1U_0402_16V7K

CV97 DIS@

CV98 DIS@

2

1

D D

0.1U_0402_16V7K

2

1

Closed toUV12

L

0.1U_0402_16V7K

CV99 DIS@

2

1

1U_0402_6.3V6K

CV103 DIS@

1U_0402_6.3V6K

CV100 DIS@

2

1

1

2

2

1

CV102 DIS@

0.1U_0402_16V7K

0.1U_0402_16V7K

CV101 DIS@

1U_0402_6.3V6K

CV104 DIS@

1

1

2

2

1U_0402_6.3V6K

CV106 DIS@

1U_0402_6.3V6K

CV105 DIS@

1

1

2

2

+1.5VGS

Closed toUV14

L

CV121 DIS@

0.1U_0402_16V7K

CV122 DIS@

CV118 DIS@

0.1U_0402_16V7K

CV119 DIS@

2

2

1

1

2

2

1

1

CV123 DIS@

1U_0402_6.3V6K

2

1

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K

CV120 DIS@

0.1U_0402_16V7K

1U_0402_6.3V6K

CV125 DIS@

1U_0402_6.3V6K

CV124 DIS@

1

1

2

2

1U_0402_6.3V6K

CV127 DIS@

1U_0402_6.3V6K

CV126 DIS@

1

1

2

2

FBx_CMD30 RAS# RAS#

Security Classification

IssuedDate

THI S SHEET OF E NG INE ER ING D RA WI NG IS T HE PRO PR IET AR Y PRO PE RT Y OF CO MPA L ELE CT RO NIC S, INC. AN D CONT AINS CONFIDE NTIAL
AND TR ADE S ECR ET IN FO RMA TI ON . THIS SHEET MAY N OT BE T RA NS FER ED FROM THE C UST OD Y OF T HE CO MPE TE NT DIV ISIO N OF R&D
DEPAR TMENT EX CEPT AS A UT HO RIZ ED BY C OMPAL ELEC TR ON ICS , INC. NEIT HER THIS SH EET NOR TH E INFO RM ATION IT CONT AIN S

1

2

MAY BE USE D BY OR DI SCLOSE D TO A NY TH IRD PA RT Y WITHOUT PRIO R WR IT TEN CON SE NT OF CO MPAL ELE CT RO NIC S, INC.

3 4

2011/07/12 2012/07/01

Compal Secret Data

DecipheredDate

Title

Size Document Number

Custom

Compal Electronics,Inc.

N15V-GM VRAM ALower

LA-B972P

5

Rev

0.1

54Date: Thursday, March 20, 2014 Sheet 37 of

1

2

3

4

5

+1.5VGS

Memory Partition A RANK 0 32 bits

12

RV152

1.33K_0402_1%
DIS@

A A

RV153

1.33K_0402_1%
DIS@

12

RV154

162_0402_1%

DIS@

B B

#8/1 9 , change C LK
termina tion to 162 ohm.

C C

12

CLKA1

CLKA1#

+FBA_VREF1

0.01U_0402_16V7K

CV138 DIS@

1

2

L:Group 4
H:Group 7

<36> CLKA1
<36> CLKA1#

<36> DQSA4
<36> DQSA7

<36> DQMA4
<36> DQMA7

<36> DQSA#4
<36> DQSA#7

+FBA_VREF1

CLKA1
CLKA1#

CMDA5

RV155
243_0402_1%
DIS@

Rank 0

UV16 X76@

M8
H1

N3

CMDA9

P7

CMDA11

P3

CMDA8

N2

CMDA25

P8

CMDA10

P2

CMDA24

R8

CMDA22

R2

CMDA7

T8

CMDA21

R3

CMDA6

L7

CMDA29

R7

CMDA23

N7

CMDA28
CMDA20

T3
T7

CMDA4

M7

M2

CMDA12

N8

CMDA27

M3

CMDA26

J7
K7
K9

CMDA19

K1

CMDA18

L2

CMDA16

J3

CMDA30

K3

CMDA15

L3

CMDA13

F3

DQSA4

C7

DQSA7

E7

DQMA4

D3

DQMA7

G3

DQSA#4

B7

DQSA#7

T2
L8

12

J1
L1
J9
L9

H5TQ2G63BFR-11C_FBGA96

310mA

96-BALL
SDRAM DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0 VD D
BA1 VD D
BA2 VD D

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ/ZQ 0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

Data32~Data63

E3

MDA35

F7

MDA37

F2

MDA34

F8

MDA39

H3

MDA32

H8

MDA38

G2

MDA33

H7

MDA36

D7

MDA56

C3

MDA60

C8

MDA58

C2

MDA61

A7

MDA57

A2

MDA63
MDA59

B8
A3

MDA62

+1.5VGS

B2
D9
G7
K2

VDD

K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

Group 4

Group 7

L:Group 6
H:Group 5

<36> DQSA6
<36> DQSA5

<36> DQMA6
<36> DQMA5

<36> DQSA#6
<36> DQSA#5

+FBA_VREF1

RV162
243_0402_1%
DIS@

CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4

CMDA12
CMDA27
CMDA26

CLKA1
CLKA1#

CMDA19

CMDA18
CMDA16
CMDA30
CMDA15
CMDA13

DQSA6
DQSA5

DQMA6
DQMA5

DQSA#6
DQSA#5

CMDA5

12

Rank 0

UV18 X76@

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ 0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL
SDRAM DDR3

H5TQ2G63BFR-11C_FBGA96

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

E3

MDA52

F7

MDA49

F2

MDA53

F8

MDA50

H3

MDA54

H8

MDA48

G2

MDA55

H7

MDA51

D7

MDA44

C3

MDA40

C8

MDA46

C2

MDA41

A7

MDA45

A2

MDA43
MDA47

B8
A3

MDA42

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1
B9
D1
D8
E2
E8
F9
G1
G9

Group 6

Group 5

MDA[0..63] <36,37>

CMDA[30..0] <36,37>

Mode D Command Mapping

RANK 0

Address 0..31 32..63

FBx_CMD 0 CS0#

FBx_CMD 1

FBx_CMD 2 ODT

FBx_CMD 3 CKE

FBx_CMD 4 A14 A14

FBx_CMD 5 RST RST

FBx_CMD 6 A9 A9

FBx_CMD 7 A7 A7

FBx_CMD 8 A2 A2

FBx_CMD 9 A0 A0

FBx_CMD 10 A4 A4

FBx_CMD 11 A1 A1

FBx_CMD 12 BA0 BA0

FBx_CMD 13 WE# WE#

FBx_CMD 14

FBx_CMD 15 CAS# CAS#

FBx_CMD 16 CS0#

FBx_CMD 17

FBx_CMD 18 ODT

FBx_CMD 19 CKE

FBx_CMD 20 A13 A13

FBx_CMD 21 A8 A8

FBx_CMD 22 A6 A6

FBx_CMD 23 A11 A11

FBx_CMD 24 A5 A5

FBx_CMD 25 A3 A3

FBx_CMD 26 BA2 BA2

FBx_CMD 27 BA1 BA1

FBx_CMD 28 A12 A12

FBx_CMD 29 A10 A10

FBx_CMD 30 RAS# RAS#

+1.5VGS

CV140 DIS@

0.1U_0402_16V7K

CV139 DIS@

2

D D

1

2

1

0.1U_0402_16V7K

Closed toUV16

L

0.1U_0402_16V7K

CV141 DIS@

2

1

+1.5VGS

CV146 DIS@

1U_0402_6.3V6K

CV144 DIS@

0.1U_0402_16V7K

CV143 DIS@

0.1U_0402_16V7K

CV142 DIS@

2

2

1

1

1U_0402_6.3V6K

CV145 DIS@

1

1

2

2

1U_0402_6.3V6K

CV147 DIS@

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

CV148 DIS@

1

1

2

2

0.1U_0402_16V7K

CV160 DIS@

0.1U_0402_16V7K

CV161 DIS@

2

2

1

1

CV162 DIS@

2

1

L

CV163 DIS@

0.1U_0402_16V7K
2

1

Closed toUV18

0.1U_0402_16V7K

CV164 DIS@

CV165 DIS@

0.1U_0402_16V7K

2

1

1

2

1U_0402_6.3V6K

1

1

2

2

1

1

2

2

1U_0402_6.3V6K

CV169 DIS@

1U_0402_6.3V6K

CV168 DIS@

1U_0402_6.3V6K

CV166 DIS@

1U_0402_6.3V6K

CV167 DIS@

Security Classification

IssuedDate

THI S SH EE T OF E NG INE ER ING DR AW IN G IS TH E PR OPR IE TAR Y PRO PE R TY OF COM PA L EL EC TRO NIC S, IN C. AN D CO NTA INS CONFI DENT IAL
AN D T RA DE S EC RE T I NFO RM AT ION . TH IS SH EET M AY NOT BE T RA NS FE R ED FRO M THE CU STO DY OF T HE COM PE TE NT DI VIS ION OF R &D
DE PA RTM ENT EX CE PT AS A UT HOR IZ ED BY CO MPA L EL EC TRO NIC S, IN C. NE ITH ER TH IS S HE ET N OR T HE I NFO RM ATI ON IT CO NTA IN S

1

2

MA Y BE USE D BY OR D IS CLO SE D TO AN Y T HIR D PAR TY W ITHO UT P RIO R WR ITTE N CO NSE NT OF C OM PAL EL EC TRO NIC S, I NC .

3

2011/07/12 2012/07/01

Compal Secret Data

DecipheredDate

Title

Siz e Document Number

Custom

4

Compal Electronics, Inc.

N15V-GM VRAM C Lower

LA-B972P

Sheet 38 of 54Date: Thursday, March 20, 2014

5

Rev

0.1

1

Check Strap pinstatus

<33> STRAP0
<33> STRAP1
<33> STRAP2

A A

<33> STRAP3
<33> STRAP4

Check SPI pin status

<33> ROM_SI
<33> ROM_SO
<33> ROM_SCLK

B B

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

ROM_SI
ROM_SO
ROM_SCLK

12

RV164
10K_0402_5%
X76@

12

RV171
10K_0402_5%
X76@

12

RV176
10K_0402_5%
@

12

RV179
10K_0402_5%
DIS@

12

RV165
10K_0402_5%
X76@

12

RV172
10K_0402_5%
X76@

12

RV177
10K_0402_5%
@

12

RV180
10K_0402_5%
DIS@

GPU Project VRAM size CH Description Compal VRAMP/N VRAM description

128M(X16) CHA DDR3 Hynix 128Mx16 1.5V SA00006H400 H5TC2G63FFR-11C1000MHz 1100 RV171+RV172+RV167+RV166

128M(X16) CHA DDR3 Micron 128Mx16 1.5V SA000067500 MT41J128M16JT-093G:K 1000MHz 0001 RV164+RV172+RV173+RV174

128M(X16) CHA DDR3 Samsung 128Mx16 1.5V SA000068U40 K4W2G1646Q-BC1A 1000MHz 1110 RV165+RV166+RV167+RV171

N15V-GM(23x23) 64bit

(One CH single rank)

ZSO40
ZSO56

+3VGS

2

12

RV166
10K_0402_5%
X76@

12

RV173
10K_0402_5%
X76@

12

RV178
10K_0402_5%
@

12

RV181
10K_0402_5%
DIS@

12

RV167
10K_0402_5%
X76@

12

RV174
10K_0402_5%
X76@

+3VGS

12

RV168
10K_0402_5%
@

12

RV175
10K_0402_5%
DIS@

ZZZ001

SAM@ MIC@

1G SAMSUNG 1G MICRON

X7654132L21 X7654132L23

ROM CFGsetup

[3...0]

3

ZZZ001

HY@

1G HYNIX

X7654132L22

RAM_CFG RP/N

ZZZ001

Table 123

Stra p pin

Name

ROM_SCL K SMB_ALT_ADDR 10K Pull- down to GND.

Strap Mapping Resist ance P olarity Logi cal

4

ROM_SI SUB_VENDOR 10K Pull-dow n to GND if no VBIOS ROM.

ROM_SO V GA_DEVIC E 10K Pull-d own to GND( no dia play).

STRAP0 RAM_CFG[0] 10K

STRAP1 RAM_CFG[1] 10K

STRAP2 RAM_CFG[2] 10K

STRAP3 RAM_CFG[3] 10K

STRAP4 P CIE_MAX_ SPEED 10K Pull-down to GND(PCIE Gen1).

SMBUS_ALT_ADDR

0

0x9E(Default)

1

0x9C (Multi-GPUusage)

SUB_VENDOR

0

Disable (Default)

1

VGA_DEVICE

0

Non-Primary 3D Acceleration Device(Class Code302h)(Default)

1

Primary Display or VGA Device.

PCIE_MAX_SPEED

0

Limit to PCIE Gen1

1

PCIE Gen 2/3 Capable

5

Strappi ng Bit0

#9/5 RAM_CFG follow RVL‐06891‐001 table 1.
Dule Rank layout with single Rank population.

C C

USER Straps

User[3: 0]

1000-1100

Customerdefined

D D

Security Classification

IssuedDate

THI S SH EE T OF E NG INE ER ING DR AW IN G IS TH E PR OPR IE TAR Y PRO PE R TY OF COM PA L EL EC TRO NIC S, IN C. AN D CO NTA INS CONFI DENT IAL
AN D T RA DE S EC RE T I NFO RM AT ION . TH IS SH EET M AY NOT BE T RA NS FE R ED FRO M THE CU STO DY OF T HE COM PE TE NT DI VIS ION OF R &D
DE PA RTM ENT EX CE PT AS A UT HOR IZ ED BY CO MPA L EL EC TRO NIC S, IN C. NE ITH ER TH IS S HE ET N OR T HE I NFO RM ATI ON IT CO NTA IN S

1

2

MA Y BE USE D BY OR D IS CLO SE D TO AN Y T HIR D PAR TY W ITHO UT P RIO R WR ITTE N CO NSE NT OF C OM PAL EL EC TRO NIC S, I NC .

3

2011/07/12 2012/07/01

Compal Secret Data

DecipheredDate

Title

Siz e Document Number

Custom

4

Date: Thursday, March 20, 2014 Sheet 39 of 54

Compal Electronics, Inc.

N15V-GM MISC

LA-B972P

5

Rev

1.0

A

B

C D

E

<MV>Rem ove R563 , delete net +5V S_IN, 4/10.

10U_0603_6.3V6

M

1

+5VALW

+3VALW

+5VALW

1 1

SUSP#

SUSP#

Q21

1

3

VOUT1

VIN1

2

VOUT1

VIN1

CT1

ON1

4
5
6

7

GND

VBIAS
ON2

CT2

VIN2

VOUT2

VIN2

VOUT2

GPAD

TPS22966DPUR_SON14_2X3-D

14
13

12

C554 1 2 100P_0402_50V8J

11

C557 1 2 680P_0402_50V7K

10
9

8
15

2

<MV>Rem ove R564 , delete net +3V S_IN, 4/10.

22U_0805_6.3V6

M

1

C575

2

+3VS

1

C570

10U_0603_6.3V6

M

2

+5VS

CC56

@

<MV>Ad d 22UF for R F suggestio n,4/1 0.

SYSON# SUSP

<30,48> SYSON SUSP# <30,48,49,52,55>

SYSON 2

61

Q18A
DMN66D0LDW-7_SOT363-6

Q18B

34

DMN66D0LDW-7_SOT363-6

5 SUSP#

+5VALW

SYSON 8
SUSP 7
SYSON# 6

+1.05V TO+1.05VS

+1.05V

2 2

AO4430L
VGS Max=+/- 20V
VGS(Th)max=2.5V

Rds Max=5.5m @VGS=10V
Rds Max=7.5m @VGS=4.5V

J1 need toshort

J1

1

1 2

JUMP_43X79
@

+V1.05A

+1.05V

short@ R570 1 20_0805_5%

2

+V1.05DX_MODPHY

+1.05VS

+1.05VS_MODPHY

SUSP# 5 4

RPH16

100K_0804_8P4R_5%

1
2
3

CPU +V1.05DX_MODPHY
Max Rdson <6m ohm
1840mA

3 3

AO4430L
VGS Max=+/- 20V
VGS(Th)max=2.5V

Rds Max=5.5m @VGS=10V
Rds Max=7.5m @VGS=4.5V

4 4

Security Classification

Issued Date

THI S SH EET OF E NGIN EERING DR AWING IS T HE PROPRIET ARY PROP ERT Y OF COMPAL ELECTRONICS, INC. AND C ONT AINS CONFIDENTIAL
AND T RADE SECRET IN FORMATIO N. T HIS SHEET MAY N OT BE TRAN SFERED FR OM TH E CU STO DY OF THE COMPET ENT DIVIS ION OF R& D
DEPA RTMENT EXC EPT A S A UTH ORIZ ED BY COMP AL ELE CTR ONIC S, IN C. NEIT HER THIS SH EET NO R T HE I NFORMAT ION IT CONTAI NS

A

B

MAY BE USED BY OR D ISCLOSED TO ANY T HIR D PARTY W ITH OUT PRIOR W RITT EN C ONSE NT OF COMPAL ELE CTR ONIC S, INC .

C D

2011/06/29 2011/06/29

Compal SecretData

Deciphered Date

Title

Size DocumentNumber

Custom

LA-B972P

Date:

Compal Electronics,Inc.

DCInterface

Sheet 40 of 54Thursday, March 20, 2014

E

Rev

0.1

5

4

3 2

1

NGFF andWLAN

D D

+3VS +3VS_WLAN

@
RL25

2

G

<8> WAKE#

WAKE# 1

2N7002H_SOT23-3

3

D

S

@

QB8

PV# 2013.01.23 Add QB8 abd RL25 to supportOBFF
PV# 2013.02.22 Unpop QB4 and RL23 for not supportOBFF

C C

100K_0402_5%

MC_WAKE#

1 2

MC_WAKE#<21>

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS T HE PRO PRIETAR Y PR OPERTY OF COMPAL ELECT RONICS, I NC. AND CO NTA INS CONFIDENTIASL
AND TRADE SECRE T INFORMATIO N. TH IS SHEET MA Y NOT BE T RANSFER ED F RO M THE CUSTODY OF THE COMPETENT DIVISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER TH IS SHEET NOR T HE INFORMATI ON IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WIT HOUT PRIOR WRITTEN CONSENT OF C OMPAL ELECTRONIC S, INC.

3 2

Compal Secret Data

DecipheredDate

Title

ize DocumentNumber

Custom

LA-B972P

Compal Electronics,Inc.

WAKE and RST-1

Sheet

41 of 54Date: Thursday, March 20,2014

1

Rev

0.1

A

B

C D

E

+3VALW

1 1

<30> PCH_PWR_EN

2 2

3 3

R559

100K_0402_5%

2

G

+3VALW

1 2

13

D

S

Q31

2N7002_SOT23-3

Q30
AO3413L_SOT23-3

1

3

DGS

2

1

@

C591

2

20mils

0.1U_0402_16V7K

+3V_PCH

1

1U_0402_6.3V6K

2

C590

4 4

Security Classification

Issued Date

THI S SHE ET O F ENG IN EER ING DR AW IN G IS T HE PR OP RIE TA RY P ROPER TY O F CO MPA L EL ECT RO NI CS, INC. AN D CO NTA INS CONFIDENTIASSL
AND TR ADE S ECR ET IN FO RMA TI ON . THIS SHEET MAY N OT BE T RA NS FER ED FROM THE C UST OD Y OF T HE CO MPE TE NT DIV ISIO N OF R&D
DEPAR TMENT EX CEPT AS A UT HO RIZ ED BY C OMPAL E LEC TR ON ICS , INC. NEIT HER THIS SH EET N OR TH E INFO RM ATION IT CONTAIN S

A

B

MAY BE USE D BY OR DI SCLOSE D TO A NY TH IRD PA RT Y WITHOUT PRIO R WR IT TEN CON SE NT OF CO MPAL ELE CT RO NIC S, INC.

C D

2011/06/29 2011/06/29

Compal Secret Data

DecipheredDate

Title

ize Document Number

Custom

LA-B972P

Compal Electronics, Inc.

DC DC Device-1

Sheet 42 of 54Date: Thursday, March 20, 2014

E

Rev

0.1

5 4 3 2 1

ADPIN

@ PJP1
ACES_59012-0080N-002

2

1

D D

Charge_LED 8

2 1

4

3

4

6

5

6

7

8

2

3

ESD@ PD1

1

L30ESD24VC3-2_SOT23-3

3

5 ADP_SIGNAL
7 ACIN_LED

ADP_SIGNAL1 2

2

3

ESD@ PD2

1

L30ESD24VC3-2_SOT23-3

12

EMI@ PC1

PR1
10K_0402_5%

HCB2012KF-121T50_0805

1 2

HCB2012KF-121T50_0805

1 2

12

EMI@ PC2

1000P_0402_50V7

100P_0402_50V8

J

12

PR7

PL1 EMI@

PL2 EMI@

K

2 1

10K_0402_5

%

VIN

@ PR2
0_0402_5%

<30> AC_LED#

12

12

EMI@ PC4

EMI@ PC3

100P_0402_50V8

J

1000P_0402_50V7

K

ADP_ID<30>

12

12

@ PD3

GLZ3.6B_LL34-

2

PC6

@ PC5

100P_0402_50V8

J

1000P_0402_50V7

K

<30> BAT_CHG_LED

1 2ACIN_LED

12

PR3
100K_0402_5%

PR5
2K_0402_5%

1 2 Charge_LED

12

PR8
100K_0402_5%

+5VS

C C

<30,4> PROCHOT#

61

PQ2A
L2N7002DW1T1G_SC88-6

2

12

@
PD4
CD4148WN-1_1206-2

0.022U_0402_16V7K

12

@
PR13

1.5M_0402_5%

@
PC8

1 2

12

@
PR10
47K_0402_1%

PU1A

4

LM393DR_SO8

2

G

-

1

O

3

+

P

8

+3VALW

12

@
PR11

10K_0402_1%

12

@
PR12

100P_0402_50V8

J

54.9K_0402_1%

2 1

B/I# <30,45>

PC9

@

+5VS

ADP_I <30,46>

PC13

100P_0402_50V8

J

+3VALW

12

PR18

10K_0402_1%

12

PR21

100K_0402_1%

2 1

ACIN <30,45,46,8>

PC12

1 2

12

PR17
47K_0402_1%

PU1B
LM393DR_SO8

8

5

P

+

7

O

6

-

G

4

B B

34

PQ2B
L2N7002DW1T1G_SC88-6

5

PD5
CD4148WN-1_1206-2

2 1

0.022U_0402_16V7K

PR20

1.5M_0402_5%

2 1

+3VALW_EC

11 2

PR25
10K_0402_1%

12

PH1
100K_0402_1%_NCP15WF104F03RC

@ PC15

2

0.1U_0402_16V7

K

ECAGND<30>

12

@ PC16

1

PR26

5.9K_0402_1%

1 22

PR27
10K_0402_1%

0.1U_0402_16V7

K

12

@ PR28
10K_0402_1%

VCIN1_PH <30>VCIN0_PH <30>

H_PROCHOT#_EC<30>

A A

Security Classification

IssuedDate

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECT RONICS, I NC. AND CO NTAINS CONFIDENTIASL
AND TRADE SECRE T INFORMATIO N. TH IS SHEET MA Y NOT BE T RANSFERED F RO M THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RON ICS, INC. NEITHER TH IS SHEET NOR T HE INFORMATI ON IT CONTAINS

5 4 3 2

MAY BE USED BY OR DISCLOSED TO ANY THIRD P ARTY WIT HOUT PRIOR WRIT TEN CONSE NT OF CO MPAL ELECTRO NICS, INC.

Compal Secret Data

DecipheredDate

Compal Electronics, Inc.

2016/08/062013/08/07

Title

ize

Date:

DC Conn

Document Number

LA-B972P

Thursday, March 20,2014

Sheet

1

Rev

44

0.4

55

of

5 4 3 2 1

@PJPB2

1

2

EMI@PL3

D D

@PJPB1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

GND

10

OCTEK_BTJ-08FUAB

C C

GND

2

3

ESD@ PD6

1

L30ESD24VC3-2_SOT23-3

BATT++ BATT+

PR19
100_0402_5%

1 2

PR22
100_0402_5%

1 2

PR30

2 1

PR29

100_0402_5

%

100K_0402_5%

1

2

+3VL

B/I# <30,44>

HCB2012KF-121T50_0805

1 2

EMI@PL4

HCB2012KF-121T50_0805

1 2

12

EMI@ PC10
1000P_0402_50V7K

2

3

ESD@ PD7

1

L30ESD24VC3-2_SOT23-3

12

EMI@ PC11 @ PR14

0.01U_0402_25V7K 470K_0402_5%

EC_SMB_DA1<28,30,46>

EC_SMB_CK1<28,30,46>

1 2

12

PR15 @
470K_0402_5%

34

PQ3B
L2N7002DW1T1G_SC88-6

JUMP_43X118

PQ1@

SI4483ADY-T1-GE3_SO8
1
2
3

2

5 @

1 2

8
7
6
5

1 4

PR16 @

4.7K_0402_5%

6 21

PQ3A @
L2N7002DW1T1G_SC88-6

+3VL

12

PR23 @
220K_0402_5%

61

BATT

PQ4A @
L2N7002DW1T1G_SC88-6

2

12

PC14 @
100P_0402_50V8J

+3VL

1

PR24 @
220K_0402_5%

3 24

5
PQ4B @
L2N7002DW1T1G_SC88-6

Need to define "AC_AND_CHAG" signal with EC

ACIN <30,44,46,8>

AC_AND_CHAG<30>

B B

A A

Security Classification

IssuedDate

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECT RONICS, I NC. AND CO NTAINS CONFIDENTIASL
AND TRADE SECRE T INFORMATIO N. TH IS SHEET MA Y NOT BE T RANSFERED F RO M THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RON ICS, INC. NEITHER TH IS SHEET NOR T HE INFORMATI ON IT CONTAINS

5 4 3 2

MAY BE USED BY OR DISCLOSED TO ANY THIRD P ARTY WIT HOUT PRIOR WRIT TEN CONSE NT OF CO MPAL ELECTRO NICS, INC.

Compal Secret Data

DecipheredDate

Compal Electronics, Inc.

2016/08/062013/08/07

Title

ize

Date:

BATT Conn

Document Number

LA-B972P

Thursday, March 20,2014

Sheet

1

Rev

45

0.4

55

of

A B C D

D

13

2

PQ102

G

2N7002KW_SOT323-3

PR101

2

4

1 2

3M_0402_5%

1
2
3

ACDRV1_CHG

1

5

PC101

2 1

1M_0402_5%

PQ101

AON6414AL_DFN8-5

2200P_0402_50V7K

1 1

2 2

3 3

PR102

S

5

+3VL

P2VIN B+P1

2 1

PC108

0.1U_0402_25V6

PR114

10K_0402_1%

1

PR103

0.01_1206_1%

1
2

1 2

PC106

0.1U_0402_25V6

2

4
3

PC109

2 1

1U_0603_25V6K

ACN_CHG

ACP_CHG

CMSRC_CHG 3

ACDRV_CHG 4

0.1U_0402_25V6

PC111

1 2

21

1

2

5

VIN

PU101

PAD

ACN

ACP

CMSRC

ACDRV

ACPRES

PQ103
AON7506_DFN33-8-5

1
2
3

PC102

2 1

0.1U_0402_25V6

PR108

2 1

2 1

4.12K_0603_1%

4

PR109

4.12K_0603_1%

<30,44,45,8> ACIN

VIN

EMI@ PL101

1.2UH_NRS4018T1R2NDGJ_2.6A_30%
1 2

3

2

PD101
BAS40CW_SOT323-3

1

PC110

0.047U_0402_25V7K
1 2

PR105

VCC

ACDET

10_1206_1%

LX_CHG

DH_CHG

19

18

PHASE

IOUT7SDA

8

IOUT_CHG

PR106

2 1

2.2_0603_5%

BST_CHG

17

BTST

HIDRV

SCL9ILIM

2 1

VCC_CHG

20

BQ24738RGRR_QFN20_3P5X3P5

ACDET_CHG 6

12

PD102
RB751V-40_SOD323-2

PC112

1U_0603_25V6K

1 2

REGN_CHG

16

REGN

15 DL_CHG

LODRV

14

GND

13 SRP_CHG

SRP

12 SRN_CHG 0_0603_5%

SRN

11 BATDRV_CHG

BATDRV

10

12

@EMI@ PC123

2200P_0402_50V7K

@PR107

0_0603_5%

DH_CHG 1 2

PR112

0_0603_1%

1 2 CSOP1

PR113

1 2 CSON1

PR115
357K_0402_1%
1 2

+3VL

PQ104
AON7506_DFN33-8-5

5

PC105

PC104

2 1

2 1

10U_0805_25V6K

10U_0805_25V6K

PC118

0.1U_0603_16V7K

2 1

5

4

321

5

PQ106

AON7506_DFN33-8-5

4

321

BATDRV_CHG 1 2 BATDRV1_CHG

PQ105
AON7408L_DFN8-5

4.7UH_ETQP3W4R7WFN_5.5A_20%

LX_CHG 1 2 CHG

1

2 1SNB_CHG 2

@EMI@ PC117 @EMI@ PR111

PL102

680P_0603_50V8J 4.7_1206_5%

PR104

4.12K_0603_1%

2 1 CSOP1

PR110

0.01_1206_1%

1
2

PC113

0.1U_0402_25V6

1
2
3

4

PC107

2 1

0.01U_0402_50V7K

BATT

4
3

PC115

PD103

PC116

2 1 CSON1

0.1U_0402_25V6

2 1

PC114

2 1

2 1

RB551V-30_SOD323-2

10U_0805_25V6K

10U_0805_25V6K

PC119

PR117

422K_0402_1%

2 1

PR116

2 1

100K_0402_1%

2 1 ILIM_CHG

0.01U_0402_25V7K

Vin Dectector

H-->L

Min. Max.

L-->H

ILIM and ext ernal D PM

4 4

Typ

17.23 V

17.63 V

3.61A

PC120

2 1

PR118

2 1

0.1U_0402_25V6

66.5K_0402_1%
12

PC121
100P_0402_50V8J

@ PR119
0_0402_5%

1 2

12

locate the RC Near EC chip

Security Classification

A B

EC_SMB_CK1 <28,30,45>

EC_SMB_DA1 <28,30,45>

ADP_I <30,44>

@ PC122

0.1U_0402_10V7K

IssuedDate

THI S SHEET OF E NG INE ER ING D RA WI NG IS T HE PROPR IET AR Y PROPE RT Y OF C OMPAL EL EC TR ONICS , INC. AND CONT AINS CONFIDENTIASSL
AND T RADE SECRE T INF ORMAT ION . THIS S HE ET MAY N OT BE T RA NS FER ED FR OM TH E C US TO DY OF T HE CO MPE TE NT DIVISION OF R&D
DEPAR TMENT EX CEPT AS A UT HO RIZ ED BY C OMPAL ELEC TR ON ICS , INC. NEIT HER THIS SH EET NOR TH E INFO RM ATION IT CONT AIN S
MAY BE USE D BY OR DI SCLOSE D TO A NY TH IRD PA RT Y WITHOUT PRIO R WR IT TEN CON SE NT OF CO MPAL ELE CT RO NIC S, INC.

2013/08/07 2016/08/06

Compal Secret Data

DecipheredDate

C

Title

ize

Custom

Date: Sheet 46 of 55

Compal Electronics, Inc.

CHARGER

Document Number

LA‐A992P

D

Rev

0.4

A B C D

PR302

165K_0402_1%

1 2

PR303

56K_0402_1%

TON_35V

3

TON

13

PC314

1U_0603_10V6K

12

1 2

143K_0402_1%
1 2

ENTRIP_5V

2

ENTRIP1

LDO514LDO3

15

+5VLP

+3VLP

@ PR317
100K_0402_5%

PR304

PR305

30K_0402_1%

1 2

PR307

19.1K_0402_1%

1 2

FB_5V

1

21

FB1

PAD

20

BYP1

19 BST_5V

BOOT1

18 DH_5V

UGATE1

17 LX_5V

PHASE1

16 LG_5V

LGATE1

PU301
RT8243AZQW_WQFN20_3X3

+3VLP

@ PJ301
JUMP_43X39

1

1

12

PC310

4.7U_0603_10V6K

@ PJ304
JUMP_43X39

1

1

12

PC309

4.7U_0603_10V6K

PR310

2.2_0402_1%

1 2 BST1_5V 1 2

2

+3VL

2

(100mA,40mils ,Via NO.= 2)

2

+VL

2

(100mA,40mils ,Via NO.= 2)

PC306

0.1U_0402_10V7K
4

4

+3VALWP

+5VALWP

5

321

5

321

PC304

2 1

10U_0805_25V6K

PQ302
AON7408L_DFN8-5

2.2UH_ETQP3W2R2WFN_8.5A_20%

12 1 SNUB_5V 2

4.7_1206_5%

@EMI@PR312

PQ304

AON7506_DFN33-8-5

@EMI@ PC312

680P_0603_50V8J

@PJ302

1

2

1

JUMP_43X118
@PJ303

1

2

1

JUMP_43X118

PC308

2 1

@

4.7U_0805_25V6-K

PL302

1 2

2

2

+3VALW

+5VALW

+5VALWP

1

+

PC317

2

220U_C6_6.3V_M_R15

1 1

@PC302

100P_0402_50V8J

1 2

PR301

14K_0402_1%

1 2

B+

EMI@ PL301

HCB2012KF-121T50_0805

1 2

2 2

PL303

3.3UH_PCMB063T-3R3MS_6.5A_20%

+3VALWP

1

+

PC316

2

3 3

1 2

220U_C6_6.3V_M_R15

3/5V_B+ 3/5V_B+

+3VALW

12

2 1

2200P_0402_50V7K

@EMI@ PC318

@

10U_0805_25V6K

1

2 1 SNUB_3V 2

5

4.7U_0805_25V6-K

123

5

4.7_1206_5%

@EMI@PR311

123

@EMI@ PC311

680P_0603_50V8J

<8> SPOK

PQ301
AON7408L_DFN8-5

0.1U_0402_10V7K

4

PQ303

AON7506_DFN33-8-5

4

PC305

1 2 BST1_3V 1 2

PC303

PC307

2 1

2 1

PR318
10K_0402_1%

PR309

2.2_0402_1%

3/5V_B+

<30> EC_ON

<30> MAINPWON

BST_3V

DH_3V

LX_3V

LG_3V

499K_0402_1%

1 2

PC313

2 1

@ PR316
0_0402_5%

1 2

PR306

20K_0402_1%

1 2

10

PR313

0.1U_0603_25V7K
PR315

2.2K_0402_1%

1 2

6

7

BOOT2

8

UGATE2

9

PHASE2

LGATE2

PGOOD

2 1

FB_3V

ENTRIP_3V

4

5

FB2

ENTRIP2

VIN

ENLDO12ENM

11

PR314

2 1

100K_0402_1%

@ PC315

2 1

4.7U_0603_6.3V6K

4 4

A B

Security Classification

IssuedDate

THI S SHEET OF E NG INE ER ING D RA WI NG IS T HE PROPR IET AR Y PROPE RT Y OF C OMPAL EL EC TR ONICS , INC. AND CONT AINS CONFIDENTIASSL
AND T RADE SECRE T INF ORMAT ION . THIS S HE ET MAY N OT BE T RA NS FER ED FR OM TH E C US TO DY OF T HE CO MPE TE NT DIVISION OF R&D
DEPAR TMENT EX CEPT AS A UT HO RIZ ED BY C OMPAL ELEC TR ON ICS , INC. NEIT HER THIS SH EET NOR TH E INFO RM ATION IT CONT AIN S
MAY BE USE D BY OR DI SCLOSE D TO A NY TH IRD PA RT Y WITHOUT PRIO R WR IT TEN CON SE NT OF CO MPAL ELE CT RO NIC S, INC.

2013/08/07 2016/08/06

Compal Secret Data

DecipheredDate

C

Title

ize

Custom

Date: Sheet 47 of 55

Compal Electronics, Inc.

3VALW/5VALW

Document Number

LA‐A992P

D

Rev

0.4

5 4 3 2 1

EMI@
PLM1

HCB2012KF-121T50_0805

1 2

B+

D D

12

@EMI@
PCM13
2200P_0402_50V7K

B+_DDR

12

PCM1
10U_0805_25V6K

12

PCM3

4.7U_0805_25V6-K

5

PCM2

0.22U_0402_10V6K
1 2 BST_DDR-1 1 2

PRM1

2.2_0402_1%

+1.35V_VDDQP

+0.6V_0.675VSP

4

PQM1

AON7408L_DFN8-5

PLM2

1.5UH_PCMC063T-1R5MN_9A_20%

+1.35V_VDDQP

12

12

C C

PCM25

22U_0603_6.3V6

B B

12

PCM22

PCM23

PCM24

2 1

22U_0603_6.3V6

22U_0603_6.3V6

22U_0603_6.3V6

M

M

M

1 2

12

12

PCM21

PCM26

22U_0603_6.3V6

M

M

22U_0603_6.3V6

12

@EMI@

PRM2

4.7_1206_5%

1SNB_DDR2

M

@EMI@
PCM7
680P_0603_50V7K

123

5

123

4
PQM2
AON7506_DFN33-8-5

+5VALW

PRM4

5.1_0603_5%

1 2

12

<30,40> SYSON

<30,40,49,52,55> SUSP#

DL_DDR

PRM3

13.3K_0402_1%

1 2 CS_DDR 13

+5VALW

VDD_DDR

12

PCM8
1U_0603_10V6K

PCM9
1U_0603_10V6K

PRM6
432K_0402_1%

B+_DDR 1 2

@ PRM9
0_0402_5%
1 2

@ PRM11
0_0402_5%
1 2

15

14

12

11

LGATE

PGND

CS

VDDP

VDD

DH_DDR

LX_DDR

16

17

PHASE

UGATE

PUM1

RT8207PGQW_WQFN20_3X3

PGOOD

TON

9

10

TON_DDR

12

@
PCM11

0.1U_0402_10V7K

BST_DDR

18

BOOT

S5

8

S5_DDR

20

19

VTT

VLDOIN

VTTGND

VTTSNS

VTTREF

S3

FB

6

7

FB_DDR

S3_DDR

12

12

@
PCM12

0.1U_0402_10V7K

21

PAD

1

2

3

GND

4

5

VDDQ

PRM5

8.06K_0402_1%

1 2

PRM8
10K_0402_1%

VTTREF_DDRT

+1.35V_VDDQP

12

+1.35V_VDDQP

+1.35V_VDDQP

+0.6V_0.675VSP

12

PCM4

PCM5

10U_0805_6.3V6

K

10U_0805_6.3V6

K

12

PCM10

0.033U_0402_16V7K

@PJPM2

1

2

1

2

JUMP_43X118

@ PJPM1
JUMP_43X39

1 2

1 2

+1.35V_VDDQ

+0.6V_0.675VS

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS T HE PRO PRIETAR Y PROPERTY OF COMPAL ELECT RONICS, I NC. AND CO NTAINS CONFIDENTIASL
AND TRADE SECRET INFORMAT ION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUS TOD Y OF TH E COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RON ICS, INC. NEITHER TH IS SHEET NOR T HE INFORMATI ON IT CONTAINS

5 4 3 2

MAY BE USED BY OR D ISCLOSED TO ANY T HIR D PARTY WITHOUT PRIOR W RITTEN CONSENT OF C OMPAL ELECTRONIC S, INC .

2013/08/07 DecipheredDate

Compal Secret Data

2016/08/06

Title

ize DocumentNumber

Custom

Date:

Compal Electronics,Inc.

1.35V/0.675VS

LA-B972P

Thursday, March 20, 2014

Sheet 48 of 55

1

Rev

0.4

5 4 3 2 1

D D

EN pin don't floating
If have pull down resistor at HW side, pls delete PR2

@ PRH1
0_0402_5%

12

PRH2
1M_0402_1%

1 2

12

@ PCH1

0.22U_0402_10V6K

SUSP# <30,40,48,52,55>

@EMI@

PRH3
EMI@
PLH1

HCB2012KF-121T50_0805

1 2

B+

12

C C

EMI@ PCH4

2200P_0402_50V7

K

+3VS

12

1

PCH5

10U_0805_25V6

K

PRH6
10K_0402_5%

12

<30> +1.05V_VS_PG_PWR

B+_1.05V

PCH6

10U_0805_25V6

K

ILMT_1.05V 3

2

PUH1
SY8206DQNC_QFN10_3X3

8

IN EN

9

2

GND

ILMT

PG

BS

LX

FB

BYP

LDO

1

6 BST_1.05V1 2

10 LX_1.05V

4 FB_1.05V
7

5 LDO_3V

@PRH4

0_0603_5%

12

Pin 7 BYP is for CS.
Common NB can delete +3VALW and PC15

12

PCH12

PCH13

4.7U_0603_6.3V6

K

BST_1.05Vn1

+3VALW

4.7U_0603_6.3V6

K

PCH3

0.1U_0603_25V7K
2

4.7_1206_5% 680P_0603_50V7K

1 2 SNB_1.05V 1 2

PLH2

1UH_PCMB063T-1R0MS_12A_20%

1 2

@EMI@
PCH2

12

12

PRH5
100K_0402_1%

PRH7
133K_0402_1%

+1.05VSP

@ PJH1
JUMP_43X118
1

1 2

12

12

12

12

PCH7

330P_0402_50V7

K

PCH9

PCH8

47U_0805_6.3V6

47U_0805_6.3V6

M

M

12

PCH10

PCH11

22U_0805_6.3VA

M

22U_0805_6.3VA

M

+1.05VS

2

continuous 6A
peak 12A

+3VALW

12

B B

PRH8 @
0_0402_5%

ILMT_1.05V

12

PRH9 @0@
0_0402_5%

The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high

A A

Security Classification

IssuedDate

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECT RONICS, I NC. AND CO NTAINS CONFIDENTIASL
AND TRADE SECRET INFORMAT ION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUS TOD Y OF TH E COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NE ITHER THIS SHEET NOR THE INFORMA TION IT CO NTAINS

5 4 3 2

MAY BE USED BY OR D ISCLOSED TO ANY T HIR D PARTY WITHOUT PRIOR W RITTEN CONSENT OF C OMPAL ELECTRONIC S, INC .

2013/08/07 2016/08/06

Compal Secret Data

DecipheredDate

Compal Electronics, Inc.

Title

1.05V

ize DocumentNumber

LA-B972P

Thursday, March 20, 2014

Date:

Sheet 49 of 55

1

Rev

0.4

5 4 3 2 1

<11>

<13>

VREF

10K_0402_1%

D D

39K_0402_1%

CPU_B+

C C

+3VS

VSSSENSE
VCCSENSE

B B

A A

PRZ15

0_0402_5%

1 2

@ PRZ19
0_0402_5%

1 2
1 2

0_0402_5%

@ PRZ20

4.87K_0402_1% 4700P_0402_25V7K
1 2 1 2

100P_0402_50V8J

PRZ27 PCZ21

@ PRZ1

PRZ6

PRZ12

10K_0402_1%

1 2

CSP1
CSN1
CSN2
CSP2

@PCZ19

1 2

PRZ25

10K_0402_1%

1 2

12

12

GFB
VFB

+5VS

12

PHZ1

100K_0402_1%_NCP15WF104F03RC

PRZ7

PCZ12

2 1

9.09K_0402_1

%

SLEWA

16

PUZ1

17

CSP1

18

CSN1

19

CSN2

20

CSP2

21

CSP3

22

CSN3

23

GFB

24

VFB

25

PRZ24

4.87K_0402_1%
1 2

VREF

PCZ22

0.33U_0402_10V6K

PRZ29

10_0603_1%

1

1U_0603_10V6K

<11> VR_SVID_ALRT#

12

PCZ1

4700P_0402_16V7K

2 1

.001U_0402_50V7-M

B-RAM

OCP-I

15

14

13

12

11

VBAT

IMON

OCP-I

SLEWA

THERM

TPS51624RSM_QFN32_4X4

COMP

V5A

GND

VREF

DROOP

28

26

2

PCZ24

29

27

VR_HOT# 30

12

12

<11> VR_SVID_CLK

<11> VR_SVID_DAT

<30> VR_HOT#

PRZ2

2 1

1

PRZ8

2

F-IMAX

O-USR

10

9

O-USR

F-IMAX

B-RAMP

VCLK

ALERT#

VR_HOT#

VR_SVID_CLK 31

VR_SVID_ALRT# 32

.1U_0402_16V7K

@ PCZ29

47P_0402_50V8J

332K_0402_1%

39K_0402_1%

VR_ON

SKIP#
PWM1
PWM2
PWM3

PGOOD

VDD

VDIO

PCZ26

VR_HOT#

@

8
7
6
5

4

3
2
1

PAD

33

PRZ3

2 1

100K_0402_1%

PRZ9

2 1

150K_0402_1%

VR_SVID_DAT

1U_0402_6.3V6K

12

PRZ33

54.9_0402_1

12

2 1PRZ34

680K_0402_1%

2 1

100K_0402_1%

VR12.5_VR_ON <11>

SKIP
PWM1
PWM2

12

PRZ5

PRZ11

12

PRZ4

PRZ10

PCZ18

+1.05VS_VCCST

2

130_0402_1

%

1

2 1

%

2 1

9.31K_0402_1%

2 1

150K_0402_1%

%

PRZ21

1_0402_5

+3VS

VR_SVID_CLK
VR_SVID_ALRT#
VR_SVID_DAT

PRZ22

2 1

VGATE <11>

10K_0402_1

%

PRZ14

2.2_0402_1%

1

1 2

PCZ14

.1U_0402_16V7K

PWM1

@PRZ28

2.2_0402_1%

1 2

1 2

@PCZ23

.1U_0402_16V7K

PWM2

CPU_B+

12

PCZ

@

CPU_B+

5

PGND2

2

CPU_B+

VIN

6

BOOT_R PGND1

7

BOOT

8

PWM

CSD97374CQ4M_SON8_3P5X4P5

5

PGND2

VIN

6

BOOT_R PGND1

7

BOOT

8

PWM

@ PUZ3

CSD97374CQ4M_SON8_3P5X4P5

9

4.7U_0805_25V6-

9

PUZ2

9

12

2 1

6 EMI@

PCZ2

0.1U_0402_25V

K

2200P_0402_50V7

EMI@
PCZ13

680P_0402_50V7K4.7_1206_5%

1 2 1 2

4

VSW

3
2

VDD

1

SKIP#

1 2

SKIP

@EMI@
PCZ20

680P_0402_50V7K

1 2

4

VSW

3
2

VDD

1

SKIP#

1 2

SKIP

2 1

K EMI@PCZ3

@
PRZ16
0_0402_5%

@
PRZ30
0_0402_5%

EMI@ PLZ1

HCB2012KF-121T50_0805

1 2

1

12

PCZ5

PCZ10

2 1

@

10U_0805_25V6

K

10U_0805_25V6

K

PCZ4RF@

68P_0402_50V8J

EMI@

PRZ13

+5VS

12

PCZ15
1U_0603_10V6K

PCZ6

PCZ11

2 1

2 1

@

10U_0805_25V6

K

10U_0805_25V6

K

PLZ2

0.15UH_ETQP4LR15AFM_29A_20%
1 4

2 3

PRZ23

2.43K_0402_1%
1 2

1

+

+

PCZ8

PCZ7

33U_25V_

M

2

2

100U_25V_

@

M

PRZ17

3K_0402_1

PRZ18

2 1

12.1K_0402_1

%

+VCC_CORE

%

1 2 1

2

PHZ2

10K_0402_1%_TSM0A103F34D1RZ

B+

CSN1

12

12

PCZ17

PCZ16

0.15U_0402_10V6

0.22U_0402_10V6

K

K

@

CSP1

NTC
B value=3435 K

@EMI@

PRZ26

4.7_1206_5%
1 2

@PLZ3

0.15UH_ETQP4LR15AFM_29A_20%

+5VS

12

@

PCZ25
1U_0603_10V6K

1 4
2 3

@ PRZ35

1.82K_0402_1%
1 2

@

PRZ32

@

36K_0402_1

%

2 1

PRZ31

2.43K_0402_1

%

2

+VCC_CORE

12

1 2 1

PHZ3

@

@

10K_0402_1%_TSM0A103F34D1RZ

CSN2

12

PCZ28

PCZ27

0.15U_0402_10V6

0.22U_0402_10V6

K

K

@

CSP2

SecurityClassification

IssuedDate

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECT RONICS, I NC. AND CO NTAINS CONFIDENTIASL
AND TRADE SECRE T INFORMATIO N. TH IS SHEET MA Y NOT BE T RANSFERED F RO M THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RON ICS, INC. NEITHER TH IS SHEET NOR T HE INFORMATI ON IT CONTAINS

5 4 3 2

MAY BE USED BY OR DISCLOSED TO ANY THIRD P ARTY WIT HOUT PRIOR WRIT TEN CONSE NT OF CO MPAL ELECTRO NICS, INC.

2013/08/07 2016/08/06

Compal Secret Data

DecipheredDate

Compal Electronics, Inc.

Title

CPU_CORE

ize

DocumentNumber

LA-B972P

Thursday, March 20,2014 Sheet

Date:

Rev

50

1

0.4

55

of

+VCC_CORE

5 4 3 2 1

D D

1

12

PCZ51

PCZ50

2

@

@

22U_0603_6.3V6

22U_0603_6.3V6

M

M

1

1

PCZ52

2

@

22U_0603_6.3V6

M

1

12

PCZ53

PCZ54

2

2

@

22U_0603_6.3V6

M

PCZ55

@

@

22U_0603_6.3V6

M

22U_0603_6.3V6

12

12

PCZ57

PCZ56

@

M

22U_0603_6.3V6

22U_0603_6.3V6

M

M

1

12

PCZ59

PCZ58

2

@

22U_0603_6.3V6

22U_0603_6.3V6

M

M

1

+

PCZ70

2

220U_D2SX_2VY_R9M

acoustic noise

1

1

1

PCZ62

PCZ61

PCZ60

2

22U_0603_6.3V6

M

C C

B B

acoustic noise

2

2

@

22U_0603_6.3V6

M

2.2U_0402_10V6

M

12

12

PCZ63

@

22U_0603_6.3V6

M

12

PCZ64

PCZ65

22U_0603_6.3V6

M

22U_0603_6.3V6

12

12

PCZ67

PCZ66

@

22U_0603_6.3V6

M

22U_0603_6.3V6

M

M

1

12

PCZ68

PCZ69

2

@

22U_0603_6.3V6

M

22U_0603_6.3V6

M

A A

SecurityClassification

IssuedDate

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECT RONICS, I NC. AND CO NTAINS CONFIDENTIASL
AND TRADE SECRE T INFORMATIO N. TH IS SHEET MA Y NOT BE T RANSFERED F RO M THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RON ICS, INC. NEITHER TH IS SHEET NOR T HE INFORMATI ON IT CONTAINS

5 4 3 2

MAY BE USED BY OR DISCLOSED TO ANY THIRD P ARTY WIT HOUT PRIOR WRIT TEN CONSE NT OF CO MPAL ELECTRO NICS, INC.

2013/08/07 2016/08/06

Compal Secret Data

DecipheredDate

Compal Electronics, Inc.

Title

PROCESSOR DECOUPLING

ize

Document Number

LA-B972P

Thursday, March 20,2014 Sheet

Date:

Rev

51

1

0.4

55

of

A

1 1

UMA@
PU1501

FB SGND

2

PG
IN

4

PGND NC

SY8003DFC_DFN8_2X2

+3VALW

@
PJ1501

JUMP_43X79

1

1 2

2

12

UMA@
PC1501
22U_0805_6.3VAM

FB_1.5V 1

VIN_1.5V 3

PGND

EN

LX

B

9
8

7 EN_1.5V
6 LX_1.5V
5

UMA@
PL1501

1UH_PH041H-1R0MS_3.8A_20%

1 2

12

@EMIUMA@
PR1504

4.7_0603_5%

12

@UMA@

PC1502

.1U_0402_16V7K

12

UMA@
PR1505

30.1K_0402_1%

@UMA@
0_0402_5%

1 2

12

UMA@
PR1503
1M_0402_5%

12

UMA@
PC1503
68P_0402_50V8J

C D

PR1502

SUSP# <30,40,48,49,55>

+1.5VS

2

12

UMA@
PC1504
22U_0805_6.3VAM

+1.5VSP

12

@
PJ1502
JUMP_43X79

1

1 2

UMA@
PC1505
22U_0805_6.3VAM

12

@EMIUMA@
PC1506
680P_0402_50V7K

2 2

3 3

12

UMA@
PR1506
20K_0402_1%

continuous 3A

4 4

Security Classification

IssuedDate

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECT RONICS, I NC. AND CO NTAINS CONFIDENTIASL
AND TRADE SECRET INFORMAT ION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUS TOD Y OF TH E COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RON ICS, INC. NEITHER TH IS SHEET NOR T HE INFORMATI ON IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WIT HOU T PRIOR WRITTEN CONSENT OF C OMPAL ELECTRONIC S, INC.

B

2013/08/07 2016/08/06

Compal Secret Data

DecipheredDate

C

Compal Electronics, Inc.

Title

1.5VS

ize DocumentNumber

LA-B972P

Date: Thursday, March 20,2014

Rev

52

Sheet

D

0.4

55

of

5

D D

12

VGA@
PCV1
1U_0402_6.3V6K

C C

VGA@
PRV12
100_0402_1%

1 2

@VGA@

<35> VSSSENSE_VGA

B B

<34> VCCSENSE_VGA

1. VSNS Soft-Start time (Internal) is 0.7ms (PCV17 un-pop)
Tss=(Css*Vrefin)/Iss+2.3ms

=0.01U*0.9V/5uA+2.3ms=4.1ms (PCV17pop)

2. Switching frequency setting:
Fsw=(Vin-0.5)/(2*Vin*Rton*3.2p)=448Khz

A A

3. Thermal monitoring:

(VGPU_VREF-VTSNS)/PRV21=VTSNS/Rth

+VGA_CORE

VGA@
PRV18
100_0402_1%

1 2

PRV16

0_0402_5%

1 2

@VGA@
PRV17

0_0402_5%

1 2

2 1

GPU_B+

@VGA@
PCV16
47P_0402_50V8J

VGA@
PRV13
340K_0402_1%
1 2

Rton

1

@VGA@
PCV14

0.01UF_0402_25V7K

2

12

VGA@
PCV23
1U_0402_6.3V6K

T_min T_typical T_max

PRV21=18.7K 96.73C 100C 103.1C

PRV21=13K 106.38C 110C 113.4C

5

4

@VGA@

PRV4

0_0402_5%

1 2

Rboot

@VGA@
PCV7

0.01U_0402_16V7K

1 2

Rref2

VGA@
PRV8

6.2K_0402_1% 1.74K_0402_1%

1 2 1 2

VGA@
PRV11

GPU_VREF

<30> GPU_HOT#

4

12

12

GPU_REFIN
GPU_VREF
GPU_TON 9
GPU_FBRTN 10
GPU_FB 11
GPU_COMP 12

1

@VGA@
PCV17

0.01U_0402_16V7K

2

Css

VGA@
PRV21

18.7K_0402_1%

VGA@
PHV1
470K_0402_5%_TSM0B474J4702RE

+3VS

12

Rref1

VGA@
PRV3

7.5K_0402_1%
VGA@

PRV5
27K_0402_1%

1 2

Rrefadj

12

VGA@
PCV8
5600P_0402_50V7K

C

GPU_FBRTN

7
8

RGND

SS

VGA@
PRV25
100K_0402_1%

1

GPU_REFADJ

6

REFADJ

REFIN
VREF

TON

VGA@

PUV1

RT8813AGQW_WQFN24_4X4

VSNS

TSNS/ISEN3

GND

13

25

GPU_TSNS/ISEN3

2

@VGA@ PRV26

@VGA@PRV28

GPU_VI

D

GPU_PSI

VID

TALERT/ISEN2

14

15

GPU_HOT#

GPU_DSBL/ISEN

@VGA@
PRV1
1K_0402_5%
1

@VGA@
0_0402_5%

1 2

1K_0402_5%
1
@VGA@

0_0402_5%
1 2

10K_0402_5%
1 2

GPU_E

354

PSI

VCC/ISNE1

16

1

GPU_PGOOD1

2

PRV2

2

PRV6

U2_BOOT

1

N

U2_UGATE1

2

1

EN

BOOT1

UGATE

1

GND/PWM3

PGOOD

BOOT2

UGATE

2

17

18

U2_UGATE2

U2_BOOT2

+3VGS

12

+3VGS

NVVDD_PWM_VID<32>

+3VGS

PSI Pull high on HWside

NVVDD_PSI <32>

@VGA@ PRV27

1K_0402_5%
1

VGA@ PRV9

1K_0402_5%
1 2

12

@VGA@
PCV9

0.1U_0402_25V6

Reserve Location

24 U2_PHASE1

PHASE1

23 U2_LGATE1

LGATE1

22 U2_PWM3U2_PWM3

21

PVCC

20 U2_LGATE2

LAGTE2

19 U2_PHASE2

PHASE2

VGA@
PRV22
10K_0402_1%

DGPU_PWROK<35>

3

Operation phaseNumber PSI Voltage setting

1 phase withDEM 0V to 0.8V

1 phase withCCM 1.2V to1.8V

Active phase withCCM 2.4V to 5.5V

2

+3VGS

Pull high on HWside

DGPU_PWR_EN <30,35,9>

+5VS

VGA@
PRV24

2.2_0603_5%

1 2

12

VGA@
PCV27
1U_0402_6.3V6K

3

2

GPU_B+

5

2 1

2 1

@VGA@

PRV10

U2_UGATE1 1 2

U2_BOOT1 1 2 1 2

U2_PHASE1

U2_LGATE1

U2_UGATE2 1 2

U2_BOOT21

U2_PHASE2

U2_LGATE2

Security Classification

Issued Date

THIS SH EET OF ENG INEE RING D RAW ING IS THE PR OPRI ETAR Y PROP ERTY OF C OMPA L EL ECTR ONICS , INC. AND CON TAIN S CONFIDENTIASL
AND TRADE SEC RET INFOR MATIO N. THIS SH EET MAY N OT BE TRANS FERE D FR OM THE C USTO DY OF THE COMPE TENT DIVISION OF R &D
DEP ARTM ENT E XCEP T A S A UTHOR IZED B Y C OMP AL EL ECTR ONIC S, INC. NE ITHER THIS SH EET NOR THE IN FORM ATIO N IT CONT AINS
MAY BE U SED BY OR DISCL OSE D TO A NY TH IRD PARTY WIT HOUT PRI OR W RIT TEN CONS ENT OF COMPA L ELE CTRO NICS , INC.

0_0603_5%

VGA@
PRV7

2.2_0603_5% 0.22U_0603_25V7K

VGA@
PRV19

2.2_0603_5%

VGA@
PCV5

12

VGA@
PRV15

12.7K_0402_1%

Rocset

@VGA@

PRV20

0_0603_5%

2 1 2

2013/08/07 2016/08/06 Title

MDU1511RH_POWERDFN56-8-5

MDU1511RH_POWERDFN56-8-5

Compal Secret Data

VGA@
PCV18

0.22U_0603_25V7K

Deciphered Date

2

4

VGA@
PQV2

VGA@

PQV4

321

4

4

4

2200P_0402_50V7

EMIVGA@ PCV3

VGA@
PQV1
SIR472DP-T1-GE3_POWERPAK8-5

5

11SNB_VGA12

321

2

12

5

2200P_0402_50V7

EMIVGA@ PCV20

VGA@
PQV3
SIR472DP-T1-GE3_POWERPAK8-5

321

5

321

1

2 1SNB_VGA22

2 1

VGA@ PCV4

K

10U_0805_25V6

K

VGA@PLV2

0.22UH_PCME064T-R22MS_28A_20%
1 2

@EMIVGA@
PRV14

4.7_1206_5%

@EMIVGA@
PCV15
680P_0603_50V7K

2 1

2 1

VGA@ PCV21

K

10U_0805_25V6

K

VGA@PLV3

0.22UH_PCME064T-R22MS_28A_20%
1 2

@EMIVGA@
PRV23

4.7_1206_5%

@EMIVGA@
PCV26
680P_0603_50V7K

EMIVGA@
PLV1

HCB2012KF-121T50_0805

1 2

VGA@ PCV6

10U_0805_25V6

K

VGA@ PCV22

10U_0805_25V6

K

ize DocumentNumber

1

B+

1

+

2

100U_25V_M

VGA@PCV19

+VGA_CORE
EDP-Continuous 33.5A
EDP-Peak 51.5A
OCP 66A

1

+

2

390U_2.5V_M

VGA@PCV12

1

+

2

VGA@PCV10

Co-Lay Co-Lay

GPU_B+

+VGA_CORE

1

+

2

390U_2.5V_M

VGA@PCV25

Co-Lay

Compal Electronics, Inc.

VGA_CORE

LA-B972P

Sheet 53 of 55Date: Thursday, March 20,2014

1

+VGA_CORE

390U_2.5V_M

Rev

0.4

A

B

C D

E

+VGA_CORE

PLACE UNDER GPU

1 1

12

VGA@
PCV51

4.7U_0603_6.3V6M

12

VGA@
PCV52

4.7U_0603_6.3V6M

12

VGA@
PCV53

4.7U_0603_6.3V6M

12

VGA@
PCV54

4.7U_0603_6.3V6M

12

VGA@
PCV55

4.7U_0603_6.3V6M

12

VGA@
PCV56

4.7U_0603_6.3V6M

2 2

12

VGA@
PCV61

1U_0402_6.3V6K

12

VGA@
PCV57

4.7U_0603_6.3V6M

12

VGA@
PCV62

1U_0402_6.3V6K

12

VGA@
PCV58

4.7U_0603_6.3V6M

12

VGA@
PCV63

1U_0402_6.3V6K

12

VGA@
PCV59

4.7U_0603_6.3V6M

12

VGA@
PCV64

1U_0402_6.3V6K

12

VGA@
PCV60

4.7U_0603_6.3V6M

PLACE NEAR GPU

12

VGA@
PCV65

4.7U_0603_6.3V6K

3 3

12

VGA@
PCV70

22U_0603_6.3V6M

12

VGA@
PCV66

4.7U_0603_6.3V6K

12

VGA@
PCV71

47U_0805_6.3V6M

12

VGA@
PCV67

4.7U_0603_6.3V6K

12

VGA@
PCV68

4.7U_0603_6.3V6K

12

VGA@
PCV69

4.7U_0603_6.3V6K

4 4

Security Classification

Issued Date

TH IS SH E ET OF ENG I NEE RI N G DR A W IN G IS TH E P ROP R IE T AR Y P ROP ERT Y O F COM PAL E L EC T RON I CS , IN C. A N D C ON TAI NS CONFIDENTISSAiL
AN D T RAD E S ECR ET IN FO RMATI ON . TH IS S H EE T MAY N O T BE T R AN S FER ED FRO M TH E CUS T OD Y OF TH E CO M PE T ENT D IVISI ON OF R& D
DE P ART MEN T EXC EPT AS A U THO R IZE D BY CO MPA L E LEC T RON ICS , IN C. NE IT HE R T HIS S H EE T N O R T H E IN F ORM ATI O N IT C ONT AI NS

A

B

MA Y BE US ED BY OR D ISC LO SE D TO AN Y T HI RD PA RT Y W ITH OUT P R IO R W RI T TEN C ONS EN T OF CO MP A L EL E CT R O NI C S, IN C.

2013/08/07 2016/08/06

C D

Compal Secret Data

Deciphered Date

Title

VGA CHIP DECOUPLING

ze Document Number

B

Compal Electronics, Inc.

LA-B972P

Sheet

E

Rev

54 of 55Date: Thursday, March 20, 2014

0.4

5

D D

4

@VGA@

PRW1

0_0402_5%

1 2

12

VGA@
PRW2
1M_0402_1%

12

@VGA@
PCW1

0.01UF_0402_25V7K

3 2

SUSP# <30,40,48,49,52>

1

@EMIVGA@

PRW3
EMIVGA@
PLW1

HCB2012KF-121T50_0805

1 2

B+

C C

12

12

VGA@ PCW4

4.7U_0805_25V6-

2200P_0402_50V7K

EMIVGA@ PCW3

K

B+_VRAMPWR 8

12

VGA@ PCW6

4.7U_0805_25V6-

K

VGA@

PUW1

IN

9

GND

3
2

SY8206DQNC_QFN10_3X3

EN
BS

LX

FB
ILMT BYP
PG LDO

1 EN_VRAMPWR

6 BST_VRAMPWR 1 2 BST_VRAMPWR1n

10 LX_VRAMPWR

4 FB_VRAMPWR

7

5

@VGA@

PRW4

0_0603_5% 0.1U_0603_25V7K

12

12

VGA@
PCW13

4.7U_0603_6.3V6K

VGA@
PCW12

4.7U_0603_6.3V6K

VGA@
PCW5

+3VALW

4.7_1206_5%

1 2 SNB_VRAMPWR1

2

VGA@
PLW2

1.5UH_PCMC063T-1R5MN_9A_20%
1 2

@EMIVGA@
PCW2

680P_0603_50V7K

2

12

VGA@
PRW5

30.1K_0402_1%

12

VGA@
PRW6

19.6K_0402_1%

12

VGA@
PCW7
330P_0402_50V7K

12

VGA@
PCW8
22U_0805_6.3VAM

12

VGA@
PCW9
22U_0805_6.3VAM

12

VGA@
PCW10
22U_0805_6.3VAM

+1.5VDIS +1.5VS

@
PJW1
JUMP_43X118

1

2

1 2

12

VGA@
PCW11
22U_0805_6.3VAM

continuous 6A
peak 12A

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS T HE PRO PRIETAR Y PROPERTY OF COMPAL ELECT RONICS, I NC. AND CO NTAINS CONFIDENTIASL
AND TRADE SECRE T INFORMATIO N. TH IS SHEET MA Y NOT BE T RANSFERED F RO M THE CUSTODY OF THE C OMPETENT DIVISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RON ICS, INC. NEITHER TH IS SHEET NOR T HE INFORMATI ON IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WIT HOU T PRIOR WRITTEN CONSENT OF C OMPAL ELECTRONIC S, INC.

2013/08/07 DecipheredDate

3 2

Compal Secret Data

2016/08/06

Title

ize DocumentNumber
Custom

Thursday, March 20, 2014

Date:

Compal Electronics,Inc.

VRAM Power

LA-B972P

Sheet 55 of 55

1

Rev

0.4