Compal LA-b753p Schematics

A

B

C

D

E

MODEL NAME :

1 1

PCB NO :

BOM P/N :

LA-B751P/LA-B753P

4319UA31L01 / 4319UA31L02 for NV

Echo 15 17 nVidia

4319UB31L01 for AMD

Compal Confidential

2 2

Echo 15 17 with nVidia GFX

Schematic Document

Broadwell H-type

Rev: 0.1(X00)

3 3

2014/01/02

@ : Nopop Component

EMC@ : EMI part
ESD@ : ESD part
RF@ : RF part
CONN@ : Connector Component

4 4

BDW@ : Intel BOARDWELL
AOAC@ : Intel AOAC

A

B

DIS@ : Discrete Part
NV@ AMD@ : Board ID

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

ZZZ1

PCB

DAB0000P000

PCB 18F LA-B752P REV0 M/B 8

12L

Compal Electronics, Inc.

Title

Title

Title

Cover Sheet

Cover Sheet

Cover Sheet

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

LA-B751P

LA-B751P

LA-B751P

E

1 69Wednesday, March 26, 2014

1 69Wednesday, March 26, 2014

1 69Wednesday, March 26, 2014

0.1

0.1

0.1

A

B

C

D

E

Echo 15"/17'' Block Diagram

eDP panel

HDMI

Page25

Page27

1

connector

mini DP
connector

Page26

50W,75W dGPU
nVIDIA / AMD
4pcs GDDR5 128bit
6pcs GDDR5 192bit
8pcs GDDR5 256bit

2

PCI-E(GEN3)x4
port8~port11

Caldera
connector

Page41

Page30

RJ45
connector

Page31

3 in 1
Card slot

3

Echo 17" only

DC in

1.05V

Battery

4

3V/5V

System

1.35V

1.5V

CPU
Vcore

dGPU
Core

Charger

dGPU

1.35V

www.schematic-x.blogspot.com

A

Page46~55

LAN(Gigabit)
Killer E2201

Page30

Card reader
RTS5227

Page31

NGFF (M.2)

Page29

SSD 1

NGFF (M.2)

Page29

SSD 2

NGFF (M.2)

Page29

SSD 3

Page30

NGFF (M.2)

Page29

SSD 4

NGFF (M.2)
WLAN+BT

SPI ROM

Page19

64Mbit

eDP 1.3

HDMI 1.4a (DDI1)

DP 1.2 (DDI2)

PCI-E(GEN3)x8
port0~port7

USB3.0 port5

USB2.0 port2

PCI-E2.0 port3

PCI-E2.0 port5

SATA3.0 port1

Gen3

SATA3.0 port5

Gen3

SATA3.0 port4

Gen3

SATA3.0 port3

Gen2 only

PCI-E2.0 port4

USB2.0 port4

SPI

Int. KBD

ENE KC3810

Page43

B

Broadwell M-Processor
4C + GT2
47W , BGA1364 balls

Page7~13

DMI x 4

Wildcat Point-LP PCH

BGA 696 balls

Page16~24

LPC Bus

ENE KB9012

Page43

USB2.0

Touch pad

C

FFS
LNG3DMTR

Memory Bus Dual Channel

1.35V DDR3L 1600 MHz

SATA3.0 port0

USB2.0 port3

USB2.0 port5

USB2.0 port6

USB3.0 port1
USB2.0 port0

USB3.0 port2
USB2.0 port7

USB3.0 port6
USB2.0 port1

USB3.0 port3
USB2.0 port8

Fan Control
ADM1032

204pin SO-DIMM x2

XDP connector

Page14~15

HDD connector

AlienFX / ELC , C8051F347

Touch screen

Digital camera(with digital MIC)

USB connector 1 , Right side

USB connector 2 , Right side

USB connector 3 , Left side
USB power share

USB connector 4 , Lift side

Page36

Page37

Page25

Page34

Page34

HP/MIC Global headset
combo JACK

HD Audio

Audio codec
Creative
Sound Core3D-EX

Page32

HP/MIC Retaskable
combo JACK

TI TPA3111

Sub-woofer

Echo 17" only

TI TPA3131D2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION I T CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

Page32

Daughter Board

Speaker

Compal Secret Data

Compal Secret Data

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Page35

Page35

Page32

Page32

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Block diagram

Block diagram

Block diagram

LA-B751P

LA-B751P

LA-B751P

E

2 69Wednesday, March 26, 2014

of

2 69Wednesday, March 26, 2014

of

2 69Wednesday, March 26, 2014

of

1

2

3

4

0.1

0.1

0.1

A

B

C

D

E

Compal Confidential

Project Code : AAP10/AAP20
File Name : LA-XXXXP

1 1

M/B

Camera

FFC

? pin

Touch Pad

2 2

LS-9335P
POWER BUTTON/B

on/off SW

Led x 2

LS-9336P

FFC

? pin

INDICATOR/B

Led-HDD

Led-Wireless

Led-CapsLock

3 3

Lid

FFC

? pin

KSI/KSO

? pin

Keyboard

Backlight

? pin

Wire

12pin

LOGO /B

Led x 2

44 pin

50pin

Coaxial/Wire Combo

Daughter/B

Sub-woofer Amplifier

Wire-Set

eDP Panel

USB3.0

USB3.0

Headphone combo JACK

Headphone combo JACK

Hot Bar Hot Bar Hot Bar

6pin 6pin6pin

WireWireWire

Alien head badge/B Alien Slits-L Light/BAlien Slits-R Light/B

Led x 2Led x 2 Led x 2

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

E

0.1

0.1

3 69Wednesday, March 26, 2014

3 69Wednesday, March 26, 2014

3 69Wednesday, March 26, 2014

0.1

CALDERA PRSNT#

A

Caldera(Echo graphic expander) block diagram

PCIE x4 TX/RX

PCIE x4 TX/RX

SMBUS

PCIE x4 Redriver
TI , DS8OPCI402

PCIE Mux Pericom ,
PI3PCIE3415ZHEX

PCIE x8 TX/RX

TO EC Control

CALDERA PWRGD

CALDERA_ON

Caidera connector

REFCLK +/-

CPERST#

CALDERA PRSNT#

Desktop PCIE x16 connector

PEG PRSNT_LOOPBACK

USB3.0

USB2.0

USB3.0 HUB
SMSC , USX2064

4x USB3.0

4 ports USB3.0

1 1

CALDERA PWRGD

19.5V IN

3.3V/5V always VR's(for USB wake support)

Dock +3.3VAW

Dock +5VAW

All POWER ready

Dock +3.3V

DC-DC VR's(main)

Dock +12V

VR_ON#

EC Control

BUTTON#
RED LED

WHITE LED

Removal Request
Button and WHTE/RED
on Connctor overmold

CALDERA_ON

CALDERA PRSNT#

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

A

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Title

Title

Title

Caldera block diagram

Caldera block diagram

Caldera block diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-B751P

LA-B751P

LA-B751P

Date: Sheet of

Date: Sheet of

Date: Sheet of

4 69Wednesday, March 26, 2014

4 69Wednesday, March 26, 2014

4 69Wednesday, March 26, 2014

0.1

0.1

0.1

A

Board ID Table for AD channel

Vcc 3.3V +/- 1%

100K +/- 1%Ra

Board ID

0
1
2
3
4
5
6
7
8
9

Rb V min

0 0.000V
12K +/- 1%
15K +/- 1%
20K +/- 1%
27K +/- 1%
33K +/- 1%
43K +/- 1%
56K +/- 1%
75K +/- 1% 1.398V
100K +/- 1%

10
11
12
13
14

160K +/- 1%
200K +/- 1%
240K +/- 1%
270K +/- 1%

15 330K +/- 1%
16
17
18

430K +/- 1%
560K +/- 1%
750K +/- 1%

19 NC

AD_BID

V typ

AD_BID

0.000V 0.300V

0.347V

0.354V

0.423V 0.430V

0.541V

0.691V

0.807V

0.550V

0.702V

0.819V

0.978V 0.992V

1.169V

1.185V

1.414V 1.430V

1.634V

1.650V

1.849V 1.865V

2.015V

2.185V

2.316V

2.031V

2.200V

2.329V

2.395V 2.408V

2.521V

2.667V

2.791V

2.533V

2.677V 0xCA - 0xD3

2.800V

2.905V 2.912V

3.300V

V

AD_BID

0.360V

0.438V

0.559V

0.713V

0.831V

1.006V

1.200V

1.667V

1.881V130K +/- 1%

2.046V

2.215V

2.343V

2.421V

2.544V

2.687V

2.808V

2.919V

3.300V

max

EC AD3

0x00 - 0x0B
0x0C - 0x1C
0x1D - 0x26
0x27 - 0x30
0x31 - 0x3B
0x3C - 0x46
0x47 - 0x54
0x55 - 0x64
0x65 - 0x76
0x77 - 0x87
0x88 - 0x96
0x97 - 0xA3
0xA4 - 0xAD
0xAE - 0xB7
0xB8 - 0xC0
0xC1 - 0xC9

0xD4 - 0xDC
0xDD - 0xE6
0xE7 - 0xFF3.000V

NVIDIA
Graphic

AMD
Graphic

Port1

Port2

Port3

Port4

Port5

Port6

Port0

Port1

Port2

Port3

Port4

Port5

Board ID TABLE

BDW

1 1

ID

NV AMD

0
1
2
3

10
11
12
13

PCB Revision

EVT-1
DVT-1
DVT-2
MP

Port6

Port7 / 8

Lane 1

Lane 2

USB3.0

Right side1

Right side2

Left side 1

Caldera

Left side 2

USB2.0

Right side1

Left side 1 (PowerShare)

Caldera

ELC

BT

Touch screen

Camera

Right side 2

Left side 2

PCI EXPRESS

Symbol Note :

: means Digital Ground

: means Analog Ground

Lane 3

Lane 4

CLOCK SIGNAL

CLKOUT_PCIE0

Lane 5

Lane 6

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

10/100/1000 LAN

M.2 Card WLAN

dGPU (N15P)

DGPU (Caldera)

A

SATA1

SATA2

SATA3

Compal Secret Data

Compal Secret Data

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

10/100/1000 LAN

M.2 Card WLAN

PCIE 4x MUX

SATA

HDDSATA0

NGFF SSD

NGFF SSD

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Notes list

Notes list

Notes list

LA-B751P

LA-B751P

LA-B751P

0.1

0.1

5 69Wednesday, March 26, 2014

5 69Wednesday, March 26, 2014

5 69Wednesday, March 26, 2014

0.1

5

4

3

2

1

D D

C C

SMBUS Address [0x9a]

Broadwell

AP2
AH1

AN1
AK1

AN1
AK1

79
80

MEM_SMBCLK
MEM_SMBDATA

SML0CLK
SML0DATA

SML1_SMBCLK

EC_SMB_CK2
EC_SMB_DA2

2.2K

2.2K

1K

1K

2.2K

2.2K

+3.3V_ALW_PCH

+3.3V_ALW_PCH

+3.3V_ALW_PCH

2.2K

2.2K

N-MOS
N-MOS

N-MOS
N-MOS

+3VALW

EC_SMB_CK2
EC_SMB_DA2SML1_SMBDATA

KBC

B B

KB9012A4

77
78

EC_SMB_CK1
EC_SMB_DA1

2.2K

2.2K

+3VALW

10K

10K

+3VS

DDR_XDP_WLAN_TP_SMBCLK
DDR_XDP_WLAN_TP_SMBDAT

0 ohm
0 ohm

0 ohm
0 ohm 0 ohm

N-MOS
N-MOS

0 ohm
0 ohm

SCL
SDA

N-MOS
N-MOS

2.2K

2.2K

VGA_SMB_CK2
VGA_SMB_DA2

PU701

11

POWER
Charger

10

DDR_XDP_SMBCLK_R1
DDR_XDP_SMBDAT_R1

CSCL CIICSCL
CSDA

0 ohm

CIICSDA

+3VS_VGA

UV28

T4

GPU

T3

SMBUS Address [0xXX]

SMBUS Address [0x12]

202
200

202
200

53
51

30
32

5
6

13
14

DIMMA

DIMMB

XDP1

M.2 NGFF

JTP

UV28
LVDS
Translator

SMBUS Address [A0]

SMBUS Address [A4]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

CPU,C
DDR,D

100 ohm
100 ohm

PD1

3 4
1

6

BAT_ALERT
BATT_PRS

PBATT1

3
5

SMBUS Address [0x16]

GPU,DP,HDMI,EDP,V
LAN,L
AUDIO,A
NGFF,N
USB,U

A A

CALDERA,M
HDD,S
ELC,E
FAN,F
TP,T
KBC,K
DC,O

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Compal Electronics, Inc.

SMBus block diagram

SMBus block diagram

SMBus block diagram

LA-B751P

LA-B751P

LA-B751P

1

6 69Wednesday, March 26, 2014

6 69Wednesday, March 26, 2014

6 69Wednesday, March 26, 2014

0.1

0.1

0.1

5

4

3

2

1

+VCOMP_OUT

PEG_COMP

D D

CPU1A

DMI_CRX_PTX_N0<17>
DMI_CRX_PTX_N1<17>
DMI_CRX_PTX_N2<17>
DMI_CRX_PTX_N3<17>

DMI_CRX_PTX_P0<17>
DMI_CRX_PTX_P1<17>
DMI_CRX_PTX_P2<17>
DMI_CRX_PTX_P3<17>

DMI_CTX_PRX_N0<17>
DMI_CTX_PRX_N1<17>
DMI_CTX_PRX_N2<17>
DMI_CTX_PRX_N3<17>

DMI_CTX_PRX_P0<17>
DMI_CTX_PRX_P1<17>
DMI_CTX_PRX_P2<17>

C C

B B

DMI_CTX_PRX_P3<17>

FDI_CSYNC<17>

FDI_INT<17>

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

FDI_CSYNC
FDI_INT

AB2

DMI_RXN0

AB3

DMI_RXN1

AC3

DMI_RXN2

AC1

DMI_RXN3

AB1

DMI_RXP0

AB4

DMI_RXP1

AC4

DMI_RXP2

AC2

DMI_RXP3

AF2

DMI_TXN0

AF4

DMI_TXN1

AG4

DMI_TXN2

AG2

DMI_TXN3

AF1

DMI_TXP0

AF3

DMI_TXP1

AG3

DMI_TXP2

AG1

DMI_TXP3

F11

FDI_CSYNC

F12

DISP_INT

HASWELL_BGA1364

HASWELL_BGA

DMI

PEG

FDI

Note:
Trace width=12 mils ,Spacing=15mils
Max length= 400 mils.

AH6

PEG_RCOMP

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8

PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

PEG_RXP0

PEG_RXP1

PEG_RXP2

PEG_RXP3

PEG_RXP4

PEG_RXP5

PEG_RXP6

PEG_RXP7

PEG_RXP8

PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

PEG_TXN0

PEG_TXN1

PEG_TXN2

PEG_TXN3

PEG_TXN4

PEG_TXN5

PEG_TXN6

PEG_TXN7

PEG_TXN8

PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8

PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

1 OF 12

PEG_COMP

E10
C10
B10
E9
D9
B9
L5
L2
M4
L4
M2
V5
V4
V1
Y3
Y2
F10
D10
A10
F9
C9
A9
M5
L1
M3
L3
M1
Y5
V3
V2
Y4
Y1
B6

PEG_HTX_GRX_N0

C5

PEG_HTX_GRX_N1

E6

PEG_HTX_GRX_N2

D4

PEG_HTX_GRX_N3

G4

PEG_HTX_GRX_N4

E3

PEG_HTX_GRX_N5

J5

PEG_HTX_GRX_N6

G3

PEG_HTX_GRX_N7

J3

PEG_HTX_GRX_N8

J2

PEG_HTX_GRX_N9

T6

PEG_HTX_GRX_N10

R6

PEG_HTX_GRX_N11

R2
R4
T4
T1
C6

PEG_HTX_GRX_P0

B5

PEG_HTX_GRX_P1

D6

PEG_HTX_GRX_P2

E4

PEG_HTX_GRX_P3

G5

PEG_HTX_GRX_P4

E2

PEG_HTX_GRX_P5

J6

PEG_HTX_GRX_P6

G2

PEG_HTX_GRX_P7

J4

PEG_HTX_GRX_P8

J1

PEG_HTX_GRX_P9

T5

PEG_HTX_GRX_P10

R5

PEG_HTX_GRX_P11

R1
R3
T3
T2

12

RC124.9_0402_1%

PEG_GTX_HRX_N0
PEG_GTX_HRX_N1
PEG_GTX_HRX_N2
PEG_GTX_HRX_N3
PEG_GTX_HRX_N4
PEG_GTX_HRX_N5
PEG_GTX_HRX_N6
PEG_GTX_HRX_N7
PEG_GTX_HRX_N8

PEG_GTX_HRX_N9
PEG_GTX_HRX_N10
PEG_GTX_HRX_N11

PEG_GTX_HRX_P0

PEG_GTX_HRX_P1

PEG_GTX_HRX_P2

PEG_GTX_HRX_P3

PEG_GTX_HRX_P4

PEG_GTX_HRX_P5

PEG_GTX_HRX_P6

PEG_GTX_HRX_P7

PEG_GTX_HRX_P8

PEG_GTX_HRX_P9

PEG_GTX_HRX_P10

PEG_GTX_HRX_P11

1 2

CC1 0.22U_0402_16 V7K

1 2

CC2 0.22U_0402_16 V7K

1 2

CC3 0.22U_0402_16 V7K

1 2

CC4 0.22U_0402_16 V7K

1 2

CC5 0.22U_0402_16 V7K

1 2

CC6 0.22U_0402_16 V7K

1 2

CC7 0.22U_0402_16 V7K

1 2

CC8 0.22U_0402_16 V7K

1 2

CC9 0.22U_0402_16 V7K

1 2

CC10 0.22U_0402_16V7K

1 2

CC11 0.22U_0402_16V7K

1 2

CC12 0.22U_0402_16V7K

1 2

CC13 0.22U_0402_16V7K

1 2

CC14 0.22U_0402_16V7K

1 2

CC15 0.22U_0402_16V7K

1 2

CC16 0.22U_0402_16V7K

1 2

CC17 0.22U_0402_16V7K

1 2

CC18 0.22U_0402_16V7K

1 2

CC19 0.22U_0402_16V7K

1 2

CC20 0.22U_0402_16V7K

1 2

CC21 0.22U_0402_16V7K

1 2

CC22 0.22U_0402_16V7K

1 2

CC23 0.22U_0402_16V7K

1 2

CC24 0.22U_0402_16V7K

Near MXM Connector x4 Gen3

PEG_HTX_C_GRX_N0
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_N8

PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_N11

PEG_HTX_C_GRX_P0

PEG_HTX_C_GRX_P1

PEG_HTX_C_GRX_P2

PEG_HTX_C_GRX_P3

PEG_HTX_C_GRX_P4

PEG_HTX_C_GRX_P5

PEG_HTX_C_GRX_P6

PEG_HTX_C_GRX_P7

PEG_HTX_C_GRX_P8

PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_P11

PEG_GTX_HRX_P[0..7] <46>
PEG_GTX_HRX_N[0..7] <46>

PEG_HTX_C_GRX_P[0..7] <46>
PEG_HTX_C_GRX_N[0..7] <46>

PEG_GTX_HRX_P[8..11] <41>
PEG_GTX_HRX_N[8..11] <41>

PEG_HTX_C_GRX_P[8..11] <41>
PEG_HTX_C_GRX_N[8..11] <41>

N5P-GX

Caldera

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(1/7) DMI,FDI,PEG

PROCESSOR(1/7) DMI,FDI,PEG

PROCESSOR(1/7) DMI,FDI,PEG

LA-B751P

LA-B751P

LA-B751P

1

of

7 69Wednesday, March 26, 2014

7 69Wednesday, March 26, 2014

7 69Wednesday, March 26, 2014

0.1

0.1

0.1

5

D D

4

+VCCIO_OUT

XDP@

0.1U_0402_25V6K~D

1

CC25

2

Place near JXDP1

+3V_PCH

1 2

RC3 1K_0402_1%~D@

CPU_PWR_DEBU G<12>

PBTN_OUT#<17,43>

IMVP_PWRGD<17,65>

PCH_SMBDATA<14,15,19,36>
PCH_SMBCLK<14,15,19,36>

SYS_PWROK_XDP

H_CPUPWRGD

RC5 need to close to JCPU1

RC4 1K_0402_1%~DXDP@
RC5 0_0402_5%~DXDP@

RC6 0_0402_5%~DXDP@
RC8 0_0402_5%~DXDP@

RC9 0_0402_5%~DXDP@
RC10 0_0402_5%~DXDP@

0.1U_0402_25V6K~D

1

CC26

2

XDP@

CFG3<11>

1 2
1 2

1 2
1 2

1 2
1 2

3

RC2 1K_0402_1 %~DXDP@

2

+VCCIO_OUT

JXDP1

1

GND0

XDP_PREQ#_R
XDP_PRDY#

CFG0<11>
CFG1<11>

CFG2<11>

1 2

CFG4<11>
CFG5<11>

CFG6<11>
CFG7<11>

CFG0
CFG1

CFG2 CFG10
CFG3_R

XDP_OBS0
XDP_OBS1

CFG4
CFG5

CFG6
CFG7

H_CPUPWRGD_XDP
CFD_PWRBTN#_X DP

CPU_PWR_DEBU G_R XDP_RST#_R
SYS_PWROK_XDP

DDR_XDP_SMBDAT_R 1
DDR_XDP_SMBCLK_R 1

XDP_TCLK_R

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

GND17

CONN@

GND1

GND3

GND5

GND7

GND9

TMS

+VCCIO_OUT

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

TD0

54
56

TDI

58
60

CFG17
CFG16

CFG8
CFG9

CFG11

CFG19
CFG18

CFG12
CFG13

CFG14
CFG15

CLK_XDP
CLK_XDP#

XDP_DBRESET#

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
CFG3_R

CFG17 <11>
CFG16 <11>

CFG8 <11>
CFG9 <11>

CFG10 <11>
CFG11 <11>

CFG19 <11>
CFG18 <11>

CFG12 <11>
CFG13 <11>

CFG14 <11>
CFG15 <11>

1 2

RH1 0_0402_5%~DXDP@

1 2

RH2 0_0402_5%~DXDP@

RC7 1K_0402_1%~D

XDP@

12

CPU_PLTRST#

1

CLK_CPU_ITP <18>
CLK_CPU_ITP# <18>

C C

H_PROCHOT#<43,58,59>

H_CPUPWRGD<21>

10K_0402_5%

CAD Note:

B B

Avoid stub in the PWRGD path
while placing resistor RC5

RC11

62_0402_5%

RC18

+VCCIO_OUT

12

1 2

R2 56_0402_5%

1

CC29
100P_0402_50V8J

2

1 2

Note:
PECI/THERMTRIP:
Trace width=4 mils ,Spacing=18mil

@ESD@

ESD 9/5

Zo=50 ohm

CLK_CPU_SSC_DPLL#<18>
CLK_CPU_SSC_DPLL<18>

H_PECI<43>

H_THERMTRIP#<21>

H_PM_SYNC<17>

CPU_PLTRST#<21>

CLK_CPU_DPLL#<18>
CLK_CPU_DPLL<18>

CLK_CPU_DMI#<18>
CLK_CPU_DMI<18>

H_CATERR#

T1

H_PECI

H_PROCHOT#_R
H_THERMTRIP#

H_PM_SYNC
H_CPUPWRGD
PM_SYS_PWRGD_BUF

CLK_CPU_DPLL#
CLK_CPU_DPLL
CLK_CPU_SSC_DPLL#
CLK_CPU_SSC_DPLL
CLK_CPU_DMI#
CLK_CPU_DMI

CPU_PLTRST#

CPU1B

C51

PROC_DETECT

G50

CATERR

G51

PECI

E50

PROCHOT

D53

THERMTRIP

D52

PM_SYNC

F50

PWRGOOD

AP48

SM_DRAMPWR OK

L54

PLTRSTIN

AC6

DPLL_REF_CLKN

AE6

DPLL_REF_CLKP

V6

SSC_DPLL_REF_CLKN

Y6

SSC_DPLL_REF_CLKP

AB6

BCLKN

AA6

BCLKP

HASWELL_BGA1364

HASWELL_BGA

MISC

THERMAL CLOCK

PWR

2 OF 12

SM_RCOMP0
SM_RCOMP1

DDR3L

SM_RCOMP2

SM_DRAMRST

JTAG

PRDY
PREQ

TCK
TMS

TRST

TDO
DBR

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

TDI

BB51

SM_RCOMP0

BB53

SM_RCOMP1

BB52

SM_RCOMP2

BE51

H_DRAMRST#

N53

XDP_PRDY#

N52

XDP_PREQ#

N54

XDP_TCLK

M51

XDP_TMS

M53

XDP_TRST#

N49

XDP_TDI_R

M49

XDP_TDO_R

F53

XDP_DBRESET#_R

R51

XDP_BPM#0_R

R50

XDP_BPM#1_R

P49

XDP_BPM#2

N50

XDP_BPM#3

R49

XDP_BPM#4

P53

XDP_BPM#5

U51

XDP_BPM#6

P51

XDP_BPM#7

remove by SIT phase

1 2

RC13 0_0402_5%@

1 2

RC14 0_0402_5%@

1 2

RC15 0_0402_5%@

1 2

RC16 0_0402_5%@

1 2

RC17 0_0402_5%@

1 2

RC19 0_0402_5%@

1 2

RC20 0_0402_5%@

T2
T3

T4
T5
T6
T7
T8
T9

SM_DRAMPWROK with DDR Power Gating Topology

+3V_PCH +3V_PCH

@

+1.35V_CPU_VDDQ

12

RC26

1.8K_0402_1%

PM_SYS_PWRGD_BUF

12

RC30

3.3K_0402_1%

1

2

UC1

5

DS3@

P

B

O

A

G

74AHC1G09GW_TSSOP5

3

1 2

NODS3@

CC30

0.1U_0402_16V7K

4

12

12

DS3@

DS3@

CC31

DS3@

RC25
100K_0402_5%

1

2

RC31 0_0402_5%

1

2

RC24

100K_0402_5%

SYS_PWROK<12,17,43>

PM_DRAM_PWR GD<17>

A A

0.01U_0402_16V7K

Follow Intel schematic
review-0930

XDP_PREQ#_R
XDP_TCLK_R

XDP_TDI
XDP_TDO
XDP_DBRESET#

XDP_OBS0
XDP_OBS1

1

CC27
100P_0402_50V8J

2

@ESD@

ESD 9/5

XDP_DBRESET# <17>

+1.35V

RC12

@

470_0402_5%

1 2

0_0402_5%

1 2

R1

1

0.1U_0402_16V7K
CC28

@ESD@

2

Place near SODIMM side,

DDR3 COMPENSATION SIGNALS

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mils

1 2

RC21 100_0402_1%

1 2

RC22 75_0402_1%

1 2

RC23 100_0402_1%

PU/PD for JTAG signals

XDP_DBRESET#_R

XDP_TMS
XDP_TDI_R

XDP_TDO_R
XDP_TCLK
XDP_TRST#

RC27 1K_0402_5%

RC28 51_0402_5%@
RC29 51_0402_5%@

TMS/TDI no require pull high on Check list

12

12
12

RP1

1 8
2 7
3 6
4 5

51_0804_8P4R_5%

DDR3_DRAMRST# <14,15>

+3VS

+1.05VS

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Title

Title

Title

PROCESSOR(2/7) PM,XDP,CLK

PROCESSOR(2/7) PM,XDP,CLK

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-B751P

LA-B751P

LA-B751P

Date: Sheet

Date: Sheet of

2

Date: Sheet of

1

8 69Wednesday, March 26, 2014

8 69Wednesday, March 26, 2014

8 69Wednesday, March 26, 2014

0.1

0.1

0.1

of

5

4

3

2

1

D D

C C

B B

DDR_A_D[0..63]<14> DDR_B_D[0..63]<15>

+SM_VREF
+SA_DIMM_VREFDQ
+SB_DIMM_VREFDQ

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

+SM_VREF
+SA_DIMM_VREFDQ
+SB_DIMM_VREFDQ

AH54
AH52
AK51
AK54
AH53
AH51
AK52
AK53
AN54
AN52
AR51
AR53
AN53
AN51
AR52
AR54
AV52
AV53

AY52

AY51
AV51
AV54

AY54

AY53

AY47

AY49
BA47
BA45

AY45

AY43
BA49
BA43

BF14
BC14
BC11

BF11
BE14
BD14
BD11
BE11

AW3

AW2

AW4

AW1

BC53

BC9
BE9
BE6
BC6
BD9
BF9
BE5
BD6
BB4
BC2

BB3
BB2

AU3
AU1
AR1
AR4
AU2
AU4
AR2
AR3

AM6
AR6
AN6

CPU1C

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

SM_VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

RSVD

3 OF 12

HASWELL_BGA

RSVD

SA_CKN0

SA_CK0
SA_CKE0
SA_CKN1

SA_CK1
SA_CKE1
SA_CKN2

SA_CK2
SA_CKE2
SA_CKN3

SA_CK3
SA_CKE3

SA_CS#0
SA_CS#1
SA_CS#2
SA_CS#3
SA_ODT0
SA_ODT1
SA_ODT2
SA_ODT3

SA_BS0

SA_BS1

SA_BS2

SA_RAS

SA_WE

SA_CAS

SA_MA0

SA_MA1

SA_MA2

SA_MA3

SA_MA4

SA_MA5

SA_MA6

SA_MA7

SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7

RSVD
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

HASWELL_BGA1364

VSS

BD31
BE25

M_CLK_DDR#0

BF25

M_CLK_DDR0

BE34

DDR_CKE0_DIMMA

BD25

M_CLK_DDR#1

BC25

M_CLK_DDR1

BF34

DDR_CKE1_DIMMA

BE23
BF23
BC34
BD23
BC23
BD34

BE16

DDR_CS0_DIMMA#

BC17

DDR_CS1_DIMMA#

BE17
BD16
BC16

M_ODT0

BF16

M_ODT1

BF17
BD17
BC20

DDR_A_BS0

BD21

DDR_A_BS1

BD32

DDR_A_BS2

BC21
BF20

DDR_A_RAS#

BF21

DDR_A_WE#

BE21

DDR_A_CAS#

BD28

DDR_A_MA0

BD27

DDR_A_MA1

BF28

DDR_A_MA2

BE28

DDR_A_MA3

BF32

DDR_A_MA4

BC27

DDR_A_MA5

BF27

DDR_A_MA6

BC28

DDR_A_MA7

BE27

DDR_A_MA8

BC32

DDR_A_MA9

BD20

DDR_A_MA10

BF31

DDR_A_MA11

BC31

DDR_A_MA12

BE20

DDR_A_MA13

BE32

DDR_A_MA14

BE31

DDR_A_MA15

AJ52

DDR_A_DQS#0

AP53

DDR_A_DQS#1

AW52

DDR_A_DQS#2

AY46

DDR_A_DQS#3

BD12

DDR_A_DQS#4

BE7

DDR_A_DQS#5

BA3

DDR_A_DQS#6

AT2

DDR_A_DQS#7

AW39
AJ53

DDR_A_DQS0

AP52

DDR_A_DQS1

AW53

DDR_A_DQS2

BA46

DDR_A_DQS3

BE12

DDR_A_DQS4

BD7

DDR_A_DQS5

BA2

DDR_A_DQS6

AT3

DDR_A_DQS7

AW40

BA40
AY40
BA39
AY39
AV40
AU40
AV39
AU39

M_CLK_DDR#0 <14>
M_CLK_DDR0 < 14>
DDR_CKE0_DIMMA <14>
M_CLK_DDR#1 <14>
M_CLK_DDR1 < 14>
DDR_CKE1_DIMMA <14>

DDR_CS0_DIMMA# <14>
DDR_CS1_DIMMA# <14>

M_ODT0 <14>
M_ODT1 <14>

DDR_A_BS0 <14>
DDR_A_BS1 <14>
DDR_A_BS2 <14>

DDR_A_RAS# <14>
DDR_A_WE# <14>
DDR_A_CAS# <14>

DDR_A_MA[0..15] <14>

DDR_A_DQS#[0..7] <14>

DDR_A_DQS[0..7] <14>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AC54
AC52
AE51
AE54
AC53
AC51
AE52
AE53
AU47
AU49
AV43
AV45
AU43
AU45
AV47
AV49
BC49
BE49
BD47
BC47
BD49
BD50
BE47

BF47
BE44
BD44
BC42

BF42

BF44
BC44
BD42
BE42
BA16
AU16
BA15
AV15

AY16
AV16

AY15
AU15
AU12

AY12
BA10
AU10
AV12
BA12

AY10
AV10

AU8

AU6

AM2
AM3

AM1
AM4

4 OF 12

HASWELL_BGA

RSVD

SB_CKN0

SB_CK0
SB_CKE0
SB_CKN1

SB_CK1
SB_CKE1
SB_CKN2

SB_CK2
SB_CKE2
SB_CKN3

SB_CK3
SB_CKE3

SB_CS#0
SB_CS#1
SB_CS#2
SB_CS#3

SB_ODT0
SB_ODT1
SB_ODT2
SB_ODT3

SB_BS0
SB_BS1
SB_BS2

SB_RAS

SB_WE

SB_CAS

SB_MA0

SB_MA1

SB_MA2

SB_MA3

SB_MA4

SB_MA5

SB_MA6

SB_MA7

SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7

RSVD
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

HASWELL_BGA1364

VSS

AY36
AW27

M_CLK_DDR#2

AV27

M_CLK_DDR2

AU36

DDR_CKE2_DIMMB

AW26

M_CLK_DDR#3

AV26

M_CLK_DDR3

AU35

DDR_CKE3_DIMMB

BA26
AY26
AV35
BA27
AY27
AV36

BA20

DDR_CS2_DIMMB#

AY19

DDR_CS3_DIMMB#

AU19
AW20

AY20

M_ODT2

BA19

M_ODT3

AV19
AW19
AY23

DDR_B_BS0

BA23

DDR_B_BS1

BA36

DDR_B_BS2

AU30
AV23

DDR_B_RAS#

AW23

DDR_B_WE#

AV20

DDR_B_CAS#

BA30

DDR_B_MA0

AW30

DDR_B_MA1

AY30

DDR_B_MA2

AV30

DDR_B_MA3

AW32

DDR_B_MA4

AY32

DDR_B_MA5

AT30

DDR_B_MA6

AV32

DDR_B_MA7

BA32

DDR_B_MA8

AU32

DDR_B_MA9

AU23

DDR_B_MA10

AY35

DDR_B_MA11

AW35

DDR_B_MA12

AU20

DDR_B_MA13

AW36

DDR_B_MA14

BA35

DDR_B_MA15

AD52

DDR_B_DQS#0

AU46

DDR_B_DQS#1

BD48

DDR_B_DQS#2

BD43

DDR_B_DQS#3

AW16

DDR_B_DQS#4

AW10

DDR_B_DQS#5

AW8

DDR_B_DQS#6

AL2

DDR_B_DQS#7

BE38
AD53

DDR_B_DQS0

AV46

DDR_B_DQS1

BE48

DDR_B_DQS2

BE43

DDR_B_DQS3

AW15

DDR_B_DQS4

AW12

DDR_B_DQS5

AW6

DDR_B_DQS6

AL3

DDR_B_DQS7

BD38

BF39
BE39
BF37
BE37
BD39
BC39
BC37
BD37

M_CLK_DDR#2 <15>
M_CLK_DDR2 <15>
DDR_CKE2_DIMMB <15>
M_CLK_DDR#3 <15>
M_CLK_DDR3 <15>
DDR_CKE3_DIMMB <15>

DDR_CS2_DIMMB# <15>
DDR_CS3_DIMMB# <15>

M_ODT2 <15>
M_ODT3 <15>

DDR_B_BS0 <15>
DDR_B_BS1 <15>
DDR_B_BS2 <15>

DDR_B_RAS# <15>
DDR_B_WE# <15>
DDR_B_CAS# <15>

DDR_B_MA[0..15] <15>

DDR_B_DQS#[0..7] <15>

DDR_B_DQS[0..7] <15>

CPU1D

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48

BA8

SB_DQ49

AV6

SB_DQ50

BA6

SB_DQ51

AV8

SB_DQ52

AY8

SB_DQ53
SB_DQ54

AY6

SB_DQ55
SB_DQ56
SB_DQ57

AK1

SB_DQ58

AK4

SB_DQ59
SB_DQ60
SB_DQ61

AK2

SB_DQ62

AK3

SB_DQ63

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

PROCESSOR(3/7) DDRIII

PROCESSOR(3/7) DDRIII

PROCESSOR(3/7) DDRIII

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-B751P

LA-B751P

LA-B751P

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

1

9 69Wednesday, March 26, 2014

9 69Wednesday, March 26, 2014

9 69Wednesday, March 26, 2014

0.1

0.1

0.1

5

D D

4

3

2

1

COMPENSATION PU FOR eDP

CPU1J

CPU_HDMI_N2<27>
CPU_HDMI_P2<27>
CPU_HDMI_N1<27>

HDMI

C C

mDP

CPU_HDMI_P1<27>
CPU_HDMI_N0<27>
CPU_HDMI_P0<27>
CPU_HDMI_N3<27>
CPU_HDMI_P3<27>

CPU_mDP_N0<26>
CPU_mDP_P0<26>
CPU_mDP_N1<26>
CPU_mDP_P1<26>
CPU_mDP_N2<26>
CPU_mDP_P2<26>
CPU_mDP_N3<26>
CPU_mDP_P3<26>

CPU_HDMI_N2
CPU_HDMI_P2
CPU_HDMI_N1
CPU_HDMI_P1
CPU_HDMI_N0
CPU_HDMI_P0
CPU_HDMI_N3
CPU_HDMI_P3

CPU_mDP_N0
CPU_mDP_P0
CPU_mDP_N1
CPU_mDP_P1
CPU_mDP_N2
CPU_mDP_P2
CPU_mDP_N3
CPU_mDP_P3

C25

DDIB_TXN0

D25

DDIB_TXP0

A25

DDIB_TXN1

B25

DDIB_TXP1

C24

DDIB_TXN2

D24

DDIB_TXP2

A24

DDIB_TXN3

B24

DDIB_TXP3

C21

DDIC_TXN0

D21

DDIC_TXP0

A21

DDIC_TXN1

B21

DDIC_TXP1

C20

DDIC_TXN2

D20

DDIC_TXP2

A20

DDIC_TXN3

B20

DDIC_TXP3

C16

DDID_TXN2

D16

DDID_TXP2

A16

DDID_TXN3

B16

DDID_TXP3

C17

DDID_TXN0

D17

DDID_TXP0

A17

DDID_TXN1

B17

DDID_TXP1

HASWELL_BGA1364

HASWELL_BGA

EDP_AUXN

EDP_AUXP

EDP_HPD

EDP_TXN0
EDP_TXN1
EDP_TXP0
EDP_TXP1

EDP_RCOMP

EDP_DISP_UTIL

FDI_TXN0
FDI_TXP0
FDI_TXN1
FDI_TXP1

10 OF 12

F15
F14
E14

C14
A12
D14
B12

AG6
E12

C12
D12
A14
B14

EDP Panel

CPU_EDP_AUX#
CPU_EDP_AUX
EDP_HPD_R

CPU_EDP_TX0N
CPU_EDP_TX1N
CPU_EDP_TX0P
CPU_EDP_TX1P

EDP_COMP
EDP_DISP_UTIL

CPU_EDP_TX2N
CPU_EDP_TX2P
CPU_EDP_TX3N
CPU_EDP_TX3P

1 2

RC33 0_0402_5%@

CPU_EDP_AUX# <25>
CPU_EDP_AUX <25>

CPU_EDP_TX0N <25>
CPU_EDP_TX1N <25>
CPU_EDP_TX0P <25>
CPU_EDP_TX1P <25>

CPU_EDP_TX2N <25>
CPU_EDP_TX2P <25>
CPU_EDP_TX3N <25>
CPU_EDP_TX3P <25>

PCH_INV_PWM <17,25>

EDP_COMP

Note:
Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.

HPD INVERSION FOR EDP

+VCCIO_OUT

RC34

1 2

EDP_HPD_R

QC1

13

LBSS138LT1G_SOT-23-3

D

S

+VCOMP_OUT

12

RC3224.9_0402_1%

10K_0402_5%

2

G

12

RC35

100K_0402_5%

CPU_EDP_HPD <25>

HPD is a active-high signal from device.

B B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

The HPD processor input is
active-low signal.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/7) eDP,DP and HDMI

PROCESSOR(4/7) eDP,DP and HDMI

PROCESSOR(4/7) eDP,DP and HDMI

LA-B751P

LA-B751P

LA-B751P

1

10 69Wednesday, March 26, 2014

10 69Wednesday, March 26, 2014

10 69Wednesday, March 26, 2014

0.1

0.1

0.1

5

4

3

2

1

CPU1K

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

BC1

BC54

BD1

BD54

BE1
BE2

BE3
BE52
BE53
BE54

BF2

BF3

BF4

A51
A52
A53

B52
B53
B54

BD3

G21
G24

G19

AG49
AD49
AC49
AE49

AB49

W51

W53
U53

R53
R52

A3
A4

B2
B3

BE4

F6

G6

F21

F51
F52
F22

L52
L53

L51

F24
F25
F20

Y50

V51

Y49
Y54
Y53

V54

L50
L49

E5

CPU1L

RSVD
RSVD

RSVD
RSVD
RSVD

RSVD
RSVD

RSVD
RSVD
RSVD

RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

HASWELL_BGA1364

T12

D D

C C

1 2

RC38 49.9_0402_1%

1 2

RC39 49.9_0402_1%

1 2

RC40 49.9_0402_1%

B B

A A

H_CPU_TESTLO

CFG_RCOMP

H_CPU_RSVD

T14

T16
T17

T18
T19

+VCC_CORE

T25
T27

T30

T32
T33

CFG0<8>
CFG1<8>
CFG2<8>
CFG3<8>
CFG4<8>
CFG5<8>
CFG6<8>
CFG7<8>
CFG8<8>
CFG9<8>
CFG10<8>
CFG11<8>
CFG12<8>
CFG13<8>
CFG14<8>
CFG15<8>

T37
T39
T40

T41

T43

T46
T47

T48

H_CPU_RSVD

H_CPU_TESTLO

B3_A3

A52_B52
A53_B53

C3_B2
B3_A3

A52_B52
A53_B53
B54_C54

BE1_BD1

BE54_BD54
BE1_BD1
BE2_BF2
BE3_BF3
BE52_BF52
BE53_BF53
BE54_BD54
BE2_BF2
BE3_BF3

HASWELL_BGA

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP
TESTLOW_F21
VSS
VSS
VSS
VCC

RSVD_TP
RSVD_TP

RSVD_TP

RSVD_TP
RSVD_TP
TESTLOW_F20

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

RSVD
RSVD
RSVD

HASWELL_BGA1364

HASWELL_BGA

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

CFG_RCOMP

CFG16
CFG18
CFG17
CFG19

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

RSVD

RSVD_TP
RSVD_TP

VSS
VSS

VSS
VSS

RSVD
RSVD
RSVD

11 OF 12

12 OF 12

RSVD
RSVD
RSVD

RSVD
RSVD
RSVD

RSVD
RSVD

RSVD

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

F1
E1
A5
A6

R54
Y52
V53
Y51
V52

B50
AH49
AM48
AU27
AU26
BD4
BC4
AL6
F8

F16

G12
G10

H54
H53

H51
H52

N51
G53
H50

CFG_RCOMP
CFG16
CFG17
CFG18
CFG19

BF51
BF52

BE52_BF52

BF53

BE53_BF53

C1

C1_C2

C2

C1_C2

C3

C3_B2

C54

B54_C54

D1

D54

AN35
AN37
AF9
AE9
G14
G17
AD45
AG45

T10
T11
T13
T15

CFG16 <8>
CFG17 <8>
CFG18 <8>
CFG19 <8>

T20
T21
T22
T23
T24
T26
T28
T29
T31

T34

T35
T36

T38

T42

T44

T45

CFG Straps for Processor

CFG2

RC36

1K_0402_1%

@

1 2

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

Embedded Display Port Presence Strap

CFG4

PCIE Port Bifurcation Straps

CFG[6:5]

PEG DEFER TRAINING

CFG7

1: Normal Operation; Lane # definition matches
socket pin map definition

*

0:Lane Reversed

CFG4

12

RC37
1K_0402_1%

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

*

CFG5

CFG6

RC41

1K_0402_1%

RC42

1K_0402_1%

1 2

1 2

11: (Default) x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled

01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

*

CFG7

RC43

@

1K_0402_1%

1 2

1: (Default) PEG Train immediately following xxRESETB
de assertion

*

0: PEG Wait for BIOS for training

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(5/7) RSVD,CFG

PROCESSOR(5/7) RSVD,CFG

PROCESSOR(5/7) RSVD,CFG

LA-B751P

LA-B751P

LA-B751P

1

11 69Wednesday, March 26, 2014

11 69Wednesday, March 26, 2014

11 69Wednesday, March 26, 2014

0.1

0.1

0.1

5

+1.35V_CPU_VDDQ Source

Note:
Intel Shark Bay
Removed the S3 power reduction circuit.

+1.35V +1.35V_CPU_VDDQ

D D

VCC_SENSE

Note:
0 ohm Resistor should be placed
cloose to CPU

VCCSENSE<65>

VSSSENSE<65>

C C

B B

+VCCIO_OUT

2.2U_0603_10V6K

1

2

VDDQ DECOUPLING (Follow INTEL DG)

+1.35V_CPU_VDDQ

A A

VCCSENSE VCCSENSE_R

VSSSENSE

Note:
Place the UP resistor close to CPU
RC47 Close to CPU 300-1500mil

+1.05VS +VCCIO_OUT

CC32

Close to CPU

10U_0603_6.3V6M

CC33

1

1

@

2

2

V0.1A

1

2

Close to CPU Close to CPU

JP1 @

JUMP_43X118

@

JP2

JUMP_43X118

+VCC_CORE

100_0402_1%

12

RC44

RC45 0_0402_5%

RC46 0_0402_5%

100_0402_1%

12

R3

SVID ALERT

VIDALERT_N<65>
VIDSCLK<65>
VIDSOUT<65>

SVID DATA

Note:
Place the UP resistor close to CPU
RC49 Close to CPU 300-1500mil

12

RC51 0_0603_5%@

RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES

10U_0603_6.3V6M

22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CC34

C3

@

CC36

CC35

1

1

2

1

2

5

1

@

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C5

C4

1

1

@

2

2

V0.1A

12

12

12

@

12

VSSSENSE_R

@

+VCCIO_OUT

12

Close to CPU Close to CPU

10U_0603_6.3V6M

10U_0603_6.3V6M

CC37

CC38

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C7

C6

1

1

@

@

2

2

+1.35V

VSSSENSE_R <13>

Broadwell/Haswe ll

HSW_BDW
Compatibility CKT

RC47
75_0402_1%

1 2

RC48 43_0402_5%

12

RC49
130_0402_1%

+VCCIO_OUT

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

22U_0805_6.3V6M

C8

10U_0603_6.3V6M

CC40

CC39

CC41

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

CC47

CC48

1

1

@

2

2

C1

0.1U_0402_16V7K

1 2

C2

0.1U_0402_16V7K

1 2

150_0402_1%

RC50

RC52

10K_0402_5%

10U_0603_6.3V6M

1

@

2

22U_0805_6.3V6M

CC49

1

2

@

@

+1.35V_CPU_VDDQ

CPU_PWR_DEBUG<8>

+1.05VS

1 2

@

1 2

CC42

22U_0805_6.3V6M

CC50

1

2

4

+1.35V_CPU_VDDQ

+VCCIO_OUT
+VCCIO2PCH
+VCOMP_OUT

CPU_PWR_DEBUG

330U_D2_2V_Y

330U_D2_2V_Y

1

1

CC43

+

+

2

2

V0.1A

22U_0805_6.3V6M

CC51

1

2

4

CPU1E

VCCSENSE_R

IVR_ERROR
IST_TRIGGER

AR29
AR31
AR33
AT13
AT19
AT23
AT27
AT32
AT36

AV37
AW22
AW25
AW29
AW33

AY18

BB21

BB22

BB26

BB27

BB30

BB31

BB34

BB36

BD22

BD26

BD30

BD33

BE18

BE22

BE26

BE30

BE33

AN31

AN22

AN18

AN33

AR49

AM49

AN49

AJ49
AG50
AK49

AJ50
AP49
AB50
AP50
AD50
AM50

AA46
AA47

RC54 0_0603_5%BDW@

J17
J21
J26
J31

L6

M6

C50

AH9

D51
F17
AK6

W9
J12

J53
J52
J50

B51
F19
E52
V49
U49

W49

V50

A36
A38
A39
A42
A43
A45
A46
A48

AA8
AA9

T49
T50
T51
T52

T53

+VCC_CORE

T54
T55

T56

T57
T58

T59

H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT

CPU_PWR_DEBUG

T60
T61
T62
T63

+VCC_CORE

CC44

@

HSW_BDW compatibility CKT

+1.05VS +VCCIO2PCH

place CC45 close to CPU

RSVD
RSVD
RSVD
RSVD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

RSVD
VCC
VCC
RSVD
RSVD

VCC_SENSE
RSVD
VCCIO_OUT
RSVD
VCOMP_OUT
RSVD
RSVD
RSVD
RSVD

VIDALERT
VIDSCLK
VIDSOUT

VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

HASWELL_BGA1364

12

HASWELL_BGA

5 OF 12

0.1U_0402_10V7K

BDW@

1

CC45

2

3

+VCC_CORE

B43

VCC

B45

VCC

B46

VCC

B48

VCC

C27

VCC

C28

VCC

C31

VCC

C32

VCC

C34

VCC

C36

VCC

C38

VCC

C39

VCC

C42

VCC

C43

VCC

C45

VCC

C46

VCC

C48

VCC

D27

VCC

D28

VCC

D31

VCC

D32

VCC

D34

VCC

D36

VCC

D38

VCC

D39

VCC

D42

VCC

D43

VCC

D45

VCC

D46

VCC

D48

VCC

E27

VCC

E28

VCC

E31

VCC

E32

VCC

E34

VCC

E36

VCC

E38

VCC

E39

VCC

E42

VCC

E43

VCC

E45

VCC

E46

VCC

E48

VCC

F27

VCC

F28

VCC

F31

VCC

F32

VCC

F34

VCC

F36

VCC

F38

VCC

F39

VCC

F42

VCC

F43

VCC

F45

VCC

F46

VCC

F48

VCC

G27

VCC

G29

VCC

G31

VCC

G32

VCC

G34

VCC

G36

VCC

G38

VCC

G39

VCC

G42

VCC

G43

VCC

G45

VCC

G46

VCC

G48

VCC

H11

VCC

H12

VCC

H13

VCC

H14

VCC

H16

VCC

H17

VCC

H18

VCC

H19

VCC

H20

VCC

H21

VCC

H23

VCC

H24

VCC

H25

VCC

H26

VCC

H27

VCC

H29

VCC

FC_D5
FC_D3

BDW@

22U_0805_6.3V6M

1

CC46

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

Broadwell/Haswe ll

D5

FC_D5

D3

FC_D3

HSW_BDW compatibility CKT

FC_D3

+VCCIO2PCH

12

BDW@

RC53

6.04K_0402_1%

12

BDW@

RC55

2.67K_0402_1%

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

RC54

CC45

CC46

RC53

RC55

RESET_OUT#

HSW BDW

X

X

X

X

X

SYS_PWROK <17,43,8>

Compal Secret Data

Compal Secret Data

Compal Secret Data

2

V

V

V

V

V

Deciphered Date

Deciphered Date

Deciphered Date

2

55A

1

HASWELL_BGA

CPU1F

AB45

VCC

AB46

VCC

AB8

VCC

AC46

VCC

AC47

VCC

AC8

VCC

AC9

VCC

AD46

VCC

AD8

VCC

AE46

VCC

AE47

VCC

AE8

VCC

AF8

VCC

AG46

VCC

AG8

VCC

AH46

VCC

AH47

VCC

AH8

VCC

AJ45

VCC

AJ46

VCC

AK46

VCC

AK47

VCC

AK8

VCC

AL45

VCC

AL46

VCC

AL8

VCC

AL9

VCC

AM46

VCC

AM47

VCC

AM8

VCC

AM9

VCC

AN10

VCC

AN12

VCC

AN13

VCC

AN14

VCC

AN15

VCC

AN16

VCC

AN17

VCC

AN19

VCC

AN20

VCC

AN21

VCC

AN23

VCC

AN24

VCC

AN25

VCC

AN26

VCC

AN27

VCC

AN29

VCC

AN30

VCC

AN32

VCC

AN34

VCC

AN36

VCC

AN38

VCC

AN39

VCC

AN40

VCC

AN41

VCC

AN42

VCC

AN43

VCC

AN44

VCC

AN45

VCC

AN46

VCC

AN8

VCC

AN9

VCC

AP10

VCC

AP12

VCC

AP13

VCC

AP14

VCC

AP15

VCC

AP16

VCC

AP17

VCC

AP18

VCC

AP19

VCC

AP20

VCC

AP21

VCC

AP22

VCC

AP23

VCC

AP24

VCC

AP25

VCC

AP26

VCC

AP27

VCC

AP29

VCC

AP30

VCC

AP31

VCC

AP32

VCC

AP33

VCC

AP34

VCC

AP35

VCC

AP36

VCC

AP37

VCC

AP38

VCC

AP39

VCC

AP40

VCC

AP41

VCC

AP42

VCC

AP43

VCC

AP44

VCC

AP46

VCC

AP47

VCC

AP8

VCC

AP9

VCC

AR35

VCC

AR37

VCC

AR39

VCC

AR41

VCC

AR43

VCC

AR45

VCC

AR46

VCC

H30

VCC

H31

VCC

H32

VCC

6 OF 12

HASWELL_BGA1364

Title

Title

Title

PROCESSOR(6/7) PWR

PROCESSOR(6/7) PWR

PROCESSOR(6/7) PWR

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

LA-B751P

LA-B751P

LA-B751P

Date: Sheet of

Date: Sheet of

Date: Sheet of

+VCC_CORE+VCC_CORE

H33

VCC

H34

VCC

H36

VCC

H37

VCC

H38

VCC

H39

VCC

H40

VCC

H42

VCC

H43

VCC

H45

VCC

H46

VCC

H48

VCC

H8

VCC

H9

VCC

J10

VCC

J14

VCC

J19

VCC

J24

VCC

J29

VCC

J33

VCC

J36

VCC

J37

VCC

J38

VCC

J39

VCC

J40

VCC

J42

VCC

J43

VCC

J45

VCC

J46

VCC

J48

VCC

J8

VCC

J9

VCC

K38

VCC

K40

VCC

K43

VCC

K44

VCC

K45

VCC

K46

VCC

K48

VCC

K8

VCC

K9

VCC

L37

VCC

L38

VCC

L39

VCC

L40

VCC

L42

VCC

L43

VCC

L44

VCC

L46

VCC

L47

VCC

L8

VCC

M37

VCC

M38

VCC

M39

VCC

M40

VCC

M42

VCC

M43

VCC

M44

VCC

M45

VCC

M46

VCC

M8

VCC

M9

VCC

N37

VCC

N38

VCC

N39

VCC

N40

VCC

N42

VCC

N43

VCC

N44

VCC

N46

VCC

N47

VCC

N8

VCC

N9

VCC

P45

VCC

P46

VCC

P8

VCC

R46

VCC

R47

VCC

R8

VCC

R9

VCC

T45

VCC

T46

VCC

U46

VCC

U47

VCC

U8

VCC

U9

VCC

V45

VCC

V46

VCC

V8

VCC

W46

VCC

W47

VCC

W8

VCC

Y45

VCC

Y46

VCC

Y8

VCC

A27

VCC

A28

VCC

A31

VCC

A32

VCC

A34

VCC

B27

VCC

B28

VCC

B31

VCC

B32

VCC

B34

VCC

B36

VCC

B38

VCC

B39

VCC

B42

VCC

1

0.1

0.1

12 69Wednesday, March 26, 2014

12 69Wednesday, March 26, 2014

12 69Wednesday, March 26, 2014

0.1

5

4

3

2

1

HASWELL_BGA

CPU1I

BC10

VSS

BC12

VSS

BC15

VSS

BC18

VSS

BC22

VSS

BC26

VSS

BC3

VSS

BC30

D D

C C

B B

A A

5

BC33
BC36
BC38
BC41
BC43
BC46
BC48

BC50
BC52

BD10
BD15
BD18
BD36
BD41
BD46

BD51
BE10
BE15
BE36
BE41
BE46

BF10
BF12
BF15
BF18
BF22
BF26
BF30
BF33
BF36
BF38
BF41
BF43
BF46
BF48

BC5

BC7

BD5

BF7
C11
C15
C19
C22
C26
C30
C33
C37

C40
C44
C49
C52

D11
D15
D19
D22
D26
D30
D33
D37
D40
D44
D49

G11
G13
G16

C4

C8

D8
E11
E15
E16
E17
E19
E20
E21
E22
E24
E25
E26
E30
E33
E37
E40
E44
E49
E51
E53

E8

F2
F26

F3
F30
F33
F37

F4
F40
F44
F49

F5

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

HASWELL_BGA1364

VSS_SENSE

9 OF 12

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS

VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF

G20
G23
G25
G26
G30
G33
G37
G40
G44
G49
G52
G54
G7
G8
G9
H44
H49
H7
J44
J49
J51
J54
J7
K1
K2
K3
K4
K5
K6
K7
L48
L7
L9
M48
M50
M52
M54
M7
N48
N7
P1
P2
P3
P4
P48
P5
P50
P52
P54
P6
P7
R48
R7
T48
U1
U2
U3
U4
U48
U5
U50
U52
U54
U6
U7
V48
V7
V9
W48
W50
W52
W54
W7
Y48
Y7
Y9

AR22
AB48
P9
G18

A49
A50
A8
B4
BA1
BA54
BB1
BB54
BD2
BD53
BF49
BF5
BF50
BF6
C53
D2
E54
F54
G1

D50

AT40
AT42
AT43
AT45
AT46
AT47
AT49

AT5
AT50
AT51
AT52
AT53
AT54

AT6

AT8

AT9
AU13
AU18
AU22
AU25
AU29
AU33
AU37
AU42

AU5

AU9

AV1
AV13
AV18

AV2
AV22
AV25
AV29

AV3
AV33

AV4
AV42

AV5
AV50

AV9

AW13
AW18
AW37
AW42
AW43
AW45
AW46
AW47
AW49

AW5
AW50
AW51
AW54

AW9

AY13
AY22
AY25
AY29
AY33
AY37
AY42

VSSSENSE_R <12>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

HASWELL_BGA

CPU1H

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

HASWELL_BGA1364

3

AY50

VSS

AY9

VSS

B11

VSS

B15

VSS

B19

VSS

B22

VSS

B26

VSS

B30

VSS

B33

VSS

B37

VSS

B40

VSS

B44

VSS

B49

VSS

B8

VSS

BA13

VSS

BA18

VSS

BA22

VSS

BA25

VSS

BA29

VSS

BA33

VSS

BA37

VSS

BA4

VSS

BA42

VSS

BA5

VSS

BA50

VSS

BA51

VSS

BA52

VSS

BA53

VSS

BA9

VSS

BB10

VSS

BB11

VSS

BB12

VSS

BB14

VSS

BB15

VSS

BB16

VSS

BB17

VSS

BB18

VSS

BB20

VSS

BB23

VSS

BB25

VSS

BB28

VSS

BB32

VSS

BB33

VSS

BB37

VSS

BB38

VSS

BB39

VSS

BB41

VSS

BB42

VSS

BB43

VSS

BB44

VSS

BB46

VSS

BB47

VSS

BB48

VSS

BB49

VSS

BB5

VSS

BB6

VSS

BB7

VSS

BB9

VSS

8 OF 12

Compal Secret Data

Compal Secret Data

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

AA48

AB51
AB52
AB53
AB54

AC48

AC50

AD48
AD51
AD54

AE48

AE50

AG48

AG51
AG52
AG53
AG54

AH48

AH50

2

AA1
AA2
AA3
AA4

AA5
AA7
AB5

AB7
AB9

AC5

AC7

AD7
AD9
AE1
AE2
AE3
AE4

AE5

AE7
AF5
AF6
AF7

AG5

AG7
AG9
AH1
AH2
AH3
AH4

AH5

AH7

A11
A15
A19
A22
A26
A30
A33
A37
A40
A44

HASWELL_BGA

CPU1G

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

HASWELL_BGA1364

AJ48

VSS

AJ51

VSS

AJ54

VSS

AK48

VSS

AK5

VSS

AK50

VSS

AK7

VSS

AK9

VSS

AL1

VSS

AL4

VSS

AL48

VSS

AL5

VSS

AL7

VSS

AM5

VSS

AM51

VSS

AM52

VSS

AM53

VSS

AM54

VSS

AM7

VSS

AN1

VSS

AN2

VSS

AN3

VSS

AN4

VSS

AN48

VSS

AN5

VSS

AN50

VSS

AN7

VSS

AP51

VSS

AP54

VSS

AP7

VSS

AR12

VSS

AR14

VSS

AR16

VSS

AR18

VSS

AR20

VSS

AR24

VSS

AR26

VSS

AR48

VSS

AR5

VSS

AR50

VSS

AR7

VSS

AR8

VSS

AR9

VSS

AT1

VSS

AT10

VSS

AT12

VSS

AT15

VSS

AT16

VSS

AT18

VSS

AT20

VSS

AT22

VSS

AT25

VSS

AT26

VSS

AT29

VSS

AT33

VSS

AT35

VSS

AT37

VSS

AT39

VSS

AT4

VSS

7 OF 12

Compal Electronics, Inc.

Title

Title

Title

PROCESSOR(7/7) VSS

PROCESSOR(7/7) VSS

PROCESSOR(7/7) VSS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-B751P

LA-B751P

LA-B751P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

13 69Wednesday, March 26, 2014

13 69Wednesday, March 26, 2014

13 69Wednesday, March 26, 2014

0.1

0.1

0.1

5

+1.35V +1.35V

3A@1.35V

3A@1.35V

3A@1.35V3A@1.35V

DDR3 SO-DIMM A

JDIMM1

0.1U_0402_16V7K

CD2

1

2

1

2

+VREF_DQ_DIMMA

DDR_A_D0
DDR_A_D1

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13
DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

2.2U_0603_10V6K

0.1U_0402_16V7K

CD22

CD23

1

2

2.2U_0603_10V6K
CD1

1

D D

C C

B B

1 2

RD7 10K_0402_5%

1 2

A A

RD8 10K_0402_5%

2

DDR_CKE0_DIMMA<9>

DDR_A_BS2<9>

M_CLK_DDR0<9>
M_CLK_DDR#0<9>

DDR_A_BS0<9>

DDR_A_WE#<9>
DDR_A_CAS#<9>

DDR_CS1_DIMMA#<9>

+3VS

5

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

SP07000LT00

CONN@

DQS0#

DQS0

DQ12
DQ13

RESET#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

CKE1

RAS#

ODT0

ODT1

VREF_CA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

EVENT#

GND2

BOSS2

VSS
DQ4
DQ5
VSS

VSS
DQ6
DQ7
VSS

VSS
DM1

VSS

VSS

VSS
DM2
VSS

VSS

VSS

VSS

VSS

VDD

VDD

VDD

VDD

VDD
CK1

CK1#

VDD
BA1

VDD

VDD

VDD

VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
DM6
VSS

VSS

VSS

VSS

VSS

SDA
SCL
VTT

4

DDR_A_D[0..63]<9>

DDR_A_DQS[0..7]<9>

DDR_A_DQS#[0..7]<9>

2
4

DDR_A_D4

6

DDR_A_D5

8
10

DDR_A_DQS#0

12

DDR_A_DQS0

14
16

DDR_A_D6

18

DDR_A_D7

20
22

DDR_A_D12

24

DDR_A_D13

26
28
30

DDR3_DRAMRST#

32
34

DDR_A_D14

36

DDR_A_D15

38
40

DDR_A_D20

42

DDR_A_D21

44
46
48
50

DDR_A_D22

52

DDR_A_D23DDR_A_D18

54
56

DDR_A_D28

58

DDR_A_D29

60
62

DDR_A_DQS#3

64

DDR_A_DQS3

66
68

DDR_A_D30

70

DDR_A_D31

72

74

DDR_CKE1_DIMMA

76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

DDR_A_MA15

DDR_A_MA14

DDR_A_MA11

DDR_A_MA7

DDR_A_MA6

DDR_A_MA4

DDR_A_MA2

DDR_A_MA0

M_CLK_DDR1

M_CLK_DDR#1

DDR_A_BS1

DDR_A_RAS#

DDR_CS0_DIMMA#

M_ODT0

M_ODT1

DDR_A_D36

DDR_A_D37

DDR_A_D38

DDR_A_D39

DDR_A_D44

DDR_A_D45

DDR_A_DQS#5

DDR_A_DQS5

DDR_A_D46

DDR_A_D47

DDR_A_D52

DDR_A_D53

DDR_A_D54

DDR_A_D55

DDR_A_D60

DDR_A_D61

DDR_A_DQS#7

DDR_A_DQS7

DDR_A_D62

DDR_A_D63

PCH_SMBDATA

PCH_SMBCLK

+0.675VS

0.65A@0.675V

0.65A@0.675V

0.65A@0.675V0.65A@0.675V

A15
A14

A11

A7

A6
A4

A2
A0

S0#

NC

4

DDR3_DRAMRST# <15,8>

DDR_CKE1_DIMMA <9>

M_CLK_DDR1 <9>
M_CLK_DDR#1 <9>

DDR_A_BS1 <9>
DDR_A_RAS# <9>

DDR_CS0_DIMMA# <9>
M_ODT0 <9>

M_ODT1 <9>

DDR_A_MA[0..15]<9>

+VREF_CA

0.1U_0402_16V7K

2.2U_0603_10V6K

CD19

1

1

2

2

M_THERMAL# <15,43>
PCH_SMBDATA <15,19,36,8>
PCH_SMBCLK <15,19,36,8>

3

Layout Note:
Place near JDIMM1

0.1U_0402_16V7K

1U_0402_6.3V6K

CD4

CD3

1

1

2

1

2

2

0.1U_0402_16V7K

0.1U_0402_16V7K

CD6

CD5

1

2

Layout Note:
Place near JDIMM1

10U_0603_6.3V6M

CD7

1

1

@

2

2

Place near JDIMM1 pin203 pin204

CD20

+SM_VREF

Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/planes

CPU DRIVER
VREF PATH IS
DEFAULT

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

CD21

0.022U_0402_16V7K

12

12

RD4

24.9_0402_1%

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

+1.35V+0.675VS

10U_0603_6.3V6M

10U_0603_6.3V6M

CD8

@

10U_0603_6.3V6M

CD9

1

2

CD10

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD12

CD11

1

2

1

1

2

2

DDR3L SODIMM ODT GENERATION

Layout Note:
Place near JDIMM1

+0.675VS +1.35V

12

12

@RF@

CD41

10P_0402_50V8J

RD2

1 2

2.2_0402_1%

@RF@

CD42

10P_0402_50V8J

+1.35V

RD1
1K_0402_1%

1 2

RD3

1K_0402_1%

1 2

Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/planes

2

*M3+M1:Default Recommendation
M1:VREF_DQ driven by a voltage Divider Network during
Processor power-off state.
M3:VREF_DQ driven by Processor.

+VREF_CA

+VREF_CA <15>

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

10U_0603_6.3V6M

10U_0603_6.3V6M

CD14

CD13

1

2

+SA_DIMM_VREFDQ

C9

0.022U_0402_16V7K

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

DDRIII-SODIMM SLOT1

DDRIII-SODIMM SLOT1

0.1U_0402_16V7K

1

2

12

12

0.1U_0402_16V7K

CD15

1

2

1 2

RD6

2.2_0402_1%

RD10

24.9_0402_1%

LA-B751P

LA-B751P

LA-B751P

0.1U_0402_16V7K

0.1U_0402_16V7K

CD40 330U_2.5V_M

CD16

CD17

1

2

+1.35V

RD5
1K_0402_1%

1 2

RD9

1K_0402_1%

1 2

1

1

CD18

1

+

2

2

Add 330u Solid Cap

+VREF_DQ_DIMMA

14 69Wednesday, March 26, 2014

14 69Wednesday, March 26, 2014

14 69Wednesday, March 26, 2014

0.1

0.1

0.1

5

+VREF_DQ_DIMMB

DDR_B_D0
DDR_B_D1

0.1U_0402_16V7K

2.2U_0603_10V6K
CD25

CD24

1

1

2

RD15

10K_0402_5%

5

2

DDR_CKE2_DIMMB<9>

DDR_B_BS2<9>

M_CLK_DDR2<9>
M_CLK_DDR#2<9>

DDR_B_BS0<9>

DDR_B_WE#<9>
DDR_B_CAS#<9>

DDR_CS3_DIMMB#<9>

+3VS

12

+3VS

D D

C C

B B

1 2

RD16 10K_0402_5%

A A

2.2U_0603_10V6K

0.1U_0402_16V7K

1

CD39

2

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

1

C16

2

3A@1.35V

3A@1.35V

3A@1.35V3A@1.35V

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4806-0103
SP07000M200

4

DQ4
DQ5

VSS3

DQS0
VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

DM1

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1
CK1#

BA1
RAS#

ODT0

ODT1

NC2

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5

DQ46
DQ47

DQ52
DQ53

DM6

DQ54
DQ55

DQ60
DQ61

DQS7

DQ62
DQ63

SDA

SCL

VTT2

+1.35V+1.35V

2
4

DDR_B_D4

6

DDR_B_D5

8
10

DDR_B_DQS#0

12

DDR_B_DQS0

14
16

DDR_B_D6

18

DDR_B_D7

20
22

DDR_B_D12

24

DDR_B_D13

26
28
30

DDR3_DRAMRST#

32
34

DDR_B_D14

36

DDR_B_D15

38
40

DDR_B_D20

42

DDR_B_D21

44
46
48
50

DDR_B_D22

52

DDR_B_D23

54
56

DDR_B_D28

58

DDR_B_D29

60
62

DDR_B_DQS#3

64

DDR_B_DQS3

66
68

DDR_B_D30

70

DDR_B_D31

72

74

DDR_CKE3_DIMMB

76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_B_MA15

DDR_B_MA14

DDR_B_MA11

DDR_B_MA7

DDR_B_MA6

DDR_B_MA4

DDR_B_MA2

DDR_B_MA0

M_CLK_DDR3

M_CLK_DDR#3

DDR_B_BS1

DDR_B_RAS#

DDR_CS2_DIMMB#

M_ODT2

M_ODT3

DDR_B_D36

DDR_B_D37

DDR_B_D38

DDR_B_D39

DDR_B_D44

DDR_B_D45

DDR_B_DQS#5

DDR_B_DQS5

DDR_B_D46

DDR_B_D47

DDR_B_D52

DDR_B_D53

DDR_B_D54

DDR_B_D55

DDR_B_D60

DDR_B_D61

DDR_B_DQS#7

DDR_B_DQS7

DDR_B_D62

DDR_B_D63

PCH_SMBDATA

PCH_SMBCLK

0.65A@0.675V

0.65A@0.675V

0.65A@0.675V0.65A@0.675V

A15
A14

A11

A7

A6
A4

A2
A0

S0#

G2

DDR3_DRAMRST# <14,8>

DDR_CKE3_DIMMB <9>

M_CLK_DDR3 <9>
M_CLK_DDR#3 <9>

DDR_B_BS1 <9>
DDR_B_RAS# <9>

DDR_CS2_DIMMB# <9>
M_ODT2 <9>

M_ODT3 <9>

+0.675VS

CONN@

DQS#0

VSS10

VSS12

VSS14

VSS16

VSS17

VSS19

VSS21

VSS24

VSS26

VDD10

VDD12

VDD14

VDD16

VDD18

VREF_CA

VSS28

VSS30

VSS31

VSS33

VSS35

DQS#5

VSS38

VSS40

VSS42

VSS43

VSS45

VSS47

DQS#7

VSS50

VSS52

EVENT#

4

3

DDR_B_D[0..63]<9>

DDR_B_DQS[0..7]<9>

DDR_B_DQS#[0..7]<9>

DDR_B_MA[0..15]<9>

Layout Note:
Place near JDIMM2

+0.675VS

1U_0402_6.3V6K

C10

1

2

2

0.1U_0402_16V7K

C11

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K

C13

C12

1

1

2

2

Place near JDIMM2 pin203 pin204

Layout Note:
Place near JDIMM2

+1.35V

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD27

CD26

1

1

2

2.2U_0603_10V6K
C15

+VREF_CA <14>

Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/planes

Compal Secret Data

Compal Secret Data

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

0.1U_0402_16V7K
C14

1

1

2

2

M_THERMAL# <14,43>
PCH_SMBDATA <14,19,36,8>
PCH_SMBCLK <14,19,36,8>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

@

@

2

10U_0603_6.3V6M

CD28

1

2

2

CD29

1

2

0.022U_0402_16V7K

10U_0603_6.3V6M

10U_0603_6.3V6M

CD31

CD30

1

1

2

2

1 2

RD12

2.2_0402_1%

CD38

12

12

RD14

24.9_0402_1%

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

Layout Note:
Place near JDIMM3

+0.675VS +1.35V

12

12

@RF@

CD43

10P_0402_50V8J

10U_0603_6.3V6M

CD32

1

2

+1.35V+SB_DIMM_VREFDQ

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

@RF@

CD44

10P_0402_50V8J

0.1U_0402_16V7K

10U_0603_6.3V6M

CD33

1

1

2

RD11
1K_0402_1%

1 2

RD13
1K_0402_1%

1 2

CD34

2

+VREF_DQ_DIMMB

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

DDRIII-SODIMM SLOT2

DDRIII-SODIMM SLOT2

LA-B751P

LA-B751P

LA-B751P

0.1U_0402_16V7K

0.1U_0402_16V7K

CD36

CD35

1

1

2

2

1

0.1U_0402_16V7K

CD37

1

2

15 69Wednesday, March 26, 2014

15 69Wednesday, March 26, 2014

15 69Wednesday, March 26, 2014

0.1

0.1

0.1

5

+RTC_CELL

12

4

330K_0402_1%~D

RH3

3

2

1

D D

INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE

High - Enable Internal VRs
Low - Enable External VRs

+3VS

RH5 10K_0402_5%~D@

NO REBOOT STRAP

DISABLED WHEN LOW (DEFAULT)
ENABLED WHEN HIGH

C C

+3VS

RH14 100K_0402_5%~D@

CMOS_CLR1

Shunt Clear CMOS

Open

ME_CLR1

Shunt Clear ME RTC Registers

Open

HDA_SYNC Isolation Circuit

B B

A A

330K_0402_1%~D

12

1 2

1 2

CMOS setting

Keep CMOS

TPM setting

Keep ME RTC Registers

PCH_INTVRMEN

@

RH4

HDA_SPKR

PCH_GPIO33

1M_0402_5%~D

RH20

1 2

+3V_PCH

RH60 10K_0402_5%~D

RH6 1K_0402_1%~D@

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = DESABLED (DEFAULT)
HIGH = ENABLED

+5VS

G

2

13

PCH_AZ_SYNCPCH_AZ_SYNC_Q

D

S

QH1

SSM3K7002FU_SC70-3~D

1 2

1 2

+RTC_CELL

PCH_GPIO13

PCH_AZ_SDOUT

YH1 Change to SJ10000LD00 (ESR=50Kohm)

CH1

1 2

PCH_RTCX1_R

18P_0402_50V8J~D

CH2

1 2

RH15 20K_0402_5%~D

1 2

RH12 1M_0402_5%~D

1 2

RH13 20K_0402_5%~D

1

1

@

CMOS1 SHORT PADS~D

CH4

CMOS place near DIMM

+3V_PCH

0_0603_5%~D

12

RH17

@

+3.3V_ALW_PCH_JTAG PCH_JTAG_TMS

1 2

18P_0402_50V8J~D

2

2

1 2

1U_0402_6.3V6K~D

12

RH18 51_0402_1%~D

1 2

RH19 210_0402_1%~D

@

1 2

RH21 210_0402_1%~D

@

1 2

RH23 210_0402_1%~D

@

RH9 0_0402_5%

12

YH1

32.768KHZ_12.5PF_9H03220008

2

CH3
1U_0402_6.3V6K~D

1

PCH_AZ_CODEC_SDIN0<32>

ME_EN<43>

100_0402_1%~D

100_0402_1%~D

12

12

RH25

HDA for Codec and MDC

RP2

1 8
2 7

PCH_AZ_CODEC_SDOUT<32>
PCH_AZ_CODEC_SYNC<32>

PCH_AZ_CODEC_RST#<32>

PCH_AZ_CODEC_BITCLK<32>

RH29 33_0402_5%~D

27P_0402_50V8J~D

@

CH5

1

2

3 6
4 5

1 2

PCH_AZ_SDOUT
PCH_AZ_SYNC_Q
PCH_AZ_RST#

33_0804_8P4R_5%

PCH_AZ_BITCLK

@

12

HDA_SPKR<32>

1 2

RH16 1K_0402_1%~D

PCH_JTAG_TCK

PCH_JTAG_TDI

PCH_JTAG_TDO

100_0402_1%~D

RH24 0_0402_5%

12

RH26

RH27

12

RH11
10M_0402_5%~D

PCH_RTCX2

SRTCRST#

INTRUDER#

PCH_INTVRMEN

PCH_RTCRST#

PCH_AZ_BITCLK

PCH_AZ_SYNC

HDA_SPKR

PCH_AZ_RST#

PCH_AZ_CODEC_SDIN0

PCH_AZ_SDOUT

PCH_GPIO33

PCH_GPIO13

@

T66 PAD~D@

T67 PAD~D@

PCH_RTCX1

12

PCH_TP25

UH1A

B5

RTCX1

B4

RTCX2

B9

SRTCRST#

A8

INTRUDER#

G10

INTVRMEN

D9

RTCRST#

B25

HDA_BCLK

A22

HDA_SYNC

AL10

SPKR

C24

HDA_RST#

L22

HDA_SDI0

K22

HDA_SDI1

G22

HDA_SDI2

F22

HDA_SDI3

A24

HDA_SDO

B17

DOCKEN#/G PIO33

C22

HDA_DOCK_ RST#/GPIO13

AB3

JTAG_TCK

AD1

JTAG_TMS

AE2

JTAG_TDI

AD3

JTAG_TDO

F8

TP25

C26

TP22

AB6

TP20

LPT_PCH_M_EDS

JTAGRTC AZALIA

LYNXPOINT_BGA695

5

1 OF 11

+3VS

PCH_GPIO21

PCH_GPIO19

PCH_SATALED#

BC8

SATA_RXN_0
SATA_RXP_ 0

SATA_TXN_0
SATA_TXP_0

SATA_RXN_1
SATA_RXP_ 1

SATA_TXN_1
SATA_TXP_1

SATA

SATA_RXN_2
SATA_RXP_ 2

SATA_TXN_2
SATA_TXP_2

SATA_RXN_3
SATA_RXP_ 3

SATA_TXN_3
SATA_TXP_3

SATA_RXN4/ PERN1

SATA_RXP4 /PERP1

SATA_TXN4/P ETN1
SATA_TXP4/P ETP1

SATA_RXN5/ PERN2

SATA_RXP5 /PERP2

SATA_TXN5/P ETN2
SATA_TXP5/P ETP2

SATA_RCOMP

SATALED#

SATA0GP/G PIO21

SATA1GP/G PIO19

SATA_IREF

SATA_PRX_DTX_N0

BE8

SATA_PRX_DTX_P0

AW8

SATA_PTX_DRX_N0

AY8

SATA_PTX_DRX_P0

BC10

SATA_PRX_DTX_N1

BE10

SATA_PRX_DTX_P1

AV10

SATA_PTX_DRX_N1

AW10

SATA_PTX_DRX_P1

BB9
BD9

AY13
AW13

BC12

SATA_PRX_DTX_N3

BE12

SATA_PRX_DTX_P3

AR13

SATA_PTX_DRX_N3

AT13

SATA_PTX_DRX_P3

BD13

SATA_PRX_DTX_N4

BB13

SATA_PRX_DTX_P4

AV15

SATA_PTX_DRX_N4

AW15

SATA_PTX_DRX_P4

BC14

SATA_PRX_DTX_N5

BE14

SATA_PRX_DTX_P5

AP15

SATA_PTX_DRX_N5

AR15

SATA_PTX_DRX_P5

AY5

SATA_COMP

AP3

PCH_SATALED#

AT1

PCH_GPIO21

AU2

PCH_GPIO19

BD4

SATA_IREF

BA2

TP9

BB2

TP8

PCH_SATALED# <38>

12

@

RH22 0_0402_5%

T64PAD~D @

T65PAD~D @

SATA Impedance Compensation

SATA_COMP

CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.

1 2

1 2

SATA_PRX_DTX_N0 <36>
SATA_PRX_DTX_P0 <36>

SATA_PTX_DRX_N0 <36>
SATA_PTX_DRX_P0 <36>

SATA_PRX_DTX_N1 <29>
SATA_PRX_DTX_P1 <29>

SATA_PTX_DRX_N1 <29>
SATA_PTX_DRX_P1 <29>

SATA_PRX_DTX_N3 <29>
SATA_PRX_DTX_P3 <29>

SATA_PTX_DRX_N3 <29>
SATA_PTX_DRX_P3 <29>

SATA_PRX_DTX_N4 <29>
SATA_PRX_DTX_P4 <29>

SATA_PTX_DRX_N4 <29>
SATA_PTX_DRX_P4 <29>

SATA_PRX_DTX_N5 <29>
SATA_PRX_DTX_P5 <29>

SATA_PTX_DRX_N5 <29>
SATA_PTX_DRX_P5 <29>

+1.5VS

1 2

+1.5VS

RH287.5K_0402_1%~D

RH710K_0402_5%~D

12

RH84.7K_0402_5%~D

RH1010K_0402_5%~D

HDD

NGFF SSD for Echo 15

NGFF SSD for Echo 17
Gen2 Only

NGFF SSD for Echo 17

NGFF SSD for Echo 15

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

PCH (1/9) RTC,HDA,SATA,XDP

PCH (1/9) RTC,HDA,SATA,XDP

PCH (1/9) RTC,HDA,SATA,XDP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-B751P

LA-B751P

LA-B751P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

16 69Wednesday, March 26, 2014

16 69Wednesday, March 26, 2014

16 69Wednesday, March 26, 2014

0.1

0.1

0.1

5

D D

+3V_PCH

1 2

RH30 10K_0402_5%~D

1 2

RH31 10K_0402_5%~D

1 2

RH35 10K_0402_5%~D

1 2

RH37 10K_0402_5%~D

+3VS

1 2

RH33 8.2K_0402_5%~D

1 2

RH38 10K_0402_5%~D

DMI_CTX_PRX_N0<7>
DMI_CTX_PRX_N1<7>

DMI_CTX_PRX_N2<7>
DMI_CTX_PRX_N3<7>

DMI_CTX_PRX_P0<7>

C C

PM_DRAM_PWRGD<8>

B B

ME_SUS_PWR_ACK<43>

+PCH_VCCDSW3_3

DMI_CTX_PRX_P1<7>

DMI_CTX_PRX_P2<7>
DMI_CTX_PRX_P3<7>

DMI_CRX_PTX_N0<7>
DMI_CRX_PTX_N1<7>

DMI_CRX_PTX_N2<7>
DMI_CRX_PTX_N3<7>

DMI_CRX_PTX_P0<7>
DMI_CRX_PTX_P1<7>

DMI_CRX_PTX_P2<7>
DMI_CRX_PTX_P3<7>

+1.5VS

+1.5VS

SUSACK#<43>

SYS_PWROK<12,43,8>

PCH_PWROK<43>

PCH_RSMRST#<43>

PBTN_OUT#<43,8>

+PCH_VCCDSW3_3

RH152 10K_0402_5%

1 2

RH36 10K_0402_5%~D

SUS_STAT#

@

ME_SUS_PWR_ACK

PCIE_WAKE#

@

PCH_RI#

PM_CLKRUN#

PCH_RSMRST#

DMI_RCOMP

SIO_PWRBTN#_R

ACIN

PCH_RI#

AW22

AR20

AP17
AV20

AY22
AP20

AR17

AW20

BD21
BE20

BD17
BE18

BB21
BC20

BB17
BC18

BE16

AW17

AV17

AY17

AB10

R6

AM1

AD7

F10

AB7

H3

J2

J4

K1

E6

K7

N4

D2

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1

DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1

DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1

DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1

DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

1 2

DMI_IREF

@

RH144 0_0402_5%

T70 PAD~D@

T72 PAD~D@ CH7

1 2

RH42 7.5K_0402_1%~D

R2458

1 2

0_0402_5%

1 2

RH47 0_0402_5%

1 2

RH49 0_0402_5%

1 2

RH50 0_0402_5%

1 2

RH52 0_0402_5%

1 2

RH53 0_0402_5%

1 2

RH55 0_0402_5%

1 2

RH56 0_0402_5%

1 2

RH58 8.2K_0402_5%~D

12

ACIN

WAKE#

@

@

@

@

@

@

@

ACIN<37,43,59>

T79 PAD~D@

SUSACK#_R

SYS_RESET#

SYS_PWROK_R

PCH_PWROK_R

PM_APWROK_R

PM_DRAM_PWRGD_R

PCH_RSMRST#_R

ME_SUS_PWR_ACK_R

PCH_BATLOW#

XDP_DBRESET#<8>

UH1B

DMI_RXN_0
DMI_RXN_1

DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1

DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1

DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1

DMI_TXP_2
DMI_TXP_3

DMI_IREF

TP12

TP7

DMI_RCOMP

SUSACK#

SYS_RESE T#

SYS_PW ROK

PWROK

APWROK

DRAMPWR OK

RSMRST#

SUSWAR N#/SUSPWR NACK/GPIO30

PWRBTN#

ACPRESEN T/GPIO31

BATLOW# /GPIO72

RI#

TP21

SLP_W LAN#/GPIO2 9

LYNXPOINT_BGA695

4

1 2

@

RH32 0_0402_5%

RH34 0_0402_5%

5

4 OF 11

FDI

SUS_STAT#/G PIO61

1 2

@

FDI_CSYNC

FDI_RCOMP

DSWVRME N

SUSCLK/G PIO62

SLP_S5# /GPIO63

ME_SUS_PWR_ACK_R SUSACK#_R

LPT_PCH_M_EDS

DMI

System Power

Management

FDI_RXN_0

FDI_RXN_1

FDI_RXP_0

FDI_RXP_1

FDI_INT

FDI_IREF

DPWROK

WAKE#

CLKRUN#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS #

PMSYNCH

SLP_LAN #

3

+3VS

CH6

@

1 2

0.1U_0402_25V6K~D

5

PCH_PWROK

IMVP_PWRGD<65,8>

SYS_RESET#

AJ35

AL35

AJ36

AL36

AV43

TP16

AY45

TP5

AV45

TP15

AW44

TP10

AL39

FDI_CSYNC

AL40

FDI_INT

AT45

AU42

TP17

AU44

TP13

AR44

C8

L13

K3

AN7

U7

Y6

Y7

C6

H1

F3

F1

AY3

G5

FDI_IREF

RH40 0_0402_5%

FDI_RCOMP

DSWODVREN

PCH_DRWROK_R

WAKE#

PM_CLKRUN#

SUS_STAT#

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_SUS#

H_PM_SYNC

1 2

@

RH45 0_0402_5%

1 2

RH48 0_0402_5%~D@

DSWODVREN

T69PAD~D @

T71PAD~D @

12

RH417.5K_0402_1%~D

RH46 0_0402_5%

1 2

@

1 2

@

T73 PAD~D@

T74 PAD~D

T75 PAD~D

T76 PAD~D

T77 PAD~D

T78

IMVP_PWRGD

FDI_CSYNC <7>

FDI_INT <7>

+1.5VS

+1.5VS

PCH_RSMRST#_R

SUSCLK <28>

@

PM_SLP_S5# <37,43>

@

PM_SLP_S4# <43>

@

PM_SLP_S3# <37,43>

@

PM_SLP_SUS# <43>

PAD~D

@

H_PM_SYNC <8>

+RTC_CELL

330K_0402_1%

RH65

1 2

330K_0402_1%

@

RH70

1

P

B

4

O

2

A

G

3

TC7SH08FU_SSOP5~D

1 2

RH39 649_0402_1%~D

PCH_INV_PWM<10, 25>

PANEL_BKLEN<43>

PCH_ENVDD<25>

GPU_PWR_LEVEL<43,46>

TS_RST#<25>

DGPU_HOLD_RST#<43,46>

WL_OFF#<28>

TS_INT#<25>

PCH_DPWROK <43>

PCIE_WAKE# <30, 43>

DSWODVREN - ON DIE DSW VR ENABLE

HIGH = ENABLED (DEFAULT)
LOW = DISABLED

SYS_PWROK

UH2

T45

VGA_BLU E

U44

VGA_GRE EN

V45

VGA_RED

M43

VGA_DDC_ CLK

M45

VGA_DDC_ DATA

N42

VGA_HSYNC

N44

VGA_VSYN C

U40

DAC_IREF

U39

VGA_IRTN

N36

PCH_INV_PWM

PANEL_BKLEN

PCH_ENVDD

PCI_PIRQA#

PCI_PIRQB#

PCI_PIRQC#

PCI_PIRQD#

GPU_PWR_LEVEL

DGPU_HOLD_RST#

BBS_BIT1

WL_OFF#

EDP_BKL TCTL

K36

EDP_BKL TEN

G36

EDP_VDDE N

H20

PIRQA#

L20

PIRQB#

K17

PIRQC#

M20

PIRQD#

A12

GPIO50

B13

GPIO52

C12

GPIO54

C10

GPIO51

A10

GPIO53

AL6

GPIO55

1 2

1 2

PCH_ENVDD

PCH_mDP_HPD

RH54 100K_0402_5%

RH57 100K_0402_5%

Mason: Follow Intel DG. HPD PL. 2014/1/21

STP_A16OVR

2

LPT_PCH_M_EV

LVDSCRT

PCI

LYNXPOINT_BGA695

A16 SWAP OVERRIDE STRAP

LOW = A16 SWAP OVERRIDE
HIGH = DEFAULT

5 OF 11

DISPLAY

5UH1E

DDPB_CTRLDA TA

DDPC_CTRLDATA

DDPD_CTRLDATA

DDPB_CTRLCL K

DDPC_CTRLCLK

DDPD_CTRLCLK

DDPB_AUX N

DDPC_AUXN

DDPD_AUXN

DDPB_AUX P

DDPC_AUXP

DDPD_AUXP

DDPB_HPD

DDPC_HPD

DDPD_HPD

PIRQE#/G PIO2

PIRQF#/GP IO3

PIRQG#/G PIO4

PIRQH#/GP IO5

PME#

PLTRST#

PCH_PLTRST#

R40

R39

R35

R36

N40

N38

H45

K43

J42

H43

K45

J44

K40

K38

H39

G17

F17

L15

M15

AD10

Y11

1

2

PCH_DPC_CLK

PCH_DPC_DAT

PCH_DPC_AUX#

PCH_DPC_AUX

PCH_HDMI_HPD

PCH_mDP_HPD

BT_OFF#

DP_CBL_DET

FFS_INT1

PCH_PLTRST#

B

A

+3VS

RV528 2.2K_0402_5%~D

RV529 2.2K_0402_5%~D

PCH_DPB_HDMI_CLK

PCH_DPB_HDMI_DAT

T68 PAD~D@

+3VS

@

1 2

0.1U_0402_25V6K~D

5

P

4

PLT_RST

O

G

UH3

TC7SH08FU_SSOP5~D

3

1 2

1 2

BT_OFF# <28>

DP_CBL_DET <26>

FFS_INT1 <36>

PCH_PLTRST# <41,46>

BT_OFF#

WL_OFF#

PCI_PIRQA#

PCI_PIRQB#

PCI_PIRQC#

PCI_PIRQD#

RH67 10K_0402_5%~D@

1

PCH_DPC_CLK

PCH_DPC_DAT

PCH_DPB_HDMI_CLK <27>

PCH_DPB_HDMI_DAT <27>

PCH_DPC_CLK <26>

PCH_DPC_DAT <26>

PCH_DPC_AUX# <26>

PCH_DPC_AUX <26>

PCH_HDMI_HPD <27>

PCH_mDP_HPD <26>

+3VS

12

RH43
10K_0402_5%~D

@

12

RH51
100K_0402_5%~D

1 2

PM_CLKRUN#

PLT_RST# <28,30,31,43,44>

+3VS

12

RH598.2K_0402_5%~D

12

RH618.2K_0402_5%~D

12

RH628.2K_0402_5%~D

12

RH638.2K_0402_5%~D

12

RH648.2K_0402_5%~D

12

RH668.2K_0402_5%~D

HDMI

mDP

Boot BIOS Strap

SATA_SLPD

BBS_BIT1 Boot BIOS Location

A A

5

BBS_BIT1

1K_0402_1%

12

@

RH71

GPIO51 has internal pull up.

*

(BBS_BIT0)

00 LPC

0 1 Reserved (NAND)

1 0

PCI

11 SPI

4

1 2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

PCH (2/9) DMI,FDI,PM,DP,CRT

PCH (2/9) DMI,FDI,PM,DP,CRT

PCH (2/9) DMI,FDI,PM,DP,CRT

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-B751P

LA-B751P

LA-B751P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

17 69Wednesday, March 26, 2014

17 69Wednesday, March 26, 2014

17 69Wednesday, March 26, 2014

0.1

0.1

0.1

5

D D

+3V_PCH

+3V_PCH

10/100/1G LAN

C C

MiniWLAN

Card Reader

CLK_PCI_LPC<43>

B B

CLK_PCIE_LAN#<30>

CLK_PCIE_LAN<30>

LANCLK_REQ#<30>

+3V_PCH

CLK_PCIE_WLAN#<28>
CLK_PCIE_WLAN<28>

WLANCLK_REQ#<28>

+3VS

CLK_PCIE_CD#<31>
CLK_PCIE_CD<31>

CDCLK_REQ#<31>

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

CLK_CPU_ITP#<8>

CLK_CPU_ITP<8>

CLK_PCI_LPBACK CLK_PCI0

CLK_PCI_LPC

1 2

RH73 10K_0402_5%~D

1 2

RH75 10K_0402_5%~D

1 2

RH77 10K_0402_5%~D

1 2

RH78 10K_0402_5%~D

1 2

RH80 10K_0402_5%~D

1 2

RH81 10K_0402_5%~D

1 2

RH82 10K_0402_5%~D

RH83 10K_0402_5%~D

RH85 0_0402_5%

RH86 0_0402_5%

RH87 22_0402_5%~D

RH89 22_0402_5%~D

12

@RF@

CH72

10P_0402_50V8J

4

LYNXPOINT_BGA695

LPT_PCH_M_EDS

2 OF 11

UH1C

Y43

CLKOUT_PCIE _N_0

Y45

CLKOUT_PCIE _P_0

CLK_PCI1

CLK_PCI2

CLK_PCI3

CLK_PCI4

AB1

PCIECLKRQ 0#/GPIO73

AA44

CLKOUT_PCIE _N_1

AA42

CLKOUT_PCIE _P_1

AF1

PCIECLKRQ 1#/GPIO18

AB43

CLKOUT_PCIE _N_2

AB45

CLKOUT_PCIE _P_2

AF3

PCIECLKRQ 2#/GPIO20/ SMI#

AD43

CLKOUT_PCIE _N_3

AD45

CLKOUT_PCIE _P_3

T3

PCIECLKRQ 3#/GPIO25

AF43

CLKOUT_PCIE _N_4

AF45

CLKOUT_PCIE _P_4

V3

PCIECLKRQ 4#/GPIO26

AE44

CLKOUT_PCIE _N5

AE42

CLKOUT_PCIE _P_5

AA2

PCIECLKRQ 5#/GPIO44

AB40

CLKOUT_PCIE _N_6

AB39

CLKOUT_PCIE _P_6

AE4

PCIECLKRQ 6#/GPIO45

AJ44

CLKOUT_PCIE _N_7

AJ42

CLKOUT_PCIE _P_7

Y3

PCIECLKRQ 7#/GPIO46

AH43

CLKOUT_ITPXD P

AH45

CLKOUT_ITPXD P_P

D44

CLKOUT_33 MHZ0

E44

CLKOUT_33 MHZ1

B42

CLKOUT_33 MHZ2

F41

CLKOUT_33 MHZ3

A40

CLKOUT_33 MHZ4

CLOCK SIGNAL

@

@

@

@

@

@

CLK_PCIE_LAN#

CLK_PCIE_LAN

LANCLK_REQ#

CLK_PCIE_WLAN#
CLK_PCIE_WLAN
WLANCLK_REQ#

CLK_PCIE_CD#
CLK_PCIE_CD
CDCLK_REQ#

12

12

12

12

12

CLK_BCLK_ITP#

CLK_BCLK_ITP

T96 PAD~D@

T95 PAD~D@

T83 PAD~D@

3

5

CLKOUT_PEG _A

CLKOUT_PEG _A_P

PEGA_CL KRQ#/GPIO47

CLKOUT_PEG _B

CLKOUT_PEG _B_P

PEGB_CL KRQ#/GPIO56

CLKOUT_DMI

CLKOUT_DMI_ P

CLKOUT_DP

CLKOUT_DP_ P

CLKOUT_DPNS

CLKOUT_DPNS _P

CLKIN_DMI

CLKIN_DMI_ P

CLKIN_GND

CLKIN_GND _P

CLKIN_DOT96 N
CLKIN_DOT96 P

CLKIN_SA TA

CLKIN_SA TA_P

REFCLK14 IN

CLKIN_33 MHZLOOPBACK

XTAL25_IN

XTAL25_O UT

CLKOUTFLEX 0/GPIO64

CLKOUTFLEX 1/GPIO65

CLKOUTFLEX 2/GPIO66

CLKOUTFLEX 3/GPIO67

ICLK_IREF

DIFFCLK_B IASREF

TP19
TP18

AB35

CLK_PEG_GPU#_R

AB36

CLK_PEG_GPU_R

AF6

Y39

Y38

U4

AF39

CLK_CPU_DMI#

AF40

CLK_CPU_DMI

AJ40

CLK_CPU_SSC_DPLL#

AJ39

CLK_CPU_SSC_DPLL

AF35

CLK_CPU_DPLL#

AF36

CLK_CPU_DPLL

AY24

CLK_BUF_DMI#

AW24

CLK_BUF_DMI

AR24

CLK_BUF_BCLK#

AT24

CLK_BUF_BCLK

H33

CLK_BUF_DOT96#

G33

CLK_BUF_DOT96

BE6

CLK_BUF_CKSSCD#

BC6

CLK_BUF_CKSSCD

F45

CLK_PCH_14M

D17

CLK_PCI_LPBACK

AL44
AM43

C40

F38

PCH_GPIO65

F36

PCH_GPIO66

F39

AM45

ICLK_IREF

AD39
AD38

AN44

PCH_CLK_BIASREF

CLKREQ#_GPU

RH7410K_0402_5%

CLK_PCIE_DGPU#

CLK_PCIE_DGPU

CLKREQ#_DGPU

RH7610K_0402_5%

XTAL25_IN
XTAL25_OUT

PCH_GPIO65
PCH_GPIO66

RH129 0_0402_5%

1 2

CLK_PEG_GPU#

@

RH128 0_0402_5%

1 2

CLK_PEG_GPU

@

CLKREQ#_GPU <41,46>

1 2

1 2

RH91 0_0402_5%

1 2

+3V_PCH

CLK_PCIE_DGPU# <41>

CLK_PCIE_DGPU <41>

CLKREQ#_DGPU <41,43>

+3V_PCH

CLK_CPU_DMI# <8>

CLK_CPU_DMI <8>

CLK_CPU_SSC_DPLL# <8>
CLK_CPU_SSC_DPLL <8>

CLK_CPU_DPLL# <8>
CLK_CPU_DPLL <8>

T80PAD~D @

12

@

T82PAD~D @
T84PAD~D @

+1.05V_+1.5V_RUN

RH927.5K_0402_1%

RPH3

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

+1.5VS

CLK_PEG_GPU# <41,46>

CLK_PEG_GPU <41,46>

Caldera

+3VS

2

1

GPU

CLOCK TERMINATION for FCIM and need close to PCH

CLK_BUF_DMI#
CLK_BUF_DMI
CLK_BUF_BCLK
CLK_BUF_BCLK#

CLK_BUF_DOT96#
CLK_BUF_DOT96

CLK_PCH_14M

CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD

距距距距，從RP拆拆拆拆拆拆

1 2

RH84 1M_0402_5%

RH88

0_0402_5%

12P_0402_50V8J

1 2

2

CH8

1

YH2

25MHZ_10PF_Q22FA2380049900

3

OUT

4

GND

GND

RPH1

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%~D

RPH2

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%~D

1 2

RH79 10K_0402_5%~D

1 2

RH122 10K_0402_5%~D

1 2

RH155 10K_0402_5%~D

1

IN

2

2

1

12P_0402_50V8J

CH9

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2012/02/28 2013/02/27

2012/02/28 2013/02/27

2012/02/28 2013/02/27

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

PCH (3/9) CLK

PCH (3/9) CLK

PCH (3/9) CLK

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-9201P

LA-9201P

LA-9201P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

18 69Wednesday, March 26, 2014

18 69Wednesday, March 26, 2014

18 69Wednesday, March 26, 2014

0.2

0.2

0.2

5

D D

+3VS

1 2

RH98 10K_0402_5%~D

C C

15_0804_8P4R_5%

4 5

SPI_PCH_DO2_R
SPI_PCH_DO3_R
PCH_SPI_SI_R
PCH_SPI_S0_R

1 2

RH104 15_0402_1%EMI@

B B

3 6
2 7
1 8

RPH5

PCH_SPI_DO2
PCH_SPI_DO3
PCH_SPI_SI
PCH_SPI_SO

PCH_SPI_CLKPCH_SPI_CLK_R

SERIRQ

+3V_PCH

1 2

RH105 1K_0402_5%

1 2

RH106 1K_0402_5%

MEM_SMBCLK

MEM_SMBDATA

LPC_AD0<43>

LPC_AD1<43>

LPC_AD2<43>

LPC_AD3<43>

LPC_FRAME#<43>

SERIRQ<43>

PCH_SPI_CLK<44>

PCH_SPI_CS1#<44>

PCH_SPI_SI<44>

PCH_SPI_SO<44>

To TPM

SPI_PCH_DO3_R

SPI_PCH_DO2_R

UH14 to SA000039A30 IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM
UH14 to SA000046400 IC FL 64M EN25Q64-104HIP SOIC 8P SPI ROM
UH14 to SA00006N100 IC FL 64M MX25L647EM2I-10G SOIC 8P SPI ROM
UH14 to SA00005L100 IC FL 64M N25Q064A13ESEC0P SOIC 8P SPI ROM

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

LPC_FRAME#

SERIRQ

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_CS1#

PCH_SPI_SI

PCH_SPI_SO

PCH_SPI_DO2

PCH_SPI_DO3

+3V_PCH

1 2

DMN66D0LDW-7_SOT363-6

4

+3VS

2

2.2K_0402_5%

6 1

@

DMN66D0LDW-7_SOT363-6

@

RH95 0_0402_5%

5

3

4

QH4B

@

12

@

RH96 0_0402_5%

UH1D

A20

LAD_0

C20

LAD_1

A18

LAD_2

C18

LAD_3

B21

LFRAME#

D21

LDRQ0#

G20

LDRQ1#/G PIO23

AL11

SERIRQ

AJ11

SPI_CLK

AJ7

SPI_CS0#

AL7

SPI_CS1#

AJ10

SPI_CS2#

AH1

SPI_MOSI

AH3

SPI_MISO

AJ4

SPI_IO2

AJ2

SPI_IO3

PCH_SPI_CS0#
PCH_SPI_S0_R
SPI_PCH_DO2_R

200 MIL SO8

64Mb Flash ROM

RH107

3.3K_0402_5%~D

@

+3VS

12

RH93

QH4A

12

SPILPC

LYNXPOINT_BGA695

UH4

1

/CS

2

DO(IO1)

3

/WP(IO2 )
GND4DI(IO0)

W25Q64FVSSIQ_SO8

12

RH94

2.2K_0402_5%

LPT_PCH_M_EDS

SMBus

C-Link

Thermal

VCC

/HOLD(IO3)

CLK

SML1ALE RT#/PCHHOT#/GPIO 74

3 OF 11 5

+3V_PCH

8
7

SPI_PCH_DO3_R

6

PCH_SPI_CLK_R

5

PCH_SPI_SI_R

3

PCH_SMBCLK <14,15,36,8>

PCH_SMBDATA <14,15,36,8>

1 2

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_DATA

CL_RST#

TD_IREF

CH10

CL_CLK

N7

R10

U11

N8

U8

R7

H6

K6

N11

AF11

AF10

AF7

BA45

TP1

BC45

TP2

BE43

TP4

BE44

TP3

AY43

SMBALERT#/ GPIO11

SML0ALE RT#/GPIO60

SML1CLK/ GPIO58

SML1DATA/G PIO75

0.1U_0402_25V6K~D

RH127

1 2

RH102

1 2

1 2

SML0CLK <41>

SML0DATA <41>

T85PAD~D @

T86PAD~D @

T87PAD~D @

T88PAD~D @

PCH_LID_SW_IN#

MEM_SMBCLK

MEM_SMBDATA

DDR_HVREF_RST_PCH

SML0CLK

SML0DATA

PCH_GPIO74

SML1CLK

SML1DATA

PCH_TD_IREF

RH103 8.2K_0402_1%

SML1CLK

SML1DATA

0_0402_5%@

0_0402_5%@

354

QH3B

DMN66D0LDW-7

EC_LID_OUT# <43>

LID_SW_IN# <37,38,43>

+3VS

6 1

PCH_SPI_CLK_R

RH108

33_0402_5%~D

1 2

22P_0402_50V8J~D

1

CH11

2

2

2

DMN66D0LDW-7

QH3A

@

@

EC_SMB_CK2 <42,43,46>

EC_SMB_DA2 <42,43,46>

MEM_SMBCLK

MEM_SMBDATA

DDR_HVREF_RST_PCH

PCH_GPIO74

SML1DATA
SML1CLK
SML0DATA
SML0CLK

@

@

RPH4

1 8
2 7
3 6
4 5

2.2K_0804_8P4R_5%

12

RH972.2K_0402_5%

12

RH992.2K_0402_5%

12

RH1001K_0402_1%

12

RH10110K_0402_5%

+3V_PCH

1

+3V_PCH

Reserve for EMI please
close to UH14

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

PCH (4/9) SPI, SMBUS,LPC

PCH (4/9) SPI, SMBUS,LPC

PCH (4/9) SPI, SMBUS,LPC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-B751P

LA-B751P

LA-B751P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

19 69Wednesday, March 26, 2014

19 69Wednesday, March 26, 2014

19 69Wednesday, March 26, 2014

0.1

0.1

0.1

5

D D

4

3

2

1

USB3RN3<35>

1 2
1 2

1 2
1 2

1 2
1 2

USB3RP3<35>

USB3TN3<35>
USB3TP3<35>

+1.5VS

+1.5VS

RH111 7.5K_0402_1%

RH110 0_0402_5%

1 2

P3: JUSB4 Left

PCIE_PRX_GLANTX_N3<30>

10/100/1G LAN

C C

WLAN

CARD READER

B B

PCIE_PRX_GLANTX_P3<30>

PCIE_PTX_GLANRX_N3<30>
PCIE_PTX_GLANRX_P3<30>

PCIE_PRX_WLANTX_N4<28>
PCIE_PRX_WLANTX_P4<28>

PCIE_PTX_WLANRX_N4<28>
PCIE_PTX_WLANRX_P4<28>

PCIE_PRX_CARDTX_N5<31>
PCIE_PRX_CARDTX_P5<31>

PCIE_PTX_CARDRX_N5<31>
PCIE_PTX_CARDRX_P5<31>

CH12 0.1U_0402_25V6K
CH13 0.1U_0402_25V6K

CH14 0.1U_0402_25V6K
CH15 0.1U_0402_25V6K

CH16 0.1U_0402_25V6K
CH17 0.1U_0402_25V6K

USB3RN3

USB3RP3

USB3TN3

USB3TP3

PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3

PCIE_PTX_GLANRX_N3_C
PCIE_PTX_GLANRX_P3_C

PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4

PCIE_PTX_WLANRX_N4_C
PCIE_PTX_WLANRX_P4_C

PCIE_PRX_CARDTX_N5
PCIE_PRX_CARDTX_P5

PCIE_PTX_CARDRX_N5_C
PCIE_PTX_CARDRX_P5_C

12

PCH_PCIE_IREF

@

T91 PAD~D@

T92 PAD~D@

PCH_PCIE_RCOMP

AY31

BE32
BC32

AT31
AR31

BD33
BB33

AW33

AY33

BE34
BC34

AT33
AR33

BE36
BC36

AW36

AV36

BD37
BB37

AY38

AW38

BC38
BE38

AT40
AT39

BE40
BC40

AN38
AN39

BD42
BD41

BE30

BC30

BB29

BD29

PERN1/USB 3RN3
PERP1/US B3RP3

PETN1/USB3 TN3
PETP1/USB 3TP3

PERN2/USB 3RN4
PERP2/US B3RP4

PETN2/USB3 TN4
PETP2/USB 3TP4

PERN_3
PERP_3

PETN_3
PETP_3

PERN_4
PERP_4

PETN_4
PETP_4

PERN_5
PERP_5

PETN_5
PETP_5

PERN_6
PERP_6

PETN_6
PETP_6

PERN_7
PERP_7

PETN_7
PETP_7

PERN_8
PERP_8

PETN_8
PETP_8

PCIE_IREF

TP11

TP6

PCIE_RCOMP

UH1I

AW31

LPT_PCH_M_EDS

LYNXPOINT_BGA695

PCIe

USB

9 OF 11 5

USB2N0

USB2P0

USB2N1

USB2P1

USB2N2

USB2P2

USB2N3

USB2P3

USB2N4

USB2P4

USB2N5

USB2P5

USB2N6

USB2P6

USB2N7

USB2P7

USB2N8

USB2P8

USB2N9

USB2P9
USB2N10
USB2P10
USB2N11
USB2P11
USB2N12
USB2P12
USB2N13
USB2P13

USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN5
USB3RP5
USB3TN5
USB3TP5
USB3RN6
USB3RP6
USB3TN6
USB3TP6

USBRBIAS #

USBRBIAS

TP24
TP23

OC0#/GPI O59
OC1#/GPI O40
OC2#/GPI O41
OC3#/GPI O42
OC4#/GPI O43

OC5#/GPI O9
OC6#/GPI O10
OC7#/GPI O14

B37
D37
A38
C38
A36
C36
A34
C34
B33
D33
F31
G31
K31
L31
G29
H29
A32
C32
A30
C30
B29
D29
A28
C28
G26
F26
F24
G24

AR26
AP26
BE24
BD23
AW26
AV26
BD25
BC24
AW29
AV29
BE26
BC26
AR29
AP29
BD27
BE28

K24
K26

M33
L33

P3
V1
U2
P1
M3
T1
N2
M1

USB_OC0#
USB_OC1#
USB_OC2#

USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9

USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN5
USB3RP5
USB3TN5
USB3TP5
USB3RN6
USB3RP6
USB3TN6
USB3TP6

USBRBIAS

USB20_N0 <34>
USB20_P0 <34>
USB20_N1 <35>
USB20_P1 <35>
USB20_N2 <41>
USB20_P2 <41>
USB20_N3 <37>
USB20_P3 <37>
USB20_N4 <28>
USB20_P4 <28>
USB20_N5 <25>
USB20_P5 <25>
USB20_N6 <25>
USB20_P6 <25>
USB20_N7 <34>
USB20_P7 <34>
USB20_N8 <35>
USB20_P8 <35>
USB20_N9 <69>
USB20_P9 <69>

USB3RN1 <34>
USB3RP1 <34>
USB3TN1 <34>
USB3TP1 <34>
USB3RN2 <34>
USB3RP2 <34>
USB3TN2 <34>
USB3TP2 <34>
USB3RN5 <41>
USB3RP5 <41>
USB3TN5 <41>
USB3TP5 <41>
USB3RN6 <35>
USB3RP6 <35>
USB3TN6 <35>
USB3TP6 <35>

T89PAD~D @
T90PAD~D @

USB_OC0# <34>
USB_OC1# <34>
USB_OC2# <32>

USB_OC4# <32>

JUSB1(Right Side)

JUSB3(Left Side) PowerShare

Caldera

ELC LED

BT

Thuch sereen

Camera

JUSB1(Right Side)

JUSB4(Left Side)

Touch PAD

P1: JUSB1 Right

On MB

P2: JUSB2 Right

P5: Calder

P6: JUSB3 Left

CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils.

USBRBIAS

22.6_0402_1%

12

RH109

+3V_PCH

RPH6

4 5

USB_OC4#

3 6

USB_OC7#USB_OC3#

2 7

USB_OC6#

1 8

USB_OC3#

10K_0804_8P4R_5%

RPH7

4 5

USB_OC0#

3 6

USB_OC1#

2 7

USB_OC2#

1 8

USB_OC5#

10K_0804_8P4R_5%

SD302100280 Chnage SD309100280 2/25

採採採採

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

PCH (5/9) PCIE,USB

PCH (5/9) PCIE,USB

PCH (5/9) PCIE,USB

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-B751P

LA-B751P

LA-B751P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

20 69Wednesday, March 26, 2014

20 69Wednesday, March 26, 2014

20 69Wednesday, March 26, 2014

0.1

0.1

0.1

5

+3VS

1 2

RH113 10K_0402_5%~D

D D

C C

B B

RH115 10K_0402_5%~D

RH116 10K_0402_5%~D

RH117 10K_0402_5%~D

RH118 10K_0402_5%~D

RH119 10K_0402_5%~D

RH120 10K_0402_5%~D

RH121 10K_0402_5%~D

RH151 10K_0402_5%~D

RH154 10K_0402_5%~D

+3V_PCH

+PCH_VCCDSW3_3

RH156 10K_0402_5%~D

PCH_GPIO0

1 2

PCH_GPIO1

1 2

PCH_GPIO6

12

STP_PCI#

1 2

PCH_GPIO22

1 2

PCH_GPIO39

1 2

PCH_GPIO70

1 2

PCH_GPIO71

1 2

PCH_GPIO68

1 2

TPM_PIRQ#

for TPM

12

12

HDD_DET#

12

PCH_GPIO35

WAKE_PCH#

RH123 10K_0402_5%

RH126 10K_0402_5%

+3VS

USB X4,PCIEX8,SATAX6

4

EC_SCI#<43>

EC_SMI#<43>

GPU_GC6_FB_EN<43,46>

PCH_GPIO16<29>

12

12

12

12

TPM_PIRQ#<44>

DGPU_PWR_EN<46,49,63>

WAKE_PCH#<43>

GC6_EVENT#<43,46>

PCH_GPIO49<29>

HDD_DET#<36>

PCH_GPIO49

PCH_GPIO16

KB_DET#

PCH_GPIO16

KB_DET#

PCH_GPIO49

FFS_INT2<36>

KB_DET#<39>

To TPM

1 2

RH157 10K_0402_5%~D

1 2

RH130 10K_0402_5%~D

RH131 10K_0402_5%~D

RH132 10K_0402_5%~D@

RH133 10K_0402_5%~D@

RH158 10K_0402_5%~D@

Config

GPIO16,49

11

01USB X6,PCIEX8,SATAX4

PCH_GPIO0

PCH_GPIO1

PCH_GPIO6

EC_SCI#

EC_SMI#

GPU_GC6_FB_EN

PCH_GPIO16

TPM_PIRQ#

PCH_GPIO22

WAKE_PCH#

GC6_EVENT#

STP_PCI#

PCH_GPIO35

PCH_GPIO36

PCH_GPIO37

DGPU_PRSNT#

PCH_GPIO39

FFS_INT2

PCH_GPIO49

HDD_DET#

PCH_GPIO68

KB_DET#

PCH_GPIO70

PCH_GPIO71

3

LPT_PCH_M_EDS

UH1F

AT8

BMBUSY#/GP IO0

F13

TACH1/GPIO1

A14

TACH2/GPIO6

G15

TACH3/GPIO7

Y1

GPIO8

K13

LAN_PHY_P WR_CTRL/GPI O12

AB11

GPIO15

AN2

SATA4GP/G PIO16

C14

TACH0/GPIO1 7

BB4

SCLOCK/G PIO22

Y10

GPIO24

R11

GPIO27

AD11

GPIO28

AN6

GPIO34

AP1

GPIO35/N MI#

AT3

SATA2GP/G PIO36

AK1

SATA3GP/G PIO37

AT7

SLOAD/GP IO38

AM3

SDATAOUT0/GP IO39

AN4

SDATAOUT1/GP IO48

AK3

SATA5GP/G PIO49

U12

GPIO57

C16

TACH4/GPIO6 8

D13

TACH5/GPIO6 9

G13

TACH6/GPIO7 0

H15

TACH7/GPIO7 1

BE41

VSS

BE5

VSS

C45

VSS

A5

VSS

LYNXPOINT_BGA695

For BIOS setting dGPU present

LOW - dGPU exist*

+3VS

GPIO

NCTF

6 OF 11 5

@

1 2

1 2

DGPU_PRSNT#

DGPU_PRSNT#

RH134 10K_0402_5%~D

RH135 10K_0402_5%~D

CPU/Misc

PROCPW RGD

THRMTRIP#

PLTRST_PROC#

RCIN#

2

+3VS

GATEA20

KB_RST#

AN10

GATEA20

TP14

AY1

H_PECI_R

PECI

AT6

KB_RST#

AV3

H_CPUPWRGD

AV1

PCH_THRMTRIP#_R_R

AU4

CPU_PLTRST#

N10

VSS

A2

VSS

A41

VSS

A43

VSS

A44

VSS

B1

VSS

B2

VSS

B44

VSS

B45

VSS

BA1

VSS

BC1

VSS

BD1

VSS

BD2

VSS

BD44

VSS

BD45

VSS

BE2

VSS

BE3

VSS

D1

VSS

E1

VSS

E45

VSS

A4

VSS

T81

KB_RST# <43>

H_CPUPWRGD <8>

CPU_PLTRST# <8>

1 2

RH124 390_0402_5%

+3VS

RH136 1K_0402_1%~D

1 2

RH137 200K_0402_5%@

RH138 10K_0402_5%~D@

RH139 10K_0402_5%~D

12

12

12

PCH_GPIO36

PCH_GPIO37

PCH_GPIO36

PCH_GPIO37

12

RH11210K_0402_5%~D

12

RH11410K_0402_5%~D

H_THERMTRIP# <8>

1

SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK.
WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER
PLRST_N DE-ASSERTS).
NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED.

A A

Same with 534345_PCH_LPT_9

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2014/2/11 2014/2/11

2014/2/11 2014/2/11

2014/2/11 2014/2/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

PCH (6/9) GPIO,MISC,NTFC

PCH (6/9) GPIO,MISC,NTFC

PCH (6/9) GPIO,MISC,NTFC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-B751P

LA-B751P

LA-B751P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

21 69Wednesday, March 26, 2014

21 69Wednesday, March 26, 2014

21 69Wednesday, March 26, 2014

0.1

0.1

0.1