Compal LA-B441P Schematic

MODEL NAME :

PCB NO :

BOM P/N :

ZZZ

1 1

MB_PCB

DAA0008I000

LA-B441P

TBD

ZAZ00

Dell/Compal Confidential

2 2

Schematic Document

Dino (Broadwell ULT)

3 3

2014-10-16

Rev: 1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P01-Cover Page

LA-B441P

150Thursday, October 16, 2014

1.0

www.vinaﬁx.vn

eDP Panel

miniDP Conn.

1 1

USB 3.0 Conn.

Precision Touch Pad

Digital Camera

Touch Screen

P.22

P.26

P.30

P.35

P.22

Daughter/B (LS-B441P)

USB 3.0 Conn.

2 2

( Power Share)

CardReader RTS5249

USB3.0

USB3.0 Re-Driver

eDP 1.3

DP 1.2

USB3.0/USB2.0

I2C / PS2

USB2.0

USB3.0

USB2.0

PCIE

Intel

Broadwell ULT

BGA 1168 Balls

15W TDP

Memory Bus (DDR3L-RS)

Dual Channel

1.35V DDR3L-RS 1600 MHz

SPI

SATA3 / PCIE *2

USB2.0

PCIE

UART

SDIO

Channel A DDR3L-RS 4Gb or 8Gb (x16) * 4

P.15,16

Channel B DDR3L-RS 4Gb or 8Gb (x16) * 4

P.17,18

SPI ROM 8MB

SPI ROM(vPRO) 4MB

TPM AT97SC3205

M.2 Slot B Key-B

# mSATA

M.2 Slot A-SD

WLAN BT

P.08

P.27

P.29

P.28

ALS/B (LS-B444P)

(Reserved ALS)

TCS3472

Reserved NFC Module Conn

(Reserved SMLink)

P.29

3 3

Fan conn.

P.29

(Reserve ALS SM BUS)

RTC conn.

DC/DC Interface CKT.

Power Circuit DC/DC

4 4

LED/B (LS-B443P)

P.32~33

P.38~48

Front Side LED+DMICx2 Board

SMBus

ECE1117

LPC Bus

MEC 5085

BCBUS

Page 5 ~ 14

HDA / I2S

Audio Codec ALC3263

P.36

I2C

MCP 23017

P.37

KBC/B (LS-B442P)

KSIO

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

Int.KBDKeyboard Controller

DMIC

Compal Secr et Data

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

Headphone Jack

( iPhone & Nokia compatible)

P.24

Int. Speaker

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P02-Block Diagram

LA-B441P

P.25

250Saturday, October 04, 2014

1.0

1 1

CPU Option

UCPU1

BDW_TBD@

UCPU1

BDW_TBD@

SA00006G10L

CL8064701325204 QDJ9

DRAM Option DRAM Config Option

UD32

Micron_4G@

UD32

UD28

Micron_4G@

UD29

Micron_4G@

UD31

Micron_4G@

UD4

Micron_4G@

UD4

UD7

Micron_4G@

UD7

UD1

Micron_4G@

UD1

Micron_4G@

UD3

Micron_4G@

UD3

Micron_4G@

Micron 4G

SA00005TH0L

2 2

SA00005TH0L

MT41K256M16HA-125M:E

UD28

Micron_8G@

UD28

Micron_8G@

SA00005TH0L

MT41K256M16HA-125M:E

UD29

Micron_8G@

UD29

Micron_8G@

SA00005TH0L

MT41K256M16HA-125M:E

UD31

Micron_8G@

UD31

Micron_8G@

SA00005TH0L

MT41K256M16HA-125M:E

UD32

Micron_8G@

UD32

Micron_8G@

SA00005TH0L

MT41K256M16HA-125M:E

UD1

Micron_8G@

UD1

Micron_8G@

SA00005TH0L

MT41K256M16HA-125M:E

UD7

Micron_8G@

UD7

Micron_8G@

SA00005TH0L

MT41K256M16HA-125M:E

UD3

Micron_8G@

UD3

Micron_8G@

SA00005TH0L

MT41K256M16HA-125M:E

UD4

Micron_8G@

UD4

Micron_8G@

Micron 8G

SA00006FB0L

MT41K512M16TNA-125M:E

UD28

Hynix_4G@

UD28

Hynix_4G@

SA00006FB0L

MT41K512M16TNA-125M:E

UD29

Hynix_4G@

UD29

Hynix_4G@

SA00006FB0L

MT41K512M16TNA-125M:E

UD31

Hynix_4G@

UD31

Hynix_4G@

SA00006FB0L

MT41K512M16TNA-125M:E

UD32

Hynix_4G@

UD32

Hynix_4G@

SA00006FB0L

MT41K512M16TNA-125M:E

UD1

Hynix_4G@

UD1

Hynix_4G@

SA00006FB0L

MT41K512M16TNA-125M:E

UD7

Hynix_4G@

UD7

Hynix_4G@

SA00006FB0L

MT41K512M16TNA-125M:E

UD3

Hynix_4G@

UD3

Hynix_4G@

SA00006FB0L

MT41K512M16TNA-125M:E

UD4

Hynix_4G@

UD4

Hynix_4G@

Hynix 4G

SA00006JF0L

H5TC4G63AFR-PBR

UD28

Hynix_8G@

UD28

Hynix_8G@

SA00006JF0L

H5TC4G63AFR-PBR

UD29

Hynix_8G@

UD29

Hynix_8G@

SA00006JF0L

H5TC4G63AFR-PBR

UD31

Hynix_8G@

UD31

Hynix_8G@

SA00006JF0L

H5TC4G63AFR-PBR

UD32

Hynix_8G@

UD32

Hynix_8G@

SA00006JF0L

H5TC4G63AFR-PBR

UD1

Hynix_8G@

UD1

Hynix_8G@

SA00006JF0L

H5TC4G63AFR-PBR

UD7

Hynix_8G@

UD7

Hynix_8G@

SA00006JF0L

H5TC4G63AFR-PBR

UD3

Hynix_8G@

UD3

Hynix_8G@

SA00006JF0L

H5TC4G63AFR-PBR

UD4

Hynix_8G@

UD4

Hynix_8G@

SA00006JF0L

Hynix 8G

SA00006Q90L

H5TC8G63AMR-PBR

3 3

UD28

Elpida_4G@

SA00006Q90L

H5TC8G63AMR-PBR

UD29

Elpida_4G@

UD29

Elpida_4G@

SA00006Q90L

H5TC8G63AMR-PBR

UD31

Elpida_4G@

UD31

Elpida_4G@

SA00006Q90L

H5TC8G63AMR-PBR

UD32

Elpida_4G@

UD32

Elpida_4G@

SA00006Q90L

H5TC8G63AMR-PBR

UD1

Elpida_4G@

UD1

Elpida_4G@

SA00006Q90L

H5TC8G63AMR-PBR

UD7

Elpida_4G@

UD7

Elpida_4G@

SA00006Q90L

H5TC8G63AMR-PBR

UD3

Elpida_4G@

UD3

Elpida_4G@

SA00006Q90L

H5TC8G63AMR-PBR

UD4

Elpida_4G@

UD4

Elpida_4G@

Elpida 4G

SA00005HT0L

K4B4G1646B-HKK0

UD28

Elpida_8G@

UD28

Elpida_8G@

SA00005HT0L

K4B4G1646B-HKK0

UD29

Elpida_8G@

UD29

Elpida_8G@

SA00005HT0L

K4B4G1646B-HKK0

UD31

Elpida_8G@

UD31

Elpida_8G@

SA00005HT0L

K4B4G1646B-HKK0

UD32

Elpida_8G@

UD32

Elpida_8G@

SA00005HT0L

K4B4G1646B-HKK0

UD1

Elpida_8G@

UD1

Elpida_8G@

SA00005HT0L

K4B4G1646B-HKK0

UD7

Elpida_8G@

UD7

Elpida_8G@

SA00005HT0L

K4B4G1646B-HKK0

UD3

Elpida_8G@

UD3

Elpida_8G@

SA00005HT0L

K4B4G1646B-HKK0

UD4

Elpida_8G@

UD4

Elpida_8G@

Elpida 8G

SA00006O90L

K4B8G1646B-MKK0

SA00006O90L

K4B8G1646B-MKK0

SA00006O90L

K4B8G1646B-MKK0

SA00006O90L

K4B8G1646B-MKK0

SA00006O90L

K4B8G1646B-MKK0

SA00006O90L

K4B8G1646B-MKK0

SA00006O90L

K4B8G1646B-MKK0

SA00006O90L

K4B8G1646B-MKK0

MEM_CONFIG2 MEM_CONFIG1 MEM_CONFIG0

RH316

Micron_4G@

RH316

RH314

Micron_4G@

RH314

Micron_4G@

SD028100280

10K_0402_5%~D

RH314

Micron_8G@

RH314

Micron_8G@

SD028100280

10K_0402_5%~D

RH314

Hynix_4G@

RH314

Hynix_4G@

SD028100280

10K_0402_5%~D

RH314

Hynix_8G@

RH314

Hynix_8G@

SD028100280

10K_0402_5%~D

RH271

Elpida_4G@

RH271

Elpida_4G@

SD028100280

10K_0402_5%~D

RH271

Elpida_8G@

RH271

Elpida_8G@

SD028100280

10K_0402_5%~D

RH315

Micron_4G@

RH315

Micron_4G@

SD028100280

10K_0402_5%~D

RH315

Micron_8G@

RH315

Micron_8G@

SD028100280

10K_0402_5%~D

RH180

Hynix_4G@

RH180

Hynix_4G@

SD028100280

10K_0402_5%~D

RH180

Hynix_8G@

RH180

Hynix_8G@

SD028100280

10K_0402_5%~D

RH315

Elpida_4G@

RH315

Elpida_4G@

SD028100280

10K_0402_5%~D

RH315

Elpida_8G@

RH315

Elpida_8G@

SD028100280

10K_0402_5%~D

Micron_4G@

SD028100280

10K_0402_5%~D

RH303

Micron_8G@

RH303

Micron_8G@

SD028100280

10K_0402_5%~D

RH316

Hynix_4G@

RH316

Hynix_4G@

SD028100280

10K_0402_5%~D

RH303

Hynix_8G@

RH303

Hynix_8G@

SD028100280

10K_0402_5%~D

RH316

Elpida_4G@

RH316

Elpida_4G@

SD028100280

10K_0402_5%~D

RH303

Elpida_8G@

RH303

Elpida_8G@

SD028100280

10K_0402_5%~D

4 4

LA-B441P

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P03-BoM Option

350Saturday, October 04, 2014

1.0

Board ID Table for AD channel

X01

X03 X04 A00

REV

CE54RE79

4700p130K 4700p

62K X02

4700p

33K

4700p

8.2K 4700p4.3K 4700p

2K 1K

4700p

BOARD_ID rise time is measured from 5%~68%.

PCH USB Port Mapping

USB PORT#

DESTINATION

External USB3(On IOB)

External USB3(On MB)

NGFF CARD WLAN

Touch Panel

Camera

SMBUS Control Table

SOURCE

I2C1C_CLK I2C1C_DATA

1 1

I2C1D_CLK I2C1D_DATA

I2C1G_CLK I2C1G_DATA

PCH_SML0CLK PCH PCH_SML0DATA

PCH_SML1CLK PCH_SML1DATA

SMBCLK SMBDATA

I2C1_DATA

MEC5085

PCH

PCHI2C1_CLK

BATTERY

Reserve ALS SMBUS

ALS

NFCCharger

XDP

Touch Pad

PCH DDI Port

Link

Mapping

DDI PORT# DESTINATION

mini-DP

CLK

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

FLEX CLK#

CLKOUT_LPC_0

CLKOUT_LPC_1

DESTINATIONDIFFERENTIAL CLK#

Card Reader

NGFF CARD WLAN

mSATA/ PCIe

DESTINATION

EC LPC

TPM

PCI EXPRESS PORT#

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

DESTINATION

Card Reader

NGFF CARD WLAN

mSATA/ PCIe(Port0+Port1)

SATA PORT#

DESTINATION

SATA0

SATA1

SATA2

SATA3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

m-SATA

Compal Secr et Data

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

Symbol Note :

: means Digital Ground

: means Analog Ground

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P04-Notes List

LA-B441P

450Saturday, October 04, 2014

1.0

D D

DP Port

PCH_DP_N0[26] PCH_DP_P0[26] PCH_DP_N1[26] PCH_DP_P1[26] PCH_DP_N2[26] PCH_DP_P2[26] PCH_DP_N3[26] PCH_DP_P3[26]

C C

BDW_ULT_DDR3L

C54 C55

C58

C51 C50 C53

C49

B58

B55 A55 A57 B57

B54

B50 A53 B53

UCPU1A@

DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3

DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3

UCPU1I@

1 OF 19

C45

EDP_TXN0

B46

EDP_TXP0

A47

EDP_TXN1

B47

EDP_TXP1

C47

EDP_TXN2

C46

EDP_TXP2

A49

EDPDDI

EDP_TXN3 EDP_TXP3

EDP_AUXN EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

B49

A45 B45

D20 A43

EDP_COM EDP_DISP

eDP_TXN_P0 [22] eDP_TXP_P0 [22] eDP_TXN_P1 [22] eDP_TXP_P1 [22]

eDP_TXN_P2 [22] eDP_TXP_P2 [22] eDP_TXN_P3 [22] eDP_TXP_P3 [22]

eDP_AUXN [22] eDP_AUXP [22]

1 2

RC36 24.9_0402_1%RC36 24.9_0402_1%

EDP_COM Width 20 mils, Spacing 25 mils, Length < 100 mil

+VCCIOA_OUT

Low voltage multipurpose DISP_UTIL pin on the processor for backlight modulation control of embedded panels and S3D device control for active shutter glasses. This pin will co-exist with functionality similar to existing BKLTCTL pin on the PCH.

A00_1004: Change to short pad.

RC147

0_0402_1%

EDP_BKLCTL

EDP_DISP

RC146

RC146 0_0402_5%~D

0_0402_5%~D

1 2

RC158

RC158 0_0402_5%~D

0_0402_5%~D

1 2

EDP_BIA_PWM [22]

EDP_HPD

Compal Secret Data

PCH_DP_CLK

PCH_DP_DAT

D9 D11

C5 B6 B5 A6

PCH_DP_HPD

A8 D6

CPU_EDP_HPD

Enable : Pull up to 3.3V with 2.2K+-5% ohm Disable : No connect

Deciphered Date

PCH_DP_CLK [26] PCH_DP_DAT [26]

PCH_DP_AUXN [26]

PCH_DP_AUXP [26]

PCH_DP_HPD [26]

PCH_DP_HPD

+5VS

RC148

0_0402_1%

CPU_EDP_HPD

Title

P05-MCP(1/10) DDI,EDP

Size Document Number Rev

LA-B441P

Date: Sheet of

0_0402_1%

A00_1004: Change to short pad.

RC160

RC160 100K_0402_5%~D

100K_0402_5%~D

Compal Electronics, Inc.

QC5

DII-DMN65D8LW-7~D

RH300100K_0402_5%~D RH300100K_0402_5%~D

EDP_HPD [22]

550Sunday, October 05, 2014

1.0

AD4

B8 A9 C6

U6 P4 N4 N2

U7 L1 L3 R5 L4

EDP_BKLCTL EDP_BKLEN EDP_VDDEN

PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO79 PIRQD/GPIO80 PME

GPIO55 GPIO52 GPIO54 GPIO51 GPIO53

eDP SIDEBAND

PCIE

9 OF 19

DISPLAY

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP

DDPB_HPD DDPC_HPD

PANEL_BKLEN[22] ENVDD_PCH[32,36]

DZ3

DZ3 RB751S40T1G_SOD523-2

RB751S40T1G_SOD523-2

PTP_INT#[35,36]

B B

1 2

T123@T123

SDIO_WAKE#[28]

CODEC_IRQ[24]

EDP_BKLCTL

PCH_GPIO77 PCH_GPIO78 PCH_GPIO79 PCH_GPIO80

TOUCHPAD _INTR# TOUCH_R ST_N_GYRO_IN T1 SDIO_WAKE# PCH_GPIO51 CODEC_IRQ

GPIO Signals

+3VS

RP4

1 8 2 7 3 6 4 5

10K_8P4R_5%

1 2

RH3547 10K_0402_5%~DRH3547 10K_0402_5%~D

1 2

RH3545 10K_0402_5%~DRH3545 10K_0402_5%~D

1 2

RH397 10K_0402_5%~DRH397 10K_0402_5%~D

1 2

RH3532 10K_0402_5%~D@RH3532 10K_0402_5%~D@

1 2

A A

RH3544 10K_0402_5%~D@RH3544 10K_0402_5%~D@

PCH_GPIO79 PCH_GPIO80 TOUCHPAD _INTR# PCH_DP_CLK PCH_GPIO78

PCH_GPIO77 TOUCH_R ST_N_GYRO_IN T1 SDIO_WAKE# CODEC_IRQ

PCH_GPIO51

+3VS

RP14

1 8 2 7 3 6 4 5

2.2K_0804_8P4R_5%

Security Classifi cation

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

PCH_DP_DAT

Functional Strap Definitions

DDI Port 1 Disabling

DDPB_CTRLDATA

Functional Strap Definitions

DDI Port 2 Disabling

DDPC_CTRLDATA

2013/07/04 2013/10/28

D D

+1.05VS_VCCST

RC43

RC43 62_0402_5%~D

62_0402_5%~D

H_PROCHOT#[36,39,40,42,47]

Avoid stub in the PWRGD path while placing resistors RC44 & RC53

C C

SM_RCOMP

1. Total Width : 12-15 mils.

2. Min Trace spacing for Group : 20 mils

3. Min Trace spacing for Group to Group :25 mils

4. Max Length : 500 mils

+1.35V_DDR

CC240

0.1U_0402_10V7K

+3VALW

B B

RC161

RC161 220K_0402_5%~D

220K_0402_5%~D

H_PECI

1. Total Length : 15 inchs

2. Resistor Value (±5%) : 43 ohm

3. Breakin/Breakout Length Max :0.4 ~ 1 inchs

H_CATERR#

H_PROCHOT#_RH_PROCHOT#

H_CPUPWRGD_R

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

T2@T2@

PECI_EC[36]

1 2

RC41 56_0402_5%RC41 56_0402_5%

1 2

RC44 10K_0402_5%~DRC44 10K_0402_5%~D

1 2

RC55 200_0402_1%~DRC55 200_0402_1%~D

1 2

RC58 121_0402_1%~DRC58 121_0402_1%~D

1 2

RC60 100_0402_1%~DRC60 100_0402_1%~D

H_DRAMRST#[15]

UC1

74AUP1G07GW_TSSOP5

VCC

GND

D61 K61 N62

K63

C61

AU60 AV60 AU61 AV15 AV61

UCPU1B@

PROC_DETECT CATERR PECI

PROCHOT

PROCPWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1

MISC

THERMAL

PWR

DDR3L

BDW_ULT_DDR3L

JTAG

2 OF 19

PRDY

PREQ PROC_TCK PROC_TMS

PROC_TRST

PROC_TDI

PROC_TDO

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

J62

XDP_PRD Y#

K62

XDP_PRE Q#

E60

CPU_XDP_TCK

E61

CPU_XDP_TMS

E59

CPU_XDP_TRST#

F63

CPU_XDP_TDI

F62

CPU_XDP_TDO

J60 H60 H61 H62 K59 H63 K60 J61

XDP_PRD Y# [20] XDP_PRE Q# [20] CPU_XDP_TCK [20] CPU_XDP_TMS [20] CPU_XDP_TRST# [20] CPU_XDP_TDI [20]

CPU_XDP_TDO [20]

XDP_BPM0 # [20] XDP_BPM1 # [20]

T226@T22 6@ T227@T22 7@ T228@T22 8@ T229@T22 9@ T230@T23 0@ T231@T23 1@

Place a test point pad to within 250 ps of the ROC_TCK pin.and the maximum distance of test point pad to the termination must not be over 200 ps.

The Pull Up/Pull down terminations (R1d,R2,R9) should be placed to within 200 ps (1100 mils) of respective Broadwell pins.

CPU_XDP_TDO

CPU_XDP_TCK

CPU_XDP_TRST#

BPM

1. Length match these signals within 360 mils.

2. Stubs on these nets should be limited to less than 1400 mils (35.5 mm) in length.

3. Routing Recommendation :1-6 inchs

4. Impedance : 50 ohm.

XDP_PRD Y# XDP_PRE Q# CPU_XDP_TCK CPU_XDP_TMS CPU_XDP_TRST# CPU_XDP_TDI CPU_XDP_TDO

R1d

RC48 51_0402_5%RC48 51_0402_5%

RC52 51_0402_5%RC52 51_0402_5%

RC54 51_0402_5%@ RC54 51_0402_5%@

T263@T26 3@ T264@T26 4@ T265@T26 5@ T266@T26 6@ T267@T26 7@ T268@T26 8@ T269@T26 9@

+1.05VS_VCCST

SM_PG_CTRL[46]

A A

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/07/04 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P06-MCP(2/10) PM,XDP

LA-B441P

1.0

650Saturday, October 04, 2014

1.0

DDR_A_D[0..63] [15,16] DDR_B_D[0..63] [17,18]

BDW_ULT_DDR3L

UCPU1C@

D D

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28

C C

DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57

B B

DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58

AW58

AY56

AW56

AV58 AU58 AV56 AU56 AY54

AW54

AY52

AW52

AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51

UCPU1C@

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

BDW_ULT_DDR3L

DDR CHANNEL A

3 OF 19

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1

SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3

SA_CS#0 SA_CS#1

SA_ODT0

SA_RAS

SA_WE

SA_CAS

SA_BA0 SA_BA1 SA_BA2

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1

AU37 AV37 AW36 AY36

AU43 AW43 AY42 AY43

AP33 AR32

AP32

AY34 AW34 AU34

AU35 AV35 AY41

AU36

DDR_A_MA0

AY37

DDR_A_MA1

AR38

DDR_A_MA2

AP36

DDR_A_MA3

AU39

DDR_A_MA4

AR36

DDR_A_MA5

AV40

DDR_A_MA6

AW39

DDR_A_MA7

AY39

DDR_A_MA8

AU40

DDR_A_MA9

AP35

DDR_A_MA10

AW41

DDR_A_MA11

AU41

DDR_A_MA12

AR35

DDR_A_MA13

AV42

DDR_A_MA14

AU42

DDR_A_MA15

AJ61

DDR_A_DQS#0

AN62

DDR_A_DQS#1

AM58

DDR_A_DQS#2

AM55

DDR_A_DQS#3

AV57

DDR_A_DQS#4

AV53

DDR_A_DQS#5

AL43

DDR_A_DQS#6

AL48

DDR_A_DQS#7

AJ62

DDR_A_DQS0

AN61

DDR_A_DQS1

AN58

DDR_A_DQS2

AN55

DDR_A_DQS3

AW57

DDR_A_DQS4

AW53

DDR_A_DQS5

AL42

DDR_A_DQS6

AL49

DDR_A_DQS7

AP49 AR51 AP51

at least 20 mils wide with 20 mils spacing to other signals/planes. Short violations are acceptable if required due to tight routing constraints.

M_CLK_A_ DDR#0 [1 5,16,19] M_CLK_A_ DDR0 [15 ,16,19]

DDR_A_CKE0 [15,16,19] DDR_A_CKE1 [15,16,19]

DDR_A_CS0# [15,16,19]

DDR_A_RAS# [15,16,19] DDR_A_WE# [15,16,19] DDR_A_CAS# [15,16,19]

DDR_A_BA0 [15,16,19] DDR_A_BA1 [15,16,19] DDR_A_BA2 [15,16,19] DDR_A_MA[0..15] [15,16,19]

DDR_A_DQS#[0..7] [15,16]

DDR_A_DQS[0..7] [15,16]

V_DDR_REF_CA [19] V_DDR_REF_DQA [19] V_DDR_REF_DQB [19]

UCPU1D@

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AY31

AW31

AY29

AW29

AV31

AU31

AV29

AU29

AY27

AW27

AY25

AW25

AV27

AU27

AV25 AU25 AM29

AK29

AL28

AK28 AR29 AN29 AR28

AP28 AN26 AR26 AR25

AP25

AK26 AM26

AK25

AL25

AY23

AW23

AY21

AW21

AV23 AU23

AV21 AU21

AY19

AW19

AY17

AW17

AV19 AU19

AV17 AU17 AR21 AR22

AL21 AM22 AN22

AP21

AK21

AK22 AN20 AR20

AK18

AL18

AK20 AM20 AR18

AP18

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

BDW_ULT_DDR3L

DDR CHANNEL B

4 OF 19

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3

SB_CS#0 SB_CS#1

SB_ODT0

SB_RAS

SB_WE

SB_CAS

SB_BA0 SB_BA1 SB_BA2

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

AM38 AN38 AK38 AL38

AY49 AU50 AW49 AV50

AM32 AK32

AL32

AM35 AK35 AM33

AL35 AM36 AU49

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

M_CLK_B _DDR#0 [1 7,18,19] M_CLK_B _DDR0 [17 ,18,19]

DDR_B_CKE0 [17,18,19] DDR_B_CKE1 [17,18,19]

DDR_B_CS0# [17,18,19]DDR_A_CS1# [15,16,19] DDR_B_CS1# [17,18,19]

DDR_B_RAS# [17,18,19] DDR_B_WE# [17,18,19] DDR_B_CAS# [17,18,19]

DDR_B_BA0 [17,18,19] DDR_B_BA1 [17,18,19] DDR_B_BA2 [17,18,19] DDR_B_MA[0..15] [17,18,19]

DDR_B_DQS#[0..7] [17,18]

DDR_B_DQS[0..7] [17,18]

A A

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/07/04 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P07-MCP(3/10) DDRIII

LA-B441P

1.0

750Saturday, October 04, 2014

1.0

RP5

D D

SPI_CLK_VROM

PCH_SPI_CLK_TPM[27]

SPI_SI_VROM

PCH_SPI_SI_TPM[27]

1 8 2 7 3 6 4 5

33_8P4R_5%

1 8 2 7 3 6 4 5

33_8P4R_5%

PCH_SPI_CLKSPI_CLK_ROM

RP6

PCH_SPI_SISPI_SI_ROM

RH55

RH55 1K_0402_5%~D

1K_0402_5%~D

+3.3V_M

RH57

RH57 1K_0402_5%~D

1K_0402_5%~D

+3.3V_M

RH3527

@0_0603_5%

EMI@

CH1245

15P_0402_50V8J

RF Reserved.

+3V_ROM

vpro@

CH1249

15P_0402_50V8J

RF Reserved.

LPC_AD0[36] LPC_AD1[36] LPC_AD2[36] LPC_AD3[36] LPC_FRAME#[36]

A00_1004: Change to short pad.

PCH_SPI_CS2#[27]

MC29

@MC29

1 2

12P_0402_50V8J~D

EMI@

MC30

22P_0402_50V8J~D

Reserve for EMI please close to U48

MC32

22P_0402_50V8J~D

Reserve for EMI please close to U727

PCH_SPI_CLK PCH_SPI_CS0# PCH_SPI_CS1#

PCH_SPI_SI PCH_SPI_SO PCH_SPI_IO2 PCH_SPI_IO3

PCH_SPI_CLK

SPI_CLK_ROM

SPI_CLK_VROM

AU14 AW12

AY12

AW11

AV12

BDW_ULT_DDR3L

UCPU1G@

LAD0 LAD1 LAD2 LAD3 LFRAME

AA3

SPI_CLK

SPI_CS0

SPI_CS1

AC2

SPI_CS2

AA2

SPI_MOSI

AA4

SPI_MISO

SPI_IO2

AF1

SPI_IO3

BDW_ULT_DDR3L

LPC

SMBUS

SML1ALERT/PCHHOT /GPIO73

C-LINKSPI

SMBALERT/GPIO11

SMBDATA

SML0ALERT/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO75

SML1DATA/GPIO74

CL_DATA

7 OF 19

SMBCLK

CL_CLK

CL_RST

AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3

AF2 AD2 AF4

PCH_SMB_ALERT# PCH_SMBCLK PCH_SMBDATA PCH_SML0ALERT SML0CLK SML0DATA PCH_GPIO73 SML1_SMBCLK SML1_SMBDAT

PCH_SMBCLK [20] PCH_SMBDATA [20]

SML0CLK [29] SML0DATA [29]

SML1_SMBCLK [36] SML1_SMBDAT [36]

CL_CK [28] CL_DAT [28] CL_RST# [28]

Connect XDP

Connect NFC

Connect EC

PCH_SMBCLK PCH_SMBDATA SML1_SMBCLK SML1_SMBDAT

SML0CLK SML0DATA

PCH_SMB_ALERT# PCH_SML0ALERT PCH_GPIO73

RP2

1 8 2 7 3 6 4 5

2.2K_0804_8P4R_5%

1 2

RH70 499_0402_1%~DRH70 499_0402_1%~D

1 2

RH72 499_0402_1%~DRH72 499_0402_1%~D

RP16

1 8 2 7 3 6 4 5

10K_8P4R_5%

+3V_PCH

RP7

1 8

SPI_SO_VROM

PCH_SPI_SO_TPM[27]

SPI_IO3_VROM SPI_IO3_ROM

SPI_IO2_VROM

C C

2 7 3 6 4 5

33_8P4R_5%

1 8 2 7 3 6 4 5

33_8P4R_5%

PCH_SPI_SOSPI_SO_ROM

RP8

PCH_SPI_IO3

PCH_SPI_IO2SPI_IO2_ROM

SPI ROM FOR ME ( 8MByte )

U48

PCH_SPI_CS0# SPI_SO_ROM

4MB SPI ROM for Vpro

PCH_SPI_CS1# SPI_SO_VROM SPI_IO2_VROM

B B

/CS

DO(IO1)

/WP(IO2) GND4DI(IO0)

W25Q64FVSSIQ_SO8

U727

vpro@U727

vpro@

/CS

DO/IO1

/WP/IO2

GND

W25Q32FVSSIQ_SO8

/HOLD(IO3)

/HOLD/IO3

DI/IO0

VCC

SPI_IO3_ROM

SPI_CLK_ROMSPI_IO2_ROM

CLK

SPI_SI_ROM

VCC

SPI_IO3_VROM

SPI_CLK_VROM

CLK

SPI_SI_VROM

+3V_ROM

CH6

CH6 .1U_0402_16V7K~D

.1U_0402_16V7K~D

vpro@

CH7

CH7 .1U_0402_16V7K~D

.1U_0402_16V7K~D

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P08-MCP(4/10) LPC,SPI,SMBUS,CL

LA-B441P

850Sunday, October 05, 2014

1.0

RTCX1 RTCX2

1. Total Length : 1000 mils

2. Space > 15 mils

3. Resistor Value (±5%) : 10M

RH2

RH2 10M_0402_5%

10M_0402_5%

D D

C C

1 2

YH1

32.768KHZ_X1A000141000300

1 2

Max Crystal ESR = 50k Ohm.

CH2

CH2 15P_0402_50V8J~D

15P_0402_50V8J~D

HDA_SDIN/HDA_SDO/HDA_SYNC/HDA_BCLK/HDA_RST#

1. BO < 500 mils

2. 1000 mils < M1 < 14000 mils.

3. Trace Length Matching (HDA_SDIO,HDA_BCLK,HDA_SDOUT)

4. Resistor Value : 33 ohm

I2S_RST_ AUDIO#[24] I2S_BITCL K_AUDIO[24] I2S_SDO UT_AUDIO[24] I2S_SYNC _AUDIO[24]

PCH_RTCX1

PCH_RTCX2

CH3

CH3 15P_0402_50V8J~D

15P_0402_50V8J~D

RP15

1 8 2 7 3 6 4 5

33_8P4R_5%

B0M1

I2S_RST# I2S_BIT_C LK I2S_SDO UT I2S_SYNC

RF Reserved.

I2S_BIT_C LK

EMI@

CH1242

CH1242 15P_0402_50V8J

15P_0402_50V8J

B B

+3VS_AUDIO

RH42

RH42 1K_0402_5%~D

1K_0402_5%~D

I2S_SDO UT

+RTCVCC

RH31

RH31 330K_0402_5%~D

330K_0402_5%~D

A A

PCH_INTVRMEN

RH34

RH34 330K_0402_5%~D

330K_0402_5%~D

I2S_SDO UT

EMI@

MC31

MC31 10P_0402_50V8J~D

10P_0402_50V8J~D

+1.05V_M

Functional Strap Definitions

Flash Descriptor Security Override

HDA_SDO/ I2S0_TXD

INTRUDER#

1. Critical Low Speed Signal

2. Space > 15 mils

3. Frequency to Avoid 32K

4. All critical signals must stay away from potential glitch or noise sources on the platform.

0 = Enable security measures defined in the Flash Descriptor. 1 = Disable Flash Descriptor Security (override). This strap should only be asserted high using external pull-up in manufacturing/debug environments ONLY.

Functional Strap Definitions

Integrated VRM

INTVRMEN

0 = DCPSUS1, DCPSUS2, DCPSUS3 and DCPSUS4 are powered from an external power source (should be connected to an external VRM). 1 = Integrated VRMs enabled. DCPSUS1, DCPSUS2 and DCPSUS3 can be left as No Connect.

INTRUDER#

1. Critical Low Speed Signal

2. Space > 15 mils

3. Frequency to Avoid 32K

4. All critical signals must stay away from potential glitch or noise sources on the platform.

+RTCVCC

RH11

RH11 1M_0402_5%~D

1M_0402_5%~D

SM_INTRUDER#

PCH JTAG

The Pull Up/Pull down terminations (R4,R3d,R5) should be placed to within 200ps of the respective Broadwell pin.

1 2

RH40 51_0402_5%RH40 51_0402_5%

R3d

1 2

RH445 51_0402_5%RH445 51_0402_5%

1 2

RH39 51_0402_5%RH39 51_0402_5%

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS

ME Reset

SRTCRST#

1. Total Length : 8000 mils

2. Space > 15 mils

3. Impedance Target 50 Ω ±15% for Microstrip.

4. RC time delay between 18 ms - 25 ms must be met.

5. There must not be a jumper for SRTCRST# pin.

+RTCVCC +RTCVCC

RH23

RH23 20K_0402_5%~D

20K_0402_5%~D

PCH_SRTCRST# PCH_RTCRST#

CH5

CH5 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

UCPU1E

PCH_RTCX1 PCH_RTCX2 SM_INTRUDER# PCH_INTVRMEN PCH_SRTCRST#

PCH_JTAG_JTAGX PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TCK PCH_JTAG_TDI

Issued Date

PCH_RTCRST#

I2S_BIT_C LK I2S_SYNC I2S_RST#

I2S_SDO UT

PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_JTAG_JTAGX

PCH_RTCRST#[21]

I2S_SDIN 0[24]

I2S_SDO UT[21]

PCH_JTAG_TRST#[20] PCH_JTAG_TCK[20] PCH_JTAG_TDI[20] PCH_JTAG_TDO[20] PCH_JTAG_TMS[20]

PCH_JTAG_JTAGX[20]

TP should be placed to with 250ps (1380 mils) of the respetive Haswell ULT pins, and the distance between TP and termination (if any) must be within 200ps (1100 mils).

T273@T27 3@ T275@T27 5@ T276@T27 6@ T277@T27 7@ T278@T27 8@

Security Classifi cation

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

AW5

RTCX1

AY5

RTCX2

AU6

INTR UDER

AV7

INTV RMEN

AV6

SRTCRST

AU7

RTCRST

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST/I2S_MCLK

AY10

HDA_SDI0/I2S0_RXD

AU12

HDA_SDI1/I2S1_RXD

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN/I2S1_TXD

AV10

HDA_DOCK_RST/I2S1_SFRM

AY8

I2S1 _SCLK

AU62

PCH_TRST

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD

AC4

RSVD

AE63

JTAGX

AV2

RSVD

GPIO Signals

SATA0GP,SATA1GP,SATA2GP,SATA3GP

1. Needs a weak pull-up:10 KΩ ±10% pull-up to V3.3.

2. Unused SATA[3:0]GP pins must be terminated to either

3.3V rail or GND using 8.2–10 KΩ on the motherboard. Either pull-up or pull-down is acceptable.

2013/07/04 2013/10/28

RTC Reset

CLRP1

CLRP1 SHORT PADS

SHORT PADS

RTCRST#

1. Total Length : 8000 mils

2. Space > 15 mils

3. Impedance Target 50 Ω ±15% for Microstrip.

4. RC time delay between 18 ms - 25 ms must be met.

MPCIE_RS T#

HDD_DET# PCH_SATALED# SATA2_PCIE6_L1 mCARD_PCIE#_SATA_R

Compal Secret Data

RH25

RH25 20K_0402_5%~D

20K_0402_5%~D

CH4

CH4 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

BDW_ULT_DDR3L

RTC

AUDIO SATA

JTAG

5 OF 19

1 2

RH393 10K_0402_5%~DRH393 10K_0402_5%~D

1 2

RH466 10K_0402_5%~DRH466 10K_0402_5%~D RH35 10K_0402_5%~DRH35 10K_0402_5%~D RH467 10K_0402_5%~D@RH467 10K_0402_5%~D@ RH392 10K_0402_5%~DRH392 10K_0402_5%~D RH395 10K_0402_5%~D@RH395 10K_0402_5%~D@

Deciphered Date

1 2

12 12

+3VS

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3 SATA_TN0/PETN6_L3

SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2 SATA_TN1/PETN6_L2

SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1 SATA_TN2/PETN6_L1

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

SATA_IREF

RSVD RSVD

SATA_RCOMP

SATALED

mCARD_PCIE#_SATA_R

SATA2_PCIE6_L1

Title

Size Document Number Rev

Date: Sheet of

1.When SATA and PCIe are muxed, always route according to SATA design guidelines.

2. Breakout < 600 mils

3. Zdiff : 85 ohm

4. Isolation to Other Signal Groups: Breakout : 8 mils/ Main routing : 20 mils in MS, 15 mils in SL,DSL

5. Max Length : 2 via Max 8", 3 vias Max 7"

6. Within Layer Max Mismatch : 15 mils.

7. Total Length Max Mismatch : 10 mils.

8. AC capacitors to be placed as close as possible to the connector. Maximum distance from AC capacitors to connector is 500 mils.

9. Minimum breakout pair-to-pair spacing of 3.5 mils is allowed for a maximum length of 20 mils within the 600 mils breakout.

10. Design constraint: breakout routing should be non-interleaved to mitigate concerns on near-end crosstalk.

J5 H5 B15 A15

J8 H8 A17 B17

J6 H6 B14 C15

F5 E5 C17 D17

MPCIE_RS T#

HDD_DET#

SATA2_PCIE6_L1

AC1

mCARD_PCIE#_SATA_R

A12 L11 K10 C12

SATA_RCOMP

PCH_SATALED#

SATA_RCOMP, SATA_IREF

1. Break-out : 4 mils

2. 12-15 mil trace with <0.2 Ω.

3. Length total <= 500 mils.

4. Requires 12 mils isolation from all High Speed I/O and clocks. SATA_RCOMP

1. Tied up to a clean 1.05V source (VCCASATA3PLL) with no capacitor on the net.

2. 3 KΩ ±1% precision pull-up resistor SATA_IREF

1. Pull-up direct to 1.05V (VCCASATA3PLL).

R1020

R1020 0_0402_5%~D

0_0402_5%~D

1 2

R1021

R1021 0_0402_5%~D

0_0402_5%~D

1 2

Compal Electronics, Inc.

P09-MCP(4/10) RTC,AUDIO,SATA

LA-B444P

SATA_RN2/PERN6_L1 [29] SATA_RP2/PERP6_L1 [29] SATA_TN2/PETN6_L1 [29] SATA_TP2/PETP6_L1 [29]

SATA_RN3/PERN6_L0 [29] SATA_RP3/PERP6_L0 [29] SATA_TN3/PETN6_L0 [29] SATA_TP3/PETP6_L0 [29]

MPCIE_RS T# [ 28]

RH43

RH43 3K_0402_1%~D

3K_0402_1%~D

1 2

mCARD_PCIE#_SATA [29]

950Saturday, October 04, 2014

+V1.05S_ASATA3PLL

1.0

UCPU1F@

CLK_PCIE_MMI#[23] CLK_PCIE_MMI[23]

D D

C C

MMICLK_RE Q#[23]

USB1_PWR_EN[30]

CLK_PCIE_WLAN#[28] CLK_PCIE_WLAN[28]

WLANCLK_REQ#[28]

CLK_PCIE_mSATA#[29] CLK_PCIE_mSATA[29]

mSATACLK_REQ#[29]

1. Breakout Routing Length Max : 500 mils.

2. Breakin Routing Length Max : 1500 mils

3. Routing Min and Max Length : 2"~9"

4. Differential Pair Length Matching. <25 mils for PCIe, <20 mils for ITP

6. Max Vias : 4

5. Stitching vias should be placed with this spacing: a).30-mils pitch between differential clock via and closest stitching GND-via. b). Every differential clock via must have at least one GND stitching via with a maximum spacing of 30 mils (0.762 mm).

6. Placement of additional stitching vias, where possible, is recommended.

MMICLK_RE Q#

USB1_PWR_EN

LANCLK_REQ#

WLANCLK_REQ#

PEG_WIGIGCLK_REQ#

mSATACLK_REQ#

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

PCIECLKRQ0/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

PCIECLKRQ1/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

PCIECLKRQ3/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

PCIECLKRQ4/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

PCIECLKRQ5/GPIO23

CardReader

BDW_ULT_DDR3L

CLOCK

SIGNALS

WiFi/BT

SSD

6 OF 19

A25 B25

K21 M21 C26

C35 C34 AK8 AL8

AN15 AP15

B35 A35

XTAL24_IN XTAL24_OU T

XCLK_BIASREF <100 MILS

XCLK_BIAS REF

TESTLOW 1 TESTLOW 2 TESTLOW 3 TESTLOW 4

CLKOUT_LPC0 CLKOUT_LPC1

TESTLOW 1 TESTLOW 2 TESTLOW 3 TESTLOW 4

XTAL24_IN

XTAL24_OUT

RSVD RSVD

DIFFCLK_BIASREF

TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8

CLKOUT_LPC_0 CLKOUT_LPC_1

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

1 2

RH113 3K_0402_1%~DRH113 3K_0402_1%~D

1 2

RH360 22_0402_5%~DRH360 22_0402_5%~D

1 2

RH428 22_0402_5%~DRH428 22_0402_5%~D

RH36 10K_0402_5%~DRH36 10K_0402_5%~D RH41 10K_0402_5%~DRH41 10K_0402_5%~D RH44 10K_0402_5%~DRH44 10K_0402_5%~D RH45 10K_0402_5%~DRH45 10K_0402_5%~D

12 12 12 12

+V1.05S_AXCK_LCPLL

CLK_PCI_MEC CLK_LPC_DEBUG

CLK_PCI_MEC [36] CLK_LPC_DEBUG [36]

XTAL24_IN

XTAL24_OU T

RH117 1M_0402_5%~DRH117 1M_0402_5%~D

24MHZ_12PF_7V24000020

CH24

CH24 15P_0402_50V8J~D

15P_0402_50V8J~D

15P_0402_50V8J

1 2

YH2

123

CLK_LPC_DEBUG CLK_PCI_MEC

CH1243

@ CH1243

CH23

CH23 15P_0402_50V8J~D

15P_0402_50V8J~D

CH1244

@CH1244

15P_0402_50V8J

RF Reserved.

+3VS

1 2

RH100 10K_0402_5%~DRH100 10K_0402_5%~D

1 2

RH95 10K_0402_5%~DRH95 10K_0402_5%~D

1 2

RH91 10K_0402_5%~DRH91 10K_0402_5%~D

1 2

RH103 10K_0402_5%~DRH103 10K_0402_5%~D

1 2

RH107 10K_0402_5%~DRH107 10K_0402_5%~D

1 2

RH110 10K_0402_5%~DRH110 10K_0402_5%~D

MMICLK_RE Q# USB1_PWR_EN LANCLK_REQ# WLANCLK_REQ# PEG_WIGIGCLK_REQ# mSATACLK_REQ#

B B

A A

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/07/04 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P10-MCP(5/10) CLOCKS

LA-B444P

1.0

10 50Saturday, October 04, 2014

1.0

Deep S3 support, connect to EC

SIO_PWRBTN#

T281@T281@

D D

NON-Deep S3 Support

Deep S3 support, connect to DSW power rail

+3V_PCH_DSW

RP20

SYS_RESET#

EC_WAKE# PCH_BATLOW#

AC_PRESENT

PCH_RSMRST#

RESET_OUT#_R

C C

TLS Confidentiality

Low - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High - Intel ME Crypto Transport Layer Security (TLS)

cipher suite with confidentiality

+3V_PCH

RH270 1K_0402_5%~DRH270 1K_0402_5%~D

+3V_PCH

RH3538 10K_0402_5%~DRH3538 10K_0402_5%~D

RH3536 10K_0402_5%~DRH3536 10K_0402_5%~D

RH382 100K_0402_5%~DRH382 100K_0402_5%~D

RH294 10K_0402_5%~D@ RH294 10K_0402_5%~D@

RH3537 10K_0402_5%~DRH3537 10K_0402_5%~D

RH3533 10K_0402_5%~DRH3533 10K_0402_5%~D

RH3535 10K_0402_5%~DRH3535 10K_0402_5%~D

B B

RH3541 10K_0402_5%~DRH3541 10K_0402_5%~D

RH3546 10K_0402_5%~DRH3546 10K_0402_5%~D

RH465 1M_0402_5%~DRH465 1M_0402_5%~D

RH400 100K_0402_5%~DRH400 100K_0402_5%~D

+3VS

RH3534 10K_0402_5%~DRH3534 10K_0402_5%~D

RH3543 10K_0402_5%~DRH3543 10K_0402_5%~D

RH383 100K_0402_5%~DRH383 100K_0402_5%~D

RH3540 10K_0402_5%~D@RH3540 10K_0402_5%~D@

RH3539 10K_0402_5%~DRH3539 10K_0402_5%~D

RH457 49.9K_0402_1%~DRH457 49.9K_0402_1%~D

RH458 49.9K_0402_1%~DRH458 49.9K_0402_1%~D

RH459 49.9K_0402_1%~DRH459 49.9K_0402_1%~D

RH460 49.9K_0402_1%~DRH460 49.9K_0402_1%~D

RH3548 10K_0402_5%~DRH3548 10K_0402_5%~D

A A

RH3530 10K_0402_5%~DRH3530 10K_0402_5%~D

RH3531 10K_0402_5%~DRH3531 10K_0402_5%~D

+3VS

1 8 2 7 3 6 4 5

10K_8P4R_5%

RH12 10K_0402_5%~DRH12 10K_0402_5%~D

RH159 10K_0402_5%~DRH159 10K_0402_5%~D

RH394 10K_0402_5%~DRH394 10K_0402_5%~D

1 2

RH37 1K_0402_5%~D@ RH37 1K_0402_5%~D@

LOW=Default

HIGH=No Reboot

+3VS

HOST_ALERT1_R_N

PCH_GPIO12

SIO_EXT_SMI#

UART_WAKE#

NFC_IRQ

SIO_EXT_WAKE#

MEDIACARD_IRQ#

MEDIACARD_RST#

CAM_CBL_DET#

PCH_GPIO58

NFC_DET#

USB0_PWR_EN

TPM_PIRQ#

PCH_GPIO49

SIO_EXT_SCI#

PCH_GPIO38

PCH_GPIO16

UART1_RXD

UART1_TXD

UART1_RTS#

UART1_CTS#

TOUCH_PANEL_INTR#

PCH_GPIO48

PCH_GPIO87

SPKR

SUSACK#[36] PM_SYS_RESET#[20,21] SYS_PWROK[20,36] RESET_OUT#[35,36]

PCH_RSMRST#[36] ME_SUS_PWR_ACK[36] SIO_PWRBTN#[20,36] AC_PRESENT[36]

PM_SLP_S0#[21,45] SIO_SLP_WLAN#[36]

PCH_PLTRST#_EC[20,23,27,28,36]

PCH_RSMRST# PCH_RSMRST#_R

A00_1004: Change to short pad.

RH171

RH171 100K_0402_5%~D

100K_0402_5%~D

Audio CODEC

+3V_PCH

BC@

RH3542 10K_0402_5%~D

CSMB@

RH3549 10K_0402_5%~D

Deep S3 (Pop RH430)

+3VS

RH168 0_0402_5%~D@RH168 0_0402_5%~D@

1 2

UH5

VCC

IN1

IN2

GND

12 12 12 12

12 12

MC74VHC1G08DFT2G_SC70-5

RH430 0_0402_1%@RH430 0_0402_1%@ RH450 0_0402_1%@RH450 0_0402_1%@ RH455 0_0402_1%@RH455 0_0402_1%@ RH452 0_0402_1%@RH452 0_0402_1%@

RH133 0_0402_1%@RH133 0_0402_1%@ RH297 0_0402_1%@RH297 0_0402_1%@

RH137 0_0402_1%@RH137 0_0402_1%@

RH463 0_0402_1%@RH463 0_0402_1%@

OUT

closed MCP 2000 mils

T279@T279@

T282@T282@

T286@T286@ T287@T287@

PCH_AUDIO_PWR[32]

SIO_EXT_WAKE#[36]

TPM_PIRQ#[27]

BT_CS_NOTICE[28]

EC_WAKE#[36]

PCH_NFC_RST#[29]

NFC_IRQ[29]

MEDIACARD_PWREN[32]

NFC_DET#[29]

CAM_CBL_DET#[22]

MEDIACARD_IRQ#[23]

TOUCH_PANEL_INTR#[22]

MPHYP_PWR_EN[33]

KB_DET#[34]

T288@T288@

EN_CAM[32]

SIO_EXT_SMI#[36]

UART_WAKE#[28]

mSATA_DEVSLP[29]

SIO_EXT_SCI#[36] SPKR[24]

I2C0_SDA_DSP[24] I2C0_SCK_DSP[24]

SUSACK#_R SYS_RESET#

RESET_OUT#_R PM_APWROK_R PCH_PLTRST#

SUS_PWR_DN SIO_PWRBTN# AC_PRESENT_RAC_PRESENT PCH_BATLOW# SLP_S0#

RH183

RH183 10K_0402_5%~D

10K_0402_5%~D

1 2

PCH_AUDIO_PWR

KB_DET#

MEM_CONFIG0 MEM_CONFIG1

PCH_AUDIO_PWR SIO_EXT_WAKE# PCH_GPIO12 HOST_ALERT1_R_N PCH_GPIO16 TPM_PIRQ#

EC_WAKE#

NFC_IRQ

MEDIACARD_RST#

PCH_GPIO58 NFC_DET# CAM_CBL_DET# MEDIACARD_IRQ# PCH_GPIO48 PCH_GPIO49 TOUCH_PANEL_INTR# MPHYP_PWR_EN KB_DET# PCH_GPIO14 EN_CAM SIO_EXT_SMI# CONFIG_BID

UART_WAKE# USB0_PWR_EN

MEM_CONFIG0 PCH_GPIO38 SIO_EXT_SCI# SPKR

1 2

RA7 0_0402_1%@RA7 0_0402_1%@

1 2

RA8 0_0402_1%@RA8 0_0402_1%@

A00_1004: Change to short pad.

CONFIG_BID

UCPU1H@

AK2

SUSACK

AC3

SYS_RESET

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST

AW6

RSMRST

AV4

SUSWARN/SUSPW RDNACK/GPIO30

AL7

PWRBTN

AJ8

ACPRESENT/GPIO31

AN4

BATLOW/ GPIO72

AF3

SLP_S0

AM5

SLP_WLAN/GPIO2 9

PCH_PLTRST#

UCPU1J@

BMBUSY/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

GPIO15

GPIO16

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

GPIO48

GPIO49

GPIO50

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

DEVSLP0/GPIO33

SDIO_POWER_EN/ GPIO70

DEVSLP1/GPIO38

DEVSLP2/GPIO39

SPKR/GPIO81

BDW_ULT_DDR3L

SYSTEM POWER MANAGEMENT

PCH Strap PIN

DSWODVREN

RH147 330K_0402_5%~DRH147 330K_0402_5%~D

DSWODVREN - On Die DSW VR Enable

H：Enable

L：Disable

3.3V_mSATA_EN

BDW_ULT_DDR3L

GPIO

1 2

RH424 5.1K_0402_1%RH424 5.1K_0402_1%

1 2

RH425 5.1K_0402_1%RH425 5.1K_0402_1%

I2C0_SDA I2C0_SCK

8 OF 19

10 OF 19

RH431 0_0402_5%~D@RH431 0_0402_5%~D@

RH423 100K_0402_5%~D@RH423 100K_0402_5%~D@

CPU/

CPU/ MISC

MISC

SERIAL IO

+3VS

DSWVRMEN

DPWROK

WAKE

CLKRUN/GPIO32

SUS_STAT/GPIO61

SUSCLK/GPIO62

SLP_S5/GPIO63

SLP_S4 SLP_S3

SLP_A SLP_SUS SLP_LAN

+RTCVCC

+3VS

U682

S IC TC7SZ14FU SSOP 5P

1 2

THRMTRIP

RCIN/GPIO82

SERIRQ

PCH_OPI_RCOMP

RSVD RSVD

GSPI0_CS/GPIO83

GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86

GSPI1_CS/GPIO87

GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90 UART0_RXD/GPIO91 UART0_TXD/GPIO92

UART0_RTS/GPIO93 UART0_CTS/GPIO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1

UART1_RST/GPIO2 UART1_CTS/GPIO3

I2C0_SDA/ GPIO4

I2C0_SCL /GPIO5

I2C1_SDA/ GPIO6

I2C1_SCL /GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69

RF Reserved.

SDIO_CLK

AW7

DSWODVREN

AV5

PCH_DPWROK_R

AJ5

PCH_PCIE_WAKE#

A00_1004: Change to short pad.

CLKRUN#

AG4

SUS_STAT#/LPCPD#

AE6

SUSCLK

AP5

AJ6 AT4 AL5 AP4 AJ7

D60 V4 T4 AW15 AF20 AB21

R6 L6 N6 L8 R7 L5 N7 K2 J1 K3 J2 G1 K4 G2 J3 J4 F2 F3 G4 F1 E3 F4 D3 E4 C3 E2

RH132 0_0402_1%@RH132 0_0402_1%@

SIO_SLP_S3# SIO_SLP_A#

PM_APWROK[36]

1.05V_M_PWRGD[45]

H_THERMTRIP# SIO_RCIN# IRQ_SERIRQ PCH_OPIRCOMP

Width = 15 mil, Spacing = 12 mil Close PCH within 500 mil

NGFF_PWREN PCH_GPIO84

3.3V_mSATA_EN BBS_BIT PCH_GPIO87 GPIO88_SLP_S0#

PCH_GPIO90 DDR_CHA_EN DDR_CHB_EN MEM_CONFIG1 MEM_CONFIG2 UART1_RXD UART1_TXD UART1_RTS# UART1_CTS# I2C0_SDA I2C0_SCK I2C1_SDA I2C1_SCK SDIO_CLK

SDIO_D0

CH1246

15P_0402_50V8J

SSD_PWREN [32]

RC156 49.9_0402_1%~DRC156 49.9_0402_1%~D

PCH_PCIE_WAKE# [ 36]

H_THERMTRIP# [36]

NGFF_PWREN [32]

GPIO88_SLP_S0# [36]

3.3V_TS_EN [32]

UART1_RXD [28] UART1_TXD [28] UART1_RTS# [28]

UART1_CTS# [28]

I2C1_SDA [35]

I2C1_SCK [35] SDIO_CLK [28]

SDIO_CMD [28]

SDIO_D0 [28]

SDIO_D1 [28]

SDIO_D2 [28]

SDIO_D3 [28]

SIO_SLP_A#

RH134

RH135

1 2

T284@T284 @

CLKRUN# [36]

SUSCLK_R [28,29] SIO_SLP_S5# [21,36]

SIO_SLP_S4# [21,36] SIO_SLP_S3# [21,36,44,46] SIO_SLP_A# [21,36] SIO_SLP_SUS# [ 36]

0_0402_5%~D

@RH135

I2C is daisy chain routing with pull up on the last device

DDR Memory Configuratino Type Strap pin

+3VS

GPIO Pin

PCH_GPIO70

PCH_GPIO93

PCH_GPIO94

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

Deep S3 Support

+3VLP

UC6

TC7SH08FU_SSOP5~D

SIO_RCIN# [36] IRQ_SERIRQ [36]

RH303 10K_0402_5%~D@ RH303 10K_0402_5%~D@

RH271 10K_0402_5%~D@ RH271 10K_0402_5%~D@

RH180 10K_0402_5%~D@ RH180 10K_0402_5%~D@

Pin Name

MEM_CONFIG0

MEM_CONFIG1

MEM_CONFIG2

SUS_STAT#/LPCPD#

SUS_PWR_DN

KB_DET#

PCH_PCIE_WAKE#

PCH_DPWROK_R

Deep S3 Support

PCH_DPWROK_R

PM_APWROK_R

CLKRUN#

H_THERMTRIP#

PCH_GPIO90

PCH_GPIO84

GPIO88_SLP_S0#

NGFF_PWREN

MPHYP_PWR_EN

I2C1_SDA

I2C1_SCK

IRQ_SERIRQ

SIO_RCIN#

DDR_CHA_EN

DDR_CHB_EN

DDR_CHA_EN

DDR_CHB_EN

GPIO86 have internal pull down

GPIO66 have internal pull down

Micron 4G SA00005TH0L

Date: Sheet of

1 2

RH197 10K_0402_5%~D@RH197 10K_0402_5%~D@

1 2

RH154 1M_0402_5%~DRH154 1M_0402_5%~D

1 2

RH302 100K_0402_5%~DRH302 100K_0402_5%~D

1 2

RH146 1K_0402_5%~DRH146 1K_0402_5%~D

1 2

RH401 100K_0402_5%~D@ RH401 100K_0402_5%~D@

RH309 0_0402_1%@RH309 0_0402_1%@

+3V_PCH

+3V_PCH_DSW

PCH_DPWROK [36]

A00_1004: Change to short pad.

+3VS

1 2

Boot BIOS LocationPCH_GPIO86

SPI

1 2

+1.05VS_VCCST

+3VS

+VS_LPSS_SDIO

RH248 8.2K_0402_5%~DRH248 8.2K_0402_5%~D

SUSCLK

CH102 10P_0402_50V8J~D

EMI@

Reserve for RF please close to UH1

EMI@

RC149 1K_0402_5%~DRC149 1K_0402_5%~D

RH200 10K_0402_5%~DRH200 10K_0402_5%~D

RH199 10K_0402_5%~DRH199 10K_0402_5%~D

RH198 10K_0402_5%~D@RH198 10K_0402_5%~D@

R1396 100K_0402_5%~DR1396 100K_0402_5%~D

R1185 100K_0402_5%~DR1185 100K_0402_5%~D

RH3 10K_0402_5%~DRH3 10K_0402_5%~D

RH5 10K_0402_5%~DRH5 10K_0402_5%~D

RH29 10K_0402_5%~DRH29 10K_0402_5%~D

RH196 10K_0402_5%~DRH196 10K_0402_5%~D

RH440 100K_0402_5%~DRH440 100K_0402_5%~D

RH441 100K_0402_5%~DRH441 100K_0402_5%~D

RH442 SHORT PADS@ RH442 SHORT PADS@

RH443 SHORT PADS@ RH443 SHORT PADS@

Boot BIOS Strap

SDIO_D0

RH434 1K_0402_5%~D@ RH434 1K_0402_5%~D@

RH435 1K_0402_5%~D@ RH435 1K_0402_5%~D@

A16 SWAP OVERRIDE STRAP

LOW = A16 SWAP OVERRIDE

STP_A16OVR

TBD

Title

Size Document Number Rev

HIGH = NO OVERRIDE

Hynix 8G SA00006Q90L

Elpida 8G SA00006O90L

TBD

11 50Sunday, October 05, 2014

MEM_CONFIG0

MEM_CONFIG2

MEM_CONFIG1

Hynix 4G SA00006JF0L

RH316 10K_0402_5%~D@ RH316 10K_0402_5%~D@

RH314 10K_0402_5%~D@ RH314 10K_0402_5%~D@

RH315 10K_0402_5%~D@ RH315 10K_0402_5%~D@

Compal Electronics, Inc.

P11-MCP(7/10) PM,GPIO,LPIO,MISC

LA-B441P

1.0

D D

PCIE_PRX_WLANTX_N4[28]

NGFF

CardReader

C C

PCIE_PRX_WLANTX_P4[28]

PCIE_PTX_WLANRX_N4[28] PCIE_PTX_WLANRX_P4[28]

PCIE_PRX_CARDTX_N1[23] PCIE_PRX_CARDTX_P1[23]

PCIE_PTX_CARDRX_N1[23] PCIE_PTX_CARDRX_P1[23]

1 2

CH11 0.1U_0402_10V7K~DCH11 0.1U_0402_10V7K~D

1 2

CH16 0.1U_0402_10V7K~DCH16 0.1U_0402_10V7K~D

1 2

CH25 0.1U_0402_10V7K~DCH25 0.1U_0402_10V7K~D

1 2

CH26 0.1U_0402_10V7K~DCH26 0.1U_0402_10V7K~D

+V1.05S_AUSB3PLL

1 2

RH338 3K_0402_1%~DRH338 3K_0402_1%~D

Width = 15 mil, Spacing = 15 mil Close PCH within 500 mil

PCIE_PTX_WLANRX_N4_C PCIE_PTX_WLANRX_P4_C

PCIE_PTX_C_CARDRX_N1 PCIE_PTX_C_CARDRX_P1

PCIE_RCOMP

F10 E10

C23 C22

F8 E8

B23 A23

H10

G10

B21 C21

E6 F6

B22 A21

G11

F11

C29 B30

F13

G13

B29 A29

G17

F17

C30 C31

F15

G15

B31 A31

E15 E13 A27 B27

UCPU1K@

PERN5_L0 PERP5_L0

PETN5_L0 PETP5_L0

PERN5_L1 PERP5_L1

PETN5_L1 PETP5_L1

PERN5_L2 PERP5_L2

PETN5_L2 PETP5_L2

PERN5_L3 PERP5_L3

PETN5_L3 PETP5_L3

PERN3 PERP3

PETN3 PETP3

PERN4 PERP4

PETN4 PETP4

PERN1/USB3RN3 PERP1/USB3RP3

PETN1/USB3TN3 PETP1/USB3TP3

PERN2/USB3RN4 PERP2/USB3RP4

PETN2/USB3TN4 PETP2/USB3TP4

RSVD RSVD PCIE_RCOMP PCIE_IREF

BDW_ULT_DDR3L

PCIE USB

11 OF 19

USB2N0 USB2P0

USB2N1 USB2P1

USB2N2 USB2P2

USB2N3 USB2P3

USB2N4 USB2P4

USB2N5 USB2P5

USB2N6 USB2P6

USB2N7 USB2P7

USB3RN1 USB3RP1

USB3TN1 USB3TP1

USB3RN2 USB3RP2

USB3TN2 USB3TP2

USBRBIAS

RSVD RSVD

OC0/GPIO40 OC1/GPIO41 OC2/GPIO42 OC3/GPIO43

AN8 AM8

AR7 AT7

AR8 AP8

AR10 AT10

AM15 AL15

AM13 AN13

AP11 AN11

AR13 AP13

G20 H20

C33 B34

E18 F18

B33 A33

AJ10

USBRBIAS

AJ11 AN10 AM10

AL3

USB_OC0#

AT1

USB_OC1#

AH2

USB_OC2#

AV3

USB_OC3#

closed MCP 2000 mils

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

USB20_N0 [23] USB20_P0 [23]

USB20_N1 [30] USB20_P1 [30]

USB20_N2 [28] USB20_P2 [28]

USB20_N3 [22] USB20_P3 [22]

USB20_N4 [22] USB20_P4 [22]

USB3RN0 [23] USB3RP0 [23]

USB3TN0 [23] USB3TP0 [23]

USB3RN1 [30] USB3RP1 [30]

USB3TN1 [30] USB3TP1 [30]

Within 450 mils

1 2

RH163

22.6_0402_1%

USB_OC0# [23] USB_OC1# [30]

USB2.0 IO/B Side

USB2.0 M/B Side

NGFF (WLAN)

Touch Panel

Camera

USB3.0 IO/B Side

USB3.0 M/B Side

Net USB_BIAS route impedacnes should be 50-ohm and length less than 450-mil spacing is 15-mil.

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

T289@T289@ T290@T290@ T291@T291@ T292@T292@

RP21

1 8 2 7 3 6 4 5

10K_8P4R_5%

+3V_PCH

BDW_ULT_DDR3L

UCPU1Q@

DC_TEST_AY2_AW2 DC_TEST_AY3_AW3

DC_TEST_AY61_AW61 DC_TEST_AY62_AW62

B B

A A

DC_TEST_A3_B3 DC_TEST_A61_B61 DC_TEST_B62_B63

DC_TEST_C1_C2

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

DAISY_CHAIN_NCTF_B2

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

DAISY_CHAIN_NCTF_C1

DAISY_CHAIN_NCTF_C2

UCPU1R@

AT2

RSVD

AU44

RSVD

AV44

RSVD

D15

RSVD

F22

RSVD

H22

RSVD

J21

RSVD

BDW_ULT_DDR3L

17 OF 19

BDW_ULT_DDR3L

18 OF 19

DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

DC_TEST_A3_B3

A60 A61

DC_TEST_A61_B61

A62 AV1 AW1 AW2

DC_TEST_AY2_AW2

AW3

DC_TEST_AY3_AW3

AW61

DC_TEST_AY61_AW61

AW62

DC_TEST_AY62_AW62

AW63

N23 R23 T23 U10

AL1 AM11 AP7 AU10 AU15 AW14 AY14

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P12-MCP(8/10) PCIE,USB

LA-B441P

12 50Saturday, October 04, 2014

1.0

+1.35V_DDR

10U_0603_6.3V6M~D

D D

2.2U_0402_6.3V6M~D

10U_0603_6.3V6M~D

CC160

CC161

2.2U_0402_6.3V6M~D

CC233

CC238

10U_0603_6.3V6M~D

CC162

2.2U_0402_6.3V6M~D

CC239

10U_0603_6.3V6M~D

CC164

CC163

CC234

CC165

VR_ON

close to ULT within 0.5"~1"

1 2

XDP_PWRGD[20]

+1.05VS_VCCST

C C

2.2UH_LQM2MPN2R2NG0L_30%

B B

+1.05VDX_MODPHY

R1240 0.005_1206_1%R1240 0.005_1206_1%

+1.05VS

1 2

2.2UH_LQM2MPN2R2NG0L_30%

100U_A1_6.3VM_R70M

+1.05VDX_MODPHY

1 2

2.2UH_LQM2MPN2R2NG0L_30%

A A

+1.05VS

RH355

1 2

0_0603_5%

R1180 1K_0402_5%~DR1180 1K_0402_5%~D

close to CPU

RC93 75_0402_5%RC93 75_0402_5%

R1371 130_0402_1%R1371 130_0402_1%

LH10

1 2

SIP

1 2

LH12

LH11

+V1.05S_AXCK_DCB_L

1 2

+3VS_AUDIO

CH85

CH85 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+V1.05S_APLLOPI

CH36

1U_0402_6.3V6K~D

2.2UH_LQM2MPN2R2NG0L_30%

100U_A1_6.3VM_R70M

C1312

22U_0805_6.3V6M

+V1.05VS_VCCHSIO

CH40

CH1213

+V1.05S_ASATA3PLL

C1314

22U_0805_6.3V6M

L61

1 2

1U_0402_6.3V6K~D

+V1.05S_AUSB3PLL+1.05VDX_MODPHY

C1313

C1315

CH62

VR_SVID_ALRT#

H_CPU_SVIDDAT

22U_0805_6.3V6M

1.05VS_VCCST_PG

EMI@

CH1247

15P_0402_50V8J

RF Reserved.

+1.05V_PCH

RH405

1 2

0_0603_5%~D

CH41

1U_0402_6.3V6K~D

22U_0603_6.3V6M~D

1U_0402_6.3V6K~D

CH1248

@ CH1248

15P_0402_50V8J

RF Reserved.

+V1.05S_AXCK_DCB

CH1229

1U_0402_6.3V6K~D

SIP

+1.05VS

RH340

RH340 0_0805_5%

0_0805_5%

1 2

CH1204

22U_0603_6.3V6M~D

1U_0402_6.3V6K~D

CH1239

CH1239 10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CSPSM@

+1.05V_PCH

CH1220

CH1234

1 2

0_0603_5%~D

+3V_PCH

+3VS

22U_0603_6.3V6M~D

+1.05VS

+V1.05S_AXCK_LCPLL

+1.05VS

1U_0402_6.3V6K~D

+1.05VS

RH356

1 2

0_0603_5%

A00_1004: Change to short pad.

+1.05VS_VCCST

RH4

RH4 10K_0402_5%

10K_0402_5%

+VCCIO_OUT

1U_0402_6.3V6K~D

RC2011.5K_0402_5% RC2011.5K_0402_5%

CH1241

0.1U_0402_10V7K~D

VR_SVID_ALRT#[47]

1.05VS_VCCST_PG[35]

H_VR_READY[47]

+1.05VS_VCCST

CH1205

H_VR_READY

VR_SVID_CLK[47] VR_SVID_DAT[47]

VCCSENSE[47]

VR_SVID_ALRT#

VR_ON[47]

H_VR_READY

H_CPU_SVIDCLK

EMI@

CC243

CC243 15P_0402_50V8J

15P_0402_50V8J

RF Reserved.

+1.05VS

+V1.05VS_VCCHSIO

+V1.05S_AUSB3PLL

+V1.05S_ASATA3PLL

CH39

+V1.05S_APLLOPI

CH1214

CH1214 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CSPSM@

RH408

CH1225

CH1235

+V1.05S_AXCK_LCPLL_L +V1.05S_AXCK_LCPLL

+V1.05A_DCPSUS3

+3VS_AUDIO

+V1.05A_DCPSUS2

CH1221

CH1221 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CSPSM@

+3V_PCH_DSW

+V1.05S_AXCK_DCB

+V1.05S_AXCK_LCPLL

L62

1 2

2.2UH_LQM2MPN2R2NG0L_30%

100U_A1_6.3VM_R70M

CH65

AA21

W21

AH14

AH13

AC9 AA9

AH10

K19 A20

R21 T21 K18 M20

AE20 AE21

1U_0402_6.3V6K~D

L10

M9 N8

P9 B18 B11

Y20

J13

V8 W9

J18

J17

V21

+1.35V_DDR

4.2A

+VCC_CORE

RC97 & RC98 close to PCH

1 2

RC97 100_0402_1%~DRC97 100_0402_1%~D

1 2

RC98 0_0402_1%@RC98 0_0402_1%@

+VCCIO_OUT +VCCIOA_OUT

1 2

RC94 43_0402_5%~DRC94 43_0402_5%~D

1 2

RC92 0_0402_1%@RC92 0_0402_1%@

1 2

RC96 0_0402_1%@RC96 0_0402_1%@

1 2

RC151 0_0402_1%@RC151 0_0402_1%@

1 2

RC152 0_0402_1%@RC152 0_0402_1%@

A00_1004: Change to short pad.

PWR_DEBUG#_XDP[20]

BDW_ULT_DDR3L

GPIO/LPC

LPT LP POWER

BDW_ULT_DDR3L

HSIO

OPI

USB3

HDA

VRM

UCPU1M@

VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL

RSVD VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3

VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD RSVD RSVD VCCSUS3_3 VCCSUS3_3

DCPSUS can be NC, if INTVRMEN pull up to enable Integrated VRM

+V1.05S_AXCK_LCPLL

CH1231

+1.05VS_VCCST

+VCC_CORE

THERMAL SENSOR

SUS OSCILLATOR

13 OF 19

VCCSENSE_R

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

1.05VS_VCCST_PG VR_ON_MCPVR_ON VRPG_MCP

RTC

SPI

CORE

SERIAL IO

USB2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

AH26

AJ31 AJ33

AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50

AC58

AB23

AD23 AA23 AE59

AD60 AD59 AA59 AE60 AC59 AG58

AC22 AE22 AE23

AB57 AD57 AG57

VCCSUS3_3

VCCRTC DCPRTC

VCCSPI

VCCASW VCCASW

VCC1_05 VCC1_05 VCC1_05 VCC1_05

VCC1_05 DCPSUSBYP DCPSUSBYP

VCCASW VCCASW

VCCASW DCPSUS1 DCPSUS1

VCCTS1_5

VCC3_3 VCC3_3

VCCSDIO

DCPSUS4

RSVD VCC1_05 VCC1_05

UCPU1L@

L59

RSVD

J58

RSVD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

F59

VCC

N58

RSVD RSVD

E63

VCC_SENSE RSVD

A59

VCCIO_OUT

E20

VCCIOA_OUT RSVD RSVD RSVD

L62

VIDALERT

N63

VIDSCLK

L63

VIDSOUT

B59

VCCST_PWR GD

F60

VR_EN

C59

VR_READY

D63

VSS

H59

PWR_DEBUG

P62

VSS

P60

RSVD_TP

P61

RSVD_TP

N59

RSVD_TP

N61

RSVD_TP

T59

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

U59

RSVD

V59

RSVD

VCCST VCCST VCCST

VCC VCC VCC

C24

VCC

C28

VCC

C32

VCC

AH11 AG10 AE7

CH1206 0.1U_0402_10V7KCH1206 0.1U_0402_10V7K

AG14 AG13

J11 H11 H15 AE8 AF22 AG19 AG20 AE9 AF9 AG8 AD10 AD8

J15 K14 K16

U8 T9

AB8

AC20 AG16 AG17

BDW_ULT_DDR3L

HSW ULT POWER

12 OF 19

+1.05V_M

+PCH_VCCDSW

CH1233

CH1233 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+RTCVCC

RH346

RH346 0_0402_1%

0_0402_1%

1 2

RH407

1 2

0_0603_5%~D

CH1219

CH1219 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CSPSM@

CH1226

0.1U_0402_10V7K

+1.05VS

Compal Secr et Data

CH47

0.1U_0402_10V7K~D

CH1218

1 2

1U_0402_6.3V6K~D

+1.05V_PCH

+3VS

+RTC_VCCSUS

Deciphered Date

+RTC_VCCSUS

1 2

+V1.05A_DCPSUS1

+1.5VS

+VS_LPSS_SDIO

+V1.05A_AOSCSUS

2013/07/04 2013/10/28

C36

VCC

C40

VCC

C44

VCC

C48

VCC

C52

VCC

C56

VCC

E23

VCC

E25

VCC

E27

VCC

E29

VCC

E31

VCC

E33

VCC

E35

VCC

E37

VCC

E39

VCC

E41

VCC

E43

VCC

E45

VCC

E47

VCC

E49

VCC

E51

VCC

E53

VCC

E55

VCC

E57

VCC

F24

VCC

F28

VCC

F32

VCC

F36

VCC

F40

VCC

F44

VCC

F48

VCC

F52

VCC

F56

VCC

G23

VCC

G25

VCC

G27

VCC

G29

VCC

G31

VCC

G33

VCC

G35

VCC

G37

VCC

G39

VCC

G41

VCC

G43

VCC

G45

VCC

G47

VCC

G49

VCC

G51

VCC

G53

VCC

G55

VCC

G57

VCC

H23

VCC

J23

VCC

K23

VCC

K57

VCC

L22

VCC

M23

VCC

M57

VCC

P57

VCC

U57

VCC

W57

VCC

+3.3V_M

CH1215

1U_0402_6.3V6K~D

CH1222

CH1222 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+VCC_CORE

closed to VCC1P05

1U_0402_6.3V6K~D

+1.05V_M

SIP

RH341

0_0603_5%

CH1207

CH1207 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+V1.05A_AOSCSUS

CH1232

CH1232 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CSPSM@

A00_1004: Change to short pad.

Deep S3 Support

1 2

RH348 @ 0_0603_5%RH348 @ 0_0603_5%

+3VALW +3V_PCH_DSW

CH1224

1U_0402_6.3V6K~D

CH1217

1 2

.47U_0402_10V6K

+1.05VS

+PCH_VCCDSW +3V_PCH_DSW

CH1216

10U_0603_6.3V6M~D

closed to VCCRTC

CH1223

CH1223 22U_0603_6.3V6M~D

22U_0603_6.3V6M~D

1U_0402_6.3V6K~D

CH84

0.1U_0402_10V7K~D

A00_1004: Change to short pad.

+3V_PCH

+VS_LPSS_SDIO

+1.05V_PCH

L63

1 2

2.2UH_LQM2MPN2R2NG0L_30%

CH61

100U_A1_6.3VM_R70M

CSPSM@

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P13-MCP(9/10) PWR,VCC

LA-B441P

CH83

RH354

1 2

0_0603_5%

RH350

1 2

0_0603_5%~D

CH1227

CH1227 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

0.1U_0402_10V7K~D

13 50Monday, October 06, 2014

CH82

+3VS

+1.8VS

+RTCVCC

1.0

Place a test point pad to within 250 ps of the ROC_TCK pin.and the maximum distance of test point pad to the termination must not be over 200 ps.

CFG3

T293@T293@

UCPU1S@

BDW_ULT_DDR3L

CFG3 CFG4

CFG_RCOMP

TD_IREF

UCPU1O@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AC60

CFG0

AC62

CFG1

AC63

CFG2

AA63

CFG3

AA60

CFG4

Y62

CFG5

Y61

CFG6

Y60

CFG7

V62

CFG8

V61

CFG9

V60

CFG10

U60

CFG11

T63

CFG12

T62

CFG13

T61

CFG14

T60

CFG15

AA62

CFG16

U63

CFG18

AA61

CFG17

U62

CFG19

V63

CFG_RCOMP

RSVD

J20

RSVD

H18

RSVD

B12

TD_IREF

BDW_ULT_DDR3L

15 OF 19

RESERVED

PROC_OPI_RCOMP

19 OF 19

AV59

VSS

AV8

VSS

AW16

VSS

AW24

VSS

AW33

VSS

AW35

VSS

AW37

VSS

AW4

VSS

AW40

VSS

AW42

VSS

AW44

VSS

AW47

VSS

AW50

VSS

AW51

VSS

AW59

VSS

AW60

VSS

AY11

VSS

AY16

VSS

AY18

VSS

AY22

VSS

AY24

VSS

AY26

VSS

AY30

VSS

AY33

VSS

AY4

VSS

AY51

VSS

AY53

VSS

AY57

VSS

AY59

VSS

AY6

VSS

B20

VSS

B24

VSS

B26

VSS

B28

VSS

B32

VSS

B36

VSS

B40

VSS

B44

VSS

B48

VSS

B52

VSS

B56

VSS

B60

VSS

C11

VSS

C14

VSS

C18

VSS

C20

VSS

C25

VSS

C27

VSS

C38

VSS

C39

VSS

C57

VSS

D12

VSS

D14

VSS

D18

VSS

D21

VSS

D23

VSS

D25

VSS

D26

VSS

D27

VSS

D29

VSS

D30

VSS

D31

VSS

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

CFG0[20] CFG1[20]

D D

CFG4

RC811K_0402_1%~D RC811K_0402_1%~D

eDP Strap

1 : Disabled; No Physical Display Port attached to Embedded Display Port

CFG4

0 : Enabled; An external Display

Port device is connected to the Embedded Display Port

TD_IREF

RC1558.2K_0402_1% RC1558.2K_0402_1%

CFG_RCOMP

RC15349.9_0402_1%~D RC15349.9_0402_1%~D

PROC_OPI_COMP

AA58 AB10 AB20 AB22

AC61 AD21

AD63 AE10

AE58

AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57

AF11 AF12 AF14 AF15 AF17 AF18

AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

RC15449.9_0402_1%~D RC15449.9_0402_1%~D

BDW_ULT_DDR3L

UCPU1N@

A11

VSS

A14

VSS

A18

VSS

A24

VSS

A28

VSS

A32

VSS

A36

VSS

A40

VSS

A44

VSS

A48

VSS

A52

VSS

A56

VSS

AA1

VSS VSS VSS VSS VSS

AB7

VSS VSS VSS

AD3

VSS VSS VSS

AE5

VSS VSS VSS VSS VSS VSS VSS VSS

AG1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

14 OF 19

AJ35

VSS

AJ39

VSS

AJ41

VSS

AJ43

VSS

AJ45

VSS

AJ47

VSS

AJ50

VSS

AJ52

VSS

AJ54

VSS

AJ56

VSS

AJ58

VSS

AJ60

VSS

AJ63

VSS

AK23

VSS

AK3

VSS

AK52

VSS

AL10

VSS

AL13

VSS

AL17

VSS

AL20

VSS

AL22

VSS

AL23

VSS

AL26

VSS

AL29

VSS

AL31

VSS

AL33

VSS

AL36

VSS

AL39

VSS

AL40

VSS

AL45

VSS

AL46

VSS

AL51

VSS

AL52

VSS

AL54

VSS

AL57

VSS

AL60

VSS

AL61

VSS

AM1

VSS

AM17

VSS

AM23

VSS

AM31

VSS

AM52

VSS

AN17

VSS

AN23

VSS

AN31

VSS

AN32

VSS

AN35

VSS

AN36

VSS

AN39

VSS

AN40

VSS

AN42

VSS

AN43

VSS

AN45

VSS

AN46

VSS

AN48

VSS

AN49

VSS

AN51

VSS

AN52

VSS

AN60

VSS

AN63

VSS

AN7

VSS

AP10

VSS

AP17

VSS

AP20

VSS

C C

B B

A A

Width = 15 mil, Spacing = 15 mil Close PCH within 500 mil

CFG2[20] CFG3[20] CFG4[20] CFG5[20] CFG6[20] CFG7[20] CFG8[20] CFG9[20] CFG10[20] CFG11[20] CFG12[20] CFG13[20] CFG14[20] CFG15[20]

CFG16[20] CFG18[20] CFG17[20] CFG19[20]

AP22 AP23 AP26 AP29

AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49

AR5 AR52 AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63

AU1 AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

RSVD_TP RSVD_TP

RSVD

RSVD_TP RSVD_TP

RSVD_TP

RSVD

RSVD RSVD

Issued Date

AV63 AU63

C63 C62 B43

A51 B51

L60

N60

W23 Y22 AY15

PROC_OPI_COMP

AV62 D58

P22

VSS

N21

VSS

P20 R20

BDW_ULT_DDR3L

UCPU1P@

D33

VSS

D34

VSS

D35

VSS

D37

VSS

D38

VSS

D39

VSS

D41

VSS

D42

VSS

D43

VSS

D45

VSS

D46

VSS

D47

VSS

D49

VSS

D50

VSS

D51

VSS

D53

VSS

D54

VSS

D55

VSS

D57

VSS

D59

VSS

D62

VSS

E11

VSS

E17

VSS

F20

VSS

F26

VSS

F30

VSS

F34

VSS

F38

VSS

F42

VSS

F46

VSS

F50

VSS

F54

VSS

F58

VSS

F61

VSS

G18

VSS

G22

VSS

H13

VSS

16 OF 19

2013/07/04 2013/10/28

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS_SENSE

VSS

Compal Secr et Data

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63

V58 AH46 V23 E62 AH16

Deciphered Date

RC99 & RC100 close to PCH

1 2

RC100 100_0402_1%~DRC100 100_0402_1%~D

Title

Size Document Number Rev

Date: Sheet of

VSSSENSE [47]

Compal Electronics, Inc.

P14-MCP(10/10) PWR,VSS,CFG

LA-B441P

14 50Saturday, October 04, 2014

1.0

CHA DDR3L Memory Down Lower Bits

DDR_A_DQS#[0..7][16,7] DDR_A_DQS[0..7][16,7] DDR_A_D[0..31][7] DDR_A_MA[0..15][16,19,7]

UD28

VREFCA

VREFDQ

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_MA15

DDR_A_BA0 DDR_A_BA1 DDR_A_BA2

M_CLK_A_ DDR0 M_CLK_A_ DDR#0

DDR_A_CKE0 DDR_A_CKE1 M_ODT0

DDR_A_CS0# DDR_A_CS1#

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS0 DDR_A_DQS1

DDR_A_DQS#0 DDR_A_DQS#1

DDR3_DRAMRST#

RD29 240_0402_1%RD29 240_0402_1%

RD31 240_0402_1%RD31 240_0402_1%

A10/AP

A11

A12/BC#

A13

A14

A15/NC

BA0

BA1

BA2

CK#

CKE0

CKE1/NC

ODT0

ODT1/NC

CS0#

CS1#/NC

RAS#

CAS#

WE#

DQSL

DQSU

DQSL#

DQSU#

DML

DMU

RESET#

ZQ0

ZQ1/NC

96-BALL

96-BALL SDRAM DDR3L

SDRAM DDR3L

MT41K256 M16HA-125M: E_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

DDR_A_D4

DDR_A_D7

DDR_A_D1

DDR_A_D2

DDR_A_D5

DDR_A_D6

DDR_A_D0

DDR_A_D3

DDR_A_D10

DDR_A_D13

DDR_A_D15

DDR_A_D9

DDR_A_D14

DDR_A_D12

DDR_A_D11

DDR_A_D8

+1.35V_DDR +1.35V_DDR

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

+MD_VREF_CA

.047U_0402_16V7K

CD87

+MD_VREF_DQA

.047U_0402_16V7K

CD78

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BA0 DDR_A_BA1 DDR_A_BA2

M_CLK_A_ DDR0

M_CLK_A_ DDR#0

DDR_A_CKE0 DDR_A_CKE1 M_ODT0

DDR_A_CS0# DDR_A_CS1#

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS2 DDR_A_DQS3

DDR_A_DQS#2 DDR_A_DQS#3

DDR3_DRAMRST#

RD30 240_0402_1%RD30 240_0402_1%

RD32 240_0402_1%RD32 240_0402_1%

UD29

VREFCA

VREFDQ

A10/AP

A11

A12/BC#

A13

A14

A15/NC

BA0

BA1

BA2

CK#

CKE0

CKE1/NC

ODT0

ODT1/NC

CS0#

CS1#/NC

RAS#

CAS#

WE#

DQSL

DQSU

DQSL#

DQSU#

DML

DMU

RESET#

ZQ0

ZQ1/NC

MT41K256 M16HA-125M: E_FBGA96

96-BALL

96-BALL SDRAM DDR3L

SDRAM DDR3L

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

DDR_A_D20 DDR_A_D23 DDR_A_D18 DDR_A_D22 DDR_A_D21

DDR_A_D17

DDR_A_D19 DDR_A_D16

DDR_A_D31 DDR_A_D25 DDR_A_D26 DDR_A_D28 DDR_A_D30 DDR_A_D29 DDR_A_D27 DDR_A_D24

.047U_0402_16V7K

CD85

+MD_VREF_DQA

.047U_0402_16V7K

CD77

+MD_VREF_CA +MD_VREF_CA

+MD_VREF_DQA +MD_VREF_DQA

+MD_VREF_CA

D D

at least 20 mils wide with 20 mils spacing to other signals/planes. Short violations are acceptable if required due to tight routing constraints.

DDR3L Package (mm^2)

Hynix

9 x 13

10 x 13Samsung

Micron

C C

B B

9 x 14 10 x 14

PLACE NEAR DRAM

TBD

11 x 13.3

+1.35V_DDR

DDR_A_BA0[16,19,7] DDR_A_BA1[16,19,7] DDR_A_BA2[16,19,7]

M_CLK_A_ DDR0[16,19,7]

M_CLK_A_ DDR#0[16,19,7]

DDR_A_CKE0[16,19,7] DDR_A_CKE1[16,19,7]

M_ODT0[16,19]

DDR_A_CS0#[16,19,7] DDR_A_CS1#[16,19,7]

DDR_A_RAS#[16,19,7] DDR_A_CAS#[16,19,7]

DDR_A_WE#[16,19,7]

RD24

RD24 470_0402_5%~D

470_0402_5%~D

A00_1004: Change to short pad.

1 2

RD28

RD28 0_0402_1%

0_0402_1%

1 2

H_DRAMRST#[6]

A A

DDR3_DRAMRST# [16,17,18]

0.1U_0402_25V6K~D

CD5

+1.35V_DDR +1.35V_DDR

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CD66

CD67

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

CD69

CD68

Compal Secret Data

2013/07/04 2013/10/28

Compal Secret Data

Deciphered Date

1U_0402_6.3V6K~D

CD70

Title

P12-DDRIII Channel A

Size Document Number Rev

LA-B441P

Date: Sheet of

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CD71

Compal Electronics, Inc.

10U_0603_6.3V6M~D

CD72

CD73

15 50Sunday, October 05, 2014

1.0

+ 35 hidden pages

Compal LA-B441P Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual