Compal LA-B441P Schematic

A

B

C

D

E

MODEL NAME :

PCB NO :

BOM P/N :

ZZZ

1 1

MB_PCB

DAA0008I000

LA-B441P

TBD

ZAZ00

Dell/Compal Confidential

2 2

Schematic Document

Dino (Broadwell ULT)

3 3

2014-10-16

Rev: 1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

C

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P01-Cover Page

LA-B441P

E

150Thursday, October 16, 2014

1.0

A

www.vinaﬁx.vn

B

C

D

E

eDP Panel

miniDP Conn.

1 1

USB 3.0 Conn.

Precision Touch Pad

Digital Camera

Touch Screen

P.22

P.26

P.30

P.35

P.22

Daughter/B (LS-B441P)

USB 3.0 Conn.

2 2

( Power Share)

CardReader RTS5249

USB3.0

USB3.0 Re-Driver

eDP 1.3

DP 1.2

USB3.0/USB2.0

I2C / PS2

USB2.0

USB3.0

USB2.0

PCIE

Intel

Broadwell ULT

BGA 1168 Balls

15W TDP

Memory Bus (DDR3L-RS)

Dual Channel

1.35V DDR3L-RS 1600 MHz

SPI

SATA3 / PCIE *2

USB2.0

PCIE

UART

SDIO

Channel A DDR3L-RS 4Gb or 8Gb (x16) * 4

P.15,16

Channel B DDR3L-RS 4Gb or 8Gb (x16) * 4

P.17,18

SPI ROM 8MB

SPI ROM(vPRO) 4MB

TPM AT97SC3205

M.2 Slot B Key-B

# mSATA

M.2 Slot A-SD

WLAN BT

P.08

P.27

P.29

P.28

ALS/B (LS-B444P)

(Reserved ALS)

TCS3472

Reserved NFC Module Conn

(Reserved SMLink)

P.29

3 3

Fan conn.

P.29

(Reserve ALS SM BUS)

RTC conn.

DC/DC Interface CKT.

Power Circuit DC/DC

4 4

LED/B (LS-B443P)

P.32~33

P.38~48

Front Side LED+DMICx2 Board

A

B

SMBus

ECE1117

LPC Bus

MEC 5085

BCBUS

Page 5 ~ 14

C

HDA / I2S

Audio Codec ALC3263

P.36

I2C

MCP 23017

P.37

KBC/B (LS-B442P)

KSIO

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

Int.KBDKeyboard Controller

DMIC

Compal Secr et Data

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

D

Headphone Jack

( iPhone & Nokia compatible)

P.24

Int. Speaker

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P02-Block Diagram

LA-B441P

E

P.25

250Saturday, October 04, 2014

1.0

A

1 1

B

C

D

E

CPU Option

UCPU1

BDW_TBD@

UCPU1

BDW_TBD@

SA00006G10L

CL8064701325204 QDJ9

DRAM Option DRAM Config Option

UD32

Micron_4G@

UD32

UD28

Micron_4G@

UD29

Micron_4G@

UD31

Micron_4G@

UD4

Micron_4G@

UD4

UD7

Micron_4G@

UD7

UD1

Micron_4G@

UD1

Micron_4G@

UD3

Micron_4G@

UD3

Micron_4G@

Micron 4G

SA00005TH0L

2 2

SA00005TH0L

MT41K256M16HA-125M:E

UD28

Micron_8G@

UD28

Micron_8G@

SA00005TH0L

MT41K256M16HA-125M:E

UD29

Micron_8G@

UD29

Micron_8G@

SA00005TH0L

MT41K256M16HA-125M:E

UD31

Micron_8G@

UD31

Micron_8G@

SA00005TH0L

MT41K256M16HA-125M:E

UD32

Micron_8G@

UD32

Micron_8G@

SA00005TH0L

MT41K256M16HA-125M:E

UD1

Micron_8G@

UD1

Micron_8G@

SA00005TH0L

MT41K256M16HA-125M:E

UD7

Micron_8G@

UD7

Micron_8G@

SA00005TH0L

MT41K256M16HA-125M:E

UD3

Micron_8G@

UD3

Micron_8G@

SA00005TH0L

MT41K256M16HA-125M:E

UD4

Micron_8G@

UD4

Micron_8G@

Micron 8G

SA00006FB0L

MT41K512M16TNA-125M:E

UD28

Hynix_4G@

UD28

Hynix_4G@

SA00006FB0L

MT41K512M16TNA-125M:E

UD29

Hynix_4G@

UD29

Hynix_4G@

SA00006FB0L

MT41K512M16TNA-125M:E

UD31

Hynix_4G@

UD31

Hynix_4G@

SA00006FB0L

MT41K512M16TNA-125M:E

UD32

Hynix_4G@

UD32

Hynix_4G@

SA00006FB0L

MT41K512M16TNA-125M:E

UD1

Hynix_4G@

UD1

Hynix_4G@

SA00006FB0L

MT41K512M16TNA-125M:E

UD7

Hynix_4G@

UD7

Hynix_4G@

SA00006FB0L

MT41K512M16TNA-125M:E

UD3

Hynix_4G@

UD3

Hynix_4G@

SA00006FB0L

MT41K512M16TNA-125M:E

UD4

Hynix_4G@

UD4

Hynix_4G@

Hynix 4G

SA00006JF0L

H5TC4G63AFR-PBR

UD28

Hynix_8G@

UD28

Hynix_8G@

SA00006JF0L

H5TC4G63AFR-PBR

UD29

Hynix_8G@

UD29

Hynix_8G@

SA00006JF0L

H5TC4G63AFR-PBR

UD31

Hynix_8G@

UD31

Hynix_8G@

SA00006JF0L

H5TC4G63AFR-PBR

UD32

Hynix_8G@

UD32

Hynix_8G@

SA00006JF0L

H5TC4G63AFR-PBR

UD1

Hynix_8G@

UD1

Hynix_8G@

SA00006JF0L

H5TC4G63AFR-PBR

UD7

Hynix_8G@

UD7

Hynix_8G@

SA00006JF0L

H5TC4G63AFR-PBR

UD3

Hynix_8G@

UD3

Hynix_8G@

SA00006JF0L

H5TC4G63AFR-PBR

UD4

Hynix_8G@

UD4

Hynix_8G@

SA00006JF0L

Hynix 8G

SA00006Q90L

H5TC8G63AMR-PBR

3 3

UD28

Elpida_4G@

SA00006Q90L

H5TC8G63AMR-PBR

UD29

Elpida_4G@

UD29

Elpida_4G@

SA00006Q90L

H5TC8G63AMR-PBR

UD31

Elpida_4G@

UD31

Elpida_4G@

SA00006Q90L

H5TC8G63AMR-PBR

UD32

Elpida_4G@

UD32

Elpida_4G@

SA00006Q90L

H5TC8G63AMR-PBR

UD1

Elpida_4G@

UD1

Elpida_4G@

SA00006Q90L

H5TC8G63AMR-PBR

UD7

Elpida_4G@

UD7

Elpida_4G@

SA00006Q90L

H5TC8G63AMR-PBR

UD3

Elpida_4G@

UD3

Elpida_4G@

SA00006Q90L

H5TC8G63AMR-PBR

UD4

Elpida_4G@

UD4

Elpida_4G@

Elpida 4G

SA00005HT0L

K4B4G1646B-HKK0

UD28

Elpida_8G@

UD28

Elpida_8G@

SA00005HT0L

K4B4G1646B-HKK0

UD29

Elpida_8G@

UD29

Elpida_8G@

SA00005HT0L

K4B4G1646B-HKK0

UD31

Elpida_8G@

UD31

Elpida_8G@

SA00005HT0L

K4B4G1646B-HKK0

UD32

Elpida_8G@

UD32

Elpida_8G@

SA00005HT0L

K4B4G1646B-HKK0

UD1

Elpida_8G@

UD1

Elpida_8G@

SA00005HT0L

K4B4G1646B-HKK0

UD7

Elpida_8G@

UD7

Elpida_8G@

SA00005HT0L

K4B4G1646B-HKK0

UD3

Elpida_8G@

UD3

Elpida_8G@

SA00005HT0L

K4B4G1646B-HKK0

UD4

Elpida_8G@

UD4

Elpida_8G@

Elpida 8G

SA00006O90L

K4B8G1646B-MKK0

SA00006O90L

K4B8G1646B-MKK0

SA00006O90L

K4B8G1646B-MKK0

SA00006O90L

K4B8G1646B-MKK0

SA00006O90L

K4B8G1646B-MKK0

SA00006O90L

K4B8G1646B-MKK0

SA00006O90L

K4B8G1646B-MKK0

SA00006O90L

K4B8G1646B-MKK0

MEM_CONFIG2 MEM_CONFIG1 MEM_CONFIG0

RH316

Micron_4G@

RH316

RH314

Micron_4G@

RH314

Micron_4G@

SD028100280

10K_0402_5%~D

RH314

Micron_8G@

RH314

Micron_8G@

SD028100280

10K_0402_5%~D

RH314

Hynix_4G@

RH314

Hynix_4G@

SD028100280

10K_0402_5%~D

RH314

Hynix_8G@

RH314

Hynix_8G@

SD028100280

10K_0402_5%~D

RH271

Elpida_4G@

RH271

Elpida_4G@

SD028100280

10K_0402_5%~D

RH271

Elpida_8G@

RH271

Elpida_8G@

SD028100280

10K_0402_5%~D

RH315

Micron_4G@

RH315

Micron_4G@

SD028100280

10K_0402_5%~D

RH315

Micron_8G@

RH315

Micron_8G@

SD028100280

10K_0402_5%~D

RH180

Hynix_4G@

RH180

Hynix_4G@

SD028100280

10K_0402_5%~D

RH180

Hynix_8G@

RH180

Hynix_8G@

SD028100280

10K_0402_5%~D

RH315

Elpida_4G@

RH315

Elpida_4G@

SD028100280

10K_0402_5%~D

RH315

Elpida_8G@

RH315

Elpida_8G@

SD028100280

10K_0402_5%~D

Micron_4G@

SD028100280

10K_0402_5%~D

RH303

Micron_8G@

RH303

Micron_8G@

SD028100280

10K_0402_5%~D

RH316

Hynix_4G@

RH316

Hynix_4G@

SD028100280

10K_0402_5%~D

RH303

Hynix_8G@

RH303

Hynix_8G@

SD028100280

10K_0402_5%~D

RH316

Elpida_4G@

RH316

Elpida_4G@

SD028100280

10K_0402_5%~D

RH303

Elpida_8G@

RH303

Elpida_8G@

SD028100280

10K_0402_5%~D

4 4

LA-B441P

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

C

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P03-BoM Option

E

350Saturday, October 04, 2014

1.0

A

Board ID Table for AD channel

X01

X03 X04 A00

REV

CE54RE79

4700p130K 4700p

62K X02

4700p

33K

4700p

8.2K 4700p4.3K 4700p

2K 1K

4700p

BOARD_ID rise time is measured from 5%~68%.

PCH USB Port Mapping

USB PORT#

0

1

2

3

4

5

6

DESTINATION

External USB3(On IOB)

External USB3(On MB)

NGFF CARD WLAN

Touch Panel

Camera

7

SMBUS Control Table

SOURCE

I2C1C_CLK I2C1C_DATA

1 1

I2C1D_CLK I2C1D_DATA

I2C1G_CLK I2C1G_DATA

PCH_SML0CLK PCH PCH_SML0DATA

PCH_SML1CLK PCH_SML1DATA

SMBCLK SMBDATA

I2C1_DATA

MEC5085

PCH

PCHI2C1_CLK

BATTERY

V

Reserve ALS SMBUS

ALS

V

NFCCharger

XDP

Touch Pad

PCH DDI Port

V

Link

Mapping

DDI PORT# DESTINATION

1

mini-DP

2

V

CLK

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

FLEX CLK#

CLKOUT_LPC_0

CLKOUT_LPC_1

DESTINATIONDIFFERENTIAL CLK#

Card Reader

NGFF CARD WLAN

mSATA/ PCIe

DESTINATION

EC LPC

TPM

PCI EXPRESS PORT#

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

DESTINATION

Card Reader

NGFF CARD WLAN

mSATA/ PCIe(Port0+Port1)

SATA PORT#

DESTINATION

SATA0

SATA1

SATA2

SATA3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

A

m-SATA

Compal Secr et Data

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

Symbol Note :

: means Digital Ground

: means Analog Ground

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P04-Notes List

LA-B441P

450Saturday, October 04, 2014

1.0

5

D D

DP Port

PCH_DP_N0[26] PCH_DP_P0[26] PCH_DP_N1[26] PCH_DP_P1[26] PCH_DP_N2[26] PCH_DP_P2[26] PCH_DP_N3[26] PCH_DP_P3[26]

C C

4

BDW_ULT_DDR3L

C54 C55

C58

C51 C50 C53

C49

B58

B55 A55 A57 B57

B54

B50 A53 B53

UCPU1A@

DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3

DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3

UCPU1I@

1 OF 19

3

C45

EDP_TXN0

B46

EDP_TXP0

A47

EDP_TXN1

B47

EDP_TXP1

C47

EDP_TXN2

C46

EDP_TXP2

A49

EDPDDI

EDP_TXN3 EDP_TXP3

EDP_AUXN EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

B49

A45 B45

D20 A43

EDP_COM EDP_DISP

eDP_TXN_P0 [22] eDP_TXP_P0 [22] eDP_TXN_P1 [22] eDP_TXP_P1 [22]

eDP_TXN_P2 [22] eDP_TXP_P2 [22] eDP_TXN_P3 [22] eDP_TXP_P3 [22]

eDP_AUXN [22] eDP_AUXP [22]

1 2

RC36 24.9_0402_1%RC36 24.9_0402_1%

EDP_COM Width 20 mils, Spacing 25 mils, Length < 100 mil

2

+VCCIOA_OUT

1

Low voltage multipurpose DISP_UTIL pin on the processor for backlight modulation control of embedded panels and S3D device control for active shutter glasses. This pin will co-exist with functionality similar to existing BKLTCTL pin on the PCH.

A00_1004: Change to short pad.

RC147

0_0402_1%

EDP_BKLCTL

EDP_DISP

12

@

RC146

RC146 0_0402_5%~D

0_0402_5%~D

@

1 2

RC158

RC158 0_0402_5%~D

0_0402_5%~D

@

1 2

EDP_BIA_PWM [22]

EDP_HPD

Compal Secret Data

B9

PCH_DP_CLK

C9

PCH_DP_DAT

D9 D11

C5 B6 B5 A6

C8

PCH_DP_HPD

A8 D6

CPU_EDP_HPD

Enable : Pull up to 3.3V with 2.2K+-5% ohm Disable : No connect

Deciphered Date

PCH_DP_CLK [26] PCH_DP_DAT [26]

PCH_DP_AUXN [26]

PCH_DP_AUXP [26]

PCH_DP_HPD [26]

PCH_DP_HPD

+5VS

G

2

D

S

D

S

RC148

0_0402_1%

CPU_EDP_HPD

Title

P05-MCP(1/10) DDI,EDP

Size Document Number Rev

LA-B441P

Date: Sheet of

2

Date: Sheet of

0_0402_1%

@

12

A00_1004: Change to short pad.

RC160

RC160 100K_0402_5%~D

100K_0402_5%~D

Compal Electronics, Inc.

12

QC5

@

QC5

@

DII-DMN65D8LW-7~D

13

12

1

RH300100K_0402_5%~D RH300100K_0402_5%~D

EDP_HPD [22]

550Sunday, October 05, 2014

1.0

AD4

B8 A9 C6

U6 P4 N4 N2

U7 L1 L3 R5 L4

EDP_BKLCTL EDP_BKLEN EDP_VDDEN

PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO79 PIRQD/GPIO80 PME

GPIO55 GPIO52 GPIO54 GPIO51 GPIO53

eDP SIDEBAND

PCIE

9 OF 19

DISPLAY

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP

DDPB_HPD DDPC_HPD

PANEL_BKLEN[22] ENVDD_PCH[32,36]

@

DZ3

DZ3 RB751S40T1G_SOD523-2

RB751S40T1G_SOD523-2

PTP_INT#[35,36]

B B

1 2

T123@T123

SDIO_WAKE#[28]

CODEC_IRQ[24]

EDP_BKLCTL

PCH_GPIO77 PCH_GPIO78 PCH_GPIO79 PCH_GPIO80

TOUCHPAD _INTR# TOUCH_R ST_N_GYRO_IN T1 SDIO_WAKE# PCH_GPIO51 CODEC_IRQ

GPIO Signals

+3VS

RP4

1 8 2 7 3 6 4 5

10K_8P4R_5%

1 2

RH3547 10K_0402_5%~DRH3547 10K_0402_5%~D

1 2

RH3545 10K_0402_5%~DRH3545 10K_0402_5%~D

1 2

RH397 10K_0402_5%~DRH397 10K_0402_5%~D

1 2

RH3532 10K_0402_5%~D@RH3532 10K_0402_5%~D@

1 2

A A

RH3544 10K_0402_5%~D@RH3544 10K_0402_5%~D@

5

PCH_GPIO79 PCH_GPIO80 TOUCHPAD _INTR# PCH_DP_CLK PCH_GPIO78

PCH_GPIO77 TOUCH_R ST_N_GYRO_IN T1 SDIO_WAKE# CODEC_IRQ

PCH_GPIO51

4

+3VS

RP14

1 8 2 7 3 6 4 5

2.2K_0804_8P4R_5%

Security Classifi cation

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

PCH_DP_DAT

Functional Strap Definitions

DDI Port 1 Disabling

DDPB_CTRLDATA

Functional Strap Definitions

DDI Port 2 Disabling

DDPC_CTRLDATA

2013/07/04 2013/10/28

3

5

4

3

2

1

D D

+1.05VS_VCCST

12

RC43

RC43 62_0402_5%~D

62_0402_5%~D

H_PROCHOT#[36,39,40,42,47]

Avoid stub in the PWRGD path while placing resistors RC44 & RC53

C C

SM_RCOMP

1. Total Width : 12-15 mils.

2. Min Trace spacing for Group : 20 mils

3. Min Trace spacing for Group to Group :25 mils

4. Max Length : 500 mils

+1.35V_DDR

1

@

CC240

0.1U_0402_10V7K

2

+3VALW

B B

12

RC161

RC161 220K_0402_5%~D

220K_0402_5%~D

H_PECI

1. Total Length : 15 inchs

2. Resistor Value (±5%) : 43 ohm

3. Breakin/Breakout Length Max :0.4 ~ 1 inchs

1

2

3

H_CATERR#

H_PROCHOT#_RH_PROCHOT#

H_CPUPWRGD_R

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

T2@T2@

PECI_EC[36]

1 2

RC41 56_0402_5%RC41 56_0402_5%

1 2

RC44 10K_0402_5%~DRC44 10K_0402_5%~D

1 2

RC55 200_0402_1%~DRC55 200_0402_1%~D

1 2

RC58 121_0402_1%~DRC58 121_0402_1%~D

1 2

RC60 100_0402_1%~DRC60 100_0402_1%~D

H_DRAMRST#[15]

UC1

5

4

74AUP1G07GW_TSSOP5

VCC

Y

NC

GND

A

D61 K61 N62

K63

C61

AU60 AV60 AU61 AV15 AV61

UCPU1B@

PROC_DETECT CATERR PECI

PROCHOT

PROCPWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1

MISC

THERMAL

PWR

DDR3L

BDW_ULT_DDR3L

JTAG

2 OF 19

PRDY

PREQ PROC_TCK PROC_TMS

PROC_TRST

PROC_TDI

PROC_TDO

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

J62

XDP_PRD Y#

K62

XDP_PRE Q#

E60

CPU_XDP_TCK

E61

CPU_XDP_TMS

E59

CPU_XDP_TRST#

F63

CPU_XDP_TDI

F62

CPU_XDP_TDO

J60 H60 H61 H62 K59 H63 K60 J61

XDP_PRD Y# [20] XDP_PRE Q# [20] CPU_XDP_TCK [20] CPU_XDP_TMS [20] CPU_XDP_TRST# [20] CPU_XDP_TDI [20]

CPU_XDP_TDO [20]

XDP_BPM0 # [20] XDP_BPM1 # [20]

T226@T22 6@ T227@T22 7@ T228@T22 8@ T229@T22 9@ T230@T23 0@ T231@T23 1@

Place a test point pad to within 250 ps of the ROC_TCK pin.and the maximum distance of test point pad to the termination must not be over 200 ps.

The Pull Up/Pull down terminations (R1d,R2,R9) should be placed to within 200 ps (1100 mils) of respective Broadwell pins.

CPU_XDP_TDO

CPU_XDP_TCK

CPU_XDP_TRST#

BPM

1. Length match these signals within 360 mils.

2. Stubs on these nets should be limited to less than 1400 mils (35.5 mm) in length.

3. Routing Recommendation :1-6 inchs

4. Impedance : 50 ohm.

XDP_PRD Y# XDP_PRE Q# CPU_XDP_TCK CPU_XDP_TMS CPU_XDP_TRST# CPU_XDP_TDI CPU_XDP_TDO

R1d

R2

R9

12

RC48 51_0402_5%RC48 51_0402_5%

RC52 51_0402_5%RC52 51_0402_5%

RC54 51_0402_5%@ RC54 51_0402_5%@

T263@T26 3@ T264@T26 4@ T265@T26 5@ T266@T26 6@ T267@T26 7@ T268@T26 8@ T269@T26 9@

+1.05VS_VCCST

SM_PG_CTRL[46]

A A

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/07/04 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P06-MCP(2/10) PM,XDP

LA-B441P

1

1.0

650Saturday, October 04, 2014

1.0

5

DDR_A_D[0..63] [15,16] DDR_B_D[0..63] [17,18]

BDW_ULT_DDR3L

UCPU1C@

D D

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28

C C

DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57

B B

DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58

AW58

AY56

AW56

AV58 AU58 AV56 AU56 AY54

AW54

AY52

AW52

AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51

UCPU1C@

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

BDW_ULT_DDR3L

DDR CHANNEL A

3 OF 19

4

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1

SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3

SA_CS#0 SA_CS#1

SA_ODT0

SA_RAS

SA_WE

SA_CAS

SA_BA0 SA_BA1 SA_BA2

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1

AU37 AV37 AW36 AY36

AU43 AW43 AY42 AY43

AP33 AR32

AP32

AY34 AW34 AU34

AU35 AV35 AY41

AU36

DDR_A_MA0

AY37

DDR_A_MA1

AR38

DDR_A_MA2

AP36

DDR_A_MA3

AU39

DDR_A_MA4

AR36

DDR_A_MA5

AV40

DDR_A_MA6

AW39

DDR_A_MA7

AY39

DDR_A_MA8

AU40

DDR_A_MA9

AP35

DDR_A_MA10

AW41

DDR_A_MA11

AU41

DDR_A_MA12

AR35

DDR_A_MA13

AV42

DDR_A_MA14

AU42

DDR_A_MA15

AJ61

DDR_A_DQS#0

AN62

DDR_A_DQS#1

AM58

DDR_A_DQS#2

AM55

DDR_A_DQS#3

AV57

DDR_A_DQS#4

AV53

DDR_A_DQS#5

AL43

DDR_A_DQS#6

AL48

DDR_A_DQS#7

AJ62

DDR_A_DQS0

AN61

DDR_A_DQS1

AN58

DDR_A_DQS2

AN55

DDR_A_DQS3

AW57

DDR_A_DQS4

AW53

DDR_A_DQS5

AL42

DDR_A_DQS6

AL49

DDR_A_DQS7

AP49 AR51 AP51

at least 20 mils wide with 20 mils spacing to other signals/planes. Short violations are acceptable if required due to tight routing constraints.

M_CLK_A_ DDR#0 [1 5,16,19] M_CLK_A_ DDR0 [15 ,16,19]

DDR_A_CKE0 [15,16,19] DDR_A_CKE1 [15,16,19]

DDR_A_CS0# [15,16,19]

DDR_A_RAS# [15,16,19] DDR_A_WE# [15,16,19] DDR_A_CAS# [15,16,19]

DDR_A_BA0 [15,16,19] DDR_A_BA1 [15,16,19] DDR_A_BA2 [15,16,19] DDR_A_MA[0..15] [15,16,19]

DDR_A_DQS#[0..7] [15,16]

DDR_A_DQS[0..7] [15,16]

V_DDR_REF_CA [19] V_DDR_REF_DQA [19] V_DDR_REF_DQB [19]

3

UCPU1D@

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AY31

AW31

AY29

AW29

AV31

AU31

AV29

AU29

AY27

AW27

AY25

AW25

AV27

AU27

AV25 AU25 AM29

AK29

AL28

AK28 AR29 AN29 AR28

AP28 AN26 AR26 AR25

AP25

AK26 AM26

AK25

AL25

AY23

AW23

AY21

AW21

AV23 AU23

AV21 AU21

AY19

AW19

AY17

AW17

AV19 AU19

AV17 AU17 AR21 AR22

AL21 AM22 AN22

AP21

AK21

AK22 AN20 AR20

AK18

AL18

AK20 AM20 AR18

AP18

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

2

BDW_ULT_DDR3L

DDR CHANNEL B

4 OF 19

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3

SB_CS#0 SB_CS#1

SB_ODT0

SB_RAS

SB_WE

SB_CAS

SB_BA0 SB_BA1 SB_BA2

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

AM38 AN38 AK38 AL38

AY49 AU50 AW49 AV50

AM32 AK32

AL32

AM35 AK35 AM33

AL35 AM36 AU49

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

1

M_CLK_B _DDR#0 [1 7,18,19] M_CLK_B _DDR0 [17 ,18,19]

DDR_B_CKE0 [17,18,19] DDR_B_CKE1 [17,18,19]

DDR_B_CS0# [17,18,19]DDR_A_CS1# [15,16,19] DDR_B_CS1# [17,18,19]

DDR_B_RAS# [17,18,19] DDR_B_WE# [17,18,19] DDR_B_CAS# [17,18,19]

DDR_B_BA0 [17,18,19] DDR_B_BA1 [17,18,19] DDR_B_BA2 [17,18,19] DDR_B_MA[0..15] [17,18,19]

DDR_B_DQS#[0..7] [17,18]

DDR_B_DQS[0..7] [17,18]

A A

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/07/04 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P07-MCP(3/10) DDRIII

LA-B441P

1

1.0

750Saturday, October 04, 2014

1.0

5

RP5

D D

SPI_CLK_VROM

PCH_SPI_CLK_TPM[27]

SPI_SI_VROM

PCH_SPI_SI_TPM[27]

1 8 2 7 3 6 4 5

33_8P4R_5%

1 8 2 7 3 6 4 5

33_8P4R_5%

PCH_SPI_CLKSPI_CLK_ROM

RP6

PCH_SPI_SISPI_SI_ROM

4

3

2

1

12

RH55

RH55 1K_0402_5%~D

1K_0402_5%~D

+3.3V_M

12

RH57

RH57 1K_0402_5%~D

1K_0402_5%~D

+3.3V_M

12

RH3527

@0_0603_5%

1

EMI@

CH1245

15P_0402_50V8J

2

RF Reserved.

+3V_ROM

1

vpro@

CH1249

15P_0402_50V8J

2

RF Reserved.

LPC_AD0[36] LPC_AD1[36] LPC_AD2[36] LPC_AD3[36] LPC_FRAME#[36]

A00_1004: Change to short pad.

PCH_SPI_CS2#[27]

MC29

@MC29

@

1 2

12P_0402_50V8J~D

EMI@

MC30

12

22P_0402_50V8J~D

Reserve for EMI please close to U48

@

MC32

12

22P_0402_50V8J~D

Reserve for EMI please close to U727

PCH_SPI_CLK PCH_SPI_CS0# PCH_SPI_CS1#

PCH_SPI_SI PCH_SPI_SO PCH_SPI_IO2 PCH_SPI_IO3

PCH_SPI_CLK

SPI_CLK_ROM

SPI_CLK_VROM

AU14 AW12

AY12

AW11

AV12

BDW_ULT_DDR3L

UCPU1G@

LAD0 LAD1 LAD2 LAD3 LFRAME

AA3

SPI_CLK

Y7

SPI_CS0

Y4

SPI_CS1

AC2

SPI_CS2

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

AF1

SPI_IO3

BDW_ULT_DDR3L

LPC

SMBUS

SML1ALERT/PCHHOT /GPIO73

C-LINKSPI

SMBALERT/GPIO11

SMBDATA

SML0ALERT/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO75

SML1DATA/GPIO74

CL_DATA

7 OF 19

SMBCLK

CL_CLK

CL_RST

AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3

AF2 AD2 AF4

PCH_SMB_ALERT# PCH_SMBCLK PCH_SMBDATA PCH_SML0ALERT SML0CLK SML0DATA PCH_GPIO73 SML1_SMBCLK SML1_SMBDAT

PCH_SMBCLK [20] PCH_SMBDATA [20]

SML0CLK [29] SML0DATA [29]

SML1_SMBCLK [36] SML1_SMBDAT [36]

CL_CK [28] CL_DAT [28] CL_RST# [28]

Connect XDP

Connect NFC

Connect EC

PCH_SMBCLK PCH_SMBDATA SML1_SMBCLK SML1_SMBDAT

SML0CLK SML0DATA

PCH_SMB_ALERT# PCH_SML0ALERT PCH_GPIO73

RP2

1 8 2 7 3 6 4 5

2.2K_0804_8P4R_5%

1 2

RH70 499_0402_1%~DRH70 499_0402_1%~D

1 2

RH72 499_0402_1%~DRH72 499_0402_1%~D

RP16

1 8 2 7 3 6 4 5

10K_8P4R_5%

+3V_PCH

RP7

1 8

SPI_SO_VROM

PCH_SPI_SO_TPM[27]

SPI_IO3_VROM SPI_IO3_ROM

SPI_IO2_VROM

C C

2 7 3 6 4 5

33_8P4R_5%

1 8 2 7 3 6 4 5

33_8P4R_5%

PCH_SPI_SOSPI_SO_ROM

RP8

PCH_SPI_IO3

PCH_SPI_IO2SPI_IO2_ROM

SPI ROM FOR ME ( 8MByte )

U48

PCH_SPI_CS0# SPI_SO_ROM

4MB SPI ROM for Vpro

PCH_SPI_CS1# SPI_SO_VROM SPI_IO2_VROM

B B

1

/CS

2

DO(IO1)

3

/WP(IO2) GND4DI(IO0)

W25Q64FVSSIQ_SO8

U727

vpro@U727

vpro@

1

/CS

2

DO/IO1

3

/WP/IO2

4

GND

W25Q32FVSSIQ_SO8

/HOLD(IO3)

/HOLD/IO3

DI/IO0

8

VCC

7

SPI_IO3_ROM

6

SPI_CLK_ROMSPI_IO2_ROM

CLK

5

SPI_SI_ROM

8

VCC

7

SPI_IO3_VROM

6

SPI_CLK_VROM

CLK

5

SPI_SI_VROM

+3V_ROM

1

CH6

CH6 .1U_0402_16V7K~D

.1U_0402_16V7K~D

2

vpro@

1

CH7

CH7 .1U_0402_16V7K~D

.1U_0402_16V7K~D

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

3

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P08-MCP(4/10) LPC,SPI,SMBUS,CL

LA-B441P

1

850Sunday, October 05, 2014

1.0

5

4

3

2

1

RTCX1 RTCX2

1. Total Length : 1000 mils

2. Space > 15 mils

3. Resistor Value (±5%) : 10M

RH2

RH2 10M_0402_5%

10M_0402_5%

D D

C C

1 2

YH1

32.768KHZ_X1A000141000300

1 2

1

Max Crystal ESR = 50k Ohm.

CH2

CH2 15P_0402_50V8J~D

15P_0402_50V8J~D

2

HDA_SDIN/HDA_SDO/HDA_SYNC/HDA_BCLK/HDA_RST#

1. BO < 500 mils

2. 1000 mils < M1 < 14000 mils.

3. Trace Length Matching (HDA_SDIO,HDA_BCLK,HDA_SDOUT)

4. Resistor Value : 33 ohm

I2S_RST_ AUDIO#[24] I2S_BITCL K_AUDIO[24] I2S_SDO UT_AUDIO[24] I2S_SYNC _AUDIO[24]

PCH_RTCX1

PCH_RTCX2

1

CH3

CH3 15P_0402_50V8J~D

15P_0402_50V8J~D

2

RP15

1 8 2 7 3 6 4 5

33_8P4R_5%

B0M1

I2S_RST# I2S_BIT_C LK I2S_SDO UT I2S_SYNC

RF Reserved.

I2S_BIT_C LK

1

EMI@

CH1242

CH1242 15P_0402_50V8J

15P_0402_50V8J

2

B B

+3VS_AUDIO

12

@

RH42

RH42 1K_0402_5%~D

1K_0402_5%~D

I2S_SDO UT

+RTCVCC

12

RH31

RH31 330K_0402_5%~D

330K_0402_5%~D

A A

PCH_INTVRMEN

12

RH34

RH34 330K_0402_5%~D

330K_0402_5%~D

@

I2S_SDO UT

12

EMI@

MC31

MC31 10P_0402_50V8J~D

10P_0402_50V8J~D

+1.05V_M

Functional Strap Definitions

Flash Descriptor Security Override

HDA_SDO/ I2S0_TXD

INTRUDER#

1. Critical Low Speed Signal

2. Space > 15 mils

3. Frequency to Avoid 32K

4. All critical signals must stay away from potential glitch or noise sources on the platform.

0 = Enable security measures defined in the Flash Descriptor. 1 = Disable Flash Descriptor Security (override). This strap should only be asserted high using external pull-up in manufacturing/debug environments ONLY.

Functional Strap Definitions

Integrated VRM

INTVRMEN

5

0 = DCPSUS1, DCPSUS2, DCPSUS3 and DCPSUS4 are powered from an external power source (should be connected to an external VRM). 1 = Integrated VRMs enabled. DCPSUS1, DCPSUS2 and DCPSUS3 can be left as No Connect.

INTRUDER#

1. Critical Low Speed Signal

2. Space > 15 mils

3. Frequency to Avoid 32K

4. All critical signals must stay away from potential glitch or noise sources on the platform.

+RTCVCC

12

RH11

RH11 1M_0402_5%~D

1M_0402_5%~D

SM_INTRUDER#

PCH JTAG

The Pull Up/Pull down terminations (R4,R3d,R5) should be placed to within 200ps of the respective Broadwell pin.

R4

1 2

RH40 51_0402_5%RH40 51_0402_5%

R3d

1 2

RH445 51_0402_5%RH445 51_0402_5%

R5

1 2

RH39 51_0402_5%RH39 51_0402_5%

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS

4

ME Reset

SRTCRST#

1. Total Length : 8000 mils

2. Space > 15 mils

3. Impedance Target 50 Ω ±15% for Microstrip.

4. RC time delay between 18 ms - 25 ms must be met.

5. There must not be a jumper for SRTCRST# pin.

+RTCVCC +RTCVCC

12

RH23

RH23 20K_0402_5%~D

20K_0402_5%~D

PCH_SRTCRST# PCH_RTCRST#

1

CH5

CH5 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

UCPU1E

PCH_RTCX1 PCH_RTCX2 SM_INTRUDER# PCH_INTVRMEN PCH_SRTCRST#

PCH_JTAG_JTAGX PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TCK PCH_JTAG_TDI

Issued Date

PCH_RTCRST#

I2S_BIT_C LK I2S_SYNC I2S_RST#

I2S_SDO UT

PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_JTAG_JTAGX

PCH_RTCRST#[21]

I2S_SDIN 0[24]

I2S_SDO UT[21]

PCH_JTAG_TRST#[20] PCH_JTAG_TCK[20] PCH_JTAG_TDI[20] PCH_JTAG_TDO[20] PCH_JTAG_TMS[20]

PCH_JTAG_JTAGX[20]

TP should be placed to with 250ps (1380 mils) of the respetive Haswell ULT pins, and the distance between TP and termination (if any) must be within 200ps (1100 mils).

T273@T27 3@ T275@T27 5@ T276@T27 6@ T277@T27 7@ T278@T27 8@

Security Classifi cation

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

AW5

RTCX1

AY5

RTCX2

AU6

INTR UDER

AV7

INTV RMEN

AV6

SRTCRST

AU7

RTCRST

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST/I2S_MCLK

AY10

HDA_SDI0/I2S0_RXD

AU12

HDA_SDI1/I2S1_RXD

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN/I2S1_TXD

AV10

HDA_DOCK_RST/I2S1_SFRM

AY8

I2S1 _SCLK

AU62

PCH_TRST

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD

AC4

RSVD

AE63

JTAGX

AV2

RSVD

GPIO Signals

SATA0GP,SATA1GP,SATA2GP,SATA3GP

1. Needs a weak pull-up:10 KΩ ±10% pull-up to V3.3.

2. Unused SATA[3:0]GP pins must be terminated to either

3.3V rail or GND using 8.2–10 KΩ on the motherboard. Either pull-up or pull-down is acceptable.

2013/07/04 2013/10/28

3

RTC Reset

12

@

CLRP1

CLRP1 SHORT PADS

SHORT PADS

RTCRST#

1. Total Length : 8000 mils

2. Space > 15 mils

3. Impedance Target 50 Ω ±15% for Microstrip.

4. RC time delay between 18 ms - 25 ms must be met.

MPCIE_RS T#

HDD_DET# PCH_SATALED# SATA2_PCIE6_L1 mCARD_PCIE#_SATA_R

Compal Secret Data

12

RH25

RH25 20K_0402_5%~D

20K_0402_5%~D

1

CH4

CH4 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

BDW_ULT_DDR3L

RTC

AUDIO SATA

JTAG

5 OF 19

1 2

RH393 10K_0402_5%~DRH393 10K_0402_5%~D

1 2

RH466 10K_0402_5%~DRH466 10K_0402_5%~D RH35 10K_0402_5%~DRH35 10K_0402_5%~D RH467 10K_0402_5%~D@RH467 10K_0402_5%~D@ RH392 10K_0402_5%~DRH392 10K_0402_5%~D RH395 10K_0402_5%~D@RH395 10K_0402_5%~D@

Deciphered Date

1 2

12

12 12

+3VS

2

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3 SATA_TN0/PETN6_L3

SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2 SATA_TN1/PETN6_L2

SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1 SATA_TN2/PETN6_L1

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

SATA_IREF

RSVD RSVD

SATA_RCOMP

SATALED

mCARD_PCIE#_SATA_R

SATA2_PCIE6_L1

Title

Size Document Number Rev

Date: Sheet of

1.When SATA and PCIe are muxed, always route according to SATA design guidelines.

2. Breakout < 600 mils

3. Zdiff : 85 ohm

4. Isolation to Other Signal Groups: Breakout : 8 mils/ Main routing : 20 mils in MS, 15 mils in SL,DSL

5. Max Length : 2 via Max 8", 3 vias Max 7"

6. Within Layer Max Mismatch : 15 mils.

7. Total Length Max Mismatch : 10 mils.

8. AC capacitors to be placed as close as possible to the connector. Maximum distance from AC capacitors to connector is 500 mils.

9. Minimum breakout pair-to-pair spacing of 3.5 mils is allowed for a maximum length of 20 mils within the 600 mils breakout.

10. Design constraint: breakout routing should be non-interleaved to mitigate concerns on near-end crosstalk.

J5 H5 B15 A15

J8 H8 A17 B17

J6 H6 B14 C15

F5 E5 C17 D17

V1

MPCIE_RS T#

U1

HDD_DET#

V6

SATA2_PCIE6_L1

AC1

mCARD_PCIE#_SATA_R

A12 L11 K10 C12

SATA_RCOMP

U3

PCH_SATALED#

SATA_RCOMP, SATA_IREF

1. Break-out : 4 mils

2. 12-15 mil trace with <0.2 Ω.

3. Length total <= 500 mils.

4. Requires 12 mils isolation from all High Speed I/O and clocks. SATA_RCOMP

1. Tied up to a clean 1.05V source (VCCASATA3PLL) with no capacitor on the net.

2. 3 KΩ ±1% precision pull-up resistor SATA_IREF

1. Pull-up direct to 1.05V (VCCASATA3PLL).

R1020

R1020 0_0402_5%~D

0_0402_5%~D

1 2

R1021

R1021 0_0402_5%~D

0_0402_5%~D

1 2

Compal Electronics, Inc.

P09-MCP(4/10) RTC,AUDIO,SATA

LA-B444P

SATA_RN2/PERN6_L1 [29] SATA_RP2/PERP6_L1 [29] SATA_TN2/PETN6_L1 [29] SATA_TP2/PETP6_L1 [29]

SATA_RN3/PERN6_L0 [29] SATA_RP3/PERP6_L0 [29] SATA_TN3/PETN6_L0 [29] SATA_TP3/PETP6_L0 [29]

MPCIE_RS T# [ 28]

RH43

RH43 3K_0402_1%~D

3K_0402_1%~D

1 2

mCARD_PCIE#_SATA [29]

950Saturday, October 04, 2014

1

+V1.05S_ASATA3PLL

1.0

5

UCPU1F@

CLK_PCIE_MMI#[23] CLK_PCIE_MMI[23]

D D

C C

MMICLK_RE Q#[23]

USB1_PWR_EN[30]

CLK_PCIE_WLAN#[28] CLK_PCIE_WLAN[28]

WLANCLK_REQ#[28]

CLK_PCIE_mSATA#[29] CLK_PCIE_mSATA[29]

mSATACLK_REQ#[29]

1. Breakout Routing Length Max : 500 mils.

2. Breakin Routing Length Max : 1500 mils

3. Routing Min and Max Length : 2"~9"

4. Differential Pair Length Matching. <25 mils for PCIe, <20 mils for ITP

6. Max Vias : 4

5. Stitching vias should be placed with this spacing: a).30-mils pitch between differential clock via and closest stitching GND-via. b). Every differential clock via must have at least one GND stitching via with a maximum spacing of 30 mils (0.762 mm).

6. Placement of additional stitching vias, where possible, is recommended.

MMICLK_RE Q#

USB1_PWR_EN

LANCLK_REQ#

WLANCLK_REQ#

PEG_WIGIGCLK_REQ#

mSATACLK_REQ#

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5/GPIO23

CardReader

BDW_ULT_DDR3L

CLOCK

SIGNALS

WiFi/BT

SSD

6 OF 19

4

A25 B25

K21 M21 C26

C35 C34 AK8 AL8

AN15 AP15

B35 A35

XTAL24_IN XTAL24_OU T

XCLK_BIASREF <100 MILS

XCLK_BIAS REF

TESTLOW 1 TESTLOW 2 TESTLOW 3 TESTLOW 4

CLKOUT_LPC0 CLKOUT_LPC1

TESTLOW 1 TESTLOW 2 TESTLOW 3 TESTLOW 4

XTAL24_IN

XTAL24_OUT

RSVD RSVD

DIFFCLK_BIASREF

TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8

CLKOUT_LPC_0 CLKOUT_LPC_1

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

3

1 2

RH113 3K_0402_1%~DRH113 3K_0402_1%~D

1 2

RH360 22_0402_5%~DRH360 22_0402_5%~D

1 2

RH428 22_0402_5%~DRH428 22_0402_5%~D

RH36 10K_0402_5%~DRH36 10K_0402_5%~D RH41 10K_0402_5%~DRH41 10K_0402_5%~D RH44 10K_0402_5%~DRH44 10K_0402_5%~D RH45 10K_0402_5%~DRH45 10K_0402_5%~D

12 12 12 12

+V1.05S_AXCK_LCPLL

CLK_PCI_MEC CLK_LPC_DEBUG

2

CLK_PCI_MEC [36] CLK_LPC_DEBUG [36]

XTAL24_IN

XTAL24_OU T

RH117 1M_0402_5%~DRH117 1M_0402_5%~D

24MHZ_12PF_7V24000020

1

CH24

CH24 15P_0402_50V8J~D

15P_0402_50V8J~D

2

15P_0402_50V8J

1

1 2

YH2

123

4

CLK_LPC_DEBUG CLK_PCI_MEC

CH1243

@ CH1243

@

1

2

1

CH23

CH23 15P_0402_50V8J~D

15P_0402_50V8J~D

2

1

CH1244

@CH1244

@

15P_0402_50V8J

2

RF Reserved.

+3VS

1 2

RH100 10K_0402_5%~DRH100 10K_0402_5%~D

1 2

RH95 10K_0402_5%~DRH95 10K_0402_5%~D

1 2

RH91 10K_0402_5%~DRH91 10K_0402_5%~D

1 2

RH103 10K_0402_5%~DRH103 10K_0402_5%~D

1 2

RH107 10K_0402_5%~DRH107 10K_0402_5%~D

1 2

RH110 10K_0402_5%~DRH110 10K_0402_5%~D

MMICLK_RE Q# USB1_PWR_EN LANCLK_REQ# WLANCLK_REQ# PEG_WIGIGCLK_REQ# mSATACLK_REQ#

B B

A A

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/07/04 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P10-MCP(5/10) CLOCKS

LA-B444P

1

1.0

10 50Saturday, October 04, 2014

1.0

5

Deep S3 support, connect to EC

SIO_PWRBTN#

T281@T281@

D D

NON-Deep S3 Support

Deep S3 support, connect to DSW power rail

+3V_PCH_DSW

RP20

SYS_RESET#

EC_WAKE# PCH_BATLOW#

AC_PRESENT

PCH_RSMRST#

RESET_OUT#_R

C C

TLS Confidentiality

Low - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High - Intel ME Crypto Transport Layer Security (TLS)

*

cipher suite with confidentiality

+3V_PCH

RH270 1K_0402_5%~DRH270 1K_0402_5%~D

+3V_PCH

RH3538 10K_0402_5%~DRH3538 10K_0402_5%~D

RH3536 10K_0402_5%~DRH3536 10K_0402_5%~D

RH382 100K_0402_5%~DRH382 100K_0402_5%~D

RH294 10K_0402_5%~D@ RH294 10K_0402_5%~D@

RH3537 10K_0402_5%~DRH3537 10K_0402_5%~D

RH3533 10K_0402_5%~DRH3533 10K_0402_5%~D

RH3535 10K_0402_5%~DRH3535 10K_0402_5%~D

B B

RH3541 10K_0402_5%~DRH3541 10K_0402_5%~D

RH3546 10K_0402_5%~DRH3546 10K_0402_5%~D

RH465 1M_0402_5%~DRH465 1M_0402_5%~D

RH400 100K_0402_5%~DRH400 100K_0402_5%~D

+3VS

RH3534 10K_0402_5%~DRH3534 10K_0402_5%~D

RH3543 10K_0402_5%~DRH3543 10K_0402_5%~D

RH383 100K_0402_5%~DRH383 100K_0402_5%~D

RH3540 10K_0402_5%~D@RH3540 10K_0402_5%~D@

RH3539 10K_0402_5%~DRH3539 10K_0402_5%~D

RH457 49.9K_0402_1%~DRH457 49.9K_0402_1%~D

RH458 49.9K_0402_1%~DRH458 49.9K_0402_1%~D

RH459 49.9K_0402_1%~DRH459 49.9K_0402_1%~D

RH460 49.9K_0402_1%~DRH460 49.9K_0402_1%~D

RH3548 10K_0402_5%~DRH3548 10K_0402_5%~D

A A

RH3530 10K_0402_5%~DRH3530 10K_0402_5%~D

RH3531 10K_0402_5%~DRH3531 10K_0402_5%~D

+3VS

1 8 2 7 3 6 4 5

10K_8P4R_5%

RH12 10K_0402_5%~DRH12 10K_0402_5%~D

RH159 10K_0402_5%~DRH159 10K_0402_5%~D

RH394 10K_0402_5%~DRH394 10K_0402_5%~D

12

1 2

RH37 1K_0402_5%~D@ RH37 1K_0402_5%~D@

LOW=Default

*

HIGH=No Reboot

12

5

+3VS

HOST_ALERT1_R_N

PCH_GPIO12

SIO_EXT_SMI#

UART_WAKE#

NFC_IRQ

SIO_EXT_WAKE#

MEDIACARD_IRQ#

MEDIACARD_RST#

CAM_CBL_DET#

PCH_GPIO58

NFC_DET#

USB0_PWR_EN

TPM_PIRQ#

PCH_GPIO49

SIO_EXT_SCI#

PCH_GPIO38

PCH_GPIO16

UART1_RXD

UART1_TXD

UART1_RTS#

UART1_CTS#

TOUCH_PANEL_INTR#

PCH_GPIO48

PCH_GPIO87

SPKR

SUSACK#[36] PM_SYS_RESET#[20,21] SYS_PWROK[20,36] RESET_OUT#[35,36]

PCH_RSMRST#[36] ME_SUS_PWR_ACK[36] SIO_PWRBTN#[20,36] AC_PRESENT[36]

PM_SLP_S0#[21,45] SIO_SLP_WLAN#[36]

PCH_PLTRST#_EC[20,23,27,28,36]

PCH_RSMRST# PCH_RSMRST#_R

A00_1004: Change to short pad.

4

12

RH171

RH171 100K_0402_5%~D

100K_0402_5%~D

Audio CODEC

+3V_PCH

BC@

RH3542 10K_0402_5%~D

CSMB@

RH3549 10K_0402_5%~D

4

Deep S3 (Pop RH430)

+3VS

RH168 0_0402_5%~D@RH168 0_0402_5%~D@

5

3

1 2

UH5

VCC

IN1

IN2

GND

1

2

12 12 12 12

12 12

12

MC74VHC1G08DFT2G_SC70-5

RH430 0_0402_1%@RH430 0_0402_1%@ RH450 0_0402_1%@RH450 0_0402_1%@ RH455 0_0402_1%@RH455 0_0402_1%@ RH452 0_0402_1%@RH452 0_0402_1%@

RH133 0_0402_1%@RH133 0_0402_1%@ RH297 0_0402_1%@RH297 0_0402_1%@

RH137 0_0402_1%@RH137 0_0402_1%@

RH463 0_0402_1%@RH463 0_0402_1%@

OUT

closed MCP 2000 mils

T279@T279@

T282@T282@

T286@T286@ T287@T287@

PCH_AUDIO_PWR[32]

SIO_EXT_WAKE#[36]

TPM_PIRQ#[27]

BT_CS_NOTICE[28]

EC_WAKE#[36]

PCH_NFC_RST#[29]

NFC_IRQ[29]

MEDIACARD_PWREN[32]

NFC_DET#[29]

CAM_CBL_DET#[22]

MEDIACARD_IRQ#[23]

TOUCH_PANEL_INTR#[22]

MPHYP_PWR_EN[33]

KB_DET#[34]

T288@T288@

EN_CAM[32]

SIO_EXT_SMI#[36]

UART_WAKE#[28]

mSATA_DEVSLP[29]

SIO_EXT_SCI#[36] SPKR[24]

I2C0_SDA_DSP[24] I2C0_SCK_DSP[24]

12

4

SUSACK#_R SYS_RESET#

RESET_OUT#_R PM_APWROK_R PCH_PLTRST#

SUS_PWR_DN SIO_PWRBTN# AC_PRESENT_RAC_PRESENT PCH_BATLOW# SLP_S0#

@

RH183

RH183 10K_0402_5%~D

10K_0402_5%~D

1 2

PCH_AUDIO_PWR

KB_DET#

MEM_CONFIG0 MEM_CONFIG1

PCH_AUDIO_PWR SIO_EXT_WAKE# PCH_GPIO12 HOST_ALERT1_R_N PCH_GPIO16 TPM_PIRQ#

EC_WAKE#

NFC_IRQ

MEDIACARD_RST#

PCH_GPIO58 NFC_DET# CAM_CBL_DET# MEDIACARD_IRQ# PCH_GPIO48 PCH_GPIO49 TOUCH_PANEL_INTR# MPHYP_PWR_EN KB_DET# PCH_GPIO14 EN_CAM SIO_EXT_SMI# CONFIG_BID

UART_WAKE# USB0_PWR_EN

MEM_CONFIG0 PCH_GPIO38 SIO_EXT_SCI# SPKR

1 2

RA7 0_0402_1%@RA7 0_0402_1%@

1 2

RA8 0_0402_1%@RA8 0_0402_1%@

A00_1004: Change to short pad.

CONFIG_BID

UCPU1H@

AK2

SUSACK

AC3

SYS_RESET

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST

AW6

RSMRST

AV4

SUSWARN/SUSPW RDNACK/GPIO30

AL7

PWRBTN

AJ8

ACPRESENT/GPIO31

AN4

BATLOW/ GPIO72

AF3

SLP_S0

AM5

SLP_WLAN/GPIO2 9

PCH_PLTRST#

UCPU1J@

P1

BMBUSY/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

GPIO15

Y1

GPIO16

T3

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN/ GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

BDW_ULT_DDR3L

SYSTEM POWER MANAGEMENT

PCH Strap PIN

DSWODVREN

RH147 330K_0402_5%~DRH147 330K_0402_5%~D

DSWODVREN - On Die DSW VR Enable

H：Enable

*

L：Disable

3.3V_mSATA_EN

BDW_ULT_DDR3L

GPIO

1 2

RH424 5.1K_0402_1%RH424 5.1K_0402_1%

1 2

RH425 5.1K_0402_1%RH425 5.1K_0402_1%

I2C0_SDA I2C0_SCK

8 OF 19

10 OF 19

3

RH431 0_0402_5%~D@RH431 0_0402_5%~D@

RH423 100K_0402_5%~D@RH423 100K_0402_5%~D@

CPU/

CPU/ MISC

MISC

SERIAL IO

+3VS

12

DSWVRMEN

DPWROK

WAKE

CLKRUN/GPIO32

SUS_STAT/GPIO61

SUSCLK/GPIO62

SLP_S5/GPIO63

SLP_S4 SLP_S3

SLP_A SLP_SUS SLP_LAN

+RTCVCC

+3VS

U682

@

5

S IC TC7SZ14FU SSOP 5P

1

P

NC

4

2

Y

A

G

3

12

1 2

THRMTRIP

RCIN/GPIO82

SERIRQ

PCH_OPI_RCOMP

RSVD RSVD

GSPI0_CS/GPIO83

GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86

GSPI1_CS/GPIO87

GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90 UART0_RXD/GPIO91 UART0_TXD/GPIO92

UART0_RTS/GPIO93 UART0_CTS/GPIO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1

UART1_RST/GPIO2 UART1_CTS/GPIO3

I2C0_SDA/ GPIO4

I2C0_SCL /GPIO5

I2C1_SDA/ GPIO6

I2C1_SCL /GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69

RF Reserved.

SDIO_CLK

AW7

DSWODVREN

AV5

PCH_DPWROK_R

AJ5

PCH_PCIE_WAKE#

A00_1004: Change to short pad.

V5

CLKRUN#

AG4

SUS_STAT#/LPCPD#

AE6

SUSCLK

AP5

AJ6 AT4 AL5 AP4 AJ7

D60 V4 T4 AW15 AF20 AB21

R6 L6 N6 L8 R7 L5 N7 K2 J1 K3 J2 G1 K4 G2 J3 J4 F2 F3 G4 F1 E3 F4 D3 E4 C3 E2

RH132 0_0402_1%@RH132 0_0402_1%@

SIO_SLP_S3# SIO_SLP_A#

PM_APWROK[36]

1.05V_M_PWRGD[45]

H_THERMTRIP# SIO_RCIN# IRQ_SERIRQ PCH_OPIRCOMP

Width = 15 mil, Spacing = 12 mil Close PCH within 500 mil

NGFF_PWREN PCH_GPIO84

3.3V_mSATA_EN BBS_BIT PCH_GPIO87 GPIO88_SLP_S0#

PCH_GPIO90 DDR_CHA_EN DDR_CHB_EN MEM_CONFIG1 MEM_CONFIG2 UART1_RXD UART1_TXD UART1_RTS# UART1_CTS# I2C0_SDA I2C0_SCK I2C1_SDA I2C1_SCK SDIO_CLK

SDIO_D0

1

CH1246

15P_0402_50V8J

2

SSD_PWREN [32]

RC156 49.9_0402_1%~DRC156 49.9_0402_1%~D

PCH_PCIE_WAKE# [ 36]

H_THERMTRIP# [36]

NGFF_PWREN [32]

GPIO88_SLP_S0# [36]

3.3V_TS_EN [32]

UART1_RXD [28] UART1_TXD [28] UART1_RTS# [28]

UART1_CTS# [28]

I2C1_SDA [35]

I2C1_SCK [35] SDIO_CLK [28]

SDIO_CMD [28]

SDIO_D0 [28]

SDIO_D1 [28]

SDIO_D2 [28]

SDIO_D3 [28]

12

SIO_SLP_A#

RH134

RH135

1 2

T284@T284 @

2

CLKRUN# [36]

SUSCLK_R [28,29] SIO_SLP_S5# [21,36]

SIO_SLP_S4# [21,36] SIO_SLP_S3# [21,36,44,46] SIO_SLP_A# [21,36] SIO_SLP_SUS# [ 36]

1

12

0_0402_5%~D

2

12

@RH135

@

I2C is daisy chain routing with pull up on the last device

DDR Memory Configuratino Type Strap pin

+3VS

GPIO Pin

PCH_GPIO70

PCH_GPIO93

PCH_GPIO94

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

3

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

2

Deep S3 Support

+3VLP

5

P

B

4

O

A

G

UC6

TC7SH08FU_SSOP5~D

3

SIO_RCIN# [36] IRQ_SERIRQ [36]

RH303 10K_0402_5%~D@ RH303 10K_0402_5%~D@

RH271 10K_0402_5%~D@ RH271 10K_0402_5%~D@

RH180 10K_0402_5%~D@ RH180 10K_0402_5%~D@

Pin Name

MEM_CONFIG0

MEM_CONFIG1

MEM_CONFIG2

SUS_STAT#/LPCPD#

SUS_PWR_DN

KB_DET#

PCH_PCIE_WAKE#

PCH_DPWROK_R

Deep S3 Support

PCH_DPWROK_R

PM_APWROK_R

CLKRUN#

H_THERMTRIP#

PCH_GPIO90

PCH_GPIO84

GPIO88_SLP_S0#

NGFF_PWREN

MPHYP_PWR_EN

I2C1_SDA

I2C1_SCK

IRQ_SERIRQ

SIO_RCIN#

DDR_CHA_EN

DDR_CHB_EN

DDR_CHA_EN

DDR_CHB_EN

GPIO86 have internal pull down

GPIO66 have internal pull down

12

Micron 4G SA00005TH0L

01

0

Date: Sheet of

1

1 2

RH197 10K_0402_5%~D@RH197 10K_0402_5%~D@

1 2

RH154 1M_0402_5%~DRH154 1M_0402_5%~D

1 2

RH302 100K_0402_5%~DRH302 100K_0402_5%~D

1 2

RH146 1K_0402_5%~DRH146 1K_0402_5%~D

1 2

RH401 100K_0402_5%~D@ RH401 100K_0402_5%~D@

RH309 0_0402_1%@RH309 0_0402_1%@

12

+3V_PCH

+3V_PCH_DSW

PCH_DPWROK [36]

A00_1004: Change to short pad.

+3VS

12

1 2

Boot BIOS LocationPCH_GPIO86

SPI

1 2

12

+1.05VS_VCCST

+3VS

+VS_LPSS_SDIO

12

RH248 8.2K_0402_5%~DRH248 8.2K_0402_5%~D

SUSCLK

CH102 10P_0402_50V8J~D

EMI@

Reserve for RF please close to UH1

EMI@

RC149 1K_0402_5%~DRC149 1K_0402_5%~D

RH200 10K_0402_5%~DRH200 10K_0402_5%~D

RH199 10K_0402_5%~DRH199 10K_0402_5%~D

RH198 10K_0402_5%~D@RH198 10K_0402_5%~D@

R1396 100K_0402_5%~DR1396 100K_0402_5%~D

R1185 100K_0402_5%~DR1185 100K_0402_5%~D

RH3 10K_0402_5%~DRH3 10K_0402_5%~D

RH5 10K_0402_5%~DRH5 10K_0402_5%~D

RH29 10K_0402_5%~DRH29 10K_0402_5%~D

RH196 10K_0402_5%~DRH196 10K_0402_5%~D

RH440 100K_0402_5%~DRH440 100K_0402_5%~D

RH441 100K_0402_5%~DRH441 100K_0402_5%~D

RH442 SHORT PADS@ RH442 SHORT PADS@

RH443 SHORT PADS@ RH443 SHORT PADS@

Boot BIOS Strap

0

*

SDIO_D0

RH434 1K_0402_5%~D@ RH434 1K_0402_5%~D@

RH435 1K_0402_5%~D@ RH435 1K_0402_5%~D@

A16 SWAP OVERRIDE STRAP

LOW = A16 SWAP OVERRIDE

STP_A16OVR

TBD

Title

Size Document Number Rev

*

HIGH = NO OVERRIDE

Hynix 8G SA00006Q90L

10

1

0

1

12

Elpida 8G SA00006O90L

TBD

0

11

11 50Sunday, October 05, 2014

MEM_CONFIG0

MEM_CONFIG2

MEM_CONFIG1

0

Hynix 4G SA00006JF0L

1

RH316 10K_0402_5%~D@ RH316 10K_0402_5%~D@

RH314 10K_0402_5%~D@ RH314 10K_0402_5%~D@

RH315 10K_0402_5%~D@ RH315 10K_0402_5%~D@

00

Compal Electronics, Inc.

P11-MCP(7/10) PM,GPIO,LPIO,MISC

LA-B441P

1

0

1.0

5

D D

PCIE_PRX_WLANTX_N4[28]

NGFF

CardReader

C C

PCIE_PRX_WLANTX_P4[28]

PCIE_PTX_WLANRX_N4[28] PCIE_PTX_WLANRX_P4[28]

PCIE_PRX_CARDTX_N1[23] PCIE_PRX_CARDTX_P1[23]

PCIE_PTX_CARDRX_N1[23] PCIE_PTX_CARDRX_P1[23]

1 2

CH11 0.1U_0402_10V7K~DCH11 0.1U_0402_10V7K~D

1 2

CH16 0.1U_0402_10V7K~DCH16 0.1U_0402_10V7K~D

1 2

CH25 0.1U_0402_10V7K~DCH25 0.1U_0402_10V7K~D

1 2

CH26 0.1U_0402_10V7K~DCH26 0.1U_0402_10V7K~D

+V1.05S_AUSB3PLL

1 2

RH338 3K_0402_1%~DRH338 3K_0402_1%~D

Width = 15 mil, Spacing = 15 mil Close PCH within 500 mil

4

PCIE_PTX_WLANRX_N4_C PCIE_PTX_WLANRX_P4_C

PCIE_PTX_C_CARDRX_N1 PCIE_PTX_C_CARDRX_P1

PCIE_RCOMP

F10 E10

C23 C22

F8 E8

B23 A23

H10

G10

B21 C21

E6 F6

B22 A21

G11

F11

C29 B30

F13

G13

B29 A29

G17

F17

C30 C31

F15

G15

B31 A31

E15 E13 A27 B27

UCPU1K@

PERN5_L0 PERP5_L0

PETN5_L0 PETP5_L0

PERN5_L1 PERP5_L1

PETN5_L1 PETP5_L1

PERN5_L2 PERP5_L2

PETN5_L2 PETP5_L2

PERN5_L3 PERP5_L3

PETN5_L3 PETP5_L3

PERN3 PERP3

PETN3 PETP3

PERN4 PERP4

PETN4 PETP4

PERN1/USB3RN3 PERP1/USB3RP3

PETN1/USB3TN3 PETP1/USB3TP3

PERN2/USB3RN4 PERP2/USB3RP4

PETN2/USB3TN4 PETP2/USB3TP4

RSVD RSVD PCIE_RCOMP PCIE_IREF

BDW_ULT_DDR3L

PCIE USB

11 OF 19

3

USB2N0 USB2P0

USB2N1 USB2P1

USB2N2 USB2P2

USB2N3 USB2P3

USB2N4 USB2P4

USB2N5 USB2P5

USB2N6 USB2P6

USB2N7 USB2P7

USB3RN1 USB3RP1

USB3TN1 USB3TP1

USB3RN2 USB3RP2

USB3TN2 USB3TP2

USBRBIAS

RSVD RSVD

OC0/GPIO40 OC1/GPIO41 OC2/GPIO42 OC3/GPIO43

AN8 AM8

AR7 AT7

AR8 AP8

AR10 AT10

AM15 AL15

AM13 AN13

AP11 AN11

AR13 AP13

G20 H20

C33 B34

E18 F18

B33 A33

AJ10

USBRBIAS

AJ11 AN10 AM10

AL3

USB_OC0#

AT1

USB_OC1#

AH2

USB_OC2#

AV3

USB_OC3#

closed MCP 2000 mils

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

USB20_N0 [23] USB20_P0 [23]

USB20_N1 [30] USB20_P1 [30]

USB20_N2 [28] USB20_P2 [28]

USB20_N3 [22] USB20_P3 [22]

USB20_N4 [22] USB20_P4 [22]

USB3RN0 [23] USB3RP0 [23]

USB3TN0 [23] USB3TP0 [23]

USB3RN1 [30] USB3RP1 [30]

USB3TN1 [30] USB3TP1 [30]

Within 450 mils

1 2

RH163

22.6_0402_1%

USB_OC0# [23] USB_OC1# [30]

2

USB2.0 IO/B Side

USB2.0 M/B Side

NGFF (WLAN)

Touch Panel

Camera

USB3.0 IO/B Side

USB3.0 M/B Side

Net USB_BIAS route impedacnes should be 50-ohm and length less than 450-mil spacing is 15-mil.

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

T289@T289@ T290@T290@ T291@T291@ T292@T292@

RP21

1 8 2 7 3 6 4 5

10K_8P4R_5%

1

+3V_PCH

BDW_ULT_DDR3L

UCPU1Q@

DC_TEST_AY2_AW2 DC_TEST_AY3_AW3

DC_TEST_AY61_AW61 DC_TEST_AY62_AW62

B B

A A

5

DC_TEST_A3_B3 DC_TEST_A61_B61 DC_TEST_B62_B63

DC_TEST_C1_C2

4

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

UCPU1R@

AT2

RSVD

AU44

RSVD

AV44

RSVD

D15

RSVD

F22

RSVD

H22

RSVD

J21

RSVD

BDW_ULT_DDR3L

17 OF 19

BDW_ULT_DDR3L

18 OF 19

DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

3

A3

DC_TEST_A3_B3

A4

A60 A61

DC_TEST_A61_B61

A62 AV1 AW1 AW2

DC_TEST_AY2_AW2

AW3

DC_TEST_AY3_AW3

AW61

DC_TEST_AY61_AW61

AW62

DC_TEST_AY62_AW62

AW63

N23 R23 T23 U10

AL1 AM11 AP7 AU10 AU15 AW14 AY14

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P12-MCP(8/10) PCIE,USB

LA-B441P

1

12 50Saturday, October 04, 2014

1.0

5

+1.35V_DDR

10U_0603_6.3V6M~D

1

2

D D

2.2U_0402_6.3V6M~D

1

2

10U_0603_6.3V6M~D

1

CC160

CC161

2

2.2U_0402_6.3V6M~D

CC233

CC238

1

2

10U_0603_6.3V6M~D

1

CC162

2

2.2U_0402_6.3V6M~D

CC239

1

2

10U_0603_6.3V6M~D

1

CC164

CC163

CC234

CC165

2

VR_ON

close to ULT within 0.5"~1"

1 2

XDP_PWRGD[20]

+1.05VS_VCCST

C C

2.2UH_LQM2MPN2R2NG0L_30%

B B

+1.05VDX_MODPHY

R1240 0.005_1206_1%R1240 0.005_1206_1%

+1.05VS

1 2

2.2UH_LQM2MPN2R2NG0L_30%

100U_A1_6.3VM_R70M

+1.05VDX_MODPHY

1 2

2.2UH_LQM2MPN2R2NG0L_30%

A A

+1.05VS

RH355

1 2

@

0_0603_5%

R1180 1K_0402_5%~DR1180 1K_0402_5%~D

close to CPU

RC93 75_0402_5%RC93 75_0402_5%

R1371 130_0402_1%R1371 130_0402_1%

LH10

1 2

SIP

1 2

LH12

LH11

+V1.05S_AXCK_DCB_L

12

1 2

+3VS_AUDIO

1

CH85

CH85 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

+V1.05S_APLLOPI

1

+

CH36

1U_0402_6.3V6K~D

2

2.2UH_LQM2MPN2R2NG0L_30%

100U_A1_6.3VM_R70M

1

C1312

2

22U_0805_6.3V6M

+V1.05VS_VCCHSIO

1

CH40

2

CH1213

+V1.05S_ASATA3PLL

1

C1314

2

22U_0805_6.3V6M

L61

1 2

5

1

2

1U_0402_6.3V6K~D

1

2

+V1.05S_AUSB3PLL+1.05VDX_MODPHY

C1313

C1315

CH62

VR_SVID_ALRT#

H_CPU_SVIDDAT

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

1.05VS_VCCST_PG

1

EMI@

CH1247

15P_0402_50V8J

2

RF Reserved.

+1.05V_PCH

RH405

1 2

@

0_0603_5%~D

1

CH41

2

1U_0402_6.3V6K~D

22U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1

CH1248

@ CH1248

@

15P_0402_50V8J

2

RF Reserved.

+V1.05S_AXCK_DCB

1

+

CH1229

1U_0402_6.3V6K~D

2

SIP

+1.05VS

RH340

RH340 0_0805_5%

0_0805_5%

1 2

@

CH1204

22U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1

CH1239

CH1239 10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CSPSM@

2

+1.05V_PCH

CH1220

CH1234

1

2

1

2

1 2

0_0603_5%~D

+3V_PCH

1

+3VS

2

22U_0603_6.3V6M~D

+1.05VS

+V1.05S_AXCK_LCPLL

+1.05VS

1

2

1U_0402_6.3V6K~D

+1.05VS

RH356

1 2

@

0_0603_5%

A00_1004: Change to short pad.

4

+1.05VS_VCCST

12

@

RH4

RH4 10K_0402_5%

10K_0402_5%

12

+VCCIO_OUT

1

1U_0402_6.3V6K~D

2

RC2011.5K_0402_5% RC2011.5K_0402_5%

1

CH1241

0.1U_0402_10V7K~D

2

VR_SVID_ALRT#[47]

1.05VS_VCCST_PG[35]

H_VR_READY[47]

+1.05VS_VCCST

1

CH1205

2

H_VR_READY

VR_SVID_CLK[47] VR_SVID_DAT[47]

VCCSENSE[47]

VR_SVID_ALRT#

VR_ON[47]

H_VR_READY

H_CPU_SVIDCLK

1

EMI@

CC243

CC243 15P_0402_50V8J

15P_0402_50V8J

2

RF Reserved.

+1.05VS

+V1.05VS_VCCHSIO

1

+V1.05S_AUSB3PLL

+V1.05S_ASATA3PLL

CH39

2

+V1.05S_APLLOPI

CH1214

CH1214 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CSPSM@

RH408

@

CH1225

CH1235

+V1.05S_AXCK_LCPLL_L +V1.05S_AXCK_LCPLL

+V1.05A_DCPSUS3

+3VS_AUDIO

1

+V1.05A_DCPSUS2

CH1221

CH1221 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

CSPSM@

+3V_PCH_DSW

1

2

+V1.05S_AXCK_DCB

+V1.05S_AXCK_LCPLL

1

2

L62

1 2

2.2UH_LQM2MPN2R2NG0L_30%

100U_A1_6.3VM_R70M

4

CH65

AA21

W21

AH14

AH13

AC9 AA9

AH10

K19 A20

R21 T21 K18 M20

AE20 AE21

1

+

1U_0402_6.3V6K~D

2

K9

L10

M9 N8

P9 B18 B11

Y20

J13

V8 W9

J18

J17

V21

3

+1.35V_DDR

4.2A

+VCC_CORE

RC97 & RC98 close to PCH

1 2

RC97 100_0402_1%~DRC97 100_0402_1%~D

1 2

RC98 0_0402_1%@RC98 0_0402_1%@

+VCCIO_OUT +VCCIOA_OUT

1 2

RC94 43_0402_5%~DRC94 43_0402_5%~D

1 2

RC92 0_0402_1%@RC92 0_0402_1%@

1 2

RC96 0_0402_1%@RC96 0_0402_1%@

1 2

RC151 0_0402_1%@RC151 0_0402_1%@

1 2

RC152 0_0402_1%@RC152 0_0402_1%@

A00_1004: Change to short pad.

PWR_DEBUG#_XDP[20]

BDW_ULT_DDR3L

1

2

GPIO/LPC

LPT LP POWER

BDW_ULT_DDR3L

HSIO

OPI

USB3

HDA

VRM

UCPU1M@

VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL

RSVD VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3

VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD RSVD RSVD VCCSUS3_3 VCCSUS3_3

DCPSUS can be NC, if INTVRMEN pull up to enable Integrated VRM

+V1.05S_AXCK_LCPLL

CH1231

+1.05VS_VCCST

+VCC_CORE

THERMAL SENSOR

SUS OSCILLATOR

13 OF 19

3

VCCSENSE_R

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

1.05VS_VCCST_PG VR_ON_MCPVR_ON VRPG_MCP

RTC

SPI

CORE

SERIAL IO

USB2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

AH26

AJ31 AJ33

AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50

AC58

AB23

AD23 AA23 AE59

AD60 AD59 AA59 AE60 AC59 AG58

AC22 AE22 AE23

AB57 AD57 AG57

VCCSUS3_3

VCCRTC DCPRTC

VCCSPI

VCCASW VCCASW

VCC1_05 VCC1_05 VCC1_05 VCC1_05

VCC1_05 DCPSUSBYP DCPSUSBYP

VCCASW VCCASW

VCCASW DCPSUS1 DCPSUS1

VCCTS1_5

VCC3_3 VCC3_3

VCCSDIO

DCPSUS4

RSVD VCC1_05 VCC1_05

UCPU1L@

L59

RSVD

J58

RSVD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

F59

VCC

N58

RSVD RSVD

E63

VCC_SENSE RSVD

A59

VCCIO_OUT

E20

VCCIOA_OUT RSVD RSVD RSVD

L62

VIDALERT

N63

VIDSCLK

L63

VIDSOUT

B59

VCCST_PWR GD

F60

VR_EN

C59

VR_READY

D63

VSS

H59

PWR_DEBUG

P62

VSS

P60

RSVD_TP

P61

RSVD_TP

N59

RSVD_TP

N61

RSVD_TP

T59

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

U59

RSVD

V59

RSVD

VCCST VCCST VCCST

VCC VCC VCC

C24

VCC

C28

VCC

C32

VCC

AH11 AG10 AE7

CH1206 0.1U_0402_10V7KCH1206 0.1U_0402_10V7K

Y8

AG14 AG13

J11 H11 H15 AE8 AF22 AG19 AG20 AE9 AF9 AG8 AD10 AD8

J15 K14 K16

U8 T9

AB8

AC20 AG16 AG17

2

BDW_ULT_DDR3L

HSW ULT POWER

12 OF 19

+1.05V_M

+PCH_VCCDSW

1

CH1233

CH1233 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

+RTCVCC

1

2

RH346

RH346 0_0402_1%

0_0402_1%

1 2

@

RH407

1 2

1

0_0603_5%~D

CH1219

CH1219 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CSPSM@

2

1

CH1226

0.1U_0402_10V7K

2

+1.05VS

Compal Secr et Data

@

CH47

0.1U_0402_10V7K~D

CH1218

1 2

1U_0402_6.3V6K~D

+1.05V_PCH

@

+3VS

+RTC_VCCSUS

Deciphered Date

2

+RTC_VCCSUS

1 2

+V1.05A_DCPSUS1

+1.5VS

+VS_LPSS_SDIO

+V1.05A_AOSCSUS

2013/07/04 2013/10/28

C36

VCC

C40

VCC

C44

VCC

C48

VCC

C52

VCC

C56

VCC

E23

VCC

E25

VCC

E27

VCC

E29

VCC

E31

VCC

E33

VCC

E35

VCC

E37

VCC

E39

VCC

E41

VCC

E43

VCC

E45

VCC

E47

VCC

E49

VCC

E51

VCC

E53

VCC

E55

VCC

E57

VCC

F24

VCC

F28

VCC

F32

VCC

F36

VCC

F40

VCC

F44

VCC

F48

VCC

F52

VCC

F56

VCC

G23

VCC

G25

VCC

G27

VCC

G29

VCC

G31

VCC

G33

VCC

G35

VCC

G37

VCC

G39

VCC

G41

VCC

G43

VCC

G45

VCC

G47

VCC

G49

VCC

G51

VCC

G53

VCC

G55

VCC

G57

VCC

H23

VCC

J23

VCC

K23

VCC

K57

VCC

L22

VCC

M23

VCC

M57

VCC

P57

VCC

U57

VCC

W57

VCC

+3.3V_M

CH1215

1U_0402_6.3V6K~D

1

CH1222

CH1222 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

1

2

+VCC_CORE

closed to VCC1P05

1

1U_0402_6.3V6K~D

2

+1.05V_M

SIP

RH341

@

0_0603_5%

CH1207

CH1207 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+V1.05A_AOSCSUS

1

CH1232

CH1232 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CSPSM@

2

1

A00_1004: Change to short pad.

Deep S3 Support

1 2

RH348 @ 0_0603_5%RH348 @ 0_0603_5%

+3VALW +3V_PCH_DSW

CH1224

1U_0402_6.3V6K~D

C1

@

CH1217

1 2

.47U_0402_10V6K

+1.05VS

1

2

+PCH_VCCDSW +3V_PCH_DSW

1

CH1216

10U_0603_6.3V6M~D

2

closed to VCCRTC

1

@

CH1223

CH1223 22U_0603_6.3V6M~D

22U_0603_6.3V6M~D

2

1U_0402_6.3V6K~D

CH84

1

0.1U_0402_10V7K~D

2

A00_1004: Change to short pad.

+3V_PCH

12

+VS_LPSS_SDIO

+1.05V_PCH

L63

@

1 2

2.2UH_LQM2MPN2R2NG0L_30%

1

+

CH61

100U_A1_6.3VM_R70M

CSPSM@

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P13-MCP(9/10) PWR,VCC

LA-B441P

1

2

CH83

RH354

1 2

0_0603_5%

RH350

1 2

0_0603_5%~D

1

CH1227

CH1227 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

1

0.1U_0402_10V7K~D

2

@

13 50Monday, October 06, 2014

CH82

+3VS

+1.8VS

+RTCVCC

1

2

1.0

5

Place a test point pad to within 250 ps of the ROC_TCK pin.and the maximum distance of test point pad to the termination must not be over 200 ps.

CFG3

T293@T293@

4

UCPU1S@

BDW_ULT_DDR3L

3

2

1

CFG3 CFG4

CFG_RCOMP

TD_IREF

UCPU1O@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AC60

CFG0

AC62

CFG1

AC63

CFG2

AA63

CFG3

AA60

CFG4

Y62

CFG5

Y61

CFG6

Y60

CFG7

V62

CFG8

V61

CFG9

V60

CFG10

U60

CFG11

T63

CFG12

T62

CFG13

T61

CFG14

T60

CFG15

AA62

CFG16

U63

CFG18

AA61

CFG17

U62

CFG19

V63

CFG_RCOMP

A5

RSVD

E1

RSVD

D1

RSVD

J20

RSVD

H18

RSVD

B12

TD_IREF

BDW_ULT_DDR3L

15 OF 19

RESERVED

PROC_OPI_RCOMP

19 OF 19

AV59

VSS

AV8

VSS

AW16

VSS

AW24

VSS

AW33

VSS

AW35

VSS

AW37

VSS

AW4

VSS

AW40

VSS

AW42

VSS

AW44

VSS

AW47

VSS

AW50

VSS

AW51

VSS

AW59

VSS

AW60

VSS

AY11

VSS

AY16

VSS

AY18

VSS

AY22

VSS

AY24

VSS

AY26

VSS

AY30

VSS

AY33

VSS

AY4

VSS

AY51

VSS

AY53

VSS

AY57

VSS

AY59

VSS

AY6

VSS

B20

VSS

B24

VSS

B26

VSS

B28

VSS

B32

VSS

B36

VSS

B4

VSS

B40

VSS

B44

VSS

B48

VSS

B52

VSS

B56

VSS

B60

VSS

C11

VSS

C14

VSS

C18

VSS

C20

VSS

C25

VSS

C27

VSS

C38

VSS

C39

VSS

C57

VSS

D12

VSS

D14

VSS

D18

VSS

D2

VSS

D21

VSS

D23

VSS

D25

VSS

D26

VSS

D27

VSS

D29

VSS

D30

VSS

D31

VSS

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

3

CFG0[20] CFG1[20]

D D

12

CFG4

RC811K_0402_1%~D RC811K_0402_1%~D

eDP Strap

1 : Disabled; No Physical Display Port attached to Embedded Display Port

CFG4

0 : Enabled; An external Display

*

Port device is connected to the Embedded Display Port

12

TD_IREF

RC1558.2K_0402_1% RC1558.2K_0402_1%

12

CFG_RCOMP

RC15349.9_0402_1%~D RC15349.9_0402_1%~D

12

PROC_OPI_COMP

AA58 AB10 AB20 AB22

AC61 AD21

AD63 AE10

AE58

AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57

AF11 AF12 AF14 AF15 AF17 AF18

AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

RC15449.9_0402_1%~D RC15449.9_0402_1%~D

BDW_ULT_DDR3L

UCPU1N@

A11

VSS

A14

VSS

A18

VSS

A24

VSS

A28

VSS

A32

VSS

A36

VSS

A40

VSS

A44

VSS

A48

VSS

A52

VSS

A56

VSS

AA1

VSS VSS VSS VSS VSS

AB7

VSS VSS VSS

AD3

VSS VSS VSS

AE5

VSS VSS VSS VSS VSS VSS VSS VSS

AG1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

14 OF 19

AJ35

VSS

AJ39

VSS

AJ41

VSS

AJ43

VSS

AJ45

VSS

AJ47

VSS

AJ50

VSS

AJ52

VSS

AJ54

VSS

AJ56

VSS

AJ58

VSS

AJ60

VSS

AJ63

VSS

AK23

VSS

AK3

VSS

AK52

VSS

AL10

VSS

AL13

VSS

AL17

VSS

AL20

VSS

AL22

VSS

AL23

VSS

AL26

VSS

AL29

VSS

AL31

VSS

AL33

VSS

AL36

VSS

AL39

VSS

AL40

VSS

AL45

VSS

AL46

VSS

AL51

VSS

AL52

VSS

AL54

VSS

AL57

VSS

AL60

VSS

AL61

VSS

AM1

VSS

AM17

VSS

AM23

VSS

AM31

VSS

AM52

VSS

AN17

VSS

AN23

VSS

AN31

VSS

AN32

VSS

AN35

VSS

AN36

VSS

AN39

VSS

AN40

VSS

AN42

VSS

AN43

VSS

AN45

VSS

AN46

VSS

AN48

VSS

AN49

VSS

AN51

VSS

AN52

VSS

AN60

VSS

AN63

VSS

AN7

VSS

AP10

VSS

AP17

VSS

AP20

VSS

C C

B B

A A

Width = 15 mil, Spacing = 15 mil Close PCH within 500 mil

5

CFG2[20] CFG3[20] CFG4[20] CFG5[20] CFG6[20] CFG7[20] CFG8[20] CFG9[20] CFG10[20] CFG11[20] CFG12[20] CFG13[20] CFG14[20] CFG15[20]

CFG16[20] CFG18[20] CFG17[20] CFG19[20]

AP22 AP23 AP26 AP29

AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49

AR5 AR52 AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63

AU1 AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

4

RSVD_TP RSVD_TP

RSVD

RSVD_TP RSVD_TP

RSVD_TP

RSVD

RSVD RSVD

Issued Date

AV63 AU63

C63 C62 B43

A51 B51

L60

N60

W23 Y22 AY15

PROC_OPI_COMP

AV62 D58

P22

VSS

N21

VSS

P20 R20

BDW_ULT_DDR3L

UCPU1P@

D33

VSS

D34

VSS

D35

VSS

D37

VSS

D38

VSS

D39

VSS

D41

VSS

D42

VSS

D43

VSS

D45

VSS

D46

VSS

D47

VSS

D49

VSS

D5

VSS

D50

VSS

D51

VSS

D53

VSS

D54

VSS

D55

VSS

D57

VSS

D59

VSS

D62

VSS

D8

VSS

E11

VSS

E17

VSS

F20

VSS

F26

VSS

F30

VSS

F34

VSS

F38

VSS

F42

VSS

F46

VSS

F50

VSS

F54

VSS

F58

VSS

F61

VSS

G18

VSS

G22

VSS

G3

VSS

G5

VSS

G6

VSS

G8

VSS

H13

VSS

16 OF 19

2013/07/04 2013/10/28

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS_SENSE

VSS

Compal Secr et Data

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63

V58 AH46 V23 E62 AH16

Deciphered Date

RC99 & RC100 close to PCH

1 2

RC100 100_0402_1%~DRC100 100_0402_1%~D

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

VSSSENSE [47]

Compal Electronics, Inc.

P14-MCP(10/10) PWR,VSS,CFG

LA-B441P

1

14 50Saturday, October 04, 2014

1.0

5

4

CHA DDR3L Memory Down Lower Bits

3

2

1

DDR_A_DQS#[0..7][16,7] DDR_A_DQS[0..7][16,7] DDR_A_D[0..31][7] DDR_A_MA[0..15][16,19,7]

UD28

@

UD28

@

M8

VREFCA

H1

VREFDQ

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_MA15

DDR_A_BA0 DDR_A_BA1 DDR_A_BA2

M_CLK_A_ DDR0 M_CLK_A_ DDR#0

DDR_A_CKE0 DDR_A_CKE1 M_ODT0

DDR_A_CS0# DDR_A_CS1#

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS0 DDR_A_DQS1

DDR_A_DQS#0 DDR_A_DQS#1

DDR3_DRAMRST#

RD29 240_0402_1%RD29 240_0402_1%

RD31 240_0402_1%RD31 240_0402_1%

12

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

T7

A14

M7

A15/NC

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE0

J9

CKE1/NC

K1

ODT0

J1

ODT1/NC

L2

CS0#

L1

CS1#/NC

J3

RAS#

K3

CAS#

L3

WE#

F3

DQSL

C7

DQSU

G3

DQSL#

B7

DQSU#

E7

DML

D3

DMU

T2

RESET#

L8

ZQ0

L9

ZQ1/NC

96-BALL

96-BALL SDRAM DDR3L

SDRAM DDR3L

MT41K256 M16HA-125M: E_FBGA96

E3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

DDR_A_D4

F7

DDR_A_D7

F2

DDR_A_D1

F8

DDR_A_D2

H3

DDR_A_D5

H8

DDR_A_D6

G2

DDR_A_D0

H7

DDR_A_D3

D7

DDR_A_D10

C3

DDR_A_D13

C8

DDR_A_D15

C2

DDR_A_D9

A7

DDR_A_D14

A2

DDR_A_D12

B8

DDR_A_D11

A3

DDR_A_D8

+1.35V_DDR +1.35V_DDR

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

+MD_VREF_CA

1

2

.047U_0402_16V7K

CD87

+MD_VREF_DQA

.047U_0402_16V7K

1

2

CD78

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BA0 DDR_A_BA1 DDR_A_BA2

M_CLK_A_ DDR0

M_CLK_A_ DDR#0

DDR_A_CKE0 DDR_A_CKE1 M_ODT0

DDR_A_CS0# DDR_A_CS1#

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS2 DDR_A_DQS3

DDR_A_DQS#2 DDR_A_DQS#3

DDR3_DRAMRST#

RD30 240_0402_1%RD30 240_0402_1%

RD32 240_0402_1%RD32 240_0402_1%

12

UD29

@

UD29

@

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

T7

A14

M7

A15/NC

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE0

J9

CKE1/NC

K1

ODT0

J1

ODT1/NC

L2

CS0#

L1

CS1#/NC

J3

RAS#

K3

CAS#

L3

WE#

F3

DQSL

C7

DQSU

G3

DQSL#

B7

DQSU#

E7

DML

D3

DMU

T2

RESET#

L8

ZQ0

L9

ZQ1/NC

MT41K256 M16HA-125M: E_FBGA96

96-BALL

96-BALL SDRAM DDR3L

SDRAM DDR3L

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

DDR_A_D20 DDR_A_D23 DDR_A_D18 DDR_A_D22 DDR_A_D21

DDR_A_D17

DDR_A_D19 DDR_A_D16

DDR_A_D31 DDR_A_D25 DDR_A_D26 DDR_A_D28 DDR_A_D30 DDR_A_D29 DDR_A_D27 DDR_A_D24

1

2

.047U_0402_16V7K

CD85

+MD_VREF_DQA

.047U_0402_16V7K

1

2

CD77

+MD_VREF_CA +MD_VREF_CA

+MD_VREF_DQA +MD_VREF_DQA

+MD_VREF_CA

D D

at least 20 mils wide with 20 mils spacing to other signals/planes. Short violations are acceptable if required due to tight routing constraints.

DDR3L Package (mm^2)

Hynix

9 x 13

10 x 13Samsung

4G

Micron

C C

B B

9 x 14 10 x 14

PLACE NEAR DRAM

8G

TBD

11 x 13.3

+1.35V_DDR

DDR_A_BA0[16,19,7] DDR_A_BA1[16,19,7] DDR_A_BA2[16,19,7]

M_CLK_A_ DDR0[16,19,7]

M_CLK_A_ DDR#0[16,19,7]

DDR_A_CKE0[16,19,7] DDR_A_CKE1[16,19,7]

M_ODT0[16,19]

DDR_A_CS0#[16,19,7] DDR_A_CS1#[16,19,7]

DDR_A_RAS#[16,19,7] DDR_A_CAS#[16,19,7]

DDR_A_WE#[16,19,7]

RD24

RD24 470_0402_5%~D

470_0402_5%~D

A00_1004: Change to short pad.

1 2

RD28

RD28 0_0402_1%

0_0402_1%

1 2

@

H_DRAMRST#[6]

A A

5

@

DDR3_DRAMRST# [16,17,18]

0.1U_0402_25V6K~D

@

1

CD5

2

4

+1.35V_DDR +1.35V_DDR

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CD66

CD67

1

2

CD67

12

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1

12

CD69

CD68

2

Compal Secret Data

2013/07/04 2013/10/28

3

Compal Secret Data

Deciphered Date

2

1U_0402_6.3V6K~D

CD70

1

2

Title

P12-DDRIII Channel A

Size Document Number Rev

LA-B441P

Date: Sheet of

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CD71

12

Compal Electronics, Inc.

10U_0603_6.3V6M~D

CD72

CD73

1

2

CD73

12

15 50Sunday, October 05, 2014

1

1.0

5

CHA DDR3L Memory Down Upper Bits

4

3

2

1

D D

+MD_VREF_CA +MD_VREF_CA

+MD_VREF_DQA +MD_VREF_DQA

+MD_VREF_DQA +MD_VREF_DQA+MD_VREF_CA +MD_VREF_CA

.047U_0402_16V7K

DDR_A_DQS#[0..7][15,7]

DDR_A_DQS[0..7][15,7]

DDR_A_D[32..63][7]

DDR_A_MA[0..15][15,19,7]

All VREF traces should have 10 mil trace width

C C

B B

1

2

.047U_0402_16V7K

1

CD88

2

DDR_A_BA0[15,19,7] DDR_A_BA1[15,19,7] DDR_A_BA2[15,19,7]

M_CLK_A_DDR0[15,19,7]

M_CLK_A_DDR#0[15,19,7]

DDR_A_CKE0[15,19,7] DDR_A_CKE1[15,19,7]

M_ODT0[15,19]

DDR_A_CS0#[15,19,7] DDR_A_CS1#[15,19,7]

DDR_A_RAS#[15,19,7] DDR_A_CAS#[15,19,7]

DDR_A_WE#[15,19,7]

DDR3_DRAMRST#[15,17,18]

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5

DDR_A_MA6

CD93

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11

DDR_A_MA12

DDR_A_MA13

DDR_A_MA14

DDR_A_MA15 DDR_A_MA15

DDR_A_BA0

DDR_A_BA1

DDR_A_BA2

M_CLK_A_DDR0

M_CLK_A_DDR#0

DDR_A_CKE0 DDR_A_CKE1

M_ODT0

DDR_A_CS0#

DDR_A_CS1#

DDR_A_RAS#

DDR_A_CAS#

DDR_A_WE#

DDR_A_DQS4

DDR_A_DQS5

DDR_A_DQS#4

DDR_A_DQS#5

DDR3_DRAMRST#

12

RD51 240_0402_1%RD51 240_0402_1%

12

RD53 240_0402_1%RD53 240_0402_1%

UD31

@

UD31

@

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

T7

A14

M7

A15/NC

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE0

J9

CKE1/NC

K1

ODT0

J1

ODT1/NC

L2

CS0#

L1

CS1#/NC

J3

RAS#

K3

CAS#

L3

WE#

F3

DQSL

C7

DQSU

G3

DQSL#

B7

DQSU#

E7

DML

D3

DMU

T2

RESET#

L8

ZQ0

L9

ZQ1/NC

96-BALL

96-BALL SDRAM DDR3L

SDRAM DDR3L

MT41K256M16HA-125M:E_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

UD32

@

UD32

E3

DDR_A_D33

F7

DDR_A_D39

F2

DDR_A_D36

F8

DDR_A_D34

H3

DDR_A_D32

H8

DDR_A_D38

G2

DDR_A_D37

H7

DDR_A_D35

D7

DDR_A_D43

C3

DDR_A_D44

C8

DDR_A_D46

C2

DDR_A_D41

A7

DDR_A_D47

A2

DDR_A_D40

B8

DDR_A_D42

A3

DDR_A_D45

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

.047U_0402_16V7K

1

2

.047U_0402_16V7K

1

CD94

CD89

CD94

2

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BA0 DDR_A_BA1 DDR_A_BA2

M_CLK_A_DDR0 M_CLK_A_DDR#0

DDR_A_CKE0 DDR_A_CKE1

M_ODT0

DDR_A_CS0# DDR_A_CS1#

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS6 DDR_A_DQS7

DDR_A_DQS#6 DDR_A_DQS#7

DDR3_DRAMRST#

12

RD52 240_0402_1%RD52 240_0402_1%

12

RD55 240_0402_1%RD55 240_0402_1%

@

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

T7

A14

M7

A15/NC

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE0

J9

CKE1/NC

K1

ODT0

J1

ODT1/NC

L2

CS0#

L1

CS1#/NC

J3

RAS#

K3

CAS#

L3

WE#

F3

DQSL

C7

DQSU

G3

DQSL#

B7

DQSU#

E7

DML

D3

DMU

T2

RESET#

L8

ZQ0

L9

ZQ1/NC

96-BALL

96-BALL SDRAM DDR3L

SDRAM DDR3L

MT41K256M16HA-125M:E_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

DDR_A_D52

F7

DDR_A_D51

F2

DDR_A_D50

F8

DDR_A_D53

H3

DDR_A_D49

H8

DDR_A_D55

G2

DDR_A_D48

H7

DDR_A_D54

D7

DDR_A_D61

C3

DDR_A_D62

C8

DDR_A_D57

C2

DDR_A_D63

A7

DDR_A_D60

A2

DDR_A_D59

B8

DDR_A_D56

A3

DDR_A_D58

+1.35V_DDR+1.35V_DDR

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

+1.35V_DDR +1.35V_DDR+1.35V_DDR +1.35V_DDR

A A

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

CD80

CD79

1

12

2

5

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

CD81

CD82

1

12

2

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

CD83

CD92

1

12

2

4

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

CD86

CD84

1

12

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

3

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P13-DDRIII Channel A

LA-B441P

1

16 50Saturday, October 04, 2014

1.0

5

4

3

2

1

CHB DDR3L Memory Down Lower Bits

UD1

@

UD1

@

+MD_VREF_CA

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3

DDR_B_MA4

.047U_0402_16V7K

DDR_B_MA5

DDR_B_MA6

CD35

DDR_B_MA7

DDR_B_MA8

DDR_B_MA9

DDR_B_MA10

DDR_B_MA11

DDR_B_MA12

DDR_B_MA13

DDR_B_MA14

DDR_B_MA15

DDR_B_BA0

DDR_B_BA1

DDR_B_BA2

M_CLK_B_DDR0

M_CLK_B_DDR#0

DDR_B_CKE0

DDR_B_CKE1

M_ODT2

M_ODT2[18,19]

DDR_B_CS0#

DDR_B_CS1#

DDR_B_RAS#

DDR_B_CAS#

DDR_B_WE#

DDR_B_DQS2

DDR_B_DQS3

DDR_B_DQS#2

DDR_B_DQS#3

DDR3_DRAMRST#

RD11 240_0402_1%RD11 240_0402_1%

RD17 240_0402_1%RD17 240_0402_1%

12

1

2

.047U_0402_16V7K

CD90

+MD_VREF_DQB

1

2

DDR_B_BA0[18,19,7] DDR_B_BA1[18,19,7] DDR_B_BA2[18,19,7]

M_CLK_B_DDR0[18,19,7]

M_CLK_B_DDR#0[18,19,7]

DDR_B_CKE0[18,19,7] DDR_B_CKE1[18,19,7]

DDR_B_CS0#[18,19,7]

DDR_B_CS1#[18,19,7]

DDR_B_RAS#[18,19,7] DDR_B_CAS#[18,19,7]

DDR_B_WE#[18,19,7]

DDR3_DRAMRST#[15,16,18]

+MD_VREF_CA

D D

DDR_B_DQS#[0..7][18,7] DDR_B_DQS[0..7][18,7] DDR_B_D[0..31][7] DDR_B_MA[0..15][18,19,7]

C C

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

T7

A14

M7

A15/NC

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE0

J9

CKE1/NC

K1

ODT0

J1

ODT1/NC

L2

CS0#

L1

CS1#/NC

J3

RAS#

K3

CAS#

L3

WE#

F3

DQSL

C7

DQSU

G3

DQSL#

B7

DQSU#

E7

DML

D3

DMU

T2

RESET#

L8

ZQ0

L9

ZQ1/NC

96-BALL

96-BALL SDRAM DDR3L

SDRAM DDR3L

MT41K256M16HA-125M:E_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

DDR_B_D20

F7

DDR_B_D22

F2

DDR_B_D21

F8

DDR_B_D18

H3

DDR_B_D17

H8

DDR_B_D19

G2

DDR_B_D16

H7

DDR_B_D23

D7

DDR_B_D27

C3

DDR_B_D28

C8

DDR_B_D30

C2

DDR_B_D29

A7

DDR_B_D26

A2

DDR_B_D25

B8

DDR_B_D31

A3

DDR_B_D24

+1.35V_DDR

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

+MD_VREF_CA

1

2

.047U_0402_16V7K

CD91

+MD_VREF_CA+MD_VREF_DQB

+MD_VREF_DQB

.047U_0402_16V7K

1

2

CD37

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_B_BA0 DDR_B_BA1 DDR_B_BA2

M_CLK_B_DDR0 M_CLK_B_DDR#0

DDR_B_CKE0 DDR_B_CKE1 M_ODT2

DDR_B_CS0# DDR_B_CS1#

DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

DDR_B_DQS0 DDR_B_DQS1

DDR_B_DQS#0 DDR_B_DQS#1

DDR3_DRAMRST#

12

RD12 240_0402_1%RD12 240_0402_1%

12

RD19 240_0402_1%RD19 240_0402_1%

UD7

@

UD7

@

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

T7

A14

M7

A15/NC

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE0

J9

CKE1/NC

K1

ODT0

J1

ODT1/NC

L2

CS0#

L1

CS1#/NC

J3

RAS#

K3

CAS#

L3

WE#

F3

DQSL

C7

DQSU

G3

DQSL#

B7

DQSU#

E7

DML

D3

DMU

T2

RESET#

L8

ZQ0

L9

ZQ1/NC

96-BALL

96-BALL SDRAM DDR3L

SDRAM DDR3L

MT41K256M16HA-125M:E_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

DDR_B_D5

F7

DDR_B_D6

F2

DDR_B_D0

F8

DDR_B_D3

H3

DDR_B_D4

H8

DDR_B_D7

G2

DDR_B_D1

H7

DDR_B_D2

D7

DDR_B_D13

C3

DDR_B_D12

C8

DDR_B_D15

C2

DDR_B_D9

A7

DDR_B_D11

A2

DDR_B_D8

B8

DDR_B_D10

A3

DDR_B_D14

+1.35V_DDR

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

B B

+1.35V_DDR

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CD40

CD41

1

A A

12

2

5

10U_0603_6.3V6M~D

CD42

CD45

1

12

2

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CD44

CD50

1

12

2

4

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CD46

CD47

1

12

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

3

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P14-DDRIII Channel B

LA-B441P

1

17 50Saturday, October 04, 2014

1.0

5

4

3

2

1

CHB DDR3L Memory Down Upper Bits

UD4

@

UD4

UD3

@

UD3

@

D D

DDR_B_DQS#[0..7][17,7]

DDR_B_DQS[0..7][17,7]

DDR_B_D[32..63][7]

DDR_B_MA[0..15][17,19,7]

All VREF traces should have 10 mil trace width

C C

+MD_VREF_CA +MD_VREF_CA

+MD_VREF_DQB +MD_VREF_DQB

+MD_VREF_DQB +MD_VREF_DQB+MD_VREF_CA +MD_VREF_CA

.047U_0402_16V7K

1

2

.047U_0402_16V7K

1

CD95

2

DDR_B_BA0[17,19,7] DDR_B_BA1[17,19,7] DDR_B_BA2[17,19,7]

M_CLK_B_DDR0[17,19,7]

M_CLK_B_DDR#0[17,19,7]

DDR_B_CKE0[17,19,7] DDR_B_CKE1[17,19,7]

M_ODT2[17,19]

DDR_B_CS0#[17,19,7] DDR_B_CS1#[17,19,7]

DDR_B_RAS#[17,19,7] DDR_B_CAS#[17,19,7]

DDR_B_WE#[17,19,7]

DDR3_DRAMRST#[15,16,17]

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5

DDR_B_MA6

CD51

DDR_B_MA7

DDR_B_MA8

DDR_B_MA9

DDR_B_MA10

DDR_B_MA11

DDR_B_MA12

DDR_B_MA13

DDR_B_MA14

DDR_B_MA15 DDR_B_MA15

DDR_B_BA0

DDR_B_BA1

DDR_B_BA2

M_CLK_B_DDR0

M_CLK_B_DDR#0

DDR_B_CKE0

DDR_B_CKE1

M_ODT2

DDR_B_CS0#

DDR_B_CS1#

DDR_B_RAS#

DDR_B_CAS#

DDR_B_WE#

DDR_B_DQS4

DDR_B_DQS5

DDR_B_DQS#4

DDR_B_DQS#5

DDR3_DRAMRST#

12

RD41 240_0402_1%RD41 240_0402_1%

12

RD42 240_0402_1%RD42 240_0402_1%

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

T7

A14

M7

A15/NC

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE0

J9

CKE1/NC

K1

ODT0

J1

ODT1/NC

L2

CS0#

L1

CS1#/NC

J3

RAS#

K3

CAS#

L3

WE#

F3

DQSL

C7

DQSU

G3

DQSL#

B7

DQSU#

E7

DML

D3

DMU

T2

RESET#

L8

ZQ0

L9

ZQ1/NC

96-BALL

96-BALL SDRAM DDR3L

SDRAM DDR3L

MT41K256M16HA-125M:E_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

DDR_B_D32

F7

DDR_B_D35

F2

DDR_B_D33

F8

DDR_B_D39

H3

DDR_B_D37

H8

DDR_B_D34

G2

DDR_B_D36

H7

DDR_B_D38

D7

DDR_B_D43

C3

DDR_B_D41

C8

DDR_B_D46

C2

DDR_B_D40

A7

DDR_B_D47

A2

DDR_B_D44

B8

DDR_B_D42

A3

DDR_B_D45

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

.047U_0402_16V7K

1

2

1

CD96

2

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3

DDR_B_MA4

.047U_0402_16V7K

DDR_B_MA5

DDR_B_MA6

CD52

DDR_B_MA7

DDR_B_MA8

DDR_B_MA9

DDR_B_MA10

DDR_B_MA11

DDR_B_MA12

DDR_B_MA13

DDR_B_MA14

DDR_B_BA0

DDR_B_BA1

DDR_B_BA2

M_CLK_B_DDR0

M_CLK_B_DDR#0

DDR_B_CKE0

DDR_B_CKE1

M_ODT2

DDR_B_CS0#

DDR_B_CS1#

DDR_B_RAS#

DDR_B_CAS#

DDR_B_WE#

DDR_B_DQS6

DDR_B_DQS7

DDR_B_DQS#6

DDR_B_DQS#7

DDR3_DRAMRST#

RD54 240_0402_1%RD54 240_0402_1%

RD56 240_0402_1%RD56 240_0402_1%

12

@

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

T7

A14

M7

A15/NC

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE0

J9

CKE1/NC

K1

ODT0

J1

ODT1/NC

L2

CS0#

L1

CS1#/NC

J3

RAS#

K3

CAS#

L3

WE#

F3

DQSL

C7

DQSU

G3

DQSL#

B7

DQSU#

E7

DML

D3

DMU

T2

RESET#

L8

ZQ0

L9

ZQ1/NC

96-BALL

96-BALL SDRAM DDR3L

SDRAM DDR3L

MT41K256M16HA-125M:E_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

DDR_B_D48

F7

DDR_B_D51

F2

DDR_B_D53

F8

DDR_B_D55

H3

DDR_B_D52

H8

DDR_B_D54

G2

DDR_B_D49

H7

DDR_B_D50

D7

DDR_B_D63

C3

DDR_B_D60

C8

DDR_B_D59

C2

DDR_B_D61

A7

DDR_B_D62

A2

DDR_B_D57

B8

DDR_B_D58

A3

DDR_B_D56

+1.35V_DDR+1.35V_DDR

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

B B

+1.35V_DDR +1.35V_DDR+1.35V_DDR +1.35V_DDR

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CD54

CD55

1

A A

12

2

5

10U_0603_6.3V6M~D

CD56

CD57

1

12

2

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CD58

CD59

1

12

2

4

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CD60

CD61

1

12

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

3

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P15-DDRIII Channel B

LA-B441P

1

18 50Saturday, October 04, 2014

1.0

5

D D

4

3

+0.675VS +0.675VS

DDR_A_MA12 DDR_A_MA15 DDR_A_MA0 DDR_A_MA10

1 2

RD25 34.8_0402_1%~DRD25 34.8_0402_1%~D

1 2

RD27 34.8_0402_1%~DRD27 34.8_0402_1%~D

1 2

RD63 34.8_0402_1%~DRD63 34.8_0402_1%~D

1 2

RD36 34.8_0402_1%~DRD36 34.8_0402_1%~D

2

DDR_B_MA12 DDR_B_MA15 DDR_B_MA0 DDR_B_MA10

1 2

RD26 34.8_0402_1%~DRD26 34.8_0402_1%~D

1 2

RD74 34.8_0402_1%~DRD74 34.8_0402_1%~D

1 2

RD94 34.8_0402_1%~DRD94 34.8_0402_1%~D

1 2

RD100 34.8_0402_1%~DRD100 34.8_0402_1%~D

1

DDR_A_MA4 DDR_A_MA2 DDR_A_MA1 DDR_A_MA6

DDR_A_MA3 DDR_A_MA9 DDR_A_MA11 DDR_A_MA5

DDR_A_MA14 DDR_A_MA7

DDR_A_MA[0..15][15,16,7]

DDR_B_MA[0..15][17,18,7]

C C

+0.675VS

1U_0402_6.3V6K~D

CD129

1U_0402_6.3V6K~D

1

CD132

2

1

CD133

2

CD135

1U_0402_6.3V6K~D

1

2

15P_0402_50V8J

10U_0603_6.3V6M~D

CD101

1

12

@

CD143

2

DDR_A_CKE0[15,16,7] DDR_A_RAS#[15,16,7] DDR_A_CS0#[15,16,7] DDR_A_CAS#[15,16,7]

DDR_A_WE#[15,16,7] DDR_A_BA0[15,16,7] DDR_A_BA2[15,16,7] DDR_A_BA1[15,16,7]

DDR_A_CKE1[15,16,7] DDR_A_CS1#[15,16,7]

DDR_A_MA8 DDR_A_MA13

RF Reserved.

+0.675VS

15P_0402_50V8J

1U_0402_6.3V6K~D

CD139

1U_0402_6.3V6K~D

1

CD140

2

1

CD136

2

B B

1U_0402_6.3V6K~D

CD142

1

@

CD144

2

RF Reserved.

M_ODT0[15,16] M_ODT2[17,18]

M_CLK_A_DDR0[15,16,7] M_CLK_A_DDR#0[15,16,7]

1 2

RD33 34.8_0402_1%~DRD33 34.8_0402_1%~D

1 2

RD66 34.8_0402_1%~DRD66 34.8_0402_1%~D

1 2

RD37 34.8_0402_1%~DRD37 34.8_0402_1%~D

1 2

RD86 34.8_0402_1%~DRD86 34.8_0402_1%~D

1 2

RD45 34.8_0402_1%~DRD45 34.8_0402_1%~D

1 2

RD83 34.8_0402_1%~DRD83 34.8_0402_1%~D

1 2

RD59 34.8_0402_1%~DRD59 34.8_0402_1%~D

1 2

RD47 34.8_0402_1%~DRD47 34.8_0402_1%~D

1 2

RD50 34.8_0402_1%~DRD50 34.8_0402_1%~D

1 2

RD85 34.8_0402_1%~DRD85 34.8_0402_1%~D

1 2

RD98 34.8_0402_1%~DRD98 34.8_0402_1%~D

1 2

RD72 34.8_0402_1%~DRD72 34.8_0402_1%~D

1 2

RD69 34.8_0402_1%~DRD69 34.8_0402_1%~D

1 2

RD79 34.8_0402_1%~DRD79 34.8_0402_1%~D

1 2

RD61 34.8_0402_1%~DRD61 34.8_0402_1%~D

1 2

RD97 34.8_0402_1%~DRD97 34.8_0402_1%~D

1 2

RD65 34.8_0402_1%~DRD65 34.8_0402_1%~D

1 2

RD67 34.8_0402_1%~DRD67 34.8_0402_1%~D

1 2

RD82 34.8_0402_1%~DRD82 34.8_0402_1%~D

1 2

RD99 34.8_0402_1%~DRD99 34.8_0402_1%~D

1 2

RD87 34.8_0402_1%~DRD87 34.8_0402_1%~D

1 2

RD88 34.8_0402_1%~DRD88 34.8_0402_1%~D

1 2

RD92 30_0402_1%~DRD92 30_0402_1%~D

1 2

RD75 26.1_0402_1%~DRD75 26.1_0402_1%~D

1 2

RD77 26.1_0402_1%~DRD77 26.1_0402_1%~D

DDR_B_MA14 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2

DDR_B_MA8 DDR_B_MA1 DDR_B_MA13 DDR_B_MA7

DDR_B_MA3 DDR_B_MA9 DDR_B_MA11 DDR_B_MA5

DDR_B_CKE0[17,18,7] DDR_B_CS0#[17,18,7] DDR_B_CAS#[17,18,7] DDR_B_RAS#[17,18,7]

DDR_B_BA1[17,18,7] DDR_B_BA2[17,18,7] DDR_B_BA0[17,18,7] DDR_B_WE#[17,18,7]

DDR_B_CKE1[17,18,7] DDR_B_CS1#[17,18,7]

+1.35V_DDR +1.35V_DDR

+0.675VS +0.675VS

M_CLK_B_DDR0[17,18,7] M_CLK_B_DDR#0[17,18,7]

1 2

RD35 34.8_0402_1%~DRD35 34.8_0402_1%~D

1 2

RD73 34.8_0402_1%~DRD73 34.8_0402_1%~D

1 2

RD38 34.8_0402_1%~DRD38 34.8_0402_1%~D

1 2

RD49 34.8_0402_1%~DRD49 34.8_0402_1%~D

1 2

RD84 34.8_0402_1%~DRD84 34.8_0402_1%~D

1 2

RD91 34.8_0402_1%~DRD91 34.8_0402_1%~D

1 2

RD46 34.8_0402_1%~DRD46 34.8_0402_1%~D

1 2

RD48 34.8_0402_1%~DRD48 34.8_0402_1%~D

1 2

RD96 34.8_0402_1%~DRD96 34.8_0402_1%~D

1 2

RD57 34.8_0402_1%~DRD57 34.8_0402_1%~D

1 2

RD71 34.8_0402_1%~DRD71 34.8_0402_1%~D

1 2

RD93 34.8_0402_1%~DRD93 34.8_0402_1%~D

1 2

RD58 34.8_0402_1%~DRD58 34.8_0402_1%~D

1 2

RD60 34.8_0402_1%~DRD60 34.8_0402_1%~D

1 2

RD62 34.8_0402_1%~DRD62 34.8_0402_1%~D

1 2

RD64 34.8_0402_1%~DRD64 34.8_0402_1%~D

1 2

RD80 34.8_0402_1%~DRD80 34.8_0402_1%~D

1 2

RD68 34.8_0402_1%~DRD68 34.8_0402_1%~D

1 2

RD70 34.8_0402_1%~DRD70 34.8_0402_1%~D

1 2

RD81 34.8_0402_1%~DRD81 34.8_0402_1%~D

1 2

RD89 34.8_0402_1%~DRD89 34.8_0402_1%~D

1 2

RD90 34.8_0402_1%~DRD90 34.8_0402_1%~D

1 2

RD95 30_0402_1%~DRD95 30_0402_1%~D

1 2

RD76 26.1_0402_1%~DRD76 26.1_0402_1%~D

1 2

RD78 26.1_0402_1%~DRD78 26.1_0402_1%~D

Channel A DQ VREFChannel B DQ VREFChannel A/B CA VREF

+1.35V_DDR+MD_VREF_DQA+1.35V_DDR+M D_VREF_DQB+1.35V_DDR+MD_VREF_CA

12

RD13

1.8K_0402_1%

RD15

2.7_0402_1%~D

1 2

12

RD16

1.8K_0402_1%

A A

Place the VREF voltage dividers as close as possible to the SO-DIMMs or memory down DRAM devices.

1

CD43

0.022U_0402_16V7K~D

2

12

RD40

24.9_0402_1%

Place the VREF voltage dividers as close as possible to the SO-DIMMs or memory down DRAM devices.

12

RD14

1.8K_0402_1%

RD20

4.99_0402_1%~D

1 2

RD18

1.8K_0402_1%

1

CD39

0.022U_0402_16V7K~D

2

12

RD39

24.9_0402_1%

Place the VREF voltage dividers as close as possible to the SO-DIMMs or memory down DRAM devices.

12

RD34

1.8K_0402_1%

1 2

12

RD119

1.8K_0402_1%

RD121

4.99_0402_1%~D

1

CD76

0.022U_0402_16V7K~D

2

12

RD120

24.9_0402_1%

V_DDR_REF_DQA [7]V_DDR_REF_DQB [7]V_DDR_REF_CA [7]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

3

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P16-DDRIII Channel B

LA-B441P

1

19 50Saturday, October 04, 2014

1.0

5

JXDP

1

GND0

XDP_PRE Q# XDP_PRD Y#

CFG0[14] CFG1[14]

D D

C C

B B

CFG2[14] CFG3[14]

XDP_BPM1 #[6]

CFG4[14] CFG5[14]

CFG6[14] CFG7[14]

PCH_SMBDATA[8] PCH_SMBCLK[8]

+1.05VS

1

XDP@

CH1

0.1U_0402_25V6K~D

2

PCH_PLTRST#_EC[11,23,27,28,36]

CFG3

XDP_PW RGD PWRBTN#_XDP

PWR_DEBUG#_XDP PCH_SYS_PWROK_XDP

XDP_TCK1 XDP_TCK0

HOCK0 [39] HOCK6 [46]

XDP_PW RGD

XDP_PW RGD[13]

XDP@

RH363

RH363 1K_0402_5%

1K_0402_5%

1 2

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

CONN@

XDP_TDOPLTRST#_XDP

4

GND1 OBSFN_C0 OBSFN_C1

GND3

OBSDATA_C0 OBSDATA_C1

GND5

OBSDATA_C2 OBSDATA_C3

GND7 OBSFN_D0 OBSFN_D1

GND9

OBSDATA_D0 OBSDATA_D1

GND11 OBSDATA_D2 OBSDATA_D3

GND13

ITPC LK/HOO K4

ITPC LK#/HO OK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TD0

TRST#

TMS

GND17

+1.05VS+1.05VS

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56

TDI

58 60

Route wiht minimal of stub of XDP_PIN60

CFG17 [14] CFG16 [14]

CFG8 [14] CFG9 [14]

CFG10 [14] CFG11 [14]

CFG19 [14]XDP_BPM0 #[6] CFG18 [14]

CFG12 [14] CFG13 [14]

CFG14 [14] CFG15 [14]

PLTRST#_XDP SYS_RESET#_XDP

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS XDP_PIN6 0

XDP@

J1d

1 2

RH373 0_0402_5%

@

J1s

1 2

RH411 0_0402_5%

XDP@

J2d

1 2

RH374 0_0402_5%

XDP@

Rs5

1 2

RH446 0_0402_5%

XDP@

J4d

1 2

RH414 0_0402_5%

XDP@

1 2

RH371 0_0402_5%

HOOK1 (41)

PWRBTN#_XDP

HOOK2 (45)

PWR_DEBUG#_XDP

HOOK3 (47)

PCH_SYS_PWROK_XDP

HOOK7 (48)

SYS_RESET#_XDP

OBSFN_A[0] (3)

XDP_PRE Q#

OBSFN_A[1] (5)

XDP_PRD Y#

Pin_60 [60]

XDP_PIN6 0

CFG3

TRST_N (54)TMS (58)TCK1 (55)TCK0 (57)TDI (58)TDO (52)

XDP_TRST#XDP_TMSXDP_ TCK1XDP_TC K0XDP_TD I

XDP_TDI_S WITCH

3

+3V_PCH +1.05VS_VCCST

12

@

R1312

R1312 3K_0402_5%~D

3K_0402_5%~D

Place CA,CB near CPU XDP Connector

XDP@

1 2

R1198 1K_0402_5%~D

+3V_PCH

XDP@

U663

16

VCC

4

1B

7

2B

10

3B

13

4B

1

NC

9

NC

74CBTLV3126DS_SSOP16

@

1 2

RH412 0_0402_5%

@

1 2

RH413 0_0402_5%

XDP@

1 2

RH369 0_0402_5%

12

XDP@

R1179

R1179 150_0402_5%~D

150_0402_5%~D

CPU_PATH_EN

S1

S2

S3

S4

GND

J2s J3s J3d

1OE

2OE

3OE

4OE

2

+3VS+3VS

12

@

R1311

R1311 3K_0402_5%~D

3K_0402_5%~D

1

XDP@

C1282

0.1U_0402_10V7K

2

3

1A

5

6

2A

12

11

3A

15

14

4A

8

12

RH367

RH367 1K_0402_5%

1K_0402_5%

1

XDP@

C1237

0.1U_0402_10V7K

2

XDP@

1 2

RH21 0_0402_5%

A00_1004: Remove BoM Structure of RH451, RH367 and C1237.

@

1 2

RH444 0_0402_5%

XDP@

1 2

R1309 0_0402_5%

1 2

RH451 0_0402_5%RH451 0_0402_5%

XDP@

1 2

RH370 0_0402_5%

+3V_PCH

@

1

CH1236

0.1U_0402_25V6K~D

2

XDP@

1 2

RH372 0_0402_5%

1

PBTN_SW# [21,23,36]

SIO_PWRBTN# [11,20,36]

EC

PWRBTN# (AL7)

SIO_PWRBTN# [11,20,36]

PWR_DEBUG# (H59)

PWR_DEBUG#_XDP [13]

PCH_SYS_PWROK (AG2)

SYS_PWROK [11,36]

SYS_RESET (AC3)

PM_SYS_RESET# [11,21 ]

CPU

XDP_PRE Q# [6]

XDP_PRD Y# [6]

CPU_XDP_TRST# [6]

ODT

CPU_XDP_TMS [6]

CPU_XDP_TCK [6]

ODT

CPU_XDP_TDI [6]

CPU_XDP_TDO [6]

ODT

PCH_JTAG_TRST# [9]

PCH

PCH_JTAG_TMS [9]

ODT

PCH_JTAG_TCK [9]

ODT

PCH_JTAG_JTAGX [9]

PCH_JTAG_TDI [9]

PCH_JTAG_TDO [9]

+3V_PCH+3V_PCH

12

XDP@

R1324

R1324 10K_0402_5%~D

10K_0402_5%~D

A A

12

@

R1325

R1325 10K_0402_5%~D

10K_0402_5%~D

RUNPWROK[36]

5

1

VCC

IN1

2

IN2

4

CPU_PATH_EN

OUT

XDP@

U697

GND

MC74VHC 1G08DFT2G_ SC70-5

3

1. Place FET Switch (S1,S2,S3,S4) and 0 ohm resistors (J1s,J1d,J2d,J2s,J3d,J3s,J4d,RS5) to within 200 ps of respective XDP pins.

2. Stubs on TCK1,TCK0 and TMS nets should not be more than 200 ps.

3. XDP test point pads recommended to layout within 2x2 area around the XDP connector layout.

4. The stub between J1d and J1s should not be more than 200 ps.

5. The stub between J1s and J2d should not be more than 200 ps.

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/07/04 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P17-XDP,APS,Debug CONN

LA-B441P

20 50Monday, O ctober 0 6, 2014

1

1.0

5

D D

4

3

2

1

A00_1004: Depop SW4, RC9; pop R1191.

Service Mode Switch: Add a switch to ME_FWP signal to unlock the ME region and allow the entire region of the SPI flash to be updated using FPT.

APS CONN

+3V_PCH

SIO_SLP_S3#[11,36,44,46]

+3VALW

SIO_SLP_S5#[11,36] SIO_SLP_S4#[11,36] SIO_SLP_A#[11,36]

C C

+3VALW

PCH_RTCRST#[9]

PBTN_SW#[20,23,36]

PM_SYS_RESET#[11,20]

PM_SLP_S0#[11,45]

JAPS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

GND

20

GND

CONN@

ACES_50506-01841-P01

I2S_SDOUT[9]

ME_FWP_EC[36]

ME_FWP PCH has internal 20K PD.

FLASH DESCRIPTOR SECURITY OVERRIDE

Disable ME Protect (ME can be updated) ----> Pin1 & Pin2 short Enable ME Protect (ME cannot be updated)-->Pin3 & Pin2 short(Default position)

+3VS_AUDIO

12

RC9

@

1K_0402_5%

SW4

@

SW4

@

ME_EN

1 2 3

4

G

5

G

SSAL120100_3P

12

RH241K_0402_5%~D RH241K_0402_5%~D

12

R11910_0402_5%~D R11910_0402_5%~D

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

3

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P18-BLANK

LA-B441P

1

21 50Monday, October 06, 2014

1.0

5

Camera + Touch Screen

1 2

CAM_CBL_DET#[11]

Camera

USB20_P4[12]

D D

USB20_N4[12]

Touch Screen

USB20_P3[12]

USB20_N3[12]

C C

RH438 1K_0402_5%~DRH438 1K_0402_5%~D

1 2

R1004 0_0402_5%~D@ R1004 0_0402_5%~D@

L55 EMI@

4

1

1 2

ML9 EMI@

4

1

1 2

3

2

3

2

1

DLW21HN900HQ2L_4P

R1005 0_0402_5%~D@ R1005 0_0402_5%~D@

R1013 0_0402_5%~D@ R1013 0_0402_5%~D@

4

1

DLW21HN900HQ2L_4P

R1012 0_0402_5%~D@ R1012 0_0402_5%~D@

CAM_CBL_DET#_R

3

USB20_P4_CONN

2

USB20_N4_CONN

3

USB20_P3_CONN

2

USB20_N3_CONN

2

3

EMI@DI3

EMI@

DI3

1

L30ESDL5V0C3-2_SOT23-3

2

3

EMI@DI4

EMI@

DI4

1

L30ESDL5V0C3-2_SOT23-3

USB20_P4_CONN USB20_N4_CONN

CAM_CBL_DET#_R

+3VS_CAM

USB20_P3_CONN USB20_N3_CONN

TOUCH_PANEL_INTR#[11]

+3VS_TSLDO

4

EMI@

1

C4

C1221

2

1U_0402_6.3V6K~D

EMI@

1

C5

C1222

2

1U_0402_6.3V6K~D

15P_0402_50V8J

JCAM

8

GND

7

GND

6

5

4

3

2

1

CVILU_CI1806M2HRP-NH

CONN@

JTS

1

2

3

4

5

6

7

GND

8

GND

CVILU_CI1806M2HRP-NH

CONN@

eDP Conn

eDP_TXP_P0[5]

eDP_TXN_P0[5]

eDP_TXP_P1[5]

eDP_TXN_P1[5]

eDP_TXP_P2[5]

eDP_TXN_P2[5]

eDP_TXP_P3[5]

eDP_TXN_P3[5]

eDP_AUXN[5]

eDP_AUXP[5]

0.1U_0402_10V7K

C1060

C1062

0.1U_0402_10V7K

C1061

C1063

0.1U_0402_10V7K

C1067

C1066

0.1U_0402_10V7K

C1069

C1068

0.1U_0402_10V7K

C1065

0.1U_0402_10V7K

C1064

0.1U_0402_10V7K

3

1 2

2

L57 EMI@

eDP_TXP_P0_C

eDP_TXN_P0_C

eDP_TXP_P1_C eDP_TXP_P1_CON N

eDP_TXN_P1_C

eDP_TXP_P2_C eDP_TXP_P2_CON N

eDP_TXP_P3_C eDP_TXP_P3_CON N

eDP_AUXN_C

eDP_AUXP_C

1 2

HCM1012GH900BP_4P

L56 EMI@

1 2

HCM1012GH900BP_4P

L59 EMI@

1 2

HCM1012GH900BP_4P

L60 EMI@

1 2

HCM1012GH900BP_4P

L58 EMI@

1 2

HCM1012GH900BP_4P

eDP_TXP_P0_CONN

34

eDP_TXN_P0_CONN

34

eDP_TXN_P1_CONN

34

eDP_TXN_P2_CONNeDP_TXN_P2_C

34

eDP_TXN_P3_CONNeDP_TXN_P3_C

A00_1016: Change L56~L60 footprint from TAIYO_MCF12102G900-T_4P to INPAQ_HCM1012GH900BP_4P to solve SMT place angle issue.

eDP_AUXN_CONN

34

eDP_AUXP_CONN

+LCDVDD

1

JEDP

.1U_0402_16V7K~D

10U_0603_6.3V6M~D

C1145

C1143

1

2

EMI@

1

C6

2

15P_0402_50V8J

EDP_HPD[5]

+INV_PWR_SRC

+LCDVDD

LCD_TST[36]

+3VS_CR

+3VS

eDP_TXN_P3_CONN eDP_TXP_P3_CONN

eDP_TXN_P2_CONN eDP_TXP_P2_CONN

eDP_TXN_P1_CONN eDP_TXP_P1_CONN

eDP_TXN_P0_CONN eDP_TXP_P0_CONN

eDP_AUXP_CONN eDP_AUXN_CONN

DISPOFF# INV_PWM_R

JEDP

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_50398-04041-001

CONN@

45

G5

44

G4

43

G3

42

G2

41

G1

Touch Screen LDO

+3VS_TS

C8

B B

A00_1004: Change to short pad.

1 2

RH357 @ 0_0603_5%RH357 @ 0_0603_5%

1

@

2

2.2U_0603_6.3V6K~D

1

2

3

U728

@U728

@

5

VIN

VOUT

GND

4

EN

NC

G9091-330TO1U_TSOT-23-5

+3VS_TSLDO

1

@

2

C1223

1U_0402_6.3V6K~D

eDP BackLight Power

R1161 220K_0402_5%~DR1161 220K_0402_5%~D

12

EN_INVPWR[36]

12

C613

0.1U_0402_25V6K~D

EN_INVPWR

2

G

EN_INVPWR

B+

60mil

12

R535

R535 1M_0402_5%~D

1M_0402_5%~D

PWR_SRC_ON

12

R536

R536 100K_0402_5%~D

100K_0402_5%~D

13

D

Q71

Q71 DII-DMN65D8LW-7~D

DII-DMN65D8LW-7~D

S

SN74AUP1G04DCKR_SC70-5

1 2

R531 0_0603_5%~D@ R531 0_0603_5%~D@

AO4407AL_SO8

1 2 3 6

4

U708

@ U708

@

1

NC

2

IN A

3

GND

+INV_PWR_SRC

Q70

8 7

60mil

5

Vgs(th) = -1 ~ -3, max 20V

MLK IC : 113m ohm 550m A

0.1U_0402_25V6K~D

C612

Discharge Circuit

+LCDVDD

5

VCC

4

OUT Y

1

2

+INV_PWR_SRC

12

@

R541

R541 820_0805_1%

820_0805_1%

13

D

2

G

S

1

C2982

2

0.1U_0402_25V6K~D

Q305

@

Q305

@

DII-DMN65D8LW-7~D

1

C2985

2

47U_1210_16V6M

BackLight PWM Control

D72

PANEL_BKLEN[5]

PANEL_BKEN_EC[37]

A A

EDP_BIA_PWM[5]

BIA_PWM_EC[36]

5

2

1

3

BAT54CW-7-F_SOT323-3~D

D73

2

1

3

BAT54CW-7-F_SOT323-3~D

12

R540

R540 220K_0402_5%~D

220K_0402_5%~D

12

R545

R545 220K_0402_5%~D

220K_0402_5%~D

DISPOFF#

INV_PWM_R

1

MC3

@MC3

@

680P_0402_50V7K~D

2

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

3

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P19-eDP/ Camera CONN

LA-B441P

1

22 50Thursday, October 16, 2014

1.0

5

+5VALW

1

C1321

C1321 1U_0402_6.3V6K~D

D D

C C

1U_0402_6.3V6K~D

2

+3VALW +3VS

1

2

C1322

0.1U_0402_10V7K

+3VS_CR

1

2

R06_0822: De-pop power switch on MB.

NPI Stage Power Switch

SW2

3

1

SKRBAAE010_4P

4

@

PBTN_SW#

2

ALS_INT#[36]

+3VS

12

C1325

C1325 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

R3

R3 10K_0402_5%~D

10K_0402_5%~D

ALS_INT#

4

1

C1324

0.1U_0402_10V7K

2

3

JIO1

1

USB3RN0[12]

USB3RP0[12]

USB3TN0[12]

USB3TP0[12]

PCIE_PTX_CARDRX_P1[12]

PCIE_PTX_CARDRX_N1[12]

USB_PWR_SHR_EN#[36]

CLK_PCIE_MMI[10]

CLK_PCIE_MMI#[10]

USB_OC0#[12]

PCIE_PRX_CARDTX_P1[12]

PCIE_PRX_CARDTX_N1[12]

MMICLK_REQ#[10]

USB20_P0[12]

USB20_N0[12]

PBTN_SW#[20,21,36]

USB0_DET#[36]

PCH_PLTRST#_EC[11,20,27,28,36]

USB0_PWR_EN_EC[36]

ALS_SMLCLK[36]

PWRBTN_LED#[36]

MEDIACARD_IRQ#[11]

ALS_SMLDATA[36]

LID_SW_IN#[36]

+3VS_CR

+3VALW

+5VALW

+3VS

PBTN_SW#

ALS_INT#

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

GND GND

JXT_FP270H-061G1AM

CONN@

62 63

2

1

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

3

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P20-BTB CONN & Battery LED

LA-B441P

1

23 50Saturday, October 04, 2014

1.0

5

+5VS_AUDIO

1

CA97

2

0.1U_0402_16V7K~N

D D

C C

B B

+5VS_AUDIO

A00_1004: Change to short pad.

I2S_BITCLK_AUDIO[9]

I2S_SYNC_AUDIO[9]

I2S_RST_AUDIO#[9]

I2S_SDIN0[9]

I2S_SDOUT_AUDIO[9]

DMIC_CLK_CODEC[34]

DMIC_DAT_CODEC[34]

+DVDD

JACK_PLUG_DL#[25]

1

2

0.1U_0402_16V7K~N

NB_MUTE#[25,37]

RA76

RA76 100K_0402_1%~D

100K_0402_1%~D

1 2

RA75

RA75 200K_0402_1%

200K_0402_1%

1 2

CA106

@ CA106

@

0.1U_0402_10V7K

CA5

For EMI

1 2

LA14

BLM15BB220SN1D_2P

For EMI

12

@

RA80

RA80 0_0603_5%

A A

0_0603_5%

LA2

BLM15PX600SN1D_2P

10U_0805_10V6K

BLM15PX600SN1D_2P

10U_0805_10V6K

1 2

RA52 0_0402_1%@RA52 0_0402_1%@

1 2

RA53 0_0402_1%@RA53 0_0402_1%@

1 2

RA54 0_0402_1%@RA54 0_0402_1%@

1 2

RA62 33_0402_5%~DRA62 33_0402_5%~D

RA36 0_0402_1%@RA36 0_0402_1%@

RA45 0_0402_1%@RA45 0_0402_1%@

RA45 close with UA2.53

+DVDD

1

2

3mA

1

2

CA42,CA31 close with UA2.7

3mA

1

2

12

1

CA98

2

LA1

12

1

CA4

2

I2C0_SDA_DSP[11]

I2C0_SCK_DSP[11]

12

CODEC_GPIO6[25]

1 2

RA85 10K_0402_5%~DRA85 10K_0402_5%~D

SPK_OUT_L+[25]

SPK_OUT_L-[25]

SPK_OUT_R-[25]

SPK_OUT_R+[25]

1

CA48

2

10U_0603_6.3V6M~D

10mil

0.1U_0402_10V7K

CA42

4.7U_0603_6.3V6K

CA42

4.7U_0603_6.3V6K

CA31

1

2

10mil

0.1U_0402_10V7K

0.1U_0402_10V7K CA104

CA104

CA105

4.7U_0603_6.3V6K

CA105

4.7U_0603_6.3V6K

1

2

50mil

1

CA49

2

0.1U_0402_16V7K~N

0.1U_0402_10V7K

+DVDD+3VS_AUDIO

+DVDDIO+3VS_AUDIO

+PVDD2

1

CA100

2

10U_0805_10V6K

+PVDD1

1

CA3

2

10U_0805_10V6K

I2S_BITCLK_AUDIO_R

I2S_SYNC_AUDIO_R

I2S_RST_AUDIO#_R

I2S_SDIN0_AUDIO

I2S_SDOUT_AUDIO_R

1

CA99

2

1

CA2

2

HD_SOC_SEL

+DVDDIO +DVDD

4

7

19

46

T-PAD

DVDD

DVDD-IO

50mA

10mA

DII-DMN65D8LW-7~D

51

PVDD1

2.5A

RA86 0_0402_1%@RA86 0_0402_1%@

57

11

I2C DAT A

12

I2C CLK

13

HDA BCLK/I2S BCLK

14

HDA SYNC/I2S LRCK

15

HDA Reset/I2S MCLK

16

HDA SDI/F_I2S_DO

17

HDA SDO/F_I2S_DI

53

DMIC-CLK1

54

DMIC-DATA1

1

GPIO_9/I2S_LRCK

2

GPIO_1/DMIC_CLK2/S/PDIF_O/I2S_In JD

3

GPIO_6/I2S_Out

4

GPIO_2/DMIC DATA2/I2S_Out JD

5

GPIO_5/I2S_In

8

I2S_Out JD/Mic1 JD

55

GPIO_8/I2S-MCLK

56

GPIO_7/I2S-BCLK

52

EAPD+PD#/GPIO_11

47

SPK-OUT-LP

48

SPK-OUT-LN

49

SPK-OUT-RN

50

SPK-OUT-RP

9

HP/Line1 JD

18

D_core_cap

10

DVSS

6

HD-SOC SEL

UA2

UA2 ALC3263-CG_QFN56_7X7

ALC3263-CG_QFN56_7X7

HDA_I2S_SEL = Low ; HDA Mode HDA_I2S_SEL = High ; I2S Mode

HDA#_I2S_SEL[36]

CODEC_IRQ[5]

A00_1004: Change to short pad.

PVDD2

Codec

Analog

Pin20~45

Digital

Pin1~19, 46~56

QA8

2

G

1 2

23

45

AVDD2

AVDD1

50mA

150mA

Mic1- Vref_ O-R/A GPO- 1

Mic1- Vref_ O-L/A GPP-0

Mic1- R/Mic 1-N/S leeve

Mic1- L/Mic 1-P/R ing2

12

RA81

RA81 1M_0402_5%~D

1M_0402_5%~D

13

D

S

100K_0402_1%~D

3

HD Audio Codec

1

CA103

CA102

2

10U_0805_10V6K

0.1U_0402_16V7K~N

AGND

CA83

10U_0603_6.3V6M~D

CA83

10U_0603_6.3V6M~D

1

24

41

PCBEEP

CPVDD

CBN2

CBP2

150mA

CBP1

CBN1

Line1-L

Line1-R

HP_Out-R

HP_Out-L

MIC1-C AP

LDO1-CAP

VREF1

LDO2-cap

VREF

CPVPP

CPVREF

CPVEE

AVSS1

AVSS2

+DVDD+5VALW

12

13

D

2

G

S

RA82

1 2

MONO_IN

25

26

27

28

39

38

37

36

35

34

33

32

40

44

21

22

43

29

30

31

42

20

RA87

RA87 1K_0402_5%~D

1K_0402_5%~D

LBSS138LT1G_SOT-23-3

LBSS138LT1G_SOT-23-3 QA7

QA7

HD_SOC_SEL

HD_SOC_SEL = Low ; I2S Mode HD_SOC_SEL = High ; HDA Mode

CA95 2.2U_0603_6.3V6K~DCA95 2.2U_0603_6.3V6K~D

CA96 2.2U_0603_6.3V6K~DCA96 2.2U_0603_6.3V6K~D

AUDIO_VREF

CA84 2.2U_0603_6.3V6K~DCA84 2.2U_0603_6.3V6K~D

CA85 2.2U_0603_6.3V6K~DCA85 2.2U_0603_6.3V6K~D

1 2

LINE1-VREFO [25]

MIC1-VREFO [25]

MIC1_R [25]

MIC1_L [25]

LINE1_L [25]

LINE1_R [25]

HP2_D_R [25]

HP2_D_L [25]

AGND AGND

1

CA78

2

0.1U_0402_10V7K

AGND AGND

CA86

CA87

1

2

0.1U_0402_10V7K

1

2

2.2U_0603_6.3V6K~D

+AVDD2

1

CA80

2

0.1U_0402_10V7K

@

CA88

CA90

1

2

0.1U_0402_10V7K

0.1U_0402_10V7K 10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

AGND AGND AGND AGN D

+3VS_AUDIO

12

@RA14

@

I2S_RST_AUDIO#_R

2

1

2

+AVDD2 +LDO2

12

RA84

@RA84

@

0_0603_5%~D

A00_1004: Change to short pad.

RA83

CA82

10U_0603_6.3V6M~D

CA82

10U_0603_6.3V6M~D

0_0603_5%

+LDO2

CA91

1

2

0.1U_0402_10V7K

RA11,CA26 Close UA2 Pin6

RA14

4.7K_0402_5%~D

CA26

CA26 10P_0402_50V8J~D

10P_0402_50V8J~D

CA92

+1.8VS_AUDIO

12

@

BEEP[36]

SPKR[11]

CA93

CA94

1

2

4.7U_0603_6.3V6K

2

10U_0603_6.3V6M~D

1

2

10U_0603_6.3V6M~D

CA18 close UA2 Pin12

DMIC_CLK_CODEC

CA23

10P_0402_50V8J~D

DMIC_DAT_CODEC

CA25

10P_0402_50V8J~D

GND

2

1

2

1

Reserved for EMI Reserved for EMI

+AVDD1+AVDD1

10U_0805_10V6K

AGND

Beep sound

RA24

1 2

47K_0402_5%~D

RA25

1 2

47K_0402_5%~D

Close to UA2 Pin2

@JPA1

@

JUMP_43X39

@JPA2

@

JUMP_43X39

@JPA3

@

JUMP_43X39

@JPA4

@

JUMP_43X39

@JPA5

@

JUMP_43X39

I2S_BIT CLK_AUDIO _R

CA57

@ CA57

@

0.1U_0402_10V7K

Close to UA2

I2S_SYNC_AUDIO_R

CA24

10P_0402_50V8J~D

I2S_SDOUT_AUDIO_R

CA27

10P_0402_50V8J~D

1

2

CA101

JPA1

JPA2

JPA3

JPA4

JPA5

12

R7

R7 10K_0402_5%~D

10K_0402_5%~D

12

1

2

1

2

1

LA3BLM21PG600SN1D_0805~D LA3BLM21PG600SN1D_0805~D

12

CA34

1 2

0.1U_0402_10V7K

AGND

+5VS_AUDIO

MONO_IN

1

CA33

CA33 100P_0402_50V8J~D

100P_0402_50V8J~D

2

5

CA105,CA104 close with UA2.19

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

3

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P21-Audio Codec

LA-B441P

1

24 50Sunday, October 05, 2014

1.0

5

Universal Audio Jack

CA68

RA27

2.2K_0402_5%~D

MIC1-VREFO[24]

D D

MIC1_L[24]

HP2_D_L[24]

HP2_D_R[24]

MIC1_R[24]

C C

LINE1-VREFO[24]

LINE1_L[24]

LINE1_R[24]

Ring2

Sleeve

1 2

RA28

2.2K_0402_5%~D

1 2

HP2_D_L

RA17 8.06_0402_1%RA17 8.06_0402_1%

1 2

HP2_D_R

RA15 8.06_0402_1%RA15 8.06_0402_1%

R06_0905: Change LA4, LA5 "P/N" to 0 Ohm.

R07_0910: Change LA4, LA5 footprint to 0 Ohm.

A00_1004: Change to short pad.

DA6

1

BAT54A-7-F_SOT23-3

3

2

RA48 4.7K_0402_5%~DRA48 4.7K_0402_5%~D

RA49 4.7K_0402_5%~DRA49 4.7K_0402_5%~D

1 2

CA70 4.7U_0402_6.3V6MCA70 4.7U_0402_6.3V6M

1 2

CA71 4.7U_0402_6.3V6MCA71 4.7U_0402_6.3V6M

HP2_D_L_R1

HP2_D_R_R2

1 2

40mil

1 2

LA4 0_0402_1%@LA4 0_0402_1%@

1 2

LA7

PBY100505T-700Y-N

1 2

LA6

PBY100505T-700Y-N

1 2

LA5 0_0402_1%@LA5 0_0402_1%@

40mil

LINE1_R_C

LINE1_L_C HP2_D_R_R2

CA68

CA28

1 2

RA50 1K_0402_5%~DRA50 1K_0402_5%~D

1 2

RA51 1K_0402_5%~DRA51 1K_0402_5%~D

100P_0402_50V8J~D

1

2

100P_0402_50V8J~D

CA69

1

2

9.09K_0402_1%

4

3

2

1

Int. Speaker Conn.

100P_0402_50V8J~D

CA29

1

2

100P_0402_50V8J~D

12

1

2

@

RA60

AZ5123-01F.R7G_DFN1006P2X2

12

EMI@

12

DA5

HP2_D_L_R1

12

@

RA61

9.09K_0402_1%

AZ5123-01F.R7G_DFN1006P2X2

EMI@

DA7

+3VS_AUDIO

2

3

1

12

@

RA19

RA19 10K_0402_5%~D

10K_0402_5%~D

MIC1_L_L

HP2_D_L_C

JACK_PLUG

HP2_D_R_C

MIC1_R_L

100K_0402_5%~D

2

3

DA2

DA1

1

AZ5125-02S.R7G_SOT23-3

12

@

RA35

@

AZ5125-02S.R7G_SOT23-3

AGND

0_0402_1%

RA30

JHP1

7 4 1

5

6

2 3

SINGA_2SJ3095-022111F

CONN@

SPK_OUT_L+[24] SPK_OUT_L-[24]

SPK_OUT_R-[24] SPK_OUT_R+[24]

L2

L2 BLM15PX181SN1D_2P

BLM15PX181SN1D_2P

1 2 1 2

L3

BLM15PX181SN1D_2P

L4

BLM15PX181SN1D_2P

1 2 1 2

L5

BLM15PX181SN1D_2P

40mil = For 4ohm 2W Speaker

1000P_0402_50V7K~D

CA53

2

1

1000P_0402_50V7K~D

CA56

2

1

2

3

CA55

2

1

DA3

1

PJDLC05C_SOT23-3

1000P_0402_50V7K~D

2

3

CA54

2

1

DA4

1

PJDLC05C_SOT23-3

SPK_L+_C SPK_L-_C SPK_R-_C SPK_R+_C

JSPK1

6

G2

5

G1

4

3

2

1

ACES_50224-00401-001

CONN@

AGND AGND

B B

Prevent S3/S4/S5 Background Noise.

2

G

+RTCVCC

12

RA16

100K_0402_5%~D

13

D

QA9

QA9 DII-DMN65D8LW-7~D

DII-DMN65D8LW-7~D

S

AGND

MIC1_R_L

34

D

G

5

S

DMN66D0LDW-7_SOT363-6

QA1A

AGND

MIC1_L_L

61

D

G

2

S

QA1B

QA1B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

AGND

DMN66D0LDW-7_SOT363-6

JACK_PLUG

4

+3VS_AUDIO

12

RA18

@

10K_0402_5%~D

1 2

RA57

@RA57

NB_MUTE#[24,37]

CODEC_GPIO6[24]

A A

1K_0402_5%~D

RA32

0_0402_5%~D

5

@

1 2

12

RA41

RA41 100K_0402_5%~D

100K_0402_5%~D

Reserved Delay cricutis

+3VS_AUDIO

12

RA37

@RA37

@

100K_0402_5%~D

RA39

@ RA39

@

100K_0402_5%~D

1 2

34

QA3A

@

QA3A

@

D

G

5

S

4/16, Reserved Delay cricutis

AGND

1 2

RA26 0_0402_1%@RA26 0_0402_1%@

A00_1004: Change to short pad.

@RA38

@

100K_0402_5%~D

12

CA40

@CA40

@

0.1U_0402_25V6K~D

12

RA38

JACK_PLUG_DL

61

QA3B

@

QA3B

@

D

G

2

DMN66D0LDW-7_SOT363-6

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

3

2013/07/04 2013/10/28

A00_1004: Change to short pad.

1 2

RA31 0_0402_1%

0_0402_1%

JACK_PLUG_DL

12

RA20

@RA20

@

100K_0402_5%~D

@

CA74

10U_0603_6.3V6M~D@CA74

10U_0603_6.3V6M~D

1

2

Compal Secr et Data

Deciphered Date

2

@RA31

@

2

G

13

D

@

QA6

QA6 DII-DMN65D8LW-7~D

DII-DMN65D8LW-7~D

S

AGNDAGND AGN D

1 2

RA29

@RA29

0_0402_1%

@

AUD_HP_NB_SENSE [36]

JACK_PLUG_DL# [24]

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P22-Audio Conn

LA-B441P

1

1.0

25 50Monday, October 06, 2014

1.0

5

1

CV13

@CV13

@

0.1U_0402_10V6K~D

PCH_DP_AUXP[5] PCH_DP_CLK[5]

D D

DP Signal ESD

C C

PCH_DP_AUXN[5] PCH_DP_DAT[5]

MD5

1

PCH_DP_N2_C PCH_DP_N2_C

2

4

PCH_DP_N1_C

5

PCH_DP_P1_C

3

TVWDF1004AD0_DFN9

EMI@

9

8

PCH_DP_P2_C

7

PCH_DP_N1_C

6

PCH_DP_P1_C

12

CV80.1U_0402_10V7K~D CV80.1U_0402_10V7K~D

12

CV100.1U _0402_10V7K~D CV100.1U_0402_10V7K~D

2

PCH_DP_AUXN_C

S = L, A port = B1 port S = H, A port = B2 port

4

UV1

Vcc

2

1B1

3

1B2

5

2B1

6

2B2 3B1

OE# 3B2 4B1

GND

4B2

Place close JDP1

DISP_DAT_AUXN_CONN

DISP_CLK_AUXP_CONN

4

1A

7

2A

9

3A

12

4A

15 1

S

8

MD16

1

2

4

5

3

TVWDF1004AD0_DFN9

EMI@

DISP_CLK_AUXP_CONN DISP_DAT_AUXN_CONNPCH_DP_AUXP_C

DP_CBL_DET

1 : HDMI/DVI/VGA Dongle 0 : DP Port

+5VS

16

11 10 14 13

SN74CBT3257CPWR_TSSOP16~D

PCH_DP_N3_C PCH_DP_N3_C

PCH_DP_P3_C PCH _DP_P3_CPCH_DP_P2_C

PCH_DP_N0_C

PCH_DP_P0_C

1 2

RV2 100K_0402_5%~DRV2 100K_0402_5%~D

1 2

RV3 100K_0402_5%~DRV3 100K_0402_5%~D

9

8

7

PCH_DP_N0_C

6

PCH_DP_P0_C

+3VS

1

EMI@

CV798

15P_0402_50V8J

2

RF Reserved.

3

2

1

Mini DP CONN

+DP_PWR

CV14 0.1U_0402_10V7K~DCV14 0.1U_0402_10V7K~D

1

2

CV1

10U_0603_6.3V6M~D

CV1

10U_0603_6.3V6M~D

CV15 22U_0805_6.3V6M~DCV15 22U_0805_6.3V6M~D

1

2

1

2

DISP_CEC

RV4 5.1M_0402_5%RV4 5.1M_0402_5%

12

CV2

.1U_0402_16V7K~D

CV2

.1U_0402_16V7K~D

1

2

JMDP

1

GND

2

HOT_PLUG

3

LANE0_P

4

CONFIG1

5

LANE0_N

6

CONFIG2

7

GND

8

GND

9

LANE1_P

10

LANE3_P

11

LANE1_N

12

LANE3_N

13

GND

14

GND

15

LANE2_P

16

AUX_CH_P

17

LANE2_N

18

AUX_CH_N

19

GND

20

DP_PWR

TE_C-PT13-061

CONN@

GND1 GND2 GND3 GND4

21 22 23 24

+3VS

U726

1

IN

AP2337SA-7_SOT23-3

PCH_DP_P0[5]

PCH_DP_N0[5]

PCH_DP_P1[5] PCH_DP_P3[5] PCH_DP_N1[5] PCH_DP_N3[5]

PCH_DP_P2[5]

PCH_DP_N2[5]

PCH_DP_HPD[5]

3

OUT

2

GND

+5VS

G

2

13

D

S

D

S

LBSS138LT1G 1N_SOT-23-3

QV2

12

CV3.1U_0402_16V7K~D CV3.1U_0402_16V7K~D

12

CV4.1U_0402_16V7K~D CV4.1U_0402_16V7K~D

12

CV5.1U_0402_16V7K~D CV5.1U_0402_16V7K~D

12

CV6.1U_0402_16V7K~D CV6.1U_0402_16V7K~D

12

CV7.1U_0402_16V7K~D CV7.1U_0402_16V7K~D

12

CV9.1U_0402_16V7K~D CV9.1U_0402_16V7K~D

12

CV11.1U_0402_16V7K~D CV11.1U_0402_16V7K~D

12

CV12.1U_0402_16V7K~D CV12.1U_0402_16V7K~D

DISP_HPD_SINK

12

@

RV10

RV10 100K_0402_5%~D

100K_0402_5%~D

DISP_HPD_SINK PCH_DP_P0_C CAB_DET_SINK PCH_DP_N0_C

PCH_DP_P1_C PCH_DP_P3_C PCH_DP_N1_C PCH_DP_N3_C

PCH_DP_P2_C DISP_CLK_AUXP_CONN PCH_DP_N2_C DISP_DAT_AUXN_CONN

RV8

RV8 0_0402_1%

0_0402_1%

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

3

2013/07/04 2013/10/28

DP_CBL_DET CAB_DET_SINK

A00_1004: Change to short pad.

1 2

Compal Secr et Data

Deciphered Date

2

@

12

RV9

RV9 1M_0402_5%~D

1M_0402_5%~D

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

P23-Mini DP CONN

LA-B441P

26 50Sunday, October 05, 2014

1

26 50Sunday, October 05, 2014

1.0

5

D D

C C

B B

4

+3.3V_M +3VS_TPM

R1393 0.01_0805_1%~DTPM@R1393 0.01_0805_1%~DTPM@

+3VS_TPM

0.1U_0402_10V7K

2200P_0402_25V7K~D

C1141

C1142

1

2

TPM@

1 2

R8 4.7K_0402_5%~DTPM@R8 4.7K_0402_5%~DTPM@

1 2

R9 4.7K_0402_5%~D

TPM@

1 2

ATMEL TPM

12

V_BAT

1

GPIO_1

2

GPIO_2

17

GPIO_3

6

GPIO-Express-00

7

PP/GPIO

9

TESTBI

8

TESTI

5

NBO_1

13

NBO_2

14

NBO_3

15

NBO_4

27

NBO_5

28

NBO_6

AT97SC3205_TSSOP28~D

TPM@

SPI_CLK SPI_CS#

SPI_RST#

PIRQ#

MISO MOSI

GND GND GND GND

U652

VCC VCC VCC VCC

3

+3VS_TPM

3 10 19 24

26 23 21

PCH_SPI_CLK_TPM

22 16

TPM_RESET#_TPM

20

25 18 11 4

+3VS_TPM

1

2

2200P_0402_25V7K~D

C1137

TPM@

1

C1138

2

TPM@

RH474 0_0402_1%@RH474 0_0402_1%@

1

C1139

2

TPM@

1 2

1

2

A00_1004: Change to short pad.

2

0.1U_0402_10V7K

0.1U_0402_10V7K C723

4.7U_0603_6.3V6K

C723

4.7U_0603_6.3V6K

C1140

1

2

TPM@

PCH_SPI_SO_TPM [8] PCH_SPI_SI_TPM [8] PCH_SPI_CLK_TPM [8] PCH_SPI_CS2# [8]

PCH_PLTRST#_EC [11,20,23,28,36]

TPM_PIRQ# [11]

@

MC33

12

22P_0402_50V8J~D

Reserve for EMI please close to U652

PCH_SPI_CLK_TPM

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

3

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P24-TPM

LA-B441P

1

27 50Sunday, October 05, 2014

1.0

A

B

C

D

E

Wireless LAN

1 2

R741 0_0402_5%~D@R741 0_0402_5%~D@

ML10 EMI@

USB20_P2[12]

1 1

USB20_N2[12]

+VS_LPSS_SDIO

2 2

1

4

DLW21HN900HQ2L_4P

1 2

R742 0_0402_5%~D

1 2

R1360 49.9K_0402_1%~D@R1360 49.9K_0402_1%~D@

1 2

R1361 49.9K_0402_1%~DR1361 49.9K_0402_1%~D

1 2

R1362 150K_0402_5%~DR1362 150K_0402_5%~D

1 2

R1363 49.9K_0402_1%~DR1363 49.9K_0402_1%~D

1 2

R1364 49.9K_0402_1%~DR1364 49.9K_0402_1%~D

1 2

R1365 49.9K_0402_1%~DR1365 49.9K_0402_1%~D

1 2

R1327 100K_0402_5%~D@R1327 100K_0402_5%~D@

1 2

R1328 10K_0402_5%~D@R1328 10K_0402_5%~D@

1 2

R1395 49.9K_0402_1%R1395 49.9K_0402_1%

2

3

USB20_P2_R

USB20_N2_R

SDIO_CLK SDIO_CMD SDIO_D0 SDIO_D1 SDIO_D2 SDIO_D3 SDIO_WAKE#_Q SDIO_RST#

SDIO_CLK

CLK_PCIE_WLAN CLK_PCIE_WLAN#

Slot A -SD

JNGFF1

1

GND

USB20_P2_R USB20_N2_R

SDIO_CLK[11]

SDIO_CMD[11]

SDIO_D0[11] SDIO_D1[11] SDIO_D2[11] SDIO_D3[11]

PCIE_PTX_WLANRX_P4[12] PCIE_PTX_WLANRX_N4[12]

PCIE_PRX_WLANTX_P4[12] PCIE_PRX_WLANTX_N4[12]

CLK_PCIE_WLAN[10] CLK_PCIE_WLAN#[10]

WLANCLK_REQ#[10]

PCIE_WAKE#[36]

@

C1302

15P_0402_50V8J@C1302

15P_0402_50V8J

C1301

15P_0402_50V8J@C1301

15P_0402_50V8J

1

2

SDIO_CLK SDIO_CMD SDIO_D0 SDIO_D1 SDIO_D2 SDIO_D3 SDIO_WAKE#_Q SDIO_RST#

CLK_PCIE_WLAN CLK_PCIE_WLAN#

3

USB_D+

5

USB_D-

7

GND

9

SIDO_CLK

11

SDIO_CMD

13

SDO_DAT0

15

SDO_DAT1

17

SDO_DAT2

19

SDO_DAT3

21

SDIO_WAKE#

23

SDIO_RESET#

25

GND

27

PETP0

29

PETN0

31

GND

33

PERP0

35

PERN0

37

GND

39

REFCLKP0

41

REFCLKN0

43

GND

45

CLKEQ0#

47

PEWAKE0#

49

GND

51

RSRVD/PETP1

53

RSRVD/PETN1

55

GND

57

RSRVD/PERP1

59

RSRVD/PERN1

61

GND

63

RESERVED

65

RESERVED

67

GND

69

MTG77

CONCR_213EBAA2FKA

CONN@

PCM_CLK

PCM_SYNC

PCM_OUT

UART_WAKE#

UART_RX

UART_TX UART_CTS UART_RTS RESERVED RESERVED RESERVED

W_DISABLE2# W_DISABLE1#

I2C_DAT A

RESERVED RESERVED RESERVED RESERVED

2

3

@

R06_0829: Reserve CAP on PCIe clock for RF.

+VS_LPSS_SDIO+3VS

1

@

C1283

0.1U_0402_10V7K

Pop for SDIO Interface NGFF

1 2

SDIO_WAKE#[5]

PCH_PLTRST#_EC[11,20,23,27,36]

MPCIE_RST#[9]

3 3

MPCIE_RST#

PCH_PLTRST#_EC

R1199 0_0402_5%~D@R1199 0_0402_5%~D@

R1313 0_0402_5%~D@R1313 0_0402_5%~D@

R1314 0_0402_5%~D@R1314 0_0402_5%~D@

U675

1

IN1

2

IN2

MC74VHC1G08DFT2G_SC70-5

1 2

+3VS

5

VCC

OUT

GND

3

4

SDIO_WAKE#_R

SDIO_RST#_R

NGFF_RST#

12

R1203

R1203 100K_0402_5%~D

100K_0402_5%~D

2

U679

@U679

@

B2

VCCB

A2

I/O Vcc 1

A1

I/O Vcc 2

B1

GND

NLSX0102FCT1G_FLIP CHIP8

NGFF_RST# [29]

VCCA

I/O VL1

I/O VL2

OE

C1

D2

D1

C2

1

2

SDIO_WAKE#_Q

SDIO_RST#PCH_PLTRST#_EC

1 2

R1131 0_0402_5%~D@R1131 0_0402_5%~D@

@

C1284

0.1U_0402_10V7K

+VS_LPSS_SDIO

3.3VAUX

3.3VAUX LED1#

PCM_IN

LED2#

GND

COEX3 COEX2 COEX1

SUSCLK

PERST0#

I2C_CLK

ALERT

3.3VAUX

MTG76

+3VS_NGFF

C712

22U_0603_6.3V6M~D

C712

22U_0603_6.3V6M~D

1

2 4 6 8 10 12 14 16 18 20 22

24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66

68

2

UART1_RXD_NGFF

UART1_TXD_NGFF UART1_CTS#_NGFF UART1_RTS#_NGFF

1 2

R1210 0_0402_1%@R1210 0_0402_1%@

1 2

R1212 0_0402_1%@R1212 0_0402_1%@

A00_1004: Change to short pad.

@

1 2

R1255 0_0402_5%~D

NGFF_RST# BT_RADIO_DIS#_R WLAN_WIGIG60GHZ_DIS#_R

1 2

R1209 0_0402_5%~D@ R1209 0_0402_5%~D@

+3VS_NGFF

UART Level Shifter

+VS_LPSS_SDIO

1 2

R1373 49.9K_0402_1%~D@R1373 49.9K_0402_1%~D@

1 2

R1374 49.9K_0402_1%~D@R1374 49.9K_0402_1%~D@

1 2

R1375 49.9K_0402_1%~D@R1375 49.9K_0402_1%~D@

1 2

R1372 49.9K_0402_1%~D@R1372 49.9K_0402_1%~D@

RF Reserved.

EMI@

C1297

15P_0402_50V8J

C1297

15P_0402_50V8J

C715

0.1U_0402_10V7K

C715

0.1U_0402_10V7K

1

2

UART_WAKE# [11]

1 2

R1200 0_0402_5%~DR1200 0_0402_5%~D

1 2

R1208 0_0402_5%~D@R1208 0_0402_5%~D@

CL_DAT [8] CL_CK [8]

RF Reserved.

EMI@

C713

0.1U_0402_10V7K

C713

0.1U_0402_10V7K

C716

22U_0603_6.3V6M~D

C716

22U_0603_6.3V6M~D

1

2

1

2

SUSCLK_R [11,29]

BT_CS_NOTICE

C1298

15P_0402_50V8J

C1298

15P_0402_50V8J

UART1_TXD_NGFF UART1_RXD_NGFF UART1_RTS#_NGFF UART1_CTS#_NGFF

BT_CS_NOTICE

@

C1299

15P_0402_50V8J@C1299

15P_0402_50V8J

1

2

CL_RST# [8]

BT_CS_NOTICE [ 11]

WLAN_WIGIG60GHZ_DIS#_R

BT_RADIO_DIS#_R

+VS_LPSS_SDIO +3VS

@

C1286

0.1U_0402_10V7K@C1286

0.1U_0402_10V7K

1

2

U671

@U671

@

1

VCCA

UART1_TXD_NGFF UART1_RXD_NGFF UART1_RTS#_NGFF UART1_CTS#_NGFF

2

A1

3

A2

4

A3

5

A4

6

NC

7

GND

TXB0104PWR_TSSOP14

DZ1

RB751S40T1G_SOD523-2

DZ2

RB751S40T1G_SOD523-2

14

VCCB

13

B1

12

B2

11

B3

10

B4

9

NC

8

R1188 0_0402_5%~D@R1188 0_0402_5%~D@

OE

12

UART1_TXD [11]

UART1_RXD [11]

UART1_RTS# [11]

UART1_CTS# [11]

1 2

0.1U_0402_10V7K@C1285

0.1U_0402_10V7K

1

2

WLAN_WIGIG60GHZ_DIS# [37]

BT_RADIO_DIS# [37]

RF Reserved.RF Reserved.

@

C1300

15P_0402_50V8J@C1300

15P_0402_50V8J

C1285

1

2

+VS_LPSS_SDIO

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

C

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P25-WLAN / BT (M.2)

LA-B441P

E

28 50Sunday, October 05, 2014

1.0

5

M.2 Slot-C Key-M (SSD)

4

3

2

1

D D

+3.3VDX_SSD

RF Reserved.

EMI@

JNGFF3

1

3

5

7

9

11

13

15

17

19

21

23

25

27

1 2

SATA_RN2/PERN6_L1[9] SATA_RP2/PERP6_L1[9]

SATA_TN2/PETN6_L1[9]

PCIe SSD

SATA SSD

C C

mCARD_PCIE#_SATA[9]

SATA_TP2/PETP6_L1[9]

SATA_RP3/PERP6_L0[9] SATA_RN3/PERN6_L0[9]

SATA_TN3/PETN6_L0[9] SATA_TP3/PETP6_L0[9]

CLK_PCIE_mSATA#[10] CLK_PCIE_mSATA[10]

0.1U_0402_10V7K

S IC TC7SZ14FU SSOP 5P

SATA -> High PCIe -> Low

CS60 0_0402_5%~DCS60 0_0402_5%~D

1 2

CS59 0_0402_5%~DCS59 0_0402_5%~D

1 2

CS58 0.1U_0402_10V7KCS58 0.1U_0402_10V7K

1 2

CS57 0.1U_0402_10V7KCS57 0.1U_0402_10V7K

1 2

CS62 0_0402_5%~DCS62 0_0402_5%~D

1 2

CS61 0_0402_5%~DCS61 0_0402_5%~D

1 2

CS43 0.1U_0402_10V7KCS43 0.1U_0402_10V7K

1 2

CS42 0.1U_0402_10V7KCS42 0.1U_0402_10V7K

R220 10K_0402_5%~DR220 10K_0402_5%~D

+3VS

1

CS44

2

U683

5

1

P

NC

4

2

Y

A

G

3

R06_0902: Main source has been banned by sourcer. change main source from SA00001N400 to SA00001N200.

mCARD_PCIE_SATA#

1 2

SATA -> GND PCIe -> OC

SATA_RN2/PERN6_L1_C SATA_RP2/PERP6_L1_C

SATA_TN2/PETN6_L1_C SATA_TP2/PETP6_L1_C

SATA_RP3/PERP6_L0_C SATA_RN3/PERN6_L0_C

SATA_TN3/PETN6_L0_C SATA_TP3/PETP6_L0_C

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

68

GND

CONCR_213MAAA32FA

CONN@

GND

2 4 6

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58

60 62 64 66

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54

SSD_PCIE_WAKE#

56 58

60 62 64 66

69

R1376 10K_0402_5%~DR1376 10K_0402_5%~D

R1377 10K_0402_5%~DR1377 10K_0402_5%~D

R2662 0_0402_5%~D@R2662 0_0402_5%~D@

4.7U_0603_6.3V6K

1

2

1 2

C720

.1U_0402_16V7K~D

C720

.1U_0402_16V7K~D

C719

0.01U_0402_16V7K~D

1

2

12

C722

47P_0402_50V8J~D

C722

47P_0402_50V8J~D

C721

1

2

+3.3VDX_SSD

mSATA_DEVSLP [ 11]

NGFF_RST# [28]

mSATACLK_REQ# [10]

+3.3VDX_SSD

SUSCLK_R [11,28]

+3.3VDX_SSD

EMI@

C1304

15P_0402_50V8J

C1304

15P_0402_50V8J

1

2

B B

FAN

+3VS

R884

R1103

1 2

10K_0402_5%~D

FAN1_PWM[36] FAN1_TACH[36]

A A

10K_0402_5%~D

D81

RB751S40T1G_SOD523-2

5

+5VS

2

1

C1102

R886

1 2

10K_0402_5%~D

12

C1102

JFAN1

0.1U_0402_25V6K~D

6

G2

5

G1

4

3

2

1

ACES_50224-00401-001

CONN@

4

NFC(Reserved)

R1242 0_0603_5%~D@R1242 0_0603_5%~D@

+3V_NFC

NFC_VDD_SIM

PCH_NFC_RST#

NFC_DET#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

3

R973 10K_0402_5%~D@R973 10K_0402_5%~D@

R974 0_0402_5%~D@R974 0_0402_5%~D@ R1142 100K_0402_5%~D@R1142 100K_0402_5%~D@ R1228 0_0402_5%~D@R1228 0_0402_5%~D@

12 1 2 1 2 1 2

Compal Secr et Data

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

+3V_PCH

PCH_NFC_RST#[11]

SML0CLK[8] SML0DATA[8]

NFC_IRQ[11] NFC_DET#[11]

2

PCH_NFC_RST#

NFC_VDD_SIM

NFC_DET#

1 2

+3V_NFC

1

C1134

@C1134

@

0.1U_0402_10V7K

2

+3V_NFC

R1100

R1100 100K_0402_5%~D

100K_0402_5%~D

1 2

Title

Size Document Number Rev

C

Date: Sheet of

JNFC1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

GND

17

GND

E-T_6705K-Y15N-00L

CONN@

Compal Electronics, Inc.

P26-mSATA / NFC / FAN Conn

LA-B441P

1

29 50Saturday, October 04, 2014

15. MOD_GND

14. VDD_IO

13. MOD_VDD

12. SWP_PWR

11. NC/Float

10. Reset/WakeUp

9. MOD_GND

8. I2C_SCL

7. I2C_SDA

6. VDD_SIM

5. IRQ

4. MOD_GND

3. SWP

2. MOD_GND

1. MOD_VDD

1.0

A

B

C

D

E

USB IO Port

+5V_USB_P1

EMI@

C3

1

C265

C303

2

.1U_0402_16V7K~D

150U_B2_6.3VM_R35M

USB20_N1_CONN USB20_P1_CONN

USB3RN1_RC_CON USB3RP1_RC_CON

USB3TN1_RC_CON USB3TP1_RC_CON

+5V_USB_P1

15P_0402_50V8J

USB3RN1_RC_CON USB3RN1_RC_CON

USB3RP1_RC_CON USB3RP1_RC_CON

USB3TN1_RC_CON USB3TN1_RC_CON

USB3TP1_RC_CON USB3TP1_RC_CON

USB1 CONN

JUSB1

1

VBUS

2

D-

3

D+

4

GND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

TE_C-PT13-067

CONN@

EMI@

DI1

1

2

4

5

3

8

TVWDF1004AD0_DFN9

Hank0225: Note, PCB footprint is different from TVWDF1004AD0_DFN9, but it's compatible.

10

GND

11

GND

12

GND

13

GND

10

9

7

6

USB3.0 Shielding Clip

EMIST_SUL-12A2M_1P

H22

@

1

EMIST_SUL-12A2M_1P

H24

@

1

EMIST_SUL-12A2M_1P

H20

@

1

EMIST_SUL-12A2M_1P

H25

@

1

EMIST_SUL-12A2M_1P

H21

@

1

USB20_N1_CONN USB20_P1_CONN

3

DI2

L30ESDL5V0C3-2_SOT23-3

EMI@

1

+

2

1 2

R262 0_0402_5%~D@ R262 0_0402_5%~D@

ML11 EMI@

USB20_P1[12]

1 1

USB20_N1[12]

1 2

USB3TP1[12]

USB3TN1[12]

USB3RN1[12]

USB3RP1[12]

2 2

C623 0.1U_0402_10V7KC623 0.1U_0402_10V7K

1 2

C621 0.1U_0402_10V7KC621 0.1U_0402_10V7K

USB3TN1_C

1

4

DLW21HN900HQ2L_4P

1 2

R222 0_0402_5%~D@ R222 0_0402_5%~D@

1 2

R556 0_0402_5%~D@ R556 0_0402_5%~D@

1 2

CMMI21T-670Y-N

1 2

R555 0_0402_5%~D@ R555 0_0402_5%~D@

1 2

R560 0_0402_5%~D@ R560 0_0402_5%~D@

1 2

R565 0_0402_5%~D@ R565 0_0402_5%~D@

ML12

EMI@

ML13

CMMI21T-670Y-N

EMI@

2

3

2

3

34

USB20_P1_CONN

USB20_N1_CONN

L40 close to JUSB1

USB3TP1_RC_CONUSB3TP1_C

USB3TN1_RC_CON

USB3RN1_RC_CON

USB3RP1_RC_CON

+5VALW

1

C962

2

10U_0603_6.3V6M~D

EMI@

1

C2

C963

2

15P_0402_50V8J

.1U_0402_16V7K~D

R06_0822: Change P/N to suffix '0'.

USB1_PWR_EN[10]

USB1_PWR_EN_EC[36]

MC74VHC1G32DFT2G_SC70-5~D

U699

+5VALW

1

2

USB1_EN

+3VALW

5

INB

INA

3

P

G

O

US2

1

GND

2

VIN3VOUT

4

EN

G547I1P81U_MSOP8

C1289

1 2

0.1U_0402_10V7K

4

USB1_EN

12

8

VOUT VOUT7VIN

6 5

OC

R1216

R1216 1M_0402_5%~D

1M_0402_5%~D

+5V_USB_P1

USB_OC1# [12]

2

1

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

C

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P27-USB 3.0 IO CONN

LA-B441P

E

30 50Saturday, October 04, 2014

1.0

A

1 1

B

C

D

E

F

G

H

Battery Gauge LED

+5VALW

21

LED13

LED11

LED10

LED14

LED12

+5VALW

RP13

6 7 8 9

10

10K_1206_10P8R_5%

+5VALW

@RP13

@

5 4 3 2 1

21

2 2

BATT_LED#_LV5[37] BATT_LED#_LV4[37] BATT_LED#_LV3[37] BATT_LED#_LV2[37] BATT_LED#_LV1[37]

EC GPIO set to OD output

3 3

Battery Gauge Button

BATBTN#[36]

1

C2983

0.1U_0402_10V7K

2

1

SW3

TBFD12KQR

4

3

1 2

R916 820_0402_5%~DR916 820_0402_5%~D

1 2

R913 820_0402_5%~DR913 820_0402_5%~D

1 2

R912 820_0402_5%~DR912 820_0402_5%~D

1 2

R911 820_0402_5%~DR911 820_0402_5%~D

1 2

R910 820_0402_5%~DR910 820_0402_5%~D

BAT_LED#_LV5

BAT_LED#_LV4

BAT_LED#_LV3

BAT_LED#_LV2

BAT_LED#_LV1

27-11-T1D-CP1Q1RY-3C_WHITE~D

R06_0825: Change P/N form SN100006P00(MISAKI) to SN100008F00 as MISAKI has been banned.

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

A

B

C

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

E

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

F

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

G

Compal Electronics, Inc.

P28-BAT LED

LA-B441P

31 50Saturday, October 04, 2014

H

1.0

5

4

3

2

1

Touch Pad, Card Reader Load Switch Camera, Touch Screen Load Switch

C1254

C1254 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

12

TP_PW _EN

+5VALW

MEDIACARD_ PWREN

C1256

C1256 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

12

MEDIACARD_ PWREN TP_PW _EN MEDIACARD_ PWREN

TP_PW _EN[37]

D D

MEDIACARD_ PWREN[11]

+3VS

R1178 100K_0402_5%~DR1178 100K_0402_5%~D

1 2

R1175 100K_0402_5%~DR1175 100K_0402_5%~D R1176 100K_0402_5%~D@R1176 100K_0402_5%~D@

U716

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

AOZ1331 _DFN_14P

R07_0910: Change load switch from APEC SA00006FD00 to AOS SA00006U300.

VOUT1 VOUT1

CT1

GND

CT2

VOUT2 VOUT2

GPAD

14 13

12

11

10

9 8

15

A00_1004: Change to short pad. A00_1004: Change to short pad.

R1323

R1323 0_0603_5%

0_0603_5%

1 2

@

C1257

C1257 2200P_0402_25V7K~D

2200P_0402_25V7K~D

1 2

C1258

C1258 2200P_0402_25V7K~D

2200P_0402_25V7K~D

1 2

R1343

R1343 0_0603_5%

0_0603_5%

1 2

@

+3VS_TP+3VS_TP+3VALW

1

2

+3VS_CR +3VS_CR

1

2

C1159

0.1U_0402_10V7K

C1264

0.1U_0402_10V7K

C1204

C1204 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

12

EN_CAM[11]

3.3V_TS_EN[11]

R1177 100K_0402_5%~DR1177 100K_0402_5%~D R1162 100K_0402_5%~DR1162 100K_0402_5%~D

EN_CAM

3.3V_TS_EN

C1203

C1203 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

12 12

+5VALW

12

+3VALW

EN_CAM

3.3V_TS_EN

U718

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

AOZ1331 _DFN_14P

VOUT1 VOUT1

CT1

GND

CT2

VOUT2 VOUT2

GPAD

R2670

R2670 0_0603_5%

0_0603_5%

14 13

12

11

10

9 8

15

1 2

@

C1202

C1202 2200P_0402_25V7K~D

2200P_0402_25V7K~D

1 2

C1281

C1281 2200P_0402_25V7K~D

2200P_0402_25V7K~D

1 2

R2671

R2671 0_0603_5%

0_0603_5%

1 2

@

+3VS_CAM +3VS_CAM

+3VS_TS+3VS_TS

1

C1220

0.1U_0402_10V7K

2

1

C1208

0.1U_0402_10V7K

2

Deeper Sleep, SSD Load Switch 5V_Run, 5V_Audio Load Switch

C1162

C1162 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

SSD_PWREN

12

PCH_ALW_ON

+5VALW

12

C1158

C1158 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

PCH_ALW_ON[33,36]

C C

SSD_PWREN[11]

RUN_ON_EC

A00_1004: Change to short pad.

R1189 0_0402_1%@R1189 0_0402_1%@

1 2

R1187 100K_0402_5%~DR1187 100K_0402_5%~D R1181 100K_0402_5%~D@R1181 100K_0402_5%~D@

+3VALW +3V_PCH

U717

12

PCH_ALW_ON SSD_PWREN

U717

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

AOZ1331 _DFN_14P

VOUT1 VOUT1

CT1

GND

CT2

VOUT2 VOUT2

GPAD

14 13

12

11

10

9 8

15

R1342

R1342 0_0805_5%

0_0805_5%

1 2

C1163

C1163 2200P_0402_25V7K~D

2200P_0402_25V7K~D

1 2

C1292

C1292 2200P_0402_25V7K~D

2200P_0402_25V7K~D

1 2

R1326

R1326 0_0805_5%

0_0805_5%

1 2

@

+3V_PCH

+3.3VDX_SSD+3.3VDX_SSD

1

C1161

0.1U_0402_10V7K

2

1

C1164

0.1U_0402_10V7K

2

RUN_ON_EC[33,36,44]

+3VS

1 2

12

R1141 100K_0402_5%~DR1141 100K_0402_5%~D R290 100K_0402_5%~DR290 100K_0402_5%~D R1140 100K_0402_5%~D@R1140 100K_0402_5%~D@

C1201

C1201 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

12

RUN_ON_EC

+5VALW

PCH_AUDIO_PWR

C1199

C1199 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

12

PCH_AUDIO_PWR RUN_ON_EC PCH_AUDIO_PWR

+5VALW +5VS

U719

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

AOZ1331 _DFN_14P

VOUT1 VOUT1

CT1

GND

CT2

VOUT2 VOUT2

GPAD

14 13

12

11

10

9 8

15

R2669

R2669 0_0805_5%

0_0805_5%

1 2

@

C355

C355 2200P_0402_25V7K~D

2200P_0402_25V7K~D

1 2

C1278

C1278 220P_0402_25V8K

220P_0402_25V8K

1 2

R1320

R1320 0_0603_5%

0_0603_5%

1 2

@

+5VS

+5VS_AUDIO+5VS_AUDIO

1

C352

0.1U_0402_10V7K

2

1

C1200

0.1U_0402_10V7K

2

WiFi, 3V_RUN Load Switch 3V_Audio, 1.8V_Audio Load Switch

C1166

C1166 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

NGFF_ON

+5VALW

RUN_ON_EC

C1160

B B

NGFF_PWREN[11]

AUX_EN_W OWL[36]

C1160 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

D116

2

3

BAT54CW-7-F_SOT323-3~D

+3VALW +3VS_NGFF

U720

12

1

NGFF_ON

U720

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

AOZ1331 _DFN_14P

VOUT1 VOUT1

CT1

GND

CT2

VOUT2 VOUT2

GPAD

14 13

12

11

10

9 8

15

R1344

R1344 0_0805_5%

0_0805_5%

1 2

@

C1167

C1167 2200P_0402_25V7K~D

2200P_0402_25V7K~D

1 2

C1293

C1293 2200P_0402_25V7K~D

2200P_0402_25V7K~D

1 2

R1329

R1329 0_0805_5%

0_0805_5%

1 2

@

LCD, M3 Load Switch

1 2

R1186 100K_0402_5%~DR1186 100K_0402_5%~D

A A

NGFF_ON

LCD_VCC_TEST_EN[36]

ENVDD_PCH[36,5]

1 2

R1026 100K_0402_5%~DR1026 100K_0402_5%~D R1163 100K_0402_5%~DR1163 100K_0402_5%~D

12

D93

D93 BAT54CW-7-F_SOT323-3~D

BAT54CW-7-F_SOT323-3~D

+3VS_NGFF

2

3

ENVDD EN_MPOWER

1

C1215

0.1U_0402_10V7K

2

+3VS+3VS

1

C1216

0.1U_0402_10V7K

2

1

EN_MPOWER[33]

C1231

C1231 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

12

EN_MPOWER

+5VALW

ENVDD

C1165

C1165 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

12

PCH_AUDIO_PWR[11]

U715

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

AOZ1331 _DFN_14P

C1213

C1213 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

12

PCH_AUDIO_PWR

+5VALW

PCH_AUDIO_PWR

C1169

C1169 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

12

14

VOUT1

13

VOUT1

12

CT1

11

GND

10

CT2

9

VOUT2

8

VOUT2

15

GPAD

+3VALW +3VS_AUDIO

U664

+1.8VS

R1322

R1322 0_0805_5%

0_0805_5%

1 2

@

C1230

C1230 2200P_0402_25V7K~D

2200P_0402_25V7K~D

1 2

C1247

C1247 2200P_0402_25V7K~D

2200P_0402_25V7K~D

1 2

R1321

R1321 0_0805_5%

0_0805_5%

1 2

@

U664

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

AOZ1331 _DFN_14P

+LCDVDD

VOUT1 VOUT1

CT1

GND

CT2

VOUT2 VOUT2

GPAD

14 13

12

11

10

9 8

15

R1318

R1318 0_0603_5%

0_0603_5%

1 2

C1212

C1212 1000P_0402_50V7K~D

1000P_0402_50V7K~D

1 2

C1214

C1214 4700P_0402_25V7K

4700P_0402_25V7K

1 2

R1125

R1125 0_0603_5%

0_0603_5%

1 2

1

C1211

0.1U_0402_10V7K

2

@

+3.3V_M+LCDVDD+3VALW +3.3V_M

1

C1219

0.1U_0402_10V7K

2

+3VS_AUDIO

1

C1218

0.1U_0402_10V7K

2

+1.8VS_AUDIO+1.8VS_AUDIO

1

C1217

0.1U_0402_10V7K

2

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2013/07/04 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P29-DC/DC Interface

LA-B441P

1.0

32 50Monday, O ctober 0 6, 2014

1

1.0

A

B

C

D

E

+1.05VDX_MODPHY Load Switch vPro Load Switch

B+B+

2

G

12

R1381

R1381 10K_0402_5%~D

10K_0402_5%~D

MPHY_PW REN#

13

D

Q362

S

DII-DMN65D8LW-7~D

4

Q361

5

SI1553CDL-T1-GE3_SC70-6

3 1

62

10uS for rising and falling

1 1

MPHYP_PW R_EN[11]

MPHYP_PW R_EN

12

@

R1169

R1169 100K_0402_5%~D

100K_0402_5%~D

+1.05V_PCH +1.05VDX_MODPHY

R1379

R1379 330_0402_5%~D

330_0402_5%~D

1 2

R1380

R1380 330_0402_5%~D

330_0402_5%~D

1 2

Q360

SiSA12DN-T1-GE3_POWERPAK8-5

5

1

C1228

0.1U_0402_10V7K

2

4

A00_1004: Change to short pad.

1

C1227

0.01U_0402_16V7K~D

2

1 2 3

1 2

@

0_0805_5%

0_0805_5% R1330

R1330

MLK IC : 5m ohm 1840m A Intel : 6m ohm 1840m A

1

C1209

C1209 10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

2

+1.05V_PCH

1

C1243

0.1U_0402_10V7K~D

2

+1.05V_PCH +1.05VS

@

1 2

0.01_0805_1%~D

0.01_0805_1%~D R1332

R1332

U673

4

VIN

5

VIN

9

VIN

10

VIN

11

VIN

12

VIN

13

VIN

14

VIN

18

VIN

19

VIN

3

GND

NCP4545IMNTWG_QFN18_3X3~D

VCC

VOUT VOUT VOUT

BLEED

Delay

2

6 7 8

15 17

SR

16

EN

1

+5VALW

1

@

C1241

0.1U_0402_10V7K~D

2

A00_1004: Change to short pad.

1 2

R1190 0_0402_1%@R1190 0_0402_1%@

1 2

C1244 1000P_0402_25V8JC1244 1000P_0402_25V8J

1 2

C1242 0.01U_0402_16V7K~D

RUN_ON_EC [32,33,36,44]

@

+1.05VS

12

@

0_0805_5%

R1331

1

C1240

C1240 10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

2

MLK IC : 5m ohm 3414m A Intel : 5m ohm 3414m A

R06_1004: Remove BoM structure, both VPRO/Non-VPRO populated.

Discharge

2 2

MPHY_PW REN#

+1.05VDX_MODPHY

12

R300

R300 470_0402_5%

470_0402_5%

+1.05VDX_MODPHY_D

13

D

Q39

2

DII-DMN65D8LW-7~D

G

S

+1.05V_PCH

1

C1224

C1224 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

CSPSM@

+1.05V_PCH

EN_MPOWER

+5VALW

A00_1004: Change to short pad.

R309 @ 0_0603_5%R309 @ 0_0603_5%

U34

1

VIN

VOUT

2

VIN

VOUT

3

ON

VBIAS

CSPSM@

GND GND

CT

4

APE8937 GN2_DFN8_ 2X2

1 2

7 8

6

5 9

R307 0.01_0603_1%@R307 0.01_0603_1%@

1 2

C218 2200P_0402_25V7K

1 2

CSPSM@

+1.05V_M

1

C219

0.1U_0402_10V7K

2

CSPSM@

+1.05V_M

3 3

R06_0822: Remove BoM structure and use A_ON only.

1 2

RUN_ON_EC[32,33,36,44]

A_ON[36]

R269 0_0402_5%~D@R269 0_0402_5%~D@

1 2

R270 0_0402_1%@R270 0_0402_1%@

EN_MPOWER

12

R272

R272 0_0402_1%@

0_0402_1%@

EN_MPOWER [32]

A00_1004: Change to short pad.

1 2

R271 0_0402_5%~D

PCH_ALW_ON[32,36]

4 4

A

R271 0_0402_5%~D

@

B

EN_+1.05SP [45]

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/07/04 2013/10/28

C

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P29-DC/DC Interface

LA-B441P

33 50Monday, O ctober 06 , 2014

E

1.0

A

FD3

FD4

FD1

FD2

FIDUCAL@

FIDUCIAL@

1

H1

1 1

2 2

H1

H_2P0

@

1

H6

H_3P3

@

1

H11

H_3P3

@

1

H16

H_3P3

@

1

R06_0822: Stand off screw hole change form 3.2mm to 3.3 mm. R06_0826: Add H26 for SSD bracket.

H_2P0

@

H_2P0

@

H_3P3

@

H_1P8N

@

H7

1

H12

H_2P0

@

1

H17

H_2P0

@

1

FD4

FIDUCAL@

FIDUCIAL@

1

H4

H3

H_2P0

@

1

H9

H10

H_2P0

@

H13

H_3P3

@

1

H18

H_2P0

@

1

H10

H_3P3

@

1

H14

H15

H_3P3

@

1

H23

H19

1

@

H_2P3X1P8N

H26

1

@

H_3P2X0P8

1

B

C

D

E

Keyboard Controller board + DMIC

JKB1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

GND GND

E-T_6710K-Y15M-31L

CONN@

Place close to JKB1

+5VALW+3VALW

1

C375

0.1U_0402_25V6K~D

2

16 17

1

C376

0.1U_0402_25V6K~D

2

+3VS

1

C377

2

0.1U_0402_25V6K~D

White

Amber

+5VALW

+5VS

+3VALW

+3VS

KB_DET#[11] BC_INT#_ECE1117[36] BC_DAT_ECE1117[36] BC_CLK_ECE1117[36] BAT2_LED#[36]

BAT1_LED#[36] DMIC_DAT_CODEC[24] DMIC_CLK_CODEC[24]

3 3

RTC Battery With Charge Function

RTC Battery Conn

+RTCBATT

RTCR1

RTCR1 1K_0402_5%~D

2

1K_0402_5%~D

1 2

W=20mils

1

3

1

2

D122

D122 BAS40-04_SOT23-3

BAS40-04_SOT23-3

CH95

CH95 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

A

+RTCVCC

1

EMI@

C1309

15P_0402_50V8J

2

RF Reserved.

+3VLP

4 4

W=20mils W=20mils

+RTCBATT

C2973

1

20mil

2

0.1U_0402_16V4Z

JRTC1

1

2

3

G1

4

G2

CONN@

ACES_50278-00201-001

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

C

2013/07/04 2013/10/28

Compal Secr et Data

Deciphered Date

D

Place at trace Source, Middle and Ended point.

Intel recommend for EMI

B+ B+ B+

EMI@

1

C1273

0.1U_0402_16V7K~D

2

Title

Size Document Number Rev

Date: Sheet of

EMI@

1

C1274

0.1U_0402_16V7K~D

2

Compal Electronics, Inc.

P30-SCREWH/KB/RTC

LA-B441P

1

2

E

EMI@

C1275

0.1U_0402_16V7K~D

34 50Saturday, October 04, 2014

1.0

5

D D

C C

4

3

2

1

+1.05VS_VCCST

12

A00_1004: Change to short pad.

1 2

RESET_OUT#[11,36]

B B

Touchpad CONN

+3VS_TP

JTP1

1

+3VS_TP+3VS_TP

2 3 4 5 6 7 8

9

10

12

R1299

R1299 100K_0402_5%~D

100K_0402_5%~D

2 3 4 5 6 7 8

GND1 GND2

E-T_6705K-Y08N-40L

CONN@

I2C1_SDA_TP

@MD9

@

PTP_INT#_R

2

3

MD9

PTP_INT#[36,5]

@ MD10

@

1

5

PTP_DIS#[37] DAT_TP_SIO[36] CLK_TP_SIO[36]

PESD5V0U2BT_SOT23-3

A A

3

1

2

1 3

D

2

G

Q40

Q40 DII-DMN65D8LW-7~D

DII-DMN65D8LW-7~D

I2C1_SCK_TP

MD10 PESD5V0U2BT_SOT23-3

PESD5V0U2BT_SOT23-3

PTP_INT#_R

S

+3VS_TP

EMI@

1

C7

C1225

2

15P_0402_50V8J

1U_0402_6.3V6K~D

A00_1004: Change JTP1 footprint from ACES_50506-00841-P01 to E-T_6705K-Y08N-40L for multiple sources SMT concern.

4

I2C1_SDA[11]

I2C1_SCK[11]

+3VS +3VS_TP

2

G

QH7B

61

S

D

S

D

DMN66D0LDW-7_SOT363-6

1 2

@

RH461 0_0402_5%~D

RH456 0_0402_5%~D

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

3

5

SGD

DMN66D0LDW-7_SOT363-6

1 2

@

Issued Date

1 2

R1104 10K_0402_5%~DR1104 10K_0402_5%~D

I2C1_SDA_TP

1 2

R1105 10K_0402_5%~DR1105 10K_0402_5%~D

QH7A

34

I2C1_SCK_TP

2013/07/04 2013/10/28

R1353 0_0402_1%@R1353 0_0402_1%@

Compal Secr et Data

Deciphered Date

2

RESET_OUT#_L

U672

1

NC

2

A

3

GND

74AUP1G07GW_TSSOP5

+3VALW

5

VCC

4

Y

Title

P31-TP/PWERGD/LID

Size Document Number Rev

LA-B441P

Date: Sheet of

R1132

R1132 10K_0402_5%~D

10K_0402_5%~D

1.05VS_VCCST_PG [13]

Compal Electronics, Inc.

35 50Sunday, October 05, 2014

1

35 50Sunday, October 05, 2014

1.0

5

+3VALW_5085

1 2

RE52 2.2K_0402_5%RE52 2.2K_0402_5%

1 2

RE53 2.2K_0402_5%RE53 2.2K_0402_5%

JDEG

+3VS_TP

PBTN_SW#[20,21,23]

LID_SW_IN#[23]

USB0_D ET#[23]

+3.3V_ALW_DEG

JDEG1

1 2 3 4 5

11

6

G1

12

7

G2

8 9

10

HB_A53 1015 -SCHR2 1

CONN@

JLPDE1

1 2 3 4 5

11

6

G1

12

7

G2

8 9

10

HB_A53 1015 -SCHR2 1

CONN@

1 2

RE6 4.7K_0402_5%~DRE6 4.7K _0402_5%~D

1 2

RE7 4.7K_0402_5%~DRE7 4.7K _0402_5%~D

1 2

RE54 10K_0402_5%@RE54 10K_0402_5%@

1 2

RE58 100K_0402_5%RE58 100K_0402_5%

1 2

RE2 10K_0402_5%RE2 10K_0402 _5%

12

CE21

CE21 1U_0402_6.3V6K

1U_0402_6.3V6K

@

1 2

12

CE22

CE22 1U_0402_6.3V6K

1U_0402_6.3V6K

@

RE76

49.9_0402_1%

1 2 3 4 5 6

MSCLK

7

MSDATA

8 9 10

+3VS

1 2 3

LPC_AD0

4

LPC_AD1

5

LPC_AD2

6

LPC_AD3

7

LPC_FRAME#

8

PCH_PLTRST#_EC

9 10

D D

C C

B B

A A

RE2610_0402_5% RE2610_0402_5%

+3VALW_5085

12

678

123

CLK_LPC_DEBUG [10]

PBAT_SMBDAT PBAT_SMBCLK

CLK_TP_SIO DAT_TP_SIO

PCH_PLTRST#_EC LCD_TST RESET_OUT#

+RTCVCC

100K_0402_5%

12

RE31

12

POWER_SW_IN#

RE3310K_0402_5% RE3310K_0402_5%

1U_0402_6.3V6K

12

CE49

+3VALW_5085

100K_0402_5%

12

RE25

LID_CL_SIO#

0.047U_0402_16V4Z

12

CE13

+RTCVCC

100K_0402_5%

12

RE36

12

USB0_D ET_E C#

RE3410K_0402_5% RE3410K_0402_5%

1U_0402_6.3V6K

12

CE56

10K_8P4R_5%

+3VALW_5085

RPE7

4 5

JTAG_TDI JTAG_TMS JTAG_CLK JTAG_TDO

5

10K_0402_5%

12

RE72

RE74

Pin8 5085_TXD for EC Debug pin9 5048_TXD for SBIOS debug

100K_0402_5%

12

RE75@

HOST_DE BUG_TX

+3VALW +3VALW_508 5

10U_0603_6.3V6M

12

CE42

HDA_I2S_SEL = Low ; HDA Mode HDA_I2S_SEL = High ; I2S Mode

+3VALW

100K_0402_5%

12

6

2

RUN_ON_EC

1

PJP15

1 2

PAD-OPEN1x1m

@

1 2

R268

RE84

DMN66D0LDW-7_SOT363-6

QE12A

RUN_ON#

+3VALW_5085

@R268

@

RUNPWROK

4

+RTCVCC

0.1U_0402_25V6

12

Connect PCH, ALS

Connect Touch Pad

Connect Battery

0_0402_5%~D

5

4

A00_1004: Change to short pad.

1 2

RE32 0 _0402_1%@RE32 0_0402 _1%@

0.1U_0402_25V6

12

CE46

CE43

+3VS

10K_0402_5%

12

RE83

DMN66D0LDW-7_SOT363-6

34

QE12B

12

CE38

CE41

MEC_XTAL2

A00_1004: Change to short pad.

0.1U_0402_25V6

3

+RTC_CELL_VBAT

0.1U_0402_25V6

12

CE65

1U_0402_6.3V6K

0.1U_0402_25V6

12

CE63

CE14

1U_0402_6.3V6K

0.1U_0402_25V6

12

CE64

CE17

0.1U_0402_25V6

12

CE40

CE44

SML1_SMBDAT[8] SML1_SMBCLK[8]

CLK_TP_SIO[35]

DAT_TP_SIO[35]

LCD_TST[22] HDA#_I2 S_SE L[24]

LCD_VCC_TEST_EN[32]

PBAT_SMBDAT[39] PBAT_SMBCLK[39]

BEEP[24 ]

BIA_PWM_EC[22] ENVDD_PCH [32,5] FAN1_PWM[29]

USB1_P WR_ EN_EC[30]

SIO_SLP_WLAN#[11]

BC_CLK_ECE1117[34] BC_DAT_ECE1117[34] BC_INT#_ECE1117[34]

RE62 0_ 0402_1%

CLK_TP_SIO DAT_TP_SIO LCD_TST

PBAT_SMBDAT PBAT_SMBCLK

JTAG_TDI JTAG_TDO JTAG_CLK JTAG_TMS JTAG_RST#

FAN1_TACH[29]

LID_CL_SIO# SUS_ON

SUSACK#[11]

USB1_P WR_ EN_EC

ACAV_IN_NBACAV_IN_NBACAV_IN

T124@T12 4@

SIO_SLP_S5#[11,21]

PS_ID[39]

BC_DAT_ECE1117

SIO_EXT_SMI#[11] SIO_RCIN#[11] IRQ_SERIRQ[11]

PCH_PLTRST#_EC

PCH_PLTRST#_EC[11,20,23,27,2 8]

CLK_PCI_MEC

CLK_PCI_MEC[10]

LPC_FRAME#

LPC_FRAME#[8]

LPC_AD0

LPC_AD0[8]

LPC_AD1

LPC_AD1[8]

LPC_AD2

LPC_AD2[8]

LPC_AD3

LPC_AD3[8] CLKRUN#[11] SIO_EXT_SCI#[11]

MEC_XTAL1

12

MEC_XTAL2_R

@

R06_0827: Change P/N to SA00006YH20.

UE5

B64

VBAT

A22

H_VTR

A58

VTR_ADC

B3

VTR

A11

VTR

A26

VTR

B35

VTR

A41

VTR

A52

VTR

A5

GPIO007/I2C1D_DATA/PS2_CLK0 B/I2C3A_DATA

B6

GPIO010/I2C1D_CLK/ PS2_DAT0B/I2C3A_CLK/GANG_DATA0

A37

GPIO110/PS2_CLK2/ GPTP-IN6

B40

GPIO111/PS2_DAT2/GPTP-OUT6

A38

GPIO112/PS2_CLK1A

B41

GPIO113/PS2_DAT1A

A39

GPIO114/PS2_CLK0A

B42

GPIO115/PS2_DAT0A

B59

GPIO154/I2C1C_DATA/PS2_CLK1 B/GANG_DATA5

A56

GPIO155/I2C1C_CLK/ PS2_DAT1B/GANG_DATA6

A51

GPIO145/I2C1K_DATA/JTAG_TDI

B55

GPIO146/I2C1K_CLK /JTAG_TDO

B56

GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK

A53

GPIO150/I2C1J_CL K/I2C2C_CLK/JTAG_TMS

B47

JTAG_RST#

B22

GPIO050/FAN_TACH1/GTACH0/GANG_START

A21

GPIO051/FAN_TACH2/GANG _MODE

B23

GPIO052/FAN_TACH3/GTACH1/GANG_ERROR

B24

GPIO053/PWM0

A23

GPIO054/PWM1/GPW M1

B25

GPIO055/PWM2

A24

GPIO056/PWM3/GPW M0

A43

GPIO123/BCM_A_CLK

B45

GPIO122/BCM_A_DAT

A42

GPIO121/BCM_A_INT#

B20

GPIO032/BCM_E_CLK

A18

GPIO031/GPTP-OUT2/BCM_E_DAT

B19

GPIO030/GPTP-IN2/BCM_E_INT#/GANG_DATA7

A20

GPIO047/LSBCM_D_CLK

B21

GPIO046/LSBCM_D_DAT/GANG_STROBE

A19

GPIO045/LSBCM_D_INT#

A6

GPIO011/nSMI

A27

GPIO061/LPCPD#

A28

SER_IRQ

B30

LRESET#

A29

PCI_CLK

B31

LFRAME#

A30

LAD0

B32

LAD1

A31

LAD2

B33

LAD3

A32

CLKRUN#

A33

GPIO100/NEC_SCI

A61

XTAL1

A62

XTAL2

AGND

VSS

VSS_ADC

B66

B11

B60

15mil

GPIO120/UART_TX/V2P_COUT_HI1

GPIO124/GPTP-OUT5/UART_RX/V2P_COUT_LO1

GPIO060/KBRST/BCM_B_INT#

GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP

GPIO117/MSCLK/V2P_COUT_HI

GPIO001/ECSPI_CS1/3 2KHZ_OUT

GPIO125/GPTP-IN5/PECI_REQUEST#/GANG_BUSY

GPIO151/GPTP-IN4/GANG_DATA2

GPIO005/I2C1B_DATA/BCM_B_DAT

GPIO006/I2C1B_CLK /BCM_B_CLK

GPIO012/I2C1H_DATA/I2C2D_DATA

GPIO013/I2C1H_CLK/I2C2 D_CLK/GANG_DATA3

GPIO130/I2C2A_DATA/BCM_C_DAT

GPIO131/I2C2A_CLK/BCM_ C_CLK

GPIO141/I2C1F_DATA/I2C2B_DATA

GPIO142/I2C1F_CLK /I2C2B_CLK

VSS_RO

H_VSS

B18

PROCHOT_IN#/PROCHOT_IO#

EP

MEC5085-LZY-HST01 _DQFN132_11X1 1

C1

VR_CAP

B12

B54

4.7U_0603_6.3V6K

+VR_CAP

12

CE45

GPIO021/RC_ID1 GPIO020/RC_ID2

GPIO014/GPTP-IN7/RC_ID3

GPIO025/UART_CLK

VCC_PW RGD

GPIO101/ECGP_SCLK GPIO103/ECGP_MISO GPIO105/ECGP_MOSI

GPIO102/BCM_C_INT#

GPIO104/SLP_S0#

GPIO106

GPIO127/A20M

GPIO156/LED1/GANG_DATA1

GPIO157/LED0

GPIO153/LED2/GANG_DATA4

GPIO027/GPTP-OUT1

GPIO026/GPTP-IN1

GPIO015/GPTP-OUT7

GPIO016/GPTP-IN8

GPIO017/GPTP-OUT8

GPIO107/NRESET_OUT

GPIO152/GPTP-OUT4

GPIO003/I2C1A_DATA

GPIO004/I2C1A_CLK

GPIO132/I2C1G_DATA

GPIO140/I2C1G_CLK

GPIO143/I2C1E_DATA

GPIO144/I2C1E_CLK

SYSPWR_PRES

VCI_OVRD _IN

VCI_OUT VCI_IN0# VCI_IN1# VCI_IN2# VCI_IN3#

VREF_PE CI

PECI_DAT

DN1_DP1A/THERM

DP1_DN1A/VREF_T

DN2_DP2A DP2_DN2A DN3_DP3A DP3_DN3A DN4_DP4A DP4_DN4A

THERMTRIP2# GPIO002/THERMTRIP3# GPIO024/THSEL_STRAP

V_ISYS0 V_ISYS1

nFWP

BGP0

VSET

VIN

VCP

A10 B10

BOARD_ID

B8

PCIE_WAKE#

B27 B44

HOST_DE BUG_TX

B46 B26

RUNPWROK

A25 B36

SIO_SLP_S4#

B37

PTP_INT#_EC

B38

USB_PW R_S HR_EN#

A34 A35

SIO_SLP_S3#

A36 A40

MSDATA

B43

MSCLK

A45 B65

FWP#

B57 B1 A55 A1 B28 B2 A8 B9

RUN_ON

A9 B39

RESET_OUT#

A44

A54 B58

A3

MCP23017_I2 CDATA

B4

MCP23017_I2 CCLK

A4 B5 B7 A7 B48 B49

R253 0_0402_1%@R253 0_0402_1%@

A47

CHARGER_SMBDAT

B50

CHARGER_SMBCLK

B52 A49 B53 A50

USB0_P WR_ EN_EC

A59

B62 A64

ACAV_IN

A60 B67

POWER_SW_IN#

A63

BATBTN#

B63

USB0_D ET_EC #

B68

VCI_IN3#

B51 A48

PECI_EC_R

B13

REM_DIODE1_N

A13

REM_DIODE1_P

B14

REM_DIODE2_N

A14

REM_DIODE2_P

A15

REM_DIODE3_N

B16

REM_DIODE3_P

A16

REM_DIODE4_N

B17

REM_DIODE4_P

B15 A17

VSET_50 85

A12 B34

THERMATRIP2#

A2

THERMATRIP3#

B29

THSEL_STRAP

A46 B61 A57

RE64 4.7K_0402_ 5%RE6 4 4.7K_0402_5%

1 2

AC_DIS [40 ]

PCIE_WAKE# [28]

EC_WAKE# [11]

ME_FWP_EC [21] RUNPWROK [20] EN_INVPWR [22] SIO_SLP_S4# [11,21]

USB_PW R_S HR_EN# [23] PCH_ALW_ON [3 2,33] SIO_SLP_S3# [11,21,44,46] PCH_DPWROK [11]

PCH_RSMRST# [11]

PWRBTN_LED# [23] BAT1_LED# [34] BAT2_LED# [34]

ALW_P WRGD _3V_5 V [41] SIO_SLP_A# [11,21] AUD_HP_NB_ SENSE [25]

ME_SUS_PWR_ACK [11 ]

PM_APWROK [11] RESET_OUT# [11,35] PCH_PCIE_WAKE# [11]

AC_PRES ENT [11] SIO_PWRBTN# [11,20]

MCP23017_I2 CDATA [37]

MCP23017_I2 CCLK [37 ] A_ON [33] SIO_EXT_WAKE# [11] SYS_PWROK [11,20]

ALS_INT# [23 ]

CHARGER_SMBDAT [40] CHARGER_SMBCLK [40]

SIO_SLP_SUS# [11]

PBAT_PRES# [39,40]

AUX_EN_W OWL [32 ] USB0_P WR_ EN_EC [23]

ACAV_IN [4 0]

ALWON [41 ]

BATBTN# [31]

1 2

RE61 43_0402_5 %RE61 43_0402 _5%

1 2

CE58 2200P_0402_50V7KCE58 2 200P_0402_50V7K

1 2

CE67 2200P_0402_50V7KCE67 2 200P_0402_50V7K

1 2

CE39 2200P_0402_50V7KCE39 2 200P_0402_50V7K

1 2

CE60 2200P_0402_50V7KCE60 2 200P_0402_50V7K

CE58, CE39, CE60, Place near UE5

I_ADP [40]

H_PROCHO T# [3 9,4 0,42 ,47, 6] I_BATT [40] I_SYS [40]

ESR <2ohms

R06_0905: Change YE1 main source form SJ10000JR00 to SJ10000JV00. R06_1004: Change YE1 from SJ00000JV00 to SJ10000IA00.

1

JTAG1 CONN@

@SHORT PADS~D

JTAG1 CONN@

@SHORT PADS~D

2

RE79 CE54

130K 4700p

4700p 4700p

33K

4700p

8.2K 4700p

4.3K 4700p

2K 1K

4700p

Change CE62 form 27P to 22P and change CE53 form 33P to 27P.

+3VALW_5085

100K_0402_5%

12

RE65

JTAG_RST#

1U_0402_6.3V6K

100_0402_1%

12

RE66@

CE59

A00_1004: Change board ID to A00.

BOARD_ID

+3VALW_5085

RE79

4.3K_0402_5%

1 2

12

CE54

CE54 4700P_0402_25V7K

4700P_0402_25V7K

X01 X0262K X03 X04 A00

REV

32 KHz Clock

MEC_XTAL1 MEC_XTAL2

22P_0402_50V8J

32.768KHZ 9PF Q13FC1350000300

CE62

1

2

+3VALW_5085

12

RE81

RE81 10K_0402_5%

10K_0402_5%

FWP#

@

RE82

RE82 10K_0402_5%

10K_0402_5%

1 2

YE1

CLK_PCI_MEC

10_0402_5%

12

RE80EMI@

EMI@

4.7P_0402_50V8C

EMI@

4.7P_0402_50V8C

12

CE52

Place close pin A29

27P_0402_50V8J

1

2

EMI depop location

CE53

BOARD_ID rise time is measured from 5%~68%.

Security Classification

Issued Date

THIS SHEE T OF ENGI NEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEE T OF ENGI NEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2

RPE5

BC_DAT_ECE1117 PTP_INT#_EC VCI_IN3 # BATBTN#

PCIE_WAKE# MCP23017_I2 CDATA MCP23017_I2 CCLK CHARGER_SMBDAT CHARGER_SMBCLK THERMATRIP3# MSDATA USB1_P WR_ EN_EC USB0_P WR_ EN_EC SUS_ON_EC

R06_0826: Change RE55, RE56 form 10K to 8.2K as EA test result.

Amber

White

GPIO88_SLP_S0# [1 1]

Charger

PECI_EC [6]

Setting for Thermal Design

Thermal diode mapping

5085 Channel

DP1/DN1

DP2/DN2

DN2A/DP2A

DP3/DN3

DP4/DN4

100P_0402_50V8J

12

CE57@

Place QE11 close to BOT Skin1 location CE57 should close to QE11

100P_0402_50V8J

C

12

CE66@

Place QE10 close to DRAM CE66 should close to QE10

100P_0402_50V8J

@

C

CE51

1 2

Place QE8 close to FAN location CE51 should close to QE8

2

PTP_INT#_EC

SIO_SLP_S3#

RUN_ON

A00_1004: Change to short pad.

SIO_SLP_S4# SUS_ON_EC

SUS_ON

1 2

RE57 1K_0402_5%RE5 7 1 K_0402_5%

100K_0402_5%

12

RE63

+1.05VS

0.1U_0402_25V6

CE50

12

PECI_EC_R

@

CE68

47P_0402_50V8J~D@CE68

47P_0402_50V8J~D

1

2

Location

CPU(OTP)

BOT Skin2

BOT Skin1

DRAM

FAN

METR3904W-G_ SC70-3

E

31

QE11

B

2

C

REM_DIODE3_P

QE10

2

B

E

3 1

METR3904W-G_ SC70-3

REM_DIODE3_N

REM_DIODE4_P

2

B

E

QE8

3 1

METR3904W-G_ SC70-3

REM_DIODE4_N

Compal Secret Data

2013/07/04 2013/10/28

Deciphered Date

1 2 3 4 5

100K_0804_8P4R_5%

1 2

RE86 1 0K_0402_5%RE86 10K_0402_5%

1 2

RE71 2 .2K_0402_5%RE71 2.2K_0402_5%

1 2

RE73 2 .2K_0402_5%RE73 2.2K_0402_5%

1 2

RE55 8 .2K_0402_5%RE55 8.2K_0402_5%

1 2

RE56 8 .2K_0402_5%RE56 8.2K_0402_5%

1 2

RE67 1 0K_0402_5%RE67 10K_0402_5%

1 2

RE85 1 0K_0402_5%RE85 10K_0402_5%

1 2

RE59 1 00K_0402_5%RE59 100K_0402_5%

1 2

RE60 1 00K_0402_5%RE60 100K_0402_5%

1 2

RE68 1 00K_0402_5%RE68 100K_0402_5%

DZ4

12

RB751S40T1G_SOD523-2

12

RUN_ON_EC

@

R2490_0402_5%~D@R2490_0402_5%~D

12

@

R2500_0402_1%

12

@

R2520_0402_5%~D@R2520_0402_5%~D

12

@

R2510_0402_1%

+3VLP

CHARGER_SMBCLK

CHARGER_SMBDAT

THSEL_STRAP

1: Channel 1 will provide Thermistor Readings 0: Channel 1 will provide Diode Readings

100P_0402_50V8J

C

12

2

CE48@

B

E

QE4

3 1

METR3904W-G_ SC70-3

Place QE4 close to BOT Skin2 CE48 should close to QE4

+3VALW_5085

+RTCVCC

8 7 6

+3VALW_5085

PTP_INT# [35,5]

RUN_ON_EC [32,33,44]

SUS_ON_EC [46]

+3VS

2

G

QH6B

@

QH6B

@

6 1

S

D

S

D

DMN66D0LDW-7_SOT363-6

1 2

RH453 0_0402_5%~D@ RH453 0_0402_5%~D@

DMN66D0LDW-7_SOT363-6

1 2

RH454 0_0402_5%~D@RH454 0_0402_5%~D@

1 2

RE78 1K_0402_5%RE78 1K_0402_5%

REM_DIODE2_P

REM_DIODE2_N

+1.05VS

1

1 2

ALS_SML CLK

RE87 1.5K_0402_5%@RE87 1.5K_0402_5%@

1 2

ALS_SML DATA

RE88 1.5K_0402_5%@RE88 1.5K_0402_5%@

QH6A

3 4

ALS_SML CLK

5

@

ALS_SML DATA

SGD

ALS_SML CLK [23]

Connect ALS

ALS_SML DATA [23]

0.1U_0402_25V6

12

CE55

VSET_50 85

1.5K_0402_1%

12

RE77

Rest=1.5K , Tp=88 degree

2

B

QE3

METR3904W-G_ SC70-3

+3VALW_5085

8.2K_0402_5%

12

RE69

MMST3904-7-F_SOT323-3

1

C

2

QE9

B

E

3

REM_DIODE1_P

REM_DIODE1_N

THERMATRIP2#

12

36 50Sunday, October 05, 2014

0.1U_0402_25V6

100P_0402_50V8J

C

CE47@

1 2

E

3 1

Place QE3 close to CPU CE47 should close to QE3

1 2

RE70 2 .2K_0402_5%RE70 2.2K_0402_5 %

H_THERMTR IP#[11]

Compal Electronics, Inc .

Title

P32-EC ENE-KB9012

Size Document Number Rev

LA-B441P

Date: Sheet of

1

+3VS

CE61

1.0

5

D D

4

3

2

1

+3VALW +3VALW_23017

+3VALW_23017

RE14 100K _0402_5%RE14 100K _0402_5%

1 2 1 2

RE13 100K _0402_5%RE13 100K _0402_5%

C C

B B

WLAN_WIGIG60GHZ_DIS#

BT_RADIO_DIS#

Device Address: b 0,1,0,0,A2,A1,A0,0 0x42

+3VALW_23017

PANEL_BKEN_EC[22]

BATT_LED#_LV5[31] BATT_LED#_LV4[31] BATT_LED#_LV3[31] BATT_LED#_LV2[31] BATT_LED#_LV1[31]

MCP23017_I 2CDATA[36]

MCP23017_I 2CCLK[36]

RE27 10K_0402_5%RE27 10K_0402_5% RE23 10K_0402_5%RE23 10K_0402_5% RE22 10K_0402_5%RE22 10K_0402_5%

RE24 10K_0402_5%RE24 10K_0402_5%

Ensure rise time within 66ms. (fast than 0.05V/ms)

1 2 1 2 1 2

1 2

12

10U_0603_6.3V6M

CE4

PJP14

1 2

PAD-OPEN1x1m

@

4 3 2

1 28 27 26 25

9

8

16 15

11 12 13

14

5

UE4

GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0

SDA SCL

INTA INTB

A0 A1 A2

RESET

MCP23017T- E-ML_QFN28_6X 6

VDD

NC/SO

VSS(Ground)

GPA0 GPA1 GPA2 GPA3 GPA4 GPA5 GPA6 GPA7

NC

0.1U_0402_25V6

12

CE3

17 18 19 20 21 22

WLAN_WIGIG60GHZ_DIS#

23

BT_RADIO_DIS#

24

10 7

6

CE10

T125@ T125@

NB_MUTE# [24,25] PTP_DIS# [35]

WLAN_WIGIG60GHZ_DIS# [28] BT_RADIO_DIS# [28]

TP_PW_EN [ 32]

A A

Security Cla ssification

Security Classi fication

Issued Date

THIS SHEET OF ENGI NEERING DRAWING I S THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGI NEERING DRAWING I S THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2013/07/04 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P32-MCP23017

LA-B441P

1

1.0

37 50Saturday, October 04, 2014

1.0

5

D D

4

3

2

1

DC IN

NVDC CHARGER BQ24777

Page 40

B+

+3VALW: TDC:2.94A +5VALW: TDC:6.3A TPS51285

+1.5VS: TDC:0.0021A

C C

TLV62150

+3VLAW

+5VALW

Page 41

+1.5VS

Page 44

Battery (2S2P)

+1.8VS: TDC:0.1246A TLV62150

Page 44

+1.05V_PCH: TDC:3.5A SY8206D

Page 45

+1.35V_DDR: TDC:4.48A +0.675VS: TDC:0.7A G5616

B B

Page 46

+VCC_CORE TDC: 10A TPS51624RSM

Page 47

+1.8VS

+1.05V_PCH

+1.35V_DDR

+0.675VS

+VCC_CORE

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

3

2011/06/02 2013/10/28

Compal Secr et Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P33-PWR_Block_Diagram

LA-9261P

1

38 50Monday, October 06, 2014

0.1

A

PL100

EMC

HCB2012KF-121T50_0805

1 2

PL101

EMC

HCB2012KF-121T50_0805

12

1 2

1000P_0402_50V7K

PC101

EMC

12

+PBATT

PC100

1 1

EMC

0.01U_0402_25V7K

B

C

D

PBATT1 connector

SMART Battery:

1.BATT++

2.BATT++

3.CLK_SMB

4.DAT_SMB

5.BAT_PRS

6.SYS_PRES

7.BAT_ALERT

8.GND

9.GND

10.GND

11.GND

2 2

12

PC102

2200P_0402_50V7K

EMC

11

GND

10

GND

9

8

7

6

5

4

3

2

1

JBATT1

JBATT1 FOX_GS73091-10272-7H

FOX_GS73091-10272-7H

CONN@

BATT_PRS DAT_SMB CLK_SMB

PBATT+_C

1

2

3

PD100

EMC

1

2

3

PD101

EMC

TVNST52302AB0_SOT523-3

PRP100

18 27 36 45

100_0804_8P4R_5%

+3VALW

12

PR100

100K_0402_5%

PBAT_PRES# [36,40] PBAT_SMBDAT [36] PBAT_SMBCLK [36]

+3VALW

PR101

@PR101

@

1 2

0_0402_5%

PL102

EMC

BLM15AG102SN1D_2P

12

PR104

12

PD102

EMC

AZ5125-01H.R7G_SOD523-2

JP100

7

GND2

6

3 3

GND1

5

4

3

2

1

ACES_88266-05001

CONN@

+DCIN_JACK

NB_PSID

-DCIN_JACK

12

PC103

1000P_0603_50V7K

EMC

12

PC105

PC104

EMC

100P_0402_50V8J

1000P_0402_50V7K

PL103

EMC

HCB2012KF-121T50_0805

1 2

PL104

EMC

HCB2012KF-121T50_0805

1 2

12

100K_0402_1%

15K_0402_1%

+DC_IN

12

PC106

1000P_0402_50V7K

EMC

PR104

1 2

PR106

1 2

12

PC108

PC107

EMC

10U_0805_25V6K

100P_0402_50V8J

12

PR107

@ PR107

@

4.7K_0805_5%

1 3

2

B

D

2

E

3 1

S

PQ100

PQ100 FDV301N_G_NL_SOT23-3

FDV301N_G_NL_SOT23-3

G

C

PQ101

PQ101 MMST3904-7-F_SOT323

MMST3904-7-F_SOT323

PR103

33_0402_5%

1 2

PR105

1 2

10K_0402_1%

Battery protection:

asserts H_PROCHOT# when adaptor is unplugged, keep low for 10ms till SW PROCHOT# is issued by EC

+DC_IN

12

PR110

@ PR110

@

1M_0402_1%

12

PR112

@ PR112

@

1M_0402_1%

+5VALW

2

12

PR111

@ PR111

@

10K_0402_1%

61

PQ102A

@ PQ102A

@

PR102

2.2K_0402_5%

1 2

+3VALW

Follow Derating A08

PC109

@ PC109

@

1 2

1U_0603_10V6K

PR113

@ PR113

@

2N7002KDWH_SOT363-6

PS_ID [36]

12

100K_0402_1%

Other component(37.1)

Erp lot6 Circuit

+DC_IN

PR116

@PR116

@

1M_0402_1%

12

PR109

@

3.3K_1206_5%

61

2

PQ103A

@

2N7002KDWH_SOT363-6

H_PROCHOT#[36,40,42,47,6]

+DC_IN

3

5

PQ102B

@ PQ102B

@

4

2N7002KDWH_SOT363-6

0.1U_0402_25V6

@

PR114

200K_0402_1%

@

PC110

12

5

12

@

PR108

1M_0402_1%

3

PQ103B

@

4

2N7002KDWH_SOT363-6

12

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

2013/04/10 2014/05/01

C

Compal Secr et Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR_DCIN/BATT CONN

LA-B072P

D

39 50Monday, October 06, 2014

2.0

A

B

C

D

PQ205

CHAGER_SRC+PWR_SRC_AC

5

4

123

5

4

123

BATDRV#

12

PC211

EMC PC211

EMC

2200P_0402_50V7K

SIR472DP-T1-GE3_POWERPAK8-5

SIR472DP-T1-GE3_POWERPAK8-5 PQ203

PQ203

EMC

EMC PC224

EMC

12

PC208

PC209

10U_0805_25V6K

PL201

3.3UH_6.3A_20%_7X7X3_M

1 2

12

PR221

4.7_1206_5%

12

PC224 1000P_0603_50V7K

1000P_0603_50V7K

+VCHGR

BATDRV#

12

PC213

PC212

10U_0805_25V6K

B+

PC225

0.1U_0402_25V6

1 2

GNDA_CHG GNDA_CHG

12

PC232

PC231

10U_0805_25V6K

Near PL201

12

PC215

PC214

@ PC214

@

10U_0805_25V6K

PR219

0.01_1206_1%

4

3

PC226

0.1U_0402_25V6

1 2

PQ204

SI4835DDY-T1-E3_SO8

1 2 3 6

4

EMCPC229

EMC

EMCPC228

EMC

12

PC228

10U_0805_25V6K

1

2

8 7

5

12

0.1U_0603_25V7K

EMCPC219

EMC

PC219

0.1U_0402_25V6

PC229

0.1U_0603_25V7K

+VCHGR

12

0.1U_0603_25V7K

@

1 2

PC227

EMCPC230

EMC

12

PC230

0.1U_0603_25V7K

12

10U_0805_25V6K

PC221

PC220

12

PC233

PC234

10U_0805_25V6K

12

10U_0805_25V6K

PC235

PC222

@ PC235

@

12

10U_0805_25V6K

PC236

PC237

@ PC236

@

@ PC237

@

+PBATT

PQ201

CSD87312Q3E_SON8-4

0.022U_0603_50V7K

2

G

PQ202B

GNDA_CHG

CSD87312Q3E_SON8-4

12

PR203

4.7_0402_1%

DCX124EK-7-F_SC74R-6

4 3

AC_DIS [ 36]

13

D

PQ206

PQ206 DMN65D8LW-7_SOT323-3

DMN65D8LW-7_SOT323-3

S

CHARGER_SMBDAT[36]

CHARGER_SMBCLK[36]

PR214 0_0402_5%@ PR214 0_0402_5%@

1 2

PR217 0_0402_5%@ PR217 0_0402_5%@

1 2

PR218 0_0402_5%@ PR218 0_0402_5%@

1 2

H_PROCHOT#[36,39,42,47,6]

PBAT_PRES#[36,39]

+DC_IN

12

PC200

PR223

PR225

GNDA_CHG

PC200

5

I_ADP[36]

I_BATT[36]

I_SYS[36]

BQ24777_REGN

12

1 1

16

PQ202A

DCX124EK-7-F_SC74R-6

CHARGER_SMBCLK CHARGER_SMBDAT pull up 10K in HW side

2 2

ACAV_IN[36]

TI FAE_Andrew suggest Cell pin set the voltage of

3 3

three cell (13.5V) for OVP

1 2

PR212

100K_0402_1%

PR213

@ PR213

@

0_0402_5%

PR215

154K_0402_1%

BQ24777_REGN

12

GNDA_CHG

121K_0402_1%

1K_0402_1%

@PR225

@

D11D2

G2S

PR210

6.49K_0402_1%

1 2

PC207

0.1U_0402_25V6

GNDA_CHG

3

4

12

PC201

0.1U_0402_25V6

12

PR204

4.02K_0402_1%

+DC_IN

12

PR209

34K_0402_1%

1 2

12

PC217

PC216

PC218

1 2

@ PC218

@

100P_0402_50V8J

PR216 0_0402_5%@ PR216 0_0402_5%@

1 2

PR224 0_0402_5%@ PR224 0_0402_5%@

+SDC_IN

SDMK0340L-7-F_SOD323-2

+PBATT

SDMK0340L-7-F_SOD323-2

+DC_IN

PR208

10_1206_5%

4.02K_0402_1%

PC206

1U_0805_25V6K

PR226 0_0402_5%@ PR226 0_0402_5%@

1 2

PR227 0_0402_5%@ PR227 0_0402_5%@

12

PR229

1 2

20K_0402_1%

PD200

PD201

PR207

12

@PR205

@

0_0402_5%

12

PC202

12

1U_0603_25V6K

+DCIN

PC202

1 2

28

11

12

10

13

14

15

16

29

GNDA_CHG

12

PR202

0.01_1206_1%

4

3

CSSP_1

PR205

1 2

PC203

0.1U_0402_25V6

1 2

4

2

ACP

VCC

ACDRV

3

CMSRC

6

ACDET

SDA

SCL

5

ACOK

7

IADP

8

IDCHG

9

PMON

/PROCHOT

CMPIN

CMPOUT

/BATPRES

CELL

PWPD

PU200

PU200 BQ24777RUYR_WQFN28_4x4

BQ24777RUYR_WQFN28_4x4

PJP200

@PJP200

@

1 2

PAD-OPEN1x1m

1

ACN

REGN

BTST

HIDRV

PHASE

LODRV

/BATDRV

1

2

CSSN_1

1 2

GND

NC

SRP

SRN

BAT

PR206

@PR206

@

0_0402_5%

PC204

0.1U_0402_25V6

1 2

24

25

26

27

23

22

21

20

19

18

17

HCB2012KF-121T50_0805

GNDA_CHGGNDA_CHG

BQ24777_REGN

PR211

2.2_0603_5%

1 2

CHG_BTS CHG_BTS_C

CHG_UGATE

CHG_SW

CHG_LGATE

PR228

1 2

BQ24777_REGN

10K_0402_1%

PR220

4.02K_0402_1%

1 2

PR222

10_0603_1%

12

PC223

+PBATT

1U_0603_25V6K

GNDA_CHG

PL200

EMCPL200

EMC

1 2

PC205

1U_0603_10V6K

1 2

PC210

0.047U_0603_25V7M

1 2

SI7716ADN-T1-GE3_POWERPAK8-5

Charger controller(40.1), Support component(40.2)

4 4

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONI CS, INC.

C

Title

Size D ocument Number Rev

Date: Sheet of

Compal Electronics, Inc.

Charger

LA-A904P

D

40 50Monday, October 06, 2014

0.1

5

4

3

2

1

+3VLP

PC300

4.7U_0603_6.3V6K

1 2

D D

PR301

FB_5V

2

VFB1

VO114DRVL1

PR301

158K_0402_1%

PR303

100K_0402_1%

1 2

12

PR305

9.53K_0402_1%

CS1

1

TP

CS1

EN1

VCLK

SW1

VBST1

DRVH1

15

+5VALWP

12

21

20

19

18

LX_5V

17

BST_5V

16

UG_5V

PR315

@ PR315

@

0_0402_5%

1 2

PR306 200_0402_1%PR306 200_0402_1%

1 2

PR308

0_0603_5%

1 2

LG_5V

3V/5VALW_EN

PC306

0.1U_0402_25V6

1 2

12

PQ301

CSD87330Q3D_SON8-7

PQ301

2

3

4

3/5V_B+

PC315

10U_0805_25V6K

1

PL304

7 6 5

8

12

EMC

12

EMC

PL304

3.3UH_6.3A_20%_7X7X3_M

1 2

PR310

4.7_0805_5%

PC310

680P_0603_50V8J

+5VALWP

1

+

PC308

2

150U_B2_6.3VM_R35M

PR300

69.8K_0402_1%

1 2

PL303

EMC

HCB2012KF-121T50_0805

1 2

PL300

EMC

HCB2012KF-121T50_0805

B+

1 2

PC314

0.1U_0402_25V6

C C

EMC

+3VALWP

B B

3/5V_B+

12

EMC

3/5V_B+

12

PC313

PC303

10U_0805_25V6K

2200P_0402_50V7K

PQ300

CSD87330Q3D_SON8-7

PL301

2.2UH_7.8A_20%_7X7X3_M

1

+

PC307

2

150U_B2_6.3VM_R35M

12

PR309

4.7_0805_5%

12

PC309

680P_0603_50V8J

EMCEMC

7 6 5

ALW_PW RGD_3V_5V[36]

1

2

+3VALWP

3

4

8

PC305

0.1U_0402_25V6

1 2

3V/5VALW_EN

PR312

@ PR312

@

0_0402_5%

1 2

PR311

100K_0402_1%

PR307

0_0603_5%

1 2

100K_0402_1%

1 2

LX_3V

BST_3V

UG_3V

LG_3V

3/5V_B+

PR302

PR304

5.1K_0402_1%

PU300

6

EN2

7

PGOOD

8

SW2

9

VBST2

10

DRVH2

VFB=2V

12

CS2

5

CS2

TPS51285BRUKR_QFN20_3X3

DRVL2

11

VFB=2V

FB_3V

3

4

VFB2

VREG3

VREG5

VIN

13

12

PC311

3.3VALWP TDC 2.94A Peak Current 4.2A

ALWON[36]

PR314

2.2K_0402_5%

1 2

3V/5VALW_EN

OCP current 6.6A

12

PC312

@ PC312

@

4.7U_0603_6.3V6M

A A

3V/5V controller(35.1), Support component(35.2)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

PC311

4.7U_0603_6.3V6K

Compal Secret Data

2011/06/02 2013/10/28

Compal Secret Data

Deciphered Date

PJP300@

JUMP_43X118

112

PJP301@

JUMP_43X118

112

2

5VALWP

+5VALW+5VALWP

TDC 6.3A Peak Current 9.0A OCP current 10.7A

+3VALW+3VALWP

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Date: Sheet of

Compal Electronics, Inc.

P36-PWR_+3.3/5V_VR

LA-9261P

1

0.1

41 50Monday, October 06, 2014

0.1

5

D D

4

3

2

1

2

G

PC51

0.47U_0603_16V7K

PR452

22.1K_0402_1%

1 2

+1.05V_M

PR319

@PR319

@

1.91K_0402_1%

1 2

PQ409A

61

DMN66D0LDW-7_SOT363-6

D

S

PR461

@PR461

@

0_0402_5%

H_PROCHOT# [36,39,40,47,6]

+3VALW

4

PU406

1

2

Y

+3VALW

B

A

+3VALW

5

P

G

3

5

P

G

3

PC433

0.1U_0402_10V7K

1 2

4

Y

PU405

M74VHC1GT00DFT2G_SC70-5

PC434

0.1U_0402_10V7K

1 2

1

B

2

A

12

PR447

8

PU404B

PU404B LM393DMR2G_MICRO8

LM393DMR2G_MICRO8

P

+

O

-

G

4

PR449

1M_0402_1%

1 2

LM393DMR2G_MICRO8

8

3

P

+

2

-

G

4

PR447

1M_0402_1%

1 2

7

FAST_COMP_OUT

+3VALW

PU404A

1

O

SLOW_COMP_OUT

+3VALW

12

PR448

10K_0402_1%

DMN66D0LDW-7_SOT363-6

12

PR455

10K_0402_1%

S

PQ409B

G

+3VALW

12

PR450

@

10K_0402_1%

D

34

5

M74VHC1GT00DFT2G_SC70-5

3/5V_B+

PC429

@

+3VALW

PR460

48.7K_0402_1%

PR458

42.2K_0402_1%

12

0.01UF_0402_25V7K

BATT_VREF

12

BATT_VREF

12

5

6

1 2

PC324

1U_0603_10V6K

12

PC428

PR445

@

232K_0402_1%

100P_0402_50V8J

12

PC302

C C

PU404_Main source PQ409A open at 3/5V_B+ below 5.73V and 3/5V_B+ recover 6.05V PA409A close

PU404_2nd_source PQ409A open at 3/5V_B+ below 5.72V and 3/5V_B+ recover 6.05V PA409A close

PU404_3rd_source PQ409A open at 3/5V_B+ below 5.73V and 3/5V_B+ recover 6.04V PA409A close

B B

PC302

PR451

82K_0402_1%

1000P_0402_50V7K

3/5V_B+ +3VALW

12

PR457

232K_0402_1%

12

PC323

PR456

82K_0402_1%

0.1U_0402_25V6

Component(37.1)

A A

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

2011/06/02 2013/10/28

3

Compal Secret Data

Deciphered Dat e

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P37-Blank

LA-9261P

0.1

42 50Monday, October 06, 2014

1

0.1

5

D D

C C

4

3

2

1

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2011/06/02 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P38-Blank

LA-9261P

1

0.1

43 50Monday, October 06, 2014

0.1

A

PR410

@PR410

@

0_0402_5%

RUN_ON_EC[32,33,36,44]

SIO_SLP_S3#[11,21,36,44,46]

1 1

1 2

PR400

@PR400

@

0_0402_5%

1 2

PC400

@

0.1U_0402_25V6

B+=NVDC 2S

PL400

EMC

HCB1608KF-121T30_0603

1 2

B+

12

PC404

PC405

0.1U_0402_25V6

EMC

2200P_0402_50V7K

2 2

+1.5V_B+

12

PC401

10U_0805_25V6K

SS_1.5V

12

PC406

3300P_0402_50V7-K

Fsw=1.25MHz @ Fsw net to 3V Css=Tss*(2.5uA/1.25V) (F) Tss=1.65mS

B

C

D

+1.5VSP

+1.5VS

12

EN_1.5V

13

15

12

PVIN

11

PVIN

10

AVIN

9

SS/TR

14

EN

VOS

PU400

PU400 TLV62150RGTR_QFN16_3X3

TLV62150RGTR_QFN16_3X3

DEF

FSW

8

7

12

PR412

@ PR412

@

+1.5VSP

AGND

6

0_0402_5%

17

TP

PGND16PGND

1

SW_1.5V

SW

2

SW

3

SW

4

1.5VS_PWRO K

PG

FB

5

FB_1.5V

PR404

@ PR404

@

100K_0402_5%

+3VS

12

PL401

2.2UH_1239AS-H-2R2N-P2_1.3A _30%

1 2

12

Rup

12

PR402

4.7_0805_5%

EMC

SNUB_1.5V

12

PC407

PC407 680P_0402_50V7K

680P_0402_50V7K

EMC

12

VFB=0.8V Vout=0.8V* (1+Rup/Rdown)

Vout=1.509V

12

PR401

88.7K_0402_1%

Rdown

PR403

PR403 100K_0402_1%

100K_0402_1%

+1.5VSP

12

PC403

PC402

22U_0805_6.3VAM

22P_0402_50V8J

1.5V controller(35.31), Support component(35.32)

TDC 2.1mA Peak Current 3mA OCP setting 1.4A(Fix)

PJP400

@PJP400

@

2

112

JUMP_43X39

+1.5VS

PR411

@PR411

@

0_0402_5%

RUN_ON_EC[32,33,36,44]

SIO_SLP_S3#[11,21,36,44,46]

3 3

1 2

PR405

@PR405

@

0_0402_5%

1 2

12

PC408

@

0.1U_0402_25V6

B+=NVDC 2S

PL402

EMC

HCB1608KF-121T30_0603

1 2

B+

12

PC412

0.1U_0402_25V6

EMC

4 4

Fsw=1.25MHz @ Fsw net to 3V Css=Tss*(2.5uA/1.25V) (F) Tss=1.65mS

EMC

PC409

PC413

10U_0805_25V6K

2200P_0402_50V7K

SS_1.8V

12

PC414

3300P_0402_50V7-K

1.8V controller(35.15), Support component(35.16)

A

12

PVIN

11

PVIN

10

AVIN

9

SS/TR

B

+1.8VSP

EN_1.8V

13

EN

PU401

PU401 TLV62150RGTR_QFN16_3X3

TLV62150RGTR_QFN16_3X3

DEF

8

14

PR413

@ PR413

@

VOS

7

12

15

FSW

0_0402_5%

16

PGND

AGND

6

+1.8VSP

17

TP

PGND

Security Classifi cation

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

SW

PG

FB

5

FB_1.8V

Issued Date

1

2

3

4

+3VS

SW_1.8V

1.8VS_PWRO K

12

PR409

@ PR409

@

100K_0402_5%

12

SNUB_1.8V

12

PL403

2.2UH_1239AS-H-2R2N-P2_1.3A _30%

1 2

12

PR406

412K_0402_1%

12

Rdown

PR408

PR408 324K_0402_1%

324K_0402_1%

12

PC410

22P_0402_50V8J

PR407

@PR407

@

4.7_0805_5%

EMC

PC415

@PC415

@

680P_0402_50V7K

EMC

Rup

VFB=0.8V Vout=0.8V* (1+Rup/Rdown)

Vout=1.817V

Compal Secret Data

2011/06/02 2013/10/28

Compal Secret Data

Deciphered Dat e

C

+1.8VSP

12

PC411

22U_0805_6.3VAM

PJP401

@PJP401

@

2

112

JUMP_43X39

+1.8VS

+1.8VS TDC 124.6mA Peak Current 178mA OCP setting 1.4A(Fix)

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P39-PWR_+1.5VS/+1.8V_DDR

LA-9261P

D

44 50Monday, October 06, 2014

0.1

5

4

3

2

1

D D

EN pin don't floating If have pull down resistor at HW side, pls delete PR501

12

PC505

1 2

+3VALW

12

PC500

@PC500

@

0.22U_0402_10V6K

PR511

@ PR511

@

0_0402_5%

1 2

PR501

1M_0402_1%

PL500

EMC

HCB2012KF-121T50_0805

C C

PC503

EMC

B B

12

2200P_0402_50V7K

12

PC504

EMC

0.1U_0402_25V6

+3VALW

1.05V_M_PWRGD[11]

12

PC506

PC507

@

10U_0805_25V6K

10K_0402_5%

1 2

@PR512

@

0_0402_5%

1 2

B+

PR506

PR512

B+_1.05V

ILMT_1.05V

1.05VA_PG

PU500

8

IN

9

GND

3

ILMT

2

PG

SY8206DQNC_QFN10_3X3

Pin 7 BYP is for CS. Common NB can delete +3VALW and PC514

BYP

LDO

1

EN

6

BST_1.05V

BS

10

LX

4

FB

7

5

LX_1.05V

12

PR503

PR503 0_0603_5%

0_0603_5%

1 2

PC513

4.7U_0603_6.3V6K

0.1U_0603_25V7K

12

PC514

4.7U_0603_6.3V6K

+3VALW

12

@

0_0402_5%

12

PR507

@PR507

@

0_0402_5%

PR504

ILMT_1.05V

PM_SLP_S0#[11,21]

If PM_SLP_S0# high, Vout=1.05V If PM_SLP_S0# low, Vout=0.95V

PR500

@PR500

@

0_0402_5%

1 2

EMC EMC

4.7_1206_5%

1 2

1UH_11A_20%_7X7X3_M

FB = 0.6V

+3V_PCH

12

PR510

PR502

PL501

1 2

100K_0402_5%

2

G

680P_0603_50V7K

1 2

SNB_1.05V

Rup

12

PR509

127K_0402_1%

13

D

PQ500

PQ500 DMN65D8LW-7_SOT323-3

DMN65D8LW-7_SOT323-3

S

EN_+1.05SP [33]

PC502

12

PR505

21K_0402_1%

12

Rdown

PR508

35.7K_0402_1%

+1.05VSP

12

PC515

22P_0402_50V8J

+1.05VSP TDC 3.5A Peak Current 5.0A OCP current 6A

PJP500

@PJP5 00

@

2

112

JUMP_43X118

12

PC509

PC510

22U_0805_6.3VAM

12

PC512

22U_0805_6.3VAM

PC511

22U_0805_6.3VAM

+1.05V_PCH

VFB=0.6V Vout=0.6V* (1+Rup/Rdown)

+1.05VSP

Vout=1.05V

A A

The current limit is set to 6A, 8A or 12A when this pin is pull low, floating or pull high

1.05V controller(35.5), Support component(35.6)

5

4

Security Classification

2011/06/02 2013/10/28

Issue d Da te

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR D ISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/02 2013/10/28

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P40-PWR_+1.05VA

LA-9261P

45 50Monday, October 06, 2014

1

0.1

5

4

3

2

1

Pin19 need pull separate from +1.35VP. If you have +1.35V and +0.675V sequence question,

PL600

EMC

HCB2012KF-121T50_0805

D D

+1.35V_DDR

B+

HCB2012KF-121T50_0805

1 2

1.35V_B+

12

PC601

PC600

0.1U_0402_25V6

EMC

12

PC603

PC602

2200P_0402_50V7K

10U_0805_25V6K

5

12

PC604

0.1U_0603_25V7K

BST_1.35V

PR600

2.2_0603_5%

1 2

TDC 4.48A Peak Current 6.4A OCP setting 7.62A

PL601

2.2UH_7.8A_20%_7X7X3_M

1

+

PC617

2

330U_B2_2.5VM_R9M

2.2UH_7.8A_20%_7X7X3_M

ESR=9m ohm

C C

B B

A A

+1.35VP

Mode S3 S5 VTT VTTREF Shutdown L L off off Stadby L H off on Normal H H on on

Note: S3 - sleep ; S5 - power off

PL601

680P_0402_50V7K

MDV1528URH_PDFN3 3-8-5

12

PR602

4.7_1206_5%

PC612

12

EMCEMC

PQ600

PR601

1 2

1U_0603_10V6K

VDD_1.35V

+3VS

SUS_ON_EC[36]

DL_1.35V

CS_1.35V

PC607

1 2

+5VALW

@PR6 04

@

1 2

100K_0402_5%

1.35V_B+

PR604

4

10.5K_0402_1%

PC611

10.5K_0402_1%

12

123

5

+5VALW

4

123

PQ601

MDV1526URH_PDFN33-8-5

PQ601

MDV1526URH_PDFN33-8-5

PR603

5.1_0603_5%

1 2

1U_0603_10V6K

SM_PG_CTRL[6]

SIO_SLP_S3#[11,21,36,44]

you can change from +1.35VP to +1.35V_DDR.

BOOT_1.35V

DH_1.35V

SW_1.35V

15

DL

14

PGND

13

CS

12

VPP

11

VCC

PR606

887K_0402_1%

1 2

@PR608

@

0_0402_5%

1 2

16

G5616ARZ1U_TQFN20_3X3

10

1.2V_DDR_PWROK

PR608

0.1U_0402_10V7K

@PR609

@

0_0402_5%

1 2

@

0_0402_5%

LX

PGOOD

PC613

@PC613

@

PR609

PR610

18

17

DH

TON

8

9

EN_1.35V

TON_1.35V

12

BST

S5

19

7

EN_0.675VSP

VLDOIN

S3

20

PU600

VTT

PAD

VTTGND

VTTSNS

GND

VTTREF

VDDQSNS

VDDQSET

6

FB_1.35V

21

1

2

3

4

5

+1.35VP +1.35V_DDR

12

PC614

@PC614

12

@

0.1U_0402_10V7K

+0.675VSP +0.67 5VS

VTTREF_1.35V

1 2

8.06K_0402_1%

12

PR607

PR607 10K_0402_1%

10K_0402_1%

PR605

+1.35VP

12

+1.35VP

@PJ P600

@

112

JUMP_43X118

@PJ P601

@

112

JUMP_43X118

PJP602

@PJP602

@

112

JUMP_43X39

PC605

PJP600

PJP601

10U_0805_6.3V6K

0.75Volt +/- 5% TDC 0.7A Peak Current 1A

12

PC606

10U_0805_6.3V6K

12

PC610

0.033U_0402_16V7K

+1.35VP

2

1

+

2

PC609

@

+0.675VSP

ESR=9m ohm

330U_B_2.5VM_R9M

DDR controller(35.3), Support component(35.4)

5

Security Class ification

Security Classifica tion

2011/06/02 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DI SCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DI SCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DI SCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/02 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P41-PWR_+1.35V_DDR/+0.675VS

LA-9261P

46 50Monday, October 06, 2014

1

0.1

5

4

3

2

1

Follow Intel 514849_514849_BDW_PDG_Rev_1.0

15W

CPU_B+

CSP1

CSN1

PC709

1 2

PR719

1 2

1500P_0402_50V7K

+5VALW

39.2K_0402_1%

1 2

10K_0402_5%

PC712

VREF

75_0402_1%

@

PR700

SLEWA

PR710

PR711

17 18 19 20 21 22 23 24

1 2

3.3K_0402_1%

0.33U_0603_10V7K

1 2

10_0603_1%

100K_0402_1%_B25/50 4250K

12

PR705

12

10K_0402_5%

16

PU700

CSP1 CSN1 CSN2 CSP2 N/C

TPS51624RSM_QFN32_4X4

N/C GFB VFB

COMP26VCLK31V5A28DROP

25

27

PR718

VREF

12

PC713

PR721

1 2

PR723

@PR723

@

56_0402_5%

VBAT

12

PH700

PC700

12

PC701

0.01U_0402_16V7K

15

14

13

12

11

10

9

IMON

OCP-I

O-USR

F-IMAX

SLEWA

THERM

B-RAMP

VR_ON

SKIP# PWM1 PWM2 MODE

PGOOD

ALERT#

GND33GND

VR_HOT#30VREF

32

29

VR_SVID_CLK

12

VR_SVID_ALRT#

PC714

1U_0603_10V6K

H_PROCHOT#[36,39,40,42,6]

IMON

12

PR701

OCP-I O-USR

12

PR706

@PR716

@

0_0402_5%

1 2

VR_SVID_DAT

12

PC718

47P_0402_50V8J

374K_0402_1%

56K_0402_1%

PR716

SKIP#

PWM1

PC708

B-RAMP

1_0603_5%

1U_0603_10V6K

12

PR702

@

12

PR707

PR715

1 2

150K_0402_1%

1 2

VDIO

12

4700P_0402_25V7K

8 7 6 5 4 3 2

VDD

1

75_0402_1%

F-IMAX

@

PR713

1.91K_0402_1%

12

PR703

681K_0402_1%

12

PR708

100K_0402_1%

VR_ON [13]

H_VR_READY [13]

+3VS

12

PR704

36.5K_0402_1%

12

PR709

20K_0402_1%

B+

PWM1

PR732

PR732 0_0805_5%

0_0805_5%

1 2

@

D D

12

PR729

@PR729

@

2M_0402_1%

@PR730

@

1 2

2M_0402_1%

12

PR731

@PR731

@

27K_0402_1%

PR730

OCP-I

CPU_B+

C C

+3VS

VSSSENSE[14]

VCCSENSE[13]

B B

VSSSENSE

VCCSENSE

@ PC709

@

100P_0402_50V8J

1 2

10K_0402_5%

1 2

PR720

4.75K_0402_1%

+1.05VS_VCCST

Vps0

Vboot 1.7V

Icc_MAX

Idyn_MAX

Icc-TDC

Load-Line

Fast Slew Rate

Input voltage is 6~8.4V for NVDC(2S BATT)

CPU_B+

PC707

1 2

0.1U_0402_25V6

1 2

PR714

2.2_0603_5%

CPU_Vcore controller(36.1), Support component(36.3)

Specifications

12

PC703

PC702

10U_0805_16V6K

9

PGND2

8

PWM

7

BOOT

6

BOOT_R

5

VIN

CSD97374CQ4M_SON8_3P5X4P5

1.8V

32A

27A

10A

2.0mV/A

48mV/us

1

+

PC704

2

100U_D2_16VM_R50M

PU701

VSW

PGND1

VDD

SKIP#

4 3 2 1

SKIP#-1

1 2

PR728

@PR728

@

0_0402_5%

PC710

1 2

1U_0603_10V6K

CPU Frequency = 1.2MHz PL2 Current 14A ICC MAX 32A OCP Current 39 A IC_Dyn_VID1 27A DCR: 0.9mohm +-7% PH700 100Kohm B value: 3370k 1% PH701 10Kohm B value: 4250k 1%

12

EMC

PC705

@

0.1U_0402_25V6

LX_CORE

SKIP#

+5VS

PC706

2200P_0402_50V7K

1 2

2.49K_0402_1%

EMC

PL701

0.15UH_MMD06CZER15MG_37A _20%

1

4

3

2

12

EMCEMC

PR717

Plz notice.

4.7_1206_5%

Snubber R power rating on

12

High voltage and High FSW

CSP

PC711

680P_0603_50V7K

PR724

11.5K_0402_1%

12

PH701

12

10K_0402_1%_B25/50 3370K

12

PR725

2.94K_0402_1%

PR722

12

PC715

.047U_0402_16V7K

+VCC_CORE

CSP1

12

PC716

.047U_0402_16V7K

CSN1

Acoustic Noise B+ Bulk CAP(37.2)

12

PR727

12

130_0402_1%

PC717

0.1U_0402_25V6

Security Cla ssification

Security Classi fication

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION O F R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION O F R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION O F R&D DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS

DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS

DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/02 2013/10/28

Compal Sec ret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P42-PWR_CPU_CORE

LA-9261P

1

47 50Monday, October 06, 2014

0.1

A A

VR_SVID_CLK[13]

VR_SVID_ALRT#[13]

VR_SVID_DAT[13]

VR_SVID_CLK

VR_SVID_ALRT#

VR_SVID_DAT

5

12

PR726

54.9_0402_1%

5

D D

4

3

2

1

CPU_Core output CAP(36.4)

+VCC_CORE

for VCORE:1 phase ---> 13pcs

12

PC820

PC821

@ PC821

C C

B B

@

22U_0805_6.3V6M

12

PC822

22U_0805_6.3V6M

PC800

22U_0805_6.3V6M

PC810

@ PC810

@

22U_0805_6.3V6M

12

PC802

PC801

@ PC802

@

22U_0805_6.3V6M

12

PC812

PC811

@ PC812

@

22U_0805_6.3V6M

12

PC803

PC804

@ PC803

@

22U_0805_6.3V6M

12

PC814

PC813

22U_0805_6.3V6M

12

PC805

PC806

@ PC806

@

22U_0805_6.3V6M

12

PC815

PC816

@ PC816

@

22U_0805_6.3V6M

12

PC807

PC808

@ PC807

@

@ PC808

@

22U_0805_6.3V6M

12

PC817

PC818

22U_0805_6.3V6M

12

PC809

@ PC809

@

22U_0805_6.3V6M

12

PC819

22U_0805_6.3V6M

EMC

PC823

0.015U_0402_16V7K

12

A A

Security Classificati on

2011/06/02 2013/10/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/02 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

P43-PWR_PROCESSOR_DECOUPLING

Size Docu ment Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

LA-9261P

0.1

48 50Monday, October 0 6, 2014

1

5

4

3

2

1

Version Change List ( P. I. R. List )

Page 1

Request

Item Issue DescriptionDate

D D

1P40

2P41 PR315 2014'10/06Compal_Henrymodify schematic for A00 garber Change 0 ohm to short pad

3P42 PR416 2014'10/06Compal_Henrymodify schematic for A00 garber Change 0 ohm to short pad

4P44

5P45PR500, PR507, PR5122014'10/06Compal_Henrymodify schematic for A00 garber Change 0 ohm to short pad

6P46 PR608, PR609 2014'10/06Compal_Henrymodify schematic for A00 garber Change 0 ohm to short pad

7P47PR716, PR718, PR7322014'10/06Compal_Henrymodify schematic for A00 garber Change 0 ohm to short pad

C C

PR205, PR206, PR213, PR214, PR216, PR217, PR218, PR224, PR226, PR227,

PR410, PR411, PR412, PR413,

2014'10/06 Compal_Henry Change 0 ohm to short padmodify schematic for A00 garber

2014'10/06 Compal_Henry modify schematic for A00 garber Change 0 ohm to short pad

Owner

Solution Description Rev.Page# Title

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

2011/06/02 2013/10/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P45-PWR_PIR-2

LA-9261P

0.1

49 50Monday, October 06, 2014

1

0.1

5

4

3

2

1

Version Change List ( P. I. R. List )

Page 2

Request

Item Issue DescriptionDate

D D

C C

Owner

Solution Description Rev.Page# Title

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2011/06/02 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P44-PWR_PIR-1

LA-9261P

0.1

50 50Monday, October 06, 2014

1

0.1

Compal LA-B441P Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual