Compal LA-9984P Schematic

A

B

C

D

E

MODEL NAME : VBW11 PROJECT CODE : ANRVBW0100 PCB NO : DA8000WN000 LA-9984P M/B

1 1

DA40001FP00 LS-9102P USB/B DA40001FR00 LS-9104P ODD/B DA40001G400 LS-9105P POWER BUTTON/B DA40001FQ00 LS-9106P TP BUTTON/B

Dell / Compal Confidential

2 2

Schematic Document

Intel Shark Bay ULT OAK Mainstream2 UMA/DIS AMD Venus XT

3 3

X76@ : 76 level 46@ : 46 level @ : Nopop component CONN@ : Connector component XDP@ : XDP function UMA@ : Only for UMA DIS@ : Only for Discrete VENUS@ : VENUS Pro,VENUS XT VENUSXT@ : VENUS XT VENUSPRO@ : VENUS Pro

4 4

@VENUS@ : VENUS nopop component EMI@ : EMI parts @EMI@ : Reserve EMI parts ESD@ : ESD parts RF@ : RF parts

A

B

2013-05-17 Rev: 1.0

BOM config UMA : UMA@,EMI@,ESD@,RF@,XDP@ DIS VENUS : VENUS@,VENUSXT@,DIS@,EMI@,ESD@,RF@,XDP@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

D

ZZZ1

R1@

ZZZ1

R1@

PCB VBW11 LA9984P/LS9102P/LS9104P/LS9105P/LS9106P

DA8000WN000

Compal Electronics, Inc.

Title

Cover Page

Size Document Number Rev

Custom

LA-9984P

Date: Sheet of

E

1 57Wednesday, May 22, 2013

1.0

A

B

C

D

E

1 1

128M*16 GDDR5*8

P.36

P.37

128M*16 GDDR5*8

AMD Venus Pro , 25W

64bit

Venus Pro(HD8850M)2GB GDDR5 (128Mx16x8pcs)

128M*16 GDDR5*8

P.34 P.35

64bit

P.28~33

PEG 2.0 x4

Intel Haswell Processor 15W DC

Memory Bus (DDR3L)

Dual Channel

1.35V DDR3 1600 MHz

SATA3.0

Port 0

BGA1168

Port 1

2 2

LVDS Conn.

HDMI Conn.

LVDS eDP

P.41

P.20

Port 2

Mini Card WLAN/BT4.0 Half

RTD2136R

Ethernet

RTL8106E

P.26

P.19

Port 1

P.21

HDMI

PCI-E

Intel Lynx Point-LP

USB 3.0

USB2.0

Port 1,2

Port 0,1

Port 2,3

Port 11

Port 8

Port 10

Port 9

Fan Control

DDRIII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

SATA HDD Conn.

SATA ODD Conn.

USB 3.0 Conn. 1 USB 3.0 Conn. 2

USB 2.0 Conn. 3 USB 2.0 Conn. 4

Digital Camera (With Digital MIC)

Mini Card WLAN (Half)

Card Reader RTS5179/5170

Touch Screen

(OAK 15" only)

P.27

8GB Max

CPU XDP Conn.

P.17~18

P.42

P.24

P.25

Daughter board

P.41

P.26

P.23

P.41

P.6

3 in 1 Socket

P.23

3 3

4 4

A

RJ45

SPI ROM

64M

Int.KBD

P.21

SPI

P.9 P6~16

LPC Bus

33MHz

ENE KBC KB9012

B

P.40P.27

PS/2

SMBus

Touch Pad

P.27

C

Digital Mic.

HD Audio

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

Audio Codec

ALC3223

2013/05/17 2014/06/01

P.22

Compal Secret Data

Deciphered Date

Headphone Jack / Mic. Jack combo

Int. Speaker R / L

D

P.22

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Block diagram

LA-9984P

E

2 57Wednesday, May 22, 2013

1.0

A

B

C

D

E

Compal Confidential Project Code : VAW10 / VAW11 File Name : LA-9983P / LA-9984P

1 1

LS-9105P (PWR/B)

UE5

Lid

(SA00003VQ00)

SW1 (SN100004Y00)

JMINI

MINI Card

PJPDC 5 pin

PBATT

Battery

JLVDS 40 pin

JKB 30 pin

JBTB2 12 pin

PWR-BTN FFC

4 pin

4 pin Hot Bar

LS-9104P (ODD/B)

JODD

2 2

JHDMI

JLAN

HDMI

RJ-45

JPWR 4 pin

JKBBL 4 pin

JFAN 3 pin

JTP 6 pin

XDP

JXDP

LA-9983P M/B

JBTB1 12 pin

USB-DB FFC

8 pin

LS-9102P (USB/B)

USB

8 pin Hot Bar

JUSB4

LA-9984P M/B

JHP

USB

HP

Led1

Led2

Led3

Led4

JSPK 4 pin

Top Side

Bottom Side

(OAK 17")

JRTC 2 pin

RTC

JREAD

Card Reader

JDB 8 pin

JUSB1

TP-MB FFC

6 pin

3 3

JUSB2

JUSB3

TP-Module

TP-BTN FFC

4 pin

LS-9106P (TP-BTN/B)

4 pin

4 4

SW2 SW3

Hot Bar

JHDD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DB block diagram

LA-9984P

E

1.0

3 57Wednesday, May 22, 2013

1.0

A

Board ID Table for AD channel

Vcc 3.3V +/- 1%

Board ID

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 330K +/- 1% 16 17 18 19 NC

SMBUS Control Table

EC_SMB_CK1

1 1

EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

SMBCLK SMBDATA

SML0CLK SML0DATA

SML1CLK SML1DATA

Board ID TABLE

ID

0 1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19

100K +/- 1%Ra

Rb V min

AD_BID

0 0.000V 12K +/- 1% 15K +/- 1% 20K +/- 1% 27K +/- 1% 33K +/- 1% 43K +/- 1% 56K +/- 1%

0.347V

0.423V 0.430V

0.541V

0.691V

0.807V

0.978V 0.992V

1.169V 75K +/- 1% 1.398V 100K +/- 1%

1.634V

1.849V 1.865V 160K +/- 1% 200K +/- 1% 240K +/- 1% 270K +/- 1%

2.015V

2.185V

2.316V

2.395V 2.408V

2.521V 430K +/- 1% 560K +/- 1% 750K +/- 1%

SOURCE

KB9012

ULT

2.667V

2.791V

2.905V 2.912V

Charger

BATT

V

PCB Revision

UMA Sun XT VenusPro VenusXT

SSI&A02

PT

ST

XB

A01

V typ

AD_BID

V

AD_BID

max

0.000V 0.300V

0.354V

0.360V

0.438V

0.550V

0.702V

0.819V

0.559V

0.713V

0.831V

1.006V

1.185V

1.200V

1.414V 1.430V

1.650V

1.667V

1.881V130K +/- 1%

2.031V

2.200V

2.329V

2.046V

2.215V

2.343V

2.421V

2.533V

2.677V 0xCA - 0xD3

2.800V

2.544V

2.687V

2.808V

2.919V

RTD2136S

V

3.300V

DDR3LVGA

V

XDP

V

3.300V

WLAN mini card

Symbol Note :

: means Digital Ground

: means Analog Ground

EC AD3

0x00 - 0x0B 0x0C - 0x1C 0x1D - 0x26 0x27 - 0x30 0x31 - 0x3B 0x3C - 0x46 0x47 - 0x54 0x55 - 0x64 0x65 - 0x76 0x77 - 0x87 0x88 - 0x96 0x97 - 0xA3 0xA4 - 0xAD 0xAE - 0xB7 0xB8 - 0xC0 0xC1 - 0xC9

0xD4 - 0xDC 0xDD - 0xE6 0xE7 - 0xFF3.000V

Touch pad

VV

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

Link

CLOCK SIGNAL

10/100 LAN

MINI Card (WLAN)

dGPU

2013/05/17 2014/06/01

A

Compal Secret Data

Deciphered Date

ULT

Port1

Port2

Port3

Port4

Port0

Port1

Port2

Port3

Port4

Port5

Port6

Port7

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

SATA0

SATA1

SATA2

SATA3

USB3.0

USB connector 2

USB connector 1

USB2.0

USB connector 2

USB connector 1

USB connector 3

USB connector 4 (DB)

MINI Card (WLAN)

Touch Screen Panel

Card Reader

Camera

PCI EXPRESS

10/100 LAN

MINI Card (WLAN)

PEG (N14P)

SATA

HDD

ODD

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-9984P

1.0

4 57Wednesday, May 22, 2013

1.0

5

4

3

2

1

SMBUS Address [0x9a]

MEM_SMBCLK

AP2

MEM_SMBDATA

D D

MCH Shark bay

AH1

AN1

AK1

AN1

AK1

SML0CLK

SML0DATA

SML1_SMBCLK

SML1_SMBDATA

2.2K

1K

2.2K

+3.3V_ALW_PCH

N-MOS

+3.3V_ALW_PCH

N-MOS

EC_SMB_CK2

EC_SMB_DA2

10K

DDR_XDP_WLAN_TP_SMBCLK

DDR_XDP_WLAN_TP_SMBDAT

+3VS

0 ohm

DDR_XDP_SMBCLK_R1

DDR_XDP_SMBDAT_R1

202

DIMMA

200

202

DIMMB

200

53

51

30

32

5

6

XDP1

JMINI

JTP

SMBUS Address [A0]

SMBUS Address [A4]

SMBUS Address [TBD]

2.2K

C C

79

EC_SMB_CK2

80

EC_SMB_DA2

2.2K

+3VALW

0 ohm

N-MOS

CSCL

CSDA

0 ohm

CIICSCL

CIICSDA

13

UV28

14

LVDS Translator

SMBUS Address [TBD]

2.2K

N-MOS

2.2K

VGA_SMB_CK2

VGA_SMB_DA2

+3VS_VGA

T4

T3

UV28 GPU

SMBUS Address [0xXX]

2.2K

77

EC_SMB_CK1

78

KBC

B B

KB9012A4

EC_SMB_DA1

+3VALW

0 ohm

100 ohm

SCL

SDA

11

10

3

1

PD1

POWERPU701

SMBUS Address [0x12]

Charger

4

BAT_ALERT

6 5

BATT_PRS

3

PBATT1

SMBUS Address [0x16]

BATT CONN

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

SMBus block diagram

Size Document Number Rev

LA-9984P

Date: Sheet of

1

5 57Wednesday, May 22, 2013

1.0

5

4

3

2

1

i3-4010U-15W-GT2-MP

UC1

4010Ui3G2R1@

UC1

4010Ui3G2R1@

CL8064701478202 SR16Q C1 1.7G BGA

SA00006SX1L

i5-4200U-15W-GT2-MP

D D

UC1

4200Ui5G2R1@

UC1

4200Ui5G2R1@

CL8064701477702 SR170 C1 1.6G BGA

SA00006SM2L

i7-4500U-15W-GT2-MP

UC1

4500Ui7G2R1@

UC1

4500Ui7G2R1@

CL8064701477202 SR16Z C1 1.8G BGA

SA00006SL1L

UC1

4010Ui3G2R3@

UC1

4010Ui3G2R3@

CL8064701478202 SR16Q C1 1.7G A31!

SA00006SX2L

UC1

4200Ui5G2R3@

UC1

4200Ui5G2R3@

CL8064701477702 SR170 C1 1.6G A31!

SA00006SM3L

UC1

4500Ui7G2R3@

UC1

4500Ui7G2R3@

CL8064701477202 SR16Z C1 1.8G A31!

SA00006SL2L

HASWELL_MCP_E

UC1A

DDI1_LANE_N0<20> DDI1_LANE_P0<20> DDI1_LANE_N1<20> DDI1_LANE_P1<20> DDI1_LANE_N2<20> DDI1_LANE_P2<20> DDI1_LANE_N3<20> DDI1_LANE_P3<20>

DDI1_LANE_N0 DDI1_LANE_P0 DDI1_LANE_N1 DDI1_LANE_P1 DDI1_LANE_N2 DDI1_LANE_P2 DDI1_LANE_N3 DDI1_LANE_P3

C54

DDI1_TXN0

C55

DDI1_TXP0

B58

DDI1_TXN1

C58

DDI1_TXP1

B55

DDI1_TXN2

A55

DDI1_TXP2

A57

DDI1_TXN3

B57

DDI1_TXP3

C51

DDI2_TXN0

C50

DDI2_TXP0

C53

DDI2_TXN1

B54

DDI2_TXP1

C49

DDI2_TXN2

B50

DDI2_TXP2

A53

DDI2_TXN3

B53

DDI2_TXP3

HASWELL_MCP_E

DDI EDP

1 OF 19

EDP_TXN0

EDP_TXP0

EDP_TXN1

EDP_TXP1

EDP_TXN2

EDP_TXP2

EDP_TXN3

EDP_TXP3

EDP_AUXN EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

Rev1p2

C45 B46 A47 B47

C47 C46 A49 B49

A45 B45

D20 A43

EDP_CPU_LANE_N0 EDP_CPU_LANE_P0 EDP_CPU_LANE_N1 EDP_CPU_LANE_P1

EDP_CPU_AUX# EDP_CPU_AUX

EDP_COMP EDP_DISP_UTIL

EDP_CPU_AUX# <19> EDP_CPU_AUX <19>

1 2

@

RC72

RC72 0_0402_5%

0_0402_5%

EDP_CPU_LANE_N0 <19> EDP_CPU_LANE_P0 <19> EDP_CPU_LANE_N1 <19> EDP_CPU_LANE_P1 <19>

EDP_BIA_PWM <10,19>

COMPENSATION PU FOR eDP

+VCCIOA_OUT

12

CAD Note:Trace width=20 mils ,Spacing= 25mil, Max length=100 mils.

RC7124.9_0402_1%~D RC7124.9_0402_1%~D

DDR_XDP_WLAN_TP_SMBDAT<17,18,19,26,27,9> DDR_XDP_WLAN_TP_SMBCLK<17,18,19,26,27,9>

CPU_PWR_DEBUG#<13>

PBTN_OUT#<10,30>

SYS_PWROK<10,30>

THERMAL

+1.05VS

0.1U_0402_10V7K

1

CC15

XDP@

CC15

XDP@

CC14

XDP@

CC14

XDP@

2

Place near JXDP1

RC48 1K_0402_5%XDP@RC48 1K_0402_5%XDP@ RC49 0_0402_5%XDP@RC49 0_0402_5%XDP@

RC50 0_0402_5%XDP@RC50 0_0402_5%XDP@ RC52 0_0402_5%XDP@RC52 0_0402_5%XDP@

PCH_JTAG_TCK

3

1 2 1 2

1 8 2 7 3 6 4 5

RP46

RP46 0_8P4R_5%

0_8P4R_5%

XDP@

PROC_TCK PROC_TMS

PROC_TRST

PROC_TDI

PROC_TDO

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H_CPUPWRGD H_VCCST_PWRGD_XDP

SYS_PWROK

HASWELL_MCP_E

MISC

JTAG

PWR

DDR3

2 OF 19

PRDY PREQ

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

Rev1p2

Issued Date

CFG0<16> CFG1<16>

CFG2<16> CFG3<16>

CFG4<16> CFG5<16>

CFG6<16> CFG7<16>

J62 K62 E60 E61 E59 F63 F62

J60 H60 H61 H62 K59 H63 K60 J61

+1.05VS+1.05VS

JXDP1

1

GND0

+3VALW_PCH

1 2

1

2

1 2

RC141 0_0402 _1%@RC141 0_0402 _1%@

T111@ T111@ T112@ T112@ T113@ T113@ T114@ T114@ T115@ T115@ T116@ T116@

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

CONN@

@

RC64

RC64 1K_0402_5%

1K_0402_5%

SYS_PWROK_XDP

ESD@

CC16

0.1U_0402_10V7K

Place near JXDP1.47

1 2

PCH_JTAG_RST#

@

R2341

R2341 0_0402_5%

0_0402_5%

Compal Secret Data

Deciphered Date

2

XDP_PREQ# XDP_PRDY#

CFG0 CFG1

CFG2

XDP_OBS0_R XDP_OBS1_R

CFG4 CFG5

CFG6 CFG7

CFD_PWRBTN#_XDP

CPU_PWR_DEBUG#_R PLT_RST# SYS_PWROK_XDP

DDR_XDP_SMBDAT_R1 DDR_XDP_SMBCLK_R1

XDP_TCLK

XDP_PRDY# XDP_PREQ# XDP_TCK XDP_TMS XDP_TRST# XDP_TDI XDP_TDO

XDP_OBS0_R XDP_OBS1_R

2013/05/17 2014/06/01

GND1 OBSFN_C0 OBSFN_C1

GND3

OBSDATA_C0 OBSDATA_C1

GND5

OBSDATA_C2 OBSDATA_C3

GND7 OBSFN_D0 OBSFN_D1

GND9

OBSDATA_D0 OBSDATA_D1

GND11 OBSDATA_D2 OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

GND17

PCH_JTAG_RST# <8>

TD0

TDI

TMS

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

XDP_DBRESET#

CFG17 CFG16

CFG8 CFG9

CFG10 CFG11CFG3

CFG19 CFG18

CFG12 CFG13

CFG14 CFG15

CLK_XDP CLK_XDP#

XDP_RST#_R XDP_DBRESET#

TDO_XDP TRST#_XDP TDI_XDP TMS_XDP CFG3_R

CFG17 <16> CFG16 <16>

CFG8 <16> CFG9 <16>

CFG10 <16> CFG11 <16>

CFG19 <16> CFG18 <16>

CFG12 <16> CFG13 <16>

CFG14 <16> CFG15 <16>

1 2

RC139 0_0402_5%XDP@RC139 0_ 0402_5%XDP@

1 2

RC140 0_0402_5%XDP@RC140 0_ 0402_5%XDP@

RC51

RC51 1K_0402_5%

1K_0402_5%

XDP@

1 2

RC56 1K_0402_5%

XDP@

1 2

@

RC26

RC26 0_0402_1%

0_0402_1%

PU/PD for JTAG signals

XDP_TMS XDP_TDI XDP_PREQ# TDO_XDP

XDP_TDO XDP_TCK XDP_TRST#

Title

MCP(1,2/19) eDP,XDP,MISC

Size Docum ent Number Rev

LA-9984P

Date: Sheet of

PLT_RST#

CC30

0.047U_0402_16V4Z

Place CC30 close to RC51.1

12

SYS_RESET#

12

RC362

RC362 1K_0402_1%

1K_0402_1%

1 2

CFG3

CC17

0.1U_0402_10V7K

SYS_RESET# <10>

+1.05VS

1 8 2 7 3 6 4 5

RP44

@RP44

@

51_8P4R_5%

1 8 2 7 3 6 4 5

RP45

RP45 51_8P4R_5%

51_8P4R_5%

Compal Electronics, Inc.

1

ESD@CC30

ESD@

2

CLK_CPU_ITP <9> CLK_CPU_ITP# <9>

PLT_RST# <10,21,26,30,48> +3VS

6 55Wednesday, May 22, 2013

1.0

+3VS

CC13

12

0.1U_0402_10V7K

1 2

TDO_XDP

@

RC43 0_0402_1%

RUNPWROK

1 2

@

RC45 0_0402_1%

RUNPWROK

1 2

TMS_XDP

@

RC46 0_0402_1%

RUNPWROK

TRST#_XDP XDP_TRST#

RUNPWROK

PCH_JTAG_TCK<8>

H_CPUPWRGD

1

CC27

CC27 100P_0402_50V8J

100P_0402_50V8J

ESD@

2

PCH_JTAG_TDI<8>

RUNPWROK

CC29

0.1U_0402_10V7K

Place CC29 close to UC4

PCH_JTAG_TDO<8>

1 2

RC44 0_0402_1%

PCH_JTAG_TMS<8>

1

ESD@CC29

ESD@

2

+1.05VS

1 2

RC58 49.9_0402_1%@RC58 4 9.9_0402_1%@

1 2

RC60 62_0402_5%RC60 62_0402_5%

TDI_XDP TDI_XDP_R

@

RUNPWROK<30>

H_CATERR#

H_PROCHOT#

12

RC66

RC66 10K_0402_5%

10K_0402_5%

C C

B B

ESD solution

CAD Note: Avoid stub in the PWRGD path while placing resistors RC115

DDR3 COMPENSATION SIGNALS

12

SM_RCOMP0

RC68200_0402_1% RC68200_0402_1%

12

SM_RCOMP1

RC69120_0402_1% RC69120_0402_1%

12

SM_RCOMP2

A A

CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil

5

RC70100_0402_1% RC70100_0402_1%

UC4

@UC4

@

14

VCC

2

1A

1

1OE

5

2A

4

2OE

9

3A

10

3OE

12

4A

13

4OE

74CBTLV3126BQ_DHVQFN14_2P5X3

reference Shark Bay ULT Validation Customer Debug Port Implementation Requirement Rev 1.0

PCH_JTAG_RST#

PCH_JTAG_JTAGX<8>

PCH_JTAG_TDO TDI_XDP_R

PCH_JTAG_TCK

H_PROCHOT#<30,36>

DDR3_DRAMRST#_CPU<17>

@

1 2

@

CPU_DETECT#<30>

DDR_PG_CTRL<17>

Place CC35 on BOT

GND PAD

PECI_EC<30>

RC67 56_0402_5%RC67 56_0402_5%

DDR3_DRAMRST#_CPU

4

3

1B

6

2B

8

3B

11

4B

7

GND

15

12

XDP_TRST#

RC570_0402_1%

XDP_TCLK

RC590_0402_1%

12

TDO_XDP

RC620_0402_5% XDP@ RC620_0402_5% XDP@

12

RC630_0402_5% XDP@ RC630_0402_5% XDP@

12

XDP_TCLK

RC650_0402_5% XDP@ RC650_0402_5% XDP@

1 2

CC35

ESD@CC35

ESD@

0.047U_0402_16V4Z

XDP_TDOPCH_JTAG_TDO

XDP_TDI

XDP_TMS

CPU_DETECT# H_CATERR# PECI_EC

H_PROCHOT#_R

H_CPUPWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

1

2

AU60 AV60 AU61 AV15 AV61

D61 K61 N62

K63

C61

UC1B

PROC_DETECT CATERR PECI

PROCHOT

PROCPWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1

5

HASWELL_MCP_E

UC1C

AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58

AW58

AY56

AW56

AV58 AU58 AV56 AU56 AY54

AW54

AY52

AW52

AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51

UC1C

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

D D

C C

DDR_A_D[0..63]<17>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

HASWELL_MCP_E

DDR CHANNEL A

4

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1

SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3

SA_CS#0 SA_CS#1

SA_ODT0

SA_RAS

SA_WE

SA_CAS

SA_BA0 SA_BA1 SA_BA2

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1

AU37 AV37 AW36 AY36

AU43 AW43 AY42 AY43

AP33 AR32

AP32

AY34 AW34 AU34

AU35 AV35 AY41

AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

AP49 AR51 AP51

M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#1 M_CLK_DDR1

DDR_CKE0_DIMMA

DDR_CS0_DIMMA# DDR_CS1_DIMMA#

DDR_A_RAS# DDR_A_WE# DDR_A_CAS#

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

M_CLK_DDR#0 <17> M_CLK_DDR0 <17> M_CLK_DDR#1 <17> M_CLK_DDR1 <17>

DDR_CKE0_DIMMA <17> DDR_CKE1_DIMMA <17>

DDR_CS0_DIMMA# <17> DDR_CS1_DIMMA# <17>

DDR_A_RAS# <17> DDR_A_WE# <17> DDR_A_CAS# <17>

DDR_A_BS0 <17> DDR_A_BS1 <17> DDR_A_BS2 <17>

+SM_VREF_CA +SM_VREF_DQ0 +SM_VREF_DQ1

DDR_B_D[0..63]<18>

DDR_A_MA[0..15] <17>

DDR_A_DQS#[0..7] <17>

DDR_A_DQS[0..7] <17>

3

UC1D

AY31

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AW31

AY29

AW29

AV31 AU31 AV29 AU29 AY27

AW27

AY25

AW25

AV27 AU27 AV25 AU25 AM29 AK29

AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25

AY23

AW23

AY21

AW21

AV23 AU23 AV21 AU21 AY19

AW19

AY17

AW17

AV19 AU19 AV17 AU17 AR21 AR22

AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18

AK20 AM20 AR18 AP18

AL28

AL25

AL21

AL18

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

HASWELL_MCP_E

DDR CHANNEL B

2

AM38

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3

SB_CS#0 SB_CS#1

SB_ODT0

SB_RAS

SB_WE

SB_CAS

SB_BA0 SB_BA1 SB_BA2

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

AN38 AK38 AL38

AY49 AU50 AW49 AV50

AM32 AK32

AL32

AM35 AK35 AM33

AL35 AM36 AU49

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#3 M_CLK_DDR3

DDR_CKE2_DIMMBDDR_CKE1_DIMMA DDR_CKE3_DIMMB

DDR_CS2_DIMMB# DDR_CS3_DIMMB#

DDR_B_RAS# DDR_B_WE# DDR_B_CAS#

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

M_CLK_DDR#2 <18> M_CLK_DDR2 <18> M_CLK_DDR#3 <18> M_CLK_DDR3 <18>

DDR_CKE2_DIMMB <18> DDR_CKE3_DIMMB <18>

DDR_CS2_DIMMB# <18> DDR_CS3_DIMMB# <18>

DDR_B_RAS# <18> DDR_B_WE# <18> DDR_B_CAS# <18>

DDR_B_BS0 <18> DDR_B_BS1 <18> DDR_B_BS2 <18>

1

DDR_B_MA[0..15] <18>

DDR_B_DQS#[0..7] <18>

DDR_B_DQS[0..7] <18>

B B

Rev1p2

1

CC8

0.022U_0402_16V7K

2

change 22nF

12

RC23

24.9_0402_1%~D

Rev1p2

+1.35V

12

RC15

1.82K_0402_1%

12

RC21

1.82K_0402_1%

1 2

RC18

2.2_0402_1%

+1.35V

12

RC16

1.82K_0402_1%

+SM_VREF_DQ0_DIMM1+SM_VREF_CA_DIMM +SM_VREF_DQ1_DIMM2

1

CC9

0.022U_0402_16V7K

2

change 22nF change 22nF

12

RC24

24.9_0402_1%~D

1.82K_0402_1%

12

RC22

1.82K_0402_1%

1 2

RC19

2.2_0402_1%

confirm by intel request PDG P141

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

3 OF 19

+1.35V

12

RC14

1.82K_0402_1%

+SM_VREF_CA +SM_VREF_DQ1

1 2

RC17

2.2_0402_1%

12

RC20

1.82K_0402_1%

A A

5

4

4 OF 19

+SM_VREF_DQ0

1

CC10

0.022U_0402_16V7K

2

12

RC25

24.9_0402_1%~D

Compal Secret Data

Deciphered Date

2

Rev1p2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

MCP(3,4/19) DDR3

LA-9984P

1

7 57Wednesday, May 22, 2013

1.0

5

RTC Battery

4

3

+RTCVCC

12

RC1

RC1 330K_0402_1%

330K_0402_1%

2

1

+RTCBATT

SATA_IREF

RSVD RSVD

SATA_RCOMP

SATALED

Rev1p2

PCH_INTVRMEN

12

@

RC2

RC2 330K_0402_1%

330K_0402_1%

J5 H5 B15 A15

J8 H8 A17 B17

J6 H6 B14 C15

F5 E5 C17 D17

V1 U1 V6 AC1

A12 L11 K10 C12 U3

EC_SMI# PCH_GPIO35 ODD_DETECT# PCH_GPIO37

SATA_IREF

SATA_RCOMP SATA_ACT#

PCH_AZ_SDOUT

PCH_AZ_SYNC

PCH_AZ_RST#

PCH_AZ_BITCLK

+3VS

1 2

+1.05VS_ASATA3PLL

RP37

RP37 10K_8P4R_5%

10K_8P4R_5%

PCH_AZ_SDOUT

SATA HDD

SATA ODD

+3VS

RC3 1K_0402_5%@RC3 1K_0402_5%@

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = DESABLED (DEFAULT) HIGH = ENABLED

SATA_PRX_DTX_N0_C <32> SATA_PRX_DTX_P0_C <32>

SATA_PTX_DRX_N0_C <32> SATA_PTX_DRX_P0_C <32>

SATA_PRX_DTX_N1_C <32> SATA_PRX_DTX_P1_C <32>

SATA_PTX_DRX_N1_C <32> SATA_PTX_DRX_P1_C <32>

PCH Rx side need use strap pin to update PCIE +/-

+3VS

RC107

RC107 10K_0402_5%

10K_0402_5%

1 2

EC_SMI# <30>

ODD_DETECT# <32>

1 2

RC126 0_0603_1%@RC126 0_0603_1%@

1 2

RC131 3.01K_0402_1%RC131 3.01K_0402_1%

SATA_ACT# <26>

ODD_DETECT# PCH_GPIO35 PCH_GPIO37

within 500 mils

1 8 2 7 3 6 4 5

SATA Impedance Compensation

CAD note: Place the resistor within 500 mils of the PCH. Avoid routing next to clock pins. reference FFRD sch 0.5

D D

RC10

+CHGRTC

W=20mils

C C

1

@

ME1 SHORT PADS~D

1 2

CC3 1U_0402_6.3V6KCC3 1U_0402_6.3V6K

B B

RC10 1K_0402_5%

1K_0402_5%

W=20mils

1 2

2

3

DC1

DC1 BAT54CW_SOT323-3

BAT54CW_SOT323-3

2

1

CC26

CC26 1U_0603_10V6K

1U_0603_10V6K

2

+RTCVCC

RC7 1M_0402_5%RC7 1M_0402_5%

RC5 20K_0402_5%RC5 20K_0402_5% RC6 20K_0402_5%RC6 20K_0402_5%

CMOS place near DIMM

+1.05VS

@

RC130 1K_0402_1%

@

RC135 51_0402_1%

+1.05VS

1 8 2 7 3 6 4 5

RP48

RP48 51_8P4R_5%

51_8P4R_5%

1 2

1 2 1 2

1

@

CMOS1 SHORT PADS~D

1 2

CC4

12

PCH_JTAG_JTAGX

12

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

+CHGRTC

2

1U_0402_6.3V6K

CC1

1 2

15P_0402_50V8J

XTAL@

CC2

XTAL@CC2

XTAL@

15P_0402_50V8J

1 2

JP12

2

112

JUMP_43X39

For GCLK

PCH_RTCX1<29>

12

XTAL@

YC1

32.768KHZ_12.5PF_Q13FC1350000

PCH_AZ_CODEC_SDIN0<22>

ME_EN<30>

CMOS_CLR1

Shunt Clear CMOS

Open

ME_CLR1

Shunt Clear ME RTC Registers

Open

+3VLP

1 2

RC8 1K_0402_5%RC8 1K_0402_5%

PCH_JTAG_RST#<6> PCH_JTAG_TCK<6> PCH_JTAG_TDI<6> PCH_JTAG_TDO<6> PCH_JTAG_TMS<6>

PCH_JTAG_JTAGX<6>

CMOS setting

Keep CMOS

TPM setting

Keep ME RTC Registers

PCH_RTCX1

12

XTAL@

RC4

RC4 10M_0402_5%

10M_0402_5%

PCH_RTCX2 INTRUDER# PCH_INTVRMEN SRTCRST# PCH_RTCRST#

PCH_AZ_BITCLK PCH_AZ_SYNC PCH_AZ_RST# PCH_AZ_CODEC_SDIN0

PCH_AZ_SDOUT

PCH_JTAG_RST# PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_JTAG_JTAGX

UC1E

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER

AV7

INTVRMEN

AV6

SRTCRST

AU7

RTCRST

AW8

HDA_BCLK/I2S0_SC LK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST/I2S_MCL K

AY10

HDA_SDI0/I2S0_RXD

AU12

HDA_SDI1/I2S1_RXD

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN/I2S1_ TXD

AV10

HDA_DOCK_RST /I2S1_SFRM

AY8

I2S1_SCLK

AU62

PCH_TRST

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD

AC4

RSVD

AE63

JTAGX

AV2

RSVD

INTVRMEN - INTEGRATED SUS 1.05V VRM ENABLE High - Enable Internal VRs Low - Enable External VRs

HASWELL_MCP_E

SATAAUDIO

SATA_RN0/PERN6_ L3

SATA_RP0/PERP6_L 3 SATA_TN0/PETN6 _L3

SATA_TP0/PETP6_ L3

SATA_RN1/PERN6_ L2

SATA_RP1/PERP6_L 2 SATA_TN1/PETN6 _L2

SATA_TP1/PETP6_ L2

SATA_RN2/PERN6_ L1

SATA_RP2/PERP6_L 1 SATA_TN2/PETN6 _L1

SATA_TP2/PETP6_ L1

SATA_RN3/PERN6_ L0

SATA_RP3/PERP6_L 0 SATA_TN3/PETN6 _L0

SATA_TP3/PETP6_ L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

RTC

JTAG

5 OF 19

HDA for Codec

1 2

PCH_AZ_CODEC_SDOUT<22>

PCH_AZ_CODEC_SYNC<22>

PCH_AZ_CODEC_RST#<22>

PCH_AZ_CODEC_BITCLK<22>

R2356 33_0402_5%EMI@ R2356 33_0402_5%EMI@

1 2

R2357 33_0402_5%EMI@ R2357 33_0402_5%EMI@

1 2

R2358 33_0402_5%EMI@ R2358 33_0402_5%EMI@

1 2

R2359 33_0402_5%EMI@ R2359 33_0402_5%EMI@

@EMI@

1

CC5

CC5 27P_0402_50V8J

27P_0402_50V8J

2

EMI depop location

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

MCP(5/19) RTC,SATA,HDA,JTAG

LA-9984P

1

8 57Wednesday, May 22, 2013

1.0

5

4

3

2

1

+3VALW_PCH

D D

10K_0402_5%

PCH_SMB_ALERT# MEM_SMBCLK MEM_SMBDATA

SML0CLK SML0DATA PCH_HOT# SML1_SMBCLK SML1_SMBDATA

10K_0402_5%

T97@ T97@ T98@ T98@ T99@ T99@

@EMI@

C2326

C2326 68P_0402_50V8J

68P_0402_50V8J

+3VS

1

2

PCH_SPI_MOSI_1 PCH_SPI_MISO_1 PCH_SPI_WP1# PCH_SPI_HOLD1#

1 2

R2334 1K_0402_1%R2334 1K_0402_1%

1 2

R2335 1K_0402_1% R2335 1K_0402_1%

LPC_LFRAME#<30>

EMI

1 2

RP39

1 8 2 7 3 6 4 5

15_8P4R_5%

LPC_LAD0<30> LPC_LAD1<30> LPC_LAD2<30> LPC_LAD3<30>

EMI@

R2333

R2333 15_0402_1%

15_0402_1%

LPC_LAD0 LPC_LAD1 LPC_LAD2

LPC_LFRAME#

PCH_SPI_CLKPCH_SPI_CLK_R PCH_SPI_CS0#

PCH_SPI_MOSI PCH_SPI_MISO PCH_SPI_WP# PCH_SPI_HOLD#

AU14

AW12

AY12

AW11

AV12

HASWELL_MCP_E

UC1G

LAD0 LAD1 LAD2 LAD3 LFRAME

AA3

SPI_CLK

Y7

SPI_CS0

Y4

SPI_CS1

AC2

SPI_CS2

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

AF1

SPI_IO3

HASWELL_MCP_E

LPC

SPI C-LINK

7 OF 19

SMBUS

SMBALERT/GPIO11

SMBCLK

SMBDATA

SML0ALERT/GPIO60

SML0CLK

SML1ALERT/PCH HOT/GPIO73

SML0DATA

SML1CLK/GPIO75

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST

Rev1p2

AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3

AF2 AD2 AF4

R2329

12

R2330

R2330 10K_0402_5%

10K_0402_5%

MEM_SMBCLKLPC_LAD3

PCH_HOT# <30>

MEM_SMBDATA

MEM Bus : DDR/XDP/WLAN/TP

+3VS

2

G

6 1

D

5

DMN66D0LDW-7_SOT363-6

3 4

SGD

QC1A

DMN66D0LDW-7_SOT363-6

10K_0402_5%

S

QC1B

R2331

12

R2332

R2332 10K_0402_5%

10K_0402_5%

DDR_XDP_WLAN_TP_SMBCLK <17,18,19,26,27,6>

DDR_XDP_WLAN_TP_SMBDAT <17,18,19,26,27,6>

SML1 Bus : EC/Sensors

C C

+3VALW_PCH

+3VS

C2327

0.1U_0402_10V7K

PCH_SPI_CS0# PCH_SPI_MISO_1

PCH_SPI_WP1#

SPI ROM ( 8MByte )

U2302

1

CS#

2

DO(IO1)

3

WP#(IO2)

4

GND

64M EN25Q64-104HIP SOP 8P

HOLD#(IO3)

DI(IO0)

8

VCC

7 6

CLK

5

PCH_SPI_HOLD1#

PCH_SPI_CLK_R PCH_SPI_MOSI_1

1 2

MEM_SMBCLK MEM_SMBDATA SML1_SMBCLK SML1_SMBDATA

SML0CLK SML0DATA

PN : SA000046400 ,64M,EN25Q64-104HIP

EC_SPI_MOSI_1<30> EC_SPI_MISO_1<30> EC_SPI_CLK_R<30> EC_SPI_CS0#<30>

B B

A A

EC_SPI_MOSI_1 EC_SPI_MISO_1 EC_SPI_CLK_R EC_SPI_CS0#

Place T183, T184, T185, T186 close to PCH_SPI_MOSI_1 PCH_SPI_MISO_1 PCH_SPI_CLK_R PCH_SPI_CS0# near U2302

T183PAD~D @T183PAD~D @ T184PAD~D @T184PAD~D @ T185PAD~D @T185PAD~D @ T186PAD~D @T186PAD~D @

10/100 LAN ------->

WLAN(Mini Card)--->

dGPU--->

CLK_PCIE_LAN#<21> CLK_PCIE_LAN<21>

LAN_CLKREQ#<21>

CLK_PCIE_WLAN#<26> CLK_PCIE_WLAN<26>

WLAN_CLKREQ#<26>

CLK_PEG_VGA#<48> CLK_PEG_VGA<48>

PEG_CLKREQ#<49>

CLK_PCIE_LAN# CLK_PCIE_LAN

CLK_PCIE_WLAN# CLK_PCIE_WLAN

CLK_PEG_VGA# CLK_PEG_VGA

+3VS

RP42

1 8 2 7 3 6 4 5

10K_8P4R_5%

RP40

1 8 2 7 3 6 4 5

2.2K_0804_8P4R_5%

RP49

1 8 2 7 3 6 4 5

1K_0804_8P4R_5%

UC1F

C43

CLKOUT_PCIE_N 0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0/GPIO18

B41

CLKOUT_PCIE_N 1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1/GPIO19

C41

CLKOUT_PCIE_N 2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2/GPIO20

B38

CLKOUT_PCIE_N 3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3/GPIO21

A39

CLKOUT_PCIE_N 4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4/GPIO22

B37

CLKOUT_PCIE_N 5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5/GPIO23

+3VALW_PCH

HASWELL_MCP_E

CLOCK

SIGNALS

6 OF 19

For GCLK

XTAL24_IN<29>

XTAL24_IN

XTAL24_OUT

RSVD RSVD

DIFFCLK_BIASREF

TESTLOW _C35 TESTLOW _C34 TESTLOW _AK8 TESTLOW _AL8

CLKOUT_LPC _0 CLKOUT_LPC _1

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

Rev1p2

SML1_SMBCLK

SML1_SMBDATA

A25

XTAL24_IN

B25

XTAL24_OUT

K21 M21 C26

CLK_BIASREF

C35 C34 AK8 AL8

AN15

CLKOUT_LPC0

AP15

B35 A35

2

QH1B

G

61

S

D

S

D

DMN66D0LDW-7_SOT363-6

XTAL24_IN

1M_0402_5%

RC12

XTAL@

1 2

RC13

3.01K_0402_1%

1 2

RP41 10K_8P4R_5%RP41 10K_8P4R_5%

1 8 2 7 3 6 4 5

5

34

SGD

QH1A

CC6

15P_0402_50V8J

XTAL@

3

4

YC2

YC2 24MHZ_12PF_X3G024000DC1H

24MHZ_12PF_X3G024000DC1H

XTAL@

1

2

CC7

15P_0402_50V8J

XTAL@

+1.05VS_AXCK_LCPLL

EMI@

R2336

R2336 22_0402_5%

22_0402_5%

12

EC_SMB_CK2 <19,30,49>

EC_SMB_DA2 <19,30,49>

12

CLK_PCI_LPC <30>

CLK_CPU_ITP# <6> CLK_CPU_ITP <6>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

MCP(6,7/19) CLK,SMB,SPI,LPC

LA-9984P

1

9 57Wednesday, May 22, 2013

1.0

5

4

3

2

1

PCH_PLTRST#

CC33

0.047U_0402_16V4Z

D D

C C

B B

+3VALW_PCH

RC27 10K_0402_5%RC27 10K_0402_5%

RC28 10K_0402_5%@RC28 10K_0402_5%@

RC29 10K_0402_5%@RC29 10K_0402_5%@

+3VALW_PCH

RC31 8.2K_0402_5%RC31 8.2K_0402_5%

RC32 10K_0402_5%RC32 10K_0402_5%

RC34 10K_0402_5%RC34 10K_0402_5%

+3VS

RC36 8.2K_0402_5%RC36 8.2K_0402_5%

SYS_PWROK

CC31

0.047U_0402_16V4Z

Place CC31 on BOT

PCH_PWROK

CC34

0.047U_0402_16V4Z

Place CC34 close to RP50.2&RP50.3

+3VS

RC73 10K_0402_5%RC73 10K_0402_5%

RC74 10K_0402_5%RC74 10K_0402_5%

RC75 10K_0402_5%

RC76 10K_0402_5%RC76 10K_0402_5%

RC77 10K_0402_5%RC77 10K_0402_5%

RC87 100K_0402_5%@RC87 100K_0402_5%@

RC88 1K_0402_1%@RC88 1K_0402_1%@

1 2

ESD@CC31

ESD@

ESD@CC34

ESD@

1 2

@

1 2

ME_SUS_PWR_ACK

SUSACK#

SUS_STAT#/LPCPD#

PCH_BATLOW#

AC_PRESENT

PCIE_WAKE#_R

CLKRUN#

1

2

1

2

DGPU_PWROK

TOUCHPAD_INTR#

EDP_BIA_PWM

TOUCH_RST_N_GYRO_INT1

DGPU_HOLD_RST#

ENVDD_PCH

12

CODEC_IRQ

PCH_DPWROK

ME_SUS_PWR_ACK_R SUSACK#

Note: SUSACK# and SUSWARN# can be tied together if EC does not want to involve in the handshake mechanism for the Deep Sleep state entry and exit CAN be NC ,if not support Deep Sx DPWROK: Tired toghter with RSMRST#

SUSACK#<30>

SYS_PWROK<30,6> PCH_PWROK<30>

ME_SUS_PWR_ACK<30>

ACIN<30,36,37,49>

EDP_BIA_PWM<19,6>

SUSACK# SUSACK#_R

SYS_PWROK

EC_RSMRST#<30>

PANEL_BKLEN<30>

1 2

DH1 RB751V-40_SOD323-2DH1 RB751V-40_SOD323-2

PCH_BATLOW# Need pull high to VCCDSW3_3 (If no deep Sx , connect to VCCSUS3_3)

1 2

@

RC33 0_0402_1%

1 2

RC35 0_0402_5%@RC35 0_0402_5%@

1 2

RC37 0_0402_5%@RC37 0_0402_5%@

RP50

RP50 0_8P4R_5%

0_8P4R_5%

1 2

RC41 0_0402_1%@RC41 0_0402_1%@

1 2

RC42 0_0402_1%@RC42 0_0402_1%@

PBTN_OUT#<30,6>

SIO_SLP_S0#<30>

DGPU_HOLD_RST#<48>

ENVDD_PCH<19,30>

DGPU_PWROK<30,44> PXS_PWREN<11,39,43,44,50>

SYS_RESET#<6>

@

RC81

RC81 0_0402_1%

0_0402_1%

1 8 2 7 3 6 4 5

PCH_RSMRST#_R

SYS_RESET# SYS_PWROK_R PCH_PWROK_R PM_APWROK_R PCH_PLTRST#

PCH_RSMRST#_R ME_SUS_PWR_ACK_R PBTN_OUT# AC_PRESENT PCH_BATLOW# SIO_SLP_S0#

12

EDP_BKLCTLEDP_BIA_PWM PANEL_BKLEN ENVDD_PCH

DGPU_PWROK PXS_PWREN DGPU_HOLD_RST#

T117 @T117 @

TOUCHPAD_INTR# TOUCH_RST_N_GYRO_INT1

CODEC_IRQ

0.047U_0402_16V4Z

Place CC33 close to UC3.1 & UC3.2

UC1H

AK2

SUSACK

AC3

SYS_RESET

AG2

SYS_PWROK

AY7

PCH_PWR OK

AB5

APWROK

AG7

PLTRST

AW6

RSMRST

AV4

SUSWARN/SUS PWRDNACK/GPIO30

AL7

PWRBTN

AJ8

ACPRESENT/GPIO31

AN4

BATLOW/GPIO72

AF3

SLP_S0

AM5

SLP_WLAN/GPIO29

UC1I

B8

EDP_BKLCTL

A9

EDP_BKLEN

C6

EDP_VDDEN

U6

PIRQA/GPIO77

P4

PIRQB/GPIO78

N4

PIRQC/GPIO79

N2

PIRQD/GPIO80

AD4

PME

U7

GPIO55

L1

GPIO52

L3

GPIO54

R5

GPIO51

L4

GPIO53

1

ESD@CC33

ESD@

2

PCH_PLTRST#

HASWELL_MCP_E

SYSTEM POWER MANAGEMENT

HASWELL_MCP_E

eDP SIDEBAND

GPIO

8 OF 19

9 OF 19

that do not support Deep Sx

SUS_STAT/GPIO61

DDPB_CTRL CLK

DDPB_CTRL DATA

DDPC_CTR LCLK

DDPC_CTR LDATA

DISPLAY

+3VS

5

1

IN1

2

IN2

3

DSWVRMEN

DPWROK

CLKRUN/GPIO32

SUSCLK/GPIO62

SLP_S5/GPIO63

SLP_S4 SLP_S3

SLP_SUS

SLP_LAN

DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP

DDPB_HPD DDPC_HPD

EDP_HPD

Rev1p2

CC11

@CC11

@

1 2

0.1U_0402_10V7K

VCC

4

PLT_RST#

OUT

GND

UC3

MC74VHC1G08DFT2G_SC70-5

AW7

DSWODVREN

AV5

PCH_DPWROK

AJ5

WAKE

V5

CLKRUN#

AG4

SUS_STAT#/LPCPD#

AE6

SUSCLK

AP5

SIO_SLP_S5#

AJ6

SIO_SLP_S4#

AT4

SIO_SLP_S3#

AL5

SLP_A

AP4 AJ7

Rev1p2

B9

CPU_DPB_CTRLCLK

C9

CPU_DPB_CTRLDAT

D9

CPU_DPC_CTRLCLK

D11

CPU_DPC_CTRLDAT

C5

CPU_DPB_AUX#

B6

CPU_DPC_AUX#

B5

CPU_DPB_AUX

A6

CPU_DPC_AUX

C8

DPB_HPD

A8

DPC_HPD

D6

CPU_EDP_HPD#

DPC_HPD

CPU_EDP_HPD#

12

R159

100K_0402_5%

DSWODVREN - On Die DSW VR Enable H

*

L

R2337 330K_0402_5%R2337 330K_0402_5% R2338 330K_0402_5%@R2338 330K_0402_5%@

T105@ T105@ T106@ T106@ T107@ T107@

RC84

100K_0402_5%

1 2

RC89

100K_0402_5%

PLT_RST# <21,26,30,48,6>

：：：：

Enable(DEFAULT)

：：：：

Disable

1 2 1 2

1 2

PCIE_WAKE#PCIE_WAKE#_R

@

RC97

RC97 0_0402_5%

0_0402_5%

T102 PAD~D@T102 PAD~D @

SIO_SLP_S5# <30>

T103 PAD~D@T103 PAD~D @

@

T104 PAD~D

SIO_SLP_S4# <30> SIO_SLP_S3# <30>

CPU_DPB_CTRLCLK <20> CPU_DPB_CTRLDAT <20>

DPB_HPD <20>

12

+RTCVCC

PCH_DPWROK <30>

PCIE_WAKE# <21,30>

eDP HPD INVERSION

DSWODVREN - ON DIE DSW VR ENABLE

HIGH = ENABLED (DEFAULT)

LOW = DISABLED

CPU_DPB_CTRLCLK CPU_DPB_CTRLDAT CPU_DPC_CTRLCLK CPU_DPC_CTRLDAT

CPU_DPB_AUX# CPU_DPC_AUX# CPU_DPB_AUX CPU_DPC_AUX

EDP_CPU_HPD<19>

1 8 2 7 3 6 4 5

RP52

2.2K_8P4R_5%

1 8 2 7 3 6 4 5

RP51

RP51 100K_8P4R_5%

100K_8P4R_5%

+VCCIOA_OUT

2

G

12

13

D

S

+3VS

RC78

@RC78

@

10K_0402_5%

CPU_EDP_HPD#

QC3

@

QC3

@

2N7002K_SOT23-3

symbol OK

A A

RC105

1 2

0_0402_5%

CPU_EDP_HPD#EDP_CPU_HPD

Reserve for eDP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

MCP(8,9/19) DDI,EDP,GPIO

LA-9984P

1

10 57Wednesday, May 22, 2013

1.0

5

D D

4

3

2

1

12

SUN@

RC112

RC112 10K_0402_5%

10K_0402_5%

12

VENUS@

RC113

RC113 10K_0402_5%

10K_0402_5%

+1.05VS

Close to R2346

1

CC28

CC28 100P_0402_50V8J

100P_0402_50V8J

ESD@

2

ESD solution

KB_RST# <30>

SERIRQ <30>

+3VS+3VS

12

UMA@

RC100

RC100 10K_0402_5%

10K_0402_5%

DIS@

RC99

RC99 10K_0402_5%

10K_0402_5%

SERIRQ

LCD_CBL_DET#

CPPE#

CPUSB#

I2C1_SDA_TCH_PAD I2C1_SCL_TCH_PAD I2C0_SDA I2C0_SCL

KB_RST# TOUCH_PANEL_INTR#

12

RC10210K_0402_5% RC10210K_0402_5%

12

RC10610K_0402_5% RC10610K_0402_5%

12

RC108100K_0402_5% RC108100K_0402_5%

12

RC111100K_0402_5% RC111100K_0402_5%

RP53

1 8 2 7 3 6 4 5

2.2K_0804_8P4R_5%

RP43

18 27 36 45

10K_8P4R_5%

+3VS

+1.05VS

T177PAD~D @T177PAD~D @ T176PAD~D @T176PAD~D @ T175PAD~D @T175PAD~D @

T178PAD~D @T178PAD~D @ T179PAD~D @T179PAD~D @

T180PAD~D @T180PAD~D @ T181PAD~D @T181PAD~D @

12

R2346

R2346 1K_0402_5%

1K_0402_5%

HASWELL_MCP_E

UC1J

PCH_AUDIO_EN

T182 PAD~D@ T182 PAD~D@

EC_LID_OUT#<30>

ODD_EN#<32>

ODD_DA#<32> BT_ON#<26>

"KB_DET#" for OAK 17 only

+3VS

12

RP54

18 27 36 45

8.2K_8P4R_5%

DEVSLP0

SIO_EXT_SCI#

HDD_DET#

KB_DET#

PCH_GPIO44

SLATE_MODE_R

PCH_AUDIO_EN

ODD_DA# BT_ON# WL_OFF# PXS_PWREN

PXS_PWREN <10,39,43,44,50>

C C

B B

RC11 10K_0402_5%RC11 10K_0402_5%

RC98 100K_0402_5%RC98 100K_0402_5%

RC9 100K_0402_5%RC9 100K_0402_5%

+3VALW_PCH

RC103 10K_0402_5%RC103 10K_0402_5%

RC104 10K_0402_5%RC104 10K_0402_5%

RC110 10K_0402_5%RC110 10K_0402_5%

RC116 10K_0402_5%RC116 10K_0402_5%

+3VS

KB_DET#<32>

HDD_DET#<32>

WL_OFF#<26>

T174 PAD~D@ T174 PAD~D@ T124 PAD~D@ T124 PAD~D@ T125 PAD~D@ T125 PAD~D@

T126 PAD~D@ T126 PAD~D@ T127 PAD~D@ T127 PAD~D@

EC_SCI#<30>

DEVSLP0<32>

HDA_SPKR<22>

PCH_GPIO12 EC_LID_OUT# ODD_EN# ODD_DA# BT_ON# KB_DET# HOST_ALERT1_R_N

HDD_DET#

SLATE_MODE_R WL_OFF# PCH_GPIO44 PCH_GPIO47 PCH_GPIO48 PCH_GPIO49 TOUCH_PANEL_INTR#

PCH_GPIO14 PCH_GPIO25

PCH_GPIO46

PCH_GPIO9 EC_SCI# DEVSLP0

SIO_EXT_SCI# HDA_SPKR

+3VS +3VS

12

@

RC118

RC118 1K_0402_5%

1K_0402_5%

PCH_GPIO66

12

@

RC122

RC122 1K_0402_5%

1K_0402_5%

GPIO66 GPIO86 GPIO15 GPIO81

TOP-BLOCK SWAP OVERRIDE

HIGH depop RC288 (DEFAULT) LOW pop RC288

+3VALW_PCH

12

RC124

RC124 10K_0402_5%

10K_0402_5%

PCH_GPIO46

P1

BMBUSY/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR _CTRL/GPIO12

AD6

GPIO15

Y1

GPIO16

T3

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN /GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

+3VALW_PCH

HASWELL_MCP_E

GPIO

10 OF 19

12

@

RC119

RC119 10K_0402_5%

10K_0402_5%

BBS_BIT

12

RC123

RC123 1K_0402_5%

1K_0402_5%

BOOT BIOS STRAP BIT BBS

HIGH LOW(DEFAULT)

12

RC125

RC125 10K_0402_5%

10K_0402_5%

PCH_GPIO9

LPC SPI

CPU/

CPU/ MISC

MISC

GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86

GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90 UART0_RXD/GPIO91 UART0_TXD/GPIO92 UART0_RTS/GP IO93

LPIO

UART0_CTS/GP IO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1 UART1_RST/GP IO2 UART1_CTS/GP IO3

SDIO_CMD/GPIO65

+3VALW_PCH

12

@

RC120

RC120 1K_0402_5%

1K_0402_5%

HOST_ALERT1_R_N

TLS CONFIDENTIALITY

HIGH LOW(DEFAULT)

THERMTRIP

RCIN/GPIO82

SERIRQ

PCH_OPI_RCOMP

RSVD RSVD

GSPI0_CS/GPIO83

GSPI1_CS/GPIO87

I2C0_SDA/GPIO4

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69

Rev1p2

GPIO15 NOT Used

D60

H_THERMTRIP#

V4

KB_RST#

T4

SERIRQ

AW15

PCH_OPI_COMP

AF20 AB21

R6

PCH_GPIO83

L6

PCH_GPIO84

N6

PCH_GPIO85

L8

BBS_BIT

R7

DGPU_PRSNT#

L5

Project_ID

N7

PCH_GPIO89

K2

PCH_GPIO90

J1

CPPE#

K3

CPUSB#

J2

PCH_GPIO93

G1

PCH_GPIO94

K4 G2 J3

LCD_CBL_DET#

J4 F2

I2C0_SDA

F3

I2C0_SCL

G4

I2C1_SDA_TCH_PAD

F1

I2C1_SCL_TCH_PAD

E3 F4 D3

PCH_GPIO66

E4 C3 E2

1 2

+3VS

12

@

RC121

RC121 1K_0402_5%

1K_0402_5%

HDA_SPKR

NO REBOOT STRAP

HIGH LOW(DEFAULT)

RC101

49.9_0402_1%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

MCP(10/19) GPIO,LPIO,MISC

LA-9984P

1

11 57Wednesday, May 22, 2013

1.0

5

D D

PEG_CRX_GTX_N0<48> PEG_CRX_GTX_P0<48>

PEG_CTX_GRX_N0<48> PEG_CTX_GRX_P0<48>

PEG_CRX_GTX_N1<48> PEG_CRX_GTX_P1<48>

PEG_CTX_GRX_N1<48> PEG_CTX_GRX_P1<48>

PEG_CRX_GTX_N2<48> PEG_CRX_GTX_P2<48>

PEG_CTX_GRX_N2<48> PEG_CTX_GRX_P2<48>

PEG_CRX_GTX_N3<48> PEG_CRX_GTX_P3<48>

PEG_CTX_GRX_N3<48>

C C

10/100 LAN

WLAN (Mini Card)

B B

PEG_CTX_GRX_P3<48>

PCIE_PRX_LANTX_N3<21> PCIE_PRX_LANTX_P3<21>

PCIE_PTX_LANRX_N3<21> PCIE_PTX_LANRX_P3<21>

PCIE_PRX_WLANTX_N4<26> PCIE_PRX_WLANTX_P4<26>

PCIE_PTX_WLANRX_N4<26> PCIE_PTX_WLANRX_P4<26>

PEG_CRX_GTX_N0 PEG_CRX_GTX_P0

PEG_CTX_GRX_N0 PEG_CTX_GRX_P0

PEG_CRX_GTX_N1 PEG_CRX_GTX_P1

PEG_CRX_GTX_N2 PEG_CRX_GTX_P2

PEG_CRX_GTX_N3 PEG_CRX_GTX_P3

PCIE_PRX_LANTX_N3 PCIE_PRX_LANTX_P3

PCIE_PTX_LANRX_N3 PCIE_PTX_LANRX_P3

PCIE_PRX_WLANTX_N4 PCIE_PRX_WLANTX_P4

PCIE_PTX_WLANRX_N4 PCIE_PTX_WLANRX_P4

+1.05VS_AUSB3PLL

4

12

CC18 0.1U_0402_10V7KDIS@ CC18 0.1U_0402_10V7KDIS@

12

CC19 0.1U_0402_10V7KDIS@ CC19 0.1U_0402_10V7KDIS@

12

CC20 0.1U_0402_10V7KDIS@ CC20 0.1U_0402_10V7KDIS@

12

CC21 0.1U_0402_10V7KDIS@ CC21 0.1U_0402_10V7KDIS@

12

CC22 0.1U_0402_10V7KDIS@ CC22 0.1U_0402_10V7KDIS@

12

CC23 0.1U_0402_10V7KDIS@ CC23 0.1U_0402_10V7KDIS@

12

CC24 0.1U_0402_10V7KDIS@ CC24 0.1U_0402_10V7KDIS@

12

CC25 0.1U_0402_10V7KDIS@ CC25 0.1U_0402_10V7KDIS@

1 2

CC32 0.1U_0402_10V7KCC32 0.1U_0402_10V7K

1 2

CC40 0.1U_0402_10V7KCC40 0.1U_0402_10V7K

RC91

3.01K_0402_1%

1 2

PEG_CTX_GRX_C_N0 PEG_CTX_GRX_C_P0

PEG_CTX_GRX_C_N1PEG_CTX_GRX_N1 PEG_CTX_GRX_C_P1PEG_CTX_GRX_P1

PEG_CTX_GRX_C_N2PEG_CTX_GRX_N2 PEG_CTX_GRX_C_P2PEG_CTX_GRX_P2

PEG_CTX_GRX_C_N3PEG_CTX_GRX_N3 PEG_CTX_GRX_C_P3PEG_CTX_GRX_P3

PCIE_PTX_LANRX_N3_C PCIE_PTX_LANRX_P3_C

T120PAD~D@T120PAD~D@ T121PAD~D@T121PAD~D@

PCH_PCIE_RCOMP

F10

PERN5_L0

E10

PERP5_L0

C23

PETN5_L0

C22

PETP5_L0

F8

PERN5_L1

E8

PERP5_L1

B23

PETN5_L1

A23

PETP5_L1

H10

PERN5_L2

G10

PERP5_L2

B21

PETN5_L2

C21

PETP5_L2

E6

PERN5_L3

F6

PERP5_L3

B22

PETN5_L3

A21

PETP5_L3

G11

PERN3

F11

PERP3

C29

PETN3

B30

PETP3

F13

PERN4

G13

PERP4

B29

PETN4

A29

PETP4

G17

PERN1/USB3RN 3

F17

PERP1/USB3RP3

C30

PETN1/USB3T N3

C31

PETP1/USB3T P3

F15

PERN2/USB3RN 4

G15

PERP2/USB3RP4

B31

PETN2/USB3T N4

A31

PETP2/USB3T P4

E15

RSVD

E13

RSVD

A27

PCIE_RCOMP

B27

PCIE_IREF

UC1K

PCIe

3

HASWELL_MCP_E

11 OF 19

2

AN8 AM8

AR7 AT7

AR8 AP8

AR10 AT10

AM15 AL15

AM13 AN13

AP11 AN11

AR13 AP13

G20 H20

C33 B34

E18 F18

B33 A33

AJ10 AJ11 AN10 AM10

AL3 AT1 AH2 AV3

USB20_JUSB2_N0 USB20_JUSB2_P0

USB20_JUSB1_N1 USB20_JUSB1_P1

USB20_JUSB3_N2 USB20_JUSB3_P2

USB20_USBDB_N3 USB20_USBDB_P3

USB20_MINI1_N4 USB20_MINI1_P4

USB20_TOUCH_N5 USB20_TOUCH_P5

USB20_CR_N6 USB20_CR_P6

USB20_CAM_N7 USB20_CAM_P7

USB3RN1_JUSB2 USB3RP1_JUSB2

USB3TN1_JUSB2 USB3TP1_JUSB2

USB3RN2_JUSB1 USB3RP2_JUSB1

USB3TN2_JUSB1 USB3TP2_JUSB1

USBRBIAS

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

USB2N0 USB2P0

USB2N1 USB2P1

USB2N2 USB2P2

USB2N3 USB2P3

USB2N4 USB2P4

USB2N5 USB2P5

USB2N6 USB2P6

USB2N7 USB2P7

USB3RN1 USB3RP1

USB

USB3TN1 USB3TP1

USB3RN2 USB3RP2

USB3TN2 USB3TP2

USBRBIAS USBRBIAS

RSVD RSVD

OC0/GPIO40 OC1/GPIO41 OC2/GPIO42 OC3/GPIO43

Rev1p2

USB20_JUSB2_N0 <24> USB20_JUSB2_P0 <24>

USB20_JUSB1_N1 <24> USB20_JUSB1_P1 <24>

USB20_JUSB3_N2 <25> USB20_JUSB3_P2 <25>

USB20_USBDB_N3 <25> USB20_USBDB_P3 <25>

USB20_MINI1_N4 <26> USB20_MINI1_P4 <26>

USB20_TOUCH_N5 USB20_TOUCH_P5

USB20_CR_N6 <23> USB20_CR_P6 <23>

USB20_CAM_N7 <31> USB20_CAM_P7 <31>

USB3RN1_JUSB2 <24>

USB3RP1_JUSB2 <24>

USB3TN1_JUSB2 <24> USB3TP1_JUSB2 <24>

USB3RN2_JUSB1 <24>

USB3RP2_JUSB1 <24>

USB3TN2_JUSB1 <24> USB3TP2_JUSB1 <24>

T118PAD~D @T118PAD~D @ T119PAD~D @T119PAD~D @

USB_OC0# <24> USB_OC1# <25>

USB Conn JUSB2

USB Conn JUSB1

USB Conn JUSB3

USB Conn 4 (DB)

Mini Card (WLAN)

Touch screen panel

"USB20_TOUCH_N5/USB20_TOUCH_P5" for OAK 15 only

Card Reader

Camera

USB Conn JUSB2

USB Conn JUSB1

12

RC90

22.6_0402_1%~D

CAD NOTE: Route single-end 50-ohms and max 500-mils length. Avoid routing next to clock pins or under stitching capacitors. Recommended minimum spacing to other signal traces is 15 mils.

1

+3VALW_PCH

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

1 8 2 7 3 6 4 5

RP55

RP55 10K_8P4R_5%

10K_8P4R_5%

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

MCP(11/19) PCIE,USB

LA-9984P

1

1.0

12 57Wednesday, May 22, 2013

1.0

5

4

3

2

1

VCCST_PG_EC

220P_0402_50V8J

D D

220P_0402_50V8J

Place C79 between R286 and UC1

VCCST_PG_EC<30>

1

C79

ESD@C79

ESD@

2

VCCST_PG_EC

+1.05VS

12

R286

R286 10K_0402_5%

10K_0402_5%

+CPU_CORE

Define EC OD pin, need double confirm.

VR_ON

0.1U_0402_10V7K

SVID ALERT

C C

VR_SVID_ALRT#<42>

SVID DATA

SVID_DAT need to pull-up double side ( PWR_VR & CPU )

VR_SVID_DAT<42>

B B

VCCSENSE<42>

VCCSENSE

+CPU_CORE

12

R1

R1 100_0402_1%

100_0402_1%

+1.05VS

12

Place the PU

R252

resistors close to CPU

75_0402_5%

R254

R254 43_0402_1%

43_0402_1%

12

H_CPU_SVIDALRT#

+1.05VS

Place the PU

12

resistors close to CPU

R256

R256 130_0402_1%

@

R257

R257 0_0402_1%

0_0402_1%

130_0402_1%

12

H_CPU_SVIDDATA

CAD Note: PU resistor on HW side

0.1U_0402_10V7K

Place C80 close to R250.1

1

C80

ESD@C80

ESD@

2

VR_SVID_CLK<42>

H_VR_READY<42>

CPU_PWR_DEBUG#<6>

RF

RF@

C5212

C5212 68P_0402_50V8J

68P_0402_50V8J

+1.05VS

@

R253

150_0402_1%

1 2

INTEL Check list , XDP use only

CPU_PWR_DEBUG#

@

R255

R255 10K_0402_5%

10K_0402_5%

C40

1 2

22U_0603_6.3V6M

ESD@

ESD solution

R245 0_0603_5%

0_0603_5%

VR_ON<30,42>

+1.35V

+VCCIO_OUT

@R245

@

+VCCIOA_OUT

H_CPU_SVIDCLK

1

2

1 2

+CPU_CORE

1 2

1 2 1 2

+CPU_CORE

+1.35V

1

2

+1.35V

+VCCIO_OUT_R

R2480_0402_1% @ R2480_0402_1% @

R2500_0402_5% R2500_0402_5% R2510_0402_1% @ R2510_0402_1% @

+1.05VS

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M C35

C35

1

2

VCCSENSE

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDATA VCCST_PG_EC VR12.5_VR_ON_R VR_READY_R

CPU_PWR_DEBUG#

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M C36

C36

L59 J58

AH26

AJ31 AJ33

AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50

F59

N58

AC58

E63

AB23

T38 @T38 @

A59

E20 AD23 AA23 AE59

L62

N63

L63

B59

F60

C59

D63

H59

P62

P60

T39 @T39 @

P61

T40 @T40 @

N59

T41 @T41 @

N61

T42 @T42 @

T59

T43 @T43 @

AD60

T44 @T44 @

AD59

T45 @T45 @

AA59

T46 @T46 @

AE60

T47 @T47 @

AC59

T48 @T48 @

AG58

T49 @T49 @

U59

T50 @T50 @

V59

T51 @T51 @

AC22 AE22 AE23

AB57 AD57 AG57

C24

C28

C32

VDDQ DECOUPLING

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M C38

C38

C37

10U_0603_6.3V6M

1

2

1

C39

2

UC1L

RSVD RSVD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCC RSVD RSVD

VCC_SENSE RSVD VCCIO_OUT VCCIOA_OUT RSVD RSVD RSVD

VIDALERT VIDSCLK VIDSOUT VCCST_PWR GD VR_EN VR_READY

VSS PWR_DEBU G VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VCCST VCCST VCCST

VCC VCC VCC VCC VCC VCC

10U_0603_6.3V6M

1

C41

2

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

Rev1p2

C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57

+CPU_CORE

HASWELL_MCP_E

12 OF 19

HSW ULT POWER

10U_0603_6.3V6M

1

C72

C42

2

10U_0603_6.3V6M

1

C74

C45

2

VSSSENSE<15,42>

A A

VSSSENSE

12

R2

R2 100_0402_1%

100_0402_1%

5

CAD Note: PD resistor on HW side

+1.35V : 470UF/2V/7343 *2 (PWR) 10UF/6.3V/0603 * 6

2.2UF/6.3V/0402 * 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

MCP(12/19) Power

LA-9984P

1

13 57Wednesday, May 22, 2013

1.0

5

D D

Close to N8

1 2

+1.05VS

+1.05VS +1.05VS_AUSB3PLL

1 2

L1

2.2UH_LQM2MPN2R2NG0L_30%

1 2

L2

2.2UH_LQM2MPN2R2NG0L_30%

R267

R267 0_0805_1%

0_0805_1%

1 2

@

1 2

L3

@L3

@

2.2UH_LQM2MPN2R2NG0L_30%

1 2

L4

2.2UH_LQM2MPN2R2NG0L_30%

C C

B B

2.2UH_LQM2MPN2R2NG0L_30%

+1.05VS_AXCK_LCPLL

1 2

L5

2.2UH_LQM2MPN2R2NG0L_30%

+1.5VS +3VS

+VCCHDA

Reserve for HDA issue, C77 close to AH14

+1.05VS

+3VALW_PCH

C57 1U_0402_6.3V6K@C57 1U_0402_6.3V6K@

1 2

C58 1U_0402_6.3V6KC58 1U_0402_6.3V6K

1 2

C59 100U_1206_6.3V6M C59 100U_1206_6.3V6M

+1.05VS_ASATA3PLL

1 2

C63 1U_0402_6.3V6KC63 1U_0402_6.3V6K

1 2

C65 100U_1206_6.3V6M C65 100U_1206_6.3V6M

+1.05VS_APLLOPI

C69 1U_0402_6.3V6KC69 1U_0402_6.3V6K C70 100U_1206_6.3V6M@C70 100U_1206_6.3V6M@

+1.05VS_AXCK_DCB

C83 1U_0402_6.3V6KC83 1U_0402_6.3V6K C84 100U_1206_6.3V6M C84 100U_1206_6.3V6M

C85 1U_0402_6.3V6KC85 1U_0402_6.3V6K C86 100U_1206_6.3V6M C86 100U_1206_6.3V6M

1 2

RC127 0_0402_5%RC127 0_0402_5%

1 2

RC128 0_0402_5%@RC128 0_0402_5%@

1 2

RC129 0_0402_5%@RC129 0_0402_5%@

C77 0.1U_0402_10V7KC77 0.1U_0402_10V7K

1 2

C50 1U_0402_6.3V6KC50 1U_0402_6.3V6K

1 2

C53 1U_0402_6.3V6KC53 1U_0402_6.3V6K

1 2

C81 0.1U_0402_10V7K

@

1 2

C78 22U_0603_6.3V6MC78 22U_0603_6.3V6M

1 2 1 2

1 2

4

+1.05VS_ASATA3PLL

+VCCHDA+3VALW_PCH

+1.05VS_AXCK_LCPLL

Close to K9,M9

Close to AH10

Close to AC9/AA9/AE20/AE21

+1.05VS

+1.05VS_AUSB3PLL

+1.05VS_APLLOPI

T53 @T53 @

+VCCHDA

T55 @T55 @

+3VALW_PCH

+3VS

+1.05VS_AXCK_DCB

+1.05VS +1.05VS

+3VALW_PCH

AA21

AH14

AH13

AH10

AE20 AE21

L10

B18 B11

Y20

W21

J13

AC9 AA9

W9

J18 K19 A20

J17 R21 T21 K18 M20 V21

K9

M9

N8 P9

V8

UC1M

VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL

RSVD VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3

VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD RSVD RSVD VCCSUS3_3 VCCSUS3_3

mPHY

OPI

USB3

AXALIA/HDA

VRM/USB2/AZALIA

GPIO/LCC

LPT LP POWER

HASWELL_MCP_E

13 OF 19

3

RTC

SPI

CORE

THERMAL SENSOR

SDIO/PLSS

SUS OSCILLATOR

USB2

VCCSUS3_3

VCCRTC DCPRTC

VCCSPI

VCCASW VCCASW

VCC1_05 VCC1_05 VCC1_05 VCC1_05

VCC1_05 DCPSUSBYP DCPSUSBYP

VCCASW

DCPSUS1 DCPSUS1

VCCTS1_5

VCC3_3 VCC3_3

VCCSDIO

DCPSUS4

RSVD VCC1_05 VCC1_05

Rev1p2

AH11

C51 1U_0402_6.3V6KC51 1U_0402_6.3V6K

AG10 AE7

+VCCRTCEXT

Y8

C68 0.1U_0402_10V7K@ C68 0.1U_0402_10V7K@

AG14 AG13

J11

C60 10U_0603_6.3V6M C60 10U_0603_6.3V6M

H11

C61 1U_0402_6.3V6KC61 1U_0402_6.3V6K

H15

C62 1U_0402_6.3V6KC62 1U_0402_6.3V6K

AE8 AF22 AG19

+PCH_VCCDSW

AG20 AE9 AF9

C66 22U_0603_6.3V6M@ C66 22U_0603_6.3V6M@

AG8

C67 1U_0402_6.3V6KC67 1U_0402_6.3V6K

AD10 AD8

T58 @T58 @ T59 @T59 @

J15 K14 K16

1 2

C71 0.1U_0402_10V7KC71 0.1U_0402_10V7K

U8

1 2

T9

C73 1U_0402_6.3V6KC73 1U_0402_6.3V6K

AB8

T56 @T56 @

AC20 AG16

+1.05VS

AG17

1 2

C76 1U_0402_6.3V6KC76 1U_0402_6.3V6K

12

1 2

1 2 1 2 1 2

1 2 1 2

R2640_0603_1% @ R2640_0603_1% @

+RTCVCC

1 2

C52 0.1U_0402_10V7KC52 0.1U_0402_10V7K

+3VS

+1.05VS

1 2

+PCH_VCCDSW_R

@

R265 0_0402_1%

+3VALW_PCH

+1.05VS

+1.5VS +3VS

+3VS

2

C64

C64 1U_0402_6.3V6K

1U_0402_6.3V6K

1 2

+RTCVCC

1

C54

2

1U_0402_6.3V6K

+1.05VS

22U_0603_6.3V6M

ESD solution

22U_0603_6.3V6M

ESD solution

C55

0.1U_0402_10V7K

C44

1 2

ESD@

C43

1 2

ESD@

1

C56

2

0.1U_0402_10V7K

+3VS

+1.35V+1.05VS

1 2

C82 22U_0603_6.3V6MC82 22U_0603_6.3V6M

+3VS

1 2

+1.05VS

+3VALW_PCH

A A

5

C87 1U_0402_6.3V6KC87 1U_0402_6.3V6K

1 2

C88 1U_0402_6.3V6K

12

C75 0.1U_0402_10V7KC75 0.1U_0402_10V7K

Close to V8

Close to J17

Close to R21

Close to AH14

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

MCP(13/19) Power

LA-9984P

1

14 57Wednesday, May 22, 2013

1.0

5

D D

HASWELL_MCP_E

UC1N

A11

VSS

A14

VSS

A18

VSS

A24

VSS

A28

VSS

A32

VSS

A36

VSS

A40

VSS

A44

VSS

A48

VSS

A52

VSS

A56

VSS

AA1

VSS

AA58

VSS

AB10

VSS

AB20

VSS

C C

B B

AB22

AC61 AD21

AD63 AE10

AE58

AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57

AF11 AF12 AF14 AF15 AF17 AF18

AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

VSS

AB7

VSS VSS VSS

AD3

VSS VSS VSS

AE5

VSS VSS VSS VSS VSS VSS VSS VSS

AG1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

14 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Rev1p2

AJ35 AJ39 AJ41 AJ43 AJ45 AJ47 AJ50 AJ52 AJ54 AJ56 AJ58 AJ60 AJ63 AK23 AK3 AK52 AL10 AL13 AL17 AL20 AL22 AL23 AL26 AL29 AL31 AL33 AL36 AL39 AL40 AL45 AL46 AL51 AL52 AL54 AL57 AL60 AL61 AM1 AM17 AM23 AM31 AM52 AN17 AN23 AN31 AN32 AN35 AN36 AN39 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN51 AN52 AN60 AN63 AN7 AP10 AP17 AP20

4

HASWELL_MCP_E

UC1O

AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49

AR52

AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59

AP22 AP23 AP26 AP29

AP31 AP38 AP39 AP48 AP52 AP54 AP57

AR5

AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63

AU1

AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

VSS VSS VSS VSS

AP3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

15 OF 19

Rev1p2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AV59 AV8 AW16 AW24 AW33 AW35 AW37 AW4 AW40 AW42 AW44 AW47 AW50 AW51 AW59 AW60 AY11 AY16 AY18 AY22 AY24 AY26 AY30 AY33 AY4 AY51 AY53 AY57 AY59 AY6 B20 B24 B26 B28 B32 B36 B4 B40 B44 B48 B52 B56 B60 C11 C14 C18 C20 C25 C27 C38 C39 C57 D12 D14 D18 D2 D21 D23 D25 D26 D27 D29 D30 D31

3

UC1P

HASWELL_MCP_E

D33

VSS

D34

VSS

D35

VSS

D37

VSS

D38

VSS

D39

VSS

D41

VSS

D42

VSS

D43

VSS

D45

VSS

D46

VSS

D47

VSS

D49

VSS

D5

VSS

D50

VSS

D51

VSS

D53

VSS

D54

VSS

D55

VSS

D57

VSS

D59

VSS

D62

VSS

D8

VSS

E11

VSS

E17

VSS

F20

VSS

F26

VSS

F30

VSS

F34

VSS

F38

VSS

F42

VSS

F46

VSS

F50

VSS

F54

VSS

F58

VSS

F61

VSS

G18

VSS

G22

VSS

G3

VSS

G5

VSS

G6

VSS

G8

VSS

H13

VSS

16 OF 19

VSS_SENSE

Rev1p2

2

H17

VSS

H57

VSS

J10

VSS

J22

VSS

J59

VSS

J63

VSS

K1

VSS

K12

VSS

L13

VSS

L15

VSS

L17

VSS

L18

VSS

L20

VSS

L58

VSS

L61

VSS

L7

VSS

M22

VSS

N10

VSS

N3

VSS

P59

VSS

P63

VSS

R10

VSS

R22

VSS

R8

VSS

T1

VSS

T58

VSS

U20

VSS

U22

VSS

U61

VSS

U9

VSS

V10

VSS

V3

VSS

V7

VSS

W20

VSS

W22

VSS

Y10

VSS

Y59

VSS

Y63

VSS

V58

VSS

AH46

VSS

V23

VSS

E62 AH16

VSS

12

X@

RC163

RC163 100_0402_1%

100_0402_1%

VSSSENSE <13,42>

1

CAD Note: RC163 SHOULD BE PLACED CLOSE TO CPU

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

MCP(14,15,16/19) VSS

LA-9984P

1

15 57Wednesday, May 22, 2013

1.0

5

D D

HASWELL_MCP_E

UC1S

HASWELL_MCP_E

17 OF 19

UC1Q

DC_TEST_AY2_AW2 DC_TEST_AY3_AW3

T166PAD~D@T166PAD~D@

T167PAD~D@T167PAD~D@

C C

DC_TEST_AY60 DC_TEST_AY61_AW61 DC_TEST_AY62_AW62 TP_DC_TEST_B2 DC_TEST_A3_B3 DC_TEST_A61_B61

DC_TEST_B62_B63

DC_TEST_C1_C2 DC_TEST_AY62_AW62

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

4

DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW6 1 DAISY_CHAIN_NCTF_AW6 2 DAISY_CHAIN_NCTF_AW6 3

Rev1p2

HASWELL_MCP_E

A3

DC_TEST_A3_B3

A4

DC_TEST_A4

A60

DC_TEST_A60

A61

DC_TEST_A61_B61

A62

DC_TEST_A62

AV1

DC_TEST_AV1

AW1

DC_TEST_AW1

AW2

DC_TEST_AY2_AW2

AW3

DC_TEST_AY3_AW3

AW61

DC_TEST_AY61_AW61

AW62 AW63

DC_TEST_AW63

T168PAD~D @T168PAD~D @

T169PAD~D @T169PAD~D @

T170PAD~D @T170PAD~D @ T171PAD~D @T171PAD~D @ T172PAD~D @T172PAD~D @

T173PAD~D @T173PAD~D @

3

UC1R

@

T128 PAD~D

@

T132 PAD~D

@

T134 PAD~D

@

T135 PAD~D

@

T138 PAD~D

@

T140 PAD~D

@

T143 PAD~D

RSVD_AT2 RSVD_AU44 RSVD_AV44 RSVD_D15

RSVD_F22 RSVD_H22 RSVD_J21

AU44 AV44

AT2

RSVD RSVD RSVD

D15

RSVD

F22

RSVD

H22

RSVD

J21

RSVD

2

HASWELL_MCP_E

18 OF 19

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

Rev1p2

N23 R23 T23 U10

AL1 AM11 AP7 AU10 AU15 AW14 AY14

RSVD_N23 RSVD_R23 RSVD_T23 RSVD_U10

RSVD_AL1 RSVD_AM11 RSVD_AP7 RSVD_AU10 RSVD_AU15 RSVD_AW14 RSVD_AY14

1

@

T129PAD~D@T129PAD~D

@

T130PAD~D@T130PAD~D

@

T131PAD~D@T131PAD~D

@

T133PAD~D@T133PAD~D

@

T136PAD~D@T136PAD~D

@

T137PAD~D@T137PAD~D

@

T139PAD~D@T139PAD~D

@

T141PAD~D@T141PAD~D

@

T142PAD~D@T142PAD~D

@

T144PAD~D@T144PAD~D

@

T145PAD~D@T145PAD~D

AC60

12

CFG_RCOMP

TDI_IREF

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

CFG_RCOMP

TDI_IREF

AC62 AC63 AA63 AA60

AA62

AA61

Y62 Y61 Y60 V62 V61 V60 U60 T63 T62 T61 T60

U63

U62

V63

A5

E1 D1

J20 H18 B12

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

CFG_RCOMP

RSVD

RSVD RSVD RSVD RSVD TD_IREF

RESERVED

19 OF 19

PROC_OPI_RCOMP

4

CFG0<6> CFG1<6> CFG2<6> CFG3<6> CFG4<6> CFG5<6> CFG6<6> CFG7<6> CFG8<6> CFG9<6> CFG10<6> CFG11<6> CFG12<6>

B B

A A

CFG13<6> CFG14<6> CFG15<6>

CFG16<6> CFG18<6> CFG17<6> CFG19<6>

T159PAD~D@T159PAD~D@

T161PAD~D@T161PAD~D@ T163PAD~D@T163PAD~D@ T164PAD~D@T164PAD~D@ T165PAD~D@T165PAD~D@

RC132 49.9_0402_1%RC132 49.9_0402_1%

1 2

RC133 8.2K_0402_1%RC133 8.2K_0402_1%

5

RSVD_TP RSVD_TP

RSVD

RSVD_TP RSVD_TP

RSVD_TP

RSVD

RSVD RSVD

Rev1p2

VSS VSS

AV63 AU63

C63 C62 B43

A51 B51

L60

N60

W23 Y22 AY15

PROC_OPI_RCOMP

AV62 D58

P22 N21

P20 R20

PROC_OPI_RCOMP

1 2

RC13449.9_0402_1% RC13449.9_0402_1%

T146PAD~D @T146PAD~D @ T147PAD~D @T147PAD~D @

T148PAD~D @T148PAD~D @ T149PAD~D @T149PAD~D @ T150PAD~D @T150PAD~D @

T151PAD~D @T151PAD~D @ T152PAD~D @T152PAD~D @

T153PAD~D @T153PAD~D @

T154PAD~D @T154PAD~D @

T155PAD~D @T155PAD~D @ T156PAD~D @T156PAD~D @

T157PAD~D @T157PAD~D @ T158PAD~D @T158PAD~D @

T160PAD~D @T160PAD~D @ T162PAD~D @T162PAD~D @

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

CFG STRAPS for CPU

CFG4

12

RC138

RC138 1K_0402_1%

1K_0402_1%

Display Port Presence Strap

1: Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port 0: Enabled; An external Display Port device is connected to the Embedded Display Port

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

MCP(17,18,19/19) CFG,RSVD

LA-9984P

1

16 57Wednesday, May 22, 2013

1.0

5

4

3

2

1

+DIMM1_VREF_DQ

1U_0402_6.3V6K

1

CD11

CD10

2

330U_D3_2.5VY_R6M

1

CD15

+

2

RD6 10K_0402_5%RD6 10K_0402_5%

RD7 10K_0402_5%RD7 10K_0402_5%

1 2

@

RD1

RD1 0_0402_1%

0_0402_1%

1 2

DDR_CKE0_DIMMA<7>

DDR_CS1_DIMMA#<7>

+3VS

2.2U_0402_6.3V6M

0.1U_0402_10V7K

DDR_A_D13

CD1

1

2

DDR_A_BS2<7>

M_CLK_DDR0<7> M_CLK_DDR#0<7>

DDR_A_BS0<7>

DDR_A_WE#<7> DDR_A_CAS#<7>

2.2U_0402_6.3V6M

1

2

DDR_A_D8

CD2

1

DDR_A_D14

2

DDR_A_D10

DDR_A_D29 DDR_A_D28 DDR_A_D24

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDR_A_D41

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D43 DDR_A_D47

DDR_A_D51 DDR_A_D50

DDR_A_D49 DDR_A_D48

DDR_CKE0_DIMMA DDR_CKE1_DIMMA

DDR_A_BS2

DDR_A_MA3

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10

DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D0 DDR_A_D1

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D2 DDR_A_D6

DDR_A_D21 DDR_A_D20

DDR_A_D17 DDR_A_D16

DDR_A_D36 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D38

DDR_A_D62 DDR_A_D58

DDR_A_D60 DDR_A_D61

0.1U_0402_10V7K

1

@

CD31

CD30

+0.675VS

2

D D

Populate RD1, De-Populate RD7 for Intel DDR3 VREFDQ multiple methods M1 Populate RD7, De-Populate RD1 for Intel DDR3 VREFDQ multiple methods M3

DDR_A_DQS#[0..7]<7>

DDR_A_D[0..63]<7>

DDR_A_DQS[0..7]<7>

DDR_A_MA[0..15]<7>

Layout Note: Place near JDIMM1

+SM_VREF_DQ0_DIMM1

All VREF traces should have 10 mil trace width

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

+1.35V

1U_0402_6.3V6K

C C

B B

1

CD4

2

+1.35V

10U_0603_6.3V6M

CD16

1

2

Layout Note: Place near JDIMM1.203,204

+0.675VS

0.1U_0402_10V7K

1

2

1

CD6

CD5

2

10U_0603_6.3V6M

@

CD17

1

2

CD24

CD18

CD12

1

2

0.1U_0402_10V7K

CD26

CD25

1

2

1U_0402_6.3V6K

1

CD7

2

10U_0603_6.3V6M

@

CD19

1

2

0.1U_0402_10V7K

CD27

1

2

1U_0402_6.3V6K

1

CD8

2

10U_0603_6.3V6M

CD20

1

2

10U_0603_6.3V6M

1

2

1

CD9

2

10U_0603_6.3V6M

CD14

CD13

1

2

10U_0603_6.3V6M

CD28

CD29

1

2

H=4mm

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1 VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9 VSS925VSS10 DQS#127DM1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16 DQS#245DM2 DQS247VSS17 VSS1849DQ22

51

DQ18 DQ1953VSS19 VSS2055DQ28

57

DQ24 DQ2559VSS21 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3 A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4406-0102

CONN@

VSS3

DQS0

VSS6

VSS8 DQ12 DQ13

DQ14 DQ15

DQ20 DQ21

DQ23

DQ29

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

+1.35V+1.35V

2 4

DQ4

6

DQ5

8 10 12 14 16

DQ6

18

DQ7

20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

80

A14

82 84 86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102

CK1

104 106 108

BA1

110 112 114

S0#

116 118 120 122

NC2

124 126 128 130 132 134 136

DM4

138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170

DM6

172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

SDA

202

SCL

204

206

G2

2-3A to 1 DIMMs/channel

DDR_A_D9 DDR_A_D12

DDR_A_DQS#1

DDR_A_DQS1

DDR_A_D15 DDR_A_D11

DDR_A_D25

DDR3_DRAMRST#

DDR_A_D27 DDR_A_D26

DDR_A_D45DDR_A_D44 DDR_A_D40

DDR_A_D42 DDR_A_D46

DDR_A_D52 DDR_A_D53

DDR_A_DQS#6

DDR_A_DQS6

DDR_A_D54 DDR_A_D55

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11DDR_A_MA12 DDR_A_MA7DDR_A_MA9

DDR_A_MA6DDR_A_MA8 DDR_A_MA4DDR_A_MA5

DDR_A_MA2 DDR_A_MA0DDR_A_MA1

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA# M_ODT0

M_ODT1

DDR_A_D5 DDR_A_D4

DDR_A_D3 DDR_A_D7

DDR_A_D18 DDR_A_D19

DDR_A_DQS#2

DDR_A_DQS2

DDR_A_D22 DDR_A_D23

DDR_A_D37 DDR_A_D32

DDR_A_D35 DDR_A_D39

DDR_A_D63 DDR_A_D59

DDR_A_DQS#7

DDR_A_DQS7

DDR_A_D56 DDR_A_D57

+0.675VS

ESD@

1

CD3

0.1U_0402_10V7K

2

CAD NOTE PLACE THE CAP NEAR TO DIMM RESET PIN

DDR_CKE1_DIMMA <7>

M_CLK_DDR1 <7> M_CLK_DDR#1 <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7>

2.2U_0402_6.3V6M

0.1U_0402_10V7K

CD21

1

2

+SM_VREF_CA_DIMM

1 2

@

RD4

RD4 CD22

CD22

0_0402_1%

DDR_PG_CTRL<6>

DDR_XDP_WLAN_TP_SMBDAT <18,19,26,27,6,9> DDR_XDP_WLAN_TP_SMBCLK <18,19,26,27,6,9>

+1.35V

12

RD3

RD3 470_0402_5%

470_0402_5%

R2347

R2347 220K_0402_5%~D

220K_0402_5%~D

@

R2351

R2351 2M_0402_5%

2M_0402_5%

2

3

1 2

@

RD5

RD5 0_0402_1%

0_0402_1%

QD2

QD2 BSS138-G_SOT23-3

BSS138-G_SOT23-3

1 3

D

S

D

S

G

2

0.675V_DDR_VTT_ON

U2303

NC1VCC

A

Y

GND

74AUP1G07GW_TSSOP5

5

4

M_ODT

1 2

R2348 66.5_0402_1%R2348 66.5_0402_1%

1 2

R2349 66.5_0402_1%R2349 66.5_0402_1%

1 2

R2350 66.5_0402_1%R2350 66.5_0402_1%

1 2

R2352 66.5_0402_1%R2352 66.5_0402_1%

+1.35V

@

CD23

0.1U_0402_10V7K

1 2

0.675V_DDR_VTT_ON

M_ODT

Place CC31 between QD2 and R2349

M_ODT0

M_ODT1

0.675V_DDR_VTT_ON <41>

DDR3_DRAMRST#<18> DDR3_DRAMRST#_CPU <6>

DDR3L SODIMM ODT GENERATION

+5VALW +1.35V

12

1 2

CD64

ESD@CD64

ESD@

0.1U_0402_10V7K

M_ODT2 <18>

M_ODT3 <18>

1

2

A A

+3VS

5

+1.35V

CD62

1 2

22U_0603_6.3V6M

ESD@

ESD solution

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMA

LA-9984P

1

17 57Wednesday, May 22, 2013

1.0

5

4

3

2

1

+DIMM2_VREF_DQ

+SM_VREF_DQ1_DIMM2

D D

Populate RD4, De-Populate RD8 for Intel DDR3 VREFDQ multiple methods M1 Populate RD8, De-Populate RD4 for Intel DDR3 VREFDQ multiple methods M3

DDR_B_DQS#[0..7]<7>

DDR_B_D[0..63]<7>

DDR_B_DQS[0..7]<7>

DDR_B_MA[0..15]<7>

Layout Note: Place near JDIMM2

All VREF traces should have 10 mil trace width

Note: Check voltage tolerance of

1 2

@

RD8

RD8 0_0402_1%

0_0402_1%

0.1U_0402_10V7K

2.2U_0402_6.3V6M

CD33

CD32

1

2

VREF_DQ at the DIMM socket

+1.35V

1U_0402_6.3V6K

1

CD35

C C

B B

CD35

2

+1.35V

10U_0603_6.3V6M

@

CD44

CD43

1

2

Layout Note: Place near JDIMM2.203,204

+0.675VS

0.1U_0402_10V7K

CD54

1

2

1U_0402_6.3V6K

1

CD37

CD36

2

10U_0603_6.3V6M

@

CD46

CD45

1

2

1

2

0.1U_0402_10V7K

CD56

CD55

1

2

1U_0402_6.3V6K

1

CD38

2

10U_0603_6.3V6M

CD47

1

2

0.1U_0402_10V7K

CD57

1

2

1U_0402_6.3V6K

1

CD39

CD40

2

10U_0603_6.3V6M

CD49

CD50

CD48

CD50

1

2

10U_0603_6.3V6M

CD58

CD59

1

2

1U_0402_6.3V6K

1

CD42

CD41

2

330U_D3_2.5VY_R6M

1

CD51

+

2

+3VS

RD12 10K_0402_5%RD12 10K_0402_5%

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7> M_CLK_DDR#2<7>

DDR_B_BS0<7>

DDR_B_WE#<7> DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

+3VS

12

10K_0402_5%

12

RD13

+1.35V +1.35V

DDR_B_D8 DDR_B_D14

DDR_B_D10 DDR_B_D11

DDR_B_D28 DDR_B_D29

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D26 DDR_B_D27

DDR_B_D40 DDR_B_D41

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D42

DDR_B_D56 DDR_B_D57

DDR_B_D59 DDR_B_D58

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

M_CLK_DDR2 M_CLK_DDR#2

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13 DDR_CS3_DIMMB#

DDR_B_D4 DDR_B_D1

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D3 DDR_B_D7

DDR_B_D21 DDR_B_D20

DDR_B_D22 DDR_B_D23

DDR_B_D36 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D35 DDR_B_D39

DDR_B_D52 DDR_B_D49

DDR_B_D48 DDR_B_D53

+0.675VS +0.675VS

0.1U_0402_10V7K

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M CD61

CD61

1

@

CD60

2

H=4mm

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1 VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9 VSS925VSS10 DQS#127DM1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16 DQS#245DM2 DQS247VSS17 VSS1849DQ22

51

DQ18 DQ1953VSS19 VSS2055DQ28

57

DQ24 DQ2559VSS21 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0 VDD175VDD2

77

NC1

79

BA2 VDD381VDD4 A12/BC#83A11

85

A9 VDD587VDD6

89

A8

91

A5 VDD793VDD8

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4406-0102

CONN@

VSS3

DQS0

VSS6

VSS8 DQ12 DQ13

DQ14 DQ15

DQ20 DQ21

DQ23

DQ29

DQS3

DQ30 DQ31

CKE1

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

2 4

DQ4

6

DQ5

8 10 12 14 16

DQ6

18

DQ7

20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

80

A14

82 84 86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102

CK1

104 106 108

BA1

110 112 114

S0#

116 118 120 122

NC2

124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

SDA

202

SCL

204

206

G2

2-3A to 1 DIMMs/channel

DDR_B_D12 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D13 DDR_B_D15

DDR_B_D25 DDR_B_D24

DDR3_DRAMRST#

DDR_B_D30 DDR_B_D31

DDR_B_D45 DDR_B_D44

DDR_B_D47 DDR_B_D43

DDR_B_D61 DDR_B_D60

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D63 DDR_B_D62

DDR_CKE3_DIMMB

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

M_CLK_DDR3 M_CLK_DDR#3

DDR_B_BS1 DDR_B_RAS#

DDR_CS2_DIMMB# M_ODT2

M_ODT3

DDR_B_D5 DDR_B_D0

DDR_B_D2 DDR_B_D6

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D19 DDR_B_D18

DDR_B_D37 DDR_B_D32

DDR_B_D34 DDR_B_D38

DDR_B_D51 DDR_B_D55

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D54 DDR_B_D50

1

2

CAD NOTE PLACE THE CAP NEAR TO DIMM RESET PIN

DDR3_DRAMRST# <17>

ESD@

CD34

0.1U_0402_10V7K

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7> M_CLK_DDR#3 <7>

DDR_B_BS1 <7> DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7> M_ODT2 <17>

M_ODT3 <17>

2.2U_0402_6.3V6M

1

CD52

2

DDR_XDP_WLAN_TP_SMBDAT <17,19,26,27,6,9> DDR_XDP_WLAN_TP_SMBCLK <17,19,26,27,6,9>

+SM_VREF_CA_DIMM

1 2

0.1U_0402_10V7K

@

RD10

RD10 0_0402_1%

0_0402_1%

CD53

1

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMB

LA-9984P

1

18 57Wednesday, May 22, 2013

1.0

5

4

3

2

1

+AVCC33 +DVCC33

0.1U_0402_10V7K

10U_0603_6.3V6M

CX35

D D

1

LVDS@CX35

LVDS@

2

0.1U_0402_10V7K

CX33

CX31

1

LVDS@CX33

LVDS@

LVDS@CX31

LVDS@

2

0.1U_0402_10V7K

10U_0603_6.3V6M

CX45

1

LVDS@CX45

LVDS@

2

22U_0805_6.3V6M

CX41

1

LVDS@CX41

LVDS@

2

0.1U_0402_10V7K

CX36

LVDS@CX36

LVDS@

CX34

CX40

1

LVDS@CX34

LVDS@

LVDS@CX40

LVDS@

2

1 2

Close to 18 pin Close to 22 pinClose to 5 pin

+3VS_RT+3VS_RT

12

@

RX168

4.7K_0402_5%

12

RX170

4.7K_0402_5%

C C

RX30

100K_0402_5%

@

RX25

100K_0402_5%

@

B B

4.7K_0402_5%

LVDS@

+3VS_RT

12

EDP_CPU_AUX# EDP_CPU_AUX

12

AUX termination

RX169

4.7K_0402_5%

LVDS@

@

RX171

4.7K_0402_5%

EDP_CPU_HPD

EDP_BIA_PWM

12

RX35

@ RX35

@

100K_0402_5%

RX36

@ RX36

@

100K_0402_5%

EEPROMEEPROM

MIIC_SCLMIIC_SDA

+3VS_RT

ROMLESSROMLESS

EDP_CPU_LANE_P0<6> EDP_CPU_LANE_N0<6>

EDP_CPU_LANE_P1<6> EDP_CPU_LANE_N1<6>

EDP_CPU_AUX<6> EDP_CPU_AUX#<6>

12

DDR_XDP_WLAN_TP_SMBCLK<17,18,26,27,6,9> DDR_XDP_WLAN_TP_SMBDAT<17,18,26,27,6,9>

EDP_CPU_LANE_P0 EDP_CPU_LANE_N0

EDP_CPU_LANE_P1 EDP_CPU_LANE_N1

EDP_CPU_AUX EDP_CPU_AUX#

DDR_XDP_WLAN_TP_SMBCLK DDR_XDP_WLAN_TP_SMBDAT

+3VS_RT+3VS +SWR_V12

30mil30mil

@

RX4

RX4 0_0805_1%

0_0805_1%

LX7

LVDS@ LX7

LVDS@

FBMA-L11-201209-221LMA30T_0805

LX8

LVDS@ LX8

LVDS@

FBMA-L11-201209-221LMA30T_0805

+SWR_V12

CX42 0.1U_0402_10V7KCX42 0.1U_0402_10V7K CX46 0.1U_0402_10V7KCX46 0.1U_0402_10V7K

CX38 0.1U_0402_10V7KCX38 0.1U_0402_10V7K CX39 0.1U_0402_10V7KCX39 0.1U_0402_10V7K

CX43 0.1U_0402_10V7KCX43 0.1U_0402_10V7K CX44 0.1U_0402_10V7KCX44 0.1U_0402_10V7K

FBMA-L11-201209-221LMA30T_0805

LX9

LVDS@ LX9

LVDS@

4.7UH_PG031B-4R7MS_1.1A_20%

1 2 1 2

EDP_CPU_HPD<10>

EDP_BIA_PWM<10,6>

RX5 12K_0402_1%

RX6 0_0402_5%@RX6 0_0402_5%@ RX31 0_0402_5%@RX31 0_0402_5%@

1 2

LVDS@

1 2 1 2

12

+DVCC33

12

+AVCC33

+SW_LX

EDP_CPU_HPD

EDP_BIA_PWM

0.1U_0402_10V7K

22U_0805_6.3V6M

CX48

1

LVDS@CX48

LVDS@

2

Close to 15 pin

+DVCC33

40 mils

60 mils

CPU_EDP_P0_C CPU_EDP_N0_C

CPU_EDP_P1_C CPU_EDP_N1_C

CPU_EDP_AUX_C CPU_EDP_AUX#_C

MIIC_SCL MIIC_SDA

CSCL CSDA

+SWR_V12

0.1U_0402_10V7K

CX37

1

2

CX47

1

LVDS@CX37

LVDS@

LVDS@CX47

LVDS@

2

Close to 11 pin Close to 43 pin

UX4

LVDS@

UX4

LVDS@

RTD2136R

22

PVCC

18

SWR_VDD

5

DP_V33

17

SWR_LX

15

SWR_VCCK

43

VCCK

11

DP_V12

7

LANE0P

8

LANE0N

9

LANE1P

10

LANE1N

4

AUX-CH_P

3

AUX-CH_N

1

DP_HPD

21

PWMIN

2

TESTMODE

12

DP_REXT

48

MODE_CFG1

47

MODE_CFG0

13

CIICSCL1

14

CIICSDA1

RTD2136R-CG_QFN48_6x6

0.1U_0402_10V7K

0.1U_0402_10V7K CX32

1

LVDS@CX32

LVDS@

2

35 36

41 42

39 40

37 38

33 34

25 26

31 32

29 30

27 28

23 24

46 45

20 19 44

6

16

49

LVDS_ACLK+ LVDS_ACLK-

LVDS_A0+ LVDS_A0-

LVDS_A1+ LVDS_A1-

LVDS_A2+ LVDS_A2-

LVDS_BCLK+ LVDS_BCLK-

LVDS_B0+ LVDS_B0-

LVDS_B1+ LVDS_B1-

LVDS_B2+ LVDS_B2-

EDID_CLK EDID_DATA

TL_ENVDD TL_INVT_PWM TL_BKOFF#_R

TXOC+

TXOC-

TXO0+

PWR

PWR DP

TXO0-

TXO1+

TXO1-

TXO2+

TXO2-

TXO3+

TXO3-

TXEC+

TXEC-

TXE0+

TXE0-

LVDSGND

DP

TXE1+

TXE1-

TXE2+

TXE2-

TXE3+

TXE3-

MIICSCL1

OTHERS

MIICSDA1

PANEL_VCC

PWMOUT

BL_EN

DP_GND

GND

PAD

LVDS_ACLK+ <31> LVDS_ACLK- <31>

LVDS_A0+ <31> LVDS_A0- <31>

LVDS_A1+ <31> LVDS_A1- <31>

LVDS_A2+ <31> LVDS_A2- <31>

LVDS_BCLK+ <31> LVDS_BCLK- <31>

LVDS_B0+ <31> LVDS_B0- <31>

LVDS_B1+ <31> LVDS_B1- <31>

LVDS_B2+ <31> LVDS_B2- <31>

EDID_CLK <31> EDID_DATA <31>

TL_ENVDD <31> TL_INVT_PWM <31>

12

RX33

LVDS@RX33

LVDS@

100K_0402_5%

RTD2136S : SA00004NW10 RTD2136R : SA000067100

+3VS_RT

QX6B

2

LVDS@

G

61

S

D

S

5

D

QX6A

DMN66D0LDW-7_SOT363-6

CSCL

A A

EC_SMB_DA2CSDA

5

34

EC_SMB_CK2

SGD

LVDS@

EC_SMB_DA2 <30,49,9>

EC_SMB_CK2 <30,49,9>

EDID_CLK EDID_DATA

CSDA CSCL

1 8 2 7 3 6 4 5

4

RP56

LVDS@RP56

LVDS@

2.2K_8P4R_5%

RP57

@RP57

@

2.2K_8P4R_5%

+DVCC33

Vendor advise reserve it

+3VS_RT

BKOFF#<30>

TL_BKOFF#_R

3

CX10

LVDS@CX10

LVDS@

0.1U_0402_10V7K

1 2

5

1

VCC

IN1

4

OUT

2

IN2

GND

UX2

LVDS@UX2

LVDS@

MC74VHC1G08DFT2G_SC70-5

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

TL_BKOFF# <31>

2013/05/17 2014/06/01

CPU_EDP_AUX#_C

CPU_EDP_AUX_C

CPU_EDP_P0_C EDP_P0 LVDS_B1-

CPU_EDP_N0_C

CPU_EDP_P1_C

CPU_EDP_N1_C EDP_N1 LVDS_B2+

ENVDD_PCH<10,30>

Compal Secret Data

Deciphered Date

2

1 2

RX37 0_0402_5%eDP@RX37 0_0402_5%eDP@

1 2

RX39 0_0402_5%eDP@RX39 0_0402_5%eDP@

1 2

RX41 0_0402_5%eDP@RX41 0_0402_5%eDP@

1 2

RX43 0_0402_5%eDP@RX43 0_0402_5%eDP@

1 2

RX45 0_0402_5%eDP@RX45 0_0402_5%eDP@

1 2

RX47 0_0402_5%eDP@RX47 0_0402_5%eDP@

EDP_BIA_PWM TL_INVT_PWM

ENVDD_PCH

EDP_CPU_HPD

EDP_AUX#

EDP_AUX

EDP_N0 LVDS_B1+

EDP_P1 LVDS_B2-

1 2

RX49 0_0402_5%eDP@RX49 0_0402_5%eDP@

1 2

RX50 0_0402_5%eDP@RX50 0_0402_5%eDP@

1 2

RX51 0_0402_5%eDP@RX51 0_0402_5%eDP@

1 2

RX52 0_0402_5%eDP@RX52 0_0402_5%eDP@

RX38 0_0402_5%eDP@RX38 0_0402_5%eDP@

RX40 0_0402_5%eDP@RX40 0_0402_5%eDP@

RX42 0_0402_5%eDP@RX42 0_0402_5%eDP@

RX44 0_0402_5%eDP@RX44 0_0402_5%eDP@

RX46 0_0402_5%eDP@RX46 0_0402_5%eDP@

RX48 0_0402_5%eDP@RX48 0_0402_5%eDP@

Across to UX4.19 & UX4.21

Close to UX2

Close to UX4

Title

eDP to LVDS converter

Size Document Number Rev

LA-9984P

Date: Sheet of

1 2

TL_BKOFF#BKOFF#

TL_ENVDD

EDP_HPD_PANEL

LVDS_B0-

LVDS_B0+

for layout smoothly, will swap NET on cable

EDP_HPD_PANEL <31>

For eDP co-layout

Compal Electronics, Inc.

1

1.0

19 57Wednesday, May 22, 2013

1.0

5

4

3

2

1

D D

12

DDI1_LANE_N3<6> DDI1_LANE_P3<6>

DDI1_LANE_N2<6> DDI1_LANE_P2<6>

DDI1_LANE_N1<6> DDI1_LANE_P1<6>

DDI1_LANE_N0<6> DDI1_LANE_P0<6>

C C

B B

CX12 0.1U_0402_10V7KCX12 0.1U_0402_10V7K CX13 0.1U_0402_10V7KCX13 0.1U_0402_10V7K

CX14 0.1U_0402_10V7KCX14 0.1U_0402_10V7K CX15 0.1U_0402_10V7KCX15 0.1U_0402_10V7K

CX16 0.1U_0402_10V7KCX16 0.1U_0402_10V7K CX17 0.1U_0402_10V7KCX17 0.1U_0402_10V7K

CX18 0.1U_0402_10V7KCX18 0.1U_0402_10V7K CX19 0.1U_0402_10V7KCX19 0.1U_0402_10V7K

CPU_DPB_CTRLCLK<10>

CPU_DPB_CTRLDAT<10>

12

12 12

TMDS_TXCN TMDS_TXCP

TMDS_TX0N TMDS_TX0P

TMDS_TX1N TMDS_TX1P

TMDS_TX2N TMDS_TX2P

+3VS

S

5

34

SGD

QX4A

DMN66D0LDW-7_SOT363-6

RP59

680_8P4R_5%

100K_0402_5%

QX4B

2

DMN66D0LDW-7_SOT363-6

G

61

CPU_DPB_CTRLCLK_R

D

CPU_DPB_CTRLDAT_R

182736

RX13

45

+3VS

12

45

2

G

2.2K_0402_5%

182736

RP58

RP58 680_8P4R_5%

680_8P4R_5%

13

D

QX3

QX3 2N7002K_SOT23-3

2N7002K_SOT23-3

S

+5VS

RX16

RX17

2.2K_0402_5%

1 2

Place close to JHDMI1

WCM-2012HS-900T_4P

TMDS_TXCN TMDS_L_TXCN

TMDS_TXCP

TMDS_TX0N

TMDS_TX0P

TMDS_TX1N

TMDS_TX1P

TMDS_TX2P TMDS_L_TX2P

TMDS_TX2N

1

4

LX2

WCM-2012HS-900T_4P

1

4

LX3

WCM-2012HS-900T_4P

1

4

LX4

LX5

4

1

WCM-2012HS-900T_4P

EMI@LX2

EMI@

EMI@LX3

EMI@

EMI@LX4

EMI@

EMI@LX5

EMI@

2

3

TMDS_L_TXCP

3

2

TMDS_L_TX0N

2

3

TMDS_L_TX0P

3

2

TMDS_L_TX1N

2

3

TMDS_L_TX1P

3

2

TMDS_L_TX2N

2

TMDS_L_TXCN

TMDS_L_TXCP

TMDS_L_TX0N

TMDS_L_TX0P

TMDS_L_TX1N

TMDS_L_TX1P

TMDS_L_TX2N

TMDS_L_TX2P

DPB_HPD<10>

W=40mils

+5VS

CX23 3.3P_0402_50V8C@EMI@ CX23 3.3P_0402_50V8C@EMI@

CX24 3.3P_0402_50V8C@EMI@ CX24 3.3P_0402_50V8C@EMI@

CX25 3.3P_0402_50V8C@EMI@ CX25 3.3P_0402_50V8C@EMI@

CX26 3.3P_0402_50V8C@EMI@ CX26 3.3P_0402_50V8C@EMI@

CX27 3.3P_0402_50V8C@EMI@ CX27 3.3P_0402_50V8C@EMI@

CX28 3.3P_0402_50V8C@EMI@ CX28 3.3P_0402_50V8C@EMI@

CX29 3.3P_0402_50V8C@EMI@ CX29 3.3P_0402_50V8C@EMI@

CX30 3.3P_0402_50V8C@EMI@ CX30 3.3P_0402_50V8C@EMI@

QX5

MMBT3904_NL_SOT23-3

QX5

FX1

1.5A_6V_1206L150PR~D

HDMI_HPLUG

CPU_DPB_CTRLDAT_R CPU_DPB_CTRLCLK_R

TMDS_L_TXCN

TMDS_L_TXCP TMDS_L_TX0N

TMDS_L_TX0P TMDS_L_TX1N

TMDS_L_TX1P TMDS_L_TX2N

TMDS_L_TX2P

1 2

+3VS

C

2

B

E

3 1

12

RX14

RX14 100K_0402_5%

100K_0402_5%

12

1 2

RX15

RX15 150K_0402_5%

150K_0402_5%

+3VS

12

RX12

RX12 10K_0402_5%

10K_0402_5%

HDMI_HPLUG

1

2

JHDMI

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

LOTES_ABA-HDM-022-K01

CONN@

CX20

CX20 220P_0402_50V8J

220P_0402_50V8J

1

2

0.1U_0402_16V7K

GND GND GND GND

12

+VDISPLAY_VCC

CX21

10U_0603_6.3V6M

20 21 22 23

@

RX34

RX34 20K_0402_5%

20K_0402_5%

1

CX22

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

HDMI

Size Document Number Rev

LA-9984P

Date: Sheet of

1

20 57Wednesday, May 22, 2013

1.0

5

4

3

2

1

W=40mils

JP3

@JP3

@

2 1

2MM

+3VALW

D D

1U_0402 _6.3V6K

WOL_E N<3 0>

C C

PCIE_PRX _LANTX_P3<12> PCIE_PRX _LANTX_N3<12 >

PCIE_PTX_ LANRX_P3<12> PCIE_PTX_ LANRX_N3<12 >

+LAN_IO

1 2

RL34

RL34 10K_040 2_5%

B B

10K_040 2_5%

1

CL39

1

@

CL38

0.1U_060 3_25V7K

2

APL3512 PIN 4 tire to VIN

WOL_E N

CL30, CL31 close to UL1 Pin 17, 18

1 2

CL30 0.1 U_0402_10 V7KCL30 0.1U_0402_1 0V7K

1 2

CL31 0.1 U_0402_10 V7KCL31 0.1U_0402_1 0V7K

PCIE_PTX_ LANRX_P3 PCIE_PTX_ LANRX_N3

PLT_RST#<10,2 6,30,48,6>

PCIE_W AKE#<10,30>

PCIE_W AKE# XTLO

2MM

UL2

5

VIN

4

SS

APL3512 ABI-TRG_SOT23-5

RL27

RL27 100K_04 02_5%

100K_04 02_5%

1 2

PCIE_PRX _LANTX_N3_C

ISOLATEB

PCIE_W AKE#

T96PAD~D @T96PAD~D @

VOUT

GND

EN

1

2

3

UL1

17

HSOP

18

HSON

13

HSIP

14

HSIN

19

PERSTB

20

ISOLATEB

21

LANWAKEB

26

GPO

3

NC

6

NC

7

NC

9

NC

10

NC

11

NC

22

NC

24

NC

RTL8106E-CG _QFN32_4X 4

W=40mils

SS table

Css

0.1uF

10nF

1nF

Open or tied to VIN

1

MDIP0

4

MDIP1

2

MDIN0

5

MDIN1

8

AVDD10

30

AVDD10

32

AVDD33

23

DVDD33

15

REFCLK_P

16

REFCLK_N

12

CLKREQB

28

CKXTAL1

29

CKXTAL2

27

LED0

25

LED1

31

RSET

33

GND

Tss

100mS

10mS

1mS

MDI0+PCIE_PRX _LANTX_P3_C MDI1+ MDI0MDI1-

XTLO XTLI

T94 PAD~D@ T94 P AD~D@ T95 PAD~D@ T95 P AD~D@

RL31 2. 49K_0402_ 1%RL3 1 2.49K_ 0402_1%

W=40mils

+LAN_IO

CL15

+LAN_IO rising time : >1ms and <100ms

1.5A

1

CL19

2

0.1U_0402_10V7K

These caps close to Pin 23,32 For 8106E pop the capacitor close pin 23,32

+LAN_VDD

1

CL20

1

CL22

2

0.1U_0402_10V7K

1

CL26

2

0.1U_0402_10V7K

These caps close to Pin 8,30 For 8106E pop capacitor close to pin 8,30

+LAN_VDD

+LAN_IO

CLK_PCIE _LAN <9> CLK_PCIE _LAN# <9>

LAN_CLKR EQ# <9 >

12

W=20mils

+LAN_VDD

For GCLK

CL36

1 2

10P_040 2_50V8J

XTAL@

CL37

1 2

10P_040 2_50V8J

XTAL@

RL19

RL19 75_0603 _5%

75_0603 _5%

1 2

MCT0

1 2

MCT1

RL20

RL20 75_0603 _5%

75_0603 _5%

Place close to TCT pin

MDI1MDI1+

MDI0MDI0+

2

CL41

0.01U_04 02_16V7K

1

XTLI<29>

XTLI

YL2

XTAL@YL2

XTAL@

1

2

OSC

GND

3

4

OSC

GND

25MHZ_10 PF_7V2500 0014

XTLI

1

EMI@

CL33

CL33 10P_120 6_2KV8J

10P_120 6_2KV8J

2

TL1

1 2 3 4 5 6 7

X'FORM_ NS0 014

Change CPN to SP050007J00 only Need CIS symbol

RD+ RDCT NC NC CT TD+ TD-8TX-

16

MDO1-

RX+

15

MDO1+

RX-

14

MCT0

CT

13

NC

12

NC

11

MCT1

CT

10

MDO0-

TX+

9

MDO0+

1

CL35

CL34

+3VS

12

RL33

RL33 1K_0402 _5%

1K_0402 _5%

ISOLATEB

RL35

RL35 15K_040 2_5%

15K_040 2_5%

1 2

A A

5

4

LAN_CLKR EQ#

WOL_E N

Reserve 10K pull LAN_IO

RL37 10K_ 0402_5%

RL38 10K_ 0402_5%

1 2

+LAN_IO

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2

1U_0402_6.3V6K

0.1U_0402_10V7K

2013/05/17 2014/06/01

MDO1-

MDO1+

MDO0-

MDO0+

Compal Secret Data

Deciphered Date

2

JLAN

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

SANTA_130 456-311

CONN@

9

SHLD1

10

SHLD2

Compal Electronics, Inc.

Title

Size Docum ent Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

LAN RTL8106E

LA-9984P

1

1.0

of

21 57Wednesday, May 22, 2013

5

4

3

2

1

Reserve for HDA issue

+3VS +CO DEC_AVDD2+1.5VS

CA71, CA51 place close to Pin 26

+5V_PVDD+5V_PVDD +5VA

CA55

4.7U_0603_6.3V6K

CA55

CA53, CA55 change Value

D D

C C

from 10U_0603_6.3V6M~D to

4.7U_0603_6.3V6K

+3VS

CA58

0.1U_0402_16V7K

CA58

0.1U_0402_16V7K

CA57,CA58 close to UA1 pin1

PCH_AZ_CODEC_BITCLK

4.7U_0603_6.3V6K

1

2

PCH_AZ_CODEC_SDIN0<8> PCH_AZ_CODEC_SDOUT<8> PCH_AZ_CODEC_BITCLK<8> PCH_AZ_CODEC_SYNC<8> PCH_AZ_CODEC_RST#<8>

@EMI@

R2355

R2355 0_0402_5%

0_0402_5%

1 2

CA57

0.1U_0402_16V7K

1

2

1

2

4.7U_0603_6.3V6K

1

CA56

2

+3VS

CA59

4.7U_0603_6.3V6K

1

@EMI@

CA21

CA21 22P_0402_50V8J

22P_0402_50V8J

2

1

2

CA53

4.7U_0603_6.3V6K

CA53

4.7U_0603_6.3V6K

1

CA54

0.1U_0402_16V7K

CA54

0.1U_0402_16V7K

1

2

1

2

+CODEC_AVDD2

1 2

RA130 22_0402_5%RA130 22_0402_5%

1 2

CA23 2.2U_0603_6.3V6KCA23 2.2U_0603_6.3V6K

1 2

RA153 20K_0402_1%RA153 20K_0402_1%

1 2

CA24 1U_0402_6.3V6KCA24 1U_0402_6.3V6K

1 2

CA25 1U_0402_6.3V6KCA25 1U_0402_6.3V6K

+MIC2-VREFO

1 2

CA62 10U_0603_6.3V6MCA62 10U_0603_6.3V6M

1 2

CA63 10U_0603_6.3V6MCA63 10U_0603_6.3V6M

1 2

CA64 10U_0603_6.3V6MCA64 10U_0603_6.3V6M

1

2

CA60

0.1U_0402_16V7K

4.7U_0603_6.3V6K

Line1-VREFO-L Line1-VREFO-R +MIC2-VREFO

CA51

0.1U_0402_16V7K

CA51

0.1U_0402_16V7K

CA61

CA71

4.7U_0603_6.3V6K

CA71

4.7U_0603_6.3V6K

1

2

1

2

+5VA

UA1

26

AVDD1

41

PVDD1

46

PVDD2

1

DVDD

36

CPVDD

9

DVDD-IO

40

AVDD2

8

SDATA-IN

5

SDATA-OUT

6

BCLK

10

SYNC

11

RESETB

28

VREF

15

JDREF

37

CBP

35

CBN

34

CPVEE

31

MIC1-VREFO-L

30

MIC1-VREFO-R

29

MIC2-VREFO

27

LDO1-CAP

39

LDO2-CAP

7

LDO3-CAP

4

DVSS

25

AVSS1

38

AVSS2

49

Thermal PAD

ALC3223-CG_MQFN48_6X6~D

1 2

RA8 0_0402_5%RA8 0_0402_5%

1 2

RA9 0_0402_5%@RA9 0_0402_5%@

12

RV54

0_0603_1%@

12

RV59

0_0603_1%@

12

PCBEEP

16

MONO-OUT

SENSE B SENSE A

SPK-OUT-R+

SPK-OUT-RSPK-OUT-LSPK-OUT-L+

24 23

22 21

20 19

18 17

14 13

45 44 43 42

33 32

48

2 3

47

PDB

LINE2-L(PORT-E-L )

LINE2-R(PORT-E-R )

LINE1-L(PORT-C- L)

LINE1-R(PORT-C- R)

MIC1-R(PORT-B-R)

MIC1-L(PORT-B-L)

MIC2-R(PORT-F-R)

MIC2-L(PORT-F-L)

HPOUT-R(PORT -I-R)

HPOUT-L(PORT -I-L)

SPDIF-OUT/GPIO2

GPIO0/DMIC-DATA

GPIO1/DMIC-CLK

+5VS+5V_PVDD

+5VS

0.1U_0402_16V7K

LINE1-L LINE1-R

MIC1-L

MIC_IN RING2

RA51 39.2K_0402_1%RA51 39.2K_0402_1%

INT-SPK-R+ INT-SPK-RINT-SPK-LINT-SPK-L+

HPOUT-R HPOUT-L

MIC_CLK_C

EC_MUTE#

LINE1-L

4.7U_0603_6.3V6K

LINE1-R

4.7U_0603_6.3V6K

1 2

CA65

CA74 10U_0603_6.3V6MCA74 10U_0603_6.3V6M

1 2

RA51, RA33 place close to UA1

MIC_DATA <31>

EC_MUTE# <30>

CA67

CA68

RA79

1K_0402_1%

CA69 100P_0402_50V8J@CA69 100P_0402_50V8J@

RA81 10K_0402_5%@RA81 10K_0402_5%@

1 2

JACK_SENSE#

RA165

4.7K_0402_5%

1 2

RA80 1K_0402_1%RA80 1K_0402_1%

1 2

RA82 1K_0402_1%RA82 1K_0402_1%

PC_BEEP

12

+MIC2-VREFO

Line1-VREFO-L Line1-VREFO-R

12

RA166

4.7K_0402_5%

Line-IN-L

Line-IN-R

RA53 2.2K_0402_5%RA53 2.2K_0402_5%

RA1109 2.2K_0402_5%RA1109 2.2K_0402_5%

12

MIC_IN

RING2

JACK_PLUG Delay circutis

+3VS +3VS

12

@

RA1

RA1 100K_0402_5%

100K_0402_5%

@

QA5B

JACK_PLUG#

DMN66D0LDW-7_SOT363-6

10U_0603_6.3V6M

JACK_PLUG#

1 2

@

RA3

RA3 10K_0402_5%

10K_0402_5%

RA4 0_0402_1%@RA4 0_0402_1%@

@

CA1

1 2

QA5B

1

2

1

2

Reserve for cancel Delay circutis

RA29 0_0603_1%@RA29 0_0603_1%@

RA30 0_0603_1%@RA30 0_0603_1%@

RA31 0_0603_1%@RA31 0_0603_1%@

RA32 0_0603_1%@RA32 0_0603_1%@

GNDA GND

Place on the moat between GND & GNDA.

12

@

RA2

RA2 100K_0402_5%

100K_0402_5%

61

D

G

S

@

CA2

CA2 10U_0603_6.3V6M

10U_0603_6.3V6M

1 2

JACK_SENSE#

34

D

G

5

QA5A

S

DMN66D0LDW-7_SOT363-6

@

JACK_SENSE#

LA1

EMI@LA1

EMI@

1 2

MIC_CLK_C

BLM15BB221SN1D_2P

+RTCVCC

12

RA5

RA5 470K_0402_5%

470K_0402_5%

B B

@

PCH_AZ_CODEC_RST#

+3VS

RA55

8.2_0402_1%

1 2

HPOUT-L AUD_HP_OUT_L_CN

1 2

HPOUT-R

8.2_0402_1%

8.2_0402_1% RA56

RA56

A A

1 2

RA6 10K_0402_5%

1 2

RA7 10K_0402_5%RA7 10K_0402_5%

Line-IN-L

Line-IN-R

RA84

10K_0402_5%

5

MIC_IN

RING2

12

QA6B

DMN66D0LDW-7_SOT363-6

LA7 FBMA-L10-160808-800LMT_2P

LA10 FBMA-L10-160808-800LMT_2P

LA8 FBMA-L10-160808-800LMT_2P

LA9 FBMA-L10-160808-800LMT_2P

12

RA83

RA83 10K_0402_5%

10K_0402_5%

61

D

G

2

S

EMI@

12

EMI@

12

EMI@

12

EMI@

12

5

iPhone and Nokia type Combo Jack

MIC_IN

34

D

G

QA6A

S

DMN66D0LDW-7_SOT363-6

40mil 40mil

CA39

100P_0402_50V8J

1

EMI@CA39

EMI@

2

4

MIC_IN_R

RING2_R

AUD_HP_OUT_R_CN

2

3

2

3

DA10

AZ5125-02S.R7G_SOT23-3

DA10

CA38

100P_0402_50V8J

CA33

100P_0402_50V8J

1

EMI@CA38

EMI@

EMI@CA33

EMI@

2

AZ5125-02S.R7G_SOT23-3

CA40

100P_0402_50V8J

EMI@CA40

EMI@

1

DA12

AZ5125-02S.R7G_SOT23-3

ESD@

DA12

AZ5125-02S.R7G_SOT23-3

ESD@

1

SM01000BV00 need CIS symbol

3

MIC_CLK

1

@EMI@

CA22

CA22 22P_0402_50V8J

22P_0402_50V8J

2

MIC_CLK <31>

EC Beep

MCU Beep

PC Beep

Close to UA1 Pin11,13,14,16

INT-SPK-RINT-SPK-R+ INT-SPK-LINT-SPK-L+

LA3 0_0603_5%EMI@ LA3 0_0603_5%EMI@ LA4 0_0603_5%EMI@ LA4 0_0603_5%EMI@ LA5 0_0603_5%EMI@ LA5 0_0603_5%EMI@ LA6 0_0603_5%EMI@ LA6 0_0603_5%EMI@

1 2 1 2 1 2 1 2

SPK_R1-_CONN SPK_R2+_CONN SPK_L1-_CONN SPK_L2+_CONN

Trace width for SPK-L+/SPK-L-/SPK-R+/SPK-RSpeaker 4 ohm : 40mil Speaker 8 ohm : 20mil

JHP

RING2_R AUD_HP_OUT_L_CN

JACK_PLUG#

AUD_HP_OUT_R_CN MIC_IN_R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3 1

5

6 2 4 7

SINGA_2SJ3080-000111F

CONN@

Compal Secret Data

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

close to Codec

1

CA29

2

EMI@ CA29

EMI@

1000P_0402_50V7K

DA8

1

2

1

CA32

2

EMI@ CA32

EMI@

1000P_0402_50V7K

2

1

3

BAT54C-7-F_SOT23-3

JSPK

1

2

3

4

E&T_3703-Q04N-11R

CONN@

1000P_0402_50V7K

Title

Size Document Number Rev

Date: Sheet of

PC_BEEP

12

@

RA19

RA19 10K_0402_5%

10K_0402_5%

5

GND

6

GND

Compal Electronics, Inc.

Audio Codec ALC3223

LA-9984P

1

1.0

22 57Wednesday, May 22, 2013

1.0

BEEP#<30>

HDA_SPKR<11>

1

CA30

CA31

2

EMI@ CA30

EMI@

EMI@ CA31

EMI@

1000P_0402_50V7K

5

D D

4

3

2

1

SD_CD# MS_INS#

22P_0402_50V8J

+VCC_3IN1+3VS

Trace width:40mil

4

5

UR1

EMI@

LR2

USB20_CR_P6<12>

USB20_CR_N6< 12>

C C

B B

USB20_CR_P6 USB20_CR_P6_R

4

1

WCM-2012HS-900T_4P

3

2

0.1U_0402_10V7K

USB20_CR_N6_RUSB20_CR_N6

+3VS

1

CR1

CR2

4.7U_0603_6.3V6K

2

RR1 6.19K_0402_1%RR1 6.19K_0402_1%

12

USB20_CR_N6_R USB20_CR_P6_R

2

CR3

1U_0402_6.3V6K

CR3

1U_0402_6.3V6K

1

2

CR4

1U_0402_6.3V6K

CR4

1U_0402_6.3V6K

1

RREF

UR1

1

RREF

2

DM

3

DP

RTS5179-GR_QFN24

7

XD_CD#

23

XD_D7

17

GPIO0

6

SDREG

24

V18

3V3_IN

CARD_3V3

Thermal pad

25

RTS5179-GR_QFN24_4X4

22

MS_BS

SP14

21

SP13 SP12 SP11 SP10

SP9 SP8

SP7 SP6 SP5 SP4 SP3 SP2 SP1

SD_D2

20

MS_D1_SD_D3

19 18

SD_CMD

16

MS_D0

15

MS_D2_SD_CLK_R MS_D2_SD_CLK

14 13

SD_CD#

12

MS_D3

11

SD_D0

10

SD_D1

9

MS_INS#

8

MS_CLK_SD_WP_R MS_CLK_SD_WPV18

1

2

22P_0402_50V8J

For EMI request. Place close to UR1

close to chip side

1 2

EMI@

RR2

RR2 22_0402_5%

22_0402_5%

1 2

EMI@

RR3

RR3 22_0402_5%

22_0402_5%

+VCC_3IN1

CR8

4.7U_0603_6.3V6K

CR9

1

2

1

EMI@CR9

EMI@

2

CR7

0.1U_0402_10V7K

22P_0402_50V8J

Close to JREAD

SD_CMD

22P_0402_50V8J

CR11

EMI@CR11

EMI@

1

2

CR10

5P_0402_50V8C

EMI@CR10

EMI@

CR5

EMI@

1

2

1

2

CR6

5P_0402_50V8C

EMI@

CR6

5P_0402_50V8C

EMI@

1

2

SD_D2

MS_D1_SD_D3

MS_CLK_SD_WP SD_CMD MS_D3 MS_INS#

MS_D2_SD_CLK

MS_D0 MS_D1_SD_D3 MS_D2_SD_CLK MS_BS

SD_D0 SD_D1 SD_CD#

MS_CLK_SD_WP

拉拉拉拉

MS_D2_SD_CLK

再再再再再再再再

Via

拉拉拉拉到到到到

拉拉拉拉

MS_CLK_SD_WP

再再再再再再再再

Via

拉拉拉拉到到到到

+VCC_3IN1

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

22

到到到到

pin 10 MS_D2

到到到到

pin 20 SD_W

JREAD

SD-DAT2 MS-VSS1 SD-CD/DAT3 MMC -RSV MS-VCC MS-SCLK SD-CMD MMC-C MD MS-DATA3 MS-INS SD-VSS MMC-VSS1 MS-DATA2 SD-VDD MMC-VDD MS-DATA0 MS-DATA1 SD-CLK MMC-CL K MS-BS MS-VSS2 SD-VSS MMC-VSS2 SD-DAT0 MMC-DAT SD-DAT1 SD-CD SD-GND21GND1 SD-WP(SW )

T-SOL_143-2300302602_RV

CONN@

GND2

Conn pin 13 SD_CLK

Conn pin 5 MS_CLK

23 24

For EMI request. Place close to JREAD

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Card Reader RTS5179

LA-9984P

1

23 57Wednesday, May 22, 2013

1.0

5

4

+5VALW

3

2

1

CI18

4.7U_0805_10V4Z

47U_0805_6.3V4Z

LI1

EMI@LI1

EMI@

D D

C C

B B

USB3TN1_JUSB2<12>

USB3TP1_JUSB2<12>

A A

USB3RN2_JUSB1<12>

USB3RP2_JUSB1< 12>

USB3TN2_JUSB1<12>

USB3TP2_JUSB1<12>

USB20_JUSB1_N1<12>

USB20_JUSB1_P1<12>

USB3RN1_JUSB2<12>

USB3RP1_JUSB2< 12>

USB3TP1_JUSB2

USB20_JUSB2_N0<12>

USB20_JUSB2_P0<12>

USB3RN2_JUSB1

USB3RP2_JUSB1

USB3TN2_JUSB1

CI3 0.1U_0402_10V7KCI3 0.1U_0402_10V7K

USB3TP2_JUSB1

CI4 0.1U_0402_10V7KCI4 0.1U_0402_10V7K

USB20_JUSB1_P1

12

USB3TN1_JUSB2_C

CI10 0.1U_0402_10V7KCI10 0.1U_0402_10V7K

12

USB3TP1_JUSB2_C USB3TP1_JUSB2_R

CI11 0.1U_0402_10V7KCI11 0.1U_0402_10V7K

USB20_JUSB2_P0

1 2

DLW21SN670HQ2L_4P

12

USB3TN2_JUSB1_C

12

USB3TP2_JUSB1_C USB3TP2_JUSB1_R

1

4

LI4

1 2

DLW21SN670HQ2L_4P

LI6

1 2

DLW21SN670HQ2L_4P

EMI@

LI5

1

4

WCM-2012HS-900T_4P

34

LI3

1 2

DLW21SN670HQ2L_4P

EMI@

LI2

1

2

3

4

WCM-2012HS-900T_4P

EMI@LI4

EMI@

34

EMI@LI6

EMI@

34

2

3

EMI@LI3

EMI@

2

3

USB20_JUSB2_N0_RUSB20_JUSB2_N0

USB20_JUSB2_P0_R

USB3RN2_JUSB1_R

USB3RP2_JUSB1_R

34

USB20_JUSB1_N1_RUSB20_JUSB1_N1

USB20_JUSB1_P1_R

USB3RN1_JUSB2_RUSB3RN1_JUSB2

USB3RP1_JUSB2_RUSB3RP1_JUSB2

USB3TN1_JUSB2_RUSB3TN1_JUSB2

47U_0805_6.3V4Z

USB3TN2_JUSB1_R

4.7U_0805_10V4Z

2

USB_EN#<25,30>

+5VALW

1

CI6

2

USB_EN# USB_OC0#

1

CI12

2

1

CI7

0.1U_0402_16V7K

2

1

CI26

0.1U_0402_16V7K

2

USB3RN1_JUSB2_R

USB3RP1_JUSB2_R

USB3TN1_JUSB2_R

USB3TP1_JUSB2_R

1

CI14

0.1U_0402_16V7K

2

1

CI13

0.1U_0402_16V7K

2

USB3RN2_JUSB1_R

USB3RP2_JUSB1_R

USB3TP2_JUSB1_R

2.0A

UI2

1

GND

2

VIN VIN3VOUT

4

EN

9

ESD@

DI4

1

2

4

5

3

8

IP4292CZ10-TBR_XSON10_2.5X1~D

2.0A

UI3

1

GND

2

VIN VIN3VOUT

4

EN

ESD@

DI1

1

2

4

5

3

8

IP4292CZ10-TBR_XSON10_2.5X1~D

+5V_USB_PWR2

8

VOUT

7

VOUT

6 5

FLG

EPAD

AP2301MPG-13_MSOP8

8

VOUT

7

VOUT

6 5

FLG

EPAD

9

AP2301MPG-13_MSOP8

80mil

10

USB3RN1_JUSB2_R

9

USB3RP1_JUSB2_R

7

USB3TN1_JUSB2_R

6

USB3TP1_JUSB2_R

+5V_USB_PWR1

10

USB3RN2_JUSB1_R

9

USB3RP2_JUSB1_R

7

USB3TN2_JUSB1_RUSB3TN2_JUSB1_R

6

USB3TP2_JUSB1_R

80mil

1

2

1

2

USB_OC0#USB_EN#

CI15

0.1U_0402_16V7K

CI17

0.1U_0402_16V7K

+5V_USB_PWR1

CI1

220U_6.3V_M

USB_OC0# <12>

+5V_USB_PWR2

CI8

220U_6.3V_M

USB connector1 USB20 port1 USB30 port2

JUSB1

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND

2

D-

6

SSRX+

4

GND

5

SSRX-

ACON_TARA4-9K1311

CONN@

10

GND

11

GND

12

GND

13

GND

2

3

DI2

L30ESDL5V0C3-2_SOT23-3

ESD@

1

USB3TP2_JUSB1_R

USB3TN2_JUSB1_R USB20_JUSB1_P1_R

USB20_JUSB1_N1_R USB3RP2_JUSB1_R

USB3RN2_JUSB1_R

1

+

2

1

CI2

CI40

2

0.1U_0402_16V7K

10U_0603_6.3V6M

USB connector2 USB20 port0 USB30 port1

JUSB2

CONN@JUSB2

CONN@

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND

2

D-

6

SSRX+

4

GND

5

SSRX-

ACON_TARA4-9K1311

10

GND

11

GND

12

GND

13

GND

2

3

DI5

L30ESDL5V0C3-2_SOT23-3

ESD@

1

USB3TP1_JUSB2_R

USB3TN1_JUSB2_R USB20_JUSB2_P0_R

USB20_JUSB2_N0_R USB3RP1_JUSB2_R

USB3RN1_JUSB2_R

10U_0603_6.3V6M

0.1U_0402_16V7K

1

+

2

0.1U_0402_16V7K

1

CI43

CI9

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

USB3.0

LA-9984P

1

24 57Wednesday, May 22, 2013

1.0

5

4

+5VALW

3

2

1

CI31

CI23

+5VALW

1

2

1

2

1

2

1

CI22

0.1U_0402_16V7K

2

1

CI16

0.1U_0402_16V7K

2

CI30

0.1U_0402_16V7K

1

CI25

0.1U_0402_16V7K

2

1 2

4

UI5

1

GND

2

VIN VIN3VOUT

4

EN

2.0A

UI4

GND

VOUT VOUT

VIN VIN3VOUT

FLG

EN

EPAD

9

AP2301MPG-13_MSOP8

2.0A

VOUT VOUT

FLG

EPAD

9

AP2301MPG-13_MSOP8

8 7 6 5

+5V_USB_PWR4

8 7 6 5

+5V_USB_PWR3

80mil

USB_OC1#USB_EN#

1

CI24

0.1U_0402_16V7K

2

USB_OC1#USB_EN#

1

CI32

0.1U_0402_16V7K

2

USB_OC1# <12>

USB20_USBDB_P3_R USB20_USBDB_N3_R

USB20_JUSB3_N2_R USB20_JUSB3_P2_R

DI7

L30ESDL5V0C3-2_SOT23-3

DI7

ESD@

2

3

1

+5V_USB_PWR4

USB connector3 USB20 port2

+5V_USB_PWR3

JUSB3

1

VBUS

2

D-

3

D+

4

GND

5

GND

6

GND

7

GND

8

GND

ACON_UARBG-4K1926

CONN@

USB connector4 USB20 port3

JDB

1

2

3

4

5

6

7

8

JESS_UCNR2210M008-0

CONN@

SP01001EX00

2nd:

SP01001AA00

Main:

Change CONN symbol for DFB

+5V_USB_PWR3

0.1U_0402_16V7K

10U_0603_6.3V6M

1

CI19

CI44

2

CI20

220U_6.3V_M

1

+

2

Place close to JUSB3

9

G1

10

G2

1

CI27

D D

WCM-2012HS-900T_4P

USB20_JUSB3_P2<12>

USB20_JUSB3_N2<12>

C C

B B

USB20_USBDB_P3<12>

USB20_USBDB_N3<12>

USB20_USBDB_P3

USB20_JUSB3_P2

USB20_JUSB3_N2

WCM-2012HS-900T_4P

4

1

LI10

EMI@

3

2

4

1

LI7

EMI@

47U_0805_6.3V4Z

3

USB20_USBDB_P3_R

2

USB20_USBDB_N3_RUSB20_USBDB_N3

47U_0805_6.3V4Z

3

2

CI21

CI27

4.7U_0805_10V4Z

2

USB_EN#<24,30>

USB20_JUSB3_P2_R

USB20_JUSB3_N2_R

1

4.7U_0805_10V4Z

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

MB to USB2.0 DB

LA-9984P

1

25 57Wednesday, May 22, 2013

1.0

5

D D

4

Mini WLAN/WIMAX H=6.7

3

+3V_WLAN

1

2

CC47

靠靠靠靠靠靠靠靠

wlan connector

0.1U_0402_10V7K

0.047U_0402_16V4Z

0.1U_0402_10V7K

@ CM47

@

1

CM47

2

0.1U_0402_10V7K

2

CM40

1

4.7U_0603_6.3V6K

2

1

CM48

CM46

CM43

1

2

1

+3V_WLAN

JMINI

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

GND1

CONCR_525B01BE17A

CONN@

10mils, All pins

12

WLAN_CLKREQ#

CLK_PCIE_WLAN# CLK_PCIE_WLAN

PCIE_PTX_WLANRX_N4_C PCIE_PTX_WLANRX_P4_C

RM11

100K_0402_5%

1 2

WLAN_CLKREQ#<9>

CLK_PCIE_WLAN#<9> CLK_PCIE_WLAN<9>

PCIE_PRX_WLANTX_N4<12> PCIE_PRX_WLANTX_P4<12>

PCIE_PTX_WLANRX_N4<12> PCIE_PTX_WLANRX_P4<12>

C C

BT_ON#<11>

1 2

CM49 0.1U_0402_10V7KCM49 0.1U_0402_10V7K

1 2

CM44 0.1U_0402_10V7KCM44 0.1U_0402_10V7K

EC_TX

EC_TX<30>

EC_RX

EC_RX<30>

BT_ON#

RM13 1K_0402_1%RM13 1K_0402_1%

HDD LED

SATA_ACT#<8>

B B

SATA_ACT#

1 2

RD15

RD15 390_0402_5%

390_0402_5%

1 2

LED2

LED2 12-21C-T3D-CM2P1B18X-2C_WHITE

12-21C-T3D-CM2P1B18X-2C_WHITE

+5VS

3

Power LED

PWR_PWM_LED#<30>

1 2

RD14

RD14 390_0402_5%

390_0402_5%

1 2

LED1

LED1 12-21C-T3D-CM2P1B18X-2C_WHITE

12-21C-T3D-CM2P1B18X-2C_WHITE

+5VALW

3

Battery LED

White

RD16

RD16 680_0402_1%

680_0402_1%

A A

BATT_CHG_LED#<30>

BATT_LOW_LED#< 30>

5

BATT_CHG_LED#

BATT_LOW_LED#

1 2

RD17

RD17 390_0402_5%

390_0402_5%

White

2

1

3

Amber

LED3

LED3 HT-210UD5-BP5_AMBER-WHITE

HT-210UD5-BP5_AMBER-WHITE

+5VALW

4

GND2

+3V_WLAN

+1.5VS

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

PLT_RST#

DDR_XDP_WLAN_TP_SMBCLK DDR_XDP_WLAN_TP_SMBDAT

USB20_MINI1_N4 USB20_MINI1_P4

WL_LED# BT_LED#

WL_LED#

BT_LED#

1 2

WL_LED#

1 2

WL_LED#

BT_LED#

100K_0402_5%

RD48

RD48 0_0402_5%

0_0402_5%

RD49

RD49 0_0402_5%

0_0402_5%

+3VS

12

RM110

RM110 10K_0402_5%

10K_0402_5%

PLT_RST# <10,21,30,48,6>

DDR_XDP_WLAN_TP_SMBCLK <17,18,19,27,6,9> DDR_XDP_WLAN_TP_SMBDAT <17,18,19,27,6,9>

USB20_MINI1_N4 <12> USB20_MINI1_P4 <12>

1 2

@

RM25

RM25 0_0805_1%

0_0805_1%

1 2

@

RM26

RM26 0_0805_1%

0_0805_1%

12

RD47

RD45

100K_0402_5%

WL_BT_LED#_EC2

WL_BT_LED#_ECBT _LED#

+3VS

5

1

IN1

2

IN2

3

1 3

+3V_WLAN+3VS

12

2

G

S

QD19

QD19 2N7002K_SOT23-3

2N7002K_SOT23-3

WL_BT_LED#_EC2 <30>

CD63

@CD63

@

0.1U_0402_10V7K

1 2

UD1

@UD1

@

MC74VHC1G08DFT2G_SC70-5

VCC

4

OUT

GND

12

+3VS

2

2N7002K_SOT23-3

G

D

S

D

S

G

S

QD18

QD18 2N7002K_SOT23-3

2N7002K_SOT23-3

13

D

@

WL_BT_LED#_EC

RD52

@RD52

@

100K_0402_5%

QM30

WL_OFF#WLAN_RADIO_DIS#_R

+3VS +CPU_CORE

22U_0603_6.3V6M

ESD solution

RD46

@ RD46

@

2

100K_0402_5%

13

D

@

CM45

1 2

ESD@

+5VALW+3VS

12

WL_OFF# <11>

WL_BT_LED#_EC

WL_BT_LED#_EC <30>

WL_BT_LED<30>

WL_BT_LED

RD50

100K_0402_5%

RD51

RD51 0_0402_5%

0_0402_5%

WL_BT_LED#_EC WL_BT_LED#

1 2

@

Reserve for WLAN module modified

Wireless LED

QD20

QD20 2N7002K_SOT23-3

2N7002K_SOT23-3

1 2

RD18

RD18 680_0402_1%

680_0402_1%

WL_BT_LED#

13

D

2

G

S

12

LED4

12-21C-T3D-CM2P1B18X-2C_WHITE

1 2

3

+5VALW

Reserve for WLAN module LED control

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Mini Card/LED

LA-9984P

1

26 57Wednesday, May 22, 2013

1.0

5

4

3

2

1

2.2U_0603_6.3V6K

1

CE22

2

EN_DFAN1

+FAN_POWER

40mil

1

CE23

2

1000P_0402_50V7K

FAN Control circuit

+5VS

+3VS

12

RE50

RE50 10K_0402_5%

10K_0402_5%

1

CE24

0.01U_0402_16V7K

2

CE25

2.2U_0603_6.3V6K

1 2

UE3

1

VEN

2

VIN

3

VO

4

VSET

APE8873M SOP 8P

GND GND GND GND

+FAN_POWER

40mil

8 7 6 5

JFAN

1

2

3

4

GND

5

GND

ACES_85204-0300N

CONN@

D D

POWER/B

+3VALW

LID_SW#<30>

LID_SW#

ON/OFFBTN#

JPWR

1

2

3

4

5

GND

6

GND

HB_A090420-SAHR21

CONN@

EN_DFAN1<30>

Power ON Circuit

ON/OFF switch

+3VLP

RE49

C C

TOP Side

SW1

SW1 SMT1-05-A_4P

SMT1-05-A_4P

1

2

6

3

4

5

RE49 100K_0402_5%

100K_0402_5%

1 2

1

CE20

0.1U_0402_16V7K

2

ON/OFFBTN# <30>

FAN_SPEED1<30>

Bottom Side

SW2

SW2 SMT1-05-A_4P

SMT1-05-A_4P

3

1

2

4

5

6

Pop only before MP

B B

KSI[0..7]<30>

KSO[0..16]<30>

KSI[0..7]

KSO[0..16]

Touch pad

+3VS

TP_CLK<30>

TP_DATA<30>

DDR_XDP_WLAN_TP_SMBCLK<17,18,19,26,6,9> DDR_XDP_WLAN_TP_SMBDAT<17,18,19,26,6,9>

A A

DDR_XDP_WLAN_TP_SMBCLK DDR_XDP_WLAN_TP_SMBDAT

TP_CLK TP_DATA

JTP

1

2

3

4

5

7

5

G1

6

8

6

G2

PS_HPF10052-06M000R

CONN@

SP01001BG00

2nd:

SP01000R910

Main:

Change CONN symbol for DFB

+5VS

RE60

1 2

240_0402_1%

CAPS_LED<30>

240_0402_1%

INT_KBD Connector

JKB

CONN@JKB

CONN@

HB_A823020-SBHR21

30

32

30

GND

29

KSI7 KSI6 KSI4 KSI2 KSI5 KSI1 KSI3 KSI0 KSO5 KSO4 KSO7 KSO6 KSO8 KSO3 KSO1 KSO2 KSO0 KSO12 KSO16 KSO15 KSO13 KSO14 KSO9 KSO11 KSO10 KB_CAPS_PWR

31

29

GND

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

FAN/TP/PWR SW

Size Document Number Rev

LA-9984P

Date: Sheet of

1

27 57Wednesday, May 22, 2013

1.0

A

B

C

D

E

+5VS and +3VS switch

1 1

+5VALW

12

R10

R10 100K_0402_5%

SUSP

12

100K_0402_5%

13

D

2

Q8

G

2N7002K_SOT23-3

G

2N7002K_SOT23-3

S

SUSP#<30,39,40>

10mil

R2313

1 2

R2318

1 2

82K_0402_5%

470K_0402_5%

12

C2322

0.01U_0603_25V7K

+5VALW

U2301

1

VIN1

2

VIN1

+3VALW

3

4

5

6 7

ON1

VBIAS

ON2

VIN2 VIN2

TPS22966DPUR_SON14_2X3

5VS_GATE

3VS_GATE

12

+3VALW

C2309

0.01U_0603_25V7K

SHORT DEFAULT

14

VOUT1 VOUT1

GND

VOUT2 VOUT2

GPAD

+5VALW

CT1

CT2

5VS

13

12

11

10

9

3VS

8

15

J510

2

JUMP_43X79@

J511

2

JUMP_43X79@

SHORT DEFAULT

C2306

10U_0603_6.3V6M

C2306

10U_0603_6.3V6M

C2305

10U_0603_6.3V6M

C2305

C2318

10U_0603_6.3V6M

C2318

10U_0603_6.3V6M

C2316

10U_0603_6.3V6M

C2316

10U_0603_6.3V6M

1

2

2 2

2

10U_0603_6.3V6M

1

2

+5VS

112

C2308

10U_0603_6.3V6M

C2308

10U_0603_6.3V6M

C2307

10U_0805_10V4Z@C2307

10U_0805_10V4Z

1

@

2

+3VS

C2323

10U_0603_6.3V6M

C2323

10U_0603_6.3V6M

C2324

10U_0603_6.3V6M@C2324

10U_0603_6.3V6M

1

@

2

SUSP#

R16

R16 100K_0402_5%

100K_0402_5%

+3VALW_PCH switch

3 3

PCH_PWR_EN<30>

PCH_PWR_EN

10mil

4 4

A

1 2

R416

R416 0_0402_1%

0_0402_1%

+3VALW_PCH_GATE

@

12

C2314

0.01U_0603_25V7K

+3VALW

U2304

1

VOUT1

VIN1

2

VOUT1

VIN1

3

4

5

6 7

CT1

ON1

GND

VBIAS

ON2

CT2

VIN2

VOUT2

VIN2

VOUT2

GPAD

TPS22966DPUR_SON14_2X3

+3VALW

C2313

C2311

10U_0603_6.3V6M

C2311

10U_0603_6.3V6M

1

2

SHORT DEFAULT

14

3VALW_PCH

13

12

11

10

9 8

15

10U_0603_6.3V6M

1

2

B

J513

2

JUMP_43X79@

+3VALW_PCH

112

C2310

10U_0805_10V4Z@C2310

10U_0805_10V4Z

C2312

10U_0603_6.3V6M

C2312

10U_0603_6.3V6M

1

@

2

+0.675VS +1.05VS

12

R2314

R2314 22_0603_5%

22_0603_5%

13

D

2

SUSP SUSP

G

Q2307

S

2N7002K_SOT23-3

D

S

12

R2315

R2315 470_0603_5%

470_0603_5%

@

13

2

G

Q2308

Q2308 2N7002K_SOT23-3

2N7002K_SOT23-3

@

For Intel S3 Power Reduction

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DC/DC Interface

LA-9984P

E

28 57Wednesday, May 22, 2013

1.0

5

D D

+3VLP+1.05VS+1.8VGS +LAN_IO +3VALW

GCLK@

GCLKDIS@

C C

B B

Depop if GCLK with UMA

1

2

0.1U_0402_10V7K

GCLK@

1

CG1

2

0.1U_0402_10V7K

CG2

CG3

2

0.1U_0402_10V7K

Place close to UG1.8

12P_0402_50V8J~D

0.1U_0402_10V7K

CG8

GCLK@CG8

GCLK@

12

15P_0402_50V8J

CG9

GCLK@CG9

GCLK@

12

GCLK@

1

CG4

2

25MHZ_10PF_7V25000014

4

+RTCBATT

12

RG1

GCLK@RG1

GCLK@

330_0402_5%

GCLK@

1

CG10

2

0.1U_0402_10V7K

CLK_X1

YG1

GCLK@YG1

GCLK@

1

3

2

OSC

GND

4

OSC

GND

CLK_X2

22U_0805_6.3V6M

CG5

GCLK@

+3VLP

+1.8VGS

+LAN_IO

+1.05VS

+3VALW

1

2

GCLK_VRTC

CLK_X1 CLK_X2

SLG3NB274VTR_TQFN16_2X3

3

UG2

GCLKDIS@UG2

UG1

GCLKUMA@UG1

GCLKUMA@

SLG3NB244VTR TQFN 16P CLK GEN

SLG3NB3374V is for DIS by output 24M*1,25M*1, 27M*1, 32K*1 SLG3NB3375V is for UMA by output 24M81, 25M*1, 32K*1

UG1

10

VBAT

VDD_RTC_OUT

15

+V3.3A

2

VDD

VDDIO_27M1127MHz

8

VDDIO_25M_A

3

VDDIO_25M_B

1

XTAL_IN

16

XTAL_OUT

@

4

25MHz_A

25MHz_B

GND1

GND2

7

14

RTC_VOUT

9

PCH_RTCX1_R

32kHz

12

VGA_X1_R

6

LAN_X1_R

5

PCH_X1_R

GND3

GND4

13

17

GCLKDIS@

SLG3NB244VTR TQFN 16P CLK GEN

+RTCVCC

12

RG2

@RG2

@

0_0402_5%

2.2U_0603_6.3V6K

1

CG6

GCLK@

2

0_0402_5%

1 2

RG3

GCLK@

1 2

RG4 10_0402_1%

GCLKDIS@

1 2

RG5 33_0402_5%

GCLK@

1 2

RG6 0_0402_5%

GCLK@

CPU_CLK 24M(P.9 ) Place RG6 close to YC2

2

CPU_RTC 32.768k (P.8) Place RG3 close to YC1

PCH_RTCX1 <8>

XTALIN_R

XTLI_R

XTAL24_IN <9>

XTALIN_R

1

@

CG11

CG11 5P_0402_50V8C

5P_0402_50V8C

2

RG7 0_0402_5%

RG8 0_0402_5%GCLK@RG8 0_0402_5%GCLK@

1

GCLK@

CG7

CG7 5P_0402_50V8C

5P_0402_50V8C

2

VGA 27M(P.29) Place RG7 close to YV1

GCLKDIS@

1 2

LAN 25M(P.21) Place RG8 close to YL2

1

XTALIN <49>

XTLI <21>

RG3, RG7,RG8, R G6 0ohm_0402 for isolated CL K tail

Reserve CG11 fo r vendor Place close to RG4

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

GCLK

Size Document Number Rev

LA-9984P

Date: Sheet of

1

57Wednesday, May 22, 2013

23

57Wednesday, May 22, 2013

23

57Wednesday, May 22, 2013

23

1.0

5

+3VALW

D D

PLT_RST#

CE36

0.047U_0402_16V4Z

Place CC30 close to RC51.1

1

ESD@CE36

ESD@

2

@EMI@

CE12

0.1U_0402_10V7K

RE8 47K_0402_5%RE8 47K_0402_5%

+3VALW

CE11 0.1U_0402_10V7KCE11 0.1U_0402_10V7K

@EMI@

R2354

R2354 0_0402_5%

12

0_0402_5%

1 2

12

"TOUCH_RST" for OAK 15 only

C C

+3VALW

1 2

RE71 10K_0402_5%RE71 10K_0402_5%

+3VALW

RP36

2.2K_0804_8P4R_5%

LID_SW#

45

EC_SMB_CK1

36

EC_SMB_DA1

27

EC_SMB_CK2

18

EC_SMB_DA2

KSI[0..7]<27>

KSO[0..16]<27>

Reserve for ESD

12

CE27

0.1U_0402_10V7K

CE28

0.1U_0402_10V7K

B B

A A

Please close to EC

VR_HOT#<42>

H_PROCHOT#<36,6>

SIO_SLP_S3#

ESD@CE27

ESD@

12

SIO_SLP_S5#

ESD@CE28

ESD@

12

PCH_PWROK

RE18

RE18 10K_0402_5%

10K_0402_5%

FAN_SPEED1

CE29

220P_0402_50V8J

Please close to EC

VR_HOT#

0_0402_1%

H_PROCHOT#

SN74LVC1G06DCKR_SC70-5

CE19

47P_0402_50V8J

RE44

1

2

0.1U_0402_10V7K

+3VS

CE15

12

@

UE2

Y4A

1

2

1

2

5

P

2

G3NC

RE47

1

RE47 100K_0402_5%

100K_0402_5%

1 2

4

EMI@

LE1

LE1 FBMA-L11-160808-800LMT_0603

FBMA-L11-160808-800LMT_0603

1 2

1

CE1

0.1U_0402_10V7K

2

ME_SUS_PWR_ACK<10>

1

CE2

0.1U_0402_10V7K

2

WL_BT_LED<26>

KB_RST#<11>

SERIRQ<11>

LPC_LFRAME#<9>

LPC_LAD3<9> LPC_LAD2<9> LPC_LAD1<9> LPC_LAD0<9>

CLK_PCI_LPC<9>

PLT_RST#<10,21,26,48,6>

EC_SCI#<11>

TOUCH_RST

KSI[0..7]

KSO[0..16]

PCH_DPWROK<10>

EC_SMB_CK1<36,37> EC_SMB_DA1<36,37> EC_SMB_CK2<19,49,9> EC_SMB_DA2<19,49,9>

SIO_SLP_S3#<10> SIO_SLP_S5#<10> EC_LID_OUT# <11>

EC_SMI#<8>

PS_ID<36>

CE_EN<31>

DGPU_PWROK<10,44>

ENVDD_PCH<10,19>

DBC_EN<31> FAN_SPEED1<27> PCIE_WAKE#<10,21>

EC_TX<26> EC_RX<26>

PCH_PWROK<10>

RUNPWROK<6>

+1.05V_PGOOD<40> VCCST_PG_EC<13>

2

@EMI@

CE5

CE5 1000P_0402_50V7K

1000P_0402_50V7K

1

WL_BT_LED KB_RST# SERIRQ LPC_LFRAME# LPC_LAD3 LPC_LAD2 LPC_LAD1 LPC_LAD0

CLK_PCI_LPC PLT_RST# EC_RST# EC_SCI# TOUCH_RST

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16

1 2

@

RE37 0_0402_1%

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

SIO_SLP_S3# SIO_SLP_S5# EC_LID_OUT# EC_SMI# PS_ID CE_EN DGPU_PWROK ENVDD_PCH DBC_EN FAN_SPEED1 PCIE_WAKE# EC_TX EC_RX PCH_PWROK ME_SUS_PWR_ACK RUNPWROK

+1.05V_PGOOD VCCST_PG_EC

2

1

UE1

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCII#/GPIO0E

38

GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CK1/GP IO44

78

EC_SMB_DA1/GPIO45

79

EC_SMB_CK2/GP IO46

80

EC_SMB_DA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

GPIO0D

25

EC_INVT_PWM/GP IO11

28

FAN_SPEED1/GPIO14

29

EC_PME#/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWR OK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

XCLKI/GPIO5D

123

XCLKO/GPIO5E

+3VALW

@EMI@

CE6

CE6 1000P_0402_50V7K

1000P_0402_50V7K

LPC & MISC

Int. K/B

Int. K/B Matrix

Matrix

9

22

33

EC_VDD/VCC

PWM Output

DA Output

PS2 Interface

SPI Device Interface

SM Bus

GPIO

GND/GND

11

24

EC_VDD/VCC

GND/GND

3

+EC_VCCA

+3VLP

67

96

111

125

EC_VDD0

EC_VDD/VCC

EC_VDD/AVCC

BATT_TEMP/GPIO38

AD Input

DAC_BRIG/GPIO3C

EN_DFAN1/GPIO3D

CHGVADJ/GPIO3F

EC_MUTE#/GPIO4A

USB_EN#/GPIO4B CAP_INT#/GPIO4C

CPU1.5V_S3_GATE/GP XIOA00

WOL_EN/GPXIOA01

ME_EN/GPXIOA02

VCIN0_PH/GPXIOD00

SPI Flash ROM

PECI_KB930/GPIO41

BATT_CHG_LE D#/GPIO52

CAPS_LED#/GPIO53

GPIO

PWR_LED #/GPIO54

BATT_LOW_ LED#/GPIO55

PM_SLP_S4#/GPIO59

EC_RSMRST# /GPXIOA03 EC_LID_OUT#/GPXIOA04 PROCHOT_IN/GPXIOA05

H_PROCHOT# _EC/GPXIOA06

VCOUT0_PH/GPXIOA07

GPO

BKOFF#/GPXIOA08

PBTN_OUT# /GPXIOA09

PCH_APWROK /GPXIOA10

SA_PGOOD/GPXIOA11

EC_ON/GPXIOD02

ON/OFF/GPXIOD03

GPI

LID_SW#/GPXIOD04

SUSP#/GPXIOD05

PECI_KB9012/GPXIOD07

GND/GND

AGND/AGND

GND/GND

GND0

KB9012QF-A4_LQFP128_14X14

35

69

94

113

ECAGND

FBMA-L11-160808-800LMT_0603

+EC_VCCA

1

2

GPIO0F

BEEP#/GPIO10

GPIO12

ACOFF/GPIO13

GPIO39

ADP_I/GPIO3A

GPIO3B GPIO42

IMON/GPIO43

IREF/GPIO3E

EAPD/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

SPIDI/GPIO5B

SPIDO/GPIO5C

SPICLK/GPIO58

SPICS#/GPIO5A

ENBKL/GPIO40

FSTCHG/GPIO50

SYSON/GPIO56 VR_ON/GPIO57

AC_IN/GPXIOD01

GPXIOD06

V18R

LE2

CE7

0.1U_0402_10V7K

ECAGND

21 23 26 27

63 64 65 66 75 76

68 70 71 72

83 84 85 86 87 88

97 98 99 109

119 120 126 128

73 74 89 90 91 92 93 95 121 127

100 101 102 103 104 105 106 107 108

110 112 114 115 116 117 118

124

12

ECAGND <36>

"KB_LED_PWM" for OAK 17 only

KB_LED_PWM BEEP# USB_EN# ACOFF

BATT_TEMP WL_BT_LED#_EC ADP_I

AD_BID0 PANEL_BKLEN

EN_INVPWR EN_DFAN1 EC_ENVDD LCD_TEST

EC_MUTE# SIO_SLP_S4# IMVP_PWRGD SYS_PWROK TP_CLK TP_DATA

SUSACK# WOL_EN ME_EN VCIN0_PH

EC_SPI_MOSI_1 EC_SPI_MISO_1 EC_SPI_CLK_R EC_SPI_CS0#

ERP_LOT6 WL_BT_LED#_EC2 SIO_SLP_S0# BATT_CHG_LED# CAPS_LED PWR_PWM_LED# BATT_LOW_LED# SYSON VR_ON_EC VR_ON CPU_DETECT#

1 2

RE11 100K_0402_5%RE11 100K_0402_5%

EC_RSMRST#

VCIN1_PH VCOUT1_PH VCOUT0_PH# BKOFF# PBTN_OUT#

ACIN_65W

ACIN EC_ON ON/OFFBTN# LID_SW# SUSP# 65W/90W# PECI_KB9012

+V18R

RE36 43_0402_1%RE36 43_0402_1%

1

CE16

4.7U_0805_10V4Z

2

12

1 2

RE43

RE43 43_0402_1%

43_0402_1%

20mil

KB9012A3 change to

VCOUT1_PH

KB9012A4 SA00004OB30

2

+3VALW

RE3

RE3 100K_0402_1%

100K_0402_1%

Ra

1 2

RE5

Rb

200K_0402_1%

UMA@

1 2

ECAGND

@

RE7

RE7 0_0402_5%

0_0402_5%

1 2

@

RE12 0_0402_5%

RE2

RE2 10K_0402_5%

10K_0402_5%

1 2

AD_BID0

1

CE8

0.1U_0402_10V7K

2

BATT_TEMP <36,37>

12

PCH_HOT#

VR_ON

CE34

ESD@CE34

ESD@

0.1U_0402_10V7K

Place CE34 between DE1 and RE12

VCCST_PG_EC

CE35

ESD@CE35

ESD@

220P_0402_50V8J

Place CE35 between DE1 and UE1

EC_RSMRST# <10>

Board ID

Venus DIS@ UMA UMA@

RE5

DIS@

RE5

DIS@

330K_0402_1%

SD034330380

KB_LED_PWM <32>

BEEP# <22> USB_EN# <24,25> ACOFF <37>

12

CE9 100P_0402_50V8JCE9 100P_0402_50V8J

WL_BT_LED#_EC <26>

ADP_I <36,37>

PANEL_BKLEN <10>

EN_INVPWR <31> EN_DFAN1 <27> EC_ENVDD <31> LCD_TEST <31>

EC_MUTE# <22> SIO_SLP_S4# <10> IMVP_PWRGD <42> SYS_PWROK <10,6> TP_CLK <27> TP_DATA <27>

SUSACK# <10> WOL_EN <21> ME_EN <8> VCIN0_PH <36>

EC_SPI_MOSI_1 <9> EC_SPI_MISO_1 <9> EC_SPI_CLK_R <9> EC_SPI_CS0# <9>

ERP_LOT6 <36> WL_BT_LED#_EC2 <26> SIO_SLP_S0# <10> BATT_CHG_LED# <26> CAPS_LED <27> PWR_PWM_LED# <26> BATT_LOW_LED# <26>

CPU_DETECT# <6>

VCIN1_PH <36> VCOUT1_PH <36> VCOUT0_PH# <38> BKOFF# <19> PBTN_OUT# <10,6>

PCH_PWR_EN <28>

ACIN_65W <49>

ACIN <10,36,37,49> EC_ON <38> ON/OFFBTN# <27> LID_SW# <27> SUSP# <28,39,40> 65W#/90W <36>

PECI_EC <6>

ME_FWP PCH has internal 20K PD. (suspend power rail)

ME_EN

12

@

RE326

RE326 1K_0402_5%

1K_0402_5%

PCH_HOT# <9>

1

2

1

2

@

RE1

RE1 10K_0402_5%

10K_0402_5%

1 2

SD028000080 0_0402_5%

SD034560280 56K_0402_1%

SD034130380 130K_0402_1% SD034160380 SD034200380 200K_0402_1%

SD034330380 330K_0402_1%

TP_CLK

TP_DATA

VR_ON

VCCST_PG_EC

3

DE1

@ESD@

L03ESDL5V0CG3-2_SOT-523-3

Place DE1 close to UE1

VR_ON <13,42>

1

CE26

0.1U_0402_10V7K

2

LID_SW#

PCH_PWROK

SYS_PWROK

CPU_DETECT#

1 2

CE30 0.1U_0402_10V7K

1 2

CE31 0.1U_0402_10V7K

1 2

CE32 0.1U_0402_10V7K

1 2

CE33 0.1U_0402_10V7K

Place CE30,CE31,CE32,CE33 close to UE1

CE18

ACIN

12

100P_0402_50V8J

1

SYSON <41>

ESD@

12K_0402_1%SD034120280 27K_0402_1%SD034100300 43K_0402_1%SD034430280

75K_0402_1%SD034750280 100K_0402_1%SD034100380

160K_0402_1%

240K_0402_1%SD000001B80 270K_0402_1%SD00000G280

430K_0402_1%SD028430380

2

+3VS

12

RE94.7K_0402_5% RE94.7K_0402_5%

12

RE104.7K_0402_5% RE104.7K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

EC ENE-KB9012

Size Document Number Rev

LA-9984P

Date: Sheet of

1

30 57Wednesday, May 22, 2013

1.0

5

LCD PWR CTRL

D D

CX7

4.7U_0805_10V4Z

+3VS

1

2

W=60mils

1

2

CX9

0.1U_0402_10V7K

UX1

5

VIN

4

SS

@CX9

@

APL3512ABI-TRG_SOT23-5

APL3512 PIN 4 tire to VIN

VOUT

GND

1

2

3

EN

FBMA-L11-201209-221LMA30T_0805

SS table

12

@

TL_ENVDD<19>

EC_ENVDD<30>

C C

@

RX7 0_0402_1%

RX8 0_0402_5%@RX8 0_0402_5%@

12

ENVDD_R

LCD backlight PWR CTRL

QX2

SI3457CDV-T1-GE3_TSOP6

S

4

RX2

100K_0402_5%

RX2

100K_0402_5%

PWR_SRC_ON

RX3

RX3 100K_0402_5%

100K_0402_5%

QX1

QX1 2N7002KW_SOT323-3

2N7002KW_SOT323-3

QX2

D

G

3

60mil

B+

CX4

1000P_0402_50V7K

CX4

1000P_0402_50V7K

12

1

B B

EN_INVPWR<30>

2

12

13

D

2

G

S

1 2

Css

0.1uF

10nF

1nF

Open or tied to VIN

6 5 2 1

1

CX5

0.1U_0603_50V_X7R

2

4

W=60mils

LX1

Tss

100mS

10mS

1mS

+INV_PWR_SRC

60mil

+LCDVDD_CONN+LCDVDD

CX11

0.1U_0402_16V4Z

CX11

0.1U_0402_16V4Z

1

2

+INV_PWR_SRC

3

eDP@

EDP_HPD_PANEL<19>

EDP_HPD_PANEL CE_EN_R

1 2

RX53 0_0402_5%

Close to JLVDS

2

1

For eDP co-layout

LVDS Connector

JLVDS

0.1U_0402_16V7K

CX2

CX1

1

2

1

2

G1

3

G2

4

G3

5

G4

6

G5

7

G6

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

STARC_107K40-000001-G2

CONN@

+LCDVDD+3VS

0.1U_0402_16V7K

10U_0805_10V6K

1

2

41 42 43 44 45 46

CX3

CE_EN_R

DBC_EN_R

USB20_CAM_P7_R USB20_CAM_N7_R

MIC_CLK

MIC_DATA LCD_TEST

DISPOFF#

+INV_PWR_SRC

W=60mils

LVDS_A0LVDS_A0+

LVDS_A1LVDS_A1+

LVDS_A2LVDS_A2+

LVDS_ACLKLVDS_ACLK+

LVDS_B0LVDS_B0+

LVDS_B1LVDS_B1+

LVDS_B2LVDS_B2+

LVDS_BCLKLVDS_BCLK+

LVDS_A0-<19>

+LCDVDD_CONN

RX26

100K_0402_5%

LVDS_A0+<19>

LVDS_A1-<19> LVDS_A1+<19>

LVDS_A2-<19> LVDS_A2+<19>

LVDS_ACLK-<19> LVDS_ACLK+<19>

LVDS_B0-<19> LVDS_B0+<19>

LVDS_B1-<19> LVDS_B1+<19>

LVDS_B2-<19> LVDS_B2+<19>

LVDS_BCLK-<19> LVDS_BCLK+<19>

LCD_TEST<30>

EDID_CLK<19>

EDID_DATA<19>

+3VS

+3VS_CAM

MIC_CLK<22>

MIC_DATA<22>

12

DX1

TL_BKOFF#<19>

CX8

4.7U_0805_10V4Z

CX8

4.7U_0805_10V4Z

1

2

USB20_CAM_P7<12>

USB20_CAM_N7<12>

CE_EN_R only for reserve.

CE_EN<30>

DBC_EN<30>

CE_EN

DBC_EN DBC_EN_R

12

RB751V-40_SOD323-2

WCM-2012HS-900T_4P

4

1

LX6

EMI@

1 2

RX22 0_0402_5%

@EMI@

1 2

RX21 0_0402_5%

@EMI@

@

RX18

RX18 0_0402_5%

0_0402_5%

1 2

@

RX19

RX19 0_0402_1%

0_0402_1%

3

2

RX20

0_0402_1%

DISPOFF#

12

10K_0402_5%

10K_0402_5% RX9

RX9

3

2

USB20_CAM_P7_R

USB20_CAM_N7_R

W=60mils

TL_INVT_PWM<19>

CE_EN_R

12

@

RX23

RX23 0_0402_5%

0_0402_5%

Place close to JLVDS

Webcam PWR CTRL

+3VS +3VS_CAM

A A

5

1 2

@

RX27

RX27 0_0603_1%

0_0603_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

LVDS/webcam

LA-9984P

1

31 57Wednesday, May 22, 2013

1.0

A

B

C

D

E

F

G

H

* Key Board Back Light

1 1

+5VS

1 2

22U_0603_6.3V6M

CE58

ESD@

+3VALW

ESD solution

KB_DET#<11>

13

D

QE4

S

KBBL@

KB_LED_PWM<30>

S

2N7002BKW_SOT323-3~D

2 2

+5VS +5VS_KBL

1U_0603_10V6K

CE56

1

2

+3VS

RE68

1 2

10K_0402_5%

2

G

12

RE58

RE58 100K_0402_5%

100K_0402_5%

KBBL@

G

3

FE1

0.75A_24V_1812L075-24DR~OK

20mil

1 2

0_0805_5%

KBBL@

KB_BL_PWM

20mil

6

2

1

D

QE5

QE5 SI3456BDV-T1-E3 1N TSOP6

SI3456BDV-T1-E3 1N TSOP6

S

KBBL@

4 5

KBBL@FE1

KBBL@

12

RE59

@

+5VS_KBL

JKBBL

1 2 3 4

HB_A090420-SAHR21

CONN@

OAK 17 only

10U_0603_6.3V6M

1

CE57

KBBL@

CE57

2

SATA_PTX_DRX_P0_C<8> SATA_PTX_DRX_N0_C<8>

SATA_PRX_DTX_N0_C<8> SATA_PRX_DTX_P0_C<8>

CS105 0.01U_0402_16V7KCS105 0.01U_0402_16V7K CS106 0.01U_0402_16V7KCS106 0.01U_0402_16V7K

CS109 0.01U_0402_16V7KCS109 0.01U_0402_16V7K CS108 0.01U_0402_16V7KCS108 0.01U_0402_16V7K

+5V_HDD Source

+5V_HDD +5VS

@

JP13

1 2 3 4

5

GND

6

GND

JP13

2

112

JUMP_43X79

SHORT DEFAULT

12 12

+3VS

DEVSLP0<11>

RS7 0_0402_5%RS7 0_0402_5%

RS8 0_0402_5%@RS8 0_0402_5%@

HDD_DET#<11>

+5V_HDD

SATA HDD Connector

SATA_PTX_DRX_P0 SATA_PTX_DRX_N0

SATA_PRX_DTX_N0 SATA_PRX_DTX_P0

1 2

HDD_DET#

JHDD_P10

CS5

+5V_HDD

JHDD

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12 V1222GND

SANTA_194301-1

CONN@

1000P_0402_50V7K

1

2

24

GND

23

0.1U_0402_25V6K

0.1U_0402_25V6K 10U_0805_10V6K

10U_0805_10V6K

1

CS6

1

CS7

2

ODD BTB Connector

+5VS_ODD

JBTB1

3 3

ODD_EN#<11>

4 4

ODD Power Control

+5VS

1

CS13

2

B+

1 2

13

D

2

G

S

RS6

RS6 470K_0402_5%

470K_0402_5%

ODD_EN

QS3

QS3 2N7002KW_SOT323-3

2N7002KW_SOT323-3

1U_0402_6.3V6K

JP7

@ JP7

@

2

112

JUMP_43X79

QS2

D

6

S

2 1

SI3456BDV-T1-E3 1N TSOP6

G

3

1

2

45

CS16

0.1U_0603_50V_X7R

+5VS_ODD

ODD_DA#<11> SATA_PRX_DTX_N1_C<8> SATA_PRX_DTX_P1_C<8>

CS14 0.01U_0402_16V7KCS14 0.01U_0402_16V7K CS15 0.01U_0402_16V7KCS15 0.01U_0402_16V7K

ODD_DA#

CS17

0.1U_0402_25V6K

ESD@

12 12

1

2

ODD_DA# SATA_PRX_DTX_N1 SATA_PRX_DTX_P1

SATA_PRX_DTX_P1 SATA_PRX_DTX_N1 ODD_DA#

+5VS_ODD

Place CS17 close to JBTB

SP02000WP00 ( 2nd connector co-layout with JBTB1 Main )

JBTB1

1

2

3

4

5

6

7

8

9

10

11

12

13

GND

14

GND

15

GND

E&T_1133-Q12C-01R

CONN@

JBTB

2

112

4

334

6

556

8

778

10

9910

12

111112

14

G113G2

16

G315G4

18

G517G6

CONN@

ACES_50100-0127N-001

2 4 6 8 10 12

16 17 18

SATA_PTX_DRX_N1 SATA_PTX_DRX_P1

ODD_DETECT#

SATA_PTX_DRX_P1 SATA_PTX_DRX_N1

1 2

CS8 0.01U_0402_16V7KCS8 0.01U_0402_16V7K

1 2

CS9 0.01U_0402_16V7KCS9 0.01U_0402_16V7K

ODD_DETECT# <8>

SATA_PTX_DRX_P1_C <8> SATA_PTX_DRX_N1_C <8>

+5VS_ODD

1000P_0402_50V7K

1

CS10

2

10U_0805_10V6K

0.1U_0402_25V6K

1

2

CS12

CS11

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

F

Compal Electronics, Inc.

Title

HDD/ODD/KB-BL

Size Document Number Rev

LA-9984P

Date: Sheet

Date: Sheet of

G

32 57Wednesday, May 22, 2013

H

1.0

of

5

D D

4

3

2

1

Screw Hole

H1

H_2P8

@

1

H16

H_2P8

@

1

C C

H31

H_3P7

@

1

H6

H_3P3

@

1

H4

H2

H_2P8

@

1

H17

H_2P8

@

1

H32

H_3P7

@

1

H7

H_3P3

@

1

H5

H_5P0N

H_2P8

@

1

H18

H_5P0X3P0N

@

1

H34

H33

H_3P7

@

1

VGA stand-off

H9

H8

H_2P8

@

1

H35

H_3P0

@

1

CPU bracket

H_2P8

@

H11

H12

H_2P8

@

1

H10

H_3P3

@

H_3P5

@

H20

1

FD2

FD2 FIDUCIAL@

FIDUCIAL@

1

FAN stand-off

H_3P5

@

ODD-DB stand-off

FD4

FD3

FIDUCIAL@

FIDUCAL@

1

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Screw Hole

LA-9984P

1

33 57Wednesday, May 22, 2013

1.0

1

H19

1

FD1

B B

A A

5

FD1 FIDUCAL@

FIDUCAL@

1

5

V ers ion C h an ge L ist ( P . I. R . L ist )

V ers ion C h an ge L ist ( P . I. R . L ist )V ers ion C h an ge L ist ( P . I. R . L ist )

R e q ue st

P a g e# T i tle

Item

Item Issue D escription

P a g e#Pa ge #

ItemItem

34 Card Reader

1

D D

C C

B B

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

T itle

T itleT itle

D ate

D ateD ate

R e q ue stR eq u est

O w ner

O w nerOw ne r

4

Issue D escriptionD ate

Issue D escriptionIssue D escription

HW2012/04/27

The Card reader USB signal is incorrect. SWAP UR1 USB si gnal P/N

3

P ag e 1

P ag e 1P a ge 1

So lu t io n D escription

So lu t io n D escription R ev.

So lu t io n D escriptionSo l u tio n D escription

2

R e v .P a g e#

R e v .R ev .

0.2

1

36

37

A A

38

39

40

41

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

HW-PIR Page.1

Size Document Number Rev

LA-9984P

Date: Sheet of

1

34 57Wednesday, May 22, 2013

1.0

5

V ers ion C h an ge L ist ( P . I. R . L ist )

V ers ion C h an ge L ist ( P . I. R . L ist )V ers ion C h an ge L ist ( P . I. R . L ist )

R e q ue st

P a g e# T i tle

Item

Item Issue D escription

P a g e#Pa ge #

ItemItem

40

D D

C C

41

42

43

44

45

46

47

48

49

50

51

52

53

54

T itle

T itleT itle

D ate

D ateD ate

R e q ue stR eq u est

O w ner

O w nerOw ne r

4

Issue D escriptionD ate

Issue D escriptionIssue D escription

3

P ag e 2

P ag e 2P a ge 2

So lu t io n D escription

So lu t io n D escription R ev.

So lu t io n D escriptionSo l u tio n D escription

2

R e v .P a g e#

R e v .R ev .

1

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

HW-PIR Page.2

Size Document Number Rev

LA-9984P

Date: Sheet of

1

35 57Wednesday, May 22, 2013

1.0

A

B

C

D

PL1

EMI@PL1

EMI@

C8B BPH 853025_2P

12

PC2

EMI@

100P_0402_50V8J

PL2

C8B BPH 853025_2P

1 2

EMI@

3

V I/O

2

Ground

1

V I/O

1 2

1

2

ADPIN PSID-3

PJPDC

1

2

3

4

5

1 1

5

6

GND

7

GND

ACES_50299-00501-003

CONN@

PL4

EMI@ PL4

EMI@

C8B BPH 853025_2P

1 2

BATT++BATT+

EMI@

PL3

SMB3025500YA_2P

BATT+

1 2

12

PC7

EMI@

0.01U_0402_25V7K

SMART

SMARTSMART Battery:

Battery:

Battery:Battery:

01.GND1

01.GND101.GND1

02.GND2

02.GND202.GND2

2 2

03.BAT_ALERT

03.BAT_ALERT03.BAT_ALERT

04.SYS_PRES

04.SYS_PRES04.SYS_PRES

05.BATT_PRS

05.BATT_PRS05.BATT_PRS

06.DAT_SMB

06.DAT_SMB06.DAT_SMB

07.CLK_SMB

07.CLK_SMB07.CLK_SMB

08.BATT1+

08.BATT1+08.BATT1+

09.BATT2+

09.BATT2+09.BATT2+

PBATT

GND GND

SUYIN_200028MR009G502ZL

CONN@

0.01U_0402_25V7K

1

2

3

BAT_ALERT

3

4

SYS_PRES

4

5

BATT_PRS

5

6

DAT_SMB

6

7

CLK_SMB

7

8

9

10 11

BATT++

12

PC8

EMI@

1000P_0402_50V7K

12

PSID

1

PD2

PD2 TVNST52302AB0_SOT523-3

TVNST52302AB0_SOT523-3

@EMI@

2

3

4

5

6

PC1

1000P_0402_50V7K

EMI@ P C1

EMI@

PD1

V I/O

V BUS

V I/O

AZC099-04S.R7G_SOT23

VIN

12

PC3

1000P_0402_50V7K

EMI@ P C3

EMI@

PD3

PD3 TVNST52302AB0_SOT523-3

TVNST52302AB0_SOT523-3

@EMI@

3

PR15

100_0402_5%

1 2

PR18

100_0402_5%

1 2

PR20

100_0402_5%

1 2

PR4

PSID@PR4

PSID@

33_0402_5%

PR8

PSID@

10K_0402_1%

1 2

12

+5VALW

12

PR3

2.2K_0402_5%

PSID@PR3

PSID@

1 3

D

S

D

S

PQ6

PSID@

PQ6

PSID@

FDV301N_G 1N SOT23-3

G

12

PC4

EMI@ P C4

EMI@

100P_0402_50V8J

PR16

10K_0402_1%

1 2

BATT_TEMP <30,37>

+3VALW

EC_SMB_CK1 <30,37>

EC_SMB_DA1 <30,37>

PR6

PSID@

1 2

100K_0402_1%

PSID-1

PR9

PSID@

15K_0402_1%

1 2

2

C

2

PQ5

B

MMST3904-7-F_SOT323~D

E

3 1

PSID-2

PSID@

PS_ID <30>

+3VALW

Other component (37.1)

ADP_I<30,37>

1 2

VCIN1_PH<30>

3 3

PR26

499K_0402_1%

1 2

ADP_I(with selector) Delay adaptor OC H_PROCHOT#

PR23

PR23 150K_0402_1%

150K_0402_1%

PR27

PR27 392K_0402_1%

392K_0402_1%

1 2

13

D

1 2

PC13

.1U_0402_16V7K@

2

G

S

PQ4

PQ4 2N7002W-T/R7_SOT323-3

2N7002W-T/R7_SOT323-3

2ms while hybrid power transition

65W#/90W <30>

PR30

160K_0402_1%

1 2

VCOUT1_PH <30>

PH1 under CPU bottem side : CPU thermal protection at 93 +/- 3 degree C

H_PROCHOT#

61

2

PQ3A

12

PC15

L2N7002DW1T1G_SC88-6

0.01U_0402_25V7K

L2N7002DW1T1G_SC88-6

H_PROCHOT# <30,6>

VCIN0_PH<30>

100K_0402_1%_TSM0B104F4251RZ

ECAGND< 30>

+EC_VCCA

PR24

12.1K_0402_1%

PH1

1 2

12

Adapter protection:

if battery removed, adaptor only, then trigger the H_PROCHOT#, keep @ in BOM since battery can not be removed by end user

H_PROCHOT#

PC14

.1U_0402_16V7K

1 2

BATT_PRS

4 4

3

5

PQ3B

4

12

PR32

100K_0402_1%

A

L2N7002DW1T1G_SC88-6

Battery protection:

asserts H_PROCHOT# when adaptor is unplugged, keep low for 10ms till SW PROCHOT# is issued by EC

PR31

1M_0402_1%

PR33

1M_0402_1%

VIN

1 2

12

3

5

4

PR28

10K_0402_1%

PQ2B

L2N7002DW1T1G_SC88-6

+3VALW

PC16

.1U_0402_16V7K

1 2

Erp lot6 Circuit

H_PROCHOT#

61

2

PQ2A

12

PQ2A

PR29

100K_0402_1%

L2N7002DW1T1G_SC88-6

B

ACIN <10,30,37,49>

PR1

@PR1

@

200K_0402_1%

PC5

@PC5

@

0.1U_0402_25V6

ERP_LOT6 <30>

12

PR2

2

10K_0402_1%

PR7

1M_0402_1%

61

PQ1A

L2N7002DW1T1G_SC88-6

VIN

12

PR5

3.3K_1206_5%~D

3

1 2

5

PQ1B

4

PR10

1M_0402_1%

1 2

L2N7002DW1T1G_SC88-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/21 2014/05/01

C

Compal Secret Data

Deciphered Date

2

-

JRTC

JRTC LOTES_AAA-BAT-054-K01

LOTES_AAA-BAT-054-K01

CONN@

1

+

Title

PWR_DCIN/BATT CONN/OTP

Size Document Number Rev

LA-9984P

Date: Sheet of

+RTCBATT

Compal Electronics, Inc.

36 57Wednesday, May 22, 2013

D

36 57Wednesday, May 22, 2013

0.4

A

PQ701

PR701

4.7_0402_1%

PC720

PQ701

CSD87312Q3E_SON8-4

D11D2

G2S

VIN

PR723

324K_0402_1%

1 2

EC_SMB_DA1<30,36>

EC_SMB_CK1<30,36>

1 2

3

4

PC702

0.1U_0402_25V6

1 2

12

PR703

4.02K_0402_1%

1 1

ACOFF<30>

2

G

VIN

12

PR720

13

D

PQ706

PQ706 2N7002KW_SOT323-3

2N7002KW_SOT323-3

S

12

3.3K_1206_5%~D

12

PC701

0.1U_0603_25V7K

For DT Mode

2 2

PC711

0.01UF_0402_25V7K

1 2

PR711

49.9K_0402_1%

1 2

REGN

12

PR707

ACIN <10,30,36,49>

ACIN

3 3

PR707

100K_0402_1%

12

PR712

158K_0402_1%

ADP_I<30,36>

100P_0402_50V8J

PC720 Close EC pin

B

Iada=0~3.33A(65W)

Iada=0~4.62A(90W)

ADP_I = 40*Iadapter*Rsense

PR721

4.02K_0402_1%

VIN

1 2

PR705

10_1206_5%

1 2

12

PC710

1U_0603_25V6K

VCC

CMSRC

ACDRV

ACDET

PR715 0_0402_5%~D@PR715 0_0402_5%~D@

1 2

PR714 0_0402_5%~D@PR714 0_0402_5%~D@

1 2

REGN

12

PR713

10K_0402_1%

C

CHG_B+

PR702

0.01_1206_1%

1

4

3

2

CSIP

PR717

PR717 0_0402_5%~D

0_0402_5%~D

@

1 2

1U_0603_25V6K

1 2

20

10

3

4

6

8

9

5

7

PC707

PU701

VCC

CMSRC

ACDRV

ACDET

SDA

SCL

ACOK

IOUT

CELL

BQ24717

PC717

0.1U_0402_25V6

1 2

2

ACP

TP

21

1

ACN

REGN

BTST

HIDRV

PHASE

LODRV

/BATDRV

EMI@

PL702

1UH_PCMB053T-1R0MS_7A_20%

1 2

CSIN

PR704

PR704 0_0402_5%~D

0_0402_5%~D

@

1 2

PC708

0.1U_0402_25V6

1 2

16

REGN

2.2_0603_5%

17

BST

18

DH_CHG

19

LX_CHG

15

14

GND

PR708 0_0402_5%~D@PR708 0_0402_5%~D@

1 2

13

SRP

PR710 0_0402_5%~D@PR710 0_0402_5%~D@

12

SRN

1 2

11

/BATDRV

12

PC704

PC703

10U_0805_25V6K

PC709

PC709 1U_0603_10V6K

1U_0603_10V6K

1 2

PD701

BAT54HT1G_SOD323-2~D

PR709

1 2

12

10U_0805_25V6K

12

BST_CHGA

@EMI@PC706

@EMI@

PC706

DL_CHG

12

0.1U_0603_25V7K

EMI@PC705

EMI@

12

PC705

2200P_0402_25V7K

PC721

0.047U_0603_25V7K

1 2

+VCHGR

1

+

PC724

2

100U_25V_M

/BATDRV

B+

5

4

5

4

5

PQ704

PQ703

MDU1516URH_POWERDFN56-8-5

123

PQ705

123

SIRA14DP-T1GE3_POWERPAK-SO8-5

PQ704

@

4

MDU1516URH_POWERDFN56-8-5

123

2.2UH_FDVE1040-H-2R2M-P3_14.2A_20%

12

PL701

1 2

PC715

@EMI@

680P_0402_50V7K

PR722

@EMI@

4.7_1206_5%

0.1U_0402_25V6

PR716

0.01_1206_1%

1

2

PC722

1 2

PR706

4.02K_0402_1%

PC718

10U_0805_25V5K~D

1 2

PC714

10U_0805_25V5K~D

1 2

D

PQ702

AO4407AL_SO8

1 2 3 6

4

12

Near PL701

4

3

PC716

10U_0805_25V5K~D

@

PC719

1 2

0.1U_0402_25V6

3S2P : CV = 13.3V CC: 1.54A 4S1P: CV = 17.7V CC: 1.1A

8 7

5

12

BATT+

PC712

@

10U_0805_25V5K~D

12

+VCHGR

12

PC713

10U_0805_25V5K~D

PC723

BATT_TEMP<30,36>

0.01U_0402_25V7K

for LEARN mode disable (pulse)

4 4

A

12

PR724

B

13

D

2

G

S

PQ708

1 2

100K_0402_1%

2N7002KW_SOT323-3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/21 2014/05/01

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR_CHARGER

LA-9984P

D

37 57Wednesday, May 22, 2013

0.4

A

1 1

B

PC102

@ PC102

@

100P_0402_50V8J

1 2

PR109

6.49K_0402_1%

1 2

VFB=2V

PR107

10K_0402_1%

1 2

+3VLP

C

PC109

1U_0603_10V6K

1 2

VFB=2V

PC108

@PC108

@

100P_0402_50V8J

1 2

PR104

15K_0402_1%

1 2

PR106

10K_0402_1%

1 2

D

Output capacitor ESR need follow below equation to make sure feed back loop stability ESR=20mV*L*fsw/2V

E

2 2

B+

3 3

4 4

EMI@

PL102

1UH_PCMB053T-1R0MS_7A_20%

1 2

3/5V_B+

12

PC113

0.1U_0402_25V6

@EMI@ PC113

@EMI@

12

PC115

PC114

10U_0805_25V6K

EMI@ PC114

EMI@

2200P_0402_50V7K

+3VALWP

3VALWP TDC 5.95A Peak Current 8.5A OCP current 10.2A TYP MAX H/S Rds(on): 22mohm , 30mohm L/S Rds(on):10.8mohm ,13.6mohm

3V_EN

5V_EN

2

3

2

3

PD101

EMI@

L03ESDL5V0CG3-2_SOT-523-3

1

PL100

2.2UH_PCMB063T-2R2MS_8A_20%

1

+

PC101

220U_6.3V_M+PC101

220U_6.3V_M

2

ESR=17m ohm

12

PR108

90.9K_0402_1%

CS2

5

CS2

6

EN2

7

PGOOD

8

TPS51225CRUKR_QFN20_3X3

SW2

9

VBST2

10

DRVH2

DRVL211VIN12VREG513VO114DRVL1

PC105

@ PC105

@

PJP100

@

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m PJP102

PJP102

@

1 2

PAD-OPEN 4x4m

FB_3V

3

4

VFB2

VREG3

12

PC106

1U_0603_25V6K

PU100

POK need pull high, it will pull high on VS transfer circuit

PQ101

3 5

241

MDV1528URH 1N PDFN33-8

12

PR113

4.7_1206_5%

@EMI@ PR113

@EMI@

PQ102

12

PC103

680P_0603_50V8J

@EMI@ PC103

@EMI@

VCOUT0_PH#<30>

3 5

241

MDV1525URH 1N PDFN33-8

3V_EN

5V_EN

PR102

2.2K_0402_5%

EC_ON<30>

2.2K_0402_5%

1 2

PC104

0.1U_0402_10V7K

1 2

PR100 0_0402_5%~D@PR100 0_0402_5%~D@

1 2

PR101 0_0402_5%~D@PR101 0_0402_5%~D@

1 2

12

PC100

4.7U_0603_6.3V6K

PR103

2.2_0402_5%

1 2

3/5V_B+

PU100

3V_EN

LX_3V

BST_3V

UG_3V

LG_3V

+3VALWP

Place PD101 close to PU100

A

B

C

PR105

1 2

84.5K_0402_1%

CS1

FB_5V

1

2

VL

21

CS1

PAD

VFB1

20

5V_EN

15

VCLK

VBST1

DRVH1

SW1

EN1

19

18

17

16

LX_5V

BST_5V

UG_5V

PR114

200_0402_5%

1 2

PR111

2.2_0402_5%

1 2

LG_5V

+5VALWP

Change to 4.7u for TPS51285

1U_0603_10V6K

PJP101

@

+3VALW

+5VALWP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m PJP103

PJP103

@

1 2

PAD-OPEN 4x4m

3/5V_B+

12

PC112

10U_0805_25V6K

@PR114

@

PC110

0.1U_0402_10V7K

1 2

5VALWP TDC 5.96A Peak Current 8.51A OCP current 10.2A TYP MAX H/S Rds(on):22mohm , 30mohm

+5VALW

2013/05/21 2014/05/01

L/S Rds(on):10.8mohm , 13.6mohm

Compal Secret Data

Deciphered Date

D

3 5

241

3 5

241

PQ103

MDV1528URH 1N PDFN33-8

2.2UH_PCMB063T-2R2MS_8A_20%

1 2

12

PR112

4.7_1206_5%

@EMI@ PR112

@EMI@

PQ104

12

PC111

MDV1525URH 1N PDFN33-8

680P_0603_50V8J

@EMI@ PC111

@EMI@

PL101

+5VALWP

1

+

PC107

220U_6.3V_M+PC107

220U_6.3V_M

2

ESR=17m ohm

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR_3.3VALWP/5VALWP

LA-9984P

E

38 57Wednesday, May 22, 2013

0.4

A

1 1

PJP400

@PJP400

@

2

@PJP600

@

112

JUMP_43X79

2

JUMP_43X79

112

22U_0805_6.3VAM

PC405

VGA@

PC605

+3VALW

2 2

PJP600

+3VALW

3 3

B

12

FB=0.6V

Note:Iload(max)=3A

12

FB=0.6V

Note:Iload(max)=3A

PU400

PGND

1

FB

SGND

2

PG

EN

3

IN

4

NC

PGND

SY8003DFC_DFN8_2X2

VGA@

PU600

PGND

1

FB

SGND

2

PG

3

IN

4

PGND

SY8003DFC_DFN8_2X2

C

PJP401

@

2

12

PL400

PR403

15K_0402_1%

PR402

10K_0402_1%

12

PL600

VGA@

20K_0402_1%

FB_1.8VSP

10K_0402_1%

12

1M_0402_5%

12

VGA@

PR603

VGA@

PR602

112

JUMP_43X79

1 2

PR404

12

Rup

12

Rdown

PJP601

112

JUMP_43X79

PR604

1M_0402_5%

12

Rup

12

Rdown

PR401

@PR401

@

0_0402_5%~D

SUSP#

Note:Iload(max)=2.5A

12

PC404

@

PR601

0_0402_5%~D

1 2

68P_0402_50V8J

VGA@PR604

VGA@

PC402

22U_0805_6.3VAM

2

@PR601

@

PXS_PWREN

Note:Iload(max)=2.5A

12

VGA@

12

PC604

PC602

68P_0402_50V8J

VGA@ PC602

VGA@

SUSP# <28,30,40>

+1.5VSP

12

PC400

22U_0805_6.3VAM

PXS_PWREN <10,11,43,44,50>

+1.8VSP

12

PC600

22U_0805_6.3VAM

VGA@ PC600

VGA@

+1.5VSP +1.5VS

+1.5VSP_ON

PC403

@

0.1U_0402_16V7K

9 8

7

6

LX

LX_1.5VSP

5

0.1U_0402_16V7K

1UH_PH041H-1R0MS_3.8A_20%

1 2

12

PR405

4.7_0603_5%

FB_1.5VSP

@EMI@ PR405

@EMI@

12

PC401

@EMI@ PC401

@EMI@

680P_0402_50V7K

+1.8VSP +1.8VS

+1.8VSP_ON

PC603

@

0.1U_0402_16V7K

9 8

7

EN

6

LX

NC

LX_1.8VSP

5

0.1U_0402_16V7K

1UH_PH041H-1R0MS_3.8A_20%

1 2

12

PR605

4.7_0603_5%

@EMI@ PR605

@EMI@

12

PC601

@EMI@ PC601

@EMI@

680P_0402_50V7K

D

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/21 2014/05/01

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR_1.5VSP / 1.8VSP

LA-9984P

D

39 57Wednesday, May 22, 2013

0.4

5

D D

C C

PL302

EMI@ PL302

EMI@

SUPPRE_ FBMA-L11-453215-800LMA90T_1812

1 2

B+

LDO_3V

12

PR304

@ PR304

@

0_0402_5%

ILMT_1.05V LDO_3V

12

PR306

@ PR306

@

0_0402_5%

B B

The current limit is set to 6A, 8A or 12A when this pin is pull low, floating or pull high

12

PC303

EMI@ PC303

EMI@

2200P_0402_50V7K

PC304

@EMI@ PC304

@EMI@

+3VS

12

PC305

10U_0805_25V6K

0.1U_0402_25V6

1 2

PR308

10K_0402_5%

4

EN pin don't floating If have pull down resistor at HW side, pls delete PR301

12

1M_0402_1%

1M_0402_1% PR301

PR301

PU300

8

B+_1.05V

12

PC306

10U_0805_25V6K

ILMT_1.05V

+1.05V_PGOOD

+1.05V_PGOOD<30>

IN

9

GND

3

ILMT

2

PG

SY8206DQNC_QFN10_3X3

1

PR303

@ PR303

EN

BS

LX

FB

BYP

LDO

@

1 2

6

BST_1.05V

10

LX_1.05V

4

7

5

12

PC312

Pin 7 BYP is for CS. Common NB can delete +3VALW and PC313

0_0603_1%

4.7U_0603_6.3V6K

0.1U_0603_25V7K

12

PC313

4.7U_0603_6.3V6K

1 2

PC302

+3VALW

@PR300

@

0_0402_5%~D

1 2

12

@ PC300

@

0.22U_0402_10V6K

PR300

PC300

3

@EMI@ PR302

@EMI@

SUSP# <28,30,39>

@EMI@ PC301

@EMI@

PR302

680P_0603_50V7K

SNB_1.05V

PL301

1 2

680P_0603_50V7K

1 2

4.7_1206_5%

1 2

1UH_PCMB063T-1R0MS_12A_20%

Rup

FB = 0.6V

Rdown

PC301

12

PR305

PC307

15K_0402_1%

12

PR307

20K_0402_1%

VFB=0.6V Vout=0.6V* (1+R up/Rdown) Vout=1.05V

12

PC309

PC308

47U_0805_6.3V6M

330P_0402_50V7K

2

+1.05VSP

PJP300

@PJP300

@

112

JUMP_43X118

2

1

+1.05VS

+1.05VSP

12

PC311

PC310

47U_0805_6.3V6M

22U_0805_6.3VAM

+1.05VSP TDC 5A Peak Current 6. 6A OCP current 8A

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2013/05/21 2014/05/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

PWR_+VCCIO

1

40 57Wednesday, May 22, 2013

0.4

5

D D

EMI@

PL201

SUPPRE_ FBMA-L11-453215-800LMA90T_1812

B+

SUPPRE_ FBMA-L11-453215-800LMA90T_1812

+1.35VP

C C

B B

PL201

1 2

1UH_PCMB063T-1R0MS_12A_20%

1

+

PC213

2

330U_2.5V_M

1.35VP TDC 6A Peak Current 8A OCP current 10A

PL200

1 2

12

PC208

0.1U_0402_25V6

@EMI@ PC208

@EMI@

PC207

@EMI@ PC207

@EMI@

680P_0402_50V7K

PR203

@EMI@ PR203

@EMI@

4.7_1206_5%

4

1.35V_B+

PC201

2200P_0402_50V7K

EMI@ PC201

EMI@

3

PR200

2.2_0603_5%

1 2

PR206

5.1_0603_5%

1 2

PC209

1U_0603_10V6K

BST_1.35V

11.8K_0402_1%

1 2

12

0.675V_DDR_VTT_ON<17>

PR205

PC204

1U_0603_10V6K

1 2

VDD_1.35V

SYSON<30>

+5VALW

1.35V_B+

12

PC206

PC212

10U_0805_25V6K

5

PQ200

AON7408L

123

12

AON7506

PQ201

5

123

4

12

0.1U_0603_25V7K

+5VALW

PC200

DL_1.35V

CS_1.35V

15

14

13

12

11

PR208

1M_0402_1%

1 2

@PR201

@

0_0402_5%~D

1 2

BOOT_1.35V

DH_1.35V

SW_1.35V

LGATE

PGND

CS

VDDP

VDD

16

17

PHASE

UGATE

RT8207MZQW_WQ FN20_3X3

PGOOD

TON

9

10

TON_1.35V

PR201

PC202

@PC202

@

0.1U_0402_10V7K

PR202

@PR202

@

0_0402_5%~D

1 2

18

BOOT

S5

8

EN_1.35V

12

20

19

VTT

VLDOIN

VTTGND

VTTSNS

VTTREF

VDDQ

FB

S3

6

7

EN_0.675VSP

12

PC203

@PC203

@

0.1U_0402_10V7K

PU200

FB_1.35V

21

PAD

1

2

3

GND

4

5

VTTREF_1.35V

54.9K_0402_1%

1 2

12

PR204

68.1K_0402_1%

2

0.675Volt +/- 5% TDC 0.7A Peak Current 1A

+1.35VP

+0.675VSP

12

PC205

PC211

10U_0805_6.3V6K

12

PC210

0.033U_0402_16V7K

+1.35VP

PJP200

@PJP200

@

+1.35VP +1.35V

+0.675VSP +0.675VS

112

JUMP_43X118

PJP201

@PJP201

@

112

JUMP_43X118

PJP203

@PJP203

@

2

JUMP_43X39

2

112

PR207

+1.35VP

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/21 2014/05/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR_+1.35VP/0.675VSP

LA-9984P

1

41 57Wednesday, May 22, 2013

0.4

5

VREF_CPU

@

PR514

100K_0402_1%_TSM0B104F4251RZ

B value:4250K

1 2

75_0402_1%

D D

PR513

39K_0402_5%

1 2

PH502

PR512

10K_0402_5%~D

12

Near PU502.

PC509

1 2

PC508

4700P_0603_50V7K

12

1000P_0402_50V7K

IMON_CPU

4

@

PR507

PR501

1 2

523K_0402_1%

PR503

1 2

75K_0402_1%

PR507

75_0402_1%

B-RAMPOCP_CPU

PR509

150K_0402_1%

PR504

1 2

F-IMAX

1 2

499K_0402_1%

PR505

75K_0402_1%

1 2

O-USR

3

PR502

1 2

9.31K_0402_1%

PR506

1 2

150K_0402_1%

+VCC_PWR_SRC

2

1

EMI Part (47.1)

PL501

EMI@PL501

1 2

EMI@

SUPPRE_ FBMA-L11-453215-800LMA90T_1812

EMI@PC521

EMI@

1

@EMI@PC519

@EMI@

12

PC517

PC518

10U_0805_25V6K

12

PC521

PC519

0.1U_0402_25V6

0.1U_0402_25V6 2200P_0402_25V7K

2200P_0402_25V7K

1

+

PC515

PC516

100U_25V_M

2

100U_25V_M

2

B+

SLEWA_CPU

C C

Check are there a pair 100Ω

VSSSENSE<13,15>

VCCSENSE<13>

B B

at HW side and close to CPU.

PC513

@PC513

@

390P_0402_50V7K

PR532

10K_0402_1%

1 2

PR529

5.76K_0402_1%

12

THERM_CPU

+VCC_PWR_SRC VBAT_CPU

CSP1_CPU

CSN1_CPU

+3VS

3.65K_0402_1%

0.33U_0402_10V6K

PC514

1500P_0402_50V7K

1 2

0.33U_0402_10V6K

+5VS

VR_HOT#<30>

VR_SVID_CLK<13>

VR_SVID_ALRT#<13>

VR_SVID_DAT<13>

PR508

10K_0402_5%~D

1 2

PR531

12

PC507

12

17

18

19

20

21

22

23

24

DROOP_CPU

COMP_CPU

VREF_CPU

PR519

10_0603_1%

1 2

16

VBAT

CSP1

CSN1

CSN2

TPS51622RSM_QFN32_4X4

CSP2

PU3

N/C

GFB

VFB

DROOP

25

1U_0603_10V6K

15

26

SLEWA

COMP

PC505

VR_ENABLE

14

13

12

11

10

9

IMON

OCP-I

O-USR

PU501

F-IMAX

VCLK

ALERT#

32

1 2

56_0402_1%

VR_ON

PWM1

PWM2

PGOOD

PC506

47P_0402_50V8J

PR533

SKIP#

VDD

VDIO

8

7

SKIP#

6

5

4

N/C

3

2

1

PAD

33

VR_SVID_DAT

VR_SVID_ALRT#

VR_SVID_CLK

12

PR526

54.9_0402_1%

B-RAMP

V5A

GND

VR_HOT#

31

28

29

30

V5A_CPU

12

1_0603_5%

12

PC504

PC504 1U_0402_6.3V6K

1U_0402_6.3V6K

PR535 0_0402_5%~D

0_0402_5%~D

1 2

PR516

12

@PR535

@

12

@

PR510

PR510 75_0402_1%

75_0402_1%

PR528

PR528 75_0402_5%

75_0402_5%

@

THERM

VREF

27

+5VS

12

+3VS

PR522

@PR522

@

0_0402_5%~D

1 2

PC522

EMI@PC522

EMI@

0.1U_0402_10V7K

SKIP#1

12

PR524

10K_0402_1%~D

12

PR530

PR530 130_0402_1%

130_0402_1%

PC503

PC503 1U_0603_10V6K

1U_0603_10V6K

@

0_0402_5%

12

+1.05VS

VR_ON <13,30>

PC502

1000P_0402_50V7K

1 2

TI recommend 1nF

PR540

12

+3VS

PC510

0.082U_0402_16V7K

12

PC512

PC512 .1U_0402_16V7K

.1U_0402_16V7K

@

PC501

IMVP_PWRGD <30>

H_VR_READY <13>

CSP1_CPU

0.082U_0402_16V7K

1 2

CSN1_CPU

PR536

PC511

1 2

0.1U_0402_25V6

12

2.2_0603_5%

Place PC523 close to PR540

1 2

PWM1

PU502

9

PGND2

8

PWM

7

VSW

BOOT

PGND1

6

BOOT_R

5

SKIP#

CSD97374CQ4M_SON8_3P5X4P5

VIN

SKIP#1

IMVP_PWRGD

12

PH501

PH501 10K_0402_1%_TSM0A103F34D1RZ

10K_0402_1%_TSM0A103F34D1RZ

B value:3435K

Near PL502.

12

PR515

3.01K_0402_1%

4 3 2

VDD

1

PC523

EMI@PC523

EMI@

0.1U_0402_10V7K

SW_CPU2PWM1

12

PC520

12

@EMI@ PC520

@EMI@

PR534

4.7_1206_5%

@EMI@ PR534

@EMI@

PR518

2.32K_0402_1%

1 2

12

16.5K_0402_1%

0.22UH_PCMB104T-R22MS_35A_20%

1

2

680P_0402_50V7K

PR517

CPU_CORE TDC 10A Peak Current 32A OCP current 40A Load line -2mV/A

PL502

4

3

+CPU_CORE

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/21 2014/05/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR_VCORE

LA-9984P

1

42 57Wednesday, May 22, 2013

0.4

5

TDC=9A

D D

Peak Current=13A OCP=16A

PR1102

VGA@PR11 02

VGA@

154K_04 02_1%

PR1103

@P R1103

@

0_0402_ 5%~D

PXS_PW REN

C C

B B

1 2

PC1104

@ PC1104

@

VENUS@_ EMI@ PL12 01

VENUS@_ EMI@

SUPPRE_ FBMA-L11-45321 5-800LMA90T_1 812

B+

PL1201

1 2

LDO_3V_VDDCI

12

VENUS@

PR1203

0_0402_ 5%

ILMT_VDDC I LDO_3V_ VDDCI

12

PR1202

@ PR1202

@

0_0402_ 5%

The current limit is set to 8A, 12A or 16A when this pin is pull low, floating or pull high

A A

1 2

12

0.1U_0402_16V7K

12

PC1203

PC1209

2200P_0402_50V7K

@EMI@ PC1203

@EMI@

VENUS@_EMI@ PC1209

VENUS@_EMI@

12

PR1108 10K_040 2_1%

10K_040 2_1%

12

10U_0805_25V6K

0.1U_0402_25V6

TRIP_+1.2V SP

12

PR1105

470K_04 02_1%

VGA@PR11 08

VGA@

12

PC1202

VENUS@

+3VS

EN_+1.2V SP

FB_+1.2V SP

RF_+1.2V SP

VGA@PR11 05

VGA@

PR1107

9.09K_04 02_1%

1 2

12

PC1204

10U_0805_25V6K

VENUS@

4

12

@

PR1110

PR1110 100K_04 02_5%

100K_04 02_5%

PU1100

VGA@PU11 00

VGA@

1

PGOOD

2

TRIP

3

EN

4

VFB

5

TST

TPS5121 2DSCR_SON10_ 3X3

VGA@PR11 07

VGA@

B+_VDDC I

ILMT_VDDC I

10

VBST

DRVH

DRVL

8

9

3

2

BST_+1.2 VSP

9

UG_+1.2V SP

8

SW_ +1.2VSP

SW

7

V5IN

6

LG_+1.2V SP

11

TP

PU1200

IN

EN

BS

LX

GND

FB

BYP

ILMT

PG

LDO

SY8208DQN C_QFN10_3X3

VENUS@

Pin 7 BYP is for CS. Common NB can delete +3VALW and PC1205

3

VGA@

PR1101

2.2_0603 _5%

1 2

VGA@

PC1103

0.1U_060 3_25V7K

1 2

+5VALW

12

VGA@

PC1105

PC1105 1U_0603 _10V6K

1U_0603 _10V6K

12

1M_0402 _1%

1M_0402 _1% PR1201

PR1201

VENUS@

1

6

BST_VDD CI

10

4

7

5

12

VENUS@

PR1200

@P R1200

@

0_0603_ 1%

1 2

LX_VDDC I

PC1213

4.7U_0603_6.3V6K

0.1U_060 3_25V7K

12

PC1205

4.7U_0603_6.3V6K

VENUS@ PC1205

VENUS@

PC1210

1 2

+3VALW

VFB=0.6V Vout=0.6V* (1+Rup/Rdown)

4

PR1206

@P R1206

@

0_0402_ 5%~D

1 2

12

PC1200

@ PC1200

@

0.22U_04 02_10V6K

FB = 0.6V

+1.2VSP_ B+

5

VGA@

PQ1100

PQ1100 AON7408 L

AON7408 L

123

5

VGA@

PQ1101

PQ1101 AON7506

AON7506

123

@EMI@ PR120 7

@EMI@

4.7_1206 _5%

1 2

VENUS@ PL12 00

VENUS@

1UH_PCM B063T-1R0MS_1 2A_20%

Rdown

12

PC1101

PC1100

0.1U_0402_25V6

0.1U_0402_25V6 2200P_0402_50V7K

@EMI@ PC1100

@EMI@

PXS_PW REN

PR1207

1 2

2200P_0402_50V7K

VGA@_EMI@ PC1101

VGA@_EMI@

VGA@ PL11 01

VGA@

1UH_PCM B063T-1R0MS_1 2A_20%

1 2

12

PR1104

4.7_1206 _5%

12

PC1106

680P_04 02_50V7K

@EMI@ PC121 2

@EMI@

680P_06 03_50V7K

1 2

SNB_VDD CI

PL1200

Rup

PR1209

VENUS@ PR12 09

VENUS@

10K_040 2_1%

1 2

PR1211

1 2

120K_04 02_1%

12

VENUS@

PR1204

PR1204 20K_040 2_1%

20K_040 2_1%

2

VGA@_EM I@ PL1100

VGA@_EM I@

HCB2012 KF-121T50_080 5

12

PC1102

10U_0805_25V6K

VGA@ PC1102

VGA@

PL1101

@EMI@PR11 04

@EMI@

@EMI@PC11 06

@EMI@

PXS_PWREN <10,11,39,44,50>

PC1212

12

PR1208

10_0402_5%

PR1208

10_0402_5%

VENUS@

PR1210

@P R1210

@

0_0402_ 5%~D

VENUS@PR1211

VENUS@

0_0402_ 5%~D

1 2

13

D

2

G

S

PQ1201

VENUS@

PQ1201

VENUS@

2N7002W -T/R7_SOT32 3-3

1

PL1100

1 2

+1.35VGPUP +1.35VS_VGA

B+

PJP1100

@P JP1100

@

112

JUMP_43 X118

PJP1101

@P JP1101

@

112

JUMP_43 X118

2

+1.35VGPUP

1

+

PC1108

2

330U_2.5V_M

VGA@

VDDCI_VID (GPIO_6)

0.95VHigh

Low 0.9V

+VDDCIP

PJP1200

@P JP1200

@

112

JUMP_43 X118

2

+VDDCI

+VDDCIP

12

VENUS@PR1212

VENUS@

12

+VDDCIP TDC 7A

PC1206

PC1201

22U_0805_6.3VAM

VENUS@ PC1201

VENUS@

12

+3VGS

12

PR1213 10K_040 2_5%

10K_040 2_5%

12

PR1214 100K_04 02_5%

100K_04 02_5%

VENUS@

22U_0805_6.3VAM

Peak Current 13A OCP current 16A

VENUS@PR1213

VENUS@

@P R1214

@

GPU_GPIO6 <49>

12

PC1207

PC1211

47U_0805_6.3V6M

VENUS@ PC1207

VENUS@

VENUS@ PC1211

VENUS@

VDDCI_SEN <52>

PR1212 10K_040 2_5%

10K_040 2_5%

12

PC1214

@ PC1214

@

4700P_0 402_25V7K

Vout=0.9V

Security Class ification

2013/05/ 21 2014/05/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/ 21 2014/05/ 01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docu ment Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PWR_+1.35VGPU/VDDCIP

LA-9984P

43 57Wednesd ay, May 22, 2013

1

0.4

5

VGA@

PR822

1_0603_5%

PC818

PR817

@PC809

@

VGA@PC818

VGA@

12

VGA@PR817

VGA@

1.2V

1.175V

1.15V

1.125V

1.1V

1.075V

1.05V

1.025V

1V

0.975V

0.95V

0.925V

0.9V

0.875V

0.85V

0.825V

12

+3VS

12

62881_COMP62881_COMP

PR815

VGA@ PR815

VGA@

12

@P R808

@

PR808

12

PC811 1U_0603_10V6K

1U_0603_10V6K

62881_FB62881_FB

62881_VW62881_VW

62881_RBIAS

12

47K_0402_1%

10K_0402_1%

VGA@PC811

VGA@

7

6

5

4

3

2

1

VSEN

FB

COMP

VW

RBIAS

PGOOD

CLK_EN#

+5VALW

D D

@

PR833

12

PR845

@PR845

10_0402_5%

VSSSENSE_VGA<52>

VCCSENSE_VGA<52>

+VGA_CORE

C C

GPU_VID5 (GPIO_10)

B B

@

0_0402_5%~D

PR846

@PR846

@

0_0402_5%~D

@

PR820

12

10_0402_5%

PC817

VGA@ PC817

VGA@

1000P_0402_50V7K

GPU_VID4

GPU_VID3

(GPIO_14)

(GPIO_15)

1 10 0 0

12

PR813

25W@PR813

25W@

909_0402_1%

12

GFX_FB-2

PR818 715_0402_1%

715_0402_1%

PC816

1 2

1000P_0402_50V7K

1 2

PC813 330P_0402_50V7K

330P_0402_50V7K

12

VGA@PR818

VGA@

DGPU_PWROK<10,30>

GPU_VID2 (GPIO_16)

VGA@PC816

VGA@

@PC813

@

PR821

97.6K_0402_1%

1 2

VGA@ PC806

VGA@

390P_0402_50V7K

PC814

VGA@ PC814

VGA@

56P_0402_50V8

1 2

GPU_VID1 (GPIO_20)

25W@PR821

25W@

GFX_FB-1

1 2

PC806

12

PC809 330P_0402_50V7K

330P_0402_50V7K

1000P_0402_50V7K

8.06K_0402_1%

Core Voltage Le vel

0 1 1 0 1

0 1 1 1 0

11110

00001

11 000

000 11

111 00

000 11

111 00

0

111 0

0

A A

11

0 0 1

1

011

1111

0 0

1 0

1111 0

01 11 0.8V

0

1 1 1 10 0.775V

5

4

@

PR823

ISUM-

ISUM+

10

9

8

29

RTN

ISUM

AGND

ISUM+

PU800

VGA@PU800

VGA@

ISL62881CHRTZ-T_QFN28_4X4

28

12

VGA@PR842

VGA@

62881_VR_ON

62881_VID6

PR842

1K_0402_1%

+3VS

+3VGS

4

GPU_B+62881_VDD

0_0603_1%

1 2

12

+5VALW

PC810

0.22U_0603_25V7K

12

VGA@ PC810

VGA@

62881_VIN

11

12

13

VIN

VDD

VID5

25

62881_VID3

62881_VID4

62881_VID5

Load line

PR824

PR824 0_0402_5%

0_0402_5%

LL@

BST_VGA_CORE

14

IMON

BOOT

UGATE

PHASE

VSSP

LGATE

VCCP

VID2

VID323VID424VID626VR_ON27DPRSLPVR

22

62881_VID2

1 2

Initial voltage:0.85V(Venus)

0.9V(Sun)

15

16

17

18

19

20

VID0

21

VID1

12

PC869

VGA@ PC869

VGA@

PR828

10K_0402_1%

10K_0402_1% PR819

10K_0402_1%

10K_0402_1% PR826

10K_0402_1%

10K_0402_1% PR834

10K_0402_1%

10K_0402_1% PR835

10K_0402_1%

10K_0402_1% PR836

10K_0402_1%

PR837

10K_0402_1%

10K_0402_1% PR838

10K_0402_1%

10K_0402_1% PR839

10K_0402_1%

10K_0402_1% PR840

10K_0402_1%

UG_VGA_CORE

SW_VGA_CORE

62881_VCCP

62881_VID0

62881_VID1

0.1U_0402_10V7K

@PR828

@

VGA@PR819

VGA@

VENUS@PR826

VENUS@

SUN@PR834

SUN@

@PR835

@

VGA@PR836

VGA@

VGA@PR837

VGA@

@PR838

@

VGA@PR839

VGA@

@PR840

@

@PR802

@

0_0603_1%

1 2

SUN XT VENUS PRO/XT

No need Need

pop un-pop

PR802

1 2

12

PR814 0_0603_1%@ PR814 0_0603_1%@

PC803

2.2U_0603_6.3V6K

VGA@PC803

VGA@

12

GPU_VID1

GPU_VID2

GPU_VID3

GPU_VID4

GPU_VID5

12

PR8110_0402_5%~D @PR8110_0402_5%~D @

12

PR8100_0402_5%~D @PR8100_0402_5%~D @

12

PR8120_0402_5%~D @PR8120_0402_5%~D @

12

PR8070_0402_5%~D @PR8070_0402_5%~D @

12

PR8090_0402_5%~D @PR8090_0402_5%~D @

12

PR8060_0402_5%~D @PR8060_0402_5%~D @

12

PR8040_0402_5%~D @PR8040_0402_5%~D @

PR8030_0402_5%~D @PR8030_0402_5%~D @

1 2

PC807

VGA@PC807

VGA@

0.1U_0603_25V7K

+5VALW

3

GPU_VID1 <49> GPU_VID2 <49> GPU_VID3 <49> GPU_VID4 <49> GPU_VID5 <49>

PXS_PWREN <10,11,39,43,50>

PJP1301

+3VALW

PJP1301

2

JUMP_43X79

PXS_PWREN

+VGA_PCIEP +VGA_PCIE

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PL800

VGA@_EMI@PL800

B+

VGA_CORE Frequency 300kHz TDC 23A(25W)/33A(32W) Peak Current 30A(25W)/47A(32W) OCP current 36A(25W)/56A(32W) TYP MAX H/S Rds(on) :12.2mohm , 15mohm L/S Rds(on) :2.75mohm , 3.5mohm Choke DCR 1.1mohm(Typ)/1.3mohm(Max) Load line : -1.5mV/A

PR813

1.4K_0402_1%

@

112

PR1300

VGA@ PR1300

VGA@

1 2

200K_0402_5%

47K_0402_5%

32W@PR813

32W@

EN_PCIE

PR1304

@PR1304

@

PCIE_B+

VGA@

12

PC1301

PC1301 22U_0805_6.3VAM

22U_0805_6.3VAM

12

FBMA-L11-453215-800LMA90T_1812

PR821

143K_0402_1%

12

1 2

32W@PR821

32W@

VGA@

10

9

8

5

VGA@PC1307

VGA@

PC1307

0.1U_0402_10V7K

PU1300

PVIN

SVIN

EN

VGA@_EMI@

11

PR825

1.5K_0402_1%

4

PG

TP

SS

7

12

Vout=0.95V

@

PJP1300

2

112

JUMP_43X79

Compal Secret Data

Issued Date

2013/05/21 2014/05/01

Compal Secret Data

2

12

PC831

PC832

@EMI@

0.1U_0402_25V6K~D

32W@

5

PQ800

4

123

VGA@

5

PQ801

4

321

32W@PR825

32W@

2

LX_PCIE

LX

3

LX

6

FB_PCIE

FB

LX

SY8036LDBC_DFN10_3x3

1

PC1302

VGA@ PC1302

VGA@

0.1U_0402_10V7K

PR1301

VGA@ PR1301

VGA@

10K_0402_1%

Deciphered Date

2

1

GPU_B+

VGA@

12

VGA@_EMI@

2200P_0402_50V7K~D

GPU_B+

PR813

MDU1516URH 1N POWERDFN56-8

PR805

MDU1511RH 1N POWERDFN56

@EMI@ PR805

@EMI@

VGA@PR1302

VGA@

12

PR821

PR825

12

PC815

680P_0603_50V7K

12

@EMI@ PC815

@EMI@

4.7_1206_5%

ISUM+

ISUM-

VGA@ PL1300

VGA@

0.47UH_PCMB063T-R47MS_18A_20%

1 2

12

PR1303

@EMI@ PR1303

@EMI@

SNUB_PCIE

12

PC1304

@EMI@ PC1304

@EMI@

+VGA_PCIEP

VGA@

5

PQ803

4

123

MDU1516URH 1N POWERDFN56-8

VGA@

5

PQ802

4

321

MDU1511RH 1N POWERDFN56

PR1302

5.9K_0402_1%

PC1306

VGA@

12

22P_0402_50V8J

12

PC804

10U_0805_25V6K

25W 32W

909

97.6K

976

0.36UH_MMD-12CE-R36M-M1L_34A_20%

12

VGA@PR829

VGA@

PR829

3.65K_0402_1%

PL1300

12

4.7_1206_5%

PC1300

22U_0805_6.3VAM

VGA@ PC1300

VGA@

680P_0402_50V7K

Title

PWR_VGA_CORE/PCIE

Size Document Number Rev

LA-9984P

Date: Sheet

Date: Sheet of

VGA@

12

PC805

PC808

10U_0805_25V6K

1.4K

143K

+VGA_CORE

1.5K

1 2

PL802

VGA@ PL802

VGA@

1 2

PR816

2.61K_0402_1%

+VGA_PCIE TDC 3A Peak Current 4.2A OCP current 6A

Compal Electronics, Inc.

ISUM-2

VGA@

1 2

PR827

VGA@PR827

VGA@

11K_0402_1%

1 2

PC819

0.15U_0402_10V6K

1 2

PC820

0.033U_0402_16V7K

12

PC1303

22U_0805_6.3VAM

VGA@ PC1303

VGA@

1

1 2

PH800

10KB_0402_5%_ERTJ0ER103J

VGA@PC819

VGA@

VGA@PC820

VGA@

12

PC1308

PC1305

22U_0805_6.3VAM

VGA@ PC1308

VGA@

VGA@ PC1305

VGA@

0_0402_5%~D

12

@

PR830

VGA@PH800

VGA@

ISUM-1

1 2

+VGA_PCIEP

22U_0805_6.3VAM

of

44 57Wednesday, May 22, 2013

VGA@

1 2

PC821

PR825

976_0402_1%

25W@ PR825

25W@

0.4

.1U_0402_16V7K

5

+CPU_CORE

4

3

2

1

+VGA_CORE

D D

C C

12

PC902

PC901

22U_0805_6.3V6M

12

PC909

PC910

22U_0805_6.3V6M

12

PC918

PC917

22U_0805_6.3V6M

12

PC904

PC903

22U_0805_6.3V6M

12

PC912

PC911

22U_0805_6.3V6M

12

PC920

PC919

22U_0805_6.3V6M

12

PC906

PC905

22U_0805_6.3V6M

12

PC914

PC913

22U_0805_6.3V6M

12

PC921

PC922

22U_0805_6.3V6M

12

PC908

PC907

22U_0805_6.3V6M

12

22U_0805_6.3V6M

12

22U_0805_6.3V6M

12

PC915

PC916

22U_0805_6.3V6M

PC923

22U_0805_6.3V6M

1

PC841

PC840

2

1U_0402_6.3V6KVGA@

1

PC848

PC849

2

1U_0402_6.3V6KVGA@

1

PC857

PC858

2

1U_0402_6.3V6KVGA@

1

PC868

PC867

2

10U_0603_6.3V6MVGA@

1

PC846

2

1U_0402_6.3V6KVGA@

1

PC853

2

1U_0402_6.3V6KVGA@

1

PC863

2

1U_0402_6.3V6KVGA@

1

PC871

PC847

2

1U_0402_6.3V6KVGA@

1

PC855

PC854

2

1U_0402_6.3V6KVGA@

1

PC865

PC864

2

1U_0402_6.3V6KVGA@

PC836

25W@PC836

25W@

330U_D2_2V_Y

1

PC872

2

1U_0402_6.3V6KVGA@

1

PC856

2

1U_0402_6.3V6KVGA@

1

PC866

2

1U_0402_6.3V6KVGA@

1

PC836

+

2

32W@

470U_D2_2VM_R4.5M~D

PC837

25W@PC837

25W@

330U_D2_2V_Y

1

PC837

+

2

32W@

470U_D2_2VM_R4.5M~D

PC838

330U_D2_2V_Y

1

PC839

PC838

+

2

32W@

470U_D2_2VM_R4.5M~D

PC839

25W@PC839

25W@PC838

25W@

330U_D2_2V_Y

1

PC842

2

1U_0402_6.3V6KVGA@

1

PC850

2

1U_0402_6.3V6KVGA@

1

PC859

2

1U_0402_6.3V6KVGA@

1

PC870

2

10U_0603_6.3V6MVGA@

1

PC844

PC845

PC843

2

1U_0402_6.3V6KVGA@

1

PC852

PC873

PC851

2

1U_0402_6.3V6KVGA@

1

PC860

PC861

PC862

2

1U_0402_6.3V6KVGA@

1

PC835

2

10U_0603_6.3V6MVGA@

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/21 2014/05/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR_PROCESSOR DECOUPLING

LA-9984P

1

45 57Wednesday, May 22, 2013

0.4

5

4

3

2

1

D D

Power block

CPU OTP

Page 45

Turn Off

DC IN

C C

Input Switch

Page 46

CHARGER

B+

+3VALWP: TDC:5.4A +5VALWP: TDC:5.6A TPS51225CRUKR

+3VALW

+1.8VSP: TDC:2.5A SY8003DFC

EC_ON

Page 47

PXS_PWREN

Page 48

CC:0A~1A(4cell) or 2.1A(6cell) CV:17.7V(4cell) / 13.3V(6cell) BQ24717

Page 46

Battery

B B

PXS_PWREN

VR_ON

+VGA_CORE TDC: 23A / 33A ISL62881CHRTZ-T

+CPU_CORE TDC: 14A TPS51622RSM

Page 53

Page 51

+3VALW

+1.5VSP: TDC:2.5A SY8003DFC

Page 48

+VGA_PCIEP: TDC:3A SY8036LDBC

Page 53

+VDDCIP: TDC:7A SY8208DQNC

Page 52

+VCCIO: TDC:5A SY8206DQNC

Page 49

+1.35VP/+0.675VSP: TDC:6A/0.7A RT8207MZQW

Page 50

SUSP#

PXS_PWREN

SUSP#

SYSON

+1.35VGPUP: TDC:9A TPS51212DSCR

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/21 2014/05/01

Compal Secret Data

Deciphered Date

Page 52

2

PXS_PWREN

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR_POWER BLOCK DIAGRAM

LA-9984P

1

0.4

46 57Wednesday, May 22, 2013

0.4

5

D D

C C

B B

P a g e# T i tle

Item

Item Issue D escription

P a g e#Pa ge #

ItemItem

1 37 CHARG ER 13/01/30 Morri s adjust design p arameter from vendor recommen d delete PD702

2 42 VCORE 13/0 1/30 Morris adju st design para meter from vend or recommend chan ge PC509 from 0.1uF to 1000pF

3 36 DCIN/ BATT CONN/OTP 13/ 01/30 Morris cha nge from ESD r equest change PD1 from SC300002E00 t o SC300001G00

4 38 3.3VA LWP/5VALWP 13/02/01 Morris add ESD dio de from ESD re quest add PD101(SCA00 002A00) 0.3

5 42 VCORE 13/0 2/21 Morris adju st design para meter from fine tune result chan ge PR501 from 422K to 523K

6 44 VGA_C ORE/PCIE 13/02/21 Morris

7 44 VGA_C ORE/PCIE 13/03/05 Morris adjust output voltage from vender r equest 0.3unpop PR826 and pop PR834 (on ly for Sun XT)

8 13/03/28 Mor ris37

38

39

40

41

42

369 DCIN/BATT CONN/ OTP 13/04/09 Mor ris design chang e for solve iss ue unpop PR1 and P C5

41 +1.35VP/0.675 VSP10

11 1 .5VSP/1.8VSP39

43 +1.35VGPU/VDD CI

44 VGA_CORE/PCIE

12 43 +1.35VGPU/V DDCI 13/04/09

36 DCIN/BATT CON N/OTP 13/04/12

15 42 VCORE 13/04/15 Morris EMI reques t pop PC522 and a dd PC523 0.1uF 0.4

T itle

T itleT itle

CHARGER

3.3VALWP/5VALWP

1.5VSP/1.8VSP

+VCCIO

+1.35VP/0.675VS P

VCORE

+1.35VGPU/VDDCI43

D ate

D ateD ate

13/04/09 Morri s part shortage i ssue change PQ201 an d PQ1101 from SB00000T600 to SB000010A00

13/04/09 ve rify function ok, so delete 0 ohm to short unpop PR601,PR802,PR 803,PR814,PR82 3,PR830,PR845,P R846,

4

V ers ion C h an ge L ist ( P . I. R . L ist )

V ers ion C h an ge L ist ( P . I. R . L ist )V ers ion C h an ge L ist ( P . I. R . L ist )

R e q ue st

R e q ue stR eq u est

O w ner

O w nerOw ne r

verify function ok, so delete 0 ohm to short unpop PR100,PR101,P R201,PR202,PR3 00,PR303,PR401, PR522,PR535,

Morris

Morris unpop VDDC I parts from v endor recommend and EEverify ok only for Sun XT unpop PL120 0,PL1201,PU120 0,PQ1201,PR1201 ,PR1203,PR1204 ,PR1208,PR1209,

Morris44 VGA_CORE/P CIE 13/04/12 change PL1300 f rom SH00000GQ0 0 to SH00000PK0 0

Morris customer r equest add PR2 10Kohm14

part shortage i ssue13

Issue D escriptionD ate

Issue D escriptionIssue D escription

3

P ag e 1

P ag e 1P a ge 1

change PC712 to unpop change PQ704 to unpop change PC707 fr om 0.1uF_0402 to 1uF_0603 change PC720 fr om 0.1uF to 10 0pF change PC711 fr om 1000pF to 0 .01uF change PQ705 fr om SB00000SD00 to SB00000WY00

change PR529 fr om 3.83K to 5. 76K change PR504 fr om 523K to 499 K

change PR503 fr om 56K to 75K

PR704,PR7 08,PR710,PR714 ,PR715,PR717

PR1103,PR 1200,PR1206,PR 1210

PR1211,PR 1212,PR1213,PC 1201,PC1202,PC1 204,PC1205,PC1 206,PC1207, PC1209,PC 1210,PC1211,PC 1213 (only for Sun XT)

2

So lu t io n D escription

So lu t io n D escription R ev.

So lu t io n D escriptionSo l u tio n D escription

R e v .P a g e#

R e v .R ev .

0.3

0.3unpop from EE r equest unpop PR8 08

0.4

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/21 2014/05/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR-PIR

LA-9984P

1

47 57Wednesday, May 22, 2013

0.4

5

D D

UV1A

4

3

2

1

12

DIS@

RV66

RV66 100K_0402_5%

100K_0402_5%

AA38

PCIE_RX0P

Y37

PCIE_RX0N

Y35

PCIE_RX1P

W36

PCIE_RX1N

W38

PCIE_RX2P

V37

PCIE_RX2N

V35

PCIE_RX3P

U36

PCIE_RX3N

U38

PCIE_RX4P

T37

PCIE_RX4N

T35

PCIE_RX5P

R36

PCIE_RX5N

R38

PCIE_RX6P

P37

PCIE_RX6N

P35

PCIE_RX7P

N36

PCIE_RX7N

N38

PCIE_RX8P

M37

PCIE_RX8N

M35

PCIE_RX9P

L36

PCIE_RX9N

L38

PCIE_RX10P

K37

PCIE_RX10N

K35

PCIE_RX11P

J36

PCIE_RX11N

J38

PCIE_RX12P

H37

PCIE_RX12N

H35

PCIE_RX13P

G36

PCIE_RX13N

G38

PCIE_RX14P

F37

PCIE_RX14N

F35

PCIE_RX15P

E37

PCIE_RX15N

CLOCK

AB35

PCIE_REFCLKP

AA36

PCIE_REFCLKN

AH16

PWRGOOD

AA30

PERSTB

216-0833000-A11-THAMES-XT-M2_FCBGA962~D

THAMES XT M2

@

PCI EXPRESS INTERFACE

CALIBRATION

PEG_CTX_GRX_P0<12> PEG_CTX_GRX_N0<12>

PEG_CTX_GRX_P1<12> PEG_CTX_GRX_N1<12>

PEG_CTX_GRX_P2<12> PEG_CTX_GRX_N2<12>

PEG_CTX_GRX_P3<12> PEG_CTX_GRX_N3<12>

C C

B B

CLK_PEG_VGA<9> CLK_PEG_VGA#<9>

PEG_CTX_GRX_P0 PEG_CTX_GRX_N0

PEG_CTX_GRX_P1 PEG_CTX_GRX_N1

PEG_CTX_GRX_P2 PEG_CTX_GRX_N2

PEG_CTX_GRX_P3 PEG_CTX_GRX_N3

CLK_PEG_VGA CLK_PEG_VGA#

DIS@

1 2

RV64 1K_0402_5%

GPU_RST#

UV1

VENUSXT@

UV1

VENUSXT@

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P PCIE_TX10N

PCIE_TX11P PCIE_TX11N

PCIE_TX12P PCIE_TX12N

PCIE_TX13P PCIE_TX13N

PCIE_TX14P PCIE_TX14N

PCIE_TX15P PCIE_TX15N

PCIE_CALRP

PCIE_CALRN

Y33

PCIE_CRX_C_GTX_P0

Y32

PCIE_CRX_C_GTX_N0

W33

PCIE_CRX_C_GTX_P1

W32

PCIE_CRX_C_GTX_N1 PEG_CRX_GTX_N1

U33

PCIE_CRX_C_GTX_P2

U32

PCIE_CRX_C_GTX_N2

U30

PCIE_CRX_C_GTX_P3

U29

PCIE_CRX_C_GTX_N3 PEG_CRX_GTX_N3

T33 T32

T30 T29

P33 P32

P30 P29

N33 N32

N30 N29

L33 L32

L30 L29

K33 K32

J33 J32

K30 K29

H33 H32

DIS@

RV198

1.69K_0402_1%

Y30

Y29

1.69K_0402_1%

1 2

DIS@

RV203

RV203 1K_0402_1%

1K_0402_1%

Thames RV198, 1.27K_0402_1% pull-down RV203, 2K_0402_1% pull-up PWR need to Modify +VGA_PCIE

+VGA_PCIE

12

CV430.1U_0402_10V7K DIS@CV430.1U_0402_10V7K DIS@

12

CV440.1U_0402_10V7K DIS@CV440.1U_0402_10V7K DIS@

12

CV450.1U_0402_10V7K DIS@CV450.1U_0402_10V7K DIS@

12

CV460.1U_0402_10V7K DIS@CV460.1U_0402_10V7K DIS@

12

CV470.1U_0402_10V7K DIS@CV470.1U_0402_10V7K DIS@

12

CV480.1U_0402_10V7K DIS@CV480.1U_0402_10V7K DIS@

12

CV490.1U_0402_10V7K DIS@CV490.1U_0402_10V7K DIS@

12

CV500.1U_0402_10V7K DIS@CV500.1U_0402_10V7K DIS@

PEG_CRX_GTX_P0 PEG_CRX_GTX_N0

PEG_CRX_GTX_P1

PEG_CRX_GTX_P2 PEG_CRX_GTX_N2

PEG_CRX_GTX_P3

PEG_CRX_GTX_P0 <12> PEG_CRX_GTX_N0 <12>

PEG_CRX_GTX_P1 <12> PEG_CRX_GTX_N1 <12>

PEG_CRX_GTX_P2 <12> PEG_CRX_GTX_N2 <12>

PEG_CRX_GTX_P3 <12> PEG_CRX_GTX_N3 <12>

DGPU_HOLD_RST#<10>

PLT_RST#<10,21,26,30,6>

LVDS Interface

UV1G

LVDS CONTROL

TXCLK_UP_DP F3P

TXCLK_UN_D PF3N

TXOUT_U0P_D PF2P

TXOUT_U0N_ DPF2N

TXOUT_U1P_D PF1P

TXOUT_U1N_ DPF1N

TXOUT_U2P_D PF0P

TXOUT_U2N_ DPF0N

LVTMDP

TXCLK_LP_DPE 3P TXCLK_LN_DP E3N

TXOUT_L0P_D PE2P TXOUT_L0N_D PE2N

TXOUT_L1P_D PE1P TXOUT_L1N_D PE1N

TXOUT_L2P_D PE0P TXOUT_L2N_D PE0N

216-0833000-A11-THAMES-XT-M2_FCBGA962~D

@

+3VGS

5

1

VCC

IN1

2

IN2

GND

3

AK27

VARY_BL

AJ27

DIGON

AK35 AL36

AJ38 AK37

AH35 AJ36

AG38 AH37

AF35

TXOUT_U3P

AG36

TXOUT_U3N

AP34 AR34

AW37 AU35

AR37 AU39

AP35 AR35

AN36

TXOUT_L3P

AP37

TXOUT_L3N

Place CV326 Close to UV13

DIS@

2

CV326

0.1U_0402_25V6K

1

4

GPU_RST#

OUT

UV13

UV13 MC74VHC1G08DFT2G_SC70-5

MC74VHC1G08DFT2G_SC70-5

DIS@

216-0846000 A1 VENUS XT M2 FCBGA 962P 0FD

SA00006KW0L

UV1

VENUSPRO@

UV1

A A

5

VENUSPRO@

216-0846009 A1 VENUS PRO M2 FCBGA 962P 0FD

SA00006MW0L

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

ATI_Venus Pro_M2_PCIE/LVDS

LA-9984P

1

48 57Wednesday, May 22, 2013

1.0

5

+1.8VGS

RV67 10K_0402_5 %X76@RV67 10K_0402_5%X76@

1 2

RV68 10K_0402_5 %@RV68 10K_0402_5%@

1 2

RV69 10K_0402_5 %X76@RV69 10K_0402_5%X76@

1 2

RV70 10K_0402_5 %@RV70 10K_0402_5%@

1 2

RV71 10K_0402_5 %X76@RV71 10K_0402_5%X76@

1 2

Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2

H5GQ2H24AFR-T2C

128Mx16bits (64Mx32bits) GDDR5

128MX16bits DDR3

+3VGS

LV14

DIS@LV14

DIS@

12

(125mA)

LV15

DIS@LV15

DIS@

0.95V@Venus

12

RV97

XTALDIS@RV97

XTALDIS@

1M_0402_5%

YV1

XTALDIS@YV1

XTALDIS@

27MHZ_10PF_7V2700005 0

3

GND

4

XTALIN

Hynix 2Gb SA00004GD1L(R1) SA00004GD2L(R3)

K4G20325FD-FC04

Samsung 2Gb SA00005B70L(R1) SA00005B71L(R3)

H5TC2G63FFR-11C

Hynix 1Gb SA00006H40L(R1) SA00006H41L(R3)

K4W2G1646E-BY11

Samsung 1Gb SA00005SH0L(R1) SA00005SH1L(R3)

MT41K128M16JT-107G:K

Micron 1Gb SA00005XB0L(R1) SA00005XB1L(R3)

STRAPS

1 2 1 2

@

@ 1 8 2 7 3 6 4 5

RP60

10K_8P4R_5%

1 2 1 2 1 2 1 2

DIS@

@

@ 1 8 2 7 3 6 4 5

RP47

10K_8P4R_5%

(75mA)

1

CV83

CV82

2

1U_0402_6.3V6K

DIS@ CV83

DIS@

DIS@ CV82

DIS@

10U_0603_6.3V6M

1

CV86

CV87

2

1U_0402_6.3V6K

DIS@ CV86

DIS@

DIS@ CV87

DIS@

10U_0603_6.3V6M

XTALINXTALOUT

1

12

GND

2

PEG_CLKREQ#<9>

1 1

RV68 RV69 RV71

0

RV67 RV70 RV71

1 0

VGA_SMB_DA2 VGA_SMB_CK2

RV7510K_0402_5 % @ RV7510K_040 2_5% @

GPU_GPIO0

RV7610K_0402_5 % @ RV7610K_040 2_5% @

GPU_GPIO1

GPU_GPIO2

GPU_GPIO8 GPU_GPIO9

RV8110K_0402_5 % @ RV8110K_0402_5% @

GPU_GPIO11

RV8210K_0402_5 % @ RV8210K_0402_5% @

GPU_GPIO12

RV8310K_0402_5 % @ RV8310K_0402_5% @

GPU_GPIO13

RV854 .7K_0402_5%

AC_BATT

GPIO24_TRSTB GPIO25_TDI GPIO27_TMS GPIO26_TCK

+DPLL_PVDD

1

CV84

2

DIS@ CV84

DIS@

0.1U_0402_10V7K

+DPLL_VDDC

1

CV88

2

DIS@ CV88

DIS@

0.1U_0402_10V7K

+1.8VGS

CV95

10P_0402_50V8J

XTALDIS@

1 3

D D

*

C C

+1.8VGS

BLM15BD121SN1D_0402

B B

+VGA_PCIE

BLM15BD121SN1D_0402

12

CV94

10P_0402_50V8J

XTALDIS@

A A

For GCLK

XTALIN<29 >

RV69RV67 RV71

1

@

RV251

RV251 0_0402_5%

0_0402_5%

1 2 1 2

@

RV252

0_0402_5%

+1.8VGS

+3VGS

12

RV235

RV235 10K_0402_5%

10K_0402_5%

@

12

RV236

RV236 10K_0402_5%

10K_0402_5%

DIS@

Add 12/6 for MLPS

(5mA)

1 2

BLM15BD121SN1D_0402

+3VGS

2

G

D

S

D

S

QV28

@

QV28

@

2N7002K_SOT23-3

VRAM_ID0

VRAM_ID1

VRAM_ID2

1

GPU_GPIO6<43>

GPU_VID5<44>

GPU_VID4<44> GPU_VID3<44> GPU_VID2<44>

RV89 10K_040 2_5%@RV89 10K_0402_5%@

1 2

GPU_VID1<44>

0.60 V level, Please VREFG Divider ans cap close to ASIC

VENUS@

RV93 499_0402_ 1%

12

VENUS@

RV95 249_0402_ 1%

12

CV81 0.1U_0402_10V7K

VENUS@

XTALIN Voltage Swing: 1.8 V

TS_FDO

DIS@

LV16

+3VGS

12

@

RV199

2.2K_0402_5%

VGA_CLKREQ#_R

1 2

0_0402_1%

(1.8V@20mA TSVDD)

SUN internal VGA Thermal Sensor Address 0x714

5

T78T78

T79T79

RV248

CV91

DIS@ CV91

DIS@

@

1

2

10U_0603_6.3V6M

VRAM_ID0 VRAM_ID1 VRAM_ID2

GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 VGA_SMB_DA2_R VGA_SMB_CK2_R AC_BATT GPU_GPIO6

GPU_GPIO8 GPU_GPIO9 GPU_VID5 GPU_GPIO11 GPU_GPIO12 GPU_GPIO13 GPU_VID4 GPU_VID3 GPU_VID2 THM_ALERT#

GPU_VID1 GPIO21_BBEN

VGA_CLKREQ#_R

GPIO24_TRSTB GPIO25_TDI GPIO26_TCK GPIO27_TMS

GPIO28_TDO

20mil

+VREFG_GPU

20mil

+DPLL_PVDD

DPLL_PVSS

20mil

+DPLL_VDDC

XTALIN XTALOUT

GPU_THERMAL_D+

GPU_THERMAL_D-

TS_FDO

+TSVDD

1

CV92

CV93

2

DIS@ CV92

DIS@

DIS@ CV93

DIS@

1U_0402_6.3V6K

4

UV1B

MUTI GFX

AR8

DVPCNTL_MVP_0

AU8

DVPCNTL_MVP_1

AP8

DVPCNTL_0

AW8

DVPCNTL_1

AR3

DVPCNTL_2

AR1

DVPCLK

AU1

DVPDATA_0

AU3

DVPDATA_1

AW3

DVPDATA_2

AP6

DVPDATA_3

AW5

DVPDATA_4

AU5

DVPDATA_5

AR6

DVPDATA_6

AW6

DVPDATA_7

AU6

DVPDATA_8

AT7

DVPDATA_9

AV7

DVPDATA_10

AN7

DVPDATA_11

AV9

DVPDATA_12

AT9

DVPDATA_13

AR10

DVPDATA_14

AW10

DVPDATA_15

AU10

DVPDATA_16

AP10

DVPDATA_17

AV11

DVPDATA_18

AT11

DVPDATA_19

AR12

DVPDATA_20

AW12

DVPDATA_21

AU12

DVPDATA_22

AP12

DVPDATA_23

AJ21

SWAPLOCKA

AK21

SWAPLOCKB

I2C

AK26

SCL

AJ26

SDA

GENERAL PURPOSE I/O

AH20

GPIO_0

AH18

GPIO_1

AN16

GPIO_2

AH23

GPIO_3_SMBDATA

AJ23

GPIO_4_SMBCLK

AH17

GPIO_5_AC_BATT

AJ17

GPIO_6

AK17

GPIO_7_BLON

AJ13

GPIO_8_ROMSO

AH15

GPIO_9_ROMSI

AJ16

GPIO_10_ROMSCK

AK16

GPIO_11

AL16

GPIO_12

AM16

GPIO_13

AM14

GPIO_14_HPD2

AM13

GPIO_15_PWRCNTL_0

AK14

GPIO_16

AG30

GPIO_17_THERMAL_INT

AN14

GPIO_18_HPD3

AM17

GPIO_19_CTF

AL13

GPIO_20_PWRCNTL_1

AJ14

GPIO_21_BB_EN

AK13

GPIO_22_ROMCSB

AN13

GPIO_23_CLKREQB

AM23

JTAG_TRSTB

AN23

JTAG_TDI

AK23

JTAG_TCK

AL24

JTAG_TMS

AM24

JTAG_TDO

AJ19

GENERICA

AK19

GENERICB

AJ20

GENERICC

AK20

GENERICD

AJ24

GENERICE_HPD4

AH26

GENERICF_HPD5

AH24

GENERICG_HPD6

AK24

HPD1

AH13

VREFG

AM32

DPLL_PVDD

AN32

DPLL_PVSS

PLL/CLOCK

AN31

DPLL_VDDC

AV33

XTALIN

AU34

XTALOUT

AW34

XO_IN

AW35

XO_IN2

AF29

DPLUS

AG29

DMINUS

AK32

TS_FDO

AL31

TS_A/NC

10mil

AJ32

TSVDD

AJ33

TSVSS

216-0833000-A1 1-THAMES-XT-M2_FCBGA962~D

@

0.1U_0402_10V7K

VGA_SMB_CK2

VGA_SMB_DA2

4

THERMAL

DIS@

RV90

10K_0402_5%

DPA

DPB

DPC

DPD

DAC1

DAC2

H2SYNC/GENLK_CLK

V2SYNC/GENLK_VSYNC

DDC/AUX

+3VGS

12

DIS@

RV91

RV91 10K_0402_5%

10K_0402_5%

DMN66D0LDW-7_SOT363-6

TXCAP_DPA3P TXCAM_DPA3N

TX0P_DPA2P

TX0M_DPA2N

TX1P_DPA1P

TX1M_DPA1N

TX2P_DPA0P

TX2M_DPA0N

TXCBP_DPB3P TXCBM_DPB3N

TX3P_DPB2P

TX3M_DPB2N

TX4P_DPB1P

TX4M_DPB1N

TX5P_DPB0P

TX5M_DPB0N

TXCCP_DPC3P

TXCCM_DPC3N

TX0P_DPC2P TX0M_DPC2N

TX1P_DPC1P TX1M_DPC1N

TX2P_DPC0P TX2M_DPC0N

TXCDP_DPD3P

TXCDM_DPD3N

TX3P_DPD2P TX3M_DPD2N

TX4P_DPD1P TX4M_DPD1N

TX5P_DPD0P TX5M_DPD0N

HSYNC VSYNC

AVSSQ

VDD1DI

VSS1DI

R2/NC

R2B/NC

G2/NC

G2B/NC

B2/NC

B2B/NC

COMP/NC

VDD2DI/NC VSS2DI/NC

A2VDD/NC

A2VDDQ/NC

A2VSSQ/TSVSSQ

R2SET/NC

DDC1CLK

DDC1DATA

AUX1P AUX1N

DDC2CLK

DDC2DATA

AUX2P AUX2N

DDCCLK_AUX3P

DDCDATA_AUX3N

DDCCLK_AUX4P

DDCDATA_AUX4N

DDCCLK_AUX5P

DDCDATA_AUX5N

DDC6CLK

DDC6DATA

DDCCLK_AUX7P

DDCDATA_AUX7N

DIS@

AU24 AV23

AT25 AR24

AU26 AV25

AT27 AR26

AR30 AT29

AV31 AU30

AR32 AT31

AT33 AU32

AU14 AV13

AT15 AR14

AU16 AV15

AT17 AR16

AU20 AT19

AT21 AR20

AU22 AV21

AT23 AR22

AD39

R

AD37

RB

AE36

G

AD35

GB

AF37

B

AE38

BB

AC36 AC38

AB34

RSET

AD34

AVDD

AE34

AC33 AC34

AC30 AC31

AD30 AD31

AF30 AF31

AC32

C/NC

AD32

Y/NC

AF32

AD29 AC29

AG31 AG32

AG33

AD33

AF33

AA29

AM26 AN26

AM27 AL27

AM19 AL19

AN20 AM20

AL30 AM30

AL29 AM29

AN21 AM21

AJ30 AJ31

AK30 AK29

ACIN<10,30,36,37>

ACIN_65W<30>

For DGPU output display Debug (For Venus ASIC)

GPU_VGA_R

GPU_VGA_G

GPU_VGA_B

GPU_VGA_HSYNC GPU_VGA_VSYNC

VENUS@

RV84 499_04 02_1%

1 2

10mil

+AVDD

(1.8V@65mA AVDD)

10mil

+VDD1DI

(1.8V@100mA VDD1DI)

1

CV78

CV79

2

0.1U_0402_10V7K

VENUS@ CV78

VENUS@

1 2

GENLK_CLK GENLK_VSYNC

RV207 0_0402_5%

RV246

RV247

2

1U_0402_6.3V6K

VENUS@ CV79

VENUS@

0_0402_5%@

SUN@

1 2

PS_1

PS_2

PS_3

NC_TSVSSQ should be tied to GND

For DGPU output display Debug (For Venus ASIC)

GPU_VGA_DDCCLK GPU_VGA_DDCDAT

VGA Thermal Sensor SMB

+3VGS

2

G

61

S

D

S

D

5

QV15B

34

SGD

QV15A

DIS@

QV15A

DIS@

DMN66D0LDW-7_SOT363-6

3

4.7K_0402_5%

DMN66D0LDW-7_SOT363-6

1 2

RV250

0_0402_5%

@

T85T85

T86T86

T87T87

T88T88 T89T89

100mA

1 2

VENUS@

LV13

LV13 BLM15BD121SN1D_0402

BLM15BD121SN1D_0402

1

CV80

2

10U_0603_6.3V6M

VENUS@ CV80

VENUS@

+DPLL_PVDD

DPLL_PVSS

T80T80 T81T81

T90T90 T91T91

EC_SMB_CK2 <19,30,9>

EC_SMB_DA2 <19,30,9>

3

QV14B

RV74

DIS@

+3VGS

12

61

D

G

2

S

+1.8VGS

RV73

DIS@

10K_0402_5%

QV14A

DMN66D0LDW-7_SOT363-6

DIS@

PACIN#

1

CV76

CV75

2

1U_0402_6.3V6K

0.1U_0402_10V7K

VENUS@ CV76

VENUS@

VENUS@ CV75

VENUS@

2

GPIO0 PCIE FULL TX OUTPUT SWINGTX_PWRS_ENB

GPIO1TX_DEEMPH_EN PCIE TRANSMITTER DE-EMPHASIS

GPIO2

GPIO8

GPIO9 VGA ENABLEDBIF_VGA DIS

GPIO21

GPIO_22_ROMCSB

GPIO[13:11]ROMIDCFG(2:0)

H2SYNC

GENERICC

HSYNCAUD[1]

VSYNCAUD[0]

H2SYNC GENERICC

TX_PWRS_ENB G PIO0

+1.8VGS

12

RV237

8.45K_0402_1%

@

12

RV238

1

4.75K_0402_1%

VENUS@

2

0.68U_0402_10V

*

DESCRIPTION OF DEFAULT SETTINGSPIN

Advertises PCIE speed when compliance test

RESERVED

ENABLE EXTERNAL BIOS ROM

SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

AUD[1] AUD[0] 0 0 No audio function 0 1 Audio for DisplayPort and HDMI if dongle is detected 1 0 Audio for DisplayPort only 1 1 Audio for both DisplayPort and HDMI

Transmitter Power Saving Enable 0: 50% Tx output swing for mobile mode 1: full Tx output swing (Default setting for Desktop)

PCI Express Transmitter De-emphasis Enable

GPIO1TX_DEEMPH_EN

0: Tx de-emphasis diabled for mobile mode 1: Tx de-emphasis enabled (Defailt setting for desktop)

CV331

VENUS@

SUN MLPs

RV241 RV242 Bits [3:1]

PS_3

NC 4.75k

Hynix

8.45k

Samsung

4.75k NC

Micron

VENUS MLPs PS_3 used default

GPIO8

+1.8VGS +1.8 VGS

12

RV239

RV239 10K_0402_1%

10K_0402_1%

@

12

RV240

1

4.75K_0402_1%

4.75K_0402_1% CV333

CV333

VENUS@

2

0.68U_0402_10V

@

000

2k

001

111

RECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR 1 = INSTALL 10K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE

0: 50% swing 1: Full swing

0: disable 1: enable

0: 2.5GT/s 1: 5GT/s

0: disable 1: enable

+3VGS

5

RV85 PU

12

chg to @

@

AC_BATT

34

D

G

S

65mA

1

CV77

2

10U_0603_6.3V6M

VENUS@ CV77

VENUS@

CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

STRAPS

RSVD

BIOS_ROM_EN

VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS

RSVD

AMD RESERVED CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND NOT CONFLICT DURING RESET

GPIO21 GPIO2

+1.8VGS

1 2

VENUS@

LV12

LV12 BLM15BD121SN1D_0402

BLM15BD121SN1D_0402

PS_1 PS_2 PS_3

CV329

@

External Thermal Sensor EMC1402-2-ACZL-TR

SDATA

ALERT#

+3VGS

8

SCLK

7

6

5

+3VGS

Closed to GPU

GPU_THERMAL_D+ VGA_SMB_DA2

GPU_THERMAL_D-

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VGS

VENUS@

2

RV98

VENUS@

CV85

0.1U_0402_10V7K

1

VENUS@

CV89

CV89 2200P_0402_50V7K

2200P_0402_50V7K

2

2013/05/17 2014/06/01

2

RV98

4.7K_0402_5%

1

1 2

Compal Secret Data

Deciphered Date

UV14

1

VDD

2

D+

3

D-

THERM#4GND

EMC1402-2-ACZL-TR_MSOP8

VENUS@

Address:100_1101b Main : SA00001Z710 2nd : SA00003PU00

1

RECOMMENDED SETTINGS

X

0

X

XXX

0

11

12

RV241

8.45K_0402_1%

@

12

RV242

1

4.75K_0402_1%

VENUS@

2

0.68U_0402_10V

VENUS@

RV96

4.7K_0402_5%

1 2

VGA_SMB_CK2

THM_ALERT#

Compal Electronics, Inc.

Title

ATI_Venus Pro_M2_Main_MSIC

Size Document Numbe r Rev

Date: Sheet of

1

LA-9984P

1.0

49 57Wedne sday, May 22, 2013

5

D D

PX_MODE=1 for Normal Operation PX_MODE=0 for BACO mode to shut down power rails expcept VDDR3,PCIE_VDDC and 1.8V rail

Note:

PX4.0 +VGA_CORE,VDDCI,+1.5VGS ON PX4.0 +3VGS, +1.0VGS,+1.8VGS OFF PX5.0 +3VGS,+VGA_CORE,VDDCI,+1.5VGV,+1.0VGS,+1.8VGS OFF

4

3

2

1

Switch circuits in BACO desingns for Thames/Seymour only [email protected], in BACO mode

+3VALW

+3VGS

12

@

RV105

RV105 20K_0402_5%

20K_0402_5%

C C

PXS_PWREN<10,11,39,43,44>

PXS_PWREN

12

DIS@

RV109

RV109 100K_0402_5%

100K_0402_5%

PXS_PWREN#

13

D

2

QV25

DIS@

QV25 2N7002K_SOT23-3

2N7002K_SOT23-3

S

DIS@

G

60mil

1 2

RV103 0_0805_5%

VENUS@

RV234 0_0603_5%

SUN@

for PX5.0

1

CV97

22U_0805_6.3V6MDIS@

2

60mil

1 2

+VGA_CORE+VGA_PCIE +BIF_VDDC

for PX4.0 and PX5.0

+1.8VS TO +1.8VGS

Power seguence of Sun XT,Venus Pro,Venus XT

+3VGS

B B

+VGA_CORE

+1.8VS

@

2 1

SHORT DEFAULT

+VDDCI(+VGA_PCIE)

+1.35V_MEM_GFX

+1.0VGS

+1.8VGS

<20ms

+1.35VS_VGA TO +1.35V_MEM_GFX

+1.35VS_VGA

SHORT DEFAULT

J92MM@J92MM

JP9

@JP9

@

2 1

2MM

+1.8VGS

+5VALW

PXS_PWREN

+1.35V_MEM_GFX

+3VS TO +3VGS

+3VS +3VGS

DIS@

G

DIS@

RV108

1 2

1K_0402_5%

13

D

QV24

S

2N7002K_SOT23-3

DIS@

RV107

20K_0402_5%

2

JP8

@JP8

@

2 1

2MM

3 1

QV22

AP2301GN-HF_SOT23-3

2

1

DIS@

CV103

0.1U_0603_25V7K

2

DIS@QV22

DIS@

1

CV101

CV101 10U_0603_6.3V6M

10U_0603_6.3V6M

2

DIS@

1

CV102

CV102 1U_0603_10V6K

1U_0603_10V6K

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

ATI_Venus Pro_M2_BACO POWER

LA-9984P

1

50 57Wednesday, May 22, 2013

1.0

5

D D

+1.8VGS

+VGA_PCIE

C C

+VGA_PCIE

B B

A A

(220mA)

1.0V@220mA DPCD_VDD10)

0.95V@Venus

1 2

@VENUS@

RV121

RV121 0_0402_1%

0_0402_1%

(220mA)

1.0V@240mA DPEF_VDD10)

0.95V@Venus

1 2

@VENUS@

RV126

RV126 0_0402_1%

0_0402_1%

+1.8VGS

12

1

CV117

@ CV117

@

2

10U_0603_6.3V6M

+1.8VGS

VENUS@

RV243

8.45K_0402_1%

VENUS@

RV201

RV201 2K_0402_1%

2K_0402_1%

CV123

@ CV123

@

(30mA)

1.8V@300mA DPCD_VDD18)

1 2

@VENUS@

RV119

RV119 0_0402_1%

0_0402_1%

+DPCD_VDD10

1

CV118

CV119

@ CV118

@

@ CV119

@

2

1U_0402_6.3V6K

0.1U_0402_10V7K

(330mA)

1 2

@VENUS@

RV124

RV124 0_0402_1%

0_0402_1%

+DPEF_VDD10

1

CV125

CV124

@ CV125

@

@ CV124

@

2

1U_0402_6.3V6K

0.1U_0402_10V7K

10U_0603_6.3V6M

0.1U_0402_10V7K

PS_0

1

@

CV335

0.68U_0402_10V

2

PS_0 Should be tied to GND on Thames/Seymour

1

CV111

@

2

10U_0603_6.3V6M

1.8V@300mA DPEF_VDD18)

CV120

VENUS@ CV120

VENUS@

1

2

Do not install for Heathrow/Mars Pro

1

CV112

CV113

@

2

1U_0402_6.3V6K

0.1U_0402_10V7K

+DPEF_VDD18

1

CV121

CV122

2

VENUS@ CV121

VENUS@

VENUS@ CV122

VENUS@

1U_0402_6.3V6K

0.1U_0402_10V7K

10U_0603_6.3V6M

0.1U_0402_10V7K

+DPEF_VDD18

+DPEF_VDD10

Thames/Seymour Only

+DPCD_VDD18

+DPCD_VDD10

+DPCD_VDD18

+DPCD_VDD10

+DPEF_VDD18

+DPEF_VDD10

1

2

20mil

PS_0

VENUS@

RV127

RV127 150_0402_1%

150_0402_1%

20mil

+DPCD_VDD18

20mil

12

RV122150_0402_1% DIS@ RV122150_0402_1% DIS@

20mil

12

4

UV1H

DP C/D POWER

AP20

DPCD/DPC_VDD 18#1

AP21

DPCD/DPC_VDD 18#2

AP13

DPCD/DPC_VDD 10#1

AT13

DPCD/DPC_VDD 10#2

AN17

DP/DPC_VSSR#1

AP16

DP/DPC_VSSR#2

AP17

DP/DPC_VSSR#3

AW14

DP/DPC_VSSR#4

AW16

DP/DPC_VSSR#5

AP22

DPCD/DPD_VDD 18#1

AP23

DPCD/DPD_VDD 18#2

AP14

DPCD/DPD_VDD 10#1

AP15

DPCD/DPD_VDD 10#2

AN19

DP/DPD_VSSR#1

AP18

DP/DPD_VSSR#2

AP19

DP/DPD_VSSR#3

AW20

DP/DPD_VSSR#4

AW22

DP/DPD_VSSR#5

AW18

DPCD_CALR

DP E/F POWER

AH34

DPEF/DPE_VDD18# 1

AJ34

DPEF/DPE_VDD18# 2

AL33

DPEF/DPE_VDD10# 1

AM33

DPEF/DPE_VDD10# 2

AN34

DP/DPE_VSSR#1

AP39

DP/DPE_VSSR#2

AR39

DP/DPE_VSSR#3

AU37

DP/DPE_VSSR#4

AF34

DPEF/DPF_VDD18# 1

AG34

DPEF/DPF_VDD18# 2

AK33

DPEF/DPF_VDD10# 1

AK34

DPEF/DPF_VDD10# 2

AF39

DP/DPF_VSSR#1

AH39

DP/DPF_VSSR#2

AK39

DP/DPF_VSSR#3

AL34

DP/DPF_VSSR#4

AM34

DP/DPF_VSSR#5

AM39

DPEF_CALR

216-0833000-A11-THAMES-XT-M2_FCBGA962~D

@

DP A/B POWER

DPAB/DPA_VDD18#1 DPAB/DPA_VDD18#2

DPAB/DPA_VDD10#1 DPAB/DPA_VDD10#2

DP/DPA_VSSR#1 DP/DPA_VSSR#2 DP/DPA_VSSR#3 DP/DPA_VSSR#4 DP/DPA_VSSR#5

DPAB/DPB_VDD18#1 DPAB/DPB_VDD18#2

DPAB/DPB_VDD10#1 DPAB/DPB_VDD10#2

DP/DPB_VSSR#1 DP/DPB_VSSR#2 DP/DPB_VSSR#3 DP/DPB_VSSR#4 DP/DPB_VSSR#5

DPAB_CALR

DP PLL POWER

DPAB_VDD18/DPA_PVDD

DP_VSSR/DPA_PVSS

DPAB_VDD18/DPB_P VDD

DP_VSSR/DPB_PVSS

DPCD_VDD18/D PC_PVDD

DP_VSSR/DPC_PVSS

DPCD_VDD18/D PD_PVDD

DP_VSSR/DPD_PVSS

DPEF_VDD18/DPE_ PVDD

DP_VSSR/DPE_PVSS

DPEF_VDD18/DPF_ PVDD

DP_VSSR/DPF_PVSS

20mil

130mA

AN24 AP24

20mil

110mA

AP31 AP32

AN27 AP27 AP28 AW24 AW26

20mil

AP25 AP26

20mil

AN33 AP33

AN29 AP29 AP30 AW30 AW32

AW28

20mA

AU28 AV27

20mA

AV29 AR28

+DPCD_VDD18

20mA

AU18 AV17

20mA

AV19 AR18

20mA

AM37 AN38

20mA

AL38 AM35

MLPS Bit

PS0:

PS1:

PS2:

PS3:

130mA

110mA

+DPAB_VDD18

+DPCD_VDD18

+DPEF_VDD18

(30mA)

1.8V@300mA DPAB_VDD18)

+DPAB_VDD18

1

CV108

2

VENUS@ CV108

VENUS@

0.1U_0402_10V7K

(1.0V@220mA DPAB_VDD10)

0.95V@Venus

+DPAB_VDD10

CV114

0.1U_0402_10V7K

VENUS@ CV114

VENUS@

+DPAB_VDD18

+DPAB_VDD10

VENUS@

RV123

RV123 150_0402_1%

150_0402_1%

1 2

10mil

11001

11000

00000

11000

1

CV110

CV109

2

VENUS@ CV110

VENUS@

VENUS@ CV109

VENUS@

1U_0402_6.3V6K

10U_0603_6.3V6M

1

CV115

CV116

2

1U_0402_6.3V6K

10U_0603_6.3V6M

VENUS@ CV115

VENUS@

VENUS@ CV116

VENUS@

AMD recommended setting

R_PU R_PD Cstrap

RV243=8.45K

RV237=NC

RV239=NC

RV241=NC

+DPAB_VDD18

(330mA)

+DPAB_VDD10

1

2

3

+1.8VGS

1 2

@

RV118

RV118 0_0402_1%

0_0402_1%

+VGA_PCIE

1 2

@

RV120

RV120 0_0402_1%

0_0402_1%

RV201=2K CV335=NC

RV238=4.75K CV329=NC

RV240=4.75K CV331=0.68u

RV242=4.75K CV333=NC

2

UV1F

AB39

PCIE_VSS#1

E39

PCIE_VSS#2

F34

PCIE_VSS#3

F39

PCIE_VSS#4

G33

PCIE_VSS#5

G34

PCIE_VSS#6

H31

PCIE_VSS#7

H34

PCIE_VSS#8

H39

PCIE_VSS#9

J31

PCIE_VSS#10

J34

PCIE_VSS#11

K31

PCIE_VSS#12

K34

PCIE_VSS#13

K39

PCIE_VSS#14

L31

PCIE_VSS#15

L34

PCIE_VSS#16

M34

PCIE_VSS#17

M39

PCIE_VSS#18

N31

PCIE_VSS#19

N34

PCIE_VSS#20

P31

PCIE_VSS#21

P34

PCIE_VSS#22

P39

PCIE_VSS#23

R34

PCIE_VSS#24

T31

PCIE_VSS#25

T34

PCIE_VSS#26

T39

PCIE_VSS#27

U31

PCIE_VSS#28

U34

PCIE_VSS#29

V34

PCIE_VSS#30

V39

PCIE_VSS#31

W31

PCIE_VSS#32

W34

PCIE_VSS#33

Y34

PCIE_VSS#34

Y39

PCIE_VSS#35

GND

F15 F17 F19 F21 F23 F25 F27 F29 F31 F33

F7

F9 G2 G6 H9

J2

J27

J6

J8

K14

K7

L11 L17

L2

L22 L24

L6

M17 M22 M24

N16 N18

N2

N21 N23 N26

N6

R15 R17

R2

R20 R22 R24 R27

R6

T11 T13 T16 T18 T21 T23 T26 U15 U17

U2

U20 U22 U24 U27

U6

V11 V16 V18 V21 V23 V26

W2

W6 Y15 Y17 Y20 Y22 Y24 Y27 U13 V13

GND

GND#100 GND#101 GND#102 GND#103 GND#104 GND#105 GND#106 GND#107 GND#108 GND#109 GND#110 GND#111 GND#112 GND#113 GND#114 GND#115 GND#116 GND#117 GND#118 GND#119 GND#120 GND#121 GND#122 GND#123 GND#124 GND#125 GND#126 GND#127 GND#128 GND#129 GND#130 GND#131 GND#132 GND#133 GND#134 GND#135 GND#136 GND#137 GND#138 GND#139 GND#140 GND#141 GND#142 GND#143 GND#144 GND#145 GND#146 GND#147 GND#148 GND#149 GND#150 GND#151 GND#153 GND#154 GND#155 GND#156 GND#157 GND#158 GND#159 GND#160 GND#161 GND#163 GND#164 GND#165 GND#166 GND#167 GND#168 GND#169 GND#170 GND#171 GND#172 GND#173 GND#174 GND#175 GND#152 GND#162

216-0833000-A11-THAMES-XT-M2_FCBGA962~D

@

GND/PX_EN#61

VSS_MECH#1 VSS_MECH#2 VSS_MECH#3

GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8

GND#9 GND#10 GND#11 GND#12 GND#13 GND#14 GND#15 GND#16 GND#17 GND#18 GND#19 GND#20 GND#21 GND#22 GND#23 GND#24 GND#25 GND#26 GND#27 GND#28 GND#29 GND#30 GND#31 GND#32 GND#33 GND#34 GND#35 GND#36 GND#37 GND#38 GND#39 GND#40 GND#41 GND#42 GND#43 GND#44 GND#45 GND#46 GND#47 GND#48 GND#49 GND#50 GND#51 GND#52 GND#53 GND#54 GND#55 GND#56 GND#57 GND#58 GND#59 GND#60

GND#62 GND#63 GND#64 GND#65 GND#66 GND#67 GND#68 GND#69 GND#70 GND#71 GND#72 GND#73 GND#74 GND#75 GND#76 GND#77 GND#78 GND#79 GND#80 GND#81 GND#82 GND#83 GND#84 GND#85 GND#86 GND#87 GND#88 GND#89 GND#90 GND#91 GND#92 GND#93 GND#94 GND#95 GND#96 GND#97 GND#98

A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20 AG22 AG6 AG9 AH21 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20 AL21 AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13

A39 AW1 AW39

MECH#1 MECH#2 MECH#3

12

@

RV125

4.7K_0402_5%

T82 PADT82 PAD T83 PADT83 PAD T84 PADT84 PAD

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

ATI_Venus Pro_M2_PWR_GND

LA-9984P

1

51 57Wednesday, May 22, 2013

1.0

5

4

3

2

1

+PCIE_VDDR

1

CV127

CV128

CV126

2

@ CV127

@

@ CV128

@

@ CV126

UV1E

For GDDR5 MVDDQ = 1.35V

(1.7)A

1

CV136

2

DIS@ CV136

DIS@

10U_0603_6.3V6M

(50mA)

DIS@ LV19

DIS@

1 2

BLM15BD121SN1D_0402

1

CV190

CV189

2

1U_0402_6.3V6K

DIS@ CV190

DIS@

DIS@ CV189

DIS@

CV139

CV138

CV137

2

DIS@ CV139

DIS@

DIS@ CV138

DIS@

DIS@ CV137

DIS@

10U_0603_6.3V6M

LV19

(1.8V@110mA VDD_CT)

10U_0603_6.3V6M

1

2

+1.8VGS

BLM15BD121SN1D_0402

(150mA)

+1.8VGS

(M97, Broadway and Madison: 1.8V@150mA MPV18)

LV21

1 2

MCK1608471YZF 0603

(1.8V@75mA SPV18)

1

CV200

CV202

CV201

2

1U_0402_6.3V6K

DIS@ CV200

DIS@

DIS@ CV202

DIS@

DIS@ CV201

DIS@

0.1U_0402_10V7K

10U_0603_6.3V6M

(120mA SPV10)

1

CV217

CV215

CV216

2

1U_0402_6.3V6K

DIS@ CV217

DIS@

DIS@ CV215

DIS@

DIS@ CV216

DIS@

0.1U_0402_10V7K

10U_0603_6.3V6M

VCCSENSE_VGA<44>

VDDCI_SEN<43>

VSSSENSE_VGA<44>

1

CV140

2

DIS@ CV140

DIS@

10U_0603_6.3V6M

1

CV170

CV171

2

1U_0402_6.3V6K

DIS@ CV170

DIS@

DIS@ CV171

DIS@

VENUS@

LV20

1 2

DIS@LV21

DIS@

1

CV141

2

1U_0402_6.3V6K

DIS@ CV141

DIS@

+1.35V_MEM_GFX

1

CV152

2

DIS@ CV152

DIS@

0.1U_0402_10V7K

1

CV172

2

1U_0402_6.3V6K

DIS@ CV172

DIS@

1

CV197

2

DIS@ CV197

DIS@

10U_0603_6.3V6M

RV215

10_0402_1%

DIS@

1

CV142

2

DIS@ CV142

DIS@

1

CV153

2

DIS@ CV153

DIS@

1

CV173

2

DIS@ CV173

DIS@

1

CV145

CV143

CV144

2

1U_0402_6.3V6K

DIS@ CV145

DIS@

DIS@ CV143

DIS@

DIS@ CV144

DIS@

1

CV154

CV155

CV156

2

DIS@ CV154

DIS@

DIS@ CV155

DIS@

DIS@ CV156

DIS@

0.1U_0402_10V7K

1

CV174

2

DIS@ CV174

DIS@

0.1U_0402_10V7K

20mil

1

CV194

CV193

2

1U_0402_6.3V6K

0.1U_0402_10V7K

VENUS@ CV194

VENUS@

VENUS@ CV193

VENUS@

1

CV199

CV198

2

1U_0402_6.3V6K

DIS@ CV199

DIS@

DIS@ CV198

DIS@

0.1U_0402_10V7K

20mil

+MPV18

10mil 20mil

+VGA_CORE+VDDCI

12

RV202

RV202 10_0402_1%

10_0402_1%

DIS@

VCCSENSE_VGA

VDDCI_SEN

VSSSENSE_VGA

12

RV204

10_0402_1%DIS@

@

+3VGS

1

CV187

2

DIS@ CV187

DIS@

10U_0603_6.3V6M

(50mA)

LV22

1 2

BLM15BD121SN1D_0402

(100mA)

0.95V@Venus

LV23

1 2

MCK1608471YZF 0603

+1.35V_MEM_GFX

220U_B2_2.5VM_R35

CV135

1

+

2

+1.8VGS +VDDC_CT

(60mA)

1

CV188

2

1U_0402_6.3V6K

DIS@ CV188

DIS@

DIS@LV22

DIS@

DIS@LV23

DIS@

D D

C C

+1.8VGS

B B

+VGA_PCIE

A A

UV1E

MEM I/O

AC7

VDDR1#1

AD11

VDDR1#2

AF7

VDDR1#3

AG10

VDDR1#4

AJ7

VDDR1#5

AK8

VDDR1#6

AL9

VDDR1#7

G11

VDDR1#8

G14

VDDR1#9

G17

VDDR1#10

G20

VDDR1#11

G23

VDDR1#12

G26

VDDR1#13

G29

VDDR1#14

H10

VDDR1#15

J7

VDDR1#16

J9

VDDR1#17

K11

VDDR1#18

K13

VDDR1#19

K8

VDDR1#20

L12

VDDR1#21

L16

VDDR1#22

L21

VDDR1#23

L23

VDDR1#24

L26

VDDR1#25

L7

VDDR1#26

M11

VDDR1#27

N11

VDDR1#28

P7

VDDR1#29

R11

VDDR1#30

U11

VDDR1#31

U7

VDDR1#32

Y11

VDDR1#33

Y7

VDDR1#34

LEVEL

20mil

TRANSLATION

AF26

VDD_CT#1

AF27

VDD_CT#2

AG26

VDD_CT#3

AG27

VDD_CT#4

10mil

+VDDR4

+SPV18

+SPV10

I/O

AF23

VDDR3#1

AF24

VDDR3#2

AG23

VDDR3#3

AG24

VDDR3#4

AF13

VDDR4#4

AF15

VDDR4#5

AG13

VDDR4#7

AG15

VDDR4#8

AD12

VDDR4#1

AF11

VDDR4#2

AF12

VDDR4#3

AG11

VDDR4#6

M20

NC_VDDRHA

M21

NC_VSSRHA

V12

NC_VDDRHB

U12

NC_VSSRHB

PLL

H7

MPV18#1

H8

MPV18#2

AM10

SPV18

AN9

SPV10

AN10

SPVSS

VOLTAGE

VOLTAGE SENESE

SENESE

10mil

AF28

FB_VDDC

10mil

AG28

FB_VDDCI

AH29

FB_GND

216-0833000-A11-THAMES-XT-M2_FCBGA962~D

@

PCIE

PCIE_VDDR#1 PCIE_VDDR#2 PCIE_VDDR#3 PCIE_VDDR#4 PCIE_VDDR#5 PCIE_VDDR#6 PCIE_VDDR#7 PCIE_VDDR#8

PCIE_VDDR/PCIE_PVDD

PCIE_VDDC#1 PCIE_VDDC#2 PCIE_VDDC#3 PCIE_VDDC#4 PCIE_VDDC#5 PCIE_VDDC#6 PCIE_VDDC#7 PCIE_VDDC#8

PCIE_VDDC#9 PCIE_VDDC#10 PCIE_VDDC#11 PCIE_VDDC#12

VDDC#1

CORE

VDDC#2 VDDC#3 VDDC#4 VDDC#5 VDDC#6 VDDC#7 VDDC#8

VDDC#9 VDDC#10 VDDC#11 VDDC#12 VDDC#13 VDDC#14 VDDC#15

POWER

VDDC#16 VDDC#17 VDDC#18 VDDC#19 VDDC#20 VDDC#21 VDDC#22 VDDC#23 VDDC#24 VDDC#25 VDDC#26 VDDC#27 VDDC#28 VDDC#29 VDDC#30 VDDC#31 VDDC#32

VDDC/BIF_VDDC#33

VDDC#34 VDDC#35 VDDC#36 VDDC#37 VDDC#38 VDDC#39 VDDC#40 VDDC#41

VDDC/BIF_VDDC#42

VDDC#43 VDDC#44 VDDC#45 VDDC#46 VDDC#47 VDDC#48 VDDC#49 VDDC#50 VDDC#51 VDDC#52 VDDC#53 VDDC#54 VDDC#55 VDDC#56 VDDC#57 VDDC#58

VDDCI#1 VDDCI#2 VDDCI#3 VDDCI#4 VDDCI#5 VDDCI#6 VDDCI#7 VDDCI#8

VDDCI#9 VDDCI#10 VDDCI#11 VDDCI#12 VDDCI#13 VDDCI#14 VDDCI#15

ISOLATED

VDDCI#16

CORE I/O

VDDCI#17 VDDCI#18 VDDCI#19 VDDCI#20 VDDCI#21 VDDCI#22

40mil

AA31 AA32 AA33 AA34 V28 W29 W30 Y31 AB37

G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28

AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18 AG21 AH22 AH27 AH28 M26 N24 N27 R18 R21 R23 R26 T17 T20 T22 T24 T27 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28

AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13

@

1U_0402_6.3V6K

0.1U_0402_10V7K

1 2

CV146

1U_0402_6.3V6K

DIS@ CV146

DIS@

+PCIE_VDDR

1

2

+PCIE_PVDD

+VGA_CORE

@

RV244 0_0402_5%

@

RV245 0_0402_5%

(20.5A)

1

CV327

CV327 330U_D2_2.5V_R6M

330U_D2_2.5V_R6M

2

ESD@

ESD solution

55mA

+BIF_VDDC

1

CV196

CV195

2

1U_0402_6.3V6K

DIS@ CV196

DIS@

DIS@ CV195

DIS@

(GDDR3/DDR3 1.12V@4A VDDCI)

(GDDR5 1.12V@16A VDDCI)

1

CV203

2

1U_0402_6.3V6K

DIS@ CV203

DIS@

VDDCI and VDDC should have seperate regulators with a merge option on PCB For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC can share one common regulator

CV206

CV205

CV204

2

1U_0402_6.3V6K

DIS@ CV206

DIS@

DIS@ CV205

DIS@

DIS@ CV204

DIS@

MBK1608121YZF_0603

1

CV129

CV130

CV131

2

@ CV129

@

@ CV130

@

@ CV131

@

1U_0402_6.3V6K

10U_0603_6.3V6M

+BIF_VDDC

1

CV147

CV149

CV148

2

1U_0402_6.3V6K

DIS@ CV147

DIS@

DIS@ CV149

DIS@

DIS@ CV148

DIS@

For non-BACO designs, connect BIF_VDDC to VDDC. For BACO designs - see BACO reference schematics

1

CV207

CV208

2

1U_0402_6.3V6K

DIS@ CV207

DIS@

DIS@ CV208

DIS@

(440mA)

(1.8V@504mA PCIE_VDDR)

@ LV17

@

1U_0402_6.3V6K

1

CV209

2

DIS@ CV209

DIS@

+1.8VGS

LV17

12

DIS@ LV18

DIS@

MBK1608121YZF_0603

1

CV132

CV134

CV133

2

1U_0402_6.3V6K

DIS@ CV132

DIS@

DIS@ CV134

DIS@

DIS@ CV133

DIS@

0.1U_0402_10V7K

10U_0603_6.3V6M

+VGA_PCIE

(SUN)

1

CV151

CV150

2

DIS@ CV151

DIS@

DIS@ CV150

DIS@

10U_0603_6.3V6M

1

CV210

2

1U_0402_6.3V6K

DIS@ CV210

DIS@

(VENUS)

(PCIe 2.0 => +0.95V@1920mA PCIE_VDDC)

(PCIe 3.0 => [email protected] PCIE_VDDC)

+VDDCI

4A

1

CV213

CV211

CV212

CV214

2

1U_0402_6.3V6K

DIS@ CV213

DIS@

DIS@ CV211

DIS@

DIS@ CV212

DIS@

DIS@ CV214

DIS@

10U_0603_6.3V6M

22U_0603_6.3V6M

1

CV325

CV324

2

1U_0402_6.3V6K

DIS@ CV325

DIS@

DIS@ CV324

DIS@

10U_0603_6.3V6M

40mA

1

CV322

2

DIS@ CV322

DIS@

+1.8VGS

LV18

12

(SUN)(VENUS)

(PCIe 2.0 => 1.8V@50mA PCIE_PVDD)

(PCIe 3.0 => 1.8V@80mA PCIE_PVDD)

LV25

@LV25

@

1 2

BLM15BD121SN1D_0402

LV26

@LV26

@

1 2

BLM15BD121SN1D_0402

1

CV323

2

DIS@ CV323

DIS@

10U_0603_6.3V6M

+VGA_CORE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/17 2014/06/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

ATI_Venus Pro_M2_Power

LA-9984P

1

52 57Wednesday, May 22, 2013

1.0

5

UV1C

DDR2

DDR2 GDDR3/GDDR5

GDDR3/GDDR5 DDR3

DDR3

C37

DQA0_0<54> DQA0_1<54> DQA0_2<54> DQA0_3<54> DQA0_4<54> DQA0_5<54> DQA0_6<54> DQA0_7<54> DQA0_8<54>

D D

C C

B B

DQA0_9<54> DQA0_10<54> DQA0_11<54> DQA0_12<54> DQA0_13<54> DQA0_14<54> DQA0_15<54> DQA0_16<54> DQA0_17<54> DQA0_18<54> DQA0_19<54> DQA0_20<54> DQA0_21<54> DQA0_22<54> DQA0_23<54> DQA0_24<54> DQA0_25<54> DQA0_26<54> DQA0_27<54> DQA0_28<54> DQA0_29<54> DQA0_30<54> DQA0_31<54> DQA1_0<55> DQA1_1<55> DQA1_2<55> DQA1_3<55> DQA1_4<55> DQA1_5<55> DQA1_6<55> DQA1_7<55> DQA1_8<55> DQA1_9<55> DQA1_10<55> DQA1_11<55> DQA1_12<55> DQA1_13<55> DQA1_14<55> DQA1_15<55> DQA1_16<55> DQA1_17<55> DQA1_18<55> DQA1_19<55> DQA1_20<55> DQA1_21<55> DQA1_22<55> DQA1_23<55> DQA1_24<55> DQA1_25<55> DQA1_26<55> DQA1_27<55> DQA1_28<55> DQA1_29<55> DQA1_30<55> DQA1_31<55>

1 2

RV206 DIS@ 120_0402_1%RV206 DIS@ 120_0402_1%

DQA0_0 DQA0_1 DQA0_2 DQA0_3 DQA0_4 DQA0_5 DQA0_6 DQA0_7 DQA0_8 DQA0_9 DQA0_10 DQA0_11 DQA0_12 DQA0_13 DQA0_14 DQA0_15 DQA0_16 DQA0_17 DQA0_18 DQA0_19 DQA0_20 DQA0_21 DQA0_22 DQA0_23 DQA0_24 DQA0_25 DQA0_26 DQA0_27 DQA0_28 DQA0_29 DQA0_30 DQA0_31 DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8 DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15 DQA1_16 DQA1_17 DQA1_18 DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30 DQA1_31

+VDD_MEM15_REFDA +VDD_MEM15_REFSA

DQA0_0/DQA_0

C35

DQA0_1/DQA_1

A35

DQA0_2/DQA_2

E34

DQA0_3/DQA_3

G32

DQA0_4/DQA_4

D33

DQA0_5/DQA_5

F32

DQA0_6/DQA_6

E32

DQA0_7/DQA_7

D31

DQA0_8/DQA_8

F30

DQA0_9/DQA_9

C30

DQA0_10/DQA_10

A30

DQA0_11/DQA_11

F28

DQA0_12/DQA_12

C28

DQA0_13/DQA_13

A28

DQA0_14/DQA_14

E28

DQA0_15/DQA_15

D27

DQA0_16/DQA_16

F26

DQA0_17/DQA_17

C26

DQA0_18/DQA_18

A26

DQA0_19/DQA_19

F24

DQA0_20/DQA_20

C24

DQA0_21/DQA_21

A24

DQA0_22/DQA_22

E24

DQA0_23/DQA_23

C22

DQA0_24/DQA_24

A22

DQA0_25/DQA_25

F22

DQA0_26/DQA_26

D21

DQA0_27/DQA_27

A20

DQA0_28/DQA_28

F20

DQA0_29/DQA_29

D19

DQA0_30/DQA_30

E18

DQA0_31/DQA_31

C18

DQA1_0/DQA_32

A18

DQA1_1/DQA_33

F18

DQA1_2/DQA_34

D17

DQA1_3/DQA_35

A16

DQA1_4/DQA_36

F16

DQA1_5/DQA_37

D15

DQA1_6/DQA_38

E14

DQA1_7/DQA_39

F14

DQA1_8/DQA_40

D13

DQA1_9/DQA_41

F12

DQA1_10/DQA_42

A12

DQA1_11/DQA_43

D11

DQA1_12/DQA_44

F10

DQA1_13/DQA_45

A10

DQA1_14/DQA_46

C10

DQA1_15/DQA_47

G13

DQA1_16/DQA_48

H13

DQA1_17/DQA_49

J13

DQA1_18/DQA_50

H11

DQA1_19/DQA_51

G10

DQA1_20/DQA_52

G8

DQA1_21/DQA_53

K9

DQA1_22/DQA_54

K10

DQA1_23/DQA_55

G9

DQA1_24/DQA_56

A8

DQA1_25/DQA_57

C8

DQA1_26/DQA_58

E8

DQA1_27/DQA_59

A6

DQA1_28/DQA_60

C6

DQA1_29/DQA_61

E6

DQA1_30/DQA_62

A5

DQA1_31/DQA_63

L18

MVREFDA

L20

MVREFSA

L27

MEM_CALRN0

N12

MEM_CALRN1

AG12

MEM_CALRN2

M12

MEM_CALRP1

M27

MEM_CALRP0

AH12

MEM_CALRP2

216-0833000-A11-THAMES-XT-M2_FCBGA962~D

@

DDR2

DDR2 GDDR5/GDDR3

GDDR5/GDDR3 DDR3

DDR3

MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA1_0/MAA_8

MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12

MAA1_5/MAA_13_BA2 MAA1_6/MAA_14_BA0

MAA1_7/MAA_A15_BA1

WCKA0_0/DQM A_0

WCKA0B_0/DQ MA_1

WCKA0_1/DQM A_2

WCKA0B_1/DQ MA_3

WCKA1_0/DQM A_4

WCKA1B_0/DQ MA_5

WCKA1_1/DQM A_6

WCKA1B_1/DQ MA_7

GDDR5/DDR2/GDDR3

MEMORY INTERFACE A

EDCA0_0/QSA_0/RDQS A_0 EDCA0_1/QSA_1/RDQS A_1 EDCA0_2/QSA_2/RDQS A_2 EDCA0_3/QSA_3/RDQS A_3 EDCA1_0/QSA_4/RDQS A_4 EDCA1_1/QSA_5/RDQS A_5 EDCA1_2/QSA_6/RDQS A_6 EDCA1_3/QSA_7/RDQS A_7

DDBIA0_0/QSA_0B/WD QSA_0 DDBIA0_1/QSA_1B/WD QSA_1 DDBIA0_2/QSA_2B/WD QSA_2 DDBIA0_3/QSA_3B/WD QSA_3 DDBIA1_0/QSA_4B/WD QSA_4 DDBIA1_1/QSA_5B/WD QSA_5 DDBIA1_2/QSA_6B/WD QSA_6 DDBIA1_3/QSA_7B/WD QSA_7

ADBIA0/ODTA0 ADBIA1/ODTA1

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B RASA1B

CASA0B CASA1B

CSA0B_0 CSA0B_1

CSA1B_0 CSA1B_1

CKEA0 CKEA1

WEA0B WEA1B

MAA0_8 MAA1_8

GDDR5

G24 J23 H24 J24 H26 J26 H21 G21 H19 H20 L13 G16 J16 H16 J17 H17

A32 C32 D23 E22 C14 A14 E10 D9

C34 D29 D25 E20 E16 E12 J10 D7

A34 E30 E26 C20 C16 C12 J11 F8

J21 G19

H27 G27

J14 H14

K23 K19

K20 K17

K24 K27

M13 K16

K21 J20

K26 L15

H23 J19

4

MAA0_0 MAA0_1 MAA0_2 MAA0_3 MAA0_4 MAA0_5 MAA0_6 MAA0_7 MAA1_0 MAA1_1 MAA1_2 MAA1_3 MAA1_4 MAA1_5 MAA1_6 MAA1_7

WCKA0_0 WCKA0B_0 WCKA0_1 WCKA0B_1 WCKA1_0 WCKA1B_0 WCKA1_1 WCKA1B_1

EDCA0_0 EDCA0_1 EDCA0_2 EDCA0_3 EDCA1_0 EDCA1_1 EDCA1_2 EDCA1_3

DDBIA0_0 DDBIA0_1 DDBIA0_2 DDBIA0_3 DDBIA1_0 DDBIA1_1 DDBIA1_2 DDBIA1_3

ADBIA0 ADBIA1

CLKA0 CLKA0#

CLKA1 CLKA1#

RASA0# RASA1#

CASA0# CASA1#

CSA0#_0

CSA1#_0

CKEA0 CKEA1

WEA0# WEA1#

MAA0_8 MAA1_8

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These Capacitors and Resistor values are an example only. The Series R and || Cap values will depend on the DRAM load and will have to be calculated for different Memory ,DRAM Load and board to pass Reset Signal Spec. Place all these components very close to GPU (Within 25mm) and keep all component close to each Other (within 5mm) except Rser2

MAA0_0 <54> MAA0_1 <54> MAA0_2 <54> MAA0_3 <54> MAA0_4 <54> MAA0_5 <54> MAA0_6 <54> MAA0_7 <54> MAA1_0 <55> MAA1_1 <55> MAA1_2 <55> MAA1_3 <55> MAA1_4 <55> MAA1_5 <55> MAA1_6 <55> MAA1_7 <55>

WCKA0_0 <54> WCKA0B_0 <54> WCKA0_1 <54> WCKA0B_1 <54> WCKA1_0 <55> WCKA1B_0 <55> WCKA1_1 <55> WCKA1B_1 <55>

EDCA0_0 <54> EDCA0_1 <54> EDCA0_2 <54> EDCA0_3 <54> EDCA1_0 <55> EDCA1_1 <55> EDCA1_2 <55> EDCA1_3 <55>

DDBIA0_0 <54> DDBIA0_1 <54> DDBIA0_2 <54> DDBIA0_3 <54> DDBIA1_0 <55> DDBIA1_1 <55> DDBIA1_2 <55> DDBIA1_3 <55>

ADBIA0 <54> ADBIA1 <55>

CLKA0 <54> CLKA0# <54>

CLKA1 <55> CLKA1# <55>

RASA0# <54> RASA1# <55>

CASA0# <54> CASA1# <55>

CSA0#_0 <54>

CSA1#_0 <55>

CKEA0 <54> CKEA1 <55>

WEA0# <54> WEA1# <55>

MAA0_8 <54> MAA1_8 <55>

GDDR5 CMD Mapping Table

<0..31> <32..63> Memory

CMD12 CMD28 RAS# CMD15 CMD31 CAS# CMD5 CMD21 WE# CMD0 CMD16 CS# CMD8 CMD24 ABI# CMD10 CMD26 A0_A10 CMD11 CMD27 A1_A9 CMD2 CMD18 A2_BA0 CMD1 CMD17 A3_BA3 CMD3 CMD19 A4_BA2 CMD4 CMD20 A5_BA1 CMD7 CMD23 A6_A11 CMD6 CMD22 A7_A8 CMD9 CMD25 A12_FRU CMD14 CMD30 CKE# CMD13 CMD29 RESET#

CLKA0

CLKA0#

CLKA1

CLKA1#

CLKB0

CLKB0#

CLKB1

CLKB1#

12

3

RV42120_0402_1% RV42120_0402_1%

RV43120_0402_1% RV43120_0402_1%

RV44120_0402_1% RV44120_0402_1%

RV45120_0402_1% RV45120_0402_1%

RV46120_0402_1% RV46120_0402_1%

RV47120_0402_1% RV47120_0402_1%

RV48120_0402_1% RV48120_0402_1%

RV49120_0402_1% RV49120_0402_1%

+1.35V_MEM_GFX

DQB0_0<56> DQB0_1<56> DQB0_2<56> DQB0_3<56> DQB0_4<56> DQB0_5<56> DQB0_6<56> DQB0_7<56> DQB0_8<56> DQB0_9<56> DQB0_10<56> DQB0_11<56> DQB0_12<56> DQB0_13<56> DQB0_14<56> DQB0_15<56> DQB0_16<56> DQB0_17<56> DQB0_18<56> DQB0_19<56> DQB0_20<56> DQB0_21<56> DQB0_22<56> DQB0_23<56> DQB0_24<56> DQB0_25<56> DQB0_26<56> DQB0_27<56> DQB0_28<56> DQB0_29<56> DQB0_30<56> DQB0_31<56> DQB1_0<57> DQB1_1<57> DQB1_2<57> DQB1_3<57> DQB1_4<57> DQB1_5<57> DQB1_6<57> DQB1_7<57> DQB1_8<57> DQB1_9<57> DQB1_10<57> DQB1_11<57> DQB1_12<57> DQB1_13<57> DQB1_14<57> DQB1_15<57> DQB1_16<57> DQB1_17<57> DQB1_18<57> DQB1_19<57> DQB1_20<57> DQB1_21<57> DQB1_22<57> DQB1_23<57> DQB1_24<57> DQB1_25<57> DQB1_26<57> DQB1_27<57> DQB1_28<57> DQB1_29<57> DQB1_30<57> DQB1_31<57>

1 2

RV133

0.1U_0402_10V7K

+VDD_MEM15_REFDB +VDD_MEM15_REFSB

DIS@

5.11K_0402_1%

CV218

RV136

51.1_0402_1%

@

DQB0_0 DQB0_1 DQB0_2 DQB0_3 DQB0_4 DQB0_5 DQB0_6 DQB0_7 DQB0_8 DQB0_9 DQB0_10 DQB0_11 DQB0_12 DQB0_13 DQB0_14 DQB0_15 DQB0_16 DQB0_17 DQB0_18 DQB0_19 DQB0_20 DQB0_21 DQB0_22 DQB0_23 DQB0_24 DQB0_25 DQB0_26 DQB0_27 DQB0_28 DQB0_29 DQB0_30 DQB0_31 DQB1_0 DQB1_1 DQB1_2 DQB1_3 DQB1_4 DQB1_5 DQB1_6 DQB1_7 DQB1_8 DQB1_9 DQB1_10 DQB1_11 DQB1_12 DQB1_13 DQB1_14 DQB1_15 DQB1_16 DQB1_17 DQB1_18 DQB1_19 DQB1_20 DQB1_21 DQB1_22 DQB1_23 DQB1_24 DQB1_25 DQB1_26 DQB1_27 DQB1_28 DQB1_29 DQB1_30 DQB1_31

TESTEN

12

2

UV1D

DDR2

DDR2 GDDR3/GDDR5

GDDR3/GDDR5 DDR3

DDR3

C5

DQB0_0/DQB_0

C3

DQB0_1/DQB_1

E3

DQB0_2/DQB_2

E1

DQB0_3/DQB_3

F1

DQB0_4/DQB_4

F3

DQB0_5/DQB_5

F5

DQB0_6/DQB_6

G4

DQB0_7/DQB_7

H5

DQB0_8/DQB_8

H6

DQB0_9/DQB_9

J4

DQB0_10/DQB_1 0

K6

DQB0_11/DQB_1 1

K5

DQB0_12/DQB_1 2

L4

DQB0_13/DQB_1 3

M6

DQB0_14/DQB_1 4

M1

DQB0_15/DQB_1 5

M3

DQB0_16/DQB_1 6

M5

DQB0_17/DQB_1 7

N4

DQB0_18/DQB_1 8

P6

DQB0_19/DQB_1 9

P5

DQB0_20/DQB_2 0

R4

DQB0_21/DQB_2 1

T6

DQB0_22/DQB_2 2

T1

DQB0_23/DQB_2 3

U4

DQB0_24/DQB_2 4

V6

DQB0_25/DQB_2 5

V1

DQB0_26/DQB_2 6

V3

DQB0_27/DQB_2 7

Y6

DQB0_28/DQB_2 8

Y1

DQB0_29/DQB_2 9

Y3

DQB0_30/DQB_3 0

Y5

DQB0_31/DQB_3 1

AA4

DQB1_0/DQB_32

AB6

DQB1_1/DQB_33

AB1

DQB1_2/DQB_34

AB3

DQB1_3/DQB_35

AD6

DQB1_4/DQB_36

AD1

DQB1_5/DQB_37

AD3

DQB1_6/DQB_38

AD5

DQB1_7/DQB_39

AF1

DQB1_8/DQB_40

AF3

DQB1_9/DQB_41

AF6

DQB1_10/DQB_4 2

AG4

DQB1_11/DQB_4 3

AH5

DQB1_12/DQB_4 4

AH6

DQB1_13/DQB_4 5

AJ4

DQB1_14/DQB_4 6

AK3

DQB1_15/DQB_4 7

AF8

DQB1_16/DQB_4 8

AF9

DQB1_17/DQB_4 9

AG8

DQB1_18/DQB_5 0

AG7

DQB1_19/DQB_5 1

AK9

DQB1_20/DQB_5 2

AL7

DQB1_21/DQB_5 3

AM8

DQB1_22/DQB_5 4

AM7

DQB1_23/DQB_5 5

AK1

DQB1_24/DQB_5 6

AL4

DQB1_25/DQB_5 7

AM6

DQB1_26/DQB_5 8

AM1

DQB1_27/DQB_5 9

AN4

DQB1_28/DQB_6 0

AP3

DQB1_29/DQB_6 1

AP1

DQB1_30/DQB_6 2

AP5

DQB1_31/DQB_6 3

Y12

MVREFDB

AA12

MVREFSB

AD28

TESTEN

AK10

CLKTESTA

AL10

CLKTESTB

216-0833000-A11-THAMES-XT-M2_FCBGA962~D

@

12

@

CV219

0.1U_0402_10V7K

12

@

RV137

51.1_0402_1%

route 50ohms single-ended/100ohms diff and keep short Debug only, for clock observation, if not needed, DNI 5mil 5mil

DDR2

DDR2 GDDR5/GDDR3

GDDR5/GDDR3 DDR3

DDR3

MAB0_0/MAB_0 MAB0_1/MAB_1 MAB0_2/MAB_2 MAB0_3/MAB_3 MAB0_4/MAB_4 MAB0_5/MAB_5 MAB0_6/MAB_6 MAB0_7/MAB_7 MAB1_0/MAB_8

MAB1_1/MAB_9 MAB1_2/MAB_10 MAB1_3/MAB_11 MAB1_4/MAB_12

MAB1_5/BA2 MAB1_6/BA0 MAB1_7/BA1

WCKB0_0 /DQMB_0

WCKB0B_0 /DQMB_1

WCKB0_1 /DQMB_2

WCKB0B_1 /DQMB_3

WCKB1_0 /DQMB_4

WCKB1B_0 /DQMB_5

WCKB1_1 /DQMB_6

WCKB1B_1 /DQMB_7

GDDR5/DDR2/GDDR3

EDCB0_0/QSB_0 /RDQSB_0

MEMORY INTERFACE B

EDCB0_1/QSB_1 /RDQSB_1 EDCB0_2/QSB_2 /RDQSB_2 EDCB0_3/QSB_3 /RDQSB_3 EDCB1_0/QSB_4 /RDQSB_4 EDCB1_1/QSB_5 /RDQSB_5 EDCB1_2/QSB_6 /RDQSB_6 EDCB1_3/QSB_7 /RDQSB_7

DDBIB0_0/QSB_0B/W DQSB_0 DDBIB0_1/QSB_1B/W DQSB_1 DDBIB0_2/QSB_2B/W DQSB_2 DDBIB0_3/QSB_3B/W DQSB_3 DDBIB1_0/QSB_4B/W DQSB_4 DDBIB1_1/QSB_5B/W DQSB_5 DDBIB1_2/QSB_6B/W DQSB_6 DDBIB1_3/QSB_7B/W DQSB_7

ADBIB0/ODTB0 ADBIB1/ODTB1

CLKB0

CLKB0B

CLKB1

CLKB1B

RASB0B RASB1B

CASB0B CASB1B

CSB0B_0 CSB0B_1

CSB1B_0 CSB1B_1

CKEB0 CKEB1

WEB0B WEB1B

MAB0_8 MAB1_8

DRAM_RST

GDDR5

P8 T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9

H3 H1 T3 T5 AE4 AF5 AK6 AK5

F6 K3 P3 V5 AB5 AH1 AJ9 AM5

G7 K1 P1 W4 AC4 AH3 AJ8 AM3

T7 W7

L9 L8

AD8 AD7

T10 Y10

W10 AA10

P10 L10

AD10 AC10

U10 AA11

N10 AB11

T8 W8

AH11

MAB0_0 MAB0_1 MAB0_2 MAB0_3 MAB0_4 MAB0_5 MAB0_6 MAB0_7 MAB1_0 MAB1_1 MAB1_2 MAB1_3 MAB1_4 MAB1_5 MAB1_6 MAB1_7

WCKB0_0 WCKB0B_0 WCKB0_1 WCKB0B_1 WCKB1_0 WCKB1B_0 WCKB1_1 WCKB1B_1

EDCB0_0 EDCB0_1 EDCB0_2 EDCB0_3 EDCB1_0 EDCB1_1 EDCB1_2 EDCB1_3

DDBIB0_0 DDBIB0_1 DDBIB0_2 DDBIB0_3 DDBIB1_0 DDBIB1_1 DDBIB1_2 DDBIB1_3

ADBIB0 ADBIB1

CLKB0 CLKB0#

CLKB1 CLKB1#

RASB0# RASB1#

CASB0# CASB1#

CSB0#_0

CSB1#_0

CKEB0 CKEB1

WEB0# WEB1#

MAB0_8 MAB1_8

DRAM_RST#_R

1

MAB0_0 <56> MAB0_1 <56> MAB0_2 <56> MAB0_3 <56> MAB0_4 <56> MAB0_5 <56> MAB0_6 <56> MAB0_7 <56> MAB1_0 <57> MAB1_1 <57> MAB1_2 <57> MAB1_3 <57> MAB1_4 <57> MAB1_5 <57> MAB1_6 <57> MAB1_7 <57>

WCKB0_0 <56> WCKB0B_0 <56> WCKB0_1 <56> WCKB0B_1 <56> WCKB1_0 <57> WCKB1B_0 <57> WCKB1_1 <57> WCKB1B_1 <57>

EDCB0_0 <56> EDCB0_1 <56> EDCB0_2 <56> EDCB0_3 <56> EDCB1_0 <57> EDCB1_1 <57> EDCB1_2 <57> EDCB1_3 <57>

DDBIB0_0 <56> DDBIB0_1 <56> DDBIB0_2 <56> DDBIB0_3 <56> DDBIB1_0 <57> DDBIB1_1 <57> DDBIB1_2 <57> DDBIB1_3 <57>

ADBIB0 <56> ADBIB1 <57>

CLKB0 <56> CLKB0# <56>

CLKB1 <57> CLKB1# <57>

RASB0# <56> RASB1# <57>

CASB0# <56> CASB1# <57>

CSB0#_0 <56>

CSB1#_0 <57>

CKEB0 <56> CKEB1 <57>

WEB0# <56> WEB1# <57>

MAB0_8 <56> MAB1_8 <57>

+1.35V_MEM_GFX

12

RV138

4.7K_0402_5%

@

+1.35V_MEM_GFX +1.35V_MEM_GFX

12

RV139

40.2_0402_1%

DIS@

A A

RV146

100_0402_1%

DIS@

12

+VDD_MEM15_REFDA

12

CV220

0.1U_0402_10V7K

DIS@

5

RV140

40.2_0402_1%

DIS@

RV147

100_0402_1%

DIS@

12

+VDD_MEM15_REFSA

12

CV221

0.1U_0402_10V7K

DIS@

DRAM_RST#<54,55,56,57>

4

1 2

RV143

51.1_0402_1%

DIS@

CV222

120P_0402_50V9

12

1 2

RV144

10_0402_1%

DIS@

3

DRAM_RST#_R

DIS@

RV145

4.99K_0402_1%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.35V_MEM_GFX +1.35V_MEM_GFX

12

RV141

40.2_0402_1%

DIS@

+VDD_MEM15_REFDB

12

CV223

RV148

100_0402_1%

DIS@

2013/05/17 2014/06/01

CV223

0.1U_0402_10V7K

DIS@

Compal Secret Data

Deciphered Date

2

RV142

40.2_0402_1%

DIS@

RV149

100_0402_1%

DIS@

12

+VDD_MEM15_REFSB

12

CV224

0.1U_0402_10V7K

DIS@

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

ATI_Venus Pro_M2_MEM IF

LA-9984P

1

1.0

53 57Wednesday, May 22, 2013

1.0

5

Memory Partition A - Lower 16 bits

UV4

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

J5

A12/RFU/NC

K4

A8/A7 A10/A0

K5

A11/A6 A9/A1

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

H11

BA0/A2 BA2/A4

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WC K23#

D4

WCK01 WCK2 3

P5

WCK23# WC K01#

P4

WCK23 WCK0 1

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

CV71

DIS@CV71

DIS@

D11 G11

L11 P11 G14

L14

H1

G5

B10 D10 G10

L10 P10

T10 H14 K14

VREFD1_2VREFC1

VDD VDD VDD VDD VDD VDD VDD

VSS

K1

VSS

B5

VSS VSS

L5

VSS

T5

VSS VSS VSS VSS VSS VSS VSS VSS VSS

170-BALL

SGRAM GDDR5

K4G20325FC-HC05_FBGA170~D

DIS@

+1.35V_MEM_GFX+1.35V_MEM_GFX

0.1U_0402_10V7K

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

EDCA0_1

EDCA0_3

DDBIA0_1

DDBIA0_3

CLKA0 CLKA0# CKEA0

MAA0_8

MAA0_7 MAA0_6 MAA0_5 MAA0_4

MAA0_3 MAA0_2 MAA0_1 MAA0_0

ADBIA0 RASA0# CSA0#_0 CASA0# WEA0#

WCKA0B_0 WCKA0_0

WCKA0B_1 WCKA0_1

VREFD1_1 VREFD1_2 VREFC1

DRAM_RST#

+1.35V_MEM_GFX

CV70

1

DIS@CV70

DIS@

2

12

CV394

RV35

DIS@CV394

DIS@

DIS@RV35

DIS@

12

RV36

CV395

DIS@RV36

DIS@

DIS@CV395

DIS@

0.1U_0402_10V7K

2.37K_0402_1%

5.49K_0402_1%

EDCA0_1<53>

EDCA0_3<53>

2.37K_0402_1%

5.49K_0402_1%

1

2

2.37K_0402_1%

5.49K_0402_1%

DDBIA0_1<53>

+1.35V_MEM_GFX

DDBIA0_3<53>

+1.35V_MEM_GFX

CLKA0<53> CLKA0#<53> CKEA0<53>

MAA0_8<53>

MAA0_7<53> MAA0_6<53> MAA0_5<53> MAA0_4<53>

MAA0_3<53> MAA0_2<53> MAA0_1<53> MAA0_0<53>

1 2

RV26 121_0402_1%DIS@ RV26 121_0402_1%DIS@

ADBIA0<53> RASA0#<53> CSA0#_0<53> CASA0#<53> WEA0#<53>

WCKA0B_0<53> WCKA0_0<53>

WCKA0B_1<53> WCKA0_1<53>

1U_0402_6.3V6K

CV372

1

DIS@CV372

DIS@

2

5

CV373

DIS@CV373

DIS@

D D

+1.35V_MEM_GFX

1U_0402_6.3V6K

C C

B B

A A

1U_0402_6.3V6K

12

CV393

RV28

1

DIS@CV393

DIS@

DIS@RV28

DIS@

2

1U_0402_6.3V6K

12

RV34

CV387

1

DIS@RV34

DIS@

DIS@CV387

DIS@

2

10U_0603_6.3V6M

CV41

1

DIS@CV41

DIS@

2

1U_0402_6.3V6K

12

RV37

CV388

1

DIS@RV37

DIS@

DIS@CV388

DIS@

2

1U_0402_6.3V6K

12

RV29

CV397

1

DIS@RV29

DIS@

DIS@CV397

DIS@

2

4

NORMAL

4

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

+1.35V_MEM_GFX

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

3

64X32 GDDR5

DQA0_13 DQA0_12 DQA0_15 DQA0_14 DQA0_11 DQA0_10 DQA0_8 DQA0_9

DQA0_13 <53> DQA0_12 <53> DQA0_15 <53> DQA0_14 <53> DQA0_11 <53> DQA0_10 <53> DQA0_8 <53> DQA0_9 <53>

+1.35V_MEM_GFX

A_1

DQA0_30 DQA0_29 DQA0_31 DQA0_28 DQA0_27 DQA0_26 DQA0_24 DQA0_25

DQA0_30 <53> DQA0_29 <53> DQA0_31 <53> DQA0_28 <53> DQA0_27 <53> DQA0_26 <53> DQA0_24 <53> DQA0_25 <53>

A_3

+1.35V_MEM_GFX

1U_0402_6.3V6K

2.37K_0402_1%

12

CV396

RV38

1

DIS@CV396

DIS@

DIS@RV38

DIS@

2

5.49K_0402_1%

1U_0402_6.3V6K

12

RV181

CV398

1

DIS@RV181

DIS@

DIS@CV398

DIS@

2

10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_10V7K

CV42

1

DIS@CV42

DIS@

2

+1.35V_MEM_GFX +1.35V_MEM_GFX

1

2

1

2

0.1U_0402_10V7K

CV374

CV380

CV59

1

DIS@CV374

DIS@

DIS@CV380

DIS@

2

1U_0402_6.3V6K

2.37K_0402_1%

12

CV328

RV183

DIS@CV328

DIS@

DIS@RV183

DIS@

1U_0402_6.3V6K

VREFC2 VREFD2_2

5.49K_0402_1%

12

CV399

RV184

DIS@CV399

DIS@

DIS@RV184

DIS@

3

DRAM_RST#<53,55,56,57>

0.1U_0402_10V7K

CV60

1

DIS@CV60

DIS@

2

+1.35V_MEM_GFX

1

2

EDCA0_2<53>

EDCA0_0<53>

DDBIA0_2<53>

DDBIA0_0<53>

+1.35V_MEM_GFX

DIS@ RV25

DIS@

0.1U_0402_10V7K

CV61

1

DIS@CV61

DIS@

2

1U_0402_6.3V6K

1

CV9

CV8

2

DIS@

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

1 2

RV25

121_0402_1%

0.1U_0402_10V7K

CV69

DIS@CV69

DIS@

0.1U_0402_10V7K

CV72

1

DIS@CV72

DIS@

2

12

RV185

CV330

DIS@RV185

DIS@

DIS@CV330

DIS@

12

CV400

RV186

DIS@CV400

DIS@

DIS@RV186

DIS@

EDCA0_2

EDCA0_0

DDBIA0_2

DDBIA0_0

CLKA0 CLKA0# CKEA0

MAA0_8

MAA0_0 MAA0_1 MAA0_3 MAA0_2

MAA0_5 MAA0_4 MAA0_6 MAA0_7

ADBIA0 CASA0# WEA0# RASA0# CSA0#_0

WCKA0B_1 WCKA0_1

WCKA0B_0 WCKA0_0

VREFD2_1 VREFD2_2 VREFC2

DRAM_RST#

0.1U_0402_10V7K

1

2

2.37K_0402_1%

5.49K_0402_1%

2

UV5

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

J5

A12/RFU/NC

K4

A8/A7 A10/A0

K5

A11/A6 A9/A1

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

H11

BA0/A2 BA2/A4

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WC K23#

D4

WCK01 WCK2 3

P5

WCK23# WC K01#

P4

WCK23 WCK0 1

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

CV73

H1

VSS

K1

VSS

B5

DIS@CV73

DIS@

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

170-BALL

SGRAM GDDR5

K4G20325FC-HC05_FBGA170~D

DIS@

MIRROR

MF=0 MF=1 MF=0MF=1

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

DQA0_19 DQA0_17 DQA0_18 DQA0_16 DQA0_21 DQA0_22 DQA0_20 DQA0_23

DQA0_0 DQA0_2 DQA0_1 DQA0_3 DQA0_5 DQA0_7 DQA0_4 DQA0_6

+1.35V_MEM_GFX

DQA0_19 <53> DQA0_17 <53> DQA0_18 <53> DQA0_16 <53> DQA0_21 <53> DQA0_22 <53> DQA0_20 <53> DQA0_23 <53>

A_2

DQA0_0 <53> DQA0_2 <53> DQA0_1 <53> DQA0_3 <53> DQA0_5 <53> DQA0_7 <53> DQA0_4 <53> DQA0_6 <53>

A_0

1U_0402_6.3V6K

1

CV14

2

DIS@

1

1U_0402_6.3V6K

0.1U_0402_10V7K

CV16

1

CV15

2

DIS@CV16

DIS@

0.1U_0402_10V7K

CV17

DIS@CV17

DIS@

CV378

CV375

1

2

DIS@CV378

DIS@

DIS@CV375

DIS@

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

VRAM_A Lower_UV4,UV5

LA-9984P

54 57Wednesday, May 22, 2013

1

1.0

of

5

Memory Partition A - Upper 16 bits

UV3

C2

1

CV383

DIS@

2

1U_0402_6.3V6K

CV350

DIS@CV350

DIS@

1U_0402_6.3V6K

CV349

DIS@CV349

DIS@

VREFD3_1 VREFD3_2 VREFC3

DRAM_RST#

+1.35V_MEM_GFX

0.1U_0402_10V7K

CV368

1

DIS@CV368

DIS@

2

2.37K_0402_1%

12

RV193

DIS@RV193

DIS@

5.49K_0402_1%

12

RV194

DIS@RV194

DIS@

EDCA1_2

EDCA1_0

DDBIA1_2

DDBIA1_0

CLKA1 CLKA1# CKEA1

MAA1_8

MAA1_0 MAA1_1 MAA1_3 MAA1_2

MAA1_5 MAA1_4 MAA1_6 MAA1_7

ADBIA1 CASA1# WEA1# RASA1# CSA1#_0

WCKA1B_1 WCKA1_1

WCKA1B_0 WCKA1_0

0.1U_0402_10V7K

CV369

DIS@CV369

DIS@

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

J5

A12/RFU/NC

K4

A8/A7 A10/A0

K5

A11/A6 A9/A1

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

H11

BA0/A2 BA2/A4

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WC K23#

D4

WCK01 WCK2 3

P5

WCK23# WC K01#

P4

WCK23 WCK0 1

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

SGRAM GDDR5

K4G20325FC-HC05_FBGA170~D

DIS@

EDCA1_2<53>

EDCA1_0<53>

DDBIA1_2<53>

D D

+1.35V_MEM_GFX

1U_0402_6.3V6K

C C

1

2

1U_0402_6.3V6K

1

2

B B

+1.35V_MEM_GFX +1.35V_MEM_GFX

1U_0402_6.3V6K

12

CV401

1

DIS@CV401

DIS@

2

A A

1U_0402_6.3V6K

12

CV332

1

DIS@CV332

DIS@

2

+1.35V_MEM_GFX

DDBIA1_0<53>

+1.35V_MEM_GFX

CLKA1<53> CLKA1#<53> CKEA1<53>

MAA1_8<53>

MAA1_0<53> MAA1_1<53> MAA1_3<53> MAA1_2<53>

MAA1_5<53> MAA1_4<53> MAA1_6<53> MAA1_7<53>

+1.35V_MEM_GFX

1 2

RV31 121_0402_1%DIS@ RV31 121_0402_1%DIS@

ADBIA1<53> CASA1#<53> WEA1#<53> RASA1#<53> CSA1#_0<53>

2.37K_0402_1%

12

CV389

RV32

WCKA1B_1<53>

DIS@CV389

DIS@

12

CV390

DIS@CV390

DIS@

2.37K_0402_1%

RV191

DIS@RV191

DIS@

5.49K_0402_1%

RV192

DIS@RV192

DIS@

WCKA1_1<53>

DIS@RV32

DIS@

WCKA1B_0<53> WCKA1_0<53>

5.49K_0402_1%

RV33

DIS@RV33

DIS@

1U_0402_6.3V6K

10U_0603_6.3V6M

CV1

1

2

1

CV382

DIS@

2

DIS@CV1

DIS@

1

2

VREFD3_2 VREFC3

1

2

5

4

MIRROR

MF=0 MF=1 MF=0MF=1

170-BALL

4

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

+1.35V_MEM_GFX

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

DQA1_19 DQA1_18 DQA1_16 DQA1_17 DQA1_20 DQA1_23 DQA1_22 DQA1_21

DQA1_0 DQA1_1 DQA1_2 DQA1_4 DQA1_3 DQA1_6 DQA1_7 DQA1_5

+1.35V_MEM_GFX

1

2

1

2

10U_0603_6.3V6M

CV3

1

DIS@CV3

DIS@

2

DQA1_19 <53> DQA1_18 <53> DQA1_16 <53> DQA1_17 <53> DQA1_20 <53> DQA1_23 <53> DQA1_22 <53> DQA1_21 <53>

A_2

DQA1_0 <53> DQA1_1 <53> DQA1_2 <53> DQA1_4 <53> DQA1_3 <53> DQA1_6 <53> DQA1_7 <53> DQA1_5 <53>

A_0

1U_0402_6.3V6K

12

CV352

DIS@CV352

DIS@

1U_0402_6.3V6K

12

CV351

DIS@CV351

DIS@

1U_0402_6.3V6K

1

CV376

2

DIS@

1U_0402_6.3V6K

CV356

1

DIS@CV356

DIS@

2

1U_0402_6.3V6K

CV355

1

DIS@CV355

DIS@

2

3

UV6

C2

1 2

121_0402_1%

1

2

1U_0402_6.3V6K

CV10

DIS@

+1.35V_MEM_GFX+1.35V_MEM_GFX

1

2

1

2

0.1U_0402_10V7K

1U_0402_6.3V6K

RV30

CV74

DIS@CV74

DIS@

1

2

CV354

DIS@CV354

DIS@

CV353

DIS@CV353

DIS@

ADBIA1 RASA1# CSA1#_0 CASA1# WEA1#

WCKA1B_0 WCKA1_0

WCKA1B_1 WCKA1_1

VREFD4_1 VREFD4_2 VREFC4

DRAM_RST#

0.1U_0402_10V7K

CV370

DIS@CV370

DIS@

12

RV197

DIS@RV197

DIS@

12

RV39

DIS@RV39

DIS@

EDCA1_1

EDCA1_3

DDBIA1_1

DDBIA1_3

CLKA1 CLKA1# CKEA1

MAA1_8

MAA1_7 MAA1_6 MAA1_5 MAA1_4

MAA1_3 MAA1_2 MAA1_1 MAA1_0

DIS@RV30

DIS@

0.1U_0402_10V7K

1

2

2.37K_0402_1%

5.49K_0402_1%

C13 R13

R2

D2 D13 P13

P2

J12 J11

J3

J5

K4

K5 K10 K11

H10 H11

H5

H4

A5

U5

J1 J10 J13

J4

G3

G12

L3 L12

D5 D4

P5 P4

A10 U10

J14

J2

G1

L1

G4

L4

C5

R5 C10 R10 D11 G11

L11 P11 G14

L14

H1

CV371

K1 B5 G5

L5

DIS@CV371

DIS@

T5 B10 D10 G10

L10 P10 T10 H14 K14

VREFC4VREFD4_2

EDC0 EDC3 EDC1 EDC2 EDC2 EDC1 EDC3 EDC0

DBI0# DBI3# DBI1# DBI2# DBI2# DBI1# DBI3# DBI0#

CK CK# CKE#

A12/RFU/NC

A8/A7 A10/A0 A11/A6 A9/A1 BA1/A5 BA3/A3 BA2/A4 BA0/A2

BA3/A3 BA1/A5 BA0/A2 BA2/A4 A9/A1 A11/A6 A10/A0 A8/A7

VPP/NC VPP/NC

MF SEN ZQ

ABI# RAS# CAS# CS# WE# CAS# RAS# WE# CS#

WCK01# WC K23# WCK01 WCK2 3

WCK23# WC K01# WCK23 WCK0 1

VREFD VREFD VREFC

RESET#

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

K4G20325FC-HC05_FBGA170~D

DIS@

EDCA1_1<53>

EDCA1_3<53>

DDBIA1_1<53>

+1.35V_MEM_GFX

DDBIA1_3<53>

+1.35V_MEM_GFX

2.37K_0402_1%

RV195

DIS@RV195

DIS@

5.49K_0402_1%

RV196

DIS@RV196

DIS@

1U_0402_6.3V6K

1

CV381

2

DIS@

2.37K_0402_1%

12

RV40

DIS@RV40

DIS@

5.49K_0402_1%

12

RV41

DIS@RV41

DIS@

DRAM_RST#<53,54,56,57>

0.1U_0402_10V7K

CV63

CV64

1

2

DIS@CV64

DIS@

+1.35V_MEM_GFX

1U_0402_6.3V6K

1

2

CV62

1

2

DIS@CV62

DIS@

1

CV11

2

DIS@

1

2

DIS@CV63

DIS@

3

2

NORMAL

MF=0 MF=1 MF=0MF=1

170-BALL

SGRAM GDDR5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

1

A4

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

DQA1_14 DQA1_12 DQA1_13 DQA1_15 DQA1_11 DQA1_10 DQA1_8 DQA1_9

DQA1_31 DQA1_29 DQA1_30 DQA1_28 DQA1_24 DQA1_26 DQA1_27 DQA1_25

+1.35V_MEM_GFX

DQA1_14 <53> DQA1_12 <53> DQA1_13 <53> DQA1_15 <53> DQA1_11 <53> DQA1_10 <53> DQA1_8 <53> DQA1_9 <53>

A_1

DQA1_31 <53> DQA1_29 <53> DQA1_30 <53> DQA1_28 <53> DQA1_24 <53> DQA1_26 <53> DQA1_27 <53> DQA1_25 <53>

A_3

1U_0402_6.3V6K

1

CV67

2

DIS@

1U_0402_6.3V6K

CV66

DIS@

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

MARX-VRAM_A Upper_UV3,UV6

LA-9984P

1

0.1U_0402_10V7K

CV65

1

2

DIS@CV65

DIS@

55 57Wednesday, May 22, 2013

0.1U_0402_10V7K

CV379

CV377

CV68

1

2

DIS@CV379

DIS@

DIS@CV377

DIS@

DIS@CV68

DIS@

1.0

of

5

4

3

2

1

Memory Partition B - Lower 16 bits

UV7

CV287

DIS@CV287

DIS@

UV7

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

J5

A12/RFU/NC

K4

A8/A7 A10/A0

K5

A11/A6 A9/A1

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

H11

BA0/A2 BA2/A4

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WC K23#

D4

WCK01 WCK2 3

P5

WCK23# WC K01#

P4

WCK23 WCK0 1

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

SGRAM GDDR5

K4G20325FC-HC05_FBGA170~D

DIS@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

UV8

C2

1

2

1U_0402_6.3V6K

1

CV295

2

DIS@

12

CV21

DIS@CV21

DIS@

12

CV22

DIS@CV22

DIS@

EDCB0_1

EDCB0_2

DDBIB0_1

DDBIB0_2

CLKB0 CLKB0# CKEB0

MAB0_8

MAB0_7 MAB0_6 MAB0_5 MAB0_4

MAB0_3 MAB0_2 MAB0_1 MAB0_0

ADBIB0 RASB0# CSB0#_0 CASB0# WEB0#

WCKB0B_0 WCKB0_0

WCKB0B_1 WCKB0_1

VREFD5_1 VREFD5_2 VREFC5

DRAM_RST#

+1.35V_MEM_GFX

0.1U_0402_10V7K

CV384

CV286

1

2

DIS@CV286

DIS@

DIS@CV384

DIS@

2.37K_0402_1%

RV6

DIS@RV6

DIS@

5.49K_0402_1%

RV5

DIS@RV5

DIS@

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

J5

A12/RFU/NC

K4

A8/A7 A10/A0

K5

A11/A6 A9/A1

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

H11

BA0/A2 BA2/A4

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WC K23#

D4

WCK01 WCK2 3

P5

WCK23# WC K01#

P4

WCK23 WCK0 1

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

SGRAM GDDR5

K4G20325FC-HC05_FBGA170~D

DIS@

EDCB0_1<53>

D D

C C

B B

A A

+1.35V_MEM_GFX

1U_0402_6.3V6K

2.37K_0402_1%

12

CV18

RV1

1

DIS@CV18

DIS@

DIS@RV1

DIS@

2

5.49K_0402_1%

1U_0402_6.3V6K

12

RV2

CV13

1

DIS@RV2

DIS@

DIS@CV13

DIS@

2

+1.35V_MEM_GFX +1.35V_MEM_GFX

2.37K_0402_1%

1U_0402_6.3V6K

12

RV3

CV19

1

DIS@RV3

DIS@

DIS@CV19

DIS@

2

5.49K_0402_1%

1U_0402_6.3V6K

12

RV4

CV20

1

DIS@RV4

DIS@

DIS@CV20

DIS@

2

EDCB0_2<53>

DDBIB0_1<53>

+1.35V_MEM_GFX

DDBIB0_2<53>

+1.35V_MEM_GFX

CLKB0<53> CLKB0#<53> CKEB0<53>

MAB0_8<53>

MAB0_7<53> MAB0_6<53> MAB0_5<53> MAB0_4<53>

MAB0_3<53> MAB0_2<53> MAB0_1<53> MAB0_0<53>

1 2

RV163 121_0402_1%DIS@ RV163 121_0402_1%DIS@

ADBIB0<53> RASB0#<53> CSB0#_0<53> CASB0#<53> WEB0#<53>

WCKB0B_0<53> WCKB0_0<53>

WCKB0B_1<53> WCKB0_1<53>

1U_0402_6.3V6K

10U_0603_6.3V6M

CV4

1

CV280

DIS@CV4

DIS@

2

DIS@

1

2

VREFD5_2 VREFC5

1

2

5

NORMAL

MF=0 MF=1 MF=0MF=1

170-BALL

4

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

DQB0_14 DQB0_12 DQB0_15 DQB0_13 DQB0_10 DQB0_11 DQB0_9 DQB0_8

DQB0_14 <53> DQB0_12 <53> DQB0_15 <53> DQB0_13 <53> DQB0_10 <53> DQB0_11 <53> DQB0_9 <53> DQB0_8 <53>

+1.35V_MEM_GFX

B_1

DQB0_22 DQB0_21 DQB0_23 DQB0_20 DQB0_19 DQB0_18 DQB0_16 DQB0_17

DQB0_22 <53> DQB0_21 <53> DQB0_23 <53> DQB0_20 <53> DQB0_19 <53> DQB0_18 <53> DQB0_16 <53> DQB0_17 <53>

B_2

+1.35V_MEM_GFX

2.37K_0402_1%

1U_0402_6.3V6K

12

RV8

CV24

1

DIS@RV8

DIS@

DIS@CV24

DIS@

2

1U_0402_6.3V6K

5.49K_0402_1%

12

CV23

RV7

1

DIS@CV23

DIS@

DIS@RV7

DIS@

2

1U_0402_6.3V6K

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

0.1U_0402_10V7K

CV5

1

DIS@CV5

DIS@

2

+1.35V_MEM_GFX +1.35V_MEM_GFX

1U_0402_6.3V6K

CV26

1

DIS@CV26

DIS@

2

1U_0402_6.3V6K

CV25

1

DIS@CV25

DIS@

2

0.1U_0402_10V7K

CV284

1

CV292

DIS@

2

12

RV10

DIS@RV10

DIS@

12

RV9

DIS@RV9

DIS@

1

CV294

DIS@

2

DIS@CV284

DIS@

2.37K_0402_1%

VREFD6_2 VREFC6

5.49K_0402_1%

3

EDCB0_3<53>

EDCB0_0<53>

DDBIB0_3<53>

DDBIB0_0<53>

+1.35V_MEM_GFX

DRAM_RST#<53,54,55,57>

0.1U_0402_10V7K

CV281

CV297

1

2

DIS@CV281

DIS@

DIS@CV297

DIS@

+1.35V_MEM_GFX

1U_0402_6.3V6K

1

CV12

2

DIS@

1

2

1

2

1 2

DIS@ RV162

DIS@

121_0402_1%

0.1U_0402_10V7K

CV291

1

2

DIS@CV291

DIS@

1U_0402_6.3V6K

1

CV293

2

DIS@

1U_0402_6.3V6K

12

CV28

DIS@CV28

DIS@

1U_0402_6.3V6K

12

CV27

DIS@CV27

DIS@

RV162

0.1U_0402_10V7K

RV12

DIS@RV12

DIS@

RV11

DIS@RV11

DIS@

CV385

DIS@CV385

DIS@

2.37K_0402_1%

5.49K_0402_1%

EDCB0_3

EDCB0_0

DDBIB0_3

DDBIB0_0

CLKB0 CLKB0# CKEB0

MAB0_8

MAB0_0 MAB0_1 MAB0_3 MAB0_2

MAB0_5 MAB0_4 MAB0_6 MAB0_7

ADBIB0 CASB0# WEB0# RASB0# CSB0#_0

WCKB0B_1 WCKB0_1

WCKB0B_0 WCKB0_0

VREFD6_1 VREFD6_2 VREFC6

DRAM_RST#

0.1U_0402_10V7K

1

2

MIRROR

MF=0 MF=1 MF=0MF=1

170-BALL

2

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

DQB0_24 DQB0_27 DQB0_25 DQB0_26 DQB0_28 DQB0_30 DQB0_31 DQB0_29

DQB0_2 DQB0_1 DQB0_3 DQB0_0 DQB0_4 DQB0_7 DQB0_6 DQB0_5

+1.35V_MEM_GFX

DQB0_24 <53> DQB0_27 <53> DQB0_25 <53> DQB0_26 <53> DQB0_28 <53> DQB0_30 <53> DQB0_31 <53> DQB0_29 <53>

B_3

DQB0_2 <53> DQB0_1 <53> DQB0_3 <53> DQB0_0 <53> DQB0_4 <53> DQB0_7 <53> DQB0_6 <53> DQB0_5 <53>

B_0

1U_0402_6.3V6K

1

CV290

2

DIS@

1U_0402_6.3V6K

0.1U_0402_10V7K

CV386

1

CV283

2

DIS@

DIS@CV386

DIS@

A4

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

MARX-VRAM_B Lower_UV7,UV8

LA-9984P

1

0.1U_0402_10V7K

1

2

56 57Wednesday, May 22, 2013

0.1U_0402_10V7K

CV285

DIS@CV285

DIS@

CV296

CV288

1

2

DIS@CV296

DIS@

DIS@CV288

DIS@

1.0

of

A

Memory Partition B - Upper 16 bits

UV9

MF=0 MF=1 MF=0MF=1

C2

EDCB1_2<53>

EDCB1_1<53>

1 1

+1.35V_MEM_GFX

2.37K_0402_1%

1U_0402_6.3V6K

2 2

3 3

4 4

12

RV14

CV30

1

DIS@RV14

DIS@

DIS@CV30

DIS@

2

1U_0402_6.3V6K

5.49K_0402_1%

12

CV29

RV13

1

DIS@CV29

DIS@

DIS@RV13

DIS@

2

+1.35V_MEM_GFX +1.35V_MEM_GFX

1U_0402_6.3V6K

12

CV32

1

DIS@CV32

DIS@

2

1U_0402_6.3V6K

12

CV31

1

DIS@CV31

DIS@

2

DDBIB1_2<53>

+1.35V_MEM_GFX

DDBIB1_1<53>

+1.35V_MEM_GFX

CLKB1<53> CLKB1#<53> CKEB1<53>

MAB1_8<53>

MAB1_0<53> MAB1_1<53> MAB1_3<53> MAB1_2<53>

MAB1_5<53> MAB1_4<53> MAB1_6<53> MAB1_7<53>

+1.35V_MEM_GFX

1 2

RV169 121_0402_1%DIS@ RV169 121_0402_1%DIS@

ADBIB1<53> CASB1#<53> WEB1#<53> RASB1#<53> CSB1#_0<53>

WCKB1B_1<53> WCKB1_1<53>

WCKB1B_0<53> WCKB1_0<53>

1U_0402_6.3V6K

10U_0603_6.3V6M

CV7

1

2

2.37K_0402_1%

RV16

DIS@RV16

DIS@

5.49K_0402_1%

RV15

DIS@RV15

DIS@

1

CV304

DIS@CV7

DIS@

2

DIS@

VREFD7_2 VREFC7

A

EDCB1_2

EDCB1_1

DDBIB1_2

DDBIB1_1

CLKB1 CLKB1# CKEB1

MAB1_8

MAB1_0 MAB1_1 MAB1_3 MAB1_2

MAB1_5 MAB1_4 MAB1_6 MAB1_7

ADBIB1 CASB1# WEB1# RASB1# CSB1#_0

WCKB1B_1 WCKB1_1

WCKB1B_0 WCKB1_0

VREFD7_1 VREFD7_2 VREFC7

DRAM_RST#

+1.35V_MEM_GFX

0.1U_0402_10V7K

CV318

CV307

1

CV313

2

DIS@

DIS@CV318

DIS@

DIS@CV307

DIS@

1U_0402_6.3V6K

12

CV34

RV19

1

DIS@CV34

DIS@

DIS@RV19

DIS@

2

1U_0402_6.3V6K

12

RV17

CV33

1

DIS@RV17

DIS@

DIS@CV33

DIS@

2

C13 R13

R2

D2 D13 P13

P2

J12 J11

K4

K5 K10 K11

H10 H11

H5

H4

A5

U5

J10 J13

G3 G12

L3

L12

D5

D4

P5

P4

A10

U10

J14

G1

L1

G4

L4

C5

R5 C10 R10 D11 G11

L11 P11 G14

L14

H1 K1 B5 G5 L5

T5 B10 D10 G10

L10

P10

T10 H14 K14

2.37K_0402_1%

5.49K_0402_1%

EDC0 EDC3 EDC1 EDC2 EDC2 EDC1 EDC3 EDC0

DBI0# DBI3# DBI1# DBI2# DBI2# DBI1# DBI3# DBI0#

CK CK#

J3

CKE#

J5

A12/RFU/NC

A8/A7 A10/A0 A11/A6 A9/A1 BA1/A5 BA3/A3 BA2/A4 BA0/A2

BA3/A3 BA1/A5 BA0/A2 BA2/A4 A9/A1 A11/A6 A10/A0 A8/A7

VPP/NC VPP/NC

J1

MF SEN ZQ

J4

ABI# RAS# CAS# CS# WE# CAS# RAS# WE# CS#

WCK01# WC K23# WCK01 WCK2 3

WCK23# WC K01# WCK23 WCK0 1

VREFD VREFD VREFC

J2

RESET#

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

170-BALL

SGRAM GDDR5

K4G20325FC-HC05_FBGA170~D

DIS@

MIRROR

B

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

+1.35V_MEM_GFX

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

DQB1_16 DQB1_18 DQB1_17 DQB1_19 DQB1_20 DQB1_22 DQB1_23 DQB1_21

DQB1_16 <53> DQB1_18 <53> DQB1_17 <53> DQB1_19 <53> DQB1_20 <53> DQB1_22 <53> DQB1_23 <53> DQB1_21 <53>

B_2

DQB1_8

DQB1_10 DQB1_12 DQB1_9 DQB1_14 DQB1_15 DQB1_13

DQB1_8 <53>

DQB1_10 <53> DQB1_12 <53> DQB1_9 <53> DQB1_14 <53> DQB1_15 <53> DQB1_13 <53>

B_1

+1.35V_MEM_GFX

1U_0402_6.3V6K

2.37K_0402_1%

12

CV36

RV21

1

DIS@CV36

DIS@

DIS@RV21

DIS@

2

5.49K_0402_1%

1U_0402_6.3V6K

12

RV20

CV35

1

DIS@RV20

DIS@

DIS@CV35

DIS@

2

1U_0402_6.3V6K

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

CV6

1

CV299

DIS@CV6

DIS@

2

DIS@

+1.35V_MEM_GFX +1.35V_MEM_GFX

1U_0402_6.3V6K

12

CV38

1

DIS@CV38

DIS@

2

1U_0402_6.3V6K

12

CV37

1

DIS@CV37

DIS@

2

0.1U_0402_10V7K

CV391

1

CV302

2

DIS@

DIS@CV391

DIS@

2.37K_0402_1%

RV23

DIS@RV23

DIS@

VREFD8_2 VREFC8

5.49K_0402_1%

RV22

DIS@RV22

DIS@

C

+1.35V_MEM_GFX

CV301

1

2

DIS@CV301

DIS@

C

D

UV10

MF=0 MF=1 MF=0MF=1

C2

1 2

+1.35V_MEM_GFX

0.1U_0402_10V7K

CV308

1

2

DIS@

2.37K_0402_1%

12

RV27

DIS@RV27

DIS@

5.49K_0402_1%

12

RV24

DIS@RV24

DIS@

1

2

EDCB1_0

EDCB1_3

DDBIB1_0

DDBIB1_3

CLKB1 CLKB1# CKEB1

MAB1_8

MAB1_7 MAB1_6 MAB1_5 MAB1_4

MAB1_3 MAB1_2 MAB1_1 MAB1_0

ADBIB1 RASB1# CSB1#_0 CASB1# WEB1#

WCKB1B_0 WCKB1_0

WCKB1B_1 WCKB1_1

VREFD8_1 VREFD8_2 VREFC8

DRAM_RST#

0.1U_0402_10V7K

CV316

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

J5

A12/RFU/NC

K4

A8/A7 A10/A0

K5

A11/A6 A9/A1

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

H11

BA0/A2 BA2/A4

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WC K23#

D4

WCK01 WCK2 3

P5

WCK23# WC K01#

P4

WCK23 WCK0 1

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

170-BALL

SGRAM GDDR5

K4G20325FC-HC05_FBGA170~D

DIS@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

EDCB1_0<53>

EDCB1_3<53>

DDBIB1_0<53>

DDBIB1_3<53>

RV171 121_0402_1%DIS@RV171 121_0402_1%DIS@

DRAM_RST#<53,54,55,56>

0.1U_0402_10V7K

CV319

CV305

1

2

DIS@CV319

DIS@

DIS@CV305

DIS@

1U_0402_6.3V6K

1

CV392

CV311

2

DIS@

1U_0402_6.3V6K

CV40

1

DIS@CV40

DIS@

2

1U_0402_6.3V6K

CV39

1

DIS@CV39

DIS@

2

NORMAL

A4

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

DQB1_5 DQB1_6 DQB1_4 DQB1_7 DQB1_2 DQB1_3 DQB1_0 DQB1_1

DQB1_31 DQB1_30 DQB1_29 DQB1_28 DQB1_27 DQB1_26DQB1_11 DQB1_24 DQB1_25

+1.35V_MEM_GFX

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

MARX-VRAM_B Upper_UV9,UV10

DQB1_5 <53> DQB1_6 <53> DQB1_4 <53> DQB1_7 <53> DQB1_2 <53> DQB1_3 <53> DQB1_0 <53> DQB1_1 <53>

B_0

DQB1_31 <53> DQB1_30 <53> DQB1_29 <53> DQB1_28 <53> DQB1_27 <53> DQB1_26 <53>DQB1_11 <53> DQB1_24 <53> DQB1_25 <53>

B_3

DIS@

1U_0402_6.3V6K

1

CV298

2

LA-9984P

E

DIS@

0.1U_0402_10V7K

CV315

1

CV310

2

57 57Wednesday, May 22, 2013

E

DIS@

0.1U_0402_10V7K

CV312

CV306

CV303

1

2

1.0

of