Compal LA-9941P VAUB0, XPS 15 Schematic

A

B

C

D

E

MODEL NAME :

PCB NO :

VAUB0

LA-9941P DAA0006W000

BOM P/N :

1 1

ZZZ

PCB

R1@

TBD

ZZZ

PCB

R3@

Dell/Compal Confidential

Schematic Document

Phantom(Shark Bay)

Hasweill(BGA) + Lynx Point

DISCRETE VGA N14P(optimus) --- Testarossa

2 2

DISCRETE VGA N15P(optimus) --- Testarossa-P

201

3-01-02

Rev: 0.1 (X00)

U6

R3@

CPU

UV1

N15R3@

3 3

N15P-Q1

R3@

N14R3@

U7

PCH

UV1

N14P-GT

R1@

N15R1@

U6

CPU

UV1

N15P-Q1

R1@

N14R1@

U7

PCH

UV1

CONN@ : Connector Component

N14P-GT

@ : Nopop Component

TPM@ : TPM function

DSP@ : DSP function N14@ : DGPU N14P-GT N15@ : DGPU N15P-Q1

Samsung 2G

UV5

K4G41325FC-HC04_FBGA170P~D

VRAMSR3@

UV9

K4G41325FC-HC04_FBGA170P~D

VRAMSR3@

UV6

K4G41325FC-HC04_FBGA170P~D

VRAMSR3@

UV10

K4G41325FC-HC04_FBGA170P~D

VRAMSR3@

Hynix 2G

UV5

4 4

H5GC4H24MFR-T2C_FBGA170P~D

VRAMHR3@

UV9

H5GC4H24MFR-T2C_FBGA170P~D

VRAMHR3@

UV6

H5GC4H24MFR-T2C_FBGA170P~D

VRAMHR3@

UV10

H5GC4H24MFR-T2C_FBGA170P~D

VRAMHR3@

A

Samsung 2G

UV5

K4G41325FC-HC04_FBGA170P~D

VRAMSR1@

UV9

K4G41325FC-HC04_FBGA170P~D

VRAMSR1@

Hynix 2G

UV5

H5GC4H24MFR-T2C_FBGA170P~D

VRAMHR1@

UV9

H5GC4H24MFR-T2C_FBGA170P~D

VRAMHR1@

B

UV6

K4G41325FC-HC04_FBGA170P~D

VRAMSR1@

UV10

K4G41325FC-HC04_FBGA170P~D

VRAMSR1@

UV6

H5GC4H24MFR-T2C_FBGA170P~D

VRAMHR1@

UV10

H5GC4H24MFR-T2C_FBGA170P~D

VRAMHR1@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/08/25 2011/08/25

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Cover Page

LA-9941P

E

1 62Wednesday, September 04, 2013

0.1

A

128M*16 x4 =1G

VRAM * 4 GD

DR5

GB4-128

1 1

Mini DP

2 2

Mi

(WLAN+BT4.0)

P.37

Port 3 Por

ni Card-1 (Half)

P.42

USB2.0

Port 4

Daughter board

GPU N14P

-GT

mD

P

Redriver

Card Reader

RTS5249

Daughter board

3 in 1 Socket

P.29~30

P.24~28

P.37

t 4

SPI Flash (BIOS 8MB)

C

NF Magnetic Peak

P.

P.49

16

DP

B

PEG 3.0 x16

Intel

Ha

swell Processor 35W QC

BGA 1364

PCI-E x1

tel

In

Lynx Point LP

BG

SPI

A 695 Balls

C

Memory Bus (DDR3L)

Dual Channel

1.35V DDR3L 1600 MHz

MI

HD

eDP

P.5~13

DMI x4

100MHz 5GB/s

SATA3.0

USB 3.0

USB2.0

HDMI Redr

iver

FHD (eDP 1.3)

Port 0

Port 1

2

Port

Port 1,2

Port 12

D

DDRIII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

page 14,15

16GB Max

P.36

P.35

SATA3 Re-driver PS

8520

Mini Card-2 (mSATA)

( Full )

P.43

SATA ODD Conn.

USB 3.0 Re-driver

Di

P.45

gital Camera

P.42

P.43

Port 0,1

P.35

HDMI

HD

P.36

D

P.43

USB Powershare TPS2543 X2

CP Conn.

44

P.

U XDP

P.6

USB 3.0 Conn. X2

( USB Charger )

E

P.45

SMBus

Port 9

Touch Panel Conn.

P.

40

3 3

RTC Counter IDT 1337

RTC CKT.

Power On/Off CKT.

DC/DC Interface CKT.

4 4

P.46

P.16

P.39

P.33~34

A

FFS

P.43

Discrete TPM AT97SC3204

P.40

PWM

Fan Control

B

P.

HD Audio

P16~23

LPC Bus

33MHz

ALC5505 DSP

P.46

Digi Mic

ENE KBC KB9012 + KC3810

Int.KBD

39

Touch Pad

P.39

PS/2

P.39

P.38

SMBus

ALS Sensor

P.35

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

C

2011/08/25 2012/07/25

Audio Codec

C3661

AL

AMP TI 3113

Int. Speaker x2

Compal Secret Data

Deciphered Date

D

P.48

P.47

adphone / Mic. Jack

He

( Combo )

Compal Electronics,Inc.

Title

Size Document Number Rev

Date: Sheet

P.47

2 62Tuesday, September 03, 2013

E

2 62Tuesday, September 03, 2013

0.1C

of

A

B

C

D

E

Compal Confidential

Project Code : VAUB0 Fil

e Name : LA-9941P

1 1

JTS

LA-9941P M/B

JeDP

2 2

JHDD

6 pin

40 pin

24 pin

8 pin

Wire

FFC

Touch screen

CD Panel

L

HDD

JTB1

90 pin

Touch Pad

3 3

FFC

JIO1

I/O B

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OFC OMPALE LECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OFC OMPALE LECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OFC OMPALE LECTRONICS, INC.

C

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

E

0.1

3 62Tuesday, September 03, 2013

0.1

A

USB PORT#

0

1

2

3

PCH

4

5

6

7

8

9

10

PCI EXPRESS

DESTINATION

SATA

DESTINATION

CLKOUT

DESTINATION

11

Lane 1

None

SATA0

HDD

PCI0

PCH_LOOPBACK

12

Lane 2

None

SATA1

SSD

PCI1

EC LPC

13

1 1

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8 None

MINI CARD-1 WLAN

CARD READER

None

SATA2

SATA3

SATA4

SATA5

None

None None

None

PCI2

PCI3

PCI4

None

USB3

1

2

3

4

DESTINATION

USB Conn 1 (Power share)

USB Conn 3 (Power share)

USB Conn 2 (Power share)

USB Conn 4 (Power share)

USB Conn 1 (Power share)

USB Conn 3 (Power share)

USB Conn 2 (Power share)

USB Conn 4 (Power share)

JMINI1 (WLAN)

None

Touch screen

None

CAMERA

None

DESTINATION

CLK

DESTINATIONDIFFERENTIAL

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

CLKOUT_PCIE6

None

MINI CARD-1 WLAN

CARD READER

None

CLKOUT_PCIE7 None

CLKOUT_PEG_B

None

FLEX CLOCKS DESTINATION

CLKOUTFLEX0None

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

CLK_PCI_TPM

None

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

Symbol Note :

: means Digital Ground

: means Analog Ground

Compal Secret Data

2011/08/25 2012/07/25

A

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-9941P

0.1

4 62Tuesday, September 03, 2013

0.1

5

4

3

2

1

+3VS

SMBUS Address [0x9a]

D D

R10

U11

SMBCLK

SMBDATA

PCH

2.2K

.2K

2

SML0CLK

SML0DATA

+3V_PCH

U8

R7

K6N

11

C C

SML1CLK

SML1DATA

DMN66D0 DMN66D0

2.2K

.2K

2

+3V_PCH

+3VS

66D0

DMN

DMN66D0

2.2K

+3VS_NGFF

2.2K

+3VS

2.2K

202

DIMMA

200

202

DIMMB

200

4

5

TP

60

58

8

9

NFC

SMBUS Address [TBD]NGFF

SMBUS Address [TBD]

4

6

FFS

51

53

XDP

9

10

Touch Sc

10

ALS

9

reen

SMBUS Address [A0]

MBUS Address [A0]

S

SM

BUS Address [TBD]

SMBUS Address [TBD]

2.2K

B8

EC_SMB_CK1

A6

EC_SMB_DA1

+3VS

8

7

ADS1115

SMBUS Address [TBD]

KBC

B B

8

7

ADS1115

SMBUS Address [TBD]

2.2K

A8

EC_SMB_CK1

A7

EC_SMB_DA1

A A

5

2.2K

4

+3VALW_EC

100 ohm

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/15

4

BATT

5

9

CHARGER

8

Compal Secret Data

Deciphered Date

SMBUS Address [16]

SMBUS Address [12]

2

Compal Electronics, Inc.

Title

SMBus Block Diagram

Size Document Number Rev

Custom

Date: Sheet of

5 62Tuesday, September 03, 2013

1

0.1

5

4

3

2

1

XDP CONN

+VCCIO_OUT +VCCIO_OUT

D D

C C

The resistor

r HOOK2 should b e

fo placed such that the stub is very sma ll on CFG0 net

XDP_PREQ#[8] XDP_PRDY#[8]

CFG0[10] CFG1[10]

CFG2[10] CFG3[10]

XDP_BPM#0[8] XDP_BPM#1[8]

CFG4[10] CFG5[10]

CFG6[10] CFG7[10]

H_CPUPWRGD[20,8]

PBTN_OUT#[18,38]

CPU_PWR_DEBU G[12]

IMVP_VR_PG[18,38,58]

PCH_SMBDATA[14,15,17,39,43]

PCH_SMBCLK[14,15,17,39,43]

XDP_TCK[8]

XDP_TCK

+3VS

RU36 1K_0402_5%

1 2

RU7 1K_0402_5%~D

1 2

PT

IMVP_VR_PG

XDP_PREQ# XDP_PRDY#

CFG0 CFG1

CFG2 CFG3

XDP_BPM#0 XDP_BPM#1

CFG4 CFG5

CFG6 CFG7

H_CPUPWRGD_XD P

PT

JXDP

2

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

151516

18

171718

20

191920

22

212122

24

232324

26

252526

28

272728

30

292930

32

313132

34

333334

36

353536

38

373738

40

393940

42

414142

44

434344

46

454546

48

474748

50

494950

52

515152

54

535354

56

555556

58

575758

60

595960

SAMTE_BSH-030-01-L-D-A-TR

CONN@

CFG17 CFG16

CFG8 CFG9

CFG10 CFG11

CFG19 CFG18

CFG12 CFG13

CFG14 CFG15

CLK_CPU_ITP CLK_CPU_ITP#

XDP_RST#_R XDP_DBRESET#

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS

CFG17 [10] CFG16 [10]

CFG8 [10] CFG9 [10]

CFG10 [10] CFG11 [10]

CFG19 [10] CFG18 [10]

CFG12 [10] CFG13 [10]

CFG14 [10] CFG15 [10]

CLK_CPU_ITP [17] CLK_CPU_ITP# [17]

1 2

RU12 1K_0402_5%~D

XDP_DBRESET# [18,8]

XDP_TDO [8] XDP_TRST# [8] XDP_TDI [8] XDP_TMS [8]

PLT_RST# [18,38,40,42,8]

PT

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OFC OMPALE LECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OFC OMPALE LECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OFC OMPALE LECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

Block Diagram

1

0.1

of

6 62Tuesday, September 03, 2013

5

4

3

2

1

D D

U6A

DMI_CRX_PTX_N0[18] DMI_CRX_PTX_N1[18] DMI_CRX_PTX_N2[18] DMI_CRX_PTX_N3[18]

DMI_CRX_PTX_P0[18] DMI_CRX_PTX_P1[18] DMI_CRX_PTX_P2[18] DMI_CRX_PTX_P3[18]

DMI_CTX_PRX_N0[18] DMI_CTX_PRX_N1[18] DMI_CTX_PRX_N2[18] DMI_CTX_PRX_N3[18]

DMI_CTX_PRX_P0[18] DMI_CTX_PRX_P1[18] DMI_CTX_PRX_P2[18] DMI_CTX_PRX_P3[18]

FDI_CSYNC[18]

C C

B B

FDI_INT[18]

AB2 AB3 AC3 AC1

AB1 AB4 AC4 AC2

AF2 AF4 AG4 AG2

AF1 AF3 AG3 AG1

F11 F12

@

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

FDI_CSYNC DISP_INT

HA

SWELL_BGA1364

HASWELL_BGA

DMI

FDI

PEG_RCOMP

PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8

PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13

PEG

PEG_RXN14 PEG_RXN15

PEG_RXP0

PEG_RXP1

PEG_RXP2

PEG_RXP3

PEG_RXP4

PEG_RXP5

PEG_RXP6

PEG_RXP7

PEG_RXP8

PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15

PEG_TXN0

PEG_TXN1

PEG_TXN2

PEG_TXN3

PEG_TXN4

PEG_TXN5

PEG_TXN6

PEG_TXN7

PEG_TXN8

PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15

PEG_TXP0

PEG_TXP1

PEG_TXP2

PEG_TXP3

PEG_TXP4

PEG_TXP5

PEG_TXP6

PEG_TXP7

PEG_TXP8

PEG_TXP9

PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15

1 OF 12

PEG_COMP C

AD Note: Trace width=12 mils ,Spacing=15mil Max length= 400 mils.

AH6

PEG_COMP

E10

PEG_GTX_C_HRX_N15

C10

PEG_GTX_C_HRX_N14

B10

PEG_GTX_C_HRX_N13

E9

PEG_GTX_C_HRX_N12

D9

PEG_GTX_C_HRX_N11

B9

PEG_GTX_C_HRX_N10

L5

PEG_GTX_C_HRX_N9

L2

PEG_GTX_C_HRX_N8

M4

PEG_GTX_C_HRX_N7

L4

PEG_GTX_C_HRX_N6

M2

PEG_GTX_C_HRX_N5

V5

PEG_GTX_C_HRX_N4

V4

PEG_GTX_C_HRX_N3

V1

PEG_GTX_C_HRX_N2

Y3

PEG_GTX_C_HRX_N1

Y2

PEG_GTX_C_HRX_N0

F10

PEG_GTX_C_HRX_P15

D10

PEG_GTX_C_HRX_P14

A10

PEG_GTX_C_HRX_P13

F9

PEG_GTX_C_HRX_P12

C9

PEG_GTX_C_HRX_P11

A9

PEG_GTX_C_HRX_P10

M5

PEG_GTX_C_HRX_P9

L1

PEG_GTX_C_HRX_P8

M3

PEG_GTX_C_HRX_P7

L3

PEG_GTX_C_HRX_P6

M1

PEG_GTX_C_HRX_P5

Y5

PEG_GTX_C_HRX_P4

V3

PEG_GTX_C_HRX_P3

V2

PEG_GTX_C_HRX_P2

Y4

PEG_GTX_C_HRX_P1

Y1

PEG_GTX_C_HRX_P0

B6

PEG_HTX_GRX_N15 PEG_HTX_C_GRX_N15

C5

PEG_HTX_GRX_N14 PEG_HTX_C_GRX_N14

E6

PEG_HTX_GRX_N13 PEG_HTX_C_GRX_N13

D4

PEG_HTX_GRX_N12 PEG_HTX_C_GRX_N12

G4

PEG_HTX_GRX_N11 PEG_HTX_C_GRX_N11

E3

PEG_HTX_GRX_N10 PEG_HTX_C_GRX_N10

J5

PEG_HTX_GRX_N9 PEG_HTX_C_GRX_N9

G3

PEG_HTX_GRX_N8 PEG_HTX_C_GRX_N8

J3

PEG_HTX_GRX_N7 PEG_HTX_C_GRX_N7

J2

PEG_HTX_GRX_N6 PEG_HTX_C_GRX_N6

T6

PEG_HTX_GRX_N5 PEG_HTX_C_GRX_N5

R6

PEG_HTX_GRX_N4 PEG_HTX_C_GRX_N4

R2

PEG_HTX_GRX_N3 PEG_HTX_C_GRX_N3

R4

PEG_HTX_GRX_N2 PEG_HTX_C_GRX_N2

T4

PEG_HTX_GRX_N1 PEG_HTX_C_GRX_N1

T1

PEG_HTX_GRX_N0 PEG_HTX_C_GRX_N0

C6

PEG_HTX_GRX_P15 PEG_HTX_C_GRX_P15

B5

PEG_HTX_GRX_P14 PEG_HTX_C_GRX_P14

D6

PEG_HTX_GRX_P13 PEG_HTX_C_GRX_P13

E4

PEG_HTX_GRX_P12 PEG_HTX_C_GRX_P12

G5

PEG_HTX_GRX_P11 PEG_HTX_C_GRX_P11

E2

PEG_HTX_GRX_P10 PEG_HTX_C_GRX_P10

J6

PEG_HTX_GRX_P9 PEG_HTX_C_GRX_P9

G2

PEG_HTX_GRX_P8 PEG_HTX_C_GRX_P8

J4

PEG_HTX_GRX_P7 PEG_HTX_C_GRX_P7

J1

PEG_HTX_GRX_P6 PEG_HTX_C_GRX_P6

T5

PEG_HTX_GRX_P5 PEG_HTX_C_GRX_P5

R5

PEG_HTX_GRX_P4 PEG_HTX_C_GRX_P4

R1

PEG_HTX_GRX_P3 PEG_HTX_C_GRX_P3

R3

PEG_HTX_GRX_P2 PEG_HTX_C_GRX_P2

T3

PEG_HTX_GRX_P1 PEG_HTX_C_GRX_P1

T2

PEG_HTX_GRX_P0 PEG_HTX_C_GRX_P0

1 2

RU1 24.9_0402_1%

1 2

CU1 0.22U_0402_16V7K~D

1 2

CU2 0.22U_0402_16V7K~D

1 2

CU3 0.22U_0402_16V7K~D

1 2

CU4 0.22U_0402_16V7K~D

1 2

CU5 0.22U_0402_16V7K~D

1 2

CU6 0.22U_0402_16V7K~D

1 2

CU7 0.22U_0402_16V7K~D

1 2

CU8 0.22U_0402_16V7K~D

1 2

CU9 0.22U_0402_16V7K~D

1 2

CU10 0.22U_0402_16V7K~D

1 2

CU11 0.22U_0402_16V7K~D

1 2

CU12 0.22U_0402_16V7K~D

1 2

CU13 0.22U_0402_16V7K~D

1 2

CU14 0.22U_0402_16V7K~D

1 2

CU15 0.22U_0402_16V7K~D

1 2

CU16 0.22U_0402_16V7K~D

1 2

CU17 0.22U_0402_16V7K~D

1 2

CU18 0.22U_0402_16V7K~D

1 2

CU19 0.22U_0402_16V7K~D

1 2

CU20 0.22U_0402_16V7K~D

1 2

CU21 0.22U_0402_16V7K~D

1 2

CU22 0.22U_0402_16V7K~D

1 2

CU23 0.22U_0402_16V7K~D

1 2

CU24 0.22U_0402_16V7K~D

1 2

CU25 0.22U_0402_16V7K~D

1 2

CU26 0.22U_0402_16V7K~D

1 2

CU27 0.22U_0402_16V7K~D

1 2

CU28 0.22U_0402_16V7K~D

1 2

CU29 0.22U_0402_16V7K~D

1 2

CU30 0.22U_0402_16V7K~D

1 2

CU31 0.22U_0402_16V7K~D

1 2

CU32 0.22U_0402_16V7K~D

+VCCIOA_OUT

PEG_GTX_C_HRX_N[0..15]

PEG_GTX_C_HRX_P[0..15]

PEG_HTX_C_GRX_N[0..15]

PEG_HTX_C_GRX_P[0..15]

PEG_GTX_C_HRX_N[0..15] [24]

PEG_GTX_C_HRX_P[0..15] [24]

PEG_HTX_C_GRX_N[0..15] [24]

PEG_HTX_C_GRX_P[0..15] [24]

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(1/7) DMI,FDI,PEG

of

7 62Tuesday, September 03, 2013

1

7 62Tuesday, September 03, 2013

0.1

5

4

3

2

1

DDR3L Compensation Signals

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

CAD Note: Tr

ace width=12~1 5 mil, Spcing=2 0 mils

Max trace leng th= 500 mil

1 2

RU58 100_0402_1%~D

1 2

RU59 75_0402_1%~D

1 2

RU61 100_0402_1%~D

PU/PD for JTAG signals

XDP_TDO

XDP_TCK

XDP_TRST#

XDP_DBRESET#

+VCCIOA_OUT

EDP_COMP CAD Note:Trace width=20 mils ,Spacing=25mil , Max length=100 mils.

VCIN0_PH[38]

100K_0402_1%_TSM0B104F4251RZ

1 2

RU66 51_0402_5%

1 2

RU67 51_0402_5%

1 2

RU68 51_0402_5%

1 2

RU35 1K_0402_5%~D

HU101

+VCCP

+3VS

+3VALW

ST

RU118 10K_0402_1%~D

1 2

12

close CPU chip

WELL_BGA1364

HASWELL_BGA

MISC

THERMAL CLOCK

PWR

2 OF 12

SM_RCOMP0 SM_RCOMP1

DDR3L

SM_RCOMP2

SM_DRAMRST

JTAG

PRDY PREQ

TRST

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

TCK TMS

TDO DBR

C25 D25 A25 B25 C24 D24 A24 B24

C21 D21 A21 B21 C20 D20 A20 B20

C16 D16 A16 B16

C17 D17 A17 B17

TDI

@

BB51

SM_RCOMP0

BB53

SM_RCOMP1

BB52

SM_RCOMP2

BE51

H_DRAMRST#

N53

XDP_PRDY#

N52

XDP_PREQ#

N54

XDP_TCK

M51

XDP_TMS

M53

XDP_TRST#

N49 M49 F53

XDP_DBRESET#

R51 R50 P49 N50 R49 P53 U51 P51

For ESD concern, please put near CPU

WELL_BGA1364

HASWELL_BGA

EDP_RCOMP

EDP_DISP_UTIL

10 OF 12

U6J

DDIB_TXN0 DDIB_TXP0 DDIB_TXN1 DDIB_TXP1 DDIB_TXN2 DDIB_TXP2 DDIB_TXN3 DDIB_TXP3

DDIC_TXN0 DDIC_TXP0 DDIC_TXN1 DDIC_TXP1 DDIC_TXN2 DDIC_TXP2 DDIC_TXN3 DDIC_TXP3

DDID_TXN2 DDID_TXP2 DDID_TXN3 DDID_TXP3

DDID_TXN0 DDID_TXP0 DDID_TXN1 DDID_TXP1

HAS

EDP_AUXN

EDP_AUXP

EDP_HPD

EDP_TXN0 EDP_TXN1 EDP_TXP0 EDP_TXP1

FDI_TXN0 FDI_TXP0 FDI_TXN1 FDI_TXP1

XDP_PRDY# [6] XDP_PREQ# [6] XDP_TCK [6] XDP_TMS [6] XDP_TRST# [6]

XDP_TDI [6] XDP_TDO [6]

XDP_DBRESET# [18,6]

XDP_BPM#0 [6] XDP_BPM#1 [6]

F15 F14 E14

C14 A12 D14 B12

AG6

EDP_COMP

E12

C12 D12 A14 B14

EDP_AUXN [35] EDP_AUXP [35] EDP_HPD [35]

EDP_TXN0 [35] EDP_TXN1 [35] EDP_TXP0 [35] EDP_TXP1 [35]

1 2

RU2 24.9_0402_1%

EDP_TXN2 [35] EDP_TXP2 [35] EDP_TXN3 [35] EDP_TXP3 [35]

Processor Pullups

+VCCIO_OUT

H_THERMTRIP#[20]

H_CPUPWRGD[20,6]

+VCCP+3VS

1 2

H_PECI[38]

H_PM_SYNC[18]

CPU_PLTRST#[20]

RU13 1K_0402_5%~D

1 2

RU48 43_0402_1%@

RU11 20K_0402_5%~D

DPLL_REF_CLK#[17]

DPLL_REF_CLK[17] CLK_CPU_SSC_DPLL#[17] CLK_CPU_SSC_DPLL[17]

CLK_CPU_DMI#[17] CLK_CPU_DMI[17]

1 2

RU30 62_0402_5%

D D

C C

B B

place RU33,RU30 near CPU

1 2

RU33 10K_0402_5%~D

+VCCIO_OUT

1 2

RU40 10K_0402_5%~D@

1 2

RU44 10K_0402_5%~D@

SSC CLOCK TERMINATION, IF NOT USED, stuff RU40,RU44

Buffered reset to CPU

CAD Note: PLACE PULL-UP RESISTOR WITHIN 2 INCH OF THE CPU

PLT_RST#[18,38,40,42,6]

PLT_RST#

H_PROCHOT#

H_CPUPWRGD

CLK_CPU_SSC_DPLL

CLK_CPU_SSC_DPLL#

+3VS

5

UU2

1

P

NC

Y

2

A

G

SN74LVC1G07DCKR_SC70-5

3

H_PROCHOT#[38,53,58]

12

RU42

@

75_0402_5%

4

PT

1 2

RU32 56_0402_5%

BUF_CPU_RST#BUFO_CPU_RST#

PM_SYS_PWRGD_BUF_R

CLK_CPU_SSC_DPLL# CLK_CPU_SSC_DPLL

RU37 0_0402_5%@

1 2

ST

H_PROCHOT#_RH_PROCHOT#

BUF_CPU_RST#

C51

G50 G51

E50 D53

D52

F50

AP48

L54

AC6 AE6

V6

Y6 AB6 AA6

@

HDMI_A2N_VGA[36] HDMI_A2P_VGA[36] HDMI_A1N_VGA[36] HDMI_A1P_VGA[36] HDMI_A0N_VGA[36] HDMI_A0P_VGA[36] HDMI_A3N_VGA[36] HDMI_A3P_VGA[36]

mDP_A0N_CPU[37] mDP_A0P_CPU[37] mDP_A1N_CPU[37] mDP_A1P_CPU[37] mDP_A2N_CPU[37] mDP_A2P_CPU[37] mDP_A3N_CPU[37] mDP_A3P_CPU[37]

U6B

PROC_DETECT

CATERR PECI

PROCHOT THERMTRIP

PM_SYNC PWRGOOD SM_DRAMPWROK PLTRSTIN

DPLL_REF_CLKN DPLL_REF_CLKP SSC_DPLL_REF_CLKN SSC_DPLL_REF_CLKP BCLKN BCLKP

HAS

SM_DRAMPWROK

NOTE: S3 POWER REDUCTION IS NOT POR THIS CIRCUIT IS FOR INTERNAL TESTING PURPOSES ONLY.

+1.35V_PWROK[55]

DRAMRST_CNTRL_S3

PT

+V1.05S_VCCP_PWRGOOD[38,56]

A A

PM_DRAM_PWRGD[18]

PM_SYS_PWRGD_BUF PM_SYS_PWRGD_BUF_R

QU7

BSS138-G_SOT23-3

RU50 0_0402_5%~D@

RU51 0_0402_5%~D@

ST

1 2

RU54 0_0402_5%~D@

RU53 0_0402_5%@

1 2

5

1 2

1 3

D

S

RU56 0_0402_5%~D@

G

2

CPU1.5V_S3_GATE_R

+3VALW

1 2

RU76 200_0402_5%

+3VALW

12

R29

100K_0402_5%~D

1

2

+3VALW

UU3

5

74AHC1G09GW_TSSOP5

P

B

4

O

A

G

3

4

+1.35V_CPU_VDDQ

PM_SYS_PWRGD_BUF

12

RU60

1.82K_0402_1%

R59

3.32K_0402_1%~D

12

RU43 0_0402_5%@

1 2

PM_SYS_PWRGD_BUF_R

T

S

S3 circuit:DRAM_RST# to memory should be high during S3

D

S

13

12

RU74

4.99K_0402_1%~D

DRAMRST_CNTRL_S3

DRAMRST_CNTRL_S3[14,38]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1 2

RU62 100K_0402_5%~D

2011/08/25 2012/07/25

For deep S3

Compal Secret Data

Deciphered Date

2

DDR3_DRAMRST#_RH_DRAMRST#

G

QU3

2

BSS138-G_SOT23-3

1

CU39

0.047U_0402_16V7K

2

Compal Electronics, Inc.

+1.35V

12

RU72

1K_0402_5%~D

1 2

RU73 1K_0402_5%~D

Title

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Custom

Date: Sheet of

DDR3_DRAMRST# [14,15]

1

8 62Tuesday, September 03, 2013

0.1

5

4

3

2

1

DDR_A_D[0..63][14]

D D

C C

+V_SM_VREF

B B

+V_DDR_REFA_R[14] +V_DDR_REFB_R[14]

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AH54

SA_DQ0

AH52

SA_DQ1

AK51

SA_DQ2

AK54

SA_DQ3

AH53

SA_DQ4

AH51

SA_DQ5

AK52

SA_DQ6

AK53

SA_DQ7

AN54

SA_DQ8

AN52

SA_DQ9

AR51

SA_DQ10

AR53

SA_DQ11

AN53

SA_DQ12

AN51

SA_DQ13

AR52

SA_DQ14

AR54

SA_DQ15

AV52

SA_DQ16

AV53

SA_DQ17

AY52

SA_DQ18

AY51

SA_DQ19

AV51

SA_DQ20

AV54

SA_DQ21

AY54

SA_DQ22

AY53

SA_DQ23

AY47

SA_DQ24

AY49

SA_DQ25

BA47

SA_DQ26

BA45

SA_DQ27

AY45

SA_DQ28

AY43

SA_DQ29

BA49

SA_DQ30

BA43

SA_DQ31

BF14

SA_DQ32

BC14

SA_DQ33

BC11

SA_DQ34

BF11

SA_DQ35

BE14

SA_DQ36

BD14

SA_DQ37

BD11

SA_DQ38

BE11

SA_DQ39

BC9

SA_DQ40

BE9

SA_DQ41

BE6

SA_DQ42

BC6

SA_DQ43

BD9

SA_DQ44

BF9

SA_DQ45

BE5

SA_DQ46

BD6

SA_DQ47

BB4

SA_DQ48

BC2

SA_DQ49

AW3

SA_DQ50

AW2

SA_DQ51

BB3

SA_DQ52

BB2

SA_DQ53

AW4

SA_DQ54

AW1

SA_DQ55

AU3

SA_DQ56

AU1

SA_DQ57

AR1

SA_DQ58

AR4

SA_DQ59

AU2

SA_DQ60

AU4

SA_DQ61

AR2

SA_DQ62

AR3

SA_DQ63

AM6

SM_VREF

AR6

SA_DIMM_VREFDQ

AN6

SB_DIMM_VREFDQ

BC53

RSVD

@

3 OF 12

HASWELL_BGA

HA

U6C

RSVD

SA_CKN0

SA_CK0 SA_CKE0 SA_CKN1

SA_CK1 SA_CKE1 SA_CKN2

SA_CK2 SA_CKE2 SA_CKN3

SA_CK3 SA_CKE3

SA_CS#0 SA_CS#1 SA_CS#2

SA_CS#3 SA_ODT0 SA_ODT1 SA_ODT2 SA_ODT3

SA_BS0 SA_BS1 SA_BS2

SA_RAS

SA_WE

SA_CAS

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

RSVD SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

RSVD

SWELL_BGA1364

VSS

BD31 BE25 BF25 BE34 BD25 BC25 BF34 BE23 BF23 BC34 BD23 BC23 BD34

BE16 BC17 BE17 BD16 BC16 BF16 BF17 BD17 BC20 BD21 BD32

BC21 BF20 BF21 BE21

BD28 BD27 BF28 BE28 BF32 BC27 BF27 BC28 BE27 BC32 BD20 BF31 BC31 BE20 BE32 BE31

AJ52 AP53 AW52 AY46 BD12 BE7 BA3 AT2 AW39 AJ53 AP52 AW53 BA46 BE12 BD7 BA2 AT3 AW40

BA40 AY40 BA39 AY39 AV40 AU40 AV39 AU39

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

M_CLK_DDR#0 [14] M_CLK_DDR0 [14] DDR_CKE0_DIMMA [14] M_CLK_DDR#1 [14] M_CLK_DDR1 [14] DDR_CKE1_DIMMA [14]

DDR_CS0_DIMMA# [14] DDR_CS1_DIMMA# [14]

M_ODT0 [14] M_ODT1 [14]

DDR_A_BS0 [14] DDR_A_BS1 [14] DDR_A_BS2 [14]

DDR_A_RAS# [14] DDR_A_WE# [14] DDR_A_CAS# [14]

DDR_A_MA[0..15] [14]

DDR_A_DQS#[0..7] [14]

DDR_A_DQS[0..7] [14]

DDR_B_D[0..63][15]

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AC54 AC52 AE51 AE54 AC53 AC51 AE52 AE53 AU47 AU49 AV43 AV45 AU43 AU45 AV47 AV49 BC49 BE49 BD47 BC47 BD49 BD50 BE47 BF47 BE44 BD44 BC42 BF42 BF44 BC44 BD42 BE42 BA16 AU16 BA15 AV15 AY16 AV16 AY15 AU15 AU12 AY12 BA10 AU10 AV12 BA12 AY10 AV10

AU8

AU6

AM2 AM3

AM1 AM4

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48

BA8

SB_DQ49

AV6

SB_DQ50

BA6

SB_DQ51

AV8

SB_DQ52

AY8

SB_DQ53 SB_DQ54

AY6

SB_DQ55 SB_DQ56 SB_DQ57

AK1

SB_DQ58

AK4

SB_DQ59 SB_DQ60 SB_DQ61

AK2

SB_DQ62

AK3

SB_DQ63

@

4 OF 12

HASWELL_BGA

HA

SWELL_BGA1364

U6D

RSVD

SB_CKN0

SB_CK0 SB_CKE0 SB_CKN1

SB_CK1 SB_CKE1 SB_CKN2

SB_CK2 SB_CKE2 SB_CKN3

SB_CK3 SB_CKE3

SB_CS#0 SB_CS#1 SB_CS#2 SB_CS#3

SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3

SB_BS0 SB_BS1 SB_BS2

VSS

SB_RAS

SB_WE

SB_CAS

SB_MA0

SB_MA1

SB_MA2

SB_MA3

SB_MA4

SB_MA5

SB_MA6

SB_MA7

SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

RSVD SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

RSVD

AY36 AW27 AV27 AU36 AW26 AV26 AU35 BA26 AY26 AV35 BA27 AY27 AV36

BA20 AY19 AU19 AW20

AY20 BA19 AV19 AW19 AY23 BA23 BA36 AU30 AV23 AW23 AV20

BA30 AW30 AY30 AV30 AW32 AY32 AT30 AV32 BA32 AU32 AU23 AY35 AW35 AU20 AW36 BA35

AD52 AU46 BD48 BD43 AW16 AW10 AW8 AL2 BE38 AD53 AV46 BE48 BE43 AW15 AW12 AW6 AL3 BD38

BF39 BE39 BF37 BE37 BD39 BC39 BC37 BD37

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

M_CLK_DDR#2 [15] M_CLK_DDR2 [15] DDR_CKE2_DIMMB [15] M_CLK_DDR#3 [15] M_CLK_DDR3 [15] DDR_CKE3_DIMMB [15]

DDR_CS2_DIMMB# [15] DDR_CS3_DIMMB# [15]

M_ODT2 [15] M_ODT3 [15]

DDR_B_BS0 [15] DDR_B_BS1 [15] DDR_B_BS2 [15]

DDR_B_RAS# [15] DDR_B_WE# [15] DDR_B_CAS# [15]

DDR_B_MA[0..15] [15]

DDR_B_DQS#[0..7] [15]

DDR_B_DQS[0..7] [15]

+1.35V_CPU_VDDQ

12

RU83

+V_SM_VREF

2

0mil

A A

Close CPU side

5

1K_0402_1%~D

12

RU84

1K_0402_1%~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

1

0.1

9 6 2Tuesday, September 03, 2013

0.1

5

D D

12

RH30

49.9_0402_1%

C C

B B

12

RH31

49.9_0402_1%

CFG0[6] CFG1[6] CFG2[6] CFG3[6] CFG4[6] CFG5[6] CFG6[6] CFG7[6] CFG8[6]

CFG9[6] CFG10[6] CFG11[6]

CFG12[6] CFG13[6] CFG14[6] CFG15[6]

CPU_TESTLOW1

+VCC_CORE

CPU_TESTLOW0

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

B3_A3

A52_B52 A53_B53

C3_B2 B3_A3

A52_B52 A53_B53 B54_C54

BE1_BD1

BE54_BD54

BE1_BD1 BE2_BF2

BE3_BF3 BE52_BF52 BE53_BF53 BE54_BD54

BE2_BF2

BE3_BF3

4

HASWELL_BGA

BC54

BD54

BE52 BE53 BE54

AG49

A51 A52 A53

B52 B53 B54

BC1

BD1

BE1 BE2 BE3

BF2 BF3 BF4

AD49 AC49 AE49

AB49

W51

W53

A3 A4

B2 B3

BE4 BD3

G21 G24

G19

U53

R53 R52

F6

G6

F21

F51 F52 F22

L52 L53

L51

F24 F25 F20

Y50

V51

Y49 Y54 Y53

V54

L50 L49

E5

U6K

RSVD_TP RSVD_TP

RSVD_TP RSVD_TP TESTLOW_F21 VSS VSS VSS VCC

RSVD_TP RSVD_TP

RSVD_TP

RSVD_TP RSVD_TP TESTLOW_F20

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

RSVD RSVD RSVD

HAS

WELL_BGA1364

@

U6L

RSVD RSVD

RSVD RSVD RSVD

RSVD RSVD

RSVD RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

CFG_RCOMP

HASWELL_BGA

RSVD_TP RSVD_TP RSVD_TP RSVD_TP

CFG16 CFG18 CFG17 CFG19

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

RSVD

RSVD_TP RSVD_TP

RSVD RSVD RSVD

11 OF 12

VSS VSS

RSVD RSVD RSVD

RSVD RSVD

RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

F1 E1 A5 A6

R54 Y52 V53 Y51 V52

B50 AH49 AM48 AU27 AU26 BD4 BC4 AL6 F8

F16

G12 G10

H54 H53

H51 H52

N51 G53 H50

CFG_RCOMP CFG16 CFG18 CFG17 CFG19

BF51 BF52 BF53

C1 C2 C3

C54 D1

D54

AN35 AN37 AF9 AE9 G14 G17 AD45 AG45

3

BE52_BF52 BE53_BF53

C1_C2 C1_C2 C3_B2

B54_C54

CFG16 [6] CFG18 [6] CFG17 [6] CFG19 [6]

2

CFG Straps for Processor

CFG2

12

RH27

49.9_0402_1%

PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS

CFG2

*

Display Port Presence Strap

CFG4

*

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

CFG[6:5]

10: x8, x8 - Device 1 function 1 enabled ; function 2

01: Reserved - (Device 1 function 1 disabled ; function

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

12

RU77

1K_0402_1%~D

1: Normal Operation; Lane # definition matches socket pin map definition

0:

Lane Reversed

CFG4

12

RU115

1K_0402_1%~D

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is co

nnected to the Embedded Display Port

CFG6

CFG5

12

RU85

@

1K_0402_1%~D

disabled

2 enabled)

CFG7

12

RU87

@

1K_0402_1%~D

12

RU86

@

1K_0402_1%~D

1

PEG DEFER TRAINING

HAS

WELL_BGA1364

A A

5

@

4

12 OF 12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

CFG7

Deciphered Date

(Default) PEG Train immediately following xxRESETB

1: de assertion

0: PEG Wait for BIOS for training

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

0.1

10 62Tuesday, September 03, 2013

1

10 62Tuesday, September 03, 2013

0.1

5

4

3

2

1

55A

AB45

VCC

AB46

VCC

AB8

VCC

AC46

VCC

AC47

VCC

AC8

VCC

AC9

VCC

AD46

VCC

AD8

VCC

D D

C C

B B

A A

AE46 AE47

AG46

AH46 AH47

AJ45 AJ46 AK46 AK47

AL45 AL46

AM46 AM47

AN10 AN12 AN13 AN14 AN15 AN16 AN17 AN19 AN20 AN21 AN23 AN24 AN25 AN26 AN27 AN29 AN30 AN32 AN34 AN36 AN38 AN39 AN40 AN41 AN42 AN43 AN44 AN45 AN46

AP10 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP29 AP30 AP31 AP32 AP33 AP34 AP35 AP36 AP37 AP38 AP39 AP40 AP41 AP42 AP43 AP44 AP46 AP47

AR35 AR37 AR39 AR41 AR43 AR45 AR46

VCC VCC

AE8

VCC

AF8

VCC VCC

AG8

VCC VCC VCC

AH8

VCC VCC VCC VCC VCC

AK8

VCC VCC VCC

AL8

VCC

AL9

VCC VCC VCC

AM8

VCC

AM9

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

AN8

VCC

AN9

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

AP8

VCC

AP9

VCC VCC VCC VCC VCC VCC VCC VCC

H30

VCC

H31

VCC

H32

VCC

@

HAS

WELL_BGA1364

6 OF 12

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

HASWELL_BGA

U6F

H33 H34 H36 H37 H38 H39 H40 H42 H43 H45 H46 H48 H8 H9 J10 J14 J19 J24 J29 J33 J36 J37 J38 J39 J40 J42 J43 J45 J46 J48 J8 J9 K38 K40 K43 K44 K45 K46 K48 K8 K9 L37 L38 L39 L40 L42 L43 L44 L46 L47 L8 M37 M38 M39 M40 M42 M43 M44 M45 M46 M8 M9 N37 N38 N39 N40 N42 N43 N44 N46 N47 N8 N9 P45 P46 P8 R46 R47 R8 R9 T45 T46 U46 U47 U8 U9 V45 V46 V8 W46 W47 W8 Y45 Y46 Y8 A27 A28 A31 A32 A34 B27 B28 B31 B32 B34 B36 B38 B39 B42

+VCC_CORE+VCC_CORE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Title

PROCESSOR(5/7) PWR,BYPASS

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

11 62Tuesday, September 03, 2013

1

0.1

5

+1.35V_CPU_VDDQ +1.35V

12

CU177 0.1U_0402_10V7K~D

12

CU178 0.1U_0402_10V7K~D

D D

C C

+VCCP +VCCIO2PCH

RESISTOR STUFFING OPTIONS ARE PROVIDED FOR TESTING PURPOSES

+VCCIO_OUT

B B

+1.35V_CPU_VDDQ Source

4

10U_0603_6.3V6M~D

1

2

1U_0402_6.3V6K~D

CU192

1

2

+VCCIO_OUT

CAD Note: CU36 SHOULD BE PLACED CLOSE T O CPU

4210mA

JP3

@

1 2

PAD-OPEN 4x4m

JP4

@

1 2

PAD-OPEN 4x4m

ST

1 2

R58 0_0805_5%@

1 2

RU91 75_0402_5%

1 2

RU90 130_0402_1%~D

CAD Note: Plac e the PU resist ors close to C PU RU90/RU91 clos e to CPU 300 - 1500mils

+1.35V +1.35V_CPU_VDDQ

10U_0603_6.3V6M~D

1

CU169

CU170

2

1U_0402_6.3V6K~D

CU194

CU193

1

2

CU36

0.01U_0402_16V7K~D

1

+VCCIO2PCH

10U_0603_6.3V6M~D

1

2

1U_0402_6.3V6K~D

1

2

30mA

VR_SVID_ALRT#

VR_SVID_DAT

3

+1.35V_CPU_VDDQ

10U_0603_6.3V6M~D

1

CU172

CU171

2

1U_0402_6.3V6K~D

CU195

CU196

1

2

10U_0603_6.3V6M~D

330U_D2_2V_Y

1

CU174

CU173

CU197

CAD Note: RU96 SHOULD BE PLAC ED CLOSE TO CP U

CU175

2

1U_0402_6.3V6K~D

CU199

CU198

1

2

VCCSENSE[58]

VR_SVID_ALRT#[58]

VR_SVID_CLK[58] VR_SVID_DAT[58]

CPU_PWR_DEBUG[6]

+VCCP

12

1

+

CU176

2

+1.35V_CPU_VDDQ

1U_0402_6.3V6K~D

CU200

1

2

RU94 150_0402_1%~D

CPU_PWR_DEBUG

CU168

1U_0402_6.3V6K~D

CU201

300mA

+VCCIOA_OUT

CPU_PWR_DEBUG

+VCC_CORE

12

+VCCIO_OUT

+1.35V_CPU_VDDQ

RU96 100_0402_1%~D

RU93 43_0402_1%

+VCC_CORE

1 2

+VCC_CORE

+VCCIO_OUT

H_CPU_SVIDALRT#VR_SVID_ALRT# VR_SVID_CLK VR_SVID_DAT

AR29 AR31 AR33 AT13 AT19 AT23 AT27 AT32 AT36

AV37 AW22 AW25 AW29 AW33

AY18

BB21

BB22

BB26

BB27

BB30

BB31

BB34

BB36

BD22

BD26

BD30

BD33

BE18

BE22

BE26

BE30

BE33

AN31

AN22

AN18

AN33

AR49

AM49

AN49

AJ49

AG50

AK49

AJ50

AP49

AB50

AP50

AD50

AM50

AA46

AA47

J17 J21 J26 J31

L6

M6

C50

AH9

D51

F17

AK6

W9 J12

J53 J52 J50

B51

F19 E52 V49 U49

W49

V50

A36 A38 A39 A42 A43 A45 A46 A48

AA8 AA9

2

U6E

RSVD RSVD RSVD RSVD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

RSVD VCC VCC RSVD RSVD

VCC_SENSE RSVD VCCIO_OUT RSVD VCOMP_OUT RSVD RSVD RSVD RSVD

VIDALERT VIDSCLK VIDSOUT

VSS PWR_DEBUG VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

HAS

@

WELL_BGA1364

HASWELL_BGA

5 OF 12

FC_D5 FC_D3

1

+VCC_CORE

B43

VCC

B45

VCC

B46

VCC

B48

VCC

C27

VCC

C28

VCC

C31

VCC

C32

VCC

C34

VCC

C36

VCC

C38

VCC

C39

VCC

C42

VCC

C43

VCC

C45

VCC

C46

VCC

C48

VCC

D27

VCC

D28

VCC

D31

VCC

D32

VCC

D34

VCC

D36

VCC

D38

VCC

D39

VCC

D42

VCC

D43

VCC

D45

VCC

D46

VCC

D48

VCC

E27

VCC

E28

VCC

E31

VCC

E32

VCC

E34

VCC

E36

VCC

E38

VCC

E39

VCC

E42

VCC

E43

VCC

E45

VCC

E46

VCC

E48

VCC

F27

VCC

F28

VCC

F31

VCC

F32

VCC

F34

VCC

F36

VCC

F38

VCC

F39

VCC

F42

VCC

F43

VCC

F45

VCC

F46

VCC

F48

VCC

G27

VCC

G29

VCC

G31

VCC

G32

VCC

G34

VCC

G36

VCC

G38

VCC

G39

VCC

G42

VCC

G43

VCC

G45

VCC

G46

VCC

G48

VCC

H11

VCC

H12

VCC

H13

VCC

H14

VCC

H16

VCC

H17

VCC

H18

VCC

H19

VCC

H20

VCC

H21

VCC

H23

VCC

H24

VCC

H25

VCC

H26

VCC

H27

VCC

H29

VCC

D5

CPU_FC_PWR

D3

CPU_FC_PWROK

T172PAD @ T173PAD @

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PROCESSOR(6/7) PWR

Size Document Number Rev

Custom

Date: Sheet of

1

12 62Tuesday, September 03, 2013

0.1

5

HASWELL_BGA

U6G

A11

VSS

A15

VSS

A19

VSS

A22

VSS

A26

VSS

A30

VSS

A33

VSS

A37

VSS

A40

VSS

A44

D D

C C

B B

A A

AA1 AA2 AA3 AA4

AA48

AA5 AA7

AB5 AB51 AB52 AB53 AB54

AB7

AB9 AC48

AC5 AC50

AC7 AD48 AD51 AD54

AD7

AD9

AE1

AE2

AE3

AE4 AE48

AE5 AE50

AE7

AF5

AF6

AF7 AG48

AG5 AG51 AG52 AG53 AG54

AG7

AG9

AH1

AH48

AH50

AH2 AH3 AH4

AH5

AH7

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

HA

SWELL_BGA1364

7 OF 12

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ48 AJ51 AJ54 AK48 AK5 AK50 AK7 AK9 AL1 AL4 AL48 AL5 AL7 AM5 AM51 AM52 AM53 AM54 AM7 AN1 AN2 AN3 AN4 AN48 AN5 AN50 AN7 AP51 AP54 AP7 AR12 AR14 AR16 AR18 AR20 AR24 AR26 AR48 AR5 AR50 AR7 AR8 AR9 AT1 AT10 AT12 AT15 AT16 AT18 AT20 AT22 AT25 AT26 AT29 AT33 AT35 AT37 AT39 AT4

4

HASWELL_BGA

U6H

AT40 AT42 AT43 AT45 AT46 AT47 AT49

AT50 AT51 AT52 AT53 AT54

AU13 AU18 AU22 AU25 AU29 AU33 AU37 AU42

AV13 AV18

AV22 AV25 AV29

AV33

AV42

AV50

AW13 AW18 AW37 AW42 AW43 AW45 AW46 AW47 AW49

AW5 AW50 AW51 AW54

AW9

AY13

AY22

AY25

AY29

AY33

AY37

AY42

AT5

AT6 AT8 AT9

AU5 AU9 AV1

AV2

AV3

AV4

AV5

AV9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

HA

SWELL_BGA1364

8 OF 12

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AY50 AY9 B11 B15 B19 B22 B26 B30 B33 B37 B40 B44 B49 B8 BA13 BA18 BA22 BA25 BA29 BA33 BA37 BA4 BA42 BA5 BA50 BA51 BA52 BA53 BA9 BB10 BB11 BB12 BB14 BB15 BB16 BB17 BB18 BB20 BB23 BB25 BB28 BB32 BB33 BB37 BB38 BB39 BB41 BB42 BB43 BB44 BB46 BB47 BB48 BB49 BB5 BB6 BB7 BB9

3

U6I

BC10

VSS

BC12

VSS

BC15

VSS

BC18

VSS

BC22

VSS

BC26

VSS

BC3

VSS

BC30

VSS

BC33

VSS

BC36

VSS

BC38

VSS

BC41

VSS

BC43

VSS

BC46

VSS

BC48

VSS

BC5

VSS

BC50

VSS

BC52

VSS

BC7

VSS

BD10

VSS

BD15

VSS

BD18

VSS

BD36

VSS

BD41

VSS

BD46

VSS

BD5

VSS

BD51

VSS

BE10

VSS

BE15

VSS

BE36

VSS

BE41

VSS

BE46

VSS

BF10

VSS

BF12

VSS

BF15

VSS

BF18

VSS

BF22

VSS

BF26

VSS

BF30

VSS

BF33

VSS

BF36

VSS

BF38

VSS

BF41

VSS

BF43

VSS

BF46

VSS

BF48

VSS

BF7

VSS

C11

VSS

C15

VSS

C19

VSS

C22

VSS

C26

VSS

C30

VSS

C33

VSS

C37

VSS

C4

VSS

C40

VSS

C44

VSS

C49

VSS

C52

VSS

C8

VSS

D11

VSS

D15

VSS

D19

VSS

D22

VSS

D26

VSS

D30

VSS

D33

VSS

D37

VSS

D40

VSS

D44

VSS

D49

VSS

D8

VSS

E11

VSS

E15

VSS

E16

VSS

E17

VSS

E19

VSS

E20

VSS

E21

VSS

E22

VSS

E24

VSS

E25

VSS

E26

VSS

E30

VSS

E33

VSS

E37

VSS

E40

VSS

E44

VSS

E49

VSS

E51

VSS

E53

VSS

E8

VSS

F2

VSS

F26

VSS

F3

VSS

F30

VSS

F33

VSS

F37

VSS

F4

VSS

F40

VSS

F44

VSS

F49

VSS

F5

VSS

G11

VSS

G13

VSS

G16

VSS

HA

SWELL_BGA1364

2

HASWELL_BGA

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS

VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF

VSS_SENSE

9 OF 12

G20 G23 G25 G26 G30 G33 G37 G40 G44 G49 G52 G54 G7 G8 G9 H44 H49 H7 J44 J49 J51 J54 J7 K1 K2 K3 K4 K5 K6 K7 L48 L7 L9 M48 M50 M52 M54 M7 N48 N7 P1 P2 P3 P4 P48 P5 P50 P52 P54 P6 P7 R48 R7 T48 U1 U2 U3 U4 U48 U5 U50 U52 U54 U6 U7 V48 V7 V9 W48 W50 W52 W54 W7 Y48 Y7 Y9

AR22 AB48 P9 G18

A49 A50 A8 B4 BA1 BA54 BB1 BB54 BD2 BD53 BF49 BF5 BF50 BF6 C53 D2 E54 F54 G1

D50

CAD Note: RU99 SHOULD BE PLACED CLOSE TO CPU

1

12

RU99 100_0402_1%~D

VSSSENSE [58]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(7/7) VSS

1

0.1

13 62Tuesday, September 03, 2013

0.1

5

DDR_A_DQS#[0..7][9]

DDR_A_DQS[0..7][9]

DDR_A_D[0..63][9]

DDR_A_MA[0..15][9]

D D

yout Note:

La Pla

ce near JDIMM1

+1.35V

1U_0402_6.3V6K~D

CD3

1

2

C C

B B

A A

+1.35V

10U_0603_6.3V6M~D

1

CD8

2

Layout Note: Place near JDIMM1.203,204

+0.675VS

1U_0402_6.3V6K~D

CD17

1

2

Layout Note: Place near JDIMM1.199

+3VS

0.1U_0402_16V7K~D

1

2

5

M1

All VREF traces should have 10 mil trace width

1U_0402_6.3V6K~D

CD4

1

2

10U_0603_6.3V6M~D

1

CD9

2

1U_0402_6.3V6K~D

CD18

1

2

2.2U_0603_6.3V6K~D

CD22

CD21

1

2

1U_0402_6.3V6K~D

CD6

CD5

1

2

10U_0603_6.3V6M~D

1

CD11

CD10

2

1U_0402_6.3V6K~D

@

CD19

CD20

1

2

10U_0603_6.3V6M~D

1

2

CD13

CD12

2

4

+V_DDR_REF

DDR_CKE0_DIMMA[9] DDR_CKE1_DIMMA [9]

330U_D2_2.5VY_R15M~D

1

CD7

+

2

DDR_CS1_DIMMA#[9]

1 2

RD8 10K_0402_5%~D

1 2

RD9 10K_0402_5%~D

4

+V_DDR_REF

0.1U_0402_16V7K~D

CD2

1

2

DDR_A_BS2[9]

M_CLK_DDR0[9] M_CLK_DDR#0[9]

DDR_A_BS0[9]

DDR_A_WE#[9] DDR_A_CAS#[9]

3

+1.35V +1.35V

JDIMM1

+V_DDR_REF

DDR_A_D4 DDR_A_D0

DDR_A_D3 DDR_A_D7

DDR_A_D9 DDR_A_D8

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D15 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D26 DDR_A_D24

DDR_A_D28 DDR_A_D29 DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10

DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

+3VS

+0.675VS

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

BELLW_80001-1021

CONN@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OFC OMPALE LECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OFC OMPALE LECTRONICS, INC.

VSS DQ4 DQ5 VSS

DQS0#

DQS0

VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

RESET#

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

CKE1

VDD

CK1

CK1#

VDD

BA1 RAS#

VDD

ODT0

VDD

ODT1

VDD

VREF_CA

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

EVENT#

SDA

SCL

VTT

GND2

BOSS2

3

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

80

A14

82 84

A11

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102 104 106 108 110 112 114

S0#

116 118 120 122

NC

124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

2

DDR_A_D1 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D2 DDR_A_D6

DDR_A_D12 DDR_A_D13

DDR3_DRAMRST#

DDR_A_D14 DDR_A_D10

DDR_A_D21 DDR_A_D20

DDR_A_D22 DDR_A_D23

DDR_A_D25 DDR_A_D30

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA# M_ODT0

M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

PCH_SMBDATA PCH_SMBCLK

+0.675VS

PCH_SMBDATA [15,17,39,43,6] PCH_SMBCLK [15,17,39,43,6]

DDR3_DRAMRST# [15,8]

M_CLK_DDR1 [9] M_CLK_DDR#1 [9]

DDR_A_BS1 [9] DDR_A_RAS# [9]

DDR_CS0_DIMMA# [9] M_ODT0 [9]

M_ODT1 [9]

0.1U_0402_16V7K~D

CD16

1

2

DRAMRST_CNTRL_S3[38,8]

M3

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

Compal Secret Data

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

For deep S3

1

All VREF traces should have 10 mil trace width

+V_DDR_REF

DRAMRST_CNTRL_S3

+V_DDR_REF

DRAMRST_CNTRL_S3

For

Title

Size Document Number Rev

Date: Sheet of

1 3

D

BSS138-G_SOT23-3

G

2

1 3

D

BSS138-G_SOT23-3

G

2

deep S3

Compal Electronics, Inc.

DDRIII DIMMA

LA-9941P

S

QD1

S

QD2

1

+V_DDR_REFA_R [9]

+V_DDR_REFB_R [9]

14 62Tuesday, September 03, 2013

0.1

5

M1

+V_DDR_REF

D D

C C

B B

A A

DDR_B_DQS#[0..7][9]

DDR_B_DQS[0..7][9]

DDR_B_D[0..63][9]

DDR_B_MA[0..15][9]

+1.35V

1U_0402_6.3V6K~D

CD26

CD25

1

2

+1.35V

10U_0603_6.3V6M~D

1

2

+0.675VS

CD31

CD30

2

Layout Note: Place near JDIMMB.203,204

1U_0402_6.3V6K~D

CD39

1

2

5

Layout Note: Place near JDIMMB

1U_0402_6.3V6K~D

CD27

1

2

10U_0603_6.3V6M~D

1

CD32

2

1U_0402_6.3V6K~D

@

CD40

CD41

1

2

All VREF traces should have 10 mil trace width

CD28

10U_0603_6.3V6M~D

1

CD33

2

1U_0402_6.3V6K~D

@

CD42

1

2

CD35

CD34

2

Layout Note:

ce near JDIMMB.199

Pla

4

+V_DDR_REF

0.1U_0402_16V7K~D

CD24

1

2

+3VS

0.1U_0402_16V7K~D

1

2

4

2.2U_0603_6.3V6K~D

CD43

CD44

1

2

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

DDR_CKE2_DIMMB[9]

DDR_CS3_DIMMB#[9]

1 2

RD16 10K_0402_5%~D

1 2

RD15 10K_0402_5%~D

+3VS

DDR_B_BS2[9]

M_CLK_DDR2[9] M_CLK_DDR#2[9]

DDR_B_BS0[9]

DDR_B_WE#[9] DDR_B_CAS#[9]

3

+1.35V +1.35V

+V_DDR_REF

DDR_B_D0 DDR_B_D1

DDR_B_D2 DDR_B_D3

DDR_B_D15 DDR_B_D8

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D13 DDR_B_D12 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_D26 DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

M_CLK_DDR2 M_CLK_DDR#2

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13

DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40

DDR_B_D42 DDR_B_D46

DDR_B_D48 DDR_B_D52

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_D62 DDR_B_D58 DDR_B_D59

+3VS

+0.675VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OFC OMPALE LECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OFC OMPALE LECTRONICS, INC.

3

2011/08/25 2012/07/25

JDIMM2

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

BELLW_80001-1021

CONN@

2

VSS

4

DQ4

6

DQ5

8

VSS

10

DQS0#

12

DQS0

14

VSS

16

DQ6

18

DQ7

20

VSS

22

DQ12

24

DQ13

26

VSS

28

DM1

30

RESET#

32

VSS

34

DQ14

36

DQ15

38

VSS

40

DQ20

42

DQ21

44

VSS

46

DM2

48

VSS

50

DQ22

52

DQ23

54

VSS

56

DQ28

58

DQ29

60

VSS

62

DQS3#

64

DQS3

66

VSS

68

DQ30

70

DQ31

72

VSS

74

CKE1

76

VDD

78

A15

80

A14

82

VDD

84

A11

86

A7

88

VDD

90

A6

92

A4

94

VDD

96

A2

98

A0

100

VDD

102

CK1

104

CK1#

106

VDD

108

BA1

110

RAS#

112

VDD

114

S0#

116

ODT0

118

VDD

120

ODT1

122

NC

124

VDD

126

VREF_CA

128

VSS

130

DQ36

132

DQ37

134

VSS

136

DM4

138

VSS

140

DQ38

142

DQ39

144

VSS

146

DQ44

148

DQ45

150

VSS

152

DQS5#

154

DQS5

156

VSS

158

DQ46

160

DQ47

162

VSS

164

DQ52

166

DQ53

168

VSS

170

DM6

172

VSS

174

DQ54

176

DQ55

178

VSS

180

DQ60

182

DQ61

184

VSS

186

DQS7#

188

DQS7

190

VSS

192

DQ62

194

DQ63

196

VSS

198

EVENT#

200

SDA

202

SCL

204

VTT

206

GND2

208

BOSS2

Compal Secret Data

Deciphered Date

2

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D14 DDR_B_D9

DDR3_DRAMRST#

DDR_B_D10

DDR_B_D20 DDR_B_D21

DDR_B_D22 DDR_B_D23

DDR_B_D28 DDR_B_D29

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D30 DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

M_CLK_DDR3 M_CLK_DDR#3

DDR_B_BS1 DDR_B_RAS#

DDR_CS2_DIMMB# M_ODT2

M_ODT3

DDR_B_D36 DDR_B_D37

DDR_B_D38 DDR_B_D39

DDR_B_D45 DDR_B_D41DDR_B_D44

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D47 DDR_B_D43

DDR_B_D53 DDR_B_D49

DDR_B_D54 DDR_B_D50DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D63

PCH_SMBDATA PCH_SMBCLK

+0.675VS

2

DDR3_DRAMRST# [14,8]

DDR_CKE3_DIMMB [9]

M_CLK_DDR3 [9] M_CLK_DDR#3 [9]

DDR_B_BS1 [9] DDR_B_RAS# [9]

DDR_CS2_DIMMB# [9] M_ODT2 [9]

M_ODT3 [9]

PCH_SMBDATA [14,17,39,43,6] PCH_SMBCLK [14,17,39,43,6]

Date: Sheet of

1

All VREF traces should have 10 mil trace width

+V_DDR_REF

0.1U_0402_16V7K~D

CD38

1

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

DDRIII DIMMB

LA-9941P

1

15 62Tuesday, September 03, 2013

0.1

5

4

3

2

1

RTC CRYSTAL

5

SM_INTRUDER#

PCH_INTVRMEN

HDA_SYNC

PT

12

RH20 210_0402_1%~D

12

RH26 100_0402_1%~D

PCH_RTCX1

PCH_RTCX2

1

CH4

18P_0402_50V8J~D

2

HDA_SPKR

HDA_SDOUT

12

RH35

51_0402_5%

+RTCVCC

1 2

RH4 20K_0402_5%~D

+RTCVCC

1 2

RH3 20K_0402_5%~D

HD Audio

HDA_BITCLK_AUDIO[46]

HDA_SYNC_AUDIO[46]

HDA_RST_AUDIO#[46,47]

HDA_SDOUT_AUDIO[46]

HDA_SDO[38]

1U_0603_10V6K~D

HDA_BITCLK_AUDIO

RH7 33_0402_5%~D

RH8 1M_0402_5%~D

4

1

CH6

CH5

1 2

12

CLRP2

SHORT PADS

2

1

12

CLRP1

SHORT PADS

2

HDA_SPKR[47]

HDA_SDIN0[46]

DP_PCH_HPD[18,37]

RH5 33_0402_5%~D

RH6 33_0402_5%~D

RH15 33_0402_5%

RH11 1K_0402_5%~D

1 2

PCH_RTCX1

PCH_RTCX2

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

PCH_RTCRST#

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDOUT

DP_PCH_HPD

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

for enable ME code programing

Reserve for EMI

1 2

CH1 10P_0402_50V8J~D@

1 2

CH2 10P_0402_50V8J~D@

Reserve for RF please close t o UH1

HDA_BIT_CLK

HDA_SDOUTPCH_JTAG_TCKPCH_JTAG_TMSPCH_JTAG_TDO PCH_JTAG_TDI

U7A

B5

RTCX1

B4

RTCX2

B9

SRTCRST#

A8

INTRUDER#

G10

INTVRMEN

D9

RTCRST#

B25

HDA_BCLK

A22

HDA_SYNC

AL10

SPKR

C24

HDA_RST#

L22

HDA_SDI0

K22

HDA_SDI1

G22

HDA_SDI2

F22

HDA_SDI3

A24

HDA_SDO

B17

DOCKEN#/GPIO33

C22

HDA_DOCK_RST #/GPIO13

AB3

JTAG_TCK

AD1

JTAG_TMS

AE2

JTAG_TDI

AD3

JTAG_TDO

F8

TP25

C26

TP22

AB6

TP20

LYNXPOINT_BGA695

@

HDA_BIT_CLK

HDA_SYNC

HDA_RST#

HDA_SDOUT

3

LPT_PCH_M_EDS

JTAGRTC AZALIA

REV = 5

SATA

1 OF 11

SATA_RXN4/PERN1 SATA_RXP4/PERP1

SATA_TXN4/PETN1

SATA_TXP4/PETP1

SATA_RXN5/PERN2 SATA_RXP5/PERP2

SATA_TXN5/PETN2

SATA_TXP5/PETP2

SATA0GP/GPIO21

SATA1GP/GPIO19

SATA_RXN_0 SATA_RXP_0

SATA_TXN_0 SATA_TXP_0

SATA_RXN_1 SATA_RXP_1

SATA_TXN_1 SATA_TXP_1

SATA_RXN_2 SATA_RXP_2

SATA_TXN_2 SATA_TXP_2

SATA_RXN_3 SATA_RXP_3

SATA_TXN_3 SATA_TXP_3

SATA_RCOMP

SATALED#

SATA_IREF

BC8 BE8

AW8 AY8

BC10 BE10

AV10

SATA_PTX_DRX_N1

AW10

SATA_PTX_DRX_P1

BB9 BD9

AY13 AW13

BC12 BE12

AR13 AT13

BD13 BB13

AV15

SATA Impedance Compensation

AW15

CAD note:

BC14

Place the resistor within 500 mils of the PCH.

BE14

Avoid routing next to clock pins.

AP15 AR15

AY5

SATA_RCOMP

AP3

PCH_SATALED#

AT1

PCH_GPIO21

AU2

BBS_BIT0

BD4

BA2

TP9

BB2

TP8

1 2

CH18 0.01U_0402_16V7K~D

1 2

CH17 0.01U_0402_16V7K~D

1 2

RH21 7.5K_0402_1%~D

1 2

RH14 10K_0402_5%~D@

1 2

RH12 10K_0402_5%~D

1 2

RH29 10K_0402_5%~D

+1.5VS

SATA_PRX_DTX_N0 [43] SATA_PRX_DTX_P0 [43]

SATA_PTX_DRX_N0 [43] SATA_PTX_DRX_P0 [43]

SATA_PRX_DTX_N1 [42] SATA_PRX_DTX_P1 [42]

SATA_PTX_DRX_N1_C [42] SATA_PTX_DRX_P1_C [42]

+3VS

+1.5VS

RTC Battery

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

HDD

SS

D

Boot BIOS Strap

1 2

RH245 1K_0402_5%~D@

1 2

RH244 1K_0402_5%~D@

GPIO19 => BBS_BIT0 GPIO51 => BBS_BIT1

Boot BIOS Strap

*

BBS_BIT[0]BBS_BIT[1]

0 0

0

1

1 1

1

0

+3VLP

W=20mils

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (1/8) SATA,HDA

LA-9941P

+RTCBATT

3

1

2

BBS_BIT0

Boot BIOS Location

LPC

Reserved (NAND)

PCI

SPI

RTCR1 1K_0402_5%~D

1 2

W=20mils

2

RTCD1 BAT54CW_SOT323-3

CH12 1U_0603_10V6K~D

1

+RTCVCC

16 62Tuesday, September 03, 2013

BBS_BIT1 [18]

0.1

1 2

RH1 10M_0402_5%

YH1

1 2

32.768KHZ_12.5PF_FC-135

1

D D

+RTCVCC

CH3

18P_0402_50V8J~D

2

1 2

RH2 1M_0402_5%~D

PCH Strap PIN

INTVRMEN Integrated 1.05V VRM Enable/Disable

+RTCVCC

1 2

RH13 330K_0402_5%

1 2

RH16 330K_0402_5%@

H：Integrated VRM enable

*

：

Integrated VRM disable

C C

B B

A A

L

SPKR No Reboot

+3VS

1 2

RH17 1K_0402_5%~D@

LOW=Default

*

HIGH=No Reboot

If the signal i s sampled high , this indicate that the system is strapped to th e "No Reboot" m ode

HDA_SYNC On-Die PLL Voltage Regulator Voltage Select

+3V_PCH

1 2

RH32 1K_0402_5%~D@

This signal has a weak intern al pull-down On Die PLL VR i s supplied by

1.5V when smapl ed high

1.8V when sampl ed low

*

Needs to be pul led High for H uron River plat from

HDA_SDO Flash Descriptor Security Override/Intel ME Debug Mode

+3V_PCH

1 2

RH23 1K_0402_5%~D@

Low = Disabled

*

High = Enabled

ME debug mode , this signal has a weak internal PD

L=>security measures defined in the Flash Descriptor will be in effect (default)

H=>Flash Descriptor Security will be overridden

JTAG

+3V_PCH +3V_PCH+3V_PCH

12

RH18 210_0402_1%~D

12

RH24 100_0402_1%~D

12

RH19 210_0402_1%~D

12

RH25 100_0402_1%~D

5

4

3

2

1

U7C

Y43

CLKOUT_PCIE_N _0

Y45

CLKOUT_PCIE_P_ 0

PCH_GPIO20

PCH_GPIO44

NFC_RST#

NFC_DET#

4

AL11

AJ11

AJ10

AD43 AD45

AH43

AH45

A20

C20

A18

C18

B21

D21

G20

AJ7

AL7

AH1

AH3

AJ4

AJ2

AB1

AA44 AA42

AF1

AB43

AB45

AF3

T3

AF43 AF45

V3

AE44 AE42

AA2

AB40 AB39

AE4

AJ44

AJ42

Y3

D44

E44

B42

F41

A40

U7D

LAD_0

LAD_1

LAD_2

LAD_3

LFRAME#

LDRQ0#

LDRQ1#/GPIO23

SERIRQ

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_CS2#

SPI_MOSI

SPI_MISO

SPI_IO2

SPI_IO3

LYN

@

PCIECLKRQ0#/GPIO73

CLKOUT_PCIE_N _1 CLKOUT_PCIE_P_ 1

PCIECLKRQ1#/GPIO18

CLKOUT_PCIE_N _2

CLKOUT_PCIE_P_ 2

PCIECLKRQ2#/GPIO20/SMI#

CLKOUT_PCIE_N _3 CLKOUT_PCIE_P_ 3 PCIECLKRQ3#/GPIO25

CLKOUT_PCIE_N _4 CLKOUT_PCIE_P_ 4 PCIECLKRQ4#/GPIO26

CLKOUT_PCIE_N 5 CLKOUT_PCIE_P_ 5 PCIECLKRQ5#/GPIO44

CLKOUT_PCIE_N _6 CLKOUT_PCIE_P_ 6 PCIECLKRQ6#/GPIO45

CLKOUT_PCIE_N _7

CLKOUT_PCIE_P_ 7

PCIECLKRQ7#/GPIO46

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

CLKOUT_33M HZ0

CLKOUT_33M HZ1

CLKOUT_33M HZ2

CLKOUT_33M HZ3

CLKOUT_33M HZ4

CLOCK SIGNAL

LYNXPOINT_BGA695

@

XPOINT_BGA695

PCIECLKREQ0#

1 2

LANCLK_REQ#

MINI3CLK_REQ#

CDCLK_REQ#

CLK_PCI1

CLK_PCI2CLK_PCI_DEBUG

D D

CLK_PCIE_MINI3#[40]

MiniWLAN (Mini Card 1)--->

Card Reader --->

+3V_PCH

+3VS

+3V_PCH

C C

PT

RPH24

4 5 3 6 2 7 1 8

10K_0804_8P4R_5%

RPH25

4 5 3 6 2 7 1 8

10K_0804_8P4R_5%

NFC_RST# PCIECLKREQ0# PCH_GPIO44 NFC_DET#

CDCLK_REQ# MINI3CLK_REQ# PCH_GPIO20 LANCLK_REQ#

CLK_PCIE_MINI3[40]

MINI3CLK_REQ#[40]

CLK_PCIE_CD#[40] CLK_PCIE_CD[40]

CDCLK_REQ#[40]

NFC_RST#[49]

NFC_DET#[49]

CLK_CPU_ITP#[6]

CLK_CPU_ITP[6]

CLK_PCI_LPBACK CLK_PCI0

CLK_PCI_LPC[38]

CLK_PCI_DEBUG[42]

CLK_PCI_LPC

RH144 22_0402_5%

RH145 22_0402_5%

RH146 22_0402_5%

Reserve for EMI

1 2

CH14 10P_0402_50V8J~D@

1 2

CH26 10P_0402_50V8J~D@

B B

RPH5

1 8

PCH_SPI_SI PCH_SPI_SO PCH_SPI_WP# PCH_SPI_WP#_R

2 7 3 6 4 5

15_0804_8P4R_5%

PCH_SPI_CLK_RPCH_SPI_CLK PCH_SPI_SI_R PCH_SPI_SO_R

CLK_PCI_LPC

CLK_PCI_DEBUG

PCH_SPI_HOLD#

LPC_AD0[38,40,42]

LPC_AD1[38,40,42]

LPC_AD2[38,40,42]

LPC_AD3[38,40,42]

LPC_FRAME#[38,40,42]

1 2

RH75 10K_0402_5%~D

+3VS

SERIRQ[38,40]

T7PAD~D @

1 2

RH41 15_0402_1%

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

LPC_FRAME#

SERIRQ

PCH_SPI_CLK_R

PCH_SPI_CS#

PCH_SPI_CS1#

PCH_SPI_SI_R

PCH_SPI_SO_R

PCH_SPI_WP#_R

PCH_SPI_HOLD#_R

SPI ROM FOR ME ( 8MByte )

+3V_PCH

1 2

RH33 3.3K_0402_5%@

1 2

RH38 1K_0402_5%~D

1 2

RH40 1K_0402_5%~D

A A

PCH_SPI_CS# PCH_SPI_SO PCH_SPI_WP#

1 2 3 4

UH2

CS# DO(IO1) WP#(IO2) GND

PCH_SPI_CS#

PCH_SPI_WP#

PCH_SPI_HOLD#

HOLD#(IO3)

DI(IO0)

W25Q64FVQ_SO8

5

8

VCC

7 6

CLK

5

PCH_SPI_HOLD# PCH_SPI_CLK PCH_SPI_SI

+3V_PCH

1

CH11

0.1U_0402_16V7K~D

2

LPT_PCH_M_EDS

REV = 5

LPT_PCH_M_EDS

REV = 5

SMBus

SPILPC

C-Link

Thermal

CLKOUT_PEG_ A

CLKOUT_PEG_ A_P

PEGA_CLKRQ#/GPIO47

CLKOUT_PEG_ B

CLKOUT_PEG_ B_P

PEGB_CLKRQ#/GPIO56

CLKOUT_DMI_P

CLKOUT_DP_ P

CLKOUT_DPN S

CLKOUT_DPN S_P

CLKIN_GND_P

CLKIN_DOT96N CLKIN_DOT96P

CLKIN_SATA_P

CLKIN_33MHZLOOP BACK

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

2 OF 11

DIFFCLK_BIASREF

SML1ALERT#/PC HHOT#/GPIO74

3 OF 11

CLKOUT_DMI

CLKOUT_DP

CLKIN_DMI

CLKIN_DMI_P

CLKIN_GND

CLKIN_SATA

REFCLK14IN

XTAL25_IN

XTAL25_OUT

ICLK_IREF

TP19 TP18

SMBALERT#/GPIO11

SMBCLK

SMBDATA

SML0ALERT#/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK

CL_DATA

CL_RST#

TD_IREF

3

AB35

CLK_PEG_VGA#

AB36

CLK_PEG_VGA

AF6

PEG_A_CLKRQ#

Y39

Y38

U4

PEG_B_CLKREQ#

AF39

CLK_CPU_DMI#

AF40

CLK_CPU_DMI

AJ40

CLK_CPU_SSC_DPLL#

AJ39

CLK_CPU_SSC_DPLL

AF35

DPLL_REF_CLK#

AF36

DPLL_REF_CLK

AY24

CLKIN_DMI#

AW24

CLKIN_DMI

AR24

CLK_BUF_BCLK#

AT24

CLK_BUF_BCLK

H33

CLKIN_DOT96#

G33

CLKIN_DOT96

BE6

CLKIN_SATA#

BC6

CLKIN_SATA

F45

CLK_PCH_14M

D17

CLK_PCI_LPBACK

AL44

XTAL25_IN

AM43

XTAL25_OUT

C40

CLK_PCI_TPM_R

F38

KB_DET#

F36

F39

AM45

AD39 AD38

AN44

PCH_CLK_BIASREF

TP1

TP2

TP4

TP3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

N7

CCD_INT

R10

SMBCLK

U11

SMBDATA

N8

DRAMRST_CNTRL_PCH

U8

SML0CLK

R7

SML0DATA

H6

NFC_IRQ

K6

SML1CLK

N11

SML1DATA

AF11

AF10

AF7

BA45

BC45

BE43

BE44

AY43

PCH_TD_IREF

No support iAMT

RH97 22_0402_1% RH98 100K_0402_5%~D

CLK_PEG_VGA# [24]

CLK_PEG_VGA [24]

PEG_A_CLKRQ# [24]

1 2

RH64 10K_0402_5%~D

PEG_B_CLKREQ# [19]

CLK_CPU_DMI# [8]

CLK_CPU_DMI [8]

CLK_CPU_SSC_DPLL# [8] CLK_CPU_SSC_DPLL [8]

DPLL_REF_CLK# [8] DPLL_REF_CLK [8]

1 2 1 2

1 2

RH28 7.5K_0402_1%~D

SML0CLK [49]

SML0DATA [49]

NFC_IRQ [49]

12

RH322

8.2K_0402_1%

2011/08/25 2012/07/25

+3V_PCH

CLK_PCI_TPM

+3VS

KB_DET# [39]

+1.5VS

PCH to NFC

Compal Secret Data

Deciphered Date

12

2

CLK_PCI_TPM [40]

CH13

@

10P_0402_50V8J~D

Reserve for EMI

6 1

SMBCLK

DMN66D0LDW-7_SOT363-6~D

SMBDATA

SML1CLK

DMN66D0LDW-7_SOT363-6~D

SML1DATA

QH2A

DMN66D0LDW-7_SOT363-6~D

XTAL25_IN

XTAL25_OUT

PT

CLK_BUF_BCLK# CLK_BUF_BCLK CLKIN_DMI# CLKIN_DMI

CLKIN_DOT96# CLKIN_DOT96 CLKIN_SATA# CLKIN_SATA

CLK_PCH_14M

CLOCK TERMINATION for FCIM and need close to PCH

+3VS

2

5

3

4

QH2B

+3VS

2

6 1

DMN66D0LDW-7_SOT363-6~D

5

QH3A

3

QH3B

Title

Size Document Number Rev

Date: Sheet of

1 2

RH89 1M_0402_5%~D

4

1

25MHZ_10PF_X3G025000DA1H~D

1

CH27 12P_0402_50V8J

2

RH66 10K_0402_5%~D RH67 10K_0402_5%~D RH68 10K_0402_5%~D RH69 10K_0402_5%~D

RH62 10K_0402_5%~D

PT

SMBCLK

SMBDATA

NFC_IRQ

CCD_INT

DRAMRST_CNTRL_PCH

SML1CLK SML1DATA PCH_SMBCLK PCH_SMBDATA

PT

SML0CLK

SML0DATA

4

Compal Electronics, Inc.

PCH (2/8) SMBUS, CLK, SPI, LPC

LA-9941P

YH2

3

NC

OSC

2

OSC

NC

1

CH28 12P_0402_50V8J

2

PT

RPH27

4 5 3 6 2 7 1 8

10K_0804_8P4R_5%

1 2 1 2 1 2 1 2

1 2

RH448 2.2K_0402_5%~D

1 2

RH456 2.2K_0402_5%~D

1 2

RH65 10K_0402_5%~D@

1 2

RH63 10K_0402_5%~D

1 2

RPH14

1 8 2 7 3 6 4 5

2.2K_8P4R_5%

1 2

1K_0402_5%~D

N14@

RH53

RH724 499_0402_1%

RH725 499_0402_1%

PCH to DDR, XDP, TP, FFS, AMP

PCH_SMBCLK [14,15,39,43,6]

PCH_SMBDATA [14,15,39,43,6]

PCH to EC

PCH_SMLCLK [25,35,38,40]

PCH_SMLDATA [25,35,38,40]

17 62Tuesday, September 17, 2013

1

17 62Tuesday, September 17, 2013

+3V_PCH

+3VS

0.1

5

U7B

DMI_RCOMP

XDP_DBRESET#

SYS_PWROK

PCH_GPIO72

RI#

SLP_WLAN#

+RTCVCC

AW22

DMI_RXN_0

AR20

DMI_RXN_1

AP17

DMI_RXN_2

AV20

DMI_RXN_3

AY22

DMI_RXP_0

AP20

DMI_RXP_1

AR17

DMI_RXP_2

AW20

DMI_RXP_3

BD21

DMI_TXN_0

BE20

DMI_TXN_1

BD17

DMI_TXN_2

BE18

DMI_TXN_3

BB21

DMI_TXP_0

BC20

DMI_TXP_1

BB17

DMI_TXP_2

BC18

DMI_TXP_3

BE16

DMI_IREF

AW17

TP12

AV17

TP7

AY17

DMI_RCOMP

R6

SUSACK#

AM1

SYS_RESE T#

AD7

SYS_PW ROK

F10

PWROK

AB7

APWROK

H3

DRAMPWR OK

J2

RSMRST#

J4

SUSWAR N#/SUSPWR NACK/GPIO30

K1

PWRBTN#

E6

ACPRESEN T/GPIO31

K7

BATLOW# /GPIO72

N4

RI#

AB10

TP21

D2

SLP_W LAN#/GPIO2 9

LYN

XPOINT_BGA695

@

PCH_PWROK_EC[38]

IMVP_VR_PG[38,58,6]

T175PAD~D@

T178PAD~D@

T81PAD~D@

T171PAD~D@

T170PAD~D@

PCH_GPIO72 RI# WAKE# PCH_SUSWARN#

PCH_RSMRST#

SYS_PWROK

PCH_PWROK_EC

AC_PRESENT

12

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1

DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1

DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1

DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1

DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

T176PAD~D@

PM_DRAM_PWRGD

T177PAD~D@

DMI_CTX_PRX_N0[7] DMI_CTX_PRX_N1[7]

DMI_CTX_PRX_N2[7] DMI_CTX_PRX_N3[7]

DMI_CTX_PRX_P0[7] DMI_CTX_PRX_P1[7]

DMI_CTX_PRX_P2[7] DMI_CTX_PRX_P3[7]

DMI_CRX_PTX_N0[7]

+1.5VS

SUSACK#[38]

+3V_PCH+3V_PCH

1 2

DSWODVREN

*

+1.5VS

PCH_PWROK_EC

H：Enable

：

Disable

L

DMI_CRX_PTX_N1[7]

DMI_CRX_PTX_N2[7] DMI_CRX_PTX_N3[7]

DMI_CRX_PTX_P0[7] DMI_CRX_PTX_P1[7]

DMI_CRX_PTX_P2[7] DMI_CRX_PTX_P3[7]

1 2

RH99 7.5K_0402_1%~D

PCH_RSMRST#

PBTN_OUT#

AC_PRESENT

RPH4

4 5 3 6 2 7 1 8

10K_0804_8P4R_5%

RH119 330K_0402_5%

RH122 330K_0402_5%@

D D

For deep S3, connector to EC

XDP_DBRESET#[6,8]

PM_DRAM_PWRGD[8]

PCH_RSMRST#[38]

For deep S3

PCH_SUSWARN#[38]

PBTN_OUT#[38,6]

AC_PRESENT[38]

C C

PT

+3VALW +3VALW

RH127 10K_0402_5%~D

RH130 10K_0402_5%~D

RH193 10K_0402_5%~D@

+3VALW

For deep S3

RH121 10K_0402_5%~D

B B

PCH Strap PIN

DSWVRMEN Deep S4/S5 Well On-Die Voltage Regulator Enable

If strap is sampled high, the Integrated Deep S4/S5 Well (DSW) On-Die VR mode is enabl ed

LPT_PCH_M_EDS

DMI

PCH_PWROK_EC

IMVP_VR_PG

System Power

Management

REV = 5

4

FDI

+3VS

5

1

IN1

2

IN2

3

PLT_RST#[38,40,42,6,8]

FDI_RXN_0

FDI_RXN_1

FDI_RXP_0

FDI_RXP_1

TP16

TP5

TP15

TP10

FDI_CSYNC

FDI_INT

FDI_IREF

TP17

TP13

FDI_RCOMP

DSWVRME N

DPWROK

WAKE#

CLKRUN#

SUS_STAT#/G PIO61

SUSCLK/G PIO62

SLP_S5# /GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS #

PMSYNCH

SLP_LAN #

4 OF 11

UH3

VCC

4

OUT

GND

MC74VHC1G08DFT2G_SC70-5

12

RH155 100K_0402_5%~D

AJ35

AL35

AJ36

AL36

AV43

AY45

AV45

AW44

AL39

FDI_CSYNC

AL40

AT45

AU42

AU44

AR44

C8

DSWODVREN

L13

K3

WAKE#

AN7

PM_CLKRUN#

PT

U7

Y6

Y7

PM_SLP_S5#

C6

PM_SLP_S4#

H1

PM_SLP_S3#

F3

PM_SLP_A#

F1

AY3

H_PM_SYNC

G5

SLP_LAN#

+3VS

RH136 8.2K_0402_5%~D

RH120 10K_0402_5%~D@

SYS_PWROK

+3VS

5

UH5

P

IN1

4

O

IN2

G

SN74AHC1G08DCKR_SC70-5

3

T46 PAD~D @ T39 PAD~D @

T41 PAD~D @

T42 PAD~D @

T44 PAD~D @

1 2

1

2

FDI_CSYNC [7]

FDI_INT [7]

T37 PAD~D @ T40 PAD~D @

T38 PAD~D @

DGPU_PWR_EN[24,33,59]

PCH_PLTRST#

PM_CLKRUN# [40]

SUSCLK_R [ 38,40]

PM_SLP_SUS# [34,38]

PM_CLKRUN#

@

0.01U_0402_16V7K~D

3

+3VS

1 2

RH167 8.2K_0402_5%~D

1 2

RH164 8.2K_0402_5%~D@

+3VS

RPH2

18

PCH_GPIO52

27

ODD_DA#

36

DGPU_HOLD_RST#

45

RPH1

18 27 36 45

WL_OFF#

PCI_PIRQA# PCI_PIRQB# PCI_PIRQD# PCI_PIRQC#

8.2K_0804_8P4R_5%

+3VS

8.2K_0804_8P4R_5%

For deep S3

POK [52,54]

PM_SLP_S5# [38]

PM_SLP_S4# [38,55]

PM_SLP_S3# [34,38,40,43,55,56]

For deep S3

H_PM_SYNC [8]

+3VS

@

10K_0402_5%~D

1 2

13

D

1

CH99

@

S

2

2N7002_SOT23-3

1 2

RH416 0_0402_5%@

PCH_GPIO5

DGPU_PWR_EN#

PT

1 2

*

RH243 1K_0402_5%~D@

eDP_PWM

ENBKL

eDP_LVDDEN

PCI_PIRQA#

PCI_PIRQB#

PCI_PIRQC#

PCI_PIRQD#

DGPU_HOLD_RST#

PCH_GPIO52

DGPU_PWR_EN#

BBS_BIT1

EN_CAM

WL_OFF#

H：Enable L：Default

1 2

eDP_PWM[35]

ENBKL[35,38]

eDP_LVDDEN[35]

BBS_BIT1[16]

T8PAD~D@

WL_OFF#[40]

RH138 100K_0402_5%~D

RH132 100K_0402_5%~D

GNT3# A16 Top-Block Swap Override (Internal PU 20K)

PT

RH247

2

DGPU_PWR_EN#

G

QH6

PLTRST_VGA#[24]

ST

T45

U44

V45

M43

M45

N42

N44

U40

U39

N36

K36

G36

H20

L20

K17

M20

A12

B13

C12

C10

A10

AL6

ENBKL

eDP_LVDDEN

2

U7E

VGA_BLU E

VGA_GRE EN

VGA_RED

VGA_DDC_ CLK

VGA_DDC_ DATA

VGA_HSYNC

VGA_VSYN C

DAC_IREF

VGA_IRTN

EDP_BKL TCTL

EDP_BKL TEN

EDP_VDDE N

PIRQA#

PIRQB#

PIRQC#

PIRQD#

GPIO50

GPIO52

GPIO54

GPIO51

GPIO53

GPIO55

LYN

XPOINT_BGA695

@

WL_OFF#

LPT_PCH_M_EV

4

12

RH154 100K_0402_5%~D

REV = 5

LVDSCRT

PCI

PCH Strap PIN

+3VS_DELAY

5

UH4

1

P

IN1

O

2

IN2

G

SN74AHC1G08DCKR_SC70-5

3

DISPLAY

DDPB_CTRLCL K

DDPB_CTRLDA TA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPB_AUX N

DDPC_AUXN

DDPD_AUXN

DDPB_AUX P

DDPC_AUXP

DDPD_AUXP

DDPB_HPD

DDPC_HPD

DDPD_HPD

PIRQE#/G PIO2

PIRQF#/GP IO3

PIRQG#/G PIO4

PIRQH#/GP IO5

PME#

PLTRST#

5 OF 11

HDMI_DDB_CTRLCLK HDMI_DDB_CTRLDATA mDP_DDC_CTRLCLK mDP_DDC_CTRLDATA

R40

R39

R35

R36

N40

N38

H45

K43

J42

H43

K45

J44

K40

K38

H39

G17

F17

L15

M15

AD10

Y11

HDMI_DDB_CTRLCLK

HDMI_DDB_CTRLDATA

mDP_DDC_CTRLCLK

mDP_DDC_CTRLDATA

P

T

mDP_AUXN_PCH

mDP_AUXP_PCH

HDMI_PCH_HPD

DP_PCH_HPD

FFS_INT1

ODD_DA#

CAB_DET_SINK

PCH_GPIO5

T6 PAD~D @

PCH_PLTRST#

RPH16

1 8 2 7 3 6 4 5

2.2K_8P4R_5%

1

PCH_PLTRST#

DGPU_HOLD_RST#

HDMI_DDB_CTRLCLK [36]

HDMI_DDB_CTRLDATA [36]

mDP_DDC_CTRLCLK [37]

mDP_DDC_CTRLDATA [37]

mDP_AUXN_PCH [37]

mDP_AUXP_PCH [37]

HDMI_PCH_HPD [36]

DP_PCH_HPD [16,37]

FFS_INT1 [ 43]

CAB_DET_SINK [37]

+3VS

PT

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

LA-9941P

1

18 62Tuesday, September 03, 2013

0.1

5

4

3

2

1

LPT_PCH_M_EDS

REV = 5

PCIe

USB

9 OF 11

USB2N0

USB2P0

USB2N1

USB2P1

USB2N2

USB2P2

USB2N3

USB2P3

USB2N4

USB2P4

USB2N5

USB2P5

USB2N6

USB2P6

USB2N7

USB2P7

USB2N8

USB2P8

USB2N9

USB2P9 USB2N10 USB2P10 USB2N11 USB2P11 USB2N12 USB2P12 USB2N13 USB2P13

USB3RN1 USB3RP1 USB3TN1

USB3TP1

USB3RN2 USB3RP2 USB3TN2

USB3TP2

USB3RN5 USB3RP5 USB3TN5

USB3TP5

USB3RN6 USB3RP6 USB3TN6

USB3TP6

USBRBIAS#

USBRBIAS

TP24 TP23

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

B37 D37 A38 C38 A36 C36 A34 C34 B33 D33 F31 G31 K31 L31 G29 H29 A32 C32 A30 C30 B29 D29 A28 C28 G26 F26 F24 G24

AR26 AP26 BE24 BD23 AW26 AV26 BD25 BC24 AW29 AV29 BE26 BC26 AR29 AP29 BD27 BE28

K24 K26

M33 L33

P3 V1 U2 P1 M3 T1 N2 M1

USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4

USB20_N9 USB20_P9

USB20_N12 USB20_P12

USB3RN1 USB3RP1 USB3TN1 USB3TP1 USB3RN2 USB3RP2 USB3TN2 USB3TP2 USB3RN3 USB3RP3 USB3TN3 USB3TP3 USB3RN4 USB3RP4 USB3TN4 USB3TP4

USBRBIAS

USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7#

USB20_N0 [44] USB20_P0 [44] USB20_N1 [44] USB20_P1 [44] USB20_N2 [40] USB20_P2 [40] USB20_N3 [40] USB20_P3 [40] USB20_N4 [40] USB20_P4 [40]

USB20_N9 [35] USB20_P9 [35]

USB20_N12 [40] USB20_P12 [40]

USB3RN1 [45] USB3RP1 [45] USB3TN1 [45] USB3TP1 [45] USB3RN2 [45] USB3RP2 [45] USB3TN2 [45] USB3TP2 [45] USB3RN3 [40] USB3RP3 [40] USB3TN3 [40] USB3TP3 [40] USB3RN4 [40] USB3RP4 [40] USB3TN4 [40] USB3TP4 [40]

1 2

RH143 22.6_0402_1%

USB_OC0# [44] USB_OC1# [40]

USB Conn 1 (Power share)

USB Conn 3 (Power share)

USB Conn 2 (Power share)

USB Conn 4 (Power share)

Mini Card(WLAN)

Touch Screen

PEG_B_CLKREQ#[17]

Camera

USB Conn 1 (Power share)

USB Conn 3 (Power share)

USB Conn 2 (Power share)

USBRBIAS CAD NOTE: Route single-end 50-ohms and max 500-mils length. Avoid routing next to clock pins or under stitching capacitors. Recommended minimum spacing to other signal traces is 15 mils.

+3V_PCH

PT

RPH29

USB_OC4# USB_OC7# USB_OC6# USB_OC0#

USB_OC3# USB_OC2# USB_OC5# PEG_B_CLKREQ#

4 5 3 6 2 7 1 8

10K_0804_8P4R_5%

RPH30

4 5 3 6 2 7 1 8

10K_0804_8P4R_5%

+3V_PCH

D D

PCIE_PRX_WLANTX_ N3[40]

MiniWLAN (Mini Card 1)--->

CARD_READER --->

C C

B B

PCIE_PRX_WLANTX_ P3[40]

PCIE_PTX_WLANRX_ N3[40] PCIE_PTX_WLANRX_ P3[40]

PCIE_PRX_CARDTX_N4[40] PCIE_PRX_CARDTX_P4[40]

PCIE_PTX_CARDRX_N4[40] PCIE_PTX_CARDRX_P4[40]

1 2

CH19 0.1U_0402_10V7K~D

1 2

CH20 0.1U_0402_10V7K~D

1 2

CH21 0.1U_0402_10V7K~D

1 2

CH22 0.1U_0402_10V7K~D

+1.5VS

1 2

RH113 7.5K_0402_1%~D

PCIE_PRX_WLANTX_ N3 PCIE_PRX_WLANTX_ P3

PCIE_PTX_WLANRX_ N3_C PCIE_PTX_WLANRX_ P3_C

PCIE_PRX_CARDTX_N4 PCIE_PRX_CARDTX_P4

PCIE_PTX_CARDRX_N4_C PCIE_PTX_CARDRX_P4_C

PCIE_RCOMP

AW31

AY31

BE32 BC32

AT31 AR31

BD33 BB33

AW33

AY33

BE34 BC34

AT33 AR33

BE36 BC36

AW36

AV36

BD37 BB37

AY38

AW38

BC38 BE38

AT40 AT39

BE40 BC40

AN38 AN39

BD42 BD41

BE30

BC30

BB29

BD29

U7I

PERN1/USB3RN3 PERP1/USB3RP3

PETN1/USB3TN3 PETP1/USB3TP3

PERN2/USB3RN4 PERP2/USB3RP4

PETN2/USB3TN4 PETP2/USB3TP4

PERN_3 PERP_3

PETN_3 PETP_3

PERN_4 PERP_4

PETN_4 PETP_4

PERN_5 PERP_5

PETN_5 PETP_5

PERN_6 PERP_6

PETN_6 PETP_6

PERN_7 PERP_7

PETN_7 PETP_7

PERN_8 PERP_8

PETN_8 PETP_8

PCIE_IREF

TP11

TP6

PCIE_RCOMP

LYN

XPOINT_BGA695

@

USB_OC1#

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OFC OMPALE LECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OFC OMPALE LECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OFC OMPALE LECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

1 2

RH84 10K_0402_5%~D

Compal Electronics, Inc.

PCH (4/8) PCI, USB

LA-9941P

+3V_PCH

0.1

19 62Tuesday, September 03, 2013

1

19 62Tuesday, September 03, 2013

0.1