Compal LA-9911P VAWGA, G505, LA-9911P VAWGB Schematic

A

1 1

B

C

D

E

Compal Confidential

VAWGA/B Schematics Document

2 2

AMD "Kabini" Platform

AMD 25W APU With Jaguar Core and Integrated Yangtze FCH + ATI Sun

LA-9911P REV: 1.0

3 3

4 4

A

B

2013-04-01

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/04/22 2015/04/22

2012/04/22 2015/04/22

2012/04/22 2015/04/22

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

COVER PAGE

COVER PAGE

COVER PAGE

VAWGA/GB

VAWGA/GB

VAWGA/GB

1 48Monday, April 01, 2013

1 48Monday, April 01, 2013

1 48Monday, April 01, 2013

E

1.0

1.0

1.0

A

Compal Confidential

Model Name : VAWGA/B

B

C

D

E

1 1

VRAM 1G/2G
2

56M16 x 4 (2G)

128M16 x 4 (1G)

P.16~19

DDR3

AMD Sun Pro M2

VRAM 1GB/2 GB
DDR3 x4

LVDS Conn.

HDMI Conn.

CRT Conn.

2 2

P21

P20

P22

page 10~15

MINI Card
(WLAN/BT)

P26

GPP1GPP2

LAN
Atheros
AR8162/8172

Transformer

RJ45

BIOS (4M)

Int.KBD

P.30

ENE
KBC9012

3 3

PS2

Touch Pad

P.5

P.28

P.30

Thermal Sensor

P.29

AMD Kabini

Gen2PCIe x 4

P24

P25

GFX

DP0

DP1

DAC

GPP

SPI

LPC

AMD FT3 APU

Jaguar Core

Integrated Yangtze FCH

BGA 769-balls

USB

USB

HDA

SATA

P.4~P.7

Memory BUS(DDR3)

Single Channel

1.5V DDRIII 1600MHz

P.21

CMOS
Camera

Port 3

USB2.0

MB

Port 8 Port 9

P.27

3.0 Conn. LP1

Port 0

USB3.0

HD Audio

Port 0

Gen3

HDD
Conn.

204pin DDRIII-SO-DIMM X2

P.26

WLAN
BT Combo

Port 5

P.27

MB

3.0 Conn. LP2

Port 1

Port 1

ODD
Conn.

P.23 P.23

BANK 0, 1, 2

Card
Reader

Port 4

P.30

P.8~P.9

Touch
S

creen

Audio
Conexant
CX20757

P.26

Port 1

P.31

S/B

2.0 Conn.

Port 0

P.27

Int. MIC

page 31

Int. Speaker Conn.

page 31

Audio Combo Jacks

HP & MIC

page 31

Sub-borad

15"

14"

IO/B

LS9633P

page 30

4 4

A

Power/B

USB/B

LS9632P

S9631P

L

page 30

page 27

ODD/B

LS9634P

LED/B

LS9635P

page 23

page 30

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/04/22 2015/04/22

2012/04/22 2015/04/22

2012/04/22 2015/04/22

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

BLOCK DIAGRAMS

BLOCK DIAGRAMS

BLOCK DIAGRAMS

VAWGA/GB

VAWGA/GB

VAWGA/GB

E

1.0

1.0

2 48Thursday, March 28, 2013

2 48Thursday, March 28, 2013

2 48Thursday, March 28, 2013

1.0

A

B

C

D

E

Voltage Rails

Power Plane Description

VIN

B+

+APU_CORE

+APU_CORE_NB ON OFF OFFVoltage for On-die VGA of APU

1 1

+VGA_CORE OFFOFFON0.95-1.2V switched power rail

+VDDCI OFF0.95-1.2V switched power rail ON OFF

+3VALW

+3VS

+1.8VALW

+1.8VS

+0.95VALW

+0.95VS

+1.5V

+3VGS

+1.8VGS

+1.5VGS

+0.95VGS

+5VALW

+5VS

2 2

+VSB ON ON

+RTC_APU

+0.75VS ON OFFOFF

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for APU

3.3V always on power rail

3.3V switched power rail

1.8V always on power rail

1.8V switched power rail

0.95V always on power rail

0.95V switched power rail

1.5V power rail for APU and DDR

1.5V switched power rail

3.3V switched power rail for VGA

1.8V switched power rail for VGA

1.5V switched power rail for VGA

0.95V switched power rail for VGA

5V always on power rail

5V switched power rail

VSB always on power rail

RTC power

0.75V switched power rail for DDR terminator

S0 S3 S5

ON ON ON

ON OFF

ONON OFF

ON OFF OFF

ON ON*ON

ON OFF OFF

ON OFF OFF

ON OFF OFF

ON OFFON

OFFON OFF+1.5VS

OFF

ON

OFF OFF

ON

ON OFF OFF

OFF

ON

ON

ON

OFF

ON

ON

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1

APU_SCLK0
APU_SDATA0

SMB_EC_CK2
SMB_EC_DA2

3 3

KB9012

+3VALW

APU

+3VS

KB9012

+3VS

VGA BATT KB9012 SODIMM

X V

+3VALW

X

X

V V

+3VS +3VS

X X

X X

WLAN
WWAN

X X

VX

+3VS +3VS

X

V

EC SM Bus1 address EC SM Bus2 address

Device Address

Smart Battery

0001 011X b

HEX

Device Address HEX

16H

Thermal Sen sor

SB-TSI (APU)

VGA Internal Thermal

1001 101X b

1001 100X b

1000 001X b

APU
SM Bus address

4 4

Device Address

DDR DIMM1

DDR DIMM2

1010 000Xb

1010 001Xb

HEX

A0H

A2H

A

B

BOARD ID Table

PCB Revision
MP
PVT
DVT
EVT

ONONON

OFF

Board ID

0
1
2
3
4
5
6
7

Board ID / SKU ID Table for AD channel

OFF

OFF

ON

OFFON

ONON

Thermal
Sensor

XX

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7 NC

FCH

100K +/- 5%R1562

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

APU RTD2132

X

X

X

+3VS

R1564 V min

0

X X

X X

V

X

USB Port Table

USB 2.0 USB 3.0

9AH

98H

82H

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF) LOW

AD_BID

0 V

V typ

AD_BID

0 V 0 V

V

AD_BID

max

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

2.200 V

3.300 V

2.341 V

3.300 V

APU PCIE PORT LIST

DevicePort

0
1
2
3

Port

0

XHCI

1

2012/04/22 2015/04/22

2012/04/22 2015/04/22

2012/04/22 2015/04/22

C

LAN
WLAN

3 External
USB Port

0

RIGHT USB

1

Touch Screen

2
3

Camera

4

CardReader

5

WLAN/BT Combo

6

LEFT USB (for colay)

7

LEFT USB (for colay)

8

LEFT USB3.0

9

LEFT USB3.0

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

SIGNAL

SLP_S3# SLP_S5# +VALW +V +VS Clock

HIGH HIGH

HIGH

LOW

USB OC MAPPING

0
1
2
3

BOM Structure Table

BOM Structure BTO Item

A6@
A4@
E2@
E1@
E1PC@
X4@
X5@
X2@
EMICU@
EMICP@
EMIUSB2RU@
EMIUSB2RP@
USB2R@
SUN@
MARS@
14@
15@
PX@
CMOS@
HDMI@
EMIGASP@
8162@
8172@
SWR@
LDO@
THERMAL@
ME@
UMA@
@
ZODD@
TS@
EMIP@
EMIU@
ESDP@
ESDU@

D

ON

ON

ON ON

ON

ON

ON

OFF

OFF

OFF

LOW

OFF

OFF

OFF

HIGHHIGH

HIGH

HIGH

LOW

ON

ON

ON

OFF

ON

OFF

USB PortOC#

USB20 port0

USB20 port1,2,8,9

A6 R3 BGA APU

A4 R3 BGA APU

E2 R3 BGA APU

E1 R3 BGA APU

E1 PC BGA APU

X4 ES2 BGA APU

X5 ES2 BGA APU

X2 ES2 BGA APU

CardReader EMI Un pop

CardReadear EMI pop

Right USB2.0 port EMI un pop

Right USB2.0 port EMI pop

Right USB2.0 port component

SUN PRO GPU (R3 compal part)

MARS XT GPU (R1 compal part)

for 14" componect

for 15" componect

Common VGA circuit

CMOS Camera part

HDMI part

Gastube

Ateros AR8162 LAN Chip

Ateros AR8172 LAN Chip

LAN Switching mode

LAN LDO mode

Lenovo Thermal Sensor

ME part

UMA part

Unpop

Zero Power ODD part

Touch Screen

EMI pop component

EMI Un pop component

ESD pop component

ESD Un pop component

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

USB30 port0,1

NOTES LIST

NOTES LIST

NOTES LIST

VAWGA/GB

VAWGA/GB

VAWGA/GB

E

3 48Monday, April 01, 2013

3 48Monday, April 01, 2013

3 48Monday, April 01, 2013

1.0

1.0

1.0

A

<8,9>

DDRAB_SMA[15..0]

1 1

<8,9>

DDRAB_SBS0#

<8,9>

DDRAB_SBS1#

<8,9>

DDRAB_SBS2#

<8,9>

DDRAB_SDM[7..0]

<8,9>

DDRAB_SDQS0

<8,9>

DDRAB_SDQS0#

<8,9>

DDRAB_SDQS1

<8,9>

DDRAB_SDQS1#

<8,9>

DDRAB_SDQS2

<8,9>

DDRAB_SDQS2#

<8,9>

DDRAB_SDQS3

<8,9>

DDRAB_SDQS3#

<8,9>

DDRAB_SDQS4

<8,9>

DDRAB_SDQS4#

<8,9>

DDRAB_SDQS5

<8,9>

DDRAB_SDQS5#

<8,9>

DDRAB_SDQS6

<8,9>

DDRAB_SDQS6#

2 2

<8,9>

DDRAB_SDQS7

<8,9>

DDRAB_SDQS7#

<8>

DDRA_CLK0

<8>

DDRA_CLK0#

<8>

DDRA_CLK1

<8>

DDRA_CLK1#

<9>

DDRB_CLK0

<9>

DDRB_CLK0#

<9>

DDRB_CLK1

<9>

DDRB_CLK1#

<8,9>

MEM_MAB_RST#

<8,9>

MEM_MAB_EVENT#

<8>

DDRA_CKE0

<8>

DDRA_CKE1

<9>

DDRB_CKE0

<9>

DDRB_CKE1

<8>

DDRA_ODT0

<8>

DDRA_ODT1

<9>

DDRB_ODT0

<9>

DDRB_ODT1

<8>

DDRA_SCS0#

<8>

DDRA_SCS1#

<9>

DDRB_SCS0#

<9>

<8,9>
<8,9>
<8,9>

DDRB_SCS1#

DDRAB_SRAS#
DDRAB_SCAS#
DDRAB_SWE#

+MEM_VREF
+VREF_DQ

ZZZ

ZZZ

LA9911P

LA9911P

DAZ0Y600101

DAZ0Y600101

14@

14@

3 3

MEM_MAB_EVENT#

R576 0_0402_5%@R576 0_0402_5%@

ZZZ

ZZZ

LA9911P

LA9911P

DAZ0Y700101

DAZ0Y700101

DDRAB_SMA0
DDRAB_SMA1
DDRAB_SMA2
DDRAB_SMA3
DDRAB_SMA4
DDRAB_SMA5
DDRAB_SMA6
DDRAB_SMA7
DDRAB_SMA8
DDRAB_SMA9
DDRAB_SMA10
DDRAB_SMA11
DDRAB_SMA12
DDRAB_SMA13
DDRAB_SMA14
DDRAB_SMA15

DDRAB_SDM0
DDRAB_SDM1
DDRAB_SDM2
DDRAB_SDM3
DDRAB_SDM4
DDRAB_SDM5
DDRAB_SDM6
DDRAB_SDM7

1 2

AG38

W35
W38
W34

U38
U37
U34
R35
R38
N38

AG34

R34
N37

AN34

L38
L35

AJ38

AG35

N34

B32
B38
G40

N41
AG40
AN41
AY40
AY34

Y40

B33

A33

B40

A40

H41

H40

P41

P40
AH41
AH40
AP41
AP40
BA40
AY41
AY33
BA34
AA40

Y41

AC35
AC34
AA34
AA32
AE38
AE37
AA37
AA38

G38
AE34

L34

J38
J37
J34

AN38
AU38
AN37
AR37

AJ34

AR38

AL38

AN35

AJ37
AL34
AL35

AD40
AC38

X5 ES2 ZM201079J4460 2G BGA 769P

X5 ES2 ZM201079J4460 2G BGA 769P

15@

15@

M_ADD0

M_ADD1

M_ADD2

M_ADD3

M_ADD4

M_ADD5

M_ADD6

M_ADD7

M_ADD8

M_ADD9

M_ADD10

M_ADD11

M_ADD12

M_ADD13

M_ADD14

M_ADD15

M_BANK0

M_BANK1

M_BANK2

M_DM0

M_DM1

M_DM2

M_DM3

M_DM4

M_DM5

M_DM6

M_DM7

M_DM8

M_DQS_H0

M_DQS_L0

M_DQS_H1

M_DQS_L1

M_DQS_H2

M_DQS_L2

M_DQS_H3

M_DQS_L3

M_DQS_H4

M_DQS_L4

M_DQS_H5

M_DQS_L5

M_DQS_H6

M_DQS_L6

M_DQS_H7

M_DQS_L7

M_DQS_H8

M_DQS_L8

M_CLK_H0

M_CLK_L0

M_CLK_H1

M_CLK_L1

M_CLK_H2

M_CLK_L2

M_CLK_H3

M_CLK_L3

M_RESET_L

M_EVENT_L

M0_CKE0

M0_CKE1

M1_CKE0

M1_CKE1

M0_ODT0

M0_ODT1

M1_ODT0

M1_ODT1

M0_CS_L0

M0_CS_L1

M1_CS_L0

M1_CS_L1

M_RAS_L

M_CAS_L

M_WE_L

M_VREF

M_VREFDQ

UAPU

+VREF_DQ

MEMORY VREF

4 4

+1.5V

RP2

RP2

1 8

+MEM_VREF

2 7
3 6

MEM_MAB_EVENT#

4 5

1K_0804_8P4R_1%

1K_0804_8P4R_1%

A

1

@

@

C342

C342
1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

C337

C337
1U_0402_6.3V6K

1U_0402_6.3V6K

2

2

@

@

C164

C164

0.1U_0402_16V7K

0.1U_0402_16V7K

1

FT3 REV 0.51

FT3 REV 0.51

X5@UAPU

X5@

2

C163

C163

0.1U_0402_16V7K

0.1U_0402_16V7K

1

MEMORY

MEMORY

UAPUA

UAPUA

M_ZVDDIO_MEM_S

0.1U_0402_16V7K

0.1U_0402_16V7K

RP11

@RP11

@

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

10K_0804_8P4R_5%

B30

M_DATA0

A32

M_DATA1

B35

M_DATA2

A36

M_DATA3

B29

M_DATA4

A30

M_DATA5

A34

M_DATA6

B34

M_DATA7

B37

M_DATA8

A38

M_DATA9

D40

M_DATA10

D41

M_DATA11

B36

M_DATA12

A37

M_DATA13

B41

M_DATA14

C40

M_DATA15

F40

M_DATA16

F41

M_DATA17

K40

M_DATA18

K41

M_DATA19

E40

M_DATA20

E41

M_DATA21

J40

M_DATA22

J41

M_DATA23

M41

M_DATA24

N40

M_DATA25

T41

M_DATA26

U40

M_DATA27

L40

M_DATA28

M40

M_DATA29

R40

M_DATA30

T40

M_DATA31

AF40

M_DATA32

AF41

M_DATA33

AK40

M_DATA34

AK41

M_DATA35

AE40

M_DATA36

AE41

M_DATA37

AJ40

M_DATA38

AJ41

M_DATA39

AM41

M_DATA40

AN40

M_DATA41

AT41

M_DATA42

AU40

M_DATA43

AL40

M_DATA44

AM40

M_DATA45

AR40

M_DATA46

AT40

M_DATA47

AV41

M_DATA48

AW40

M_DATA49

BA38

M_DATA50

AY37

M_DATA51

AU41

M_DATA52

AV40

M_DATA53

AY39

M_DATA54

AY38

M_DATA55

BA36

M_DATA56

AY35

M_DATA57

BA32

M_DATA58

AY31

M_DATA59

BA37

M_DATA60

AY36

M_DATA61

BA33

M_DATA62

AY32

M_DATA63

V41

M_CHECK0

W40

M_CHECK1

AB40

M_CHECK2

AC40

M_CHECK3

U41

M_CHECK4

V40

M_CHECK5

AA41

M_CHECK6

AB41

M_CHECK7

AD41

X4@

X4@

FT3_BGA769

FT3_BGA769

ESDP@ C195

ESDP@

APU_TRST#

B

DDRAB_SDQ0
DDRAB_SDQ1
DDRAB_SDQ2
DDRAB_SDQ3
DDRAB_SDQ4
DDRAB_SDQ5
DDRAB_SDQ6
DDRAB_SDQ7

DDRAB_SDQ8
DDRAB_SDQ9
DDRAB_SDQ10
DDRAB_SDQ11
DDRAB_SDQ12
DDRAB_SDQ13
DDRAB_SDQ14
DDRAB_SDQ15

DDRAB_SDQ16
DDRAB_SDQ17
DDRAB_SDQ18
DDRAB_SDQ19
DDRAB_SDQ20
DDRAB_SDQ21
DDRAB_SDQ22
DDRAB_SDQ23

DDRAB_SDQ24
DDRAB_SDQ25
DDRAB_SDQ26
DDRAB_SDQ27
DDRAB_SDQ28
DDRAB_SDQ29
DDRAB_SDQ30
DDRAB_SDQ31

DDRAB_SDQ32
DDRAB_SDQ33
DDRAB_SDQ34
DDRAB_SDQ35
DDRAB_SDQ36
DDRAB_SDQ37
DDRAB_SDQ38
DDRAB_SDQ39

DDRAB_SDQ40
DDRAB_SDQ41
DDRAB_SDQ42
DDRAB_SDQ43
DDRAB_SDQ44
DDRAB_SDQ45
DDRAB_SDQ46
DDRAB_SDQ47

DDRAB_SDQ48
DDRAB_SDQ49
DDRAB_SDQ50
DDRAB_SDQ51
DDRAB_SDQ52
DDRAB_SDQ53
DDRAB_SDQ54
DDRAB_SDQ55

DDRAB_SDQ56
DDRAB_SDQ57
DDRAB_SDQ58
DDRAB_SDQ59
DDRAB_SDQ60
DDRAB_SDQ61
DDRAB_SDQ62
DDRAB_SDQ63

UAPU

E2 PR KABINI EM3000IBJ23HM 1.65G BGA 769P APU

E2 PR KABINI EM3000IBJ23HM 1.65G BGA 769P APU

M_ZVDDIO

+1.8VS

2

C195

1

B

DDRAB_SDQ[63..0]

<20>
<20>

<20>
<20>

HDMI

<20>
<20>

<20>
<20>

<21>
<21>

<21>
<21>

LVDS

<21>
<21>

<21>
<21>

<40>
<40>
<40>

<11,28,29>
<11,28,29>

<40>

<28,34,40,6>

<40>
<40>

<40>

UAPU

A6 PR KABINI AM5200IAJ44HM 2G BGA769P APU

A6 PR KABINI AM5200IAJ44HM 2G BGA769P APU

E2@UAPU

E2@

1 2

R74

R74

39.2_0402_1%

39.2_0402_1%

+1.5V

HDT+

JHDT2

JHDT2

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

SAMTE_ASP-136446-07-B@

SAMTE_ASP-136446-07-B@

C

HDMI & LVDS should be reverse in KABINI:

<8,9>

APU TX0 to Connector TX2 ; APU TX1 to Connector TX1
APU TX2 to Connector TX0 ; APU TX3 to Connector CLK

DP2_TXP0
DP2_TXN0

DP2_TXP1
DP2_TXN1

DP2_TXP2
DP2_TXN2

DP2_TXP3
DP2_TXN3

LVDS_A2
LVDS_A2#

LVDS_A1
LVDS_A1#

LVDS_A0
LVDS_A0#

LVDS_ACLK
LVDS_ACLK#

APU_SVT
APU_SVC
APU_SVD

EC_SMB_CK2

EC_SMB_DA2

APU_PWRGD

H_PROCHOT#

APU_VDDNB_SEN

APU_VDD_SEN

1 2

R124 0_0402 _5%@R124 0_0402 _5%@

1 2

R127 0_0402 _5%@R127 0_0402 _5%@

1 2

R117 0_0402_5%@R117 0_040 2_5%@

1 2

R118 0_0402_5%@R118 0_040 2_5%@

1 2

R120 0_0402_5%@R120 0_040 2_5%@

APU_VDD_RUN_FB_L

A6@UAPU

A6@

A4 PR KABINI AM5000IBJ44HM 1.5G BGA 769P APU

A4 PR KABINI AM5000IBJ44HM 1.5G BGA 769P APU

UAPU

E1@UAPU

E1@

E1 PR KABINI EM2100ICJ23HM 1G BGA769P APU

E1 PR KABINI EM2100ICJ23HM 1G BGA769P APU

UAPU

X2@UAPU

X2@

X2 ES2 KABINI ZMA5B078J2360 1.65G BGA CPU

X2 ES2 KABINI ZMA5B078J2360 1.65G BGA CPU

2

APU_TCK

2

4

APU_TMS

4

6

APU_TDI

6

8

APU_TDO

8

10

APU_PWRGD

10

12

APU_RST#

12

14

APU_DBRDY

14

16

APU_DBREQ#

16

18

APU_PLLTEST0

18

20

APU_PLLTEST1

20

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

APU_TDI
APU_TMS
APU_TCK
APU_DBREQ#

RP11, RP6 will @ when MP

Issued Date

Issued Date

Issued Date

C

DISPLAY/SVI2/JTAG/TEST

A9
B9

A10
B10

A11
B11

A12
B12

A4
B4

A5
B5

A6
B6

A7
B7

K15
H15

LDT_RST#

LDT_PWRGD

ESDU@

ESDU@

ESDU@

ESDU@

E1PC@UAPU

E1PC@

Compal Secret Data

Compal Secret Data

Compal Secret Data

G31
D27
E29

B22
B21

B20
A20

B19
A19

A22
B18

D29
D31
D35
D33
G27
B25
A25

D23
G23
E25
E23

AV33
AU33

DP_STEREOSYNC
CRT_HSYNC

+1.8VS

APU_SVT
APU_SVC
APU_SVD

APU_SIC
APU_SID

APU_RST#

APU_PWRGD

APU_PROCHOT#

APU_ALERT#

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

UAPU

A4@UAPU

A4@

APU_PWRGD

APU_RST#

1 2

C1270 100P_0402_50V8J

C1270 100P_0402_50V8J

1 2

C1273 100P_0402_50V8J

C1273 100P_0402_50V8J

UAPU

E1 PC 2M101082J2361 1G BGA 769P

E1 PC 2M101082J2361 1G BGA 769P

RP6

RP6

1 8
2 7
3 6
4 5

1K_0804_8P4R_5%

1K_0804_8P4R_5%

2012/04/22 2015/04/22

2012/04/22 2015/04/22

2012/04/22 2015/04/22

DISPLAY/SVI2/JTAG/TEST

TDP1_TXP0

TDP1_TXN0

TDP1_TXP1

TDP1_TXN1

TDP1_TXP2

TDP1_TXN2

TDP1_TXP3

TDP1_TXN3

LTDP0_TXP0

LTDP0_TXN0

LTDP0_TXP1

LTDP0_TXN1

LTDP0_TXP2

LTDP0_TXN2

LTDP0_TXP3

LTDP0_TXN3

DISP_CLKIN_H

DISP_CLKIN_L

SVT

SVC

SVD

SIC

SID

APU_RST_L

LDT_RST_L

APU_PWROK

LDT_PWROK

PROCHOT_L

ALERT_L

TDI

TDO

TCK

TMS

TRST_L

DBRDY

DBREQ_L

VDDCR_NB_SENSE

VDDCR_CPU_SENSE

VDDIO_MEM_S_SENSE

VSS_SENSE

VDD_095_FB_H

VDD_095_FB_L

FT3 REV 0.51

FT3 REV 0.51

PU +1.8VS + PD

APU_SCLK
APU_CLKINT
APU_SCLK
APU_CLKINT

Deciphered Date

Deciphered Date

Deciphered Date

D

UAPUC

UAPUC

DP_150_ZVSS

DP_2K_ZVSS

DP_BLON

DP_DIGON

DP_VARY_BL

TDP1_AUXP

TDP1_AUXN

TDP1_HPD

LTDP0_AUXP

LTDP0_AUXN

LTDP0_HPD

DAC_RED

DAC_GREEN

DAC_BLUE

DAC_HSYNC

DAC_VSYNC

DAC_SCL

DAC_SDA

DAC_ZVSS

THERMDA

THERMDC

DIECRACKMON

BP0

BP1

BP2

BP3

PLLTEST1

PLLTEST0

BYPASSCLK_H

BYPASSCLK_L

PLLCHRZ_H

PLLCHRZ_L

M_TEST

FREE_2

GIO_TSTDTM0_SERIALCLK

GIO_TSTDTM0_CLKINIT

USB_ATEST0

USB_ATEST1

M_ANALOGIN

M_ANALOGOUT

TMON_CAL

HDMI_EN/DP_STEREOSYNC

X4@

X4@

+1.8VS +3VS

R114

R114

1K_0402_5%

1K_0402_5%

1 2

For HDMI Need

RP3

@RP3

@

1 8
2 7
3 6
4 5

1K_0804_8P4R_5%

1K_0804_8P4R_5%

D

B16

DP_150_ZVSS

A21

DP_2K_ZVSS

B17
A17
A18

D17
E17

H19

D15
E15

H17

1 2

R897 100K_0402_5%R897 100K_0402_5%

B14

A14

B15

G19

CRT_HSYNC

E19

D19
D21

A16

DAC_ZVSS

H27
H29
D25
A27

APU_BP0

B27

APU_BP1

A26

APU_BP2

B26

APU_BP3

B28

APU_PLLTEST1

A28

APU_PLLTEST0

B24

APU_BPCLK_H

A24

APU_BPCLK_L

AV35
AU35
E33

A29
H21

APU_SCLK

H25

APU_CLKINT

AJ10
AJ8
R32
N32
AP29

E21

DP_STEREOSYNC

FT3_BGA769

FT3_BGA769

R113

R113
1K_0402_5%

1K_0402_5%

1 2

+1.8VS

E

1 2

R400 2K_0 402_1%R400 2K_0 402_1%

+3VS

1 2

R416 499_04 02_1%R416 499_0402_1%

ENBKL <28>
APU_ENVDD
APU_INVT_PWM

HDMI_CLK
HDMI_DATA

HDMI_DET

EDID_CLK
EDID_DATA

DAC_RED

DAC_GRN

DAC_BLU

CRT_HSYNC
CRT_VSYNC

CRT_DDC_CLK
CRT_DDC_DATA

<21>
<21>

<20,22>
<20,22>

<20>

<21>
<21>

<22>

<22>

CRT

<22>

<22>
<22>

<22>
<22>

+3VS

EDID_CLK

R255 4.7K_0402_5%R255 4.7K_0402_5%

EDID_DATA

R256 4.7K_0402_5%R256 4.7K_0402_5%

T39T39
T40T40
T41T41

T42T42

T45T45
T43T43
T44T44
T46T46
T47T47

PU +3VS

APU_ALERT#
APU_SID
APU_PROCHOT#
APU_SIC

PU +1.8VS

APU_SVT
APU_SVC
APU_SVD

APU_RST#
APU_PWRGD
APU_BPCLK_L

R80 300_0402_5%R80 300_0402_5%
R82 300_0402_5%R82 300_0402_5%
R18 511_0402_1%R18 511_0402_1%

PD

APU_BP2
APU_BP3
APU_BP0
APU_BP1

APU_TRST#
APU_PLLTEST0
APU_PLLTEST1

APU_BPCLK_H

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

FT3 DDR3/DISP/MISC//HDT+

FT3 DDR3/DISP/MISC//HDT+

FT3 DDR3/DISP/MISC//HDT+

R19 511_0402_1%R19 511_0402_1%

VAWGA/GB

VAWGA/GB

VAWGA/GB

12
12

RP23

RP23

18
27
36
45

150_0804_8P4R_1%

150_0804_8P4R_1%

RP4

RP4

1 8
2 7
3 6
4 5

1K_0804_8P4R_5%

1K_0804_8P4R_5%

RP5

@RP5

@

1 8
2 7
3 6
4 5

1K_0804_8P4R_5%

1K_0804_8P4R_5%

1 2
1 2
1 2

RP7

@RP7

@

1 8
2 7
3 6
4 5

1K_0804_8P4R_5%

1K_0804_8P4R_5%

RP8

RP8

1 8
2 7
3 6
4 5

1K_0804_8P4R_5%

1K_0804_8P4R_5%

1 2

E

DAC_BLU
DAC_GRN
DAC_RED
DP_150_ZVSS

+1.8VS

4 48Monday, April 01, 2013

4 48Monday, April 01, 2013

4 48Monday, April 01, 2013

+3VS

+1.8VS

1.0

1.0

1.0

A

R10

P_GPP_RXP0

R8

P_GPP_RXN0

R5

N10

GFX_CLKP
GFX_CLKN

GPP_CLK1P
GPP_CLK1N

GPP_CLK2P
GPP_CLK2N

T50T50

P_GPP_RXP1

R4

P_GPP_RXN1

N5

P_GPP_RXP2

N4

P_GPP_RXN2

P_GPP_RXP3

N8

P_GPP_RXN3

W8

P_TX_ZVDD_095

L5

P_GFX_RXP0

L4

P_GFX_RXN0

J5

P_GFX_RXP1

J4

P_GFX_RXN1

G5

P_GFX_RXP2

G4

P_GFX_RXN2

D7

P_GFX_RXP3

E7

P_GFX_RXN3

BA14

SATA_TX0P

AY14

SATA_TX0N

BA16

SATA_RX0N

AY16

SATA_RX0P

AY19

SATA_TX1P

BA19

SATA_TX1N

AY17

SATA_RX1N

BA17

SATA_RX1P

AR19

SATA_ZVSS

AP19

SATA_ZVDD_095

BA30

SATA_ACT_L/GPIO67

AY12

SATA_X1

BA12

SATA_X2

U4

GFX_CLKP

U5

GFX_CLKN

AC8

GPP_CLK0P

AC10

GPP_CLK0N

AE4

GPP_CLK1P

AE5

GPP_CLK1N

AC4

GPP_CLK2P

AC5

GPP_CLK2N

AA5

GPP_CLK3P

AA4

GPP_CLK3N

AP13

X14M_25M_48M_OSC

N2

X48M_X1

N1

X48M_X2

AY2

LPCCLK0

AW2

LPCCLK1

AT2

LAD0

AT1

LAD1

AR2

LAD2

AR1

LAD3

AP2

LFRAME_L

AP1

LDRQ0_L

AV29

SERIRQ/GPIO48

AP25

LPC_CLKRUN_L

AV2

LPC_PD_L/GEVENT5_L/SPI_TPM_CS_L

<24>

LAN

WLAN WLAN

1 1

VGA

2 2

HDD

ODD

PCIE_DTX_C_ARX_P1

<24>

PCIE_DTX_C_ARX_N1

<26>

PCIE_DTX_C_ARX_P2

<26>

PCIE_DTX_C_ARX_N2

<10>

PCIE_GTX_C_ARX_P0

<10>

PCIE_GTX_C_ARX_N0

<10>

PCIE_GTX_C_ARX_P1

<10>

PCIE_GTX_C_ARX_N1

<10>

PCIE_GTX_C_ARX_P2

<10>

PCIE_GTX_C_ARX_N2

<10>

PCIE_GTX_C_ARX_P3

<10>

PCIE_GTX_C_ARX_N3

<23>

SATA_ATX_DRX_P0

<23>

SATA_ATX_DRX_N0

<23>

SATA_DTX_C_ARX_N0

<23>

SATA_DTX_C_ARX_P0

<23>

SATA_ATX_DRX_P1

<23>

SATA_ATX_DRX_N1

<23>

SATA_DTX_C_ARX_N1

<23>

SATA_DTX_C_ARX_P1

R90 1K_0402_1%R90 1K_0402_1%
R96 1K_0402_1%R96 1K_0402_1%

+0.95VS

1 2

P_TX_ZVDD_095 P_RX_ZVDD_095

R404

R404

1.69K_0402_1%

1.69K_0402_1%

12
12

SATA_ZVSS
SATA_ZVDD

T48T48

0_0402_5%

VGA

<10>

CLK_PEG_VGA

<10>

CLK_PEG_VGA#

LAN

3 3

<24>

CLK_PCIE_LAN

<24>

CLK_PCIE_LAN#

<26>

CLK_PCIE_WLAN

<26>

CLK_PCIE_WLAN#

WLAN

R112
R115

R116
R119

R125
R126

0_0402_5%

1 2

@R112

@

1 2

@R115

@

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

1 2

@R116

@

1 2

@R119

@

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

1 2

@R125

@

1 2

@R126

@

0_0402_5%

0_0402_5%

48M_X1

1 2
1 2

48M_X2

R103 R104 for EMI

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

SERIRQ

A

R103 0_0402 _5%@R103 0_0402 _5%@
R104 0_0402 _5%@R104 0_0402 _5%@

<28,6>

LPC_CLK0_EC

<6>

LPC_CLK1

<28>
<28>
<28>
<28>
<28,6>

<28>

4 4

FT3 REV 0.51

FT3 REV 0.51

UAPUB

UAPUB

PCIE

PCIE

B

P_GPP_TXP0

P_GPP_TXN0

P_GPP_TXP1

P_GPP_TXN1

P_GPP_TXP2

P_GPP_TXN2

P_GPP_TXP3

P_GPP_TXN3

P_RX_ZVDD_095

P_GFX_TXP0

P_GFX_TXN0

P_GFX_TXP1

P_GFX_TXN1

P_GFX_TXP2

P_GFX_TXN2

P_GFX_TXP3

P_GFX_TXN3

X4@

X4@

UAPUE

UAPUE

CLK/SATA/USB/SPI/LPC

CLK/SATA/USB/SPI/LPC

FT3 REV 0.51

FT3 REV 0.51

B

L2
L1

K2

PCIE_ATX_DRX_P1

K1

PCIE_ATX_DRX_N1

J2

PCIE_ATX_DRX_P2

J1

PCIE_ATX_DRX_N2

H2
H1

W7

G2

PCIE_ATX_GRX_P0

G1

PCIE_ATX_GRX_N0

F2

PCIE_ATX_GRX_P1

F1

PCIE_ATX_GRX_N1

E2

PCIE_ATX_GRX_P2

E1

PCIE_ATX_GRX_N2

D2

PCIE_ATX_GRX_P3

D1

PCIE_ATX_GRX_N3

FT3_BGA769

FT3_BGA769

USBCLK/14M_25M_48M_OSC

USB_SS_ZVSS

USB_SS_ZVDD_095_USB3_DUAL

USB_SS_0TXP

USB_SS_0TXN

USB_SS_0RXP

USB_SS_0RXN

USB_SS_1TXP

USB_SS_1TXN

USB_SS_1RXP

USB_SS_1RXN

SPI_CLK/GPIO162

SPI_CS1_L/GPIO165

SPI_CS2_L/GPIO166

SPI_DO/GPIO163

SPI_DI/GPIO164

SPI_HOLD_L/GEVENT9_L

SPI_WP_L/GPIO161

FT3_BGA769X4@

FT3_BGA769X4@

USB_ZVSS

USB_HSD0P

USB_HSD0N

USB_HSD1P

USB_HSD1N

USB_HSD2P

USB_HSD2N

USB_HSD3P

USB_HSD3N

USB_HSD4P

USB_HSD4N

USB_HSD5P

USB_HSD5N

USB_HSD6P

USB_HSD6N

USB_HSD7P

USB_HSD7N

USB_HSD8P

USB_HSD8N

USB_HSD9P

USB_HSD9N

1 2

C19 0.1U_0402_16V7KC19 0.1U_0402_16V7K

1 2

C20 0.1U_0402_16V7KC20 0.1U_0402_16V7K

1 2

C17 0.1U_0402_16V7KC17 0.1U_0402_16V7K

1 2

C18 0.1U_0402_16V7KC18 0.1U_0402_16V7K

12

R73

R73
1K_0402_1%

1K_0402_1%

1 2

C1 0.1U_0402_16V7KPX@C1 0.1U_0402_16V7KPX@

1 2

C2 0.1U_0402_16V7KPX@C2 0.1U_0402_16V7KPX@

1 2

C3 0.1U_0402_16V7KPX@C3 0.1U_0402_16V7KPX@

1 2

C4 0.1U_0402_16V7KPX@C4 0.1U_0402_16V7KPX@

1 2

C5 0.1U_0402_16V7KPX@C5 0.1U_0402_16V7KPX@

1 2

C6 0.1U_0402_16V7KPX@C6 0.1U_0402_16V7KPX@

1 2

C7 0.1U_0402_16V7KPX@C7 0.1U_0402_16V7KPX@

1 2

C8 0.1U_0402_16V7KPX@C8 0.1U_0402_16V7KPX@

W4

AG4

USB_ZVSS

AL4
AL5

AJ4
AJ5

AG7
AG8

AG1
AG2

AF1
AF2

AE1
AE2

AD1
AD2

AC1
AC2

AB1
AB2

AA1
AA2

AE10
AE8

T2
T1

V2
V1

R1
R2

W1
W2

AU7
AW9
AR4
AR11
AR7
AU11
AU9

R641 11.8K_040 2_1%R641 11.8K_0402_1%

USBSS_ZVSS
USBSS_ZVDD

APU_SPI_CLK
APU_SPI_CS1#

APU_SPI_AOSI

APU_SPI_AISO

APU_SPI_HOLD#
APU_SPI_WP#

R644 1K_0 402_1%R644 1K_0 402_1%
R645 1K_0 402_1%R645 1K_0 402_1%

C

D

APU POWER SEQUENCE

PCIE_ATX_C_DRX_P1
PCIE_ATX_C_DRX_N1

PCIE_ATX_C_DRX_P2
PCIE_ATX_C_DRX_N2

+0.95VS_APU_GFX+0.95VS_APU_GFX

PCIE_ATX_C_GRX_P0
PCIE_ATX_C_GRX_N0

PCIE_ATX_C_GRX_P1
PCIE_ATX_C_GRX_N1

PCIE_ATX_C_GRX_P2
PCIE_ATX_C_GRX_N2

PCIE_ATX_C_GRX_P3
PCIE_ATX_C_GRX_N3

<24>
<24>

<26>
<26>

<10>
<10>

<10>
<10>

<10>
<10>

<10>
<10>

LAN

VGA

G-B

G-C

G-D

G-E

G-A

1 2

USB20_P0
USB20_N0

USB20_P1
USB20_N1

USB20_P3
USB20_N3

USB20_P4
USB20_N4

USB20_P5
USB20_N5

USB20_P6
USB20_N6

USB20_P7
USB20_N7

USB30_P8
USB30_N8

USB30_P9
USB30_N9

1 2
1 2

USB30_MTX_C_DRX_P0
USB30_MTX_C_DRX_N0

USB30_MRX_DTX_P0
USB30_MRX_DTX_N0

USB30_MTX_C_DRX_P1
USB30_MTX_C_DRX_N1

USB30_MRX_DTX_P1
USB30_MRX_DTX_N1

1 2

R110 33_040 2_5%R110 33_0402_5%

1 2

R111 33_040 2_5%R111 33_0402_5%

T51T51

1 2

R109 33_040 2_5%R109 33_0402_5%

<27>

Right USB port

<27>

<26>

Touch Screen

<26>

<21>

CAMERA

<21>

<30>

CardReader

<30>

<26>

WLAN/BT combo

<26>

<27>

USB2.0 LP1

<27>

<27>

USB2.0 LP2

<27>

<27>

MB USB3.0 port0

<27>

<27>

MB USB3.0 port1

<27>

+0.95VALW

<27>
<27>

<27>
<27>

<27>
<27>

<27>
<27>

R109,R110,R111 close to APU

APU_SPI_CLK_U
APU_SPI_CS1#_U

APU_SPI_AISO

APU_SPI_AOSI_U

APU_SPI_CLK_U

APU_SPI_CS1#_U

APU_SPI_AOSI_U

APU_SPI_AISO

R108 close to ROM

1 2

R108 33_040 2_5%R108 33_0402_5%

RP12

RP12

1 8
2 7
3 6
4 5

0_0804_8P4R_5%

0_0804_8P4R_5%

APU->EC->ROM must route as
Daisy Chain for Share ROM quality
(RP12 was request to added for the recoverable solution
as original method--backup)

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/04/22 2015/04/22

2012/04/22 2015/04/22

2012/04/22 2015/04/22

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+RTC

EC_ON

+3VALW/+5VALW

+1.8VALW

+0.95VALW

SYSON

+1.5V

SUSP#

+3VS

+1.8VS

+1.5VS

+0.95VS

VR_ON

+APU_CORE

+APU_CORE_NB

EC_SPI_AISO
EC_SPI_AOSI

EC_SPI_CLK
EC_SPI_CS1#

EC_SPI_AISO
EC_SPI_AOSI
EC_SPI_CLK
EC_SPI_CS1#

4MB SPI ROM
(Current Share mode)

+3VALW

R614

R614
10K_0402_5%

10K_0402_5%

1 2

1 2

R616

R616
10K_0402_5%

10K_0402_5%

D

APU_SPI_CS1#_U
APU_SPI_AISO_U
APU_SPI_WP#

U56

U56

1

CS#

2

SO/SIO1

3

WP#

4

GND

W25Q32FVSSIG SOIC 8P SPI ROM

W25Q32FVSSIG SOIC 8P SPI ROM

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

E

48MHz CRYSTAL

R938

R938
1M_0402_5%

1M_0402_5%

2

2

3

3

Y20

Y20
48MHZ_8PF_X3S048000D81H-W

48MHZ_8PF_X3S048000D81H-W

12

C794

<28>
<28>
<28>
<28>

C794
6P_0402_50V8

6P_0402_50V8

8

VCC

7

HOLD#

SCLK

SI/SIO0

APU_SPI_HOLD#

6

APU_SPI_CLK_U

5

APU_SPI_AOSI_U

APU_SPI_CLK_U

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

FT3 PCIE/SATA/CLK/USB/SPI

FT3 PCIE/SATA/CLK/USB/SPI

FT3 PCIE/SATA/CLK/USB/SPI

VAWGA/GB

VAWGA/GB

VAWGA/GB

1 2

R617

10_0402_5%

10_0402_5%

E

1

1

4

4

12

@

@

12

C635

C635

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

R615

R615
10K_0402_5%

10K_0402_5%

1 2

EMIU@R617

EMIU@

5 48Thursday, March 28, 2013

5 48Thursday, March 28, 2013

5 48Thursday, March 28, 2013

48M_X2

48M_X1

C795

C795
6P_0402_50V8

6P_0402_50V8

+3VALW

C636

EMIU@C636

EMIU@

10P_0402_50V8J

10P_0402_50V8J

1.0

1.0

1.0

A

1 2

C615

C615
150P_0402_50V8J

<28>

1 1

<24>
<26>

<11>

<27>
<27>

<31>

HDA_SDIN0

2 2

150P_0402_50V8J

LPC_RST#

<28>

<26>

<28>
<28>

<28>
<28>
<28>
<28>

LAN_CLKREQ#

WLAN_CLKREQ#

VGA_CLKREQ#

USB_OC0#

USB_OC1#

1 2

PBTN_OUT#

APU_PCIE_WAKE#

SLP_S3#
SLP_S5#

KBRST#
GATEA20
EC_SCI#
EC_SMI#

1 2

R578 0_0402_5%@R578 0_0402_5%@

R602

R602
33_0402_5%

33_0402_5%

LAN_CLKREQ#
WLAN_CLKREQ#

VGA_CLKREQ#_R

T55T55
T56T56
T57T57

LPC_RST_A#
APU_PCIE_RST#_BUF

EC_RSMRST#_R

PWR_GOOD_APU

APU_PCIE_WAKE#

TEST0
CS_JTAG_TMS_TEST1
TEST2

HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SYNC
HDA_RST#

32K_X1

32K_X2

T36T36

T53T53

T52T52
T54T54

AY4

LPC_RST_L

AY9

PCIE_RST_L

AY5

RSMRST_L

BA8

PWR_BTN_L

AM19

PWR_GOOD

AY7

SYS_RESET_L/GEVENT19_L

AW11

WAKE_L/GEVENT8_L

AY3

SLP_S3_L

BA5

SLP_S5_L

AU13

TEST0

AY10

TEST1/TMS

AY6

TEST2

AR23

KBRST_L

AR31

GA20IN/GEVENT0_L

AN5

LPC_PME_L/GEVENT3_L

AL7

LPC_SMI_L/GEVENT23_L

AP15

AC_PRES/IR_RX0/GEVENT16_L

AV13

IR_TX0/GEVENT21_L

BA9

IR_TX1/GEVENT6_L

BA10

IR_RX1/GEVENT20_L

AV15

IR_LED_L/LLB_L/GPIO184

AU29

CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60

AW29

CLK_REQ1_L/GPIO61

AR27

CLK_REQ2_L/GPIO62

AV27

CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63

AY29

CLK_REQG_L/GPIO65/OSCIN

AY8

USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L

AW1

USB_OC1_L/TDI/GEVENT13_L

AV1

USB_OC2_L/TCK/GEVENT14_L

AY1

USB_OC3_L/TDO/GEVENT15_L

AN2

AZ_BITCLK

AN1

AZ_SDOUT

AK2

AZ_SDIN0/GPIO167

AK1

AZ_SDIN1/GPIO168

AM1

AZ_SDIN2/GPIO169

AL2

AZ_SDIN3/GPIO170

AM2

AZ_SYNC

AL1

AZ_RST_L

AJ2

X32K_X1

AJ1

X32K_X2

PU +3VALW + PD

+3VALW

3 3

1 2

R691 10K_ 0402_5%@R691 10K_ 0402_5%@

1 2

R686 10K_ 0402_5%R686 10K_ 0402_5%

APU_GPIO174

<31>

HDA_RST#_AUDIO

<31>

HDA_SYNC_AUDIO

<31>

HDA_BITCLK_AUDIO

<31>

HDA_SDOUT_AUDIO

PU +3VALW

+3VALW

+3VS

RP14

RP14

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

10K_0804_8P4R_5%

1 2

R656 100K _0402_5%@R656 100K _0402_5%@

1 2

R650 100K _0402_5%R650 100K_0402_5%

1 2

R651 100K _0402_5%R651 100K_0402_5%

1 2

R121 0_0402 _5%

R121 0_0402 _5%

APU_SCLK1
APU_SDATA1
APU_PCIE_WAKE#

@

@

EC_LID_OUT#
USB_OC0#
USB_OC1#

PXS_PWREN

PU +3VS

+3VS

4 4

PD

1 2

R622 8.2K_0402 _5%@R622 8.2K_0402 _5%@

1 2

R621 8.2K_0402 _5%@R621 8.2K_0402 _5%@

1 2

R673 2.2K_0402 _5%R673 2.2K_0402_5%

1 2

R674 2.2K_0402 _5%R674 2.2K_0402_5%

1 2

R618 8.2K_0402 _5%@R618 8.2K_0402 _5%@

1 2

R684 10K_ 0402_5%@R684 10K_ 0402_5%@

1 2

R688 10K_ 0402_5%@R688 10K_ 0402_5%@

1 2

R689 10K_ 0402_5%@R689 10K_ 0402_5%@

A

WLAN_CLKREQ#

LAN_CLKREQ#
APU_SCLK0
APU_SDATA0

VGA_CLKREQ#_R

HDA_BITCLK

HDA_SDIN0

VGA_CLKREQ#_R

EC_RSMRST# , POWER_GOOD
follow CRB
(APU side 1.8V power rail)

<28>

EC_RSMRST#

<28>

SYS_PWRGD_EC

PU +3VALW + PD

TEST0
CS_JTAG_TMS_TEST1
TEST2

B

UAPUD

UAPUD

ACPI/SD/AZ/GPIO/RTC/MISC

ACPI/SD/AZ/GPIO/RTC/MISC

FT3 REV 0.51

FT3 REV 0.51

RP13

RP13

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

33_0804_8P4R_5%

Must connected to 10 ms RC delay
circuit on +1.8-V S5 power rail.

D3

D3

1 2

RB751V-40TE17_SOD323-2

RB751V-40TE17_SOD323-2

D5

D5

1 2

RB751V-40TE17_SOD323-2

RB751V-40TE17_SOD323-2

RP9

@RP9

@

1 8
2 7
3 6
4 5

1K_0804_8P4R_5%

1K_0804_8P4R_5%

RP10

@RP10

@

1 8
2 7
3 6
4 5

15K_0804_8P4R_5%

B

15K_0804_8P4R_5%

HDA_RST#
HDA_SYNC
HDA_BITCLK
HDA_SDOUT

EC_RSMRST#_R

PWR_GOOD_APU

1U_0402_6.3V6K

1U_0402_6.3V6K

+3VALW

SD_PWR_CTRL

SD_CLK/GPIO73

SD_CMD/GPIO74

SD_CD/GPIO75

SD_WP/GPIO76

SD_DATA0/GPIO77

SD_DATA1/GPIO78

SD_DATA2/GPIO79

SD_DATA3/GPIO80

SD_LED/GPIO45

SCL0/GPIO43

SDA0/GPIO47

SCL1/GPIO227

SDA1/GPIO228

GPIO49

GPIO50

GPIO51

GPIO55

GPIO57

GPIO58

GPIO59

GPIO64

SPKR/GPIO66

GPIO68

GPIO69

GPIO70

GPIO71

GPIO174

GEVENT2_L

GEVENT4_L

GEVENT7_L

GEVENT10_L

GEVENT11_L

GEVENT17_L

BLINK/GEVENT18_L

GEVENT22_L

GENINT1_L/GPIO32

GENINT2_L/GPIO33

FANOUT0/GPIO52

FANIN0/GPIO56

RTCCLK

X4@

X4@

BA23
AY22

AY23
AY20
BA20

BA22
AY21
AY24
BA24

AY25

AU25
AV25

AY11
BA11

AP27
AY28
BA28
AV23
AP21
BA26
AV19
AY27
BA27
AU21
AY26
AV21
AM21
BA3

AV17
BA4
AR15
AP17
AP11
AN8
AU17
BA6

BA29
AP23

AV31
AU31

AV11

FT3_BGA769

FT3_BGA769

C

APU_SCLK0
APU_SDATA0

1 2

R122 0_0402_5%@R122 0_040 2_5%@

1 2

R661 0_0402_5%@R661 0_040 2_5%@

APU_GPIO174

GEVENT2#

EC_LID_OUT#

VGA_PWRGD

APU_SCLK1
APU_SDATA1

APU_SCLK0
APU_SDATA0

Board_ID1

PXS_PWREN

EC_LID_OUT#

BT_DISABLE#

H_PROCHOT#

VGA_PWRGD

<26,8,9>
<26,8,9>

<28>

<26>

RTC_CLK

APU_PCIE_RST#_BUF

BT_OFF#

WL_OFF#
ODD_EN

PXS_RST#
APU_SPKR
PXS_PWREN

<28,34,4,40>

<39>

<28>

D

1 2

R907

R907
33_0402_5%

33_0402_5%

C912

C912

150P_0402_50V8J

150P_0402_50V8J

If use as SMBUS :
Pulled-up to VDD_33(port0) , VDD_33_ALW(port1) with a resistor of:
Qty: 1; Value: 2.2 KΩ; Tol: 5%
If no use :
Pulled-up to VDD_33(port0) , VDD_33_ALW(port1) with a resistor of:

<26>

Qty: 1; Value: 10 KΩ; Tol: 5%

<26>
<23>

<10>
<31>
<12,28,39>

STRAPS OF APU

LPC_FRAME# LPC_CLK0_EC LPC_CLK1 GEVENT2_L

SPI ROM
(

H

+1.8VALW

L

R345

R345

47K_0402_5%

47K_0402_5%

C209

C209

R685

R685
10K_0402_5%

10K_0402_5%

1 2

1 2

<28,5>

LPC_FRAME#

<28,5>

1

1

1U_0402_6.3V6K

1U_0402_6.3V6K
C212

C212

2

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/04/22 2015/04/22

2012/04/22 2015/04/22

2012/04/22 2015/04/22

LPC_CLK0_EC

<5>

LPC_CLK1

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

DEFAULT)

LPC ROM

GEVENT2#

RTC_CLK

D

12

R902

R902
10K_0402_5%

10K_0402_5%

12

@

@

R903

R903
2K_0402_5%

2K_0402_5%

BOOT FAIL TIMER
ENABLED

BOOT FAIL TIMER
D
(DEFAULT)

ISABLED

1

2

12

@

@

R904

R904
10K_0402_5%

10K_0402_5%

12

R926

R926
2K_0402_5%

2K_0402_5%

E

APU_PCIE_RST#

+3VS

12

R911

UMA@ R911

UMA@

10K_0402_5%

10K_0402_5%

Board_ID1

Board_ID1

0 PX5.5

1

Function

UMA

12

R912

PX@ R912

PX@

10K_0402_5%

10K_0402_5%

32.768KMHz CRYSTAL

1

2

NORMAL POWR
UP/RESET TIMING
(DEFAULT)

FAST POWER
U
FOR SIMULATION

R949

R949
10K_0402_5%

10K_0402_5%

@

@

R950

R950

2.2K_0402_5%

2.2K_0402_5%

E

32K_X1

32K_X2

C686

C686
18P_0402_50V8J

18P_0402_50V8J

RTC_CLK

P/RESET TIMING

6 48Thursday, March 28, 2013

6 48Thursday, March 28, 2013

6 48Thursday, March 28, 2013

1 2

R914

R914
20M_0402_5%

20M_0402_5%

Y3

Y3

32.768KHZ_12.5P_1TJF125DP1A000D

32.768KHZ_12.5P_1TJF125DP1A000D

1 2

1

C682

C682
22P_0402_50V8J

22P_0402_50V8J

2

CLKGEN
ENABLE
(DEFAULT)

CLKGEN
DISABLED

12

R925

R925
10K_0402_5%

10K_0402_5%

12

@

@

R927

R927
2K_0402_5%

2K_0402_5%

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

.8V SPI ROM

1

3.3V SPI ROM
(DEFAULT)

+3VALW

12

@

@

R928

R928
10K_0402_5%

10K_0402_5%

12

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

FT3 GPIO/AZ/MISC

FT3 GPIO/AZ/MISC

FT3 GPIO/AZ/MISC

VAWGA/GB

VAWGA/GB

VAWGA/GB

R929

R929

2.2K_0402_5%

2.2K_0402_5%

12

12

<10,24,26>

1.0

1.0

1.0

A

B

C

D

E

CORE POWER OF APU

+APU_CORE

1 1

VDDCR_CPU

C179 1U_0402_6.3V6KC179 1U_0402_6.3V6K

C184 1U_0402_6.3V6KC184 1U_0402_6.3V6K

C186 1U_0402_6.3V6KC186 1U_0402_6.3V6K

C180 1U_0402_6.3V6KC180 1U_0402_6.3V6K

C181 1U_0402_6.3V6KC181 1U_0402_6.3V6K

C182 1U_0402_6.3V6K@C182 1U_0402_6.3V6K

1

2

C183 1U_0402_6.3V6KC183 1U_0402_6.3V6K

1

1

1

1

2

2

2

2

C187 1U_0402_6.3V6KC187 1U_0402_6.3V6K

1

1

2

2

C190 180P_0402_50V8JC190 180P_0402_50V8J

C188 1U_0402_6.3V6KC188 1U_0402_6.3V6K

C189 1U_0402_6.3V6KC189 1U_0402_6.3V6K

1

2

1

1

1

2

2

2

RTC OF APU

+RTCBATT_R

C166

C166

0.22U_0402_10V6K

0.22U_0402_10V6K

VDDBT_RTC_G

W=20mils

1

2

+RTCBATT

1 2

R93 10K_0402_5%R93 10K_0402_5%

12

CLRP1

J@CLRP1

J@

SHORT PADS

SHORT PADS

Need OPEN

for Clear CMOS

@

INTEGRATED GPU POWER OF APU +3VALW/+3VS OF APU

+APU_CORE_NB

2 2

+1.5V/+1.5VS OF APU

C924 10U_0603_6.3V6MC924 10U_0603_6.3V6M

+0.95VALW/+0.95VS OF APU

3 3

+0.95VS +0.95VS_APU_GFX

VDD_095

C934 10U_0603_6.3V6MC934 10U_0603_6.3V6M

C935 10U_0603_6.3V6MC935 10U_0603_6.3V6M

C198 1U_0402_6.3V6KC198 1U_0402_6.3V6K

1

1

2

2

4 4

VDD_095_USB3_DUAL

VDDCR_NB

C201 1U_0402_6.3V6KC201 1U_0402_6.3V6K

C202 1U_0402_6.3V6KC202 1U_0402_6.3V6K

C200 1U_0402_6.3V6KC200 1U_0402_6.3V6K

1

1

1

2

2

2

C194 1U_0402_6.3V6KC194 1U_0402_6.3V6K

C191 1U_0402_6.3V6KC191 1U_0402_6.3V6K

C192 1U_0402_6.3V6KC192 1U_0402_6.3V6K

C193 1U_0402_6.3V6KC193 1U_0402_6.3V6K

1

1

1

1

2

2

2

2

VDDIO_MEM_S

C923 0.1U_0402_16V7KC923 0.1U_0402_16V7K

C927 0.1U_0402_16V7KC927 0.1U_0402_16V7K

C928 0.1U_0402_16V7KC928 0.1U_0402_16V7K

C931 0.1U_0402_16V7KC931 0.1U_0402_16V7K

C932 0.1U_0402_16V7KC932 0.1U_0402_16V7K

C949 10U_0603_6.3V6M@C949 10U_0603_6.3V6M

C925 10U_0603_6.3V6MC925 10U_0603_6.3V6M

1

2

C926 0.1U_0402_16V7KC926 0.1U_0402_16V7K

1

1

1

2

2

1

1

2

2

2

@

C930 0.1U_0402_16V7KC930 0.1U_0402_16V7K

C929 0.1U_0402_16V7K@C929 0.1U_0402_16V7K

1

1

2

2

C211 180P_0402_50V8JC211 180P_0402_50V8J

1

1

1

1

2

2

2

2

@

VDD_095_GFX

L22

L22

FBMA-L11-201209-121LMA50T_0805

C205 1U_0402_6.3V6KC205 1U_0402_6.3V6K

C206 1U_0402_6.3V6KC206 1U_0402_6.3V6K

C199 1U_0402_6.3V6K@C199 1U_0402_6.3V6K

C204 1U_0402_6.3V6K@C204 1U_0402_6.3V6K

1

1

1

1

2

2

2

2

@

@

FBMA-L11-201209-121LMA50T_0805

C213 180P_0402_50V8JC213 180P_0402_50V8J

C260 1U_0402_6.3V6KC260 1U_0402_6.3V6K

1

1

1

2

2

2

12

+0.95VALW +0.95VALW

C214 1U_0402_6.3V6KC214 1U_0402_6.3V6K

C216 1U_0402_6.3V6KC216 1U_0402_6.3V6K

C938 10U_0603_6.3V6MC938 10U_0603_6.3V6M

C937 10U_0603_6.3V6MC937 10U_0603_6.3V6M

1

2

C221 1U_0402_6.3V6K@C221 1U_0402_6.3V6K

C218 180P_0402_50V8JC218 180P_0402_50V8J

1

1

1

2

1

1

2

2

2

2

C220 1U_0402_6.3V6KC220 1U_0402_6.3V6K

@

VDD_095_ALW VDD_18_ALW

A

+3VS

C197 180P_0402_50V8JC197 180P_0402_50V8J

1

2

C257 180P_0402_50V8JC257 180P_0402_50V8J

C249 1U_0402_6.3V6KC249 1U_0402_6.3V6K

1

1

2

2

+3VALW_APU

C253 1U_0402_6.3V6KC253 1U_0402_6.3V6K

C252 1U_0402_6.3V6KC252 1U_0402_6.3V6K

1

1

2

2

@

@

R582 0_0603_5%

R582 0_0603_5%

+1.5V +APU_CORE

VDD_33_ALWVDD_33

VDDIO_AZ_ALW

PLANE SPLIT

C230 180P_0402_50V8JC230 180P_0402_50V8J

C231 180P_0402_50V8JC231 180P_0402_50V8J

C207 180P_0402_50V8J@C207 180P_0402_50V8J

C208 180P_0402_50V8J@C208 180P_0402_50V8J

C210 180P_0402_50V8JC210 180P_0402_50V8J

1

2

1

1

1

1

2

2

2

2

@

@

(Could be S0 or S5 power rail)

+1.5VS+1.5V

C259 180P_0402_50V8JC259 180P_0402_50V8J

C258 180P_0402_50V8JC258 180P_0402_50V8J

1

1

2

2

C161 4.7U_0603_6.3V6KC161 4.7U_0603_6.3V6K

1

2

C232 180P_0402_50V8JC232 180P_0402_50V8J

C254 1U_0402_6.3V6KC254 1U_0402_6.3V6K

C256 1U_0402_6.3V6K@C256 1U_0402_6.3V6K

C255 1U_0402_6.3V6KC255 1U_0402_6.3V6K

1

1

1

1

2

2

2

2

@

+1.8VALW/+1.8VS OF APU

+1.8VS

C203 1U_0402_6.3V6KC203 1U_0402_6.3V6K

C936 10U_0603_6.3V6MC936 10U_0603_6.3V6M

1

2

C219 1U_0402_6.3V6KC219 1U_0402_6.3V6K

C222 1U_0402_6.3V6KC222 1U_0402_6.3V6K

C217 1U_0402_6.3V6K@C217 1U_0402_6.3V6K

1

1

1

1

2

2

2

2

C933 10U_0603_6.3V6MC933 10U_0603_6.3V6M

1

2

1

2

@

VDD_18

C236 1U_0402_6.3V6KC236 1U_0402_6.3V6K

C237 1U_0402_6.3V6KC237 1U_0402_6.3V6K

C238 1U_0402_6.3V6KC238 1U_0402_6.3V6K

C239 1U_0402_6.3V6KC239 1U_0402_6.3V6K

C240 1U_0402_6.3V6KC240 1U_0402_6.3V6K

1

1

2

2

+1.8VALW

C160 4.7U_0603_6.3V6KC160 4.7U_0603_6.3V6K

1

2

B

C233 180P_0402_50V8JC233 180P_0402_50V8J

1

1

1

1

2

2

2

2

+1.5VS

+1.8VALW

+3VALW_APU

C250 1U_0402_6.3V6KC250 1U_0402_6.3V6K

C244 1U_0402_6.3V6KC244 1U_0402_6.3V6K

1

2

C245 180P_0402_50V8JC245 180P_0402_50V8J

C246 1U_0402_6.3V6KC246 1U_0402_6.3V6K

C248 1U_0402_6.3V6KC248 1U_0402_6.3V6K

1

2

1

1

1

2

2

2

+0.95VALW

+0.95VALW

+RTCBATT_R

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

+3VALW

12

UAPUF

UAPUF

POWER

J35

VDDIO_MEM_S_1

L32

VDDIO_MEM_S_2

L37

VDDIO_MEM_S_3

N35

VDDIO_MEM_S_4

R31

VDDIO_MEM_S_5

R37

VDDIO_MEM_S_6

U32

VDDIO_MEM_S_7

U35

VDDIO_MEM_S_8

W31

VDDIO_MEM_S_9

W32

VDDIO_MEM_S_10

W37

VDDIO_MEM_S_11

AA31

VDDIO_MEM_S_12

AA35

VDDIO_MEM_S_13

AC32

VDDIO_MEM_S_14

AC37

VDDIO_MEM_S_15

AE31

VDDIO_MEM_S_16

AE35

VDDIO_MEM_S_17

AG32

VDDIO_MEM_S_18

AG37

VDDIO_MEM_S_19

AJ35

VDDIO_MEM_S_20

AL32

VDDIO_MEM_S_21

AL37

VDDIO_MEM_S_22

AR35

VDDIO_MEM_S_23

AL10

VDDIO_AZ_ALW_1

AL11

VDDIO_AZ_ALW_2

B1

VDD_18_ALW_1

B2

VDD_18_ALW_2

AL13

VDD_33_ALW_1

AM13

VDD_33_ALW_2

AR5

VDD_095_USB3_DUAL_1

AU4

VDD_095_USB3_DUAL_2

AV7

VDD_095_USB3_DUAL_3

AW5

VDD_095_USB3_DUAL_4

AE11

VDD_095_ALW_1

AE13

VDD_095_ALW_2

AJ11

VDD_095_ALW_3

AJ13

VDD_095_ALW_4

AN4

VDDBT_RTC_G

2012/04/22 2015/04/22

2012/04/22 2015/04/22

2012/04/22 2015/04/22

POWER

FT3 REV 0.51

FT3 REV 0.51

Compal Secret Data

Compal Secret Data

Compal Secret Data

L21

VDDCR_CPU_1

L23

VDDCR_CPU_2

L25

VDDCR_CPU_3

L27

VDDCR_CPU_4

L29

VDDCR_CPU_5

N21

VDDCR_CPU_6

N23

VDDCR_CPU_7

N27

VDDCR_CPU_8

R21

VDDCR_CPU_9

R23

VDDCR_CPU_10

R27

VDDCR_CPU_11

U21

VDDCR_CPU_12

U23

VDDCR_CPU_13

U27

VDDCR_CPU_14

W21

VDDCR_CPU_15

W23

VDDCR_CPU_16

W27

VDDCR_CPU_17

AA21

VDDCR_CPU_18

AA23

VDDCR_CPU_19

AA27

VDDCR_CPU_20

AC21

VDDCR_CPU_21

AC23

VDDCR_CPU_22

AC27

VDDCR_CPU_23

AE21

VDDCR_CPU_24

AE23

VDDCR_CPU_25

AE27

VDDCR_CPU_26

L13

VDDCR_NB_1

L17

VDDCR_NB_2

N11

VDDCR_NB_3

N13

VDDCR_NB_4

N17

VDDCR_NB_5

R11

VDDCR_NB_6

R13

VDDCR_NB_7

R17

VDDCR_NB_8

U13

VDDCR_NB_9

U17

VDDCR_NB_10

W13

VDDCR_NB_11

W17

VDDCR_NB_12

AA13

VDDCR_NB_13

AA17

VDDCR_NB_14

AC13

VDDCR_NB_15

AC17

VDDCR_NB_16

AE15

VDDCR_NB_17

AE17

VDDCR_NB_18

AE19

VDDCR_NB_19

AG17

VDDCR_NB_20

AG21

VDDCR_NB_21

A2

VDD_18_1

A3

VDD_18_2

B3

VDD_18_3

C3

VDD_18_4

AM15

VDD_33_1

AM17

VDD_33_2

AG23

VDD_095_1

AG27

VDD_095_2

AJ21

VDD_095_3

AJ27

VDD_095_4

AL21

VDD_095_5

AL23

VDD_095_6

AL27

VDD_095_7

AM23

VDD_095_8

AM25

VDD_095_9

U10

VDD_095_GFX_1

W10

VDD_095_GFX_2

AA10

VDD_095_GFX_3

X4@

X4@

FT3_BGA769

FT3_BGA769

Deciphered Date

Deciphered Date

Deciphered Date

+APU_CORE_NB

+1.8VS

+3VS

+0.95VS

+0.95VS_APU_GFX

D

UAPUH

UAPUH

UAPUG

UAPUG

GND

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSS_13

VSS_14

VSS_15

VSS_16

VSS_17

VSS_18

VSS_19

VSS_20

VSS_21

VSS_22

VSS_23

VSS_24

VSS_25

VSS_26

VSS_27

VSS_28

VSS_29

VSS_30

VSS_31

VSS_32

VSS_33

VSS_34

VSS_35

VSS_36

VSS_37

VSS_38

VSS_39

VSS_40

VSS_41

VSS_42

VSS_43

VSS_44

VSS_45

VSS_46

VSS_47

VSS_48

VSS_49

VSS_50

VSS_51

VSS_52

VSS_53

VSS_54

VSS_55

VSS_56

VSS_57

VSS_58

VSS_59

VSS_60

VSS_61

VSS_62

GND

FT3 REV 0.51

FT3 REV 0.51

J3

VSS_63

J7

VSS_64

J8

VSS_65

J39

VSS_66

K11

VSS_67

K13

VSS_68

K17

VSS_69

K19

VSS_70

K21

VSS_71

K23

VSS_72

K25

VSS_73

K27

VSS_74

K29

VSS_75

K31

VSS_76

L3

VSS_77

L7

VSS_78

L8

VSS_79

L10

VSS_80

L11

VSS_81

L15

VSS_82

L19

VSS_83

L31

VSS_84

L39

VSS_85

L41

VSS_86

M1

VSS_87

M2

VSS_88

N3

VSS_89

N7

VSS_90

N15

VSS_91

N19

VSS_92

N25

VSS_93

N29

VSS_94

N31

VSS_95

N39

VSS_96

P1

VSS_97

P2

VSS_98

R3

VSS_99

R7

VSS_100

R15

VSS_101

R19

VSS_102

R25

VSS_103

R29

VSS_104

R39

VSS_105

R41

VSS_106

U1

VSS_107

U2

VSS_108

U3

VSS_109

U7

VSS_110

U8

VSS_111

U11

VSS_112

U15

VSS_113

U19

VSS_114

U25

VSS_115

U29

VSS_116

U31

VSS_117

U39

VSS_118

W3

VSS_119

W5

VSS_120

W11

VSS_121

W15

VSS_122

W19

VSS_123

W25

VSS_124

X4@

X4@

FT3_BGA769

FT3_BGA769

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet

W29
W39
W41

Y1

Y2
AA3
AA7
AA8

AA11
AA15
AA19
AA25
AA29
AA39

AC3
AC7

AC11
AC15
AC19
AC25
AC29
AC31
AC39
AC41

AE3
AE7

AE25
AE29
AE32
AE39

AG3
AG5

AG10
AG11
AG13
AG15
AG19
AG25
AG29
AG31
AG39
AG41

AH1
AH2

AJ3

AJ7
AJ15
AJ17
AJ19
AJ23
AJ25
AJ29
AJ31
AJ32
AJ39

AL3

AL8
AL15
AL17
AL19
AL25
AL29

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

FT3 PW R/GND

FT3 PW R/GND

FT3 PW R/GND

VAWGA/GB

VAWGA/GB

VAWGA/GB

A8
A13
A23
A31
A35
A39

B8
B13
B23
B31
B39

C1

C2

C5

C7

C9
C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31
C33
C35
C37
C39
C41

D9
D11
D13

E3

E4

E9
E11
E13
E27
E31
E35
E38
E39

G3

G7
G11
G13
G15
G17
G21
G25
G29
G35
G37
G39
G41
H11
H13
H23
H31

VSS_125

VSS_126

VSS_127

VSS_128

VSS_129

VSS_130

VSS_131

VSS_132

VSS_133

VSS_134

VSS_135

VSS_136

VSS_137

VSS_138

VSS_139

VSS_140

VSS_141

VSS_142

VSS_143

VSS_144

VSS_145

VSS_146

VSS_147

VSS_148

VSS_149

VSS_150

VSS_151

VSS_152

VSS_153

VSS_154

VSS_155

VSS_156

VSS_157

VSS_158

VSS_159

VSS_160

VSS_161

VSS_162

VSS_163

VSS_164

VSS_165

VSS_166

VSS_167

VSS_168

VSS_169

VSS_170

VSS_171

VSS_172

VSS_173

VSS_174

VSS_175

VSS_176

VSS_177

VSS_178

VSS_179

VSS_180

VSS_181

VSS_182

VSS_183

VSS_184

VSS_185

VSS_186

GND

GND

FT3 REV 0.51

FT3 REV 0.51

E

VSS_187

VSS_188

VSS_189

VSS_190

VSS_191

VSS_192

VSS_193

VSS_194

VSS_195

VSS_196

VSS_197

VSS_198

VSS_199

VSS_200

VSS_201

VSS_202

VSS_203

VSS_204

VSS_205

VSS_206

VSS_207

VSS_208

VSS_209

VSS_210

VSS_211

VSS_212

VSS_213

VSS_214

VSS_215

VSS_216

VSS_217

VSS_218

VSS_219

VSS_220

VSS_221

VSS_222

VSS_223

VSS_224

VSS_225

VSS_226

VSS_227

VSS_228

VSS_229

VSS_230

VSS_231

VSS_232

VSS_233

VSS_234

VSS_235

VSS_236

VSS_237

VSS_238

VSS_239

VSS_240

VSS_241

VSS_242

VSSBG_DAC

VBURN

X4@

X4@

7 48Thursday, March 28, 2013

7 48Thursday, March 28, 2013

7 48Thursday, March 28, 2013

PSEN

FT3_BGA769

FT3_BGA769

of

AL39
AL41
AM11
AM27
AM31
AN3
AN7
AN39
AP31
AR3
AR13
AR17
AR21
AR25
AR29
AR39
AR41
AU1
AU2
AU3
AU15
AU19
AU23
AU27
AU39
AV9
AW3
AW7
AW13
AW15
AW17
AW19
AW21
AW23
AW25
AW27
AW31
AW33
AW35
AW37
AW39
AW41
AY13
AY15
AY18
AY30
BA2
BA7
BA13
BA15
BA18
BA21
BA25
BA31
BA35
BA39
A15
AL31
AM29

1.0

1.0

1.0

A

B

C

D

E

+1.5V +1.5V+VREF_DQ

2

1

C176

C176

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1000P_0402_50V7K

1 1

<4,9>
<4,9>

<4,9>
<4,9>

<4>

2 2

3 3

4 4

<4,9>

<4>
<4>

<4,9>

<4,9>
<4,9>

<4>

<4,9>
<4,9>

<4,9>
<4,9>

C135

C135

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

+3VS

1

2

1000P_0402_50V7K

DDRAB_SDQS1#
DDRAB_SDQS1

DDRAB_SDQS2#
DDRAB_SDQS2

DDRA_CKE0

DDRAB_SBS2#

DDRA_CLK0
DDRA_CLK0#

DDRAB_SBS0#

DDRAB_SWE#

DDRAB_SCAS#

DDRA_SCS1#

DDRAB_SDQS4#
DDRAB_SDQS4

DDRAB_SDQS6#
DDRAB_SDQS6

1

C136

C136

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

A

DDRAB_SDQ0
DDRAB_SDQ1

C142

C142

DDRAB_SDM0

DDRAB_SDQ2
DDRAB_SDQ3

DDRAB_SDQ8
DDRAB_SDQ9

DDRAB_SDQS1#
DDRAB_SDQS1

DDRAB_SDQ10
DDRAB_SDQ11

DDRAB_SDQ16
DDRAB_SDQ17

DDRAB_SDQS2#
DDRAB_SDQS2

DDRAB_SDQ18
DDRAB_SDQ19

DDRAB_SDQ24
DDRAB_SDQ25

DDRAB_SDM3

DDRAB_SDQ26
DDRAB_SDQ27

DDRA_CKE0

DDRAB_SBS2#

DDRAB_SMA12
DDRAB_SMA9

DDRAB_SMA8
DDRAB_SMA5

DDRAB_SMA3
DDRAB_SMA1

DDRA_CLK0
DDRA_CLK0#

DDRAB_SMA10
DDRAB_SBS0#

DDRAB_SWE#
DDRAB_SCAS# DDRA_ODT0

DDRAB_SMA13
DDRA_SCS1#

DDRAB_SDQ32
DDRAB_SDQ33

DDRAB_SDQS4#
DDRAB_SDQS4

DDRAB_SDQ34
DDRAB_SDQ35

DDRAB_SDQ40
DDRAB_SDQ41

DDRAB_SDM5

DDRAB_SDQ42
DDRAB_SDQ43

DDRAB_SDQ48
DDRAB_SDQ49

DDRAB_SDQS6#
DDRAB_SDQS6

DDRAB_SDQ50
DDRAB_SDQ51

DDRAB_SDQ56
DDRAB_SDQ57

DDRAB_SDM7

DDRAB_SDQ58
DDRAB_SDQ59

R69 10K_0402_5%R69 10K_0402_5%

+3VS

1 2

12

R70

R70

10K_0402_5%

10K_0402_5%

JDIMM1

JDIMM1

15mil

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

205

VREF_CA
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0

EVENT#
VDDSPD
SA1
VTT1

G1

FOX_AS0A626-U8SN-7F

FOX_AS0A626-U8SN-7F

ME@

ME@

DIMM_A H:8mm

<Address: 00>

DQ4
DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6
DQ7

VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

SDA
SCL

VTT2

2
4

DDRAB_SDQ4

6

DDRAB_SDQ5

8
10

DDRAB_SDQS0#

12

DDRAB_SDQS0

14
16

DDRAB_SDQ6

18

DDRAB_SDQ7

20
22

DDRAB_SDQ12

24

DDRAB_SDQ13

26
28

DDRAB_SDM1

30

MEM_MAB_RST#

32
34

DDRAB_SDQ14

36

DDRAB_SDQ15

38
40

DDRAB_SDQ20

42

DDRAB_SDQ21

44
46

DDRAB_SDM2

48
50

DDRAB_SDQ22

52

DDRAB_SDQ23

54
56

DDRAB_SDQ28

58

DDRAB_SDQ29

60
62

DDRAB_SDQS3#

64

DDRAB_SDQS3

66
68

DDRAB_SDQ30

70

DDRAB_SDQ31

72

74
76
78

A15

80

A14

82
84

A11

86

A7

88
90

A6

92

A4

94
96

A2

98

A0

100
102
104
106
108
110
112
114

S0#

116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

G2

B

DDRA_CKE1

DDRAB_SMA15
DDRAB_SMA14

DDRAB_SMA11
DDRAB_SMA7

DDRAB_SMA6
DDRAB_SMA4

DDRAB_SMA2
DDRAB_SMA0

DDRA_CLK1
DDRA_CLK1#

DDRAB_SBS1#
DDRAB_SRAS#

DDRA_SCS0#

DDRA_ODT1

15mil

DDRAB_SDQ36
DDRAB_SDQ37

DDRAB_SDM4

DDRAB_SDQ38
DDRAB_SDQ39

DDRAB_SDQ44
DDRAB_SDQ45

DDRAB_SDQS5#
DDRAB_SDQS5

DDRAB_SDQ46
DDRAB_SDQ47

DDRAB_SDQ52
DDRAB_SDQ53

DDRAB_SDM6

DDRAB_SDQ54
DDRAB_SDQ55

DDRAB_SDQ60
DDRAB_SDQ61

DDRAB_SDQS7#
DDRAB_SDQS7

DDRAB_SDQ62
DDRAB_SDQ63

MEM_MAB_EVENT#

+0.75VS

DDRAB_SDQS0#
DDRAB_SDQS0

MEM_MAB_RST#

DDRAB_SDQS3#
DDRAB_SDQS3

DDRA_CKE1

DDRA_CLK1
DDRA_CLK1#

DDRAB_SBS1#
DDRAB_SRAS#

DDRA_SCS0#
DDRA_ODT0

DDRA_ODT1

1000P_0402_50V7K

1000P_0402_50V7K

DDRAB_SDQS5#
DDRAB_SDQS5

DDRAB_SDQS7#
DDRAB_SDQS7

MEM_MAB_EVENT# <4,9>

APU_SDATA0
APU_SCLK0

<4,9>
<4,9>

<4,9>

<4,9>
<4,9>

<4>

<4>
<4>

<4,9>
<4,9>

<4>
<4>

<4>

+VREF_CA

1

2

C134

C134

C167

2

C167

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

<4,9>
<4,9>

<4,9>
<4,9>

<26,6,9>
<26,6,9>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

DDRAB_SDQ[0..63]

DDRAB_SDM[0..7]

DDRAB_SMA[0..15]

DDRAB_SDQ[0..63]

DDRAB_SDM[0..7] <4,9>

DDRAB_SMA[0..15] <4,9>

+1.5V/+0.75VS OF DIMM1

+1.5V +0.75VS

C115 0.1U_0402_16V4ZC115 0.1U_0402_16V4Z

C116 0.1U_0402_16V4Z@C116 0.1U_0402_16V4Z

C114 0.1U_0402_16V4Z@C114 0.1U_0402_16V4Z

1

1

1

2

2

2

@

@

C120 0.1U_0402_16V4Z@C120 0.1U_0402_16V4Z

C121 0.1U_0402_16V4Z@C121 0.1U_0402_16V4Z

C117 0.1U_0402_16V4ZC117 0.1U_0402_16V4Z

C118 0.1U_0402_16V4ZC118 0.1U_0402_16V4Z

1

1

2

2

C122 0.1U_0402_16V4ZC122 0.1U_0402_16V4Z

C119 0.1U_0402_16V4Z@C119 0.1U_0402_16V4Z

1

1

1

2

2

2

@

@

@

VREF for DIMM1,2

+VREF_DQ

Compal Secret Data

Compal Secret Data

2012/04/22 2015/04/22

2012/04/22 2015/04/22

2012/04/22 2015/04/22

C

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

<4,9>

C123 0.1U_0402_16V4Z@C123 0.1U_0402_16V4Z

1

1

2

2

@

+1.5V +1.5V

1 2

1 2

R65

R65
20K_0402_1%

20K_0402_1%

R67

R67
20K_0402_1%

20K_0402_1%

C126 0.1U_0402_16V4ZC126 0.1U_0402_16V4Z

C127 4.7U_0603_6.3V6KC127 4.7U_0603_6.3V6K

1

1

2

2

+VREF_CA

D

R66

R66
1K_0402_1%

1K_0402_1%

1 2

R68

R68
1K_0402_1%

1K_0402_1%

1 2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDR3 SODIMM-I Socket

DDR3 SODIMM-I Socket

DDR3 SODIMM-I Socket

VAWGA/GB

VAWGA/GB

VAWGA/GB

8 48Thursday, March 28, 2013

8 48Thursday, March 28, 2013

8 48Thursday, March 28, 2013

E

1.0

1.0

1.0

A

B

C

D

E

+VREF_DQ

15mil

DDRAB_SDQ0

2

1

C177

C177

C143

2

1000P_0402_50V7K

1000P_0402_50V7K

DDRAB_SDQS1#
DDRAB_SDQS1

DDRAB_SDQS2#
DDRAB_SDQS2

DDRB_CKE0

DDRAB_SBS2#

DDRB_CLK0
DDRB_CLK0#

DDRAB_SBS0#

DDRAB_SWE#

DDRAB_SCAS#

DDRB_SCS1#

DDRAB_SDQS4#
DDRAB_SDQS4

DDRAB_SDQS6#
DDRAB_SDQS6

C143

+3VS

1

0.1U_0402_16V4Z

<4,8>
<4,8>

<4,8>
<4,8>

<4>

<4,8>

<4>
<4>

<4,8>

<4,8>
<4,8>

<4>

<4,8>
<4,8>

<4,8>
<4,8>

0.1U_0402_16V4Z

1 1

2 2

3 3

4 4

DDRAB_SDQ1

DDRAB_SDM0

DDRAB_SDQ2
DDRAB_SDQ3

DDRAB_SDQ8
DDRAB_SDQ9

DDRAB_SDQS1#
DDRAB_SDQS1

DDRAB_SDQ10
DDRAB_SDQ11

DDRAB_SDQ16
DDRAB_SDQ17

DDRAB_SDQS2#
DDRAB_SDQS2

DDRAB_SDQ18
DDRAB_SDQ19

DDRAB_SDQ24
DDRAB_SDQ25

DDRAB_SDM3

DDRAB_SDQ26
DDRAB_SDQ27

DDRB_CKE0

DDRAB_SBS2#

DDRAB_SMA12
DDRAB_SMA9

DDRAB_SMA8
DDRAB_SMA5

DDRAB_SMA3
DDRAB_SMA1

DDRB_CLK0
DDRB_CLK0#

DDRAB_SMA10
DDRAB_SBS0#

DDRAB_SWE#

DDRAB_SMA13
DDRB_SCS1#

DDRAB_SDQ32
DDRAB_SDQ33

DDRAB_SDQS4#
DDRAB_SDQS4

DDRAB_SDQ34
DDRAB_SDQ35

DDRAB_SDQ40
DDRAB_SDQ41

DDRAB_SDM5

DDRAB_SDQ42
DDRAB_SDQ43

DDRAB_SDQ48
DDRAB_SDQ49

DDRAB_SDQS6#
DDRAB_SDQS6

DDRAB_SDQ50
DDRAB_SDQ51

DDRAB_SDQ56
DDRAB_SDQ57

DDRAB_SDM7

DDRAB_SDQ58
DDRAB_SDQ59

R71 10K_0402_5%R71 10K_0402_5%

1 2

1 2

R72 10K_0402_5%R72 10K_0402_5%

JDIMM2

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4SN-7F

FOX_AS0A626-U4SN-7F

E@

E@

M

M

VSS3

DQS#0

DQS0

VSS6

VSS8
DQ12
DQ13

VSS10

DQ14
DQ15

DQ20
DQ21

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44

DQ45
VSS35
DQS#5

DQS5

VSS38

DQ46

DQ47
VSS40

DQ52

DQ53
VSS42

VSS43

DQ54

DQ55
VSS45

DQ60

DQ61
VSS47
DQS#7

DQS7

VSS50

DQ62

DQ63
VSS52

EVENT#

VTT2

DQ4
DQ5

DQ6
DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA
SCL

A15
A14

A11

S0#

+1.5V+1.5V

2
4

DDRAB_SDQ4

6

DDRAB_SDQ5

8
10

DDRAB_SDQS0#

12

DDRAB_SDQS0

14
16

DDRAB_SDQ6

18

DDRAB_SDQ7

20
22

DDRAB_SDQ12

24

DDRAB_SDQ13

26
28

DDRAB_SDM1

30

MEM_MAB_RST#

32
34

DDRAB_SDQ14

36

DDRAB_SDQ15

38
40

DDRAB_SDQ20

42

DDRAB_SDQ21

44
46

DDRAB_SDM2

48
50

DDRAB_SDQ22

52

DDRAB_SDQ23

54
56

DDRAB_SDQ28

58

DDRAB_SDQ29

60
62

DDRAB_SDQS3#

64

DDRAB_SDQS3

66
68

DDRAB_SDQ30

70

DDRAB_SDQ31

72

74
76
78
80
82
84
86

A7

88
90

A6

92

A4

94
96

A2

98

A0

100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

G2

DDRB_CKE1

DDRAB_SMA15
DDRAB_SMA14

DDRAB_SMA11
DDRAB_SMA7

DDRAB_SMA6
DDRAB_SMA4

DDRAB_SMA2
DDRAB_SMA0

DDRB_CLK1
DDRB_CLK1#

DDRAB_SBS1#
DDRAB_SRAS#

DDRB_SCS0#
DDRB_ODT0DDRAB_SCAS#

DDRB_ODT1

15mil

DDRAB_SDQ36
DDRAB_SDQ37

DDRAB_SDM4

DDRAB_SDQ38
DDRAB_SDQ39

DDRAB_SDQ44
DDRAB_SDQ45

DDRAB_SDQS5#
DDRAB_SDQS5

DDRAB_SDQ46
DDRAB_SDQ47

DDRAB_SDQ52
DDRAB_SDQ53

DDRAB_SDM6

DDRAB_SDQ54
DDRAB_SDQ55

DDRAB_SDQ60
DDRAB_SDQ61

DDRAB_SDQS7#
DDRAB_SDQS7

DDRAB_SDQ62
DDRAB_SDQ63

MEM_MAB_EVENT#

+0.75VS

DDRAB_SDQS0#
DDRAB_SDQS0

MEM_MAB_RST#

DDRAB_SDQS3#
DDRAB_SDQS3

DDRB_CKE1

DDRB_CLK1
DDRB_CLK1#

DDRAB_SBS1#
DDRAB_SRAS#

DDRB_SCS0#
DDRB_ODT0

DDRB_ODT1

1000P_0402_50V7K

1000P_0402_50V7K

DDRAB_SDQS5#
DDRAB_SDQS5

DDRAB_SDQS7#
DDRAB_SDQS7

MEM_MAB_EVENT# <4,8>

APU_SDATA0
APU_SCLK0

<4,8>
<4,8>

<4,8>

<4,8>
<4,8>

<4>

<4>
<4>

<4,8>
<4,8>

<4>
<4>

<4>

+VREF_CA

1

2

C139

C139

C174

C174

2

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

<4,8>
<4,8>

<4,8>
<4,8>

<26,6,8>
<26,6,8>

DDRAB_SDQ[0..63]

DDRAB_SDM[0..7]

DDRAB_SMA[0..15]

DDRAB_SDQ[0..63]

DDRAB_SDM[0..7] <4,8>

DDRAB_SMA[0..15] <4,8>

<4,8>

+1.5V/+0.75VS OF DIMM2

C132 0.1U_0402_16V4ZC132 0.1U_0402_16V4Z

C133 0.1U_0402_16V4Z@C133 0.1U_0402_16V4Z

C162 0.1U_0402_16V4ZC162 0.1U_0402_16V4Z

C155 0.1U_0402_16V4ZC155 0.1U_0402_16V4Z

C165 0.1U_0402_16V4ZC165 0.1U_0402_16V4Z

C168 0.1U_0402_16V4Z@C168 0.1U_0402_16V4Z

C169 0.1U_0402_16V4Z@C169 0.1U_0402_16V4Z

C170 0.1U_0402_16V4ZC170 0.1U_0402_16V4Z

C171 0.1U_0402_16V4ZC171 0.1U_0402_16V4Z

1

1

1

1

1

1

2

2

2

2

2

2

@

@

C172 0.1U_0402_16V4Z@C172 0.1U_0402_16V4Z

1

1

1

1

2

2

2

2

@

@

+1.5V+1.5V +0.75VS

C158 4.7U_0603_6.3V6KC158 4.7U_0603_6.3V6K

C175 0.1U_0402_16V4ZC175 0.1U_0402_16V4Z

1

1

2

2

1

+

+

C644

C644

2

220U_6.3V_M

220U_6.3V_M

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

DIMM_B H:4mm

<Address: 10>

A

B

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/04/22 2015/04/22

2012/04/22 2015/04/22

2012/04/22 2015/04/22

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DDR3 SODIMM-II Socket

DDR3 SODIMM-II Socket

DDR3 SODIMM-II Socket

VAWGA/GB

VAWGA/GB

VAWGA/GB

9 48Thursday, March 28, 2013

9 48Thursday, March 28, 2013

9 48Thursday, March 28, 2013

E

1.0

1.0

1.0

A

UV1A

UV1A

1 1

2 2

3 3

<5>

PCIE_ATX_C_GRX_P0

<5>

PCIE_ATX_C_GRX_N0

<5>

PCIE_ATX_C_GRX_P1

<5>

PCIE_ATX_C_GRX_N1

<5>

PCIE_ATX_C_GRX_P2

<5>

PCIE_ATX_C_GRX_N2

<5>

PCIE_ATX_C_GRX_P3

<5>

PCIE_ATX_C_GRX_N3

<5>

CLK_PEG_VGA

<5>

CLK_PEG_VGA#

CLK_PEG_VGA
CLK_PEG_VGA#

PX@

PX@

RV2 1K_0402_5%

RV2 1K_0402_5%

GPU_RST#

12

12

PX@

PX@

RV4

RV4
100K_0402_5%

100K_0402_5%

AA38

W36

W38

M37

M35

G36

G38

AB35
AA36

AH16

AA30

Y37

Y35

V37

V35
U36

U38
T37

T35
R36

R38
P37

P35
N36

N38

L36

L38
K37

K35

J36

J38

H37

H35

F37

F35
E37

PCIE_RX0P
PCIE_RX0N

PCIE_RX1P
PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX7P
PCIE_RX7N

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

CLOCK

CLOCK

PCIE_REFCLKP
PCIE_REFCLKN

TEST_PG

PERSTB

MARS@

MARS@

B

PART 1 0F 9

PART 1 0F 9

PCI EXPRESS INTERFACE

PCI EXPRESS INTERFACE

MARS-XT M2_FCBGA962

MARS-XT M2_FCBGA962

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

CALIBRATION

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

Y33

PCIE_GTX_ARX_P0

Y32

PCIE_GTX_ARX_N0

W33

PCIE_GTX_ARX_P1

W32

PCIE_GTX_ARX_N1

U33

PCIE_GTX_ARX_P2

U32

PCIE_GTX_ARX_N2

U30

PCIE_GTX_ARX_P3

U29

PCIE_GTX_ARX_N3

T33
T32

T30
T29

P33
P32

P30
P29

N33
N32

N30
N29

L33
L32

L30
L29

K33
K32

J33
J32

K30
K29

H33
H32

Y30

RV1 1.69K_0402_1%PX@RV1 1.69K_0402_1%PX@

Y29

RV3 1K_0402_1%PX@RV3 1K_0402_1%PX@

1 2

1 2

CV1 0.1U_0402_16V7KPX@CV1 0.1U_0402_16V7KPX@
CV2 0.1U_0402_16V7KPX@CV2 0.1U_0402_16V7KPX@

CV3 0.1U_0402_16V7KPX@CV3 0.1U_0402_16V7KPX@
CV4 0.1U_0402_16V7KPX@CV4 0.1U_0402_16V7KPX@

CV5 0.1U_0402_16V7KPX@CV5 0.1U_0402_16V7KPX@
CV6 0.1U_0402_16V7KPX@CV6 0.1U_0402_16V7KPX@

CV7 0.1U_0402_16V7KPX@CV7 0.1U_0402_16V7KPX@
CV8 0.1U_0402_16V7KPX@CV8 0.1U_0402_16V7KPX@

C

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

+0.95VGS

+0.95VGS

D

<6>

<24,26,6>

<5>
<5>

<5>
<5>

<5>
<5>

<5>
<5>

PXS_RST#

APU_PCIE_RST#

PCIE_GTX_C_ARX_P0
PCIE_GTX_C_ARX_N0

PCIE_GTX_C_ARX_P1
PCIE_GTX_C_ARX_N1

PCIE_GTX_C_ARX_P2
PCIE_GTX_C_ARX_N2

PCIE_GTX_C_ARX_P3
PCIE_GTX_C_ARX_N3

UV1

SUN@

UV1

SUN@

S IC 216-0841000-00 A0 SUN PRO M2 FCBGA 962P C38

S IC 216-0841000-00 A0 SUN PRO M2 FCBGA 962P C38

SA00006BA20

SA00006BA20

LVDS Interface

UV1D

UV1D

PART 7 0F 9

PART 7 0F 9

RSVD/VARY_BL

RSVD/DIGON

LVDS CONTROL

LVDS CONTROL

TXCBP_DPB3P
TXCBM_DPB3N

TX3P_DPB2P

TX3M_DPB2N

TX4P_DPB1P

TX4M_DPB1N

TX5P_DPB0P

TX5M_DPB0N

NC#AF35
NC#AG36

LVTMDP

LVTMDP

TXCAP_DPA3P
TXCAM_DPA3N

TX0P_DPA2P

TX0M_DPA2N

TX1P_DPA1P

TX1M_DPA1N

TX2P_DPA0P

TX2M_DPA0N

NC
NC

MARS-XT M2_FCBGA962

MARS-XT M2_FCBGA962

MARS@

MARS@

+3VGS

5

2

P

B

4

Y

1

A

G

PX@

PX@

UV2

UV2

3

MC74VHC1G08DFT2G SC70 5P

MC74VHC1G08DFT2G SC70 5P

AK27
AJ27

AK35
AL36

AJ38
AK37

AH35
AJ36

AG38
AH37

AF35
AG36

AP34
AR34

AW37
AU35

AR37
AU39

AP35
AR35

AN36
AP37

GPU_RST#

E

SUN NC

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/07/03 2013/07/03

2012/07/03 2013/07/03

2012/07/03 2013/07/03

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

ATI_MarsXTX_M2_PCIE/LVDS

ATI_MarsXTX_M2_PCIE/LVDS

ATI_MarsXTX_M2_PCIE/LVDS

VAWGA/GB

VAWGA/GB

VAWGA/GB

10 48Monday, April 01, 2013

10 48Monday, April 01, 2013

10 48Monday, April 01, 2013

E

1.0

1.0

1.0

A

UV1B

UV1B

MUTI GFX

MUTI GFX

+VREFG_GPU

PX_EN

TESTEN

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO

THERM_D+
THERM_D­GPIO_28_FDO

+TSVDD

1

CV32

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

PX@ CV32

PX@

AD29
AC29

AJ21
AK21

AW8

AW3

AW5

AW6

AR10

AW10

AU10
AP10
AV11
AT11
AR12

AW12

AU12
AP12

AJ23
AH23

AK26
AJ26

AH20
AH18
AN16

AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13

AG32
AG33

AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24

AC30

AK24

AH13

AL21

AD28

AM23
AN23
AK23
AL24
AM24

AF29
AG29

AK32

AL31

AJ32
AJ33

AR8
AU8
AP8

AR3
AR1
AU1
AU3

AP6

AU5
AR6

AU6
AT7
AV7
AN7
AV9
AT9

GENLK_CLK
GENLK_VSYNC

SWAPLOCKA
SWAPLOCKB

NC
NC
DBG_CNTL0
NC
NC
NC
DBG_DATA0
DBG_DATA1
DBG_DATA2
DBG_DATA3
DBG_DATA4
DBG_DATA5
DBG_DATA6
DBG_DATA7
DBG_DATA8
DBG_DATA9
DBG_DATA10
DBG_DATA11
DBG_DATA12
DBG_DATA13
DBG_DATA14
DBG_DATA15
DBG_DATA16
DBG_DATA17
DBG_DATA18
DBG_DATA19
DBG_DATA20
DBG_DATA21
DBG_DATA22
DBG_DATA23

SMBCLK

SMBus

SMBus

SMBDATA

SCL

I2C

I2C

SDA

GENERAL PURPOSE I/O

GENERAL PURPOSE I/O

GPIO_0
GPIO_1
GPIO_2

GPIO_5_AC_BATT
GPIO_6_TACH
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21
GPIO_22_ROMCSB
CLKREQB

GPIO_29
GPIO_30

GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6

CEC_1

HPD1

DBG_VREFG

BACO

BACO

PX_EN

DEBUG

DEBUG

TESTEN

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO

THERMAL

THERMAL

DPLUS
DMINUS

GPIO_28_FDO

TS_A

TSVDD
TSVSS

MARS@

MARS@

GENLK_CLK

T1T1

GENLK_VSYNC

T2T2

1 1

VGA_SMB_CK2
VGA_SMB_DA2

2 2

3 3

4 4

<39>

GPU_GPIO0

<28,35>
<39>

<39>

<39>

<6>

<39>
<39>

+1.8VGS

PX@

PX@

RV13 499_0402_1%

RV13 499_0402_1%

PX@

PX@

RV14 249_0402_1%

RV14 249_0402_1%

CV23

CV23

PX@

PX@

GPIO_28_FDO

H

L

<29>

REMOTE1+

<29>

REMOTE1-

TSVDD MarsCRB Design
120ohm 1 1

0.1u 1 1
1u 1 1
10u 1 1

VGA_CLKREQ#

12

12

12

0.1U_0402_16V7K

0.1U_0402_16V7K

MLPS

Disable

Enable

1 2

LV3 0_0402_5%@LV3 0_0402_5%@

ACIN

GPU_VID5

GPU_VID1

GPU_VID2

GPU_VID3
GPU_VID4

+VREFG_GPU

+3VGS

RV16 0_0402_5%@RV16 0_0402_5%@
RV17 0_0402_5%@RV17 0_0402_5%@

+3VGS

A

DV1

DV1
RB751V_SOD323 @

RB751V_SOD323 @

1 2
1 2

+TSVDD+1.8VGS

RV12 10K_0402_5%@ RV12 10K_0402_5%@

0.60 V level, Please
VREFG Divider ans
cap close to ASIC

T29T29

RV18 5.11K_0402_5%

RV18 5.11K_0402_5%

RV19 1K_0402_5%

RV19 1K_0402_5%

GPU_GPIO0

21

GPU_GPIO5
GPU_VID5

GPU_VID1

THM_ALERT#

1 2

GPU_VID2

VGA_CLKREQ#

GPU_VID3
GPU_VID4

1 2

@

@

1 2

PX@

PX@

T11T11

1 2

@

@

RV26 10K_0402_5%

RV26 10K_0402_5%

1 2

PX@

PX@

RV31 10K_0402_5%

RV31 10K_0402_5%

(1.8V@13mA TSVDD)

1

1

CV31

CV30

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

PX@ CV31

PX@

PX@ CV30

PX@

PART 2 0F 9

PART 2 0F 9

B

DPA

DPA

DPB

DPB

DPC

DPC

DPD

DPD

DAC1

DAC1

NC_SVI2
NC_SVI2
NC_SVI2

MLPS

MLPS

DDC/AUX

DDC/AUX

DDC1CLK

DDC1DATA

DDC2CLK

DDC2DATA

DDCVGACLK

DDCVGADATA

MARS-XT M2_FCBGA962

MARS-XT M2_FCBGA962

B

AVSSN

AVSSN

AVSSN

HSYNC
VSYNC

RSET

AVDD

AVSSQ

VDD1DI
VSS1DI

PS_0

PS_1

PS_2

PS_3

AUX1P
AUX1N

AUX2P
AUX2N

C

AU24

NC

AV23

NC

AT25

NC

AR24

NC

AU26

NC

AV25

NC

AT27

NC

AR26

NC

AR30

NC

AT29

NC

AV31

NC

AU30

NC

AR32

NC

AT31

NC

AT33

NC

AU32

NC

AU14

NC

AV13

NC

AT15

NC

AR14

NC

AU16

NC

AV15

NC

AT17

NC

AR16

NC

AU20

NC

AT19

NC

AT21

NC

AR20

NC

AU22

NC

AV21

NC

AT23

NC

AR22

NC

AD39

VGA_R

R

AD37

AE36

VGA_G

G

AD35

AF37

VGA_B

B

AE38

AC36

HSYNC

AC38

VSYNC

AB34

RV11 499_0402_1%PX@RV11 499_0402_1%PX@

AD34

+AVDD

AE34

AC33

+VDD1DI

AC34

V13

NC

U13

NC

AF33

NC

AF32

NC

AA29

NC

AG21

NC

AC32

NC

AC31
AD30
AD32

AM34

PS_0

AD31

PS_1

AG31

PS_2

AD33

PS_3

AM26

VGA_CLK

AN26

VGA_DAT

AM27
AL27

AM19
AL19

AN20
AM20

AL30

NC

AM30

NC

AL29

NC

AM29

NC

AN21

NC

AM21

NC

AK30

NC

AK29

NC

AJ30
AJ31

T24T24

T25T25

T26T26

T4T4
T6T6

1 2

(1.8V@70mA AVDD)

(1.8V@117mA VDD1DI)

T27T27
T28T28

GPU_GPIO5

THM_ALERT#

JTAG_TRSTB
JTAG_TDI
JTAG_TMS

JTAG_TCK

+VDD1DI

1

CV20

2

@ CV20

@

0.1U_0402_16V7K

0.1U_0402_16V7K

10K_0402_5%

10K_0402_5%

VGA_SMB_CK2

VGA_SMB_DA2

1U_0402_6.3V6K

1U_0402_6.3V6K

@

@

RV24

RV24

CV21

@ CV21

@

+AVDD

0.1U_0402_16V7K

0.1U_0402_16V7K

1

2

+3VGS

STRAPS

RV5 100K_0402_5%@RV5 100K_0402_5%@

RV6 2.2K_0402_5%@RV6 2.2K_0402_5%@

RV7 10K_0402_5%@RV7 10K_0402_5%@
RV8 10K_0402_5%@RV8 10K_0402_5%@
RV9 10K_0402_5%@RV9 10K_0402_5%@

RV10 10K_0402_5%@RV10 10K_0402_5%@

1

1

CV18

CV17

2

2

@ CV18

@

@ CV17

@

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CV22

2

@ CV22

@

10U_0603_6.3V6M

10U_0603_6.3V6M

12

12

@

@

RV25

RV25
10K_0402_5%

10K_0402_5%

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

C

+3VGS

12

12

+3VGS

12
12
12

12

AVDD MarsCRB Design
120ohm 1 1

0.1u 1 1
1u 1 1
10u 1 1

1 2

LV1 0_0402_5%@LV1 0_0402_5%@

1

CV19

2

@ CV19

@

10U_0603_6.3V6M

10U_0603_6.3V6M

1 2

LV2 0_0402_5%@LV2 0_0402_5%@

VDD1DI MarsCR B Design
120ohm 1 1

0.1u 1 1
1u 1 1
10u 1 1

+3VGS

2

61

5

QV3A

@QV3A

@

4

QV3B

@QV3B

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

@

+1.8VGS

+1.8VGS

EC_SMB_CK2

3

EC_SMB_DA2

2012/07/03 2013/07/03

2012/07/03 2013/07/03

2012/07/03 2013/07/03

<28,29,4>

<28,29,4>

Compal Secret Data

Compal Secret Data

Compal Secret Data

D

CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

STRAPS

TX_PWRS_ENB

TX_DEEMPH_EN

BIF_GEN3_EN_A

BIF_VGA DIS

ROMIDCFG[2:0]

BIOS_ROM_EN PS_2[3]

AUD[1]

AUD[0]

CEC_DIS PS_0[4]

RESERVED PS_1[3]

RESERVED PS_1[2]

RESERVED NA

RESERVED NA

AUD_PORT_CONN_PINSTRAP[2] PS_3[5]

AUD_PORT_CONN_PINSTRAP[1] PS_3[4]

AUD_PORT_CONN_PINSTRAP[0] PS_0[5]

PS_1[4] 0:50% Tx output swing

PS_1[5] 0:Tx de-emphasis disabled

PS_1[1]

PS_2[4]

PS_0[3..1]

NA

NA

DESCRIPTION OF DEFAULT SETTINGSMLPS

Transmitter Power Savings Enable

1:Full Tx output swing

PCIE Transmitter De-emphasis Enable

1:Tx de-emphasis enabled

PCIE Gen3 Enable
(NOTE:RESERVED for Thames/Seymour and should
be strapped to 0)

0:GEN3 not support at power-on
1:GEN3 supported at power-on

VGA control

0:VGA controller capacity enabled
1:VGA controller capacity disabled (for multi-GPU)

Serial ROM type or Memory Aperture Size Select

If PS_2[3]=0, defines memory aperture siz e
If PS_2[3]=1, defines ROM type
100 - 512Kbit M25P05A (ST)
101 - 1Mbit M25P10A (ST)
101 - 2Mbit M25P20 (ST)
101 - 4Mbit M25P40 (ST)
101 - 8Mbit M25P80 (ST)
100 - 512Kbit Pm25LV010 (Chingis)
101 - 1Mbit Pm25LV010 (Chingis)

Enable external BIOS ROM device

0:Disabled
1:Enabled

00 - No audio function
01 - Audio for DP only
10 - Audio for DP and HDMI if dongle is detected
11 - Audio for both DP and HDMI

HDMI must only be enabled on systems that are
legally entitled. It isthe responsibility of the system
designer to ensure that the system is entitled to
support this feature.

Reserved for future ASIC

NOTE:ALLOW FOR PULLUP PADS FOR THE
RESERVED STRAPS BUT DO NOT INSTALL
RESISTOR
IF THESE GPIOS ARE USEED, THEY MUST KEEP
LOW AND NOT CONFLICT DURING RESET

Reserved

Reserved

Reserved

Reserved (for Thames/Whistler/Seymour only)

STRAPS TO INDICATE THE NUMBER OF AUDIO
CAPABLE DISPLAY OUTPUTS

111 = 0 usable endpoints
110 = 1 usable endpoints
101 = 2 usable endpoints
100 = 3 usable endpoints
011 = 4 usable endpoints
010 = 5 usable endpoints
001 = 6 usable endpoints
000 = all endpoints are usable

MLPS Strap

CapacitorBits[5:4]

Deciphered Date

Deciphered Date

Deciphered Date

D

PS_0[5:1]

PS_1[5:1]

PS_2[5:1]

PS_3[5:1]

PS_0
PS_1
PS_2
PS_3

@

@

CV26

CV26

0.01U_0402_25V7K

0.01U_0402_25V7K

Bits[3:1]

0 0 1

1 1

0 1 0

0 1

0 0 0

0 0

1 1

X X X

@

PX@

PX@

1

CV27

CV27

2

@

PX@

PX@

CV29

CV29

1

1

CV28

CV28

2

2

0.01U_0402_25V7K

0.01U_0402_25V7K

0.082U_0402_16V7K

0.082U_0402_16V7K

1

2

0.68U_0402_10V6K

0.68U_0402_10V6K

R_pu R_pd

NC

8.45K 2K

82 nF

4.53K

680 nF

NC

NC

X

12

RV20

X76@ RV20

X76@

8.45K_0402_1%

8.45K_0402_1%

4.75K_0402_1%

4.75K_0402_1%

RV27

X76@ RV27

X76@

8.45K_0402_1%

8.45K_0402_1%

12

4.75K_0402_1%

4.75K_0402_1%

PX@RV28

PX@

Place CLOSE VGA CHIP

Title

Title

Title

ATI_MarsXTX_M2_Main_MSIC

ATI_MarsXTX_M2_Main_MSIC

ATI_MarsXTX_M2_Main_MSIC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

E

RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE

2K

4.75K

Mapping to VRAM type please refer to page 45

X

12

RV21

@RV21

@

12

RV28

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PX@RV22

PX@

4.53K_0402_1%

4.53K_0402_1%

PX@RV29

PX@

2K_0402_1%

2K_0402_1%

VAWGA/GB

VAWGA/GB

VAWGA/GB

E

RV22

RV29

12

8.45K_0402_1%

8.45K_0402_1%

12

PX@RV23

PX@

PX@RV30

PX@

2K_0402_1%

2K_0402_1%

Default Setting

+1.8VGS

12

RV23

12

RV30

11 48Thursday, March 28, 2013

11 48Thursday, March 28, 2013

11 48Thursday, March 28, 2013

1

0

0

0

001
256MB

0

NC

1

0
1
NA
NA

111

1.0

1.0

1.0

A

MPLL_PVDD MarsCRB Design

1 1

2 2

220ohm 1 1

0.1u 1 1
1u 1 1
10u 1 1

SPLL_PVDD MarsCRB Design
120ohm 1 1

0.1u 1 1
1u 1 1
10u 1 1

SPLL_VDDC MarsCRB Design
120ohm 1 1

0.1u 1 1
1u 1 1
10u 1 1

+1.8VGS

+1.8VGS

+0.95VGS

B

@

@

LV4

LV4

1 2

0_0603_5%

0_0603_5%

1 2

@

@

LV5

LV5
0_0402_5%

0_0402_5%

1 2

@

@

LV6

LV6
0_0402_5%

0_0402_5%

+MPV18

(MPLL_PVDD:1.8V@130mA )

1

1

CV34

CV33

2

2

1U_0402_6.3V6K

PX@ CV34

1U_0402_6.3V6K

PX@

PX@ CV33

PX@

0.1U_0402_16V7K

0.1U_0402_16V7K

10U_0603_6.3V6M

10U_0603_6.3V6M

+SPV18

(SPLL_PVDD:1.8V@75mA )

1

1

CV38

CV39

2

2

PX@ CV39

PX@

PX@ CV38

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

10U_0603_6.3V6M

10U_0603_6.3V6M

+SPLL_VDDC

(SPLL_VDDC:0.95V@100mA )

1

1

CV43

CV44

2

2

PX@ CV44

PX@

PX@ CV43

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

10U_0603_6.3V6M

10U_0603_6.3V6M

C

UV1C

UV1C

PART 9 0F 9

PART 9 0F 9

AV33

XTALIN

1

CV35

2

PX@ CV35

PX@

AM10

AN9

AN10

AF30
AF31

H7
H8

MPLL_PVDD
MPLL_PVDD

SPLL_PVDD

SPLL_VDDC

SPLL_PVSS

NC_XTAL_PVDD
NC_XTAL_PVSS

MARS@

MARS@

PLLS/XTAL

PLLS/XTAL

MARS-XT M2_FCBGA962

MARS-XT M2_FCBGA962

+MPV18

+SPV18

1

CV40

2

PX@ CV40

PX@

1

CV45

2

PX@ CV45

PX@

+SPLL_VDDC

XTALOUT

XO_IN

XO_IN2

CLKTESTA
CLKTESTB

AU34

AW34

AW35

AK10
AL10

XTALIN

XTALOUT

D

12

@

@

CV41

CV41

0.1U_0402_16V7K

0.1U_0402_16V7K

12

@

@

RV33

RV33

51.1_0402_1%

51.1_0402_1%

12

@

@

CV42

CV42

0.1U_0402_16V7K

0.1U_0402_16V7K

12

@

@

RV34

RV34

51.1_0402_1%

51.1_0402_1%

CV36

PX@CV36

PX@

10P_0402_50V8J

10P_0402_50V8J

1 2

RV32 1M_0402_5%

RV32 1M_0402_5%

PX@

PX@

YV1

YV1

4

NC

OSC

1

XTALIN

1

2

OSC

PX@

PX@

NC

27MHZ 10PF +-20PPM X3G027000DA1H

27MHZ 10PF +-20PPM X3G027000DA1H

E

3

XTALOUT

2

1

CV37

PX@CV37

PX@

10P_0402_50V8J

10P_0402_50V8J

2

+3VS TO +3VGS

+5VALW

RV37

PX@RV37

PX@

20K_0402_5%

3 3

<28,39,6>

PXS_PWREN

20K_0402_5%

PXS_PWREN

2

G

G

+1.5V TO +1.5VGS

PX@

PX@

CV48

CV48

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

B+

+3VALW

12

PX@

PX@

R286

R286

100K_0402_5%

PXS_PWREN

R276

PX@ R 276

PX@

100K_0402_5%

100K_0402_5%

100K_0402_5%

5

12

A

34

PX@

PX@

QV157B

QV157B
DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

4 4

+3VS +3VGS

QV8

QV8
LP2301ALT1G_SOT23-3

LP2301ALT1G_SOT23-3

PX@

PX@

13

D

D

PX@

PX@

QV6

QV6
2N7002H_SOT23-3

2N7002H_SOT23-3

S

S

3 1

2

RV38

PX@RV38

PX@

20K_0402_5%

20K_0402_5%

1

2

AO4430: Rdson: 5.5mohm @ VGS=10V

+1.5V +1.5VGS

360mil(9A) 360mil(9A)

1

2

RV41 240K_0402_5%

RV41 240K_0402_5%

PX@

PX@

PXS_PWREN#

12

6

PX@

PX@

2

QV157A

QV157A
DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

1

8
7
6
5

PX@

PX@

CV52

CV52

0.1U_0402_16V4Z

0.1U_0402_16V4Z

UV4

UV4

AO4304L_SO8

AO4304L_SO8

4

PX@

PX@

RV42
0_0402_5%

0_0402_5%

1 2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

PX@

PX@

1
2
3

@RV42

@

1

CV46

CV46

@

@

2

PXS_PWREN#

1

PX@

PX@

CV53

CV53

0.1U_0402_25V6

0.1U_0402_25V6

2

B

1U_0603_10V6K

1U_0603_10V6K

1

CV47

CV47

2

D

D

S

S

PX@

PX@

1

CV49

CV49

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

2

12

@

@

RV36

RV36
470_0603_5%

470_0603_5%

13

2

G

G

@

@

QV7

QV7
2N7002H_SOT23-3

2N7002H_SOT23-3

@

@

1

CV50

CV50

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

2N7002H_SOT23-3@G

2N7002H_SOT23-3

1 2

13

D

D

QV1

QV1

@

S

S

+1.8VALW TO +1.8VGS
+0.95VALW TO +0.95VGS
Load switch

+1.8VALW

C29

C29

1

@

@

1U_0402_6.3V6K

1U_0402_6.3V6K

2

RV39

@RV39

@

470_0603_5%

470_0603_5%

2

PXS_PWREN#

G

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/07/03 2013/07/03

2012/07/03 2013/07/03

2012/07/03 2013/07/03

VIN 1.8V and 0. 95V (VBIAS=5V) ,IMAX(per chann el)=6A,Rds=18m ohm

U1895V

PXS_PWREN

VL

PXS_PWREN

+0.95VALW

1

C30

@ C30

@

1U_0402_6.3V6K

1U_0402_6.3V6K

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

U1895V

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

TPS22966DPUR_SON14_2X3

TPS22966DPUR_SON14_2X3

PX@

PX@

D

VOUT1
VOUT1

GND

VOUT2
VOUT2

GPAD

14
13

12

CT1

11

10

CT2

9
8

15

+1.8VGS

J18VG

J18VG

J@

J@

C282200P_0402_50V7K

C282200P_0402_50V7K

C272200P_0402_50V7K

C272200P_0402_50V7K

1 2

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m

+0.95VGS

J95VG

J95VG

J@

J@

PAD-OPEN 4x4m

PAD-OPEN 4x4m

VAWGA/GB

VAWGA/GB

VAWGA/GB

E

2

@ C31

@

1

C31

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

@ C32

@

1

C32

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12 48Thursday, March 28, 2013

12 48Thursday, March 28, 2013

12 48Thursday, March 28, 2013

+1.8VGS_LS

1 2

PX@

PX@

1 2

PX@

PX@

+0.95VGS_LS

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

ATI_MarsXTX_M2_BACO POWER

ATI_MarsXTX_M2_BACO POWER

ATI_MarsXTX_M2_BACO POWER

1.0

1.0

1.0

A

UV1G

UV1G

PART 6 0F 9

PART 6 0F 9

AB39

GND

E39

GND

F34

GND

F39

GND

G33

GND

G34

GND

H31

GND

H34

GND

H39

GND

J31

M34
M39

W31
W34

M17
M22
M24

GND

J34

GND

K31

GND

K34

GND

K39

GND

L31

GND

L34

GND
GND
GND

N31

GND

N34

GND

P31

GND

P34

GND

P39

GND

R34

GND

T31

GND

T34

GND

T39

GND

U31

GND

U34

GND

V34

GND

V39

GND
GND
GND

Y34

GND

Y39

GND

GND

F15

GND

F17

GND

F19

GND

F21

GND

F23

GND

F25

GND

F27

GND

F29

GND

F31

GND

F33

GND

F7

GND

F9

GND

G2

GND

G6

GND

H9

GND

J2

GND

J27

GND

J6

GND

J8

GND

K14

GND

K7

GND

L11

GND

L17

GND

L2

GND

L22

GND

L24

GND

L6

GND
GND
GND
GND

N16

GND

N18

GND

N2

GND

N21

GND

N23

GND

N26

GND

N6

GND

R15

GND

R17

GND

R2

GND

R20

GND

R22

GND

R24

GND

R27

GND

R6

GND

T11

GND

T13

GND

T16

GND

T18

GND

T21

GND

T23

GND

T26

GND

U15

GND

U17

GND

U2

GND

U20

GND

U22

GND

U24

GND

U27

GND

U6

GND

V11

GND

V16

GND

V18

GND

V21

GND

V23

GND

V26

GND

W2

GND

W6

GND

Y15

GND

Y17

GND

Y20

GND

Y22

GND

Y24

GND

Y27

GND

MARS@

MARS@

GND

VSS_MECH
VSS_MECH
VSS_MECH

MARS-XT M2_FCBGA962

MARS-XT M2_FCBGA962

1 1

2 2

3 3

4 4

A

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

B

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20

AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20

AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

AG22

NC

A39

MECH#1

AW1

MECH#2

AW39

MECH#3

B

DP_VDDR MarsCRB Design

0.1u 1 1
1u 1 1
10u 1 1

+1.8VGS

1 2

RV43 0_0402_5%@RV43 0_0402_5%@

TV12 PADTV12 PAD
TV13 PADTV13 PAD
TV14 PADTV14 PAD

+DP_VDDR

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

(DP_VDDR:1.8V@237mA/link )

+DP_VDDR

1

1

CV57

2

PX@ CV57

PX@

10U_0603_6.3V6M

10U_0603_6.3V6M

RV44 150_0402_1%PX@RV44 150_0402_1%PX@

C

1

CV58

CV59

2

2

PX@ CV58

PX@

PX@ CV59

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

12

D

UV1F

UV1F

AN24

NC

AP24

NC

AP25

NC

AP26

NC

AU28

NC

AV29

NC

AP20

NC

AP21

NC

AP22

NC

AP23

NC

AU18

NC

AV19

NC

AH34

DP_VDDR

AJ34

DP_VDDR

AF34

DP_VDDR

AG34

DP_VDDR

AM37

DP_VDDR

AL38

DP_VDDR

AM32

DP_VDDR

AW28

NC

AW18

NC

AM39

DP_CALR

MARS@

MARS@

2012/07/03 2013/07/03

2012/07/03 2013/07/03

2012/07/03 2013/07/03

PART 8 0F 9

PART 8 0F 9

DP_VDDR DP_VDDC

DP_VDDR DP_VDDC

DP GND

DP GND

CALIBRATION

CALIBRATION

MARS-XT M2_FCBGA962

MARS-XT M2_FCBGA962

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC

DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR

D

NC
NC
NC
NC

(DP_VDDC:0.95V@280mA/link )

AP31
AP32
AN33
AP33
AL33
AM33
AK33
AK34
AN31

AP13
AT13
AP14
AP15

AN27
AP27
AP28
AW24
AW26
AN29
AP29
AP30
AW30
AW32
AN17
AP16
AP17
AW14
AW16
AN19
AP18
AP19
AW20
AW22
AN34
AP39
AR39
AU37
AF39
AH39
AK39
AL34
AV27
AR28
AV17
AR18
AN38
AM35
AN32

CV54

1

2

PX@ C V54

PX@

0.1U_0402_16V7K

0.1U_0402_16V7K

E

+0.95VGS

1

1

CV55

CV56

CV56

2

2

PX@ CV55

PX@

PX@

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

DP_VDDC MarsCRB Design

0.1u 1 1
1u 1 1
10u 1 1

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

ATI_MarsXTX_M2_PWR_GND

ATI_MarsXTX_M2_PWR_GND

ATI_MarsXTX_M2_PWR_GND

VAWGA/GB

VAWGA/GB

VAWGA/GB

13 48Thursday, March 28, 2013

13 48Thursday, March 28, 2013

13 48Thursday, March 28, 2013

E

1.0

1.0

1.0

A

B

C

D

E

UV1E

AD11

AG10

AG26
AG27

AG23
AG24

AD12

AG11
AG13
AG15

AG28

AH29

AF26
AF27

AF23
AF24

AF11
AF12
AF13

AF15

AF28

AC7

AF7

AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10

J7

J9
K11
K13

K8
L12
L16
L21
L23
L26

L7
M11
N11

P7
R11
U11

U7
Y11

Y7

UV1E

MEM I/O

MEM I/O

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

LEVEL

LEVEL

TRANSLATION

TRANSLATION

VDD_CT
VDD_CT
VDD_CT
VDD_CT

I/O

I/O

VDDR3
VDDR3
VDDR3
VDDR3

DVP

DVP

VDDR4
VDDR4
VDDR4
VDDR4

VDDR4
VDDR4
VDDR4
VDDR4

VOLTAGE

VOLTAGE
SENESE

SENESE

FB_VDDC

FB_VDDCI

FB_GND

MARS@

MARS@

PART 5 0F 9

PART 5 0F 9

NC_BIF_VDDC
NC_BIF_VDDC

PCIE_PVDD

PCIE

PCIE

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

BIF_VDDC

BACO

BACO

BIF_VDDC

CORE

CORE

CORE I/O

CORE I/O

ISOLATED

ISOLATED

MARS-XT M2_FCBGA962

MARS-XT M2_FCBGA962

NC
NC
NC
NC
NC
NC

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI

AA31
AA32
AA33
AA34
W30
Y31
V28
W29
AB37

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

N27
T27

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18

AH22
AH27
AH28
M26
N24
R18
R21
R23
R26
T17
T20
T22
T24
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

+1.5VGS

1

CV66

CV66

+

+

@

@

1 1

VDDR1 MarsCRB Design

0.01u 5 0

0.1u 5 5
1u 0 5

2.2u 5 0
10u 3 5
220u 0 1

VDD_CT MarsCR B Design
120ohm 1 1

0.1u 1 1
1u 1 3
10u 1 1

VDDR3 MarsCRB Design
120ohm 1 0

2 2

0.1u 1 0
1u 2 3
10u 0 1

VDDR4 MarsCRB Design
220ohm 1 1

0.1u 1 1
1u 1 1
10u 1 0

3 3

2

220U_B2_2.5VM_R35

220U_B2_2.5VM_R35

1

1

1

CV67

CV60

2

2

@ CV67

@

@ CV60

@

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CV68

CV70

CV69

2

2

2

@ CV68

@

PX@ CV70

PX@

PX@ CV69

PX@

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

+1.8VGS +VDDC_CT

1 2

@

@

LV8

LV8
0_0402_5%

0_0402_5%

+3VGS

1 2

LV9

LV9
0_0402_5%

0_0402_5%

+1.8VGS

@

@

1 2

0_0603_5%

0_0603_5%

For GDDR5, MVDDQ = 1.5V

(VDDR1:1.5V@3A,GDDR5:1125MHz )

1

1

1

CV71

2

PX@ CV71

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

@

@

LV10

LV10

CV74

CV73

CV171

2

2

PX@ CV171

PX@

PX@ CV74

PX@

PX@ CV73

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

+VDDR3

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CV75

2

2

PX@ CV75

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

(VDD_CT:1.8V@13mA )

1

CV89

2

PX@ CV89

PX@

10U_0603_6.3V6M

10U_0603_6.3V6M

(VDDR3:3.3V@25mA)

1

1

CV92

CV93

2

2

@ CV93

@

PX@ CV92

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

+VDDR4

( VDDR4:1.8V@300mA)

+1.5VGS

1

CV76

2

PX@ CV76

PX@

0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CV94

2

PX@ CV94

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

1

1

CV78

CV61

CV77

CV79

2

2

2

2

PX@ CV78

PX@

PX@ CV61

PX@

PX@ CV77

PX@

PX@ CV79

PX@

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

1

1

CV90

CV91

2

2

@ CV90

@

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CV96

2

PX@ CV96

PX@

+VDDC_CT

PX@ CV91

PX@

0.1U_0402_16V7K

0.1U_0402_16V7K

+VDDR3

1

CV95

2

PX@ CV95

PX@

+VDDR4

1

CV97

2

PX@ CV97

PX@

0.1U_0402_16V7K

0.1U_0402_16V7K

Route as differential pair

<39>

VCCSENSE_VGA

<39>

VSSSENSE_VGA

TV15TV15

(PCIE_VDDR:1.8V@100mA )

+PCIE_VDDR

1

1

CV63

CV62

2

2

PX@ CV62

PX@

PX@ CV63

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

(PCIE_VDDC:0.95V@2.5A_GEN3.0 )

+0.95VGS

1

1

CV80

CV81

2

2

PX@ CV80

PX@

PX@ CV81

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

(BIF_VDDC:0.95V@1.4A)

+0.95VGS

1

1

CV87

CV86

2

2

PX@ CV87

PX@

PX@ CV86

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

(VDDCI:0.9~1.15V@8.8A)

1

CV64

2

PX@ CV64

PX@

1

CV82

2

PX@ CV82

PX@

PX@

PX@

10U_0603_6.3V6M

10U_0603_6.3V6M

+PCIE_VDDR

1

CV65

2

PX@ CV65

PX@

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

1

CV84

CV83

CV85

2

2

2

@ CV84

@

PX@ CV83

PX@

PX@ CV85

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CV88

CV88

2

LV7

LV7

0_0603_5%

0_0603_5%

+VGA_CORE

@

@

12

+0.95VGS

+0.95VGS

+1.8VGS

+VGA_CORE

PCIE_VDDR Mar sCRB Design

0.1u 0 2
1u 2 3
10u 1 1

PCIE_VDDC Mar sCRB Design
1u 7 5
10u 2 1

VGA_CORE Cap in power side sheet

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2012/07/03 2013/07/03

2012/07/03 2013/07/03

2012/07/03 2013/07/03

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

ATI_MarsXTX_M2_Power

ATI_MarsXTX_M2_Power

ATI_MarsXTX_M2_Power

VAWGA/GB

VAWGA/GB

VAWGA/GB

E

14 48Thursday, March 28, 2013

14 48Thursday, March 28, 2013

14 48Thursday, March 28, 2013

of

1.0

1.0

1.0

A

UV1H

UV1H

PART 3 0F 9

PART 3 0F 9

GDDR5/DDR3

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31

MVREFDA
MVREFSA

NC
NC
NC

MEM_CALRP0

NC
NC

MARS@

MARS@

GDDR5/DDR3

MEMORY INTERFACE A

MEMORY INTERFACE A

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8

MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12

MAA1_5/MAA_BA2
MAA1_6/MAA_BA0
MAA1_7/MAA_BA1

WCKA0_0/DQMA_0

WCKA0B_0/DQMA_1

WCKA0_1/DQMA_2

WCKA0B_1/DQMA_3

WCKA1_0/DQMA_4

WCKA1B_0/DQMA_5

WCKA1_1/DQMA_6

WCKA1B_1/DQMA_7

EDCA0_0/QSA_0
EDCA0_1/QSA_1
EDCA0_2/QSA_2
EDCA0_3/QSA_3
EDCA1_0/QSA_4
EDCA1_1/QSA_5
EDCA1_2/QSA_6
EDCA1_3/QSA_7

DDBIA0_0/QSA_0B
DDBIA0_1/QSA_1B
DDBIA0_2/QSA_2B
DDBIA0_3/QSA_3B
DDBIA1_0/QSA_4B
DDBIA1_1/QSA_5B
DDBIA1_2/QSA_6B
DDBIA1_3/QSA_7B

ADBIA0/ODTA0

ADBIA1/ODTA1

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B
RASA1B

CASA0B
CASA1B

CSA0B_0
CSA0B_1

CSA1B_0
CSA1B_1

CKEA0
CKEA1

WEA0B
WEA1B

MAA0_8/MAA_13
MAA1_8/MAA_14
MAA0_9/MAA_15

MAA1_9/RSVD

MARS-XT M2_FCBGA962

MARS-XT M2_FCBGA962

G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

A32
C32
D23
E22
C14
A14
E10
D9

C34
D29
D25
E20
E16
E12
J10
D7

A34
E30
E26
C20
C16
C12
J11
F8

J21
G19

H27
G27

J14
H14

K23
K19

K20
K17

K24
K27

M13
K16

K21
J20

K26
L15

H23
J19
M21
M20

C37

MDA0

C35

MDA1

A35

MDA2

E34

MDA3

G32

MDA4

D33

MDA5

F32

MDA6

E32

MDA7

D31

MDA8

F30

MDA9

C30

MDA10

A30

MDA11

F28

MDA12

C28

+VDD_MEM15_REFDA
+VDD_MEM15_REFSA

1 2

PX@

PX@

MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

AG12

AH12

A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13

J13
H11
G10

G8
K9

K10

G9
A8
C8
E8
A6
C6
E6
A5

L18

L20

L27
N12

M27

M12

1 1

2 2

RV47 120_0402_1%

RV47 120_0402_1%

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1

ODTA0
ODTA1

CLKA0
CLKA0#

CLKA1
CLKA1#

RASA0#
RASA1#

CASA0#
CASA1#

CSA0#_0

CSA1#_0

CKEA0
CKEA1

WEA0#
WEA1#

MAA13
MAA14

DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

B

ODTA0
ODTA1

CLKA0
CLKA0#

CLKA1
CLKA1#

RASA0#
RASA1#

CASA0#
CASA1#

CSA0#_0

CSA1#_0

CKEA0
CKEA1

WEA0#
WEA1#

<16>
<17>

<16>
<16>

<17>
<17>

<16>
<17>

<16>
<17>

<16>

<17>

<16>
<17>

<16>
<17>

MDA[0..63]

MAA[0..15]

A_BA[0..2]

DQMA[0..7]

QSA[0..7]

QSA#[0..7]

MDB[0..63]

MAB[0..15]

B_BA[0..2]

DQMB[0..7]

QSB[0..7]

QSB#[0..7]

C

MDA[0..63]

MAA[0..15]

A_BA[0..2]

DQMA[0..7]

QSA[0..7]

QSA#[0..7]

MDB[0..63]

MAB[0..15]

B_BA[0..2]

DQMB[0..7]

QSB[0..7]

QSB#[0..7]

<16,17>

<16,17>

<16,17>

<16,17>

<16,17>

<16,17>

<18,19>

<18,19>

<18,19>

<18,19>

<18,19>

<18,19>

+VDD_MEM15_REFDB
+VDD_MEM15_REFSB

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

D

UV1I

UV1I

PART 4 0F 9

PART 4 0F 9

GDDR5/DDR3

DQB0_0
DQB0_1
DQB0_2
DQB0_3
DQB0_4
DQB0_5
DQB0_6
DQB0_7
DQB0_8
DQB0_9
DQB0_10
DQB0_11
DQB0_12
DQB0_13
DQB0_14
DQB0_15
DQB0_16
DQB0_17
DQB0_18
DQB0_19
DQB0_20
DQB0_21
DQB0_22
DQB0_23
DQB0_24
DQB0_25
DQB0_26
DQB0_27
DQB0_28
DQB0_29
DQB0_30
DQB0_31
DQB1_0
DQB1_1
DQB1_2
DQB1_3
DQB1_4
DQB1_5
DQB1_6
DQB1_7
DQB1_8
DQB1_9
DQB1_10
DQB1_11
DQB1_12
DQB1_13
DQB1_14
DQB1_15
DQB1_16
DQB1_17
DQB1_18
DQB1_19
DQB1_20
DQB1_21
DQB1_22
DQB1_23
DQB1_24
DQB1_25
DQB1_26
DQB1_27
DQB1_28
DQB1_29
DQB1_30
DQB1_31

MVREFDB
MVREFSB

MARS@

MARS@

GDDR5/DDR3

MEMORY INTERFACE B

MEMORY INTERFACE B

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8

MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12

MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

WCKB0_0/DQMB_0

WCKB0B_0/DQMB_1

WCKB0_1/DQMB_2

WCKB0B_1/DQMB_3

WCKB1_0/DQMB_4

WCKB1B_0/DQMB_5

WCKB1_1/DQMB_6

WCKB1B_1/DQMB_7

EDCB0_0/QSB_0
EDCB0_1/QSB_1
EDCB0_2/QSB_2
EDCB0_3/QSB_3
EDCB1_0/QSB_4
EDCB1_1/QSB_5
EDCB1_2/QSB_6
EDCB1_3/QSB_7

DDBIB0_0/QSB_0B
DDBIB0_1/QSB_1B
DDBIB0_2/QSB_2B
DDBIB0_3/QSB_3B
DDBIB1_0/QSB_4B
DDBIB1_1/QSB_5B
DDBIB1_2/QSB_6B
DDBIB1_3/QSB_7B

ADBIB0/ODTB0
ADBIB1/ODTB1

CLKB0

CLKB0B

CLKB1

CLKB1B

RASB0B
RASB1B

CASB0B
CASB1B

CSB0B_0
CSB0B_1

CSB1B_0
CSB1B_1

CKEB0
CKEB1

WEB0B
WEB1B

MAB0_8/MAB_13
MAB1_8/MAB_14
MAB0_9/MAB_15

MAB1_9/RSVD

DRAM_RST

MARS-XT M2_FCBGA962

MARS-XT M2_FCBGA962

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

H3
H1
T3
T5
AE4
AF5
AK6
AK5

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

T7
W7

L9
L8

AD8
AD7

T10
Y10

W10
AA10

P10
L10

AD10
AC10

U10
AA11

N10
AB11

T8
W8
U12
V12

AH11

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1

DQMB0
DQMB1
DQMB2
DQMB3
DQMB4
DQMB5
DQMB6
DQMB7

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

ODTB0
ODTB1

CLKB0
CLKB0#

CLKB1
CLKB1#

RASB0#
RASB1#

CASB0#
CASB1#

CSB0#_0

CSB1#_0

CKEB0
CKEB1

WEB0#
WEB1#

MAB13
MAB14MAA15
MAB15

DRAM_RST#_R

AA12

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3

Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6

AJ4
AK3
AF8
AF9
AG8
AG7
AK9

AL7
AM8
AM7
AK1

AL4
AM6
AM1

AN4

AP3

AP1

AP5

Y12

E

ODTB0
ODTB1

CLKB0
CLKB0#

CLKB1
CLKB1#

RASB0#
RASB1#

CASB0#
CASB1#

CSB0#_0

CSB1#_0

CKEB0
CKEB1

WEB0#
WEB1#

<18>
<19>

<18>
<18>

<19>
<19>

<18>
<19>

<18>
<19>

<18>

<19>

<18>
<19>

<18>
<19>

3 3

Ball to RV57 < 1"

+1.5VGS +1.5VGS

12

RV49

RV49

40.2_0402_1%

40.2_0402_1%

PX@

PX@

+VDD_MEM15_REFDA DRAM_RST#_R

12

RV55

RV55

100_0402_1%

100_0402_1%

PX@

PX@

4 4

A

1

CV98

CV98
1U_0402_6.3V6K

1U_0402_6.3V6K

2

PX@

PX@

RV50

RV50

40.2_0402_1%

40.2_0402_1%

RV56

RV56

100_0402_1%

100_0402_1%

12

PX@

PX@

+VDD_MEM15_REFSA +VDD_MEM15_REFSB+VDD_MEM15_REFDB

12

1

CV99

CV99
1U_0402_6.3V6K

PX@

PX@

1U_0402_6.3V6K

2

PX@

PX@

<16,17,18,19>

B

CV100 to RV57 < 200 mil
CV100 to RV53 < 1"

1 2

PX@

DRAM_RST#

DRAM_RST# is a daisy-chain net that connects to all VRAM

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
Capacitors and Resistor values are an example only. The Series R and
|| Cap values will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board to pass Reset
Signal Spec.
Place all these components very close to GPU (Within
25mm) and keep all component close to each Other (within
5mm) except Rser2

PX@

RV53 51.1_0402_1%

RV53 51.1_0402_1%

+1.5VGS

12

RV48

RV48

4.7K_0402_5%

4.7K_0402_5%

@

@

1 2

PX@

PX@

RV54 10_0402_5%

RV54 10_0402_5%

12

CV100

CV100

120P_0402_50V9

120P_0402_50V9

PX@

PX@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

RV57

RV57

4.99K_0402_1%

4.99K_0402_1%

PX@

PX@

1 2

Compal Secret Data

Compal Secret Data

2012/07/03 2013/07/03

2012/07/03 2013/07/03

2012/07/03 2013/07/03

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

+1.5VGS +1.5VGS

RV51

RV51

40.2_0402_1%

40.2_0402_1%

PX@

PX@

RV58

RV58

100_0402_1%

100_0402_1%

PX@

PX@

12

12

1

CV101

CV101
1U_0402_6.3V6K

1U_0402_6.3V6K

2

PX@

PX@

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

RV52

RV52

40.2_0402_1%

40.2_0402_1%

PX@

PX@

12

RV59

RV59

100_0402_1%

100_0402_1%

PX@

PX@

1

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

ATI_MarsXTX_M2_MEM IF

ATI_MarsXTX_M2_MEM IF

ATI_MarsXTX_M2_MEM IF

VAWGA/GB

VAWGA/GB

VAWGA/GB

E

CV102

CV102
1U_0402_6.3V6K

1U_0402_6.3V6K

PX@

PX@

1.0

1.0

15 48Thursday, March 28, 2013

15 48Thursday, March 28, 2013

15 48Thursday, March 28, 2013

1.0