Compal LA-9911P VAWGA, G505, LA-9911P VAWGB Schematic

A

1 1

B

C

D

E

Compal Confidential

VAWGA/B Schematics Document

2 2

AMD "Kabini" Platform

AMD 25W APU With Jaguar Core and Integrated Yangtze FCH + ATI Sun

LA-9911P REV: 1.0

3 3

4 4

A

B

2013-04-01

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/04/22 2015/04/22

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

COVER PAGE

VAWGA/GB

1 48Monday, April 01, 2013

E

1.0

A

Compal Confidential

Model Name : VAWGA/B

B

C

D

E

1 1

VRAM 1G/2G 2

56M16 x 4 (2G)

128M16 x 4 (1G)

P.16~19

DDR3

AMD Sun Pro M2

VRAM 1GB/2 GB DDR3 x4

LVDS Conn.

HDMI Conn.

CRT Conn.

2 2

P21

P20

P22

page 10~15

MINI Card (WLAN/BT)

P26

GPP1GPP2

LAN Atheros AR8162/8172

Transformer

RJ45

BIOS (4M)

Int.KBD

P.30

ENE KBC9012

3 3

PS2

Touch Pad

P.5

P.28

P.30

Thermal Sensor

P.29

AMD Kabini

Gen2PCIe x 4

P24

P25

GFX

DP0

DP1

DAC

GPP

SPI

LPC

AMD FT3 APU

Jaguar Core

Integrated Yangtze FCH

BGA 769-balls

USB

HDA

SATA

P.4~P.7

Memory BUS(DDR3)

Single Channel

1.5V DDRIII 1600MHz

P.21

CMOS Camera

Port 3

USB2.0

MB

Port 8 Port 9

P.27

3.0 Conn. LP1

Port 0

USB3.0

HD Audio

Port 0

Gen3

HDD Conn.

204pin DDRIII-SO-DIMM X2

P.26

WLAN BT Combo

Port 5

P.27

MB

3.0 Conn. LP2

Port 1

ODD Conn.

P.23 P.23

BANK 0, 1, 2

Card Reader

Port 4

P.30

P.8~P.9

Touch S

creen

Audio Conexant CX20757

P.26

Port 1

P.31

S/B

2.0 Conn.

Port 0

P.27

Int. MIC

page 31

Int. Speaker Conn.

page 31

Audio Combo Jacks

HP & MIC

page 31

Sub-borad

15"

14"

IO/B

LS9633P

page 30

4 4

A

Power/B

USB/B

LS9632P

S9631P

L

page 30

page 27

ODD/B

LS9634P

LED/B

LS9635P

page 23

page 30

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/04/22 2015/04/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

BLOCK DIAGRAMS

VAWGA/GB

E

1.0

2 48Thursday, March 28, 2013

1.0

A

B

C

D

E

Voltage Rails

Power Plane Description

VIN

B+

+APU_CORE

+APU_CORE_NB ON OFF OFFVoltage for On-die VGA of APU

1 1

+VGA_CORE OFFOFFON0.95-1.2V switched power rail

+VDDCI OFF0.95-1.2V switched power rail ON OFF

+3VALW

+3VS

+1.8VALW

+1.8VS

+0.95VALW

+0.95VS

+1.5V

+3VGS

+1.8VGS

+1.5VGS

+0.95VGS

+5VALW

+5VS

2 2

+VSB ON ON

+RTC_APU

+0.75VS ON OFFOFF

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for APU

3.3V always on power rail

3.3V switched power rail

1.8V always on power rail

1.8V switched power rail

0.95V always on power rail

0.95V switched power rail

1.5V power rail for APU and DDR

1.5V switched power rail

3.3V switched power rail for VGA

1.8V switched power rail for VGA

1.5V switched power rail for VGA

0.95V switched power rail for VGA

5V always on power rail

5V switched power rail

VSB always on power rail

RTC power

0.75V switched power rail for DDR terminator

S0 S3 S5

ON ON ON

ON OFF

ONON OFF

ON OFF OFF

ON ON*ON

ON OFF OFF

ON OFFON

OFFON OFF+1.5VS

OFF

ON

OFF OFF

ON

ON OFF OFF

OFF

ON

OFF

ON

SMBUS Control Table

SOURCE

SMB_EC_CK1 SMB_EC_DA1

APU_SCLK0 APU_SDATA0

SMB_EC_CK2 SMB_EC_DA2

3 3

KB9012

+3VALW

APU

+3VS

KB9012

+3VS

VGA BATT KB9012 SODIMM

X V

+3VALW

X

V V

+3VS +3VS

X X

WLAN WWAN

X X

VX

+3VS +3VS

X

V

EC SM Bus1 address EC SM Bus2 address

Device Address

Smart Battery

0001 011X b

HEX

Device Address HEX

16H

Thermal Sen sor

SB-TSI (APU)

VGA Internal Thermal

1001 101X b

1001 100X b

1000 001X b

APU SM Bus address

4 4

Device Address

DDR DIMM1

DDR DIMM2

1010 000Xb

1010 001Xb

HEX

A0H

A2H

A

B

BOARD ID Table

PCB Revision MP PVT DVT EVT

ONONON

OFF

Board ID

0 1 2 3 4 5 6 7

Board ID / SKU ID Table for AD channel

OFF

ON

OFFON

ONON

Thermal Sensor

XX

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7 NC

FCH

100K +/- 5%R1562

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

APU RTD2132

X

+3VS

R1564 V min

0

X X

V

X

USB Port Table

USB 2.0 USB 3.0

9AH

98H

82H

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF) LOW

AD_BID

0 V

V typ

AD_BID

0 V 0 V

V

AD_BID

max

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

2.200 V

3.300 V

2.341 V

3.300 V

APU PCIE PORT LIST

DevicePort

0 1 2 3

Port

0

XHCI

1

2012/04/22 2015/04/22

C

LAN WLAN

3 External USB Port

0

RIGHT USB

1

Touch Screen

2 3

Camera

4

CardReader

5

WLAN/BT Combo

6

LEFT USB (for colay)

7

LEFT USB (for colay)

8

LEFT USB3.0

9

LEFT USB3.0

Compal Secret Data

Deciphered Date

SIGNAL

SLP_S3# SLP_S5# +VALW +V +VS Clock

HIGH HIGH

HIGH

LOW

USB OC MAPPING

0 1 2 3

BOM Structure Table

BOM Structure BTO Item

A6@ A4@ E2@ E1@ E1PC@ X4@ X5@ X2@ EMICU@ EMICP@ EMIUSB2RU@ EMIUSB2RP@ USB2R@ SUN@ MARS@ 14@ 15@ PX@ CMOS@ HDMI@ EMIGASP@ 8162@ 8172@ SWR@ LDO@ THERMAL@ ME@ UMA@ @ ZODD@ TS@ EMIP@ EMIU@ ESDP@ ESDU@

D

ON

ON ON

ON

OFF

LOW

OFF

HIGHHIGH

HIGH

LOW

ON

OFF

ON

OFF

USB PortOC#

USB20 port0

USB20 port1,2,8,9

A6 R3 BGA APU

A4 R3 BGA APU

E2 R3 BGA APU

E1 R3 BGA APU

E1 PC BGA APU

X4 ES2 BGA APU

X5 ES2 BGA APU

X2 ES2 BGA APU

CardReader EMI Un pop

CardReadear EMI pop

Right USB2.0 port EMI un pop

Right USB2.0 port EMI pop

Right USB2.0 port component

SUN PRO GPU (R3 compal part)

MARS XT GPU (R1 compal part)

for 14" componect

for 15" componect

Common VGA circuit

CMOS Camera part

HDMI part

Gastube

Ateros AR8162 LAN Chip

Ateros AR8172 LAN Chip

LAN Switching mode

LAN LDO mode

Lenovo Thermal Sensor

ME part

UMA part

Unpop

Zero Power ODD part

Touch Screen

EMI pop component

EMI Un pop component

ESD pop component

ESD Un pop component

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

USB30 port0,1

NOTES LIST

VAWGA/GB

E

3 48Monday, April 01, 2013

1.0

A

<8,9>

DDRAB_SMA[15..0]

1 1

<8,9>

DDRAB_SBS0#

<8,9>

DDRAB_SBS1#

<8,9>

DDRAB_SBS2#

<8,9>

DDRAB_SDM[7..0]

<8,9>

DDRAB_SDQS0

<8,9>

DDRAB_SDQS0#

<8,9>

DDRAB_SDQS1

<8,9>

DDRAB_SDQS1#

<8,9>

DDRAB_SDQS2

<8,9>

DDRAB_SDQS2#

<8,9>

DDRAB_SDQS3

<8,9>

DDRAB_SDQS3#

<8,9>

DDRAB_SDQS4

<8,9>

DDRAB_SDQS4#

<8,9>

DDRAB_SDQS5

<8,9>

DDRAB_SDQS5#

<8,9>

DDRAB_SDQS6

<8,9>

DDRAB_SDQS6#

2 2

<8,9>

DDRAB_SDQS7

<8,9>

DDRAB_SDQS7#

<8>

DDRA_CLK0

<8>

DDRA_CLK0#

<8>

DDRA_CLK1

<8>

DDRA_CLK1#

<9>

DDRB_CLK0

<9>

DDRB_CLK0#

<9>

DDRB_CLK1

<9>

DDRB_CLK1#

<8,9>

MEM_MAB_RST#

<8,9>

MEM_MAB_EVENT#

<8>

DDRA_CKE0

<8>

DDRA_CKE1

<9>

DDRB_CKE0

<9>

DDRB_CKE1

<8>

DDRA_ODT0

<8>

DDRA_ODT1

<9>

DDRB_ODT0

<9>

DDRB_ODT1

<8>

DDRA_SCS0#

<8>

DDRA_SCS1#

<9>

DDRB_SCS0#

<9>

<8,9> <8,9> <8,9>

DDRB_SCS1#

DDRAB_SRAS# DDRAB_SCAS# DDRAB_SWE#

+MEM_VREF +VREF_DQ

ZZZ

LA9911P

DAZ0Y600101

14@

3 3

MEM_MAB_EVENT#

R576 0_0402_5%@R576 0_0402_5%@

ZZZ

LA9911P

DAZ0Y700101

DDRAB_SMA0 DDRAB_SMA1 DDRAB_SMA2 DDRAB_SMA3 DDRAB_SMA4 DDRAB_SMA5 DDRAB_SMA6 DDRAB_SMA7 DDRAB_SMA8 DDRAB_SMA9 DDRAB_SMA10 DDRAB_SMA11 DDRAB_SMA12 DDRAB_SMA13 DDRAB_SMA14 DDRAB_SMA15

DDRAB_SDM0 DDRAB_SDM1 DDRAB_SDM2 DDRAB_SDM3 DDRAB_SDM4 DDRAB_SDM5 DDRAB_SDM6 DDRAB_SDM7

1 2

AG38

W35 W38 W34

U38 U37 U34 R35 R38 N38

AG34

R34 N37

AN34

L38 L35

AJ38

AG35

N34

B32 B38 G40

N41 AG40 AN41 AY40 AY34

Y40

B33

A33

B40

A40

H41

H40

P41

P40 AH41 AH40 AP41 AP40 BA40 AY41 AY33 BA34 AA40

Y41

AC35 AC34 AA34 AA32 AE38 AE37 AA37 AA38

G38 AE34

L34

J38 J37 J34

AN38 AU38 AN37 AR37

AJ34

AR38

AL38

AN35

AJ37 AL34 AL35

AD40 AC38

X5 ES2 ZM201079J4460 2G BGA 769P

15@

M_ADD0

M_ADD1

M_ADD2

M_ADD3

M_ADD4

M_ADD5

M_ADD6

M_ADD7

M_ADD8

M_ADD9

M_ADD10

M_ADD11

M_ADD12

M_ADD13

M_ADD14

M_ADD15

M_BANK0

M_BANK1

M_BANK2

M_DM0

M_DM1

M_DM2

M_DM3

M_DM4

M_DM5

M_DM6

M_DM7

M_DM8

M_DQS_H0

M_DQS_L0

M_DQS_H1

M_DQS_L1

M_DQS_H2

M_DQS_L2

M_DQS_H3

M_DQS_L3

M_DQS_H4

M_DQS_L4

M_DQS_H5

M_DQS_L5

M_DQS_H6

M_DQS_L6

M_DQS_H7

M_DQS_L7

M_DQS_H8

M_DQS_L8

M_CLK_H0

M_CLK_L0

M_CLK_H1

M_CLK_L1

M_CLK_H2

M_CLK_L2

M_CLK_H3

M_CLK_L3

M_RESET_L

M_EVENT_L

M0_CKE0

M0_CKE1

M1_CKE0

M1_CKE1

M0_ODT0

M0_ODT1

M1_ODT0

M1_ODT1

M0_CS_L0

M0_CS_L1

M1_CS_L0

M1_CS_L1

M_RAS_L

M_CAS_L

M_WE_L

M_VREF

M_VREFDQ

UAPU

+VREF_DQ

MEMORY VREF

4 4

+1.5V

RP2

1 8

+MEM_VREF

2 7 3 6

MEM_MAB_EVENT#

4 5

1K_0804_8P4R_1%

A

1

@

C342

C342 1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

C337

C337 1U_0402_6.3V6K

1U_0402_6.3V6K

2

@

C164

0.1U_0402_16V7K

1

FT3 REV 0.51

X5@UAPU

X5@

2

C163

0.1U_0402_16V7K

1

MEMORY

UAPUA

M_ZVDDIO_MEM_S

0.1U_0402_16V7K

RP11

@RP11

@

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

B30

M_DATA0

A32

M_DATA1

B35

M_DATA2

A36

M_DATA3

B29

M_DATA4

A30

M_DATA5

A34

M_DATA6

B34

M_DATA7

B37

M_DATA8

A38

M_DATA9

D40

M_DATA10

D41

M_DATA11

B36

M_DATA12

A37

M_DATA13

B41

M_DATA14

C40

M_DATA15

F40

M_DATA16

F41

M_DATA17

K40

M_DATA18

K41

M_DATA19

E40

M_DATA20

E41

M_DATA21

J40

M_DATA22

J41

M_DATA23

M41

M_DATA24

N40

M_DATA25

T41

M_DATA26

U40

M_DATA27

L40

M_DATA28

M40

M_DATA29

R40

M_DATA30

T40

M_DATA31

AF40

M_DATA32

AF41

M_DATA33

AK40

M_DATA34

AK41

M_DATA35

AE40

M_DATA36

AE41

M_DATA37

AJ40

M_DATA38

AJ41

M_DATA39

AM41

M_DATA40

AN40

M_DATA41

AT41

M_DATA42

AU40

M_DATA43

AL40

M_DATA44

AM40

M_DATA45

AR40

M_DATA46

AT40

M_DATA47

AV41

M_DATA48

AW40

M_DATA49

BA38

M_DATA50

AY37

M_DATA51

AU41

M_DATA52

AV40

M_DATA53

AY39

M_DATA54

AY38

M_DATA55

BA36

M_DATA56

AY35

M_DATA57

BA32

M_DATA58

AY31

M_DATA59

BA37

M_DATA60

AY36

M_DATA61

BA33

M_DATA62

AY32

M_DATA63

V41

M_CHECK0

W40

M_CHECK1

AB40

M_CHECK2

AC40

M_CHECK3

U41

M_CHECK4

V40

M_CHECK5

AA41

M_CHECK6

AB41

M_CHECK7

AD41

X4@

FT3_BGA769

ESDP@ C195

ESDP@

APU_TRST#

B

DDRAB_SDQ0 DDRAB_SDQ1 DDRAB_SDQ2 DDRAB_SDQ3 DDRAB_SDQ4 DDRAB_SDQ5 DDRAB_SDQ6 DDRAB_SDQ7

DDRAB_SDQ8 DDRAB_SDQ9 DDRAB_SDQ10 DDRAB_SDQ11 DDRAB_SDQ12 DDRAB_SDQ13 DDRAB_SDQ14 DDRAB_SDQ15

DDRAB_SDQ16 DDRAB_SDQ17 DDRAB_SDQ18 DDRAB_SDQ19 DDRAB_SDQ20 DDRAB_SDQ21 DDRAB_SDQ22 DDRAB_SDQ23

DDRAB_SDQ24 DDRAB_SDQ25 DDRAB_SDQ26 DDRAB_SDQ27 DDRAB_SDQ28 DDRAB_SDQ29 DDRAB_SDQ30 DDRAB_SDQ31

DDRAB_SDQ32 DDRAB_SDQ33 DDRAB_SDQ34 DDRAB_SDQ35 DDRAB_SDQ36 DDRAB_SDQ37 DDRAB_SDQ38 DDRAB_SDQ39

DDRAB_SDQ40 DDRAB_SDQ41 DDRAB_SDQ42 DDRAB_SDQ43 DDRAB_SDQ44 DDRAB_SDQ45 DDRAB_SDQ46 DDRAB_SDQ47

DDRAB_SDQ48 DDRAB_SDQ49 DDRAB_SDQ50 DDRAB_SDQ51 DDRAB_SDQ52 DDRAB_SDQ53 DDRAB_SDQ54 DDRAB_SDQ55

DDRAB_SDQ56 DDRAB_SDQ57 DDRAB_SDQ58 DDRAB_SDQ59 DDRAB_SDQ60 DDRAB_SDQ61 DDRAB_SDQ62 DDRAB_SDQ63

UAPU

E2 PR KABINI EM3000IBJ23HM 1.65G BGA 769P APU

M_ZVDDIO

+1.8VS

2

C195

1

B

DDRAB_SDQ[63..0]

<20> <20>

HDMI

<20> <20>

<21> <21>

LVDS

<21> <21>

<40> <40> <40>

<11,28,29> <11,28,29>

<40>

<28,34,40,6>

<40> <40>

<40>

UAPU

A6 PR KABINI AM5200IAJ44HM 2G BGA769P APU

E2@UAPU

E2@

1 2

R74

39.2_0402_1%

+1.5V

HDT+

JHDT2

1

3

5

7

9

11

13

15

17

19

SAMTE_ASP-136446-07-B@

C

HDMI & LVDS should be reverse in KABINI:

<8,9>

APU TX0 to Connector TX2 ; APU TX1 to Connector TX1 APU TX2 to Connector TX0 ; APU TX3 to Connector CLK

DP2_TXP0 DP2_TXN0

DP2_TXP1 DP2_TXN1

DP2_TXP2 DP2_TXN2

DP2_TXP3 DP2_TXN3

LVDS_A2 LVDS_A2#

LVDS_A1 LVDS_A1#

LVDS_A0 LVDS_A0#

LVDS_ACLK LVDS_ACLK#

APU_SVT APU_SVC APU_SVD

EC_SMB_CK2

EC_SMB_DA2

APU_PWRGD

H_PROCHOT#

APU_VDDNB_SEN

APU_VDD_SEN

1 2

R124 0_0402 _5%@R124 0_0402 _5%@

1 2

R127 0_0402 _5%@R127 0_0402 _5%@

1 2

R117 0_0402_5%@R117 0_040 2_5%@

1 2

R118 0_0402_5%@R118 0_040 2_5%@

1 2

R120 0_0402_5%@R120 0_040 2_5%@

APU_VDD_RUN_FB_L

A6@UAPU

A6@

A4 PR KABINI AM5000IBJ44HM 1.5G BGA 769P APU

UAPU

E1@UAPU

E1@

E1 PR KABINI EM2100ICJ23HM 1G BGA769P APU

UAPU

X2@UAPU

X2@

X2 ES2 KABINI ZMA5B078J2360 1.65G BGA CPU

2

APU_TCK

2

4

APU_TMS

4

6

APU_TDI

6

8

APU_TDO

8

10

APU_PWRGD

10

12

APU_RST#

12

14

APU_DBRDY

14

16

APU_DBREQ#

16

18

APU_PLLTEST0

18

20

APU_PLLTEST1

20

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

APU_TDI APU_TMS APU_TCK APU_DBREQ#

RP11, RP6 will @ when MP

Issued Date

C

DISPLAY/SVI2/JTAG/TEST

A9 B9

A10 B10

A11 B11

A12 B12

A4 B4

A5 B5

A6 B6

A7 B7

K15 H15

LDT_RST#

LDT_PWRGD

ESDU@

E1PC@UAPU

E1PC@

Compal Secret Data

G31 D27 E29

B22 B21

B20 A20

B19 A19

A22 B18

D29 D31 D35 D33 G27 B25 A25

D23 G23 E25 E23

AV33 AU33

DP_STEREOSYNC CRT_HSYNC

+1.8VS

APU_SVT APU_SVC APU_SVD

APU_SIC APU_SID

APU_RST#

APU_PWRGD

APU_PROCHOT#

APU_ALERT#

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

UAPU

A4@UAPU

A4@

APU_PWRGD

APU_RST#

1 2

C1270 100P_0402_50V8J

1 2

C1273 100P_0402_50V8J

UAPU

E1 PC 2M101082J2361 1G BGA 769P

RP6

1 8 2 7 3 6 4 5

1K_0804_8P4R_5%

2012/04/22 2015/04/22

DISPLAY/SVI2/JTAG/TEST

TDP1_TXP0

TDP1_TXN0

TDP1_TXP1

TDP1_TXN1

TDP1_TXP2

TDP1_TXN2

TDP1_TXP3

TDP1_TXN3

LTDP0_TXP0

LTDP0_TXN0

LTDP0_TXP1

LTDP0_TXN1

LTDP0_TXP2

LTDP0_TXN2

LTDP0_TXP3

LTDP0_TXN3

DISP_CLKIN_H

DISP_CLKIN_L

SVT

SVC

SVD

SIC

SID

APU_RST_L

LDT_RST_L

APU_PWROK

LDT_PWROK

PROCHOT_L

ALERT_L

TDI

TDO

TCK

TMS

TRST_L

DBRDY

DBREQ_L

VDDCR_NB_SENSE

VDDCR_CPU_SENSE

VDDIO_MEM_S_SENSE

VSS_SENSE

VDD_095_FB_H

VDD_095_FB_L

FT3 REV 0.51

PU +1.8VS + PD

APU_SCLK APU_CLKINT APU_SCLK APU_CLKINT

Deciphered Date

D

UAPUC

DP_150_ZVSS

DP_2K_ZVSS

DP_BLON

DP_DIGON

DP_VARY_BL

TDP1_AUXP

TDP1_AUXN

TDP1_HPD

LTDP0_AUXP

LTDP0_AUXN

LTDP0_HPD

DAC_RED

DAC_GREEN

DAC_BLUE

DAC_HSYNC

DAC_VSYNC

DAC_SCL

DAC_SDA

DAC_ZVSS

THERMDA

THERMDC

DIECRACKMON

BP0

BP1

BP2

BP3

PLLTEST1

PLLTEST0

BYPASSCLK_H

BYPASSCLK_L

PLLCHRZ_H

PLLCHRZ_L

M_TEST

FREE_2

GIO_TSTDTM0_SERIALCLK

GIO_TSTDTM0_CLKINIT

USB_ATEST0

USB_ATEST1

M_ANALOGIN

M_ANALOGOUT

TMON_CAL

HDMI_EN/DP_STEREOSYNC

X4@

+1.8VS +3VS

R114

1K_0402_5%

1 2

For HDMI Need

RP3

@RP3

@

1 8 2 7 3 6 4 5

1K_0804_8P4R_5%

D

B16

DP_150_ZVSS

A21

DP_2K_ZVSS

B17 A17 A18

D17 E17

H19

D15 E15

H17

1 2

R897 100K_0402_5%R897 100K_0402_5%

B14

A14

B15

G19

CRT_HSYNC

E19

D19 D21

A16

DAC_ZVSS

H27 H29 D25 A27

APU_BP0

B27

APU_BP1

A26

APU_BP2

B26

APU_BP3

B28

APU_PLLTEST1

A28

APU_PLLTEST0

B24

APU_BPCLK_H

A24

APU_BPCLK_L

AV35 AU35 E33

A29 H21

APU_SCLK

H25

APU_CLKINT

AJ10 AJ8 R32 N32 AP29

E21

DP_STEREOSYNC

FT3_BGA769

R113

R113 1K_0402_5%

1K_0402_5%

1 2

+1.8VS

E

1 2

R400 2K_0 402_1%R400 2K_0 402_1%

+3VS

1 2

R416 499_04 02_1%R416 499_0402_1%

ENBKL <28> APU_ENVDD APU_INVT_PWM

HDMI_CLK HDMI_DATA

HDMI_DET

EDID_CLK EDID_DATA

DAC_RED

DAC_GRN

DAC_BLU

CRT_HSYNC CRT_VSYNC

CRT_DDC_CLK CRT_DDC_DATA

<21> <21>

<20,22> <20,22>

<20>

<21> <21>

<22>

CRT

<22>

<22> <22>

+3VS

EDID_CLK

R255 4.7K_0402_5%R255 4.7K_0402_5%

EDID_DATA

R256 4.7K_0402_5%R256 4.7K_0402_5%

T39T39 T40T40 T41T41

T42T42

T45T45 T43T43 T44T44 T46T46 T47T47

PU +3VS

APU_ALERT# APU_SID APU_PROCHOT# APU_SIC

PU +1.8VS

APU_SVT APU_SVC APU_SVD

APU_RST# APU_PWRGD APU_BPCLK_L

R80 300_0402_5%R80 300_0402_5% R82 300_0402_5%R82 300_0402_5% R18 511_0402_1%R18 511_0402_1%

PD

APU_BP2 APU_BP3 APU_BP0 APU_BP1

APU_TRST# APU_PLLTEST0 APU_PLLTEST1

APU_BPCLK_H

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

FT3 DDR3/DISP/MISC//HDT+

R19 511_0402_1%R19 511_0402_1%

VAWGA/GB

12 12

RP23

18 27 36 45

150_0804_8P4R_1%

RP4

1 8 2 7 3 6 4 5

1K_0804_8P4R_5%

RP5

@RP5

@

1 8 2 7 3 6 4 5

1K_0804_8P4R_5%

1 2 1 2 1 2

RP7

@RP7

@

1 8 2 7 3 6 4 5

1K_0804_8P4R_5%

RP8

1 8 2 7 3 6 4 5

1K_0804_8P4R_5%

1 2

E

DAC_BLU DAC_GRN DAC_RED DP_150_ZVSS

+1.8VS

4 48Monday, April 01, 2013

+3VS

+1.8VS

1.0

A

R10

P_GPP_RXP0

R8

P_GPP_RXN0

R5

N10

GFX_CLKP GFX_CLKN

GPP_CLK1P GPP_CLK1N

GPP_CLK2P GPP_CLK2N

T50T50

P_GPP_RXP1

R4

P_GPP_RXN1

N5

P_GPP_RXP2

N4

P_GPP_RXN2

P_GPP_RXP3

N8

P_GPP_RXN3

W8

P_TX_ZVDD_095

L5

P_GFX_RXP0

L4

P_GFX_RXN0

J5

P_GFX_RXP1

J4

P_GFX_RXN1

G5

P_GFX_RXP2

G4

P_GFX_RXN2

D7

P_GFX_RXP3

E7

P_GFX_RXN3

BA14

SATA_TX0P

AY14

SATA_TX0N

BA16

SATA_RX0N

AY16

SATA_RX0P

AY19

SATA_TX1P

BA19

SATA_TX1N

AY17

SATA_RX1N

BA17

SATA_RX1P

AR19

SATA_ZVSS

AP19

SATA_ZVDD_095

BA30

SATA_ACT_L/GPIO67

AY12

SATA_X1

BA12

SATA_X2

U4

GFX_CLKP

U5

GFX_CLKN

AC8

GPP_CLK0P

AC10

GPP_CLK0N

AE4

GPP_CLK1P

AE5

GPP_CLK1N

AC4

GPP_CLK2P

AC5

GPP_CLK2N

AA5

GPP_CLK3P

AA4

GPP_CLK3N

AP13

X14M_25M_48M_OSC

N2

X48M_X1

N1

X48M_X2

AY2

LPCCLK0

AW2

LPCCLK1

AT2

LAD0

AT1

LAD1

AR2

LAD2

AR1

LAD3

AP2

LFRAME_L

AP1

LDRQ0_L

AV29

SERIRQ/GPIO48

AP25

LPC_CLKRUN_L

AV2

LPC_PD_L/GEVENT5_L/SPI_TPM_CS_L

<24>

LAN

WLAN WLAN

1 1

VGA

2 2

HDD

ODD

PCIE_DTX_C_ARX_P1

<24>

PCIE_DTX_C_ARX_N1

<26>

PCIE_DTX_C_ARX_P2

<26>

PCIE_DTX_C_ARX_N2

<10>

PCIE_GTX_C_ARX_P0

<10>

PCIE_GTX_C_ARX_N0

<10>

PCIE_GTX_C_ARX_P1

<10>

PCIE_GTX_C_ARX_N1

<10>

PCIE_GTX_C_ARX_P2

<10>

PCIE_GTX_C_ARX_N2

<10>

PCIE_GTX_C_ARX_P3

<10>

PCIE_GTX_C_ARX_N3

<23>

SATA_ATX_DRX_P0

<23>

SATA_ATX_DRX_N0

<23>

SATA_DTX_C_ARX_N0

<23>

SATA_DTX_C_ARX_P0

<23>

SATA_ATX_DRX_P1

<23>

SATA_ATX_DRX_N1

<23>

SATA_DTX_C_ARX_N1

<23>

SATA_DTX_C_ARX_P1

R90 1K_0402_1%R90 1K_0402_1% R96 1K_0402_1%R96 1K_0402_1%

+0.95VS

1 2

P_TX_ZVDD_095 P_RX_ZVDD_095

R404

1.69K_0402_1%

12 12

SATA_ZVSS SATA_ZVDD

T48T48

0_0402_5%

VGA

<10>

CLK_PEG_VGA

<10>

CLK_PEG_VGA#

LAN

3 3

<24>

CLK_PCIE_LAN

<24>

CLK_PCIE_LAN#

<26>

CLK_PCIE_WLAN

<26>

CLK_PCIE_WLAN#

WLAN

R112 R115

R116 R119

R125 R126

0_0402_5%

1 2

@R112

@

1 2

@R115

@

0_0402_5%

1 2

@R116

@

1 2

@R119

@

0_0402_5%

1 2

@R125

@

1 2

@R126

@

0_0402_5%

48M_X1

1 2 1 2

48M_X2

R103 R104 for EMI

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME#

SERIRQ

A

R103 0_0402 _5%@R103 0_0402 _5%@ R104 0_0402 _5%@R104 0_0402 _5%@

<28,6>

LPC_CLK0_EC

<6>

LPC_CLK1

<28> <28> <28> <28> <28,6>

<28>

4 4

FT3 REV 0.51

UAPUB

PCIE

B

P_GPP_TXP0

P_GPP_TXN0

P_GPP_TXP1

P_GPP_TXN1

P_GPP_TXP2

P_GPP_TXN2

P_GPP_TXP3

P_GPP_TXN3

P_RX_ZVDD_095

P_GFX_TXP0

P_GFX_TXN0

P_GFX_TXP1

P_GFX_TXN1

P_GFX_TXP2

P_GFX_TXN2

P_GFX_TXP3

P_GFX_TXN3

X4@

UAPUE

CLK/SATA/USB/SPI/LPC

FT3 REV 0.51

B

L2 L1

K2

PCIE_ATX_DRX_P1

K1

PCIE_ATX_DRX_N1

J2

PCIE_ATX_DRX_P2

J1

PCIE_ATX_DRX_N2

H2 H1

W7

G2

PCIE_ATX_GRX_P0

G1

PCIE_ATX_GRX_N0

F2

PCIE_ATX_GRX_P1

F1

PCIE_ATX_GRX_N1

E2

PCIE_ATX_GRX_P2

E1

PCIE_ATX_GRX_N2

D2

PCIE_ATX_GRX_P3

D1

PCIE_ATX_GRX_N3

FT3_BGA769

USBCLK/14M_25M_48M_OSC

USB_SS_ZVSS

USB_SS_ZVDD_095_USB3_DUAL

USB_SS_0TXP

USB_SS_0TXN

USB_SS_0RXP

USB_SS_0RXN

USB_SS_1TXP

USB_SS_1TXN

USB_SS_1RXP

USB_SS_1RXN

SPI_CLK/GPIO162

SPI_CS1_L/GPIO165

SPI_CS2_L/GPIO166

SPI_DO/GPIO163

SPI_DI/GPIO164

SPI_HOLD_L/GEVENT9_L

SPI_WP_L/GPIO161

FT3_BGA769X4@

USB_ZVSS

USB_HSD0P

USB_HSD0N

USB_HSD1P

USB_HSD1N

USB_HSD2P

USB_HSD2N

USB_HSD3P

USB_HSD3N

USB_HSD4P

USB_HSD4N

USB_HSD5P

USB_HSD5N

USB_HSD6P

USB_HSD6N

USB_HSD7P

USB_HSD7N

USB_HSD8P

USB_HSD8N

USB_HSD9P

USB_HSD9N

1 2

C19 0.1U_0402_16V7KC19 0.1U_0402_16V7K

1 2

C20 0.1U_0402_16V7KC20 0.1U_0402_16V7K

1 2

C17 0.1U_0402_16V7KC17 0.1U_0402_16V7K

1 2

C18 0.1U_0402_16V7KC18 0.1U_0402_16V7K

12

R73

R73 1K_0402_1%

1K_0402_1%

1 2

C1 0.1U_0402_16V7KPX@C1 0.1U_0402_16V7KPX@

1 2

C2 0.1U_0402_16V7KPX@C2 0.1U_0402_16V7KPX@

1 2

C3 0.1U_0402_16V7KPX@C3 0.1U_0402_16V7KPX@

1 2

C4 0.1U_0402_16V7KPX@C4 0.1U_0402_16V7KPX@

1 2

C5 0.1U_0402_16V7KPX@C5 0.1U_0402_16V7KPX@

1 2

C6 0.1U_0402_16V7KPX@C6 0.1U_0402_16V7KPX@

1 2

C7 0.1U_0402_16V7KPX@C7 0.1U_0402_16V7KPX@

1 2

C8 0.1U_0402_16V7KPX@C8 0.1U_0402_16V7KPX@

W4

AG4

USB_ZVSS

AL4 AL5

AJ4 AJ5

AG7 AG8

AG1 AG2

AF1 AF2

AE1 AE2

AD1 AD2

AC1 AC2

AB1 AB2

AA1 AA2

AE10 AE8

T2 T1

V2 V1

R1 R2

W1 W2

AU7 AW9 AR4 AR11 AR7 AU11 AU9

R641 11.8K_040 2_1%R641 11.8K_0402_1%

USBSS_ZVSS USBSS_ZVDD

APU_SPI_CLK APU_SPI_CS1#

APU_SPI_AOSI

APU_SPI_AISO

APU_SPI_HOLD# APU_SPI_WP#

R644 1K_0 402_1%R644 1K_0 402_1% R645 1K_0 402_1%R645 1K_0 402_1%

C

D

APU POWER SEQUENCE

PCIE_ATX_C_DRX_P1 PCIE_ATX_C_DRX_N1

PCIE_ATX_C_DRX_P2 PCIE_ATX_C_DRX_N2

+0.95VS_APU_GFX+0.95VS_APU_GFX

PCIE_ATX_C_GRX_P0 PCIE_ATX_C_GRX_N0

PCIE_ATX_C_GRX_P1 PCIE_ATX_C_GRX_N1

PCIE_ATX_C_GRX_P2 PCIE_ATX_C_GRX_N2

PCIE_ATX_C_GRX_P3 PCIE_ATX_C_GRX_N3

<24> <24>

<26> <26>

<10> <10>

LAN

VGA

G-B

G-C

G-D

G-E

G-A

1 2

USB20_P0 USB20_N0

USB20_P1 USB20_N1

USB20_P3 USB20_N3

USB20_P4 USB20_N4

USB20_P5 USB20_N5

USB20_P6 USB20_N6

USB20_P7 USB20_N7

USB30_P8 USB30_N8

USB30_P9 USB30_N9

1 2 1 2

USB30_MTX_C_DRX_P0 USB30_MTX_C_DRX_N0

USB30_MRX_DTX_P0 USB30_MRX_DTX_N0

USB30_MTX_C_DRX_P1 USB30_MTX_C_DRX_N1

USB30_MRX_DTX_P1 USB30_MRX_DTX_N1

1 2

R110 33_040 2_5%R110 33_0402_5%

1 2

R111 33_040 2_5%R111 33_0402_5%

T51T51

1 2

R109 33_040 2_5%R109 33_0402_5%

<27>

Right USB port

<27>

<26>

Touch Screen

<26>

<21>

CAMERA

<21>

<30>

CardReader

<30>

<26>

WLAN/BT combo

<26>

<27>

USB2.0 LP1

<27>

USB2.0 LP2

<27>

MB USB3.0 port0

<27>

MB USB3.0 port1

<27>

+0.95VALW

<27> <27>

R109,R110,R111 close to APU

APU_SPI_CLK_U APU_SPI_CS1#_U

APU_SPI_AISO

APU_SPI_AOSI_U

APU_SPI_CLK_U

APU_SPI_CS1#_U

APU_SPI_AOSI_U

APU_SPI_AISO

R108 close to ROM

1 2

R108 33_040 2_5%R108 33_0402_5%

RP12

1 8 2 7 3 6 4 5

0_0804_8P4R_5%

APU->EC->ROM must route as Daisy Chain for Share ROM quality (RP12 was request to added for the recoverable solution as original method--backup)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/04/22 2015/04/22

Compal Secret Data

Deciphered Date

+RTC

EC_ON

+3VALW/+5VALW

+1.8VALW

+0.95VALW

SYSON

+1.5V

SUSP#

+3VS

+1.8VS

+1.5VS

+0.95VS

VR_ON

+APU_CORE

+APU_CORE_NB

EC_SPI_AISO EC_SPI_AOSI

EC_SPI_CLK EC_SPI_CS1#

EC_SPI_AISO EC_SPI_AOSI EC_SPI_CLK EC_SPI_CS1#

4MB SPI ROM (Current Share mode)

+3VALW

R614

R614 10K_0402_5%

10K_0402_5%

1 2

R616

R616 10K_0402_5%

10K_0402_5%

D

APU_SPI_CS1#_U APU_SPI_AISO_U APU_SPI_WP#

U56

1

CS#

2

SO/SIO1

3

WP#

4

GND

W25Q32FVSSIG SOIC 8P SPI ROM

Title

Size Document Number Rev

Custom

Date: Sheet of

E

48MHz CRYSTAL

R938

R938 1M_0402_5%

1M_0402_5%

2

3

Y20

Y20 48MHZ_8PF_X3S048000D81H-W

48MHZ_8PF_X3S048000D81H-W

12

C794

<28> <28> <28> <28>

C794 6P_0402_50V8

6P_0402_50V8

8

VCC

7

HOLD#

SCLK

SI/SIO0

APU_SPI_HOLD#

6

APU_SPI_CLK_U

5

APU_SPI_AOSI_U

APU_SPI_CLK_U

Compal Electronics, Inc.

FT3 PCIE/SATA/CLK/USB/SPI

VAWGA/GB

1 2

R617

10_0402_5%

E

1

4

12

@

12

C635

0.1U_0402_16V4Z

1 2

R615

R615 10K_0402_5%

10K_0402_5%

1 2

EMIU@R617

EMIU@

5 48Thursday, March 28, 2013

48M_X2

48M_X1

C795

C795 6P_0402_50V8

6P_0402_50V8

+3VALW

C636

EMIU@C636

EMIU@

10P_0402_50V8J

1.0

A

1 2

C615

C615 150P_0402_50V8J

<28>

1 1

<24> <26>

<11>

<27> <27>

<31>

HDA_SDIN0

2 2

150P_0402_50V8J

LPC_RST#

<28>

<26>

<28> <28>

<28> <28> <28> <28>

LAN_CLKREQ#

WLAN_CLKREQ#

VGA_CLKREQ#

USB_OC0#

USB_OC1#

1 2

PBTN_OUT#

APU_PCIE_WAKE#

SLP_S3# SLP_S5#

KBRST# GATEA20 EC_SCI# EC_SMI#

1 2

R578 0_0402_5%@R578 0_0402_5%@

R602

R602 33_0402_5%

33_0402_5%

LAN_CLKREQ# WLAN_CLKREQ#

VGA_CLKREQ#_R

T55T55 T56T56 T57T57

LPC_RST_A# APU_PCIE_RST#_BUF

EC_RSMRST#_R

PWR_GOOD_APU

APU_PCIE_WAKE#

TEST0 CS_JTAG_TMS_TEST1 TEST2

HDA_BITCLK HDA_SDOUT HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SYNC HDA_RST#

32K_X1

32K_X2

T36T36

T53T53

T52T52 T54T54

AY4

LPC_RST_L

AY9

PCIE_RST_L

AY5

RSMRST_L

BA8

PWR_BTN_L

AM19

PWR_GOOD

AY7

SYS_RESET_L/GEVENT19_L

AW11

WAKE_L/GEVENT8_L

AY3

SLP_S3_L

BA5

SLP_S5_L

AU13

TEST0

AY10

TEST1/TMS

AY6

TEST2

AR23

KBRST_L

AR31

GA20IN/GEVENT0_L

AN5

LPC_PME_L/GEVENT3_L

AL7

LPC_SMI_L/GEVENT23_L

AP15

AC_PRES/IR_RX0/GEVENT16_L

AV13

IR_TX0/GEVENT21_L

BA9

IR_TX1/GEVENT6_L

BA10

IR_RX1/GEVENT20_L

AV15

IR_LED_L/LLB_L/GPIO184

AU29

CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60

AW29

CLK_REQ1_L/GPIO61

AR27

CLK_REQ2_L/GPIO62

AV27

CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63

AY29

CLK_REQG_L/GPIO65/OSCIN

AY8

USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L

AW1

USB_OC1_L/TDI/GEVENT13_L

AV1

USB_OC2_L/TCK/GEVENT14_L

AY1

USB_OC3_L/TDO/GEVENT15_L

AN2

AZ_BITCLK

AN1

AZ_SDOUT

AK2

AZ_SDIN0/GPIO167

AK1

AZ_SDIN1/GPIO168

AM1

AZ_SDIN2/GPIO169

AL2

AZ_SDIN3/GPIO170

AM2

AZ_SYNC

AL1

AZ_RST_L

AJ2

X32K_X1

AJ1

X32K_X2

PU +3VALW + PD

+3VALW

3 3

1 2

R691 10K_ 0402_5%@R691 10K_ 0402_5%@

1 2

R686 10K_ 0402_5%R686 10K_ 0402_5%

APU_GPIO174

<31>

HDA_RST#_AUDIO

<31>

HDA_SYNC_AUDIO

<31>

HDA_BITCLK_AUDIO

<31>

HDA_SDOUT_AUDIO

PU +3VALW

+3VALW

+3VS

RP14

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

1 2

R656 100K _0402_5%@R656 100K _0402_5%@

1 2

R650 100K _0402_5%R650 100K_0402_5%

1 2

R651 100K _0402_5%R651 100K_0402_5%

1 2

R121 0_0402 _5%

APU_SCLK1 APU_SDATA1 APU_PCIE_WAKE#

@

EC_LID_OUT# USB_OC0# USB_OC1#

PXS_PWREN

PU +3VS

+3VS

4 4

PD

1 2

R622 8.2K_0402 _5%@R622 8.2K_0402 _5%@

1 2

R621 8.2K_0402 _5%@R621 8.2K_0402 _5%@

1 2

R673 2.2K_0402 _5%R673 2.2K_0402_5%

1 2

R674 2.2K_0402 _5%R674 2.2K_0402_5%

1 2

R618 8.2K_0402 _5%@R618 8.2K_0402 _5%@

1 2

R684 10K_ 0402_5%@R684 10K_ 0402_5%@

1 2

R688 10K_ 0402_5%@R688 10K_ 0402_5%@

1 2

R689 10K_ 0402_5%@R689 10K_ 0402_5%@

A

WLAN_CLKREQ#

LAN_CLKREQ# APU_SCLK0 APU_SDATA0

VGA_CLKREQ#_R

HDA_BITCLK

HDA_SDIN0

VGA_CLKREQ#_R

EC_RSMRST# , POWER_GOOD follow CRB (APU side 1.8V power rail)

<28>

EC_RSMRST#

<28>

SYS_PWRGD_EC

PU +3VALW + PD

TEST0 CS_JTAG_TMS_TEST1 TEST2

B

UAPUD

ACPI/SD/AZ/GPIO/RTC/MISC

FT3 REV 0.51

RP13

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

Must connected to 10 ms RC delay circuit on +1.8-V S5 power rail.

D3

1 2

RB751V-40TE17_SOD323-2

D5

1 2

RB751V-40TE17_SOD323-2

RP9

@RP9

@

1 8 2 7 3 6 4 5

1K_0804_8P4R_5%

RP10

@RP10

@

1 8 2 7 3 6 4 5

15K_0804_8P4R_5%

B

15K_0804_8P4R_5%

HDA_RST# HDA_SYNC HDA_BITCLK HDA_SDOUT

EC_RSMRST#_R

PWR_GOOD_APU

1U_0402_6.3V6K

+3VALW

SD_PWR_CTRL

SD_CLK/GPIO73

SD_CMD/GPIO74

SD_CD/GPIO75

SD_WP/GPIO76

SD_DATA0/GPIO77

SD_DATA1/GPIO78

SD_DATA2/GPIO79

SD_DATA3/GPIO80

SD_LED/GPIO45

SCL0/GPIO43

SDA0/GPIO47

SCL1/GPIO227

SDA1/GPIO228

GPIO49

GPIO50

GPIO51

GPIO55

GPIO57

GPIO58

GPIO59

GPIO64

SPKR/GPIO66

GPIO68

GPIO69

GPIO70

GPIO71

GPIO174

GEVENT2_L

GEVENT4_L

GEVENT7_L

GEVENT10_L

GEVENT11_L

GEVENT17_L

BLINK/GEVENT18_L

GEVENT22_L

GENINT1_L/GPIO32

GENINT2_L/GPIO33

FANOUT0/GPIO52

FANIN0/GPIO56

RTCCLK

X4@

BA23 AY22

AY23 AY20 BA20

BA22 AY21 AY24 BA24

AY25

AU25 AV25

AY11 BA11

AP27 AY28 BA28 AV23 AP21 BA26 AV19 AY27 BA27 AU21 AY26 AV21 AM21 BA3

AV17 BA4 AR15 AP17 AP11 AN8 AU17 BA6

BA29 AP23

AV31 AU31

AV11

FT3_BGA769

C

APU_SCLK0 APU_SDATA0

1 2

R122 0_0402_5%@R122 0_040 2_5%@

1 2

R661 0_0402_5%@R661 0_040 2_5%@

APU_GPIO174

GEVENT2#

EC_LID_OUT#

VGA_PWRGD

APU_SCLK1 APU_SDATA1

APU_SCLK0 APU_SDATA0

Board_ID1

PXS_PWREN

EC_LID_OUT#

BT_DISABLE#

H_PROCHOT#

VGA_PWRGD

<26,8,9> <26,8,9>

<28>

<26>

RTC_CLK

APU_PCIE_RST#_BUF

BT_OFF#

WL_OFF# ODD_EN

PXS_RST# APU_SPKR PXS_PWREN

<28,34,4,40>

<39>

<28>

D

1 2

R907

R907 33_0402_5%

33_0402_5%

C912

150P_0402_50V8J

If use as SMBUS : Pulled-up to VDD_33(port0) , VDD_33_ALW(port1) with a resistor of: Qty: 1; Value: 2.2 KΩ; Tol: 5% If no use : Pulled-up to VDD_33(port0) , VDD_33_ALW(port1) with a resistor of:

<26>

Qty: 1; Value: 10 KΩ; Tol: 5%

<26> <23>

<10> <31> <12,28,39>

STRAPS OF APU

LPC_FRAME# LPC_CLK0_EC LPC_CLK1 GEVENT2_L

SPI ROM (

H

+1.8VALW

L

R345

47K_0402_5%

C209

R685

R685 10K_0402_5%

10K_0402_5%

1 2

<28,5>

LPC_FRAME#

<28,5>

1

1U_0402_6.3V6K

1U_0402_6.3V6K C212

C212

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/04/22 2015/04/22

LPC_CLK0_EC

<5>

LPC_CLK1

Compal Secret Data

Deciphered Date

DEFAULT)

LPC ROM

GEVENT2#

RTC_CLK

D

12

R902

R902 10K_0402_5%

10K_0402_5%

12

@

R903

R903 2K_0402_5%

2K_0402_5%

BOOT FAIL TIMER ENABLED

BOOT FAIL TIMER D (DEFAULT)

ISABLED

1

2

12

@

R904

R904 10K_0402_5%

10K_0402_5%

12

R926

R926 2K_0402_5%

2K_0402_5%

E

APU_PCIE_RST#

+3VS

12

R911

UMA@ R911

UMA@

10K_0402_5%

Board_ID1

0 PX5.5

1

Function

UMA

12

R912

PX@ R912

PX@

10K_0402_5%

32.768KMHz CRYSTAL

1

2

NORMAL POWR UP/RESET TIMING (DEFAULT)

FAST POWER U FOR SIMULATION

R949

R949 10K_0402_5%

10K_0402_5%

@

R950

2.2K_0402_5%

E

32K_X1

32K_X2

C686

C686 18P_0402_50V8J

18P_0402_50V8J

RTC_CLK

P/RESET TIMING

6 48Thursday, March 28, 2013

1 2

R914

R914 20M_0402_5%

20M_0402_5%

Y3

32.768KHZ_12.5P_1TJF125DP1A000D

1 2

1

C682

C682 22P_0402_50V8J

22P_0402_50V8J

2

CLKGEN ENABLE (DEFAULT)

CLKGEN DISABLED

12

R925

R925 10K_0402_5%

10K_0402_5%

12

@

R927

R927 2K_0402_5%

2K_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet of

.8V SPI ROM

1

3.3V SPI ROM (DEFAULT)

+3VALW

12

@

R928

R928 10K_0402_5%

10K_0402_5%

12

Compal Electronics, Inc.

FT3 GPIO/AZ/MISC

VAWGA/GB

R929

2.2K_0402_5%

12

<10,24,26>

1.0

A

B

C

D

E

CORE POWER OF APU

+APU_CORE

1 1

VDDCR_CPU

C179 1U_0402_6.3V6KC179 1U_0402_6.3V6K

C184 1U_0402_6.3V6KC184 1U_0402_6.3V6K

C186 1U_0402_6.3V6KC186 1U_0402_6.3V6K

C180 1U_0402_6.3V6KC180 1U_0402_6.3V6K

C181 1U_0402_6.3V6KC181 1U_0402_6.3V6K

C182 1U_0402_6.3V6K@C182 1U_0402_6.3V6K

1

2

C183 1U_0402_6.3V6KC183 1U_0402_6.3V6K

1

2

C187 1U_0402_6.3V6KC187 1U_0402_6.3V6K

1

2

C190 180P_0402_50V8JC190 180P_0402_50V8J

C188 1U_0402_6.3V6KC188 1U_0402_6.3V6K

C189 1U_0402_6.3V6KC189 1U_0402_6.3V6K

1

2

1

2

RTC OF APU

+RTCBATT_R

C166

0.22U_0402_10V6K

VDDBT_RTC_G

W=20mils

1

2

+RTCBATT

1 2

R93 10K_0402_5%R93 10K_0402_5%

12

CLRP1

J@CLRP1

J@

SHORT PADS

Need OPEN

for Clear CMOS

@

INTEGRATED GPU POWER OF APU +3VALW/+3VS OF APU

+APU_CORE_NB

2 2

+1.5V/+1.5VS OF APU

C924 10U_0603_6.3V6MC924 10U_0603_6.3V6M

+0.95VALW/+0.95VS OF APU

3 3

+0.95VS +0.95VS_APU_GFX

VDD_095

C934 10U_0603_6.3V6MC934 10U_0603_6.3V6M

C935 10U_0603_6.3V6MC935 10U_0603_6.3V6M

C198 1U_0402_6.3V6KC198 1U_0402_6.3V6K

1

2

4 4

VDD_095_USB3_DUAL

VDDCR_NB

C201 1U_0402_6.3V6KC201 1U_0402_6.3V6K

C202 1U_0402_6.3V6KC202 1U_0402_6.3V6K

C200 1U_0402_6.3V6KC200 1U_0402_6.3V6K

1

2

C194 1U_0402_6.3V6KC194 1U_0402_6.3V6K

C191 1U_0402_6.3V6KC191 1U_0402_6.3V6K

C192 1U_0402_6.3V6KC192 1U_0402_6.3V6K

C193 1U_0402_6.3V6KC193 1U_0402_6.3V6K

1

2

VDDIO_MEM_S

C923 0.1U_0402_16V7KC923 0.1U_0402_16V7K

C927 0.1U_0402_16V7KC927 0.1U_0402_16V7K

C928 0.1U_0402_16V7KC928 0.1U_0402_16V7K

C931 0.1U_0402_16V7KC931 0.1U_0402_16V7K

C932 0.1U_0402_16V7KC932 0.1U_0402_16V7K

C949 10U_0603_6.3V6M@C949 10U_0603_6.3V6M

C925 10U_0603_6.3V6MC925 10U_0603_6.3V6M

1

2

C926 0.1U_0402_16V7KC926 0.1U_0402_16V7K

1

2

1

2

@

C930 0.1U_0402_16V7KC930 0.1U_0402_16V7K

C929 0.1U_0402_16V7K@C929 0.1U_0402_16V7K

1

2

C211 180P_0402_50V8JC211 180P_0402_50V8J

1

2

@

VDD_095_GFX

L22

FBMA-L11-201209-121LMA50T_0805

C205 1U_0402_6.3V6KC205 1U_0402_6.3V6K

C206 1U_0402_6.3V6KC206 1U_0402_6.3V6K

C199 1U_0402_6.3V6K@C199 1U_0402_6.3V6K

C204 1U_0402_6.3V6K@C204 1U_0402_6.3V6K

1

2

@

FBMA-L11-201209-121LMA50T_0805

C213 180P_0402_50V8JC213 180P_0402_50V8J

C260 1U_0402_6.3V6KC260 1U_0402_6.3V6K

1

2

12

+0.95VALW +0.95VALW

C214 1U_0402_6.3V6KC214 1U_0402_6.3V6K

C216 1U_0402_6.3V6KC216 1U_0402_6.3V6K

C938 10U_0603_6.3V6MC938 10U_0603_6.3V6M

C937 10U_0603_6.3V6MC937 10U_0603_6.3V6M

1

2

C221 1U_0402_6.3V6K@C221 1U_0402_6.3V6K

C218 180P_0402_50V8JC218 180P_0402_50V8J

1

2

1

2

C220 1U_0402_6.3V6KC220 1U_0402_6.3V6K

@

VDD_095_ALW VDD_18_ALW

A

+3VS

C197 180P_0402_50V8JC197 180P_0402_50V8J

1

2

C257 180P_0402_50V8JC257 180P_0402_50V8J

C249 1U_0402_6.3V6KC249 1U_0402_6.3V6K

1

2

+3VALW_APU

C253 1U_0402_6.3V6KC253 1U_0402_6.3V6K

C252 1U_0402_6.3V6KC252 1U_0402_6.3V6K

1

2

@

R582 0_0603_5%

+1.5V +APU_CORE

VDD_33_ALWVDD_33

VDDIO_AZ_ALW

PLANE SPLIT

C230 180P_0402_50V8JC230 180P_0402_50V8J

C231 180P_0402_50V8JC231 180P_0402_50V8J

C207 180P_0402_50V8J@C207 180P_0402_50V8J

C208 180P_0402_50V8J@C208 180P_0402_50V8J

C210 180P_0402_50V8JC210 180P_0402_50V8J

1

2

1

2

@

(Could be S0 or S5 power rail)

+1.5VS+1.5V

C259 180P_0402_50V8JC259 180P_0402_50V8J

C258 180P_0402_50V8JC258 180P_0402_50V8J

1

2

C161 4.7U_0603_6.3V6KC161 4.7U_0603_6.3V6K

1

2

C232 180P_0402_50V8JC232 180P_0402_50V8J

C254 1U_0402_6.3V6KC254 1U_0402_6.3V6K

C256 1U_0402_6.3V6K@C256 1U_0402_6.3V6K

C255 1U_0402_6.3V6KC255 1U_0402_6.3V6K

1

2

@

+1.8VALW/+1.8VS OF APU

+1.8VS

C203 1U_0402_6.3V6KC203 1U_0402_6.3V6K

C936 10U_0603_6.3V6MC936 10U_0603_6.3V6M

1

2

C219 1U_0402_6.3V6KC219 1U_0402_6.3V6K

C222 1U_0402_6.3V6KC222 1U_0402_6.3V6K

C217 1U_0402_6.3V6K@C217 1U_0402_6.3V6K

1

2

C933 10U_0603_6.3V6MC933 10U_0603_6.3V6M

1

2

1

2

@

VDD_18

C236 1U_0402_6.3V6KC236 1U_0402_6.3V6K

C237 1U_0402_6.3V6KC237 1U_0402_6.3V6K

C238 1U_0402_6.3V6KC238 1U_0402_6.3V6K

C239 1U_0402_6.3V6KC239 1U_0402_6.3V6K

C240 1U_0402_6.3V6KC240 1U_0402_6.3V6K

1

2

+1.8VALW

C160 4.7U_0603_6.3V6KC160 4.7U_0603_6.3V6K

1

2

B

C233 180P_0402_50V8JC233 180P_0402_50V8J

1

2

+1.5VS

+1.8VALW

+3VALW_APU

C250 1U_0402_6.3V6KC250 1U_0402_6.3V6K

C244 1U_0402_6.3V6KC244 1U_0402_6.3V6K

1

2

C245 180P_0402_50V8JC245 180P_0402_50V8J

C246 1U_0402_6.3V6KC246 1U_0402_6.3V6K

C248 1U_0402_6.3V6KC248 1U_0402_6.3V6K

1

2

1

2

+0.95VALW

+RTCBATT_R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

+3VALW

12

UAPUF

POWER

J35

VDDIO_MEM_S_1

L32

VDDIO_MEM_S_2

L37

VDDIO_MEM_S_3

N35

VDDIO_MEM_S_4

R31

VDDIO_MEM_S_5

R37

VDDIO_MEM_S_6

U32

VDDIO_MEM_S_7

U35

VDDIO_MEM_S_8

W31

VDDIO_MEM_S_9

W32

VDDIO_MEM_S_10

W37

VDDIO_MEM_S_11

AA31

VDDIO_MEM_S_12

AA35

VDDIO_MEM_S_13

AC32

VDDIO_MEM_S_14

AC37

VDDIO_MEM_S_15

AE31

VDDIO_MEM_S_16

AE35

VDDIO_MEM_S_17

AG32

VDDIO_MEM_S_18

AG37

VDDIO_MEM_S_19

AJ35

VDDIO_MEM_S_20

AL32

VDDIO_MEM_S_21

AL37

VDDIO_MEM_S_22

AR35

VDDIO_MEM_S_23

AL10

VDDIO_AZ_ALW_1

AL11

VDDIO_AZ_ALW_2

B1

VDD_18_ALW_1

B2

VDD_18_ALW_2

AL13

VDD_33_ALW_1

AM13

VDD_33_ALW_2

AR5

VDD_095_USB3_DUAL_1

AU4

VDD_095_USB3_DUAL_2

AV7

VDD_095_USB3_DUAL_3

AW5

VDD_095_USB3_DUAL_4

AE11

VDD_095_ALW_1

AE13

VDD_095_ALW_2

AJ11

VDD_095_ALW_3

AJ13

VDD_095_ALW_4

AN4

VDDBT_RTC_G

2012/04/22 2015/04/22

POWER

FT3 REV 0.51

Compal Secret Data

L21

VDDCR_CPU_1

L23

VDDCR_CPU_2

L25

VDDCR_CPU_3

L27

VDDCR_CPU_4

L29

VDDCR_CPU_5

N21

VDDCR_CPU_6

N23

VDDCR_CPU_7

N27

VDDCR_CPU_8

R21

VDDCR_CPU_9

R23

VDDCR_CPU_10

R27

VDDCR_CPU_11

U21

VDDCR_CPU_12

U23

VDDCR_CPU_13

U27

VDDCR_CPU_14

W21

VDDCR_CPU_15

W23

VDDCR_CPU_16

W27

VDDCR_CPU_17

AA21

VDDCR_CPU_18

AA23

VDDCR_CPU_19

AA27

VDDCR_CPU_20

AC21

VDDCR_CPU_21

AC23

VDDCR_CPU_22

AC27

VDDCR_CPU_23

AE21

VDDCR_CPU_24

AE23

VDDCR_CPU_25

AE27

VDDCR_CPU_26

L13

VDDCR_NB_1

L17

VDDCR_NB_2

N11

VDDCR_NB_3

N13

VDDCR_NB_4

N17

VDDCR_NB_5

R11

VDDCR_NB_6

R13

VDDCR_NB_7

R17

VDDCR_NB_8

U13

VDDCR_NB_9

U17

VDDCR_NB_10

W13

VDDCR_NB_11

W17

VDDCR_NB_12

AA13

VDDCR_NB_13

AA17

VDDCR_NB_14

AC13

VDDCR_NB_15

AC17

VDDCR_NB_16

AE15

VDDCR_NB_17

AE17

VDDCR_NB_18

AE19

VDDCR_NB_19

AG17

VDDCR_NB_20

AG21

VDDCR_NB_21

A2

VDD_18_1

A3

VDD_18_2

B3

VDD_18_3

C3

VDD_18_4

AM15

VDD_33_1

AM17

VDD_33_2

AG23

VDD_095_1

AG27

VDD_095_2

AJ21

VDD_095_3

AJ27

VDD_095_4

AL21

VDD_095_5

AL23

VDD_095_6

AL27

VDD_095_7

AM23

VDD_095_8

AM25

VDD_095_9

U10

VDD_095_GFX_1

W10

VDD_095_GFX_2

AA10

VDD_095_GFX_3

X4@

FT3_BGA769

Deciphered Date

+APU_CORE_NB

+1.8VS

+3VS

+0.95VS

+0.95VS_APU_GFX

D

UAPUH

UAPUG

GND

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSS_13

VSS_14

VSS_15

VSS_16

VSS_17

VSS_18

VSS_19

VSS_20

VSS_21

VSS_22

VSS_23

VSS_24

VSS_25

VSS_26

VSS_27

VSS_28

VSS_29

VSS_30

VSS_31

VSS_32

VSS_33

VSS_34

VSS_35

VSS_36

VSS_37

VSS_38

VSS_39

VSS_40

VSS_41

VSS_42

VSS_43

VSS_44

VSS_45

VSS_46

VSS_47

VSS_48

VSS_49

VSS_50

VSS_51

VSS_52

VSS_53

VSS_54

VSS_55

VSS_56

VSS_57

VSS_58

VSS_59

VSS_60

VSS_61

VSS_62

GND

FT3 REV 0.51

J3

VSS_63

J7

VSS_64

J8

VSS_65

J39

VSS_66

K11

VSS_67

K13

VSS_68

K17

VSS_69

K19

VSS_70

K21

VSS_71

K23

VSS_72

K25

VSS_73

K27

VSS_74

K29

VSS_75

K31

VSS_76

L3

VSS_77

L7

VSS_78

L8

VSS_79

L10

VSS_80

L11

VSS_81

L15

VSS_82

L19

VSS_83

L31

VSS_84

L39

VSS_85

L41

VSS_86

M1

VSS_87

M2

VSS_88

N3

VSS_89

N7

VSS_90

N15

VSS_91

N19

VSS_92

N25

VSS_93

N29

VSS_94

N31

VSS_95

N39

VSS_96

P1

VSS_97

P2

VSS_98

R3

VSS_99

R7

VSS_100

R15

VSS_101

R19

VSS_102

R25

VSS_103

R29

VSS_104

R39

VSS_105

R41

VSS_106

U1

VSS_107

U2

VSS_108

U3

VSS_109

U7

VSS_110

U8

VSS_111

U11

VSS_112

U15

VSS_113

U19

VSS_114

U25

VSS_115

U29

VSS_116

U31

VSS_117

U39

VSS_118

W3

VSS_119

W5

VSS_120

W11

VSS_121

W15

VSS_122

W19

VSS_123

W25

VSS_124

X4@

FT3_BGA769

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

W29 W39 W41

Y1

Y2 AA3 AA7 AA8

AA11 AA15 AA19 AA25 AA29 AA39

AC3 AC7

AC11 AC15 AC19 AC25 AC29 AC31 AC39 AC41

AE3 AE7

AE25 AE29 AE32 AE39

AG3 AG5

AG10 AG11 AG13 AG15 AG19 AG25 AG29 AG31 AG39 AG41

AH1 AH2

AJ3

AJ7 AJ15 AJ17 AJ19 AJ23 AJ25 AJ29 AJ31 AJ32 AJ39

AL3

AL8 AL15 AL17 AL19 AL25 AL29

Compal Electronics, Inc.

FT3 PW R/GND

VAWGA/GB

A8 A13 A23 A31 A35 A39

B8 B13 B23 B31 B39

C1

C2

C5

C7

C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C33 C35 C37 C39 C41

D9 D11 D13

E3

E4

E9 E11 E13 E27 E31 E35 E38 E39

G3

G7 G11 G13 G15 G17 G21 G25 G29 G35 G37 G39 G41 H11 H13 H23 H31

VSS_125

VSS_126

VSS_127

VSS_128

VSS_129

VSS_130

VSS_131

VSS_132

VSS_133

VSS_134

VSS_135

VSS_136

VSS_137

VSS_138

VSS_139

VSS_140

VSS_141

VSS_142

VSS_143

VSS_144

VSS_145

VSS_146

VSS_147

VSS_148

VSS_149

VSS_150

VSS_151

VSS_152

VSS_153

VSS_154

VSS_155

VSS_156

VSS_157

VSS_158

VSS_159

VSS_160

VSS_161

VSS_162

VSS_163

VSS_164

VSS_165

VSS_166

VSS_167

VSS_168

VSS_169

VSS_170

VSS_171

VSS_172

VSS_173

VSS_174

VSS_175

VSS_176

VSS_177

VSS_178

VSS_179

VSS_180

VSS_181

VSS_182

VSS_183

VSS_184

VSS_185

VSS_186

GND

FT3 REV 0.51

E

VSS_187

VSS_188

VSS_189

VSS_190

VSS_191

VSS_192

VSS_193

VSS_194

VSS_195

VSS_196

VSS_197

VSS_198

VSS_199

VSS_200

VSS_201

VSS_202

VSS_203

VSS_204

VSS_205

VSS_206

VSS_207

VSS_208

VSS_209

VSS_210

VSS_211

VSS_212

VSS_213

VSS_214

VSS_215

VSS_216

VSS_217

VSS_218

VSS_219

VSS_220

VSS_221

VSS_222

VSS_223

VSS_224

VSS_225

VSS_226

VSS_227

VSS_228

VSS_229

VSS_230

VSS_231

VSS_232

VSS_233

VSS_234

VSS_235

VSS_236

VSS_237

VSS_238

VSS_239

VSS_240

VSS_241

VSS_242

VSSBG_DAC

VBURN

X4@

7 48Thursday, March 28, 2013

PSEN

FT3_BGA769

of

AL39 AL41 AM11 AM27 AM31 AN3 AN7 AN39 AP31 AR3 AR13 AR17 AR21 AR25 AR29 AR39 AR41 AU1 AU2 AU3 AU15 AU19 AU23 AU27 AU39 AV9 AW3 AW7 AW13 AW15 AW17 AW19 AW21 AW23 AW25 AW27 AW31 AW33 AW35 AW37 AW39 AW41 AY13 AY15 AY18 AY30 BA2 BA7 BA13 BA15 BA18 BA21 BA25 BA31 BA35 BA39 A15 AL31 AM29

1.0

A

B

C

D

E

+1.5V +1.5V+VREF_DQ

2

1

C176

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1000P_0402_50V7K

1 1

<4,9> <4,9>

<4>

2 2

3 3

4 4

<4,9>

<4> <4>

<4,9>

<4,9> <4,9>

<4>

<4,9> <4,9>

C135

2.2U_0603_6.3V6K

+3VS

1

2

1000P_0402_50V7K

DDRAB_SDQS1# DDRAB_SDQS1

DDRAB_SDQS2# DDRAB_SDQS2

DDRA_CKE0

DDRAB_SBS2#

DDRA_CLK0 DDRA_CLK0#

DDRAB_SBS0#

DDRAB_SWE#

DDRAB_SCAS#

DDRA_SCS1#

DDRAB_SDQS4# DDRAB_SDQS4

DDRAB_SDQS6# DDRAB_SDQS6

1

C136

0.1U_0402_16V4Z

2

A

DDRAB_SDQ0 DDRAB_SDQ1

C142

DDRAB_SDM0

DDRAB_SDQ2 DDRAB_SDQ3

DDRAB_SDQ8 DDRAB_SDQ9

DDRAB_SDQS1# DDRAB_SDQS1

DDRAB_SDQ10 DDRAB_SDQ11

DDRAB_SDQ16 DDRAB_SDQ17

DDRAB_SDQS2# DDRAB_SDQS2

DDRAB_SDQ18 DDRAB_SDQ19

DDRAB_SDQ24 DDRAB_SDQ25

DDRAB_SDM3

DDRAB_SDQ26 DDRAB_SDQ27

DDRA_CKE0

DDRAB_SBS2#

DDRAB_SMA12 DDRAB_SMA9

DDRAB_SMA8 DDRAB_SMA5

DDRAB_SMA3 DDRAB_SMA1

DDRA_CLK0 DDRA_CLK0#

DDRAB_SMA10 DDRAB_SBS0#

DDRAB_SWE# DDRAB_SCAS# DDRA_ODT0

DDRAB_SMA13 DDRA_SCS1#

DDRAB_SDQ32 DDRAB_SDQ33

DDRAB_SDQS4# DDRAB_SDQS4

DDRAB_SDQ34 DDRAB_SDQ35

DDRAB_SDQ40 DDRAB_SDQ41

DDRAB_SDM5

DDRAB_SDQ42 DDRAB_SDQ43

DDRAB_SDQ48 DDRAB_SDQ49

DDRAB_SDQS6# DDRAB_SDQS6

DDRAB_SDQ50 DDRAB_SDQ51

DDRAB_SDQ56 DDRAB_SDQ57

DDRAB_SDM7

DDRAB_SDQ58 DDRAB_SDQ59

R69 10K_0402_5%R69 10K_0402_5%

+3VS

1 2

12

R70

10K_0402_5%

JDIMM1

15mil

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

VREF_CA VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0

EVENT# VDDSPD SA1 VTT1

G1

FOX_AS0A626-U8SN-7F

ME@

DIMM_A H:8mm

<Address: 00>

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

SDA SCL

VTT2

2 4

DDRAB_SDQ4

6

DDRAB_SDQ5

8 10

DDRAB_SDQS0#

12

DDRAB_SDQS0

14 16

DDRAB_SDQ6

18

DDRAB_SDQ7

20 22

DDRAB_SDQ12

24

DDRAB_SDQ13

26 28

DDRAB_SDM1

30

MEM_MAB_RST#

32 34

DDRAB_SDQ14

36

DDRAB_SDQ15

38 40

DDRAB_SDQ20

42

DDRAB_SDQ21

44 46

DDRAB_SDM2

48 50

DDRAB_SDQ22

52

DDRAB_SDQ23

54 56

DDRAB_SDQ28

58

DDRAB_SDQ29

60 62

DDRAB_SDQS3#

64

DDRAB_SDQS3

66 68

DDRAB_SDQ30

70

DDRAB_SDQ31

72

74 76 78

A15

80

A14

82 84

A11

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102 104 106 108 110 112 114

S0#

116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

G2

B

DDRA_CKE1

DDRAB_SMA15 DDRAB_SMA14

DDRAB_SMA11 DDRAB_SMA7

DDRAB_SMA6 DDRAB_SMA4

DDRAB_SMA2 DDRAB_SMA0

DDRA_CLK1 DDRA_CLK1#

DDRAB_SBS1# DDRAB_SRAS#

DDRA_SCS0#

DDRA_ODT1

15mil

DDRAB_SDQ36 DDRAB_SDQ37

DDRAB_SDM4

DDRAB_SDQ38 DDRAB_SDQ39

DDRAB_SDQ44 DDRAB_SDQ45

DDRAB_SDQS5# DDRAB_SDQS5

DDRAB_SDQ46 DDRAB_SDQ47

DDRAB_SDQ52 DDRAB_SDQ53

DDRAB_SDM6

DDRAB_SDQ54 DDRAB_SDQ55

DDRAB_SDQ60 DDRAB_SDQ61

DDRAB_SDQS7# DDRAB_SDQS7

DDRAB_SDQ62 DDRAB_SDQ63

MEM_MAB_EVENT#

+0.75VS

DDRAB_SDQS0# DDRAB_SDQS0

MEM_MAB_RST#

DDRAB_SDQS3# DDRAB_SDQS3

DDRA_CKE1

DDRA_CLK1 DDRA_CLK1#

DDRAB_SBS1# DDRAB_SRAS#

DDRA_SCS0# DDRA_ODT0

DDRA_ODT1

1000P_0402_50V7K

DDRAB_SDQS5# DDRAB_SDQS5

DDRAB_SDQS7# DDRAB_SDQS7

MEM_MAB_EVENT# <4,9>

APU_SDATA0 APU_SCLK0

<4,9> <4,9>

<4,9>

<4,9> <4,9>

<4>

<4> <4>

<4,9> <4,9>

<4> <4>

<4>

+VREF_CA

1

2

C134

C167

2

C167

1

0.1U_0402_16V4Z

<4,9> <4,9>

<26,6,9> <26,6,9>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

DDRAB_SDQ[0..63]

DDRAB_SDM[0..7]

DDRAB_SMA[0..15]

DDRAB_SDQ[0..63]

DDRAB_SDM[0..7] <4,9>

DDRAB_SMA[0..15] <4,9>

+1.5V/+0.75VS OF DIMM1

+1.5V +0.75VS

C115 0.1U_0402_16V4ZC115 0.1U_0402_16V4Z

C116 0.1U_0402_16V4Z@C116 0.1U_0402_16V4Z

C114 0.1U_0402_16V4Z@C114 0.1U_0402_16V4Z

1

2

@

C120 0.1U_0402_16V4Z@C120 0.1U_0402_16V4Z

C121 0.1U_0402_16V4Z@C121 0.1U_0402_16V4Z

C117 0.1U_0402_16V4ZC117 0.1U_0402_16V4Z

C118 0.1U_0402_16V4ZC118 0.1U_0402_16V4Z

1

2

C122 0.1U_0402_16V4ZC122 0.1U_0402_16V4Z

C119 0.1U_0402_16V4Z@C119 0.1U_0402_16V4Z

1

2

@

VREF for DIMM1,2

+VREF_DQ

Compal Secret Data

2012/04/22 2015/04/22

C

Compal Secret Data

Deciphered Date

<4,9>

C123 0.1U_0402_16V4Z@C123 0.1U_0402_16V4Z

1

2

@

+1.5V +1.5V

1 2

R65

R65 20K_0402_1%

20K_0402_1%

R67

R67 20K_0402_1%

20K_0402_1%

C126 0.1U_0402_16V4ZC126 0.1U_0402_16V4Z

C127 4.7U_0603_6.3V6KC127 4.7U_0603_6.3V6K

1

2

+VREF_CA

D

R66

R66 1K_0402_1%

1K_0402_1%

1 2

R68

R68 1K_0402_1%

1K_0402_1%

1 2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DDR3 SODIMM-I Socket

VAWGA/GB

8 48Thursday, March 28, 2013

E

1.0

A

B

C

D

E

+VREF_DQ

15mil

DDRAB_SDQ0

2

1

C177

C143

2

1000P_0402_50V7K

DDRAB_SDQS1# DDRAB_SDQS1

DDRAB_SDQS2# DDRAB_SDQS2

DDRB_CKE0

DDRAB_SBS2#

DDRB_CLK0 DDRB_CLK0#

DDRAB_SBS0#

DDRAB_SWE#

DDRAB_SCAS#

DDRB_SCS1#

DDRAB_SDQS4# DDRAB_SDQS4

DDRAB_SDQS6# DDRAB_SDQS6

C143

+3VS

1

0.1U_0402_16V4Z

<4,8> <4,8>

<4>

<4,8>

<4> <4>

<4,8>

<4,8> <4,8>

<4>

<4,8> <4,8>

0.1U_0402_16V4Z

1 1

2 2

3 3

4 4

DDRAB_SDQ1

DDRAB_SDM0

DDRAB_SDQ2 DDRAB_SDQ3

DDRAB_SDQ8 DDRAB_SDQ9

DDRAB_SDQS1# DDRAB_SDQS1

DDRAB_SDQ10 DDRAB_SDQ11

DDRAB_SDQ16 DDRAB_SDQ17

DDRAB_SDQS2# DDRAB_SDQS2

DDRAB_SDQ18 DDRAB_SDQ19

DDRAB_SDQ24 DDRAB_SDQ25

DDRAB_SDM3

DDRAB_SDQ26 DDRAB_SDQ27

DDRB_CKE0

DDRAB_SBS2#

DDRAB_SMA12 DDRAB_SMA9

DDRAB_SMA8 DDRAB_SMA5

DDRAB_SMA3 DDRAB_SMA1

DDRB_CLK0 DDRB_CLK0#

DDRAB_SMA10 DDRAB_SBS0#

DDRAB_SWE#

DDRAB_SMA13 DDRB_SCS1#

DDRAB_SDQ32 DDRAB_SDQ33

DDRAB_SDQS4# DDRAB_SDQS4

DDRAB_SDQ34 DDRAB_SDQ35

DDRAB_SDQ40 DDRAB_SDQ41

DDRAB_SDM5

DDRAB_SDQ42 DDRAB_SDQ43

DDRAB_SDQ48 DDRAB_SDQ49

DDRAB_SDQS6# DDRAB_SDQS6

DDRAB_SDQ50 DDRAB_SDQ51

DDRAB_SDQ56 DDRAB_SDQ57

DDRAB_SDM7

DDRAB_SDQ58 DDRAB_SDQ59

R71 10K_0402_5%R71 10K_0402_5%

1 2

R72 10K_0402_5%R72 10K_0402_5%

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4SN-7F

E@

M

VSS3

DQS#0

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45 VSS35 DQS#5

DQS5

VSS38

DQ46

DQ47 VSS40

DQ52

DQ53 VSS42

VSS43

DQ54

DQ55 VSS45

DQ60

DQ61 VSS47 DQS#7

DQS7

VSS50

DQ62

DQ63 VSS52

EVENT#

VTT2

DQ4 DQ5

DQ6 DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA SCL

A15 A14

A11

S0#

+1.5V+1.5V

2 4

DDRAB_SDQ4

6

DDRAB_SDQ5

8 10

DDRAB_SDQS0#

12

DDRAB_SDQS0

14 16

DDRAB_SDQ6

18

DDRAB_SDQ7

20 22

DDRAB_SDQ12

24

DDRAB_SDQ13

26 28

DDRAB_SDM1

30

MEM_MAB_RST#

32 34

DDRAB_SDQ14

36

DDRAB_SDQ15

38 40

DDRAB_SDQ20

42

DDRAB_SDQ21

44 46

DDRAB_SDM2

48 50

DDRAB_SDQ22

52

DDRAB_SDQ23

54 56

DDRAB_SDQ28

58

DDRAB_SDQ29

60 62

DDRAB_SDQS3#

64

DDRAB_SDQS3

66 68

DDRAB_SDQ30

70

DDRAB_SDQ31

72

74 76 78 80 82 84 86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

G2

DDRB_CKE1

DDRAB_SMA15 DDRAB_SMA14

DDRAB_SMA11 DDRAB_SMA7

DDRAB_SMA6 DDRAB_SMA4

DDRAB_SMA2 DDRAB_SMA0

DDRB_CLK1 DDRB_CLK1#

DDRAB_SBS1# DDRAB_SRAS#

DDRB_SCS0# DDRB_ODT0DDRAB_SCAS#

DDRB_ODT1

15mil

DDRAB_SDQ36 DDRAB_SDQ37

DDRAB_SDM4

DDRAB_SDQ38 DDRAB_SDQ39

DDRAB_SDQ44 DDRAB_SDQ45

DDRAB_SDQS5# DDRAB_SDQS5

DDRAB_SDQ46 DDRAB_SDQ47

DDRAB_SDQ52 DDRAB_SDQ53

DDRAB_SDM6

DDRAB_SDQ54 DDRAB_SDQ55

DDRAB_SDQ60 DDRAB_SDQ61

DDRAB_SDQS7# DDRAB_SDQS7

DDRAB_SDQ62 DDRAB_SDQ63

MEM_MAB_EVENT#

+0.75VS

DDRAB_SDQS0# DDRAB_SDQS0

MEM_MAB_RST#

DDRAB_SDQS3# DDRAB_SDQS3

DDRB_CKE1

DDRB_CLK1 DDRB_CLK1#

DDRAB_SBS1# DDRAB_SRAS#

DDRB_SCS0# DDRB_ODT0

DDRB_ODT1

1000P_0402_50V7K

DDRAB_SDQS5# DDRAB_SDQS5

DDRAB_SDQS7# DDRAB_SDQS7

MEM_MAB_EVENT# <4,8>

APU_SDATA0 APU_SCLK0

<4,8> <4,8>

<4,8>

<4,8> <4,8>

<4>

<4> <4>

<4,8> <4,8>

<4> <4>

<4>

+VREF_CA

1

2

C139

C174

2

1

0.1U_0402_16V4Z

<4,8> <4,8>

<26,6,8> <26,6,8>

DDRAB_SDQ[0..63]

DDRAB_SDM[0..7]

DDRAB_SMA[0..15]

DDRAB_SDQ[0..63]

DDRAB_SDM[0..7] <4,8>

DDRAB_SMA[0..15] <4,8>

<4,8>

+1.5V/+0.75VS OF DIMM2

C132 0.1U_0402_16V4ZC132 0.1U_0402_16V4Z

C133 0.1U_0402_16V4Z@C133 0.1U_0402_16V4Z

C162 0.1U_0402_16V4ZC162 0.1U_0402_16V4Z

C155 0.1U_0402_16V4ZC155 0.1U_0402_16V4Z

C165 0.1U_0402_16V4ZC165 0.1U_0402_16V4Z

C168 0.1U_0402_16V4Z@C168 0.1U_0402_16V4Z

C169 0.1U_0402_16V4Z@C169 0.1U_0402_16V4Z

C170 0.1U_0402_16V4ZC170 0.1U_0402_16V4Z

C171 0.1U_0402_16V4ZC171 0.1U_0402_16V4Z

1

2

@

C172 0.1U_0402_16V4Z@C172 0.1U_0402_16V4Z

1

2

@

+1.5V+1.5V +0.75VS

C158 4.7U_0603_6.3V6KC158 4.7U_0603_6.3V6K

C175 0.1U_0402_16V4ZC175 0.1U_0402_16V4Z

1

2

1

+

C644

2

220U_6.3V_M

Security Classification

Issued Date

DIMM_B H:4mm

<Address: 10>

A

B

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/04/22 2015/04/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DDR3 SODIMM-II Socket

VAWGA/GB

9 48Thursday, March 28, 2013

E

1.0

A

UV1A

1 1

2 2

3 3

<5>

PCIE_ATX_C_GRX_P0

<5>

PCIE_ATX_C_GRX_N0

<5>

PCIE_ATX_C_GRX_P1

<5>

PCIE_ATX_C_GRX_N1

<5>

PCIE_ATX_C_GRX_P2

<5>

PCIE_ATX_C_GRX_N2

<5>

PCIE_ATX_C_GRX_P3

<5>

PCIE_ATX_C_GRX_N3

<5>

CLK_PEG_VGA

<5>

CLK_PEG_VGA#

CLK_PEG_VGA CLK_PEG_VGA#

PX@

RV2 1K_0402_5%

GPU_RST#

12

PX@

RV4

RV4 100K_0402_5%

100K_0402_5%

AA38

W36

W38

M37

M35

G36

G38

AB35 AA36

AH16

AA30

Y37

Y35

V37

V35 U36

U38 T37

T35 R36

R38 P37

P35 N36

N38

L36

L38 K37

K35

J36

J38

H37

H35

F37

F35 E37

PCIE_RX0P PCIE_RX0N

PCIE_RX1P PCIE_RX1N

PCIE_RX2P PCIE_RX2N

PCIE_RX3P PCIE_RX3N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P PCIE_RX5N

PCIE_RX6P PCIE_RX6N

PCIE_RX7P PCIE_RX7N

NC NC

CLOCK

PCIE_REFCLKP PCIE_REFCLKN

TEST_PG

PERSTB

MARS@

B

PART 1 0F 9

PCI EXPRESS INTERFACE

MARS-XT M2_FCBGA962

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

NC NC

Y33

PCIE_GTX_ARX_P0

Y32

PCIE_GTX_ARX_N0

W33

PCIE_GTX_ARX_P1

W32

PCIE_GTX_ARX_N1

U33

PCIE_GTX_ARX_P2

U32

PCIE_GTX_ARX_N2

U30

PCIE_GTX_ARX_P3

U29

PCIE_GTX_ARX_N3

T33 T32

T30 T29

P33 P32

P30 P29

N33 N32

N30 N29

L33 L32

L30 L29

K33 K32

J33 J32

K30 K29

H33 H32

Y30

RV1 1.69K_0402_1%PX@RV1 1.69K_0402_1%PX@

Y29

RV3 1K_0402_1%PX@RV3 1K_0402_1%PX@

1 2

CV1 0.1U_0402_16V7KPX@CV1 0.1U_0402_16V7KPX@ CV2 0.1U_0402_16V7KPX@CV2 0.1U_0402_16V7KPX@

CV3 0.1U_0402_16V7KPX@CV3 0.1U_0402_16V7KPX@ CV4 0.1U_0402_16V7KPX@CV4 0.1U_0402_16V7KPX@

CV5 0.1U_0402_16V7KPX@CV5 0.1U_0402_16V7KPX@ CV6 0.1U_0402_16V7KPX@CV6 0.1U_0402_16V7KPX@

CV7 0.1U_0402_16V7KPX@CV7 0.1U_0402_16V7KPX@ CV8 0.1U_0402_16V7KPX@CV8 0.1U_0402_16V7KPX@

C

1 2 1 2

+0.95VGS

D

<6>

<24,26,6>

<5> <5>

PXS_RST#

APU_PCIE_RST#

PCIE_GTX_C_ARX_P0 PCIE_GTX_C_ARX_N0

PCIE_GTX_C_ARX_P1 PCIE_GTX_C_ARX_N1

PCIE_GTX_C_ARX_P2 PCIE_GTX_C_ARX_N2

PCIE_GTX_C_ARX_P3 PCIE_GTX_C_ARX_N3

UV1

SUN@

UV1

SUN@

S IC 216-0841000-00 A0 SUN PRO M2 FCBGA 962P C38

SA00006BA20

LVDS Interface

UV1D

PART 7 0F 9

RSVD/VARY_BL

RSVD/DIGON

LVDS CONTROL

TXCBP_DPB3P TXCBM_DPB3N

TX3P_DPB2P

TX3M_DPB2N

TX4P_DPB1P

TX4M_DPB1N

TX5P_DPB0P

TX5M_DPB0N

NC#AF35 NC#AG36

LVTMDP

TXCAP_DPA3P TXCAM_DPA3N

TX0P_DPA2P

TX0M_DPA2N

TX1P_DPA1P

TX1M_DPA1N

TX2P_DPA0P

TX2M_DPA0N

NC NC

MARS-XT M2_FCBGA962

MARS@

+3VGS

5

2

P

B

4

Y

1

A

G

PX@

UV2

3

MC74VHC1G08DFT2G SC70 5P

AK27 AJ27

AK35 AL36

AJ38 AK37

AH35 AJ36

AG38 AH37

AF35 AG36

AP34 AR34

AW37 AU35

AR37 AU39

AP35 AR35

AN36 AP37

GPU_RST#

E

SUN NC

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/07/03 2013/07/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

ATI_MarsXTX_M2_PCIE/LVDS

VAWGA/GB

10 48Monday, April 01, 2013

E

1.0

A

UV1B

MUTI GFX

+VREFG_GPU

PX_EN

TESTEN

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

THERM_D+ THERM_DGPIO_28_FDO

+TSVDD

1

CV32

2

0.1U_0402_16V4Z

PX@ CV32

PX@

AD29 AC29

AJ21 AK21

AW8

AW3

AW5

AW6

AR10

AW10

AU10 AP10 AV11 AT11 AR12

AW12

AU12 AP12

AJ23 AH23

AK26 AJ26

AH20 AH18 AN16

AH17 AJ17 AK17 AJ13 AH15 AJ16 AK16 AL16 AM16 AM14 AM13 AK14 AG30 AN14 AM17 AL13 AJ14 AK13 AN13

AG32 AG33

AJ19 AK19 AJ20 AK20 AJ24 AH26 AH24

AC30

AK24

AH13

AL21

AD28

AM23 AN23 AK23 AL24 AM24

AF29 AG29

AK32

AL31

AJ32 AJ33

AR8 AU8 AP8

AR3 AR1 AU1 AU3

AP6

AU5 AR6

AU6 AT7 AV7 AN7 AV9 AT9

GENLK_CLK GENLK_VSYNC

SWAPLOCKA SWAPLOCKB

NC NC DBG_CNTL0 NC NC NC DBG_DATA0 DBG_DATA1 DBG_DATA2 DBG_DATA3 DBG_DATA4 DBG_DATA5 DBG_DATA6 DBG_DATA7 DBG_DATA8 DBG_DATA9 DBG_DATA10 DBG_DATA11 DBG_DATA12 DBG_DATA13 DBG_DATA14 DBG_DATA15 DBG_DATA16 DBG_DATA17 DBG_DATA18 DBG_DATA19 DBG_DATA20 DBG_DATA21 DBG_DATA22 DBG_DATA23

SMBCLK

SMBus

SMBDATA

SCL

I2C

SDA

GENERAL PURPOSE I/O

GPIO_0 GPIO_1 GPIO_2

GPIO_5_AC_BATT GPIO_6_TACH GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16 GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21 GPIO_22_ROMCSB CLKREQB

GPIO_29 GPIO_30

GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 GENERICF_HPD5 GENERICG_HPD6

CEC_1

HPD1

DBG_VREFG

BACO

PX_EN

DEBUG

TESTEN

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

THERMAL

DPLUS DMINUS

GPIO_28_FDO

TS_A

TSVDD TSVSS

MARS@

GENLK_CLK

T1T1

GENLK_VSYNC

T2T2

1 1

VGA_SMB_CK2 VGA_SMB_DA2

2 2

3 3

4 4

<39>

GPU_GPIO0

<28,35> <39>

<39>

<6>

<39> <39>

+1.8VGS

PX@

RV13 499_0402_1%

PX@

RV14 249_0402_1%

CV23

PX@

GPIO_28_FDO

H

L

<29>

REMOTE1+

<29>

REMOTE1-

TSVDD MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

VGA_CLKREQ#

12

0.1U_0402_16V7K

MLPS

Disable

Enable

1 2

LV3 0_0402_5%@LV3 0_0402_5%@

ACIN

GPU_VID5

GPU_VID1

GPU_VID2

GPU_VID3 GPU_VID4

+VREFG_GPU

+3VGS

RV16 0_0402_5%@RV16 0_0402_5%@ RV17 0_0402_5%@RV17 0_0402_5%@

+3VGS

A

DV1

DV1 RB751V_SOD323 @

RB751V_SOD323 @

1 2 1 2

+TSVDD+1.8VGS

RV12 10K_0402_5%@ RV12 10K_0402_5%@

0.60 V level, Please VREFG Divider ans cap close to ASIC

T29T29

RV18 5.11K_0402_5%

RV19 1K_0402_5%

GPU_GPIO0

21

GPU_GPIO5 GPU_VID5

GPU_VID1

THM_ALERT#

1 2

GPU_VID2

VGA_CLKREQ#

GPU_VID3 GPU_VID4

1 2

@

1 2

PX@

T11T11

1 2

@

RV26 10K_0402_5%

1 2

PX@

RV31 10K_0402_5%

(1.8V@13mA TSVDD)

1

CV31

CV30

2

1U_0402_6.3V6K

10U_0603_6.3V6M

PX@ CV31

PX@

PX@ CV30

PX@

PART 2 0F 9

B

DPA

DPB

DPC

DPD

DAC1

NC_SVI2 NC_SVI2 NC_SVI2

MLPS

DDC/AUX

DDC1CLK

DDC1DATA

DDC2CLK

DDC2DATA

DDCVGACLK

DDCVGADATA

MARS-XT M2_FCBGA962

B

AVSSN

HSYNC VSYNC

RSET

AVDD

AVSSQ

VDD1DI VSS1DI

PS_0

PS_1

PS_2

PS_3

AUX1P AUX1N

AUX2P AUX2N

C

AU24

NC

AV23

NC

AT25

NC

AR24

NC

AU26

NC

AV25

NC

AT27

NC

AR26

NC

AR30

NC

AT29

NC

AV31

NC

AU30

NC

AR32

NC

AT31

NC

AT33

NC

AU32

NC

AU14

NC

AV13

NC

AT15

NC

AR14

NC

AU16

NC

AV15

NC

AT17

NC

AR16

NC

AU20

NC

AT19

NC

AT21

NC

AR20

NC

AU22

NC

AV21

NC

AT23

NC

AR22

NC

AD39

VGA_R

R

AD37

AE36

VGA_G

G

AD35

AF37

VGA_B

B

AE38

AC36

HSYNC

AC38

VSYNC

AB34

RV11 499_0402_1%PX@RV11 499_0402_1%PX@

AD34

+AVDD

AE34

AC33

+VDD1DI

AC34

V13

NC

U13

NC

AF33

NC

AF32

NC

AA29

NC

AG21

NC

AC32

NC

AC31 AD30 AD32

AM34

PS_0

AD31

PS_1

AG31

PS_2

AD33

PS_3

AM26

VGA_CLK

AN26

VGA_DAT

AM27 AL27

AM19 AL19

AN20 AM20

AL30

NC

AM30

NC

AL29

NC

AM29

NC

AN21

NC

AM21

NC

AK30

NC

AK29

NC

AJ30 AJ31

T24T24

T25T25

T26T26

T4T4 T6T6

1 2

(1.8V@70mA AVDD)

(1.8V@117mA VDD1DI)

T27T27 T28T28

GPU_GPIO5

THM_ALERT#

JTAG_TRSTB JTAG_TDI JTAG_TMS

JTAG_TCK

+VDD1DI

1

CV20

2

@ CV20

@

0.1U_0402_16V7K

10K_0402_5%

VGA_SMB_CK2

VGA_SMB_DA2

1U_0402_6.3V6K

@

RV24

CV21

@ CV21

@

+AVDD

0.1U_0402_16V7K

1

2

+3VGS

STRAPS

RV5 100K_0402_5%@RV5 100K_0402_5%@

RV6 2.2K_0402_5%@RV6 2.2K_0402_5%@

RV7 10K_0402_5%@RV7 10K_0402_5%@ RV8 10K_0402_5%@RV8 10K_0402_5%@ RV9 10K_0402_5%@RV9 10K_0402_5%@

RV10 10K_0402_5%@RV10 10K_0402_5%@

1

CV18

CV17

2

@ CV18

@

@ CV17

@

1U_0402_6.3V6K

1

CV22

2

@ CV22

@

10U_0603_6.3V6M

12

@

RV25

RV25 10K_0402_5%

10K_0402_5%

DMN66D0LDW-7_SOT363-6

C

+3VGS

12

+3VGS

12 12 12

12

AVDD MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

1 2

LV1 0_0402_5%@LV1 0_0402_5%@

1

CV19

2

@ CV19

@

10U_0603_6.3V6M

1 2

LV2 0_0402_5%@LV2 0_0402_5%@

VDD1DI MarsCR B Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

+3VGS

2

61

5

QV3A

@QV3A

@

4

QV3B

@QV3B

DMN66D0LDW-7_SOT363-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

@

+1.8VGS

EC_SMB_CK2

3

EC_SMB_DA2

2012/07/03 2013/07/03

<28,29,4>

Compal Secret Data

D

CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

STRAPS

TX_PWRS_ENB

TX_DEEMPH_EN

BIF_GEN3_EN_A

BIF_VGA DIS

ROMIDCFG[2:0]

BIOS_ROM_EN PS_2[3]

AUD[1]

AUD[0]

CEC_DIS PS_0[4]

RESERVED PS_1[3]

RESERVED PS_1[2]

RESERVED NA

AUD_PORT_CONN_PINSTRAP[2] PS_3[5]

AUD_PORT_CONN_PINSTRAP[1] PS_3[4]

AUD_PORT_CONN_PINSTRAP[0] PS_0[5]

PS_1[4] 0:50% Tx output swing

PS_1[5] 0:Tx de-emphasis disabled

PS_1[1]

PS_2[4]

PS_0[3..1]

NA

DESCRIPTION OF DEFAULT SETTINGSMLPS

Transmitter Power Savings Enable

1:Full Tx output swing

PCIE Transmitter De-emphasis Enable

1:Tx de-emphasis enabled

PCIE Gen3 Enable (NOTE:RESERVED for Thames/Seymour and should be strapped to 0)

0:GEN3 not support at power-on 1:GEN3 supported at power-on

VGA control

0:VGA controller capacity enabled 1:VGA controller capacity disabled (for multi-GPU)

Serial ROM type or Memory Aperture Size Select

If PS_2[3]=0, defines memory aperture siz e If PS_2[3]=1, defines ROM type 100 - 512Kbit M25P05A (ST) 101 - 1Mbit M25P10A (ST) 101 - 2Mbit M25P20 (ST) 101 - 4Mbit M25P40 (ST) 101 - 8Mbit M25P80 (ST) 100 - 512Kbit Pm25LV010 (Chingis) 101 - 1Mbit Pm25LV010 (Chingis)

Enable external BIOS ROM device

0:Disabled 1:Enabled

00 - No audio function 01 - Audio for DP only 10 - Audio for DP and HDMI if dongle is detected 11 - Audio for both DP and HDMI

HDMI must only be enabled on systems that are legally entitled. It isthe responsibility of the system designer to ensure that the system is entitled to support this feature.

Reserved for future ASIC

NOTE:ALLOW FOR PULLUP PADS FOR THE RESERVED STRAPS BUT DO NOT INSTALL RESISTOR IF THESE GPIOS ARE USEED, THEY MUST KEEP LOW AND NOT CONFLICT DURING RESET

Reserved

Reserved (for Thames/Whistler/Seymour only)

STRAPS TO INDICATE THE NUMBER OF AUDIO CAPABLE DISPLAY OUTPUTS

111 = 0 usable endpoints 110 = 1 usable endpoints 101 = 2 usable endpoints 100 = 3 usable endpoints 011 = 4 usable endpoints 010 = 5 usable endpoints 001 = 6 usable endpoints 000 = all endpoints are usable

MLPS Strap

CapacitorBits[5:4]

Deciphered Date

D

PS_0[5:1]

PS_1[5:1]

PS_2[5:1]

PS_3[5:1]

PS_0 PS_1 PS_2 PS_3

@

CV26

0.01U_0402_25V7K

Bits[3:1]

0 0 1

1 1

0 1 0

0 1

0 0 0

0 0

1 1

X X X

@

PX@

1

CV27

2

@

PX@

CV29

1

CV28

2

0.01U_0402_25V7K

0.082U_0402_16V7K

1

2

0.68U_0402_10V6K

R_pu R_pd

NC

8.45K 2K

82 nF

4.53K

680 nF

NC

X

12

RV20

X76@ RV20

X76@

8.45K_0402_1%

4.75K_0402_1%

RV27

X76@ RV27

X76@

8.45K_0402_1%

12

4.75K_0402_1%

PX@RV28

PX@

Place CLOSE VGA CHIP

Title

ATI_MarsXTX_M2_Main_MSIC

Size Document Number Rev

C

Date: Sheet of

E

RECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR 1 = INSTALL 10K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE

2K

4.75K

Mapping to VRAM type please refer to page 45

X

12

RV21

@RV21

@

12

RV28

Compal Electronics, Inc.

PX@RV22

PX@

4.53K_0402_1%

PX@RV29

PX@

2K_0402_1%

VAWGA/GB

E

RV22

RV29

12

8.45K_0402_1%

12

PX@RV23

PX@

PX@RV30

PX@

2K_0402_1%

Default Setting

+1.8VGS

12

RV23

12

RV30

11 48Thursday, March 28, 2013

1

0

001 256MB

0

NC

1

0 1 NA NA

111

1.0

A

MPLL_PVDD MarsCRB Design

1 1

2 2

220ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

SPLL_PVDD MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

SPLL_VDDC MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

+1.8VGS

+0.95VGS

B

@

LV4

1 2

0_0603_5%

1 2

@

LV5

LV5 0_0402_5%

0_0402_5%

1 2

@

LV6

LV6 0_0402_5%

0_0402_5%

+MPV18

(MPLL_PVDD:1.8V@130mA )

1

CV34

CV33

2

1U_0402_6.3V6K

PX@ CV34

1U_0402_6.3V6K

PX@

PX@ CV33

PX@

0.1U_0402_16V7K

10U_0603_6.3V6M

+SPV18

(SPLL_PVDD:1.8V@75mA )

1

CV38

CV39

2

PX@ CV39

PX@

PX@ CV38

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

10U_0603_6.3V6M

+SPLL_VDDC

(SPLL_VDDC:0.95V@100mA )

1

CV43

CV44

2

PX@ CV44

PX@

PX@ CV43

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

10U_0603_6.3V6M

C

UV1C

PART 9 0F 9

AV33

XTALIN

1

CV35

2

PX@ CV35

PX@

AM10

AN9

AN10

AF30 AF31

H7 H8

MPLL_PVDD MPLL_PVDD

SPLL_PVDD

SPLL_VDDC

SPLL_PVSS

NC_XTAL_PVDD NC_XTAL_PVSS

MARS@

PLLS/XTAL

MARS-XT M2_FCBGA962

+MPV18

+SPV18

1

CV40

2

PX@ CV40

PX@

1

CV45

2

PX@ CV45

PX@

+SPLL_VDDC

XTALOUT

XO_IN

XO_IN2

CLKTESTA CLKTESTB

AU34

AW34

AW35

AK10 AL10

XTALIN

XTALOUT

D

12

@

CV41

0.1U_0402_16V7K

12

@

RV33

51.1_0402_1%

12

@

CV42

0.1U_0402_16V7K

12

@

RV34

51.1_0402_1%

CV36

PX@CV36

PX@

10P_0402_50V8J

1 2

RV32 1M_0402_5%

PX@

YV1

4

NC

OSC

1

XTALIN

1

2

OSC

PX@

NC

27MHZ 10PF +-20PPM X3G027000DA1H

E

3

XTALOUT

2

1

CV37

PX@CV37

PX@

10P_0402_50V8J

2

+3VS TO +3VGS

+5VALW

RV37

PX@RV37

PX@

20K_0402_5%

3 3

<28,39,6>

PXS_PWREN

20K_0402_5%

PXS_PWREN

2

G

+1.5V TO +1.5VGS

PX@

CV48

4.7U_0603_6.3V6K

B+

+3VALW

12

PX@

R286

100K_0402_5%

PXS_PWREN

R276

PX@ R 276

PX@

100K_0402_5%

5

12

A

34

PX@

QV157B

QV157B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

4 4

+3VS +3VGS

QV8

QV8 LP2301ALT1G_SOT23-3

LP2301ALT1G_SOT23-3

PX@

13

D

PX@

QV6

QV6 2N7002H_SOT23-3

2N7002H_SOT23-3

S

3 1

2

RV38

PX@RV38

PX@

20K_0402_5%

1

2

AO4430: Rdson: 5.5mohm @ VGS=10V

+1.5V +1.5VGS

360mil(9A) 360mil(9A)

1

2

RV41 240K_0402_5%

PX@

PXS_PWREN#

12

6

PX@

2

QV157A

QV157A DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

1

8 7 6 5

PX@

CV52

0.1U_0402_16V4Z

UV4

AO4304L_SO8

4

PX@

RV42 0_0402_5%

0_0402_5%

1 2

4.7U_0603_6.3V6K

PX@

1 2 3

@RV42

@

1

CV46

@

2

PXS_PWREN#

1

PX@

CV53

0.1U_0402_25V6

2

B

1U_0603_10V6K

1

CV47

2

D

S

PX@

1

CV49

4.7U_0603_6.3V6K

2

12

@

RV36

RV36 470_0603_5%

470_0603_5%

13

2

G

@

QV7

QV7 2N7002H_SOT23-3

2N7002H_SOT23-3

@

1

CV50

0.1U_0402_16V4Z

2

2N7002H_SOT23-3@G

2N7002H_SOT23-3

1 2

13

D

QV1

@

S

+1.8VALW TO +1.8VGS +0.95VALW TO +0.95VGS Load switch

+1.8VALW

C29

1

@

1U_0402_6.3V6K

2

RV39

@RV39

@

470_0603_5%

2

PXS_PWREN#

G

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/07/03 2013/07/03

VIN 1.8V and 0. 95V (VBIAS=5V) ,IMAX(per chann el)=6A,Rds=18m ohm

U1895V

PXS_PWREN

VL

PXS_PWREN

+0.95VALW

1

C30

@ C30

@

1U_0402_6.3V6K

2

Compal Secret Data

Deciphered Date

U1895V

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

TPS22966DPUR_SON14_2X3

PX@

D

VOUT1 VOUT1

GND

VOUT2 VOUT2

GPAD

14 13

12

CT1

11

10

CT2

9 8

15

+1.8VGS

J18VG

J@

C282200P_0402_50V7K

C272200P_0402_50V7K

1 2

PAD-OPEN 4x4m

+0.95VGS

J95VG

J@

PAD-OPEN 4x4m

VAWGA/GB

E

2

@ C31

@

1

C31

0.1U_0402_16V4Z

2

@ C32

@

1

C32

0.1U_0402_16V4Z

12 48Thursday, March 28, 2013

+1.8VGS_LS

1 2

PX@

1 2

PX@

+0.95VGS_LS

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

ATI_MarsXTX_M2_BACO POWER

1.0

A

UV1G

PART 6 0F 9

AB39

GND

E39

GND

F34

GND

F39

GND

G33

GND

G34

GND

H31

GND

H34

GND

H39

GND

J31

M34 M39

W31 W34

M17 M22 M24

GND

J34

GND

K31

GND

K34

GND

K39

GND

L31

GND

L34

GND GND GND

N31

GND

N34

GND

P31

GND

P34

GND

P39

GND

R34

GND

T31

GND

T34

GND

T39

GND

U31

GND

U34

GND

V34

GND

V39

GND GND GND

Y34

GND

Y39

GND

F15

GND

F17

GND

F19

GND

F21

GND

F23

GND

F25

GND

F27

GND

F29

GND

F31

GND

F33

GND

F7

GND

F9

GND

G2

GND

G6

GND

H9

GND

J2

GND

J27

GND

J6

GND

J8

GND

K14

GND

K7

GND

L11

GND

L17

GND

L2

GND

L22

GND

L24

GND

L6

GND GND GND GND

N16

GND

N18

GND

N2

GND

N21

GND

N23

GND

N26

GND

N6

GND

R15

GND

R17

GND

R2

GND

R20

GND

R22

GND

R24

GND

R27

GND

R6

GND

T11

GND

T13

GND

T16

GND

T18

GND

T21

GND

T23

GND

T26

GND

U15

GND

U17

GND

U2

GND

U20

GND

U22

GND

U24

GND

U27

GND

U6

GND

V11

GND

V16

GND

V18

GND

V21

GND

V23

GND

V26

GND

W2

GND

W6

GND

Y15

GND

Y17

GND

Y20

GND

Y22

GND

Y24

GND

Y27

GND

MARS@

GND

VSS_MECH VSS_MECH VSS_MECH

MARS-XT M2_FCBGA962

1 1

2 2

3 3

4 4

A

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

B

A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20

AG6 AG9 AH21 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20

AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13

AG22

NC

A39

MECH#1

AW1

MECH#2

AW39

MECH#3

B

DP_VDDR MarsCRB Design

0.1u 1 1 1u 1 1 10u 1 1

+1.8VGS

1 2

RV43 0_0402_5%@RV43 0_0402_5%@

TV12 PADTV12 PAD TV13 PADTV13 PAD TV14 PADTV14 PAD

+DP_VDDR

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

(DP_VDDR:1.8V@237mA/link )

+DP_VDDR

1

CV57

2

PX@ CV57

PX@

10U_0603_6.3V6M

RV44 150_0402_1%PX@RV44 150_0402_1%PX@

C

1

CV58

CV59

2

PX@ CV58

PX@

PX@ CV59

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

12

D

UV1F

AN24

NC

AP24

NC

AP25

NC

AP26

NC

AU28

NC

AV29

NC

AP20

NC

AP21

NC

AP22

NC

AP23

NC

AU18

NC

AV19

NC

AH34

DP_VDDR

AJ34

DP_VDDR

AF34

DP_VDDR

AG34

DP_VDDR

AM37

DP_VDDR

AL38

DP_VDDR

AM32

DP_VDDR

AW28

NC

AW18

NC

AM39

DP_CALR

MARS@

2012/07/03 2013/07/03

PART 8 0F 9

DP_VDDR DP_VDDC

DP GND

CALIBRATION

MARS-XT M2_FCBGA962

Compal Secret Data

Deciphered Date

DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC

DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR

D

NC NC NC NC

(DP_VDDC:0.95V@280mA/link )

AP31 AP32 AN33 AP33 AL33 AM33 AK33 AK34 AN31

AP13 AT13 AP14 AP15

AN27 AP27 AP28 AW24 AW26 AN29 AP29 AP30 AW30 AW32 AN17 AP16 AP17 AW14 AW16 AN19 AP18 AP19 AW20 AW22 AN34 AP39 AR39 AU37 AF39 AH39 AK39 AL34 AV27 AR28 AV17 AR18 AN38 AM35 AN32

CV54

1

2

PX@ C V54

PX@

0.1U_0402_16V7K

E

+0.95VGS

1

CV55

CV56

2

PX@ CV55

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

DP_VDDC MarsCRB Design

0.1u 1 1 1u 1 1 10u 1 1

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

ATI_MarsXTX_M2_PWR_GND

VAWGA/GB

13 48Thursday, March 28, 2013

E

1.0

A

B

C

D

E

UV1E

AD11

AG10

AG26 AG27

AG23 AG24

AD12

AG11 AG13 AG15

AG28

AH29

AF26 AF27

AF23 AF24

AF11 AF12 AF13

AF15

AF28

AC7

AF7

AJ7 AK8 AL9 G11 G14 G17 G20 G23 G26 G29 H10

J7

J9 K11 K13

K8 L12 L16 L21 L23 L26

L7 M11 N11

P7 R11 U11

U7 Y11

Y7

UV1E

MEM I/O

VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1

LEVEL

TRANSLATION

VDD_CT VDD_CT VDD_CT VDD_CT

I/O

VDDR3 VDDR3 VDDR3 VDDR3

DVP

VDDR4 VDDR4 VDDR4 VDDR4

VOLTAGE

VOLTAGE SENESE

SENESE

FB_VDDC

FB_VDDCI

FB_GND

MARS@

PART 5 0F 9

NC_BIF_VDDC NC_BIF_VDDC

PCIE_PVDD

PCIE

PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC

BIF_VDDC

BACO

BIF_VDDC

CORE

CORE I/O

ISOLATED

MARS-XT M2_FCBGA962

NC NC NC NC NC NC

VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC

VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC

VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI

AA31 AA32 AA33 AA34 W30 Y31 V28 W29 AB37

G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28

N27 T27

AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18

AH22 AH27 AH28 M26 N24 R18 R21 R23 R26 T17 T20 T22 T24 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28

AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13

+1.5VGS

1

CV66

+

@

1 1

VDDR1 MarsCRB Design

0.01u 5 0

0.1u 5 5 1u 0 5

2.2u 5 0 10u 3 5 220u 0 1

VDD_CT MarsCR B Design 120ohm 1 1

0.1u 1 1 1u 1 3 10u 1 1

VDDR3 MarsCRB Design 120ohm 1 0

2 2

0.1u 1 0 1u 2 3 10u 0 1

VDDR4 MarsCRB Design 220ohm 1 1

0.1u 1 1 1u 1 1 10u 1 0

3 3

2

220U_B2_2.5VM_R35

1

CV67

CV60

2

@ CV67

@

@ CV60

@

10U_0603_6.3V6M

1

CV68

CV70

CV69

2

@ CV68

@

PX@ CV70

PX@

PX@ CV69

PX@

10U_0603_6.3V6M

+1.8VGS +VDDC_CT

1 2

@

LV8

LV8 0_0402_5%

0_0402_5%

+3VGS

1 2

LV9

LV9 0_0402_5%

0_0402_5%

+1.8VGS

@

1 2

0_0603_5%

For GDDR5, MVDDQ = 1.5V

(VDDR1:1.5V@3A,GDDR5:1125MHz )

1

CV71

2

PX@ CV71

PX@

1U_0402_6.3V6K

@

LV10

CV74

CV73

CV171

2

PX@ CV171

PX@

PX@ CV74

PX@

PX@ CV73

PX@

1U_0402_6.3V6K

+VDDR3

10U_0603_6.3V6M

1

CV75

2

PX@ CV75

PX@

1U_0402_6.3V6K

(VDD_CT:1.8V@13mA )

1

CV89

2

PX@ CV89

PX@

10U_0603_6.3V6M

(VDDR3:3.3V@25mA)

1

CV92

CV93

2

@ CV93

@

PX@ CV92

PX@

1U_0402_6.3V6K

+VDDR4

( VDDR4:1.8V@300mA)

+1.5VGS

1

CV76

2

PX@ CV76

PX@

0.1U_0402_16V7K

1U_0402_6.3V6K

1

CV94

2

PX@ CV94

PX@

1U_0402_6.3V6K

1

CV78

CV61

CV77

CV79

2

PX@ CV78

PX@

PX@ CV61

PX@

PX@ CV77

PX@

PX@ CV79

PX@

0.1U_0402_16V7K

1

CV90

CV91

2

@ CV90

@

1U_0402_6.3V6K

1

CV96

2

PX@ CV96

PX@

+VDDC_CT

PX@ CV91

PX@

0.1U_0402_16V7K

+VDDR3

1

CV95

2

PX@ CV95

PX@

+VDDR4

1

CV97

2

PX@ CV97

PX@

0.1U_0402_16V7K

Route as differential pair

<39>

VCCSENSE_VGA

<39>

VSSSENSE_VGA

TV15TV15

(PCIE_VDDR:1.8V@100mA )

+PCIE_VDDR

1

CV63

CV62

2

PX@ CV62

PX@

PX@ CV63

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

0.01U_0402_25V7K

(PCIE_VDDC:0.95V@2.5A_GEN3.0 )

+0.95VGS

1

CV80

CV81

2

PX@ CV80

PX@

PX@ CV81

PX@

1U_0402_6.3V6K

(BIF_VDDC:0.95V@1.4A)

+0.95VGS

1

CV87

CV86

2

PX@ CV87

PX@

PX@ CV86

PX@

1U_0402_6.3V6K

(VDDCI:0.9~1.15V@8.8A)

1

CV64

2

PX@ CV64

PX@

1

CV82

2

PX@ CV82

PX@

10U_0603_6.3V6M

+PCIE_VDDR

1

CV65

2

PX@ CV65

PX@

10U_0603_6.3V6M

1

CV84

CV83

CV85

2

@ CV84

@

PX@ CV83

PX@

PX@ CV85

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

1

CV88

2

LV7

0_0603_5%

+VGA_CORE

@

12

+0.95VGS

+1.8VGS

+VGA_CORE

PCIE_VDDR Mar sCRB Design

0.1u 0 2 1u 2 3 10u 1 1

PCIE_VDDC Mar sCRB Design 1u 7 5 10u 2 1

VGA_CORE Cap in power side sheet

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2012/07/03 2013/07/03

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

ATI_MarsXTX_M2_Power

VAWGA/GB

E

14 48Thursday, March 28, 2013

of

1.0

A

UV1H

PART 3 0F 9

GDDR5/DDR3

DQA0_0 DQA0_1 DQA0_2 DQA0_3 DQA0_4 DQA0_5 DQA0_6 DQA0_7 DQA0_8 DQA0_9 DQA0_10 DQA0_11 DQA0_12 DQA0_13 DQA0_14 DQA0_15 DQA0_16 DQA0_17 DQA0_18 DQA0_19 DQA0_20 DQA0_21 DQA0_22 DQA0_23 DQA0_24 DQA0_25 DQA0_26 DQA0_27 DQA0_28 DQA0_29 DQA0_30 DQA0_31 DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8 DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15 DQA1_16 DQA1_17 DQA1_18 DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30 DQA1_31

MVREFDA MVREFSA

NC NC NC

MEM_CALRP0

NC NC

MARS@

GDDR5/DDR3

MEMORY INTERFACE A

MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA1_0/MAA_8

MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12

MAA1_5/MAA_BA2 MAA1_6/MAA_BA0 MAA1_7/MAA_BA1

WCKA0_0/DQMA_0

WCKA0B_0/DQMA_1

WCKA0_1/DQMA_2

WCKA0B_1/DQMA_3

WCKA1_0/DQMA_4

WCKA1B_0/DQMA_5

WCKA1_1/DQMA_6

WCKA1B_1/DQMA_7

EDCA0_0/QSA_0 EDCA0_1/QSA_1 EDCA0_2/QSA_2 EDCA0_3/QSA_3 EDCA1_0/QSA_4 EDCA1_1/QSA_5 EDCA1_2/QSA_6 EDCA1_3/QSA_7

DDBIA0_0/QSA_0B DDBIA0_1/QSA_1B DDBIA0_2/QSA_2B DDBIA0_3/QSA_3B DDBIA1_0/QSA_4B DDBIA1_1/QSA_5B DDBIA1_2/QSA_6B DDBIA1_3/QSA_7B

ADBIA0/ODTA0

ADBIA1/ODTA1

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B RASA1B

CASA0B CASA1B

CSA0B_0 CSA0B_1

CSA1B_0 CSA1B_1

CKEA0 CKEA1

WEA0B WEA1B

MAA0_8/MAA_13 MAA1_8/MAA_14 MAA0_9/MAA_15

MAA1_9/RSVD

MARS-XT M2_FCBGA962

G24 J23 H24 J24 H26 J26 H21 G21 H19 H20 L13 G16 J16 H16 J17 H17

A32 C32 D23 E22 C14 A14 E10 D9

C34 D29 D25 E20 E16 E12 J10 D7

A34 E30 E26 C20 C16 C12 J11 F8

J21 G19

H27 G27

J14 H14

K23 K19

K20 K17

K24 K27

M13 K16

K21 J20

K26 L15

H23 J19 M21 M20

C37

MDA0

C35

MDA1

A35

MDA2

E34

MDA3

G32

MDA4

D33

MDA5

F32

MDA6

E32

MDA7

D31

MDA8

F30

MDA9

C30

MDA10

A30

MDA11

F28

MDA12

C28

+VDD_MEM15_REFDA +VDD_MEM15_REFSA

1 2

PX@

MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63

AG12

AH12

A28 E28 D27 F26 C26 A26 F24 C24 A24 E24 C22 A22 F22 D21 A20 F20 D19 E18 C18 A18 F18 D17 A16 F16 D15 E14 F14 D13 F12 A12 D11 F10 A10 C10 G13 H13

J13 H11 G10

G8 K9

K10

G9 A8 C8 E8 A6 C6 E6 A5

L18

L20

L27 N12

M27

M12

1 1

2 2

RV47 120_0402_1%

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 A_BA2 A_BA0 A_BA1

ODTA0 ODTA1

CLKA0 CLKA0#

CLKA1 CLKA1#

RASA0# RASA1#

CASA0# CASA1#

CSA0#_0

CSA1#_0

CKEA0 CKEA1

WEA0# WEA1#

MAA13 MAA14

DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7

QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7

QSA#0 QSA#1 QSA#2 QSA#3 QSA#4 QSA#5 QSA#6 QSA#7

B

ODTA0 ODTA1

CLKA0 CLKA0#

CLKA1 CLKA1#

RASA0# RASA1#

CASA0# CASA1#

CSA0#_0

CSA1#_0

CKEA0 CKEA1

WEA0# WEA1#

<16> <17>

<16> <16>

<17> <17>

<16> <17>

<16>

<17>

<16> <17>

MDA[0..63]

MAA[0..15]

A_BA[0..2]

DQMA[0..7]

QSA[0..7]

QSA#[0..7]

MDB[0..63]

MAB[0..15]

B_BA[0..2]

DQMB[0..7]

QSB[0..7]

QSB#[0..7]

C

MDA[0..63]

MAA[0..15]

A_BA[0..2]

DQMA[0..7]

QSA[0..7]

QSA#[0..7]

MDB[0..63]

MAB[0..15]

B_BA[0..2]

DQMB[0..7]

QSB[0..7]

QSB#[0..7]

<16,17>

<18,19>

+VDD_MEM15_REFDB +VDD_MEM15_REFSB

MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63

D

UV1I

PART 4 0F 9

GDDR5/DDR3

DQB0_0 DQB0_1 DQB0_2 DQB0_3 DQB0_4 DQB0_5 DQB0_6 DQB0_7 DQB0_8 DQB0_9 DQB0_10 DQB0_11 DQB0_12 DQB0_13 DQB0_14 DQB0_15 DQB0_16 DQB0_17 DQB0_18 DQB0_19 DQB0_20 DQB0_21 DQB0_22 DQB0_23 DQB0_24 DQB0_25 DQB0_26 DQB0_27 DQB0_28 DQB0_29 DQB0_30 DQB0_31 DQB1_0 DQB1_1 DQB1_2 DQB1_3 DQB1_4 DQB1_5 DQB1_6 DQB1_7 DQB1_8 DQB1_9 DQB1_10 DQB1_11 DQB1_12 DQB1_13 DQB1_14 DQB1_15 DQB1_16 DQB1_17 DQB1_18 DQB1_19 DQB1_20 DQB1_21 DQB1_22 DQB1_23 DQB1_24 DQB1_25 DQB1_26 DQB1_27 DQB1_28 DQB1_29 DQB1_30 DQB1_31

MVREFDB MVREFSB

MARS@

GDDR5/DDR3

MEMORY INTERFACE B

MAB0_0/MAB_0 MAB0_1/MAB_1 MAB0_2/MAB_2 MAB0_3/MAB_3 MAB0_4/MAB_4 MAB0_5/MAB_5 MAB0_6/MAB_6 MAB0_7/MAB_7 MAB1_0/MAB_8

MAB1_1/MAB_9 MAB1_2/MAB_10 MAB1_3/MAB_11 MAB1_4/MAB_12

MAB1_5/BA2 MAB1_6/BA0 MAB1_7/BA1

WCKB0_0/DQMB_0

WCKB0B_0/DQMB_1

WCKB0_1/DQMB_2

WCKB0B_1/DQMB_3

WCKB1_0/DQMB_4

WCKB1B_0/DQMB_5

WCKB1_1/DQMB_6

WCKB1B_1/DQMB_7

EDCB0_0/QSB_0 EDCB0_1/QSB_1 EDCB0_2/QSB_2 EDCB0_3/QSB_3 EDCB1_0/QSB_4 EDCB1_1/QSB_5 EDCB1_2/QSB_6 EDCB1_3/QSB_7

DDBIB0_0/QSB_0B DDBIB0_1/QSB_1B DDBIB0_2/QSB_2B DDBIB0_3/QSB_3B DDBIB1_0/QSB_4B DDBIB1_1/QSB_5B DDBIB1_2/QSB_6B DDBIB1_3/QSB_7B

ADBIB0/ODTB0 ADBIB1/ODTB1

CLKB0

CLKB0B

CLKB1

CLKB1B

RASB0B RASB1B

CASB0B CASB1B

CSB0B_0 CSB0B_1

CSB1B_0 CSB1B_1

CKEB0 CKEB1

WEB0B WEB1B

MAB0_8/MAB_13 MAB1_8/MAB_14 MAB0_9/MAB_15

MAB1_9/RSVD

DRAM_RST

MARS-XT M2_FCBGA962

P8 T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9

H3 H1 T3 T5 AE4 AF5 AK6 AK5

F6 K3 P3 V5 AB5 AH1 AJ9 AM5

G7 K1 P1 W4 AC4 AH3 AJ8 AM3

T7 W7

L9 L8

AD8 AD7

T10 Y10

W10 AA10

P10 L10

AD10 AC10

U10 AA11

N10 AB11

T8 W8 U12 V12

AH11

MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 B_BA2 B_BA0 B_BA1

DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7

QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7

QSB#0 QSB#1 QSB#2 QSB#3 QSB#4 QSB#5 QSB#6 QSB#7

ODTB0 ODTB1

CLKB0 CLKB0#

CLKB1 CLKB1#

RASB0# RASB1#

CASB0# CASB1#

CSB0#_0

CSB1#_0

CKEB0 CKEB1

WEB0# WEB1#

MAB13 MAB14MAA15 MAB15

DRAM_RST#_R

AA12

C5 C3 E3 E1 F1 F3 F5 G4 H5 H6 J4 K6 K5 L4 M6 M1 M3 M5 N4 P6 P5 R4 T6 T1 U4 V6 V1 V3 Y6 Y1 Y3

Y5 AA4 AB6 AB1 AB3 AD6 AD1 AD3 AD5 AF1 AF3 AF6 AG4 AH5 AH6

AJ4 AK3 AF8 AF9 AG8 AG7 AK9

AL7 AM8 AM7 AK1

AL4 AM6 AM1

AN4

AP3

AP1

AP5

Y12

E

ODTB0 ODTB1

CLKB0 CLKB0#

CLKB1 CLKB1#

RASB0# RASB1#

CASB0# CASB1#

CSB0#_0

CSB1#_0

CKEB0 CKEB1

WEB0# WEB1#

<18> <19>

<18> <18>

<19> <19>

<18> <19>

<18>

<19>

<18> <19>

3 3

Ball to RV57 < 1"

+1.5VGS +1.5VGS

12

RV49

40.2_0402_1%

PX@

+VDD_MEM15_REFDA DRAM_RST#_R

12

RV55

100_0402_1%

PX@

4 4

A

1

CV98

CV98 1U_0402_6.3V6K

1U_0402_6.3V6K

2

PX@

RV50

40.2_0402_1%

RV56

100_0402_1%

12

PX@

+VDD_MEM15_REFSA +VDD_MEM15_REFSB+VDD_MEM15_REFDB

12

1

CV99

CV99 1U_0402_6.3V6K

PX@

1U_0402_6.3V6K

2

PX@

<16,17,18,19>

B

CV100 to RV57 < 200 mil CV100 to RV53 < 1"

1 2

PX@

DRAM_RST#

DRAM_RST# is a daisy-chain net that connects to all VRAM

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These Capacitors and Resistor values are an example only. The Series R and || Cap values will depend on the DRAM load and will have to be calculated for different Memory ,DRAM Load and board to pass Reset Signal Spec. Place all these components very close to GPU (Within 25mm) and keep all component close to each Other (within 5mm) except Rser2

PX@

RV53 51.1_0402_1%

+1.5VGS

12

RV48

4.7K_0402_5%

@

1 2

PX@

RV54 10_0402_5%

12

CV100

120P_0402_50V9

PX@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

RV57

4.99K_0402_1%

PX@

1 2

Compal Secret Data

2012/07/03 2013/07/03

Compal Secret Data

Deciphered Date

D

+1.5VGS +1.5VGS

RV51

40.2_0402_1%

PX@

RV58

100_0402_1%

PX@

12

1

CV101

CV101 1U_0402_6.3V6K

1U_0402_6.3V6K

2

PX@

Title

Size Document Number Rev

C

Date: Sheet of

12

RV52

40.2_0402_1%

PX@

12

RV59

100_0402_1%

PX@

1

2

Compal Electronics, Inc.

ATI_MarsXTX_M2_MEM IF

VAWGA/GB

E

CV102

CV102 1U_0402_6.3V6K

1U_0402_6.3V6K

PX@

1.0

15 48Thursday, March 28, 2013

1.0

5

D D

<15>

MDA[0..31]

<15,17>

MAA[15..0]

<15>

DQMA[3..0]

<15>

C C

B B

QSA[3..0]

QSA#[3..0]

MDA[0..31]

CLKA0

CLKA0#

<15,17> <15,17> <15,17>

<15> <15>

<15> <15> <15> <15> <15>

<15,17,18,19>

1 2

MARS@

RV60 40.2_0402_1%

1 2

MARS@

RV61 40.2_0402_1%

A_BA0 A_BA1 A_BA2

<15>

ODTA0 CSA0#_0 RASA0# CASA0# WEA0#

DRAM_RST#

12

CV195

0.01U_0402_25V7K

MARS@

CLKA0 CLKA0#

CKEA0

4

+VREFC_A0

RV84

RV84 240_0402_1%

240_0402_1%

MARS@

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MAA14 MAA15

QSA2 QSA0

DQMA2 DQMA0

QSA#2 QSA#0

12

4.99K_0402_1%

UV5

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

+1.5VGS

12

MARS@

RV62

15mil

0.1U_0402_16V7K

12

MARS@

RV64

CV103

+VREFC_A0

12

MARS@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

3

UV6

12

CV104

0.1U_0402_16V7K

CV104

0.1U_0402_16V7K

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MAA14 MAA15

A_BA0 A_BA1 A_BA2

CLKA0 CLKA0# CKEA0

ODTA0 CSA0#_0 RASA0# CASA0# WEA0#

QSA3 QSA1

DQMA3 DQMA1

QSA#3 QSA#1

DRAM_RST#

+VREFC_A1

12

MARS@

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

RV85

RV85 240_0402_1%

240_0402_1%

MARS@

+1.5VGS

12

MARS@

RV63

+VREFC_A1

E3

MDA23

F7

MDA19

F2

MDA22

F8

MDA18

H3

MDA21

H8

MDA17

G2

MDA20

H7

MDA16

D7

MDA0

C3

MDA5

C8

MDA1

C2

MDA6

A7

MDA3

A2

MDA4

B8

MDA2

A3

MDA7

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

4.99K_0402_1%

15mil

12

MARS@

RV65

4.99K_0402_1%

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

2

E3

MDA24

F7

MDA30

F2

MDA27

F8

MDA29

H3

MDA25

H8

MDA28

G2

MDA26

H7

MDA31

D7

MDA12

C3

MDA10

C8

MDA14

C2

MDA11

A7

MDA13

A2

MDA9

B8

MDA15

A3

MDA8

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

1

+1.5VGS

CV113

0.1U_0402_16V7K

CV114

0.1U_0402_16V7K

CV106

1U_0402_6.3V6K

CV107

1U_0402_6.3V6K

CV109

1U_0402_6.3V6K

CV108

1U_0402_6.3V6K

CV105

10U_0603_6.3V6M

1

MARS@CV105

MARS@

2

A A

5

1U_0402_6.3V6K

1

MARS@CV106

MARS@

MARS@CV107

MARS@

MARS@CV109

MARS@

MARS@CV108

MARS@

2

4

CV111

0.1U_0402_16V7K

CV110

1U_0402_6.3V6K

1

@CV111

@

MARS@CV110

MARS@

2

0.1U_0402_16V7K

CV112

0.1U_0402_16V7K

1

@CV113

@

@CV114

@

@CV112

@

2

+1.5VGS

CV151

10U_0603_6.3V6M

1

2

1

@CV151

@

2

+1.5VGS

CV118

1U_0402_6.3V6K

CV116

10U_0603_6.3V6M

CV117

1U_0402_6.3V6K

1

MARS@CV118

MARS@

MARS@CV116

MARS@

MARS@CV117

MARS@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CV152

1U_0402_6.3V6K

CV122

0.1U_0402_16V7K

CV119

1U_0402_6.3V6K

CV120

1U_0402_6.3V6K

1

MARS@CV119

MARS@

MARS@CV120

MARS@

2

0.1U_0402_16V7K

1

2

2010/08/25 2012/08/25

1

MARS@CV152

MARS@

@CV122

@

2

CV125

0.1U_0402_16V7K

CV153

0.1U_0402_16V7K

CV164

0.1U_0402_16V7K

Compal Secret Data

1

@CV164

@

2

1

@CV125

@

@CV153

@

2

Deciphered Date

2

Compal Electronics, Inc.

Title

ATI_Whistler_M2_VRAM_A

Size Document Number Rev

C 1.0

VAWGA/GB

Date: Sheet of

1

16 48Thursday, March 28, 2013

5

D D

<15>

MDA[32..63]

<15,16>

MAA[15..0]

<15>

DQMA[7..4]

<15>

C C

QSA[7..4]

QSA#[7..4]

MDA[32..63]

<15,16> <15,16> <15,16>

A_BA0 A_BA1 A_BA2

<15> <15>

<15>

<15> <15> <15> <15> <15>

CKEA1

ODTA1 CSA1#_0 RASA1# CASA1# WEA1#

<15,16,18,19>

CLKA1 CLKA1#

4

DRAM_RST#

3

UV7

M8

VREFCA

H1

VREFDQ

N3

MAA0

A0

P7

A1

P3

MAA2

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

MAA10

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

MAA15

A15/BA3

M2

A_BA0

QSA4 QSA5 QSA6

DQMA4 DQMA5 DQMA6

QSA#4 QSA#5 QSA#6

DRAM_RST#

12

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

RV86

RV86 240_0402_1%

240_0402_1%

MARS@

+VREFC_A2

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

MDA38

F7

MDA36

F2

MDA39

F8

MDA34

H3

MDA35

H8

MDA33

G2

MDA37

H7

MDA32

D7

MDA42

C3

MDA44

C8

MDA40

C2

MDA46

A7

MDA43 MDA56

A2

MDA45

B8

MDA41

A3

MDA47

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

RV87

RV87 240_0402_1%

240_0402_1%

MARS@

+VREFC_A3

12

MAA0MAA1 MAA1 MAA2MAA3 MAA3MAA4 MAA4MAA5 MAA5MAA6 MAA6MAA7 MAA7MAA8 MAA8MAA9 MAA9 MAA10MAA11 MAA11MAA12 MAA12MAA13 MAA13MAA14 MAA14 MAA15

A_BA0A_BA1 A_BA1A_BA2 A_BA2

CLKA1 CLKA1# CKEA1

ODTA1 CSA1#_0 RASA1# CASA1# WEA1#

QSA7

DQMA7

QSA#7

DRAM_RST#

2

UV8

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

1

E3

MDA49

F7

MDA51

F2

MDA48

F8

MDA52

H3

MDA50

H8

MDA53

G2

MDA55

H7

MDA54

D7

MDA60

C3

MDA57

C8

MDA63

C2 A7

MDA61

A2

MDA59

B8

MDA62

A3

MDA58

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

B B

1 2

CLKA1

MARS@

RV66 40.2_0402_1%

1 2

CLKA1#

MARS@

RV69 40.2_0402_1%

A A

5

12

CV196

0.01U_0402_25V7K

MARS@

+1.5VGS

CV131

1U_0402_6.3V6K

CV129

1U_0402_6.3V6K

CV130

1U_0402_6.3V6K

CV128

10U_0603_6.3V6M

1

MARS@CV128

MARS@

2

4

1

MARS@CV131

MARS@

MARS@CV129

MARS@

MARS@CV130

MARS@

2

4.99K_0402_1%

CV132

1U_0402_6.3V6K

1

MARS@CV132

MARS@

2

+1.5VGS

12

MARS@

RV68

15mil

+VREFC_A2

CV127

0.1U_0402_16V7K

CV127

0.1U_0402_16V7K

12

MARS@

RV71

CV133

1U_0402_6.3V6K

1

MARS@CV133

MARS@

2

12

MARS@

+1.5VGS

CV138

10U_0603_6.3V6M

CV137

0.1U_0402_16V7K

CV134

0.1U_0402_16V7K

@CV134

@

0.1U_0402_16V7K

CV135

0.1U_0402_16V7K

CV136

0.1U_0402_16V7K

1

2

1

@CV137

@

@CV135

@

@CV136

@

2

1

@CV138

@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.5VGS

CV139

10U_0603_6.3V6M

MARS@CV139

MARS@

1

2

+1.5VGS

12

MARS@

RV67

4.99K_0402_1%

1U_0402_6.3V6K

15mil

+VREFC_A3

CV126

0.1U_0402_16V7K

CV126

0.1U_0402_16V7K

12

MARS@

RV70

CV141

1U_0402_6.3V6K

CV140

1

MARS@CV141

MARS@

MARS@CV140

MARS@

2

2010/08/25 2012/08/25

CV142

1U_0402_6.3V6K

1

MARS@CV142

MARS@

2

12

CV144

1U_0402_6.3V6K

CV143

1U_0402_6.3V6K

1

MARS@CV144

MARS@

MARS@CV143

MARS@

2

Compal Secret Data

MARS@

1

2

Deciphered Date

0.1U_0402_16V7K

1

@CV145

@

2

1

@CV148

@

@CV147

@

@CV146

@

2

CV148

0.1U_0402_16V7K

CV147

0.1U_0402_16V7K

CV146

0.1U_0402_16V7K

CV145

0.1U_0402_16V7K

Compal Electronics, Inc.

Title

ATI_Whistler_M2_VRAM_A

Size Document Number Rev

C 1.0

VAWGA/GB

Date: Sheet of

1

17 48Thursday, March 28, 2013

5

D D

<15>

MDB[0..31]

<15,19>

MAB[15..0]

<15>

DQMB[3..0]

<15>

C C

QSB[3..0]

QSB#[3..0]

MDB[0..31]

<15> <15>

1 2

CLKB0

RV72 40.2_0402_1%

1 2

CLKB0#

RV73 40.2_0402_1%

<15,19> <15,19> <15,19>

CLKB0 CLKB0#

<15>

<15> <15> <15> <15> <15>

PX@

ODTB0 CSB0#_0 RASB0# CASB0# WEB0#

12

CV197

0.01U_0402_25V7K

PX@

B_BA0 B_BA1 B_BA2

<15,16,17,19>

CKEB0

4

DRAM_RST#

3

UV9

M8

VREFCA

H1

VREFDQ

N3

MAB0

A0

P7

MAB1

A1

P3

MAB2

A2

N2

MAB3

A3

P8

MAB4

A4

P2

MAB5

A5

R8

MAB6

A6

R2

MAB7

A7

T8

MAB8

A8

R3

MAB9

A9

L7

MAB10 MAB10

A10/AP

R7

MAB11

A11

N7

MAB12

A12

T3

MAB13

A13

T7

MAB14

A14

M7

MAB15 MAB15

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

QSB2 QSB0 QSB1

DQMB2 DQMB3 DQMB0 DQMB1

QSB#2 QSB#3 QSB#0 QSB#1

12

RV88

RV88 240_0402_1%

240_0402_1%

PX@

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

MDB19

F7

MDB20

F2

MDB22

F8

MDB16

H3

MDB23

H8

MDB17

G2

MDB21

H7

MDB18

D7

MDB0

C3

MDB4

C8

MDB1

C2

MDB6

A7

MDB3

A2

MDB7

B8

MDB2

A3

MDB5

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

RV89

RV89 240_0402_1%

240_0402_1%

PX@

2

UV10

B_BA0 B_BA1 B_BA2

CLKB0 CLKB0# CKEB0

ODTB0 CSB0#_0 RASB0# CASB0# WEB0#

QSB3

DRAM_RST#

12

MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9

MAB11 MAB12 MAB13 MAB14

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

+VREFC_B1+VREFC_B0

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

MDB26

F7

MDB30

F2

MDB24

F8

MDB29

H3

MDB27

H8

MDB28

G2

MDB25

H7

MDB31

D7

MDB15

C3

MDB10

C8

MDB14

C2

MDB11

A7

MDB12

A2

MDB9

B8

MDB13

A3

MDB8

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

1

+1.5VGS

12

PX@

RV74

4.99K_0402_1%

B B

+1.5VGS

CV156

1U_0402_6.3V6K

CV157

0.1U_0402_16V7K

CV124

1U_0402_6.3V6K

CV121

1U_0402_6.3V6K

CV115

10U_0603_6.3V6M

1

PX@CV121

PX@

PX@CV115

PX@

2

A A

5

CV155

1U_0402_6.3V6K

CV191

1U_0402_6.3V6K

1

PX@CV124

PX@

PX@CV155

PX@

PX@CV191

PX@

2

0.1U_0402_16V7K

1

PX@CV156

PX@

@CV157

@

2

4.99K_0402_1%

CV159

0.1U_0402_16V7K

CV158

0.1U_0402_16V7K

1

@CV159

@

@CV158

@

2

4

15mil

+VREFC_B0

CV149

0.1U_0402_16V7K

CV149

0.1U_0402_16V7K

12

PX@

RV76

CV160

1

@CV160

@

2

+1.5VGS

CV161

10U_0603_6.3V6M

@CV161

@

12

PX@

+1.5VGS

CV123

1U_0402_6.3V6K

CV162

10U_0603_6.3V6M

CV163

1U_0402_6.3V6K

1

2

1

PX@CV162

PX@

PX@CV163

PX@

2

CV166

1U_0402_6.3V6K

CV165

1U_0402_6.3V6K

CV167

1U_0402_6.3V6K

1

PX@CV123

PX@

PX@CV166

PX@

PX@CV165

PX@

PX@CV167

2

3

PX@

2

Security Classification

2

+1.5VGS

12

PX@

RV75

4.99K_0402_1%

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

15mil

+VREFC_B1

CV150

0.1U_0402_16V7K

CV150

0.1U_0402_16V7K

12

PX@

RV77

CV168

0.1U_0402_16V7K

1

@CV168

@

2

12

PX@

CV170

0.1U_0402_16V7K

CV72

0.1U_0402_16V7K

CV169

0.1U_0402_16V7K

1

@CV170

@

@CV72

@

@CV169

@

2

Compal Secret Data

2010/08/25 2012/08/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

ATI_Whistler_M2_VRAM_B

Size Document Number Rev

C 1.0

VAWGA/GB

Date: Sheet of

1

18 48Thursday, March 28, 2013

5

D D

C C

<15>

<15,18>

<15>

MDB[32..63]

MAB[15..0]

DQMB[7..4]

QSB[7..4]

QSB#[7..4]

MDB[32..63]

<15,18> <15,18> <15,18>

<15> <15>

B_BA0 B_BA1 B_BA2

CLKB1 CLKB1#

<15>

<15> <15> <15> <15> <15>

<15,16,17,18>

CKEB1

ODTB1 CSB1#_0 RASB1# CASB1# WEB1#

DRAM_RST#

4

UV11

M8

VREFCA

H1

VREFDQ

N3

MAB0 MAB0

A0

P7

MAB1 MAB1

A1

P3

MAB2 MAB2

A2

N2

MAB3 MAB3

A3

P8

MAB4 MAB4

A4

P2

MAB5 MAB5

A5

R8

MAB6 MAB6

A6

R2

MAB7 MAB7

A7

T8

MAB8 MAB8

A8

R3

MAB9 MAB9

A9

L7

MAB10 MAB10

A10/AP

R7

MAB11

A11

N7

MAB12 MAB12

A12

T3

MAB13 MAB13

A13

T7

MAB14 MAB14

A14

M7

MAB15 MAB15

A15/BA3

M2

B_BA0 B_BA1 B_BA2

QSB4 QSB5

DQMB4 DQMB5

QSB#4 QSB#5

DRAM_RST# DRAM_RST#

12

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

RV90

RV90 240_0402_1%

240_0402_1%

PX@

+VREFC_B2

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

MDB33

F7

MDB37

F2

MDB35

F8

MDB39

H3

MDB32

H8

MDB36

G2

MDB34

H7

MDB38

D7

MDB44

C3

MDB41

C8

MDB47

C2

MDB43

A7

MDB45

A2

MDB40

B8

MDB46

A3

MDB42

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

3

UV12

RV91

RV91 240_0402_1%

240_0402_1%

PX@

+VREFC_B3

12

B_BA0 B_BA1 B_BA2

CLKB1 CLKB1# CKEB1

ODTB1 CSB1#_0 RASB1# CASB1# WEB1#

QSB6 QSB7

DQMB6 DQMB7

QSB#6 QSB#7

MAB11

UV12

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

MDB55 MDB50 MDB54 MDB51 MDB53 MDB49 MDB52 MDB48

MDB56 MDB59 MDB63 MDB62 MDB57 MDB61 MDB58 MDB60

+1.5VGS

2

1

4.99K_0402_1%

+1.5VGS

CV184

10U_0603_6.3V6M

1

@CV184

@

2

3

+1.5VGS

12

PX@

RV78

15mil

+VREFC_B3

CV172

0.1U_0402_16V7K

CV172

0.1U_0402_16V7K

12

PX@

RV82

12

PX@

CV188

1U_0402_6.3V6K

CV189

1U_0402_6.3V6K

CV187

1U_0402_6.3V6K

CV185

10U_0603_6.3V6M

CV186

1U_0402_6.3V6K

1

PX@CV185

PX@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

PX@CV188

PX@

PX@CV189

PX@

PX@CV187

PX@

PX@CV186

PX@

2

2010/08/25 2012/08/25

CV154

0.1U_0402_16V7K

CV190

1U_0402_6.3V6K

1

@CV154

@

PX@CV190

PX@

2

CV194

0.1U_0402_16V7K

CV193

0.1U_0402_16V7K

CV192

0.1U_0402_16V7K

Compal Secret Data

1

@CV192

@

2

1

@CV194

@

@CV193

@

2

Deciphered Date

2

Compal Electronics, Inc.

Title

ATI_Whistler_M2_VRAM_A

Size Document Number Rev

C 1.0

VAWGA/GB

Date: Sheet of

1

19 48Thursday, March 28, 2013

+1.5VGS

1 2

CLKB1

PX@

RV79 40.2_0402_1%

1 2

CLKB1#

PX@

RV81 40.2_0402_1%

B B

A A

RV81 40.2_0402_1%

5

12

CV198

0.01U_0402_25V7K

PX@

12

PX@

RV80

4.99K_0402_1%

+1.5VGS +1.5VGS

10U_0603_6.3V6M

15mil

+VREFC_B2

CV173

0.1U_0402_16V7K

CV173

0.1U_0402_16V7K

12

PX@

RV83

CV174

1U_0402_6.3V6K

1

PX@CV174

PX@

2

4

12

PX@

CV182

0.1U_0402_16V7K

CV181

0.1U_0402_16V7K

CV180

0.1U_0402_16V7K

CV176

1U_0402_6.3V6K

CV175

1

PX@CV175

PX@

2

CV178

1U_0402_6.3V6K

CV177

1U_0402_6.3V6K

1

PX@CV176

PX@

PX@CV178

PX@

PX@CV177

PX@

2

0.1U_0402_16V7K

CV179

1U_0402_6.3V6K

1

@CV180

@

PX@CV179

PX@

2

CV183

0.1U_0402_16V7K

1

@CV182

@

@CV181

@

@CV183

@

2

5

D D

HDMI_DET<4>

<4> <4>

C C

B B

DP2_TXP0 DP2_TXN0

DP2_TXP1 DP2_TXN1

DP2_TXP2 DP2_TXN2

DP2_TXP3 DP2_TXN3

HDMI_CLKP

HDMI_CLKN

HDMI_TX0P

HDMI_TX0N

HDMI_TX1P

HDMI_TX1N

HDMI_TX2P

HDMI_TX2N

4

1

4

1

2

3

WCM-2012HS-900T

2

3

WCM-2012HS-900T

DP2_TXP0 DP2_TXN0

DP2_TXP1 DP2_TXN1

DP2_TXP2 DP2_TXN2

DP2_TXP3 DP2_TXN3

WCM-2012HS-900T

4

1

L30

EMIP@L30

EMIP@

WCM-2012HS-900T

4

1

L31

EMIP@L31

EMIP@

L39

EMIP@ L39

EMIP@

2

3

L40

EMIP@ L40

EMIP@

2

3

2

3

2

1

4

1

4

C51 0.1U_0402_16 V7KHDMI@C51 0.1U_0402_16V7KHDMI@ C52 0.1U_0402_16 V7KHDMI@C52 0.1U_0402_16V7KHDMI@

C53 0.1U_0402_16 V7KHDMI@C53 0.1U_0402_16V7KHDMI@ C54 0.1U_0402_16 V7KHDMI@C54 0.1U_0402_16V7KHDMI@

C55 0.1U_0402_16 V7KHDMI@C55 0.1U_0402_16V7KHDMI@ C56 0.1U_0402_16 V7KHDMI@C56 0.1U_0402_16V7KHDMI@

C57 0.1U_0402_16 V7KHDMI@C57 0.1U_0402_16V7KHDMI@

C5888 0.1U_0402_ 16V7KHDMI@C588 8 0.1U_0402_16V7KHD MI@

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

1 2 1 2

+3VS

HDMI CLK DATA Pull high in Page 22 for 8P4R

HDMI_CLK<22,4>

A A

HDMI_DATA<22,4>

5

HDMI_CLK

HDMI_DATA

4

HDMI_TX2P HDMI_TX2N

HDMI_TX1P HDMI_TX1N

HDMI_TX0P HDMI_TX0N

HDMI_CLKP HDMI_CLKN

Q75A

HDMI@

2

DMN66D0LDW-7_SOT 363-6

5

3

Q75B

HDMI@

DMN66D0LDW-7_SOT 363-6

61

4

HDMI@

Q87

MMBT3904_NL_SOT23-3

Q87

+3VS

C

E

3 1

12

HDMI@

R898

R898 100K_0402_5%

100K_0402_5%

B

2

3

HDMI@

R434

1 2

150K_0402_5%

200K_0402_5%

R894

@

1 2

2

0.1U_0402_16V7K

Close to HDMI connector

D1

ESDU@D 1

ESDU@

HDMI_TX2+_CONN

HDMI_TX2-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMICLK_R

HDMIDAT_R

HDMICLK_R

HDMIDAT_R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

4

5

3

TVWDF1004AD0_D FN9

D2

ESDU@

1

2

4

5

3

TVWDF1004AD0_D FN9

3

9

HDMI_TX2+_CONN

8

HDMI_TX2-_CONN

7

HDMI_TX1+_CONN

6

HDMI_TX1-_CONN

9

8

7

6

2

D69

D69 L30ESDL5V0C3-2_SOT23 -3

L30ESDL5V0C3-2_SOT23 -3

ESDU@

1

2012/04/22 2015/04/22

3

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_CLK+_CONN

HDMI_CLK-_CONN

Compal Secret Data

Deciphered Date

HDMI_CLK-_CONN

HDMI_CLK+_CONN

HDMI_TX1-_CONN

HDMI_TX1+_CONN

HDMI_TX0-_CONN

HDMI_TX0+_CONN

HDMI_TX2-_CONN

HDMI_TX2+_CONN

2

+5VS

C544

R1470

HDMI@ R1470

HDMI@

2.2K_0402_5%

1

U73

1

2

IN

AP2330W-7_SC59-3

R1471

2.2K_0402_5%

1 2

HDMI_DET_R

HDMIDAT_R HDMICLK_R

HDMI_CLK-_CONN

HDMI_CLK+_CONN HDMI_TX0-_CONN

HDMI_TX0+_CONN HDMI_TX1-_CONN

HDMI_TX1+_CONN HDMI_TX2-_CONN

HDMI_TX2+_CONN

1 2

R432 499_0402_1%HDMI@R432 499_0402_1%HD MI@

1 2

R433 499_0402_1%HDMI@R433 499_0402_1%HD MI@

1 2

R435 499_0402_1%HDMI@R435 499_0402_1%HD MI@

1 2

R436 499_0402_1%HDMI@R436 499_0402_1%HD MI@

1 2

R439 499_0402_1%HDMI@R439 499_0402_1%HD MI@

1 2

R440 499_0402_1%HDMI@R440 499_0402_1%HD MI@

1 2

R441 499_0402_1%HDMI@R441 499_0402_1%HD MI@

1 2

R442 499_0402_1%HDMI@R442 499_0402_1%HD MI@

Title

Size Document Number Rev

B

Date: Sheet of

OUT

GND

HDMI@R1471

HDMI@

+5V_Display

+3VS

Compal Electronics, Inc.

HDMI CONN

VAWGA/GB

W=40mils

3

2

JHDMI1

19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

SUYIN_100042GR019M23DZL

ME@

13

D

2

G

2N7002K_SOT23-3

S

0.1U_0402_16V7K

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKCK_shield CK+ D0D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

Q76

HDMI@

1

+5V_Display

C543

G1 G2 G3 G4

20 48Monday, April 01, 2013

1

2

20 21 22 23

1.0

5

4

3

2

1

LCD POWER CIRCUIT

CMOS Camera

+3VS

@

12

R694 0_0402_5%

D

13

1

CMOS@

C1152

0.1U_0402_16V4Z

2

R02

VGA LCD/PANEL BD. Conn.

Add for protect BKOFF# damage

1 2

R1466 0_0402_5%R1466 0_0402_5%

LVDS_ACLK LVDS_ACLK#

LVDS_A2 LVDS_A2# LVDS_A1 LVDS_A1# LVDS_A0

LVDS_A0# EDID_DATA EDID_CLK

1

EMIU@C1160

EMIU@

12 12

R696 R695

+LCDVDD_CONN

2

+3VS_CMOS

CMOS

+3VS

USB20_P3_R USB20_N3_R

(60 MIL)

(40 MIL)(40 MIL)

680P_0402_50V7K

BKOFF# INVT_PWM

USB20_P3_R USB20_N3_R

+3VS_CMOS

10U

1

@

C1153

C1153 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

C1158

EMIU@

2

JLVDS1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

ACES_88341-3001 ME@

1 2

@

R813 0_0805_5%

1

C1159

4.7U_0805_25V6-K

2

31

G1

32

G2

33

G3

34

G4

B++LEDVDD

R652

R652 100K_0402_5%

100K_0402_5%

1 2

W=60mils

1

C522

2

4.7U_0603_6.3V6K

<28>

CMOS_ON#

R1458

CMOS@R1458

CMOS@

150K_0402_5%

1

C1155

CMOS@C1155

CMOS@

0.1U_0402_16V4Z

2

CMOS@

Q70

Q70 PMV65XP_SOT23-3

PMV65XP_SOT23-3

S

G

2

+3VS +LCDVDD_CONN

D D

C C

W=60mils

1500P_0402_50V7K

<4>

C16

U72

5

4

1

APL3512ABI-TRG_SOT23-5

2

APU_ENVDD

VIN

SS

GND

2

3

EN

1

+LCDVDD_CONN

VOUT

Use APU control for WIN8

1 2

<4>

APU_INVT_PWM

B B

<28>

BKOFF#

12

R899

R899 10K_0402_5%

10K_0402_5%

<5> <5>

R1463 0_0402_5%@R1463 0_0402_5%@

USB20_P3 USB20_N3

100K_0402_5%

USB20_P3 USB20_N3

R826

<4> <4>

<4>

12

<4> <4> <4> <4> <4> <4> <4>

+3VS

680P_0402_50V7K

C1160

0_0402_5%

@ R69 6

@ @ R69 5

@

0_0402_5%

L58

EMIU@L58

EMIU@

1

USB20_P3

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2012/04/22 2015/04/22

Compal Secret Data

USB20_N3

Deciphered Date

1

4

WCM-2012-900T_4P

2

3

2

USB20_P3_R

3

USB20_N3_R

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

LVDS CONN / Camera

VAWGA/GB

21 48Thursday, March 28, 2013

1

1.0

A

<4>

1 1

2 2

3 3

4 4

<4>

RP22

150_0804_8P4R_1%

0.1U_0402_16V7K

18 27 36 45

+5VS

C529

0.1U_0402_16V7K

DAC_RED

DAC_GRN

DAC_BLU

DAC_BLU DAC_GRN DAC_RED

1

2

C537

A

+3VS

DAC_RED

DAC_GRN

DAC_BLU

1

2

CRT_DDC_DAT A

<4>

CRT_DDC_CLK

<4>

CRT_VSYNC

<4>

CRT_HSYNC

1 2

R693 4.7K_0402_5%R693 4.7K_0402_5%

1 2

R697 4.7K_0402_5%R697 4.7K_0402_5%

HDMI_CLK<20,4> HDMI_DATA<20,4>

C1094

C1094 6P_0402_50V8

6P_0402_50V8

CRT_DDC_DAT A

CRT_DDC_CLK

B

12

C1103

C1103 6P_0402_50V8

6P_0402_50V8

HDMI_CLK HDMI_DATA CRT_DDC_DAT _CONN CRT_DDC_CLK_ CONN

U10

1

VCC_SYNC

2

VCC_VIDEO

7

VCC_DDC

10

DDC_IN1

11

DDC_IN2

13

SYNC_IN1

15

SYNC_IN2

6

GND

TPD7S019-15DBQR_SSOP16

B

C

FCM1608CF-121T03 0603

1 2

EMIP@

L36

FCM1608CF-121T03 0603

1 2

L37

FCM1608CF-121T03 0603

1 2

L38

12

C1104

C1104 6P_0402_50V8

6P_0402_50V8

VIDEO1

VIDEO2

VIDEO3

DDC_OUT1

DDC_OUT2

SYNC_OUT1

SYNC_OUT2

BYP

12

C1105

C1105 6P_0402_50V8

6P_0402_50V8

8

1 2

C23 0.22U_0402_10V6KC23 0.22U_0402_1 0V6K

3

RED

4

GREEN

5

BLUE

9

CRT_DDC_DAT _CONN

12

CRT_DDC_CLK_ CONN

14

JVGA_VS_U

16

JVGA_HS_U

1 8 2 7 3 6 4 5

R106 R107 for EMI

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

C1107

C1107 6P_0402_50V8

6P_0402_50V8

C1106

C1106 6P_0402_50V8

6P_0402_50V8

+3VS

RP1

4.7K_8P4R_5%

ESDP@ C6 00

ESDP@

1 2

R106 22_0402_5%EMIP@R106 22_0402_5%EMIP@

1 2

R107 22_0402_5%EMIP@R107 22_0402_5%EMIP@

2012/04/22 2015/04/22

C

+5V_Display

1

C600 1000P_0402_50V7K

1000P_0402_50V7K

2

JVGA_VS

JVGA_HS

1

@

C411

Compal Secret Data

1

@

C412

2

10P_0402_50V8J

Deciphered Date

10P_0402_50V8J

RED

GREEN

BLUE

RED

CRT_DDC_DAT _CONN GREEN

JVGA_HS BLUE

JVGA_VS

CRT_DDC_CLK_ CONN

D

+5V_Display

JCRT1

6

T49T49

T58T58

Title

Size Document Number Rev

Date: Sheet of

11

1 7

12

2 8

13

3 9

14

4 10 15

5

B

16

G

17

G

CONTE_80431-5K1- 152

ME@

Compal Electronics, Inc.

CRT CONN

VAWGA/GB

E

1.0

22 48Thursday, March 28, 2013

E

A

B

C

D

E

F

G

H

SATA HDD Conn.

JHDD1

1

GND

12

SATA_ATX_C_DRX_P0

SATA_ATX_DRX_P0<5>

<5> <5>

1 1

EMIP@ C598

EMIP@

SATA_ATX_DRX_N0<5>

SATA_DTX_C_ARX_N0 SATA_DTX_C_ARX_P0

+5V_HDD

R02

1

C598 1000P_0402_50V7K

1000P_0402_50V7K

2

SATA_DTX_C_ARX_P0

1

C599

0.1U_0402_16V4Z

2

C596 0.01U_0402_25V7KC596 0.01U_0402_25V7K C597 0.01U_0402_25V7KC597 0.01U_0402_25V7K

C1370.01U_0402_2 5V7K C1370 .01U_0402_25V7K

12

C1380.01U_0402_2 5V7K C1380 .01U_0402_25V7K

1 2 1 2

+3VS

R551 0_0805_5%

+5VS

R550 0_0805_5%

SATA_ATX_C_DRX_N0

1 2

@

1 2

@

10U

1

C602

C602 10U_0603_6.3V6M

10U_0603_6.3V6M

2

SATA_DTX_ARX_N0SATA_DTX_C_ARX_N0 SATA_DTX_ARX_P0

+3V_HDD

+5V_HDD

2

RX+

3

RX-

4

GND

5

TX-

6

TX+

7

GND

8

3.3V

9

3.3V

10

3.3V

11

GND

12

GND

13

GND

14

5V

15

5V

16

5V

17

GND

18

Reserved

19

GND

20

12V

21 22

SUYIN_127043FB022G278ZR

GND

12V

GND

12V

23 24

2 2

FOR 15"

SATA ODD FFC Conn.

JODD2

CAP in Small Board

1 2

R710 0_0402_5%ZODD@R710 0_0402_5%ZODD@

ODD_DA#

ODD_DETECT# +5V_ODD

R02

<5>

SATA_DTX_C_ARX_N1

<5>

SATA_DTX_C_ARX_P1

SATA_ATX_DRX_P1<5> SATA_ATX_DRX_N1<5>

SATA_ATX_DRX_P1 SATA_ATX_DRX_N1

SATA_DTX_C_ARX_N1 SATA_DTX_C_ARX_P1

<28>

ODD_DA#

Co-lay

3 3

+5VALW

12

ZODD@ R930

ZODD@

<6>

ODD_EN

R930 10K_0402_5%

10K_0402_5%

2

IN

+5VS

1

OUT

ZODD@

GND

Q91

Q91 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

3

ODD Power Control

J@ J6

J@

112

JUMP_43X79

Q90

S

G

R1110

1 2

200K_0402_5%

ZODD@

J6

D

13

LP2301ALT1G_SOT23-3ZODD@

2

1 2

2

C642

0.1U_0402_16V4Z

ZODD@

Need OPEN

+5V_ODD

1

C641

C641 10U_0603_6.3V6M

10U_0603_6.3V6M

2

SATA_ATX_DRX_P1 SATA_ATX_DRX_N1

SATA_DTX_C_ARX_N1 SATA_DTX_C_ARX_P1 SATA_DTX_ARX_P1_14

1 2

C619 0.01U_0402_25V7K14@C619 0.01U_0402_25V7K14@

1 2

C616 0.01U_0402_25V7K14@C616 0.01U_0402_25V7K14@

1 2

C614 0.01U_0402_25V7K14@C614 0.01U_0402_25V7K14@

1 2

C613 0.01U_0402_25V7K14@C613 0.01U_0402_25V7K14@

SATA_ATX_C_DRX_P1_14 SATA_ATX_C_DRX_N1_14

SATA_DTX_ARX_N1_14

1 2

R555

+3VS

10K_0402_5%

ZODD@

ODD_DETECT# +5V_ODD

ODD_DA#

FOR 14"

SATA ODD Conn.

R02

JODD2

1

2

3

4

5

6

7

8

9

10

GND GND

HB_A051020-SAHR21

ME@

JODD1

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

DP

9

+5V

10

+5V

11

MD

12

GND GND13GND

ALLTO_C18518-11305-L

ME@

GND

11 12

15 14

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

D

2012/04/22 2015/04/22

E

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Date: Sheet of

F

Date: Sheet of

Compal Electronics, Inc.

HDD/ODD/FAN/SCREW

VAWGA/GB

G

1.0

of

23 48Thursday, March 28, 2013

H

A

+3VALW

Layout Notice : Place as close chip as possible.

1 1

<28>

LAN_PWR_ON#

LAN Chip Vendor recommand reserve the PU resistor close LAN chip AMD recommand reserve Diode

LAN_PWR_ON#

RL3

12

@

10K_0402_5%

2

1

@

CL7

0.1U_0402_16V7K

J10

112

JUMP_43X79

J@

2

@

D

S

D

S

13

G

QL1

2

PMV65XP_SOT23-3~D

B

C

D

E

+3V_LAN

Close together

LL1

SWR@LL1

SWR@

+LX_R +LX

1

CL2

CL1

2

1000P_0402_50V7K

SWR@

Close to Pin40

UL1

8172@UL1

8172@

1 2

4.7UH_SIA4012-4R7M_20%

1

2

CL3

0.1U_0402_16V7K

10U_0603_6.3V6M

10U

SWR@

Note: Place Close to LAN chip LL1 DCR< 0.15 ohm

Rate current > 1A

+LX

LL3

SWR@LL3

SWR@

1 2

+LX_R+1.1_AVDDL+1.1_AVDDL_L

1

CL5

CL4

2

0.1U_0402_16V7K

LL2

FBMA-L11160808601LMA10T_2P

1 2

1

CL6

2

1U_0402_6.3V4Z

4.7U_0603_6.3V6K

FBMA-L11160808601LMA10T_2P

Place close to Pin34

1 2

+3V_LAN

<10,6>

APU_PCIE_RST#

2 2

3 3

<6>

<5>

PCIE_DTX_C_ARX_N1

<5>

PCIE_DTX_C_ARX_P1

<5>

PCIE_ATX_C_DRX_N1

<5>

PCIE_ATX_C_DRX_P1

<5>

CLK_PCIE_LAN#

<5>

CLK_PCIE_LAN

<28>

LAN_CLKREQ#

LAN_WAKE#

RL4 4.7K_0402 _5%@RL4 4.7K_0402_5%@

RB751V-40TE17_SOD323-2

R577 0_0402_5%

1

CL17

2

0.1U_0402_16V7K

Near

Pin13

Pin19

D4

@

12

1 2

@

Place Close to Chip

1 2

CL9 0.1U_0402_16V7KCL9 0.1U_040 2_16V7K

1 2

CL11 0.1U_0402_16V7KCL11 0.1U_0402_16V7K

1

CL19

CL18

2

0.1U_0402_16V7K

Near Pin31

LAN_PERST#

PCIE_DTX_ARX_N1

PCIE_DTX_ARX_P1

Near Pin6

0.1U_0402_16V7K

LAN_PERST#

LAN_XTALO LAN_XTALI

+1.1_AVDDL +1.1_AVDDL +1.1_AVDDL +1.1_AVDDL_L +1.1_AVDDL

1

CL20

CL21

2

1U_0402_6.3V4Z

AR8172-AL3A-R

1

CL8

CL10

UL1

29

TX_N

Atheros

30

36

35

32 33

2

3

25 26

28 27

7 8

4

13 19 31 34

6

41

0.1U_0402_16V7K

Atheros

TX_P

AR8151/AR8161

RX_N

RX_P

REFCLK_N REFCLK_P

PERST#

WAKE#

SMCLK SMDATA

NC TESTMODE

XTLO XTLI

CLKREQ#

AVDDL AVDDL AVDDL AVDDL AVDDL_REG/AVDDL

GND

AR8162-AL3A-R_QFN40_5X5

8162@

VDDCT/ISOLAN

DVDDL_REG/DVDD L

AVDDH/AVDD33

AVDDH_REG

LED_0 LED_1 LED_2

TRXN0 TRXP0 TRXN1 TRXP1 TRXN2 TRXP2 TRXN3 TRXP3

RBIAS

VDD33

DVDDL/PPS

AVDDH

38

RL12 10K_0402_5%

39 23

12 11 15 14 18 17 21 20

10

1

40

LX

5

24 37

16 22 9

Near Pin9

12

LDO@

MDI0MDI0+ MDI1MDI1+

LAN_RBIAS

+3V_LAN

+LX

+1.7_VDDCT

+LX_R

+2.7_AVDDH +2.7_AVDDH

1 2

RL8 2.37K_0402_1%RL 8 2.37K_0402_1%

Place Close to PIN1

+LX

+3V_LAN

1

CL22

CL23

2

1U_0402_6.3V4Z

0.1U_0402_16V7K

Near Pin22

mount RL12 if u se LDO modue

MDI0MDI0+ MDI1MDI1+

RL10 30K_0402_5%RL10 30K_0402_5%

1 2

+2.7_AVDDH

1

CL24

2

0.1U_0402_16V7K

Near

in37

P

+3V_LAN

1

CL25

CL26

2

0.1U_0402_16V7K

<25> <25> <25> <25>

Place Close to PIN1

CL12

1 2

1000P_0402_50V7K

1U_0402_6.3V4Z

+3V_LAN

1

CL13

2

0.1U_0402_16V7K

1

CL14

CL15

2

1U_0402_6.3V4Z

1

CL16

2

10U_0603_6.3V6M

10U

CL10

2

1U_0402_6.3V4Z

0.1U_0402_16V7K

Place close to Pin16

+3V_LAN

LAN_XTALI

YL1

4

NC

OSC

4 4

CL28

15P_0402_50V8J

A

B

1

OSC

25MHZ_20PF_FSX3M-25.M20FDO

1

2

NC

15P_0402_50V8J

LAN_XTALO

3

2

1

CL29

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/04/22 2015/04/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

LAN-AR8151

VAWGA/GB

Thursday, March 28, 2013

E

24 48

1.0

A

Place Close to TL1

B

ESDU@

DL1

AZC099-04S.R7G_SOT23- 6

MDI1+ MDI0+

1

I/O1

I/O3

4

C

Reserve gas tube for EMI go rural solution

D

E

DL1

1 1

2 2

3 3

1'S PN:SC300001G00 2'S PN:SC300002E00

<24> <24>

1

CL31

EMIP@ CL31

EMIP@

0.01U_0402_25V7K

2

<24> <24>

MDI0- MDI1-

MDI0+ MDI0-

MDI1+ MDI1-

MDI0+ MDI0-

MDI1+ MDI1-

2

3

MDO0+

MDO0-

MDO1+

MCT

MDO1-

MCT

GND

I/O2

1 2 3 4 5 6 7

TL1

TD+ TDCT NC NC CT RD+ RD-8RX-

MHPC_NS681612A

1

2

3

4

5

6

7

8

5

VDD

6

I/O4

16

MDO0+

TX+

15

MDO0-

TX-

14

MCT

CT

13

NC

12

NC

11

MCT

CT

10

MDO1+

RX+

9

MDO1-

JLAN1

PR1+

PR1-

PR2+

PR3+

PR3-

PR2-

PR4+

PR4-

SANTA_130456-121

ME@

GND GND

CHASSIS1_GND

RL14

1 2

75_0805_5%

EMIP@

DLL1

DLL1 BS4200N-C-LV_SMB-F2

BS4200N-C-LV_SMB-F2

EMIGASP@

CL30

1 2

10P_0603_50V

EMIP@

12

CHASSIS1_GND

Place Close to TL1

EMIP@

1 2

CL63 0.1U_0603_50 V7K

1 2

CL61 0.1U_0603_50 V7K

EMIP@

CHASSIS1_GND

9 10

C173

ESDP@ C173

ESDP@

0.1U_0402_16V7K

2

1

C178

ESDP@C178

ESDP@

0.1U_0402_16V7K

4 4

Security Classification

2012/04/22 2015/04/22

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/04/22 2015/04/22

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

LAN_Transformer

VAWGA/GB

25 48Thursday, March 28, 2013

E

1.0

A

1 1

<28>

2 2

EC_TS_ON#

@

1 2

R5581 100K_0402_5%

C1331

0.1U_0402_16V4Z

@

B

+3VS +3VS_TS

1 2

TS@

R5583 0_0402_5%

D

S

D

S

13

G

Q156

2

PMV65XP_SOT23-3~D

@

1

2

@

2

1

TS@

0.1U_0402_16V4Z

C

+3VS_TS

<5> <5>

C1322

+1.5VS

+3VS_WLAN

USB20_N1 USB20_P1

1 2

R726 0_0402_5%TS@R726 0 _0402_5%TS@

D

JTS1

8

GND

7

GND

6

5

4

3

2

TS_RST#EC_TS_ON#

1

ACES_50208-00601-P01

ME@

E

Mini-Express Card(WLAN/WiMAX)

JWLN1

1 2

<6>

APU_PCIE_WAKE#

<6>

3 3

<6>

4 4

<28> <28>

BT_DISABLE#

<6>

BT_OFF#

WLAN_CLKREQ#

<5> <5>

EC_TX EC_RX

A

R1500 0_0402_5%@R1500 0_0402_5%@

CLK_PCIE_WLAN#

CLK_PCIE_WLAN

PCIE_DTX_C_ARX_N2 PCIE_DTX_C_ARX_P2

PCIE_ATX_C_DRX_N2 PCIE_ATX_C_DRX_P2

EC_TX EC_RX

R1520 1K_0402_5%R1520 1K_0402_5%

1 2 1 2

1 2

100_0402_1%

R1498

R1499

100_0402_1%

BT_OFF#_R

APU_PCIE_WLAN_WAKE#

WLAN_CLKREQ#

+3VS_WLAN

1 2

For EC to detect debug card insert.

R1501

R1501 100K_0402_5%

100K_0402_5%

B

JWLN1

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

GND1

BELLW_80003-8041

ME@

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

GND2

Issued Date

APU_SCLK0_W APU_SDATA0_W

APU_PCIE_RST#

+3VS_WLAN

1 2

R1496 0_0402_5%@R1496 0_0402_5%@

1 2

R1497 0_0402_5%@R1497 0_0402_5%@

USB20_N5 USB20_P5

Compal Secret Data

2012/04/22 2015/04/22

C

Compal Secret Data

Deciphered Date

WL_OFF#

APU_PCIE_RST#

APU_SCLK0 <6,8,9> APU_SDATA0 <6,8,9>

USB20_N5 USB20_P5

<6> <10,6>

<5> <5>

D

+3VS_WLAN+3VS

J7

J@

2

112

JUMP_43X79

Compal Electronics, Inc.

Title

MINI1 CARD (WLAN) / MINI2 CARD (Option)

Size Document Number Rev

B

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

VAWGA/GB

of

26 48Thursday, March 28, 2013

E

1.0

5

Right Ext.USB Conn.

+5VALW

R02

U36

D D

USB2R@

220U_6.3V_M

6.3Φ * 5.9 SF000001500

C C

+USB_VCCB

C714

C713 0.1U_0402_16V4Z

<28>

12

USB2R@

W=80mils

1

<5>

+

<5>

2

USB20_N0

USB20_P0

C715

C715 470P_0402_50V7K

470P_0402_50V7K

2

USB2R@

USB20_N0

USB20_P0

USB_ON#

1

4

EMIUSB2RP@

L66

1

4

U36

1

GND

2

VIN VIN3VOUT

4

EN

G547I2P81U_MSOP8

USB2R@

WCM-2012-900T_ 4P

2

3

2A/Active Low

+5VALW +USB3_VCCA

R02

U35

5

U2DP1

U2DN0

1 2

4

U35

GND VIN VIN3VOUT EN

G547I2P81U_MSOP8

8

VOUT

7

VOUT

6 5

FLG

D34

ESDU@

3

I/O2

2

GND

1

I/O1

AZC099-04S.R7G_SOT23- 6

D22

ESDU@

3

I/O2

2

GND

1

I/O1

AZC099-04S.R7G_SOT23- 6

I/O4

VDD

I/O3

I/O4

VDD

I/O3

W=80mils

6

5

4

6

5

4

C704

0.1U_0402_16V4Z

1 2

B B

+USB3_VCCA

A A

C736

220U_6.3V_M

SF000002Y00

1

+

2

USB_ON#

C735

1

470P_0402_50V7K

2

+USB_VCCB

VOUT VOUT

FLG

EMIUSB2RU@

R900 0_0402_5%

R900 0_0402_5% R896 0_0402_5%

R896 0_0402_5%

EMIUSB2RU@

USB20_N0_C

USB20_P0_C

USB_OC1#

+5VALW

U2DN1

+5VALW

U2DP0

4

8 7 6 5

12 12

RIGHT USB PORT X1

USB_OC0#

USB20_N0_C USB20_P0_C

2

3

D25

ESDU@D25

ESDU@

1

PJDLC05_SOT23-3

U3RXDP0

<6>

4

U3TXDN0

U3TXDP0

U3RXDN1 U3RXDN1

U3TXDN1

U3TXDP1

<6>

JUSB3

ME@JUSB3

ME@

8

GND

7

GND

6

5

4

3

2

1

ACES_88058-060N

D27

ESDU@

9

10

8

9

7

6

6 5

YSCLAMP0524P_SLP2510P8-10-9

ESDU@

9

10

8

9

7

6

6 5

YSCLAMP0524P_SLP2510P8-10-9

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D30

1

U3RXDN0U 3RXDN0

1

2

U3RXDP0

2

4

U3TXDN0

4

5

U3TXDP0

3

8

1

2

U3RXDP1U3RXDP1

2

4

U3TXDN1

4

5

U3TXDP1

3

8

3

<5>

USB20_N6

USB20_P6

USB30_N8

USB30_P8

1 2

0_0402_5%

1 2

0_0402_5%

1 2

0_0402_5%

1 2

0_0402_5%

R567

R569

R574

R575

@R567

@

@R569

@

U2DN0_L

U2DP0_L

Colay with USB2.0 only

<5>

USB30_MRX_DTX_N0

<5>

USB30_MRX_DTX_P0

C858

0.1U_0402_16V7K

<5>

USB30_MTX_C_DRX_N0

<5>

USB30_MTX_C_DRX_P0

<5>

USB20_N7

USB20_P7

USB30_N9

USB30_P9

1 2

0_0402_5%

1 2

0_0402_5%

1 2

0_0402_5%

1 2

0_0402_5%

U3TXDN0_L U3TXDN0

U3TXDP0_L

C859

0.1U_0402_16V7K

U2DN1_L

R570

@R570

@

U2DP1_L

R571

@R571

@

R572

R573

Colay with USB2.0 only

<5>

USB30_MRX_DTX_N1

<5>

USB30_MRX_DTX_P1

C856

0.1U_0402_16V7K

1 2

<5>

USB30_MTX_C_DRX_N1

<5>

USB30_MTX_C_DRX_P1

Compal Secret Data

2012/04/22 2015/04/22

3

Compal Secret Data

Deciphered Date

U3TXDN1_L

1 2

U3TXDP1_L

C857

0.1U_0402_16V7K

2

EMIU@

1 2

R566

0_0402_5%

L51

EMIP@

4

1

WCM-2012-900T_ 4P

1 2

R562

0_0402_5%

EMIU@

WCM-2012HS-900T

1

4

EMIP@

L50

WCM-2012HS-900T

1

4

L49

EMIP@L49

EMIP@

1 2

L55

4

1

WCM-2012-900T_ 4P

1 2

WCM-2012HS-900T

1

4

L54

WCM-2012HS-900T

1

4

L53

2

1

3

U2DN0

3

2

U2DP0

2

U3RXDN0

2

3

U3RXDP0

3

2

3

U3TXDP0

3

EMIU@

R728

R728 0_0402_5%

0_0402_5%

EMIP@

R721

R721 0_0402_5%

0_0402_5%

EMIU@

EMIP@

3

U2DN1

3

2

U2DP1

2

3

2

U3TXDN1

2

3

U3TXDP1

3

EMIP@

Title

USB2.0 / USB3.0 / BT

Size Document Number Rev

B

Date: Sheet of

+USB3_VCCA

W=80mils

JUSB1

U3TXDP0+USB_VCCB

U3TXDN0 U2DP0

U2DN0 U3RXDP0

U3RXDN0

U3RXDN1

U3RXDP1

U3TXDP1

U3TXDN1 U2DP1

U2DN1 U3RXDP1

U3RXDN1

Compal Electronics, Inc.

VAWGA/GB

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND

2

D-

6

SSRX+

4

GND

5

SSRX-

TAITW_PUBAU1-09FNLSC NN4H0

ME@

+USB3_VCCA

W=80mils

JUSB2

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND

2

D-

6

SSRX+

4

GND

5

SSRX-

TAITW_PUBAU1-09FNLSC NN4H0

ME@

LP1 Port0

10

GND

11

GND

12

GND

13

GND

LP2 Port1

GND GND GND GND

27 48Thursday, March 28, 2013

1

10 11 12 13

1.0

5

L44

FBM-11-160808-601-T_0603

1 2

D D

C1263 22P_0402_50V8J

<5,6>

C C

Pull high in APU side

B B

0.1U_0402_16V4Z

1 2

FBM-11-160808-601-T_0603

EMIU@

12

LPC_CLK0_EC

+3V_EC

KSO[0..17]

KSI[0..7]

L43

1

C1262

2

ECAGND

R1560

EMIU@

10_0402_5%

12

R818 47K_0402_5%R818 47K_0402_5%

12

C819 0.1U_0402_16V4ZC819 0.1U_0402_16V4Z

KSO[0..17]

KSI[0..7]

Pull high in ODD side

<6>

A A

RTC_CLK

PXS_PWREN<12,39,6>

5

+EC_VCCA+3V_EC

1

C1260

C1260 1000P_0402_50V7K

1000P_0402_50V7K

2

<6> <6> <5> <5,6> <5> <5> <5>

12

<5>

<6>

<6> <34>

<30>

<34,35> <34,35> <11,29,4> <11,29,4>

<6> <6> <6> <21>

<39> <23> <33> <29> <24> <26> <26> <6>

1 2

R836 0_0402_5%@R836 0_0402_5%@

GATEA20

KBRST#

SERIRQ

LPC_FRAME#

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

LPC_RST#

EC_SCI# BATT_LEN#

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

SLP_S3#

SLP_S5# EC_SMI# CMOS_ON#

EC_VGA_EN ODD_DA# ADP_ID_CLOSE

EC_TACH

LAN_WAKE#

EC_TX

SYS_PWRGD_EC

100K_0402_5%

C1255

0.1U_0402_16V4Z

C1255

0.1U_0402_16V4Z

EC_RX

NOVO#<30>

R1587

1

2

12

@

C1256

0.1U_0402_16V4Z

C1256

0.1U_0402_16V4Z

12

@ C1271

@

4

+3VALW

J11

J@

2

112

JUMP_43X79

C1257

0.1U_0402_16V4Z@C1257

0.1U_0402_16V4Z

C1258

0.1U_0402_16V4Z@C1258

0.1U_0402_16V4Z

1

2

@

GATEA20 KBRST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

LPC_CLK0_EC

LPC_RST# EC_RST# EC_SCI#

BATT_LEN#

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

EC_SMB_CK1

EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

SLP_S3#

SLP_S5# EC_SMI# CMOS_ON#

EC_VGA_EN ODD_DA# ADP_ID_CLOSE EC_TACH LAN_WAKE# EC_TX EC_RX SYS_PWRGD_EC 095VS_PWR_EN NOVO#

XCLKO PXS_PWREN

C1271 20P_0402_50V8

20P_0402_50V8

4

+3V_EC

C1261

1000P_0402_50V7K

C1261

1000P_0402_50V7K

C1259

1000P_0402_50V7K

C1259

1000P_0402_50V7K

1

2

U44

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC & MISC

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCII#/GPIO0E

38

GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CK1/GPIO44

78

EC_SMB_DA1/GPIO45

79

EC_SMB_CK2/GPIO46

80

EC_SMB_DA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

GPIO0D

25

EC_INVT_PWM/GPIO11

28

FAN_SPEED1/GPIO14

29

EC_PME#/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

XCLKI/GPIO5D

123

XCLKO/GPIO5E

KB9012QF-A3_LQFP128_14X14

Part Number = SA00004OB30

J12

112

JUMP_43X79

1

2

Int. K/B

Int. K/B Matrix

Matrix

SM Bus

+3VLP

J@

2

1

C1254

C1254 100P_0402_50V8J

100P_0402_50V8J

2

+3V_EC

+EC_VCCA

9

22

33

96

125

111

67

EC_VDD0

EC_VDD/VCC

EC_VDD/AVCC

PWM Output

BATT_TEMP/AD0/GPIO38

AD Input

DA Output

PS2 Interface

CPU1.5V_S3_GATE/GPXIOA00

SPI Device Interface

SPI Flash ROM

GPIO

GND/GND

11

24

35

VCIN0_PH/GPXIOD00

PECI_KB930/AD7/GPIO41

BATT_CHG_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO55

PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04

PROCHOT_IN/GPXIOA05

H_PROCHOT#_EC/GPXIOA06

VCOUT0_PH/GPXIOA07

GPO

PBTN_OUT#/GPXIOA09

PCH_APWROK/GPXIOA10

SA_PGOOD/GPXIOA11

GPI

PECI_KB9012/GPXIOD07

GND/GND

AGND/AGND

GND/GND

GND0

69

94

113

20mil

ECAGND

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

GPIO0F

BEEP#/GPIO10

GPIO12

ACOFF/GPIO13

AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B AD4/GPIO42

IMON/AD5/GPIO43

DAC_BRIG/GPIO3C

EN_DFAN1/GPIO3D

IREF/GPIO3E

CHGVADJ/GPIO3F

EC_MUTE#/GPIO4A

USB_EN#/GPIO4B

CAP_INT#/GPIO4C

EAPD/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

WOL_EN/GPXIOA01

ME_EN/GPXIOA02

SPIDI/GPIO5B

SPIDO/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A

ENBKL/AD6/GPIO40

FSTCHG/GPIO50

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

SYSON/GPIO56

VR_ON/GPIO57

BKOFF#/GPXIOA08

AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF/GPXIOD03

LID_SW#/GPXIOD04

SUSP#/GPXIOD05

GPXIOD06

V18R

3

3.3V +/- 5%

Vcc

100K +/- 5%

R1562

Board ID

+5VALW

R1266

1 2

USB_ON#

10K_0402_5%

21

ADP_65

23

BEEP#

26

EC_FAN_PWM

27

ACOFF

63

BATT_TEMP

64

GPU_IMON

65

ADP_I

66

ADP_ID

75

BRDID

76

ENBKL

68

ADP_90

70 71 72

83

EC_MUTE#

84

USB_ON#

85

ADP_135

86 87

TP_CLK

88

TP_DATA

97

EC_TS_ON#

98 99

095VS_PWR_EN

109

NTC_V

119

EC_SPI_AISO

120

EC_SPI_AOSI

126

EC_SPI_CLK

128

EC_SPI_CS1#

73

APU_IMON

74

VGATE

89

LAN_PWR_ON#

90

BATT_CHG_LED#

91

CAPS_LED#

92

PWR_LED#

93

BATT_LOW_LED#

95

SYSON

121

VR_ON

127

095_18ALW_PWR_EN

100

EC_RSMRST#

101

EC_LID_OUT#

102

Turbo_V

103 104 105

BKOFF#

106

PBTN_OUT#

107 108

110

ACIN

112

EC_ON

114

ON/OFF

115

LID_SW#

116

SUSP#

117 118

124

+V18R

2012/04/22 2015/04/22

ADP_65 BEEP# EC_FAN_PWM ACOFF

BATT_TEMP

GPU_IMON ADP_I ADP_ID

ENBKL

ADP_90

EC_MUTE# USB_ON#

ADP_135

TP_CLK TP_DATA

EC_TS_ON#

095VS_PWR_EN

NTC_V <34>

EC_SPI_AISO EC_SPI_AOSI EC_SPI_CLK EC_SPI_CS1#

APU_IMON <40>

VGATE <40> LAN_PWR_ON# BATT_CHG_LED#

CAPS_LED#

PWR_LED# <30> BATT_LOW_LED#

SYSON VR_ON 095_18ALW_PWR_EN

EC_RSMRST# EC_LID_OUT#

BKOFF# PBTN_OUT#

ACIN

EC_ON

ON/OFF

SUSP#

ESDP@ C601

ESDP@

1

C823

4.7U_0603_6.3V6K

2

Compal Secret Data

Deciphered Date

0 1 2 3

1

C601 1000P_0402_50V7K

1000P_0402_50V7K

2

PROCHOT

R1564 V

8.2K +/- 5%

18K +/- 5%

33K +/- 5%

<34> <31> <29> <35>

MP

<34> <39> <34,35> <33>

<4>

<34>

<31> <27> <34>

<30> <30>

<26>

<32>

<5> <5> <5> <5>

<24> <30> <30>

<30> <32,37> <40> <37,38>

<6> <6>

<21> <6>

<11,35> <36> <30>

<32,37>

2N7002H_SOT23-3

2

0

BRDID

+3VLP

Q82

2

12

AD_BID

0 V

min

typ

V

AD_BID

0 V 0 V

0.216 V 0.250 V 0.289 V

@

R343

R343 47K_0402_5%

47K_0402_5%

13

D

2

G

S

0.436 V

0.712 V

+3VALW

12

@

12

Turbo_V PROCHOT MAINPWON

LID_SW#

0.503 V

0.819 V

R1562

R1562 100K_0402_5%

100K_0402_5%

R1564

R1564 0_0402_5%

0_0402_5%

<34> <34> <36>

<30>

H_PROCHOT#

1

C1269

C1269 47P_0402_50V8J

47P_0402_50V8J

2

Title

Size Document Number Rev

Custom

VAWGA/GB

Date: Sheet of

Date: Sheet

V

AD_BID

0.538 V

0.875 V

TP_CLK

TP_DATA

EC_FAN_PWM

EC_TACH

EC_SMB_DA2

EC_SMB_CK2

EC_SMB_DA1

EC_SMB_CK1

EC_MUTE#

LAN_WAKE#

LID_SW#

For share ROM need

SYS_PWRGD_EC

095_18ALW_PWR_EN

EC_RSMRST#

BATT_TEMP

ACIN

ENBKL

<34,4,40,6>

Compal Electronics, Inc.

EC ENE KB930/9012

1

max

MP PVT DVT EVT

1 2

R1568 4.7K_0402_5%R1568 4.7K_0402_5%

1 2

R1570 4.7K_0402_5%R1570 4.7K_0402_5%

1 2

R1561 10K_0402_5%@R1561 10K_0402_5%@

1 2

R1581 10K_0402_5%R1581 10K_0402_5%

1 2

R1579 2.2K_0402_5%@R1579 2.2K_0402_5%@

1 2

R1578 2.2K_0402_5%@R1578 2.2K_0402_5%@

1 2

R1577 2.2K_0402_5%R1577 2.2K_0402_5%

1 2

R1574 2.2K_0402_5%R1574 2.2K_0402_5%

1 2

R1565 10K_0402_5%@R1565 10K_0402_5%@

1 2

R1566 10K_0402_5%R1566 10K_0402_5%

1 2

R344 47K_0402_5%R344 47K_0402_5%

1 2

R208 100K_0402_5%R208 100K_0402_5%

1 2

R1575 100K_0402_5%R1575 100K_0402_5%

1 2

R1576 100K_0402_5%R1576 100K_0402_5%

1 2

C1265 100P_0402_50V8JC1265 100P_0402_50V8J

1 2

C1266 100P_0402_50V8JC1266 100P_0402_50V8J

1 2

@

R1573 4.7K_0402_5%

1 2

R207 100K_0402_5%R207 100K_0402_5%

1 2

R206 100K_0402_5%R206 100K_0402_5%

of

28 48Thursday, March 28, 2013

1

+5VS

+3VS

+3V_EC

+3VALW

1.0

5

D D

<11>

4

REMOTE1+

C587

2200P_0402_50V7K

REMOTE1-

2200P_0402_50V7K

1

THERMAL@C587

THERMAL@

2

3

+3VGS

SMSC thermal sensor

2

C329

0.1U_0402_16V4Z

@

REMOTE1+ EC_SMB_DA2

REMOTE1-

1 2

R335

+3VGS

R335

4.7K_0402_5%

@

placed near APU

1

EMC1402-2-ACZL-TR MSOP 8P

2

U9

THERMAL@U9

THERMAL@

1

VDD

2

D+

3

D-

THERM#4GND

Address is 1001100xb

SCLK

SDATA

ALERT#

1

8

7

6

5

EC_SMB_CK2

EC_SMB_DA2

<11,28,4>

REMOTE1,2+/-: Trace width/space:10/10 mil Trace length:<8"

C C

CPU

H3

H2

H1

H1 HOLEA

HOLEA

1

H_3P8

+5VS_FAN

FAN1 Conn

JFAN1

1

2

3

4

5

G5

6

G6

ACES_85205-04001

ME@

4

H6

H6 HOLEA

HOLEA

1

H_2P8

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

B B

+5VS

@

R581 0_0603_5%

<28>

2

C591

C591 10U_0603_6.3V6M

10U_0603_6.3V6M

1

10U

A A

5

12

EC_TACH

EC_FAN_PWM<28>

HOLEA

1

H_3P8

H8

H7

HOLEA

1

H_2P8

2P8 * 9 pcd

Compal Secret Data

Deciphered Date

VGA_L VGA_R HDD

H5

H4

H4 HOLEA

HOLEA

1

H_3P3

H5 HOLEA

HOLEA

1

H_3P3

BA

H11

H10

HOLEA

1

H_2P8

D

H18

H18 HOLEA

HOLEA

1

H_2P8

FD1FD1

FD2FD2

1

FD3FD3

FD4FD4

1

C

R

H16

H16 HOLEA

HOLEA

1

H_2P5X3P5N

E

M/B

橢橢橢

Compal Electronics,Ltd.

Title

Fintek-Thermal IC/FAN/screw

Size Document Number Rev

B

Date: Sheet of

2

Date: Sheet of

VAWGA/GB

H17

H17 HOLEA

HOLEA

1

H_3P0N

F

M/B

1

橢橢

29 48Thursday, March 28, 2013

1.0

<28> <28>

+5VS

4

3

4

3

SWP1SMT1-05_4P @SWP1SMT1-05_4P @

6

SWP0SMT1-05_4P @SWP0SMT1-05_4P @

6

3

4

5

3

4

5

C696

0.1U_0402_16V4Z

TP_CLK TP_DATA

1

2

1

2

L R

SW4

14@SW4

14@

TJG-533-V-T/R_6P

5

6

5

6

2

1

SW6

15@SW6

15@

TJG-533-V-T/R_6P

2

1

TP_3

TP_2 TP_1

+3VLP

1 2

R701

R701 100K_0402_5%

100K_0402_5%

5

6

4

3

5

6

4

3

ON/OFF

15@

12

R628

R628 0_0402_5%

0_0402_5%

12

R629

14@R629

14@

0_0402_5%

SW5

14@SW5

14@

TJG-533-V-T/R_6P

2

1

SW7

15@SW7

15@

TJG-533-V-T/R_6P

2

1

TP_3

TP_1

<28>

ON/OFF

TP_CLK TP_DATA TP_3 TP_2 TP_1

TP_2

NOVO#

<28>

JTP1

ME@JTP1

ME@

8

GND

7

GND

6

5

4

3

2

1

ACES_88058-060N

1

VCC

2

CLK

3

DAT

4

GND

5

L

6

R

+3VLP

USB20_N4 USB20_P4

PWR_LED#<28>

KSI[0..7]

KSO[0..17]

USB20_N4

USB20_P4

PWR_LED#

ON/OFF

NOVO#

R643

R643 100K_0402_5%@

100K_0402_5%@

1 2

+3VALW

R642

R642 100K_0402_5%

100K_0402_5%

1 2

@

12

R630

R630 0_0402_5%

0_0402_5%

D26

2

1

3

DAN202UT106_SC70-3

<5> <5>

NOVO_BTN#

14"15/17"

1

VCC

2

CLK

3

DAT

4

L

5

R

GND

6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

BATT_LOW_LED#<28>

BATT_CHG_LED#<28>

CAPS_LED#<28>

2012/04/22 2015/04/22

BATT_LOW_LED#

BATT_CHG_LED#

CAPS_LED#

Compal Secret Data

KSI[0..7]

KSO[0..17]

USB20_N4 USB20_P4

Deciphered Date

1

4

LED1

19-213A-T1D-CP2Q2HY-3T_WHITE

LED2

HT-191UD5_AMBER

LED5

19-213A-T1D-CP2Q2HY-3T_WHITE

LED6

19-213A-T1D-CP2Q2HY-3T_WHITE

WCM-2012-900T_4P

L67

1

4

EMICP@

R692 0_0402 _5%EMICU@R692 0_0402_5%EMICU@ R687 0_0402 _5%EMICU@R687 0_0402_5%EMICU@

14@

21

14@LED2

14@

21

14@LED5

14@

21

14@

21

<28>

R623

R623 649_0402_1%

649_0402_1%

14@

470_0402_5%

2

3

12 12

<28>

12

R764

14@

R765

R765 649_0402_1%

649_0402_1%

14@

R303

R303 649_0402_1%

649_0402_1%

14@

12

JKB1

ME@JK B1

ME@

1

KSI1

1

2

KSI7

2

3

KSI6

3

4

KSO9

4

5

KSI4

5

6

KSI5

6

7

KSO0

7

8

KSI2

8

9

KSI3

9

10

KSO5

10

11

KSO1

11

12

KSI0

12

13

KSO2

13

14

KSO4

14

15

KSO7

15

16

KSO8

16

17

KSO6

17

18

KSO3

18

19

KSO12

19

20

KSO13

20

21

KSO14

21

22

KSO11

22

23

KSO10

23

24

KSO15

24

25

KSO16

25

26

KSO17

26

27

28

29 30

ACES_88514-3001

USB20_N4_R

USB20_P4_R

USB20_N4_R USB20_P4_R

LID_SW#

+5VALW

PJSOT24C 3P C/A SOT-23

+3VALW

+5VALW

+5VS

Title

BIOS, I/O Port & K/B CONN/TP CONN/PBTN

Size Document Number Rev

B

Date: Sheet of

31

GND

29

32

GND

30

+3VS

+3VALW

2

C185

ESDP@ C185

ESDP@

0.1U_0402_16V7K

ESDP@

D24

+5VALW +3VALW

VAWGA/GB

1

NOVO_BTN# ON/OFF

2

3

1

+5VS

LID_SW#

PWR_LED# BATT_LOW_LED# BATT_CHG_LED# CAPS_LED#

Compal Electronics, Inc.

KSO12 KSO13 KSO14 KSO11 KSO10 KSO15

JCR1

1

2

3

4

GND GND

CVILU_CF06041H0RB-NH

ME@

ACES_88058-060N

26 25

24

KSI1

23

KSI7

22

KSI6

21

KSO9

20

KSI4

19

KSI5

18

KSO0

17

KSI2

16

KSI3

15

KSO5

14

KSO1

13

KSI0

12

KSO2

11

KSO4

10

KSO7

9

KSO8

8

KSO6

7

KSO3

6 5 4 3 2 1

ACES_88514-2401

5 6

JPWRB1

1

2

3

4

5

6

7

GND

8

GND

ME@

JLED1

1

2

3

4

5

6

7

8

9

10

11

GND

12

GND

HB_A091020-SAHR21

ME@

30 48Thursday, March 28, 2013

JKB2

GND2 GND1

24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

ME@JKB2

ME@

1.0

5

1 2

RA11 0_0402_5%@RA11 0_0402_5%@

+3VLP

1

2

0.1U_0402_16V7K

1

CA17

2

0.1U_0402_16V7K

HDA_RST#_AUDIO

HDA_BITCLK_AUDIO HDA_SYNC_AUDIO HDA_SDIN0_R HDA_SDOUT_AUDIO

1

CA5

2

PC_BEEP

MIC_IN

SPK_L2+ SPK_L1-

SPK_R2+ SPK_R1-

0.1U_0402_16V7K

1 2

@

+3VALW

D D

Should be same supply rail as used for PCH HDA bus controller section

+3VS

+1.5VS

1 2

RA4 0_0402_5%@RA4 0_0402_5%@

For EMI

<6>

C C

<6>

HDA_SYNC_AUDIO <6> <6>

HDA_SDIN0

HDA_SDOUT_AUDIO

<28>

<6>

EC_MUTE#

HDA_RST#_AUDIO

HDA_BITCLK_AUDIO

@

RA10 0_0402_5%

1

CA8

2

@

1

CA16

2

@

EMIU@

1 2

33_0402_5%

1 2

EMIU@

RA21

CA7

22P_0402_50V8J

RA9 33_0402_5%RA9 33_0402_5%

CA9

1U_0603_10V6K

4.7U_0603_6.3V6K

Internal analog MIC

Internal SPEAKER

using wide copper bridge under codec (100 mils or more)

B B

PC Beep

EMIU@

1 2

CA64 0.1U _0603_50V7K

EMIU@

1 2

CA65 0.1U _0603_50V7K

EMIU@

1 2

CA66 0.1U _0603_50V7K

Place colose to Codec chip

+MICBIASC

12

RA23

2.2K_0402_5%

A A

MIC1

1 2

GNDA

1

WM-64PCY_2P

45@

1

2

CA42

CA44

0.1U_0402_16V7K

@

2.2K_0402_5%

CA41 1U_0603_10V6KCA41 1U_0603_10V6K

CA41 vendor suggest change to 1U

0.1U_0402_16V7K

5

1 2

EC Beep

ICH Beep

MIC_INMIC_IN_C

APU_SPKR<6>

ESD

SPK_R2+_CONN

CA6

@

+3VS

+LDO_1.8V

1

CA24

2

BEEP#<28>

1

2

4.7U_0603_6.3V6K

+5VS

4.7U_0603_6.3V6K

CA25

4

+AVDD_HP

1

2

4

+VREF_1V65

1

CA1

2

1

@

CA15

2

@

CA10

2

1U_0603_10V6K

0.1U_0402_16V7K

10 mils

3

7

UA1

0.1U_0402_16V7K

VDD_IO

9

5 8 6 4

10 39

1

40

36 37

12 14

17 15

6

5

4

FILT_1.8

RESET#

BIT_CLK SYNC SDATA_IN SDATA_OUT

PC_BEEP SPKR_MUTE#

DMIC_DAT/GPIO1 DMIC_CLK / MUSIC_REQ/GPIO0

MUSIC_REQ/GPIO0/PORTC_L_MIC GPIO1/PORTC_R_MIC

LEFT+ LEFT-

RIGHT+ RIGHT-

GND

41

1 2

CA37 0.1U_0402_16V7KCA37 0.1U_0402_16V7K

1 2

CA45 0.1U_0402_16V7KCA45 0.1U_0402_16V7K

DA3

I/O4

I/O2

VDD

GND

I/O3

AZC099-04S.R7G_SOT23-6

ESDU@

I/O1

CA2

1U_0603_10V6K

18

2

DVDD_3.3

VDDO_3.3

@ RA22

@

3

2

1

CA3 vendor suggest change to 2.2U

1

2

0.1U_0402_16V7K

27

24

28

29

AVDD_5V

AVDD_3.3

AVDD_HP

CLASS-D_REF

VREF_1.65V

PORTB_L_LINE

PORTB_R_LINE

PORTD_A_MIC PORTD_B_MIC

CX20751-11Z_QFN40

RA492

1 2

33_0402_5%

12

RA22 10K_0402_5%

10K_0402_5%

SPK_L2+_CONNSPK_R1-_CONN

SPK_L1-_CONN

3

+LDO_OUT_3.3V

2

CA3

1

LPWR_5.0

RPWR_5.0

JSENSE

MICBIASB

MICBIASC

HGNDA HGNDB

PORTA_L

PORTA_R

AVEE

FLY_P

FLY_N

AVDD_3.3 pinis output of

1

internal LDO. NOT connec t

CA4

to external supply.

2

0.1U_0402_16V7K

2.2U_0603_6.3V6K

Layout Note:Path from +5VS to LPWR_5.0

RPWR_5.0 must be very low resistance (<0.01 ohms)

+5VS

1

CA18

CA19

@

2

0.1U_0402_16V7K

4.7U_0603_6.3V6K

13 16 11

38

34 35

32 33

30 31 25 26

22 23

21 19 20

4.7U_0603_6.3V6K

PC_BEEP

SPK_R1SPK_R2+ SPK_L1-

JSENSE

MICB_L

MICB_R

APPLE_MIC NOKIA_MIC

HGNDA HGNDB

HP_L

HP_R

1 2

CA29 1U_0603_10V6KCA29 1U_0603_10V6K

EMIP@ LA1

EMIP@

EMIP@ LA3

EMIP@

CA26

+MICBIASB +MICBIASC

Universal Jack

External MIC

Headphone

LA1 0_0603_5%

0_0603_5%

LA3 0_0603_5%

0_0603_5%

1 2

LA1 FBMA-L11-160808-121LMT_0603EM IU@LA1 FBMA-L11-160808-121LMT_060 3EMIU@

1 2

LA2 FBMA-L11-160808-121LMT_0603EM IU@LA2 FBMA-L11-160808-121LMT_060 3EMIU@

1 2

LA3 FBMA-L11-160808-121LMT_0603EM IU@LA3 FBMA-L11-160808-121LMT_060 3EMIU@

1 2

LA4 FBMA-L11-160808-121LMT_0603EM IU@LA4 FBMA-L11-160808-121LMT_060 3EMIU@

1

2

0.1U_0402_16V7K

LA2 0_0603_5%

0_0603_5%

LA4 0_0603_5%

0_0603_5%

wide 30MIL

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

1

CA20

2

CA22

CA21

@

2

0.1U_0402_16V7K

Please bypass caps very close to device.

APPLE_MIC HGNDB NOKIA_MIC HGNDA HP_L HPOUT_ L

2

1

CA30

CA35

1

2

0.1U_0402_16V7K

2.2U_0603_6.3V6K

CA30 vendor suggest change to 2.2U

EMIP@LA2

EMIP@

EMIP@LA4

EMIP@

LA1~LA4 vendor suggest mount 0 ohm first~ Bead reserve for EMI if needed

SPK_R1-_CONN SPK_R2+_CONN SPK_L1-_CONN SPK_L2+_CONNSPK_L 2+

vendor suggest change to 1000p

Compal Secret Data

1

CA23

2

4.7U_0603_6.3V6K

RA16 100_0402_1%EMIP@RA16 100_0402_1%EMIP@ RA12 100_0402_1%EMIP@RA12 100_0402_1%EMIP@ RA13 15_0402_5%EMIP@RA13 15_0402_5%EMIP@ RA14 15_0402_5%EMIP@RA14 15_0402_5%EMIP@

+MICBIASB

Deciphered Date

JSENSE

4.7U_0603_6.3V6K

1 2 1 2 1 2 1 2

EMIP@

1

CA38

2

1 2

RA5 5.11K_0402_1%RA5 5.11K_0402_1%

RA6 10K_0402_1%RA6 10K_0402_1%

1 2

RA7 20K_0402_1%RA7 20K_0402_1%

1 2

RA8 39.2K_0402_1%RA8 39.2K_0402_1%

For Universal jack

MICB_L HP_L

MICB_R HP_R

EMIP@

1

CA39

2

1000P_0402_50V7K

1 2

RA17 100_0402_1%RA17 100_0402_1%

1 2

RA18 100_0402_1%RA18 100_0402_1%

1 2

RA20 3K_0402_5%RA20 3K_0402_5%

1 2

RA19 3K_0402_5%RA19 3K_0402_5%

EMIP@

1

CA43

CA40

2

1000P_0402_50V7K

2

+5VS

HGNDA, HGNDB 80mils

1 2

CA28 2.2U _0402_6.3V6MCA28 2.2U_0402_6.3V6M

1 2

CA27 2.2U _0402_6.3V6MCA27 2.2U_0402_6.3V6M

HPOUT_L

HPOUT_R

HGNDB

HGNDA

12

CA31

CA32

100P_0402_50V8J

1

2

1000P_0402_50V7K

Date: Sheet

Date: Sheet of

1

Sense resistors must be connected same power that is used for VAUX_3.3

+3VS

mount RA6 on the Jack Sense circuit to configure Port-C for mono MIC.

PLUG_IN

Don't support LINE_IN function RA7 could be @

Combo Jack (Normal Open)

JHP1

4 3 1

HPOUT_RHP_R

PLUG_IN

CA36

1 2

2.2U_0402_6.3V6M

CA46

1 2

2.2U_0402_6.3V6M

12

CA33

CA34

100P_0402_50V8J

Title

Size Document Number Rev

Custom

100P_0402_50V8J

Compal Electronics, Inc.

2

5

6

SINGA_2SJ2352-000131F

ME@

ESD

HPOUT_L

HPOUT_R

HGNDB

HGNDA

2

3

DA1

ESDP@

1

AZ5125-02S.R7G_SOT23-3

CX20751 Codec

VAWGA/GB

1

2

3

ESDP@

1

AZ5125-02S.R7G_SOT23-3

1 2 3 4 5 6

ACES_85205-04001

of

31 48Thursday, March 28, 2013

DA2

JSPK1

1 2 3 4 G5 G6

ME@

1.0

A

+5VALW TO +5VS

+5VALW

VIN 5V and 3.3V (VBIAS=5V),IM AX(per channel) =6A,Rds=18mohm

+3VALW TO +3VS

C12

Load switch

1 1

1

@

1U_0402_6.3V6K

2

+3VALW

@ C11

@

VL

1

C11

1U_0402_6.3V6K

2

SUSP#

B

U35P

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

TPS22966DPUR_SON14_2X3

VOUT1 VOUT1

GND

VOUT2 VOUT2

GPAD

C

+5VS

J5V

J@

14

+5VS_LS

13

12

CT1

11

10

CT2

9 8

15

C10 180P_0 402_50V8J

1 2

@

C9 330P_0402_50V7K

1 2

@

+3VS_LS

1 2

PAD-OPEN 4x4m

J3V

J@

1 2

PAD-OPEN 4x4m

J@

+3VS

@ C14

@

2

1

C14

0.1U_0402_16V4Z

2

@ C13

@

1

C13

0.1U_0402_16V4Z

D

E

+1.8VALW

1U_0402_6.3V6K

+1.8VALW TO +1.8VS +0.95VALW TO +0.95VS Load switch

2 2

+1.5V to +1.5VS

C470

10U_0603_6.3V6M

SUSP#

+5VALW

12

100K_0402_5%

100K_0402_5% R337

R337

1.5VS_GATE 1.5VS_GATE_R

13

D

2

G

S

3 3

+1.5V +1.5VS

1

LP2301ALT1G_SOT23-3

2

1 2

0_0402_5%

Q26

Q26 2N7002K_SOT23-3

2N7002K_SOT23-3

3 1

R339

@

Q20

2

1U_0402_6.3V6K

@

<28>

1

@

C469

C469 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

C462

0.1U_0402_16V4Z

2

C24

1

2

095VS_PWR_EN

VIN 1.8V and 0. 95V (VBIAS=5V) ,IMAX(per chann el)=6A,Rds=18m ohm

U1895P

+0.95VALW

1

C22

@ C22

@

1U_0402_6.3V6K

2

VL

SUSP#

095VS_PWR_EN

U1895P

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

TPS22966DPUR_SON14_2X3

VOUT1 VOUT1

CT1

GND

CT2

VOUT2 VOUT2

GPAD

14 13

12

11

10

9 8

15

Vgs=-4.5V,Id=-2 .8A,Rds=110moh m

1

C463

C463 1U_0603_10V6K

1U_0603_10V6K

2

12

R1461

R1461 220_0603_5%

220_0603_5%

13

D

2

G

Q23

S

2N7002K_SOT23-3

SUSP

<28,37>

+1.8VS_LS

C21 180P_0402_50V 8J

1 2

@

C15 330P_0402_50V 7K

1 2

@

+0.95VS_LS

SUSP#

J18V

1 2

PAD-OPEN 4x4m

J95V

J@

1 2

PAD-OPEN 4x4m

SUSP

+1.8VS

J@

2

C26

@ C26

@

0.1U_0402_16V4Z

1

+0.95VS

2

C25

@ C25

@

0.1U_0402_16V4Z

1

+RTCBATT_3V

R1636

R1636 100K_0402_5%

100K_0402_5%

1 2

DTC124EKAT146_SC59-3

2

12

R1639

@R1639

@

100K_0402_5%

+1.5V +0.75VS

12

R1627

R1627 470_0603_5%

470_0603_5%

@

13

D

2

G

Q93

S

2N7002K_SOT23-3

@

Q101

1

OUT

IN

GND

3

<28,37>

SYSON

D

S

SYSON#

SYSON

12

13

R1629

R1629 470_0603_5%

470_0603_5%

@

2

SUSPSYSON#

G

Q95

Q95 2N7002K_SOT23-3

2N7002K_SOT23-3

@

100K_0402_5%

12

R1640

R1640 100K_0402_5%

100K_0402_5%

+5VALW

12

@

R1638

1

OUT

Q102

2

IN

Q102 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

@

GND

3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/04/22 2015/04/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

D

Date: Sheet

Compal Electronics, Inc.

DC Interface

VAWGA/GB

E

1.0

of

32 48Thursday, March 28, 2013

5

4

3

2

1

VIN

PL101

12

100P_0402_50V8J

PL101

SMB3025500YA_2P

1 2

12

PC103

PC104

100P_0402_50V8J

1000P_0402_50V7K

PF101

JDCIN1

1

2

PR102

750_0402_1%

12

PR105

2

3

4

5

@

12

PQ102B

100K_0402_1%

2N7002KDW-2N_SOT363-6

PQ102A

PQ102A 2N7002KDW-2N_SOT363-6

2N7002KDW-2N_SOT363-6

6 1

2

34

5

ADP_ID_CLOSE

D D

ACES_50312-00541-001

+3VALW

100K_0402_1%

PR104

VIN

C C

12

APDIN

12

PC109

PC108

0.1U_0402_16V7K

<28>

PF101

7A_24VDC_429007.WRML

ADP_ID

680P_0603_50VK

21

APDIN1

12

PC101

PC102

1000P_0402_50V7K

<28>

+CHGRTC

PR103

1K_0603_5%

1 2

+CHGRTC_R

1 2 3 4

ACES_50271-0020N-001

JRTC1

1 2 GND GND

+3VLP

@JRTC1

@

Vin

+RTCBATT_3V

1

+RTCBATT_3V

12

PC110

PU102

+RTCBATT

12

B B

3

2

AP2138N-1.5TRG1_SOT23-3

PC111

0.1U_0603_25V7K

Vout

GND

PD101

S SCH DIO BAS40CW SOT-323

680P_0603_50VK

2

1

3

PR101

1K_0603_5%

1 2

RTC Battery

Need use+3.3V transfer to +1.5V LDO to APU side for Kaibini

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR-DCIN / RTC Battery

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

VAWGA/B

33 48Thursday, March 28, 2013

1

33 48Thursday, March 28, 2013

1.0

5

4

3

2

1

VMB2

@

JBATT1

1

2

3

4

5

6

7

PC212

@ PC212

@

GND GND

SUYIN_200082GR007M229ZR

JBATT2

GND GND

SUYIN_200082GR007M229ZR

VL

+5VALW

12

22U_0603_6.3V6M

1 2

7

8 9

@

1

2

3

4

5

6

7

8 9

0.01U_0402_25V7K

PR202

PR202 75K_0402_1%

75K_0402_1%

PR213

PR213 100K_0402_1%

100K_0402_1%

VMB

PR208

75K_0402_1%

@ PR208

75K_0402_1%

@

1 2

PR217

1 2

@ PR217

@

100K_0402_1%

@PU202

@

1

2

G9191-330T1U_SOT23-5

PC202

BATT_TEMP

12

PC207

PC207 100P_0402_50V8J

100P_0402_50V8J

PC213

@ PC213

@

PU202

IN

OUT

GND

SHDN#3BYP

1U_0402_16V6K

12

+3V_LDO

12

100P_0402_50V8J

PC211

5

D D

C C

B B

A A

EC_SMCA

EC_SMDA

12

PR201

VL

8

3

P

+

1

O

2

-

G

PU201A

AS393MTR-E1 SO 8P OP

4

5

+

6

-

PU201B

AS393MTR-E1 SO 8P OP

5

4

12

@PC211

@

12

PR204

100_0402_1%

PR206

6.49K_0402_1%

PR209

@PR209

@

6.49K_0402_1%

PR207

PR207 10K_0402_5%

10K_0402_5%

12

PR210

47K_0402_1%

0.068U_0402_16V7K

VL

1.5M_0402_5%

8

P

7

O

G

4

12

@PC214

@

4.7U_0402_6.3V6M

PF201

PF201 12A_65V_451012MRL

12A_65V_451012MRL

100_0402_1%

1 2

PC208

1 2

PR205

12

@PR218

@

47K_0402_1%

0.068U_0402_16V7K~N

@PR223

@

1.5M_0402_5%

+3V_LDO

PC214

21

PD201

1N4148WS-7-F_SOD323-2

1 2

PR218

PC210

@PC210

@

1 2

PR223

1 2

VMB

+3VLP

+3VALW

<28,4,40,6>

12

2

<28>

G

12

PD203

@

1N4148WS-7-F_SOD323-2

SMB3025500YA_2P

1 2

12

PC201

PC201 1000P_0402_50V7K

1000P_0402_50V7K

EC_SMB_CK1

EC_SMB_DA1

BATT_TEMP

H_PROCHOT#

5

13

D

BATT_LEN#

S

PQ209

@

2N7002KW_SOT323-3

4

PL201

12

<28>

A/D

PROCHOT

PR211

100K_0402_1%

1 2

34

PQ202B

2N7002KDW-2N_SOT363-6

BATT+

PC203

0.01U_0402_25V7K

PQ201

13

D

@

2N7002KW_SOT323-3

S

+3VALW

2

+3VLP

1 2

PH201 under CPU botten side : CPU thermal protection at 93 +-3 degree C Recovery at 56 +-3 degree C

@

PR215

1 2

100K_0402_1%

2

ADP_OCP_1

G

PR216

PR216 0_0402_5%

0_0402_5%

1 2

@

PR214

100K_0402_1%

1 2 61

PQ202A

2N7002KDW-2N_SOT363-6

PR220

100K_0402_1%

13

D

2

G

S

90W(DIS) : 6.65K 100W active 90W recovery 65W(UMA): 1.65K 70W active 65W recovery

<28,35>

<28>

BATT_OUT

3

PROCHOT

Turbo_V

ADP_65

ADP_90

ADP_135

2011/06/15 2012/07/11

<28>

BATT_OUT

PQ205

2N7002KW_SOT323-3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

@PR229

@

10K_0402_1%

PR225

2

G

<35>

PR229

1 2

25.5K_0402_1%

ADP_I

1 2

13

D

PQ206

S

2N7002KW_SOT323-3

13

D

2

G

S

Compal Secret Data

Deciphered Date

PR221

1 2

8.45K_0402_1%

PR222

PR222 100K_0402_1%

PR228

PR227

9.31K_0402_1%

PQ208

PR228

1 2

2N7002KW_SOT323-3

13

D

2

G

S

ECAGND

100K_0402_1%

1 2

5.9K_0402_1%

PQ207

2N7002KW_SOT323-3

2

<28>

20120314 Change to +EC_VCCA from +3VLP

+EC_VCCA+3VS

12

PR226

NTC_V

<28>

Compal Electronics, Inc.

Title

PWR-BATTERY CONN/OTP

Size Document Number Rev

Custom

Date: Sheet of

PR226

ECAGND

VAWGA/B

12.7K_0402_1%

12

PH201

PH201 100K_0402_1%_TSM0B104F4251RZ

100K_0402_1%_TSM0B104F4251RZ

1

ECAGND

34 48Thursday, March 28, 2013

1.0

5

PQ301

PQ301 AO4407AL_SO8

AO4407AL_SO8

DTA144EUA_SC70-3

47K_0402_5%

13

2

PQ307A

PACIN

PQ305

DTC115EUA_SC70-3

PR313

1 2

10K_0402_1%

PQ314

8 7

5

PQ304

2

1 3

PQ303

DTC115EUA_SC70-3

PR303

47K_0402_1%

1 2

2

ACOFF-1

<28>

13

D

2

G

S

4

<34>

VIN

D D

C C

ACOFF

B B

2

BATT_OUT

12

PR302

61

2N7002KDW -2N_SOT363-6

2N7002KW_S OT323-3

P2

1 2 36

12

PR304

PC302

200K_0402_1%

0.1U_0603_25V7K

P2-1

12

13

12

D

PR305

S

150K_0402_1%

P2-2

34

PQ307B

5

13

2N7002KDW-2N_SOT363-6

<28>

PQ302

AO4423L_SO8

1 2 3 6

4

PR306

PR306 20K_0402_1%

20K_0402_1%

PQ306

2N7002KW_S OT323-3

2

BATT_OUT

G

PR308

64.9K_0402_1%

1 2

PC303

1 2

0.1U_0402_25V6

EC_SMB_DA1

EC_SMB_CK1

5600P_0402_25V7K

VIN

12

PR309

<28,34>

392K_0402_1%

4

8 7

5

PC301

+3VALW

1 2

PR315

316K_0402_1%

1 2

100K_0402_1%

P3

ADP_I

PC304

1 2

100P_0402_50V8J

PR316

PR301

0.01_1206_1%

1

2

ACPRN

6

ACDET

7

IOUT

8

SDA

BQ24727RGRR_VQFN20_ 3P5X3P5

9

SCL

10

12

ILIM

B+

4

3

ACP

4

5

ACOK

CMPIN

PU301

SRN12BM

11

12

PR317

6.8_0402_5%

PC306

0.1U_0402_25V6

PC307

1 2

3

CMPOUT

SRP

13

12

ACN

0.1U_0402_25V6

PC308

0.1U_0402_25V6

12

2

ACP

GND

14

PR318

10_0402_5%

3

1 2

PL301

1UH_PCMB061H-1R0M S_7A_20%

1 2

PC310

10U_0805_25V6K@

PC311

12

0.1U_0402_25V6

1

ACN

21

TP

20

VCC

19

PHASE

18

HIDRV

17

16

BST_CHG

12

PC312

PC312 1U_0603_25V6K

1U_0603_25V6K

BTST

REGN

LODRV

15

1 2

P2

PR319

10_1206_5%

1 2

BQ24737VCC

DH_CHG

PD301

12

RB751V-40_SOD323-2

DL_CHG

PC313

10U_0805_25V6K@

PC314

1 2

1U_0603_25V6K

PR320

2.2_0603_5%

1 2

BQ24737VDD

1 2

PC315

LX_CHG

0.047U_0603_16V7K

10U_0805_25V6K

PC317

1 2

PC316

10U_0805_25V6K

PR311

1 2

0_0402_5%

12

2

CHG_B+

PQ312

AO4407AL_SO8

1 2 3 6

ACOFF-1

PD302

1SS355_SOD323-2

1 2

PD303

1SS355_SOD323-2

CHG

4

0.01_1206_1%

1

2

SRP

1 2

2200P_0402_50V7K

6

578

4

123

6

578

4

123

PR322

200K_0402_1%

1 2

PR321

PR321 47K_0402_1%

47K_0402_1%

1 2

DISCHG_G-1

PQ311

13

DTC115EUA_SC70-3

2

PQ309

MDS1525URH 1N SO8

10UH_PCMB104T-100MS _6A_20%

PQ310

MDS1521URH 1N SO8

1 2

12

PR323

@

24737_SN

12

PC320

@

PL302

4.7_1206_5%

680P_0603_50V7K

DISCHG_G

PC319

PC324

PR324

1 2

12

0.1U_0402_25V6

SRN

8 7

5

PR325

PR325 200K_0402_1%

200K_0402_1%

4

3

1

VIN

PQ313

2N7002KW_S OT323-3

13

D

2

PACIN

G

S

12

PC322

10U_0805_25V6K

BATT+

12

PC323

10U_0805_25V6K

12

PC305

0.1U_0402_25V6

BQ24737VDD

PR314

10K_0402_1%

4

10K_0402_1%

1 2

PACIN

12

PR312

12K_0402_1%

ACIN <11 ,28>

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

Issued Date

PQ308

2

G

12

PR310

PR310 10K_0402_1%

10K_0402_1%

13

D

S

12

PR307

47K_0402_1%

2N7002KW_S OT323-3

ACPRN

A A

5

12

PC309

@ PC309

@

0.1U_0402_25V6

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2012/07/112011/06/15

2

Title

PWR-CHARGER

Size D ocument Number Rev

Date: Sheet of

VAWGA/B

35 48Thursday, March 28, 2013

1

1.0

A

1 1

PU401

12

10U_0805_25V6K

12

@

100K_0402_1%

PU401

7

IN

8

IN

9

GND

PG2LDO

SY8208BQNC_QFN10_3X3

PR410

100K_0402_1%

EN1

EN2

BS

OUT

B+

PL401

HCB2012KF-121T50_0805

1 2

12

PC401

PC403

@

0.1U_0402_25V6

68P_0402_50V8J

2 2

3V_VIN

12

PC405

PC404

2200P_0402_50V7K

SPOK<37>

+3VLP

PC406

@

10U_0805_25V6K

12

PR417

+3VALWP

B+

PL403

HCB2012KF-121T50_0805

1 2

12

PC420

PC419

@

68P_0402_50V8J

10U_0805_25V6K

3 3

<28>

4 4

EC_ON

MAINPWON

5V_VIN

PU402

8

IN

12

PC416

10U_0805_25V6K

12

PC417

2200P_0402_50V7K

EC_ON

MAINPWON

12

PC418

@

0.1U_0402_25V6

9

5

5V_VCC

2

12

PC422

4.7U_0603_6.3V6M

PR407

2.2K_0402_5%

1 2

PR408

0_0402_5%

EN1

EN2

BS

LX

GND

OUT

VCC

LDO

PG

SY8208CQNC_QFN10_3X3

12

3V5V_EN

12

PR409

PC431

1M_0402_1%

4.7U_0402_6.3V6M

B

12

PR411

10K_0402_1%

12

PC432

0.047U_0402_25V6

1

3

6

10

LX

4

5

1

3

6

10

4

7

BST_3V

3V5V_EN

BST_5V

12

3V5V_EN_R

1 2

PR401

0_0402_5%

+3VLP

12

PC414

4.7U_0603_6.3V6M

@

1 2

PR405

0_0402_5%

VL

PC430

4.7U_0603_6.3V6M

ENLDO_3V5V

12

PR412

PC402

1 2

0.1U_0603_25V7K

0_0402_5%

6800P_0402_25V7K

PC421

0.1U_0603_25V7K

1 2

LX_5V

3V5V_EN3V5V_EN_R

PC439

1 2

0.01U_0402_25V7K

LX_3V

1.5UH_PCMC063T-1R5MN_9A_20%

@PR404

@

12

PR404

4.7_1206_5%

3V_SN

12

@PC415

@

PC415

680P_0603_50V7K

PC436

1 2

1.5UH_PCMC063T-1R5MN_9A_20%

12

@PR406

@

PR406

4.7_1206_5%

5V_SN

12

@PC429

@

PC429

680P_0603_50V7K

PR414

1 2

0_0402_5%

PR415

@PR415

@

0_0402_5%

PL402

1 2

PR413

1K_0402_5%

1 2

12

PL404

ENLDO_3V5V

PR416

1K_0402_5%

C

PR402

499K_0402_1%

12

PR403

PC407

150K_0402_1%

1U_0603_25V6K

12

1U_0603_25V6K

12

D

E

B+

+3VALWP

@

12

PC408

22U_0805_6.3V6M

12

PC409

PC410

22U_0805_6.3V6M

12

@PC412

@

PC411

PC412

22U_0805_6.3V6M

12

@PC413

@

PC413

22U_0805_6.3V6M

PC435

PC434

470P_0402_50V8J

+5VALWP

1

@

12

PC423

22U_0805_6.3V6M

12

PC425

PC424

22U_0805_6.3V6M

12

+

@PC427

@

@PC428

@

PC433

PC426

22U_0805_6.3V6M

2

PC427

PC428

@

22U_0805_6.3V6M

150U_D2_6.3VY_R15M

@

12

PC437

PC438

470P_0402_50V8J

PJ401

@PJ401

@

+3VALWP +3VALW

+5VALWP

112

JUMP_43X118

PJ402

@PJ402

@

112

JUMP_43X118

2

+5VALW

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR-3VALWP/5VALWP

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

VAWGA/GB

E

36 48Thursday, March 28, 2013

1.0

A

STATE S3 S5 1.5VP VTT_REFP 0.75VSP

S0

Hi Hi

S3

S4/S5

1 1

HiLo

Lo Lo

On

Off

On

Off (Hi-Z)

Off Off

Note: S3 - sleep ; S5 - power off

+0.75VSP

12

PC504

PC505

10U_0805_25V6K

+VTT_REFP

+1.5VP

12

PC506

2 2

PR502

49.9K_0402_1%

SUSP#

SYSON

1 2

PC503

0.1U_0402_16V6K

<28,32>

12

PC506

0.033U_0402_16V7K

1 2

0.1U_0402_16V7K

PR505

0_0402_5%

@PC5 08

@

PU501

21

PAD

1

VTTGND

2

VTTSNS

3

GND

4

VTTREF

5

VDDQ

12

PC508

PR506

5.76K_0402_1%

B

+1.5VP

PR503

PR503 0_0402_5%

0_0402_5%

1 2

BST_1.5V BST_1.5V-1

19

18

VLDOIN

S3

8

7

S3_1.5V

S5_1.5V

5.6K_0402_1%

68P_0402_50V8J

BOOT

S5

PR507

PC526

@PC5 26

@

1 2

17

UGATE

TON

9

20

VTT

RT8207MZQW _WQFN20_3X3

FB

6

12

PR501

2.2_0603_5%

1 2

16

PHASE LGATE

PGND

CS

VDDP

VDD

PGOOD

10

PR509

887K_0402_1%

12

LX_1.5V

15

14

6.65K_0402_1%

13

12

11

+3VALW

12

@

12

1.5V_B+

UG_1.5VUG_1.5 V

PR511

PR510

PGOOD_1.5V

10K_0402_5%

0.1U_0603_25V7K

LG_1.5V

12

PC510

1U_0603_10V6K

PC512

1 2

12

1U_0603_10V6K

5.1_0603_5%

PC511

PR514

C

1.5V_B+

12

5

4

12

123

5

123

+5VALW

PQ501

MDU1516URH_POWERDFN56-8-5

12

PQ502

12

MDU1511RH_POWERDFN56-8-5

12

1UH_PCMB104T-1R0M H_18A_20%

@

PR515

4.7_1206_5%

@

PC517

PC517 680P_0603_50V7K

680P_0603_50V7K

PC520

PC501

@

10U_0805_25V6K

4.7U_0805_25V6-K

PL501

12

PC513

PC509

@

0.1U_0402_25V6

0.1U_0402_25V6 2200P_0402_50V7K

2200P_0402_50V7K

12

330U_2.5V_M

PL502

1 2

HCB2012KF-121T50_0805

1

+

PC521

2

D

@

1

+

PC522

2

220U_6.3V_M

+1.5VP

B+

+1.5VP

OCP min 20A OVP min 1.65V

PJ504

2

112

JUMP_43X118@

PJ505

+1.5VP +1.5V

2

112

JUMP_43X118@

PJ506

2

112

JUMP_43X79

@

3 3

PU502

PU502 SY8033BDBC_DFN10_3X3

SY8033BDBC_DFN10_3X3

PJ502

+3VALW

2

112

JUMP_43X79@

SPOK

095_18ALW_PWR_EN

<28>

4 4

A

12

PR516

@PR5 16

@

1 2

0_0402_5%

PR611

1 2

0_0402_5%

1.8VSP_VIN

PC502

PC502 22U_0805_6.3VAM

22U_0805_6.3VAM

EN_1.8VSP

<36,38>

PR504

PR504 1M_0402_5%

1M_0402_5%

@PC507

@

12

PC507

1 2

4

PG

FB

TP

NC

7

11

12

PC524

0.1U_0402_10V7K

2

LX

1.8VSP_LX

3

FB=0.6Volt

6

NC

1

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

10

PVIN

9

PVIN

8

SVIN

5

EN

0.1U_0402_10V7K

PL503

1UH_PH041H-1R0MS_3. 2A_20%

1 2

12

PR508

4.7_1206_5%

@

12

PC523

@

680P_0603_50V7K

PR512

20K_0402_1%

1.8VSP_FB

PR513

10K_0402_1%

12

PC525

68P_0402_50V8J

12

2011/06/15 2012/07/11

12

PC515

PC514

22U_0805_6.3VAM

Compal Secret Data

Deciphered Date

C

12

PC516

@

2200P_0402_50V7K

12

PC518

@

68P_0402_50V8J

+1.8VALWP

PC519

@

0.1U_0402_25V6

Title

Size D ocument Number Rev

Custom

Date: Sheet of

@

PJ507

2

112

JUMP_43X79@

Compal Electronics, Inc.

PWR-+1.5VP/+1.8VALWP

VAWGA/GB

D

+0.75VS+0.75VSP

+1.8VALW+1.8VALW P

1.0

37 48Thursday, March 28, 2013

1.0

5

4

3

2

1

D D

0.95V_B+

678

PQ601

PR609

1 2

0_0402_5%

PR610

095_18ALW_PWR_EN

<28>

SPOK<37>

PR605 reserve

C C

PR610

1 2

0_0402_5%

PR601

@ PR601

@

0_0402_5%

1 2

PR605

@ PR605

@

PR602

2.2_0603_5%

40.2K_0402_1%

PR603

12

0.95V_TRIP

0.95V_EN

0.95V_FB

1 2

0.95V_RF

PR606

12

1 2

47K_0402_5%

PR607

PC601

1 2

@

.1U_0402_16V7K

3.48K_0402_1%

12

PR608

PR608 10K_0402_1%

10K_0402_1%

PR606

470K_0402_1%

PU601

1

VBST

PGOOD

2

TRIP

DRVH

3

EN

SW

4

V5IN

VFB

5

DRVL

RF

TP

TPS51212DSCR_SON10_3X3

VFB=0.7V

2.2_0603_5%

1 2

10

BST_0.95V

9

DH_0.95V

8

LX_0.95V

7

6

DL_0.95V

11

0.22U_0603_16V7K

BST_0.95V-1

12

1U_0603_10V6K

1 2

PC608

PC606

+5VALW

4

PQ601

35241

MDS1525URH 1N SO8

786

5

PQ602

123

MDS1521URH 1N SO8

12

PC602

PC603

10U_0805_25V6K

PL661

PR604

PC609

4.7_1206_5%

680P_0603_50V7K

PL661

1 2

1UH_PCMC063T-1R0MN_12A_20%

12

@

12

@

12

PC604

@

0.1U_0402_25V6

HCB2012KF-121T50_0805

12

PC605

2200P_0402_50V7K

1

+

2

PL601

1 2

PC607

PC607 220U_6.3V_M

220U_6.3V_M

B+

+0.95VALWP

+

0.95VALWP OCP(min)=15.6A

PJ602

2

112

JUMP_43X118@

PJ603

2

112

JUMP_43X118@

+0.95VALW+0.95VALWP

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PWR-+0.95VALWP

Size Document Number Rev

C

Date: Sheet of

VAWGA/B

1

38 48Thursday, March 28, 2013

1.0

A

GPU_VID5 GPU_VID3 GPU_VID2 GPU_VID1 GPU_VID0GPU_VID4

VBOOT

0.85V 1 01 10 NA

PR813

@ PR813

DPRSLPVR_VGA-1

PR833

2.2K_0402_1%

PR834

PR835

12

PR836

COMP_VGA

1 2

ISEN3_VGA

PC871

PC874

1 2

390P_0402_50V7K

PR863

330P_0402_50V7K

1000P_0402_50V7K

@

0_0402_5%

1 2

PR820

1 2

0_0402_5%

PC805

@PC805

@

1 2

100P_0402_25V8K

CLK_ENABLE#_VGA

PSI#_VGA

RBIAS_VGA

1 2 3 4 5 6 7 8

FB_VGA

9

10

41

PR864

0_0402_5%

1 2

For 15W one phase

+5VS

12

PC850

@

0.22U_0402_10V6K

PC859

PC862

VRON_VGA

PU801

PGOOD PSI# RBIAS VR_TT# NTC VW COMP FB ISEN3 ISEN2

AGND

VSEN_VGA

12

PC875

@

12

39

40

CLK_EN#

ISEN111VSEN12RTN13ISUM-14ISUM+15VDD

0.22U_0402_10V6K

@PC863

@

12

PC863

330P_0402_50V7K

PR814

PR814 0_0402_5%

0_0402_5%

1 2

GPU_VID3

GPU_VID4

GPU_VID5

GPU_VID6

37

35

38

VID031VID132VID233VID334VID536VID6

VID4

VR_ON

DPRSLPVR

17

16

RTN_VGA

VDD_VGA

ISUM-_VGA

12

@PR851

@

12

PR851

VSUM_VGA_N001

@PC864

@

12

PC864

PR862

PR862 887_0402_1%

887_0402_1%

1 2

Sun Pro OCP:42A

30

BOOT2

29

UGATE2

28

PHASE2

27

VSSP2

26

LGATE2

25

VCCP

24

PWM3

23

LGATE1

22

VSSP1

21

PHASE1

VIN

IMON18BOOT119UGATE1

ISL62883CHRTZ-T_TQFN40_5X5

20

PR845

1 2

VIN_VGA

0_0402_5%

PR848

1 2

12

1_0402_5%

PC877

PC876

1U_0603_10V6K

0.22U_0603_25V7K

82.5_0402_5%

PC860

0.1U_0603_25V7K

0.01U_0402_25V7K

+VGA_B+

+5VS

12

PC861

0.033U_0603_25V7K

12

0.1U_0402_16V7K

1 1

GPU_GPIO0

<11>

VGA_PWRGD

2 2

@PR840

@

PR840

PR841

1 2

249K_0402_1%

33P_0402_50V8J

1 2

PC848

150P_0402_50V8J

<14>

FB2_VGA

VCCSENSE_VGA

3 3

4 4

+3VS

PR832

1 2

0_0402_5%

GPU_GPIO0

12

5.9K_0402_1%

PC847

1 2

PR846

267K_0402_1%

VSSSENSE_VGA

12

PC873

1000P_0402_50V7K

PR849

30K_0402_1%

+VGA_CORE

<12,28,6>

<28>

+3VS

PR831

12

PXS_PWREN

EC_VGA_EN

@ PR816

@

1 2

@ PR818

@

1 2

2.2K_0402_1%

1 2

12

1.91K_0402_1%

+3VS

VW_VGA

PR842

499_0402_1%

1 2

PR843

1.69K_0402_1%

1 2

ISEN2_VGA

ISEN1_VGA

PR816

2.2K_0402_1%

PR818

0_0402_5%

PR819

PR830

@PR830

@

1.91K_0402_1%

1 2

@

1 2

0_0402_5%

@ PR835

@

1 2

2.2K_0402_1%

147K_0402_1%

@ PC871

@

22P_0402_50V8J

FB1_VGA

0_0402_5%

1 2

VSUM-_VGA

1 2

PR850

10_0402_1%

PR854

1 2

0_0402_5%

PR860

1 2

0_0402_5%

0_0402_5% PR861

PR861

10_0402_1%

1 2

A

GPU_VID2

<11>

PC866

12

PC849

PR859

B

1 2

PR801 10K_0402_1%PR801 10K_0402_1%

GPU_VID5

GPU_VID1

GPU_VID0

<11>

PC812

@ PC812

@

1U_0603_10V6K

1 2

12

PC872

PC872 1U_0603_10V6K

1U_0603_10V6K

PR844 0_0402_5%@PR844 0_0402_5%@

1 2

PR865

1 2

0_0402_5%

PR847

1 2

6.65K_0402_1%

VSSSENSE_VGA

0.047U_0402_16V7-K

12

PR853

2.61K_0402_1%

NTC_VGA

12

PH802

PH802 10K_0402_1%_TSM0A103F34D1RZ

10K_0402_1%_TSM0A103F34D1RZ

11K_0402_1%

Layout Note: Place near Phase1 Choke

B

+3VGS

@

1 2

PR802 10K_0402_1%PR802 10K_0402_1%

GPU_VID4

<11>

+5VS

GPU_IMON

VSUM+_VGA

VSUM-_VGA

1 2

PR803 10K_0402_1%@PR803 10K_0402_1%@

PR804 10K_0402_1%@PR804 10K_0402_1%

PR806 10K_0402_1%@PR806 10K_0402_1%@

PR805 10K_0402_1%@PR805 10K_0402_1%@

GPU_VID3

GPU_VID2

GPU_VID1

GPU_VID0

@

2.2_0603_5%

BOOT2_VGA BOOT2_2_VGA

2.2_0603_5%

<11>

+5VS

BOOT1_VGA

PR817

<28>

UGATE1_VGA

2.2_0603_5%

PHASE1_VGA

LGATE1_VGA

C

1 2

PR807 10K_0402_1%@PR807 10K_0402_1%@

PR809 10K_0402_1%PR809 10K_0402_1%

PR808 10K_0402_1%@PR808 10K_0402_1%@

GPU_VID3

GPU_VID5

GPU_VID4

12

UGATE2_VGA

LGATE2_VGA

1 2

PR811 10K_0402_1%PR811 10K_0402_1%

PR810 10K_0402_1%PR810 10K_0402_1%

GPU_VID2

GPU_VID1

PC806

@

0.22U_0603_10V7K

1 2

PR812 10K_0402_1%PR812 10K_0402_1%

1 2

GPU_VID0

PHASE2_VGA

PQ801

@

CSD87351Q5D_SON8-7

2

3

4

1

8

+VGA_B+

@PC801

@

PC801

0.1U_0402_25V6

7 6 5

12

@PR826

@

PR826

4.7_1206_5%

SNUB2_VGA

@PC811

@

12

PC811

680P_0402_50V7K

+VGA_CORE

12

PC825

PC824

2.2U_0402_6.3V6M

12

PR852

12

BOOT1_1_VGA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

12

PC840

PC841

10U_0603_6.3V6M

PC858

0.22U_0603_10V7K

1 2

12

10U_0603_6.3V6M

12

PC826

PC827

2.2U_0402_6.3V6M

12

PC842

PC843

10U_0603_6.3V6M

CSD87351Q5D_SON8-7

2011/06/15 2012/07/11

C

12

PC828

PC829

2.2U_0402_6.3V6M

12

PC844

PC845

10U_0603_6.3V6M

PQ802

2

3

4

Compal Secret Data

12

2.2U_0402_6.3V6M

12

10U_0603_6.3V6M

12

PC831

PC830

2.2U_0402_6.3V6M

PC846

10U_0603_6.3V6M

1

7 6 5

8

Deciphered Date

12

PC832

2.2U_0402_6.3V6M

12

PC852

PC851

1U_0402_6.3V6K

PC878

@

PR855

@

PC865

12

SW2_VGA

PC833

2.2U_0402_6.3V6M

12

0.1U_0402_25V6

12

4.7_1206_5%

SNUB1_VGA

12

680P_0402_50V7K

12

PC853

PC802

@ PC802

@

2200P_0402_50V7K

PR827

@ PR827

@

PC834

12

1U_0402_6.3V6K

PC879

2200P_0402_50V7K

SW1_VGA

12

PC803

@ PC803

@

10U_0805_25V6K

12

3.65K_0402_1%

ISEN2_VGA

VSUM+_VGA

12

PC835

2.2U_0402_6.3V6M

12

PC854

1U_0402_6.3V6K

12

PC880

10U_0805_25V6K

12

PR856

3.65K_0402_1%

VSUM+_VGA

D

PL801

HCB4532KF-800T90_1812

1 2

12

PC804

@ PC804

@

10U_0805_25V6K

PL802

@

0.22UH_PCME064T-R22MS_28A_20%

1

4

3

2

PR828

10K_0402_1%

@ PR828

10K_0402_1%

@

12

PC836

PC837

2.2U_0402_6.3V6M

12

PC855

PC856

0.1U_0402_10V7K

+VGA_B+

12

PC881

10U_0805_25V6K

0.22UH_PCME064T-R22MS_28A_20%

LF1_VGA

12

PR857

@

10K_0402_1%

ISEN1_VGA

Title

Size Document Number Rev

C

Date: Sheet of

V2N_VGALF2_VGA

12

PR837

PR829

1_0402_1%

@ PR837

@

@ PR829

@

10K_0402_1%

VSUM-_VGA

ISEN1_VGA

12

PC839

PC838

2.2U_0402_6.3V6M

12

PC857

0.1U_0402_10V7K

PL803

1

4

3

2

PR838

@ PR838

@

V1N_VGA

12

ISEN2_VGA

12

PR858

10K_0402_1%

VSUM-_VGA

Compal Electronics, Inc.

PWR-VGA_CORE

VAWGA/GB

D

1

+

PC807

2

330U_D2_2V_Y

1_0402_1%

B+

+VGA_CORE

1

+

2

1

+

PC809

PC810

PC808

PC810

2

330U_D2_2V_Y

+VGA_CORE

330U_D2_2V_Y

1.0

330U_D2_2V_Y

39 48Thursday, March 28, 2013

5

PC901

330P_04 02_50V7K

PR906

0_0402_ 5%

1 2

0.01U_04 02_50V7K

PR913

@

220P_04 02_50V7K

12

PR917

VR_ON

1 2

VSUM+

VSUM-

330P_04 02_50V7K

1000P_0 402_50V7 K

PC1037

12

PC1042

12

PR918 0_ 0402_5%PR918 0_0402_ 5%

PR920 0_ 0402_5%PR920 0_0402_ 5%

PR921 0_ 0402_5%PR921 0_0402_ 5%

PR923 0_ 0402_5%PR923 0_0402_ 5%

PR925 0_ 0402_5%PR925 0_0402_ 5%

PR926 0_ 0402_5%PR926 0_0402_ 5%

PR927 0_ 0402_5%PR927 0_0402_ 5%

PR932

0_0402_ 5%

1 2

PH904

12

<4>

APU_VDDNB _SEN

+APU_CORE_NB

D D

2011/10/21 NTC near phase 1 choke

VSUMP_NB

VSUMN_NB

C C

PR919 13 3K_0402_ 1%PR9 19 133K_0 402_1%

APU_IMON

B B

2011/10/21 NTC near CPU_CORE H/S mos

12

PR909

12

2.61K_0402_1%

2.61K_0402_1% PR911

PR911

PH901

1 2

10K_0402_5%_ERTJ0ER103J

12

PC1041

0.1U_060 3_50V7K

2011/10/21 NTC near NB_CORE H/S mos

PR916 27.4K_040 2_1%PR916 27. 4K_0402_1 %

470K_04 02_5%_TSM0B 474J4702R E

PC1043

1000P_0 402_50V7 K

12

+1.5VS

1 2

PC1073

PC6602 1000P _0402_50V 7KP C6602 1000P_04 02_50V7K

0.1U_0402_25V6

12

PH903

12

H_PROCHOT#

1 2

1

2

<28,34,4 ,6>

+3VS

+1.8VS

1 2

PR951

0_0402_ 5%

1 2

PR928

133K_04 02_1%

PC1047

1000P_0 402_50V7 K

1 2

PR930 2 7.4K_0402 _1%P R930 27.4 K_0402_1%

470K_04 02_5%_TSM0B 474J4702R E

11K_0402_1%

PH902

PR922100K_0402_ 1% @PR922100K_04 02_1% @

PR953

0_0402_ 5%

PR952

@PR 952

@

0_0402_ 5%

1 2

PC1038

12

20K_040 2_1%

1 2

PR902

10_0402 _5%

12

1 2

PC1039

324_040 2_1%

0.15U_0603_16V7K

0.022U_0402_25V7K

PR915

@PR 915

@

100_040 2_1%

20K_040 2_1%

<4>

<28>

<4>

PR931

APU_SVC

APU_SVD

APU_SVT

PC1044

0.1U_040 2_25V6

1 2

APU_PW RGD

+5VS

2011/10/21 NTC near phase 1 choke

12

PR903

1.54K_0 402_1%

PC1034

12

PR942

12

2.61K_0402_1%

1 2

10K_0402_5%_ERTJ0ER103J

PC1062

0.1U_060 3_50V7K

PR901

2K_0402 _1%

12

499_040 2_1%

SVC

SVD

VDDIO

SVT

ENABLE

PWROK

12

PR934

10K_040 2_1%

1 2

PR943

11K_0402_1%

PR907

1

2

3

4

5

6

7

8

9

10

12

267K_04 02_1%

12

PU901

NTC_NB

IMON_NB

SVC

VR_HOT_L

SVD

VDDIO

SVT

ENABLE

PWROK

IMON

ISEN2

1 2

PC1059

0.01U_0402_50V7K

PR948

@ PR9 48

@

100_040 2_1%

PR904

47P_040 2_50V8J

41

TP

PC1060

150P_04 02_50V8J

PC1033

12

PC1035

12

38

40

39

ISUMP_NB

ISUMN_NB

ISL6277 1HRTZ-T_TQFN40_5X5

13

11

ISEN1

PR945

0.15U_0603_16V7K

0.15U_0603_16V7K 487_040 2_1%

487_040 2_1%

12

PC1063

820P_04 02_50V7K

12

4

PR954

1 2

30

29

28

27

26

VDDP

25

VDD

24

23

22

21

PR937

499_040 2_1%

PR939

1.54K_0 402_1%

12

UGATE_NB1

PHASE_NB 1

BOOT_NB1

LGATE_NB1

LGATE1

PHASE1

UGATE1

BOOT1

100K_04 02_1%

12

PR946

10_0402 _5%

PR947

0_0402_ 5%

1 2

PR949

0_0402_ 5%

1 2

PR950

10_0402 _5%

PR908

2.2_060 3_1%

PR929

47P_040 2_50V8J

PR940

267K_04 02_1%

PR944

2K_0402 _1%

12

0_0402_ 5%

0.22U_06 03_25V7K

12

1_0603_ 5%

12

PC1045

+3VS

12

PC1055

12

PC1058

150P_04 02_50V8J

12

PC1061

330P_04 02_50V7K

12

+APU_CORE

APU_VDD_ SEN

APU_VDD_ RUN_FB_L

PC1036

PR924

1U_0603_25V6K

PR905

@ PR90 5

@

41.2K_0 402_1%

12

37

FB_NB

VSEN_NB

ISUMP14ISEN212NTC

@PC1063

@

12

36

COMP_NB

ISUMN15ISEN1

34

35

PGOOD_NB

VSEN

17

16

@

1 2

PC1056

1 2

12

32

33

LGATE_NB

PHASE_NB

UGATE_NB

RTN

COMP

FB18PGOOD

19

1000P_0 402_50V7 K

330P_0402_50V7K

PC1064

0.01U_0402_50V7K

LGATE_NB1

PHASE_NB 1

UGATE_NB1

BOOT_NB1

31

BOOT_NB

BOOT2

UGATE2

PHASE2

LGATE2

LGATE1

PHASE1

UGATE1

BOOT1

20

PC1054

12

5

4

12

5

4

+5VALW

12

PC1046

1

PC6601

PC6601 1000P_0 402_50V7 K

1000P_0 402_50V7 K

2

VGATE

PR938

32.4K_0 402_1%

<4>

3

CPU_B+

5

4

PQ905

123

MDU1516URH_POWERDFN56-8-5

PQ906

123

MDU1511RH_POWERDFN56-8-5

1U_0603_25V6K

UGATE1

PHASE1

BOOT1

@PR938

@

12

<28>

PR933

2.2_060 3_1%

LGATE1

4

PR955

1 2

0_0402_ 5%

123

5

123

0.22U_06 03_25V7K

12

PC1027

10U_0805_25V6K

PQ901

MDU1516URH_POWERDFN56-8-5

PQ902

MDU1511RH_POWERDFN56-8-5

2012/10/30 Load Line:VDD-->4m

5

4

PC1053

12

5

4

12

123

12

PC1029

PC1028

10U_0805_25V6K

12

@PR9 10

@

4.7_120 6_5%

12

PC1040

@PC 1040

@

680P_0603_50V7K

VDDNB-->4.0m

4

PQ907

MDU1516URH_POWERDFN56-8-5

4

PQ908

MDU1511RH_POWERDFN56-8-5

12

PR910

PC1030

@

5

12

0.1U_0402_25V5K

VSUMP_NB

VSUMN_NB

123

PC1032

2200P_0402_50V7K

PQ903

MDU1516URH_POWERDFN56-8-5

PQ904

MDU1511RH_POWERDFN56-8-5

2

HCB2012K F-121T50_080 5

1 2

12

SH00000N900 (DCR 1.1+-5%)

PR912

3.65K_0 402_1%

1_0402_ 1%

PC1049

10U_0805_25V6K

PL902

0.36UH_V MPI1004AR-R3 6M-Z03_30A_ 20%

1

4

3

2

12

PR914

12

CPU_B+

12

PC1048

10U_0805_25V6K

12

PC1051

PC1050

10U_0805_25V6K

0.1U_0402_25V5K

@

12

PC1052

@PR 935

@

4.7_120 6_5%

@PC 1057

@

680P_06 03_50V7K

PL901

2200P_0402_50V7K

PR935

PC1057

1

B+

1

+

PC1031

PC1031 220U_25 V_M

220U_25 V_M

2

+APU_CORE_NB

12

SH00000GH00 (DCR 1.25+-7%)

PR936

3.65K_0 402_1%

VSUM+

PR941

1_0402_ 1%

VSUM-

PL903

0.36UH_FD UE1030D-H-R36 M=P3_32A_2 0%

1

4

3

2

12

+APU_CORE

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2011/07/08 2015/07/08

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

APU_CORE/APU_CORE_NB

Size Document Numb er Rev

Custom

Date: Sheet of

VAWGA/B

1

40 48Thursd ay, March 28, 201 3

1.0

A

1 1

B

C

D

E

10U_0603 *3

+APU_CORE +APU_CORE_NB

PC100222U_0603_6.3V6M PC100222U_0603_6.3V6M12PC100422U_0603_6.3V6M PC100422U_0603_6.3V6M

12

PC100322U_0603_6.3V6M PC100322U_0603_6.3V6M

12

PC100122U_0603_6.3V6M PC100122U_0603_6.3V6M

12

2 2

3 3

12

PC1017

@

0.01U_0402_25V7K~N

12

PC1018

@

0.1U_0402_25V7K~N

PC106722U_0603_6.3V6M PC106722U_0603_6.3V6M12PC106822U_0603_6.3V6M PC106822U_0603_6.3V6M12PC106522U_0603_6.3V6M@PC106522U_0603_6.3V6M@12

PC106622U_0603_6.3V6M@PC106622U_0603_6.3V6M@12

PC101110U_0603_6.3V6M@PC101110U_0603_6.3V6M@12

PC100910U_0603_6.3V6M PC100910U_0603_6.3V6M

12

PC101010U_0603_6.3V6M PC101010U_0603_6.3V6M

12

PC100522U_0603_6.3V6MPC100522U_0603_6.3V6M

PC100822U_0603_6.3V6MPC100822U_0603_6.3V6M

PC100622U_0603_6.3V6MPC100622U_0603_6.3V6M

PC100722U_0603_6.3V6MPC100722U_0603_6.3V6M

12

PC1019

@

0.01U_0402_25V7K~N

12

PC1020

@

0.1U_0402_25V7K~N

PC107222U_0603_6.3V6M PC107222U_0603_6.3V6M

12

PC107122U_0603_6.3V6M PC107122U_0603_6.3V6M

12

PC106922U_0603_6.3V6M@PC106922U_0603_6.3V6M@12

PC107022U_0603_6.3V6M@PC107022U_0603_6.3V6M@12

10U_0603 * 4

PC101410U_0603_6.3V6M PC101410U_0603_6.3V6M

12

PC101510U_0603_6.3V6M@PC101510U_0603_6.3V6M@12

PC101310U_0603_6.3V6M PC101310U_0603_6.3V6M

12

PC101610U_0603_6.3V6M@PC101610U_0603_6.3V6M@12

1

+

PC1023

PC1021

PC1022

2

330U_D2_2V_Y

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

1

+

PC1025

PC1026

PC1024

2

@

330U_D2_2V_Y

Compal Secret Data

2011/07/08 2015/07/08

C

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PWR-PROCESSOR DECOUPLING

VAWGA/B

41 48Thursday, March 28, 2013

E

1.0

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

for PWR

Reason for change PG# Modify List Date PhaseItem

1

D D

2

3

4

5

6

7

8

C C

9

10

11

12

13

14

B B

15

16

17

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PIR (PWR)

C38-G series Chief River Schematic

42 48Thursday, March 28, 2013

1

1.0

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

for HW

Reason for change PG# Modify List Date PhaseItem

For share rom 28 Change SYS_PWRGD_EC from pin 86 to pin 32 12/17 DVT

1

D D

2

Add R20728For 095VS_PWR_EN pull down

12/17 DVT

3

For follow VIWGP design 27 Change JUSB3 pin define 12/18 DVT

4

5

6

For share rom 28 Change R1575, R1576 to 100K 12/24 DVT

7

For reserve EC +3VL 2805Add J11, J12 and modify +3VALW to +3V_EC 12/24 DVT

8

C C

10

11

12

13

14

15

16

B B

17

For share ROM 05 modify ROM net-name & resistor value 12/24 DVT

9

For common VIWGP design 22 modify R106, R107 to 22ohm 12/24 DVT

For power S3 reduction 28 Change EC_INVT_PWM to ADP_ID_CLOSE 12/25 DVT

For common VIWGP design 23 Change JODD1 symbol 12/27 DVT

For reserve wake on wlan function 26 Add R1500 12/27 DVT

For 1.5VS discharge 32 Change R339 to 0ohm, mount Q23 & R1461 12/29 DVT

For AMD suggest 4 Change R576 to 0ohm 12/29 DVT

For VGA sequence 12 Delete R123 & C40, change C28, C27 to 2200P 12/29 DVT

For +3VALW APU Power Consumption 7 Add R582 01/03 DVT

12, 32

Change U1895V, U35P, U1895P VBIAS from +5VALW to VLFor VBIAS first raise up

12/17 DVT

DVT12/21Change CA36, CA46 from 1U to 2.2U31For Audio Precision

DVT12/24Add R20828For SYS_PWRGD_EC pull down

18

For ESD request 22

Add C600, C601, PC6601, PC6602 01/03 DVT 28 40

19

20

21

22

23

A A

For no support DC wake & LID function 28 Pull high only SMB & RST use +3V_EC, other use +3VALW 01/04 DVT

For reserve cost down experiment

30 Add R630, R643 01/04 DVT

For Common VIWGP 30 Change SW4,SW5,SW6,SW7 footprint 01/04 DVT

For instant plug/unplug AC has beep sound 31 DVT01/04

For Crystal Capactance fine tune

@RA22

5 6

01/09 DVTModify C794,C795,C682,C686,CV36,CV37 value

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PIR (PWR)

C38-G series Chief River Schematic

1

1.0

43 48Thursday, March 28, 2013

1.0

5

4

3

2

Version change list (P.I.R. List) Page 1 of 1

for HW

Reason for change PG# Modify List Date PhaseItem

1

For EMI request 30 Change L67 to EMICP@, Change R692,R687 to EMICU@ 02/02

1

D D

C C

10

11

For Share ROM recoverable solution as

2

original method

For BIOS post time 06 Pull high PXS_PWREN to +3VS by RP14 02/02 PVT

3

For ZiZi noise 31 Change AVDD_HP from +3VS to +3VLP 02/02 PVT

4

For follow KABINI latest CRB 04 @ R576,C164,C342 02/02 PVT

5

For APU control PWM only 21 Delete R1465 02/02 PVT

6

For Corret Net-name to prevet confuse 0421Change TL_INVT_PWM, TL_ENVDD to APU_INVT_PWM, APU_ENVDD 02/02 PVT

7

8

For Reserve DDC CLK DATA pull high 22 Add R693, R697 02/02 PVT

For Common Intel project 30 Change R623,R765,R303 to 620ohm 02/02 PVT

9

05 Add RP12 02/02 PVT

For Common Intel project 23 Reserve R551 02/02 PVT

For reduce BOM 31 Delete RA3, and Change RA4 to short-pad 02/05 PVT

12

13

For reduce BOM

11

Change RV43,LV1,LV2,LV3,LV4,LV5,LV6,RV16,RV17,LV7,LV8,LV9,LV10 12

to short-pad 13

02/05 PVT

PVT

PVT02/05Change R1498,R1499 from 0 ohm to 100 ohm26For reduce BOM

14

For better location

14 18

02/05 PVTCV72 <-> CV171 ; CV60 <-> CV70 ; CV154 <-> CV191

19

B B

15

For reduce BOM 21 Change R1463 from 0 ohm to short-pad 02/06 PVT

16

17

18

19

20

21

22

A A

23

For better audio precision performance 31 Change CA27,CA28 from 1U to 2.2U 02/08 PVT

For reduce BOM & layout concern 07 Delete C195 02/16 PVT

For test point request 22 Add T49, T58 on JCRT1 02/18 PVT

For ESD request 25 Add C173, C178 02/18 PVT

For reduce BOM 05 Change R112, R115, R116, R119, R125, R126 to short-pad 02/18 PVT

For Crystal timming PVT02/20Change C682 from 18P to 22P06

For ESD request 30 Change D24 from ESDU@ to ESDP@, Part number from SCA00000E00

02/23 PVT

to SCA00001G00 21

Change L58,L51,L55,L66,L67 from SM070000K00 to SM070000Z00

27

02/23 PVTFor EMI request

30

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PIR (PWR)

C38-G series Chief River Schematic

44 48Thursday, March 28, 2013

1

1.0

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

for PWR

Reason for change PG# Modify List Date PhaseItem

For Common Intel project 30 Change R623,R765,R303 to 649ohm 03/05 PreMP

1

D D

For VGA Clock Request 06 Reserve R578,R689 03/05 PreMP

2

For Reduce BOM 05 Change R103, R104 to short-pad 03/11 PreMP

3

For Reduce BOM 21 Change R696, R695, R813 to short-pad 03/11 PreMP

4

For Reduce BOM 23 Change R550 to short-pad 03/11 PreMP

5

For Reduce BOM 28 Change R1564 to short-pad 03/11 PreMP

6

For Reduce BOM 29 Change R581 to short-pad 03/11 PreMP

7

For Reduce BOM 31 Change RA11 to short-pad 03/11 PreMP

8

C C

B B

For Reduce BOM 32 Change R339 to short-pad 03/11 PreMP

9

For Reduce BOM 06 Change R121 to short-pad 03/11 PreMP

10

For Reduce BOM 07 Change R582 to short-pad 03/11 PreMP

11

For ESD require 30 Add C185 03/25 PreMP

12

For Module Design 22 Change R693, R697 from 10k to 4.7k 03/25 PreMP

13

For ESD require 04 Add C195 03/26 PreMP

14

For Reduce BOM 04 @ RP11 03/26 PreMP

15

For Board ID 28 @ R1562 and change R1564 to 0ohm 03/28 PreMP

16

17

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PIR (PWR)

C38-G series Chief River Schematic

45 48Thursday, March 28, 2013

1

1.0

5

4

3

2

1

Power-Up/Down Sequence

Mars XT VRAM STRAP

Vendor PS_3[ 0 ]PS_3[ 1 ]PS_3[ 2 ]

D D

K4W2G1646E-BC1A SA000068U00

MT41J128M16JT-093G:K SA000067500

2G

H5TQ2G63DFR-N0C SA000065300

SA00006H400

K4W1G1646G-BC11 SA00004GS00

1

G

SA000041SB0

C C

MS2G@ X7646738L01 M

M2G@ X7646738L02 OLDMH2G@ X7646738L09 NEWMH2G@ X7646738L10 MS1G@ X7646738L03 MH1G@ X7646738L04

0 0

0 01H5TC2G63FFR-11C

0 1 1

1 1

1H5TQ1G63EFR-11C

0

10 0

00 1

R_pu R_pd

RV20 RV27

NC 4.75K

RV20 RV27

8.45K 2K

RV20 RV27

4.53K 2K

RV20 RV27

4.53K 4.99K

RV20 RV27

6.98K 4.99K

RV20

4.75K

RV27

NC

"Mars" has the following requirements with regards to power-supply sequencing to avoid damaging the ASIC:

All the ASIC supplies must reach their respective nominal voltages within 20 ms

‧

of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred. The maximum slew rate on all rails is 50 mV/µs.

The external pull ups on the DDC/AUX signals (if applicable) should ramp up

‧

before or after both VDDC and VDD_CT have ramped up.

VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC

‧

should reach 90% before VDD_CT starts to ramp up (or vice versa).

For power down, reversing the ramp-up sequence is recommended.

‧

VDDR3(3.3VGS)

PCIE_VDDC(0.95VGSV)

VDDR1(1.5VGS)

VDDC/VDDCI(1.12V)

VDD_CT(1.8V)

PERSTb

SUN PRO VRAM STRAP

REFCLK

Vendor PS_3[ 0 ]PS_3[ 1 ]PS_3[ 2 ]

K4W4G1646B-HC11 SA000068R00

MT41K256M16HA-107G:E

2G

SA000065D00

B B

A A

H5TQ4G63MFR-11C SA00006DG00

K4W2G1646E-BC1A SA000068U00

MT41J128M16JT-093G:K

1G

SA000067500

H5TC2G63FFR-11C SA00006H400

H5TQ2G63DFR-N0C

A000065300

S

SS2G@ X7646738L05 SM2G@ X7646738L06 SH2G@ TBD SS1G@ X7646738L07 SM1G@ X7646738L08 NEWSH1G@ X7646738L13 OLDSH1G@ X7647538L01

5

0 0

0 1 1

0 0 4.53K

1

0

10 0

8.45K 2K

00 1

4.53K 2K

6.98K 4.99K

RV20 RV27

011

3.4K 10K

RV20

4.75K11 NC

R_pu R_pd

RV20 RV27

NC 4.75K

RV20 RV27

RV27

4.99K1

RV27

4

Straps Reset

Straps Valid

Global ASIC Reset

T4+16clock

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

VGA Notes List

VAWGA/GB

46 48Thursday, March 28, 2013

1

1.0

A

B+

PU401 SY8208BQKC

EC_ON

B

C

D

E

+3VLP

+3VALW

+EC_VCCA

P-CHANNEL PMV65XP

1 1

U35P TPS22966DPUR

LAN_PWR_ON#

SUSP#

U315V TPS22966DPUR

PXS_PWREN

+3V_LAN

+3VS

+3VGS

PU502 SY8033BDBC

2 2

3 3

PU402 SY8208CQKC

PU501 RT8207MZQW

PU601 TPS51212DSCR

PU801 ISL62883CHRTZ

EC_ON

SUSP# / SYSON

SPOK

EC_VGA_EN

U35P TPS22966DPUR

P-CHANNEL LP2301ALT1G

U315V TPS22966DPUR

U1895P TPS22966DPUR

U1895V TPS22966DPUR

SPOK

SUSP#

PXS_PWREN

SUSP#

PXS_PWREN

U1895P TPS22966DPUR

U1895V TPS22966DPUR

+1.8VALW

SUSP#

+1.8VS

PXS_PWREN

+1.8VGS

+VL

+5VALW

+5VS

+0.75VS

+1.5V

+1.5VS

+1.5VGS

+0.95VALW

+0.95VS

+0.95VGS

+VGA_CORE

PU901 ISL62771HRTZ

4 4

PQ204 TP0610K

A

VR_ON

SPOK

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+APU_CORE

+APU_CORE_NB

+VSB

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Power Map

VAWGA/GB

E

1.0

47 48Thursday, March 28, 2013

1.0

5

B++3VALW

PU502 +1.8VALW

VV

D D

VV

PU402 +5VALW / VL

VV

1A

ACIN

C C

ON/OFF

1B

4A

PU601 +0.95VALW

PU401 +3VALW/+3VLP

+5VS / +3VS / +1.8VS

AC MODE

VIN

APU_PWRGD

BATT MODE

BATT+

VR_ON

18

PU901 +APU_CORE /

15

+APU_CORE_NB

V V

RTC Battery +CHGRTC_R

3VALW

B B

V

+CHGRTC_R +3VLP

IN BATT+

+

+5VALW

B+

PU501

PU102

RTCBATT

+

PU301

B+

+1.5V

+5VALW

B+B+

V

4

3A 3B

095_18ALW_PWR_EN

3A 3B

SPOK

2A 2B

EC_ON

B++5VALW

16

VGATE

+3VALW

V

+5VALW

U35P +3VS

+1.5V

Q20 +1.5VS

+3VLP +3VALW

EC

VV

4A

3B

8

5

SUSP#

SYSON

9

V V

3

EC_RSMRST#

PBTN_OUT#

V

SLP_S3# / SLP_S5#

SYS_PWRGD_EC

V

PXS_PWREN 13

EC_VGA_EN

095VS_PWR_EN

+5VALW

U35P

V

+5VS

+1.8VALW

U1895P

V

+1.8VS

+3VALW

+5VALW

2

+3VALW / +1.8VALW / +1.5VALW / +0.95VALW

+3VS / +1.8VS / +1.5VS / +0.95VS

+APU_CORE / +APU_CORE_NB

+RTCBATT

V

+5VALW

+3VGS

AND G

ATE

23

GPU_RST#

5

6

7

10KBRST#

17

19LPC_RST#

12

11

B

+

V V

V

+1.8VALW

+0.95VALW

APU

+5VALW

U1895V +1.8VGS

+5VALW

U1895V +0.95VGS

+5VALW

V

22

PXS_RST#

20

APU_PCIE_RST#

18 APU_PWRGD

VGA_PEWGD

14

B+

+5VS +3VS

V

PU801 +

VGA_CORE

V

+3VS

U315V

V

+3VGS

+1.5V

U315V

V

+1.5VGS

1

+3VGS / +1.5VGS

+1.8VGS / +0.95VGS

GPU

V

MarsXTX

+3VS +1.5VA

WLAN / WiMAX

VV

Mini-Express Card

D4

V

Diode

3V_LAN

+

LAN

LAN_PERST#

+VGA_CORE

21

MODEL NAME:

A A

PCB NAME:

PU501

V

+0.75VS

U1895P

V

+0.95VS

REVISION: DATE:

COMPAL CONFIDENTIAL

2011/11/23

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Power sequence

1

1.0