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LA-9868P
Schematics
41 pgs1.27 Mb0
Schematics Rev1.0
42 pgs1.79 Mb0

Compal LA-9868P Schematics Rev1.0

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Page 1
CyberForum.ru
A
1 1
B
C
D
E
VNKAE
2 2
Rosetta 10AN/10ANG
LA-9868P SchematicREV 1.0
3 3
AMD KABINI Quad Core 25W only for UMA AMD KABINI Quad Core 15W for DIS&UMA
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2012/09/27 2015/09/27
2012/09/27 2015/09/27
2012/09/27 2015/09/27
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
LA-9868P
LA-9868P
LA-9868P
1 42Thursday, May 16, 2013
1 42Thursday, May 16, 2013
1 42Thursday, May 16, 2013
E
1.0
1.0
1.0
Page 2
CyberForum.ru
A
A
D GPU
M
A
1 1
MD Sun Pro M2, 64bit with 1GB DDR3(2Gbit)
AMD Sun Pro M2, 64bit with 2GB DDR3(4Gbit)
p
age 12-19
B
PCIe Gen2 X4
5Gbps
A
D FT3 APU
M
C
M
emory BUS(DDRIII)
Single Channel
1
.5V DDRIII 1333/1600 MT/s
APU SMBUS
D
2
0pin DDRIII-SO-DIMM X2
0
B
ANK 0, 1, 2, 3
p
age 10,11
E
L
DS/eDP Conn
V
H
D
MI Conn
p
age 20
DP0 X4
DP1 X4
J
aguar
Core
Integrated Yangtze FCH
USB 2.0
5
V
480Mbps
U
B 2.0 Left
S
U
U
SB Right1
U
S
B2.0 port 8
B port 0
S
p
age 25
p
age 24
U
U
SB Right2
U
S
B2.0 port 9
SB port 4
p
age 20
p
age 24
C
ardreaderTouchScreen
U
B port 2
S
p
age 28
I
nt. Camera
U
S
p
age 20
B port 3
P
IeMini Card
C
For BT
U
SB port 1
p
age 23
(1.4b & 3D)
p
age 21
2 2
C
T Conn
R
p
age 22
P
CIeMini Card For WLAN
P
CIe port 2
p
age 23
R
T
L8106E 10/100M
P
C
Ie port 1
p
S
ROM
PI
(4MB)
age 25
p
age 7
3 3
T
uch Screen Control/B
o
p
age 20
D
C
A
P
Ie Gen1 X1
C
APU SMBUS
2
5bps
.
PCIe Gen1 X1
2
.
5bps
S
P
I BUS
3
.
3V 33HZ
APU SMBus
BGA 769-balls
L
3
E
E KB9012
N
E
C SMBus
p
PC Bus
3V 33 MHz
.
p
age 29
age 5-9
U
S
5
V
5Gbps
S
TA port 0
A
5
6Gbps
V
S
TA port 1
A
5
6Gbps
V
H
D
3
.
3V 24MHz
B 3.0
Audio
U
S
B Right1
U
S
TA HDD
A
S
TA ODD
A
H
D
A Codec
A
L
S
B3.0 port 0
p
age 24
SATA port 0
p
SATA port 1
p
C259
age 23
age 23
p
age 26
U
S
B Right2
U
S
B3.0 port 1
p
age 24
S
PK Conn
p
age 27
J
PI
O
(HP & MIC)
p
age 27
DC/DC Interface CKT.
p
age 31
4 4
P
o
wer Circuit DC/DC
p
age 32~41
P
o
wer On/Off CKT & Power/B
p
age 30
A
U
S
B2.0&LAN/B
p
age 25
R
T
C CKT.
page 9
B
T
ouch Pad
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
T
T
T
H
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ed Date
ssued Date
ed Date
ssu
ssu
I
nt.KBD
page 30page 30
C
G
-Sensor
p
age 25
C
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
2
2
2
0
0
12/09/27 2015/09/27
012/09/27 2015/09/27
12/09/27 2015/09/27
o
D
D
D
ciphered Date
eciphered Date
ciphered Date
e
e
D
C
C
C
o
mpal Electronics, Inc.
mpal Electronics, Inc.
ompal Electronics, Inc.
T
T
T
i
i
tle
tle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
B
B
B
l
l
ock Diagram
lock Diagram
ock Diagram
L
L
L
A
A
-9868P
-9868P
-9868P
A
2
o
2
2
o
o
4
4
f
2Thursday, May 16, 2013
2Thursday, May 16, 2013
2Thursday, May 16, 2013
f
4
E
f
1
1
1
.
.
0
0
0
.
Page 3
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4
3
2
1
DESIGN CURRENT 0.15A
D
B+
D D
Ipeak=12A, Imax=8.4A, Iocp min=14A
S
SP#
U
N
CHANNEL
-
T
PS22966
O
D
N
-CHANNEL
T
S22966
P
D_PWR
ESIGN CURRENT 0A
D
ESIGN CURRENT 4A
D
ESIGN CURRENT 2A
+3VL +
+5VALW
+5VS
+
5VS_ODD
5VL
RT8243A
I
peak=8A, Imax=5.6A, Iocp min=10A
3
VALW_APU_PWREN
D
P
-
CHANNEL
A
O
-3413
1
.
8_0.95VALW_PWREN
S
C C
S
USP#
N-CHANNEL
T
S22966
P
Y8032
L
CD_ENVDD
P
-CHANNEL A
-3413
O
D
GPU_PWR_EN
P-CHANNEL
AO-3413
ESIGN CURRENT 330mA
D
ESIGN CURRENT 2.5A
S
U
SP#
N
-CHANNEL
TPS22966
V
A_PWRGD
G
N
-CHANNEL
TPS22966
D
ESIGN CURRENT 4A
DESIGN CURRENT 1.5A
D
ESIGN CURRENT 60mA
+
3VALW
+
3VALW_APU
+
3V_LAN
+
1.8VALW
+
1.8VS
+
1.8VGS
+LCD_VDD
+
3VS_DGPU
+3VS
D
S
Y
R
T8207M
S
Y8208D
R
T8880A
SL62881
G
SON
1
8_0.95VALW_PWREN
.
V
R_ON
P
U_DPRSLPVR
Ipeak=12A, Imax=8.4A, Iocp min=13.8A
V
G
A_PWRGD
N
-CHANNEL
T
P
S22966
SUSP#
I
eak=2.5A, Imax=1.75A, Iocp min=16A
p
0
95VS_PWREN#
.
N
-CHANNEL
F
S6676
D
I
p
eak=15A, Imax=10.5A, Iocp min=30A
I
p
eak=13A, Imax=9.1A, Iocp min=30A
I
p
eak=21A, Imax=14.7A, Iocp min=40A
4
B B
A A
I
5
ESIGN CURRENT 2A
D
ESIGN CURRENT 2A
D
ESIGN CURRENT 1.5A
D
ESIGN CURRENT 2A
+
3V_WLAN
+1.5V
+
1.5VGS
+
0.75VS
+
0.95VALW
+0.95VS
A
PU_CORE
APU_CORE_NB
V
GA_CORE
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
s
ssued Date
sued Date
sued Date
s
T
T
T
H
HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL
IS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFI DENTIAL
IS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFI DENTIAL
H
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
3
2
2
2
0
0
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
C
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
o
D
D
D
e
eciphered Date
ciphered Date
ciphered Date
e
2
C
C
C
o
o
mpal Electronics, Inc.
ompal Electronics, Inc.
mpal Electronics, Inc.
T
T
T
i
i
i
tle
tle
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
L
L
L
P
P
P
A
A
-9868P
-9868P
-9868P
A
o
o
wer Tree
wer Tree
wer Tree
o
3
o
3
3
o
o
4
f
2Thursday, May 16, 2013
2Thursday, May 16, 2013
2Thursday, May 16, 2013
f
4
f
1
4
1
1
1
.
.
0
0
0
.
Page 4
CyberForum.ru
A
B
C
D
E
V
ltage Rails
o
State
S0
S1
S
3
S5 S4/AC
power plane
1 1
2 2
S
5 S4/ Battery only
S5 S4/AC & Battery don't exist
( O MEANS ON X MEANS OFF )
+RTCVCC
O
O
O
O
O
O
B
+
O
O
O
O
O
X
+5VL
+3VL
O
O
O
O
O
X
+5VALW
+3VALW
+1.8VALW
+0.95VALW
+
VSB
O
O
O
O
X
X
+1.5V
O
X
X
X
UMA
+5VS
+3VS
+
0.95VS
+1.8VS
+1.5VS
+
0.75VS
+
APU_CORE
+
APU_CORE_NB
OO
OO
X
X
X
X
B
O Option Table
T
F
unction
description
explain
BTO
S
ATE
T
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
G
3 L
SIGNAL
SLP_S3# SLP_S5#
HIGHHIGH
HIGH HIGH
LOW
HIGH
H
I
LOW
OW LOW
GH
L
O
WLOW
A
P
U SM Bus Address (SCL0/SDA0)
H
E
3 3
+
3VS DDR SO-DIMM A A0H 1010 0000 b +3VS DDR SO-DIMM B A2H 1010 0010 b +3VS WLAN
E
SM Bus1 Address
C
D
vice Address
e
HEX
HEX Address
+3VL Smart Battery 16H 0001 0110 b +3VL Charger 12H 0001 0010 b
4 4
A
X AddressDevicePower
E
SM Bus2 Address
C
D
vicePowerPower
e
HEX Address
+3VS G-Sensor 40H 0100 0000 b +3VS VGA thermal 82H 1000 0010 b +3VS APU thermal 98H 1001 1000 b
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
ed Date
ssued Date
ed Date
ssu
ssu
T
T
T
H
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
2
2
0
0
12/09/27 2015/09/27
012/09/27 2015/09/27
12/09/27 2015/09/27
C
C
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
o
D
D
D
A
G
G-B
G-C
G-D
G-E
ciphered Date
eciphered Date
ciphered Date
e
e
P
U POWER SEQUENCE
-A
+RTC
3
ALW_APU_PWREN
V
+
3
VALW_APU
1.8_0.95VALW_PWREN
+1.8VALW
+0.95VALW
SYSON
+1.5V
SUSP#
+3VS
+1.8VS
+
1.5VS
+0.95VS
VR_ON
+APU_CORE
+APU_CORE_NB
D
C
C
C
o
mpal Electronics, Inc.
mpal Electronics, Inc.
ompal Electronics, Inc.
T
T
T
i
i
tle
tle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
u
u
stom
stom
stom
u
Date: Sheet
Date: Sheet
Date: Sheet
o
L
L
L
A
A
A
N
N
N
-9868P
-9868P
-9868P
o
o
tes List
otes List
tes List
E
o
o
o
f
4 42Thursday, May 16, 2013
4 42Thursday, May 16, 2013
4 42Thursday, May 16, 2013
f
f
1
1
1
.
.
0
0
0
.
Page 5
CyberForum.ru
5
D
R_AB_DQS[0..7]<10,11>
D
R_AB_DQS#[0..7]<10,11>
D
D
D
R_AB_MA[0..15]<10,11>
D
D D
D
R_AB_BS0<10,11>
D
D
R_AB_BS1<10,11>
D
D
R_AB_BS2<10,11>
D
R_AB_DM[0..7]<10,11>
D
D
C C
D
R_A_CLK0<10>
D
R_A_CLK0#<10>
D
D
R_A_CLK1<10>
D
D
D
R_A_CLK1#<10>
D
R_B_CLK0<11>
D
D
R_B_CLK0#<11>
D
D
D
R_B_CLK1<11>
D
R_B_CLK1#<11>
D
D
M_MAB_RST#<10,11>
E
M
M_MAB_EVENT#<10,11>
E
M
D
R_A_CKE0<10>
D
D
R_A_CKE1<10>
D
R_B_CKE0<11>
D
D
R_B_CKE1<11>
D
B B
1 2
94
94
C
C
C
C
C
C
R
R
1K_0402_1%
1K_0402_1%
A A
C
C
R
R
1K_0402_1%
1K_0402_1%
D
R_A_ODT0<10>
D
D
R_A_ODT1<10>
D
D
D
R_B_ODT0<11>
D
D
R_B_ODT1<11>
D
D
R_A_SCS0#<10>
D
D
R_A_SCS1#<10>
D
R_B_SCS0#<11>
D
D
R_B_SCS1#<11>
D
D
D
R_AB_RAS#<10,11>
D
R_AB_CAS#<10,11>
D
D
R_AB_WE#<10,11>
D
D
ESD@
ESD@
E
M_MAB_RST#
M
180P_0402_50V8J
180P_0402_50V8J
c
ose to APU
l
1
.5V
+
M
EMORY Reference Voltage (Cap follower checklist 1.02)
6
6
1 2
8
8
2
C
C
17
17
C
C 1U_0402_6.3V6K
1U_0402_6.3V6K
1
1 2
C
l
ose to APU AD40
5
D
D
R_AB_MA0
D
D
R_AB_MA1
D
D
R_AB_MA2
D
R_AB_MA3
D
D
R_AB_MA4
D
D
D
R_AB_MA5
D
D
R_AB_MA6
D
D
R_AB_MA7
D
R_AB_MA8
D
D
R_AB_MA9
D
D
R_AB_MA10
D
D
DR_AB_MA11
D
R_AB_MA12
D
D
R_AB_MA13
D
D
R_AB_MA14
D
D
DR_AB_MA15
R_AB_BS0
D
D
R_AB_BS1
D
D
D
R_AB_BS2
D
D
D
R_AB_DM0
D
D
R_AB_DM1
D
D
R_AB_DM2
D
D
R_AB_DM3
D
R_AB_DM4
D
D
R_AB_DM5
D
D
DR_AB_DM6
D
R_AB_DM7
D
D
D
R_AB_DQS0
D
DR_AB_DQS#0
D
DR_AB_DQS1
D
D
R_AB_DQS#1
D
D
R_AB_DQS2
D
R_AB_DQS#2
D
D
R_AB_DQS3
D
D
R_AB_DQS#3
D
D
R_AB_DQS4
D
D
R_AB_DQS#4
D
D
DR_AB_DQS5
D
D
R_AB_DQS#5
D
R_AB_DQS6
D
D
R_AB_DQS#6
D
D
D
R_AB_DQS7
D
R_AB_DQS#7
D
D
R_A_CLK0
D
D
R_A_CLK0#
D
D
R_A_CLK1
D
D
R_A_CLK1#
D
R_B_CLK0
D
D
D
R_B_CLK0#
D
D
R_B_CLK1
D
R_B_CLK1#
D
D
M
M_MAB_RST#
E
M
M_MAB_EVENT#
E
D
DR_A_CKE0
D
R_A_CKE1
D
R_B_CKE0
D
D
D
R_B_CKE1
D
D
D
R_A_ODT0
D
D
R_A_ODT1
R_B_ODT0
D
D
R_B_ODT1
D
D
D
DR_A_SCS0#
D
D
R_A_SCS1#
D
D
R_B_SCS0#
D
R_B_SCS1#
D
D
D
R_AB_RAS#
D
R_AB_CAS#
D
D
D
R_AB_WE#
M
EM_VREF
+
r
emove from CRB_ver0C
Check List 1.02
15mil
M
EM_VREF
+
2
C
C
18
18
C
C
0.1U_0402_16V7K
0.1U_0402_16V7K
1
U
U
1A
1A
C
C
A
G
38
M
_
ADD0
W
3
5
M
_
ADD1
W
3
8
M
_
ADD2
W
3
4
M
_
ADD3
U
8
3
M
ADD4
_
U
7
3
M
ADD5
_
U
4
3
M
ADD6
_
R
5
3
M
_ADD7
R
3
8
M
_
ADD8
N
3
8
M
_
ADD9
A
G
34
M
_
ADD10
R
4
3
M
ADD11
_
N
3
7
M
_
ADD12
A
N
34
M
_
ADD13
L
3
8
M
_
ADD14
L
3
5
M
_
ADD15
A
38
J
M
BANK0
_
A
35
G
M
BANK1
_
N
4
3
M
BANK2
_
B
3
2
M
_
DM0
B
3
8
M
_
DM1
G
4
0
M
_
DM2
N
4
1
M
_
DM3
A
G
40
M
_
DM4
A
41
N
M
DM5
_
A
40
Y
M
DM6
_
A
34
Y
M
DM7
_
Y
0
4
M
DM8
_
B
3
3
M
DQS_H0
_
A
3
3
M
_
DQS_L0
B
4
0
M
_
DQS_H1
A
4
0
M
_
DQS_L1
H
4
1
M
_
DQS_H2
H
4
0
M
_
DQS_L2
P
4
1
M
_
DQS_H3
P
4
0
M
_
DQS_L3
A
H
41
M
_
DQS_H4
A
H
40
M
_
DQS_L4
A
P
41
M
_
DQS_H5
A
P
40
M
_
DQS_L5
B
A
40
M
_
DQS_H6
A
Y
41
M
_
DQS_L6
A
33
Y
M
DQS_H7
_
B
A
34
M
_
DQS_L7
A
A
40
M
DQS_H8
_
Y
1
4
M
DQS_L8
_
A
C
35
M
_
CLK_H0
A
34
C
M
CLK_L0
_
A
34
A
M
CLK_H1
_
A
A
32
M
_
CLK_L1
A
38
E
M
CLK_H2
_
A
37
E
M
CLK_L2
_
A
A
37
M
_
CLK_H3
A
A
38
M
CLK_L3
_
G
3
8
M
_
RESET_L
A
E
34
M
_
EVENT_L
L
4
3
M
_CKE0
0
J
8
3
M
_CKE1
0
J
3
7
M
1
_CKE0
J
3
4
M
1
_CKE1
A
N
38
M
0
_ODT0
A
U
38
M
0
_ODT1
A
N
37
M
1
_ODT0
A
R
37
M
1
_ODT1
A
J
34
M
0
_CS_L0
A
R
38
M
0
_CS_L1
A
L
38
M
1
_CS_L0
A
35
N
M
_CS_L1
1
A
J37
M
_
RAS_L
A
34
L
M
CAS_L
_
A
35
L
M
WE_L
_
A
40
D
M
VREF
_
A
C
38
M
_
VREFDQ
FT3_BGA769 @
FT3_BGA769 @
M
M
MORY
MORY
E
E
EMORY M
F
F
3 REV 0.51
3 REV 0.51
T
T
M
M
M
M
M
M
M
M
M
ZVDDIO_MEM_S
_
4
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
_
_
_
_
_
_
_
_
4
DATA0
_
_
DATA1
_
DATA2
_
DATA3
DATA4
_
DATA5
_
_
DATA6
_
DATA7
DATA8
_
_
DATA9
_
DATA10
DATA11
_
_
DATA12
DATA13
_
DATA14
_
_
DATA15
DATA16
_
DATA17
_
_
DATA18
_
DATA19
DATA20
_
_
DATA21
_
DATA22
DATA23
_
_
DATA24
_
DATA25
DATA26
_
DATA27
_
DATA28
_
_
DATA29
_
DATA30
_
DATA31
DATA32
_
DATA33
_
_
DATA34
_
DATA35
_
DATA36
_
DATA37
DATA38
_
DATA39
_
_
DATA40
_
DATA41
_
DATA42
DATA43
_
DATA44
_
DATA45
_
DATA46
_
_
DATA47
_
DATA48
DATA49
_
DATA50
_
DATA51
_
DATA52
_
DATA53
_
DATA54
_
_
DATA55
_
DATA56
_
DATA57
DATA58
_
DATA59
_
DATA60
_
DATA61
_
_
DATA62
DATA63
_
CHECK0
CHECK1
CHECK2
CHECK3
CHECK4
CHECK5
CHECK6
CHECK7
B A B A B A A B
B A D D B A B C
F F K K E E J J
M N T
U L M R T
A A A A A A A A
A A A A A A A A
A A B A A A A A
B A B A B A B A
V W A A U V A A
A
0
3
2
3 3
5
3
6 9
2
0
3 3
4
3
4
7
3 3
8
4
0 1
4 3
6 7
3
1
4 4
0
0
4
1
4
4
0
4
1 0
4
1
4
4
0
4
1
4
4
0 1
4
0
4
0
4
4
4
0
4
0
40
F
41
F K K E E
40
J
41
J
M N T
41
U
40
L M R T
40
V W A Y
37 U V
39
Y Y
38
A Y
35 A
31
Y A
36
Y A
32
Y
4
1
4 B C 4
1 4
0 A B
D
D D D D D D D D
D D D D D D D D
D D D D D D D D
1
D D D D D
0
D D D
D D
40
D
41
D
40
D
41
D D D
41
D
40
D D
40
D D
40
D
40
D D
41
D
40
D
38
D D
41
D
40
D D D
36
D D
32
D D
37
D D
33
D D
0 40 40
41 41
41
DR_AB_D0 DR_AB_D1 D
R_AB_D2
D
R_AB_D3
D
R_AB_D4
D
R_AB_D5
D
R_AB_D6 R_AB_D7
D
R_AB_D8
D
R_AB_D9
D
R_AB_D10
D
R_AB_D11
D
R_AB_D12
D
R_AB_D13
D
R_AB_D14
D
R_AB_D15
D
D
R_AB_D16
D
R_AB_D17
D
R_AB_D18 R_AB_D19
D
R_AB_D20
D
R_AB_D21
D
R_AB_D22
D D
R_AB_D23
D
R_AB_D24
D
R_AB_D25 R_AB_D26
D
R_AB_D27
D
R_AB_D28
D D
R_AB_D29
D
R_AB_D30
D
R_AB_D31
R_AB_D32
D
R_AB_D33
D DR_AB_D34 D
R_AB_D35 R_AB_D36
D
R_AB_D37
D DR_AB_D38 D
R_AB_D39
D
R_AB_D40 R_AB_D41
D
R_AB_D42
D DR_AB_D43 D
R_AB_D44 R_AB_D45
D
R_AB_D46
D DR_AB_D47
D
R_AB_D48
D
R_AB_D49 R_AB_D50
D DR_AB_D51 D
R_AB_D52 R_AB_D53
D
R_AB_D54
D
R_AB_D55
D
R_AB_D56
D
R_AB_D57
D D
R_AB_D58
D
R_AB_D59
D
R_AB_D60 R_AB_D61
D D
R_AB_D62
D
R_AB_D63
M
ZVDDIO
_
R_AB_D[0..63] <10,11>
D
D
LAN
WLAN
+
P P
P P
V
GA
P P
P P
1 2
1
+
439.2_0402_1%
439.2_0402_1%
C
C
R
R
EVENT# pull high
.5V
1
+
1 2
C
7 1K_0402_5%
7 1K_0402_5%
C
R
R
S
S
S
T
T
T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
IE_LANTX_ARX_P1<25>
P
C
IE_LANTX_ARX_N1<25>
P
IE_WLANTX_ARX_P2<23>
C
P
IE_WLANTX_ARX_N2<23>
C
P
0
.95VS_APU_GFX
C
IE_GTX_C_ARX_P0<12>
C
IE_GTX_C_ARX_N0<12>
IE_GTX_C_ARX_P1<12>
C
IE_GTX_C_ARX_N1<12>
C
C
IE_GTX_C_ARX_P2<12>
C
IE_GTX_C_ARX_N2<12>
IE_GTX_C_ARX_P3<12>
C C
IE_GTX_C_ARX_N3<12>
3
1 2
1 1.69K_0402_1%
1 1.69K_0402_1%
RC
RC
P
_
TX_ZVDD
1
0
R
8
R
5
R
4
R
5
N
4
N
0
1
N
8
N
8
W
5
L
4
L
5
J
4
J
5
G
4
G
7
D
7
E
1B
1B
C
C
U
U
_
GPP_RXP0
P
_
GPP_RXN0
P
GPP_RXP1
_
P
GPP_RXN1
_
P
_
GPP_RXP2
P
_
GPP_RXN2
P
GPP_RXP3
_
P
GPP_RXN3
_
P
_
TX_ZVDD_095
P
GFX_RXP0
_
P
_
GFX_RXN0
P
_
GFX_RXP1
P
GFX_RXN1
_
P
GFX_RXP2
_
P
_
GFX_RXN2
P
GFX_RXP3
_
P
GFX_RXN3
_
P
FT3_BGA769
FT3_BGA769
+
3 REV 0.51
3 REV 0.51
T
T
F
F
5
VS
PCIE
PCIE
1
A
2 0
2 0
R
R
GPP
RAPHICS G
1
@
@
GPP_TXP0
_
P
GPP_TXN0
_
P
_
GPP_TXP1
P
_
GPP_TXN1
P
GPP_TXP2
_
P
GPP_TXN2
_
P
GPP_TXP3
_
P
_
GPP_TXN3
P
_
RX_ZVDD_095
P
GFX_TXP0
_
P
_
GFX_TXN0
P
_
GFX_TXP1
P
_
GFX_TXN1
P
GFX_TXP2
_
P
GFX_TXN2
_
P
_
GFX_TXP3
P
GFX_TXN3
_
P
2
_0603_5%
_0603_5%
2
@
@
AN1
F
+
2
L
1
L
2
K
IE_ATX_LANRX_P1
C
P
1
K
IE_ATX_LANRX_N1
C
P
2
J
C
IE_ATX_WLANRX_P2
P
1
J
C
IE_ATX_WLANRX_N2
P
2
H
1
H
7
W
P
2
G
P
IE_ATX_GRX_P0
C
1
G
P
IE_ATX_GRX_N0
C
2
F
P
IE_ATX_GRX_P1
C
1
F
P
C
IE_ATX_GRX_N1
2
E
P
C
IE_ATX_GRX_P2
1
E
P
C
IE_ATX_GRX_N2
2
D
P
C
IE_ATX_GRX_P3
1
D
P
C
IE_ATX_GRX_N3
_
RX_ZVDD
R
R
C
C
CC
CC
C
C C
C
C
C
C
C
C
C
C
C
F
A
N Control Circuit
3
+
.5V
A
N_SPEED1<29>
F
E
M_MAB_EVENT#
M
e
e
curity Classification
curity Classification
curity Classification
e
ssu
ed Date
ed Date
ed Date
ssu
ssu
I
I
I
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
H
3
0
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
2
2
2
o
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
C
C
C
ciphered Date
ciphered Date
ciphered Date
e
e
e
D
D
D
2
1
1 2
C
CC
3 0.1U_0402_16V7K
3 0.1U_0402_16V7K
C
2
1
C
C
4 0.1U_0402_16V7K
4 0.1U_0402_16V7K
C
C
1 2
CC
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
CC
1 2
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
C
C
C
C
12
C
2 1K_0402_1%
2 1K_0402_1%
C
1 2
5
5
C
C
C
C C
C
C
C
C
C
C
C
C
C
6
6
7
7 8
8
9
9
10
10
11
11
12
12
1
1 1 2
1
1 2
1 2
1 2
2
2
2
VGA@
VGA@
VGA@
VGA@
0.1U_0402_16V7KVGA@
0.1U_0402_16V7KVGA@
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7KVGA@
0.1U_0402_16V7KVGA@
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7KVGA@
0.1U_0402_16V7KVGA@
0.1U_0402_16V7KVGA@
0.1U_0402_16V7KVGA@
0.1U_0402_16V7KVGA@
0.1U_0402_16V7KVGA@
0.1U_0402_16V7KVGA@
0.1U_0402_16V7KVGA@
C
IE_ATX_C_LANRX_P1 <25>
P
IE_ATX_C_LANRX_N1 <25>
C
P
IE_ATX_C_WLANRX_P2 <23>
C
P
IE_ATX_C_WLANRX_N2 <23>
C
P
0
.95VS_APU_GFX
+
IE_ATX_C_GRX_P0 <12>
C
P
IE_ATX_C_GRX_N0 <12>
C
P
C
IE_ATX_C_GRX_P1 <12>
P
C
IE_ATX_C_GRX_N1 <12>
P
C
IE_ATX_C_GRX_P2 <12>
P
C
IE_ATX_C_GRX_N2 <12>
P
IE_ATX_C_GRX_P3 <12>
C
P
C
IE_ATX_C_GRX_N3 <12>
P
VS
12
R
R
1
1
1
1
0K_0402_5%
0K_0402_5%
NPWM<29>
A
F
AN1
F
1
1
1
C
C 0
.01U_0402_25V7K
.01U_0402_25V7K
0
@
@
2
i
i
tle
tle
tle
i
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
+
1
D
D
1
1
AS16_SOT23-3
AS16_SOT23-3
B
B
T3 DISP/MISC/HDT
T
T
F
F
F
h
ursday, May 16, 2013
ursday, May 16, 2013
ursday, May 16, 2013
h
h
T
T
T
2
3 DISP/MISC/HDT
3 DISP/MISC/HDT
A
-9868P
-9868P
-9868P
A
A
L
L
L
1
2
1
0U_0603_6.3V6M
0U_0603_6.3V6M
1
1
F
F
J
J
6
G
5
G
4
4
3
3
2
2
1
1
ACES_50273-0040N-001
ACES_50273-0040N-001
3
3
C
C
5
5
5
AN
AN
N N
L
N
A
WLAN
V
GA
@
@
D D
.
0
0
0
.
.
1
1
1
4
f
2
2
2
f
4
f
4
o
o
o
Page 6
CyberForum.ru
5
E
_LCD_TXOUT0+_R
DP
E
DP
_LCD_TXOUT0-_R
A
P
U_HDMI_TX2+<21>
A
U_HDMI_TX2-<21>
D D
H
D
MI
E
DP use 2 Lane for FHD
E
P Cap co-lay
D
A
P
U_TDI
A
U_TCK
P
A
PU_TMS
A
P
U_TRST#
A
P
U_DBREQ#
A
U_RST#
P
A
U_PWRGD
P
EDP/LVDS
A
U_PROCHOT#
P
A
PU_RST#
A
U_PWRGD
P
C1
C1
C1
07
07
C
C
0.1U_0402_16V7K
0.1U_0402_16V7K
S
VT,SVC,SVD, APU_PWRGD is 1.8V Output
PROCHOT is 3.3V Input
VS
3
+
C C
.8VS
1
+
1
.8VS
+
B B
C1
08
08
C
C
EDP@
EDP@
R
R
C2
C2
6 1K_0402_5%
6 1K_0402_5%
C3
C3
2 300_0402_5%
2 300_0402_5%
R
R
4 300_0402_5%
4 300_0402_5%
C3
C3
R
R
1 2 7 3 6 4
C2
C2
R
R
0.1U_0402_16V7K
0.1U_0402_16V7K
1 2
1 2
R
R
P
P
C2
C2
8
5
1K_8P4R_5%
1K_8P4R_5%
8
8
1 2
C
C
C9
9 1000P_0402_50V7K
9 1000P_0402_50V7K
C9
1 2
C9
3
3
C9
C
C
180P_0402_50V8J
180P_0402_50V8J
EDP@
EDP@
12
12
1K_0402_5%
1K_0402_5%
ESD@
ESD@
ESD@
ESD@
P
A
PU_HDMI_TX1+<21>
A
P
U_HDMI_TX1-<21>
A
P
U_HDMI_TX0+<21>
A
P
U_HDMI_TX0-<21>
A
U_HDMI_CLK+<21>
P
A
P
U_HDMI_CLK-<21>
E
_LCD_TXOUT2+_R<20>
DP
E
_LCD_TXOUT2-_R<20>
DP
E
_LCD_TXOUT1+_R<20>
DP
E
_LCD_TXOUT1-_R<20>
DP
E
DP
_LCD_TXOUT0+_R<20>
E
DP
_LCD_TXOUT0-_R<20>
L
CD_TXCLK+<20>
L
CD_
TXCLK-<20>
A
P
U_SVT<38>
A
U_SVC<38>
P
A
U_SVD<38>
P
E
C_
SMB_CK2<13,25,29>
SMB_DA2<13,25,29>
C_
E
U_PWRGD<38>
P
A
U_PROCHOT#<29,38>
P
A
P
U_VDDNB_SEN_H<38>
A
P
U_VDD_SEN_H<38>
A
U_VDD_SEN_L<38>
P
A
close to APU
C1
C1
D
D
12
A
PU_PROCHOT#
@
ESD@
ESD@
@
SCV00001K00
SCV00001K00
close to APU
4
0.1U_0402_16V7K
0.1U_0402_16V7K
1 2
09
EDP@
09
EDP@
CC1
CC1
0.1U_0402_16V7K
0.1U_0402_16V7K
1 2
C1
C1
10
EDP@
10
EDP@
C
C
LVDS@
LVDS@
1
1 2
1
1 2
LVDS@
LVDS@
1 2 1 2
2
2
C7
5 0_0402_5%
5 0_0402_5%
C7
R
R
C7
6 0_0402_5%LVDS@
6 0_0402_5%LVDS@
C7
R
R
C1
C1
07 0_0402_5%LVDS@
07 0_0402_5%LVDS@
C
C
C1
08 0_0402_5%LVDS@
08 0_0402_5%LVDS@
C1
C
C
7 0_0402_5%
7 0_0402_5%
C7
C7
R
R
8 0_0402_5%LVDS@
8 0_0402_5%LVDS@
RC7
RC7
2
2
8
8
T
T
2
2
3
3
T
T T37T3
7
T15T15
T
T
T
T
1
8
8
1
1
9
9
1
E
DP
E
DP
E
DP
E
DP
E E
A
U_PROCHOT#
P
E
_LCD_TXOUT2+
DP
E
DP
_LCD_TXOUT2-
_LCD_TXOUT2+ _LCD_TXOUT2-
_LCD_TXOUT1+ _LCD_TXOUT1-
DP_LCD_TXOUT0+ DP
_LCD_TXOUT0-
L
TXCLK+
CD_
L
TXCLK-
CD_
A
U_RST#
P
A
U_PWRGD
P
A
P
U_ALERT#
A
U_TDI
P
A
P
U_TDO
A
P
U_TCK
A
U_TMS
P
A
U_TRST#
P
A
PU_DBRDY
A
P
U_DBREQ#
V
DDM
EM_SENSE
V
95_FB_H
DD0
V
95_FB_L
DD0
U
U
C
C
C1
C1
DISPLAY/SVI2/JTAG/TEST
T
P1_TXP0
D
T
P1_TXN0
D
T
P1_TXP1
D
T
P1_TXN1
D
T
P1_TXP2
D
T
P1_TXN2
D
T
P1_TXP3
D
T
P1_TXN3
D
L
DP0_TXP0
T
L
DP0_TXN0
T
L
DP0_TXP1
T
L
DP0_TXN1
T
L
T
DP0_TXP2
L
DP0_TXN2
T
L
T
DP0_TXP3
L
DP0_TXN3
T
D
I
SP_CLKIN_H
D
I
SP_CLKIN_L
S
V
T
S
V
C
S
V
D
S
I
C
S
I
D
A
P
U_RST_L
L
T_RST_L
D
A
P
U_PWROK
L
D
T_PWROK
P
OCHOT_L
R
A
ERT_L
L
T
I
D
T
O
D
T
K
C
T
S
M
T
R
ST_L
D
RDY
B
D
REQ_L
B
V
D
DCR_NB_SENSE
V
D
DCR_CPU_SENSE
V
D
DIO_MEM_S_SENSE
V
S
S_SENSE
V
D
D_095_FB_H
V
D
D_095_FB_L
DISPLAY/SVI2/JTAG/TEST
ISPLAY D
MISC
TEST
A
9
B
9
A
0
1
B
0
1
A
1
1
B
1
1
A
2
1
B
2
1
A
4
B
4
A
5
B
5
A
6
B
6
A
7
B
7
K
1
5
H
1
5
G
3
1
D
2
7
E
2
9
B
2
2
B
2
1
B
2
0
A
0
2
B
1
9
A
1
9
A
2
2
B
8
1
D
2
9
D
1
3
D
5
3
D
3
3
G
7
2
B
5
2
A
5
2
D
2
3
G
2
3
E
2
5
E
2
3
A
V
33
A
U
33
MISC
F
F
3 REV 0.51
3 REV 0.51
T
FT3_BGA769 @
FT3_BGA769 @
T
3
D
_150_ZVSS
P
D
P
D
D
P
T
D
T
D
T
L
DP0_AUXP
T
L
DP0_AUXN
T
L
T
D
A
D
D
A
D
A
D
T
T
D
ECRACKMON
I
P
P
B
PASSCLK_H
Y
B
PASSCLK_L
Y
P
L
P
G
O_TSTDTM0_SERIALCLK
I
G
O_TSTDTM0_CLKINIT
I
U
S
B_ATEST0
U
B_ATEST1
S
M
ANALOGIN
_
M
_
ANALOGOUT
T
H
MI_EN/DP_STEREOSYNC
D
2
L
ENBKL : APU to EC to LCD
CD_
B
6
1
D
P
A
1
2
_2K_ZVSS
D
_VARY_BL
D
C_GREEN
D
L
M
DP
B
7
1
LCD_
_BLON
P
A
7
1
L
P
P1_AUXP
P1_AUXN
D
DP0_HPD
A
C_HSYNC
C_VSYNC
D
A
H
H
L
L
LCHRZ_H
LCHRZ_L
M
CD_
_DIGON
A
1
8
L
CD_
D
1
7
A
P
E
1
7
A
P
H
1
9
P1_HPD
D
5
1
E
DP
E
5
1
E
DP
H
7
1
E
DP
B
1
4
A
A
C_BLUE
A
A
C_ZVSS
LTEST1
LTEST0
F
ON_CAL
P
C_RED
A
1
4
A
P
B
1
5
A
P
G
9
1
A
P
E
1
9
D
1
9
A
P
C_SCL
D
2
1
A
P
C_SDA
A
1
6
D
A
H
2
7
ERMDA
H
9
2
ERMDC
D
5
2
A
7
2
B
0
P
B
7
2
B
1
P
A
6
2
B
2
P
B
6
2
B
3
P
B
8
2
A
8
2
B
4
2
A
4
2
A
35
V
A
35
U
E
3
3
TEST
_
A
9
2
EE_2
R
H
1
2
H
5
2
A
J
10
A
8
J
R
2
3
N
3
2
A
29
P
E
1
2
D
P
D
P_STEREOSYNC
Used to align shutter glasses with the interleaved video fram e
RC1
RC1
_150_ZVSS _2K_ZVSS
R
R
ENBKL ENVDD INT_PWM
U_HDMI_CLK U_HDMI_DATA
_LVDS_CLK_R _LVDS_DATA_R
_LVDS_HPD
U_CRT_R
U_CRT_G
U_CRT_B
U_CRT_HSYNC
U_CRT_CLK U_CRT_DATA
1 499_0402_1%
1 499_0402_1%
RC2
RC2
C_ZVSS
T
ST4
E
T
ST5
E
T
EST14
T
E
ST15
T
E
ST16
T
ST17
E
T
E
ST18
T
E
ST19
T
ST25_H
E
T
ST25_L
E
T
EST28_H
T
E
ST28_L
T
ST31
E
T
E
ST36
T
ST37
E
T
ST42
E
T
E
ST43
T
E
ST39
T
E
ST40
T
ST41
E
_STEREOSYNC
C9 2
C9 2
1
2
1
3 150_0402_1%
3 150_0402_1%
2
1
01 0_0402_5%LVDS@
01 0_0402_5%LVDS@
C1
C1
C
C
03 0_0402_5%LVDS@
03 0_0402_5%LVDS@
C1
C1
C
C
1 2
1
K_0402_1%
K_0402_1%
2
2
T
T
1
1
2
2
T
T
3
T3T
4
4
T
T
5
T5T
6
T6T T
T3
4
4
3
T
T
3
3
5
5
r
oute TEST25_H/L AND TEST28_H/L differentially
7
7
T
T
8
8
T
T
9
T9T
NOTE: DP_STEREOSYNC & APU_HSYN C PU FOR INTERNAL(HDMI enable), DP_STER EOSYNC & APU_HSYNC PD FOR CUSTOMER(HDMI disable)
T
T
1
1
2
2
1
1
3
3
T
T
1
1
4
4
T
T
6
6
1
1
T
T
1
1
7
7
T
T
LVDS_CLK&LVDS_DATA layout follow EDP AUX route 85 ohm
L
CD_
ENBKL <20,29>
L
ENVDD <20>
CD_
L
INT_PWM <20>
CD_
A
P
U_HDMI_CLK <21>
A
U_HDMI_DATA <21>
P
DM
I_HPD <21,8>
H
_LVDS_CLK <20>
DP
E
_LVDS_DATA <20>
DP
E
DP
_LVDS_HPD <20>
E
A
P
U_CRT_R <22>
A
U_CRT_G <22>
P
A
P
U_CRT_B <22>
A
P
U_CRT_HSYNC <22>
A
U_CRT_VSYNC <22>
P
P
U_CRT_CLK <22>
A
A
PU_CRT_DATA <22>
EDP/LVDS
HDMI
EDP/LVDS
C
R
T
1
EDP
_LVDS_CLK_R
E
DP
_LVDS_DATA_R
HDMI DDC PU RES move to HDMI page
A
U_CRT_DATA
P
A
U_CRT_CLK
P
A
P
U_CRT_HSYNC
E
_LVDS_HPD
DP
E
DP Cap co-lay
C1
C1
01
01
C
C
EDP@
EDP@
0.1U_0402_16V7K
0.1U_0402_16V7K
E
DP_LVDS_HPD
L
CD_
ENBKL
L
INT_PWM
CD_
A
PU_CRT_R
A
P
U_CRT_G
A
U_CRT_B
P
A
U_CRT_HSYNC
P
T
E
ST25_L
T
ST36
E
T
E
ST37
D
_STEREOSYNC
P
T
EST36
T
E
ST37
T
ST25_H
E
A
U_ALERT#
P
D
_STEREOSYNC
P
T
ST19
E
T
E
ST18
1 2
R
R
C1
C1
4 4.7K_0402_5%LVDS@
4 4.7K_0402_5%LVDS@
1 2
5 4.7K_0402_5%LVDS@
5 4.7K_0402_5%LVDS@
C1
C1
R
R
2
C1
C1
7 4.7K_0402_5%
7 4.7K_0402_5%
R
R
C1
C1
2 4.7K_0402_5%
2 4.7K_0402_5%
R
R
1 2
C1
8 1K_0402_5%
8 1K_0402_5%
C1
R
R
2
C4
C4
5 100K_0402_5%
5 100K_0402_5%
R
R
C
C
C1
C1
03
03
EDP@
EDP@
0.1U_0402_16V7K
0.1U_0402_16V7K
2
C4
C4
4 100K_0402_5%
4 100K_0402_5%
R
R
R
R
9 100K_0402_5%
9 100K_0402_5%
C1
C1
2
C2
C2
0 100K_0402_5%
0 100K_0402_5%
R
R
1 2
R
R
C2
C2
2 150_0402_1%
2 150_0402_1%
1 2
C2
C2
4 150_0402_1%
4 150_0402_1%
R
R
1 2
R
R
C2
C2
7 150_0402_1%
7 150_0402_1%
1
R
R
C3
C3
0 1K_0402_5%
0 1K_0402_5%
1
C3
C3
5 510_0402_1%
5 510_0402_1%
R
R
1 2
C3
C3
7 1K_0402_5%@
7 1K_0402_5%@
R
R
1 2
C3
9 1K_0402_5%@
9 1K_0402_5%@
C3
R
R
1 2
C3
6 1K_0402_5%@
6 1K_0402_5%@
C3
R
R
1 2
1 1K_0402_5%@
1 1K_0402_5%@
C4
C4
R
R
1 2
C4
C4
6 1K_0402_5%@
6 1K_0402_5%@
R
R
1
3 510_0402_1%
3 510_0402_1%
C4
C4
R
R
1 8 2 7 3 6 4
@
@
EDP@
EDP@
1
12
1
@
@
2
R
R
P
C4
C4
P
1K_8P4R_5%
1K_8P4R_5%
3
VS
+
1
12
1
1
.8VS
+
2
2
VS
3
+
1
.8VS
5
+
A A
e
e
curity Classification
curity Classification
curity Classification
e
S
S
S
ssu
ssu
ed Date
ed Date
ed Date
ssu
I
I
I
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
H
T
T
T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
2
2
2
o
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
C
C
C
e
e
ciphered Date
ciphered Date
ciphered Date
e
D
D
D
i
tle
tle
tle
i
i
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
T
T
3 DISP/MISC/HDT
3 DISP/MISC/HDT
3 DISP/MISC/HDT
T
F
F
F
-9868P
-9868P
-9868P
A
A
A
L
L
L
h
ursday, May 16, 2013
ursday, May 16, 2013
ursday, May 16, 2013
h
h
T
T
T
1
o
.0
.0
.0
1
1
1
4
f
f
2
2
2
4
f
4
6
6
o
o
6
Page 7
CyberForum.ru
5
S
A
TA_ATX_DRX_P0<23>
SA
TA HDD
SA
D D
SATA ODD
VGA
LAN WLAN
C C
EC
TA_ATX_DRX_N0<23>
S
TA_DTX_C_ARX_N0<23>
A
S
TA_DTX_C_ARX_P0<23>
A
S
TA_ATX_DRX_P1<23>
A
S
TA_ATX_DRX_N1<23>
A
S
A
TA_DTX_C_ARX_N1<23>
S
A
TA_DTX_C_ARX_P1<23>
+
.95VS
0
C
K_PCIE_VGA<12>
L
C
K_PCIE_VGA#<12>
L
C
L
K_LAN<25>
C
L
K_LAN#<25>
C
K_WLAN<23>
L
C
LK_WLAN#<23>
C
K_PCI_EC<29,8>
L
C
LK_PCI_DDR<8>
L
C_AD0<29>
P
L
C_AD1<29>
P
L
C_AD2<29>
P
L
P
C_AD3<29>
L
C_FRAME#<29,8>
P
S
RIRQ<29>
E
8 1K_0402_1%
8 1K_0402_1%
C5
C5
R
R
9 1K_0402_1%
9 1K_0402_1%
C5
C5
R
R
4
2
1 12
EMI@
EMI@
1 2
2 22_0402_5%
2 22_0402_5%
C6
C6
R
R
1 2
C6
3 0_0402_5%
3 0_0402_5%
C6
R
R
@EMI@
@EMI@
T
T
2
2
S
A
S
A
0
0
TA_ZVSS TA_ZVSS_095
S
TA_ACT
A
4
M_X1
8
4
8
M_X2
L
C_CLK0
P
L
C_CLK1
P
3
UC1E
UC1E
14
A
B
TA_TX0P
A
S
14
Y
A
TA_TX0N
A
S
B
16
A
S
TA_RX0N
A
A
Y
16
S
A
TA_RX0P
A
19
Y
S
TA_TX1P
A
B
19
A
S
TA_TX1N
A
A
Y
17
S
A
TA_RX1N
B
A
17
S
TA_RX1P
A
A
19
R
S
TA_ZVSS
A
A
P
19
S
A
TA_ZVDD_095
B
A
30
S
A
TA_ACT_L/GPIO67
A
12
Y
S
TA_X1
A
B
12
A
S
TA_X2
A
U
4
G
F
X_CLKP
U
5
G
F
X_CLKN
A
8
C
G
P_CLK0P
P
A
C
10
G
P
P_CLK0N
A
E
4
G
P
P_CLK1P
A
5
E
G
P_CLK1N
P
A
C4
G
PP_CLK2P
A
C5
G
PP_CLK2N
A
A
5
G
P_CLK3P
P
A
4
A
G
P_CLK3N
P
A
13
P
X
4M_25M_48M_OSC
1
N
2
X
4
8M_X1
N
1
X
4
8M_X2
A
2
Y
L
CCLK0
P
A
2
W
L
CCLK1
P
A
T
2
L
A
D0
A
T
1
L
A
D1
A
R
2
L
A
D2
A
1
R
L
D3
A
A
2
P
L
RAME_L
F
A
1
P
L
RQ0_L
D
A
29
V
S
RIRQ/GPIO48
E
A
25
P
L
C_CLKRUN_L
P
A
2
V
L
PC_PD_L/GEVENT5_L/SPI_TPM_CS_L
FT3_BGA769 @
FT3_BGA769 @
CLK/SATA/USB/SPI/LPC
CLK/SATA/USB/SPI/LPC
ATACLK S
LPC
F
F
T
3 REV 0.51
3 REV 0.51
T
S
U
S
BCLK/14M_25M_48M_OSC
U
B_ZVSS
S
U
B_HSD0P
S
U
S
B_HSD0N
U
B_HSD1P
S
U
B_HSD1N
S
U
S
B_HSD2P
U
S
B_HSD2N
U
B_HSD3P
S
U
S
B_HSD3N
U
B_HSD4P
S
U
S
B_HSD4N
U
B_HSD5P
S
U
B_HSD5N
S
U
S
B_HSD6P
U
B_HSD6N
S
U
USBSPI
B_HSD7P
S
U
S
B_HSD7N
U
B_HSD8P
S
U
B_HSD8N
S
U
S
B_HSD9P
U
B_HSD9N
S
U
S
B_SS_ZVSS
U
B_SS_ZVDD_095_USB3_DUAL
S
B_SS_0TXP
U
S
B_SS_0TXN
U
B_SS_0RXP
S
U
S
B_SS_0RXN
U
B_SS_1TXP
S
U
B_SS_1TXN
S
U
S
B_SS_1RXP
U
B_SS_1RXN
S
U
I_CLK/GPIO162
P
S
P
I_CS1_L/GPIO165
S
P
I_CS2_L/GPIO166
S
I_DO/GPIO163
P
S
P
I_DI/GPIO164
S
P
I_HOLD_L/GEVENT9_L
S
P
I_WP_L/GPIO161
S
2
4
W
4
G
A
U
B_ZVSS
S
4
L
A
L
5
A
4
J
A
5
J
A
G
7
A
G
8
A
1
G
A
G
2
A
1
F
A
F
2
A
1
E
A
2
E
A
D
1
A
D
2
A
1
C
A
C
2
A
1
B
A
2
B
A
A
1
A
2
A
A
E
10
A
U
S
BSS_ZVSS
E
8
A
U
S
BSS_ZVDD
2
T
1
T
2
V
1
V
1
R
2
R
1
W
2
W
7
U
A
A
9
W
A
A
R
4
A
A
R
11
A
A
R
7
A
A
U
11
A
9
U
A
A
1 2
C5
C5
7 11.8K_0402_1%
7 11.8K_0402_1%
R
R
U_SPI_CLK
P
U_SPI_CS1#
P
U_SPI_CS2#
P P
U_SPI_MOSI
P
U_SPI_MISO
P
U_SPI_WP#
1 2
C6
C6
0 1K_0402_1%
0 1K_0402_1%
R
R
1 2
C6
C6
1 1K_0402_1%
1 1K_0402_1%
R
R
1 2
@
@
0_0402_5%
0_0402_5%
C1
C1
30
30
R
R
2
1
1
2
T
T
2
2
2
2
T
T
U
S
B20_P0 <24>
U
S
B20_N0 <24>
U
S
B20_P1 <23>
U
S
B20_N1 <23>
U
B20_P2 <28>
S
U
B20_N2 <28>
S
U
S
B20_P3 <20>
U
B20_N3 <20>
S
U
S
B20_P4 <20>
U
S
B20_N4 <20>
U
B20_P8 <24>
S
U
B20_N8 <24>
S
U
SB20_P9 <24>
U
S
B20_N9 <24>
U
SB30_TX0P <24>
U
S
B30_TX0N <24>
U
B30_RX0P <24>
S
U
B30_RX0N <24>
S
U
B30_TX1P <24>
S
U
SB30_TX1N <24>
U
B30_RX1P <24>
S
U
B30_RX1N <24>
S
A
PU_SPI_CLK_R
R
R
10_0402_5%
10_0402_5%
@EMI@
@EMI@
C
C
10P_0402_50V8J
10P_0402_50V8J
@EMI@
@EMI@
U
WLAN (BT) Cardreader Int. Camera
Touch Screen
USB2.0-Right1
USB2.0-Right2
+
0
.95VALW
USB3.0-Right1
USB3.0-Right2
12
C1
C1
0
0
2
3
3
C1
C1
1
B2.0-Left1 (Debug Port)
S
1
B B
4
8KMHz CRYSTAL
4
8
M_X2
4
8
1
4
1
2
M_X1
C2
3
3
C2
C
C
4.7P_0402_50V8J
4.7P_0402_50V8J
S
S
S
e
ecurity Classification
curity Classification
curity Classification
e
I
I
I
ssu
ed Date
ed Date
ssued Date
ssu
T
T
T
H
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
2
2
0
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
3
C6
C6
4 1M_0402_5%
4 1M_0402_5%
R
R
2
2
3
3
C1
C1
Y
Y
8MHZ_8PF_X3S048000D81H-W
8MHZ_8PF_X3S048000D81H-W
4
4
1
2
2
C2
C2
C
C
4.7P_0402_50V8J
4.7P_0402_50V8J
2
A A
1
4
5
S
P
I ROM
E
C_
SPIDO<29>
E
C_
SPIDI<29>
E
SPICLK<29>
C_
E
C_
SPICS#<29>
1
6 10K_0402_5%
6 10K_0402_5%
C6
C6
R
R
+
VALW_APU
3
S
ocket: SP07000F500/SP07000H900
Please place UC5 close to UC1 APU,
4
MB ROM P/N:
SA00004LI00
C
C
C
o
ompal Secret Data
mpal Secret Data
mpal Secret Data
o
D
D
D
e
ciphered Date
ciphered Date
eciphered Date
e
885@
885@
1
01 33_0402_5%
01 33_0402_5%
C1
C1
R
R
885@
885@
1
C1
C1
02 33_0402_5%
02 33_0402_5%
R
R
885@
885@
1 2
R
R
C1
21 33_0402_5%
21 33_0402_5%
C1
885@
885@
1 2
C1
C1
24 33_0402_5%
24 33_0402_5%
R
R
2
2
2 2
A
P
U_SPI_MOSI
A
PU_SPI_CLK_R
A
U_SPI_CS1#
P
S
W
said ROM can change to 4MB
T
T
T
i
i
tle
tle
tle
i
F
F
F
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
T
T
T
T
h
h
ursday, May 16, 2013
ursday, May 16, 2013
ursday, May 16, 2013
h
4
M Byte
C5
C5
U
U
5
I
S
6
C
S
1
S
C
7
O
H
3
P
W
8
C
V
2
M
M
X25L3205DM2I-12G SO8
X25L3205DM2I-12G SO8
5
5
C2
C2
C
C
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
3-SATA/CLK/USB/SPI/LPC
3-SATA/CLK/USB/SPI/LPC
3-SATA/CLK/USB/SPI/LPC
L
L
L
A
A-9868P
-9868P
-9868P
A
2
A
P
O
S
U_SPI_MISO
LK
LD
4
N
C
D
G
7
7
7
1
1
1
1
.0
.0
o
o
o
.0
4
f
4
2
2
2
4
f
f
Page 8
CyberForum.ru
CH7
CH7
@
@
8
5
12
A
U_PCIE_WAKE#
P
1
A
P
U_GPIO174
10P_0402_50V8J
10P_0402_50V8J
FAULT
G
E
VENT2
R
C_CLK
T
5
D
D
C2
C2
21
51H-40PT_SOD323-2
51H-40PT_SOD323-2
29
29 C
C C
C
S
Y
S S
U
S
U
S
U
SB_CHG_OC#
O
DD_
A
Z_
BITCLK_HD
H
DA_BITCLK
A
Z_
SDIN0_HD
C3
C3
0
0
C
C
1
20M_0402_5%
20M_0402_5%
C
C
1
1
C3
C3
1 2
CLKGEN ENABLE
D
EFAULT DEFAULT
CLKGEN DISABLED
12
1
2
5
+
1
.8VALW
71
71 C
C R
R
1 2
2
1
1U_0402_6.3V6K
1U_0402_6.3V6K
S_PWRGD
P_S3#
L LP_S5#
B_OC#0 B_OC#2
PLUGIN#
10P_0402_50V8J
10P_0402_50V8J
2
C1
C1
R
R
8P_0402_50V8D
8P_0402_50V8D
@
@
R
R
07
07
C1
C1
10K_0402_5%
10K_0402_5%
12
12
C1
C1
R
R 2K_0402_5%
2K_0402_5%
1 2
7
7
C9
C9
C
C
180P_0402_50V8J
180P_0402_50V8J
47K_0402_5%
47K_0402_5%
R
MRST#
S
A
MD G3-S5 clock issue
A
Z_
BITCLK_HD<26>
A
SDOUT_HD<26>
Z_
A
Z_
SDIN0_HD<26>
A
Z_
SYNC_HD<26>
A
RST_HD#<26>
Z_
C2
C2
Y
Y
1
04
04
2
4
1
2.768KHZ_7PF_Q13MC1461000100
2.768KHZ_7PF_Q13MC1461000100
3
3
SPI ROM 1.8V SPI ROM
LPC ROM
12
R
R 10K_0402_5%
10K_0402_5%
12
@
@
R
R 2K_0402_5%
2K_0402_5%
12
C1
C1
08
08
C1
C1
13
13
C1
C1
R
R 10K_0402_5%
10K_0402_5%
1
@
@
C1
C1
R
R 2K_0402_5%
2K_0402_5%
2
06
06
11
11
ESD@
ESD@
3
2
3.3V SPI ROM
DEFAULT
1
2
12
F
ollow check list & ORB_0C design 10 ms RC delay circuit on +1.8-V S5 power rail.
E
C_RSMRST#<29>
D D
.8VALW
1
+
1 2
R
R
27 10K_0402_5%
27 10K_0402_5%
C1
C1
+
3VALW_APU
VALW_APU
3
+
C C
S
TRAP PINS
B B
PULL HIGH
P LOW
A A
S
LP_S3#, SLP_S5# PU reserve
1 2
C1
28 2.2K_0402_5%
28 2.2K_0402_5%
C1
R
R
1 2
29 2.2K_0402_5%
29 2.2K_0402_5%
C1
C1
R
R
@
@
C5
C5
P
P
R
R
1 2 7 3 6 4
100K_8P4R_5%
100K_8P4R_5%
10K_0402_5%
10K_0402_5%
C2
C2
3
3
R
R
R
R
C2
5
5
C2
2
10K_0402_5%
10K_0402_5%
EMI@
EMI@
C1
5
5
C1
C
C
1 2
1 2
R
R
6 10K_0402_5%@
6 10K_0402_5%@
C9
C9
1 2
C9
7 10K_0402_5%@
7 10K_0402_5%@
C9
R
R
B
OOT FAIL TIMER
BOOT FAIL TIMER
LL
U
DISABLED
D
E
C
L
K_PCI_EC<29,7>
C
K_PCI_DDR<7>
L
L
C_FRAME#<29,7>
P
4
SY
S_PWRGD
c
lose to APU
P
TN_OUT#<29>
B
S
YS_PWRGD<29>
A
U_PCIE_WAKE#<25>
P
S
P_S3#<29>
L
S
P_S5#<29>
L
T
ST0/2
E
K
_RST#<29>
B
G
TEA20<29>
A
E
C_SCI#<29>
E
C_
SMI#<29>
S
P_CHG_CB0<24>
L
S
LP_CHG_CB1<24>
L
N_EN<25>
A
C
L
KREQ_WLAN#<23>
S
PK_DET<27>
C
KREQ_LAN#<25>
L
C
KREQ_PEG#<13>
L
U
B_OC#0<24,29>
S
U
B_CHG_OC#<24,29>
S
O
PLUGIN#<23>
DD_
U
SB_OC#2<24,29>
EMI@
EMI@
2
1
RC9
RC9
2 33_0402_5%
2 33_0402_5%
1 2
C9
3 33_0402_5%
3 33_0402_5%
C9
R
R
1 2
C9
C9
8 33_0402_5%
8 33_0402_5%
R
R
1 2
C1
00 33_0402_5%
00 33_0402_5%
C1
R
R
3
2K_X1
3
K_X2
2
+
3
VALW_APU
12
@
@
09
09
C1
C1
R
R 10K_0402_5%
10K_0402_5%
C1
14
14
C1
R
R 2K_0402_5%
2K_0402_5%
12
4
C1
C1
R
R 10K_0402_5%
10K_0402_5%
@
@
C1
C1
R
R 2K_0402_5%
2K_0402_5%
C_RST#_R
LP A
U_PCIE_RST#_R
P
R
S
MRST#
S
Y
A
P
U_PCIE_WAKE#
S
P_S3#
L
S
P_S5#
L
5
5
2
2
T
T
3
2
3
2
RTC_CLKCLK_PCI_EC CLK_PCI_DDR LPC_FRAME# GEVENT2
NORMAL POWR UP/RESET TIMING
DEFAULT
FAST POWER UP/RESET TIMING FOR SIMULATION
10
10
15
15
S_PWRGD
T
T
T
E
ST1/TMS
U
B_OC#0
S
U
B_CHG_OC#
S
O
DD_
PLUGIN#
U
B_OC#2
S
H
DA
_BITCLK
H
DA
_SDOUT
A
Z_
SDIN0_HD
H
DA
_SYNC
H
_RST#
DA
K_X1
K_X2
3
D
D
UC1
UC1
A
Y
4
L
P
C_RST_L
A
Y
9
P
C
IE_RST_L
A
Y
5
R
S
MRST_L
BA
8
P
W
R_BTN_L
A
19
M
P
W
R_GOOD
A
7
Y
2
2
3
3
S
S_RESET_L/GEVENT19_L
Y
A
11
W
W
KE_L/GEVENT8_L
A
A
3
Y
S
P_S3_L
L
B
5
A
S
P_S5_L
L
A
13
U
T
ST0
E
A
Y
10
T
E
ST1/TMS
A
Y
6
T
E
ST2
A
23
R
K
B
RST_L
A
31
R
G
20IN/GEVENT0_L
A
A
5
N
L
C_PME_L/GEVENT3_L
P
A
7
L
L
C_SMI_L/GEVENT23_L
P
A
15
P
A
_PRES/IR_RX0/GEVENT16_L
C
A
13
V
I
_TX0/GEVENT21_L
R
B
9
A
I
_TX1/GEVENT6_L
R
B
10
A
I
_RX1/GEVENT20_L
R
A
15
V
I
_LED_L/LLB_L/GPIO184
R
A
29
U
C
K_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60
L
A
29
W
C
K_REQ1_L/GPIO61
L
A
27
R
C
K_REQ2_L/GPIO62
L
A
27
V
C
K_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63
L
A
29
Y
C
K_REQG_L/GPIO65/OSCIN
L
A
8
Y
U
B_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L
S
A
1
W
U
B_OC1_L/TDI/GEVENT13_L
S
A
1
V
U
B_OC2_L/TCK/GEVENT14_L
S
A
1
Y
U
B_OC3_L/TDO/GEVENT15_L
S
A
2
N
A
_BITCLK
Z
A
1
N
A
_SDOUT
Z
A
K
2
A
Z
_SDIN0/GPIO167
A
K
1
A
Z
_SDIN1/GPIO168
A
1
M
A
Z
_SDIN2/GPIO169
A
L
2
A
Z
_SDIN3/GPIO170
A
M
2
A
Z
_SYNC
A
L
1
A
Z
_RST_L
A
J
2
X
3
2K_X1
A
J
1
X
3
2K_X2
FT3_BGA769 @
FT3_BGA769 @
P
ANEL_SEL
T
O
UCH_SEL
Sleep&
SM_EN
PlayMusic (ALC269)
PX5 Reserved DIS UMA
SPK_DET
ACPI/SD/AZ/GPIO/RTC/MISC
ACPI/SD/AZ/GPIO/RTC/MISC
Sequence
R
TC CLK
H L
eDP panel
H L
Non Touch
Touch
Panel
Panel
(turn off EHCI)
H
ALC259
B
oard_ID0
0 0 1 1
Onkyo
No Brand
0 1
IR
F
F
T
3 REV 0.51
3 REV 0.51
T
L
LVDS panel
Board_ID1Board Conf.
MSICHDA
0 1 0 1
D S
GPIO
P
X P B
o B
F
o
r DIS
P
S
_PWR_CTRL
D
S
_CLK/GPIO73
D
S
_CMD/GPIO74
D
S
D
_CD/GPIO75
S
D
_WP/GPIO76
S
D
_DATA0/GPIO77
S
_DATA1/GPIO78
D
S
_DATA2/GPIO79
D
S
_DATA3/GPIO80
D
S
D
_LED/GPIO45
S
L0/GPIO43
C
S
A0/GPIO47
D
S
C
L1/GPIO227
S
D
A1/GPIO228
S
P
KR/GPIO66
G
G
E
VENT2_L
G
E
VENT4_L
G
E
VENT7_L
G
VENT10_L
E
G
VENT11_L
E
G
VENT17_L
E
B
INK/GEVENT18_L
L
G
VENT22_L
E
G
NINT1_L/GPIO32
E
G
NINT2_L/GPIO33
E
F
NOUT0/GPIO52
A
F
NIN0/GPIO56
A
S_PWREN
XS_EN#
ard_ID0 ard_ID1
o
S_PWREN
X
G
G
G
G
G
G
G
G
G
G
G
G
P
R
B
23
A
A
22
Y
A
23
Y
A
Y
20
B
A
20
B
A
22
A
21
Y
A
24
Y
B
24
A
A
Y
25
A
25
U
A
U_SCLK0
P
A
25
V
A
U_SDATA0
P
A
Y
11
A
U_SCLK1
P
B
A
11
A
U_SDATA1
P
A
P
27
P
IO49
A
Y
28
P
IO50
P
IO51
P
IO55
P
IO57
P
IO58
P
IO59
P
IO64
P
P
IO68
P
IO69
P
IO70
P
IO71
IO174
T
CCLK
W
B
28
A
A
23
V
P
A
21
P
B
26
A
B
A
19
V
B
A
27
Y
P
B
A
27
A
21
U
P
A
Y
26
T
A
V
21
S
A
M
21
B
A
3
A
A
17
V
G
B
A
4
A
R
15
A
17
P
H
A
P
11
A
8
N
O
A
17
U
B
6
A
E
B
29
A
A
23
P
A
31
V
A
31
U
A
V
11
R
T
C6
C6
P
P
R
R
1 8 2 7 3 4 5
10K_8P4R_5%
10K_8P4R_5%
VGA@
VGA@
Q
Q
C3
C3
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
6
Q
Q
B
B
C3
C3
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
34
VGA@
VGA@
E
PXCONTROL
C_
5
P
S_RST#
X
C4
C4
C
C
O
DD_DA#_APU
C1
C1
C
C
_CLEAR#
A
NEL_SEL
ard_ID0
o
ard_ID1
o X
S_RST#
S_PWREN
X
O
M
P
U_GPIO174
VENT2
E
DM
DD_
C_
C_CLK
A
A
2
1
8
8
1 2
04
04
J
J
UCH_SEL _DET
I_HPD_N
DA#_APU
LID_OUT#
3
+
3
+
6
P
lace at GPU
1
VGA@
VGA@
P
XS_EN#
@ESD@
@ESD@
2
180P_0402_50V8J
180P_0402_50V8J
ESD@
ESD@
180P_0402_50V8J
180P_0402_50V8J
2
U_PCIE_RST#_R
AP
L
C_RST#_R
P
A
U_SCLK0 <10,11,23>
P
A
U_SDATA0 <10,11,23>
P
A
U_SCLK1 <30>
P
A
U_SDATA1 <30>
P
2
1
P
P
W @
W @
G
PIO174 PD CHK1.03
VS VALW_APU
E
C_
PXCONTROL <29>
PCIE_RST# is for PCIE devices on APU
1 2
8 33_0402_5%
8 33_0402_5%
C6
C6
R
R
1
C2
C2
8
8
C
C
150P_0402_50V8J
150P_0402_50V8J
A_RST# is for LPC devices
1
3 33_0402_5%
3 33_0402_5%
RC7
RC7
150P_0402_50V8J
150P_0402_50V8J
O
PWR <31>
DD_
P
S_RST# <12>
X
A
P
U_SPKR <26>
P
X
S_PWREN <14,39>
SW request
E
C_
LID_OUT# <29>
V
G
A_PWRGD <15,39>
R
T
C_CLK <29>
O
D DA#
D
0.1U_0402_16V4Z
0.1U_0402_16V4Z
H
2
2
1
C
C
7
7
C2
C2
2
A
U SMBus0 for S0 , SMBus1 for S 5
P
If APU_SMBUS no use pull high 10K
A
PU_SDATA0
A
P
U_SCLK0
A
P
U_SCLK1
A
P
S
M
_DET
B
o
ard_ID0
B
ard_ID1
o
P
S_RST#
X
S
M_DET
E
LID_OUT#
C_
DM
I_HPD_N
P
NEL_SEL
A
O
DA#_APU
DD_
1
2
2
C3
C3
C
C
@
@
2
2
C7
C7
2
2
R
R
@
@
100K_0402_5%
100K_0402_5%
1
R
RC7
4
4
C7
100K_0402_5%
100K_0402_5%
@
@
1 2
U_SDATA1
1 2
35 10K_0402_5%
35 10K_0402_5%
C1
C1
R
R
269@
269@
1
C1
C1
37 10K_0402_5%UMA@
37 10K_0402_5%UMA@
R
R
1 2
38 10K_0402_5%
38 10K_0402_5%
C1
C1
R
R
UMA@
UMA@
VGA@
VGA@
C1
C1
33
33
R
R
1 2
1 2
36 1K_0402_5%
36 1K_0402_5%
C1
C1
R
R
259@
259@
1 2
C9
C9
4 10K_0402_5%
4 10K_0402_5%
R
R
3
VS
+
2
G
G
C2
C2
Q
Q 2
N7002KW_SOT323-3
N7002KW_SOT323-3
2
1 3
D
D
VS
3
+
C1
25
25
C1
R
R 10K_0402_5%
10K_0402_5%
EDP@
EDP@
1 2
C1
26
26
C1
R
R 10K_0402_5%
10K_0402_5%
LVDS@
LVDS@
1 2
3
VS
+
+
2
1
6
A
A
C1
C1
Q
Q 2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
1
C1
C1
P
P
R
R
1 8 2 3 6 4 5
2.2K_8P4R_5%
2.2K_8P4R_5%
2
S
S
T
VS
3
2
R
R
05
05
C1
C1
10K_0402_5%
10K_0402_5%
1
A
1K_0402_5%
1K_0402_5%
O
U_PCIE_RST# <12,23,25>
P
L
PC_RST# <29>
7
3
VS
+
VALW_APU
3
+
+
3
VS
3
VALW_APU
+
H
DM
I_HPD <21,6>
VRAM_SEL Control by X76
VS
3
+
R
R
C9
C9
5
5
10K_0402_5%
10K_0402_5%
TOUCH@
TOUCH@
1 2
UCH_SEL
2
9
9
C9
C9
R
R 1K_0402_5%
1K_0402_5%
NTOUCH@
NTOUCH@
1
O
DA# <23>
DD_
close to APU
e
curity Classification
curity Classification
curity Classification
e
e
S
S
S
ssu
ssu
ed Date
ed Date
ed Date
ssu
I
I
I
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
H
T
T
T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
2
2
2
o
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
C
C
C
e
e
ciphered Date
ciphered Date
ciphered Date
e
D
D
D
i
tle
tle
tle
i
i
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
T
T
3 GPIO/AZ/MISC
3 GPIO/AZ/MISC
3 GPIO/AZ/MISC
T
F
F
F
A
-9868P
-9868P
-9868P
A
A
L
L
L
h
h
ursday, May 16, 2013
ursday, May 16, 2013
ursday, May 16, 2013
h
T
T
T
1
o
.0
.0
.0
1
1
1
4
4
f
2
2
2
f
4
f
8
8
o
o
8
Page 9
CyberForum.ru
5
5V OF APU
1.
+
.5V
1
3
A
@
2
1
1
4010U_0603_6.3V6M
4010U_0603_6.3V6M
3910U_0603_6.3V6M
3910U_0603_6.3V6M C
C C
C
D D
2
330.1U_0402_16V7K
C
C
C
C330.1U_0402_16V7K
C
C
C
C
2
2
2
2
2
340.1U_0402_16V7KCC340.1U_0402_16V7K
410.1U_0402_16V7K
410.1U_0402_16V7K
350.1U_0402_16V7K
350.1U_0402_16V7K
420.1U_0402_16V7K
420.1U_0402_16V7K
C
C
C
C
C
C
C
C
C
C
CC
C
C
1
1
1
1
2
2
2
360.1U_0402_16V7K
360.1U_0402_16V7K
430.1U_0402_16V7K
430.1U_0402_16V7K C370.1U_0402_16V7KCC370.1U_0402_16V7K
C
C
C
C
C
C
C
C
C
1
1
1
1
@
1
4
4
CC1
CC1
2
U_0805_6.3V6M
U_0805_6.3V6M 7
7 4
4
AMD CKL v1.01
VDDIO_MEM_S
AMD CKL v1.01 4.7uF
1.8VALW & 1.8VS OF APU
VDD_18
VDD_18_ALW
+
1
+
.8VALW
1
1 2
@
@
R
R
16 0_0603_5%
16 0_0603_5%
C1
C1
C C
1
1
501U_0402_6.3V6KCC501U_0402_6.3V6K
494.7U_0603_6.3V6K
494.7U_0603_6.3V6K C
C
CC
C
C
2
2
+
.8VALW_APU
1
0
.5A
1
1
511U_0402_6.3V6K
511U_0402_6.3V6K
521U_0402_6.3V6K
521U_0402_6.3V6K
C
C
C
C
C
C
C
C
2
1
1
1
551U_0402_6.3V6K
551U_0402_6.3V6K
541U_0402_6.3V6K
541U_0402_6.3V6K
531U_0402_6.3V6K
531U_0402_6.3V6K
C
C
C
C
C
C
C
C
C
C
C
C
2
2
2
2
.8VS
5710U_0603_6.3V6M
5710U_0603_6.3V6M C
C C
C
3.3VALW & 3.3VS OF APU
+
1
1
721U_0402_6.3V6KCC721U_0402_6.3V6K CC
2
V
DDIO_AZ_ALW
VDDIO_33_ALW
VDDIO_33
+
RT
.5VS
f
or VDDIO_AZ_ALW 0.1A
1
1
664.7U_0603_6.3V6K
664.7U_0603_6.3V6K
671U_0402_6.3V6K
671U_0402_6.3V6K C
C
C
C
C
C
C
C
2
2
P
lace on TOP
4.7uF 1uF 180pFAMD CKL v1.01
1 3 1
C_APU
4
.5uA
1
98
98 C
C C
C
2
0.22U_0402_16V7K
0.22U_0402_16V7K
+
3
VALW_APU
for VDDIO_33_ALW 0.2A
+
VS
3
R
R
C1
C1
+
3
VS_APU
1 2
@
@
17 0_0603_5%
17 0_0603_5%
0.2A
1
711U_0402_6.3V6K
711U_0402_6.3V6K C
C C
C
2
1
1
741U_0402_6.3V6K
741U_0402_6.3V6K
751U_0402_6.3V6K
751U_0402_6.3V6K C
C
C
C
C
C
C
B B
C
2
2
RTC OF APU
A A
+
3
VL
2
CH7
CH7
51H-40PT_SOD323-2
51H-40PT_SOD323-2
+
RT
C5
C5
D
D
C
1
5
4
10uF 0.1uF 180pF
2 8 4
10uF 1uF 180pF
1 7 1
1 6 1
1
1
2
1
1
1
1
601U_0402_6.3V6K
601U_0402_6.3V6K
611U_0402_6.3V6K
611U_0402_6.3V6K
581U_0402_6.3V6K
581U_0402_6.3V6K
591U_0402_6.3V6K
591U_0402_6.3V6K
621U_0402_6.3V6K
621U_0402_6.3V6K
C
C
C
C
C
C
C
C C
C
2
C
C
C
C
C
C
C
C
C
C
2
2
2
2
1
1
691U_0402_6.3V6K
691U_0402_6.3V6K
701U_0402_6.3V6K
701U_0402_6.3V6K
C
C
C C
C
CC
C
2
2
2
2 1
12
R
R
C1
23
23
C1
120_0402_5%
120_0402_5%
r
oute to 20mil
1
@
@
J
J
CM
CM
OS
OS
2
4
1.5A
631U_0402_6.3V6K
631U_0402_6.3V6K C
C C
C
1
2
1
641U_0402_6.3V6K
641U_0402_6.3V6K C
C C
C
2
22
22
C1
C1
R
R
1 2
10K_0402_5%
10K_0402_5%
+
.8VALW_APU
1
+
3VALW_APU
+
0
.95VALW_APU_USB3
+
0
.95VALW_APU
+
+
C_APU_R
RT
RT
0
1A
.
+
1
0.5A
0.2A
1A
0.5A
4.5uA
C_APU
+
.5VS
3A
1
3
C1
C1
F
F
U
U
J
5
3
V
DIO_MEM_S_1
.5V
D
L
2
3
V
DIO_MEM_S_2
D
L
7
3
DIO_MEM_S_3
VD
N
5
3
V
DIO_MEM_S_4
D
R
1
3
V
DIO_MEM_S_5
D
7
R3
V
DIO_MEM_S_6
D
U
2
3
V
DIO_MEM_S_7
D
5
U3
DIO_MEM_S_8
VD
1
W3
DIO_MEM_S_9
VD
W
2
3
V
DDIO_MEM_S_10
W
7
3
DIO_MEM_S_11
VD
A
31
A
DIO_MEM_S_12
VD
A
A
35
V
DIO_MEM_S_13
D
A
32
C
V
DIO_MEM_S_14
D
AC
37
VD
DIO_MEM_S_15
AE
31
VD
DIO_MEM_S_16
AE
35
VD
DIO_MEM_S_17
AG
32
VD
DIO_MEM_S_18
AG
37
VD
DIO_MEM_S_19
AJ
35
VD
DIO_MEM_S_20
AL
32
VD
DIO_MEM_S_21
AL
37
VD
DIO_MEM_S_22
AR
35
VD
DIO_MEM_S_23
AL
10
VD
DIO_AZ_ALW_1
AL
11
VD
DIO_AZ_ALW_2
B1
VD
D_18_ALW_1
B2
VD
D_18_ALW_2
AL
13
D_33_ALW_1
VD
13
AM
D_33_ALW_2
VD
5
AR
D_095_USB3_DUAL_1
VD
4
AU
D_095_USB3_DUAL_2
VD
V
7
A
D
D_095_USB3_DUAL_3
V
W
5
A
D
D_095_USB3_DUAL_4
V
E
11
A
D
D_095_ALW_1
V
13
E
A
D_095_ALW_2
D
V
11
J
A
D_095_ALW_3
D
V
13
J
A
D_095_ALW_4
D
V
N
4
A
D
DBT_RTC_G
V
FT3_BGA769 @
FT3_BGA769 @
T
T
F
F
POWER
POWER
3 REV 0.51
3 REV 0.51
V
DCR_CPU_1
D
V
DCR_CPU_2
D
V
DCR_CPU_3
D
V
DCR_CPU_4
D
V
D
DCR_CPU_5
V
D
DCR_CPU_6
V
D
DCR_CPU_7
V
D
DCR_CPU_8
V
DCR_CPU_9
D
V
DCR_CPU_10
D
V
DCR_CPU_11
D
V
DCR_CPU_12
D
V
D
DCR_CPU_13
V
D
DCR_CPU_14
V
DCR_CPU_15
D
V
DCR_CPU_16
D
V
DCR_CPU_17
D
V
DCR_CPU_18
D
V
D
DCR_CPU_19
V
D
DCR_CPU_20
V
D
DCR_CPU_21
V
D
DCR_CPU_22
V
D
DCR_CPU_23
V
D
DCR_CPU_24
V
D
DCR_CPU_25
V
D
DCR_CPU_26
V
DCR_NB_1
D
V
DCR_NB_2
D
V
DCR_NB_3
D
V
DCR_NB_4
D
V
DCR_NB_5
D
V
DCR_NB_6
D
V
DCR_NB_7
D
V
DCR_NB_8
D
V
DCR_NB_9
D
V
DCR_NB_10
D
V
D
DCR_NB_11
V
D
DCR_NB_12
V
D
DCR_NB_13
V
D
DCR_NB_14
V
DCR_NB_15
D
V
D
DCR_NB_16
V
DCR_NB_17
D
V
DCR_NB_18
D
V
D
DCR_NB_19
V
D
DCR_NB_20
V
DDCR_NB_21
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
D_095_GFX_1
D
V
D
D_095_GFX_2
V
D
D_095_GFX_3
D
D
D
D
D
D
D
D_095_1
D
D_095_2
D_095_3
D
D_095_4
D
D_095_5
D
D_095_6
D
D_095_7
D
D
D_095_8
D_095_9
D
D_18_1
D_18_2
D_18_3
D_18_4
D_33_1
D_33_2
15A/21A
L
1
2
+
PU_CORE
3 5 7 9 1 3 7 1 3 7 1 3 7
1
2
3
2
7
2
21 23 27 21 23 27 21 23 27
3 7 1 3 7 1 3 7 3 7
1
3 7
1
13 17
17 15 17 19 17 21
15 17
23
27 21 27 21 23 27
23
25
0
1
0
10
A
13A/17A
+
A
PU_CORE_NB
1.5A
+
1.8VS
0.2A
+
3
VS_APU
5A
+
.95VS_APU
0
0.6A
+
.95VS_APU_GFX
0
L
2
L
2
L
2
L
2
N
2
N
2
N
2
R
2
R
2
R
2
U
2
U
2
U
2 W W W A
A A
A A
A A
C A
C A
C A
E A
E A
E
L
1 L
1 N
1 N
1 N
1 R
1 R
1 R
1 U
1 U
1 W W A
A A
A A
C13 A
C A
E A
E A
E A
G A
G
A
2 A
3 B
3 C
3
A
M A
M
A
G A
G A
J A
J A
L A
L A
L A
M A
M
U
1 W A
A
2
U
U
C1G
C1G
8
A
S
S_1
V
3
1
A
S_2
S
V
3
2
A
S_3
S
V
1
3
A
S_4
S
V
3
5
A
S
S_5
V
3
9
A
S
S_6
V
8
B
S_7
S
V
3
1
B
S_8
S
V
3
2
B
S
S_9
V
3
1
B
S
S_10
V
3
9
B
S
S_11
V
1
C
S_12
S
V
2
C
S_13
S
V
5
C
S_14
S
V
7
C
S_15
S
V
9
C
S
S_16
V
1
1
C
S
S_17
V
1
3
C
S_18
S
V
5
1
C
S_19
S
V
1
7
C
S
S_20
V
1
9
C
S
S_21
V
2
1
C
S
S_22
V
3
2
C
S_23
S
V
5
2
C
S
S_24
V
2
7
C
S
S_25
V
9
2
C
S_26
S
V
1
3
C
S_27
S
V
3
3
C
S
S_28
V
3
5
C
S
S_29
V
7
3
C
S_30
S
V
9
3
C
S_31
S
V
4
1
C
S
S_32
V
9
D
S
S_33
V
1
1
D
S_34
S
V
1
3
D
S
S_35
V
3
E
S
S_36
V
4
E
S_37
S
V
9
E
S
S_38
V
1
1
E
S
S_39
V
3
1
E
S_40
S
V
7
2
E
S_41
S
V
3
1
E
S
S_42
V
E
3
5
V
S
S_43
E
3
8
V
S_44
S
E
9
3
V
S_45
S
G
3
V
S_46
S
G
7
V
S_47
S
G
1
1
V
S
S_48
G
1
3
V
S
S_49
G
1
5
V
S
S_50
G
7
1
V
S_51
S
G
1
2
V
S_52
S
G
5
2
V
S_53
S
G
29
V
SS_54
G
5
3
V
S_55
S
G
3
7
V
S
S_56
G
3
9
V
S
S_57
G
4
1
V
S
S_58
H
1
1
V
S_59
S
H
3
1
V
S_60
S
H
3
2
V
S_61
S
H
1
3
V
S_62
S
FT3_BGA769 @
FT3_BGA769 @
F
F
0.95VALW & 0.95VS OF APU
+
.95VALW
0
1 2
@
@
C1
C1
19 0_0603_5%
19 0_0603_5%
R
R
S
S
S
e
e
curity Classification
curity Classification
curity Classification
e
I
I
I
ssu
ssued Date
ed Date
ed Date
ssu
T
T
T
H
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+
.95VALW_APU_USB3
0
1A
+
.95VALW
0
1
@
@
20 0_0603_5%
20 0_0603_5%
C1
C1
R
1
801U_0402_6.3V6K
801U_0402_6.3V6K C
C C
C
2
C
C
C
o
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
R
D
D
D
e
eciphered Date
ciphered Date
ciphered Date
e
1
1
1
781U_0402_6.3V6K
781U_0402_6.3V6K
7710U_0603_6.3V6M
7710U_0603_6.3V6M C
C C
C
791U_0402_6.3V6K
791U_0402_6.3V6K
C
C
C
C
C
C
C
C
2
2
2
2
2
2
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
+
.95VALW_APU
0
2
0.5A
1
1
831U_0402_6.3V6K
831U_0402_6.3V6K
821U_0402_6.3V6K
821U_0402_6.3V6K
C
C
C
C
C
C
C
C
2
2
2
1
1
841U_0402_6.3V6K
851U_0402_6.3V6K
851U_0402_6.3V6K
841U_0402_6.3V6K C
C
C
C
C
C
C
C
2
2
T
3 REV 0.51
3 REV 0.51
T
+
1
U
U
C1H
GND
GND
J3
S_63
VS
J7
S_64
S
V
J8
S_65
VS
9
J3
S_66
VS
1
1
K
S_67
VS
3
K1
S
S_68
V
1
7
K
S
S_69
V
1
9
K
S
S_70
V
2
1
K
S
S_71
V
2
3
K
S
S_72
V
5
2
K
S_73
S
V
7
2
K
S_74
S
V
9
2
K
S_75
S
V
3
1
K
S
S_76
V
3
L
S_77
S
V
7
L
S_78
S
V
8
L
S_79
S
V
0
1
L
S_80
S
V
1
1
L
S
S_81
V
1
5
L
S
S_82
V
1
9
L
S
S_83
V
3
1
L
S
S_84
V
9
3
L
S_85
S
V
1
4
L
S_86
S
V
1
M
S_87
S
V
2
M
S
S_88
V
3
N
S
S_89
V
7
N
S
S_90
V
5
1
N
S_91
S
V
9
1
N
S_92
S
V
5
2
N
S_93
S
V
2
9
N
S
S_94
V
3
1
N
S
S_95
V
3
9
N
S_96
S
V
1
P
S_97
S
V
2
P
S
S_98
V
3
R
S
S_99
V
7
R
S
S_100
V
5
1
R
S_101
S
V
9
1
R
S_102
S
V
2
5
R
S
S_103
V
2
9
R
S
S_104
V
9
3
R
S_105
S
V
1
4
R
S_106
S
V
1
U
S_107
S
V
2
U
S
S_108
V
3
U
S
S_109
V
7
U
S_110
S
V
8
U
S_111
S
V
1
1
U
S
S_112
V
1
5
U
S
S_113
V
9
1
U
S_114
S
V
5
2
U
S_115
S
V
2
9
U
S
S_116
V
3
1
U
S_117
S
V
9
3
U
S_118
S
V
3
W
S_119
S
V
5
W
S
S_120
V
1
1
W
S
S_121
V
5
1
W
S_122
S
V
1
9
W
S
S_123
V
2
5
W
S
S_124
V
AMD CKL v1.01
VDD_095_USB3_DUAL VDD_095 VDD_095_ALW VDD_095_GFX
0
.95VS
2
P
P
J2
J2
2
P_43X79
P_43X79
JUM
JUM
@
@
1
1
5A
1
1
8610U_0603_6.3V6M
8610U_0603_6.3V6M C
C C
C
1
881U_0402_6.3V6K
881U_0402_6.3V6K
8710U_0603_6.3V6M
8710U_0603_6.3V6M
C
C
C
C C
C
C
C
2
2
2
T
T
i
Title
tle
tle
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
1
1
911U_0402_6.3V6K
911U_0402_6.3V6K
891U_0402_6.3V6K
891U_0402_6.3V6K
901U_0402_6.3V6K
901U_0402_6.3V6K
C
C
C
C
C
C
C
C
C
C
C
C
2
2
F
F
F
T
T
T
h
hursday, May 16, 2013
ursday, May 16, 2013
ursday, May 16, 2013
h
+
0
.95VS_APU
1
1
921U_0402_6.3V6K
921U_0402_6.3V6K C
C C
C
2
2
T
3 PWR/GND
3 PWR/GND
3 PWR/GND
T
T
L
L
L
C1H
9
2
W
S
V
9
3
W
S
V
1
4
W
S
V
1
Y
S
V
2
Y
S
V
3
A
A
S
V
7
A
A
S
V
A
8
A
S
V
A
11
A
S
V
15
A
A
S
V
19
A
A
S
V
A
25
A
S
V
A
29
A
S
V
A
39
A
S
V
C
3
A
S
V
7
C
A
S
V
11
C
A
S
V
C
15
A
S
V
C
19
A
S
V
25
C
A
S
V
C
29
A
S
V
C
31
A
S
V
C
39
A
S
V
41
C
A
S
V
E
3
A
S
V
E
7
A
S
V
A
E
25
V
S
A
E
29
V
S
A
32
E
V
S
A
39
E
V
S
A
G
3
V
S
A
G
5
V
S
A
G
10
V
S
A
11
G
V
S
A
13
G
V
S
A
15
G
V
S
A
G
19
V
S
A
G
25
V
S
A
G
29
V
S
A
G
31
V
S
A
39
G
V
S
A
41
G
V
S
A
1
H
V
S
A
H
2
V
S
A
J
3
V
S
A
J
7
V
S
A
15
J
V
S
A
17
J
V
S
A
19
J
V
S
A
23
J
V
S
A
25
J
V
S
A
J
29
V
S
A
J
31
V
S
A
J
32
V
S
A
J
39
V
S
A
3
L
V
S
A
L
8
V
S
A
15
L
V
S
A
17
L
V
S
A
19
L
V
S
A
25
L
V
S
A
29
L
V
S
FT3_BGA769
FT3_BGA769
10uF 1uF 180pF
2 3 1 2 5 1
1 1
A
A
-9868P
-9868P
-9868P
A
S_125
S_126
S_127
S_128
S_129
S_130
S_131
S_132
S_133
S_134
S_135
S_136
S_137
S_138
S_139
S_140
S_141
S_142
S_143
S_144
S_145
S_146
S_147
S_148
S_149
S_150
S_151
S_152
S_153
S_154
S_155
S_156
S_157
S_158
S_159
S_160
S_161
S_162
S_163
S_164
S_165
S_166
S_167
S_168
S_169
S_170
S_171
S_172
S_173
S_174
S_175
S_176
S_177
S_178
S_179
S_180
S_181
S_182
S_183
S_184
S_185
S_186
F
F
T
T
3 REV 0.51
3 REV 0.51
4
FB
FB
MA-L11-201209-300LMA30T
MA-L11-201209-300LMA30T
1
GND
GND
S_187
VS
S_188
S
V
S
S_189
V
S
S_190
V
S
S_191
V
S
S_192
V
S_193
S
V
S_194
S
V
S_195
S
V
S_196
S
V
S
S_197
V
S
S_198
V
S
S_199
V
S
S_200
V
S
S_201
V
S
S_202
V
S_203
S
V
S_204
S
V
S_205
S
V
S
S_206
V
S
S_207
V
S
S_208
V
S_209
S
V
S_210
S
V
S
S_211
V
S
S_212
V
S_213
S
V
S_214
S
V
S_215
S
V
S
S_216
V
S
S_217
V
S
S_218
V
S_219
S
V
S_220
S
V
S
S_221
V
S
S_222
V
S_223
S
V
S_224
S
V
S
S_225
V
S
S_226
V
S_227
S
V
S_228
S
V
S
S_229
V
S
S_230
V
S_231
S
V
S_232
S
V
S
S_233
V
S
S_234
V
S_235
S
V
S_236
S
V
S
S_237
V
S
S_238
V
S_239
S
V
S
S_240
V
S
S_241
V
S_242
S
V
SBG_DAC
S
V
B
V
P
@
@
LC1
LC1
1 2
9
9
9
39
AL
41
AL
M
11
A
M
27
A
M
31
A
N
3
A
7
N
A
39
N
A
31
P
A
3
R
A
R
13
A
R
17
A
R
21
A
R
25
A
R
29
A
R
39
A
R
41
A
1
U
A
2
U
A
U
3
A
U
15
A
U
19
A
23
U
A
27
U
A
U
39
A
V
9
A
W
3
A
7
W
A
13
W
A
W
15
A
W
17
A
W
19
A
21
W
A
23
W
A
W
25
A
W
27
A
31
W
A
33
W
A
W
35
A
W
37
A
39
W
A
41
W
A
Y
13
A
Y
15
A
18
Y
A
30
Y
A
2
A
B
A
7
B
13
A
B
15
A
B
A
18
B
A
21
B
25
A
B
A
31
B
A
35
B
A
39
B
5
1
A
L
31
A
URN
M
29
A
S
EN
+
0
.95VS_APU_GFX
0.6A
o
o
o
f
f
f
1
1
9510U_0603_6.3V6M
9510U_0603_6.3V6M
961U_0402_6.3V6K
961U_0402_6.3V6K
C
C
C
C
C
C
C
C
2
2
1
1
1
.0
.0
.0
4
4
2
2
2
4
Page 10
CyberForum.ru
5
REF_DQA
+V
D
DR_
DDR_
D
DR_
D
DR_AB_D2
D
DR_
D
DR_
D
D D
D
DR_
A_CKE0<5>
AB_BS2<11,5>
DR_
C C
B B
A A
+
D
A_CLK0<5>
DR_
D
DR_
A_CLK0#<5>
D
AB_BS0<11,5>
DR_
D
DR_
AB_WE#<11,5>
D
AB_CAS#<11,5>
DR_
D
DR_
A_SCS1#<5>
D
VS
3
DR_
D
DR_
D
DR_AB_DQS1
D
DR_
D
DR_
D
DR_AB_D16
D
DR_
D
DR_
D
DR_
D
DR_AB_D18
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_AB_D50
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_AB_D59
2
20
20 D
D C
C
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
5
AB_D0 AB_D1
AB_DM0
AB_D3
AB_D8 AB_D9
AB_DQS#1
AB_D10 AB_D11
AB_D17
AB_DQS#2 AB_DQS2
AB_D19
AB_D24 AB_D25
AB_DM3
AB_D26 AB_D27
A_CKE0
AB_BS2
AB_MA12 AB_MA9
AB_MA8 AB_MA5
AB_MA3 AB_MA1
A_CLK0 A_CLK0#
AB_MA10 AB_BS0
AB_WE# AB_CAS#
AB_MA13 A_SCS1#
AB_D32 AB_D33
AB_DQS#4 AB_DQS4
AB_D34 AB_D35
AB_D40 AB_D41
AB_DM5
AB_D42 AB_D43
AB_D48 AB_D49
AB_DQS#6 AB_DQS6
AB_D51
AB_D56 AB_D57
AB_DM7
AB_D58
+1
.5V
JDDR3
JDDR3
L
L
1
R
EF_DQ
V
3
S
S
V
5
Q
0
D
7
Q
1
D
9
VS
S
11
DM
0
13
VS
S
15
DQ
2
17
DQ
3
19
VS
S
21
DQ
8
23
DQ
9
25
VS
S
27
DQ
S1#
29
DQ
S1
31
V
S
S
33
D
10
Q
35
DQ
11
37
VS
S
39
DQ
16
41
D
Q
17
43
V
S
S
45
D
Q
S2#
47
D
Q
S2
49
V
S
S
51
D
18
Q
53
D
19
Q
55
V
S
S
57
D
24
Q
59
D
25
Q
61
V
S
S
63
D
M
3
65
V
S
S
67
D
Q
26
69
D
27
Q
71
V
S
S
73
C
E0
K
75
V
D
D
7
7
N
C
79
B
2
A
81
V
D
D
83
A
2/BC#
1
5
8
A
9
87
V
D
D
8
9
A
8
1
9
A
5
93
V
D
D
5
9
A
3
9
7
A
1
99
V
D
D
101
C
K
0
103
C
0#
K
105
V
D
D
107
A
0/AP
1
109
B
A
0
111
V
D
D
113
W
E
#
115
C
S#
A
117
V
D
D
119
A
1
3
121
S
1
#
123
V
D
D
125
T
ST
E
127
V
S
S
129
D
Q
32
131
D
Q
33
133
V
S
S
135
D
S4#
Q
137
D
Q
S4
139
V
S
S
141
D
34
Q
143
D
35
Q
145
V
S
S
147
D
40
Q
149
D
41
Q
151
V
S
S
153
D
M
5
155
V
S
S
157
D
42
Q
159
D
Q
43
161
V
S
S
163
D
48
Q
165
D
Q
49
167
V
S
S
169
D
S6#
Q
171
D
S6
Q
173
V
S
S
175
D
50
Q
177
D
51
Q
179
V
S
S
181
D
56
Q
183
D
57
Q
185
V
S
S
187
D
7
M
189
V
S
S
191
D
58
Q
193
D
59
Q
195
V
S
S
197
S
0
A
199
V
DSPD
D
201
1
A
S
203
0
.75VS
+
T
T
V
205
D1
N
G
207
O
SS1
B
LCN_DAN06-K4406-0103
LCN_DAN06-K4406-0103
@
@
V
R
R
E
VS DQ DQ VS
D
Q D
Q V D D
V D D
V
D
E
SET#
V D D
V D D
V
D
V D D
V D D
V
D
Q D
Q
V D D
V
C
V
V
V
V
V
C
C
V
B
R
A
V
O
D
V O
D
V
EF_CA
V
Q
D
Q
D
V
D
V
Q
D
Q
D
V
Q
D
Q
D
V Q
D
Q
D
V
Q
D
Q
D
V
Q
D
Q
D
V
D
V
Q
D
Q
D
V
Q
D
Q
D
V Q
D
Q
D
V
Q
D
Q
D
V
V
ENT#
S
S V
N
G
SS2
O
B
S0#
Q Q
M
S Q Q
S Q Q
S
M
S Q Q
S Q Q
S S3#
S Q Q
S
K
D A A
D A
D
D
D
K
D
D S
D
N
D
S
S M S
S
S
S5#
S
S
S M S
S
S
S7#
S
S
D C
D2
4
+1
.5V
2
S
4
D
AB_D4
4 5 S
S0
S
S
6
Q
7
Q
S
S 12 13
S
S
1
S 14 15
S 20 21
S
2
S 22 23
S 28 29
S
S3
S 30 31
S
E1
D 1
5
4
1
D
1
1 A
7
D A
6 A
4
D A
2 A
0
D
1
K 1#
D
1
A S#
D
#
0 T0
D T1
C
D
S 36 37
S
4
S 38 39
S 44 45
S
S5
S 46 47
S 52 53
S
6
S 54 55
S 60 61
S
S7
S 62 63
S
A
L
T
T
DR_
6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
74 76 78 80 82 84 8
6
88
0
9 9
2
94
6
9 9
8 100 102 104 106 108 110 112 114 116 118 120 1
22 124 126
128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
206 208
D
D
D
D
4
DDR_
DR_ D
DR_
D
DR_
D
DR_AB_D7
D
DR_
D
DR_
D
DR_
M
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
DR_ D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
D
DR_AB_MA6
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
D
DR_
D
DR_
D
DR_A_ODT1
+
V
D
DR_AB_D36
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_AB_D45
DR_ D
DR_
D
DR_
D
DR_
D
DR_AB_D52
D
DR_
D
DR_AB_DM6
D
DR_
D
DR_
D
DR_
D
DR_
DR_ D
DR_
D
DR_
D
DR_
M A
P
A
P
0
+
AB_D5
AB_DQS#0
AB_DQS0
AB_D6
AB_D12 AB_D13
AB_DM1
EM_MAB_RST#
AB_D14 AB_D15
AB_D20 AB_D21
AB_DM2
AB_D22 AB_D23
AB_D28 AB_D29
AB_DQS#3
AB_DQS3
AB_D30 AB_D31
A_CKE1
AB_MA15 AB_MA14
AB_MA11 AB_MA7
DR_
AB_MA4
AB_MA2 AB_MA0
A_CLK1 A_CLK1#
AB_BS1 AB_RAS#
DR_
A_SCS0# A_ODT0
REF_CAA
AB_D37
AB_DM4
AB_D38 AB_D39
AB_D44
AB_DQS#5
AB_DQS5
AB_D46 AB_D47
AB_D53
AB_D54 AB_D55
AB_D60 AB_D61
AB_DQS#7
AB_DQS7
AB_D62 AB_D63
M_MAB_EVENT#
E
U_SDATA0 U_SCLK0
.75VS
DDR3 SO-DIMM A
verse Type
Re
M_MAB_RST# <11,5>
E
M
D
DR_
A_CKE1 <5>
A_CLK1 <5>
DR_
D
A_CLK1# <5>
DR_
D
DR_
AB_BS1 <11,5>
D
AB_RAS# <11,5>
DR_
D
A_SCS0# <5>
DR_
D
DR_
A_ODT0 <5>
D
DR_
A_ODT1 <5>
D
M_MAB_EVENT# <11,5>
E
M
U_SDATA0 <11,23,8>
P
A
U_SCLK0 <11,23,8>
P
A
e
curity Classification
curity Classification
curity Classification
e
e
S
S
S
I
I
I
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
H
T
T
T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ssu
ssu
ssu
ed Date
ed Date
ed Date
3
S
O-DIMM VREF
AB_DQS[0..7] <11,5>
DR_
D
DR_
AB_DQS#[0..7] <11,5>
D
AB_D[0..63] <11,5>
DR_
D
AB_DM[0..7] <11,5>
DR_
D
DR_
AB_MA[0..15] <11,5>
D
L
a
L
a
yout Note:
Place near JDDR3L
.5V
1
+
D4
D4
3
3
C
C
D1
D1
C
C
D1
D1
C
C
D1
D1
C
C
D1
D1
C
C
D1
D1
C
C
D1
D1
C
C
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
2
2
2
3
47U_0805_6.3V6M
47U_0805_6.3V6M
2
1
1 2
0 10U_0603_6.3V6M
0 10U_0603_6.3V6M
1 2
1 10U_0603_6.3V6M
1 10U_0603_6.3V6M
2
1
3 10U_0603_6.3V6M
3 10U_0603_6.3V6M
2
1
4 10U_0603_6.3V6M
4 10U_0603_6.3V6M
1 2
6 10U_0603_6.3V6M
6 10U_0603_6.3V6M
1 2
8 10U_0603_6.3V6M
8 10U_0603_6.3V6M
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
o
C
C
C
yout Note: Place these 4 Caps near
Command and Control signals of DIMMA
e
e
ciphered Date
ciphered Date
ciphered Date
e
D
D
D
+
.5V
1
+
2
1
.5V
+
12
D1
D1
R
R
1
1
K_0402_1%
K_0402_1%
+
V
REF_DQA
1
D1
D1
C
C
1U_0402_16V7K
1U_0402_16V7K
.
. 0
0
2
.1U_0402_16V4Z
.1U_0402_16V4Z
.1U_0402_16V4Z
.1U_0402_16V4Z
2
.1U_0402_16V4Z
.1U_0402_16V4Z
.1U_0402_16V4Z
.1U_0402_16V4Z
1
@
@
D2
D2
C
C
2
2 .
.
2U_0402_6.3V6M
2U_0402_6.3V6M
2
D3
D3
R
R
K_0402_1%
K_0402_1%
1
1
2
i
tle
tle
tle
i
i
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
2
1
C
ose to JDDR3L.1 Close to JDDR3L.126
l
1
D5 0
D5 0
C
C
1 2
D6 0
D6 0
C
C
1
D7 0
D7 0
C
C
1 2
D8 0
D8 0
C
C
2
V
REF_CAA
Layout Note: Place near JDDR3L.203 and 204
0
.75VS
+
D9 1
D9 1
C
C
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
D1
D1
C
C
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
C
C
C
D
D
D
D
D
D
A
-9868P
-9868P
-9868P
A
A
L
L
L
1
D3
D3
C
C
1U_0402_16V7K
1U_0402_16V7K
.
. 0
0
U_0402_6.3V6K
U_0402_6.3V6K
1
1
@
@
D4
D4
C
C
2
2 .
.
2U_0402_6.3V6M
2U_0402_6.3V6M
2
2
1
12
12
RIII-SODIMMA
RIII-SODIMMA
RIII-SODIMMA
1
.5V
+
12
D2
D2
R
R
1K_0402_1%
1K_0402_1%
12
D4
D4
R
R
1
1
K_0402_1%
K_0402_1%
0 4
0 4
0 4
1
1
o
o
1
o
.0
.0
.0
1
1
1
f
2Thursday, May 16, 2013
2Thursday, May 16, 2013
2Thursday, May 16, 2013
f
f
Page 11
CyberForum.ru
5
.5V
+1
+V
REF_DQB
D
DR_
AB_D0
D
AB_D1
DR_
D
DR_AB_DM0
D
DR_
AB_D2
D
DR_AB_D3
D
DR_
D D
D
B_CKE0<5>
C C
B B
A A
+
DR_
DR_
AB_BS2<10,5>
D
DR_
B_CLK0<5>
D
DR_
B_CLK0#<5>
D
DR_
AB_BS0<10,5>
D
AB_WE#<10,5>
DR_
D DR_
AB_CAS#<10,5>
D
B_SCS1#<5>
DR_
D
1 2
D9
D9
R
3
VS
R
5
D
D D
D D
D D
D D
D D
D D
D
D D
D
D
D D
D D
D D
D D
D D
D D
D D
D D
D D
D D
D D
D
D D
D D
D D
D D
D D
D
D D
10K_0402_5%
10K_0402_5%
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AB_D8 AB_D9
DR_
AB_DQS#1
DR_ DR_
AB_DQS1
DR_AB_D10
AB_D11
DR_
DR_
AB_D16
DR_AB_D17
DR_
AB_DQS#2
DR_
AB_DQS2
DR_
AB_D18
DR_
AB_D19
AB_D24
DR_
AB_D25
DR_
AB_DM3
DR_
DR_AB_D26 DR_
AB_D27
DR_B_CKE0
AB_BS2
DR_
DR_
AB_MA12 AB_MA9
DR_
AB_MA8
DR_
AB_MA5
DR_
DR_
AB_MA3 AB_MA1
DR_
B_CLK0
DR_ DR_
B_CLK0#
DR_AB_MA10
AB_BS0
DR_
DR_
AB_WE#
DR_
AB_CAS#
AB_MA13
DR_
B_SCS1#
DR_
DR_AB_D32
AB_D33
DR_
AB_DQS#4
DR_
AB_DQS4
DR_
DR_AB_D34 DR_
AB_D35
DR_
AB_D40
DR_
AB_D41
AB_DM5
DR_
AB_D42
DR_
AB_D43
DR_
DR_AB_D48 DR_AB_D49
AB_DQS#6
DR_ DR_AB_DQS6
DR_
AB_D50 AB_D51
DR_
DR_
AB_D56
DR_
AB_D57
DR_
AB_DM7
AB_D58
DR_ DR_
AB_D59
40
40 D
D C
C
.75VS
0
+
DDR3
DDR3
H
H
J
J
1
R
EF_DQ
V
3
S
S
V
5
DQ
0
7
DQ
1
9
VS
S
11
DM
0
13
VS
S
15
DQ
2
17
DQ
3
19
VS
S
21
DQ
8
23
DQ
9
25
VS
S
27
DQ
S1#
29
DQ
S1
31
S
VS
33
10
DQ
35
11
DQ
37
S
VS
39
16
DQ
41
D
17
Q
43
V
S
S
45
D
S2#
Q
47
D
S2
Q
49
V
S
S
51
D
Q
18
53
D
Q
19
55
V
S
S
57
D
Q
24
59
D
Q
25
61
V
S
S
63
D
3
M
65
V
S
S
67
D
26
Q
69
D
Q
27
71
V
S
S
73
C
K
E0
75
V
D
D
7
7
N
C
79
B
2
A
81
V
D
D
83
A
2/BC#
1
8
5
A
9
87
V
D
D
8
9
A
8
9
1
A
5
93
V
D
D
5
9
A
3
7
9
A
1
99
V
D
D
101
C
K
0
103
C
0#
K
105
V
D
D
107
A
0/AP
1
109
B
0
A
111
V
D
D
113
W
E
#
115
C
S#
A
117
V
D
D
119
A
3
1
121
S
1
#
123
V
D
D
125
T
ST
E
127
V
S
S
129
D
Q
32
131
D
Q
33
133
V
S
S
135
D
S4#
Q
137
D
S4
Q
139
V
S
S
141
D
Q
34
143
D
35
Q
145
V
S
S
147
D
Q
40
149
D
Q
41
151
V
S
S
153
D
5
M
155
V
S
S
157
D
42
Q
159
D
43
Q
161
V
S
S
163
D
Q
48
165
D
49
Q
167
V
S
S
169
D
Q
S6#
171
D
Q
S6
173
V
S
S
175
D
Q
50
177
D
Q
51
179
V
S
S
181
D
Q
56
183
D
Q
57
185
V
S
S
187
D
7
M
189
V
S
S
191
D
Q
58
193
D
59
Q
195
V
S
S
197
S
A
0
199
V
DSPD
D
201
A
1
S
203
T
T
V
205
N
D1
G
207
SS1
O
B
LCN_DAN06-K4806-0103
LCN_DAN06-K4806-0103
@
@
V D DQ VS
D
S0#
Q
D
Q V D D V
D
Q
D
Q
V
D
M
R
SET#
E
VS DQ DQ
VS D
Q
D
Q
V
D
M
V D
Q
D
Q
V D
Q
D
Q
V
D
Q
S3#
D
Q
V D
Q
D
Q
V
C
K
V
D A A
V
D A
V
D
V
D
V
D
C
C
K
V
D B
R
A
V
D S
O
D
V
D
O
D
N
V
D
V
EF_CA
R
V
D
Q
D
Q
V
D
M
V
D
Q
D
Q
V
D
Q
D
Q
V
QS5#
D
Q
D
V
Q
D
Q
D
V
Q
D
Q
D
V
M
D
V
Q
D
Q
D
V
Q
D
Q
D
V
Q
S7#
D
Q
D
V
Q
D
Q
D
V
ENT#
V
E
D
S S
V
N
G O
SS2
B
4
.5V
+1
2
S
S
4
D
Q
4 5
S
S0
S
S
6
Q
7
Q
S
S
12 13
S
S
1
S 14 15
S 20 21
S
S
2
S
S
22 23
S
S 28 29
S
S
S3
S
S
30 31
S
S
E1
D
5
1
4
1
D 1
1
A
7
D
A
6
A
4
D
A
2
A
0
D
1
K
1#
D
1
A S#
D
#
0 T0
D T1
C
D
S
S 36 37
S
S
4
S
S
38 39
S
S 44 45
S
S
S5 S
S 46 47
S
S 52 53
S
S
6
S
S
54 55
S
S
60 61
S
S
S7 S
S 62 63
S
S
A
L
C T
T
D2
DR_AB_D4
6
D
AB_D5
DR_
8 10
D
DR_AB_DQS#0
12
D
DR_AB_DQS0
14 16
D
DR_
D
D D
D M
D D
D D
D
D D
D D
D D
D D
D
D D
D D
D D
D D
D D
D D
D D
D
+
D D
D
D D
D D
D D
D D
D D
D
D D
D D
D D
D D
M A A
0
+
4
AB_D6
DR_
AB_D7
DR_
AB_D12
DR_
AB_D13
AB_DM1
DR_ E
M_MAB_RST#
DR_
AB_D14 AB_D15
DR_
DR_
AB_D20 AB_D21
DR_
DR_
AB_DM2
DR_
AB_D22
DR_
AB_D23
DR_
AB_D28
DR_AB_D29
AB_DQS#3
DR_
AB_DQS3
DR_
AB_D30
DR_ DR_
AB_D31
DR_B_CKE1
DR_
AB_MA15
DR_
AB_MA14
AB_MA11
DR_ DR_AB_MA7
DR_
AB_MA6
DR_
AB_MA4
AB_MA2
DR_
AB_MA0
DR_
B_CLK1
DR_ DR_
B_CLK1#
DR_
AB_BS1 AB_RAS#
DR_
DR_
B_SCS0# B_ODT0
DR_
DR_
B_ODT1
V
REF_CAB
DR_
AB_D36 AB_D37
DR_
AB_DM4
DR_
DR_
AB_D38 AB_D39
DR_
AB_D44
DR_ DR_
AB_D45
AB_DQS#5
DR_ DR_
AB_DQS5
DR_
AB_D46
DR_
AB_D47
DR_
AB_D52 AB_D53
DR_
DR_
AB_DM6
AB_D54
DR_
AB_D55
DR_
AB_D60
DR_ DR_
AB_D61
DR_
AB_DQS#7
DR_
AB_DQS7
AB_D62
DR_
AB_D63
DR_
E
M_MAB_EVENT#
U_SDATA0
P
U_SCLK0
P
.75VS
18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
74 76 78 80 82 84
6
8 88 9
0 2
9 94 9
6 8
9 100 102 104 106 108 110 112 114 116 118 120 1
22 124 126 128 130 132 134 136 138 140 142 144 146 148 150
152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
206 208
DDR3 SO-DIMM B
verse Type
Re
E
M_MAB_RST# <10,5>
M
D
B_CKE1 <5>
DR_
DR_
B_CLK1 <5>
D
DR_
B_CLK1# <5>
D
AB_BS1 <10,5>
DR_
D
DR_
AB_RAS# <10,5>
D
B_SCS0# <5>
DR_
D
B_ODT0 <5>
DR_
D
B_ODT1 <5>
DR_
D
E
M_MAB_EVENT# <10,5>
M
P
U_SDATA0 <10,23,8>
A
P
U_SCLK0 <10,23,8>
A
e
curity Classification
curity Classification
curity Classification
e
e
S
S
S
I
I
I
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
H
T
T
T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ssu
ssu
ssu
ed Date
ed Date
ed Date
3
L
a
yout Note:
Place near JDDR3H
1
.5V
+
1 2
0 10U_0603_6.3V6M
0 10U_0603_6.3V6M
D3
D3
C
C
1
1 10U_0603_6.3V6M
1 10U_0603_6.3V6M
D3
D3
C
C
1
3 10U_0603_6.3V6M
3 10U_0603_6.3V6M
D3
D3
C
C
1
D3
D3
4 10U_0603_6.3V6M
4 10U_0603_6.3V6M
C
C
1 2
D3
6 10U_0603_6.3V6M
6 10U_0603_6.3V6M
D3
C
C
1 2
8 10U_0603_6.3V6M
8 10U_0603_6.3V6M
D3
D3
C
C
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
2
2
2
3
AB_DQS[0..7] <10,5>
DR_
D
DR_
AB_DQS#[0..7] <10,5>
D
AB_D[0..63] <10,5>
DR_
D
DR_
AB_DM[0..7] <10,5>
D
DR_
AB_MA[0..15] <10,5>
D
2
2
2
2
S
O-DIMM VREF
+
V
REF_DQB
C
ose to JDDR3H.1
l
L
a
yout Note: Place these 4 Caps near
Command and Control signals of DIMMB
1
.5V
+
12
D2
D2
5 0.1U_0402_16V4Z
5 0.1U_0402_16V4Z
C
C
12
D2
6 0.1U_0402_16V4Z
6 0.1U_0402_16V4Z
D2
C
C
12
D2
7 0.1U_0402_16V4Z
7 0.1U_0402_16V4Z
D2
C
C
12
D2
8 0.1U_0402_16V4Z
8 0.1U_0402_16V4Z
D2
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
o
C
C
C
e
e
ciphered Date
ciphered Date
ciphered Date
e
D
D
D
2
1
1
.5V
1
2
@
@
D2
D2
C
C
2
2 .
.
2U_0402_6.3V6M
2U_0402_6.3V6M
+
4
4
1 4
1 4
1 4
1
1
1
12
RD8
RD8
K_0402_1%
K_0402_1%
1
1
12
R
R
K_0402_1%
K_0402_1%
1
1
f
f
f
o
o
o
D7
D7
.0
.0
.0
1
1
1
2Thursday, May 16, 2013
2Thursday, May 16, 2013
2Thursday, May 16, 2013
1
.5V
+
12
RD6
RD6
K_0402_1%
K_0402_1%
1
1
+
V
REF_CAB
12
2
1
1
@
D2
D2
C
C
1U_0402_16V7K
1U_0402_16V7K
.
. 0
0
@
D2
D2
1
1
C
C
2
2 .
.
2U_0402_6.3V6M
2U_0402_6.3V6M
2
D5
D5
R
R
2
2
K_0402_1%
K_0402_1%
1
1
Layout Note: Place near JDDRH.203 and 204
.75VS
0
+
12
D2
D2
9 1U_0402_6.3V6K
9 1U_0402_6.3V6K
C
C
12
D3
D3
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
C
C
C
C
i
tle
tle
tle
i
i
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
C
L
L
L
2
3
3
D2
D2
C
C
1
1U_0402_16V7K
1U_0402_16V7K
.
. 0
0
C
lose to JDDR3H.126
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
D
D
RIII-SODIMMB
RIII-SODIMMB
RIII-SODIMMB
D
D
D
D
A
-9868P
-9868P
-9868P
A
A
1
Page 12
CyberForum.ru
A
P
P
IE_ATX_C_GRX_P[3..0]<5>
C
P
IE_ATX_C_GRX_N[3..0]<5>
C
1 1
2 2
3 3
C
LK_PCIE_VGA<7>
C
L
K_PCIE_VGA#<7>
3.3-V tolerant
4 4
P
X
S_RST#<8>
A
P
U_PCIE_RST#<23,25,8>
A
CIE_ATX_C_GRX_P[3..0]
P
C
IE_ATX_C_GRX_N[3..0]
P
C
IE_ATX_C_GRX_P0
P
C
IE_ATX_C_GRX_N0
P
IE_ATX_C_GRX_P1
C
P
CIE_ATX_C_GRX_N1
P
CIE_ATX_C_GRX_P2
P
CIE_ATX_C_GRX_N2
P
CIE_ATX_C_GRX_P3
P
C
IE_ATX_C_GRX_N3
C
K_PCIE_VGA
L
C
K_PCIE_VGA#
L
VGA@
VGA@
R
R
V
V
2 1K_0402_5%
2 1K_0402_5%
G
U_RST#
P
2
1
12
12
VGA@
VGA@
R
R 100K_0402_5%
100K_0402_5%
+
3
B
A
U
U
1A
1A
V
V
A
38
A
PCIE_RX0P
3
7
Y
PCIE_RX0N
Y
3
5
PCIE_RX1P
W
3
6
PCIE_RX1N
W
3
8
PCIE_RX2P
V
3
7
PCIE_RX2N
V
5
3
PCIE_RX3P
U
3
6
PCIE_RX3N
U
8
3
PCIE_RX4P
T
7
3
PCIE_RX4N
T
3
5
PCIE_RX5P
R
6
3
PCIE_RX5N
R
3
8
PCIE_RX6P
P
3
7
PCIE_RX6N
P
5
3
PCIE_RX7P
N
36
PCIE_RX7N
N
8
3
NC
M
7
3
NC
M
3
5
NC
L
3
6
NC
L
8
3
NC
K
7
3
NC
K
5
3
NC
J
3
6
NC
J
38
NC
H
3
7
NC
H
5
3
NC
G
6
3
NC
G
3
8
NC
F
3
7
NC
F
5
3
NC
E
7
3
NC
CLOCK
CLOCK
A
B
35
PCIE_REFCLKP
A
36
A
PCIE_REFCLKN
A
16
H
TEST_PG
A
30
A
PERSTB
V
212
212
V
VS
VGA@
VGA@
5
13
13
V
V
U
U
P
4
Y
G
3
MC74VHC1G08DFT2G SC70 5P
MC74VHC1G08DFT2G SC70 5P
B
P
P
ART 1 0F 9
ART 1 0F 9
CI EXPRESS INTERFACE
CI EXPRESS INTERFACE P
P
SUN-PRO M2_FCBGA962VGA@
SUN-PRO M2_FCBGA962VGA@
G
P
U_RST#
B
PCIE_TX0P PCIE_TX0N
PCIE_TX1P PCIE_TX1N
PCIE_TX2P PCIE_TX2N
PCIE_TX3P PCIE_TX3N
PCIE_TX4P PCIE_TX4N
PCIE_TX5P PCIE_TX5N
PCIE_TX6P PCIE_TX6N
PCIE_TX7P PCIE_TX7N
CALIBRATION
CALIBRATION
PCIE_CALR_TX
PCIE_CALR_RX
C
P
C
IE_GTX_C_ARX_P[3..0]
P
C
IE_GTX_C_ARX_N[3..0]
.1U_0402_16V7K
3
3
Y
P
IE_GTX_ARX_P0
C
3
2
Y
P
IE_GTX_ARX_N0
C
3
3
W
P
IE_GTX_ARX_P1
C
2
3
W
P
IE_GTX_ARX_N1
C
3
3
U
P
IE_GTX_ARX_P2
C
3
2
U
P
IE_GTX_ARX_N2
C
0
3
U
P
C
IE_GTX_ARX_P3
2
9
U
P
C
IE_GTX_ARX_N3
3
3
T
3
2
T
0
3
T
9
2
T
3
3
P
2
3
P
3
0
P
9
2
P
3
3
N
NC
2
3
N
NC
3
0
N
NC
9
2
N
NC
3
3
L
NC
3
2
L
NC
3
0
L
NC
9
2
L
NC
3
3
K
NC
2
3
K
NC
3
3
J
NC
2
3
J
NC
3
0
K
NC
9
2
K
NC
3
3
H
NC
2
3
H
NC
3
0
Y
V
A_PCIE_CALRP
G
9
2
Y
V
GA_PCIE_CALRN
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
A
C Coupling Capa citor PCIeR Gen1 and Gen2 only: Reco mmended value is 100 nF 10%. PCIeR Gen3: Rec ommended value is 220 nF 10%.
1 1.69K_0402_1%VGA@
1 1.69K_0402_1%VGA@
V
V
R
R
R
R
V
V
3 1K_0402_1%VGA@
3 1K_0402_1%VGA@
P
IE_GTX_C_ARX_P[3..0] <5>
C
P
IE_GTX_C_ARX_N[3..0] <5>
C
C
C
1
1
V
V
C
C
V
V
2
2
C
C
3
3
V
V
C
C
4
4
V
V
5
5
V
V
C
C
C
C
6
6
V
V
C
C
V7
V7
8
8
V
V
C
C
1 2
1 2
1 2 1 2
1 1 2
1 2
1
1 2
1 2
P
IE_GTX_C_ARX_P0
VGA@
VGA@ VGA@
VGA@
2
VGA@
VGA@ VGA@
VGA@
VGA@
VGA@
2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
C
P
IE_GTX_C_ARX_N0
C
P
C
IE_GTX_C_ARX_P1
P
C
IE_GTX_C_ARX_N1
P
C
IE_GTX_C_ARX_P2
P
IE_GTX_C_ARX_N2
C
P
C
IE_GTX_C_ARX_P3
P
C
IE_GTX_C_ARX_N3
F
or MEMCLK 1GHz Brand
g
DDR3-2Gbit
+
.95VGS
0
+
.95VGS
0
F
or MEMCLK 900MHz Brand
s
kHynix
S
amsung
s
g
DDR3-2Gbit
M
S
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
s
sued Date
sued Date
sued Date
s
s
T
T
T
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
H
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2
2
2
12/09/27 2015/09/27
012/09/27 2015/09/27
12/09/27 2015/09/27
0
0
C
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
o
D
D
D
e
ciphered Date
ciphered Date
ciphered Date
e
e
D
escription
H
5TQ2G63DFR-N0C
K4W2G1646E-BC1A
kHynix
MT41K128M16JT-1 07G:K
icron
amsung
D
L
DS Interface
V
V
V
1D
1D
U
U
ART 7 0F 9
ART 7 0F 9
P
P
RSVD/VARY_BL
RSVD/DIGON
LVDS CONTROL
LVDS CONTROL
TXCBP_DPB3P TXCBM_DPB3N
TX3P_DPB2P TX3M_DPB2N
TX4P_DPB1P TX4M_DPB1N
TX5P_DPB0P TX5M_DPB0N
NC#AF35
VTMDP
VTMDP L
L
C
omment PS_3[3:1] R_pu(ohm) R_pd(ohm)
1
.5V/1GHz
1.5V/1GHz
D
escription
H
5TQ2G63DFR-11C
K
4W2G1646E-BC11 1.5V/900MHz 111
D
NC#AG36
TXCAP_DPA3P TXCAM_DPA3N
TX0P_DPA2P TX0M_DPA2N
TX1P_DPA1P TX1M_DPA1N
TX2P_DPA0P TX2M_DPA0N
NC NC
SUN-PRO M2_FCBGA962VGA@
SUN-PRO M2_FCBGA962VGA@
000
111
C
omment PS_3[3:1]R_pu(ohm) R_pd(ohm)
1
.5V/900MHz
1.35V/900MHz
1.5V/900MHz
T
T
T
i
tle
tle
tle
i
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
u
u
stom
stom
ustom
Date: S heet
Date: S heet
Date: S heet
E
K
27
A
J2
7
A
35
K
A
36
L
A
8
J3
A
K
37
A
H
35
A
6
J3
A
38
G
A
37
H
A
F
35
A
36
G
A
P
34
A
34
R
A
37
W
A
35
U
A
R
37
A
39
U
A
35
P
A
R
35
A
N
36
A
37
P
A
NC
4750
000
001
NC
8450 2000
4750
C
C
C
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
P
P
P
C
CIE/LVDS
IE/LVDS
IE/LVDS
C
LA-9868P
LA-9868P
LA-9868P
E
4750
NC
4750
NC
1
1
1
.
.
0
0
.0
o
o
o
12 42Thursday, May 16, 2013
f
12 42Thursday, May 16, 2013
12 42Thursday, May 16, 2013
f
f
Page 13
CyberForum.ru
A
+
3
VGS
1 1
R
R
12
12
V
V
8
1
J
2 7 3 6 4
10K_8P4R_5%
10K_8P4R_5%
+
VGS
3
2 2
+
3
3 3
4 4
10K_8P4R_5%
10K_8P4R_5%
CHECK VR IF VR Suport PSI# and DPRSLPVR PU 10K to +3VGS: PSI# :Low load current flag DPRSLPVR : Deeper sleep enable flag
GENERIC_X Stereo-sync signal. Indicates left/right frame, or top/bottom field. Can be left unconnected if not used.
VGS
Enable JTAG access
R
R
7
7
V
V
5.11K_0402_5%
5.11K_0402_5%
@
@
1 2
T
Reserved signal, for normal ASIC operation.
2
R
R
9
9
V
V
1K_0402_5%
1K_0402_5%
VGA@
VGA@
1
T
VDD MarsCRB Design
S
120ohm 1 1
0.1u 1 1 1u 1 1 10u 1 1
TAG_TRSTB J
AG_TDI
T
J
AG_TMS
T
5
J
AG_TCK
T
@
@
R
R
V
V
13
13
1 8
G
IO_16
P
2 7
G
IO_28_FDO
P
6
3
V
A_SMB_CK2
G
4 5
V
A_SMB_DA2
G
VGA@
VGA@
G
U_DPRSLPVR<39>
P
VGA@
VGA@
1 2
R
R
V
11 10K_0402_5%
11 10K_0402_5%
V
G
P
U_DOWN#<29>
G
U_VID5<39>
P
G
P
U_VID1<39>
G
U_VID2<39>
P
C
KREQ_PEG#<8>
L
VGA@
VGA@
R
R
V
V
14 10K_0402_5%
14 10K_0402_5%
2
1
G
U_VID3<39>
P
G
P
U_VID4<39>
PX_EN :
High (3.3 V) switches the regulators
off (enter BACO mode).
Low (0 V) switches the regulators
on. (Default)
E
STEN
G
M
IO_28_FDO
P
D
i
H
E
n
L
+
1
.8VGS
L
L
V
V
3
VGA@
3
VGA@
2
1
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
A
V
A_SMB_CK2
G
V
GA_SMB_DA2
G
U_DPRSLPVR
P
G
U_VID5
P
T
T
1
1
V
V
G
P
U_GPIO8
T
T
V
V
2
2
G
U_GPIO9
P
T
3TV3
V
G
U_GPIO10
P
G
P
U_VID1
G
P
10K_0402_5%@
10K_0402_5%@
R
R
8
8
V
V
2
1
G
P
U_VID2
T
T
4
4
V
V
G
P
U_GPIO21
TV5T
V5
G
P
U_GPIO22
C
KREQ_PEG#
L
G
P
U_VID3
G
U_VID4
P
T
T
V
V
9
9
P
X
J
AG_TRSTB
T
J
AG_TDI
T
J
AG_TCK
T
J
TAG_TMS
T
T
V
7
7
V
J
T
SVDD
1
17
17 V
V C
C
2
VGA@
VGA@
G
P
(
.8V@13mA TSVDD)
1
1
18
18 V
V C
C
2
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
VGA@
VGA@
AG_TDO
IO_28_FDO
+
T
1
19
19 V
V C
C
2
VGA@
VGA@
LPS
sable
able
+
T
U
U
V
V
1B
1B
PART 2 0F 9
PART 2 0F 9
MUTI GFX
MUTI GFX
29
D
A
NLK_CLK
E
G
29
C
A
NLK_VSYNC
E
G
21
AJ
APLOCKA
SW
21
AK
APLOCKB
W
S
R
8
A
C
N
U
8
A
C
N
P
8
A
B
G_CNTL0
D
8
W
A
C
N
3
R
A
C
N
1
R
A
C
N
1
U
A
G_DATA0
B
D
3
U
A
G_DATA1
B
D
W
3
A
B
G_DATA2
D
P
6
A
B
G_DATA3
D
W
5
A
B
G_DATA4
D
U
5
A
B
G_DATA5
D
R
6
A
B
G_DATA6
D
6
W
A
G_DATA7
B
D
6
U
A
B
G_DATA8
D
T
7
A
B
G_DATA9
D
7
V
A
G_DATA10
B
D
7
N
A
G_DATA11
B
D
9
V
A
G_DATA12
B
D
9
T
A
G_DATA13
B
D
10
R
A
G_DATA14
B
D
W
10
A
B
G_DATA15
D
U
10
A
B
G_DATA16
D
P
10
A
B
G_DATA17
D
11
V
A
G_DATA18
B
D
11
T
A
G_DATA19
B
D
12
R
A
G_DATA20
B
D
W
12
A
B
G_DATA21
D
U
12
A
B
G_DATA22
D
P
12
A
B
G_DATA23
D
23
J
A
BCLK
M
S
23
H
A
BDATA
M
S
K
26
A
C
L
S
26
J
A
A
D
S
G
G
ENERAL PURPOSE I/O
ENERAL PURPOSE I/O
H
20
A
P
IO_0
G
H
18
A
P
IO_1
G
16
N
A
IO_2
P
G
17
H
A
IO_5_AC_BATT
P
G
17
J
A
P
IO_6_TACH
G
K
17
A
P
IO_7_BLON
G
J
13
A
P
IO_8_ROMSO
G
H
15
A
IO_9_ROMSI
P
G
16
J
A
IO_10_ROMSCK
P
G
K
16
A
P
IO_11
G
L
16
A
P
IO_12
G
M
16
A
IO_13
P
G
14
M
A
IO_14_HPD2
P
G
13
M
A
IO_15_PWRCNTL_0
P
G
K
14
A
IO_16
_EN
SVDD
P
IO_16
G
G
30
A
P
IO_17_THERMAL_INT
G
N
14
A
P
IO_18_HPD3
G
17
M
A
IO_19_CTF
P
G
13
L
A
IO_20_PWRCNTL_1
P
G
14
J
A
P
IO_21
G
K
13
A
P
IO_22_ROMCSB
G
13
N
A
KREQB
L
C
32
G
A
IO_29
P
G
G
33
A
P
IO_30
G
19
J
A
NERICA
E
G
19
K
A
NERICB
E
G
J
20
A
E
NERICC
G
K
20
A
E
NERICD
G
J
24
A
E
NERICE_HPD4
G
26
H
A
NERICF_HPD5
E
G
H
24
A
E
NERICG_HPD6
G
30
C
A
C_1
E
C
K
24
A
P
D1
H
13
H
A
G_VREFG
B
D
L
21
A
X
_EN
P
28
D
A
STEN
E
T
M
23
A
T
AG_TRSTB
J
23
N
A
AG_TDI
T
J
K
23
A
T
AG_TCK
J
L
24
A
T
AG_TMS
J
M
24
A
T
AG_TDO
J
THERMAL
THERMAL
29
F
A
LUS
P
D
29
G
A
INUS
M
D
K
32
A
P
IO_28_FDO
G
L
31
A
S
_A
T
32
J
A
VDD
S
T
A
33
J
T
VSS
S
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DEBUG
DEBUG
DPA
DPA
DPB
DPB
DPC
DPC
DPD
DPD
S
S
MBus
MBus
I2C
I2C
DAC1
DAC1
ML
ML
P
P
S
S
B
B
ACO
ACO
DDC/
DDC/
A
A
UX
UX
D D
D
SUN-PRO M2_FCBGA962VGA@
SUN-PRO M2_FCBGA962VGA@
A
V V
C
N
C
N
C
N
D
C1CLK
D
D
C1DATA
D
C2CLK
D
D
D
C2DATA
D
CVGACLK
D CVGADATA
B
C
D
E
MLPS
24
AU
NC
23
AV
NC
A
25
T
N
C
A
24
R
N
C
A
26
U
N
C
A
25
V
N
C
27
AT
NC
A
26
R
N
C
30
AR
N
C
A
29
T
N
C
31
AV
N
C
A
30
U
NC
32
AR
N
C
A
31
T
NC
AT
33
N
C
AU
32
C
N
AU
14
NC
13
AV
NC
15
AT
NC
14
AR
NC
16
AU
NC
15
AV
NC
17
AT
NC
16
AR
NC
20
AU
NC
19
AT
NC
T
21
A
C
N
R
20
A
C
N
U
22
A
C
N
V
21
A
C
N
T
23
A
C
N
R
22
A
C
N
39
D
A
R
37
D
A
SSN
V
A
36
E
A
G
35
D
A
SSN
V
A
37
F
A
B
E
38
A
V
SSN
A
C
36
A
S
YNC
H
C
38
A
S
YNC
V
34
B
A
ET
S
R
34
D
A
DD
V
A
34
E
A
SSQ
V
33
C
A
D
D1DI
34
C
A
S1DI
S
1
3
V
C
N
1
3
U
C
N
F
33
A
C
N
F
32
A
C
N
29
A
A
C
N
21
G
A
C
N
32
C
A
C
N
C
31
A
_SVI2
D
30
A
_SVI2
D
32
A
_SVI2
34
M
A
P
S
_0
_0
S
P
D
31
A
P
_1
S
S
_1
P
G
31
A
P
_2
S
S
_2
P
33
D
A
P
_3
S
_3
S
P
M
26
A
N
26
A
27
M
A
X1P
U
A
27
L
A
X1N
U
A
19
M
A
L
19
A
N
20
A
U
X2P
A
M
20
A
U
X2N
A
30
L
A
C
N
30
M
A
C
N
L
29
A
C
N
M
29
A
C
N
21
N
A
C
N
21
M
A
C
N
K
30
A
C
N
K
29
A
C
N
J
30
A
31
J
A
B
M
ars MLPS configuration
Bits[5:1]
xx000
xx001
xx010
xx011
xx100
xx101
xx110
xx111
00xxx
01xxx
10xxx
11xxx
P
in Name
G
PIO_0
G
PIO_5_AC_BATT
GPIO_6
GPIO_15_PWRCNTL_0
GPIO_20_PWRCNTL_1
GPIO_29
GPIO_30
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_22_ROMCSB
GPIO_17_THERMAL_INT
GPIO_19_CTF
GPIO_21
GPIO_28_FDO
CLKREQB
PX_EN
PD(1%) CapPU(1%)
NC 4.75k
8.45k 2.00k
4.53k 2.00k
6.98k 4.99k
4.53k 4.99k
3.24k 5.62k
3.40k 10.0k
4.75k NC
T
ype PD/PU Description
I/O
3.3 V (VDDR3)
I/O
3.3 V (VDDR3)
I/O
3.3 V (VDDR3)
I
3.3 V (VDDR3)
O
3.3 V (VDDR3)
I/O
3.3 V (VDDR3)
O
3.3 V (VDDR3)
I/O
3.3 V (VDDR3)
I/O
3.3 V (VDDR3)
O
O PD
Primary Memory Aperture Size Requested at PCI Configuration
S
ze of the Primary
i
Memory Apertures
1
8 MB
2
ROM_CONFIG [2:0]
256 MB
64 MB
Reserved
512 MB
680nF
82nF
10nF
NC
PD-reset
PD-reset
PD-reset
PD-reset
PD-reset
PD-reset
PD-reset
PD-reset
PD-reset
1 GB
2 GB
4 GB Not supported
Power-state indicator. Permits the voltage regulator to activate power-saving features. IF VR Suport PSI# and DPRSLPVR PU 10K to +3VGS. PSI# :Low load current flag DPRSLPVR : Deeper sleep enable flag
(Optional) An input which allows the system to request a fastpower reduction by setting GPIO_5_AC_BATT to low (0 V). The resulting state transition may disturb the display momentarily. Power reductions that are less time critical should use the standard software methods in order to prevent display disturbances.
Voltage control signals for the core (VDDC and VDDCI). At reset, these signals will be inputs with weak internal pulldown resistors. The VBIOS can define all voltage-control signals to be either 3.3-V or open-drain outputs (all signals must be the same type). The output states (high/low) of these pins are programmable for each AMD PowerPlay state when they are used as voltage control signals. Note: GPIO_29 and GPIO_30 are only available on 28-nm ASICs, and are NC on earlier generation ASICs.
Serial-ROM output from ROM. General purpose I/O or open-drain output.
Design: No use external VGA ROM, so use the test point.
Serial-ROM input to ROM. General purpose I/O or open-drain output.
Serial-ROM clock to ROM. General purpose I/O or open-drain output.
BIOS-ROM chip select. Used to enable the ROM for ROM read and program operations.
Design: No use external VGA ROM, so use the test points.
Thermal monitor interrupt. An input from an external temperature sensor (ALERTb).
Critical temperature fault (CTF) (active high) will output 3.3 V if the on-die temperature sensor exceeds a critical temperature so that the motherboard can protect the ASIC from damage by removing power. The CTF setpoint is 109 by default, and is p
ogrammed during ASIC initialization. See the
r
advisory for AMD PowerPlay states for more details.
(Optional) Voltage control signal for the memory-voltage regulator. Note: This signal must be low (0 V) at reset (failure to do so will prevent booting).
Disable MLPS: PU 10K ohm to 3.3V. (Do not install for Mars) Enable MLPS: PD 10K ohm to GND. (Install for Mars)
Supports the CLKREQB feature for saving power to turn on/off the REFCLK clock on the ASIC.
On/off regulator switch in AMD PowerXpress? (switchable graphics) BACO mode. High (3.3 V) switches the regulators off (enter BACO mode). Low (0 V) switches the regulators on. (Default) PX_EN is tri-state before internal TEST_PG is asserted and PERSTb is deasserted.
Not supported
Not supported
Not supported
℃℃℃℃
C
000
001
010
011
MLPS Bit Strap Name Description Settings
ROM_CONFIG[0]
PS_0[1]
ROM_CONFIG[1]
PS_0[2]
ROM_CONFIG[2]
PS_0[3]
PS_0[4] N/A
STRAP_BIF_
PS_1[1]
GEN3_EN_A
PS_1[2] STRAP_BIF_
CLK_PM_EN
PS_1[3] N/A Reserved for internal use only. Must be 0 at reset.
PS_1[4] TX_PWRS_ENB
PS_1[5] TX_DEEMPH_EN
PS_2[1]
N/A
PS_2[2]
N/A
PS_2[3] BIOS_ROM_EN
PS_2[4] BIF_VGA_DIS
PS_2[5] N/A Reserved.
P
S
_3[1]
BOARD_CONFIG[0]
PS_3[2]
BOARD_CONFIG[1]
PS_3[3]
BOARD_CONFIG[2]
PS_0[5]
AUD_PORT_CONN_
PS_3[4]
PINSTRAP[0]
PS_3[5]
AUD_PORT_CONN_ PINSTRAP[1]
AUD_PORT_CONN_ PINSTRAP[2]
M
L
PS Strap
1
1
PS_0[5:1]
1 1
P
_1[5:1]
S
0 0
PS_2[5:1]
1 1
PS_3[5:1]
P
_0
S
P
S
_1
P
_2
S
P
_3
S
V
V
G
G
A@
A@
@
@
1
1
C
C
V
V
21
21
C
C
C
C
V20
V20
V
V
2
2
68U_0402_10V6K
68U_0402_10V6K
01U_0402_16V7K
01U_0402_16V7K
.
.
.
.
0
0
0
0
S
S
S
e
ecurity Classification
curity Classification
curity Classification
e
I
I
I
s
s
sued Date
sued Date
sued Date
s
T
T
T
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
H
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Legacy
G
PIO[13:11]
GENLK_VSYNC
GPIO_2
GPIO_8
If BIOS_ROM_EN = 1, ROM_CONFIG[2:0] define the ROM type. If BIOS_ROM_EN = 0, ROM_CONFIG[2:0] define the primary memory-aperture size. Refer to current databooks for details.
R
eserved for internal use only. Must be 1 at reset.
Re-defined strap to indicate PCIe GEN3 capability. 1 = PCIe GEN3 supported. 0 = PCIe GEN3 not supported.
Determines whether or not the PCIe reference clock power management capability is reported in the PCI configuration space (otherwise known as CLKREQB). 0 = The CLKREQB power management capability is disabled 1 = The CLKREQB power management capability is enabled
GENLK_CLK
GPIO_0
GPIO_1
N/A
N/A
GPIO_22
GPIO_9
Transmitter (Tx) power savings enable. 0 = 50% Tx output swing. 1 = Full Tx output swing.
PCI EXPRESS transmitter, deemphasis enable. 0 = Tx deemphasis disabled. 1 = Tx deemphasis enabled.
Reserved.
Reserved.
To enable the external BIOS ROM device. 0 = Disable the external BIOS ROM device. 1 = Enable the external BIOS ROM device.
VGA disable determines whether or not the card will be recognized as the system's VGA controller. 0 = VGA controller capacity enabled. 1 = The device will not be recognized as the system’s VGA controller.
N/A
N/A
N/A
C
B
a
i
pacitorBits[5:4]
ts[3:1]
0
0 1
NC
0
0 1
NC
0 0 0
680 nF
X
X X
NC
M
apping to VRAM type please refer to page 6
@
@
R
R
V
V
8.45K_0402_1%
8.45K_0402_1%
@
@
@
@
1
1
C
C
23
23
V
V
22
22
2K_0402_1%
2K_0402_1%
2
2
01U_0402_16V7K
01U_0402_16V7K
01U_0402_16V7K
01U_0402_16V7K
.
.
.
.
0
0
0
0
2
2
2
0
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
Board configuration related strapping (such as memory ID).
Together with PS_0[5] form the three-bit strap option to indicate the number of audio-capable display outputs. In a given ASIC there are as many endpoints as there are digital display outputs, though not all outputs are audio capable. 111 = No usable endpoints. 110 = One usable endpoint. 101 = Two usable endpoints. 100 = Three usable endpoints. 011 = Four usable endpoints. 010 = Five usable endpoints. 001 = Six usable endpoints. 000 = All endpoints are usable.
R
_
pu R_pd
8.45K 2K
8
45K
2K
.
NC
4.75K
X
X
12
12
@
@
R
R
V
V
21
21
20
20
8.45K_0402_1%
8.45K_0402_1%
8.45K_0402_1%
8.45K_0402_1%
1
VGA@
VGA@
R
R
V
V28
4.75K_0402_1%
4.75K_0402_1%
2
C
C
C
o
ompal Secret Data
mpal Secret Data
mpal Secret Data
o
12
28
4.75K_0402_1%
4.75K_0402_1%
Deciphered Date
Deciphered Date
Deciphered Date
@
@
R
R
27
27
V
V
D
@
@
R
R
VGA@
VGA@
R
R
001
1
0
0
0
1
1
0
0
0
0
0
Base on VRAM ID
111
+
1.8VGS
1
12
VGA@
VGA@
R
R
V
23
23
22
V22
V
V
8.45K_0402_1%
8.45K_0402_1%
2
12
12
V
V
68
68
2K_0402_1%
2K_0402_1%
VGA@
VGA@
R
R
V
G
A_SMB_CK2
V
V
30
30
V
A_SMB_DA2
G
T
T
T
i
i
tle
tle
tle
i
Size Document Numbe r Rev
Size Document Numbe r Rev
Size Document Numbe r Rev
C
C
C
ustom
stom
stom
u
u
Date: Sheet
Date: Sheet
Date: Sheet
+
VGS
3
2
VGA@
VGA@
Q
Q
V
1A
1A
V
DMN66D0LDW-7 2N_SOT363-6
DMN66D0LDW-7 2N_SOT363-6
DMN66D0LDW-7 2N_SOT363-6
DMN66D0LDW-7 2N_SOT363-6
C
C
C
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
M
M
M
L
L
L
A
-9868P
-9868P
-9868P
A
A
E
61
5
4
Q
Q
V
V
a
in_MSIC
in_MSIC
in_MSIC
a
a
E
_SMB_CK2 <25,29,6>
C
3
E
_SMB_DA2 <25,29,6>
VGA@
VGA@
C
1
1
1
o
o
o
f
f
13 42Thursday, May 16, 2013
13 42Thursday, May 16, 2013
13 42Thursday, May 16, 2013
f
1B
1B
.0
0
0
.
.
Page 14
CyberForum.ru
A
MPLL_PVDD MarsCRB Design
1 1
2 2
220ohm 1 1
0.1u 1 1 1u 1 1
2.2u 1 1
S
PLL_PVDD MarsCRB Design
120ohm 1 1
0.1u 1 1 1u 1 1
2.2u 1 1
SPLL_VDDC MarsCRB Design 120ohm 1 1
0.1u 1 1 1u 1 1
2.2u 1 1
+
1
.8VGS
L
L
1 2
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
+
.8VGS
1
L
L
1 2
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
+
.95VGS
0
L
L
1 2
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
B
+
M
PV18
(
PLL_PVDD:1.8V@130mA )
7
VGA@
7
VGA@
V
V
8
VGA@
8
VGA@
V
V
V
9
VGA@
9
VGA@
V
M
79
79
78
78
V
V
V
V
1
1
C
C
C
C
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
VGA@
VGA@
VGA@
VGA@
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
+
PV18
S
(SPLL_PVDD:1.8V@75mA )
81
81
82
82
V
V
V
V
1
1
C
C
C
C
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
VGA@
VGA@
VGA@
VGA@
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
+
S
PLL_VDDC
(SPLL_VDDC:0.95V@100mA )
93
93
92
92
V
V
V
V
1
1
C
C
C
C
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
VGA@
VGA@
VGA@
VGA@
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
80
80 V
V
1
C
C
2
VGA@
VGA@
83
83 V
V
1
C
C
2
VGA@
VGA@
94
94 V
V
1
C
C
2
VGA@
VGA@
+
PV18
M
+
S
PV18
+
S
PLL_VDDC
C
7
H
8
H
M
10
A
9
N
A
N
10
A
F
30
A
F
31
A
V
V
1C
1C
U
U
M
PLL_PVDD
MPLL_PVDD
SPLL_PVDD
SPLL_VDDC
SPLL_PVSS
NC_XTAL_PVDD NC_XTAL_PVSS
P
P
RT 9 0F 9
RT 9 0F 9
A
A
D
VGA@
VGA@
1 2
R
R
V
V
31 1M_0402_5%
31 1M_0402_5%
VGA@
VGA@
V
V
1
1
Y
Y
4
S
C
C
O
N
1
XT
V
33
A
X
XTALIN
XTALOUT
XO_IN
LS/XTAL
LS/XTAL L
L P
P
SUN-PRO M2_FCBGA962V GA@
SUN-PRO M2_FCBGA962V GA@
XO_IN2
CLKTESTA CLKTESTB
TALIN
34
U
A
X
ALOUT
T
W34
A
W
35
A
D
ebug Only, for clock observati on
10
K
A
As short as pos sible
10
L
A
15P_0402_50V8J
15P_0402_50V8J
VGA@
VGA@
ALIN
2
27MHZ 10PF +-20PPM X3G027000DA1H
27MHZ 10PF +-20PPM X3G027000DA1H
V
V
24
24
C
C
1
C
S
C
O
N
E
3
X
TALOUT
2
2
C
C
V
V
25
25
15P_0402_50V8J
15P_0402_50V8J
1
VGA@
VGA@
+
.95VALW
A
0
VGA@
VGA@
Q
Q
3
3
V
V
8
D
7
D
6
D
5
D
FDS6676AS_SO8
FDS6676AS_SO8
3 3
4 4
+
.95VGS
0
V
1
S
2
S
3
S
4
G
Q
V
3_GATE
1
12
49
49
106
106
V
V
V
V
R
R
C
C
2
VGA@
VGA@
VGA@
VGA@
820K_0402_5%
820K_0402_5%
0.1U_0402_25V6
0.1U_0402_25V6
+0.95VS to +0.95VGS
g
s=10V,Id=14.5A, Rds=6mohm
R
R
V
V
45
45
V
V
A@
A@
G
2
1
R
R
48
48
V
V
220K_0402_5%
220K_0402_5%
61
VGA@
VGA@
2
P
X
S_PWREN#
VGA@
VGA@
V
V
8A
8A
Q
Q
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
G
B
+
5
B
0_0805_5%
0_0805_5% 7
7 4
4
1 2 3
VGA@
VGA@
Q
Q
8B
8B
V
V
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
4
+
3
VGS
VGA@
VGA@
V
V
43
43
R
R
470_0805_5%
470_0805_5%
1 2
3
VGA@
VGA@
Q
Q
9B
V9B
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
P
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
s
sued Date
sued Date
sued Date
s
s
T
T
T
H
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2
2
2
12/09/27 2015/09/27
012/09/27 2015/09/27
12/09/27 2015/09/27
0
0
C
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
o
D
D
D
e
eciphered Date
ciphered Date
ciphered Date
e
V
4
P
X
S_PWREN<39,8>
X
D
5
P
S_PWREN
VGA@
VGA@
R
R
100K_0402_5%
100K_0402_5%
S_PWREN#
X
V
V
Q
Q
+
3VS to +3VGS
+
3
VALW
@
@
2
C
44
44
V
V
VGA@
VGA@
R
R
1 2
47K_0402_5%
47K_0402_5%
1 2
6
A@
A@
G
G
V
V
9A
9A
2
1
7002DW-T/R7_SOT363-6
7002DW-T/R7_SOT363-6 N
N 2
2
Date: S heet
Date: S heet
Date: S heet
C
0.1U_0402_16V7K
0.1U_0402_16V7K
1
46
46
V
V
2
104
104 V
V C
C
1
VGA@
VGA@
0.01U_0402_25V7K
0.01U_0402_25V7K
T
T
T
i
tle
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
u
stom
stom
stom
u
u
+
VS
3
V
103
103
V
C
C
C
o
o
o
Vgs=-4.5V,Id=3A ,Rds<97mohm
S
S
3
G
G
2
D
D
Q
Q
4
V4
V
1
3413_SOT23
3413_SOT23
V
V
G
A@
A@
G
O
O A
A
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
B
B
B
A
CO POWER
CO POWER
CO POWER
A
A
L
L
L
A
-9868P
-9868P
A-9868P
A
E
+
VGS
3
1
1
1
.
0
0
0
.
.
o
o
o
f
14 42Thursday, May 16, 2013
14 42Thursday, May 16, 2013
14 42Thursday, May 16, 2013
f
f
Page 15
CyberForum.ru
A
O
ly for Kabini
n
B
+
1.8VALW to +1.8VGS
C
D
E
+1.5V to +1.5VGS
1 1
+
.5V
1
C
C
1
@
@
1
1 U
U _0402_6.3V6K
_0402_6.3V6K
2
2 2
V
N 5V and 3.3V ( VBIAS=5V),IMAX( per channel)=6 A,Rds=18mohm
I
1
A_PWRGD
2
3
4
5
6 7
96
96
V
V
+
5
V
G
A_PWRGD<39,8>
+
.8VALW
1
1
C
@ C
@
100
100
V
V
1
1 U
U _0402_6.3V6K
_0402_6.3V6K
2
VALW
V
GA_PWRGD
V
G
VGA@
VGA@
U
U
3
3
V
V
V
I
N1
V
N1
I
O
1
N
V
B
IAS
O
2
N
V
N2
I
V
N2
I
TPS22966DPUR_SON14_2X3
TPS22966DPUR_SON14_2X3
14
V
O
UT1
13
V
O
UT1
12
C
T
1
11
G
N
D
10
C
T
2
9
V
UT2
O
8
V
O
UT2
15
G
AD
P
+
.5VGS_LS
1
+
1
.8VGS_LS
C
C
V
V
C
C
V
V
1 2
1 2
95 180P_0402_50V8J
95 180P_0402_50V8J
VGA@
VGA@
99 330P_0402_50V7K
99 330P_0402_50V7K
VGA@
VGA@
P
P
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
1
3
3
J1
J1
@
@
P
P
J1
J1
2
2
@
@
2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
+
.8VGS
1
2
C
@ C
@
0
0 .1U_0402_10V7K
.1U_0402_10V7K
1
+
1.5VGS
@ C
@
V
V
98
98
2
C
V97
V97
0
0 .
.
1U_0402_10V7K
1U_0402_10V7K
1
3 3
4 4
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
s
s
sued Date
sued Date
sued Date
s
T
T
T
H
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2
2
2
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
C
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
o
D
D
D
e
e
ciphered Date
ciphered Date
ciphered Date
e
C
C
C
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
T
T
T
tle
itle
itle
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
u
stom
stom
stom
u
u
Date: S heet
Date: S heet
D
Date: S heet
o
L
L
L
B
B
B
A
-9868P
-9868P
-9868P
A
A
A
CO POWER
CO POWER
CO POWER
A
A
E
1
1
1
.
0
0
0
.
.
o
o
o
f
15 42Thursday, May 16, 2013
f
15 42Thursday, May 16, 2013
15 42Thursday, May 16, 2013
f
Page 16
CyberForum.ru
A
B
C
D
E
VDDR1 MarsCRB Design
0.01u 5 0
0.1u 5 0
2.2u 5 5 10u 3 3
VDD_CT MarsCRB Design 120ohm 1 1
1 1
0.1u 1 1 1u 1 1 10u 1 1
V
DR3 Mars chec k list Design
D 120ohm 1 1 1u 3 2 10u 1 0
0.1u 0 1
+
.8VGS
1
1 2
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
+
VGS
2 2
3 3
3
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
1
.5VGS
+1
(VDDR1:1.5V@1.5A)
36
36
34
34
33
33
V
V
V
1
1
C
C
C
CV
2
2
10U_0603_6.3V6M
VGA@
10U_0603_6.3V6M
VGA@
10U_0603_6.3V6M
VGA@
10U_0603_6.3V6M
VGA@
+
DDC_CT
VGA@
VGA@
VGA@
VGA@
V
51
51 V
V
1
C
C
2
10U_0603_6.3V6M
VGA@
10U_0603_6.3V6M
VGA@
+
DDR3
V
2
42
42 V
V
1
C
C
2
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
R
oute as differential pair
L
L
V
V
4
4
L
L
V
V
5
5
37
37
35
35
V
V
V
V
V
1
1
1
C
C
CV
C
C
C
2
2
2
VGA@
VGA@
VGA@
VGA@
10U_0603_6.3V6M
VGA@
10U_0603_6.3V6M
VGA@
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
(
VDD_CT:1.8V@13mA )
52
52
53
53
V
V
V
V
1
1
C
C
C
C
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
VGA@
VGA@
VGA@
VGA@
(VDDR3:3.3V@25mA)
54
54
55
55
V
V
1
1
CV
CV
C
C
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
VGA@
VGA@
VGA@
VGA@
V
C
C_GPU_SENSE<39>
V
S
S_GPU_SENSE<39>
+
1
39
39
38
38
40
40
V
V
V
V
V
V
1
1
1
C
C
C
C
C
C
2
2
2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
+
DDC_CT
V
+
DDR3
V
T
T
V
V
44
44
.5VGS
U
U
1E
1E
V
V
P
P
ART 5 0F 9
ART 5 0F 9
MEM I/O
MEM I/O
7
C
A
D
DR1
V
D
11
A
D
DR1
V
F
7
A
D
DR1
V
10
G
A
DR1
D
V
7
J
A
DR1
D
V
8
K
A
D
DR1
V
L
9
A
D
DR1
V
1
1
G
D
DR1
V
4
1
G
DR1
D
V
7
1
G
DR1
D
V
0
2
G
D
DR1
V
2
3
G
D
DR1
V
2
6
G
DR1
D
V
9
2
G
DR1
D
V
1
0
H
D
DR1
V
7
J
DR1
D
V
9
J
DR1
D
V
K
1
1
V
DR1
D
K
3
1
V
DR1
D
K
8
V
D
DR1
L
1
2
V
D
DR1
L
1
6
V
D
DR1
L
2
1
V
DR1
D
L
3
2
V
DR1
D
L
6
2
V
DR1
D
L
7
V
DR1
D
M
1
1
V
DDR1
N
1
1
V
D
DR1
P
7
V
D
DR1
R
1
1
V
D
DR1
U
1
1
V
DR1
D
U
7
V
DR1
D
Y
1
1
V
DR1
D
Y
7
V
DR1
D
LEVEL
LEVEL
T
T
RANSLATION
RANSLATION
A
F
26
V
D
D_CT
A
F27
V
D
D_CT
A
G
26
V
D
D_CT
A
G
27
V
D
D_CT
I/O
I/O
A
23
F
V
DR3
D
A
F24
V
D
DR3
A
G
23
V
D
DR3
A
G
24
V
D
DR3
D
D
VP
VP
A
12
D
V
DR4
D
A
11
F
V
DR4
D
A
12
F
V
DR4
D
A
13
F
V
DR4
D
A
F
15
V
D
DR4
A
G
11
V
D
DR4
A
G
13
V
D
DR4
A
G
15
V
D
DR4
VOLTAGE
VOLTAGE SENESE
SENESE
A
F
28
F
B
_VDDC
A
28
G
F
_VDDCI
B
A
H
29
F
B
_GND
NC NC
CIE
CIE P
P
BACO
BACO
CORE
CORE
ISOLATED
ISOLATED
SUN-PRO M2_FCBGA962VGA@
SUN-PRO M2_FCBGA962VGA@
_BIF_VDDC _BIF_VDDC C
IE_PVDD
P
C
P
C
P
C
P
C
P
C
P
C
P
C
P
C
P
C
P
C
P
C
P
C
P
B B
ORE I/O
ORE I/O C
C
NC NC N NC NC NC
IE_VDDC IE_VDDC IE_VDDC IE_VDDC IE_VDDC IE_VDDC IE_VDDC IE_VDDC IE_VDDC IE_VDDC IE_VDDC IE_VDDC
F_VDDC
I
F_VDDC
I
V V V V V V V V V V V V V V V V V V V V V V V V V V
V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
V V V V V V V V V V V V V V V V V V V V V V
A
31
A
A
32
A
33
AA
C
34
AA
0
W3
1
3
Y
8
V2
9
W2
37
AB
3
0
G
3
1
G
2
9
H
3
0
H
9
2
J
3
0
J
2
8
L
2
8
M
2
8
N
2
8
R
2
8
T
8
2
U
7
2
N
7
2
T
A
15
A
D
DC
A
17
A
D
DC
A
20
A
D
DC
22
A
A
DC
D
24
A
A
DC
D
27
A
A
DC
D
B
16
A
D
DC
B
18
A
D
DC
B
21
A
D
DC
B
23
A
DC
D
26
B
A
DC
D
28
B
A
DC
D
17
C
A
DC
D
C
20
A
D
DC
C
22
A
D
DC
C
24
A
D
DC
C
27
A
DDC
18
D
A
DC
D
21
D
A
DC
D
23
D
A
D
DC
D
26
A
D
DC
F
17
A
D
DC
20
F
A
DC
D
22
F
A
DC
D
16
G
A
D
DC
G
18
A
D
DC
H
22
A
D
DC
27
H
A
DC
D
28
H
A
DC
D
6
2
M
DC
D
2
4
N
D
DC
1
8
R
D
DC
1
2
R
DC
D
3
2
R
DC
D
6
2
R
DC
D
1
7
T
D
DC
2
0
T
DC
D
2
2
T
DC
D
2
4
T
D
DC
1
6
U
D
DC
1
8
U
D
DC
1
2
U
DC
D
3
2
U
DC
D
6
2
U
DC
D
1
7
V
D
DC
0
2
V
DC
D
2
2
V
DC
D
2
4
V
D
DC
2
7
V
D
DC
1
6
Y
D
DC
8
1
Y
DC
D
1
2
Y
D
DC
2
3
Y
D
DC
6
2
Y
DC
D
8
2
Y
DC
D
A
13
A
D
DCI
13
B
A
DCI
D
12
C
A
DCI
D
15
C
A
DCI
D
D
13
A
D
DCI
16
D
A
DCI
D
5
1
M
DCI
D
1
6
M
D
DCI
1
8
M
D
DCI
3
2
M
DCI
D
1
3
N
D
DCI
1
5
N
D
DCI
1
7
N
DCI
D
0
2
N
D
DCI
2
2
N
D
DCI
1
2
R
D
DCI
3
1
R
DCI
D
1
6
R
D
DCI
1
2
T
D
DCI
5
1
T
DCI
D
1
5
V
D
DCI
1
3
Y
D
DCI
(PCIE_PVDD: 1.80V@100mA)
+
.8VGS
1
30
30 V
V
1
C
C
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
+0
.95VGS
V43
V43
1
C
C
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
(
B
+
0
.95VGS
67
67 V
V
1
C
C
2 @
@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
+
GA_CORE
V
+
V
GA_CORE
+
GA_CORE
V
31
31 V
V
1
C
C
2
VGA@
VGA@
10U_0603_6.3V6M
10U_0603_6.3V6M
44
44 V
V
1
C
C
2
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
IF_VDDC: 0.95V@1.4A)
68
68 V
V
1
C
C
2 @
@
10U_0603_6.3V6M
10U_0603_6.3V6M
Maximum Current on +1.8VGS:
32
32 V
V
1
"Sun": ~0.5 A
C
C
2
VGA@
VGA@
P
CIE_VDDC:
0.95 V @ 1.88 A (PCIe Gen 2.0)
0.95 V @ 2.50 A (PCIe Gen 3.0)
46
46
41
41
45
45 V
V
1
C
C
2
VGA@
VGA@
V69
V69
1
C
C
2 @
@
47
47
V
V
V
V
V
V
1
1
1
C
C
C
C
C
C
2
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
+
Maximum Current on +0.95VGS: "Sun": ~4.0 A for PCIe GEN 3.0 designs (estimated)
0
1U_0402_6.3V6K
1U_0402_6.3V6K
.95VGS
.8VGS
+1
+
0
.95VGS
49
48
48
50
50
V49
V
V
V
V
V
1
1
1
C
C
C
C
C
C
2
2
2
10U_0603_6.3V6M
VGA@
10U_0603_6.3V6M
VGA@
VGA@
VGA@
10U_0603_6.3V6M
VGA@
10U_0603_6.3V6M
VGA@
P
IE_PVDD MarsC RB Design
C 1u 2 2 10u 1 1
PCIE_VDDC Mar sCRB Design 1u 7 7 10u 2 2
B
F_VDDC Mars check list De sign
I 1u 1 1 10u 1 1
+
GA_CORE
V
N
ed check all power current and decoupling capacitors
e
4 4
A
after got SUN databook and reference schematic.
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
sued Date
ssued Date
sued Date
s
s
T
T
T
H
HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL
IS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFI DENTIAL
IS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFI DENTIAL
H
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
B
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
C
2
2
2
12/09/27 2015/09/27
012/09/27 2015/09/27
12/09/27 2015/09/27
0
0
C
C
C
o
mpal Secret Data
mpal Secret Data
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o
o
D
D
D
ciphered Date
eciphered Date
ciphered Date
e
e
C
C
C
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
T
T
Title
tle
itle
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet
D
Date: Sheet
o
P
P
P
o
wer
wer
wer
o
L
L
L
A
A
A
o
-9868P
-9868P
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6 4
6 4
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1
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.
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2Thursday, May 16, 2013
2Thursday, May 16, 2013
2Thursday, May 16, 2013
f
0
0
0
Page 17
CyberForum.ru
A
UV
UV
1H
1H
PART 3 0F 9
PART 3 0F 9
GDDR5/DDR3
D DQ D D DQ D DQ DQ DQ DQ D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
M M
N N N
M
N N
VGA@
VGA@
Q
Q Q
Q
Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
V V
C C C
E
C C
A0_0 A0_1 A0_2 A0_3 A0_4 A0_5 A0_6 A0_7 A0_8 A0_9 A0_10 A0_11 A0_12 A0_13 A0_14 A0_15 A0_16 A0_17 A0_18 A0_19 A0_20 A0_21 A0_22 A0_23 A0_24 A0_25 A0_26 A0_27 A0_28 A0_29 A0_30 A0_31 A1_0 A1_1 A1_2 A1_3 A1_4 A1_5 A1_6 A1_7 A1_8 A1_9 A1_10 A1_11 A1_12 A1_13 A1_14 A1_15 A1_16 A1_17 A1_18 A1_19 A1_20 A1_21 A1_22 A1_23 A1_24 A1_25 A1_26 A1_27 A1_28 A1_29 A1_30 A1_31
REFDA REFSA
M_CALRP0
GDDR5/DDR3
EMORY INTERFACE A
EMORY INTERFACE A M
M
SUN-PRO M2_FCBGA962
SUN-PRO M2_FCBGA962
Compal P/N
SA00003YO70
SA00005XB00
SA00005SH00
Compal P/N
SA000065300
SA000068U20
A0_0/MAA_0
MA M
A0_1/MAA_1
A
A0_2/MAA_2
MA
A0_3/MAA_3
MA M
A0_4/MAA_4
A
A0_5/MAA_5
MA M
A0_6/MAA_6
A
M
A0_7/MAA_7
A
M
A1_0/MAA_8
A
M
A
A1_1/MAA_9
MA
A1_2/MAA_10
M
A
A1_3/MAA_11
M
A
A1_4/MAA_12
M
A
A1_5/MAA_BA2
M
A
A1_6/MAA_BA0
M
A
A1_7/MAA_BA1
W
KA0_0/DQMA_0
C
W
KA0B_0/DQMA_1
C
W
KA0_1/DQMA_2
C
WC
KA0B_1/DQMA_3
WC
KA1_0/DQMA_4
WC
KA1B_0/DQMA_5
WC
KA1_1/DQMA_6
WC
KA1B_1/DQMA_7
ED
CA0_0/QSA_0
ED
CA0_1/QSA_1
ED
CA0_2/QSA_2
ED
CA0_3/QSA_3
ED
CA1_0/QSA_4
ED
CA1_1/QSA_5
ED
CA1_2/QSA_6
ED
CA1_3/QSA_7
BIA0_0/QSA_0B
DD
BIA0_1/QSA_1B
DD
BIA0_2/QSA_2B
DD
BIA0_3/QSA_3B
DD
BIA1_0/QSA_4B
DD
BIA1_1/QSA_5B
DD
BIA1_2/QSA_6B
DD
BIA1_3/QSA_7B
DD
D
BIA0/ODTA0
A
D
BIA1/ODTA1
A
A
A0_8/MAA_13
M
A
A1_8/MAA_14
M
A0_9/MAA_15
A
M
A1_9/RSVD
A
M
C
C
R R
C C
S
C
S
C
S
C
S
C
C C
W W
3
7
C C3
5
3
5
A E3
4 2
3
G
3
3
D
2
F3
2
E3
1
D3
0
3
F
3
0
C
3
0
A
2
8
1 1
2 2
1 2
V
V
34 120_0402_1%VGA@
34 120_0402_1%VGA@
R
R
Memory clock 900MHz RC99 10K pull down
3 3
GPU Type
SUN PRO-M2
SUN PRO-M2
SUN PRO-M2
M
emory clock 1GHz RC95 10K pull high
GPU Type
SUN PRO-M2 2Gbit
SUN PRO-M2
4 4
Memory Bus Width
64bit
64bit
64bit
Memory Bus Width
64bit
64bit
F
2
8
C
2
8
A
2
8
E
2
7
D
6
2
F
2
6
C
2
6
A
2
4
F
2
4
C
4
2
A
4
2
E
2
2
C
2
2
A
2
2
F
2
1
D
2
0
A
2
0
F
1
9
D
8
1
E
8
1
C
8
1
A
1
8
F
1
7
D
1
6
A
6
1
F
5
1
D
4
1
E
4
1
F
1
3
D
1
2
F
1
2
A
1
1
D
0
1
F
0
1
A
1
0
C
1
3
G
1
3
H
3
1
J
1
1
H
1
0
G
8
G
9
K
0
1
K
9
G
8
A
8
C
8
E
6
A
6
C
6
E
5
A
8
1
L
0
2
L
2
7
L
1
2
N G
12
A
2
7
M
1
2
M
12
H
A
VRAM Vendor
Hynix
Micron
Samsung
VRAM Vendor
Hynix
Samsung
B
4
G2 J
3
2
4
H2 J
4
2
6
H2
6
J2 H
1
2
G
1
2
H
9
1
0
H2 L
3
1
G
1
6
J
1
6
H
1
6
J
1
7
H
1
7
2
A3 C3
2
D
3
2
E2
2
C1
4
A1
4
E1
0
D9
C3
4
D2
9
D2
5
E2
0
E1
6
E1
2
J1
0
D7
4
A3
0
E3
6
E2
0
C2
6
C1
2
C1
1
J1 F8
2
1
J
1
9
G
2
7
H
L
KA0
C
2
7
G
L
KA0B
1
4
J
L
KA1
C
1
4
H
L
KA1B
3
2
K
SA0B
A
9
1
K
SA1B
A
0
2
K
SA0B
A
7
1
K
SA1B
A
2
4
K
A0B_0
2
7
K
A0B_1
1
3
M
A1B_0
1
6
K
A1B_1
1
2
K
EA0
K
0
2
J
EA1
K
6
2
K
A0B
E
1
5
L
E
A1B
2
3
H
1
9
J
1
2
M
0
2
M
Manufacturer P/N
H5TQ2G63DFR-11C
MT41K128M16JT-107G:K
K4W2G1646E-BC11
Manufacturer P/N
H5TQ2G63DFR-N0C
K4W2G1646E-BC1A
C
lose to pin Y12 and AA12
Z
Z2
Z2
Z
Z
Z
G
G
1
1
S
S
S1G@
S1G@
7
6xxxxxLx1
6xxxxxLx1
7
X
X
X76 P/N
X7648051L01
X7648051L03
X7648051L04
X76 P/N
X7648051L05
1
.5VGS
+
1
V
V
72
72
R
R
40.2_0402_1%
40.2_0402_1%
VGA@
VGA@
R
R
100_0402_1%
100_0402_1%
VGA@
VGA@
Size per part
73
73
V
V
Z
Z
Z
Z
7
7
X
X
2
12
Z3
Z3
1
1
H
H
H1G@
H1G@
6xxxxxLx2
6xxxxxLx2
G
G
1
5
+
VREFDB_SB
M
1
V
V
159
159
C
C 1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
2
Z4
Z4
Z
Z
Z
Z
2
2
G
G
S
S
S2G@
S2G@
7
6xxxxxLx3
6xxxxxLx3
7
X
X
Configuration
mil
2Gbit 128M*16 1GB/4pcs
2Gbit
2Gbit
Size per part
128M*16
128M*16 1GB/4pcs
Configuration
128M*16 1GB/4pcsX7648051L02
2Gbit
128M*16
C
D
B[0..63]<19>
M
Z
Z
Z5
Z5
Z
Z
G
G
2
2
H
H
H2G@
H2G@
7
6xxxxxLx4
6xxxxxLx4
7
X
X
Total Memory Size/Qty
1GB/4pcs
Total Memory Size/Qty
1GB/4pcs
D
U
U
1I
1I
V
V
P
P
ART 4 0F 9
B[0..63]
MD
+
M
VREFDB_SB
C
5
MD
B0
C
3
M
B1
D
E
3
M
B2
D
E
1
M
B3
D
F
1
M
B4
D
F
3
M
DB5
F
5
M
D
B6
G
4
M
D
B7
H
5
M
D
B8
H
6
M
B9
D
J
4
M
B10
D
K
6
M
B11
D
K
5
M
DB12
L
4
M
D
B13
M
6
M
D
B14
M
1
M
B15
D
M
3
M
B16
D
M
5
M
B17
D
N
4
M
B18
D
P
6
M
B19
D
P
5
M
B20
D
R
4
M
DB21
T
6
M
D
B22
T
1
M
D
B23
U
4
M
B24
D
V
6
M
B25
D
V
1
M
DB26
V
3
M
D
B27
Y
6
M
D
B28
Y
1
M
B29
D
Y
3
M
B30
D
Y
5
M
B31
D
A
4
A
M
D
B32
A
6
B
M
D
B33
A
1
B
M
B34
D
A
3
B
M
B35
D
A
6
D
M
DB36
A
1
D
M
D
B37
A
3
D
M
B38
D
A
D
5
M
B39
D
A
F
1
M
B40
D
A
3
F
M
D
B41
A
F
6
M
D
B42
A
G
4
M
B43
D
A
5
H
M
B44
D
A
H
6
M
DB45
A
J
4
M
D
B46
A
K3
M
B47
D
A
F
8
M
B48
D
A
F
9
M
B49
D
A
G
8
M
D
B50
A
G
7
M
B51
D
A
K
9
M
B52
D
A
7
L
M
D
B53
A
M
8
M
D
B54
A
7
M
M
D
B55
A
K
1
M
B56
D
A
L
4
M
D
B57
A
M
6
M
D
B58
A
1
M
M
B59
D
A
4
N
M
B60
D
A
3
P
M
D
B61
A
1
P
M
B62
D
A
5
P
M
B63
D
Y
2
1
A
12
A
R
_
pu & R_pd resistor:
0402 1% resistors are required.
0 0
0
0
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
D D D D D D
M M
VGA@
VGA@
Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
V V
B0_0 B0_1 B0_2 B0_3 B0_4 B0_5 B0_6 B0_7 B0_8 B0_9 B0_10 B0_11 B0_12 B0_13 B0_14 B0_15 B0_16 B0_17 B0_18 B0_19 B0_20 B0_21 B0_22 B0_23 B0_24 B0_25 B0_26 B0_27 B0_28 B0_29 B0_30 B0_31 B1_0 B1_1 B1_2 B1_3 B1_4 B1_5 B1_6 B1_7 B1_8 B1_9 B1_10 B1_11 B1_12 B1_13 B1_14 B1_15 B1_16 B1_17 B1_18 B1_19 B1_20 B1_21 B1_22 B1_23 B1_24 B1_25 B1_26 B1_27 B1_28 B1_29 B1_30 B1_31
REFDB REFSB
ART 4 0F 9
GDDR5/DDR3
GDDR5/DDR3
PS_3[ 1]PS_3[ 2 ]PS_3[ 3 ]
0
1
11 1
M M M M M M M M M
M M M M
KB0_0/DQMB_0
C
W
C
KB0B_0/DQMB_1
W
W
C
KB0_1/DQMB_2
W
C
KB0B_1/DQMB_3
W
KB1_0/DQMB_4
C
W
KB1B_0/DQMB_5
C
W
KB1_1/DQMB_6
C
EMORY INTERFACE B
EMORY INTERFACE B M
M
W
C
KB1B_1/DQMB_7
E
D
E
D
E
D
E
D
E
D
E
D
E
D
E
D
D
BIB0_0/QSB_0B
D
D
BIB0_1/QSB_1B
D
D
BIB0_2/QSB_2B
D
D
D
BIB0_3/QSB_3B
D
D
BIB1_0/QSB_4B
D
D
BIB1_1/QSB_5B
D
D
BIB1_2/QSB_6B
D
D
BIB1_3/QSB_7B
A A
M M M
M
SUN-PRO M2_FCBGA962
SUN-PRO M2_FCBGA962
R_pu
RV20
N
C
RV20
8
45K 2K
.
RV20
4.75K
A
B0_0/MAB_0 B0_1/MAB_1
A
B0_2/MAB_2
A
B0_3/MAB_3
A A
B0_4/MAB_4
A
B0_5/MAB_5 B0_6/MAB_6
A
B0_7/MAB_7
A
B1_0/MAB_8
A A
B1_1/MAB_9
A
B1_2/MAB_10 B1_3/MAB_11
A
B1_4/MAB_12
A
A
M
A
M
A
M
CB0_0/QSB_0 CB0_1/QSB_1 CB0_2/QSB_2 CB0_3/QSB_3 CB1_0/QSB_4 CB1_1/QSB_5 CB1_2/QSB_6 CB1_3/QSB_7
BIB0/ODTB0
D
BIB1/ODTB1
D
B0_8/MAB_13
A
B1_8/MAB_14
A
B0_9/MAB_15
A
A
D
4.75K
B1_5/BA2 B1_6/BA0 B1_7/BA1
C
L
C
L
KB0B
C
L
C
L
KB1B
R
SB0B
A
R
SB1B
A
C
SB0B
A
C
A
SB1B
C
S
B0B_0
C
S
B0B_1
C
B1B_0
S
C
B1B_1
S
C
K
C
K
W
E
W
E
B1_9/RSVD
AM_RST
R
R_pd
RV27
RV27
RV27
NC
8
P
B0
MA
9
T
M
B1
A
9
P
M
AB2
7
N
M
AB3
8
N
M
A
B4
9
N
M
A
B5
9
U
M
A
B6
8
U
M
A
B7
9
Y
M
A
B8
9
W
M
A
B9
C
8
A
M
B10
A
C
9
A
M
B11
A
7
A
A
M
A
B12
8
A
A
B_
BA2
8
Y
B_
BA0
A
9
A
B
BA1
_
3
H
D
MB#0
Q
1
H
D
MB#1
Q
T
3
D
MB#2
Q
T
5
D
MB#3
Q
A
4
E
D
MB#4
Q
A
5
F
D
QMB#5
A
6
K
D
QMB#6
A
K
5
D
Q
MB#7
F
6
Q
S
B0
K
3
Q
S
B1
P
3
Q
B2
S
V
5
Q
B3
S
A
5
B
Q
B4
S
A
H
1
Q
B5
S
A
J
9
Q
S
B6
A
M
5
Q
S
B7
G
7
Q
S
B#0
K
1
Q
B#1
S
P
1
Q
B#2
S
W
4
Q
B#3
S
A
C
4
Q
SB#4
A
H
3
Q
S
B#5
A
J
8
Q
S
B#6
A
M
3
Q
S
B#7
T
7
O
TB0
D
W
7
O
TB1
D
L
9
C
L
KB0
KB1
EB0 EB1
B0B B1B
KB0
L
8
C
L
KB0#
A
D
8
C
KB1
L
A
D
7
C
KB1#
L
T
0
1
R
SB0#
A
Y
0
1
R
A
SB1#
W
0
1
C
A
SB0#
A
A
10
C
SB1#
A
P
1
0
C
SB0#_0
L
1
0
A
10
D
C
B1#_0
S
A
C
10
U
0
1
C
EB0
K
A
11
A
C
EB1
K
N
1
0
W
E
B0#
A
B
11
W
E
B1#
T
8
M
B13
A
W
8
M
B14
A
U
1
2
M
A
B15
V
2
1
A
11
H
AM_RST#_R
R
D
VGA@
VGA@
V
V
71
71
R
R
4.99K_0402_1%
4.99K_0402_1%
Place all these components close to GPU (Within 25mm) and keep all component close to each other
_
B
_
B
_
B
D
O
D
O
L
C
L
C
L
C
L
C
A
R
A
R
A
C
A
C
S
C
S
C
K
C
K
C
E
W
E
W
1 2
BA2 <19> BA0 <19> BA1 <19>
TB0 <19> TB1 <19>
KB0 <19> KB0# <19>
KB1 <19> KB1# <19>
SB0# <19> SB1# <19>
SB0# <19> SB1# <19>
B0#_0 <19>
B1#_0 <19>
EB0 <19> EB1 <19>
B0# <19> B1# <19>
1 2
B[0..15]
MA
MB#[0..7]
DQ
B[0..7]
QS
B#[0..7]
QS
36
VGA@
36
VGA@
V
V
R
R
10_0402_1%
10_0402_1%
VGA@
VGA@
V
V
C
C
120P_0402_50V9
120P_0402_50V9
158
158
12
V
V
70
70
R
R
1 2
51.1_0402_1%
51.1_0402_1%
E
A
B[0..15] <19>
M
MB#[0..7] <19>
Q
D
B[0..7] <19>
S
Q
S
B#[0..7] <19>
Q
VGA@
VGA@
R
AM_RST# <19>
D
PS_3[ 2 ] PS_3[ 1]PS_3[ 3 ] R_pu R_pd
RV27
0
1 0
1
1
RV20
4.53K
0
3.4K
RV20
2K
RV27
10K
e
e
curity Classification
curity Classification
curity Classification
e
S
S
S
s
sued Date
sued Date
sued Date
s
s
I
I
I
H
H
IS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFI DENTIAL
IS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFI DENTIAL
IS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFI DENTIAL
H
T
T
T AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
A
B
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
C
0
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
2
2
2
o
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
C
C
C
e
ciphered Date
ciphered Date
ciphered Date
e
e
D
D
D
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
C
C
i
i
i
tle
tle
tle
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet
D
Date: Sheet
C
M Interface
M Interface
M Interface
E
E
E
M
M
M
A
A
A
-9868P
-9868P
-9868P
L
L
L
E
7 4
f
7 4
f
7 4
f
1
1
o
o
1
o
.
.
0
0
0
.
1
1
1
2Thursday, May 16, 2013
2Thursday, May 16, 2013
2Thursday, May 16, 2013
Page 18
CyberForum.ru
A
UV
UV
1G
1G
PART 6 0F 9
PART 6 0F 9
39
AB
GND
3
9
E
GND
3
4
F
GND
3
9
F
GND
3
3
G
GND
4
3
G
GND
1
3
H
GND
4
3
H
GND
3
9
H
GND
3
1
J
1 1
2 2
3 3
4 4
A
GND
3
4
J
GND
1
3
K
GND
4
3
K
GND
9
3
K
GND
3
1
L
GND
4
3
L
GND
4
3
M
GND
3
9
M
GND
3
1
N
GND
4
3
N
GND
1
3
P
GND
4
3
P
GND
3
9
P
GND
3
4
R
GND
1
3
T
GND
4
3
T
GND
3
9
T
GND
3
1
U
GND
3
4
U
GND
4
3
V
GND
9
3
V
GND
1
3
W
GND
3
4
W
GND
3
4
Y
GND
9
3
Y
GND
GND
1
5
F
GND
1
7
F
GND
9
1
F
GND
1
2
F
GND
2
3
F
GND
2
5
F
GND
7
2
F
GND
9
2
F
GND
3
1
F
GND
3
3
F
GND
7
F
G
9
F
G
2
G
G
6
G
G
9
H
G
2
J
G
2
7
J
GND
6
J
G
8
J
G
1
4
K
GND
7
K
G
1
1
L
GND
1
7
L
GND
2
L
G
2
2
L
GND
2
4
L
GND
6
L
G
7
1
M
GND
2
2
M
GND
2
4
M
GND
1
6
N
GND
1
8
N
GND
N
2
G
N
1
2
GND
N
3
2
GND
N
6
2
GND
N
6
G
R
1
5
GND
R
7
1
GND
R
2
G
R
2
0
GND
R
2
2
GND
R
2
4
GND
R
7
2
GND
R
6
G
T
1
1
GND
T
3
1
GND
T
6
1
GND
T
8
1
GND
T
21
GND
T
3
2
GND
T
6
2
GND
U
1
5
GND
U
7
1
GND
U
2
GND
U
2
0
GND
U
22
GND
U
2
4
GND
U
2
7
GND
U
6
GND
V
1
1
GND
V
1
6
GND
V
1
8
GND
V
2
1
GND
V
3
2
GND
V
2
6
GND
W
2
G
W
6
G
Y
1
5
GND
Y
1
7
GND
Y
0
2
GND
Y
2
2
GND
Y
2
4
GND
Y
2
7
GND
GND
ND ND ND ND ND ND
ND ND
ND
ND
ND
ND
ND
ND
ND
ND ND
VSS_MECH VSS_MECH VSS_MECH
SUN-PRO M2_FCBGA962VGA@
SUN-PRO M2_FCBGA962VGA@
G GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
GND GND GND GND GND G GND G GND GND GND GND GND GND GND GND
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND G G G GND GND G GND GND
B
A
3
ND
7
A3 A
16
A
A
18
A
A
2
A
A
21
A
A
23
A
A
26
A
28
AA
6
AA A
12
B
15
AB A
17
B
A
20
B
A
22
B
AB
24
AB
27
AC
11
AC
13
AC
16
AC18
2
AC AC21
23
AC
26
AC
28
AC
6
AC
15
AD
17
AD
20
AD
D
22
A
24
AD
D
27
A
D
9
A
E
2
A
6
E
A
F
10
A
16
F
A
18
F
A
21
F
A
17
G
A
G
2
A
G
20
A
G
6
A
G
9
A
H
21
A
0
J1
A
1
J1
A
J2
A
ND
J2
8
A
J6
A
ND
K
11
A
31
K
A
7
K
A
11
L
A
L
14
A
17
L
A
L
2
A
L
20
A
23
L
A
26
L
A
32
L
A
L
6
A
L
8
A
11
M
A
31
M
A
9
M
A
N
11
A
N
2
A
N
30
A
6
N
A
8
N
A
11
P
A
P
7
A
P
9
A
R
5
A
1
1
B
3
1
B
1
5
B
7
1
B
9
1
B
1
2
B
2
3
B
2
5
B
2
7
B
9
2
B
3
1
B
3
3
B
7
B
9
B
ND
1
C
ND
9
3
C
ND
5
3
E
5
E
1
1
F
ND
1
3
F
22
G
A
NC
9
3
A
1
W
A
39
W
A
B
S
S
S
e
e
curity Classification
ecurity Classification
curity Classification
I
I
I
s
s
s
T
T
T
H
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
+
.8VGS
1
(DP_VDDR: 1.8V@ 20mA)
sued Date
sued Date
sued Date
C
D
1F
1F
UV
UV
A
24
N
NC
A
24
P
NC
A
25
P
NC
A
P26
NC
A
U28
NC
A
V
29
NC
A
20
P
NC
A
21
P
NC
A
22
P
NC
A
23
P
NC
A
18
U
NC
A
V19
NC
A
H
34
DP_VDDR
A
J3
4
DP_VDDR
A
F
34
DP_VDDR
A
G
34
DP_VDDR
A
M
37
DP_VDDR
A
L
38
DP_VDDR
A
M
32
DP_VDDR
A
W
28
NC
A
W
18
NC
A
M
39
DP_CALR
2
2
2
0
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
P
P
ART 8 0F 9
ART 8 0F 9
DP_VDDR DP_VDDC
DP_VDDR DP_VDDC
DP GND
DP GND
CALIBRATION
CALIBRATION
SUN-PRO M2_FCBGA962VGA@
SUN-PRO M2_FCBGA962VGA@
C
C
C
o
o
mpal Secret Data
ompal Secret Data
mpal Secret Data
D
D
D
e
e
ciphered Date
ciphered Date
ciphered Date
e
DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC
DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR
D
A
P
31
A
P
32
A
33
N
A
33
P
A
33
L
A
33
M
A
K
33
A
K
34
A
N
31
A
P
13
NC
A
T
13
NC
A
14
P
NC
A
15
P
NC
A
N
27
A
P
27
A
P
28
A
W
24
A
26
W
A
29
N
A
29
P
A
30
P
A
30
W
A
32
W
A
N
17
A
P16
A
P
17
A
W
14
A
W
16
A
N
19
A
P
18
A
P
19
A
W
20
A
22
W
A
N
34
A
39
P
A
39
R
A
37
U
A
39
F
A
39
H
A
39
K
A
34
L
A
27
V
A
28
R
A
17
V
A
18
R
A
38
N
A
35
M
A
32
N
(
DP_VDDC: 0.95V@ 20mA)
T
T
i
Title
tle
tle
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
u
stom
stom
stom
u
u
Date: S heet
Date: S heet
Date: S heet
.95VGS
+0
C
C
C
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
P
P
P
W
W
R_GND
R_GND
R_GND
W
L
L
L
A
-9868P
-9868P
-9868P
A
A
E
1
1
1
.
0
0
0
.
.
o
o
o
f
f
18 42Thursday, May 16, 2013
18 42Thursday, May 16, 2013
18 42Thursday, May 16, 2013
E
f
Page 19
CyberForum.ru
5
4
3
2
1
CHANNEL B: 512MB/1024MB DDR3
6
V
U
U
V
M
B0
A
M
B1
A
M
A
B2
M
A
B3
M
B4
A
M
B5
A
M
A
B6
M
A
B7
M
B8
A
M
B9
A
M
B10
A
M
B11
A
M
AB12
M
B13
A
M
B14
A
B15
A
M
TB0
B0#
B2 B0
MB#2 MB#0
B#2 B#0
AM_RST#
6
M8
R
EFCA
V
H1
EFDQ
VR
N
3
0
A
P
7
1
A
3
P
2
A
2
N
3
A
8
P
4
A
P
2
5
A
R
8
6
A
R
2
7
A
T
8
8
A
3
R
9
A
L7
0/AP
1
A
R7
1
1
A
N7
1
2
A
T3
3
1
A
T7
4
1
A
M7
5/BA3
1
A
M2
0
A
B
N8
A
1
B
M3
2
A
B
J
7
K
C
7
K
K
C
K9
E/CKE0
K
C
K1
T/ODT0
D
O
L2
S
/CS0
C
3
J
S
A
R
3
K
S
A
C
3
L
E
W
F3
Q
SL
D
C7
Q
SU
D
E7
L
M
D
D3
M
U
D
3
G
SL
Q
D
7
B
SU
Q
D
2
T
E
SET
R
L8
/ZQ0
Q
Z
J1
/ODT1
C
N
1
L
/CS1
C
N
J9
C
/CE1
N
L9
C
ZQ1
N
6
-BALL
9
9
-BALL
6
SDRAM DDR3
SDRAM DDR3
K4W1G1646G-BC11_FBGA96
K4W1G1646G-BC11_FBGA96
E3
D
B17
M
L0
Q
D
F7
M
D
B19
L1
Q
D
F2
D
B16
M
L2
Q
D
F8
M
B22
D
Q
L3
D
H3
B20
D
M
Q
L4
D
H8
M
DB21
Q
L5
D
G2
M
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
V V V V V V V V V
D
V
D
V
D
V
D
V
D
V
D
V
D
V
D
V
D
V
V V V V V V V V V V V V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
B18
L6
H7
M
D
B23
L7
D7
M
B1
D
U0
C3
M
B7
D
U1
C8
B2
D
M
U2
C2
B4
D
M
U3
A7
B3
D
M
U4
A2
M
D
B5
U5
B8
B0
D
M
U6
A3
B6
D
M
U7
1
.5VGS
+
B2
D
D
D9
D
D
G7
D
D
K2
D
D
K8
D
D
N1
D
D
N9
D
D
R1
D
D
R9
D
D
1
.5VGS
+
A1
DQ
A8
DQ
C1
DQ
C9
DQ
D2
DQ
E9
DQ
F1
DQ
H2
DQ
H9
DQ
A9
S
S
B3
S
S
E1
S
S
G8
S
S
J2
S
S
J8
S
S
M1
S
S
M9
S
S
P1
S
S
P9
S
S
T1
S
S
T9
S
S
B1
SQ
B9
SQ
D1
SQ
D8
SQ
E2
SQ
E8
SQ
F9
SQ
G1
SQ
G9
SQ
@
@
V
REFC_A3_B
+
C C C
O C R C W
243_0402_1%
243_0402_1%
L L K
S A A
KB1<17> KB1#<17>
EB1<17>
TB1<17>
D
B1#_0<17> SB1#<17> SB1#<17>
E
R
R
V
V
VGA@
VGA@
B1#<17>
82
82
5
5
UV
UV
V
REFC_A1_B
+
D D
D
B[0..63]<17>
M
A
B[15..0]<17>
M
MB#[7..0]<17>
Q
D
B[7..0]<17>
S
Q
S
B#[7..0]<17>
Q
C C
C
LKB0
R
R
78 40.2_0402_1%
78 40.2_0402_1%
V
V
C
L
KB0#
R
R
79 40.2_0402_1%
79 40.2_0402_1%
V
V
1 2
C
L
KB1
V
84 40.2_0402_1%
84 40.2_0402_1%
V
R
R
1 2
C
KB1#
L
V
V
85 40.2_0402_1%
85 40.2_0402_1%
R
R
1
1
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
M
D
B[0..63]
M
B[15..0]
A
B B
C C C
O C R C W
R
AM_RST#<17>
D
243_0402_1%
243_0402_1%
B
L
KB0<17> KB0#<17>
L
EB0<17>
K
D S
B0#_0<17>
A
SB0#<17> SB0#<17>
A
E
RV
RV
VGA@
VGA@
D
MB#[7..0]
Q
Q
S
B[7..0]
Q
B#[7..0]
S
2
2
VGA@
VGA@
12
160
160
V
V
C
C
0.01U_0402_16V7K
0.01U_0402_16V7K
VGA@
VGA@
1
161
161
V
V
C
C
0.01U_0402_16V7K
0.01U_0402_16V7K
2
M8
V
EFCA
R
H1
V
R
EFDQ
N
3
M
B0
A
A
0
P
7
M
B1
A
A
1
P
3
M
A
B2
A
2
N
2
M
A
B3
A
3
P
8
M
B4
A
A
4
2
P
M
B5
A
A
5
8
R
M
A
B6
A
6
2
R
M
A
B7
A
7
8
T
M
B8
A
A
8
3
R
M
B9
A
A
9
L7
M
B10
A
A
0/AP
1
R7
M
B11
A
A
1
1
N7
M
B12
A
A
2
1
T3
M
B13
A
A
3
1
T7
M
B14
A
A
4
1
M7
B15
A
M
A
1
5/BA3
M2
BA0<17>
_ _
BA1<17> BA2<17>
_
TB0<17>
B0#<17>
Q Q
D
Q
D
Q
Q
Q
12
80
80
S
B3 B1
S
MB#3 MB#1
S
B#3
S
B#1
B
A
0
N8
B
1
A
M3
B
2
A
J
7
C
K
K
7
C
K
K9
C
E/CKE0
K
K1
O
D
T/ODT0
L2
C
/CS0
S
J
3
R
A
S
K
3
C
S
A
L
3
W
E
F3
D
SL
Q
C7
D
Q
SU
E7
D
M
L
D3
D
M
U
G
3
D
Q
SL
B
7
D
Q
SU
T
2
R
SET
E
L8
Z
Q
/ZQ0
J1
N
C
/ODT1
L
1
N
C
/CS1
J9
N
C
/CE1
L9
N
C
ZQ1
9
9
6
-BALL
-BALL
6
SDRAM DDR3
SDRAM DDR3
K4W1G1646G-BC11_FBGA96
K4W1G1646G-BC11_FBGA96
E3
D
B24
M
D
Q
L0
F7
B26
D
M
D
Q
L1
F2
M
B30
D
D
Q
L2
F8
M
B31
D
D
Q
L3
H3
M
B25
D
D
L4
Q
H8
M
B27
D
D
L5
Q
G2
M
D
B28
D
L6
Q
H7
M
D
B29
D
L7
Q
D7
B15
D
M
D
Q
U0
C3
B10
D
M
D
Q
U1
C8
M
B14
D
D
Q
U2
C2
M
B11
D
D
U3
Q
A7
D
B13
M
D
U4
Q
A2
M
D
B9
D
U5
Q
B8
D
B12
M
D
U6
Q
A3
D
B8
M
D
U7
Q
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
DQ
D
V
DQ
D
V
DQ
D
V
DQ
D
V
DQ
D
V
D
DQ
V
D
DQ
V
DQ
D
V
DQ
D
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
SQ
S
V
SQ
S
V
S
SQ
V
S
SQ
V
SQ
S
V
SQ
S
V
S
SQ
V
S
SQ
V
SQ
S
.5VGS
1
+
B2 D9 G7 K2 K8 N1 N9 R1 R9
1
.5VGS
+
A1 A8 C1 C9 D2 E9 F1 H2 H9
A9
S
B3
S
E1
S
G8
S
J2
S
J8
S
M1
S
M9
S
P1
S
P9
S
T1
S
T9
S
B1 B9 D1 D8 E2 E8 F9 G1 G9
@
@
S
upported Memory Configurations: Up to 4 Gbit/part for DDR3.
V
REFC_A2_B
+
243_0402_1%
243_0402_1%
R
R
VGA@
VGA@
B
_BA0
B
_
BA1
B
_
BA2
C
KB0
L
C
L
KB0#
C
EB0
K
O
D
C
B0#_0
S
A
SB0#
R
C
A
SB0#
E
W
S
Q
S
Q
D
Q
D
Q
S
Q
S
Q
D
R
1
81
81
V
V
2
B
_
B
_
B
_
S
Q
S
Q
D
Q
D
Q
S
Q
S
Q
D
R
12
BA0 BA1 BA2
B4 B7
MB#4 MB#7
B#4 B#7
AM_RST#
M
B0
A
M
B1
A
M
A
B2
M
A
B3
M
B4
A
M
B5
A
M
A
B6
M
A
B7
M
B8
A
M
B9
A
M
B10
A
M
B11
A
M
AB12
M
B13
A
M
AB14
B15
A
M
U
U
7
7
V
V
M8
R
EFCA
V
H1
EFDQ
VR
N
3
0
A
7
P
1
A
3
P
2
A
2
N
3
A
P
8
4
A
P
2
5
A
R
8
6
A
2
R
7
A
8
T
8
A
3
R
9
A
L7
1
0/AP
A
R7
1
1
A
N7
2
1
A
T3
3
1
A
T7
4
1
A
M7
5/BA3
1
A
M2
A
0
B
N8
A
1
B
M3
A
2
B
7
J
K
C
7
K
K
C
K9
K
E/CKE0
C
K1
D
T/ODT0
O
L2
C
S
/CS0
J
3
R
A
S
K
3
C
S
A
L
3
W
E
F3
Q
SL
D
C7
SU
Q
D
E7
L
M
D
D3
U
M
D
3
G
Q
SL
D
7
B
Q
SU
D
2
T
E
SET
R
L8
Q
/ZQ0
Z
J1
/ODT1
C
N
1
L
C
/CS1
N
J9
C
/CE1
N
L9
C
ZQ1
N
9
9
6
6
-BALL
-BALL
SDRAM DDR3
SDRAM DDR3
K4W1G1646G-BC11_FBGA96
K4W1G1646G-BC11_FBGA96
E3
M
D
L0
Q
D
L1
Q
D
Q
L2
D
Q
L3
D
Q
L4
D
QL5
D
L6
Q
D
L7
Q
D
U0
Q
D
Q
U1
D
Q
U2
D
Q
U3
D
Q
U4
D
Q
U5
D
U6
Q
D
U7
Q
D
D
V
D
V
D
V
D
V
D
V
D
V
D
V
D
V
D
V
DQ
D
V
DQ
D
V
DQ
D
V
D
DQ
V
DQ
D
V
D
DQ
V
D
DQ
V
D
DQ
V
D
DQ
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
SQ
V
S
SQ
V
S
SQ
V
SQ
S
V
S
SQ
V
SQ
S
V
S
SQ
V
S
SQ
V
SQ
S
V
B33
F7
M
B37
D
F2
M
B35
D
F8
M
B39
D
H3
M
B32
D
H8
M
D
B36
G2
M
D
B34
H7
M
B38
D
D7
B58
D
M
C3
B60
D
M
C8
M
B56
D
C2
B62
D
M
A7
D
B57
M
A2
M
D
B63
B8
M
B59
D
A3
D
B61
M
1
.5VGS
+
B2
D
D9
D
G7
D
K2
D
K8
D
N1
D
N9
D
R1
D
R9
D
1
.5VGS
+
A1 A8 C1 C9 D2 E9 F1 H2 H9
A9
S
B3
S
E1
S
G8
S
J2
S
J8
S
M1
S
M9
S
P1
S
P9
S
T1
S
T9
S
B1 B9 D1 D8 E2 E8 F9 G1 G9
@
@
V
REFC_A4_B
+
243_0402_1%
243_0402_1%
R
R
V
V
VGA@
VGA@
B
_
B
_
B
_
C
LKB1
C
L
C
KEB1
O C
S
A
R
C
A
W
Q Q
D
Q
D
QMB#5
Q Q
D
R
12
83
83
M M M M M M M M M M M M M M M
M
BA0 BA1 BA2
KB1#
D
TB1 B1#_0
SB1#
SB1#
E
B1#
S
B6
S
B5
MB#6
B#6
S S
B#5
AM_RST#
A A A A A A A A A A A A AB12 A AB14
A
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
B13
B15
V
V
8
8
U
U
M8
V
R
EFCA
H1
V
EFDQ
R
N
3
A
0
7
P
A
1
P
3
A2
2
N
A
3
P
8
A4
2
P
A
5
8
R
A
6
2
R
A7
8
T
A
8
3
R
A
9
L7
0/AP
A1
R7
A
1
1
N7
A
2
1
T3
A
1
3
T7
A
4
1
M7
A
5/BA3
1
M2
0
BA
N8
1
BA
M3
B
A
2
7
J
CK
K7
CK
K9
E/CKE0
CK
K1
O
T/ODT0
D
L2
S
/CS0
C
3
J
A
S
R
3
K
A
S
C
3
L
E
W
F3
D
Q
SL
C7
D
SU
Q
E7
D
M
L
D3
D
U
M
G
3
D
Q
SL
B7
SU
DQ
T
2
R
SET
E
L8
Z
/ZQ0
Q
J1
N
/ODT1
C
L
1
N
C
/CS1
J9
N
/CE1
C
L9
N
ZQ1
C
6
-BALL
-BALL
6
9
9 SDRAM DDR3
SDRAM DDR3
K4W1G1646G-BC11_FBGA96
K4W1G1646G-BC11_FBGA96
E3
D
B49
D D D D DQ D D D
D D D D D D D D
V V V V V V V V V
V V V V V V V V V
M
L0
Q
F7
B53
D
M
L1
Q
F2
D
B51
M
L2
Q
F8
B55
D
M
L3
Q
H3
B48
D
M
L4
H8
D
B54
M
L5
Q
G2
B50
D
M
L6
Q
H7
B52
D
M
L7
Q
D7
B47
D
M
Q
U0
C3
D
B43
M
Q
U1
C8
B45
D
M
Q
U2
C2
D
B42
M
Q
U3
A7
D
B44
M
U4
Q
A2
B40
D
M
U5
Q
B8
B46
D
M
Q
U6
A3
B41
D
M
Q
U7
1
.5VGS
+
B2
V
D
D
D9
V
DD
G7
V
D
D
K2
V
D
D
K8
V
D
D
N1
V
D
D
N9
V
D
D
R1
V
D
D
R9
V
D
D
1
.5VGS
+
A1
D
DQ
A8
D
DQ
C1
DQ
D
C9
DQ
D
D2
D
DQ
E9
DQ
D
F1
DQ
D
H2
D
DQ
H9
D
DQ
A9
V
S
S
B3
V
S
S
E1
V
S
S
G8
V
S
S
J2
V
S
S
J8
V
S
S
M1
V
S
S
M9
V
S
S
P1
V
S
S
P9
V
S
S
T1
V
S
S
T9
V
S
S
B1
S
SQ
B9
S
SQ
D1
SQ
S
D8
SQ
S
E2
SQ
S
E8
SQ
S
F9
SQ
S
G1
SQ
S
G9
SQ
S
@
@
VGA@
VGA@
V
V
88
88
R
R
4.99K_0402_1%
4.99K_0402_1%
VGA@
VGA@
R
R
V
92
92
V
4.99K_0402_1%
4.99K_0402_1%
188
188
1
V
V C
C
2
1U_0402_6.3V6K
1U_0402_6.3V6K
G
G
A@
A@
V
V
ompal Secret Data
ompal Secret Data
ompal Secret Data
C
C
C
1
.5VGS
+
1
2
12
G
G
V
V
Deciphered Date
Deciphered Date
Deciphered Date
2
REFC_A3_B
V
+
1
164
164 V
V C
C
2
A@
A@
0.1U_0402_16V7K
0.1U_0402_16V7K
1
.5VGS
+
close to UV9 UV 10
194
194
195
193
193 V
V C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
G
G
V
V
195
196
196
1
1
V
V C
C
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
V
V
A@
A@
G
G
A@
A@
1
1
V
V
V
V
C
C
C
C
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
G
G
G
A@
A@
A@
A@
G
V
V
V
V
i
i
tle
tle
tle
i
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C 1
C 1
C 1
Date: Sheet of
Date: Sheet of
Date: Sheet of
.5VGS
1
B B
.5VGS
1
+
167
167
168
166
166 V CV
C
A A
c
lose to UV7 UV8
0.1U_0402_16V7K
0.1U_0402_16V7K
V
V
G
G
168
1
1
V
V
V
V
C
C
C
C
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
V
V
G
G
G
G
A@
A@
V
V
A@
A@
5
170
170
169
169
1
1
V
V C
C
CV
CV
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
G
G
A@
A@
V
V
A@
A@
VG
VG
172
172
171
171
1
V
V C
C
2
0.1U_0402_16V7K
0.1U_0402_16V7K
V
V
G
A@
A@
G
173
173
1
1
1
V
V
V
V
C
C
C
C
close to UV9 UV 10
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
G
G
A@
A@
A@
A@
V
V
A@
A@
G
G
V
V
VGA@
VGA@
R
R
86
86
V
V
4.99K_0402_1%
4.99K_0402_1%
VGA@
VGA@
V
V
90
90
R
R
4.99K_0402_1%
4.99K_0402_1%
+
12
1
5mil 15mil 15mil 15mil
REFC_A1_B
V
+
1
1
162
162 V
V C
C
2
2
V
V
G
A@
A@
G
0.1U_0402_16V7K
0.1U_0402_16V7K
.5VGS
1
+
C
C V
V 179 22U_0603_6.3V6M
179 22U_0603_6.3V6M
1
2
G
A@
A@
G
V
V
4
VGA@
VGA@
R
R
87
87
V
V
4.99K_0402_1%
4.99K_0402_1%
VGA@
VGA@
R
R
91
91
V
V
4.99K_0402_1%
4.99K_0402_1%
.5VGS
1
+
1
2
REFC_A2_B
V
+
12
1
163
163 V
V C
C
2
V
V
A@
A@
G
G
0.1U_0402_16V7K
0.1U_0402_16V7K
close to UV7 UV 8
.5VGS
1
+
186
184
184
183
183
1
V
V
V
V
C
C
C
C
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
G
G
V
V
V
V
G
G
A@
A@
ecurity Classification
ecurity Classification
ecurity Classification
S
S
S
s
s
sued Date
sued Date
sued Date
s
I
I
I
H
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
T
T
T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
186
187
185
185
1
V
V C
C
2
1U_0402_6.3V6K
1U_0402_6.3V6K
A@
A@
G
G
V
V
187
1
1
2
A@
A@
1
V
V
V
V
C
C
C
C
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
V
V
V
V
G
G
A@
A@
A@
A@
G
G
0
0
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
2
2
2
1
.5VGS
+
12
VGA@
VGA@
R
R
89
89
V
V
4.99K_0402_1%
4.99K_0402_1%
1
VGA@
VGA@
93
93
V
V
R
R
4.99K_0402_1%
4.99K_0402_1%
2
197
197
198
198
1
1
V
V
V
V C
C
C
C
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
A@
A@
G
G
V
V
V
V
A@
A@
G
G
o
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
C
C
C
V
V
V
A
A
A
L
L
L
REFC_A4_B
V
+
1
165
165 V
V C
C
2
V
V
G
A@
A@
G
0.1U_0402_16V7K
0.1U_0402_16V7K
R
R
R
AM Channel B
AM Channel B
AM Channel B
-9868P
-9868P
-9868P
1
9 4
9 4
9 4
1
1
1
.
.
.
2Thursday, May 16, 2013
2Thursday, May 16, 2013
2Thursday, May 16, 2013
0
0
0
Page 20
CyberForum.ru
5
4
3
2
1
E
_LCD_TXOUT0+_R
E
DP
_LCD_TXOUT0+_R<6>
E
_LCD_TXOUT0-_R<6>
DP
E
_LCD_TXOUT1+_R<6>
DP
E
DP
_LCD_TXOUT1-_R<6>
E
DP
D D
C C
B B
STARC_111H30-000000-G4-R
STARC_111H30-000000-G4-R
_LCD_TXOUT2+_R<6>
E
_LCD_TXOUT2-_R<6>
DP
L
TXCLK+<6>
CD_
L
TXCLK-<6>
CD_
E
DP
_LVDS_CLK<6>
E
_LVDS_DATA<6>
DP
J
J
L
LVDS
VDS
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
0
1
0
1
1
1
1
1
2
1
2
1
1
3
3
1
1
4
4
1
1
5
5
1
1
6
6
1
1
7
7
1
8
1
8
1
9
1
9
1
0
2
0
2
1
2
1
2
2
2
2
2
2
3
3
2
2
4
4
2
5
2
5
2
2
6
6
2
7
2
7
2
8
2
8
2
9
2
9
2
0
3
0
3
31
N
D
G
32
N
D
G
33
N
D
G
34
N
D
G
35
N
D
G
@
@
+
VS_LVDS_TOUCH
5
U
B20_N4_R
S
U
SB20_P4_R
B
K
OFF#
I
NT_MIC_DATA
I
NT_MIC_CLK
U
S
B20_P3_R
U
S
B20_N3_R
+
3
VS_LVDS_CAM
+
CD_VDD
L
+
3VS
E
DP
_LVDS_CLK
E
DP
_LVDS_DATA
E
DP
_LCD_TXOUT0-_R
E
DP
_LCD_TXOUT0+_R
E
_LCD_TXOUT1-_R
DP
E
DP_LCD_TXOUT1+_R
E
_LCD_TXOUT2-_R
DP
E
_LCD_TXOUT2+_R
DP
L
TXCLK-
CD_
L
TXCLK+
CD_
L
E
D_PWM
B
K
OFF#_R
DP
E
_LCD_TXOUT0-_R
DP
E
_LCD_TXOUT1+_R
DP
E
DP_LCD_TXOUT1-_R
E
DP
_LCD_TXOUT2+_R
E
DP
_LCD_TXOUT2-_R
L
CD_
L
CD_TXCLK-
E
DP
E
DP
@
@
1 2
3
3
89 0_0603_5%
89 0_0603_5%
R
R
I
f it's EPD, they're become
LCD_TXOUT2+_R = EDP_TX0+
TXCLK+
_LVDS_CLK
_LVDS_DATA
+
L
+
L
CD_INV
LCD_TXOUT2-_R = EDP_TX0­LCD_TXOUT1+_R = EDP_TX1+ LCD_TXOUT1-_R = EDP_TX1­LVDS_CLK = EDP_AUXP LVDS_DATA = EDP_AUXN
1 2
@
@
R
R
3
3
90 0_0603_5%
90 0_0603_5%
I
rush=1.5A
CD_VDD
E
DP_LVDS_HPD <6>
I
rush=1.5A
60mils
I
_MIC_DATA <26>
NT
I
_MIC_CLK <26>
NT
6
0mils
+
5
VS
20mils
+
VS
3
20mils
+
3
VS
pin1-4 Touch function for panel pin5-10 For Webcam with single or dual MIC pin11-30 For LVDS or EDP panel
LCD_VDD
Need check eDP&LVDS both 3V power rail.
U
B20_P3_R
S
I
_MIC_DATA
NT
LCD Control
+
3
VS
W=60mils
1.5A
+
CD_VDD_SS
L
1
C
C
1
1
7
7
1500P_0402_50V7K
1500P_0402_50V7K
2
2
2
9
9
D
D
4
4
+
VS
3
5
b
us
V
6
6
SC300001400
SC300001400
1
1
6
6
U
U
5
V
4
S
APL3512ABI-TRG_SOT23-5
APL3512ABI-TRG_SOT23-5
L
ENVDD<6>
CD_
ESD@
ESD@
3
3
2
N
D
G
1
1
close to LVDS conn.
N
I
S
U
I
NT
V
B20_N3_R
S
_MIC_CLK
O
UT
N
G
E
1
2
D
3
N
12
12
1
1
R
R 100K_0402_5%
100K_0402_5%
1 2
+
L
CD_VDD
W
I rush=1.5A
=60mils
+
L
CD_INV
C
C
2
2
@
@
E
MI@
MI@
E
LCD_INV
B
EMI@
1
.5A
1
2
2
2
1U_0402_25V6
1U_0402_25V6
.
. 0
0
EMI@
2
2
L
L
MA-L11-201209-221LMA30T_0805
MA-L11-201209-221LMA30T_0805
FB
FB
12
+
C
armera & Touch Screen
D
D
6
L
INT_PWM<6>
CD_
CAM_EMI@
CAM_EMI@
U
S
B20_P3<7>
U
S
B20_N3<7>
3
2
CM-2012-900T_0805
CM-2012-900T_0805
W
W
Reserve for EMI request
A A
U
S
B20_N4<7>
U
S
B20_P4<7>
5
@TOUCH_EMI@
@TOUCH_EMI@
3
2
W
CM-2012-900T_0805
CM-2012-900T_0805
W
R
eserve for EMI request
3
2
TOUCH_EMI@
TOUCH_EMI@
1
04 0_0402_5%
04 0_0402_5%
1
1
R
R
3
2
TOUCH_EMI@
TOUCH_EMI@
1 2
R
R
1
1
05 0_0402_5%
05 0_0402_5%
L
L
3
3
4
U
S
4
1
2
L
L
4
4
4
1
B20_P3_R
1
U
B20_N3_R
S
4
U
B20_N4_R
S
1
U
B20_P4_R
S
4
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
ssu
ed Date
ed Date
ed Date
ssu
ssu
T
T
T
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
6
2
2
2
3
12
RB
RB
751V40_SC76-2
751V40_SC76-2
C
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
0
o
D
D
D
12
1
1
R
R 47K_0402_5%
47K_0402_5%
e
ciphered Date
ciphered Date
ciphered Date
e
e
31
31
L
E
D_PWM
2
B
OFF#_R
K
Reserve for eDP panel potential issue
2
1
EDP@
EDP@
1
1
03 0_0402_5%
03 0_0402_5%
R
R
1 2
1
1
5 RB751V40_SC76-2
5 RB751V40_SC76-2
D
D
LVDS@
LVDS@
1
R
R
13
13
1
1
10K_0402_5%
10K_0402_5%
2
T
T
T
i
tle
tle
tle
i
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
+
3
VS
5
EDP@
EDP@
7
7
1
1
U
U
1
P
N
1
I
4
O
2
B
K
OFF#
2
N
I
G
3
SN74AHC1G08DCKR_SC70-5
SN74AHC1G08DCKR_SC70-5
1 2
1
47 0_0402_5%
47 0_0402_5%
1
R
R
LVDS@
LVDS@
C
C
C
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
L
L
L
V
V
DS/EDP W/ CAMERA
DS/EDP W/ CAMERA
DS/EDP W/ CAMERA
V
L
L
L
A
-9868P
-9868P
-9868P
A
A
1
L
CD_ENBKL <29,6>
B
K
OFF# <29>
2
2
o
o
2
o
0 4
f
f
0 4
f
0 4
1
1
1
.0
.0
.0
2Thursday, May 16, 2013
2Thursday, May 16, 2013
2Thursday, May 16, 2013
Page 21
CyberForum.ru
5
4
3
2
1
R
R
P
Y3
Y3
P
1 8 2 7 3 4 5
499_8P4R_1%
499_8P4R_1%
Y4
Y4
P
P
R
R
1 8 2 3 6 4 5
499_8P4R_1%
499_8P4R_1%
+
VS
5
+HDMI_5V_OUT
H
DM
5
1
U
U
Y
Y
#
P
E O
A2Y
G
74AHCT1G125GW_SOT353-5
74AHCT1G125GW_SOT353-5
3
H
V
IN = 5V, IOUT = 0.5A , RDS(ON) TYP=95m ; MAX=115m
Current Limit: TYP=0.8A ; MAX=1A
0.1U_0402_10V7K
0.1U_0402_10V7K
6
7
Q
Q
2
G
G
2
R
R
1
1
Y
Y
1 2
I_HPD_U
1K_0402_5%
1K_0402_5%
1
1
4
H
DM
I_HPD
+
VS
3
12
Y
Y
R
R
2.2K_0402_5%
2.2K_0402_5%
DMI POWER CIRCUIT
+
HDMI_5V_OUT
1
18
18
Y
Y
C
C
2
+
13
D
D
Y
3
3
Y
S
S
2N7002KW_SOT323-3
2N7002KW_SOT323-3
# A Y
H
I_HPD_C
DM
2
4
4
2
2
Y
Y
Y
R
R
100K_0402_5%
100K_0402_5%
3
3
H
I_HPD
DM
HDM
I_5V_OUT
T
T
tle
itle
i
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Y
C
C
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1 2
H
I_HPD <6,8>
DM
U
U
Y
Y
2
2
1
O
I
T
U
2
3
N
G
N
D
F
E
G
L
N
AP2151DWG-7_SOT25-5
AP2151DWG-7_SOT25-5
S
A00006H000
H
H
DM
I_HPD_C
H
I_SDATA
DM
H
DM
I_SCLK
H
DM
I_R_CK-
H
I_R_CK+
DM
H
I_R_D0-
DM
H
DM
I_R_D0+
H
I_R_D1-
DM
H
DM
I_R_D1+
H
I_R_D2-
DM
H
DM
I_R_D2+
C
C
C
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
H
H
H
L
L
L
A
-9868P
-9868P
-9868P
A
A
D
D
D
D
OE
L
L L
L
H H
H
X Z
5
4
+
5
VS
MI Connector
HDM
HDM
I @
I @
J
J
19
P
_DET
H
18
V
5
+
17
C/CEC_GN D
D
D
16
D
A
S
15
C
L
S
14
served
e
R
13
C
E
C
12
-
K
C
11
K
_shield
C
10
K+
C
9
-
0
D
8
0
_shield
D
7
0
+
D
6
-
1
D
5
_shield
1
D
4
1
N
+
D
G
D
3
-
D
2
N
G
D
2 1
TYCO_2041343-1~D
TYCO_2041343-1~D
MI W/O CEC
MI W/O CEC
MI W/O CEC
N
_shield
D
2
G
D
N
+
D
2
G
D
2
2
2
1 4
1 42Thursday, May 16, 2013
1
1 4
23 22 21 20
1
1
1
.0
.0
o
o
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f
2Thursday, May 16, 2013
2Thursday, May 16, 2013
f
f
P
P
Y2
Y2
R
R
I
I
I
ssu
ssued Date
ed Date
ed Date
ssu
1 8 2 3 4 5
4.7K_8P4R_5%
4.7K_8P4R_5%
2
3 1
SGD
SGD
BSH111_SOT23-3
BSH111_SOT23-3
+3
VS
+
I_5V_OUT
HDM
D D
A
P
A
U_HDMI_CLK<6>
P
A
P
U_HDMI_DATA<6>
C C
L
L
1
EMI@
1
EMI@
Y
1 2
Y
Y
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
C
A
U_HDMI_CLK-<6>
P
A
PU_HDMI_CLK+<6>
A
U_HDMI_TX0-<6>
P
A
P
U_HDMI_TX0+<6>
B B
A
PU_HDMI_TX1-<6>
A
P
U_HDMI_TX1+<6>
A
P
U_HDMI_TX2-<6>
A
PU_HDMI_TX2+<6>
HDMI45@
HDMI45@
ZZ
ZZ
Z
H
DMI Royalty
A A
p
lease manually load
Z
RO0000003HM
HDM
I W/Logo + HDCP
I W/Logo + HDCP
HDM
HDMI W/O Logo: RO0000001HM HDMI W/Logo: RO0000002HM HDMI W/Logo + HDCP: RO0000003HM
C
2
1
Y
Y
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
C
C
1 2
5 0.1U_0402_16V7K
5 0.1U_0402_16V7K
Y
Y
C
C
2
1
Y
Y
3 0.1U_0402_16V7K
3 0.1U_0402_16V7K
C
C
2
1
7 0.1U_0402_16V7K
7 0.1U_0402_16V7K
Y
Y
C
C
1 2
Y
6 0.1U_0402_16V7K
6 0.1U_0402_16V7K
Y
C
C
2
1
Y
Y
9 0.1U_0402_16V7K
9 0.1U_0402_16V7K
C
C
1 2
Y
Y
8 0.1U_0402_16V7K
8 0.1U_0402_16V7K
C
C
H
DM
I_TXC-
H
DM
I_TXC+
H
I_TXD0-
DM
H
DM
I_TXD0+
H
I_TXD1-
DM
H
DM
I_TXD1+
H
DM
I_TXD2-
H
I_TXD2+
DM
Y
1
1
4
4
KINGCORE WCM-2012HS-900T
KINGCORE WCM-2012HS-900T
L
L
1
1
4
4
KINGCORE WCM-2012HS-900T
KINGCORE WCM-2012HS-900T
L
L
1
1
4
4
KINGCORE WCM-2012HS-900T
KINGCORE WCM-2012HS-900T
L
L
1
1
4
4
KINGCORE WCM-2012HS-900T
KINGCORE WCM-2012HS-900T
2
3
2
EMI@
2
EMI@
Y
Y
2
3
3
EMI@
3
EMI@
Y
Y
2
3
4
EMI@
4
EMI@
Y
Y
2
3
2
3
2
3
2
3
2
3
this virtual material to 45@ BOM
5
4
U_HDMI_CLK
A
P
U_HDMI_DATA
S
S
S
e
e
curity Classification
curity Classification
curity Classification
e
T
T
T
H
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
U_HDMI_CLK
P
7
A
U_HDMI_DATA
P
6
H
I_SCLK
DM
H
I_SDATA
DM
+
3
VS
2
3 1
SGD
SGD
Y
1
1
Y
Q
Q
BSH111_SOT23-3
BSH111_SOT23-3
2
2
Y
Y
Q
Q
2
2
2
0
12/09/27 2015/09/27
012/09/27 2015/09/27
12/09/27 2015/09/27
0
3
H
DM
I_SCLK
H
DM
I_SDATA
H
I_R_CK+
DM
H
DMI_R_CK-
H
I_R_D0+
DM
H
I_R_D0-
DM
H
DMI_R_D2+
H
I_R_D2-
DM
H
I_R_D1+
DM
H
I_R_D1-
DM
C
C
C
o
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
D
D
D
e
eciphered Date
ciphered Date
ciphered Date
e
Page 22
CyberForum.ru
5
D D
A
U_CRT_R
+
HDM
A
A
I_5V_OUT
P
U_CRT_G
P
PU_CRT_B
RT
RT
C
C
A
P
U_CRT_R<6>
A
U_CRT_G<6>
P
A
U_CRT_B<6>
P
C C
4
CRT_EMI@
CRT_EMI@
1 2
8 NB
8 NB
L
L
CRT_EMI@
CRT_EMI@
1
L
L
9 NB
9 NB
CRT_EMI@
CRT_EMI@
1
1
1
0 NBQ100505T-800Y_0402
0 NBQ100505T-800Y_0402
L
L
C
C
RT
RT
@
@
2
73
73
74
74
1
1
1
1 R
R
R
R
1
150_0402_1%
150_0402_1%
@
@
RT
@
@
RT
C
C
2
75
75 1
1 R
R
1 2
1
150_0402_1%
150_0402_1%
C
C
@
@
RT
RT
1
1
1
62
62
C
C
C
C
1
1
63
63
2
150_0402_1%
150_0402_1%
2P_0402_50V8C
2P_0402_50V8C
.
. 2
2
@
@
RT
RT
C
C
1
1
64
64
1
1
C
C
2
2
2P_0402_50V8C
2P_0402_50V8C
2P_0402_50V8C
2P_0402_50V8C
.
.
.
.
2
2
2
2
RT
RT
@
@
C
C
Q100505T-800Y_0402
Q100505T-800Y_0402
2
Q100505T-800Y_0402
Q100505T-800Y_0402
2
1
C
C
1
1
65
65
2
C
C
RT
RT
@
@
3
A
PU_CRT_R_L
A
P
U_CRT_G_L
A
P
C
C
1
1
C
C
C
C
1
1
66
66
67
67
1
1
2
2
2P_0402_50V8C
2P_0402_50V8C
2P_0402_50V8C
2P_0402_50V8C
.
.
.
.
2
2
2
2
C
C
RT
RT
@
@
U_CRT_B_L
RT
RT
@
@
2P_0402_50V8C
2P_0402_50V8C
.
. 2
2
2
+
HDM
U
E HDMI POWER
S
I_5V_OUT
A
PU_CRT_R_L
C
_DDC_DAT
RT
A
U_CRT_G_L
P
H
S
YNC
A
P
U_CRT_B_L
V
S
YNC
C
RT
_DDC_CLK
T
T
T
T
6
6
6
6
5 PAD
5 PAD
6 PAD
6 PAD
J
J
CRT
CRT
6
1
1 1 7
1
2 2 8
1
3 3 9
1
4 4
1
0
1
5 5
13-12201513CP
13-12201513CP
C-H_
C-H_
@
@
1
1
6
G
G
1
7
G
G
2
C
C
61
61
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
@
@
A
P
B B
A A
5
U_CRT_DATA<6>
A
P
U_CRT_CLK<6>
A
P
U_CRT_VSYNC<6>
A
U_CRT_HSYNC<6>
P
+
HDM
A
U_CRT_DATA
P
A
PU_CRT_CLK
A
U_CRT_VSYNC
P
A
P
U_CRT_HSYNC
I_5V_OUT
+
3
VS
+
3
VS
4
U
U
9
9
4
4
1
V
C
C_SYNC
2
V
C
C_VIDEO
7
V
C_DDC
C
10
D
D
C_IN1
11
D
D
C_IN2
13
S
Y
NC_IN1
15
S
Y
NC_IN2
6
G
D
N
TPD7S019-15DBQR_SSOP16
TPD7S019-15DBQR_SSOP16
+
I_5V_OUT
CRT@
CRT@
CRT@
8
B
P
Y
3
V
DEO1
I
4
V
DEO2
I
5
V
DEO3
I
D
D
S
Y
S
Y
S
S
S
e
ecurity Classification
e
T
T
T
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
9
DC_OUT1
12
D
C_OUT2
14
NC_OUT1
16
NC_OUT2
curity Classification
curity Classification
I
I
I
ssu
ssu
ed Date
ed Date
ed Date
ssu
CRT@
1 2
48 0.22U_0402_16V7K
48 0.22U_0402_16V7K
1
1
C
C
A
PU_CRT_R_L
A
P
A
P
V
S
YNC_R
H
S
YNC_R
2
2
2
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
3
U_CRT_G_L
U_CRT_B_L
R
R
2
62
6
R
R
6
3
3
6
4.7K_0402_5%
4.7K_0402_5%
CRT@
CRT@
1 2
CRT@
CRT@
1 2
C
C
C
HDM
1
1
76
76
R
R
R
R
1
1
53
53
4.7K_0402_5%
4.7K_0402_5%
CRT@
1 2
1 2
D
D
D
e
e
ciphered Date
ciphered Date
ciphered Date
e
CRT@
CRT@
CRT@
22_0402_5%
22_0402_5%
22_0402_5%
22_0402_5%
o
mpal Secret Data
ompal Secret Data
mpal Secret Data
o
C
C
V
S
H
RT
_DDC_DAT
RT
_DDC_CLK
YNC
S
YNC
2
C
C
C
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
T
T
T
i
tle
tle
tle
i
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
L
L
L
A
A
A
C
C
C
T
T
T
R
R
R
-9868P
-9868P
-9868P
2
2
o
o
2
o
2 4
f
2 4
2Thursday, May 16, 2013
2Thursday, May 16, 2013
2 42Thursday, May 16, 2013
f
1
f
1
1
1
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Page 23
CyberForum.ru
5
ot 1 Half PCIe Mini Card-WLAN
Sl
J1
J1
1
1
P
P
+
3
1
1
M
M
V_WLAN
2 1
JUMP_43X39
JUMP_43X39
@
@
4
0 mils
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
2
2
M
M
C
C
2
2
M
M
C
C
D D
C C
+
3
V_WLAN
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
+
3
VS
1
3
3
2
7U_0603_6.3V6K
7U_0603_6.3V6K
.
. 4
4
4
B
T
_ON
C
KREQ_WLAN#<8>
L
C
K_WLAN#<7>
L
C
K_WLAN<7>
L
P
E_WLANTX_ARX_N2<5>
CI
P
E_WLANTX_ARX_P2<5>
CI
P
CI
E_ATX_C_WLANRX_N2<5>
P
CI
E_ATX_C_WLANRX_P2<5>
E
5
1_TXD<29>
E
1_RXD<29>
5
D
ebug card using
3
+
3
J
J
LAN
LAN
W
W
1
1
3
2
1
1
1
M
M
R
R
B
T
_CTRL_R
0_0402_5%@
0_0402_5%@
+
3
V_WLAN
E
1_TXD
5
E
1_RXD
5
3
5
5
7
7
9
9
1
1
1
1
1
3
1
3
1
5
1
5
7
1
1
7
9
1
1
9
1
2
2
1
3
2
2
3
25
2
5
2
7
2
7
2
9
2
9
1
3
3
1
3
3
3
3
3
5
3
5
3
7
3
7
9
3
3
9
1
4
4
1
43
4
3
4
5
4
5
7
4
4
7
9
4
4
9
51
5
1
53
G
N
LCN_DAN08-52406-0500
LCN_DAN08-52406-0500
@
@
2
2
4
4
6
6
8
8
0
1
1
0
2
1
1
2
14
1
4
1
6
1
6
8
1
1
8
0
2
2
0
2
2
2
2
4
2
2
4
26
2
6
2
8
2
8
0
3
3
0
2
3
3
2
34
3
4
3
6
3
6
8
3
3
8
0
4
4
0
4
2
4
2
4
4
4
4
6
4
4
6
48
4
8
5
0
5
0
2
5
5
2
54
G
N
D1
D2
V_WLAN
W A
P
A
P
U_SCLK0 <10,11,8>
A
P
U_SDATA0 <10,11,8>
U
S
B20_N1 <7>
U
S
B20_P1 <7>
L
_OFF# <29>
U_PCIE_RST# <12,25,8>
B
T
2
W
LAN&BT Combo module circuits
B
T
on module
1
BT on module
Enable Disable
H L
1 2
R
B
T
_ON
F
or isolate BT_CTRL and
Compal Debug Card.
R
2
2
M
M
1K_0402_5%
1K_0402_5%
E
5
1_RXD
From EC
BT_ON
B
T_ON<29>
S
ATA HDD Conn.
+
VS
5
B B
HDD @
HDD @
J
J
23
N
D
G
24
N
D
A A
G
UYIN_127043FR022G196ZR
UYIN_127043FR022G196ZR
S
S
5
1
.2A
1
1
1
85
85
C
C 10U_0805_10V4Z
10U_0805_10V4Z
2
D
N
G
+
A
A
N
D
G
B
+
B
N
D
G
3
3
V
3
3
V
3
3
V
N
D
G
N
D
G
N
D
G
5
V
5
V
5
V
D
N
G
S/DSS
A
D
D
N
G
2
1
V
2
1
V
1
2
V
P
lace closely JHDD SATA CONN.
-
-
1 2 3 4 5 6 7
8 9 10 11 12 13 1
4
1
5 6
1 17 18 19 20 21 22
1
86
86
1
1
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
2
S
TA_ATX_C_DRX_P0
A
S
A
TA_ATX_C_DRX_N0
S
TA_DTX_ARX_N0
A
S
A
TA_DTX_ARX_P0
1
1
1
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
2
+
3
+
5
87
87
C
lose to JHDD
2
1
1
1
94 0.01U_0402_25V7K
94 0.01U_0402_25V7K
C
C
1 2
95 0.01U_0402_25V7K
95 0.01U_0402_25V7K
1
1
C
C
1 2
1
96 0.01U_0402_25V7K
96 0.01U_0402_25V7K
1
C
C
1 2
C
C
1
1
98 0.01U_0402_25V7K
98 0.01U_0402_25V7K
VS
VS
S
TA_ATX_DRX_P0 <7>
A
S
TA_ATX_DRX_N0 <7>
A
S
A
TA_DTX_C_ARX_N0 <7>
S
A
TA_DTX_C_ARX_P0 <7>
S
S
S
T
T
T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
S
ATA ODD Conn
+
VS_ODD
5
1
1A
.
2
1
1
93
93
1
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
2
1 2
1
97 0.01U_0402_25V7K
97 0.01U_0402_25V7K
1
C
C
1 2
1
99 0.01U_0402_25V7K
99 0.01U_0402_25V7K
1
C
C
1
2
00 0.01U_0402_25V7K
00 0.01U_0402_25V7K
2
C
C
1 2
2
01 0.01U_0402_25V7K
01 0.01U_0402_25V7K
2
C
C
O
PLUGIN# <8>
DD_
O
DA# <8>
DD_
2
1
89
89
1
1
C
C 10U_0805_10V4Z
10U_0805_10V4Z
DD
DD
O
O
G
G
G
+ +
N
D
G
G
N
D
G
G
SANTA_202401-1
SANTA_202401-1
C
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
o
2
@
@
1
D
N
2
+
A
3
-
A
4
D
N
5
-
B
6
+
B
7
N
D
8
P
D
9
V
5
10
V
5
1
D
M
12
D
N
13
D
N
D
D
D
e
ciphered Date
ciphered Date
ciphered Date
e
e
P
lace components closely ODD CONN.
J
J
15 14
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
ssu
ed Date
ed Date
ed Date
ssu
ssu
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
H
2
2
2
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
0
3
1
1
C
C
1
1
92
92
0.1U_0402_10V7K
0.1U_0402_10V7K
2
S
A
TA_ATX_C_DRX_P1
S
ATA_ATX_C_DRX_N1
S
TA_DTX_ARX_N1
A
S
A
TA_DTX_ARX_P1
+
5
O
DD_
DA#
VS_ODD
S
TA_ATX_DRX_P1 <7>
A
S
A
TA_ATX_DRX_N1 <7>
S
TA_DTX_C_ARX_N1 <7>
A
S
TA_DTX_C_ARX_P1 <7>
A
C
C
C
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
T
T
T
i
tle
tle
tle
i
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
W
W
W
L
LAN/SATA HDD&ODD
AN/SATA HDD&ODD
AN/SATA HDD&ODD
L
L
L
L
A
A
-9868P
-9868P
-9868P
A
1
2
2
o
o
2
o
3 4
f
f
3 4
f
3 4
2Thursday, May 16, 2013
2Thursday, May 16, 2013
2Thursday, May 16, 2013
1
1
1
.0
.0
.0
Page 24
CyberForum.ru
5
USB Sleep & Charge
4
3
ght side USB 3.0 x 2/ Sleep&Charge
Ri
2
1
State table for MAX14641
M
CB0 STATUS
0
0
D D
1
CB1
0
1
0
1 1
C
HG_PWR_GATE#<29>
R
S
LP_CHG_CB1<8>
E
C
_CHG_CB1<29>
L
e
ft Side USB Port
C C
R
R
R
U
S
B20_P0<7>
U
B20_N0<7>
S
U
S
B_EN#2<29>
de
o
2A auto-detection charger mode for Apple device.
AM2
Resistor dividers are connected to DP/DM. Including DCP
Forced 1A charger mode for Apple devices.
AP1
Resistor dividers are connected to DP/DM.
PM
USB pass-through mode.DP/DM are connected to TDP/TDM
USB pass-through mode with CDP emulation.
CM
Auto connects DP/DM to TDP/TDM depending on CDP detection status.
@
@
0_0402_5%
0_0402_5%
R
R
6
6
R
1
C
C
1
1
R
R
2
1U_0402_10V7K
1U_0402_10V7K
.
. 0
0
U
B20_P0_L <25>
S
U
SB20_N0_L <25>
R
+
5
R
R
R
R
VALW
U U
14641@
14641@
1
1
S
B20_N9 <7> B20_P9 <7>
S
0_0402_5%
0_0402_5%
R
R
U
U
MAX14640ETA+TGH7
MAX14640ETA+TGH7
14640@
14640@
14641@
14641@
U
U
R
R
4
4
1
C
E
U
B20_DN9
S
U
@
@
+
VALW
5
SB20_DP9
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
2 3 4 1
SY6288DCAC_MSOP8
SY6288DCAC_MSOP8
S
2
R
R
U
U
I I E G
A00003TV00
14641@
14641@
R
R
2
2
5
5
R
R
2 3 4
C
C
G_CB1
HG_CB1
H
9
MAX14641ETA+TGH7_TDFN-EP8_2X2
MAX14641ETA+TGH7_TDFN-EP8_2X2
CB0,CB1->VIH=1.4V
EMI@
EMI@
4
4
1
1
WCM-2012-900T_0805
WCM-2012-900T_0805
.0A
3
3
6
U
T
N
O
7
T
U
N
O
8
U
/ENB
T
N
O
5
N
D
B
C
O
D
M
D
P
C
B
P
G
W
=
+
USB_VCCC
N
T T V
1 ND
R
R
7
7
L
L
3
3
2
2
80mils
1
14
14
R
R
C
C
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
@
@
C
B
DM
D
C
0
P C
8
C
H
7
U
S
6
U
SB20_P9
5
U
B_OC#2 <29,8>
S
G_CB0 B20_N9
4
4
A 0x35
d
dress
E
_CHG_CB0 <29>
C
S
L
P_CHG_CB0 <8>
U
S
B30_RX0N<7>
U
B30_RX0P<7>
S
U
B30_TX0N<7>
S
U
S
B30_TX0P<7>
U
B30_RX1N<7>
S
U
B30_RX1P<7>
S
U
B30_TX1N<7>
S
U
B30_TX1P<7>
S
U
B30_RX0N
S
U
B30_RX0P
S
1 2
U
S
15 0.1U_0402_16V7K
15 0.1U_0402_16V7K
R
R
C
C
2
1
U
SB30_TX0P_C
C
C
16 0.1U_0402_16V7K
16 0.1U_0402_16V7K
R
R
U
B30_RX1N
S
U
B30_RX1P
S
1 2
R
R
17 0.1U_0402_16V7K
17 0.1U_0402_16V7K
C
C
1 2
18 0.1U_0402_16V7K
18 0.1U_0402_16V7K
R
R
C
C
KINGCORE WCM-2012HS-670T
KINGCORE WCM-2012HS-670T
B30_TX0N_C
KINGCORE WCM-2012HS-670T
KINGCORE WCM-2012HS-670T
KINGCORE WCM-2012HS-670T
KINGCORE WCM-2012HS-670T
U
S
B30_TX1N_C
U
B30_TX1P_C
S
KINGCORE WCM-2012HS-670T
KINGCORE WCM-2012HS-670T
EMI@
EMI@
1
1
R
R
L
L
4
4
1
1
L
L
R
R
3
3
4
4
1
1
L
L
4
4
R
R
4
4
1
1
6
6
R
R
L
L
4
4
1
1
EMI@
EMI@
EMI@
EMI@
EMI@
EMI@
3
U
B30_RX0N_L
S
3
2
U
B30_RX0P_L
S
2
3
U
S
B30_TX0N_C_L
3
2
U
B30_TX0P_C_L
S
2
3
U
B30_RX1N_L
S
3
2
U
SB30_RX1P_L
2
3
U
S
B30_TX1N_C_L
3
2
U
S
B30_TX1P_C_L
2
U
S
U
SB20_N8<7>
B20_P8<7>
+
USB_VCCB
+
U
SB_VCCA
U
S
B20_P8
U
B20_N8
S
U
B30_TX0P_C_L
S
U
B30_TX0N_C_L
S
U
B30_RX0P_L
S
U
B30_RX0N_L
S
U
S
B20_P8_L
U
S
B20_N8_L
U
U
U
B30_TX1P_C_L
S
U
B30_TX1N_C_L
S
U
B30_RX1P_L
S
U
B30_RX1N_L
S
U
B20_P9_L
S
U
SB20_N9_L
B20_DN9
S
B20_DP9
S
R
R
2
EMI@
2
EMI@
L
L
4
4
1
1
WCM-2012-900T_0805
WCM-2012-900T_0805
9 8 7 6 5 4 3 2 1
R
R
5
5
L
L
4
4
1
1
WCM-2012-900T_0805
WCM-2012-900T_0805
S
leep & Charge Port
3
3
2
2
U
U
SBR
@
SBR
J
J
S S G S S G D D V
LOTES_AUSB0015-P001A
LOTES_AUSB0015-P001A
9 8 7 6 5 4 3 2 1
@
t
dA-SSTX+
D
GN
N
t
dA-SSTX-
D
G
N
N
D-DRAIN
D
G
N
t
dA-SSRX+
D
G
t
dA-SSRX-
D
N +
­US
B
EMI@
EMI@
3
3
2
2
SBF
SBF
U
U
J
J
LOTES_AUSB0015-P001A
LOTES_AUSB0015-P001A
t
dA-SSTX+
S
dA-SSTX-
t
S
D-DRAIN
N
G
t
dA-SSRX+
S
t
dA-SSRX-
S
D
N
G
+
D
-
D
US
B
V
N
G
N
G
N
G
N
G
@
@
D D D D
U
S
B20_P8_L
U
B20_N8_L
S
13 12 11 10
U
S
U
SB20_P9_L
13 12 11 10
B20_N9_L
+
3
U
S
B POWER SWITH
B B
+
VALW
5
2
.5A
1
1
R
R
U
U
2
N
I
3
N
I
U
SB_CHG_EN#<29>
U
S
B_EN#0<29>
+
U
A A
SB_VCCA
1
2
C
C
R
R
4
N
/ENB
E
1
D
N
G
SY6288DCAC_MSOP8
SY6288DCAC_MSOP8
S
A00006DN00
+
5VALW
2
.0A
U
U
R
R
2
2
2
I
N
3
I
N
4
E
/ENB
N
1
G
N
D
SY6288DCAC_MSOP8
SY6288DCAC_MSOP8
S
A00003TV00
W
=
100mils W=80mils
1
1
7
7
1U_0402_10V7K
1U_0402_10V7K
0.
0.
R
R
C
C
R
R
2
2
C
C
@
@
2
2
U_0805_6.3V6M
U_0805_6.3V6M
7U_0805_10V4Z
7U_0805_10V4Z
7
7
.
.
4
4
4
4
W
=
100mils
+
U
SB_VCCA
6
T
OU
7
T
OU
8
OU
T
5
B
OC
W=80mils
+
U
SB_VCCB
6
O
U
T
7
O
T
U
8
O
U
T
5
O
B
C
+
U
9
9
SB_VCCB
1
2
R
R
11
11
C
C
1U_0402_10V7K
1U_0402_10V7K
.
. 0
0
U
S
B_CHG_OC# <29,8>
U
B_OC#0 <29,8>
S
1
R
3
3
R
C
C
@
@
2
U_0805_6.3V6M
U_0805_6.3V6M 7
7 4
4
E
C
_SMB_CK1<29,33,34>
E
_SMB_DA1<29,33,34>
C
1
C
C
R
13
13
R
2
7U_0805_10V4Z
7U_0805_10V4Z
.
4.
4
5
4
VALW
2
Q
Q
1A
1A
R
R
6 1
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
14640@
14640@
3 4
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
Q
Q
14640@
14640@
S
S
S
e
e
ecurity Classification
T
T
T
H
H
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+
3
VALW
RR
RR
3
3
4.7K_0402_5%
4.7K_0402_5%
14640@
14640@
5
1B
1B
R
R
1 2
R
R
R
R
4
4
4.7K_0402_5%
4.7K_0402_5%
14640@
14640@
1 2
C
HG_CB1
C
H
G_CB0
C
hange ESD Diode for EMI request
Change ESD Diode for EMI request
curity Classification
curity Classification
I
I
I
ed Date
ed Date
ed Date
ssu
ssu
ssu
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3
2
2
2
0
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
C
C
C
o
o
mpal Secret Data
ompal Secret Data
mpal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
R
R
1
@ESD@
1
@ESD@
D
D
U
B30_TX0P_C_L
S
U
S
B30_TX0N_C_L
U
B30_RX0P_L
S
U
SB30_RX0N_L
U
S
B30_TX1P_C_L
U
B30_TX1N_C_L
S
U
B30_RX1P_L
S
U
S
B30_RX1N_L
T
T
i
Title
tle
tle
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
1
1
1
2
2
2
4
4
4
5
3
3
3
8
8
YSCLAMP0524P_SLP2510P8-10-9
YSCLAMP0524P_SLP2510P8-10-9
SC300002800
SC300002800
R
R
3
3
D
D
1
1
1
2
2
2
4
4
4
5
3
3
3
8
8
YSCLAMP0524P_SLP2510P8-10-9
YSCLAMP0524P_SLP2510P8-10-9
SC300002800
SC300002800
C
C
C
o
ompal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
L
L
L
U
SB/RUSB/S&C
SB/RUSB/S&C
SB/RUSB/S&C
U
U
L
L
L
A
A
-9868P
-9868P
-9868P
A
9
U
B30_TX0P_C_L
S
10
10
8
U
S
B30_TX0N_C_L
9
9
7
U
S
B30_RX0P_L
7
7
6
U
S
B30_RX0N_L
65
65
@ESD@
@ESD@
9
U
S
B30_TX1P_C_L
10
10
8
U
S
B30_TX1N_C_L
9
9
7
U
SB30_RX1P_L
7
7
6
U
S
B30_RX1N_L
65
65
2
2
o
2
o
o
4 4
f
2Thursday, May 16, 2013
2Thursday, May 16, 2013
2Thursday, May 16, 2013
4 4
f
f
1
4 4
1
1
1
.
.0
0
0
.
Page 25
CyberForum.ru
5
Battery Reset
D D
E
DO<35>
NL
G
-
SENSOR
+
VS
G
G
C
C
GSENSOR@
GSENSOR@
5
1
12
12
2
1
2
3
G9191-330T1U_SOT23-5
G9191-330T1U_SOT23-5
SA000022I00
C C
1U_0402_6.3V6K
1U_0402_6.3V6K
UG
UG
VI
GN
SH
3
4
3
GSENSOR@
3
GSENSOR@
N
D
DN#
W
W
6
6
S
S TJG-533-V-T/R_6P
TJG-533-V-T/R_6P
1
2
6
5
5
VO
UT
4
BP
+
LAN Conn
For LAN function
VS_HDP
3
1
G
13
13
G
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
GSENSOR@
GSENSOR@
2
+
3VS
L
AN_EN<8>
C
L
KREQ_LAN#<8>
+
VS_HDP
3
S
+
VS_HDP
3
4
L
N_EN
A
C
LKREQ_LAN#
U
U
2
12
4 6 8
9
TSH352TR LGA 16P
TSH352TR LGA 16P
S
12
2N7002KW_SOT323-3
2N7002KW_SOT323-3
1
1
G
G
d1
d
V
d
d2
V
T
S
D
P
S
F
e
v
R
A00004GB00
RL
RL
24 10K_0402_5%
24 10K_0402_5%
E
LF_TEST
1
D
D
GSENSOR@
GSENSOR@
utx
o
V
uty
o
V
utz
o
V
C
N
C
N
C
N
C
N
C
N
N
D1
G
N
D2
G
L
A
NCLK_REQ#
2
G
G
1
1
L
L
Q
Q
3 5 7
10
1
11
2
14
3
15
4
16
5
1 13
3
S
S
V V V
L
ANCLK_REQ#
UTX
O OUTY OUTZ
+
VS
3
1
2
1 2
G
G
1 0.033U_0402_16V7KGSENSOR@
1 0.033U_0402_16V7KGSENSOR@
C
C
2
1
2 0.033U_0402_16V7KGSENSOR@
2 0.033U_0402_16V7KGSENSOR@
CG
CG
2
1
3 0.033U_0402_16V7KGSENSOR@
3 0.033U_0402_16V7KGSENSOR@
G
G
C
C
+3
1K_0402_5%
1K_0402_5%
L
L
1
1
R
R
@
@
I
OLATE#
S
3
3
L
L
R
R
15K_0402_5%
15K_0402_5%
3
VALW_APU
1 2
@
@
2 0_0402_5%
2 0_0402_5%
L
L
R
R
W
OL_EN#
L
L
1
EMI@
EMI@
2
+3V_LAN
L
L
1
1
2
A
P
CI
E_ATX_C_LANRX_N1<5>
P
CI
E_ATX_C_LANRX_P1<5>
P
CI
E_LANTX_ARX_N1<5>
P
E_LANTX_ARX_P1<5>
W
L_EN#
O
Sx Enable Wake up
LOW
L
E
D
White LED bright when both AC-adaptor is plugged in and Battery is full charged Amber LED bright while charging battery from AC-adaptor. Amber LED blink during Critical Low Battery
W
L_EN# <29>
O
Sx Disable Wake up
S0
HIGH HIGH
B
ATT CHARGE /FULL LED
+
VALW
5
CI
2
2
4
4
D
D
2 1
HT-F196BP5_WHITE
HT-F196BP5_WHITE
3
3
2
2
D
D
2 1
HT-191UD5_AMBER_0603
HT-191UD5_AMBER_0603
+3
AP
P
V_LAN
U_PCIE_RST#<12,23,8>
U_PCIE_WAKE#<8>
C
LK_LAN#<7>
C
L
K_LAN<7>
U
B20_P0_L<24>
S
U
B20_N0_L<24>
S
+
US
R
R 390_0402_5%
390_0402_5%
1 2
1 2
R
R 5
5
B_VCCC
6
6
0
0
3
3
10_0402_5%
10_0402_5%
L
ANCLK_REQ#
I
S
OLATE#
c
lose to JLAN
EMI@
EMI@
L
L
4
4
R
R
1 2
5
5
L
L
R
R
1 2
EMI@
EMI@
+
B_VCCC
US
W
=60mils
0_0402_5%
0_0402_5% 0_0402_5%
0_0402_5%
B
A
TT_FULL_LED# <29>
B
ATT_CHG_LOW_LED# <29>
C
K_LAN#_R
L
C
K_LAN_R
L
1
JL
JL
AN
AN
1
1
2
2
2
3
3
4
4
4
5
5
6
6
6
7
7
8
8
8
9
9
10
1
0
10
1
1
1
1
12
1
12
2
13
1
3
14
1
4
14
1
5
1
5
16
1
6
16
1
7
1
7
18
1
18
8
1
9
1
9
20
2
0
20
2
G
1
2
G
2
23
G
3
2
G
4
ACES_50559-02001-001
ACES_50559-02001-001
@
@
1 2
4
+
VS_HDP
3
B B
H
DP
A A
INT<29>
R
R
1
1
G
G
1 8 2 3 6 4 5
4.7K_8P4R_5%
4.7K_8P4R_5%
GSENSOR@
GSENSOR@
E
H
INT
DP
R
SET#
E
7
G
X
OUT
G
IN
X
M
DE
O
C_
SMB_CK2<13,29,6>
+
3
VS_HDP
M
DE
O
2
R
R
G
G
4 1K_0402_5%
4 1K_0402_5%
GSENSOR@
GSENSOR@
0.1U_0402_10V7K
0.1U_0402_10V7K
GSENSOR@
GSENSOR@
5
S
E
R
E
G
X
G
X
C
C
LF_TEST
SET#
OUT
IN
1
G
G
7
7
1
1
G
G
8
8
C
C
GSENSOR@
GSENSOR@
0.1U_0402_10V7K
0.1U_0402_10V7K
2
2
G
G
2
2
U
U
1
3
_5/SSCK/S CL/CMP1_2
P
2
3
_7/CNTR0 #/SSO/TXD1
P
3
SET#
E
R
4
UT/P4_7
O
X
5
S/AVSS
S
V
6
I
N/P4_6
X
7
C/AVCC
C
V
8
O
DE
M
9
4
_5/INT0#/RX D1
P
10
_7/CNTR0 0/INT10#
1
P
R5F211B4D34SP GSENSOR@
R5F211B4D34SP GSENSOR@
SA00003A600
_5/RXD0/C NTR01/INT11#
1
P
1
P
_2/KI2#/AN1 0/CMP0_2
1
P
1
P
1
P
3
_3/TCIN/INT3#/S SI00/CMP1_0
P
_4/SCS#/S DA/CMP1_1
3
P
4
_6/CLK0/S SI01
1
P
_4/TXD0
1
P
_3/KI3#/AN1 1/TZOUT
_2/VREF
4
P
_1/KI1#/AN9 /CMP0_1
_0/KI0#/AN8 /CMP0_0
White LED bright when system is power on.
11
12
13
14
15
16
17
18
19
20
G
2
2
G
R
R 47K_0402_5%
47K_0402_5%
GSENSOR@
GSENSOR@
1 2
V
UTZ
O
V
UTX
O
V
UTY
O
S
S
S
e
curity Classification
curity Classification
ecurity Classification
e
I
I
I
ssu
ssu
ed Date
ed Date
ed Date
ssu
T
T
T
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
H
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
G
G
3 47K_0402_5%
3 47K_0402_5%
R
R
12
GSENSOR@
GSENSOR@
+
VS_HDP
3
1
6
6
G
G
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
GSENSOR@
GSENSOR@
2
H
DP
ACT <29>
H
DP
LOCK <29>
E
C_SMB_DA2 <13,29,6>
2
2
2
0
0
0
3
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
White LED blink when system is sleep mode.
+
5
Amber LED bright while Wireless and/or WiMAX turns on.
C
C
C
o
mpal Secret Data
mpal Secret Data
ompal Secret Data
o
POWER LED
8
8
2
2
D
D
+
VALW
5
2 1
HT-F196BP5_WHITE
HT-F196BP5_WHITE
1
1
6
6
R
R 390_0402_5%
390_0402_5%
1
2
WLAN/WiMAX LED (AMD NO WIMAX)
D
D
7
7
2
2
VS
HT-191UD5_AMBER_0603
HT-191UD5_AMBER_0603
D
D
D
e
e
ciphered Date
ciphered Date
ciphered Date
e
2
1
1
6
6
6
6
R
R 510_0402_5%
510_0402_5%
2
2
W
L_BT_LED# <29>
T
T
i
tle
tle
i
Title
L
L
L
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
P
W
R_SUSP_LED# <29>
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
ompal Electronics, Inc.
o
o
A
N/G-SENSOR/LED/B_RES
AN/G-SENSOR/LED/B_RES
N/G-SENSOR/LED/B_RES
A
L
L
L
A
-9868P
-9868P
A-9868P
A
2
2
2
5 4
5 42Thursday, May 16, 2013
1
5 4
1
1
1
.0
.0
o
o
o
.0
f
2Thursday, May 16, 2013
2Thursday, May 16, 2013
f
f
Page 26
CyberForum.ru
5
U
U
22 21
17 16
31
30 29
15 14
20
12
NO_IN
O
10
11
10 mil
19
A
_JDREF
C
28
L
D
O_CAP
27
A
C
_VREF
34
C
VEE
P
35
C
B
N
36
C
P
B
2 3
13
NSE_A
E
18
NSE_B
E
47
4
ALC259-VC2-CG_MQFN48_6X6
ALC259-VC2-CG_MQFN48_6X6
259@
50
50
A
A
R
R
4.7K_0402_5%
4.7K_0402_5%
269@
269@
T
E
259@
o solve noise issue
Internal AMP
C_MUTE#
Hight
Enable
LOW
Disable
+
IC1_VREFO_L
M
+
IC1_VREFO_R
M
E
_MUTE_INT<29>
C
A
Z
_SYNC_HD<8>
12
C_MUTE#<29>
584.7U_0603_6.3V6KCA584.7U_0603_6.3V6K
CA
A
A
574.7U_0603_6.3V6K
574.7U_0603_6.3V6K
C
C
M
IC1_LINE1_R_C_R
M
I
C1_LINE1_R_C_L
M
I
NT_MIC_CLK_R
S S
1 2
M
IC1_LINE1_R_R
M
C1_LINE1_R_L
I
D D
@ESD@
@ESD@
0.01U_0402_25V7K
0.01U_0402_25V7K
1 2
A
A
65
65
C
C
A
Z
_RST_HD#<8>
c
close to pin 28
1 2
A
A
60 10U_0603_6.3V6M
60 10U_0603_6.3V6M
C
C
1
12
A
A
C
C
2.2U_0603_10V6K
2.2U_0603_10V6K
C C
I
T_MIC_CLK<20>
N
25
25
A
A
55
55
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
2
R
R
F
FBMA-10-100505-301T
FBMA-10-100505-301T
lose to pin19
R
R
30 20K_0402_1%
30 20K_0402_1%
A
A
1 2
A
A
C
C
1 2
C
C
A
A
I
N
T_MIC_DATA<20>
12
@
@
A
34 20K_0402_1%
34 20K_0402_1%
A
o
r EMI reserve
I
T_MIC_CLK_R
N
42
42
A
A
R
R
CAM_EMI@
CAM_EMI@
54 2.2U_0402_6.3V6M
54 2.2U_0402_6.3V6M
53 2.2U_0402_6.3V6M
53 2.2U_0402_6.3V6M
E
1
1
A
A
M
I
C1_R
M
I
C1_L
M
C2_R
I
M
C2_L
I
C1_VREFO_L
I
M
M
IC1_VREFO_R
M
I
C2_VREFO
L
I
NE2_R
L
I
NE2_L
M
NO_OUT
O
P
C
BEEP
S
NC
Y
R
E
SET#
J
REF
D
O_CAP
D
L
R
EF
V
VEE
P
C
C
N
B
C
BP
G
PIO0/DMIC_DATA
G
P
IO1/DMIC_CLK
S
E
NSE_A
S
E
NSE_B
PD
A
E
#
D
P
4
K_OUT_R+
P
S
K_OUT_R-
P
S
K_OUT_L+
P
S
K_OUT_L-
P
S
H
S
D
S
h
T
V
D
V
DD_IO
D
V
DD1
A
DD2
V
A
DD1
V
P
V
DD2
P
OUT_R
P
P
OUT_L
H
ATA_OUT
DATA_IN
B
L
I
NE1_L
L
NE1_R
I
V
A
A
VSS2
V
P
V
P
V
D
ermal Pad
3
3
5mA for 3.3V level
@
@
2
+D
1
+
VDD
DD
C
N
SS1
SS1 SS2
D
9
+
DVDD_IO
25
+
A
VDD
38
+
A
VDD
39
+
P
VDD
46
+
VDD
P
45
S
KR+
P
44
S
KR-
P
40
S
P
KL+
41
S
KL-
P
33
H
POUT_R
32
H
P
5 8
A
_SDIN0_HD_R
Z
6
A
_BITCLK_HD
Z
LK
23
L
I
NE1_R_C_L
24
L
I
NE1_R_C_R
8
4
C
26
37
42 43 7
SS
A
49
D
GND
OUT_L
GND
75_0402_1%
75_0402_1%
19
19
A
A
R
R
20
20
RA
RA
75_0402_1%
75_0402_1%
R
R
23 33_0402_5%
23 33_0402_5%
A
A
1 2
C
C
A
A
9 0.1U_0402_10V6K269@
9 0.1U_0402_10V6K269@
1 2
A
A
10 0.1U_0402_10V6K269@
10 0.1U_0402_10V6K269@
C
C
F
or EMI reserve
close to codec
A
Z
_BITCLK_HD
12
0.1U_0402_16V4Z
0.1U_0402_16V4Z
ose to pin1
cl
c
H
_R <27>
P
H
P
_L <27>
F
o
r S&M
EMI@
EMI@
12
A
A
4110_0402_5%
4110_0402_5%
R
R
lose to pin9
A
Z
A
_SDIN0_HD <8>
Z
A
_BITCLK_HD <8>
Z
10P_0402_50V8J
10P_0402_50V8J
1
A
A
4
4
C
C
2
CA
CA
0.1U_0402_16V4Z
0.1U_0402_16V4Z
_SDOUT_HD <8>
M
I
C1_LINE1_R_L
M
C1_LINE1_R_R
I
A
A
51
51
C
C
1 2
EMI@
EMI@
VDD
+
D
VDD_IO
1
45
45
2
1
22 0_ 0402_5%
22 0_ 0402_5%
RA
RA
1
C
C
3
3
A
A
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2
H
@
@
1 2
R
R
1 0_0402_5%
1 0_0402_5%
A
A
F
or P/N and footprint
Please place them to ISPD page
A
1
1
A
U
U
ALC269Q-VB6-CG
ALC269Q-VB6-CG
269@
269@
EMI@
EMI@
C
C
5 0.1U_0402_10V7K
5 0.1U_0402_10V7K
A
A
2
1
C
C
A
A
6 0.1U_0402_10V7KEMI@
6 0.1U_0402_10V7KEMI@
2
1
A
A
7 0.1U_0402_10V7KEMI@
7 0.1U_0402_10V7KEMI@
C
C
2
1
1 2
R
R
A
A
38 0_0603_5%
38 0_0603_5%
EMI@
EMI@
1
A
A
31
31
R
R
@EMI@
@EMI@
2
+A
+
VS
3
DALink is 1.5V
+
1
.5VS
2
0_0603_5%
0_0603_5%
6
40 mil20 mil
close to pin 25 close to pin 38
VDD
42
42
A
A
C
C
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
c
ose to pin39
l
0.1U_0402_10V7K
0.1U_0402_10V7K
c
lose to pin46
50mA for 5V level
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
CA
CA
1
47
47
C
C
A
A
C
C
A
A
2
33
33
32
32
C
C
A
A
37
37
10U_0603_6.3V6M
10U_0603_6.3V6M
60 mil
+
P
VDD
1
2
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
2
A
A
50
50
C
C
1
Sleep and Music
259@
269@
No
Yes
1
2
2
CA
CA
35
35
1
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1 2
@
@
18 0_0603_5%
18 0_0603_5%
RA
RA
1 2
@
@
R
R
24 0_0603_5%
24 0_0603_5%
A
A
+
VALW
5
+
5
VALW
K_L1 <27>
K_L2 <27>
K_R1 <27>
K_R2 <27>
M
IC/LINE IN
M
M
S
_SENSE#<29>
M
E
C
2
I
C1_LINE1_R_R
C1_LINE1_R_L
I
+
3VL
2
47
47
A
A
R
R
1K_0402_5%
1K_0402_5%
2
1
2
1
1K_0402_5%
1K_0402_5%
R
R
A
A
45
45
M
C_SENSE
I
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
35 100K_0402_5%
35 100K_0402_5%
A
A
R
R
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
N
A_PLUG<27>
B
C
C
C
61
Q
Q
1A
1A
A
A
269@
269@
3
Q
Q
A
A
1B
1B
269@
269@
4
p
lace close to chip
M
C_SENSE
I
R
R
R
R
T
T
T
i
i
tle
tle
tle
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
u
u
stom
stom
stom
u
Date: S heet
Date: S heet
Date: S heet
1
12
269@
269@
12
o
ver Sheet
ver Sheet
ver Sheet
o
o
+
+
1
R
R
48 2.2K_0402_5%
48 2.2K_0402_5%
A
A
46 2.2K_0402_5%
46 2.2K_0402_5%
A
A
R
R
R
R
A
A
29
29
100K_0402_5%
100K_0402_5%
2
5
A
32 20K_0402_1%
32 20K_0402_1%
A
A
A
33 39.2K_0402_1%
33 39.2K_0402_1%
C
C
C
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
C
C
C
M
IC1_VREFO_R
M
M
M
IC1_VREFO_L
2
37
37
RA
RA 0_0402_5%
0_0402_5%
@
@
1
S
ENSE_A
C1_R <27>
I
I
C1_L <27>
J
A
26 42Thursday, May 16, 2013
26 42Thursday, May 16, 2013
26 42Thursday, May 16, 2013
CK_SENSE <27>
o
o
o
f
f
f
1
1
1
.
.
0
0
0
.
S
B
eep sound
PCI Beep
A
U_SPKR<8>
B B
Sense Pin
SENSE A
A A
P
Impedance
39.2K
20K
10K
5.1K
39.2K
20K
10K
Codec Signals
PORT-I (PIN 32, 33)
PORT-B (PIN 21, 22)
PORT-C (PIN 23, 24)
(PIN 48)
PORT-E (PIN 14, 15)
PORT-F (PIN 16, 17)SENSE B
PORT-H (PIN 20)
5
R
R
A
52
52
A
2
1
47K_0402_5%
47K_0402_5%
A
49
49
A
R
R
4.7K_0402_5%
4.7K_0402_5%
Function
Headphone out
Ext. MIC
1 2
C
C
A
70
70
A
1 2
0.1U_0402_10V7K
0.1U_0402_10V7K
A
27
27
A
C
C
100P_0402_50V8J
100P_0402_50V8J
For better sound by customer request
4
M
O
NO_IN
PK
2W 4ohm =40mil For EMI reserve 1W 8ohm =20mil
S
KL+
P
S
KL-
P
S
KR+
P
S
P
KR-
close to codec
1 2
@
@
7 0_0603_5%
7 0_0603_5%
A
A
R
R
1 2
@
@
R
R
8 0_0603_5%
8 0_0603_5%
A
A
2
1
@
@
R
R
9 0_0603_5%
9 0_0603_5%
A
A
2
1
@
@
A
A
10 0_0603_5%
10 0_0603_5%
R
R
S
S
S
e
e
curity Classification
curity Classification
curity Classification
e
I
I
I
s
ssued Date
sued Date
sued Date
s
T
T
T
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
S
P
S
P
C
C
A
31
31
A
ESD@
ESD@
SCV00001K00
SCV00001K00
34
34
A
A
C
C
ESD@
ESD@
SCV00001K00
SCV00001K00
2
2
2
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
1 2
1 2
A
30
30
A
C
C
ESD@
ESD@ SCV00001K00
SCV00001K00
1 2
36
36
A
A
C
C
ESD@
ESD@ SCV00001K00
SCV00001K00
1 2
C
C
C
o
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
S
P
S
P
D
D
D
e
eciphered Date
ciphered Date
ciphered Date
e
Page 27
CyberForum.ru
5
4
3
2
1
SPK Conn.
F
or common design,
pull-high resistor should be placed at connector side.
ACES_50228-0067N-001
ACES_50228-0067N-001
@
@
8
G
D
N
7
G
D
N
S
P
D D
K_R1<26>
S
P
K_R2<26>
S
K_L1<26 >
P
S
K_L2<26 >
P
S
K_DET<8>
P
D
D
A
A
1
1
ESD@
ESD@
SCV00001K00
SCV00001K00
1 2
6
6
5
5
4
4
3
3
2
2
1
1
J
J
PK
SPK
S
1 Harman/Kardon
0
BIOS setupSM_DET
S&M option
Non-Harman detection
SPK_DET
H
e
adPhone/LINE Out JACK
C C
1 2
@
H
P_L<26>
H
P
_R< 26>
@
R
R
A54 0_0402_5%
A54 0_0402_5%
1 2
@
@
R
R
A
A
53 0_0402_5%
53 0_0402_5%
YSDA0502C_SOT23-3
YSDA0502C_SOT23-3
H
P
H
P
D
D
A
A
@ESD@
@ESD@
_R_L
_R_R
6
6
3
2
C
C
13
13
A
A
@
@
MI@
MI@
E
E
0P_0402_50V8J
0P_0402_50V8J
1
0
0 1
1
N
A_PLUG<26>
B
C
C
A
14
14
A
@
@
MI@
EMI@
E
0P_0402_50V8J
0P_0402_50V8J 0
0 1
1
Speaker Type
0
1 Non-Brand
J
J
L
L
INE
@
INE
@ 6 1 2
3
4
5
TYCO_2041280-1_3.6D
TYCO_2041280-1_3.6D
Non Harman
ONKYO
BOM
269@
259@
B B
A A
MIC/LINE IN JACK
J
J
EXMIC
@
EXMIC
@
6
1 2
@
M
I
C1_L<26>
M
I
C1_R<26>
5
R
R
A
56 0_0402_5%
56 0_0402_5%
A
1
R
R
55 0_0402_5%
55 0_0402_5%
A
A
@
@
@
2
YSDA0502C_SOT23-3
YSDA0502C_SOT23-3
@ESD@
@ESD@
M
I
D
D
M
C1_R_L
I
C1_R_R
7
7
A
A
J
ACK_SENSE<26>
C
C
C
C
A
11
11
12
12
A
A
3
2
1
A
@
@
MI@
MI@
E
E
@
@
MI@
MI@
E
E
0P_0402_50V8J
0P_0402_50V8J
0P_0402_50V8J
0P_0402_50V8J
0
0
0
0 1
1
1
1
4
+
3
VL
R
R
40
40
A
A
4.7K_0402_5%
4.7K_0402_5%
269@
269@
1 2
3
4
5
TYCO_2041280-1_3.6D
TYCO_2041280-1_3.6D
2
R
R
36
36
A
A
0_0402_5%
0_0402_5%
@
@
1
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
s
s
sued Date
sued Date
sued Date
s
T
T
T
H
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
2
2
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
C
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
o
D
D
D
e
e
ciphered Date
ciphered Date
eciphered Date
C
C
C
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
T
T
T
i
tle
tle
tle
i
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
u
u
stom
stom
stom
u
Date: S heet
Date: S heet
2
Date: S heet
o
C
C
C
o
nn
nn
nn
o
o
27 42Thursday, May 16, 2013
27 42Thursday, May 16, 2013
27 42Thursday, May 16, 2013
1
1
1
1
.
.
0
0
0
.
o
o
o
f
f
f
Page 28
CyberForum.ru
5
8
8
W
W
C
C
0.1U_0402_16V4Z
U
SB20_N2<7>
U
S
B20_P2<7>
+
CC_3IN1
V
3
0
W
W
5
5
C
C
0.1U_0402_16V4Z
0.1U_0402_16V4Z
ND_SW N
D_SW
T-SOL_156-2000302604
T-SOL_156-2000302604
0.1U_0402_16V4Z
mils
C
D D
F
or power consumption measureme nt
and remove it after Pre-MP pha se
30mils
p
lease close the pin19 of UW1
+
VS_CR
3
3
0mils
C C
p
lease close the pin4 of UW1
+
3
VS_CR
3
0mils
W
W
3
3
C
C
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
+
VS
3
W
1 0_0402_5%
1 0_0402_5%
W
R
R
+
VS_CR
3
1
W
W
2
2
C
C
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
W
W
4
4
C
C
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1 2
@
@
1
1
1
W
W
C
C
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2
D
e-coupling and Bulk capacitor should place near to Cardreader chip and Combo Socket
<
+
VS_CR
3
1
2
2 in 1 Card Reader >
12
G
13
G
"
Normal Close" type connector
+
+ +
+ +
1
1
2
J
J
@
@
D D D
D/DAT3
W
P_SW
C
D
VS_CR
3
VS_CR
3 3VS_CR
3
VS_CR
DD18
V
2mils
RD
RD
CA
CA
V
D
D
C
M
D
C
K
L
V
S
S
V
S
S
AT0
T1
A
T2
A
_SW
4
1
U
U
W1
W1
2
22
R
TZ
S
2
D
M
3
D
P
1
D
V
DD
24
P
OS
M
19
D
V
DD
23
D
DD
V
20
G
IO0
P
4
A
VDD
18
V
D
D18
25
T
ermal pad
h
GL834L-OGY01_QFN24_4X4
GL834L-OGY01_QFN24_4X4
5 3 6 7 4
8 9 1 2
10 11
S
S
DCM
S
DCL
K_L
S
DATA0_L
D_
S
DATA1_L
D_
S
D_DATA2_L
S
D_
DATA3_L
S
P#
DW
S
DCD
S
_D2/MS_D 5/SB13
D
S
_D3/MS_D 4/SB12
D
S
CMD/SD_C MD
D S
D CLK/SD_ CLK
S
D
_D0/MS_D 6/SB9
S
_D1/MS_D 7/SB8
D
M
BS/MS_BS
S
S
_WP /MS_D1/SB5
D
S
_D4/MS_D 0/SB4
D
S
D
_D5/MS_D 2/SB3
S
D
_D6/MS_D 3/SB1
_D7/MS_C LK/SB0
D
D_L
5
M
S
_INS
17 16 15 14 21
S
_CDZ
D
13 12 11 10 9 8 7 6
G
PIO0 Normal mode
Close to connector
1
W
W
C
C
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
3
S
DATA2
D_
S
D_
DATA3
S
DCM
D
S
DCL
K
S
DCD#
S
DATA0
D_
S
DATA1
D_
S
P
DW
NC (default)
Power saving mode
Close to IC
6
6
1
C
C
7
7
W
W
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
2
10K pull down
3
0mil
+
V
CC_3IN1
2
L
L
1
1
W
W
S
DATA0
D_
S
DATA1
D_
S
DATA2
D_
S
DATA3
D_
S
DCL
K
S
DCM
D
BLM15BB121SN1D_0402
BLM15BB121SN1D_0402
BLM15BB121SN1D_0402
BLM15BB121SN1D_0402
BLM15BB121SN1D_0402
BLM15BB121SN1D_0402
BLM15BB121SN1D_0402
BLM15BB121SN1D_0402
BLM15BB121SN1D_0402
BLM15BB121SN1D_0402
BLM15BB121SN1D_0402
BLM15BB121SN1D_0402
12
EMI@
EMI@
L
L
W
W
2
2
EMI@
EMI@
L
L
W
W
3
3
2
EMI@
EMI@
W
W
4
4
L
L
EMI@
EMI@
5
5
W
W
L
L
EMI@
EMI@
6
6
W
W
L
L
EMI@
EMI@
2
1
12
2
1
1
2
1
12
2
1
12
2
1
12
2
1
1
S
DATA0_L
D_
11
EMI@
11
EMI@
W
W
C
C
4.7P_0402_50V8J
4.7P_0402_50V8J
S
DATA1_L
D_
W
W
12
EMI@
12
EMI@
C
C
4.7P_0402_50V8J
4.7P_0402_50V8J
S
D_DATA2_L
13
EMI@
13
EMI@
W
W
C
C
4.7P_0402_50V8J
4.7P_0402_50V8J
S
DATA3_L
D_
C
C
W
W
14
EMI@
14
EMI@
4.7P_0402_50V8J
4.7P_0402_50V8J
S
DCL
C
C
15
EMI@
15
EMI@
W
W
4.7P_0402_50V8J
4.7P_0402_50V8J
S
DCM
C
C
W
W10
@EMI@
10
@EMI@
4.7P_0402_50V8J
4.7P_0402_50V8J
K_L
D_L
B B
Card Uninsertion
C
rd Insertion
a
A A
5
CD_SW WP_SW
Close
Open
C
lose
O
pen
P
4
r
otect EnableProtect disable
C
Close
lose
F
or normal close type connector invert circuit
+
3
VS_CR
12
3
3
W
W
R
R 100K_0402_5%
100K_0402_5%
Q
Q
2
S
DCD
G
G
S
S
S
e
e
curity Classification
curity Classification
curity Classification
e
I
I
I
ssu
ed Date
ed Date
ssued Date
ssu
T
T
T
H
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
2
2
3
S
DCD#
61
W
W
1A
1A
D
D
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
S
S
C
C
C
o
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
0
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
o
D
D
D
e
ciphered Date
ciphered Date
eciphered Date
e
W
W
4
4
R
R 100K_0402_5%
100K_0402_5%
S
P#
DW
+
3
VS_CR
12
Q
Q
5
G
G
2
3
W
1B
1B
W
D
D
S
S
4
S
DW
P
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
C
C
C
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
T
T
T
i
i
tle
tle
tle
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
C
C
C
a
rdReader GL834L
rdReader GL834L
rdReader GL834L
a
a
L
L
L
-9868P
A-9868P
-9868P
A
A
2
2
o
o
2
o
f
8 4
f
8 42Thursday, May 16, 2013
2Thursday, May 16, 2013
2Thursday, May 16, 2013
8 4
1
f
1
1
1
.0
.0
.0
Page 29
CyberForum.ru
5
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
1
B
B
C
C
0.1U_0402_10V7K
F
r EMI
o
C
K_PCI_EC
L
12
3
3
B
B
R
R
10_0402_5%
10_0402_5%
@EMI@
22P_0402_50V8J
22P_0402_50V8J
3
VL
ESD@
ESD@
@ESD@
@ESD@
47K_0402_5%
47K_0402_5%
1
C
C
B
B
C
C
C
C
@EMI@
1
B
11
C
C
B11
@EMI@
@EMI@
2
R
R
B
B
2
2
2
1 2
12 0.1U_0402_10V7K
12 0.1U_0402_10V7K
2
1
C
B
B
R
R
2.2K_0804_8P4R_5%
2.2K_0804_8P4R_5%
1 2
B
6 0.1U_0402_10V7K
6 0.1U_0402_10V7K
B
1 2
14 180P_0402_50V8J
14 180P_0402_50V8J
B
B
H
23 10K_0402_5%
23 10K_0402_5%
R
R
P
B1
B1
P
1 8
E
6
S
Y
S_PWRGD
S
U
SP#
C
E
C
E
C
E
C
2 7 3 4 5
E
G_PWR_GATE#
_SMB_CK1 _SMB_DA1 _SMB_CK2 _SMB_DA2
D D
+
C C
VL
3
+
SMBUS1->BATT, S mart Charger SMBUS2->G-Senso r,GPU Thermal S ensor, APU The rmal Sensor
EC SMBus2 for S 0 , SMBus1 for S5
3
VL
+
VS
3
+
B B
0.1U_0402_10V7K
C_RST#
K
SI[0..7]<30>
K
O[0..15]<30>
S
C
_MUTE_INT<26>
E
R
T
P
.32_SYS_PWRGD OD/L
for 1.8V PU APU
2
G K S
L
C_FRAME#<7,8>
P
L L L L
C
L
K_PCI_EC<7,8>
L
E
95VS_PWREN#<31>
.
0
K
S
I[0..7]
K
O[0..15]
S
G_PWR_GATE#<24>
H
C
E
C
E
C
E
_SMB_CK2<13 ,25,6>
C
E
C_SMB_DA2<13,25,6>
U
U
B_CHG_OC#<24,8>
S
U
B_CHG_EN#<24>
S
F
A
N_SPEED1<5>
S
Y
S_PWRGD<8>
M
S
B
B
25 0_0402_5%
25 0_0402_5%
R
R
C_CLK<8>
B
20 0_0402_5%
20 0_0402_5%
B
R
R
1
2
2
B
B
C
C
CB
CB
2
0.1U_0402_10V7K
0.1U_0402_10V7K
TEA20<8>
A
B
_RST#< 8> RIRQ<7>
E
C_AD3<7>
P P
C_AD2<7>
P
C_AD1<7>
P
C_AD0<7>
P
C_RST#<8>
_SCI#<8>
C
_SMB_CK1<24,33,34> _SMB_DA1<24,33,34>
S
P_S3#<8>
L
S
LP_S5#<8>
E
_SMI#<8>
C
S
B_OC#2<24,8>
U
S
B_EN#2<24>
K
_LED<30>
B
W
L
_OFF#<23>
E
1_TXD<23>
5
E
1_RXD<23>
5
_ON<23>
T
B
_SENSE#<26>
1 2
@
@
1 2
@
@
0.1U_0402_10V7K
0.1U_0402_10V7K
1
4
4
2
C
H
E
C
100K_0402_5%
100K_0402_5%
Close to EC
R
R
B
27
27
B
100K_0402_5%
100K_0402_5%
1 2
4.7K_0402_5%
4.7K_0402_5%
A A
1 2
E
1_TXD
5
28
28
B
B
R
R
E
_MUTE_INT_R
C
5
E
_ON_R
C
8
5_EC_ON
8
R
R
1 3
4
1
5
5
B
B
C
C
2
1 2 3 4 5 7 8
10
12 13
E
C
_RST#
G_PWR_GATE#
E
C_SMB_CK1
E
C
E
_SMB_CK2
C
E
C
E
_MUTE_INT_R
X
C
B
B
R
R
1
36 0_0402_5%
36 0_0402_5%
B
B
D
D
2
1 2
37 20 38
55
K
I0
S
56
K
I1
S
57
K
I2
S
58
K
I3
S
59
K
I4
S
60
K
I5
S
61
K
S
I6
62
K
S
I7
39
K
S
O0
40
K
S
O1
41
K
SO2
42
K
S
O3
43
K
S
O4
44
K
S
O5
45
K
O6
S
46
K
S
O7
47
K
O8
S
48
K
SO9
49
K
O10
S
50
K
O11
S
51
K
O12
S
52
K
O13
S
53
K
O14
S
54
K
S
O15
81 82
77 78
_SMB_DA1
79 80
_SMB_DA2
6 14 15 16 17 18 19 25 28 29 30
5
1_TXD
31 32 34 36
122 123
LKO
12
1
C
C
B
22
22
@
@
G
G
R
R
B
B
10K_0402_5%
10K_0402_5%
885@
885@
16
16
B
20P_0402_50V8
20P_0402_50V8
2
2
S
S
Q
Q
B
2
2
B
2N7002KW_SOT323-3
2N7002KW_SOT323-3
885@
885@
24
24
F
or KB9012 EC_ON low pulse work around
4
1
1
UB
UB
A
TEA20/GPIO00
G
B
RST#/GPIO01
K
E
RIRQ
S
P
C_FRAME#
L
P
C_AD3
L
C_AD2
P
L
C_AD1
P
L
P
P
L
L
C_AD0
P
L
K_PCI_EC
L
C
IRST#/GPIO05
C
P
_RST#
EC
C
_SCII#/GPIO0E
E GPIO1D
K
I0/GPIO30
S
K
I1/GPIO31
S
K
I2/GPIO32
S
K
S
I3/GPIO33
K
S
I4/GPIO34
K
S
I5/GPIO35
K
S
I6/GPIO36
K
I7/GPIO37
S
O0/GPIO20
KS
O1/GPIO21
KS KS
O2/GPIO22
KS
O3/GPIO23
KS
O4/GPIO24
KS
O5/GPIO25
KS
O6/GPIO26
KS
O7/GPIO27
K
O8/GPIO28
S
K
O9/GPIO29
S
K
O10/GPIO2A
S
K
O11/GPIO2B
S
K
S
O12/GPIO2C
K
O13/GPIO2D
S
K
S
O14/GPIO2E
K
S
O15/GPIO2F
K
O16/GPIO48
S
K
O17/GPIO49
S
E
_SMB_CK1/GPIO44
C
E
_SMB_DA1/GPIO45
C
E
_SMB_CK2/GPIO46
C
E
C
_SMB_DA2/GPIO47
_SLP_S3#/GPIO04
M
P
M
_SLP_S5#/GPIO07
P
C
_SMI#/GPIO08
E
P
IO0A
G
P
IO0B
G
IO0C
P
G
IO0D
P
G
C
_INVT_PWM/GPIO11
E
N_SPEED1/GPIO14
A
F
_PME#/GPIO15
C
E
_TX/GPIO16
C
E
_RX/GPIO17
C
E
C
H_PWROK/GPIO18
P
U
SP_LED#/GPIO19
S
M_LED#/GPIO1A
NU
X
C
LKI/GPIO5D
X
C
LKO/GPIO5E
1
2
+3VL
C & MISC
C & MISC
n
n
t. K/B
t. K/B
I
I Matrix
Matrix
SM Bus
SM Bus
885@
885@
B
B
19 330K_0402_5%
19 330K_0402_5%
R
R
1U_0402_6.3V6K
1U_0402_6.3V6K
B
50
50
B
C
C
@
@
9
22
_VDD/VCC
_VDD/VCC C
C
E
E
PS2 Interface
PS2 Interface
D/GND N G
11
+3VL
111
33
67
96
125
_VDD0 C E
_VDD/VCC
_VDD/VCC
_VDD/VCC
_VDD/AVCC
C
C
C E
E
C
E
E
PWM Output
PWM Output
DA Output
DA Output
SPI Device Interface
SPI Device Interface
SPI Flash ROM
SPI Flash ROM
GPIO
GPIO
D/GND N G
24
35
12
B
AD Input
AD Input
C
P
U1.5V_S3_GATE/GPXIOA00
V
B
TT_CHG_LED#/GPIO52
A
GPIO
GPIO
B
A
TT_LOW_LED#/GPIO55
P
E
_RSMRST#/GPXIOA03
C
E
_LID_OUT#/GPXIOA04
C
P
OCHOT_IN/GPXIOA05
R
H
_
PROCHOT#_EC/GPXIOA06
V
C
OUT0_PH/GPXIOA07
GPO
GPO
P
B
P
H_APWROK/GPXIOA10
C
S
A
GPI
GPI
P
CI_KB9012/GPXIOD07
E
D/GND
D/GND
D0
ND/AGND
N
N
G
G
G
A
GN
69
94
113
3
+
C
E
3
3
3
B
B
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2
21
IO0F
P
G
EP#/GPIO10
P
IO12
G
OFF/GPIO13
G
IO39
P
P_I/GPIO3A
G
P
IO3B
G
P
IO42
ON/GPIO43
EF/GPIO3E
R
PD/GPIO4D
IDI/GPIO5B
IDO/GPIO5C
BKL/GPIO40
G
P
XIOD06
V
1
23 26 27
63 64 65 66 75 76
68 70
8
5_EC_ON
8
71 72
83 84 85 86 87
T
_CLK
P
88
T
_DATA
P
97 98 99 109
119 120 126 128
73 74 89 90 91 92 93 95
S
Y
SON
121
V
R
_ON
127
100 101 102 103
H
PROCHOT_EC
_
104
V
OUT0_PH_L
C
105 106 107 108
110 112
E
_ON_R
C
114 115
L
ID_SW#
116
S
USP#
117 118
124
+
E
8R
C_V18R
Voltage Comparator Pins FOR 9012 A3
V
CIN0 pin109
VCIN1 pin102
V
COUT0 pin104
BE
AC
TT_TEMP/GPIO38
A
A
D
I
M
D
A
C_BRIG/GPIO3C
E
N
_DFAN1/GPIO3D
I
C
GVADJ/GPIO3F
H
E
_MUTE#/GPIO4A
C U
B_EN#/GPIO4B
S
C
P_INT#/GPIO4C
A
E
A
T
P
_CLK/GPIO4E
T
P
_DATA/GPIO4F
W
O
L_EN/GPXIOA01
M
E
_EN/GPXIOA02
C
IN0_PH/GPXIOD00
S
P
S
P
S
P
ICLK/GPIO58
S
P
ICS#/GPIO5A
E
N
P
E
CI_KB930/GPIO41
F
TCHG/GPIO50
S
C
A
PS_LED#/GPIO53
P
W
R_LED#/GPIO54
S
SON/GPIO56
Y
V
R
_ON/GPIO57
M
_SLP_S4#/GPIO59
B
K
OFF#/GPXIOA08
TN_OUT#/GPXIOA09
_PGOOD/GPXIOA11
A
_IN/GPXIOD01
C
E
C
_ON/GPXIOD02
O
N
/OFF/GPXIOD03
L
D_SW#/GPXIOD04
I
S
SP#/GPXIOD05
U
KB9012QF-A3_LQFP128_14X14
KB9012QF-A3_LQFP128_14X14
VL
_ON <35>
VCOUT1 pin103
e
e
curity Classification
curity Classification
curity Classification
e
S
S
S
s
s
sued Date
sued Date
sued Date
s
I
I
I
H
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
H
T
T
T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
W
L_BT_LED# <25>
B_EN#0 <24>
S
U
F
NPWM <5>
A
B
ATT_PRES <33>
B_OC#0 <24,8>
S
U
A
D
P_I <33,34>
A
P_V <34>
D
D
PLOCK <25>
H
H
PINT <25>
D
E
_MUTE# <26>
C
T
P
_CLK <30>
T
_DATA <30>
P
ATE <3 8>
G
V
U_DOWN# <13>
P
G
O
K <35>
1
B
B
15
15
C
C
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
P
V
C
IN0_PH <33>
E
_SPIDI <7>
C
C
_SPIDO <7>
E
E
C
_SPICLK <7>
E
C
_SPICS# <7>
L
D_ENBKL <20,6>
C
L_EN# <25>
O
W
H
PACT <25>
D
B
ATT_FULL_LED# <25>
C
PS_LED# <30>
A
B
A
TT_CHG_LOW_LED# <25>
S
Y
SON <31,36>
V
R
_ON <38>
ALW_APU_PW REN <31,35>
V
3
E
_RSMRST# <8>
C
E
_LID_OUT# <8>
C
R
OCHOT_IN <33>
P
B
K
OFF# <20>
P
TN_OUT# <8>
B
8_0.95VALW_PWR EN <37>
.
1
_PXCONTROL <8>
C
E
A
IN <34>
C
O
N
/OFFBTN# < 30>
L
D_SW# <30>
I
S
SP# <31,36>
U
C
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E
C
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E
V
CIN0_PH connect to
power portion ( 9012 only)
Nuvoton EC shar e ROM
H_PROCHOT_EC H/L, no PU/PD
P H/L, no PU/PD
>1.2V <1.2V
L
HIGH
L
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0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
2
2
2
OW
HIGH
o
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
C
C
C
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e
ciphered Date
ciphered Date
ciphered Date
e
D
D
D
1
@
@
14 0_0402_5%
14 0_0402_5%
B
B
R
R
BTN_OUT#
2
2
2
P
W
R_SUSP_LED# <25>
H
_
PROCHOT_EC
H
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1
VL
3
+
V
R
_ON
S
Y
SON
T
_DATA
P
T
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2
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8
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4
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2
1
@
@
R
R
34 0_0402_5%
34 0_0402_5%
B
B
1 2
R
R
21 10K_0402_5%
21 10K_0402_5%
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B
1
1
B
B
D
D
2
1
A
U_PROCHOT#
P
@ESD@
@ESD@
SCV00001K00
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lose to APU
A
U_PROCHOT#
P
Low Active (+3. 3V)
13
D
D
2N7002KW_SOT323-3
2N7002KW_SOT323-3
1
1
B
B
Q
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S
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C
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L
L
L
1
3
VS
+
V
S_ON <35>
A
PU_PROCHOT# <38,6>
f
f
9 4
f
9 4
9 4
2
2
o
o
2
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2
2
2
L
I
D_SW#
V
C
OUT0_PH_L
V
COUT0_PH connect to power portion (9012 only)
S
SP#
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T
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Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: S heet
Date: S heet
Date: S heet
.
.
0
0
0
.
1
1
1
Page 30
CyberForum.ru
5
Power Button Touchpad Connector
+
3
VL
02
02
2
2
R
R 100K_0402_5%
100K_0402_5%
1 2
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D D
N/OFFBTN#
1
2
2
4
4
C
C
D@
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S
E
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2
1U_0402_25V6
1U_0402_25V6
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. 0
0
3
ACES_50611-0040N-001
ACES_50611-0040N-001
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VS_LED
9
9
Q
Q
O3413_SOT23
O3413_SOT23
A
A
+
5
VS
C C
K
_LED<29>
B
R2
R2
10K_0402_5%
10K_0402_5%
KBL@
KBL@
2
G
G
1
04
04
2
13
D
D
S
S
D
S
D
S
13
KBL@
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G
G
2
Q
Q
1
1
0
0
2N7002KW_SOT323-3
2N7002KW_SOT323-3
KBL@
KBL@
+
5
VS_LED
5
O
N/O
P
P
WR
WR
J
J
112 3 556 778
4
FFBTN# <29>
@
@
2 4
4
6 8
O
FFBTN#
N/O
LG @
LG @
B
B
J
J
1
1
2
2
3
3
4
4
5
N
D
G
6
D
N
G
ACES_50578-0040N-001
ACES_50578-0040N-001
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VS
5
3
JT
JT
P
@
P
1
5
1
3
1
1 9 7 5 3 1
@
1
15
6
3
14
1
1
11
2 0
1
9
8
7
6
5
4
3
2
1
E-T_6900-G08N-00R
E-T_6900-G08N-00R
Lid SW
S
crew Hole
2
VS
+3
+
3
2
2
98
98
2
2
R
R
4.7K_0402_5%
4.7K_0402_5%
6
1
4
1
2
1 1
0 8 6
T
P
_SDATA1
4
T
P
_SCLK1
2
+
VS
3
T
_DATA <29>
P
T
_CLK <29>
P
+
VL
3
1
C
C
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
CPU
1
2
2
1
H
H
H
H
H
H
3
H_
4P2
4P2
H_
@
@
1
3
H_
H_
4P6
4P6
H_
H_
@
@
@
1
@
1
U
U
1
1
9
9
APX9132ATI-TRL_SOT23-3
APX9132ATI-TRL_SOT23-3
2
V
DD
18
18
2
2
4P2x4P6
4P2x4P6
T
P
T
P
_SCLK1
_SDATA1
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1
H
H
3
V
O
UT
C
C
10P_0402_50V8J
10P_0402_50V8J
V
A
G
5
5
H
H
3P3
3P3
H_
H_
@
@
1
2
99
99
R
R
4.7K_0402_5%
4.7K_0402_5%
1
1 2
DMN66D0LDW-7 2N_SOT363-6
DMN66D0LDW-7 2N_SOT363-6
L
I
D_SW# <29>
1
2
2
19
19
2
4
4
H_
3P3
3P3
H_
@
@
1
FCH
H
H
VS
2
61
5
Q
Q
8
8
A
A
DMN66D0LDW-7 2N_SOT363-6
DMN66D0LDW-7 2N_SOT363-6
2
1
1
2
H_7P0
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@
@
1
3
4
Q
Q
8
8
B
B
WLAN
2
2
H
H
9
9
1
H_3P3
H_3P3
@
@
1
A
PU_SCLK1 <8>
A
P
U_SDATA1 <8>
PTH
1
1
0
7
7
H
NEW KEYBOARD CONN.
K
I[0..7]
S
K
O[0..15]
B B
C
A
A A
5
S
PS_LED#<29> +
3
VS
4
4
R
R
300_0402_5%
300_0402_5%
K
I[0..7] <29>
S
K
O[0..15] <29>
S
12
K
I1
S
K
I6
S
K
I5
S
K
I0
S
K
S
I4
K
S
I3
K
SI2
K
S
I7
K
O15
S
K
O12
S
K
O11
S
K
S
O10
K
O9
S
K
SO8
K
S
O13
K
O7
S
K
O6
S
K
O14
S
K
S
O5
K
S
O3
K
SO4
K
SO0
K
O1
S
K
O2
S
B
B
K
K
J
J
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
1
0
0
1
1
1
1
1
2
1
2
1
1
3
3
1
1
4
4
1
5
1
5
1
1
6
6
1
1
7
7
1
1
8
8
1
9
1
9
1
2
0
0
2
2
1
1
2
2
2
2
2
3
2
3
2
4
2
4
2
25
5
2
6
2
6
2
7
2
7
2
2
8
8
2
2
9
9
2
3
0
0
3
1
3
1
3
3
2
2
3
3
3
3
3
4
3
4
3
35
D1
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G
36
D2
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CVILU_CF17341U0R0-NH
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@
@
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H
1
H
H
8
8
1
I
SPD
ZZ1
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Z0WJ00100
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D
D
P
CB LA-9868P
CB LA-9868P
P
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
ssu
ed Date
ssued Date
ed Date
ssu
T
T
T
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
0
H
H
4P0
4P0
H_
H_
@
@
1
1
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8
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H
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H_
@
@
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H
1
1
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@
@
2
2
2
0
12/09/27 2015/09/27
12/09/27 2015/09/27
012/09/27 2015/09/27
0
H_3P0
H_3P0
@
@
1
1
2
2
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H
H_3P0
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1
1
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4
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U
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CP
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U
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S
00006R330
00006R330
A
A
CP
CP
U A6-5200 25W 4C
U A6-5200 25W 4C
C
C
C
o
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mpal Secret Data
mpal Secret Data
o
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H
H
3
3
1
1
H_3P0
H_3P0
@
@
1
H
H
5
5
1
1
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@
@
1
4
4
@
@
X
X
X
X
5
5
@
@
D
D
D
e
ciphered Date
eciphered Date
ciphered Date
e
H
H
9
9
H_
3P2x3P7
3P2x3P7
H_
@
@
1
1
6
6
1
H
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H_3P2
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00006R400
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U A4-5000 15W 4C
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CP
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U
A
A
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S
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2
X
X
X
X
4
4
5
5
NPI@
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1
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@
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1
4
4
R1@
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C1
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U
U
A
A
00006R410
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S
S
CP
CP
U A4-5000 15W 4C
U A4-5000 15W 4C
5
R1@
R1@
5
X
X
C1
C1
U
U
A
00006R310
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A
S
S
CP
U A6-5200 25W 4C
U A6-5200 25W 4C
CP
T
T
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i
K
K
K
B
B
/TP/LED/LID/DEBUG/ISPD
/TP/LED/LID/DEBUG/ISPD
/TP/LED/LID/DEBUG/ISPD
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
B
F
F
F
F
D4
D3
D4
D3
@
@
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C
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1
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2Thursday, May 16, 2013
2Thursday, May 16, 2013
2Thursday, May 16, 2013
Page 31
CyberForum.ru
5
+5VALW
6
6
C
C
1
@
@
1
1 U
U _0402_6.3V6K
_0402_6.3V6K
2
D D
+
3
@
@
N 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm
VALW
VI
S
USP#
+
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5
1
C
C
1
1
0
0
1
1 U
U _0402_6.3V6K
_0402_6.3V6K
2
SUS
P#
U
U
1
1
1 2
3
4
5
6 7
+
VALW TO +5VS
5
V
V
O
I
UT1
N1
V
V
O
V
O
V V
PS22966DPUR_SON14_2X3
PS22966DPUR_SON14_2X3
T
T
UT1
N1
O
I
C
1
1
N
T
G
N
B
IAS
N
N2
I I
N2
D
C
2
2
T
V
UT2
O
V
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UT2
G
P
AD
+3VALW TO +3VS
14
+
VS_LS
5
13
12
11
10
9 8
+3
15
VS_LS
Load switch
C
C
180P_0402_50V8J
180P_0402_50V8J
5
5
1 2
9
9
330P_0402_50V7K
330P_0402_50V7K
C
C
1 2
4
P
P
J6
J6
1 2
JUM
JUM
P
P
J7
J7
@
@
1 2
JUM
JUM
P_43X118
P_43X118
@
@
P_43X118
P_43X118
+
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3
@ C
@
3
+
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5
+5
VS
2
7
7
C
@ C
@
0
0 .
.
1U_0402_10V7K
1U_0402_10V7K
1
2
8
8
C
0
0 .
.
1U_0402_10V7K
1U_0402_10V7K
1
C
C
1
1
1
@
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1U _0402_6.3V6K
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2
4
4
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I
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DD_
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5
1
3
3
1
1
C
1
1 U
U _0402_6.3V6K
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2
2
2
2
U
U
1 2
3
4
5
S
US
P#
6 7
+
.8VALW TO +1.8VS
1
VO
VI VI
ON
VB
ON
V V
T
T
PS22966DPUR_SON14_2X3
PS22966DPUR_SON14_2X3
UT1
N1
VO
UT1
N1
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I
N2
I
N2
1
1
CT
D
GN
2
2
CT
UT2
VO
UT2
VO
AD
GP
1
+
VS_ODD
5
@
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PJ8
J9
J9
P
P
1
JUM
JUM
PJ8
1 2
JUM
JUM
P_43X79
P_43X79
+
1.8VS
@
@
2
P_43X79
P_43X79
@
@
2
C
@ C
@
5
5
1
1
0
0 .
.
1U_0402_10V7K
1U_0402_10V7K
1
2
C
C
1
1
6
6
0
0 .
.
1U_0402_10V7K
1U_0402_10V7K
1
14
+
VS_ODD_LS
5
13
12
11
10
9 8
15
+
1
C
C
C
C
.8VS_LS
1
1
1
1
1
1 2
2 180P_0402_50V8J
2 180P_0402_50V8J
2
1 330P_0402_50V7K
1 330P_0402_50V7K
+5VS TO +5VS_ODD Load switch
+
0
.95VALW to +0.95VS
+
0
C C
+
.95VALW
0
1
1
1
1
Q
Q
8
D
7
D
6
D
5
D
FDS6676AS_SO8
FDS6676AS_SO8
+
.95VS
0
V
g
s=10V,Id=14.5A,Rds=6mohm
1
S
2
S
3
S
4
G
C2
C
Q
1
1_GATE
1
1
R
R
2
2
17
2
50
50
2
17
820K_0402_5%
820K_0402_5%
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
2
1U_0402_25V6
1U_0402_25V6
0.
0.
1
16
16
2
2
R
R
220K_0402_5%
220K_0402_5%
6
A
A
2
2
Q
Q
2
1
2
R
R
2
2
14
14
0_0805_5%
0_0805_5% 7
7 4
4
B
+
1 2
3
2
2
B
B
Q
Q
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
4
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
+
.5V
1
+
VALW
2
2
R
R
100K_0402_5%
100K_0402_5%
S
YSON#
5
5
12
12
1 2
34
Q
Q
3B
3B
2
R
R
11
11
2
2
470_0805_5%
470_0805_5%
1 61
Q
Q
A
3A
3
2
S
Y
SON#
S
SON<29,36>
Y
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
+
VALW_APU
3
21
21
2
2
R
R 470_0805_5%
470_0805_5%
1 2
61
Q
Q
5
5
A
A
2
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
3
ALW_APU_PWREN
V
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
5
+
VALW
5
2
1
3
4
19
19
2
2
R
R 100K_0402_5%
100K_0402_5%
Q
Q
5
5
B
B
.75VS
2
2
2
13
13
R
R 470_0805_5%
470_0805_5%
1
61
4
4
A 2N7002KDWH_SOT363-6
A 2N7002KDWH_SOT363-6
Q
Q
2
S
USP
S
USP#<29,36>
S
US
P
5
S
US
P#
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
+
VALW
5
2
1
34
R
R
215
215
100K_0402_5%
100K_0402_5%
Q
Q
4B
4B
0
.95VS_PWREN#<29>
B B
E
+
1
.5V to +1.5VS
+
1
.5VS
+
.5V
1
Q
Q
1
1
S
S
2
G
G
D
D
O3419L_SOT23-3
O3419L_SOT23-3
A
A
1 3
+
.5VS
A A
1
S
P
US
1
2
53
53
2
C
C
2
1U_0402_25V6
1U_0402_25V6
.
. 0
0
5
2
R222
R222 470_0805_5%
470_0805_5%
1
1
D
D
6
6
Q
2
G
G
Q 2
N7002KW_SOT323-3
N7002KW_SOT323-3
2
S
S
3
MI Cap.
Please check location
B
+
2
0
8
8
1
1
C
C
1
2
1U_0402_25V6
1U_0402_25V6
.
. 0
0
E
MI@
MI@
E
@
@
4
0
2
C
C
C
C
19
19
1
2
@
@
MI@
MI@
E
E
2
2
1
1
C
C
1
1
2
2
1U_0402_25V6
1U_0402_25V6
1U_0402_25V6
1U_0402_25V6
.
.
1U_0402_25V6
MI@
MI@
1U_0402_25V6
.
.
0
0
0
0
E
E
MI@
MI@
@
@
.
. 0
0
E
E
@
@
C
C
@
@
+
3
VALW to +3VALW_FCH
+
VALW
3
2
3
3
2
1
2
_0402_6.3V6K U
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1
E
SD@
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3
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ALW_APU_PWREN<29,35>
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
ssu
ssu
ed Date
ed Date
ed Date
ssu
T
T
T
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+
3
VL
2
24
24
2
R
R
10K_0402_5%
10K_0402_5%
885@
885@
1 2
3
V
2
2
2
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
10K_0402_5%
10K_0402_5%
ALW_APU_PWREN
12
R
R 100K_0402_5%
100K_0402_5%
9012@
9012@
C
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
o
D
D
D
R
R
2
18
18
2
@
@
5
23
23
2
2
e
e
ciphered Date
ciphered Date
ciphered Date
e
2
1
1
2
2
20 47K_0402_5%
20 47K_0402_5%
R
R
34
Q
Q
C1
C1
B
B
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
@
@
2
+
3VALW
2
2
@
@
2
51
51
2
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
1
AO3413_SOT23
AO3413_SOT23
2
@
@
2
52
52
2
C
C
0.01U_0402_25V7K
0.01U_0402_25V7K
1
V
s=-4.5V,Id=3A,Rds<97mohm
g
1
S
S
@
@
J4
J4
P
G
G
2
1 3
T
T
i
itle
tle
tle
i
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
P JUM
JUM
P_43X39
P_43X39
@
@
2
2
1
1
Q
Q
D
D
2
+
VALW_APU
3
C
C
C
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
D
D
D
C
TO DC INTERFACE
C TO DC INTERFACE
TO DC INTERFACE
C
L
L
L
A
-9868P
-9868P
-9868P
A
A
1
3
o
3
3
o
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f
1 42Thursday, May 16, 2013
f
1 4
1 4
1
1
1
.0
.0
.0
2Thursday, May 16, 2013
2Thursday, May 16, 2013
Page 32
CyberForum.ru
A
E
I Part (47.1)
M
O
ther component (37.1)
A
51 need add fuse
1 1
@
@
P
P
1
1
JP
JP
1
1
2
2
3
3
4
4
ACES_50299-00401-001
ACES_50299-00401-001
2 2
P
P
F1
F1
21
7
7
A_32V_S1206-H-7.0A
A_32V_S1206-H-7.0A
- +
D
C_
IN_S1
P
P
J101 @
J101 @
B
B
ML1220T13RE
ML1220T13RE
12
EMI@
EMI@
P
P
02
02
C1
C1
1000P_0603_50V7K
1000P_0603_50V7K
For ML1220 RTC (38.2)
P
P
R1
R1
560_0603_5%
560_0603_5%
12
1
P
P
1
EMI@
1
EMI@
L
L
HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
1 2
P
L3
EMI@PL3
EMI@
HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
1
12
EMI@
EMI@
P
P
C1
C1
03
03
100P_0603_50V8
100P_0603_50V8
P
P
R1
R1
02
2
+
RT
02
560_0603_5%
560_0603_5%
1 2
C_R
01
01
2
B
12
P
P
C1
C101
01
100P_0603_50V8
100P_0603_50V8
+
C
RT
EMI@
EMI@
V
IN
12
EMI@
EMI@
P
P
04
04
C1
C1
1000P_0603_50V7K
1000P_0603_50V7K
C
For RTC (38.2)
+
R
TC_APU_R
3
2
AP2138N-1.5TRG1_SOT23-3
AP2138N-1.5TRG1_SOT23-3
12
10
10 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
D
P
P
U1
U1
V
o
ut
1
V
i
n
G
ND
1
2
+
TC
R
9
9 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
3 3
4 4
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
ssu
ssued Date
ed Date
ed Date
ssu
T
T
T
H
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
2
2
12/09/27 2015/09/27
012/09/27 2015/09/27
12/09/27 2015/09/27
0
0
C
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
o
D
D
D
e
eciphered Date
ciphered Date
ciphered Date
e
C
C
C
C
o
mpal Electronics, Inc.
ompal Electronics, Inc.
mpal Electronics, Inc.
T
T
T
i
tle
tle
itle
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
u
stom
stom
stom
u
u
Date: Sheet
Date: Sheet
Date: Sheet
o
D
D
D
C
IN/PRECHARGE
IN/PRECHARGE
IN/PRECHARGE
C
C
L
L
L
A
-9868P
-9868P
-9868P
A
A
D
o
o
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32 42
32 42
32 42
f
f
1
1
1
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Page 33
CyberForum.ru
A
1
.
0
1
.
0
1
.
0
Other component (37.1)
@
@
ACES_50299-01001-W01
ACES_50299-01001-W01
1
1
2
2
3
3
4
4
5
5
6
6
7
7
1 1
2 2
8
8
9
9
0
1
1
0
P
P
2
2
JP
JP
B
TT_S1
A
EC
_SMCA
P
P
R
R
100_0402_1%
100_0402_1%
B
TT_P4
A
B
TT_P5
A
EC_SMDA
20
20
1 2
P
P
F
F
2
2
10A_125V_TR2/6125FF10-R
10A_125V_TR2/6125FF10-R
P
P
R21
R21
100_0402_1%
100_0402_1%
1 2
21
1
P
P
R
R
1K_0402_1%
1K_0402_1%
2
14
14
P
P
16
16
R
R
6.49K_0402_1%
6.49K_0402_1%
P
P
19
19
R
R
1 2
1K_0402_1%
1K_0402_1%
12
E
_SMB_DA1 <24,29,34>
C
E
_SMB_CK1 <24,29,34>
C
VM
+
VL
3
B
TT_PRES <29>
A
B
B
HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
1 2
HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
1 2
1
P
P
C
C
7
7
EMI@
EMI@
1000P_0402_50V7K
1000P_0402_50V7K
2
P
P
4
EMI@
4
EMI@
L
L
EMI@
EMI@
P
P
5
5
L
L
EMI Part (47.1)
B
ATT+
12
EMI@
EMI@
P
P
C
C8
8
0.01U_0402_25V7K
0.01U_0402_25V7K
C
O
P (39.7)
T
A
DP_I<29,34>
@PR2
@
0_0402_5%
0_0402_5%
P
R
OCHOT_IN<29>
1 2
2
1
1 R
R P
P
1
1K_0402_1%
P
R2
1K_0402_1%
V
IN0_PH<29>
C
2
3
3 R
R P
P
1
20K_0402_1%
20K_0402_1%
D
P
P
R
R
5
@
5
@
0_0402_5%
0_0402_5%
1 2
12
P
P
11
@
11
@
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
+
VL
3
12
4 R
R4 P
P
12.1K_0402_1%
12.1K_0402_1%
12
1
1 H
H P
P
100K_0402_1%_TSM0B104F4251RZ
100K_0402_1%_TSM0B104F4251RZ
3 3
4 4
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
s
s
sued Date
sued Date
sued Date
s
T
T
T
H
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
2
2
2
0
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
C
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
o
C
D
D
D
e
e
ciphered Date
ciphered Date
ciphered Date
e
C
C
C
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
T
T
T
i
tle
tle
tle
i
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
stom
stom
u
u
Date: S heet
Date: S heet
Date: S heet
o
B
B
B
A
TTERY CONN / OTP
TTERY CONN / OTP
TTERY CONN / OTP
A
A
L
L
L
A-9868P
-9868P
-9868P
A
A
D
o
o
o
f
f
33 42
33 42
33 42
f
Page 34
CyberForum.ru
A
B
C
D
for reverse input protection
arger controller (40.1), Support component (40.2)
P
P
211
211
R
R
0.01_1206_1%
0.01_1206_1%
1
2
1 2
P
P
236
236
C
C
B Q 24725_ACP
Q
24725_CMSRC
24725_ACDRV
Q
1
2
Ch
4
3
12
B Q 24725_ACN
B
Q
24725_ACOK
244
244 C
C P
P
0.1U_0402_25V6
0.1U_0402_25V6
B
235
235 C
C P
P
0.1U_0402_25V6
0.1U_0402_25V6
P
P
C
C
1 2
1U_0603_25V6K
1U_0603_25V6K
21
1
2
3
4
5
12
244
244 R
R P
P
422K_0402_1%
422K_0402_1%
1
245
245 R
R P
P
2
66.5K_0402_1%
66.5K_0402_1%
100P_0402_50V8J
100P_0402_50V8J
E
MI Part (47.1)
+
V
I
N
3
2
1
1
2
24725_VCC
239
239
Q B
20
U
U
200
200
P
P
C C V
D
A
P
N
C
A
P
C
A
M
SRC
C
DRV
C
A
OK
C
A
DET C A
6
24725_ACDET Q B
C
245
245
C
P
P
12
B
EMI@
EMI@
L
201
201
L
P
1UH_NRS4018T1R0NDGJ_3.2A_30%
1UH_NRS4018T1R0NDGJ_3.2A_30%
D
D
230
230
P
P BAS40CW_SOT323-3
BAS40CW_SOT323-3
1 2
228
228 R
R P
P
10_1206_1%
10_1206_1%
24725_LX Q B
19
ASE H P
UT O
I
7
S
S
S
e
e
curity Classification
curity Classification
curity Classification
e
I
I
I
s
s
ssued Date
T
T
T
H
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
P
1 2
1
207
207
C
C
P
P 1U_0603_25V6K
1U_0603_25V6K
2
0.047U_0402_25V7K
0.047U_0402_25V7K
P
P
237
237
C
C
1
229
229 R
R P
P
2
2.2_0603_5%
2.2_0603_5%
_CHG
24725_BST
H
Q
D
B
17
18
ST T
DRV
I
B
H
A
L
D
C S
S
8
9
246
@
246
@
R
R
P
P
0_0402_5%
0_0402_5%
1 2
sued Date
sued Date
@
@
12
24725_REGN Q B
16
GN E R
O
L
TDRV
A
B
IM L
I
10
B
12
1
211
211 C
C P
P
2
10U_0805_25V6K
10U_0805_25V6K
1
1
214
214
213
213
C
C
C
C P
P
P
2
D
D
231
231
P
P RB751V-40_SOD323-2
RB751V-40_SOD323-2
D
H
_CHG
P
P
205
205
C
C
2
1
1U_0603_25V6K
1U_0603_25V6K
15
D
_CHG
L
DRV
14
D
N
G
13
S
RP
R
P
S
12
S
R
N
R
S
11
B
Q
BQ24725RGRR_QFN20_3P5X3P5
BQ24725RGRR_QFN20_3P5X3P5
Q
24725_ILIM
12
243
242
242
C
C243 P
P
PR
PR
100K_0402_1%
100K_0402_1%
0.01U_0402_25V7K
0.01U_0402_25V7K
E
E
A
12
C
C
246
@
246
@
P
P
0.1U_0402_10V7K
0.1U_0402_10V7K
P
l
ease locate the RC Near EC chip 2011-02-22
2
2
2
0
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
P
2
10U_0805_25V6K
10U_0805_25V6K
@EMI@
@EMI@
1 2
P
P
R
R
210
210
@
@
0_0603_5%
0_0603_5%
236
236
R
R
P
P
10_0603_1%
10_0603_1%
1 2
C
R
237
237
R
P
P
6.8_0603_5%
6.8_0603_5%
1 2
N
24725_BATDRV
C
1 2
P
P
R
241
241
R
590K_0402_1%
590K_0402_1%
_SMB_CK1 <24,29,33>
C
C
_SMB_DA1 <24,29,33>
D
P_I <29,33>
2200P_0402_25V7K
2200P_0402_25V7K
5
4
4
SOP1
12
S
ON1
P
P
C242
C242
0.1U_0603_16V7K
0.1U_0603_16V7K
+
5
VALW
C
C
C
o
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
D
D
D
e
e
e
ciphered Date
ciphered Date
ciphered Date
P
P AON7408L
AON7408L
123
B
Q
5
AON7406L
AON7406L
123
B
Q
24725_BATDRV
201
201
Q
Q
P
P
202
202
L
202
202
1 2
1
206
206 R
R P
P
MI@
MI@
2
E
E @
@
12
206
206 C
C P
P
@EMI@
@EMI@
L
4.7_1206_5%
4.7_1206_5%
680P_0603_50V8J
680P_0603_50V8J
4.7UH_ETQP3W4R7WF N_5.5A_20%
4.7UH_ETQP3W4R7WF N_5.5A_20%
24725_LX
Q
Q
P
P
EMI Part (35.33)
309K_0402_1%
309K_0402_1%
47K_0402_1%
47K_0402_1%
For A51 ADP_V function
C
1
R
R
233
233
P
P
4.12K_0603_1%
4.12K_0603_1%
C
H
G
OP1 S C
12
V
I
12
P
P
247
247
R
R
1
P
P
249
249
R
R
2
5
2
B
Q
1
2
240
240 C
C P
P
N
S TR SI7716ADN
S TR SI7716ADN
207
207
PQ
PQ
24725_BATDRV_1
P
P
R
R
0.01_1206_1%
0.01_1206_1%
0.1U_0402_25V6
0.1U_0402_25V6
1 2 3
4
227
227
1
0.1U_0402_10V7K
0.1U_0402_10V7K
2
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: S heet
Date: S heet
Date: S heet
4
3
ON1 S C
12
10K_0402_1%
10K_0402_1%
1 2
@
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C
C
P
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C
C
C
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234 C
C P
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0.01U_0402_50V7K
12
221
221 C
C P
P
241
241 C
C
@
@
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P
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0402_25V6
248
248
PR
PR
247
247
C
C
C
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
C
C
C
H
ARGER
ARGER
ARGER
H
H
L
L
L
12
222
222 C
C P
P
10U_0805_25V6K
10U_0805_25V6K
A
-9868P
A-9868P
-9868P
A
A
12
P_V <29>
D
C223
C223 P
P
10U_0805_25V6K
10U_0805_25V6K
B
A
TT+
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o
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f
f
34 42
34 42
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f
D
1
1
1
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.
.
13
D
D
2
226
226
R
R
P
1 2 3
24725_ACDRV_1
Q
P
1 2
3M_0402_5%
3M_0402_5%
P
1
P
P
R
R
225
225
1 2
1M_0402_5%
1 1
2 2
3 3
1M_0402_5%
TPCA 8057
TPCA 8057
V
I
N
P
P
203
203
Q
Q
5
12
4
230
230 C
C P
P
B
2200P_0402_50V7K
2200P_0402_50V7K
G
G
209
209
PQ
PQ 2N7002FU_SOT23
2N7002FU_SOT23
S
S
SI7716ADN-T1-GE3_POWERPAK8-5
SI7716ADN-T1-GE3_POWERPAK8-5
1 2 3
12
231
231 C
C P
P
0.1U_0402_25V6
0.1U_0402_25V6
12
12
235
235
234
234
R
R
R
P
PR
P
P
4.12K_0603_1%
4.12K_0603_1%
4.12K_0603_1%
4.12K_0603_1%
P
P
205
205
Q
Q
4
P
2
5
0.1U_0402_25V6
0.1U_0402_25V6
1
238
238 C
C P
P
2
0.1U_0402_25V6
0.1U_0402_25V6
B
B
+
VL
3
A
CIN<29>
V
N
I
1 2
R
R
239 10K_0402_1%
239 10K_0402_1%
P
P
Vin Dectector
Min. Typ Max. H-->L 17.23V L--> H 17.63V
ILIM and external DPM
3.97A
4 4
A
Page 35
CyberForum.ru
A
5VALW controller (35.1), Support component (35.2)
3/
3V
1 1
E
MI Part (47.1)
B
+
EMI@
EMI@
331
331
L
L
P
P
HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
1 2
2 2
+
3
VALWP
3
5V_B+
/
12
12
339
339 C
C P
P
2200P_0402_50V7K
2200P_0402_50V7K
@EMI@
@EMI@
340
340 C
C P
P
10U_0805_25V6K
10U_0805_25V6K
332
332
L
L
P
P
4.7UH_ETQP3W4R7W FN_5.5A_20%
4.7UH_ETQP3W4R7W FN_5.5A_20%
1
+
+
354 C354
C P
P
2
150U_D2_6.3VY_R15M
150U_D2_6.3VY_R15M
12
331
331 Q
Q P
P
AON7408L
AON7408L
2
1
12
336
336 R
R P
P
4.7_1206_5%
4.7_1206_5%
@EMI@
@EMI@
UB_3V
1
2
N S
12
336
336 C
C P
P
680P_0603_50V8J
680P_0603_50V8J
@EMI@
@EMI@
ALW_APU_PWREN<29,31>
5
4
P
P
335
335
C
C
0.1U_0402_10V7K
4
AON7406L
AON7406L
332
332
Q
Q
P
P
0.1U_0402_10V7K
1
3
5
3
EMI Part (35.33)
3 3
3
.
3V Peak Current 8A OCP current 10A Delta I=1.160A ,ripple=1.160 x17m=19.27mV FSW=455kHz DCR 35mohm +/-15% TYP MAX H/S Rds(on) :27mohm , 34mohm L/S Rds(on) :19mohm , 23.5mohm
B
P
P
333
333
Q
Q
S
2N7002FU_SOT23
2N7002FU_SOT23
P
P
330
330
R
R
14K_0402_1%
14K_0402_1%
1 2
R
R
331
331
P
P
20K_0402_1%
20K_0402_1%
1
V
L
P
K<29>
O
12
335
335 R
R P
P
P
P
33
@
33
@
3
3
0_0402_5%
0_0402_5%
2
1 2
B
T1_3V
S
3
5V_B+
/
E
C_ON<29>
V
S
_ON<29>
B
T_3V
S
U
G
_3V
L
X
_3V
L
_3V
G
P
P
499K_0402_1%
499K_0402_1%
1
1
360
360 C
C P
P
2
0.1U_0603_25V7K
0.1U_0603_25V7K
@
@
P
P
0_0402_5%
0_0402_5%
1 2
G
G
2
2
F
B
_3V
100K_0402_1%
100K_0402_1%
6
7
8
9
10
R
R
334
334
2
R
R
340
340
P
P
2.2K_0402_1%
2.2K_0402_1%
1 2
R
341
341
R
S
339
339 R
R P
P
D
D
1 3
OOD
G
P
OT2
O
B
G
ATE2
U
H
ASE2
P
ATE2
G
L
12
338
338 R
R P
P
100K_0402_1%
100K_0402_1%
0_0402_5%
0_0402_5%
@
@
1 2
P
P
350
350
R
R
30K_0402_1%
30K_0402_1%
1
2
2
2
342
342
337
337
357
357
R
R
R
R
R
R
P
P
P
P
P
P
56K_0402_1%
56K_0402_1%
1
1
1
210K_0402_1%
210K_0402_1%
174K_0402_1%
174K_0402_1%
2
3
4
5
2
N
B
O
F
T
TRIP1
TRIP2 N
N
E
E
LDO
CFB
O5
E
S
13
E
NLDO<25>
1 2
D L
14
15
12
4.7U_0603_10V6K
4.7U_0603_10V6K
332
332 R
R P
P
@
@
100K_0402_5%
100K_0402_5%
O3 D L
N
I
N
V
E
11
12
12
342
342 C
C P
P
1U_0603_10V6K
1U_0603_10V6K
1
343
343 C
C P
P
2
@
@
4.7U_0805_25V6-K
4.7U_0805_25V6-K
P
P
R
R
351
351
19.1K_0402_1%
19.1K_0402_1%
1 2
F
B
_5V
1
1 B
21
F
A
D
P
20
P1
Y
B
19
O
OT1
B
18
G
ATE1
U
17
H
ASE1
P
16
G
ATE1
L
PU330
PU330
T
T
8243AZQW_WQFN20_3X3
8243AZQW_WQFN20_3X3
R
R
V
L
344
344
C
C
P
P
+
3VLP
(
B
S
U
G
L
X
L
G
12
4.7U_0603_10V6K
4.7U_0603_10V6K
100mA,20mils ,Via NO.= 1)
_5V
T_5V
_5V
_5V
2
+
P
P
VLP
3
C
C
341
341
C
P
P
3
355
@
@
0_0402_5%
0_0402_5%
1 2
@
@
P
P
2
JUMP_43X39
JUMP_43X39
55
J3
J3
112
32
32
0.1U_0402_10V7K
0.1U_0402_10V7K
B
T1_5V
S
3
5V_B+
/
12
361
361 C
C P
P
10U_0805_25V6K
10U_0805_25V6K
C
355
355
C
P
P
1 2
FDMC7692S_MLP8-5
FDMC7692S_MLP8-5
+
3
VL
D
P
P
351
351
Q
Q
AON7408L
4
4
352
352
Q
Q
P
P
AON7408L
1
2
3 5
2.2UH_MMD-06CZ-2R2M-V1_8A_20%
2.2UH_MMD-06CZ-2R2M-V1_8A_20%
5
3
1
2
UB_5V N S
1
2
12
P
P
352
352
L
L
2
1
EMI Part (47.1)
356
356 R
R P
P
4.7_1206_5%
4.7_1206_5%
@EMI@
@EMI@
356 C
C356 P
P
680P_0603_50V8J
680P_0603_50V8J
@EMI@
@EMI@
1
+
+
353
353 C
C P
P
2
150U_D2_6.3VY_R15M
150U_D2_6.3VY_R15M
5V Peak Current 12A OCP current 14A FSW=390kHz Delta I=2.791A,ripple=2.791*15m=41.865mV DCR 18~20mohm TYP MAX H/S Rds(on) ::27mohm , 34mohm L/S Rds(on) :10.8mohm , 13.6mohm
P
P
J3
J3
31
@
31
@
2
1
2
+
3
+
5
VALWP
(
8A,160mils ,Via NO.= 16)
VALWP
(12A,240mils ,Via NO.= 24)
1
JUMP_43X118
JUMP_43X118
@
@
112
JUMP_43X118
JUMP_43X118
+
VALW
3
P
P
J3
51
51
J3
2
+
VALW
5
+
5
VALWP
4 4
S
S
S
e
e
curity Classification
curity Classification
curity Classification
e
I
I
I
s
sued Date
sued Date
sued Date
s
s
T
T
T
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
H
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
2
2
2
0
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
C
C
C
o
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
D
D
D
e
ciphered Date
ciphered Date
ciphered Date
e
e
C
C
C
C
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
T
T
T
i
i
tle
tle
tle
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
u
stom
stom
stom
u
u
Date: S heet
Date: S heet
Date: S heet
o
3
3
3
V
V
ALW/5VALW
VALW/5VALW
ALW/5VALW
o
o
o
f
f
35 42
35 42
35 42
f
D
1
1
1
.
0
0
0
.
.
Page 36
CyberForum.ru
D
R controller (35.3), Support component (35.4)
D
EMI@
EMI@
P
P
151
151
L
B
+
L
HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
1 2
1
5V_B+
.
M
I Part (47.1)
E
BS
T_1.5V-1
P
P
R
R
155
155
2.2_0603_5%
2.2_0603_5%
1 2
A
S
T_1.5V
B
+
1
.5V
H
_1.5V
VALW
D
P
P
R
159
159
R
5.1_0603_5%
5.1_0603_5%
1 2
P
P
C
C
1U_0603_10V6K
1U_0603_10V6K
12
C
166
@
166
@
C
P
P
0.1U_0402_10V7K
0.1U_0402_10V7K
SW_1.5V
DL_1.5V
1
164
164
2
E
12
@EMI@
@EMI@
C152
C152 P
P
2200P_0402_50V7K
2200P_0402_50V7K
L
L
152
152
P
1UH_VMPI0703AR-1R0M-Z01_11A_20%
+
1
.5VP
1 1
@
@
+
.75VSP
0
(0.5A,40mils ,Via NO.= 1)
2
JUMP_43X79
JUMP_43X79
1UH_VMPI0703AR-1R0M-Z01_11A_20%
1
+
+
157
157 C
C P
P
2
P
P
J7
50
50
J7
112
P
12
1
220U_6.3V_M
220U_6.3V_M
+
.75VS
0
2
SNUB_+1.5VP
12
1
154
154
2
C
C P
P
10U_0805_25V6K
10U_0805_25V6K
151
151 Q
Q P
P
AON7408L
AON7408L
123
152
EMI@
EMI@
R
R
156
156
P
P
4.7_1206_5%
4.7_1206_5%
EMI@
EMI@
C
C
156
156
P
P
680P_0402_50V7K
680P_0402_50V7K
+
.5VP
1
(12A, 480mils ,Via NO.= 24) OCP=13.8A
152 Q
Q P
P
FDMC7692S_MLP8-5
FDMC7692S_MLP8-5
1
S
Y
SON<2 9,31>
@
@
2
2
JUMP_43X118
JUMP_43X118
@
@
2
2
JUMP_43X118
JUMP_43X118
P
P
P
P
155
155 C
C P
P
1
1
4
4
@
@
0_0402_5%
0_0402_5%
1 2
1 2
0.1U_0603_25V7K
0.1U_0603_25V7K
+
5
R
163
163
R
P
P
+
1
.5V
5
5
2
3
J1
J1
51
51
1
J1
J1
52
52
1
P
P
P
P
R
R
17.4K_0402_1%
17.4K_0402_1%
1 2
C
C
P
P
1U_0603_10V6K
1U_0603_10V6K
1 2
V
DD_1.5V
_1.5V
N
S
U
1 2
@
@
157 0_0603_5%
157 0_0603_5%
R
R
158
158
CS_1.5V
162
162
+
5VALW
887K_0402_1%
887K_0402_1%
1.5V_B+
SP#<29,31>
15
L
G
14
P
G
13
C
S
12
V
D
11
V
D
R
161
161
R
P
P
1 2
ATE
ND
DP
D
1 2
16
18
17
OT
ATE
O
G
HASE
B
P
U
RT8207MZQW_W QFN20_3X3
RT8207MZQW_W QFN20_3X3
OOD
N
5
G
O T
S
P
8
9
10
TON_1.5V
P
P
164
@
164
@
R
R
0_0402_5%
0_0402_5%
20
19
T T
V DOIN L V
V
TGND
T
V
TSNS
T
V
TTREF
V
3
B S
F
6
7
_0.75VSP N E
12
@
@
P
P
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
+
0
.75VSP
1
12
159
159 C
C
C160
C160 P
P
P
P
P
U
U
150
150
21
P
D
A
1
2
3
G
D
N
4
V
T
TREF_1.5V
5
DQ
D
R
160
160
R
P
P
10.2K_0402_1%
10.2K_0402_1%
F
_1.5V
B
P
P 10K_0402_1%
10K_0402_1%
1 2
167
167
12
R
R
162
162
P
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
+
.5VP
1
+
1
.5VP
12
P
P
C
163
163
C
0.033U_0402_16V7K
0.033U_0402_16V7K
1.5V Peak Current 12A OCP current 13.82A FSW=500kHz DCR 8.3 ~ 10mohm TYP MAX H/S Rds(on) :27mohm , 34mohm L/S Rds(on) :10.8mohm , 13.6mohm
STATE S3 S5 1.5VP VTT_REFP 0.75VSP
S0
Hi Hi
S3
S4/S5
HiLo
Lo Lo
Note: S3 - sleep ; S5 - power off
On
On
Off (Discharge)
On
On
Off (Discharge)
On
Off (Hi-Z)
Off (Discharge)
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
s
s
sued Date
sued Date
sued Date
s
T
T
T
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
H
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
2
2
2
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
C
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
o
D
D
D
e
e
ciphered Date
ciphered Date
ciphered Date
e
C
C
C
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
T
T
i
Title
tle
tle
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
u
u
stom
ustom
stom
Date: S heet
Date: S heet
Date: S heet
o
1
1
1
.
5VP/0.75VSP/1.8VSP
5VP/0.75VSP/1.8VSP
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.
L
L
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A-9869P
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36 42
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Page 37
CyberForum.ru
A
1
8V controller (35.15), Support component (35.16)
.
1 1
+3
VALW
12
C458
C458 P
P
22U_0603_6.3V6M
P
P
452
@
452
@
R
R
0_0402_5%
0_0402_5%
1
.
8_0.95VALW_PWREN<29>
@
@
J
J
451
451
P
P
2
+
.8VALWP
2 2
1
112
JUMP_43X79
JUMP_43X79
(
2.5A,100mils ,Via NO.=5)
+
1
.8VALW
1 2
@
@
P
P
C
C
0.1U_0402_16V7K
0.1U_0402_16V7K
453
453
22U_0603_6.3V6M
+
1
.8_EN
12
B
Need create Symbol.
N
ote:Iload(max)=3A
P
P
U
450
450
U
1UH_NRS4018T1R0NDGJ _3.2A_30%
1UH_NRS4018T1R0NDGJ _3.2A_30%
4
I
N
5
P
G
6
F
B
3
L
X
2
G
N
D
1
E
N
SY8032ABC_SOT23-6
SY8032ABC_SOT23-6
1 2
FB=0.6V
P
P
L
L
451
451
P
P
R
R
100K_0402_1%
100K_0402_1%
P
P
R
R
49.9K_0402_1%
49.9K_0402_1%
C
D
1.8V Peak Current 2.5A
+
1
12
451
451
1
453
453
2
12
450
450 C
C P
P
22P_0402_50V8J
22P_0402_50V8J
12
12
452
452 C
C P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
.8VALWP
451
451 C
C P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
OCP current 3.5A FSW=800kHz
H/S Rds(on) :100mohm , L/S Rds(on) :80mohm ,
0
.95V controller (35.5), Support component (35.6)
R
404
@
404
@
R
P
P
0_0402_5%
0_0402_5%
1 2
2
P
P
405
405
R
R
10K_0402_1%
3 3
E
I Part (47.1)
M
EMI@
EMI@
L
L
402
402
P
P
HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
B+
4 4
12
1
404
404 C
C
2
P
P
@EMI@
@EMI@
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
2200P_0402_50V7K
+3VALW
B
_0.95V
+
12
410 C410
C P
P
A
8
9
3
2
B
P
P
U
U
400
400
I
N
G
D
N
I
LMT
P
G
SY8208DQNC_QFN10_3X3
SY8208DQNC_QFN10_3X3
1
E
N
0.1U_0603_25V7K
0.1U_0603_25V7K
6
B
S
1
0
L
X
4
F
B
7
B
YP
5
L
O
D
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
s
s
sued Date
sued Date
sued Date
s
T
T
T
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONFIDENTIAL
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
C
C
P
P
1
L
X_0.953V
12
405
405
2
+
12
402 C
C402 P
P
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
10K_0402_1%
1
@EMI@
@EMI@
R
R
P
P
4.7_1206_5%
4.7_1206_5%
1
L
401
401
L
P
P
1UH_PCMB063T-1R0M S_12A_20%
1UH_PCMB063T-1R0M S_12A_20%
1 2
VALW
3
411
411 C
C P
P
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2
2
2
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
401
401
2
S
N
B_0.95V
F
B=0.6V
100K_0402_1%
100K_0402_1%
1
@
@
0.01U_0402_16V7K
0.01U_0402_16V7K
2
@EMI@
@EMI@
P
P
C
C
403
403
680P_0603_50V7K
680P_0603_50V7K
2
1
R
R
406
406
P
P
C
C
C
o
o
o
P
P
C
C
12
1
2
mpal Secret Data
mpal Secret Data
mpal Secret Data
1
.
8_0.95VALW _PWREN
454
454
EMI Part (47.1)
12
402
402 R
R
409
409
P
P
C
C P
P
1
66.5K_0402_1%
66.5K_0402_1%
4700P_0402_50V7K
4700P_0402_50V7K
2
R403
R403 P
P
1K_0402_1%
1K_0402_1%
D
D
D
e
e
ciphered Date
ciphered Date
ciphered Date
e
C
0.95V Peak Current 11.1A OCP current 16A FSW=800kHz
H/S Rds(on) :22mohm , L/S Rds(on) :11mohm ,
+0.95VALWP
12
12
408
408
407
407
C
C
C
C P
P
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
401
401 C
C P
P
1
412
412
406
406
C
C
C
C
2
P
P
P
P
@
@
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+
.95VALW P
0
(
11A,440mils ,Via NO.=22)
OCP=
T
T
T
i
tle
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tle
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Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sh eet
Date: Sh eet
Date: Sh eet
P
P
J1
@
1
@
J
2
112
JUMP_43X118
JUMP_43X118
C
C
C
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mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
+
.95VALW
0
+1.8VALWP/+0.95VALWP
L
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37 42Thurs day, May 16, 2013
37 42Thurs day, May 16, 2013
37 42Thurs day, May 16, 2013
1
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Page 38
CyberForum.ru
A
APU_VDD_SEN_H <6>APU_VDD_SEN_L<6>
12
0.01U_0402_50V7K
0.01U_0402_50V7K P
P
503
503
C
505
505
R
R
P
P
P
P
513
513
R
R
10K_0402_1%
10K_0402_1%
1 2
513
513
C
C
P
P
560P_0402_50V7K
560P_0402_50V7K
1 2
1U_0402_6.3V6K
1U_0402_6.3V6K
@
@
@
@
@
@
@
@
1
12
517
517 C
C P
P
526
526 C
C
2
P
P
@
@
1
502
502 H
H P
P
2
100K_0402_1%_TSM0B104F4251RZ
100K_0402_1%_TSM0B104F4251RZ
P
P
R
550
550
R
P
P
555
555
R
R
2
C
+
PU_CORE
A
C
516
516
C
P
P
2
1
P
P
R
521
521
R
1 2
P
P
R
R
522
522
1
R
R
523
523
P
P
1
P
P
R
524
524
R
1 2
12
518
518 PC
PC
1000P_0402_50V7K
1000P_0402_50V7K
@
@
R
R
563
563
P
P
124K_0402_1%
124K_0402_1%
1
567
567
R
R
P
P
124K_0402_1%
124K_0402_1%
1 2
+
1
.8VS
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
2
0_0402_5%
0_0402_5%
2
0_0402_5%
0_0402_5%
1000P_0402_50V7K
1000P_0402_50V7K
A
2
P
82K_0402_1%
82K_0402_1%
1
C
C
511
511
P
P
68P_0402_50V8J
68P_0402_50V8J
1
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M
V
EF
R
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V
DIO
D
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V
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V
T
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F
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T1
S
E
T2
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@
0_0402_5%
0_0402_5%
1 2
U_PROCHOT#<29,6>
+
VS
5
+
5
VS
10_0402_5%
R
R
507
507
P
P
C
C
509
509
12
1 2
R
R
P
P
R561
R561
P
P
R
R
P
P
1
2
@
@
A
P
U_PWRGD<6>
A
P
A
P
A
P
526
526 R
R P
P
22K_0402_1%
22K_0402_1%
P
P
5.23K_0402_1%
5.23K_0402_1%
535
535 R
R P
P
18.7K_0402_1%
18.7K_0402_1%
554
554
2
565
565
2
10_0402_5%
1 2
U_SVC<6>
U_SVD<6>
U_SVT<6>
1000P_0402_50V7K
1000P_0402_50V7K
R
531
531
R
12
S F O
20K_0402_5%
20K_0402_5%
1 2
20K_0402_5%
20K_0402_5%
1
SA F O
T1 E S
T2 E S
10_0402_5%
10_0402_5%
1 2
12
PR
PR
504
504
@
P
P
R
R
R
R
R
R
506
506
12
1 2
12
548
548
553
553
@
0_0402_5%
0_0402_5%
1 2
P
P
330P_0402_50V
330P_0402_50V
525
525 R
R P
P
35.7K_0402_1%
35.7K_0402_1%
534
534 R
R P
P
22.6K_0402_1%
22.6K_0402_1%
V
R
EF
525
525 C
C P
P
0.47U_0402_16V4Z
0.47U_0402_16V4Z
120_0402_1%
120_0402_1%
1 2
53.6K_0402_1%
53.6K_0402_1%
1
470_0402_1%
470_0402_1%
1
A
@
@
0_0402_5%
0_0402_5%
1 1
2 2
R
530
530
R
P
P
1.58K_0402_1%
1.58K_0402_1%
501
501 H
H P
P
100K_0402_1%_TSM0B104F4251RZ
100K_0402_1%_TSM0B104F4251RZ
12
P
P
6.34K_0402_1%
6.34K_0402_1%
1 2
P
P
6.34K_0402_1%
6.34K_0402_1%
1 2
12
3 3
4 4
R
R
515
515
P
P
2
ND G
14
R
15
16
17
18
19
20
21
22
23
24
25
26
P
P
532
532
R
R
115K_0402_1%
115K_0402_1%
B
U controller (36.1),Driver (36.2) Support component (36.3)
CP
2
MP O C
13
MP O C
R
ND
G
I
M
ON
V
64
0
I
ONA
M
V
DIO
D
P
ROK
W
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V
C
S
V
D
S
V
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P_L C O
27
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528
528
C
C
68P_0402_50V8J
68P_0402_50V8J
1
R
R
544
544
P
P
12
B
EN
F
S V
2
11
1
B F
C C V
28
C C V
R536
R536 P
P
2
+
V
V
C
C
C
C
10
9
EN S
EN3P
EN3N
V
S
S
I
I
MPA
IAS
O
B
C
I
29
30
31
MPA
A
IAS
O
B
B
I
C
F
1 2
100K_0402_5%
100K_0402_5%
A
PU_CORE_NB
0.01U_0402_50V7K
0.01U_0402_50V7K
V
EN1N
EN1P S
S
I
I
8
7
EN1P
EN1N
S
S
I
I
ENA
A
S
B F
V
32
33
SENA V
V
C
560P_0402_50V7K
560P_0402_50V7K
10K_0402_1%
10K_0402_1%
C
C
533
533
P
P
C
C
6
ENA2P S
I
C
P
P
1 2
P
P
EN2N S
I
34
C
C
R
R
2
1
V
C
C
5
EN2P S
I
ENA2N S
I
529
529
546
546
0_0402_5%
0_0402_5%
10_0402_5%
10_0402_5%
NSET O T
4
NSET O T
ENA1N S
I
35
ENA1N S
I
12
@
@
P
P
501
501
R
R
P
P
1 2
110K_0402_1%
110K_0402_1%
V
C
C
3
2
M3 W
P
ENA1P
N S
I
E
7 3
36
ENA1P S
I
R
R
557
557
P
P
559
559
R
R
12
1
OT2
ATE2
O
G
G
B
U
P
H
ASE2
L
ATE2
G
P
V
L
ATE1
G
P
H
ASE1
U
G
ATE1
B
O
L
ATEA1
G
P
ASEA1
H
U
ATEA1
G
B
OTA1
O
P
W
MA2
T
NSETA
O
OODA
OOD
G
G P
P
38
39
330P_0402_50V
330P_0402_50V
1
2
A
P
N
D
CC
OT1
0_0402_5% @
0_0402_5% @
1
2
P
P
C
C
@
@
12
C
U_B+
P
P
U
U
500
500
RT8880AGQW_QFN52_6X6
RT8880AGQW_QFN52_6X6
53
52
51
50
P
CC
V
49
L
G
ATE1
48
P
H
ASE1
47
U
ATE1
G
46
B
O
OT1
45
L
ATE_NB1
G
44
P
ASE_NB1
H
43
U
ATE_NB1
G
42
B
OT_NB1
O
41
V
C
C
P
R
537
537
R
P
P
2
P
P 0_0402_5%
0_0402_5%
1
R G ND
542
542
R
R
R
R
558
558
P
1 2
110K_0402_1%
110K_0402_1%
V
G
ATE <29 >
+
3
VS
V
R_ON <29>
40
P
P
1 2
100K_0402_5%
100K_0402_5%
1 2
521
521
C
C
P
P
0.1U_0402_25V6
0.1U_0402_25V6
531
531
R
R
B
OT_NB1
O
P
ASE_NB1
H
L
G
ATE_NB1
P
V
527
527
U
CC
V
C
C
501
501 C
C P
P
G
ATE_NB1
12
2.2U_0603_10V7K
2.2U_0603_10V7K
5
R
569
569
R
P
P
2.2_0603_5%
2.2_0603_5%
R
R
512
512
P
P
2.2_0603_5%
2.2_0603_5%
1
12
502
502 C
C P
P
2.2U_0603_10V7K
2.2U_0603_10V7K
A
P
U_B+
1 2
0.22U_0603_25V7K
0.22U_0603_25V7K
P
P
C
C
1 2
2
B
OT_NB1-1
O
1 2
R
R
520
520
P
P 10_0603_5%
10_0603_5%
4
510
510
4
R
R
@
@
P
P
0_0402_5%
0_0402_5%
1 2
502
502
P
B
H
O
L
GATE1
5
ASE1
OT1
APU_core TDC 15A(A) 13A(B) Peak Current 21A(A) 18A(B) OCP current > 31.5A Load line -4mV/A FSW=400kHz DCR 1.4mohm +/-5% TYP MAX H/S Rds(on) :11.7mohm , 14.5mohm L/S Rds(on) :4.2mohm , 5mohm
A
U_VDDNB_SEN_H<6>
P
B
S
S
S
e
curity Classification
ecurity Classification
curity Classification
e
I
I
I
s
s
sued Date
sued Date
sued Date
s
T
T
T
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
H
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2
2
2
0
0
0
12/09/27
12/09/27
12/09/27
C
C
C
o
mpal Secret Data
ompal Secret Data
mpal Secret Data
o
D
D
D
e
e
e
501
501 Q
Q P
P
123
S TR MDU1516URH 1N POWERDFN56-8
S TR MDU1516URH 1N POWERDFN56-8
502
502 Q
Q P
P
123
MDU1512RH 1N POWERDFN56-8
MDU1512RH 1N POWERDFN56-8
U
G
ATE1
R
R
533
533
P
P
2.2_0603_5%
2.2_0603_5%
1 2
0.22U_0603_25V7K
0.22U_0603_25V7K
ciphered Date
ciphered Date
ciphered Date
D
EMI Part (47.1)
HCB2012KF-121T50_0805
A
U_B+
P
EMI@
EMI@
506
506 C
C P
P
517
517 R
R P
P
514
514 C
C P
P
EMI@
EMI@
1
2
10U_0805_25V6K
10U_0805_25V6K
12
S
1
2
I
SENA1P
I
S
N
4.7_1206_5%
4.7_1206_5%
B_APU_NB
680P_0603_50V7K
680P_0603_50V7K
ENA1N
1
+
+
507
507 C
C P
P
2
P
P
2.8K_0402_1%
2.8K_0402_1%
1
1
1
505
505
534
534
C
C
C
C
P
P
P
P
2
2
10U_0805_25V6K
10U_0805_25V6K
@EMI@
@EMI@
2200P_0402_50V7K
2200P_0402_50V7K
A
PU_CORE_NB
TDC 13A(A) 12A(B)
+
VS
5
Peak Current 17A(A) 15A(B)
HCB2012KF-121T50_0805
@
@
1
+
+
508
508 C
C P
P
2
100U_25V_M
100U_25V_M
P
P
L
L
0.36UH_PDME064T-R36MS_24A_2 0%
0.36UH_PDME064T-R36MS_24A_2 0%
4
33U_D2_25VM_R60M
33U_D2_25VM_R60M
3
R
R
516
516
2
.1U_0402_16V7K
.1U_0402_16V7K
1 2
519
519
R
R
P
P 910_0402_1%
910_0402_1%
1 2
OCP current > 22.5A Load line -4mV/A FSW=400kHz DCR 1.4mohm +/-5% TYP MAX H/S Rds(on) :11.7mohm , 14.5mohm L/S Rds(on) :4.2mohm , 5mohm
5
503
503 Q
Q P
P
P
R
R
570
570
2.2_0603_5%
2.2_0603_5%
2
1
1 2
B
OT1-1
O
523
523
C
C
P
P
4
D
4
5
504
504 Q
Q P
P
@
@
4
3
1
2
MDU1512RH 1N POWERDFN56-8
MDU1512RH 1N POWERDFN56-8
P
123
5
506
506 Q
Q P
P
2
3
1
T
T
T
i
tle
tle
tle
i
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
u
u
stom
stom
stom
u
Date: S heet
Date: S heet
Date: S heet
PL
PL
1 2
502
502
12
512
512
C
C
P
P
R
R
518
@
518
@
P
P 0_0402_5%
0_0402_5%
12
515
515 C
C P
P
@
@
0.1U_0402_25V6
0.1U_0402_25V6
S TR MDU1516URH 1N POWERDFN56-8
S TR MDU1516URH 1N POWERDFN56-8
EMI@
EMI@
12
540
540 R
R
4.7_1206_5%
4.7_1206_5%
P
P
S
NB_APU
12
527
527 C
C P
P
EMI@
EMI@
680P_0603_50V7K
680P_0603_50V7K
MDU1512RH 1N POWERDFN56-8
MDU1512RH 1N POWERDFN56-8
E
EMI@
EMI@
501
501
B
+
1
+
PU_CORE_NB
A
2
ENA1N-1 S
I
EMI Part (47.1)
A
P
U_B+
12
1
519
519
520
520
C
C
C
C P
P
P
P
2
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
R
R
541
541
P
P
2.8K_0402_1%
2.8K_0402_1%
1
I
EN1P
S
P
P 910_0402_1%
910_0402_1%
1
I
EN1N
S
C
C
C
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
+
+
+
C
C
PU_CORE/VDDNBP
PU_CORE/VDDNBP
PU_CORE/VDDNBP
C
L
A9868P
522
522 C
C P
P
@EMI@
@EMI@
L
L
503
503
P
P
0.36UH_PDME064T-R36MS_24A_2 0%
0.36UH_PDME064T-R36MS_24A_2 0%
4
3
2
P
P
C
C
524
524
.1U_0402_16V7K
.1U_0402_16V7K
R
R
547
547
2
1
530
530 C
C
2
P
P
@
@
0.1U_0402_25V6
0.1U_0402_25V6
E
1
2
2200P_0402_50V7K
2200P_0402_50V7K
1
+
APU_CORE
2
12
EN1N-1 S
I
1
1
1
.
.
0
0
0
o
o
o
38 42Thursday, May 16, 2013
38 42Thursday, May 16, 2013
38 42Thursday, May 16, 2013
.
f
f
f
Page 39
CyberForum.ru
5
D D
E
MI Part (47.1)
VGA@
VGA@
P
P
801
801
L
L
HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
2
B
+
VGA@
VGA@
PR
PR
804
804
10_0402_5%
10_0402_5%
2
1
V
S_GPU_SENSE<16>
C C
B B
V
+
V
S
CC_GPU_SENSE<16>
GA_CORE
1 2 VGA@
VGA@
P
P
10_0402_5%
10_0402_5%
806
806
R
R
1000P_0402_50V7K
1000P_0402_50V7K
GPIO6
A A
1
VGA@
VGA@
P
P
809
809
C
C
1000P_0402_50V7K
1000P_0402_50V7K
12
12
VGA@
VGA@
811
811
C
C
P
P
330P_0402_50V7K
330P_0402_50V7K
VGA@
VGA@
R
R
812
812
P
P
2.37K_0402_1%
2.37K_0402_1%
1 2
1 2
2
1
VGA@
VGA@
R
R
816
816
P
VGA@
VGA@
VID5
0
1
1
1
1
1 0 1 0 0
1
1
1
1
1
1
1
1
P
715_0402_1%
715_0402_1%
P
P
818
818
C
C
GPIO30
VID4
1
0
0 0
0
0
0
11 000
1
1
1
1
G
P
U_B+
12
1
802
802
803
803 C
C
C
C
P
P
P
P
2
10U_0805_25V6K
10U_0805_25V6K
VGA@
VGA@
2200P_0402_50V7K
2200P_0402_50V7K
@EMI@
@EMI@
VGA@
VGA@
C
C
812
812
P
P
330P_0402_50V7K
330P_0402_50V7K
1 2
VGA@
VGA@
R
R
813
813
P
P
226K_0402_1%
226K_0402_1%
1 2
VGA@
VGA@
390P_0402_50V7K
390P_0402_50V7K
VGA@
VGA@
56P_0402_50V8
56P_0402_50V8
1
VGA@
VGA@
120K_0402_1%
120K_0402_1%
GPIO29
VID3
1 1
0
0
1
1
0
0
0
1
11 0.775V
VGA@
VGA@
1000P_0402_50V7K
1000P_0402_50V7K
2
1
814
814
C
C
P
P
819
819
C
C
P
P
2
VGA@
VGA@
12
8.06K_0402_1%
8.06K_0402_1%
P
P
R
R
835
835
V
G
A_PWRGD<15,8>
GPIO20
VID2
0
1
10
0
1
10
0
1
1
0
12
804 C804
C P
P
10U_0805_25V6K
10U_0805_25V6K
VGA@
VGA@
C
815
815
C
P
P
12
1
4
47K for GPU
12
R
R
817
817
P
P
GPIO15
VID1
0
1
0
101.075V
0
1
110
0
1
1
0
1
0
10
4
7K for CPU
VGA@
VGA@
1.8K_0402_1%
1.8K_0402_1%
VDDC
1.15V
1.125V1110
1.100V
1.050V
1.025V
1.000V
0.975V
0.950V
0.925V
0.900V
0.875V
0.850V
0.825V
0.800V
P
P
718
718
R
R
Default
+
5
VALW
47K_0402_1%
47K_0402_1%
+
VS
3
12
3
V
A controller (43.1),Driver (43.2) Support component (43.3)
G
12
P
P
802
R802
R
1_0603_5%
1_0603_5%
C
C
806
806
P
P
10
9
8
TN
UM-
R
S I
VGA@
VGA@
_ON
RSLPVR P
R V
D
26
27
28
2
1
@
@
PU_DPRSLPVR G
828
828
1
R
R P
P
12
2
47K_0402_1%
47K_0402_1%
VGA@
VGA@
S_PWREN X P
807
807 C
C P
P
1
A@
A@ G
G V
V
2
0.22U_0603_25V7K
0.22U_0603_25V7K
+
5VALW
12
11
12
13
D
N I
D
VGA@
VGA@
V
V
UM+ S
I
P
P
801
801
U
U
D5
D4
D6
I
I
I
V
V
V
25
23
24
<13>
0.1U_0402_16V7K
0.1U_0402_16V7K
826 0_0402_5%
826 0_0402_5%
827 0_0402_5%
827 0_0402_5%
822
822
R
R
R
R
C
C
P
P
P
P
P
P
1 2
1 2
1 2
@
@
@
@
@
@
VGA@
VGA@
<14,8>
U_VID3
U_VID5
PU_VID4
P
P
G
G
G
P
P 0_0402_1%
0_0402_1%
14
ON M
I
D3 I
V
22
825 0_0402_5%
825 0_0402_5% R
R P
P
1 2
<13>
VGA@
VGA@
VGA@
VGA@
810
810
805
805
C
C
PR
PR
P
P
0.1U_0603_25V7K
0.1U_0603_25V7K
2.2_0603_5%
2.2_0603_5%
12
2
2
P
P
R
R
1_0603_5%
1_0603_5%
VGA@
VGA@
P
P
C
C
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
12
1
830
830 R
R P
P
@
@
2
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
12
12
837
837 PR
PR
VGA@
VGA@
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
<13>
1
4
5
1
814
814
817
817
12
832
832
831
831
R
R
R
R
P
P
P
P
VGA@
VGA@
VGA@
VGA@
10K_0402_1%
10K_0402_1%
12
839
839
838
838 R
R
R
R
P
P
P
P
@
@
@
@
10K_0402_1%
10K_0402_1%
4
+
VALW
5
Rds(on):2.7mΩ~3.3mΩ
+
3
VGS
12
833
833 R
R P
P
@
@
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
12
840
840 R
R P
P
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
VGA@
VGA@
B
T_GPU
S
R
R
841
841
A@
A@
VG
VG
OT O B
15
D
_GPU
H
U
G
ATE
16
L
X
_GPU
P
HASE
17
V
SP
S
18
D
L
_GPU
L
ATE
G
19
V
CP
C
20
V
D0
I
21
V
ID1
D2 I
V
824 0_0402_5%
824 0_0402_5% R
R P
P
@
@
<13>
U_VID2 P G
1
2
VGA@
VGA@
1
823
823 R
R P
P
2
VGA@
VGA@
12
836
836 R
R P
P
@
@
821 0_0402_5%
821 0_0402_5% R
R P
P
1 2
@
@
<13>
<13>
PU_VID1 G
VGA@
VGA@
VGA@
VGA@
1_0603_5%
1_0603_5%
1
P
P
R
809
809
R
801
801
R
R
P
P
2
7
6
5
4
12
3
2
1
12
VGA@
VGA@
1U_0603_6.3V6M
1U_0603_6.3V6M
G
P
U_ISUM+
G
U_ISUM-
P
29
ND G A
V
S
EN
F
B
C
O
MP
V
W
ISL62881CHRTZ-T_TQFN28_4X4
ISL62881CHRTZ-T_TQFN28_4X4
R
B
IAS
P
OOD
G
C
L
K_EN#
0_0402_5%
0_0402_5%
829
829 R
R P
P
2
+VGA_CORE TDC 21A EDC 31.5A OCP current ?? A FSW=??kHz DCR 1.4m ohm +- 5% T YP MAX H/S Rds(on) :11 .7mohm , 14moh m
5
801
801 Q
Q P
P
VGA@
VGA@
123
S TR MDU1516URH 1N POWERDF N56-8
S TR MDU1516URH 1N POWERDF N56-8
5
803
4
123
Layout Note: Place near Choke
803 Q
Q P
P
VGA@
VGA@
802
802 Q
Q P
P
VGA@
VGA@
123
MDU1512RH 1N POWERDFN56-8
MDU1512RH 1N POWERDFN56-8
L/S Rds(on) :2. 7mohm , 3.3mo hm
P
P
802
VGA@
802
VGA@
L
L
0.36UH_PDME064T-R36MS_24A_20%
0.36UH_PDME064T-R36MS_24A_20%
1
1
2
2
1
MDU1512RH 1N POWERDFN56-8
MDU1512RH 1N POWERDFN56-8
@EMI@
@EMI@
R
R
808
808
P
P
4.7_1206_5%
4.7_1206_5%
@EMI@
@EMI@
C
C
816
816
P
P
680P_0603_50V7K
680P_0603_50V7K
G
P
G
P
U_ISUM+
U_ISUM-
12
VGA@
VGA@
3.65K_0805_1%
3.65K_0805_1%
VGA@
VGA@
P
P
R
R
1
2.61K_0402_1%
2.61K_0402_1%
2
P
P
R
R
810
810
815
815
VGA@
VGA@
1 2
2
10KB_0402_5%_ERTJ1VR103J
10KB_0402_5%_ERTJ1VR103J
1 2
VGA@
VGA@
P
P
R
R
818
818
11K_0402_1%
11K_0402_1%
1 2
VGA@
VGA@
P
P
820
820
C
C
0.047U_0402_16V7K
0.047U_0402_16V7K
1 2
VGA@
VGA@
C
821
821
C
P
P
0.1U_0402_16V7K
0.1U_0402_16V7K
1.2K_0402_1%
1.2K_0402_1%
4
3
12
H
7
7
H
P
P
B value:4250K±2%
12
VGA@
VGA@
P
P
R
822
822
R
P
P
811
@
811
@
R
R
0_0402_5%
0_0402_5%
1
+
GA_CORE
V
1
1
+
+
+
+
899
899
900
900
C
C
C
C
P
P
P
P
2
2
390U_2.5V_M
390U_2.5V_M
390U_2.5V_M
390U_2.5V_M
VGA@
VGA@
VGA@
VGA@
0.1U_0402_16V7K
0.1U_0402_16V7K
1
C823
C823 P
P
2
VGA@
VGA@
S
S
S
curity Classification
ecurity Classification
curity Classification
e
e
I
I
I
s
s
sued Date
sued Date
sued Date
s
T
T
T
H
H
IS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFI DENTIAL
IS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFI DENTIAL
IS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFI DENTIAL
H
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
5
4
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
3
2
2
2
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
C
C
C
mpal Secret Data
ompal Secret Data
mpal Secret Data
o
o
D
D
D
e
e
ciphered Date
ciphered Date
ciphered Date
e
C
C
C
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
L
L
L
-9868P
A-9868P
-9868P
A
A
o
+
+
+
V
V
V
PU_COREP
PU_COREP
PU_COREP
1
3
o
3
o
3
o
f
f
9 42Thursday, May 16, 2013
9 4
f
9 4
1
1
1
0
.0
0
.
.
2Thursday, May 16, 2013
2Thursday, May 16, 2013
T
T
T
itle
tle
tle
i
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet
2
Date: Sheet
Page 40
CyberForum.ru
5
PU_Core output CAP (Including MLCC) 36.4
C
+
PU_CORE
A
12
C1000
C1000 P
D D
P
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1004
1004 C
C
2
P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
12
1014
1014 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
1
2
1
2
+
PU_CORE
A
12
1001
1001 C
C P
P
10U_0603_6.3V6M
10U_0603_6.3V6M
1010
1010 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
1015
1015 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
1002 C
C1002 P
P
10U_0603_6.3V6M
10U_0603_6.3V6M
12
1011
1011 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
12
1016
1016 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
12
1012
1012 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
12
1017 C1017
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
4
+APU_CORE_NB
12
1003
1003 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
12
1013
1013 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
12
1018
1018 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
+
APU_CORE_NB
12
12
1036
1036 C
C P
P
180P_0402_50V8J
180P_0402_50V8J
1005
1005 C
C P
P
10U_0603_6.3V6M
10U_0603_6.3V6M
3
2
1
GFX output CAP (Including MLCC) 36.5
+A
1
+
+
1032
1032 C P
PC
2
@
@
PU_CORE_NB
1
12
+
+
1033
1033 C
C P
P
2
1U_0402_6.3V6K
330U_D2_2V_Y
330U_D2_2V_Y
1U_0402_6.3V6K
1
2
1020
1020 C
C P
P
1025
1025 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
12
1021
1021 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
12
1026
1026 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
12
1022
1022 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1027
1027 C
C
2
P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
12
1023
1023 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1028
1028 C
C
2
P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
12
1024
1024 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
@
@
12
1029
1029 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
Local
12
1
1007
1007
1008
1008
C
C
C
C
2
P
P
P
P
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1009
1009 C
C
2
P
P
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
560U_D2_2VM_R4.5M
560U_D2_2VM_R4.5M
C C
12
12
1006
1006
1019
1019
C
C P
P
PC
PC
@
@
B B
A A
0.22U_0402_16V7K
0.22U_0402_16V7K
180P_0402_50V8J
180P_0402_50V8J
+
PU_CORE
A
1
+
+
1100
1100 PC
PC
2
560U_D2_2VM_R4.5M
560U_D2_2VM_R4.5M
Local
1
+
+
1101
1101 C
C P
P
2
330U_D2_2V_Y
330U_D2_2V_Y
1
+
+
1102
1102 C
C P
P
2
@
@
330U_D2_2V_Y
330U_D2_2V_Y
+VGA_CORE
+
V
GA_CORE
1
12
1042
1042
1043
1043 C
C
C
C
2
P
P
P
P
VGA@
VGA@
VGA@
VGA@
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
12
1
1077
1077
1076
1076
C
C
C
C
2
P
P
P
P
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
12
12
1051
1051
1050
1050
C
C
C
C P
P
P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
1
1069
1069 C
C P
P
12
1060
1060 C
C
2
P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
1U_0402_6.3V6K
VGA@
1040
1040 C
C P
P
VGA@
VGA@
10U_0603_6.3V6M
10U_0603_6.3V6M
1078
1078 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
1052
1052 C
C P
P
VGA@
VGA@
1U_0402_6.3V6K
1U_0402_6.3V6K
1068
1068 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
+VDDC
12
1041
1041 C
C P
P
VGA@
VGA@
12
1044
1044 C
C P
P
VGA@
VGA@
12
1053
1053 C PC
P
VGA@
VGA@
1
1061
1061 C
C
2
P
P
VGA@
VGA@
12
10U_0603_6.3V6M
10U_0603_6.3V6M
12
12
1045
1045 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
12
1054
1054 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
1
1062
1062 C
C
2
P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
1
12
1079
1079
1046
1046
C
C
C
C
2
P
P
P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
1
1055
1055 C
C
2
P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
12
1063
1063 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
1U_0402_6.3V6K
VGA@
VGA@
1
12
1056
1056 C
C
2
P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
12
1
1064
1064 C
C
2
P
P
VGA@
VGA@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
kabini
VDD
VDD_NB
VGA_Core output CAP (Including MLCC 43.9)
12
1048
1048
1047
1047
C
C
C
C P
P
P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
VGA@
VGA@
12
1058
1058
1057
1057 C
C
C
C
P
P
P
P
VGA@
VGA@
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
1
1066
1066
1065
1065
C
C
C
C
2
P
P
P
P
VGA@
VGA@
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
12
12
1049
1049 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
12
12
1059
1059 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
12
12
1067
1067 C
C P
P
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VGA@
VGA@
560uF*4.5m
2
1
10uF (0603)
3
4 9
1u (0402)
11
0.22uF
180P (0402)
1
1
S
S
S
curity Classific ation
ecurity Classif ication
curity Classific ation
e
e
2
2
2
0
0
12/09/27
12/09/27
12/09/27
I
I
I
ssu
ed Date
ed Date
ed Date
ssu
ssu
T
T
T
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
0
3
C
C
C
mpal Secret Data
ompal Secret Data
mpal Secret Data
o
o
D
D
D
e
ciphered Da te
ciphered Da te
ciphered Da te
e
e
C
C
C
o
mpal Electronics, Inc.
ompal Electronics, Inc.
mpal Electronics, Inc.
T
T
T
i
i
tle
tle
tle
i
Size D ocument Number Rev
Size D ocument Number Rev
Size D ocument Number Rev
A
A
A
3
3
3
Date: Sheet
Date: Sheet
2
Date: Sheet
o
P
P
P
R
R
OCESSOR DECOUPLING
OCESSOR DECOUPLING
OCESSOR DECOUPLING
R
L
A-9868P
4
0 42Thursday, May 16, 2013
0 42Thursday, May 16, 2013
0 42Thursday, May 16, 2013
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f
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CyberForum.ru
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Version change list (P.I.R. List) Page 1 of 1
for PWR
Reason for change PG# Modify List Date
D D
P
_VNKAE_DIS-UMA1226.xlsx (命令列)
IR
C C
PhaseItem
B B
A A
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
s
sued Date
sued Date
sued Date
s
s
T
T
T
H
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONFIDENTIAL
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
2
2
2
0
0
0
12/09/27 2015/09/27
12/09/27 2015/09/27
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3
C
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
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mpal Electronics, Inc.
ompal Electronics, Inc.
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Date: Sh eet
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Date: Sh eet
mpal Electronics, Inc.
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41 42Thurs day, May 16, 2013
41 42Thurs day, May 16, 2013
41 42Thurs day, May 16, 2013
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Page 42
CyberForum.ru
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PIR (Product Improve Record)
HW
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NKAE LA-9868P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.3 TO 1.0
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Item Page Date Request Solution
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1 2013/03/5a Change APU to PR sample PR sample PN SA00006R300, SKU 4519NL51L03 2 P30 2013/03/5a PCB cut outline Remove SW1 3 P06 2013/03/5a co-lay eDP & LVDS Due to common eDP cable, swap Lane0 and Lane2 to follow common design; replace CC106, CC102 with RC75, RC76; add RC77, RC78, CC109, CC110. 4 P30 2013/03/06a no need power button Remove SW2 5 P30 2013/03/06a Add C24(0.1uF) to ON/OFFBTN# and set to ESD@ 6 P06 2013/03/06a Add CC99(1000pF) to APU_RST# and set to ESD@ 7 2013/03/06a Change CC93, CC94, CC97, CB6 to ESD@ 8 P07 2013/03/06a BIOS ROM Change UC5 to always mount on 43-level 9 P07 2013/03/06a For vendor recommand Change CC22, CC23 from 5.6pF to 4.7pF(SE07147AC80) 10 P28 2013/03/07a co-lay card reader for EMI request Update card reader schematic for co-lay GL834L and RT5117 11 P09 2013/03/07b Remove 0ohm res Change RC116, RC117, RC119, RC120 to short pad symbol 12 P26 2013/03/07b Remove 0ohm res Change RA18, RA24, RA22, RA36, RA37 to short pad symbol 13 P05 2013/03/07b Remove 0ohm res Change R2 to short pad symbol 14 P20 2013/03/07b Remove 0ohm res Remove R106 15 P29 2013/03/07b Remove 0ohm res Change RB36 to short pad symbol 16 2013/03/11a Update power schematic 17 P28 2013/03/12a Remove co-lay RT5117 Update card reader schematic 18 P30 2013/03/18a Change PCB PN Change PCB PN to DAZ0WJ00100 19 P30 2013/03/18a Remove DC-IN JACK PN due to BOM structure changed 20 P24 2013/03/18a Remove 0ohm res Change RR1, RR2 to short pad symbol 21 P08 2013/03/18a For power consumption improve Change VRAM_SEL to TOUCH_SEL for BTO to improve battery life.
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22 P26 2013/03/25a ESD request Change DA1, CA30, CA31, CA34, CA36 to varistor(SCV00001K00) 23 P08 2013/03/25a vendor recommand Change CC31 to 8pF(SE00000DB80) 24 P24 2013/03/25a Remove 0ohm res Change RR1, RR2 to 0 ohm
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HW PIR
HW PIR
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
A-9868P 1.0
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A-9868P 1.0
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A-9868P 1.0
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Date: Sheet
Date: Sheet
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Date: Sheet
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42 42Thursday, May 16, 2013
42 42Thursday, May 16, 2013
42 42Thursday, May 16, 2013
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