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LA-9868P
Schematics
41 pgs1.27 Mb0
Schematics Rev1.0
42 pgs1.79 Mb0

Compal LA-9868P Schematics Rev1.0

CyberForum.ru
A
1 1
B
C
D
E
VNKAE
2 2
Rosetta 10AN/10ANG
LA-9868P SchematicREV 1.0
3 3
AMD KABINI Quad Core 25W only for UMA AMD KABINI Quad Core 15W for DIS&UMA
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2012/09/27 2015/09/27
2012/09/27 2015/09/27
2012/09/27 2015/09/27
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
LA-9868P
LA-9868P
LA-9868P
1 42Thursday, May 16, 2013
1 42Thursday, May 16, 2013
1 42Thursday, May 16, 2013
E
1.0
1.0
1.0
CyberForum.ru
A
A
D GPU
M
A
1 1
MD Sun Pro M2, 64bit with 1GB DDR3(2Gbit)
AMD Sun Pro M2, 64bit with 2GB DDR3(4Gbit)
p
age 12-19
B
PCIe Gen2 X4
5Gbps
A
D FT3 APU
M
C
M
emory BUS(DDRIII)
Single Channel
1
.5V DDRIII 1333/1600 MT/s
APU SMBUS
D
2
0pin DDRIII-SO-DIMM X2
0
B
ANK 0, 1, 2, 3
p
age 10,11
E
L
DS/eDP Conn
V
H
D
MI Conn
p
age 20
DP0 X4
DP1 X4
J
aguar
Core
Integrated Yangtze FCH
USB 2.0
5
V
480Mbps
U
B 2.0 Left
S
U
U
SB Right1
U
S
B2.0 port 8
B port 0
S
p
age 25
p
age 24
U
U
SB Right2
U
S
B2.0 port 9
SB port 4
p
age 20
p
age 24
C
ardreaderTouchScreen
U
B port 2
S
p
age 28
I
nt. Camera
U
S
p
age 20
B port 3
P
IeMini Card
C
For BT
U
SB port 1
p
age 23
(1.4b & 3D)
p
age 21
2 2
C
T Conn
R
p
age 22
P
CIeMini Card For WLAN
P
CIe port 2
p
age 23
R
T
L8106E 10/100M
P
C
Ie port 1
p
S
ROM
PI
(4MB)
age 25
p
age 7
3 3
T
uch Screen Control/B
o
p
age 20
D
C
A
P
Ie Gen1 X1
C
APU SMBUS
2
5bps
.
PCIe Gen1 X1
2
.
5bps
S
P
I BUS
3
.
3V 33HZ
APU SMBus
BGA 769-balls
L
3
E
E KB9012
N
E
C SMBus
p
PC Bus
3V 33 MHz
.
p
age 29
age 5-9
U
S
5
V
5Gbps
S
TA port 0
A
5
6Gbps
V
S
TA port 1
A
5
6Gbps
V
H
D
3
.
3V 24MHz
B 3.0
Audio
U
S
B Right1
U
S
TA HDD
A
S
TA ODD
A
H
D
A Codec
A
L
S
B3.0 port 0
p
age 24
SATA port 0
p
SATA port 1
p
C259
age 23
age 23
p
age 26
U
S
B Right2
U
S
B3.0 port 1
p
age 24
S
PK Conn
p
age 27
J
PI
O
(HP & MIC)
p
age 27
DC/DC Interface CKT.
p
age 31
4 4
P
o
wer Circuit DC/DC
p
age 32~41
P
o
wer On/Off CKT & Power/B
p
age 30
A
U
S
B2.0&LAN/B
p
age 25
R
T
C CKT.
page 9
B
T
ouch Pad
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
T
T
T
H
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ed Date
ssued Date
ed Date
ssu
ssu
I
nt.KBD
page 30page 30
C
G
-Sensor
p
age 25
C
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
2
2
2
0
0
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012/09/27 2015/09/27
12/09/27 2015/09/27
o
D
D
D
ciphered Date
eciphered Date
ciphered Date
e
e
D
C
C
C
o
mpal Electronics, Inc.
mpal Electronics, Inc.
ompal Electronics, Inc.
T
T
T
i
i
tle
tle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
B
B
B
l
l
ock Diagram
lock Diagram
ock Diagram
L
L
L
A
A
-9868P
-9868P
-9868P
A
2
o
2
2
o
o
4
4
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2Thursday, May 16, 2013
2Thursday, May 16, 2013
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.
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2
1
DESIGN CURRENT 0.15A
D
B+
D D
Ipeak=12A, Imax=8.4A, Iocp min=14A
S
SP#
U
N
CHANNEL
-
T
PS22966
O
D
N
-CHANNEL
T
S22966
P
D_PWR
ESIGN CURRENT 0A
D
ESIGN CURRENT 4A
D
ESIGN CURRENT 2A
+3VL +
+5VALW
+5VS
+
5VS_ODD
5VL
RT8243A
I
peak=8A, Imax=5.6A, Iocp min=10A
3
VALW_APU_PWREN
D
P
-
CHANNEL
A
O
-3413
1
.
8_0.95VALW_PWREN
S
C C
S
USP#
N-CHANNEL
T
S22966
P
Y8032
L
CD_ENVDD
P
-CHANNEL A
-3413
O
D
GPU_PWR_EN
P-CHANNEL
AO-3413
ESIGN CURRENT 330mA
D
ESIGN CURRENT 2.5A
S
U
SP#
N
-CHANNEL
TPS22966
V
A_PWRGD
G
N
-CHANNEL
TPS22966
D
ESIGN CURRENT 4A
DESIGN CURRENT 1.5A
D
ESIGN CURRENT 60mA
+
3VALW
+
3VALW_APU
+
3V_LAN
+
1.8VALW
+
1.8VS
+
1.8VGS
+LCD_VDD
+
3VS_DGPU
+3VS
D
S
Y
R
T8207M
S
Y8208D
R
T8880A
SL62881
G
SON
1
8_0.95VALW_PWREN
.
V
R_ON
P
U_DPRSLPVR
Ipeak=12A, Imax=8.4A, Iocp min=13.8A
V
G
A_PWRGD
N
-CHANNEL
T
P
S22966
SUSP#
I
eak=2.5A, Imax=1.75A, Iocp min=16A
p
0
95VS_PWREN#
.
N
-CHANNEL
F
S6676
D
I
p
eak=15A, Imax=10.5A, Iocp min=30A
I
p
eak=13A, Imax=9.1A, Iocp min=30A
I
p
eak=21A, Imax=14.7A, Iocp min=40A
4
B B
A A
I
5
ESIGN CURRENT 2A
D
ESIGN CURRENT 2A
D
ESIGN CURRENT 1.5A
D
ESIGN CURRENT 2A
+
3V_WLAN
+1.5V
+
1.5VGS
+
0.75VS
+
0.95VALW
+0.95VS
A
PU_CORE
APU_CORE_NB
V
GA_CORE
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
s
ssued Date
sued Date
sued Date
s
T
T
T
H
HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL
IS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFI DENTIAL
IS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFI DENTIAL
H
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
3
2
2
2
0
0
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
C
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
o
D
D
D
e
eciphered Date
ciphered Date
ciphered Date
e
2
C
C
C
o
o
mpal Electronics, Inc.
ompal Electronics, Inc.
mpal Electronics, Inc.
T
T
T
i
i
i
tle
tle
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
L
L
L
P
P
P
A
A
-9868P
-9868P
-9868P
A
o
o
wer Tree
wer Tree
wer Tree
o
3
o
3
3
o
o
4
f
2Thursday, May 16, 2013
2Thursday, May 16, 2013
2Thursday, May 16, 2013
f
4
f
1
4
1
1
1
.
.
0
0
0
.
CyberForum.ru
A
B
C
D
E
V
ltage Rails
o
State
S0
S1
S
3
S5 S4/AC
power plane
1 1
2 2
S
5 S4/ Battery only
S5 S4/AC & Battery don't exist
( O MEANS ON X MEANS OFF )
+RTCVCC
O
O
O
O
O
O
B
+
O
O
O
O
O
X
+5VL
+3VL
O
O
O
O
O
X
+5VALW
+3VALW
+1.8VALW
+0.95VALW
+
VSB
O
O
O
O
X
X
+1.5V
O
X
X
X
UMA
+5VS
+3VS
+
0.95VS
+1.8VS
+1.5VS
+
0.75VS
+
APU_CORE
+
APU_CORE_NB
OO
OO
X
X
X
X
B
O Option Table
T
F
unction
description
explain
BTO
S
ATE
T
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
G
3 L
SIGNAL
SLP_S3# SLP_S5#
HIGHHIGH
HIGH HIGH
LOW
HIGH
H
I
LOW
OW LOW
GH
L
O
WLOW
A
P
U SM Bus Address (SCL0/SDA0)
H
E
3 3
+
3VS DDR SO-DIMM A A0H 1010 0000 b +3VS DDR SO-DIMM B A2H 1010 0010 b +3VS WLAN
E
SM Bus1 Address
C
D
vice Address
e
HEX
HEX Address
+3VL Smart Battery 16H 0001 0110 b +3VL Charger 12H 0001 0010 b
4 4
A
X AddressDevicePower
E
SM Bus2 Address
C
D
vicePowerPower
e
HEX Address
+3VS G-Sensor 40H 0100 0000 b +3VS VGA thermal 82H 1000 0010 b +3VS APU thermal 98H 1001 1000 b
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
ed Date
ssued Date
ed Date
ssu
ssu
T
T
T
H
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
2
2
0
0
12/09/27 2015/09/27
012/09/27 2015/09/27
12/09/27 2015/09/27
C
C
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
o
D
D
D
A
G
G-B
G-C
G-D
G-E
ciphered Date
eciphered Date
ciphered Date
e
e
P
U POWER SEQUENCE
-A
+RTC
3
ALW_APU_PWREN
V
+
3
VALW_APU
1.8_0.95VALW_PWREN
+1.8VALW
+0.95VALW
SYSON
+1.5V
SUSP#
+3VS
+1.8VS
+
1.5VS
+0.95VS
VR_ON
+APU_CORE
+APU_CORE_NB
D
C
C
C
o
mpal Electronics, Inc.
mpal Electronics, Inc.
ompal Electronics, Inc.
T
T
T
i
i
tle
tle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
u
u
stom
stom
stom
u
Date: Sheet
Date: Sheet
Date: Sheet
o
L
L
L
A
A
A
N
N
N
-9868P
-9868P
-9868P
o
o
tes List
otes List
tes List
E
o
o
o
f
4 42Thursday, May 16, 2013
4 42Thursday, May 16, 2013
4 42Thursday, May 16, 2013
f
f
1
1
1
.
.
0
0
0
.
CyberForum.ru
5
D
R_AB_DQS[0..7]<10,11>
D
R_AB_DQS#[0..7]<10,11>
D
D
D
R_AB_MA[0..15]<10,11>
D
D D
D
R_AB_BS0<10,11>
D
D
R_AB_BS1<10,11>
D
D
R_AB_BS2<10,11>
D
R_AB_DM[0..7]<10,11>
D
D
C C
D
R_A_CLK0<10>
D
R_A_CLK0#<10>
D
D
R_A_CLK1<10>
D
D
D
R_A_CLK1#<10>
D
R_B_CLK0<11>
D
D
R_B_CLK0#<11>
D
D
D
R_B_CLK1<11>
D
R_B_CLK1#<11>
D
D
M_MAB_RST#<10,11>
E
M
M_MAB_EVENT#<10,11>
E
M
D
R_A_CKE0<10>
D
D
R_A_CKE1<10>
D
R_B_CKE0<11>
D
D
R_B_CKE1<11>
D
B B
1 2
94
94
C
C
C
C
C
C
R
R
1K_0402_1%
1K_0402_1%
A A
C
C
R
R
1K_0402_1%
1K_0402_1%
D
R_A_ODT0<10>
D
D
R_A_ODT1<10>
D
D
D
R_B_ODT0<11>
D
D
R_B_ODT1<11>
D
D
R_A_SCS0#<10>
D
D
R_A_SCS1#<10>
D
R_B_SCS0#<11>
D
D
R_B_SCS1#<11>
D
D
D
R_AB_RAS#<10,11>
D
R_AB_CAS#<10,11>
D
D
R_AB_WE#<10,11>
D
D
ESD@
ESD@
E
M_MAB_RST#
M
180P_0402_50V8J
180P_0402_50V8J
c
ose to APU
l
1
.5V
+
M
EMORY Reference Voltage (Cap follower checklist 1.02)
6
6
1 2
8
8
2
C
C
17
17
C
C 1U_0402_6.3V6K
1U_0402_6.3V6K
1
1 2
C
l
ose to APU AD40
5
D
D
R_AB_MA0
D
D
R_AB_MA1
D
D
R_AB_MA2
D
R_AB_MA3
D
D
R_AB_MA4
D
D
D
R_AB_MA5
D
D
R_AB_MA6
D
D
R_AB_MA7
D
R_AB_MA8
D
D
R_AB_MA9
D
D
R_AB_MA10
D
D
DR_AB_MA11
D
R_AB_MA12
D
D
R_AB_MA13
D
D
R_AB_MA14
D
D
DR_AB_MA15
R_AB_BS0
D
D
R_AB_BS1
D
D
D
R_AB_BS2
D
D
D
R_AB_DM0
D
D
R_AB_DM1
D
D
R_AB_DM2
D
D
R_AB_DM3
D
R_AB_DM4
D
D
R_AB_DM5
D
D
DR_AB_DM6
D
R_AB_DM7
D
D
D
R_AB_DQS0
D
DR_AB_DQS#0
D
DR_AB_DQS1
D
D
R_AB_DQS#1
D
D
R_AB_DQS2
D
R_AB_DQS#2
D
D
R_AB_DQS3
D
D
R_AB_DQS#3
D
D
R_AB_DQS4
D
D
R_AB_DQS#4
D
D
DR_AB_DQS5
D
D
R_AB_DQS#5
D
R_AB_DQS6
D
D
R_AB_DQS#6
D
D
D
R_AB_DQS7
D
R_AB_DQS#7
D
D
R_A_CLK0
D
D
R_A_CLK0#
D
D
R_A_CLK1
D
D
R_A_CLK1#
D
R_B_CLK0
D
D
D
R_B_CLK0#
D
D
R_B_CLK1
D
R_B_CLK1#
D
D
M
M_MAB_RST#
E
M
M_MAB_EVENT#
E
D
DR_A_CKE0
D
R_A_CKE1
D
R_B_CKE0
D
D
D
R_B_CKE1
D
D
D
R_A_ODT0
D
D
R_A_ODT1
R_B_ODT0
D
D
R_B_ODT1
D
D
D
DR_A_SCS0#
D
D
R_A_SCS1#
D
D
R_B_SCS0#
D
R_B_SCS1#
D
D
D
R_AB_RAS#
D
R_AB_CAS#
D
D
D
R_AB_WE#
M
EM_VREF
+
r
emove from CRB_ver0C
Check List 1.02
15mil
M
EM_VREF
+
2
C
C
18
18
C
C
0.1U_0402_16V7K
0.1U_0402_16V7K
1
U
U
1A
1A
C
C
A
G
38
M
_
ADD0
W
3
5
M
_
ADD1
W
3
8
M
_
ADD2
W
3
4
M
_
ADD3
U
8
3
M
ADD4
_
U
7
3
M
ADD5
_
U
4
3
M
ADD6
_
R
5
3
M
_ADD7
R
3
8
M
_
ADD8
N
3
8
M
_
ADD9
A
G
34
M
_
ADD10
R
4
3
M
ADD11
_
N
3
7
M
_
ADD12
A
N
34
M
_
ADD13
L
3
8
M
_
ADD14
L
3
5
M
_
ADD15
A
38
J
M
BANK0
_
A
35
G
M
BANK1
_
N
4
3
M
BANK2
_
B
3
2
M
_
DM0
B
3
8
M
_
DM1
G
4
0
M
_
DM2
N
4
1
M
_
DM3
A
G
40
M
_
DM4
A
41
N
M
DM5
_
A
40
Y
M
DM6
_
A
34
Y
M
DM7
_
Y
0
4
M
DM8
_
B
3
3
M
DQS_H0
_
A
3
3
M
_
DQS_L0
B
4
0
M
_
DQS_H1
A
4
0
M
_
DQS_L1
H
4
1
M
_
DQS_H2
H
4
0
M
_
DQS_L2
P
4
1
M
_
DQS_H3
P
4
0
M
_
DQS_L3
A
H
41
M
_
DQS_H4
A
H
40
M
_
DQS_L4
A
P
41
M
_
DQS_H5
A
P
40
M
_
DQS_L5
B
A
40
M
_
DQS_H6
A
Y
41
M
_
DQS_L6
A
33
Y
M
DQS_H7
_
B
A
34
M
_
DQS_L7
A
A
40
M
DQS_H8
_
Y
1
4
M
DQS_L8
_
A
C
35
M
_
CLK_H0
A
34
C
M
CLK_L0
_
A
34
A
M
CLK_H1
_
A
A
32
M
_
CLK_L1
A
38
E
M
CLK_H2
_
A
37
E
M
CLK_L2
_
A
A
37
M
_
CLK_H3
A
A
38
M
CLK_L3
_
G
3
8
M
_
RESET_L
A
E
34
M
_
EVENT_L
L
4
3
M
_CKE0
0
J
8
3
M
_CKE1
0
J
3
7
M
1
_CKE0
J
3
4
M
1
_CKE1
A
N
38
M
0
_ODT0
A
U
38
M
0
_ODT1
A
N
37
M
1
_ODT0
A
R
37
M
1
_ODT1
A
J
34
M
0
_CS_L0
A
R
38
M
0
_CS_L1
A
L
38
M
1
_CS_L0
A
35
N
M
_CS_L1
1
A
J37
M
_
RAS_L
A
34
L
M
CAS_L
_
A
35
L
M
WE_L
_
A
40
D
M
VREF
_
A
C
38
M
_
VREFDQ
FT3_BGA769 @
FT3_BGA769 @
M
M
MORY
MORY
E
E
EMORY M
F
F
3 REV 0.51
3 REV 0.51
T
T
M
M
M
M
M
M
M
M
M
ZVDDIO_MEM_S
_
4
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
_
_
_
_
_
_
_
_
4
DATA0
_
_
DATA1
_
DATA2
_
DATA3
DATA4
_
DATA5
_
_
DATA6
_
DATA7
DATA8
_
_
DATA9
_
DATA10
DATA11
_
_
DATA12
DATA13
_
DATA14
_
_
DATA15
DATA16
_
DATA17
_
_
DATA18
_
DATA19
DATA20
_
_
DATA21
_
DATA22
DATA23
_
_
DATA24
_
DATA25
DATA26
_
DATA27
_
DATA28
_
_
DATA29
_
DATA30
_
DATA31
DATA32
_
DATA33
_
_
DATA34
_
DATA35
_
DATA36
_
DATA37
DATA38
_
DATA39
_
_
DATA40
_
DATA41
_
DATA42
DATA43
_
DATA44
_
DATA45
_
DATA46
_
_
DATA47
_
DATA48
DATA49
_
DATA50
_
DATA51
_
DATA52
_
DATA53
_
DATA54
_
_
DATA55
_
DATA56
_
DATA57
DATA58
_
DATA59
_
DATA60
_
DATA61
_
_
DATA62
DATA63
_
CHECK0
CHECK1
CHECK2
CHECK3
CHECK4
CHECK5
CHECK6
CHECK7
B A B A B A A B
B A D D B A B C
F F K K E E J J
M N T
U L M R T
A A A A A A A A
A A A A A A A A
A A B A A A A A
B A B A B A B A
V W A A U V A A
A
0
3
2
3 3
5
3
6 9
2
0
3 3
4
3
4
7
3 3
8
4
0 1
4 3
6 7
3
1
4 4
0
0
4
1
4
4
0
4
1 0
4
1
4
4
0
4
1
4
4
0 1
4
0
4
0
4
4
4
0
4
0
40
F
41
F K K E E
40
J
41
J
M N T
41
U
40
L M R T
40
V W A Y
37 U V
39
Y Y
38
A Y
35 A
31
Y A
36
Y A
32
Y
4
1
4 B C 4
1 4
0 A B
D
D D D D D D D D
D D D D D D D D
D D D D D D D D
1
D D D D D
0
D D D
D D
40
D
41
D
40
D
41
D D D
41
D
40
D D
40
D D
40
D
40
D D
41
D
40
D
38
D D
41
D
40
D D D
36
D D
32
D D
37
D D
33
D D
0 40 40
41 41
41
DR_AB_D0 DR_AB_D1 D
R_AB_D2
D
R_AB_D3
D
R_AB_D4
D
R_AB_D5
D
R_AB_D6 R_AB_D7
D
R_AB_D8
D
R_AB_D9
D
R_AB_D10
D
R_AB_D11
D
R_AB_D12
D
R_AB_D13
D
R_AB_D14
D
R_AB_D15
D
D
R_AB_D16
D
R_AB_D17
D
R_AB_D18 R_AB_D19
D
R_AB_D20
D
R_AB_D21
D
R_AB_D22
D D
R_AB_D23
D
R_AB_D24
D
R_AB_D25 R_AB_D26
D
R_AB_D27
D
R_AB_D28
D D
R_AB_D29
D
R_AB_D30
D
R_AB_D31
R_AB_D32
D
R_AB_D33
D DR_AB_D34 D
R_AB_D35 R_AB_D36
D
R_AB_D37
D DR_AB_D38 D
R_AB_D39
D
R_AB_D40 R_AB_D41
D
R_AB_D42
D DR_AB_D43 D
R_AB_D44 R_AB_D45
D
R_AB_D46
D DR_AB_D47
D
R_AB_D48
D
R_AB_D49 R_AB_D50
D DR_AB_D51 D
R_AB_D52 R_AB_D53
D
R_AB_D54
D
R_AB_D55
D
R_AB_D56
D
R_AB_D57
D D
R_AB_D58
D
R_AB_D59
D
R_AB_D60 R_AB_D61
D D
R_AB_D62
D
R_AB_D63
M
ZVDDIO
_
R_AB_D[0..63] <10,11>
D
D
LAN
WLAN
+
P P
P P
V
GA
P P
P P
1 2
1
+
439.2_0402_1%
439.2_0402_1%
C
C
R
R
EVENT# pull high
.5V
1
+
1 2
C
7 1K_0402_5%
7 1K_0402_5%
C
R
R
S
S
S
T
T
T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
IE_LANTX_ARX_P1<25>
P
C
IE_LANTX_ARX_N1<25>
P
IE_WLANTX_ARX_P2<23>
C
P
IE_WLANTX_ARX_N2<23>
C
P
0
.95VS_APU_GFX
C
IE_GTX_C_ARX_P0<12>
C
IE_GTX_C_ARX_N0<12>
IE_GTX_C_ARX_P1<12>
C
IE_GTX_C_ARX_N1<12>
C
C
IE_GTX_C_ARX_P2<12>
C
IE_GTX_C_ARX_N2<12>
IE_GTX_C_ARX_P3<12>
C C
IE_GTX_C_ARX_N3<12>
3
1 2
1 1.69K_0402_1%
1 1.69K_0402_1%
RC
RC
P
_
TX_ZVDD
1
0
R
8
R
5
R
4
R
5
N
4
N
0
1
N
8
N
8
W
5
L
4
L
5
J
4
J
5
G
4
G
7
D
7
E
1B
1B
C
C
U
U
_
GPP_RXP0
P
_
GPP_RXN0
P
GPP_RXP1
_
P
GPP_RXN1
_
P
_
GPP_RXP2
P
_
GPP_RXN2
P
GPP_RXP3
_
P
GPP_RXN3
_
P
_
TX_ZVDD_095
P
GFX_RXP0
_
P
_
GFX_RXN0
P
_
GFX_RXP1
P
GFX_RXN1
_
P
GFX_RXP2
_
P
_
GFX_RXN2
P
GFX_RXP3
_
P
GFX_RXN3
_
P
FT3_BGA769
FT3_BGA769
+
3 REV 0.51
3 REV 0.51
T
T
F
F
5
VS
PCIE
PCIE
1
A
2 0
2 0
R
R
GPP
RAPHICS G
1
@
@
GPP_TXP0
_
P
GPP_TXN0
_
P
_
GPP_TXP1
P
_
GPP_TXN1
P
GPP_TXP2
_
P
GPP_TXN2
_
P
GPP_TXP3
_
P
_
GPP_TXN3
P
_
RX_ZVDD_095
P
GFX_TXP0
_
P
_
GFX_TXN0
P
_
GFX_TXP1
P
_
GFX_TXN1
P
GFX_TXP2
_
P
GFX_TXN2
_
P
_
GFX_TXP3
P
GFX_TXN3
_
P
2
_0603_5%
_0603_5%
2
@
@
AN1
F
+
2
L
1
L
2
K
IE_ATX_LANRX_P1
C
P
1
K
IE_ATX_LANRX_N1
C
P
2
J
C
IE_ATX_WLANRX_P2
P
1
J
C
IE_ATX_WLANRX_N2
P
2
H
1
H
7
W
P
2
G
P
IE_ATX_GRX_P0
C
1
G
P
IE_ATX_GRX_N0
C
2
F
P
IE_ATX_GRX_P1
C
1
F
P
C
IE_ATX_GRX_N1
2
E
P
C
IE_ATX_GRX_P2
1
E
P
C
IE_ATX_GRX_N2
2
D
P
C
IE_ATX_GRX_P3
1
D
P
C
IE_ATX_GRX_N3
_
RX_ZVDD
R
R
C
C
CC
CC
C
C C
C
C
C
C
C
C
C
C
C
F
A
N Control Circuit
3
+
.5V
A
N_SPEED1<29>
F
E
M_MAB_EVENT#
M
e
e
curity Classification
curity Classification
curity Classification
e
ssu
ed Date
ed Date
ed Date
ssu
ssu
I
I
I
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
H
3
0
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
2
2
2
o
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
C
C
C
ciphered Date
ciphered Date
ciphered Date
e
e
e
D
D
D
2
1
1 2
C
CC
3 0.1U_0402_16V7K
3 0.1U_0402_16V7K
C
2
1
C
C
4 0.1U_0402_16V7K
4 0.1U_0402_16V7K
C
C
1 2
CC
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
CC
1 2
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
C
C
C
C
12
C
2 1K_0402_1%
2 1K_0402_1%
C
1 2
5
5
C
C
C
C C
C
C
C
C
C
C
C
C
C
6
6
7
7 8
8
9
9
10
10
11
11
12
12
1
1 1 2
1
1 2
1 2
1 2
2
2
2
VGA@
VGA@
VGA@
VGA@
0.1U_0402_16V7KVGA@
0.1U_0402_16V7KVGA@
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7KVGA@
0.1U_0402_16V7KVGA@
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7KVGA@
0.1U_0402_16V7KVGA@
0.1U_0402_16V7KVGA@
0.1U_0402_16V7KVGA@
0.1U_0402_16V7KVGA@
0.1U_0402_16V7KVGA@
0.1U_0402_16V7KVGA@
0.1U_0402_16V7KVGA@
C
IE_ATX_C_LANRX_P1 <25>
P
IE_ATX_C_LANRX_N1 <25>
C
P
IE_ATX_C_WLANRX_P2 <23>
C
P
IE_ATX_C_WLANRX_N2 <23>
C
P
0
.95VS_APU_GFX
+
IE_ATX_C_GRX_P0 <12>
C
P
IE_ATX_C_GRX_N0 <12>
C
P
C
IE_ATX_C_GRX_P1 <12>
P
C
IE_ATX_C_GRX_N1 <12>
P
C
IE_ATX_C_GRX_P2 <12>
P
C
IE_ATX_C_GRX_N2 <12>
P
IE_ATX_C_GRX_P3 <12>
C
P
C
IE_ATX_C_GRX_N3 <12>
P
VS
12
R
R
1
1
1
1
0K_0402_5%
0K_0402_5%
NPWM<29>
A
F
AN1
F
1
1
1
C
C 0
.01U_0402_25V7K
.01U_0402_25V7K
0
@
@
2
i
i
tle
tle
tle
i
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
+
1
D
D
1
1
AS16_SOT23-3
AS16_SOT23-3
B
B
T3 DISP/MISC/HDT
T
T
F
F
F
h
ursday, May 16, 2013
ursday, May 16, 2013
ursday, May 16, 2013
h
h
T
T
T
2
3 DISP/MISC/HDT
3 DISP/MISC/HDT
A
-9868P
-9868P
-9868P
A
A
L
L
L
1
2
1
0U_0603_6.3V6M
0U_0603_6.3V6M
1
1
F
F
J
J
6
G
5
G
4
4
3
3
2
2
1
1
ACES_50273-0040N-001
ACES_50273-0040N-001
3
3
C
C
5
5
5
AN
AN
N N
L
N
A
WLAN
V
GA
@
@
D D
.
0
0
0
.
.
1
1
1
4
f
2
2
2
f
4
f
4
o
o
o
CyberForum.ru
5
E
_LCD_TXOUT0+_R
DP
E
DP
_LCD_TXOUT0-_R
A
P
U_HDMI_TX2+<21>
A
U_HDMI_TX2-<21>
D D
H
D
MI
E
DP use 2 Lane for FHD
E
P Cap co-lay
D
A
P
U_TDI
A
U_TCK
P
A
PU_TMS
A
P
U_TRST#
A
P
U_DBREQ#
A
U_RST#
P
A
U_PWRGD
P
EDP/LVDS
A
U_PROCHOT#
P
A
PU_RST#
A
U_PWRGD
P
C1
C1
C1
07
07
C
C
0.1U_0402_16V7K
0.1U_0402_16V7K
S
VT,SVC,SVD, APU_PWRGD is 1.8V Output
PROCHOT is 3.3V Input
VS
3
+
C C
.8VS
1
+
1
.8VS
+
B B
C1
08
08
C
C
EDP@
EDP@
R
R
C2
C2
6 1K_0402_5%
6 1K_0402_5%
C3
C3
2 300_0402_5%
2 300_0402_5%
R
R
4 300_0402_5%
4 300_0402_5%
C3
C3
R
R
1 2 7 3 6 4
C2
C2
R
R
0.1U_0402_16V7K
0.1U_0402_16V7K
1 2
1 2
R
R
P
P
C2
C2
8
5
1K_8P4R_5%
1K_8P4R_5%
8
8
1 2
C
C
C9
9 1000P_0402_50V7K
9 1000P_0402_50V7K
C9
1 2
C9
3
3
C9
C
C
180P_0402_50V8J
180P_0402_50V8J
EDP@
EDP@
12
12
1K_0402_5%
1K_0402_5%
ESD@
ESD@
ESD@
ESD@
P
A
PU_HDMI_TX1+<21>
A
P
U_HDMI_TX1-<21>
A
P
U_HDMI_TX0+<21>
A
P
U_HDMI_TX0-<21>
A
U_HDMI_CLK+<21>
P
A
P
U_HDMI_CLK-<21>
E
_LCD_TXOUT2+_R<20>
DP
E
_LCD_TXOUT2-_R<20>
DP
E
_LCD_TXOUT1+_R<20>
DP
E
_LCD_TXOUT1-_R<20>
DP
E
DP
_LCD_TXOUT0+_R<20>
E
DP
_LCD_TXOUT0-_R<20>
L
CD_TXCLK+<20>
L
CD_
TXCLK-<20>
A
P
U_SVT<38>
A
U_SVC<38>
P
A
U_SVD<38>
P
E
C_
SMB_CK2<13,25,29>
SMB_DA2<13,25,29>
C_
E
U_PWRGD<38>
P
A
U_PROCHOT#<29,38>
P
A
P
U_VDDNB_SEN_H<38>
A
P
U_VDD_SEN_H<38>
A
U_VDD_SEN_L<38>
P
A
close to APU
C1
C1
D
D
12
A
PU_PROCHOT#
@
ESD@
ESD@
@
SCV00001K00
SCV00001K00
close to APU
4
0.1U_0402_16V7K
0.1U_0402_16V7K
1 2
09
EDP@
09
EDP@
CC1
CC1
0.1U_0402_16V7K
0.1U_0402_16V7K
1 2
C1
C1
10
EDP@
10
EDP@
C
C
LVDS@
LVDS@
1
1 2
1
1 2
LVDS@
LVDS@
1 2 1 2
2
2
C7
5 0_0402_5%
5 0_0402_5%
C7
R
R
C7
6 0_0402_5%LVDS@
6 0_0402_5%LVDS@
C7
R
R
C1
C1
07 0_0402_5%LVDS@
07 0_0402_5%LVDS@
C
C
C1
08 0_0402_5%LVDS@
08 0_0402_5%LVDS@
C1
C
C
7 0_0402_5%
7 0_0402_5%
C7
C7
R
R
8 0_0402_5%LVDS@
8 0_0402_5%LVDS@
RC7
RC7
2
2
8
8
T
T
2
2
3
3
T
T T37T3
7
T15T15
T
T
T
T
1
8
8
1
1
9
9
1
E
DP
E
DP
E
DP
E
DP
E E
A
U_PROCHOT#
P
E
_LCD_TXOUT2+
DP
E
DP
_LCD_TXOUT2-
_LCD_TXOUT2+ _LCD_TXOUT2-
_LCD_TXOUT1+ _LCD_TXOUT1-
DP_LCD_TXOUT0+ DP
_LCD_TXOUT0-
L
TXCLK+
CD_
L
TXCLK-
CD_
A
U_RST#
P
A
U_PWRGD
P
A
P
U_ALERT#
A
U_TDI
P
A
P
U_TDO
A
P
U_TCK
A
U_TMS
P
A
U_TRST#
P
A
PU_DBRDY
A
P
U_DBREQ#
V
DDM
EM_SENSE
V
95_FB_H
DD0
V
95_FB_L
DD0
U
U
C
C
C1
C1
DISPLAY/SVI2/JTAG/TEST
T
P1_TXP0
D
T
P1_TXN0
D
T
P1_TXP1
D
T
P1_TXN1
D
T
P1_TXP2
D
T
P1_TXN2
D
T
P1_TXP3
D
T
P1_TXN3
D
L
DP0_TXP0
T
L
DP0_TXN0
T
L
DP0_TXP1
T
L
DP0_TXN1
T
L
T
DP0_TXP2
L
DP0_TXN2
T
L
T
DP0_TXP3
L
DP0_TXN3
T
D
I
SP_CLKIN_H
D
I
SP_CLKIN_L
S
V
T
S
V
C
S
V
D
S
I
C
S
I
D
A
P
U_RST_L
L
T_RST_L
D
A
P
U_PWROK
L
D
T_PWROK
P
OCHOT_L
R
A
ERT_L
L
T
I
D
T
O
D
T
K
C
T
S
M
T
R
ST_L
D
RDY
B
D
REQ_L
B
V
D
DCR_NB_SENSE
V
D
DCR_CPU_SENSE
V
D
DIO_MEM_S_SENSE
V
S
S_SENSE
V
D
D_095_FB_H
V
D
D_095_FB_L
DISPLAY/SVI2/JTAG/TEST
ISPLAY D
MISC
TEST
A
9
B
9
A
0
1
B
0
1
A
1
1
B
1
1
A
2
1
B
2
1
A
4
B
4
A
5
B
5
A
6
B
6
A
7
B
7
K
1
5
H
1
5
G
3
1
D
2
7
E
2
9
B
2
2
B
2
1
B
2
0
A
0
2
B
1
9
A
1
9
A
2
2
B
8
1
D
2
9
D
1
3
D
5
3
D
3
3
G
7
2
B
5
2
A
5
2
D
2
3
G
2
3
E
2
5
E
2
3
A
V
33
A
U
33
MISC
F
F
3 REV 0.51
3 REV 0.51
T
FT3_BGA769 @
FT3_BGA769 @
T
3
D
_150_ZVSS
P
D
P
D
D
P
T
D
T
D
T
L
DP0_AUXP
T
L
DP0_AUXN
T
L
T
D
A
D
D
A
D
A
D
T
T
D
ECRACKMON
I
P
P
B
PASSCLK_H
Y
B
PASSCLK_L
Y
P
L
P
G
O_TSTDTM0_SERIALCLK
I
G
O_TSTDTM0_CLKINIT
I
U
S
B_ATEST0
U
B_ATEST1
S
M
ANALOGIN
_
M
_
ANALOGOUT
T
H
MI_EN/DP_STEREOSYNC
D
2
L
ENBKL : APU to EC to LCD
CD_
B
6
1
D
P
A
1
2
_2K_ZVSS
D
_VARY_BL
D
C_GREEN
D
L
M
DP
B
7
1
LCD_
_BLON
P
A
7
1
L
P
P1_AUXP
P1_AUXN
D
DP0_HPD
A
C_HSYNC
C_VSYNC
D
A
H
H
L
L
LCHRZ_H
LCHRZ_L
M
CD_
_DIGON
A
1
8
L
CD_
D
1
7
A
P
E
1
7
A
P
H
1
9
P1_HPD
D
5
1
E
DP
E
5
1
E
DP
H
7
1
E
DP
B
1
4
A
A
C_BLUE
A
A
C_ZVSS
LTEST1
LTEST0
F
ON_CAL
P
C_RED
A
1
4
A
P
B
1
5
A
P
G
9
1
A
P
E
1
9
D
1
9
A
P
C_SCL
D
2
1
A
P
C_SDA
A
1
6
D
A
H
2
7
ERMDA
H
9
2
ERMDC
D
5
2
A
7
2
B
0
P
B
7
2
B
1
P
A
6
2
B
2
P
B
6
2
B
3
P
B
8
2
A
8
2
B
4
2
A
4
2
A
35
V
A
35
U
E
3
3
TEST
_
A
9
2
EE_2
R
H
1
2
H
5
2
A
J
10
A
8
J
R
2
3
N
3
2
A
29
P
E
1
2
D
P
D
P_STEREOSYNC
Used to align shutter glasses with the interleaved video fram e
RC1
RC1
_150_ZVSS _2K_ZVSS
R
R
ENBKL ENVDD INT_PWM
U_HDMI_CLK U_HDMI_DATA
_LVDS_CLK_R _LVDS_DATA_R
_LVDS_HPD
U_CRT_R
U_CRT_G
U_CRT_B
U_CRT_HSYNC
U_CRT_CLK U_CRT_DATA
1 499_0402_1%
1 499_0402_1%
RC2
RC2
C_ZVSS
T
ST4
E
T
ST5
E
T
EST14
T
E
ST15
T
E
ST16
T
ST17
E
T
E
ST18
T
E
ST19
T
ST25_H
E
T
ST25_L
E
T
EST28_H
T
E
ST28_L
T
ST31
E
T
E
ST36
T
ST37
E
T
ST42
E
T
E
ST43
T
E
ST39
T
E
ST40
T
ST41
E
_STEREOSYNC
C9 2
C9 2
1
2
1
3 150_0402_1%
3 150_0402_1%
2
1
01 0_0402_5%LVDS@
01 0_0402_5%LVDS@
C1
C1
C
C
03 0_0402_5%LVDS@
03 0_0402_5%LVDS@
C1
C1
C
C
1 2
1
K_0402_1%
K_0402_1%
2
2
T
T
1
1
2
2
T
T
3
T3T
4
4
T
T
5
T5T
6
T6T T
T3
4
4
3
T
T
3
3
5
5
r
oute TEST25_H/L AND TEST28_H/L differentially
7
7
T
T
8
8
T
T
9
T9T
NOTE: DP_STEREOSYNC & APU_HSYN C PU FOR INTERNAL(HDMI enable), DP_STER EOSYNC & APU_HSYNC PD FOR CUSTOMER(HDMI disable)
T
T
1
1
2
2
1
1
3
3
T
T
1
1
4
4
T
T
6
6
1
1
T
T
1
1
7
7
T
T
LVDS_CLK&LVDS_DATA layout follow EDP AUX route 85 ohm
L
CD_
ENBKL <20,29>
L
ENVDD <20>
CD_
L
INT_PWM <20>
CD_
A
P
U_HDMI_CLK <21>
A
U_HDMI_DATA <21>
P
DM
I_HPD <21,8>
H
_LVDS_CLK <20>
DP
E
_LVDS_DATA <20>
DP
E
DP
_LVDS_HPD <20>
E
A
P
U_CRT_R <22>
A
U_CRT_G <22>
P
A
P
U_CRT_B <22>
A
P
U_CRT_HSYNC <22>
A
U_CRT_VSYNC <22>
P
P
U_CRT_CLK <22>
A
A
PU_CRT_DATA <22>
EDP/LVDS
HDMI
EDP/LVDS
C
R
T
1
EDP
_LVDS_CLK_R
E
DP
_LVDS_DATA_R
HDMI DDC PU RES move to HDMI page
A
U_CRT_DATA
P
A
U_CRT_CLK
P
A
P
U_CRT_HSYNC
E
_LVDS_HPD
DP
E
DP Cap co-lay
C1
C1
01
01
C
C
EDP@
EDP@
0.1U_0402_16V7K
0.1U_0402_16V7K
E
DP_LVDS_HPD
L
CD_
ENBKL
L
INT_PWM
CD_
A
PU_CRT_R
A
P
U_CRT_G
A
U_CRT_B
P
A
U_CRT_HSYNC
P
T
E
ST25_L
T
ST36
E
T
E
ST37
D
_STEREOSYNC
P
T
EST36
T
E
ST37
T
ST25_H
E
A
U_ALERT#
P
D
_STEREOSYNC
P
T
ST19
E
T
E
ST18
1 2
R
R
C1
C1
4 4.7K_0402_5%LVDS@
4 4.7K_0402_5%LVDS@
1 2
5 4.7K_0402_5%LVDS@
5 4.7K_0402_5%LVDS@
C1
C1
R
R
2
C1
C1
7 4.7K_0402_5%
7 4.7K_0402_5%
R
R
C1
C1
2 4.7K_0402_5%
2 4.7K_0402_5%
R
R
1 2
C1
8 1K_0402_5%
8 1K_0402_5%
C1
R
R
2
C4
C4
5 100K_0402_5%
5 100K_0402_5%
R
R
C
C
C1
C1
03
03
EDP@
EDP@
0.1U_0402_16V7K
0.1U_0402_16V7K
2
C4
C4
4 100K_0402_5%
4 100K_0402_5%
R
R
R
R
9 100K_0402_5%
9 100K_0402_5%
C1
C1
2
C2
C2
0 100K_0402_5%
0 100K_0402_5%
R
R
1 2
R
R
C2
C2
2 150_0402_1%
2 150_0402_1%
1 2
C2
C2
4 150_0402_1%
4 150_0402_1%
R
R
1 2
R
R
C2
C2
7 150_0402_1%
7 150_0402_1%
1
R
R
C3
C3
0 1K_0402_5%
0 1K_0402_5%
1
C3
C3
5 510_0402_1%
5 510_0402_1%
R
R
1 2
C3
C3
7 1K_0402_5%@
7 1K_0402_5%@
R
R
1 2
C3
9 1K_0402_5%@
9 1K_0402_5%@
C3
R
R
1 2
C3
6 1K_0402_5%@
6 1K_0402_5%@
C3
R
R
1 2
1 1K_0402_5%@
1 1K_0402_5%@
C4
C4
R
R
1 2
C4
C4
6 1K_0402_5%@
6 1K_0402_5%@
R
R
1
3 510_0402_1%
3 510_0402_1%
C4
C4
R
R
1 8 2 7 3 6 4
@
@
EDP@
EDP@
1
12
1
@
@
2
R
R
P
C4
C4
P
1K_8P4R_5%
1K_8P4R_5%
3
VS
+
1
12
1
1
.8VS
+
2
2
VS
3
+
1
.8VS
5
+
A A
e
e
curity Classification
curity Classification
curity Classification
e
S
S
S
ssu
ssu
ed Date
ed Date
ed Date
ssu
I
I
I
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
H
T
T
T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
2
2
2
o
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
C
C
C
e
e
ciphered Date
ciphered Date
ciphered Date
e
D
D
D
i
tle
tle
tle
i
i
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
T
T
3 DISP/MISC/HDT
3 DISP/MISC/HDT
3 DISP/MISC/HDT
T
F
F
F
-9868P
-9868P
-9868P
A
A
A
L
L
L
h
ursday, May 16, 2013
ursday, May 16, 2013
ursday, May 16, 2013
h
h
T
T
T
1
o
.0
.0
.0
1
1
1
4
f
f
2
2
2
4
f
4
6
6
o
o
6
CyberForum.ru
5
S
A
TA_ATX_DRX_P0<23>
SA
TA HDD
SA
D D
SATA ODD
VGA
LAN WLAN
C C
EC
TA_ATX_DRX_N0<23>
S
TA_DTX_C_ARX_N0<23>
A
S
TA_DTX_C_ARX_P0<23>
A
S
TA_ATX_DRX_P1<23>
A
S
TA_ATX_DRX_N1<23>
A
S
A
TA_DTX_C_ARX_N1<23>
S
A
TA_DTX_C_ARX_P1<23>
+
.95VS
0
C
K_PCIE_VGA<12>
L
C
K_PCIE_VGA#<12>
L
C
L
K_LAN<25>
C
L
K_LAN#<25>
C
K_WLAN<23>
L
C
LK_WLAN#<23>
C
K_PCI_EC<29,8>
L
C
LK_PCI_DDR<8>
L
C_AD0<29>
P
L
C_AD1<29>
P
L
C_AD2<29>
P
L
P
C_AD3<29>
L
C_FRAME#<29,8>
P
S
RIRQ<29>
E
8 1K_0402_1%
8 1K_0402_1%
C5
C5
R
R
9 1K_0402_1%
9 1K_0402_1%
C5
C5
R
R
4
2
1 12
EMI@
EMI@
1 2
2 22_0402_5%
2 22_0402_5%
C6
C6
R
R
1 2
C6
3 0_0402_5%
3 0_0402_5%
C6
R
R
@EMI@
@EMI@
T
T
2
2
S
A
S
A
0
0
TA_ZVSS TA_ZVSS_095
S
TA_ACT
A
4
M_X1
8
4
8
M_X2
L
C_CLK0
P
L
C_CLK1
P
3
UC1E
UC1E
14
A
B
TA_TX0P
A
S
14
Y
A
TA_TX0N
A
S
B
16
A
S
TA_RX0N
A
A
Y
16
S
A
TA_RX0P
A
19
Y
S
TA_TX1P
A
B
19
A
S
TA_TX1N
A
A
Y
17
S
A
TA_RX1N
B
A
17
S
TA_RX1P
A
A
19
R
S
TA_ZVSS
A
A
P
19
S
A
TA_ZVDD_095
B
A
30
S
A
TA_ACT_L/GPIO67
A
12
Y
S
TA_X1
A
B
12
A
S
TA_X2
A
U
4
G
F
X_CLKP
U
5
G
F
X_CLKN
A
8
C
G
P_CLK0P
P
A
C
10
G
P
P_CLK0N
A
E
4
G
P
P_CLK1P
A
5
E
G
P_CLK1N
P
A
C4
G
PP_CLK2P
A
C5
G
PP_CLK2N
A
A
5
G
P_CLK3P
P
A
4
A
G
P_CLK3N
P
A
13
P
X
4M_25M_48M_OSC
1
N
2
X
4
8M_X1
N
1
X
4
8M_X2
A
2
Y
L
CCLK0
P
A
2
W
L
CCLK1
P
A
T
2
L
A
D0
A
T
1
L
A
D1
A
R
2
L
A
D2
A
1
R
L
D3
A
A
2
P
L
RAME_L
F
A
1
P
L
RQ0_L
D
A
29
V
S
RIRQ/GPIO48
E
A
25
P
L
C_CLKRUN_L
P
A
2
V
L
PC_PD_L/GEVENT5_L/SPI_TPM_CS_L
FT3_BGA769 @
FT3_BGA769 @
CLK/SATA/USB/SPI/LPC
CLK/SATA/USB/SPI/LPC
ATACLK S
LPC
F
F
T
3 REV 0.51
3 REV 0.51
T
S
U
S
BCLK/14M_25M_48M_OSC
U
B_ZVSS
S
U
B_HSD0P
S
U
S
B_HSD0N
U
B_HSD1P
S
U
B_HSD1N
S
U
S
B_HSD2P
U
S
B_HSD2N
U
B_HSD3P
S
U
S
B_HSD3N
U
B_HSD4P
S
U
S
B_HSD4N
U
B_HSD5P
S
U
B_HSD5N
S
U
S
B_HSD6P
U
B_HSD6N
S
U
USBSPI
B_HSD7P
S
U
S
B_HSD7N
U
B_HSD8P
S
U
B_HSD8N
S
U
S
B_HSD9P
U
B_HSD9N
S
U
S
B_SS_ZVSS
U
B_SS_ZVDD_095_USB3_DUAL
S
B_SS_0TXP
U
S
B_SS_0TXN
U
B_SS_0RXP
S
U
S
B_SS_0RXN
U
B_SS_1TXP
S
U
B_SS_1TXN
S
U
S
B_SS_1RXP
U
B_SS_1RXN
S
U
I_CLK/GPIO162
P
S
P
I_CS1_L/GPIO165
S
P
I_CS2_L/GPIO166
S
I_DO/GPIO163
P
S
P
I_DI/GPIO164
S
P
I_HOLD_L/GEVENT9_L
S
P
I_WP_L/GPIO161
S
2
4
W
4
G
A
U
B_ZVSS
S
4
L
A
L
5
A
4
J
A
5
J
A
G
7
A
G
8
A
1
G
A
G
2
A
1
F
A
F
2
A
1
E
A
2
E
A
D
1
A
D
2
A
1
C
A
C
2
A
1
B
A
2
B
A
A
1
A
2
A
A
E
10
A
U
S
BSS_ZVSS
E
8
A
U
S
BSS_ZVDD
2
T
1
T
2
V
1
V
1
R
2
R
1
W
2
W
7
U
A
A
9
W
A
A
R
4
A
A
R
11
A
A
R
7
A
A
U
11
A
9
U
A
A
1 2
C5
C5
7 11.8K_0402_1%
7 11.8K_0402_1%
R
R
U_SPI_CLK
P
U_SPI_CS1#
P
U_SPI_CS2#
P P
U_SPI_MOSI
P
U_SPI_MISO
P
U_SPI_WP#
1 2
C6
C6
0 1K_0402_1%
0 1K_0402_1%
R
R
1 2
C6
C6
1 1K_0402_1%
1 1K_0402_1%
R
R
1 2
@
@
0_0402_5%
0_0402_5%
C1
C1
30
30
R
R
2
1
1
2
T
T
2
2
2
2
T
T
U
S
B20_P0 <24>
U
S
B20_N0 <24>
U
S
B20_P1 <23>
U
S
B20_N1 <23>
U
B20_P2 <28>
S
U
B20_N2 <28>
S
U
S
B20_P3 <20>
U
B20_N3 <20>
S
U
S
B20_P4 <20>
U
S
B20_N4 <20>
U
B20_P8 <24>
S
U
B20_N8 <24>
S
U
SB20_P9 <24>
U
S
B20_N9 <24>
U
SB30_TX0P <24>
U
S
B30_TX0N <24>
U
B30_RX0P <24>
S
U
B30_RX0N <24>
S
U
B30_TX1P <24>
S
U
SB30_TX1N <24>
U
B30_RX1P <24>
S
U
B30_RX1N <24>
S
A
PU_SPI_CLK_R
R
R
10_0402_5%
10_0402_5%
@EMI@
@EMI@
C
C
10P_0402_50V8J
10P_0402_50V8J
@EMI@
@EMI@
U
WLAN (BT) Cardreader Int. Camera
Touch Screen
USB2.0-Right1
USB2.0-Right2
+
0
.95VALW
USB3.0-Right1
USB3.0-Right2
12
C1
C1
0
0
2
3
3
C1
C1
1
B2.0-Left1 (Debug Port)
S
1
B B
4
8KMHz CRYSTAL
4
8
M_X2
4
8
1
4
1
2
M_X1
C2
3
3
C2
C
C
4.7P_0402_50V8J
4.7P_0402_50V8J
S
S
S
e
ecurity Classification
curity Classification
curity Classification
e
I
I
I
ssu
ed Date
ed Date
ssued Date
ssu
T
T
T
H
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
2
2
0
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
3
C6
C6
4 1M_0402_5%
4 1M_0402_5%
R
R
2
2
3
3
C1
C1
Y
Y
8MHZ_8PF_X3S048000D81H-W
8MHZ_8PF_X3S048000D81H-W
4
4
1
2
2
C2
C2
C
C
4.7P_0402_50V8J
4.7P_0402_50V8J
2
A A
1
4
5
S
P
I ROM
E
C_
SPIDO<29>
E
C_
SPIDI<29>
E
SPICLK<29>
C_
E
C_
SPICS#<29>
1
6 10K_0402_5%
6 10K_0402_5%
C6
C6
R
R
+
VALW_APU
3
S
ocket: SP07000F500/SP07000H900
Please place UC5 close to UC1 APU,
4
MB ROM P/N:
SA00004LI00
C
C
C
o
ompal Secret Data
mpal Secret Data
mpal Secret Data
o
D
D
D
e
ciphered Date
ciphered Date
eciphered Date
e
885@
885@
1
01 33_0402_5%
01 33_0402_5%
C1
C1
R
R
885@
885@
1
C1
C1
02 33_0402_5%
02 33_0402_5%
R
R
885@
885@
1 2
R
R
C1
21 33_0402_5%
21 33_0402_5%
C1
885@
885@
1 2
C1
C1
24 33_0402_5%
24 33_0402_5%
R
R
2
2
2 2
A
P
U_SPI_MOSI
A
PU_SPI_CLK_R
A
U_SPI_CS1#
P
S
W
said ROM can change to 4MB
T
T
T
i
i
tle
tle
tle
i
F
F
F
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
T
T
T
T
h
h
ursday, May 16, 2013
ursday, May 16, 2013
ursday, May 16, 2013
h
4
M Byte
C5
C5
U
U
5
I
S
6
C
S
1
S
C
7
O
H
3
P
W
8
C
V
2
M
M
X25L3205DM2I-12G SO8
X25L3205DM2I-12G SO8
5
5
C2
C2
C
C
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
3-SATA/CLK/USB/SPI/LPC
3-SATA/CLK/USB/SPI/LPC
3-SATA/CLK/USB/SPI/LPC
L
L
L
A
A-9868P
-9868P
-9868P
A
2
A
P
O
S
U_SPI_MISO
LK
LD
4
N
C
D
G
7
7
7
1
1
1
1
.0
.0
o
o
o
.0
4
f
4
2
2
2
4
f
f
CyberForum.ru
CH7
CH7
@
@
8
5
12
A
U_PCIE_WAKE#
P
1
A
P
U_GPIO174
10P_0402_50V8J
10P_0402_50V8J
FAULT
G
E
VENT2
R
C_CLK
T
5
D
D
C2
C2
21
51H-40PT_SOD323-2
51H-40PT_SOD323-2
29
29 C
C C
C
S
Y
S S
U
S
U
S
U
SB_CHG_OC#
O
DD_
A
Z_
BITCLK_HD
H
DA_BITCLK
A
Z_
SDIN0_HD
C3
C3
0
0
C
C
1
20M_0402_5%
20M_0402_5%
C
C
1
1
C3
C3
1 2
CLKGEN ENABLE
D
EFAULT DEFAULT
CLKGEN DISABLED
12
1
2
5
+
1
.8VALW
71
71 C
C R
R
1 2
2
1
1U_0402_6.3V6K
1U_0402_6.3V6K
S_PWRGD
P_S3#
L LP_S5#
B_OC#0 B_OC#2
PLUGIN#
10P_0402_50V8J
10P_0402_50V8J
2
C1
C1
R
R
8P_0402_50V8D
8P_0402_50V8D
@
@
R
R
07
07
C1
C1
10K_0402_5%
10K_0402_5%
12
12
C1
C1
R
R 2K_0402_5%
2K_0402_5%
1 2
7
7
C9
C9
C
C
180P_0402_50V8J
180P_0402_50V8J
47K_0402_5%
47K_0402_5%
R
MRST#
S
A
MD G3-S5 clock issue
A
Z_
BITCLK_HD<26>
A
SDOUT_HD<26>
Z_
A
Z_
SDIN0_HD<26>
A
Z_
SYNC_HD<26>
A
RST_HD#<26>
Z_
C2
C2
Y
Y
1
04
04
2
4
1
2.768KHZ_7PF_Q13MC1461000100
2.768KHZ_7PF_Q13MC1461000100
3
3
SPI ROM 1.8V SPI ROM
LPC ROM
12
R
R 10K_0402_5%
10K_0402_5%
12
@
@
R
R 2K_0402_5%
2K_0402_5%
12
C1
C1
08
08
C1
C1
13
13
C1
C1
R
R 10K_0402_5%
10K_0402_5%
1
@
@
C1
C1
R
R 2K_0402_5%
2K_0402_5%
2
06
06
11
11
ESD@
ESD@
3
2
3.3V SPI ROM
DEFAULT
1
2
12
F
ollow check list & ORB_0C design 10 ms RC delay circuit on +1.8-V S5 power rail.
E
C_RSMRST#<29>
D D
.8VALW
1
+
1 2
R
R
27 10K_0402_5%
27 10K_0402_5%
C1
C1
+
3VALW_APU
VALW_APU
3
+
C C
S
TRAP PINS
B B
PULL HIGH
P LOW
A A
S
LP_S3#, SLP_S5# PU reserve
1 2
C1
28 2.2K_0402_5%
28 2.2K_0402_5%
C1
R
R
1 2
29 2.2K_0402_5%
29 2.2K_0402_5%
C1
C1
R
R
@
@
C5
C5
P
P
R
R
1 2 7 3 6 4
100K_8P4R_5%
100K_8P4R_5%
10K_0402_5%
10K_0402_5%
C2
C2
3
3
R
R
R
R
C2
5
5
C2
2
10K_0402_5%
10K_0402_5%
EMI@
EMI@
C1
5
5
C1
C
C
1 2
1 2
R
R
6 10K_0402_5%@
6 10K_0402_5%@
C9
C9
1 2
C9
7 10K_0402_5%@
7 10K_0402_5%@
C9
R
R
B
OOT FAIL TIMER
BOOT FAIL TIMER
LL
U
DISABLED
D
E
C
L
K_PCI_EC<29,7>
C
K_PCI_DDR<7>
L
L
C_FRAME#<29,7>
P
4
SY
S_PWRGD
c
lose to APU
P
TN_OUT#<29>
B
S
YS_PWRGD<29>
A
U_PCIE_WAKE#<25>
P
S
P_S3#<29>
L
S
P_S5#<29>
L
T
ST0/2
E
K
_RST#<29>
B
G
TEA20<29>
A
E
C_SCI#<29>
E
C_
SMI#<29>
S
P_CHG_CB0<24>
L
S
LP_CHG_CB1<24>
L
N_EN<25>
A
C
L
KREQ_WLAN#<23>
S
PK_DET<27>
C
KREQ_LAN#<25>
L
C
KREQ_PEG#<13>
L
U
B_OC#0<24,29>
S
U
B_CHG_OC#<24,29>
S
O
PLUGIN#<23>
DD_
U
SB_OC#2<24,29>
EMI@
EMI@
2
1
RC9
RC9
2 33_0402_5%
2 33_0402_5%
1 2
C9
3 33_0402_5%
3 33_0402_5%
C9
R
R
1 2
C9
C9
8 33_0402_5%
8 33_0402_5%
R
R
1 2
C1
00 33_0402_5%
00 33_0402_5%
C1
R
R
3
2K_X1
3
K_X2
2
+
3
VALW_APU
12
@
@
09
09
C1
C1
R
R 10K_0402_5%
10K_0402_5%
C1
14
14
C1
R
R 2K_0402_5%
2K_0402_5%
12
4
C1
C1
R
R 10K_0402_5%
10K_0402_5%
@
@
C1
C1
R
R 2K_0402_5%
2K_0402_5%
C_RST#_R
LP A
U_PCIE_RST#_R
P
R
S
MRST#
S
Y
A
P
U_PCIE_WAKE#
S
P_S3#
L
S
P_S5#
L
5
5
2
2
T
T
3
2
3
2
RTC_CLKCLK_PCI_EC CLK_PCI_DDR LPC_FRAME# GEVENT2
NORMAL POWR UP/RESET TIMING
DEFAULT
FAST POWER UP/RESET TIMING FOR SIMULATION
10
10
15
15
S_PWRGD
T
T
T
E
ST1/TMS
U
B_OC#0
S
U
B_CHG_OC#
S
O
DD_
PLUGIN#
U
B_OC#2
S
H
DA
_BITCLK
H
DA
_SDOUT
A
Z_
SDIN0_HD
H
DA
_SYNC
H
_RST#
DA
K_X1
K_X2
3
D
D
UC1
UC1
A
Y
4
L
P
C_RST_L
A
Y
9
P
C
IE_RST_L
A
Y
5
R
S
MRST_L
BA
8
P
W
R_BTN_L
A
19
M
P
W
R_GOOD
A
7
Y
2
2
3
3
S
S_RESET_L/GEVENT19_L
Y
A
11
W
W
KE_L/GEVENT8_L
A
A
3
Y
S
P_S3_L
L
B
5
A
S
P_S5_L
L
A
13
U
T
ST0
E
A
Y
10
T
E
ST1/TMS
A
Y
6
T
E
ST2
A
23
R
K
B
RST_L
A
31
R
G
20IN/GEVENT0_L
A
A
5
N
L
C_PME_L/GEVENT3_L
P
A
7
L
L
C_SMI_L/GEVENT23_L
P
A
15
P
A
_PRES/IR_RX0/GEVENT16_L
C
A
13
V
I
_TX0/GEVENT21_L
R
B
9
A
I
_TX1/GEVENT6_L
R
B
10
A
I
_RX1/GEVENT20_L
R
A
15
V
I
_LED_L/LLB_L/GPIO184
R
A
29
U
C
K_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60
L
A
29
W
C
K_REQ1_L/GPIO61
L
A
27
R
C
K_REQ2_L/GPIO62
L
A
27
V
C
K_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63
L
A
29
Y
C
K_REQG_L/GPIO65/OSCIN
L
A
8
Y
U
B_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L
S
A
1
W
U
B_OC1_L/TDI/GEVENT13_L
S
A
1
V
U
B_OC2_L/TCK/GEVENT14_L
S
A
1
Y
U
B_OC3_L/TDO/GEVENT15_L
S
A
2
N
A
_BITCLK
Z
A
1
N
A
_SDOUT
Z
A
K
2
A
Z
_SDIN0/GPIO167
A
K
1
A
Z
_SDIN1/GPIO168
A
1
M
A
Z
_SDIN2/GPIO169
A
L
2
A
Z
_SDIN3/GPIO170
A
M
2
A
Z
_SYNC
A
L
1
A
Z
_RST_L
A
J
2
X
3
2K_X1
A
J
1
X
3
2K_X2
FT3_BGA769 @
FT3_BGA769 @
P
ANEL_SEL
T
O
UCH_SEL
Sleep&
SM_EN
PlayMusic (ALC269)
PX5 Reserved DIS UMA
SPK_DET
ACPI/SD/AZ/GPIO/RTC/MISC
ACPI/SD/AZ/GPIO/RTC/MISC
Sequence
R
TC CLK
H L
eDP panel
H L
Non Touch
Touch
Panel
Panel
(turn off EHCI)
H
ALC259
B
oard_ID0
0 0 1 1
Onkyo
No Brand
0 1
IR
F
F
T
3 REV 0.51
3 REV 0.51
T
L
LVDS panel
Board_ID1Board Conf.
MSICHDA
0 1 0 1
D S
GPIO
P
X P B
o B
F
o
r DIS
P
S
_PWR_CTRL
D
S
_CLK/GPIO73
D
S
_CMD/GPIO74
D
S
D
_CD/GPIO75
S
D
_WP/GPIO76
S
D
_DATA0/GPIO77
S
_DATA1/GPIO78
D
S
_DATA2/GPIO79
D
S
_DATA3/GPIO80
D
S
D
_LED/GPIO45
S
L0/GPIO43
C
S
A0/GPIO47
D
S
C
L1/GPIO227
S
D
A1/GPIO228
S
P
KR/GPIO66
G
G
E
VENT2_L
G
E
VENT4_L
G
E
VENT7_L
G
VENT10_L
E
G
VENT11_L
E
G
VENT17_L
E
B
INK/GEVENT18_L
L
G
VENT22_L
E
G
NINT1_L/GPIO32
E
G
NINT2_L/GPIO33
E
F
NOUT0/GPIO52
A
F
NIN0/GPIO56
A
S_PWREN
XS_EN#
ard_ID0 ard_ID1
o
S_PWREN
X
G
G
G
G
G
G
G
G
G
G
G
G
P
R
B
23
A
A
22
Y
A
23
Y
A
Y
20
B
A
20
B
A
22
A
21
Y
A
24
Y
B
24
A
A
Y
25
A
25
U
A
U_SCLK0
P
A
25
V
A
U_SDATA0
P
A
Y
11
A
U_SCLK1
P
B
A
11
A
U_SDATA1
P
A
P
27
P
IO49
A
Y
28
P
IO50
P
IO51
P
IO55
P
IO57
P
IO58
P
IO59
P
IO64
P
P
IO68
P
IO69
P
IO70
P
IO71
IO174
T
CCLK
W
B
28
A
A
23
V
P
A
21
P
B
26
A
B
A
19
V
B
A
27
Y
P
B
A
27
A
21
U
P
A
Y
26
T
A
V
21
S
A
M
21
B
A
3
A
A
17
V
G
B
A
4
A
R
15
A
17
P
H
A
P
11
A
8
N
O
A
17
U
B
6
A
E
B
29
A
A
23
P
A
31
V
A
31
U
A
V
11
R
T
C6
C6
P
P
R
R
1 8 2 7 3 4 5
10K_8P4R_5%
10K_8P4R_5%
VGA@
VGA@
Q
Q
C3
C3
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
6
Q
Q
B
B
C3
C3
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
34
VGA@
VGA@
E
PXCONTROL
C_
5
P
S_RST#
X
C4
C4
C
C
O
DD_DA#_APU
C1
C1
C
C
_CLEAR#
A
NEL_SEL
ard_ID0
o
ard_ID1
o X
S_RST#
S_PWREN
X
O
M
P
U_GPIO174
VENT2
E
DM
DD_
C_
C_CLK
A
A
2
1
8
8
1 2
04
04
J
J
UCH_SEL _DET
I_HPD_N
DA#_APU
LID_OUT#
3
+
3
+
6
P
lace at GPU
1
VGA@
VGA@
P
XS_EN#
@ESD@
@ESD@
2
180P_0402_50V8J
180P_0402_50V8J
ESD@
ESD@
180P_0402_50V8J
180P_0402_50V8J
2
U_PCIE_RST#_R
AP
L
C_RST#_R
P
A
U_SCLK0 <10,11,23>
P
A
U_SDATA0 <10,11,23>
P
A
U_SCLK1 <30>
P
A
U_SDATA1 <30>
P
2
1
P
P
W @
W @
G
PIO174 PD CHK1.03
VS VALW_APU
E
C_
PXCONTROL <29>
PCIE_RST# is for PCIE devices on APU
1 2
8 33_0402_5%
8 33_0402_5%
C6
C6
R
R
1
C2
C2
8
8
C
C
150P_0402_50V8J
150P_0402_50V8J
A_RST# is for LPC devices
1
3 33_0402_5%
3 33_0402_5%
RC7
RC7
150P_0402_50V8J
150P_0402_50V8J
O
PWR <31>
DD_
P
S_RST# <12>
X
A
P
U_SPKR <26>
P
X
S_PWREN <14,39>
SW request
E
C_
LID_OUT# <29>
V
G
A_PWRGD <15,39>
R
T
C_CLK <29>
O
D DA#
D
0.1U_0402_16V4Z
0.1U_0402_16V4Z
H
2
2
1
C
C
7
7
C2
C2
2
A
U SMBus0 for S0 , SMBus1 for S 5
P
If APU_SMBUS no use pull high 10K
A
PU_SDATA0
A
P
U_SCLK0
A
P
U_SCLK1
A
P
S
M
_DET
B
o
ard_ID0
B
ard_ID1
o
P
S_RST#
X
S
M_DET
E
LID_OUT#
C_
DM
I_HPD_N
P
NEL_SEL
A
O
DA#_APU
DD_
1
2
2
C3
C3
C
C
@
@
2
2
C7
C7
2
2
R
R
@
@
100K_0402_5%
100K_0402_5%
1
R
RC7
4
4
C7
100K_0402_5%
100K_0402_5%
@
@
1 2
U_SDATA1
1 2
35 10K_0402_5%
35 10K_0402_5%
C1
C1
R
R
269@
269@
1
C1
C1
37 10K_0402_5%UMA@
37 10K_0402_5%UMA@
R
R
1 2
38 10K_0402_5%
38 10K_0402_5%
C1
C1
R
R
UMA@
UMA@
VGA@
VGA@
C1
C1
33
33
R
R
1 2
1 2
36 1K_0402_5%
36 1K_0402_5%
C1
C1
R
R
259@
259@
1 2
C9
C9
4 10K_0402_5%
4 10K_0402_5%
R
R
3
VS
+
2
G
G
C2
C2
Q
Q 2
N7002KW_SOT323-3
N7002KW_SOT323-3
2
1 3
D
D
VS
3
+
C1
25
25
C1
R
R 10K_0402_5%
10K_0402_5%
EDP@
EDP@
1 2
C1
26
26
C1
R
R 10K_0402_5%
10K_0402_5%
LVDS@
LVDS@
1 2
3
VS
+
+
2
1
6
A
A
C1
C1
Q
Q 2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
1
C1
C1
P
P
R
R
1 8 2 3 6 4 5
2.2K_8P4R_5%
2.2K_8P4R_5%
2
S
S
T
VS
3
2
R
R
05
05
C1
C1
10K_0402_5%
10K_0402_5%
1
A
1K_0402_5%
1K_0402_5%
O
U_PCIE_RST# <12,23,25>
P
L
PC_RST# <29>
7
3
VS
+
VALW_APU
3
+
+
3
VS
3
VALW_APU
+
H
DM
I_HPD <21,6>
VRAM_SEL Control by X76
VS
3
+
R
R
C9
C9
5
5
10K_0402_5%
10K_0402_5%
TOUCH@
TOUCH@
1 2
UCH_SEL
2
9
9
C9
C9
R
R 1K_0402_5%
1K_0402_5%
NTOUCH@
NTOUCH@
1
O
DA# <23>
DD_
close to APU
e
curity Classification
curity Classification
curity Classification
e
e
S
S
S
ssu
ssu
ed Date
ed Date
ed Date
ssu
I
I
I
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
H
T
T
T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
2
2
2
o
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
C
C
C
e
e
ciphered Date
ciphered Date
ciphered Date
e
D
D
D
i
tle
tle
tle
i
i
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
T
T
3 GPIO/AZ/MISC
3 GPIO/AZ/MISC
3 GPIO/AZ/MISC
T
F
F
F
A
-9868P
-9868P
-9868P
A
A
L
L
L
h
h
ursday, May 16, 2013
ursday, May 16, 2013
ursday, May 16, 2013
h
T
T
T
1
o
.0
.0
.0
1
1
1
4
4
f
2
2
2
f
4
f
8
8
o
o
8
CyberForum.ru
5
5V OF APU
1.
+
.5V
1
3
A
@
2
1
1
4010U_0603_6.3V6M
4010U_0603_6.3V6M
3910U_0603_6.3V6M
3910U_0603_6.3V6M C
C C
C
D D
2
330.1U_0402_16V7K
C
C
C
C330.1U_0402_16V7K
C
C
C
C
2
2
2
2
2
340.1U_0402_16V7KCC340.1U_0402_16V7K
410.1U_0402_16V7K
410.1U_0402_16V7K
350.1U_0402_16V7K
350.1U_0402_16V7K
420.1U_0402_16V7K
420.1U_0402_16V7K
C
C
C
C
C
C
C
C
C
C
CC
C
C
1
1
1
1
2
2
2
360.1U_0402_16V7K
360.1U_0402_16V7K
430.1U_0402_16V7K
430.1U_0402_16V7K C370.1U_0402_16V7KCC370.1U_0402_16V7K
C
C
C
C
C
C
C
C
C
1
1
1
1
@
1
4
4
CC1
CC1
2
U_0805_6.3V6M
U_0805_6.3V6M 7
7 4
4
AMD CKL v1.01
VDDIO_MEM_S
AMD CKL v1.01 4.7uF
1.8VALW & 1.8VS OF APU
VDD_18
VDD_18_ALW
+
1
+
.8VALW
1
1 2
@
@
R
R
16 0_0603_5%
16 0_0603_5%
C1
C1
C C
1
1
501U_0402_6.3V6KCC501U_0402_6.3V6K
494.7U_0603_6.3V6K
494.7U_0603_6.3V6K C
C
CC
C
C
2
2
+
.8VALW_APU
1
0
.5A
1
1
511U_0402_6.3V6K
511U_0402_6.3V6K
521U_0402_6.3V6K
521U_0402_6.3V6K
C
C
C
C
C
C
C
C
2
1
1
1
551U_0402_6.3V6K
551U_0402_6.3V6K
541U_0402_6.3V6K
541U_0402_6.3V6K
531U_0402_6.3V6K
531U_0402_6.3V6K
C
C
C
C
C
C
C
C
C
C
C
C
2
2
2
2
.8VS
5710U_0603_6.3V6M
5710U_0603_6.3V6M C
C C
C
3.3VALW & 3.3VS OF APU
+
1
1
721U_0402_6.3V6KCC721U_0402_6.3V6K CC
2
V
DDIO_AZ_ALW
VDDIO_33_ALW
VDDIO_33
+
RT
.5VS
f
or VDDIO_AZ_ALW 0.1A
1
1
664.7U_0603_6.3V6K
664.7U_0603_6.3V6K
671U_0402_6.3V6K
671U_0402_6.3V6K C
C
C
C
C
C
C
C
2
2
P
lace on TOP
4.7uF 1uF 180pFAMD CKL v1.01
1 3 1
C_APU
4
.5uA
1
98
98 C
C C
C
2
0.22U_0402_16V7K
0.22U_0402_16V7K
+
3
VALW_APU
for VDDIO_33_ALW 0.2A
+
VS
3
R
R
C1
C1
+
3
VS_APU
1 2
@
@
17 0_0603_5%
17 0_0603_5%
0.2A
1
711U_0402_6.3V6K
711U_0402_6.3V6K C
C C
C
2
1
1
741U_0402_6.3V6K
741U_0402_6.3V6K
751U_0402_6.3V6K
751U_0402_6.3V6K C
C
C
C
C
C
C
B B
C
2
2
RTC OF APU
A A
+
3
VL
2
CH7
CH7
51H-40PT_SOD323-2
51H-40PT_SOD323-2
+
RT
C5
C5
D
D
C
1
5
4
10uF 0.1uF 180pF
2 8 4
10uF 1uF 180pF
1 7 1
1 6 1
1
1
2
1
1
1
1
601U_0402_6.3V6K
601U_0402_6.3V6K
611U_0402_6.3V6K
611U_0402_6.3V6K
581U_0402_6.3V6K
581U_0402_6.3V6K
591U_0402_6.3V6K
591U_0402_6.3V6K
621U_0402_6.3V6K
621U_0402_6.3V6K
C
C
C
C
C
C
C
C C
C
2
C
C
C
C
C
C
C
C
C
C
2
2
2
2
1
1
691U_0402_6.3V6K
691U_0402_6.3V6K
701U_0402_6.3V6K
701U_0402_6.3V6K
C
C
C C
C
CC
C
2
2
2
2 1
12
R
R
C1
23
23
C1
120_0402_5%
120_0402_5%
r
oute to 20mil
1
@
@
J
J
CM
CM
OS
OS
2
4
1.5A
631U_0402_6.3V6K
631U_0402_6.3V6K C
C C
C
1
2
1
641U_0402_6.3V6K
641U_0402_6.3V6K C
C C
C
2
22
22
C1
C1
R
R
1 2
10K_0402_5%
10K_0402_5%
+
.8VALW_APU
1
+
3VALW_APU
+
0
.95VALW_APU_USB3
+
0
.95VALW_APU
+
+
C_APU_R
RT
RT
0
1A
.
+
1
0.5A
0.2A
1A
0.5A
4.5uA
C_APU
+
.5VS
3A
1
3
C1
C1
F
F
U
U
J
5
3
V
DIO_MEM_S_1
.5V
D
L
2
3
V
DIO_MEM_S_2
D
L
7
3
DIO_MEM_S_3
VD
N
5
3
V
DIO_MEM_S_4
D
R
1
3
V
DIO_MEM_S_5
D
7
R3
V
DIO_MEM_S_6
D
U
2
3
V
DIO_MEM_S_7
D
5
U3
DIO_MEM_S_8
VD
1
W3
DIO_MEM_S_9
VD
W
2
3
V
DDIO_MEM_S_10
W
7
3
DIO_MEM_S_11
VD
A
31
A
DIO_MEM_S_12
VD
A
A
35
V
DIO_MEM_S_13
D
A
32
C
V
DIO_MEM_S_14
D
AC
37
VD
DIO_MEM_S_15
AE
31
VD
DIO_MEM_S_16
AE
35
VD
DIO_MEM_S_17
AG
32
VD
DIO_MEM_S_18
AG
37
VD
DIO_MEM_S_19
AJ
35
VD
DIO_MEM_S_20
AL
32
VD
DIO_MEM_S_21
AL
37
VD
DIO_MEM_S_22
AR
35
VD
DIO_MEM_S_23
AL
10
VD
DIO_AZ_ALW_1
AL
11
VD
DIO_AZ_ALW_2
B1
VD
D_18_ALW_1
B2
VD
D_18_ALW_2
AL
13
D_33_ALW_1
VD
13
AM
D_33_ALW_2
VD
5
AR
D_095_USB3_DUAL_1
VD
4
AU
D_095_USB3_DUAL_2
VD
V
7
A
D
D_095_USB3_DUAL_3
V
W
5
A
D
D_095_USB3_DUAL_4
V
E
11
A
D
D_095_ALW_1
V
13
E
A
D_095_ALW_2
D
V
11
J
A
D_095_ALW_3
D
V
13
J
A
D_095_ALW_4
D
V
N
4
A
D
DBT_RTC_G
V
FT3_BGA769 @
FT3_BGA769 @
T
T
F
F
POWER
POWER
3 REV 0.51
3 REV 0.51
V
DCR_CPU_1
D
V
DCR_CPU_2
D
V
DCR_CPU_3
D
V
DCR_CPU_4
D
V
D
DCR_CPU_5
V
D
DCR_CPU_6
V
D
DCR_CPU_7
V
D
DCR_CPU_8
V
DCR_CPU_9
D
V
DCR_CPU_10
D
V
DCR_CPU_11
D
V
DCR_CPU_12
D
V
D
DCR_CPU_13
V
D
DCR_CPU_14
V
DCR_CPU_15
D
V
DCR_CPU_16
D
V
DCR_CPU_17
D
V
DCR_CPU_18
D
V
D
DCR_CPU_19
V
D
DCR_CPU_20
V
D
DCR_CPU_21
V
D
DCR_CPU_22
V
D
DCR_CPU_23
V
D
DCR_CPU_24
V
D
DCR_CPU_25
V
D
DCR_CPU_26
V
DCR_NB_1
D
V
DCR_NB_2
D
V
DCR_NB_3
D
V
DCR_NB_4
D
V
DCR_NB_5
D
V
DCR_NB_6
D
V
DCR_NB_7
D
V
DCR_NB_8
D
V
DCR_NB_9
D
V
DCR_NB_10
D
V
D
DCR_NB_11
V
D
DCR_NB_12
V
D
DCR_NB_13
V
D
DCR_NB_14
V
DCR_NB_15
D
V
D
DCR_NB_16
V
DCR_NB_17
D
V
DCR_NB_18
D
V
D
DCR_NB_19
V
D
DCR_NB_20
V
DDCR_NB_21
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
D_095_GFX_1
D
V
D
D_095_GFX_2
V
D
D_095_GFX_3
D
D
D
D
D
D
D
D_095_1
D
D_095_2
D_095_3
D
D_095_4
D
D_095_5
D
D_095_6
D
D_095_7
D
D
D_095_8
D_095_9
D
D_18_1
D_18_2
D_18_3
D_18_4
D_33_1
D_33_2
15A/21A
L
1
2
+
PU_CORE
3 5 7 9 1 3 7 1 3 7 1 3 7
1
2
3
2
7
2
21 23 27 21 23 27 21 23 27
3 7 1 3 7 1 3 7 3 7
1
3 7
1
13 17
17 15 17 19 17 21
15 17
23
27 21 27 21 23 27
23
25
0
1
0
10
A
13A/17A
+
A
PU_CORE_NB
1.5A
+
1.8VS
0.2A
+
3
VS_APU
5A
+
.95VS_APU
0
0.6A
+
.95VS_APU_GFX
0
L
2
L
2
L
2
L
2
N
2
N
2
N
2
R
2
R
2
R
2
U
2
U
2
U
2 W W W A
A A
A A
A A
C A
C A
C A
E A
E A
E
L
1 L
1 N
1 N
1 N
1 R
1 R
1 R
1 U
1 U
1 W W A
A A
A A
C13 A
C A
E A
E A
E A
G A
G
A
2 A
3 B
3 C
3
A
M A
M
A
G A
G A
J A
J A
L A
L A
L A
M A
M
U
1 W A
A
2
U
U
C1G
C1G
8
A
S
S_1
V
3
1
A
S_2
S
V
3
2
A
S_3
S
V
1
3
A
S_4
S
V
3
5
A
S
S_5
V
3
9
A
S
S_6
V
8
B
S_7
S
V
3
1
B
S_8
S
V
3
2
B
S
S_9
V
3
1
B
S
S_10
V
3
9
B
S
S_11
V
1
C
S_12
S
V
2
C
S_13
S
V
5
C
S_14
S
V
7
C
S_15
S
V
9
C
S
S_16
V
1
1
C
S
S_17
V
1
3
C
S_18
S
V
5
1
C
S_19
S
V
1
7
C
S
S_20
V
1
9
C
S
S_21
V
2
1
C
S
S_22
V
3
2
C
S_23
S
V
5
2
C
S
S_24
V
2
7
C
S
S_25
V
9
2
C
S_26
S
V
1
3
C
S_27
S
V
3
3
C
S
S_28
V
3
5
C
S
S_29
V
7
3
C
S_30
S
V
9
3
C
S_31
S
V
4
1
C
S
S_32
V
9
D
S
S_33
V
1
1
D
S_34
S
V
1
3
D
S
S_35
V
3
E
S
S_36
V
4
E
S_37
S
V
9
E
S
S_38
V
1
1
E
S
S_39
V
3
1
E
S_40
S
V
7
2
E
S_41
S
V
3
1
E
S
S_42
V
E
3
5
V
S
S_43
E
3
8
V
S_44
S
E
9
3
V
S_45
S
G
3
V
S_46
S
G
7
V
S_47
S
G
1
1
V
S
S_48
G
1
3
V
S
S_49
G
1
5
V
S
S_50
G
7
1
V
S_51
S
G
1
2
V
S_52
S
G
5
2
V
S_53
S
G
29
V
SS_54
G
5
3
V
S_55
S
G
3
7
V
S
S_56
G
3
9
V
S
S_57
G
4
1
V
S
S_58
H
1
1
V
S_59
S
H
3
1
V
S_60
S
H
3
2
V
S_61
S
H
1
3
V
S_62
S
FT3_BGA769 @
FT3_BGA769 @
F
F
0.95VALW & 0.95VS OF APU
+
.95VALW
0
1 2
@
@
C1
C1
19 0_0603_5%
19 0_0603_5%
R
R
S
S
S
e
e
curity Classification
curity Classification
curity Classification
e
I
I
I
ssu
ssued Date
ed Date
ed Date
ssu
T
T
T
H
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+
.95VALW_APU_USB3
0
1A
+
.95VALW
0
1
@
@
20 0_0603_5%
20 0_0603_5%
C1
C1
R
1
801U_0402_6.3V6K
801U_0402_6.3V6K C
C C
C
2
C
C
C
o
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
R
D
D
D
e
eciphered Date
ciphered Date
ciphered Date
e
1
1
1
781U_0402_6.3V6K
781U_0402_6.3V6K
7710U_0603_6.3V6M
7710U_0603_6.3V6M C
C C
C
791U_0402_6.3V6K
791U_0402_6.3V6K
C
C
C
C
C
C
C
C
2
2
2
2
2
2
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
+
.95VALW_APU
0
2
0.5A
1
1
831U_0402_6.3V6K
831U_0402_6.3V6K
821U_0402_6.3V6K
821U_0402_6.3V6K
C
C
C
C
C
C
C
C
2
2
2
1
1
841U_0402_6.3V6K
851U_0402_6.3V6K
851U_0402_6.3V6K
841U_0402_6.3V6K C
C
C
C
C
C
C
C
2
2
T
3 REV 0.51
3 REV 0.51
T
+
1
U
U
C1H
GND
GND
J3
S_63
VS
J7
S_64
S
V
J8
S_65
VS
9
J3
S_66
VS
1
1
K
S_67
VS
3
K1
S
S_68
V
1
7
K
S
S_69
V
1
9
K
S
S_70
V
2
1
K
S
S_71
V
2
3
K
S
S_72
V
5
2
K
S_73
S
V
7
2
K
S_74
S
V
9
2
K
S_75
S
V
3
1
K
S
S_76
V
3
L
S_77
S
V
7
L
S_78
S
V
8
L
S_79
S
V
0
1
L
S_80
S
V
1
1
L
S
S_81
V
1
5
L
S
S_82
V
1
9
L
S
S_83
V
3
1
L
S
S_84
V
9
3
L
S_85
S
V
1
4
L
S_86
S
V
1
M
S_87
S
V
2
M
S
S_88
V
3
N
S
S_89
V
7
N
S
S_90
V
5
1
N
S_91
S
V
9
1
N
S_92
S
V
5
2
N
S_93
S
V
2
9
N
S
S_94
V
3
1
N
S
S_95
V
3
9
N
S_96
S
V
1
P
S_97
S
V
2
P
S
S_98
V
3
R
S
S_99
V
7
R
S
S_100
V
5
1
R
S_101
S
V
9
1
R
S_102
S
V
2
5
R
S
S_103
V
2
9
R
S
S_104
V
9
3
R
S_105
S
V
1
4
R
S_106
S
V
1
U
S_107
S
V
2
U
S
S_108
V
3
U
S
S_109
V
7
U
S_110
S
V
8
U
S_111
S
V
1
1
U
S
S_112
V
1
5
U
S
S_113
V
9
1
U
S_114
S
V
5
2
U
S_115
S
V
2
9
U
S
S_116
V
3
1
U
S_117
S
V
9
3
U
S_118
S
V
3
W
S_119
S
V
5
W
S
S_120
V
1
1
W
S
S_121
V
5
1
W
S_122
S
V
1
9
W
S
S_123
V
2
5
W
S
S_124
V
AMD CKL v1.01
VDD_095_USB3_DUAL VDD_095 VDD_095_ALW VDD_095_GFX
0
.95VS
2
P
P
J2
J2
2
P_43X79
P_43X79
JUM
JUM
@
@
1
1
5A
1
1
8610U_0603_6.3V6M
8610U_0603_6.3V6M C
C C
C
1
881U_0402_6.3V6K
881U_0402_6.3V6K
8710U_0603_6.3V6M
8710U_0603_6.3V6M
C
C
C
C C
C
C
C
2
2
2
T
T
i
Title
tle
tle
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
1
1
911U_0402_6.3V6K
911U_0402_6.3V6K
891U_0402_6.3V6K
891U_0402_6.3V6K
901U_0402_6.3V6K
901U_0402_6.3V6K
C
C
C
C
C
C
C
C
C
C
C
C
2
2
F
F
F
T
T
T
h
hursday, May 16, 2013
ursday, May 16, 2013
ursday, May 16, 2013
h
+
0
.95VS_APU
1
1
921U_0402_6.3V6K
921U_0402_6.3V6K C
C C
C
2
2
T
3 PWR/GND
3 PWR/GND
3 PWR/GND
T
T
L
L
L
C1H
9
2
W
S
V
9
3
W
S
V
1
4
W
S
V
1
Y
S
V
2
Y
S
V
3
A
A
S
V
7
A
A
S
V
A
8
A
S
V
A
11
A
S
V
15
A
A
S
V
19
A
A
S
V
A
25
A
S
V
A
29
A
S
V
A
39
A
S
V
C
3
A
S
V
7
C
A
S
V
11
C
A
S
V
C
15
A
S
V
C
19
A
S
V
25
C
A
S
V
C
29
A
S
V
C
31
A
S
V
C
39
A
S
V
41
C
A
S
V
E
3
A
S
V
E
7
A
S
V
A
E
25
V
S
A
E
29
V
S
A
32
E
V
S
A
39
E
V
S
A
G
3
V
S
A
G
5
V
S
A
G
10
V
S
A
11
G
V
S
A
13
G
V
S
A
15
G
V
S
A
G
19
V
S
A
G
25
V
S
A
G
29
V
S
A
G
31
V
S
A
39
G
V
S
A
41
G
V
S
A
1
H
V
S
A
H
2
V
S
A
J
3
V
S
A
J
7
V
S
A
15
J
V
S
A
17
J
V
S
A
19
J
V
S
A
23
J
V
S
A
25
J
V
S
A
J
29
V
S
A
J
31
V
S
A
J
32
V
S
A
J
39
V
S
A
3
L
V
S
A
L
8
V
S
A
15
L
V
S
A
17
L
V
S
A
19
L
V
S
A
25
L
V
S
A
29
L
V
S
FT3_BGA769
FT3_BGA769
10uF 1uF 180pF
2 3 1 2 5 1
1 1
A
A
-9868P
-9868P
-9868P
A
S_125
S_126
S_127
S_128
S_129
S_130
S_131
S_132
S_133
S_134
S_135
S_136
S_137
S_138
S_139
S_140
S_141
S_142
S_143
S_144
S_145
S_146
S_147
S_148
S_149
S_150
S_151
S_152
S_153
S_154
S_155
S_156
S_157
S_158
S_159
S_160
S_161
S_162
S_163
S_164
S_165
S_166
S_167
S_168
S_169
S_170
S_171
S_172
S_173
S_174
S_175
S_176
S_177
S_178
S_179
S_180
S_181
S_182
S_183
S_184
S_185
S_186
F
F
T
T
3 REV 0.51
3 REV 0.51
4
FB
FB
MA-L11-201209-300LMA30T
MA-L11-201209-300LMA30T
1
GND
GND
S_187
VS
S_188
S
V
S
S_189
V
S
S_190
V
S
S_191
V
S
S_192
V
S_193
S
V
S_194
S
V
S_195
S
V
S_196
S
V
S
S_197
V
S
S_198
V
S
S_199
V
S
S_200
V
S
S_201
V
S
S_202
V
S_203
S
V
S_204
S
V
S_205
S
V
S
S_206
V
S
S_207
V
S
S_208
V
S_209
S
V
S_210
S
V
S
S_211
V
S
S_212
V
S_213
S
V
S_214
S
V
S_215
S
V
S
S_216
V
S
S_217
V
S
S_218
V
S_219
S
V
S_220
S
V
S
S_221
V
S
S_222
V
S_223
S
V
S_224
S
V
S
S_225
V
S
S_226
V
S_227
S
V
S_228
S
V
S
S_229
V
S
S_230
V
S_231
S
V
S_232
S
V
S
S_233
V
S
S_234
V
S_235
S
V
S_236
S
V
S
S_237
V
S
S_238
V
S_239
S
V
S
S_240
V
S
S_241
V
S_242
S
V
SBG_DAC
S
V
B
V
P
@
@
LC1
LC1
1 2
9
9
9
39
AL
41
AL
M
11
A
M
27
A
M
31
A
N
3
A
7
N
A
39
N
A
31
P
A
3
R
A
R
13
A
R
17
A
R
21
A
R
25
A
R
29
A
R
39
A
R
41
A
1
U
A
2
U
A
U
3
A
U
15
A
U
19
A
23
U
A
27
U
A
U
39
A
V
9
A
W
3
A
7
W
A
13
W
A
W
15
A
W
17
A
W
19
A
21
W
A
23
W
A
W
25
A
W
27
A
31
W
A
33
W
A
W
35
A
W
37
A
39
W
A
41
W
A
Y
13
A
Y
15
A
18
Y
A
30
Y
A
2
A
B
A
7
B
13
A
B
15
A
B
A
18
B
A
21
B
25
A
B
A
31
B
A
35
B
A
39
B
5
1
A
L
31
A
URN
M
29
A
S
EN
+
0
.95VS_APU_GFX
0.6A
o
o
o
f
f
f
1
1
9510U_0603_6.3V6M
9510U_0603_6.3V6M
961U_0402_6.3V6K
961U_0402_6.3V6K
C
C
C
C
C
C
C
C
2
2
1
1
1
.0
.0
.0
4
4
2
2
2
4
CyberForum.ru
5
REF_DQA
+V
D
DR_
DDR_
D
DR_
D
DR_AB_D2
D
DR_
D
DR_
D
D D
D
DR_
A_CKE0<5>
AB_BS2<11,5>
DR_
C C
B B
A A
+
D
A_CLK0<5>
DR_
D
DR_
A_CLK0#<5>
D
AB_BS0<11,5>
DR_
D
DR_
AB_WE#<11,5>
D
AB_CAS#<11,5>
DR_
D
DR_
A_SCS1#<5>
D
VS
3
DR_
D
DR_
D
DR_AB_DQS1
D
DR_
D
DR_
D
DR_AB_D16
D
DR_
D
DR_
D
DR_
D
DR_AB_D18
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_AB_D50
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_AB_D59
2
20
20 D
D C
C
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
5
AB_D0 AB_D1
AB_DM0
AB_D3
AB_D8 AB_D9
AB_DQS#1
AB_D10 AB_D11
AB_D17
AB_DQS#2 AB_DQS2
AB_D19
AB_D24 AB_D25
AB_DM3
AB_D26 AB_D27
A_CKE0
AB_BS2
AB_MA12 AB_MA9
AB_MA8 AB_MA5
AB_MA3 AB_MA1
A_CLK0 A_CLK0#
AB_MA10 AB_BS0
AB_WE# AB_CAS#
AB_MA13 A_SCS1#
AB_D32 AB_D33
AB_DQS#4 AB_DQS4
AB_D34 AB_D35
AB_D40 AB_D41
AB_DM5
AB_D42 AB_D43
AB_D48 AB_D49
AB_DQS#6 AB_DQS6
AB_D51
AB_D56 AB_D57
AB_DM7
AB_D58
+1
.5V
JDDR3
JDDR3
L
L
1
R
EF_DQ
V
3
S
S
V
5
Q
0
D
7
Q
1
D
9
VS
S
11
DM
0
13
VS
S
15
DQ
2
17
DQ
3
19
VS
S
21
DQ
8
23
DQ
9
25
VS
S
27
DQ
S1#
29
DQ
S1
31
V
S
S
33
D
10
Q
35
DQ
11
37
VS
S
39
DQ
16
41
D
Q
17
43
V
S
S
45
D
Q
S2#
47
D
Q
S2
49
V
S
S
51
D
18
Q
53
D
19
Q
55
V
S
S
57
D
24
Q
59
D
25
Q
61
V
S
S
63
D
M
3
65
V
S
S
67
D
Q
26
69
D
27
Q
71
V
S
S
73
C
E0
K
75
V
D
D
7
7
N
C
79
B
2
A
81
V
D
D
83
A
2/BC#
1
5
8
A
9
87
V
D
D
8
9
A
8
1
9
A
5
93
V
D
D
5
9
A
3
9
7
A
1
99
V
D
D
101
C
K
0
103
C
0#
K
105
V
D
D
107
A
0/AP
1
109
B
A
0
111
V
D
D
113
W
E
#
115
C
S#
A
117
V
D
D
119
A
1
3
121
S
1
#
123
V
D
D
125
T
ST
E
127
V
S
S
129
D
Q
32
131
D
Q
33
133
V
S
S
135
D
S4#
Q
137
D
Q
S4
139
V
S
S
141
D
34
Q
143
D
35
Q
145
V
S
S
147
D
40
Q
149
D
41
Q
151
V
S
S
153
D
M
5
155
V
S
S
157
D
42
Q
159
D
Q
43
161
V
S
S
163
D
48
Q
165
D
Q
49
167
V
S
S
169
D
S6#
Q
171
D
S6
Q
173
V
S
S
175
D
50
Q
177
D
51
Q
179
V
S
S
181
D
56
Q
183
D
57
Q
185
V
S
S
187
D
7
M
189
V
S
S
191
D
58
Q
193
D
59
Q
195
V
S
S
197
S
0
A
199
V
DSPD
D
201
1
A
S
203
0
.75VS
+
T
T
V
205
D1
N
G
207
O
SS1
B
LCN_DAN06-K4406-0103
LCN_DAN06-K4406-0103
@
@
V
R
R
E
VS DQ DQ VS
D
Q D
Q V D D
V D D
V
D
E
SET#
V D D
V D D
V
D
V D D
V D D
V
D
Q D
Q
V D D
V
C
V
V
V
V
V
C
C
V
B
R
A
V
O
D
V O
D
V
EF_CA
V
Q
D
Q
D
V
D
V
Q
D
Q
D
V
Q
D
Q
D
V Q
D
Q
D
V
Q
D
Q
D
V
Q
D
Q
D
V
D
V
Q
D
Q
D
V
Q
D
Q
D
V Q
D
Q
D
V
Q
D
Q
D
V
V
ENT#
S
S V
N
G
SS2
O
B
S0#
Q Q
M
S Q Q
S Q Q
S
M
S Q Q
S Q Q
S S3#
S Q Q
S
K
D A A
D A
D
D
D
K
D
D S
D
N
D
S
S M S
S
S
S5#
S
S
S M S
S
S
S7#
S
S
D C
D2
4
+1
.5V
2
S
4
D
AB_D4
4 5 S
S0
S
S
6
Q
7
Q
S
S 12 13
S
S
1
S 14 15
S 20 21
S
2
S 22 23
S 28 29
S
S3
S 30 31
S
E1
D 1
5
4
1
D
1
1 A
7
D A
6 A
4
D A
2 A
0
D
1
K 1#
D
1
A S#
D
#
0 T0
D T1
C
D
S 36 37
S
4
S 38 39
S 44 45
S
S5
S 46 47
S 52 53
S
6
S 54 55
S 60 61
S
S7
S 62 63
S
A
L
T
T
DR_
6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
74 76 78 80 82 84 8
6
88
0
9 9
2
94
6
9 9
8 100 102 104 106 108 110 112 114 116 118 120 1
22 124 126
128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
206 208
D
D
D
D
4
DDR_
DR_ D
DR_
D
DR_
D
DR_AB_D7
D
DR_
D
DR_
D
DR_
M
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
DR_ D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
D
DR_AB_MA6
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
D
DR_
D
DR_
D
DR_A_ODT1
+
V
D
DR_AB_D36
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_
D
DR_AB_D45
DR_ D
DR_
D
DR_
D
DR_
D
DR_AB_D52
D
DR_
D
DR_AB_DM6
D
DR_
D
DR_
D
DR_
D
DR_
DR_ D
DR_
D
DR_
D
DR_
M A
P
A
P
0
+
AB_D5
AB_DQS#0
AB_DQS0
AB_D6
AB_D12 AB_D13
AB_DM1
EM_MAB_RST#
AB_D14 AB_D15
AB_D20 AB_D21
AB_DM2
AB_D22 AB_D23
AB_D28 AB_D29
AB_DQS#3
AB_DQS3
AB_D30 AB_D31
A_CKE1
AB_MA15 AB_MA14
AB_MA11 AB_MA7
DR_
AB_MA4
AB_MA2 AB_MA0
A_CLK1 A_CLK1#
AB_BS1 AB_RAS#
DR_
A_SCS0# A_ODT0
REF_CAA
AB_D37
AB_DM4
AB_D38 AB_D39
AB_D44
AB_DQS#5
AB_DQS5
AB_D46 AB_D47
AB_D53
AB_D54 AB_D55
AB_D60 AB_D61
AB_DQS#7
AB_DQS7
AB_D62 AB_D63
M_MAB_EVENT#
E
U_SDATA0 U_SCLK0
.75VS
DDR3 SO-DIMM A
verse Type
Re
M_MAB_RST# <11,5>
E
M
D
DR_
A_CKE1 <5>
A_CLK1 <5>
DR_
D
A_CLK1# <5>
DR_
D
DR_
AB_BS1 <11,5>
D
AB_RAS# <11,5>
DR_
D
A_SCS0# <5>
DR_
D
DR_
A_ODT0 <5>
D
DR_
A_ODT1 <5>
D
M_MAB_EVENT# <11,5>
E
M
U_SDATA0 <11,23,8>
P
A
U_SCLK0 <11,23,8>
P
A
e
curity Classification
curity Classification
curity Classification
e
e
S
S
S
I
I
I
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
H
T
T
T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ssu
ssu
ssu
ed Date
ed Date
ed Date
3
S
O-DIMM VREF
AB_DQS[0..7] <11,5>
DR_
D
DR_
AB_DQS#[0..7] <11,5>
D
AB_D[0..63] <11,5>
DR_
D
AB_DM[0..7] <11,5>
DR_
D
DR_
AB_MA[0..15] <11,5>
D
L
a
L
a
yout Note:
Place near JDDR3L
.5V
1
+
D4
D4
3
3
C
C
D1
D1
C
C
D1
D1
C
C
D1
D1
C
C
D1
D1
C
C
D1
D1
C
C
D1
D1
C
C
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
2
2
2
3
47U_0805_6.3V6M
47U_0805_6.3V6M
2
1
1 2
0 10U_0603_6.3V6M
0 10U_0603_6.3V6M
1 2
1 10U_0603_6.3V6M
1 10U_0603_6.3V6M
2
1
3 10U_0603_6.3V6M
3 10U_0603_6.3V6M
2
1
4 10U_0603_6.3V6M
4 10U_0603_6.3V6M
1 2
6 10U_0603_6.3V6M
6 10U_0603_6.3V6M
1 2
8 10U_0603_6.3V6M
8 10U_0603_6.3V6M
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
o
C
C
C
yout Note: Place these 4 Caps near
Command and Control signals of DIMMA
e
e
ciphered Date
ciphered Date
ciphered Date
e
D
D
D
+
.5V
1
+
2
1
.5V
+
12
D1
D1
R
R
1
1
K_0402_1%
K_0402_1%
+
V
REF_DQA
1
D1
D1
C
C
1U_0402_16V7K
1U_0402_16V7K
.
. 0
0
2
.1U_0402_16V4Z
.1U_0402_16V4Z
.1U_0402_16V4Z
.1U_0402_16V4Z
2
.1U_0402_16V4Z
.1U_0402_16V4Z
.1U_0402_16V4Z
.1U_0402_16V4Z
1
@
@
D2
D2
C
C
2
2 .
.
2U_0402_6.3V6M
2U_0402_6.3V6M
2
D3
D3
R
R
K_0402_1%
K_0402_1%
1
1
2
i
tle
tle
tle
i
i
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
2
1
C
ose to JDDR3L.1 Close to JDDR3L.126
l
1
D5 0
D5 0
C
C
1 2
D6 0
D6 0
C
C
1
D7 0
D7 0
C
C
1 2
D8 0
D8 0
C
C
2
V
REF_CAA
Layout Note: Place near JDDR3L.203 and 204
0
.75VS
+
D9 1
D9 1
C
C
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
D1
D1
C
C
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
C
C
C
D
D
D
D
D
D
A
-9868P
-9868P
-9868P
A
A
L
L
L
1
D3
D3
C
C
1U_0402_16V7K
1U_0402_16V7K
.
. 0
0
U_0402_6.3V6K
U_0402_6.3V6K
1
1
@
@
D4
D4
C
C
2
2 .
.
2U_0402_6.3V6M
2U_0402_6.3V6M
2
2
1
12
12
RIII-SODIMMA
RIII-SODIMMA
RIII-SODIMMA
1
.5V
+
12
D2
D2
R
R
1K_0402_1%
1K_0402_1%
12
D4
D4
R
R
1
1
K_0402_1%
K_0402_1%
0 4
0 4
0 4
1
1
o
o
1
o
.0
.0
.0
1
1
1
f
2Thursday, May 16, 2013
2Thursday, May 16, 2013
2Thursday, May 16, 2013
f
f
CyberForum.ru
5
.5V
+1
+V
REF_DQB
D
DR_
AB_D0
D
AB_D1
DR_
D
DR_AB_DM0
D
DR_
AB_D2
D
DR_AB_D3
D
DR_
D D
D
B_CKE0<5>
C C
B B
A A
+
DR_
DR_
AB_BS2<10,5>
D
DR_
B_CLK0<5>
D
DR_
B_CLK0#<5>
D
DR_
AB_BS0<10,5>
D
AB_WE#<10,5>
DR_
D DR_
AB_CAS#<10,5>
D
B_SCS1#<5>
DR_
D
1 2
D9
D9
R
3
VS
R
5
D
D D
D D
D D
D D
D D
D D
D
D D
D
D
D D
D D
D D
D D
D D
D D
D D
D D
D D
D D
D D
D
D D
D D
D D
D D
D D
D
D D
10K_0402_5%
10K_0402_5%
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AB_D8 AB_D9
DR_
AB_DQS#1
DR_ DR_
AB_DQS1
DR_AB_D10
AB_D11
DR_
DR_
AB_D16
DR_AB_D17
DR_
AB_DQS#2
DR_
AB_DQS2
DR_
AB_D18
DR_
AB_D19
AB_D24
DR_
AB_D25
DR_
AB_DM3
DR_
DR_AB_D26 DR_
AB_D27
DR_B_CKE0
AB_BS2
DR_
DR_
AB_MA12 AB_MA9
DR_
AB_MA8
DR_
AB_MA5
DR_
DR_
AB_MA3 AB_MA1
DR_
B_CLK0
DR_ DR_
B_CLK0#
DR_AB_MA10
AB_BS0
DR_
DR_
AB_WE#
DR_
AB_CAS#
AB_MA13
DR_
B_SCS1#
DR_
DR_AB_D32
AB_D33
DR_
AB_DQS#4
DR_
AB_DQS4
DR_
DR_AB_D34 DR_
AB_D35
DR_
AB_D40
DR_
AB_D41
AB_DM5
DR_
AB_D42
DR_
AB_D43
DR_
DR_AB_D48 DR_AB_D49
AB_DQS#6
DR_ DR_AB_DQS6
DR_
AB_D50 AB_D51
DR_
DR_
AB_D56
DR_
AB_D57
DR_
AB_DM7
AB_D58
DR_ DR_
AB_D59
40
40 D
D C
C
.75VS
0
+
DDR3
DDR3
H
H
J
J
1
R
EF_DQ
V
3
S
S
V
5
DQ
0
7
DQ
1
9
VS
S
11
DM
0
13
VS
S
15
DQ
2
17
DQ
3
19
VS
S
21
DQ
8
23
DQ
9
25
VS
S
27
DQ
S1#
29
DQ
S1
31
S
VS
33
10
DQ
35
11
DQ
37
S
VS
39
16
DQ
41
D
17
Q
43
V
S
S
45
D
S2#
Q
47
D
S2
Q
49
V
S
S
51
D
Q
18
53
D
Q
19
55
V
S
S
57
D
Q
24
59
D
Q
25
61
V
S
S
63
D
3
M
65
V
S
S
67
D
26
Q
69
D
Q
27
71
V
S
S
73
C
K
E0
75
V
D
D
7
7
N
C
79
B
2
A
81
V
D
D
83
A
2/BC#
1
8
5
A
9
87
V
D
D
8
9
A
8
9
1
A
5
93
V
D
D
5
9
A
3
7
9
A
1
99
V
D
D
101
C
K
0
103
C
0#
K
105
V
D
D
107
A
0/AP
1
109
B
0
A
111
V
D
D
113
W
E
#
115
C
S#
A
117
V
D
D
119
A
3
1
121
S
1
#
123
V
D
D
125
T
ST
E
127
V
S
S
129
D
Q
32
131
D
Q
33
133
V
S
S
135
D
S4#
Q
137
D
S4
Q
139
V
S
S
141
D
Q
34
143
D
35
Q
145
V
S
S
147
D
Q
40
149
D
Q
41
151
V
S
S
153
D
5
M
155
V
S
S
157
D
42
Q
159
D
43
Q
161
V
S
S
163
D
Q
48
165
D
49
Q
167
V
S
S
169
D
Q
S6#
171
D
Q
S6
173
V
S
S
175
D
Q
50
177
D
Q
51
179
V
S
S
181
D
Q
56
183
D
Q
57
185
V
S
S
187
D
7
M
189
V
S
S
191
D
Q
58
193
D
59
Q
195
V
S
S
197
S
A
0
199
V
DSPD
D
201
A
1
S
203
T
T
V
205
N
D1
G
207
SS1
O
B
LCN_DAN06-K4806-0103
LCN_DAN06-K4806-0103
@
@
V D DQ VS
D
S0#
Q
D
Q V D D V
D
Q
D
Q
V
D
M
R
SET#
E
VS DQ DQ
VS D
Q
D
Q
V
D
M
V D
Q
D
Q
V D
Q
D
Q
V
D
Q
S3#
D
Q
V D
Q
D
Q
V
C
K
V
D A A
V
D A
V
D
V
D
V
D
C
C
K
V
D B
R
A
V
D S
O
D
V
D
O
D
N
V
D
V
EF_CA
R
V
D
Q
D
Q
V
D
M
V
D
Q
D
Q
V
D
Q
D
Q
V
QS5#
D
Q
D
V
Q
D
Q
D
V
Q
D
Q
D
V
M
D
V
Q
D
Q
D
V
Q
D
Q
D
V
Q
S7#
D
Q
D
V
Q
D
Q
D
V
ENT#
V
E
D
S S
V
N
G O
SS2
B
4
.5V
+1
2
S
S
4
D
Q
4 5
S
S0
S
S
6
Q
7
Q
S
S
12 13
S
S
1
S 14 15
S 20 21
S
S
2
S
S
22 23
S
S 28 29
S
S
S3
S
S
30 31
S
S
E1
D
5
1
4
1
D 1
1
A
7
D
A
6
A
4
D
A
2
A
0
D
1
K
1#
D
1
A S#
D
#
0 T0
D T1
C
D
S
S 36 37
S
S
4
S
S
38 39
S
S 44 45
S
S
S5 S
S 46 47
S
S 52 53
S
S
6
S
S
54 55
S
S
60 61
S
S
S7 S
S 62 63
S
S
A
L
C T
T
D2
DR_AB_D4
6
D
AB_D5
DR_
8 10
D
DR_AB_DQS#0
12
D
DR_AB_DQS0
14 16
D
DR_
D
D D
D M
D D
D D
D
D D
D D
D D
D D
D
D D
D D
D D
D D
D D
D D
D D
D
+
D D
D
D D
D D
D D
D D
D D
D
D D
D D
D D
D D
M A A
0
+
4
AB_D6
DR_
AB_D7
DR_
AB_D12
DR_
AB_D13
AB_DM1
DR_ E
M_MAB_RST#
DR_
AB_D14 AB_D15
DR_
DR_
AB_D20 AB_D21
DR_
DR_
AB_DM2
DR_
AB_D22
DR_
AB_D23
DR_
AB_D28
DR_AB_D29
AB_DQS#3
DR_
AB_DQS3
DR_
AB_D30
DR_ DR_
AB_D31
DR_B_CKE1
DR_
AB_MA15
DR_
AB_MA14
AB_MA11
DR_ DR_AB_MA7
DR_
AB_MA6
DR_
AB_MA4
AB_MA2
DR_
AB_MA0
DR_
B_CLK1
DR_ DR_
B_CLK1#
DR_
AB_BS1 AB_RAS#
DR_
DR_
B_SCS0# B_ODT0
DR_
DR_
B_ODT1
V
REF_CAB
DR_
AB_D36 AB_D37
DR_
AB_DM4
DR_
DR_
AB_D38 AB_D39
DR_
AB_D44
DR_ DR_
AB_D45
AB_DQS#5
DR_ DR_
AB_DQS5
DR_
AB_D46
DR_
AB_D47
DR_
AB_D52 AB_D53
DR_
DR_
AB_DM6
AB_D54
DR_
AB_D55
DR_
AB_D60
DR_ DR_
AB_D61
DR_
AB_DQS#7
DR_
AB_DQS7
AB_D62
DR_
AB_D63
DR_
E
M_MAB_EVENT#
U_SDATA0
P
U_SCLK0
P
.75VS
18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
74 76 78 80 82 84
6
8 88 9
0 2
9 94 9
6 8
9 100 102 104 106 108 110 112 114 116 118 120 1
22 124 126 128 130 132 134 136 138 140 142 144 146 148 150
152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
206 208
DDR3 SO-DIMM B
verse Type
Re
E
M_MAB_RST# <10,5>
M
D
B_CKE1 <5>
DR_
DR_
B_CLK1 <5>
D
DR_
B_CLK1# <5>
D
AB_BS1 <10,5>
DR_
D
DR_
AB_RAS# <10,5>
D
B_SCS0# <5>
DR_
D
B_ODT0 <5>
DR_
D
B_ODT1 <5>
DR_
D
E
M_MAB_EVENT# <10,5>
M
P
U_SDATA0 <10,23,8>
A
P
U_SCLK0 <10,23,8>
A
e
curity Classification
curity Classification
curity Classification
e
e
S
S
S
I
I
I
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
H
T
T
T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ssu
ssu
ssu
ed Date
ed Date
ed Date
3
L
a
yout Note:
Place near JDDR3H
1
.5V
+
1 2
0 10U_0603_6.3V6M
0 10U_0603_6.3V6M
D3
D3
C
C
1
1 10U_0603_6.3V6M
1 10U_0603_6.3V6M
D3
D3
C
C
1
3 10U_0603_6.3V6M
3 10U_0603_6.3V6M
D3
D3
C
C
1
D3
D3
4 10U_0603_6.3V6M
4 10U_0603_6.3V6M
C
C
1 2
D3
6 10U_0603_6.3V6M
6 10U_0603_6.3V6M
D3
C
C
1 2
8 10U_0603_6.3V6M
8 10U_0603_6.3V6M
D3
D3
C
C
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
0
2
2
2
3
AB_DQS[0..7] <10,5>
DR_
D
DR_
AB_DQS#[0..7] <10,5>
D
AB_D[0..63] <10,5>
DR_
D
DR_
AB_DM[0..7] <10,5>
D
DR_
AB_MA[0..15] <10,5>
D
2
2
2
2
S
O-DIMM VREF
+
V
REF_DQB
C
ose to JDDR3H.1
l
L
a
yout Note: Place these 4 Caps near
Command and Control signals of DIMMB
1
.5V
+
12
D2
D2
5 0.1U_0402_16V4Z
5 0.1U_0402_16V4Z
C
C
12
D2
6 0.1U_0402_16V4Z
6 0.1U_0402_16V4Z
D2
C
C
12
D2
7 0.1U_0402_16V4Z
7 0.1U_0402_16V4Z
D2
C
C
12
D2
8 0.1U_0402_16V4Z
8 0.1U_0402_16V4Z
D2
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
o
C
C
C
e
e
ciphered Date
ciphered Date
ciphered Date
e
D
D
D
2
1
1
.5V
1
2
@
@
D2
D2
C
C
2
2 .
.
2U_0402_6.3V6M
2U_0402_6.3V6M
+
4
4
1 4
1 4
1 4
1
1
1
12
RD8
RD8
K_0402_1%
K_0402_1%
1
1
12
R
R
K_0402_1%
K_0402_1%
1
1
f
f
f
o
o
o
D7
D7
.0
.0
.0
1
1
1
2Thursday, May 16, 2013
2Thursday, May 16, 2013
2Thursday, May 16, 2013
1
.5V
+
12
RD6
RD6
K_0402_1%
K_0402_1%
1
1
+
V
REF_CAB
12
2
1
1
@
D2
D2
C
C
1U_0402_16V7K
1U_0402_16V7K
.
. 0
0
@
D2
D2
1
1
C
C
2
2 .
.
2U_0402_6.3V6M
2U_0402_6.3V6M
2
D5
D5
R
R
2
2
K_0402_1%
K_0402_1%
1
1
Layout Note: Place near JDDRH.203 and 204
.75VS
0
+
12
D2
D2
9 1U_0402_6.3V6K
9 1U_0402_6.3V6K
C
C
12
D3
D3
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
C
C
C
C
i
tle
tle
tle
i
i
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
C
L
L
L
2
3
3
D2
D2
C
C
1
1U_0402_16V7K
1U_0402_16V7K
.
. 0
0
C
lose to JDDR3H.126
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
D
D
RIII-SODIMMB
RIII-SODIMMB
RIII-SODIMMB
D
D
D
D
A
-9868P
-9868P
-9868P
A
A
1
CyberForum.ru
A
P
P
IE_ATX_C_GRX_P[3..0]<5>
C
P
IE_ATX_C_GRX_N[3..0]<5>
C
1 1
2 2
3 3
C
LK_PCIE_VGA<7>
C
L
K_PCIE_VGA#<7>
3.3-V tolerant
4 4
P
X
S_RST#<8>
A
P
U_PCIE_RST#<23,25,8>
A
CIE_ATX_C_GRX_P[3..0]
P
C
IE_ATX_C_GRX_N[3..0]
P
C
IE_ATX_C_GRX_P0
P
C
IE_ATX_C_GRX_N0
P
IE_ATX_C_GRX_P1
C
P
CIE_ATX_C_GRX_N1
P
CIE_ATX_C_GRX_P2
P
CIE_ATX_C_GRX_N2
P
CIE_ATX_C_GRX_P3
P
C
IE_ATX_C_GRX_N3
C
K_PCIE_VGA
L
C
K_PCIE_VGA#
L
VGA@
VGA@
R
R
V
V
2 1K_0402_5%
2 1K_0402_5%
G
U_RST#
P
2
1
12
12
VGA@
VGA@
R
R 100K_0402_5%
100K_0402_5%
+
3
B
A
U
U
1A
1A
V
V
A
38
A
PCIE_RX0P
3
7
Y
PCIE_RX0N
Y
3
5
PCIE_RX1P
W
3
6
PCIE_RX1N
W
3
8
PCIE_RX2P
V
3
7
PCIE_RX2N
V
5
3
PCIE_RX3P
U
3
6
PCIE_RX3N
U
8
3
PCIE_RX4P
T
7
3
PCIE_RX4N
T
3
5
PCIE_RX5P
R
6
3
PCIE_RX5N
R
3
8
PCIE_RX6P
P
3
7
PCIE_RX6N
P
5
3
PCIE_RX7P
N
36
PCIE_RX7N
N
8
3
NC
M
7
3
NC
M
3
5
NC
L
3
6
NC
L
8
3
NC
K
7
3
NC
K
5
3
NC
J
3
6
NC
J
38
NC
H
3
7
NC
H
5
3
NC
G
6
3
NC
G
3
8
NC
F
3
7
NC
F
5
3
NC
E
7
3
NC
CLOCK
CLOCK
A
B
35
PCIE_REFCLKP
A
36
A
PCIE_REFCLKN
A
16
H
TEST_PG
A
30
A
PERSTB
V
212
212
V
VS
VGA@
VGA@
5
13
13
V
V
U
U
P
4
Y
G
3
MC74VHC1G08DFT2G SC70 5P
MC74VHC1G08DFT2G SC70 5P
B
P
P
ART 1 0F 9
ART 1 0F 9
CI EXPRESS INTERFACE
CI EXPRESS INTERFACE P
P
SUN-PRO M2_FCBGA962VGA@
SUN-PRO M2_FCBGA962VGA@
G
P
U_RST#
B
PCIE_TX0P PCIE_TX0N
PCIE_TX1P PCIE_TX1N
PCIE_TX2P PCIE_TX2N
PCIE_TX3P PCIE_TX3N
PCIE_TX4P PCIE_TX4N
PCIE_TX5P PCIE_TX5N
PCIE_TX6P PCIE_TX6N
PCIE_TX7P PCIE_TX7N
CALIBRATION
CALIBRATION
PCIE_CALR_TX
PCIE_CALR_RX
C
P
C
IE_GTX_C_ARX_P[3..0]
P
C
IE_GTX_C_ARX_N[3..0]
.1U_0402_16V7K
3
3
Y
P
IE_GTX_ARX_P0
C
3
2
Y
P
IE_GTX_ARX_N0
C
3
3
W
P
IE_GTX_ARX_P1
C
2
3
W
P
IE_GTX_ARX_N1
C
3
3
U
P
IE_GTX_ARX_P2
C
3
2
U
P
IE_GTX_ARX_N2
C
0
3
U
P
C
IE_GTX_ARX_P3
2
9
U
P
C
IE_GTX_ARX_N3
3
3
T
3
2
T
0
3
T
9
2
T
3
3
P
2
3
P
3
0
P
9
2
P
3
3
N
NC
2
3
N
NC
3
0
N
NC
9
2
N
NC
3
3
L
NC
3
2
L
NC
3
0
L
NC
9
2
L
NC
3
3
K
NC
2
3
K
NC
3
3
J
NC
2
3
J
NC
3
0
K
NC
9
2
K
NC
3
3
H
NC
2
3
H
NC
3
0
Y
V
A_PCIE_CALRP
G
9
2
Y
V
GA_PCIE_CALRN
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
A
C Coupling Capa citor PCIeR Gen1 and Gen2 only: Reco mmended value is 100 nF 10%. PCIeR Gen3: Rec ommended value is 220 nF 10%.
1 1.69K_0402_1%VGA@
1 1.69K_0402_1%VGA@
V
V
R
R
R
R
V
V
3 1K_0402_1%VGA@
3 1K_0402_1%VGA@
P
IE_GTX_C_ARX_P[3..0] <5>
C
P
IE_GTX_C_ARX_N[3..0] <5>
C
C
C
1
1
V
V
C
C
V
V
2
2
C
C
3
3
V
V
C
C
4
4
V
V
5
5
V
V
C
C
C
C
6
6
V
V
C
C
V7
V7
8
8
V
V
C
C
1 2
1 2
1 2 1 2
1 1 2
1 2
1
1 2
1 2
P
IE_GTX_C_ARX_P0
VGA@
VGA@ VGA@
VGA@
2
VGA@
VGA@ VGA@
VGA@
VGA@
VGA@
2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
C
P
IE_GTX_C_ARX_N0
C
P
C
IE_GTX_C_ARX_P1
P
C
IE_GTX_C_ARX_N1
P
C
IE_GTX_C_ARX_P2
P
IE_GTX_C_ARX_N2
C
P
C
IE_GTX_C_ARX_P3
P
C
IE_GTX_C_ARX_N3
F
or MEMCLK 1GHz Brand
g
DDR3-2Gbit
+
.95VGS
0
+
.95VGS
0
F
or MEMCLK 900MHz Brand
s
kHynix
S
amsung
s
g
DDR3-2Gbit
M
S
S
S
S
e
curity Classification
curity Classification
curity Classification
e
e
I
I
I
s
sued Date
sued Date
sued Date
s
s
T
T
T
H
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
H
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2
2
2
12/09/27 2015/09/27
012/09/27 2015/09/27
12/09/27 2015/09/27
0
0
C
C
C
o
mpal Secret Data
mpal Secret Data
mpal Secret Data
o
o
D
D
D
e
ciphered Date
ciphered Date
ciphered Date
e
e
D
escription
H
5TQ2G63DFR-N0C
K4W2G1646E-BC1A
kHynix
MT41K128M16JT-1 07G:K
icron
amsung
D
L
DS Interface
V
V
V
1D
1D
U
U
ART 7 0F 9
ART 7 0F 9
P
P
RSVD/VARY_BL
RSVD/DIGON
LVDS CONTROL
LVDS CONTROL
TXCBP_DPB3P TXCBM_DPB3N
TX3P_DPB2P TX3M_DPB2N
TX4P_DPB1P TX4M_DPB1N
TX5P_DPB0P TX5M_DPB0N
NC#AF35
VTMDP
VTMDP L
L
C
omment PS_3[3:1] R_pu(ohm) R_pd(ohm)
1
.5V/1GHz
1.5V/1GHz
D
escription
H
5TQ2G63DFR-11C
K
4W2G1646E-BC11 1.5V/900MHz 111
D
NC#AG36
TXCAP_DPA3P TXCAM_DPA3N
TX0P_DPA2P TX0M_DPA2N
TX1P_DPA1P TX1M_DPA1N
TX2P_DPA0P TX2M_DPA0N
NC NC
SUN-PRO M2_FCBGA962VGA@
SUN-PRO M2_FCBGA962VGA@
000
111
C
omment PS_3[3:1]R_pu(ohm) R_pd(ohm)
1
.5V/900MHz
1.35V/900MHz
1.5V/900MHz
T
T
T
i
tle
tle
tle
i
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
u
u
stom
stom
ustom
Date: S heet
Date: S heet
Date: S heet
E
K
27
A
J2
7
A
35
K
A
36
L
A
8
J3
A
K
37
A
H
35
A
6
J3
A
38
G
A
37
H
A
F
35
A
36
G
A
P
34
A
34
R
A
37
W
A
35
U
A
R
37
A
39
U
A
35
P
A
R
35
A
N
36
A
37
P
A
NC
4750
000
001
NC
8450 2000
4750
C
C
C
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
P
P
P
C
CIE/LVDS
IE/LVDS
IE/LVDS
C
LA-9868P
LA-9868P
LA-9868P
E
4750
NC
4750
NC
1
1
1
.
.
0
0
.0
o
o
o
12 42Thursday, May 16, 2013
f
12 42Thursday, May 16, 2013
12 42Thursday, May 16, 2013
f
f
CyberForum.ru
A
+
3
VGS
1 1
R
R
12
12
V
V
8
1
J
2 7 3 6 4
10K_8P4R_5%
10K_8P4R_5%
+
VGS
3
2 2
+
3
3 3
4 4
10K_8P4R_5%
10K_8P4R_5%
CHECK VR IF VR Suport PSI# and DPRSLPVR PU 10K to +3VGS: PSI# :Low load current flag DPRSLPVR : Deeper sleep enable flag
GENERIC_X Stereo-sync signal. Indicates left/right frame, or top/bottom field. Can be left unconnected if not used.
VGS
Enable JTAG access
R
R
7
7
V
V
5.11K_0402_5%
5.11K_0402_5%
@
@
1 2
T
Reserved signal, for normal ASIC operation.
2
R
R
9
9
V
V
1K_0402_5%
1K_0402_5%
VGA@
VGA@
1
T
VDD MarsCRB Design
S
120ohm 1 1
0.1u 1 1 1u 1 1 10u 1 1
TAG_TRSTB J
AG_TDI
T
J
AG_TMS
T
5
J
AG_TCK
T
@
@
R
R
V
V
13
13
1 8
G
IO_16
P
2 7
G
IO_28_FDO
P
6
3
V
A_SMB_CK2
G
4 5
V
A_SMB_DA2
G
VGA@
VGA@
G
U_DPRSLPVR<39>
P
VGA@
VGA@
1 2
R
R
V
11 10K_0402_5%
11 10K_0402_5%
V
G
P
U_DOWN#<29>
G
U_VID5<39>
P
G
P
U_VID1<39>
G
U_VID2<39>
P
C
KREQ_PEG#<8>
L
VGA@
VGA@
R
R
V
V
14 10K_0402_5%
14 10K_0402_5%
2
1
G
U_VID3<39>
P
G
P
U_VID4<39>
PX_EN :
High (3.3 V) switches the regulators
off (enter BACO mode).
Low (0 V) switches the regulators
on. (Default)
E
STEN
G
M
IO_28_FDO
P
D
i
H
E
n
L
+
1
.8VGS
L
L
V
V
3
VGA@
3
VGA@
2
1
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
A
V
A_SMB_CK2
G
V
GA_SMB_DA2
G
U_DPRSLPVR
P
G
U_VID5
P
T
T
1
1
V
V
G
P
U_GPIO8
T
T
V
V
2
2
G
U_GPIO9
P
T
3TV3
V
G
U_GPIO10
P
G
P
U_VID1
G
P
10K_0402_5%@
10K_0402_5%@
R
R
8
8
V
V
2
1
G
P
U_VID2
T
T
4
4
V
V
G
P
U_GPIO21
TV5T
V5
G
P
U_GPIO22
C
KREQ_PEG#
L
G
P
U_VID3
G
U_VID4
P
T
T
V
V
9
9
P
X
J
AG_TRSTB
T
J
AG_TDI
T
J
AG_TCK
T
J
TAG_TMS
T
T
V
7
7
V
J
T
SVDD
1
17
17 V
V C
C
2
VGA@
VGA@
G
P
(
.8V@13mA TSVDD)
1
1
18
18 V
V C
C
2
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
VGA@
VGA@
AG_TDO
IO_28_FDO
+
T
1
19
19 V
V C
C
2
VGA@
VGA@
LPS
sable
able
+
T
U
U
V
V
1B
1B
PART 2 0F 9
PART 2 0F 9
MUTI GFX
MUTI GFX
29
D
A
NLK_CLK
E
G
29
C
A
NLK_VSYNC
E
G
21
AJ
APLOCKA
SW
21
AK
APLOCKB
W
S
R
8
A
C
N
U
8
A
C
N
P
8
A
B
G_CNTL0
D
8
W
A
C
N
3
R
A
C
N
1
R
A
C
N
1
U
A
G_DATA0
B
D
3
U
A
G_DATA1
B
D
W
3
A
B
G_DATA2
D
P
6
A
B
G_DATA3
D
W
5
A
B
G_DATA4
D
U
5
A
B
G_DATA5
D
R
6
A
B
G_DATA6
D
6
W
A
G_DATA7
B
D
6
U
A
B
G_DATA8
D
T
7
A
B
G_DATA9
D
7
V
A
G_DATA10
B
D
7
N
A
G_DATA11
B
D
9
V
A
G_DATA12
B
D
9
T
A
G_DATA13
B
D
10
R
A
G_DATA14
B
D
W
10
A
B
G_DATA15
D
U
10
A
B
G_DATA16
D
P
10
A
B
G_DATA17
D
11
V
A
G_DATA18
B
D
11
T
A
G_DATA19
B
D
12
R
A
G_DATA20
B
D
W
12
A
B
G_DATA21
D
U
12
A
B
G_DATA22
D
P
12
A
B
G_DATA23
D
23
J
A
BCLK
M
S
23
H
A
BDATA
M
S
K
26
A
C
L
S
26
J
A
A
D
S
G
G
ENERAL PURPOSE I/O
ENERAL PURPOSE I/O
H
20
A
P
IO_0
G
H
18
A
P
IO_1
G
16
N
A
IO_2
P
G
17
H
A
IO_5_AC_BATT
P
G
17
J
A
P
IO_6_TACH
G
K
17
A
P
IO_7_BLON
G
J
13
A
P
IO_8_ROMSO
G
H
15
A
IO_9_ROMSI
P
G
16
J
A
IO_10_ROMSCK
P
G
K
16
A
P
IO_11
G
L
16
A
P
IO_12
G
M
16
A
IO_13
P
G
14
M
A
IO_14_HPD2
P
G
13
M
A
IO_15_PWRCNTL_0
P
G
K
14
A
IO_16
_EN
SVDD
P
IO_16
G
G
30
A
P
IO_17_THERMAL_INT
G
N
14
A
P
IO_18_HPD3
G
17
M
A
IO_19_CTF
P
G
13
L
A
IO_20_PWRCNTL_1
P
G
14
J
A
P
IO_21
G
K
13
A
P
IO_22_ROMCSB
G
13
N
A
KREQB
L
C
32
G
A
IO_29
P
G
G
33
A
P
IO_30
G
19
J
A
NERICA
E
G
19
K
A
NERICB
E
G
J
20
A
E
NERICC
G
K
20
A
E
NERICD
G
J
24
A
E
NERICE_HPD4
G
26
H
A
NERICF_HPD5
E
G
H
24
A
E
NERICG_HPD6
G
30
C
A
C_1
E
C
K
24
A
P
D1
H
13
H
A
G_VREFG
B
D
L
21
A
X
_EN
P
28
D
A
STEN
E
T
M
23
A
T
AG_TRSTB
J
23
N
A
AG_TDI
T
J
K
23
A
T
AG_TCK
J
L
24
A
T
AG_TMS
J
M
24
A
T
AG_TDO
J
THERMAL
THERMAL
29
F
A
LUS
P
D
29
G
A
INUS
M
D
K
32
A
P
IO_28_FDO
G
L
31
A
S
_A
T
32
J
A
VDD
S
T
A
33
J
T
VSS
S
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DEBUG
DEBUG
DPA
DPA
DPB
DPB
DPC
DPC
DPD
DPD
S
S
MBus
MBus
I2C
I2C
DAC1
DAC1
ML
ML
P
P
S
S
B
B
ACO
ACO
DDC/
DDC/
A
A
UX
UX
D D
D
SUN-PRO M2_FCBGA962VGA@
SUN-PRO M2_FCBGA962VGA@
A
V V
C
N
C
N
C
N
D
C1CLK
D
D
C1DATA
D
C2CLK
D
D
D
C2DATA
D
CVGACLK
D CVGADATA
B
C
D
E
MLPS
24
AU
NC
23
AV
NC
A
25
T
N
C
A
24
R
N
C
A
26
U
N
C
A
25
V
N
C
27
AT
NC
A
26
R
N
C
30
AR
N
C
A
29
T
N
C
31
AV
N
C
A
30
U
NC
32
AR
N
C
A
31
T
NC
AT
33
N
C
AU
32
C
N
AU
14
NC
13
AV
NC
15
AT
NC
14
AR
NC
16
AU
NC
15
AV
NC
17
AT
NC
16
AR
NC
20
AU
NC
19
AT
NC
T
21
A
C
N
R
20
A
C
N
U
22
A
C
N
V
21
A
C
N
T
23
A
C
N
R
22
A
C
N
39
D
A
R
37
D
A
SSN
V
A
36
E
A
G
35
D
A
SSN
V
A
37
F
A
B
E
38
A
V
SSN
A
C
36
A
S
YNC
H
C
38
A
S
YNC
V
34
B
A
ET
S
R
34
D
A
DD
V
A
34
E
A
SSQ
V
33
C
A
D
D1DI
34
C
A
S1DI
S
1
3
V
C
N
1
3
U
C
N
F
33
A
C
N
F
32
A
C
N
29
A
A
C
N
21
G
A
C
N
32
C
A
C
N
C
31
A
_SVI2
D
30
A
_SVI2
D
32
A
_SVI2
34
M
A
P
S
_0
_0
S
P
D
31
A
P
_1
S
S
_1
P
G
31
A
P
_2
S
S
_2
P
33
D
A
P
_3
S
_3
S
P
M
26
A
N
26
A
27
M
A
X1P
U
A
27
L
A
X1N
U
A
19
M
A
L
19
A
N
20
A
U
X2P
A
M
20
A
U
X2N
A
30
L
A
C
N
30
M
A
C
N
L
29
A
C
N
M
29
A
C
N
21
N
A
C
N
21
M
A
C
N
K
30
A
C
N
K
29
A
C
N
J
30
A
31
J
A
B
M
ars MLPS configuration
Bits[5:1]
xx000
xx001
xx010
xx011
xx100
xx101
xx110
xx111
00xxx
01xxx
10xxx
11xxx
P
in Name
G
PIO_0
G
PIO_5_AC_BATT
GPIO_6
GPIO_15_PWRCNTL_0
GPIO_20_PWRCNTL_1
GPIO_29
GPIO_30
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_22_ROMCSB
GPIO_17_THERMAL_INT
GPIO_19_CTF
GPIO_21
GPIO_28_FDO
CLKREQB
PX_EN
PD(1%) CapPU(1%)
NC 4.75k
8.45k 2.00k
4.53k 2.00k
6.98k 4.99k
4.53k 4.99k
3.24k 5.62k
3.40k 10.0k
4.75k NC
T
ype PD/PU Description
I/O
3.3 V (VDDR3)
I/O
3.3 V (VDDR3)
I/O
3.3 V (VDDR3)
I
3.3 V (VDDR3)
O
3.3 V (VDDR3)
I/O
3.3 V (VDDR3)
O
3.3 V (VDDR3)
I/O
3.3 V (VDDR3)
I/O
3.3 V (VDDR3)
O
O PD
Primary Memory Aperture Size Requested at PCI Configuration
S
ze of the Primary
i
Memory Apertures
1
8 MB
2
ROM_CONFIG [2:0]
256 MB
64 MB
Reserved
512 MB
680nF
82nF
10nF
NC
PD-reset
PD-reset
PD-reset
PD-reset
PD-reset
PD-reset
PD-reset
PD-reset
PD-reset
1 GB
2 GB
4 GB Not supported
Power-state indicator. Permits the voltage regulator to activate power-saving features. IF VR Suport PSI# and DPRSLPVR PU 10K to +3VGS. PSI# :Low load current flag DPRSLPVR : Deeper sleep enable flag
(Optional) An input which allows the system to request a fastpower reduction by setting GPIO_5_AC_BATT to low (0 V). The resulting state transition may disturb the display momentarily. Power reductions that are less time critical should use the standard software methods in order to prevent display disturbances.
Voltage control signals for the core (VDDC and VDDCI). At reset, these signals will be inputs with weak internal pulldown resistors. The VBIOS can define all voltage-control signals to be either 3.3-V or open-drain outputs (all signals must be the same type). The output states (high/low) of these pins are programmable for each AMD PowerPlay state when they are used as voltage control signals. Note: GPIO_29 and GPIO_30 are only available on 28-nm ASICs, and are NC on earlier generation ASICs.
Serial-ROM output from ROM. General purpose I/O or open-drain output.
Design: No use external VGA ROM, so use the test point.
Serial-ROM input to ROM. General purpose I/O or open-drain output.
Serial-ROM clock to ROM. General purpose I/O or open-drain output.
BIOS-ROM chip select. Used to enable the ROM for ROM read and program operations.
Design: No use external VGA ROM, so use the test points.
Thermal monitor interrupt. An input from an external temperature sensor (ALERTb).
Critical temperature fault (CTF) (active high) will output 3.3 V if the on-die temperature sensor exceeds a critical temperature so that the motherboard can protect the ASIC from damage by removing power. The CTF setpoint is 109 by default, and is p
ogrammed during ASIC initialization. See the
r
advisory for AMD PowerPlay states for more details.
(Optional) Voltage control signal for the memory-voltage regulator. Note: This signal must be low (0 V) at reset (failure to do so will prevent booting).
Disable MLPS: PU 10K ohm to 3.3V. (Do not install for Mars) Enable MLPS: PD 10K ohm to GND. (Install for Mars)
Supports the CLKREQB feature for saving power to turn on/off the REFCLK clock on the ASIC.
On/off regulator switch in AMD PowerXpress? (switchable graphics) BACO mode. High (3.3 V) switches the regulators off (enter BACO mode). Low (0 V) switches the regulators on. (Default) PX_EN is tri-state before internal TEST_PG is asserted and PERSTb is deasserted.
Not supported
Not supported
Not supported
℃℃℃℃
C
000
001
010
011
MLPS Bit Strap Name Description Settings
ROM_CONFIG[0]
PS_0[1]
ROM_CONFIG[1]
PS_0[2]
ROM_CONFIG[2]
PS_0[3]
PS_0[4] N/A
STRAP_BIF_
PS_1[1]
GEN3_EN_A
PS_1[2] STRAP_BIF_
CLK_PM_EN
PS_1[3] N/A Reserved for internal use only. Must be 0 at reset.
PS_1[4] TX_PWRS_ENB
PS_1[5] TX_DEEMPH_EN
PS_2[1]
N/A
PS_2[2]
N/A
PS_2[3] BIOS_ROM_EN
PS_2[4] BIF_VGA_DIS
PS_2[5] N/A Reserved.
P
S
_3[1]
BOARD_CONFIG[0]
PS_3[2]
BOARD_CONFIG[1]
PS_3[3]
BOARD_CONFIG[2]
PS_0[5]
AUD_PORT_CONN_
PS_3[4]
PINSTRAP[0]
PS_3[5]
AUD_PORT_CONN_ PINSTRAP[1]
AUD_PORT_CONN_ PINSTRAP[2]
M
L
PS Strap
1
1
PS_0[5:1]
1 1
P
_1[5:1]
S
0 0
PS_2[5:1]
1 1
PS_3[5:1]
P
_0
S
P
S
_1
P
_2
S
P
_3
S
V
V
G
G
A@
A@
@
@
1
1
C
C
V
V
21
21
C
C
C
C
V20
V20
V
V
2
2
68U_0402_10V6K
68U_0402_10V6K
01U_0402_16V7K
01U_0402_16V7K
.
.
.
.
0
0
0
0
S
S
S
e
ecurity Classification
curity Classification
curity Classification
e
I
I
I
s
s
sued Date
sued Date
sued Date
s
T
T
T
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
H
H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Legacy
G
PIO[13:11]
GENLK_VSYNC
GPIO_2
GPIO_8
If BIOS_ROM_EN = 1, ROM_CONFIG[2:0] define the ROM type. If BIOS_ROM_EN = 0, ROM_CONFIG[2:0] define the primary memory-aperture size. Refer to current databooks for details.
R
eserved for internal use only. Must be 1 at reset.
Re-defined strap to indicate PCIe GEN3 capability. 1 = PCIe GEN3 supported. 0 = PCIe GEN3 not supported.
Determines whether or not the PCIe reference clock power management capability is reported in the PCI configuration space (otherwise known as CLKREQB). 0 = The CLKREQB power management capability is disabled 1 = The CLKREQB power management capability is enabled
GENLK_CLK
GPIO_0
GPIO_1
N/A
N/A
GPIO_22
GPIO_9
Transmitter (Tx) power savings enable. 0 = 50% Tx output swing. 1 = Full Tx output swing.
PCI EXPRESS transmitter, deemphasis enable. 0 = Tx deemphasis disabled. 1 = Tx deemphasis enabled.
Reserved.
Reserved.
To enable the external BIOS ROM device. 0 = Disable the external BIOS ROM device. 1 = Enable the external BIOS ROM device.
VGA disable determines whether or not the card will be recognized as the system's VGA controller. 0 = VGA controller capacity enabled. 1 = The device will not be recognized as the system’s VGA controller.
N/A
N/A
N/A
C
B
a
i
pacitorBits[5:4]
ts[3:1]
0
0 1
NC
0
0 1
NC
0 0 0
680 nF
X
X X
NC
M
apping to VRAM type please refer to page 6
@
@
R
R
V
V
8.45K_0402_1%
8.45K_0402_1%
@
@
@
@
1
1
C
C
23
23
V
V
22
22
2K_0402_1%
2K_0402_1%
2
2
01U_0402_16V7K
01U_0402_16V7K
01U_0402_16V7K
01U_0402_16V7K
.
.
.
.
0
0
0
0
2
2
2
0
0
12/09/27 2015/09/27
12/09/27 2015/09/27
12/09/27 2015/09/27
0
Board configuration related strapping (such as memory ID).
Together with PS_0[5] form the three-bit strap option to indicate the number of audio-capable display outputs. In a given ASIC there are as many endpoints as there are digital display outputs, though not all outputs are audio capable. 111 = No usable endpoints. 110 = One usable endpoint. 101 = Two usable endpoints. 100 = Three usable endpoints. 011 = Four usable endpoints. 010 = Five usable endpoints. 001 = Six usable endpoints. 000 = All endpoints are usable.
R
_
pu R_pd
8.45K 2K
8
45K
2K
.
NC
4.75K
X
X
12
12
@
@
R
R
V
V
21
21
20
20
8.45K_0402_1%
8.45K_0402_1%
8.45K_0402_1%
8.45K_0402_1%
1
VGA@
VGA@
R
R
V
V28
4.75K_0402_1%
4.75K_0402_1%
2
C
C
C
o
ompal Secret Data
mpal Secret Data
mpal Secret Data
o
12
28
4.75K_0402_1%
4.75K_0402_1%
Deciphered Date
Deciphered Date
Deciphered Date
@
@
R
R
27
27
V
V
D
@
@
R
R
VGA@
VGA@
R
R
001
1
0
0
0
1
1
0
0
0
0
0
Base on VRAM ID
111
+
1.8VGS
1
12
VGA@
VGA@
R
R
V
23
23
22
V22
V
V
8.45K_0402_1%
8.45K_0402_1%
2
12
12
V
V
68
68
2K_0402_1%
2K_0402_1%
VGA@
VGA@
R
R
V
G
A_SMB_CK2
V
V
30
30
V
A_SMB_DA2
G
T
T
T
i
i
tle
tle
tle
i
Size Document Numbe r Rev
Size Document Numbe r Rev
Size Document Numbe r Rev
C
C
C
ustom
stom
stom
u
u
Date: Sheet
Date: Sheet
Date: Sheet
+
VGS
3
2
VGA@
VGA@
Q
Q
V
1A
1A
V
DMN66D0LDW-7 2N_SOT363-6
DMN66D0LDW-7 2N_SOT363-6
DMN66D0LDW-7 2N_SOT363-6
DMN66D0LDW-7 2N_SOT363-6
C
C
C
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
M
M
M
L
L
L
A
-9868P
-9868P
-9868P
A
A
E
61
5
4
Q
Q
V
V
a
in_MSIC
in_MSIC
in_MSIC
a
a
E
_SMB_CK2 <25,29,6>
C
3
E
_SMB_DA2 <25,29,6>
VGA@
VGA@
C
1
1
1
o
o
o
f
f
13 42Thursday, May 16, 2013
13 42Thursday, May 16, 2013
13 42Thursday, May 16, 2013
f
1B
1B
.0
0
0
.
.
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