Compal LA-9866P VSKAA Schematic

A

1 1

B

C

D

E

VSKAA Schematics Document

2 2

Haswell with DDR3L + Lynx Point PCH

nVIDIA N14P-GV2 (Dual Rank) nVIDIA N14M-GL

3 3

Intel Processor (Haswell) / PCH(Lynx Point)

2013-02-03 Rev 0.3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

VSKAA

1 57Monday, March 18, 2013

E

0.3

A

B

C

D

E

VGA (DDR3)

nVIDIA N14P-GV2 & N14M-GL

1 1

page 13,14,15,16,17,18,19,20,21

PCI-Express 4X Gen3 8GT/s

eDP 1X 5.4GT/s

Intel CPU Haswell (37W)

rPGA946

Memory BUS(DDR3L)

Dual Channel

1.35V DDR3L 1333/1600 MT/s

204pin DDR3-SO-DIMM X2

BANK 0, 1, 2

page 11,12

37.5mm x 37.5mm

LVDS Conn. Colay eDP

page 23

HDMI Conn.

page 25

2 2

Sub Boards

LVDS Translator RTD2132R (Single)

page 22

HDMI Re-driver PS8201&PS8401

PCIeMini Card WLAN

PCIeMini Card WIMAX

SATA HDD

page 24

PCIe port 4

page 38

USB20 port 9

page 38

SATA port 4

page 37

PCIe Gen1 1x

1.5V 5GT/s

USB20 1x

5V 480MHz

SATA Gen3 port 4

5V 6GHz(600MB/s)

page 5,6,7,8,9,10

FDI X2

2.7GT/s

Intel PCH Lynx Point HM86

FCBGA 695Balls 20mm x 20mm

DMI X4

5GT/s

USB30 2x

5V 5GT/s

USB20 2x

5V 480MHz

USB20 1x

5V 480MHz

USB20 1x

5V 480MHz

USB20 1x

5V 480MHz

USB Right

USB20 port 0,1 USB30 port 1,2

page 41

CardReader GL834L

USB20 port 3

page 40

Touch Screen

USB20 port 8

page 23

Int. Camera

USB20 port 11

page 23

GCLK

SLG3NB304VTR page 38

LAN (Port 3)+USB (Port 2)/B RTL8106E/RTL8111G

page 39

3 3

Power/B

page 44

SATA ODD

SATA port 2

page 37

SPI ROM

RTC CKT.

page 27

8MB

page 30

SATA Gen2 port 2

5V 6GHz(600MB/s)

Debug Port

page 45

page 27,28,29,30,31,32,33,34,35,36

LPC BUS

3.3V 33 MHz

KB9012

page 44

HD Audio

3.3V 24MHz

HDA Codec

ALC259 (w/o S&M) ALC269 (w/ S&M)

page 42

CRT

page 26

DC/DC Interface CKT.

page 46

Power Circuit DC/DC

4 4

page 47,48,49,50,51,52,53,54,55

Touch Pad

Int.KBD

page 45page 45

G-Sensor

page 37

SPK Conn

page 43

JLINE & JEXMIC

page 43

Power On/Off CKT.

page 45

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

VSKAA

2 57Monday, March 18, 2013

E

0.3

5

4

3

2

1

DESIGN CURRENT 0.1A

B+

D D

Ipeak=8.13A, Imax=5.69A, Iocp min=8.7

DESIGN CURRENT 5A

+3VL

+5VALW

SUSP#

TPS22966

RT8243AZQW

Ipeak=5A, Imax=3.5A, Iocp min=6.2A

SUSP#

TPS22966

WOL_EN#

P-CHANNEL

AO-3413

LCD_ENVDD

APL3512

DGPU_PWR_EN

C C

P-CHANNEL

AO-3413

PJ6

DESIGN CURRENT 4A

DESIGN CURRENT 5A

DESIGN CURRENT 330mA

DESIGN CURRENT 4A

DESIGN CURRENT 1.5A

DESIGN CURRENT 60mA

DESIGN CURRENT 2A

+5VS

+3VALW

+3V_LAN

+3VS

+LCD_VDD

+3VS_DGPU

+3V_WLAN

VR_ON

TPS51631

DESIGN CURRENT 55A

+CPU_CORE

SUSP#

B B

TPS51212

SUSP#

TPS51212

Ipeak=20.53A, Imax=14.37A, Iocp min=23.91A

VGA_PWROK

P-CHANNEL

AO-3416

VGA_PWROK

N-CHANNEL

FDS6676AS

DESIGN CURRENT 60mA

DESIGN CURRENT 2A

DESIGN CURRENT 8.6A

+1.05VS_VCCP

+1.05VS_DGPU

+1.5VS

+VRAM_1.5VS

SYSON

RT8207M

Ipeak=15A, Imax=10.5A, Iocp min=18A

0.675VR_EN

A A

DESIGN CURRENT 10A

DESIGN CURRENT 1.5A

+1.35V

+0.675VS

DGPU_PWR_EN

NCP81172

5

Ipeak=33.8A, Imax=23.4A, Iocp min=40A

4

DESIGN CURRENT 20.5A

+VGA_CORE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Power Tree

VSKAA

1

3 57Monday, March 18, 2013

0.3

A

Voltage Rails

power plane

1 1

State

( O MEANS ON X MEANS OFF )

+RTCVCC

B+

+5VL

+3VL

+5VALW

+3VALW

+VSB

B

Platform

+1.35V

+5VS

+3VS

+1.8VS

+1.5VS

+CPU_CORE

+VGA_CORE

+VRAM_1.5VS

+3VS_DGPU

+1.05VS_DGPU

Chief River

BTO Option Table

Function

C

SKU CPU PCH

Ivy Bridge i3 (CPUI3@) Ivy Bridge i5 (CPUI5@)

SKU MIC

HM77C1(HM77@) HM77C1_R1(HM77R1@) HM77C1_R3(HM77R3@)

LAN

D

E

VGA

nVIDIA N13P-GL (N13PGL@)

description

explain

BTO

S0

S1

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

O

X

O

X

O

X

O

X X

X

X X

OO

X

Function

description

X

explain

BTO

Function

PCH SM Bus Address

Power

+3VS

Device

DDR SO-DIMM 0

DDR SO-DIMM 1

HEX

Address

1010 0000 bA0 H

1010 0100 bA4 H

description

explain

BTO

Function

3 3

description

explain

BTO

EC SM Bus1 Address

Device Address Address

+3VL

EC SM Bus2 Address

HEX HEX

0001 0110 bSmart Battery

16 H

12 HSmart Charger 0001 0010 b+3VL

PowerPower

+3VS

HEXDevice AddressPower

Device

96 H

NVIDIA GPU 1001 1010 b

9E H

STATE

Full ON

1001 0110 bPCH

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

G3 LOW LOWLOW

SIGNAL

SLP_S3# SLP_S4# SLP_S5#

HIGH HIGHHIGH

LOW

LOW LOW

OW

HIGH HIGHHIGH

HIGH

LOW LOWL

HIGH

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

VSKAA

4 57Monday, March 18, 2013

E

0.3

A

B

C

D

E

+VCCIO_OUT

RC44 62_0402_5%RC44 62_0402_5%

RC45 10K_0402_5%RC45 10K_0402_5%

12

H_PROCHOT#

H_PWRGOOD

H_DRAMRST#

@

1 2

CC34 180P_0402_50V8J

by ESD requestion and place near CPU

DDR3 Compensation CAD Note:

Haswell rPGA EDS

1 1

2 2

Please place near JCPU

If no use eDP, please stuff them.

@

ESD@

@

@ESD@

1 2

12

DRAMPWROK

CC621000P_0402_50V7K

H_PWRGOOD

CC63100P_0402_50V8J

CC701000P_0402_50V7K

CC671000P_0402_50V7K

CC661000P_0402_50V7K

CC2100P_0402_50V8J

H_PECI

H_PM_SYNC

CPU_PLTRST#

H_THERMTRIP#

H_PROCHOT#<44,47>

135 MHz

35 MHz

1

100 MHz

H_PECI<44>

1 2

RC60 56_0402_5%RC60 56_0402_5%

H_THERMTRIP#<33>

H_PM_SYNC<28> H_PWRGOOD<33> DRAMPWROK<28> CPU_PLTRST#<33>

CLK_CPU_EDP#<29> CLK_CPU_EDP<29> CLK_CPU_SSC_EDP#<29> CLK_CPU_SSC_EDP<29> CLK_CPU_DMI#<29> CLK_CPU_DMI<29>

T2 PAD

TP@

H_CATERR#

H_PECI

H_PROCHOT#_R

H_PM_SYNC H_PWRGOOD DRAMPWROK CPU_PLTRST#

CLK_CPU_SSC_EDP# CLK_CPU_SSC_EDP

JCPUB

AP32

SKTOCC

AN32

CATERR

AR27

PECI

AK31

FC_AK31

AM30

PROCHOT

AM35

THERMTRIP

AT28

PM_SYNC

AL34

PWRGOOD

AC10

SM_DRAMPWROK

AT26

PLTRSTIN

G28

DPLL_REF_CLKN

H28

DPLL_REF_CLKP

F27

SSC_DPLL_REF_CLKN

E27

SSC_DPLL_REF_CLKP

D26

BCLKN

E26

BCLKP

Conn@

Haswell rPGA EDS

MISC

THERMAL

PWR

TEL_HASWELL_HASWELL

IN

DDR3

CLOCK

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 SM_DRAMRST

JTAG

BPM_N_0 BPM_N_1 BPM_N_2 BPM_N_3 BPM_N_4 BPM_N_5 BPM_N_6 BPM_N_7

2 OF 9

PRDY PREQ

TCK TMS

TRST

TDO DBR

AP3 AR3 AP2 AN3

AR29 AT29 AM34 AN33 AM33 AM31

TDI

AL33 AP33

AR30 AN31 AN29 AP31 AP30 AN28 AP29 AP28

Trace width=12~15 mil, Spacing=20 mils Max trace length= 500 mil

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 H_DRAMRST#

XDP_PRDY# XDP_PREQ# XDP_TCLK XDP_TMS XDP_TRST# XDP_TDI XDP_TDO XDP_DBRESET#

1 2

RC56 100_0402_1%RC56 100_0402_1%

1 2

RC59 75_0402_1%RC59 75_0402_1%

1 2

RC61 100_0402_1%RC61 100_0402_1%

Close to CPU side

H_DRAMRST# <11>

T42PAD TP@T42PAD TP@ T43PAD TP@T43PAD TP@

T19PAD TP@T19PAD TP@

T18PAD TP@T18PAD TP@

T35PAD TP@T35PAD TP@

XDP_DBRESET#

1 2

CC3 100P_0402_50V8J

XDP Connector reserve test point

@ESD@

PU/PD for JTAG signals

+1.05VS_VCCP

SM_DRAMPWROK for nonsupport Deep S3

+1.35V

12

RC16

1.8K_0402_1%

DRAMPWROK

12

RC14

3.3K_0402_1%

3 3

XDP_TDO

XDP_TCLK

XDP_TRST#

1 2

RC49 51_0402_1%RC49 51_0402_1%

1 2

RC42 51_0402_1%RC42 51_0402_1%

1 2

RC41 51_0402_1%RC41 51_0402_1%

ESD@

CC68100P_0402_50V8J

ESD@

CC69100P_0402_50V8J

ESD@

CC83100P_0402_50V8J

+1.05VS_VCCP

Buffered Rest to CPU

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

FAN Control Circuit

+3VS

12

R2

R2 10K_0402_5%

10K_0402_5%

+5VS

FAN_SPEED1<44>

1A

1 2

D

R1

0_0603_5%

+FAN1

1

C4

0.01U_0402_25V7K

@

2

Title

Size Document Number Rev

Date: Sheet of

Custom

FANPWM<44>

+FAN1

12

D1

BAS16_SOT23-3

Compal Electronics, Inc.

Haswell_JTAG/XDP/FAN

VSKAA

1

C5

2

10U_0603_6.3V6M

E

JFAN

Conn@JFAN

Conn@

6

G6

5

G5

4

3

2

1

ACES_50273-0040N-001

5 57Monday, March 18, 2013

0.3

A

1 1

2 2

3 3

DMI_PTX_CRX_N0<28> DMI_PTX_CRX_N1<28> DMI_PTX_CRX_N2<28> DMI_PTX_CRX_N3<28>

DMI_PTX_CRX_P0<28> DMI_PTX_CRX_P1<28> DMI_PTX_CRX_P2<28> DMI_PTX_CRX_P3<28>

DMI_CTX_PRX_N0<28> DMI_CTX_PRX_N1<28> DMI_CTX_PRX_N2<28> DMI_CTX_PRX_N3<28>

DMI_CTX_PRX_P0<28> DMI_CTX_PRX_P1<28> DMI_CTX_PRX_P2<28> DMI_CTX_PRX_P3<28>

FDI_CSYNC<28> FDI_INT<28>

B

Haswell rPGA EDS

JCPUA

PEG_RCOMP

D21 C21 B21 A21

D20 C20 B20 A20

D18 C17 B17 A17

D17 C18 B18 A18

H29

J29

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

FDI_CSYNC DISP_INT

IN

DMI FDI

TEL_HASWELL_HASWELLConn@

PEG_RXN_0 PEG_RXN_1 PEG_RXN_2 PEG_RXN_3 PEG_RXN_4 PEG_RXN_5 PEG_RXN_6

PEG

PEG_RXN_7 PEG_RXN_8

PEG_RXN_9 PEG_RXN_10 PEG_RXN_11 PEG_RXN_12 PEG_RXN_13 PEG_RXN_14 PEG_RXN_15

PEG_RXP_0

PEG_RXP_1

PEG_RXP_2

PEG_RXP_3

PEG_RXP_4

PEG_RXP_5

PEG_RXP_6

PEG_RXP_7

PEG_RXP_8

PEG_RXP_9

PEG_RXP_10 PEG_RXP_11 PEG_RXP_12 PEG_RXP_13 PEG_RXP_14 PEG_RXP_15

PEG_TXN_0

PEG_TXN_1

PEG_TXN_2

PEG_TXN_3

PEG_TXN_4

PEG_TXN_5

PEG_TXN_6

PEG_TXN_7

PEG_TXN_8

PEG_TXN_9

PEG_TXN_10 PEG_TXN_11 PEG_TXN_12 PEG_TXN_13 PEG_TXN_14 PEG_TXN_15

PEG_TXP_0

PEG_TXP_1

PEG_TXP_2

PEG_TXP_3

PEG_TXP_4

PEG_TXP_5

PEG_TXP_6

PEG_TXP_7

PEG_TXP_8

PEG_TXP_9

PEG_TXP_10 PEG_TXP_11 PEG_TXP_12 PEG_TXP_13 PEG_TXP_14 PEG_TXP_15

1 OF 9

C

E23

PEG_COMP

M29

PCIE_GTX_C_CRX_N0

K28

PCIE_GTX_C_CRX_N1

M31

PCIE_GTX_C_CRX_N2

L30

PCIE_GTX_C_CRX_N3

M33 L32 M35 L34 E29 D28 E31 D30 E35 D34 E33 E32 L29

PCIE_GTX_C_CRX_P0

L28

PCIE_GTX_C_CRX_P1

L31

PCIE_GTX_C_CRX_P2

K30

PCIE_GTX_C_CRX_P3

L33 K32 L35 K34 F29 E28 F31 E30 F35 E34 F33 D32 H35

PCIE_CTX_GRX_N0

H34

PCIE_CTX_GRX_N1

J33

PCIE_CTX_GRX_N2

H32

PCIE_CTX_GRX_N3

J31 G30 C33 B32 B31 A30 B29 A28 B27 A26 B25 A24 J35

PCIE_CTX_GRX_P0

G34

PCIE_CTX_GRX_P1

H33

PCIE_CTX_GRX_P2

G32

PCIE_CTX_GRX_P3

H31 H30 B33 A32 C31 B30 C29 B28 C27 B26 C25 B24

RC1

24.9_0402_1%

+VCOMP_OUT

CAD Note:

12

Trace width=12 mils ,Spacing=15mil Max length= 400 mils.

1 2

CC8 0.22U_0402_16V7KCC8 0.22U_0402_16V7K

1 2

CC11 0.22U_0402_16V7KCC11 0.22U_0402_16V7K

1 2

CC16 0.22U_0402_16V7KCC16 0.22U_0402_16V7K

1 2

CC20 0.22U_0402_16V7KCC20 0.22U_0402_16V7K

1 2

CC10 0.22U_0402_16V7KCC10 0.22U_0402_16V7K

1 2

CC5 0.22U_0402_16V7KCC5 0.22U_0402_16V7K

1 2

CC6 0.22U_0402_16V7KCC6 0.22U_0402_16V7K

1 2

CC7 0.22U_0402_16V7KCC7 0.22U_0402_16V7K

D

PCIE_GTX_C_CRX_N[0..3] <13>

PCIE_GTX_C_CRX_P[0..3] <13>

PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_P3

E

PCIE_CTX_C_GRX_N[0..3] <13>

PCIE_CTX_C_GRX_P[0..3] <13>

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Haswell_DMI/PEG/FDI

VSKAA

6 57Monday, March 18, 2013

E

0.3

A

B

C

D

E

DDR_A_D[0..63]<11>

JCPUC

1 1

2 2

3 3

+V_SM_VREF +VREF_DQA_M3 +VREF_DQB_M3

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AR15 AT14 AM14 AN14 AT15 AR14 AN15 AM15

AM9

AN9

AM8

AN8 AR9 AT9 AR8 AT8

AK9

AK6

AJ10

AK10

AK7 AF4 AF5 AF1 AF2 AG4 AG5 AG1 AG2

D12

D11

AM3

AJ9

AJ6

AJ7

J1 J2

J5 H5 H2 H1

J4 H4 F2 F1 D2 D3 D1 F3 C3 B3 B5 E6 A5 D6 D5 E5 B6 A6

E12

B11 A11 E11

B12 A12

F16 F13

JCPUC

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 SM_VREF SA_DIMM_VREFDQ SB_DIMM_VREFDQ

TEL_HASWELL_HASWELLConn@

IN

Haswell rPGA EDS

SA_CK_N_0 SA_CK_P_0

SA_CKE_0 SA_CK_N_1 SA_CK_P_1

SA_CKE_1 SA_CK_N_2 SA_CK_P_2

SA_CKE_2 SA_CK_N_3 SA_CK_P_3

SA_CKE_3

SA_CS_N_0 SA_CS_N_1 SA_CS_N_2 SA_CS_N_3

SA_ODT_0

SA_ODT_1

SA_ODT_2

SA_ODT_3

SA_BS_0 SA_BS_1 SA_BS_2

SA_RAS

SA_WE

SA_CAS

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_MA_15

SA_DQS_N_0 SA_DQS_N_1 SA_DQS_N_2 SA_DQS_N_3 SA_DQS_N_4 SA_DQS_N_5 SA_DQS_N_6 SA_DQS_N_7 SA_DQS_P_0 SA_DQS_P_1 SA_DQS_P_2 SA_DQS_P_3 SA_DQS_P_4 SA_DQS_P_5 SA_DQS_P_6 SA_DQS_P_7

3 OF 9

RSVD

VSS

AC7 U4 V4 AD9 U3 V3 AC9 U2 V2 AD8 U1 V1 AC8

M7 L9 M9 M10 M8 L7 L8 L10 V5 U5 AD1

V10 U6 U7 U8

V8 AC6 V9 U9 AC5 AC4 AD6 AC3 AD5 AC2 V6 AC1 AD4 V7 AD3 AD2

AP15 AP8 AJ8 AF3 J3 E2 C5 C11 AP14 AP9 AK8 AG3 H3 E3 C6 C12

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8

DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDRA_CLK0# <11> DDRA_CLK0 <11> DDRA_CKE0 <11> DDRA_CLK1# <11> DDRA_CLK1 <11> DDRA_CKE1 <11>

DDRA_SCS0# <11> DDRA_SCS1# <11>

DDRA_ODT0 <11> DDRA_ODT1 <11>

DDR_A_BS0 <11> DDR_A_BS1 <11> DDR_A_BS2 <11>

DDR_A_RAS# <11> DDR_A_WE# <11> DDR_A_CAS# <11>

DDR_A_MA[0..15] <11>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_B_D[0..63]<12>

Haswell rPGA EDS

RSVD

SB_CKN0

SB_CK0

SB_CKE_0

SB_CKN1

SB_CK1

SB_CKE_1

SB_CKN2

SB_CK2

SB_CKE_2

SB_CKN3

SB_CK3

SB_CKE_3

SB_CS_N_0 SB_CS_N_1 SB_CS_N_2 SB_CS_N_3

SB_ODT_0 SB_ODT_1 SB_ODT_2 SB_ODT_3

SB_BS_0 SB_BS_1 SB_BS_2

SB_RAS

SB_WE

SB_CAS

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_MA_15

SB_DQS_N_0 SB_DQS_N_1 SB_DQS_N_2 SB_DQS_N_3 SB_DQS_N_4 SB_DQS_N_5 SB_DQS_N_6 SB_DQS_N_7 SB_DQS_P_0 SB_DQS_P_1 SB_DQS_P_2 SB_DQS_P_3 SB_DQS_P_4 SB_DQS_P_5 SB_DQS_P_6 SB_DQS_P_7

4 OF 9

VSS

AG8 Y4 AA4 AF10 Y3 AA3 AG10 Y2 AA2 AG9 Y1 AA1 AF9

P4 R2 P3 P1

R4 R3 R1 P2 R7 P8 AA9

R10 R6 P6 P7

R8 Y5 Y10 AA5 Y7 AA6 Y6 AA7 Y8 AA10 R9 Y9 AF7 P9 AA8 AG7

AP18 AP11 AP5 AJ3 L3 H9 C8 C14 AP17 AP12 AP6 AK3 M3 H8 C9 C15

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8

DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0

DDR_B_DQS1

DDR_B_DQS2

DDR_B_DQS3

DDR_B_DQS4

DDR_B_DQS5

DDR_B_DQS6

DDR_B_DQS7

DDRB_CLK0# <12> DDRB_CLK0 <12> DDRB_CKE0 <12> DDRB_CLK1# <12> DDRB_CLK1 <12> DDRB_CKE1 <12>

DDRB_SCS0# <12> DDRB_SCS1# <12>

DDRB_ODT0 <12> DDRB_ODT1 <12>

DDR_B_BS0 <12> DDR_B_BS1 <12> DDR_B_BS2 <12>

DDR_B_RAS# <12> DDR_B_WE# <12> DDR_B_CAS# <12>

DDR_B_MA[0..15] <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AR18 AT18 AM17 AM18 AR17 AT17 AN17 AN18 AT12 AR12 AN12 AM11 AT11 AR11 AM12 AN11

AR5 AR6 AM5 AM6 AT5 AT6 AN5 AN6

AK4

AM1 AN1 AK2 AK1

G10

D15

D14

AJ4

AJ1 AJ2

J10

E15

A15 B15 E14

A14 B14

L2

M2

L4

M4

L1

M1

L5 M5 G7

J8 G8 G9

J7

J9

A8

B8

A9

B9 D8

E8 D9

E9

JCPUD

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

TEL_HASWELL_HASWELLConn@

IN

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Haswell_DDR3

VSKAA

7 57Monday, March 18, 2013

E

0.3

A

1 1

B

C

D

E

COMPENSATION PU FOR eDP

+VCOMP_OUT

12

RC2

24.9_0402_1%

Haswell rPGA EDS

H_HDMI_TX2-<25> H_HDMI_TX2+<25> H_HDMI_TX1-<25> H_HDMI_TX1+<25> H_HDMI_TX0-<25> H_HDMI_TX0+<25> H_HDMI_TXC-<25> H_HDMI_TXC+<25>

2 2

3 3

T28 U28 T30 U30 U29 V29 U31 V31

T34 U34 U35 V35 U32 T32 U33 V33

P29 R29 N28 P28 P31 R31 N30 P30

DDIB_TXBN_0 DDIB_TXBP_0 DDIB_TXBN_1 DDIB_TXBP_1 DDIB_TXBN_2 DDIB_TXBP_2 DDIB_TXBN_3 DDIB_TXBP_3

DDIC_TXCN_0 DDIC_TXCP_0 DDIC_TXCN_1 DDIC_TXCP_1 DDIC_TXCN_2 DDIC_TXCP_2 DDIC_TXCN_3 DDIC_TXCP_3

DDID_TXDN_0 DDID_TXDP_0 DDID_TXDN_1 DDID_TXDP_1 DDID_TXDN_2 DDID_TXDP_2 DDID_TXDN_3 DDID_TXDP_3

IN

JCPUH

eDP

EDP_RCOMP

EDP_DISP_UT IL

TEL_HASWELL_HASWELLConn@

EDP_AUXN EDP_AUXP

EDP_HPD

EDP_TXN_0 EDP_TXP_0 EDP_TXN_1 EDP_TXP_1

FDI_TXN_0

FDI_TXP_0

FDI_TXN_1

FDI_TXP_1

DDI

8 OF 9

M27 N27 P27 E24 R27

P35 R35 N34 P34 P33 R33 N32 P32

H_EDP_HPD# EDP_RCOMP

T12PAD TP@T12PAD TP@

H_EDP_AUXN <22> H_EDP_AUXP <22>

H_EDP_TXN0 <22> H_EDP_TXP0 <22> H_EDP_TXN1 <22> H_EDP_TXP1 <22> FDI_CTX_PRX_N0 <28> FDI_CTX_PRX_P0 <28> FDI_CTX_PRX_N1 <28> FDI_CTX_PRX_P1 <28>

24.9_0402_1%

EDP_RCOMP

CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils.

+VCCIO_OUT

12

RC5

RC5 10K_0402_5%

10K_0402_5%

H_EDP_HPD#

1

OUT

H_EDP_HPD<22,23>

2

IN

GND

QC1

DTC124EKAT146_SC59-3

3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Haswell_DDI/eDP

VSKAA

8 57Monday, March 18, 2013

E

0.3

A

B

C

D

E

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCC VCC VCC VCC

VCC VCC

AA26 AA28 AA34 AA30 AA32 AB26 AB29 AB25 AB27 AB28 AB30 AB31 AB33 AB34 AB32 AC26 AB35 AC28 AD25 AC30 AD28 AC32 AD31 AC34 AD34 AD26 AD27 AD29 AD30 AD32 AD33 AD35 AE26 AE32 AE28 AE30 AG28 AG34 AE34 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AF35 AG26 AH26 AH29 AG30 AG32 AH32 AH35 AH25 AH27 AH28 AH30 AH31 AH33 AH34 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 G25 H25 J25 K25 L25 M25 N25 P25 R25 T25

U25 U26 V25 V26

W26 W27

+CPU_CORE

Haswell rPGA EDS

JCPUE

1 1

2 2

VCC_SENSE

VCCSENSE<54>

VSSSENSE<10,54,9>

+CPU_CORE

RC93

RC93 100_0402_1%

100_0402_1%

1 2

RC95

RC95 100_0402_1%

100_0402_1%

1 2

Reserve short pad on power side

VCCSENSE

VSSSENSE

lose to CPU

C

VSSSENSE <10,54,9>

+1.35V

CC51

10U_0603_6.3V6M

CC64

22U_0805_6.3V6M

VDDQ DECOUPLING

10U_0603_6.3V6M

1

CC52

2

22U_0805_6.3V6M

1

CC73

2

10U_0603_6.3V6M

1

CC55

CC54

2

10U_0603_6.3V6M

22U_0805_6.3V6M

1

CC74

CC75

2

22U_0805_6.3V6M

1

CC56

2

10U_0603_6.3V6M

1

CC76

2

22U_0805_6.3V6M

10U_0603_6.3V6M

1

CC57

CC58

2

10U_0603_6.3V6M

22U_0805_6.3V6M

1

CC77

CC78

2

22U_0805_6.3V6M

10U_0603_6.3V6M

1

CC59

CC60

2

10U_0603_6.3V6M

22U_0805_6.3V6M

1

CC80

CC79

2

22U_0805_6.3V6M

10U_0603_6.3V6M

1

CC61

2

22U_0805_6.3V6M

1

CC81

CC82

2

22U_0805_6.3V6M

12

CC53

47U_0805_6.3V6M

1

2

+CPU_CORE

+1.35V

Reserve 0.1u to avoid noise

+VCCIO_OUT +VCCIO_OUT

0.1U_0402_10V7K

1 2

CC49

@

12

RC89

RC89 75_0402_5%

75_0402_5%

VR_SVID_ALRT#<54> VR_SVID_CLK<54> VR_SVID_DAT<54>

Pull high resistor on VR side

3 3

4 4

0.1U_0402_10V7K

1 2

CC50

@

1 2

RC96 43_0402_1%RC96 43_0402_1%

1 2

RC88 0_0402_5%Rshort@RC88 0_0402_5%Rshort@

1 2

RC92 0_0402_5%Rshort@RC92 0_0402_5%Rshort@

12

RC91

RC91 130_0402_5%

130_0402_5%

H_CPU_SVIDALRT#

H_CPU_SVIDCLK H_CPU_SVIDDAT

+VCCIO_OUT+1.05VS_VCCP

@

1 2

RC10 0_0603_5%

RESISTOR STUFFING OPTIONS ARE PROVIDED FOR TESTING PURPOSES

+VCCIO_OUT

+VCOMP_OUT

+CPU_CORE

VCCSENSE

T13 PAD

TP@

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

T57 PADTP@T57 PADTP@

T14 PADTP@T14 PADTP@ T15 PADTP@T15 PADTP@ T16 PADTP@T16 PADTP@ T17 PADTP@T17 PADTP@

K27

V27

AB11

AB2 AB5 AB8

AE11

AE2 AE5 AE8

AH11

K11 N11

W11

N26 K26

AL27

AK27

AL35

E17

AN35

A23

W32

AL16

AL13

AM28 AM29

AL28

AP35

H27 AP34 AT35 AR35 AR32

AL26

AT34

AL22 AT33 AM21 AM25 AM22 AM20 AM24

AL19 AM23 AT32

Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35

L27 T27

N8

T11

T2 T5 T8

W2 W5 W8

F22

J27

JCPUE

RSVD RSVD RSVD RSVD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VDDQ

VDDQ VDDQ

4

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

RSVD VCC RSVD RSVD

VCC_SENSE RSVD VCCIO_OUT RSVD VCOMP_OUT RSVD RSVD RSVD RSVD

VIDALERT VIDSCLK VIDSOUT

VSS PWR_DEBUG VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

IN

.2A

TEL_HASWELL_HASWELLConn@

VCC 55A

5 OF 9

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Haswell_POWER

VSKAA

9 57Monday, March 18, 2013

E

0.3

A

B

C

D

E

Haswell rPGA EDS

A10 A13 A16 A19 A22 A25 A27 A29

A3

AA11 AA25 AA27 AA31 AA29

AB10 AA33 AA35

AC25 AC27

AC11 AD11 AC29 AC31 AC33 AC35

AD7

AE1 AE10 AE25 AE29

AE3 AE27 AE35

AE4

AE6

AE7

AE9 AF11

AF6

AF8 AG11 AG25 AE31 AG31 AE33

AG6

AH1 AH10

AH2 AG27 AG29

AH3 AG33 AG35

AH4

AH5

AH6

AH7

AH8

AH9

AJ11

AK11 AK25 AK26 AK28 AK29 AK30 AK32

A31 A33

A4 A7

AB1

AB3

AB4 AB6 AB7 AB9

AJ5

E19

1 1

2 2

3 3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

JCPUF

NTEL_HASWELL_HASWELLConn@

I

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

6 OF 9

AK34 AK5 AL1 AL10 AL11 AL12 AL14 AL15 AL17 AL18 AL2 AL20 AL21 AL23 E22 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AM10 AM13 AM16 AM19 E25 AM32 AM4 AM7 AN10 AN13 AN16 AN19 AN2 AN21 AN24 AN27 AN30 AN34 AN4 AN7 AP1 AP10 AP13 AP16 AP19 AP4 AP7 W25 AR10 AR13 AR16 AR19 AR2 AR22 AR25 AR28 AR31 AR34 AR4 AR7 AT10 AT13 AT16 AT19 AT21 AT24 AT27 AT3 AT30 AT4 AT7 B10 B13 B16 B19 B2 B22

Haswell rPGA EDS

B34

VSS

B4

VSS

B7

VSS

C1

VSS

C10

VSS

C13

VSS

C16

VSS

C19

VSS

C2

VSS

C22

VSS

C24

VSS

C26

VSS

C28

VSS

C30

VSS

C32

VSS

C34

VSS

C4

VSS

C7

VSS

D10

VSS

D13

VSS

D16

VSS

D19

VSS

D22

VSS

D25

VSS

D27

VSS

D29

VSS

D31

VSS

D33

VSS

D35

VSS

D4

VSS

D7

VSS

E1

VSS

E10

VSS

E13

VSS

E16

VSS

E4

VSS

E7

VSS

F10

VSS

F11

VSS

F12

VSS

F14

VSS

F15

VSS

F17

VSS

F18

VSS

F20

VSS

F21

VSS

F23

VSS

F24

VSS

F26

VSS

F28

VSS

F30

VSS

F32

VSS

F34

VSS

F4

VSS

F6

VSS

F7

VSS

F8

VSS

F9

VSS

G1

VSS

G11

VSS

G2

VSS

G27

VSS

G29

VSS

G3

VSS

G31

VSS

G33

VSS

G35

VSS

G4

VSS

G5

VSS

H10

VSS

H26

VSS

H6

VSS

H7

VSS

J11

VSS

J26

VSS

J28

VSS

J30

VSS

J32

VSS

J34

VSS

J6

VSS

K1

VSS

NTEL_HASWELL_HASWELL

I

Conn@

JCPUG

VSS_SENSE

RSVD

7 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

K10 K2 K29 K3 K31 K33 K35 K4 K5 K7 K8 K9 L11 L26 L6 M11 M26 M28 M30 M32 M34 M6 N1 N10 N2 N29 N3 N31 N33 N35 N4 N5 N6 N7 N9 P11 P26 P5 R11 R26 R28 R30 R32 R34 R5 T1 T10 T29 T3 T31 T33 T35 T4 T6 T7 T9 U11 U27 V11 V28 V30 V32 V34 W1 W10 W3 W35 W4 W6 W7 W9 Y11 H11 AL24 F19 T26 AK35 AK33

T20 PADTP@T20 PADTP@ T21 PADTP@T21 PADTP@

T22 PADTP@T22 PADTP@ T23 PADTP@T23 PADTP@

T24 PADTP@T24 PADTP@ T25 PADTP@T25 PADTP@

+CPU_CORE

T26 PADTP@T26 PADTP@ T27 PADTP@T27 PADTP@

T28 PADTP@T28 PADTP@

T29 PADTP@T29 PADTP@ T30 PADTP@T30 PADTP@

T41 PADTP@T41 PADTP@ T44 PADTP@T44 PADTP@

T40 PADTP@T40 PADTP@

VSSSENSE <54,9>

CPU_TESTLO_G26

CPU_TESTLO

CFG2

CFG4 CFG5 CFG6

1 2

RC100 49.9_0402_1%RC100 49.9_0402_1%

1 2

RC101 49.9_0402_1%RC101 49.9_0402_1%

1 2

RC102 49.9_0402_1%RC102 49.9_0402_1%

Haswell rPGA EDS

AT1

RSVD_TP

AT2

RSVD_TP

AD10

RSVD

A34

RSVD_TP

A35

RSVD_TP

W29

RSVD_TP

W28

RSVD_TP

G26

TESTLO_G26

W33

RSVD

AL30

RSVD

AL29

RSVD

F25

VCC

C35

RSVD_TP

B35

RSVD_TP

AL25

RSVD_TP

W30

RSVD_TP

W31

RSVD_TP

W34

TESTLO

AT20

CFG_0

AR20

CFG_1

AP20

CFG_2

AP22

CFG_3

AT22

CFG_4

AN22

CFG_5

AT25

CFG_6

AN23

CFG_7

AR24

CFG_8

AT23

CFG_9

AN20

CFG_10

AP24

CFG_11

AP26

CFG_12

AN25

CFG_13

AN26

CFG_14

AP25

CFG_15

NTEL_HASWELL_HASWELLConn@

I

CPU_TESTLO_G26

CPU_TESTLO

CFG_RCOMP

JCPUI

RSVD_TP RSVD_TP RSVD_TP RSVD_TP

CFG_RCOMP

CFG_16 CFG_18 CFG_17 CFG_19

RSVD

FC_G6

RSVD RSVD RSVD RSVD RSVD

RSVD

RSVD RSVD

RSVD

RSVD_TP

RSVD_TP RSVD_TP

RSVD RSVD

VSS VSS

9 OF 9

C23 B23 D24 D23

AT31

CFG_RCOMP

AR21 AR23 AP21 AP23

AR33 G6 AM27 AM26 F5 AM2 K6

E18

U10 P10

B1

NC

A2 AR1

E21 E20

AP27 AR26

AL31 AL32

CFG Straps for Processor

(CFG[17:0] internal pull high 5~15K to VCCIO)

T31PAD TP@T31PAD TP@ T32PAD TP@T32PAD TP@ T33PAD TP@T33PAD TP@ T34PAD TP@T34PAD TP@

T53PAD TP@T53PAD TP@ T54PAD TP@T54PAD TP@

PEG Static Lane Reversal - CFG2 is for the 16x

T55PAD TP@T55PAD TP@ T56PAD TP@T56PAD TP@

T39PAD TP@T39PAD TP@

T36PAD TP@T36PAD TP@

T37PAD TP@T37PAD TP@ T38PAD TP@T38PAD TP@

CFG2

Embedded Display Port Presence Strap

CFG4

CFG2

1: Normal Operation; Lane # definition

*

atches socket pin map definition

m

0:Lane Reversed

CFG4

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port

*

evice is connected to the Embedded

d Display Port

CFG6

CFG5

1K_0402_1%

RC83

12

RC79

RC79 1K_0402_1%

1K_0402_1%

@

12

RC82

RC82 1K_0402_1%

1K_0402_1%

12

RC84

RC84 1K_0402_1%

1K_0402_1%

@

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2

*

disabled

CFG[6:5]

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

D

10: x8, x8 - Device 1 function 1 enabled; function 2 disabled

0

1: Reserved - (Device 1 function 1 disabled;

function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Haswell_GND/RSVD/CFG

VSKAA

10 57Monday, March 18, 2013

E

0.3

A

+VREF_DQA

1

CD1

0.1U_0402_10V7K

2

Close to JDDR3L.1

1 1

DDRA_CKE0<7>

DDR_A_BS2<7>

2 2

DDRA_CLK0<7>

DDRA_CLK0#<7>

DDR_A_BS0<7>

DDR_A_WE#<7>

DDR_A_CAS#<7>

DDRA_SCS1#<7>

3 3

+3VS

4 4

CD26

DDR_A_D0 DDR_A_D1

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

1

2

0.1U_0402_10V7K

SPD setting (SA0, SA1) PU/PD by Channel A/B

->Channel A 00

->Channel B 01

A

+0.675VS

+1.35V

3 5 7

9 11 13 15 17 19 21 23 25 27

33 35

39 41

45 47 49 51 53 55 57 59

63

67 69

73 75 77 79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

JDDR3L

VREF_DQ1VSS1 VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS1131VSS12 DQ10 DQ11 VSS1337VSS14 DQ16 DQ17 VSS1543VSS16 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS2365VSS24 DQ26 DQ27 VSS2571VSS26

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

G1

LCN_DAN06-K4406-0103_204P

C

onn@

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA SCL

VTT2

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

+1.35V

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

SM_DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

DDR_A_D36 DDR_A_D37

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

+0.675VS

B

DDR3 SO-DIMM A Reverse Type H=4.0mm

DDRA_CKE1 <7>

DDRA_CLK1 <7> DDRA_CLK1# <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDRA_SCS0# <7> DDRA_ODT0 <7>

DDRA_ODT1 <7>

1

CD16 0.1U_0402_10V7KCD16 0.1U_0402_10V7K

2

close to JDDR3L.126

PM_SMBDATA <12,30,38,45> PM_SMBCLK <12,30,38,45>

C

DDR_A_DQS[0..7] <7>

DDR_A_DQS#[0..7] <7>

DDR_A_D[0..63] <7>

DDR_A_MA[0..15] <7>

+1.35V

@

RC78

1 2

RC78

1K_0402_5%

Compal Secret Data

SM_DRAMRST#<12>

+V_SM_VREF_CNT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

SM_DRAMRST#

Layout Note: Place near JDDR3L

+1.35V

CD8 10U_0603_6.3V6MCD8 10U_0603_6.3V6M

CD9 10U_0603_6.3V6MCD9 10U_0603_6.3V6M

CD10 10U_0603_6.3V6MCD10 10U_0603_6.3V6M

CD11 10U_0603_6.3V6MCD11 10U_0603_6.3V6M

CD13 10U_0603_6.3V6MCD13 10U_0603_6.3V6M

CD14 10U_0603_6.3V6MCD14 10U_0603_6.3V6M

2012/04/19 2015/04/19

1 2

12

Deciphered Date

D

RC80

RC80 1K_0402_5%

1K_0402_5%

H_DRAMRST# <5>

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

+1.35V

1 2

CD17 1U_0402_6.3V6KCD17 1U_0402_6.3V6K

1 2

CD18 1U_0402_6.3V6KCD18 1U_0402_6.3V6K

1 2

CD19 1U_0402_6.3V6KCD19 1U_0402_6.3V6K

1 2

CD20 1U_0402_6.3V6KCD20 1U_0402_6.3V6K

D

E

SM_DRAMRST#

Layout Note: Place near JDDR3L.203 and 204

+0.675VS

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM0

VSKAA

1 2

CD2 100P_0402_50V8J

@ESD@

12

CD24 1U_0402_6.3V6KCD24 1U_0402_6.3V6K

12

CD21 1U_0402_6.3V6KCD21 1U_0402_6.3V6K

11 57Monday, March 18, 2013

E

0.3

A

+VREF_DQB

0.1U_0402_10V7K

1 1

Close to JDDR3H.1

DDRB_CKE0<7>

DDR_B_BS2<7>

2 2

DDRB_CLK0<7> DDRB_CLK0#<7>

DDR_B_BS0<7>

DDR_B_WE#<7> DDR_B_CAS#<7>

DDRB_SCS1#<7>

3 3

+3VS

1

4 4

2

0.1U_0402_10V7K

CD27

RD15

RD15 10K_0402_5%

10K_0402_5%

CD49

1

2

1 2

DDR_B_D0 DDR_B_D1

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_D26 DDR_B_D27

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

DDR_B_MA10

DDR_B_MA13

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_D58 DDR_B_D59

+0.675VS

+1.35V

JDDR3H

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

VREF_CA

VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

G1

LCN_DAN06-K4806-0103_204P

LCN_DAN06-K4806-0103_204P C

C

onn@

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA SCL

VTT2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

80

A14

82 84

A11

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102 104 106 108

BA1

110 112 114

S0#

116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

G2

B

+1.35V

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_D22 DDR_B_D23

DDR_B_D28 DDR_B_D29

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D30 DDR_B_D31

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

DDR_B_D36 DDR_B_D37

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

+0.675VS

DDR3 SO-DIMM B Reverse Type H=9.0mm

SM_DRAMRST# <11>

DDRB_CKE1 <7>

DDRB_CLK1 <7> DDRB_CLK1# <7>

DDR_B_BS1 <7> DDR_B_RAS# <7>

DDRB_SCS0# <7> DDRB_ODT0 <7>

DDRB_ODT1 <7>

1

CD47 0.1U_0402_10V7KCD47 0.1U_0402_10V7K

2

Close to JDDR3H.126

PM_SMBDATA <11,30,38,45> PM_SMBCLK <11,30,38,45>

+VREF_DQA_M3

@ CC71

@

+V_SM_VREF_CNT

C

+1.35V

12

1 2

RC187 2_0402_1%RC187 2_0402_1%

12

CC71

0.022U_0402_25V7K

12

RC8

24.9_0402_1%@

12

Layout Note: Place near JDDR3H

+1.35V

CD31 47U_0805_6.3V6MCD31 47U_0805_6.3V6M

CD41 10U_0603_6.3V6MCD41 10U_0603_6.3V6M

CD36 10U_0603_6.3V6MCD36 10U_0603_6.3V6M

CD37 10U_0603_6.3V6MCD37 10U_0603_6.3V6M

CD39 10U_0603_6.3V6MCD39 10U_0603_6.3V6M

CD40 10U_0603_6.3V6MCD40 10U_0603_6.3V6M

CD58 10U_0603_6.3V6MCD58 10U_0603_6.3V6M

DDR_B_DQS#[0..7] <7>

DDR_B_DQS[0..7] <7>

DDR_B_D[0..63] <7>

DDR_B_MA[0..15] <7>

All VREF traces should have 20 mil trace width

+VREF_DQA +1.35V

RC121

RC121 1K_0402_1%

1K_0402_1%

RC110

RC110 1K_0402_1%

1K_0402_1%

1 2

SE00000PL00

1 2

+VREF_DQB_M3

D

+VREF_DQB +1.35V

12

RC122

RC122 1K_0402_1%

1K_0402_1%

1 2

RC188 2_0402_1%RC188 2_0402_1%

12

CC72

@ CC72

@

0.022U_0402_25V7K

12

RC9

24.9_0402_1%@

Layout Note: Place these 4 Caps near Command and Control signals of DIMMB

+1.35V

12

RC111

RC111 1K_0402_1%

1K_0402_1%

12

CD29 1U_0402_6.3V6KCD29 1U_0402_6.3V6K

12

CD30 1U_0402_6.3V6KCD30 1U_0402_6.3V6K

12

CD32 1U_0402_6.3V6KCD32 1U_0402_6.3V6K

12

CD33 1U_0402_6.3V6KCD33 1U_0402_6.3V6K

+V_SM_VREF

1 2

RC189 2_0402_1%RC189 2_0402_1%

12

CC65

@ CC65

@

0.022U_0402_25V7K

12

RC3

24.9_0402_1%@

Layout Note: Place near JDDR3H.203 and 204

+0.675VS

CD45 1U_0402_6.3V6KCD45 1U_0402_6.3V6K

CD42 1U_0402_6.3V6KCD42 1U_0402_6.3V6K

12

RC120

RC120 1K_0402_1%

1K_0402_1%

12

RC109

RC109 1K_0402_1%

1K_0402_1%

12

E

+V_SM_VREF_CNT

SPD setting (SA0, SA1) PU/PD by Channel A/B

->Channel A 00

->Channel B 01

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM1

VSKAA

12 57Monday, March 18, 2013

E

0.3

of

A

PCIE_GTX_C_CRX_P[0..3]<6>

PCIE_GTX_C_CRX_N[0..3]<6>

PCIE_CTX_C_GRX_P[0..3]<6>

PCIE_CTX_C_GRX_N[0..3]<6>

1 1

PCIE_GTX_C_CRX_P0 PCIE_GTX_C_CRX_N0 PCIE_GTX_C_CRX_P1 PCIE_GTX_C_CRX_N1 PCIE_GTX_C_CRX_P2 PCIE_GTX_C_CRX_N2 PCIE_GTX_C_CRX_P3 PCIE_GTX_C_CRX_N3

2 2

3 3

CLK_REQ_VGA#<29>

4 4

PCIE_GTX_C_CRX_P[0..3]

PCIE_GTX_C_CRX_N[0..3]

PCIE_CTX_C_GRX_P[0..3]

PCIE_CTX_C_GRX_N[0..3]

1 2

CV1 0.22U_0402_16V7KOPT@CV1 0.22U_0402_16V7KOPT@

1 2

CV2 0.22U_0402_16V7KOPT@CV2 0.22U_0402_16V7KOPT@

1 2

CV3 0.22U_0402_16V7KOPT@CV3 0.22U_0402_16V7KOPT@

1 2

CV4 0.22U_0402_16V7KOPT@CV4 0.22U_0402_16V7KOPT@

1 2

CV5 0.22U_0402_16V7KOPT@CV5 0.22U_0402_16V7KOPT@

1 2

CV6 0.22U_0402_16V7KOPT@CV6 0.22U_0402_16V7KOPT@

1 2

CV7 0.22U_0402_16V7KOPT@CV7 0.22U_0402_16V7KOPT@

1 2

CV8 0.22U_0402_16V7KOPT@CV8 0.22U_0402_16V7KOPT@

CLK_PCIE_VGA<29>

CLK_PCIE_VGA#<29>

PLTRST_VGA#<31>

61

QV2A

2N7002DW-T/R7_SOT363-6

OPT@

2

1 2

RV4 200_0402_1%

@

+3VS_DGPU

PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3

PCIE_GTX_CRX_P0 PCIE_GTX_CRX_N0 PCIE_GTX_CRX_P1 PCIE_GTX_CRX_N1 PCIE_GTX_CRX_P2 PCIE_GTX_CRX_N2 PCIE_GTX_CRX_P3 PCIE_GTX_CRX_N3

CLK_PCIE_VGA CLK_PCIE_VGA# CLK_REQ_GPU#

PEX_TSTCLK_OUT PEX_TSTCLK_OUT#

RV5

2.49K_0402_1%

OPT@

1 2

B

UV1A

AG6

PEX_RX0

AG7

PEX_RX0_N

AF7

PEX_RX1

AE7

PEX_RX1_N

AE9

PEX_RX2

AF9

PEX_RX2_N

AG9

PEX_RX3

AG10

PEX_RX3_N

AF10

PEX_RX4

AE10

PEX_RX4_N

AE12

PEX_RX5

AF12

PEX_RX5_N

AG12

PEX_RX6

AG13

PEX_RX6_N

AF13

PEX_RX7

AE13

PEX_RX7_N

AE15

NC

AF15

NC

AG15

NC

AG16

NC

AF16

NC

AE16

NC

AE18

NC

AF18

NC

AG18

NC

AG19

NC

AF19

NC

AE19

NC

AE21

NC

AF21

NC

AG21

NC

AG22

NC

AC9

PEX_TX0

AB9

PEX_TX0_N

AB10

PEX_TX1

AC10

PEX_TX1_N

AD11

PEX_TX2

AC11

PEX_TX2_N

AC12

PEX_TX3

AB12

PEX_TX3_N

AB13

PEX_TX4

AC13

PEX_TX4_N

AD14

PEX_TX5

AC14

PEX_TX5_N

AC15

PEX_TX6

AB15

PEX_TX6_N

AB16

PEX_TX7

AC16

PEX_TX7_N

AD17

NC

AC17

NC

AC18

NC

AB18

NC

AB19

NC

AC19

NC

AD20

NC

AC20

NC

AC21

NC

AB21

NC

AD23

NC

AE23

NC

AF24

NC

AE24

NC

AG24

NC

AG25

NC

AE8

PEX_REFCLK

AD8

PEX_REFCLK_N

AC6

PEX_CLKREQ_N

AF22

PEX_TSTCLK_OUT

AE22

PEX_TSTCLK_OUT_N

AC7

PEX_RST_N

AF25

PEX_TERMP

N14P-GV2-S-A2_FCBGA595

N14PGV2@

1

CV17

CV17 18P_0402_50V8J

18P_0402_50V8J

NOGCLK@

2

Part 1 of 6

PCI EXPRESS

YV1

1

DACsI2C GPIO

120mA

52mA

71mA

41mA

CLK

NOGCLK@

27MHZ_16PF

GND

2

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_HSYNC DACA_VSYNC

DACA_VDD DACA_VREF DACA_RSET

I2CA_SCL

I2CA_SDA

I2CB_SCL

I2CB_SDA

I2CC_SCL

I2CC_SDA

I2CS_SCL

I2CS_SDA

CORE_PLLVDD

SP_PLLVDD

VID_PLLVDD

XTAL_IN

XTAL_OUT

XTAL_SSIN

XTAL_OUTBUFF

3

GND

4

18P_0402_50V8J

NC

XTAL_OUTXTALIN

NOGCLK@

C6 B2 D6 C7 F9 A3 A4 B6 A6 F8 C5 E7 D7 B4 B3 C3 D5 D4 C2 F7 E6 C4

AB6

AG3 AF4 AF3

AE3 AE4

W5 AE2 AF2

B7 A7

C9 C8

A9 B9

D9 D8

L6 M6

N6

C11 B10

A10 C10

CV18

FB_CLAMP_MON

FB_CLAMP_REQ#

OVERT#_VGA GPU_EVENT

DGPU_VID GPS_DOWN# PSI

VGA_CRT_CLK VGA_CRT_DATA

HDCP_SCL HDCP_SDA

VGA_EDID_CLK VGA_EDID_DATA

SMB_CLK_GPU SMB_DATA_GPU

+PLLVDD

+GPU_PLLVDD

XTALIN XTAL_OUT

XTAL_SSIN XTAL_OUTBUFF

1

2

C

DV1

+3VS_DGPU

2

G

QV8

13

D

S

2N7002KW_SOT323-3

DGPU_VID <55>

GPS_DOWN# <44>

PSI <55>

1

OPT@

2

CV42, CV43 under GPU close to ball : AE8,AD7

VGA_X1<38>

10_0402_5%

10P_0402_50V8J

N14PGV2@

CV9

0.1U_0402_10V7K

RV7

CV113

RB751V40_SC76-2

OPT@

1

CV10

2

0.1U_0402_10V7K

OPT@

12

@EMI@RV7

@EMI@

1

@EMI@CV113

@EMI@

2

for EMI

12

CLK_REQ_GC6# <44>

LV1

BLM18PG181SN1D_2P

1 2

1

CV11

CV12

2

4.7U_0603_6.3V6K

OPT@

1 2

RV8 0_0402_5%

GCLK@

FB_CLAMP <14,17,44>

+1.05VS_DGPU

OPT@

22U_0805_6.3V6M

XTALIN

D

For GC6

1

CV13

2

10U_0603_6.3V6M

JTAG_TRST<15> TESTMODE<15>

Internal Thermal Sensor

SMB_CLK_GPU

SMB_DATA_GPU

under GPU close to AD8

OPT@

QV1A

2N7002DW-T/R7_SOT363-6

+PLLVDD

1

2

GPS_DOWN# GPU_EVENT XTAL_OUTBUFF XTAL_SSIN

VGA_EDID_CLK VGA_EDID_DATA SMB_CLK_GPU SMB_DATA_GPU

VGA_CRT_CLK VGA_CRT_DATA HDCP_SDA HDCP_SCL

FB_CLAMP FB_CLAMP_REQ# FB_CLAMP_MON OVERT#_VGA

CLK_REQ_GC6#

CLK_REQ_GPU#

+3VS_DGPU

5

OPT@

QV1B

4

2

2N7002DW-T/R7_SOT363-6

61

1

CV14

2

OPT@ CV14

OPT@

0.1U_0402_10V7K

E

RPV1

1 8 2 7 3 6 4 5

10K_8P4R_5%

OPT@

RPV2

1 8 2 7 3 6 4 5

2.2K_8P4R_5%

OPT@

RPV3

1 8 2 7 3 6 4 5

2.2K_8P4R_5%

OPT@

RPV12

1 8 2 7 3 6 4 5

10K_8P4R_5%

OPT@

RPV13

1 8 2 7 3 6 4 5

10K_8P4R_5%

OPT@

3

LV2

1 2

FBMA-L11-160808300LMA25T_2P

CV15

OPT@ CV15

OPT@

22U_0805_6.3V6M

EC_SMB_CK2 <24,30,37,44>

+1.05VS_DGPU

OPT@LV2

OPT@

+3VS_DGPU

+3VS

EC_SMB_DA2 <24,30,37,44>

1

CV16

2

OPT@ CV16

OPT@

10U_0603_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/09/28 2013/09/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

VGA_N14x PEG & DAC

13 57Monday, March 18, 2013

E

13 57Monday, March 18, 2013

0.3

of

A

VRAM Interface

+FB_PLLAVDD

CV20

22U_0805_6.3V6M

1

OPT@CV20

OPT@

2

MDA[15..0]

MDA[31..16]

MDA[47..32]

MDA[63..48]

Close to H22

CV21

0.1U_0402_10V7K

2

OPT@CV21

OPT@

1

CV22

1

OPT@CV22

OPT@

2

Close to P22

CV114

0.1U_0402_10V7K

1

OPT@CV114

OPT@

2

0.1U_0402_10V7K

UV1B

Part 2 of 6

FBA_D00 FBA_D01 FBA_D02 FBA_D03 FBA_D04 FBA_D05 FBA_D06 FBA_D07 FBA_D08 FBA_D09 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FB_PLLAVDD_1 FB_PLLAVDD_2

FB_VREF_PROBE

FB_DLLAVDD

FB_CLAMP

FBA_DEBUG0 FBA_DEBUG1

Part 2 of 6

62mA

2mA

6

35mA

MEMORY

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

FBA_DQM0

FBA_DQM1

FBA_DQM2

FBA_DQM3

FBA_DQM4

FBA_DQM5

FBA_DQM6

FBA_DQM7

FBA_DQS_RN0 FBA_DQS_RN1

INTERFACE A

FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FBA_CLK0_N

FBA_CLK1_N

FBA_WCK01

FBA_WCK01_N

FBA_WCK23

FBA_WCK23_N

FBA_WCK45

FBA_WCK45_N

FBA_WCK67

FBA_WCK67_N

FBA_CLK0

FBA_CLK1

C27 C26 E24 F24 D27 D26 F25 F26 F23 G22 G23 G24 F27 G25 G27 G26 M24 M23 K24 K23 M27 M26 M25 K26 K22 J23 J25 J24 K27 K25 J27 J26

D19 D14 C17 C22 P24 W24 AA25 U25

F19 C14 A16 A22 P25 W22 AB27 T27

E19 C15 B16 B22 R25 W23 AB26 T26

D24 D25

N22 M22

D18 C18 D17 D16 T24 U24 V24 V25

CMDA0 CMDA1 CMDA2 CMDA3 CMDA4 CMDA5 CMDA6 CMDA7 CMDA8 CMDA9 CMDA10 CMDA11 CMDA12 CMDA13 CMDA14 CMDA15 CMDA16 CMDA17 CMDA18 CMDA19 CMDA20 CMDA21 CMDA22 CMDA23 CMDA24 CMDA25 CMDA26 CMDA27 CMDA28 CMDA29 CMDA30

DQSA#0 DQSA#1 DQSA#2 DQSA#3 DQSA#4 DQSA#5 DQSA#6 DQSA#7

TP@

D20 D21

D15

C13

D13

C16

C19

C23

C20 C21 R22 R24

R23 N25 N26 N23 N24

U22

AA24

AA23 AD27 AB25 AD26 AC25 AA27 AA26

W26

R26

N27 R27

W27 W25

D23

H22

E18 F18 E16 F17

F20 E21 E15

F15 F13

B13 E13

B15

A13 A15 B18 A18 A19

B24

A25 A24 A21 B21

T22

V23 V22 T23

Y24

Y22

Y25

T25

V26 V27

F16 P22

F22 J22

F3

N14P-GV2-S-A2_FCBGA595

N14PGV2@

MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63

+FB_PLLAVDD

FB_CLAMP<13,17,44>

TV1 PAD

TV1 PAD TV2 PAD

TV2 PAD

DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7

DQSA0 DQSA1 DQSA2 DQSA3 DQSA4 DQSA5 DQSA6 DQSA7

CMDA[30..0] <18,19,20,21>

CLKA0 <18,20> CLKA0# <18,20>

CLKA1 <19,21> CLKA1# <19,21>

DQMA[3..0] <18,20>

DQMA[7..4] <19,21>

DQSA#[3..0] <18,20>

DQSA#[7..4] <19,21>

DQSA[3..0] <18,20>

DQSA[7..4] <19,21>

MDA[15..0]<18,20>

MDA[31..16]<18,20>

MDA[47..32]<19,21>

MDA[63..48]<19,21>

1 1

30ohms (ESR=0.01)

+1.05VS_DGPU

LV3

OPT@LV3

OPT@

1 2

FBMA-L11-160808300LMA25T_2P

Place close to BGA

Near GPU Close to F16

Place close to the first T point

+VRAM_1.5VS

109876

12345

+VRAM_1.5VS

109876

12345

+VRAM_1.5VS

DDR3

CMDA16 CMDA19 CMDA3 CMDA0 CMDA20

RV10 100_0402_5%

RV12 100_0402_5%

CMDA12 CMDA14 CMDA15 CMDA7

RPV4

RPV4 100_1206_10P8R_5%

100_1206_10P8R_5%

OPT@

CMDA11 CMDA4 CMDA5 CMDA6

CMDA22 CMDA9 CMDA21 CMDA24

RPV6

RPV6 100_1206_10P8R_5%

100_1206_10P8R_5%

OPT@

CMDA23 CMDA13 CMDA8 CMDA10

RPV8

18

CMDA26

27

CMDA25

36

CMDA27

45

CMDA28

100_0804_8P4R_5%

OPT@

12

OPT@

12

OPT@

Command Bit Default Pull-down

ODTx

CKEx

RST

CS* No Termination

1 2

RV36 10K_0402_5%OPT@RV36 10K_0402_5%OPT@

1 2

RV37 10K_0402_5%OPT@RV37 10K_0402_5%OPT@

1 2

RV38 10K_0402_5%OPT@RV38 10K_0402_5%OPT@

1 2

RV40 10K_0402_5%OPT@RV40 10K_0402_5%OPT@

1 2

RV15 10K_0402_5%OPT@RV15 10K_0402_5%OPT@

CMDA29

CMDA30

10k

109876

12345

109876

12345

1 8

CMDA28

2 7

CMDA27

3 6

CMDA25

4 5

CMDA26

RV11 100_0402_5%

RV13 100_0402_5%

RPV5

RPV5 100_1206_10P8R_5%

100_1206_10P8R_5%

OPT@

RPV7

RPV7 100_1206_10P8R_5%

100_1206_10P8R_5%

OPT@

RPV9

100_0804_8P4R_5%

OPT@

12

OPT@

12

OPT@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2012/09/28 2013/09/28

Compal Secret Data

Deciphered Date

Custom

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

N14x VRAM Interface

14 57Monday, March 18, 2013

0.3

5

UV1C

AC3

IFPA_TXC

AC4

IFPA_TXC_N

Y4

IFPA_TXD0

Y3

IFPA_TXD0_N

AA3

IFPA_TXD1

AA2

IFPA_TXD1_N

AB1

IFPA_TXD2

AA1

IFPA_TXD2_N

AA4

D D

C C

B B

A A

IFPA_TXD3

AA5

IFPA_TXD3_N

AB5

IFPB_TXC

AB4

IFPB_TXC_N

AB3

IFPB_TXD4

AB2

IFPB_TXD4_N

AD3

IFPB_TXD5

AD2

IFPB_TXD5_N

AE1

IFPB_TXD6

AD1

IFPB_TXD6_N

AD4

IFPB_TXD7

AD5

IFPB_TXD7_N

T2

IFPC_L0

T3

IFPC_L0_N

T1

IFPC_L1

R1

IFPC_L1_N

R2

IFPC_L2

R3

IFPC_L2_N

N2

IFPC_L3

N3

IFPC_L3_N

V3

IFPD_L0

V4

IFPD_L0_N

U3

IFPD_L1

U4

IFPD_L1_N

T4

IFPD_L2

T5

IFPD_L2_N

R4

IFPD_L3

R5

IFPD_L3_N

N1

NC

M1

NC

M2

NC

M3

NC

K2

NC

K3

NC

K1

NC

J1

NC

M4

NC

M5

NC

L3

NC

L4

NC

K4

NC

K5

NC

J4

NC

J5

NC

N4

IFPC_AUX_I2CW_SCL

N5

IFPC_AUX_I2CW_SDA_N

P3

IFPD_AUX_I2CX_SCL

P4

IFPD_AUX_I2CX_SDA_N

J2

IFPE_AUX_I2CY_SCL

J3

IFPE_AUX_I2CY_SDA_N

H3

IFPF_AUX_I2CZ_SCL

H4

IFPF_AUX_I2CZ_SDA_N

N14P-GV2-S-A2_FCBGA595

N14PGV2@

Part 3 of 6

NC

GENERAL

MULTI_STRAP_REF0_GND

LVDS/TMDS

VDD_SENSE

GND_SENSE

TEST

JTAG_TRST_N

SERIAL

BUFRST_N

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

THERMDP

THERMDN

TESTMODE

JTAG_TCK

JTAG_TDI JTAG_TDO JTAG_TMS

ROM_CS_N

ROM_SI

ROM_SO

ROM_SCLK

F11

NC

AD10

NC

AD7

NC

B19

NC

V5

NC

V6

NC

G1

NC

G2

NC

G3

NC

G4

NC

G5

NC

G6

NC

G7

NC

V1

NC

V2

NC

W1

NC

W2

NC

W3

NC

W4

NC

D11

D10

NC

E9

NC

E10

NC

F10

NC

D1 D2 E4 E3 D3 C1

NC

F6 F4

NC

F5

NC

F12

E12

F2

F1

AD9 AE5 AE6 AF6 AD6 AG4

D12 B12 A12 C12

4

OPT@

1 2

RV16 10K_0402_5%

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

MULTI_STRAP_REF0_GND

VGA_VCC_SENSE

trace width: 16mils differential voltage sensing.

VGA_VSS_SENSE

JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS

ROM_SI ROM_SO ROM_SCLK

differential signal routing.

PAD

PAD PAD

PAD PAD TP@

PAD TP@ PAD

PAD

N14PGV2@

1 2

RV17 40.2K_0402_1%

+VGA_CORE

RV26

RV26 100_0402_1%

100_0402_1%

OPT@

1 2

OPT@

12

RV35

100_0402_1%

TESTMODE <13>

TP@

TV3

TP@

TV4

TV4 TV5

TV5 TV6

TP@TV6

TP@

JTAG_TRST <13>

VGA_VCC_SENSE <55>

VGA_VSS_SENSE <55>

N14P-GV2

3

ogical

Physical Strapping pin

ROM_SO

ROM_SCLK

ROM_SI

STRAP0

STRAP1

TRAP2

S

STRAP3

STRAP4

ower Rail

P

+3VS_DGPU

+

3VS_DGPU

+3VS_DGPU

+3VS_DGPU 3

+3VS_DGPU

+3VS_DGPU SOR0_EXPOSEDSOR2_EXPOSED SOR1_EXPOSED

3VS_DGPU DP_PLL_VDD33V

+

L Strapping Bit3

FB[1]

PCI_DEVID[4]

AMCFG[3] RAMCFG[2]

USER[3]

3GIO_PADCFG[3]

PCI_DEVID[3]

SOR3_EXPOSED

RESERVED

SKU Device ID biit5 to bit0

N14P-GV2

N14M-GL

MULTI LEVEL STRAPS

12

@

N14PGV2@

RV18

45.3K_0402_1%

STRAP0 STRAP1 STRAP3 STRAP2

45.3K_0402_1%

12

@

RV27

4.99K_0402_1%

N14PGV2@

12

0x1140 000000

+3VS_DGPU

12

@

10K_0402_1%

12

N14PGV2@

45.3K_0402_1%

10K_0402_1%

RV20

RV29

15K_0402_1%

RV19

RV28

N14PGV2@

FB Memory gDDR3

K4W2G1646E-BC11

icron

amsung

900MHz

GHz

1

900MHz

1GHz

900MHz

K4W2G1646E-BC1A

H5TQ2G63DFR-11C

H5TQ2G63DFR-N0C

MT41K128M16JT-107G

K4W4G1646B-HC11S

MT41K256M16HA-107G

1 2 8 M

x 1 6

2 5 6 M

x 1 6

Samsung

Hynix

M

Micron

12

@

RV21

4.99K_0402_1%

12

RV30

4.99K_0402_1%

0100100x1292

12

@

RV22

12

N14PGV2@

RV31

ROM_SIGPU

PD 45.3K

PD 34.8K

PD 30K

PD 20K

PD 10K

2

10K_0402_1%

STRAP4

45.3K_0402_1%

Logical Strapping Bit2

B[0]

F

SUB_VENDOR

PCIE_SPEED_CHANGE_GEN3

Resistor Values

RV31

10K_0402_1%

N14MGL@

For X76 (N14P-GV2)For X76 (N14M-GL)

N14M-GL

Logical Strapping Bit1

S

MB_ALT_ADDR

PCI_DEVID[5]

RAMCFG[1]R

PCIE_MAX_SPEED

Pull-up to +3VS _D

ROM_SI ROM_SO ROM_SCLK

GPU

1000

1001

1010

1011

1100

1101

1110

1111

N14MGL@

12

@

RV23

4.99K_0402_1%

RV32

10K_0402_1%

5K

10K

1

20K

25K

30K

35K

45K

5K

FB Memory gDDR3

Samsung

1 2 8 M

Hynix

x 1 6

Micron

Samsung K4W4G1646B-HC11

2 5 6 M

Hynix

x 1 6

M

icron

1GHz

900MHz

9

00MHz

9

00MHz

K4W2G1646E-BC11900MHz

K4W2G1646E-BC1A

H5TQ2G63DFR-11C900MHz

5TQ2G63DFR-N0C

H

MT41K128M16JT-107G

H5TC4G63AFR-11C

MT41K256M16HA-107G

1

Logical S

trapping Bit0

VGA_DEVICE

PEX_PLLEN_TERM

RAMCFG[0]

USER[0]USER[1]USER[2]

GIO_PADCFG[0]3GIO_PADCFG[1]3GIO_PADCFG[2]

PCI_DEVID[0]PCI_DEVID[1]PCI_DEVID[2]

Pull-down to Gnd

0000

0001

0010

0011

0100

0101

0110

0111

+3VS_DGPU

12

N14PGV2@

RV24

4.99K_0402_1%

12

N14MGL@

RV33

10K_0402_1%

12

RV25

4.99K_0402_1%

12

RV34

10K_0402_1%

STRAP[3:0]GPU

0101

0110

0001

1011

0100

1

101

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/09/28 2013/09/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

VGA_N14x LVDS&TMDS

15 57Monday, March 18, 2013

1

15 57Monday, March 18, 2013

0.3

of

5

+VRAM_1.5VS

D D

C C

B B

1

CV32

2

OPT@ CV32

OPT@

1

CV43

2

OPT@ CV43

OPT@

nder GPU

U

1

CV24

2

OPT@ CV24

OPT@

4.7U_0603_6.3V6K

N

ear GPU

1

CV44

2

OPT@ CV44

OPT@

22U_0805_6.3V6M

1

CV33

2

OPT@ CV33

OPT@

1U_0402_6.3V6K

10U_0603_6.3V6M

1

2

1

CV34

2

OPT@ CV34

OPT@

1U_0402_6.3V6K

4

1

CV25

2

OPT@ CV25

OPT@

0.1U_0402_10V7K

CV35

OPT@ CV35

OPT@

0.1U_0402_10V7K

UV1D

B26 C25 E23 E26 F14 F21 G13 G14 G15 G16 G18 G19 G20 G21 H24 H26

J21 K21 L22 L24 L26

M21

N21 R21 T21 V21

W21

V7

W7 AA6

W6

Y6

M7 N7

T6 P6

T7 R7 U6 R6

J7

K7

K6 H6

J6

N14P-GV2-S-A2_FCBGA595

N14PGV2@

Part 4 of 6

3500 mA 2000 mA

FBVDDQ_01 FBVDDQ_02 FBVDDQ_03 FBVDDQ_04 FBVDDQ_05 FBVDDQ_06 FBVDDQ_07 FBVDDQ_08 FBVDDQ_09 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27

IFPAB_PLLVDD_1 IFPAB_PLLVDD_2 IFPAB_RSET IFPA_IOVDD IFPB_IOVDD

IFPC_PLLVDD_1 IFPC_PLLVDD_2 IFPC_RSET IFPC_IOVDD

IFPD_PLLVDD_2 IFPD_PLLVDD_1 IFPD_RSET IFPD_IOVDD

NC NC NC NC NC

PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8

PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14

PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5 PEX_IOVDD_6

VDD33_1 VDD33_2 VDD33_3 VDD33_4

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

PEX_PLL_HVDD_1 PEX_PLL_HVDD_2

PEX_SVDD_3V3

120mA

PEX_PLLVDD_1

PEX_PLLVDD_2

3

AA10 AA12 AA13 AA16 AA18 AA19 AA20 AA21 AB22 AC23 AD24 AE25 AF26 AF27

AA22 AB23 AC24 AD25 AE26 AE27

G10 G12 G8 G9

D22

+FB_CAL_PD_VDDQ

C24

FB_CAL_PU_GND

B25

FB_CAL_TERM_GND

AA8 AA9

AB8

AA14 AA15

Under GPU

Near Ball

1

CV54

2

OPT@ CV54

OPT@

1 2

1

2

0.1U_0402_10V7K

Near GPU

Under GPU

1

CV26

2

OPT@ CV26

OPT@

1U_0402_6.3V6K

1

CV36

2

OPT@ CV36

OPT@

1U_0402_6.3V6K

RV3940.2_0402_1%

OPT@

12

RV4142.2_0402_1%

OPT@

12

RV4251.1_0402_1%

OPT@

1

CV55

2

OPT@ CV55

OPT@

1U_0402_6.3V6K

1

CV23

2

OPT@ CV23

OPT@

1U_0402_6.3V6K

1

CV37

2

OPT@ CV37

OPT@

1U_0402_6.3V6K

+VRAM_1.5VS

+PEX_PLLVDD

CV56

OPT@ CV56

OPT@

4.7U_0603_6.3V6K

1

CV27

2

OPT@ CV27

OPT@

1

CV38

2

OPT@ CV38

OPT@

4.7U_0603_6.3V6K

m and Power supply

1

2

1

2

Near GPU

Under GPU

1

CV45

2

OPT@ CV45

OPT@

0.1U_0402_10V7K

LV4

BLM18PG121SN1D_0603

N14MGL@

RV1

0_0603_5%

N14PGV2@

2

idway between GPU

CV28

OPT@ CV28

OPT@

10U_0603_6.3V6M

CV39

OPT@ CV39

OPT@

10U_0603_6.3V6M

2

1

2

OPT@ CV29

OPT@

10U_0603_6.3V6M

CV40

OPT@ CV40

OPT@

10U_0603_6.3V6M

2

1

2

1

CV29

Near GPU

1

CV47

CV46

2

OPT@ CV47

OPT@

OPT@ CV46

OPT@

0.1U_0402_10V7K

+1.05VS_DGPU

12

+1.05VS_DGPU

1

CV30

CV31

2

OPT@ CV30

OPT@

OPT@ CV31

OPT@

22U_0805_6.3V6M

+1.05VS_DGPU

1

CV42

CV41

2

OPT@ CV42

OPT@

OPT@ CV41

OPT@

22U_0805_6.3V6M

+3VS_DGPU

1

CV48

CV49

2

OPT@ CV48

OPT@

OPT@ CV49

OPT@

1U_0402_6.3V6K

4.7U_0603_6.3V6K

Under GPU C

lose to AH12/AG12

1

2

CV50

OPT@ CV50

OPT@

0.1U_0402_10V7K

1

2

Near GPU

CV51

OPT@ CV51

OPT@

0.1U_0402_10V7K

1

CV52

2

OPT@ CV52

OPT@

+3VS_DGPU

1

CV53

2

OPT@ CV53

OPT@

4.7U_0603_6.3V6K

1

4.7U_0603_6.3V6K

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/09/28 2013/09/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

VGA_N14x POWER

1

0.3

16 57Monday, March 18, 2013

0.3

5

4

3

2

1

+1.05VS_VCCP to +1.05VS_DGPU

+5VALW

12

RV43

RV43 270K_0402_5%

270K_0402_5%

OPT@

61

2N7002DW-T/R7_SOT363-6

0.01U_0402_25V7K

VGA_PWROK

OPT@

QV4A

2

VGA_PWROK#

QV5A

2

G

OPT@

AO3416_SOT23-3

+1.05VS_DGPU

+1.05VS_VCCP

Vgs=4.5V,Id=6.5A,Rds<22mohm

QV3

OPT@

QV3

OPT@

13

D

2

G

S

CV57

OPT@

1

2

+1.5V to +VRAM_1.5VS

CV59

OPT@

+1.5VS

QV6

OPT@QV6

OPT@

8

D

7

D

6

D

5

D

FDS6676AS_SO8

1

CV60

OPT@

2

4.7U_0603_6.3V6K

+VRAM_1.5VS

Vgs=10V,Id=14.5A,Rds=6mohm

1

S

2

S

3

S

4

G

VRAM_1.5VS_GATE

1

12

RV48

RV48 820K_0402_5%OPT@

0.01U_0402_25V7K

820K_0402_5%OPT@

2N7002DW-T/R7_SOT363-6

2

1.5V_PWR_EN

OPT@

RV47

1 2

180K_0402_5%

61

QV7A

2

OPT@

QV5B

5

G

OPT@

B+

1.5V_PWR_EN#

34

D

2N7002KDWH_SOT363-6

S

2N7002DW-T/R7_SOT363-6

1 2

OPT@

61

D

2N7002KDWH_SOT363-6

S

RV46

RV46 470_0805_5%

470_0805_5%

OPT@

1 2

3

QV7B

5

2N7002DW-T/R7_SOT363-6

OPT@

4

1 2

RV49100K_0402_5%

OPT@

+1.05VS_DGPU

RV44

22_0805_5%OPT@

1 2

3

OPT@

QV4B

5

4

RV45100K_0402_5%

+5VALW

V18 V16 V14 V12 V10 U17 U15 U13 U11 T18 T16 T14 T12 T10 R17 R15 R13 R11 P18 P16 P14

+3VS

UV2

5

N14PGV2@

4

Vcc

Y

G

NC7SZ32P5X_SC70-5

3

+VGA_CORE+VGA_CORE

1.5V_PWR_EN

UV1F

K10 K12 K14 K16 K18 L11 L13 L15

L17 M10 M12 M14 M16 M18 N11 N13 N15 N17

P10

P12

FB_CLAMP<13,14,44>

UV1F

VDD_001 VDD_002 VDD_003 VDD_004 VDD_005 VDD_006 VDD_007 VDD_008 VDD_009 VDD_010 VDD_011 VDD_012 VDD_013 VDD_014 VDD_015 VDD_016 VDD_017 VDD_018 VDD_019 VDD_020

N

14P-GV2-S-A2_FCBGA595

N14PGV2@

Part 6 of 6

VDD_041 VDD_040 VDD_039 VDD_038 VDD_037 VDD_036 VDD_035 VDD_034 VDD_033 VDD_032 VDD_031 VDD_030 VDD_029 VDD_028 VDD_027 VDD_026 VDD_025 VDD_024 VDD_023 VDD_022 VDD_021

2

B

1

A

1 2

RV50 0_0402_5%

N14MGL@

UV1E

A2

A26 AB11 AB14 AB17 AB20

D D

C C

B B

AB24

AC2 AC22 AC26

AC5

AC8 AD12 AD13 AD15 AD16 AD18 AD19 AD21 AD22 AE11 AE14 AE17 AE20

AF1 AF11 AF14 AF17 AF20 AF23

AF5

AF8

AG2 AG26

B1 B11 B14 B17 B20 B23 B27

B5

B8 E11 E14 E17

E2 E20 E22 E25

E5

E8

H2 H23 H25

H5

N14P-GV2-S-A2_FCBGA595

N14PGV2@

GND_001 GND_002 GND_003 GND_004 GND_005 GND_006 GND_007 GND_008 GND_009 GND_010 GND_011 GND_012 GND_013 GND_014 GND_015 GND_016 GND_017 GND_018 GND_019 GND_020 GND_021 GND_022 GND_023 GND_024 GND_025 GND_026 GND_027 GND_028 GND_029 GND_030 GND_031 GND_032 GND_033 GND_034 GND_035 GND_036 GND_037 GND_038 GND_039 GND_040 GND_041 GND_042 GND_043 GND_044 GND_045 GND_046 GND_047 GND_048 GND_049 GND_050 GND_051 GND_052 GND_053 GND_054 GND_055 GND_056

Part 5 of 6

GND_057 GND_058 GND_059 GND_060 GND_061 GND_062 GND_063 GND_064 GND_065 GND_066 GND_067 GND_068 GND_069 GND_070 GND_071 GND_072 GND_073 GND_074 GND_075 GND_076 GND_077 GND_078 GND_079 GND_080 GND_081 GND_082 GND_083 GND_084 GND_085 GND_086 GND_087 GND_088 GND_089 GND_090 GND_091 GND_092 GND_093 GND_094 GND_095 GND_096 GND_097 GND_098 GND_099 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112

GND GND

K11 K13 K15 K17 L10 L12 L14 L16 L18 L2 L23 L25 L5 M11 M13 M15 M17 N10 N12 N14 N16 N18 P11 P13 P15 P17 P2 P23 P26 P5 R10 R12 R14 R16 R18 T11 T13 T15 T17 U10 U12 U14 U16 U18 U2 U23 U26 U5 V11 V13 V15 V17 Y2 Y23 Y26 Y5

AA7 AB7

For GC6

VGA_PWROK<33,55>

+3VS to +3VS_DGPU

+VGA_CORE

RV51

470_0805_5%

OPT@

1 2 3

QV9B

5

2N7002DW-T/R7_SOT363-6

A A

5

4

OPT@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DGPU_PWR_EN#

4

3

RV52

470_0805_5%

OPT@

1 2 3

QV2B

5

2N7002DW-T/R7_SOT363-6

OPT@

4

Compal Secret Data

2012/09/28 2013/09/28

Compal Secret Data

Deciphered Date

DGPU_PWR_EN<31>

2

DGPU_PWR_EN#

+3VS+3VS_DGPU

RV53

RV53 10K_0402_5%OPT@

10K_0402_5%OPT@

1 2

RV54

1 2

33K_0402_5%

61

OPT@

QV9A

2N7002DW-T/R7_SOT363-6

OPT@

2

OPT@

Title

Size Document Number Rev

Custom

Date: Sheet of

2

CV61

0.1U_0402_10V7K

OPT@

1

AO3413_SOT23

2

CV62

OPT@

0.01U_0402_25V7K

1

Compal Electronics, Inc.

VGA_N14x POWER & GND

+3VS

Vgs=-4.5V,Id=3A,Rds<97mohm

S

QV11

G

2

OPT@

D

1 3

+3VS_DGPU

17 57Monday, March 18, 2013

1

17 57Monday, March 18, 2013

0.3

5

RANK 0 [31...0]

VRAM DDR3 Chips

+VRAM_1.5VS

12

+VRAM_1.5VS

12

DQSA[3..0]

DQSA#[3..0]

DQMA[3..0]

MDA[31..0]

CMDA[30..0]

+MEM_VREF_CA0

1

CV63

0.01U_0402_25V7K

OPT@

2

+MEM_VREF_DQ0

1

CV64

0.01U_0402_25V7K

OPT@

2

+MEM_VREF_CA0

+MEM_VREF_DQ0

243_0402_1%

DQSA[3..0]<14,20>

D D

DQSA#[3..0]<14,20>

DQMA[3..0]<14,20>

MDA[31..0]<14,20>

CMDA[30..0]

RV55

1K_0402_1%

OPT@

RV56

1K_0402_1%

OPT@

C C

RV57

1K_0402_1%

OPT@

RV58

1K_0402_1%

OPT@

B B

4

UV3

@

UV3

@

+MEM_VREF_CA0 +MEM_VREF_DQ0

OPT@

RV60

M8

VREFCA

H1

VREFDQ

N3

CMDA7 CMDA10 CMDA24 CMDA6 CMDA22 CMDA26 CMDA5 CMDA21 CMDA8 CMDA4 CMDA25 CMDA23 CMDA9 CMDA12 CMDA14

CMDA29 CMDA13 CMDA27

CLKA0 CLKA0 CLKA0# CMDA3

CMDA0 CMDA2 CMDA11 CMDA15 CMDA28

DQSA1 DQSA2

DQMA1 DQMA2

DQSA#1 DQSA#2

CMDA20

12

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

310mA

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4B1G1646E-HC12_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

MDA9 MDA12 MDA8 MDA15 MDA13 MDA11 MDA10 MDA14

MDA18 MDA22 MDA16 MDA23 MDA17 MDA20 MDA19 MDA21

+VRAM_1.5VS

3

Group1

Group2

OPT@

RV61

243_0402_1%

+MEM_VREF_CA0 +MEM_VREF_DQ0

CMDA7 CMDA10 CMDA24 CMDA6 CMDA22 CMDA26 CMDA5 CMDA21 CMDA8 CMDA4 CMDA25 CMDA23 CMDA9 CMDA12 CMDA14

CMDA29 CMDA13 CMDA27

CLKA0# CMDA3

CMDA0 CMDA2 CMDA11 CMDA15 CMDA28

DQSA0 DQSA3

DQMA0 DQMA3

DQSA#0 DQSA#3

CMDA20

ZQ1ZQ0

12

UV4

@

UV4

M8 H1

N3

P7 P3

N2

P8

P2 R8 R2

T8 R3

L7 R7 N7

T3

T7 M7

M2 N8 M3

J7

K7

K9

K1

L2

J3

K3

L3

F3 C7

E7 D3

G3

B7

T2

L8

J1

L1

J9

L9

@

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS/CS0 RAS CAS WE

3

10mA

DQSL DQSU

DML DMU

DQSL DQSU

RESET

ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4B1G1646E-HC12_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VSS VSS VSS

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

+VRAM_1.5VS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+VRAM_1.5VS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

MDA6 MDA1 MDA5 MDA0 MDA4 MDA2 MDA7 MDA3

MDA30 MDA26 MDA29 MDA24 MDA28 MDA27 MDA31 MDA25

2

Mode E Address

CMD0

Rank 0 Rank 1

0..31

ODT

CMD1

Group0

Group3

CMD2

CMD3

CMD4

CMD5

CMD6

CMD7

CMD8

CMD9

CMD10

CMD11

CMD12

CMD13

CMD14

CMD15

CS0#

CKE

A9

A6

A3

A0

A8

A12

A1

RAS#

A13

BA1

A14

CAS#

CMD16

CMD17

CMD18

CMD19

CMD20

CMD21 A7

CMD22

CMD23

CMD24

CMD25

CMD26

CMD27

CMD28

CMD29

RST

A7

A4

A11

A2

A10

A5

BA2

WE#

BA0

CMD30

1

32..63

0..31 32..63

ODT

CS1#

CKE

A11

A6

A3

A0

A8

A12 A0

A1

A7 A7

BA1 BA1

A12 A12

A8 A8

A0

A2 A2

RAS# RAS# RAS#

A13

A14

A3

A14

CAS#

A13 A13

CAS# CAS#

ODT

CS0#

CKE

RST RST RST

A6

A4

A11

A2

A10

A5

A5 A5

A9 A9

A1 A1

WE# WE#

A4 A4

BA2

WE#

BA0

A10 A10

BA0 BA0

BA2

A11A9

A14

A3BA1

ODT

CS1#

CKE

A6

BA2

Place close to the first T point

CLKA0<14,20>

CLKA0#<14,20>

12

OPT@

RV63

RV63 160_0402_1%

160_0402_1%

lace close to RANK0 VRAM

P

+VRAM_1.5VS +VRAM_1.5VS

1

2

A A

5

1

CV67

2

OPT@ CV67

OPT@

1U_0402_6.3V6K

4

1

CV68

2

OPT@ CV68

OPT@

1U_0402_6.3V6K

1

CV69

2

OPT@ CV69

OPT@

1U_0402_6.3V6K

1

CV70

2

OPT@ CV70

OPT@

1U_0402_6.3V6K

1

CV71

2

OPT@ CV71

OPT@

1U_0402_6.3V6K

1

CV72

2

OPT@ CV72

OPT@

0.1U_0402_10V7K

1

CV73

2

OPT@ CV73

OPT@

0.1U_0402_10V7K

1

CV75

CV74

OPT@ CV74

OPT@

0.1U_0402_10V7K

CV76

2

OPT@ CV75

OPT@

OPT@ CV76

OPT@

0.1U_0402_10V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/09/28 2013/09/28

1

2

1

CV77

2

OPT@ CV77

OPT@

1U_0402_6.3V6K

1

CV78

CV79

CV80

2

OPT@ CV78

OPT@

OPT@ CV79

OPT@

OPT@ CV80

1U_0402_6.3V6K

Compal Secret Data

OPT@

1U_0402_6.3V6K

Deciphered Date

1

2

1

CV81

2

OPT@ CV81

OPT@

1U_0402_6.3V6K

1

CV82

2

OPT@ CV82

OPT@

0.1U_0402_10V7K

2

1

CV83

2

OPT@ CV83

OPT@

0.1U_0402_10V7K

1

CV84

2

OPT@ CV84

OPT@

0.1U_0402_10V7K

1

CV85

2

OPT@ CV85

OPT@

0.1U_0402_10V7K

+VRAM_1.5VS

1

CV86

OPT@ CV86

OPT@

0.1U_0402_10V7K

Title

Size Document Number Rev

Custom

Date: Sheet of

CV87

2

OPT@ CV87

OPT@

22U_0805_6.3V6M

Compal Electronics, Inc.

VGA_N14x VRAM RANK 0L

18 57Monday, March 18, 2013

1

18 57Monday, March 18, 2013

0.3

Compal LA-9866P VSKAA Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual