Compal LA-9863P VFKAA Rosetta 10FG, Satellite S40-A Schematic

5

B

+

D D

I

peak=8.13A, Imax=5.69A, Iocp min=8.7

USP#

S

SY8032ABC

S

USP#

T

PS22966DPUR

RT8243AZQW

Ipeak=5A, Imax=3.5A, Iocp min=6.2A

C C

S

USP#

T

PS22966DPUR

V

R_ON

5

NCP81012BMNR

SUSP#

S

Y8208QKC

S

YSON

R

T8207M

D

GPU_PWR_EN

N

CP81172MNTWG

Ipeak=20.53A, Imax=14.37A, Iocp min=23.91A

V

GA_PWROK#

N

-CHANNEL
AO3416

V

CCP_PWRGOOD

G

978F11U

I

peak=15A, Imax=10.5A, Iocp min=18A

0

.75VR_ON

S

USP

N-CHANNEL

F

DS6676AS

1

.5_PWR_EN#

N

-CHANNEL

FDS6676AS

I

peak=59A, Imax=45.7A, Iocp min=70A

B B

A A

4

P

CH_PWR_EN#

P-CHANNEL

O-3413

A

K

B_LED

P-CHANNEL

A

O-3413

+

5VS

L

DO

G

9191-330T1U

O

DD_EN#

P-CHANNEL

AO-3413

W

OWL_EN#

P

-CHANNEL
A

O-3413

P

CH_PWR_EN#

P-CHANNEL

AO-3413

L

CD_ENVDD

A

PL3512ABI

D

GPU_PWR_EN

P-CHANNEL

A

O-3413

4

ESIGN CURRENT 0 .1A

D

D

ESIGN CURRENT 5 A

D

ESIGN CURRENT 2 A

D

ESIGN CURRENT 6 A

D

ESIGN CURRENT 4 00mA

D

ESIGN CURRENT 3 00mA

D

ESIGN CURRENT 1 .6A

D

ESIGN CURRENT 5 A

D

ESIGN CURRENT 3 30mA

D

ESIGN CURRENT 3 A

DESIGN CURRENT 6A

D

ESIGN CURRENT 1 .5A

D

ESIGN CURRENT 0 .1A

D

ESIGN CURRENT 6 5A

D

ESIGN CURRENT 4 0A

D

ESIGN CURRENT 3 A

D

ESIGN CURRENT 6 A

D

ESIGN CURRENT 2 A

D

ESIGN CURRENT 1 .5A

D

ESIGN CURRENT 2 A

DESIGN CURRENT 2A

D

ESIGN CURRENT 1 1A

D

ESIGN CURRENT 3 0A

+

3VL

+

5VALW

+

5VALW_PCH

+

1.8VS

+

5VS

+

5VS_LED

+

3VS_HDP

+

5VS_ODD

+

3VALW

+

3V_LAN

+

3V_WLAN

+

3VALW_PCH

+

3VS

+

LCD_VDD

+

3VS_DGPU

+CPU_CORE

+

GFX_CORE

+1.05VS_VCCP

+

1.05VS_DGPU

+

VCCSA

+1.5V

+0.75VS

+

1.5V_CPU

+

1.5VS

+

VRAM_1.5VS

+

VGA_CORE

3

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

2

C

C

C

ompal Secret Data

ompal Secret Data

012/12/07 2013/12/07

012/12/07 2013/12/07

012/12/07 2013/12/07

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

V

V

V

FKAA

FKAA

FKAA

P

P

P

ower Tree

ower Tree

ower Tree

1

3

o

3

3

o

o

f

56Monday, March 11, 2013

f

56Monday, March 11, 2013

f

56Monday, March 11, 2013

0

0

0

.2

.2

.2

A

(

oltage Rails

V

power

1 1

2 2

S

5 S4/ Battery only

S5 S4/AC & Battery
don't exist

plane

State

S0

S1

S

3

S5 S4/AC

P

CH SM Bus Address

O MEANS ON X MEANS OFF )

+RTCVCC

O

O

O

O

O

O

B

O

O

O

O

O

X

+5VL

+

+

3VL

O

O

O

O

O

X

B

+5VALW

+

3VALW

O

O

O

O

X

X

+1.5V

O

X

X

X

+5VS

+3VS

+1.8VS

+1.5VS

+

1.05VS

+0.75VS

+

CPU_CORE

+

VGA_CORE

+GFX_CORE

+

VTT

+VRAM_1.5V S

+3VS_DGPU

+1.05VS_DG PU

OO

OO

X

X

X

X

C

TO Option Table

B

unction

F

description

explain

BTO

Function

description

explain

BTO

F

unction

description

explain

BTO

F

unction

description

explain

BTO

SKU

Optimus

Optimus

OPT@

LVDS-eDP

LVDS-eDP

LVDS eDP

LVDS@ IEDP@

WOWL

WOWL

w/

WOWL@

Sleep & Music

Sleep & Music

w/ S&M w/o S&M

269@ 259@

Panther Point

HM76R1@

HM76R3@ HM70R3@

w/o

NOWOWL@

PCH

HM70HM76

HM70R1@

Camera & Mic

Camera & Mic

Camera & Mic

CAM_EMI@

G-SENSOR

G-SENSOR

G-SENSOR

GSENSOR@

KB Light

K

B Light

KB Light

KBL@

D

G

PU

N14M-GL

N14MGL@

N14MGLR1@ N14PGV2R1@

N14MGLR3@ N14PGV2R3@

14640 14641

14640

14640@

ZPODD@

EMI/ESD part

EMI/ESD part

EMI/ESD part

EMI@ ESD@

USB S&C

w/

N14P-GV2

N14P-GV2N14M-GL

N14PGV2@

14641

14641@

ZPODD

ZPODD

w/o

NONZP@

VRAM

Dual Rank

Dual Rank

DRANK@

CRT

CRT

w/ CRT w/o CRT

CRT@ CRT_EMI@ NOCRT@

GCLK

GCLK

GCLK non-GCLK

GCLK@

non-GCLK

EC

EC

KB9012 NPCE885N

9012@ 885@

NOGCLK@

E

Touch Screen

Touch Screen

Touch Screen

TOUCH_EMI@

VRAM SKU for GV2

Single Rank

Single Rank

GVSR@

ISPD

HDMI Logo

HDMI Logo

HDMI45@

Dual Rank

Dual Rank

GVDR@

HEX

0001 0110 bSmart Battery

Address

1

010 0000 bA0 H

1010 0100 bA4 H

PowerPower

+3VS

+3VS

+3VS

E

C SM Bus2 Address

D

evice

9

6 H

1

E H

0 H

001 0110 bPCH

0100 0000 b

NVIDIA GPU 1001 1010 b

G-Sensor

B

9

4

S

TATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

G

3 LOW LOWLOW

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2

2

2

012/12/07 2013/12/07

012/12/07 2013/12/07

012/12/07 2013/12/07

SIGNAL

SLP_S3# SLP_S4# SLP_S5#

HIGH HIGHHIGH

LOW

LOW LOW

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

HIGH HIGHHIGH

HIGH

L

OW LOWLOW

HIGH

HIGH

D

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

N

N

N

otes List

otes List

otes List

V

V

V

FKAA

FKAA

FKAA

4 56Monday, March 11, 2013

4 56Monday, March 11, 2013

4 56Monday, March 11, 2013

E

o

o

o

f

f

f

0

0

0

.2

.2

.2

Power

+3VS

+

3VS

3 3

4 4

+3VS

+

3VS 2C H 0010 1100 bTouch Pad

+3VL

+3VL USB S&C 14640 35 H 0011 0101 b

Device

DDR SO-DIMM 0

DDR SO-DIMM 1

W

LAN/WIMAX

E

C SM Bus1 Address

D

evice Address Address

A

HEX HEX

16 H

12 H 0001 0010 bSmart Charger+3VL

5

4

3

2

1

CPUB

CPUB

J

J

1

00 MHz

B
B
B
B
B
B
B
B

B

CLK#

B

RDY#

P

REQ#

P

RST#

T

D

PM#[0]
PM#[1]
PM#[2]
PM#[3]
PM#[4]
PM#[5]
PM#[6]
PM#[7]

A28

CLK

A27

120 MHz

A16

C

LK_CPU_EDP

A15

C

LK_CPU_EDP#

R8

H

_DRAMRST#

AK1

S

M_RCOMP_0

A5

S

M_RCOMP_1

A4

S

M_RCOMP_2

AP29
AP27

AR26

X

CK

T

MS

T

T

DO

T

BR#

DP_TCK

AR27

X

DP_TMS

AP30

X

DP_TRST#

AR28

X

DP_TDI

DI

AP26

X

DP_TDO

AL35

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

C

C

LK_CPU_DMI <26>

C

LK_CPU_DMI# <26>

C

LK_CPU_EDP <26>

C

LK_CPU_EDP# <26>

H

_DRAMRST# <7>

C56 140_0402_1%

C56 140_0402_1%

R

R

C59 25.5_0402_1%

C59 25.5_0402_1%

R

R

R

R

C61 200_0402_1%

C61 200_0402_1%

12
12

2

1

T

13 PADT13 PAD

T

15 PADT15 PAD

2

1

C55 51_0402_5%

C55 51_0402_5%

R

R

T

7 PADT7 PAD

T

10 PADT10 PAD

lose to CPU side

@

@

12

P

M_DRAM_PWR GD_R

C621000P_0402_50V7K

C621000P_0402_50V7K

C

C

ESD@

ESD@

2

D D

C C

by ESD requestion and place near CPU

+

1.05VS_VCCP

R

R

C44 62_0402_5%

C44 62_0402_5%

2

R

R

C45 10K_0402_5%

C45 10K_0402_5%

+

3VALW_PCH

2

C11 200_0402_5%

C11 200_0402_5%

R

R

D

RAMPWROK<27>

1

2

1

1

@

@

2

1

@

@

12

@

@

12

P

lease place near JCPU

1

D

RAMPWROK

10K_0402_5%

10K_0402_5%

2

C13

C13

R

R

+

3VS

H

_PWRGOOD

C63180P_0402_50V8J

C63180P_0402_50V8J

C

C

H

_PROCHOT#

H

_PWRGOOD

C

C

C701000P_0402_50V7K

C701000P_0402_50V7K

H

C671000P_0402_50V7K

C671000P_0402_50V7K

C

C

C661000P_0402_50V7K

C661000P_0402_50V7K

C

C

_PM_SYNC

B

UF_CPU_RST#

+

3VALW_PCH

1

1

B

2

A

H

_PROCHOT#<41>

H

_PECI

0

206: Delete 0.1uF

C3

C3

U

U

5

74AHC1G09GW_TSSOP5

74AHC1G09GW_TSSOP5

P

4

P

M_SYS_PWRGD_BUF

O

G

3

H

_PWRGOOD<30>

H

_SNB_IVB#<30>

H

_PROCHOT#

H

_PM_SYNC<27>

P

M_SYS_PWRGD_BUF

+

1.5V_CPU

12

R

R

C14

C14

200_0402_5%

200_0402_5%

H

C159 56_0402_5%

C159 56_0402_5%

R

R

H

_THERMTRIP#<30>

H

_PWRGOOD

1 PADT1 PAD

T

T

2 PADT2 PAD

_PECI<41>

1 2

C183 0_0402_5%

C183 0_0402_5%

R

R

1 2

C170 1 30_0402_5%

C170 1 30_0402_5%

R

R

1 2

Rshort@

Rshort@

B

UF_CPU_RST#

H

_SNB_IVB#

T

P_SKTOCC#

H

_CATERR#

H

_PECI

H

_PROCHOT#_R

H

_PM_SYNC

H

_PWRGOOD_R

P

M_DRAM_PWR GD_R

C26

ROC_SELECT#

P

AN34

KTOCC#

S

AL33

ATERR#

C

AN33

ECI

P

AL32

ROCHOT#

P

AN32

HERMTRIP#

T

AM34

M_SYNC

P

AP33

NCOREPWRGOOD

U

V8

M_DRAMPWROK

S

AR33

ESET#

R

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

Conn@

Conn@

PLL_REF_CLK

MISCTHERMALPWR MANAGEMENT

MISCTHERMALPWR MANAGEMENT

D

PLL_REF_CLK#

D

LOCKS

LOCKS
C

C

M_DRAMRST#

S

M_RCOMP[0]

S

M_RCOMP[1]

S

DR3

DR3

M_RCOMP[2]

S

MISC

MISC

D

D

TAG & BPM

TAG & BPM
J

J

Stuff R41 and R42 if do not support eDP

+

1.05VS_VCCP

C

LK_CPU_EDP#

C

LK_CPU_EDP

H

_DRAMRST#

b

y ESD requestion and place near CPU

D

DR3 Compensatio n Signals
Layout Note:Pla ce these
resistors near Processor

1 2

R

R

C157 1K_0402_5%LVDS@

C157 1K_0402_5%LVDS@

1

R

R

C158 1K_0402_5%LVDS@

C158 1K_0402_5%LVDS@

@ESD@

@ESD@

1 2

C34 180P_0402_50V8J

C34 180P_0402_50V8J

C

C

2

B B

F

AN Control Circuit

+

B

uffered Reset to CPU

+

3VS

0206: Delete 0.1uF

P

LT_RST# <29,35,36,41>

C2

C2

U

U

1

E#

O

2

N

I

3

ND

A A

G

74AHC1G125GW_SOT353-5

74AHC1G125GW_SOT353-5

5

5

CC

V

4

B

UT

O

UFO_CPU_RST#

+

1.05VS_VCCP

1

R

R
75_0402_5%

75_0402_5%

2

C38

C38

R

R

C35

C35

43_0402_1%

43_0402_1%

1

2

B

UF_CPU_RST#

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2

2

2

012/12/07 2013/12/07

012/12/07 2013/12/07

012/12/07 2013/12/07

5VS

1

A

1

1 0_0603_5%

1 0_0603_5%

R

R

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

Rshort@

Rshort@

+

2

+

FAN1

F

AN_SPEED1<41>

2

3VS

12

2

2

R

R
10K_0402_5%

10K_0402_5%

F

ANPWM<41>

+

FAN1

12

1

1

D

D

BAS16_SOT23-3

BAS16_SOT23-3

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

I

I

I

vy Bridge_JTAG/XDP/FAN

vy Bridge_JTAG/XDP/FAN

vy Bridge_JTAG/XDP/FAN

V

V

V

FKAA

FKAA

FKAA

J

J

FAN

FAN

6

G

5

G

4

4

3

3

2

2

1

1

ACES_50273-0040N-001

ACES_50273-0040N-001

Conn@

Conn@

1

C

C

5

5

10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

6
5

0

0

0

.2

.2

.2

o

o

o

f

5 56Monday, March 11, 2013

f

5 56Monday, March 11, 2013

f

5 56Monday, March 11, 2013

5

4

3

2

1

+

1.05VS_VCCP

R

R

C1

C1

24.9_0402_1%

J

J

CPUA

CPUA

D D

C C

+

1.05VS_VCCP

e

DP_COMP signals should be
shorted near balls and
routed with typical
impedance <25m ohm

B B

+

1.05VS_VCCP

D

MI_PTX_CRX_N0<27>

D

MI_PTX_CRX_N1<27>

D

MI_PTX_CRX_N2<27>

D

MI_PTX_CRX_N3<27>

D

MI_PTX_CRX_P0<27>

D

MI_PTX_CRX_P1<27>

D

MI_PTX_CRX_P2<27>

D

MI_PTX_CRX_P3<27>

D

MI_CTX_PRX_N0<27>

D

MI_CTX_PRX_N1<27>

D

MI_CTX_PRX_N2<27>

D

MI_CTX_PRX_N3<27>

D

MI_CTX_PRX_P0<27>

D

MI_CTX_PRX_P1<27>

D

MI_CTX_PRX_P2<27>

D

MI_CTX_PRX_P3<27>

F

DI_CTX_PRX_N0<27>

F

DI_CTX_PRX_N1<27>

F

DI_CTX_PRX_N2<27>

F

DI_CTX_PRX_N3<27>

F

DI_CTX_PRX_N4<27>

F

DI_CTX_PRX_N5<27>

F

DI_CTX_PRX_N6<27>

F

DI_CTX_PRX_N7<27>

F

DI_CTX_PRX_P0<27>

F

DI_CTX_PRX_P1<27>

F

DI_CTX_PRX_P2<27>

F

DI_CTX_PRX_P3<27>

F

DI_CTX_PRX_P4<27>

F

DI_CTX_PRX_P5<27>

F

DI_CTX_PRX_P6<27>

F

DI_CTX_PRX_P7<27>

F

DI_FSYNC0<27>

F

DI_FSYNC1<27>

F

DI_INT<27>

F

DI_LSYNC0<27>

F

DI_LSYNC1<27>

2

1

R

R

C2 24.9_0402_1%

C2 24.9_0402_1%

H

_EDP_AUXP<22>

H

_EDP_AUXN<22>

H

_EDP_TXP0<22>

H

_EDP_TXP1<22>

H

_EDP_TXN0<22>

H

_EDP_TXN1<22>

E

DP_COMP

H

_EDP_HPD#

B27

D

MI_RX#[0]

B25

D

MI_RX#[1]

A25

D

MI_RX#[2]

B24

D

MI_RX#[3]

B28

D

MI_RX[0]

B26

MI_RX[1]

D

A24

MI_RX[2]

D

B23

MI_RX[3]

D

G21

MI_TX#[0]

D

E22

MI_TX#[1]

D

F21

MI_TX#[2]

D

D21

MI_TX#[3]

D

G22

MI_TX[0]

D

D22

MI_TX[1]

D

F20

MI_TX[2]

D

C21

MI_TX[3]

D

A21

DI0_TX#[0]

F

H19

DI0_TX#[1]

F

E19

DI0_TX#[2]

F

F18

DI0_TX#[3]

F

B21

DI1_TX#[0]

F

C20

DI1_TX#[1]

F

D18

DI1_TX#[2]

F

E17

DI1_TX#[3]

F

A22

DI0_TX[0]

F

G19

DI0_TX[1]

F

E20

DI0_TX[2]

F

G18

DI0_TX[3]

F

B20

DI1_TX[0]

F

C19

DI1_TX[1]

F

D19

DI1_TX[2]

F

F17

DI1_TX[3]

F

J18

DI0_FSYNC

F

J17

DI1_FSYNC

F

H20

DI_INT

F

J19

DI0_LSYNC

F

H17

DI1_LSYNC

F

A18

DP_COMPIO

e

A17

DP_ICOMPO

e

B16

DP_HPD#

e

C15

DP_AUX

e

D15

DP_AUX#

e

C17

DP_TX[0]

e

F16

DP_TX[1]

e

C16

DP_TX[2]

e

G15

DP_TX[3]

e

C18

DP_TX#[0]

e

E16

DP_TX#[1]

e

D16

DP_TX#[2]

e

F15

DP_TX#[3]

e

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

Conn@

Conn@

DMI

DMI

ntel(R) FDI

ntel(R) FDI
I

I

DP

DP
e

e

P

P

EG_RCOMPO

P

P
P
P
P
P
P

P

CI EXPRESS* - GRAPHICS

CI EXPRESS* - GRAPHICS

P
P

P

P

P
P
P

EG_ICOMPI

EG_ICOMPO

EG_RX#[0]

P

EG_RX#[1]

P

EG_RX#[2]

P

EG_RX#[3]

P

EG_RX#[4]

P

EG_RX#[5]

P

EG_RX#[6]

P

EG_RX#[7]

P

EG_RX#[8]

P

EG_RX#[9]

P
EG_RX#[10]
EG_RX#[11]
EG_RX#[12]
EG_RX#[13]
EG_RX#[14]
EG_RX#[15]

EG_RX[0]

P

EG_RX[1]

P

EG_RX[2]

P

EG_RX[3]

P

EG_RX[4]

P

EG_RX[5]

P

EG_RX[6]

P

EG_RX[7]

P

EG_RX[8]

P

EG_RX[9]

P
EG_RX[10]

P

EG_RX[11]

P

EG_RX[12]

P

EG_RX[13]

P

EG_RX[14]

P

EG_RX[15]

P

EG_TX#[0]

P

EG_TX#[1]

P

EG_TX#[2]

P

EG_TX#[3]

P

EG_TX#[4]

P

EG_TX#[5]

P

EG_TX#[6]

P

EG_TX#[7]

P

EG_TX#[8]

P

EG_TX#[9]

P
EG_TX#[10]
EG_TX#[11]
EG_TX#[12]
EG_TX#[13]
EG_TX#[14]
EG_TX#[15]

EG_TX[0]

P

EG_TX[1]

P

EG_TX[2]

P

EG_TX[3]

P

EG_TX[4]

P

EG_TX[5]

P

EG_TX[6]

P

EG_TX[7]

P

EG_TX[8]

P

EG_TX[9]

P

EG_TX[10]

P

EG_TX[11]

P

EG_TX[12]

P

EG_TX[13]

P

EG_TX[14]

P

EG_TX[15]

P

J22
J21
H22

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

P

EG_COMP

P

CIE_GTX_C_CRX_N0

P

CIE_GTX_C_CRX_N1

P

CIE_GTX_C_CRX_N2

P

CIE_GTX_C_CRX_N3

P

CIE_GTX_C_CRX_P0

P

CIE_GTX_C_CRX_P1

P

CIE_GTX_C_CRX_P2

P

CIE_GTX_C_CRX_P3

P

CIE_CTX_GRX_N0

P

CIE_CTX_GRX_N1

P

CIE_CTX_GRX_N2

P

CIE_CTX_GRX_N3

P

CIE_CTX_GRX_P0

P

CIE_CTX_GRX_P1

P

CIE_CTX_GRX_P2

P

CIE_CTX_GRX_P3

24.9_0402_1%

1 2

C

C

C8 0.22U_0402_16V7K

C8 0.22U_0402_16V7K

1 2

C

C

C11 0.22U_040 2_16V7K

C11 0.22U_040 2_16V7K

1

C16 0.22U_040 2_16V7K

C16 0.22U_040 2_16V7K

C

C

1

C

C

C20 0.22U_040 2_16V7K

C20 0.22U_040 2_16V7K

1 2

C10 0.22U_040 2_16V7K

C10 0.22U_040 2_16V7K

C

C

1 2

C

C

C5 0.22U_0402_16V7K

C5 0.22U_0402_16V7K

1

C6 0.22U_0402_16V7K

C6 0.22U_0402_16V7K

C

C

1 2

C7 0.22U_0402_16V7K

C7 0.22U_0402_16V7K

C

C

IVY Bridge

PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical

12

impedance = 43 m ohm (4 mils)
PEG_ICOMPO signals should be routed with ­max length = 500 mils

- typical impedance = 14.5 m ohm (12 mils)

P

CIE_GTX_C_CRX_N[0..3] <13>

P

CIE_GTX_C_CRX_P[0..3] <13>

P

CIE_CTX_C_GRX_N0

P

2

2

2

CIE_CTX_C_GRX_N1

P

CIE_CTX_C_GRX_N2

P

CIE_CTX_C_GRX_N3

P

CIE_CTX_C_GRX_P0

P

CIE_CTX_C_GRX_P1

P

CIE_CTX_C_GRX_P2

P

CIE_CTX_C_GRX_P3

PEG DG suggest AC cap

Gen1/Gen2

75 nF~265 nF

P

CIE_CTX_C_GRX_N[0..3] <1 3>

P

CIE_CTX_C_GRX_P[0..3] <13>

Gen3 180 nF~265 nF

C9

C9

R

R
1K_0402_5%

1K_0402_5%

1 2

H

_EDP_HPD#

1

UT
O

C

PU_EDP_HPD<22>

A A

2

I

N

ND
G

Q

Q

C1

C1

DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

3

IEDP@

IEDP@

SANDY Bridge Gen1/Gen2 180 nF~265 nF

NV N14x Gen1/2/3 Suggest 220 nF

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2

2

2

012/12/07 2013/12/07

012/12/07 2013/12/07

012/12/07 2013/12/07

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

I

I

I

vy Bridge_DMI/PEG/FDI

vy Bridge_DMI/PEG/FDI

vy Bridge_DMI/PEG/FDI

V

V

V

FKAA

FKAA

FKAA

1

0

0

0

.2

.2

.2

o

o

o

f

6 56Monday, March 11, 2013

f

6 56Monday, March 11, 2013

f

6 56Monday, March 11, 2013

5

CPUC

CPUC

J

AP11
AN11

AL12
AM12
AM11

AL11

AP12
AN12

AJ14

AH14

AL15

AK15

AL14

AK14

AJ15

AH15

AE10

AF10

G10

M10

AG6
AG5
AK6
AK5
AH5
AH6

AK8

AK9
AH8
AH9

AE8
AD9

J

C5

S

A_DQ[0]

D5

S

A_DQ[1]

D3

S

A_DQ[2]

D2

S

A_DQ[3]

D6

S

A_DQ[4]

C6

S

A_DQ[5]

C2

S

A_DQ[6]

C3

S

A_DQ[7]

F10

S

A_DQ[8]

F8

S

A_DQ[9]

S

A_DQ[10]

G9

S

A_DQ[11]

F9

S

A_DQ[12]

F7

S

A_DQ[13]

G8

S

A_DQ[14]

G7

S

A_DQ[15]

K4

S

A_DQ[16]

K5

S

A_DQ[17]

K1

S

A_DQ[18]

J1

S

A_DQ[19]

J5

S

A_DQ[20]

J4

S

A_DQ[21]

J2

S

A_DQ[22]

K2

S

A_DQ[23]

M8

S

A_DQ[24]

N10

S

A_DQ[25]

N8

S

A_DQ[26]

N7

S

A_DQ[27]

S

A_DQ[28]

M9

S

A_DQ[29]

N9

S

A_DQ[30]

M7

S

A_DQ[31]

S

A_DQ[32]

S

A_DQ[33]

S

A_DQ[34]

S

A_DQ[35]

S

A_DQ[36]

S

A_DQ[37]

AJ5

S

A_DQ[38]

AJ6

S

A_DQ[39]

AJ8

S

A_DQ[40]

S

A_DQ[41]

AJ9

S

A_DQ[42]

S

A_DQ[43]

S

A_DQ[44]

S

A_DQ[45]

AL9

S

A_DQ[46]

AL8

S

A_DQ[47]

S

A_DQ[48]

S

A_DQ[49]

S

A_DQ[50]

S

A_DQ[51]

S

A_DQ[52]

S

A_DQ[53]

S

A_DQ[54]

S

A_DQ[55]

S

A_DQ[56]

S

A_DQ[57]

S

A_DQ[58]

S

A_DQ[59]

S

A_DQ[60]

S

A_DQ[61]

S

A_DQ[62]

S

A_DQ[63]

A_BS[0]

S

A_BS[1]

S

V6

A_BS[2]

S

A_CAS#

S

A_RAS#

S

AF9

A_WE#

S

DR SYSTEM MEMORY A

DR SYSTEM MEMORY A
D

D

DR_A_D[0..63]<11>

D

DR_A_D0

D

DR_A_D1

D

DR_A_D2

D

D

DR_A_D3

D

D D

C C

DR_A_BS0<11>

B B

D

DR_A_BS1<11>

D

DR_A_BS2<11>

D

DR_A_CAS#<11>

D

DR_A_RAS#<11>

D

DR_A_WE#<11>

D

DR_A_D4

D

DR_A_D5

D

DR_A_D6

D

DR_A_D7

D

DR_A_D8

DR_A_D9

D

DR_A_D10

D

DR_A_D11

D

DR_A_D12

D

DR_A_D13

D

DR_A_D14

D

DR_A_D15

D

DR_A_D16

D

DR_A_D17

D

DR_A_D18

D

DR_A_D19

D

DR_A_D20

D

DR_A_D21

D

DR_A_D22

D

DR_A_D23

D

DR_A_D24

D

DR_A_D25

D

DR_A_D26

D

DR_A_D27

D

DR_A_D28

D

DR_A_D29

D

DR_A_D30

D

DR_A_D31

D

DR_A_D32

D

DR_A_D33

D

DR_A_D34

D

DR_A_D35

D

DR_A_D36

D

DR_A_D37

D

DR_A_D38

D

D

DR_A_D39

D

DR_A_D40

D

DR_A_D41

D

DR_A_D42

D

DR_A_D43

D

DR_A_D44

D

DR_A_D45

D

DR_A_D46

D

DR_A_D47

DR_A_D48

D

DR_A_D49

D

DR_A_D50

D

DR_A_D51

D

DR_A_D52

D

DR_A_D53

D

DR_A_D54

D

DR_A_D55

D

D

DR_A_D56

D

DR_A_D57

D

DR_A_D58

D

DR_A_D59

DR_A_D60

D

DR_A_D61

D

D

DR_A_D62

D

DR_A_D63

S

A_CLK[0]

S

A_CLK#[0]

S

A_CKE[0]

A_CLK[1]

S

S

A_CLK#[1]

A_CKE[1]

S

R

SVD_TP[1]

R

SVD_TP[2]

R

SVD_TP[3]

R

SVD_TP[4]

R

SVD_TP[5]

R

SVD_TP[6]

A_CS#[0]

S

A_CS#[1]

S

R

SVD_TP[7]

R

SVD_TP[8]

A_ODT[0]

S

A_ODT[1]

S

R

SVD_TP[9]

R

SVD_TP[10]

A_DQS#[0]

S

A_DQS#[1]

S
S

A_DQS#[2]

S

A_DQS#[3]

S

A_DQS#[4]

S

A_DQS#[5]

S

A_DQS#[6]

S

A_DQS#[7]

A_DQS[0]

S
S

A_DQS[1]
A_DQS[2]

S
S

A_DQS[3]

S

A_DQS[4]

S

A_DQS[5]

S

A_DQS[6]

S

A_DQS[7]

S

A_MA[0]

S

A_MA[1]

S

A_MA[2]

S

A_MA[3]

S

A_MA[4]

S

A_MA[5]

S

A_MA[6]

S

A_MA[7]

S

A_MA[8]

S

A_MA[9]

S

A_MA[10]

S

A_MA[11]

S

A_MA[12]

S

A_MA[13]

S

A_MA[14]

S

A_MA[15]

4

DR_B_D[0..63]<12>

D

AB6
AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

D

DR_A_DQS#0

D

DR_A_DQS#1

D

DR_A_DQS#2

D

DR_A_DQS#3

D

DR_A_DQS#4

D

DR_A_DQS#5

D

DR_A_DQS#6

D

DR_A_DQS#7

DR_A_DQS0

D

DR_A_DQS1

D

D

DR_A_DQS2

DR_A_DQS3

D

D

DR_A_DQS4

D

DR_A_DQS5

D

DR_A_DQS6

D

DR_A_DQS7

DR_A_MA0

D

DR_A_MA1

D

DR_A_MA2

D

DR_A_MA3

D

DR_A_MA4

D

DR_A_MA5

D

DR_A_MA6

D

DR_A_MA7

D

DR_A_MA8

D

DR_A_MA9

D

DR_A_MA10

D

DR_A_MA11

D

DR_A_MA12

D

DR_A_MA13

D

DR_A_MA14

D

D

DR_A_MA15

DRA_CLK0 <11>

D

DRA_CLK0# <11>

D

DRA_CKE0 <11>

D

DRA_CLK1 <11>

D

DRA_CLK1# <11>

D

DRA_CKE1 <11>

D

DRA_SCS0# <11>

D

DRA_SCS1# <11>

D

DRA_ODT0 <11>

D

DRA_ODT1 <11>

D

DR_A_DQS#[0..7] <11>

D

DR_A_DQS[0..7] <11>

D

DR_A_MA[0..15] <11>

D

3

J

J

CPUD

CPUD

D

DR_B_D0

D

DR_B_D1

D

DR_B_D2

D

DR_B_D3

D

DR_B_D4

D

DR_B_D5

D

DR_B_D6

D

DR_B_D7

D

DR_B_D8

D

DR_B_D9

D

DR_B_D10

D

DR_B_D11

D

DR_B_D12

D

DR_B_D13

D

DR_B_D14

D

DR_B_D15

D

DR_B_D16

D

DR_B_D17

D

DR_B_D18

D

DR_B_D19

D

DR_B_D20

D

DR_B_D21

D

DR_B_D22

D

DR_B_D23

D

DR_B_D24

D

DR_B_D25

D

DR_B_D26

D

DR_B_D27

D

DR_B_D28

D

DR_B_D29

D

DR_B_D30

D

DR_B_D31

D

DR_B_D32

D

DR_B_D33

D

DR_B_D34

D

DR_B_D35

D

DR_B_D36

D

DR_B_D37

D

DR_B_D38

D

DR_B_D39

D

DR_B_D40

D

DR_B_D41

D

DR_B_D42

D

DR_B_D43

D

DR_B_D44

D

DR_B_D45

D

DR_B_D46

D

DR_B_D47

D

DR_B_D48

D

DR_B_D49

D

DR_B_D50

D

DR_B_D51

D

DR_B_D52

D

DR_B_D53

D

DR_B_D54

D

DR_B_D55

D

DR_B_D56

D

DR_B_D57

D

DR_B_D58

D

DR_B_D59

D

DR_B_D60

D

DR_B_D61

D

DR_B_D62

D

DR_B_D63

DR_B_BS0<12>

D

DR_B_BS1<12>

D

DR_B_BS2<12>

D

DR_B_CAS#<12>

D

DR_B_RAS#<12>

D

DR_B_WE#<12>

D

D10

K10

AM5
AM6
AR3

AP3
AN3
AN2
AN1

AP2

AP5
AN9

AT5

AT6

AP6
AN8
AR6
AR5
AR9

AJ11

AT8

AT9

AH11

AR8

AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

AA9

AA7

AA10

AB8

AB9

C9

B_DQ[0]

S

A7

B_DQ[1]

S

B_DQ[2]

S

C8

B_DQ[3]

S

A9

B_DQ[4]

S

A8

B_DQ[5]

S

D9

B_DQ[6]

S

D8

B_DQ[7]

S

G4

B_DQ[8]

S

F4

B_DQ[9]

S

F1

B_DQ[10]

S

G1

B_DQ[11]

S

G5

B_DQ[12]

S

F5

B_DQ[13]

S

F2

B_DQ[14]

S

G2

B_DQ[15]

S

J7

B_DQ[16]

S

J8

B_DQ[17]

S

B_DQ[18]

S

K9

B_DQ[19]

S

J9

B_DQ[20]

S

J10

B_DQ[21]

S

K8

B_DQ[22]

S

K7

B_DQ[23]

S

M5

B_DQ[24]

S

N4

B_DQ[25]

S

N2

B_DQ[26]

S

N1

B_DQ[27]

S

M4

B_DQ[28]

S

N5

B_DQ[29]

S

M2

B_DQ[30]

S

M1

B_DQ[31]

S

B_DQ[32]

S

B_DQ[33]

S

B_DQ[34]

S

B_DQ[35]

S

B_DQ[36]

S

B_DQ[37]

S

B_DQ[38]

S

B_DQ[39]

S

B_DQ[40]

S

B_DQ[41]

S

B_DQ[42]

S

B_DQ[43]

S

B_DQ[44]

S

B_DQ[45]

S

B_DQ[46]

S

B_DQ[47]

S

B_DQ[48]

S

B_DQ[49]

S

B_DQ[50]

S

B_DQ[51]

S

B_DQ[52]

S

B_DQ[53]

S

B_DQ[54]

S

B_DQ[55]

S

B_DQ[56]

S

B_DQ[57]

S

B_DQ[58]

S

B_DQ[59]

S

B_DQ[60]

S

B_DQ[61]

S

B_DQ[62]

S

B_DQ[63]

S

S

B_BS[0]

S

B_BS[1]

R6

S

B_BS[2]

S

B_CAS#

S

B_RAS#

S

B_WE#

2

AE2

S

B_CLK[0]

AD2

S

B_CLK#[0]

R9

S

B_CKE[0]

AE1

S

B_CLK[1]

AD1

S

B_CLK#[1]

R10

S

B_CKE[1]

AB2

SVD_TP[11]

R
R
R

R
R
R

R
R

R
R

DR SYSTEM MEMORY B

DR SYSTEM MEMORY B
D

D

SVD_TP[12]
SVD_TP[13]

SVD_TP[14]
SVD_TP[15]
SVD_TP[16]

B_CS#[0]

S

B_CS#[1]

S
SVD_TP[17]
SVD_TP[18]

S

B_ODT[0]

S

B_ODT[1]

SVD_TP[19]
SVD_TP[20]

S

B_DQS#[0]
S

B_DQS#[1]
S

B_DQS#[2]

B_DQS#[3]

S

S

B_DQS#[4]
S

B_DQS#[5]
S

B_DQS#[6]
S

B_DQS#[7]

S

B_DQS[0]

S

B_DQS[1]

S

B_DQS[2]

S

B_DQS[3]

S

B_DQS[4]

S

B_DQS[5]

S

B_DQS[6]

S

B_DQS[7]

B_MA[0]

S

B_MA[1]

S

B_MA[2]

S

B_MA[3]

S

B_MA[4]

S

B_MA[5]

S

B_MA[6]

S

B_MA[7]

S

B_MA[8]

S

B_MA[9]

S
B_MA[10]

S

B_MA[11]

S

B_MA[12]

S

B_MA[13]

S

B_MA[14]

S

B_MA[15]

S

AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4

AD5
AE5

D7
F3
K6

N3

AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

D

DR_B_DQS#0

D

DR_B_DQS#1

D

DR_B_DQS#2

D

DR_B_DQS#3

D

DR_B_DQS#4

D

DR_B_DQS#5

D

DR_B_DQS#6

D

DR_B_DQS#7

D

DR_B_DQS0

D

DR_B_DQS1

D

DR_B_DQS2

D

DR_B_DQS3

D

DR_B_DQS4

D

DR_B_DQS5

D

DR_B_DQS6

D

DR_B_DQS7

D

DR_B_MA0

D

DR_B_MA1

D

DR_B_MA2

D

DR_B_MA3

D

DR_B_MA4

D

DR_B_MA5

D

DR_B_MA6

D

DR_B_MA7

D

DR_B_MA8

D

DR_B_MA9

D

DR_B_MA10

D

DR_B_MA11

D

DR_B_MA12

D

DR_B_MA13

D

DR_B_MA14

D

DR_B_MA15

DRB_CLK0 <12>

D

DRB_CLK0# <12>

D

DRB_CKE0 <12>

D

DRB_CLK1 <12>

D

DRB_CLK1# <12>

D

DRB_CKE1 <12>

D

DRB_SCS0# <12>

D

DRB_SCS1# <12>

D

DRB_ODT0 <12>

D

DRB_ODT1 <12>

D

DR_B_DQS#[0..7] <12>

D

DR_B_DQS[0..7] <12>

D

DR_B_MA[0..15] <12>

D

1

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

Conn@

Conn@

1.5V

+

12

R

R

C76

C76

1K_0402_5%

1K_0402_5%

C3

C3

Q

Q

D

S

D

S

3

1

DR3_DRAMRST#_R

_DRAMRST#<5>

H

4.99K_0402_1%

A A

RAMRST_CNTRL_PCH<26,9>

D

5

4.99K_0402_1%

1 2

Rshort@

Rshort@

C73 0_0402_5%

C73 0_0402_5%

R

R

2

R

R

C78

C78

1

RAMRST_CNTRL

D

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

G

G

2

1

C

C

C37

C37

0.047U_0402_25V6K

0.047U_0402_25V6K

2

D

4

R

R

C77

C77

1K_0402_5%

1K_0402_5%

1 2

M_DRAMRST# <11,12>

S

ecurity Classification

ecurity Classification

ecurity Classification

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

012/12/07 2013/12/07

012/12/07 2013/12/07

012/12/07 2013/12/07

2

2

2

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

Conn@

Conn@

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

eciphered Date

eciphered Date

eciphered Date

D

D

D

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

itle

itle

itle

T

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

ustom

ustom

ustom

C

C

C

Date: Sheet

Date: Sheet

2

Date: Sheet

C

vy Bridge_DDR3

vy Bridge_DDR3

vy Bridge_DDR3

I

I

I

FKAA

FKAA

FKAA

V

V

V

.2

.2

.2

0

0

0

f

7 56Monday, March 11, 2013

f

7 56Monday, March 11, 2013

f

7 56Monday, March 11, 2013

o

o

1

o

5

CPU_CORE

+

J

J

CPUF

CPUF

53A

AG35

V

D D

C C

B B

A A

AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26

AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27

AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26

CC1

V

CC2

V

CC3

V

CC4

V

CC5

V

CC6

V

CC7

V

CC8

V

CC9

V

CC10

V

CC11

V

CC12

V

CC13

V

CC14

V

CC15

V

CC16

V

CC17

V

CC18

V

CC19

V

CC20

V

CC21

V

CC22

V

CC23

V

CC24

V

CC25

V

CC26

V

CC27

V

CC28

V

CC29

V

CC30

V

CC31

V

CC32

V

CC33

V

CC34

V

CC35

V

CC36

V

CC37

V

CC38

V

CC39

V

CC40

V

CC41

V

CC42

V

CC43

V

CC44

V

CC45

V

CC46

V

CC47

V

CC48

V

CC49

V

CC50

Y35

V

CC51

Y34

V

CC52

Y33

V

CC53

Y32

V

CC54

Y31

V

CC55

Y30

V

CC56

Y29

V

CC57

Y28

V

CC58

Y27

V

CC59

Y26

CC60

V

V35

CC61

V

V34

CC62

V

V33

CC63

V

V32

CC64

V

V31

CC65

V

V30

CC66

V

V29

CC67

V

V28

CC68

V

V27

CC69

V

V26

CC70

V

U35

CC71

V

U34

CC72

V

U33

CC73

V

U32

CC74

V

U31

CC75

V

U30

CC76

V

U29

CC77

V

U28

CC78

V

U27

CC79

V

U26

CC80

V

R35

CC81

V

R34

CC82

V

R33

CC83

V

R32

CC84

V

R31

CC85

V

R30

CC86

V

R29

CC87

V

R28

CC88

V

R27

CC89

V

R26

CC90

V

P35

CC91

V

P34

CC92

V

P33

CC93

V

P32

CC94

V

P31

CC95

V

P30

CC96

V

P29

CC97

V

P28

CC98

V

P27

CC99

V

P26

CC100

V

P

P

OWER

OWER

PEG AND DDR

PEG AND DDR

ORE SUPPLY

ORE SUPPLY
C

C

V

SS_SENSE_VCCIO

SENSE LINES SVID

SENSE LINES SVID

V

V

CCIO_SENSE

V

8.5A

CCIO1

V

CCIO2

V

CCIO3

V

CCIO4

V

CCIO5

V

CCIO6

V

CCIO7

V

CCIO8

V

CCIO9

V
CCIO10

V

CCIO11

V

CCIO12

V

CCIO13

V

CCIO14

V

CCIO15

V

CCIO16

V

CCIO17

V

CCIO18

V

CCIO19

V

CCIO20

V

CCIO21

V

CCIO22

V

CCIO23

V

CCIO24

V

CCIO25

V

CCIO26

V

CCIO27

V

CCIO28

V

CCIO29

V

CCIO30

V

CCIO31

V

CCIO32

V

CCIO33

V

CCIO34

V

CCIO35

V

CCIO36

V

CCIO37

V

CCIO38

V

CCIO39

V

CCIO40

V

V

IDALERT#

V

IDSCLK

V

IDSOUT

CC_SENSE
SS_SENSE

1.05VS_VCCP

+

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

AJ29
AJ30
AJ28

AJ35
AJ34

B10

A10

R

R

10_0402_1%

10_0402_1%

H

_CPU_SVIDALRT#

1

C96

C96

2

Close to CPU

TYCO_2013620-2_IVY BRIDGEConn@

TYCO_2013620-2_IVY BRIDGEConn@

5

4

1.05VS_VCCP

+

1

1

1

C17

C17

C18

C18

C19

C19
C

C

C

C

C

C

2

ESD@

ESD@

100P_0402_50V8J

100P_0402_50V8J

2

2

ESD@

ESD@

ESD@

ESD@

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

by ESD requestion and place near CPU

+

12

R

R

C98

C98

10_0402_1%

10_0402_1%

1.05VS_VCCP

1

R

R

C91

C91

130_0402_5%

130_0402_5%

2

R

R

C90 43_0402 _1%

C90 43_0402 _1%

V

CCIO_SENSE <49>

+

1.05VS_VCCP

4

1 2

+

1.05VS_VCCP

1

2

R

R

C89

C89

75_0402_5%

75_0402_5%

P

ull high resistor on VR side

+

CPU_CORE

2

R

R

C93

C93

100_0402_1%

100_0402_1%

1

12

R

R

C97

C97

100_0402_1%

100_0402_1%

V

R_SVID_ALRT# <51>

V

R_SVID_CLK <51>

V

R_SVID_DAT <51>

3

2

Close to CPU

V

CCSENSE <51>

V

SSSENSE <51>

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2

2

2

012/12/07 2013/12/07

012/12/07 2013/12/07

012/12/07 2013/12/07

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

2

1

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

I

I

I

vy Bridge_POWER-1

vy Bridge_POWER-1

vy Bridge_POWER-1

V

V

V

FKAA

FKAA

FKAA

1

o

o

o

f

8 56Monday, March 11, 2013

f

8 56Monday, March 11, 2013

f

8 56Monday, March 11, 2013

0

0

0

.2

.2

.2

5

+

GFX_CORE

CPUG

CPUG

J

J

33A

AT24

AXG1

V

AT23

AXG2

D D

C C

V

CCPLL Decoupling:

1X 10U, 1x 1U

2

1

Rshort@

+

1.8VS

B B

A A

Rshort@

C119 0_0805_5%

C119 0_0805_5%

R

R

10U_0603_6.3V6M

10U_0603_6.3V6M

C

C

C59

C59

+

1.8VS_VCCPLL

1

C

C

C60

C60

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

V

AT21

AXG3

V

AT20

AXG4

V

AT18

AXG5

V

AT17

AXG6

V

AR24

AXG7

V

AR23

AXG8

V

AR21

AXG9

V

AR20

AXG10

V

AR18

AXG11

V

AR17

AXG12

V

AP24

AXG13

V

AP23

AXG14

V

AP21

AXG15

V

AP20

AXG16

V

AP18

AXG17

V

AP17

AXG18

V

AN24

AXG19

V

AN23

AXG20

V

AN21

AXG21

V

AN20

AXG22

V

AN18

AXG23

V

AN17

AXG24

V

AM24

AXG25

V

AM23

AXG26

V

AM21

AXG27

V

AM20

AXG28

V

AM18

AXG29

V

AM17

AXG30

V

AL24

AXG31

V

AL23

AXG32

V

AL21

AXG33

V

AL20

AXG34

V

AL18

AXG35

V

AL17

AXG36

V

AK24

AXG37

V

AK23

AXG38

V

AK21

AXG39

V

AK20

AXG40

V

AK18

AXG41

V

AK17

AXG42

V

AJ24

AXG43

V

AJ23

AXG44

V

AJ21

AXG45

V

AJ20

AXG46

V

AJ18

AXG47

V

AJ17

AXG48

V

AH24

AXG49

V

AH23

AXG50

V

AH21

AXG51

V

AH20

AXG52

V

AH18

AXG53

V

AH17

AXG54

V

1.2A

B6

CCPLL1

V

A6

CCPLL2

V

A2

CCPLL3

V

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

Conn@

Conn@

4

OWER

OWER

P

P

ENSE

ENSE
S

S

S

REFMISC

REFMISC

S

V

V

RAPHICS

RAPHICS
G

G

DDR3 -1.5V RAILS

DDR3 -1.5V RAILS

A RAIL

A RAIL
S

S

.8V RAIL

.8V RAIL
1

1

AXG_SENSE

V

SSAXG_SENSE

V

LINES

LINES

M_VREF

S

A_DIMM_VREFDQ
B_DIMM_VREFDQ

5

A

DDQ1

V

DDQ2

V

DDQ3

V

DDQ4

V

DDQ5

V

DDQ6

V

DDQ7

V

DDQ8

V

DDQ9

V

DDQ10

V

DDQ11

V

DDQ12

V

DDQ13

V

DDQ14

V

DDQ15

V

6A

CCSA1

V

CCSA2

V

CCSA3

V

CCSA4

V

CCSA5

V

CCSA6

V

CCSA7

V

CCSA8

V

CCSA_SENSE

V

CCSA_VID[0]

V

CCSA_VID[1]

V

CCIO_SEL

V

AK35
AK34

+

V_SM_VREF should

have 20 mil trace width

AL1

B4
D1

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

+

V_SM_VREF

+

VREF_DQA_M3

+

VREF_DQB_M3

C

C

C57

C57

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

Bottom Socket Cavity

M27

10U_0603_6.3V6M

10U_0603_6.3V6M

M26
L26
J26
J25
J24
H26
H25

H23

C22
C24

A19

1

C

C

C42

C42

2

10U_0603_6.3V6M

10U_0603_6.3V6M

C

C

C41

C41

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

C

C

H

_VCCSA_VID0 < 50>

H

_VCCSA_VID1 < 50>

3

GFX_CORE

+

12

R

R

C105

C105

10_0402_1%

10_0402_1%

1

R

R

C106

C106

10_0402_1%

10_0402_1%

1

C

C

C65

C65

0.1U_0402_10V7K

0.1U_0402_10V7K

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

1

C52

C52

C55

C55

C

C

C

C

C

C

C51

C51

10U_0603_6.3V6M

10U_0603_6.3V6M

2

+

C

C

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

VCCSA Decoupling:

1X 47U (MLCC), 3X 10U

+

VCCSA

1

C43

C43

2

Bottom Socket Edge

1

C

C

C44

C44

47U_0805_6.3V6M

47U_0805_6.3V6M

@

@

2

P

lease kindly ch eck whether
there is pull-d own resister
in PWR-side or HW-side

1

0/3: confirmed with PWR, IC in tergrate PD

Close to CPU

2

+

R

R

C120

C120

1 2

1K_0402_0.5%

1K_0402_0.5%

1 2

1K_0402_0.5%

1K_0402_0.5%
R

R

C109

C109

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C

C

C54

C54

C56

C56

2

+

1.5V_CPU

C

C

C46 0.1U_0402_10V7K

C46 0.1U_0402_10V7K

C47 0.1U_0402_10V7K

C47 0.1U_0402_10V7K

C

C

C48 0.1U_0402_10V7K

C48 0.1U_0402_10V7K

C

C

C45 0.1U_0402_10V7K

C45 0.1U_0402_10V7K

C

C

V

CC_AXG_SENSE <51>

V

SS_AXG_SENSE <51>

1.5V_CPU

+

1.5V_CPU

1

12

C

C

C50

C50

47U_0805_6.3V6M

47U_0805_6.3V6M

@

@

2

1 2

@

@

1 2

@

@

1 2

@

@

1 2

@

@

2

ntel DDR Vref M3

I

+

VREF_DQA_M3

+

VREF_DQB_M3

+1.5V_CPU Decoupling:
1X 47U (MLCC), 6X 10U

0

0

1

1 1

+

1.5V

V

gs=10V,Id=14.5A ,Rds=6mohm

2

R

R

C203

C203

470_0805_5%

470_0805_5%

1

3

C5B

C5B

Q

Q

5

S

USP

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

1

C68

C68

C

C
10U_0603_6.3V6M

10U_0603_6.3V6M

2

0.1U_0402_25V6

0.1U_0402_25V6

Place near SO-DIMM side

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

S

S

3

G

G

2

G

G

2

3

S

S

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

+VCCSAVCCSA_VID0 VCCSA_VID1

0

1

0

0.90 V

0.80 V

0.725 V

0.675 V

+

1.5V_CPU

C

C

C69

C69

2

JUMP_43X39

JUMP_43X39

C4

C4

Q

Q

1

S

2

S

3

S

4

G

FDS6676AS_SO8

FDS6676AS_SO8

1

2

JP@

JP@

J1

J1

P

P

2

1

D
D
D
D

R

UN_ON_CPU1.5VS3

12

R

R

C205

C205

820K_0402_5%

820K_0402_5%

1

Q

Q

C7

C7

D

D

1

1

D

D

Q

Q

C8

C8

V

REF traces should be at least
20 mils wide and 20 mils spacing
to other signals/planes.

+

VREF_DQA

D

RAMRST_CNTRL_PCH < 26,7>

+

VREF_DQB

For Sandy Bridge

+

1.5VS

1

+

1.5V

8
7
6
5

R

R

C204

C204

1 2

220K_0402_5%

220K_0402_5%

6

C5A

C5A

Q

Q

2

S

USP

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

1

B

+

S

USP <43>

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2

2

2

012/12/07 2013/12/07

012/12/07 2013/12/07

012/12/07 2013/12/07

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

I

I

I

vy Bridge_POWER-2

vy Bridge_POWER-2

vy Bridge_POWER-2

V

V

V

FKAA

FKAA

FKAA

1

0

0

0

.2

.2

.2

o

o

o

f

9 56Monday, March 11, 2013

f

9 56Monday, March 11, 2013

f

9 56Monday, March 11, 2013

5

CPUI

CPUI

J

CPUH

CPUH

J

J

AT35

V

SS1

AT32

V

SS2

AT29

V

SS3

AT27

V

SS4

AT25

V

SS5

AT22

V

SS6

AT19

V

SS7

AT16

V

SS8

AT13

V

SS9

AT10

V

SS10

AT7

V

SS11

AT4

D D

C C

B B

V

SS12

AT3

V

SS13

AR25

V

SS14

AR22

V

SS15

AR19

V

SS16

AR16

V

SS17

AR13

V

SS18

AR10

V

SS19

AR7

V

SS20

AR4

V

SS21

AR2

V

SS22

AP34

V

SS23

AP31

V

SS24

AP28

V

SS25

AP25

V

SS26

AP22

V

SS27

AP19

V

SS28

AP16

V

SS29

AP13

V

SS30

AP10

V

SS31

AP7

V

SS32

AP4

V

SS33

AP1

V

SS34

AN30

V

SS35

AN27

V

SS36

AN25

V

SS37

AN22

V

SS38

AN19

V

SS39

AN16

V

SS40

AN13

V

SS41

AN10

V

SS42

AN7

V

SS43

AN4

V

SS44

AM29

V

SS45

AM25

V

SS46

AM22

V

SS47

AM19

V

SS48

AM16

V

SS49

AM13

V

SS50

AM10

V

SS51

AM7

V

SS52

AM4

V

SS53

AM3

V

SS54

AM2

V

SS55

AM1

V

SS56

AL34

V

SS57

AL31

V

SS58

AL28

V

SS59

AL25

V

SS60

AL22

V

SS61

AL19

V

SS62

AL16

V

SS63

AL13

V

SS64

AL10

V

SS65

AL7

V

SS66

AL4

V

SS67

AL2

V

SS68

AK33

V

SS69

AK30

V

SS70

AK27

V

SS71

AK25

V

SS72

AK22

V

SS73

AK19

V

SS74

AK16

V

SS75

AK13

V

SS76

AK10

V

SS77

AK7

V

SS78

AK4

V

SS79

AJ25

V

SS80

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

Conn@

Conn@

V

V

SS

SS

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

V

SS100
SS101
SS102
SS103
SS104
SS105
SS106
SS107
SS108
SS109
SS110
SS111
SS112
SS113
SS114
SS115
SS116
SS117
SS118
SS119
SS120
SS121
SS122
SS123
SS124
SS125
SS126
SS127
SS128
SS129
SS130
SS131
SS132
SS133
SS134
SS135
SS136
SS137
SS138
SS139
SS140
SS141
SS142
SS143
SS144
SS145
SS146
SS147
SS148
SS149
SS150
SS151
SS152
SS153
SS154
SS155
SS156
SS157
SS158
SS159
SS160

SS81
SS82
SS83
SS84
SS85
SS86
SS87
SS88
SS89
SS90
SS91
SS92
SS93
SS94
SS95
SS96
SS98

SS99

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25

AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

J

T35

V

SS161

T34

V

SS162

T33

V

SS163

T32

V

SS164

T31

V

SS165

T30

V

SS166

T29

V

SS167

T28

V

SS168

T27

V

SS169

T26

V

SS170

P9

V

SS171

P8

V

SS172

P6

V

SS173

P5

V

SS174

P3

V

SS175

P2

V

SS176

N35

V

SS177

N34

V

SS178

N33

V

SS179

N32

V

SS180

N31

V

SS181

N30

V

SS182

N29

V

SS183

N28

V

SS184

N27

V

SS185

N26

V

SS186

M34

V

SS187

L33

V

SS188

L30

V

SS189

L27

V

SS190

L9

V

SS191

L8

V

SS192

L6

V

SS193

L5

V

SS194

L4

V

SS195

L3

V

SS196

L2

V

SS197

L1

V

SS198

K35

V

SS199

K32

V

SS200

K29

V

SS201

K26

V

SS202

J34

V

SS203

J31

V

SS204

H33

V

SS205

H30

V

SS206

H27

V

SS207

H24

V

SS208

H21

V

SS209

H18

V

SS210

H15

V

SS211

H13

V

SS212

H10

V

SS213

H9

V

SS214

H8

V

SS215

H7

V

SS216

H6

V

SS217

H5

V

SS218

H4

V

SS219

H3

V

SS220

H2

V

SS221

H1

V

SS222

G35

V

SS223

G32

V

SS224

G29

V

SS225

G26

V

SS226

G23

V

SS227

G20

V

SS228

G17

V

SS229

G11

V

SS230

F34

V

SS231

F31

V

SS232

F29

V

SS233

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

Conn@

Conn@

4

F22

V

SS234

F19

V

SS235

E30

V

SS236

E27

V

SS237

E24

V

SS238

E21

V

SS239

E18

V

SS240

E15

V

SS241

E13

V

SS242

E10

V

SS243

E9

V

SS244

E8

V

SS245

E7

V

SS246

E6

V

SS247

E5

V

SS248

E4

V

SS249

E3

V

SS250

E2

V

SS251

E1

V

SS252

D35

V

SS253

D32

V

SS254

D29

V

SS255

D26

V

SS256

D20

V

SS257

D17

V

SS258

C34

V

SS259

C31

V

SS260

C28

V

SS261

C27

V

SS262

C25

V

SS263

C23

V

SS264

C10

V

SS265

C1

V

SS266

B22

V

SS267

B19

V

SS268

V

V

SS

SS

V
V
V
V
V
V
V
V

V
V
V
V
V
V
V
V
V

SS269
SS270
SS271
SS272
SS273
SS274
SS275
SS276

SS277
SS278
SS279
SS280
SS281
SS282
SS283
SS284
SS285

B17
B15
B13
B11
B9
B8
B7
B5

B3
B2
A35
A32
A29
A26
A23
A20
A3

T

14 PADT14 PAD
20 PADT20 PAD

T

23 PADT23 PAD

T

T

18 PADT18 PAD

T

22 PADT22 PAD

T

21 PADT21 PAD

24 PADT24 PAD

T

25 PADT25 PAD

T

3

CPUE

CPUE

J

J

V

ESERVED

ESERVED
R

R

CC_DIE_SENSE

V

SS_DIE_SENSE

SVD28

R
R

SVD29

R

SVD30

R

SVD31

R

SVD32

SVD33

R

SVD34

R

SVD35

R

SVD37

R

SVD38

R

SVD39

R

SVD40

R

SVD_NCTF1

R

SVD_NCTF2

R

SVD_NCTF3

R

SVD_NCTF4

R

SVD_NCTF5

R

SVD_NCTF6

R

SVD_NCTF7

R

SVD_NCTF8

R

SVD_NCTF9

R
SVD_NCTF10

R

SVD51

R

SVD52

R

B

CLK_ITP

B

CLK_ITP#

SVD_NCTF11

R

SVD_NCTF12

R

SVD_NCTF13

R

K

EY

AK28

FG[0]

C

AK29

FG[1]

C

C

FG2

C

FG4

C

FG5

C

FG6

C

FG7

C

FG10

C

FG11

C

FG12

C

FG13

C

FG14

C

FG15

C

FG16

C

FG17

AL26

FG[2]

C

AL27

FG[3]

C

AK26

FG[4]

C

AL29

FG[5]

C

AL30

FG[6]

C

AM31

FG[7]

C

AM32

FG[8]

C

AM30

FG[9]

C

AM28

FG[10]

C

AM26

FG[11]

C

AN28

FG[12]

C

AN31

FG[13]

C

AN26

FG[14]

C

AM27

FG[15]

C

AK31

FG[16]

C

AN29

FG[17]

C

AJ31

V

AXG_VAL_SENSE

AH31

SSAXG_VAL_SENSE

V

AJ33

V

CC_VAL_SENSE

AH33

V

SS_VAL_SENSE

AJ26

SVD5

R

F25

SVD8

R

F24

SVD9

R

F23

SVD10

R

D24

SVD11

R

G25

SVD12

R

G24

SVD13

R

E23

SVD14

R

D23

SVD15

R

C30

SVD16

R

A31

SVD17

R

B30

SVD18

R

B29

SVD19

R

D30

SVD20

R

B31

SVD21

R

A30

SVD22

R

C29

SVD23

R

J20

R

SVD24

B18

R

SVD25

J15

SVD27

R

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

Conn@

Conn@

FG

FG
C

C

2

AH27
AH26

L7
AG7
AE7
AK2

W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AN35
AM35

AT2
AT1
AR1

B1

T

3PADT3PAD

P

EG Static Lane Reversal - CFG2 is for the 16x

CFG2

E

mbedded Display Port Presence Strap

CFG4

T

64PADT64PAD

P

CIE Port Bifurcation Straps

C

FG[6:5]

1

FG Straps for Processor

C

CFG[17:0] internal pull high 5~15K to VCCIO)

(

C

FG2

1

: Normal Operation; Lane # definition matches

*

socket pin map definition

12

C79

C79

R

R
1K_0402_1%

1K_0402_1%

@

@

0:Lane Reversed

C

FG4

1 : Disabled; No Physical Display Port

*

attached to Embedded Display Port

0

: Enabled; An external Display Port device is

connected to the Embedded Display Port

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

1

0: x8, x8 - Device 1 function 1 enabled ; function 2

disabled
01: Reserved - (Device 1 function 1 disabled ; function

2 enabled)
0

0: x8,x4,x4 - Device 1 functions 1 and 2 enabled

C

FG6

C

FG5

C

FG7

R

R

1K_0402_1%

1K_0402_1%

12

C83

C83

@

@

R

R

C82

C82
1K_0402_1%

1K_0402_1%

IEDP@

IEDP@

12

12

12

C85

C85

R

R
1K_0402_1%

1K_0402_1%

@

@

C84

C84

R

R
1K_0402_1%

1K_0402_1%

@

@

P

EG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB
de assertion

C

FG7

A A

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

2

2

012/12/07 2013/12/07

012/12/07 2013/12/07

012/12/07 2013/12/07

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

0: PEG Wait for BIOS for training

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

I

I

I

vy Bridge_GND/RSVD/CFG

vy Bridge_GND/RSVD/CFG

vy Bridge_GND/RSVD/CFG

V

V

V

FKAA

FKAA

FKAA

1

10 56Monday, March 11, 2013

0

0

0

.2

.2

.2

o

o

o

f

10 56Monday, March 11, 2013

f

10 56Monday, March 11, 2013

f

5

4

3

2

1

+

1.5V

DDR3L

DDR3L

J

J

+

VREF_DQA

D1

D1

C

C

0

0
.1U_0402_10V7K

.1U_0402_10V7K

D D

C

lose to JDDR3L.1

D

DRA_CKE0<7>

C C

B B

A A

+

3VS

D

DR_A_BS2<7>

D

DRA_CLK0<7>

D

DRA_CLK0#<7>

D

DR_A_BS0<7>

D

DR_A_WE#<7>

D

DR_A_CAS#<7>

D

DRA_SCS1#<7>

0.1U_0402_10V7K

0.1U_0402_10V7K

D

DR_A_D0

D

1

2

DR_A_D1

D

DR_A_D2

D

DR_A_D3

D

DR_A_D8

D

DR_A_D9

D

DR_A_DQS#1

D

DR_A_DQS1

D

DR_A_D10

D

DR_A_D11

D

DR_A_D16

D

DR_A_D17

D

DR_A_DQS#2

D

DR_A_DQS2

D

DR_A_D18

D

DR_A_D19

D

DR_A_D24

D

DR_A_D25

D

DR_A_D26

D

DR_A_D27

D

DR_A_MA12

D

DR_A_MA9

D

DR_A_MA8

D

DR_A_MA5

D

DR_A_MA3

D

DR_A_MA1

D

DR_A_MA10

D

DR_A_MA13

D

DR_A_D32

D

DR_A_D33

D

DR_A_DQS#4

D

DR_A_DQS4

D

DR_A_D34

D

DR_A_D35

D

DR_A_D40

D

DR_A_D41

D

DR_A_D42

D

DR_A_D43

D

DR_A_D48

D

DR_A_D49

D

DR_A_DQS#6

D

DR_A_DQS6

D

DR_A_D50

D

DR_A_D51

D

DR_A_D56

D

DR_A_D57

D

DR_A_D58

D

DR_A_D59

1

D26

D26

C

C

2

S

PD setting (SA0 , SA1)

PU/PD by Channe l A/B

->Channel A 00

->Channel B 01

5

+

0.75VS

1

REF_DQ

V

3

SS2

V

5

Q0

D

7

Q1

D

9

SS4

V

11

M0

D

13

SS5

V

15

Q2

D

17

Q3

D

19

SS7

V

21

Q8

D

23

Q9

D

25

SS9

V

27

QS#1

D

29

QS1

D

31

SS11

V

33

Q10

D

35

Q11

D

37

SS13

V

39

Q16

D

41

Q17

D

43

SS15

V

45

QS#2

D

47

QS2

D

49

SS18

V

51

Q18

D

53

Q19

D

55

SS20

V

57

Q24

D

59

Q25

D

61

SS22

V

63

D

M3

65

V

SS23

67

D

Q26

69

D

Q27

71

V

SS25

73

C

KE0

75

V

DD1

77

N

C1

79

B

A2

81

V

DD3

83

A

12/BC#

85

A

9

87

V

DD5

89

A

8

91

A

5

93

V

DD7

95

A

3

97

A

1

99

V

DD9

101

C

K0

103

C

K0#

105

V

DD11

107

A

10/AP

109

B

A0

111

V

DD13

113

W

E#

115

C

AS#

117

V

DD15

119

A

13

121

S

1#

123

V

DD17

125

N

CTEST

127

V

SS27

129

D

Q32

131

D

Q33

133

V

SS29

135

D

QS#4

137

D

QS4

139

V

SS32

141

D

Q34

143

D

Q35

145

V

SS34

147

D

Q40

149

D

Q41

151

V

SS36

153

D

M5

155

V

SS37

157

D

Q42

159

D

Q43

161

V

SS39

163

D

Q48

165

D

Q49

167

V

SS41

169

D

QS#6

171

D

QS6

173

V

SS44

175

D

Q50

177

D

Q51

179

V

SS46

181

D

Q56

183

D

Q57

185

V

SS48

187

D

M7

189

V

SS49

191

D

Q58

193

D

Q59

195

V

SS51

197

S

A0

199

V

DDSPD

201

S

A1

203

V

TT1

205

G

1

LCN_DAN06-K4406-0102

LCN_DAN06-K4406-0102
Conn@

Conn@

R

V

REF_CA

E

D

D

D
D

V

ESET#
V

D
D

V

D
D

V

V

D
D

V

D

D
V
D

D
V

D

D
V

C

V

V

V

V

V

V

R
V

O
V

O

V

V

D

D
V

V

D

D
V

D

D
V
D

D
V

D

D
V

D

D
V

V

D

D
V

D

D
V
D

D
V

D

D
V
VENT#

SS1

V

D
D
SS3

V
QS#0

QS0
SS6

V

D
D
SS8

V

Q12
Q13

SS10

D

SS12

Q14
Q15

SS14

Q20
Q21

SS16

D

SS17

Q22
Q23

SS19

Q28

Q29
SS21
QS#3

QS3
SS24

Q30

Q31
SS26

KE1

DD2

DD4

DD6

DD8

DD10

C
C
DD12

B

AS#
DD14

DT0
DD16

DT1

N
DD18

SS28

Q36

Q37
SS30

D
SS31

Q38

Q39
SS33

Q44

Q45
SS35
QS#5

QS5
SS38

Q46

Q47
SS40

Q52

Q53
SS42

D
SS43

Q54

Q55
SS45

Q60

Q61
SS47
QS#7

QS7
SS50

Q62

Q63
SS52

S

S
V

+

1.5V

2
4

D

Q4
Q5

Q6
Q7

M1

M2

A

15

A

14

A

11

A

7

A

6

A

4

A

2

A

0

K1

K1#

A1

S

0#

C2

M4

M6

DA
CL

TT2

G

2

DR_A_D4

6

D

DR_A_D5

8
10

D

DR_A_DQS#0

12

D

DR_A_DQS0

14
16

D

DR_A_D6

18

D

DR_A_D7

20
22

D

DR_A_D12

24

D

DR_A_D13

26
28
30
32
34

D

DR_A_D14

36

D

DR_A_D15

38
40

D

DR_A_D20

42

D

DR_A_D21

44
46
48
50

D

DR_A_D22

52

D

DR_A_D23

54
56

D

DR_A_D28

58

D

DR_A_D29

60
62

D

DR_A_DQS#3

64

D

DR_A_DQS3

66
68

D

DR_A_D30

70

D

DR_A_D31

72

74
76
78

D

DR_A_MA15

80

D

DR_A_MA14

82
84

D

DR_A_MA11

86

D

DR_A_MA7

88
90

D

DR_A_MA6

92

D

DR_A_MA4

94
96

D

DR_A_MA2

98

D

DR_A_MA0

100
102
104
106
108
110
112
114
116
118
120
122
124
126

+

VREF_CAA

128
130

D

DR_A_D36

132

D

DR_A_D37

134
136
138
140

D

DR_A_D38

142

D

DR_A_D39

144
146

D

DR_A_D44

148

D

DR_A_D45

150
152

D

DR_A_DQS#5

154

D

DR_A_DQS5

156
158

D

DR_A_D46

160

D

DR_A_D47

162
164

D

DR_A_D52

166

D

DR_A_D53

168
170
172
174

D

DR_A_D54

176

D

DR_A_D55

178
180

D

DR_A_D60

182

D

DR_A_D61

184
186

D

DR_A_DQS#7

188

D

DR_A_DQS7

190
192

D

DR_A_D62

194

D

DR_A_D63

196
198
200
202
204

+

0.75VS

206

4

DDR3 SO-DIMM A

tandard Type

S

S

M_DRAMRST# <12,7>

D

DRA_CKE1 <7>

D

DRA_CLK1 <7>

D

DRA_CLK1# <7>

D

DR_A_BS1 <7>

D

DR_A_RAS# <7>

D

DRA_SCS0# <7>

D

DRA_ODT0 <7>

D

DRA_ODT1 <7>

1

D16

D16

C

C

0

0
.1U_0402_10V7K

.1U_0402_10V7K

2

close to JDDR3L.126

P

M_SMBDATA <12,26,35,42>

P

M_SMBCLK <12,26,35,42>

D

DR_A_DQS[0..7] <7>

D

DR_A_DQS#[0..7] <7>

D

DR_A_D[0..63] <7>

D

DR_A_MA[0..15] <7>

1.5V

+

1

D1

D1

R

R

1K_0402_1%

1K_0402_1%

eciphered Date

eciphered Date

eciphered Date

D

D

D

2

12

D2

D2

R

R

1K_0402_1%

1K_0402_1%

Layout Note: Place these 4 Caps near
Command and Control signals of DIMMA

+

1.5V

1 2

D20 0.1U_0402_10V7K

D20 0.1U_0402_10V7K

C

C

2

1

D17 0.1U_0402_10V7K

D17 0.1U_0402_10V7K

C

C

1 2

D18 0.1U_0402_10V7K

D18 0.1U_0402_10V7K

C

C

1 2

D19 0.1U_0402_10V7K

D19 0.1U_0402_10V7K

C

C

2

VREF_DQA

+

+

1.5V

12

D6

D6

R

R

1K_0402_1%

1K_0402_1%

12

D7

D7

R

R

1K_0402_1%

1K_0402_1%

L

ayout Note:

Place near JDDRL

+

1.5V

1 2

D8 10U_0603_6.3V6M

D8 10U_0603_6.3V6M

C

C

2

1

D9 10U_0603_6.3V6M

D9 10U_0603_6.3V6M

C

C

1 2

D10 10U_0603_6.3V6M

C

C

D10 10U_0603_6.3V6M

1 2

D11 10U_0603_6.3V6M

D11 10U_0603_6.3V6M

C

C

1 2

D12 10U_0603_6.3V6M

D12 10U_0603_6.3V6M

C

C

1 2

D13 10U_0603_6.3V6M

D13 10U_0603_6.3V6M

C

C

ecurity Classification

ecurity Classification

ecurity Classification

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

012/12/07 2013/12/07

012/12/07 2013/12/07

012/12/07 2013/12/07

2

2

2

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

Layout Note:
Place near JDDRL1.203 a nd 204

+

0.75VS

2

1

D24 1U_0402_6.3V6K

D24 1U_0402_6.3V6K

C

C

12

C

C

D21 1U_0402_6.3V6K

D21 1U_0402_6.3V6K

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

Title

itle

itle

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

ustom

ustom

ustom

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

C

DRIII-SODIMM0

DRIII-SODIMM0

DRIII-SODIMM0

D

D

D

FKAA

FKAA

FKAA

V

V

V

f

11 56Monday, March 11, 2013

f

11 56Monday, March 11, 2013

f

11 56Monday, March 11, 2013

o

o

1

o

.2

.2

.2

0

0

0

A

B

C

D

E

D

D

QS3

DD2

DD4

DD6

DD8

N

D

QS5

D

QS7

S

SS1
D
D
SS3

QS0
SS6
D
D
SS8
Q12
Q13

Q14
Q15

Q20
Q21

Q22
Q23

Q28
Q29

Q30
Q31

KE1

A
A

A

C
K1#

B
AS#

S
DT0

DT1

Q36
Q37

Q38
Q39

Q44
Q45

Q46
Q47

Q52
Q53

Q54
Q55

Q60
Q61

Q62
Q63

S
TT2

+

1.5V

2
4

D

Q4
Q5

Q6
Q7

M1

M2

15
14

11
A

7

A

6

A

4

A

2

A

0

K1

A1

0#

C2

M4

M6

DA
CL

G

2

DR_B_D4

6

D

DR_B_D5

8
10

D

DR_B_DQS#0

12

D

DR_B_DQS0

14
16

D

DR_B_D6

18

D

DR_B_D7

20
22

D

DR_B_D12

24

D

DR_B_D13

26
28
30
32
34

D

DR_B_D14

36

D

DR_B_D15

38
40

D

DR_B_D20

42

D

DR_B_D21

44
46
48
50

D

DR_B_D22

52

D

DR_B_D23

54
56

D

DR_B_D28

58

D

DR_B_D29

60
62

D

DR_B_DQS#3

64

D

DR_B_DQS3

66
68

D

DR_B_D30

70

D

DR_B_D31

72

74
76
78

D

DR_B_MA15

80

D

DR_B_MA14

82
84

D

DR_B_MA11

86

D

DR_B_MA7

88
90

D

DR_B_MA6

92

D

DR_B_MA4

94
96

D

DR_B_MA2

98

D

DR_B_MA0

100
102
104
106
108
110
112
114
116
118
120
122
124
126

+

VREF_CAB

128
130

D

DR_B_D36

132

D

DR_B_D37

134
136
138
140

D

DR_B_D38

142

D

DR_B_D39

144
146

D

DR_B_D44

148

D

DR_B_D45

150
152

D

DR_B_DQS#5

154

D

DR_B_DQS5

156
158

D

DR_B_D46

160

D

DR_B_D47

162
164

D

DR_B_D52

166

D

DR_B_D53

168
170
172
174

D

DR_B_D54

176

D

DR_B_D55

178
180

D

DR_B_D60

182

D

DR_B_D61

184
186

D

DR_B_DQS#7

188

D

DR_B_DQS7

190
192

D

DR_B_D62

194

D

DR_B_D63

196
198
200
202
204

+

206

0.75VS

B

D

DRB_CKE1 <7>

D

DRB_CLK1 <7>

D

DRB_CLK1# <7>

D

DR_B_BS1 <7>

D

DR_B_RAS# <7>

D

DRB_SCS0# <7>

D

DRB_ODT0 <7>

D

DRB_ODT1 <7>

C

C

Close to JDDR3H.126

P

M_SMBDATA <11,26,35,42>

P

M_SMBCLK <11,26,35,42>

DDR3 SO-DIMM B
S

tandard Type

S

M_DRAMRST# <11,7>

D47

D47

1

0

0
.1U_0402_10V7K

.1U_0402_10V7K

2

D

DR_B_DQS#[0..7] <7>

D

DR_B_DQS[0..7] <7>

D

DR_B_D[0..63] <7>

D

DR_B_MA[0..15] <7>

1.5V

+

12

D10

D10

R

R

1K_0402_1%

1K_0402_1%

VREF_DQB

+

+

1.5V

1

D12

D12

R

R

1K_0402_1%

1K_0402_1%

2

12

D13

D13

R

R

1K_0402_1%

1K_0402_1%

L

ayout Note:

Place near JDDRH

+

1.5V

ecurity Classification

ecurity Classification

ecurity Classification

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

012/12/07 2013/12/07

012/12/07 2013/12/07

012/12/07 2013/12/07

2

2

2

2

1

D31 47U_0805_6.3V6M

D31 47U_0805_6.3V6M

C

C

1 2

D41 10U_0603_6.3V6M

D41 10U_0603_6.3V6M

C

C

1 2

D36 10U_0603_6.3V6M

D36 10U_0603_6.3V6M

C

C

1 2

D37 10U_0603_6.3V6M

D37 10U_0603_6.3V6M

C

C

1 2

C

C

D38 10U_0603_6.3V6M

D38 10U_0603_6.3V6M

1 2

D39 10U_0603_6.3V6M

D39 10U_0603_6.3V6M

C

C

1 2

D40 10U_0603_6.3V6M

D40 10U_0603_6.3V6M

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

eciphered Date

eciphered Date

eciphered Date

D

D

D

1

D11

D11

R

R

1K_0402_1%

1K_0402_1%

2

Layout Note: Place these 4 Caps near
Command and Control signals of DIMMB

+

1.5V

1 2

D33 0.1U_0402_10V7K

D33 0.1U_0402_10V7K

C

C

1 2

D29 0.1U_0402_10V7K

D29 0.1U_0402_10V7K

C

C

2

1

D30 0.1U_0402_10V7K

D30 0.1U_0402_10V7K

C

C

1 2

D32 0.1U_0402_10V7K

D32 0.1U_0402_10V7K

C

C

D

Layout Note:
Place near JDDRH.203 and 2 04

+

0.75VS

12

D45 1U_0402_6.3V6K

D45 1U_0402_6.3V6K

C

C

2

1

D42 1U_0402_6.3V6K

D42 1U_0402_6.3V6K

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

itle

itle

itle

T

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

ustom

ustom

ustom

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

C

DRIII-SODIMM1

DRIII-SODIMM1

DRIII-SODIMM1

D

D

D

FKAA

FKAA

FKAA

V

V

V

f

12 56Monday, March 11, 2013

f

12 56Monday, March 11, 2013

f

12 56Monday, March 11, 2013

o

o

E

o

.2

.2

.2

0

0

0

+

1.5V

DDR3H

DDR3H

J

J

+

VREF_DQB

D27

D27

C

C

0

0
.1U_0402_10V7K

1 1

2 2

3 3

+

3VS

4 4

.1U_0402_10V7K

C

lose to JDDR3H.1

D

DRB_CKE0<7>

D

DR_B_BS2<7>

D

DRB_CLK0<7>

D

DRB_CLK0#<7>

D

DR_B_BS0<7>

D

DR_B_WE#<7>

D

DR_B_CAS#<7>

D

DRB_SCS1#<7>

1

D49

D49

C

C

2

0.1U_0402_10V7K

0.1U_0402_10V7K

D

DR_B_D0

D

DR_B_D1

1

D

DR_B_D2

2

D

DR_B_D3

D

DR_B_D8

D

DR_B_D9

D

DR_B_DQS#1

D

DR_B_DQS1

D

DR_B_D10

D

DR_B_D11

D

DR_B_D16

D

DR_B_D17

D

DR_B_DQS#2

D

DR_B_DQS2

D

DR_B_D18

D

DR_B_D19

D

DR_B_D24

D

DR_B_D25

D

DR_B_D26

D

DR_B_D27

D

DR_B_MA12

D

DR_B_MA9

D

DR_B_MA8

D

DR_B_MA5

D

DR_B_MA3

D

DR_B_MA1

D

DR_B_MA10

D

DR_B_MA13

D

DR_B_D32

D

DR_B_D33

D

DR_B_DQS#4

D

DR_B_DQS4

D

DR_B_D34

D

DR_B_D35

D

DR_B_D40

D

DR_B_D41

D

DR_B_D42

D

DR_B_D43

D

DR_B_D48

D

DR_B_D49

D

DR_B_DQS#6

D

DR_B_DQS6

D

DR_B_D50

D

DR_B_D51

D

DR_B_D56

D

DR_B_D57

D

DR_B_D58

D

DR_B_D59

2

1

D15 10K_0402_5%

D15 10K_0402_5%

R

R

S

PD setting (SA0 , SA1)

PU/PD by Channe l A/B

->Channel A 00

->Channel B 01

A

+

0.75VS

1

REF_DQ

V

3

SS2

V

5

Q0

D

7

Q1

D

9

SS4

V

11

M0

D

13

SS5

V

15

Q2

D

17

Q3

D

19

SS7

V

21

Q8

D

23

Q9

D

25

SS9

V

27

QS#1

D

29

QS1

D

31

SS11

V

33

Q10

D

35

Q11

D

37

SS13

V

39

Q16

D

41

Q17

D

43

SS15

V

45

QS#2

D

47

QS2

D

49

SS18

V

51

Q18

D

53

Q19

D

55

SS20

V

57

Q24

D

59

Q25

D

61

V

SS22

63

D

M3

65

V

SS23

67

D

Q26

69

D

Q27

71

V

SS25

73

C

KE0

75

V

DD1

77

N

C1

79

B

A2

81

V

DD3

83

A

12/BC#

85

A

9

87

V

DD5

89

A

8

91

A

5

93

V

DD7

95

A

3

97

A

1

99

V

DD9

101

C

K0

103

C

K0#

105

V

DD11

107

A

10/AP

109

B

A0

111

V

DD13

113

W

E#

115

C

AS#

117

V

DD15

119

A

13

121

S

1#

123

V

DD17

125

N

CTEST

127

V

SS27

129

D

Q32

131

D

Q33

133

V

SS29

135

D

QS#4

137

D

QS4

139

V

SS32

141

D

Q34

143

D

Q35

145

V

SS34

147

D

Q40

149

D

Q41

151

V

SS36

153

D

M5

155

V

SS37

157

D

Q42

159

D

Q43

161

V

SS39

163

D

Q48

165

D

Q49

167

V

SS41

169

D

QS#6

171

D

QS6

173

V

SS44

175

D

Q50

177

D

Q51

179

V

SS46

181

D

Q56

183

D

Q57

185

V

SS48

187

D

M7

189

V

SS49

191

D

Q58

193

D

Q59

195

V

SS51

197

S

A0

199

V

DDSPD

201

S

A1

203

V

TT1

205

G

1

LCN_DAN06-K4806-0102

LCN_DAN06-K4806-0102

Conn@

Conn@

R

V

REF_CA

E

V

V

QS#0

D

D
V

V
D
D

SS10

V

ESET#

SS12

V

D
D

SS14

V

D
D

SS16

V

SS17

V

D
D

SS19

V

D
D

SS21

V
D

QS#3

D

V

SS24
D
D

V

SS26

C
V

V

V

V

V

DD10

C

V

DD12

R

V

DD14

O

V

DD16
O

V

DD18

V

SS28
D
D

V

SS30

V

SS31
D
D

V

SS33
D
D

V

SS35

D

QS#5
D

V

SS38
D
D

V

SS40
D
D

V

SS42

V

SS43
D
D

V

SS45
D
D

V

SS47

D

QS#7
D

V

SS50
D
D

V

SS52

VENT#

V

A

P

P

CIE_GTX_C_CRX_P[0..3]<6>

P

CIE_GTX_C_CRX_N[0..3]<6>

P

CIE_CTX_C_GRX_P[0..3]<6>

P

CIE_CTX_C_GRX_N[0..3]<6>

1 1

P

CIE_GTX_C_CRX_P0

P

CIE_GTX_C_CRX_N0

P

CIE_GTX_C_CRX_P1

P

CIE_GTX_C_CRX_N1

P

CIE_GTX_C_CRX_P2

P

CIE_GTX_C_CRX_N2

P

CIE_GTX_C_CRX_P3

P

CIE_GTX_C_CRX_N3

2 2

3 3

C

LK_REQ_VGA#<26>

4 4

CIE_GTX_C_CRX_P[0..3]

P

CIE_GTX_C_CRX_N[0..3]

P

CIE_CTX_C_GRX_P[0..3]

P

CIE_CTX_C_GRX_N[0..3]

1 2

C

C

V1 0.22U_0402_16V7KOPT@

V1 0.22U_0402_16V7KOPT@

2

1

V2 0.22U_0402_16V7KOPT@

V2 0.22U_0402_16V7KOPT@

C

C

1 2

V3 0.22U_0402_16V7KOPT@

V3 0.22U_0402_16V7KOPT@

C

C

2

1

C

C

V4 0.22U_0402_16V7KOPT@

V4 0.22U_0402_16V7KOPT@

2

1

C

C

V5 0.22U_0402_16V7KOPT@

V5 0.22U_0402_16V7KOPT@

2

1

C

C

V6 0.22U_0402_16V7KOPT@

V6 0.22U_0402_16V7KOPT@

1 2

C

C

V7 0.22U_0402_16V7KOPT@

V7 0.22U_0402_16V7KOPT@

1 2

C

C

V8 0.22U_0402_16V7KOPT@

V8 0.22U_0402_16V7KOPT@

C

LK_PCIE_VGA<26>

C

LK_PCIE_VGA#<26>

P

LTRST_VGA#<29>

61

Q

Q

V2A

V2A

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

OPT@

OPT@

2

1 2

@

@

R

R

V4 200_0402_1%

V4 200_0402_1%

+

3VS_DGPU

PCIE_CTX_C_GRX_P0
P

CIE_CTX_C_GRX_N0

P

CIE_CTX_C_GRX_P1

P

CIE_CTX_C_GRX_N1

P

CIE_CTX_C_GRX_P2

P

CIE_CTX_C_GRX_N2

P

CIE_CTX_C_GRX_P3

P

CIE_CTX_C_GRX_N3

P

CIE_GTX_CRX_P0

P

CIE_GTX_CRX_N0

P

CIE_GTX_CRX_P1

P

CIE_GTX_CRX_N1

P

CIE_GTX_CRX_P2

P

CIE_GTX_CRX_N2

P

CIE_GTX_CRX_P3

P

CIE_GTX_CRX_N3

C

LK_PCIE_VGA

C

LK_PCIE_VGA#

C

LK_REQ_GPU#

P

EX_TSTCLK_OUT

P

EX_TSTCLK_OUT#

R

R

V5

V5

2.49K_0402_1%

2.49K_0402_1%

OPT@

OPT@

1 2

B

V1A

V1A

U

U

AG6

EX_RX0

P

AG7

EX_RX0_N

P

AF7

P

EX_RX1

AE7

EX_RX1_N

P

AE9

P

EX_RX2

AF9

EX_RX2_N

P

AG9

EX_RX3

P

AG10

P

EX_RX3_N

AF10

P

EX_RX4

AE10

EX_RX4_N

P

AE12

EX_RX5

P

AF12

EX_RX5_N

P

AG12

P

EX_RX6

AG13

EX_RX6_N

P

AF13

EX_RX7

P

AE13

P

EX_RX7_N

AE15

C

N

AF15

C

N

AG15

N

C

AG16

C

N

AF16

C

N

AE16

N

C

AE18

N

C

AF18

N

C

AG18

N

C

AG19

C

N

AF19

N

C

AE19

C

N

AE21

C

N

AF21

N

C

AG21

C

N

AG22

C

N

AC9

EX_TX0

P

AB9

P

EX_TX0_N

AB10

EX_TX1

P

AC10

EX_TX1_N

P

AD11

P

EX_TX2

AC11

EX_TX2_N

P

AC12

P

EX_TX3

AB12

P

EX_TX3_N

AB13

EX_TX4

P

AC13

P

EX_TX4_N

AD14

EX_TX5

P

AC14

P

EX_TX5_N

AC15

EX_TX6

P

AB15

EX_TX6_N

P

AB16

EX_TX7

P

AC16

EX_TX7_N

P

AD17

C

N

AC17

N

C

AC18

N

C

AB18

N

C

AB19

N

C

AC19

C

N

AD20

N

C

AC20

C

N

AC21

N

C

AB21

C

N

AD23

C

N

AE23

N

C

AF24

N

C

AE24

N

C

AG24

C

N

AG25

C

N

AE8

EX_REFCLK

P

AD8

EX_REFCLK_N

P

AC6

EX_CLKREQ_N

P

AF22

EX_TSTCLK_OUT

P

AE22

EX_TSTCLK_OUT_N

P

AC7

P

EX_RST_N

AF25

P

EX_TERMP

N14P-GV2-S-A2_FCBGA595

N14P-GV2-S-A2_FCBGA595

N14PGV2R3@

N14PGV2R3@

1

C

C
18P_0402_50V8J

18P_0402_50V8J

NOGCLK@

NOGCLK@

2

X

V17

V17

TALIN

art 1 of 6

art 1 of 6

P

P

1

CI EXPRESS

CI EXPRESS
P

P

Y

Y

V1

V1

1

ACs

ACs
D

D

120mA

2C GPIO

2C GPIO

I

I

52mA

71mA

41mA

CLK

CLK

NOGCLK@

NOGCLK@

27MHZ_16PF

27MHZ_16PF

G

ND

2

G
G
G
G
G
G
G
G
G
G
G
G

D

ACA_RED

ACA_GREEN

D

ACA_BLUE

D

ACA_HSYNC

D
D

ACA_VSYNC

ACA_VDD

D

ACA_VREF

D

ACA_RSET

D

2CA_SCL

I

I

2CA_SDA

2CB_SCL

I

I

2CB_SDA

I

2CC_SCL

2CC_SDA

I

2CS_SCL

I
2CS_SDA

I

C

ORE_PLLVDD

P_PLLVDD

S

ID_PLLVDD

V

X

TAL_IN

TAL_OUT

X

X

TAL_SSIN

TAL_OUTBUFF

X

3

G

ND

4

18P_0402_50V8J

18P_0402_50V8J

G
G
G
G
G
G
G
G
G
G

PIO10
PIO11
PIO12
PIO13
PIO14
PIO15
PIO16
PIO17
PIO18
PIO19
PIO20
PIO21

PIO0
PIO1
PIO2
PIO3
PIO4
PIO5
PIO6
PIO7
PIO8
PIO9

N

3

C6
B2
D6
C7
F9
A3
A4
B6
A6
F8
C5
E7
D7
B4
B3
C3
D5
D4
C2
F7
E6
C4

AB6

C

AG3
AF4
AF3

AE3
AE4

W5
AE2
AF2

B7
A7

C9
C8

A9
B9

D9
D8

L6
M6

N6

C11
B10

A10
C10

X

TAL_OUT

C

C

NOGCLK@

NOGCLK@

V18

V18

F

B_CLAMP_MON

F

B_CLAMP_REQ#

O

VERT#_VGA

G

PU_EVENT

D

GPU_VID

G

PS_DOWN#

P

SI

V

GA_CRT_CLK

V

GA_CRT_DATA

H

DCP_SCL

H

DCP_SDA

V

GA_EDID_CLK

V

GA_EDID_DATA

S

MB_CLK_GPU

S

MB_DATA_GPU

+

PLLVDD

+

GPU_PLLVDD

X

TALIN

X

TAL_OUT

X

TAL_SSIN

X

TAL_OUTBUFF

1

2

C

+

3VS_DGPU

G

G

2

V8

V8

Q

Q

N14PGV2@

N14PGV2@

13

D

D

S

S

2N7002KW_SOT323-3

2N7002KW_SOT323-3

D

GPU_VID <54>

G

PS_DOWN# <41>

P

SI <54>

1

V9

V9

1

V10

V10

C

C

C

O

O

PT@

PT@

2

CV42, CV43 under GPU
close to ball : AE8,AD7

V

GA_X1<35>

10_0402_5%

10_0402_5%

10P_0402_50V8J

10P_0402_50V8J

f

or EMI

C

2

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

O

O

PT@

PT@

12

V7

@EMI@

V7

@EMI@

R

R

1

V113

@EMI@

V113

@EMI@

C

C

2

D

D

V1

V1

12

RB751V40_SC76-2

RB751V40_SC76-2

OPT@

OPT@

C

LK_REQ_GC6# <41>

BLM18PG181SN1D_2P

BLM18PG181SN1D_2P

1

V11

V11
C

C

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

O

O

PT@

PT@

1 2

R

R

V8 0_0402_5%

V8 0_0402_5%

1 2

1

V12

V12
C

C

2

O

O

PT@

PT@

GCLK@

GCLK@

F

B_CLAMP <14,17,41>

L

L

V1

V1

OPT@

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

X

TALIN

+

1.05VS_DGPU

1

PT@

PT@

O

O

2

D

F

or GC6

V13

V13
C

C

10U_0603_6.3V6M

10U_0603_6.3V6M

J

TAG_TRST<15>

T

ESTMODE<15>

I

nternal Thermal Sensor

S

MB_CLK_GPU

S

MB_DATA_GPU

under GPU
close to AD8

OPT@

OPT@

Q

Q

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

+

PLLVDD

+

4

2

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

V1A

V1A

1

V14

V14
C

C

2

OPT@

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

G

PS_DOWN#

G

PU_EVENT

X

TAL_OUTBUFF

X

TAL_SSIN

V

GA_EDID_CLK

V

GA_EDID_DATA

S

MB_CLK_GPU

S

MB_DATA_GPU

V

GA_CRT_CLK

V

GA_CRT_DATA

H

DCP_SDA

H

DCP_SCL

F

B_CLAMP

F

B_CLAMP_REQ#

F

B_CLAMP_MON

O

VERT#_VGA

C

LK_REQ_GC6#

C

LK_REQ_GPU#

3VS_DGPU

5

OPT@

OPT@

V1B

V1B

Q

Q

3

61

FBMA-L11-160808300LMA25T_2P

FBMA-L11-160808300LMA25T_2P

1

V15

V15
C

C

2

OPT@

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

E

R

R

PV1

PV1

1
2 7
3 6
4 5

10K_8P4R_5%

10K_8P4R_5%

OPT@

OPT@

R

R

PV2

PV2

1 8
2
3 6
4 5

2.2K_8P4R_5%

2.2K_8P4R_5%

OPT@

OPT@

PV3

PV3

R

R

1 8
2
3 6
4 5

2.2K_8P4R_5%

2.2K_8P4R_5%

OPT@

OPT@

R

R

PV12

PV12

1
2 7
3 6
4

10K_8P4R_5%

10K_8P4R_5%

OPT@

OPT@

PV13

PV13

R

R

1 8
2 7
3 6
4

10K_8P4R_5%

10K_8P4R_5%

OPT@

OPT@

L

L

V2

OPT@

V2

OPT@

1 2

+

3VS_DGPU

8

7

7

8

5

5

E

C_SMB_CK2 <26,34,41>

E

C_SMB_DA2 <26,34,41>

+

1.05VS_DGPU

1

V16

V16
C

C

2

OPT@

OPT@

+

3VS

10U_0603_6.3V6M

10U_0603_6.3V6M

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2

2

2

012/12/07 2013/12/07

012/12/07 2013/12/07

012/12/07 2013/12/07

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

D

Date: Sheet

ompal Electronics, Inc.

V

V

V

GA_N14x PEG & DAC

GA_N14x PEG & DAC

GA_N14x PEG & DAC

E

0

0

0

.2

.2

o

o

o

13 56Monday, March 11, 2013

13 56Monday, March 11, 2013

13 56Monday, March 11, 2013

.2

f

f

f

A

P

V

RAM Interface

M

+

FB_PLLAVDD

C

C

22U_0805_6.3V6M

22U_0805_6.3V6M

V20

V20

1

OPT@

OPT@

2

DA[15..0]

M

DA[31..16]

DA[47..32]

M

DA[63..48]

M

Close to H22

0.1U_0402_10V7K

0.1U_0402_10V7K

C

C
V21

V21

2

OPT@

OPT@

1

C

C
V22

V22

1

OPT@

OPT@

2

Close to P22

C

C

0.1U_0402_10V7K

0.1U_0402_10V7K
V114

V114

OPT@

OPT@

U

U

V1B

V1B

art 2 of 6

art 2 of 6

P

BA_D00

F

BA_D01

F

BA_D02

F

BA_D03

F

BA_D04

F

BA_D05

F

BA_D06

F

BA_D07

F

BA_D08

F

BA_D09

F

BA_D10

F

BA_D11

F

BA_D12

F

BA_D13

F

BA_D14

F

BA_D15

F

BA_D16

F

BA_D17

F
F

BA_D18
BA_D19

F
F

BA_D20

F

BA_D21

F

BA_D22

F

BA_D23

F

BA_D24

F

BA_D25

F

BA_D26

F

BA_D27

F

BA_D28

F

BA_D29

F

BA_D30

F

BA_D31

F

BA_D32

F

BA_D33

F

BA_D34

F

BA_D35

F

BA_D36

F

BA_D37

F

BA_D38

F

BA_D39

F

BA_D40

F

BA_D41

F

BA_D42

F

BA_D43

F

BA_D44

F

BA_D45

F

BA_D46

F

BA_D47

F

BA_D48

F

BA_D49

F

BA_D50

F

BA_D51

F

BA_D52

F

BA_D53

F

BA_D54

F

BA_D55

F

BA_D56

F

BA_D57

F

BA_D58

F

BA_D59

F

BA_D60

F

BA_D61

F

BA_D62

F

BA_D63

F

B_PLLAVDD_1

F

B_PLLAVDD_2

F

B_VREF_PROBE

F

B_DLLAVDD

F

B_CLAMP

F

BA_DEBUG0

F

BA_DEBUG1

P

62mA
62mA

35mA

EMORY

EMORY
M

M

F

BA_DQS_RN0

F

BA_DQS_RN1

INTERFACE A

INTERFACE A

F

BA_DQS_RN2

F

BA_DQS_RN3

F

BA_DQS_RN4

F

BA_DQS_RN5

F

BA_DQS_RN6

F

BA_DQS_RN7

F

BA_DQS_WP0

F

BA_DQS_WP1

F

BA_DQS_WP2

F

BA_DQS_WP3

F

BA_DQS_WP4

F

BA_DQS_WP5

F

BA_DQS_WP6

F

BA_DQS_WP7

F

BA_WCK01_N

F

BA_WCK23_N

F

BA_WCK45_N

F

BA_WCK67_N

F

BA_CMD0

F

BA_CMD1

F

BA_CMD2

F

BA_CMD3

F

BA_CMD4

F

BA_CMD5

F

BA_CMD6

F

BA_CMD7

F

BA_CMD8

F

BA_CMD9

F

BA_CMD10

F

BA_CMD11

F

BA_CMD12

F

BA_CMD13

F

BA_CMD14

F

BA_CMD15

F

BA_CMD16

F

BA_CMD17

F

BA_CMD18

F

BA_CMD19

F

BA_CMD20

F

BA_CMD21

F

BA_CMD22

F

BA_CMD23

F

BA_CMD24

F

BA_CMD25

F

BA_CMD26

F

BA_CMD27

F

BA_CMD28

F

BA_CMD29

F

BA_CMD30

F

BA_CMD31

F

BA_DQM0

F

BA_DQM1

F

BA_DQM2

F

BA_DQM3

F

BA_DQM4

F

BA_DQM5

F

BA_DQM6

F

BA_DQM7

F

BA_CLK0

F

BA_CLK0_N

F

BA_CLK1

F

BA_CLK1_N

F

BA_WCK01

F

BA_WCK23

F

BA_WCK45

F

BA_WCK67

C27
C26
E24
F24
D27
D26
F25
F26
F23
G22
G23
G24
F27
G25
G27
G26
M24
M23
K24
K23
M27
M26
M25
K26
K22
J23
J25
J24
K27
K25
J27
J26

D19
D14
C17
C22
P24
W24
AA25
U25

F19
C14
A16
A22
P25
W22
AB27
T27

E19
C15
B16
B22
R25
W23
AB26
T26

D24
D25

N22
M22

D18
C18
D17
D16
T24
U24
V24
V25

C

MDA0

C

MDA1

C

MDA2

C

MDA3

C

MDA4

C

MDA5

C

MDA6

C

MDA7
CMDA8
C

MDA9
C

MDA10

C

MDA11

C

MDA12

C

MDA13

C

MDA14
C

MDA15
C

MDA16
C

MDA17

C

MDA18

C

MDA19

C

MDA20
CMDA21
C

MDA22
C

MDA23

C

MDA24

C

MDA25

C

MDA26
CMDA27
C

MDA28

C

MDA29

C

MDA30

D
D
D
D
D
D
D
D

D
D
D
D
D
D
D
D

M

DA0

M

DA1

M

DA2

M

DA3

M

DA4

M

DA5

M

DA6

M

DA7

M

DA8

M

DA9

M

DA10

M

DA11

M

DA12

M

DA13

M

DA14

M

DA15

M

DA16

M

DA17

M

DA18

M

DA19

M

DA20

M

DA21

M

DA22

M

DA23

M

DA24

M

DA25

M

DA26

M

DA27

M

DA28

M

DA29

M

DA30

M

DA31

M

DA32

M

DA33

M

DA34

M

DA35

M

DA36

M

DA37

M

DA38

M

DA39

M

DA40

M

DA41

M

DA42

M

DA43

M

DA44

M

DA45

M

DA46

M

DA47

M

DA48

M

DA49

M

DA50

M

DA51

M

DA52

M

DA53

M

DA54

M

DA55
MDA56
M

DA57
M

DA58
M

0.1U_0402_10V7K

0.1U_0402_10V7K

1

2

B_CLAMP<13,17,41>

F

DA59
M

DA60
M

DA61
MDA62
M

DA63

+

FB_PLLAVDD

V1 PADTV1 PAD

T

V2 PADTV2 PAD

T

E18
F18
E16
F17
D20
D21
F20
E21
E15
D15
F15
F13
C13
B13
E13
D13
B15
C16
A13
A15
B18
A18
A19
C19
B24
C23
A25
A24
A21
B21
C20
C21
R22
R24
T22
R23
N25
N26
N23
N24
V23
V22
T23
U22
Y24

AA24

Y22
AA23
AD27
AB25
AD26
AC25
AA27
AA26

W26

Y25

R26

T25

N27

R27

V26

V27

W27
W25

F16

P22

D23

H22

F3

F22

J22

N14P-GV2-S-A2_FCBGA595

N14P-GV2-S-A2_FCBGA595

N14PGV2R3@

N14PGV2R3@

D

QMA0

D

QMA1

D

QMA2

D

QMA3

D

QMA4

D

QMA5

D

QMA6

D

QMA7

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

MDA[30..0] <18,19,20,21>

C

LKA0 <18,20>

C

LKA0# <18,20>

C

LKA1 <19,21>

C

LKA1# <19,21>

C

QMA[3..0] <18,20>

D

QMA[7..4] <19,21>

D

QSA#[3..0] < 18,20>

D

QSA#[7..4] < 19,21>

D

QSA[3..0] < 18,20>

D

QSA[7..4] < 19,21>

D

DA[15..0]<18,20>

M

DA[31..16]<18,20>

M

DA[47..32]<19,21>

M

DA[63..48]<19,21>

M

1 1

30ohms (ESR=0.01)

1.05VS_DGPU

+

V3

OPT@

V3

OPT@

L

L

1 2

FBMA-L11-160808300LMA25T_2P

FBMA-L11-160808300LMA25T_2P

Place close to BGA

Near GPU Close to F16

lace close to t he first T poin t

VRAM_1.5VS

+

7

6

109

8

R

R

PV4

PV4

100_1206_10P8R_5%

100_1206_10P8R_5%

OPT@

OPT@

5

234

1

VRAM_1.5VS

+

0

6

987

1

PV6

PV6

R

R
100_1206_10P8R_5%

100_1206_10P8R_5%

OPT@

OPT@

345

1

2

VRAM_1.5VS

+

PV8

PV8

R

R

18

7

2
36
45

100_0804_8P4R_5%

100_0804_8P4R_5%

OPT@

OPT@

12

V10 100_0402_5%

V10 100_0402_5%

R

R

OPT@

OPT@

12

V12 100_0402_5%

V12 100_0402_5%

R

R

OPT@

OPT@

Command Bit Default Pull-down

ODTx

CKEx

DDR3

RST

CS* No Termination

C
C
C
C
C

MDA16
MDA19
MDA3
MDA0
MDA20

1 2

V36 10K_0402_5%OPT@

V36 10K_0402_5%OPT@

R

R

1 2

R

R

V37 10K_0402_5%OPT@

V37 10K_0402_5%OPT@

1 2

V38 10K_0402_5%OPT@

V38 10K_0402_5%OPT@

R

R

1 2

V40 10K_0402_5%OPT@

V40 10K_0402_5%OPT@

R

R

1 2

V15 10K_0402_5%OPT@

V15 10K_0402_5%OPT@

R

R

C

MDA26

C

MDA25

C

MDA27

C

MDA28

C
C
C
C

C
C

C

C

C
C
C
C

C
C
C
C

MDA12
MDA14
MDA15
MDA7

MDA11
MDA4

MDA5

MDA6

MDA22
MDA9
MDA21
MDA24

MDA23
MDA13
MDA8
MDA10

MDA29

C

MDA30

C

0

6

987

1

PV5

PV5

R

R
100_1206_10P8R_5%

100_1206_10P8R_5%

OPT@

OPT@

345

1

2

7

6

109

8

PV7

PV7

R

R
100_1206_10P8R_5%

100_1206_10P8R_5%

OPT@

OPT@

5

234

1

R

R

PV9

PV9

1 8

MDA28

C

2 7

MDA27

C

MDA25

C

MDA26

C

10k

10k

10k

6

3
4 5

100_0804_8P4R_5%

100_0804_8P4R_5%

OPT@

OPT@

12

V11 100_0402_5%

V11 100_0402_5%

R

R

OPT@

OPT@

2

1

V13 100_0402_5%

V13 100_0402_5%

R

R

OPT@

OPT@

ecurity Classification

ecurity Classification

ecurity Classification

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

012/12/07 2013/12/07

012/12/07 2013/12/07

012/12/07 2013/12/07

2

2

2

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

eciphered Date

eciphered Date

eciphered Date

D

D

D

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

itle

itle

itle

T

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

ustom

ustom

ustom

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

C

14x VRAM Interface

14x VRAM Interface

14x VRAM Interface

N

N

N

f

14 56Monday, March 11, 2013

f

14 56Monday, March 11, 2013

f

14 56Monday, March 11, 2013

o

o

o

.2

.2

.2

0

0

0

5

U

U

V1C

V1C

AC3

FPA_TXC

I

AC4

FPA_TXC_N

I

Y4

FPA_TXD0

I

Y3

I

FPA_TXD0_N

AA3

FPA_TXD1

D D

C C

B B

A A

I

AA2

I

FPA_TXD1_N

AB1

FPA_TXD2

I

AA1

FPA_TXD2_N

I

AA4

FPA_TXD3

I

AA5

FPA_TXD3_N

I

AB5

FPB_TXC

I

AB4

FPB_TXC_N

I

AB3

I

FPB_TXD4

AB2

FPB_TXD4_N

I

AD3

I

FPB_TXD5

AD2

FPB_TXD5_N

I

AE1

I

FPB_TXD6

AD1

FPB_TXD6_N

I

AD4

FPB_TXD7

I

AD5

FPB_TXD7_N

I

T2

FPC_L0

I

T3

I

FPC_L0_N

T1

I

FPC_L1

R1

FPC_L1_N

I

R2

FPC_L2

I

R3

FPC_L2_N

I

N2

I

FPC_L3

N3

FPC_L3_N

I

V3

FPD_L0

I

V4

FPD_L0_N

I

U3

FPD_L1

I

U4

I

FPD_L1_N

T4

I

FPD_L2

T5

FPD_L2_N

I

R4

FPD_L3

I

R5

FPD_L3_N

I

N1

N

C

M1

N

C

M2

C

N

M3

C

N

K2

C

N

K3

C

N

K1

C

N

J1

C

N

M4

C

N

M5

C

N

L3

C

N

L4

C

N

K4

C

N

K5

C

N

J4

C

N

J5

N

C

N4

FPC_AUX_I2CW_SCL

I

N5

FPC_AUX_I2CW_SDA _N

I

P3

FPD_AUX_I2CX_SCL

I

P4

I

FPD_AUX_I2CX_SDA_N

J2

FPE_AUX_I2CY_SCL

I

J3

FPE_AUX_I2CY_SDA_N

I

H3

FPF_AUX_I2CZ_SCL

I

H4

I

FPF_AUX_I2CZ_SDA_N

N14P-GV2-S-A2_FCBGA595

N14P-GV2-S-A2_FCBGA595

N14PGV2R3@

N14PGV2R3@

P

P

art 3 of 6

art 3 of 6

C

C
N

N

ENERAL

ENERAL
G

G

ULTI_STRAP_REF0_GND

M

VDS/TMDS

VDS/TMDS
L

L

V

G

T

T

EST

EST

TAG_TRST_N

J

S

S

ERIAL

ERIAL

UFRST_N

B

TRAP0

S

TRAP1

S

TRAP2

S

TRAP3

S

TRAP4

S

HERMDP

T

HERMDN

T

DD_SENSE

ND_SENSE

ESTMODE

T

TAG_TCK

J

TAG_TDI

J
TAG_TDO

J

TAG_TMS

J

OM_CS_N

R

OM_SI

R

OM_SO

R

OM_SCLK

R

N

N

N

N

N
N
N

N

N

N
N

N
N
N
N
N
N
N
N

N

N

N

N

N

N
N

C

C

C

C

C
C
C

C

C

C
C

C
C
C
C
C
C
C
C

C

C

C

C

C

C
C

F11

AD10

AD7

B19

V5
V6
G1

G2

G3

G4
G5

G6
G7
V1
V2
W1
W2
W3
W4

D11

D10

E9

E10

F10

D1
D2
E4
E3
D3
C1

F6
F4
F5

F12

E12

F2

F1

AD9
AE5
AE6
AF6
AD6
AG4

D12
B12
A12
C12

V

V

R

R

M

GA_VCC_SENSE

GA_VSS_SENSE

OPT@

OPT@

2

1

V16 10K_0402_5%

V16 10K_0402_5%

S

TRAP0

S

TRAP1

S

TRAP2

S

TRAP3

S

TRAP4

ULTI_STRAP_REF0_GND

t

race width: 16mils
differential voltage sensing.
differential signal routing.

J

TAG_TCK

J

TAG_TDI

J

TAG_TDO

J

TAG_TMS

R

OM_SI

R

OM_SO

R

OM_SCLK

4

N14PGV2@

N14PGV2@

1 2

V17 40.2K_0402_1%

V17 40.2K_0402_1%

R

R

+

VGA_CORE

2

R

R

V26

V26

100_0402_1%

100_0402_1%

OPT@

OPT@

1

100_0402_1%

100_0402_1%

PAD

PAD

T

T

V3

V3

PAD

PAD

V4

V4

T

T

PAD

PAD

T

T

V5

V5

PAD

PAD

V6

V6

T

T

Strap Pin Strap Mapping

R

ROM_SI

ROM_SO

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

OPT@

OPT@

R

R

V35

V35

OM_SCLK

12

T

ESTMODE <13>

J

TAG_TRST <13>

SMB_ALT_ADDR

SUB_VENDOR

VGA_DEVICE

RAMCFG[0]

RAMCFG[1]

RAMCFG[2]

RAMCFG[3]

PCIE_MAX_SPEED

V

GA_VCC_SENSE <54>

V

GA_VSS_SENSE <54>

3

PD 10k

P

U 10k if VBIOS ROM exists

PD 10k if no VB IOS ROM

P

D 10k (no display)

Refer to RVL

PD 10k

M

ULTI LEVEL STRAPS

S

TRAP0

S

TRAP1

S

TRAP2

N14P-GV2

1
2
8
M

x
1
6

2
5
6
M

x
1
6

1

2

N14PGV2@

N14PGV2@

1

@

@

2

Samsung

Hynix

Micron

Micron

M

ULTI LEVEL STRAPS (for N14P-GV2)BINARY STRAPS (for N14M-GL)

Physical
Strapping pin

R

OM_SO

R

OM_SCLK

ROM_SI

STRAP0

STRAP1

STRAP2

S

TRAP3

S

TRAP4

Power Rail

+3VS_DGPU

+3VS_DGPU

+3VS_DGPU

+3VS_DGPU

+

3VS_DGPU 3GIO_PADCFG[0]3GIO_PADCFG[1]3GIO_PADCFG[2]

+

3VS_DGPU

+3VS_DGPU SOR0_EXPOSEDSOR2_EXPOSED SOR1_EXPOSED

+3VS_DGPU DP_PLL_VDD33V

SKU Device ID biit5 to bit0

N

14P-GV2

N

14M-GL

12

@

@

V19

V19

V18

V18
R

R

V27

V27
R

R

10K_0402_1%

10K_0402_1%

R

R

45.3K_0402_1%

45.3K_0402_1%

12

V28

V28

N14PGV2@

N14PGV2@

R

R

4.99K_0402_1%

4.99K_0402_1%

45.3K_0402_1%

45.3K_0402_1%

0

x1140 000000

+

3VS_DGPU

12

@

@

V20

V20

10K_0402_1%

10K_0402_1%

R

R

1

2

V29

V29

N14PGV2@

N14PGV2@

R

R

15K_0402_1%

15K_0402_1%

12

@

@

V21

V21
R

R

4.99K_0402_1%

4.99K_0402_1%

12

V30

V30

N14PGV2@

N14PGV2@

R

R

4.99K_0402_1%

4.99K_0402_1%

FB Memory gDDR3

9

00MHz

K4W2G1646E-BC11

K4W2G1646E-BC1A

1GHz

900MHz

H5TQ2G63DFR-11C

H5TQ2G63DFR-N0C

1GHz

M

T41K128M16JT-107G

900MHz

K

9

9

00MHz

00MHz

4W4G1646B-HC11Samsung

M

T41K256M16HA-107G

2

Logical
Strapping Bit3

F

B[1]

P

CI_DEVID[4]

USER[3]

3

GIO_PADCFG[3]

P

CI_DEVID[3]

S

OR3_EXPOSED

R

ESERVED

0

100100x1292

12

@

@

V22

V22

10K_0402_1%

10K_0402_1%

R

R

S

TRAP3

S

TRAP4

12

V31

V31

N14PGV2@

N14PGV2@

R

R

45.3K_0402_1%

45.3K_0402_1%

ROM_SIGPU

PD 45.3K

P

D 34.8K

PD 30K

PD 20K

PD 10K

Logical
Strapping Bit2

FB[0]

PCIE_SPEED_CHANGE_GEN3

R

R

V31

V31

10K_0402_1%

10K_0402_1%

N14MGL@

N14MGL@

N14M-GL

Logical
Strapping Bit1

SMB_ALT_ADDR

P

SUB_VENDOR

CI_DEVID[5]

R

AMCFG[1]RAMCFG[3] RAMCFG[2]

PCIE_MAX_SPEED

R

esistor Values

5

K

1

0K

15K

20K

25K

30K

35K

45K

R

OM_SI

R

OM_SO

R

OM_SCLK

For X76 (N14P-GV2)For X76 (N14M-GL)

FB Memory gDDR3

Samsung

1
2
8
M

Hynix

x
1
6

Micron

Samsung K4W4G1646B-HC11

2
5
6
M

Micron

x
1
6

1GHz

1GHz

900MHz

9

00MHz

9

00MHz

K4W2G1646E-BC11900MHz

K4W2G1646E-BC1A

H5TQ2G63DFR-11C900MHz

H5TQ2G63DFR-N0C

M

M

1

L

ogical

Strapping Bit0

V

GA_DEVICE

PEX_PLLEN_TERM

RAMCFG[0]

USER[0]USER[1]USER[2]

PCI_DEVID[0]PCI_DEVID[1]PCI_DEVID[2]

P

ull-up to +3VS

_DGPU

1

000

1001

1010

1011

1100

1101

1110

1111

12

12

@

@

V24

V24

V23

V23

N14PGV2@

N14PGV2@

R

R

R

R

4.99K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

12

1

2

N14MGL@

N14MGL@

N14MGL@

N14MGL@

V33

V33

V32

V32

R

R

R

R

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

T41K128M16JT-107G

T41K256M16HA-107G

P

ull-down to Gnd

0000

0001

0010

0011

0100

0101

0110

0111

+

3VS_DGPU

12

V25

V25

N14PGV2@

N14PGV2@

R

R

4.99K_0402_1%

4.99K_0402_1%

12

N14MGL@

N14MGL@

V34

V34
R

R

10K_0402_1%

10K_0402_1%

STRAP[3:0]GPU

0101

0110

0001

1011

1101

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2

2

2

012/12/07 2013/12/07

012/12/07 2013/12/07

012/12/07 2013/12/07

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

V

V

V

GA_N14x LVDS&TMDS

GA_N14x LVDS&TMDS

GA_N14x LVDS&TMDS

1

0

0

0

.2

.2

o

o

o

15 56Monday, March 11, 2013

15 56Monday, March 11, 2013

15 56Monday, March 11, 2013

.2

f

f

f

5

4

3

2

1

U

nder GPU

+

VRAM_1.5VS

D D

Under GPU

1

2

1

1

1

1

V32

V32
C

C

OPT@

OPT@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

V33

V33

V24

V24

C

C

C

C

2

2

OPT@

OPT@

2

OPT@

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1

V34

V34
C

C

OPT@

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

V35

V35

V25

V25
C

C

C

C

2

2

OPT@

OPT@

OPT@

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

Near GPU

1

1

V43

V43

V44

V44
C

C

C

C

2

2

OPT@

OPT@

OPT@

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

C C

B B

V1D

V1D

U

U

3

B26

BVDDQ_01

F

C25

BVDDQ_02

F

E23

BVDDQ_03

F

E26

BVDDQ_04

F

F14

BVDDQ_05

F

F21

BVDDQ_06

F

G13

BVDDQ_07

F

G14

BVDDQ_08

F

G15

BVDDQ_09

F

G16

BVDDQ_10

F

G18

BVDDQ_11

F

G19

BVDDQ_12

F

G20

BVDDQ_13

F

G21

BVDDQ_14

F

H24

BVDDQ_15

F

H26

BVDDQ_16

F

J21

BVDDQ_17

F

K21

BVDDQ_18

F

L22

BVDDQ_19

F

L24

BVDDQ_20

F

L26

BVDDQ_21

F

M21

BVDDQ_22

F

N21

BVDDQ_23

F

R21

BVDDQ_24

F

T21

BVDDQ_25

F

V21

BVDDQ_26

F

W21

BVDDQ_27

F

V7

FPAB_PLLVDD_1

I

W7

FPAB_PLLVDD_2

I

AA6

FPAB_RSET

I

W6

FPA_IOVDD

I

Y6

FPB_IOVDD

I

M7

FPC_PLLVDD_1

I

N7

FPC_PLLVDD_2

I

T6

FPC_RSET

I

P6

FPC_IOVDD

I

T7

FPD_PLLVDD_2

I

R7

FPD_PLLVDD_1

I

U6

FPD_RSET

I

R6

FPD_IOVDD

I

J7

N

K7

N

K6

N

H6

N

J6

N

N14P-GV2-S-A2_FCBGA595

N14P-GV2-S-A2_FCBGA595

N14PGV2R3@

N14PGV2R3@

art 4 of 6

Part 4 of 6

P

500 mA 2000 mA

C
C
C
C
C

EX_IOVDDQ_1

P

EX_IOVDDQ_2

P

EX_IOVDDQ_3

P

EX_IOVDDQ_4

P

EX_IOVDDQ_5

P

EX_IOVDDQ_6

P

EX_IOVDDQ_7

P

EX_IOVDDQ_8

P

EX_IOVDDQ_9

P

EX_IOVDDQ_10

P

EX_IOVDDQ_11

P

EX_IOVDDQ_12

P

EX_IOVDDQ_13

P

EX_IOVDDQ_14

P

EX_IOVDD_1

P

EX_IOVDD_2

P

EX_IOVDD_3

P

EX_IOVDD_4

P

EX_IOVDD_5

P

EX_IOVDD_6

P

DD33_1

V

DD33_2

V

DD33_3

V

OWER

OWER

DD33_4

V

P

P

B_CAL_PD_VDDQ

F

B_CAL_PU_GND

F

B_CAL_TERM_GND

F

EX_PLL_HVDD_1

P

EX_PLL_HVDD_2

P

EX_SVDD_3V3

P

1

20mA

EX_PLLVDD_1

P

EX_PLLVDD_2

P

AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25
AF26
AF27

AA22
AB23
AC24
AD25
AE26
AE27

G10
G12
G8
G9

D22

C24

B25

AA8
AA9

AB8

AA14
AA15

+

FB_CAL_PD_VDDQ

F

B_CAL_PU_GND

F

B_CAL_TERM_GND

Under GPU

Near Ball

1

V54

V54
C

C

2

OPT@

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

1 2

2

2

1

2

Near GPU

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

V55

V55
C

C

OPT@

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

1

2

V26

V26
C

C

OPT@

OPT@

V36

V36
C

C

OPT@

OPT@

R

R

V3940.2_0402_1%

V3940.2_0402_1%

1

R

R

V4142.2_0402_1%

V4142.2_0402_1%

1

R

R

V4251.1_0402_1%

V4251.1_0402_1%

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

+

PEX_PLLVDD

V56

V56
C

C

OPT@

OPT@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1

V23

V23
C

C

2

OPT@

OPT@

1

V37

V37
C

C

2

OPT@

OPT@

N

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

+

VRAM_1.5VS

midway between GPU

ear GPU

and Power suppl y

1

1

V28

V28

V27

V27
C

C

C

C

2

2

OPT@

OPT@

OPT@

OPT@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1

1

V38

V38

V39

V39
C

C

C

C

2

2

OPT@

OPT@

OPT@

OPT@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

Under GPU

1

1

V45

V45

V46

V46

C

C

C

C

2

2

OPT@

OPT@

OPT@

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

L

L

V4

V4

2

N14MGL@

N14MGL@

R

R

V1

V1

0_0603_5%

0_0603_5%

N14PGV2@

N14PGV2@

1

12

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

0.1U_0402_10V7K

0.1U_0402_10V7K

+

1.05VS_DGPU

V29

V29
C

C

OPT@

OPT@

10U_0603_6.3V6M

10U_0603_6.3V6M

V40

V40
C

C

OPT@

OPT@

10U_0603_6.3V6M

10U_0603_6.3V6M

V47

V47
C

C

OPT@

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

Near GPU

1.05VS_DGPU

+

1

1

V30

V30
C

C

2

2

OPT@

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

+

1.05VS_DGPU

1

1

V41

V41
C

C

2

2

OPT@

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

+

1

1

V48

V48
C

C

2

2

OPT@

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

U

nder GPU

Close to AH12/A G12

V31

V31
C

C

OPT@

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

V42

V42
C

C

OPT@

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

3VS_DGPU

V49

V49
C

C

OPT@

OPT@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1

2

+

Near GPU

1

1

V51

V51

V50

V50

C

C

C

C

2

2

OPT@

OPT@

OPT@

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

3VS_DGPU

1

V53

V53

V52

V52

C

C

C

C

2

OPT@

OPT@

OPT@

OPT@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

A A

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2

2

2

012/12/07 2013/12/07

012/12/07 2013/12/07

012/12/07 2013/12/07

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

V

V

V

GA_N14x POWER

GA_N14x POWER

GA_N14x POWER

1

0

0

0

.2

.2

o

o

o

16 56Monday, March 11, 2013

16 56Monday, March 11, 2013

16 56Monday, March 11, 2013

.2

f

f

f

5

V1E

V1E

U

U

A2

G

A26

G

AB11

G

AB14

G

AB17

G

AB20

G

AB24

D D

C C

B B

G

AC2

G

AC22

G

AC26

G

AC5

G

AC8

G

AD12

G

AD13

G

AD15

G

AD16

G

AD18

G

AD19

G

AD21

G

AD22

G

AE11

G

AE14

G

AE17

G

AE20

G

AF1

G

AF11

G

AF14

G

AF17

G

AF20

G

AF23

G

AF5

G

AF8

G

AG2

G

AG26

G

B1

G

B11

G

B14

G

B17

G

B20

G

B23

G

B27

G

B5

G

B8

G

E11

G

E14

G

E17

G

E2

G

E20

G

E22

G

E25

G

E5

G

E8

G

H2

G

H23

G

H25

G

H5

G

N14P-GV2-S-A2_FCBGA595

N14P-GV2-S-A2_FCBGA595

N14PGV2R3@

N14PGV2R3@

ND_001
ND_002
ND_003
ND_004
ND_005
ND_006
ND_007
ND_008
ND_009
ND_010
ND_011
ND_012
ND_013
ND_014
ND_015
ND_016
ND_017
ND_018
ND_019
ND_020
ND_021
ND_022
ND_023
ND_024
ND_025
ND_026
ND_027
ND_028
ND_029
ND_030
ND_031
ND_032
ND_033
ND_034
ND_035
ND_036
ND_037
ND_038
ND_039
ND_040
ND_041
ND_042
ND_043
ND_044
ND_045
ND_046
ND_047
ND_048
ND_049
ND_050
ND_051
ND_052
ND_053
ND_054
ND_055
ND_056

art 5 of 6

art 5 of 6

P

P

ND

ND
G

G

ND_057

G
G

ND_058

G

ND_059

G

ND_060

G

ND_061
ND_062

G

ND_063

G
G

ND_064
ND_065

G
G

ND_066

G

ND_067
ND_068

G

ND_069

G

ND_070

G

ND_071

G

ND_072

G

ND_073

G

ND_074

G

ND_075

G

ND_076

G

ND_077

G

ND_078

G

ND_079

G

ND_080

G

ND_081

G

ND_082

G

ND_083

G

ND_084

G

ND_085

G

ND_086

G

ND_087

G

ND_088

G

ND_089

G

ND_090

G

ND_091

G

ND_092

G

ND_093

G

ND_094

G

ND_095

G

ND_096

G

ND_097

G

ND_098

G

ND_099

G

ND_100

G

ND_101

G

ND_102

G

ND_103

G

ND_104

G

ND_105

G

ND_106

G

ND_107

G

ND_108

G
G

ND_109
ND_110

G
G

ND_111

G

ND_112

K11
K13
K15
K17
L10
L12
L14
L16
L18
L2
L23
L25
L5
M11
M13
M15
M17
N10
N12
N14
N16
N18
P11
P13
P15
P17
P2
P23
P26
P5
R10
R12
R14
R16
R18
T11
T13
T15
T17
U10
U12
U14
U16
U18
U2
U23
U26
U5
V11
V13
V15
V17
Y2
Y23
Y26
Y5

AA7

G

ND

AB7

G

ND

4

+

VGA_CORE

F

or GC6

K10
K12
K14
K16
K18
L11
L13
L15

L17
M10
M12
M14
M16
M18

N11

N13

N15

N17

P10

P12

F

B_CLAMP<13,14,41>

V

GA_PWROK<30,54>

UV1F

UV1F

V

DD_001

V

DD_002

V

DD_003

V

DD_004

V

DD_005

V

DD_006

V

DD_007

V

DD_008

DD_009

V

DD_010

V

DD_011

V

DD_012

V

DD_013

V

DD_014

V

DD_015

V

DD_016

V

DD_017

V

DD_018

V

DD_019

V

DD_020

V

N14P-GV2-S-A2_FCBGA595

N14P-GV2-S-A2_FCBGA595

N14PGV2R3@

N14PGV2R3@

P

P

art 6 of 6

art 6 of 6

OWER

OWER
P

P

V18

DD_041

V

V16

DD_040

V

V14

DD_039

V

V12

DD_038

V

V10

DD_037

V

U17

DD_036

V

U15

DD_035

V

U13

DD_034

V

U11

DD_033

V

T18

DD_032

V

T16

DD_031

V

T14

DD_030

V

T12

DD_029

V

T10

DD_028

V

R17

DD_027

V

R15

DD_026

V

R13

DD_025

V

R11

DD_024

V

P18

DD_023

V

P16

DD_022

V

P14

DD_021

V

+

3VS

5

U

U

V2

V2

2

cc

B

V

1

A

G

NC7SZ32P5X_SC70-5

NC7SZ32P5X_SC70-5

3

2

1

R

R

V50 0_0402_5%

V50 0_0402_5%

N14MGL@

N14MGL@

Y

3

+

VGA_CORE

N14PGV2@

N14PGV2@

4

1

.5V_PWR_EN

2

1.05VS_VCCP to +1.05VS_DGPU

+

+

+

1.05VS_VCCP

V

gs=4.5V,Id=6.5A ,Rds<22mohm

Q

Q

V3

OPT@

V3

OPT@

13

D

D

2

G

AO3416_SOT23-3

AO3416_SOT23-3

+

1.05VS_DGPU

+

1.5V to +VRAM_1.5VS

+

1.5V

Q

Q

V6

OPT@

V6

OPT@

8

D

S

7

D

S

6

D

S

5

D

G

FDS6676AS_SO8

FDS6676AS_SO8

1

C

C

V60

C

C

V59

V59

O

O

PT@

PT@

V60

O

O

PT@

PT@

2

.7U_0603_6.3V6K

.7U_0603_6.3V6K
4

4

G

S

+

VRAM_1.5VS

V

1
2
3
4

1

2

S

1

C

C

V57

V57

O

O

PT@

PT@

2

gs=10V,Id=14.5A ,Rds=6mohm

V

RAM_1.5VS_GATE

12

R

R

V48

V48

820K_0402_5%OPT@

820K_0402_5%OPT@

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

.01U_0402_25V7K

.01U_0402_25V7K
0

0

1

.5V_PWR_EN

5VALW

1

R

R

V43

V43

270K_0402_5%

270K_0402_5%

OPT@

OPT@

2

6

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

V

GA_PWROK

OPT@

OPT@

R

R

1 2

180K_0402_5%

180K_0402_5%

61

Q

Q

OPT@

OPT@

5

OPT@

OPT@

1

V47

V47

V7A

V7A

2

1

V5B

V5B

Q

Q

G

G

.5V_PWR_EN#

.01U_0402_25V7K

.01U_0402_25V7K
0

0

OPT@

OPT@

Q

Q

V4A

V4A

2

S

S

V

GA_PWROK#

61

D

D

Q

Q

V5A

V5A

2

G

G

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

S

S

OPT@

OPT@

B

+

5

1

OPT@

OPT@

34

D

D

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

1

+

1.05VS_DGPU

2

R

R

V44

V44

22_0805_5%OPT@

22_0805_5%OPT@

1

3

OPT@

OPT@

Q

Q

V4B

V4B

5

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

1 2

V45100K_0402_5%

V45100K_0402_5%

R

R

OPT@

OPT@

R

R

V46

V46

470_0805_5%

470_0805_5%

OPT@

OPT@

1 2

3

Q

Q

V7B

V7B

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

OPT@

OPT@

4

+

5VALW

2

R

R

V49100K_0402_5%

V49100K_0402_5%

+

5VALW

+

3VS to +3VS_DGPU

+

+

3VS_DGPU

2

R

R

V51

V51

470_0805_5%

470_0805_5%

OPT@

OPT@

1

3

Q

Q

V9B

V9B

5

D

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

A A

5

4

OPT@

OPT@

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

GPU_PWR_EN#

4

3

+

VGA_CORE

2

R

R

V52

V52

470_0805_5%

470_0805_5%

OPT@

OPT@

1

3

Q

Q

V2B

V2B

5

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

OPT@

OPT@

4

C

C

C

ompal Secret Data

ompal Secret Data

2

2

2

012/12/07 2013/12/07

012/12/07 2013/12/07

012/12/07 2013/12/07

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

D

GPU_PWR_EN<29>

2

D

GPU_PWR_EN#

+

3VS

R

R

V53

V53

10K_0402_5%OPT@

10K_0402_5%OPT@

1 2

V54

V54

R

R

1

33K_0402_5%

33K_0402_5%

61

OPT@

Q

Q

V9A

V9A

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

OPT@

2

OPT@

OPT@

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

2

C

C

V61

V61

0.1U_0402_10V7K

0.1U_0402_10V7K

OPT@

OPT@

1

2

AO3413_SOT23

AO3413_SOT23

2

C

C

V62

V62

OPT@

OPT@

0.01U_0402_25V7K

0.01U_0402_25V7K

1

C

C

C

V

V

V

GA_N14x POWER & GND

GA_N14x POWER & GND

GA_N14x POWER & GND

3VS

V

gs=-4.5V,Id=3A, Rds<97mohm

S

S

Q

Q

V11

V11

G

G

2

OPT@

OPT@

D

D

1 3

+

3VS_DGPU

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

1

0

0

0

.2

.2

o

o

o

17 56Monday, March 11, 2013

17 56Monday, March 11, 2013

17 56Monday, March 11, 2013

.2

f

f

f

5

R

ANK 0 [31...0]

V

RAM DDR3 Chips

D

1

2

+

12

12

+

12

QSA[3..0]

D

QSA#[3..0]

D

QMA[3..0]

M

DA[31..0]

C

MDA[30..0]

MEM_VREF_CA0

1

V63

V63

C

C

0.01U_0402_25V7K

0.01U_0402_25V7K

OPT@

OPT@

2

MEM_VREF_DQ0

1

V64

V64

C

C

0.01U_0402_25V7K

0.01U_0402_25V7K

OPT@

OPT@

2

+

MEM_VREF_CA0

+

MEM_VREF_DQ0

243_0402_1%

243_0402_1%

D

QSA[3..0]<14,20>

D D

D

QSA#[3..0]<14,20>

D

QMA[3..0]<14,20>

M

DA[31..0]<14,20>

C

MDA[30..0]

+

VRAM_1.5VS

V55

V55

R

R

1K_0402_1%

1K_0402_1%

OPT@

OPT@

V56

V56

R

R

1K_0402_1%

1K_0402_1%

OPT@

OPT@

C C

B B

V57

V57

R

R

1K_0402_1%

1K_0402_1%

OPT@

OPT@

V58

V58

R

R

1K_0402_1%

1K_0402_1%

OPT@

OPT@

+

VRAM_1.5VS

+

MEM_VREF_CA0

+

MEM_VREF_DQ0

12

OPT@

OPT@

V60

V60

R

R

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

C
C
C

C
C
C

C
C
C
C
C

D
D

D
D

D
D

C

MDA7
MDA10
MDA24
MDA6
MDA22
MDA26
MDA5
MDA21
MDA8
MDA4
MDA25
MDA23
MDA9
MDA12
MDA14

MDA29
MDA13
MDA27

LKA0
LKA0#
MDA3

MDA0
MDA2
MDA11
MDA15
MDA28

QSA1
QSA2

QMA1
QMA2

QSA#1
QSA#2

MDA20

Z

4

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

T8

R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7
K

7

K9

K1

L2

J

3

K

3

L

3

F3
C7

E7
D3

G

3

B

7

T

2

L8

Q0

J1

L

1
J9
L9

U

U

V3

@

V3

@

V

REFCA

V

REFDQ

A

0

A

1

A

2

A

3

A

4

A

5

A

6

A

7

A

8

A

9

A

10/AP

A

11

A

12

A

13

A

14

A

15/BA3

B

A0

B

A1

B

A2

C

K

C

K

C

KE/CKE0

O

DT/ODT0

C

S/CS0

R

AS

C

AS

W

D

QSL

D

QSU

D

ML

D

MU

D

QSL

D

QSU

R

ESET

Z

Q/ZQ0

N

C/ODT1

N

C/CS1

N

C/CE1

N

CZQ1

K4B1G1646E-HC12_FBGA96

K4B1G1646E-HC12_FBGA96

E

3

10mA

9

9

6-BALL

6-BALL

SDRAM DDR3

SDRAM DDR3

D

QL0

D

QL1

D

QL2

D

QL3

D

QL4

D

QL5

D

QL6

D

QL7

D

QU0

D

QU1

D

QU2

D

QU3

D

QU4

D

QU5

D

QU6

D

QU7

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DDQ

V

DDQ

V

DDQ

V

DDQ

DDQ

V

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9

D2

E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

M

DA9

M

DA12

M

DA8

M

DA15

M

DA13

M

DA11

M

DA10

M

DA14

M

DA18

M

DA22

M

DA16

M

DA23

M

DA17

M

DA20

M

DA19

M

DA21

+

VRAM_1.5VS

+

VRAM_1.5VS

G

roup1

Group2

3

243_0402_1%

243_0402_1%

+

MEM_VREF_CA0

+

MEM_VREF_DQ0

OPT@

OPT@

V61

V61

R

R

2

M

ode E

Address

CMD0

Rank 0 Rank 1

0..31

ODT

CMD1

CMD2

CMD3

CMD4

V4

@

V4

@

U

U

M8

REFCA

V

H1

V

REFDQ

N3

C

MDA7

C

MDA10

C

MDA24

C

MDA6

C

MDA22

C

MDA26

C

MDA5

C

MDA21

C

MDA8

C

MDA4

C

MDA25

C

MDA23

C

MDA9

C

MDA12

C

MDA14

C

MDA29

C

MDA13

C

MDA27

C

LKA0

C

LKA0#

C

MDA3

C

MDA0

C

MDA2

C

MDA11

C

MDA15

C

MDA28

D

QSA0

D

QSA3

D

QMA0

D

QMA3

D

QSA#0

D

QSA#3

C

MDA20

Z

Q1

1

2

0

A

P7

1

A

P3

2

A

N2

3

A

P8

4

A

P2

5

A

R8

6

A

R2

7

A

T8

8

A

R3

9

A

L7

10/AP

A

R7

11

A

N7

12

A

T3

13

A

T7

A

14

M7

A

15/BA3

M2

A0

B

N8

A1

B

M3

B

A2

J7

K

C

7

K

K

C

K9

KE/CKE0

C

K1

DT/ODT0

O

L2

S/CS0

C

3

J

AS

R

3

K

AS

C

3

L

E

W

310mA

F3

QSL

D

C7

QSU

D

E7

ML

D

D3

MU

D

3

G

QSL

D

7

B

QSU

D

2

T

ESET

R

L8

Q/ZQ0

Z

J1

C/ODT1

N

1

L

C/CS1

N

J9

C/CE1

N

L9

N

CZQ1

6-BALL

6-BALL

9

9
SDRAM DDR3

SDRAM DDR3

K4B1G1646E-HC12_FBGA96

K4B1G1646E-HC12_FBGA96

E3

M

F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

DA6

M

DA1

M

DA5

M

DA0

M

DA4

M

DA2

M

DA7

M

DA3

M

DA30

M

DA26

M

DA29

M

DA24

M

DA28

M

DA27

M

DA31

M

DA25

+

VRAM_1.5VS

+

VRAM_1.5VS

Group0

Group3

P

lace close to t he first T poin t

C

LKA0<14,20>

C

LKA0#<14,20>

QL0

D

QL1

D

QL2

D

QL3

D

QL4

D

QL5

D

QL6

D

QL7

D

QU0

D

QU1

D

QU2

D

QU3

D

QU4

D

QU5

D

QU6

D
D

QU7

DD

V

DD

V

DD

V

DD

V

DD

V
V

DD

V

DD

V

DD

V

DD

DDQ

V

DDQ

V

DDQ

V

DDQ

V
V

DDQ
DDQ

V

DDQ

V

DDQ

V

DDQ

V

SS

V

SS

V

SS

V

SS

V

SS

V
V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

CMD5

CMD6

CMD7

CMD8

CMD9

CMD10

CMD11

CMD12

CMD13

CMD14

CMD15

CMD16

CMD17

CMD18

CMD19

CMD20

CMD21 A7

CMD22

CMD23

CMD24

CMD25

CMD26

CMD27

CMD28

CMD29

CMD30

1

OPT@

OPT@

V63

V63

R

R
160_0402_1%

160_0402_1%

2

CS0#

CKE

A9

A6

A3

A0

A8

A12

A1

RAS#

A13

BA1

A14

CAS#

RST

A7

A4

A11

A2

A10

A5

BA2

WE#

BA0

1

2..63

3

0..31 32..63

ODT

CS1#

CKE

A11

A6

A3

A

A8

A12 A0

A1

0

A7 A7

BA1 BA1

A12 A12

A8 A8

A0

A2 A2

RAS# RAS# RAS#

A13

A14

A3

A14

CAS#

A13 A13

CAS# CAS#

ODT

CS0#

CKE

RST RST RST

A6

A4

A11

A2

A10

A5

A5 A5

A9 A9

A1 A1

WE# WE#

A4 A4

BA2

WE#

BA0

A10 A10

BA0 BA0

BA2

A11A9

A14

A3BA1

ODT

CS1#

CKE

A6

BA2

Place close to RANK0 VRAM

+

VRAM_1.5VS

1

1

1

V68

V68

V67

V67
C

C

C

C

2

2

2

OPT@

OPT@

OPT@

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

A A

5

4

1

1

V70

V70

V69

V69

C

C

C

C

2

2

OPT@

OPT@

OPT@

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

V71

V71

V72

V72

C

C

C

C

2

2

OPT@

OPT@

OPT@

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

1

1

V73

V73
C

C

2

OPT@

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

1

V75

V75

V76

V74

V74
C

C

OPT@

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

V76

C

C

C

C

2

2

OPT@

OPT@

OPT@

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

ecurity Classification

ecurity Classification

ecurity Classification

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

+

VRAM_1.5VS

1

1

V77

V77
C

C

2

2

OPT@

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

012/12/07 2013/12/07

012/12/07 2013/12/07

012/12/07 2013/12/07

2

2

2

1

1

V79

V79

V78

V78
C

C

C

C

2

2

OPT@

OPT@

OPT@

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

eciphered Date

eciphered Date

eciphered Date

D

D

D

1

V80

V80
C

C

2

OPT@

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

V83

V81

V81
C

C

OPT@

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

V83

V82

V82

C

C

C

C

2

2

OPT@

OPT@

OPT@

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

2

1

2

0.1U_0402_10V7K

0.1U_0402_10V7K

1

1

V85

V85

V84

V84
C

C

C

C

2

2

OPT@

OPT@

OPT@

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

+

VRAM_1.5VS

1

V87

V86

V86
C

C

OPT@

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

Title

Title

T

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

ustom

ustom

ustom

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

V87
C

C

2

OPT@

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

GA_N14x VRAM RANK 0L

GA_N14x VRAM RANK 0L

GA_N14x VRAM RANK 0L

V

V

V

18 56Monday, March 11, 2013

18 56Monday, March 11, 2013

1

18 56Monday, March 11, 2013

f

f

f

o

o

o

.2

.2

.2

0

0

0