Page 1
Page 2
Page 3
5
B
+
D D
I
peak=8.13A, Imax=5.69A, Iocp min=8.7
USP#
S
SY8032ABC
S
USP#
T
PS22966DPUR
RT8243AZQW
Ipeak=5A, Imax=3.5A, Iocp min=6.2A
C C
S
USP#
T
PS22966DPUR
V
R_ON
5
NCP81012BMNR
SUSP#
S
Y8208QKC
S
YSON
R
T8207M
D
GPU_PWR_EN
N
CP81172MNTWG
Ipeak=20.53A, Imax=14.37A, Iocp min=23.91A
V
GA_PWROK#
N
-CHANNEL
AO3416
V
CCP_PWRGOOD
G
978F11U
I
peak=15A, Imax=10.5A, Iocp min=18A
0
.75VR_ON
S
USP
N-CHANNEL
F
DS6676AS
1
.5_PWR_EN#
N
-CHANNEL
FDS6676AS
I
peak=59A, Imax=45.7A, Iocp min=70A
B B
A A
4
P
CH_PWR_EN#
P-CHANNEL
O-3413
A
K
B_LED
P-CHANNEL
A
O-3413
+
5VS
L
DO
G
9191-330T1U
O
DD_EN#
P-CHANNEL
AO-3413
W
OWL_EN#
P
-CHANNEL
A
O-3413
P
CH_PWR_EN#
P-CHANNEL
AO-3413
L
CD_ENVDD
A
PL3512ABI
D
GPU_PWR_EN
P-CHANNEL
A
O-3413
4
ESIGN CURRENT 0 .1A
D
D
ESIGN CURRENT 5 A
D
ESIGN CURRENT 2 A
D
ESIGN CURRENT 6 A
D
ESIGN CURRENT 4 00mA
D
ESIGN CURRENT 3 00mA
D
ESIGN CURRENT 1 .6A
D
ESIGN CURRENT 5 A
D
ESIGN CURRENT 3 30mA
D
ESIGN CURRENT 3 A
DESIGN CURRENT 6A
D
ESIGN CURRENT 1 .5A
D
ESIGN CURRENT 0 .1A
D
ESIGN CURRENT 6 5A
D
ESIGN CURRENT 4 0A
D
ESIGN CURRENT 3 A
D
ESIGN CURRENT 6 A
D
ESIGN CURRENT 2 A
D
ESIGN CURRENT 1 .5A
D
ESIGN CURRENT 2 A
DESIGN CURRENT 2A
D
ESIGN CURRENT 1 1A
D
ESIGN CURRENT 3 0A
+
3VL
+
5VALW
+
5VALW_PCH
+
1.8VS
+
5VS
+
5VS_LED
+
3VS_HDP
+
5VS_ODD
+
3VALW
+
3V_LAN
+
3V_WLAN
+
3VALW_PCH
+
3VS
+
LCD_VDD
+
3VS_DGPU
+CPU_CORE
+
GFX_CORE
+1.05VS_VCCP
+
1.05VS_DGPU
+
VCCSA
+1.5V
+0.75VS
+
1.5V_CPU
+
1.5VS
+
VRAM_1.5VS
+
VGA_CORE
3
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
2
2
2
C
C
C
ompal Secret Data
ompal Secret Data
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
ompal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
1
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
T
itle
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
V
V
V
FKAA
FKAA
FKAA
P
P
P
ower Tree
ower Tree
ower Tree
1
3
o
3
3
o
o
f
56Monday, March 11, 2013
f
56Monday, March 11, 2013
f
56Monday, March 11, 2013
0
0
0
.2
.2
.2
Page 4
A
(
oltage Rails
V
power
1 1
2 2
S
5 S4/ Battery only
S5 S4/AC & Battery
don't exist
plane
State
S0
S1
S
3
S5 S4/AC
P
CH SM Bus Address
O MEANS ON X MEANS OFF )
+RTCVCC
O
O
O
O
O
O
B
O
O
O
O
O
X
+5VL
+
+
3VL
O
O
O
O
O
X
B
+5VALW
+
3VALW
O
O
O
O
X
X
+1.5V
O
X
X
X
+5VS
+3VS
+1.8VS
+1.5VS
+
1.05VS
+0.75VS
+
CPU_CORE
+
VGA_CORE
+GFX_CORE
+
VTT
+VRAM_1.5V S
+3VS_DGPU
+1.05VS_DG PU
OO
OO
X
X
X
X
C
TO Option Table
B
unction
F
description
explain
BTO
Function
description
explain
BTO
F
unction
description
explain
BTO
F
unction
description
explain
BTO
SKU
Optimus
Optimus
OPT@
LVDS-eDP
LVDS-eDP
LVDS eDP
LVDS@ IEDP@
WOWL
WOWL
w/
WOWL@
Sleep & Music
Sleep & Music
w/ S&M w/o S&M
269@ 259@
Panther Point
HM76R1@
HM76R3@ HM70R3@
w/o
NOWOWL@
PCH
HM70HM76
HM70R1@
Camera & Mic
Camera & Mic
Camera & Mic
CAM_EMI@
G-SENSOR
G-SENSOR
G-SENSOR
GSENSOR@
KB Light
K
B Light
KB Light
KBL@
D
G
PU
N14M-GL
N14MGL@
N14MGLR1@ N14PGV2R1@
N14MGLR3@ N14PGV2R3@
14640 14641
14640
14640@
ZPODD@
EMI/ESD part
EMI/ESD part
EMI/ESD part
EMI@ ESD@
USB S&C
w/
N14P-GV2
N14P-GV2N14M-GL
N14PGV2@
14641
14641@
ZPODD
ZPODD
w/o
NONZP@
VRAM
Dual Rank
Dual Rank
DRANK@
CRT
CRT
w/ CRT w/o CRT
CRT@ CRT_EMI@ NOCRT@
GCLK
GCLK
GCLK non-GCLK
GCLK@
non-GCLK
EC
EC
KB9012 NPCE885N
9012@ 885@
NOGCLK@
E
Touch Screen
Touch Screen
Touch Screen
TOUCH_EMI@
VRAM SKU for GV2
Single Rank
Single Rank
GVSR@
ISPD
HDMI Logo
HDMI Logo
HDMI45@
Dual Rank
Dual Rank
GVDR@
HEX
0001 0110 bSmart Battery
Address
1
010 0000 bA0 H
1010 0100 bA4 H
PowerPower
+3VS
+3VS
+3VS
E
C SM Bus2 Address
D
evice
9
6 H
1
E H
0 H
001 0110 bPCH
0100 0000 b
NVIDIA GPU 1001 1010 b
G-Sensor
B
9
4
S
TATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
G
3 LOW LOWLOW
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
SIGNAL
SLP_S3# SLP_S4# SLP_S5#
HIGH HIGHHIGH
LOW
LOW LOW
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
HIGH HIGHHIGH
HIGH
L
OW LOWLOW
HIGH
HIGH
D
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
T
itle
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
Date: Sheet
ompal Electronics, Inc.
N
N
N
otes List
otes List
otes List
V
V
V
FKAA
FKAA
FKAA
4 56Monday, March 11, 2013
4 56Monday, March 11, 2013
4 56Monday, March 11, 2013
E
o
o
o
f
f
f
0
0
0
.2
.2
.2
Power
+3VS
+
3VS
3 3
4 4
+3VS
+
3VS 2C H 0010 1100 bTouch Pad
+3VL
+3VL USB S&C 14640 35 H 0011 0101 b
Device
DDR SO-DIMM 0
DDR SO-DIMM 1
W
LAN/WIMAX
E
C SM Bus1 Address
D
evice Address Address
A
HEX HEX
16 H
12 H 0001 0010 bSmart Charger+3VL
Page 5
5
4
3
2
1
CPUB
CPUB
J
J
1
00 MHz
B
B
B
B
B
B
B
B
B
CLK#
B
RDY#
P
REQ#
P
RST#
T
D
PM#[0]
PM#[1]
PM#[2]
PM#[3]
PM#[4]
PM#[5]
PM#[6]
PM#[7]
A28
CLK
A27
120 MHz
A16
C
LK_CPU_EDP
A15
C
LK_CPU_EDP#
R8
H
_DRAMRST#
AK1
S
M_RCOMP_0
A5
S
M_RCOMP_1
A4
S
M_RCOMP_2
AP29
AP27
AR26
X
CK
T
MS
T
T
DO
T
BR#
DP_TCK
AR27
X
DP_TMS
AP30
X
DP_TRST#
AR28
X
DP_TDI
DI
AP26
X
DP_TDO
AL35
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
C
C
LK_CPU_DMI <26>
C
LK_CPU_DMI# <26>
C
LK_CPU_EDP <26>
C
LK_CPU_EDP# <26>
H
_DRAMRST# <7>
C56 140_0402_1%
C56 140_0402_1%
R
R
C59 25.5_0402_1%
C59 25.5_0402_1%
R
R
R
R
C61 200_0402_1%
C61 200_0402_1%
12
12
2
1
T
13 PADT13 PAD
T
15 PADT15 PAD
2
1
C55 51_0402_5%
C55 51_0402_5%
R
R
T
7 PADT7 PAD
T
10 PADT10 PAD
lose to CPU side
@
@
12
P
M_DRAM_PWR GD_R
C621000P_0402_50V7K
C621000P_0402_50V7K
C
C
ESD@
ESD@
2
D D
C C
by ESD requestion and place near CPU
+
1.05VS_VCCP
R
R
C44 62_0402_5%
C44 62_0402_5%
2
R
R
C45 10K_0402_5%
C45 10K_0402_5%
+
3VALW_PCH
2
C11 200_0402_5%
C11 200_0402_5%
R
R
D
RAMPWROK<27>
1
2
1
1
@
@
2
1
@
@
12
@
@
12
P
lease place near JCPU
1
D
RAMPWROK
10K_0402_5%
10K_0402_5%
2
C13
C13
R
R
+
3VS
H
_PWRGOOD
C63180P_0402_50V8J
C63180P_0402_50V8J
C
C
H
_PROCHOT#
H
_PWRGOOD
C
C
C701000P_0402_50V7K
C701000P_0402_50V7K
H
C671000P_0402_50V7K
C671000P_0402_50V7K
C
C
C661000P_0402_50V7K
C661000P_0402_50V7K
C
C
_PM_SYNC
B
UF_CPU_RST#
+
3VALW_PCH
1
1
B
2
A
H
_PROCHOT#<41>
H
_PECI
0
206: Delete 0.1uF
C3
C3
U
U
5
74AHC1G09GW_TSSOP5
74AHC1G09GW_TSSOP5
P
4
P
M_SYS_PWRGD_BUF
O
G
3
H
_PWRGOOD<30>
H
_SNB_IVB#<30>
H
_PROCHOT#
H
_PM_SYNC<27>
P
M_SYS_PWRGD_BUF
+
1.5V_CPU
12
R
R
C14
C14
200_0402_5%
200_0402_5%
H
C159 56_0402_5%
C159 56_0402_5%
R
R
H
_THERMTRIP#<30>
H
_PWRGOOD
1 PADT1 PAD
T
T
2 PADT2 PAD
_PECI<41>
1 2
C183 0_0402_5%
C183 0_0402_5%
R
R
1 2
C170 1 30_0402_5%
C170 1 30_0402_5%
R
R
1 2
Rshort@
Rshort@
B
UF_CPU_RST#
H
_SNB_IVB#
T
P_SKTOCC#
H
_CATERR#
H
_PECI
H
_PROCHOT#_R
H
_PM_SYNC
H
_PWRGOOD_R
P
M_DRAM_PWR GD_R
C26
ROC_SELECT#
P
AN34
KTOCC#
S
AL33
ATERR#
C
AN33
ECI
P
AL32
ROCHOT#
P
AN32
HERMTRIP#
T
AM34
M_SYNC
P
AP33
NCOREPWRGOOD
U
V8
M_DRAMPWROK
S
AR33
ESET#
R
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
Conn@
Conn@
PLL_REF_CLK
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
D
PLL_REF_CLK#
D
LOCKS
LOCKS
C
C
M_DRAMRST#
S
M_RCOMP[0]
S
M_RCOMP[1]
S
DR3
DR3
M_RCOMP[2]
S
MISC
MISC
D
D
TAG & BPM
TAG & BPM
J
J
Stuff R41 and R42 if do not support eDP
+
1.05VS_VCCP
C
LK_CPU_EDP#
C
LK_CPU_EDP
H
_DRAMRST#
b
y ESD requestion and place near CPU
D
DR3 Compensatio n Signals
Layout Note:Pla ce these
resistors near Processor
1 2
R
R
C157 1K_0402_5%LVDS@
C157 1K_0402_5%LVDS@
1
R
R
C158 1K_0402_5%LVDS@
C158 1K_0402_5%LVDS@
@ESD@
@ESD@
1 2
C34 180P_0402_50V8J
C34 180P_0402_50V8J
C
C
2
B B
F
AN Control Circuit
+
B
uffered Reset to CPU
+
3VS
0206: Delete 0.1uF
P
LT_RST# <29,35,36,41>
C2
C2
U
U
1
E#
O
2
N
I
3
ND
A A
G
74AHC1G125GW_SOT353-5
74AHC1G125GW_SOT353-5
5
5
CC
V
4
B
UT
O
UFO_CPU_RST#
+
1.05VS_VCCP
1
R
R
75_0402_5%
75_0402_5%
2
C38
C38
R
R
C35
C35
43_0402_1%
43_0402_1%
1
2
B
UF_CPU_RST#
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
5VS
1
A
1
1 0_0603_5%
1 0_0603_5%
R
R
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
Rshort@
Rshort@
+
2
+
FAN1
F
AN_SPEED1<41>
2
3VS
12
2
2
R
R
10K_0402_5%
10K_0402_5%
F
ANPWM<41>
+
FAN1
12
1
1
D
D
BAS16_SOT23-3
BAS16_SOT23-3
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
Title
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
Date: Sheet
ompal Electronics, Inc.
I
I
I
vy Bridge_JTAG/XDP/FAN
vy Bridge_JTAG/XDP/FAN
vy Bridge_JTAG/XDP/FAN
V
V
V
FKAA
FKAA
FKAA
J
J
FAN
FAN
6
G
5
G
4
4
3
3
2
2
1
1
ACES_50273-0040N-001
ACES_50273-0040N-001
Conn@
Conn@
1
C
C
5
5
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1
6
5
0
0
0
.2
.2
.2
o
o
o
f
5 56Monday, March 11, 2013
f
5 56Monday, March 11, 2013
f
5 56Monday, March 11, 2013
Page 6
5
4
3
2
1
+
1.05VS_VCCP
R
R
C1
C1
24.9_0402_1%
J
J
CPUA
CPUA
D D
C C
+
1.05VS_VCCP
e
DP_COMP signals should be
shorted near balls and
routed with typical
impedance <25m ohm
B B
+
1.05VS_VCCP
D
MI_PTX_CRX_N0<27>
D
MI_PTX_CRX_N1<27>
D
MI_PTX_CRX_N2<27>
D
MI_PTX_CRX_N3<27>
D
MI_PTX_CRX_P0<27>
D
MI_PTX_CRX_P1<27>
D
MI_PTX_CRX_P2<27>
D
MI_PTX_CRX_P3<27>
D
MI_CTX_PRX_N0<27>
D
MI_CTX_PRX_N1<27>
D
MI_CTX_PRX_N2<27>
D
MI_CTX_PRX_N3<27>
D
MI_CTX_PRX_P0<27>
D
MI_CTX_PRX_P1<27>
D
MI_CTX_PRX_P2<27>
D
MI_CTX_PRX_P3<27>
F
DI_CTX_PRX_N0<27>
F
DI_CTX_PRX_N1<27>
F
DI_CTX_PRX_N2<27>
F
DI_CTX_PRX_N3<27>
F
DI_CTX_PRX_N4<27>
F
DI_CTX_PRX_N5<27>
F
DI_CTX_PRX_N6<27>
F
DI_CTX_PRX_N7<27>
F
DI_CTX_PRX_P0<27>
F
DI_CTX_PRX_P1<27>
F
DI_CTX_PRX_P2<27>
F
DI_CTX_PRX_P3<27>
F
DI_CTX_PRX_P4<27>
F
DI_CTX_PRX_P5<27>
F
DI_CTX_PRX_P6<27>
F
DI_CTX_PRX_P7<27>
F
DI_FSYNC0<27>
F
DI_FSYNC1<27>
F
DI_INT<27>
F
DI_LSYNC0<27>
F
DI_LSYNC1<27>
2
1
R
R
C2 24.9_0402_1%
C2 24.9_0402_1%
H
_EDP_AUXP<22>
H
_EDP_AUXN<22>
H
_EDP_TXP0<22>
H
_EDP_TXP1<22>
H
_EDP_TXN0<22>
H
_EDP_TXN1<22>
E
DP_COMP
H
_EDP_HPD#
B27
D
MI_RX#[0]
B25
D
MI_RX#[1]
A25
D
MI_RX#[2]
B24
D
MI_RX#[3]
B28
D
MI_RX[0]
B26
MI_RX[1]
D
A24
MI_RX[2]
D
B23
MI_RX[3]
D
G21
MI_TX#[0]
D
E22
MI_TX#[1]
D
F21
MI_TX#[2]
D
D21
MI_TX#[3]
D
G22
MI_TX[0]
D
D22
MI_TX[1]
D
F20
MI_TX[2]
D
C21
MI_TX[3]
D
A21
DI0_TX#[0]
F
H19
DI0_TX#[1]
F
E19
DI0_TX#[2]
F
F18
DI0_TX#[3]
F
B21
DI1_TX#[0]
F
C20
DI1_TX#[1]
F
D18
DI1_TX#[2]
F
E17
DI1_TX#[3]
F
A22
DI0_TX[0]
F
G19
DI0_TX[1]
F
E20
DI0_TX[2]
F
G18
DI0_TX[3]
F
B20
DI1_TX[0]
F
C19
DI1_TX[1]
F
D19
DI1_TX[2]
F
F17
DI1_TX[3]
F
J18
DI0_FSYNC
F
J17
DI1_FSYNC
F
H20
DI_INT
F
J19
DI0_LSYNC
F
H17
DI1_LSYNC
F
A18
DP_COMPIO
e
A17
DP_ICOMPO
e
B16
DP_HPD#
e
C15
DP_AUX
e
D15
DP_AUX#
e
C17
DP_TX[0]
e
F16
DP_TX[1]
e
C16
DP_TX[2]
e
G15
DP_TX[3]
e
C18
DP_TX#[0]
e
E16
DP_TX#[1]
e
D16
DP_TX#[2]
e
F15
DP_TX#[3]
e
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
Conn@
Conn@
DMI
DMI
ntel(R) FDI
ntel(R) FDI
I
I
DP
DP
e
e
P
P
EG_RCOMPO
P
P
P
P
P
P
P
P
CI EXPRESS* - GRAPHICS
CI EXPRESS* - GRAPHICS
P
P
P
P
P
P
P
EG_ICOMPI
EG_ICOMPO
EG_RX#[0]
P
EG_RX#[1]
P
EG_RX#[2]
P
EG_RX#[3]
P
EG_RX#[4]
P
EG_RX#[5]
P
EG_RX#[6]
P
EG_RX#[7]
P
EG_RX#[8]
P
EG_RX#[9]
P
EG_RX#[10]
EG_RX#[11]
EG_RX#[12]
EG_RX#[13]
EG_RX#[14]
EG_RX#[15]
EG_RX[0]
P
EG_RX[1]
P
EG_RX[2]
P
EG_RX[3]
P
EG_RX[4]
P
EG_RX[5]
P
EG_RX[6]
P
EG_RX[7]
P
EG_RX[8]
P
EG_RX[9]
P
EG_RX[10]
P
EG_RX[11]
P
EG_RX[12]
P
EG_RX[13]
P
EG_RX[14]
P
EG_RX[15]
P
EG_TX#[0]
P
EG_TX#[1]
P
EG_TX#[2]
P
EG_TX#[3]
P
EG_TX#[4]
P
EG_TX#[5]
P
EG_TX#[6]
P
EG_TX#[7]
P
EG_TX#[8]
P
EG_TX#[9]
P
EG_TX#[10]
EG_TX#[11]
EG_TX#[12]
EG_TX#[13]
EG_TX#[14]
EG_TX#[15]
EG_TX[0]
P
EG_TX[1]
P
EG_TX[2]
P
EG_TX[3]
P
EG_TX[4]
P
EG_TX[5]
P
EG_TX[6]
P
EG_TX[7]
P
EG_TX[8]
P
EG_TX[9]
P
EG_TX[10]
P
EG_TX[11]
P
EG_TX[12]
P
EG_TX[13]
P
EG_TX[14]
P
EG_TX[15]
P
J22
J21
H22
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
P
EG_COMP
P
CIE_GTX_C_CRX_N0
P
CIE_GTX_C_CRX_N1
P
CIE_GTX_C_CRX_N2
P
CIE_GTX_C_CRX_N3
P
CIE_GTX_C_CRX_P0
P
CIE_GTX_C_CRX_P1
P
CIE_GTX_C_CRX_P2
P
CIE_GTX_C_CRX_P3
P
CIE_CTX_GRX_N0
P
CIE_CTX_GRX_N1
P
CIE_CTX_GRX_N2
P
CIE_CTX_GRX_N3
P
CIE_CTX_GRX_P0
P
CIE_CTX_GRX_P1
P
CIE_CTX_GRX_P2
P
CIE_CTX_GRX_P3
24.9_0402_1%
1 2
C
C
C8 0.22U_0402_16V7K
C8 0.22U_0402_16V7K
1 2
C
C
C11 0.22U_040 2_16V7K
C11 0.22U_040 2_16V7K
1
C16 0.22U_040 2_16V7K
C16 0.22U_040 2_16V7K
C
C
1
C
C
C20 0.22U_040 2_16V7K
C20 0.22U_040 2_16V7K
1 2
C10 0.22U_040 2_16V7K
C10 0.22U_040 2_16V7K
C
C
1 2
C
C
C5 0.22U_0402_16V7K
C5 0.22U_0402_16V7K
1
C6 0.22U_0402_16V7K
C6 0.22U_0402_16V7K
C
C
1 2
C7 0.22U_0402_16V7K
C7 0.22U_0402_16V7K
C
C
IVY Bridge
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
12
impedance = 43 m ohm (4 mils)
PEG_ICOMPO signals should be routed with Âmax length = 500 mils
- typical impedance = 14.5 m ohm (12 mils)
P
CIE_GTX_C_CRX_N[0..3] <13>
P
CIE_GTX_C_CRX_P[0..3] <13>
P
CIE_CTX_C_GRX_N0
P
2
2
2
CIE_CTX_C_GRX_N1
P
CIE_CTX_C_GRX_N2
P
CIE_CTX_C_GRX_N3
P
CIE_CTX_C_GRX_P0
P
CIE_CTX_C_GRX_P1
P
CIE_CTX_C_GRX_P2
P
CIE_CTX_C_GRX_P3
PEG DG suggest AC cap
Gen1/Gen2
75 nF~265 nF
P
CIE_CTX_C_GRX_N[0..3] <1 3>
P
CIE_CTX_C_GRX_P[0..3] <13>
Gen3 180 nF~265 nF
C9
C9
R
R
1K_0402_5%
1K_0402_5%
1 2
H
_EDP_HPD#
1
UT
O
C
PU_EDP_HPD<22>
A A
2
I
N
ND
G
Q
Q
C1
C1
DTC124EKAT146_SC59-3
DTC124EKAT146_SC59-3
3
IEDP@
IEDP@
SANDY Bridge Gen1/Gen2 180 nF~265 nF
NV N14x Gen1/2/3 Suggest 220 nF
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
T
itle
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
2
Date: Sheet
ompal Electronics, Inc.
I
I
I
vy Bridge_DMI/PEG/FDI
vy Bridge_DMI/PEG/FDI
vy Bridge_DMI/PEG/FDI
V
V
V
FKAA
FKAA
FKAA
1
0
0
0
.2
.2
.2
o
o
o
f
6 56Monday, March 11, 2013
f
6 56Monday, March 11, 2013
f
6 56Monday, March 11, 2013
Page 7
5
CPUC
CPUC
J
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
G10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AK8
AK9
AH8
AH9
AE8
AD9
J
C5
S
A_DQ[0]
D5
S
A_DQ[1]
D3
S
A_DQ[2]
D2
S
A_DQ[3]
D6
S
A_DQ[4]
C6
S
A_DQ[5]
C2
S
A_DQ[6]
C3
S
A_DQ[7]
F10
S
A_DQ[8]
F8
S
A_DQ[9]
S
A_DQ[10]
G9
S
A_DQ[11]
F9
S
A_DQ[12]
F7
S
A_DQ[13]
G8
S
A_DQ[14]
G7
S
A_DQ[15]
K4
S
A_DQ[16]
K5
S
A_DQ[17]
K1
S
A_DQ[18]
J1
S
A_DQ[19]
J5
S
A_DQ[20]
J4
S
A_DQ[21]
J2
S
A_DQ[22]
K2
S
A_DQ[23]
M8
S
A_DQ[24]
N10
S
A_DQ[25]
N8
S
A_DQ[26]
N7
S
A_DQ[27]
S
A_DQ[28]
M9
S
A_DQ[29]
N9
S
A_DQ[30]
M7
S
A_DQ[31]
S
A_DQ[32]
S
A_DQ[33]
S
A_DQ[34]
S
A_DQ[35]
S
A_DQ[36]
S
A_DQ[37]
AJ5
S
A_DQ[38]
AJ6
S
A_DQ[39]
AJ8
S
A_DQ[40]
S
A_DQ[41]
AJ9
S
A_DQ[42]
S
A_DQ[43]
S
A_DQ[44]
S
A_DQ[45]
AL9
S
A_DQ[46]
AL8
S
A_DQ[47]
S
A_DQ[48]
S
A_DQ[49]
S
A_DQ[50]
S
A_DQ[51]
S
A_DQ[52]
S
A_DQ[53]
S
A_DQ[54]
S
A_DQ[55]
S
A_DQ[56]
S
A_DQ[57]
S
A_DQ[58]
S
A_DQ[59]
S
A_DQ[60]
S
A_DQ[61]
S
A_DQ[62]
S
A_DQ[63]
A_BS[0]
S
A_BS[1]
S
V6
A_BS[2]
S
A_CAS#
S
A_RAS#
S
AF9
A_WE#
S
DR SYSTEM MEMORY A
DR SYSTEM MEMORY A
D
D
DR_A_D[0..63]<11>
D
DR_A_D0
D
DR_A_D1
D
DR_A_D2
D
D
DR_A_D3
D
D D
C C
DR_A_BS0<11>
B B
D
DR_A_BS1<11>
D
DR_A_BS2<11>
D
DR_A_CAS#<11>
D
DR_A_RAS#<11>
D
DR_A_WE#<11>
D
DR_A_D4
D
DR_A_D5
D
DR_A_D6
D
DR_A_D7
D
DR_A_D8
DR_A_D9
D
DR_A_D10
D
DR_A_D11
D
DR_A_D12
D
DR_A_D13
D
DR_A_D14
D
DR_A_D15
D
DR_A_D16
D
DR_A_D17
D
DR_A_D18
D
DR_A_D19
D
DR_A_D20
D
DR_A_D21
D
DR_A_D22
D
DR_A_D23
D
DR_A_D24
D
DR_A_D25
D
DR_A_D26
D
DR_A_D27
D
DR_A_D28
D
DR_A_D29
D
DR_A_D30
D
DR_A_D31
D
DR_A_D32
D
DR_A_D33
D
DR_A_D34
D
DR_A_D35
D
DR_A_D36
D
DR_A_D37
D
DR_A_D38
D
D
DR_A_D39
D
DR_A_D40
D
DR_A_D41
D
DR_A_D42
D
DR_A_D43
D
DR_A_D44
D
DR_A_D45
D
DR_A_D46
D
DR_A_D47
DR_A_D48
D
DR_A_D49
D
DR_A_D50
D
DR_A_D51
D
DR_A_D52
D
DR_A_D53
D
DR_A_D54
D
DR_A_D55
D
D
DR_A_D56
D
DR_A_D57
D
DR_A_D58
D
DR_A_D59
DR_A_D60
D
DR_A_D61
D
D
DR_A_D62
D
DR_A_D63
S
A_CLK[0]
S
A_CLK#[0]
S
A_CKE[0]
A_CLK[1]
S
S
A_CLK#[1]
A_CKE[1]
S
R
SVD_TP[1]
R
SVD_TP[2]
R
SVD_TP[3]
R
SVD_TP[4]
R
SVD_TP[5]
R
SVD_TP[6]
A_CS#[0]
S
A_CS#[1]
S
R
SVD_TP[7]
R
SVD_TP[8]
A_ODT[0]
S
A_ODT[1]
S
R
SVD_TP[9]
R
SVD_TP[10]
A_DQS#[0]
S
A_DQS#[1]
S
S
A_DQS#[2]
S
A_DQS#[3]
S
A_DQS#[4]
S
A_DQS#[5]
S
A_DQS#[6]
S
A_DQS#[7]
A_DQS[0]
S
S
A_DQS[1]
A_DQS[2]
S
S
A_DQS[3]
S
A_DQS[4]
S
A_DQS[5]
S
A_DQS[6]
S
A_DQS[7]
S
A_MA[0]
S
A_MA[1]
S
A_MA[2]
S
A_MA[3]
S
A_MA[4]
S
A_MA[5]
S
A_MA[6]
S
A_MA[7]
S
A_MA[8]
S
A_MA[9]
S
A_MA[10]
S
A_MA[11]
S
A_MA[12]
S
A_MA[13]
S
A_MA[14]
S
A_MA[15]
4
DR_B_D[0..63]<12>
D
AB6
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
D
DR_A_DQS#0
D
DR_A_DQS#1
D
DR_A_DQS#2
D
DR_A_DQS#3
D
DR_A_DQS#4
D
DR_A_DQS#5
D
DR_A_DQS#6
D
DR_A_DQS#7
DR_A_DQS0
D
DR_A_DQS1
D
D
DR_A_DQS2
DR_A_DQS3
D
D
DR_A_DQS4
D
DR_A_DQS5
D
DR_A_DQS6
D
DR_A_DQS7
DR_A_MA0
D
DR_A_MA1
D
DR_A_MA2
D
DR_A_MA3
D
DR_A_MA4
D
DR_A_MA5
D
DR_A_MA6
D
DR_A_MA7
D
DR_A_MA8
D
DR_A_MA9
D
DR_A_MA10
D
DR_A_MA11
D
DR_A_MA12
D
DR_A_MA13
D
DR_A_MA14
D
D
DR_A_MA15
DRA_CLK0 <11>
D
DRA_CLK0# <11>
D
DRA_CKE0 <11>
D
DRA_CLK1 <11>
D
DRA_CLK1# <11>
D
DRA_CKE1 <11>
D
DRA_SCS0# <11>
D
DRA_SCS1# <11>
D
DRA_ODT0 <11>
D
DRA_ODT1 <11>
D
DR_A_DQS#[0..7] <11>
D
DR_A_DQS[0..7] <11>
D
DR_A_MA[0..15] <11>
D
3
J
J
CPUD
CPUD
D
DR_B_D0
D
DR_B_D1
D
DR_B_D2
D
DR_B_D3
D
DR_B_D4
D
DR_B_D5
D
DR_B_D6
D
DR_B_D7
D
DR_B_D8
D
DR_B_D9
D
DR_B_D10
D
DR_B_D11
D
DR_B_D12
D
DR_B_D13
D
DR_B_D14
D
DR_B_D15
D
DR_B_D16
D
DR_B_D17
D
DR_B_D18
D
DR_B_D19
D
DR_B_D20
D
DR_B_D21
D
DR_B_D22
D
DR_B_D23
D
DR_B_D24
D
DR_B_D25
D
DR_B_D26
D
DR_B_D27
D
DR_B_D28
D
DR_B_D29
D
DR_B_D30
D
DR_B_D31
D
DR_B_D32
D
DR_B_D33
D
DR_B_D34
D
DR_B_D35
D
DR_B_D36
D
DR_B_D37
D
DR_B_D38
D
DR_B_D39
D
DR_B_D40
D
DR_B_D41
D
DR_B_D42
D
DR_B_D43
D
DR_B_D44
D
DR_B_D45
D
DR_B_D46
D
DR_B_D47
D
DR_B_D48
D
DR_B_D49
D
DR_B_D50
D
DR_B_D51
D
DR_B_D52
D
DR_B_D53
D
DR_B_D54
D
DR_B_D55
D
DR_B_D56
D
DR_B_D57
D
DR_B_D58
D
DR_B_D59
D
DR_B_D60
D
DR_B_D61
D
DR_B_D62
D
DR_B_D63
DR_B_BS0<12>
D
DR_B_BS1<12>
D
DR_B_BS2<12>
D
DR_B_CAS#<12>
D
DR_B_RAS#<12>
D
DR_B_WE#<12>
D
D10
K10
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
AA10
AB8
AB9
C9
B_DQ[0]
S
A7
B_DQ[1]
S
B_DQ[2]
S
C8
B_DQ[3]
S
A9
B_DQ[4]
S
A8
B_DQ[5]
S
D9
B_DQ[6]
S
D8
B_DQ[7]
S
G4
B_DQ[8]
S
F4
B_DQ[9]
S
F1
B_DQ[10]
S
G1
B_DQ[11]
S
G5
B_DQ[12]
S
F5
B_DQ[13]
S
F2
B_DQ[14]
S
G2
B_DQ[15]
S
J7
B_DQ[16]
S
J8
B_DQ[17]
S
B_DQ[18]
S
K9
B_DQ[19]
S
J9
B_DQ[20]
S
J10
B_DQ[21]
S
K8
B_DQ[22]
S
K7
B_DQ[23]
S
M5
B_DQ[24]
S
N4
B_DQ[25]
S
N2
B_DQ[26]
S
N1
B_DQ[27]
S
M4
B_DQ[28]
S
N5
B_DQ[29]
S
M2
B_DQ[30]
S
M1
B_DQ[31]
S
B_DQ[32]
S
B_DQ[33]
S
B_DQ[34]
S
B_DQ[35]
S
B_DQ[36]
S
B_DQ[37]
S
B_DQ[38]
S
B_DQ[39]
S
B_DQ[40]
S
B_DQ[41]
S
B_DQ[42]
S
B_DQ[43]
S
B_DQ[44]
S
B_DQ[45]
S
B_DQ[46]
S
B_DQ[47]
S
B_DQ[48]
S
B_DQ[49]
S
B_DQ[50]
S
B_DQ[51]
S
B_DQ[52]
S
B_DQ[53]
S
B_DQ[54]
S
B_DQ[55]
S
B_DQ[56]
S
B_DQ[57]
S
B_DQ[58]
S
B_DQ[59]
S
B_DQ[60]
S
B_DQ[61]
S
B_DQ[62]
S
B_DQ[63]
S
S
B_BS[0]
S
B_BS[1]
R6
S
B_BS[2]
S
B_CAS#
S
B_RAS#
S
B_WE#
2
AE2
S
B_CLK[0]
AD2
S
B_CLK#[0]
R9
S
B_CKE[0]
AE1
S
B_CLK[1]
AD1
S
B_CLK#[1]
R10
S
B_CKE[1]
AB2
SVD_TP[11]
R
R
R
R
R
R
R
R
R
R
DR SYSTEM MEMORY B
DR SYSTEM MEMORY B
D
D
SVD_TP[12]
SVD_TP[13]
SVD_TP[14]
SVD_TP[15]
SVD_TP[16]
B_CS#[0]
S
B_CS#[1]
S
SVD_TP[17]
SVD_TP[18]
S
B_ODT[0]
S
B_ODT[1]
SVD_TP[19]
SVD_TP[20]
S
B_DQS#[0]
S
B_DQS#[1]
S
B_DQS#[2]
B_DQS#[3]
S
S
B_DQS#[4]
S
B_DQS#[5]
S
B_DQS#[6]
S
B_DQS#[7]
S
B_DQS[0]
S
B_DQS[1]
S
B_DQS[2]
S
B_DQS[3]
S
B_DQS[4]
S
B_DQS[5]
S
B_DQS[6]
S
B_DQS[7]
B_MA[0]
S
B_MA[1]
S
B_MA[2]
S
B_MA[3]
S
B_MA[4]
S
B_MA[5]
S
B_MA[6]
S
B_MA[7]
S
B_MA[8]
S
B_MA[9]
S
B_MA[10]
S
B_MA[11]
S
B_MA[12]
S
B_MA[13]
S
B_MA[14]
S
B_MA[15]
S
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
D
DR_B_DQS#0
D
DR_B_DQS#1
D
DR_B_DQS#2
D
DR_B_DQS#3
D
DR_B_DQS#4
D
DR_B_DQS#5
D
DR_B_DQS#6
D
DR_B_DQS#7
D
DR_B_DQS0
D
DR_B_DQS1
D
DR_B_DQS2
D
DR_B_DQS3
D
DR_B_DQS4
D
DR_B_DQS5
D
DR_B_DQS6
D
DR_B_DQS7
D
DR_B_MA0
D
DR_B_MA1
D
DR_B_MA2
D
DR_B_MA3
D
DR_B_MA4
D
DR_B_MA5
D
DR_B_MA6
D
DR_B_MA7
D
DR_B_MA8
D
DR_B_MA9
D
DR_B_MA10
D
DR_B_MA11
D
DR_B_MA12
D
DR_B_MA13
D
DR_B_MA14
D
DR_B_MA15
DRB_CLK0 <12>
D
DRB_CLK0# <12>
D
DRB_CKE0 <12>
D
DRB_CLK1 <12>
D
DRB_CLK1# <12>
D
DRB_CKE1 <12>
D
DRB_SCS0# <12>
D
DRB_SCS1# <12>
D
DRB_ODT0 <12>
D
DRB_ODT1 <12>
D
DR_B_DQS#[0..7] <12>
D
DR_B_DQS[0..7] <12>
D
DR_B_MA[0..15] <12>
D
1
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
Conn@
Conn@
1.5V
+
12
R
R
C76
C76
1K_0402_5%
1K_0402_5%
C3
C3
Q
Q
D
S
D
S
3
1
DR3_DRAMRST#_R
_DRAMRST#<5>
H
4.99K_0402_1%
A A
RAMRST_CNTRL_PCH<26,9>
D
5
4.99K_0402_1%
1 2
Rshort@
Rshort@
C73 0_0402_5%
C73 0_0402_5%
R
R
2
R
R
C78
C78
1
RAMRST_CNTRL
D
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
G
G
2
1
C
C
C37
C37
0.047U_0402_25V6K
0.047U_0402_25V6K
2
D
4
R
R
C77
C77
1K_0402_5%
1K_0402_5%
1 2
M_DRAMRST# <11,12>
S
ecurity Classification
ecurity Classification
ecurity Classification
S
S
S
ssued Date
ssued Date
ssued Date
I
I
I
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
T
T
T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
2
2
2
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
Conn@
Conn@
ompal Secret Data
ompal Secret Data
ompal Secret Data
C
C
C
eciphered Date
eciphered Date
eciphered Date
D
D
D
ompal Electronics, Inc.
ompal Electronics, Inc.
ompal Electronics, Inc.
C
C
itle
itle
itle
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
ustom
ustom
ustom
C
C
C
Date: Sheet
Date: Sheet
2
Date: Sheet
C
vy Bridge_DDR3
vy Bridge_DDR3
vy Bridge_DDR3
I
I
I
FKAA
FKAA
FKAA
V
V
V
.2
.2
.2
0
0
0
f
7 56Monday, March 11, 2013
f
7 56Monday, March 11, 2013
f
7 56Monday, March 11, 2013
o
o
1
o
Page 8
5
CPU_CORE
+
J
J
CPUF
CPUF
53A
AG35
V
D D
C C
B B
A A
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
CC1
V
CC2
V
CC3
V
CC4
V
CC5
V
CC6
V
CC7
V
CC8
V
CC9
V
CC10
V
CC11
V
CC12
V
CC13
V
CC14
V
CC15
V
CC16
V
CC17
V
CC18
V
CC19
V
CC20
V
CC21
V
CC22
V
CC23
V
CC24
V
CC25
V
CC26
V
CC27
V
CC28
V
CC29
V
CC30
V
CC31
V
CC32
V
CC33
V
CC34
V
CC35
V
CC36
V
CC37
V
CC38
V
CC39
V
CC40
V
CC41
V
CC42
V
CC43
V
CC44
V
CC45
V
CC46
V
CC47
V
CC48
V
CC49
V
CC50
Y35
V
CC51
Y34
V
CC52
Y33
V
CC53
Y32
V
CC54
Y31
V
CC55
Y30
V
CC56
Y29
V
CC57
Y28
V
CC58
Y27
V
CC59
Y26
CC60
V
V35
CC61
V
V34
CC62
V
V33
CC63
V
V32
CC64
V
V31
CC65
V
V30
CC66
V
V29
CC67
V
V28
CC68
V
V27
CC69
V
V26
CC70
V
U35
CC71
V
U34
CC72
V
U33
CC73
V
U32
CC74
V
U31
CC75
V
U30
CC76
V
U29
CC77
V
U28
CC78
V
U27
CC79
V
U26
CC80
V
R35
CC81
V
R34
CC82
V
R33
CC83
V
R32
CC84
V
R31
CC85
V
R30
CC86
V
R29
CC87
V
R28
CC88
V
R27
CC89
V
R26
CC90
V
P35
CC91
V
P34
CC92
V
P33
CC93
V
P32
CC94
V
P31
CC95
V
P30
CC96
V
P29
CC97
V
P28
CC98
V
P27
CC99
V
P26
CC100
V
P
P
OWER
OWER
PEG AND DDR
PEG AND DDR
ORE SUPPLY
ORE SUPPLY
C
C
V
SS_SENSE_VCCIO
SENSE LINES SVID
SENSE LINES SVID
V
V
CCIO_SENSE
V
8.5A
CCIO1
V
CCIO2
V
CCIO3
V
CCIO4
V
CCIO5
V
CCIO6
V
CCIO7
V
CCIO8
V
CCIO9
V
CCIO10
V
CCIO11
V
CCIO12
V
CCIO13
V
CCIO14
V
CCIO15
V
CCIO16
V
CCIO17
V
CCIO18
V
CCIO19
V
CCIO20
V
CCIO21
V
CCIO22
V
CCIO23
V
CCIO24
V
CCIO25
V
CCIO26
V
CCIO27
V
CCIO28
V
CCIO29
V
CCIO30
V
CCIO31
V
CCIO32
V
CCIO33
V
CCIO34
V
CCIO35
V
CCIO36
V
CCIO37
V
CCIO38
V
CCIO39
V
CCIO40
V
V
IDALERT#
V
IDSCLK
V
IDSOUT
CC_SENSE
SS_SENSE
1.05VS_VCCP
+
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
AJ35
AJ34
B10
A10
R
R
10_0402_1%
10_0402_1%
H
_CPU_SVIDALRT#
1
C96
C96
2
Close to CPU
TYCO_2013620-2_IVY BRIDGEConn@
TYCO_2013620-2_IVY BRIDGEConn@
5
4
1.05VS_VCCP
+
1
1
1
C17
C17
C18
C18
C19
C19
C
C
C
C
C
C
2
ESD@
ESD@
100P_0402_50V8J
100P_0402_50V8J
2
2
ESD@
ESD@
ESD@
ESD@
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
by ESD requestion and place near CPU
+
12
R
R
C98
C98
10_0402_1%
10_0402_1%
1.05VS_VCCP
1
R
R
C91
C91
130_0402_5%
130_0402_5%
2
R
R
C90 43_0402 _1%
C90 43_0402 _1%
V
CCIO_SENSE <49>
+
1.05VS_VCCP
4
1 2
+
1.05VS_VCCP
1
2
R
R
C89
C89
75_0402_5%
75_0402_5%
P
ull high resistor on VR side
+
CPU_CORE
2
R
R
C93
C93
100_0402_1%
100_0402_1%
1
12
R
R
C97
C97
100_0402_1%
100_0402_1%
V
R_SVID_ALRT# <51>
V
R_SVID_CLK <51>
V
R_SVID_DAT <51>
3
2
Close to CPU
V
CCSENSE <51>
V
SSSENSE <51>
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
2
1
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
T
itle
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
Date: Sheet
ompal Electronics, Inc.
I
I
I
vy Bridge_POWER-1
vy Bridge_POWER-1
vy Bridge_POWER-1
V
V
V
FKAA
FKAA
FKAA
1
o
o
o
f
8 56Monday, March 11, 2013
f
8 56Monday, March 11, 2013
f
8 56Monday, March 11, 2013
0
0
0
.2
.2
.2
Page 9
5
+
GFX_CORE
CPUG
CPUG
J
J
33A
AT24
AXG1
V
AT23
AXG2
D D
C C
V
CCPLL Decoupling:
1X 10U, 1x 1U
2
1
Rshort@
+
1.8VS
B B
A A
Rshort@
C119 0_0805_5%
C119 0_0805_5%
R
R
10U_0603_6.3V6M
10U_0603_6.3V6M
C
C
C59
C59
+
1.8VS_VCCPLL
1
C
C
C60
C60
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
V
AT21
AXG3
V
AT20
AXG4
V
AT18
AXG5
V
AT17
AXG6
V
AR24
AXG7
V
AR23
AXG8
V
AR21
AXG9
V
AR20
AXG10
V
AR18
AXG11
V
AR17
AXG12
V
AP24
AXG13
V
AP23
AXG14
V
AP21
AXG15
V
AP20
AXG16
V
AP18
AXG17
V
AP17
AXG18
V
AN24
AXG19
V
AN23
AXG20
V
AN21
AXG21
V
AN20
AXG22
V
AN18
AXG23
V
AN17
AXG24
V
AM24
AXG25
V
AM23
AXG26
V
AM21
AXG27
V
AM20
AXG28
V
AM18
AXG29
V
AM17
AXG30
V
AL24
AXG31
V
AL23
AXG32
V
AL21
AXG33
V
AL20
AXG34
V
AL18
AXG35
V
AL17
AXG36
V
AK24
AXG37
V
AK23
AXG38
V
AK21
AXG39
V
AK20
AXG40
V
AK18
AXG41
V
AK17
AXG42
V
AJ24
AXG43
V
AJ23
AXG44
V
AJ21
AXG45
V
AJ20
AXG46
V
AJ18
AXG47
V
AJ17
AXG48
V
AH24
AXG49
V
AH23
AXG50
V
AH21
AXG51
V
AH20
AXG52
V
AH18
AXG53
V
AH17
AXG54
V
1.2A
B6
CCPLL1
V
A6
CCPLL2
V
A2
CCPLL3
V
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
Conn@
Conn@
4
OWER
OWER
P
P
ENSE
ENSE
S
S
S
REFMISC
REFMISC
S
V
V
RAPHICS
RAPHICS
G
G
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
A RAIL
A RAIL
S
S
.8V RAIL
.8V RAIL
1
1
AXG_SENSE
V
SSAXG_SENSE
V
LINES
LINES
M_VREF
S
A_DIMM_VREFDQ
B_DIMM_VREFDQ
5
A
DDQ1
V
DDQ2
V
DDQ3
V
DDQ4
V
DDQ5
V
DDQ6
V
DDQ7
V
DDQ8
V
DDQ9
V
DDQ10
V
DDQ11
V
DDQ12
V
DDQ13
V
DDQ14
V
DDQ15
V
6A
CCSA1
V
CCSA2
V
CCSA3
V
CCSA4
V
CCSA5
V
CCSA6
V
CCSA7
V
CCSA8
V
CCSA_SENSE
V
CCSA_VID[0]
V
CCSA_VID[1]
V
CCIO_SEL
V
AK35
AK34
+
V_SM_VREF should
have 20 mil trace width
AL1
B4
D1
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
+
V_SM_VREF
+
VREF_DQA_M3
+
VREF_DQB_M3
C
C
C57
C57
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
Bottom Socket Cavity
M27
10U_0603_6.3V6M
10U_0603_6.3V6M
M26
L26
J26
J25
J24
H26
H25
H23
C22
C24
A19
1
C
C
C42
C42
2
10U_0603_6.3V6M
10U_0603_6.3V6M
C
C
C41
C41
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
C
C
H
_VCCSA_VID0 < 50>
H
_VCCSA_VID1 < 50>
3
GFX_CORE
+
12
R
R
C105
C105
10_0402_1%
10_0402_1%
1
R
R
C106
C106
10_0402_1%
10_0402_1%
1
C
C
C65
C65
0.1U_0402_10V7K
0.1U_0402_10V7K
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
1
C52
C52
C55
C55
C
C
C
C
C
C
C51
C51
10U_0603_6.3V6M
10U_0603_6.3V6M
2
+
C
C
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
VCCSA Decoupling:
1X 47U (MLCC), 3X 10U
+
VCCSA
1
C43
C43
2
Bottom Socket Edge
1
C
C
C44
C44
47U_0805_6.3V6M
47U_0805_6.3V6M
@
@
2
P
lease kindly ch eck whether
there is pull-d own resister
in PWR-side or HW-side
1
0/3: confirmed with PWR, IC in tergrate PD
Close to CPU
2
+
R
R
C120
C120
1 2
1K_0402_0.5%
1K_0402_0.5%
1 2
1K_0402_0.5%
1K_0402_0.5%
R
R
C109
C109
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C
C
C54
C54
C56
C56
2
+
1.5V_CPU
C
C
C46 0.1U_0402_10V7K
C46 0.1U_0402_10V7K
C47 0.1U_0402_10V7K
C47 0.1U_0402_10V7K
C
C
C48 0.1U_0402_10V7K
C48 0.1U_0402_10V7K
C
C
C45 0.1U_0402_10V7K
C45 0.1U_0402_10V7K
C
C
V
CC_AXG_SENSE <51>
V
SS_AXG_SENSE <51>
1.5V_CPU
+
1.5V_CPU
1
12
C
C
C50
C50
47U_0805_6.3V6M
47U_0805_6.3V6M
@
@
2
1 2
@
@
1 2
@
@
1 2
@
@
1 2
@
@
2
ntel DDR Vref M3
I
+
VREF_DQA_M3
+
VREF_DQB_M3
+1.5V_CPU Decoupling:
1X 47U (MLCC), 6X 10U
0
0
1
1 1
+
1.5V
V
gs=10V,Id=14.5A ,Rds=6mohm
2
R
R
C203
C203
470_0805_5%
470_0805_5%
1
3
C5B
C5B
Q
Q
5
S
USP
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
4
1
C68
C68
C
C
10U_0603_6.3V6M
10U_0603_6.3V6M
2
0.1U_0402_25V6
0.1U_0402_25V6
Place near SO-DIMM side
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
S
S
3
G
G
2
G
G
2
3
S
S
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
+VCCSAVCCSA_VID0 VCCSA_VID1
0
1
0
0.90 V
0.80 V
0.725 V
0.675 V
+
1.5V_CPU
C
C
C69
C69
2
JUMP_43X39
JUMP_43X39
C4
C4
Q
Q
1
S
2
S
3
S
4
G
FDS6676AS_SO8
FDS6676AS_SO8
1
2
JP@
JP@
J1
J1
P
P
2
1
D
D
D
D
R
UN_ON_CPU1.5VS3
12
R
R
C205
C205
820K_0402_5%
820K_0402_5%
1
Q
Q
C7
C7
D
D
1
1
D
D
Q
Q
C8
C8
V
REF traces should be at least
20 mils wide and 20 mils spacing
to other signals/planes.
+
VREF_DQA
D
RAMRST_CNTRL_PCH < 26,7>
+
VREF_DQB
For Sandy Bridge
+
1.5VS
1
+
1.5V
8
7
6
5
R
R
C204
C204
1 2
220K_0402_5%
220K_0402_5%
6
C5A
C5A
Q
Q
2
S
USP
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
1
B
+
S
USP <43>
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
Title
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
2
Date: Sheet
ompal Electronics, Inc.
I
I
I
vy Bridge_POWER-2
vy Bridge_POWER-2
vy Bridge_POWER-2
V
V
V
FKAA
FKAA
FKAA
1
0
0
0
.2
.2
.2
o
o
o
f
9 56Monday, March 11, 2013
f
9 56Monday, March 11, 2013
f
9 56Monday, March 11, 2013
Page 10
5
CPUI
CPUI
J
CPUH
CPUH
J
J
AT35
V
SS1
AT32
V
SS2
AT29
V
SS3
AT27
V
SS4
AT25
V
SS5
AT22
V
SS6
AT19
V
SS7
AT16
V
SS8
AT13
V
SS9
AT10
V
SS10
AT7
V
SS11
AT4
D D
C C
B B
V
SS12
AT3
V
SS13
AR25
V
SS14
AR22
V
SS15
AR19
V
SS16
AR16
V
SS17
AR13
V
SS18
AR10
V
SS19
AR7
V
SS20
AR4
V
SS21
AR2
V
SS22
AP34
V
SS23
AP31
V
SS24
AP28
V
SS25
AP25
V
SS26
AP22
V
SS27
AP19
V
SS28
AP16
V
SS29
AP13
V
SS30
AP10
V
SS31
AP7
V
SS32
AP4
V
SS33
AP1
V
SS34
AN30
V
SS35
AN27
V
SS36
AN25
V
SS37
AN22
V
SS38
AN19
V
SS39
AN16
V
SS40
AN13
V
SS41
AN10
V
SS42
AN7
V
SS43
AN4
V
SS44
AM29
V
SS45
AM25
V
SS46
AM22
V
SS47
AM19
V
SS48
AM16
V
SS49
AM13
V
SS50
AM10
V
SS51
AM7
V
SS52
AM4
V
SS53
AM3
V
SS54
AM2
V
SS55
AM1
V
SS56
AL34
V
SS57
AL31
V
SS58
AL28
V
SS59
AL25
V
SS60
AL22
V
SS61
AL19
V
SS62
AL16
V
SS63
AL13
V
SS64
AL10
V
SS65
AL7
V
SS66
AL4
V
SS67
AL2
V
SS68
AK33
V
SS69
AK30
V
SS70
AK27
V
SS71
AK25
V
SS72
AK22
V
SS73
AK19
V
SS74
AK16
V
SS75
AK13
V
SS76
AK10
V
SS77
AK7
V
SS78
AK4
V
SS79
AJ25
V
SS80
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
Conn@
Conn@
V
V
SS
SS
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS100
SS101
SS102
SS103
SS104
SS105
SS106
SS107
SS108
SS109
SS110
SS111
SS112
SS113
SS114
SS115
SS116
SS117
SS118
SS119
SS120
SS121
SS122
SS123
SS124
SS125
SS126
SS127
SS128
SS129
SS130
SS131
SS132
SS133
SS134
SS135
SS136
SS137
SS138
SS139
SS140
SS141
SS142
SS143
SS144
SS145
SS146
SS147
SS148
SS149
SS150
SS151
SS152
SS153
SS154
SS155
SS156
SS157
SS158
SS159
SS160
SS81
SS82
SS83
SS84
SS85
SS86
SS87
SS88
SS89
SS90
SS91
SS92
SS93
SS94
SS95
SS96
SS98
SS99
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
J
T35
V
SS161
T34
V
SS162
T33
V
SS163
T32
V
SS164
T31
V
SS165
T30
V
SS166
T29
V
SS167
T28
V
SS168
T27
V
SS169
T26
V
SS170
P9
V
SS171
P8
V
SS172
P6
V
SS173
P5
V
SS174
P3
V
SS175
P2
V
SS176
N35
V
SS177
N34
V
SS178
N33
V
SS179
N32
V
SS180
N31
V
SS181
N30
V
SS182
N29
V
SS183
N28
V
SS184
N27
V
SS185
N26
V
SS186
M34
V
SS187
L33
V
SS188
L30
V
SS189
L27
V
SS190
L9
V
SS191
L8
V
SS192
L6
V
SS193
L5
V
SS194
L4
V
SS195
L3
V
SS196
L2
V
SS197
L1
V
SS198
K35
V
SS199
K32
V
SS200
K29
V
SS201
K26
V
SS202
J34
V
SS203
J31
V
SS204
H33
V
SS205
H30
V
SS206
H27
V
SS207
H24
V
SS208
H21
V
SS209
H18
V
SS210
H15
V
SS211
H13
V
SS212
H10
V
SS213
H9
V
SS214
H8
V
SS215
H7
V
SS216
H6
V
SS217
H5
V
SS218
H4
V
SS219
H3
V
SS220
H2
V
SS221
H1
V
SS222
G35
V
SS223
G32
V
SS224
G29
V
SS225
G26
V
SS226
G23
V
SS227
G20
V
SS228
G17
V
SS229
G11
V
SS230
F34
V
SS231
F31
V
SS232
F29
V
SS233
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
Conn@
Conn@
4
F22
V
SS234
F19
V
SS235
E30
V
SS236
E27
V
SS237
E24
V
SS238
E21
V
SS239
E18
V
SS240
E15
V
SS241
E13
V
SS242
E10
V
SS243
E9
V
SS244
E8
V
SS245
E7
V
SS246
E6
V
SS247
E5
V
SS248
E4
V
SS249
E3
V
SS250
E2
V
SS251
E1
V
SS252
D35
V
SS253
D32
V
SS254
D29
V
SS255
D26
V
SS256
D20
V
SS257
D17
V
SS258
C34
V
SS259
C31
V
SS260
C28
V
SS261
C27
V
SS262
C25
V
SS263
C23
V
SS264
C10
V
SS265
C1
V
SS266
B22
V
SS267
B19
V
SS268
V
V
SS
SS
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS269
SS270
SS271
SS272
SS273
SS274
SS275
SS276
SS277
SS278
SS279
SS280
SS281
SS282
SS283
SS284
SS285
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
T
14 PADT14 PAD
20 PADT20 PAD
T
23 PADT23 PAD
T
T
18 PADT18 PAD
T
22 PADT22 PAD
T
21 PADT21 PAD
24 PADT24 PAD
T
25 PADT25 PAD
T
3
CPUE
CPUE
J
J
V
ESERVED
ESERVED
R
R
CC_DIE_SENSE
V
SS_DIE_SENSE
SVD28
R
R
SVD29
R
SVD30
R
SVD31
R
SVD32
SVD33
R
SVD34
R
SVD35
R
SVD37
R
SVD38
R
SVD39
R
SVD40
R
SVD_NCTF1
R
SVD_NCTF2
R
SVD_NCTF3
R
SVD_NCTF4
R
SVD_NCTF5
R
SVD_NCTF6
R
SVD_NCTF7
R
SVD_NCTF8
R
SVD_NCTF9
R
SVD_NCTF10
R
SVD51
R
SVD52
R
B
CLK_ITP
B
CLK_ITP#
SVD_NCTF11
R
SVD_NCTF12
R
SVD_NCTF13
R
K
EY
AK28
FG[0]
C
AK29
FG[1]
C
C
FG2
C
FG4
C
FG5
C
FG6
C
FG7
C
FG10
C
FG11
C
FG12
C
FG13
C
FG14
C
FG15
C
FG16
C
FG17
AL26
FG[2]
C
AL27
FG[3]
C
AK26
FG[4]
C
AL29
FG[5]
C
AL30
FG[6]
C
AM31
FG[7]
C
AM32
FG[8]
C
AM30
FG[9]
C
AM28
FG[10]
C
AM26
FG[11]
C
AN28
FG[12]
C
AN31
FG[13]
C
AN26
FG[14]
C
AM27
FG[15]
C
AK31
FG[16]
C
AN29
FG[17]
C
AJ31
V
AXG_VAL_SENSE
AH31
SSAXG_VAL_SENSE
V
AJ33
V
CC_VAL_SENSE
AH33
V
SS_VAL_SENSE
AJ26
SVD5
R
F25
SVD8
R
F24
SVD9
R
F23
SVD10
R
D24
SVD11
R
G25
SVD12
R
G24
SVD13
R
E23
SVD14
R
D23
SVD15
R
C30
SVD16
R
A31
SVD17
R
B30
SVD18
R
B29
SVD19
R
D30
SVD20
R
B31
SVD21
R
A30
SVD22
R
C29
SVD23
R
J20
R
SVD24
B18
R
SVD25
J15
SVD27
R
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
Conn@
Conn@
FG
FG
C
C
2
AH27
AH26
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AN35
AM35
AT2
AT1
AR1
B1
T
3PADT3PAD
P
EG Static Lane Reversal - CFG2 is for the 16x
CFG2
E
mbedded Display Port Presence Strap
CFG4
T
64PADT64PAD
P
CIE Port Bifurcation Straps
C
FG[6:5]
1
FG Straps for Processor
C
CFG[17:0] internal pull high 5~15K to VCCIO)
(
C
FG2
1
: Normal Operation; Lane # definition matches
*
socket pin map definition
12
C79
C79
R
R
1K_0402_1%
1K_0402_1%
@
@
0:Lane Reversed
C
FG4
1 : Disabled; No Physical Display Port
*
attached to Embedded Display Port
0
: Enabled; An external Display Port device is
connected to the Embedded Display Port
11: (Default) x16 - Device 1 functions 1 and 2 disabled
*
1
0: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
0
0: x8,x4,x4 - Device 1 functions 1 and 2 enabled
C
FG6
C
FG5
C
FG7
R
R
1K_0402_1%
1K_0402_1%
12
C83
C83
@
@
R
R
C82
C82
1K_0402_1%
1K_0402_1%
IEDP@
IEDP@
12
12
12
C85
C85
R
R
1K_0402_1%
1K_0402_1%
@
@
C84
C84
R
R
1K_0402_1%
1K_0402_1%
@
@
P
EG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB
de assertion
C
FG7
A A
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
0: PEG Wait for BIOS for training
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
T
itle
itle
itle
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
Date: Sheet
ompal Electronics, Inc.
I
I
I
vy Bridge_GND/RSVD/CFG
vy Bridge_GND/RSVD/CFG
vy Bridge_GND/RSVD/CFG
V
V
V
FKAA
FKAA
FKAA
1
10 56Monday, March 11, 2013
0
0
0
.2
.2
.2
o
o
o
f
10 56Monday, March 11, 2013
f
10 56Monday, March 11, 2013
f
Page 11
5
4
3
2
1
+
1.5V
DDR3L
DDR3L
J
J
+
VREF_DQA
D1
D1
C
C
0
0
.1U_0402_10V7K
.1U_0402_10V7K
D D
C
lose to JDDR3L.1
D
DRA_CKE0<7>
C C
B B
A A
+
3VS
D
DR_A_BS2<7>
D
DRA_CLK0<7>
D
DRA_CLK0#<7>
D
DR_A_BS0<7>
D
DR_A_WE#<7>
D
DR_A_CAS#<7>
D
DRA_SCS1#<7>
0.1U_0402_10V7K
0.1U_0402_10V7K
D
DR_A_D0
D
1
2
DR_A_D1
D
DR_A_D2
D
DR_A_D3
D
DR_A_D8
D
DR_A_D9
D
DR_A_DQS#1
D
DR_A_DQS1
D
DR_A_D10
D
DR_A_D11
D
DR_A_D16
D
DR_A_D17
D
DR_A_DQS#2
D
DR_A_DQS2
D
DR_A_D18
D
DR_A_D19
D
DR_A_D24
D
DR_A_D25
D
DR_A_D26
D
DR_A_D27
D
DR_A_MA12
D
DR_A_MA9
D
DR_A_MA8
D
DR_A_MA5
D
DR_A_MA3
D
DR_A_MA1
D
DR_A_MA10
D
DR_A_MA13
D
DR_A_D32
D
DR_A_D33
D
DR_A_DQS#4
D
DR_A_DQS4
D
DR_A_D34
D
DR_A_D35
D
DR_A_D40
D
DR_A_D41
D
DR_A_D42
D
DR_A_D43
D
DR_A_D48
D
DR_A_D49
D
DR_A_DQS#6
D
DR_A_DQS6
D
DR_A_D50
D
DR_A_D51
D
DR_A_D56
D
DR_A_D57
D
DR_A_D58
D
DR_A_D59
1
D26
D26
C
C
2
S
PD setting (SA0 , SA1)
PU/PD by Channe l A/B
->Channel A 00
->Channel B 01
5
+
0.75VS
1
REF_DQ
V
3
SS2
V
5
Q0
D
7
Q1
D
9
SS4
V
11
M0
D
13
SS5
V
15
Q2
D
17
Q3
D
19
SS7
V
21
Q8
D
23
Q9
D
25
SS9
V
27
QS#1
D
29
QS1
D
31
SS11
V
33
Q10
D
35
Q11
D
37
SS13
V
39
Q16
D
41
Q17
D
43
SS15
V
45
QS#2
D
47
QS2
D
49
SS18
V
51
Q18
D
53
Q19
D
55
SS20
V
57
Q24
D
59
Q25
D
61
SS22
V
63
D
M3
65
V
SS23
67
D
Q26
69
D
Q27
71
V
SS25
73
C
KE0
75
V
DD1
77
N
C1
79
B
A2
81
V
DD3
83
A
12/BC#
85
A
9
87
V
DD5
89
A
8
91
A
5
93
V
DD7
95
A
3
97
A
1
99
V
DD9
101
C
K0
103
C
K0#
105
V
DD11
107
A
10/AP
109
B
A0
111
V
DD13
113
W
E#
115
C
AS#
117
V
DD15
119
A
13
121
S
1#
123
V
DD17
125
N
CTEST
127
V
SS27
129
D
Q32
131
D
Q33
133
V
SS29
135
D
QS#4
137
D
QS4
139
V
SS32
141
D
Q34
143
D
Q35
145
V
SS34
147
D
Q40
149
D
Q41
151
V
SS36
153
D
M5
155
V
SS37
157
D
Q42
159
D
Q43
161
V
SS39
163
D
Q48
165
D
Q49
167
V
SS41
169
D
QS#6
171
D
QS6
173
V
SS44
175
D
Q50
177
D
Q51
179
V
SS46
181
D
Q56
183
D
Q57
185
V
SS48
187
D
M7
189
V
SS49
191
D
Q58
193
D
Q59
195
V
SS51
197
S
A0
199
V
DDSPD
201
S
A1
203
V
TT1
205
G
1
LCN_DAN06-K4406-0102
LCN_DAN06-K4406-0102
Conn@
Conn@
R
V
REF_CA
E
D
D
D
D
V
ESET#
V
D
D
V
D
D
V
V
D
D
V
D
D
V
D
D
V
D
D
V
C
V
V
V
V
V
V
R
V
O
V
O
V
V
D
D
V
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
V
D
D
V
D
D
V
D
D
V
D
D
V
VENT#
SS1
V
D
D
SS3
V
QS#0
QS0
SS6
V
D
D
SS8
V
Q12
Q13
SS10
D
SS12
Q14
Q15
SS14
Q20
Q21
SS16
D
SS17
Q22
Q23
SS19
Q28
Q29
SS21
QS#3
QS3
SS24
Q30
Q31
SS26
KE1
DD2
DD4
DD6
DD8
DD10
C
C
DD12
B
AS#
DD14
DT0
DD16
DT1
N
DD18
SS28
Q36
Q37
SS30
D
SS31
Q38
Q39
SS33
Q44
Q45
SS35
QS#5
QS5
SS38
Q46
Q47
SS40
Q52
Q53
SS42
D
SS43
Q54
Q55
SS45
Q60
Q61
SS47
QS#7
QS7
SS50
Q62
Q63
SS52
S
S
V
+
1.5V
2
4
D
Q4
Q5
Q6
Q7
M1
M2
A
15
A
14
A
11
A
7
A
6
A
4
A
2
A
0
K1
K1#
A1
S
0#
C2
M4
M6
DA
CL
TT2
G
2
DR_A_D4
6
D
DR_A_D5
8
10
D
DR_A_DQS#0
12
D
DR_A_DQS0
14
16
D
DR_A_D6
18
D
DR_A_D7
20
22
D
DR_A_D12
24
D
DR_A_D13
26
28
30
32
34
D
DR_A_D14
36
D
DR_A_D15
38
40
D
DR_A_D20
42
D
DR_A_D21
44
46
48
50
D
DR_A_D22
52
D
DR_A_D23
54
56
D
DR_A_D28
58
D
DR_A_D29
60
62
D
DR_A_DQS#3
64
D
DR_A_DQS3
66
68
D
DR_A_D30
70
D
DR_A_D31
72
74
76
78
D
DR_A_MA15
80
D
DR_A_MA14
82
84
D
DR_A_MA11
86
D
DR_A_MA7
88
90
D
DR_A_MA6
92
D
DR_A_MA4
94
96
D
DR_A_MA2
98
D
DR_A_MA0
100
102
104
106
108
110
112
114
116
118
120
122
124
126
+
VREF_CAA
128
130
D
DR_A_D36
132
D
DR_A_D37
134
136
138
140
D
DR_A_D38
142
D
DR_A_D39
144
146
D
DR_A_D44
148
D
DR_A_D45
150
152
D
DR_A_DQS#5
154
D
DR_A_DQS5
156
158
D
DR_A_D46
160
D
DR_A_D47
162
164
D
DR_A_D52
166
D
DR_A_D53
168
170
172
174
D
DR_A_D54
176
D
DR_A_D55
178
180
D
DR_A_D60
182
D
DR_A_D61
184
186
D
DR_A_DQS#7
188
D
DR_A_DQS7
190
192
D
DR_A_D62
194
D
DR_A_D63
196
198
200
202
204
+
0.75VS
206
4
DDR3 SO-DIMM A
tandard Type
S
S
M_DRAMRST# <12,7>
D
DRA_CKE1 <7>
D
DRA_CLK1 <7>
D
DRA_CLK1# <7>
D
DR_A_BS1 <7>
D
DR_A_RAS# <7>
D
DRA_SCS0# <7>
D
DRA_ODT0 <7>
D
DRA_ODT1 <7>
1
D16
D16
C
C
0
0
.1U_0402_10V7K
.1U_0402_10V7K
2
close to JDDR3L.126
P
M_SMBDATA <12,26,35,42>
P
M_SMBCLK <12,26,35,42>
D
DR_A_DQS[0..7] <7>
D
DR_A_DQS#[0..7] <7>
D
DR_A_D[0..63] <7>
D
DR_A_MA[0..15] <7>
1.5V
+
1
D1
D1
R
R
1K_0402_1%
1K_0402_1%
eciphered Date
eciphered Date
eciphered Date
D
D
D
2
12
D2
D2
R
R
1K_0402_1%
1K_0402_1%
Layout Note: Place these 4 Caps near
Command and Control signals of DIMMA
+
1.5V
1 2
D20 0.1U_0402_10V7K
D20 0.1U_0402_10V7K
C
C
2
1
D17 0.1U_0402_10V7K
D17 0.1U_0402_10V7K
C
C
1 2
D18 0.1U_0402_10V7K
D18 0.1U_0402_10V7K
C
C
1 2
D19 0.1U_0402_10V7K
D19 0.1U_0402_10V7K
C
C
2
VREF_DQA
+
+
1.5V
12
D6
D6
R
R
1K_0402_1%
1K_0402_1%
12
D7
D7
R
R
1K_0402_1%
1K_0402_1%
L
ayout Note:
Place near JDDRL
+
1.5V
1 2
D8 10U_0603_6.3V6M
D8 10U_0603_6.3V6M
C
C
2
1
D9 10U_0603_6.3V6M
D9 10U_0603_6.3V6M
C
C
1 2
D10 10U_0603_6.3V6M
C
C
D10 10U_0603_6.3V6M
1 2
D11 10U_0603_6.3V6M
D11 10U_0603_6.3V6M
C
C
1 2
D12 10U_0603_6.3V6M
D12 10U_0603_6.3V6M
C
C
1 2
D13 10U_0603_6.3V6M
D13 10U_0603_6.3V6M
C
C
ecurity Classification
ecurity Classification
ecurity Classification
S
S
S
ssued Date
ssued Date
ssued Date
I
I
I
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
T
T
T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
2
2
2
ompal Secret Data
ompal Secret Data
ompal Secret Data
C
C
C
Layout Note:
Place near JDDRL1.203 a nd 204
+
0.75VS
2
1
D24 1U_0402_6.3V6K
D24 1U_0402_6.3V6K
C
C
12
C
C
D21 1U_0402_6.3V6K
D21 1U_0402_6.3V6K
ompal Electronics, Inc.
ompal Electronics, Inc.
ompal Electronics, Inc.
C
C
Title
itle
itle
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
ustom
ustom
ustom
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
C
DRIII-SODIMM0
DRIII-SODIMM0
DRIII-SODIMM0
D
D
D
FKAA
FKAA
FKAA
V
V
V
f
11 56Monday, March 11, 2013
f
11 56Monday, March 11, 2013
f
11 56Monday, March 11, 2013
o
o
1
o
.2
.2
.2
0
0
0
Page 12
A
B
C
D
E
D
D
QS3
DD2
DD4
DD6
DD8
N
D
QS5
D
QS7
S
SS1
D
D
SS3
QS0
SS6
D
D
SS8
Q12
Q13
Q14
Q15
Q20
Q21
Q22
Q23
Q28
Q29
Q30
Q31
KE1
A
A
A
C
K1#
B
AS#
S
DT0
DT1
Q36
Q37
Q38
Q39
Q44
Q45
Q46
Q47
Q52
Q53
Q54
Q55
Q60
Q61
Q62
Q63
S
TT2
+
1.5V
2
4
D
Q4
Q5
Q6
Q7
M1
M2
15
14
11
A
7
A
6
A
4
A
2
A
0
K1
A1
0#
C2
M4
M6
DA
CL
G
2
DR_B_D4
6
D
DR_B_D5
8
10
D
DR_B_DQS#0
12
D
DR_B_DQS0
14
16
D
DR_B_D6
18
D
DR_B_D7
20
22
D
DR_B_D12
24
D
DR_B_D13
26
28
30
32
34
D
DR_B_D14
36
D
DR_B_D15
38
40
D
DR_B_D20
42
D
DR_B_D21
44
46
48
50
D
DR_B_D22
52
D
DR_B_D23
54
56
D
DR_B_D28
58
D
DR_B_D29
60
62
D
DR_B_DQS#3
64
D
DR_B_DQS3
66
68
D
DR_B_D30
70
D
DR_B_D31
72
74
76
78
D
DR_B_MA15
80
D
DR_B_MA14
82
84
D
DR_B_MA11
86
D
DR_B_MA7
88
90
D
DR_B_MA6
92
D
DR_B_MA4
94
96
D
DR_B_MA2
98
D
DR_B_MA0
100
102
104
106
108
110
112
114
116
118
120
122
124
126
+
VREF_CAB
128
130
D
DR_B_D36
132
D
DR_B_D37
134
136
138
140
D
DR_B_D38
142
D
DR_B_D39
144
146
D
DR_B_D44
148
D
DR_B_D45
150
152
D
DR_B_DQS#5
154
D
DR_B_DQS5
156
158
D
DR_B_D46
160
D
DR_B_D47
162
164
D
DR_B_D52
166
D
DR_B_D53
168
170
172
174
D
DR_B_D54
176
D
DR_B_D55
178
180
D
DR_B_D60
182
D
DR_B_D61
184
186
D
DR_B_DQS#7
188
D
DR_B_DQS7
190
192
D
DR_B_D62
194
D
DR_B_D63
196
198
200
202
204
+
206
0.75VS
B
D
DRB_CKE1 <7>
D
DRB_CLK1 <7>
D
DRB_CLK1# <7>
D
DR_B_BS1 <7>
D
DR_B_RAS# <7>
D
DRB_SCS0# <7>
D
DRB_ODT0 <7>
D
DRB_ODT1 <7>
C
C
Close to JDDR3H.126
P
M_SMBDATA <11,26,35,42>
P
M_SMBCLK <11,26,35,42>
DDR3 SO-DIMM B
S
tandard Type
S
M_DRAMRST# <11,7>
D47
D47
1
0
0
.1U_0402_10V7K
.1U_0402_10V7K
2
D
DR_B_DQS#[0..7] <7>
D
DR_B_DQS[0..7] <7>
D
DR_B_D[0..63] <7>
D
DR_B_MA[0..15] <7>
1.5V
+
12
D10
D10
R
R
1K_0402_1%
1K_0402_1%
VREF_DQB
+
+
1.5V
1
D12
D12
R
R
1K_0402_1%
1K_0402_1%
2
12
D13
D13
R
R
1K_0402_1%
1K_0402_1%
L
ayout Note:
Place near JDDRH
+
1.5V
ecurity Classification
ecurity Classification
ecurity Classification
S
S
S
ssued Date
ssued Date
ssued Date
I
I
I
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
T
T
T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
2
2
2
2
1
D31 47U_0805_6.3V6M
D31 47U_0805_6.3V6M
C
C
1 2
D41 10U_0603_6.3V6M
D41 10U_0603_6.3V6M
C
C
1 2
D36 10U_0603_6.3V6M
D36 10U_0603_6.3V6M
C
C
1 2
D37 10U_0603_6.3V6M
D37 10U_0603_6.3V6M
C
C
1 2
C
C
D38 10U_0603_6.3V6M
D38 10U_0603_6.3V6M
1 2
D39 10U_0603_6.3V6M
D39 10U_0603_6.3V6M
C
C
1 2
D40 10U_0603_6.3V6M
D40 10U_0603_6.3V6M
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
C
C
C
eciphered Date
eciphered Date
eciphered Date
D
D
D
1
D11
D11
R
R
1K_0402_1%
1K_0402_1%
2
Layout Note: Place these 4 Caps near
Command and Control signals of DIMMB
+
1.5V
1 2
D33 0.1U_0402_10V7K
D33 0.1U_0402_10V7K
C
C
1 2
D29 0.1U_0402_10V7K
D29 0.1U_0402_10V7K
C
C
2
1
D30 0.1U_0402_10V7K
D30 0.1U_0402_10V7K
C
C
1 2
D32 0.1U_0402_10V7K
D32 0.1U_0402_10V7K
C
C
D
Layout Note:
Place near JDDRH.203 and 2 04
+
0.75VS
12
D45 1U_0402_6.3V6K
D45 1U_0402_6.3V6K
C
C
2
1
D42 1U_0402_6.3V6K
D42 1U_0402_6.3V6K
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
ompal Electronics, Inc.
C
C
itle
itle
itle
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
ustom
ustom
ustom
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
C
DRIII-SODIMM1
DRIII-SODIMM1
DRIII-SODIMM1
D
D
D
FKAA
FKAA
FKAA
V
V
V
f
12 56Monday, March 11, 2013
f
12 56Monday, March 11, 2013
f
12 56Monday, March 11, 2013
o
o
E
o
.2
.2
.2
0
0
0
+
1.5V
DDR3H
DDR3H
J
J
+
VREF_DQB
D27
D27
C
C
0
0
.1U_0402_10V7K
1 1
2 2
3 3
+
3VS
4 4
.1U_0402_10V7K
C
lose to JDDR3H.1
D
DRB_CKE0<7>
D
DR_B_BS2<7>
D
DRB_CLK0<7>
D
DRB_CLK0#<7>
D
DR_B_BS0<7>
D
DR_B_WE#<7>
D
DR_B_CAS#<7>
D
DRB_SCS1#<7>
1
D49
D49
C
C
2
0.1U_0402_10V7K
0.1U_0402_10V7K
D
DR_B_D0
D
DR_B_D1
1
D
DR_B_D2
2
D
DR_B_D3
D
DR_B_D8
D
DR_B_D9
D
DR_B_DQS#1
D
DR_B_DQS1
D
DR_B_D10
D
DR_B_D11
D
DR_B_D16
D
DR_B_D17
D
DR_B_DQS#2
D
DR_B_DQS2
D
DR_B_D18
D
DR_B_D19
D
DR_B_D24
D
DR_B_D25
D
DR_B_D26
D
DR_B_D27
D
DR_B_MA12
D
DR_B_MA9
D
DR_B_MA8
D
DR_B_MA5
D
DR_B_MA3
D
DR_B_MA1
D
DR_B_MA10
D
DR_B_MA13
D
DR_B_D32
D
DR_B_D33
D
DR_B_DQS#4
D
DR_B_DQS4
D
DR_B_D34
D
DR_B_D35
D
DR_B_D40
D
DR_B_D41
D
DR_B_D42
D
DR_B_D43
D
DR_B_D48
D
DR_B_D49
D
DR_B_DQS#6
D
DR_B_DQS6
D
DR_B_D50
D
DR_B_D51
D
DR_B_D56
D
DR_B_D57
D
DR_B_D58
D
DR_B_D59
2
1
D15 10K_0402_5%
D15 10K_0402_5%
R
R
S
PD setting (SA0 , SA1)
PU/PD by Channe l A/B
->Channel A 00
->Channel B 01
A
+
0.75VS
1
REF_DQ
V
3
SS2
V
5
Q0
D
7
Q1
D
9
SS4
V
11
M0
D
13
SS5
V
15
Q2
D
17
Q3
D
19
SS7
V
21
Q8
D
23
Q9
D
25
SS9
V
27
QS#1
D
29
QS1
D
31
SS11
V
33
Q10
D
35
Q11
D
37
SS13
V
39
Q16
D
41
Q17
D
43
SS15
V
45
QS#2
D
47
QS2
D
49
SS18
V
51
Q18
D
53
Q19
D
55
SS20
V
57
Q24
D
59
Q25
D
61
V
SS22
63
D
M3
65
V
SS23
67
D
Q26
69
D
Q27
71
V
SS25
73
C
KE0
75
V
DD1
77
N
C1
79
B
A2
81
V
DD3
83
A
12/BC#
85
A
9
87
V
DD5
89
A
8
91
A
5
93
V
DD7
95
A
3
97
A
1
99
V
DD9
101
C
K0
103
C
K0#
105
V
DD11
107
A
10/AP
109
B
A0
111
V
DD13
113
W
E#
115
C
AS#
117
V
DD15
119
A
13
121
S
1#
123
V
DD17
125
N
CTEST
127
V
SS27
129
D
Q32
131
D
Q33
133
V
SS29
135
D
QS#4
137
D
QS4
139
V
SS32
141
D
Q34
143
D
Q35
145
V
SS34
147
D
Q40
149
D
Q41
151
V
SS36
153
D
M5
155
V
SS37
157
D
Q42
159
D
Q43
161
V
SS39
163
D
Q48
165
D
Q49
167
V
SS41
169
D
QS#6
171
D
QS6
173
V
SS44
175
D
Q50
177
D
Q51
179
V
SS46
181
D
Q56
183
D
Q57
185
V
SS48
187
D
M7
189
V
SS49
191
D
Q58
193
D
Q59
195
V
SS51
197
S
A0
199
V
DDSPD
201
S
A1
203
V
TT1
205
G
1
LCN_DAN06-K4806-0102
LCN_DAN06-K4806-0102
Conn@
Conn@
R
V
REF_CA
E
V
V
QS#0
D
D
V
V
D
D
SS10
V
ESET#
SS12
V
D
D
SS14
V
D
D
SS16
V
SS17
V
D
D
SS19
V
D
D
SS21
V
D
QS#3
D
V
SS24
D
D
V
SS26
C
V
V
V
V
V
DD10
C
V
DD12
R
V
DD14
O
V
DD16
O
V
DD18
V
SS28
D
D
V
SS30
V
SS31
D
D
V
SS33
D
D
V
SS35
D
QS#5
D
V
SS38
D
D
V
SS40
D
D
V
SS42
V
SS43
D
D
V
SS45
D
D
V
SS47
D
QS#7
D
V
SS50
D
D
V
SS52
VENT#
V
Page 13
A
P
P
CIE_GTX_C_CRX_P[0..3]<6>
P
CIE_GTX_C_CRX_N[0..3]<6>
P
CIE_CTX_C_GRX_P[0..3]<6>
P
CIE_CTX_C_GRX_N[0..3]<6>
1 1
P
CIE_GTX_C_CRX_P0
P
CIE_GTX_C_CRX_N0
P
CIE_GTX_C_CRX_P1
P
CIE_GTX_C_CRX_N1
P
CIE_GTX_C_CRX_P2
P
CIE_GTX_C_CRX_N2
P
CIE_GTX_C_CRX_P3
P
CIE_GTX_C_CRX_N3
2 2
3 3
C
LK_REQ_VGA#<26>
4 4
CIE_GTX_C_CRX_P[0..3]
P
CIE_GTX_C_CRX_N[0..3]
P
CIE_CTX_C_GRX_P[0..3]
P
CIE_CTX_C_GRX_N[0..3]
1 2
C
C
V1 0.22U_0402_16V7KOPT@
V1 0.22U_0402_16V7KOPT@
2
1
V2 0.22U_0402_16V7KOPT@
V2 0.22U_0402_16V7KOPT@
C
C
1 2
V3 0.22U_0402_16V7KOPT@
V3 0.22U_0402_16V7KOPT@
C
C
2
1
C
C
V4 0.22U_0402_16V7KOPT@
V4 0.22U_0402_16V7KOPT@
2
1
C
C
V5 0.22U_0402_16V7KOPT@
V5 0.22U_0402_16V7KOPT@
2
1
C
C
V6 0.22U_0402_16V7KOPT@
V6 0.22U_0402_16V7KOPT@
1 2
C
C
V7 0.22U_0402_16V7KOPT@
V7 0.22U_0402_16V7KOPT@
1 2
C
C
V8 0.22U_0402_16V7KOPT@
V8 0.22U_0402_16V7KOPT@
C
LK_PCIE_VGA<26>
C
LK_PCIE_VGA#<26>
P
LTRST_VGA#<29>
61
Q
Q
V2A
V2A
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
OPT@
OPT@
2
1 2
@
@
R
R
V4 200_0402_1%
V4 200_0402_1%
+
3VS_DGPU
PCIE_CTX_C_GRX_P0
P
CIE_CTX_C_GRX_N0
P
CIE_CTX_C_GRX_P1
P
CIE_CTX_C_GRX_N1
P
CIE_CTX_C_GRX_P2
P
CIE_CTX_C_GRX_N2
P
CIE_CTX_C_GRX_P3
P
CIE_CTX_C_GRX_N3
P
CIE_GTX_CRX_P0
P
CIE_GTX_CRX_N0
P
CIE_GTX_CRX_P1
P
CIE_GTX_CRX_N1
P
CIE_GTX_CRX_P2
P
CIE_GTX_CRX_N2
P
CIE_GTX_CRX_P3
P
CIE_GTX_CRX_N3
C
LK_PCIE_VGA
C
LK_PCIE_VGA#
C
LK_REQ_GPU#
P
EX_TSTCLK_OUT
P
EX_TSTCLK_OUT#
R
R
V5
V5
2.49K_0402_1%
2.49K_0402_1%
OPT@
OPT@
1 2
B
V1A
V1A
U
U
AG6
EX_RX0
P
AG7
EX_RX0_N
P
AF7
P
EX_RX1
AE7
EX_RX1_N
P
AE9
P
EX_RX2
AF9
EX_RX2_N
P
AG9
EX_RX3
P
AG10
P
EX_RX3_N
AF10
P
EX_RX4
AE10
EX_RX4_N
P
AE12
EX_RX5
P
AF12
EX_RX5_N
P
AG12
P
EX_RX6
AG13
EX_RX6_N
P
AF13
EX_RX7
P
AE13
P
EX_RX7_N
AE15
C
N
AF15
C
N
AG15
N
C
AG16
C
N
AF16
C
N
AE16
N
C
AE18
N
C
AF18
N
C
AG18
N
C
AG19
C
N
AF19
N
C
AE19
C
N
AE21
C
N
AF21
N
C
AG21
C
N
AG22
C
N
AC9
EX_TX0
P
AB9
P
EX_TX0_N
AB10
EX_TX1
P
AC10
EX_TX1_N
P
AD11
P
EX_TX2
AC11
EX_TX2_N
P
AC12
P
EX_TX3
AB12
P
EX_TX3_N
AB13
EX_TX4
P
AC13
P
EX_TX4_N
AD14
EX_TX5
P
AC14
P
EX_TX5_N
AC15
EX_TX6
P
AB15
EX_TX6_N
P
AB16
EX_TX7
P
AC16
EX_TX7_N
P
AD17
C
N
AC17
N
C
AC18
N
C
AB18
N
C
AB19
N
C
AC19
C
N
AD20
N
C
AC20
C
N
AC21
N
C
AB21
C
N
AD23
C
N
AE23
N
C
AF24
N
C
AE24
N
C
AG24
C
N
AG25
C
N
AE8
EX_REFCLK
P
AD8
EX_REFCLK_N
P
AC6
EX_CLKREQ_N
P
AF22
EX_TSTCLK_OUT
P
AE22
EX_TSTCLK_OUT_N
P
AC7
P
EX_RST_N
AF25
P
EX_TERMP
N14P-GV2-S-A2_FCBGA595
N14P-GV2-S-A2_FCBGA595
N14PGV2R3@
N14PGV2R3@
1
C
C
18P_0402_50V8J
18P_0402_50V8J
NOGCLK@
NOGCLK@
2
X
V17
V17
TALIN
art 1 of 6
art 1 of 6
P
P
1
CI EXPRESS
CI EXPRESS
P
P
Y
Y
V1
V1
1
ACs
ACs
D
D
120mA
2C GPIO
2C GPIO
I
I
52mA
71mA
41mA
CLK
CLK
NOGCLK@
NOGCLK@
27MHZ_16PF
27MHZ_16PF
G
ND
2
G
G
G
G
G
G
G
G
G
G
G
G
D
ACA_RED
ACA_GREEN
D
ACA_BLUE
D
ACA_HSYNC
D
D
ACA_VSYNC
ACA_VDD
D
ACA_VREF
D
ACA_RSET
D
2CA_SCL
I
I
2CA_SDA
2CB_SCL
I
I
2CB_SDA
I
2CC_SCL
2CC_SDA
I
2CS_SCL
I
2CS_SDA
I
C
ORE_PLLVDD
P_PLLVDD
S
ID_PLLVDD
V
X
TAL_IN
TAL_OUT
X
X
TAL_SSIN
TAL_OUTBUFF
X
3
G
ND
4
18P_0402_50V8J
18P_0402_50V8J
G
G
G
G
G
G
G
G
G
G
PIO10
PIO11
PIO12
PIO13
PIO14
PIO15
PIO16
PIO17
PIO18
PIO19
PIO20
PIO21
PIO0
PIO1
PIO2
PIO3
PIO4
PIO5
PIO6
PIO7
PIO8
PIO9
N
3
C6
B2
D6
C7
F9
A3
A4
B6
A6
F8
C5
E7
D7
B4
B3
C3
D5
D4
C2
F7
E6
C4
AB6
C
AG3
AF4
AF3
AE3
AE4
W5
AE2
AF2
B7
A7
C9
C8
A9
B9
D9
D8
L6
M6
N6
C11
B10
A10
C10
X
TAL_OUT
C
C
NOGCLK@
NOGCLK@
V18
V18
F
B_CLAMP_MON
F
B_CLAMP_REQ#
O
VERT#_VGA
G
PU_EVENT
D
GPU_VID
G
PS_DOWN#
P
SI
V
GA_CRT_CLK
V
GA_CRT_DATA
H
DCP_SCL
H
DCP_SDA
V
GA_EDID_CLK
V
GA_EDID_DATA
S
MB_CLK_GPU
S
MB_DATA_GPU
+
PLLVDD
+
GPU_PLLVDD
X
TALIN
X
TAL_OUT
X
TAL_SSIN
X
TAL_OUTBUFF
1
2
C
+
3VS_DGPU
G
G
2
V8
V8
Q
Q
N14PGV2@
N14PGV2@
13
D
D
S
S
2N7002KW_SOT323-3
2N7002KW_SOT323-3
D
GPU_VID <54>
G
PS_DOWN# <41>
P
SI <54>
1
V9
V9
1
V10
V10
C
C
C
O
O
PT@
PT@
2
CV42, CV43 under GPU
close to ball : AE8,AD7
V
GA_X1<35>
10_0402_5%
10_0402_5%
10P_0402_50V8J
10P_0402_50V8J
f
or EMI
C
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
O
O
PT@
PT@
12
V7
@EMI@
V7
@EMI@
R
R
1
V113
@EMI@
V113
@EMI@
C
C
2
D
D
V1
V1
12
RB751V40_SC76-2
RB751V40_SC76-2
OPT@
OPT@
C
LK_REQ_GC6# <41>
BLM18PG181SN1D_2P
BLM18PG181SN1D_2P
1
V11
V11
C
C
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
O
O
PT@
PT@
1 2
R
R
V8 0_0402_5%
V8 0_0402_5%
1 2
1
V12
V12
C
C
2
O
O
PT@
PT@
GCLK@
GCLK@
F
B_CLAMP <14,17,41>
L
L
V1
V1
OPT@
OPT@
22U_0805_6.3V6M
22U_0805_6.3V6M
X
TALIN
+
1.05VS_DGPU
1
PT@
PT@
O
O
2
D
F
or GC6
V13
V13
C
C
10U_0603_6.3V6M
10U_0603_6.3V6M
J
TAG_TRST<15>
T
ESTMODE<15>
I
nternal Thermal Sensor
S
MB_CLK_GPU
S
MB_DATA_GPU
under GPU
close to AD8
OPT@
OPT@
Q
Q
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
+
PLLVDD
+
4
2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
V1A
V1A
1
V14
V14
C
C
2
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
G
PS_DOWN#
G
PU_EVENT
X
TAL_OUTBUFF
X
TAL_SSIN
V
GA_EDID_CLK
V
GA_EDID_DATA
S
MB_CLK_GPU
S
MB_DATA_GPU
V
GA_CRT_CLK
V
GA_CRT_DATA
H
DCP_SDA
H
DCP_SCL
F
B_CLAMP
F
B_CLAMP_REQ#
F
B_CLAMP_MON
O
VERT#_VGA
C
LK_REQ_GC6#
C
LK_REQ_GPU#
3VS_DGPU
5
OPT@
OPT@
V1B
V1B
Q
Q
3
61
FBMA-L11-160808300LMA25T_2P
FBMA-L11-160808300LMA25T_2P
1
V15
V15
C
C
2
OPT@
OPT@
22U_0805_6.3V6M
22U_0805_6.3V6M
E
R
R
PV1
PV1
1
2 7
3 6
4 5
10K_8P4R_5%
10K_8P4R_5%
OPT@
OPT@
R
R
PV2
PV2
1 8
2
3 6
4 5
2.2K_8P4R_5%
2.2K_8P4R_5%
OPT@
OPT@
PV3
PV3
R
R
1 8
2
3 6
4 5
2.2K_8P4R_5%
2.2K_8P4R_5%
OPT@
OPT@
R
R
PV12
PV12
1
2 7
3 6
4
10K_8P4R_5%
10K_8P4R_5%
OPT@
OPT@
PV13
PV13
R
R
1 8
2 7
3 6
4
10K_8P4R_5%
10K_8P4R_5%
OPT@
OPT@
L
L
V2
OPT@
V2
OPT@
1 2
+
3VS_DGPU
8
7
7
8
5
5
E
C_SMB_CK2 <26,34,41>
E
C_SMB_DA2 <26,34,41>
+
1.05VS_DGPU
1
V16
V16
C
C
2
OPT@
OPT@
+
3VS
10U_0603_6.3V6M
10U_0603_6.3V6M
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
Title
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
D
Date: Sheet
ompal Electronics, Inc.
V
V
V
GA_N14x PEG & DAC
GA_N14x PEG & DAC
GA_N14x PEG & DAC
E
0
0
0
.2
.2
o
o
o
13 56Monday, March 11, 2013
13 56Monday, March 11, 2013
13 56Monday, March 11, 2013
.2
f
f
f
Page 14
A
P
V
RAM Interface
M
+
FB_PLLAVDD
C
C
22U_0805_6.3V6M
22U_0805_6.3V6M
V20
V20
1
OPT@
OPT@
2
DA[15..0]
M
DA[31..16]
DA[47..32]
M
DA[63..48]
M
Close to H22
0.1U_0402_10V7K
0.1U_0402_10V7K
C
C
V21
V21
2
OPT@
OPT@
1
C
C
V22
V22
1
OPT@
OPT@
2
Close to P22
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
V114
V114
OPT@
OPT@
U
U
V1B
V1B
art 2 of 6
art 2 of 6
P
BA_D00
F
BA_D01
F
BA_D02
F
BA_D03
F
BA_D04
F
BA_D05
F
BA_D06
F
BA_D07
F
BA_D08
F
BA_D09
F
BA_D10
F
BA_D11
F
BA_D12
F
BA_D13
F
BA_D14
F
BA_D15
F
BA_D16
F
BA_D17
F
F
BA_D18
BA_D19
F
F
BA_D20
F
BA_D21
F
BA_D22
F
BA_D23
F
BA_D24
F
BA_D25
F
BA_D26
F
BA_D27
F
BA_D28
F
BA_D29
F
BA_D30
F
BA_D31
F
BA_D32
F
BA_D33
F
BA_D34
F
BA_D35
F
BA_D36
F
BA_D37
F
BA_D38
F
BA_D39
F
BA_D40
F
BA_D41
F
BA_D42
F
BA_D43
F
BA_D44
F
BA_D45
F
BA_D46
F
BA_D47
F
BA_D48
F
BA_D49
F
BA_D50
F
BA_D51
F
BA_D52
F
BA_D53
F
BA_D54
F
BA_D55
F
BA_D56
F
BA_D57
F
BA_D58
F
BA_D59
F
BA_D60
F
BA_D61
F
BA_D62
F
BA_D63
F
B_PLLAVDD_1
F
B_PLLAVDD_2
F
B_VREF_PROBE
F
B_DLLAVDD
F
B_CLAMP
F
BA_DEBUG0
F
BA_DEBUG1
P
62mA
62mA
35mA
EMORY
EMORY
M
M
F
BA_DQS_RN0
F
BA_DQS_RN1
INTERFACE A
INTERFACE A
F
BA_DQS_RN2
F
BA_DQS_RN3
F
BA_DQS_RN4
F
BA_DQS_RN5
F
BA_DQS_RN6
F
BA_DQS_RN7
F
BA_DQS_WP0
F
BA_DQS_WP1
F
BA_DQS_WP2
F
BA_DQS_WP3
F
BA_DQS_WP4
F
BA_DQS_WP5
F
BA_DQS_WP6
F
BA_DQS_WP7
F
BA_WCK01_N
F
BA_WCK23_N
F
BA_WCK45_N
F
BA_WCK67_N
F
BA_CMD0
F
BA_CMD1
F
BA_CMD2
F
BA_CMD3
F
BA_CMD4
F
BA_CMD5
F
BA_CMD6
F
BA_CMD7
F
BA_CMD8
F
BA_CMD9
F
BA_CMD10
F
BA_CMD11
F
BA_CMD12
F
BA_CMD13
F
BA_CMD14
F
BA_CMD15
F
BA_CMD16
F
BA_CMD17
F
BA_CMD18
F
BA_CMD19
F
BA_CMD20
F
BA_CMD21
F
BA_CMD22
F
BA_CMD23
F
BA_CMD24
F
BA_CMD25
F
BA_CMD26
F
BA_CMD27
F
BA_CMD28
F
BA_CMD29
F
BA_CMD30
F
BA_CMD31
F
BA_DQM0
F
BA_DQM1
F
BA_DQM2
F
BA_DQM3
F
BA_DQM4
F
BA_DQM5
F
BA_DQM6
F
BA_DQM7
F
BA_CLK0
F
BA_CLK0_N
F
BA_CLK1
F
BA_CLK1_N
F
BA_WCK01
F
BA_WCK23
F
BA_WCK45
F
BA_WCK67
C27
C26
E24
F24
D27
D26
F25
F26
F23
G22
G23
G24
F27
G25
G27
G26
M24
M23
K24
K23
M27
M26
M25
K26
K22
J23
J25
J24
K27
K25
J27
J26
D19
D14
C17
C22
P24
W24
AA25
U25
F19
C14
A16
A22
P25
W22
AB27
T27
E19
C15
B16
B22
R25
W23
AB26
T26
D24
D25
N22
M22
D18
C18
D17
D16
T24
U24
V24
V25
C
MDA0
C
MDA1
C
MDA2
C
MDA3
C
MDA4
C
MDA5
C
MDA6
C
MDA7
CMDA8
C
MDA9
C
MDA10
C
MDA11
C
MDA12
C
MDA13
C
MDA14
C
MDA15
C
MDA16
C
MDA17
C
MDA18
C
MDA19
C
MDA20
CMDA21
C
MDA22
C
MDA23
C
MDA24
C
MDA25
C
MDA26
CMDA27
C
MDA28
C
MDA29
C
MDA30
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
M
DA0
M
DA1
M
DA2
M
DA3
M
DA4
M
DA5
M
DA6
M
DA7
M
DA8
M
DA9
M
DA10
M
DA11
M
DA12
M
DA13
M
DA14
M
DA15
M
DA16
M
DA17
M
DA18
M
DA19
M
DA20
M
DA21
M
DA22
M
DA23
M
DA24
M
DA25
M
DA26
M
DA27
M
DA28
M
DA29
M
DA30
M
DA31
M
DA32
M
DA33
M
DA34
M
DA35
M
DA36
M
DA37
M
DA38
M
DA39
M
DA40
M
DA41
M
DA42
M
DA43
M
DA44
M
DA45
M
DA46
M
DA47
M
DA48
M
DA49
M
DA50
M
DA51
M
DA52
M
DA53
M
DA54
M
DA55
MDA56
M
DA57
M
DA58
M
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
B_CLAMP<13,17,41>
F
DA59
M
DA60
M
DA61
MDA62
M
DA63
+
FB_PLLAVDD
V1 PADTV1 PAD
T
V2 PADTV2 PAD
T
E18
F18
E16
F17
D20
D21
F20
E21
E15
D15
F15
F13
C13
B13
E13
D13
B15
C16
A13
A15
B18
A18
A19
C19
B24
C23
A25
A24
A21
B21
C20
C21
R22
R24
T22
R23
N25
N26
N23
N24
V23
V22
T23
U22
Y24
AA24
Y22
AA23
AD27
AB25
AD26
AC25
AA27
AA26
W26
Y25
R26
T25
N27
R27
V26
V27
W27
W25
F16
P22
D23
H22
F3
F22
J22
N14P-GV2-S-A2_FCBGA595
N14P-GV2-S-A2_FCBGA595
N14PGV2R3@
N14PGV2R3@
D
QMA0
D
QMA1
D
QMA2
D
QMA3
D
QMA4
D
QMA5
D
QMA6
D
QMA7
QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
MDA[30..0] <18,19,20,21>
C
LKA0 <18,20>
C
LKA0# <18,20>
C
LKA1 <19,21>
C
LKA1# <19,21>
C
QMA[3..0] <18,20>
D
QMA[7..4] <19,21>
D
QSA#[3..0] < 18,20>
D
QSA#[7..4] < 19,21>
D
QSA[3..0] < 18,20>
D
QSA[7..4] < 19,21>
D
DA[15..0]<18,20>
M
DA[31..16]<18,20>
M
DA[47..32]<19,21>
M
DA[63..48]<19,21>
M
1 1
30ohms (ESR=0.01)
1.05VS_DGPU
+
V3
OPT@
V3
OPT@
L
L
1 2
FBMA-L11-160808300LMA25T_2P
FBMA-L11-160808300LMA25T_2P
Place close to BGA
Near GPU Close to F16
lace close to t he first T poin t
VRAM_1.5VS
+
7
6
109
8
R
R
PV4
PV4
100_1206_10P8R_5%
100_1206_10P8R_5%
OPT@
OPT@
5
234
1
VRAM_1.5VS
+
0
6
987
1
PV6
PV6
R
R
100_1206_10P8R_5%
100_1206_10P8R_5%
OPT@
OPT@
345
1
2
VRAM_1.5VS
+
PV8
PV8
R
R
18
7
2
36
45
100_0804_8P4R_5%
100_0804_8P4R_5%
OPT@
OPT@
12
V10 100_0402_5%
V10 100_0402_5%
R
R
OPT@
OPT@
12
V12 100_0402_5%
V12 100_0402_5%
R
R
OPT@
OPT@
Command Bit Default Pull-down
ODTx
CKEx
DDR3
RST
CS* No Termination
C
C
C
C
C
MDA16
MDA19
MDA3
MDA0
MDA20
1 2
V36 10K_0402_5%OPT@
V36 10K_0402_5%OPT@
R
R
1 2
R
R
V37 10K_0402_5%OPT@
V37 10K_0402_5%OPT@
1 2
V38 10K_0402_5%OPT@
V38 10K_0402_5%OPT@
R
R
1 2
V40 10K_0402_5%OPT@
V40 10K_0402_5%OPT@
R
R
1 2
V15 10K_0402_5%OPT@
V15 10K_0402_5%OPT@
R
R
C
MDA26
C
MDA25
C
MDA27
C
MDA28
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
MDA12
MDA14
MDA15
MDA7
MDA11
MDA4
MDA5
MDA6
MDA22
MDA9
MDA21
MDA24
MDA23
MDA13
MDA8
MDA10
MDA29
C
MDA30
C
0
6
987
1
PV5
PV5
R
R
100_1206_10P8R_5%
100_1206_10P8R_5%
OPT@
OPT@
345
1
2
7
6
109
8
PV7
PV7
R
R
100_1206_10P8R_5%
100_1206_10P8R_5%
OPT@
OPT@
5
234
1
R
R
PV9
PV9
1 8
MDA28
C
2 7
MDA27
C
MDA25
C
MDA26
C
10k
10k
10k
6
3
4 5
100_0804_8P4R_5%
100_0804_8P4R_5%
OPT@
OPT@
12
V11 100_0402_5%
V11 100_0402_5%
R
R
OPT@
OPT@
2
1
V13 100_0402_5%
V13 100_0402_5%
R
R
OPT@
OPT@
ecurity Classification
ecurity Classification
ecurity Classification
S
S
S
ssued Date
ssued Date
ssued Date
I
I
I
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
T
T
T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
2
2
2
ompal Secret Data
ompal Secret Data
ompal Secret Data
C
C
C
eciphered Date
eciphered Date
eciphered Date
D
D
D
ompal Electronics, Inc.
ompal Electronics, Inc.
ompal Electronics, Inc.
C
C
itle
itle
itle
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
ustom
ustom
ustom
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
C
14x VRAM Interface
14x VRAM Interface
14x VRAM Interface
N
N
N
f
14 56Monday, March 11, 2013
f
14 56Monday, March 11, 2013
f
14 56Monday, March 11, 2013
o
o
o
.2
.2
.2
0
0
0
Page 15
5
U
U
V1C
V1C
AC3
FPA_TXC
I
AC4
FPA_TXC_N
I
Y4
FPA_TXD0
I
Y3
I
FPA_TXD0_N
AA3
FPA_TXD1
D D
C C
B B
A A
I
AA2
I
FPA_TXD1_N
AB1
FPA_TXD2
I
AA1
FPA_TXD2_N
I
AA4
FPA_TXD3
I
AA5
FPA_TXD3_N
I
AB5
FPB_TXC
I
AB4
FPB_TXC_N
I
AB3
I
FPB_TXD4
AB2
FPB_TXD4_N
I
AD3
I
FPB_TXD5
AD2
FPB_TXD5_N
I
AE1
I
FPB_TXD6
AD1
FPB_TXD6_N
I
AD4
FPB_TXD7
I
AD5
FPB_TXD7_N
I
T2
FPC_L0
I
T3
I
FPC_L0_N
T1
I
FPC_L1
R1
FPC_L1_N
I
R2
FPC_L2
I
R3
FPC_L2_N
I
N2
I
FPC_L3
N3
FPC_L3_N
I
V3
FPD_L0
I
V4
FPD_L0_N
I
U3
FPD_L1
I
U4
I
FPD_L1_N
T4
I
FPD_L2
T5
FPD_L2_N
I
R4
FPD_L3
I
R5
FPD_L3_N
I
N1
N
C
M1
N
C
M2
C
N
M3
C
N
K2
C
N
K3
C
N
K1
C
N
J1
C
N
M4
C
N
M5
C
N
L3
C
N
L4
C
N
K4
C
N
K5
C
N
J4
C
N
J5
N
C
N4
FPC_AUX_I2CW_SCL
I
N5
FPC_AUX_I2CW_SDA _N
I
P3
FPD_AUX_I2CX_SCL
I
P4
I
FPD_AUX_I2CX_SDA_N
J2
FPE_AUX_I2CY_SCL
I
J3
FPE_AUX_I2CY_SDA_N
I
H3
FPF_AUX_I2CZ_SCL
I
H4
I
FPF_AUX_I2CZ_SDA_N
N14P-GV2-S-A2_FCBGA595
N14P-GV2-S-A2_FCBGA595
N14PGV2R3@
N14PGV2R3@
P
P
art 3 of 6
art 3 of 6
C
C
N
N
ENERAL
ENERAL
G
G
ULTI_STRAP_REF0_GND
M
VDS/TMDS
VDS/TMDS
L
L
V
G
T
T
EST
EST
TAG_TRST_N
J
S
S
ERIAL
ERIAL
UFRST_N
B
TRAP0
S
TRAP1
S
TRAP2
S
TRAP3
S
TRAP4
S
HERMDP
T
HERMDN
T
DD_SENSE
ND_SENSE
ESTMODE
T
TAG_TCK
J
TAG_TDI
J
TAG_TDO
J
TAG_TMS
J
OM_CS_N
R
OM_SI
R
OM_SO
R
OM_SCLK
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
F11
AD10
AD7
B19
V5
V6
G1
G2
G3
G4
G5
G6
G7
V1
V2
W1
W2
W3
W4
D11
D10
E9
E10
F10
D1
D2
E4
E3
D3
C1
F6
F4
F5
F12
E12
F2
F1
AD9
AE5
AE6
AF6
AD6
AG4
D12
B12
A12
C12
V
V
R
R
M
GA_VCC_SENSE
GA_VSS_SENSE
OPT@
OPT@
2
1
V16 10K_0402_5%
V16 10K_0402_5%
S
TRAP0
S
TRAP1
S
TRAP2
S
TRAP3
S
TRAP4
ULTI_STRAP_REF0_GND
t
race width: 16mils
differential voltage sensing.
differential signal routing.
J
TAG_TCK
J
TAG_TDI
J
TAG_TDO
J
TAG_TMS
R
OM_SI
R
OM_SO
R
OM_SCLK
4
N14PGV2@
N14PGV2@
1 2
V17 40.2K_0402_1%
V17 40.2K_0402_1%
R
R
+
VGA_CORE
2
R
R
V26
V26
100_0402_1%
100_0402_1%
OPT@
OPT@
1
100_0402_1%
100_0402_1%
PAD
PAD
T
T
V3
V3
PAD
PAD
V4
V4
T
T
PAD
PAD
T
T
V5
V5
PAD
PAD
V6
V6
T
T
Strap Pin Strap Mapping
R
ROM_SI
ROM_SO
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
OPT@
OPT@
R
R
V35
V35
OM_SCLK
12
T
ESTMODE <13>
J
TAG_TRST <13>
SMB_ALT_ADDR
SUB_VENDOR
VGA_DEVICE
RAMCFG[0]
RAMCFG[1]
RAMCFG[2]
RAMCFG[3]
PCIE_MAX_SPEED
V
GA_VCC_SENSE <54>
V
GA_VSS_SENSE <54>
3
PD 10k
P
U 10k if VBIOS ROM exists
PD 10k if no VB IOS ROM
P
D 10k (no display)
Refer to RVL
PD 10k
M
ULTI LEVEL STRAPS
S
TRAP0
S
TRAP1
S
TRAP2
N14P-GV2
1
2
8
M
x
1
6
2
5
6
M
x
1
6
1
2
N14PGV2@
N14PGV2@
1
@
@
2
Samsung
Hynix
Micron
Micron
M
ULTI LEVEL STRAPS (for N14P-GV2)BINARY STRAPS (for N14M-GL)
Physical
Strapping pin
R
OM_SO
R
OM_SCLK
ROM_SI
STRAP0
STRAP1
STRAP2
S
TRAP3
S
TRAP4
Power Rail
+3VS_DGPU
+3VS_DGPU
+3VS_DGPU
+3VS_DGPU
+
3VS_DGPU 3GIO_PADCFG[0]3GIO_PADCFG[1]3GIO_PADCFG[2]
+
3VS_DGPU
+3VS_DGPU SOR0_EXPOSEDSOR2_EXPOSED SOR1_EXPOSED
+3VS_DGPU DP_PLL_VDD33V
SKU Device ID biit5 to bit0
N
14P-GV2
N
14M-GL
12
@
@
V19
V19
V18
V18
R
R
V27
V27
R
R
10K_0402_1%
10K_0402_1%
R
R
45.3K_0402_1%
45.3K_0402_1%
12
V28
V28
N14PGV2@
N14PGV2@
R
R
4.99K_0402_1%
4.99K_0402_1%
45.3K_0402_1%
45.3K_0402_1%
0
x1140 000000
+
3VS_DGPU
12
@
@
V20
V20
10K_0402_1%
10K_0402_1%
R
R
1
2
V29
V29
N14PGV2@
N14PGV2@
R
R
15K_0402_1%
15K_0402_1%
12
@
@
V21
V21
R
R
4.99K_0402_1%
4.99K_0402_1%
12
V30
V30
N14PGV2@
N14PGV2@
R
R
4.99K_0402_1%
4.99K_0402_1%
FB Memory gDDR3
9
00MHz
K4W2G1646E-BC11
K4W2G1646E-BC1A
1GHz
900MHz
H5TQ2G63DFR-11C
H5TQ2G63DFR-N0C
1GHz
M
T41K128M16JT-107G
900MHz
K
9
9
00MHz
00MHz
4W4G1646B-HC11Samsung
M
T41K256M16HA-107G
2
Logical
Strapping Bit3
F
B[1]
P
CI_DEVID[4]
USER[3]
3
GIO_PADCFG[3]
P
CI_DEVID[3]
S
OR3_EXPOSED
R
ESERVED
0
100100x1292
12
@
@
V22
V22
10K_0402_1%
10K_0402_1%
R
R
S
TRAP3
S
TRAP4
12
V31
V31
N14PGV2@
N14PGV2@
R
R
45.3K_0402_1%
45.3K_0402_1%
ROM_SIGPU
PD 45.3K
P
D 34.8K
PD 30K
PD 20K
PD 10K
Logical
Strapping Bit2
FB[0]
PCIE_SPEED_CHANGE_GEN3
R
R
V31
V31
10K_0402_1%
10K_0402_1%
N14MGL@
N14MGL@
N14M-GL
Logical
Strapping Bit1
SMB_ALT_ADDR
P
SUB_VENDOR
CI_DEVID[5]
R
AMCFG[1]RAMCFG[3] RAMCFG[2]
PCIE_MAX_SPEED
R
esistor Values
5
K
1
0K
15K
20K
25K
30K
35K
45K
R
OM_SI
R
OM_SO
R
OM_SCLK
For X76 (N14P-GV2)For X76 (N14M-GL)
FB Memory gDDR3
Samsung
1
2
8
M
Hynix
x
1
6
Micron
Samsung K4W4G1646B-HC11
2
5
6
M
Micron
x
1
6
1GHz
1GHz
900MHz
9
00MHz
9
00MHz
K4W2G1646E-BC11900MHz
K4W2G1646E-BC1A
H5TQ2G63DFR-11C900MHz
H5TQ2G63DFR-N0C
M
M
1
L
ogical
Strapping Bit0
V
GA_DEVICE
PEX_PLLEN_TERM
RAMCFG[0]
USER[0]USER[1]USER[2]
PCI_DEVID[0]PCI_DEVID[1]PCI_DEVID[2]
P
ull-up to +3VS
_DGPU
1
000
1001
1010
1011
1100
1101
1110
1111
12
12
@
@
V24
V24
V23
V23
N14PGV2@
N14PGV2@
R
R
R
R
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
12
1
2
N14MGL@
N14MGL@
N14MGL@
N14MGL@
V33
V33
V32
V32
R
R
R
R
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
T41K128M16JT-107G
T41K256M16HA-107G
P
ull-down to Gnd
0000
0001
0010
0011
0100
0101
0110
0111
+
3VS_DGPU
12
V25
V25
N14PGV2@
N14PGV2@
R
R
4.99K_0402_1%
4.99K_0402_1%
12
N14MGL@
N14MGL@
V34
V34
R
R
10K_0402_1%
10K_0402_1%
STRAP[3:0]GPU
0101
0110
0001
1011
1101
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
2
Date: Sheet
ompal Electronics, Inc.
V
V
V
GA_N14x LVDS&TMDS
GA_N14x LVDS&TMDS
GA_N14x LVDS&TMDS
1
0
0
0
.2
.2
o
o
o
15 56Monday, March 11, 2013
15 56Monday, March 11, 2013
15 56Monday, March 11, 2013
.2
f
f
f
Page 16
5
4
3
2
1
U
nder GPU
+
VRAM_1.5VS
D D
Under GPU
1
2
1
1
1
1
V32
V32
C
C
OPT@
OPT@
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
V33
V33
V24
V24
C
C
C
C
2
2
OPT@
OPT@
2
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
V34
V34
C
C
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
V35
V35
V25
V25
C
C
C
C
2
2
OPT@
OPT@
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
Near GPU
1
1
V43
V43
V44
V44
C
C
C
C
2
2
OPT@
OPT@
OPT@
OPT@
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C C
B B
V1D
V1D
U
U
3
B26
BVDDQ_01
F
C25
BVDDQ_02
F
E23
BVDDQ_03
F
E26
BVDDQ_04
F
F14
BVDDQ_05
F
F21
BVDDQ_06
F
G13
BVDDQ_07
F
G14
BVDDQ_08
F
G15
BVDDQ_09
F
G16
BVDDQ_10
F
G18
BVDDQ_11
F
G19
BVDDQ_12
F
G20
BVDDQ_13
F
G21
BVDDQ_14
F
H24
BVDDQ_15
F
H26
BVDDQ_16
F
J21
BVDDQ_17
F
K21
BVDDQ_18
F
L22
BVDDQ_19
F
L24
BVDDQ_20
F
L26
BVDDQ_21
F
M21
BVDDQ_22
F
N21
BVDDQ_23
F
R21
BVDDQ_24
F
T21
BVDDQ_25
F
V21
BVDDQ_26
F
W21
BVDDQ_27
F
V7
FPAB_PLLVDD_1
I
W7
FPAB_PLLVDD_2
I
AA6
FPAB_RSET
I
W6
FPA_IOVDD
I
Y6
FPB_IOVDD
I
M7
FPC_PLLVDD_1
I
N7
FPC_PLLVDD_2
I
T6
FPC_RSET
I
P6
FPC_IOVDD
I
T7
FPD_PLLVDD_2
I
R7
FPD_PLLVDD_1
I
U6
FPD_RSET
I
R6
FPD_IOVDD
I
J7
N
K7
N
K6
N
H6
N
J6
N
N14P-GV2-S-A2_FCBGA595
N14P-GV2-S-A2_FCBGA595
N14PGV2R3@
N14PGV2R3@
art 4 of 6
Part 4 of 6
P
500 mA 2000 mA
C
C
C
C
C
EX_IOVDDQ_1
P
EX_IOVDDQ_2
P
EX_IOVDDQ_3
P
EX_IOVDDQ_4
P
EX_IOVDDQ_5
P
EX_IOVDDQ_6
P
EX_IOVDDQ_7
P
EX_IOVDDQ_8
P
EX_IOVDDQ_9
P
EX_IOVDDQ_10
P
EX_IOVDDQ_11
P
EX_IOVDDQ_12
P
EX_IOVDDQ_13
P
EX_IOVDDQ_14
P
EX_IOVDD_1
P
EX_IOVDD_2
P
EX_IOVDD_3
P
EX_IOVDD_4
P
EX_IOVDD_5
P
EX_IOVDD_6
P
DD33_1
V
DD33_2
V
DD33_3
V
OWER
OWER
DD33_4
V
P
P
B_CAL_PD_VDDQ
F
B_CAL_PU_GND
F
B_CAL_TERM_GND
F
EX_PLL_HVDD_1
P
EX_PLL_HVDD_2
P
EX_SVDD_3V3
P
1
20mA
EX_PLLVDD_1
P
EX_PLLVDD_2
P
AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25
AF26
AF27
AA22
AB23
AC24
AD25
AE26
AE27
G10
G12
G8
G9
D22
C24
B25
AA8
AA9
AB8
AA14
AA15
+
FB_CAL_PD_VDDQ
F
B_CAL_PU_GND
F
B_CAL_TERM_GND
Under GPU
Near Ball
1
V54
V54
C
C
2
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2
2
2
1
2
Near GPU
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
V55
V55
C
C
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
1
2
V26
V26
C
C
OPT@
OPT@
V36
V36
C
C
OPT@
OPT@
R
R
V3940.2_0402_1%
V3940.2_0402_1%
1
R
R
V4142.2_0402_1%
V4142.2_0402_1%
1
R
R
V4251.1_0402_1%
V4251.1_0402_1%
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
+
PEX_PLLVDD
V56
V56
C
C
OPT@
OPT@
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
V23
V23
C
C
2
OPT@
OPT@
1
V37
V37
C
C
2
OPT@
OPT@
N
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
+
VRAM_1.5VS
midway between GPU
ear GPU
and Power suppl y
1
1
V28
V28
V27
V27
C
C
C
C
2
2
OPT@
OPT@
OPT@
OPT@
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
1
V38
V38
V39
V39
C
C
C
C
2
2
OPT@
OPT@
OPT@
OPT@
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
Under GPU
1
1
V45
V45
V46
V46
C
C
C
C
2
2
OPT@
OPT@
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
L
L
V4
V4
2
N14MGL@
N14MGL@
R
R
V1
V1
0_0603_5%
0_0603_5%
N14PGV2@
N14PGV2@
1
12
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
+
1.05VS_DGPU
V29
V29
C
C
OPT@
OPT@
10U_0603_6.3V6M
10U_0603_6.3V6M
V40
V40
C
C
OPT@
OPT@
10U_0603_6.3V6M
10U_0603_6.3V6M
V47
V47
C
C
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
Near GPU
1.05VS_DGPU
+
1
1
V30
V30
C
C
2
2
OPT@
OPT@
22U_0805_6.3V6M
22U_0805_6.3V6M
+
1.05VS_DGPU
1
1
V41
V41
C
C
2
2
OPT@
OPT@
22U_0805_6.3V6M
22U_0805_6.3V6M
+
1
1
V48
V48
C
C
2
2
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
U
nder GPU
Close to AH12/A G12
V31
V31
C
C
OPT@
OPT@
22U_0805_6.3V6M
22U_0805_6.3V6M
V42
V42
C
C
OPT@
OPT@
22U_0805_6.3V6M
22U_0805_6.3V6M
3VS_DGPU
V49
V49
C
C
OPT@
OPT@
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
2
+
Near GPU
1
1
V51
V51
V50
V50
C
C
C
C
2
2
OPT@
OPT@
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
3VS_DGPU
1
V53
V53
V52
V52
C
C
C
C
2
OPT@
OPT@
OPT@
OPT@
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
A A
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
Title
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
2
Date: Sheet
ompal Electronics, Inc.
V
V
V
GA_N14x POWER
GA_N14x POWER
GA_N14x POWER
1
0
0
0
.2
.2
o
o
o
16 56Monday, March 11, 2013
16 56Monday, March 11, 2013
16 56Monday, March 11, 2013
.2
f
f
f
Page 17
5
V1E
V1E
U
U
A2
G
A26
G
AB11
G
AB14
G
AB17
G
AB20
G
AB24
D D
C C
B B
G
AC2
G
AC22
G
AC26
G
AC5
G
AC8
G
AD12
G
AD13
G
AD15
G
AD16
G
AD18
G
AD19
G
AD21
G
AD22
G
AE11
G
AE14
G
AE17
G
AE20
G
AF1
G
AF11
G
AF14
G
AF17
G
AF20
G
AF23
G
AF5
G
AF8
G
AG2
G
AG26
G
B1
G
B11
G
B14
G
B17
G
B20
G
B23
G
B27
G
B5
G
B8
G
E11
G
E14
G
E17
G
E2
G
E20
G
E22
G
E25
G
E5
G
E8
G
H2
G
H23
G
H25
G
H5
G
N14P-GV2-S-A2_FCBGA595
N14P-GV2-S-A2_FCBGA595
N14PGV2R3@
N14PGV2R3@
ND_001
ND_002
ND_003
ND_004
ND_005
ND_006
ND_007
ND_008
ND_009
ND_010
ND_011
ND_012
ND_013
ND_014
ND_015
ND_016
ND_017
ND_018
ND_019
ND_020
ND_021
ND_022
ND_023
ND_024
ND_025
ND_026
ND_027
ND_028
ND_029
ND_030
ND_031
ND_032
ND_033
ND_034
ND_035
ND_036
ND_037
ND_038
ND_039
ND_040
ND_041
ND_042
ND_043
ND_044
ND_045
ND_046
ND_047
ND_048
ND_049
ND_050
ND_051
ND_052
ND_053
ND_054
ND_055
ND_056
art 5 of 6
art 5 of 6
P
P
ND
ND
G
G
ND_057
G
G
ND_058
G
ND_059
G
ND_060
G
ND_061
ND_062
G
ND_063
G
G
ND_064
ND_065
G
G
ND_066
G
ND_067
ND_068
G
ND_069
G
ND_070
G
ND_071
G
ND_072
G
ND_073
G
ND_074
G
ND_075
G
ND_076
G
ND_077
G
ND_078
G
ND_079
G
ND_080
G
ND_081
G
ND_082
G
ND_083
G
ND_084
G
ND_085
G
ND_086
G
ND_087
G
ND_088
G
ND_089
G
ND_090
G
ND_091
G
ND_092
G
ND_093
G
ND_094
G
ND_095
G
ND_096
G
ND_097
G
ND_098
G
ND_099
G
ND_100
G
ND_101
G
ND_102
G
ND_103
G
ND_104
G
ND_105
G
ND_106
G
ND_107
G
ND_108
G
G
ND_109
ND_110
G
G
ND_111
G
ND_112
K11
K13
K15
K17
L10
L12
L14
L16
L18
L2
L23
L25
L5
M11
M13
M15
M17
N10
N12
N14
N16
N18
P11
P13
P15
P17
P2
P23
P26
P5
R10
R12
R14
R16
R18
T11
T13
T15
T17
U10
U12
U14
U16
U18
U2
U23
U26
U5
V11
V13
V15
V17
Y2
Y23
Y26
Y5
AA7
G
ND
AB7
G
ND
4
+
VGA_CORE
F
or GC6
K10
K12
K14
K16
K18
L11
L13
L15
L17
M10
M12
M14
M16
M18
N11
N13
N15
N17
P10
P12
F
B_CLAMP<13,14,41>
V
GA_PWROK<30,54>
UV1F
UV1F
V
DD_001
V
DD_002
V
DD_003
V
DD_004
V
DD_005
V
DD_006
V
DD_007
V
DD_008
DD_009
V
DD_010
V
DD_011
V
DD_012
V
DD_013
V
DD_014
V
DD_015
V
DD_016
V
DD_017
V
DD_018
V
DD_019
V
DD_020
V
N14P-GV2-S-A2_FCBGA595
N14P-GV2-S-A2_FCBGA595
N14PGV2R3@
N14PGV2R3@
P
P
art 6 of 6
art 6 of 6
OWER
OWER
P
P
V18
DD_041
V
V16
DD_040
V
V14
DD_039
V
V12
DD_038
V
V10
DD_037
V
U17
DD_036
V
U15
DD_035
V
U13
DD_034
V
U11
DD_033
V
T18
DD_032
V
T16
DD_031
V
T14
DD_030
V
T12
DD_029
V
T10
DD_028
V
R17
DD_027
V
R15
DD_026
V
R13
DD_025
V
R11
DD_024
V
P18
DD_023
V
P16
DD_022
V
P14
DD_021
V
+
3VS
5
U
U
V2
V2
2
cc
B
V
1
A
G
NC7SZ32P5X_SC70-5
NC7SZ32P5X_SC70-5
3
2
1
R
R
V50 0_0402_5%
V50 0_0402_5%
N14MGL@
N14MGL@
Y
3
+
VGA_CORE
N14PGV2@
N14PGV2@
4
1
.5V_PWR_EN
2
1.05VS_VCCP to +1.05VS_DGPU
+
+
+
1.05VS_VCCP
V
gs=4.5V,Id=6.5A ,Rds<22mohm
Q
Q
V3
OPT@
V3
OPT@
13
D
D
2
G
AO3416_SOT23-3
AO3416_SOT23-3
+
1.05VS_DGPU
+
1.5V to +VRAM_1.5VS
+
1.5V
Q
Q
V6
OPT@
V6
OPT@
8
D
S
7
D
S
6
D
S
5
D
G
FDS6676AS_SO8
FDS6676AS_SO8
1
C
C
V60
C
C
V59
V59
O
O
PT@
PT@
V60
O
O
PT@
PT@
2
.7U_0603_6.3V6K
.7U_0603_6.3V6K
4
4
G
S
+
VRAM_1.5VS
V
1
2
3
4
1
2
S
1
C
C
V57
V57
O
O
PT@
PT@
2
gs=10V,Id=14.5A ,Rds=6mohm
V
RAM_1.5VS_GATE
12
R
R
V48
V48
820K_0402_5%OPT@
820K_0402_5%OPT@
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
.01U_0402_25V7K
.01U_0402_25V7K
0
0
1
.5V_PWR_EN
5VALW
1
R
R
V43
V43
270K_0402_5%
270K_0402_5%
OPT@
OPT@
2
6
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
V
GA_PWROK
OPT@
OPT@
R
R
1 2
180K_0402_5%
180K_0402_5%
61
Q
Q
OPT@
OPT@
5
OPT@
OPT@
1
V47
V47
V7A
V7A
2
1
V5B
V5B
Q
Q
G
G
.5V_PWR_EN#
.01U_0402_25V7K
.01U_0402_25V7K
0
0
OPT@
OPT@
Q
Q
V4A
V4A
2
S
S
V
GA_PWROK#
61
D
D
Q
Q
V5A
V5A
2
G
G
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
S
S
OPT@
OPT@
B
+
5
1
OPT@
OPT@
34
D
D
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
1
+
1.05VS_DGPU
2
R
R
V44
V44
22_0805_5%OPT@
22_0805_5%OPT@
1
3
OPT@
OPT@
Q
Q
V4B
V4B
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
4
1 2
V45100K_0402_5%
V45100K_0402_5%
R
R
OPT@
OPT@
R
R
V46
V46
470_0805_5%
470_0805_5%
OPT@
OPT@
1 2
3
Q
Q
V7B
V7B
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
OPT@
OPT@
4
+
5VALW
2
R
R
V49100K_0402_5%
V49100K_0402_5%
+
5VALW
+
3VS to +3VS_DGPU
+
+
3VS_DGPU
2
R
R
V51
V51
470_0805_5%
470_0805_5%
OPT@
OPT@
1
3
Q
Q
V9B
V9B
5
D
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
A A
5
4
OPT@
OPT@
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
GPU_PWR_EN#
4
3
+
VGA_CORE
2
R
R
V52
V52
470_0805_5%
470_0805_5%
OPT@
OPT@
1
3
Q
Q
V2B
V2B
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
OPT@
OPT@
4
C
C
C
ompal Secret Data
ompal Secret Data
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
D
GPU_PWR_EN<29>
2
D
GPU_PWR_EN#
+
3VS
R
R
V53
V53
10K_0402_5%OPT@
10K_0402_5%OPT@
1 2
V54
V54
R
R
1
33K_0402_5%
33K_0402_5%
61
OPT@
Q
Q
V9A
V9A
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
OPT@
2
OPT@
OPT@
T
T
T
itle
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
Date: Sheet
2
C
C
V61
V61
0.1U_0402_10V7K
0.1U_0402_10V7K
OPT@
OPT@
1
2
AO3413_SOT23
AO3413_SOT23
2
C
C
V62
V62
OPT@
OPT@
0.01U_0402_25V7K
0.01U_0402_25V7K
1
C
C
C
V
V
V
GA_N14x POWER & GND
GA_N14x POWER & GND
GA_N14x POWER & GND
3VS
V
gs=-4.5V,Id=3A, Rds<97mohm
S
S
Q
Q
V11
V11
G
G
2
OPT@
OPT@
D
D
1 3
+
3VS_DGPU
ompal Electronics, Inc.
ompal Electronics, Inc.
ompal Electronics, Inc.
1
0
0
0
.2
.2
o
o
o
17 56Monday, March 11, 2013
17 56Monday, March 11, 2013
17 56Monday, March 11, 2013
.2
f
f
f
Page 18
5
R
ANK 0 [31...0]
V
RAM DDR3 Chips
D
1
2
+
12
12
+
12
QSA[3..0]
D
QSA#[3..0]
D
QMA[3..0]
M
DA[31..0]
C
MDA[30..0]
MEM_VREF_CA0
1
V63
V63
C
C
0.01U_0402_25V7K
0.01U_0402_25V7K
OPT@
OPT@
2
MEM_VREF_DQ0
1
V64
V64
C
C
0.01U_0402_25V7K
0.01U_0402_25V7K
OPT@
OPT@
2
+
MEM_VREF_CA0
+
MEM_VREF_DQ0
243_0402_1%
243_0402_1%
D
QSA[3..0]<14,20>
D D
D
QSA#[3..0]<14,20>
D
QMA[3..0]<14,20>
M
DA[31..0]<14,20>
C
MDA[30..0]
+
VRAM_1.5VS
V55
V55
R
R
1K_0402_1%
1K_0402_1%
OPT@
OPT@
V56
V56
R
R
1K_0402_1%
1K_0402_1%
OPT@
OPT@
C C
B B
V57
V57
R
R
1K_0402_1%
1K_0402_1%
OPT@
OPT@
V58
V58
R
R
1K_0402_1%
1K_0402_1%
OPT@
OPT@
+
VRAM_1.5VS
+
MEM_VREF_CA0
+
MEM_VREF_DQ0
12
OPT@
OPT@
V60
V60
R
R
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
D
D
D
D
D
D
C
MDA7
MDA10
MDA24
MDA6
MDA22
MDA26
MDA5
MDA21
MDA8
MDA4
MDA25
MDA23
MDA9
MDA12
MDA14
MDA29
MDA13
MDA27
LKA0
LKA0#
MDA3
MDA0
MDA2
MDA11
MDA15
MDA28
QSA1
QSA2
QMA1
QMA2
QSA#1
QSA#2
MDA20
Z
4
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
J7
K
7
K9
K1
L2
J
3
K
3
L
3
F3
C7
E7
D3
G
3
B
7
T
2
L8
Q0
J1
L
1
J9
L9
U
U
V3
@
V3
@
V
REFCA
V
REFDQ
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10/AP
A
11
A
12
A
13
A
14
A
15/BA3
B
A0
B
A1
B
A2
C
K
C
K
C
KE/CKE0
O
DT/ODT0
C
S/CS0
R
AS
C
AS
W
D
QSL
D
QSU
D
ML
D
MU
D
QSL
D
QSU
R
ESET
Z
Q/ZQ0
N
C/ODT1
N
C/CS1
N
C/CE1
N
CZQ1
K4B1G1646E-HC12_FBGA96
K4B1G1646E-HC12_FBGA96
E
3
10mA
9
9
6-BALL
6-BALL
SDRAM DDR3
SDRAM DDR3
D
QL0
D
QL1
D
QL2
D
QL3
D
QL4
D
QL5
D
QL6
D
QL7
D
QU0
D
QU1
D
QU2
D
QU3
D
QU4
D
QU5
D
QU6
D
QU7
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
V
DDQ
V
DDQ
DDQ
V
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
M
DA9
M
DA12
M
DA8
M
DA15
M
DA13
M
DA11
M
DA10
M
DA14
M
DA18
M
DA22
M
DA16
M
DA23
M
DA17
M
DA20
M
DA19
M
DA21
+
VRAM_1.5VS
+
VRAM_1.5VS
G
roup1
Group2
3
243_0402_1%
243_0402_1%
+
MEM_VREF_CA0
+
MEM_VREF_DQ0
OPT@
OPT@
V61
V61
R
R
2
M
ode E
Address
CMD0
Rank 0 Rank 1
0..31
ODT
CMD1
CMD2
CMD3
CMD4
V4
@
V4
@
U
U
M8
REFCA
V
H1
V
REFDQ
N3
C
MDA7
C
MDA10
C
MDA24
C
MDA6
C
MDA22
C
MDA26
C
MDA5
C
MDA21
C
MDA8
C
MDA4
C
MDA25
C
MDA23
C
MDA9
C
MDA12
C
MDA14
C
MDA29
C
MDA13
C
MDA27
C
LKA0
C
LKA0#
C
MDA3
C
MDA0
C
MDA2
C
MDA11
C
MDA15
C
MDA28
D
QSA0
D
QSA3
D
QMA0
D
QMA3
D
QSA#0
D
QSA#3
C
MDA20
Z
Q1
1
2
0
A
P7
1
A
P3
2
A
N2
3
A
P8
4
A
P2
5
A
R8
6
A
R2
7
A
T8
8
A
R3
9
A
L7
10/AP
A
R7
11
A
N7
12
A
T3
13
A
T7
A
14
M7
A
15/BA3
M2
A0
B
N8
A1
B
M3
B
A2
J7
K
C
7
K
K
C
K9
KE/CKE0
C
K1
DT/ODT0
O
L2
S/CS0
C
3
J
AS
R
3
K
AS
C
3
L
E
W
310mA
F3
QSL
D
C7
QSU
D
E7
ML
D
D3
MU
D
3
G
QSL
D
7
B
QSU
D
2
T
ESET
R
L8
Q/ZQ0
Z
J1
C/ODT1
N
1
L
C/CS1
N
J9
C/CE1
N
L9
N
CZQ1
6-BALL
6-BALL
9
9
SDRAM DDR3
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
K4B1G1646E-HC12_FBGA96
E3
M
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
DA6
M
DA1
M
DA5
M
DA0
M
DA4
M
DA2
M
DA7
M
DA3
M
DA30
M
DA26
M
DA29
M
DA24
M
DA28
M
DA27
M
DA31
M
DA25
+
VRAM_1.5VS
+
VRAM_1.5VS
Group0
Group3
P
lace close to t he first T poin t
C
LKA0<14,20>
C
LKA0#<14,20>
QL0
D
QL1
D
QL2
D
QL3
D
QL4
D
QL5
D
QL6
D
QL7
D
QU0
D
QU1
D
QU2
D
QU3
D
QU4
D
QU5
D
QU6
D
D
QU7
DD
V
DD
V
DD
V
DD
V
DD
V
V
DD
V
DD
V
DD
V
DD
DDQ
V
DDQ
V
DDQ
V
DDQ
V
V
DDQ
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
CMD5
CMD6
CMD7
CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
CMD15
CMD16
CMD17
CMD18
CMD19
CMD20
CMD21 A7
CMD22
CMD23
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29
CMD30
1
OPT@
OPT@
V63
V63
R
R
160_0402_1%
160_0402_1%
2
CS0#
CKE
A9
A6
A3
A0
A8
A12
A1
RAS#
A13
BA1
A14
CAS#
RST
A7
A4
A11
A2
A10
A5
BA2
WE#
BA0
1
2..63
3
0..31 32..63
ODT
CS1#
CKE
A11
A6
A3
A
A8
A12 A0
A1
0
A7 A7
BA1 BA1
A12 A12
A8 A8
A0
A2 A2
RAS# RAS# RAS#
A13
A14
A3
A14
CAS#
A13 A13
CAS# CAS#
ODT
CS0#
CKE
RST RST RST
A6
A4
A11
A2
A10
A5
A5 A5
A9 A9
A1 A1
WE# WE#
A4 A4
BA2
WE#
BA0
A10 A10
BA0 BA0
BA2
A11A9
A14
A3BA1
ODT
CS1#
CKE
A6
BA2
Place close to RANK0 VRAM
+
VRAM_1.5VS
1
1
1
V68
V68
V67
V67
C
C
C
C
2
2
2
OPT@
OPT@
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
A A
5
4
1
1
V70
V70
V69
V69
C
C
C
C
2
2
OPT@
OPT@
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
V71
V71
V72
V72
C
C
C
C
2
2
OPT@
OPT@
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
V73
V73
C
C
2
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
1
V75
V75
V76
V74
V74
C
C
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
V76
C
C
C
C
2
2
OPT@
OPT@
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
ecurity Classification
ecurity Classification
ecurity Classification
S
S
S
ssued Date
ssued Date
ssued Date
I
I
I
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
T
T
T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
+
VRAM_1.5VS
1
1
V77
V77
C
C
2
2
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
2
2
2
1
1
V79
V79
V78
V78
C
C
C
C
2
2
OPT@
OPT@
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
ompal Secret Data
ompal Secret Data
ompal Secret Data
C
C
C
eciphered Date
eciphered Date
eciphered Date
D
D
D
1
V80
V80
C
C
2
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
V83
V81
V81
C
C
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
V83
V82
V82
C
C
C
C
2
2
OPT@
OPT@
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
2
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
V85
V85
V84
V84
C
C
C
C
2
2
OPT@
OPT@
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
+
VRAM_1.5VS
1
V87
V86
V86
C
C
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
Title
Title
T
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
ustom
ustom
ustom
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
V87
C
C
2
OPT@
OPT@
22U_0805_6.3V6M
22U_0805_6.3V6M
ompal Electronics, Inc.
ompal Electronics, Inc.
ompal Electronics, Inc.
C
C
C
GA_N14x VRAM RANK 0L
GA_N14x VRAM RANK 0L
GA_N14x VRAM RANK 0L
V
V
V
18 56Monday, March 11, 2013
18 56Monday, March 11, 2013
1
18 56Monday, March 11, 2013
f
f
f
o
o
o
.2
.2
.2
0
0
0
Page 19
5
R
ANK 0 [63...32]
V
RAM DDR3 Chips
D
12
+
12
12
+
1
2
QSA[7..4]
D
QSA#[7..4]
D
QMA[7..4]
M
DA[63..32]
C
MDA[30..0]
MEM_VREF_CA1
1
V65
V65
C
C
0.01U_0402_25V7K
0.01U_0402_25V7K
OPT@
OPT@
2
MEM_VREF_DQ1
1
V66
V66
C
C
0.01U_0402_25V7K
0.01U_0402_25V7K
OPT@
OPT@
2
+
MEM_VREF_CA1
+
MEM_VREF_DQ1
+
+
243_0402_1%
243_0402_1%
D
QSA[7..4]<14,21>
D
D D
C C
B B
QSA#[7..4]<14,21>
D
QMA[7..4]<14,21>
M
DA[63..32]<14,21>
C
MDA[30..0]<14,18,20,21>
V59
V59
R
R
1K_0402_1%
1K_0402_1%
OPT@
OPT@
V62
V62
R
R
1K_0402_1%
1K_0402_1%
OPT@
OPT@
R
R
V64
V64
1K_0402_1%
1K_0402_1%
OPT@
OPT@
R
R
V65
V65
1K_0402_1%
1K_0402_1%
OPT@
OPT@
+
VRAM_1.5VS
+
VRAM_1.5VS
MEM_VREF_CA1
MEM_VREF_DQ1
C
MDA7
C
MDA10
C
MDA24
C
MDA6
C
MDA22
C
MDA26
C
MDA5
C
MDA21
C
MDA8
C
MDA4
C
MDA25
C
MDA23
C
MDA9
C
MDA12
C
MDA14
C
MDA29
C
MDA13
C
MDA27
C
LKA1
C
LKA1#
C
MDA19
C
MDA16
C
MDA18
C
MDA11
C
MDA15
C
MDA28
D
QSA4
D
QSA7
D
QMA4
D
QMA7
D
QSA#4
D
QSA#7
C
MDA20
Z
Q2
12
OPT@
OPT@
V71
V71
R
R
4
V5
V5
U
U
M8
REFCA
V
H1
REFDQ
V
N3
0
A
P7
1
A
P3
2
A
N2
3
A
P8
4
A
P2
5
A
R8
6
A
R2
7
A
T8
8
A
R3
9
A
L7
10/AP
A
R7
11
A
N7
12
A
T3
13
A
T7
14
A
M7
15/BA3
A
M2
A0
B
N8
A1
B
M3
A2
B
J7
K
C
7
K
K
C
K9
KE/CKE0
C
K1
DT/ODT0
O
L2
S/CS0
C
3
J
AS
R
3
K
AS
C
3
L
E
W
F3
QSL
D
C7
QSU
D
E7
ML
D
D3
MU
D
3
G
QSL
D
7
B
QSU
D
2
T
ESET
R
L8
Q/ZQ0
Z
J1
C/ODT1
N
1
L
C/CS1
N
J9
C/CE1
N
L9
CZQ1
N
6-BALL
6-BALL
9
9
SDRAM DDR3
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
K4B1G1646E-HC12_FBGA96
3
U
Z
Q3
12
U
V6
@
V6
@
M8
V
REFCA
H1
V
REFDQ
N3
A
0
P7
A
1
P3
A
2
N2
A
3
P8
A
4
P2
A
5
R8
A
6
R2
A
7
T8
A
8
R3
A
9
L7
A
10/AP
R7
A
11
N7
A
12
T3
A
13
T7
A
14
M7
A
15/BA3
M2
B
A0
N8
B
A1
M3
B
A2
J7
C
K
K
7
C
K
K9
C
KE/CKE0
K1
O
DT/ODT0
L2
C
S/CS0
J
3
R
AS
K
3
C
AS
L
3
W
E
F3
D
QSL
C7
D
QSU
E7
D
ML
D3
D
MU
G
3
D
QSL
B
7
D
QSU
T
2
R
ESET
L8
Z
Q/ZQ0
J1
N
C/ODT1
L
1
N
C/CS1
J9
N
C/CE1
L9
N
CZQ1
9
9
6-BALL
6-BALL
SDRAM DDR3
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
K4B1G1646E-HC12_FBGA96
@
@
3
10mA 310mA
E3
M
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
DA35
M
DA37
M
DA32
M
DA36
M
DA33
M
DA38
M
DA34
M
DA39
M
DA58
M
DA62
M
DA56
M
DA63
M
DA57
M
DA61
M
DA59
M
DA60
+
VRAM_1.5VS
+
VRAM_1.5VS
G
roup4
QL0
D
QL1
D
QL2
D
QL3
D
QL4
D
QL5
D
QL6
D
QL7
D
QU0
D
QU1
D
QU2
D
QU3
D
QU4
D
QU5
D
QU6
D
QU7
D
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
V
DDQ
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
V
SS
SS
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
+
MEM_VREF_CA1
+
MEM_VREF_DQ1
OPT@
OPT@
R
R
V72
V72
243_0402_1%
243_0402_1%
C
MDA7
C
MDA10
C
MDA24
C
MDA6
C
MDA22
C
MDA26
C
MDA5
C
MDA21
C
MDA8
C
MDA4
C
MDA25
C
MDA23
C
MDA9
C
MDA12
C
MDA14
C
MDA29
C
MDA13
C
MDA27
C
LKA1
C
LKA1#
C
MDA19
C
MDA16
C
MDA18
C
MDA11
C
MDA15
C
MDA28
D
QSA5
D
QSA6
D
QMA5
D
QMA6
D
QSA#5
D
QSA#6
C
MDA20
2
M
ode E
Address
CMD0
R
0..31
ODT
CMD1
CMD2
CMD3
CMD4
E3
M
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
DA45
M
DA41
M
DA46
M
DA40
M
DA44
M
DA43
M
DA47
M
DA42
M
DA54
M
DA50
M
DA55
M
DA48
M
DA53
M
DA51
M
DA52
M
DA49
+
VRAM_1.5VS
+
VRAM_1.5VS
Group5
Group6Group7
P
lace close to t he first T poin t
C
LKA1<14,21>
C
LKA1#<14,21>
D
QL0
D
QL1
D
QL2
D
QL3
D
QL4
D
QL5
D
QL6
D
QL7
D
QU0
D
QU1
D
QU2
D
QU3
D
QU4
D
QU5
D
QU6
D
QU7
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
CMD5
CMD6
CMD7
CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
CMD15
CMD16
CMD17
CMD18
CMD19
CMD20
CMD21 A7
CMD22
CMD23
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29
CMD30
12
OPT@
OPT@
V74
V74
R
R
160_0402_1%
160_0402_1%
CS0#
CKE
A9
A6
A3
A0
A8
A12
A1
RAS#
A13
BA1
A14
CAS#
RST
A7
A4
A11
A2
A10
A5
BA2
WE#
BA0
1
ank 0 Rank 1
2..63
3
0..31 32..63
ODT
CS1#
CKE
A11
0
A7 A7
BA1 BA1
A12 A12
A8 A8
A0
A2 A2
A6
A3
A
A8
A12 A0
A1
RAS# RAS# RAS#
A13
A14
A3
A14
CAS#
A13 A13
CAS# CAS#
ODT
CS0#
CKE
RST RST RST
A6
A4
A11
A2
A10
A5
A5 A5
A9 A9
A1 A1
WE# WE#
A4 A4
BA2
WE#
BA0
A10 A10
BA0 BA0
BA2
A11A9
A14
A3BA1
ODT
CS1#
CKE
A6
BA2
Place close to RANK1 VRAM
+
VRAM_1.5VS
1
1
V92
V92
C
C
2
2
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
A A
5
4
1
1
V93
V93
V94
V94
C
C
C
C
2
2
OPT@
OPT@
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
1
V95
V95
V96
V96
C
C
C
C
2
2
OPT@
OPT@
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
V98
V98
V97
V97
C
C
C
C
2
2
OPT@
OPT@
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
V99
V99
V100
V100
V101
C
C
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
V101
C
C
C
C
2
2
OPT@
OPT@
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
ecurity Classification
ecurity Classification
ecurity Classification
S
S
S
ssued Date
ssued Date
ssued Date
I
I
I
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
T
T
T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
+
VRAM_1.5VS
1
V103
V103
V102
V102
C
C
C
C
2
OPT@
OPT@
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
ompal Secret Data
ompal Secret Data
ompal Secret Data
C
C
C
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
D
D
D
1
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
2
2
2
1
V105
V105
V104
V104
C
C
C
C
2
OPT@
OPT@
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
eciphered Date
eciphered Date
eciphered Date
1
2
1
1
V107
V106
V106
V107
C
C
C
C
2
2
OPT@
OPT@
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
V108
V108
C
C
2
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
V109
V109
V110
V110
C
C
C
C
2
2
OPT@
OPT@
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
+
VRAM_1.5VS
V111
V111
C
C
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
itle
itle
T
T
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
ustom
ustom
ustom
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
1
V112
V112
C
C
2
22U_0805_6.3V6M
22U_0805_6.3V6M
DRANK@
DRANK@
ompal Electronics, Inc.
ompal Electronics, Inc.
ompal Electronics, Inc.
C
C
C
GA_N14x VRAM RANK 0H
GA_N14x VRAM RANK 0H
GA_N14x VRAM RANK 0H
V
V
V
19 56Monday, March 11, 2013
19 56Monday, March 11, 2013
1
19 56Monday, March 11, 2013
f
f
o
o
o
f
.2
.2
.2
0
0
0
Page 20
5
14,18,19,21>
RANK 1 [31...0]
V
RAM DDR3 Chips
D
D
QSA[3..0]<14,18>
D D
D
QSA#[3..0]<14,18>
D
QMA[3..0]<14,18>
M
DA[31..0]<14,18>
C
MDA[30..0]
C C
B B
QSA[3..0]
D
QSA#[3..0]
D
QMA[3..0]
M
DA[31..0]
C
MDA[30..0]
+
MEM_VREF_CA0
+
MEM_VREF_DQ0
C
LKA0<14,18>
C
LKA0#<14,18>
R
R
243_0402_1%
243_0402_1%
DRANK@
DRANK@
DRANK@
DRANK@
0.01U_0402_25V7K
0.01U_0402_25V7K
12
V88
V88
C
C
C
MDA9
C
MDA24
C
MDA10
C
MDA13
C
MDA26
C
MDA22
C
MDA21
C
MDA5
C
MDA8
C
MDA23
C
MDA28
C
MDA4
C
MDA7
C
MDA14
C
MDA12
C
MDA29
C
MDA6
C
MDA30
C
MDA3
C
MDA0
C
MDA1
C
MDA11
C
MDA15
C
MDA25
D
QSA1
D
QSA2
D
QMA1
D
QMA2
D
QSA#1
D
QSA#2
C
MDA20
Z
Q4
12
V77
V77
4
V7
@
V7
@
U
U
M8
REFCA
V
H1
REFDQ
V
N3
0
A
P7
1
A
P3
2
A
N2
3
A
P8
4
A
P2
5
A
R8
6
A
R2
7
A
T8
8
A
R3
9
A
L7
10/AP
A
R7
11
A
N7
12
A
T3
13
A
T7
14
A
M7
15/BA3
A
M2
A0
B
N8
A1
B
M3
A2
B
J7
K
C
7
K
K
C
K9
KE/CKE0
C
K1
DT/ODT0
O
L2
S/CS0
C
3
J
AS
R
3
K
AS
C
3
L
E
W
3
10mA 310mA
F3
QSL
D
C7
QSU
D
E7
ML
D
D3
MU
D
3
G
QSL
D
7
B
QSU
D
2
T
ESET
R
L8
Q/ZQ0
Z
J1
C/ODT1
N
1
L
C/CS1
N
J9
C/CE1
N
L9
CZQ1
N
6-BALL
6-BALL
9
9
SDRAM DDR3
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
K4B1G1646E-HC12_FBGA96
3
V8
@
V8
@
U
Z
Q5
12
U
M8
V
REFCA
H1
V
REFDQ
N3
A
0
P7
A
1
P3
2
A
N2
3
A
P8
4
A
P2
5
A
R8
6
A
R2
A
7
T8
8
A
R3
A
9
L7
A
10/AP
R7
A
11
N7
A
12
T3
A
13
T7
A
14
M7
A
15/BA3
M2
A0
B
N8
A1
B
M3
B
A2
J7
K
C
7
K
K
C
K9
KE/CKE0
C
K1
O
DT/ODT0
L2
S/CS0
C
3
J
AS
R
3
K
AS
C
3
L
E
W
F3
D
QSL
C7
D
QSU
E7
D
ML
D3
D
MU
G
3
D
QSL
7
B
QSU
D
T
2
R
ESET
L8
Z
Q/ZQ0
J1
N
C/ODT1
L
1
N
C/CS1
J9
N
C/CE1
L9
N
CZQ1
6-BALL
6-BALL
9
9
SDRAM DDR3
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
K4B1G1646E-HC12_FBGA96
D
QL0
D
QL1
D
QL2
D
QL3
D
QL4
D
QL5
D
QL6
D
QL7
D
QU0
D
QU1
D
QU2
D
QU3
D
QU4
D
QU5
D
QU6
D
QU7
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
E3
M
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
DA12
M
DA9
M
DA15
M
DA8
M
DA14
M
DA10
M
DA11
M
DA13
M
DA22
M
DA18
M
DA23
M
DA16
M
DA21
M
DA19
M
DA20
M
DA17
+
VRAM_1.5VS
+
VRAM_1.5VS
QL0
D
QL1
D
QL2
D
QL3
D
QL4
D
QL5
D
QL6
D
QL7
D
QU0
D
QU1
D
QU2
D
QU3
D
QU4
D
QU5
D
QU6
D
QU7
D
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
Group1
Group2
+
MEM_VREF_CA0
+
MEM_VREF_DQ0
0.01U_0402_25V7K
0.01U_0402_25V7K
C
C
DRANK@
DRANK@
C
R
R
V78
V78
243_0402_1%
243_0402_1%
DRANK@
DRANK@
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
D
D
D
D
D
D
C
MDA9
MDA24
MDA10
MDA13
MDA26
MDA22
MDA21
MDA5
MDA8
MDA23
MDA28
MDA4
MDA7
MDA14
MDA12
MDA29
MDA6
MDA30
LKA0
LKA0#
MDA3
MDA0
MDA1
MDA11
MDA15
MDA25
QSA0
QSA3
QMA0
QMA3
QSA#0
QSA#3
MDA20
1
V89
V89
2
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
M
DA1
M
DA6
M
DA0
M
DA5
M
DA3
M
DA7
M
DA2
M
DA4
M
DA26
M
DA30
M
DA24
M
DA29
M
DA25
M
DA31
M
DA27
M
DA28
+
VRAM_1.5VS
+
VRAM_1.5VS
2
M
ode E
Address
CMD0
Rank 0
0..31
ODT
CMD1
G
roup0
Group3
CMD2
CMD3
CMD4
CMD5
CMD6
CMD7
CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
C
MD15
CMD16
CS0#
CKE
A9
A6
A3
A0
A8
A12
A1
RAS#
A13
BA1
A14
CAS#
CMD17
CMD18
CMD19
CMD20
RST
A7
CMD22
CMD23
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29
A4
A11
A2
A10
A5
BA2
WE#
BA0
CMD30
1
Rank 1
32..63
ODT
CS1#
CKE
A9
A11
A6
A3
BA1
A0
A
8
A8
A0
A1
RAS#RAS#
A13
BA1 A3
A14
A3
A14
CAS#
ODT
CS0#
CKE
RST
A7CMD21
A4
A6
A5
A11
A2
A1
A10
A5
A4
BA2
WE#
BA0
BA0
BA2
32..630..31
A11
A7A7
BA1
A12A12
A8
A0A12
A2A2
RAS#
A14
A13A13
CAS#CAS#
ODT
CS1#
CKE
RSTRST
A6
A5
A9A9
A1
WE#WE#
A4
A10A10
BA0
BA2
A A
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
012/12/07 2013/12/07
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
ompal Electronics, Inc.
C
C
C
ompal Electronics, Inc.
T
T
T
itle
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
ustom
C
C
C
ustom
ustom
Date: Sheet
Date: Sheet
2
Date: Sheet
ompal Electronics, Inc.
GA_N14x VRAM RANK 1L
V
V
V
GA_N14x VRAM RANK 1L
GA_N14x VRAM RANK 1L
20 56Monday, March 11, 2013
20 56Monday, March 11, 2013
1
20 56Monday, March 11, 2013
0
0
0
o
o
o
f
f
f
.2
.2
.2
Page 21
5
ANK 1[63...32]
R
RAM DDR3 Chips
V
D
QSA[7..4]<14,19>
D
QSA#[7..4]<14,19>
D D
D
QMA[7..4]<14,19>
M
DA[63..32]<14,19>
C
MDA[30..0]
C C
B B
DQSA[7..4]
D
QSA#[7..4]
D
QMA[7..4]
M
DA[63..32]
C
MDA[30..0]
+
MEM_VREF_CA1
+
MEM_VREF_DQ1
C
LKA1<14,19>
C
LKA1#<14,19>
V79
V79
R
R
243_0402_1%
243_0402_1%
DRANK@
DRANK@
DRANK@
DRANK@
0.01U_0402_25V7K
0.01U_0402_25V7K
12
C
C
V90
V90
C
MDA9
C
MDA24
C
MDA10
C
MDA13
C
MDA26
C
MDA22
C
MDA21
C
MDA5
C
MDA8
C
MDA23
C
MDA28
C
MDA4
C
MDA7
C
MDA14
C
MDA12
C
MDA29
C
MDA6
C
MDA30
C
MDA19
C
MDA16
C
MDA17
C
MDA11
C
MDA15
C
MDA25
D
QSA4
D
QSA7
D
QMA4
D
QMA7
D
QSA#4
D
QSA#7
C
MDA20
Z
Q6
12
4
V9
@
V9
@
U
U
M8
REFCA
V
H1
REFDQ
V
N3
0
A
P7
1
A
P3
2
A
N2
3
A
P8
4
A
P2
5
A
R8
6
A
R2
7
A
T8
8
A
R3
9
A
L7
10/AP
A
R7
11
A
N7
12
A
T3
13
A
T7
14
A
M7
15/BA3
A
M2
A0
B
N8
A1
B
M3
A2
B
J7
K
C
7
K
K
C
K9
KE/CKE0
C
K1
DT/ODT0
O
L2
S/CS0
C
3
J
AS
R
3
K
AS
C
3
L
E
W
3
10mA
F3
QSL
D
C7
QSU
D
E7
ML
D
D3
MU
D
3
G
QSL
D
7
B
QSU
D
2
T
ESET
R
L8
Q/ZQ0
Z
J1
C/ODT1
N
1
L
C/CS1
N
J9
C/CE1
N
L9
CZQ1
N
6-BALL
6-BALL
9
9
SDRAM DDR3
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
K4B1G1646E-HC12_FBGA96
3
V10
@
V10
@
U
E3
M
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
DA37
M
DA35
M
DA36
M
DA32
M
DA39
M
DA34
M
DA38
M
DA33
M
DA62
M
DA58
M
DA63
M
DA56
M
DA60
M
DA59
M
DA61
M
DA57
+
VRAM_1.5VS
+
VRAM_1.5VS
QL0
D
QL1
D
QL2
D
QL3
D
QL4
D
QL5
D
QL6
D
QL7
D
QU0
D
QU1
D
QU2
D
QU3
D
QU4
D
QU5
D
QU6
D
QU7
D
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
SSQ
V
Group7
+
MEM_VREF_CA1
+
MEM_VREF_DQ1
0.01U_0402_25V7K
0.01U_0402_25V7K
C
C
DRANK@
DRANK@
V91
V91
1
2
R
R
243_0402_1%
243_0402_1%
DRANK@
DRANK@
C
MDA9
C
MDA24
C
MDA10
C
MDA13
C
MDA26
C
MDA22
C
MDA21
C
MDA5
C
MDA8
C
MDA23
C
MDA28
C
MDA4
C
MDA7
C
MDA14
C
MDA12
C
MDA29
C
MDA6
C
MDA30
C
LKA1
C
LKA1#
C
MDA19
C
MDA16
C
MDA17
C
MDA11
C
MDA15
C
MDA25
D
QSA5
D
QSA6
D
QMA5
D
QMA6
D
QSA#5
D
QSA#6
C
MDA20
12
V80
V80
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
J7
K
K9
K1
L2
J
K
L
F3
C7
E7
D3
G
B
T
L8
Z
Q7
J1
L
J9
L9
U
V
REFCA
V
REFDQ
A
0
A
1
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
A
10/AP
11
A
A
12
A
13
A
14
A
15/BA3
A0
B
A1
B
B
A2
K
C
7
K
C
KE/CKE0
C
O
C
3
R
3
C
3
W
D
D
D
D
3
D
7
D
2
R
Z
Q/ZQ0
N
1
N
N
N
K4B1G1646E-HC12_FBGA96
K4B1G1646E-HC12_FBGA96
DT/ODT0
S/CS0
AS
AS
E
310mA
QSL
QSU
ML
MU
QSL
QSU
ESET
C/ODT1
C/CS1
C/CE1
CZQ1
6-BALL
6-BALL
9
9
SDRAM DDR3
SDRAM DDR3
V
V
V
V
V
V
V
V
V
DQL0
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
QU0
QU1
QU2
QU3
QU4
QU5
QU6
QU7
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SSQ
SSQ
SSQ
SSQ
SSQ
SSQ
SSQ
SSQ
SSQ
E3
F7
QL1
F2
QL2
F8
QL3
H3
QL4
H8
QL5
G2
QL6
H7
QL7
D7
C3
C8
C2
A7
A2
B8
A3
B2
DD
D9
DD
G7
DD
K2
DD
K8
DD
N1
DD
N9
DD
R1
DD
R9
DD
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
SS
B3
SS
E1
SS
G8
SS
J2
SS
J8
SS
M1
SS
M9
SS
P1
SS
P9
SS
T1
SS
T9
SS
B1
B9
D1
D8
E2
E8
F9
G1
G9
M
DA41
M
DA45
M
DA40
M
DA46
M
DA42
M
DA47
M
DA43
M
DA44
M
DA50
M
DA54
M
DA48
M
DA55
M
DA49
M
DA52
M
DA51
M
DA53
+
VRAM_1.5VS
+
VRAM_1.5VS
2
ode E
M
Address
CMD0
Rank 0
0..31
ODT
CMD1
Group5Group4
G
roup6
CMD2
CMD3
CMD4
CMD5
CMD6
CMD7
CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
C
MD15
CMD16
CMD17
CS0#
CKE
A9
A6
A3
A0
A8
A12
A1
RAS#
A13
BA1
A14
CAS#
CMD18
CMD19
CMD20
RST
A7
CMD22
CMD23
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29
A4
A11
A2
A10
A5
BA2
WE#
BA0
CMD30
1
Rank 1
32..63
ODT
CS1#
CKE
A9
A11
A6
A3
A
A8
BA1
0
A8
A0
A1
RAS#RAS#
A13
BA1 A3
A14
A3
A14
CAS#
ODT
CS0#
CKE
RST
A7CMD21
A4
A6
A5
A11
A2
A1
A10
A5
A4
BA2
WE#
BA0
BA0
BA2
32..630..31
A11
A7A7
BA1
A12A12
A8
A0A12
A2A2
RAS#
A14
A13A13
CAS#CAS#
ODT
CS1#
CKE
RSTRST
A6
A5
A9A9
A1
WE#WE#
A4
A10A10
BA0
BA2
A A
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
012/12/07 2013/12/07
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
ompal Electronics, Inc.
C
C
C
ompal Electronics, Inc.
T
itle
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
ustom
C
C
C
ustom
ustom
Date: Sheet
Date: Sheet
2
Date: Sheet
ompal Electronics, Inc.
GA_N14x VRAM RANK 1H
V
V
V
GA_N14x VRAM RANK 1H
GA_N14x VRAM RANK 1H
21 56Monday, March 11, 2013
21 56Monday, March 11, 2013
1
21 56Monday, March 11, 2013
.2
0
0
0
.2
o
o
o
.2
f
f
f
Page 22
A
For eDP Panel
IEDP@
IEDP@
1 2
C
C
890 0.1U_0402_1 0V7K
H
_EDP_AUXP<6>
H
1 1
F
2 2
3 3
_EDP_AUXN<6>
H
_EDP_TXP0<6>
H
_EDP_TXN0<6>
H
_EDP_TXP1<6>
H
_EDP_TXN1<6>
or LVDS 1ch Panel
L
CD_TXOUT0+<28>
L
CD_TXOUT0-<28>
L
CD_TXOUT1+<28>
L
CD_TXOUT1-<28>
L
CD_TXOUT2+<28>
L
CD_TXOUT2-<28>
L
CD_TXCLK+<28>
L
CD_TXCLK-<28>
L
CD_EDID_CLK<28>
L
CD_EDID_DATA<28>
R
eserve for eDP panel potential issue
890 0.1U_0402_1 0V7K
IEDP@
IEDP@
2
1
C
C
891 0.1U_0402_1 0V7K
891 0.1U_0402_1 0V7K
IEDP@
IEDP@
1 2
912 0.1U_0402_1 0V7K
912 0.1U_0402_1 0V7K
C
C
IEDP@
IEDP@
1 2
913 0.1U_0402_1 0V7K
913 0.1U_0402_1 0V7K
C
C
IEDP@
IEDP@
1 2
914 0.1U_0402_1 0V7K
914 0.1U_0402_1 0V7K
C
C
IEDP@
IEDP@
2
1
915 0.1U_0402_1 0V7K
915 0.1U_0402_1 0V7K
C
C
1
LVDS@
LVDS@
262 0_0402_5%
262 0_0402_5%
R
R
1 2
LVDS@
LVDS@
263 0_0402_5%
263 0_0402_5%
R
R
1
LVDS@
LVDS@
R
R
265 0_0402_5%
265 0_0402_5%
1 2
LVDS@
LVDS@
264 0_0402_5%
264 0_0402_5%
R
R
1 2
LVDS@
LVDS@
R
R
300 0_0402_5%
300 0_0402_5%
1
LVDS@
LVDS@
299 0_0402_5%
299 0_0402_5%
R
R
+
3VS
2
2
2
L
VDS_EDID_CLK
L
VDS_EDID_DATA
L
VDS_TXOUT0+
L
VDS_TXOUT0-
L
VDS_TXOUT1+
L
VDS_TXOUT1-
L
VDS_TXOUT0+
L
VDS_TXOUT0-
L
VDS_TXOUT1+
L
VDS_TXOUT1-
L
CD_TXOUT2+
L
CD_TXOUT2-
L
CD_TXCLK+
L
CD_TXCLK-
L
VDS_EDID_CLK
L
VDS_EDID_DATA
B
CAM_EMI@
CAM_EMI@
U
SB20_N11_R
U
SB20_P11_R
1
1
4
4
55
55
L
L
2
2
3
3
WCM-2012-900T_0805
WCM-2012-900T_0805
Reserve fo r EMI requ est
1 2
R
R
267 0_0402_5%
267 0_0402_5%
@TOUCH_EMI@
@TOUCH_EMI@
TOUCH_EMI@
TOUCH_EMI@
U
SB20_P8_R
U
SB20_N8_R
L
VDS colay eDP cable
1
1
4
4
57
57
L
L
1 2
R
R
266 0_0402_5%
266 0_0402_5%
@TOUCH_EMI@
@TOUCH_EMI@
R
eserve for EMI reque st
2
2
3
3
WCM-2012-900T_0805
WCM-2012-900T_0805
pin1-4 Touch function for panel
pin5-10 For Webcam with single or dual MIC
pin11-30 For LVDS or EDP panel
U
SB20_N11 <29>
U
SB20_P11 <29>
U
SB20_P8 <29>
U
SB20_N8 <29>
LVDS
LVDS
J
J
G
G
G
G
G
Conn@
Conn@
C
CD POWER CIRCUIT
L
D
E
eDP&LVDS both 3V power rail
+
3VS
W=60mils
1.5A
+
LCD_VDD_SS
12
C
C
7
7
0.015U_0402_50V7K
0.015U_0402_50V7K
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
0
1
11
1
1
12
2
1
13
3
1
14
4
1
15
5
1
16
6
1
17
7
1
18
8
1
19
9
1
20
0
2
21
1
2
22
2
2
23
3
2
24
4
2
25
5
2
26
6
2
27
7
2
28
8
2
29
9
2
30
0
3
31
ND
32
ND
33
ND
34
ND
35
ND
+
5VS_LVDS_TOUCH
U
SB20_N8_R
U
SB20_P8_R
B
KOFF#
I
NT_MIC_DATA
I
NT_MIC_CLK
U
SB20_P11_R
U
SB20_N11_R
+
3VS_LVDS_CAM
+
LCD_VDD
+
3VS
L
VDS_EDID_CLK
L
VDS_EDID_DATA
L
VDS_TXOUT0-
L
VDS_TXOUT0+
L
VDS_TXOUT1-
L
VDS_TXOUT1+
L
CD_TXOUT2-
L
CD_TXOUT2+
L
CD_TXCLK-
L
CD_TXCLK+
L
ED_PWM
B
KOFF#_R
2
1
Rshort@
Rshort@
389 0_0603_5%
389 0_0603_5%
R
R
+
LCD_INV
I
rush=1.5A
+
LCD_VDD
C
+
LCD_INV
U
U
16
16
5
IN
V
4
S
S
APL3512ABI-TRG_SOT23-5
APL3512ABI-TRG_SOT23-5
L
CD_ENVDD<28>
1 2
Rshort@
Rshort@
390 0_0603_5%
390 0_0603_5%
R
R
Irush=1.5A
PU_EDP_HPD <6>
I
rush=1.5A
6
0mils
2
2
L
L
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
EMI@
EMI@
1
OUT
V
2
ND
G
3
N
E
I
NT_MIC_DATA <39>
I
NT_MIC_CLK <39>
6
0mils
60mils
12
+
LCD_VDD_OUT
2
R
R
112
112
100K_0402_5%
100K_0402_5%
1
+
5VS
20mils
+
+
3VS
1 2
Rshort@
Rshort@
106 0_0805_5%
106 0_0805_5%
R
R
3VS
2
0mils
B
+
+
LCD_VDD
=60mils
W
I rush=1.5A
IEDP@
103 0_0402_5%
103 0_0402_5%
R
R
B
KOFF#_R
4 4
1 2
15 RB751V40_SC76-2
15 RB751V40_SC76-2
D
D
LVDS@
LVDS@
12
113
113
R
R
10K_0402_5%
10K_0402_5%
A
IEDP@
IEDP@
5
17
17
U
U
P
N1
I
4
O
N2
I
G
3
SN74AHC1G08DCKR_SC70-5
SN74AHC1G08DCKR_SC70-5
1 2
147 0_0402_5%
147 0_0402_5%
R
R
LVDS@
LVDS@
2
L
R
R
47K_0402_5%
47K_0402_5%
ED_PWM
131
131
12
1
2
E
C_ENBKL <28,41>
B
KOFF# <41>
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
D
1
17RB751V40_SC76-2D17RB751V40_SC76-2
D
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
Title
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
Date: Sheet
ompal Electronics, Inc.
L
L
L
VDS
VDS
VDS
V
V
V
FKAA
FKAA
FKAA
P
CH_PWM <28>
o
o
o
f
22 56Monday, March 11, 2013
f
22 56Monday, March 11, 2013
f
22 56Monday, March 11, 2013
E
0
0
0
.2
.2
.2
2
1
IEDP@
Page 23
A
1 1
U
MA_CRT_R<28>
U
MA_CRT_G<28>
U
MA_CRT_B<28>
C
C
C
C
RT@
RT@
RT@
RT@
R
R
R
R
139
139
138
138
12
50_0402_1%
50_0402_1%
1
1
2 2
B
1 2
L
L
3 N BQ100505T-800Y_0402
3 N BQ100505T-800Y_0402
CRT_EMI@
CRT_EMI@
1 2
L
L
4 N BQ100505T-800Y_0402
4 N BQ100505T-800Y_0402
CRT_EMI@
CRT_EMI@
1 2
L
L
5 N BQ100505T-800Y_0402
5 N BQ100505T-800Y_0402
CRT_EMI@
CRT_EMI@
RT@
RT@
RT@
C
C
140
140
R
R
1
1
50_0402_1%
50_0402_1%
1
1
2
C
C
238
238
50_0402_1%
50_0402_1%
1
1
2
RT@
C
C
C
C
C
RT@
RT@
1
239
239
C
C
2
.2P_0402_50V8C
.2P_0402_50V8C
2
2
C
RT@
RT@
1
1
C
C
240
240
2
2
.2P_0402_50V8C
.2P_0402_50V8C
.2P_0402_50V8C
.2P_0402_50V8C
2
2
2
2
C
C
RT@
RT@
1
C
C
241
241
2
.2P_0402_50V8C
.2P_0402_50V8C
2
2
C
C
RT_R_L
C
RT_G_L
C
RT_B_L
RT@
RT@
RT@
RT@
C
C
C
C
1
1
242
242
243
243
C
C
C
C
2
2
.2P_0402_50V8C
.2P_0402_50V8C
.2P_0402_50V8C
.2P_0402_50V8C
2
2
2
2
U
SE HDMI POWER
+
HDMI_5V_OUT
D
C
RT CONNECTOR
T
65, T66: for AT E
C
RT_R_L
C
RT_DDC_DAT
C
RT_G_L
H
SYNC
C
RT_B_L
V
SYNC
C
RT_DDC_CLK
T
65 PADT65 PAD
66 PADT66 PAD
T
J
J
CRT
CRT
6
1
1
1
7
1
2
2
8
1
3
3
9
1
4
G
G
4
G
G
1
0
1
5
5
C-H_13-12201513CP
C-H_13-12201513CP
Conn@
Conn@
1
1
E
6
7
CRT@
U
U
49
49
+
HDMI_5V_OUT
+
3VS
+
3VS
U
3 3
4 4
A
MA_CRT_DATA<28>
U
MA_CRT_CLK<28>
U
MA_CRT_VSYNC<28>
U
MA_CRT_HSYNC<28>
B
1
V
CC_SYNC
2
V
CC_VIDEO
7
V
CC_DDC
10
D
DC_IN1
11
D
DC_IN2
13
S
YNC_IN1
15
S
YNC_IN2
6
G
ND
TPD7S019-15DBQR_SSOP16
TPD7S019-15DBQR_SSOP16
S
S
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
V
IDEO1
V
IDEO2
V
IDEO3
D
DC_OUT1
D
DC_OUT2
YNC_OUT1
YNC_OUT2
CRT@
CRT@
8
B
YP
3
4
5
9
12
14
16
C
CRT@
2
1
C
C
15 0.22U_0402_1 6V7K
15 0.22U_0402_1 6V7K
C
RT_R_L
C
RT_G_L
C
RT_B_L
V
SYNC_R
H
SYNC_R
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
4.7K_0402_5%
4.7K_0402_5%
R
R
62
62
CRT@
CRT@
1 2
R
R
63
63
CRT@
CRT@
1
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
R
R
153
153
CRT@
CRT@
22_0402_5%
22_0402_5%
2
22_0402_5%
22_0402_5%
D
D
D
eciphered Date
eciphered Date
eciphered Date
+
HDMI_5V_OUT
2
159
159
R
R
4.7K_0402_5%
4.7K_0402_5%
CRT@
CRT@
1 2
1
V
SYNC
H
SYNC
C
RT_DDC_DAT
C
RT_DDC_CLK
D
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
Title
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
ompal Electronics, Inc.
C
C
C
RT
RT
RT
V
V
V
FKAA
FKAA
FKAA
2
2
2
3 56Monday, March 11, 2013
3 56Monday, March 11, 2013
E
3 56Monday, March 11, 2013
o
o
o
f
f
f
0
0
0
.2
.2
.2
Page 24
A
R
R
PY1
PY1
U
MA_HDMI_CLK
1 8
2 7
3 6
4
2.2K_0804_8P4R_5%
2.2K_0804_8P4R_5%
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
C
C
C
C
C
C
C
C
C
C
C
C
+
3VS
+
HDMI_5V_OUT
1 1
U
MA_HDMI_CLK<28>
U
U
MA_HDMI_DATA<28>
2 2
U
MA_HDMI_CLK-<28>
U
MA_HDMI_CLK+<28>
U
MA_HDMI_TX0-<28>
U
MA_HDMI_TX0+<28>
U
3 3
MA_HDMI_TX1-<28>
U
MA_HDMI_TX1+<28>
MA_HDMI_DATA
U
MA_HDMI_CLK
U
MA_HDMI_DATA
H
DMI_SCLK
5
H
DMI_SDATA
+
3VS
G
G
2
13
D
S
D
S
Y1
Y1
Q
G
G
2
S
S
1 2
Y2 0.1U_0402_10V7K
Y2 0.1U_0402_10V7K
1 2
Y1 0.1U_0402_10V7K
Y1 0.1U_0402_10V7K
1 2
Y5 0.1U_0402_10V7K
Y5 0.1U_0402_10V7K
1 2
Y3 0.1U_0402_10V7K
Y3 0.1U_0402_10V7K
1
Y7 0.1U_0402_10V7K
Y7 0.1U_0402_10V7K
1
Y6 0.1U_0402_10V7K
Y6 0.1U_0402_10V7K
Q
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
13
D
D
Y2
Y2
Q
Q
2
2
B
H
DMI_TXC-
H
DMI_TXC+
H
DMI_TXD0-
H
DMI_TXD0+
H
DMI_TXD1-
H
DMI_TXD1+
H
DMI_SCLK
H
DMI_SDATA
Y1
EMI@
Y1
EMI@
L
L
1
1
4
4
WCM-2012HS-900T_4P
WCM-2012HS-900T_4P
L
L
Y2
EMI@
Y2
EMI@
1
1
4
4
WCM-2012HS-900T_4P
WCM-2012HS-900T_4P
Y3
EMI@
Y3
EMI@
L
L
1
1
4
4
WCM-2012HS-900T_4P
WCM-2012HS-900T_4P
C
O
E# A Y
L
L L
L
H H
H
X Z
+
HDMI_5V_OUT
H
DMI_HPD_U
5
1
Y1
Y1
U
U
P
E#
2
O
Y
A
G
74AHCT1G125GW_SOT353-5
74AHCT1G125GW_SOT353-5
3
H
DMI_HPD
2
2
3
3
2
2
3
3
2
2
3
3
4
1
1K_0402_5%
1K_0402_5%
H
DMI_HPD
Y3
Y3
R
R
2.2K_0402_5%
2.2K_0402_5%
Y1
Y1
R
R
2
12
R
R
Y2
Y2
100K_0402_5%
100K_0402_5%
+
3VS
H
H
DMI_HPD_C
2
C
C
Y4
Y4
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1 2
DMI_HPD <28,30>
D
H
DMI POWER CIRCUIT
V
IN = 5V, IOUT = 0.5A , RDS(ON) TYP=95m ; MAX=115m
Current Limit: TYP=0.8A ; MAX=1A
+
HDMI_5V_OUT
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
1
Y18
Y18
2
+
HDMI_5V_OUT
Y2
U
U
Y2
1
N
UT
O
I
2
ND
G
3
N
LG
E
F
AP2151DWG-7_SOT25-5
AP2151DWG-7_SOT25-5
S
A00006H000
H
DMI Connector
H
DMI_HPD_C
H
DMI_SDATA
H
DMI_SCLK
H
DMI_R_CK-
H
DMI_R_CK+
H
DMI_R_D0-
H
DMI_R_D0+
H
DMI_R_D1-
H
DMI_R_D1+
H
DMI_R_D2-
H
DMI_R_D2+
5
4
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
E
HDMI
HDMI
J
J
P_DET
H
5V
+
DC/CEC_GND
D
DA
S
CL
S
eserved
R
EC
C
K-
C
K_shield
C
K+
C
0-
D
0_shield
D
0+
D
1-
D
1_shield
D
1+
D
2-
D
2_shield
D
2+
D
Conn@
Conn@
+
5VS
ND
G
ND
G
ND
G
ND
G
23
22
21
20
680 +-5% 8P4R
680 +-5% 8P4R
5
8
R
R
PY3
PY3
680 +-5% 8P4R
680 +-5% 8P4R
5
8
PY4
PY4
R
R
2
4
36
27
1
4
36
27
1
Y4
Y4
Q
Q
G
G
D
13
D
D
S
S
2N7002KW_SOT323-3
2N7002KW_SOT323-3
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
Title
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
ompal Electronics, Inc.
H
H
H
DMI Conn.
DMI Conn.
DMI Conn.
V
V
V
FKAA
FKAA
FKAA
E
2
2
o
2
o
o
f
4 56Monday, March 11, 2013
f
4 56Monday, March 11, 2013
f
4 56Monday, March 11, 2013
0
0
0
.2
.2
.2
H
DMI_R_CK+
H
DMI_R_CK-
H
2
1
C
C
Y9 0.1U_0402_10V7K
U
MA_HDMI_TX2-<28>
U
MA_HDMI_TX2+<28>
H
DMI Royalty
4 4
HDMI W/O Logo: RO0000001HM
HDMI W/Logo: RO0000002HM
HDMI W/Logo + HDCP: RO0000003HM
p
lease manually load
this virtual material to 45@ BOM
A
Y9 0.1U_0402_10V7K
1 2
C
C
Y8 0.1U_0402_10V7K
Y8 0.1U_0402_10V7K
ZZ
HDMI45@
ZZ
HDMI45@
Z
Z
RO0000003HM
HDMI W/Logo + HDCP
HDMI W/Logo + HDCP
H
DMI_TXD2-
H
DMI_TXD2+
B
1
1
4
4
WCM-2012HS-900T_4P
WCM-2012HS-900T_4P
2
2
3
3
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
Y4
EMI@
Y4
EMI@
L
L
DMI_R_D0+
H
DMI_R_D0-
H
DMI_R_D2+
H
DMI_R_D2-
H
DMI_R_D1+
H
DMI_R_D1-
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
+
5VS
Page 25
5
SP@
MOS Setting, near DDR Door
C
1 2
H23
H23
R
+
RTCVCC
D D
P
+
RTCVCC
+
3VS
C C
B B
R
20K_0402_5%
20K_0402_5%
iME Setting.
H24
H24
R
R
20K_0402_5%
20K_0402_5%
I
ntegrated SUS 1.05V VRM Enable
CH_INTVRMEN
1 2
H12
H12
R
R
1 2
H33
H33
R
R
@
@
1 2
R
R
H36 1K_0402_5%
H36 1K_0402_5%
+
RTCVCC
3
1
C
C
H8
H8
0.1U_0402_10V7K
0.1U_0402_10V7K
2
A
Z_BITCLK_HD<39>
A
Z_SYNC_HD<39>
A
Z_RST_HD#<39>
A
Z_SDOUT_HD<39>
HDA_SDO
M
E debug mode,
this signal has a weak internal pull down
Low = Disable (default)
*
High = Enable (flash descriptor security overide)
HDA_SYNC
T
his signal has a weak internal pull down
*
H=>On Die PLL is supplied by 1.5V
L=>On Die PLL is supplied by 1.8V
Need to pull high for Chief River Mobile platform
A
Z_SYNC_R
1M_0402_5%
1M_0402_5%
PCH_RTCRST#
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
P
CH_SRTCRST#
1U_0402_6.3V6K
1U_0402_6.3V6K
H
igh - Enable Internal VRs
(must be always pulled high)
S
2
H56
H56
1 2
M_INTRUDER#
P
CH_INTVRMEN
P
CH_SPKR
+
RTCBATT
H1
H1
D
D
BAS40-04_SOT23-3
BAS40-04_SOT23-3
+
3VL
A
Z_BITCLK_HD
+
5VS
G
G
2
Q
Q
D
S
D
S
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
1 8
2
3 6
4 5
H1
H1
13
1M_0402_5%
1M_0402_5%
330K_0402_5%
330K_0402_5%
1
R
R
SP@
J
J
CMOS
CMOS
1 2
1 2
H4
H4
C
C
SP@
SP@
J
J
ME
ME
2
1
1 2
H5
H5
C
C
P
CH_SPKR
High = Enabled "No Reboot Mode"
*
Low = Disabled (Default)
R
R
PH2
PH2
A
Z_BITCLK
7
A
Z_SYNC_R
A
Z_RST#
A
+
3VALW_PCH
2
1
Z_SDOUT
H55
H55
R
R
1K_0402_5%
1K_0402_5%
A
Z_SYNC
33_8P4R_5%
33_8P4R_5%
P
CH_RTCX1_R<35>
Placement near to YH 1
4
H26
GCLK@
H26
GCLK@
R
R
1 2
0_0402_5%
0_0402_5%
PCH_RTCX1
H2 15P_0402_50V8J
H2 15P_0402_50V8J
C
C
NOGCLK@
NOGCLK@
32.768KHZ_12.5P_1TJF125DP1A000D
32.768KHZ_12.5P_1TJF125DP1A000D
H3 15P_0402_50V8J
H3 15P_0402_50V8J
C
C
P
WRME_CTRL<41>
C
hange Net name due to
this function is high
active
S
PI ROM for BIOS & ME (4MByte )
1 2
P
CH_SPIDO
Rshort@
Rshort@
H68
H68
R
R
0_0402_5%
0_0402_5%
+
12
H1
H1
Y
Y
12
P
CH_SPICS0#
P
CH_SPI0_DO
3VALW_PCH
NOGCLK@
NOGCLK@
2
H2
H2
R
R
1
NOGCLK@
NOGCLK@
P
CH_SPKR<39>
A
Z_SDIN0_HD<39>
1 2
Rshort@
Rshort@
H25 0_0402_5%
H25 0_0402_5%
R
R
1
2
3
4
4MB ROM P/N:
SA00003K800
SA00004LI00
P
P
12
P
P
NOGCLK@
NOGCLK@
S
10M_0402_5%
10M_0402_5%
P
A
A
P
A
A
A
P
70 PADT70 PAD
T
P
67 PADT67 PAD
T
P
68 PADT68 PAD
T
P
T
69 PADT69 PAD
P
P
P
P
P
U
U
H3
H3
V
C
S#
CC
H
D
O
OLD#
C
W
P#
LK
D
G
ND
W25Q32BVSSIG_SO8
W25Q32BVSSIG_SO8
I
P
lease place UH3 & UH4 close to UH1 PCH,
3
CH_RTCX1
CH_RTCX2
CH_RTCRST#
CH_SRTCRST#
M_INTRUDER#
CH_INTVRMEN
Z_BITCLK
Z_SYNC
CH_SPKR
Z_RST#
Z_SDIN0_HD
Z_SDOUT
CH_JTAG_TCK
CH_JTAG_TMS
CH_JTAG_TDI
CH_JTAG_TDO
CH_SPICLK
CH_SPICS0#
CH_SPICS1#
CH_SPIDI
CH_SPIDO
+
3VALW_PCH
8
7
6
P
5
P
2
H1A
H1A
U
U
A20
TCX1
R
C20
R
TCX2
D20
R
TCRST#
G22
S
RTCRST#
K22
NTRUDER#
I
C17
NTVRMEN
I
N34
H
DA_BCLK
L34
H
DA_SYNC
T10
S
PKR
K34
H
DA_RST#
E34
H
DA_SDIN0
G34
H
DA_SDIN1
C34
H
DA_SDIN2
A34
H
DA_SDIN3
A36
H
DA_SDO
C36
H
DA_DOCK_EN# / GPIO33
N32
H
DA_DOCK_RST# / GPIO13
J3
J
TAG_TCK
H7
J
TAG_TMS
K5
J
TAG_TDI
H1
J
TAG_TDO
T3
S
PI_CLK
Y14
S
PI_CS0#
T1
S
PI_CS1#
V4
S
PI_MOSI
U3
S
PI_MISO
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
HM76R3@
HM76R3@
0
206: Delete 0.1uF 0206: Delete 0.1uF
H66 0_0402_5%
H66 0_0402_5%
R
R
CH_SPI0_CLK
CH_SPI0_DI
1 2
1
H67 0_0402_5%
H67 0_0402_5%
R
R
Rshort@
Rshort@
Rshort@
Rshort@
INT.PH 20K
INT.PH 20K
INT.PH 20K
INT.PH 20K
I
NT.PD 20K
INT.PD 20K
INT.PD 20K
INT.PD 20K
INT.PD 20K
INT.PD 20K
INT.PD 20K
INT.PD 20K
INT.PH 20K
INT.PH 20K
TAG
TAG
J
J
INT.PD 20K
INT.PH 20K
P
CH_SPICLK
2
P
CH_SPIDI
PC
PC
L
L
INT.PH 20K
INT.PH 20K
TC
TC
R
R
HDA
HDA
I
I
SATA
SATA
PI
PI
S
S
S
S
INT.PH 20K
F
F
F
F
F
WH4 / LFRAME#
L
DRQ1# / GPIO23
ATA 6G
ATA 6G
S
S
S
S
S
ATA3RCOMPO
S
S
ATA0GP / GPIO21
ATA1GP / GPIO19
P
CH_SPIDO
WH0 / LAD0
WH1 / LAD1
WH2 / LAD2
WH3 / LAD3
L
DRQ0#
S
ERIRQ
S
ATA0RXN
S
ATA0RXP
S
ATA0TXN
S
ATA0TXP
S
ATA1RXN
S
ATA1RXP
S
ATA1TXN
S
ATA1TXP
S
ATA2RXN
S
ATA2RXP
S
ATA2TXN
S
ATA2TXP
S
ATA3RXN
S
ATA3RXP
S
ATA3TXN
S
ATA3TXP
S
ATA4RXN
S
ATA4RXP
S
ATA4TXN
S
ATA4TXP
S
ATA5RXN
S
ATA5RXP
S
ATA5TXN
S
ATA5TXP
ATAICOMPO
ATAICOMPI
ATA3COMPI
ATA3RBIAS
S
ATALED#
C38
A38
B37
C37
D36
E36
K36
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
AH1
P3
V14
P1
H269
R
1
0_0402_5%
0_0402_5%
L
PC_AD0
L
PC_AD1
L
PC_AD2
L
PC_AD3
L
PC_FRAME#
S
ERIRQ
S
ATA_PRX_C_DTX_N0
S
ATA_PRX_C_DTX_P0
S
ATA_PTX_DRX_N0
S
ATA_PTX_DRX_P0
S
ATA_PRX_C_DTX_N2
S
ATA_PRX_C_DTX_P2
S
ATA_PTX_DRX_N2
S
ATA_PTX_DRX_P2
S
ATAICOMP
S
ATA3_COMP
R
BIAS_SATA3
S
ATA_LED#
P
CH_GPIO21
P
CH_GPIO19
P
CH_SPICS1#
@RH269
@
2
P
CH_SPI1_DO
+
3VALW_PCH
1 2
H43 37.4_0402_1%
H43 37.4_0402_1%
R
R
1 2
H48 49.9_0402_1%
H48 49.9_0402_1%
R
R
1 2
H41 750_0402_1%
H41 750_0402_1%
R
R
P
B
OOT BIOS Strap Bit 0
S
PI ROM (2MByte )
H4
H4
U
U
1
S#
C
2
O
S
3
P#
W
4
ND
G
MX25L1606EM2I-12G_SO8
MX25L1606EM2I-12G_SO8
L
PC_AD0 <41>
L
PC_AD1 <41>
L
PC_AD2 <41>
L
PC_AD3 <41>
L
PC_FRAME# <41>
S
ERIRQ <41>
S
ATA_PRX_C_DTX_N0 <34>
S
ATA_PRX_C_DTX_P0 <34>
S
ATA_PTX_DRX_N0 <34>
S
ATA_PTX_DRX_P0 <34>
S
ATA_PRX_C_DTX_N2 <34>
S
ATA_PRX_C_DTX_P2 <34>
S
ATA_PTX_DRX_N2 <34>
S
ATA_PTX_DRX_P2 <34>
+
1.05VS_PCH
+
1.05VS_PCH
CH_GPIO19 <29>
+
@
@
8
CC
V
7
OLD#
H
6
P
CH_SPI1_CLK
CLK
S
5
P
CH_SPI1_DI
I
S
O
S
ERIRQ
P
CH_GPIO21
P
CH_GPIO19
S
ATA_LED#
3VALW_PCH
H
DD
2MB ROM P/N:
SA000041N00
SA00003FO10
1
DD
PH1
PH1
R
R
1
2 7
3 6
4
10K_0804_8P4R_5%
10K_0804_8P4R_5%
H267 0 _0402_5%
H267 0 _0402_5%
R
R
2
1
1 2
@
@
H271 0 _0402_5%@RH271 0 _0402_5%@
R
+
8
5
P
CH_SPICLK
P
CH_SPIDI
3VS
please place RH66, RH67, RH68 near UH3
A A
PH9
PH9
R
R
E
C_SDIO<41>
E
C_CS0#<41>
E
C_SCK<41>
E
C_SDI<41>
1 8
2
3 6
4 5
33_8P4R_5%
33_8P4R_5%
885@
885@
7
P
CH_SPI0_DO
P
CH_SPICS0#
P
CH_SPI0_CLK
P
CH_SPI0_DI
Reserve for NPCE885N EC
5
4
Please place RH267 near RH66, Please place RH271 near RH67,
Please place RH269 near RH68.
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
012/12/07 2013/12/07
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
2
ompal Electronics, Inc.
C
C
C
ompal Electronics, Inc.
T
T
T
itle
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
ustom
C
C
C
ustom
ustom
Date: Sheet
Date: Sheet
Date: Sheet
ompal Electronics, Inc.
CH_HDA/JTAG/SATA/SPI/LPC
P
P
P
CH_HDA/JTAG/SATA/SPI/LPC
CH_HDA/JTAG/SATA/SPI/LPC
FKAA
V
V
V
FKAA
FKAA
25 56Monday, March 11, 2013
25 56Monday, March 11, 2013
25 56Monday, March 11, 2013
1
o
o
o
f
f
f
.2
0
0
0
.2
.2
Page 26
5
CIE_PRX_C_LANTX_N1
P
CIE_PRX_C_LANTX_N1<36>
P
L
AN
WLAN
D D
+
3VS
I
ntel Spec:
PCIECLK_RQ0# is suspend well,
but we pull high to +3VS
for LAN en/disable function
+
3VALW_PCH
10K_0804_8P4R_5%
10K_0804_8P4R_5%
C C
CIE_PRX_C_LANTX_P1<36>
P
CIE_PTX_C_LANRX_N1<36>
P
CIE_PTX_C_LANRX_P1<36>
P
CIE_PRX_WLANTX_N 2<35>
P
CIE_PRX_WLANTX_P 2<35>
P
CIE_PTX_C_WLANRX _N2<35>
P
CIE_PTX_C_WLANRX _P2<35>
1 2
H104 10K_0402_5%
H104 10K_0402_5%
R
R
H95 10K_0 402_5%
H95 10K_0 402_5%
R
R
2
1
R
R
PH10
PH10
18
7
2
36
45
C
LKREQ_WLAN#
C
LKREQ_LAN#
R
I#
L
VDS_SEL
P
CH_GPIO28
P
ASSWORD_CLEAR#
LAN
WLAN
+
3VALW_PCH
B B
+
3VALW_PCH
A A
R
R
PH6
PH6
1 8
2 7
3 6
4 5
10K_0804_8P4R_5%
10K_0804_8P4R_5%
2
1
LVDS@
LVDS@
H119 10K_0402_5%
H119 10K_0402_5%
R
R
1 2
IEDP@
IEDP@
R
R
H276 10K_0402_5%
H276 10K_0402_5%
L
VDS_SEL
LVDS_SEL
Channel
Single
(Default)
5
E
C_SWI#
L
AN_EN
P
CH_SUSPWRDN #_R
U
SB_CHG_OC#
P
ANEL_SEL
P
ANEL_SEL
H L
12
H13 0.1U_0402_10V7K
H13 0.1U_0402_10V7K
C
C
12
C
C
H11 0.1U_0402_10V7K
H11 0.1U_0402_10V7K
2
1
C
C
H14 0.1U_0402_10V7K
H14 0.1U_0402_10V7K
2
1
C
C
H17 0.1U_0402_10V7K
H17 0.1U_0402_10V7K
R
I# <27>
P
CH_GPIO28 <30>
C
LK_LAN#<36>
C
LK_LAN<36>
C
LKREQ_LAN#<36>
C
LK_WLAN#<35>
C
LK_WLAN<35>
C
LKREQ_WLAN#<35>
E
C_SWI# <27,36>
P
CH_SUSPWRDN #_R <27>
U
SB_CHG_OC# <29,38,41>
Note: place in DDR area
Dual
P
PCIE_PRX_C_LANTX_P1
P
CIE_PTX_LANRX_N1
P
CIE_PTX_LANRX_P1
P
CIE_PRX_WLANTX_N 2
P
CIE_PRX_WLANTX_P 2
P
CIE_PTX_WLANRX_N 2
P
CIE_PTX_WLANRX_P 2
C
LK_LAN#
C
LK_LAN
C
LKREQ_LAN#
C
LK_WLAN#
C
LK_WLAN
C
LKREQ_WLAN#
P
ASSWORD_CLEAR#
1
PW
PW
J
J
SP@
SP@
2
L
VDS_SEL
P
ANEL_SEL
P
ANEL_SEL
PANEL_SEL
Channel LVDS
4
U
U
BG34
ERN1
P
BJ34
ERP1
P
AV32
ETN1
P
AU32
ETP1
P
BE34
ERN2
P
BF34
ERP2
P
BB32
ETN2
P
AY32
ETP2
P
BG36
ERN3
P
BJ36
ERP3
P
AV34
ETN3
P
AU34
ETP3
P
BF36
ERN4
P
BE36
ERP4
P
AY34
ETN4
P
BB34
ETP4
P
BG37
ERN5
P
BH37
ERP5
P
AY36
ETN5
P
BB36
ETP5
P
BJ38
ERN6
P
BG38
ERP6
P
AU36
ETN6
P
AV36
ETP6
P
BG40
ERN7
P
BJ40
ERP7
P
AY40
ETN7
P
BB40
ETP7
P
BE38
ERN8
P
BC38
ERP8
P
AW38
ETN8
P
AY38
ETP8
P
Y40
C
Y39
C
J2
CIECLKRQ0# / GPIO73
P
AB49
C
AB47
C
M1
CIECLKRQ1# / GPIO18
P
AA48
C
AA47
C
V10
CIECLKRQ2# / GPIO20
P
Y37
C
Y36
C
A8
CIECLKRQ3# / GPIO25
P
Y43
C
Y45
C
L12
P
CIECLKRQ4# / GPIO26
V45
C
V46
C
L14
P
CIECLKRQ5# / GPIO44
AB42
C
AB40
C
E6
P
EG_B_CLKRQ# / GPIO56
V40
C
V42
C
T13
P
CIECLKRQ6# / GPIO45
V38
C
V37
C
K12
P
CIECLKRQ7# / GPIO46
AK14
C
AK13
C
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
HM76R3@
HM76R3@
H L
EDP
4
H1B
H1B
LKOUT_PCIE0N
LKOUT_PCIE0P
LKOUT_PCIE1N
LKOUT_PCIE1P
LKOUT_PCIE2N
LKOUT_PCIE2P
LKOUT_PCIE3N
LKOUT_PCIE3P
LKOUT_PCIE4N
LKOUT_PCIE4P
LKOUT_PCIE5N
LKOUT_PCIE5P
LKOUT_PEG_B_N
LKOUT_PEG_B_P
LKOUT_PCIE6N
LKOUT_PCIE6P
LKOUT_PCIE7N
LKOUT_PCIE7P
LKOUT_ITPXDP_N
LKOUT_ITPXDP_P
MBUSController
MBUSController
S
S
S
CI-E*
CI-E*
P
P
LOCKS
LOCKS
C
C
INT. PH 20K
INT. PH 20K
3
E12
CH_SMBALERT#
MBALERT# / GPIO11
S
MBCLK
S
S
MBDATA
S
ML0ALERT# / GPIO60
S
ML0CLK
S
ML0DATA
ML1ALERT# / PCHHOT# / GPIO74
S
ML1CLK / GPIO58
S
ML1DATA / GPIO75
C
L_CLK1
C
L_DATA1
Link
Link
P
LEX CLOCKS
LEX CLOCKS
F
F
C
L_RST1#
EG_A_CLKRQ# / GPIO47
LKOUT_PEG_A_N
C
LKOUT_PEG_A_P
C
C
LKOUT_DMI_N
C
LKOUT_DMI_P
C
LKOUT_DP_N
C
LKOUT_DP_P
LKIN_DMI_N
C
LKIN_DMI_P
C
LKIN_GND1_N
C
LKIN_GND1_P
C
LKIN_DOT_96N
C
LKIN_DOT_96P
C
LKIN_SATA_N
C
LKIN_SATA_P
C
EFCLK14IN
R
LKIN_PCILOOPBACK
C
TAL25_IN
X
TAL25_OUT
X
X
CLK_RCOMP
INT. PD 20K
C
LKOUTFLEX0 / GPIO64
INT. PD 20K
C
LKOUTFLEX1 / GPIO65
INT. PD 20K
C
LKOUTFLEX2 / GPIO66
INT. PD 20K
C
LKOUTFLEX3 / GPIO67
P
H14
P
CH_SMBCLK
C9
P
CH_SMBDATA
A12
D
RAMRST_CNTRL_PCH
C8
P
CH_SMLCLK0
G12
P
CH_SMLDATA0
C13
L
AN_EN
E14
P
CH_SMLCLK1
M16
P
CH_SMLDATA1
M7
C
ontrol Link only for support Intel IAMT.
T11
P10
M10
C
LK_REQ_VGA#
AB37
C
LK_PCIE_VGA#
AB38
C
LK_PCIE_VGA
AV22
AU22
AM12
AM13
BF18
P
CH_CLK_DMI#
BE18
P
CH_CLK_DMI
BJ30
C
LKIN_GND1#
BG30
C
LKIN_GND1
G24
C
LK_DOT#
E24
C
LK_DOT
AK7
C
LK_SATA#
AK5
C
LK_SATA
K45
C
LK_14M_PCH
H45
C
LK_PCILOOP
V47
P
CH_X1
V49
P
CH_X2
X
CLK_RCOMP
R
R
H38 0_0402_5%
H38 0_0402_5%
C
LK_FLEX0
C
LK_FLEX1
C
LK_FLEX2
D
GPU_PRSNT#
GPU_PRSNT#
1 2
Rshort@
Rshort@
Y47
K43
F47
H47
K49
D
DGPU_PRSNT#
M/B SKU UMA
ecurity Classification
ecurity Classification
S
S
S
ecurity Classification
ssued Date
ssued Date
I
I
I
ssued Date
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
012/12/07 2013/12/07
012/12/07 2013/12/07
2
2
2
012/12/07 2013/12/07
P
CH_SMBALERT# <27>
D
RAMRST_CNTRL_PCH < 7,9>
L
AN_EN <36>
C
LK_REQ_VGA# <13>
C
LK_PCIE_VGA# <13>
C
LK_PCIE_VGA <13>
C
LK_CPU_DMI# <5>
C
LK_CPU_DMI <5>
C
LK_CPU_EDP# <5>
C
LK_CPU_EDP <5>
C
LK_PCILOOP <29>
X
CLK_RCOMP_R
72 PADT72 PAD
T
74 PADT74 PAD
T
73 PADT73 PAD
T
1
R
R
H261 10K_0402_5%
H261 10K_0402_5%
H L
DIS/OPT
ompal Secret Data
ompal Secret Data
C
C
C
ompal Secret Data
eciphered Date
eciphered Date
D
D
D
eciphered Date
F
rom Clock Gen.
R
R
H115
H115
1 2
90.9_0402_1%
90.9_0402_1%
2
+
3VALW_PCH
R
R
2.2K_0804_8P4R_5%
2.2K_0804_8P4R_5%
VGA
120 MHz for eDP
+
1.05VS_VCCDIFFCLKN
2
C
ompal common design SW request to
add DGPU_Present on this GPIO67
2
PH5
PH5
45
P
CH_SMBDATA
36
P
CH_SMBCLK
27
P
CH_SMLDATA1
18
P
CH_SMLCLK1
27P_0402_50V8J
27P_0402_50V8J
NOGCLK@
NOGCLK@
1
H102 4 .7K_0402_5%
H102 4 .7K_0402_5%
R
R
5
H103 4 .7K_0402_5%
R
R
4
+
3VS
4
2
12
12
12
PH3
PH3
6
PH4
PH4
6
@EMI@
@EMI@
1
C
C
H9 10P _0402_50V8J
H9 10P _0402_50V8J
H103 4 .7K_0402_5%
P
M_SMBDATA <11,12,35,42>
P
E
C_SMB_DA2 <13,34,41>
E
C_SMB_CK2 <13,34,41>
N
eed to check dG PU
2
P
CH_X1
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
Q
Q
H4A
H4A
6
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
D
RAMRST_CNTRL_PCH
P
CH_SMLCLK0
P
CH_SMLDATA0
C
LK_REQ_VGA#
P
CH_CLK_DMI
P
CH_CLK_DMI#
C
LKIN_GND1#
C
LKIN_GND1
C
LK_DOT#
C
LK_DOT
C
LK_SATA#
C
LK_SATA
C
LK_14M_PCH
C
LK_PCILOOP
R
R
H70 10_0402_5%
H70 10_0402_5%
P
CH_X1_R<35>
H3B
H3B
Q
Q
3
2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
H3A
H3A
Q
Q
6 1
5
H4B
H4B
Q
Q
3
2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
1
H76 1K_04 02_5%
H76 1K_04 02_5%
R
R
R
R
H73 2.2K_0402_ 5%
H73 2.2K_0402_ 5%
H77 2.2K_0402_ 5%
H77 2.2K_0402_ 5%
R
R
H89 10K_0 402_5%
H89 10K_0 402_5%
R
R
1 8
2 7
3
4 5
1 8
2 7
3
4 5
1 2
H87 10K_0 402_5%
H87 10K_0 402_5%
R
R
@EMI@
@EMI@
1 2
R
R
1 2
0_0402_5%
0_0402_5%
GCLK@
GCLK@
1
R
R
10K_0804_8P4R_5%
10K_0804_8P4R_5%
R
R
10K_0804_8P4R_5%
10K_0804_8P4R_5%
H37
H37
Placement near to YH 2
NOGCLK@
NOGCLK@
2
H117 1M_0402_5%
H117 1M_0402_5%
R
R
Y
Y
1
P
CH_X1
1
1
C
C
H26
H26
2
itle
T
T
Title
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
ustom
ustom
C
C
C
ustom
Date: Sheet
Date: Sheet
Date: Sheet
1
H2
H2
25MHZ_20PF_7V25000016NOGCLK@
25MHZ_20PF_7V25000016NOGCLK@
ND
G
2
C
C
C
P
P
P
V
V
V
3
P
CH_X2
3
ND
G
4
ompal Electronics, Inc.
ompal Electronics, Inc.
ompal Electronics, Inc.
CH_PCI-E/SMBUS/CLK
CH_PCI-E/SMBUS/CLK
CH_PCI-E/SMBUS/CLK
FKAA
FKAA
FKAA
1
1
2
+
3VS
M_SMBCLK <11,12,35,42>
+
3VALW_PCH
+
3VALW_PCH
C
C
H27
H27
27P_0402_50V8J
27P_0402_50V8J
NOGCLK@
NOGCLK@
26 56Monday, March 11, 2013
f
26 56Monday, March 11, 2013
o
o
o
f
26 56Monday, March 11, 2013
f
.2
.2
0
0
0
.2
Page 27
5
D
+
3VALW_PCH
D D
C C
S
tuff R137 if EC does not want to
involve in the handshake mechanism
for the DeepSX state entry and exit
B B
PH7
PH7
R
R
1 8
2 7
3 6
4 5
10K_0804_8P4R_5%
10K_0804_8P4R_5%
R
R
PH17
PH17
R
R
1 8
2 7
3 6
4
10K_0804_8P4R_5%
10K_0804_8P4R_5%
S
USACK#_R
P
CH_LOW_BAT#
S
LP_CHG_CB0
P
CH_SMBALERT#
E
C_SMI#
12
H163 10K_0402_5%
H163 10K_0402_5%
P
M_PWROK
P
CH_GPIO32
P
CH_GPIO37
5
O
PTIMUS_EN#
12
P
CH_SUSPWRDN #_R
@
@
H282 0 _0402_5%
H282 0 _0402_5%
R
R
P
CH_RSMRST#
S
LP_CHG_CB0 <29,38>
P
CH_SMBALERT# <26>
E
C_SMI# <30,41>
P
CH_GPIO37 <30>
O
PTIMUS_EN# <30>
Reserve this signal to EC by SW demand
2011/10/18a
S
P
CH_SUSPWRDN #_R<26>
P
CH_SUSPWRDN #<41>
+
3VALW_PCH
A
CIN<41,46>
R
eserve this signal to EC by SW demand
2011/10/18a
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
+
1.05VS_PCH
USACK#<41>
+
3VS
V
GATE<41,51>
D
RAMPWROK<5>
P
CH_RSMRST#<41>
P
BTN_OUT#<41>
1
H161 3 30K_0402_5%
H161 3 30K_0402_5%
R
R
RB751V40_SC76-2
RB751V40_SC76-2
2
1 2
MI_CTX_PRX_N0<6>
MI_CTX_PRX_N1<6>
MI_CTX_PRX_N2<6>
MI_CTX_PRX_N3<6>
MI_CTX_PRX_P0<6>
MI_CTX_PRX_P1<6>
MI_CTX_PRX_P2<6>
MI_CTX_PRX_P3<6>
MI_PTX_CRX_N0<6>
MI_PTX_CRX_N1<6>
MI_PTX_CRX_N2<6>
MI_PTX_CRX_N3<6>
MI_PTX_CRX_P0<6>
MI_PTX_CRX_P1<6>
MI_PTX_CRX_P2<6>
MI_PTX_CRX_P3<6>
1 2
H126 4 9.9_0402_1%
H126 4 9.9_0402_1%
R
R
1 2
H127 7 50_0402_1%
H127 7 50_0402_1%
R
R
1
H47 1K_0402_5%
H47 1K_0402_5%
R
R
P
M_PWROK<41>
1 2
H132 0_0402_5%
H132 0_0402_5%
R
R
H2
H2
D
D
4
1
@
@
D
MI_COMP
R
BIAS_CPY
2
@
@
H133 0_0402_5%
H133 0_0402_5%
R
R
2
P
CH_SUSPWRDN #_R
R
I#<26>
S
USACK#_R
X
DP_DBRESET#
P
M_PWROK
D
RAMPWROK
P
CH_RSMRST#
P
BTN_OUT#
P
CH_ACIN
P
CH_LOW_BAT#
R
I#
U
U
H1C
H1C
BC24
D
MI0RXN
BE20
D
MI1RXN
BG18
D
MI2RXN
BG20
D
MI3RXN
BE24
D
MI0RXP
BC20
D
MI1RXP
BJ18
D
MI2RXP
BJ20
MI3RXP
D
AW24
MI0TXN
D
AW20
MI1TXN
D
BB18
MI2TXN
D
AV18
MI3TXN
D
AY24
MI0TXP
D
AY20
MI1TXP
D
AY18
MI2TXP
D
AU18
MI3TXP
D
BJ24
MI_ZCOMP
D
BG25
MI_IRCOMP
D
BH21
MI2RBIAS
D
C12
INT.PH 20K
USACK#
S
K3
YS_RESET#
S
P12
YS_PWROK
S
L22
WROK
P
L10
PWROK
A
B13
RAMPWROK
D
C21
SMRST#
R
K16
USWARN#/SUSPW RDNACK/GPIO30
S
E20
H20
E10
A10
I
NT.PH 20K
WRBTN#
P
CPRESENT / GPIO31
A
ATLOW# / GPIO72
B
I#
R
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
HM76R3@
HM76R3@
3
BJ14
DI_RXN0
F
AY14
DI_RXN1
F
BE14
DI_RXN2
F
BH13
DI_RXN3
F
BC12
DI_RXN4
F
BJ12
DI_RXN5
F
BG10
DI_RXN6
F
BG9
DI_RXN7
F
BG14
DI_RXP0
F
BB14
DI_RXP1
F
BF14
DI_RXP2
F
BG13
DI_RXP3
F
BE12
DI_RXP4
F
BG12
DI_RXP5
F
DI_RXP6
F
DI_RXP7
F
DI_INT
F
DI_FSYNC0
DI_FSYNC1
DI_LSYNC0
DI_LSYNC1
SWVRMEN
PWROK
D
AKE#
W
LP_S4#
S
LP_S3#
S
LP_A#
S
LP_SUS#
S
MSYNCH
P
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
DI
DI
DMIF
DMIF
F
F
F
F
D
LKRUN# / GPIO32
C
US_STAT# / GPIO61
S
USCLK / GPIO62
S
LP_S5# / GPIO63
S
ystem Power Management
ystem Power Management
S
S
INT.PD 20K
INT.PH 20K
LP_LAN# / GPIO29
S
D
SWVREN
P
CH_DPWROK
E
C_SWI#
P
CH_GPIO32
S
US_STAT#
P
M_SLP_S5#
P
M_SLP_S4#
P
M_SLP_S3#
P
M_SLP_A#
P
M_SLP_SUS#
H
_PM_SYNC
76 PADT76 PAD
T
77 PADT77 PAD
T
78 PADT78 PAD
T
F
DI_CTX_PRX_N0 <6>
F
DI_CTX_PRX_N1 <6>
F
DI_CTX_PRX_N2 <6>
F
DI_CTX_PRX_N3 <6>
F
DI_CTX_PRX_N4 <6>
F
DI_CTX_PRX_N5 <6>
F
DI_CTX_PRX_N6 <6>
F
DI_CTX_PRX_N7 <6>
F
DI_CTX_PRX_P0 <6>
F
DI_CTX_PRX_P1 <6>
F
DI_CTX_PRX_P2 <6>
F
DI_CTX_PRX_P3 <6>
F
DI_CTX_PRX_P4 <6>
F
DI_CTX_PRX_P5 <6>
F
DI_CTX_PRX_P6 <6>
F
DI_CTX_PRX_P7 <6>
F
DI_INT <6>
F
DI_FSYNC0 <6>
F
DI_FSYNC1 <6>
F
DI_LSYNC0 <6>
F
DI_LSYNC1 <6>
E
C_SWI# <26,36>
32.768 KHz
C
LK_EC <41>
P
M_SLP_S5# <41>
P
M_SLP_S4# <41>
P
M_SLP_S3# <41>
H
_PM_SYNC <5>
2
H128 0_0402_5%
H128 0_0402_5%
R
R
P
CH_DPWROK
1 2
Rshort@
Rshort@
1
P
CH_RSMRST#
Do not support DeepSX state
+
RTCVCC
D
SWVREN
H150 330K_0402_5%
H150 330K_0402_5%
R
R
12
DSWVREN must be always pulled high to +RTCVCC
D
SWVREN - Internal Deep Sleep 1.05V regulator
：：：：
E
H
nable
*
：：：：
D
L
isable
Follow EC check list demand,
but don't implement CLKRUN# this fuction
H5
H5
D
D
12
P
P
M_PWROK
RB751V40_SC76-2
RB751V40_SC76-2
D
D
P
OK<41,47>
A A
5
1
RB751V40_SC76-2
RB751V40_SC76-2
4
P
CH_RSMRST#
CH_RSMRST#
H6
H6
2
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
T
itle
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
2
Date: Sheet
ompal Electronics, Inc.
P
P
P
CH_DMI/FDI/PM
CH_DMI/FDI/PM
CH_DMI/FDI/PM
V
V
V
FKAA
FKAA
FKAA
1
0
0
0
.2
.2
o
o
o
27 56Monday, March 11, 2013
27 56Monday, March 11, 2013
27 56Monday, March 11, 2013
.2
f
f
f
Page 28
5
2
1
H125 1 00K_0402_5%
H125 1 00K_0402_5%
R
R
D D
+
3VS
R
R
1 8
2 7
3
4 5
2.2K_0804_8P4R_5%
2.2K_0804_8P4R_5%
2
R
R
H142 2.2K_0402_5%
H142 2.2K_0402_5%
R
R
H144 2.2K_0402_5%
H144 2.2K_0402_5%
C C
1
H154 1 50_0402_1%
H154 1 50_0402_1%
R
R
1 2
H156 1 50_0402_1%
H156 1 50_0402_1%
R
R
1 2
H152 1 50_0402_1%
H152 1 50_0402_1%
R
R
B B
PH8
PH8
CRT@
CRT@
CRT@
CRT@
CRT@
CRT@
CRT@
CRT@
CRT@
CRT@
6
1
12
2
E
C_ENBKL
L
CTL_CLK
L
CTL_DATA
L
CD_EDID_CLK
L
CD_EDID_DATA
U
MA_CRT_DATA
U
MA_CRT_CLK
U
MA_CRT_B
U
MA_CRT_G
U
MA_CRT_R
U
U
E
C_ENBKL<22,41>
L
CD_ENVDD<22>
P
CH_PWM<22>
L
CD_EDID_CLK<22>
L
CD_EDID_DATA<22>
1 2
H143 2 .37K_0402_1%
H143 2 .37K_0402_1%
R
R
L
CD_TXCLK-<22>
L
CD_TXCLK+<22>
L
CD_TXOUT0-<22>
L
CD_TXOUT1-<22>
L
CD_TXOUT2-<22>
L
CD_TXOUT0+<22>
L
CD_TXOUT1+<22>
L
CD_TXOUT2+<22>
U
MA_CRT_B<23>
U
MA_CRT_G<23>
U
MA_CRT_R<23>
U
MA_CRT_CLK<23>
U
MA_CRT_DATA<23>
MA_CRT_HSYNC<23>
MA_CRT_VSYNC<23>
4
H138 1 K_0402_0.5%
H138 1 K_0402_0.5%
R
R
CRT@
CRT@
H138
H138
R
R
1K_0402_5%
1K_0402_5%
NOCRT@
NOCRT@
E
C_ENBKL
L
CD_ENVDD
P
CH_PWM
LCD_EDID_CLK
L
CD_EDID_DATA
L
CTL_CLK
L
CTL_DATA
L
VDS_IBG
U
MA_CRT_B
U
MA_CRT_G
U
MA_CRT_R
U
MA_CRT_CLK
U
MA_CRT_DATA
12
C
RT_IREF
U
U
H1D
H1D
J47
L
_BKLTEN
M45
L
_VDD_EN
P45
L
_BKLTCTL
T40
L
_DDC_CLK
K47
L
_DDC_DATA
T45
L
_CTRL_CLK
P39
L
_CTRL_DATA
INT.PD 20K
AF37
L
VD_IBG
AF36
L
VD_VBG
AE48
L
VD_VREFH
AE47
L
VD_VREFL
AK39
L
VDSA_CLK#
AK40
L
VDSA_CLK
AN48
L
VDSA_DATA#0
AM47
L
VDSA_DATA#1
AK47
L
VDSA_DATA#2
AJ48
L
VDSA_DATA#3
AN47
L
VDSA_DATA0
AM49
L
VDSA_DATA1
AK49
L
VDSA_DATA2
AJ47
L
VDSA_DATA3
AF40
L
VDSB_CLK#
AF39
L
VDSB_CLK
AH45
L
VDSB_DATA#0
AH47
L
VDSB_DATA#1
AF49
L
VDSB_DATA#2
AF45
L
VDSB_DATA#3
AH43
L
VDSB_DATA0
AH49
L
VDSB_DATA1
AF47
L
VDSB_DATA2
AF43
L
VDSB_DATA3
N48
RT_BLUE
C
P49
RT_GREEN
C
T49
RT_RED
C
T39
RT_DDC_CLK
C
M40
RT_DDC_DATA
C
M47
RT_HSYNC
C
M49
RT_VSYNC
C
T43
AC_IREF
D
T42
RT_IRTN
C
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
HM76R3@
HM76R3@
3
DVO_INTN
S
DVO_INTP
S
DPB_AUXN
DPB_AUXP
DPB_HPD
D
D
DPB_0N
D
DPB_0P
D
DPB_1N
D
DPB_1P
D
DPB_2N
D
DPB_2P
D
DPB_3N
D
DPB_3P
DPC_AUXN
DPC_AUXP
DPC_HPD
D
D
DPC_0N
D
DPC_0P
D
DPC_1N
D
DPC_1P
D
DPC_2N
DPC_2P
D
D
DPC_3N
DPC_3P
D
DPD_AUXN
DPD_AUXP
DPD_HPD
D
D
DPD_0N
DPD_0P
D
D
DPD_1N
DPD_1P
D
D
DPD_2N
D
DPD_2P
D
DPD_3N
D
DPD_3P
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
INT.PD 50
INT.PD 50
VDS
VDS
L
L
RT
RT
C
C
DVO_TVCLKINN
S
DVO_TVCLKINP
S
INT.PD 50
INT.PD 50
INT.PD 50
INT.PD 50
DVO_STALLN
S
DVO_STALLP
S
DVO_CTRLCLK
S
DVO_CTRLDATA
S
INT.PD 20K
D
D
DPC_CTRLCLK
D
DPC_CTRLDATA
D
INT.PD 20K
D
D
Digital Display Interface
Digital Display Interface
DPD_CTRLCLK
D
DPD_CTRLDATA
D
INT.PD 20K
D
D
U
MA_HDMI_CLK <24>
U
MA_HDMI_DATA <24>
H
DMI_HPD
H141 100K_0402_5%
H141 100K_0402_5%
R
R
H255 100K_0402_5%
H255 100K_0402_5%
R
R
H
U
U
U
U
U
U
U
U
12
12
DMI_HPD <24,30>
MA_HDMI_TX2- <24>
MA_HDMI_TX2+ <24>
MA_HDMI_TX1- <24>
MA_HDMI_TX1+ <24>
MA_HDMI_TX0- <24>
MA_HDMI_TX0+ <24>
MA_HDMI_CLK- <24>
MA_HDMI_CLK+ <24>
2
H
DMI
1
A A
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
Title
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
2
Date: Sheet
ompal Electronics, Inc.
P
P
P
CH_CRT/LVDS/HDMI
CH_CRT/LVDS/HDMI
CH_CRT/LVDS/HDMI
V
V
V
FKAA
FKAA
FKAA
1
0
0
0
.2
.2
.2
o
o
o
f
28 56Monday, March 11, 2013
f
28 56Monday, March 11, 2013
f
28 56Monday, March 11, 2013
Page 29
5
D D
+
3VS
C C
B B
PH12
PH12
R
R
1 8
7
2
3 6
5
4
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
R
R
PH13
PH13
1 8
7
2
3 6
4 5
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
R
H17610K_0402_5%RH17610K_0402_5%
1 2
R
H3058.2K_0402_5%RH3058.2K_0402_5%
2
1
R
H3068.2K_0402_5%RH3068.2K_0402_5%
1 2
P
CH_GPIO52
P
CH_GPIO2
P
CH_GPIO51
O
DD_DA#
P
CI_PIRQD#
P
CI_PIRQA#
P
CI_PIRQB#
P
CI_PIRQC#
D
GPU_PWR_EN
P
CH_GPIO4
P
CH_GPIO5
C
LK_PCI_EC<41>
C
LK_PCILOOP<26>
U
O
DD_DA#<34>
T
LT_RST#<35,36,41,5>
1
1 2
T
80 PADT80 PAD
81 PADT81 PAD
3RXDN1
U
3RXDN2
U
3RXDP1
U
3RXDP2
U
3TXDN1
U
3TXDN2
U
3TXDP1
U
3TXDP2
2
R
R
U
3RXDN1< 38>
U
3RXDN2< 38>
U
3RXDP1<38>
U
3RXDP2<38>
U
3TXDN1<38>
U
3TXDN2<38>
U
3TXDP1<38>
U
3TXDP2<38>
D
GPU_PWR_EN<17>
P
1
H115
H115
RF@
RF@
@
@
C
C
2
22P_0402_50V8J
22P_0402_50V8J
P
CI_PIRQA#
P
CI_PIRQB#
P
CI_PIRQC#
P
CI_PIRQD#
D
GPU_RST#
P
CH_GPIO52
D
GPU_PWR_EN
P
CH_GPIO51
P
CH_GPIO2
O
DD_DA#
P
CH_GPIO4
P
CH_GPIO5
P
CI_PME#
P
LT_RST#
C
LK_EC_R
H16722_0402_5% EMI@RH16722_0402_5% EMI@
C
LK_PCH
H1660_0402_5% Rshort@RH1660_0402_5% Rshort@
C
LK_PCI_DDR
4
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
B21
M20
AY16
BG46
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
K40
K38
H38
G38
C46
C44
E40
D47
E42
F46
G42
G40
C42
D44
K10
C6
H49
H43
J48
K42
H40
H1E
H1E
U
U
T
P1
T
P2
T
P3
T
P4
P5
T
P6
T
T
P7
P8
T
T
P9
T
P10
T
P11
T
P12
T
P13
T
P14
T
P15
P16
T
P17
T
P18
T
P19
T
P20
T
SVD
SVD
R
P21
T
P22
T
P23
T
T
P24
SB3Rn1
U
SB3Rn2
U
SB3Rn3
U
SB3Rn4
U
U
SB3Rp1
U
SB3Rp2
U
SB3Rp3
U
SB3Rp4
U
SB3Tn1
U
SB3Tn2
U
SB3Tn3
U
SB3Tn4
U
SB3Tp1
U
SB3Tp2
U
SB3Tp3
U
SB3Tp4
IRQA#
P
IRQB#
P
IRQC#
P
IRQD#
P
EQ1# / GPIO50
R
EQ2# / GPIO52
R
EQ3# / GPIO54
R
NT1# / GPIO51
G
NT2# / GPIO53
G
NT3# / GPIO55
G
IRQE# / GPIO2
P
IRQF# / GPIO3
P
IRQG# / GPIO4
P
IRQH# / GPIO5
P
ME#
P
LTRST#
P
LKOUT_PCI0
C
LKOUT_PCI1
C
LKOUT_PCI2
C
LKOUT_PCI3
C
LKOUT_PCI4
C
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
HM76R3@
HM76R3@
R
I
NT.PU 20K
INT.PU 20K
INT.PU 20K
INT.PU 20K
INT.PD 20K
INT.PD 20K
INT.PD 20K
INT.PD 20K
INT.PD 20K
CI
CI
P
P
INT.PD 20K
E
HCI 1
EHCI 2
USB
USB
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
SBP10N
U
SBP10P
U
SBP11N
U
SBP11P
U
SBP12N
U
SBP12P
U
SBP13N
U
SBP13P
U
SBRBIAS#
U
SBRBIAS
U
C0# / GPIO59
O
C1# / GPIO40
O
C2# / GPIO41
O
C3# / GPIO42
O
C4# / GPIO43
O
C5# / GPIO9
O
C6# / GPIO10
O
C7# / GPIO14
O
SVD1
R
SVD2
R
SVD3
R
SVD4
R
SVD5
R
SVD6
R
SVD7
R
SVD8
R
SVD9
R
SVD10
SVD11
SVD12
SVD13
SVD14
SVD15
SVD16
SVD17
SVD18
SVD19
SVD20
SVD21
SVD22
SVD23
SVD24
SVD25
SVD26
SVD27
SVD28
SVD29
SBP0N
SBP0P
SBP1N
SBP1P
SBP2N
SBP2P
SBP3N
SBP3P
SBP4N
SBP4P
SBP5N
SBP5P
SBP6N
SBP6P
SBP7N
SBP7P
SBP8N
SBP8P
SBP9N
SBP9P
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33
B33
A14
K20
B17
C16
L16
A16
D14
C14
3
F
or Optimus
100K_0402_5%
100K_0402_5%
N
V_ALE
N
ote: HM70 only enable
USB port 0, 1, 2, 3, 8, 9, 10, 11
U
SB20_N0
U
SB20_P0
U
SB20_N1
U
SB20_P1
U
SB20_N2
U
SB20_P2
U
SB20_N3
U
SB20_P3
U
SB20_N8
U
SB20_P8
U
SB20_N9
U
SB20_P9
U
SB20_N11
U
SB20_P11
U
SBBIAS
U
SB_OC#0
U
SB_CHG_OC#
U
SB_OC#2
S
LP_CHG_CB1
S
LP_CHG_CB0
U
SB_OC#5_7
U
SB20_N0 <38>
U
SB20_P0 <38>
U
SB20_N1 <38>
U
SB20_P1 <38>
U
SB20_N2 <36>
U
SB20_P2 <36>
U
SB20_N3 <37>
U
SB20_P3 <37>
U
SB20_N8 <22>
U
SB20_P8 <22>
U
SB20_N9 <35>
U
SB20_P9 <35>
U
SB20_N11 <22>
U
SB20_P11 <22>
1
H165 2 2.6_0402_1%
H165 2 2.6_0402_1%
R
R
Within 500 mils
U
U
U
S
S
2
SB_OC#0 <38,41>
SB_CHG_OC# <26,38,41>
SB_OC#2 <36,41>
LP_CHG_CB1 <38>
LP_CHG_CB0 <27,38>
P
LT_RST#
D
GPU_RST#
2
R
R
H173
H173
1
USB-Right1
USB-Right2
USB-Left
CardReader
T
ouch Screen
B
T
Int. Camera
U
SB-Right Rear
USB-Right Front
U
SB-Left
2
+
3VS
12
H175
H175
R
R
10K_0402_5%
10K_0402_5%
2
C
C
H12
H12
0.47U_0402_6.3V6K
0.47U_0402_6.3V6K
1
+
3VS
0
206: Delete 0.1uF
5
U
U
H6
H6
1
P
I
N1
4
O
2
I
N2
G
SN74AHC1G08DCKR_SC70-5
SN74AHC1G08DCKR_SC70-5
3
100K_0402_5%
100K_0402_5%
N
V_ALE
P
12
H288
H288
R
R
I
ntel Anti-Theft Techonlogy
LTRST_VGA# <13>
High=Endabled
Low=Disable(floating)
N
V_ALE
U
SB_OC#0
U
SB_OC#5_7
S
LP_CHG_CB1
U
SB_OC#2
1 2
@
@
R
R
H164 1K_0402_5%
H164 1K_0402_5%
R
R
PH11
PH11
1 8
2 7
6
3
4 5
10K_0804_8P4R_5%
10K_0804_8P4R_5%
+
3VALW_PCH
1
*
+
1.8VS
Boot BIOS Strap
P
CH_GPIO51
ESD@
ESD@
1 2
A A
2
O
DD_DA#
H105180P_0402_50V8J
H105180P_0402_50V8J
C
C
12
P
CH_GPIO51
R
H2931K_0402_5% @RH2931K_0402_5% @
1
P
CH_GPIO19
R
H2941K_0402_5% @RH2941K_0402_5% @
P
CH_GPIO19 <25>
P
CH_GPIO19 Boot BIOS Loaction
0
0
1
0
1
0
1 1
LPC
Reserved
PCI
S
PI
*
A16 Swap Override Strap
L
W
L_OFF#
5
ow= A16 swap override Enable
High= A16 swap override Disable
*
4
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
2
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
T
itle
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
Date: Sheet
ompal Electronics, Inc.
P
P
P
CH_PCI/USB/NAND
CH_PCI/USB/NAND
CH_PCI/USB/NAND
V
V
V
FKAA
FKAA
FKAA
1
o
o
o
f
29 56Monday, March 11, 2013
f
29 56Monday, March 11, 2013
f
29 56Monday, March 11, 2013
0
0
0
.2
.2
.2
Page 30
5
4
3
2
1
ONKYO
Non-Brand1
H
_SNB_IVB# <5>
+3VS
H1F
H1F
U
U
H
H
+
3VALW_PCH
12
E
R
R
H204 1K_0402_5%
H204 1K_0402_5%
D D
+
3VS
2
1
R
R
H178 200K_0402_5%
H178 200K_0402_5%
+
3VS
R
R
PH15
PH15
8
1
2 7
3 6
5
4
10K_0804_8P4R_5%
10K_0804_8P4R_5%
GVDR@
GVDR@
R
R
R
R
C C
SM_DET
(GPIO48)
R
R
R
R
R
12
H202 10K_0402_5%
H202 10K_0402_5%
12
H200 10K_0402_5%269@
H200 10K_0402_5%269@
GVSR@
GVSR@
12
H203 10K_0402_5%
H203 10K_0402_5%
12
H201 10K_0402_5%259@
H201 10K_0402_5%259@
2
1
H199 10K_0402_5%@RH199 10K_0402_5%@
BIOS setup
1
0
B B
C_LID_OUT#
O
DD_DETECT#
P
CH_GPIO34
P
CH_GPIO16
E
C_SCI#
P
CH_GPIO49
V
RAM_DR_SR#
S
M_DET
V
RAM_DR_SR#
S
M_DET
P
CH_GPIO27
S
peaker Type
F
ollow Compal ORB
and Intel Check list 460603 V1.5
Harman/KardonS&M option 269@
Non Harman
BOM
259@
F
or Optimus
DMI_HPD<24,28>
E
C_SCI#<41>
E
C_SMI#<27,41>
E
C_LID_OUT#<41>
V
GA_PWROK<17,54>
P
CH_GPIO28<26>
O
DD_DETECT#<34>
P
CH_GPIO37<27>
O
PTIMUS_EN#<27>
DMI_HPD
E
C_SCI#
E
C_LID_OUT#
P
CH_GPIO16
V
GA_PWROK
V
RAM_DR_SR#
P
CH_GPIO27
P
CH_GPIO34
O
DD_DETECT#
S
M_DET
P
CH_GPIO49
T7
MBUSY# / GPIO0
B
A42
ACH1 / GPIO1
T
H36
ACH2 / GPIO6
T
E38
ACH3 / GPIO7
T
C10
INT.PH 20K
PIO8
G
C4
AN_PHY_PWR_CTRL / GPIO12
L
G2
INT.PD 20K
PIO15
G
U2
ATA4GP / GPIO16
S
D40
T5
E8
E16
P8
K1
K4
V8
M5
N2
M3
V13
V3
D6
A4
A44
A45
A46
A5
A6
B3
B47
BD1
BD49
BE1
BE49
BF1
BF49
INT.PH 20K
ACH0 / GPIO17
T
CLOCK / GPIO22
S
PIO24
G
INT.PH 20K
PIO27
G
INT.PH 20K
PIO28
G
TP_PCI# / GPIO34
S
PIO35
G
ATA2GP / GPIO36
S
ATA3GP / GPIO37
S
LOAD / GPIO38
S
DATAOUT0 / GPIO39
S
DATAOUT1 / GPIO48
S
ATA5GP / GPIO49 / TEMP_ALERT#
S
PIO57
G
SS_NCTF_1
V
SS_NCTF_2
V
SS_NCTF_3
V
SS_NCTF_4
V
SS_NCTF_5
V
SS_NCTF_6
V
SS_NCTF_7
V
SS_NCTF_8
V
SS_NCTF_9
V
SS_NCTF_10
V
SS_NCTF_11
V
SS_NCTF_12
V
SS_NCTF_13
V
SS_NCTF_14
V
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
HM76R3@
HM76R3@
INT.PH 20K
INT.PH 20K
INT.PH 20K
INT.PD 20K
INT.PD 20K
GPIO28
O
n-Die PLL Voltage Regulator
H: Enable
*
L: Disable
INT.PH 20K
T
INT.PH 20K
T
INT.PH 20K
T
INT.PH 20K
T
INT.PD 350
GPIO
GPIO
INT.PH 20K
INT.PD 20K
PU/MISC
PU/MISC
C
C
CTF
CTF
N
N
ACH4 / GPIO68
ACH5 / GPIO69
ACH6 / GPIO70
ACH7 / GPIO71
20GATE
A
P
CIN#
R
ROCPWRGD
P
HRMTRIP#
T
NIT3_3V#
I
F_TVS
D
S_VSS1
T
S_VSS2
T
S_VSS3
T
S_VSS4
T
N
SS_NCTF_15
V
SS_NCTF_16
V
SS_NCTF_17
V
SS_NCTF_18
V
SS_NCTF_19
V
SS_NCTF_20
V
SS_NCTF_21
V
SS_NCTF_22
V
SS_NCTF_23
V
SS_NCTF_24
V
SS_NCTF_25
V
SS_NCTF_26
V
SS_NCTF_27
V
SS_NCTF_28
V
SS_NCTF_29
V
SS_NCTF_30
V
SS_NCTF_31
V
SS_NCTF_32
V
C40
O
DD_EN#
B41
C
PU_PGA_BGA#
C41
S
PK_DET
A40
P4
G
ATEA20
AU16
ECI
P5
K
B_RST#
AY11
H
_PWRGOOD
AY10
P
CH_THRMTRIP#
T14
AY1
AH8
AK11
AH10
AK10
P37
C_1
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
N
V_CLE
O
DD_EN# <43>
f
or common BIOS on PBA/BGA CPU
S
PK_DET <40>
G
K
1 2
R
R
H191 390_0402_5%
H191 390_0402_5%
T
his signal has weak internal
pull-up, can't be pulled low
H
H
ATEA20 <41>
B_RST# < 41>
_PWRGOOD <5>
_THERMTRIP# <5>
N
V_CLE
O
DD_EN#
G
ATEA20
K
B_RST#
C
PU_PGA_BGA#
SPK_DET
(GPIO70)
DMI & FDI Termination Voltage
Set to VCC when HIGH
NV_CLE
S
et to VSS when LOW
2
1
R
R
H189 1K_0402_5%
H189 1K_0402_5%
R
R
PH16
PH16
1 8
2 7
3 6
4 5
10K_0804_8P4R_5%
10K_0804_8P4R_5%
Non-Harman detection
0
+
1.8VS
12
R
R
H187
H187
2.2K_0402_5%
2.2K_0402_5%
GPIO8
Integrated Clock Chip Enable (Removed)
H: Disable
L: Enable
*
A A
Integrated clock enable functionality
is achieved by soft-strap
The current default is clock enable
5
OPTIMUS_EN#
OPTIMUS_EN#
SKU NonOPT
H L
4
Optimus
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
2
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
Title
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
Date: Sheet
ompal Electronics, Inc.
P
P
P
CH_CPU/GPIO
CH_CPU/GPIO
CH_CPU/GPIO
V
V
V
FKAA
FKAA
FKAA
1
o
o
o
f
30 56Monday, March 11, 2013
f
30 56Monday, March 11, 2013
f
30 56Monday, March 11, 2013
0
0
0
.2
.2
.2
Page 31
5
+
1.05VS_VCCP
D D
C C
B B
JP@
JP@
2
2
JUMP_43X79
JUMP_43X79
10U_0603_6.3V6M
10U_0603_6.3V6M
+
1.05VS_PCH
C
C
10U_0603_6.3V6M
10U_0603_6.3V6M
P
P
J4
J4
1
1
1
H32
H32
C
C
2
This pin can be left as NC if
On-Die VR is enabled (Default)
1
C
C
H43
H43
H45
H45
2
1U_0402_6.3V6K
1U_0402_6.3V6K
T
his pin can be left as NC if
On-Die VR is enabled (Default)
1
H33
H33
C
C
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C
C
H46
H46
2
2
+
3VS
1U_0402_6.3V6K
1U_0402_6.3V6K
C
C
H31
H31
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C
C
2
1U_0402_6.3V6K
1U_0402_6.3V6K
+
1.05VS_PCH
1
H47
H47
2
1
H50
H50
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
2
+
1.05VS_PCH
+
VCCP_VCCDMI
+
1.05VS_PCH
1
H34
H34
2
1
C
C
H44
H44
1U_0402_6.3V6K
1U_0402_6.3V6K
2
+
VCCAFDI_VRM
4
U
U
H1G
H1G
1730mA
AA23
CCCORE[1]
V
AC23
CCCORE[2]
V
AD21
CCCORE[3]
V
AD23
CCCORE[4]
V
AF21
CCCORE[5]
V
AF23
CCCORE[6]
V
AG21
CCCORE[7]
V
AG23
CCCORE[8]
V
AG24
CCCORE[9]
V
AG26
CCCORE[10]
V
AG27
CCCORE[11]
V
AG29
CCCORE[12]
V
AJ23
CCCORE[13]
V
AJ26
CCCORE[14]
V
AJ27
CCCORE[15]
V
AJ29
CCCORE[16]
V
AJ31
CCCORE[17]
V
AN19
CCIO[28]
V
BJ22
82PADT82PAD
T
T
83PADT83PAD
CCAPLLEXP
V
AN16
CCIO[15]
V
AN17
CCIO[16]
V
AN21
CCIO[17]
V
AN26
CCIO[18]
V
AN27
CCIO[19]
V
AP21
CCIO[20]
V
AP23
CCIO[21]
V
AP24
CCIO[22]
V
AP26
CCIO[23]
V
AT24
CCIO[24]
V
AN33
CCIO[25]
V
AN34
CCIO[26]
V
BH29
CC3_3[3]
V
AP16
CCVRM[2]
V
BG6
ccAFDIPLL
V
AP17
CCIO[27]
V
AU20
CCDMI[2]
V
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
HM76R3@
HM76R3@
3709mA
P
P
OWER
OWER
CC CORE
CC CORE
V
V
VCCIO
VCCIO
FDI
FDI
V
1mA
V
RTLVDS
RTLVDS
C
C
1mA
CCALVDS
V
SSALVDS
V
CCTX_LVDS[1]
V
CCTX_LVDS[2]
V
60mA
CCTX_LVDS[3]
V
CCTX_LVDS[4]
V
V
V
VCMOS
VCMOS
H
H
CCVRM[3]
V
V
MI
MI
D
D
7
5mA
CCCLKDMI
V
V
CCDFTERM
CCDFTERM[1]
V
CCDFTERM[2]
V
190mA
CCDFTERM[3]
V
CCDFTERM[4]
V
DFT / SPI
DFT / SPI
20mA
CCADAC
SSADAC
CC3_3[6]
CC3_3[7]
CCDMI[1]
CCSPI
V
U48
U47
AK36
AK37
AM37
AM38
AP36
AP37
V33
V34
AT16
AT20
AB36
AG16
AG17
AJ16
AJ17
V1
3
+
VCCA_DAC
0.01U_0402_25V7K
0.01U_0402_25V7K
+
VCCA_LVDS
+
VCCTX_LVDS
C
C
0.01U_0402_25V7K
0.01U_0402_25V7K
1
2
+
VCCAFDI_VRM
+
VCCP_VCCDMI
+
1.05VS_VCC_DMI
1
2
1
2
C
C
H35
H35
0.01U_0402_25V7K
0.01U_0402_25V7K
H38
H38
C
C
H42
H42
0.1U_0402_10V7K
0.1U_0402_10V7K
+
VCCP_VCCDMI
R
R
1
C
C
H49
H49
1U_0402_6.3V6K
1U_0402_6.3V6K
2
C
C
H51
H51
0.1U_0402_10V7K
0.1U_0402_10V7K
+
3VALW_PCH
H53
H53
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
C
C
H36
H36
2
1
Rshort@
Rshort@
R
R
H208 0_0402_5%
H208 0_0402_5%
H39
H39
C
C
+
3VS
+
VCCAFDI_VRM
H214 0_0402_5%
H214 0_0402_5%
1 2
Rshort@
Rshort@
+
1.8VS
1 2
1
H37
H37
C
C
10U_0603_6.3V6M
10U_0603_6.3V6M
2
2
1
H40
H40
C
C
22U_0805_6.3V6M
22U_0805_6.3V6M
2
+
1.05VS_PCH
H309
H309
R
R
+
VCCA_DAC_R
1_0603_1%
1_0603_1%
+
3VS
H2
H2
L
L
2
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
H221 0_0402_5%
H221 0_0402_5%
R
R
1 2
Rshort@
Rshort@
R
R
H213 0_0402_5%
H213 0_0402_5%
1 2
1
H48
H48
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
2
Rshort@
Rshort@
1
+
2
H1
H1
L
L
2
1
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
+
1.8VS
1.5VS
+
1.05VS_VCCP
1
+
3VS
P
CH Power Rail Table
Refer to PCH EDS R1.0
Voltage Rail
V_PROC_IO
V5REF
V5REF_Sus
Vcc3_3
VccADAC
VccADPLLA
VccADPLLB
VccCore
VccDMI
Voltage
1.05
5
5
3.3
3
.3
1.05
1.05
1.05
1
.1
S
0 Iccmax
Current (A)
0.001
0.001
0.001
0.228
0.063
0.08
0.08
1.7
0.047
1.05VccIO 3.711
1.05VccASW 0.903
3.3VccSPI 0.01
3.3VccDSW 0.001
1.8 0. 002VccDFTERM
3.3VccRTC N/A
3.3VccSus3_3
3.3VccSusHDA
0.095
0.01
VccVRM 1.5 0.16 7
1.05VccCLKDMI
V
ccSSC 1.05 0.095
0.07
VccDIFFCLKN 1.05 0.055
VccALVDS 3 .3
0.001
1.8VccTX_LVDS 0.04
+
3VALW to +3VALW_PCH
+
3VALW
A A
2
P
P
CH_PWR_EN#<32,43>
CH_PWR_EN#
5
1
H3 47K_0402_5%
H3 47K_0402_5%
R
R
JP@
JP@
2
JUMP_43X39
JUMP_43X39
H2
H2
Q
Q
AO3413_SOT23
AO3413_SOT23
S
S
3
G
G
1
H1110.1U_0402_25V6CH1110.1U_0402_25V6
C
2
P
P
J2
J2
112
D
D
1
2
H1120.01U_0402_25V7KCH1120.01U_0402_25V7K
C
+
3VALW_PCH
1
H1130.1U_0402_10V7KCH1130.1U_0402_10V7K
C
2
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
Title
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
2
Date: Sheet
ompal Electronics, Inc.
P
P
P
CH_POWER-1
CH_POWER-1
CH_POWER-1
V
V
V
FKAA
FKAA
FKAA
1
0
0
0
.2
.2
.2
o
o
o
f
31 56Monday, March 11, 2013
f
31 56Monday, March 11, 2013
f
31 56Monday, March 11, 2013
Page 32
5
4
3
2
1
+
+3VS
L
L
H5
H5
1 2
10UH_LB2012T100MR_20%
10UH_LB2012T100MR_20%
D D
C C
+
1.05VS_PCH
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
B B
+
1.05VS_PCH
R
R
H247 0_0402_5%
H247 0_0402_5%
2
1
Rshort@
Rshort@
A A
+
1
C
C
H81
H81
1U_0402_6.3V6K
1U_0402_6.3V6K
2
+
3VS_VCC_CLKF33
1
H73
H73
C
C
10U_0603_6.3V6M
10U_0603_6.3V6M
2
L
L
H7
H7
2
1
L
L
H8
H8
1 2
C
C
H93
H93
10U_0603_6.3V6M
10U_0603_6.3V6M
P
lace CH79 near pin AF17
+
1.05VS_VCCDIFFCLKN
1.05VS_VCCDIFFCLKN
1
H74
H74
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
2
+
1.05VS_VCCADPLLA
+
1.05VS_VCCADPLLB
1
1
C
C
H94
H94
1U_0402_6.3V6K
1U_0402_6.3V6K
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
+
1.05VS_VCCP
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C
C
H95
H95
+
3VALW_PCH
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
+
1.05VS_PCH
1U_0402_6.3V6K
1U_0402_6.3V6K
+
1.05VS_PCH
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
C
C
C
C
H86
H86
2
+
1.05VS_PCH
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
H87
H87
Place CH86, CH8 7, CH88 near pi n BJ8
This pin can be left as NC if
On-Die VR is enabled (Default)
1
H55
H55
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
2
+
1.05VS_PCH
H64
H64
C
C
22U_0805_6.3V6M
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C
C
C
C
H67
H67
H68
H68
2
H96
H96
1
H78
H78
C
C
2
1
C
C
H79
H79
2
1
H84
H84
C
C
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
H85
H85
C
C
2
1
1
C
C
H88
H88
0.1U_0402_10V7K
0.1U_0402_10V7K
2
2
+
3VS_VCC_CLKF33
1
1
H65
H65
C
C
22U_0805_6.3V6M
22U_0805_6.3V6M
2
2
1
1
C
C
H69
H69
1U_0402_6.3V6K
1U_0402_6.3V6K
2
2
+
VCCRTCEXT
+
VCCAFDI_VRM
+
1.05VS_VCCADPLLA
+
1.05VS_VCCADPLLB
+
1.05VS_VCCDIFFCLKN
+
VCCSST
+
RTCVCC
0.1U_0402_10V7K
0.1U_0402_10V7K
1
C
C
H90
H90
2
H1J
H1J
U
U
AD49
CCACLK
V
T16
CCDSW3_3
V
V12
CPSUSBYP
D
T38
CC3_3[5]
V
BH23
CCAPLLDMI2
V
AL29
CCIO[14]
V
AL24
CPSUS[3]
D
AA19
CCASW[1]
V
AA21
CCASW[2]
V
AA24
CCASW[3]
V
AA26
CCASW[4]
V
AA27
CCASW[5]
V
AA29
CCASW[6]
V
AA31
CCASW[7]
V
AC26
CCASW[8]
V
AC27
CCASW[9]
V
AC29
CCASW[10]
V
AC31
CCASW[11]
V
AD29
CCASW[12]
V
AD31
CCASW[13]
V
W21
CCASW[14]
V
W23
CCASW[15]
V
W24
CCASW[16]
V
W26
CCASW[17]
V
W29
CCASW[18]
V
W31
CCASW[19]
V
W33
CCASW[20]
V
N16
CPRTC
D
Y49
CCVRM[4]
V
BD47
CCADPLLA
V
BF47
CCADPLLB
V
AF17
CCIO[7]
V
AF33
CCDIFFCLKN[1]
V
AF34
CCDIFFCLKN[2]
V
AG34
CCDIFFCLKN[3]
V
AG33
CCSSC
V
V16
CPSST
D
T17
CPSUS[1]
D
V19
CPSUS[2]
D
1mA
BJ8
_PROC_IO
V
A22
CCRTC
V
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
OWER
OWER
P
P
CCIO[29]
V
CCIO[30]
119mA
1mA
V
CCIO[31]
V
CCIO[32]
V
CCIO[33]
V
CCSUS3_3[7]
V
CCSUS3_3[8]
V
CCSUS3_3[9]
V
CCSUS3_3[10]
V
CCSUS3_3[6]
V
CCIO[34]
V
5REF_SUS
V
CPSUS[4]
D
CCSUS3_3[1]
V
3
mA
1010mA
1mA
CCSUS3_3[2]
V
CCSUS3_3[3]
V
CCSUS3_3[4]
V
CCSUS3_3[5]
V
CC3_3[1]
lock and Miscellaneous
lock and Miscellaneous
C
C
80mA
80mA
55mA
95mA
CPURTC
CPURTC
HM76R3@
HM76R3@
V
CI/GPIO/LPC
CI/GPIO/LPC
CC3_3[8]
V
P
P
CC3_3[4]
V
CC3_3[2]
V
CCIO[5]
V
CCIO[12]
V
CCIO[13]
V
CCIO[6]
V
CCAPLLSATA
V
ATA USB
ATA USB
S
S
CCVRM[1]
V
CCIO[2]
V
CCIO[3]
V
CCIO[4]
V
CCASW[22]
V
CCASW[23]
V
ISC
ISC
M
M
CCASW[21]
V
10mA
CCSUSHDA
V
DA
DA
H
H
+
N26
P26
P28
T27
T29
T23
T24
V23
V24
P24
T26
M26
+
PCH_V5REF_SUS
AN23
AN24
P34
+
N20
N22
P20
P22
AA16
W16
T34
AJ2
AF13
AH13
AH14
AF14
AK1
AF11
AC16
AC17
AD17
T21
V21
T19
P32
PCH_V5REF_RUN
+
VCCAFDI_VRM
5REF
V
1.05VS_PCH
1
C
C
H56
H56
1U_0402_6.3V6K
1U_0402_6.3V6K
2
+
3VALW_PCH
1
C
C
H60
H60
0.1U_0402_10V7K
0.1U_0402_10V7K
2
+
1.05VS_PCH
1 2
C
C
H66 0.1U_0402_10V7K
H66 0.1U_0402_10V7K
1 2
C
C
H75
H75
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
1
H92
H92
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
2
1
2
+
3VALW_PCH
+
3VALW_PCH
1
C
C
H70
H70
1U_0402_6.3V6K
1U_0402_6.3V6K
2
+
3VS
+
3VS
H76
H76
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
This pin can be left as NC if
On-Die VR is enabled (Default)
+
VCCAFDI_VRM
+
1.05VS_PCH
+
3VALW_PCH
+
3VALW_PCH
C
C
H61
H61
0.1U_0402_10V7K
0.1U_0402_10V7K
+
3VS
1
C
C
H72
H72
0.1U_0402_10V7K
0.1U_0402_10V7K
2
+
1.05VS_PCH
1
C
C
H82
H82
1U_0402_6.3V6K
1U_0402_6.3V6K
2
P
CH_PWR_EN#<31,43>
C
hange RH232, RH237 to 10 ohm by follow Compal ORB abd Intel CRB
+
1.05VS_PCH
1
H77
H77
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
2
Place CH77 near pin AF13, AH13 , AH14, AF14
Place CH82 near pin AC16, AC17 , AD17
5VALW
R
R
H328
H328
47K_0402_5%
47K_0402_5%
10_0402_5%
10_0402_5%
10_0402_5%
10_0402_5%
12
+
R
R
R
R
JP@
JP@
JUMP_43X39
JUMP_43X39
P
P
J5
J5
2
112
Q
Q
H6
H6
AO3413_SOT23
AO3413_SOT23
D
S
D
S
3
1
G
G
2
1
H80
H80
C
C
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
5VALW_PCH+3VALW_PCH
12
D
D
H3
H232
H232
H237
H237
+
5VS+3VS
12
H3
RB751V40_SC76-2
RB751V40_SC76-2
1 2
+
PCH_V5REF_SUS
1
C
C
H63
H63
0.1U_0402_10V7K
0.1U_0402_10V7K
2
2
D
D
H4
H4
RB751V40_SC76-2
RB751V40_SC76-2
1
+
PCH_V5REF_RUN
1
C
C
H71
H71
1U_0402_6.3V6K
1U_0402_6.3V6K
2
+5VALW_PCH
1
H59
H59
C
C
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C
H63 & CH71 are
different by Intel CRB.
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
Title
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
2
Date: Sheet
ompal Electronics, Inc.
P
P
P
CH_POWER-2
CH_POWER-2
CH_POWER-2
V
V
V
FKAA
FKAA
FKAA
1
0
0
0
.2
.2
o
o
o
32 56Monday, March 11, 2013
32 56Monday, March 11, 2013
32 56Monday, March 11, 2013
.2
f
f
f
Page 33
5
U
U
H1H
H1H
H5
SS[0]
V
AA17
V
SS[1]
AA2
V
SS[2]
AA3
V
SS[3]
AA33
SS[4]
D D
C C
B B
A A
V
AA34
V
SS[5]
AB11
V
SS[6]
AB14
V
SS[7]
AB39
V
SS[8]
AB4
V
SS[9]
AB43
V
SS[10]
AB5
V
SS[11]
AB7
V
SS[12]
AC19
V
SS[13]
AC2
V
SS[14]
AC21
V
SS[15]
AC24
V
SS[16]
AC33
V
SS[17]
AC34
V
SS[18]
AC48
V
SS[19]
AD10
V
SS[20]
AD11
V
SS[21]
AD12
V
SS[22]
AD13
V
SS[23]
AD19
V
SS[24]
AD24
V
SS[25]
AD26
V
SS[26]
AD27
V
SS[27]
AD33
V
SS[28]
AD34
V
SS[29]
AD36
V
SS[30]
AD37
V
SS[31]
AD38
SS[32]
V
AD39
V
SS[33]
AD4
V
SS[34]
AD40
V
SS[35]
AD42
V
SS[36]
AD43
V
SS[37]
AD45
V
SS[38]
AD46
V
SS[39]
AD8
SS[40]
V
AE2
SS[41]
V
AE3
SS[42]
V
AF10
V
SS[43]
AF12
V
SS[44]
AD14
SS[45]
V
AD16
V
SS[46]
AF16
V
SS[47]
AF19
V
SS[48]
AF24
V
SS[49]
AF26
V
SS[50]
AF27
V
SS[51]
AF29
V
SS[52]
AF31
V
SS[53]
AF38
V
SS[54]
AF4
V
SS[55]
AF42
V
SS[56]
AF46
V
SS[57]
AF5
SS[58]
V
AF7
V
SS[59]
AF8
V
SS[60]
AG19
V
SS[61]
AG2
V
SS[62]
AG31
V
SS[63]
AG48
V
SS[64]
AH11
V
SS[65]
AH3
V
SS[66]
AH36
V
SS[67]
AH39
V
SS[68]
AH40
V
SS[69]
AH42
V
SS[70]
AH46
V
SS[71]
AH7
V
SS[72]
AJ19
V
SS[73]
AJ21
SS[74]
V
AJ24
SS[75]
V
AJ33
V
SS[76]
AJ34
V
SS[77]
AK12
V
SS[78]
AK3
V
SS[79]
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
HM76R3@
HM76R3@
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS[100]
SS[101]
V
V
SS[102]
V
SS[103]
V
SS[104]
V
SS[105]
V
SS[106]
V
SS[107]
V
SS[108]
V
SS[109]
V
SS[110]
V
SS[111]
V
SS[112]
V
SS[113]
V
SS[114]
SS[115]
V
V
SS[116]
V
SS[117]
V
SS[118]
V
SS[119]
V
SS[120]
V
SS[121]
V
SS[122]
V
SS[123]
V
SS[124]
V
SS[125]
V
SS[126]
V
SS[127]
V
SS[128]
SS[129]
V
SS[130]
V
V
SS[131]
SS[132]
V
SS[133]
V
SS[134]
V
SS[135]
V
SS[136]
V
SS[137]
V
SS[138]
V
SS[139]
V
SS[140]
V
SS[141]
V
SS[142]
V
SS[143]
V
SS[144]
V
SS[145]
V
SS[146]
V
SS[147]
V
SS[148]
V
SS[149]
V
SS[150]
V
SS[151]
V
SS[152]
V
SS[153]
V
SS[154]
V
SS[155]
V
SS[156]
V
SS[157]
V
SS[158]
V
SS[80]
SS[81]
SS[82]
SS[83]
SS[84]
SS[85]
SS[86]
SS[87]
SS[88]
SS[89]
SS[90]
SS[91]
SS[92]
SS[93]
SS[94]
SS[95]
SS[96]
SS[97]
SS[98]
SS[99]
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
4
3
H1I
H1I
U
U
AY4
SS[159]
V
AY42
SS[160]
V
AY46
SS[161]
V
AY8
SS[162]
V
B11
SS[163]
V
B15
SS[164]
V
B19
SS[165]
V
B23
SS[166]
V
B27
SS[167]
V
B31
SS[168]
V
B35
SS[169]
V
B39
SS[170]
V
B7
SS[171]
V
F45
V
SS[172]
BB12
SS[173]
V
BB16
SS[174]
V
BB20
SS[175]
V
BB22
SS[176]
V
BB24
SS[177]
V
BB28
SS[178]
V
BB30
SS[179]
V
BB38
SS[180]
V
BB4
SS[181]
V
BB46
SS[182]
V
BC14
SS[183]
V
BC18
SS[184]
V
BC2
SS[185]
V
BC22
SS[186]
V
BC26
SS[187]
V
BC32
SS[188]
V
BC34
SS[189]
V
BC36
SS[190]
V
BC40
SS[191]
V
BC42
SS[192]
V
BC48
SS[193]
V
BD46
SS[194]
V
BD5
SS[195]
V
BE22
SS[196]
V
BE26
SS[197]
V
BE40
SS[198]
V
BF10
SS[199]
V
BF12
SS[200]
V
BF16
SS[201]
V
BF20
SS[202]
V
BF22
SS[203]
V
BF24
SS[204]
V
BF26
SS[205]
V
BF28
SS[206]
V
BD3
SS[207]
V
BF30
SS[208]
V
BF38
SS[209]
V
BF40
SS[210]
V
BF8
SS[211]
V
BG17
SS[212]
V
BG21
SS[213]
V
BG33
SS[214]
V
BG44
SS[215]
V
BG8
SS[216]
V
BH11
SS[217]
V
BH15
SS[218]
V
BH17
SS[219]
V
BH19
SS[220]
V
H10
V
SS[221]
BH27
SS[222]
V
BH31
SS[223]
V
BH33
SS[224]
V
BH35
SS[225]
V
BH39
SS[226]
V
BH43
SS[227]
V
BH7
SS[228]
V
D3
SS[229]
V
D12
SS[230]
V
D16
SS[231]
V
D18
SS[232]
V
D22
SS[233]
V
D24
SS[234]
V
D26
SS[235]
V
D30
SS[236]
V
D32
SS[237]
V
D34
V
SS[238]
D38
V
SS[239]
D42
V
SS[240]
D8
V
SS[241]
E18
V
SS[242]
E26
V
SS[243]
G18
V
SS[244]
G20
V
SS[245]
G26
V
SS[246]
G28
V
SS[247]
G36
V
SS[248]
G48
V
SS[249]
H12
V
SS[250]
H18
V
SS[251]
H22
V
SS[252]
H24
V
SS[253]
H26
V
SS[254]
H30
V
SS[255]
H32
V
SS[256]
H34
V
SS[257]
F3
V
SS[258]
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
HM76R3@
HM76R3@
V
SS[259]
V
SS[260]
V
SS[261]
V
SS[262]
V
SS[263]
V
SS[264]
SS[265]
V
V
SS[266]
SS[267]
V
SS[268]
V
V
SS[269]
SS[270]
V
V
SS[271]
SS[272]
V
SS[273]
V
SS[274]
V
SS[275]
V
SS[276]
V
SS[277]
V
SS[278]
V
SS[279]
V
SS[280]
V
SS[281]
V
SS[282]
V
SS[283]
V
SS[284]
V
SS[285]
V
V
SS[286]
V
SS[287]
V
SS[288]
SS[289]
V
V
SS[290]
V
SS[291]
V
SS[292]
V
SS[293]
V
SS[294]
V
SS[295]
V
SS[296]
V
SS[297]
V
SS[298]
V
SS[299]
V
SS[300]
V
SS[301]
V
SS[302]
V
SS[303]
V
SS[304]
V
SS[305]
V
SS[306]
V
SS[307]
V
SS[308]
V
SS[309]
V
SS[310]
V
SS[311]
V
SS[312]
V
SS[313]
V
SS[314]
V
SS[315]
V
SS[316]
V
SS[317]
V
SS[318]
V
SS[319]
V
SS[320]
V
SS[321]
V
SS[322]
V
SS[323]
V
SS[324]
V
SS[325]
V
SS[328]
V
SS[329]
V
SS[330]
V
SS[331]
V
SS[333]
V
SS[334]
V
SS[335]
V
SS[337]
V
SS[338]
V
SS[340]
V
SS[342]
V
SS[343]
V
SS[344]
V
SS[345]
V
SS[346]
V
SS[347]
V
SS[348]
V
SS[349]
V
SS[350]
V
SS[351]
V
SS[352]
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
2
1
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
T
itle
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
2
Date: Sheet
ompal Electronics, Inc.
P
P
P
CH_GND
CH_GND
CH_GND
V
V
V
FKAA
FKAA
FKAA
1
0
0
0
.2
.2
.2
o
o
o
f
33 56Monday, March 11, 2013
f
33 56Monday, March 11, 2013
f
33 56Monday, March 11, 2013
Page 34
A
S
ATA HDD Conn.
lose to JHDD
J
J
HDD
HDD
True
1 1
23
G
ND
24
G
ND
SUYIN_127043FR022G196ZR
SUYIN_127043FR022G196ZR
Conn@
Conn@
D
G
G
G
V
V
V
G
G
G
G
AS/DSS
G
V
V
V
1
ND
2
S
A
+
3
A
-
4
ND
5
B
-
6
B
+
7
ND
8
33
9
33
10
33
11
ND
12
ND
13
ND
14
V
5
15
V
5
16
V
5
17
ND
18
19
ND
20
12
21
12
22
12
ATA_PTX_C_DRX_P0
S
ATA_PTX_C_DRX_N0
S
ATA_PRX_DTX_N0
S
ATA_PRX_DTX_P0
C
1 2
369 0.01U_0402_25V7K
369 0.01U_0402_25V7K
C
C
1 2
367 0.01U_0402_25V7K
367 0.01U_0402_25V7K
C
C
1 2
C
C
368 0.01U_0402_25V7K
368 0.01U_0402_25V7K
1 2
C
C
370 0.01U_0402_25V7K
370 0.01U_0402_25V7K
+
3VS
+
5VS
+
5VS
1
.2A
1
C
C
356
356
10U_0805_10V4Z
10U_0805_10V4Z
2
P
lace closely JHDD SATA CONN.
1
357
357
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
2
B
S
ATA_PTX_DRX_P0 <25>
S
ATA_PTX_DRX_N0 <25>
S
ATA_PRX_C_DTX_N0 <25>
S
ATA_PRX_C_DTX_P0 <25>
1
C
C
358
358
0.1U_0402_10V7K
0.1U_0402_10V7K
2
ATA ODD Conn
S
15
ND
G
14
ND
G
SANTA_202401-1
SANTA_202401-1
Conn@
Conn@
C
C
ODD
ODD
J
J
1
ND
G
2
S
3
4
5
6
7
8
9
10
11
12
13
ATA_PTX_C_DRX_P2
S
ATA_PTX_C_DRX_N2
S
ATA_PRX_DTX_N2
S
ATA_PRX_DTX_P2
+
5VS_ODD
+
A
-
A
ND
G
-
B
+
B
ND
G
P
D
5V
+
5V
+
D
M
ND
G
ND
G
lose to JODD
1 2
376 0.01U_0402_ 25V7K
376 0.01U_0402_ 25V7K
C
C
1 2
377 0.01U_0402_ 25V7K
377 0.01U_0402_ 25V7K
C
C
1 2
378 0.01U_0402_ 25V7K
378 0.01U_0402_ 25V7K
C
C
1 2
375 0.01U_0402_ 25V7K
375 0.01U_0402_ 25V7K
C
C
O
DD_DETECT# <30>
O
DD_DA# <29>
D
+
5VS_ODD
1
2
S
ATA_PTX_DRX_P2 <25>
S
ATA_PTX_DRX_N2 <25>
S
ATA_PRX_C_DTX_N2 <25>
S
ATA_PRX_C_DTX_P2 <25>
Place components closely ODD CONN.
355
355
C
C
10U_0805_10V4Z
10U_0805_10V4Z
1
360
360
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
2
1
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
2
380
380
E
ower Consumption
P
Peak 1800 mA
Read (CD) 1100 mA
Read (DVD) 950 mA
Write 1300 mA
Standby 20mA
G-Sensor
2 2
G1
GSENSOR@
G1
GSENSOR@
U
U
2
dd1
V
12
dd2
V
4
T
S
6
D
P
8
S
F
9
ev
R
TSH352TR LGA 16P
TSH352TR LGA 16P
S
A00004GB00
3
V
OUTX
outx
V
5
V
OUTY
outy
V
7
V
OUTZ
outz
V
10
C1
N
11
C2
N
14
C3
N
15
C4
N
16
C5
N
1
ND1
G
13
ND2
G
2
1
C
C
G1 0.033U_0402_16V7KGSENSOR@
G1 0.033U_0402_16V7KGSENSOR@
1 2
C
C
G2 0.033U_0402_16V7KGSENSOR@
G2 0.033U_0402_16V7KGSENSOR@
1 2
G3 0.033U_0402_16V7KGSENSOR@
G3 0.033U_0402_16V7KGSENSOR@
C
C
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
GSENSOR@
GSENSOR@
+
5VS
1
U
2
U
G3
GSENSOR@
G3
GSENSOR@
1
2
3
OUT
V
V
IN
ND
G
S
HDN#
G9191-330T1U_SOT23-5
G9191-330T1U_SOT23-5
SA000022I00
G12
G12
+
3VS_HDP
1
C
C
G13
G13
1U_0402_6.3V6K
5
4
P
B
1U_0402_6.3V6K
GSENSOR@
GSENSOR@
2
+
3VS_HDP
+
3VS_HDP
S
ELF_TEST
G2
G2
U
U
E
3 3
+
3VS_HDP
PG1
PG1
R
R
1 8
2 7
3
4 5
4 4
A
6
4.7K_8P4R_5%
4.7K_8P4R_5%
GSENSOR@
GSENSOR@
+
3VS_HDP_R
G
XOUT
G
XIN
+
3VS_HDP_M
H
DPINT<41>
C_SMB_CK2<13,26,41>
H
DPINT
G7 1K_0402_5%
G7 1K_0402_5%
R
R
S
ELF_TEST
+
3VS_HDP_R
G
XOUT
G
XIN
+
3VS_HDP
+
3VS_HDP_M
12
GSENSOR@
GSENSOR@
C
C
G7
G7
0.1U_0402_10V7K
0.1U_0402_10V7K
GSENSOR@
GSENSOR@
B
1
2
1
2
3
4
5
6
7
8
9
10
1
G8
G8
C
C
GSENSOR@
GSENSOR@
0.1U_0402_10V7K
0.1U_0402_10V7K
2
3_5/SSCK/SCL/CMP1_2
P
3_7/CNTR0#/SSO/TXD1
P
ESET#
R
OUT/P4_7
X
SS/AVSS
V
IN/P4_6
X
CC/AVCC
V
ODE
M
4_5/INT0#/RXD1
P
1_7/CNTR00/INT10#
P
R5F211B4D34SP GSENSOR@
R5F211B4D34SP GSENSOR@
SA00003A600
P
S
S
S
T
T
T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
1_6/CLK0/SSI01
P
1_5/RXD0/CNTR01/INT11#
P
1_3/KI3#/AN11/TZOUT
P
1_2/KI2#/AN10/CMP0_2
P
1_1/KI1#/AN9/CMP0_1
P
1_0/KI0#/AN8/CMP0_0
P
3_3/TCIN/INT3#/SSI00/CMP1_0
3_4/SCS#/SDA/CMP1_1
P
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
C
1_4/TXD0
P
4_2/VREF
P
11
12
13
14
15
V
OUTZ
16
17
V
OUTX
18
V
OUTY
19
20
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
2
G9
G9
R
R
47K_0402_5%
47K_0402_5%
GSENSOR@
GSENSOR@
1
H
DPACT <41>
H
DPLOCK <41>
G10 47K_0402_5%
G10 47K_0402_5%
R
R
12
GSENSOR@
GSENSOR@
+
3VS_HDP
1
G6
G6
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
GSENSOR@
GSENSOR@
2
E
C_SMB_DA2 <13,26,41>
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
D
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
itle
itle
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
ompal Electronics, Inc.
H
H
H
DD/ODD/G-Sensor
DD/ODD/G-Sensor
DD/ODD/G-Sensor
V
V
V
FKAA
FKAA
FKAA
E
3
3
o
o
3
o
f
4 56Monday, March 11, 2013
f
4 56Monday, March 11, 2013
f
4 56Monday, March 11, 2013
0
0
0
.2
.2
.2
Page 35
A
Slot 1 Half PCIe Mini Card-WLAN
40 mils
+
3V_WLAN
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
M2
M2
C
C
C
C
M1
1 1
To EC
(Need pull-up + 3VL)
M1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
W
C
LKREQ_WLAN#<26>
To PCH
P
To PCH
2 2
WLAN/ WiFi
To PCH
CIE_PRX_WLANTX_N 2<26>
P
CIE_PRX_WLANTX_P 2<26>
P
CIE_PTX_C_WLANRX _N2<26>
P
CIE_PTX_C_WLANRX _P2<26>
D
ebug card using
M3
M3
C
C
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
LAN_WAKE#<41>
B
T_ON
C
LK_WLAN#<26>
C
LK_WLAN<26>
E
51_TXD<41>
E
51_RXD<41>
1
2
1
M24
M24
R
R
+
3V_WLAN
2
0_0402_5%@
0_0402_5%@
E
51_TXD
E
51_RXD
B
T_CTRL_R
WLAN
WLAN
J
J
1
1
3
3
5
5
7
7
9
9
11
1
1
13
3
1
15
5
1
17
7
1
19
9
1
21
1
2
23
3
2
25
5
2
27
7
2
29
9
2
31
1
3
33
3
3
35
5
3
37
7
3
39
9
3
41
1
4
43
3
4
45
5
4
47
7
4
49
9
4
51
1
5
53
ND1
ND2
G
G
LOTES_AAA-PCI-049-P06-A
LOTES_AAA-PCI-049-P06-A
Conn@
Conn@
B
+
2
2
4
4
6
6
8
8
10
0
1
12
2
1
14
4
1
16
6
1
18
8
1
20
0
2
22
2
2
24
4
2
26
6
2
28
8
2
30
0
3
32
2
3
34
4
3
36
6
3
38
8
3
40
0
4
42
2
4
44
4
4
46
6
4
48
8
4
50
0
5
52
2
5
54
3V_WLAN
L
ED_WIMAX#
M6 100K_0402_5%
M6 100K_0402_5%
R
R
T
o EC
W
L_OFF# <41>
P
LT_RST# <29,36,41,5>
To PCH
P
M_SMBCLK <11,12,26,42>
P
M_SMBDATA <11,12,26,42>
U
SB20_N9 <29>
U
SB20_P9 <29>
1 2
W
iMax/ BT
L
ED_WIMAX# <42>
+
3VS
From EC
C
W
LAN&BT Combo module circuits
BT_ON
B
T_ON<41>
F
or isolate BT_O N and
Compal Debug Ca rd.
T
o EC
B
T
on module
E
nable Disable
H L
B
T_ON
W
OWL_EN#<41>
BT
on module
1
R
R
M27
M27
1K_0402_5%
1K_0402_5%
WOWL@
WOWL@
R
R
M2
M2
100K_0402_5%
100K_0402_5%
+
3VALW
2
E
51_RXD
1
R
R
M31
M31
10K_0402_5%
10K_0402_5%
2
1 2
47K_0402_5%
47K_0402_5%
12
D
+
3VALW TO +3V_WLAN for WOWL
+
3VALW
WOWL@
WOWL@
2
C
C
M9
M30
M30
R
R
WOWL@
WOWL@
M9
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
WOWL@
WOWL@
M10
M10
C
C
0.01U_0402_25V7K
0.01U_0402_25V7K
1
Vgs=-4.5V,Id=3A ,Rds<97mohm
S
S
G
G
2
AO3413_SOT23
AO3413_SOT23
M2
M2
Q
Q
D
D
1 3
WOWL@
WOWL@
E
I
f system don't support WOWL
+
3V_WLAN
R
R
M1
M1
1 2
0_0603_5%
0_0603_5%
NOWOWL@
NOWOWL@
+
3VS
3VL
1
C
C
CL1
CL1
G
G
CLK@
CLK@
2
C
LK_X1
1
C
C
18P_0402_50V8J
18P_0402_50V8J
GCLK@
GCLK@
2
+
1.05VS_VCCP
1
2
.1U_0402_10V7K
.1U_0402_10V7K
0
0
CL1 25MHZ 12PF X3G025000DK1H-X
CL1 25MHZ 12PF X3G025000DK1H-X
Y
Y
1
1
CL9
CL9
A
+
3 3
4 4
.1U_0402_10V7K
.1U_0402_10V7K
0
0
+
3VS_DGPU+3VALW
1
CL6
CL3
CL3
C
C
CLK@
CLK@
G
G
GCLK@
GCLK@
ND
G
G
2
CL6
C
C
CLK@
CLK@
G
G
2
.1U_0402_10V7K
.1U_0402_10V7K
0
0
3
C
LK_X2
3
ND
4
1
CL8
CL8
C
C
CLK@
CLK@
G
G
2
.1U_0402_10V7K
.1U_0402_10V7K
0
0
f
or safety request
+
RTC
+
3VL
+
3VALW
+
3VS_DGPU
+
1.05VS_VCCP
1
CL12
CL12
C
C
18P_0402_50V8J
18P_0402_50V8J
GCLK@
GCLK@
2
22U_0805_6.3V6M
22U_0805_6.3V6M
CL4
CL4
R
R
120_0603_5%
120_0603_5%
12
GCLK@
GCLK@
P
N: SA000063300
B
1
C
C
CL7
CL7
GCLK@
GCLK@
2
+
RTCGCLK
C
LK_X1
C
LK_X2
SLG3NB304VTR_TQFN16_2X3
SLG3NB304VTR_TQFN16_2X3
10
15
2
11
8
3
1
16
U
U
CL1
CL1
V
BAT
+
V3.3A
V
DD
V
DDIO_27M
V
DDIO_25M_A
V
DDIO_25M_B
X
TAL_IN
X
TAL_OUT
GCLK@
GCLK@
V
DD_RTC_OUT
2
5MHz_A
2
5MHz_B
ND1
ND2
G
G
4
7
13
1
CL11
CL11
C
C
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
GCLK@
GCLK@
2
14
9
3
2kHz
12
2
7MHz
6
5
ND3
ND4
G
G
17
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
V
GA_X1_R
P
CH_X1_R_R
I
I
I
ssued Date
ssued Date
ssued Date
GCLK@
GCLK@
1 2
R
R
CL3 22_0402_5%
CL3 22_0402_5%
2
2 ohm for NV chip
C
P
CH_RTCX1_R <25>
V
GA_X1 <13>
P
CH_X1_R_R
C
C
C
ompal Secret Data
ompal Secret Data
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
1 2
Rshort@
Rshort@
R
R
CL1 0_0402_5%
CL1 0_0402_5%
D
P
CH_X1_R <26>
C
T
T
T
itle
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
ompal Electronics, Inc.
W
W
W
LAN/GCLK
LAN/GCLK
LAN/GCLK
V
V
V
FKAA
FKAA
FKAA
M
M
M
onday, March 11, 2013
onday, March 11, 2013
onday, March 11, 2013
3
3
3
5 56
5 56
E
5 56
0
0
0
.2
.2
.2
o
o
o
f
f
f
Page 36
A
L
eft USB 2.0 x 1
B
C
D
E
O
O
O
O
Rshort@
Rshort@
OL_EN#
UT
UT
UT
CB
2
W=80mils
+
USB_VCCC
6
7
8
5
W
OL_EN#
Sx Enable
Wake up
LOW
F
or EMI
@EMI@
@EMI@
12
C
C
R38 1000P_0402_50V7K
R38 1000P_0402_50V7K
U
SB_OC#2 <29,41>
W
OL_EN# <41>
Sx Disable
Wake up
HIGH
HIGH
J
J
LAN
LAN
+
3V_LAN
P
LT_RST#<29,35,41,5>
E
C_SWI#<26,27>
C
LK_LAN#<26>
C
LK_LAN<26>
P
CIE_PTX_C_LANRX_N1<26>
P
CIE_PTX_C_LANRX_P1<26>
P
CIE_PRX_C_LANTX_N1<26>
P
CIE_PRX_C_LANTX_P1<26>
+
USB_VCCC
S
0
L
ANCLK_REQ#
I
SOLATE#
U
SB20_P2_L
U
SB20_N2_L
W
=80mils
1
1
2
2
2
3
3
4
4
4
5
5
6
6
6
7
7
8
8
8
9
9
10
1
0 10
11
1
1
12
1
2 12
13
1
3
14
1
4 14
15
1
5
16
1
6 16
17
1
7
18
1
8 18
19
1
9
20
2
0 20
21
G
1
22
G
2
23
G
3
24
G
4
ACES_50559-02001-001
ACES_50559-02001-001
Conn@
Conn@
+
5VALW
2
.0A
U
U
R1
R1
3VS
12
1K_0402_5%
1K_0402_5%
R
R
L6
L6
@
@
R
R
15K_0402_5%
15K_0402_5%
I
SOLATE#
L7
L7
2
I
N
3
I
N
4
E
N/ENB
1
G
ND
SY6288DCAC_MSOP8
SY6288DCAC_MSOP8
SA00004KB00
SA00003TV00
1
R
R
L433 0_0402_5%
L433 0_0402_5%
L
R1
EMI@LR1
EMI@
U
U
SB20_N2<29>
U
1 1
2 2
SB20_P2<29>
F
or LAN function
+
3VS
L
AN_EN<26>
C
LKREQ_LAN#<26>
SB20_N2
U
SB20_P2
R
R
L24 10K_0402_5%
L24 10K_0402_5%
L
AN_EN
C
LKREQ_LAN#
2
3
WCM-2012-900T_0805
WCM-2012-900T_0805
12
1 3
2N7002KW_SOT323-3
2N7002KW_SOT323-3
2
3
L
ANCLK_REQ#
2
D
D
Q
Q
L53
L53
G
G
S
S
1
1
4
4
L
ANCLK_REQ#
U
SB20_N2_L
U
SB20_P2_L
U
SB_EN#2< 41>
USB_EN#2
+
W
JP@
JP@
P
P
J29
J29
+
3VALW_PCH
2
JUMP_43X39
JUMP_43X39
+
112
3V_LAN
+
3 3
3V_LAN rising time (10%~90%) need > 1ms and <100ms.
LAN WOL LAN_EN ISOLATEB
S0 Sx S0 Sx
---------------------------------------------Â 0 0 0 0 1 1
0 1 0 0 1 1
1 0 1 1 1 1
1 1 1 1 1 0*
*
S3: after SUSP# assert low over 100ms
S4/S5: after SYSON assert low over 100ms
4 4
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
T
itle
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
D
Date: Sheet
ompal Electronics, Inc.
L
L
L
USB20/LAN conn.
USB20/LAN conn.
USB20/LAN conn.
V
V
V
FKAA
FKAA
FKAA
E
0
0
0
.2
.2
o
o
o
36 56Monday, March 11, 2013
36 56Monday, March 11, 2013
36 56Monday, March 11, 2013
.2
f
f
f
Page 37
5
4
3
2
1
C
C
W8
W8
0.1U_0402_10V7K
0.1U_0402_10V7K
U
SB20_N3<29>
U
D D
C C
B B
"
3
0mils
1 2
Rshort@
Rshort@
+
3VS
R
R
W1 0_0402_5%
W1 0_0402_5%
p
lease close the pin19 of UW1
+
+
3VS_CR
3
0mils
p
lease close the pin4 of UW1
+
3VS_CR
3
0mils
W3
W3
C
C
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
Conn@
Conn@
12
G
ND_SW
13
G
ND_SW
3VS_CR
1
W2
W2
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
2
1
C
C
W4
W4
0.1U_0402_10V7K
0.1U_0402_10V7K
2
<
2 in 1 Card Reader >
J
J
CARD
CARD
V
DD
C
MD
C
V
SS
V
SS
D
AT0
D
AT1
D
AT2
C
D/DAT3
W
P_SW
C
D_SW
T-SOL_156-2000302604
T-SOL_156-2000302604
1
2
5
3
6
LK
7
4
8
9
1
2
10
11
Normal Close" type connector
1
W1
W1
C
C
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2
+
3VS_CR
S
DCMD_R
S
DCLK_R
S
D_DATA0_R
S
D_DATA1_R
S
D_DATA2_R
S
D_DATA3_R
S
DWP#
S
DCD
SB20_P3<29>
+
VCC_3IN1
3
0mils
C
C
W5
W5
0.1U_0402_10V7K
0.1U_0402_10V7K
D
e-coupling and Bulk capacitor should place near to Cardreader chip and Combo Socket
1
@EMI@CW16
@EMI@
1
1
W12
W12
W13
W13
C
C
C
C
2
2
4.7P_0402_50V8C
4.7P_0402_50V8C
4.7P_0402_50V8C
4.7P_0402_50V8C
MI@
MI@
E
E
E
E
MI@
MI@
1
U
U
2
22
2
3
1
+
3VS_CR
24
19
+
3VS_CR
23
+
3VS_CR
20
4
+
3VS_CR
18
+
VDD18
12mils
25
1
GL834L-OGY01_QFN24_4X4
2
GL834L-OGY01_QFN24_4X4
Close to connector
1
C
C
W6
W6
0.1U_0402_10V7K
0.1U_0402_10V7K
2
2
C
W16
4.7P_0402_50V8C
4.7P_0402_50V8C
1
1
W14
W14
W15
W15
C
C
C
C
2
2
4.7P_0402_50V8C
4.7P_0402_50V8C
4.7P_0402_50V8C
4.7P_0402_50V8C
MI@
MI@
E
E
E
E
MI@
MI@
W1
W1
STZ
R
M
D
P
D
VDD
D
MOS
P
VDD
D
VDD
D
PIO0
G
VDD
A
DD18
V
hermal pad
T
M
D_D2/MS_D5/SB13
S
D_D3/MS_D4/SB12
S
D CMD/SD_CMD
S
D CLK/SD_CLK
S
D_CDZ
S
D_D0/MS_D6/SB9
S
D_D1/MS_D7/SB8
S
S BS/MS_BS
M
D_WP/MS_D1/SB5
S
D_D4/MS_D0/SB4
S
D_D5/MS_D2/SB3
S
D_D6/MS_D3/SB1
S
D_D7/MS_CLK/SB0
S
S_INS
Close to IC
1
C
C
W7
W7
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2
2
2
F
or EMI request
(Place close to connector)
12
L
L
@EMI@
@EMI@
1
L
1
L
12
L
12
L
5
17
16
15
14
21
13
12
11
10
9
8
7
6
W6BLM15BD121SN1D_0402
W6BLM15BD121SN1D_0402
W1BLM15BD121SN1D_0402 EMI@LW1BLM15BD121SN1D_0402 EMI@
W2BLM15BD121SN1D_0402 EMI@LW2BLM15BD121SN1D_0402 EMI@
W3BLM15BD121SN1D_0402 EMI@LW3BLM15BD121SN1D_0402 EMI@
W4BLM15BD121SN1D_0402 EMI@LW4BLM15BD121SN1D_0402 EMI@
F
or EMI request
(Place close to chip)
S
D_DATA2
S
D_DATA3
S
DCMD
S
DCLK
S
DCD#
BLM15BD121SN1D_0402
D_DATA0
D_DATA1
DWP
BLM15BD121SN1D_0402
S
S
S
Power saving mode
+
VCC_3IN1
3
0mil
S
DCMD
S
D_DATA0
S
D_DATA1
S
D_DATA2
S
D_DATA3
W5
W5
L
L
2
1
EMI@
EMI@
NC (default)
S
DCLK_R
2
C
C
W9
W9
4.7P_0402_50V8J
4.7P_0402_50V8J
EMI@
EMI@
1
10K pull down
N
ormal modeGPIO0
F
or normal close type connector invert circuit
+
W3
W3
R
R
100K_0402_5%
100K_0402_5%
S
DCD
3VS_CR
1
2
2
W1A
W1A
Q
Q
2
G
G
S
DCD#
61
D
D
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
S
S
T
T
T
itle
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
Date: Sheet
WP_SWCD_SW
P
C
ard Uninsertion
C
ard Insertion
A A
5
Close
O
pen CloseOpen
rotect disable Protect Enable
C
lose
C
lose
4
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
+
3VS_CR
1
W4
W4
R
R
100K_0402_5%
100K_0402_5%
C
C
C
U
U
U
2
S
DWP#
ompal Electronics, Inc.
ompal Electronics, Inc.
ompal Electronics, Inc.
SB-CardReader GL834L
SB-CardReader GL834L
SB-CardReader GL834L
V
V
V
FKAA
FKAA
FKAA
W1B
W1B
Q
Q
5
G
G
1
34
D
D
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
S
S
S
DWP
0
0
0
.2
.2
o
o
o
37 56Monday, March 11, 2013
37 56Monday, March 11, 2013
37 56Monday, March 11, 2013
.2
f
f
f
Page 38
5
SB Sleep & Charge
U
S
tate table for MAX14641
M
EMI@
EMI@
EMI@
EMI@
EMI@
EMI@
ode
AM2
AP1
PM
CM
1
1
4
4
2
2
3
3
2
2
3
3
CB0 STATUS
0
D D
0
1
CB1
0
1
0
1 1
Right rear USB3.0 Conn.
Right rear USB3.0 Conn.
Right rear USB3.0 Conn.Right rear USB3.0 Conn.
R6
R6
L
L
U
SB20_N0<29>
U
SB20_P0<29>
C C
U
3TXDN1<29>
U
3TXDP1<29>
U
3RXDN1< 29>
U
3RXDP1<29>
R14 0.1U_0402_10V7K
R14 0.1U_0402_10V7K
C
C
R15 0.1U_0402_10V7K
R15 0.1U_0402_10V7K
C
C
1 2
1
U
3TXDN1_C
2
U
3TXDP1_C
2
2
3
3
WCM-2012-900T_0805
WCM-2012-900T_0805
R2
R2
L
L
1
1
4
4
KINGCORE WCM-2012HS-670T
KINGCORE WCM-2012HS-670T
L
L
R5
R5
1
1
4
4
KINGCORE WCM-2012HS-670T
KINGCORE WCM-2012HS-670T
4
2A auto-detection charger mode for Apple device.
Resistor dividers are connected to DP/DM. Including DCP
Forced 1A charger mode for Apple devices.
Resistor dividers are connected to DP/DM.
USB pass-through mode.DP/DM are connected to TDP/TDM
USB pass-through mode with CDP emulation.
Auto connects DP/DM to TDP/TDM depending
on CDP detection status.
Right front USB3.0 Conn.
Right front USB3.0 Conn.
Right front USB3.0 Conn.Right front USB3.0 Conn.
(Support S&C function)
(Support S&C function)
(Support S&C function)(Support S&C function)
U
SB20_N0_R
U
SB20_P0_R
U
3RXDN1_L
U
3RXDP1_L
U
3TXDN1_C_L
U
3TXDP1_C_L
U
3TXDN2<29>
U
3TXDP2<29>
U
3RXDN2< 29>
U
3RXDP2<29>
1 2
R16 0.1U_0402_10V7K
R16 0.1U_0402_10V7K
C
C
1 2
C
C
R17 0.1U_0402_10V7K
R17 0.1U_0402_10V7K
U
3TXDN2_C
U
3TXDP2_C
3
U
SB20_N1_S
U
SB20_P1_S
C
HG_PWR_GATE#<41>
S
LP_CHG_CB1<29>
R7
EMI@
R7
EMI@
L
L
2
2
3
3
WCM-2012-900T_0805
WCM-2012-900T_0805
R3
R3
L
L
1
1
4
4
KINGCORE WCM-2012HS-670T
KINGCORE WCM-2012HS-670T
R4
R4
L
L
1
1
4
4
KINGCORE WCM-2012HS-670T
KINGCORE WCM-2012HS-670T
EMI@
EMI@
EMI@
EMI@
1
1
4
4
2
2
3
3
2
2
3
3
R
R
R2
R2
0_0402_5%
0_0402_5%
U
SB20_N1_R
U
SB20_P1_R
U
3RXDN2_L
U
3RXDP2_L
U
3TXDN2_C_L
U
3TXDP2_C_L
14641@
14641@
U
SB20_N1_S
U
SB20_P1_S
C
HG_CB1
2
U
U
R2
R2
1
C
2
D
3
D
4
C
9
P
MAX14641ETA-TGH7_TDFN8
MAX14641ETA-TGH7_TDFN8
E
C_SMB_CK1<41,45,46>
E
C_SMB_DA1<41,45,46>
EN
M
P
B1
GND
14641@
14641@
8
C
HG_CB0
C
B0
7
T
DM
6
T
DP
5
V
CC
R2
R2
U
U
A
ddress
0x35
MAX14640ETA+TGH7
MAX14640ETA+TGH7
14640@
14640@
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
14641@
14641@
R
R
R1 0_0 402_5%
R1 0_0 402_5%
+
5VALW
1
R9
R9
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
2
+
R1A
R1A
Q
Q
6 1
14640@
14640@
3 4
14640@
14640@
3VALW
2
4.7K_0402_5%
4.7K_0402_5%
5
R1B2N7002KDWH_SOT363-6
R1B2N7002KDWH_SOT363-6
Q
Q
1
14640@
14640@
S
U
SB20_N1 <29>
U
SB20_P1 <29>
+
3VALW
2
R3
R3
R
R
1
LP_CHG_CB0 <27,29>
R4
R4
R
R
4.7K_0402_5%
4.7K_0402_5%
14640@
14640@
1 2
C
HG_CB1
C
HG_CB0
+
W=80mils
+
5VALW
2
.0A
U
U
R4
R4
2
I
N
3
N
I
U
SB_EN#0< 41>
B B
3
3
D
D
@ESD@
@ESD@
1
U
3TXDP1_C_L
2
U
3TXDN1_C_L
4
U
3RXDP1_L
5
U
3RXDN1_L
3
TVWDF1004AD0_DFN 9
TVWDF1004AD0_DFN 9
A A
4
N/ENB
E
1
G
ND
SY6288DCAC_MSOP8
SY6288DCAC_MSOP8
S
A00004KB00
SA00003TV00
9
U
3TXDP1_C_L
8
U
3TXDN1_C_L
7
U
3RXDP1_L
6
U
3RXDN1_L
5
+
USB_VCCB
6
UT
O
7
UT
O
8
UT
O
5
CB
O
+
USB_VCCB
U
SB_OC#0 <29,41>
U
3TXDP1_C_L
U
3TXDN1_C_L
U
3RXDP1_L
U
3RXDN1_L
U
SB20_P0_R
U
SB20_N0_R
USB_VCCB
1
2
47U_0805_6.3V6M
47U_0805_6.3V6M
4
0.1U_0402_10V7K
0.1U_0402_10V7K
1
R13
R13
C
C
C
C
R12
R12
2
USBR
USBR
J
J
9
tdA-SSTX+
S
8
tdA-SSTX-
S
7
ND-DRAIN
G
6
tdA-SSRX+
S
5
tdA-SSRX-
S
4
ND
G
3
+
D
2
-
D
1
BUS
V
LOTES_AUSB0015-P001A
LOTES_AUSB0015-P001A
1000P_0402_50V7K
1000P_0402_50V7K
1
C
C
@EMI@
@EMI@
2
Conn@
Conn@
13
ND
G
12
ND
G
11
ND
G
10
ND
G
+
5VALW
2
.5A
R3
R3
U
U
2
I
N
3
I
N
R39
R39
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
U
SB_CHG_EN#<41>
U
3TXDP2_C_L
U
3TXDN2_C_L
U
3RXDP2_L
U
3RXDN2_L
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
3
4
E
N/ENB
1
G
ND
SY6288DCAC_MSOP8
SY6288DCAC_MSOP8
S
A00006DN00
R4
R4
D
D
@ESD@
@ESD@
1
2
4
5
3
TVWDF1004AD0_DFN 9
TVWDF1004AD0_DFN 9
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
W=100mils
+
USB_VCCA
6
O
UT
7
O
UT
8
O
UT
5
O
CB
9
U
3TXDP2_C_L
8
U
3TXDN2_C_L
7
U
3RXDP2_L
6
U
3RXDN2_L
U
SB_CHG_OC# <26,29,41>
+
USB_VCCA
2
+
USB_VCCA
W=100milsW=80mils
0.1U_0402_10V7K
0.1U_0402_10V7K
12
R10
R10
C
C
47U_0805_6.3V6M
47U_0805_6.3V6M
U
3TXDP2_C_L
U
3TXDN2_C_L
U
3RXDP2_L
U
3RXDN2_L
U
SB20_P1_R
U
SB20_N1_R
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
Title
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
Date: Sheet
ompal Electronics, Inc.
R
R
R
USB30/S&C
USB30/S&C
USB30/S&C
1000P_0402_50V7K
1000P_0402_50V7K
1
R11
R11
C
C
2
USBF
USBF
J
J
9
tdA-SSTX+
S
8
tdA-SSTX-
S
7
ND-DRAIN
G
6
tdA-SSRX+
S
5
tdA-SSRX-
S
4
ND
G
3
+
D
2
-
D
1
BUS
V
LOTES_AUSB0015-P001A
LOTES_AUSB0015-P001A
V
V
V
FKAA
FKAA
FKAA
1
C
C
@EMI@
@EMI@
2
1
R40
R40
Conn@
Conn@
13
ND
G
12
ND
G
11
ND
G
10
ND
G
o
o
o
f
38 56Monday, March 11, 2013
f
38 56Monday, March 11, 2013
f
38 56Monday, March 11, 2013
0
0
0
.2
.2
.2
Page 39
A
U
U
M
IC1_LINE1_R_R
M
IC1_LINE1_R_L
1 1
@ESD@
@ESD@
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
A65
A65
C
C
A
Z_RST_HD#<25>
c
close to pin 28
1 2
C
C
A60 10U_0603_6.3V6M
A60 10U_0603_6.3V6M
1
12
A25
A25
C
C
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2 2
I
NT_MIC_CLK<22>
A55
A55
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
2
lose to pin19
A30 20K_0402_1%
A30 20K_0402_1%
R
R
C
C
C
C
I
NT_MIC_DATA<22>
12
@
@
A34 20K_0402_1%
A34 20K_0402_1%
R
R
F
or EMI reserve
I
NT_MIC_CLK_R
A42
A42
R
R
FBMA-10-100505-301T
FBMA-10-100505-301T
CAM_EMI@
CAM_EMI@
M
IC1_LINE1_R_C_R
C
A584.7U_0603_6.3V6KCA584.7U_0603_6.3V6K
M
IC1_LINE1_R_C_L
A574.7U_0603_6.3V6KCA574.7U_0603_6.3V6K
C
+
MIC1_VREFO_L
+
MIC1_VREFO_R
E
C_MUTE_INT<41>
A
Z_SYNC_HD<25>
12
1 2
A54 2.2U_0402_6.3V6M
A54 2.2U_0402_6.3V6M
1 2
A53 2.2U_0402_6.3V6M
A53 2.2U_0402_6.3V6M
E
C_MUTE#<41>
269@
269@
M
I
NT_MIC_CLK_R
S
S
1 2
22
21
17
16
31
30
29
15
14
20
12
ONO_IN
10
11
10 mil
19
A
C_JDREF
28
L
DO_CAP
27
A
C_VREF
34
C
PVEE
35
C
BN
36
C
BP
2
3
13
ENSE_A
18
ENSE_B
47
4
R
R
A50
A50
4.7K_0402_5%
4.7K_0402_5%
T
o solve S&M noise issue
Internal AMP
E
C_MUTE#
Hight
Enable
LOW
Disable
B
A1
A1
M
IC1_R
IC1_L
M
M
IC2_R
M
IC2_L
M
IC1_VREFO_L
M
IC1_VREFO_R
IC2_VREFO
M
L
INE2_R
INE2_L
L
M
ONO_OUT
P
CBEEP
S
YNC
R
ESET#
DREF
J
L
DO_CAP
V
REF
C
PVEE
C
BN
C
BP
G
PIO0/DMIC_DATA
G
PIO1/DMIC_CLK
S
ENSE_A
ENSE_B
S
E
APD
P
D#
ALC259-VC2-CG_MQFN48_6X6
ALC259-VC2-CG_MQFN48_6X6
259@
259@
D
S
PK_OUT_R+
S
PK_OUT_R-
S
PK_OUT_L+
S
PK_OUT_L-
H
H
S
DATA_OUT
S
T
hermal Pad
D
VDD
VDD_IO
A
VDD1
A
VDD2
P
VDD1
P
VDD2
POUT_R
POUT_L
DATA_IN
B
INE1_L
L
INE1_R
L
A
VSS1
A
VSS2
P
VSS1
P
VSS2
D
VSS
CLK
C
3
5mA for 3.3V level
DVDD
1
+
DVDD
9
+
DVDD
25
+
AVDD
38
+
AVDD
39
+
PVDD
46
+
PVDD
45
S
PKR+
44
S
PKR-
40
S
PKL+
41
S
PKL-
33
H
POUT_R
32
H
POUT_L
5
8
A
Z_SDIN0_HD_R
6
A
Z_BITCLK_HD
23
L
INE1_R_C_L
24
L
INE1_R_C_R
48
N
C
26
37
42
43
7
A
49
D
GND
A19
A19
R
R
A20
A20
R
R
GND
For EMI reserve
close to codec
A
75_0402_1%
75_0402_1%
75_0402_1%
75_0402_1%
2
R
R
A23 33_0402_5%
A23 33_0402_5%
269@
269@
2
1
A9 0.1U_0402_10V6K
A9 0.1U_0402_10V6K
C
C
269@
269@
1 2
A10 0.1U_0402_10V6K
A10 0.1U_0402_10V6K
C
C
Z_BITCLK_HD
lose to pin1
c
c
lose to pin9
H
P_R <40>
H
P_L <40>
1
M
IC1_LINE1_R_L
M
IC1_LINE1_R_R
F
@EMI@
@EMI@
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
A
A
A
or S&M
1
A4110_0402_5%
A4110_0402_5%
R
R
10P_0402_50V8J
10P_0402_50V8J
+
1
A4
A4
C
C
2
1
A45
A45
C
C
2
Z_SDOUT_HD <25>
Z_SDIN0_HD <25>
Z_BITCLK_HD <25>
A51
A51
C
C
2
1
@EMI@
@EMI@
1 2
Rshort@
Rshort@
A22 0_0402_5%
A22 0_0402_5%
R
R
1
A3
A3
C
C
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2
For P/N and footprint
Please place them to ISPD page
A1
A1
U
U
ALC269Q-VB6-CG
ALC269Q-VB6-CG
269@
269@
1
Rshort@
Rshort@
A44 0_0603_5%
A44 0_0603_5%
R
R
1 2
Rshort@
Rshort@
A43 0_0603_5%
A43 0_0603_5%
R
R
1 2
Rshort@
Rshort@
A39 0_0603_5%
A39 0_0603_5%
R
R
1 2
Rshort@
Rshort@
A38 0_0603_5%
A38 0_0603_5%
R
R
1
Rshort@
Rshort@
A31 0_0603_5%
A31 0_0603_5%
R
R
+
3VS
D
6
40 mil20 mil
lose to pin 25 clo se to pin 38
c
AVDD
+
C
C
A42
A42
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
c
lose to pin39
0.1U_0402_10V7K
0.1U_0402_10V7K
c
lose to pin46
50mA for 5V level
0.1U_0402_10V7K
0.1U_0402_10V7K
2
1
C
C
A47
A47
C
C
C
A33
A33
C
C
A32
A32
2
C
10U_0603_6.3V6M
10U_0603_6.3V6M
6
0 mil
+
PVDD
1
2
1
2
1
A37
A37
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
C
C
A50
A50
2
1
2
1
C
C
A35
A35
10U_0603_6.3V6M
10U_0603_6.3V6M
E
1 2
Rshort@
Rshort@
R
R
A18
A18
0_0603_5%
0_0603_5%
1 2
A24
A24
R
R
0_0603_5%
0_0603_5%
Rshort@
Rshort@
+
5VALW
+
5VALW
Sleep and Music
259@
2
2
269@
No
Yes
S
B
eep sound
PCI Beep
P
CH_SPKR<25>
3 3
Sense Pin Impedance
39.2K
SENSE A
4 4
20K
10K
5.1K
39.2K
20K
10K
A
A52
A52
R
R
2
1
47K_0402_5%
47K_0402_5%
R
R
A49
A49
4.7K_0402_5%
4.7K_0402_5%
Codec Signals
PORT-I (PIN 32, 33)
PORT-B (PIN 21, 22)
PORT-C (PIN 23, 24)
(PIN 48)
PORT-E (PIN 14, 15)
PORT-F (PIN 16, 17)SENSE B
PORT-H (PIN 20)
2
1
Headphone out
Ext. MIC
C
C
A70
A70
1 2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
A27
A27
C
C
100P_0402_50V8J
100P_0402_50V8J
2
For better sound
by customer request
Function
M
ONO_IN
B
PK
2W 4ohm =40mil For EMI reserve
1W 8ohm =20mil
S
S
S
S
close to codec
PKL+
PKL-
PKR+
PKR-
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
1 2
Rshort@
Rshort@
A7 0_0603_5%
A7 0_0603_5%
R
R
1 2
Rshort@
Rshort@
A8 0_0603_5%
A8 0_0603_5%
R
R
1000P_0402_50V7K
1000P_0402_50V7K
2
1
Rshort@
Rshort@
R
R
A9 0_0603_5%
A9 0_0603_5%
2
1
Rshort@
Rshort@
R
R
A10 0_0603_5%
A10 0_0603_5%
1000P_0402_50V7K
1000P_0402_50V7K
C
@EMI@
@EMI@
@EMI@
@EMI@
S
PK_L1 <40>
S
1
1
C
C
A31
A31
2
2
1
1
C
C
A34
A34
2
2
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
PK_L2 <40>
C
C
A30
A30
1000P_0402_50V7K
1000P_0402_50V7K
@EMI@
@EMI@
S
PK_R1 <40>
S
PK_R2 <40>
C
C
A36
A36
1000P_0402_50V7K
1000P_0402_50V7K
@EMI@
@EMI@
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
M
IC/LINE IN
M
M
S
M_SENSE#<41>
E
C
D
IC1_LINE1_R_R
IC1_LINE1_R_L
+
3VL
A47
A47
R
R
1K_0402_5%
1K_0402_5%
2
1
2
1
1K_0402_5%
1K_0402_5%
R
R
A45
A45
M
IC_SENSE
Q
Q
A1A
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
R
R
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
A1A
269@
269@
A35 100K_0402_5%
A35 100K_0402_5%
A1B
A1B
Q
Q
269@
269@
p
lace close to chip
M
IC_SENSE
N
BA_PLUG<40>
T
T
T
itle
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
Date: Sheet
12
+
12
269@
269@
MIC1_VREFO_R
+
MIC1_VREFO_L
S
ENSE_A
E
R
R
A48 2.2K_0402_5%
A48 2.2K_0402_5%
2
1
A46 2.2K_0402_5%
A46 2.2K_0402_5%
R
R
61
R
R
A29
A29
100K_0402_5%
100K_0402_5%
2
34
5
A32 20K_0402_1%
A32 20K_0402_1%
R
R
A33 39.2K_0402_1%
A33 39.2K_0402_1%
R
R
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
ompal Electronics, Inc.
H
H
H
DA-ALC259-VC/269-VB
DA-ALC259-VC/269-VB
DA-ALC259-VC/269-VB
R
R
A37
A37
0_0402_5%
0_0402_5%
259@
259@
M
IC1_R <40>
M
IC1_L <40>
39 56Monday, March 11, 2013
39 56Monday, March 11, 2013
39 56Monday, March 11, 2013
J
ACK_SENSE <40>
o
o
o
f
f
f
Page 40
PK Conn.
S
or common design,
F
pull-high resistor should be placed at connector side.
R
R
A95
A95
10K_0402_5%
10K_0402_5%
S
PK_R1<39>
S
PK_R2<39>
SPK_L1<39>
SPK_L2<39>
SPK_DET<30>
HeadPhone/LINE Out JACK
2
1
Rshort@
HP_L<39>
HP_R<39>
Rshort@
R
R
A54 0_0402_5%
A54 0_0402_5%
1 2
Rshort@
Rshort@
R
R
A53 0_0402_5%
A53 0_0402_5%
YSDA0502C_SOT23-3
YSDA0502C_SOT23-3
@ESD@
@ESD@
S
+
3VS
SM_DET
(GPIO48)
BIOS setup
1
J
J
SPK
SPK
8
G
ND
7
G
1 2
HP_R_L
HP_R_R
2
3
D
D
A6
A6
1
ND
6
6
5
5
4
4
3
3
2
2
1
1
ACES_50228-0067N-001
ACES_50228-0067N-001
Conn@
Conn@
A11100P_0 402_50V8J
A11100P_0 402_50V8J
A12100P_0 402_50V8J
A12100P_0 402_50V8J
C
C
C
C
1
1
2
2
@EMI@
@EMI@
@EMI@
@EMI@
NBA_PLUG<39>
0
Non-Harman detection
0
SPK_DET
(GPIO70)
ONKYO
Non-Brand1
J
J
LINE
Conn@
LINE
Conn@
6
1
2
3
4
5
TYCO_2041280-1_3.6D
TYCO_2041280-1_3.6D
peaker Type
Harman/KardonS&M option
Non Harman
BOM
269@
259@
MIC/LINE IN JACK
MIC1_L<39>
MIC1_R<39>
1 2
R
R
A56 0_0402_5%
A56 0_0402_5%
1 2
R
R
A55 0_0402_5%
A55 0_0402_5%
Rshort@
Rshort@
Rshort@
Rshort@
D
@ESD@
@ESD@
D
YSDA0502C_SOT23-3
YSDA0502C_SOT23-3
J
J
EXMIC
Conn@
EXMIC
Conn@
6
1
MIC1_R_L
MIC1_R_R
JACK_SENSE<39>
A13100P_0402_50V8J
A13100P_0402_50V8J
A14100P_0402_50V8J
A14100P_0402_50V8J
1
1
C
C
C
2
3
A7
A7
1
C
+
3VL
2
2
@EMI@
@EMI@
@EMI@
@EMI@
R
R
A40
A40
4.7K_0402_5%
4.7K_0402_5%
269@
269@
2
3
4
5
TYCO_2041280-1_3.6D
TYCO_2041280-1_3.6D
R
R
A36
A36
0_0402_5%
0_0402_5%
259@
259@
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
T
itle
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
ompal Electronics, Inc.
A
A
A
UDIO CONN
UDIO CONN
UDIO CONN
M
M
M
onday, March 11, 2013
onday, March 11, 2013
onday, March 11, 2013
4
o
4
4
o
o
f
0 56
f
0 56
f
0 56
0
0
0
.2
.2
.2
Page 41
A
B1
B1
C
C
0.1U_0402_10V7K
F
or RF
C
LK_PCI_EC
12
R
R
B3
B3
22_0402_5% @RF@
22_0402_5% @RF@
1 1
10P_0402_50V8J
10P_0402_50V8J
3VL
+
3VL
+
2 2
3VL
+
3VS
+
3 3
1
B11
@RF@
B11
@RF@
C
C
2
B2
B2
R
R
47K_0402_5%
47K_0402_5%
2
1
1 2
B12 0.1U_0402_10V7K
B12 0.1U_0402_10V7K
C
C
ESD@
ESD@
1 2
B13 100P_0402_50V8J
B13 100P_0402_50V8J
C
C
2
1
R
R
B11 10K_0402_5%
B11 10K_0402_5%
PB1
PB1
R
R
1 8
2 7
6
3
4 5
2.2K_8P4R_5%
2.2K_8P4R_5%
B27
B27
R
R
100K_0402_5%
100K_0402_5%
1 2
1 2
B12 4.7K_0402_5%
B12 4.7K_0402_5%
R
R
E
C_RST#
P
LT_RST#
C
HG_PWR_GATE#
E
C_SMB_CK1
E
C_SMB_DA1
E
C_SMB_CK2
E
C_SMB_DA2
E
51_TXD
E
C_MUTE_INT_R
K
SI[0..7]<42>
K
SO[0..15]<42>
C_MUTE_INT<39>
E
C
0.1U_0402_10V7K
G
ATEA20<30>
K
B_RST#<30>
S
ERIRQ<25>
L
PC_FRAME#<25>
L
PC_AD3<25>
L
PC_AD2<25>
L
PC_AD1<25>
L
PC_AD0<25>
C
LK_PCI_EC<29>
P
LT_RST#<29,35,36,5>
E
C_SCI#<30>
OWL_EN#<35>
W
K
SI[0..7]
K
SO[0..15]
HG_PWR_GATE#<38>
C
E
C_SMB_CK1<38,45,46>
E
C_SMB_DA1<38,45,46>
E
C_SMB_CK2<13,26,34>
E
C_SMB_DA2<13,26,34>
P
M_SLP_S3#<27>
M_SLP_S5#<27>
P
E
C_SMI#<27,30>
SB_OC#2<29,36>
U
SB_CHG_OC#<26,29,38>
U
U
SB_CHG_EN#<38>
SB_EN#2<36>
U
K
F
AN_SPEED1<5>
W
L_OFF#<35>
E
51_TXD<35>
E
51_RXD<35>
M_PWROK<27>
P
B
M_SENSE#<39>
S
LK_EC<27>
P
R
OK<27,47>
R
R
C
E
E
E
E
B_LED<42>
T_ON<35>
B37 0_0402_5%
B37 0_0402_5%
R
R
2
1
Rshort@
Rshort@
2
1
B13 0_0402_5%@RB13 0_0402_5%@
1 2
B14 0_0402_5%
B14 0_0402_5%
100K_0402_5%
100K_0402_5%
1
1
2
2
E
C_RST#
K
SI0
K
SI1
K
SI2
K
SI3
K
SI4
K
SI5
K
SI6
K
SI7
K
SO0
K
SO1
K
SO2
K
SO3
K
SO4
K
SO5
K
SO6
K
SO7
K
SO8
K
SO9
K
SO10
K
SO11
K
SO12
K
SO13
K
SO14
K
SO15
HG_PWR_GATE#
C_SMB_CK1
C_SMB_DA1
C_SMB_CK2
C_SMB_DA2
E
51_TXD
E
C_MUTE_INT_R
P
OK_R
12
B22
B22
R
R
@
@
B
B2
B2
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
U
B1
B1
U
1
G
2
K
3
S
4
L
5
L
7
L
8
L
10
L
12
C
13
P
37
E
20
E
38
G
55
K
56
K
57
K
58
K
59
K
60
K
61
K
62
K
39
K
40
K
41
K
42
K
43
K
44
K
45
K
46
K
47
K
48
K
49
K
50
K
51
K
52
K
53
K
54
K
81
K
82
K
77
E
78
E
79
E
80
E
6
P
14
P
15
E
16
G
17
G
18
G
19
G
25
E
28
F
29
E
30
E
31
E
32
P
34
S
36
N
122
X
123
X
1
B16
B16
C
C
20P_0402_50V8
20P_0402_50V8
@
@
2
+
3VL
ATEA20/GPIO00
BRST#/GPIO01
ERIRQ
PC_FRAME#
PC_AD3
PC_AD2
PC_AD1
PC & MISC
PC & MISC
L
L
PC_AD0
LK_PCI_EC
CIRST#/GPIO05
C_RST#
C_SCII#/GPIO0E
PIO1D
SI0/GPIO30
SI1/GPIO31
SI2/GPIO32
SI3/GPIO33
SI4/GPIO34
SI5/GPIO35
SI6/GPIO36
SI7/GPIO37
SO0/GPIO20
SO1/GPIO21
SO2/GPIO22
SO3/GPIO23
SO4/GPIO24
nt. K/B
nt. K/B
I
I
SO5/GPIO25
Matrix
Matrix
SO6/GPIO26
SO7/GPIO27
SO8/GPIO28
SO9/GPIO29
SO10/GPIO2A
SO11/GPIO2B
SO12/GPIO2C
SO13/GPIO2D
SO14/GPIO2E
SO15/GPIO2F
SO16/GPIO48
SO17/GPIO49
C_SMB_CK1/GPIO44
C_SMB_DA1/GPIO45
C_SMB_CK2/GPIO46
C_SMB_DA2/GPIO47
M_SLP_S3#/GPIO04
M_SLP_S5#/GPIO07
C_SMI#/GPIO08
PIO0A
PIO0B
PIO0C
PIO0D
C_INVT_PWM/GPIO11
AN_SPEED1/GPIO14
C_PME#/GPIO15
C_TX/GPIO16
C_RX/GPIO17
CH_PWROK/GPIO18
USP_LED#/GPIO19
UM_LED#/GPIO1A
CLKI/GPIO5D
CLKO/GPIO5E
9
22
33
C_VDD/VCC
C_VDD/VCC
E
E
PWM Output
PWM Output
DA Output
DA Output
PS2 Interface
PS2 Interface
SPI Device Interface
SPI Device Interface
SM Bus
SM Bus
GPIO
GPIO
ND/GND
G
11
24
+
3VL
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2
111
67
96
125
C_VDD0
E
C_VDD/VCC
C_VDD/VCC
C_VDD/VCC
E
E
C_VDD/AVCC
E
E
AD Input
AD Input
C
PU1.5V_S3_GATE/GPXIOA00
V
SPI Flash ROM
SPI Flash ROM
B
ATT_CHG_LED#/GPIO52
GPIO
GPIO
B
ATT_LOW_LED#/GPIO55
P
E
C_RSMRST#/GPXIOA03
E
C_LID_OUT#/GPXIOA04
P
ROCHOT_IN/GPXIOA05
H
_PROCHOT#_EC/GPXIOA06
V
COUT0_PH/GPXIOA07
GPO
GPO
P
BTN_OUT#/GPXIOA09
P
CH_APWROK/GPXIOA10
S
A_PGOOD/GPXIOA11
GPI
GPI
P
ECI_KB9012/GPXIOD07
ND/GND
ND/GND
ND/GND
ND0
GND/AGND
G
G
A
G
G
35
69
94
113
C
B3
B3
C
C
21
PIO0F
G
PIO12
G
G
PIO39
G
PIO3B
G
PIO42
REF/GPIO3E
PIDI/GPIO5B
G
PXIOD06
V
B1
B1
23
26
27
63
64
65
66
75
76
68
70
71
72
83
84
85
86
87
88
97
98
99
109
119
120
126
128
73
74
89
90
91
92
93
95
121
127
100
101
102
103
104
105
106
107
108
110
112
114
115
116
117
118
124
18R
B
EEP#/GPIO10
A
COFF/GPIO13
B
ATT_TEMP/GPIO38
A
DP_I/GPIO3A
I
MON/GPIO43
D
AC_BRIG/GPIO3C
E
N_DFAN1/GPIO3D
I
C
HGVADJ/GPIO3F
E
C_MUTE#/GPIO4A
U
SB_EN#/GPIO4B
C
AP_INT#/GPIO4C
E
APD/GPIO4D
T
P_CLK/GPIO4E
T
P_DATA/GPIO4F
W
OL_EN/GPXIOA01
M
E_EN/GPXIOA02
CIN0_PH/GPXIOD00
S
S
PIDO/GPIO5C
S
PICLK/GPIO58
S
PICS#/GPIO5A
E
NBKL/GPIO40
P
ECI_KB930/GPIO41
F
STCHG/GPIO50
C
APS_LED#/GPIO53
P
WR_LED#/GPIO54
S
YSON/GPIO56
V
R_ON/GPIO57
M_SLP_S4#/GPIO59
B
KOFF#/GPXIOA08
A
C_IN/GPXIOD01
E
C_ON/GPXIOD02
O
N/OFF/GPXIOD03
L
ID_SW#/GPXIOD04
S
USP#/GPXIOD05
KB9012QF-A3_LQFP128_14X14
KB9012QF-A3_LQFP128_14X14
9012@
9012@
U
U
NPCE885NB0DX LQFP 128P
NPCE885NB0DX LQFP 128P
885@
885@
B
ATT_PRES
8
85_EC_ON
T
P_CLK
T
P_DATA
W
LAN_WAKE#
S
YSON
V
R_ON
F
B_CLAMP_R
H
_PROCHOT#_EC
V
COUT0_PH_L
A
CIN_D
E
C_ON_R
L
ID_SW#
S
USP#
+
VTT_EC
E
C_PECI
+
EC_V18R
1
C
C
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2
L_BT_LED# <42>
W
U
SB_EN#0 <38>
ANPWM <5>
F
C
LK_REQ_GC6# <13>
B
ATT_PRES <45>
SB_OC#0 <29,38>
U
A
DP_I <45,46>
DP_V <46>
A
DPLOCK <34>
H
C_ENBKL <22,28>
E
E
C_MUTE# <3 9>
P
M_SLP_S4# <27>
T
P_CLK <42 >
T
P_DATA <42>
2
1
Rshort@
Rshort@
R
R
B5 0_0402_5%
B5 0_0402_5%
P
B
S
O
N/OFFBTN# <42>
L
ID_SW# <42>
S
USP# <43,48,49>
B15
B15
DPINT <34>
H
P
CH_SUSPWRDN # <27>
USACK# <27>
S
R
eserve this signal to EC by SW demand
2011/10/18a
V
GATE <27,51>
PS_DOWN# <13>
G
P
WRME_CTRL <25>
V
CIN0_PH <45>
C_SDIO <25>
E
C_SDI <25>
E
C_SCK <25>
E
C_CS0# <25>
E
LAN_WAKE# <35>
W
OL_EN# <36>
W
DPACT <34>
H
B
ATT_FULL_LED# <42>
APS_LED# <42>
C
WR_SUSP_LED# <42>
P
B
ATT_CHG_LOW_LED# <42>
S
YSON <48>
V
R_ON <51>
P
CH_RSMRST# <27>
E
C_LID_OUT# <30>
ROCHOT_IN <45>
KOFF# <22>
P
BTN_OUT# < 27>
CH_PWR_EN < 43>
P
A_PGOOD <50>
B4 0_0402_5 %
B4 0_0402_5 %
R
R
B19 43_0402_5%
B19 43_0402_5%
R
R
V
CIN0_PH connect to
power portion ( 9012 only)
B_CLAMP <13,14,17>
F
P
ROCHOT_IN connect
to power portion (9012 only)
2
1
885@
885@
1 2
D
V
R_HOT#<51>
1.05VS_VCCP
+
_PECI <5>
H
1 2
Rshort@
Rshort@
B1 0_0402_5 %
B1 0_0402_5 %
R
R
H
_PROCHOT#_EC
2N7002KW_SOT323-3
2N7002KW_SOT323-3
B
ATT_PRES
A
CIN_D
H
_PROCHOT#_EC
L
ID_SW#
W
LAN_WAKE#
T
P_CLK
T
P_DATA
S
YSON
S
USP#
V
R_ON
V
COUT0_PH_L
VCOUT0_PH connect to power portion (9012 only)
A
CIN_D
2
G
G
Q
Q
B1
B1
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
1 2
R
R
B34 0_0402_5%
B34 0_0402_5%
13
D
D
S
S
@
@
1 2
B9 100P_0402_50V8J
B9 100P_0402_50V8J
C
C
1 2
B10 100P_0402_50V8J
B10 100P_0402_50V8J
C
C
1 2
@
@
B6 10K_040 2_5%
B6 10K_040 2_5%
2
1
B35 47K_0402_5%
B35 47K_0402_5%
1 2
B7 10K_040 2_5%
B7 10K_040 2_5%
1 2
B8 4.7K_0402_5%
B8 4.7K_0402_5%
1 2
B9 4.7K_0402_5%
B9 4.7K_0402_5%
1 2
B10 4.7K_0402_5%
B10 4.7K_0402_5%
1 2
B21 10K_0402_5%
B21 10K_0402_5%
1 2
B23 10K_0402_5%
B23 10K_0402_5%
Rshort@
Rshort@
B18
B18
R
R
330K_0402_5%
330K_0402_5%
2
1
D
1
B8
B8
C
C
47P_0402_50V8J
47P_0402_50V8J
2
3VS
+
+
3VS
+
3VL
+
12
B1RB751V40_SC76-2DB1RB751V40_SC76-2
Close to EC
@ESD@
@ESD@
1 2
B14 180P_0402_50V8J
B14 180P_0402_50V8J
C
C
S
USP#
E
3VL
V
S_ON <47>
H
_PROCHOT# <5>
A
CIN <27,46>
885@
885@
2
1
R
R
B20 330K_0402_5%
E
C_ON_R
2N7002KW_SOT323-3
4 4
A
Voltage Comparator Pins FOR 9012 A3
V
CIN0 pin109
VCIN1 pin102
V
COUT0 pin104
VCOUT1 pin103
>
1.2V <1.2V
HIGH
(default)
H
IGH
LOW
LOW
(default)
B
2N7002KW_SOT323-3
8
85_EC_ON
1 2
9012@
9012@
B36 0_0402_5%
B36 0_0402_5%
R
R
S
S
1 3
D
D
B2
B2
Q
Q
885@
885@
G
G
2
ecurity Classification
ecurity Classification
ecurity Classification
S
S
S
ssued Date
ssued Date
ssued Date
I
I
I
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
T
T
T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
B20 330K_0402_5%
B24
885@
B24
885@
R
R
2
1
10K_0402_5%
10K_0402_5%
C
C
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
2
2
2
C
3VL
+
C_ON <47>
E
ompal Secret Data
ompal Secret Data
ompal Secret Data
eciphered Date
eciphered Date
eciphered Date
D
D
D
ompal Electronics, Inc.
ompal Electronics, Inc.
ompal Electronics, Inc.
C
C
itle
itle
itle
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
D
Date: Sheet
C
L
L
L
onday, March 11, 2013
onday, March 11, 2013
onday, March 11, 2013
M
M
M
PC-EC-KB9012&NPCE885N
PC-EC-KB9012&NPCE885N
PC-EC-KB9012&NPCE885N
f
1 56
f
1 56
f
1 56
4
4
o
o
4
E
o
.2
.2
.2
0
0
0
Page 42
5
Power Button Conn.
J
J
PWR
PWR
2
112
4
+
3VL
395
395
R
D D
R
100K_04 02_5%
100K_04 02_5%
1 2
O
N/OFFBTN#
O
N/OFFBTN# <41>
3
4
3
5
6
5
778
ACES_50 611-0040N-0 01
ACES_50 611-0040N-0 01
Conn@
Conn@
6
8
O
N/OFFBTN#
4
+
5VS
3
ouchpad Connector
T
TP
Conn@JTP
Conn@
J
16
14
12
10
8
6
4
2
HB_A060 877-SAVR01
HB_A060 877-SAVR01
15
5
6
1
1
13
3
4
1
1
11
1
2
1
1
9
0
1
9
7
8
7
5
6
5
3
4
3
1
2
1
+
T
T
P
P
3VS
P_DATA <41>
P_CLK <41>
M_SMBDATA <11,12,26,3 5>
M_SMBCLK <11,12,26 ,35>
2
1
ESD diode on SB
B
ATT CHARGE /FULL LED
60
60
R
D
D
2 1
HT-F196BP5_ WHITE
+
5VALW
C C
W
hite LED bright when both AC-a daptor is plugg ed in and Batte ry is full char ged
Amber LED brigh t while chargin g battery from AC-adaptor.
Amber LED blink during Critica l Low Battery
HT-F196BP5_ WHITE
D
D
2 1
HT-191UD5_A MBER_0603
HT-191UD5_A MBER_0603
R
24
24
390_040 2_5%
390_040 2_5%
2
1
23
23
1
3
3
R
R
510_040 2_5%
510_040 2_5%
2
B
ATT_FULL_LE D# <41>
B
ATT_CHG_LOW _LED# <41 >
POWER LED
25
25
D
D
+
5VALW
White LED brigh t when system i s power on.
White LED blink when system is sleep mode.
2 1
HT-F196BP5_ WHITE
HT-F196BP5_ WHITE
61
61
R
R
390_040 2_5%
390_040 2_5%
1 2
P
WR_SUS P_LED# <41 >
WLAN/WiMAX LED
L
819
819
R
B B
26
26
D
D
2 1
+
5VS
HT-191UD5_A MBER_0603
HT-191UD5_A MBER_0603
1 2
66
66
R
R
510_040 2_5%
510_040 2_5%
+
5VS
R
10K_040 2_5%
10K_040 2_5%
@
@
3
2
12
6 1
5
Q
Q
157A
157A
2N7002DW -T/R7_SOT363 -6
2N7002DW -T/R7_SOT363 -6
4
@
@
Q
Q
157B 2N700 2DW-T/R7_SO T363-6
157B 2N700 2DW-T/R7_SO T363-6
@
@
W
L_BT_LED# <41>
ED_WIMA X# <35>
Amber LED brigh t while Wireles s and/or WiMAX turns on.
Lid SW
+
3VL
21
21
U
U
APX9132 ATI-TRL_SOT23-3
APX9132 ATI-TRL_SOT23-3
2
A A
1
2
5
V
453
453
C
C
0.1U_040 2_10V7K
0.1U_040 2_10V7K
DD
OUT
V
ND
G
1
10P_040 2_50V8J
10P_040 2_50V8J
3
C
C
L
ID_SW# <41>
1
@
@
452
452
2
Keyboard LED
10K_040 2_5%
10K_040 2_5%
K
B_LED<41>
KEYBOARD CONN.
K
SI[0..7]
K
K
SO[0..15 ]
4
SI[0..7] <41>
K
SO[0..15 ] <41>
E
C Reset
E
NLDO<47>
2
G
G
R
R
KBL@
KBL@
C
587
587
APS_LED #<41>
+
5VS
3
12
1
D
D
Q
Q
2N7002K W_SOT323-3
2N7002K W_SOT323-3
KBL@
KBL@
S
S
3
Q
Q
38
38
AO3413_ SOT23
AO3413_ SOT23
D
S
D
S
G
G
2
52
52
+
3VS
TJG-533-V-T/R_6 P
TJG-533-V-T/R_6 P
3
4
KBL@
KBL@
1
376 300_0 402_5%
376 300_0 402_5%
R
R
W4
W4
S
S
5
6
+
5VS_LED
2
1
2
1
+
5VS_LED
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
3
SI1
SI6
SI5
SI0
SI4
SI3
SI2
SI7
SO15
SO12
SO11
SO10
SO9
SO8
SO13
SO7
SO6
SO14
SO5
SO3
SO4
SO0
SO1
SO2
S
crew Hole
1
1
2
2
H
H
H
H
H_4P6
BLG Conn@
BLG Conn@
J
J
1
1
2
2
3
3
4
4
5
ND
G
6
ND
G
ACES_50 578-0040N-0 01
ACES_50 578-0040N-0 01
KB
KB
J
J
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
1
0
11
1
1
12
1
2
13
1
3
14
1
4
15
1
5
16
1
6
17
1
7
18
1
8
19
1
9
20
2
0
21
2
1
22
2
2
23
2
3
24
2
4
25
2
5
26
2
6
27
2
7
28
2
8
29
2
9
30
3
0
31
3
1
32
3
2
33
3
3
34
3
4
35
G
ND1
36
G
ND2
CVILU_CF1 7341U0R0-NH
CVILU_CF1 7341U0R0-NH
Conn@
Conn@
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL
HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL
HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
I
H_4P6
@
@
1
7
7
H
H
H
H
6
6
H_3P0
H_3P0
@
@
1
1
H
H
12
12
H
H
13
13
H_3P0
H_3P0
@
@
1
1
SPD
P
CH
U
U
H1
HM76R1@
H1
HM76R1@
S
S
A00005FHA0
A00005FHA0
BD82HM76 SLJ8E C1
BD82HM76 SLJ8E C1
U
U
H1
HM70R1@
H1
HM70R1@
S
S
A00005MQ50
A00005MQ50
BD82HM70 SJTNV C1
BD82HM70 SJTNV C1
Z
Z
ZZ
ZZ
D
D
AZ0WG00100
AZ0WG00100
PCB LA-98 63P
PCB LA-98 63P
C
C
C
ompal Secret Data
ompal Secret Data
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
ompal Secret Data
H_4P6x4P2
H_4P6x4P2
@
@
1
H_4P0
H_4P0
@
@
H_3P0
H_3P0
@
@
D
D
D
eciphered Date
eciphered Date
eciphered Date
2
H
H
3
3
H_4P2
H_4P2
@
@
1
P
TH
8
8
9
9
H
H
H
H
H_3P2
H_3P2
H_3P0
H_3P0
@
@
@
@
1
1
15
15
14
14
H
H
H
H
H_3P0
H_3P0
H_7P0
H_7P0
@
@
@
@
1
1
P
CB Fedical Mark PAD
D1
D1
F
F
F
F
@
@
@
@
1
(
Default)
HM76R3@
BD82HM76 SLJ8E C1
SA00005FHE0
U
U
H1
HM70R3@
H1
HM70R3@
S
S
A00005MQC0
A00005MQC0
BD82HM70 SJTNV C1
BD82HM70 SJTNV C1
H
H
10
10
H
H
H_3P0
H_3P0
@
@
1
17
17
H
H
H_3P2
H_3P2
@
@
1
D2
D2
F
F
F
F
D3
D3
@
@
@
@
1
1
4
4
1
D4
D4
1
VGA standoffCPU
H_3P3
H_3P3
@
@
H
H
H
H
W
LAN standoff
N
PTH
19
19
H
H
H_3P2N
H_3P2N
@
@
1
11
11
1
18
18
1
H_3P0
H_3P0
@
@
H_3P2x3P7
H_3P2x3P7
@
@
5
5
H
H
H_3P3
H_3P3
@
@
1
GPU
V1
N14PGV2 R1@
V1
N14PGV2 R1@
U
U
A00006DO00
A00006DO00
S
S
N14P-GV2 -S-A1 FCBGA
N14P-GV2 -S-A1 FCBGA
U
U
V1
N14MGLR1 @
V1
N14MGLR1 @
S
S
A000069000
A000069000
N14M-GL-S-A 2 FCBGA
N14M-GL-S-A 2 FCBGA
T
T
T
itle
itle
itle
T
T
T
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
M
M
M
onday, March 11, 2013
onday, March 11, 2013
onday, March 11, 2013
Date: Sheet
Date: Sheet
Date: Sheet
(Default)
N14PGV2R3@
N14P-GV2-S-A1
SA00006DO40
V1
N14MGLR3 @
V1
N14MGLR3 @
U
U
A000069010
A000069010
S
S
N14M-GL-S-A 2 FCBGA
N14M-GL-S-A 2 FCBGA
C
ompal Electronics, Inc.
P/ISPD/KB/LED/Screw
P/ISPD/KB/LED/Screw
P/ISPD/KB/LED/Screw
V
V
V
FKAA
FKAA
FKAA
1
H
H
29
29
H_3P3
H_3P3
@
@
1
0
0
0
.2
.2
4
4
4
2 56
2 56
2 56
.2
o
o
o
f
f
f
Page 43
A
+5VALW TO +5VS
+3VALW TO +3VS
Load switch
1 1
2 2
+
5VALW
B
IN 5V and 3.3V (VBIAS=5V),IMAX (per channel)=6A,Rds=18mohm
V
1
1
C
C
1
@
@
1
1
U_0402_6.3V6K
U_0402_6.3V6K
+
5VALW
2
+
3VALW
1
10
10
C
@ C
@
1
1
U_0402_6.3V6K
U_0402_6.3V6K
2
S
USP#
S
USP#
885@R5546
885@
10K_0402_5%
10K_0402_5%
P
CH_PWR_EN<41>
1
1
U
U
1
IN1
V
2
IN1
V
3
N1
O
4
BIAS
V
5
N2
O
6
IN2
V
7
IN2
V
TPS22966DPUR_SON14_2X3
TPS22966DPUR_SON14_2X3
+
3VL
5546
R
1 2
2
G
G
OUT1
V
OUT1
V
C
ND
G
C
OUT2
V
OUT2
V
PAD
G
+
5527
5527
Q
Q
14
13
12
T1
11
10
T2
9
8
15
5VALW
2
5545
5545
R
R
10K_0402_5%
10K_0402_5%
1
P
13
D
D
2N7002KW_SOT323-3
2N7002KW_SOT323-3
S
S
CH_PWR_EN#
C
C
C
2 180P_0402_50V8J
2 180P_0402_50V8J
1 2
C
C
9 330P_0402_50V7K
9 330P_0402_50V7K
2
1
P
CH_PWR_EN# <31,32>
+
3VS
2
@ C
@
1
2N7002KW_SOT323-3
2N7002KW_SOT323-3
D
5VS
+
2
3
3
C
@ C
@
0
0
.1U_0402_10V7K
.1U_0402_10V7K
1
8
8
C
0
0
.1U_0402_10V7K
.1U_0402_10V7K
+
+
1.8VS
2
1
13
D
D
Q
Q
S
S
470
470
R
R
470_0805_5%
470_0805_5%
190
190
2
G
G
5VALW
R
R
422
422
100K_0402_5%
100K_0402_5%
1 2
S
S
USP<9>
S
S
USP
USP#<41,48,49>
USP
6
Q
Q
6A
6A
2
S
USP#
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
1
+
0.75VS
D
D
S
S
E
2
R
R
421
421
22_0805_5%
22_0805_5%
1
13
Q
Q
189
189
2
G
G
2N7002KW_SOT323-3
2N7002KW_SOT323-3
+
2
S
USP
G
G
2N7002KW_SOT323-3
2N7002KW_SOT323-3
1.05VS_VCCP
2
1
1
Q
Q
60
60
3
R
R
468
468
470_0805_5%
470_0805_5%
D
D
S
S
For S3 CPU Power Saving
V
CCP_PWRGOOD<49,50>
3 3
4 4
A
B
1 2
R
R
158 220K_0402_5%
158 220K_0402_5%
S
USP
0
.75VR_EN
3
Q
Q
6B
6B
5
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
4
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
0
.75VR_EN <48>
+
5VS_ODD
1 2
61
ZPODD@
ZPODD@
C
C
C
ompal Secret Data
ompal Secret Data
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
ompal Secret Data
+
5VS TO +5VS_ODD
R
R
457
457
470_0805_5%ZPODD@
470_0805_5%ZPODD@
Q
Q
53A
53A
2
O
DD_EN#
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
O
DD_EN#<30>
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
Deciphered Date
Deciphered Date
Deciphered Date
D
4
ZPODD@
ZPODD@
+
3VS
5
53B
53B
Q
Q
3
+
5VS
ZPODD@
ZPODD@
R
R
441
441
100K_0402_5%
100K_0402_5%
1 2
+
5VS
2
C
471
ZPODD@C471
ZPODD@
0.1U_0402_10V7K
0.1U_0402_10V7K
1
440
440
R
R
2
1
47K_0402_5%
47K_0402_5%
ZPODD@
ZPODD@
2
AO3413_SOT23
AO3413_SOT23
C
C
217
217
ZPODD@
ZPODD@
0.01U_0402_25V7K
0.01U_0402_25V7K
1
T
T
Title
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
M
M
M
onday, March 11, 2013
onday, March 11, 2013
onday, March 11, 2013
Date: Sheet
Date: Sheet
Date: Sheet
V
gs=-4.5V,Id=3A,Rds<97mohm
ZPODD@
ZPODD@
S
S
1
3
Q
Q
45
45
G
G
2
C
ompal Electronics, Inc.
D
D
D
V
V
V
FKAA
FKAA
FKAA
NONZP@
NONZP@
R
R
D
D
0_0805_5%
0_0805_5%
1
2
C-DC INTERFACE
C-DC INTERFACE
C-DC INTERFACE
E
120
120
+
5VS_ODD
0
0
0
.2
.2
4
4
4
3 56
3 56
3 56
.2
o
o
o
f
f
f
Page 44
A
E
MI Part (47.1)
EMI@
EMI@
P
P
L102
A
51 need add fuse
1 1
@
@
P
P
JP1
JP1
1
1
2
2
3
3
4
4
ACES_50299-00401-001
ACES_50299-00401-001
2 2
P
P
F1
F1
21
7A_32V_S1206-H-7.0A
7A_32V_S1206-H-7.0A
D
C_IN_S1
12
EMI@
EMI@
P
P
C102
C102
1000P_0603_50V7K
1000P_0603_50V7K
L102
FBMA-L11-201209-121LMA50T_0805
FBMA-L11-201209-121LMA50T_0805
1 2
EMI@
EMI@
P
P
L101
L101
FBMA-L11-201209-121LMA50T_0805
FBMA-L11-201209-121LMA50T_0805
1 2
12
EMI@
EMI@
P
P
C103
C103
100P_0603_50V8
100P_0603_50V8
B
1
EMI@
EMI@
P
P
C101
C101
100P_0603_50V8
100P_0603_50V8
2
V
IN
12
EMI@
EMI@
P
P
C104
C104
1000P_0603_50V7K
1000P_0603_50V7K
C
D
For ML1220 RTC (38.2)
P
P
P
BJ101 @
BJ101 @
-
2
+
1
P
P
R101
R101
560_0603_5%
560_0603_5%
1 2
+
RTC_R
P
R102
R102
560_0603_5%
560_0603_5%
1
2
+
RTCBATT
ML1220T13RE
ML1220T13RE
+
RTC
3 3
4 4
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
2
2
2
012/09/24 2013/09/24
012/09/24 2013/09/24
012/09/24 2013/09/24
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
C
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
Title
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
Date: Sheet
ompal Electronics, Inc.
D
D
D
CIN/PRECHARGE
CIN/PRECHARGE
CIN/PRECHARGE
V
V
V
FKAA
FKAA
FKAA
D
o
o
o
f
44 55
f
44 55
f
44 55
0
0
0
.1
.1
.1
Page 45
A
@
@
ACES_50299-01001-W01
ACES_50299-01001-W01
1
1
2
2
3
3
4
4
5
5
6
6
7
7
1 1
2 2
8
8
9
9
10
1
0
P
P
JP2
JP2
Other component (37.1)
B
ATT_S1
B
ATT_P5
EC_SMDA
EC_SMCA
P
P
R20
R20
100_0402_1%
100_0402_1%
2
1
P
P
R21
R21
100_0402_1%
100_0402_1%
1 2
P
P
F2
F2
21
10A_125V_TR2/6125FF10-R
10A_125V_TR2/6125FF10-R
1
P
P
R14
R14
1K_0402_1%
1K_0402_1%
2
12
P
P
R19
R19
1K_0402_1%
1K_0402_1%
P
P
R16
R16
6.49K_0402_1%
6.49K_0402_1%
2
1
B
ATT_PRES <41>
E
C_SMB_DA1 <38,41,46>
E
C_SMB_CK1 <38,41,46>
V
B
P
L3
EMI@PL3
EMI@
FBMA-L11-201209-121LMA50T_0805
FBMA-L11-201209-121LMA50T_0805
MB
+
3VL
1 2
P
L2
EMI@PL2
EMI@
FBMA-L11-201209-121LMA50T_0805
FBMA-L11-201209-121LMA50T_0805
1 2
EMI@
EMI@
12
P
P
C7
C7
1000P_0402_50V7K
1000P_0402_50V7K
E
MI Part (47.1)
EMI@
EMI@
12
P
P
C8
C8
0.01U_0402_25V7K
0.01U_0402_25V7K
B
ATT+
C
OTP (39.7)
A
DP_I<41,46>
P
ROCHOT_IN<41>
P
R2
@PR2
@
0_0402_5%
0_0402_5%
1 2
D
+
3VL
1
R4
R4
P
R1
R1
P
P
1 2
1K_0402_1%
1K_0402_1%
V
CIN0_PH<41>
R3
R3
P
P
1 2
20K_0402_1%
20K_0402_1%
P
R5
@PR5
@
0_0402_5%
0_0402_5%
1
12
P
C11
@PC11
@
0.1U_0402_10V7K
0.1U_0402_10V7K
P
2
12.1K_0402_1%
12.1K_0402_1%
2
12
H1
H1
P
P
100K_0402_1%_TSM0B104F4251RZ
100K_0402_1%_TSM0B104F4251RZ
PH1 under CPU botten side :
CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C
Initial Protect Recovery
65W
75W
3 3
0.75V
0.9V
0.752V
0.902V
0.626V
0.722V
Initial Protect Recovery
CPU OTP 65W 93 C
4 4
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
2
2
2
012/09/24 2013/09/24
012/09/24 2013/09/24
012/09/24 2013/09/24
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
C
56 C
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
T
itle
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
Date: Sheet
ompal Electronics, Inc.
B
B
B
ATTERY CONN / OTP
ATTERY CONN / OTP
ATTERY CONN / OTP
V
V
V
FKAA
FKAA
FKAA
D
o
o
o
f
45 55
f
45 55
f
45 55
0
0
0
.1
.1
.1
Page 46
A
B
C
D
for reverse input protection
harger controller (40.1), Support component (40.2)
P
P
R211
R211
0.01_1206_1%
0.01_1206_1%
1
2
1 2
P
P
C236
C236
B
B
Q24735_ACN
Q24735_ACP
Q24735_CMSRC
Q24735_ACDRV
B
Q24735_ACOK
12
C244
C244
P
P
C
0.1U_0402_25V6
0.1U_0402_25V6
4
3
1
2
C235
C235
P
P
0.1U_0402_25V6
0.1U_0402_25V6
P
P
1
1U_0603_25V6K
1U_0603_25V6K
21
1
2
3
4
5
1
R244
R244
P
P
2
422K_0402_1%
422K_0402_1%
12
R245
R245
P
P
66.5K_0402_1%
66.5K_0402_1%
100P_0402_50V8J
100P_0402_50V8J
E
MI Part (47.1)
B
+
1UH_NRS4018T1R0NDGJ_3.2A_30%
1UH_NRS4018T1R0NDGJ_3.2A_30%
V
IN
2
3
P
P
D230
D230
BAS40CW_SOT323-3
BAS40CW_SOT323-3
1
1
1 2
R228
R228
P
P
10_1206_1%
10_1206_1%
2
C239
C239
Q24735_VCC
2
B
Q24735_LX
B
19
20
U200
U200
P
P
CC
V
AD
P
A
A
C
A
A
B
HASE
P
CN
CP
BQ24725RGRR_QFN20_3P5X3P5
BQ24725RGRR_QFN20_3P5X3P5
MSRC
CDRV
COK
CDET
OUT
I
A
6
7
Q24735_ACDET
B
P
P
C245
C245
2
1
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
EMI@
EMI@
P
P
L201
L201
1 2
0.047U_0402_25V7K
0.047U_0402_25V7K
P
P
C237
C237
1
12
R229
R229
P
P
2
2.2_0603_5%
2.2_0603_5%
H_CHG
Q24735_REGN
Q24735_BST
B
D
B
16
17
18
TST
IDRV
B
H
B
DA
CL
S
S
8
9
10
12
P
R246
@PR246
@
0_0402_5%
0_0402_5%
1 2
EGN
R
ODRV
L
ATDRV
LIM
I
12
C211
C211
P
P
10U_0805_25V6K
10U_0805_25V6K
12
1
C213
C213
C214
C214
P
P
P
P
2
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_25V7K
2200P_0402_25V7K
@EMI@
@EMI@
5
P
P
D231
D231
RB751V-40_SOD323-2
RB751V-40_SOD323-2
1U_0603_25V6K
1U_0603_25V6K
ND
G
RP
S
RN
S
B
Q24735_ILIM
R242
R242
P
P
100K_0402_1%
100K_0402_1%
1
0.1U_0402_10V7K
0.1U_0402_10V7K
2
1 2
D
H_CHG
@
@
P
P
R210 0_0603_5%
R210 0_0603_5%
C205
C205
P
P
2
1
15
D
L_CHG
14
R236
R236
P
P
10_0603_1%
10_0603_1%
13
1 2
S
RP
P
P
R237
R237
6.8_0603_5%
6.8_0603_5%
12
1 2
S
RN
11
B
Q24735_BATDRV
1 2
P
P
R241
R241
357K_0402_1%
357K_0402_1%
12
C243
C243
P
P
0.01U_0402_25V7K
0.01U_0402_25V7K
E
C_SMB_CK1 <38,41,45>
E
C_SMB_DA1 <38,41,45>
A
DP_I <41,45>
C246
@PC246
@
P
P
lease locate th e RC
Near EC chip
2011-02-22
2
2
2
012/09/24 2013/09/24
012/09/24 2013/09/24
012/09/24 2013/09/24
4
4
C
SOP1
C
SON1
P
P
0.1U_0603_16V7K
0.1U_0603_16V7K
+
3VALW
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
123
B
5
123
12
C242
C242
D
D
D
eciphered Date
eciphered Date
eciphered Date
Q201
Q201
P
P
AON7408L
AON7408L
Q24735_LX
AON7406L
AON7406L
B
Q24735_BATDRV
P
P
L202
L202
4.7UH_ETQP3W4R7WF N_5.5A_20%
4.7UH_ETQP3W4R7WF N_5.5A_20%
1 2
1
Q202
Q202
P
P
R206
R206
P
P
4.7_1206_5%
4.7_1206_5%
2
EMI@
EMI@
@
@
12
C206
C206
P
P
680P_0603_50V8J
680P_0603_50V8J
@EMI@
@EMI@
EMI Part (47.1)
309K_0402_1%
309K_0402_1%
47K_0402_1%
47K_0402_1%
For A51 ADP_V function
C
5
SI7716ADN-T1-GE3_POWERPAK8-5
SI7716ADN-T1-GE3_POWERPAK8-5
1 2
B
Q24735_BATDRV_1
P
P
R233
R233
4.12K_0603_1%
4.12K_0603_1%
R227
R227
P
P
0.01_1206_1%
0.01_1206_1%
1
C
HG
2
SOP1
C
12
C240
C240
P
P
0.1U_0402_25V6
0.1U_0402_25V6
V
IN
12
P
P
R247
R247
12
R249
R249
P
P
1
Q207
Q207
P
P
2
3
4
1
0.1U_0402_10V7K
0.1U_0402_10V7K
2
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
4
3
10K_0402_1%
10K_0402_1%
1
@PC247
@
P
itle
itle
itle
C
C
C
ustom
ustom
ustom
1
C234
C234
P
P
2
0.01U_0402_50V7K
0.01U_0402_50V7K
SON1
C
12
P
P
C247
R248
R248
C241
C241
P
P
12
0.1U_0402_25V6
0.1U_0402_25V6
2
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
ompal Electronics, Inc.
C
C
C
HARGER
HARGER
HARGER
V
FKAA
C222
C222
P
P
10U_0805_25V6K
10U_0805_25V6K
A
1
C223
C223
P
P
2
10U_0805_25V6K
10U_0805_25V6K
DP_V <41>
B
ATT+
o
o
o
f
46 56
f
46 56
f
46 56
D
0
0
0
.1
.1
.1
1
D
D
2
P
P
Q209
Q209
G
G
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
S
S
3
R226
R226
P
P
P
R225
R225
1
1M_0402_5%
1 1
2 2
3 3
1M_0402_5%
TPCA8057-H_PPAK56-8-5
TPCA8057-H_PPAK56-8-5
V
IN
Q203
Q203
P
P
5
12
C230
C230
P
P
2200P_0402_50V7K
2200P_0402_50V7K
4
B
1 2
2
3M_0402_5%
3M_0402_5%
1
2
3
Q24735_ACDRV_1
P
P
1
1
Q205
Q205
P
P
2
3
12
C231
C231
P
P
0.1U_0402_25V6
0.1U_0402_25V6
12
12
R234
R234
P
P
4.12K_0603_1%
4.12K_0603_1%
4
SI7716ADN-T1-GE3_POWERPAK8-5
SI7716ADN-T1-GE3_POWERPAK8-5
R235
R235
P
P
4.12K_0603_1%
4.12K_0603_1%
P
2
5
0.1U_0402_25V6
0.1U_0402_25V6
12
C238
C238
P
P
0.1U_0603_25V7K
0.1U_0603_25V7K
B
B
+
3VL
A
CIN<27,41>
V
IN
1 2
P
P
R239 10K_0402_1%
R239 10K_0402_1%
Vin Dectector
Min. Typ Max.
H-->L 17.23V
L--> H 17.63V
ILIM and external DPM
3.61A
4 4
A
Page 47
A
B
C
D
/5VALW controller (35.1), Support component (35.2)
3
5V
Peak Current 10A
OCP current 12.03A
FSW=390kHz
Delta I=4.29A,ripple=4.29*17m=72.93mV
DCR 15.5mohm+/-15%
1 1
ESR 17mohm
TYP MAX
H/S Rds(on) :27mohm , 34mohm
C345@
C345@
P
P
100P_0402_50V8J
100P_0402_50V8J
2
2
R333
@PR333
@
P
1
P
P
R330
R330
14K_0402_1%
14K_0402_1%
1 2
R331
R331
P
P
20K_0402_1%
20K_0402_1%
1
B
ST_3V
U
G_3V
L
X_3V
L
G_3V
499K_0402_1%
499K_0402_1%
1
12
C360
C360
P
P
@PR341
@
0_0402_5%
0_0402_5%
1 2
2
P
P
R334
R334
0.1U_0603_25V7K
0.1U_0603_25V7K
P
P
R340
R340
2.2K_0402_1%
2.2K_0402_1%
1 2
P
R341
2
F
B_3V
1 2
4
5
B2
F
6
P
GOOD
7
B
OOT2
8
U
GATE2
9
P
HASE2
10
L
GATE2
IN
V
11
12
2
12
1
C342
C342
R338
R338
P
P
P
P
2
100K_0402_1%
100K_0402_1%
1U_0603_10V6K
1U_0603_10V6K
12
C343
C343
P
P
R357
R357
R342
R342
R337
R337
P
P
P
P
P
P
226K_0402_1%
226K_0402_1%
NTRIP2
E
NLDO
E
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
3
ON
T
ECFB
S
13
1 2
56K_0402_1%
56K_0402_1%
1 2
143K_0402_1%
143K_0402_1%
2
NTRIP1
E
DO5
L
14
15
12
4.7U_0603_10V6K
4.7U_0603_10V6K
R332
R332
P
P
@
@
100K_0402_5%
100K_0402_5%
DO3
L
F
1
U
P
L
PU330
PU330
R
R
P
P
B1
F
B
GATE1
HASE1
GATE1
E
MI Part (47.1)
B
+
2 2
EMI@
EMI@
P
P
L331
L331
HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
1 2
+
3VALWP
C339
C339
P
P
@EMI@
@EMI@
3
/5V_B+
12
2200P_0402_50V7K
2200P_0402_50V7K
12
C340
C340
P
P
10U_0805_25V6K
10U_0805_25V6K
L332
L332
P
P
4.7UH_ETQP3W4R7W FN_5.5A_20%
4.7UH_ETQP3W4R7W FN_5.5A_20%
1
+
+
C331
C331
P
P
2
150U_D2_6.3VY_R15M
150U_D2_6.3VY_R15M
5
Q331
Q331
P
P
12
12
R336
R336
P
P
4.7_1206_5%
4.7_1206_5%
@EMI@
@EMI@
NUB_3V
S
12
C336
C336
P
P
680P_0603_50V8J
680P_0603_50V8J
@EMI@
@EMI@
4
AON7408L
AON7408L
123
5
AON7406L
AON7406L
3
1
2
P
P
4
Q332
Q332
P
P
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2
C335
C335
1
+
3VL
P
OK<27>
B
ST1_3V
R335
R335
P
P
100K_0402_1%
100K_0402_1%
0_0402_5%
0_0402_5%
1 2
3
/5V_B+
EMI Part (47.1)
E
3 3
3
.3V
C_ON<41>
V
S_ON<41>
Peak Current 8A
OCP current 9.68A
Delta I=1.28A ,ripple=1.28x15m=19.2mV
FSW=455kHz
DCR 35mohm +/-15%
ESR 15mohm
TYP MAX
P
P
R350
R350
30K_0402_1%
30K_0402_1%
1
P
P
R351
R351
19.1K_0402_1%
19.1K_0402_1%
2
1
B_5V
21
P
AD
20
B
YP1
19
B
OOT1
T8243AZQW_WQFN20_3X 3
T8243AZQW_WQFN20_3X 3
C344
C344
E
NLDO <42>
ST_5V
18
U
G_5V
17
L
X_5V
16
L
G_5V
1
4.7U_0603_10V6K
4.7U_0603_10V6K
2
+
3VLP
(
100mA,40mils ,Via NO.= 2)
2
+
P
P
0_0402_5%
0_0402_5%
1
3VLP
C341
C341
R355
@PR355
@
P
@PJ333
@
P
2
2
JUMP_43X39
JUMP_43X39
2
J333
1
B
ST1_5V
1
0.1U_0402_10V7K
0.1U_0402_10V7K
H/S Rds(on) :27mohm , 34mohm
L/S Rds(on) :19mohm , 23.5mohm
L/S Rds(on) :10.8mohm , 13.6mohm
3
/5V_B+
1
C361
C361
P
P
2
10U_0805_25V6K
10U_0805_25V6K
C355
C355
P
P
2
1
Q352
Q352
P
P
FDMC7692S_MLP8-5
FDMC7692S_MLP8-5
5
4
4
AON7408L
AON7408L
P
P
Q351
Q351
3
1
2
2.2UH_ETQP3W2R2W FN_8.5A_20%
2.2UH_ETQP3W2R2W FN_8.5A_20%
5
3
12
NUB_5V
S
2
1
12
L352
L352
P
P
1 2
R356
R356
P
P
@EMI@
@EMI@
4.7_1206_5%
4.7_1206_5%
C356
C356
P
P
@EMI@
@EMI@
680P_0603_50V8J
680P_0603_50V8J
EMI Part (47.1)
P
J331
@PJ331
+
3VL
+
3VALWP
+
5VALWP
@
112
JUMP_43X118
JUMP_43X118
@PJ332
@
1
1
JUMP_43X118
JUMP_43X118
P
J332
2
+
5VALWP
1
+
+
C351
C351
P
P
2
150U_D2_6.3VY_R15M
150U_D2_6.3VY_R15M
2
2
+
3VALW
+
5VALW
4 4
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
2
2
2
012/09/24 2013/09/24
012/09/24 2013/09/24
012/09/24 2013/09/24
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
C
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
T
itle
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
Date: Sheet
ompal Electronics, Inc.
3
3
3
VALW/5VALW
VALW/5VALW
VALW/5VALW
V
FKAA
D
o
o
o
f
47 56
f
47 56
f
47 56
0
0
0
.1
.1
.1
Page 48
A
DR controller (35.3), Support component (35.4)
D
EMI@
EMI@
L151
L151
P
P
HCB1608KF-121T30_0603
HCB1608KF-121T30_0603
B
+
1.5VP
1 1
1 2
+
L152
L152
P
0.68UH_PCMB053T-1R0MS_8.5A_20%
0.68UH_PCMB053T-1R0MS_8.5A_20%
1
+
+
C157
C157
P
P
2
P
390U_2.5V_M
390U_2.5V_M
1
.5V_B+
1
2
C152
C152
P
P
2200P_0402_50V7K
2200P_0402_50V7K
@EMI@
@EMI@
12
12
SNUB_+1.5VP
1
2
E
@EMI@
@EMI@
P
P
R156
R156
4.7_1206_5%
4.7_1206_5%
@EMI@
@EMI@
C156
C156
P
P
680P_0402_50V7K
680P_0402_50V7K
MI Part (47.1)
12
C154
C154
P
P
10U_0805_25V6K
10U_0805_25V6K
5
Q151
Q151
P
P
AON7408L
AON7408L
123
5
Q152
Q152
P
P
FDMC7692S_MLP8-5
FDMC7692S_MLP8-5
2
3
1
S
YSON<41>
4
4
2
C155
C155
P
P
1
0.1U_0603_25V7K
0.1U_0603_25V7K
R163
@PR163
@
P
0_0402_5%
0_0402_5%
1 2
+
5VALW
ST_1.5V-1
B
P
P
R159
R159
5.1_0603_5%
5.1_0603_5%
1
1U_0603_10V6K
1U_0603_10V6K
1 2
@
@
P
P
R155 0_0603_5%
R155 0_0603_5%
SW_1.5V
DL_1.5V
27.4K_0402_1%
27.4K_0402_1%
1U_0603_10V6K
1U_0603_10V6K
2
12
P
P
C164
C164
E
N_1.5V
ST_1.5V
B
P
P
R158
R158
1 2
C162
C162
P
P
1
V
DD_1.5V
D
H_1.5V
CS_1.5V
2
+
5VALW
1.5V_B+
15
L
GATE
14
P
GND
13
C
S
12
V
DDP
11
V
DD
R161
R161
P
P
510K_0402_1%
510K_0402_1%
1 2
16
18
17
19
OOT
GATE
HASE
B
P
RT8207MZQW_W QFN20_3X3
RT8207MZQW_W QFN20_3X3
GOOD
P
9
10
TON_1.5V
LDOIN
U
V
5
3
ON
S
T
S
8
7
20
TT
V
V
TTGND
V
TTSNS
V
TTREF
B
F
6
P
P
V
F
U150
U150
P
AD
G
ND
DDQ
B_1.5V
21
1
2
3
4
5
V
TTREF_1.5V
P
P
10K_0402_1%
10K_0402_1%
1 2
R160
R160
P
P
10.2K_0402_1%
10.2K_0402_1%
R162
R162
+
1.5V
+
12
1.5VP
+
0.75VSP
12
12
C159
C159
C160
C160
P
P
P
P
10U_0805_6.3V6K
10U_0805_6.3V6K
10U_0805_6.3V6K
10U_0805_6.3V6K
12
P
P
C163
C163
0.033U_0402_16V7K
0.033U_0402_16V7K
+
1.5VP
J153
@PJ153
@
P
+
0.75VSP
2
JUMP_43X39
JUMP_43X39
+
112
0.75VS
+
1.5VP
(0.5A,40mils ,Via NO.= 1)
1.5V
Peak Current 16.8A
OCP current 20 A
FSW=495kHz
DCR 13mohm
ESR 9mohm
TYP MAX
H/S Rds(on) :27mohm , 34mohm
L/S Rds(on) :10.8mohm , 13.6mohm
STATE S3 S5 1.5VP VTT_REFP 0.75VSP
S0
S3
S4/S5
Hi Hi
HiLo
Lo Lo
On
On
Off
(Discharge)
On
On
Off
(Discharge)
Off
(Discharge)
Note: S3 - sleep ; S5 - power off
@
@
P
P
J151
J151
2
112
JUMP_43X118
JUMP_43X118
@
@
J152
J152
P
P
2
112
JUMP_43X118
(15A, 600mils ,Via NO.= 30)
OCP=18A
JUMP_43X118
+
5VALW
On
Off
(Hi-Z)
+
1.5V
S
USP#<41,43,49>
1
C166
@PC166
@
P
0.1U_0402_10V7K
0.1U_0402_10V7K
2
L181
L181
P
P
HCB1608KF-121T30_0603
HCB1608KF-121T30_0603
1 2
@
@
R181
R181
P
P
1 2
0_0402_5%
0_0402_5%
499K_0402_1%
499K_0402_1%
R164
@PR164
@
P
0_0402_5%
0_0402_5%
0
.75VR_EN<43 >
1
N_0.75VSP
2
E
1
C167
@PC167
@
P
0.1U_0402_10V7K
0.1U_0402_10V7K
2
1.8VS controller (35.15), Support component (35.16)
U180
U180
P
P
SY8032ABC_SOT23-6
SY8032ABC_SOT23-6
4
N
I
5
12
C184
C184
P
P
22U_0805_6.3VAM
22U_0805_6.3VAM
E
N_1.8V
1
@
@
R182
R182
P
P
2
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
12
C185
C185
P
P
0.1U_0402_10V7K
0.1U_0402_10V7K
@
@
P
6
B
F
2
2
2
012/09/24 2013/09/24
012/09/24 2013/09/24
012/09/24 2013/09/24
G
3
X
L
2
ND
G
1
N
E
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
L
X_1.8V
D
D
D
eciphered Date
eciphered Date
eciphered Date
1UH_NRS4018T1R0NDGJ_3.2A_30%
1UH_NRS4018T1R0NDGJ_3.2A_30%
R186
R186
P
P
4.7_0402_1%
4.7_0402_1%
C186
C186
P
P
1 2
12
1 2
680P_0402_50V7K
680P_0402_50V7K
P
P
L182
L182
20K_0402_1%
20K_0402_1%
F
B_1.8V
P
J180
@PJ180
@
2
12
JUMP_43X79
JUMP_43X79
C183
C183
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
112
+
1.8VSP
+
1.8VSP
12
R183
R183
P
P
1
C187
C187
P
P
2
12
68P_0402_50V8J
68P_0402_50V8J
1
P
P
R184
R184
10K_0402_1%
10K_0402_1%
2
T
T
Title
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
Date: Sheet
C182
C182
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
ompal Electronics, Inc.
1
1
1
.5VP/0.75VSP/1.8VSP
.5VP/0.75VSP/1.8VSP
.5VP/0.75VSP/1.8VSP
V
V
V
FKAA
FKAA
FKAA
o
o
o
f
48 56
f
48 56
f
48 56
+
1.8VS
0
0
0
.1
.1
.1
Page 49
5
D D
EMI Part (47.1)
C C
HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
B+
T
he current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high respectively.
B B
EMI@
EMI@
4
1
.05VCCP controller (35.5), Support component (35.6)
P
P
L401
L401
12
1
2
C404
C404
P
P
2200P_0402_50V7K
2200P_0402_50V7K
@EMI@
@EMI@
+3VS
V
CCP_PWRGOOD<43,50>
1
C401
C401
P
P
2
10U_0805_25V6K
10U_0805_25V6K
1
P
P
R401
R401
100K_0402_5%
100K_0402_5%
+
1.05VSP_B+
+3VS
2
P
GD_1.05V
8
9
3
2
3
P
P
U400
U400
I
N
G
ND
I
LMT
P
G
SY8208DQNC_QFN10_3X3
SY8208DQNC_QFN10_3X3
E
N
B
S
L
X
F
B
B
YP
L
DO
1
0.1U_0603_25V7K
0.1U_0603_25V7K
6
10
4
7
5
P
P
C406
C406
1 2
12
2
P
P
R402
R402
@
@
12
0_0402_5%
0_0402_5%
12
P
C402
@PC402
@
0.1U_0402_16V7K
0.1U_0402_16V7K
@EMI@
@EMI@
P
P
R403
R403
4.7_1206_5%
4.7_1206_5%
1 2
P
P
0.68UH_PCMC063T-R68MN_15.5A_20 %
0.68UH_PCMC063T-R68MN_15.5A_20 %
S
W_+1.05VSP
+
12
C413
C413
P
P
C412
C412
P
P
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1 2
3VALW
S
USP# <41,43,48>
E
MI Part (47.1)
S
NUB_+1.05VSP
L402
L402
1
2
12
@EMI@
@EMI@
P
P
C403
C403
680P_0603_50V7K
680P_0603_50V7K
1
12
12
R404
R404
P
P
75K_0402_1%
75K_0402_1%
P
P
R405
R405
100K_0402_1%
100K_0402_1%
2
C407
C407
P
P
4700P_0402_16V7K
4700P_0402_16V7K
R406
R406
P
P
1K_0402_1%
1K_0402_1%
12
C408
C408
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
C409
C409
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
1
2
C411
C411
C410
C410
P
P
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
1
+1.05VS_VCCPP
22U_0603_6.3V6M
22U_0603_6.3V6M
12
P
R413
@PR413
@
0_0402_5%
0_0402_5%
V
CCIO_SENSE <8>
P
J401
@PJ401
@
2
+
1.05VS_VCCPP
(
17A,680mils ,Via NO.=34)
OCP=23.91A
A A
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
Title
Title
2
2
2
013/09/242012/09/24
013/09/242012/09/24
013/09/242012/09/24
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
1
2
1
JUMP_43X118
JUMP_43X118
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
ompal Electronics, Inc.
+
+
+
1.05VS_VCCP
1.05VS_VCCP
1.05VS_VCCP
VFKAA
M
M
M
onday, March 11, 2013
onday, March 11, 2013
onday, March 11, 2013
+
1.05VS_VCCP
0
0
0
.1
.1
.1
5
5
5
649
649
649
o
o
o
f
f
1
f
Page 50
5
4
3
2
ID [0] VID[1] VCCSA Vout
V
1
0 0 0.9V
0 1 0.85V
1 0 0.775V
1 1 0.75V
D D
VCCSA controller (35.17), Support component (35.18)
+
VCCSAP
+
1.05VS_VCCP
C C
S
A_PGOOD<41>
+
3VS
1
2
R610
R610
P
P
100K_0402_5%
100K_0402_5%
+
VCCSA_B+
12
C628
C628
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
+
5VALW
P
R601
@PR601
@
0_0402_5%
0_0402_5%
2
V
CCP_PWRGOOD<43,49>
1
12
C626
C626
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
12
C629
C629
C624
C624
P
P
P
P
1U_0603_6.3V6M
1U_0603_6.3V6M
P
P
U601
U601
9
G
ND
5
V
IN
6
V
PP
7
P
OK
8
V
EN/MODE
G978F11U_SO8
G978F11U_SO8
1
2
1U_0603_6.3V6M
1U_0603_6.3V6M
4
V
o
3
P
R621
@PR621
@
V
o
0_0402_5%
0_0402_5%
1 2
2
P
R622
@PR622
@
D
1
0_0402_5%
0_0402_5%
1
1
D
0
2
H
_VCCSA_VID1 <9>
H
_VCCSA_VID0 <9>
12
C615
C615
C613
C613
P
P
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
C616
C616
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
12
C618
C618
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
P
@PJ602
@
112
JUMP_43X118
JUMP_43X118
P
PEN@PR611
PEN@
1 2
0.005_1206_1%
0.005_1206_1%
+
VCCSAP
0
.9V
J602
R611
+
VCCSA
2
+
VCCSA
P
J601
@PJ601
@
2
+
B B
A A
1.05VS_VCCP
(
6A, 240mils ,Via NO.= 6)
5
2
1
JUMP_43X79
JUMP_43X79
1
+
VCCSA_B+
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
2
2
012/09/24 2013/09/24
012/09/24 2013/09/24
012/09/24 2013/09/24
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
T
itle
itle
itle
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
2
Date: Sheet
ompal Electronics, Inc.
V
V
V
CC_SAP
CC_SAP
CC_SAP
V
V
V
FKAA
FKAA
FKAA
1
o
o
o
f
50 56
f
50 56
f
50 56
0
0
0
.1
.1
.1
Page 51
5
4
3
2
1
+
2
1
P
P
R501
R501
1
8.06K_0402_1%
8.06K_0402_1%
0.033U_0402_16V7K
0.033U_0402_16V7K
1.05VS_VCCP
130_0402_1%
130_0402_1%
R523
R523
V
GATE<27,41>
T
RBST#
C
R549
R549
P
P
R533
R533
P
P
SCOMP
5VS
F
BA3
2
1 2
CSP1A, CSP2A to +5VS.
L
GA, SWA, HGA, BSTA, DIFFA, TRBSTA#, ILIMA, PWMA are float.
VSPA, VSNA to GND (HW side).
CSREFA, TSNSA, IOUTA to GND.
D D
10_0402_1%
V
V
12
C518
C518
P
P
+
1.05VS_VCCP
CC_AXG_SENSE<9>
SS_AXG_SENSE<9>
1U_0402_16V7K
1U_0402_16V7K
.
.
12
10_0402_1%
+
R534
R534
P
P
1 2
P
P
@75_0402_1%
@75_0402_1%
T
RBSTA#
C C
V
R_SVID_DAT<8>
V
R_SVID_ALRT#<8>
V
R_SVID_CLK<8>
V
R_HOT#<41>
V
SSSENSE<8>
B B
V
CCSENSE<8>
A A
1 2
R502 @0_0402_5%
R502 @0_0402_5%
P
P
FBA and COMPA are short.
CSCOMPA, CSSUMA, DROOPA are short.
2
1
C501
C501
P
P
0.033U_0402_16V7K
0.033U_0402_16V7K
C519
C519
P
P
54.9_0402_1%
54.9_0402_1%
P
P
C505
C505
1
2
1U_0402_16V7K
1U_0402_16V7K
.
.
P
P
R514
R514
1 2
10_0402_1%
10_0402_1%
8.06K_0402_1%
8.06K_0402_1%
3P: 806
2P: 1K
F
BA1
1
2
+
3VS
12
3P: 330p
2P: 1000p
F
B_CPU3
R511
R511
P
P
1 2
R503
P
P
R503
1
1K_0402_1%
1K_0402_1%
P
P
1 2
806_0402_1%
806_0402_1%
V
R_ON<41>
C
PU_B+
R522
R522
P
P
10K_0402_5%
10K_0402_5%
C531
C531
P
P
1 2
0.033U_0402_16V7K
0.033U_0402_16V7K
2
D
R548
R548
F
ROOP
C
B_CPU2
P
P
SP1A
P
P
49.9_0402_1%
49.9_0402_1%
C534
C534
R545
R545
P
P
1 2
10_0402_1%
10_0402_1%
1 2
P
P
R542
R542
1K_0402_1%
1K_0402_1%
+
5VS
P
R527
R527
P
P
66.5K_0402_1%
66.5K_0402_1%
1 2
1 2
R525 1K_0402_1%
R525 1K_0402_1%
P
P
12
P
P
1000P_0402_50V7K
1000P_0402_50V7K
R517
R517
P
P
2
1
F
1 2
1
806_0402_1%
806_0402_1%
2
.033U_0402_16V7K
.033U_0402_16V7K
0
0
C539
C539
P
P
1
1000P_0402_50V7K
1000P_0402_50V7K
F
BA2
1
2_0603_5%
2_0603_5%
1 2
2.2U_0603_10V7K
2.2U_0603_10V7K
1
R532 0_0402_5%@PR532 0_0402_5%@
C522
C522
C524
C524
1
P
P
R519
R519
1K_0402_1%
1K_0402_1%
B_CPU1
560P_0402_50V7K
560P_0402_50V7K
P
P
R510
R510
2
C
C508
C508
P
P
2
1
560P_0402_50V7K
560P_0402_50V7K
2
P
P
R535
R535
C517
C517
P
P
2
V
R_ON_CPU
P
P
R529
R529
1 2
10K_0402_1%
10K_0402_1%
12
.01U_0402_25V7K
.01U_0402_25V7K
0
0
2
C529
C529
P
P
1 2
SREF
DIS only:
All AXG components are @.
Except
PR272 and PR273 are 0ohm.
PC223, PC226, PR202 are 0ohm.
PC220, PC215, PR206 are 0ohm.
P
P
C502
C502
2
1
.1U_0402_16V7K
.1U_0402_16V7K
1 2
P
P
R550
R550
24.9K_0402_1%
C509
C509
P
P
1
10P_0402_50V8J
10P_0402_50V8J
2
C
OMPA1
C513
C513
P
P
1 2
PU501
PU501
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
C527
C527
P
P
10P_0402_50V8J
10P_0402_50V8J
C
OMP_CPU1
24.9K_0402_1%
2
C510
C510
P
P
1 2
1500P_0402_50V7K
1500P_0402_50V7K
IFFA
D
60
61
59
58
AD
SPA
SNA
P
V
V
V
CC
DDBP
V
V
RDYA
E
N
S
DIO
A
LERT#
S
CLK
BOOT
V
N
N
CP81012BMNR2G_QFN60_7X7
CP81012BMNR2G_QFN60_7X7
R
OSC
V
RMP
V
RHOT#
V
RDY
V
SN
V
SP
D
IFF
RBST#
B
T
F
16
18
17
B_CPU
RBST#
T
F
OMP_CPU
C
12
C530
C530
P
P
12
1800P_0402_50V7K
1800P_0402_50V7K
C537
C537
P
P
R508
R508
P
P
1 2
24.9K_0402_1%
24.9K_0402_1%
PUT COLSE
TO VCORE
Phase 1
Inductor
R538
R538
P
P
1 2
15.8K_0402_1%
15.8K_0402_1%
BA
F
OMPA
ROOPA
RBSTA#
LIMA
MONAIMONA
T
I
C
D
I
56
55
53
54
57
52
BA
F
IFFA
LIMA
I
OUTA
D
OMPA
I
C
RBSTA#
T
SCOMP
SSUM
OMP
ROOP
OUT
LIM
I
I
D
C
C
C
19
20
22
24
23
21
ROOP
D
LIM_CPU
MONIMON
I
I
1 2
R520 12.4K_ 0402_1%PR520 12.4K_ 0402_1%
P
2
SCOMPCSCOMPCSCOMPCSCOMPCSCOMPCSCOMP
1
C
1 2
1
75K_0402_1%
75K_0402_1%
.1U_0402_16V7K
.1U_0402_16V7K
2P: 24K
1P: 24.9K
P
P
R541
R541
1
5.11K_0402_1%
5.11K_0402_1%
2P: 21.5K
1P: 15.8K
1000P_0402_50V7K
1000P_0402_50V7K
8
1012_VCC
V
R_SVID_DAT
V
R_SVID_ALRT#
V
R_SVID_CLK
V
BOOT
R
OSC_CPU
V
RMP
V
R_HOT#
V
GATE
D
IFF_CPU
3P: 22p
2P: 10p
R515
R515
P
P
6.34K_0402_1%
6.34K_0402_1%
3P: 6.04K
2P: 4.32K
3P: 23.7K
2P: 24.9K
12
1 2
C503
C503
C504
C504
1 2
P
P
P
P
1000P_0402_50V7K
1000P_0402_50V7K
165K_0402_1%
165K_0402_1%
R540
R540
1 2
P
P
59K_0603_1%
59K_0603_1%
C512
C512
P
P
1000P_0402_50V7K
1000P_0402_50V7K
1 2
+
5VS
1 2
SP1A
.1U_0402_16V7K
.1U_0402_16V7K
C
SCOMPA
SREFA
SSUMA
C
C
C
SENSEA
T
49
50
48
51
47
46
SP2A
SP1A
SNSA
C
C
SREFA
T
SSUMA
ROOPA
C
C
SCOMPA
D
WMA
P
C
STA
B
H
GA
S
WA
L
GA
B
ST2
H
G2
S
W2
L
G2
P
VCC
P
GND
L
G1
S
W1
G1
H
ST1
B
RVEN
SP2
SP3
SREF
SP1
WM
SNS
P
T
C
D
C
C
C
29
26
28
30
25
27
SENSETSENSE
T
P
P
1 2
C
SP1
C
SP2
3P: 21K
2P: 12.4K
P
P
C532
C532
1000P_0402_50V7K
1000P_0402_50V7K
C
SSUM
C535
C535
P
P
1 2
1000P_0402_50V7K
1000P_0402_50V7K
1 2
2
P
P
R505
R505
N
TC_PH201
P
P
H501
H501
12
220K_0402_5%_ERTJ0EV224J
220K_0402_5%_ERTJ0EV224J
R551
R551
P
P
@330P_0402_50V7K
@330P_0402_50V7K
12
P
P
R544
R544
C
P
P
C514
C514
45
44
43
42
41
40
39
38
37
36
8
1012P_VCCP
35
34
33
32
31
1
R521
R521
P
P
41.2K_0402_1%
41.2K_0402_1%
C525
C525
.1U_0402_16V7K
.1U_0402_16V7K
+
5VS
C538
C538
P
P
330P_0402_50V7K
330P_0402_50V7K
R504
R504
P
P
1
165K_0402_1%
165K_0402_1%
2
75K_0402_1%
75K_0402_1%
1
N
TC_PH203
S
SREFA <52>
B
ST2
B
ST1
2
D
RVEN <52>
C
SREF <52>
3P: 1500p
2P: 1200p
2
12
P
P
H503
H503
220K_0402_5%_ERTJ0EV224J
220K_0402_5%_ERTJ0EV224J
C
SREFA
W1A <51,52>
C
SP1A
R543
R543
P
P
2
1
26.1K_0402_1%
26.1K_0402_1%
H
G2 <52>
L
G2 <52>
L
G1 <52>
H
G1 <52>
3P: 73.2K
2P: 41.2K
PUT COLSE
TO GT
Inductor
P
P
0.047U_0402_16V7K
0.047U_0402_16V7K
1 2
2P: 36K
1P: 26.1K
1 2
R530
R530
P
P
2.2_0603_5%
2.2_0603_5%
P
R524
R524
P
P
1
2.2_0603_5%
2.2_0603_5%
C
C
SREF
C
C
SREF
1 2
R509
R509
P
P
120K_0603_1%
120K_0603_1%
P
1 2
P
R507
R507
120K_0603_1%
120K_0603_1%
C511
C511
R539 4.7K_0402_1%
R539 4.7K_0402_1%
P
P
1 2
6
132_PWMA <52>
B
ST2_1
1 2
R528 0_0402_5%@PR528 0_0402_5%@
2
B
ST1_1
SP2
1
2
SP1
1
2
C520
C520
P
P
1 2
0.22U_0402_10V6K
0.22U_0402_10V6K
C523
C523
P
P
1 2
0.22U_0402_10V6K
0.22U_0402_10V6K
1 2
P
P
R518
R518
P
P
4.7K_0402_1%
4.7K_0402_1%
C528
C528
0.047U_0402_16V7K
0.047U_0402_16V7K
1 2
P
P
R513
R513
4.7K_0402_1%
4.7K_0402_1%
C533
C533
P
P
0.047U_0402_16V7K
0.047U_0402_16V7K
S
W1
S
W2
C
SCOMPA
S
W1A <51,52>
P
P
C521
C521
1 2
2.2U_0603_10V7K
2.2U_0603_10V7K
1K_0402_1%
1K_0402_1%
S
W2 <51,52>
S
W1 <51,52>
S
W2 <51,52>
S
W1 <51,52>
R546
R546
P
P
1 2
2P: 1.65K
1P: 1K
+
5VS
D
ROOPA
C507
C507
P
P
2
1
1000P_0402_50V7K
1000P_0402_50V7K
T
SENSEA
1
R537
R537
P
P
2
23.2K_0402_1%
23.2K_0402_1%
PUT COLSE
TO V_GT
HOT SPOT
T
SENSE
12
R512
R512
P
P
23.2K_0402_1%
23.2K_0402_1%
PUT COLSE
TO VCORE
HOT SPOT
C
SREFA
H504
H504
P
P
100K_0402_1%_TSM0B104F4251RZ
100K_0402_1%_TSM0B104F4251RZ
1 2
2
H502
H502
P
P
100K_0402_1%_TSM0B104F4251RZ
100K_0402_1%_TSM0B104F4251RZ
1
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
2
2
012/09/24 2013/09/24
012/09/24 2013/09/24
012/09/24 2013/09/24
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C
ompal Electronics, Inc.
T
T
T
itle
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
2
Date: Sheet
P
P
P
WR-CPU_CORE
WR-CPU_CORE
WR-CPU_CORE
V
FKAA
1
o
o
o
f
51 56
f
51 56
f
51 56
0
0
0
.1
.1
.1
Page 52
5
E
H
D D
G1<51>
S
W1<51,52>
L
G1<51>
HG1_1 HG2_1
7
1
2
1
1
D
G
1/D2
S
FDMS3664S_PO WER56-8-7
FDMS3664S_PO WER56-8-7
2
2
2
2
S
G
S
S
P
P
Q501
Q501
4
6
5
3
4
MI Part (47.1)
1
12
C552
C552
C541
C541
P
P
P
P
2
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_25V7K
2200P_0402_25V7K
@EMI@
@EMI@
C
12
C542
C542
P
P
10U_0805_25V6K
10U_0805_25V6K
0.22UH_MMD -06DZNR22MEO1L_2 5A_20%
0.22UH_MMD -06DZNR22MEO1L_2 5A_20%
12
EMI@
EMI@
R506
R506
P
P
4.7_1206_5%
4.7_1206_5%
NUB_CPU1
S
EMI@
EMI@
12
C506
C506
P
P
680P_0402_ 50V7K
680P_0402_ 50V7K
EMI Part (47.1)
PU_B+
P
P
1
L502
L502
+
CPU_CORE
2
10_0402_1 %
10_0402_1 %
3
EMI@
EMI@
P
P
L501
L501
FBMA-L11-20120 9-121LMA50T_0805
FBMA-L11-20120 9-121LMA50T_0805
+
FBMA-L11-20120 9-121LMA50T_0805
FBMA-L11-20120 9-121LMA50T_0805
12
1 2
EMI@
EMI@
P
P
L505
L505
1
C
SREF <51>
S
W1 <51,52>
2
1
+
+
C551
C551
P
P
2
100U_25V_M
100U_25V_M
C
PU_B+
1
+
+
C598
C598
P
P
2
@
@
H
G2<51>
S
33U_D2_25VM_R60M
33U_D2_25VM_R60M
W2<51,52>
L
G2<51>
FDMS3664S_PO WER56-8-7
FDMS3664S_PO WER56-8-7
B
P
P
R552
R552
2
1
CPU_B+
12
12
C544
C544
C543
C543
P
P
P
P
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
L503
L503
P
P
0.22UH_MMD -06DZNR22MEO1L_2 5A_20%
0.22UH_MMD -06DZNR22MEO1L_2 5A_20%
7
1
2
Q505
Q505
P
P
1
1
D
G
1/D2
S
2
2
2
2
S
S
G
S
4
6
5
3
1
EMI@
EMI@
P
P
R526
R526
4.7_1206_5%
4.7_1206_5%
2
NUB_CPU2
S
EMI@
EMI@
12
P
P
C526
C526
680P_0402_ 50V7K
680P_0402_ 50V7K
1 2
+
CPU_CORE
R553
R553
P
P
10_0402_1 %
10_0402_1 %
12
C
SREF
S
W2 <51,52>
EMI Part (47.1)
C C
D
C
PU_B+
12
R284
R284
P
P
1 2
2.2_0603_5%
2.2_0603_5%
F
LAG
D
RVH
S
G
ND
D
RVL
B
STA1_1
12
C286
C286
P
P
.22U_0402_10V6K
.22U_0402_10V6K
0
0
9
8
H
G1A
7
S
W
W1A
6
5
L
G1A
FDMS3664S_PO WER56-8-7
FDMS3664S_PO WER56-8-7
1
2
1
1
D
G
2
2
S
S
Q503
Q503
P
P
4
3
4
B
STA1
P
P
U202
U202
1
B
ST
6
132_PWMA<51>
B B
D
RVEN<51 >
+
5VS
A A
2
P
P
@
@
0_0402_5%
0_0402_5%
R272
R272
R285
R285
P
P
2
2K_0402_1%
2K_0402_1%
1
V
CC_GFX1
1
2
2
@PR275
@
0_0402_5%
0_0402_5%
P
P
2.2U_0603_ 10V6K
2.2U_0603_ 10V6K
1
C289
C289
E
P
N_GFX1
R275
5
2
3
1
4
P
WM
E
N
V
CC
NCP5911MN TBG_DFN8_2X2
NCP5911MN TBG_DFN8_2X2
12
C547
C547
C548
C548
P
P
P
P
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
+
R554
R554
P
P
10_0402_1 %
10_0402_1 %
GFX_CORE
12
C
SREFA <51>
S
W1A <51>
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
2
2
012/09/24 2013/09/24
012/09/24 2013/09/24
012/09/24 2013/09/24
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
2
P
P
L504
L504
0.22UH_MMD -06DZNR22MEO1L_2 5A_20%
0.22UH_MMD -06DZNR22MEO1L_2 5A_20%
7
1/D2
S
2
S
6
5
12
EMI@
EMI@
P
P
R516
R516
4.7_1206_5%
4.7_1206_5%
2
G
NUB_GFX1
S
EMI@
EMI@
12
P
P
C516
C516
680P_0402_ 50V7K
680P_0402_ 50V7K
EMI Part (47.1)
1 2
DC 35W GT2
VID1=1.23V
IccMax=33A
Icc_Dyn=20.2A
Icc_TDC=21.5A
R_LL=3.9m ohm
OCP~40A
C 35W CPU
VID1=1.05V
IccMax=53A
Icc_Dyn=43A
Icc_TDC=33A
R_LL=1.9m ohm
OCP~65A
T
T
T
itle
itle
itle
P
P
P
WR-CPU_CORE
WR-CPU_CORE
Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
Date: Sheet
WR-CPU_CORE
V
FKAA
o
o
o
f
52 56Monday, March 11, 20 13
f
52 56Monday, March 11, 20 13
f
1
52 56Monday, March 11, 20 13
0
0
0
.1
.1
.1
C
ompal Electronics, Inc.
Page 53
5
PU_CORE output cap (36.4)
C
4
3
+
CPU_CORE
2
1
GFX_CORE output cap (36.5)
VCCP output cap (36.6)
D D
+
GFX_CORE
1
C584
C584
P
P
2
22U_0603_6.3V6M
22U_0603_6.3V6M
1
C590
C590
P
P
C C
2
22U_0603_6.3V6M
22U_0603_6.3V6M
1
+
+
C596
C596
P
P
2
330U_D2_2V_Y
330U_D2_2V_Y
1
1
C585
C585
P
P
2
22U_0603_6.3V6M
22U_0603_6.3V6M
1
C591
C591
P
P
2
22U_0603_6.3V6M
22U_0603_6.3V6M
1
C586
C586
C587
C587
P
P
P
P
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
C593
C593
C592
C592
P
P
P
P
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
C588
C588
C589
C589
P
P
P
P
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
C594
C594
C595
C595
P
P
P
P
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+
CPU_CORE
+
CPU_CORE
22U_0603_6.3V6M
22U_0603_6.3V6M
1
2
22U_0603_6.3V6M
22U_0603_6.3V6M
1
2
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
1
C565
C565
2
22U_0603_6.3V6M
22U_0603_6.3V6M
P
P
1
C573
C573
2
22U_0603_6.3V6M
22U_0603_6.3V6M
P
P
1
C555
C555
2
22U_0603_6.3V6M
22U_0603_6.3V6M
P
P
12
C560
C560
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
C567
C567
2
2
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
C574
C574
2
2
P
P
P
P
1
C556
C556
2
P
P
1
C561
C561
2
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
C566
C566
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
C575
C575
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
12
C557
C557
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
C562
C562
2
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
C568
C568
2
2
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
C576
C576
2
2
P
P
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
1
C558
C558
C559
C559
2
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
P
P
1
C564
C564
C563
C563
2
P
P
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
C570
C570
C569
C569
2
2
P
P
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
C577
C577
2
22U_0603_6.3V6M
22U_0603_6.3V6M
1
C578
C578
2
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
P
P
1
C571
C571
C572
C572
2
P
P
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
1
C580
C580
C579
C579
2
1
+
+
C581
C581
P
P
330U_D2_2V_Y
330U_D2_2V_Y
2
B B
+
1.05VS_VCCP
+
1.05VS_VCCP
1
1
C417
C417
C418
C418
P
P
P
P
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
C428
C428
C427
C427
P
P
P
P
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
A A
22U_0603_6.3V6M
5
1
1
1
C420
C420
C419
C419
P
P
P
P
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
C429
C429
C430
C430
P
P
P
P
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
C422
C422
C421
C421
P
P
P
2
1
2
P
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
C431
C431
C432
C432
P
P
P
P
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
1
C424
C424
C423
C423
P
P
P
P
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
C433
C433
C434
C434
P
P
P
P
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
4
1
C426
C426
C425
C425
P
P
P
2
P
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
2
2
012/09/24 2013/09/24
012/09/24 2013/09/24
012/09/24 2013/09/24
3
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
1
+
+
P
P
C582
C582
330U_D2_2V_Y
330U_D2_2V_Y
2
C
T
T
Title
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
2
Date: Sheet
ompal Electronics, Inc.
C
C
C
PU_CORE_CAP
PU_CORE_CAP
PU_CORE_CAP
V
FKAA
53 56Monday, March 11, 2013
53 56Monday, March 11, 2013
53 56Monday, March 11, 2013
1
0
0
0
.1
.1
o
o
o
.1
f
f
f
Page 54
A
VGA_CORE
+
1 1
+
VGA_CORE
1
2
2 2
P
RV11 = 71.5K ==>Fsw = 450KHz
V
GA_VSS_SENSE<15>
V
GA_VCC_SENSE<15>
Under VGA Core
12
12
C923
C923
P
P
12
12
C904
C904
C903
C903
P
P
P
P
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
12
C919
C919
C918
C918
P
P
P
P
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
N
ear VGA Core
12
C924
C924
P
P
22U_0603_6.3V6M
22U_0603_6.3V6M
47U_0805_6.3V6M
47U_0805_6.3V6M
12
C905
C905
P
P
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
C920
C920
P
P
0.1U_0402_10V7K
0.1U_0402_10V7K
12
C925
C925
P
P
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
R917
@PR917
@
P
0_0402_5%
0_0402_5%
1 2
P
R920
@PR920
@
0_0402_5%
0_0402_5%
1 2
12
C907
C907
P
P
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
1
C927
C927
P
P
2
12
C936
C936
P
P
1000P_0402_50V7K
1000P_0402_50V7K
1
C908
C908
P
P
2
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
1
C928
C928
P
P
2
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
P
P
C937
C937
47P_0402_50V8J
47P_0402_50V8J
1 2
12
C909
C909
P
P
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
C921
C921
P
P
0.1U_0402_10V7K
0.1U_0402_10V7K
12
C926
C926
P
P
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
N14P-GV2 N14M-GL
3 3
R
1 PR913
R2 PR915
R3 PR930
R4 PR914
C PC940
20 Kohm
20 Kohm
2 Kohm
18 Kohm
2.7 nF
B4-128 package
G
12
C911
C911
P
P
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
C952
C952
P
P
@
@
1
P
P
51_0402_1%
51_0402_1%
1 2
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
R919
R919
C912
C912
P
P
1
2
2
1
C913
C913
P
P
2
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
C953
C953
P
P
@
@
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
GV@PR915
GV@
20K_0402_1%
20K_0402_1%
V
REF
1500P_0402_50V7K
1500P_0402_50V7K
GV@PR914
GV@
P
18K_0402_1%
18K_0402_1%
2
100P_0402_50V8J
100P_0402_50V8J
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
2
R914
P
P
12
C955
C955
P
P
@
@
1
1 2
C939
C939
12
C958
C958
P
P
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
1
C929
C929
P
P
2
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
C934 .01U_0603_16V 7K
C934 .01U_0603_16V 7K
P
P
F
B1_VGA
R921
R921
P
P
10K_0402_1%
10K_0402_1%
1 2
39 Kohm
30 Kohm
3 Kohm
27 Kohm
1.8 nF
1
1
C950
C950
C951
C951
P
P
P
P
2
2
@
@
@
@
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
12
C954
C954
C956
C956
P
P
P
P
@
@
@
@
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
P
R915
1
12
P
C933
@PC933
@
P
C940 2700P_0402_50V7KGV@PC940 2700P_0402_50V7KGV@
12
2
1
P
P
R931 34K _0402_1%
R931 34K _0402_1%
P
P
C938 10P _0402_50V8J
C938 10P _0402_50V8J
2
1
1 2
F
B2_VGA
R922
R922
P
P
82K_0402_1%
82K_0402_1%
P
P
R913
GL@
R913
GL@
39K_0402_1%
39K_0402_1%
P
P
R915
GL@
R915
GL@
30K_0402_1%
30K_0402_1%
P
P
R930
GL@
R930
GL@
3K_0402_1%
3K_0402_1%
R914
GL@
R914
GL@
P
P
27K_0402_1%
27K_0402_1%
C940
GL@
C940
GL@
P
P
1800P_0402_50V7K
1800P_0402_50V7K
C949
C949
P
P
@
@
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
C
1
C902
C902
P
P
2
@
@
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
GV@PR913
GV@
P
20K_0402_1%
20K_0402_1%
12
GV@PR930
GV@
2K_0402_1%
2K_0402_1%
R
EFIN
V
REF
F
S
F
B_VGA
OMP_VGA
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
R913
B
V
GA_CORE controller (43.1), Support component (43.2)
<13>
<13>
SI
GPU_VID
P
D
3VS_DGPU+3VS_DGPU
+
12
1
R912
R912
P
P
10K_0402_5%
R932 0_0402_5%@PR932 0_0402_5%@
1 2
P
SI_VGA
P
4
SI
ID
P
V
CC
ALERT#
T
V
15
CC_VGA
V
2
1
10K_0402_5%
2
1
C930 .1U_0402_16V 7KPC930 .1U_0402_16V 7K
P
U
GATE1_VGA
N_VGA
E
1
2
3
N
G1
E
ST1
H
B
P
L
GND
P
VCC
P
L
P
G2
GOOD
ST2
H
B
P
16
17
18
U
GATE2_VGA
R925 10K_0402_5 %
R925 10K_0402_5 %
P
P
P
P
R927 2.2_0402 _5%
R927 2.2_0402 _5%
C946
C946
P
P
1U_0402_10V6K
1U_0402_10V6K
H1
G1
G2
H2
NCP81172MNTWG_QFN24_4X 4
NCP81172MNTWG_QFN24_4X 4
B
OOT2_VGA
12
12
2
R909
R909
P
P
0_0402_5%
0_0402_5%
@
@
R929 10K_0402_5%PR929 10K_0402_5%
1 2
P
G
PU_VID
12
V
IDBUF
R930
P
7
8
9
10
11
12
P
P
R
V
F
F
F
C
U900
U900
EFIN
REF
S
BRTN
B
OMP
5
6
IDBUF
V
ND
SNS
G
T
13
14
25
12
R926 5.9K_0402_1%PR926 5.9K_0402_1%
P
REF
V
P
P
R907
R907
2.2_0603_5%
2.2_0603_5%
OOT1_VGA
B
HASE1_VGA
P
24
23
22
21
P
VCC_VGA
20
19
V
GA_PWROK <17,30>
+
3VS
+
5VS
12
B
OOT1_2_VGA
P
R901
@PR901
@
0_0402_5%
0_0402_5%
P
P
C922
C922
0.22U_0603_10V7K
0.22U_0603_10V7K
1 2
L
GATE1_VGA
P
P
C935 4.7U_0603_10V 6K
C935 4.7U_0603_10V 6K
1 2
12
R924
R924
P
P
2.2_0603_5%
2.2_0603_5%
P
HASE2_VGA
L
GATE2_VGA
2
@
@
12
MDU1512, Rdson(max)=5mohm
@
@
R908
R908
P
P
0_0603_5%
0_0603_5%
12
@
@
P
P
R923
R923
0_0603_5%
0_0603_5%
B
OOT2_2_VGA
C
1
U
GATE1_2_VGA
R911
R911
P
P
10K_0402_5%
10K_0402_5%
+
5VS
12
U
GATE2_2_VGA
C944
C944
P
P
0.22U_0603_10V7K
0.22U_0603_10V7K
1
P
P
Q901
Q901
AON7518
AON7518
P
P
Q902
Q902
TPCA8059
TPCA8059
P
P
AON7518
AON7518
2
P
P
TPCA8059
TPCA8059
Q903
Q903
Q904
Q904
4
4
4
4
5
3
1
2
5
4.7_1206_5%
4.7_1206_5%
3
1
2
EMI@
EMI@
P
P
680P_0402_50V7K
680P_0402_50V7K
E
MI Part (47.1)
5
123
5
3
1
2
680P_0402_50V7K
680P_0402_50V7K
+
VGA_B+
12
C915
C915
P
P
EMI@
EMI@
0.22UH_MMD-06DZNR22MEO1L_25 A_20%
0.22UH_MMD-06DZNR22MEO1L_25 A_20%
1
EMI@
EMI@
P
P
R906
R906
2
NUB1_VGA
S
12
C906
C906
0.22UH_MMD-06DZNR22MEO1L_25 A_20%
0.22UH_MMD-06DZNR22MEO1L_25 A_20%
12
EMI@
EMI@
R916
R916
P
P
4.7_1206_5%
4.7_1206_5%
NUB2_VGA
S
12
EMI@
EMI@
C916
C916
P
P
2200P_0402_50V7K
2200P_0402_50V7K
1
1
C910
C910
P
P
2
10U_0805_25V6K
10U_0805_25V6K
7
P
P
L903
L903
1
C942
C942
P
P
2
P
P
1 2
E
MI Part (47.1)
12
C917
C917
P
P
10U_0805_25V6K
10U_0805_25V6K
x7
2
1
+
+
2
+
VGA_B+
12
C943
C943
P
P
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
7x7
L904
L904
D
EMI@
EMI@
L901
L901
P
P
SUPPRE_ FBMA-L11-453215-800LMA90T_ 1812
SUPPRE_ FBMA-L11-453215-800LMA90T_ 1812
C931
C931
P
P
560U_D2_2VM_R4.5M
560U_D2_2VM_R4.5M
12
+
VGA_CORE
+
VGA_CORE
1
+
+
C947
C947
P
P
2
@
@
330U_D2_2V_Y
330U_D2_2V_Y
B
+
EMI Part (47.1)
4 4
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
2
2
2
012/09/24 2013/09/24
012/09/24 2013/09/24
012/09/24 2013/09/24
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
C
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
T
itle
itle
itle
Size D ocument Number Rev
Size D ocument Number Rev
Size D ocument Number Rev
C
C
C
ustom
ustom
ustom
Date: Sheet
Date: Sheet
Date: Sheet
ompal Electronics, Inc.
+
+
+
VGA_COREP
VGA_COREP
VGA_COREP
V
FKAA
D
o
o
o
f
54 56
f
54 56
f
54 56
0
0
0
.1
.1
.1
Page 55
NO DATE PAGE MODIFICATION LIST PURPOSE
--------------------------------------------------------------------------------------------------------------------------------
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
2012/10/26 2013/10/26
2012/10/26 2013/10/26
2012/10/26 2013/10/26
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Power PIR
Power PIR
Power PIR
QFKAA
55 56Monday, March 11, 2013
55 56Monday, March 11, 2013
55 56Monday, March 11, 2013
0.1
0.1
0.1
Page 56
5
W PIR (Product Improve Record)
H
V
FKAA LA-9863P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 to 0.2
GERBER-OUT DATE: 2012/12/06
NO DATE PAGE MODIFICATION LIST PURPOSE
-----------------------------------------------------------------------------------------------------------------------------------
1. 11/20 06 Mount CC37 To solve S3 shutdown issue
D D
2. 11/20 29 Change USB port 10 to NC No support NFC
3. 11/20 42 Delete JNFC No support NFC
4. 11/20 37 Add QW1, RW3, RW4; change JCARD.10 to SDWP# and JCARD.11 to SDCD To solve card reader no function issue
5. 11/27 40 Change JSPK to ACES_50228-0067N-001_6P For SPK recognize design
6. 11/28 08 Mount CC17, CC18, CC19 For ESD request
7. 11/28 29 Mount CB13 For ESD request
8. 11/28 05 Mount CC63 For ESD request
9. 12/03 38 Add S&C 14640/14641 co-layout circuit Reserved for S&C SPEC update
VFKAA LA-9863P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.2 to 0.3
GERBER-OUT DATE: 2013/01/23
4
3
2
1
NO DATE PAGE MODIFICATION LIST PURPOSE
1. 12/19 41 Change CB13 to SE071101J80 (100pF) ESD request
C C
Change RV43 to 270K, RV53 to 10K, RV54 to 33K 1712/262. For VGA power sequence
3. 01/16 41 Add RB12, RB37, connect EC_MUTE_INT from codec to EC To solve audio "bo" sound issue
For ME drawing updateModify JTP pin define4201/164.
5. 01/16 13 Connect GPIO12 as GPS_DOWN# to EC For GPS function
Mount RH382601/166. For EMI request
For EMI requestReserve R266, R2672201/167.
B B
A A
S
S
S
ecurity Classification
ecurity Classification
ecurity Classification
I
I
I
ssued Date
ssued Date
5
4
ssued Date
T
T
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
2
2
2
012/12/07 2013/12/07
012/12/07 2013/12/07
012/12/07 2013/12/07
3
C
C
C
ompal Secret Data
ompal Secret Data
ompal Secret Data
D
D
D
eciphered Date
eciphered Date
eciphered Date
C
C
C
ompal Electronics, Inc.
ompal Electronics, Inc.
T
T
T
itle
itle
2
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
ompal Electronics, Inc.
H
H
H
W-PIR
W-PIR
W-PIR
1
Page 57
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