Compal LA-9862P VFKTA Rosetta 10FT, Satellite L40, LA-9862P VFKTA Rosetta 10FTG Schematic

A

1 1

B

C

D

E

VFKTA

Rosetta 10FT/10FTG

2 2

LA-9862P REV 1.0 Schematic

Intel Processor (Ivy Bridge/Sandy Bridge)+

3 3

PCH(Panther Point)

2013-02-06 Rev 1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OFC OMPALEL ECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OFC OMPALEL ECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OFC OMPALEL ECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

VFKTA

1 46Monday, March 11, 2013

E

1.0

A

B

C

D

E

Intel CPU Ivy Bridge

17W

1 1

eDP 1.1 2x

2.7GT/s

BGA-1023

31mm*24mm

page 5,6,7,8,9,10

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1066/1333/1600 MT/s

200pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

page 11,12

FDI X8

2.7GT/s

LVDS & eDP Conn.

page 13

2 2

HDMI Conn.

RJ45 Conn.

page 15

RTL8106E & 8111G

PCIe port 1

USB Left

USB20 port 2

page 27

PCIe Gen1 1x

1.5V 5GT/s

USB20 2x

5V 480MHz

To sub-board

3 3

RTC CKT.

page 16

SPI ROM (4MB)

page 16

Intel PCH Panther Point

FCBGA-989

25mm*25mm

page 16,17,18,19,20,21,22,23,24

LPC BUS

3.3V 33 MHz

KB9012

page 32

DMI X4

5GT/s

HD Audio

3.3V 24MHz

USB30 2x

5V 5GT/s

USB20 3x

5V 480MHz

USB20 2x

5V 480MHz

PCIe Gen1 1x

1.5V 5GT/s

USB20 2x

5V 480MHz

SATA Gen3 1x

5V 6GHz(600MB/s)

SA

TA Gen2 1x

5V 3GHz(300MB/s)

HDA Codec

ALC259/269

page 30

USB Right

USB20 port 0,1 USB30 port 1,2

page 29

CardReader GL834L

USB20 port 8

page 28

Int. Camera

PCIeMini Card WLAN and BT

PCIe port 2 &USB port 9

page 26

SATA HDD

SATA port 0

page 25

SATA ODD

SATA port 2

page 25

USB port 11

page 22

DC/DC Interface CKT.

page 34

Power Circuit DC/DC

page 35,36,37,38,39,40, 41,42,43

Touch Pad

Int.KBD

page 33page 33

G-Sensor

page 25

LED+LID/B

page 33

SPK Conn

page 31

JPIO (HP & MIC)

page 31

GCLK

4 4

SLG3NB244VTR

Power/B

A

page 26

page 33

To sub-board

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OFC OMPALEL ECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OFC OMPALEL ECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OFC OMPALEL ECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

VFKTA

2 46Monday, March 11, 2013

E

1.0

5

4

3

2

1

DESIGN CURRENT 0.1A

B+

Ipeak=8.5A, Imax=5.95A, Iocp min=10.2

DESIGN CURRENT 5A

+3VL

+5VALW

PCH_PWR_EN#

D D

SUSP#

SY8032ABC

P-CHANNEL

AO-3413

DESIGN CURRENT 2A

+5VALW_PCH

+1.8VS

SUSP#

TPS22966DPUR

RT8243AZQW

KB_LED

P

-CHANNEL AO-3413

+5VS

LDO

G9191-330T1U

ODD_EN#

P-CHANNEL

AO-3413

Ipeak=5A, Imax=3.5A, Iocp min=6.12A

C C

WOWL_EN#

P-CHANNEL

AO-3413

DESIGN CURRENT 6A

DESIGN CURRENT 400mA

DESIGN CURRENT 300mA

DESIGN CURRENT 1.6A

DESIGN CURRENT 5A

DESIGN CURRENT 330mA

DESIGN CURRENT 3A

+5VS

+5VS_LED

+3VS_HDP

+5VS_ODD

+3VALW

+3V_LAN

+3V_WLAN

PCH_PWR_EN#

+3VALW_PCH

+3VS

+LCD_VDD

SUSP#

TPS22966DPUR

P-CHANNEL

AO-3413

LCD_ENVDD

APL3512ABI

DESIGN CURRENT 6A

DESIGN CURRENT 1.5A

VR_ON

B B

ISL95833HRTZ

USP#

S

SY8208DQNC

Ipeak=14.37A, Imax=10.06A, Iocp min=17.24A

VCCP_PWRGOOD

SYSON

RT8207MZQW

G978F11U

Ipeak=16.66A, Imax=11.66A, Iocp min=20A

0.75VR_ON

DESIGN CURRENT 65A

DESIGN CURRENT 40A

DESIGN CURRENT 6A

DESIGN CURRENT 2A

DESIGN CURRENT 1.5A

+CPU_CORE

+GFX_CORE

+1.05VS_VCCP

+VCCSA

+1.5V

+0.75VS

SUSP

N

-CHANNEL

FDS6676AS

A A

5

4

DESIGN CURRENT 2A

+1.5V_CPU

+1.5VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Power Tree

VFKTA

1

of

3 46Monday, March 11, 2013

of

3 46Monday, March 11, 2013

of

3 46Monday, March 11, 2013

1.0

A

Voltage Rails

power plane

1 1

State

( O MEANS ON X MEANS OFF )

+RTCVCC

B+

+5VL

+3VL

+5VALW

+3VALW

+VSB

B

C

D

E

BTO Option Table

+1.5V

+5VS

+3VS

+1.8VS

+1.5VS

+1.5V_CPU

+0.75VS

+CPU_CORE

+GFX_CORE

+VCCSA

+1.05VS_VCCP

+

3V_WLAN

+3V_LAN

+LCD_VDD

Function

description

explain

BTO

Function

description

explain

BTO

IVB i5 3337U

CPUI53337UR1@

CPUI53337UR3@

LVDS-eDP

LVDS eDP

LVDS@ IEDP@

IVB i3 3227U

CPUI33227UR1@

CPUI33227UR3@

Camera & Mic

CAM_EMI@

CPU

IVB i3 2375M

CPUI32375MR1@

CPUI32375MR3@

USB S&C

14640

14641

14640

14641

14640@

14641@

IVB P 2117U

CPUP2117UR1@

CPUP2117UR3@

CRT@ CRT_EMI@ NOCRT@

IVB C 847

IVB C 847IVB P 2117U

CPUC847R1@

CPUC847R3@ HM76R3@ HM70R3@

CRT

w/ CRT w/o CRT

HM76 HM70

HM76R1@ HM70R1@

KB9012

9012@

PCH

Panther Point

EC

NPCE885N

885@

S0

S1

S3

2 2

S5 S4/AC

S5 S4/ Bat tery only

S5 S4/AC & Battery don't exis t

O

X

O

X

O

X

O

X X

X

X X

OO

X

description

explain

BTO

Function

X

description

explain

BTO

Function

WOWL

w/o

w/

NOWOWL@

WOWL@

Sleep & Music

w/ S&M w/o S&M

269@ 259@

G-SENSOR

GSENSOR@

KB Light

KBL@

ZPODD

w/

w/o

ZPODD@

NONZP@

EMI/ESD/RF part

EM

EMI@ @EMI@ ESD@ @ESD@ @RF@

GCLK

GCLK non-GCLK

GCLK@

I/ESD/RF part

non-GCLK

NOGCLK@

Touch Screen

TOUCH_EMI@

ISPD

HDMI Logo

HDMI45@

Red Word: always un-mount

PCH SM Bus Address

HEX

0001 0110 bSmart Battery

0011 0101 b35 HUSB S&C 14640+3VL

Address

1010 0000 bA0 H

1010 0100 bA4 H

Po

+3VS

EC SM Bus2 Address

Device

werPower

10/22A Add G-sensor reference Hemen

96 H

40 H

X

1001 0110 bPCH

0100 0000 b

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

G3 LOW LOWLOW

SIGNAL

SLP_S3# SLP_S4# SLP_S5#

HIGH HIGHHIGH

LOW

LOW LOW

HIGH HIGHHIGH

HIGH

LOW LOWLOW

HIGH

VS

Device

DDR SO-DIMM 0

DDR SO-DIMM 1

Power

+3VS

+3

+3VS 2C H 0010 1100 bTouch Pad

3 3

EC SM Bus1 Address

Device Address Address

+3VL

10/22A Add Smart Charger SMBus address: 0x12 Hemen we Add already

4 4

HEX HE

16 H

12 HSmart Charger 0001 0010 b+3VL +3VS G-Sensor

HEXDevice AddressPower

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

VFKTA

4 46Monday, March 11, 2013

E

1.0

A

@

12

PM_DRAM_PWR GD_R

CC621000P_0402_50V7K

ESD@

1 2

ESD@

1 2

CC20

1 1

100P_0402_50V8J

H_PWRGOOD_R

CC63180P_0402_50V8J

H_THERMTRIP#

by ESD requestion and place near CPU

+1.05VS_VCCP

12

DRAMPWROK

+3VS

DRAMPWROK

12

RC44 62_0402_5%

RC45 10K_0402_5%

2 2

+3VALW_PCH

RC11 200_0402_5%

DRAMPWROK18

H_PROCHOT#

H_PWRGOOD

@

12

CC701000P_0402_50V7K

@

12

CC671000P_0402_50V7K

@

12

CC661000P_0402_50V7K

H_PECI

H_PM_SYNC

BUF_CPU_RST#

Please place near JCPU

+3VALW_PCH

02/20 Delete CC33 0.1U

UC3

5

1

12

B

2

A

74AHC1G09GW_TSSOP5

P

4

PM_SYS_PWRGD_BUF

O

G

3

10K_0402_5%

RC13

21

11/30 Change CC63 from @ESD@ to ESD@ for ESD request

32

21

H_PROCHOT#32

H_THERMTRIP#

H_PM_SYNC18

H_PWRGOOD21

+1.5V_CPU

12

RC14 200_0402_5%

B

H_SNB_IVB#

H_PECI

T1 PAD TP@

T2 PAD TP@

1 2

RC170 130_0402_5%

H_SNB_IVB#

TP_SKTOCC#

H_CATERR#

H_PECI

RC159

1 2

H_PROCHOT#_R

56_0402_5%

H_THERMTRIP#

H_PM_SYNC

1 2

H_PWRGOOD_R

Rshort@

RC183 0_0402_5%

PM_DRAM_PWR GD_RPM_SYS_PW RGD_BUF

BUF_CPU_RST#

UC1B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWR OK

D44

RESET#

IVY-BRIDGE_BGA1023

P

U@

C

MISC THERMAL PWR MANAGEMENT

CLOCKS

DDR3

JTAG & BPM

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

MISC

BCLK

BCLK#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PRDY#

PREQ#

TCK TMS

TRST#

TDO

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

TDI

<BOM>

J3 H2

AG3 AG1

AT30

BF44 BE43 BG43

N53 N55

L56 L55 J58

M60 L59

K58

G58 E55 E59 G55 G59 H60 J59 J61

100 MHz

CLK_CPU_DMI CLK_CPU_DMI#

120 MHz

CLK_CPU_EDP CLK_CPU_EDP#

H_DRAMRST#

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

XDP_TCK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

D

CLK_CPU_DMI CLK_CPU_DMI#

CLK_CPU_EDP CLK_CPU_EDP#

H_DRAMRST#

RC56 140_0402_1% RC59 25.5_0402_1% RC61 200_0402_1%

12 12 12

T3 PADTP@ T4 PADTP@

1 2

RC55 51_0402_5%

T6 PADTP@ T7 PADTP@

Close to CPU side

Stuff RC158&RC157 if do not support eDP

17 17

CLK_CPU_EDP#

17 17

CLK_CPU_EDP

7

by ESD requestion and place near CPU

DDR3 Compensati on Signals Layout Note:Pla ce these resistors near Processor

E

LVDS@

1 2

RC157 1K_0402_5%

1 2

RC158 1K_0402_5%

LVDS@

@ESD@

H_DRAMRST#

1 2

CC34 180P_0402_50V8J

ESD@

1 2

100P_0402_50V8J

CC35

Routed as a sin gle daisy chain

+1.05VS_VCCP

3 3

Buffered Rest to CPU

+3VS

02/20 Delete CC36 0.1U

PLT_RST# 20,26,27,32

UC2

PLT_RST#

4 4

1

OE#

IN

GND

VCC

OUT

A

2

3

74AHC1G125GW_SOT353-5

5

4

BUFO_CPU_RST# BUF_CPU_RST#

+1.05VS_VCCP

12

RC38 75_0402_5%

43_0402_1%

1 2

RC35

B

XDP Connector

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

Issued Date

For power consumption

+5VS +3VS

Rshort@

1A

1 2

R1

0_0603_5%

32

FAN_SPEED1

02/20 change R1 to short pad for part count reduce

Compal Secret Data

2012/04/19 2015/04/19

C

Compal Secret Data

Deciphered Date

D

FAN Control Circuit

12

R2 10K_0402_5%

FANPWM32

+FAN1

02/20 Delete C4 0.01U

12

D1

BAS16_SOT23-3

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Ivy Bridge_JTAG/XDP/FAN

VFKTA

1

C5

2

10U_0603_6.3V6M

E

JFAN

Conn@

6

GND

5

GND

4

3

2

1

ACES_50273-0040N-001

5 46Monday, March 11, 2013

1.0

A

1 1

2 2

eDP_COMP signals should be shorted near balls and routed with typical impedance <25m ohm

3 3

02/20 Swap H_EDP_TXN[0\1] to H_EDP_TXP[0\1]

10/24 SWAP pin H_EDP_AUXN/P

+1.05VS_VCCP

18

DMI_PTX_CRX_N0

18

DMI_PTX_CRX_N1

18

DMI_PTX_CRX_N2

18

DMI_PTX_CRX_N3

18

DMI_PTX_CRX_P0

18

DMI_PTX_CRX_P1

18

DMI_PTX_CRX_P2

18

DMI_PTX_CRX_P3

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

18

FDI_CTX_PRX_N0

18

FDI_CTX_PRX_N1

18

FDI_CTX_PRX_N2

18

FDI_CTX_PRX_N3

18

FDI_CTX_PRX_N4

18

FDI_CTX_PRX_N5

18

FDI_CTX_PRX_N6

18

FDI_CTX_PRX_N7

18

FDI_CTX_PRX_P0

18

FDI_CTX_PRX_P1

18

FDI_CTX_PRX_P2

18

FDI_CTX_PRX_P3

18

FDI_CTX_PRX_P4

18

FDI_CTX_PRX_P5

18

FDI_CTX_PRX_P6

18

FDI_CTX_PRX_P7

FDI_FSYNC018 FDI_FSYNC118

FDI_INT18

FDI_LSYNC018 FDI_LSYNC118

1 2

RC2 24.9_0402_1%

H_EDP_AUXN13 H_EDP_AUXP13

13

H_EDP_TXN0

13

H_EDP_TXN1

13

H_EDP_TXP0

13

H_EDP_TXP1

B

DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3

DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3

DMI_CTX_PRX_N0

18

DMI_CTX_PRX_N1

18

DMI_CTX_PRX_N2

18

DMI_CTX_PRX_N3

18

DMI_CTX_PRX_P0

18

DMI_CTX_PRX_P1

18

DMI_CTX_PRX_P2

18

DMI_CTX_PRX_P3

18

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT

FDI_LSYNC0 FDI_LSYNC1

EDP_COMP

H_EDP_HPD#

UC1A

M2

DMI_RX#[0]

P6

DMI_RX#[1]

P1

DMI_RX#[2]

P10

DMI_RX#[3]

N3

DMI_RX[0]

P7

DMI_RX[1]

P3

DMI_RX[2]

P11

DMI_RX[3]

K1

DMI_TX#[0]

M8

DMI_TX#[1]

N4

DMI_TX#[2]

R2

DMI_TX#[3]

K3

DMI_TX[0]

M7

DMI_TX[1]

P4

DMI_TX[2]

T3

DMI_TX[3]

U7

FDI0_TX#[0]

W11

FDI0_TX#[1]

W1

FDI0_TX#[2]

AA6

FDI0_TX#[3]

W6

FDI1_TX#[0]

V4

FDI1_TX#[1]

Y2

FDI1_TX#[2]

AC9

FDI1_TX#[3]

U6

FDI0_TX[0]

W10

FDI0_TX[1]

W3

FDI0_TX[2]

AA7

FDI0_TX[3]

W7

FDI1_TX[0]

T4

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

eDP_COMPIO

AD2

eDP_ICOMPO

AG11

eDP_HPD#

AG4

eDP_AUX#

AF4

eDP_AUX

AC3

eDP_TX#[0]

AC4

eDP_TX#[1]

AE11

eDP_TX#[2]

AE7

eDP_TX#[3]

AC1

eDP_TX[0]

AA4

eDP_TX[1]

AE10

eDP_TX[2]

AE6

eDP_TX[3]

IVY-BRIDGE_BGA1023

P

U@

C

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

<BOM>

G3 G1 G4

H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7

K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6

G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4

F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

DMI Intel(R) FDI

PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PCI EXPRESS -- GRAPHICS

eDP

PEG_COMP

RC1

24.9_0402_1%

+1.05VS_VCCP

12

D

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 m ohm (4 mils) PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 m ohm (12 mils)

E

RC10 1K_0402_5%

1 2

H_EDP_HPD#

13

D

2N7002_SOT23-3

CPU_EDP_HPD13

4 4

A

2

G

IEDP@

RC9 100K_0402_5%

1 2

QC1

IEDP@

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Ivy Bridge_DMI/PEG/FDI

VFKTA

6 46Monday, March 11, 2013

E

1.0

A

11

DDR_A_D[0..63]

UC1C

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6

1 1

2 2

DDR_A_BS0 DDR_A_BS1

3 3

DDR_A_BS2

DDR_A_CAS# DDR_A_RAS#

DDR_A_WE#

DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_CAS# DDR_A_RAS# DDR_A_WE#

AG6

SA_DQ[0]

AJ6

SA_DQ[1]

AP11

SA_DQ[2]

AL6

SA_DQ[3]

AJ10

SA_DQ[4]

AJ8

SA_DQ[5]

AL8

SA_DQ[6]

AL7

SA_DQ[7]

AR11

SA_DQ[8]

AP6

SA_DQ[9]

AU6

SA_DQ[10]

AV9

SA_DQ[11]

AR6

SA_DQ[12]

AP8

SA_DQ[13]

AT13

SA_DQ[14]

AU13

SA_DQ[15]

BC7

SA_DQ[16]

BB7

SA_DQ[17]

BA13

SA_DQ[18]

BB11

SA_DQ[19]

BA7

SA_DQ[20]

BA9

SA_DQ[21]

BB9

SA_DQ[22]

AY13

SA_DQ[23]

AV14

SA_DQ[24]

AR14

SA_DQ[25]

AY17

SA_DQ[26]

AR19

SA_DQ[27]

BA14

SA_DQ[28]

AU14

SA_DQ[29]

BB14

SA_DQ[30]

BB17

SA_DQ[31]

BA45

SA_DQ[32]

AR43

SA_DQ[33]

AW48

SA_DQ[34]

BC48

SA_DQ[35]

BC45

SA_DQ[36]

AR45

SA_DQ[37]

AT48

SA_DQ[38]

AY48

SA_DQ[39]

BA49

SA_DQ[40]

AV49

SA_DQ[41]

BB51

SA_DQ[42]

AY53

SA_DQ[43]

BB49

SA_DQ[44]

AU49

SA_DQ[45]

BA53

SA_DQ[46]

BB55

SA_DQ[47]

BA55

SA_DQ[48]

AV56

SA_DQ[49]

AP50

SA_DQ[50]

AP53

SA_DQ[51]

AV54

SA_DQ[52]

AT54

SA_DQ[53]

AP56

SA_DQ[54]

AP52

SA_DQ[55]

AN57

SA_DQ[56]

AN53

SA_DQ[57]

AG56

SA_DQ[58]

AG53

SA_DQ[59]

AN55

SA_DQ[60]

AN52

SA_DQ[61]

AG55

SA_DQ[62]

AK56

SA_DQ[63]

BD37

11

SA_BS[0]

BF36

11

SA_BS[1]

BA28

11

SA_BS[2]

BE39

11

SA_CAS#

BD39

11

SA_RAS#

AT41

11

SA_WE#

DDR SYSTEM MEMORY A

B

SA_CK[0] SA_CK#[0] SA_CKE[0]

SA_CK[1] SA_CK#[1] SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

C

12

DDR_B_D[0..63]

UC1D

AU36

DDRA_CLK0

AV36

DDRA_CLK0#

AY26

DDRA_CKE0

AT40

DDRA_CLK1 DDRB_ CLK1

AU40

DDRA_CLK1# DDRB_ CLK1#

BB26

DDRA_CKE1 DDRB_CKE1

BB40

DDRA_SCS0# DDRB_SCS0#

BC41

DDRA_SCS1#

AY40

DDRA_ODT0 DDRB_ODT0

BA41

DDRA_ODT1

AL11

DDR_A_DQS#0

AR8

DDR_A_DQS#1

AV11

DDR_A_DQS#2

AT17

DDR_A_DQS#3

AV45

DDR_A_DQS#4

AY51

DDR_A_DQS#5

AT55

DDR_A_DQS#6

AK55

DDR_A_DQS#7

AJ11

DDR_A_DQS0

AR10

DDR_A_DQS1

AY11

DDR_A_DQS2

AU17

DDR_A_DQS3

AW45

DDR_A_DQS4

AV51

DDR_A_DQS5

AT56

DDR_A_DQS6

AK54

DDR_A_DQS7

BG35

DDR_A_MA0

BB34

DDR_A_MA1

BE35

DDR_A_MA2

BD35

DDR_A_MA3

AT34

DDR_A_MA4

AU34

DDR_A_MA5

BB32

DDR_A_MA6

AT32

DDR_A_MA7

AY32

DDR_A_MA8

AV32

DDR_A_MA9

BE37

DDR_A_MA10

BA30

DDR_A_MA11

BC30

DDR_A_MA12

AW41

DDR_A_MA13

AY28

DDR_A_MA14

AU26

DDR_A_MA15

DDRA_CLK0 DDRA_CLK0# DDRA_CKE0

DDRA_CLK1 DDRA_CLK1# DDRA_CKE1

DDRA_SCS0# DDRA_SCS1#

DDRA_ODT0 DDRA_ODT1

DDR_A_MA[0..15]

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

11 11 11

11 11

11

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CAS# DDR_B_RAS#

DDR_B_WE#

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CAS# DDR_B_RAS# DDR_B_WE#

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]

BD13

SB_DQ[18]

BF12

SB_DQ[19]

BF8

SB_DQ[20]

BD10

SB_DQ[21]

BD14

SB_DQ[22]

BE13

SB_DQ[23]

BF16

SB_DQ[24]

BE17

SB_DQ[25]

BE18

SB_DQ[26]

BE21

SB_DQ[27]

BE14

SB_DQ[28]

BG14

SB_DQ[29]

BG18

SB_DQ[30]

BF19

SB_DQ[31]

BD50

SB_DQ[32]

BF48

SB_DQ[33]

BD53

SB_DQ[34]

BF52

SB_DQ[35]

BD49

SB_DQ[36]

BE49

SB_DQ[37]

BD54

SB_DQ[38]

BE53

SB_DQ[39]

BF56

SB_DQ[40]

BE57

SB_DQ[41]

BC59

SB_DQ[42]

AY60

SB_DQ[43]

BE54

SB_DQ[44]

BG54

SB_DQ[45]

BA58

SB_DQ[46]

AW59

SB_DQ[47]

AW58

SB_DQ[48]

AU58

SB_DQ[49]

AN61

SB_DQ[50]

AN59

SB_DQ[51]

AU59

SB_DQ[52]

AU61

SB_DQ[53]

AN58

SB_DQ[54]

AR58

SB_DQ[55]

AK58

SB_DQ[56]

AL58

SB_DQ[57]

AG58

SB_DQ[58]

AG59

SB_DQ[59]

AM60

SB_DQ[60]

AL59

SB_DQ[61]

AF61

SB_DQ[62]

AH60

SB_DQ[63]

BG39

12

SB_BS[0]

BD42

12

SB_BS[1]

AT22

12

SB_BS[2]

AV43

12

SB_CAS#

BF40

12

SB_RAS#

BD45

12

SB_WE#

D

BA34

SB_CK[0]

AY34

SB_CK#[0]

AR22

SB_CKE[0]

BA36

SB_CK[1]

BB36

SB_CK#[1]

BF27

SB_CKE[1]

BE41

SB_CS#[0]

BE47

SB_CS#[1]

AT43

SB_ODT[0]

BG47

SB_ODT[1]

AL3

SB_DQS#[0]

AV3

SB_DQS#[1]

BG11

SB_DQS#[2]

BD17

SB_DQS#[3]

BG51

SB_DQS#[4]

BA59

SB_DQS#[5]

AT60

SB_DQS#[6]

AK59

SB_DQS#[7]

AM2

SB_DQS[0]

AV1

SB_DQS[1]

BE11

SB_DQS[2]

BD18

SB_DQS[3]

BE51

SB_DQS[4]

BA61

SB_DQS[5]

AR59

SB_DQS[6]

AK61

SB_DQS[7]

DDR SYSTEM MEMORY B

BF32

SB_MA[0]

BE33

SB_MA[1]

BD33

SB_MA[2]

AU30

SB_MA[3]

BD30

SB_MA[4]

AV30

SB_MA[5]

BG30

SB_MA[6]

BD29

SB_MA[7]

BE30

SB_MA[8]

BE28

SB_MA[9]

BD43

SB_MA[10]

AT28

SB_MA[11]

AV28

SB_MA[12]

BD46

SB_MA[13]

AT26

SB_MA[14]

AU22

SB_MA[15]

DDRB_CLK0 DDRB_CLK0# DDRB_CKE0

DDRB_SCS1#

DDRB_ODT1

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8

DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDRB_CLK0 DDRB_CLK0# DDRB_CKE0

DDRB_CLK1 DDRB_CLK1# DDRB_CKE1

DDRB_SCS0# DDRB_SCS1#

DDRB_ODT0 DDRB_ODT1

DDR_B_DQS#[0..7]

DDR_B_DQS[0..7]

DDR_B_MA[0..15]

E

12 12 12

12 12

12

IVY-BRIDGE_BGA1023

P

U@

C

2013/02/06 change QC3 to SB00000PF00 for X1 code

QC3

D

S

13

H_DRAMRST#5

RC78

RC73

1 2

Rshort@

0_0402_5%

4.99K_0402_1%

1 2

DRAMRST_CNTRL

11/28 Change RC73 to 0 ohm

4 4

(do not use short pad on this location)

DRAMRST_CNTRL_PC H9,17

2013/02/06 PVT Delete RC3.

A

DDR3_DRAMRST#_RH_DRAMRST#

BSS138_NL_SOT23-3

G

2

02/20 Change RC73 to short pad for part count reduce

1

CC37

0.047U_0402_25V6K

2

<BOM>

+1.5V

12

RC76

1K_0402_5%

RC77 1K_0402_5%

1 2

2013/02/06 Confim with rick_Chu , delete CC22 , because HW timing

B

SM_DRAMRST#

11,12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

IVY-BRIDGE_BGA1023

P

U@

C

Compal Secret Data

Deciphered Date

<BOM>

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Ivy Bridge_DDR3

VFKTA

7 46Monday, March 11, 2013

E

1.0

A

B

C

D

E

+CPU_CORE +1.05VS_VCCP

1 1

2 2

3 3

UC1F

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

POWER

CORE SUPPLY

8.5A33A

AF46

VCCIO[1]

AG48

VCCIO[3]

AG50

VCCIO[4]

AG51

VCCIO[5]

AJ17

VCCIO[6]

AJ21

VCCIO[7]

AJ25

VCCIO[8]

AJ43

VCCIO[9]

AJ47

VCCIO[10]

AK50

VCCIO[11]

AK51

VCCIO[12]

AL14

VCCIO[13]

AL15

VCCIO[14]

AL16

VCCIO[15]

AL20

VCCIO[16]

AL22

VCCIO[17]

AL26

VCCIO[18]

AL45

VCCIO[19]

AL48

VCCIO[20]

AM16

VCCIO[21]

AM17

VCCIO[22]

AM21

VCCIO[23]

AM43

VCCIO[24]

AM47

VCCIO[25]

AN20

VCCIO[26]

AN42

VCCIO[27]

AN45

VCCIO[28]

AN48

VCCIO[29]

AA14

VCCIO[30]

AA15

VCCIO[31]

AB17

VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]

VCCIO50 VCCIO51

1mA

VCCIO_SEL

VCCPQE[1] VCCPQE[2]

VIDALERT#

VIDSCLK VIDSOUT

AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

+1.05VS_VCCP

W16 W17

BC22

+1.05VS_VCCP

AM25 AN22

A44

H_CPU_SVIDALRT#

B43 C44

PEG IO AND DDR IO

RAILS

For DDR

For PEG

1

CC71 1U_0402_6.3V6K

2

+1.05VS_VCCP

1

CC17

2

ESD@

100P_0402_50V8J

1

CC19

CC18

2

ESD@

100P_0402_50V8J

by ESD requestion and place near CPU

11/30 install 3 CAP(100pF)CC17,CC18,CC19 on +1.05Vs_Vccp and must close to CPU

+1.05VS_VCCP+1.05VS_VCCP

12

RC91 130_0402_5%

1 2

RC90 43_0402_1%

+CPU_CORE

12

RC89 75_0402_5%

VR_SVID_ALRT# VR_SVID_CLK VR_SVID_DAT

Pu

ll high resistor on VR side

42 42 42

RC93 100_0402_1%

Issued Date

1 2

12

40

RC97 100_0402_1%

Close to CPU

C

VCCSENSE VSSSENSE

2012/04/19 2015/04/19

42 42

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Ivy Bridge_POWER-1

VFKTA

8 46Monday, March 11, 2013

E

1.0

<BOM>

F43 G43

AN16 AN17

VCCIO_SENSE

12

RC96 10_0402_1%

Close to CPU

VCCIO_SENSE

12

RC98 10_0402_1%

+1.05VS_VCCP

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

VCC_SENSE VSS_SENSE

4 4

IVY-BRIDGE_BGA1023

P

U@

C

A

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID QUIET

B

A

B

C

D

E

+GFX_CORE

UC1G

A

29

AA46

VAXG[1]

AB47

VAXG[2]

AB50

VAXG[3]

AB51

1 1

2 2

+GFX_CORE

12

RC105 100_0402_1%

C

lose to CPU

VCC_AXG_SENSE

1

2

10U_0603_6.3V6M

1U_0402_6.3V6K

VSS_AXG_SENSE

1 2

+1.8VS_VCCPLL

CC60

1

2

CC43

2

12

1

10U_0603_6.3V6M

CC75

1

2

1U_0402_6.3V6K

42 42

RC106

100_0402_1%

02/20 Delete CC61

1U_0402_6.3V6K

CC40

@

47U_0805_6.3V6M

CC74

CC73

1

2

1U_0402_6.3V6K

VCC_AXG_SENSE VSS_AXG_SENSE

3 3

4 4

VCCPLL Decoupling: 1X 330U (6m ohm), 1X 10U, 2x1U

02/20 change RC119 to short pad

Reserve for power consumption R

emove on PVT phase

+VCCSA Decoupling: 2X 47U (MLCC), 3X 10U, 5X 1U

11/28 Change CC44 100u to 0805 size (SE00000PL00), Add CC40 (SE00000PL00)

1 2

+1.8VS

RC119 0_0805_5%

+VCCSA

Rshort@

CC44

12

@

47U_0805_6.3V6M

10U_0603_6.3V6M

CC42

2

1

CC77

1

2

A

CC59

Place TOP IN BGA

CC41

2

1

10U_0603_6.3V6M

lace BOT OUT BGA

P

CC76

1

2

1U_0402_6.3V6K

VAXG[4]

AB52

VAXG[5]

AB53

VAXG[6]

AB55

VAXG[7]

AB56

VAXG[8]

AB58

VAXG[9]

AB59

VAXG[10]

AC61

VAXG[11]

AD47

VAXG[12]

AD48

VAXG[13]

AD50

VAXG[14]

AD51

VAXG[15]

AD52

VAXG[16]

AD53

VAXG[17]

AD55

VAXG[18]

AD56

VAXG[19]

AD58

VAXG[20]

AD59

VAXG[21]

AE46

VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47]

W50

VAXG[48]

W51

VAXG[49]

W52

VAXG[50]

W53

VAXG[51]

W55

VAXG[52]

W56

VAXG[53]

W61

VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

1.2A

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

6A

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

IVY-BRIDGE_BGA1023

P

U@

C

POWER

VREF

DDR3 - 1.5V RAILS

GRAPHICS

SENSE

LINES

1.8V RAIL

SA RAIL

VCCSA VID

B

SM_VREF

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8]

VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26]

1mA

VCCDQ[1] VCCDQ[2]

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

SENSE LINES

VCCSA_VID[0] VCCSA_VID[1]

lines

5A

+V_SM_VREF should

ave 20 mil trace width

h

<BOM>

AY43

BE7 BG7

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

AM28 AN26

BC43 BA43

U10

D48 D49

+V_SM_VREF

+VREF_DQA_M3 +VREF_DQB_M3

+1.5V_CPU

1

CC72 1U_0402_6.3V6K

2

H_VCCSA_VID0 H_VCCSA_VID1

Please kindly c heck whether there is pull-d own resister in PWR-side or HW-side

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

Place TOP IN BGA

CC57

CC51

2

1

10U_0603_6.3V6M

CC81

CC82

1

2

1U_0402_6.3V6K

H_VCCSA_VID0 H_VCCSA_VID1

C

RC120 1K_0402_0.5%

CC65

RC109 1K_0402_0.5%

1

2

0.1U_0402_10V7K

CC52

CC55

2

1

10U_0603_6.3V6M

Place BOT OUT BGA

CC80

CC79

1

2

1U_0402_6.3V6K

41 41

2012/04/19 2015/04/19

+1.5V_CPU

1 2

11/28 Change CC53 100u to 47U 0805 (SE00000PL00) Add CC50 (SE00000PL00)

+1.5V_CPU

CC56

CC54

2

1

10U_0603_6.3V6M

CC87

CC78

1

2

1U_0402_6.3V6K

VCCSA_VID0

0

1

+1.5V_CPU +1.5V

CC46 0.1U_0402_10V7K@

CC47 0.1U_0402_10V7K@

CC48 0.1U_0402_10V7K@

CC45 0.1U_0402_10V7K@

2013/02/06 change QC5,QH3,QH4,QW1, Q6 ,QA1 QR1 Q53 from SB00000EO10 to SB00000DH00 DVT 2nd source for X1 code issue

CC50

CC53

12

@

10U_0603_6.3V6M

CC86

1

2

1U_0402_6.3V6K

47U_0805_6.3V6M

CC85

1

2

1U_0402_6.3V6K

VCCSA_VID1

0

1

0

1

1 2

2N7002DW-T/R7_SOT363-6

Compal Secret Data

Deciphered Date

Intel DDR Vref M3

BSS138_NL_SOT23-3

+VREF_DQA_M3

+VREF_DQB_M3

BSS138_NL_SOT23-3

+1.5V_CPU Decoupling: 2X 47U(MLCC), 6X 10U, 8X 1U

+VCCSA

0.90 V

0.80 V

0.725 V

0.675 V

Vgs=10V,Id=14.5 A,Rds=6mohm

RC203

470_0805_5%

1 2 3

QC5B

5

SUSP

4

D

For Sandy Bridge

1

CC68 10U_0603_6.3V6M@

2

0.1U_0402_25V6

CC69

QC7

D

S

13

G

2

G

2

13

D

S

QC8

PJ1

JP@

2

112

JUMP_43X39

QC4

1

S

D

2

S

D

3

S

D

4

G

D

FDS6676AS_SO8

RUN_ON_CPU1.5VS3

12

1

RC205 820K_0402_5%

2

Title

Size Document Number Rev

Custom

Date: Sheet of

+VREF_DQA

DRAMRST_CNTRL_PC H

+VREF_DQB

+1.5VS+1.5V_CPU

+1.5V

8 7 6 5

Compal Electronics, Inc.

VFKTA

02/20 Delete CC83

RC204

1 2

220K_0402_5%

61

QC5A

2

SUSP

2N7002DW-T/R7_SOT363-6

Ivy Bridge_POWER-2

E

7,17

B+

9 46Monday, March 11, 2013

SUSP

34

1.0

UC1H

A13

VSS[1]

A17

VSS[2]

A21

VSS[3]

A25

VSS[4]

A28

VSS[5]

A33

VSS[6]

A37

VSS[7]

A40

VSS[8]

A45

VSS[9]

A49

AA13 AA50 AA51 AA52 AA53 AA55 AA56

AB16 AB18 AB21 AB48

AB61 AC10 AC14 AC46

AD17 AD20

AD61

AE13

AF17

AF21

AF47

AF48

AF50

AF51

AF52

AF53

AF55

AF56

AF58

AF59 AG10 AG14 AG18 AG47 AG52 AG61

AH58

AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48

AK52

AL10

AL13

AL17

AL21

AL25

AL28

AL33

AL36

AL40

AL43

AL47

AL61 AM13 AM20 AM22 AM26 AM30 AM34

AC6

AD4

AE8 AF1

AG7 AH4

AK1

VSS[10]

A53

VSS[11]

A9

VSS[12]

AA1

VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20]

AA8

VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69]

AJ7

VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90]

1 1

2 2

3 3

A

VSS

VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

UC1I

BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53

BG9 C29 C35 C40 D10 D14 D18 D22 D26 D29 D35

D4 D40 D43 D46 D50 D54 D58

D6

E25 E29

E3

E35 E40 F13 F15 F19 F29 F35 F40 F55

G51

G6 G61 H10 H14 H17 H21

H4 H53 H58

J1 J49 J55

K11 K21 K51

K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61

M11 M15

IVY-BRIDGE_BGA1023

C

VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249]

P

U@

B

VSS

VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301]

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11

NCTF

VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14

<BOM>

M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59 G48

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

C

UC1E

B50

T89 PADTP@

CFG0

CFG2

CFG4 CFG5 CFG6 CFG7

T87PADTP@

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

IVY-BRIDGE_BGA1023

P

U@

C

BCLK_ITP

BCLK_ITP#

RSVD30 RSVD31 RSVD32 RSVD33

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44

RESERVED

RSVD45

These pins are for s older join t

eliability and non-c ritical to

r function. For BGA on ly.

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3 DC_TEST_D1

DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61

DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59

DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1

<BOM>

N59 N58

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1

D

DC_TEST_C4_D3

DC_TEST_A59_C59

DC_TEST_A61_C61

DC_TEST_BE61_BE59

DC_TEST_BG61_BG59

DC_TEST_BG3_BE3

DC_TEST_BG1_BE1

E

CFG Straps for Processor

(CFG[17:0] internal pull high 5~15K to VCCIO)

CFG2

12

RC79 1K_0402_1%

@

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition

atches socket pin map definition

CFG2

m

0:Lane Reversed

*

CFG4

12

RC82 1K_0402_1%

IEDP@

Embedded Display Port Presence Strap

1 : Disabled; No Physical Display Port attached to Embedded Display Port

*

CFG4

0 : Enabled; An external Display Port

evice is connected to the Embedded

d Display Port

CFG7

12

RC85 1K_0402_1%

@

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB de assertion

*

CFG7

0

: PEG Wait for BIOS for training

CFG6

CFG5

1K_0402_1%

RC83

12

RC84 1K_0402_1%

@

PCIE Port Bifurcation Straps

IVY-BRIDGE_BGA1023

P

U@

C

4 4

<BOM>

CFG[6:5]

1: (Default) x16 - Device 1 functions 1 and 2

1 disabled

*

10: x8, x8 - Device 1 function 1 enabled; function 2 disabled

1: Reserved - (Device 1 function 1 disabled;

0 function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Ivy Bridge_GND/RSVD/CFG

VFKTA

10 46Monday, March 11, 2013

E

1.0

5

4

3

2

1

+1.5V

+VREF_DQA

1

CD1

0.1U_0402_10V7K

2

D D

Close to JDDRL.1

02/20 Delete CD2, CD15

7

DDRA_CKE0

C C

7

DDR_A_BS2

7

DDRA_CLK0

7

DDRA_CLK0#

7

DDR_A_BS0

7

DDR_A_WE#

7

DDR_A_CAS#

7

DDRA_SCS1#

B B

+3VS

A A

0.1U_0402_10V7K

DDR_A_D0 DDR_A_D1

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

1

CD26

2

SPD setting (SA 0, SA1) PU/PD by Channe l A/B

->Channel A 00

->Channel B 01

5

+0.75VS

JDDR3L

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4406-0102

o

nn@

C

DQS#0

DQS0 VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45 VSS35 DQS#5

DQS5 VSS38

DQ46

DQ47 VSS40

DQ52

DQ53 VSS42

VSS43

DQ54

DQ55 VSS45

DQ60

DQ61 VSS47 DQS#7

DQS7 VSS50

DQ62

DQ63 VSS52

EVENT#

DQ4 DQ5

VSS3

DQ6 DQ7

DM1

DM2

CK1

CK1#

BA1

NC2

DM4

DM6

SDA SCL

VTT2

+1.5V

2 4

DDR_A_D4

6

DDR_A_D5

8 10

DDR_A_DQS#0

12

DDR_A_DQS0

14 16

DDR_A_D6

18

DDR_A_D7

20 22

DDR_A_D12

24

DDR_A_D13

26 28 30 32 34

DDR_A_D14

36

DDR_A_D15

38 40

DDR_A_D20

42

DDR_A_D21

44 46 48 50

DDR_A_D22

52

DDR_A_D23

54 56

DDR_A_D28

58

DDR_A_D29

60 62

DDR_A_DQS#3

64

DDR_A_DQS3

66 68

DDR_A_D30

70

DDR_A_D31

72

74 76 78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

DDR_A_MA15

80

DDR_A_MA14

82 84

DDR_A_MA11

86

DDR_A_MA7

88 90

DDR_A_MA6

92

DDR_A_MA4

94 96

DDR_A_MA2

98

DDR_A_MA0

100 102 104 106 108 110 112 114 116 118 120 122 124 126

+VREF_CAA

128 130

DDR_A_D36

132

DDR_A_D37

134 136 138 140

DDR_A_D38

142

DDR_A_D39

144 146

DDR_A_D44

148

DDR_A_D45

150 152

DDR_A_DQS#5

154

DDR_A_DQS5

156 158

DDR_A_D46

160

DDR_A_D47

162 164

DDR_A_D52

166

DDR_A_D53

168 170 172 174

DDR_A_D54

176

DDR_A_D55

178 180

DDR_A_D60

182

DDR_A_D61

184 186

DDR_A_DQS#7

188

DDR_A_DQS7

190 192

DDR_A_D62

194

DDR_A_D63

196 198 200 202 204

+0.75VS

206

4

DDR3 SO-DIMM A Standard Type

1

2

7,12

7

7 7

7

0.1U_0402_10V7K

12,17,26,33 12,17,26,33

SM_DRAMRST#

DDRA_CKE1

DDRA_CLK1 DDRA_CLK1#

DDR_A_BS1 DDR_A_RAS#

DDRA_SCS0# DDRA_ODT0

DDRA_ODT1

CD16

close to JDDRL.126

PM_SMBDATA PM_SMBCLK

DDR_A_DQS[0..7] 7

DDR_A_DQS#[0..7]

DDR_A_D[0..63] 7

DDR_A_MA[0..15]

+VREF_DQA

+1.5V

12

RD6

1K_0402_1%

12

RD7

1K_0402_1%

0

2/20 Delete CD2, CD15

Layout Note: Place near JDDRL

+1.5V +1.5V +0.75VS

1 2

CD8 10U_0603_6.3V6M

1 2

CD9 10U_0603_6.3V6M

1 2

CD10 10U_0603_6.3V6M

1 2

CD11 10U_0603_6.3V6M

1 2

CD12 10U_0603_6.3V6M

1 2

CD13 10U_0603_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

7

+1.5V

12

RD1

1K_0402_1%

12

RD2

1K_0402_1%

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

1 2

CD20 0.1U_0402_10V7K

1 2

CD17 0.1U_0402_10V7K

1 2

CD18 0.1U_0402_10V7K

1 2

CD19 0.1U_0402_10V7K

2

Layout Note: Place near JDDRL1.203 a nd 204

12

CD24 1U_0402_6.3V6K

12

CD21 1U_0402_6.3V6K

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM0

VFKTA

11 46Monday, March 11, 2013

1

1.0

A

B

C

D

E

DQ4 DQ5

DQ6 DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA SCL

+1.5V

2 4

DDR_B_D4

6

DDR_B_D5

8 10

DDR_B_DQS#0

12

DDR_B_DQS0

14 16

DDR_B_D6

18

DDR_B_D7

20 22

DDR_B_D12

24

DDR_B_D13

26 28 30 32 34

DDR_B_D14

36

DDR_B_D15

38 40

DDR_B_D20

42

DDR_B_D21

44 46 48 50

DDR_B_D22

52

DDR_B_D23

54 56

DDR_B_D28

58

DDR_B_D29

60 62

DDR_B_DQS#3

64

DDR_B_DQS3

66 68

DDR_B_D30

70

DDR_B_D31

72

74 76 78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

DDR_B_MA15

80

DDR_B_MA14

82 84

DDR_B_MA11

86

DDR_B_MA7

88 90

DDR_B_MA6

92

DDR_B_MA4

94 96

DDR_B_MA2

98

DDR_B_MA0

100 102 104 106 108 110 112 114 116 118 120 122 124 126

+VREF_CAB

128 130

DDR_B_D36

132

DDR_B_D37

134 136 138 140

DDR_B_D38

142

DDR_B_D39

144 146

DDR_B_D44

148

DDR_B_D45

150 152

DDR_B_DQS#5

154

DDR_B_DQS5

156 158

DDR_B_D46

160

DDR_B_D47

162 164

DDR_B_D52

166

DDR_B_D53

168 170 172 174

DDR_B_D54

176

DDR_B_D55

178 180

DDR_B_D60

182

DDR_B_D61

184 186

DDR_B_DQS#7

188

DDR_B_DQS7

190 192

DDR_B_D62

194

DDR_B_D63

196 198 200 202 204

+0.75VS

206

B

DDRB_CKE1

DDRB_CLK1 DDRB_CLK1#

DDR_B_BS1 DDR_B_RAS#

DDRB_SCS0# DDRB_ODT0

DDRB_ODT1

CD47

Close to JDDRH.126

PM_SMBDATA PM_SMBCLK

DDR3 SO-DIMM B Standard Type

SM_DRAMRST#

7,11

7

7 7

7

0.1U_0402_10V7K

1

2

11,17,26,33 11,17,26,33

DDR_B_DQS#[0..7]7

DDR_B_DQS[0..7]

DDR_B_D[0..63] 7

DDR_B_MA[0..15] 7

+1.5V

12

RD10

1K_0402_1%

+VREF_DQB

+1.5V

12

RD12

1K_0402_1%

02/20 Delete CD28, CD46

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

12

RD13

1K_0402_1%

Layout Note: Place near JDDRH

+1.5V +0.75VS+1.5V

1 2

CD31 47U_0805_6.3V6M

1 2

CD41 10U_0603_6.3V6M

1 2

CD36 10U_0603_6.3V6M

1 2

CD37 10U_0603_6.3V6M

1 2

CD38 10U_0603_6.3V6M

1 2

CD39 10U_0603_6.3V6M

1 2

CD40 10U_0603_6.3V6M

11/28 Change CD31 47U 1206 to 0805 size (SE00000PL00)

2012/04/19 2015/04/19

C

12

RD11

1K_0402_1%

Compal Secret Data

Deciphered Date

7

11/28 Move RD10, RD11 to page 12

Layout Note: Place these 4 Caps near Command and Control signals of DIMMB

1 2

CD33 0.1U_0402_10V7K

1 2

CD29 0.1U_0402_10V7K

1 2

CD30 0.1U_0402_10V7K

1 2

CD32 0.1U_0402_10V7K

D

Layout Note: Place near JDDRH.203 and 2 04

12

CD45 1U_0402_6.3V6K

12

CD42 1U_0402_6.3V6K

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM1

VFKTA

12 46Monday, March 11, 2013

E

1.0

+1.5V

+VREF_DQB

1 1

02/20 Delete CD28, CD46

Close to JDDRH.1

7

+3VS

7

7 7

7

7 7

7

DDRB_CKE0

DDR_B_BS2

DDRB_CLK0 DDRB_CLK0#

DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDRB_SCS1#

1

CD49

2

0.1U_0402_10V7K

2 2

3 3

4 4

DDR_B_D0 DDR_B_D1

CD27

1

DDR_B_D2 DDR_B_D3

0.1U_0402_10V7K

2

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_D26 DDR_B_D27

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

DDR_B_MA10

DDR_B_MA13

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_D58 DDR_B_D59

12

RD15 10K_0402_5%

SPD setting (SA 0, SA1) PU/PD by Channe l A/B

->Channel A 00

->Channel B 01

A

+0.75VS

JDDR3H

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4806-0102

Conn@

VSS3

DQS#0

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

A

B

C

D

E

For eDP Panel

USB20_N11_R

IEDP@

1 2

H_EDP_AUXP6

1 1

H_EDP_AUXN6

H_EDP_TXP0 6

H_EDP_TXN0 6

H_EDP_TXP1 6

H_EDP_TXN1 6

C890 0.1U_0402_10V7K

IEDP@

1 2

C891 0.1U_0402_10V7K

IEDP@

1 2

C912 0.1U_0402_10V7K

IEDP@

1 2

C913 0.1U_0402_10V7K

IEDP@

1 2

C914 0.1U_0402_10V7K

IEDP@

1 2

C915 0.1U_0402_10V7K

LVDS_EDID_CLK

LVDS_EDID_DATA

LVDS_TXOUT0+

LVDS_TXOUT0-

LVDS_TXOUT1+

LVDS_TXOUT1-

USB20_P11_R

USB20_P8_R

USB20_N8_R

CAM_EMI@

1

4

L55

R

eserve for EMI reque st

@TOUCH_EMI@

1 2

R267 0_0402_5%

TOUCH_EMI@

1

4

L57

1 2

R266 0_0402_5%

@TOUCH_EMI@

2

3

WCM-2012-900T_0805

2

3

WCM-2012-900T_0805

USB20_N11

USB20_P11

2013/02/06 Add R266 ,

267 Co-lay L57

R

USB20_P8

USB20_N8

LCD POWER CIRCUIT

Need check eDP&LVDS both 3V power rail.

20

+3VS

02/20 Change C7 to SE076153K80 (15nF) for LCD sequence tuning

W=60mils

1.5A

+LCD_VDD_SS

12

C7

0.015u_0402_16V_X7R

19

U16

5

VIN

4

SS

APL3512ABI-TRG_SOT23-5

LCD_ENVDD

VOUT

GND

EN

Reserve for power consumption R

move on PVT phase

e

02/20 Change R106 to shortpad

1

+LCD_VDD_OUT

2

3

1 2

R112 100K_0402_5%

1 2

Rshort@

R106 0_0805_5%

+LCD_VDD

W=60mils

I rush=1.5A

Reserve fo r EMI requ est

For LVDS 1ch Panel

1 2

2 2

3 3

LCD_TXOUT0+ 19

LCD_TXOUT0- 19

LCD_TXOUT1+ 19

LCD_TXOUT1- 19

LCD_TXOUT2+ 19

LCD_TXOUT2- 19

LCD_TXCLK+ 19

LCD_TXCLK- 19

LCD_EDID_CLK19

LCD_EDID_DATA19

Reserve for eDP panel potential issue

LVDS@

R262 0_0402_5%

1 2

LVDS@

R263 0_0402_5%

1 2

LVDS@

R265 0_0402_5%

1 2

LVDS@

R264 0_0402_5%

1 2

LVDS@

R300 0_0402_5%

1 2

LVDS@

R299 0_0402_5%

+3VS

LVDS_TXOUT0+

LVDS_TXOUT0-

LVDS_TXOUT1+

LVDS_TXOUT1-

LCD_TXOUT2+

LCD_TXOUT2-

LCD_TXCLK+

LCD_TXCLK-

LVDS_EDID_CLK

LVDS_EDID_DATA

LVDS colay eDP cable

Pin define will be change after ME ready

pin1-4 Touch function for panel

pin5-10 For Webcam with single or dual MIC

pin11-30 For LVDS or EDP panel

JLVDS

Conn@

GND GND GND GND GND

+5VS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31 32 33 34 35

+5VS_LVDS_TOUCH USB20_N8_R USB20_P8_R BKOFF# INT_MIC_DATA INT_MIC_CLK

USB20_P11_R USB20_N11_R +3VS_LVDS_CAM +LCD_VDD

+3VS LVDS_EDID_CLK LVDS_EDID_DATA LVDS_TXOUT0LVDS_TXOUT0+ LVDS_TXOUT1LVDS_TXOUT1+ LCD_TXOUT2LCD_TXOUT2+

LCD_TXCLKLCD_TXCLK+

LED_PWM BKOFF#_R

1 2

Rshort@

R389 0_0603_5%

+LCD_VDD

+LCD_INV

Irush=1.5A

+LCD_INV

CPU_EDP_HPD

1 2

Rshort@

R390 0_0603_5%

INT_MIC_DATA

INT_MIC_CLK

I

rush=1.5A

Irush=1.5A

60mils

6

0mils

60mils

L2

FBMA-L11-201209-221LMA30T_0805

12

EMI@

20mils

30 30

+3VS

20mils

+3VS

B+

1 2

IEDP@

R103 0_0402_5%

BKOFF#_R

4 4

1 2

D15 RB751V40_S C76-2

LVDS@

12

R113 10K_0402_5%

A

IEDP@

5

U17

1

P

IN1

4

O

2

IN2

G

3

SN74AHC1G08DCKR_SC70-5

1 2

R147 0_0402_5%

LVDS@

EC_ENBKL

BKOFF#

19,32

32

LED_PWM

12

R131

47K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

D

1 2

D17RB751V40_SC76-2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

LVDS

VFKTA

E

PCH_PWM 19

13 46Monday, March 11, 2013

1.0

A

B

C

D

E

CRT CONNECTOR

1 1

1 2

UMA_CRT _R 19

UMA_CRT _G 19

UMA_CRT _B 19

CRT@

R138

R140

R139

12

150_0402_1%

2 2

02/20 Delete C250 0.1u

UMA_CRT _DATA

19

UMA_CRT _CLK

19

3 3

19

UMA_CRT _VSYNC

19

UMA_CRT _HSYNC

150_0402_1%

+HDMI_5V_ OUT

+3VS

C238

CRT@

1

C239

2

2.2P_0402_50V8C

L3 NBQ1005 05T-800Y_0402

CRT_EMI@

1 2

L4 NBQ1005 05T-800Y_0402

CRT_EMI@

1 2

L5 NBQ1005 05T-800Y_0402

CRT_EMI@

CRT@

1

C240

2

2.2P_0402_50V8C

11/28 change BOM structureC238 C239 C240 C241 C242 C243 to CRT@EMI@

U49

1

VCC_SYNC

2

VCC_VIDEO

7

VCC_DDC

10

DDC_IN1

11

DDC_IN2

13

SYNC_IN1

15

SYNC_IN2

6

GND

TPD7S01 9-15DBQR_SSOP 16

CRT@

1

C241

2

VIDEO1

VIDEO2

VIDEO3

DDC_OUT1

DDC_OUT2

SYNC_OUT1

SYNC_OUT2

CRT@

C242

2.2P_0402_50V8C

8

BYP

3

4

5

9

12

14

16

1

C243

2

2.2P_0402_50V8C

C15 0.22U_04 02_16V7K

CRT@

1

2

2.2P_0402_50V8C

CRT@

1 2

CRT_R_L

CRT_G_L

CRT_B_L

+HDMI_5V_ OUT

USE HDMI POWER

+HDMI_5V_ OUT

CRT_R_L

CRT_G_L

CRT_B_L

1 2

VSYNC_R

1 2

HSYNC_R

11/29 add 22-ohm (PN: SD028220A80) on CRT HSYNC/VSYNC trace.

R153

4.7K_040 2_5%

CRT@

R6222_0402 _5% CRT@

R6322_0402 _5% CRT@

1 2

VSYNC

HSYNC

R159

4.7K_040 2_5%

CRT@

1 2

CRT_R_L

CRT_DDC _DAT CRT_G_L

HSYNC CRT_B_L

VSYNC

CRT_DDC _CLK

CRT_DDC _DAT

CRT_DDC _CLK

T65, T66: for A TE

T65 PAD

T66 PAD

JCRT

6

11

1 7

12

2 8

13

3 9

14

G

4

G

10 15

5

C-H_13-12 201513CP

Conn@

16 17

4 4

Security Class ification

2012/04/ 19 2015/04/ 19

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/04/ 19 2015/04/ 19

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docum ent Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

CRT

VFKTA

14 46Monday, March 11 , 2013

E

1.0

A

B

C

D

E

RPY1

+3VS

+HDMI_5V_OUT

1 1

19

UMA_HDMI_CLK

19

UMA_HDMI_DATA

2 2

19

UMA_HDMI_CLK-

19

UMA_HDMI_CLK+

19

UMA_HDMI_TX0-

19

UMA_HDMI_TX0+

19

UMA_HDMI_TX1-

UMA_HDMI_TX1+

UMA_HDMI_TX2-

UMA_HDMI_TX2+

3 3

UMA_HDMI_DATA HDMI_SD ATA

HDMI Royalty

4 4

HDMI W/O Logo: RO0000001HM HDMI W/Logo: RO0000002HM HDMI W/Logo + HDCP: RO0000003HM

please manually load this virtual material to 45@ BOM

A

1 8 2 7 3 6 4 5

2.2K_0804_8P4R_5%

UMA_HDMI_CLK HDMI_SCLK

CY2 0.1U_0402_16V7K

CY1 0.1U_0402_16V7K

CY5 0.1U_0402_16V7K

CY3 0.1U_0402_16V7K

CY7 0.1U_0402_16V7K

CY6 0.1U_0402_16V7K

CY9 0.1U_0402_16V7K

CY8 0.1U_0402_16V7K

ZZZ

RO0000003HM

HDMI W/Logo + HDCP

UMA_HDMI_CLK UMA_HDMI_DATA

HDMI_SCLK HDMI_SDATA

+3VS

G

2

BSS138 1N SOT23-3

13

D

S

G

2

S

2013/02/06 change QY1 QY2 to SB00000PF00 for X1 code

1 2

HDMI45@

QY1

BSS138 1N SOT23-3

13

D

QY2

HDMI_TXC-

HDMI_TXC+

HDMI_TXD0-

HDMI_TXD0+

HDMI_TXD1-

HDMI_TXD1+

HDMI_TXD2-

HDMI_TXD2+

10/18 Modify the BOM structure @ to HDMI45@ , change Location HDMI to ZZZ.

B

1

4

WCM-2012HS-900T_4P

LY2

EMI@

1

4

WCM-2012HS-900T_4P

LY3

EMI@

1

4

WCM-2012HS-900T_4P

LY4

EMI@

1

4

WCM-2012HS-900T_4P

2

3

2

3

2

3

2

3

LY1

EMI@

1

L

L L

L

H H

H

X Z

+HDMI_5V_OUT

5

1

UY1

P

OE#

A2Y

G

74AHCT1G125GW_SOT353-5

3

HDMI_HPD

2

3

2

3

2

3

2

3

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

4

HDMI_HPD

Issued Date

RY1

1 2

1K_0402_5%

12

RY3

2.2K_0402_5%

12/04 SWAP RPY4 netname

C

HDMI_HPD_CHDMI_HPD_U

2

RY2

1 2

HDMI_HPD

CY4

0.1U_0402_16V4Z

1

19,21

Compal Secret Data

HDMI_R_D0HDMI_R_D0+ HDMI_R_CK-

HDMI_R_CK+

HDMI_R_D1-

HDMI_R_D1+ HDMI_R_D2HDMI_R_D2+

Deciphered Date

+5VS

100K_0402_5%

+3VS

2012/04/19 2015/04/19

HDMI POWER CIRCUIT

VIN = 5V, IOUT = 0.5A , RDS(ON) TYP=95m ; MAX=115m Current Limit: TYP=0.8A ; MAX=1A

+HDMI_5V_OUT

CY18

0.1U_0402_10V7K

1

2

UY2

1

2

3

AP2151DWG-7_SOT25-5

SA00006H00 0

11/28 Update HDMI current limited IC from AP230W-7 to AP2151DDWG-7.

OUT

GND

FLG

5

IN

4

EN

HDMI Connector

19 18 17 16 15 14 13 12 11 10

11/28 Add @ to JHDMI

Compal Electronics, Inc.

HDMI Conn.

VFKTA

680 +-5% 8P4R

RPY3

680 +-5% 8P4R

RPY4

2

G

D

45 36 27 18

13

QY4

+HDMI_5V_OUT

D

S

2N7002KW_SOT323-3

HDMI_HPD_C

HDMI_SDATA HDMI_SCLK

HDMI_R_CK-

HDMI_R_CK+

HDMI_R_D0-

HDMI_R_D0+

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D2-

HDMI_R_D2+

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

JHDMI

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKCK_shield CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

Conn@

E

GND GND GND GND

+5VS

23 22 21 20

1.0

of

15 46Monday, March 11, 2013

OE# A Y