Compal LA-6882P Schematic

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Compal Confidential

2 2

PIQY1 M/B Schematics Document

Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH

nVIDIA N12P-GT1

3 3

2010-10-05

REV:0.2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/08/01 2010/08/01

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

LA-6882P

E

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Compal confidential

File Name : LA-6882P

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POWER & BOARD

CAP SENSOR BOARD

LA6882P

1 1

NVidia N12P-GT1

PCI-E X16

Intel

Sandy Bridge

VRAM 64*16

I/O BOARD

GDDR5*8

Socket-rPGA988B

37.5mm*37.5mm

DDR3-SO-DIMM X2

BANK 0, 1, 2, 3

HDMI

CONN

CRT Connector

2 2

LVDS Connector

PCI Express Mini card Slot 1

WLAN/WiMAX

USB(WiMAX)

PCI-E(WLAN)

PCI Express Mini card Slot 2

SSD

SATA(SSD)

3 3

PCI Express Mini card Slot 3

TV

PCI-E

USB(WWAN)

USB

Card Reader

Jmicro JMB389 SD/MMC/MS/MS Pro/XD

Passive level shift

optimus 1.0

USB3.0 Controller 2 PORT

6*PCI-E BUS

SPI ROM

Realtek

BCM7780/57781

GIGA LAN

BIOS

100MHz

2.7GT/s

FDI *8

Intel Cougar Point

FCBGA 951

25mm*25mm

LPC BUS

EC

ENE KB930

DMI *4

AZALIA

14*USB2.0

6*SATA serial

(port0,1 support SATA3)

Int.KBD

Dual Channel

DDR3-1066(1.5V) DDR3-1333(1.5V)

UP TO 8G

2Channel Speaker

Audio Codec

RealTek ALC272/ALC5503

BlueTooth CONN

Array Digital MIC

Audio Jacks

Stereo HeadPhone Output Microphone Input

CMOS Camera

USB PORT 2.0 x2(Right) Option3.0 x2

A-COVET Light

WLAN/WiMAX

USB PORT 2.0 x1(Left)

TV

IR

ESATA HDD AND USB CONN

WLAN/WiMAX

RJ45 CONN

Touch Pad

SPI ROM

(Left)

SATA3.0 HDD CONN

4 4

TV

Thermal Sensor

EMC1403

SATA3.0 HDD (SSD)

SATA ODD CONN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/03/24 2008/04/

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

MB Block Diagram

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Voltage Rails

SIGNAL

STATE

+5VS

power plane

1 1

+B

State

+5VALW

+3VALW

+1.5V

+3VS

+1.5VS

+VCCP

+CPU_CORE

+VGA_CORE

+GFX_CORE

+1.8VS

+0.75VS

+1.05VS

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Board ID

0 1 2

S0

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

O

X

O

X

O

XX

X

OO

X

XX X

3 4 5 6 7

USB Port Table

USB 2.0 USB 1.1 Port

UHCI0

UHCI1

SMBUS Control Table

X X

V

+3VS

X

WLAN WWAN

SOURCE

SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 SMBCLK SMBDATA

3 3

SML0CLK SML0DATA SML1CLK SML1DATA

KB930

+3VALW

KB930

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

EC SM Bus1 address

Device

Smart Battery

0001 011X b

VGA BATT KE930 SODIMM

X V

+3VALW

Address

X X X

V

+3VS

X X X

X

X X

V

+3VS

EC SM Bus2 address

Device

Thermal Sensor EMC 1403-2

Thermal Sensor EMC 1402-1

X XX

V

+3VS

X

Address

1001_101xb

100_1100 b

Thermal Sensor

X X X XX

V

+3VS

PCH

+3VS

EHCI1

X

V

EHCI2

X X

PCIE PORT LIST

XXX

Port Device

1 2 3 4 5 6

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

LAN WLAN

USB3.0 Card Reader TV

7

PCH SM Bus address

Device Address

DDR DIMM0

4 4

DDR DIMM2

A

1001 000Xb

1001 010Xb

B

8

SKU

OPTIMUS

Discrete only

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

SLP_S4# SLP_S5# +VALW +V +VS Clock

LOW

PCB Revision

0.1

4 External USB Port

0

USB Port (Left Side)

1

USB Port (Left Side)

2

USB Port (Right Side)

3

USB Port (Right Side)

4

Camera(3D)

5

Camera

6 7 8

IR

9

Mini Card(WLAN)

10

A Cover Light

11 12

Mini Card(TV)

13

Blue Tooth

UMA@+DIS@+OPTI@

DIS@+DIS_ONLY@

2009/08/01 2010/08/01

C

ON

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

ON

Board ID / SKU ID Table for AD channelBOARD ID Table

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7 NC

Compal Secret Data

10K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

Deciphered Date

ON

ON ON

ON

OFF

AD_BID

LOW

OFF

ON

OFF

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V

1.935 V

2.500 V

BOM Structure Table

BTO ItemBOM Structure

OPTI@ DIS@ UMA@ DIS_ONLY@ HDMI@ UMA_HDMI@ DIS_HDMI@ USB20@ USB30@ USB30_SUB@ TV@ TV_SW@ NO_TVSW@ USB_CHG@ NO_CHG@ 272@ 5503@ 57780@ 57781@ ACOVER@ BT@ CMOS@ ESATA@ VENTURA@ X76@ S1G@ S2G@ H1G@ ME@ @

D

OPTIMUS part

Discrete part

UMA part

Discrete only part

HDMI part (DIS and UMA)

HDMI part (UMA)

HDMI part (DIS)

USB20 option (Right side 2 ports)

USB30 option (Right side 2 ports)

USB30 part at sub-board

TV module part

TV module power swith part

No TV module power swith part

USB charger part

No USB charger part

ALC272 audio codec part

ALC5503 audio codec part

BCM57780 LAN part

BCM57781 LAN part

A cover light part

Blue Tooth part

CMOS Camera part

E-SATA part

NVDIA VENTURA function part

X76 Level part

Samsun VRAM 1G part

Samsun VRAM 2G part

Hynix VRAM 1G part

ME part

Unpop

V typ

AD_BID

0 V 0 V

V

AD_BID

max

EVT DVT

0.503 V

0.819 V

0.538 V

0.875 V

PVT MP

1.185 V 1.264 V

1.759 V

2.200 V

3.300 V

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

2.341 V

3.300 V

Notes List

LA-6882P

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VGA and GDDR5 Voltage Rails (N12Px GPIO)

GPIO I/O ACTIVE Function Description

GPIO0

D D

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

C C

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

N/A

IN

OUT

I/O

OUT

I/O

IN

OUT

IN

OUT

IN

N/A

-

Hot plug detect for IFP link C

H

Panel Back-Light brightness(PWM capable)

H

Panel Power Enable

H

Panel Back-Light On/Off (PWM)

GPU VID0

-

GPU VID1

-

N/A

-

Thermal Catastrophic Over T emperature

-

Thermal Alert

-

Memory VREF Control

N/A

AC Power Detect Input

N/A

Hot Plug Detect for IFPE

N/A

(10K pull low)

Performance Mode P0 TDP at Tj = 102 C* (GDDR5)

FBVDDQ PCI Express I/O and GPU Mem NVCLK (4) (1,5) (6)

(W) (W) (MHz)

Products

N12P-GT1

TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

64bit 1GB GDDR5

Physical Strapping pin

ROM_SO FB_0_BAR_SIZE

ROM_SCLK

ROM_SI

STRAP2

STRAP1

STRAP0

/MCLK NVVDD

TBD TBD

Power Rail

+3VS_VGA

(V) (A) (W) (A) (W)

Logical Strapping Bit3

XCLK_417

PCI_DEVID[4]

PCI_DEVID[3]

3GIO_PAD_CFG_ADR[3]

USER[3]

3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]

GPIO6GPIO5

GPU_VID1

0

1

0

1

ROM_SO

PD 10K

N12P-GT1 (40nm)

Device ID

0x0DEB

FB Memory (GDDR5)

Samsung 1800MHz (defaul)

Hynix 1600MHz

K4G10325FE-HC04

H5GQ1H24AFR-T2L

GPU_VID0 VGA_CORE

(GPU+Mem)

FBVDD

(1.35V)(1.35V)

(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

Logical Strapping Bit2

SUB_VENDOR

0.825V

1.075V

PD 15K

P-State

Deep P12

P8

P0

(1.05V)

Logical Strapping Bit1

SLOT_CLK_CFG

RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]

ROM_SIROM_SCLK STRAP0STRAP1STRAP2GPU

PU 20K

PD 15K32Mx32

X76

PLLVDD

I/O and PLLVDD

Logical Strapping Bit0

VGA_DEVICESMB_ALT_ADDR

PEX_PLL_EN_TERM

RAM_CFG[0]

PCI_DEVID[0]PCI_DEVID[1]PCI_DEVID[2]

USER[0]USER[1]USER[2]

PU 45KPD 10K PD 20K32Mx32

PD 35KN12P-GT1

PD 35K

PU 45K

Other

(3.3V)(1.05V)(1.8V)

B B

+3VS_VGA

+1.05VS_VGA

+VGA_CORE

+1.8VS_VGA

+1.35VS

A A

tNVVDD >0

tNV-IFPAB_IOVDD >0

tNV-FBVDDQ >0

1. The ramp rate for any rail must be more than 40us.

2. +VGA_CORE <= +3VS_VGA +0.5V

3. +1.5VS_VGA <= +3VS_VGA +0.5V

4. Optimus follows power sequencing rules specified in discrete GPU design guide.

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Doc ument Number Rev

Date: Sheet

Compal Electronics, Inc.

VGA Notes List

LA-6882P

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D D

+1.05VS

12

R1

24.9_0402_1%

JCPU1A

EDP_COMP

eDP_HP D

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COM PIO

A17

eDP_ICOMPO

B16

eDP_HP D

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX [0]

F16

eDP_TX [1]

C16

eDP_TX [2]

G15

eDP_TX [3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

Sandy Bridge_ rPGA_Rev1p0

ME@

DMI

Intel(R) FDI

eDP

DMI_CRX_PTX_N0<16> DMI_CRX_PTX_N1<16> DMI_CRX_PTX_N2<16> DMI_CRX_PTX_N3<16>

DMI_CRX_PTX_P0<16> DMI_CRX_PTX_P1<16> DMI_CRX_PTX_P2<16> DMI_CRX_PTX_P3<16>

DMI_CTX_PRX_N0<16> DMI_CTX_PRX_N1<16> DMI_CTX_PRX_N2<16> DMI_CTX_PRX_N3<16>

DMI_CTX_PRX_P0<16>

C C

DISCRETE ONLY

12

DIS_ONLY@

12

DIS_ONLY@

12

DIS_ONLY@

12

DIS_ONLY@

12

DIS_ONLY@

B B

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms

24.9_0402_1%

FDI_FSYNC0

R12751K_0402_5%

FDI_FSYNC1

R12761K_0402_5%

R12771K_0402_5%

R12781K_0402_5%

R12791K_0402_5%

+1.05VS

R7

FDI_LSYNC0

FDI_LSYNC1

12

FDI_INT

FDI_FSYNC0<16> FDI_FSYNC1<16>

FDI_INT<16>

FDI_LSYNC0<16> FDI_LSYNC1<16>

DMI_CTX_PRX_P1<16> DMI_CTX_PRX_P2<16> DMI_CTX_PRX_P3<16>

FDI_CTX_PRX_N0<16> FDI_CTX_PRX_N1<16> FDI_CTX_PRX_N2<16> FDI_CTX_PRX_N3<16> FDI_CTX_PRX_N4<16> FDI_CTX_PRX_N5<16> FDI_CTX_PRX_N6<16> FDI_CTX_PRX_N7<16>

FDI_CTX_PRX_P0<16> FDI_CTX_PRX_P1<16> FDI_CTX_PRX_P2<16> FDI_CTX_PRX_P3<16> FDI_CTX_PRX_P4<16> FDI_CTX_PRX_P5<16> FDI_CTX_PRX_P6<16> FDI_CTX_PRX_P7<16>

FDI_FSYNC0 FDI_FSYNC1

FDI_INT

FDI_LSYNC0 FDI_LSYNC1

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_TX#[10] PEG_TX#[11]

PCI EXPRESS* - GRAPHICS

PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_COMP

PCIE_CRX_GTX_N15 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_N10

PCIE_CRX_GTX_N9 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P15 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_P12 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P0

PCIE_CTX_GRX_C_N15 PCIE_CTX_GRX_C_N14 PCIE_CTX_GRX_C_N13 PCIE_CTX_GRX_C_N12 PCIE_CTX_GRX_C_N11 PCIE_CTX_GRX_C_N10 PCIE_CTX_GRX_C_N9 PCIE_CTX_GRX_C_N8 PCIE_CTX_GRX_C_N7 PCIE_CTX_GRX_C_N6 PCIE_CTX_GRX_C_N5 PCIE_CTX_GRX_C_N4 PCIE_CTX_GRX_C_N3 PCIE_CTX_GRX_C_N2 PCIE_CTX_GRX_C_N1 PCIE_CTX_GRX_C_N0

PCIE_CTX_GRX_C_P15 PCIE_CTX_GRX_C_P14 PCIE_CTX_GRX_C_P13 PCIE_CTX_GRX_C_P12 PCIE_CTX_GRX_C_P11 PCIE_CTX_GRX_C_P10 PCIE_CTX_GRX_C_P9 PCIE_CTX_GRX_C_P8 PCIE_CTX_GRX_C_P7 PCIE_CTX_GRX_C_P6 PCIE_CTX_GRX_C_P5 PCIE_CTX_GRX_C_P4 PCIE_CTX_GRX_C_P3 PCIE_CTX_GRX_C_P2 PCIE_CTX_GRX_C_P1 PCIE_CTX_GRX_C_P0

24.9_0402_1%

PCIE_CRX_GTX_N[0..15] <23>

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

PCIE_CRX_GTX_P[0..15] <23>

C1 0.1U_0402_10V6K

1 2

C2 0.1U_0402_10V6K

1 2

C3 0.1U_0402_10V6K

1 2

DIS@

C4 0.1U_0402_10V6K

1 2

DIS@

C5 0.1U_0402_10V6K

1 2

DIS@

C6 0.1U_0402_10V6K

1 2

DIS@

C7 0.1U_0402_10V6K

1 2

DIS@

C8 0.1U_0402_10V6K

1 2

DIS@

C9 0.1U_0402_10V6K

1 2

DIS@

C10 0.1U_0402_10V6K

1 2

DIS@

C11 0.1U_0402_10V6K

1 2

DIS@

C12 0.1U_0402_10V6K

1 2

DIS@

C13 0.1U_0402_10V6K

1 2

DIS@

C14 0.1U_0402_10V6K

1 2

DIS@

C15 0.1U_0402_10V6K

1 2

DIS@

C16 0.1U_0402_10V6K

1 2

DIS@

DIS@ DIS@

DIS@

C17 0.1U_0402_10V6K

1 2

DIS@

C18 0.1U_0402_10V6K

1 2

C19 0.1U_0402_10V6K

1 2

DIS@

C20 0.1U_0402_10V6K

1 2

DIS@

C21 0.1U_0402_10V6K

1 2

DIS@

C22 0.1U_0402_10V6K

1 2

DIS@

C23 0.1U_0402_10V6K

1 2

DIS@

C24 0.1U_0402_10V6K

1 2

DIS@

C25 0.1U_0402_10V6K

1 2

DIS@

C26 0.1U_0402_10V6K

1 2

DIS@

C27 0.1U_0402_10V6K

1 2

DIS@

C28 0.1U_0402_10V6K

1 2

DIS@

C29 0.1U_0402_10V6K

1 2

DIS@

C30 0.1U_0402_10V6K

1 2

DIS@

C31 0.1U_0402_10V6K

1 2

DIS@

C32 0.1U_0402_10V6K

1 2

DIS@

DIS@ DIS@

DIS@

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 mohms

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

*

PCIE_CTX_GRX_N15 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P15 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P0

PCIE_CTX_GRX_N[0..15] <23>

PCIE_CTX_GRX_P[0..15] <23>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(1/7) DMI,FDI,PEG

LA-6882P

1

563Wednesday , October 06, 2010

of

0.2

CyberForum.ru

5

D D

+1.05VS

12

R9

62_0402_5%

H_PROCHOT#<45>

H_PROCHOT#

closs to EC 250~750mils

H_PECI<19,45>

H_THRMTRIP#<19>

H_SNB_IVB#<18>

4

0_0402_5%

1 2

56_0402_5%

R14

R15

1 2

R19

0_0402_5%

1 2

H_CATERR#

H_PECI_ISO

H_PROCHOT#_R

H_THEMTRIP#_R

C26

AN34

AL33

AN33

AL32

AN32

JCPU1B

PROC_SELECT#

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

3

BCLK

BCLK#

MISCTHERMALPWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

CLK_CPU_DMI_R

A28

CLK_CPU_DMII#_R

A27

R12 1K_0402_5%R12 1K_0402_5%

A16

R13 1K_0402_5%R13 1K_0402_5%

A15

H_DRAMRST#

R8

SM_RCOMP0

AK1

SM_RCOMP1

A5

SM_RCOMP2

A4

2

R10 0_0402_5%R10 0_0402_5%

1 2

R11

1 2

0_0402_5%

12 12

H_DRAMRST# <7>

R16 140_0402_1%R16 140_0402_1% R17 25.5_0402_1%R17 25.5_0402_1% R18 200_0402_1%R18 200_0402_1%

+1.05VS

12 12 12

DG1.0

CLK_CPU_DMI <15> CLK_CPU_DMI# <15>

DDR3 Compensation Signals

1

PRDY#

R22

C C

R26

R338

R26

1 2

10K_0402_5%

+3VS

1 2

R27

+3VALW

1

C33

0.1U_0402_16V4Z

2

1

B

2

A

SUSP<10,51,57>

1 2

5

3

U1

P

PM_SYS_PWRGD_BUF

4

O

G

74AHC1G09GW_TSSOP5

SUSP

0_0402_5%

H_CPUPWRGD<19>

B B

PM_DRAM_PWRGD<16>

0_0402_5%

10K_0402_5%

2

G

H_PM_SYNC<16>

+1.5V_CPU_VDDQ

12

@

R33

R33 39_0402_5%

39_0402_5%

13

D

@

Q1

Q1 2N7002_SOT23

2N7002_SOT23

S

12

R30

R30 200_0402_5%

200_0402_5%

R22

0_0402_5%

1 2

R29

1 2

130_0402_5%

H_PM_SYNC_R

H_CPUPWRGD_R

PM_DRAM_PWRGD_R

BUF_CPU_RST#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

Sandy Bridge_ rPGA_Rev1p0

ME@

12

R35

@R35

@

0_0402_5%

+1.05VS

R32

75_0402_5%

R34

43_0402_1%

1 2

SN74LVC1G07DCKR_SC70-5

Buffered reset to CPU

0.1U_0402_16V4Z

12

BUFO_CPU_RST#

JTAG & BPM

C34

U2

4

PREQ#

TRST#

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

+3VS

1

2

5

1

P

NC

Y

2

A

G

3

TCK TMS

TDO

TDI

AP27

AR26 AR27 AP30

AR28 AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

PLT_RST#

XDP_PREQ#

XDP_TCK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7

3V

PLT_RST# <18>

XDP_TMS

R20 51_0402_5%R20 51_0402_5%

XDP_TDI

R21 51_0402_5%R21 51_0402_5%

XDP_TDO

R23 51_0402_5%R23 51_0402_5%

XDP_TCK

R24 51_0402_5%R24 51_0402_5%

XDP_TRST#

R25 51_0402_5%R25 51_0402_5%

R28 1K_0402_5%R28 1K_0402_5%

12

+3VS

XDP_PRDY#

AP29

+1.05VS

12 12 12

12 12

PU/PD for JTAG signals

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

LA-6882P

1

663Wednesday , October 06, 2010

0.2

of

CyberForum.ru

5

JCPU1C

4

3

JCPU1D

2

1

DDR_A_D[0..63]<12>

D D

C C

B B

DDR_A_BS0<12> DDR_A_BS1<12> DDR_A_BS2<12>

DDR_A_CAS#<12> DDR_A_RAS#<12> DDR_A_WE#<12>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

G10

N10

M10

AG6 AG5 AK6 AK5 AH5 AH6

AK8

AK9 AH8 AH9 AL9

AL8 AP11 AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10 AF10

AE8 AD9 AF9

F10

AJ5 AJ6 AJ8

AJ9

C5 D5 D3 D2 D6 C6 C2 C3

F8

G9

F9

F7 G8 G7

K4

K5

K1

K2 M8

N8

N7

M9

N9 M7

V6

J1 J5 J4 J2

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

RSVD_TP[10]

DDR SYSTEM MEMORY A

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

RSVD_TP[1] RSVD_TP[2] RSVD_TP[3]

RSVD_TP[4] RSVD_TP[5] RSVD_TP[6]

SA_CS#[0]

SA_CS#[1] RSVD_TP[7] RSVD_TP[8]

SA_ODT[0]

SA_ODT[1] RSVD_TP[9]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

M_CLK_DDR0 <12> M_CLK_DDR#0 <12> DDR_CKE0_DIMMA <12>

M_CLK_DDR1 <12> M_CLK_DDR#1 <12> DDR_CKE1_DIMMA <12>

DDR_CS0_DIMMA# <12> DDR_CS1_DIMMA# <12>

M_ODT0 <12> M_ODT1 <12>

DDR_A_DQS#[0..7] <12>

DDR_A_DQS[0..7] <12>

DDR_A_MA[0..15] <12> DDR_B_MA[0..15] <13>

DDR_B_D[0..63]<13>

DDR_B_BS0<13> DDR_B_BS1<13> DDR_B_BS2<13>

DDR_B_CAS#<13> DDR_B_RAS#<13> DDR_B_WE#<13>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AM5 AM6 AR3

AN3 AN2 AN1

AN9

AN8 AR6 AR5 AR9

AJ11

AH11

AR8

AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA10

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34]

AP3

SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40] SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

RSVD_TP[11] RSVD_TP[12] RSVD_TP[13]

RSVD_TP[14] RSVD_TP[15] RSVD_TP[16]

RSVD_TP[17] RSVD_TP[18]

RSVD_TP[19] RSVD_TP[20]

DDR SYSTEM MEMORY B

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

AE2 AD2 R9

AE1 AD1 R10

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

M_CLK_DDR2 <13> M_CLK_DDR#2 <13> DDR_CKE2_DIMMB <13>

M_CLK_DDR3 <13> M_CLK_DDR#3 <13> DDR_CKE3_DIMMB <13>

DDR_CS2_DIMMB# <13> DDR_CS3_DIMMB# <13>

M_ODT2 <13> M_ODT3 <13>

DDR_B_DQS#[0..7] <13>

DDR_B_DQS[0..7] <13>

Sandy Bridge_ rPGA_Rev1p0

Deciphered Date

Sandy Bridge_ rPGA_Rev1p0

ME@

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

LA-6882P

1

763Wednesday , October 06, 2010

of

0.2

Sandy Bridge_ rPGA_Rev1p0

ME@

R36

@R36

@

0_0402_5%

1 2

D

S

D

S

DDR3_DRAMRST#_RH_DRAMRST#

1 2

13

Q2

G

BSS138_NL_SOT23-3

2

1

C35

0.047U_0402_16V4Z

2

H_DRAMRST#<6>

R39

4.99K_0402_1%

A A

DRAMRST_CNTRL_PCH<15>

5

R40

0_0402_5%

1 2

DRAMRST_CNTRL

+1.5V

12

R37

1K_0402_5%

R38

R38 1K_0402_5%

1K_0402_5%

1 2

Eiffel used 0.01u Module design used 0.047u

4

DDR3_DRAMRST# <12,13>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

Compal Secret Data

CyberForum.ru

5

4

3

2

1

CFG Straps for Processor

CFG2

D D

JCPU1E

L7

RSVD28

AG7

AK28

CFG[0]

AK29

CFG2

CFG4 CFG5 CFG6 CFG7

C C

B B

R64

1K_0402_1%

@

T9 PADT9 PAD T10 PADT10 PAD T11 PADT11 PAD T12 PADT12 PAD

12

R353

1K_0402_1%

@

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

B4

RSVD6

D1

RSVD7

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

A19

VCCIO_SEL

J15

RSVD27

Sandy Bridge_ rPGA_Rev1p0

ME@

RESERVED

RSVD29 RSVD30 RSVD31 RSVD32

RSVD33 RSVD34 RSVD35

RSVD37 RSVD38 RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44 RSVD45

RSVD46 RSVD47 RSVD48 RSVD49 RSVD50

RSVD51 RSVD52

VCC_DIE_SENSE

RSVD54 RSVD55

RSVD56 RSVD57 RSVD58

KEY

AE7 AK2 W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AH27

AN35 AM35

AT2 AT1 AR1

B1

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

*

Display Port Presence Strap

CFG4

*

T13PAD T13PAD

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

CFG[6:5]

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

12

R41

R41 1K_0402_1%

1K_0402_1%

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

CFG4

1K_0402_1%

12

R42

@ R42

@

1K_0402_1%

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG6

CFG5

CFG7

@R43

@

12

R44

@R44

12

@R45

@

1K_0402_1%

R45 1K_0402_1%

1K_0402_1%

R43

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7

de assertion

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

Compal Secret Data

Deciphered Date

0: PEG Wait for BIOS for training

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

LA-6882P

1

863Wednesday , October 06, 2010

0.2

of

CyberForum.ru

5

+CPU_CORE

D D

+CPU_CORE

C C

+CPU_CORE

B B

A A

(6/16 change 10uF_0603_6.3V)*5

10U_0805_6.3V6M

1

2

10U_0603_6.3V6M

1

2

10U_0805_6.3V6M

1

C36

2

C48

1

2

10U_0805_6.3V6M

1

C37

C38

2

C49

10U_0603_6.3V6M

C49

10U_0603_6.3V6M

C50

10U_0603_6.3V6M

C50

10U_0603_6.3V6M

1

2

(22uF_0805_6.3V)*16

C66

22U_0805_6.3V6M

C66

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

1

2

(330uF)*4

C67

22U_0805_6.3V6M

C67

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

C74

1

2

22U_0805_6.3V6M

C79

1

2

22U_0805_6.3V6M

1

2

1

+

2

C68

22U_0805_6.3V6M

C68

22U_0805_6.3V6M

1

2

C75

C76

22U_0805_6.3V6M

C76

22U_0805_6.3V6M

1

2

C80

C81

22U_0805_6.3V6M

C81

22U_0805_6.3V6M

1

2

C84

C85

22U_0805_6.3V6M@C85

22U_0805_6.3V6M

1

@

2

330U_X_2VM_R6M

1

C89

C88

+

2

10U_0805_6.3V6M

1

C39

2

C51

10U_0603_6.3V6M

C51

10U_0603_6.3V6M

1

2

C70

22U_0805_6.3V6M

C70

22U_0805_6.3V6M

C77

22U_0805_6.3V6M

C77

22U_0805_6.3V6M

C82

22U_0805_6.3V6M

C82

22U_0805_6.3V6M

C86

22U_0805_6.3V6M@C86

22U_0805_6.3V6M

@

330U_X_2VM_R6M

1

C90

+

2

4

POWER

JCPU1F

POWER

3

2

1

Cap quantity follow HR_PDDG_Rev07

QC=94A

10U_0805_6.3V6M

1

C40

2

C52

10U_0603_6.3V6M

C52

10U_0603_6.3V6M

1

2

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M@C87

22U_0805_6.3V6M

1

2

330U_X_2VM_R6M

C53

10U_0603_6.3V6M@C53

10U_0603_6.3V6M

1

@

2

C71

C78

C83

C87

@

C91

DC=53A

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

CORE SUPPLY

SENSE LINES SVID

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30

PEG AND DDR

VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

VIDALERT#

VIDSCLK VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE VSSIO_SENSE

AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

AJ29 AJ30 AJ28

AJ35 AJ34

B10 A10

VCCSENSE_R VSSSENSE_R

VSSIO_SENSE

18A

+1.05VS

1

2

1

2

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

R1294 10_0402_1%R1294 10_0402_1%

C41

22U_0805_6.3V6M

C41

22U_0805_6.3V6M

C42

22U_0805_6.3V6M

C42

22U_0805_6.3V6M

1

2

C57

22U_0805_6.3V6M

C57

22U_0805_6.3V6M

C58

22U_0805_6.3V6M

C58

22U_0805_6.3V6M

1

2

1

+

C922

C922 330U_2.5V_M

330U_2.5V_M

2

OSCAN

(330U 2.5V M 6.3X5.9 R15M)*1=(SF000002000)

R47 43_0402_5%R47 43_0402_5% R48 0_0402_5% R48 0_0402_5% R49 0_0402_5% R49 0_0402_5%

R50 130_0402_5%R50 130_0402_5%

VCC_SENCE 100ohm +-1% pull-up to VCC near processor

R52 0_0402_5%R52 0_0402_5%

1 2

R53 0_0402_5%R53 0_0402_5%

1 2

12

VCCIO_SENSE <58>

R1297

R1297 10_0402_1%

10_0402_1%

1 2

22uF*7 NO-STUFF

(22uF_0805_6.3V)*13

C44

22U_0805_6.3V6M

C44

22U_0805_6.3V6M

C43

22U_0805_6.3V6M

C43

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M@C59

22U_0805_6.3V6M

1

2

1 2 1 2 1 2

+1.05VS

C59

@

2

22U_0805_6.3V6M@C60

22U_0805_6.3V6M

1

2

1

+

2

12

+CPU_CORE

C60

@

330U_2.5V_M

1

2

1

2

C288

12

R51

R51 100_0402_1%

100_0402_1%

12

R54

100_0402_1%

C54

22U_0805_6.3V6M

C54

22U_0805_6.3V6M

C61

22U_0805_6.3V6M@C61

22U_0805_6.3V6M

+1.05VS

@

1

+

2

330U_D2_2.5VY_R9M

12

+1.05VS

C45

22U_0805_6.3V6M

C45

22U_0805_6.3V6M

1

2

C62

22U_0805_6.3V6M@C62

22U_0805_6.3V6M

1

@

2

C69

@

R46

R46 75_0402_5%

75_0402_5%

12

@

27.4_0402_1%

C46

22U_0805_6.3V6M

C46

22U_0805_6.3V6M

1

2

C63

22U_0805_6.3V6M@C63

22U_0805_6.3V6M

1

@

2

1

+

2

VR_SVID_CLK

R1295

@

27.4_0402_1%

+1.05VS

C56

22U_0805_6.3V6M

C56

22U_0805_6.3V6M

C47

22U_0805_6.3V6M

C47

C55

22U_0805_6.3V6M

C55

22U_0805_6.3V6M

1

2

C64

22U_0805_6.3V6M@C64

22U_0805_6.3V6M

1

@

2

330U_D2_2.5VY_R9M

C72

22U_0805_6.3V6M

1

2

C65

22U_0805_6.3V6M@C65

22U_0805_6.3V6M

1

@

2

330U_D2_2.5VY_R9M

C73

1

+

@

2

series-resistors close to VR

VR_SVID_ALRT# <60> VR_SVID_CLK <60> VR_SVID_DAT <60>

R1296

12

VCCSENSE <60> VSSSENSE <60>

Sandy Bridge_ rPGA_Rev1p0

ME@

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

Compal Secret Data

Deciphered Date

VSS_SENCE 100ohm +-1% pull-down to GND near processor

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(5/7) PWR,BYPASS

LA-6882P

1

963Wednesday , October 06, 2010

of

0.2

CyberForum.ru

5

4

3

2

1

+1.5V +1.5V_CPU_VDDQ

6/24 R56 change to 15K

SUSP<6,51,57>

100K_0402_5%

C100

22U_0805_6.3V6M

C100

22U_0805_6.3V6M

1

2

UMA@

1

2

UMA@

R667

2

22U_0805_6.3V6M

22U_0805_6.3V6M@C110

22U_0805_6.3V6M

+3VALW

G

C101

UMA@

C110

@

1

+

2

12

13

D

S

1

2

1

2

330U_2.5V_M

D D

UMA@

1 2

C98

22U_0805_6.3V6M

C98

22U_0805_6.3V6M

1

2

UMA@

C108

22U_0805_6.3V6M

C108

22U_0805_6.3V6M

1

2

UMA@

R580_0402_5% R580_0402_5%

@

R590_0402_5%@R590_0402_5%

C99

22U_0805_6.3V6M

C99

22U_0805_6.3V6M

1

2

UMA@

C109

22U_0805_6.3V6M

C109

22U_0805_6.3V6M

1

2

CPU1.5V_S3_GATE<45>

SUSP#<45,51,56,57,58,59>

+VGFX_CORE

12

0_0402_5%

R60

DIS_ONLY@

C C

DIS_ONLY@

1 2

R6680_0402_5%@R6680_0402_5%

@

+VSB

12

R56

15K_0402_1%

RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3

Q7

Q7 2N7002_SOT23

2N7002_SOT23

C105

22U_0805_6.3V6M

C105

22U_0805_6.3V6M

UMA@

22U_0805_6.3V6M@C111

22U_0805_6.3V6M

@

C102

C103

22U_0805_6.3V6M

C103

22U_0805_6.3V6M

1

2

UMA@

C111

C112

22U_0805_6.3V6M@C112

22U_0805_6.3V6M

1

2

@

330U_D2_2.5VY_R9M

C116

1

C115

+

2

22U_0805_6.3V6M

C104

22U_0805_6.3V6M

C104

22U_0805_6.3V6M

1

2

UMA@

C113

22U_0805_6.3V6M@C113

22U_0805_6.3V6M

1

2

@

13

D

Q4

2

2N7002_SOT23

G

S

C106

22U_0805_6.3V6M

C106

22U_0805_6.3V6M

C107

22U_0805_6.3V6M

C107

22U_0805_6.3V6M

1

2

UMA@

OSCAN

B B

A A

(330U 2.5V M 6.3X4.2 R17M)*1=(SF000002Z00)

+1.8VS

R67

0_0805_5%

1 2

22U_0805_6.3V6M@C154

22U_0805_6.3V6M

1

2

@

+1.8VS_VCCPLL VCCSA_SENSE

C131

1U_0402_6.3V6K

C131

1U_0402_6.3V6K

C132

1U_0402_6.3V6K

C132

C130

10U_0805_6.3V6M

C130

10U_0805_6.3V6M

C345

22U_0805_6.3V6M@C345

22U_0805_6.3V6M

C154

1

2

@

2

1U_0402_6.3V6K

1

2

J1

@J1

@

1 2

PAD-OPEN 4x4m

U3

8

D

7

D

6

D

5

D

DMN3030LSS-13_SOP8L-8

JCPU1G

AT24

VAXG1

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24

AM24

VAXG25

AM23

VAXG26

AM21

VAXG27

AM20

VAXG28

AM18

VAXG29

AM17

VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36

AK24

VAXG37

AK23

VAXG38

AK21

VAXG39

AK20

VAXG40

AK18

VAXG41

AK17

VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48

AH24

VAXG49

AH23

VAXG50

AH21

VAXG51

AH20

VAXG52

AH18

VAXG53

AH17

VAXG54

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

Sandy Bridge_ rPGA_Rev1p0

ME@

1

S

2

S

3

S

4

G

12

R57

R57 330K_0402_5%

330K_0402_5%

@

POWER

1.8V RAIL

220_0402_5%

2N7002_SOT23

1

C97

0.1U_0603_25V7K

2

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

VREFMISC

GRAPHICS

DDR3 -1.5V RAILS

SA RAIL

R55

Q3

VAXG_SENSE

SM_VREF

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

VCCSA_SENSE

FC_C22

VCCSA_VID1

12

1

C92

@ C92

@

0.1U_0402_10V6K

2

13

D

G

S

AK35 AK34

AL1

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

M27 M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

RUN_ON_CPU1.5VS3#

2

+1.5V_CPU_VDDQ

VCC_AXG_SENSE <60> VSS_AXG_SENSE <60>

R61

0_0402_5%

+V_SM_VREF_CNT +V_SM_VREF

C114

0.1U_0402_16V4Z

C117

10U_0603_6.3V6M

C117

10U_0603_6.3V6M

1

2

+VCCSA

C124

10U_0805_6.3V6M

C124

10U_0805_6.3V6M

1

2

H_FC_C22

100K_0402_5%

1

R666

@

2

1 2

C120

10U_0603_6.3V6M

C120

C119

10U_0603_6.3V6M

C119

10U_0603_6.3V6M

1

2

C126

10U_0805_6.3V6M

C126

10U_0805_6.3V6M

1

2

1 2

@

10U_0603_6.3V6M

1

2

1

2

1

2

+VCCSA

C127

10U_0805_6.3V6M@C127

10U_0805_6.3V6M

@

VCCSA_SEL <57>

C118

10U_0603_6.3V6M

C118

10U_0603_6.3V6M

1

2

C125

10U_0805_6.3V6M

C125

10U_0805_6.3V6M

1

2

R68 0_0402_5%

R69 1K_0402_1%R69 1K_0402_1%

RUN_ON_CPU1.5VS3

C121

10U_0603_6.3V6M

C121

10U_0603_6.3V6M

1

+

2

+1.5V_CPU_VDDQ

1

C122

10U_0603_6.3V6M

C122

10U_0603_6.3V6M

1

+

2

1 2

330U_D2_2.5VY_R9M

C128

1 2

2

1

330U_D2_2.5VY_R9M

C123

@

R65 100_0402_1%R65 100_0402_1%

R66

+1.5V

0.1U_0402_10V6K

0.1U_0402_10V6K C95

C95

1

2

12

3

Q5

@Q5

@

AP2302GN-HF_SOT23-3

VCCSA_SENSE

0_0402_5%

0.1U_0402_10V6K

C96

C286

1

2

VSSSA_SENSE <57>

0.1U_0402_10V6K

0.1U_0402_10V6K C287

C287

1

2

VCCSA_SENSE <57>

+1.5V_CPU_VDDQ

12

R62

R62 100_0402_1%

100_0402_1%

12

R63

R63 100_0402_1%

100_0402_1%

6/9 change 330U to 22U X2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(6/7) PWR

LA-6882P

1

0.2

10 63Wednesday , October 06, 2010

0.2

of

CyberForum.ru

5

D D

C C

B B

4

JCPU1H

AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10

AR25 AR22 AR19 AR16 AR13 AR10

AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AJ25

AT7 AT4 AT3

AR7 AR4 AR2

AP7 AP4 AP1

AN7 AN4

AL7 AL4 AL2

AK7 AK4

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

3

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

VSS

2

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

1

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

Sandy Bridge_ rPGA_Rev1p0

ME@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

Sandy Bridge_ rPGA_Rev1p0

ME@

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(7/7) VSS

LA-6882P

1

0.2

11 63Wednesday , October 06, 2010

0.2

of

CyberForum.ru

5

+VREF_DQ_DIMMA

0.1U_0402_10V6K

2.2U_0603_6.3V6K

C133

1

D D

C C

B B

A A

5

1

2

DDR_CKE0_DIMMA<7>

DDR_A_BS2<7>

M_CLK_DDR0<7> M_CLK_DDR#0<7>

DDR_A_BS0<7>

DDR_A_WE#<7> DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

+3VS

DDR_A_D0

C134

DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS# M_ODT0

DDR_A_MA13 DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

1 2

10K_0402_5%

2.2U_0603_6.3V6K

0.1U_0402_10V6K

C155

C156

1

2

+1.5V +1.5V

R81

R83

10K_0402_5%

R83

10K_0402_5%

12

4

4BA2/6W

4BA2/6W4BA2/6W

DDR3 SO-DIMM A

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2 DQS247VSS17

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4526-0100

ME@

4

VSS3

DQS#0

DQS0 VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45 VSS35 DQS#5

DQS5 VSS38

DQ46

DQ47 VSS40

DQ52

DQ53 VSS42

VSS43

DQ54

DQ55 VSS45

DQ60

DQ61 VSS47 DQS#7

DQS7 VSS50

DQ62

DQ63 VSS52

EVENT#

VTT2

2 4

DQ4

6

DQ5

8 10 12 14 16

DQ6

18

DQ7

20 22 24 26 28

DM1

30 32 34 36 38 40 42 44 46

DM2

48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

80

A14

82 84

A11

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102

CK1

104 106 108

BA1

110 112 114

S0#

116 118 120 122

NC2

124 126 128 130 132 134 136

DM4

138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170

DM6

172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

SDA

202

SCL

204

206

G2

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR_A_DM1 DDR3_DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA#

M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

SMB_DATA_S3 SMB_CLK_S3

+0.75VS

1/76BA1/86W

1/76BA1/86W1/76BA1/86W

DDR3_DRAMRST# <7,13>

DDR_CKE1_DIMMA <7>

M_CLK_DDR1 <7> M_CLK_DDR#1 <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7> M_ODT0 <7>

M_ODT1 <7>

0.1U_0402_10V6K

0.1U_0402_10V6K C135

C135

1

2

SMB_DATA_S3 <13,15,37> SMB_CLK_S3 <13,15,37>

3

DDR_A_D[0..63]<7>

DDR_A_DQS[0..7]<7>

DDR_A_DQS#[0..7]<7>

DDR_A_MA[0..15]<7>

Layout Note: Place near DIMM

+1.5V

12

R72

1K_0402_1%

+VREF_CA

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K C136

C136

1

2

3

12

R73

1K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

10U_0603_6.3V6M

C137

@

Layout Note: Place near DIMM

C150

10U_0603_6.3V6M

C138

1

@

2

+0.75VS

1U_0402_6.3V6K

C151

1U_0402_6.3V6K

C151

1U_0402_6.3V6K

1

2

2008/10/31 2009/10/31

C152

C139

1

2

1U_0402_6.3V6K

1

2

+1.5V

10U_0603_6.3V6M

C140

1

2

C153

1U_0402_6.3V6K

C153

1U_0402_6.3V6K

1

2

Compal Secret Data

2

R70

1K_0402_1%

(220uF_6.3V_5.9L_ESR15m)*1=(SF000001500)

OSCAN

(10uF_0603_6.3V)*8

(0.1uF_402_10V)*4

10U_0603_6.3V6M

C141

1

2

Deciphered Date

2

C142

1

2

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

Layout Note: Place near DIMM

C143

1

+1.5V

12

+VREF_DQ_DIMMA

12

R71

10U_0603_6.3V6M

1

2

C144

0.1U_0402_10V6K

0.1U_0402_10V6K C145

C145

1

2

0.1U_0402_10V6K

0.1U_0402_10V6K C146

C146

1

2

Title

Size Doc ument Number Rev

Custom

Date: Sheet

0.1U_0402_10V6K

C147

C148

1

2

1

+

C149

C149 220U_6.3V_M

220U_6.3V_M

2

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

LA-6882P

1

12 63Wednesday, October 06, 2010

of

0.2

CyberForum.ru

5

+VREF_DQ_DIMMB

C177

C157

1

2

0.1U_0402_10V6K

0.1U_0402_10V6K C178

C178

+VREF_DQ_DIMMB

DDR_B_D0 DDR_B_D1

DDR_B_DM0

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_DM3

DDR_B_D26 DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

M_CLK_DDR2 M_CLK_DDR#2

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13 DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_DM7

DDR_B_D58 DDR_B_D59

R95

1 2

10K_0402_5%

1 2

R97 10K_0402_5%R97 10K_0402_5%

0.1U_0402_10V6K

2.2U_0603_6.3V6K

C158

1

D D

C C

B B

A A

+3VS

5

1

2

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7> M_CLK_DDR#2<7>

DDR_B_BS0<7>

DDR_B_WE#<7> DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

2.2U_0603_6.3V6K

1

2

+1.5V

4BA2/6W

4BA2/6W4BA2/6W

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1 VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3 A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4926-0100

LCN_DAN06-K4926-0100 ME@

ME@

4

VSS3

DQS0 VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

4

3

DDR_B_D[0..63]<7>

DDR_B_DQS[0..7]<7>

+1.5V

2

DDR_B_D4

4

DQ4 DQ5

DQ6 DQ7

DM1

DM2

A15 A14

A7

A6 A4

A2 A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA

SCL

G2

6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR_B_DM1 DDR3_DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2

DDR_B_D22 DDR_B_D23

DDR_B_D28 DDR_B_D29

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D30 DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

M_CLK_DDR3 M_CLK_DDR#3

DDR_B_BS1 DDR_B_RAS#

DDR_CS2_DIMMB# M_ODT2

M_ODT3

DDR_B_D36 DDR_B_D37

DDR_B_DM4

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_DM6

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

SMB_DATA_S3 SMB_CLK_S3

1/76BA1/86W

1/76BA1/86W1/76BA1/86W

DDR3_DRAMRST# <7,12>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7> M_CLK_DDR#3 <7>

DDR_B_BS1 <7> DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7> M_ODT2 <7>

M_ODT3 <7>

0.1U_0402_10V6K

C159

1

2

SMB_DATA_S3 <12,15,37> SMB_CLK_S3 <12,15,37>

+0.75VS

+VREF_CB

2.2U_0603_6.3V6K

C160

1K_0402_1%

R86

1K_0402_1%

R87

+1.5V

3

DDR_B_DQS#[0..7]<7>

DDR_B_MA[0..15]<7>

Layout Note: Place near DIMM

12

10U_0603_6.3V6M

C161

12

1

@

2

Layout Note: Place near DIMM

+0.75VS

C173

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C163

C162

1

@

2

C174

1U_0402_6.3V6K

C174

1U_0402_6.3V6K

C175

1U_0402_6.3V6K

C175

1U_0402_6.3V6K

1

2

(10uF_0603_6.3V)*8

(0.1uF_402_10V)*4

+1.5V

10U_0603_6.3V6M

C164

C165

1

2

DDR_B_DM0 DDR_B_DM1

1U_0402_6.3V6K

DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

Compal Secret Data

C176

1

2

2008/10/31 2009/10/31

2

10U_0603_6.3V6M

C167

C166

1

2

Layout Note: Place near DIMM

Deciphered Date

2

C168

1

+1.5V

12

R84

1K_0402_1%

10U_0603_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K C169

C169

1

2

0.1U_0402_10V6K

0.1U_0402_10V6K C170

C170

1

2

0.1U_0402_10V6K

C171

C172

1

2

C172

1

2

Compal Electronics, Inc.

Title

Size Doc ument Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

R85

+VREF_DQ_DIMMB

12

LA-6882P

1

0.2

of

13 63Wednesday, October 06, 2010

of

13 63Wednesday, October 06, 2010

of

13 63Wednesday, October 06, 2010

CyberForum.ru

5

W=20milsW=20mils

+RTCBATT+RTCVCC

R99

1K_0402_5%

1

C179

C179 1U_0603_10V4Z

1U_0603_10V4Z

2

D D

+RTCVCC

R101 1M_0402_5%R101 1M_0402_5%

R102 330K_0402_5%R102 330K_0402_5%

R1330 330K_0402_5%

*

1 2

@

INTVRMEN

H

烉烉烉烉

Integrated VRM enable

L

烉烉烉烉

Integrated VRM disable

12

CLRP1

SHORT PADS

SM_INTRUDER#

PCH_INTVRMEN

+RTCVCC

R103 20K_0402_5%R103 20K_0402_5%

R100 20K_0402_5%R100 20K_0402_5%

(INTVRMEN should always be pull high.)

+3VS

R105 1K_0402_5%@R105 1K_0402_5%@

1 2

HIGH= Enable ( No Reboot ) LOW= Disable (Default)

*

C C

+3VALW

R106 1K_0402_5%@R106 1K_0402_5%@

Low = Disabled (Default)

*

High = Enabled [Flash Descriptor Security Overide]

+3VALW

R108 1K_0402_5% R108 1K_0402_5%

12

HDA_SPKR

HDA_SDOUT

ME_FLASH<45>

HDA_SYNC

This signal has a weak internal pull-down

On Die PLL VR Select is supplied by

1.5V when smapled high

*

1.8V when sampled low Needs to be pulled High for Huron River platfrom

R112

33_0402_5%

HDA_BIT_CLK

HDA_BITCLK_AUDIO<42>

HDA_SYNC_AUDIO<42>

B B

HDA_RST_AUDIO#<42>

HDA_SDOUT_AUDIO<42>

+3VALW +3VALW+3VALW

12

R121

200_0402_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

12

R125

100_0402_1%

1 2

33_0402_5%

1 2

33_0402_5%

1 2

33_0402_5%

1 2

12

R122

200_0402_5%

12

R126

R126 100_0402_1%

100_0402_1%

R114

R116

R118

HDA_SYNC_R

HDA_RST#

HDA_SDOUT

12

R123

200_0402_5%

12

R128

100_0402_1%

+3VS

G

2

D

S

D

S

1 2

R325

@R325

@

0_0402_5%

6/17 follow module design

4MB SPI ROM FOR ME & Non-share ROM.

18P_0402_50V8J

C183

1U_0603_10V4Z

1 2

C182

1U_0603_10V4Z

HDA_SPKR<42>

HDA_SDIN0<42>

ME_FLASH

R107 1K_0402_1%@R107 1K_0402_1%@

1 2

Kill_SW#<49>

Q10

Q10 BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

HDA_SYNC

13

+3VS

DPDG1.1

6/30 update R121, R122, R123

A A

SPI_SB_CS1# SPI_SO_R SPI_SO_L1

5

R1337

@R1337

@

0_0402_5%

1 2

33_0402_5%

@

R1338

1 2

R98 10M_0402_5%R98 10M_0402_5%

1

C180

2

CMOS

SHORT PADS

1

12

2

SHORT PADS

1

12

2

R109

1 2

0_0402_5%

R110

51_0402_5%

R1334

1 2

@

R1335

1 2

@

SPI_SB_CS1#_R

SPI_WP#_1

4

CLRP2

CLRP3

Y1

OSC4OSC

NC3NC

12

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDIN0

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

SPI_CLK_PCH

SPI_SB_CS0#

SPI_SB_CS1#

SPI_SI

SPI_SO_R

1

C181

C181 18P_0402_50V8J

18P_0402_50V8J

2

32.768KHZ_12.5PF_9H03200413

HDA_SDOUT

PCH_GPIO33

Kill_SW#

PCH_RTCX1

PCH_RTCX2

For Fast Boot

SPI_WP#_1

3.3K_0402_5%

SPI_HOLD#_1

3.3K_0402_5%

U61

1

CS#

2

SO

3

WP#

4

GND

S IC FL 32M W25Q32BVSSIG SOIC 8P

@

4

VCC

HOLD#

SCLK

8 7 6 5

SI

U4A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK _EN# / GPIO33

N32

HDA_DOCK _RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

COUGARPOINT_FCBGA989

+3VS

C923

@

1 2

0.1U_0402_16V4Z

SPI_HOLD#_1 SPI_CLK_PCH_1 SPI_SI_R1

33_0402_5%

33_0402_5% R1340

R1340

1 2 1 2

33_0402_5%

R1339

@

3

LPC_AD0

LDRQ0#

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATALED#

3

SPI_SB_CS0#_R<45>

C38

LPC_AD1

A38

LPC_AD2

B37

LPC_AD3

C37

LPC_FRAME#

D36

E36 K36

SERIRQ

V5

AM3 AM1

SATA_ITX_C_DRX_N0

AP7

SATA_ITX_C_DRX_P0

AP5

AM10 AM8

SATA_ITX_C_DRX_N1

AP11

SATA_ITX_C_DRX_P1

AP10

AD7 AD5

SATA_ITX_C_DRX_N2

AH5

SATA_ITX_C_DRX_P2

AH4

AB8 AB10 AF3 AF1

Y7 Y5

SATA_ITX_C_DRX_N4

AD3

SATA_ITX_C_DRX_P4

AD1

Y3 Y1 AB3 AB1

Y11

SATA_COMP

Y10

AB12

SATA3_COMP

AB13

RBIAS_SATA3

AH1

R117 10K_0402_5%R117 10K_0402_5%

HDD_LED#

P3

PCH_GPIO21

V14

SATA_DET#

P1

R316 10K_0402_5%R316 10K_0402_5%

2009/12/01 2010/12/31

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ1# / GPIO23

RTCIHDA

SATA 6G

SATA

SATAICOMPO

JTAG

SPI

@

SPI_CLK_PCH

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATA0GP / GPIO2 1

SATA1GP / GPIO1 9

SPI_SI

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LPC_AD0 <37,45> LPC_AD1 <37,45> LPC_AD2 <37,45> LPC_AD3 <37,45>

LPC_FRAME# <37,45>

R104 10K_0402_5%R104 10K_0402_5%

R111

37.4_0402_1%

1 2

R113

49.9_0402_1%

1 2

R115 750_0402_1%R115 750_0402_1%

1 2

12

R119

10K_0402_5%

12

Q134

SPI_SB_CS0#_R

Q134

2N7002_SOT23-3

Compal Secret Data

EC and Mini card debug port

12

SERIRQ <45>

+1.05VS_VCC_SATA

+1.05VS_SATA3

HDD_LED# <50>

12

SATA_DET# <37>

+3VS

12

R1346

@ R1346

@

10K_0402_5%

SPI_SB_CS1#_R

13

D

2

G

S

@

Deciphered Date

ESATA@

+3VS

2

+3VS

SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0

C1840.01U_0402_16V7K C1840.01U_0402_16V7K

12

C1850.01U_0402_16V7K C1850.01U_0402_16V7K

12

SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1

C2730.01U_0402_16V7K C2730.01U_0402_16V7K

12

C2720.01U_0402_16V7K C2720.01U_0402_16V7K

12

SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2

SATA_ITX_DRX_N2_CONN

C1860.01U_0402_16V7K C1860.01U_0402_16V7K

12

SATA_ITX_DRX_P2_CONN

C1870.01U_0402_16V7K C1870.01U_0402_16V7K

12

SATA_DTX_C_IRX_N4 SATA_DTX_C_IRX_P4

C1880.01U_0402_16V7K

12

C1890.01U_0402_16V7K

12

4MB SPI ROM FOR ME & Non-share ROM.

SPI_SB_CS0# SPI_SO_R SPI_SO_L

2

SATA_ITX_DRX_N0 SATA_ITX_DRX_P0

SATA_ITX_DRX_N1 SATA_ITX_DRX_P1

SATA_ITX_DRX_N4 SATA_ITX_DRX_P4

+3VS

R130

0_0402_5%

1 2

33_0402_5%

R131

SATA_DTX_C_IRX_N0 <37>

SATA_DTX_C_IRX_P0 <37> SATA_ITX_DRX_N0 <37> SATA_ITX_DRX_P0 <37>

SATA_DTX_C_IRX_N1 <41>

SATA_DTX_C_IRX_P1 <41> SATA_ITX_DRX_N1 <41> SATA_ITX_DRX_P1 <41>

SATA_DTX_C_IRX_N2 <41>

SATA_DTX_C_IRX_P2 <41> SATA_ITX_DRX_N2_CONN <41> SATA_ITX_DRX_P2_CONN <41>

SATA_DTX_C_IRX_N4 <48>

SATA_DTX_C_IRX_P4 <48> SATA_ITX_DRX_N4 <48> SATA_ITX_DRX_P4 <48>

R127

1 2

R129

1 2

SPI_SB_CS0#_R

SPI_WP#

1

SSD

HDD

ODD

ESATA

SPI_CLK_PCH

R124

33_0402_5%

@

SPI_WP#

3.3K_0402_5%

SPI_HOLD#

3.3K_0402_5%

U5

1

CS#

2

SO

3

WP#

4

GND

S IC FL 32M W25Q32BVSSIG SOIC 8P

Compal Electronics, Inc.

Title

PCH (1/8) SATA,HDA,SPI, LPC, XDP

Size Document Number Rev

Custom

Date: Sheet

VCC

HOLD#

SCLK

SI

+3VS

8

SPI_HOLD#

7

SPI_CLK_PCH_0

6

SPI_SI_R

5

C191

1 2

0.1U_0402_16V4Z

1 2 1 2

33_0402_5%

LA-6882P

1

33_0402_5%

33_0402_5% R1342

R1342

R133

22P_0402_50V8J

SPI_CLK_PCH

SPI_SI

14 63Wednesday , October 06, 2010

of

C190

@

12

0.2

CyberForum.ru

5

LAN

WLAN

D D

USB3.0

Card Reader

TV

C C

WLAN

USB3.0

LAN

TV

Card Reader

B B

PCIE_PRX_DTX_N1<38>

PCIE_PRX_DTX_P1<38> PCIE_PTX_C_DRX_N1<38> PCIE_PTX_C_DRX_P1<38>

PCIE_PRX_DTX_N2<37>

PCIE_PRX_DTX_P2<37> PCIE_PTX_C_DRX_N2<37> PCIE_PTX_C_DRX_P2<37>

PCIE_PRX_DTX_N4<49>

PCIE_PRX_DTX_P4<49> PCIE_PTX_C_DRX_N4<49> PCIE_PTX_C_DRX_P4<49>

PCIE_PRX_DTX_N5<44>

PCIE_PRX_DTX_P5<44> PCIE_PTX_C_DRX_N5<44> PCIE_PTX_C_DRX_P5<44>

PCIE_PRX_DTX_N6<37>

PCIE_PRX_DTX_P6<37> PCIE_PTX_C_DRX_N6<37> PCIE_PTX_C_DRX_P6<37>

CLK_PCIE_WLAN1#<37> CLK_PCIE_WLAN1<37>

WLAN_CLKREQ1#<37>

CLK_PCIE_USB30#<49> CLK_PCIE_USB30<49>

USB30_CLKREQ#<49>

CLK_PCIE_LAN#<38> CLK_PCIE_LAN<38>

CLKREQ_LAN#<38>

CLK_PCIE_TV#<37> CLK_PCIE_TV<37>

CLKREQ_TV#<37>

CLK_PCIE_CARD_PCH#<44> CLK_PCIE_CARD_PCH<44>

CPPE#<44>

C192 0.1U_0402_10V7KC192 0.1U_0402_10V7K

1 2

C193 0.1U_0402_10V7KC193 0.1U_0402_10V7K

1 2

C194 0.1U_0402_10V7KC194 0.1U_0402_10V7K

1 2

C195 0.1U_0402_10V7KC195 0.1U_0402_10V7K

1 2

C275 0.1U_0402_10V7KC275 0.1U_0402_10V7K

1 2

C274 0.1U_0402_10V7KC274 0.1U_0402_10V7K

1 2

C277 0.1U_0402_10V7KC277 0.1U_0402_10V7K

1 2

C276 0.1U_0402_10V7KC276 0.1U_0402_10V7K

1 2

C284 0.1U_0402_10V7K

1 2

C283 0.1U_0402_10V7K

1 2

R147 10K_0402_5%R147 10K_0402_5%

+3VALW

R149 0_0402_5%R149 0_0402_5%

1 2

R150 0_0402_5%R150 0_0402_5%

1 2

R156 0_0402_5%R156 0_0402_5%

1 2

R158 10K_0402_5%R158 10K_0402_5%

+3VS

R310 0_0402_5%R310 0_0402_5%

1 2

R309 0_0402_5%R309 0_0402_5%

1 2

R308 0_0402_5%R308 0_0402_5%

1 2

R301 10K_0402_5%R301 10K_0402_5%

+3VS

R153 0_0402_5%R153 0_0402_5%

1 2

R154 0_0402_5%R154 0_0402_5%

1 2

R151 0_0402_5%R151 0_0402_5%

1 2

R152 10K_0402_5%R152 10K_0402_5%

+3VALW

R332 0_0402_5%TV@R332 0_0402_5%TV@

1 2

R334 0_0402_5%

1 2

R333 0_0402_5%TV@R333 0_0402_5%TV@

1 2

R165 10K_0402_5%R165 10K_0402_5%

+3VALW

R312 0_0402_5%R312 0_0402_5%

1 2

R311 0_0402_5%R311 0_0402_5%

1 2

R342 0_0402_5%@R342 0_0402_5%@

1 2

R168 10K_0402_5%R168 10K_0402_5%

+3VALW

R170 10K_0402_5%R170 10K_0402_5%

+3VALW

R172 10K_0402_5%R172 10K_0402_5%

+3VALW

R174 10K_0402_5%R174 10K_0402_5%

+3VALW

TV@

12

4

PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4

PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5

PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6

PCH_GPIO73

CLK_PCIE_WLAN1#_R CLK_PCIE_WLAN1_R

WLAN_CLKREQ1#_R

CLK_USB30# CLK_USB30

PCH_GPIO20

CLK_PCIE_LAN#_R CLK_PCIE_LAN_R

PCH_GPIO25

CLK_PCIE_TV#_R CLK_PCIE_TV_R

PCH_GPIO26

CLK_PCIE_CARD_PCH#_R CLK_PCIE_CARD_PCH_R

PCH_GPIO44

PCH_GPIO56

PCH_GPIO45

PCH_GPIO46

U4B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKR Q0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKR Q1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKR Q2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKR Q3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKR Q4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKR Q5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKR Q6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKR Q7# / GPIO46

AK14

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

AK13

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

COUGARPOINT_FCBGA989

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P

3

SMBALER T# / GPIO11

SMBCLK

SMBDATA

SML0ALERT# / GPIO60

SML0CLK

SML0DATA

SML1CLK / GP IO58

SML1DATA / GPIO75

CL_CLK1

Link

CLKIN_SATA_N / CKSSCD_N

CLKIN_SATA_P / CKSSCD_P

FLEX CLOCKS

CL_DATA1

CL_RST1#

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_DMI2_N CLKIN_DMI2_P

CLKIN_DOT_96N CLKIN_DOT_96P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLE X0 / GPIO64

CLKOUTFLE X1 / GPIO65

CLKOUTFLE X2 / GPIO66

CLKOUTFLE X3 / GPIO67

10K_0402_5%

12

EC_LID_OUT# <45>

12

R144

0_0402_5%

1 2

R14510K_0402_5%

DIS_ONLY@

1 2 1 2

DIS@

CLK_CPU_DMI# <6> CLK_CPU_DMI <6>

1 2 1 2

1 2

CLK_PCI_LPBACK <18>

22_0402_5%

@

+3VALW

+1.05VS_VCCDIFFCLKN

R134

EC_LID_OUT#

E12

PCH_SMBCLK

H14

PCH_SMBDATA

C9

DRAMRST_CNTRL_PCH

A12

C8

1 2

R335 2.2K_0402_5%R335 2.2K_0402_5%

1 2

G12

R336 2.2K_0402_5%R336 2.2K_0402_5%

PCH_GPIO74

C13

PCH_SML1CLK

E14

PCH_SML1DATA

M16

M7

T11

P10

PEG_CLKREQ#_R

M10

CLK_PCIE_VGA#_R CLK_PCIE_VGA#

AB37 AB38

CLK_CPU_DMI#

AV22

CLK_CPU_DMI

AU22

AM12 AM13

CLK_BUF_CPU_DMI#

BF18

CLK_BUF_CPU_DMI

BE18

CLKIN_DMI2#

BJ30

CLKIN_DMI2

BG30

CLK_BUF_DREF_96M#

G24

CLK_BUF_DREF_96M

E24

CLK_BUF_PCIE_SATA#

AK7

CLK_BUF_PCIE_SATA

AK5

CLK_BUF_ICH_14M

K45

CLK_PCI_LPBACK

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

K43

CLK_PCI_DB_R

F47

H47

K49

R134

10K_0402_5%

R140

+3VALW

R143

R143 10K_0402_5%

10K_0402_5%

OPTI@

1 2

OPTI@

1 2

R146 0_0402_5%DIS@R146 0_0402_5%DIS@ R148 0_0402_5%

R148 0_0402_5%

R155 10K_0402_5%R155 10K_0402_5% R157 10K_0402_5%R157 10K_0402_5%

R159 10K_0402_5%R159 10K_0402_5% R160 10K_0402_5%R160 10K_0402_5%

R162 10K_0402_5%R162 10K_0402_5% R163 10K_0402_5%R163 10K_0402_5%

R164 10K_0402_5%R164 10K_0402_5% R166 10K_0402_5%R166 10K_0402_5%

R167 10K_0402_5%R167 10K_0402_5%

R171

90.9_0402_1%

1 2

R173

1 2

2

R329

R329 1K_0402_5%

1K_0402_5%

Q60A

Q60A DMN66D0LDW-7 2N_SOT363-6

DMN66D0LDW-7 2N_SOT363-6

2.2K_0402_5%

2.2K_0402_5% R136

R136

1 2

+3VALW

1 2

R135

2.2K_0402_5%

DRAMRST_CNTRL_PCH <7>

12

+3VALW

2.2K_0402_5%

2.2K_0402_5% R141

R141

CLK_PCIE_VGACLK_PCIE_VGA_R

1 2

R142

2.2K_0402_5%

CLK_CPU_DMI# CLK_CPU_DMI

+3VALW +3VS

CLK_REQ_VGA# <23>

CLK_PCI_DB <37>

6 1

3

6 1

3

CLK_PCIE_VGA# <23>

CLK_PCIE_VGA <23>

R349 10K_0402_5%@R 349 10K_0402_5%@

1 2

R347 10K_0402_5%

1 2

XTAL25_IN

XTAL25_OUT

C196

C196 18P_0402_50V8J

18P_0402_50V8J

CLK_BUF_ICH_14M

SMB_CLK_S3

2.2K_0402_5%

1 2

2

+3VS

1 2

5

2.2K_0402_5%

SMB_DATA_S3

4

DMN66D0LDW-7 2N_SOT363-6

DMN66D0LDW-7 2N_SOT363-6 Q60B

Q60B

Q61A

Q61A DMN66D0LDW-7 2N_SOT363-6

DMN66D0LDW-7 2N_SOT363-6

2

5

4

DMN66D0LDW-7 2N_SOT363-6

DMN66D0LDW-7 2N_SOT363-6 Q61B

Q61B

@

1 2

R169 1M_0402_5%R169 1M_0402_5%

1

25MHZ_20PF_7A25000012

2

@R175

@

33_0402_5%

EC_SMB_CK2

EC_SMB_DA2

Y2

12

R175

12

1

SMB_CLK_S3 <12,13,37>

DIMM1

R137

DIMM2

R138

MINI CARD

SMB_DATA_S3 <12,13,37>

EC_SMB_CK2 <23,40,45,50>

VGA EC thermal sensor

EC_SMB_DA2 <23,40,45,50>

1

C197

C197 18P_0402_50V8J

18P_0402_50V8J

2

C198

@C198

@

22P_0402_50V8J

1 2

Reserve for EMI please close to PCH

C199

@C199

12

@

22P_0402_50V8J

1 2

R176

@R176

@

33_0402_5%

A A

CLK_PCI_LPBACK

33_0402_5%

Reserve for EMI please close to PCH

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

LA-6882P

1

15 63Wednesday , October 06, 2010

0.2

of

CyberForum.ru

5

D D

MC74VHC1G08DFT2G SC70 5P

VGATE

PCH_POK

C C

+3VALW

B B

R192 200_0402_5%@R192 200_0402_5%@

R194 10K_0402_5%R194 10K_0402_5%

R195 10K_0402_5%R195 10K_0402_5%

R197 10K_0402_5%R197 10K_0402_5%

+3VS

3

1

G

A

2

B

+3VS

R180 100K_0402_1%R180 100K_0402_1%

SYS_PWROK

4

Y

P

U6

5

12

PCH_APWROK<45>

AEPWROK can be connect to PWROK if iAMT disable

12

SYS_PWROK

VGATE<60>

PCH_POK<45>

PM_DRAM_PWRGD

SUSWARN#

ACIN_R

PCH_RSMRST#_R

SUSACK# is only used on platform that support the Deep Sx state.

R188 0_0402_5%@R188 0_0402_5%@

1 2

R190 0_0402_5%R190 0_0402_5%

1 2

R302 0_0402_5%R302 0_0402_5%

1 2

PM_DRAM_PWRGD<6>

EC_RSMRST#<45>

SUSWARN#<45>

ACIN<45,54>

4

DMI_CTX_PRX_N0<5> DMI_CTX_PRX_N1<5> DMI_CTX_PRX_N2<5> DMI_CTX_PRX_N3<5>

DMI_CTX_PRX_P0<5> DMI_CTX_PRX_P1<5> DMI_CTX_PRX_P2<5> DMI_CTX_PRX_P3<5>

DMI_CRX_PTX_N0<5> DMI_CRX_PTX_N1<5> DMI_CRX_PTX_N2<5> DMI_CRX_PTX_N3<5>

DMI_CRX_PTX_P0<5> DMI_CRX_PTX_P1<5> DMI_CRX_PTX_P2<5> DMI_CRX_PTX_P3<5>

+1.05VS_PCH

R177 49.9_0402_1%R177 49.9_0402_1%

R178 750_0402_1%R178 750_0402_1%

4mil width and place within 500mil of the PCH

T72 PADT72 PAD

+3VS

R184 10K_0402_5%R184 10K _0402_5%

R191 0_0402_5%

R193 0_0402_5%R193 0_0402_5%

R196 0_0402_5%R196 0_0402_5%

PBTN_OUT#<45>

D29 RB751V_SOD323D29 RB751V_SOD323

1 2

R199 0_0402_5%@R199 0_0402_5%@

+3VALW

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

1 2

SUSACK#

12

@

12

1 2

SUSWARN#_R SLP_S3#

1 2

R198 0_0402_5%R198 0_0402_5%

21

R200

1 2

8.2K_0402_5%

8.2K_0402_5% R201

R201

10K_0402_5%

DMI_IRCOMP

RBIAS_CPY

SYS_RST#

SYS_PWROK

PWROK

APWROK

PM_DRAM_PWRGD

PCH_RSMRST#_R

PBTN_OUT#_R

ACIN_R

PCH_GPIO72

RI#

12

U4C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN# / SUS_PWR_DN_ACK / GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

COUGARPOINT_FCBGA989

3

BJ14

FDI_RXN0

AY14

FDI_RXN1

BE14

FDI_RXN2

BH13

FDI_RXN3

BC12

FDI_RXN4

BJ12

FDI_RXN5

BG10

FDI_RXN6

BG9

FDI_RXN7

BG14

FDI_RXP0

BB14

FDI_RXP1

BF14

FDI_RXP2

BG13

FDI_RXP3

BE12

FDI_RXP4

BG12

FDI_RXP5

BJ10

DMI

System Power Management

FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO6 2

SLP_S5# / GPIO6 3

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GP IO29

BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

10/06 Test point request

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWODVREN

PCH_DPWROK_R

WAKE#

1 2 1 2

PM_CLKRUN#

SUS_STAT#

SUSCLK

SLP_S5#

SLP_S4#

PM_SLP_SUS#

H_PM_SYNC

PM_SLP_LAN#

R185

R185 0_0402_5%

0_0402_5%

R186

1 2

8.2K_0402_5%

1 2

10K_0402_5%

R189

2

FDI_CTX_PRX_N0 <5> FDI_CTX_PRX_N1 <5> FDI_CTX_PRX_N2 <5> FDI_CTX_PRX_N3 <5> FDI_CTX_PRX_N4 <5> FDI_CTX_PRX_N5 <5> FDI_CTX_PRX_N6 <5> FDI_CTX_PRX_N7 <5>

FDI_CTX_PRX_P0 <5> FDI_CTX_PRX_P1 <5> FDI_CTX_PRX_P2 <5> FDI_CTX_PRX_P3 <5> FDI_CTX_PRX_P4 <5> FDI_CTX_PRX_P5 <5> FDI_CTX_PRX_P6 <5> FDI_CTX_PRX_P7 <5>

FDI_INT <5>

FDI_FSYNC0 <5>

FDI_FSYNC1 <5>

FDI_LSYNC0 <5>

FDI_LSYNC1 <5>

0_0402_5%

PCH_RSMRST#_R

R181

@

R337

0_0402_5%

SUSCLK <45>

SLP_S5# <45>

SLP_S4# <45>

SLP_S3# <45>

T71PAD T71PAD

H_PM_SYNC <6>

T74PAD T74PAD

PCH_DPWROK <45>

PCIE_WAKE# <37,38,49>

+3VALW

T73PAD T73PAD

+3VS

Can be left NC when IAMT is not support on the platfrom

Can be left NC if no use integrated LAN.

+RTCVCC

12

R179

R179 330K_0402_5%

330K_0402_5%

R183

R183 330K_0402_5%

330K_0402_5%

@

1

DSWODVREN - On Die DSW VR Enable

*

H

烉

Enable

L

烉

Disable

R1290 200_0402_5%R1290 200_0402_5%

12

PM_DRAM_PWRGD

7/28 Modify follow Module Design.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,

LA-6882P

1

16 63Wednesday , October 06, 2010

0.2

of

CyberForum.ru

5

D D

Pull up R for CONN SIDE

C C

DAC_BLU<35>

DAC_GRN<35>

DAC_RED<35>

B B

R524

2.2K_0402_5%

@

CRT_DDC_CLK CRT_DDC_DATA

R208 150_0402_1%

R209 150_0402_1%

R210 150_0402_1%

+3VS

12

R559

2.2K_0402_5%

@

12

UMA@

12

UMA@

12

UMA@

Pull up R for CONN SIDE

4

R204 2.2K_0402_5%R204 2.2K_0402_5%

+3VS

R205 2.2K_0402_5%R205 2.2K_0402_5%

DAC_BLU

DAC_GRN

DAC_RED

PCH_ENBKL<34> PCH_ENVDD<34>

1 2 1 2

EDID_CLK<34> EDID_DATA<34>

R206

R207

PCH_PWM<34>

LVDS_ACLK#<34> LVDS_ACLK<34>

LVDS_A0#<34> LVDS_A1#<34> LVDS_A2#<34>

LVDS_A0<34> LVDS_A1<34> LVDS_A2<34>

LVDS_BCLK#<34> LVDS_BCLK<34>

LVDS_B0#<34> LVDS_B1#<34> LVDS_B2#<34>

LVDS_B0<34> LVDS_B1<34> LVDS_B2<34>

CRT_DDC_CLK<35> CRT_DDC_DATA<35>

CRT_HSYNC<35> CRT_VSYNC<35>

2.37K_0402_1%

0_0402_5%

PCH_ENBKL PCH_ENVDD

EDID_CLK EDID_DATA

12

UMA@

12

UMA@

R211

1K_0402_1%

CTRL_CLK CTRL_DATA

LVDS_IBG

LVD_VREF

CRT_DDC_CLK CRT_DDC_DATA

CRT_IREF

12

U4D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

COUGARPOINT_FCBGA989

3

SDVO_INTN SDVO_INTP

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39

2.2K_0402_5%

AP40

UMA_HDMI@

HDMICLK

P38

HDMIDAT

M39

AT49 AT47 AT40

TMDS_B_DATA2#_PCH

AV42

TMDS_B_DATA2_PCH

AV40

TMDS_B_DATA1#_PCH

AV45

TMDS_B_DATA1_PCH

AV46

TMDS_B_DATA0#_PCH

AU48

TMDS_B_DATA0_PCH

AU47

TMDS_B_CLK#_PCH

AV47

TMDS_B_CLK_PCH

AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

R202

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

2

+3VS

12

R203

2.2K_0402_5%

UMA_HDMI@

TMDS_B_HPD <36>

HDMICLK <36> HDMIDAT <36>

C200 0.1U_0402_10V6KUMA_HDMI@ C200 0.1U_0402_10V6KUMA_HDMI@

1 2

C201 0.1U_0402_10V6KUMA_HDMI@ C201 0.1U_0402_10V6KUMA_HDMI@

1 2

C202 0.1U_0402_10V6KUMA_HDMI@ C202 0.1U_0402_10V6KUMA_HDMI@

1 2

C203 0.1U_0402_10V6KUMA_HDMI@ C203 0.1U_0402_10V6KUMA_HDMI@

1 2

C204 0.1U_0402_10V6KUMA_HDMI@ C204 0.1U_0402_10V6KUMA_HDMI@

1 2

C205 0.1U_0402_10V6KUMA_HDMI@ C205 0.1U_0402_10V6KUMA_HDMI@

1 2

C206 0.1U_0402_10V6KUMA_HDMI@ C206 0.1U_0402_10V6KUMA_HDMI@

1 2

C207 0.1U_0402_10V6KUMA_HDMI@ C207 0.1U_0402_10V6KUMA_HDMI@

1 2

UMA_HDMI@

1

HDMI_TX2-_CK <36> HDMI_TX2+_CK <36> HDMI_TX1-_CK <36> HDMI_TX1+_CK <36> HDMI_TX0-_CK <36> HDMI_TX0+_CK <36> HDMI_CLK-_CK <36> HDMI_CLK+_CK <36>

HDMI

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (4/9) LVDS,CRT,DP,HDMI

LA-6882P

1

17 63Wednesday , October 06, 2010

of

0.2

CyberForum.ru

5

+3VS

R297 8.2K_0402_5%@R297 8.2K_0402_5%@

1 2

RP2

PCI_PIRQA#

18

PCI_PIRQD#

27

PCI_PIRQC#

36

PCI_PIRQB#

45

8.2K_0804_8P4R_5%

D D

WL_OFF#

C C

GPIO53=This Signal has a weak i nternal pull-up. NOTE: The internal pull-up is disabled after PLTRST# deasserts.

B B

PCH_GPIO51

8.2K_0804_8P4R_5%

RP1

PCH_GPIO2

18

PCH_GPIO54

27

PCH_GPIO4

36

PCH_GPIO3

45

8.2K_0804_8P4R_5%

R225 8.2K_0402_5%R225 8.2K_0402_5%

1 2

R212 8.2K_0402_5%R212 8.2K_0402_5%

1 2

R213 8.2K_0402_5%R213 8.2K_0402_5%

1 2

R214 8.2K_0402_5%

1 2

@

R215 1K_0402_5%@R215 1K_0402_5%@

1 2

A16 swap overide Strap/Top-Block Swap Override jumper

PCI_GNT3#

Low=A16 swap override/Top-Block Swap Override enabled High=Default

R221 1K_0402_5%@R221 1K_0402_5%@

1 2

PCH_GPIO53

09/11 reserved

WL_OFF#

PCH_GPIO52

PCH_GPIO5

PCH_GPIO50

*

R314

DGPU_HOLD_RST#<23>

DGPU_PWR_EN<23,51,57,58,59>

ODD_DA#<41,45>

CLK_PCI_LPBACK<15>

CLK_PCI_LPC<45>

R314

R315

ODD_DA# PCH_GPIO3

4

OPTI@

1 2

0_0402_5%

1 2

0_0402_5%

OPTI@

WL_OFF#<37>

1 2

R7150_0402_5%@R7150_0402_5%

PCI_PME#<45>

PLT_RST#<6>

R219 22_0402_5%R219 22_0402_5%

1 2 1 2

R220 22_0402_5%R220 22_0402_5%

@

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

PCH_GPIO50 PCH_GPIO52 PCH_GPIO54

PCH_GPIO53 WL_OFF#

PCH_GPIO2

PCH_GPIO4 PCH_GPIO5

PLT_RST#

CLK_PCI_LPBACK_R CLK_PCI_LPC_R

U4E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

TP25

BC30

TP26

BE32

TP27

BJ32

TP28

BC28

TP29

BE30

TP30

BF32

TP31

BG32

TP32

AV26

TP33

BB26

TP34

AU28

TP35

AY30

TP36

AU26

TP37

AY26

TP38

AV28

TP39

AW30

TP40

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

COUGARPOINT_FCBGA989

RSVD

PCI

3

NV_DQ0 / NV_ IO0 NV_DQ1 / NV_ IO1 NV_DQ2 / NV_ IO2 NV_DQ3 / NV_ IO3 NV_DQ4 / NV_ IO4 NV_DQ5 / NV_ IO5 NV_DQ6 / NV_ IO6 NV_DQ7 / NV_ IO7 NV_DQ8 / NV_ IO8 NV_DQ9 / NV_ IO9

NV_DQ10 / NV_IO10

NVRAM

NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15

NV_RE#_WRB0 NV_RE#_WRB1

NV_WE#_CK0 NV_WE#_CK1

USB

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3

NV_DQS0 NV_DQS1

NV_ALE NV_CLE

NV_RCOMP

NV_RB#

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

AV5

NV_CLE

AY1

AV10

AT8

AY5 BA2

AT12 BF3

USB20_N0

C24

USB20_P0

A24

USB20_N1

C25

USB20_P1

B25

USB20_N2

C26

USB20_P2

A26

USB20_N3

K28

USB20_P3

H28 E28 D28

USB20_N5

C28

USB20_P5

A28 C29 B29 N28

Some PCH config not support USB port 6 & 7.

M28

USB20_N8

L30

USB20_P8

K30

USB20_N9

G30

USB20_P9

E30

USB20_N10

C30

USB20_P10

A30 L32 K32

USB20_N12

G32

USB20_P12

E32

USB20_N13

C32

USB20_P13

A32

USBRBIAS

C33

B33

USB_OC0#

A14

USB_OC1#

K20

USB_OC2#

B17

USB_OC3#

C16

USB_OC4#

L16

USB_OC5#

A16

USB_OC6#

D14

USB_OC7#

C14

USB DEBUG=PORT1 AND PORT9

USB20_N0 <48> USB20_P0 <48> USB20_N1 <48> USB20_P1 <48> USB20_N2 <49> USB20_P2 <49> USB20_N3 <49> USB20_P3 <49>

USB20_N5 <34> USB20_P5 <34>

USB20_N8 <50> USB20_P8 <50> USB20_N9 <37> USB20_P9 <37> USB20_N10 <50> USB20_P10 <50>

USB20_N12 <37> USB20_P12 <37> USB20_N13 <47> USB20_P13 <47>

Within 500 mils

1 2

R218 22.6_0402_1%R218 22.6_0402_1%

LEFT USB

LEFT USB (COMBO)

RIGHT USB

USB Camera

IR

WLAN

USB_OC0# <48> USB_OC1# <49>

2

A Cover Light

TV

Bluetooth

DMI Termination Voltage

NV_CLE

Set to Vcc when HIGH

Set to Vss when LOW

1 2

R217 1K_0402_5%R217 1K_0402_5%

CLOSE TO THE BRANCHING POINT

USB_OC0# USB_OC2#PCH_GPIO51 USB_OC7# USB_OC5#

USB_OC1# USB_OC4# USB_OC3# USB_OC6#

1

+1.8VS

RP3

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%

RP4

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%

R216

2.2K_0402_5%

H_SNB_IVB# <6>

+3VALW

Boot BIOS Strap bit1 BBS1

12

R223

R223 100K_0402_5%

100K_0402_5%

1 2

R222 0_0402_5%R222 0_0402_5%

3

@

4

U7

1

G

A

Y

2

B

P

5

+3VS

PLT_RST#

Boot BIOS

Bit10

0

1

0

Destination

Reserved

SPI

*

LPC

(Default)

MC74VHC1G08DFT2G SC70 5P

BUF_PLT_RST#<23,37,38,44,45,49>

1

@

C208

1U_0402_6.3V6K

2

Bit11

GNT1#/ GPIO51

01

1

0

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

PCH (5/9) PCI, USB

LA-6882P

1

0.2

18 63Wednesday , October 06, 2010

0.2

of

CyberForum.ru

5

D D

6/24 Change to @ follow module design and double check on module design meeting

ICC_EN#

Integrated Clock Chip Enable

H ; Disable L ; Enable

*

@

R235 1K_0402_5%

1 2

EC_SMI#

DEVICE_RST#<37,38,44>

Weak internal pull-high

GPIO28

On-Die PLL Voltage Regulator This signal has a weak internal pull up

H

烉

On-Die voltage regulator enable

*

L烉On-Die PLL Voltage Regulator disable

R240 1K_0402_5%@R240 1K_0402_5%@

1 2

C C

PCH_GPIO27 (Have internal Pull-High) High: VCCVRM VR Enable

*

Low: VCCVRM VR Disable

R245 10K_0402_5%@R245 10K_0402_5%@

1 2

R250 200_0402_5%@R250 200_0402_5%@

+3VS

B B

1 2

R264 10K_0402_5%R264 10K_0402_5%

1 2

ESATA_DET#<48>

7/29 update for ESATA detect

PCH_GPIO28

PCH_GPIO27

PCH_GPIO36

1 2

R3400_0402_5%@R3400_0402_5%

@

VGA_PGOOD<23,59>

BT_DISABLE<37>

BT_OFF#<37,47>

ESATA_DET_RR#

+3VS

ESATA_DET#<48>

+3VS

+3VALW

SMIB<49>

+3VS

+3VALW

4

R233 10K_0402_5%R233 10K_0402_5%

1 2

1 2 1 2

1 2

R241

1 2

R242

1 2

NO_VENTURA@

1 2

VENTURA@

R3030_0402_5% R3030_0402_5%

EC_SCI#<45>

EC_SMI#<45>

@

R3390_0402_5% R 3390_0402_5%

ODD_EN<41>

10K_0402_5%

10K_0402_5%@

R227 10K_0402_5%R227 10K_0402_5%

R228 10K_0402_5%R228 10K_0402_5%

R229 10K_0402_5%@R229 10K_0402_5%@

R230 1K_0402_5%@R230 1K_0402_5%@

R231 10K_0402_5%R231 10K_0402_5% R232 10K_0402_1%

R232 10K_0402_1%

R238 10K_0402_5%R238 10K_0402_5%

+3VALW

R243 10K_0402_5%R243 10K_0402_5%

R259 10K_0402_5%R259 10K_0402_5%

R244 10K_0402_5%@R244 10K_0402_5%@

R246 10K_0402_5%R246 10K_0402_5%

R247 10K_0402_5%R247 10K_0402_5%

R248 10K_0402_5%R248 10K_0402_5%

R249 10K_0402_5%R249 10K_0402_5%

R251 10K_0402_5%

R1345 10K_0402_5%

3

GPIO69 GPIO70 GPIO71

14": Low 15": Hi

1

PCH_GPIO0

ESATA_DET_R# PCH_GPIO69

DEVICE_RST#

EC_SCI#

EC_SMI#

PCH_GPIO12

SMIB

ESATA_DET_RR#

VGA_PGOOD_R

BT_DISABLE

ODD_EN

PCH_GPIO27

PCH_GPIO28

BT_OFF#

PCH_GPIO35

PCH_GPIO36

PCH_GPIO37

PCH_GPIO38

PCH_GPIO39

PCH_GPIO48

PCH_GPIO49

PCH_GPIO57

VSS_NCTF_1

VSS_NCTF_2

VSS_NCTF_3

VSS_NCTF_4

VSS_NCTF_5

VSS_NCTF_6

VSS_NCTF_7

VSS_NCTF_8

VSS_NCTF_9

VSS_NCTF_10

VSS_NCTF_11

VSS_NCTF_12

VSS_NCTF_13

VSS_NCTF_14

U4F

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO1 6

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24 / MEM_L ED

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GP IO34

K4

GPIO35

V8

SATA2GP / GPIO3 6

M5

SATA3GP / GPIO3 7

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO4 9

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

COUGARPOINT_FCBGA989

GPIO

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

CPU/MISC

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

NCTF

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

NC_1

NC_2

NC_3

NC_4

NC_5

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

ALC272: Low ALC5503: Hi

PCH_GPIO68

PCH_GPIO70

PCH_GPIO71

PCH_PECI_R

KB_RST#

PCH_THRMTRIP#_R

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

2

DIS ONLY: Low OPTIMUS: Hi

00

0

1

0

11

+3VS

R236

R236 10K_0402_5%

10K_0402_5%

1 2

@

1 2

R2370_0402_5%@R2370_0402_5%

1 2

R239 390_0402_5%R239 390_0402_5%

H_PECI <6,45>

KB_RST# <45>

H_CPUPWRGD <6>

H_THRMTRIP#

PCH_GPIO69

PCH_GPIO70

PCH_GPIO71

6/23 update for MB ID

GATEA20 <45>

PCH_GPIO68

KB_RST#

H_THRMTRIP# <6>

PCH_THRMTRIP#_R <23>

R702

R707

R224 10K_0402_5%R224 10K_0402_5%

R226 10K_0402_5%R226 10K_0402_5%

INIT3_3V

This signal has weak internal PU, can't pull low

Intel schematic reviwe recommand.

Change VSS_NCTF pin form TEST point to Trace for layout SPACE reducing..

1

R703

1 2

R705

@

1 2

10K_0402_5%

5503@

1 2

10K_0402_5%

272@

R704

10K_0402_5%

R706

10K_0402_5%

+3VS

1 2

OPTI@

10K_0402_5%

DIS_ONLY@

10K_0402_5%

+3VS

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (6/9) GPIO, CPU, MISC

LA-6882P

1

19 63Wednesday , October 06, 2010

0.2

of

CyberForum.ru

5

4

3

2

1

POWER

2925mA

POWER

VCC CORE

VCCIO

FDI

1mA

CRTLVDS

1mA

VCCTX_LVDS[1]

VCCTX_LVDS[2]

60mA

VCCTX_LVDS[3]

VCCTX_LVDS[4]

DMI

20mA

190mA

NAND / SPI HVCMOS

20mA

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCIO[1]

VCCPNAND[1]

VCCPNAND[2]

VCCPNAND[3]

VCCPNAND[4]

VCCSPI

+VCCADAC

U48

U47

+VCCA_LVDS

AK36

AK37

AM37

AM38

+VCCTX_LVDS

AP36

AP37

+3VS_VCC3_3_6

V33

V34

+VCCAFDI_VRM

AT16

+VCCP_VCCDMI

AT20

+1.05VS_VCC_DMI_CCI

AB36

@

C226

1U_0402_6.3V6K

AG16

AG17

AJ16

AJ17

+3V_VCCPSPI

V1

C213

0.01U_0402_16V7K

C213

0.01U_0402_16V7K

1

2

1

C216

0.01U_0402_16V7K

2

UMA@

0_0805_5%

1 2

1

C219

0.1U_0402_10V7K

2

1

2

1

C228

0.1U_0402_10V7K

2

1

C230

C230 1U_0402_6.3V6K

1U_0402_6.3V6K

2

C214

0.1U_0402_10V7K

C214

0.1U_0402_10V7K

1

C215

C215 10U_0805_6.3V6M

1

C217

0.01U_0402_16V7K

2

UMA@

+VCCP_VCCDMI

L8

1 2

C285

@

R313

1 2

0_0805_5%

10U_0805_6.3V6M

2

12

DIS_ONLY@

R253

R253 0_0402_5%

0_0402_5%

+3VS

R261

R261 0_0805_5%

0_0805_5%

1 2

2

R256

10UH_LB2012T100MR_20%

1

10U_0603_6.3V6M

2

L1

MBK1608221YZF_2P

12

R252

0.022_0805_1%

1 2

UMA@

22U_0805_6.3V6M

1

UMA@

2

+1.05VS_PCH

+1.8VS+VCCPNAND

+3VS

L2

UMA@L2

0.1UH_MLF1608DR10KT_10%_1608

C218

12

1

C220

C220 1U_0402_6.3V6K

1U_0402_6.3V6K

2

UMA@

0.1uH inductor, 200mA

DIS_ONLY@

R255

R255 0_0402_5%

0_0402_5%

+1.05VS

R258

1 2

0_0805_5%

+1.8VS

12

+1.05VS

D D

+1.05VS_PCH

C C

+1.05VS_PCH

B B

0_0805_5%

1 2

@PJP1

@

PAD-OPEN 4x4m

+1.05VS_PCH

PJP2

@PJP2

@

12

PAD-OPEN 4x4m

R257

@

R262

@R262

@

0_0603_5%

1U_0402_6.3V6K

PJP1

12

1

2

R254 0_0603_5%R254 0_0603_5%

This pin can be left as no connect in On-Die VR enabled mode (default).

C221

10U_0805_6.3V6M

C221

10U_0805_6.3V6M

1

2

+3VS

R260

0_0805_5%

1 2

Place CH53 Near BG6 pin

12

1

C229

@C229

@

2

C210

1U_0402_6.3V6K

C210

1U_0402_6.3V6K

C209

10U_0603_6.3V6M

C209

10U_0603_6.3V6M

1

2

12

T47PAD @T47PAD @

+1.05VS_VCC_EXP

C222

1U_0402_6.3V6K

C222

1U_0402_6.3V6K

1

2

1

C227

0.1U_0402_10V7K

2

+1.05VS_PCH

1

2

C223

1

2

R263

1 2

0_0805_5%

+VCCP_VCCDMI

+1.05VS_PCH

C211

1U_0402_6.3V6K

C211

1U_0402_6.3V6K

1

2

+1.05VS_VCCDPLLEXP

+VCCAPLLEXP

C224

1U_0402_6.3V6K

C224

1U_0402_6.3V6K

1

2

+3VS_VCCA3GBG

+VCCAFDI_VRM

+1.05VS_VCCAPLL_FDI

+1.05VS_VCCDPLL_FDI

C212

C225

1U_0402_6.3V6K

C225

1U_0402_6.3V6K

U4G

1300mA

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VCCFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

COUGARPOINT_FCBGA989

PCH Power Rail Table

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

Voltage

1.05

3.3

1.05

S0 Iccmax Current (A)

0.001

5

0.001

0.266

0.001

0.08

1.3

0.042

1.05VccIO 2.925

1.05VccASW 1.01

3.3VccSPI 0.02

3.3VccDSW 0.003

1.8 0.19VccpNAND

3.3VccRTC 6 uA

3.3VccSus3_3

3.3 / 1.5VccSusHDA

0.119

0.01

VccVRM 1.8 / 1.5 0.16

1.05VccCLKDMI

0.02

VccSSC 1.05 0.095

VccDIFFCLKN 1.05 0.055

VccALVDS 3.3

0.001

1.8VccTX_LVDS 0.06

+1.5VS

R265 0_0603_5%R265 0_0603_5%

12

+VCCAFDI_VRM

VCCVRM = 160mA detail waiting for newest spec

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (7/9) PWR

LA-6882P

1

20 63Wednesday , October 06, 2010

0.2

of

CyberForum.ru

5

+3VS

D D

+1.05VS_PCH

C C

OSCAN SF000001500

R267

@R267

@

0_0805_5%

1 2

L3

10UH_LB2012T100MR_20%

1 2

R271

@R271

@

0_0603_5%

+VCCAPLL_CPY

1 2

+3VS_VCC_CLKF33

C231

10U_0805_10V4Z

C231

10U_0805_10V4Z

1

2

L4

@ L4

@

10UH_LB2012T100MR_20%

1 2

@

C232

1U_0402_6.3V6K

C232

1U_0402_6.3V6K

1

2

1

+1.05VS_PCH

C237

10U_0805_6.3V6M@C237

10U_0805_6.3V6M

2

+1.05VS_PCH

+3VALW

R274 0_0603_5%R274 0_0603_5%

+1.05VS_PCH

0_0805_5%

1 2

R277

(220U 6.3V M V LESR15M VL H5.9)*2

+1.05VS_PCH

R280

R280 0_0805_5%

0_0805_5%

+VCCA_DPLL_L

1 2

R284

0_0603_5%

+1.05VS_PCH

B B

+1.05VS_PCH

A A

0_0603_5%

R286

0_0603_5%

R288

0_0603_5%

R290

@R290

@

0_0603_5%

L5

10UH_LB2012T100MR_20%

1 2

L6

10UH_LB2012T100MR_20%

+VCCDIFFCLK

12

1

C256

C256 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+1.05VS_VCCDIFFCLKN

12

1

C259

C259 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+1.05VS_SSCVCC

12

1

C262

C262 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+1.05VM_VCCSUS

12

1

C264

C264 1U_0402_6.3V6K

1U_0402_6.3V6K

2

@

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

1U_0402_6.3V6K

220U_6.3V_M

1

C250

1

+

2

+1.05VS_VCCDIFFCLKN

+1.05VS

C251

R293

0_0603_5%

1 2

220U_6.3V_M

1

C252

+

2

0.1U_0402_10V7K

1

2

4

Have internal VRM

R268

@R268

@

0_0603_5%

12

R269

0_0603_5%

1 2

C235

0.1U_0402_10V7K

12

@

1 2

C244

1U_0402_6.3V6K

C244

1U_0402_6.3V6K

1

2

C253

1U_0402_6.3V6K

C253

1U_0402_6.3V6K

1

2

1

C258

2

1

C263

2

C265

4.7U_0603_6.3V6K

C265

4.7U_0603_6.3V6K

C266

0.1U_0402_10V7K

C266

0.1U_0402_10V7K

1

2

+VCCACLK

+VCCPDSW

1

C234

0.1U_0402_10V7K

2

+PCH_VCCDSW

+3VS_VCC_CLKF33

+VCCAPLL_CPY_PCH

+VCCDPLL_CPY

+VCCSUS1

1

C239

@C239

@

1U_0402_6.3V6K

2

+1.05VM_VCCASW

C241

22U_0805_6.3V6M

C241

22U_0805_6.3V6M

1

2

C245

1U_0402_6.3V6K

C245

1U_0402_6.3V6K

1

2

+VCCRTCEXT

+VCCAFDI_VRM

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

+VCCDIFFCLK

+1.05VS_VCCDIFFCLKN

+1.05VS_SSCVCC

+VCCSST

+1.05VM_VCCSUS

+V_CPU_IO

C267

0.1U_0402_10V7K

C267

0.1U_0402_10V7K

+RTCVCC

1U_0402_6.3V6K

1

2

3

2

1

VCC3_3 = 266mA detal waiting for newest spec

VCCDMI = 42mA detal waiting for newest spec

POWER

U4J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

C242

22U_0805_6.3V6M

C242

22U_0805_6.3V6M

C246

1U_0402_6.3V6K

C246

1U_0402_6.3V6K

C268

C269

0.1U_0402_10V7K

C269

0.1U_0402_10V7K

1

2

AA26

AA27

AA29

AA31

AC26

AC27

AC29

AC31

AD29

AD31

W21

W23

W24

W26

W29

W31

W33

N16

Y49

BD47

BF47

AF17 AF33 AF34 AG34

AG33

V16

T17 V19

BJ8

A22

C270

0.1U_0402_10V7K

C270

0.1U_0402_10V7K

1

2

VCCASW[3]

VCCASW[4]

VCCASW[5]

VCCASW[6]

VCCASW[7]

VCCASW[8]

VCCASW[9]

VCCASW[10]

VCCASW[11]

VCCASW[12]

VCCASW[13]

VCCASW[14]

VCCASW[15]

VCCASW[16]

VCCASW[17]

VCCASW[18]

VCCASW[19]

VCCASW[20]

DCPRTC

VCCVRM[4]

VCCADPLLA

VCCADPLLB

VCCIO[7] VCCIO[8] VCCIO[9] VCCIO[11]

VCCIO[10]

DCPSST

DCPSUS[1] DCPSUS[2]

V_PROC_IO

VCCRTC

COUGARPOINT_FCBGA989

POWER

VCCIO[29]

119mA

PCI/GPIO/LPCMISC

SATA USB

HDA

VCCSUS3_3[7]

VCCSUS3_3[8]

VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

1mA

VCCSUS3_3[1]

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

VCCAPLLSATA

10mA

VCCSUSHDA

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

V5REF

1mA

VCC3_3[1]

VCC3_3[8]

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

3mA

1010mA

Clock and Miscellaneous

80mA

55mA

95mA

1mA

CPURTC

N26

P26

P28

T27

T29

T23

T24

V23

V24

P24

T26

M26

AN23

AN24

P34

N20

N22

P20

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

P32

+1.05VS_VCCUSBCORE

1

2

1

2

+1.05VS_VCCAUPLL

+PCH_V5REF_SUS

+VCCA_USBSUS

+3V_VCCPSUS

+PCH_V5REF_RUN

+3V_VCCPSUS

+3VS_VCCPCORE

+3VS_VCCPPCI

+VCC3_3_2

+VCCAFDI_VRM

+1.05VS_VCC_SATA

+VCCME_22

+VCCME_23

+VCCME_21

+VCCSUSHDA

1

C271

0.1U_0402_16V4Z

2

0_0603_5%

C233

C233 1U_0402_6.3V6K

1U_0402_6.3V6K

+3V_VCCPUSB

C236

0.1U_0402_10V7K

C236

0.1U_0402_10V7K

+3V_VCCAUBG

1

C238

0.1U_0402_10V7K

2

C243 1U_0402_6.3V6K

R283

0_0603_5%

1

C255

0.1U_0402_10V7K

2

+1.05VS_SATA3

+VCCSATAPLL

+1.05VS_VCC_SATA

R295 0_0603_5%R295 0_0603_5%

R270

R272

R272 0_0603_5%

0_0603_5%

@

1 2

+3VS

12

1

C261

C261 1U_0402_6.3V6K

1U_0402_6.3V6K

2

12

+1.05VS_PCH

12

+3VALW

12

+3VALW

R273

12

+1.05VS_PCH

R276

12

1

2

1

2

1

2

+1.05VS_SATA3

1

2

R289

0_0805_5%

+1.05VS_PCH

R278

R278 0_0603_5%

0_0603_5%

C247

C247 1U_0402_6.3V

1U_0402_6.3V

R281

R281 0_0805_5%

0_0805_5%

C249

0.1U_0402_10V7K

C254

0.1U_0402_10V7K

C257

C257 1U_0402_6.3V6K

1U_0402_6.3V6K

+1.05VS_PCH

12

+3VALW

12

+3VS

12

R282

R282 0_0603_5%

0_0603_5%

0_0805_5%

+3VS

12

+1.05VS_PCH

R285

12

L7

@L7

@

10UH_LB2012T100MR_20%

1 2

1

C260

@C260

@

10U_0805_6.3V6M

Place CH80 Near AK1 pin

2

R275

100_0402_5%

+VCCSATAPLL_R

R279

12

R287

@R287

@

0_0805_5%

+3VALW+5VALW

21

D1

D1 RB751V-40 SOD-323

RB751V-40 SOD-323

+PCH_V5REF_SUS

1

C240

0.1U_0603_25V7K

2

+3VS+5VS

21

D2

D2 RB751V-40 SOD-323

RB751V-40 SOD-323

+PCH_V5REF_RUN

1

C248

C248 1U_0603_10V6K

1U_0603_10V6K

2

+1.05VS_PCH

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (8/9) PWR

LA-6882P

1

21 63Wednesday , October 06, 2010

0.2

of

CyberForum.ru

5

D D

C C

B B

A A

U4H

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

VSS[19]

AD10

VSS[20]

AD11

VSS[21]

AD12

VSS[22]

AD13

VSS[23]

AD19

VSS[24]

AD24

VSS[25]

AD26

VSS[26]

AD27

VSS[27]

AD33

VSS[28]

AD34

VSS[29]

AD36

VSS[30]

AD37

VSS[31]

AD38

VSS[32]

AD39

VSS[33]

AD4

VSS[34]

AD40

VSS[35]

AD42

VSS[36]

AD43

VSS[37]

AD45

VSS[38]

AD46

VSS[39]

AD8

VSS[40]

AE2

VSS[41]

AE3

VSS[42]

AF10

VSS[43]

AF12

VSS[44]

AD14

VSS[45]

AD16

VSS[46]

AF16

VSS[47]

AF19

VSS[48]

AF24

VSS[49]

AF26

VSS[50]

AF27

VSS[51]

AF29

VSS[52]

AF31

VSS[53]

AF38

VSS[54]

AF4

VSS[55]

AF42

VSS[56]

AF46

VSS[57]

AF5

VSS[58]

AF7

VSS[59]

AF8

VSS[60]

AG19

VSS[61]

AG2

VSS[62]

AG31

VSS[63]

AG48

VSS[64]

AH11

VSS[65]

AH3

VSS[66]

AH36

VSS[67]

AH39

VSS[68]

AH40

VSS[69]

AH42

VSS[70]

AH46

VSS[71]

AH7

VSS[72]

AJ19

VSS[73]

AJ21

VSS[74]

AJ24

VSS[75]

AJ33

VSS[76]

AJ34

VSS[77]

AK12

VSS[78]

AK3

VSS[79]

COUGARPOINT_FCBGA989

4

AK38

VSS[80]

AK4

VSS[81]

AK42

VSS[82]

AK46

VSS[83]

AK8

VSS[84]

AL16

VSS[85]

AL17

VSS[86]

AL19

VSS[87]

AL2

VSS[88]

AL21

VSS[89]

AL23

VSS[90]

AL26

VSS[91]

AL27

VSS[92]

AL31

VSS[93]

AL33

VSS[94]

AL34

VSS[95]

AL48

VSS[96]

AM11

VSS[97]

AM14

VSS[98]

AM36

VSS[99]

AM39

VSS[100]

AM43

VSS[101]

AM45

VSS[102]

AM46

VSS[103]

AM7

VSS[104]

AN2

VSS[105]

AN29

VSS[106]

AN3

VSS[107]

AN31

VSS[108]

AP12

VSS[109]

AP19

VSS[110]

AP28

VSS[111]

AP30

VSS[112]

AP32

VSS[113]

AP38

VSS[114]

AP4

VSS[115]

AP42

VSS[116]

AP46

VSS[117]

AP8

VSS[118]

AR2

VSS[119]

AR48

VSS[120]

AT11

VSS[121]

AT13

VSS[122]

AT18

VSS[123]

AT22

VSS[124]

AT26

VSS[125]

AT28

VSS[126]

AT30

VSS[127]

AT32

VSS[128]

AT34

VSS[129]

AT39

VSS[130]

AT42

VSS[131]

AT46

VSS[132]

AT7

VSS[133]

AU24

VSS[134]

AU30

VSS[135]

AV16

VSS[136]

AV20

VSS[137]

AV24

VSS[138]

AV30

VSS[139]

AV38

VSS[140]

AV4

VSS[141]

AV43

VSS[142]

AV8

VSS[143]

AW14

VSS[144]

AW18

VSS[145]

AW2

VSS[146]

AW22

VSS[147]

AW26

VSS[148]

AW28

VSS[149]

AW32

VSS[150]

AW34

VSS[151]

AW36

VSS[152]

AW40

VSS[153]

AW48

VSS[154]

AV11

VSS[155]

AY12

VSS[156]

AY22

VSS[157]

AY28

VSS[158]

3

U4I

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

COUGARPOINT_FCBGA989

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352]

2

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (9/9) VSS

LA-6882P

1

22 63Wednesday , October 06, 2010

0.2

of

CyberForum.ru

5

PCIE_CTX_GRX_N[0..15]<5>

PCIE_CTX_GRX_P[0..15]<5>

PCIE_CRX_GTX_N[0..15]<5>

PCIE_CRX_GTX_P[0..15]<5>

D D

+3VS_VGA

RV24

DIS@ RV24

DIS@

2.2K_0402_5%

VGA_SMB_CK2

VGA_SMB_DA2

C C

B B

A A

1 2

BUF_PLT_RST#<18,37,38, 44,45,49>

DGPU_HOLD_RST#< 18>

DGPU_PWR_EN<18,51,57,58,59>

CLK_REQ_VGA#<15>

+3VS_VGA

DIS@

RV25

2.2K_0402_5%

1 2

4

2

2N7002DW-T/R7_SOT363-6

DIS@

QV1A

2N7002DW-T/R7_SOT363-6

BUF_PLT_RST#

DGPU_HOLD_RST#

QV2

2N7002H 1N_SOT23-3

1 2

RV110 0_0402_5%

5

DIS@

QV1B

61

1 2

RV220 0_0402_5%

NC7SZ08P5X_NL_SC70-5

RV29

RV29 10K_0402_5%

10K_0402_5%

OPTI@

2

G

1 2

OPTI@

1 3

D

S

D

S

@

BLM18PG330SN1D_0603

+1.05VS_VGA

30ohms (ESR=0.01) Bead

3

1 2

LV1

DIS@

EC_SMB_CK2 <15,40,45,50>

EC_SMB_DA2 <15,40,45,50>

PU AT EC SIDE, +3VS AND 4.7K

+3VS_VGA +3VS_VGA

DIS_ONLY@

5

UV2

2

B

1

A

OPTI@

27MHZ_16PF_X5H027000FG1H

1

CV37

CV37 18P_0402_50V8J

18P_0402_50V8J

DIS@

2

+3VS_VGA

1 2

P

4

Y

G

12

3

XTALIN XTAL_OUT

1 2

RV23 10M_0402_5%

DIS@

YV1

21

DIS@

RV30

RV30 10K_0402_5%

10K_0402_5%

DIS@

CLK_REQ_GPU#

RV32

@RV32

@

10K_0402_5%

RV18

10K_0402_5%

@

RV105

RV105 10K_0402_5%

10K_0402_5%

PLT_RST_VGA#

OPTI@

1

2

PCIE_CTX_GRX_N[0..15]

PCIE_CTX_GRX_P[0..15]

PCIE_CRX_GTX_N[0..15]

PCIE_CRX_GTX_P[0..15]

Under GPU(below 150mils)

1

2

CV3

CV2

2

1

DIS@ CV2

DIS@

DIS@ CV3

DIS@

0.1U_0402_10V7K

10U_0603_6.3V6M

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_C_GTX_N4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_N9 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_N10 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_P12 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_P15 PCIE_CRX_GTX_N15

Differential signal

CV38

CV38 18P_0402_50V8J

18P_0402_50V8J

DIS@

1

CV1

2

DIS@ CV1

DIS@

0.1U_0402_10V7K

4

1

2

0.1U_0402_10V7K

CV6 0.1U_0402_10V6KDIS@CV6 0.1U_0402_10V6KDIS@ CV7 0.1U_0402_10V6KDIS@CV7 0.1U_0402_10V6KDIS@ CV8 0.1U_0402_10V6KDIS@CV8 0.1U_0402_10V6KDIS@ CV9 0.1U_0402_10V6KDIS@CV9 0.1U_0402_10V6KDIS@ CV10 0.1U_0402_10V6KDIS@CV10 0.1U_0402_10V6KDIS@ CV11 0.1U_0402_10V6KDIS@CV11 0.1U_0402_10V6KDIS@ CV12 0.1U_0402_10V6KDIS@CV12 0.1U_0402_10V6KDIS@ CV13 0.1U_0402_10V6KDIS@CV13 0.1U_0402_10V6KDIS@ CV14 0.1U_0402_10V6KDIS@CV14 0.1U_0402_10V6KDIS@ CV15 0.1U_0402_10V6KDIS@CV15 0.1U_0402_10V6KDIS@ CV16 0.1U_0402_10V6KDIS@CV16 0.1U_0402_10V6KDIS@ CV17 0.1U_0402_10V6KDIS@CV17 0.1U_0402_10V6KDIS@ CV18 0.1U_0402_10V6KDIS@CV18 0.1U_0402_10V6KDIS@ CV19 0.1U_0402_10V6KDIS@CV19 0.1U_0402_10V6KDIS@ CV20 0.1U_0402_10V6KDIS@CV20 0.1U_0402_10V6KDIS@ CV21 0.1U_0402_10V6KDIS@CV21 0.1U_0402_10V6KDIS@ CV22 0.1U_0402_10V6KDIS@CV22 0.1U_0402_10V6KDIS@ CV23 0.1U_0402_10V6KDIS@CV23 0.1U_0402_10V6KDIS@ CV24 0.1U_0402_10V6KDIS@CV24 0.1U_0402_10V6KDIS@ CV25 0.1U_0402_10V6KDIS@CV25 0.1U_0402_10V6KDIS@ CV26 0.1U_0402_10V6KDIS@CV26 0.1U_0402_10V6KDIS@ CV27 0.1U_0402_10V6KDIS@CV27 0.1U_0402_10V6KDIS@ CV28 0.1U_0402_10V6KDIS@CV28 0.1U_0402_10V6KDIS@ CV29 0.1U_0402_10V6KDIS@CV29 0.1U_0402_10V6KDIS@ CV239 0.1U_0402_10V6KDIS@CV239 0.1U_0402_10V6KDIS@ CV30 0.1U_0402_10V6KDIS@CV30 0.1U_0402_10V6KDIS@ CV31 0.1U_0402_10V6KDIS@CV31 0.1U_0402_10V6KDIS@ CV32 0.1U_0402_10V6KDIS@CV32 0.1U_0402_10V6KDIS@ CV33 0.1U_0402_10V6KDIS@CV33 0.1U_0402_10V6KDIS@ CV34 0.1U_0402_10V6KDIS@CV34 0.1U_0402_10V6KDIS@ CV35 0.1U_0402_10V6KDIS@CV35 0.1U_0402_10V6KDIS@ CV36 0.1U_0402_10V6KDIS@CV36 0.1U_0402_10V6KDIS@

4

CV4

DIS@ CV4

DIS@

0.1U_0402_10V7K

DIS@

12

RV27

RV27 10K_0402_5%

10K_0402_5%

DIS@

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

150mA

+PLLVDD

1

CV5

2

DIS@ CV5

DIS@

CLK_PCIE_VGA<15>

CLK_PCIE_VGA#<15>

@

1 2

RV20 200_0402_1%

1 2

RV22 2.49K_0402_1%DIS@RV22 2.49K_0402_1%DIS@

SP_PLLVDD, PLLVDD and VID_PLLVDD Combined

RV26 10K_0402_5%DIS@RV26 10K_0402_5%DIS@

Internal Thermal Sensor

VGA_EDID_CLK<34>

LVDS

VGA_EDID_DATA<34>

I2CB_SCL<33> I2CB_SDA<33>

VGA_CRT_CLK<35>

CRT

VGA_CRT_DATA<35>

PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_P15 PCIE_CTX_GRX_N15

PCIE_CRX_C_GTX_P0 PCIE_CRX_C_GTX_N0 PCIE_CRX_C_GTX_P1 PCIE_CRX_C_GTX_N1 PCIE_CRX_C_GTX_P2 PCIE_CRX_C_GTX_N2 PCIE_CRX_C_GTX_P3 PCIE_CRX_C_GTX_N3 PCIE_CRX_C_GTX_P4

PCIE_CRX_C_GTX_P5 PCIE_CRX_C_GTX_N5 PCIE_CRX_C_GTX_P6 PCIE_CRX_C_GTX_N6 PCIE_CRX_C_GTX_P7 PCIE_CRX_C_GTX_N7 PCIE_CRX_C_GTX_P8 PCIE_CRX_C_GTX_N8 PCIE_CRX_C_GTX_P9 PCIE_CRX_C_GTX_N9 PCIE_CRX_C_GTX_P10 PCIE_CRX_C_GTX_N10 PCIE_CRX_C_GTX_P11 PCIE_CRX_C_GTX_N11 PCIE_CRX_C_GTX_P12 PCIE_CRX_C_GTX_N12 PCIE_CRX_C_GTX_P13 PCIE_CRX_C_GTX_N13 PCIE_CRX_C_GTX_P14 PCIE_CRX_C_GTX_N14 PCIE_CRX_C_GTX_P15 PCIE_CRX_C_GTX_N15

CLK_PCIE_VGA CLK_PCIE_VGA# CLK_REQ_GPU#

PEX_TSTC LK_OUT PEX_TSTC LK_OUT#

PLT_RST_VGA#

PEX_TERM P

+PLLVDD

XTALIN XTAL_OUT

XTALOUT XTALSSIN

12

VGA_SMB_CK2 VGA_SMB_DA2

VGA_EDID_CLK VGA_EDID_DATA

I2CB_SCL I2CB_SDA

VGA_CRT_CLK VGA_CRT_DATA

HDCP_SCL HDCP_SDA

60mA

45mA

AM17 AM18 AM19

AM20 AM21 AM22

AM23 AM24 AM25

AM26 AM27 AM28

AM29 AM30 AM31 AM32

AM16

AP17 AN17 AN19 AP19 AR19 AR20 AP20 AN20 AN22 AP22 AR22 AR23 AP23 AN23 AN25 AP25 AR25 AR26 AP26 AN26 AN28 AP28 AR28 AR29 AP29 AN29 AN31 AP31 AR31 AR32 AR34 AP34

AL17

AL19 AK19 AL20

AL22 AK22 AL23

AL25 AK25 AL26

AL28 AK28 AK29 AL29

AN32 AP32

AR16 AR17 AR13

AG21

AJ17 AJ18

AE9

AF9

AD9

B1 B2

D1 D2

E2 E1

E3 E4

G3 G2

G1 G4

F6 G6

3

UV1A

Part 1 of 7

PEX_RX0 PEX_RX0_N PEX_RX1 PEX_RX1_N PEX_RX2 PEX_RX2_N PEX_RX3 PEX_RX3_N PEX_RX4 PEX_RX4_N PEX_RX5 PEX_RX5_N PEX_RX6 PEX_RX6_N PEX_RX7 PEX_RX7_N PEX_RX8 PEX_RX8_N PEX_RX9 PEX_RX9_N PEX_RX10 PEX_RX10_N PEX_RX11 PEX_RX11_N PEX_RX12 PEX_RX12_N PEX_RX13 PEX_RX13_N PEX_RX14 PEX_RX14_N PEX_RX15 PEX_RX15_N

PEX_TX0 PEX_TX0_N PEX_TX1 PEX_TX1_N PEX_TX2 PEX_TX2_N PEX_TX3 PEX_TX3_N PEX_TX4 PEX_TX4_N PEX_TX5 PEX_TX5_N PEX_TX6 PEX_TX6_N PEX_TX7 PEX_TX7_N PEX_TX8 PEX_TX8_N PEX_TX9 PEX_TX9_N PEX_TX10 PEX_TX10_N PEX_TX11 PEX_TX11_N PEX_TX12 PEX_TX12_N PEX_TX13 PEX_TX13_N PEX_TX14 PEX_TX14_N PEX_TX15 PEX_TX15_N

PEX_REFCLK PEX_REFCLK_N PEX_CLKREQ_N

PEX_TSTCLK_OUT PEX_TSTCLK_OUT_N

PEX_RST_ N PEX_TERM P

PLLVDD

SP_PLLVDD

VID_PLLVDD

XTAL_IN XTAL_OUT

XTAL_OUTBUFF XTAL_SSIN

I2CS_SCL I2CS_SDA

I2CC_SCL I2CC_SDA

I2CB_SCL I2CB_SDA

I2CA_SCL I2CA_SDA

I2CH_SCL I2CH_SDA

N12P-GT1-A1_BGA_973P DIS@

Part 1 of 7

GPIO

DVO

PCI EXPRESS

MIOA_HSYNC_NC MIOA_VSYNC_NC

MIOB_HSYNC_NC MIOB_VSYNC_NC

MIOA_CLKOUT_NC

MIOB_CLKOUT_NC

MIOA_CLKOUT_NC_N MIOB_CLKOUT_NC_N

MIOACAL_PD_VDDQ_NC

MIOACAL_PU_GND_NC

MIOBCAL_PD_VDDQ_NC

MIOBCAL_PU_GND_NC

CLK

DACs

I2C

3

MIOA_CLKIN_NC

MIOB_CLKIN_NC

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24

MIOA_D0_NC MIOA_D1_NC MIOA_D2_NC MIOA_D3_NC MIOA_D4_NC MIOA_D5_NC MIOA_D6_NC MIOA_D7_NC MIOA_D8_NC

MIOA_D9_NC MIOA_D10_NC MIOA_D11_NC MIOA_D12_NC MIOA_D13_NC MIOA_D14_NC

MIOB_D0_NC

MIOB_D1_NC

MIOB_D2_NC

MIOB_D3_NC

MIOB_D4_NC

MIOB_D5_NC

MIOB_D6_NC

MIOB_D7_NC

MIOB_D8_NC

MIOB_D9_NC MIOBD_10_NC MIOB_D11_NC MIOB_D12_NC MIOB_D13_NC MIOB_D14_NC

MIOA_DE_NC

MIOA_CTL3_NC MIOA_VREF_NC

MIOB_DE_NC

MIOB_CTL3_NC MIOB_VREF_NC

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_HSYNC

DACA_VSYNC

DACA_VDD DACA_VREF DACA_RSET

DACB_RED

DACB_GREEN

DACB_BLUE

DACB_HSYNC

DACB_VSYNC

DACB_VDD DACB_VREF DACB_RSET

2

K1

VGA_GPIO1

K2

VGA_BL_PWM

K3 H3 H2 H1 H4 H5 H6 J7 K4 K5 H7 J4 J6 L1 L2 L4 M4 L7 L5 K6 L6 M6 M7

N1 P4 P1 P2 P3 T3 T2 T1 U4 U1 U2 U3 R6 T6 N6

Y1 Y2 Y3 AB3 AB2 AB1 AC4 AC1 AC2 AC3 AE3 AE2 U6 W6 Y6

N3 L3

W1 W2

N2 P5 N5

Y5 W3 AF1

N4 R4

AE1 V4

T4 W4

U5 T5

AA7 AA6

AM15 AM14 AL14

AM13 AL13

AJ12 AK12 AK13

AK4 AL4 AJ4

AM1 AM2

AG7 AK6 AH7

VGA_ENVDD VGA_ENBKL GPU_VID0 GPU_VID1

OVERT# THERM#_VGA

GPIO12

RV19 10K_0402_5%DIS@RV19 10K_0402_5%DIS@

RV21 10K_0402_5%DIS@RV21 10K_0402_5%DIS@

VGA_CRT_R VGA_CRT_G VGA_CRT_B

VGA_CRT_HSYNC VGA_CRT_VSYNC

+DACA_VDD +DACA_VREF DACA_RSET

124_0402_1%

DIS_ONLY@

+DACB_VDD

VGA_BL_PWM <34> VGA_ENVDD <34> VGA_ENBKL <34> GPU_VID0 <59> GPU_VID1 <59>

MEM_VREF <28,29,30,31>

TV1TV1

dGPU_HDMI_HPD

1 2

VGA_CRT_R <35> VGA_CRT_G <35> VGA_CRT_B <35>

VGA_CRT_HSYNC <35> VGA_CRT_VSYNC <35>

12

1

RV107

CV130

2

DIS_ONLY@

0.1U_0402_10V7K

1 2

RV31 10K_0402_5%DIS@RV31 10K_0402_5%DIS@

Security Classification

Security Classification Compal Secret Data

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

@

4

1 2

RV104 0_0402_5%DIS_ONLY@ RV104 0_0402_5%DIS_ONLY@

UV14

Y

+3VS_VGA

@ CV252

@

1 2

5

0.1U_0402_16V4Z

2

P

B

1

A

G

3

NC7SZ08P5X_NL_SC70-5

OVERT#

GPIO12

VGA_EDID_CLK

VGA_EDID_DATA

THERM#_VGA

HDCP_SCL

HDCP_SDA

VGA_CRT_DATA

VGA_CRT_CLK

I2CB_SCL

I2CB_SDA

VGA_ENVDD

VGA_ENBKL

VGA_BL_PWM

VGA_GPIO1

120mA

+DACA_VDD

CV252

1

CV124

2

0.1U_0402_10V7K

DIS_ONLY@ CV124

DIS_ONLY@

VGA_PGOOD <19,59>

VGA_HDMI_HPD <36>

1 2

RV1 10K_0402_5%DIS@RV1 10K_0402_5%DIS@

1 2

RV2 10K_0402_5%DIS@RV2 10K_0402_5%DIS@

1 2

RV3 2.2K_0402_5%DIS@RV3 2.2K_0402_5%DIS@

1 2

RV4 2.2K_0402_5%DIS@RV4 2.2K_0402_5%DIS@

1 2

RV7 100K_0402_5%DIS@RV7 100K_0402_5%DIS@

1 2

RV8 2.2K_0402_5%DIS@RV8 2.2K_0402_5%DIS@

1 2

RV9 2.2K_0402_5%DIS@RV9 2.2K_0402_5%DIS@

1 2

RV10 2.2K_0402_5%DIS@RV10 2.2K_0402_5%DIS@

1 2

RV11 2.2K_0402_5%DIS@RV11 2.2K_0402_5%DIS@

1 2

RV12 2.2K_0402_5%DIS@RV12 2.2K_0402_5%DIS@

1 2

RV13 2.2K_0402_5%DIS@RV13 2.2K_0402_5%DIS@

DIS@

1 2

RV14 10K_0402_5%

1 2

RV15 10K_0402_5%

RV16 10K_0402_5%@RV16 10K_0402_5%@

1 2

RV17 100K_0402_5%DIS@R V17 100K_0402_5%DIS@

CV124

10K_0402_5%

OPTI@

1

CV125

2

0.1U_0402_10V7K

DIS_ONLY@ CV125

DIS_ONLY@

Close to GPU

VGA_CRT_R

VGA_CRT_G

VGA_CRT_B

2010/07/09 2011/05/11

1 2

RV106 150_0402_1%DIS_ONLY@RV106 150_0402_1%DIS_ONLY@

1 2

RV108 150_0402_1%DIS_ONLY@RV108 150_0402_1%DIS_ONLY@

1 2

RV109 150_0402_1%DIS_ONLY@RV109 150_0402_1%DIS_ONLY@

Compal Secret Data

Deciphered Date

2

@

12

1

CV126

2

0.1U_0402_10V7K

DIS_ONLY@ CV126

DIS_ONLY@

+3VS_VGA

1

CV122

2

0.1U_0402_10V7K

DIS_ONLY@ CV122

DIS_ONLY@

7/12 Update

OVERT#

2

At LVDS site

Near GPUUnder GPU

1

CV127

2

1U_0402_6.3V4Z

DIS_ONLY@ CV127

DIS_ONLY@

1

+3VS_VGA

12

61

QV7A

QV7A DMN66D0LDW-7 2N_SOT363-6

DMN66D0LDW-7 2N_SOT363-6

DIS@

1

2

4.7U_0603_6.3V6K

Title

Size Document Number Rev

Date: Sheet

PCH_THRMTRIP#_R

RV208

3

10K_0402_5%

DIS@

CV128

DIS_ONLY@ CV128

DIS_ONLY@

QV7B

QV7B DMN66D0LDW-7 2N_SOT363-6

DMN66D0LDW-7 2N_SOT363-6

5

DIS@

4

300 ohms @100MHz (ESR=0.25)

LV5

DIS_ONLY@LV5

DIS_ONLY@

1 2

MMZ1608D301BT_0603

Compal Electronics, Inc.

N12P-PCIE/DAC/GPIO

LA-6882P

1

PCH_THRMTRIP#_R <19>

+3VS_VGA

23 63W ednesday, October 06, 2010

0.2

of

CyberForum.ru

5

VGA_TXCLK+<34>

VGA_TXCLK-<34>

VGA_TXOUT0+<34>

VGA_TXOUT0-<34>

VGA_TXOUT1+<34>

VGA_TXOUT1-<34>

VGA_TXOUT2+<34>

VGA_TXOUT2-<34>

D D

VGA_TZCLK+<34>

VGA_TZCLK-<34>

VGA_TZOUT0+<34>

VGA_TZOUT0-<34>

VGA_TZOUT1+<34>

VGA_TZOUT1-<34>

VGA_TZOUT2+<34>

VGA_TZOUT2-<34>

C C

VGA_HDMI_TX2+<36> VGA_HDMI_TX2-<36> VGA_HDMI_TX1+<36> VGA_HDMI_TX1-<36> VGA_HDMI_TX0+<36> VGA_HDMI_TX0-<36>

VGA_HDMI_CLK+<36>

VGA_HDMI_CLK-<36>

B B

+3VS_VGA

1 2

RV113 4.7K_0402_5%

DIS_ONLY@

1 2

RV114 4.7K_0402_5%

DIS_ONLY@

A A

VGA_HDMI_CLK

VGA_HDMI_DATA

HDMI

VGA_HDMI_CLK<36> VGA_HDMI_DATA<36>

STRAP0<32> STRAP1<32> STRAP2<32>

4

VGA_TXCLK+ VGA_TXCLKVGA_TXOUT0+ VGA_TXOUT0VGA_TXOUT1+ VGA_TXOUT1VGA_TXOUT2+ VGA_TXOUT2-

VGA_TZCLK+ VGA_TZCLKVGA_TZOUT0+ VGA_TZOUT0VGA_TZOUT1+ VGA_TZOUT1VGA_TZOUT2+ VGA_TZOUT2-

VGA_HDMI_TX2+

VGA_HDMI_TX2-

VGA_HDMI_TX1+

VGA_HDMI_TX1-

VGA_HDMI_TX0+

VGA_HDMI_TX0-

VGA_HDMI_CLK+

VGA_HDMI_CLK-

VGA_HDMI_CLK VGA_HDMI_DATA

+3VS_VGA

RV35

RV35 10K_0402_5%

10K_0402_5%

DIS@

1 2

STRAP0 STRAP1 STRAP2

UV1D

AM11

IFPA_TXC

AM12

IFPA_TXC_N

AM8

IFPA_TXD0

AL8

IFPA_TXD0_N

AM10

IFPA_TXD1

AM9

IFPA_TXD1_N

AK10

IFPA_TXD2

AL10

IFPA_TXD2_N

AK11

IFPA_TXD3

AL11

IFPA_TXD3_N

AP13

IFPB_TXC

AN13

IFPB_TXC_N

AN8

IFPB_TXD4

AP8

IFPB_TXD4_N

AP10

IFPB_TXD5

AN10

IFPB_TXD5_N

AR11

IFPB_TXD6

AR10

IFPB_TXD6_N

AN11

IFPB_TXD7

AP11

IFPB_TXD7_N

AM7

IFPC_L0

AM6

IFPC_L0_N

AL5

IFPC_L1

AM5

IFPC_L1_N

AM3

IFPC_L2

AM4

IFPC_L2_N

AP1

IFPC_L3

AR2

IFPC_L3_N

AR8

IFPD_L0

AR7

IFPD_L0_N

AP7

IFPD_L1

AN7

IFPD_L1_N

AN5

IFPD_L2

AP5

IFPD_L2_N

AR5

IFPD_L3

AR4

IFPD_L3_N

AH6

IFPE_L0

AH5

IFPE_L0_N

AH4

IFPE_L1

AG4

IFPE_L1_N

AF4

IFPE_L2

AF5

IFPE_L2_N

AE6

IFPE_L3

AE5

IFPE_L3_N

AL2

IFPF_L0

AL3

IFPF_L0_N

AJ3

IFPF_L1

AJ2

IFPF_L1_N

AJ1

IFPF_L2

AH1

IFPF_L2_N

AH2

IFPF_L3

AH3

IFPF_L3_N

AP2

IFPC_AUX_I2CW_SCL

AN3

IFPC_AUX_I2CW_SDA_N

AP4

IFPD_AUX_I2CX_SCL

AN4

IFPD_AUX_I2CX_SDA_N

AE4

IFPE_AUX_I2CY_SCL

AD4

IFPE_AUX_I2CY_SDA_N

AF3

IFPF_AUX_I2CZ_SCL

AF2

IFPF_AUX_I2CZ_SDA_N

A4

BUFRST_N

AB5

CEC

W5

STRAP0

W7

STRAP1

V7

STRAP2

N12P-GT1-A1_BGA_973P DIS@

Part 4 of 7

GENERAL

3

A2

NC_0

A7

NC_1

B7

NC_2

C5

NC_3

C7

NC_4

D5

NC_5

D6

NC_6

D7

NC_7

E5

NC_8

E7

NC_9

F4

NC_10

G5

NC_11

H32

NC_12

J25

NC_13

J26

NC_14

P6

NC_15

U7

NC_16

V6

NC_17

Y4

NC_18

AA4

NC_19

AB4

NC_20

AB7

NC_21

AC5

NC_22

AD6

NC_23

AF6

NC_24

AG6

NC_25

AG20

NC_26

NC

VDD_SENSE_0

LVDS/TMDS

VDD_SENSE_1 VDD_SENSE_2

GND_SENSE_0 GND_SENSE_1 GND_SENSE_2

TEST

TESTMODE

JTAG_TRST_N

SERIAL

ROM_CS_N

ROM_SCLK

NC/SPDIF_NC

MULTI_STRAP_REF0_GND

MULTI_STRAP_REF1_GND

NC_27 NC_28 NC_29

JTAG_TCK

JTAG_TDI JTAG_TDO JTAG_TMS

ROM_SI

ROM_SO

THERMDP THERMDN

AJ5 AK15 AL7

D35 P7 AD20

AD19 E35 R7

AP35 AP14 AN14 AN16 AR14 AP16

C3 D3 C4 D4

A5

N9

M9

B5 B4

VDD_SENSE_VGA

GND_SENSE_VGA

trace width: 16mils differential voltage sensing. differential signal routing.

TESTMODE

1 2

RV34 10K_0402_5%

DIS@

ROM_SI ROM_SO ROM_SCLK

1 2

RV36 36K_0402_5%@RV36 36K_0402_5%@

1 2

RV37 40.2K_0402_1%DIS@RV37 40.2K_0402_1%DIS@

1 2

RV38 40.2K_0402_1%DIS@RV38 40.2K_0402_1%DIS@

VDD_SENSE_VGA <59>

GND_SENSE_VGA <59>

TV2TV2 TV3TV3 TV4TV4 TV5TV5

ROM_SI <32> ROM_SO <32> ROM_SCLK <32>

12

10K_0402_5%

10K_0402_5% RV33

RV33

DIS@

2

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL EL ECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIO N IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL EL ECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIO N IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL EL ECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIO N IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CON SENT OF COMPAL ELE CTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CON SENT OF COMPAL ELE CTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CON SENT OF COMPAL ELE CTRONICS, INC.

2010/07/09 2011/05/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

N12P-LVDS/HDMI/DP/THM

LA-6882P

24 63Wednesday, October 06, 2010

1

0.2

of

CyberForum.ru

5

+1.35VS_VGA

D D

C C

B B

For GDDR5 setting. Near GPU

1

2

4.7U_0603_6.3V6K

1

CV261

2

DIS@ CV261

DIS@

4.7U_0603_6.3V6K

+1.35VS_VGA

1

CV262

CV263

2

DIS@ CV262

DIS@

DIS@ CV263

DIS@

4.7U_0603_6.3V6K

1

CV277

2

DIS@ CV277

DIS@

1U_0402_6.3V6K

120ohms @100MHz (ESR=0.18)

180ohms @100MHz (ESR=0.2)

+1.8VS

BLM18PG181SN1D_0603

1

CV264

CV265

2

DIS@ CV264

DIS@

DIS@ CV265

DIS@

4.7U_0603_6.3V6K

Under GPU(below 150mils)

1

CV279

CV278

2

DIS@ CV279

DIS@

DIS@ CV278

DIS@

1U_0402_6.3V6K

+1.05VS_VGA

LV6

BLM18PG181SN1D_0603

DIS_ONLY@

CV141

10K_0402_5%

OPTI@

LV8

12

DIS_ONLY@

CV145

4.7U_0603_6.3V6K

10K_0402_5%

OPTI@

1

CV266

CV267

2

DIS@ CV266

DIS@

DIS@ CV267

DIS@

4.7U_0603_6.3V6K

1

CV280

2

DIS@ CV280

DIS@

1U_0402_6.3V6K

0.47U_0402_6.3V6K

2

CV268

1

DIS@ CV268

DIS@

10U_0603_6.3V6M

1

CV281

2

DIS@

2

CV270

CV269

1

DIS@ CV270

DIS@

DIS@ CV269

DIS@

10U_0603_6.3V6M

1

CV282

2

DIS@

0.47U_0402_6.3V6K

Under GPU(below 150mils)

12

4.7U_0603_6.3V6K

1

CV142

2

DIS_ONLY@ CV142

DIS_ONLY@

200mA

1

CV139

2

1U_0402_6.3V6K

DIS_ONLY@ CV139

DIS_ONLY@

1

CV143

2

1U_0402_6.3V6K

0.1U_0402_10V7K

DIS_ONLY@ CV143

DIS_ONLY@

+IFPAB_PLLVDD

1

CV140

CV141

2

0.1U_0402_10V7K

DIS_ONLY@ CV141

DIS_ONLY@

DIS_ONLY@ CV140

DIS_ONLY@

1

CV145

CV144

2

0.1U_0402_10V7K

DIS_ONLY@ CV145

DIS_ONLY@

DIS_ONLY@ CV144

DIS_ONLY@

Under GPU(below 150mils)

4

2

CV271

1

DIS@ CV271

DIS@

10U_0603_6.3V6M

1

CV283

2

DIS@

300mA

+IFPAB_IOVDD

IFPA_IOVDD and IFPB_IOVDD combined

1

CV273

CV272

2

DIS@ CV273

DIS@

DIS@ CV272

DIS@

22U_0805_6.3V6M

1

CV284

2

DIS@ CV284

DIS@

0.1U_0402_10V7K

@

1 2

RV40 1K_0402_1%

@

1 2

RV43 1K_0402_1%

@

1 2

RV46 1K_0402_1%

DIS@

1 2

RV50 1K_0402_1%

CV274

DIS@ CV274

DIS@

1

2

RV42 10K_0402_5%

RV44 10K_0402_5%

RV45 10K_0402_5%

RV47 10K_0402_5%

220ohms @100MHz (ESR=0.05)

UV1E

3.5A

J23 J24

LV9

DIS_ONLY@

12

J29 AA27 AA29 AA31 AB27 AB29 AC27 AD27 AE27

AJ28

B18 E21 G17 G18 G22

G8 G9

H29

J14

J15

J16

J17

J20

J21

J22

N27 P27 R27

T27

U27 U29 V27 V29 V34

W27

Y27

AK9

AJ11

AG9

AG10

AJ9

AK7

AJ8

AC6 AB6

AK8

AJ6

AL1

AE7 AD7

12

1

2

4.7U_0603_6.3V6K

Under GPU(below 150mils)

1

CV151

2

DIS_ONLY@ CV151

DIS_ONLY@

4.7U_0603_6.3V6K

1

CV276

CV275

2

DIS@ CV276

DIS@

DIS@ CV275

DIS@

22U_0805_6.3V6M

1

CV286

CV285

2

DIS@ CV286

DIS@

DIS@ CV285

DIS@

0.1U_0402_10V7K

+IFPAB_PLLVDD

+IFPAB_IOVDD

+IFPC_PLLVDD

DIS@

12

DIS@

+IFPC_IOVDD

12

DIS@

+IFPD_PLLVDD

12

+IFPD_IOVDD

DIS@

12

+IFPEF_PLLVDD

+IFPE_IOVDD

300ohms @100MHz (ESR=0.25)

+3VS_VGA

BLM18PG181SN1D_0603

+1.05VS_VGA

LV10

BLM18PG181SN1D_0603

DIS_ONLY@

3

Part 5 of 7

FBVDDQ_0 FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37

IFPAB_PLLVDD IFPAB_RSET

IFPA_IOVDD IFPB_IOVDD

IFPC_PLLVDD IFPC_RSET

IFPC_IOVDD

IFPD_PLLVDD IFPD_RSET

IFPD_IOVDD

IFPEF_PLLVDD IFPEF_RSET

IFPE_IOVDD IFPF_IOVDD

N12P-GT1-A1_BGA_973P DIS@

PEX_IOVDDQ_0 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8

PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14 PEX_IOVDDQ_15 PEX_IOVDDQ_16 PEX_IOVDDQ_17 PEX_IOVDDQ_18 PEX_IOVDDQ_19 PEX_IOVDDQ_20 PEX_IOVDDQ_21 PEX_IOVDDQ_22 PEX_IOVDDQ_23 PEX_IOVDDQ_24

PEX_IOVDD_0 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4

POWER

PEX_PLLVDD

PEX_SVDD_3V3

PEX_SVDD_3V3_NC

VDD33_0 VDD33_1 VDD33_2 VDD33_3 VDD33_4

MIOA_VDDQ_NC_0 MIOA_VDDQ_NC_1 MIOA_VDDQ_NC_2 MIOA_VDDQ_NC_3

MIOB_VDDQ_NC_0 MIOB_VDDQ_NC_1 MIOB_VDDQ_NC_2 MIOB_VDDQ_NC_3

Under GPU(below 150mils)

1

CV146

CV147

2

1U_0402_6.3V6K

DIS_ONLY@ CV146

DIS_ONLY@

DIS_ONLY@ CV147

DIS_ONLY@

1

CV152

2

0.1U_0402_10V7K

1U_0402_6.3V6K

DIS_ONLY@ CV152

DIS_ONLY@

1

CV148

CV149

2

0.1U_0402_10V7K

DIS_ONLY@ CV148

DIS_ONLY@

DIS_ONLY@ CV149

DIS_ONLY@

+IFPE_IOVDD

1

CV154

CV153

2

0.1U_0402_10V7K

DIS_ONLY@ CV154

DIS_ONLY@

DIS_ONLY@ CV153

DIS_ONLY@

AG11 AG12 AG13 AG15 AG16 AG17 AG18 AG22 AG23 AG24 AG25 AG26 AJ14 AJ15 AJ19 AJ21 AJ22 AJ24 AJ25 AJ27 AK18 AK20 AK23 AK26 AL16

AK16 AK17 AK21 AK24 AK27

AG14

AG19 F7

J10 J11 J12 J13 J9

P9 R9 T9 U9

AA9 AB9 W9 Y9

220mA

1

2

0.1U_0402_10V7K

570mA

CV154

10K_0402_5%

OPTI@

2000mA

1U_0402_6.3V6K

Under GPU(below 150mils)

0.1U_0402_10V7K

120mA

+PEX_PLLVDD

240mA (120mA each)

120mA(12~16mils)

RV48

RV48 10K_0402_5%

10K_0402_5%

DIS@

1 2

RV52

RV52 10K_0402_5%

10K_0402_5%

DIS@

1 2

+IFPEF_PLLVDD

CV150

10K_0402_5%

DIS_ONLY@ CV150

DIS_ONLY@

OPTI@

Near GPU

1

CV44

CV43

2

DIS@ CV44

DIS@

DIS@ CV43

DIS@

1U_0402_6.3V6K

1

CV53

CV54

2

DIS@ CV53

DIS@

DIS@ CV54

DIS@

0.1U_0402_10V7K

Under GPU(below 150mils)

1

2

0.1U_0402_10V7K

1

2

0.1U_0402_10V7K

Under GPU(below 150mils)

1

CV45

2

DIS@ CV45

DIS@

1U_0402_6.3V6K

1

CV55

2

DIS@ CV55

DIS@

0.1U_0402_10V7K

1

CV65

CV66

2

DIS@ CV66

DIS@

DIS@ CV65

DIS@

1U_0402_6.3V6K

1

CV71

CV70

2

DIS@ CV71

DIS@

DIS@ CV70

DIS@

0.1U_0402_10V7K

DGPU_PWR_EN#<51>

CV46

DIS@ CV46

DIS@

CV56

DIS@ CV56

DIS@

4.7U_0603_6.3V6K

1

2

1U_0402_6.3V6K

2

Close to PEX_IOVDD PIN: AK16, AK17, AK21, AK24, and AK27

2

1

CV48

CV47

2

DIS@ CV47

DIS@

4.7U_0603_6.3V6K

+1.05VS_VGA

1

CV67

2

DIS@ CV67

DIS@

+3VS_VGA

CV72

DIS@ CV72

DIS@

4.7U_0603_6.3V6K

1

2

1

2

DIS@ CV48

DIS@

10U_0603_6.3V6M

4.7U_0603_6.3V6K

LV2

BLM18PG121SN1D_0603

1

2

0.1U_0402_10V7K

CV73

DIS@ CV73

DIS@

+3VS to +3VS_VGA

OPTI@

RV205

1 2

10K_0402_5%

1

2

CV49

CV50

1

DIS@ CV49

DIS@

DIS@ CV50

DIS@

10U_0603_6.3V6M

+1.05VS_VGA

12

120ohms @100MHz (ESR=0.18)

+1.05VS_VGA

1

CV68

CV287

2

DIS@ CV287

DIS@

DIS@ CV68

DIS@

4.7U_0603_6.3V6K

1U_0402_6.3V6K

+3VS +3VS_VGA

QV5

AO3413_SOT23

OPTI@

S

G

2

1

CV241

2

OPTI@ CV241

OPTI@

0.1U_0402_10V7K

1

CV51

2

DIS@ CV51

DIS@

22U_0805_6.3V6M

1

CV69

2

DIS@ CV69

DIS@

D

13

12

RV206

RV206 470_0603_5%

470_0603_5%

@

13

D

G

QV6

S

2N7002_SOT23

@

1

+1.05VS_VGA

CV52

DIS@ CV52

DIS@

J10

+3VS +3VS_VGA

@

RV207

2

10K_0402_5%

1

CV242

@ CV242

@

2

0.1U_0402_10V7K

112

JUMP_43X79

@

12

2

DGPU_PWR_EN# <51>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/07/09 2011/05/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

N12P-POWER

LA-6882P

1

of

25 63Wednesday, October 06, 2010

of

25 63Wednesday, October 06, 2010

of

25 63Wednesday, October 06, 2010

0.2

CyberForum.ru

5

UV1G

AB11

VDD_0

Part 7 of 7

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55

5

Part 7 of 7

D D

C C

B B

A A

AB13 AB15 AB17 AB19 AB21 AB23

AB25 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AD12 AD14 AD16 AD18 AD22 AD24

L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24

L25 M12 M14 M16 M18 M20 M22 M24

P11

P13

P15

P17

P19

N12P-GT1-A1_BGA_973P

DIS@

VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71 VDD_72 VDD_73 VDD_74 VDD_75 VDD_76 VDD_77 VDD_78 VDD_79 VDD_80 VDD_81 VDD_82 VDD_83 VDD_84 VDD_85 VDD_86 VDD_87 VDD_88 VDD_89

POWER

VDD_90 VDD_91 VDD_92 VDD_93 VDD_94 VDD_95 VDD_96 VDD_97 VDD_98

VDD_99 VDD_100 VDD_101 VDD_102 VDD_103 VDD_104 VDD_105 VDD_106 VDD_107 VDD_108 VDD_109 VDD_110

P21 P23 P25 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 T12 T14 T16 T18 T20 T22 T24 V11 V13 V15 V17 V19 V21 V23 V25 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 Y12 Y14 Y16 Y18 Y20 Y22 Y24

+VGA_CORE+VGA_CORE

4

Near GPU

+VGA_CORE

2

1

10U_0603_6.3V6M

Under GPU

+VGA_CORE

1

2

0.047U_0402_25V6K

+VGA_CORE

1

2

0.01U_0402_25V7K

4

3

1

2

CV77

1

DIS@ CV77

DIS@

10U_0603_6.3V6M

1

CV82

2

DIS@ CV82

DIS@

0.047U_0402_25V6K

1

CV94

2

DIS@ CV94

DIS@

0.01U_0402_25V7K

1

CV79

CV78

DIS@ CV78

DIS@

CV83

DIS@ CV83

DIS@

CV95

DIS@ CV95

DIS@

CV79

@

2

47U_0805_4V6

1

CV84

2

DIS@ CV84

DIS@

0.047U_0402_25V6K

0.022U_0402_25V7K

1

CV96

2

DIS@ CV96

DIS@

0.01U_0402_25V7K

1

CV80

CV81

2

DIS@ CV80

DIS@

DIS@ CV81

DIS@

22U_0805_6.3V6M

4.7U_0603_6.3V6K

1

CV88

2

DIS@

1

CV100

2

DIS@ CV100

DIS@

Issued Date

3

1

CV89

CV90

2

DIS@ CV89

DIS@

0.1U_0402_10V7K

1

CV101

2

DIS@ CV101

DIS@

0.22U_0402_6.3V6K

0.01U_0402_25V7K

CV91

2

DIS@ CV90

DIS@

DIS@ CV91

DIS@

4700P_0402_25V7K

12

CV102

CV103

DIS@

0.22U_0402_6.3V6K

2010/07/09 2011/05/11

CV93

CV92

DIS@ CV93

DIS@

DIS@ CV92

DIS@

4700P_0402_25V7K

12

CV104

DIS@

Compal Secret Data

Deciphered Date

1

CV85

2

DIS@ CV85

DIS@

0.022U_0402_25V7K

1

CV97

2

DIS@ CV97

DIS@

0.01U_0402_25V7K

CV87

CV86

2

DIS@ CV87

DIS@

DIS@ CV86

DIS@

CV98

DIS@ CV98

DIS@

1U_0603_10V6K

0.022U_0402_25V7K

1

CV99

2

DIS@ CV99

DIS@

0.01U_0402_25V7K

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INF ORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INF ORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INF ORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRON ICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CON TAINS

DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRON ICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CON TAINS

DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRON ICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CON TAINS MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WIT HOUT PRIOR WRIT TEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WIT HOUT PRIOR WRIT TEN CONSENT OF CO MPAL ELECTRONICS, INC.

1

2

UV1F

B3 B6

B9 B12 B15 B21 B24 B27 B30 B33

C2

C34

E6

E9 E12 E15 E18 E24 E27 E30

F2 F31 F34

F5

J2

J5 J31 J34

K9

L9

M2

M5 M11 M13 M15 M17 M19 M21 M23 M25 M31 M34 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25

P12 P14 P16 P18 P20 P22 P24

R2

R5 R31 R34

T11 T13 T15 T17 T19 T21 T23

T25 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25

V2 V5

V9 V12 V14 V16

N12P-GT1-A1_BGA_973P

DIS@

2

Part 6 of 7

GND_0 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96

GND

Title

Size Document Number Rev

Date: Sh eet

GND_97 GND_98

GND_99 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192

Compal Electronics, Inc.

N12P-VGA CORE, GND

V18 V20 V22 V24 V31 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25 AA2 AA5 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA34 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AC9 AD2 AD5 AD11 AD13 AD15 AD17 AD21 AD23 AD25 AD31 AD34 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AG2 AG5 AG31 AG34 AK2 AK5 AK14 AK31 AK34 AL6 AL9 AL12 AL15 AL18 AL21 AL24 AL27 AL30 AN2 AN34 AP3 AP6 AP9 AP12 AP15 AP18 AP21 AP24 AP27 AP30 AP33

LA-6882P

1

0.2

of

26 63Wednesday, O ctober 06, 2010

of

26 63Wednesday, O ctober 06, 2010

of

1

26 63Wednesday, O ctober 06, 2010

CyberForum.ru

5

UV1B

CV108

DIS@ CV108

DIS@

CV114

DIS@ CV114

DIS@

1

CV109

2

DIS@ CV109

DIS@

0.1U_0402_10V7K

1

CV115

2

DIS@ CV115

DIS@

0.1U_0402_10V7K

FBA_D[0..63]

1

2

1U_0402_6.3V6K

+1.35VS_VGA

1

2

1U_0402_6.3V6K

200mA

CV110

DIS@ CV110

DIS@

10U_0603_6.3V6M

CV116

DIS@ CV116

DIS@

10U_0603_6.3V6M

FBA_D[0..63]<28,29>

D D

C C

30ohms (ESR=0.01) Bead

+1.05VS_VGA

BLM18PG330SN1D_0603

B B

+1.05VS_VGA

BLM18PG330SN1D_0603

Under GPU(below 150mils)

1 2

LV3

DIS@

1

2

0.1U_0402_10V7K

1 2

LV4

DIS@

1

2

0.1U_0402_10V7K

1

CV106

2

DIS@ CV106

DIS@

0.1U_0402_10V7K

1

CV112

2

DIS@ CV112

DIS@

0.1U_0402_10V7K

CV107

DIS@ CV107

DIS@

CV113

DIS@ CV113

DIS@

1

2

0.1U_0402_10V7K

1

2

0.1U_0402_10V7K

2

CV111

1

DIS@ CV111

DIS@

200mA

2

CV117

1

DIS@ CV117

DIS@

+FB_PLLAVDD_0

+FB_PLLAVDD_1

RV58 60.4_0402_1%RV58 60.4_0402_1%

RV59 10K_0402_5%

+FB_PLLAVDD_1

FBA_D0

L32

FBA_D1

N33

FBA_D2

L33

FBA_D3

N34

FBA_D4

N35

FBA_D5

P35

FBA_D6

P33

FBA_D7

P34

FBA_D8

K35

FBA_D9

K33

FBA_D10

K34

FBA_D11

H33

FBA_D12

G34

FBA_D13

G33

FBA_D14

E34

FBA_D15

E33

FBA_D16

G31

FBA_D17

F30

FBA_D18

G30

FBA_D19

G32

FBA_D20

K30

FBA_D21

K32

FBA_D22

H30

FBA_D23

K31

FBA_D24

L31

FBA_D25

L30

FBA_D26

M32

FBA_D27

N30

FBA_D28

M30

FBA_D29

P31

FBA_D30

R32

FBA_D31

R30

FBA_D32

AG30

FBA_D33

AG32

FBA_D34

AH31

FBA_D35

AF31

FBA_D36

AF30

FBA_D37

AE30

FBA_D38

AC32

FBA_D39

AD30

FBA_D40

AN33

FBA_D41

AL31

FBA_D42

AM33

FBA_D43

AL33

FBA_D44

AK30

FBA_D45

AK32

FBA_D46

AJ30

FBA_D47

AH30

FBA_D48

AH33

FBA_D49

AH35

FBA_D50

AH34

FBA_D51

AH32

FBA_D52

AJ33

FBA_D53

AL35

FBA_D54

AM34

FBA_D55

AM35

FBA_D56

AF33

FBA_D57

AE32

FBA_D58

AF34

FBA_D59

AE35

FBA_D60

AE34

FBA_D61

AE33

FBA_D62

AB32

FBA_D63

AC35

AG27

AF27

J19 J18

J27

12

T30

12

T29

@

FBx_PLLAVDD and FBx_DLLAVDD Combined

N12P-GT1-A1_BGA_973P DIS@

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FB_DLLAVDD_0 FB_PLLAVDD_0

FB_DLLAVDD_1 FB_PLLAVDD_1

FB_VREF_NC FBA_DEBUG0 FBA_DEBUG1

Part 2 of 7

4

MEMORY INTERFACE

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

FBA_DQM0

FBA_DQM1

FBA_DQM2

FBA_DQM3

FBA_DQM4

FBA_DQM5

FBA_DQM6

FBA_DQM7

FBA_DQS_RN0

A

FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FBA_WCK0

FBA_WCK0_N

FBA_WCK1

FBA_WCK1_N

FBA_WCK2

FBA_WCK2_N

FBA_WCK3

FBA_WCK3_N

FBA_CLK0_N

FBA_CLK1_N

FBA_CLK0

FBA_CLK1

U30 V30 U31 V32 T35 U33 W32 W33 W31 W34 U34 U35 U32 T34 T33 W30 AB30 AA30 AB31 AA32 AB33 Y32 Y33 AB34 AB35 Y35 W35 Y34 Y31 Y30 W29 Y29

P32 H34 J30 P30 AF32 AL32 AL34 AF35

L35 G35 H31 N32 AD32 AJ31 AJ35 AC34

L34 H35 J32 N31 AE31 AJ32 AJ34 AC33

P29 R29 L29 M29 AG29 AH29 AD29 AE29

T32 T31

AC31 AC30

FBA_CS#_L FBA_MA3_BA3_L FBA_MA2_BA0_L FBA_MA4_BA2_L FBA_MA5_BA1_L FBA_WE#_L FBA_MA7_MA8_L FBA_MA6_MA11_L FBA_ABI#_L FBA_MA12_RFU_L FBA_CKE_L FBA_MA1_MA9_L FBA_MA0_MA10_L FBA_RAS#_L FBA_CAS#_L FBA_RST# FBA_WE#_H FBA_MA5_BA1_H FBA_MA4_BA2_H FBA_MA2_BA0_H FBA_MA3_BA3_H FBA_CS#_H FBA_MA0_MA10_H FBA_MA1_MA9_H FBA_ABI#_H FBA_MA12_RFU_H FBA_CKE_H FBA_MA6_MA11_H FBA_MA7_MA8_H FBA_CAS#_H FBA_RAS#_H

FBA_DBI0# FBA_DBI1# FBA_DBI2# FBA_DBI3# FBA_DBI4# FBA_DBI5# FBA_DBI6# FBA_DBI7#

FBA_EDC0 FBA_EDC1 FBA_EDC2 FBA_EDC3 FBA_EDC4 FBA_EDC5 FBA_EDC6 FBA_EDC7

FBA_WCK0 FBA_WCK0_N FBA_WCK1 FBA_WCK1_N FBA_WCK2 FBA_WCK2_N FBA_WCK3 FBA_WCK3_N

FBA_CLK0 FBA_CLK0#

FBA_CLK1 FBA_CLK1#

3

FBA_CKE_L <28>

FBA_CKE_H <29>

DIS@

1 2

DIS@

1 2

DIS@

1 2

12

RV71

RV71 10K_0402_5%

10K_0402_5%

DIS@

FBC_D[0..63]

RV61 10K_0402_5%@R V61 10K_0402_5%@

12

RV72

RV72 10K_0402_5%

10K_0402_5%

DIS@

FBC_D0 FBC_D1 FBC_D2 FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7 FBC_D8

FBC_D9 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63

FBA_EDC[3..0] <28>

FBA_EDC[7..4] <29>

+1.35VS_VGA

FBA_RST# FBC_RST#

FBC_D[0..63]<30, 31>

12

RV209

RV209 10K_0402_5%

10K_0402_5%

DIS@

12

RV221

RV221 10K_0402_5%

10K_0402_5%

DIS@

RV55 40.2_0402_1%

RV56 40.2_0402_1%

RV57 60.4_0402_1%

+1.35VS_VGA

FBA_CS#_L <28> FBA_MA3_BA3_L <28> FBA_MA2_BA0_L <28> FBA_MA4_BA2_L <28> FBA_MA5_BA1_L <28> FBA_WE#_L <28> FBA_MA7_MA8_L <28> FBA_MA6_MA11_L <28> FBA_ABI#_L <28> FBA_MA12_RFU_L <28>

FBA_MA1_MA9_L <28> FBA_MA0_MA10_L <28> FBA_RAS#_L <28> FBA_CAS#_L <28> FBA_RST# <28,29> FBA_WE#_H <29> FBA_MA5_BA1_H <29> FBA_MA4_BA2_H <29> FBA_MA2_BA0_H <29> FBA_MA3_BA3_H <29> FBA_CS#_H <29> FBA_MA0_MA10_H <29> FBA_MA1_MA9_H <29> FBA_ABI#_H <29> FBA_MA12_RFU_H <29>

FBA_MA6_MA11_H <29> FBA_MA7_MA8_H <29> FBA_CAS#_H <29> FBA_RAS#_H <29> FBC_CAS#_H <31>

FBA_DBI0# <28> FBA_DBI1# <28> FBA_DBI2# <28> FBA_DBI3# <28> FBA_DBI4# <29> FBA_DBI5# <29> FBA_DBI6# <29> FBA_DBI7# <29>

FBA_WCK0 <28> FBA_WCK0_N <28> FBA_WCK1 <28> FBA_WCK1_N <28> FBA_WCK2 <29> FBA_WCK2_N <29>

FBA_WCK3_N <29>

FBA_CLK0 <28> FBA_CLK0# <28>

FBA_CLK1 <29> FBA_CLK1# <29>

UV1C

Part 3 of 7

MEMORY INTERFACE C

FBC_CMD0 FBC_CMD1 FBC_CMD2 FBC_CMD3 FBC_CMD4 FBC_CMD5 FBC_CMD6 FBC_CMD7 FBC_CMD8

FBC_CMD9 FBC_CMD10 FBC_CMD11 FBC_CMD12 FBC_CMD13 FBC_CMD14 FBC_CMD15 FBC_CMD16 FBC_CMD17 FBC_CMD18 FBC_CMD19 FBC_CMD20 FBC_CMD21 FBC_CMD22 FBC_CMD23 FBC_CMD24 FBC_CMD25 FBC_CMD26 FBC_CMD27 FBC_CMD28 FBC_CMD29 FBC_CMD30 FBC_CMD31

FBC_DQM0

FBC_DQM1

FBC_DQM2

FBC_DQM3

FBC_DQM4

FBC_DQM5

FBC_DQM6

FBC_DQM7

FBC_DQS_RN0 FBC_DQS_RN1 FBC_DQS_RN2 FBC_DQS_RN3 FBC_DQS_RN4 FBC_DQS_RN5 FBC_DQS_RN6 FBC_DQS_RN7

FBC_DQS_WP0 FBC_DQS_WP1 FBC_DQS_WP2 FBC_DQS_WP3 FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6 FBC_DQS_WP7

FBC_WCK0

FBC_WCK0_N

FBC_WCK1

FBC_WCK1_N

FBC_WCK2

FBC_WCK2_N

FBC_WCK3

FBC_WCK3_N

FBC_CLK0

FBC_CLK0_N

FBC_CLK1

FBC_CLK1_N

B13

FBC_D0

D13

FBC_D1

A13

FBC_D2

A14

FBC_D3

C16

FBC_D4

B16

FBC_D5

A17

FBC_D6

D16

FBC_D7

C13

FBC_D8

B11

FBC_D9

C11

FBC_D10

A11

FBC_D11

C10

FBC_D12

C8

FBC_D13

B8

FBC_D14

A8

FBC_D15

E8

FBC_D16

F8

FBC_D17

F10

FBC_D18

F9

FBC_D19

F12

FBC_D20

D8

FBC_D21

D11

FBC_D22

E11

FBC_D23

D12

FBC_D24

E13

FBC_D25

F13

FBC_D26

F14

FBC_D27

F15

FBC_D28

E16

FBC_D29

F16

FBC_D30

F17

FBC_D31

D29

FBC_D32

F27

FBC_D33

F28

FBC_D34

E28

FBC_D35

D26

FBC_D36

F25

FBC_D37

D24

FBC_D38

E25

FBC_D39

E32

FBC_D40

F32

FBC_D41

D33

FBC_D42

E31

FBC_D43

C33

FBC_D44

F29

FBC_D45

D30

FBC_D46

E29

FBC_D47

B29

FBC_D48

C31

FBC_D49

C29

FBC_D50

B31

FBC_D51

C32

FBC_D52

B32

FBC_D53

B35

FBC_D54

B34

FBC_D55

A29

FBC_D56

B28

FBC_D57

A28

FBC_D58

C28

FBC_D59

C26

FBC_D60

D25

FBC_D61

B25

FBC_D62

A25

FBC_D63

K27

FBCAL_PD_VDDQ

L27

FBCAL_PU_GND

M27

FBCAL_TERM_GND

RV6060.4_0402_1% DIS@ RV6060.4_0402_1% DIS@

12

G19

FBC_DEBUG0

12

G16

FBB_DEBUG1

N12P-GT1-A1_BGA_973P DIS@

F18 E19 D18 C17 F19 C19 B17 E20 B19 D20 A19 D19 C20 F20 B20 G21 F22 F24 F23 C25 C23 F21 E22 D21 A23 D22 B23 C22 B22 A22 A20 G20

A16 D10 F11 D15 D27 D34 A34 D28

B14 B10 D9 E14 F26 D31 A31 A26

C14 A10 E10 D14 E26 D32 A32 B26

G14 G15 G11 G12 G27 G28 G24 G25

E17 D17

D23 E23

2

FBC_CS#_L FBC_MA3_BA3_L FBC_MA2_BA0_L FBC_MA4_BA2_L FBC_MA5_BA1_L FBC_WE#_L FBC_MA7_MA8_L FBC_MA6_MA11_L FBC_ABI#_L FBC_MA12_RFU_L FBC_CKE_L FBC_MA1_MA9_L FBC_MA0_MA10_L FBC_RAS#_L FBC_CAS#_L FBC_RST# FBC_WE#_H FBC_MA5_BA1_H FBC_MA4_BA2_H FBC_MA2_BA0_H FBC_MA3_BA3_H FBC_CS#_H FBC_MA0_MA10_H FBC_MA1_MA9_H FBC_ABI#_H FBC_MA12_RFU_H FBC_CKE_H FBC_MA6_MA11_H FBC_MA7_MA8_H FBC_CAS#_H FBC_RAS#_H

FBC_DBI0# FBC_DBI1# FBC_DBI2# FBC_DBI3# FBC_DBI4# FBC_DBI5# FBC_DBI6# FBC_DBI7#

FBC_EDC0 FBC_EDC1 FBC_EDC2 FBC_EDC3 FBC_EDC4 FBC_EDC5 FBC_EDC6 FBC_EDC7

FBC_WCK0 FBC_WCK0_N FBC_WCK1 FBC_WCK1_N FBC_WCK2 FBC_WCK2_N FBC_WCK3 FBC_WCK3_N

FBC_CLK0 FBC_CLK0#

FBC_CLK1 FBC_CLK1#

FBC_DBI0# <30> FBC_DBI1# <30> FBC_DBI2# <30> FBC_DBI3# <30> FBC_DBI4# <31> FBC_DBI5# <31> FBC_DBI6# <31> FBC_DBI7# <31>

FBC_CLK0 <30> FBC_CLK0# <30>

FBC_CLK1 <31> FBC_CLK1# <31>

FBC_CS#_L <30> FBC_MA3_BA3_L <30> FBC_MA2_BA0_L <30> FBC_MA4_BA2_L <30> FBC_MA5_BA1_L <30> FBC_WE#_L <30> FBC_MA7_MA8_L <30> FBC_MA6_MA11_L <30> FBC_ABI#_L <30> FBC_MA12_RFU_L <30>

FBC_MA1_MA9_L <30> FBC_MA0_MA10_L <30> FBC_RAS#_L <30> FBC_CAS#_L <30> FBC_RST# <30,31> FBC_WE#_H <31> FBC_MA5_BA1_H <31> FBC_MA4_BA2_H <31> FBC_MA2_BA0_H <31> FBC_MA3_BA3_H <31> FBC_CS#_H <31> FBC_MA0_MA10_H <31> FBC_MA1_MA9_H <31> FBC_ABI#_H <31> FBC_MA12_RFU_H <31>

FBC_MA6_MA11_H <31> FBC_MA7_MA8_H <31>

FBC_RAS#_H <31>

FBC_EDC[3..0] <30>

FBC_EDC[7..4] <31>

FBC_WCK0 <30> FBC_WCK0_N <30> FBC_WCK1 <30> FBC_WCK1_N <30> FBC_WCK2 <31> FBC_WCK2_N <31>FBA_WCK3 <29> FBC_WCK3 <31> FBC_WCK3_N <31>

1

GDDR5 Mode G - Mirror Mode Mapping

FBC_CKE_L <30>

12

RV210

RV210 10K_0402_5%

10K_0402_5%

DIS@

12

RV222

RV222 10K_0402_5%

10K_0402_5%

DIS@

FBC_CKE_H <31>

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

0..31 32..63

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

CKE#

A1_A9

A0_A10

RAS#

CAS#

RST#

DATA Bus

RST#

WE#

A5_BA1

A4_BA2

A2_BA0

A3_BA3

CS#

A0_A10

A1_A9

ABI#

A12_RFU

CKE#

A6_A11

A7_A8

CAS#

RAS#

A A

Security Classification Compal Secret Data

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/07/09 2011/05/11

2

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

N12P-MEM Interface

LA-6882P

1

27 63W ednesday, October 06, 2010

of

0.2

CyberForum.ru

5

Memory Partition A - Lower 32 bits

FBA_EDC0

FBA_D[0..31]<27>

FBA_EDC[3..0]<27>

D D

Follow DG v02

FBA_CLK0

RV121

12

80.6_0402_1%DIS@

RV123

RV123 160_0402_1%

160_0402_1%

@

FBA_CLK0#

@

1 2

RV125

12

80.6_0402_1%DIS@

1

CV155

2

DIS@ CV155

DIS@

0.01U_0402_25V7K

549_0402_1%

RV212

1 2

931_0402_1%

DIS@

1.33K_0402_1%

13

D

DIS@

MEM_VREF<23,29,30,31>

2

G

QV9

S

2N7002W-T/R7_SOT323-3

13

D

DIS@

MEM_VREF<23,29,30,31>

2

G

S

2N7002W-T/R7_SOT323-3

+1.35VS_VGA

QV8

2

1

10U_0603_6.3V6M

C C

B B

A A

FBA_DBI0#<27>

FBA_DBI2#<27> FBA_DBI1#<27>

FBA_CLK0<27>

FBA_CLK0#<27>

FBA_CKE_L<27>

FBA_MA2_BA0_L<27> FBA_MA5_BA1_L<27> FBA_MA4_BA2_L<27> FBA_MA3_BA3_L<27>

FBA_MA7_MA8_L<27>

FBA_MA1_MA9_L<27> FBA_MA0_MA10_L<27> FBA_MA6_MA11_L<27> FBA_MA12_RFU_L<27>

RV119

121_0402_1%DIS@

FBA_ABI#_L<27>

FBA_RAS#_L<27>

FBA_CS#_L<27>

FBA_CAS#_L<27>

FBA_WE#_L<27>

FBA_WCK0_N<27> FBA_WCK0<27>

FBA_WCK1_N<27> FBA_WCK1<27>

FBA_RST#<27,29>

+1.35VS_VGA

12

RV127

DIS@

12

1

RV128

DIS@

2

0.01U_0402_25V7K

+1.35VS_VGA

RV129

549_0402_1%

DIS@

RV213

1 2

931_0402_1%

DIS@

RV130

1.33K_0402_1%

DIS@

UV3 SIDE

1

CV166

CV159

2

DIS@ CV166

DIS@

DIS@ CV159

DIS@

4.7U_0603_6.3V6K

FBA_EDC2

FBA_DBI0#

FBA_DBI2#

FBA_CLK0 FBA_CLK0#

FBA_CKE_L

FBA_MA2_BA0_L FBA_MA5_BA1_L FBA_MA4_BA2_L FBA_MA3_BA3_L

FBA_MA7_MA8_L

FBA_MA1_MA9_L FBA_MA0_MA10_L FBA_MA6_MA11_L

FBA_MA12_RFU_L

RV115

12

1K_0402_1%DIS@

RV117

12

1K_0402_1%DIS@

12

FBA_ABI#_L

FBA_RAS#_L

FBA_CS#_L

FBA_CAS#_L

FBA_WE#_L

FBA_WCK0_N FBA_WCK0

FBA_WCK1_N FBA_WCK1

+FBA_VREFD_L

+FBA_VREFC0

FBA_RST#

+FBA_VREFC0

16 mil

CV157

DIS@ CV157

DIS@

+1.35VS_VGA +1.35VS_VGA

12

+FBA_VREFD_L

12

1

CV158

2

DIS@ CV158

DIS@

0.01U_0402_25V7K

1

CV160

CV161

2

DIS@ CV160

DIS@

DIS@ CV161

DIS@

4.7U_0603_6.3V6K

UV3

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

1

CV288

2

1

2

170-BALL

DIS@ CV288

DIS@

SGRAM GDDR5

X76@

1

CV163

CV162

DIS@ CV162

DIS@

CV164

2

DIS@ CV163

DIS@

DIS@ CV164

DIS@

1U_0402_6.3V6K

CV165

DIS@ CV165

DIS@

4

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

H5GQ1H24AFR-T2L_BGA170

3

UV4

MF=0 MF=1 MF=0MF=1

FBA_D0

A4

FBA_D1

A2

FBA_D2

B4

FBA_D3

B2

FBA_D4

E4

FBA_D5

E2

FBA_D6

F4

FBA_D7

F2 A11 A13 B11 B13 E11 E13 F11 F13

FBA_D16

U11

FBA_D17

U13

FBA_D18

T11

FBA_D19

T13

FBA_D20

N11

FBA_D21

N13

FBA_D22

M11

FBA_D23

M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

+1.35VS_VGA

2

1

10U_0603_6.3V6M

CV174

DIS@ CV174

DIS@

BYTE0

BYTE2

UV4 SIDE

1

CV173

2

DIS@ CV173

DIS@

4.7U_0603_6.3V6K

FBA_DBI3#<27>

FBA_CLK0<27>

FBA_CLK0#<27>

FBA_CKE_L<27>

FBA_MA4_BA2_L<27> FBA_MA3_BA3_L<27> FBA_MA2_BA0_L<27> FBA_MA5_BA1_L<27>

FBA_MA0_MA10_L<27> FBA_MA6_MA11_L<27>

FBA_MA7_MA8_L<27> FBA_MA1_MA9_L<27>

FBA_MA12_RFU_L<27>

+1.35VS_VGA

RV120

121_0402_1%DIS@

FBA_ABI#_L<27>

FBA_CAS#_L<27>

FBA_WE#_L<27>

FBA_RAS#_L<27>

FBA_CS#_L<27>

FBA_WCK1_N<27> FBA_WCK1< 27>

FBA_WCK0_N<27> FBA_WCK0< 27>

FBA_RST#<27,29>

1

CV172

2

DIS@ CV172

DIS@

4.7U_0603_6.3V6K

1

CV171

DIS@ CV171

DIS@

CV169

CV170

2

DIS@ CV170

DIS@

DIS@ CV169

DIS@

4.7U_0603_6.3V6K

1U_0402_6.3V6K

12

1

CV168

2

DIS@ CV168

DIS@

FBA_CLK0 FBA_CLK0#

FBA_CKE_L

FBA_MA4_BA2_L FBA_MA3_BA3_L FBA_MA2_BA0_L FBA_MA5_BA1_L

FBA_MA0_MA10_L FBA_MA6_MA11_L

FBA_MA7_MA8_L FBA_MA1_MA9_L

FBA_MA12_RFU_L

RV116

12

1K_0402_1%DIS@

RV118

12

1K_0402_1%DIS@

FBA_ABI#_L

FBA_CAS#_L

FBA_WE#_L

FBA_RAS#_L

FBA_CS#_L

FBA_WCK1_N FBA_WCK1

FBA_WCK0_N FBA_WCK0

+FBA_VREFD_L

+FBA_VREFC0

FBA_RST#

1

CV167

2

DIS@ CV167

DIS@

1U_0402_6.3V6K

FBA_EDC3

FBA_EDC1

FBA_DBI3#

FBA_DBI1#

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

X76@

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

H5GQ1H24AFR-T2L_BGA170

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

2

FBA_D24

A4

FBA_D25

A2

FBA_D26

B4

FBA_D27

B2

FBA_D28

E4

FBA_D29

E2

FBA_D30

F4

FBA_D31

F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13

FBA_D10

T11

FBA_D11

T13

FBA_D12

N11

FBA_D13

N13

FBA_D14

M11

FBA_D15

M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

FBA_D8 FBA_D9

BYTE3

GDDR5

BYTE1

+1.35VS_VGA+1.35VS_VGA

Mode G - Mirror Mode Mapping

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

1

DATA Bus

0..31 32..63

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

CKE#

A1_A9

A0_A10

RAS#

CAS#

RST#

WE#

A5_BA1

A4_BA2

A2_BA0

A3_BA3

CS#

A0_A10

A1_A9

ABI#

A12_RFU

CKE#

A6_A11

A7_A8

CAS#

RAS#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TR ANSFERED FROM THE C USTODY OF THE COMPETEN T DIVISION OF R&D

AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TR ANSFERED FROM THE C USTODY OF THE COMPETEN T DIVISION OF R&D

AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TR ANSFERED FROM THE C USTODY OF THE COMPETEN T DIVISION OF R&D DEPARTMENT EXCEPT AS AUTH ORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SH EET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTH ORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SH EET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTH ORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SH EET NOR THE INFORM ATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PR IOR WRITTEN CO NSENT OF COMPAL ELEC TRONICS, INC.

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PR IOR WRITTEN CO NSENT OF COMPAL ELEC TRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PR IOR WRITTEN CO NSENT OF COMPAL ELEC TRONICS, INC.

Compal Secret Data

2010/07/09 2011/05/11

Compal Secret Data

2

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet of

N12P-VRAM A Lower

LA-6882P

1

28 63Wednesday, October 06, 2010

0.2

CyberForum.ru

5

Memory Partition A - Upper 32 bits

FBA_EDC4

C2

C13

FBA_EDC6

1K_0402_1%DIS@

FBA_RST#

CV289

DIS@ CV289

DIS@

CV185

DIS@ CV185

DIS@

FBA_DBI4#

FBA_DBI6#

12

1U_0402_6.3V6K

R13

R2

D2

D13

P13

P2

J12 J11

J3

H11

K10 K11

H10

K4 H5 H4

K5

J5

A5 U5

J1

J10 J13

J4 G3

G12

L3

L12

D5 D4

P5

P4

A10

U10

J14

J2

H1

K1

B5 G5

L5

T5

B10 D10 G10

L10

P10

T10 H14

K14

G1

L1

G4

L4 C5 R5

C10 R10 D11 G11

L11 P11

G14

L14

1

CV186

2

DIS@ CV186

DIS@

FBA_D[63..32]<27>

D D

FBA_EDC[7..4]<27>

Follow DG v02

FBA_CLK1

C C

FBA_CLK1#

MEM_VREF<23,28,30,31>

B B

MEM_VREF<23,28,30,31>

A A

RV139

RV139 160_0402_1%

160_0402_1%

@

1 2

+1.35VS_VGA

RV137

12

80.6_0402_1%DIS@

RV141

12

80.6_0402_1%DIS@

13

D

2

G

S

2N7002W-T/R7_SOT323-3

13

D

2

G

S

2N7002W-T/R7_SOT323-3

2

CV179

1

DIS@ CV179

DIS@

10U_0603_6.3V6M

1

2

0.01U_0402_25V7K

1 2

931_0402_1%

DIS@

QV10

DIS@

QV11

UV5 SIDE

1

CV180

2

DIS@ CV180

DIS@

4.7U_0603_6.3V6K

CV175

DIS@ CV175

DIS@

RV214

DIS@

RV215

1 2

931_0402_1%

DIS@

1

2

4.7U_0603_6.3V6K

549_0402_1%

1.33K_0402_1%

549_0402_1%

1.33K_0402_1%

1

CV181

2

DIS@ CV181

DIS@

4.7U_0603_6.3V6K

FBA_MA2_BA0_H<27> FBA_MA5_BA1_H<27> FBA_MA4_BA2_H<27> FBA_MA3_BA3_H<27>

FBA_MA7_MA8_H<27>

FBA_MA1_MA9_H<27> FBA_MA0_MA10_H<27> FBA_MA6_MA11_H<27>

FBA_MA12_RFU_H<27>

FBA_WCK2_N<27> FBA_WCK2< 27>

FBA_WCK3_N<27> FBA_WCK3< 27>

+1.35VS_VGA

RV143

DIS@

RV144

DIS@

+1.35VS_VGA

RV145

DIS@

RV146

DIS@

CV182

DIS@ CV182

DIS@

FBA_DBI4#<27>

FBA_DBI6#<27>

FBA_CLK1<27>

FBA_CLK1#<27>

FBA_CKE_H<27>

FBA_ABI#_H<27>

FBA_RAS#_H<27>

FBA_CS#_H<27>

FBA_CAS#_H<27>

FBA_WE#_H< 27>

FBA_RST#<27,28>

4.7U_0603_6.3V6K

FBA_CLK1

FBA_CLK1#

FBA_CKE_H

FBA_MA2_BA0_H FBA_MA5_BA1_H FBA_MA4_BA2_H FBA_MA3_BA3_H

FBA_MA7_MA8_H

FBA_MA1_MA9_H FBA_MA0_MA10_H FBA_MA6_MA11_H

FBA_MA12_RFU_H

RV131

RV133

RV135

12

121_0402_1%DIS@

FBA_ABI#_H

FBA_RAS#_H

FBA_CS#_H

FBA_CAS#_H

FBA_WE#_H

FBA_WCK2_N FBA_WCK2

FBA_WCK3_N FBA_WCK3

+FBA_VREFD_H

+FBA_VREFC1

12

+FBA_VREFC1

16 mil

12

1

CV177

+1.35VS_VGA

2

DIS@ CV177

DIS@

0.01U_0402_25V7K

12

+FBA_VREFD_H

12

1

CV178

2

DIS@ CV178

DIS@

0.01U_0402_25V7K

1

CV183

CV184

2

DIS@ CV183

DIS@

DIS@ CV184

DIS@

1U_0402_6.3V6K

4

UV5

MF=0 MF=1 MF=0MF=1

EDC0 EDC3 EDC1 EDC2 EDC2 EDC1 EDC3 EDC0

DBI0# DBI3# DBI1# DBI2# DBI2# DBI1# DBI3# DBI0#

CK CK# CKE#

BA0/A2 BA2/A4 BA1/A5 BA3/A3 BA2/A4 BA0/A2 BA3/A3 BA1/A5

A8/A7 A10/A0 A9/A1 A11/A6 A10/A0 A8/A7 A11/A6 A9/A1 A12/RFU/NC

VPP/NC VPP/NC

MF SEN ZQ

ABI# RAS# CAS# CS# WE# CAS# RAS# WE# CS#

WCK01# WCK23# WCK01 WCK23

WCK23# WCK01# WCK23 WCK01

VREFD VREFD VREFC

RESET#

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

170-BALL

SGRAM GDDR5

X76@

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

H5GQ1H24AFR-T2L_BGA170

3

UV6

MF=0 MF=1 MF=0MF=1

12

1

2

1U_0402_6.3V6K

FBA_CLK1

FBA_CLK1#

FBA_CKE_H

FBA_MA4_BA2_H FBA_MA3_BA3_H FBA_MA2_BA0_H FBA_MA5_BA1_H

FBA_MA0_MA10_H FBA_MA6_MA11_H

FBA_MA7_MA8_H FBA_MA1_MA9_H

FBA_MA12_RFU_H

RV132

12

1K_0402_1%DIS@

RV134

12

1K_0402_1%DIS@

FBA_ABI#_H

FBA_CAS#_H

FBA_WE#_H

FBA_RAS#_H

FBA_CS#_H

FBA_WCK3_N FBA_WCK3

FBA_WCK2_N FBA_WCK2

+FBA_VREFD_H

+FBA_VREFC1

FBA_RST#

+1.35VS_VGA

1

CV193

2

DIS@ CV193

DIS@

1U_0402_6.3V6K

FBA_EDC7

FBA_EDC5

FBA_DBI7#

FBA_DBI5#

CV194

DIS@ CV194

DIS@

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

X76@

H5GQ1H24AFR-T2L_BGA170

FBA_D32

A4

FBA_D33

A2

FBA_D34

B4

FBA_D35

B2

FBA_D36

E4

FBA_D37

E2

FBA_D38

F4

FBA_D39

F2 A11 A13 B11 B13 E11 E13 F11 F13

FBA_D48

U11

FBA_D49

U13

FBA_D50

T11

FBA_D51

T13

FBA_D52

N11

FBA_D53

N13

FBA_D54

M11

FBA_D55

M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

+1.35VS_VGA

2

1

10U_0603_6.3V6M

CV187

DIS@ CV187

DIS@

BYTE4

BYTE6

UV6 SIDE

1

CV188

2

DIS@ CV188

DIS@

4.7U_0603_6.3V6K

FBA_DBI7#<27>

FBA_DBI5#<27>

FBA_CLK1<27>

FBA_CLK1#<27>

FBA_CKE_H<27>

FBA_MA4_BA2_H<27> FBA_MA3_BA3_H<27> FBA_MA2_BA0_H<27> FBA_MA5_BA1_H<27>

FBA_MA0_MA10_H<27> FBA_MA6_MA11_H<27>

FBA_MA7_MA8_H<27> FBA_MA1_MA9_H<27>

FBA_MA12_RFU_H<27>

+1.35VS_VGA

RV136

121_0402_1%DIS@

FBA_ABI#_H<27>

FBA_CAS#_H<27>

FBA_WE#_H< 27>

FBA_RAS#_H<27>

FBA_CS#_H<27>

FBA_WCK3_N<27> FBA_WCK3< 27>

FBA_WCK2_N<27> FBA_WCK2< 27>

FBA_RST#<27,28>

1

CV190

CV189

2

DIS@ CV190

DIS@

DIS@ CV189

DIS@

4.7U_0603_6.3V6K

CV192

CV191

2

DIS@ CV192

DIS@

DIS@ CV191

DIS@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K 1U_0402_6.3V6K

1U_0402_6.3V6K

2

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

1

FBA_D56

A4

FBA_D57

A2

FBA_D58

B4

FBA_D59

B2

FBA_D60

E4

FBA_D61

E2

FBA_D62

F4

FBA_D63

F2 A11 A13 B11 B13 E11 E13 F11 F13

FBA_D40

U11

FBA_D41

U13

FBA_D42

T11

FBA_D43

T13

FBA_D44

N11

FBA_D45

N13

FBA_D46

M11

FBA_D47

M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

+1.35VS_VGA

BYTE7

BYTE5

GDDR5 Mode G - Mirror Mode Mapping

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

DATA Bus

0..31 32..63

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

CKE#

A1_A9

A0_A10

RAS#

CAS#

RST#

WE#

A5_BA1

A4_BA2

A2_BA0

A3_BA3

CS#

A0_A10

A1_A9

ABI#

A12_RFU

CKE#

A6_A11

A7_A8

CAS#

RAS#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TR ANSFERED FROM THE C USTODY OF THE COMPETEN T DIVISION OF R&D

AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TR ANSFERED FROM THE C USTODY OF THE COMPETEN T DIVISION OF R&D

AND TRADE SECRET IN FORMATION. THIS SHEET MAY NOT BE TR ANSFERED FROM THE C USTODY OF THE COMPETEN T DIVISION OF R&D DEPARTMENT EXCEPT AS AUTH ORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SH EET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTH ORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SH EET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTH ORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SH EET NOR THE INFORM ATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PR IOR WRITTEN CO NSENT OF COMPAL ELEC TRONICS, INC.

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PR IOR WRITTEN CO NSENT OF COMPAL ELEC TRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PR IOR WRITTEN CO NSENT OF COMPAL ELEC TRONICS, INC.

Compal Secret Data

2010/07/09 2011/05/11

Compal Secret Data

2

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet of

N12P-VRAM A Upper

LA-6882P

1

29 63Wednesday, October 06, 2010

0.2

CyberForum.ru

5

4

3

2

1

Memory Partition C - Lower 32 bits

UV8

UV7

MF=0 MF=1 MF=0MF=1

FBC_EDC0

C2

EDC0 EDC3

C13

CV206

DIS@ CV206

DIS@

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# W CK23#

D4

WCK01 W CK23

P5

WCK23# W CK01#

P4

WCK23 W CK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

X76@

FBC_MA2_BA0_L FBC_MA5_BA1_L FBC_MA4_BA2_L FBC_MA3_BA3_L

FBC_MA7_MA8_L

FBC_MA1_MA9_L FBC_MA0_MA10_L FBC_MA6_MA11_L

FBC_MA12_RFU_L

+FBC_VREFC0

1

CV197

2

DIS@ CV197

DIS@

+FBC_VREFD_L

1

CV198

2

DIS@ CV198

DIS@

1

2

1U_0402_6.3V6K

FBC_EDC2

FBC_DBI0#

FBC_DBI2#

FBC_CLK0 FBC_CLK0#

FBC_CKE_L

RV147

12

1K_0402_1%DIS@

RV149

12

1K_0402_1%DIS@

FBC_ABI#_L

FBC_RAS#_L

FBC_CS#_L

FBC_CAS#_L

FBC_WE#_L

FBC_WCK0_N FBC_WCK0

FBC_WCK1_N FBC_WCK1

+FBC_VREFD_L

+FBC_VREFC0

FBC_RST#

+1.35VS_VGA

1

CV290

2

DIS@ CV290

DIS@

0.01U_0402_25V7K

1

CV205

2

DIS@ CV205

DIS@

1U_0402_6.3V6K

FBC_D[0..31]<27>

D D

C C

B B

A A

FBC_EDC[3..0]<27>

Follow DG v02

FBC_CLK0

1 2

FBC_CLK0#

MEM_VREF<23,28,29,31>

+1.35VS_VGA

10U_0603_6.3V6M

RV153

80.6_0402_1%DIS@

RV155

RV155 160_0402_1%

160_0402_1%

@

RV157

80.6_0402_1%DIS@

2

CV199

1

DIS@ CV199

DIS@

12

0.01U_0402_25V7K

13

D

2

G

S

2N7002W-T/R7_SOT323-3

13

D

2

G

S

2N7002W-T/R7_SOT323-3

UV7 SIDE

1

CV200

2

DIS@ CV200

DIS@

4.7U_0603_6.3V6K

1

CV195

2

DIS@ CV195

DIS@

1 2

DIS@

QV12

1 2

931_0402_1%

DIS@

QV13

1

2

4.7U_0603_6.3V6K

RV216

931_0402_1%

DIS@

RV217

DIS@

1

CV201

2

DIS@ CV201

DIS@

4.7U_0603_6.3V6K

FBC_CLK0#<27>

FBC_MA2_BA0_L<27> FBC_MA5_BA1_L<27> FBC_MA4_BA2_L<27> FBC_MA3_BA3_L<27>

FBC_MA7_MA8_L<27>

FBC_MA1_MA9_L<27> FBC_MA0_MA10_L<27> FBC_MA6_MA11_L<27>

FBC_MA12_RFU_L<27>

FBC_RAS#_L<27>

FBC_CAS#_L<27>

FBC_WCK0_N<27> FBC_WCK0<27>

FBC_WCK1_N<27> FBC_WCK1<27>

RV159

549_0402_1%

DIS@

RV160

1.33K_0402_1%

DIS@

+1.35VS_VGA

RV161

549_0402_1%

DIS@

RV162

1.33K_0402_1%

DIS@

1

CV202

2

DIS@ CV202

DIS@

4.7U_0603_6.3V6K

FBC_CLK0<27>

FBC_CKE_L<27>

RV151

FBC_ABI#_L<27>

FBC_CS#_L<27>

FBC_WE#_L<27>

FBC_RST#<27,31>

+1.35VS_VGA

12

CV203

DIS@ CV203

DIS@

121_0402_1%DIS@

12

1

2

1U_0402_6.3V6K

FBC_DBI0#<27>

FBC_DBI2#<27>

12

0.01U_0402_25V7K

CV204

DIS@ CV204

DIS@

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

H5GQ1H24AFR-T2L_BGA170

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

FBC_D0

A4

FBC_D1

A2

FBC_D2

B4

FBC_D3

B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

FBC_D4 FBC_D5 FBC_D6 FBC_D7

FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23

+1.35VS_VGA

BYTE0

BYTE2

+1.35VS_VGA

2

1

10U_0603_6.3V6M

CV207

DIS@ CV207

DIS@

4.7U_0603_6.3V6K

UV8 SIDE

1

CV208

2

DIS@ CV208

DIS@

FBC_DBI3#<27>

FBC_DBI1#<27>

FBC_CLK0<27>

FBC_CLK0#<27>

FBC_CKE_L<27>

FBC_MA4_BA2_L<27> FBC_MA3_BA3_L<27> FBC_MA2_BA0_L<27> FBC_MA5_BA1_L<27>

FBC_MA0_MA10_L<27> FBC_MA6_MA11_L<27>

FBC_MA7_MA8_L<27> FBC_MA1_MA9_L<27>

FBC_MA12_RFU_L<27>

+1.35VS_VGA

RV152

12

121_0402_1%DIS@

FBC_ABI#_L<27>

FBC_CAS#_L<27>

FBC_WE#_L<27>

FBC_RAS#_L<27>

FBC_CS#_L<27>

FBC_WCK1_N<27> FBC_WCK1<27>

FBC_WCK0_N<27> FBC_WCK0<27>

FBC_RST#<27,31>

1

2

4.7U_0603_6.3V6K

1

CV210

CV209

DIS@ CV209

DIS@

CV211

2

DIS@ CV210

DIS@

DIS@ CV211

DIS@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K 1U_0402_6.3V6K

1U_0402_6.3V6K

1

CV212

2

DIS@ CV212

DIS@

FBC_EDC3

FBC_EDC1

FBC_DBI3#

FBC_DBI1#

FBC_CLK0 FBC_CLK0#

FBC_CKE_L

FBC_MA4_BA2_L FBC_MA3_BA3_L FBC_MA2_BA0_L FBC_MA5_BA1_L

FBC_MA0_MA10_L FBC_MA6_MA11_L

FBC_MA7_MA8_L FBC_MA1_MA9_L

FBC_MA12_RFU_L

RV148

12

1K_0402_1%DIS@

RV150

12

1K_0402_1%DIS@

FBC_ABI#_L

FBC_CAS#_L

FBC_WE#_L

FBC_RAS#_L

FBC_CS#_L

FBC_WCK1_N FBC_WCK1

FBC_WCK0_N FBC_WCK0

+FBC_VREFD_L

+FBC_VREFC0

FBC_RST#

+1.35VS_VGA

1

CV213

2

DIS@ CV213

DIS@

1U_0402_6.3V6K

UV8

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# W CK23#

D4

WCK01 W CK23

P5

WCK23# W CK01#

P4

WCK23 W CK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

X76@

1

CV214

2

DIS@ CV214

DIS@

1U_0402_6.3V6K

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14

DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

H5GQ1H24AFR-T2L_BGA170

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

FBC_D24

A4

FBC_D25

A2

FBC_D26

B4

FBC_D27

B2

FBC_D28

E4

FBC_D29

E2

FBC_D30

F4

FBC_D31

F2 A11 A13 B11 B13 E11 E13 F11 F13

FBC_D8

U11

FBC_D9

U13

FBC_D10

T11

FBC_D11

T13

FBC_D12

N11

FBC_D13

N13

FBC_D14

M11

FBC_D15

M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

+1.35VS_VGA

BYTE3

GDDR5 Mode G - Mirror Mode Mapping

BYTE1

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

DATA Bus

0..31 32..63

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

CKE#

A1_A9

A0_A10

RAS#

CAS#

RST#

WE#

A5_BA1

A4_BA2

A2_BA0

A3_BA3

CS#

A0_A10

A1_A9

ABI#

A12_RFU

CKE#

A6_A11

A7_A8

CAS#

RAS#

Security Classification Compal Secret Data

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/07/09 2011/05/11

2

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

N12P-VRAM C Lower

LA-6882P

1

30 63W ednesday, October 06, 2010

of

0.2

CyberForum.ru

5

4

3

2

1

Memory Partition C - Upper 32 bits

UV9

MF=0 MF=1 MF=0MF=1

FBC_EDC4

C2

EDC0 EDC3

C13

CV248

DIS@ CV248

DIS@

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# W CK23#

D4

WCK01 W CK23

P5

WCK23# W CK01#

P4

WCK23 W CK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

X76@

FBC_CLK1

FBC_CLK1#

FBC_MA0_MA10_H FBC_MA6_MA11_H

FBC_MA12_RFU_H

1

CV291

2

DIS@ CV291

DIS@

0.01U_0402_25V7K

1

CV247

2

DIS@ CV247

DIS@

1U_0402_6.3V6K

FBC_EDC6

FBC_DBI4#

FBC_DBI6#

FBC_CKE_H

FBC_MA2_BA0_H FBC_MA5_BA1_H FBC_MA4_BA2_H FBC_MA3_BA3_H

FBC_MA7_MA8_H FBC_MA1_MA9_H

RV163

12

1K_0402_1%DIS@

RV165

12

1K_0402_1%DIS@

FBC_ABI#_H

FBC_RAS#_H

FBC_CS#_H

FBC_CAS#_H

FBC_WE#_H

FBC_WCK2_N FBC_WCK2

FBC_WCK3_N FBC_WCK3

+FBC_VREFD_H

+FBC_VREFC1

FBC_RST#

+1.35VS_VGA

1

CV246

2

DIS@ CV246

DIS@

1U_0402_6.3V6K

FBC_D[63..32]<27>

D D

FBC_EDC[7..4]<27>

Follow DG v02

FBC_CLK1

C C

FBC_CLK1#

MEM_VREF<23,28,29,30>

B B

MEM_VREF<23,28,29,30>

A A

RV171

RV171 160_0402_1%

160_0402_1%

@

1 2

2

G

2

G

+1.35VS_VGA

2

1

10U_0603_6.3V6M

RV169

12

80.6_0402_1%DIS@

RV173

12

80.6_0402_1%DIS@

1 2

931_0402_1%

13

D

DIS@

QV14

S

2N7002W-T/R7_SOT323-3

1 2

931_0402_1%

13

D

DIS@

QV15

S

2N7002W-T/R7_SOT323-3

UV9 SIDE

1

CV245

CV244

2

DIS@ CV245

DIS@

DIS@ CV244

DIS@

4.7U_0603_6.3V6K

1

2

0.01U_0402_25V7K

RV218

DIS@

RV219

DIS@

4.7U_0603_6.3V6K

CV215

DIS@ CV215

DIS@

549_0402_1%

1.33K_0402_1%

549_0402_1%

1.33K_0402_1%

1

CV249

2

DIS@ CV249

DIS@

4.7U_0603_6.3V6K

+1.35VS_VGA

RV175

DIS@

RV176

DIS@

+1.35VS_VGA

RV177

DIS@

RV178

DIS@

1

CV243

2

DIS@ CV243

DIS@

FBC_DBI4#<27>

FBC_DBI6#<27>

FBC_CLK1<27>

FBC_CLK1#<27>

FBC_CKE_H<27>

FBC_MA2_BA0_H<27> FBC_MA5_BA1_H<27> FBC_MA4_BA2_H<27> FBC_MA3_BA3_H<27>

FBC_MA7_MA8_H<27>

FBC_MA1_MA9_H<27> FBC_MA0_MA10_H<27> FBC_MA6_MA11_H<27>

FBC_MA12_RFU_H<27>

RV167

12

121_0402_1%DIS@

FBC_ABI#_H<27>

FBC_RAS#_H<27>

FBC_CS#_H<27>

FBC_CAS#_H<27>

FBC_WE#_H<27>

FBC_WCK2_N<27> FBC_WCK2<27>

FBC_WCK3_N<27> FBC_WCK3<27>

FBC_RST#<27,30>

12

+FBC_VREFC1

12

1

CV217

2

DIS@ CV217

DIS@

0.01U_0402_25V7K

12

+FBC_VREFD_H

12

1

CV218

2

DIS@ CV218

DIS@

0.01U_0402_25V7K

1

CV240

2

DIS@ CV240

DIS@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K 1U_0402_6.3V6K

1U_0402_6.3V6K

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

H5GQ1H24AFR-T2L_BGA170

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

FBC_D32

A4

FBC_D33

A2

FBC_D34

B4

FBC_D35

B2

FBC_D36

E4

FBC_D37

E2

FBC_D38

F4

FBC_D39

F2 A11 A13 B11 B13 E11 E13 F11 F13

FBC_D48

U11

FBC_D49

U13

FBC_D50

T11

FBC_D51

T13

FBC_D52

N11

FBC_D53

N13

FBC_D54

M11

FBC_D55

M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

+1.35VS_VGA

10U_0603_6.3V6M

2

1

BYTE4

BYTE6

UV10 SIDE

CV227

DIS@ CV227

DIS@

4.7U_0603_6.3V6K

FBC_DBI7#<27>

FBC_DBI5#<27>

FBC_CLK1<27>

FBC_CLK1#<27>

FBC_CKE_H<27>

FBC_MA4_BA2_H<27> FBC_MA3_BA3_H<27> FBC_MA2_BA0_H<27> FBC_MA5_BA1_H<27>

FBC_MA0_MA10_H<27> FBC_MA6_MA11_H<27>

FBC_MA7_MA8_H<27> FBC_MA1_MA9_H<27>

FBC_MA12_RFU_H<27>

+1.35VS_VGA

RV168

12

121_0402_1%DIS@

FBC_ABI#_H<27>

FBC_CAS#_H<27>

FBC_WE#_H<27>

FBC_RAS#_H<27>

FBC_CS#_H<27>

FBC_WCK3_N<27> FBC_WCK3<27>

FBC_WCK2_N<27> FBC_WCK2<27>

FBC_RST#<27,30>

1

2

1

CV228

CV229

2

DIS@ CV228

DIS@

DIS@ CV229

DIS@

4.7U_0603_6.3V6K

CV231

CV230

2

DIS@ CV231

DIS@

DIS@ CV230

DIS@

4.7U_0603_6.3V6K

FBC_CLK1

FBC_CLK1#

FBC_MA0_MA10_H FBC_MA6_MA11_H

FBC_MA12_RFU_H

1

CV232

2

DIS@ CV232

DIS@

1U_0402_6.3V6K

FBC_EDC7

FBC_EDC5

FBC_DBI7#

FBC_DBI5#

FBC_CKE_H

FBC_MA4_BA2_H FBC_MA3_BA3_H FBC_MA2_BA0_H FBC_MA5_BA1_H

FBC_MA7_MA8_H FBC_MA1_MA9_H

RV164

12

1K_0402_1%DIS@

RV166

12

1K_0402_1%DIS@

FBC_ABI#_H

FBC_CAS#_H

FBC_WE#_H

FBC_RAS#_H

FBC_CS#_H

FBC_WCK3_N FBC_WCK3

FBC_WCK2_N FBC_WCK2

+FBC_VREFD_H

+FBC_VREFC1

FBC_RST#

+1.35VS_VGA

1

CV233

2

DIS@ CV233

DIS@

1U_0402_6.3V6K

1

2

UV10

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# W CK23#

D4

WCK01 W CK23

P5

WCK23# W CK01#

P4

WCK23 W CK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

X76@

CV234

DIS@ CV234

DIS@

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

H5GQ1H24AFR-T2L_BGA170

FBC_D56

A4

FBC_D57

A2

FBC_D58

B4

FBC_D59

B2

FBC_D60

E4

FBC_D61

E2

FBC_D62

F4

FBC_D63

F2 A11 A13 B11 B13 E11 E13 F11 F13

FBC_D40

U11

FBC_D41

U13

FBC_D42

T11

FBC_D43

T13

FBC_D44

N11

FBC_D45

N13

FBC_D46

M11

FBC_D47

M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

+1.35VS_VGA

BYTE7

GDDR5 Mode G - Mirror Mode Mapping

DATA Bus

0..31 32..63

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

CKE#

A1_A9

A0_A10

RAS#

CAS#

RST#

BYTE5

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

RST#

WE#

A5_BA1

A4_BA2

A2_BA0

A3_BA3

CS#

A0_A10

A1_A9

ABI#

A12_RFU

CKE#

A6_A11

A7_A8

CAS#

RAS#

Security Classification Compal Secret Data

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/07/09 2011/05/11

2

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

N12P-VRAM C Upper

LA-6882P

1

31 63W ednesday, October 06, 2010

of

0.2

CyberForum.ru

5

RV92

45.3K_0402_1%

DIS@

D D

STRAP0<24> STRAP1<24> STRAP2<24>

STRAP0 STRAP1 STRAP2

DIS@

1 2

RV95

@RV95

@

45.3K_0402_1%

1 2

RV93

34.8K_0402_1%

@

1 2

DIS@

RV96

34.8K_0402_1%

1 2

+3VS_VGA

1 2

RV97

4.99K_0402_1%

1 2

+3VS_VGA

4

RV94

RV94 20K_0402_1%

20K_0402_1%

DIS@

@

ZZZ

Hynix

H1G@

X7625938L01

ZZZ

Samsung

S1G@

S1G@ X7625938L02

X7625938L02

ZZZ

Samsung

S2G@

S2G@ X7625938L03

X7625938L03

3

Physical Strapping pin

ROM_SO FB_0_BAR_SIZE

ROM_SCLK

ROM_SI

STRAP2

STRAP1

STRAP0

Resistor Values

Power Rail

+3VS_VGA

Pull-up to +3VS_VGA

5K

10K

15K

20K

25K

30K

35K

45K

Logical Strapping Bit3

XCLK_417

PCI_DEVID[4]

PCI_DEVID[3]

3GIO_PAD_CFG_ADR[3]

USER[3]

1000

1001

1010

1011

1100

1101

1110

1111

2

3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]

Pull-down to Gnd

0000

0001

0010

0011

0100

0101

0110

0111

Logical Strapping Bit2

SUB_VENDOR

Logical Strapping Bit1

SLOT_CLK_CFG

RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]

1

Logical Strapping Bit0

VGA_DEVICESMB_ALT_ADDR

PEX_PLL_EN_TERM

RAM_CFG[0]

PCI_DEVID[0]PCI_DEVID[1]PCI_DEVID[2]

USER[0]USER[1]USER[2]

C C

ROM_SI<24>

ROM_SO<24>

ROM_SCLK<24>

ROM_SI ROM_SO ROM_SCLK

X76

B B

A A

RV98

4.99K_0402_1%

@

1 2

RV101

RV101 20K_0402_1%

20K_0402_1%

X76@

1 2

FB Memory (GDDR5)

Samsung 1800MHz (defaul)

Hynix 1600MHz

RV99

4.99K_0402_1%

@

1 2

RV102

RV102 10K_0402_1%

10K_0402_1%

DIS@

1 2

K4G10325FE-HC04

H5GQ1H24AFR-T2L

RV100

RV100 15K_0402_1%

15K_0402_1%

@

1 2

RV103

RV103 15K_0402_1%

15K_0402_1%

DIS@

1 2

ROM_SO

PD 10K

PD 15K

SUB_VENDOR

0

No VBIOS ROM

1

BIOS ROM is present (Default)

FB_0_BAR_SIZE

0

256MB (Default)

1

Reserved

XCLK_417

0

277MHz (Default)

1

Reserved

USER Straps

User[3:0]

1000-1100

Customer defined

ROM_SIROM_SCLK STRAP0STRAP1STRAP2GPU

3GIO_PADCFG

PU 20K

PD 15K32Mx32

PU 20K

PD 35KN12P-GT1

PD 35K

PU 45KPD 10K PD 20K32Mx32

PU 45K

X76

3GIO_PADCFG[3:0]

0110

Notebook Default

SLOT_CLK_CFG

0

GPU and MCH don't share a common reference clock

1

GPU and MCH share a common reference clock (Default)

SMBUS_ALT_ADDR

0

0x9E (Default)

1

0x9C (Multi-GPU usage)

PEX_PLL_EN_TERM

0

Disable (Default)

1

Enable

VGA_DEVICE

0

3D Device (Class Code 302h)

1

VGA Device (Default)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/07/09 2011/05/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

N12P_MISC

LA-6882P

32 63Wednesday, October 06, 2010

of

1

of

0.2

CyberForum.ru

5

4

3

2

1

TOP side (under inductor)

RV180

CPU_VIN+<60>

D D

C C

Link to Rsense, PWR side

CPU_VIN-<60>

1 2

RV179 0_0402_5%

VENTURA@

0_0402_5%

2

@

CV235

0.1U_0402_16V4Z

1

RV183

+3VS_VGA

RV186

0_0402_5%

@

RV190

GPU_VIN+<59>

Link to Rsense, PWR side

GPU_VIN-<59>

0_0402_5%

@

RV198

@

RV202

+3VS

RV199

0_0402_5%

VENTURA@

1 2

GPU_A1

GPU_A0

RV203

0_0402_5%

1 2

@

B B

1 2

VENTURA@

1 2

VENTURA@

1 2

RV189

10_0402_1%

2

VENTURA@

CV236

0.1U_0402_16V4Z

1

10_0402_1%

+3VS

RV187

0_0402_5%@

1 2

V_A0 I2C_DATA_R

V_A1

RV191

@

0_0402_5%

1 2

VENTURA@

1 2

RV195

0_0402_5%

I2C_DATA

12

0_0402_5%VENTUR A@

1 2 3 4

RV188

RV196

1 2

1

CV237

0.1U_0402_16V4Z

2

@

RV197 10_0402_1%

1 2

UV12

VIN+ VINGND VS

INA219AIDCNRG4_SOT23-8

VENTURA@

12

0_0402_5%VENTUR A@

VENTURA@

8

A1

7

A0

6

SDA

5

SCL

For CPU Ventura slave address : 1000010 please placemnet near R-sense

10_0402_1%

2

1

+3VS

Ventura for GPU SIDE Slave Address 1000110 Placement near Rsense

V_A1

V_A0 I2C_DATA_R I2C_CLK_R

RV185

VENTURA@

CV238

0.1U_0402_16V4Z

VENTURA@

RV184 0_0402_5%

12 12

0_0402_5%

VENTURA@RV185

VENTURA@

UV13

1

VIN+

2

VIN-

3

GND

4

VS

INA219AIDCNRG4_SOT23-8

VENTURA@

SDA

I2C_DATA I2C_CLK

+3VS

12

RV194

RV193

2.2K_0402_5%

I2C_DATA

GPU_A1

8

A1

GPU_A0

7

A0

I2C_DATA

6

I2C_CLK

5

SCL

VENTURA@

2N7002E-T1-GE3_SOT23-3

2

1 3

D

QV3

VENTURA@

G

+3VS_VGA

S

1 3

D

I2CB_SDA

2

G

I2CB_SCLI2C_CLK

S

QV4

I2CB_SDA <23>

Link to GPU

I2CB_SCL <23>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INF ORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INF ORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INF ORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRON ICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CON TAINS

DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRON ICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CON TAINS

DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRON ICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CON TAINS MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WIT HOUT PRIOR WRIT TEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WIT HOUT PRIOR WRIT TEN CONSENT OF CO MPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WIT HOUT PRIOR WRIT TEN CONSENT OF CO MPAL ELECTRONICS, INC.

3

2010/07/09 2011/05/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

VENTURA Interface

LA-6882P

1

33 63W ednesday, October 06, 2010

0.2

of

CyberForum.ru

5

INVPWM

DISPOFF#

C525

@

1

2

470P_0402_50V7K

D D

@

1

C527

2

470P_0402_50V7K

For EMI

LCD POWER CIRCUIT

+LCDVDD

13

D

Q67

2N7002_SOT23

R1193 0_0402_5%

PCH_PWM<17>

LVDS_A0<17> LVDS_A0#<17>

LVDS_A1<17> LVDS_A1#<17>

LVDS_A2<17> LVDS_A2#<17>

LVDS_ACLK<17> LVDS_ACLK#<17>

LVDS_BCLK<17> LVDS_BCLK#<17>

LVDS_B0<17> LVDS_B0#<17>

LVDS_B1<17> LVDS_B1#<17>

LVDS_B2<17> LVDS_B2#<17>

R1193 0_0402_5%

R1194 0_0402_5%

PCH_ENVDD<17>

VGA_ENVDD<23>

C C

B B

A A

S

1 2

UMA@

1 2

DIS_ONLY@

R821

100K_0402_5%

R1195 0_0402_5%

1 2

UMA@

LVDS_A0 LVDS_A0#

LVDS_A1 LVDS_A1#

LVDS_A2 LVDS_A2#

LVDS_ACLK LVDS_ACLK#

LVDS_BCLK LVDS_BCLK#

LVDS_B0 LVDS_B0#

LVDS_B1 LVDS_B1#

LVDS_B2 LVDS_B2#

5

+5VALW

12

R817

R816

R816 150_0603_1%

150_0603_1%

2

G

12

R1243 0_0402_5%

R1243 0_0402_5% R1245 0_0402_5%

R1245 0_0402_5%

R1247 0_0402_5%

R1247 0_0402_5% R1249 0_0402_5%

R1249 0_0402_5%

R1251 0_0402_5%

R1251 0_0402_5% R1253 0_0402_5%

R1253 0_0402_5%

R1255 0_0402_5%

R1255 0_0402_5% R1257 0_0402_5%

R1257 0_0402_5%

R1259 0_0402_5%

R1259 0_0402_5% R1261 0_0402_5%

R1261 0_0402_5%

R1262 0_0402_5%

R1262 0_0402_5% R1265 0_0402_5%

R1265 0_0402_5%

R1267 0_0402_5%

R1267 0_0402_5% R1269 0_0402_5%

R1269 0_0402_5%

R817 100K_0402_5%

100K_0402_5%

1 2

1

DTC124EK

OUT

2

IN

GND

Q69

DTC124EKAT146_SC59-3

3

@R821

@

G

2

13

D

S

D

S

2N7002_SOT23

Q70

@

R1239 0_0402_5%

1 2

R1241 0_0402_5%

1 2

UMA@

UMA@ UMA@

UMA@ 1 2 1 2

UMA@

UMA@ UMA@

UMA@ 1 2 1 2

UMA@

UMA@ 1 2 1 2

UMA@

UMA@ 1 2 1 2

UMA@

UMA@ 1 2 1 2

UMA@

UMA@ 1 2 1 2

UMA@

1 2 1 2

UMA@

R820 220K_0402_5%R820 220K_0402_5%

1

C530

0.1U_0402_16V4Z

2

+3VS

@

5

1

P

NC

A2Y

G

NC7SZ14P5X_NL_SC70-5

3

UMA@

R824

1 2

0_0402_5%

INVPWM

10K_0402_5% @

+3VS

S

G

2

D

1 3

+LCDVDD

FBMA-L11-201209-221LM A30T_0805

U23

PCH_PWM_R

4

R826

12

VGA_TXOUT0+<24> VGA_TXOUT0-<24>

VGA_TXOUT1+<24> VGA_TXOUT1-<24>

VGA_TXOUT2+<24>

VGA_TXOUT2-<24>

VGA_TXCLK+<24>

VGA_TXCLK-<24>

VGA_TZCLK+<24>

VGA_TZCLK-<24>

VGA_TZOUT0+<24>

VGA_TZOUT0-<24>

VGA_TZOUT1+<24>

VGA_TZOUT1-<24>

VGA_TZOUT2+<24>

VGA_TZOUT2-<24>

4

W=60mils

1

C529

4.7U_0805_10V4Z

2

AO3413_SOT23-3

AO3413_SOT23-3 Q68

Q68

L15

1 2

4.7U_0805_10V4Z

UMA@

R823

1 2

0_0402_5%

For GMCH DPST

VGA_TXOUT0+ VGA_TXOUT0-

VGA_TXOUT1+ VGA_TXOUT1-

VGA_TXOUT2+ VGA_TXOUT2-

VGA_TXCLK+ VGA_TXCLK-

VGA_TZCLK+ VGA_TZCLK-

VGA_TZOUT0+ VGA_TZOUT0-

VGA_TZOUT1+ VGA_TZOUT1-

VGA_TZOUT2+ VGA_TZOUT2-

4

+LCDVDD_CONN

W=60mils

+LCDVDD_CONN

1

C531

C532

0.1U_0402_16V4Z

2

INVPWM

+3VS

R1240 0_0402_5%

1 2

R1242 0_0402_5%

1 2

R1244 0_0402_5%

1 2

R1246 0_0402_5%

1 2

R1248 0_0402_5%

R1248 0_0402_5% R1250 0_0402_5%

R1250 0_0402_5%

R1252 0_0402_5%

R1252 0_0402_5% R1254 0_0402_5%

R1254 0_0402_5%

R1256 0_0402_5%

1 2

R1258 0_0402_5%

1 2

R1260 0_0402_5%

R1260 0_0402_5% R1264 0_0402_5%

R1264 0_0402_5%

R1263 0_0402_5%

R1263 0_0402_5% R1266 0_0402_5%

R1266 0_0402_5%

R1268 0_0402_5%

R1268 0_0402_5% R1270 0_0402_5%

R1270 0_0402_5%

DIS_ONLY@

DIS_ONLY@ DIS_ONLY@

DIS_ONLY@

DIS_ONLY@ DIS_ONLY@

DIS_ONLY@ 1 2 1 2

DIS_ONLY@

DIS_ONLY@ DIS_ONLY@

DIS_ONLY@ 1 2 1 2

DIS_ONLY@

DIS_ONLY@ DIS_ONLY@

DIS_ONLY@ 1 2 1 2

DIS_ONLY@

DIS_ONLY@ 1 2 1 2

DIS_ONLY@

1 2 1 2

DIS_ONLY@

+3VS

+CMOS_PW

EDID_CLK<17>

VGA_EDID_CLK<23>

VGA_EDID_DATA<23>

EDID_DATA<17>

+LEDVDD

DISPOFF# INVPWM

DMIC_DATA DMIC_CLK

LVDS_ACLK_CONN

LVDS_ACLK#_CONN

LVDS_A2_CONN

LVDS_A2#_CONN

LVDS_A1_CONN

LVDS_A1#_CONN

LVDS_A0_CONN

LVDS_A0#_CONN EDID_DATA_CONN EDID_CLK_CONN

USB20_P5 USB20_N5

LVDS_A0_CONN LVDS_A0#_CONN

LVDS_A1_CONN LVDS_A1#_CONN

LVDS_A2_CONN LVDS_A2#_CONN

LVDS_ACLK_CONN LVDS_ACLK#_CONN

LVDS_BCLK_CONN LVDS_BCLK#_CONN

LVDS_B0_CONN LVDS_B0#_CONN

LVDS_B1_CONN LVDS_B1#_CONN

LVDS_B2_CONN LVDS_B2#_CONN

ACES_88341-3001

EDID_CLK

VGA_EDID_CLK

VGA_EDID_DATA

EDID_DATA

3

JLVDS2

1

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

31

2

G1

32

3

G2

33

4

G3

34

5

G4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

ME@

R1199 0_0402_5%UMA@R1199 0_0402_5%UMA@

1 2

DIS_ONLY@

R1196 0_0402_5%

1 2

R1197 0_0402_5%

1 2

DIS_ONLY@

R1200 0_0402_5%

1 2

UMA@

3

2

DISPOFF#

LVDS_BCLK_CONN

LVDS_BCLK#_CONN

LVDS_B2_CONN

LVDS_B2#_CONN

LVDS_B1_CONN

LVDS_B1#_CONN

LVDS_B0_CONN

LVDS_B0#_CONN

LVDS_ACLK_CONN LVDS_ACLK#_CONN

LVDS_A2_CONN

LVDS_A2#_CONN

LVDS_A1_CONN

LVDS_A1#_CONN

LVDS_A0_CONN

LVDS_A0#_CONN

USB20_P5 USB20_N5

R891

1 2

0_0402_5%

12

R890

R890 10K_0402_5%

10K_0402_5%

DIS_ONLY@

INVPWM

D30

21

RB751V-40 SOD-323

@

R827

100K_0402_1%

+3VS

1 2

INVT_PWM<45>

VGA_BL_PWM<23>

(60 MIL)

+LCDVDD_CONN

+3VS

W=60mils

680P_0402_50V7K

EDID_DATA_CONN EDID_CLK_CONN

1

@

C528

2

EDID_CLK_CONN

EDID_DATA_CONN

R818

2.2K_0402_5%

+CMOS_PW

R815

1 2

0_0402_5% DIS@

R825

1 2

0_0402_5% @

+3VS

R819

2.2K_0402_5%

+3VS

CMOS

W=40mils

BKOFF#<45>

PCH_ENBKL<17>

VGA_ENBKL<23>

DMIC_DATA<42>

DMIC_CLK<42>

USB20_P5<18> USB20_N5<18>

BKOFF#

R1201 0_0402_5%UMA@R1201 0_0402_5%UMA@

1 2

R1202 0_0402_5%

1 2

CMOS Camera

R596

(40 MIL)

0_0603_5%

1 2

+3VS

+5VALW

CMOS_OFF#<45>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CMOS@

R434100K_0402_5%

CMOS@

1

OUT

2

IN

GND

Q84

Q84 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

3

CMOS@

2010/07/09 2008/10/15

S

G

2

SI2301BDS-T1-E3_S OT23-3

CMOS@

4.7V

R435

R435 150K_0402_5%

150K_0402_5%

CMOS@

1

CMOS@

C520

0.1U_0402_16V4Z

2

Compal Secret Data

Deciphered Date

D

+CMOS_PW_R+3VS_CMOS_IN

13

Q83

2

0_0603_5%

1 2

1

CMOS@

C518

0.1U_0402_16V4Z

2

JLVDS1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

STARC_107K40-000001-G2

ME@

12

@

R822

4.7K_0402_5%

DISPOFF#

(40 MIL)

+CMOS_PW

R432

CMOS@

1

Ventura_B++LEDVDD

DMIC_DATA

DMIC_CLK

2

3

D55

@

PJDLC05_SOT23-3

1

680P_0402_50V7K

41

G1

42

G2

43

G3

44

G4

45

G5

46

G6

C523

R813 0_0805_5%R813 0_0805_5%

1 2

1

C524

4.7U_0805_25V6-K

@

4.7U_0805_25V6-K

2

USB20_P5

USB20_N5

2

3

D52

@

PJDLC05_SOT23-3

1

ESD request

ENBKL <45>

1

CMOS@

C519

10U_0805_10V4Z

2

Compal Electronics, Inc.

Title

Size Doc ument Number Rev

Date: Sheet

Compal Electronics, Inc.

LVDS/CAMERA

Custom

LVDS/CAMERA

LA-6882P

34 63Wednesday, October 06, 2010

of

1

of

0.2

CyberForum.ru

A

VGA_CRT_R<23>

1 1

2 2

3 3

VGA_CRT_G<23>

VGA_CRT_B<23>

DAC_RED<17>

DAC_GRN<17>

DAC_BLU<17>

VGA_CRT_HSYNC<23>

VGA_CRT_VSYNC<23>

VGA_CRT_R

VGA_CRT_G

VGA_CRT_B

DAC_RED

DAC_GRN

DAC_BLU

CRT_HSYNC<17>

CRT_VSYNC<17>

R1271 0_0402_5%

1 2

DIS_ONLY@

R1272 0_0402_5%

1 2

DIS_ONLY@

R1273 0_0402_5%

1 2

DIS_ONLY@

R1274 0_0402_5%

1 2

UMA@

R1181 0_0402_5%

1 2

UMA@

R1182 0_0402_5%

1 2

UMA@

CRT_HSYNC

VGA_CRT_HSYNC

CRT_VSYNC

R1183 0_0402_5%

1 2

R1184 0_0402_5%

1 2

R1185 0_0402_5%

1 2

UMA@

R1186 0_0402_5%

1 2

DIS_ONLY@

+3VS

UMA@

DIS_ONLY@

B

DAC_RED_1

DAC_BLU_1

12

R830

R830 150_0402_1%

150_0402_1%

12

R831

R831 150_0402_1%

150_0402_1%

CLOSE TO CONN

0.1U_0402_16V4Z

HSYNC_G

FCM1608CF-121T03 0603

0.1U_0402_16V4Z

VSYNC_GVGA_CRT_VSYNC

+3VS

+5VS +5VS +5VS +5VS +5VS

3

2

@

D31

D31 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

C544

C546

12

R832

R832 150_0402_1%

150_0402_1%

+CRT_VCC

1

2

+CRT_VCC

1

2

1

2

10P_0402_50V8J

R833

1 2

1K_0402_5%

5

1

P

OE#

A2Y

G

U24

U24 SN74AHCT1G125DCKR_SC70-5

SN74AHCT1G125DCKR_SC70-5

3

R834

1 2

1K_0402_5%

5

1

P

OE#

A2Y

G

U25

U25 SN74AHCT1G125DCKR_SC70-5

SN74AHCT1G125DCKR_SC70-5

3

+CRT_VCC

1

4

C537

C

1

C538

2

10P_0402_50V8J

CRT_HSYNC_1

CRT_VSYNC_1

3

1

2

@

D32

D32 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

FCM1608CF-121T03 0603

1 2

L16

FCM1608CF-121T03 0603

1 2

L17

FCM1608CF-121T03 0603

1 2

L18

1

C539

C539 10P_0402_50V8J

10P_0402_50V8J

2

1

C540

2

10P_0402_50V8J

1 2

L19

1 2

L20FCM1608CF-121T03 0603 L20FCM1608CF-121T03 0603

3

2

1

C542

2

10P_0402_50V8J

1

BAT54S-7-F_SOT23-3

@

D33

RED

GREENDAC_GRN_1

BLUE

1

C541

C541 10P_0402_50V8J

10P_0402_50V8J

2

1

2

1

2

D

REDGREENBLUE

JVGA_HS

@

C545

C545 10P_0402_50V8J

10P_0402_50V8J

JVGA_VS

C547

@C547

@

10P_0402_50V8J

3

2

1

@

D34

D34 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

+5VS

2 1

RB491D_SC59-3

RED

CRT_DDC_DAT_CONN GREEN

JVGA_HS BLUE

JVGA_VS

CRT_DDC_CLK_CONN

D36

3

1

2

@

D35

D35 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

+CRT_VCC

CRT Connector

F1

1.1A_6V_SMD1812P110TF

W=40mils

1

C543

100P_0402_50V8J

2

E

JVGA_VSJVGA_HS

21

+CRT_VCC_CONN

1

C536

0.1U_0402_16V4Z

2

JCRT1

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

TYCO_1775763-1

ME@

16

G

17

G

12

R836

R835

2.2K_0402_5%

UMA@

CRT_DDC_DATA<17>

CRT_DDC_CLK<17>

VGA_CRT_DATA<23>

VGA_CRT_CLK<23>

4 4

CRT_DDC_DATA

CRT_DDC_CLK

VGA_CRT_DATA

VGA_CRT_CLK

A

R836

2.2K_0402_5%

UMA@

R1189 0_0402_5%

1 2

UMA@

R1190 0_0402_5%

1 2

UMA@

R1191 0_0402_5%

1 2

DIS_ONLY@

R1192 0_0402_5%

1 2

DIS_ONLY@

CRT_DDC_DATA_R

CRT_DDC_CLK_R

B

DMN66D0LDW-7 2N_SOT363-6

4

2

Q73A

Security Classification

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

2.2K_0402_5%

3

Q73B

61

Issued Date

12

R837

@

C548

100P_0402_50V8J

12

R838

2.2K_0402_5%

CRT_DDC_DAT_CONN

CRT_DDC_CLK_CONN

1

@

C549

C549 68P_0402_50V8K

68P_0402_50V8K

2

Compal Secret Data

2007/10/15 2008/10/15

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

CRT Connector

LA-6882P

35 63Wednesday, October 06, 2010

E

0.2

of

CyberForum.ru

5

R1130

D D

680_0402_1%

UMA_HDMI@

R1135

R1132

680_0402_1%

UMA_HDMI@

R1137

4

HDMI_CLK+_CK<17> HDMI_CLK-_CK<17>

HDMI_TX0+_CK<17>

HDMI_TX0-_CK<17> HDMI_TX1+_CK<17> HDMI_TX1-_CK<17> HDMI_TX2+_CK<17> HDMI_TX2-_CK<17>

VGA_HDMI_CLK+<24>

VGA_HDMI_CLK-<24> VGA_HDMI_TX0+<24>

VGA_HDMI_TX0-<24> VGA_HDMI_TX1+<24> VGA_HDMI_TX1-<24> VGA_HDMI_TX2+<24> VGA_HDMI_TX2-<24>

3

HDMI_CLK+_CK HDMI_CLK-_CK HDMI_TX0+_CK HDMI_TX0-_CK HDMI_TX1+_CK HDMI_TX1-_CK HDMI_TX2+_CK HDMI_TX2-_CK

VGA_HDMI_CLK+ VGA_HDMI_CLKVGA_HDMI_TX0+ VGA_HDMI_TX0VGA_HDMI_TX1+ VGA_HDMI_TX1VGA_HDMI_TX2+ VGA_HDMI_TX2-

2

CV253 0.1U_0402_10V6KDIS_HDMI@ CV253 0.1U_0402_10V6KDIS_HDMI@

1 2

CV254 0.1U_0402_10V6KDIS_HDMI@ CV254 0.1U_0402_10V6KDIS_HDMI@

1 2

CV255 0.1U_0402_10V6KDIS_HDMI@ CV255 0.1U_0402_10V6KDIS_HDMI@

1 2

CV256 0.1U_0402_10V6KDIS_HDMI@ CV256 0.1U_0402_10V6KDIS_HDMI@

1 2

CV257 0.1U_0402_10V6KDIS_HDMI@ CV257 0.1U_0402_10V6KDIS_HDMI@

1 2

CV258 0.1U_0402_10V6KDIS_HDMI@ CV258 0.1U_0402_10V6KDIS_HDMI@

1 2

CV259 0.1U_0402_10V6KDIS_HDMI@ CV259 0.1U_0402_10V6KDIS_HDMI@

1 2

CV260 0.1U_0402_10V6KDIS_HDMI@ CV260 0.1U_0402_10V6KDIS_HDMI@

1 2

+3VS

HDMI_CLK+_CK HDMI_CLK-_CK HDMI_TX0+_CK HDMI_TX0-_CK HDMI_TX1+_CK HDMI_TX1-_CK HDMI_TX2+_CK HDMI_TX2-_CK

1

680_0402_1%

UMA_HDMI@

R1140

680_0402_1%

UMA_HDMI@

R1134

680_0402_1%

2

3

2

3

2

3

2

3

680_0402_1%

UMA_HDMI@

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

HDMI_CLK+_CONN

HDMI_CLK-_CONN HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

C C

B B

HDMI_CLK+_CK

HDMI_CLK-_CK

HDMI_TX0+_CK

HDMI_TX0-_CK

HDMI_TX1+_CK

HDMI_TX1-_CK

HDMI_TX2+_CK

A A

HDMI_TX2-_CK

HDMI_CLK+_CK HDMI_CLK-_CK HDMI_TX0+_CK HDMI_TX0-_CK HDMI_TX1+_CK HDMI_TX1-_CK HDMI_TX2+_CK HDMI_TX2-_CK

L23

@L23

@

1

4

WCM-2012-900T_4P

L24

@L24

@

1

4

WCM-2012-900T_4P

L26

@L26

@

1

4

WCM-2012-900T_4P

L27

@L27

@

1

4

WCM-2012-900T_4P

R865 0_0402_5%HDMI@R865 0_0402_5%HDMI@

1 2

R866 0_0402_5%HDMI@R866 0_0402_5%HDMI@

1 2

R867 0_0402_5%HDMI@R867 0_0402_5%HDMI@

1 2

R868 0_0402_5%HDMI@R868 0_0402_5%HDMI@

1 2

R869 0_0402_5%HDMI@R869 0_0402_5%HDMI@

1 2

R870 0_0402_5%HDMI@R870 0_0402_5%HDMI@

1 2

R871 0_0402_5%HDMI@R871 0_0402_5%HDMI@

1 2

R872 0_0402_5%HDMI@R872 0_0402_5%HDMI@

1 2

5

680_0402_1%

UMA_HDMI@

R1141

680_0402_1%

UMA_HDMI@

R1138

680_0402_1%

UMA_HDMI@

DIS_HDMI@

+3VS

1 2

R1130 499_0402_1%

1 2

R1132 499_0402_1%

1 2

R1134 499_0402_1%

1 2

R1135 499_0402_1%

1 2

R1137 499_0402_1%

1 2

R1138 499_0402_1%

1 2

R1140 499_0402_1%

1 2

R1141 499_0402_1%

2

G

@

1 2

R1142 100K_0402_5%

4

13

D

Q114

2N7002H 1N_SOT23-3

HDMI@

S

VGA_HDMI_HPD<23>

R864

R864 20K_0402_5%

20K_0402_5%

UMA_HDMI@

1 2

Deciphered Date

HDMICLK

HDMIDAT

+3VS_VGA

+5VS

3

4

2

@

1

D38

D38 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

HDMICLK<17>

HDMIDAT<17>

VGA_HDMI_CLK<24>

VGA_HDMI_DATA<24>

+3VS

R859

1M_0402_5%

UMA_HDMI@

TMDS_B_HPD<17>

10K_0402_5%

12

R1144

DIS_HDMI@

100K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

G

2

Q85

1 2

R1143

1 2

DIS_HDMI@

Q85

UMA_HDMI@

HDMI_DET_UMA

13

D

S

D

S

2N7002_SOT23

L67

BLM18PG181SN1D_0603

2008/03/25 2008/04/

3

DIS_HDMI@

12

Compal Secret Data

2

UMA_HDMI@

61

DMN66D0LDW-7 2N_SOT363-6

5

2

DMN66D0LDW-7 2N_SOT363-6

Q80A

UMA_HDMI@

3

DMN66D0LDW-7 2N_SOT363-6

Q80B

DIS_HDMI@

61

DMN66D0LDW-7 2N_SOT363-6

5

DIS_HDMI@

Q115A

DIS_HDMI@

4

Q115B

R857

0_0805_5%

R860

2.2K_0402_5%

HDMI@

HDMIDAT_R HDMICLK_R

2

HDMICLK_R

3

DMN66D0LDW-7 2N_SOT363-6

1 2

HDMIDAT_R

+5VS

21

HDMI@

D37

D37 RB491D_SC59-3

RB491D_SC59-3

@R857

@

21

F2

1.1A_6V_SMD1812P110TF

+5VS_HDMI

R861

2.2K_0402_5%

HDMI@

1 2

HDMI_CLK-_CONN

HDMI_CLK+_CONN HDMI_TX0-_CONN

HDMI_TX0+_CONN HDMI_TX1-_CONN

HDMI_TX1+_CONN HDMI_TX2-_CONN

HDMI_TX2+_CONN

Title

Size Document Number Rev

Custom

Date: Sheet

HDMICLK_R

HDMIDAT_R

+5VS_HDMI_F

HDMI@

Compal Electronics,Ltd.

09/11 Add

C561

1

0.1U_0402_16V4Z

HDMI@

2

19 18 17 16 15 14 13 12 11 10

HDMI CONN

LA-6882P

JHDMI1

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CK-

G1

CK_shield

G2 CK+ D0D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

G3

G4

1

9 8 7 6 5 4 3 2 1

SUYIN_100042GR019M23DZL

ME@

20 21 22 23

0.2

36 63W ednesday, October 06, 2010

of

CyberForum.ru

A

B

C

D

E

Mini-Express Card for WLAN/WiMAX(Half) Mini-Express Card for SSD(Full)

+1.5VS

+3VS_WLAN+3VS

J3

33 35 37 39 41 43 45 47 49 51

C566

JP1

112 334 556 778 9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 33 35 37 39 41 43 45 47 49 51

GND53GND

ME@

J3

112

JUMP_43X79

@

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34

34

36

38

40

42

44

46

48

50

52

54

0.1U_0402_16V4Z

1

C567

2

10U_0805_10V4Z

1 1

R892 0_0402_5%@R892 0_0402_5%@

BT_OFF#<19,47>

BT_DISABLE<19>

2 2

DEVICE_RST#<19,38,44>

BUF_PLT_RST#<18,23,38,44,45,49>

1 2

R897 0_0402_5%@R897 0_0402_5%@

1 2

DEVICE_RST#

BUF_PLT_RST#

PCIE_WAKE#<16,38,49>

WLAN_CLKREQ1#<15>

1

2

1 2

R1343 0_0402_5%R1343 0_0402_5%

Mini-Express Card(SSD)

0.01U_0402_16V7K

3 3

4 4

SATA_DTX_C_IRX_P0<14> SATA_DTX_C_IRX_N0<14>

SATA_ITX_DRX_N0<14> SATA_ITX_DRX_P0<14>

EC_TX_P80_DATA<45,46> EC_RX_P80_CLK<45,46>

SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_N0 SATA_DTX_I RX_N0

EC_TX_P80_DATA EC_RX_P80_CLK

DA_DSS

SATA_DET#<14>

For SSD use:

0.01U_0402_16V7K

SATA_ITX_DRX_N0 SATA_ITX_DRX_P0

R893

R894

DA_DSS

R895 0_0402_5%R895 0_0402_5%

SATA_DET#

R896 0_0402_5%

C572

12

C573

12

100_0402_1%

1 2 1 2

100_0402_1%

1 2

@

Mini-Express Card(WLAN/WiMAX)

PCIE_WAKE#

BT_ACTIVE<47>

EC_TX_P80_DATA<45,46> EC_RX_P80_CLK<45,46>

MC74VHC1G08DFT2G SC70 5P

3

G

A

4

Y

B

P

@

U60

5

+3VS

SATA_DTX_IRX_P0

+3VS_SSD

@R893

@ @

@

BT_ACTIVE BT_DISABLE_R WLAN_CLKREQ1#

CLK_PCIE_WLAN1#<15>

CLK_PCIE_WLAN1<15>

PCIE_PRX_DTX_N2< 15> PCIE_PRX_DTX_P2<15>

PCIE_PTX_C_DRX_N2<15> PCIE_PTX_C_DRX_P2<15>

EC_TX_P80_DATA EC_RX_P80_CLK

For EC to detect debug card insert.

WL_RST#

R877 0_0402_5%@R 877 0_0402_5%@

1 2

100_0402_1%

R887

1 2 1 2

R888

100_0402_1%

SSD Active:4.5W(1.5A)

+3VS

JP3

112 334 556 778 9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132

33

35

37

39

41

43

45

47

49

51

GND53GND

ACES_51711-0520W-001

ME@

PCI_RST#_R CLK_PCI_DB

+3VS_WLAN

J5

112

JUMP_43X79

@

34 36 38 40 42 44 46 48 50 52

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54

R889

R889 100K_0402_5%

100K_0402_5%

1 2

2

+3VS_SSD

ACES_51711-0520W-001

1

2

0.01U_0402_25V7K

1

J4

1

JUMP_43X79

@

2

+1.5VS_WLAN

R880 0_0402_5%R880 0_0402_5%

1 2

R881 0_0402_5%@R 881 0_0402_5%@

1 2

R882 0_0402_5%R882 0_0402_5%

1 2

R883 0_0402_5%@R 883 0_0402_5%@

1 2

R884 0_0402_5%@R 884 0_0402_5%@

1 2

USB20_N9 <18> USB20_P9 <18>

R8850_0402_5% R8850_0402_5%

12

R8860_0402_5% R8860_0402_5%

12

FAST_BOOT#<38,44,45>

+3VS_SSD

10U_0805_10V4Z

1

C568

2

1

2

PCIE_PRX_DTX_N6< 15> PCIE_PRX_DTX_P6<15>

PCIE_PTX_C_DRX_N6<15> PCIE_PTX_C_DRX_P6<15>

EC_TX_P80_DATA<45,46> EC_RX_P80_CLK<45,46>

LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R

WLAN_LED#

@

C569

WL_RST#

FAST_BOOT#

+3VS_WLAN

1

2

+3VALW +3VS

SMB_CLK_S3 <12,13,15> SMB_DATA_S3 <12, 13,15>

WLAN_LED# <47>

Q132

2N7002_SOT23-3

@

CLKREQ_TV#<15>

CLK_PCIE_TV#<15>

CLK_PCIE_TV<15>

+1.5VS

1

C564

@

R1329

R1329 33K_0402_5%

33K_0402_5%

D

S

C564

0.1U_0402_16V4Z

2

+3VS

2

C921

0.1U_0402_16V4Z

1

@

C563

0.1U_0402_16V4Z

WL_OFF# <18>

+5VS

12

13

2

G

Mini-Express Card(TV)

CLKREQ_TV#

+3VS_TV

@

100_0402_1%

R1209

EC_TX_P80_DATA EC_RX_P80_CLK

R1209

1 2 1 2

R1208

100_0402_1%

@

1

2

JP14

112 334 556 778 9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132

33

35

37

39

41

43

45

47

49

51

GND53GND

ACES_51711-0520W-001

ME@

Reserve for SW mini-pcie debug card. Series resistors closed to KBC side.

C565

0.1U_0402_16V4Z

D

S

D

S

1 3

AO3414_SOT23-3

G

@

2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34

34

36

38

40

42

44

46

48

50

52

54

LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R PCI_RST#_R CLK_PCI_DB

Q133

+3VS_TV

R873 0_0402_5%@R873 0_0402_5%@ R874 0_0402_5%@R874 0_0402_5%@ R875 0_0402_5%@R875 0_0402_5%@ R876 0_0402_5%@R876 0_0402_5%@ R878 0_0402_5%@R878 0_0402_5%@ R879 0_0402_5%@R879 0_0402_5%@

4.7U_0805_10V4Z

+1.5VS_TV

TV_RST#

33K_0402_5%

TV_POWER_OFF#<45>

C901

USB20_N12 <18> USB20_P12 <18>

1 2 1 2 1 2 1 2 1 2 1 2

+3VS_WLAN

1

2

TV@

0.1U_0402_16V4Z

R1203

0.1U_0402_16V4Z

LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 BUF_PLT_RST#

+3VS_TV+1.5VS_TV

1

C902

4.7U_0805_10V4Z

2

TV@

1

C912

@ C912

@

2

4

NC7SZ08P5X_NL_SC70-5

+5VS

AO3414_SOT23-3

Q118

12

TVSW@

2

G

1

C900

2

TVSW@

+3VS

R1206

5

U54

2

P

B

Y

1

A

G

TVSW@

3

NO_TVSW@

R12070_0402_5%

1 2

+3VS +1.5VS

AO3414_SOT23-3

13

D

R1204

R1204 0_0805_5%

0_0805_5%

S

NO_TVSW@

1 2

LPC_FRAME# <14,45> LPC_AD3 < 14,45> LPC_AD2 < 14,45> LPC_AD1 < 14,45> LPC_AD0 < 14,45>

CLK_PCI_DB < 15>

1 2

33K_0402_5%

1

TVSW@

C903

0.1U_0402_16V4Z

2

TVSW@

BUF_PLT_RST# <18,23,38, 44,45,49>

TV SW

Q119

13

D

TVSW@

2

G

S

TV SW

+3VS_TV

1 2

R1205

R1205 0_0402_5%

0_0402_5%

NO_TVSW@

+1.5VS_TV+3VS_TV

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/10/15 2008/10/15

Compal Secret Dat a

Deciphered Dat e

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Mini-Card

LA-6882P

E

of

37 63Wednesday, October 06, 2010

of

37 63Wednesday, October 06, 2010

of

37 63Wednesday, October 06, 2010

0.2

CyberForum.ru

5

3

1

G

A

2

B

P

5

+3VS

+1.2V_LAN

C586

4.7U_0603_6.3V6K

C586

4.7U_0603_6.3V6K

1

2

C601 0.1U_0402_16V7KC601 0.1U_0402_16V7K

1 2

C602 0.1U_0402_16V7KC602 0.1U_0402_16V7K

1 2

R901 4.7K_0402_5%@R901 4.7K_0402_5%@

1 2

R902 0_0402_5%@R902 0_0402_5%@

1 2

R903 0_0402_5%

1 2

57781@

57781@ 57781@

57781@

R904 0_0402_5%

R904 0_0402_5% R1217 0_0402_5%

R1217 0_0402_5%

57780@

LAN_RST#_R

LAN_XTALO LAN_XTALI

LAN_XTALO

CLKREQ_LAN#<15>

J11

D

1 3

20mil

PCIE_PRX_DTX_P1<15>

PCIE_PRX_DTX_N1<15> PCIE_PTX_C_DRX_P1<15> PCIE_PTX_C_DRX_N1<15>

12

@

R234

R234 33K_0402_5%

33K_0402_5%

13

D

S

DEVICE_RST#

BUF_PLT_RST#

PCIE_WAKE#<16,37,49>

LAN_WAKE#<45>

CLK_PCIE_LAN<15>

CLK_PCIE_LAN#<15>

+3VALW

2

1

+3V_LAN

LAN_RST#_R

+LAN_XTALVDDH

C289

0.1U_0402_16V4Z

@

DEVICE_RST#<19,37,44>

BUF_PLT_RST#<18,23,37,44,45,49>

D D

C C

B B

A A

SM010005500 500ma 600ohm@100mhz DCR 0.38

+1.2V_LAN

L29

BLM18AG601SN1D_2P

C593

4.7U_0603_6.3V6K

L32

BLM18AG601SN1D_2P

1

2

FAST_BOOT#<37,44,45>

12

C597

4.7U_0603_6.3V6K

L33

12

C599

4.7U_0603_6.3V6K

+1.2V_LAN

Y4

25MHZ_20PF_7A25000012

1 2

C608

C608 27P_0402_50V8J

27P_0402_50V8J

12

1

2

1

2

1

2

FAST_BOOT#

Q18

2N7002_SOT23-3

5

+LAN_PCIEPLLVDD

1

C594

0.1U_0402_16V4Z

2

+LAN_GPHYPLLVDDL

1

C598

0.1U_0402_16V4Z

2

+LAN_AVDDL

1

C600

0.1U_0402_16V4Z

2

LAN_XTALI

LAN_XTALO

1

C609

C609 27P_0402_50V8J

27P_0402_50V8J

2

+5VALW

2

G

@

4

MC74VHC1G08DFT2G SC70 5P

@

1 2

LAN_RST#_R

4

Y

U8

R914 0_0402_5%R914 0_0402_5%

091211 EMI add 1000P

C588

0.1U_0402_16V4Z

C588

0.1U_0402_16V4Z

C587

0.1U_0402_16V4Z

C587

0.1U_0402_16V4Z

1

2

1 2 1 2

57780@

R1224 0_0402_5%

57781@

R1225 200_0402_1%

R1225 200_0402_1% R1226 0_0402_5%

R1226 0_0402_5%

57781@

R1227 200_0402_1%

57780@

@J11

@

JOPEN

12

S

Q17

AO3414_SOT23-3

G

@

2

1

2

+3VS

R909 1K_0402_5%

R909 1K_0402_5% R1222 0_0402_5%

R1222 0_0402_5%

57780@

1 2

12

1 2

12

1 2

R912 1.24K_0402_1%

R1228 0_0402_5%

4.7U_0603_6.3V6K

4

C590

1000P_0402_50V7K

C590

1000P_0402_50V7K

C589

0.1U_0402_16V4Z

C589

0.1U_0402_16V4Z

1

2

+LAN_AVDDL

+LAN_GPHYPLLVDDL

+LAN_PCIEPLLVDD

PCIE_PRX_C_DTX_P1 PCIE_PRX_C_DTX_N1

1 2 1 2

LAN_XTALO_81 LAN_XTALI_81

LAN_RDAC

1 2

57781@

+3V_LAN

60mil

1

C583

2

+3V_LAN

C591

1000P_0402_50V7K

C591

1000P_0402_50V7K

1

2

LAN_PME#

1

C584

0.1U_0402_16V4Z

2

3

U27

42

VDDO

15

VDDC

41

VDDC

27

AVDDL

33

AVDDL

39

AVDDL

24

GPHY_PLLVDDL

18

PCIE_PLLVDDL

21

PCIE_PLLVDDL

17

PCIE_TXD_P

16

PCIE_TXD_N

22

PCIE_RXD_P

23

PCIE_RXD_N

1

WAKE#/WAKE#/LOW_PWR

6

PERST#/PERST#/VDDC

20

PCIE_REFCLK_P

19

PCIE_REFCLK_N

40

VMAIN_PRSNT

2

LOW_PWR/LOW_PWR/PERST#

14

XTALO/XTAL O/XTALVDDH

13

XTALI/XTAL I/XTALO

26

RDAC

7

CLK_REQ#/CLK_REQ#/DC

BCM57781A0KMLG_QFN48_6X6 57781@

BCM57781A0KMLG_QFN48_6X6

BCM57781

SO#_LINKLED#/SO#_LINKLED#/TRAFFICLED#

SCLK_SPD1000LED#/SCLK_SPD1000LED#/SPD1000LED#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SPD100LED#/SPD100LED#/LINKLED#

TRAFFICLED#/TRAFFICLED#/SPD100LED#

CS#_EECLK/CS#_EECLK/EEDATA

SI#_EEDATA/SI#_EEDATA/EECLK

PAD

49

3

+LAN_BIASVDDH

25

BIASVDDH

R1210

57780@R1210

LAN_XTALI_80

AVDDH AVDDH

TRD3_N TRD3_P

TRD2_N TRD2_P

TRD1_N TRD1_P

TRD0_N TRD0_P

SR_LX

SR_VFB

SR_VDDP

SR_VDD

U27

BCM57780

12

R1211 0_0402_5%

+LAN_AVDDH

30 36

MDI3-

37

MDI3+

38

MDI2-

35

MDI2+

34

MDI1-

31

MDI1+

32

MDI0-

29

MDI0+

28

57780@

R1212 0_0402_5%

R1212 0_0402_5% R1213 0_0402_5%

R1213 0_0402_5%

45

57781@

48

46

57781@

R1214 0_0402_5%

47

R1215 0_0402_5%

57780@

3

R913 4.7K_0402_5%@R913 4.7K_0402_5%@ R1216 0_0402_5%

R1216 0_0402_5%

57780@

R1287 0_0402_5%57780@R1287 0_0402_5%57780@

R1218 0_0402_5%@R1218 0_0402_5%@

57781@

R905 4.7K_0402_5%

4

R906 4.7K_0402_5%

5

57781@

R1219 0_0402_5%

57780@

R1220 0_0402_5%

43

57781@

R1221 0_0402_5%

44

57781@

R1223 0_0402_5%

57780@

40mil

+1.2V_LAN_ OUT

11 8

10 9

C606

4.7U_0603_6.3V6K

57780@

Compal Secret Data

Deciphered Date

XTALVDDH/XTALVDDH/XTALI

GPIO0/GPIO0/CLK_R EQ#

SMB_CLK/TEST_1/WAKE#

SMB_DATA/TEST_2/MODE

2008/08/10 2010/08/01

57780@

1 2

57781@

12 12

1 2 1 2

1 2

1 2 1 2

1 2

4.7UH_PG031B-4R7MS_1.1A_20%

1 2

0.1U_0402_16V4Z

+3V_LAN

1

C607

0.1U_0402_16V4Z

2

0_0402_5%

MDI3- <39> MDI3+ <39>

MDI2- <39> MDI2+ <39>

MDI1- <39> MDI1+ <39>

MDI0- <39> MDI0+ <39>

L34

2

LAN_XTALI

+LAN_XTALVDDH

ACTIVITY# LAN_SK#

LAN_SK#

ACTIVITY# LAN_SK#

CLKREQ_LAN#

LAN_WAKE#

PCIE_WAKE#

SPROM_DOU T

SPROM_CLK

SPROM_DOU T

SPROM_CLK

1

C604

2

SM010005500 500ma 600ohm@100mhz DCR 0.38

C595

20mil

1

2

1 2

+1.2V_LAN

1

C605

C605 10U_0805_10V4Z

10U_0805_10V4Z

2

LAN_SK# <39>

ACTIVITY# <39>

+3V_LAN

+LAN_BIASVDDH

+LAN_XTALVDDH

+LAN_AVDDH

0.1U_0402_16V4Z

SPROM_CLK

SPROM_DOU T

On chip

AT24C02

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

1

BLM18AG601SN1D_2P

1

C585

0.1U_0402_16V4Z

2

1

C592

0.1U_0402_16V4Z

2

BLM18AG601SN1D_2P

1

C596

0.1U_0402_16V4Z

2

@

R907

1K_0402_1%@R907

1K_0402_1%

1 2

R910

1K_0402_1% R910

1K_0402_1%

1 2

L30

1 2

L28

BLM18AG601SN1D_2P

1 2

L31

1 2

+3V_LAN

R908

1K_0402_1% R908

1K_0402_1%

@

R911

1K_0402_1%@R911

1K_0402_1%

SPROM_CLK (EECLK)

+3V_LAN

@

1

C603

0.1U_0402_16V4Z

2

U28

@U28

@

8

VCC

7

WP

6

SCL

5

SDA

AT24C02_SO8

SPROM_DOUT (EE DATA)

1 1

Broadcom BCM57781

LA-6882P

1

A0

2

A1

3

NC

4

GND

01

0.2

38 63Wednesday , October 06, 2010

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CyberForum.ru

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4

3

2

1

D D

C C

Close to T49

C280 0.01U_0402_16V7KC280 0.01U_0402_16V7K

12

C281 0.01U_0402_16V7KC281 0.01U_0402_16V7K

12

C282 0.01U_0402_16V7KC282 0.01U_0402_16V7K

12

C278 0.01U_0402_16V7KC278 0.01U_0402_16V7K

12

Place close to TCT pin

T49

1

TCT1

1:1

MDI3+

MDI3-

MDI2+

MDI2-

MDI1+

MDI1-

MDI0+

MDI0-

2

3

4

5

6

7

8

9

10

11

12

MDI3+<38>

MDI3-<38>

MDI2+<38>

MDI2-<38>

MDI1+<38>

MDI1-<38>

MDI0+<38>

MDI0-<38>

TD1+

TD1-

TCT2

TD2+

TD2-

TCT3

TD3+

TD3-

TCT4

TD4+

TD4-

LG-2446S-1

1:1

MCT1

MX1+

MX1-

MCT2

MX2+

MX2-

MCT3

MX3+

MX3-

MCT4

MX4+

MX4-

MCT3

24

MDO3+

23

MDO3-

22

MCT2

21

MDO2+

20

MDO2-

19

MCT1

18

MDO1+

17

MDO1-

16

MCT0

15

MDO0+

14

MDO0-

13

R320 75_0402_5%R320 75_0402_5%

R321 75_0402_5%R321 75_0402_5%

R318 75_0402_5%R318 75_0402_5%

R319 75_0402_5%R319 75_0402_5%

12

1000P_1206_2KV7K

C129

1

2

RJ45 Conn.

JRJ45

LAN_SK#<38>

B B

3

ACTIVITY#

LAN_SK#

2

D68

D68 AZC199-02S.R7G C/C SOT23

AZC199-02S.R7G C/C SOT23

@

1

ESD request

LAN_SK#

1

@

2

ACTIVITY#<38>

C279

C279 68P_0402_50V8K

68P_0402_50V8K

ACTIVITY#

R317 300_0402_5%R317 300_0402_5%

+3V_LAN

C93

@C93

@

470P_0402_50V7K

12

For EMI.

R574 300_0402_5%R574 300_0402_5%

1

C610

C610 68P_0402_50V8K

68P_0402_50V8K

2

@

12

MDO3-

MDO3+

MDO1-

MDO2-

MDO2+

MDO1+

MDO0-

MDO0+

12

+3V_LAN

JRJ45

12

Green LED -

11

GreenLED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

Yellow LED-

9

Yellow LED+

SUYIN_100073HR012M25KZL

ME@

SHLD2 SHLD1

16 15

14 13

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/08/10 2010/08/01

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

LAN Magnetic & RJ45

LA-6882P

1

39 63Wednesday , October 06, 2010

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CyberForum.ru

5

D D

Close U29

C622

2200P_0402_50V7K

C623

2200P_0402_50V7K

C C

1

2

1

2

REMOTE1+

REMOTE1-

REMOTE2+

REMOTE2-

4

C625

0.1U_0402_16V4Z

+3VS

3

SMSC thermal sensor placed near by palmrest

U29

1

REMOTE1+

2

REMOTE1-

REMOTE2+

1

REMOTE2-

VDD

2

DP1

3

DN1

4

DP2

5

DN2

F75303M MSOP 10P

SMCLK

SMDATA

ALERT#

THERM#

GND

+3VS

12

R920

R920 10K_0402_5%

10K_0402_5%

@

10

9

8

7

6

EC_SMB_CK2

EC_SMB_DA2

EC_SMB_CK2 <15,23,45,50>

EC_SMB_DA2 <15,23,45,50>

Address 1001_101xb

2

REMOTE1+

C621

100P_0402_50V8J

REMOTE1-

REMOTE2+

C624

100P_0402_50V8J

REMOTE2-

1

@

2

1

@

2

Under VRAM

C

Q86

2

B

MMST3904-7-F_SOT323-3

E

3 1

Close to DDR

C

Q87

2

B

MMST3904-7-F_SOT323-3

E

3 1

REMOTE1,2+/-: Trace width/space:10/10 mil

1

Trace length:<8"

B B

+5VS

J16

@ J16

@

2

112

JUMP_43X79

2

C626

C626 10U_0805_10V4Z

10U_0805_10V4Z

1

A A

Security Classification

2008/03/25 2008/04/

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/25 2008/04/

3

Compal Secret Data

Deciphered Date

2

JUMP_43X79

EC_TACH<45>

EC_FAN_PWM<45>

Compal Electronics,Ltd.

Title

EMC1403_Thermal sensor/FAN

Size Document Number Rev

Custom

Date: Sheet

FAN1 Conn

JP4

1

2

3

4

5

G5

6

G6

ACES_85205-04001

ME@

LA-6882P

1

0.2

40 63W ednesday, October 06, 2010

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CyberForum.ru

A

1 1

B

C

D

E

F

G

H

SATA HDD Conn.

JHDD1

2 2

SATA_DTX_C_IRX_N1<14>

SATA_DTX_C_IRX_P1<14>

+5VS +3VS

1

C631

C631 1000P_0402_50V7K

1000P_0402_50V7K

3 3

4 4

2

SATA_DTX_C_IRX_P1

1

C632

0.1U_0402_16V4Z

2

1

C633

C633 1U_0603_10V4Z

1U_0603_10V4Z

2

SATA_ITX_DRX_P1<14> SATA_ITX_DRX_N1<14>

C627 0.01U_0402_16V7KC627 0.01U_0402_16V7K

1 2

C628 0.01U_0402_16V7KC628 0.01U_0402_16V7K

1 2

@ J13

+3VS

+5VS

1

C634

C634 10U_0805_10V4Z

10U_0805_10V4Z

2

@

112

JUMP_43X79

@ J12

@

112

JUMP_43X79

J13

2

J12

2

1

C635

C635 10U_0805_10V4Z

10U_0805_10V4Z

2

SATA_ITX_DRX_P1 SATA_ITX_DRX_N1

SATA_DTX_IRX_N1SATA_DTX_C_IRX_N1 SATA_DTX_IRX_P1

+3VS_HDD

+5VS_HDD

1

@

C636

0.1U_0402_16V4Z

2

JHDD1

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

VCC3.3

9

VCC3.3

10

VCC3.3

11

GND

12

GND

13

GND

14

VCC5

15

VCC5

16

VCC5

17

GND

18

Reserved

19

GND

20

VCC12

21

VCC12

GND

22

VCC12

GND

OCTEK_SAT-22HTAB

ME@

SATA ODD Conn.

JODD1

1

SATA_ITX_DRX_P2_CONN<14>

SATA_DTX_C_IRX_N2<14> SATA_DTX_C_IRX_P2<14>

23 24

ODD_DA#<18,45>

SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 SATA_DTX_IRX_P2

+3VS

ODD_DA#

SATA_ITX_DRX_N2_CONN<14>

C629 0.01U_0402_16V7KC629 0.01U_0402_16V7K

1 2

C630 0.01U_0402_16V7KC630 0.01U_0402_16V7K

1 2

R921

@R921

@

1 2

10K_0402_5%

R922 0_0402_5%R922 0_0402_5%

SATA_ITX_DRX_P2_CONN SATA_ITX_DRX_N2_CONN

SATA_DTX_IRX_N2

R710 0_0402_5%R710 0_0402_5%

1 2

+5V_ODD

1 2

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

DP

9

+5V

10

+5V

11

MD

12

GND GND13GND

OCTEK_SLS-13PNAB

ME@

GND

15 14

ODD Power Control

J6

@ J6

@

2

112

JUMP_43X79

+5VS

12

R923

R923 10K_0402_5%

10K_0402_5%

R1110

1 2

100K_0402_5%

1

OUT

ODD_EN<19>

2

IN

GND

3

100K_0402_5%

Q89

Q89 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

JUMP_43X79

Q88

S

G

2

D

13

AO3413_SOT23-3

C638

0.01U_0402_16V7K

1 2

+5V_ODD

1

2

C639

C639 10U_0805_10V4Z

10U_0805_10V4Z

1

C637

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2007/10/15 2008/10/15

E

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

F

Date: Sheet

Compal Electronics, Inc.

HDD/ODD Connector

LA-6882P

G

0.2

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Adjustable Output

J8

@J8

@

+5VAMP

+5VS

R924

+3VS

5503@

10U_0805_10V4Z

R929

10U_0805_10V4Z

12

1

C640

2

0.1U_0402_16V4Z

12

1

C656

2

0.1U_0402_16V4Z

CHB1608U301_0603

D D

CHB1608U301_0603

1.2V LDO for ALC5503 only.

C C

JOPEN

U30

1

IN

2

GND

3

SHDN

G9191-475T1U_SOT23-5

C641

4.75V LDO

Adjustable Output

U31

1

IN

2

GND

3

SHDN

5503@

G9091-120T11U_SOT23-5

5503@

C657

12

+5VDDA_CODEC

5

OUT

4

BYP

5

OUT

4

BYP

5503@

HDA_RST_AUDIO#<14>

1

C642

2

0.01U_0402_16V7K

+12VDD_CODEC

1

C658

2

0.01U_0402_16V7K

C643

4.7U_0805_10V4Z

C659

5503@

4.7U_0805_10V4Z

C650

@

22P_0402_50V8J

+3VS

12

R331

4.7K_0402_5%

@

2

C822

C822 100P_0402_50V8J

100P_0402_50V8J

1

@

1

2

@

22P_0402_50V8J

Reserve for EMI.

2

1

B B

MIC_EXTR_C MIC_EXTL_C

CBP CBN

SENSEB SENSEA

C_LINE_OUTL

+MIC1_VREFO_L

A A

5

C_LINE_OUTR

VREF

CPVREF JDREF EAPD_R

HDA_RST_AUDIO# PC_BEEP

VDMIC-CLK

30

LINE1_R

29

LINE1_L

21

LINE2_R

20

LINE2_L

28

MIC1_R

27

MIC1_L

23

MIC2_R

22

MIC2_L

39

CBP

40

CBN

44

SENSE B

19

SENSE A

45

FRONT_L

46

FRONT_R

38

VREFO-B

26

VREFO-E

25

VREFO-F

24

VREFO-C

37

VREF

55

SURR-R

53

SURR-L

41

CPVEE

54

JDREF

61

EAPD

13

RESETB

14

PCBEEP IN

9

DVSS-IO

6

DVSS

65

THERMAL PAD

ALC5503_QFN64_9X9

5503@

VDMIC-DATA

4

HDA_RST_AUDIO#

HDA_SYNC_AUDIO

HDA_SDOUT_AUDIO

@

1 2

R926 33_0402_5%

1

C653

C652

C651

2

@

22P_0402_50V8J

RB751V_SOD323

EXT_MIC_L<43>

EXT_MIC_R<43>

2

+MIC1_VREFO_L

D22

R930

2.2K_0402_5%

external MIC

MIC Sense R939 place near pin13 Capless HP Sense R940 place near pin34

+5VDDA_CODEC

52

56

AVSS136AVSS2

GPIO1/D MIC-DATA3 4 GPIO0/D MIC-DATA1 2

VGPIO5/VOL-MUTE/T DO

VGPIO4/VOL-UP/T CLK

VGPIO3/TDI/VOL-D N

AVDD135AVDD2

DMIC_CLK34 DMIC_CLK12

MONO_OUT

MCLKO

BCLK

SYNC

SPDIF_OUT2

SPDIF_OUT

HPOUT_L

HPOUT_R

SDATA_OUT

SDATA_IN

VGPIO2/TMS

VGPIO1

VGPIO0/TRST#

DVDD-12 DVDD-12 DVDD-12 DVDD-IO DVDD-33

4

U33

58 60

51 63

8 12

59 62

43 42

7 10

5 4

49 50 47 34 32 31

64 33 16 11 3

57

NC

48

NC

18

NC

17

NC

15

NC

EMI

HDA_BITCLK_AUDIO

21

D23

RB751V_SOD323

Vendor recommend. 2.2K

R931

2.2K_0402_5%

1 2

HDA_BITCLK_AUDIO<14>

HDA_SDOUT_AUDIO<14>

HDA_SDIN0<14>

HDA_SYNC_AUDIO<14>

DMIC_DATA<34>

MIC_JD<43>

PLUG_IN<43>

EAPD<45>

DMIC_CLK_R

HDA_BITCLK_AUDIO HDA_SYNC_AUDIO

SPDIF

HPOUT_L HPOUT_R

HDA_SDOUT_AUDIO

SDATA_IN

DMIC_DATA

@

12

@

R322 10K_0402_5%

12

R323 10K_0402_5%

@

12

@

R324 10K_0402_5%

12

R326 10K_0402_5%

@

12

R328 10K_0402_5%

@

12

R327 10K_0402_5%

+IOVDD_CODEC +3VDD_CODEC

+3VS +3VDD_CODEC

R925

1 2

CHB1608U301_0603

1

C644

2

Place near Pin1

Vendor recommend. 4.7u

C6624.7U_0603_6.3V6K C6624.7U_0603_6.3V6K

33_0402_5%

DMIC_DATA

C94

1 2

0.1U_0402_16V4Z

1

C674

2

0.1U_0402_16V4Z

1 2

R938

1 2

1

2

0.1U_0402_16V4Z

C6634.7U_0603_6.3V6K C6634.7U_0603_6.3V6K

HDA_SDOUT_AUDIO

HDA_RST_AUDIO#

HDA_SYNC_AUDIO

12

R93920K_0402_1% R93920K_0402_1%

12

R9405.1K_0402_1% R9405.1K_0402_1%

R9410_0402_5% R9410_0402_5%

+12VDD_CODEC

1

C675

2

R9331K_0402_5% R9331K_0402_5%

R9351K_0402_5% R9351K_0402_5%

HDA_BITCLK_AUDIO

+3VDD_CODEC

C673

Place near Pin 16,33,64

3

1

C645

2

0.1U_0402_16V4Z

MIC_EXTL_C

MIC_EXTR_C

PC_BEEP

SDATA_INHDA_SDIN0

SENSEA

SENSEB

EAPD_R

10U_0805_10V4Z

+5VDDA_CODEC

U32

AVDD125AVDD2

14

LINE2-L

15

LINE2-R

16

MIC2_L

17

MIC2_R

23

LINE1_L

24

LINE1_R

21

MIC1_L

22

MIC1_R

12

BEEP_IN

6

BITCLK

5

SDATA_OUT

8

SDATA_IN

11

RESET#

10

SYNC

2

GPIO0/D MIC_DATA1/ 2

3

GPIO1/D MIC_DATA3/ 4

13

SENSE A

34

SENSE B

47

EAPD

43

NC

4

DVSS

7

DVSS

ALC272-VA2-GR_LQFP48

272@

38

+3VDD_CODEC

9

1

DVDD

DMIC_CLK1/2

DMIC_CLK3/4

LINE2_VREFO

LINE1_VREFO

MIC1_VREFO

MIC2_VREFO

DVDD_IO

LOUT1_L

LOUT1_R

LOUT2_L

LOUT2_R

SPDIFO1

SPDIFO2

HPOUT_L

HPOUT_R

MONO_OUT

CPVREF

VREF

JDREF

AVSS1 AVSS2

Place near Pin9

+IOVDD_CODEC

C654

C_LINE_OUTL

35

C_LINE_OUTR

36

39

41

48

45

33

32

37

46

44

20

18

28

19

31

27

40

30

CBN

29

CBP

26 42

2

1

C655

2

10U_0805_10V4Z

0.1U_0402_16V4Z

C660 0.1U_0603_25V7KC660 0.1U_0603_25V7K

1 2

C661 0.1U_0603_25V7KC661 0.1U_0603_25V7K

1 2

(FBMA-L10-160808-800LMT) CO PMAL PN:SM01000DI00

SPDIF

HPOUT_L

HPOUT_R

DMIC_CLK_R

CBN

CBP

1 2

L66

1 2

FBMA-10-100505-301T_0402

(FBMA-10-100505-301T 0402 ) COPMAL PN:S M01000CY00

For EMI request.

+MIC1_VREFO_L

CPVREF

1 2

C664 2.2U_0603_6.3V6KC664 2.2U_0603_6.3V6K

VREF

JDREF

1 2

C666 2.2U_0603_6.3V6KC666 2.2U_0603_6.3V6K

Pin Assignment

LINE-OUT (Pin35/36)

Capless HP-OUT (Pin32/33)

LINE1 (Pin23/24)

MIC1(Pin21/22)

MIC2(Pin16/17)

PC Beep

EC Beep

BEEP#<45>

0.1U_0402_16V4Z@

HDA_SPKR<14>

ICH Beep

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/25 2008/04/

Compal Secret Dat a

Deciphered Dat e

2

1 2

R9320_0402_5% R9320_0402_5%

12

R93463.4_0402_1% R93463.4_0402_1%

12

R93663.4_0402_1% R93663.4_0402_1%

SPDIF_OUT <43>

HP_OUTL <43>

HP_OUTR <43>

12

R942

R942 20K_0402_1%

20K_0402_1%

Location Function

Internal

External

Internal

C670

1

1U_0603_10V4Z

C671

2

C672

1U_0603_10V4Z

1

+5VDDA_CODEC

1

C646

C647

2

10U_0805_10V4Z

0.1U_0402_16V4Z

Place near Pin25 Place near Pin38

R9270_0402_5% R9270_0402_5%

R9280_0402_5% @ R9280_0402_5% @

LINE_OUTL

LINE_OUTR

+3VS

+1.5VS

LINE_OUTL <43>

LINE_OUTR <43>

Internal Speaker

SPDIF

Headphone

Add 64 ohm serial resistor to avoid ESD

DMIC_CLK <34>

1

2

C667

C665

2

1

10U_0805_10V4Z

0.1U_0402_16V4Z

Place near Pin27

Int Speaker

Headphone out

Line in

Mic in

Internal Mic

+3VS

12

R947

R947 10K_0402_1%

10K_0402_1%

C668

12

1U_0603_10V4Z

R948

R948 10K_0402_1%

10K_0402_1%

1 2

R949 20K_0402_5%R949 20K_0402_5%

1

C

1 2

12

560_0402_5%

12

1 2

560_0402_5%

10K_0402_5%

R952

R950

C

Q90

2

B

2SC2411KT146_SOT23-3

E

3

12

D45

@D45

R953

Title

Size Document Number Rev

C

Date: Sheet

@

RB751V_SOD323

2 1

Compal Electronics,Ltd.

HD Audio Codec_ALC272

LA-6882P

1

C649

C648

2

0.1U_0402_16V4Z

C928

1 2

C929

1 2

C913

1 2

C914

1 2

R943

1 2

R944

1 2

R945

1 2

R946

1 2

C669 1U _0603_10V4ZC669 1U_0603_10V4Z

12

R951

R951 20K_0402_5%

20K_0402_5%

@

1 2

5503@

10U_0805_10V4Z

0.1U_0402_16V4Z

0_0402_5%

GNDAGND

PC_BEEPPC_BEEP1

42 63Wednesday, October 06, 2010

of

0.2

CyberForum.ru

5

wide 25MIL

SPK_R1SPK_R2+ SPK_L1-

D D

C C

B B

LINE_OUTL<42>

LINE_OUTR<42>

A A

SPK_L2+

LINE_OUTL

LINE_OUTR

R1280 0_0805_5%R1280 0_0805_5%

1 2

R1281 0_0805_5%R1281 0_0805_5%

1 2

R1282 0_0805_5%R1282 0_0805_5%

1 2

R1283 0_0805_5%R1283 0_0805_5%

1 2

C926 0.033U_0402_16V7KC926 0.033U_0402_16V7K

1 2

C927 0.033U_0402_16V7KC927 0.033U_0402_16V7K

1 2

@

SPK_R1-_CONN SPK_R2+_CONN SPK_L1-_CONN SPK_L2+_CONN

SPK_R1-_CONN

SPK_R2+_CONN

2

3

@

D59

PACDN042Y3R_SOT23-3

1

Reserve for ESD request.

+5VAMP +3VALW

12

R961

R960

10K_0402_5%

@

1

C678

2

@

W=40mil

GAIN0

GAIN1

LIN

RIN

1

C691

0.1U_0603_25V7K

2

4

1

C679

2

@

1000P_0402_50V7K

SPK_L1-_CONN

SPK_L2+_CONN HP_OUTL

2

3

PACDN042Y3R_SOT23-3

1

16

6

15

2

3

5

17

9

7

1

C692

0.1U_0603_25V7K

2

C681

C680

2

@

1000P_0402_50V7K

@

D60

U34

VDD PVDD PVDD

GAIN0

GAIN1

LIN-

RIN-

LIN+

RIN+

TPA6017A2PWPR_TSSOP20

1

2

1000P_0402_50V7K

3

SHUTDOWN

ROUT-

LOUT+

ROUT+

BYPASS

JSPK1

1

2

3

4

5

GND

6

GND

ACES_87212-04G0

ME@

HP_OUTR

2

@

D61

PACDN042Y3R_SOT23-3

1

10K_0402_5%

12

NC

AMP_OFF# EC_MUTE#

19

8

LOUT-

14

4

18

1

GND

11

GND

13

GND

20

GND

21

GND

10

R956

@

3

EXT_MIC_L<42>

EXT_MIC_R<42>

HP_OUTR<42>

HP_OUTL<42>

1 2

R957

20mil

1

C695

4.7U_0805_10V4Z

2

MIC_JD<42>

1 2

0_0402_5%

SPK_L1-

SPK_R1-

SPK_L2+

SPK_R2+

EXT_MIC_L

47P_0402_50V8J

EXT_MIC_R

47P_0402_50V8J

MIC_JD

HP_OUTR

HP_OUTL

FBMA-L10-160808-121LMT_2P

1

C676

2

GNDA

FBMA-L10-160808-121LMT_2P

1

C682

2

GNDA

R954

@R954

@

1K_0402_5%

SPDIF_OUT<42>

L37

1 2

L40

1 2

12

GNDA

PLUG_IN<42>

SPDIF_OUT

220P_0402_50V7K

EC_MUTE# <45>

2

EXT_MIC_L-2

1

C677

@C677

@

10P_0402_50V8J

2

GNDA

EXT_MIC_R-2

1

C683

@C683

@

10P_0402_50V8J

2

GNDA

220P_0402_50V7K

12

R955

@R955

@

1K_0402_5%

L41

1 2

FBMA-L10-160808-121LMT_2P

FBMA-L10-160808-121LMT_2P L42

L42

1 2

FBMA-L10-160808-121LMT_2P

+5VS

12

C688

PLUG_IN

1

C68410P_0402_50V8J@C68410P_0402_50V8J

@

2

GNDA

C685

1 2

PR-OUT

PL-OUT

1

C687

0.1U_0402_16V4Z

2

EXT_MIC_L-2

EXT_MIC_R-2

2

3

D69

D69 ZEN ROW PJDLC05C 3P C/A SOT23

ZEN ROW PJDLC05C 3P C/A SOT23

@

1

ESD request

Audio Jack

MIC IN

JMIC1

1 2 6 7 3

GNDAGNDA

220P_0402_50V7K

1 2

+5VAMP +5VAMP

@ R962

@

4

5

SUYIN_010168FR006G576ZL

ME@

C686

Headphone

JHP1

1

2

3

4

5

6

DRIVE

7

IC

7

8

SINGA_2SJ-A373-H03

ME@

GAIN0 GAIN1 0 0 6dB 0 1 10dB 1 0 15.6dB 1 1 21.6dB

R962

100K_0402_1%

1 2

R965

100K_0402_1%

1 2

1

GND

GND GND

GND

GND GND

R963

100K_0402_1%

1 2

GAIN1GAIN0

R966

100K_0402_1%

@

1 2

8 9 10

9 10

Security Classification

2008/03/25 2008/04/

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/25 2008/04/

3

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

AMP,Audio speaker CONN

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

LA-6882P

1

43 63W ednesday, October 06, 2010

of

0.2

CyberForum.ru

5

D D

DEVICE_RST#<19,37,38>

BUF_PLT_RST#<18,23,37,38,45,49>

CLK_PCIE_CARD_PCH#<15>

CLK_PCIE_CARD_PCH<15>

PCIE_PTX_C_DRX_N5<15> PCIE_PTX_C_DRX_P5<15>

PCIE_PRX_DTX_N5<15>

C C

B B

FAST_BOOT#<37,38,45>

A A

PCIE_PRX_DTX_P5<15>

BUF_PLT_RST#<18,23,37,38,45,49>

BUF_PLT_RST# CARD_RST#

FAST_BOOT#

Q20

2N7002_SOT23-3

@

R970

100_0402_5%

0.1U_0402_16V4Z

Reserve RC for old IC ESD problem JMB389 has internal RC.

+5VS

12

@

R266

R266 33K_0402_5%

33K_0402_5%

13

D

2

G

S

DEVICE_RST#

BUF_PLT_RST#

C698 0.1U_0402_10V 7KC698 0.1U_0402_10V 7K C699 0.1U_0402_10V 7KC699 0.1U_0402_10V 7K

X7R type

12

@

1

C704

2

+3VS

2

C290

0.1U_0402_16V4Z

1

@

12 12

2.2U_0603_6.3V6K

R973

0_0603_5%

D

1 3

1

2

1 2

R1344 0_0402_5%R1344 0_0402_5%

CPPE#<15>

12

Q19

S

AO3414_SOT23-3

G

@

2

MC74VHC1G08DFT2G SC70 5P

3

G

A

4

Y

B

P

@

U9

5

+3VS

CLK_PCIE_CARD_PCH# CLK_PCIE_CARD_PCH

PCIE_PRX_C_DTX_N5 PCIE_PRX_C_DTX_P5

R968

1 2

12K_0402_1%

1

C702

2

+CRD_POWER

4

CARD_RST#

U35

3

APCLKN

4

APCLKP

9

APRXN

8

APRXP

11

APTXN

12

APREXT

(12mil)

GND MDIO10

XD_CD#

MS_CD# SD_CD#

APTXP

7

APREXT

43

SDDV/MDIO4

39

TXIN/NC

1

XRSTN

2

XTEST

13

CPPE_N

14

CR1_CD2N

15

CR1_CD1N

16

CR1_CD0N

17

CR1_PCTLN

21

CR1_LEDN

JMB389-LGAZ0C_LQFP 48_7X7

JMB389

NC/TAV33

G/MDIO6

NC/SPI_SCK NC/SPI_CSN

NC/SPI_SO

NC/SPI_SI

LQFP48 Package

+3VS_CARD

APVDD

APV18

DV33 DV33 DV33 DV18 DV18

MDIO0 MDIO1 MDIO2 MDIO3

MDIO6/4

MDIO5

MDIO7 MDIO8

MDIO9 MDIO10 MDIO11 MDIO12 MDIO13 MDIO14

APGND

NC/GND NC/GND NC/GND

3

+CRD_POWER

1

C696

10U_0805_10V4Z

Close to CONN.

5 10 36

19 20 44 18 37

48 47 46 45 41 42 24 40 29 28 27 26 25 23 22

30 33 34 35

6 31 32 38

MDIO0 MDIO1 MDIO2 MDIO3 MDIO4 MDIO5_R MDIO6 MDIO7 MDIO8 MDIO9

MDIO11 MDIO12 MDIO13 MDIO14

(20mil)

(40mil)

(20mil)

Close to IC

1 2

0_0402_5%

1 2

0_0402_5%

1 2

0_0402_5%

+1.8VS_CARD

+3VS_CARD

+1.8VS_CARD

R969

R1014

R1029

108mA

45mA

SD_CLK

MS_CLK

XD_CLK

C705

2

1

C697

2

0.1U_0402_16V4Z

1

C706

2

@

0.1U_0402_16V4Z

Close to pin10

Close to pin5->1000P->0.1u->10u

XD_CD#

SD_CD#

0.1U_0402_16V4Z

(20mil)

600mA

1

2

1000P_0402_50V7K

C715

@

2

MDIO0 MDIO1 MDIO2 MDIO3 MDIO8 MDIO9 MDIO10

MDIO4 MDIO6 MDIO14 XD_CD# MDIO13 MDIO12 XD_CLK MDIO7

C707

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

JREAD1

22

XD-VCC

30

XD10-D0

29

XD11-D1

28

XD12-D2

27

XD13-D3

26

XD14-D4

25

XD15-D5

24

XD16-D6

23

XD17-D7

33

XD07-WE

32

XD08-WP

34

XD06-ALE

39

XD01-CD

38

XD02-R/B

37

XD03-RE

36

XD04-CE

35

XD05-CLE

31

XD GND

40

XD GND

41

SD CD/WP G ND

42

SD CD/WP G ND

T-SOL_144-1300002600_NR

ME@

SD_CLK

R1009

100_0402_5%

R1036

R1051

100_0402_5%

MS_CLK

XD_CLK

Close to connector for EMI request.

+1.8VS_CARD

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

Close to pin 37

1

2

C708

2

10U_0805_10V4Z

C716

@

@R1009

@

@R1036

@

@R1051

@

MDIO6

MDIO13

C709

12

SD4-VDD MS9-VCC

SD5-CLK SD7-DAT0 SD8-DAT1 SD9-DAT2 SD1-DAT3

SD2-CMD

SD6-VSS

SD3-VSS

MS8-SCLK MS4-DAT A0 MS3-DAT A1 MS5-DAT A2 MS7-DAT A3

MS6-INS

MS1-VSS

MS10-VSS

@

C703

1 2

100P_0402_50V8J

@

C765

1 2

100P_0402_50V8J

@

C821

1 2

100P_0402_50V8J

+1.8VS_CARD

1

2

R971

1 2

1K_0402_5%

R972

1 2

1K_0402_5%

SD-CD

SD-WP

MS2-BS

1

C710

10U_0805_10V4Z

2

Close to pin 18

11 18

9 4 3 21 19 16 1 2

6 13

17 10 8 12 15 14 7 5 20

+CRD_POWER

(20mil)

SD_CLK MDIO0 MDIO1 MDIO2 MDIO3 MDIO4 SD_CD#MDIO11 MDIO6

MS_CLK MDIO0 MDIO1 MDIO2 MDIO3 MS_CD# MDIO4

C711

@

Close to pin 19,20

1

+CRD_POWER

C701

1

2

0.1U_0402_16V4Z

(20mil)

1

2

0.1U_0402_16V4Z

+3VS_CARD

1

C712

2

0.1U_0402_16V4Z

Close to pin 44

1

C700

2

0.1U_0402_16V4Z

1

C713

2

0.1U_0402_16V4Z

Close to pin 36

C714

1

2

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Doc ument Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Carder JMB389

LA-6882P

1

44 63Wednesday, October 06, 2010

of

0.2

CyberForum.ru

L43

+3VALW +EC_AVCC

+3VALW

1 2

FBM-11-160808-601-T_0603

1 2

R978 47K_0402_5%R978 47K_0402_5%

KSO[0..17]<46>

KSI[0..7]<46>

R983 47K_0402_5%R983 47K_0402_5%

R984 47K_0402_5%R984 47K_0402_5%

C721

0.1U_0402_16V4Z

1 2

L44 FBM-11-160808-601-T_0603L44 FBM-11-160808-601-T_0603

12

C726 22P_0402_50V8J@C726 22P_0402_50V8J@

C725

0.1U_0402_16V4Z

KSO[0..17]

KSI[0..7]

1 2

1

2

1

ECAGND

KB_RST#<19>

2

1

2

R976 10_0402_5%@R976 10_0402_5%@

KSO1

KSO2

C722

1000P_0402_50V7K

12

ENE UPDATE 08/10/21

EC_SMB_CK2 EC_SMB_DA2

CPU1.5V_S3_GATE<10>

2

@

1

32.768KHZ_12.5PF_1TJS125DJ4A420P

+3VALW

EC_RTCX1

SUSCLK_R

C733

@

15P_0402_50V8J

R986

2.2K_0402_5%

R990

2.2K_0402_5%

CPU1.5V_S3_GATE

SUSCLK<16>

+3VS

R988

2.2K_0402_5%

1

@

C729

C729 100P_0402_50V8J

100P_0402_50V8J

2

+3VS

12

R992

10K_0402_5%

1 2

R1000 10M _0402_5%

@

1

C732

@

15P_0402_50V8J

4

Y5

IN

2

OUT

NC3NC

1

2

09/11 Unstuff

R989

2.2K_0402_5%

1

@

C730

C730 100P_0402_50V8J

100P_0402_50V8J

2

EC_TACH

EC_SMB_CK1

EC_SMB_DA1

+3VS

0.1U_0402_16V4Z

SG_SW_LED#<49>

EC_TX_P80_DATA<37,46> EC_RX_P80_CLK<37,46>

EC_FAN_PWM<40>

1 2

C717

LPC_FRAME#<14,37>

CLK_PCI_LPC<18>

BUF_PLT_RST#<18,23,37,38,44,49>

EC_SCI#<19>

EC_SMB_CK1<53> EC_SMB_DA1<53> EC_SMB_CK2<15,23,40,50> EC_SMB_DA2<15,23,40,50>

SLP_S3#<16> SLP_S5#<16>

EC_SMI#<19>

SUSWARN#<16>

INVT_PW M<34>

NUM_LED#<50>

12

R9960_0402_5% R9960_0402_5%

R1299

R1300

1

2

KSI3<46> KSI4<46>

ESB_CLK<50> ESB_DAT<50>

EC_TACH<40>

ODD_DA#<18,41>

ON/OFF#<50>

C718

0.1U_0402_16V4Z

C718

0.1U_0402_16V4Z

GATEA20<19>

SERIRQ<14>

LPC_AD3<14,37> LPC_AD2<14,37> LPC_AD1<14,37> LPC_AD0<14,37>

4.7K_0402_5%

+3VALW

C724

1000P_0402_50V7K

C724

C720

0.1U_0402_16V4Z

C720

0.1U_0402_16V4Z

C719

0.1U_0402_16V4Z

C719

0.1U_0402_16V4Z

1

2

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

EC_SMI#

ESB_CLK ESB_DAT SUSWARN#

EC_TACH ODD_DA# EC_TX_P80_DATA EC_RX_P80_CLK

EC_FAN_PWM

1

2

KB_RST#

LPC_AD3 LPC_AD2 LPC_AD1 BATT_TEMP LPC_AD0

EC_RST# EC_SCI#

INVT_PW M

EC_RTCX1

122

SUSCLK_R

123

1

C815

R139

20P_0402_50V8

2

1 2

100K_0402_5%

ESB_CLK

ESB_DAT

1000P_0402_50V7K

C723

1000P_0402_50V7K

C723

1000P_0402_50V7K

1

GA20/GPIO00

2

KBRST#/GPIO0 1

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LAD0

12

PCICLK

13

PCIRST#/GPIO0 5

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO0 8

16

LID_SW# /GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT# /GPIO0C

19

EC_PME#/GP IO0D

25

EC_THERM #/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO1 5

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LE D#/GPIO19

36

NUMLED# /GPIO1A

XCLK1 XCLK0

1

2

LPC & MISC

1

2

Int. K/B

Int. K/B Matrix

Matrix

SM Bus

+EC_AVCC

9

22

33

96

111

125

67

VCC

AVCC

INVT_PW M/PWM1/GPIO0F

BEEP#/PWM2/GPIO10

ACOFF/FANP WM2/GPIO13

PWM Output

BATT_TEM P/AD0/GPIO38

BATT_OVP/AD1/GPIO39

AD Input

DAC_BRIG/D A0/GPIO3C

EN_DFAN1 /DA1/GPIO3D

DA Output

PS2 Interface

11

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SPI Device Interface

SPI Flash ROM

FSTCHG/SEL IO#/GPIO50

BATT_CHGI_ LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO54

VR_ON/XCLK32K/GPIO57

EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04

ICH_PWROK/GPXO06

GPO

GPIO

PM_SLP_S4#/GPXID1

GPI

GND

AGND

GND

KB930QF A1 LQFP 128P

24

KB930QF A1 LQFP 128P

35

69

94

113

ECAGND

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U36

FANPWM 1/GPIO12

ADP_I/AD2/GP IO3A

AD3/GPIO3B AD4/GPIO42

SELIO2#/AD5/GP IO43

IREF/DA2/GPIO3 E

DA3/GPIO3F

PSCLK1/GPIO4 A PSDAT1/GPIO4 B PSCLK2/GPIO4 C

PSDAT2/GPIO4 D

SDICS#/GPXOA00 SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

CAPS_LED #/GPIO53

SUSP_LED #/GPIO55

SYSON/GPIO56

AC_IN/GPIO59

EC_ON/GPXO05

EC_SWI#/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10 GPXO11

ENBKL/GPXID2

GPXID3 GPXID4 GPXID5 GPXID6 GPXID7

V18R

TP_LED#

21

BEEP#

23

LED_KB_PWM_R

26

ACOFF

27

63 64 65 66

BRDID

75 76

EC_BATT

68

FAST_BOOT#

70

IREF

71 72

83

USB_ON#

84

ESB_INT

85 86

TP_CLK

87

TP_DATA

88

97

TV_POWER_OFF#

98 99

LID_SW#

109

FRD#SPI_SO

119

FWR#SPI_SI

120

SPI_CLK

126

FSEL#SPICS#

128

73

H_PECI_R

74 89

CHARGE_LED0#

90

CAPS_LED#

91 92

CHARGE_LED1#

93

SYSON

95 121

ACIN

127

100

EC_LID_OUT#

101

EC_ON

102 103

PCH_POK_EC PCH_POK

104

BKOFF#

105

RF_LED#

106 107 108

110 112 114

NOVO#

115

SUSP#

116

PBTN_OUT#

117 118

124

1

C731

4.7U_0805_10V4Z

2

2007/10/15 2008/10/15

TP_LED# <47> BEEP# <42>

ACOFF <52,54>

BATT_TEMP <53>

SG_SW# <49>

ADP_I <53,54>

IMVP_IMON < 60>

SPI_SB_CS0#_REC_SB_CS0#

12

R13470_0402_5%@R13470_0402_5%

@

EC_BATT <50>

FAST_BOOT# <37,38,44> IREF <54> CHGVADJ <54>

EC_MUTE#

EC_MUTE# <43>

USB_ON# <48,49>

ESB_INT <50>

CMOS_OFF# <34>

TP_CLK <46>

TP_DATA <46>

ACOVER_OFF# <50>

TV_POWER_OFF# <37>

ME_FLASH <14>

LID_SW# <46>

FRD#SPI_SO <47>

FWR#SPI_SI <47>

SPI_CLK <47>

FSEL#SPICS# <47>

R991 43_0402_1%R991 43_0402_1%

H_PROCHOT#_EC

1 2

FSTCHG <54>

CHARGE_LED0# <47>

CAPS_LED# <50> PWR_LED# <47,50>

CHARGE_LED1# <47>

SYSON <49,51,56> VR_ON <60> ACIN <16,54>

EC_RSMRST# <16> EC_LID_OUT# <15> EC_ON <50,55>

ESB_RST# <50>

BKOFF# <34> RF_LED# <47> PCH_APWROK <16> SA_PGOOD <57>

SLP_S4# <16>

ENBKL <34>

EAPD <42>

NOVO# <50>

SUSP# <10,51,56,57,58,59>

PBTN_OUT# <16>

Compal Secret Data

Deciphered Date

1 2

R1341 0_0402_5%R1341 0_0402_5%

1 2

R1333 0_0402_5%

@

SPI_SB_CS0#_R <14>

ESB_INT

R979 10K_0402_5%R979 10K_0402_5%

1 2

H_PECI <6,19>

USB_ON#

FRD#SPI_SO

FSEL#SPICS#

D46 RB751V_SOD323

+3VALW

@

1 2

R993 0_0402_5%R993 0_0402_5%

R980 10K_0402_5%R980 10K _0402_5%

LED_KB_PWM <50>

PCH_DPWROK <16>

+3VS

12

R1298

R1298 10K_0402_5%

10K_0402_5%

1 2

12

R985100K_0402_1% @ R985100K_0402_1%@

12

R987100K_0402_1% @ R987100K_0402_1%@

H_PROCHOT#_EC

21

R994 10K_0402_5%

+3VALW

R974

R974 10K_0402_5%

10K_0402_5%

1 2

BRDID

R977

@

10K_0402_5%

1 2

6/19 Add BRDID

+3VS

12

R975

R975 10K_0402_5%

+3VALW

VR_HOT#

1 2

PCH_POK <16>

@

+3VS

10K_0402_5%

EC_PME#

Title

Size Document Number Rev

Custom

Date: Sheet

EC_FAN_PWM

TP_CLK

TP_DATA

BATT_TEMP

ACIN

R1286

0_0402_5%

12

+3VALW

R995

1 2

Q91

2N7002_SOT23

Compal Electronics, Inc.

BIOS & EC I/O Port

10K_0402_5%

@

R981 4.7K_0402_5%R981 4.7K_0402_5%

1 2

R982 4.7K_0402_5%R982 4.7K_0402_5%

1 2

C727 100P_0402_50V8JC727 100P_0402_50V8J

1 2

C728 100P_0402_50V8JC728 100P_0402_50V8J

R1285

0_0402_5%

12

R9970_0402_5% R9970_0402_5%

12

R9990_0402_5%@ R9990_0402_5%@

D

S

D

S

1 3

@

G

2

+3VALW

LA-6882P

45 63Wednesday , October 06, 2010

+5VS

H_PROCHOT# <6>VR_HOT#<53,60>

LAN_WAKE# <38>

PCI_PME# <18>

of

0.2

CyberForum.ru

5

INT_KBD Conn.

1 2

KSI[0..7] <45>

KSO[0..17] <45>

KSO1

KSO7

KSI2

KSO5

KSI3

KSO14

KSI7

KSI6

KSI5

KSI4

KSO9

KSI1

D D

C C

KSO[0..17]

KSO2

C734 100P_0402_50V8J@C734 100P_0402_50V8J@

KSO15

C736 100P_0402_50V8J@C736 100P_0402_50V8J@

KSO6

C738 100P_0402_50V8J@C738 100P_0402_50V8J@

KSO8

C740 100P_0402_50V8J@C740 100P_0402_50V8J@

KSO13

C742 100P_0402_50V8J@C742 100P_0402_50V8J@

KSO12

C744 100P_0402_50V8J@C744 100P_0402_50V8J@

KSO11

C746 100P_0402_50V8J@C746 100P_0402_50V8J@

KSO10

C748 100P_0402_50V8J@C748 100P_0402_50V8J@

KSO3

C750 100P_0402_50V8J@C750 100P_0402_50V8J@

KSO4

C752 100P_0402_50V8J@C752 100P_0402_50V8J@

KSI0

C754 100P_0402_50V8J@C754 100P_0402_50V8J@

KSO0

C756 100P_0402_50V8J@C756 100P_0402_50V8J@

CONN PIN define need double check

To TP/B Conn.

TP_RIGHT TP_LEFT

TP_DATA<45> TP_CLK<45>

CONN PIN define need double check

B B

TP_DATA TP_CLK

1

@

C761

C761 100P_0402_50V8J

100P_0402_50V8J

2

1

@

C762

C762 100P_0402_50V8J

100P_0402_50V8J

2

3

1

+5VS

2

@

D58

PACDN042Y3R_SOT23-3

4

C735 100P_0402_50V8J@C735 100P_0402_50V8J@

1 2

C737 100P_0402_50V8J@C737 100P_0402_50V8J@

1 2

C739 100P_0402_50V8J@C739 100P_0402_50V8J@

1 2

C741 100P_0402_50V8J@C741 100P_0402_50V8J@

1 2

C743 100P_0402_50V8J@C743 100P_0402_50V8J@

1 2

C745 100P_0402_50V8J@C745 100P_0402_50V8J@

1 2

C747 100P_0402_50V8J@C747 100P_0402_50V8J@

1 2

C749 100P_0402_50V8J@C749 100P_0402_50V8J@

1 2

C751 100P_0402_50V8J@C751 100P_0402_50V8J@

1 2

C753 100P_0402_50V8J@C753 100P_0402_50V8J@

1 2

C755 100P_0402_50V8J@C755 100P_0402_50V8J@

1 2

C757 100P_0402_50V8J@C757 100P_0402_50V8J@

1 2

8 7

6 5 4 3 2 1

C760

ACES_88058-060N

0.1U_0402_16V4Z

JP19

GND GND

6 5 4 3 2 1

ME@

3

KSO17 KSO16 KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

ACES_85201-3005N

ME@

2

JP5

1

EC DEBUG PORT

JP6

+3VALW EC_TX_P80_DATA<37,45> EC_RX_P80_CLK<37,45>

EC_TX_P80_DATA EC_RX_P80_CLK

1

2

3

4

ACES_85205-0400

ME@

Lid Switch

31

G1

32

G2

+3VALW

1 2

R1002 0_0402_5%R1002 0_0402_5%

C758

0.1U_0402_16V4Z

+VCC_LID

1

2

R1003 100K_0402_5%R1003 100K_0402_5%

1 2

2

5711ACDL-M3T1S SOT-23

VDD

3

OUTPUT

GND

U37

1

2

C759

10P_0402_50V8J

1

LID_SW# <45>

To TP Button/B Conn.

JP7

1

2

TP_RIGHT TP_LEFT

A A

5

2

3

4

5

GND

6

GND

JOINT_F1017WR-S-04P

ME@

4

Security Classification

2007/10/15 2008/10/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

KB /SW /LPC Debug Conn.

LA-6882P

46 63Wednesday, October 06, 2010

of

1

of

0.2

CyberForum.ru

FOR EC 128KB SPI ROM (150mil PACKAGE) P/N : SA00002C100

+3VALW

1

C763

0.1U_0402_16V4Z

2

FSEL#SPICS#<45>

R1006 15_0402_5%R1006 15_0402_5%

FRD#SPI_SO<45>

1 2

FSEL#SPICS#

20mils

U38

1 2 3 4

VCC

CS#

HOLD#

DO

CLK

WP#

DIO

GND

MX25L1005AMC-12G SOP

12

R1005

R1005 10K_0402_5%

10K_0402_5%

Changed to BEAD for EMI.

8

HOLD#FRD#SPI_SO SPI_SO

7 6 5

SPI_SI_EC

Close to EC.

R1007 FBM A-10-100505-101T 0402R1007 FBMA-10-100505-101T 0402

1 2

15_0402_5%

1 2

R1008

SPI_CLKSPI_CLK_R

FWR#SPI_SI

SPI_CLK <45>

FWR#SPI_SI <45>

LED

LED1

LED2

White

LED3

White

LED5

21

1

21

PWR_LED#<45,50>

CHARGE_LED1#<45>

Amber

CHARGE_LED0#<45>

White

WLAN_LED#<37>

RF_LED#<45>

TP_LED#<45>

BT_LED#

RB751V_SOD323

BATT_LOW_LED#

BATT_CHG_LED#

D47

D57

1 2

R1111 0_0402_5%R1111 0_0402_5%

@

21

@

21

12-21SYGCS530-E1S155TR8_W

3

2

12-22-S2ST3D-C30-2C_WHI-ORG

12-21SYGCS530-E1S155TR8_W

White

+5VALW

12

R1022

BT@ R1022

BT@

100K_0402_5%

1

OUT

BT_OFF#<19,37>

2

BT_LED#

IN

GND

3

1

OUT

GND

3

BT MODULE CONN

R1025

1 2

100K_0402_5%

BT@

Q92

Q92 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

BT@

Q94

Q94 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

@

2

IN

C775

0.1U_0402_16V4Z

1 2

BT@

+3VS

Q93 AO3413_SOT23-3

S

G

USB20_P13<18> USB20_N13<18>

BT_ACTIVE<37>

+3VS_BT

USB20_P13 USB20_N13 BTON_LED BT_ACTIVE

30mils

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z C776

C776

BT@

JP8

1

2

3

4

5

7

5

G1

6

8

6

G2

ACES_87213-0600G

ME@

D

13

BT@

2

12

+5VALW

R1010300_0402_5% R1010300_0402_5%

12

+5VALW

R1012470_0402_5% R1012470_0402_5%

12

R1013300_0402_5% R1013300_0402_5%

12

R1026300_0402_5% R1026300_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+5VS

Compal Secret Data

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

SPI_CLK_R

@

R330

0_0402_5%

C764

1 2

1

2

@

Colse to EC

10P_0402_50V8J

EMI

FD1FD11FD2FD2

1

B:H_4P2

H2

H1

HOLEAH2HOLEA

HOLEAH1HOLEA

1

A:H_3P8

H5

H6 HOLEAH6HOLEA

1

H7 HOLEAH7HOLEA

1

HOLEAH5HOLEA

1

C:H_3P0

H13

H12

HOLEA

1

D:H_3P0 E:H_3P0 F:H_3P0 G:H_3P0

H16

H20

H20 HOLEA

HOLEA

1

H16 HOLEA

HOLEA

1

H21

H21 HOLEA

HOLEA

1

H15

H15 HOLEA

HOLEA

1

H_2P8 H_2P8 H_3P0 H_4P5X3P0N

FD4FD4

FD3FD3

1

H4

H3

HOLEAH4HOLEA

HOLEAH3HOLEA

1

H10

H9

H8

HOLEAH9HOLEA

HOLEAH8HOLEA

1

H14

H14 HOLEA

HOLEA

1

H17

H17 HOLEA

HOLEA

1

H22

H22 HOLEA

HOLEA

1

H27

H26

HOLEA

1

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

H11

HOLEA

1

H18

H18 HOLEA

HOLEA

1

LED/EC SPI ROM/BT

H19

H19 HOLEA

HOLEA

1

H24

H24 HOLEA

HOLEA

1

LA-6882P

H25

H25 HOLEA

HOLEA

1

H23

H23 HOLEA

HOLEA

1

47 63Wednesday , October 06, 2010

0.2

of

CyberForum.ru

A

B

C

D

E

+USB_VCCB

OUT OUT OUT

OC#

+USB_VCCB+5VALW

8 7 6 5

U39

1

1 1

C767 0.1U_0402_16V4ZC767 0.1U_0402_16V4Z

12

USB_ON#<45,49>

USB_ON# USB_OC0#

GND

2

IN

3

IN

4

EN

APL3510BKI_SO8

Low Active

E-SATA COMBO LEFT USB PORT

1

C904

1000P_0402_50V7K@

2

USB_OC0# <18>

1

C780

C780 470P_0402_50V7K

470P_0402_50V7K

2

USB20_N0<18>

USB20_P0<18>

USB20_N0 USB20_N0_C

USB20_P0 USB20_P0_C

W=80mils

R1109 0_0402_5%R1109 0_0402_5%

1 2

R1108 0_0402_5%R1108 0_0402_5%

1 2

WCM-2012-900T_4P

4

1

L64

Light USB Conn.

3

2

@L64

@

USB20_N0_C USB20_P0_C

PJDLC05_SOT23-3

JUSB1

1

VBUS

2

D-

3

D+

4

GND1

2

3

D49

@

1

5

GND2

6

GND3

7

GND4

8

GND5

SUYIN_020133GR004M53CZL

ME@

OSCAN

(220uF_6.3V_5.9L_ESR17m)*1=(SF000001500)

+USB_VCCB

2 2

SATA_ITX_DRX_P4<14>

SATA_DTX_C_IRX_N4<14>

SATA_DTX_C_IRX_P4<14>

3 3

4 4

SATA_DTX_C_IRX_N4 SATA_DTX_C_IRX_P4

SATA_ITX_DRX_N4<14>

0.01U_0402_16V7K ESATA@

USB20_N1

USB20_P1 USB20_P1_C

4

1

+USB_VCCB

220U_6.3V_M

1

C769

+

2

WCM-2012-900T_4P

4

1

L65

@L65

@

3

PJDLC05_SOT23-3

3

2

USB20_N1

USB20_P1

2

1

3

2

W=80mils

470P_0402_50V7K

1

C770

2

ESATA@

C7710.01U_0402_16V7K

12

C772

12

USB20_N1_C

D50

@

USB20_N1<18>

USB20_P1<18>

SATA_ITX_DRX_P4 SATA_ITX_DRX_N4

SATA_DTX_IRX_N4 SATA_DTX_IRX_P4

SATA_ITX_DRX_P4 SATA_ITX_DRX_N4

SATA_DTX_IRX_P4 SATA_DTX_IRX_N4

R1106 0_0402_5%R1106 0_0402_5% R1107 0_0402_5%R1107 0_0402_5%

R1015 0_0402_5%ESATA@R1015 0_0402_5%ESATA@

1 2

R1016 0_0402_5%

1 2

R1017 0_0402_5%ESATA@R1017 0_0402_5%ESATA@

1 2

R1018 0_0402_5%

1 2

+3VS

R1019

@

4.7K_0402_5%

1 2

17 18 19 21

SN75LVCP412ARTJR_QFN20_4X4

ESATA and USB Conn.

1 2 1 2

SATA_ITX_DRX_P4_R

VCC VCC VCC

TX_0P

RX_1N RX_1P

D0 D1

SATA_ITX_DRX_N4_R

SATA_DTX_IRX_N4_R SATA_DTX_IRX_P4_R

6 10 16 20

9 8

15 14

12 11

ESATA@

ESATA_DET#<19>

U40

7

EN

1

RX_0P RX_0N2VCC

5

TX_1P

4

TX_1N

3

GND GND13TX_0N GND GND GND PAD

@

USB20_N1_C USB20_P1_C

+3VS

1

C773

@

2

0.1U_0402_16V4Z

SATA_ITX_DRX_P4_R SATA_ITX_DRX_N4_R

SATA_DTX_IRX_N4_R SATA_DTX_IRX_P4_R

JESAT1

1

VBUS

2

D-

3

D+

4

GND

5

GND

6

A+

7

A-

8

GND

9

B-

10

B+

11

GND

TAIW_EU131-117CRL-TW

2

C774

@

1

0.01U_0402_16V7K

USB

ESATA

SHIELD SHIELD SHIELD SHIELD

R1020

4.7K_0402_5%

@

1 2

R1023

R1023 0_0402_5%

0_0402_5%

@

1 2

USB A+ = RXP

A- = RXN

12 13 14 15

B- = TXN B+ = TXP

R1021

4.7K_0402_5%

@

1 2

R1024

R1024 0_0402_5%

0_0402_5%

@

1 2

Security Classification

2006/08/18 2007/8/18

Issued Date

THIS SHEE T OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEE T OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

Compal Secret Data

C

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

USB ports/E-SATA

LA-6882P

E

0.2

48 63Wednesday, October 06, 2010

CyberForum.ru

5

D D

C C

4

CLK_PCIE_USB30< 15> CLK_PCIE_USB30#<15>

PCIE_PRX_DTX_P4<15> PCIE_PRX_DTX_N4<15>

PCIE_PTX_C_DRX_P4<15> PCIE_PTX_C_DRX_N4<15>

PCIE_PRX_DTX_N4 PCIE_PRX_DTX_N4_R

3

USB30_SUB@

USB30_CLKREQ#<15> PCIE_WAKE#<16,37,38> SMIB<19>

BUF_PLT_RST#<18,23,37,38,44,45> SYSON<45,51,56>

SG_SW#<45> KILL_SW#<14>

SG_SW_LED#<45>

Close to Conn.

R1188 0_0402_5%

1 2

R1198 0_0402_5%

1 2

USB30_SUB@

R1288 0_0402_5%

1 2

R1291 0_0402_5%

1 2

USB30_SUB@

R1292 0_0402_5%

1 2

R1293 0_0402_5%

1 2

+1.5V

+3VALW

+5VS

+USB3_VCCA

Close to IC

CLK_PCIE_USB30_RCLK_PCIE_USB30 CLK_PCIE_USB30#_RCLK_PCIE_USB30#

PCIE_PRX_DTX_P4_RPCIE_PRX_DTX_P4

PCIE_PTX_C_DRX_P4_RPCIE_PTX_C_DRX_P4 PCIE_PTX_C_DRX_N4_RPCIE_PTX_C_DRX_N4

USB_ON# USB30_CLKREQ# PCIE_WAKE# SMIB BUF_PLT_RST# SYSON SG_SW# KILL_SW# SG_SW_LED#

2

JP18

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

ACES_85201-26051

G1

26

G2

ME@

1

27 28

09/30 Delete USB3.0 controller

10/04 Short J19 with JP18.

JP20

B B

+5VALW +USB3_VCCA

USB20@

C830

.1U_0402_16V7K

1 2

USB_ON#<45,48>

A A

USB_ON#

5

R1068

1 2

0_0402_5%

USB20@

U44

1

GND

2

IN

3

IN

4

EN

APL3510BKI_SO8

2A/Active Low

USB20@

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

J19

1 2

JOPEN

Issued Date

@

OUT OUT OUT OC#

8 7 6 5

4

W=60mils

R1073

1 2

USB20@

0_0402_5%

2007/1/15 2008/1/15

USB_OC1# <18>

Compal Secret Data

Deciphered Date

3

SG_SW#<45> KILL_SW#<14>

SG_SW_LED#<45>

+USB3_VCCA

USB20_P2<18>

USB20_N2<18>

USB20_P3<18>

USB20_N3<18>

+3VALW

+5VS

USB20_P2

USB20_N2

USB20_P3

USB20_N3

Title

Size Document Number Rev

Custom

Date: Sheet

2

JP20

16

15

14

13

12

GND

11

GND

10

9

8

7

6

5

4

3

2

1

ACES_85201-1605N

ME@

18 17

Compal Electronics, Inc.

USB Right Ports/ USB Brd Conn.

LA-6882P

49 63Wednesday, October 06, 2010

of

1

0.2

CyberForum.ru

ON/OFF switch

Power Button

TOP Side

Bottom Side

ON/OFFBTN#

EC_ON<45,55>

NOVO#<45>

51_ON#<52>

1

2

SW2

1 2

EC_ON

5

6

J7

SHORT PADS

1 2

NOVO#

51_ON#

3

4

SMT1-05_4P

D53

1

DAN202UT106_SC70-3

R1112

R1112 10K_0402_5%

10K_0402_5%

+3VALW

1 2

3

2

Q95

2N7002_SOT23-3

R1118

R1118 100K_0402_5%

100K_0402_5%

2

3

+3VALW

R1115

R1115 100K_0402_5%

100K_0402_5%

1 2

ON/OFF#

51_ON#

13

D

2

G

S

D56

1

DAN202UT106_SC70-3

NOVO_BTN#

Power Button Board Conn. 10pin

CAPS_LED#<45>

NUM_LED#<45>

HDD_LED#<14>

ON/OFF# <45>

51_ON# <52>

9/30 remove EC_SMB_CK2, EC_SMB_DA2

PWR_LED#<45,47>

NOVO_BTN# ON/OFFBTN#

2

3

D54

D54 PJSOT24C 3P C/A SOT-23

PJSOT24C 3P C/A SOT-23

@

1

EMI REQUEST 1ST = SCA00000E00

2ST = SCA00000R00

+5VALW +5VS

NOVO_BTN# ON/OFFBTN#

ME@

E&T_6701-Q12N-00R

12 11 10

14

12

G2 11 10

9

8

7

6

5

4

3

2

1

13

1

G1

JP10

Cap Sensor Board Conn. 8pin

ENE SB3534

+5VS

ESB_INT<45>

ESB_CLK<45> ESB_DAT<45>

+3VS

ESB_RST#<45>

10/05 Change to SM01000CY00, EMI request

J18

2

112

JUMP_43X39@

R1114 0_0402_5%R1114 0_0402_5%

1 2

R1117 0_0402_5%R1117 0_0402_5%

1 2

R1116 0_0402_5%R1116 0_0402_5%

1 2

J9

2

112

JUMP_43X39@J9JUMP_43X39@

@

C858

33P_0402_50V8J

FAN Lighting Conn. 2pin (For Y15 only)

+5VS

2

1

JP17

1

2

ACES_87212-02G0

ME@

+5VS_CAPB ESB_INT_R

ESB_CLK_R ESB_DAT_R

+3VS_CAPB

2

C859

33P_0402_50V8J

1

3

G1

4

G2

JP9

1

2

3

4

5

6

7

8

9

GND

10

GND

ACES_85201-08051

ME@

A Cover Lighting CONN. 8pin (For Y15 only)

(20 MIL) (20 MIL)

+5VALW

R437100K_0402_5%

ACOVER@

ACOVER_OFF#<45>

1

2

IN

3

USB20_N10<18> USB20_P10<18>

EC_SMB_CK2<15,23,40,45> EC_SMB_DA2<15,23,40,45>

R436

R436 150K_0402_5%

150K_0402_5%

ACOVER@

OUT

GND

Q109

Q109 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

ACOVER@

IR CONN. 6pin (For Y15 only)

+5VS

USB20_N8<18> USB20_P8<18>

J17

2

JUMP_43X39@

USB20_N8 USB20_P8

EC_BATT<45>

S

G

Q110

2

SI2301BDS-T1-E3_SOT23-3

ACOVER@

4.7V

1

ACOVER@

C521

0.1U_0402_16V4Z

2

112

ACES_87213-0600G

USB20_N10

USB20_P10

EC_SMB_CK2 EC_SMB_DA2

D

13

JP16

1

2

3

4

5

G1

6

G2

ME@

+COVER_LIGHT

1

ACOVER@

C526

0.1U_0402_16V4Z

2

7 8

JP13

1

GND

2

3

4

5

6

7

8

GND

ACES_87213-0800G

ME@

+COVER_LIGHT

1

ACOVER@

C522

10U_0805_10V4Z

2

9

KB Lighting CONN.4pin

10

+VCC_KB_LED

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

JP12

1

2

3

4

5

GND

6

GND

JOINT_F1017WR-S-04P

ME@

LED_KB_PWM<45>

Compal Secret Data

2008/03/25 2008/04/

Compal Secret Data

+5VS +VCC_KB_LED

12

R937

R937 10K_0402_5%

10K_0402_5%

KBL@

1 2

1

OUT

2

IN

GND

Q111

Q111 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

3

KBL@

Deciphered Date

R1120

100K_0402_5%

KBL@

Q112

S

D

13

AO3413_SOT23-3

G

KBL@

2

C689

0.01U_0402_16V7K

1 2

KBL@

Compal Electronics,Ltd.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics,Ltd.

1

C693

0.1U_0402_16V4Z

2

KBL@

1

C690

C690 10U_0805_10V4Z

10U_0805_10V4Z

2

KBL@

other IO connector

LA-6882P

KBL@

0.2

50 63W ednesday, October 06, 2010

of

CyberForum.ru

A

+5VALW

U46

8

D

1

C836

C836 10U_0805_10V4Z

2

G

+VSB

13

D

S

2

R1085

R1085 20K_0402_5%

20K_0402_5%

10U_0805_10V4Z

Q99

Q99 2N7002_SOT23

2N7002_SOT23

1 1

7

D

6

D

5

D

DMN3030LSS-13_SOP8L-8

5VS_GATE_R

R1088

12

10K_0402_5%

1

S

2

S

3

S

4

G

+5VS

1

C837

C837 10U_0805_10V4Z

10U_0805_10V4Z

2

1

C842

0.1U_0603_25V7K

2

1

C838

C838 1U_0603_10V4Z

1U_0603_10V4Z

2

12

R1113

R1113 470_0603_5%

470_0603_5%

@

13

D

S

B

SUSP

2

G

Q96

Q96 2N7002_SOT23

2N7002_SOT23

@

+3VALW TO +3VS+5VALW TO +5VS

SUSP

2

G

1

C839

C839 10U_0805_10V4Z

10U_0805_10V4Z

2

+VSB

12

R1086

R1086 47K_0402_5%

47K_0402_5%

13

D

Q100

Q100 2N7002_SOT23

2N7002_SOT23

S

+3VALW

U47

8

S

D

7

S

D

6

S

D

5

G

D

DMN3030LSS-13_SOP8L-8

R1089

R1089 0_0402_5%

0_0402_5%

@

1 2

C

+3VS

1 2

1 3 4

2

1

C843

0.1U_0603_25V7K

2

C840

C840 10U_0805_10V4Z

10U_0805_10V4Z

1

C841

C841 1U_0603_10V4Z

1U_0603_10V4Z

2

12

R1084

R1084 470_0603_5%

470_0603_5%

@

13

D

S

SUSP

2

G

Q97

Q97 2N7002_SOT23

2N7002_SOT23

@

D

+1.5V to +1.5VS

+3VALW

12

100K_0402_5%

100K_0402_5% R1087

R1087

Q101

13

D

2

G

2N7002_SOT23

D

S

SUSP#SUSP

1

C856

C856 10U_0805_10V4Z

10U_0805_10V4Z

2

R1090

R1090 0_0402_5%

0_0402_5%

+1.5V

SI2301BDS-T1-E3_SOT23-3

12

0.1U_0603_25V7K

+1.5VS

S

D

13

Q120

G

2

1.5VS_GATE5VS_GATE

1

C844

2

E

7/26 change SI4800 to SI2301

1

C857

C857 10U_0805_10V4Z

10U_0805_10V4Z

2

1

C845

0.1U_0603_25V7K

2

1

C835

C835 1U_0603_10V4Z

1U_0603_10V4Z

2

12

R1119

R1119 470_0603_5%

470_0603_5%

@

13

D

Q98

S

2N7002_SOT23

@

SUSP

2

G

+1.5V +1.05VS_VGA+1.8VS +0.75VS

12

R1091

R1091 470_0603_5%

470_0603_5%

2 2

@

13

D

2

G

Q102

S

2N7002_SOT23

@

12

R1092

R1092 470_0603_5%

470_0603_5%

@

13

D

S

SYSON# SUSP SUSPSUSP

2

G

Q103

Q103 2N7002_SOT23

2N7002_SOT23

@

12

R1093

R1093 470_0603_5%

470_0603_5%

@

13

D

S

2

G

Q104

Q104 2N7002_SOT23

2N7002_SOT23

@

12

R1094

R1094 22_0603_5%

22_0603_5%

13

D

S

2

G

Q105

Q105 2N7002_SOT23

2N7002_SOT23

+1.05VS

12

13

D

S

R1095

R1095 470_0603_5%

470_0603_5%

@

SUSP

2

G

Q106

Q106 2N7002_SOT23

2N7002_SOT23

@

SUSP<6,10,57>

SUSP#<10,45,56,57,58,59> SYSON<45,49,56>

SUSP

DTC124EKAT146_SC59-3

For Intel S3 Power Reduction.

+5VALW

12

R1103

2

G

R1103 100K_0402_5%

100K_0402_5%

OPTI@

DGPU_PWR_EN#

13

D

Q113

Q113 2N7002_SOT23

2N7002_SOT23

OPTI@

S

DGPU_PWR_EN# <25>

3 3

R1104

R1104 0_0402_5%

0_0402_5%

DGPU_PWR_EN<18,23,57,58,59>

OPTI@

12

R1105

R1105 100K_0402_5%

100K_0402_5%

OPTI@

12

R1096

R1096 100K_0402_5%

100K_0402_5%

Q107

2

IN

+5VALW+RTCVCC

12

1

3

@

R1097

R1097 100K_0402_5%

100K_0402_5%

OUT

GND

100K_0402_5%

SYSON#

DTC124EKAT146_SC59-3

SYSON

+5VALW

12

@

R1098

Q108

1

@

OUT

2

IN

GND

3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CON SENT OF COMPAL ELE CTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CON SENT OF COMPAL ELE CTRONICS, INC.

2006/08/18 2007/8/18

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

DC Interface

LA-6882P

51 63Wednesday, October 06, 2010

E

0.2

of

CyberForum.ru

5

4

3

2

1

DC030006J00

JDCIN1

1

2

D D

C C

B B

2

3

4

4602-Q04C-09R 4P P2.5

@

BATT+

51_ON#<43>

JRTC1

-+

ML1220T13RE

45@

PF101

7A_24VDC_429007.WRML

PD103

LL4148_LL34-2

12

PR110

100K_0402_5%

PR111

22K_0402_5%

1 2

+RTCBATT

12

21

PC105

APDIN1APDIN

N1

12

0.22U_0603_25V7K

+RTCBATT

12

PC101

PQ101

TP0610K-T1-E3_SOT23-3

PR117

560_0603_5%

1 2

2

51_ON-2

SMB3025500YA_2P

12

1000P_0402_50V7K

CHGRTC-1

PL101

1 2

100P_0402_50V8J

PC102

13

PR118

560_0603_5%

1 2

VIN

PD101

PD101 LL4148_LL34-2

LL4148_LL34-2

1 2

51_ON-1

12

PR101

PR101 68_1206_5%

68_1206_5%

12

PC106

0.1U_0603_25V7K

12

100P_0402_50V8J

PC103

12

PR109

PR109 68_1206_5%

68_1206_5%

+CHGRTC

1 2

PD106

RB751V-40_SOD323-2

12

+3VLP

PR102

PR102 1K_1206_5%

PC104

1000P_0402_50V7K

VS

VIN

1K_1206_5%

1 2

PR103

PR103 1K_1206_5%

1K_1206_5%

1 2

PR104

PR104 1K_1206_5%

1K_1206_5%

1 2

PR107

PR107 1K_1206_5%

1K_1206_5%

1 2

ACOFF<39,47>

+5VALW<48>

VL

12

PR114

100K_0402_1%

PD105

MAINPW ON<46,48>

ACON

2

1

3

RB715F_SOT323-3@

12

VIN

Precharge detector

15.97V/14.84V FOR ADAPTOR

PreCHG

PQ103

PQ103 DDTC115EUA-7-F_SOT323-3

DDTC115EUA-7-F_SOT323-3

PD104

2

3

RB715F_SOT323-3

LM393DG_SO8

PRG-1

PC108

0.1U_0603_25V7K

6251VREF

1

PU101A

1

PD102

PD102 LL4148_LL34-2

LL4148_LL34-2

VS

8

P

+

O

G

4

PR119

34K_0402_1%

12

PR105

2

PR112

2.2M_0402_5%

12

PC107

@

3

2

-

12

100K_0402_1%

13

12

0.01U_0402_25V7K

PRG+

PRG-

PC109

1000P_0402_50V7K

12

PR106

100K_0402_1%

PR121

66.5K_0402_1%

1 2

PQ102

PQ102 TP0610K-T1-E3_SOT23-3

TP0610K-T1-E3_SOT23-3

2

12

13

2

12

PR115

205K_0402_1%

PRG++

PQ105

2N7002W-T/R7_SOT323-3

13

D

2

G

S

13

PR108

100K_0402_1%

PQ104

PQ104 DDTC115EUA-7-F_SOT323-3

DDTC115EUA-7-F_SOT323-3

12

PR113

@

12

PR116

PR120

47K_0402_5%

13

PQ106

PQ106 DTC115EUA_SC70-3

DTC115EUA_SC70-3

2

499K_0402_1%

12

499K_0402_1%

12

B+

PC110

0.01U_0402_25V7K

PACIN <47>

+5VALW

ACIN

Precharge detector Min. typ. Max.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

L-->H 14.991V 15.381V 15.782V H-->L 13.860V 14.247V 14.621V

Compal Secret Data

2010/01/25 2010/12/31

Compal Secret Data

Deciphered Date

2

BATT ONLY

Precharge detector

Min. typ. Max. L-->H 7.196V 7.349V 7.505V H-->L 6.138V 6.214V 6.056V

Compal Electronics, Inc.

Title

PWR DCIN / Vin Detector /Pre-charge

Size Document Number Rev

Custom

Date: Sheet

PIQY0/Y1

0.1

52 63Wednesday , October 06, 2010

1

52 63Wednesday , October 06, 2010

0.1

of

CyberForum.ru

5

4

3

2

1

JBATT1

1

2

D D

C C

2

3

4

5

6

7

8

GND

9

GND

TYCO_1775789-1

@

EC_SMCA EC_SMDA TS

12

PR201

100_0402_1%

PR201

100_0402_1%

12

PR202

100_0402_1%

PR202

100_0402_1%

VMB2

PR213

PR213 649K_0402_1%

649K_0402_1%

PR215

10K_0402_1%

VMB2

1 2

PR216

B B

PR216 232K_0402_1%

232K_0402_1%

1 2

BATDE-3BATDE-4

1 2

PR208

6.49K_0402_1%

1 2

PR210

PR210 10K_0402_5%

10K_0402_5%

12

PC204

0.01U_0402_25V7K

5

6

BATDE-2

PR218

PR218 10K_0402_1%

10K_0402_1%

PF201

PF201 12A_65V_451012MRL

12A_65V_451012MRL

VS

5.1M_0402_5%

8

P

+

O

-

G

PU101B

LM393DG_SO8

4

12

21

PR214

1 2

BATDE-1

7

6251VREF

VMB

12

PC201

PC201 1000P_0402_50V7K

1000P_0402_50V7K

EC_SMB_CK1 <39>

EC_SMB_DA1 <39>

+3VALW

BATT_TEMP <39>

+3VALW

PR211

PR211 100K_0402_1%

100K_0402_1%

1 2

PL201

SMB3025500YA_2P

1 2

A/D

+3VALW

PR212

PR212 10K_0402_1%

10K_0402_1%

1 2

PQ202

13

D

2N7002KW_SOT323-3

2

G

S

BATT+

12

PC202

0.01U_0402_25V7K

BATT_OUT <47>

100K_0402_1%

SPOK<48>

PR220

VR_HOT#<53>

VL

1 2

0.1U_0603_25V7K

2N7002KW_SOT323-3@

PR221

PR221 1K_0402_5%

1K_0402_5%

1 2

PQ201

PC203

12

PC207

D

S

+3VALW

13

2

G

1U_0402_6.3V6K

PH201 under CPU botten side :

CPU thermal protection at 92 degree C Recovery at 56 degree C

12

VL

PU201

G718_OT2

PU201

1

VCC

2

GND

3

OT1

4

OT2

G718TM1U_SOT23-8

PR223

PR223 0_0402_5%

0_0402_5%

1 2

12

PR217

100K_0402_1%

8

TMSNS1

7

RHYST1

6

TMSNS2

5

RHYST2

TP0610K-T1-E3_SOT23-3

PC205

0.22U_0603_25V7K

G718_TMSN1

G718_RHYST1

G718_TMSN2

G718_RHYST2

10K_0402_1%

PQ203

2

1 2

PR224

12

PR206

100K_0402_1%@

2

G

B+

PR219

PR219 22K_0402_1%

22K_0402_1%

1 2

13

D

PQ204

2N7002W-T/R7_SOT323-3

S

PR222

1 2

3.92K_0402_1%

12

PH201

PH201 100K_0402_1%_TSM0B104F4251RZ

100K_0402_1%_TSM0B104F4251RZ

PR209

19.6K_0402_1%

1 2

13

12

0.1U_0603_25V7K

+VSBP

ADP_I <39,47>

12

PR204

PR204 10K_0402_1%

10K_0402_1%

PR207

9.76K_0402_1%

1 2

+VSBP

PC206

VL

1 2

PJ201

PJ201 JUMP_43X39@

JUMP_43X39@

112

PR205

PR205 100K_0402_1%@

100K_0402_1%@

MAINPWON <45,48>

2

+VSB

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/01/25 2010/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR-BATTERY CONN/OTP

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

2

Date: Sheet

PIQY0/Y1

1

53 63Wednesday , October 06, 2010

0.1

of

CyberForum.ru

5

PQ301

PQ301 AO4407A_SO8

AO4407A_SO8

DTA144EUA_SC70-3

200K_0402_5%

13

2

PQ308A

PACIN

PQ313

DTC115EUA_SC70-3

ACOFF-1

1 2

8 7

5

PQ304

2

1 3

PQ306

DTC115EUA_SC70-3

PR319

47K_0402_1%

1 2

2

12

PR327

PR327 0_0402_5%

0_0402_5%

PQ315

13

D

2

G

S

4

2N7002KW_SOT323-3

VIN

D D

C C

B B

BATT_ON

ACOFF<39,45>

BATT_OUT<46>

12

PR301

61

2N7002KDW-2N _SOT363-6

2

PACIN<45>

PR325

PR325 10K_0402_1%

10K_0402_1%

P2

1 2 36

12

PR304

PC301

200K_0402_1%

0.1U_0603_25V7K

P2-1

12

PR314

P2-2

34

5

13

IREF<39>

PQ302

AO4407A_SO8

1 2 3 6

4

12

PC302

@

0.1U_0603_25V7K

61

2

PQ305A

PQ305A 2N7002KDW-2N _SOT363-6@

2N7002KDW-2N _SOT363-6@

12

PR313

PR313 10K_0402_1%

10K_0402_1%

13

D

2

G

150K_0402_1%

S

PQ309

2N7002KW_SOT323- 3

PQ308B

PQ308B 2N7002KDW-2N _SOT363-6

2N7002KDW-2N _SOT363-6

0.01U_0402_25V7K

ADP_I<39,46>

PR328

154K_0402_1%

PR331

100K_0402_1%

FSTCHG<39>

Connect to EC A/D Pin.

CHGVADJ=(Vcell-4)/0.10627

Vcell

4V

4.2V

4.35V

CC=0.25A~3A

IREF=1.016*Icharge

IREF=0.254V~3.048V

CHGVADJ

0V

1.882V

3.2935V

65W Adapter Vaclim=2.39*(1.96K/(1.96K+16.9K))=0.2484V Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05) where Vaclim=0.2484V, Iinput=2.76A

90W Adapter Vaclim=2.39*(2.87K/(2.87K+16.9K))=0.347V Iinput=(1/0.015)((0.05*Vaclim)/2.39+0.05) where Vaclim=0.347V, Iinput=3.82A

VCHLIM need over 95mV

120W Adapter

A A

Vaclim=2.39*(1K/(1K+50K))=0.047V Iinput=(1/0.01)((0.05*Vaclim)/2.39+0.05) where Vaclim=0.047V, Iinput=5.1A

65W : PR330=16.9K, PR333=1.96K 90W : PR330=16.9K, PR333=2.87K 120W : PR330=50K, PR333=1K

5

8 7

5

VIN

PR303

@PR303

@

47K_0402_1%

1 2

PQ305B

PQ305B 2N7002KDW-2N _SOT363-6@

2N7002KDW-2N _SOT363-6@

34

5

BATT_OUT <46>

PC315

6251_VCOMP-1

1 2

12

PC320

0.01U_0402_25V7K

CHGVADJ<39>

4

P3

65W:0.020 = SD00000S100 90W:0.015 = SD00000DL00 120W:0.01 = SD00000K810

0.01_1206_1%

1

2

BATT_OUT <46>

PR311

0_0402_5%

FSTCHG

12

4

12

PR315

PC313 6800P_0402_25V7KPC313 6800P_0402_25V7K

1 2

PR321 10K_0402_1%PR321 10K_0402_1%

1 2

PC316

0.1U_0402_16V7K

6251VREF

PR334

15.4K_0402_1%

1 2

PR302

12

100K_0402_1%

1 2

PR323

PR323 100_0402_1%

100_0402_1%

6251VREF

PR330

PR330 51K_0402_1%

51K_0402_1%

1 2

PR333

1K_0402_1%

31.6K_0402_1%

3

B+

PJ301

VIN

PR306

1 2 12

14.3K_0402_1%

PC309

0.1U_0603_25V7K

6251_DCIN

6251_CSON

12

6251_CSOP

6251_CSIN

PC314

0.1U_0402_16V7K

6251_CSIP

1 2

LX_CHG

DH_CHG

BST_CHG

6251_VDDP

DL_CHG

12

PR340

PR340 10K_0402_1%

10K_0402_1%

13

3

2

112

JUMP_43X118@

PreCHG

12

PR307

PR307 191K_0402_1%

191K_0402_1%

191K_0402_1%@

12

PR312

12

ACPRN <48>

20_0402_5%

1 2

PC312

0.047U_0402_16V7K

1 2

PR318

20_0402_5%

1 2

2_0402_5%

PR329

0_0603_5%

1 2

12

PC322

4.7U_0805_6.3V6K

PR338

10K_0402_1%

1 2

PACIN

12

PR343

14.3K_0402_1%

ACSETIN

12

PC307

PC307 1000P_0402_25V8J

1000P_0402_25V8J

PR317

12

PR320

PR320 20_0402_5%

20_0402_5%

PR322

PC317

0.1U_0603_25V7K

BST_CHGA

12

PD304

PD304 RB751V-40TE17_SOD323-2

RB751V-40TE17_SOD323-2

1 2

PR332

4.7_0402_5%

Compal Secret Data

12

6251_VDD

ACIN <16,24,39>

Deciphered Date

4

3

CSIP

PD301

6251_VDD

PC308

2.2U_0603_6.3V6K

ACSETIN

6251_EN CSON

CELLS

6251_ICOMP

6251_VCOMP

6251_ICM

6251_CHLIM

6251_ACLIM

12

PR335

ACPRN<48>

1 2

6251_VADJ

12

PU301

1

VDD

2

ACSET

3

EN

4

CELLS

5

ICOMP

6

VCOMP

7

ICM

8

VREF

9

CHLIM

10

ACLIM

11

VADJ

12

GND

ISL6251AHAZ-T_QSOP24

PR339

47K_0402_1%

DTC115EUA_SC70-3

Security Classification

PD301

RB751V-40_SOD323-2

PR310

10_1206_5%

24

DCIN

23

ACPRN

22

CSON

21

CSOP

20

CSIN

19

CSIP

18

PHASE

17

UGATE

16

BOOT

15

VDDP

14

LGATE

13

PGND

6251_VDD

12

2

PQ316

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

CHG_B+

PQ303

AO4407A_SO8

1 2

DISCHG_GCSIN

PC306

1 2

PC303

PC304

4.7U_0805_25V6-K

CSOP

PC306

1 2

PC305

2200P_0402_50V7K

4.7U_0805_25V6-K

6

578

4

123

6

578

4

123

CELLS

12

PR341

PR341 0_0402_5%

0_0402_5%

2N7002KDW-2N _SOT363-6@

2011/01/132010/01/13

2

PR305

47K_0402_1%

1 2

PR308

PR308 10K_0402_1%

10K_0402_1%

1SS355_SOD323-2@

1 2

DISCHG_G-1

PQ307

13

DTC115EUA_SC70-3

2

PR316

ACPRN

PQ311

AO4466L_SO8

10U_LF919AS-100M-P3_4.5A_20%

12

PQ314

AO4466L_SO8

6251_SN

12

6251_VDD 6251_VDD

1 2

61

PQ317A

Date: Sheet

3 6

4

ACOFF-1

PD302

1 2

PD303

PD303 1SS355_SOD323-2@

1SS355_SOD323-2@

1 2

12

PC310

BATT_ON

1 2

100K_0402_5%

2200P_0402_50V7K

13

D

2

G

PQ312

S

2N7002W-T/R7_SOT323-3

PL301

1 2

PR326

4.7_1206_5%

PC321

680P_0603_50V7K

PR336

100K_0402_1%@

2

Title

Size Document Number Rev

2N7002W-T/R7_SOT323-3

CHGCHG

1

2

PR337

PR337 100K_0402_1%@

100K_0402_1%@

1 2

34

5

BATT_SEL_EC

PQ317B

2N7002KDW-2N _SOT363-6@

Compal Electronics, Inc.

CHARGER

1

8 7

5

VIN

PR309

@

200K_0402_1%

1 2

PQ310

13

D

2N7002W-T/R 7_SOT323-3@

PACIN

2

12

G

S

PC311

0.1U_0603_25V7K

@

PR324

0.02_1206_1%

4

3

12

PC318

PC319

10U_1206_25V6M

3cell : GND 4cell : VDD

12

PR342

PR342 0_0402_5%@

0_0402_5%@

PIQY0/Y1

1

BATT+

12

PC323

10U_1206_25V6M

0.2

of

54 63Wednesday, October 06, 2010

CyberForum.ru

5

Note: Use TPS51125 IC can remove RTC refernece LDO Use TPS51427 IC must keep RTC refernece LDO

4

3

2

1

2VREF_8205

+3VALWP +3VALW

D D

PR401

13K_0402_1%

1 2

PR403

RT8205_B+

PJ401

B+

PC401

C C

B B

PJ401

2

JUMP_43X118@

12

@

680P_0402_50V7K

MAINPWON<45,46>

112

PC403

0.1U_0603_25V7K

12

PC405

PC404

4.7U_0805_25V6-K

+3VALWP

150U_B2_6.3VM_R45M

PR414

PR414 0_0402_5%

0_0402_5%

12

PC406

2200P_0402_50V7K

4.7UH_PCMC063T-4R7MN_5.5A_20%

1 2

1

+

PC414

2

PQ405A

2N7002KDW-2N_SOT363-6

PQ405A

VL

AO4466L_SO8

PL402

61

PQ401

12

PR409

4.7_1206_5%

12

PC416

680P_0603_50V7K

2

PR415

100K_0402_1%

123

12

6

3 6

241

578

4

578

PQ403

PQ403 AO4712_SO8

AO4712_SO8

Typ: 175mA

34

5

+3VLP

12

PC411

4.7U_0805_10V6K

BST_3V-1

1 2

PC412

0.1U_0603_25V7K

B+

PQ405B

PQ405B 2N7002KDW-2N_SOT363-6

2N7002KDW-2N_SOT363-6

PR412

499K_0402_1%

1 2

ENTRIP2ENTRIP1

1 2

0_0603_5%

MAINPWON

PR407

PR410 0_0402_5%

0_0402_5%

12

PR413

100K_0402_1%

PR403

20K_0402_1%

1 2

PR405

110K_0402_1%

1 2

25

7

8

BST_3V

9

UG_3V

10

LX_3V

11

LG_3V

12

@PR410

@

12

PC418

1U_0603_10V6K

2VREF_8205

PU401

P PAD

VO2

VREG3

BOOT2

UGATE2

PHASE2

LGATE2

12

PC402

1U_0603_10V6K

FB_3V

ENTRIP2

6

5

FB2

ENTRIP2

VFB=2.0V

SKIPSEL

EN

14

13

RT8205_B+

4

TONSEL

15

FB_5V

1

3

2

FB1

REF

UGATE1

PHASE1

VIN16GND

17

12

PC419

12

PC420

0.1U_0603_25V7K

PR402

30K_0402_1%

1 2

PR404

20K_0402_1%

1 2

PR406

154K_0402_1%

ENTRIP1

1 2

ENTRIP1

24

VO1

23

PGOOD

22

BOOT1

21

20

19

LGATE1

RT8205EGQW_W QFN24_4X4

NC18VREG5

VL

Typ: 175mA

4.7U_0805_10V6K

BST_5V

UG_5V

LX_5V

LG_5V

PC407

PR408

0_0603_5%

1 2

RT8205_B+

12

PC408

4.7U_0805_25V6-K

SPOK <46>

PC413

0.1U_0603_25V7K

BST_5V-1

1 2

12

PC410

PC409

0.1U_0603_25V7K

2200P_0402_50V7K

+5VALWP +5VALW

12

6

578

4

578

AO4712_SO8

PQ404

3 6

+3.3VALWP OCP(min)=5.81A +5VALWP OCP(min)=8.44A

PJ402

2

112

JUMP_43X118@

PJ403

2

112

JUMP_43X118@

PQ402

AO4466L_SO8

123

PL401

1 2

12

PR411

4.7_1206_5%

12

150U_B2_6.3VM_R45M

PC417

680P_0603_50V7K

PL401

4.7UH_PCMC063T-4R7MN_5.5A_20%

241

PC415

1

+

2

+5VALWP

13

PR416

200K_0402_1%

ACPRN

A A

200K_0402_1%

12

EC_ON<39,43>

2

5

2

G

13

D

VS

PQ407

S

2N7002W-T/R7_SOT323-3

PQ408

DTC115EUA_SC70-3

1 2

PR417

100K_0402_1%

12

PR418

40.2K_0402_1%

2

12

PC421

2.2U_0603_10V7K

4

PQ406

PQ406 DTC115EUA_SC70-3

DTC115EUA_SC70-3

Security Classification

2010/01/25 2010/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/01/25 2010/12/31

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

3VALWP/5VALWP

Size Document Number Rev

Custom

Date: Sheet

PIQY0/Y1

1

55 63Wednesday, October 06, 2010

of

0.1

CyberForum.ru

A

1 1

PR501

0_0402_5%

SYSON<39,44>

2 2

+5VALW

1 2

PR503

@

PR506

100_0603_5%

1 2

4.7U_0603_6.3V6K

1 2

47K_0402_5%

PC510

12

PC501

.1U_0402_16V7K

47P_0402_50V8J

12

PR509

PR509 10K_0402_1%

10K_0402_1%

@PC501

@

PC509

@PC509

@

1 2

PR508

1 2

10K_0402_1%

1.5V_TON

1.5V_V5FILT

1.5V_FB

2

3

4

5

6

1.5V_EN

PU501

TON

VOUT

VDD

FB

PGOOD

B

PR502

267K_0402_1%

1 2

15

14

1

NC

BOOT

UGATE

EN/DEM

PHASE

VFB=0.75V

LGATE

GND7PGND

RT8209BGQW _WQFN14_3P5X3P5

8

BST_1.5V

CS

VDDP

13

12

11

10

9

PR504

0_0603_5%

1 2

DH_1.5V

LX_1.5V

1.5V_TRIP

DL_1.5V

BST_1.5V-1

1 2

PR507

9.76K_0402_1%

PC505

0.1U_0603_25V7K

1 2

+5VALW

12

PC507

4.7U_0805_10V6K

C

PL503

HCB2012KF-121T50_0805

PL501

PC503

4.7U_0805_25V6-K

HCB2012KF-121T50_0805

1 2

12

1

+

PC506

PC506 330U_X_2VM_R6M

330U_X_2VM_R6M

2

786

5

PQ501

PQ501 AO4406AL_SO8

AO4406AL_SO8

4

123

578

PQ502

PQ502 AO4456_SO8

AO4456_SO8

3 6

241

1.5_51117_B+

12

PC502

4.7U_0805_25V6-K

1UH_PCMB103T-1R0MS_13A_20%

1 2

12

PR505

4.7_1206_5%

1.5V_SNB

12

PC508

680P_0603_50V7K

B+

12

PC504

@PC504

@

680P_0402_50V7K

D

+1.5VP

+1.5VP OCP(min)=15.6A

1.8VSP max current=4A

PJ502

+1.5VP

3 3

PJ502

2

112

JUMP_43X118@

+1.5V

4.5x4.5 2H

PJ505

PL502

PU502

PJ504

+5VALW

4 4

2

112

JUMP_43X118@

SUSP#<10,39,44,51,52>

12

PC511

PC511 22U_0805_6.3VAM

22U_0805_6.3VAM

1 2

PR512 0_0402_5%PR512 0_0402_5%

PR513

1M_0402_5%

1.8V_VIN

1.8V_EN

12

PC516

@

1 2

A

4

10

PVIN

PG

9

PVIN

8

SVIN

5

EN

TP

NC

7

11

SY8033BDBC_DFN10_3X3

0.1U_0402_10V7K

B

LX

FB

NC

1

LX_1.8V

2

3

FB_1.8V

6

FB=0.6Volt

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PL502

1UH_PCMB042T-1R0MS_4.5A_20%

1 2

12

PR511

30K_0402_1%

PR510

4.7_1206_5%

1.8V_SNB

12

PC513

680P_0603_50V7K

PR514

14.7K_0402_1%

2010/01/25 2010/12/31

12

PC512

68P_0402_50V8J

12

Compal Secret Data

12

PC514

22U_0805_6.3VAM

Deciphered Date

C

12

+1.8VSP

PC515

22U_0805_6.3VAM

Compal Electronics, Inc.

Title

PWR-+1.5VP/+1.8VSP

Size Document Number Rev

Custom

Date: Sheet

PJ505

2

112

JUMP_43X118@

PIQY0/Y1

D

+1.8VS+1.8VSP

0.1

of

56 63Wednesday, October 06, 2010

CyberForum.ru

5

PR601

0_0402_5%

+5VALW

0_0402_5%

1 2

PR604

@ PR604

@

47K_0402_5%

1 2

PC608

4.7U_0603_6.3V6K

12

PR606

PR606 100_0603_1%

100_0603_1%

VFB=0.75V

30K_0402_1%

12

0.1U_0402_16V7K

@

12

PR614

PC601

PR612

PR612 2K_0402_1%

2K_0402_1%

1 2

12

D

S

12

13

VCCSAP_TON

VCCSAP_V5FILT

VCCSAP_FB

+3VS

PR609

10K_0402_5%

1 2

PR615

PR615 15K_0402_1%

15K_0402_1%

PQ603

PQ603 2N7002W-T/R7_SOT323-3

2N7002W-T/R7_SOT323-3

VCCSASEL-3

2

G

VCCSAP_EN

VCCSAP_PGOOD

VCCSAP_FB-1

12

4700P_0402_25V7K@

2

3

4

5

6

0_0402_5%

PR611

10K_0402_5%

PC609

PU601

TON

VOUT

VDD

FB

PGOOD

12

PR617

VCCPPWRGOOD<51>

D D

C C

PR602

280K_0402_1%

1 2

BST_VCCSAP

1

15

14

NC

EN/DEM

GND7PGND

RT8209BGQW_WQFN14_3P5X3P5

8

SA_PGOOD <39>

+3VS

12

PR616

10K_0402_5%

VCCSASEL-2

12

PR618

@PR618

@

100K_0402_5%

4

BOOT UGATE

PHASE

CS

VDDP

LGATE

PMBT2222A_SOT23-3

1

3

PR603

0_0603_5%

1 2

UG_VCCSAP

13

LX_VCCSAP

12

VCCSAP_TRIP

11

10

LG_VCCSAP

9

PQ604

VCCSASEL-1

2

BST_VCCSAP-1

1 2

PR610

PR610 13K_0402_1%

13K_0402_1%

PR619

0_0402_5%

0.1U_0603_25V7K

12

PR620

10K_0402_5%@

PC604

1 2

+5VALW

12

AO4712_SO8

PC607

4.7U_0805_10V6K

VCCSA_SEL <10>

3

51117_VCCSAP_B+

12

PC603

PC602

6

578

PQ601

AO4466L_SO8

4

123

578

PQ602

3 6

241

VID[0] VID[1] VCCSA Vout Require on 2011/ 2012 Required 0 0 0.9 V Yes/Yes 0 1 0.8 V Yes/Yes 1 1 0.75V No/Yes 1 1 0.65V No/Yes

Note:Use VCCSA_SEL to switch High & Low Level for VID[1] (ie. VCCSA_SEL) due to the VID[0] is don't care for this setting.

PC602

4.7U_0805_25V6-K

PL601

2.2UH_PCMC063T-2R2MN_8A_20%

1 2

12

PR605

4.7_1206_5%

VCCSAP_SNB

12

PC606

470P_0603_50V8J

2

JUMP_43X118

4.7U_0805_25V6-K

PR607

PR607 0_0402_5%

0_0402_5%

1 2

PR613

1 2

10_0402_5%

PJ601

@ PJ601

@

Ventura_B+

112

1

+

PC605

220U_6.3V_M

OS-CON

2

VCCSA_SENSE <10>

PR608

1 2

0_0402_5%

2

+VCCSAP

VSSSA_SENSE <10>

+VCCSAP OCP(min)=6.28A

PJ602

2

112

JUMP_43X118@

1

+VCCSA+VCCSAP

PJ605

2

112

JUMP_43X118@

Optimus: PR633 DIS: PR624

PR630

267K_0402_1%

2

3

4

5

6

1.35V_EN

PU603

TON

VOUT

VDD

FB

PGOOD

267K_0402_1%

1 2

15

1

NC

EN/DEM

VFB=0.75V

GND7PGND

8

PR625

0_0603_5%

1 2

13

12

11

10

9

DH_1.35V

LX_1.35V

1.35V_TRIP

DL_1.35V

BST_1.35V-1

1 2

BST_1.35V

14

BOOT UGATE

PHASE

CS

VDDP

LGATE

RT8209BGQW_WQFN14_3P5X3P5

4

PC617

0.1U_0603_25V7K

1 2

PR629

9.76K_0402_1%

+5VALW

12

PC620

4.7U_0805_10V6K

4

PR633

0_0402_5%

DGPU_PWR_EN

B B

SUSP#

<10,39,44,49,51>

+5VALW

A A

0_0402_5%

1 2

PR624

0_0402_5%@

1 2

PR632

47K_0402_5%

@

PR626

100_0603_5%

1 2

4.7U_0603_6.3V6K

5

1 2

PC619

12

PC616

.1U_0402_16V7K

12

@PC 616

@

PC623

@ PC623

@

47P_0402_50V8J

1 2

PR627

8.06K_0402_1%

1 2

PR628

PR628 10K_0402_1%

10K_0402_1%

1.35V_TON

1.35V_V5FILT

1.35V_FB

6

578

3 6

123

241

1.35_51117_B+

PQ606

PQ606 AO4466L_SO8

AO4466L_SO8

PQ607

PQ607 AO4712_SO8

AO4712_SO8

12

PC622

PC621

4.7U_0805_25V6-K

PL602

1UH_PCMC063T-1R0MN_11A_20%

1 2

12

PR631

4.7_1206_5%

1.35V_SNB

12

PC625

680P_0603_50V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

12

PL603

HCB2012KF-121T50_0805

1 2

12

PC624

@ PC624

@

680P_0402_50V7K

B+

+1.35VSP_VGA

1

+

PC618

PC618 220U_B2_2.5VM_R15M

220U_B2_2.5VM_R15M

2

4.7U_0805_6.3V6K

PR622

24.9K_0402_1%

LDO_0.75_EN

SUSP<6,10,44>

2010/01/25 2010/12/31

1 2

PC613

1U_0402_6.3V6K

Compal Secret Dat a

Deciphered Dat e

2

12

PC610

2

G

+1.5V

13

D

S

1

PJ604

1

JUMP_43X79

@

2

1 2

2N7002W-T/R7_SOT323-3

PQ605

PR621

1K_0402_1%

PR623

1K_0402_1%

LDO_0.75_VIN

LDO_0.75_VREF

PJ603

2

112

JUMP_43X79@

PU602

VIN1VCNTL

2

12

PC612

0.1U_0402_16V7K

Title

PWR +VCCSAP/+1.35VSP_VGA/+0.75VSP

Size Document Number Rev

C

Date: Sheet

GND

3

VREF

4

VOUT

G2992F1U_SO8

12

PC614

10U_0603_6.3V6M

Compal Electronics, Inc.

NC

TP

+0.75VSP

PC615

10U_0603_6.3V6M

PIQY0/Y1

6

5

7

8

9

1

+1.35VS_VGA+1.35VSP_VGA

+0.75VS+0.75VSP

+3VALW

12

PC611

PC611 1U_0603_10V6K

1U_0603_10V6K

57 63Wednesday, October 06, 2010

of

0.1

CyberForum.ru

5

4

3

2

1

+1.05VS_VCCPP OCP(min)=20.75A

PL702

HCB2012KF-121T50_0805

PL701

12

PR705

0_0603_5%

HCB2012KF-121T50_0805

1 2

PJ702

2

JUMP_43X118@

JUMP_43X118@ PJ703

PJ703

2

JUMP_43X118@

PJ705

2

JUMP_43X118@

1.05VS_B+

786

PR702

267K_0402_1%

PU701

2

TON

3

VOUT

4

VDD

5

FB

6

PGOOD

+5VALW

12

PC712

1U_0402_6.3V6K

PU702

7

POK

8

EN

267K_0402_1%

1 2

15

14

1

NC

BOOT UGATE

EN/DEM

VFB=0.75V

VCCPPWRGOOD <50>

6

VCNTL

GND

1

PHASE

VDDP

LGATE

GND7PGND

RT8209BGQW_W QFN14_3P5X3P5

8

VGAPCIE_VIN

5

VIN

4

VOUT

3

VOUT

2

FB

9

VIN

APL5912-KAC-TRL_SO8

CS

DH_1.05VS_VCCP

13

LX_1.05VS_VCCP

12

1.05VS_VCCP_TRIP

11

10

DL_1.05VS_VCCP

9

+1.5V

1

2

12

PC713

4.7U_0805_6.3V6K

1.15K_0402_1%

VGAPCIE_FB

3.57K_0402_1%

PR703

0_0603_5%

1 2

PJ704

PJ704 JUMP_43X79

JUMP_43X79

@

PR716

PR718

BST_1.05VS_VCCP-1

1 2

PR707

13.7K_0402_1%

12

PC706

0.1U_0603_25V7K

1 2

+5VALW

12

PC714

0.01U_0402_25V7K

PC709

4.7U_0805_10V6K

+1.05VS_VGAP

PC715

22U_0805_6.3V6M

D D

PR701

0_0402_5%

10,39,44,49,52>

SUSP#

+5VALW

C C

B B

Optimus: PR714 DIS: PR715

DGPU_PWR_EN<25>

A A

1 2

PR706

100_0603_5%

1 2

PC711

4.7U_0603_6.3V6K

SUSP#<10,39,44,49,51>

12

PR709

10K_0402_1%

DGPU_PWR_EN

12

PC701

PC701 .1U_0402_16V7K@

.1U_0402_16V7K@

@PC710

@

47P_0402_50V8J

4.02K_0402_1%

1 2

12

PD702

PD702 RB751V-40_SOD323-2@

RB751V-40_SOD323-2@

1 2

PR714

PR714 0_0402_5%

0_0402_5%

1 2

PR715

PR715 0_0402_5%@

0_0402_5%@

1 2

PD701

RB751V-40_SOD323-2@

PC710

1 2

PR708

+3VS

1.05VS_VCCP_TON

1.05VS_VCCP_V5FILT

1.05VS_VCCP_FB

PR710

PR710 10K_0402_1%

10K_0402_1%

1 2

PC716

@ PC716

@

1.05VS_VCCP_EN BST_1.05VS_VCCP

1.05VS_VCCP_FB1

PR712

PR712 10K_0402_1%

10K_0402_1%

@

1 2

+5VALW

12

PR713

PR713 0_0402_5%@

0_0402_5%@

VGAPCIE_POK

VGAPCIE_ENSUSP#

12

PR717

47K_0402_5%@

0.1U_0603_25V7K

47K_0402_5%@

5

PQ701

PQ701 AO4406AL_SO8

AO4406AL_SO8

4

123

578

PQ702

PQ702 AO4456_SO8

AO4456_SO8

3 6

241

12

PC703

PC702

4.7U_0805_25V6-K

1UH_FDUE1040D-1R0M-P3_21.3A_20%

12

PR704

4.7_1206_5%

1.05VS_VCCP_SNB

12

PC708

680P_0603_50V7K

+1.05VS_VGAP +1.05VS_VGA

PC707

PR711

10_0402_5%

112

Ventura_B+

12

PC704

@PC704

@

680P_0402_50V7K

+1.05VS_VCCPP

1

+

2

330U_X_2VM_R6M

12

Ventura_B+

1

+

PC705

2

VCCIO_SENSE <9>

+1.05VS+1.05VS_VCCPP

68U_25V_M_R0.36

Security Classification

2010/01/25 2010/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/01/25 2010/12/31

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR +1.05VS_VCCPP/1.05VS_VGA

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

PIQY0/Y1

1

58 63Wednesday, October 06, 2010

of

0.1

CyberForum.ru

5

4

3

2

1

GPIO6 GPIO5

N12P-GS

GPU_VID1 GPU_VID0

00 0 1

D D

N12P-GT/GT1

GPIO6

GPU_VID1

GPIO5

GPU_VID0

00 0 1

C C

PC812

PR821

97.6K_0402_1%

1 2

220P_0402_50V8J

PR823

1K_0402_1%

PR824

255_0402_1%

1 2

VDD_SENSE_VGA

6

B B

+VGA_CORE

8

A A

GND_SENSE_VGA

PR826

10_0402_5%

PC812

470P_0402_50V7K

1 2

PC814

1 2

12

PC815

1000P_0402_50V7K

1 2

12

5

PR825

0_0402_5%

PR830

PR830 10_0402_5%

10_0402_5%

1 2

1 1

1 2

12

PR829

0_0402_5%

VGA_CORE

1.0V

0.975V

0.825V

VGA_CORE

1.075V

0.925V

0.825V

PC808

1 2

PR812

1000P_0402_50V7K

6.81K_0603_1%

1 2

PC816

@ PC816

@

1000P_0402_50V7K

12

1 2

VCC_PRM1

PC806

1 2

PR815

1000P_0402_50V7K@

1 2

6.34K_0402_1%

PC817

PC817 330P_0603_50V8

330P_0603_50V8

1 2

PC823

1 2

Optimus: PR801 DIS: PR802

10K_0402_5%

VGA_PGOOD<25>

+3VS

PC807

0.047U_0603_25V7M

1000P_0402_50V7K

PC824

PR814

PR813

1 2

150K_0402_1%

36.5K_0402_1%

@

6264_RBIAS

6264_OFS

6264_SOFT

6264_OCSET

6264_VW

6264_COMP

6264_FB

6264_VDIFF

6264_VSEN

180P_0402_50V8J

PR827

1K_0402_1%

VCC_PRM1

1 2

PC825

0.22U_0402_6.3V6K

4

+3VS

PR842

PR811

1 2

10K_0402_5%

6264_SET

1

2

3

4

5

6

7

8

9

10

41

PC819

1 2

1.5K_0402_1%

1 2

12

1 2

PC826

0.022U_0402_16V7K

1 2

PR809

1 2

10K_0402_5% @

SET

RBIAS

OFS

SOFT

OCSET

VW

COMP

FB

VDIFF

VSEN

GND PAD

6264_RTN

PR828

ŃġŷŢŭŶŦľĵĴııŌ

ŃġŷŢŭŶŦľĵĴııŌŃġŷŢŭŶŦľĵĴııŌ

PR833

1 2

GS: PR840,PR845,PR847,PR853 GT/GT1:PR843,PR844.PR846,PR854

PR801

10K_0402_1%

PC801

1 2

0.1U_0402_16V7K

+3VS

PR807

0_0402_5%

PR807

0_0402_5%

1 2

6264_VRON

39

38

40

PSI_L

VR_ON

PGOOD

ISL6264CRZ-T_QFN40_6X6

DROOP

RTN

DFB

12

11

13

6264_DFB

6264_DROOP 6264_PSI

PH801

1 2

11K_0402_1%

PR838

1 2

2.61K_0402_1%

2.61K_0402_1% 10K_0603_5%_TSM1A103J4302RE

10K_0603_5%_TSM1A103J4302RE

VSUM1

12

PR802

@ PR802

@

0_0402_5%

1 2

+3VS_VGA

PR804

1 2

0_0402_5%

+3VS_VGA

1 2

PR810 10K_0402_1%

6264_VID5

6264_VID4

6264_VID3

35

37

VID3

VID436VID5

PU801

VSUM

VIN

VO

15

16

14

6264_VIN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS_VGA

1 2

PR840 10K_0402_5%PR840 10K_0402_5%

34

VID2

GND

17

B+

PR832

1 2

DGPU_PWR_EN

SUSP# <3,14,16>

+3VS_VGA

1 2

PR805 10K_0402_5%PR805 10K_0402_5%

6264_VID0

PR843 10K_0402_5%PR843 10K_0402_5%

BST1_VGA

32

33

31

VID0

VID1

BOOT1

UGATE1

PHASE1

LGATE1

LGATE2

PHASE2

UGATE2

ISEN2

ISEN1

VDD

19

20

18

6264_VDD

+5VS

PR831

1 2

10_0603_5%

12

PC829

0.01U_0603_50V7K

PGND1

PGND2

BOOT2

6264_VID2

1 2

30

29

28

27

26

PVCC

25

24

23

22

21

VGA_ISEN1

VGA_ISEN2

10_0603_5%

PC830

1U_0402_6.3V6K

2006/12/12

3

1 2

PR808

2.2_0603_1%

UG1_VGA

PHASE1_VGA

LG1_VGA

PVCC_VGA

LG2_VGA

PHASE2_VGA

UG2_VGA

BST2_VGA

12

PR845

PR845 0_0402_5%

0_0402_5%

PR854

PR854 0_0402_5%

0_0402_5%

PR847

PR847 0_0402_5%

0_0402_5%

PR846

PR846 0_0402_5%

0_0402_5%

PR844

PR844 0_0402_5%

0_0402_5%

PR853

PR853 0_0402_5%

0_0402_5%

BST1_VGA-1

12

PR822

2.2_0603_1%

BST2_VGA-1

1 2

PC818

0.22U_0603_10V7K

Compal Secret Data

PQ807

13

D

2N7002KW_SOT323-3

2

G

S

PQ806

13

D

2N7002KW_SOT323-3

2

G

S

PC805

0.22U_0603_10V7K

12

Deciphered Date

1 2

PR839

10K_0402_5%

1 2

PR852

10K_0402_5%

1 2

PR820

PR820 0_0402_5%

0_0402_5%

12

PC811

4.7U_0603_6.3V6K

PR848

PR848 0_0402_5%

0_0402_5%

PR851

PR851 0_0402_5%

0_0402_5%

+5VS

4

GPU_VID1

GPU_VID0

5

4

123

4

123 5

5

PQ803

123

TPCA8030-H_SOP-ADV8-5

PQ804

123 5

TPCA8028-H_SOP-ADVANCE8-5

2007/12/12

2

VGA_B+ VGA_B+1

1 2

PC802

PC803

4.7U_0805_25V6-K

PQ801

TPCA8030-H_SOP-ADV8-5

PR816

1 2

PQ802

TPCA8028-H_SOP-ADVANCE8-5

VGA_SNB2

VGA_SNB1

12

1 2

0.36UH_PCMC104T-R36MN1R17_30A_20%

PR834

PR835

1 2

4.7_1206_5%

3.65K_0805_1%

VSUM1

12

PC832

680P_0603_50V7K

Title

Size Document Number Rev

Custom

Date: Sheet

PL801

HCB4532KF-800T90_1812

1 2

PC804

4.7U_0805_25V6-K

0.36UH_PCMC104T-R36MN1R17_30A_20%

4.7_1206_5%

PR817

1 2

3.65K_0805_1%

VSUM1

PC813

680P_0603_50V7K

1 2

PC820

PC821

4.7U_0805_25V6-K

PL803

10K_0402_1%

PC831

PR836

0.22U_0603_16V7K

1 2

VGA_ISEN2 VCC_PRM1

Compal Electronics, Inc.

GPU_VIN-

PL802

10K_0402_1%

PC810

PR818

0.22U_0603_16V7K

1 2

VGA_ISEN1 VCC_PRM1

VGA_B+

1 2

PC822

4.7U_0805_25V6-K

12

PR837

1_0402_5%

PR837

1_0402_5%

1 2

PR850

1 2

VGA_ISEN1

Power-VGA_CORE

PIQY0/Y1

Wednesday, October 06, 2010

0.004_2512_1%

4

3

<33>

12

PR819

1_0402_5%

PR819

1_0402_5%

1 2

10K_0402_1%

1

PR841

1

2

GPU_VIN+

+VGA_CORE

1

+

2

PR849

10K_0402_1%

1 2

VGA_ISEN2

+VGA_CORE

1

+

PC827

2

330U_D2E_2.5VM_R9M

59 63

of

B+

<33>

PC809

330U_D2E_2.5VM_R9M

PC828

330U_D2E_2.5VM_R9M

0.1

CyberForum.ru

PR906

@P R906

@

VR_SVID_DAT<9>

VR_SVID_ALRT#<9>

VR_SVID_CLK<9>

PR928

1 2

1.91K_0402_1%

VGATE <16>

12

PC926

19.1K_0402_1%

For shortage changed

0.047U_0603_16V7K

12

5

PR902

8.06K_0402_1%

12

PR918

For shortage changed

PR956 QC:19.1K DC:19.6K

1 2

3.83K_0402_1%

12

PR944

8.06K_0402_1%

47P_0402_50V8J

PC943

150P_0402_50V8J

12

PC908

PC908 39P_0402_50V7K

39P_0402_50V7K

PC913

PC913 150P_0402_50V8J

150P_0402_50V8J

12

PC919

18.2K_0402_1%

PC928

@PC928

@

PR940

470KB_0402_5%_ERTJ0EV474J

12

PC932

1000P_0402_50V7K

PC941

12

PR955

12

220K_0402_1%

+CPU_CORE

VCCSENSE<9>

VSSSENSE<9>

12

PC905

1000P_0402_50V7K

PR909

12

1 2

PR920

.1U_0402_16V7K@

GFX_CORE_PW RGD

PH903

12

PR951

3.74K_0402_1%

PR957

10_0402_1%@

PR961

10_0402_1%@

PR909

422_0402_1%

PR912

2.55K_0402_1%

12

130_0402_1%

PR933

1 2

0_0402_5%

12

470P_0402_50V7K

PR956

12

PR911

PR911 475K_0402_1%

475K_0402_1%

PC920

0.047U_0603_16V7K

VR_ON<39>

470P_0402_50V7K

12

1 2

PR941 27.4K _0402_1%PR941 27. 4K_0402_1%

499_0402_1%

12

PC912

PC912 330P_0402_50V7K

330P_0402_50V7K

12

+1.05VS_VCCPP

12

+3VS

PR922

PR923

54.9_0402_1%

43_0402_1%@

12

PR927

SVID_SDA

SVID_ALERT#

SVID_SCLK

ŃġŷŢŭŶŦľĵĸııŌ

ŃġŷŢŭŶŦľĵĸııŌŃġŷŢŭŶŦľĵĸııŌ

QC: PC935 DC: PC933

PC939

12

PR956 QC:3.724K DC:2.15K

Alert# PU resister need close CPU, so the PU resister in HW schematic. but DAT and CLK need close PWM-IC, so the PU resister in POWER schematic.

D D

499K_0402_1%

GFXVR_IMON

VSS_AXG_SENSE<10>

Parallel and tune length

+3VS

C C

VSSSENSE<9>

IMVP_IMON

+1.05VS_VCCPP

B B

12

PR936

VR_HOT#<46>

PR939

1 2

499_0402_1%

@

PC929

PC929 47P_0402_50V8J

47P_0402_50V8J

change from 43P to 47P for shortage problem 2010-03-15

PR950

1 2

499K_0402_1%@

*Iccmax in Turbo Mode for SV (35W) is 53A

A A

+CPU_CORE

Icc-max=53A Rdson=3.6~4.5m ohm DCR=1.1m ohm HW output cap: (1)10U_0805_4V *10 (2)22U_0805_6.3V *15 (3)470U_D2_2V *4(ESR=4.5m ohm)

*OCP setting value=71.5A *OCP setting value=37A

5

4

PC901 470P_0402_50V 7K@ PC901 470P_0402_50V7K@

12

470KB_0402_5%_ERTJ0EV474J

46

47

48

FBG

VSENG

COMPG

ISL95831CRZ-T_TQFN48_6X6

ISEN2

ISEN3

12

PH901

1 2

PR903

27.4K_0402_1%

12

PC909

330P_0402_50V7K

ISPG

ISNG

45

44

43

ISPG

RTNG

PU901

ISEN1

12

PC946

330P_0402_50V7K

12

PC906

1 2

330P_0402_50V7K

NTCG

42

ISNG

NTCG

1.54K_0402_1%

@PC951

@

330P_0402_50V7K

12

1.91K_0402_1%

VSUM-

PR901

3.83K_0402_1%

49

GND

1

VWG

2

IMONG

3

PGOODG

4

SDA

5

ALERT#

6

SCLK

7

VR_ON

8

PGOOD

9

IMON

10

VR_HOT#

11

NTC

12

VW

COMP13FB14ISEN3/ FB215ISEN216ISEN117VSEN18RTN19ISUMN20ISUMP21VDD22VIN23PROG1

PC933

PC933 22P_0402_50V8J@

22P_0402_50V8J@

12

PC9350.22U_0402_6.3V6K PC9350.22U_0402_6.3V6K

12

PC938

12

0.22U_0402_6.3V6K

PC942

12

0.22U_0402_6.3V6K

PC947

330P_0402_50V7K

PC950

1000P_0402_50V7K

+VGFX_COREP

Ipeak=26A , Imax=18.2A , 1.2Ipeak=31.2A Rdson=3.6~4.5m ohm DCR=1.1m ohm HW output cap: (1)22U_0805_6.3V *12 (2)470U_D2_2V *2(ESR=4.5m ohm)

4

PC911

12

1000P_0402_50V7K

PR919

16.5K_0402_1%@

1 2

PHASEG

UGATEG

BOOTG

39

40

41

38

UGG

PROG2

BOOTG

24

12

PC936

0.22U_0603_25V7K

1U_0603_10V6K

12

PC955

@ PC955

@

PR959

12

PC951

PR959 QC:1.54K=120A DC:887=70A

3

NTCG

PR968

0.004_2512_1%

CPU_VIN-

12

PR915

0_0603_5%

12

PR925

12

PR943

PR943 590_0402_1%

590_0402_1%

VSUM+

12

PR954

ŃġŷŢŭŶŦľĵĳĶıŌ

ŃġŷŢŭŶŦľĵĳĶıŌŃġŷŢŭŶŦľĵĳĶıŌ

12

2.61K_0402_1%

10K_0402_5%_ERTJ0ER103J

11K_0402_1%

12

PC952

.1U_0402_16V7K

0.004_2512_1%

4

3

<33>

+5VS

12

PU902

5

VCC

6

FCCM

2

PWM

3

GND

ISL6208CRZ-T_QFN8

PR929

1 2

0_0402_5%@

12

PC927

2.2U_0603_10V6K

PR943 0 ohm =>98A (Vboot=0v) 590 ohm=>91A (Vboot=0v)

PH904

VSUM-

UGATE1

PHASE1

BOOT1

LGATE1

2010/01/25 2010/12/31

ŃġŷŢŭŶŦľĵĸııŌ

ŃġŷŢŭŶŦľĵĸııŌŃġŷŢŭŶŦľĵĸııŌ

PR904

10_0402_1%

LGATEG

37

LGG

PHG

36

BOOT2

35

UG2

34

PH2

33

VSSP2

32

LG2

31

VDDP

30

PWM3

29

LG1

28

VSSP1

27

PH1

26

UG1

25

BOOT1

PR942

1 2

0_0603_5%

PR946

1_0603_5%

12

PC937

12

PC945

0.033U_0402_16V7K

PR960

100_0402_1%@

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Ventura_B+

+VGFX_CORE

12

VCC_AXG_SENSE <10>

VSS_AXG_SENSE <10>

PR913

12

0_0402_5%

BOOT2

UGATE2

PHASE2

LGATE2

PWM3

LGATE1

PHASE1

UGATE1

BOOT1

CPU_B+

12

+5VS

12

PC944

PR958

0.033U_0402_16V7K

0.22U_0603_10V7K

12

Issued Date

3

1

2

CPU_VIN+

PC915

1U_0603_10V6K

BOOT

UGATE

PHASE

LGATE

PR932

1 2

0_0402_5%

UGATE2

PHASE2

BOOT2

LGATE2

2.2_0603_5%

B+Ventura_B+

1

+

PC904

2

PHASEG

68U_25V_M_R0.36

<33>

BOOTG

2.2_0603_5%

LGATEG

PR916

12

2.2_0603_5%

BOOT3

1

UGATE3 CPU_B+

8

PHASE3

7

LGATE3

4

+5VS

2.2_0603_5%

2.2_0603_5% PR945

PR945

0.22U_0603_10V7K

PR962

Compal Secret Data

12

PC934

0.22U_0603_10V7K

PC953

12

Deciphered Date

12

4

PR905

4

5

PC916

1 2

213

12

5

@

2

PC907

0.22U_0603_10V7K

213

PQ910

PQ911

SI7170DP-T1-GE3_POWERPAK8-5

2

CPU_B+

1 2

PL901

PL901 HCB4532KF-800T90_1812

5

PQ901

PC902

10U_0805_25V6K

UGATEG

12

4

PQ907

PQ909

SI7170DP-T1-GE3_POWERPAK8-5

@

4

TPCA8030-H_SOP-ADV8-5

4

5

PQ903

4

TPCA8030-H_SOP-ADV8-5

4

213

5

PQ904

@

CPU_B+

123

213

PQ905

SI7170DP-T1-GE3_POWERPAK8-5

5

PQ908

5

PQ903

SI7170DP-T1-GE3_POWERPAK8-5

@

5

4

TPCA8030-H_SOP-ADV8-5

4

CPU_B+

123

213

SI7170DP-T1-GE3_POWERPAK8-5

12

PC948

10U_0805_25V6K

12

PQ912

12

SI7170DP-T1-GE3_POWERPAK8-5

4

5

10U_0805_25V6K

123

TPCA8030-H_SOP-ADV8-5

5

PQ902

4

213

SI7170DP-T1-GE3_POWERPAK8-5

12

PC923

10U_0805_25V6K

123

5

12

PQ906

PR934

12

213

SI7170DP-T1-GE3_POWERPAK8-5

12

PC931

PC930

10U_0805_25V6K

12

4.7_1206_5%

PR947

ISEN2

12

3.65K_0402_1%

PC940

VSUM+

680P_0603_50V7K

12

PC949

10U_0805_25V6K

DCR=1.33~1.396m ohm

10K_0402_1%

ISEN1

PR963

4.7_1206_5%

3.65K_0402_1%

VSUM+

PC954

680P_0603_50V7K

Title

Size Document Num ber Rev

Custom

Date: Sheet

HCB4532KF-800T90_1812

12

PC903

10U_0805_25V6K

Choke PN:SH00000JX00

DCR=1.33~1.396m ohm

0.36UH_PCMB103T-R36MS1R335_23A_20%

12

PR910

10K_0402_1%

4.7_1206_5%

PR907

12

1 2

7.5K_0402_1%

PC914

680P_0603_50V7K

ISPG

12

+5VS

PC924

10U_0805_25V6K

Choke PN:SH00000JX00

DCR=1.33~1.396m ohm

0.36UH_PCMB103T-R36MS1R335_23A_20%

ISEN3

PR930

10K_0402_1%

4.7_1206_5%

PR935

VSUM+

3.65K_0402_1%

PC925

VSUM-

680P_0603_50V7K

Choke PN:SH00000JX00

DCR=1.33~1.396m ohm

0.36UH_PCMB103T-R36MS1R335_23A_20%

4

3

10K_0402_1%

PR948

12

PR952

12

Choke PN:SH00000JX00

0.36UH_PCMB103T-R36MS1R335_23A_20%

4

3

PR964

12

PR966

12

Compal Electronics, Inc.

PWR +CPU_CORE/+VGFX_CORE

1

Ventura_B+

PL902

1

4

3

2

PH902

10K_0402_1%_ERTJ0EG103FA

PR914

1 2

PR917

1 2

11K_0402_1%

1 2

PC917 0.033U_0402_16V7KPC917 0.033U_0402_16V 7K

PC921

1 2

0.033U_0402_16V7K

PR926

ISNG

12

0_0402_5%@

PL903

4

3

12

PR938

12

1_0402_5%

PL904

1

2

PL905

1

2

PIQY0/Y1

1

12

PC956

0.1U_0603_25V7K

12

PR908

PR908 1_0402_5%

1_0402_5%

12

PR924

1

2

10K_0402_1%

PR949

10K_0402_1%@

PR953

1_0402_5%

PR969

10K_0402_1%@

+CPU_CORE

PR965

10K_0402_1%@

PR967

1_0402_5%

PR970

10K_0402_1%@

12

PC957

2200P_0402_50V7K

+VGFX_CORE

.1U_0402_16V7K

PC918

1 2

100_0402_1%

PR921

@PR921

@

1 2

750_0402_1%

PR931

@

PR937

@

+CPU_CORE

ISEN1

12

VSUM-

12

ISEN3

12

ISEN2

12

VSUM-

12

ISEN3

12

60 63Wednesday, October 06, 2010

of

+CPU_CORE

ISEN1

12

ISEN2

12

1

+

2

PC910

330U_X_2VM_R6M

12

PC922

470P_0402_50V7K

@ PC922

@

0.1

CyberForum.ru

5

4

3

2

1

9HUVLRQFKDQJHOLVW3,5/LVW 3DJHRI

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5HDVRQIRUFKDQJH 3* 0RGLI\/LVW 'DWH 3KDVH,WHP

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D D











C C







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B B















A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/06 2009/01/06

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PIR (PWR)

PIQY0/Y1

61 63Wednesday, October 06, 2010

1

0.1

of

CyberForum.ru

5

PIQY1 HW PIR List

4

3

2

1

OP!EBUF!!!QBHF!!!!!!!!!!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!QVSQPTF

FWU!UP!EWU

2

Q29 Sftfswf!S3:8

Sftfswf!qvmm!epxo!gps!QDI!HQJP64/ Gps!gbtu!cppu!gvodujpo/3 Q29 Fydibohf!TBUB!qpsu1!'!qpsu2

D D

Dibohf!LC!mjhiu!dpouspm!gspn!QXN!up!po0pgg/4 Q61 Dibohf!LC!mjhiu!dpouspm!djsdvju Gps!IENJ!qpsu!ejpef!qspufdujpo/5 Q47 Bee!G3!)qpmz.gvtf* Dibohf!FTBUB`EFU$!up!HQJP2/6 Q2: Tuvgg!S414-!votuvgg!S451 Sftfswf!VTC4/1!qpxfs!txjdui!dpouspm!jowfsufs!djsdvju/7 Q5: Tuvgg!S2179-!sftfswf!S2182-S2183-S21::-R232 Gps!DIH`PO$!qvmm!epxo/8 Q59 Bee!S2265 Dibohf!FD!DML!gspn!dsztubm!up!TVTDML/9 Q56 Tuvgg!S::7-S24:-D926-!votuvgg!S2111-D843-D844-Z6

Bee!V71-!R243-!D:32-!S243:-!R244-!S2439Q48: Bee!XMBO!qpxfs!txjudi!djsdvju

21

Q1: Bee!D:33 Q32

22

Bee!D:33!up!qmbdf!bu!DQV!tejf/

Bee!gps!JOUWSFO!dpouspmBee!S2441 23 Dibohf!MFE!uzqfNpejgz!MFE2-MFE3-MFE4-MFE6Q58 24 Dibohf!MFE`LC`QXN!up!V47/!qjo37!HQJP23/Npejgz!UQ`MFE$-!QDI`EQXSPL!boe!MFE`LC`QXN!mjolQ56 25 Bee!GBTU`CPPU$!up!sfqmbdf!FO`DBSE`QX$!boe!FO`XPM$Efmfuf!FO`DBSE`QX$-!FO`XPM$Q29 26 Sfnpwf!VTC!dibshfs!gvodujpoEfmfuf!VTC!dibshfs!djsdvjuQ59 27 Gspn!I`4Q1!up!I`4Q9Npejgz!I6-I7-I8!tj{fQ58

Gps!211I{!Ijhi!Qbtt!gjmufs28 Dibohf!D771-!D772!gspn!4411q!up!1/2vQ53

C C

Gps!211I{!Ijhi!Qbtt!gjmufs29 Sfqmbdf!S:69-!S:6:!up!D:37-!D:38!1/144vQ54

Sfnpwf!mjhiu!tfotps!gvodujpoSfnpwf!FD`TNC`DL3-!FD`TNC`EB3!mjol!up!KQ24Q612:

FNJ!SfrvftuBee!D:39-!D:3:Q5331

gps!VTC41-!VTC31!dpmbzpvu!eftjhoBee!K2:Q5:32

gps!VTC41-!VTC31!dpmbzpvu!eftjhoNpejgz!K29-!K31

Bee!gps!Gbtu!cppu!TQJ!SPN!tfmfdujpo!cz!FD/Bee!R245-!S2458-!S2457Q2533 34

Q2:35

Beefe!gps!XMBO!boe!DBSE!sfbefs!Sftfu!tjhobm/Bee!S2455-S2454Q48-!Q55

Beefe!gps!WFOUVSB!efufdujpo/Bee!S2456

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/06 2009/01/06

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PIR (HW)

LA-6882P

62 63Wednesday, October 06, 2010

1

0.2

of

CyberForum.ru

5

4

3

2

1

D D

AC MODE

BATT MODE

A1

VIN

BATT

B1

V

PU2

A3

B4

+3VALW

B5

A5

V

B7

V

A2

PU3

V

B+

V

B2

B+

PCH_PWR_EN#

2

V

PQ2

EC

VV

A5

A4

ON/OFF

B7

B6

V

PBTN_OUT#

PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# PM_SLP_A#

V

PM_SLP_SUS#

SYSON

DGPU_PWR_EN

SUSP#,SUSP

B3

51ON#

C C

EC_ON

2

4

PCH_RSMRST#

5

7 SYSON#

(DIS)

8a

8

6

U14,+3VALW_PCH

V

QH4,+5VALW_PCH

+3VALW_PCH

3

+5VALW_PCH

V

PCH

VV

+1.5V

V

PU5

VGA_ON

U49

V

+5VS

V

SYS_PWROK

PM_DRAM_PWRGD

H_CPUPWRGD

PLT_RST#

+3VSDGPU

V

Q6

+1.5VSDGPU

V

13

V

14

CPU

V

15

V

VVVV

11

VGATE

U40

U20

V

+3VS

B B

V

U13 +1.5VS

+1.8VSDGPU

V

U37

+1.0VSDGPU

V

VGA

V

PU28

PU8

VCCPPWRGOOD

V

PU9 +1.05VS_VCCP

VR_ON

9

PU1000 +CPU_CORE

V

VV

+0.75V

PU7 +VCCSA

+VGA_CORE

V

PU998

VGA_PWROK

(DIS)

8b

U47 CK505

V

10

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/01/25 2010/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Power sequence

LA-6361P

0.1

63 63Wednesday , October 06, 2010

1

63 63Wednesday , October 06, 2010

0.1

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