Compal LA-5071P KIUN0, IdeaPad S10-2 Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

KIUN0 Schematics Document

Intel Diamondville Processor with Calistoga(945GSE) + DDRII + ICH7M

2009-03-31

3 3

REV: 1.0

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

B

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

LA-4421P

1 42Monday, A pril 06, 2009

E

0.2

A

B

C

D

E

Compal Confidential

page 21

ZZZ 3

PCB

DAZ@

RGB

LVDS

PCI-Express

10/100 Ethernet

RTL8103E(L)

page 25

ZZ Z

ZZZ 1

ZZZ 2

Model Name : KIUN0
File Name : LA-5071P

1 1

Thermal Se nsor

EMC1402

2 2

page 4

PCB

PCB

DAZ@

CR T Conn

page 16

LCD Conn.

page 15

PCB

DAZ@

MINI Card x1

Diamondville SC

FCBGA8
437Pi ns

22x22mm

H_ A#( 3.. 31) H_ D#( 0..6 3)

FSB

400/533MHz

Calistoga GSE

page 4,5

Memory BUS(DDRII)

FCBGA998

27x27mm

page 6,7,8,9,10

DM I
X2 mode

ICH7M
BGA652

31x31mm

page 17,18,19,20

LPC BUS

1.8V DDRII 400/533

SATA

SSD

page 21

Clock Generator
CK 5 05

page 14

DDRII-SO-DIMM

US B

HDA

HDD

page 24

page 13

MINI Card x2

USB Port X3

Bl ueT ooth

CMOS CAM

page 21

page 30

page21

page24

Transfermer

3 3

page 25

Aralia Codec

ALC272

Power ON/OFF

page 28

DC IN

page 34

DC/DC Interface

3VALW/5VALW

page 31

page 37

RJ45

page 25

ENE KBC
KB926

page 27

SPI

1.5VS/0.9VS/

BATT IN

CHARGER

4 4

page 35

page 36

2.5VS

page 39

1.8V/VCCP

page 38

Int.KBD

page 29

Touch Pad

page 29

SP I ROM

page 27

AMP & INT
Speaker

page 22

page 22

INT MIC HeadPhone &

page 22

MIC Jack

page 23

Card Reader
RTS5159

page 26

SD / M M C/MS
CONN

page 26

CPU_CORE

A

page 40

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

B

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

LA-4421P

2 42Monday, A pril 06, 2009

E

0.1

A

1 1

B

C

D

E

Voltage Rails

S5

DescriptionPower Plane

VIN

B+

+CPU_CORE

+VCCP

+1.5VS

+1.8V

+2.5VS

+3VALW

+3VS

+5VALW

2 2

+5VS

+VSB VSB always on power rail ON ON*

+RTCVCC RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

STATE

Full ON

S1(P ower On Suspend)

S3 ( Suspend to RAM)

S4 ( Suspend to Disk)

S5 ( Soft OFF)

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

0.9V switched power rail for DDR terminator+0.9VS

VCCP switched power rail

1.5V switched power rail

1.8V power rail for DDR

2.5V switched power rail

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V swi tched power rail

SIGNAL

SLP_S3#

SLP_S4#

HIGH HIGH HIGH

HIGH

LOW

LOW LOW

LOWLOW

SLP_S5#

HIGHHIGHHIGH

HIGH

HIGH

LOW

+VALW

ON

ON

ON

ON

ON

S3S1

N/A N/A N/A

ON

ON OFF

ON

ON

ON

ON

ON

N/AN/AN/A

OFF

OFFON

OFF

OFFON

OFFOFFON

OFFOFFON

ON

OFF

OFF

ON ON*

OFF

OFF

ON ON*

OFF

OFFON

ONON

+V +VS Clock

ON

ON

ON

OFF

ON

OFF

OFF

OFF

OFF

ONON

LOW

OFF

OFF

OFF

External PCI Devices

DE VI CE RE Q/ GNT #

IDS EL #

No PCI Device

EC SM Bus1 address

Device

Smart Battery

Address

EC SM Bus2 address

Device

EMC1402

PI RQ

Address

100 _1100000 1 011 X b

3 3

BOARD ID Table(Page 25)

ID

0

1

2

3

4 4

BRD ID

R01 (EVT)

R02 (DVT)

R03 (PVT)

R10A (MP)

A

Ra

NC
100K
100K
100K

Rb Vab

0

8.2K
18K
NC

0V

0.25V

0.50V

3.3V

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ICH7M SM Bus address

Device

Clock Generator
(SL G8SP556 VTR)

DDR D IMMA

2006/08/18 2007/8/18

C

Address

1101 001Xb

101 0 000 Xb

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

B

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-4421P

3 42Monday, A pril 06, 2009

E

0.2

5

H_A#[ 3..16]<6>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13

D D

H_ADSTB#0<6>
H_RE Q#[0..4]<6>

H_A#[ 17..31]<6>

H_ADSTB#1<6>

C C

B B

H_A20M#<18>

H_FER R#<18>

H_IGNN E#<18>

H_STPCLK#<18>

H_INTR<18>

H_NMI<18>

H_SMI#<18>

+VCCP

+VCCP

H_A#14
H_A#15
H_A#16

H_ADSTB#0

H_AP0

T5

H_REQ#0

PAD

H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_AP1

T4 PAD

H_A20M#
H_FER R#
H_IGNN E# CLK_CPU_BCLK#
H_STPCLK#
H_INT R
H_NMI
H_SMI#

R233 1K_0402_5%

1 2

R231 1K_0402_5%

1 2

R232 1K_0402_5%

1 2

R230 1K_0402_5%

1 2

R31 1K_0402_5%

1 2

R55 1K_0402_5%

1 2

U9A

P21

A[3]#

H20

A[4]#

N20

A[5]#

R20

A[6]#

J19

A[7]#

N19

A[8]#

G20

A[9]#

M19

A[10]#

H21

A[11]#

L20

A[12]#

M20

A[13]#

K19

A[14]#

J20

A[15]#

L21

A[16]#

K20

ADSTB[0]#

D17

AP0

N21

REQ[0]#

J21

REQ[1]#

G19

REQ[2]#

P20

REQ[3]#

R19

REQ[4]#

C19

A[17]#

F19

A[18]#

E21

A[19]#

A16

A[20]#

D19

A[21]#

C14
C18
C20

E20

D20

B18

C15

B16
B17

C16

A17
B14
B15
A14
B19

M18

U18

T16

J4

R16

T15
R15
U17

D6
G6
H6

K4
K5

M15

L16

ADDR GROUP 1

A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
AP1

A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#

NC1
NC2
NC3
NC4
NC5
NC6
NC7

AU80586GE025512_FCBGA437

N270@

H_A#32
H_A#33
H_A#34
H_A#35

H_A20M#
H_IGNN E#

ADDR

GROUP

0

DEFER#

CONTROL

RESET#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PROCHOT#

XDP /ITP SI GNALS

THRMDA

THRMDC

THERM

THERMTRIP#

BCLK[0]
BCLK[1]

H CL K

NC

ADS#
BNR#

BPRI#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

BR1#

RSVD3
RSVD2
RSVD1

TDI

V19
Y19
U21

T21
T19
Y18

T20

F16
V16

W20

D15
W18
Y17
U20
W19

AA17
V20

K17
J18
H15
J15
K18
J16
M17
N16
M16
L17
K16
V15

G17
E4
E5

H17

V11
V12

C21
C1
A3

H_A20M#

.

H_FER R#

H_IGNN E#

H_INT R

H_NMI

H_STPCLK#

H_SMI#

FAN1 Conn

+5VS

+VCC_FAN1

EN_FAN1<27>

A A

EN_FAN1

FAN_SPEED1<27>

5

C312 2.2U_0603_10V6K

1 2

U12

1

EN

2

VIN

3

VOUT

4

VSET

APL5607KI-TRG_SO8

GND
GND
GND
GND

+3VS

12

R256
1K_0402_5%

1

C311
100P_0402_50V8J

2

8
7
6
5

40mil

+VCC_FAN1

4

H_ADS#
H_BNR#
H_BPRI#

H_DEF ER#
H_D RDY#
H_ DBSY#

H_BR0#

H_IER R#
H_INIT #_R

H_LOCK#

H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_ TRDY#

H_HIT#
H_HITM#

PREQ#
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#

H_PRO CHOT#_R
H_THERMDA
H_THERMDC

H_THERMTRIP#

CLK_CPU_BCLK

H_ADS# <6>

H_BNR# <6>

H_BPRI# <6>

H_DEF ER# <6>

H_D RDY# <6>

H_DB SY# <6>

H_BR0# <6>

R244 1K_0402_5%

1 2

H_LOCK# <6>

H_RESET# <6>

H_TR DY# <6>

H_HIT# <6>

H_HITM# <6>

1 2

R24 22_0402_5%

H_THERMTRIP# <6,18>

CLK_CPU_BCLK <14>
CLK_CPU_BCLK# <14>

ESD request

C391 100P_0402_50V8J

1 2

C392 100P_0402_50V8J

1 2

C393 100P_0402_50V8J

1 2

C394 100P_0402_50V8J

1 2

C395 100P_0402_50V8J

1 2

C396 100P_0402_50V8J

1 2

C397 100P_0402_50V8J

1 2

+5VS

DIODE
Closed to

12

Connector

D19

1SS355_SOD323

D20

@

1N4148_SOT23@

1 2

C314

2.2U_0603_10V6K

1 2

C313

1000P_0402_50V7K

1 2

1
2
3

4

+VCCP +VCCP

Close to CPU

Close to CPU

+VCCP

This shall place near CPU

R21 56_0402_5%
R19 56_0402_5%
R23 56_0402_5%
R20 56_0402_5%

R28 56_0402_5%
R36 56_0402_5%

JP12

1

4

2

G1

5

3

G2

ACES_85204-03001

ME@

12

1 2
1 2
1 2
1 2

1 2
1 2

R22
56_0402_5%

H_RS #[0..2] <6>

H_PRO CHOT# <40>

+CPU_EXTBGREF

1U_0603_10V4Z

12

R242
330_0402_5%

C71

Close to CPU pin
within 500mils.
Zo=55ohm

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ITP_TMS
ITP_TDI
PREQ#
ITP_TDO

ITP_TCK
ITP_TRST#

+VCCP

1

2

H_INIT# <18>

12

R48
1K_0402_1%

12

R49
2K_0402_1%

3

+CPU_GTLREF

+CPU_EXTBGREF

3

U9

N280

N280@

+CPU_CMREF

0.1U_0402_16V4Z

Close to CPU pin
within 500mils.
Zo=55ohm

2006/08/18 2007/8/18

H_D #[0..15]<6>

H_DSTBN#0<6>
H_DSTBP#0<6>

H_D# [16..31]<6>

H_DSTBN#1<6>
H_DSTBP#1<6>

R52 1K_0402_5%@

1 2

R50 1K_0402_5%@

1 2

CPU_BSEL0<14>
CPU_BSEL1<14>
CPU_BSEL2<14>

+VCCP

12

12

1

C296

2

Compal Secret Data

H_DIN V#0<6>

H_DIN V#1<6>

R241
1K_0402_1%

R240
2K_0402_1%

Deciphered Date

T6 PAD

T9 PAD

0.1U_0402_16V4Z

Close to CPU pin
within 500mils.
Zo=55ohm

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

2

Y11

W10

Y12
AA14
AA11

W12

AA16

Y10

Y9

Y13

W15

AA13

Y16

W13

AA9

W9
Y14
Y15

W16

V9

AA5

Y8

W3

U1
W7
W6

Y7

AA6

Y3
W2

V3

U2

T3

AA8

V2
W4

Y4

Y5

Y6

R4

A7

U5

V5

T17

R6
M6

N15

N6

P17

T6

J6

H5
G5

+VCCP

12

12

1

C295

2

+3VS

1

C80

2

H_THERMDA

0.1U_040 2_16V4Z~D

H_THERMDC

2200P_0402_50V7K

2

U9B

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DP#0

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
DP#1

GTLREF
ACLKPH
DCLKPH
BINIT#
EDM
EXTBGREF
FORCEPR#
HFPLL
MCERR#
RSP#
BSEL[0]
BSEL[1]
BSEL[2]

AU80586GE025512_FCBGA437

N270@

R237
1K_0402_1%

R238
2K_0402_1%

D[32]#
D[33]#
D[34]#

DATA GRP 0 DATA GRP 1

D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#

DAT A GRP 2

D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

DP#2

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

DATA GRP 3

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#

DP#3

COMP[0]
COMP[1]
COMP[2]
COMP[3]

MI SC

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

CORE_DET

CMREF[1]

Layout note:
COMP 0,2 connect with Zo=27.4ohm +/-15%, make
trac e le ngth shorter than 0.5"
COMP 1,3 connect with Zo=55ohm +/-15%, make
trac e length shorter than0.5"

CPU THERMAL SENSOR

U2

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

Addres s:100_1100

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DIN V#0
H_DP#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1 H_DSTBN#3
H_DSTBP#1
H_DIN V#1
H_DP#1

ACLKPH
DCLKPH

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

+CPU_GTLREF

C79

1 2

H_D#32

R3

H_D#33

R2

H_D#34

P1

H_D#35

N1

H_D#36

M2

H_D#37

P2

H_D#38

J3

H_D#39

N3

H_D#40

G3

H_D#41

H2

H_D#42

N2

H_D#43

L2

H_D#44

M3

H_D#45

J2

H_D#46

H1

H_D#47

J1

H_DSTBN#2

K2

H_DSTBP#2

K3

H_DIN V#2

L1

H_DP#2

M4

H_D#48

C2

H_D#49

G2

H_D#50

F1

H_D#51

D3

H_D#52

B4

H_D#53

E1

H_D#54

A5

H_D#55

C3

H_D#56

A6

H_D#57

F2

H_D#58

C6

H_D#59

B6

H_D#60

B3

H_D#61

C4

H_D#62

C7

H_D#63

D2
E2

H_DSTBP#3

F3

H_DIN V#3

C5

H_DP#3

D4

COMP0

T1

COMP1

T2

COMP2

F20

COMP3

F21

H_DPRSTP#

R18

H_DPSLP#

R17

H_DPWR#

U4

H_PW RGOOD

V17

H_CPUSLP#

N18
A13
B7

SMCLK

SMDATA

ALERT#

GND

Compal Electronics, Inc.

T7PAD

T8PAD
R243 27.4_0402_1%

1 2

R53 54.9_0402_1%

1 2

R26 27.4_0402_1%
R25 54.9_0402_1%

EC_SMB_CK2

8

EC_SMB_DA2

7

6

5

R58

10K_0402_5%

@

Diamondville(1/2)

LA-4421P

1

H_D# [32..47] <6>

H_DSTBN#2 <6>
H_DSTBP#2 <6>
H_DIN V#2 <6>

H_D# [48..63] <6>

H_DSTBN#3 <6>
H_DSTBP#3 <6>
H_DIN V#3 <6>

12
12

H_DPRSTP# <18,40>
H_DPSLP# <18>
H_DPWR# <6>
H_PW RGOOD <18>
H_CPUSLP# <6>

+CPU_CMREF

EC_SMB_CK2 <27>

EC_SMB_DA2 <27>

12

4 42Monday, A pril 06, 2009

1

+3VS

0.2

5

4

3

2

1

C72

C60

+VC CP

1

2

+1.5VS

1

2

1

C61

2

1U_ 0402_6.3V6K

1

C280

2

10U _0805_10V6K

1

+

C28 9

2

220 U_B2_2.5V M_R35

C67

0.1U _0402_10V7K

1U_ 0402_6.3V6K

1

C62

2

10U _0805_10V6K

1

C290

2

1

C64

2

1U_ 0402_6.3V6K

1

2

VC CSENSE <40>

VSS SENSE <40>

1U_ 0402_6.3V6K

1

C65

2

1

C63

2

1U_ 0402_6.3V6K

Length match within 25 mils
The trace space 7 mils,
Zo=27.4ohm

+CP U_COR E

1U_ 0402_6.3V6K

1

C53

2

1

2

2 x 330uF(9mohm/2)

1

+

C275

33 0U 2 .5V Y

2

1

+

C278

33 0U 2 .5V Y

2

U9 D

A2

VSS1

A4

VSS2

A8

VSS4

A15

VSS5

A18

VSS6

A19

VSS7

A20

VSS8

B1

VSS9

B2

VSS10

D D

C C

B B

A A

B5

VSS11

B8

VSS12

B13

VSS13

B20

VSS14

B21

VSS15

C8

VSS16

C17

VSS17

D1

VSS18

D5

VSS19

D8

VSS20

D14

VSS21

D18

VSS22

D21

VSS23

E3

VSS24

E6

VSS25

E7

VSS26

E8

VSS27

E15

VSS28

E16

VSS29

E19

VSS30

F4

VSS31

F5

VSS32

F6

VSS33

F7

VSS34

F17

VSS35

F18

VSS36

G1

VSS37

G4

VSS38

G7

VSS39

G9

VSS41

G13

VSS42

G21

VSS45

H3

VSS46

H4

VSS48

H7

VSS49

H9

VSS51

H13

VSS52

H16

VSS53

H18

VSS54

H19

VSS55

J5

VSS56

J7

VSS57

J9

VSS58

J13

VSS59

J17

VSS60

K1

VSS61

K6

VSS62

K7

VSS63

K9

VSS64

K13

VSS65

K15

VSS66

K21

VSS67

L3

VSS68

L4

VSS69

L5

VSS70

L6

VSS71

L7

VSS72

L9

VSS73

L13

VSS74

L15

VSS75

L18

VSS76

L19

VSS77

M1

VSS78

M5

VSS79

M7

VSS80

M9

VSS81

M13

VSS82

M21

VSS83

N4

VSS84

AU8 0586GE 025512_FCBGA437

N270@

VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100

VSS99
VSS98
VSS97
VSS96
VSS95

N5
N7
N9
N13
N17
P3
P4
P5
P6
P7
P9
P13
P15
P16
P18
P19
R1
R5
R7
R9
R13
R21
T4
T5
T7
T9
T10
T11
T12
T13
T18
U3
U6
U7
U15
U16
U19
V1
V4
V6
V7
V8
V13
V14
V18
V21
W1
W5
W8
W11
W14
W17
W21
Y1
Y2
Y20
Y21
AA2
AA3
AA4
AA7
AA10
AA12
AA15
AA18
AA19
AA20

+CP U_COR E

+CP U_COR E

10U _0805_10V6K

+VC CP

1

C46

2

1U_ 0402_6.3V6K

1

C70

2

U9 C

V10

VCCF

A9

VCCQ1

B9

VCCQ2

A10

VCCP1

A11

VCCP2

A12

VCCP3

B10

VCCP4

B11

VCCP5

B12

VCCP6

C10

VCCP7

C11

VCCP8

C12

VCCP9

D10

VCCP10

D11

VCCP11

D12

VCCP12

E10

VCCP13

E11

VCCP14

E12

VCCP15

F10

VCCP16

F11

VCCP17

F12

VCCP18

G10

VCCP19

G11

VCCP20

G12

VCCP21

H10

VCCP22

H11

VCCP23

H12

VCCP24

J10

VCCP25

J11

VCCP26

J12

VCCP27

K10

VCCP28

K11

VCCP29

K12

VCCP30

L10

VCCP31

L11

VCCP32

L12

VCCP33

M10

VCCP34

M11

VCCP35

M12

VCCP36

N10

VCCP37

N11

VCCP38

N12

VCCP39

P10

VCCP40

P11

VCCP41

P12

VCCP42

R10

VCCP43

R11

VCCP44

R12

VCCP45

AU8 0586GE 025512_FCBGA437

N270@

1U_ 0402_6.3V6K

1

C47

C48

2

1U_ 0402_6.3V6K

10U _0805_10V6K

1

C78

C77

2

10U _0805_10V6K

VCCPC64
VCCPC63
VCCPC62
VCCPC61

VCCSENSE

VSSSENSE

1U_ 0402_6.3V6K

1

C49

2

10U _0805_10V6K

1

C286

2

C9

VTT1

D9

VTT2

E9

VTT3

F8

VTT4

F9

VTT5

G8

VTT6

G14

VTT7

H8

VTT8

H14

VTT9

J8

VTT10

J14

VTT11

K8

VTT12

K14

VTT13

L8

VTT14

L14

VTT15

M8

VTT16

M14

VTT17

N8

VTT18

N14

VTT19

P8

VTT20

P14

VTT21

R8

VTT22

R14

VTT23

T8

VTT24

T14

VTT25

U8

VTT26

U9

VTT27

U10

VTT28

U11

VTT29

U12

VTT30

U13

VTT31

U14

VTT32

F14
F13
E14
E13

D7

VCCA

F15

VID[0]

D16

VID[1]

E18

VID[2]

G15

VID[3]

G16

VID[4]

E17

VID[5]

G18

VID[6]

C13

D13

PLACE IN CAVITY

1

C50

2

1U_ 0402_6.3V6K

1

C291

2

10U _0805_10V6K

+1.5VS

CP U_VID 0
CP U_VID 1
CP U_VID 2
CP U_VID 3
CP U_VID 4
CP U_VID 5
CP U_VID 6

VC CSENSE

VSS SENSE

1U_ 0402_6.3V6K

1

C51

2

10U _0805_10V6K

1

C284

2

0.1U _0402_10V7K

1

C52

2

1U_ 0402_6.3V6K

1

C40

2

10U _0805_10V6K

0.1U _0402_10V7K

1

C45

C41

2

CP U_VID0 <40>
CP U_VID1 <40>
CP U_VID2 <40>
CP U_VID3 <40>
CP U_VID4 <40>
CP U_VID5 <40>
CP U_VID6 <40>

1U_ 0402_6.3V6K

1

C58

2

10U _0805_10V6K

1

C76

2

1

2

1U_ 0402_6.3V6K

130mA

1

C59

2

1U_ 0402_6.3V6K

1

C294

2

10U _0805_10V6K

1U_ 0402_6.3V6K

1

C68

2

PLACE IN CAVITY

1U_ 0402_6.3V6K

1

2

10U _0805_10V6K

1

C75

2

PLACE IN CORRIDOR AND CLOSE TO CPU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

Title

Size Doc umen t Numb er R ev

B

2

Da te: Sheet o f

Compal Electronics, Inc.

Diamondville(2/2)

LA-4421P

5 42Mo nday, Ap ril 06, 2 009

1

0.2

5

4

3

2

1

H_D #[0..63]<4>

D D

C C

+VCCP

12

12

R37

R226

54.9_0402_1%

54.9_0402_1%

B B

12

R35

R227

24.9_0402_1%

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_XRCOMP
H_XSCOMP

+H_SWNG0

H_YRCOM P
H_YSCOMP

+H_SWNG1

12

24.9_0402_1%

AB4
AB8

AA9
AA8
AB1
AB7
AA2
AB5

A10

C15

C4
F6
H9
H6
F7
E3
C2
C3
K9
F5

J7
K7
H8
E5
K8

J8

J2

J3
N1

M5

K5

J5
H3

J4
N3

M4
M3

N8
N6
K3
N9

M1

V8
V9
R6
T8
R2
N5
N2
R5
U7
R8
T4
T7
R3
T5
V6
V3

W2
W1

V2

W4
W7
W5

V5

W8

A6

J1
K1
H1

U8A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31

H_ADS#
H_ADSTB#_0
H_ADSTB#_1

H_VREF0

H_BNR#

H_BPRI#

H_BREQ0#

H_CPURST#

H_VREF1

HCLKN

HOST

HCLKP

H_DBSY#
H_DEFER#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DPWR#

H_DRDY#

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_HIT#

H_HITM#

H_LOCK#
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

H_SLPCPU#

H_TRDY#

Calistoga-G SE_FCBGA998

F8
D12
C13
A8
E13
E12
J12
B13
A13
G13
A12
D14
F14
J13
E17
H15
G15
G14
A15
B18
B15
E14
H13
C14
A17
E15
H17
D17
G17

F10
C12
H16
E2
B9
C7
G8
B10
E1

AA6
AA5
C10
C6
H5
J6
T9
U6
G7
E6
F3
M8
T1
AA3
F4
M7
T2
AB3

C8
B4
C5
G9
E9
G12
B8
F12
A5
B6
G10
E8
E10

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_ADS#
H_ADSTB#0
H_ADSTB#1
+H_VREF
H_BNR#
H_BPRI#
H_BR0#
H_RESET#
+H_VREF

CLK_MCH_BCLK#
CLK_MCH_BCLK
H_ DBSY#
H_DEF ER#
H_DIN V#0
H_DIN V#1
H_DIN V#2
H_DIN V#3
H_DPWR#
H_D RDY#
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_HIT#
H_HITM#
H_LOCK#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_CPUSLP#
H_ TRDY#

H_A#[ 3..31] <4>

H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>

H_BNR# <4>
H_BPR I# <4>
H_BR0# <4>
H_RESET# <4>

CLK_MCH_BCLK# <14>
CLK_MCH_BCLK <14>
H_D BSY# <4>
H_DEF ER# <4>
H_DIN V#0 <4>
H_DIN V#1 <4>
H_DIN V#2 <4>
H_DIN V#3 <4>
H_DPWR# <4>
H_D RDY# <4>

H_DST BN#[0..3] <4>

H_DST BP#[0..3] <4>

H_HIT# <4>
H_HITM# <4>
H_LOCK# <4>

H_RE Q#[0..4] <4>

H_R S#[0..2] <4>

H_CPUSLP# <4>
H_TR DY# <4>

+DIMM_VREF

DMI_TXN0<19>
DMI_TXN1<19>
DMI_TXP0<19>
DMI_TXP1<19>

DMI_RXN0<19>
DMI_RXN1<19>
DMI_RXP0<19>
DMI_RXP1<19>

M_CLK_DDR0<13>
M_CLK_DDR1<13>

M_CLK_DDR#0<13>
M_CLK_DDR#1<13>

DDR_C KE0<13>
DDR_C KE1<13>

DDR_C S0#<13>
DDR_C S1#<13>

+1.8V

R56 80.6_0402_1%

1 2
1 2

R54 80.6_0402_1%

1

Layout Note:
+DIMM_ VREF trace

C293

2

width and spacing
is 20/20.

0.1U_0402_16V4Z

AF33

AG1

AM30

AG33

AF1

AK1

AN30

AN21
AN22

AF26
AF25

AG14

AF12
AK14

AH12

AJ21
AF11

AE12
AF14
AJ14
AJ12

AN12
AN14

AA33

AE1

Y29
Y32
Y28
Y31

V28
V31
V29
V32

AJ1

U8B

DMI_RXN_0
DMI_RXN_1
DMI_RXP_0
DMI_RXP_1

DMI_TXN_0
DMI_TXN_1
DMI_TXP_0
DMI_TXP_1

SM_CK_0
SM_CK_1

SM_CK_2
SM_CK_3

SM_CK#_0
SM_CK#_1

SM_CK#_2
SM_CK#_3

SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_OCDCOMP_0
SM_OCDCOMP_1

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMPN
SM_RCOMPP
SM_VREF_0
SM_VREF_1

Calistoga-G SE_FCBGA998

DMI

DDR2 MUXING

RESERVED1
RESERVED2
RESERVED7
RESERVED8
RESERVED9

CFG/RSVD

PM_ICHSYNC#

PM_BMBUSY#
PM_EXTTS#_0

PM

PM_EXTTS#_1

THRMTRIP#

PWROK

RSTIN#

D_REFCLKN
D_REFCLKP

CLK

D_REFSSCLKN
D_REFSSCLKP

CLKREQ#

CFG_0
CFG_1
CFG_2
CFG_3
CFG_5
CFG_6

C18
E18
G20
G18
J20
J18

K32
K31
C17
F18
A3

E31
G21
F26
H26
J15
AB29
W27

A27
A26
J33
H33
J22

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

T2

CFG5

PM_EXTTS#0
PM_EXTTS#1

PLTRST_R#

PAD

1 2

R34 2.2K_0402_5%

T3PAD

R44 0_0402_5%

H_THERMTRIP#

ICH_P OK

1 2

R47 100_0402_5%

MCH_CLKSEL0 <14>
MCH_CLKSEL1 <14>
MCH_CLKSEL2 <14>

MCH _ICH_SYNC # <17>

PM_BMBUSY# <19>
PM_EXTTS#0 <13>

12

PM_DPRSLPVR <19,40>

H_THERMTRIP# <4,18>

ICH_P OK <19,27>

PLTRST# <17,19,21,25>

CLK_M CH_DREFCLK# <14>
CLK_M CH_DREFCLK <14>
MCH_ SSCDREFCLK# <14>
MCH_ SSCDREFCLK <14>
MCH_CLKREQ# <14>

DMI_TXN0
DMI_TXN1
DMI_TXP0
DMI_TXP1

DMI_RXN0
DMI_RXN1
DMI_RXP0
DMI_RXP1

M_CLK_DDR0
M_CLK_DDR1

M_CLK_DDR#0
M_CLK_DDR#1

DDR_C KE0
DDR_C KE1

DDR_C S0#
DDR_C S1#

M_ODT0<13>
M_ODT1<13>

M_ODT0
M_ODT1

SMRCOMPN
SMRCOMPP

10uA

Strap Pin Table

CFG5

Low = DMI x 2

High = DMI x 4

*

Layout Note:
H_XR COMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SW NG1 trace width and spacing is 10/20.

+VCCP

12

A A

R27

100_0402_1%

+H_VREF

12

1

C31

R29

2

200_0402_1%

5

C be placed <100mils
from GMCH pin

0.1U_0402_16V4Z

+VCCP

R18

R17

12

+H_SWNG0

221_0402_1%~D

12

1

C29

2

100_0402_1%

0.1U_0402_16V4Z

4

+VCCP

R33

R30

12

+H_SWNG1

221_0402_1%~D

12

1

C33

2

100_0402_1%

0.1U_0402_16V4Z

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

2

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

PM_EXTTS#0

PM_EXTTS#1

1 2

R42 10K_0402_5%

@

1 2

R43 10K_0402_5%

Compal Electronics, Inc.

Calistoga(1/5)-GTL/DMI/DDR

LA-4421P

1

+3VS

0.2

6 42Monday, A pril 06, 2009

5

4

3

2

1

D D

DDR_ A_DQS#[0..7 ]<13>

C C

B B

DDR_A_BS 0<13>
DDR_A_BS 1<13>
DDR_A_BS 2<13>

DDR_ A_DM[0..7]<13>

DDR_ A_DQS[0..7]<13>

DDR_A_ MA[0..13]<13>

DDR_A_ CAS#<13>
DDR_A_ RAS#<13>

DDR_A_W E#<13>

DDR_A_ DM0
DDR_A_ DM1
DDR_A_ DM2
DDR_A_ DM3
DDR_A_ DM4
DDR_A_ DM5
DDR_A_ DM6
DDR_A_ DM7

DDR_A_ DQS0
DDR_A_ DQS1
DDR_A_ DQS2
DDR_A_ DQS3
DDR_A_ DQS4
DDR_A_ DQS5
DDR_A_ DQS6
DDR_A_ DQS7

DDR_A_DQ S#0
DDR_A_DQ S#1
DDR_A_DQ S#2
DDR_A_DQ S#3
DDR_A_DQ S#4
DDR_A_DQ S#5
DDR_A_DQ S#6
DDR_A_DQ S#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_ A_CAS#
DDR_ A_RAS#

DDR_A_W E#

AK12
AH11
AG17

AB30

AL31
AF30
AK26

AL9
AG7
AK5
AH3

AC28

AJ30

AK33

AL25

AN9
AH8
AM2
AE3

AC29
AK30

AJ33

AM25

AN8

AJ8
AM3
AE2

AJ15
AM17
AM15
AH15
AK15
AN15

AJ18
AF19
AN17

AL17
AG16

AL18
AG18

AL14

AJ17
AK18
AN28
AM28
AH17

AH21

AJ20
AE27

AN20

AL21
AK21
AK22

AL22
AH22
AG22
AF21
AM21
AE21

AL20
AE22
AE26
AE20

U8C

SA_BS_0
SA_BS_1
SA_BS_2

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

SB_BS_0
SB_BS_1
SB_BS_2

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8

SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47

DDR2 SYSTEM MEMORY

SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

SB_CAS#

SB_RAS#

SB_WE#

Calistoga -GSE_FCBGA998

AC31
AB28
AE33
AF32
AC33
AB32
AB31
AE31
AH31
AK31
AL28
AK27
AH30
AL32
AJ28
AJ27
AH32
AF31
AH27
AF28
AJ32
AG31
AG28
AG27
AN27
AM26
AJ26
AJ25
AL27
AN26
AH25
AG26
AM12
AL11
AH9
AK9
AM11
AK11
AM8
AK8
AG9
AF9
AF8
AK6
AF7
AG11
AJ6
AH6
AN6
AM6
AK3
AL2
AM5
AL5
AJ3
AJ2
AG2
AF3
AE7
AF6
AH5
AG3
AG5
AF5

AG19
AG21
AG20

DDR _A_D0
DDR _A_D1
DDR _A_D2
DDR _A_D3
DDR _A_D4
DDR _A_D5
DDR _A_D6
DDR _A_D7
DDR _A_D8
DDR _A_D9
DDR_ A_D10
DDR_ A_D11
DDR_ A_D12
DDR_ A_D13
DDR_ A_D14
DDR_ A_D15
DDR_ A_D16
DDR_ A_D17
DDR_ A_D18
DDR_ A_D19
DDR_ A_D20
DDR_ A_D21
DDR_ A_D22
DDR_ A_D23
DDR_ A_D24
DDR_ A_D25
DDR_ A_D26
DDR_ A_D27
DDR_ A_D28
DDR_ A_D29
DDR_ A_D30
DDR_ A_D31
DDR_ A_D32
DDR_ A_D33
DDR_ A_D34
DDR_ A_D35
DDR_ A_D36
DDR_ A_D37
DDR_ A_D38
DDR_ A_D39
DDR_ A_D40
DDR_ A_D41
DDR_ A_D42
DDR_ A_D43
DDR_ A_D44
DDR_ A_D45
DDR_ A_D46
DDR_ A_D47
DDR_ A_D48
DDR_ A_D49
DDR_ A_D50
DDR_ A_D51
DDR_ A_D52
DDR_ A_D53
DDR_ A_D54
DDR_ A_D55
DDR_ A_D56
DDR_ A_D57
DDR_ A_D58
DDR_ A_D59
DDR_ A_D60
DDR_ A_D61
DDR_ A_D62
DDR_ A_D63

DDR_ A_D[0..63 ] <13>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

Title

Size Do cument Numbe r R ev

Cust om

2

Date: Sheet o f

Compal Electronics, Inc.

Calistoga(2/5)-DDR2

LA-4421P

7 42Monday, Apr il 06, 2009

1

0.2

5

D D

GMCH _CRT_ R

R225 150_0402_1%

R223 150_0402_1%

R222 150_0402_1%

12

12

12

GMCH _CRT_G

GMCH _CRT_B

Close to U8.H25

12

R39 255_0402_1%

C C

+3VS

1 2

R32 10K_0402_5%

1 2

B B

R40 10K_0402_5%

LCT LA_CLK

LCTLB_DATA

R224 100K_0402_5%

GMCH _ENBKL<27>

R38 1.5K_0402_1%

4

U8 F

H27

SDVO_CTRLDATA

J27

SDVO_CTRLCLK

CLK _MCH_3GPLL#<14>
CLK _MCH_3GPLL<14>

GMCH _CRT_ CLK<16>
GMCH _CRT_DATA<16>

GMCH _CRT_B<16>

GMCH _CRT_G<16>

GMCH _CRT_ R<16>

GM CH_C RT_VSYN C<16>
GM CH_C RT_HS YNC<16>

12

LVD S_SCL<15>
LVD S_SDA<15>

GM CH_EN VDD<15>

12

LVD S_ACLK#<15>
LVD S_ACLK<15>

LVD S_A0#<15>
LVD S_A1#<15>
LVD S_A2#<15>

LVD S_A0<15>
LVD S_A1<15>
LVD S_A2<15>

GMCH _CRT_B

GMCH _CRT_G

GMCH _CRT_ R

CR T_IRE F

LCT LA_CLK
LCTLB_DATA
LVD S_SCL
LVD S_SDA

L_IBG

LVD S_ACLK#
LVD S_ACLK

LVD S_A0#
LVD S_A1#
LVD S_A2#

LVD S_A0
LVD S_A1
LVD S_A2

Y26

AA26

H20
H22
A24
A23
E25
F25
C25
D25
F27
D27
H25

H30
G29
F28
E28
G28
H28
K30
K27

K29

D30
C30
A30
A29

G31
F32
D31

H31
G32
C31

F33
D33
F30

E33
D32
F29

J29
J30

G_CLKN
G_CLKP

CRT_DDC_CLK
CRT_DDC_DATA
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
CRT_VSYNC
CRT_HSYNC
CRT_IREF

L_BKLTCTL
L_BKLTEN
L_CLKCTLA
L_CTLBDATA
L_DDC_CLK
L_DDC_DATA
L_VDDEN
L_IBG
L_VBG
L_VREFH
L_VREFL

LA_CLKN
LA_CLKP
LB_CLKN
LB_CLKP

LA_DATAN_0
LA_DATAN_1
LA_DATAN_2

LA_DATAP_0
LA_DATAP_1
LA_DATAP_2

LB_DATAN_0
LB_DATAN_1
LB_DATAN_2

LB_DATAP_0
LB_DATAP_1
LB_DATAP_2

3

EXP_A_COMPI

EXP_A_ICOMPO

SDVO_TVCLKIN#

SDVO_INT#

SDVO_FLDSTALL#

MISC

SDVO_TVCLKIN

SDVO_INT

SDVO_FLDSTALL

SDVO

SDVO_RED#

SDVO_GREEN#

SDVO_BLUE#

SDVO_CLKN

SDVO_RED

SDVO_GREEN

SDVO_BLUE
SDVO_CLKP

TV_DACA
TV_DACB
TV_DACC

TV_IREF

TV_IRTNA

TV

TV_IRTNB

LVDS VGA

TV_IRTNC

TV_DCONSEL0
TV_DCONSEL1

Calisto ga-GSE_ FCBGA 998

R28
M28

N30
R30
T29

M30
P30
T30

P28
N32
P32
T32

N28
M32
P33
R32

A21
C20
E20
G23
B21
C21
D21

G26
J26

PEGCOMP

+1.5VS

+1.5 VS_PC IE

R45

24.9_0402_1%

1 2

Disable TV

2

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

Title

Size Doc umen t Numb er R ev

B

2

Da te: Sheet o f

Compal Electronics, Inc.

Calistoga(3/5)-VGA/LVDS/TV

LA-4421P

8 42Mo nday, Ap ril 06, 2 009

1

0.2

5

+VCCP

D D

C C

+VCCP

B B

A A

W22

W21

W20

W14

AB10
AA10

T25
R25
P25
N25
M25
P24
N24
M24
Y22

V22
U22
T22
R22
P22
N22
M22
Y21

V21
U21
T21
R21
P21
N21
M21
Y20

V20
U20
T20
R20
P20
N20
M20
Y19
P19
N19
M19
Y18
P18
N18
M18
Y17
P17
N17
M17
Y16
P16
N16
M16
Y15
P15
N15
M15
Y14

V14
U14
T14
R14
P14
N14
M14

T10
R10
P10
N10

L10

D1

M10
A18

U8H

VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64

VTT_NCTF1
VTT_NCTF2
VTT_NCTF3
VTT_NCTF4
VTT_NCTF5
VTT_NCTF6

RSVD_3
RSVD_4
RSVD_5
RSVD_6

NCTF

Calistoga-G SE_FCBGA998

4

VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19

CFG_19

RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED14
RESERVED15
RESERVED16
RESERVED17
RESERVED18
RESERVED19
RESERVED20
RESERVED21
RESERVED22
RESERVED23
RESERVED24
RESERVED25

AD25
AC25
AB25
AD24
AC24
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
K14
AD13
Y13
W13
V13
U13
T13
R13
P13
N13
M13
AD12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
AD11
AD10
K10
AN33
AA25
V25
U25
AA22
AA21
AA20
AA19
AA18
AA17
AA16
AA15
AA14
AA13
A4
A33
B2
AN1
C1

K28

K25
K26
R24
T24
K21
K19
K20
K24
K22
J17
K23
K17
K12
K13
K16
K15

+1.5VS

3

U8E

AH33

VSS_1

AK32

AG32

AE32
AC32
AA32

AM31

AJ31

AA31

AL30

AG30

AE30
AC30
AA30

AA29

AK28
AH28
AE28
AA28

AM27

AF27
AB27
AA27

AL26

AH26

W26

AN25
AK25

AG25

AE25

AM22

AJ22

AF22

AM20

AK20
AH20
AF20

W19

AM18

AH18
AF18

AK17

AH16

Y33

VSS_2

V33

VSS_3

R33

VSS_4

G33

VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10

U32

VSS_11

H32

VSS_12

E32

VSS_13

C32

VSS_14
VSS_15
VSS_16
VSS_17

U31

VSS_18

T31

VSS_19

R31

VSS_20

P31

VSS_21

N31

VSS_22

M31

VSS_23

J31

VSS_24

F31

VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30

Y30

VSS_31

V30

VSS_32

U30

VSS_33

G30

VSS_34

E30

VSS_35

B30

VSS_36
VSS_37

U29

VSS_38

R29

VSS_39

P29

VSS_40

N29

VSS_41

M29

VSS_42

H29

VSS_43

E29

VSS_44

B29

VSS_45
VSS_46
VSS_47
VSS_48
VSS_49

U28

VSS_50

T28

VSS_51

J28

VSS_52

D28

VSS_53
VSS_54
VSS_55
VSS_56
VSS_57

Y27

VSS_58

U27

VSS_59

T27

VSS_60

R27

VSS_61

P27

VSS_62

N27

VSS_63

M27

VSS_64

G27

VSS_65

E27

VSS_66

C27

VSS_67

B27

VSS_68
VSS_69
VSS_70
VSS_71

U26

VSS_72
VSS_73
VSS_74
VSS_75
VSS_76

J25

VSS_77

G25

VSS_78

A25

VSS_79

H23

VSS_80

F23

VSS_81

B23

VSS_82
VSS_83
VSS_84
VSS_85

G22

VSS_86

E22

VSS_87

J21

VSS_88

H21

VSS_89

F21

VSS_90
VSS_91
VSS_92
VSS_93
VSS_94

D20

VSS_95
VSS_96

R19

VSS_97
VSS_98
VSS_99
VSS_100

U18

VSS_101

H18

VSS_102

D18

VSS_103
VSS_104

V17

VSS_105

T17

VSS_106

F17

VSS_107

B17

VSS_108
VSS_109

U16

VSS_110

VSS

Calistoga-G SE_FCBGA998

VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185

J16
AL15
AG15
W15
R15
F15
D15
AM14
AH14
AE14
H14
B14
F13
D13
AL12
AG12
H12
B12
AN11
AJ11
AE11
AM9
AJ9
AB9
W9
R9
M9
J9
F9
C9
A9
AL8
AG8
AE8
U8
AA7
V7
R7
N7
H7
E7
B7
AL6
AG6
AE6
AB6
W6
T6
M6
K6
AN5
AJ5
B5
AA4
V4
R4
N4
K4
H4
E4
AL3
AD3
W3
T3
B3
AK2
AH2
AF2
AB2
M2
K2
H2
F2
V1
R1

2

U8G

W33

NC1

AM33

NC2

AL33

NC3

C33

NC4

B33

NC5

AN32

NC6

A32

NC7

AN31

NC8

W28

NC9

V27

NC10

W29

NC11

J24

NC12

H24

NC13

W32

NC14

G24

NC15

F24

NC16

E24

NC17

D24

NC18

K33

NC19

A31

NC20

E21

NC21

C23

NC22

AN19

NC23

AM19

NC24

AL19

NC25

AK19

NC26

AJ19

NC27

AH19

NC28

AN3

NC29

Y9

NC30

J19

NC31

H19

NC32

G19

NC33

F19

NC34

E19

NC35

D19

NC36

C19

NC37

B19

NC38

A19

NC39

Y8

NC40

G16

NC41

F16

NC42

E16

NC43

D16

NC44

C16

NC45

B16

NC46

AN2

NC47

A16

NC48

Y7

NC49

AM4

NC50

AF4

NC51

AD4

NC52

AL4

NC53

AK4

NC54

W31

NC55

AJ4

NC56

AH4

NC57

AG4

NC58

AE4

NC59

AM1

NC60

Calistoga-G SE_FCBGA998

NC

RESERVED26
RESERVED27
RESERVED28
RESERVED29
RESERVED30
RESERVED31
RESERVED32
RESERVED33
RESERVED34
RESERVED35
RESERVED36
RESERVED37
RESERVED38
RESERVED39
RESERVED40
RESERVED41
RESERVED42

1

W30

NC61

Y6

NC62

AL1

NC63

Y5

NC64

Y10

NC65

W10

NC66

W25

NC67

V24

NC68

U24

NC69

V10

NC70

U10

NC71

K18

NC72

Y25
Y24
AB22
AB21
AB19
AB16
AB14
AA12
W24
AA24
AB24
AB20
AB18
AB15
AB13
AB12
AB17

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

Calistoga(4/5)-PWR/GND

LA-4421P

9 42Monday, A pril 06, 2009

1

0.2

2940mA

1

+

C279

2

10U_0805_10V4Z

5

T26
R26
P26
N26

M26

V19

1

1

C274

2

2

10U_0805_10V4Z

1

1

C37

2

0.1U_0402_16V4Z

1

C55

C43

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.5VS

1250mA

1

C32

2

0.1U_0402_16V4Z

+VCCP

780mA

C268

1 2

10mil

0.47U_ 0603_16VY5V

C267

1 2

10mil

0.47U_ 0603_16VY5V

1

+

C273

2

220U_B2_2.5VM_R35

1

1

C57

C38

2

2

4.7U_0 603_6.3V4Z

4.7U_0 603_6.3V4Z

10mil

2

2

0.47U_ 0603_16VY5V

5

C66

1

1

U19
T19

W18

V18
T18
R18

W17

U17
R17

W16

V16
T16
R16
V15
U15
T15

AD33
AD32
AD31
AD30
AD29
AD28
AD27
AC27
AD26
AC26
AB26
AE19
AE18

AF17

AE17

AF16

AE16

AF15

AE15

J14

J10
H10

AE9
AD9

U9
AD8
AD7
AD6

U1_A14

A14
D10

P9
L9

D9

P8
L8

D8

P7
L7

D7

U1_A7

A7
P6

L6
G6
D6
U5

P5

L5
G5
D5

Y4
U4

P4

L4
G4
D4

Y3
U3

P3

L3
G3
D3

Y2
U2

P2

L2
G2
D2

U1_AA1

AA1

U1_F1

F1

10mil

C30

0.47U_ 0603_16VY5V

+VCCP

C44

D D

C C

B B

A A

220U_B2_2.5VM_R35

U8D

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21

VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT36
VTT35
VTT37
VTT38
VTT39
VTT40

4

VCCATVDACA0
VCCATVDACA1
VCCATVDACB0

VCCATVDACB1
VCCATVDACC0
VCCATVDACC1

VCCATVBG
VSSATVBG

VCCDTVDAC

VCCDQTVDAC

VCCDLVDS0
VCCDLVDS1
VCCDLVDS2

VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51

VCCAMPLL

VCCAHPLL
VCCADPLLA
VCCADPLLB

POWER

VCCDHMPLL1
VCCDHMPLL2

VCCTXLVDS0
VCCTXLVDS1

VCCA3GPLL

VCCA3GBG
VSSA3GBG

VCCSYNC
VCCACRTDAC0
VCCACRTDAC1

VSSACRTDAC

VCCALVDS

VSSALVDS

Calistoga-G SE_FCBGA998

4

VCCHV0
VCCHV1
VCCHV2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9

VCC3G0
VCC3G1

VTT41
VTT42
VTT43
VTT44
VTT45

B20
A20
B22
A22
D22
C22
D23
E23
F20
F22
C28
B28
A28
E26
D26
C26
AB33
AM32
AN29
AM29
AL29
AK29
AJ29
AH29
AG29
AF29
AE29
AN24
AM24
AL24
AK24
AJ24
AH24
AG24
AF24
AE24
AN18
AN16
AM16
AL16
AK16
AJ16
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AN4
AM10
AL10
AK10
AH1
AH10
AG10
AF10
AE10
AN7
AM7
AL7
AK7
AJ7
AH7
AN10
AJ10
AD1
AD2
B26
J32
AE5
AD5
D29
C29
U33
T33
V26
N33
M33
J23
C24
B24
B25
B31
B32

P1
L1
G1
U1
Y1

+1.5VS

400mA

2mA

10mA

144mA

Disable TV

20mA

40mA

U1_AB33
U1_AM32

10mil

10mil

10mil

10mil

+1.5VS_MPLL
+1.5VS_HPLL
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS

+2.5VS

+1.5VS_3GPLL
+2.5VS

+2.5VS_CRTDAC

+2.5VS

3

+1.5VS

+3VS

10mil

1

1

C73

C82

C297

1U_0603_10V4Z

150mA

60mA

2

2

1U_0603_10V4Z

1U_0603_10V4Z

1

C81
1U_0603_10V4Z

2

1

C85
1U_0603_10V4Z

2

1

2

45mA
45mA

50mA
50mA

Route +2.5VS fr om GMCH pinN33 to
deco upling ca p <200mil to the edge.

1

1

C269

2

2

C24

10U_0805_10V4Z

0.1U_0402_16V4Z

+1.8V

533 MTS=1720mA

1

1

1

C84

C83

C74

2

2

2

4.7U_0 603_6.3V4Z

1U_0603_10V4Z

4.7U_0 603_6.3V4Z

C39

400mA

70mA
70mA

+VCCP

1

2

1

1

C28

2

2

C27

0.1U_0402_16V4Z

0.022U_0402_16V7K

Route VSSACRTDAC gnd from GMCH to
deco upling ca p ground lead and then
conn ect to the gnd plane.

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

R229

12

10_0603_5%

C25

10U_0805_10V4Z

+2.5VS

CRTDAC: Route FB
within 3" of Cal istoga

2006/08/18 2007/8/18

1

1

C265

2

2

C20

10U_0805_10V4Z

0.1U_0402_16V4Z

+2.5VS

1

2

0.1U_0402_16V4Z

+2.5VS

1

C34

C270

2

10U_0805_10V4Z

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

1

2

C285

2

1

2

10U_0805_10V4Z

2

+1.5VS_MPLL

C288

+1.5VS_PCIE

C283

10U_0805_10V4Z

PCI-E/MEM/PSB PLL decoupling

R46

0_0603_5%

+1.5VS

+1.5VS +1.5VS

+1.5VS

C42

+2.5VS

4.7U_0 603_6.3V4Z

12

1

2

+1.5VS

+1.5VS_HPLL

1

C282

2

0.1U_0402_16V4Z

+1.5VS_DPLLA+1.5VS_DPLLB

0.1U_040 2_16V4Z~D

1

2

1

C35

2

0.1U_0402_16V4Z

clos e pin C29/D29

Compal Electronics, Inc.

Calistoga(5/5)-PWR/GND

LA-4421P

1

C287

2

0.1U_0402_16V4Z

330U_D2E_2.5VM

0.1U_040 2_16V4Z~D

C36

1

+

2

1

1

C292

2

2

220U_B2_2.5VM_R35

+1.5VS_3GPLL

1

1

C54

C56

2

2

10U_0805_10V4Z

0.1U_0402_16V4Z

45mA Max.

R236
0_0603_5%

12

1

2

10U_0805_10V4Z

L10

1 2

FBMA-L10-160808-301LMT_2P

1

C264

2

R239

12

0_0805_5%

+

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

1

+1.5VS+1.5VS_3GPLL

1

C69

@

2

0.1U_0402_16V4Z

45mA Max.

R235
0_0603_5%

1

C281

2

10U_0805_10V4Z

40mA Max.40mA Max.

L9

1 2

330U_D2E_2.5VM

FBMA-L10-160808-301LMT_2P

1

C21

C263

+

2

+2.5VS

1

C271

2

0.01U_0402_25V7K

clos e pin B31

10 42Monday, A pril 06, 2009

1

12

+1.5VS

1

C272

2

0.1U_0402_16V4Z

0.2

5

DDR_A _DQS#[0.. 7]<7>

DDR _A_D[0..6 3]<7>

DDR_A _DM[0..7]<7>

DDR_ A_DQS[0.. 7]<7>

DDR_A _MA[0..13]<7>

D D

+1.8V

2

2

2

C129

C128

1

2.2U_0 603_6.3V4Z

1

+

@

C94

C106

2

220U_B2_2.5VM_R35

C C

+0.9VS

1

C117

2

0.1U_0402_16V4Z

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

1

C86

2

0.1U_0402_16V4Z

RP6

1 8
2 7
3 6
4 5

RP2

1 8
2 7
3 6
4 5

RP3

1 8
2 7
3 6
4 5

1

C119

B B

A A

2

0.1U_0402_16V4Z

DDR_A_MA0
DDR_A_MA13
DDR_C S0#
M_ODT0

DDR_A_MA1
DDR_A_MA3
DDR_A_MA5
DDR_A _CAS#

DDR_A_WE#
DDR_A_BS0
M_ODT1
DDR_C S1#

C110

1

2.2U_0 603_6.3V4Z

1

1

C105

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Layout Note:
Plac e on e cap close to every 2 pullup
resi stor s terminated to +0.9VS

1

C87

C121

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+0.9VS

56_0804_8P4R_5%

56_0804_8P4R_5%

2

C109

1

1

2.2U_0 603_6.3V4Z

2.2U_0 603_6.3V4Z

1

C108

2

0.1U_0402_16V4Z

1

1

C88

C122

2

2

0.1U_0402_16V4Z

RP5

18
27
36
45

RP4

18
27
36
45

RP1

DDR_A_MA12

18
27
36

DDR_A_MA10

45

56_0804_8P4R_5%

C130

1

C107

2

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

DDR_A _RAS#

DDR_A_MA4
DDR_A_MA2
DDR_A_BS1

DDR_C KE1
DDR_A_MA7
DDR_A_MA6

DDR_A_MA11

DDR_A_MA9
DDR_A_MA8

2

1

2.2U_0 603_6.3V4Z

1

C91

C115

2

0.1U_0402_16V4Z

Layout Note:
Plac e near JDIM1

1

2

0.1U_0402_16V4Z

4

1

1

C90

C120

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Layout Note:
Place these resistor
closel y DIMMA,all
trace length<750 mil

3

CLK_SMBDATA<14>

DDR_A_BS2<7>

DDR_A_BS0<7>
DDR_A_WE#<7>

DDR_A_CAS#<7>

CLK_SMBCLK<14>

DDR_C KE0<6>

DDR_C S1#<6>

M_ODT1<6>

+DIMM_VREF

DDR_A _D0
DDR_A _D1

DDR_A _DQS#0
DDR_A _DQS0

DDR_A _D2
DDR_A _D3

DDR_A _D9
DDR_A _D8

DDR_A _DQS#1
DDR_A _DQS1

DDR_A _D10
DDR_A _D11

DDR_A _D16
DDR_A _D17

DDR_A _DQS#2
DDR_A _DQS2

DDR_A _D18
DDR_A _D19

DDR_A _D24
DDR_A _D25

DDR_A_DM3

DDR_A _D26
DDR_A _D27

DDR_C KE0

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A _CAS#
DDR_C S1#

M_ODT1

DDR_A _D32
DDR_A _D33

DDR_A _DQS#4
DDR_A _DQS4

DDR_A _D34
DDR_A _D35

DDR_A _D40
DDR_A _D41

DDR_A_DM5

DDR_A _D42
DDR_A _D43

DDR_A _D48
DDR_A _D49

DDR_A _DQS#6
DDR_A _DQS6

DDR_A _D50
DDR_A _D51

DDR_A _D56
DDR_A _D57

DDR_A_DM7

DDR_A _D58
DDR_A _D59

CLK_SMBDATA
CLK_SMBCLK

+3VS

+1.8V

12

R61

1K_0402_1%

+DIMM_VREF

12

R62

1K_0402_1%

+DIMM_VREF

1

1

C89

C118

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Shar e +DIMM_VREF for

1.DDRII VREF

2.GM CH SM_VREF_0
SM_VREF_1

20mils

1

C111

0.1U_0402_16V4Z

2

1

C112

2.2U_0 603_6.3V4Z

2

+3VS

1

C116

2

0.1U_0402_16V4Z

2

+1.8V +1.8V

JDIM1

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_AS0A426-N4SN-7F

ME@

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106

BA1

108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198

SA0

200

SA1

DIMMA

DDR_A _D4
DDR_A _D5

DDR_A_DM0

DDR_A _D6
DDR_A _D7

DDR_A _D12
DDR_A _D13

DDR_A_DM1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A _D14
DDR_A _D15

DDR_A _D20
DDR_A _D21

DDR_A_DM2

DDR_A _D22
DDR_A _D23

DDR_A _D28
DDR_A _D29

DDR_A _DQS#3
DDR_A _DQS3

DDR_A _D30
DDR_A _D31

DDR_C KE1

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS1
DDR_A _RAS#
DDR_C S0#

M_ODT0
DDR_A_MA13

DDR_A _D36
DDR_A _D37

DDR_A_DM4

DDR_A _D38
DDR_A _D39

DDR_A _D44
DDR_A _D45

DDR_A _DQS#5
DDR_A _DQS5

DDR_A _D46
DDR_A _D47

DDR_A _D52
DDR_A _D53

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_DM6

DDR_A _D54
DDR_A _D55

DDR_A _D60
DDR_A _D61

DDR_A _DQS#7
DDR_A _DQS7

DDR_A _D62
DDR_A _D63

R66 10K_0402_5%

1 2

R65 10K_0402_5%

1 2

R64

M_CLK_DDR0 <6>
M_CLK_DDR#0 <6>

1 2

DDR_C KE1 <6>

DDR_A_BS1 <7>
DDR_A _RAS# <7>
DDR_C S0# <6>

M_ODT0 <6>

M_CLK_DDR1 <6>
M_CLK_DDR#1 <6>

1

0_0402_5%

PM_EXTTS#0 <6>

DDR_A_BS2

DDR_C KE0

R60

1 2

56_0402_5%
R59

1 2

56_0402_5%

5

Layout Note:
Place these resistor
closel y DIMMA,all
trace length
Max=1.3"

4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

2

Title

Size Doc ument Number Re v

B

Date: Sheet of

Compal Electronics, Inc.

DDRII-SODIMMA

LA-4421P

13 42Monday, A pril 06, 2009

1

0.2

5

PCI

SRC

CPU

CLKS EL1

0

FSA

CLKS EL0

MHz

266

MHz

1000

MHz

MHz

33.30

14.318 96.0 48.0

DOT_96
MHz

USB
MHz

FSC FSB REF

CLKS EL2

0 1000 133 33.31 1 4.318 96.0 48.0

0 1001 200 33.30 1 4.318 96.0 48.0

0 1001 166 33.31 1 4.318 96.0 48.0

D D

1 1000 333 33.30 1 4.318 96.0 48.0

1 1000 100 33.31 1 4.318 96.0 48.0

1 1001 400 33.30 1 4.318 96.0 48.0

1 1 1

Res erved

4

+3VM_CK505

1 2

+3VS

+VCCP

R137 0_0805_5%

1 2

R138 0_0805_5%

1

C174

10U_0805_10V4Z

2

+1.05VM_CK505

1

C175

10U_0805_10V4Z

2

1

C172

0.1U_0402_16V 4Z

2

1

C139

0.1U_0402_16 V4Z

2

3

1

C138

0.1U_0402_16V 4Z

2

1

C167

0.1U_0402_16 V4Z

2

1

C148

0.1U_0402_16V 4Z

2

1

C137

0.1U_0402_16 V4Z

2

1

C140

0.1U_0402_16V 4Z

2

1

C146

0.1U_0402_16 V4Z

2

2

1

C160

0.1U_0402_16V 4Z

2

1

C165

0.1U_0402_16 V4Z

2

1

C169

0.1U_0402_16V 4Z

2

1

C173

0.1U_0402_16V 4Z

2

ICH_SMBDATA<19>

ICH_SMB CLK<19>

2N7002DW-T /R7_SOT363-6

+3VS

2N7002DW-T /R7_SOT363-6

2.2K_0402_5%

6 1

3

Q10A

Q10B

+3VS

2

5

1

R72

4

R91

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

SA000020K00 (Silego : SLG8SP556VTR )
SA000020H10 (ICS : ICS9LPRS387AKLFT)

+3VM_CK505

+VCCP

R68

R76

2.2K_0402_5%

C C

B B

A A

FSA

FS C

1 2

R69
0_0402_5%

1 2

R119
0_0402_5%

R98
10K_0402_5%

1 2

R84
0_0402_5%

CPU_BSEL0<4>

CPU_BSEL1<4>

CPU_BSEL2<4>

@

56_0402_5%

1 2

12

1 2

R67
1K_0402_5%

12

R73

1K_0402_5%

@

+VCCP

R113

1K_0402_5%

@

1 2

FSB

1 2

R115
1K_0402_5%

12

R110

@

0_0402_5%

+VCCP

R92

1K_0402_5%

@

1 2

1 2

12

R79
1K_0402_5%

12

R87

@

0_0402_5%

For PC I2_TME :0=Overclocking of CPU and SRC allowed
(ICS o nly) 1=Overclocking of CPU and SRC NOT allowed

C161 22P_0402_50V8J

14.31818MHZ_16P F_DSX840GA

C164 22P_0402_50V8J

Y1

Rou tin g the tr ace at least 1 0mil

5

MCH_CLKSEL0 <6>

CLK_48M_CR<26>

CLK_I CH_48M<19>

CLK_I CH_14M<19>

MCH_CLKSEL1 <6>

MCH_CLKSEL2 <6>

VGATE<19,27,40>

H_STP_CPU#<19>

H_STP_PCI#<19>

CLK_P CI_LPC<27>

CLK_P CI_ICH<17>

For ITP_ EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#

For P CI4_ SEL, 0 = Pin24/25 : DOT96 / DOT96#
Pin28/29 : LCDCLK / LCDCLK#

CLK_XTAL_IN

12

CLK_XTAL_OUT

1 = P in24 /25 : SRC_0 / SRC_0#
P in28/29 : 27M/27M_SS

+3VS+3VS +3VS

R85

10K_0402_5%

@

1 2

ITP_EN PCI4_SEL PCI2 _TME

R89

10K_0402_5%

1 2

4

1 2

1 2

@

1 2

CLK_4 8M_CR

C387

C390

C389

1

@

2

R95

10K_0402_5%

@

R90

10K_0402_5%

C386

10P_0402_50V8J

R75

1 2

10P_0402_50V8J@

1 2

12P_0402_50V8J

1

2

10P_0402_50V8J

R71

10K_0402_5%

1 2

@

R77

10K_0402_5%

1 2

+1.05VM_CK505

R74

1 2

22_0402_5%

1 2

22_0402_5%

1 2

1 2

1 2

C388

@

10P_0402_50V8J

R10433_0402_5%

VGATE

H_STP_CP U#

H_STP_PCI#

CLK_XTAL_IN

CLK_XTAL_OUT

R8633_0402_5%

R8033_0402_5%

FSA

FSB

FS C

PCI2_TME

PCI4_SEL

ITP_EN

U4

55

VDD_SRC

6

VDD_REF

12

VDD_PCI

72

VDD_CPU

19

VDD_48

27

VDD_PLL3

66

VDD_CPU_IO

31

VDD_PLL3_IO

62

VDD_SRC_IO

52

VDD_SRC_IO

23

VDD_IO

38

VDD_SRC_IO

20

USB_0/FS_A

2

FS_B/TEST_MODE

7

REF_0/FS_C/TEST_

8

REF_1

1

CKPWRGD/PD#

11

NC

53

CPU_STOP#

54

PCI_STOP#

5

XTAL_IN

4

XTAL_OUT

13

PCI_1

14

PCI_2

15

PCI_3

16

PCI_4/SEL_LCDCL

17

PCIF_5/ITP_EN

18

VSS_PCI

3

VSS_REF

22

VSS_48

26

VSS_IO

69

VSS_CPU

30

VSS_PLL3

34

VSS_SRC

59

VSS_SRC

42

VSS_SRC

73

VSS

SLG8SP556VT R_QFN72_10X10

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CPU_0#

CPU_1#

SRC_0/DOT_96

SRC_0#/DOT_96#

LCDCLK/27M

LCDCLK#/27M_SS

SRC_2#

SRC_3#

SRC_4#

SRC_6#

SRC_7#

SRC_8/CPU_ITP

SRC_8#/CPU_ITP#

SRC_9#

SRC_10

SRC_10#

SRC_11

SRC_11#

CLKREQ_3#

CLKREQ_4#

CLKREQ_6#

CLKREQ_7#

CLKREQ_9#

SLKREQ_10#

CLKREQ_11#

USB_1/CLKREQ_A#

2007/10/15 2008/10/15

9

SDA

10

SCL

71

CPU_0

70

68

CPU_1

67

24

25

28

29

32

SRC_2

33

35

SRC_3

36

39

SRC_4

40

57

SRC_6

56

61

SRC_7

60

64

63

44

SRC_9

45

50

51

48

47

37

41

58

65

43

49

46

21

Compal Secret Data

CLK_SMBDATA

CLK_SMBCLK

CLK_ CPU_BCLK

CLK_ CPU_BCLK#

CLK_MCH_ BCLK

CLK_MCH_ BCLK#

CLK_M CH_DREFCLK

CLK_M CH_DREFCLK#

MCH_S SCDREFCLK

MCH_S SCDREFCLK#

CLK_MCH_3GP LL

CLK_MCH_3GPL L#

CLK_PCIE_SATA

CLK_PCIE_S ATA#

CLK_PCI E_WLAN

CLK_PCI E_WLAN#

CLK_P CIE_LAN

CLK_PCI E_LAN#

CLK_P CIE_ICH

CLK_P CIE_ICH#

SATA_CLKREQ#

WL AN_CLKREQ#

CLKRE Q_LAN#

MCH_CLK REQ#

Deciphered Date

2

CLK_SMBDATA <13>

CLK_SMBCLK <13>

CLK_C PU_BCLK <4>

CLK_CPU _BCLK# <4>

CLK_MCH_BC LK <6>

CLK_MCH_BC LK# <6>

CLK_M CH_DREFCLK <6>

CLK_M CH_DREFCLK# <6>

MCH_S SCDREFCLK <6>

MCH_S SCDREFCLK# <6>

CLK_MCH_3GPLL <8>

CLK_MCH_3GPLL# <8>

CLK_PCIE_SATA <18>

CLK_PCIE_S ATA# <18>

CLK_PCIE_ WLAN <21>

CLK_PCIE_ WLAN# <21>

CLK_PCI E_LAN <25>

CLK_PCI E_LAN# <25>

CLK_P CIE_ICH <19>

CLK_P CIE_ICH# <19>

SATA_CLKREQ# <19>

WLAN_ CLKREQ# <21>

CLKREQ_LA N# <25>

MCH_CLKRE Q# <6>

Title

Size Document Number Rev

Date : Sheet o f

SRC PORT LIST

PORT

SRC0
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11

MCH_CLK REQ#
WL AN_CLKREQ#
SATA_CLKREQ#
CLKRE Q_LAN#

DEVICE

MCH_DREFCLK
MCH_3GPLL

PCIE_SATA
PCIE_WLAN

PCIE_LAN
PCIE_ICH

R78 10K_0402_5%
R121 10K_0402_5%
R105 10K_0402_5%
R106 10K_0402_5%

12
12
12
12

REQ PORT LIST

DEVICEPORT

REQ_3#
REQ_4#
REQ_6#
REQ_7#
REQ_9#
REQ_10#
REQ_11#
REQ_A#

Compal Electronics, Inc.

Clock Generator CK505

PCIE_SATA
PCIE_WLAN

PCIE_LAN

MCH_3GPLL

LA-4421P

1

14 42Monday, A pril 06, 2009

+3VS

0.2

5

4

3

2

1

LCD POWER CIRCUIT

G

2

+3VS

S

D

1 3

W=20mils

Q22
SI2301BDS_SOT23

+LCDVDD

1

C260

@

4.7U_0805_10V4Z

2

W=20mils

1

C261

0.1U_0402_16V4Z

2

R218
150_0603_5%

2

G

2

+3VALW

12

13

R219
47K_0402_5%

R221

100K_0402_5%

Q20
DTC124EK_SC59

12

2

C262

0.1U_0402_16V4Z

1

+LCDVDD

D D

2N7002_SOT23

GMCH_ ENVDD<8>

C C

12

13

D

Q21

S

+3VS

LCD/PANEL BD. Conn.

+LCDVDD_L

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

C18 0.1U_0603_50V4Z

+INVPWR_B+

+LCDVDD_L

INVT_PWM

BKOFF#

LVDS_SDA
LVDS_SCL

LVDS_ACLK#

LVDS_ACLK

LVDS_A2#
LVDS_A2

LVDS_A1#
LVDS_A1

LVDS_A0#
LVDS_A0

+3VS

B B

A A

5

JLVDS1

22

GND

21

GND

ACES_87213-2000G

ME@

20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

C12

1 2

4.7U_0805_10V4Z

L1 FBMA-L11-201209-221LMA30T_0805

1 2

L8 FBMA-L11-201209-221LMA30T_0805

1 2

INVT_PWM <27>

LVDS_ACLK# <8>

LVDS_ACLK <8>

LVDS_A2# <8>

LVDS_A2 <8>

LVDS_A1# <8>

LVDS_A1 <8>

LVDS_A0# <8>

LVDS_A0 <8>

4

C11

220P_0402_50V7K

LVDS_SCL

B+

+LCDVDD

INVT_PWM

BKOFF#

12

12

C10
220P_0402_50V7K

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

LVDS_SDA

BKOFF#

Compal Secret Data

R7

10K_0402_5%

Deciphered Date

R6

10K_0402_5%

1 2

1 2

2

LVDS_SCL <8>

LVDS_SDA <8>

BKOFF# <27>

Title

Size Doc ument Number Re v

B

Date: Sheet of

Compal Electronics, Inc.

LVDS /INVERTER

LA-4421P

15 42Monday, A pril 06, 2009

1

0.2

A

B

C

D

E

Close to CRT CONN for ESD.

2

2

3

1

2

JVGA_HS

JVGA_VS

@

D18

1

C304
10P_0402_50V8J

@

1 1

L15

BK1608LL121-T_2P

GMCH_CRT_R<8>

GMCH_CRT_G<8>

GMCH_CRT_B<8>

R255

2 2

GMCH_ CRT_HSYNC<8>

Place closed to chipset

GMCH_ CRT_VSYNC<8>

12

12

R253

R250

150_0402_1%

150_0402_1%

1 2

C301 0.1U_0402_16V4Z

39_0402_5%

R249

1 2

R247

1 2

39_0402_5%

12

150_0402_1%

+CRT_VCC

1

5

P

OE#

A2Y

G

SN74A HCT1G125DCKR_SC70-5

3

1 2

C298 0.1U_0402_16V4Z

@

U11

4

+CRT_VCC

5

P

A2Y

G

SN74A HCT1G125DCKR_SC70-5

3

1

C308

2

@

22P_0402_50V8J

1

C303

2

@

22P_0402_50V8J

C310

22P_0402_50V8J

CRT_H SYNC_1

1

U10

OE#

CRT_V SYNC_1

4

1 2

L14

BK1608LL121-T_2P

1 2

L12

BK1608LL121-T_2P

1 2

1

2

@

L13 FCM1608CF-121T03_2P

1 2

L11 FCM1608CF-121T03_2P

1 2

10P_0402_50V8J

10P_0402_50V8J

C302

@

C307

@

1

2

1

2

C306
10P_0402_50V8J

@

1

C300
10P_0402_50V8J

2

PSOT24C_SOT23-3

1

2

@

3

@

D17

PSOT24C_SOT23-3

1

RED

GREEN

BLUE

+3VS

12

3 3

2.2K_0402_5%

GMCH_CRT_DATA<8>

GMCH_CRT_CLK<8>

4 4

R248

12

2.2K_0402_5%

R245

+3VS

2.2K_0402_5%

5

4

2

Q24B

2N7002DW-T/R7_SOT363-6

61

Q24A
2N7002DW-T/R7_SOT363-6

+CRT_VCC

12

R246

3

100P_0402_50V8J

@

C305

12

R251

2.2K_0402_5%

VGA_DDC_DAT

VGA_D DC_CLK

1

2

@

1

C299

2

100P_0402_50V8J

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CRT PORT

+5VS

D2

2

3

RB491D_SOT23-3

C

+CRT_VCC

1.1A_6V_SMD1812P110TF

W=40mils

1

2006/08/18 2007/8/18

F1

2 1

RED

VGA_DDC_DAT
GREEN

JVGA_HS
BLUE

JVGA_VS

VGA_D DC_CLK

Compal Secret Data

Deciphered Date

0.1U_0402_16V4Z

C123

1 2

ME@

JCRT1

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070546FR015SX28XR

D

16
17

Title

Size Doc ument Number Re v

B

Date: Sheet of

Compal Electronics, Inc.

CRT PORT

LA-4421P

16 42Monday, A pril 06, 2009

E

0.2

5

D D

+3VS

R162 8.2K_0402_5%

1 2

R152 8.2K_0402_5%

1 2

R153 8.2K_0402_5%

1 2

R151 8.2K_0402_5%

1 2

R155 8.2K_0402_5%

1 2

R158 8.2K_0402_5%

1 2

R156 8.2K_0402_5%

1 2

R157 8.2K_0402_5%

1 2

C C

B B

+3VS

R160 8.2K_0402_5%

1 2

R159 8.2K_0402_5%

1 2

R132 8.2K_0402_5%

1 2

R133 8.2K_0402_5%

1 2

R126 8.2K_0402_5%

1 2

R131 8.2K_0402_5%

1 2

R127 8.2K_0402_5%

1 2

R130 8.2K_0402_5%

1 2

R129 8.2K_0402_5%

1 2

R150 8.2K_0402_5%

1 2

R146 8.2K_0402_5%

1 2

R154 8.2K_0402_5%

1 2

R125 8.2K_0402_5%

1 2

R128 8.2K_0402_5%

1 2

PCI_D EVSEL#

PCI_S TOP#

PC I_TRD Y#

PC I_FRAME #

PCI_P LOCK#

PC I_I RDY#

PC I_SERR #

PC I_PERR #

PC I_PIRQ A#

PC I_PIRQ B#

PC I_PIR QC#

PC I_PIR QD#

PC I_PIRQ E#

PC I_PIR QF#

PC I_PIRQ G#

PC I_PIR QH#

PC I_REQ#0

PC I_REQ#1

PC I_REQ#2

PC I_REQ#3

PC I_REQ#4

PC I_REQ#5

4

U17 B

E18

AD0

C18

AD1

A16

AD2

F18

AD3

E16

AD4

A18

AD5

E17

AD6

A17

AD7

A15

AD8

C14

AD9

E14

AD10

D14

AD11

B12

AD12

C13

AD13

G15

AD14

G13

AD15

E12

AD16

C11

AD17

D11

AD18

A11

AD19

A10

AD20

F11

AD21

F10

AD22

E9

AD23

D9

AD24

B9

AD25

A8

AD26

A6

AD27

C7

AD28

B6

AD29

E6

AD30

D6

AD31

PC I_PIRQ A#
PC I_PIRQ B# PC I_PIR QF#
PC I_PIR QC#
PC I_PIR QD#

Interrupt I/F

A3

PIRQA#

B4

PIRQB#

C5

PIRQC#

B5

PIRQD#

AE5

RSVD[1]

AD5

RSVD[2]

AG4

RSVD[3]

AH4

RSVD[4]

AD9

RSVD[5]

ICH7_ BGA652

3

PCI

REQ4# / GPIO22
GNT4# / GPIO48

GPIO1 / REQ5#

GPIO17 / GNT5#

GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

MISC

MCH_SYNC#

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

B15
C12
D12
C15

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

C26
A9
B19

G8
F7
F8
G7

AE9
AG8
AH8
F21
AH20

PC I_REQ#0

PC I_REQ#1

PC I_REQ#2

PC I_REQ#3

PC I_REQ#4

PC I_REQ#5

PC I_I RDY#

PCI_R ST#
PCI_D EVSEL#
PC I_PERR #
PCI_P LOCK#
PC I_SERR #
PCI_S TOP#
PC I_TRD Y#

PC I_FRAME #

PLTRST#
CL K_PC I_ICH

PC I_PIRQ E#

PC I_PIRQ G#
PC I_PIR QH#

2

PCI_R ST# <27>

R169

1 2

100K_0402_5%

For EC r equest.

CL K_PC I_ICH <14>

MC H_ICH _SYN C# <6>

For EMI, close to ICH7

PCI_R ST#

PLTRST#

2

@

@

C18 7

C20 3

1

0.1 U_0402_1 6V4Z

0.1 U_0402_1 6V4Z

Pla ce close ly pin A9

CL K_PC I_ICH

@

R167

10_0402_5%

8.2P _0402_50V8D

C186

1 2

1

@

2

1

2

1

PLTRST#

12

R142

100K_0402_5%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

2

PLTRST# <6,19, 21,25>

Title

Size Doc umen t Numb er R ev

Da te: Sheet o f

Compal Electronics, Inc.

ICH7M(1/4)HUB,PCI,HOST

LA-4421P

17 42Mon day, Ap ril 06, 20 09

1

0.2

5

D D

C C

B B

+RTCBATT

R198 1M_0402_5%

1 2

R197 332K_0402_1%

1 2

+RTCBATT

2

C231

0.1U_0402_16V4Z

1

SATA_ITX_C_DRX_P0<24>

SATA_ITX_C_DRX_N0<24>

SATA_ITX_C_DRX_P1<21>

SATA_ITX_C_DRX_N1<21>

SM_INTRUDER#

ICH_IN TVRMEN

HDA _SYNC_AU DIO<22>

HDA_B ITCLK_AUDIO<22>

HDA_R ST_AUDIO#<22>

HDA_S DOUT_AUDIO<22>

SATA_ITX_C_DRX_N0

SATA_ITX_C_DRX_N1

+RTCBATT

1 2

R277 39_0402_5%

1 2

R284 39_0402_5%

1 2

R268 39_0402_5%

1 2

R282 39_0402_5%

3900P_0402_50V7K

C379

1 2

C378

1 2

3900P_0402_50V7K

3900P_0402_50V7K

C382

1 2

C384

1 2

3900P_0402_50V7K

+3VS

R196

1 2

20K_0402_5%

J3

@

C230

1U_0603_10V4Z

1 2

HDA _SYNC_ ICH

HDA_B ITCLK_ICH

HDA_R ST_ICH#

HDA_S DOUT_ICH

39P_0402_50V8J

SATA_ITX_DRX_P0SATA_ITX_C_DRX_P0

SATA_ITX_DRX_N0

SATA_ITX_DRX_P1SATA_ITX_C_DRX_P1

SATA_ITX_DRX_N1

1 2

R204 8.2K_0402_5%

1 2

4

C368

15P_0402_50V8J

12

32.768K_1TJS125BJ4A421P

2

3

C371

15P_0402_50V8J

12

21

3MM

1

C363

@

2

R2124.7K_0402_5%
R20110K_0402_5%

12

Y3

NC

NC

IDE _DIO RDY
SATA_LED#

IDE _IRQ

1

IN

4

OUT

2

C364

39P_0402_50V8J

1

@

SATA_DTX_C_IRX_N0<24>
SATA_DTX_C_IRX_P0<24>

SATA_DTX_C_IRX_N1<21>
SATA_DTX_C_IRX_P1<21>

HDA_S DIN0<22>

CLK_PCIE_SATA#<14>
CLK_PCIE_SATA<14>

ICH_RTCX1

ICH_RTCX2

SATA_LED#<28>

3

12

R288

10M_0402_5%

ICH_R TCRST#

ICH_IN TVRMEN
SM_INTRUDER#

T11 PAD

HDA_B ITCLK_ICH
HDA _SYNC_ ICH

HDA_R ST_ICH#

HDA_S DOUT_ICH

SATA_LED#

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0

SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1
SATA_ITX_DRX_N1
SATA_ITX_DRX_P1

CLK_PCIE_SATA#
CLK_PCIE_SATA

R205

1 2

24.9_0402_1%

IDE _DIO RDY
IDE _IRQ

AF18

AH10
AG10

AG16
AH16

AF16

AH15

AF15

AB1
AB2

AA3

AF3
AE3
AG2
AH2

AF7
AE7
AG6
AH6

AF1
AE1

W4

Y5

W1

Y1
Y2

W3

V3

U3

U5
V4
T5

U7
V6
V7

U1
R6

R5

T2
T3
T1

T4

U17A

RTXC1
RTCX2

RTCRST#

INTVRMEN
INTRUDER#

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK

LAN_RSTSYNC

LAN_RXD0
LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

ACZ_BCLK
ACZ_SYNC

ACZ_RST#

ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2

ACZ_SDOUT

SATALED#

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA_CLKN
SATA_CLKP

SATARBIASN
SATARBIASP

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

ICH7_BGA652

RTC

GPIO49 / CPUPWRGD

LPCCPU

LDRQ1# / GPIO23

LFRAME#

LAN

A20GATE

CPUSLP#

TP1 / DPRSTP#

TP2 / DPSLP#

INIT3_3V#

AC-97/AZALIA

STPCLK#

THERMTRIP#

SATA

IDE

LAD0
LAD1
LAD2
LAD3

LDRQ0#

A20M#

FERR#

IGNNE#

INIT#

INTR

RCIN#

SMI#

DCS1#
DCS3#

DD10
DD11
DD12
DD13
DD14
DD15

DDREQ

NMI

DA0
DA1
DA2

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9

AA6
AB5
AC4
Y6

AC3
AA5

AB3

AE22
AH28

AG27

AF24
AH25

AG26

AG24

AG22
AG21
AF22
AF25

AG23

AF23
AH24

AH22

AF26

AH17
AE17
AF17

AE16
AD16

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

AE15

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

GATEA20
H_A20M#

H_DPRSTP#
H_DPSLP#

H_FER R#

H_PW RGOOD

H_IGNN E#

H_INIT#
H_INT R

KB_RST#

H_SMI#
H_NMI

H_STPCLK#

THRM TRIP_ICH#

2

LPC_A D[0..3] <27>

LPC_FRAME# <27>

GATEA20 <27>
H_A20M# <4>

H_FER R# <4>

H_PW RGOOD <4>

H_IGNN E# <4>

H_INIT# <4>
H_INTR <4>

KB_RST# <27>

H_SMI# <4>
H_NMI <4>

H_STPCLK# <4>

1 2

R200 10K_0402_5%

12

56_0402_5%

12

R202

24.9_0402_1%

R208

+3VS

H_DPRSTP# <4,40>
H_DPSLP# <4>

+VCCP

+VCCP

12

R203

56_0402_5%

Layout note: R202 needs to placed
within 2" of ICH7, R203 must be placed
within 2 " of R194 w/o stub.

1

H_THERMTRIP# <4,6>

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

ICH7M(2/4)LAN,ATA,LPC,RTC

LA-4421P

18 42Monday, A pril 06, 2009

1

0.2

5

4

3

2

1

+3VS

2.2K_0402_5%

+3VALW

PM_BMBUSY#<6>

H_STP_PCI#<14>

H_STP_CPU#<14>

ICH_P CIE_WAKE#<21>

EC_THERM#<27>

12
12

12
12

+3VALW+3VALW

R259

1 2

8.2K_0402_5%

SB_SPKR<22>

SERI RQ<27>

VGATE<14,27,40>

EC_SMI#<27>

USB_OC#0<30>
USB_OC#1<30>

USB_OC#7<30>

12

R261

12

R258

2.2K_0402_5%

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_S MLINK0
ICH_S MLINK1

ICH _RI#

SB_SPKR

ITP_DBRESET#

PM_BMBUSY#

OCP#

H_STP_PCI#
H_STP_CPU#

PM_CLKRUN#

ICH_P CIE_WAKE#

SERIR Q
EC_THERM#

VGATE

EC_SMI#

PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2

PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P2

PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3

PCIE_ITX_PRX_N3
PCIE_ITX_PRX_P3

SB_SPI_CS#

SPI_MOSI
SPI_MISO

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

U17C

C22

SMBCLK

B22

SMBDATA

A26

LINKALERT#

B25

SMLINK0

A25

SMLINK1

A28

RI#

A19

SPKR

A27

SUS_STAT#

A22

SYS_RST#

AB18

GPIO0 / BM_BUSY#

B23

GPIO11 / SMBALERT#

AC20

GPIO18 / STPPCI#

AF21

GPIO20 / STPCPU#

A21

GPIO26

B21

GPIO27

E23

GPIO28

AG18

GPIO32 / CLKRUN#

AC19

GPIO33 / AZ_DOCK_EN#

U2

GPIO34 / AZ_DOCK_RST#

F20

WAKE#

AH21

SERIRQ

AF20

THRM#

AD22

VRMPWRGD

AC21

GPIO6

AC18

GPIO7

E21

GPIO8

ICH7_ BGA652

U17D

F26

PERn1

F25

PERp1

E28

PETn1

E27

PETp1

H26

PERn2

H25

PERp2

G28

PETn2

G27

PETp2

K26

PERn3

K25

PERp3

J28

PETn3

J27

PETp3

M26

PERn4

M25

PERp4

L28

PETn4

L27

PETp4

P26

PERn5

P25

PERp5

N28

PETn5

N27

PETp5

T25

PERn6

T24

PERp6

R28

PETn6

R27

PETp6

R2

SPI_CLK

P6

SPI_CS#

P1

SPI_ARB

P5

SPI_MOSI

P2

SPI_MISO

D3

OC0#

C4

OC1#

D5

OC2#

D4

OC3#

E5

OC4#

C3

OC5# / GPIO29

A2

OC6# / GPIO30

B3

OC7# / GPIO31

ICH7_ BGA652

PCI-EXPRESS

SPI

USB

SMB

SYS

GPIO

GPIO

DIRECT MEDIA INTERFACE

DMI_ZCOMP

DMI_IRCOMP

SATA

GPIO

Clocks

POWER MGT

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

DMI_CLKN
DMI_CLKP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

USBRBIAS#

USBRBIAS

GPIO21 / SATA0GP
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

CLK14
CLK48

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

GPIO16 / DPRSLPVR

TP0 / BATLOW#

PWRBTN#

LAN_RST#

RSMRST#

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25

GPIO35 / SATAREQ#

GPIO38
GPIO39

V26
V25
U28
U27

Y26
Y25
W28
W27

AB26
AB25
AA28
AA27

AD25
AD24
AC28
AC27

AE28
AE27

C25
D25

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

USBR BIAS

D2
D1

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

CLK_P CIE_ICH#
CLK_P CIE_ICH

DMI_IRCOMP

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4

USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

10K_0402_5%

R209

D D

C C

B B

A A

R210

+3VALW

R144

R145

R148

R192

R193

R184

R149

R195

SERIR Q

1 2

8.2K_0402_5%

PM_CLKRUN#

1 2

10K_0402_5%

LINKALERT#

1 2

10K_0402_5%

ITP_DBRESET#

1 2

10K_0402_5%

OCP# PM_SLP_S5#

1 2

10K_0402_5%@

SPI_MISO

1 2

10K_0402_5%@

SB_SPI_CS#

1 2

1K_0402_5%

ICH_P CIE_WAKE#

1 2

8.2K_0402_5%

ICH_LOW_BAT#

12

10K_0402_5%@

SPI_MOSI

1 2

10K_0402_5%

WL AN

LAN

USB_OC#6 USB20_N5
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5

USB_OC#7

USB_OC#0

USB_OC#1

R147

PCIE_PTX_C_IRX_N2<21>
PCIE_PTX_C_IRX_P2<21>
PCIE_ITX_C_PRX_N2<21>
PCIE_ITX_C_PRX_P2<21>

PCIE_PTX_C_IRX_N3<25>
PCIE_PTX_C_IRX_P3<25>
PCIE_ITX_C_PRX_N3<25>
PCIE_ITX_C_PRX_P3<25>

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

R143

10K_0402_5%

1 2

R164

R163

R161

ICH_SMBCLK<14>

ICH_SMBDATA<14>

C341 0.1U_0402_10V7K
C337 0.1U_0402_10V7K

C350 0.1U_0402_10V7K
C346 0.1U_0402_10V7K

+3VALW

AF19
AH18
AH19
AE19

AC1
B2

C20

B24
D23
F22

AA4

AC22

C21

C23

C19

Y4

E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

+3VS

R211

8.2K_0402_5%

1 2

CLK_ICH_14M
CLK_ICH_48M

PM_SLP_S3#
PM_SLP_S4#

ICH_P OK

PM_DPRSLPVR

ICH_LOW_BAT#

PBTN_OUT#

PLTRST#

EC_RSMRST#

R206 10K_0402_5%

1 2

EC_SCI#
AC IN

EC_LID_OUT#

SATA_CLKREQ#

DMI_RXN0 <6>
DMI_RXP0 <6>

DMI_TXN0 <6>
DMI_TXP0 <6>

DMI_RXN1 <6>
DMI_RXP1 <6>

DMI_TXN1 <6>
DMI_TXP1 <6>

CLK_P CIE_ICH# <14>
CLK_P CIE_ICH <14>

R180 24.9_0402_1%

1 2

USB20_N0 <30>
USB20_P0 <30>
USB20_N1 <30>
USB20_P1 <30>
USB20_N2 <24>
USB20_P2 <24>
USB20_N3 <26>
USB20_P3 <26>
USB20_N4 <21>
USB20_P4 <21>
USB20_N5 <21>
USB20_P5 <21>
USB20_N6 <21>
USB20_P6 <21>
USB20_N7 <30>
USB20_P7 <30>

R181 22.6_0402_1%

1 2

Wit hin 50 0 mils

CLK_ICH_14M <14>
CLK_ICH_48M <14>

PM_SLP_S3# <27>

PM_SLP_S4# <27>
PM_SLP_S5# <27>

ICH_P OK <6,27>

PBTN_OUT# <27>

PLTRST# <6,17,21,25>

EC_RSMRST# <27>

EC_SCI# <27>
ACIN <27,34>

EC_LID_OUT# <27>

T10PAD

SATA_CLKREQ# <14>

Wit hin 50 0 mils

+1.5VS

1 2

CMOS
Card reader
WWAN
WiMAX
BT
USB3(Left)

Pla ce c los el y p in B2 Pla ce c los el y p in AC1

CLK_ICH_48M

12

R168

10_0402_5%@

1

C189

4.7P_0402_50V8C@

2

R207
10K_0402_5%

PM_DPRSLPVR <6,40>

USB1(Right)
USB2(Right)

12

R199

10_0402_5%@

1

C240

4.7P_0402_50V8C@

2

CLK_ICH_14M

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

ICH7M(3/4)USB,GPIO,PCIE

LA-4421P

1

19 42Monday, A pril 06, 2009

0.2

5

4

3

2

1

C193

1

2

1

2

1

2

0.1U_04 02_16V4Z

+1.5VS

+1.5VS

+VCCP

0.94A

1

+

2

220U_B2_2.5VM_R35

10mA

+3VALW

14mA

0.27A

+3VS

C235

0.1U_04 02_16V4Z

1

C212

C195

2

0.1U_04 02_16V4Z

0.1U_04 02_16V4Z

1

C213

0.1U_04 02_16V4Z

2

1

C206

0.1U_04 02_16V4Z

2

Deciphered Date

C248

+3VS

+3VALW

+3VALW

U17E

A4

VSS[0]

A23

VSS[1]

B1

VSS[2]

B8

VSS[3]

B11

VSS[4]

B14

VSS[5]

B17

VSS[6]

B20

VSS[7]

B26

VSS[8]

B28

VSS[9]

C2

VSS[10]

C6

VSS[11]

C27

VSS[12]

D10

VSS[13]

D13

VSS[14]

D18

VSS[15]

D21

VSS[16]

D24

VSS[17]

E1

VSS[18]

E2

VSS[19]

E4

VSS[21]

E8

VSS[22]

56mA

+3VS

1

1

2

1

C237

2

C243

0.1U_04 02_16V4Z

2

+RTCBATT

0.1U_04 02_16V4Z

Title

Size Do cument Numbe r R ev

Cust om

Date: Sheet o f

+VCCP

1

1

C247

C242

C244

0.1U_04 02_16V4Z

2

45mA

2

4.7U_08 05_10V4Z

0.1U_04 02_16V4Z

1

C233

2

0.1U_04 02_16V4Z

2

E15

VSS[23]

F3

VSS[24]

F4

VSS[25]

F5

VSS[26]

F12

VSS[27]

F27

VSS[28]

F28

VSS[29]

G1

VSS[30]

G2

VSS[31]

G5

VSS[32]

G6

VSS[33]

G9

VSS[34]

G14

VSS[35]

G18

VSS[36]

G21

VSS[37]

G24

VSS[38]

G25

VSS[39]

G26

VSS[40]

H3

VSS[41]

H4

VSS[42]

H5

VSS[43]

H24

VSS[44]

H27

VSS[45]

H28

VSS[46]

J1

VSS[47]

J2

VSS[48]

J5

VSS[49]

J24

VSS[50]

J25

VSS[51]

J26

VSS[52]

K24

VSS[53]

K27

VSS[54]

K28

VSS[55]

L13

VSS[56]

L15

VSS[57]

L24

VSS[58]

L25

VSS[59]

L26

VSS[60]

M3

VSS[61]

M4

VSS[62]

M5

VSS[63]

M12

VSS[64]

M13

VSS[65]

M14

VSS[66]

M15

VSS[67]

M16

VSS[68]

M17

VSS[69]

M24

VSS[70]

M27

VSS[71]

M28

VSS[72]

N1

VSS[73]

N2

VSS[74]

N5

VSS[75]

N6

VSS[76]

N11

VSS[77]

N12

VSS[78]

N13

VSS[79]

N14

VSS[80]

N15

VSS[81]

N16

VSS[82]

N17

VSS[83]

N18

VSS[84]

N24

VSS[85]

N25

VSS[86]

N26

VSS[87]

P3

VSS[88]

P4

VSS[89]

P12

VSS[90]

P13

VSS[91]

P14

VSS[92]

P15

VSS[93]

P16

VSS[94]

P17

VSS[95]

P24

VSS[96]

P27

VSS[97]

ICH7_BGA652

Compal Electronics, Inc.

ICH7M(4/4)POWER/GND

LA-4421P

1

VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

20 42Monday, April 0 6, 2009

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

0.2

ICH_ V5REF_R UN

6mA

+1.5VS

0.77A

C367

1

C381

2

10U_0805_10V4Z

C188

1

+

C228

2

0.1U_04 02_16V4Z

220U_B2_2.5VM_R35

+1.5VS_DMIPLL

1

C246

2

0.01U_0402_25V7K

1

C239

2

0.1U_04 02_16V4Z

1

2

1

2

Place clo sely pin
D28,T28,AD28.

Place clo sely pin AG5 .

Place clo sely pin AG9 .

10mA

D D

100_0402_5%

10_0402_5%

C C

B B

A A

+3VS+5VS

12

R189

R186

D12

@

RB751V-40TE17_SOD323-2

1 2

ICH_ V5REF_R UN

1

C215

1U_0603_10V4Z

2

+3VALW+5VALW

12

D10

@

RB751V-40TE17_SOD323-2

1 2

ICH_ V5REF_SUS

1

C207

0.1U_04 02_16V4Z

2

+1.5VS

50mA

+5VS +3VS +1.5VS +VCCP

1

1

C398

C257

2

2

0.1U_04 02_16V4Z

0.1U_04 02_16V4Z

Place clo sely pin AG28 within 100mlis.

1

C399

2

R291

1 2

0.5_0805_1%

+1.5VS

+3VALW

0.1U_04 02_16V4Z

1

C400

2

0.1U_04 02_16V4Z

+1.5VS_ DMIPLLR

0.1U_04 02_16V4Z

C217

R290

1 2

0_0805_5%

1

C241

2

0.1U_04 02_16V4Z

1

2

0.1U_04 02_16V4Z

+3VS

+1.5VS

ICH_ V5REF_SUS

10mA

0.1U_04 02_16V4Z

1

C216

C204

2

0.1U_04 02_16V4Z

C192

0.1U_04 02_16V4Z

+1.5VS_DMIPLL

+1.5VS

0.64A

C245

0.1U_04 02_16V4Z

+1.5VS

C238

1U_0603_10V4Z

+3VS

1

2

+3VS

1

2

1

2

1

2

EMI Request

5

4

U17F

G10

AD17

F6

AA22
AA23
AB22

AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28

D26
D27
D28
E24
E25
E26

F23

F24
G22
G23
H22
H23

J22

J23
K22
K23

L22

L23

M22
M23

N22
N23
P22
P23
R22
R23
R24
R25
R26

T22

T23

T26

T27

T28
U22
U23
V22
V23

W22
W23

Y22
Y23

B27

AG28

AB7

AC6
AC7
AD6

AE6
AF5
AF6

AG5
AH5

AD2

AH11

AB10

AB9

AC10
AD10

AE10
AF10

AF9

AG9
AH9

E3

C1

AA2

Y7

V5

V1
W2
W7

ICH7_BGA652

1

C232

0.1U_04 02_16V4Z

2

0.1U_04 02_16V4Z

V5REF[1]

V5REF[2]

V5REF_Sus

Vcc1_5_B[1]
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

Vcc3_3[1]

VccDMIPLL

Vcc1_5_A[1]
Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

VccSATAPLL

Vcc3_3[2]

Vcc1_5_A[10]
Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

VccSus3_3[19]

VccUSBPLL

VccSus1_05/VccLAN1_05[1]
VccSus1_05/VccLAN1_05[2]

VccSus3_3/VccLAN3_3[1]
VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

Vcc3_3 / VccHDA

VccSus3_3/VccSusHDA

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

VccSus3_3[1]

VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

VccSus3_3[7]
VccSus3_3[8]

VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

Vcc1_5_A[19]

Vcc1_5_A[20]

Vcc1_5_A[21]

Vcc1_5_A[22]

Vcc1_5_A[23]

Vcc1_5_A[24]

Vcc1_5_A[25]

VccSus1_05[1]

VccSus1_05[2]
VccSus1_05[3]

Vcc1_5_A[26]

Vcc1_5_A[27]

Vcc1_5_A[28]

Vcc1_5_A[29]

Vcc1_5_A[30]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

L11

Vcc1_05[1]

L12

Vcc1_05[2]

L14

Vcc1_05[3]

L16

Vcc1_05[4]

L17

Vcc1_05[5]

L18

Vcc1_05[6]

M11

Vcc1_05[7]

M18

Vcc1_05[8]

P11

Vcc1_05[9]

P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

U6

R7

AE23
AE26
AH26

AA7

Vcc3_3[3]

AB12

Vcc3_3[4]

AB20

Vcc3_3[5]

AC16

Vcc3_3[6]

AD13

Vcc3_3[7]

AD18

Vcc3_3[8]

AG12

Vcc3_3[9]

AG15

Vcc3_3[10]

AG19

Vcc3_3[11]

A5

Vcc3_3[12]

B13

Vcc3_3[13]

B16

Vcc3_3[14]

B7

Vcc3_3[15]

C10

Vcc3_3[16]

D15

Vcc3_3[17]

F9

Vcc3_3[18]

G11

Vcc3_3[19]

G12

Vcc3_3[20]

G16

Vcc3_3[21]

W5

VccRTC

P7

A24
C24
D19
D22
G19

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

AB17
AC17

T7
F17
G17

AB8
AC8

K7

C28
G20

A1
H6
H7
J6
J7

2006/08/18 2007/8/18

3

1

C222

C227

2

1U_0603_10V4Z

1

2

1

C225

0.1U_04 02_16V4Z

2

1

C224

0.1U_04 02_16V4Z

2

1 2

C236 0.1U_0402_16V4Z

1

C214

0.1U_04 02_16V4Z

2

Compal Secret Data

A

B

C

D

E

Mini-Express Card for WLAN

GND2

+3VS

GND2

+1.5VS

1

4.7U_0805_10V4Z

2

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

J2

@

12

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

C158

JOPEN

0.1U_0402_16V4Z

+3VS_WWAN

WXMIT_OFF#

1

C190

2

+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

1

C151

0.01U_0402_25V7K

2

R252 0_0805_5%

1 2

WL_O FF#
PLTRST#

1 2

R124

1 2

R122

@

WLAN_LED#

BT_LED#

WWAN_LED#

WXMIT_OFF# <27>

USB20_N4 <19>

+1.5VS

0.1U_0402_16V4Z

USB20_P4 <19>

1

C168

2

WWAN_LED#

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0_0402_5%

0_0402_5%

+1.5VS

+1.5VS

+1.5VS+3VALW

C

+3VS

+1.5VS

WL_O FF# <27>
PLTRST# <6,17,19,25>

+3VS

+3VALW

USB20_N5 <19>
USB20_P5 <19>

D6

21

RB751V_SOD323

D5

21

RB751V_SOD323

BT@

D4

21

RB751V_SOD323

WWAN@

0.1U_0402_16V4Z

1

C159

2

2006/08/05 2007/08/05

WW_LED# <24>

BT MODULE CONN

BT_OFF#<27>

BT_LED#

Q11

DTC124EK_SC59

BT@

Compal Secret Data

Deciphered Date

+5VS

R254
10K_0402_5%

BT@

1 2
13

Q25

2

12

R102
10K_0402_5%

@

BT@

DTC124EK_SC59

USB20_N6<19>
USB20_P6<19>

+3VS +3VS_BT

USB20_N6
USB20_P6

Title

Size Doc ument Number Re v

Date: Sheet of

BT@

Q26
SI2301BDS_SOT23

S

G

2

BTON_LED

BT_ACTIVE
WLAN_ACTIVE

D

13

0.1U_0402_16V4Z

+3VS_BT

BT@

C309

12

JP5

1

1

GND

2

2

3

3

4

4

5

5

6

6

7

7

8

8

GND

ACES_87213-0800G

ME@

Compal Electronics, Inc.

Mini-Card/BT CONN

LA-4421P

E

9

10

21 42Monday, A pril 06, 2009

0.2

2

13

D

+3VS_WLAN

1

C145

4.7U_0805_10V4Z

1 1

2 2

2

ICH_P CIE_WAKE#<19>

WLAN_CLKREQ#<14>

1

C178

0.1U_0402_16V4Z

2

ICH_P CIE_WAKE# +3VS_WLAN

BT_ACTIVE
WLAN_ACTIVE

WLAN _CLKREQ#

R182 0_0402_5%@

1 2

R174 0_0402_5%@

1 2

CLK_P CIE_WLAN#<14>

CLK_P CIE_WLAN<14>

PCIE_PTX_C_IRX_N2<19>
PCIE_PTX_C_IRX_P2<19>

PCIE_ITX_C_PRX_N2<19>

PCIE_ITX_C_PRX_P2<19>

+3VS_WLAN

1 2

C1630.1U_0402_16V4Z

JP14

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

ACES_88910-5204

ME@

Mini-Express Card for WWAN

+3VS_WWAN

WWAN@

1

C149

0.1U_0402_16V4Z

2

SB RX+

SB RX-

SATA_DTX_C_IRX_P1<18>

SATA_DTX_C_IRX_N1<18>

3 3

SB TX­SB TX+

+3VS_WWAN

WWAN@

1

C200

2

For EMI request

0.1U_0402_16V4Z

UIM_VPP
UIM_DATA

4 4

+UIM_PWR

Reserv e for SIM card does not meet rise time
and pu ll-up is needed.

1

WWAN@

C153

2

10U_0805_10V4Z

SATA_DTX_C_IRX_P1
SATA_DTX_C_IRX_N1

SATA_ITX_C_DRX_N1<18>
SATA_ITX_C_DRX_P1<18>

+3VS_WWAN

PIN 45 NC for SATA SSD DA/DSS

TO EC

R228

@

DETECTION<27>

JP1

4

GND

5

VPP

6

I/O

7

DET

12

10K_0402_5%

TAITW_PMPAT6-06GLBS7N14N0 ME@

A

EC_TX_P80_DATA<27>

EC_RX_P80_CLK<27>

1

C202

WWAN@

0.01U_0402_25V7K

2

3900P_0402_50V7K

C318

1 2
1 2

C319 3900P_0402_50V7K

SATA_ITX_C_DRX_N1
SATA_ITX_C_DRX_P1

R117100K_0402_5% @

1 2

1

VCC

2

RST

3

CLK

8

GND

9

GND

SATA_DTX_IRX_P1
SATA_DTX_IRX_N1

J5

2

JUMP_43X39@
J6

2

JUMP_43X39@

+UIM_PWR
UIM_RST
UIM_CLK

JP13

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

WWAN@

49

49

51

51

53

GND1

ACES_88910-5204

ME@

1

C266

2

B

1U_0603_10V4Z

112

112

5

4

3

2

1

+5VS

D D

INT _MIC_ L<28>

C C

R26 0

0_0 805_5%

12

C33 0

@

10U _080 5_10V4Z

+5VAM P

1

1

2

2

0.1 U_04 02_16V 4Z

+MI C2_ VREFO

Adjustable Output

U1 4

1

IN

2

GND

3

SHDN

<BO M Stru cture>

G919 1-475T1U _SOT23- 5

@

C3 29

12

R18 8

4.7 K_0402 _5%

1

C20 9

47P _0402_ 50V8J

2

GN DA

OUT

BYP

5

4

INT _MIC _L

+5V DDA_ COD EC

1

1

@

C32 3

2

2

@

0.0 1U_0 402_25V7K

C36 1

4.7 U_08 05_10V4 Z

+5VAM P

J4

@

12

JO PEN

D2 2

RB7 51V_ SOD323

4.7 K_0402 _5%

Intern al MIC / Array MIC

EXT_M IC_L<2 3>

EXT_M IC_R<23>

+5V DDA_ COD EC

+MI C1_ VREFO_L

21

12

R26 6

21

D2 3
RB7 51V_ SOD323

12

R27 9

4.7 K_0402 _5%

C34 3

@

22P _0402_ 50V8J

INT _MIC _L

1

2

1 2

1 2

extern al MIC

R14 0

1 2

0_0 402_5%

R26 9

1 2

R13 6

0_0 402_5%

1 2

R17 1

1 2

R13 5

1 2

0_0 402_5%

0_0 402_5%

0_0 402_5%

MIC Sense
R271 place near pin13
Capless HP Sense
R170 place near pin34

GNDAG ND

Pin Assi gnment

LINE-OUT (Pin35 /36)

B B

Capless HP-OUT (Pin32/3 3)

LINE1 (P in23/24)

MIC1(Pin 21/22)

MONO-OUT (Pin37)

MIC2(Pin 16/17)

Location Function

Internal

External

Int Spea ker

Headphon e out

External

External

Mic in

Internal

Internal

Internal Mic

0.1 U_04 02_16V 4Z

PC Beep

LIN E_OU TL

EC Beep

BEE P#<27>

A A

SB_ SPKR<19>

ICH Beep

5

R26 7

1 2

47K _0402_5 %

R26 4

1 2

47K _0402_ 5%

10K _0402_5 %

R27 0

12

1

C36 2

0.1 U_04 02_16V4 Z

2

C34 8

1 2

0.1 U_04 02_16V 4Z

PC_ BEEPPC_ BEEP1

4

LIN E_O UTR

HDA _RST _AU DIO#

HD A_S YN C_AU DIO

1 2

R26 2

@

33_ 0402_5%

1

1

C34 0

C33 1

2

2

@

@

22P _0402_ 50V8J

22P _0402_ 50V8J

1 2

R27 81K _0402 _5%

R26 51K _0402 _5%

HDA _BI TCLK _AUDI O<18>

HDA _SDO UT_ AUDI O<18>

HDA _RST _AU DIO#<18>

HD A_S YN C_AU DIO< 18>

MIC _JD<23>

PLU G_IN<23>

EA PD<27>

+5VAMP

HDA _BI TCLK _AUD IO

R28 01K_ 0402_5%

HD A_S DIN 0<18>

EMI

2.2 U_06 03_6.3V 6K

MIC _INT L

2.2 U_06 03_6.3V 6K

1 2

R2 63 3 9_04 02_5%

1 2

FBMA -L11-1608 08-800LM T_0603

C35 2

12

C35 3

12

C35 42.2 U_06 03_6.3V 6K

12

C35 52.2 U_06 03_6.3V 6K

12

C34 5

100 P_0402 _50V8J

1 2

HDA _RST _AU DIO#

HD A_S YN C_AU DIO

12

R27 120 K_040 2_1%

12

R17 05.1 K_0402 _1%

R1 660_ 0402_5 %

1 2

MIC _IN L

MIC _IN R

MIC_E XTL_C

MI C_EXTR_ C

PC_ BEEP

SEN SEA

SEN SEB

L16

+5V DDA_ COD EC

U1 5

AVDD125AVDD2

14

LINE2-L

15

LINE2-R

16

MIC2_L

17

MIC2_R

23

LINE1_L

24

LINE1_R

21

MIC1_L

22

MIC1_R

12

BEEP_IN

6

BITCLK

5

SDATA_OUT

8

SDATA_IN

11

RESET#

10

SYNC

2

GPIO0/DMIC_DATA1/2

3

GPIO1/DMIC_DATA3/4

13

SENSE A

34

SENSE B

47

EAPD

43

NC

4

DVSS

7

DVSS

ALC 272- GR_LQ FP48

1

C32 7

2

38

1

C32 5

2

@

0.1 U_04 02_16V 4Z

+3V DD_C ODE C

1

9

DVDD

DVDD_IO

MONO_OUT

DMIC_CLK1/2

DMIC_CLK3/4

LINE2_VREFO

LINE1_VREFO

MIC1_VREFO

MIC2_VREFO

10U _080 5_10V4Z

LOUT1_L

LOUT1_R

LOUT2_L

LOUT2_R

SPDIFO1

SPDIFO2

HPOUT_L

HPOUT_R

CPVREF

VREF

JDREF

AVSS1
AVSS2

CBN

CBP

Place ne ar Pin9

1

1

C32 6

C33 6

2

2

0.1 U_04 02_16V 4Z

C_L INE _OUTL

35

C_L INE _OUTR

36

39

41

48

45

33

32

37

46

44

20

18

28

19

31

27

40

30

29

26
42

+MI C1_ VREFO_L

+MI C2_ VREFO

C3 28 2 .2U _0603 _6.3V4

1 2

C33 2 2 .2U_ 0603_ 6.3V4

+5V DDA_ COD EC+3VS +3V DD_C ODE C

1

C34 4

2

Place ne ar Pin25 Place near Pi n38Place ne ar Pin1

10U _080 5_10V4Z

C32 4 0 .01U _0603 _16V7K

1 2

C32 2 0 .01U _0603 _16V7K

1 2

12

R17 562 _0402 _5%

12

R18 362 _0402 _5%

1 2

C34 9

0.1 U_04 02_16V 4Z

HP_ OUTL <2 3>

HP_ OUTR <23>

12

R2 57
20K _0402_1 %

1

2

10U _080 5_10V4Z

LIN E_OU TL

LIN E_O UTR

C32 1

1

2

0.1 U_04 02_16V 4Z

2

C33 4

1

Int ernal Speaker

Headph one

1

C33 9

2

10U _080 5_10V4Z

0.1 U_04 02_16V4 Z

Close Pin27

W=40mi l

1

C3 60

1

2

C33 8

4.7 U_08 05_10V4 Z

2

2

C34 7

0.4 7U_0 603_ 16VY5V

1

3

U1 6

16

VDD

6

PVDD

15

GA IN0

GA IN1

PVDD

2

GAIN0

3

GAIN1

5

LIN-

17

RIN-

9

LIN+

7

RIN+

2

C3 51

0.4 7U_0 603_ 16VY5V

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

NC

19

SHUTDOWN

8

LOUT-

14

ROUT-

4

LOUT+

18

ROUT+

1

GND

11

GND

13

GND

20

GND

21

GND

10

BYPASS

TPA 6017 A2PWPR_ TSSOP20

2008/03/25 2008/04/

EC_ MUTE#

20mil

2

C3 42

0.4 7U_0 603_ 16VY5V

1

Compal Secret Data

Deciphered Date

2

SPK L-

SPK R-

SPK L+

SPK R+

EC_M UTE# < 27>

SPK L- <23>

SPK R- <2 3>

SPKL + <23>

SPK R+ < 23>

GAIN0 GAIN1
0 0 6dB
0 1 10dB
1 0 15.6dB
1 1 21.6dB

+5VAMP +5VAMP

R19 4

@

100 K_0402 _5%

1 2

R28 3

100 K_0402 _5%

1 2

Compal Electronics,Ltd.

Title

HD Audio Codec_ALC272

Size Doc ume nt N umber Re v

C

Dat e: Sh eet o f

KIWB1/ B2_LA4601P

1

R1 91

100 K_0402 _5%

1 2

GA IN1GA IN0

R2 81

100 K_0402 _5%

@

1 2

22 42Mon day, Apr il 06, 2009

0. 1

5

4

3

2

1

D8

3

1

2

PSOT24C_SOT23-3

@

D D

SPKL+<22>
SPKL-<22>
SPKR+<22>
SPK R-<22>

C C

SPKL+ SPK_L1+
SPKL­SPKR+
SPK R-

R176 0_0402_5%

1 2

R177 0_0402_5%

1 2

R178 0_0402_5%

1 2

R179 0_0402_5%

1 2

20mil

Speaker Conn.

SPK_L1­SPK_R1+
SPK _R1-

C19 6 22 P_0402_50 V8J@

1

2

D9

1

PSOT24C_SOT23-3

@

C19 8 22 P_0402_50 V8J@

C19 7 22 P_0402_50 V8J@

1

1

2

2

3

2

ME@

ACE S_87213-0400G

4

6

4

GND

3

5

3

GND

2

2

1

1

JP7

C19 9 22 P_0402_50 V8J@

1

2

W=20mils

EXT_MIC_L<22>

W=20mils

EXT_MIC_R<22>

MIC _JD<22>

EXT_MIC_L

47P_0402_50V8J

EXT_MIC_R

47P_0402_50V8J

MIC _JD

1

C226

2

1

C205

2

L5

1 2

FBMA-L10-160808-121LMT_2P

L4

1 2

FBMA-L10-160808-121LMT_2P

EXT_MIC_L-2

1

C220

@

10P_0402_50V8J

2

GN DAGN DA

EXT_MIC_R-2

1

C335

@

10P_0402_50V8J

2

GN DAGN DA

1

C33310P_0402_50V8J

@

2

GN DA

Audio Jack

MIC IN

JM IC1

1
2

3

GN DAGN DA

2

3

@

D11

PSOT24C _SOT23-3

GN DA

1

4

5

6

G

SINGA _2SJ- 0960-C02

ME@

B B

W=20mils

HP_ OUTL<22>

HP_ OUTR<22>

PL UG_IN<22>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

HP_ OUTL

HP_ OUTR

PL UG_IN

2008/03/25 2008/04/

Compal Secret Data

Deciphered Date

L7

1 2

FBMA-L10-160808-121LMT_2P
L6

1 2

FBMA-L10-160808-121LMT_2P

220P_0402_50V7K

1

2

GN DA

2

C36610P_0402_50V8J

@

1 2

GN DA

D13

C234

@

220P_0402_50V7K

C229

1 2

Headphone

JH P1

PL-OUT

PR-O UT

2

3

PSOT24C _SOT23-3

GN DA

1

Title

Size Doc umen t Numb er R ev

Cu stom

Da te: Sheet o f

1
2

3

4

5

6

G

SINGA _2SJ- 0960-C02

ME@

Compal Electronics,Ltd.

AMP,Audio speaker CONN

KIWB1/B2_LA4601P

1

GN DA

0.1

23 42Mo nday, Ap ril 06, 2 009

A

B

C

D

E

F

G

H

1 1

LED

CMOS Camera CONN

+5VS

12

R41
10K_0402_5%

CMOS@

1

OUT

CMOS_OFF#<27>

2 2

2

IN

GND

3

CMOS1

Q5
DTC124EKAT146_SC59-3

CMOS@

SI2301BDS-T1-E3_SOT23-3

CMOS@

S

D

+5V_CMOS_R

13

G

Q23

2

C277

CMOS@

0.01U_0402_25V7K

1 2

USB20_N2<19>
USB20_P2<19>

+5VS

1

C23

2

1000P_0402_50V7K

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C26

2

R234

CMOS@

0_0603_5%

CMOS@

USB20_N2
USB20_P2

1

2

1U_0603_10V4Z

C276

C22

+5V_CMOS

1

2

2

3

1

10U_0805_10V4Z

1

C19

2

@

D16
PSOT24C_SOT23-3

JP2

1

1

2

2

3

3

4

4

5

5

6

GND1

7

GND2

ACES_88266-05001

ME@

+5VALW

+5VALW

+3VALW

+5VS

+5VALW

R214

510_0402_5%

R213

510_0402_5%

R216

300_0402_5%

R215

510_0402_5%

R4

510_0402_5%

LED3

12

2 1

HT-F196BP5_WHITE
LED2

2 1

12

HT-F196BP5_WHITE

LED5

12

HT-191UD-DT_AMBER_0603

LED4

12

2 1

HT-F196BP5_WHITE

LED1

12

2 1

HT-F196BP5_WHITE

Whit e

Whit e

Amber

12

Whit e

Whit e

PWR_LED# <27>

CHAR GE_LED0# <27>

CHAR GE_LED1# <27>

WW_LED# <21>

PWR_LED# <27>

SATA HDD Conn.

3 3

SATA_DTX_C_IRX_N0<18>

SATA_DTX_C_IRX_P0<18>

SATA_DTX_C_IRX_N0

SATA_DTX_C_IRX_P0

SATA_ITX_C_DRX_P0<18>
SATA_ITX_C_DRX_N0<18>

1 2

1 2

C383

3900P_0402_50V7K

3900P_0402_50V7K

C380

SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0

SATA_DTX_IRX_N0

SATA_DTX_IRX_P0

+3VS

+5VS

JP10

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12
V1222GND

SUYIN_1 27085FR0 22G211ZR

ME@

GND

24
23

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2006/08/18 2007/8/18

E

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

B

F

Date: Sheet of

Compal Electronics, Inc.

SSD,CMOS CONN\LED

LA-4421P

G

24 42Monday, A pril 06, 2009

H

0.2

A

LAN_D I

LAN_CS

4 4

PCIE_PTX_C_IRX_P3<19>

PCIE_PTX_C_IRX_N3<19>

CLKREQ_LAN#<14>

+3VS

3 3

12

R11
1K_0402_5%

ISOLATEB

R12
15K_0402_5%

LAN_X1 LAN_X2

1

C253

30P_0402_50V8J

2

Place Close to Chip

C254 0.1U_0402_10V7K

12

C255 0.1U_0402_10V7K

12

PCIE_ITX_C_PRX_P3<19>

PCIE_ITX_C_PRX_N3<19>

CLK_P CIE_LAN<14>

CLK_P CIE_LAN#<14>

LAN_WAKE#<27>

Y2

1 2

25MHZ_20P

+3V_LAN

R9 10K_0402_5%

1

C252

30P_0402_50V8J

2

PCIE_PTX_IRX_P3

PCIE_PTX_IRX_N3

PLTRST#<6 ,17,19,21>

R217 2.49K_0402_1%

1 2

12

ISOLATEB

LAN_X1
LAN_X2

B

1 2

R14 3.6K_0402_5%

1 2

R13 1K_0402_5%

U1

20

HSOP

21

HSON

15

HSIP

16

HSIN

17

REFCLK_P

18

REFCLK_M

25

CLKREQB

27

PERSTB

46

RSET

26

LANWAKEB

28

ISOLATEB

41

CKXTAL1

42

CKXTAL2

23

NC

24

NC

7

GND

14

GND

31

GND

47

GND

22

GNDTX

RTL8103EL-GR_LQFP48_7X7

RTL8103EL-GR

+3V_LAN

LED3/EEDO

LED2/EEDI/AUX

LED1/EESK

EECS

LED0

MDIP0
MDIN0
MDIP1
MDIN1

VCTRL12A

VDDTX
DVDD12
DVDD12
DVDD12
DVDD12

VCTRL12D

VDD33
VDD33

AVDD33

NC
NC
NC
NC

NC

NC

NC

NC
NC

33

LAN_D I

34

LAN_SK_LAN_LINK#

35

LAN_CS

32

LAN_A CTIVITY#

38

LAN_MDI0+

2

LAN_MDI0-

3

LAN_MDI1+

5

LAN_MDI1-

6
8
9
11
12

4

VCTRL12

48

19
30
36
13
10

39

44
45

29
37

1
40
43

+EVDD12
+LAN_VDD12

+LAN_VDD12

+3V_LAN

C

Clos e to Pin10,13,30,36

0.1U_0402_16V4Z

2

C6

1

0.1U_0402_16V4Z

2

C16

1

D

2

C250

1

0.1U_0402_16V4Z

+LAN_VDD12

2

C14

0.1U_0402_16V4Z

1

Clos e to Pin1,37,29

0.1U_0402_16V4Z

2

C9

1

0.1U_0402_16V4Z

2

C4

1

E

+3V_LAN

2

C15

1

0.1U_0402_16V4Z

Clos e to Pin48

Clos e to Pin45

VCTRL12

Clos e to Pin19

1U_0603_10V4Z

+EVDD12

2

C259

1

0.1U_0402_16V4Z

2

C258

1U_0603_10V4Z

1

2

C256

1

0.1U_0402_16V4Z

+LAN_VDD12

2

C251

1

1

C249

10U_0805_10V4Z@

2

2 2

C3 0.01U_0402_25V7K

1 2

C5 0.01U_0402_25V7K

1 2

+3VALW

12

1 1

13

EN_WOL<27>

EN_WOL

2N7002_SOT23

D

2

G

Q3

S

@

A

R10
33K_0402_5%

@

LAN_MDI1+
LAN_MDI1­LAN_CT0

LAN_CT1
LAN_MDI0+
LAN_MDI0-

+3VALW

2

C17

@

0.1U_0402_16V4Z

1

1
2
3
4
5
6
7

J1

T1

RD+

RX+

RD-

RX-

CT

CT

NC

NC

NC

NC

CT

CT

TD+

TX+

TD-8TX-

350uH_NS0013LF

@

JOPEN

12

D

S

1 3

AO3414_SOT23-3

G

2

@

RJ45_ MIDI1+

16

RJ45_ MIDI1-

15

RJ45_CT0

14
13
12

RJ45_CT1

11

RJ45_ MIDI0+

10

RJ45_ MIDI0-

9

La yout No tic e : Pl ace a s clos e
ch ip as p oss ible .

R3 75_0402_5%

12
12

R2 75_0402_5%

1000P_1206_2KV7K

+3V_LAN

Q1

@

C13

4.7U_0805_10V4Z

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

LAN_A CTIVITY#

1

C2

2

2006/08/04 2006/10/06

1

C1
68P_0402_50V8K

@

2

LAN_SK_LAN_LINK#

Compal Secret Data

Deciphered Date

R1 300_0402_5%

+3V_LAN

For EMI.

C8

@

470P_0402_50V7K

12

R5 300_0402_5%

1

C7
68P_0402_50V8K

2

@

D

12

RJ45_ MIDI0+

RJ45_ MIDI1+

RJ45_ MIDI0-

RJ45_ MIDI1-

12

+3V_LAN

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

JRJ1

12

Amber LED-

11

Amber LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

Green LED-

9

Green LED+

SUYIN_1 00073FR0 12S102ZR

ME@

SHLD4

SHLD3

SHLD2

SHLD1

Compal Electronics, Inc.

RTL8103EL

Monday, April 06, 2009

E

16

15

14

13

0.2

25 42

5

D D

4

3

2

1

12

RST #
MOD E SEL

USB 20_N3
USB 20_P3

R2 89

6.19 K_040 2_1%

+V CC_3 IN1

CLK _48M_ CR

1 2

C3 74 0.1U _0402 _16V4Z

1 2

U1 8

1

AV_PLL

3

NC1

7

NC

9

CARD_3V3

11

D3V3

33

D3V3

8

3V3_IN

44

RST#

45

MODE_SEL

47

XTLO

48

XTLI

4

DM

5

DP

14

GPIO0

2

RREF

12

DGND

32

DGND

6

AGND

46

AGND

RTS 5159- GR_LQFP48_ 7X7

VREG

MS_D4

XD_CLE_SP19
XD_CE#_SP18
XD_ALE_SP17

SD_DAT2/XD_RE#_SP16

SD_DAT3/XD_WE#_SP15

SD_DAT4/XD_WP#/MS_D7_SP13

XD_RDY_SP14

SD_DAT5/XD_D0/MS_D6_SP12
SD_CLK/XD_D1/MS_CLK_SP11
SD_DAT6/XD_D7/MS_D3_SP10

MS_INS#_SP9
SD_DAT7/XD_D2/MS_D2_SP8
SD_DAT0/XD_D6/MS_D0_SP7
SD_DAT1/XD_D3/MS_D1_SP6

XD_D5_SP5

XD_D4/SD_DAT1_SP4

SD_CD#_SP3

SD_WP_SP2

XD_CD#_SP1

EEDI

XTAL_CTR

MS_D5

EEDO
EECS
EESK

SD_CMD

10
22
30

NC

43
42
41
40
39
38
37
35
34

SD_ DATA6 _XD_DATA7 _MS_DATA 3

31
29

SD_ DATA7 _XD_DATA2 _MS_DATA 2

28

SD_ DATA0 _XD_DATA6 _MS_DATA 0

27
26
25
23
21
20
19
18

13
24

15
16
17
36

C3 73

1 2

1U_0 603_1 0V4Z

SD_ DATA 2_XD_RE#
SD_ DATA 3_XD_WE #

XD_D ATA1

MS_ INS#

XD_D ATA3_MS_ DATA1

XD_DAT A5_MS_BS

XD_ DATA4 _SD_DATA1

SD _CD #
SD _WP

+3VS

SD _CM D

EMI

12

R2 76

@

100K _0402_5 %

0.1U _0402 _16V4Z

1

2

R2 75

XD_ DATA1_R

12

0_06 03_5%

S D_CLK MS _CLK

12

R2 72

@

100K _0402_5 %

0.1U _0402 _16V4Z

C3 59

@

1

C3 56

@

2

R2 73

1 2

22_0 402_5%

R2 74

1 2

22_0 402_5%

SD _WP
XD_ DATA4 _SD_DATA1
SD_ DATA0 _XD_DATA6 _MS_DATA 0

XD_DAT A5_MS_BS
S D_CLK
XD_D ATA3_MS_ DATA1
SD_ DATA0 _XD_DATA6 _MS_DATA 0

SD_ DATA7 _XD_DATA2 _MS_DATA 2

MS_ INS#

SD_ DATA6 _XD_DATA7 _MS_DATA 3
SD _CM D
MS _CLK

SD_ DATA 3_XD_WE #

SD_ DATA 2_XD_RE#
SD _CD #

MS _CLK

S D_CLK

3 in 1 Card Reader

+V CC_3 IN1

250mA

JP 9

1

SD-WP

2

SD-DAT1

3

SD-DAT0

4

SD-GND

5

MS-GND

6

MS-BS

7

SD-CLK

8

MS-DAT1

9

MS-DAT0

10

SD-VCC

11

MS-DAT2

12

SD-GND

13

MS-INS

14

MS-DAT3

15

SD-CMD

16

MS-SCLK

17

MS-VCC

18

SD-DAT3

19

MS-GND

20

SD-DAT2

21

SD-CD

TAI TW_R 009-0 25-LR_NR

0.1U _0402 _16V4Z

0.1U _0402 _16V4Z

1

C3 58

2

ME@

1

C3 57

2

GND1
GND2

22
23

C3 76

CLK _48M_ CR<14>

USB 20_N3<1 9>
USB 20_P3<19 >

C3 75

0.1U _0402 _16V4Z

12

+3VS

0.1U _0402 _16V4Z

1

+3VS

0.1U _0402 _16V4Z

1

2

+3VS

0.1U _0402 _16V4Z

1

1

C3 72

C3 69

2

2

4.7U _0805 _10V4Z

CLK _48M_ CR

12

R2 87

@

100K _0402_5 %

0.1U _0402 _16V4Z

1

C3 70

@

2

C3 65

1U_0 603_1 0V4Z

+3VS

12

1

2

R2 85

100K _0402_5 %

RST #

C C

B B

A A

2

C3 77

R2 86 0_040 2_5%

EMI

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

2

Title

Size D ocum ent N umber R ev

Da te: She et of

Compal Electronics, Inc.

1

26 42Mon day, Apri l 06, 2 009

0. 1Cus tom

L2

+3VALW +EC_AVCC

+3VALW

+3VALW

+5VALW

R107 4.7K_0402_5%

R109 4.7K_0402_5%

+3VS

R112 2.2K_0402_5%

R116 2.2K_0402_5%

1 2

FCM1608CF-121T03_2P

L3

1 2

FCM1608CF-121T03_2P

22P_0402_50V8J@

12

12

1 2

R10810K_0402_5%

EC_SMB_CK1

EC_SMB_DA1

EC_SMB_CK2

EC_SMB_DA2

+3VS

C166

+3VALW

KB_RST#<18>

R82 47K_0402_5%

R81 47K_0402_5%

1 2

1 2

2

C154

0.1U_0402_16V4Z

1

ECAGND

R134 10K_0402_5%

1 2

12

R83 47K_0402_5%

KSO1

KSO2

USER _DEFINE#

12

R118 10_0402_5%@

1 2

0.1U_0402_16V4Z

+3VS

KILL_SW#<30> CMOS_OFF# <24>

C141

KSO[0.. 15]<29>

KSI [0..7]<29>

R111

100K_0402_5%

C182

22P_0402_50V8J

2

1

12

0.1U_0402_16V4Z

KSO[0.. 15]

KSI [0..7]

USER _DEFINE#<28>

EC_TX_P80_DATA<21>
EC_RX_P80_CLK<21>

4IN1

X1

OUT

NC3NC

2

32.768K_1TJS125BJ4A421P

+3VALW

C181

C162

C142

0.1U_0402_16V4Z

C171

1

2

LPC_FRAME#<18>

CLK_P CI_LPC<14>

PCI_RST#<17>

EC_SCI#<19>

EC_SMB_CK1<35>
EC_SMB_DA1<35>
EC_SMB_CK2<4>
EC_SMB_DA2<4>

PM_SLP_S3#<19>
PM_SLP_S5#<19>

EC_SMI#<19>

DETECTION<21>

FAN_SPEED1<4>

ON/OF F#<28>

PWR_LED#<24>

NUM_LED#<28>

C183

0.1U_0402_16V4Z

1

1

2

2

GATEA20<18>

SERIR Q<19> EN_WOL <25>

LPC_AD3<18>
LPC_AD2<18>
LPC_AD1<18>
LPC_AD0<18>

22P_0402_50V8J

XCLKI
XCLKO

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

EC_RST#
EC_SCI#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
KILL_SW#
USER _DEFINE#

DETECTION

FAN_SPEED1

EC_TX_P80_DATA
EC_RX_P80_CLK

TP_CLK

TP_DATA

BATT_OVP

BATT_TEMP

AC IN

1000P_0402_50V7K

C177

0.1U_0402_16V4Z

1

2

U6

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

LID_SW#/GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT#/GPIO0C

19

EC_PME#/GPIO0D

25

EC_THERM#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LED#/GPIO19

36

NUMLED#/GPIO1A

122

XCLK1

123

XCLK0

KB926QFC0_LQFP128

1 2

R120 4.7K_0402_5%

1 2

R123 4.7K_0402_5%

C143

1 2

C144

1 2

C185

1 2

C184

1000P_0402_50V7K

1

2

LPC & MISC

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

1

2

Int . K/B
Matr ix

SM Bu s

+5VS

+EC_AVCC

9

22

33

67

96

111

125

VCC

VCC

VCC

VCC

VCC

VCC

INVT_PWM/PWM1/GPIO0F

ACOFF/FANPWM2/GPIO13

PW M Outp ut

AD In put

DA Ou tpu t

PS 2 Inter face

TP_DATA/PSDAT3/GPIO4F

SP I Device Inter face

SP I Fl a sh ROM

GP IO

G PO

GP IO

GP I

GND

GND

GND

GND

GND

11

24

35

94

113

AVCC

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B
AD4/GPIO42

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C

PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXO03

EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10
GPXO11

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

AGND

69

ECAGND

21
23
26
27

63
64
65
66
75
76

68
70
71
72

83
84
85
86
87
88

97
98
99
109

119
120
126
128

73
74
89

CHAR GE_LED0#

90
91

CHAR GE_LED1#

92
93
95
121
127

100
101
102
103
104
105
106
107
108

110
112
114

EC_THERM#

115
116

PBTN_OUT#

117
118

20mil

124

INVT_PWM
BEEP#

ACOF F

BATT_TEMP
BATT_OVP

BRD _ID

EN_FAN1
IRE F

USB_ON

TP_CLK
TP_DATA

LID_SW#

FRD#S PI_SO
FWR #SPI_SI
SPI_CLK
FSEL#SPICS#

CAPS_LED#

SYS ON

EC_LID_OUT#

EC_ON

ICH_P OK

SUSP#

1

C194

4.7U_0805_10V4Z

2

R165 c hange to Bead for EMI

C385

10P_0402_50V8J~D

C147

12

22P_0402_50V8J

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

R93

SPI_CLK_R

SPI_CLK_R

12

33_0402_5%

2006/08/04 2006/10/06

INVT_PWM <15>
BEEP# <22>

ACOF F <36>

BATT_TEMP <35>
BATT_OVP <36>
ADP_I <36>

EN_FAN1 <4>
IREF <36>
CHGVA DJ <36>

EC_MUTE# <22>

USB_ON <30>

TP_CLK <29>

TP_DATA <29>

WL_O FF# <21>

LID_SW# <28>

NOVO# <28>

FSTCHG <36>

CHAR GE_LED0# <24>

CAPS_LED# <28>

CHAR GE_LED1# <24>

SYSO N <31,38>
VR_ON <40>
ACIN <19,34>

EC_RSMRST# <19>
EC_LID_OUT# <19>
EC_ON <28>

ICH_P OK <6,19>

BKOFF# <15>

BT_OFF# <21>

WXMIT_OFF# <21>

PM_SLP_S4# <19>
GMCH_ENBKL <8>
EAPD <22>
EC_THERM# <19>
SUSP# < 31,36,38,39>
PBTN_OUT# <19>

LAN_WAKE# <25>

C152

0.1U_0402_16V4Z~D

FSEL#SPICS#

SPI_CLK

Compal Secret Data

Deciphered Date

+3VALW

1

2

+3VALW

12

12

12

SPI_CS#
SPI_SO

R99 0_0402_5%

R165 FBMA-11-100505-900T 0402

R88 0_0402_5%

8M SPI ROM

20mil s

SPI_CS#

SPI_CLK_R

SPI_SIFWR #SPI_SI FRD#S PI_SO

BOARD ID Table

ID

0

1

2

3

ICH_P OK

U3

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

SST25LF080A_SO8-200mil

JP11

E&T_2941-G08N-00E~D

ME@

D7

2 1

RB751V_SOD323

4

VSS

2

Q

2

112

4

334

6

556

8

778

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

+3VALW

Ra

R97
100K_0402_5%

1 2

R94

8.2K_0402_5%

Rb

1 2

BRD ID

R01 (EVT)

R02 (DVT)

R03 (PVT)

R10A (MP)

@

SPI_SO

SPI_CLK_R
SPI_SI

12

R96 0_0402_5%

+3VALW

Compal Electronics, Inc.

KB926/BIOS

LA-4421P

BRD _ID

@

Ra

NC

8.2K

100K
100K
100K

VGATE <14,19,40>

Rb Vab

0

0.25V

18K

0.50V

NC

27 42Monday, A pril 06, 2009

0V

3.3V

0.2

LID Switch

1

2

NOVO#<27>

51_ON#<34>

SW1

EC_ON<27>

ON/OFF BTN#

SMT1-05_4P

5

6

NOVO#

3

4

10K_0402_5%

100K_0402_5%

51_ON#

1

D1

BAV70W-7-F_SOT323-3

EC_ON

R15

1 2

+3VALW

R220

1 2

D14

2

3

BAV70W-7-F_SOT323-3

+3VALW

R8

100K_0402_5%

1 2

2

51_ON#

3

13

D

2

G

2N7002_SOT23

S

ON/ OFF#

Q2

1

ONE_K EY_RECOVER#

SW2

1

2

6

ON/OF F# <27>

51_ON# <34>

SMT1-05_4P

5

INT_MIC_L<22>

3

4

USER_SW

SATA_LED#<18>

CAPS_LED#<27>

NUM_LED#<27>

D15

PSOT24C_SOT23-3

+5VS

INT_MIC_L

ON/OFF BTN#

ONE_K EY_RECOVER#

2

3

FOR ESD

1

GNDA

JP3

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

GND

10

GND

ACES_85201-08051

ME@

+3VALW

0.1U_0402_16V4Z~D

2

VDD

1

C155

OUTPUT

GND

2

U5

1

APX9132ATI-TRL SOT-23 3P

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R103

47K_0402_5%

1 2

3

1

C150

2

10P_0402_50V8J

2006/08/18 2007/8/18

LID_SW# <27>

Compal Secret Data

Deciphered Date

USER _DEFINE#<27>

51_ON#<34>

51_ON#

D24

2

3

BAV70W-7-F_SOT323-3

Title

Size Doc ument Number Re v

B

Date: Sheet of

USER_SW

1

Compal Electronics, Inc.

LID SW

LA-4421P

28 42Monday, A pril 06, 2009

0.2

5

D D

KS I[0..7 ]

KS O[0..15 ]

KS I0

KS I1

KS I2

KS I3

KS I4

KS I5

KS I6

KS I7

C C

KSO0

KSO1

KSO2

KSO3

C136 100P_0402_50V8J@

C135 100P_0402_50V8J@

C134 100P_0402_50V8J@

C133 100P_0402_50V8J@

C132 100P_0402_50V8J@

C131 100P_0402_50V8J@

C127 100P_0402_50V8J@

C126 100P_0402_50V8J@

C125 100P_0402_50V8J@

C124 100P_0402_50V8J@

C114 100P_0402_50V8J@

C113 100P_0402_50V8J@

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

KS I[0..7 ] <27>

KS O[0..15 ] <27>

KSO4

KSO5

KSO6

KSO7

KSO8

KSO9

KSO10

KSO11

KSO12

KSO13

KSO14

KSO15

4

C104 100P_0402_50V8J@

1 2

C103 100P_0402_50V8J@

1 2

C102 100P_0402_50V8J@

1 2

C101 100P_0402_50V8J@

1 2

C100 100P_0402_50V8J@

1 2

C99 100P_0402_50V8J@

1 2

C98 100P_0402_50V8J@

1 2

C97 100P_0402_50V8J@

1 2

C96 100P_0402_50V8J@

1 2

C95 100P_0402_50V8J@

1 2

C93 100P_0402_50V8J@

1 2

C92 100P_0402_50V8J@

1 2

3

INT_KBD Conn.

KS I0
KS I1
KS I2
KSO0
KSO1
KSO2
KS I3
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KS I4
KSO9
KS I5
KS I6
KSO10
KSO11
KS I7
KSO12
KSO13
KSO14
KSO15

JP4

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

GND2
GND1

E-T_ 6905-E24N-01R

ME@

2

JP8

To TP/B Conn.

R101 10K_0402_5%@

R100 10K_0402_5%@

0.1 U_0402_1 6V4Z

@

C156

@

0.1U _0402_16V4Z

2

1

SW3

C157

26
25

SW /L

12

12

5

6

TP_CLK<27>
TP_DATA<27>

TP_CLK

TP_DATA

SMT1-05_4P

4

3

+5VS

2

1

TP_CLK
TP_DATA

SW /R

SW /L

TP_DATA

TP_CLK

3

D3

@

PSOT24C_SOT23

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

ACE S_85201-06051

ME@

+5VS

C180

0.1U _0402_16V4Z

1

5

6

SMT1-05_4P

SW /R

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

2

1

SW4

4

3

Title

Size Doc umen t Numb er R ev

B

2

Da te: Sheet o f

Compal Electronics, Inc.

KB/SW/TP/LPC Debug CONN

LA-4421P

29 42Mon day, Ap ril 06, 20 09

1

0.2

A

1 1

+5VALW

B

C

D

E

OUT
OUT
OUT
OC#

OUT
OUT
OUT
OC#

8
7
6
5

8
7
6
5

+USB_VCCA

+USB_VCCC

1

2

C320

USB_OC#1 <19>

USB_OC#0 <19>

JP6

1
2
3
4
GND
GND
GND
GND

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_85201-1005N

ME@

1

C211

1000P_0402_50V7K@

2

USB_OC#7 <19>

1000P_0402_50V7K@

150U_B_6.3VM_R40M

USB20_N7<19>
USB20_P7<19>

USB CONN. 3

+USB_VCCC

+USB_VCCC

1

+

C315

2

USB20_N7
USB20_P7

3

2

@

D21
PSOT24C_SOT23-3

1

+USB_VCCA

+USB_VCCA
USB20_N0<19>
USB20_P0<19>

USB20_N1<19>
USB20_P1<19>

KILL_SW#<27>

W=40mils

1

C316

470P_0402_50V7K

2

USB20_N0
USB20_P0

USB20_N1
USB20_P1

KILL_SW#

JP15

1
2
3
4
5
6
7
8

SUYIN_0 20173MR004S558ZL

ME@

R185
200K_0402_5%

@

U7

1

GND

2

IN

3

IN

4

EN

RT9715AGS SOP 8P

High active

U13

1

GND

2

IN

3

IN

4

EN

RT9715AGS SOP 8P

High active

C210

0.1U_0402_16V4Z

12

USB_ON<27>

2 2

3 3

USB_ON

C317

0.1U_0402_16V4Z

USB_ON<27>

12

+5VALW

1

2

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

B

D

Date: Sheet of

Compal Electronics, Inc.

USB PORTS

LA-4421P

30 42Monday, A pril 06, 2009

E

0.2

A

1 1

B

C

D

E

+5VALW

8
7

13

D

S

5

5VS_GATE

1

1

C218

C221

2 2

3 3

10U_0805_10V4Z

B+

R187
20K_0402_5%

2

10U_0805_10V4Z

1 2

SUSP

Q17

2N7002_SOT23

2

2

G

Q19SI48 00BDY-T1-E3_SO8

4

1

C208

0.01U_0402_25V7K

2

+1.5VS +2.5VS +1.8V+0.9VS

D

S

+5VS

1
2
36

C223

10U_0805_10V4Z

R51
470_0603_5%

1 2

13

SUSP SUSP SUSP SUSP SYSO N#

2

G

Q6
2N7002_SOT23

1

2

1

C219

2

1U_0603_10V4Z

R16
470_0603_5%

1 2

13

D

S

R190

470_0603_5%

1 2

13

D

S

2

G

Q4
2N7002_SOT23

SUSP

2

G

Q18
2N7002_SOT23

+VCCP

D

S

R57
470_0603_5%

1 2

13

2

G

Q7
2N7002_SOT23

C191

10U_0805_10V4Z

B+

D

S

1

2

1 2

13

+3VALW +3VS

8
7

C201

10U_0805_10V4Z

1 2

R139
100K_0402_5%

2N7002_SOT23

R70
470_0603_5%

2

G

Q9
2N7002_SOT23

1

2

SUSP

5

13

D

2

G

Q13

S

R63
470_0603_5%

1 2

13

D

2

G

Q8

S

2N7002_SOT23

Q15SI4 800BDY-T1-E3_SO8

1
2
36

4

1

C179

0.1U_0402_25V7K

2

1

C170

10U_0805_10V4Z

2

1

C176

2

1U_0603_10V4Z

R114

470_0603_5%

1 2
13

D

Q12

S

2N7002_SOT23

+5VALW

R141
100K_0402_5%

SUSP

2

G

SYSO N<27,38>

SUSP<39>

SUSP#< 27,36,38,39>

SYSO N#

SYS ON

100K_0402_5%

SUSP

RTCVREF

R172

@

1 2

13

Q14

2

DTC124EK_SC59

+5VALW

R173
100K_0402_5%

1 2

1 2

13

Q16

2

DTC124EK_SC59

+3VALW TO +3VS+5VALW TO +5VS

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

B

D

Date: Sheet of

Compal Electronics, Inc.

DC INTERFACE

LA-4421P

31 42Monday, A pril 06, 2009

E

0.2

H8
H

@

1

H_3P6X5P6N

H12
H

@

1

H6

H11
H

@

1

H2

H

H

@

@

1

1

H5
H

H_3P2

@

1

H16
H

FM2

Issued Date

H14

H3

H13

H15

H

H

@

1

H

@

@

1

1

2006/08/18 2007/8/18

H10

H

H

@

1

1

Compal Secret Data

@

H_2P8

Deciphered Date

Title

Size Doc ument Number Re v

B

Date: Sheet of

Compal Electronics, Inc.

Screw

LA-4421P

33 43Monday, A pril 06, 2009

0.2

H4

H9

H

@

@

1

1

FM4

@

@

1

1

H1

H

H

@

@

1

1

FM3

@

1

H7
H

1

FM1

@

FIDUCIAL_C40M80

1

@

Secur ity Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

D

VIN

PF2

1

1

2

2

3

3

4

4

JD CIN

ACES _85204-0400N@

1 1

7A_24 VDC_4290 07.WRML

1000P _0402_50V7K

21

PC59

APD IN1

12

PL7

SMB3 025500YA_2P

1 2

12

PC52

100P_ 0402_50V8J

12

PC60

100P_ 0402_50V8J

12

PC63

1000P _0402_50V7K

Vin Detector

High 17.944 17.706 17.470
Low 16.242 16.027 15.808

ACIN

Precharge detector

Min. typ. Max.
High 14.936V 15.381V 15.814V
Low 13.843V 14.247V 14.636V

VI N

PD4
RLS41 48_LL34-2@

PR29
1K_12 06_5%@

1 2

PR30
1K_12 06_5%@

12

1 2

PR31
1K_12 06_5%@

1 2

BATT ONLY

Precharge detector
Min. typ. Max.
High 7.196V 7.349V 7.505V
Low 6.138V 6.214V 6.359V

B+

PU10A

LM393 DG_SO8@

+RTCBATT

PR138

2.2M _0402_5%@

12

VS

12

PC98

8

P

+

1

O

-

G

4

PR127
10K_0 402_1%@

0.01U_ 0402_25V7K@

3

2

12

PC95

1000P _0402_50V7K@

12

12

PR119

205K_ 0402_1%@

PRG++

PQ22

13

D

2N700 2KW_SOT323-3@

2

G

S

12

PR124

66.5K_ 0402_1%@

PU10B

LM393 DG_SO8@

12

PR142

499K_ 0402_1%@

12

12

PC92

PR121

499K_ 0402_1%@

0.01U_ 0402_25V7K@

PR120

47K_0 402_1%@

12

13

2

PQ19
DTC11 5EUA_SC 70-3@

8

P

+

7

O

-

G

4

PACIN <3 6>

+5VALWP

5

6

VL

PR137
1M_0402_1%

1 2

2 2

PC104

VI N

12

PR133

PR132

84.5K_ 0402_1%

90.9K _0402_1%

1 2

12

12

PR136

1000P _0603_50V7K

12

22K_0 402_1%

PC96

0.1U_0 402_16V7K

VS

8

3

+

2

-

4

PR128
10K_0 402_1%

12

P

1

O

G

PU12A
LM393 DG_SO8

12

RTC VREF

PC91

0.01U_ 0402_25V7K

3.3V

VI N

12

PD15

RB715 F_SOT323-3@

2

3

12

PR117

PR118
10K_0 402_1%

1 2

PAC IN

10K_0 402_1%

AC IN <19,27>

PAC IN <36>

MAINPWON<35,37>

ACON<36>

PR123

10K_0 805_5%

12

PD13

RLZ4 .3B_LL34

12

PR135

100K_ 0402_1%@

1

12

PC105

0.1U_0 402_10V7K@

RTCVREF

VIN

PD5

PR32

13

RLS41 48_LL34-2

1 2

12

12

PR33
68_12 06_5%

12

PC30

0.1U_ 0603_25V7K

VS

JR TC

- +

MAXEL_ML1220T10@

12

SP093MX0000

RTC Battery

PD6

1 2

RB751 V-40TE17_SOD323-2

+CH GRTC

3 3

PR35

200_0 603_5%

1 2

100K_ 0402_1%

PR37

22K_0 402_1%

1 2

RTC VREF

3.3V

12

12

12

PR116

G920A T24U_SOT89-3

3

OUT

PC29
10U_0 805_6.3V6M

TP0610K-T1-E3_SOT23-3

N1

PC28

1 2

0.22U_ 0603_25V7K

PU4

2

IN

GND

1

PQ15

N2

68_12 06_5%

2

12

PR34
200_0 603_5%

12

PC27
1U_08 05_25V4Z

BATT+

CH GRTCP

PD12
RLS41 48_LL34-2

51_ON#<28>

PR36

560_0 603_5%

4 4

+CH GRTC

1 2

PR38

560_0 603_5%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/09/20 2008/09/20

Compal Secret Data

Deciphered Date

C

Title

Size D ocum ent Nu mber R ev

Cus tom

Dat e: Sheet o f

Compal Electronics, Inc.

DCIN & DETECTOR

D

34 43Monday, A pril 06, 2009

0.1

A

1 1

B

C

D

PH3 under CPU botten side :

CPU thermal protection at 90 degree C

Recovery at 45 degree C

VL

12

100K_ 0603_1%_ TH11-4H104FT

EC_SM CA
EC_SM DA
TS

VMB2

7A_24 VDC_4290 07.WRML

100_0 402_1%

PF1

21

12

12

PR2

PR1
100_0 402_1%

2 2

JBATT

SUY IN_200082 MR007G1 00ZR@

GND
GND

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8
9

VMB

SMB3 025500YA_2P

1 2

12

PC45
1000P _0402_50V7K

PL4

BATT+

12

PC51

0.01U _0402_25V7K

EC_SM B_CK1 <27>

PH1

PR140

13.7K _0402_1%

1 2

12

12

PC12

12

PR141

16.9K_ 0402_1%

0.22U_ 0402_6.3V 6K

TM_REF1

PC99

1000P _0402_50V7K

5

6

PR131

12

100K_ 0402_1%

PR134
100K_ 0402_1%

+

-

8

P

O

G

PU12B
LM393 DG_SO8

4

12

PR139

47K_0 402_1%

1 2

7

VL

EC_SM B_DA1 <27>

1 2

PR3

6.49K _0402_1%

+3VALWP

VL

PR129
47K_0 402_1%

1 2

2

G

13

D

PQ23
2N700 2KW_SOT323-3

S

MAINP WON <34,37>

1 2

PR4

3 3

4 4

A

10K_0 402_1%

BATT_TEMP <27>

B

A/D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

2008/6/222007/6/22

Title

Size D ocum ent Nu mber R ev

Dat e: Sheet o f

Compal Electronics, Inc.

BATTERY CONN / OTP

D

35 43Monday, April 0 6, 2009

0.1

5

P2

4

P3

B+

3

2

1

PD9

B340A_SMA2

VIN

D D

C C

B B

12

PR143

DTA14 4EUA_SC70-3

47K_0 402_5%

13

2

PQ28

13

D

2N700 2KW_SOT323-3

2

G

S

PAC IN<34>

ACO N<34>

ACO FF<27>

PAC IN

PQ1

DTC11 5EUA_SC 70-3

ACO FF

Iada=0~2A(40W) CP = 85%*Iada ; CP = 1.7A

CP mode
Vaclim=2.39*(31.6K/(231.6K+13.7K))=1.6672V
Iinput=(1/0.05)((0.05*Vaclm)/2.39+0.05)
where Va clm=0. 8199V, Iinput=1.7A

12

PQ27

2

1 3

PQ26

DTC11 5EUA_SC 70-3

PR9
3K_04 02_1%

1 2

2

12

PC49

0.1U_0 603_25V7K

2

G

13

CC=0.3~1.8A

IREF=1. 56*Icharge

IREF=0. 468V~2.81V

IREF=3. 3V =>2.12A

P3

A A

12

PR14

100K_ 0402_1%

5

PQ10 TP0610K-T1-E3_SOT23-3

DTC11 5EUA_SC 70-3

2

100K_ 0402_1%

PQ8

PR12

13

625 1DCIN

PQ16
FDS44 35BZ_SO 8

1

S

2

S

3

S

4

G

12

PR61

200K_ 0402_1%

FSTCHG<27 >

12

PR64

150K_ 0402_1%

PQ2

13

D

2N700 2KW_SOT323-3

S

56K_0 402_1%

IREF<27>

100K_ 0402_1%

Connect to EC A/D Pin.

CHGVAD J=(Vcell-4)/0.10627

Vcell

4V

4.2V

4.35V

12

13

2

8

D

7

D

6

D

5

D

PC65

1 2

0.01U _0402_25V7K

ADP _I<27>

PR75

12

12

PR76

CHGVADJ<27>

CHGVADJ

2

1

3

PD2

RB715 F_SOT323-3

RB751 V-40TE17_SOD323-2

1 2

10K_0 402_1%

0.1U_ 0402_16V7K

PC61 6800P _0402_25V7K

1 2

PR72 6.81K _0402_1%

1 2

1 2

PC64
100P_ 0402_50V8J@

PC68

0.1U_ 0402_16V7K

6251_ VREF

12

PC69

0.01U_ 0402_25V7K

0V

1.88 2V

3.2 935V

FST CHG

SUSP #

4

PR58 0.05_1206_1%

1

2

PD10

6251 VDD

PR67

12

1 2

PC58

1 2

PR73
100_0 402_1%

1 2

PR81

13.7K _0402_1%

1 2

PR80

31.6K _0402_1%

PR78

15.4K _0402_1%

1 2

31.6K _0402_1%

FSTCHG <27>

SUSP# < 27,31 ,38,39>

625 1DCIN

12

PC57

0.047 U_0402_16V7K

PC62

0.1U_ 0402_16V7K

1 2

LX_CHG

DH_ CHG

2.2_0 402_5%

BST_C HG

6251V DDP

DL_ CHG

PJ7

2

112

JUMP_43X118@

PC54

0.1U_ 0603_25V7K

12

20_04 02_5%

1 2

1 2

PR69

20_04 02_5%

12

PR70
20_04 02_5%

1 2

2.2_0 402_5%

PR74

1 2

12

PC70

4.7U_ 0805_6.3V6K

CS IN

CSI P

PR65

PR71

BST_C HGA

12

1 2

4

3

12

PC55

12

PR68

6251_ EN CS ON

100K_ 0402_1%

6251_ VREF

12

PR79

2.2U_0 603_6.3V 6K

12

PU6

1

VDD

2

ACSET

3

EN

4

CELLS

5

ICOMP

6

VCOMP

7

ICM

8

VREF

9

CHLIM

10

ACLIM

11

VADJ

12

GND

ISL625 1AHAZ-T_QSOP24

DCIN

ACPRN

CSON

CSOP

CSIN

CSIP

PHASE

UGATE

BOOT

VDDP

LGATE

PGND

12

PC106

470P_ 0603_50V8J

24

23

22

21

20

19

18

17

16

15

14

13

LI-3S :13.5V----BATT-OVP=1.5012V

BATT-OVP=0.1112*VMB

Per cell=3.5V

PR115
10K_0 402_1%@

BATT_OVP<27>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1 2

PC4

1 2

CSOP

PC67

0.1U_ 0603_25V7K

PD11
RB751 V-40TE17_SOD323-2

PR77

4.7_0 402_5%

PU9A
LM358DT_SO8@

12

6251 VDD

1

0

Compal Secret Data

Deciphered Date

CHG_ B+

PQ17

FDS44 35BZ_SO 8

1
2
3

1 2
13

PL5

1 2

PR10

4.7_12 06_5%@

PC8

680P_ 0603_50V7K@

4

47K_0 402_1%

1 2

4.7U_1 206_25V6K

1 2

4.7U_1 206_25V6K

4.7U_1 206_25V6K
2200P _0402_50V7K

DTC11 5EUA_SC 70-3

PQ3

3 5

241

SIS41 2DN-T1-GE 3 _PAK1212-8

PQ4

3 5

241

SI7716 ADN-T1-G E3 _PAK1212-8

PR13

10K_0 402_1%

PQ7

10UH_ PCMB063T-100MS_4A_20%

12

12

PC5

PC2

PC3

1 2

S
S
S
G

PR16

1 2

1

PD3
RB715 F_SOT323-3

2

C HGC HG

1

2

8

D

7

D

6

D

5

D

VIN

ACO FF

3

2

12

PC11

0.1U_0 603_25V7K

PR63 0.0 5_1206_1%

4

3

PR15

200K_ 0402_1%

1 2

13

D

PAC IN

2

G

S

PQ9

2N700 2KW_SOT323-3

12

PC47

PC46

10U_1 206_25V6M

VI N

BATT+

12

12

PC48

10U_1 206_25V6M

10U_1 206_25V6M

VMB2

12

VS

12

8

3

P

+

2

-

G

4

PR114
340K_ 0402_1%@

12

PC87

PR113
499K_ 0402_1%@

0.01U_ 0402_25V7K@

PU9B

12

PR112
105K_ 0402_1%@

2008/6/222007/6/22

2

LM358DT_SO8@

12

PC85

0.01U_ 0402_25V7K@

Title

Size D ocum ent Nu mber R ev

Dat e: Sheet o f

VS

8

5

P

+

7

0

6

-

G

4

Compal Electronics, Inc.

CHARGER

36 43Monday, April 0 6, 2009

0.1

1

5

4

3

2

1

3V_B+

12

PL3

4.7U H_PCM C063T- 4R7MN_5.5A_20%

12

PR1 26

4.7_1206_5%

12

PC9 7

680P_0603_50V8J

12

PC 89

PC 88

10U_1 206_25V6M

2200P _0402_50V7K

12

PR 53

61. 9K_0402_1%@

PR 54

0_040 2_5%

+5VALWP
Imax=5A
Ipeak=6.5A
Iocp(minimum)=7.6A

PJ5

112

JUMP_43X118@

PJ6

112

JUMP_43X118@

+5VALWP

1

1 2

1 2

+

PC 38

2

150 U_B2_6.3VM _R45M

12

PC 93

2200P _0402_50V7K

PR5 7

0_0402_5%

3V_B+

PQ20

SIS 412DN-T1- GE3_PAK1212- 8

PQ21

SI7 716DN-T1-E 3_PAK1212-8

PR4 9

100K_0402_1%

1 2

12

PR5 1

0_0402_5%

1 2

VL

PC3 9

0.1U _0603_25V7K

3 5

241

D H3

BST3A

12

PR4 8
0_0603_5%

PC3 3

0.1U _0603_25V7K

1 2

3 5

241

LX3

DL3

FB3

VL

1 2

33

TP

26

UGATE2

24

BOOT2

25

PHASE2

23

LGATE2

30

OUT2

32

REFIN2

1 2

PC 34

3

6

VIN

VCC

2VREF_ISL6237

2VR EF_ISL6237

1 2

PC3 2

0.22 U_0603_25V7K

PC3 5

200K_ 0402_1%

1 2

0.22 U_0603_25V7K

1 2

PR 50

VL

806K_ 0603_1%

47K_0402_5%@

1 2

12

PC 42

PR4 2

0.0 47U_0402_1 6V7K

PC 31

0.0 47U_0402_1 6V7K@

PR 56

1 2

1

REF

8

LDOREFIN

20

NC

4

EN_LDO

14

EN1

27

EN2

PR4 1
0_0402_5%

1 2

12

2VR EF_IS L6237

TON

NC

2

5

12

12

PC 37

PR4 7
0_0402_5%

1U_ 0603_10V6K

2VR EF_IS L6237

12

PC 41

1U_ 0603_10V6K

7

4.7 U_0805_6 .3V6K

19

LDO

PVCC

15

UGATE1

17

BOOT1

16

PHASE1

18

LGATE1

22

PGND

10

OUT1

11

FB1

9

BYP

29

SKIP

28

POK2

13

POK1

12

ILIM1

31

ILIM2

GND

PU5

21

SN0 806081 RHBR_QFN32_5X5

PC3 6

1U_ 0603_10V6K

1 2

D H5

BST5A

PR5 2
0_0603_5%

LX5

DL5

FB5

ILM1

ILIM 2

12

1 2

PC4 0

0.1U _0603_25V7K

PR4 3 0_0402_5%@

12

PR3 9 0_0402_5%@

1 2

PR4 0 0_0402_5%

1 2

12

PR5 5
301K_0402_1%

PR4 4
301K_0402_1%

2VR EF_ISL6237

12

+3VALWP +3VALW

+5VALWP +5VALW

PQ24

3 5

241

SIS 412DN-T1- GE3_PAK1212- 8

PQ25

3 5

241

SI7 716DN-T1-E 3_PAK1212-8

VL

2

2

B+

PJ12

2

112

D D

+3VALWP

1

+

PC 26

2

C C

150 U_B2_6.3VM _R45M

JUMP_43X79@

4.7U H_PCM C063T- 4R7MN_5.5A_20%

1 2

PR 45

0_040 2_5%

1 2

PR 46

10K_0 402_1%@

1 2

680P_0603_50V8J

12

PL2

PR1 11

4.7_1206_5%

PC8 6

PC1 01

10U_1 206_25V6M

12

12

+3VALWP
Imax=5A
Ipeak=6.5A
Iocp(minimum)=7.6A

PD1 4

VS

B B

A A

RLZ 5.1B_LL34

1 2

MAINP WON<34,35>

PD7

RB7 51V-40TE17_SOD323-2

1 2

PD8

RB7 51V-40TE17_SOD323-2

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/06/22 2008/06/22

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Doc umen t Numb er R ev

2

Da te: Sheet o f

3V/5V

Monday, April 06, 2009

1

0.1Cu stom

37 43

5

4

3

2

1

PR26

1.8V_ TON

D D

SYS ON<27 ,31>

+5VALW

C C

SUSP #<27,3 1,36,39>

B B

+5VS

PR25

0_0402_5%

1 2

PR110

422_0 603_1%

1 2

PC84

1U_06 03_10V6K

PR6

2.2K_ 0402_5%

1 2

PR62

422_0 603_1%

1 2

PC44

1U_06 03_10V6K

12

PC24

0.1U_ 0402_16V7K

@

12

12

12

PC1

1U_04 02_6.3V6K

12

8.87K _0402_1%

12

PR60
21K_0 402_1%

PC25

47P_0 402_50V8J@

1 2

PR27

30.1K _0402_1%

1 2

PR28
21K_0 402_1%

PR59

1 2

1.8V_ EN

1.8V_ V5FILT

1.8V_ FB

VCCP _TON

VCC P_EN

VCC P_V5FILT

VCC P_FB

240K_ 0402_5%

1 2

PR24

2.2_0 603_5%

BST_1.8V BST_1.8V-1

1 2

1

14TP15

DRVH

TRIP

DRVL

LL

LL

13

12

11

10

9

UG_1. 8V

13

SW _1.8V

12

1.8V_ TRIP

11

10

LG_1.8V

9

PR7

0_0603_5%

1 2

UG_ VCCP

SW _VCCP

VC CP_TRIP

LG_ VCCP

2

TON

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

240K_ 0402_5%

1 2

1

2

TON

EN_PSV

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

VBST

EN_PSV

V5DRV

GND7PGND

8

PU3
TPS 51117RGY R_QFN14 _3.5x3.5

PR5

BST_V CCP BST_V CCP-1

14TP15

VBST

DRVH

TRIP

V5DRV

DRVL

GND7PGND

8

PU1
TPS 51117RGY R_QFN14 _3.5x3.5

0.1U_ 0603_25V7K

1 2

PR22

15.4K _0402_1%

4.7U_ 0805_6.3V6K

0.1U_ 0603_25V7K

1 2

PR8

15.4K _0402_1%

4.7U_ 0805_6.3V6K

1 2

PC20

PC83

1 2

PC6

PC7

+5VALW

12

+5VS

3 5

3 5

3 5

241

12

3 5

241

1.8 V_IN1 .8V_I N1.8 V_IN 1 .8V_ IN1.8 V_IN1 .8V_I N

12

PQ12

241

241

2.2UH _PCMC0 63T-2R2MN_8A_20%

SIS41 2DN-T1-GE 3_PAK1212-8

PQ13

SI7716 DN-T1-E3 _PAK1212-8

PQ5

2.2UH _PCMC0 63T-2R2MN_8A_20%

SIS41 2DN-T1-GE 3_PAK1212-8

12

VC CP_SNB

PQ6

12

SI7716 DN-T1-E3 _PAK1212-8

PC108

<BOM S tructure>

1000P _0603_50V7K

12

PR19

1.8V _SNB

12

PC18

VCC P_IN

1 2

PR11

4.7_12 06_5%

PC10

680P_ 0603_50V7K

PL9

1 2

4.7_12 06_5%

680P_ 0603_50V7K

12

PL6

PJ2

2

JUMP_43X79@

12

PC16

10U_1 206_25V6M

1

+

2

PJ1

2

112

JUMP_43X79@

PC9

10U_1 206_25V6M

1

+

PC50

2

B+

112

12

PC43

<BOM S tructure>

470P_ 0603_50V8J

+1.8VP

12

PC76

PC74

10U_0 805_6.3V6M

220U_ B2_2.5VM_R25M

B+

+VCC PP

12

PC53

10U_0 805_6.3V6M

220U_ B2_2.5VM_R25M

PJ10

2

112

JUMP_43X118@

PJ8

+VCCPP +VCCP

2

112

JUMP_43X118@

+1.8V+1.8VP

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

Compal Secret Data

Deciphered Date

2008/6/222007/6/22

2

Title

Size D ocum ent Nu mber R ev

Dat e: Sheet o f

Compal Electronics, Inc.

1.8VP/VCCPP

0.1

38 43Monday, April 0 6, 2009

1

5

4

3

2

1

D D

10U_0 805_6.3V6M

PD16

RB751 V-40TE17_SOD323-2

1 2

PR122
30K_0 402_1%

1 2

SUSP #<27,3 1,36,38>

C C

B B

SUSP<31>

0.68U _0603_10V6K

PR23

0_0402_5%

1 2

0.1U_ 0402_16V7K@

PC90

4.7U_ 0805_6.3V6K

12

PC21

+1.8V +5VALW

PJ14

JUMP_43X79@

PC103

12

+1.8V

1

1

2

2

12

PC23

13

D

2

G

S

1

1

2

2

12

PJ4
JUMP_43X79@

1K_04 02_1%

1K_04 02_1%

PQ14

2N700 2KW_SOT323-3

PR20

PR21

1

PJ11

1

JUMP_43X79@

2

2

12

PC100

1U_06 03_10V6K

12

12

PU11
APL59 13-KAC-TRL_SO8

6

VCNTL

5

VIN

9

VIN

8

EN

7

POK

12

PC19

0.1U_0 402_16V7K

3

VOUT

4

VOUT

2

FB

GND

1

PU2
APL53 31KAC-TRL_SO8

VIN1VCNTL

2

GND

3

VREF

4

VOUT

+0.9VSP

12

PC17
10U_0 805_6.3V6M

PR130

2.7K_ 0402_1%

PR125

3K_04 02_1%

6

5

NC

7

NC

8

NC

9

TP

PU7

12

12

PC94

12

+3VALW

12

PC22
1U_06 03_10V6K

0.01U_ 0402_25V7K

+1.5VSP

12

PC102

22U_0 805_6.3V6M

+3VS

APL55 08-25DC-TRL_SOT89-3

2

IN

12

PC56

1U_06 03_10V6K

3

OUT

GND

1

+1.5VSP +1.5VS

12

12

PR66
150_1 206_5%@

PC66

4.7U_0 805_6.3V 6K

PJ13

2

112

JUMP_43X79@

PJ3

2

112

JUMP_43X79@

+2.5VSP

+0.9VS+0.9VSP

PJ9

+2.5VSP +2.5VS

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

Compal Secret Data

Deciphered Date

2008/6/222007/6/22

2

Title

Size D ocum ent Nu mber R ev

Dat e: Sheet o f

2

112

JUMP_43X39@

Compal Electronics, Inc.

1.5V/0.9V/2.5V

1

39 43Monday, April 0 6, 2009

0.1

A

1 1

VSS SENSE<5>

VC CSEN SE<5>

2 2

+C PU_ CORE

H_P ROCH OT#<4>

PR1 7

100 _0402_1 %

1 2

1 2

PR 18
100 _0402_1 %

B

C SN

H_P ROCH OT#

0.2 2U_0 603_25V7K
PC 79
33P _0402_ 50V8K

1 2

1 2

PR1 07 4 70_04 02_1%

PC 80 33P _0402_ 50V8K

1 2

CS P

1 2

PR1 08 47 0_0402 _1%

PR1 06
10K _0402_1 %

+V CCP

H_D PRST P#< 4,18>

CP U_VI D6<5>

CP U_VI D5<5>

CP U_VI D4<5>

CP U_VI D3<5>

CP U_VI D2<5>

CP U_VI D1<5>

CP U_VI D0<5>

PC8 1

1 2

PC7 8
100 P_0402 _50V8J

1 2

1 2

12

PR1 03
0_0 402_5%

PR1 04
56_ 0402_5%

20K _0603_ 1%

PH 3

1 2

12

PR1 01 0_0 402_5%

1 2

PR 99 0_0402 _5%

1 2

PR 98 0_0402 _5%

1 2

PR 96 0_0402 _5%

1 2

PR 94 0_0402 _5%

1 2

PR 91 0_0402 _5%

1 2

PR 90 0_0402 _5%

1 2

PR 85 0_0402 _5%

1 2

C

1U_ 0603_ 10V6K

PC 77

27P _0402 _50V8J

1 2

1 2

PR1 02

4.5 3K_040 2_1%

VR EF_ CPU

1

2

3

4

5

6

7

8

VREF

GND

CSN

CSP

GNDSNS

VSNS

THERM

VR_TT#

PR1 05

124 K_0402 _1%

PC7 5

32TP33

9

12

12

PR1 00

30

31

ISLEW

V5FILT

DROOP

TPS 5161 0RHB_QF N32_5X5

VID6

DPRSTP#

11

10

D

E

F

G

H

+5VS

VR EF_ CPU

12

12

0_0 402_5%

27

28

29

TONSEL

OSRSEL

TRIPSEL

PU 8

VID2

VID412VID5

VID3

14

13

PR 97
0_0 402_5%

26

PWRMON

VID1

15

PM ON

25

VR_ON

CLKEN#

DPRSLP

PGOOD

DRVL

VBST

DRVH

VID0

16

1 2

V5IN

LL

12

PR 95
0_0 402_5%@

PR 93
0_0 402_5%

24

23

22

21

20

19

18

17

PR 87 0 _040 2_5%@

PR 88 4 99_0 402_1%

PR1 44 0_0 402_5%

LGA TE_C PU

PHA SE_C PU

BOO T_CP U

UGA TE_ CPU

1 2

PR 86

0_0 603_5%

12

12

12

1 2

0.2 2U_0 603_25V 7K

+5VS

4.7 U_08 05_6.3V 6K

PC 72

12

PR 89
10K _0402_1 %

PC7 3

VR _ON <2 7>

PM_ DPRS LPVR < 6,19>

VGATE <1 4,19,2 7>

12

+CP U_B+

PL1

FBM A-L11-20 1209-121L MA50T_0 805

1 2

12

12

PC1 5

10U _1206_2 5V6M

PQ11

3 5

241

SIS 412D N-T1- GE3_PAK12 12-8

12

PR 84

6.8 _1206_ 5%

PQ18

12

3 5

241

PC7 1

680 P_060 3_50V8J

SI7 716D N-T1-E 3_PAK1212 -8

12

PC1 3

PC1 4

10U _1206_2 5V6M

220 0P_040 2_50V7K

2.2 UH_ PCMC 063T-2 R2MN_8A _20%

1 2

12

PR8 3
162 K_0402_ 1%

1 2

PH 2

150 K +- 5% E RTJ1VV1 54J 060 3

24. 9K_040 2_1%

CS P

680 0P_040 2_25V7K

PL8

43. 2K_040 2_1%

1 2

1 2

PR1 09

1 2

PC 82

PR 82

B+

12

PC1 07

@

470 P_060 3_50V8J

+CP U_C ORE

C SN

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

2007/09/20 2008/09/20

Compal Secret Data

Deciphered Date

F

Title

Size Doc ume nt N umber Re v

C

Dat e: Sh eet o f

G

Compal Electronics, Inc.

+CPU_CORE

KAV10 LA-4781P

40 43M ond ay, April 06, 20 09

H

0.1

A

B

C

D

E

Version change list (P.I.R. List) Page 1 of 1

Rev. PG# Modify ListFixed IssueItem

1

1 1

2

3

4 0.2 Q26 3413 cha nge to 2301

6

7 0.2 P22 Change C352,C35 3,C3 54,C355 to SE107225K80

9 0.2 P13 Change C109,C11 0,C1 28,C129,C13 0,C112 to SE103225Z80

10 0.2 P15Modify L CD p ower squence Change R 221 to 100K

11 0.2 P21 Delete WLAN por t80 and cut WWAN port80

12 User def ine key support power on 0.2

13 0.2 P28 D15 change to S CA00000R00

14 0.2 P25 C258 change to 1uf Realtek recommend

15 0.2 C71 and C81 change to 0603

2 2

16 0.2 P27 Add R97 100k an d ch ange R94 to 8.2KFor B Phase

17 0.2 P27 ,15EMI request Add R93, C385 ,C147,C10,C 11 C hange R165 to 33 ohm

18 0.2 P4ESD request Add C391 ~C397

19 0.2 P14For N280 Unpop: R 68,1 10,87 Pop:R69,119,84

20 0.2 P25 Delete C257Realtek recommend

21 0.2 C30 chan ge t o SE027474Z80P10

22 0.2 P30 U7,30 change to hig h active unpop R185Customer request

23 0.2 P22 Unpop C325 POP C326

24 1.0 P27EC code for MP Unpop R94

25

26 1.0 P28 Change D14,D24 foorprint

27 1.0

28 1.0 P16 Change D2 from SC1B 491D000 to SCS00002000

29 1.0 Change C 373, C297, C71, C73 , C81, C82, C84 and C85 to SE052105Z80

30 1.0 P20 Unpop D12

3 3

31 1.0 P20EMI request Add C257 ,C39 8,C399,C400

32 1.0 P04 Unpop R58

33 SSD 1.0 Unpop R117P21

34 EMI request 1.0 P27 R165 change to bead for EMI request

35 3G request 1.0 P14 Pop C390

36 1.0 P28 Change D1,14,24 P/N SC2N202U010 to SC6AV70W110

37 1.0 P27 Unpop D7

LAN JRJ1 0.2 P25 Change JRJ1 Pin define

Change N B,SB P/N 0.2 Change N B to SA00002KQ5 0 SB to SA00000V1D0

Customer request

TP 12pin cha nge to 6pin0.2 P29

0.25 P29 SW3,4 chang e to SN100000K00

Customer request

0.2 P28 change net nam e NO VO_BTN# to ONE_KEY_RECOVER#

P04 Change C312,C314 to SE000003H000.28

Fix WLAN car d leakage

P28 Add D24 for user define key powe r on and pull up change to +3valw

ESD request

1.0 P21SSD pin change JP13 32p in c hange to 47pin

Change B T connect

4 4

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Doc umen t Numbe r R e v

Da te: Sheet o f

Compal Electronics, Inc.

HW PIR

LA-4421P

41 43Mon day, Ap ril 06, 20 09

E

5

4

3

2

1

Page 1 of 1 for PWRVersion change list (P.I.R. List)

Item Fixed Issue PhaseDateModify ListPG#

D D

2

Adjust charging voltage Adjust charging voltage

3

4
5

6

7

EMI

EMI

EMI

Design change

Adjust CPU OTP from 85 degree C to 90 degree C P35 Ch ange PR141 from 21.5k to 16.9k.Thermal

Adjust charging current Change PR75 from 88.7K to 56K.P36

1

Adjust charging current

EMI requests to add soltion

EMI requests to add soltion

EMI requests to add soltion

Adjust +1.5VSP turn on timing

Rev.Reason for change

P40

Add PC107

Change PR78 from 18.2K to 15.4K.

P36

Add PC106P36

Add PC108 and PC43

P38

Add PD16

P39

Change PR122 from 10K to 30K.

20 08. 12. 30

20 09. 02. 13

20 09. 02. 13

20 09. 02. 13

20 09. 02. 13

20 09. 02. 13

EVT

PVT

PVT

PVT

PVT

PVT

Change PC90 from 0.47u to 0.68u.

20 09. 03. 13

Pre-MP

8

9

C C

10

11

12

13

14

B B

15

16

17

18

19

20

21

22

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2007/09/20 2008/09/20

3

Compal Secret Data

Deciphered Date

Title

Size Docu ment Nu mber R ev

Cu stom

Dat e: Sh eet o f

2

Compal Electronics, Inc.

PIR (PWR)

<Doc>

42 43Mon day, April 0 6, 2009

0.1

1

A

B

C

D

E

Version change list (P.I.R. List) Page 1 of 1

Rev. PG# Modify ListFixed IssueItem

1

2

1 1

3

4 0.2

6

7 0.2

9 0.2

10 0.2

11 0.2

12

13 0.2

14 1.0

15

16

17

2 2

18

19

22

LAN JRJ1 0.2 P25 Change JRJ1 Pin define

P15Modify LCD powe r squence Change R 221 to 100K

Customer request

Fix WLAN car d leakage

User def ine key support power on

Customer request

ESD request

P21 Delete WLAN port8 0 and cut WWAN port80

0.25

0.2 P28 Change net name NOVO_B TN# to ONE_KEY_RECOVER#

P28 D15 change to SCA00000R00

0.28

P25 C258 change to 1uf Realtek recommend

TP 12pin cha nge to 6pin0.2 P29

Add D24 for user define key power on a nd pull up change to +3valw

P27 Add R97 100k and change R94 to 8.2KFor B Phase

P27,15EMI request Add R93, C385 ,C147,C10,C 11 C hange R165 to 33 ohm

P4ESD request Add C391 ~C397

0.2

P14For N280 Unpop: R 68,1 10,87 Pop:R69,119,84

P30 U7,30 change to h igh active unpop R185Customer request

EC code for MP P27 Unpop R94

1.0 P21Mini SSD pin define change JP13 pin 32 change to 4 7 30 change to 45

3 3

22

4 4

23

0.2

0.2

24

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Doc umen t Numbe r R e v

Da te: Sheet o f

Compal Electronics, Inc.

HW PIR

LA-4421P

43 43Mon day, Ap ril 06, 20 09

E