Compal LA-5071P KIUN0, IdeaPad S10-2 Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

KIUN0 Schematics Document

Intel Diamondville Processor with Calistoga(945GSE) + DDRII + ICH7M

2009-03-31

3 3

REV: 1.0

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

B

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

LA-4421P

1 42Monday, A pril 06, 2009

E

0.2

A

B

C

D

E

Compal Confidential

page 21

ZZZ 3

PCB

DAZ@

RGB

LVDS

PCI-Express

10/100 Ethernet

RTL8103E(L)

page 25

ZZ Z

ZZZ 1

ZZZ 2

Model Name : KIUN0
File Name : LA-5071P

1 1

Thermal Se nsor

EMC1402

2 2

page 4

PCB

PCB

DAZ@

CR T Conn

page 16

LCD Conn.

page 15

PCB

DAZ@

MINI Card x1

Diamondville SC

FCBGA8
437Pi ns

22x22mm

H_ A#( 3.. 31) H_ D#( 0..6 3)

FSB

400/533MHz

Calistoga GSE

page 4,5

Memory BUS(DDRII)

FCBGA998

27x27mm

page 6,7,8,9,10

DM I
X2 mode

ICH7M
BGA652

31x31mm

page 17,18,19,20

LPC BUS

1.8V DDRII 400/533

SATA

SSD

page 21

Clock Generator
CK 5 05

page 14

DDRII-SO-DIMM

US B

HDA

HDD

page 24

page 13

MINI Card x2

USB Port X3

Bl ueT ooth

CMOS CAM

page 21

page 30

page21

page24

Transfermer

3 3

page 25

Aralia Codec

ALC272

Power ON/OFF

page 28

DC IN

page 34

DC/DC Interface

3VALW/5VALW

page 31

page 37

RJ45

page 25

ENE KBC
KB926

page 27

SPI

1.5VS/0.9VS/

BATT IN

CHARGER

4 4

page 35

page 36

2.5VS

page 39

1.8V/VCCP

page 38

Int.KBD

page 29

Touch Pad

page 29

SP I ROM

page 27

AMP & INT
Speaker

page 22

page 22

INT MIC HeadPhone &

page 22

MIC Jack

page 23

Card Reader
RTS5159

page 26

SD / M M C/MS
CONN

page 26

CPU_CORE

A

page 40

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

B

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

LA-4421P

2 42Monday, A pril 06, 2009

E

0.1

A

1 1

B

C

D

E

Voltage Rails

S5

DescriptionPower Plane

VIN

B+

+CPU_CORE

+VCCP

+1.5VS

+1.8V

+2.5VS

+3VALW

+3VS

+5VALW

2 2

+5VS

+VSB VSB always on power rail ON ON*

+RTCVCC RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

STATE

Full ON

S1(P ower On Suspend)

S3 ( Suspend to RAM)

S4 ( Suspend to Disk)

S5 ( Soft OFF)

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

0.9V switched power rail for DDR terminator+0.9VS

VCCP switched power rail

1.5V switched power rail

1.8V power rail for DDR

2.5V switched power rail

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V swi tched power rail

SIGNAL

SLP_S3#

SLP_S4#

HIGH HIGH HIGH

HIGH

LOW

LOW LOW

LOWLOW

SLP_S5#

HIGHHIGHHIGH

HIGH

HIGH

LOW

+VALW

ON

ON

ON

ON

ON

S3S1

N/A N/A N/A

ON

ON OFF

ON

ON

ON

ON

ON

N/AN/AN/A

OFF

OFFON

OFF

OFFON

OFFOFFON

OFFOFFON

ON

OFF

OFF

ON ON*

OFF

OFF

ON ON*

OFF

OFFON

ONON

+V +VS Clock

ON

ON

ON

OFF

ON

OFF

OFF

OFF

OFF

ONON

LOW

OFF

OFF

OFF

External PCI Devices

DE VI CE RE Q/ GNT #

IDS EL #

No PCI Device

EC SM Bus1 address

Device

Smart Battery

Address

EC SM Bus2 address

Device

EMC1402

PI RQ

Address

100 _1100000 1 011 X b

3 3

BOARD ID Table(Page 25)

ID

0

1

2

3

4 4

BRD ID

R01 (EVT)

R02 (DVT)

R03 (PVT)

R10A (MP)

A

Ra

NC
100K
100K
100K

Rb Vab

0

8.2K
18K
NC

0V

0.25V

0.50V

3.3V

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ICH7M SM Bus address

Device

Clock Generator
(SL G8SP556 VTR)

DDR D IMMA

2006/08/18 2007/8/18

C

Address

1101 001Xb

101 0 000 Xb

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

B

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-4421P

3 42Monday, A pril 06, 2009

E

0.2

5

H_A#[ 3..16]<6>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13

D D

H_ADSTB#0<6>
H_RE Q#[0..4]<6>

H_A#[ 17..31]<6>

H_ADSTB#1<6>

C C

B B

H_A20M#<18>

H_FER R#<18>

H_IGNN E#<18>

H_STPCLK#<18>

H_INTR<18>

H_NMI<18>

H_SMI#<18>

+VCCP

+VCCP

H_A#14
H_A#15
H_A#16

H_ADSTB#0

H_AP0

T5

H_REQ#0

PAD

H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_AP1

T4 PAD

H_A20M#
H_FER R#
H_IGNN E# CLK_CPU_BCLK#
H_STPCLK#
H_INT R
H_NMI
H_SMI#

R233 1K_0402_5%

1 2

R231 1K_0402_5%

1 2

R232 1K_0402_5%

1 2

R230 1K_0402_5%

1 2

R31 1K_0402_5%

1 2

R55 1K_0402_5%

1 2

U9A

P21

A[3]#

H20

A[4]#

N20

A[5]#

R20

A[6]#

J19

A[7]#

N19

A[8]#

G20

A[9]#

M19

A[10]#

H21

A[11]#

L20

A[12]#

M20

A[13]#

K19

A[14]#

J20

A[15]#

L21

A[16]#

K20

ADSTB[0]#

D17

AP0

N21

REQ[0]#

J21

REQ[1]#

G19

REQ[2]#

P20

REQ[3]#

R19

REQ[4]#

C19

A[17]#

F19

A[18]#

E21

A[19]#

A16

A[20]#

D19

A[21]#

C14
C18
C20

E20

D20

B18

C15

B16
B17

C16

A17
B14
B15
A14
B19

M18

U18

T16

J4

R16

T15
R15
U17

D6
G6
H6

K4
K5

M15

L16

ADDR GROUP 1

A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
AP1

A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#

NC1
NC2
NC3
NC4
NC5
NC6
NC7

AU80586GE025512_FCBGA437

N270@

H_A#32
H_A#33
H_A#34
H_A#35

H_A20M#
H_IGNN E#

ADDR

GROUP

0

DEFER#

CONTROL

RESET#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PROCHOT#

XDP /ITP SI GNALS

THRMDA

THRMDC

THERM

THERMTRIP#

BCLK[0]
BCLK[1]

H CL K

NC

ADS#
BNR#

BPRI#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

BR1#

RSVD3
RSVD2
RSVD1

TDI

V19
Y19
U21

T21
T19
Y18

T20

F16
V16

W20

D15
W18
Y17
U20
W19

AA17
V20

K17
J18
H15
J15
K18
J16
M17
N16
M16
L17
K16
V15

G17
E4
E5

H17

V11
V12

C21
C1
A3

H_A20M#

.

H_FER R#

H_IGNN E#

H_INT R

H_NMI

H_STPCLK#

H_SMI#

FAN1 Conn

+5VS

+VCC_FAN1

EN_FAN1<27>

A A

EN_FAN1

FAN_SPEED1<27>

5

C312 2.2U_0603_10V6K

1 2

U12

1

EN

2

VIN

3

VOUT

4

VSET

APL5607KI-TRG_SO8

GND
GND
GND
GND

+3VS

12

R256
1K_0402_5%

1

C311
100P_0402_50V8J

2

8
7
6
5

40mil

+VCC_FAN1

4

H_ADS#
H_BNR#
H_BPRI#

H_DEF ER#
H_D RDY#
H_ DBSY#

H_BR0#

H_IER R#
H_INIT #_R

H_LOCK#

H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_ TRDY#

H_HIT#
H_HITM#

PREQ#
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#

H_PRO CHOT#_R
H_THERMDA
H_THERMDC

H_THERMTRIP#

CLK_CPU_BCLK

H_ADS# <6>

H_BNR# <6>

H_BPRI# <6>

H_DEF ER# <6>

H_D RDY# <6>

H_DB SY# <6>

H_BR0# <6>

R244 1K_0402_5%

1 2

H_LOCK# <6>

H_RESET# <6>

H_TR DY# <6>

H_HIT# <6>

H_HITM# <6>

1 2

R24 22_0402_5%

H_THERMTRIP# <6,18>

CLK_CPU_BCLK <14>
CLK_CPU_BCLK# <14>

ESD request

C391 100P_0402_50V8J

1 2

C392 100P_0402_50V8J

1 2

C393 100P_0402_50V8J

1 2

C394 100P_0402_50V8J

1 2

C395 100P_0402_50V8J

1 2

C396 100P_0402_50V8J

1 2

C397 100P_0402_50V8J

1 2

+5VS

DIODE
Closed to

12

Connector

D19

1SS355_SOD323

D20

@

1N4148_SOT23@

1 2

C314

2.2U_0603_10V6K

1 2

C313

1000P_0402_50V7K

1 2

1
2
3

4

+VCCP +VCCP

Close to CPU

Close to CPU

+VCCP

This shall place near CPU

R21 56_0402_5%
R19 56_0402_5%
R23 56_0402_5%
R20 56_0402_5%

R28 56_0402_5%
R36 56_0402_5%

JP12

1

4

2

G1

5

3

G2

ACES_85204-03001

ME@

12

1 2
1 2
1 2
1 2

1 2
1 2

R22
56_0402_5%

H_RS #[0..2] <6>

H_PRO CHOT# <40>

+CPU_EXTBGREF

1U_0603_10V4Z

12

R242
330_0402_5%

C71

Close to CPU pin
within 500mils.
Zo=55ohm

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ITP_TMS
ITP_TDI
PREQ#
ITP_TDO

ITP_TCK
ITP_TRST#

+VCCP

1

2

H_INIT# <18>

12

R48
1K_0402_1%

12

R49
2K_0402_1%

3

+CPU_GTLREF

+CPU_EXTBGREF

3

U9

N280

N280@

+CPU_CMREF

0.1U_0402_16V4Z

Close to CPU pin
within 500mils.
Zo=55ohm

2006/08/18 2007/8/18

H_D #[0..15]<6>

H_DSTBN#0<6>
H_DSTBP#0<6>

H_D# [16..31]<6>

H_DSTBN#1<6>
H_DSTBP#1<6>

R52 1K_0402_5%@

1 2

R50 1K_0402_5%@

1 2

CPU_BSEL0<14>
CPU_BSEL1<14>
CPU_BSEL2<14>

+VCCP

12

12

1

C296

2

Compal Secret Data

H_DIN V#0<6>

H_DIN V#1<6>

R241
1K_0402_1%

R240
2K_0402_1%

Deciphered Date

T6 PAD

T9 PAD

0.1U_0402_16V4Z

Close to CPU pin
within 500mils.
Zo=55ohm

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

2

Y11

W10

Y12
AA14
AA11

W12

AA16

Y10

Y9

Y13

W15

AA13

Y16

W13

AA9

W9
Y14
Y15

W16

V9

AA5

Y8

W3

U1
W7
W6

Y7

AA6

Y3
W2

V3

U2

T3

AA8

V2
W4

Y4

Y5

Y6

R4

A7

U5

V5

T17

R6
M6

N15

N6

P17

T6

J6

H5
G5

+VCCP

12

12

1

C295

2

+3VS

1

C80

2

H_THERMDA

0.1U_040 2_16V4Z~D

H_THERMDC

2200P_0402_50V7K

2

U9B

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DP#0

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
DP#1

GTLREF
ACLKPH
DCLKPH
BINIT#
EDM
EXTBGREF
FORCEPR#
HFPLL
MCERR#
RSP#
BSEL[0]
BSEL[1]
BSEL[2]

AU80586GE025512_FCBGA437

N270@

R237
1K_0402_1%

R238
2K_0402_1%

D[32]#
D[33]#
D[34]#

DATA GRP 0 DATA GRP 1

D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#

DAT A GRP 2

D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

DP#2

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

DATA GRP 3

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#

DP#3

COMP[0]
COMP[1]
COMP[2]
COMP[3]

MI SC

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

CORE_DET

CMREF[1]

Layout note:
COMP 0,2 connect with Zo=27.4ohm +/-15%, make
trac e le ngth shorter than 0.5"
COMP 1,3 connect with Zo=55ohm +/-15%, make
trac e length shorter than0.5"

CPU THERMAL SENSOR

U2

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

Addres s:100_1100

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DIN V#0
H_DP#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1 H_DSTBN#3
H_DSTBP#1
H_DIN V#1
H_DP#1

ACLKPH
DCLKPH

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

+CPU_GTLREF

C79

1 2

H_D#32

R3

H_D#33

R2

H_D#34

P1

H_D#35

N1

H_D#36

M2

H_D#37

P2

H_D#38

J3

H_D#39

N3

H_D#40

G3

H_D#41

H2

H_D#42

N2

H_D#43

L2

H_D#44

M3

H_D#45

J2

H_D#46

H1

H_D#47

J1

H_DSTBN#2

K2

H_DSTBP#2

K3

H_DIN V#2

L1

H_DP#2

M4

H_D#48

C2

H_D#49

G2

H_D#50

F1

H_D#51

D3

H_D#52

B4

H_D#53

E1

H_D#54

A5

H_D#55

C3

H_D#56

A6

H_D#57

F2

H_D#58

C6

H_D#59

B6

H_D#60

B3

H_D#61

C4

H_D#62

C7

H_D#63

D2
E2

H_DSTBP#3

F3

H_DIN V#3

C5

H_DP#3

D4

COMP0

T1

COMP1

T2

COMP2

F20

COMP3

F21

H_DPRSTP#

R18

H_DPSLP#

R17

H_DPWR#

U4

H_PW RGOOD

V17

H_CPUSLP#

N18
A13
B7

SMCLK

SMDATA

ALERT#

GND

Compal Electronics, Inc.

T7PAD

T8PAD
R243 27.4_0402_1%

1 2

R53 54.9_0402_1%

1 2

R26 27.4_0402_1%
R25 54.9_0402_1%

EC_SMB_CK2

8

EC_SMB_DA2

7

6

5

R58

10K_0402_5%

@

Diamondville(1/2)

LA-4421P

1

H_D# [32..47] <6>

H_DSTBN#2 <6>
H_DSTBP#2 <6>
H_DIN V#2 <6>

H_D# [48..63] <6>

H_DSTBN#3 <6>
H_DSTBP#3 <6>
H_DIN V#3 <6>

12
12

H_DPRSTP# <18,40>
H_DPSLP# <18>
H_DPWR# <6>
H_PW RGOOD <18>
H_CPUSLP# <6>

+CPU_CMREF

EC_SMB_CK2 <27>

EC_SMB_DA2 <27>

12

4 42Monday, A pril 06, 2009

1

+3VS

0.2

5

4

3

2

1

C72

C60

+VC CP

1

2

+1.5VS

1

2

1

C61

2

1U_ 0402_6.3V6K

1

C280

2

10U _0805_10V6K

1

+

C28 9

2

220 U_B2_2.5V M_R35

C67

0.1U _0402_10V7K

1U_ 0402_6.3V6K

1

C62

2

10U _0805_10V6K

1

C290

2

1

C64

2

1U_ 0402_6.3V6K

1

2

VC CSENSE <40>

VSS SENSE <40>

1U_ 0402_6.3V6K

1

C65

2

1

C63

2

1U_ 0402_6.3V6K

Length match within 25 mils
The trace space 7 mils,
Zo=27.4ohm

+CP U_COR E

1U_ 0402_6.3V6K

1

C53

2

1

2

2 x 330uF(9mohm/2)

1

+

C275

33 0U 2 .5V Y

2

1

+

C278

33 0U 2 .5V Y

2

U9 D

A2

VSS1

A4

VSS2

A8

VSS4

A15

VSS5

A18

VSS6

A19

VSS7

A20

VSS8

B1

VSS9

B2

VSS10

D D

C C

B B

A A

B5

VSS11

B8

VSS12

B13

VSS13

B20

VSS14

B21

VSS15

C8

VSS16

C17

VSS17

D1

VSS18

D5

VSS19

D8

VSS20

D14

VSS21

D18

VSS22

D21

VSS23

E3

VSS24

E6

VSS25

E7

VSS26

E8

VSS27

E15

VSS28

E16

VSS29

E19

VSS30

F4

VSS31

F5

VSS32

F6

VSS33

F7

VSS34

F17

VSS35

F18

VSS36

G1

VSS37

G4

VSS38

G7

VSS39

G9

VSS41

G13

VSS42

G21

VSS45

H3

VSS46

H4

VSS48

H7

VSS49

H9

VSS51

H13

VSS52

H16

VSS53

H18

VSS54

H19

VSS55

J5

VSS56

J7

VSS57

J9

VSS58

J13

VSS59

J17

VSS60

K1

VSS61

K6

VSS62

K7

VSS63

K9

VSS64

K13

VSS65

K15

VSS66

K21

VSS67

L3

VSS68

L4

VSS69

L5

VSS70

L6

VSS71

L7

VSS72

L9

VSS73

L13

VSS74

L15

VSS75

L18

VSS76

L19

VSS77

M1

VSS78

M5

VSS79

M7

VSS80

M9

VSS81

M13

VSS82

M21

VSS83

N4

VSS84

AU8 0586GE 025512_FCBGA437

N270@

VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100

VSS99
VSS98
VSS97
VSS96
VSS95

N5
N7
N9
N13
N17
P3
P4
P5
P6
P7
P9
P13
P15
P16
P18
P19
R1
R5
R7
R9
R13
R21
T4
T5
T7
T9
T10
T11
T12
T13
T18
U3
U6
U7
U15
U16
U19
V1
V4
V6
V7
V8
V13
V14
V18
V21
W1
W5
W8
W11
W14
W17
W21
Y1
Y2
Y20
Y21
AA2
AA3
AA4
AA7
AA10
AA12
AA15
AA18
AA19
AA20

+CP U_COR E

+CP U_COR E

10U _0805_10V6K

+VC CP

1

C46

2

1U_ 0402_6.3V6K

1

C70

2

U9 C

V10

VCCF

A9

VCCQ1

B9

VCCQ2

A10

VCCP1

A11

VCCP2

A12

VCCP3

B10

VCCP4

B11

VCCP5

B12

VCCP6

C10

VCCP7

C11

VCCP8

C12

VCCP9

D10

VCCP10

D11

VCCP11

D12

VCCP12

E10

VCCP13

E11

VCCP14

E12

VCCP15

F10

VCCP16

F11

VCCP17

F12

VCCP18

G10

VCCP19

G11

VCCP20

G12

VCCP21

H10

VCCP22

H11

VCCP23

H12

VCCP24

J10

VCCP25

J11

VCCP26

J12

VCCP27

K10

VCCP28

K11

VCCP29

K12

VCCP30

L10

VCCP31

L11

VCCP32

L12

VCCP33

M10

VCCP34

M11

VCCP35

M12

VCCP36

N10

VCCP37

N11

VCCP38

N12

VCCP39

P10

VCCP40

P11

VCCP41

P12

VCCP42

R10

VCCP43

R11

VCCP44

R12

VCCP45

AU8 0586GE 025512_FCBGA437

N270@

1U_ 0402_6.3V6K

1

C47

C48

2

1U_ 0402_6.3V6K

10U _0805_10V6K

1

C78

C77

2

10U _0805_10V6K

VCCPC64
VCCPC63
VCCPC62
VCCPC61

VCCSENSE

VSSSENSE

1U_ 0402_6.3V6K

1

C49

2

10U _0805_10V6K

1

C286

2

C9

VTT1

D9

VTT2

E9

VTT3

F8

VTT4

F9

VTT5

G8

VTT6

G14

VTT7

H8

VTT8

H14

VTT9

J8

VTT10

J14

VTT11

K8

VTT12

K14

VTT13

L8

VTT14

L14

VTT15

M8

VTT16

M14

VTT17

N8

VTT18

N14

VTT19

P8

VTT20

P14

VTT21

R8

VTT22

R14

VTT23

T8

VTT24

T14

VTT25

U8

VTT26

U9

VTT27

U10

VTT28

U11

VTT29

U12

VTT30

U13

VTT31

U14

VTT32

F14
F13
E14
E13

D7

VCCA

F15

VID[0]

D16

VID[1]

E18

VID[2]

G15

VID[3]

G16

VID[4]

E17

VID[5]

G18

VID[6]

C13

D13

PLACE IN CAVITY

1

C50

2

1U_ 0402_6.3V6K

1

C291

2

10U _0805_10V6K

+1.5VS

CP U_VID 0
CP U_VID 1
CP U_VID 2
CP U_VID 3
CP U_VID 4
CP U_VID 5
CP U_VID 6

VC CSENSE

VSS SENSE

1U_ 0402_6.3V6K

1

C51

2

10U _0805_10V6K

1

C284

2

0.1U _0402_10V7K

1

C52

2

1U_ 0402_6.3V6K

1

C40

2

10U _0805_10V6K

0.1U _0402_10V7K

1

C45

C41

2

CP U_VID0 <40>
CP U_VID1 <40>
CP U_VID2 <40>
CP U_VID3 <40>
CP U_VID4 <40>
CP U_VID5 <40>
CP U_VID6 <40>

1U_ 0402_6.3V6K

1

C58

2

10U _0805_10V6K

1

C76

2

1

2

1U_ 0402_6.3V6K

130mA

1

C59

2

1U_ 0402_6.3V6K

1

C294

2

10U _0805_10V6K

1U_ 0402_6.3V6K

1

C68

2

PLACE IN CAVITY

1U_ 0402_6.3V6K

1

2

10U _0805_10V6K

1

C75

2

PLACE IN CORRIDOR AND CLOSE TO CPU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

Title

Size Doc umen t Numb er R ev

B

2

Da te: Sheet o f

Compal Electronics, Inc.

Diamondville(2/2)

LA-4421P

5 42Mo nday, Ap ril 06, 2 009

1

0.2

5

4

3

2

1

H_D #[0..63]<4>

D D

C C

+VCCP

12

12

R37

R226

54.9_0402_1%

54.9_0402_1%

B B

12

R35

R227

24.9_0402_1%

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_XRCOMP
H_XSCOMP

+H_SWNG0

H_YRCOM P
H_YSCOMP

+H_SWNG1

12

24.9_0402_1%

AB4
AB8

AA9
AA8
AB1
AB7
AA2
AB5

A10

C15

C4
F6
H9
H6
F7
E3
C2
C3
K9
F5

J7
K7
H8
E5
K8

J8

J2

J3
N1

M5

K5

J5
H3

J4
N3

M4
M3

N8
N6
K3
N9

M1

V8
V9
R6
T8
R2
N5
N2
R5
U7
R8
T4
T7
R3
T5
V6
V3

W2
W1

V2

W4
W7
W5

V5

W8

A6

J1
K1
H1

U8A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31

H_ADS#
H_ADSTB#_0
H_ADSTB#_1

H_VREF0

H_BNR#

H_BPRI#

H_BREQ0#

H_CPURST#

H_VREF1

HCLKN

HOST

HCLKP

H_DBSY#
H_DEFER#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DPWR#

H_DRDY#

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_HIT#

H_HITM#

H_LOCK#
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

H_SLPCPU#

H_TRDY#

Calistoga-G SE_FCBGA998

F8
D12
C13
A8
E13
E12
J12
B13
A13
G13
A12
D14
F14
J13
E17
H15
G15
G14
A15
B18
B15
E14
H13
C14
A17
E15
H17
D17
G17

F10
C12
H16
E2
B9
C7
G8
B10
E1

AA6
AA5
C10
C6
H5
J6
T9
U6
G7
E6
F3
M8
T1
AA3
F4
M7
T2
AB3

C8
B4
C5
G9
E9
G12
B8
F12
A5
B6
G10
E8
E10

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_ADS#
H_ADSTB#0
H_ADSTB#1
+H_VREF
H_BNR#
H_BPRI#
H_BR0#
H_RESET#
+H_VREF

CLK_MCH_BCLK#
CLK_MCH_BCLK
H_ DBSY#
H_DEF ER#
H_DIN V#0
H_DIN V#1
H_DIN V#2
H_DIN V#3
H_DPWR#
H_D RDY#
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_HIT#
H_HITM#
H_LOCK#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_CPUSLP#
H_ TRDY#

H_A#[ 3..31] <4>

H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>

H_BNR# <4>
H_BPR I# <4>
H_BR0# <4>
H_RESET# <4>

CLK_MCH_BCLK# <14>
CLK_MCH_BCLK <14>
H_D BSY# <4>
H_DEF ER# <4>
H_DIN V#0 <4>
H_DIN V#1 <4>
H_DIN V#2 <4>
H_DIN V#3 <4>
H_DPWR# <4>
H_D RDY# <4>

H_DST BN#[0..3] <4>

H_DST BP#[0..3] <4>

H_HIT# <4>
H_HITM# <4>
H_LOCK# <4>

H_RE Q#[0..4] <4>

H_R S#[0..2] <4>

H_CPUSLP# <4>
H_TR DY# <4>

+DIMM_VREF

DMI_TXN0<19>
DMI_TXN1<19>
DMI_TXP0<19>
DMI_TXP1<19>

DMI_RXN0<19>
DMI_RXN1<19>
DMI_RXP0<19>
DMI_RXP1<19>

M_CLK_DDR0<13>
M_CLK_DDR1<13>

M_CLK_DDR#0<13>
M_CLK_DDR#1<13>

DDR_C KE0<13>
DDR_C KE1<13>

DDR_C S0#<13>
DDR_C S1#<13>

+1.8V

R56 80.6_0402_1%

1 2
1 2

R54 80.6_0402_1%

1

Layout Note:
+DIMM_ VREF trace

C293

2

width and spacing
is 20/20.

0.1U_0402_16V4Z

AF33

AG1

AM30

AG33

AF1

AK1

AN30

AN21
AN22

AF26
AF25

AG14

AF12
AK14

AH12

AJ21
AF11

AE12
AF14
AJ14
AJ12

AN12
AN14

AA33

AE1

Y29
Y32
Y28
Y31

V28
V31
V29
V32

AJ1

U8B

DMI_RXN_0
DMI_RXN_1
DMI_RXP_0
DMI_RXP_1

DMI_TXN_0
DMI_TXN_1
DMI_TXP_0
DMI_TXP_1

SM_CK_0
SM_CK_1

SM_CK_2
SM_CK_3

SM_CK#_0
SM_CK#_1

SM_CK#_2
SM_CK#_3

SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_OCDCOMP_0
SM_OCDCOMP_1

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMPN
SM_RCOMPP
SM_VREF_0
SM_VREF_1

Calistoga-G SE_FCBGA998

DMI

DDR2 MUXING

RESERVED1
RESERVED2
RESERVED7
RESERVED8
RESERVED9

CFG/RSVD

PM_ICHSYNC#

PM_BMBUSY#
PM_EXTTS#_0

PM

PM_EXTTS#_1

THRMTRIP#

PWROK

RSTIN#

D_REFCLKN
D_REFCLKP

CLK

D_REFSSCLKN
D_REFSSCLKP

CLKREQ#

CFG_0
CFG_1
CFG_2
CFG_3
CFG_5
CFG_6

C18
E18
G20
G18
J20
J18

K32
K31
C17
F18
A3

E31
G21
F26
H26
J15
AB29
W27

A27
A26
J33
H33
J22

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

T2

CFG5

PM_EXTTS#0
PM_EXTTS#1

PLTRST_R#

PAD

1 2

R34 2.2K_0402_5%

T3PAD

R44 0_0402_5%

H_THERMTRIP#

ICH_P OK

1 2

R47 100_0402_5%

MCH_CLKSEL0 <14>
MCH_CLKSEL1 <14>
MCH_CLKSEL2 <14>

MCH _ICH_SYNC # <17>

PM_BMBUSY# <19>
PM_EXTTS#0 <13>

12

PM_DPRSLPVR <19,40>

H_THERMTRIP# <4,18>

ICH_P OK <19,27>

PLTRST# <17,19,21,25>

CLK_M CH_DREFCLK# <14>
CLK_M CH_DREFCLK <14>
MCH_ SSCDREFCLK# <14>
MCH_ SSCDREFCLK <14>
MCH_CLKREQ# <14>

DMI_TXN0
DMI_TXN1
DMI_TXP0
DMI_TXP1

DMI_RXN0
DMI_RXN1
DMI_RXP0
DMI_RXP1

M_CLK_DDR0
M_CLK_DDR1

M_CLK_DDR#0
M_CLK_DDR#1

DDR_C KE0
DDR_C KE1

DDR_C S0#
DDR_C S1#

M_ODT0<13>
M_ODT1<13>

M_ODT0
M_ODT1

SMRCOMPN
SMRCOMPP

10uA

Strap Pin Table

CFG5

Low = DMI x 2

High = DMI x 4

*

Layout Note:
H_XR COMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SW NG1 trace width and spacing is 10/20.

+VCCP

12

A A

R27

100_0402_1%

+H_VREF

12

1

C31

R29

2

200_0402_1%

5

C be placed <100mils
from GMCH pin

0.1U_0402_16V4Z

+VCCP

R18

R17

12

+H_SWNG0

221_0402_1%~D

12

1

C29

2

100_0402_1%

0.1U_0402_16V4Z

4

+VCCP

R33

R30

12

+H_SWNG1

221_0402_1%~D

12

1

C33

2

100_0402_1%

0.1U_0402_16V4Z

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

2

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

PM_EXTTS#0

PM_EXTTS#1

1 2

R42 10K_0402_5%

@

1 2

R43 10K_0402_5%

Compal Electronics, Inc.

Calistoga(1/5)-GTL/DMI/DDR

LA-4421P

1

+3VS

0.2

6 42Monday, A pril 06, 2009

5

4

3

2

1

D D

DDR_ A_DQS#[0..7 ]<13>

C C

B B

DDR_A_BS 0<13>
DDR_A_BS 1<13>
DDR_A_BS 2<13>

DDR_ A_DM[0..7]<13>

DDR_ A_DQS[0..7]<13>

DDR_A_ MA[0..13]<13>

DDR_A_ CAS#<13>
DDR_A_ RAS#<13>

DDR_A_W E#<13>

DDR_A_ DM0
DDR_A_ DM1
DDR_A_ DM2
DDR_A_ DM3
DDR_A_ DM4
DDR_A_ DM5
DDR_A_ DM6
DDR_A_ DM7

DDR_A_ DQS0
DDR_A_ DQS1
DDR_A_ DQS2
DDR_A_ DQS3
DDR_A_ DQS4
DDR_A_ DQS5
DDR_A_ DQS6
DDR_A_ DQS7

DDR_A_DQ S#0
DDR_A_DQ S#1
DDR_A_DQ S#2
DDR_A_DQ S#3
DDR_A_DQ S#4
DDR_A_DQ S#5
DDR_A_DQ S#6
DDR_A_DQ S#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_ A_CAS#
DDR_ A_RAS#

DDR_A_W E#

AK12
AH11
AG17

AB30

AL31
AF30
AK26

AL9
AG7
AK5
AH3

AC28

AJ30

AK33

AL25

AN9
AH8
AM2
AE3

AC29
AK30

AJ33

AM25

AN8

AJ8
AM3
AE2

AJ15
AM17
AM15
AH15
AK15
AN15

AJ18
AF19
AN17

AL17
AG16

AL18
AG18

AL14

AJ17
AK18
AN28
AM28
AH17

AH21

AJ20
AE27

AN20

AL21
AK21
AK22

AL22
AH22
AG22
AF21
AM21
AE21

AL20
AE22
AE26
AE20

U8C

SA_BS_0
SA_BS_1
SA_BS_2

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

SB_BS_0
SB_BS_1
SB_BS_2

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8

SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47

DDR2 SYSTEM MEMORY

SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

SB_CAS#

SB_RAS#

SB_WE#

Calistoga -GSE_FCBGA998

AC31
AB28
AE33
AF32
AC33
AB32
AB31
AE31
AH31
AK31
AL28
AK27
AH30
AL32
AJ28
AJ27
AH32
AF31
AH27
AF28
AJ32
AG31
AG28
AG27
AN27
AM26
AJ26
AJ25
AL27
AN26
AH25
AG26
AM12
AL11
AH9
AK9
AM11
AK11
AM8
AK8
AG9
AF9
AF8
AK6
AF7
AG11
AJ6
AH6
AN6
AM6
AK3
AL2
AM5
AL5
AJ3
AJ2
AG2
AF3
AE7
AF6
AH5
AG3
AG5
AF5

AG19
AG21
AG20

DDR _A_D0
DDR _A_D1
DDR _A_D2
DDR _A_D3
DDR _A_D4
DDR _A_D5
DDR _A_D6
DDR _A_D7
DDR _A_D8
DDR _A_D9
DDR_ A_D10
DDR_ A_D11
DDR_ A_D12
DDR_ A_D13
DDR_ A_D14
DDR_ A_D15
DDR_ A_D16
DDR_ A_D17
DDR_ A_D18
DDR_ A_D19
DDR_ A_D20
DDR_ A_D21
DDR_ A_D22
DDR_ A_D23
DDR_ A_D24
DDR_ A_D25
DDR_ A_D26
DDR_ A_D27
DDR_ A_D28
DDR_ A_D29
DDR_ A_D30
DDR_ A_D31
DDR_ A_D32
DDR_ A_D33
DDR_ A_D34
DDR_ A_D35
DDR_ A_D36
DDR_ A_D37
DDR_ A_D38
DDR_ A_D39
DDR_ A_D40
DDR_ A_D41
DDR_ A_D42
DDR_ A_D43
DDR_ A_D44
DDR_ A_D45
DDR_ A_D46
DDR_ A_D47
DDR_ A_D48
DDR_ A_D49
DDR_ A_D50
DDR_ A_D51
DDR_ A_D52
DDR_ A_D53
DDR_ A_D54
DDR_ A_D55
DDR_ A_D56
DDR_ A_D57
DDR_ A_D58
DDR_ A_D59
DDR_ A_D60
DDR_ A_D61
DDR_ A_D62
DDR_ A_D63

DDR_ A_D[0..63 ] <13>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

Title

Size Do cument Numbe r R ev

Cust om

2

Date: Sheet o f

Compal Electronics, Inc.

Calistoga(2/5)-DDR2

LA-4421P

7 42Monday, Apr il 06, 2009

1

0.2

5

D D

GMCH _CRT_ R

R225 150_0402_1%

R223 150_0402_1%

R222 150_0402_1%

12

12

12

GMCH _CRT_G

GMCH _CRT_B

Close to U8.H25

12

R39 255_0402_1%

C C

+3VS

1 2

R32 10K_0402_5%

1 2

B B

R40 10K_0402_5%

LCT LA_CLK

LCTLB_DATA

R224 100K_0402_5%

GMCH _ENBKL<27>

R38 1.5K_0402_1%

4

U8 F

H27

SDVO_CTRLDATA

J27

SDVO_CTRLCLK

CLK _MCH_3GPLL#<14>
CLK _MCH_3GPLL<14>

GMCH _CRT_ CLK<16>
GMCH _CRT_DATA<16>

GMCH _CRT_B<16>

GMCH _CRT_G<16>

GMCH _CRT_ R<16>

GM CH_C RT_VSYN C<16>
GM CH_C RT_HS YNC<16>

12

LVD S_SCL<15>
LVD S_SDA<15>

GM CH_EN VDD<15>

12

LVD S_ACLK#<15>
LVD S_ACLK<15>

LVD S_A0#<15>
LVD S_A1#<15>
LVD S_A2#<15>

LVD S_A0<15>
LVD S_A1<15>
LVD S_A2<15>

GMCH _CRT_B

GMCH _CRT_G

GMCH _CRT_ R

CR T_IRE F

LCT LA_CLK
LCTLB_DATA
LVD S_SCL
LVD S_SDA

L_IBG

LVD S_ACLK#
LVD S_ACLK

LVD S_A0#
LVD S_A1#
LVD S_A2#

LVD S_A0
LVD S_A1
LVD S_A2

Y26

AA26

H20
H22
A24
A23
E25
F25
C25
D25
F27
D27
H25

H30
G29
F28
E28
G28
H28
K30
K27

K29

D30
C30
A30
A29

G31
F32
D31

H31
G32
C31

F33
D33
F30

E33
D32
F29

J29
J30

G_CLKN
G_CLKP

CRT_DDC_CLK
CRT_DDC_DATA
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
CRT_VSYNC
CRT_HSYNC
CRT_IREF

L_BKLTCTL
L_BKLTEN
L_CLKCTLA
L_CTLBDATA
L_DDC_CLK
L_DDC_DATA
L_VDDEN
L_IBG
L_VBG
L_VREFH
L_VREFL

LA_CLKN
LA_CLKP
LB_CLKN
LB_CLKP

LA_DATAN_0
LA_DATAN_1
LA_DATAN_2

LA_DATAP_0
LA_DATAP_1
LA_DATAP_2

LB_DATAN_0
LB_DATAN_1
LB_DATAN_2

LB_DATAP_0
LB_DATAP_1
LB_DATAP_2

3

EXP_A_COMPI

EXP_A_ICOMPO

SDVO_TVCLKIN#

SDVO_INT#

SDVO_FLDSTALL#

MISC

SDVO_TVCLKIN

SDVO_INT

SDVO_FLDSTALL

SDVO

SDVO_RED#

SDVO_GREEN#

SDVO_BLUE#

SDVO_CLKN

SDVO_RED

SDVO_GREEN

SDVO_BLUE
SDVO_CLKP

TV_DACA
TV_DACB
TV_DACC

TV_IREF

TV_IRTNA

TV

TV_IRTNB

LVDS VGA

TV_IRTNC

TV_DCONSEL0
TV_DCONSEL1

Calisto ga-GSE_ FCBGA 998

R28
M28

N30
R30
T29

M30
P30
T30

P28
N32
P32
T32

N28
M32
P33
R32

A21
C20
E20
G23
B21
C21
D21

G26
J26

PEGCOMP

+1.5VS

+1.5 VS_PC IE

R45

24.9_0402_1%

1 2

Disable TV

2

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

Title

Size Doc umen t Numb er R ev

B

2

Da te: Sheet o f

Compal Electronics, Inc.

Calistoga(3/5)-VGA/LVDS/TV

LA-4421P

8 42Mo nday, Ap ril 06, 2 009

1

0.2

5

+VCCP

D D

C C

+VCCP

B B

A A

W22

W21

W20

W14

AB10
AA10

T25
R25
P25
N25
M25
P24
N24
M24
Y22

V22
U22
T22
R22
P22
N22
M22
Y21

V21
U21
T21
R21
P21
N21
M21
Y20

V20
U20
T20
R20
P20
N20
M20
Y19
P19
N19
M19
Y18
P18
N18
M18
Y17
P17
N17
M17
Y16
P16
N16
M16
Y15
P15
N15
M15
Y14

V14
U14
T14
R14
P14
N14
M14

T10
R10
P10
N10

L10

D1

M10
A18

U8H

VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64

VTT_NCTF1
VTT_NCTF2
VTT_NCTF3
VTT_NCTF4
VTT_NCTF5
VTT_NCTF6

RSVD_3
RSVD_4
RSVD_5
RSVD_6

NCTF

Calistoga-G SE_FCBGA998

4

VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19

CFG_19

RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED14
RESERVED15
RESERVED16
RESERVED17
RESERVED18
RESERVED19
RESERVED20
RESERVED21
RESERVED22
RESERVED23
RESERVED24
RESERVED25

AD25
AC25
AB25
AD24
AC24
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
K14
AD13
Y13
W13
V13
U13
T13
R13
P13
N13
M13
AD12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
AD11
AD10
K10
AN33
AA25
V25
U25
AA22
AA21
AA20
AA19
AA18
AA17
AA16
AA15
AA14
AA13
A4
A33
B2
AN1
C1

K28

K25
K26
R24
T24
K21
K19
K20
K24
K22
J17
K23
K17
K12
K13
K16
K15

+1.5VS

3

U8E

AH33

VSS_1

AK32

AG32

AE32
AC32
AA32

AM31

AJ31

AA31

AL30

AG30

AE30
AC30
AA30

AA29

AK28
AH28
AE28
AA28

AM27

AF27
AB27
AA27

AL26

AH26

W26

AN25
AK25

AG25

AE25

AM22

AJ22

AF22

AM20

AK20
AH20
AF20

W19

AM18

AH18
AF18

AK17

AH16

Y33

VSS_2

V33

VSS_3

R33

VSS_4

G33

VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10

U32

VSS_11

H32

VSS_12

E32

VSS_13

C32

VSS_14
VSS_15
VSS_16
VSS_17

U31

VSS_18

T31

VSS_19

R31

VSS_20

P31

VSS_21

N31

VSS_22

M31

VSS_23

J31

VSS_24

F31

VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30

Y30

VSS_31

V30

VSS_32

U30

VSS_33

G30

VSS_34

E30

VSS_35

B30

VSS_36
VSS_37

U29

VSS_38

R29

VSS_39

P29

VSS_40

N29

VSS_41

M29

VSS_42

H29

VSS_43

E29

VSS_44

B29

VSS_45
VSS_46
VSS_47
VSS_48
VSS_49

U28

VSS_50

T28

VSS_51

J28

VSS_52

D28

VSS_53
VSS_54
VSS_55
VSS_56
VSS_57

Y27

VSS_58

U27

VSS_59

T27

VSS_60

R27

VSS_61

P27

VSS_62

N27

VSS_63

M27

VSS_64

G27

VSS_65

E27

VSS_66

C27

VSS_67

B27

VSS_68
VSS_69
VSS_70
VSS_71

U26

VSS_72
VSS_73
VSS_74
VSS_75
VSS_76

J25

VSS_77

G25

VSS_78

A25

VSS_79

H23

VSS_80

F23

VSS_81

B23

VSS_82
VSS_83
VSS_84
VSS_85

G22

VSS_86

E22

VSS_87

J21

VSS_88

H21

VSS_89

F21

VSS_90
VSS_91
VSS_92
VSS_93
VSS_94

D20

VSS_95
VSS_96

R19

VSS_97
VSS_98
VSS_99
VSS_100

U18

VSS_101

H18

VSS_102

D18

VSS_103
VSS_104

V17

VSS_105

T17

VSS_106

F17

VSS_107

B17

VSS_108
VSS_109

U16

VSS_110

VSS

Calistoga-G SE_FCBGA998

VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185

J16
AL15
AG15
W15
R15
F15
D15
AM14
AH14
AE14
H14
B14
F13
D13
AL12
AG12
H12
B12
AN11
AJ11
AE11
AM9
AJ9
AB9
W9
R9
M9
J9
F9
C9
A9
AL8
AG8
AE8
U8
AA7
V7
R7
N7
H7
E7
B7
AL6
AG6
AE6
AB6
W6
T6
M6
K6
AN5
AJ5
B5
AA4
V4
R4
N4
K4
H4
E4
AL3
AD3
W3
T3
B3
AK2
AH2
AF2
AB2
M2
K2
H2
F2
V1
R1

2

U8G

W33

NC1

AM33

NC2

AL33

NC3

C33

NC4

B33

NC5

AN32

NC6

A32

NC7

AN31

NC8

W28

NC9

V27

NC10

W29

NC11

J24

NC12

H24

NC13

W32

NC14

G24

NC15

F24

NC16

E24

NC17

D24

NC18

K33

NC19

A31

NC20

E21

NC21

C23

NC22

AN19

NC23

AM19

NC24

AL19

NC25

AK19

NC26

AJ19

NC27

AH19

NC28

AN3

NC29

Y9

NC30

J19

NC31

H19

NC32

G19

NC33

F19

NC34

E19

NC35

D19

NC36

C19

NC37

B19

NC38

A19

NC39

Y8

NC40

G16

NC41

F16

NC42

E16

NC43

D16

NC44

C16

NC45

B16

NC46

AN2

NC47

A16

NC48

Y7

NC49

AM4

NC50

AF4

NC51

AD4

NC52

AL4

NC53

AK4

NC54

W31

NC55

AJ4

NC56

AH4

NC57

AG4

NC58

AE4

NC59

AM1

NC60

Calistoga-G SE_FCBGA998

NC

RESERVED26
RESERVED27
RESERVED28
RESERVED29
RESERVED30
RESERVED31
RESERVED32
RESERVED33
RESERVED34
RESERVED35
RESERVED36
RESERVED37
RESERVED38
RESERVED39
RESERVED40
RESERVED41
RESERVED42

1

W30

NC61

Y6

NC62

AL1

NC63

Y5

NC64

Y10

NC65

W10

NC66

W25

NC67

V24

NC68

U24

NC69

V10

NC70

U10

NC71

K18

NC72

Y25
Y24
AB22
AB21
AB19
AB16
AB14
AA12
W24
AA24
AB24
AB20
AB18
AB15
AB13
AB12
AB17

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

Calistoga(4/5)-PWR/GND

LA-4421P

9 42Monday, A pril 06, 2009

1

0.2

2940mA

1

+

C279

2

10U_0805_10V4Z

5

T26
R26
P26
N26

M26

V19

1

1

C274

2

2

10U_0805_10V4Z

1

1

C37

2

0.1U_0402_16V4Z

1

C55

C43

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.5VS

1250mA

1

C32

2

0.1U_0402_16V4Z

+VCCP

780mA

C268

1 2

10mil

0.47U_ 0603_16VY5V

C267

1 2

10mil

0.47U_ 0603_16VY5V

1

+

C273

2

220U_B2_2.5VM_R35

1

1

C57

C38

2

2

4.7U_0 603_6.3V4Z

4.7U_0 603_6.3V4Z

10mil

2

2

0.47U_ 0603_16VY5V

5

C66

1

1

U19
T19

W18

V18
T18
R18

W17

U17
R17

W16

V16
T16
R16
V15
U15
T15

AD33
AD32
AD31
AD30
AD29
AD28
AD27
AC27
AD26
AC26
AB26
AE19
AE18

AF17

AE17

AF16

AE16

AF15

AE15

J14

J10
H10

AE9
AD9

U9
AD8
AD7
AD6

U1_A14

A14
D10

P9
L9

D9

P8
L8

D8

P7
L7

D7

U1_A7

A7
P6

L6
G6
D6
U5

P5

L5
G5
D5

Y4
U4

P4

L4
G4
D4

Y3
U3

P3

L3
G3
D3

Y2
U2

P2

L2
G2
D2

U1_AA1

AA1

U1_F1

F1

10mil

C30

0.47U_ 0603_16VY5V

+VCCP

C44

D D

C C

B B

A A

220U_B2_2.5VM_R35

U8D

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21

VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT36
VTT35
VTT37
VTT38
VTT39
VTT40

4

VCCATVDACA0
VCCATVDACA1
VCCATVDACB0

VCCATVDACB1
VCCATVDACC0
VCCATVDACC1

VCCATVBG
VSSATVBG

VCCDTVDAC

VCCDQTVDAC

VCCDLVDS0
VCCDLVDS1
VCCDLVDS2

VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51

VCCAMPLL

VCCAHPLL
VCCADPLLA
VCCADPLLB

POWER

VCCDHMPLL1
VCCDHMPLL2

VCCTXLVDS0
VCCTXLVDS1

VCCA3GPLL

VCCA3GBG
VSSA3GBG

VCCSYNC
VCCACRTDAC0
VCCACRTDAC1

VSSACRTDAC

VCCALVDS

VSSALVDS

Calistoga-G SE_FCBGA998

4

VCCHV0
VCCHV1
VCCHV2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9

VCC3G0
VCC3G1

VTT41
VTT42
VTT43
VTT44
VTT45

B20
A20
B22
A22
D22
C22
D23
E23
F20
F22
C28
B28
A28
E26
D26
C26
AB33
AM32
AN29
AM29
AL29
AK29
AJ29
AH29
AG29
AF29
AE29
AN24
AM24
AL24
AK24
AJ24
AH24
AG24
AF24
AE24
AN18
AN16
AM16
AL16
AK16
AJ16
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AN4
AM10
AL10
AK10
AH1
AH10
AG10
AF10
AE10
AN7
AM7
AL7
AK7
AJ7
AH7
AN10
AJ10
AD1
AD2
B26
J32
AE5
AD5
D29
C29
U33
T33
V26
N33
M33
J23
C24
B24
B25
B31
B32

P1
L1
G1
U1
Y1

+1.5VS

400mA

2mA

10mA

144mA

Disable TV

20mA

40mA

U1_AB33
U1_AM32

10mil

10mil

10mil

10mil

+1.5VS_MPLL
+1.5VS_HPLL
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS

+2.5VS

+1.5VS_3GPLL
+2.5VS

+2.5VS_CRTDAC

+2.5VS

3

+1.5VS

+3VS

10mil

1

1

C73

C82

C297

1U_0603_10V4Z

150mA

60mA

2

2

1U_0603_10V4Z

1U_0603_10V4Z

1

C81
1U_0603_10V4Z

2

1

C85
1U_0603_10V4Z

2

1

2

45mA
45mA

50mA
50mA

Route +2.5VS fr om GMCH pinN33 to
deco upling ca p <200mil to the edge.

1

1

C269

2

2

C24

10U_0805_10V4Z

0.1U_0402_16V4Z

+1.8V

533 MTS=1720mA

1

1

1

C84

C83

C74

2

2

2

4.7U_0 603_6.3V4Z

1U_0603_10V4Z

4.7U_0 603_6.3V4Z

C39

400mA

70mA
70mA

+VCCP

1

2

1

1

C28

2

2

C27

0.1U_0402_16V4Z

0.022U_0402_16V7K

Route VSSACRTDAC gnd from GMCH to
deco upling ca p ground lead and then
conn ect to the gnd plane.

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

R229

12

10_0603_5%

C25

10U_0805_10V4Z

+2.5VS

CRTDAC: Route FB
within 3" of Cal istoga

2006/08/18 2007/8/18

1

1

C265

2

2

C20

10U_0805_10V4Z

0.1U_0402_16V4Z

+2.5VS

1

2

0.1U_0402_16V4Z

+2.5VS

1

C34

C270

2

10U_0805_10V4Z

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

1

2

C285

2

1

2

10U_0805_10V4Z

2

+1.5VS_MPLL

C288

+1.5VS_PCIE

C283

10U_0805_10V4Z

PCI-E/MEM/PSB PLL decoupling

R46

0_0603_5%

+1.5VS

+1.5VS +1.5VS

+1.5VS

C42

+2.5VS

4.7U_0 603_6.3V4Z

12

1

2

+1.5VS

+1.5VS_HPLL

1

C282

2

0.1U_0402_16V4Z

+1.5VS_DPLLA+1.5VS_DPLLB

0.1U_040 2_16V4Z~D

1

2

1

C35

2

0.1U_0402_16V4Z

clos e pin C29/D29

Compal Electronics, Inc.

Calistoga(5/5)-PWR/GND

LA-4421P

1

C287

2

0.1U_0402_16V4Z

330U_D2E_2.5VM

0.1U_040 2_16V4Z~D

C36

1

+

2

1

1

C292

2

2

220U_B2_2.5VM_R35

+1.5VS_3GPLL

1

1

C54

C56

2

2

10U_0805_10V4Z

0.1U_0402_16V4Z

45mA Max.

R236
0_0603_5%

12

1

2

10U_0805_10V4Z

L10

1 2

FBMA-L10-160808-301LMT_2P

1

C264

2

R239

12

0_0805_5%

+

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

1

+1.5VS+1.5VS_3GPLL

1

C69

@

2

0.1U_0402_16V4Z

45mA Max.

R235
0_0603_5%

1

C281

2

10U_0805_10V4Z

40mA Max.40mA Max.

L9

1 2

330U_D2E_2.5VM

FBMA-L10-160808-301LMT_2P

1

C21

C263

+

2

+2.5VS

1

C271

2

0.01U_0402_25V7K

clos e pin B31

10 42Monday, A pril 06, 2009

1

12

+1.5VS

1

C272

2

0.1U_0402_16V4Z

0.2

5

DDR_A _DQS#[0.. 7]<7>

DDR _A_D[0..6 3]<7>

DDR_A _DM[0..7]<7>

DDR_ A_DQS[0.. 7]<7>

DDR_A _MA[0..13]<7>

D D

+1.8V

2

2

2

C129

C128

1

2.2U_0 603_6.3V4Z

1

+

@

C94

C106

2

220U_B2_2.5VM_R35

C C

+0.9VS

1

C117

2

0.1U_0402_16V4Z

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

1

C86

2

0.1U_0402_16V4Z

RP6

1 8
2 7
3 6
4 5

RP2

1 8
2 7
3 6
4 5

RP3

1 8
2 7
3 6
4 5

1

C119

B B

A A

2

0.1U_0402_16V4Z

DDR_A_MA0
DDR_A_MA13
DDR_C S0#
M_ODT0

DDR_A_MA1
DDR_A_MA3
DDR_A_MA5
DDR_A _CAS#

DDR_A_WE#
DDR_A_BS0
M_ODT1
DDR_C S1#

C110

1

2.2U_0 603_6.3V4Z

1

1

C105

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Layout Note:
Plac e on e cap close to every 2 pullup
resi stor s terminated to +0.9VS

1

C87

C121

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+0.9VS

56_0804_8P4R_5%

56_0804_8P4R_5%

2

C109

1

1

2.2U_0 603_6.3V4Z

2.2U_0 603_6.3V4Z

1

C108

2

0.1U_0402_16V4Z

1

1

C88

C122

2

2

0.1U_0402_16V4Z

RP5

18
27
36
45

RP4

18
27
36
45

RP1

DDR_A_MA12

18
27
36

DDR_A_MA10

45

56_0804_8P4R_5%

C130

1

C107

2

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

DDR_A _RAS#

DDR_A_MA4
DDR_A_MA2
DDR_A_BS1

DDR_C KE1
DDR_A_MA7
DDR_A_MA6

DDR_A_MA11

DDR_A_MA9
DDR_A_MA8

2

1

2.2U_0 603_6.3V4Z

1

C91

C115

2

0.1U_0402_16V4Z

Layout Note:
Plac e near JDIM1

1

2

0.1U_0402_16V4Z

4

1

1

C90

C120

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Layout Note:
Place these resistor
closel y DIMMA,all
trace length<750 mil

3

CLK_SMBDATA<14>

DDR_A_BS2<7>

DDR_A_BS0<7>
DDR_A_WE#<7>

DDR_A_CAS#<7>

CLK_SMBCLK<14>

DDR_C KE0<6>

DDR_C S1#<6>

M_ODT1<6>

+DIMM_VREF

DDR_A _D0
DDR_A _D1

DDR_A _DQS#0
DDR_A _DQS0

DDR_A _D2
DDR_A _D3

DDR_A _D9
DDR_A _D8

DDR_A _DQS#1
DDR_A _DQS1

DDR_A _D10
DDR_A _D11

DDR_A _D16
DDR_A _D17

DDR_A _DQS#2
DDR_A _DQS2

DDR_A _D18
DDR_A _D19

DDR_A _D24
DDR_A _D25

DDR_A_DM3

DDR_A _D26
DDR_A _D27

DDR_C KE0

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A _CAS#
DDR_C S1#

M_ODT1

DDR_A _D32
DDR_A _D33

DDR_A _DQS#4
DDR_A _DQS4

DDR_A _D34
DDR_A _D35

DDR_A _D40
DDR_A _D41

DDR_A_DM5

DDR_A _D42
DDR_A _D43

DDR_A _D48
DDR_A _D49

DDR_A _DQS#6
DDR_A _DQS6

DDR_A _D50
DDR_A _D51

DDR_A _D56
DDR_A _D57

DDR_A_DM7

DDR_A _D58
DDR_A _D59

CLK_SMBDATA
CLK_SMBCLK

+3VS

+1.8V

12

R61

1K_0402_1%

+DIMM_VREF

12

R62

1K_0402_1%

+DIMM_VREF

1

1

C89

C118

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Shar e +DIMM_VREF for

1.DDRII VREF

2.GM CH SM_VREF_0
SM_VREF_1

20mils

1

C111

0.1U_0402_16V4Z

2

1

C112

2.2U_0 603_6.3V4Z

2

+3VS

1

C116

2

0.1U_0402_16V4Z

2

+1.8V +1.8V

JDIM1

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_AS0A426-N4SN-7F

ME@

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106

BA1

108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198

SA0

200

SA1

DIMMA

DDR_A _D4
DDR_A _D5

DDR_A_DM0

DDR_A _D6
DDR_A _D7

DDR_A _D12
DDR_A _D13

DDR_A_DM1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A _D14
DDR_A _D15

DDR_A _D20
DDR_A _D21

DDR_A_DM2

DDR_A _D22
DDR_A _D23

DDR_A _D28
DDR_A _D29

DDR_A _DQS#3
DDR_A _DQS3

DDR_A _D30
DDR_A _D31

DDR_C KE1

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS1
DDR_A _RAS#
DDR_C S0#

M_ODT0
DDR_A_MA13

DDR_A _D36
DDR_A _D37

DDR_A_DM4

DDR_A _D38
DDR_A _D39

DDR_A _D44
DDR_A _D45

DDR_A _DQS#5
DDR_A _DQS5

DDR_A _D46
DDR_A _D47

DDR_A _D52
DDR_A _D53

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_DM6

DDR_A _D54
DDR_A _D55

DDR_A _D60
DDR_A _D61

DDR_A _DQS#7
DDR_A _DQS7

DDR_A _D62
DDR_A _D63

R66 10K_0402_5%

1 2

R65 10K_0402_5%

1 2

R64

M_CLK_DDR0 <6>
M_CLK_DDR#0 <6>

1 2

DDR_C KE1 <6>

DDR_A_BS1 <7>
DDR_A _RAS# <7>
DDR_C S0# <6>

M_ODT0 <6>

M_CLK_DDR1 <6>
M_CLK_DDR#1 <6>

1

0_0402_5%

PM_EXTTS#0 <6>

DDR_A_BS2

DDR_C KE0

R60

1 2

56_0402_5%
R59

1 2

56_0402_5%

5

Layout Note:
Place these resistor
closel y DIMMA,all
trace length
Max=1.3"

4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

2

Title

Size Doc ument Number Re v

B

Date: Sheet of

Compal Electronics, Inc.

DDRII-SODIMMA

LA-4421P

13 42Monday, A pril 06, 2009

1

0.2

5

PCI

SRC

CPU

CLKS EL1

0

FSA

CLKS EL0

MHz

266

MHz

1000

MHz

MHz

33.30

14.318 96.0 48.0

DOT_96
MHz

USB
MHz

FSC FSB REF

CLKS EL2

0 1000 133 33.31 1 4.318 96.0 48.0

0 1001 200 33.30 1 4.318 96.0 48.0

0 1001 166 33.31 1 4.318 96.0 48.0

D D

1 1000 333 33.30 1 4.318 96.0 48.0

1 1000 100 33.31 1 4.318 96.0 48.0

1 1001 400 33.30 1 4.318 96.0 48.0

1 1 1

Res erved

4

+3VM_CK505

1 2

+3VS

+VCCP

R137 0_0805_5%

1 2

R138 0_0805_5%

1

C174

10U_0805_10V4Z

2

+1.05VM_CK505

1

C175

10U_0805_10V4Z

2

1

C172

0.1U_0402_16V 4Z

2

1

C139

0.1U_0402_16 V4Z

2

3

1

C138

0.1U_0402_16V 4Z

2

1

C167

0.1U_0402_16 V4Z

2

1

C148

0.1U_0402_16V 4Z

2

1

C137

0.1U_0402_16 V4Z

2

1

C140

0.1U_0402_16V 4Z

2

1

C146

0.1U_0402_16 V4Z

2

2

1

C160

0.1U_0402_16V 4Z

2

1

C165

0.1U_0402_16 V4Z

2

1

C169

0.1U_0402_16V 4Z

2

1

C173

0.1U_0402_16V 4Z

2

ICH_SMBDATA<19>

ICH_SMB CLK<19>

2N7002DW-T /R7_SOT363-6

+3VS

2N7002DW-T /R7_SOT363-6

2.2K_0402_5%

6 1

3

Q10A

Q10B

+3VS

2

5

1

R72

4

R91

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

SA000020K00 (Silego : SLG8SP556VTR )
SA000020H10 (ICS : ICS9LPRS387AKLFT)

+3VM_CK505

+VCCP

R68

R76

2.2K_0402_5%

C C

B B

A A

FSA

FS C

1 2

R69
0_0402_5%

1 2

R119
0_0402_5%

R98
10K_0402_5%

1 2

R84
0_0402_5%

CPU_BSEL0<4>

CPU_BSEL1<4>

CPU_BSEL2<4>

@

56_0402_5%

1 2

12

1 2

R67
1K_0402_5%

12

R73

1K_0402_5%

@

+VCCP

R113

1K_0402_5%

@

1 2

FSB

1 2

R115
1K_0402_5%

12

R110

@

0_0402_5%

+VCCP

R92

1K_0402_5%

@

1 2

1 2

12

R79
1K_0402_5%

12

R87

@

0_0402_5%

For PC I2_TME :0=Overclocking of CPU and SRC allowed
(ICS o nly) 1=Overclocking of CPU and SRC NOT allowed

C161 22P_0402_50V8J

14.31818MHZ_16P F_DSX840GA

C164 22P_0402_50V8J

Y1

Rou tin g the tr ace at least 1 0mil

5

MCH_CLKSEL0 <6>

CLK_48M_CR<26>

CLK_I CH_48M<19>

CLK_I CH_14M<19>

MCH_CLKSEL1 <6>

MCH_CLKSEL2 <6>

VGATE<19,27,40>

H_STP_CPU#<19>

H_STP_PCI#<19>

CLK_P CI_LPC<27>

CLK_P CI_ICH<17>

For ITP_ EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#

For P CI4_ SEL, 0 = Pin24/25 : DOT96 / DOT96#
Pin28/29 : LCDCLK / LCDCLK#

CLK_XTAL_IN

12

CLK_XTAL_OUT

1 = P in24 /25 : SRC_0 / SRC_0#
P in28/29 : 27M/27M_SS

+3VS+3VS +3VS

R85

10K_0402_5%

@

1 2

ITP_EN PCI4_SEL PCI2 _TME

R89

10K_0402_5%

1 2

4

1 2

1 2

@

1 2

CLK_4 8M_CR

C387

C390

C389

1

@

2

R95

10K_0402_5%

@

R90

10K_0402_5%

C386

10P_0402_50V8J

R75

1 2

10P_0402_50V8J@

1 2

12P_0402_50V8J

1

2

10P_0402_50V8J

R71

10K_0402_5%

1 2

@

R77

10K_0402_5%

1 2

+1.05VM_CK505

R74

1 2

22_0402_5%

1 2

22_0402_5%

1 2

1 2

1 2

C388

@

10P_0402_50V8J

R10433_0402_5%

VGATE

H_STP_CP U#

H_STP_PCI#

CLK_XTAL_IN

CLK_XTAL_OUT

R8633_0402_5%

R8033_0402_5%

FSA

FSB

FS C

PCI2_TME

PCI4_SEL

ITP_EN

U4

55

VDD_SRC

6

VDD_REF

12

VDD_PCI

72

VDD_CPU

19

VDD_48

27

VDD_PLL3

66

VDD_CPU_IO

31

VDD_PLL3_IO

62

VDD_SRC_IO

52

VDD_SRC_IO

23

VDD_IO

38

VDD_SRC_IO

20

USB_0/FS_A

2

FS_B/TEST_MODE

7

REF_0/FS_C/TEST_

8

REF_1

1

CKPWRGD/PD#

11

NC

53

CPU_STOP#

54

PCI_STOP#

5

XTAL_IN

4

XTAL_OUT

13

PCI_1

14

PCI_2

15

PCI_3

16

PCI_4/SEL_LCDCL

17

PCIF_5/ITP_EN

18

VSS_PCI

3

VSS_REF

22

VSS_48

26

VSS_IO

69

VSS_CPU

30

VSS_PLL3

34

VSS_SRC

59

VSS_SRC

42

VSS_SRC

73

VSS

SLG8SP556VT R_QFN72_10X10

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CPU_0#

CPU_1#

SRC_0/DOT_96

SRC_0#/DOT_96#

LCDCLK/27M

LCDCLK#/27M_SS

SRC_2#

SRC_3#

SRC_4#

SRC_6#

SRC_7#

SRC_8/CPU_ITP

SRC_8#/CPU_ITP#

SRC_9#

SRC_10

SRC_10#

SRC_11

SRC_11#

CLKREQ_3#

CLKREQ_4#

CLKREQ_6#

CLKREQ_7#

CLKREQ_9#

SLKREQ_10#

CLKREQ_11#

USB_1/CLKREQ_A#

2007/10/15 2008/10/15

9

SDA

10

SCL

71

CPU_0

70

68

CPU_1

67

24

25

28

29

32

SRC_2

33

35

SRC_3

36

39

SRC_4

40

57

SRC_6

56

61

SRC_7

60

64

63

44

SRC_9

45

50

51

48

47

37

41

58

65

43

49

46

21

Compal Secret Data

CLK_SMBDATA

CLK_SMBCLK

CLK_ CPU_BCLK

CLK_ CPU_BCLK#

CLK_MCH_ BCLK

CLK_MCH_ BCLK#

CLK_M CH_DREFCLK

CLK_M CH_DREFCLK#

MCH_S SCDREFCLK

MCH_S SCDREFCLK#

CLK_MCH_3GP LL

CLK_MCH_3GPL L#

CLK_PCIE_SATA

CLK_PCIE_S ATA#

CLK_PCI E_WLAN

CLK_PCI E_WLAN#

CLK_P CIE_LAN

CLK_PCI E_LAN#

CLK_P CIE_ICH

CLK_P CIE_ICH#

SATA_CLKREQ#

WL AN_CLKREQ#

CLKRE Q_LAN#

MCH_CLK REQ#

Deciphered Date

2

CLK_SMBDATA <13>

CLK_SMBCLK <13>

CLK_C PU_BCLK <4>

CLK_CPU _BCLK# <4>

CLK_MCH_BC LK <6>

CLK_MCH_BC LK# <6>

CLK_M CH_DREFCLK <6>

CLK_M CH_DREFCLK# <6>

MCH_S SCDREFCLK <6>

MCH_S SCDREFCLK# <6>

CLK_MCH_3GPLL <8>

CLK_MCH_3GPLL# <8>

CLK_PCIE_SATA <18>

CLK_PCIE_S ATA# <18>

CLK_PCIE_ WLAN <21>

CLK_PCIE_ WLAN# <21>

CLK_PCI E_LAN <25>

CLK_PCI E_LAN# <25>

CLK_P CIE_ICH <19>

CLK_P CIE_ICH# <19>

SATA_CLKREQ# <19>

WLAN_ CLKREQ# <21>

CLKREQ_LA N# <25>

MCH_CLKRE Q# <6>

Title

Size Document Number Rev

Date : Sheet o f

SRC PORT LIST

PORT

SRC0
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11

MCH_CLK REQ#
WL AN_CLKREQ#
SATA_CLKREQ#
CLKRE Q_LAN#

DEVICE

MCH_DREFCLK
MCH_3GPLL

PCIE_SATA
PCIE_WLAN

PCIE_LAN
PCIE_ICH

R78 10K_0402_5%
R121 10K_0402_5%
R105 10K_0402_5%
R106 10K_0402_5%

12
12
12
12

REQ PORT LIST

DEVICEPORT

REQ_3#
REQ_4#
REQ_6#
REQ_7#
REQ_9#
REQ_10#
REQ_11#
REQ_A#

Compal Electronics, Inc.

Clock Generator CK505

PCIE_SATA
PCIE_WLAN

PCIE_LAN

MCH_3GPLL

LA-4421P

1

14 42Monday, A pril 06, 2009

+3VS

0.2

5

4

3

2

1

LCD POWER CIRCUIT

G

2

+3VS

S

D

1 3

W=20mils

Q22
SI2301BDS_SOT23

+LCDVDD

1

C260

@

4.7U_0805_10V4Z

2

W=20mils

1

C261

0.1U_0402_16V4Z

2

R218
150_0603_5%

2

G

2

+3VALW

12

13

R219
47K_0402_5%

R221

100K_0402_5%

Q20
DTC124EK_SC59

12

2

C262

0.1U_0402_16V4Z

1

+LCDVDD

D D

2N7002_SOT23

GMCH_ ENVDD<8>

C C

12

13

D

Q21

S

+3VS

LCD/PANEL BD. Conn.

+LCDVDD_L

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

C18 0.1U_0603_50V4Z

+INVPWR_B+

+LCDVDD_L

INVT_PWM

BKOFF#

LVDS_SDA
LVDS_SCL

LVDS_ACLK#

LVDS_ACLK

LVDS_A2#
LVDS_A2

LVDS_A1#
LVDS_A1

LVDS_A0#
LVDS_A0

+3VS

B B

A A

5

JLVDS1

22

GND

21

GND

ACES_87213-2000G

ME@

20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

C12

1 2

4.7U_0805_10V4Z

L1 FBMA-L11-201209-221LMA30T_0805

1 2

L8 FBMA-L11-201209-221LMA30T_0805

1 2

INVT_PWM <27>

LVDS_ACLK# <8>

LVDS_ACLK <8>

LVDS_A2# <8>

LVDS_A2 <8>

LVDS_A1# <8>

LVDS_A1 <8>

LVDS_A0# <8>

LVDS_A0 <8>

4

C11

220P_0402_50V7K

LVDS_SCL

B+

+LCDVDD

INVT_PWM

BKOFF#

12

12

C10
220P_0402_50V7K

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

LVDS_SDA

BKOFF#

Compal Secret Data

R7

10K_0402_5%

Deciphered Date

R6

10K_0402_5%

1 2

1 2

2

LVDS_SCL <8>

LVDS_SDA <8>

BKOFF# <27>

Title

Size Doc ument Number Re v

B

Date: Sheet of

Compal Electronics, Inc.

LVDS /INVERTER

LA-4421P

15 42Monday, A pril 06, 2009

1

0.2