Compal LA-5051P Schematics

A

1 1

B

C

D

E

Compal Confidential

2 2

KBYF0 Schematics Document

AMD Griffin Processor with RS780M+SB700

(With ATI MXM/B)

3 3

2009-01-22

REV:0.3

ZZZ1

PCB

DA60000B600-*

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/11/03 2009/11/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

KBYF0 LA-5051P

146Tuesday, Fe b r u a r y 03, 2009

E

0.3

of

A

Compal Confidential

B

C

D

E

Model Name : KBYF0
File Name: LA-5051P

1 1

HDMI Conn.

page 17

LCD Conn.

Clock Generator

ICS9LPRS488B

page 16

page 15

CRT Conn.

page 18

Thermal Sensor

ADM1032

page 5

Fan Control

page 36

AMD S1G2 Processor

uPGA-638 Package

page 4,5,6,7

Hyper Transport Link
16 x 16

Memory BUS(DDRII)

Dual Channel

1.8V DDRII 667/800

200pin DDRII-SO-DIMM X2

BANK 0, 1, 2, 3

page 8,9

ATI RS780M

MXM III VGA/B

page 14

2 2

MINI Card x2

TV-Tuner WLAN

page 28

LAN(GbE)
B5784M

page 26

PCI-Express 16x

PCI-Express 1x

port 3port 1,2

BGA-528

page 10,11,12,13

A link
Express2

3.3V 48MHz

USB Conn
x4

page 29 page 16 page 29

USB port 0,1,2,6

CMOS
Camera

USB port 3 USB port 12 USB port4

Bluetooth
Conn

USB

Card Reader
RTS5159

page 25

5 in 1
Socket

page 25

ATI SB700

RJ45

page 27

SPI

RTC CKT.

3 3

page 19

BTN/B Conn.

page 31

BIOS ROM

page 21

BGA-528

page 19,20,21,22,23

LPC BUS

Power On/Off CKT.

page 32

LED/B Conn.

page 31

ENE KB926

page 30

3.3V 24MHz

S-ATA

SATA HDD
Conn.

page 24

port 0

DC/DC Int erface CKT.

page 37

Media/B Conn.

page 31

Touch Pad

page 31

Int.KBD

page 31

HD Audio

Second SATA
HDD Conn.

page 24

port1

SATA ODD
Conn.

page 24

port 2

MDC 1.5
Conn

page 32

HDA Codec
ALC272

page 33

Audio AMP
TPA6017

page 34

Phone Jack x2

page 34

Int. MIC

page 33

Digital/Analog MIC.

Mono AMP
(for Woofer)

page 34

FUN/B Conn.

page 31

4 4

Power Circuit DC/DC

page 39,40,41
42,43,44,45

A

USB/B Conn.

USB port 0,1,2,6

page 28

B

CIR

page 32

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

EC ROM

page 31

2008/11/03 2009/11/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

Block Diagrams

KBKC0 LA-5051P

0.3

of

246Tuesday, Fe b r u a r y 03, 2009

E

A

Voltage Rails

Power Pl ane Description

VIN

B+

1 1

2 2

+CPU_CORE_0

+CPU_CORE_1 Core voltage for CPU ON OFF OFF

+CPU_CORE_NB Core voltage for CPU

+0.9V 0.9V switched power rail for DDR terminator

+1.1VS

+1.2V_HT 1.25V switched power rail ON OFF OFF

+NB_CORE

+1.5VS

+1.8V

+1.8VS 1.8V switched power rail

+2.5VS

+3VALW

+3V_LAN 3.3V power rail for LAN ON ON ON

+3VS

+5VALW

+5VS

+VSB VSB always on power rail ON ON*

+RTCVCC RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise i t is OFF.

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

1.05V switched power rail

1.5V power rail for PCIE Card

1.8V power rail for CPU VDDIO and DDR

2.5V for CPU_VDDA and MXM/B

3.3V always on power rail

3.3V switched power r ail

5V always on power rail

5V switched power rail

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupt s

No PCI device

B

S1 S3 S5

N/A N/A N/A

ON OFF

ON OFF OFF

ON

ON OFF OFF

ON

ON

ON

ON

ON

ON

ON

ON

ON

N/AN/AN/A

OFF

OFF

ON

OFFOFFON1.0V~1.1V switched power rail for NB VDDC

OFF OF F

ON

OFF

OFF

OFF

OFF

OFF

ON ON *

OFF

OFF

ON*

ON

OFFON

OFF

ONON

C

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW

LOW LOW LOW LOW

SLP_S4# SLP_S5# +VALW +V +VS Clock

LOW

HIGH

LOWLOWLOW

D

HIGHHIGHHIGH

HIGH

HIGH

ON

ON

ON

ON

ON

ONONON ON

ON

OFF

ON

OFF

OFF

OFF

OFF

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7 NC

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

Vtyp

AD_BID

V

AD_BID

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

max

BOARD ID Table BTO Option Table

Board ID

0
1
2

PCB Revision

0.1

0.2

0.3 0.4 1.0*

BTO Item BOM Structure

Discrete

UMA

VGA@
UMA@

E

LOW

OFF

OFF

OFF

3
4
5
6
7

EC SM Bus1 address

3 3

Device

Smart Battery
EEPROM(24C16/02)
MXM GMT G781-1

Address Address

1010 000X b

1001 101X b

EC SM Bus2 address

Device

ADI ADM1032

CPU SB

1001 100X b0001 011X b

1001 101X b

PROJECT ID Table

Board ID

0
1
2

PROJECT

KBKC0 (SJM70)
KBYF0 (SJV70)

3

SB700
SM Bus 0 address

Device

Clock Generator
(ICS9LPRS365)

DDR DIMM0
DDR DIMM2

Minicard

4 4

Minicard

A

Address

1101 001Xb

1001 000Xb

1001 010Xb

SB700
SM Bus 1 address

Device Address

Lan

B

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4
5
6
7

2008/11/03 2009/11/03

C

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

Notes List

KBYF0 LA-5051P

346Tuesday, Fe b r u a r y 03, 2009

E

0.3

of

A

1 1

B

C

D

E

+1.2V_HT

250 mil

1

H_CADIP[0..15]<10>
H_CADIN[0..15]<10>

H_CADIP[0..15]
H_CADIN[0..15]

H_CADOP[0..15]
H_CADON[0..15]

H_CADOP[0..15] <10>
H_CADON[0..15] <10>

C535

4.7U_0805_10V4Z

2

1

C534

4.7U_0805_10V4Z

2

VLDT CAP.

1

C520

0.22U_0603_16V4Z

2

1

2

C518

0.22U_0603_16V4Z

1

C516
180P_0402_50V8J

2

1

C517
180P_0402_50V8J

2

Near CPU Socket

+1.2V_HT

2 2

3 3

H_CLKIP0<10>
H_CLKIN0<10>
H_CLKIP1<10>
H_CLKIN1<10>

H_CTLIP0<10>
H_CTLIN0<10>
H_CTLIP1<10>
H_CTLIN1<10>

VLDT=500mA

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1

H_CTLIN0
H_CTLIP1

D1
D2
D3
D4

E3
E2
E1
F1
G3
G2
G1
H1

J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5

J3

J2

J5
K5

N1
P1
P3
P4

VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3

L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15

L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1

L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1

6090022100G_B

Athlon 64 S1
Processor Socket

CONN@

JCPU1A

HT LINK

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H15

L0_CADOUT_L15

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CLKOUT_H1

L0_CLKOUT_L1
L0_CTLOUT_H0

L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1

+1.2V_HT

AE2
AE3
AE4
AE5

AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3

Y1
W1
Y4
Y3

R2
R3
T5
R5

1 2

C533 4.7U_0805_10V4Z

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

H_CTLOP0H_CTLIP0
H_CTLON0
H_CTLOP1
H_CTLON1H_CTLIN1

H_CLKOP0 <10>
H_CLKON0 <10>
H_CLKOP1 <10>
H_CLKON1 <10>

H_CTLOP0 <10>
H_CTLON0 <10>
H_CTLOP1 <10>
H_CTLON1 <10>

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/11/03 2009/11/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

AMD CPU S1G2 HT I/F

KBYF0 LA-5051P

446Tuesday, F e b r u a r y 03, 2009

E

0.3

of

A

B

C

D

E

PLACE CLOSE TO PROCESSOR

Processor DDR2 Memory Interface

WITHIN 1.5 INCH

AD10
AF10

AE10

AA16

D10
C10
B10

H16
T19

V22
U21
V19

T20
U19
U20
V20

J22
J20

N19
N20
E16
F16
Y16

P19
P20

N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19

R20
R23

J21

R19
T22
T24

DDRA_CLK0

DDRA_CLK0#
DDRA_CLK1

DDRA_CLK1#

DDRB_CLK0

DDRB_CLK0#
DDRB_CLK1

DDRB_CLK1#

VTT1

MEM:CMD/CTRL/CLK

VTT2
VTT3
VTT4

MEMZP
MEMZN

RSVD_M1
MA0_ODT0

MA0_ODT1
MA1_ODT0
MA1_ODT1

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

MA_CKE0
MA_CKE1

MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1
MA_CLK_H2
MA_CLK_L2
MA_CLK_H3
MA_CLK_L3

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MA_BANK0
MA_BANK1
MA_BANK2

MA_RAS_L
MA_CAS_L
MA_WE_L

Athlon 64 S1
Processor
Socket

CONN@

JCPU1B

1

2

1

2

1

2

1

2

VTT5
VTT6
VTT7
VTT8
VTT9

VTT_SENSE

MEMVREF

RSVD_M2

MB0_ODT0
MB0_ODT1
MB1_ODT0

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0

MB_CKE0
MB_CKE1

MB_CLK_H0

MB_CLK_L0

MB_CLK_H1

MB_CLK_L1

MB_CLK_H2

MB_CLK_L2

MB_CLK_H3

MB_CLK_L3

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8

MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

MB_BANK0
MB_BANK1
MB_BANK2

MB_RAS_L
MB_CAS_L

MB_WE_L

C244

1.5P_0402_50V9C

C178

1.5P_0402_50V9C

C509

1.5P_0402_50V9C

C447

1.5P_0402_50V9C

W10
AC10
AB10
AA10
A10

Y10
W17
B18
W26

W23
Y26

V26
W25
U22

J25
H26

P22
R22
A17
A18
AF18
AF17
R26
R25

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24

R24
U26
J26

U25
U24
U23

+0.9V+0.9V

+MCH_REF

DDRB_ODT0
DDRB_ODT1

DDRB_SCS1#

DDRB_CKE0
DDRB_CKE1

DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#DDRA_CLK1#

DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
DDRB_SMA15

DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#

DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#

@

@

DDRB_SBS0# <9>
DDRB_SBS1# <9>
DDRB_SBS2# <9>

DDRB_SRAS# <9>
DDRB_SCAS# <9>
DDRB_SWE# <9>

T2PAD

T17PAD

DDRB_ODT0 <9>
DDRB_ODT1 <9>

DDRB_SCS0# <9>
DDRB_SCS1# <9>

DDRB_CKE0 <9>
DDRB_CKE1 <9>

DDRB_CLK0 <9>
DDRB_CLK0# <9>
DDRB_CLK1 <9>
DDRB_CLK1# <9>

DDRB_SMA[15..0] <9>

1 1

2 2

R79

1K_0402_1%

R78

1K_0402_1%

+1.8V

1 2

1 2

+MCH_REF

1

C181

2

1

C189

2

0.1U_0402_16V4Z
1000P_0402_50V7K

Place them close to CPU within 1"

R343 39.2_0402_1%

1 2

+1.8V

DDRA_ODT0<8>
DDRA_ODT1<8>

DDRA_SCS0#<8>
DDRA_SCS1#<8>

DDRA_CKE0<8>
DDRA_CKE1<8>

DDRA_CLK0<8>
DDRA_CLK0#<8>
DDRA_CLK1<8>
DDRA_CLK1#<8>

3 3

4 4

DDRA_SMA[15..0]<8>

DDRA_SBS0#<8>
DDRA_SBS1#<8>
DDRA_SBS2#<8>

DDRA_SRAS#<8>
DDRA_SCAS#<8>
DDRA_SWE#<8>

1 2

R352 39.2_0402_1%

T5 PA D

DDRA_SCS0#
DDRA_SCS1# DDRB_SCS0#

DDRA_CKE0
DDRA_CKE1

DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1

MBMZP
MBMZN VTT_SENSE

@

DDRA_ODT0
DDRA_ODT1

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15

DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#

DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#

DDRB_SDQ[63..0]<9>

DDRB_SDM[7..0]<9>

DDRB_SDQS0<9>
DDRB_SDQS0#<9>
DDRB_SDQS1<9>
DDRB_SDQS1#<9>
DDRB_SDQS2<9>
DDRB_SDQS2#<9>
DDRB_SDQS3<9>
DDRB_SDQS3#<9>
DDRB_SDQS4<9>
DDRB_SDQS4#<9>
DDRB_SDQS5<9>
DDRB_SDQS5#<9>
DDRB_SDQS6<9>
DDRB_SDQS6#<9>
DDRB_SDQS7<9>
DDRB_SDQS7#<9>

DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63

DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7

DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#

AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11

AE14
AF14
AF11
AD11

AB26
AE22
AC16
AD12

AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12

C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24

Y11

A12
B16
A22
E25

C12
B12
D16
C16
A24
A23
F26
E26

JCPU1C

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

6090022100G_B

CONN@

MEM:DATA

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8

MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

MA_DQS_H0

MA_DQS_L0

MA_DQS_H1

MA_DQS_L1

MA_DQS_H2

MA_DQS_L2

MA_DQS_H3

MA_DQS_L3

MA_DQS_H4

MA_DQS_L4

MA_DQS_H5

MA_DQS_L5

MA_DQS_H6

MA_DQS_L6

MA_DQS_H7

MA_DQS_L7

Athlon 64 S1
Processor Socket

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12

E12
C15
E19
F24
AC24
Y19
AB16
Y13

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13

DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63

DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7

DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#

DDRA_SDQ[63..0] <8>

DDRA_SDM[7..0] <8>

DDRA_SDQS0 <8>
DDRA_SDQS0# <8>
DDRA_SDQS1 <8>
DDRA_SDQS1# <8>
DDRA_SDQS2 <8>
DDRA_SDQS2# <8>
DDRA_SDQS3 <8>
DDRA_SDQS3# <8>
DDRA_SDQS4 <8>
DDRA_SDQS4# <8>
DDRA_SDQS5 <8>
DDRA_SDQS5# <8>
DDRA_SDQS6 <8>
DDRA_SDQS6# <8>
DDRA_SDQS7 <8>
DDRA_SDQS7# <8>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/11/03 2009/11/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

AMD CPU S1G2 DDRII I/F

KBYF0 LA-5051P

546Tuesday, F e b r u a r y 03, 2009

E

0.3

of

A

B

C

D

E

+2.5VDDA

L33

1 2

FBM_L11_201209_300L_0805

3900P_0402_50V7K

12

R409
169_0402_1%

CPU_VDD0_FB_H

1 2

CPU_VDD0_FB_L

1 2

Close to CPU

CPU_VDD1_FB_H

1 2

CPU_VDD1_FB_L

1 2

R107

@

300_0402_5%

1 2

R105

@

300_0402_5%

1 2

R351

@

20K_0402_5%

R361

12

390_0402_5%

CPU_SID

390_0402_5%

CPU_SIC

8
7
6
5

R365

12

EC_SMB_CK2
EC_SMB_DA2

Q31 FDV301N_NL_SOT23-3@

12

G

S

G

S

Q30

CLK_CPU_BCLK<15>

CLK_CPU_BCLK#<15>

R420
300_0402_5%

1 2

LDT_RST#

1

C554

0.01U_0402_16V7K

@

2

R419
300_0402_5%

1 2

H_PWRGD

1

C553

0.01U_0402_16V7K

@

2

+1.8VS

R113
300_0402_5%

1 2

LDT_STOP#

1

C245

0.01U_0402_16V7K

@

2

1

C446

2

THERMDA_CPU
THERMDC_CPU

+2.5VS

1

+

C282
150U_D2_6.3VM

2

1 2

C531

1 2

C532 3900P_0402_50V7K

Place close to CPU wihtin 1.5"

+CPU_CORE_0

R92 10_0402_5%

R95 10_0402_5%

+CPU_CORE_1

R80 10_0402_5%

R81 10_0402_5%

+1.8VS +1.8VS

R108
300_0402_5% @

1 2

TEST25_H TEST25_L

R98
300_0402_5%@

1 2

+3VS

+1.8V

CPU_SID_SB<20>

CPU_SIC_SB<20>

Address:100_1101

1 2

R564 0_0402_5%@

+1.8V

1 2

R565 0_0402_5%@

U27

1

VDD

2
3

SCLK

D+

SDATA

ALERT#

D­THERM#4GND

ADM1032ARMZ_MSOP8

EC is PU to 5VALW

A:Need to re-Link "SGN00000200"

1 1

+1.8VS

LDT_RST#<19>

2 2

H_PWRGD<19>

LDT_STOP#<11,19>

3 3

4 4

C449 3300p for tigris

2200p change to
1000p for ADT7421

+1.8VS

+3VS

0.1U_0402_16V4Z

C449

1 2

2200P_0402_50V7K

A

VDDA=300mA

3300P_0402_50V7K

1

1

C2644.7U_0805_10V4Z

C255

2

2

<BOM Structure>

CPU_CLKIN_SC_P

CPU_CLKIN_SC_N

CPU_LDT_REQ#<11>

Address:100_1100

+1.2V_HT

C436 0.1U_0402_16V4Z

34.8K_0402_1%~N

2

2

FDV301N_NL_SOT23-3@

B

+1.8V

R82 44.2_0402_1%

1 2

R86 44.2_0402_1%

1 2

CPU_VDD0_FB_H<44>
CPU_VDD0_FB_L<44>

CPU_VDD1_FB_H<44>
CPU_VDD1_FB_L<44>

T10 PAD @

T27 PAD
T28 PAD

T21 PAD
T22 PAD
T23 PAD
T24 PAD
T25 PAD
T26 PAD

@

1 2

R360

@

12

13

D

R567 0_0402_5%@

13

D

R569 0_0402_5%@

FDV301N, the Vgs is:
min = 0.65V
Typ = 0.85V
Max = 1.5V

EC_SMB_CK2 <30>
EC_SMB_DA2 <30>

1

C261

0.22U_0603_16V4Z

2

LDT_RST#
H_PWRGD
LDT_STOP#
CPU_LDT_REQ#

CPU_SIC
CPU_SID

@

1 2

R356 1K_0402_5%

CPU_TEST23_TSTUPD

@
@

CPU_TEST21_SCANEN

@

CPU_TEST20_SCANCLK2

@

CPU_TEST24_SCANCLK1

@

CPU_TEST22_SCANSHIFTEN

@

CPU_TEST12_SCANSHIFTENB

@

CPU_TEST27_SINGLECHAIN

@

1 2

CPU_HTREF0
CPU_HTREF1

CPU_VDD0_FB_H
CPU_VDD0_FB_L

CPU_VDD1_FB_H
CPU_VDD1_FB_L

CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI

CPU_TEST18_PLLTEST1
CPU_TEST19_PLLTEST0

TEST25_H
TEST25_L

R418 0_0402_5%

CPU intern al thermal sensor

2.09V for Gate

1 2

1 2

JCPU1D

F8

VDDA1

F9

VDDA2

A9

CLKIN_H

A8

CLKIN_L

B7

RESET_L

A7

PWROK

F10

LDTSTOP_L

C6

LDTREQ_L

AF4

SIC

AF5

SID

AE6

ALERT_L

R6

HT_REF0

P6

HT_REF1

F6

VDD0_FB_H

E6

VDD0_FB_L

Y6

VDD1_FB_H

AB6

VDD1_FB_L

G10

DBRDY

AA9

TMS

AC9

TCK

AD9

TRST_L

AF9

TDI

AD7

TEST23

H10

TEST18

G9

TEST19

E9

TEST25_H

E8

TEST25_L

AB8

TEST21

AF7

TEST20

AE7

TEST24

AE8

TEST22

AC8

TEST12

AF8

TEST27

C2

TEST9

AA6

TEST6

A3

RSVD1

A5

RSVD2

B3

RSVD3

B5

RSVD4

C1

RSVD5

6090022100G_B

CPU_TEST18_PLLTEST1
CPU_TEST19_PLLTEST0

CPU_TEST22_SCANSHIFTEN

EC_SMB_DA1 <14,30,38>

EC_SMB_CK1 <14,30,38>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

KEY1
KEY2

SVC
SVD

THERMTRIP_L

PROCHOT_L

MEMHOT_L

THERMDC
THERMDA

VDDIO_FB_H
VDDIO_FB_L

VDDNB_FB_H
VDDNB_FB_L

DBREQ_L

TDO

TEST28_H

TEST28_L

TEST17
TEST16
TEST15
TEST14

TEST7

TEST10

TEST8

TEST29_H

TEST29_L

RSVD10

RSVD9
RSVD8
RSVD7
RSVD6

1 2

R531 300_0402_5% @

1 2

R532 300_0402_5% @

1 2

R533 300_0402_5% @

2008/11/03 2009/11/03

+1.8V

M11
W18

CPU_SVC

A6

CPU_SVD

A4

CPU_THERMTRIP#_R

AF6

H_PROCHOT#

AC7

CPU_MEMHOT#_1.8V

AA8

THERMDC_CPU

W7

THERMDA_CPU

W8

T30

+1.8V sense no support

T29

PAD@

W9

PAD@

Y9

CPU_VDDNB_FB_H

H6

CPU_VDDNB_FB_L

G6

CPU_DBREQ#

E10

CPU_TDO

AE9

CPU_TEST28_H_PLLCHRZ_P

J7

CPU_TEST28_L_PLLCHRZ_N

H8

CPU_TEST17_BP3

D7

CPU_TEST16_BP2

E7

CPU_TEST15_BP1

F7

CPU_TEST14_BP0

C7
C3

CPU_TEST10

K8
C4

CPU_TEST29_H_FBCLKOUT_P

C9

CPU_TEST29_L_FBCLKOUT_N

C8

H18
H19
AA7
D5
C5

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.

1 2

R364 10K_0402_5%

1 2

R358 300_0402_5%

CPU_SVC <44>
CPU_SVD <44>

@
@
@
@

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

HDT_RST#

+1.8V

R118220_0402_5%

R112220_0402_5%

R115220_0402_5%

R119220_0402_5%

12

12

12

12

@

@

@

@

Compal Secret Data

Deciphered Date

B

E

3 1

MMBT3904_NL_SOT23-3

R353

12

300_0402_5%

CPU_VDDNB_FB_H <44>
CPU_VDDNB_FB_L <44>

@
@

@
@

R129300_0402_5%

12

+1.8V

T3PAD
T4PAD

T16PAD
T7PAD
T6PAD
T9PAD

T8PAD
T15PAD

D

2

Q32

C

1 2
1 2

+1.8V

CPU_VDDNB_FB_H
CPU_VDDNB_FB_L

R335
R334

1 2

R357 300_0402_5%

H_PROCHOT#

Close to CPU

route as differential
as short as possible

testpoint under package

CPU_SVC
CPU_SVD

CPU_TEST23_TSTUPD

JP29

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_85201-1005N

@

HDT Connector

JP1

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

2423
26

SAMTEC_ASP-68200-07

@

MAINPWON

0_0402_5%@

H_THERMTRIP#CPU_THERMTRIP#_R

0_0402_5%

1 2

+CPU_CORE_NB

R101 10_0402_5%

1 2
1 2

R106 10_0402_5%

0718 AMD --> 1K ohm

1 2

R415 1K_0402_5%

1 2

R416 1K_0402_5%

CPU_TEST20_SCANCLK2
CPU_TEST21_SCANEN
CPU_TEST24_SCANCLK1

HDT_RST#

Title

Size Document Number Rev

Custom

Date: Sheet of

R537 300_0402_5%
R538 300_0402_5%
R539 300_0402_5%
R535 300_0402_5%

1 2

U8

4

Y

Compal Electronics, Inc.

AMD CPU S1G2 CTRL

MAINPWON <38,39>
H_THERMTRIP# <20>

R370

0_0402_5%

CPU_TEST10

+1.8V

@
1 2
1 2
1 2
1 2

@

R93

0_0402_5%

+3VS

5

2

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5@

3

KBYF0 LA-5051P

E

H_PROCHOT# <19>

+1.2V_HT

SB_PWRGD <20,32>

646Tuesday, F e b r u a r y 03, 2009

12

R337
0_0402_5%

@

LDT_RST#

0.3

A

VDD(+CPU_CORE) decoupling.

+CPU_CORE_0

1

C221
22U_0805_6.3V6M

2

1

2

1

+

C79
330U_X_2VM_R6M

2

C219
180P_0402_50V8J

Near CPU Socket

1

C224
22U_0805_6.3V6M

2

Under CPU Socket

1

+

1 1

+CPU_CORE_0

1

C214
22U_0805_6.3V6M

2

+CPU_CORE_0

1

C220

0.22U_0603_16V4Z

2

2 2

C80

330U_X_2VM_R6M

2

1

C225
22U_0805_6.3V6M

2

1

C217

0.01U_0402_25V4Z

2

VDDIO decoupling.

+1.8V

1

C206
22U_0805_6.3V6M

2

1

C226
22U_0805_6.3V6M

2

Under CPU Socket

1

C216

0.22U_0603_16V4Z

2

1

C230

0.22U_0603_16V4Z

2

B

+CPU_CORE_1

1

C191

180P_0402_50V8J

2

+CPU_CORE_1

1

+

2

1

C196
22U_0805_6.3V6M

2

1

2

C77

330U_X_2VM_R6M

1

2

+CPU_CORE_1

1

C195

0.22U_0603_16V4Z

2

C182
180P_0402_50V8J

C

+CPU_CORE_0

1

+

C78
330U_X_2VM_R6M

2

+CPU_CORE_NB

C200
22U_0805_6.3V6M

1

C186
22U_0805_6.3V6M

2

1

C184

0.01U_0402_25V4Z

2

1

C201
22U_0805_6.3V6M

2

1

C179
180P_0402_50V8J

2

+1.8V

+CPU_CORE_NB decoupling.

+CPU_CORE_NB

1

C198
22U_0805_6.3V6M

2

1

C207
22U_0805_6.3V6M

2

1

C223
22U_0805_6.3V6M

2

G4
H2

J9
J11
J13
J15

K6
K10
K12
K14

L4

L7

L9
L11
L13
L15

M2
M6
M8

M10

N7
N9

N11

K16

M16

P16
T16
V16

H25

J17
K18
K21
K23
K25
L17

M18
M21
M23
M25
N17

6090022100G_B

Athlon 64 S1
Processor Socket

JCPU1E

VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12

VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8

VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26

VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13

D

JCPU1F

AA4

P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2

Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18

+CPU_CORE_1

+1.8V

AA11
AA13
AA15
AA17
AA19

AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21

AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23

AB2
AB7
AB9

AD6
AD8

B4
B6
B8

B9
B11
B13
B15
B17
B19
B21
B23
B25

D6
D8

D9
D11
D13
D15
D17
D19
D21
D23
D25

E4

F2
F11
F13
F15
F17
F19
F21
F23
F25

H7

H9
H21
H23

J4

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

6090022100G_B

Athlon 64 S1
Processor Socket

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

E

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

3 3

4 4

+1.8V

1

C235

0.22U_0603_16V4Z

2

+1.8V +1.8V

1

C162

0.01U_0402_25V4Z

2

+1.8V

1

2

Between CPU Socket and DIMM

1

C165

0.22U_0603_16V4Z

2

180PF Qt'y follow the distance between
CPU socket and DIMM0. <2.5inch>

1

C164
180P_0402_50V8J

2

1

C169

4.7U_0805_10V4Z

2

C167

4.7U_0805_10V4Z

1

C234

0.22U_0603_16V4Z

2

1

C163

0.01U_0402_25V4Z

2

1

C168

4.7U_0805_10V4Z

2

1

C166

0.22U_0603_16V4Z

2

1

C237
180P_0402_50V8J

2

A: Add C165 and C176
to follow AMD Layout
review recommand for
EMI

1

C170

4.7U_0805_10V4Z

2

1

C238
180P_0402_50V8J

2

1

+

C233

220U_D2_4VM_R15

2

1

2

1

+

C218

220U_D2_4VM_R15

2

@

C: Change to NBO CAP

C239
180P_0402_50V8J

VTT decoupling.

+0.9V

1

C141

4.7U_0805_10V4Z

2

+0.9V

1

C541

4.7U_0805_10V4Z

2

1

C146

4.7U_0805_10V4Z

2

Near CPU Socket Right side.

1

C530

4.7U_0805_10V4Z

2

1

C144

0.22U_0603_16V4Z

2

1

C514

0.22U_0603_16V4Z

2

+0.9V

Near Power Supply

1

C: Change to NBO CAP

+

C281
220U_D2_4VM_R15

2

1

C148

0.22U_0603_16V4Z

2

1

C515

0.22U_0603_16V4Z

2

1

C273
22U_0805_6.3V6M

2

1

C174
1000P_0402_50V7K

2

1

C528
1000P_0402_50V7K

2

1

C173
1000P_0402_50V7K

2

1

C537
1000P_0402_50V7K

2

1

C172
180P_0402_50V8J

2

1

C540
180P_0402_50V8J

2

1

C175
180P_0402_50V8J

2

1

C543
180P_0402_50V8J

2

Near CPU Socket Left side.

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/11/03 2009/11/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

AMD CPU S1G2 PWR & GND

KBYF0 LA-5051P

E

of

746Tuesday, F e b r u a r y 03, 2009

0.3

A

B

C

D

E

+1.8V +1.8V

JDIMM1

+V_DDR_MCH_REF

DDRA_SDQS0#<5>

1 1

2 2

3 3

4 4

DDRA_SDQS0<5>

DDRA_SDQS1#<5>
DDRA_SDQS1<5>

DDRA_SDQS2#<5>
DDRA_SDQS2<5>

DDRA_CKE0<5>

DDRA_SBS2#<5>

DDRA_SBS0#<5>
DDRA_SWE#<5>

DDRA_SCAS#<5>
DDRA_SCS1#<5>

DDRA_ODT1<5>

DDRA_SDQS4#<5>
DDRA_SDQS4<5>

DDRA_SDQS6#<5>
DDRA_SDQS6<5>

ICH_SMBDATA0<9,15,20,28>
ICH_SMBCLK0<9,15,20,28>

DDRA_SDQ0
DDRA_SDQ1

DDRA_SDQS0#
DDRA_SDQS0

DDRA_SDQ2
DDRA_SDQ3

DDRA_SDQ8
DDRA_SDQ9

DDRA_SDQS1#
DDRA_SDQS1

DDRA_SDQ10
DDRA_SDQ11

DDRA_SDQ16
DDRA_SDQ17

DDRA_SDQS2#
DDRA_SDQS2

DDRA_SDQ18
DDRA_SDQ19

DDRA_SDQ24
DDRA_SDQ25 DDRA_SDQ29

DDRA_SDM3

DDRA_SDQ26
DDRA_SDQ27

DDRA_SBS2#
DDRA_SMA12

DDRA_SMA9
DDRA_SMA8

DDRA_SMA5
DDRA_SMA3
DDRA_SMA1

DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#

DDRA_SCAS#
DDRA_SCS1#

DDRA_ODT1
DDRA_SDQ32

DDRA_SDQ33
DDRA_SDQS4#

DDRA_SDQS4
DDRA_SDQ34

DDRA_SDQ35
DDRA_SDQ40

DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42

DDRA_SDQ43
DDRA_SDQ48

DDRA_SDQ49

DDRA_SDQS6#
DDRA_SDQS6

DDRA_SDQ50
DDRA_SDQ51

DDRA_SDQ56
DDRA_SDQ57

DDRA_SDM7
DDRA_SDQ58

DDRA_SDQ59
ICH_SMBDATA0

ICH_SMBCLK0

+3VS

+3VS

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

203

GND

FOX_AS0A426-M2RN-7F

CONN@

DQ12
DQ13

CK0#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

NC/A15
NC/A14

RAS#

ODT0

NC/A13

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

GND

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS
CK0

VSS

VSS

VSS

VSS
DM2

VSS

VSS

VSS

VSS

VSS
VDD

VDD

VDD

VDD
BA1

VDD

VDD
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SAO
SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204

DDRA_SDQ4
DDRA_SDQ5

DDRA_SDM0
DDRA_SDQ6

DDRA_SDQ7
DDRA_SDQ12

DDRA_SDQ13
DDRA_SDM1
DDRA_CLK0

DDRA_CLK0#
DDRA_SDQ14

DDRA_SDQ15

DDRA_SDQ20
DDRA_SDQ21

DDRA_SDM2
DDRA_SDQ22

DDRA_SDQ23
DDRA_SDQ28

DDRA_SDQS3#
DDRA_SDQS3

DDRA_SDQ30
DDRA_SDQ31

DDRA_CKE1DDRA_CKE0
DDRA_SMA15

DDRA_SMA14
DDRA_SMA11

DDRA_SMA7
DDRA_SMA6

DDRA_SMA4
DDRA_SMA2
DDRA_SMA0

DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS0#

DDRA_ODT0
DDRA_SMA13

DDRA_SDQ36
DDRA_SDQ37

DDRA_SDM4
DDRA_SDQ38

DDRA_SDQ39
DDRA_SDQ44

DDRA_SDQ45
DDRA_SDQS5#

DDRA_SDQS5
DDRA_SDQ46

DDRA_SDQ47
DDRA_SDQ52

DDRA_SDQ53
DDRA_CLK1

DDRA_CLK1#
DDRA_SDM6
DDRA_SDQ54

DDRA_SDQ55
DDRA_SDQ60

DDRA_SDQ61
DDRA_SDQS7#

DDRA_SDQS7
DDRA_SDQ62

DDRA_SDQ63

R314 10K_0402_5%

1 2

R315 10K_0402_5%

1 2

DDRA_CLK0 <5>
DDRA_CLK0# <5>

DDRA_SDQS3# <5>
DDRA_SDQS3 <5>

DDRA_CKE1 <5>

DDRA_SBS1# <5>
DDRA_SRAS# <5>
DDRA_SCS0# <5>

DDRA_ODT0 <5>

DDRA_SDQS5# <5>
DDRA_SDQS5 <5>

DDRA_CLK1 <5>
DDRA_CLK1# <5>

DDRA_SDQS7# <5>
DDRA_SDQS7 <5>

DDRA_SDQ[63..0]

DDRA_SDM[7..0]

DDRA_SMA[15..0]

+V_DDR_MCH_REF

1

C256

2

1000P_0402_50V7K

0.1U_0402_16V4Z

+1.8V

1 2

1

C257

2

1 2

1U_0402_6.3V4Z

+1.8V

0.1U_0402_16V4Z

1

C155

2

0.1U_0402_16V4Z

1

C113

2

0.1U_0402_16V4Z

DDRA_SDQ[63..0] <5>

DDRA_SDM[7..0] <5>

DDRA_SMA[15..0] <5>

R148
1K_0402_1%

R141
1K_0402_1%

1

1

C128

C151

2

2

0.1U_0402_16V4Z

+0.9V

1

1

C119

2

2

0.1U_0402_16V4Z

+V_DDR_MCH_REF

0.1U_0402_16V4Z

1

C124

2

0.1U_0402_16V4Z

1

C55

C197

2

RESERVE
+V_DDR_MCH_REF BUFFER CIRCUIT

+0.9V

DDRA_SMA6
DDRA_SMA7
DDRA_SMA11
DDRA_SMA15

DDRA_CKE0
DDRA_SBS2#
DDRA_SMA14
DDRA_CKE1

DDRA_SBS1#
DDRA_SMA0
DDRA_SMA2
DDRA_SMA4

DDRA_SMA5
DDRA_SMA8
DDRA_SMA9
DDRA_SMA12

DDRA_SBS0#
DDRA_SMA10
DDRA_SMA1
DDRA_SMA3

DDRA_SCS1#
DDRA_ODT1
DDRA_SWE#
DDRA_SCAS#

DDRA_SMA13
DDRA_ODT0
DDRA_SCS0#
DDRA_SRAS#

RP20

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

RP23

47_0804_8P4R_5%

RP17

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

RP18

47_0804_8P4R_5%

RP15

47_0804_8P4R_5%

RP9

47_0804_8P4R_5%

RP12

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

1 2

C187 0.1U_0402_16V4Z

1 2

C213 0.1U_0402_16V4Z

1 2

18

C194 0.1U_0402_16V4Z

27

1 2

36

C222 0.1U_0402_16V4Z

45

1 2

C157 0.1U_0402_16V4Z

1 2

C152 0.1U_0402_16V4Z

18

1 2

C190 0.1U_0402_16V4Z

27
36

1 2

C211 0.1U_0402_16V4Z

45

1 2

18

C180 0.1U_0402_16V4Z

27

1 2

36

C199 0.1U_0402_16V4Z

45

1 2

18

C161 0.1U_0402_16V4Z

27
36

1 2

C156 0.1U_0402_16V4Z

45

1 2

C159 0.1U_0402_16V4Z

1 2

C154 0.1U_0402_16V4Z

+1.8V

1

C413

0.1U_0402_16V4Z

2

4.7U_0805_10V4Z

A

C414

1

2

DIMM1 REV H:5.2mm (BOT)

B

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/11/03 2009/11/03

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRII SO-DIMM 0

KBYF0 LA-5051P

846Tuesday, F e b r u a r y 03, 2009

E

of

0.3

A

B

C

D

E

+1.8V +1.8V

JDIMM2

+V_DDR_MCH_REF

1 1

2 2

3 3

4 4

DDRB_SDQS0#<5>
DDRB_SDQS0<5>

DDRB_SDQS1#<5>
DDRB_SDQS1<5>

DDRB_SDQS2#<5>
DDRB_SDQS2<5>

DDRB_CKE0<5>

DDRB_SBS2#<5>

DDRB_SBS0#<5>
DDRB_SWE#<5>

DDRB_SCAS#<5>
DDRB_SCS1#<5>

DDRB_ODT1<5>

DDRB_SDQS4#<5>
DDRB_SDQS4<5>

DDRB_SDQS6#<5>
DDRB_SDQS6<5>

ICH_SMBDATA0<8,15,20,28>
ICH_SMBCLK0<8,15,20,28>

DDRB_SDQ0
DDRB_SDQ1

DDRB_SDQS0#
DDRB_SDQS0

DDRB_SDQ2
DDRB_SDQ3

DDRB_SDQ8
DDRB_SDQ9

DDRB_SDQS1#
DDRB_SDQS1

DDRB_SDQ10
DDRB_SDQ11

DDRB_SDQ16
DDRB_SDQ17

DDRB_SDQS2#
DDRB_SDQS2

DDRB_SDQ18
DDRB_SDQ19

DDRB_SDQ24
DDRB_SDQ25

DDRB_SDM3

DDRB_SDQ26 DDRB_SDQ30
DDRB_SDQ27

DDRB_CKE0

DDRB_SBS2#
DDRB_SMA12

DDRB_SMA9
DDRB_SMA8

DDRB_SMA5
DDRB_SMA3
DDRB_SMA1

DDRB_SMA10
DDRB_SBS0#
DDRB_SWE#

DDRB_SCAS#
DDRB_SCS1#

DDRB_ODT1
DDRB_SDQ32

DDRB_SDQ33
DDRB_SDQS4#

DDRB_SDQS4
DDRB_SDQ34

DDRB_SDQ35
DDRB_SDQ40

DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42

DDRB_SDQ43
DDRB_SDQ48

DDRB_SDQ49

DDRB_SDQS6#
DDRB_SDQS6

DDRB_SDQ50
DDRB_SDQ51

DDRB_SDQ56
DDRB_SDQ57

DDRB_SDM7
DDRB_SDQ58

DDRB_SDQ59
ICH_SMBDATA0

ICH_SMBCLK0

+3VS

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

FOX_AS0A426-MARG-7F

CONN@

DIMM1 REV H:9.2mm (BOT)

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

CK0

32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106

BA1

108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164

CK1

166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

SA1

202

DDRB_SDQ4
DDRB_SDQ5

DDRB_SDM0
DDRB_SDQ6

DDRB_SDQ7
DDRB_SDQ12

DDRB_SDQ13
DDRB_SDM1
DDRB_CLK0

DDRB_CLK0#
DDRB_SDQ14

DDRB_SDQ15

DDRB_SDQ20
DDRB_SDQ21

DDRB_SDM2
DDRB_SDQ22

DDRB_SDQ23
DDRB_SDQ28

DDRB_SDQ29
DDRB_SDQS3#

DDRB_SDQS3

DDRB_SDQ31
DDRB_CKE1
DDRB_SMA15

DDRB_SMA14
DDRB_SMA11

DDRB_SMA7
DDRB_SMA6

DDRB_SMA4
DDRB_SMA2
DDRB_SMA0

DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS0#

DDRB_ODT0
DDRB_SMA13

DDRB_SDQ36
DDRB_SDQ37

DDRB_SDM4
DDRB_SDQ38

DDRB_SDQ39
DDRB_SDQ44

DDRB_SDQ45
DDRB_SDQS5#

DDRB_SDQS5
DDRB_SDQ46

DDRB_SDQ47
DDRB_SDQ52

DDRB_SDQ53
DDRB_CLK1

DDRB_CLK1#
DDRB_SDM6
DDRB_SDQ54

DDRB_SDQ55
DDRB_SDQ60

DDRB_SDQ61
DDRB_SDQS7#

DDRB_SDQS7
DDRB_SDQ62

DDRB_SDQ63

R331 10K_0402_5%

1 2

R327 10K_0402_5%

1 2

DDRB_SDQS3# <5>
DDRB_SDQS3 <5>

DDRB_SDQS5# <5>
DDRB_SDQS5 <5>

DDRB_SDQS7# <5>
DDRB_SDQS7 <5>

DDRB_CLK0 <5>
DDRB_CLK0# <5>

DDRB_CKE1 <5>

DDRB_SBS1# <5>
DDRB_SRAS# <5>
DDRB_SCS0# <5>

DDRB_ODT0 <5>

DDRB_CLK1 <5>
DDRB_CLK1# <5>

+3VS

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DDRB_SDQ[63..0]
DDRB_SDM[7..0]

DDRB_SMA[15..0]

+V_DDR_MCH_REF

1

1

C202

2

2

1000P_0402_25V8J

2008/11/03 2009/11/03

DDRB_SDQ[63..0] <5>

DDRB_SDM[7..0] <5>
DDRB_SMA[15..0] <5>

+V_DDR_MCH_REF

1

C3388
22U_0805_6.3V6M

C292

@

2

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

D

DDRB_SRAS#
DDRB_SMA0
DDRB_SMA2
DDRB_SMA4

DDRB_SMA6
DDRB_SMA7
DDRB_SMA11
DDRB_SMA14

DDRB_CKE0
DDRB_SBS2#
DDRB_SMA15
DDRB_CKE1

DDRB_SMA8
DDRB_SMA5
DDRB_SMA12
DDRB_SMA9

DDRB_SBS0#
DDRB_SMA10
DDRB_SMA3
DDRB_SMA1

DDRB_ODT1
DDRB_SCS1#
DDRB_SWE#
DDRB_SCAS#

DDRB_SMA13
DDRB_ODT0
DDRB_SCS0#
DDRB_SBS1#

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

RP19

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

RP22

18
27
36
45

47_0804_8P4R_5%

RP21

18
27
36

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

45

RP16

18
27
36
45

RP10

18
27
36
45

RP11

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

Title

Size Document Number Rev

Custom

Date: Sheet

12

C185 0.1U_0402_16V4Z

1 2

C176 0.1U_0402_16V4Z

12

C188 0.1U_0402_16V4Z

1 2

C193 0.1U_0402_16V4Z

12

C203 0.1U_0402_16V4Z

1 2

C215 0.1U_0402_16V4Z

12

C205 0.1U_0402_16V4Z

1 2

C210 0.1U_0402_16V4Z

12

C204 0.1U_0402_16V4Z

1 2

C209 0.1U_0402_16V4Z

12

C171 0.1U_0402_16V4Z

1 2

C153 0.1U_0402_16V4Z

12

C158 0.1U_0402_16V4Z

1 2

C160 0.1U_0402_16V4Z

Compal Electronics, Inc.

DDRII SO-DIMM 1

KBYF0 LA-5051P

+0.9V

RP14

+1.8V

E

0.3

of

946Tuesday, F e b r u a r y 03, 2009

A

B

C

D

E

PCIE_GTX_C_MRX_P[0..15]<14>
PCIE_GTX_C_MRX_N[0..15]<14>

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2

1 1

2 2

PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3 PCIE_GTX_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6 PCIE_GTX_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7 PCIE_GTX_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9 PCIE_GTX_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11 PCIE_GTX_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14 PCIE_GTX_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15 PCIE_GTX_MRX_P15
PCIE_GTX_C_MRX_N15

C681 0.1U_0402_16V7K VGA@

1 2

C683 0.1U_0402_16V7K VGA@

1 2

C685 0.1U_0402_16V7K VGA@

1 2

C687 0.1U_0402_16V7K VGA@

1 2

C689 0.1U_0402_16V7K VGA@

1 2

C691 0.1U_0402_16V7K VGA@

1 2

C693 0.1U_0402_16V7K VGA@

1 2

C695 0.1U_0402_16V7K VGA@

1 2

C697 0.1U_0402_16V7K VGA@

1 2

C699 0.1U_0402_16V7K VGA@

1 2

C701 0.1U_0402_16V7K VGA@

1 2

C703 0.1U_0402_16V7K VGA@

1 2

C705 0.1U_0402_16V7K VGA@

1 2

C707 0.1U_0402_16V7K VGA@

1 2

C709 0.1U_0402_16V7K VGA@

1 2

C711 0.1U_0402_16V7K VGA@

1 2

C680 0.1U_0402_16V7K VGA@

1 2

C682 0.1U_0402_16V7K VGA@

1 2

C684 0.1U_0402_16V7K VGA@

1 2

C686 0.1U_0402_16V7K VGA@

1 2

C688 0.1U_0402_16V7K VGA@

1 2

C690 0.1U_0402_16V7K VGA@

1 2

C692 0.1U_0402_16V7K VGA@

1 2

C694 0.1U_0402_16V7K VGA@

1 2

C696 0.1U_0402_16V7K VGA@

1 2

C698 0.1U_0402_16V7K VGA@

1 2

C700 0.1U_0402_16V7K VGA@

1 2

C702 0.1U_0402_16V7K VGA@

1 2

C704 0.1U_0402_16V7K VGA@

1 2

C706 0.1U_0402_16V7K VGA@

1 2

C708 0.1U_0402_16V7K VGA@

1 2

C710 0.1U_0402_16V7K VGA@

1 2

PCIE_PTX_C_IRX_P1<28>
PCIE_PTX_C_IRX_N1<28>
PCIE_PTX_C_IRX_P2<28>
PCIE_PTX_C_IRX_N2<28>
PCIE_PTX_C_IRX_P3<26>
PCIE_PTX_C_IRX_N3<26>

SB_RX0P<19>
SB_RX0N<19>
SB_RX1P<19>
SB_RX1N<19>
SB_RX2P<19>
SB_RX2N<19>
SB_RX3P<19>
SB_RX3N<19>

PCIE_GTX_MRX_P0
PCIE_GTX_MRX_N0
PCIE_GTX_MRX_P1
PCIE_GTX_MRX_N1
PCIE_GTX_MRX_P2
PCIE_GTX_MRX_N2
PCIE_GTX_MRX_P3

PCIE_GTX_MRX_P4
PCIE_GTX_MRX_N4
PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N5

PCIE_GTX_MRX_N6
PCIE_GTX_MRX_P7

PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N8
PCIE_GTX_MRX_P9

PCIE_GTX_MRX_P10
PCIE_GTX_MRX_N10
PCIE_GTX_MRX_P11

PCIE_GTX_MRX_P12
PCIE_GTX_MRX_N12
PCIE_GTX_MRX_P13
PCIE_GTX_MRX_N13

PCIE_GTX_MRX_N14
PCIE_GTX_MRX_N15

PCIE_PTX_C_IRX_P1
PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P2
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P3
PCIE_PTX_C_IRX_N3

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

RS780M Display Port Support (muxed on GFX)

DP0

3 3

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P3 HDMI_CLK+_UMA
PCIE_MTX_GRX_N3

4 4

DP1

C897 0.1U_0402_10V7KUMA@

1 2

C898 0.1U_0402_10V7KUMA@

1 2

C899 0.1U_0402_10V7KUMA@

1 2

C900 0.1U_0402_10V7KUMA@

1 2

C901 0.1U_0402_10V7KUMA@

1 2

C902 0.1U_0402_10V7KUMA@

1 2

C903 0.1U_0402_10V7KUMA@

1 2

C904 0.1U_0402_10V7KUMA@

1 2

GFX_TX0,TX1,TX2 and TX3
AUX0 and HPD0

GFX_TX4,TX5,TX6 and TX7
AUX1 and HPD1

HDMI_TX2+_UMA
HDMI_TX2-_UMA
HDMI_TX1+_UMA
HDMI_TX1-_UMA
HDMI_TX0+_UMA
HDMI_TX0-_UMA

HDMI_CLK-_UMA

U25B

D4

GFX_RX0P

C4

GFX_RX0N

A3

GFX_RX1P

B3

GFX_RX1N

C2

GFX_RX2P

C1

GFX_RX2N

E5

GFX_RX3P

F5

GFX_RX3N

G5

GFX_RX4P

G6

GFX_RX4N

H5

GFX_RX5P

H6

GFX_RX5N

J6

GFX_RX6P

J5

GFX_RX6N

J7

GFX_RX7P

J8

GFX_RX7N

L5

GFX_RX8P

L6

GFX_RX8N

M8

GFX_RX9P

L8

GFX_RX9N

P7

GFX_RX10P

M7

GFX_RX10N

P5

GFX_RX11P

M5

GFX_RX11N

R8

GFX_RX12P

P8

GFX_RX12N

R6

GFX_RX13P

R5

GFX_RX13N

P4

GFX_RX14P

P3

GFX_RX14N

T4

GFX_RX15P

T3

GFX_RX15N

AE3

GPP_RX0P

AD4

GPP_RX0N

AE2

GPP_RX1P

AD3

GPP_RX1N

AD1

GPP_RX2P

AD2

GPP_RX2N

V5

GPP_RX3P

W6

GPP_RX3N

U5

GPP_RX4P

U6

GPP_RX4N

U8

GPP_RX5P

U7

GPP_RX5N

AA8

SB_RX0P

Y8

SB_RX0N

AA7

SB_RX1P

Y7

SB_RX1N

AA5

SB_RX2P

AA6

SB_RX2N

W5

SB_RX3P

Y5

SB_RX3N

RS780M_FCBGA528

HDMI_TX2+_UMA <17>
HDMI_TX2-_UMA <17>
HDMI_TX1+_UMA <17>
HDMI_TX1-_UMA <17>
HDMI_TX0+_UMA <17>
HDMI_TX0-_UMA <17>
HDMI_CLK+_UMA <17>
HDMI_CLK-_UMA <17>

PART 2 OF 6

GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F SB

PCE_CALRP(PCE_BCALRP)

PCE_CALRN(PCE_BCALRN)

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]

A5

PCIE_MTX_GRX_N0

B5

PCIE_MTX_GRX_P1

A4
B4

PCIE_MTX_GRX_P2

C3

PCIE_MTX_GRX_N2

B2

PCIE_MTX_GRX_P3

D1
D2

PCIE_MTX_GRX_P4

E2

PCIE_MTX_GRX_N4

E1

PCIE_MTX_GRX_P5

F4
F3

PCIE_MTX_GRX_P6

F1
F2

PCIE_MTX_GRX_P7

H4
H3

PCIE_MTX_GRX_P8

H1
H2

PCIE_MTX_GRX_P9

J2

PCIE_MTX_GRX_N9

J1
K4

PCIE_MTX_GRX_N10

K3

PCIE_MTX_GRX_P11

K1

PCIE_MTX_GRX_N11

K2

PCIE_MTX_GRX_P12

M4

PCIE_MTX_GRX_N12

M3

PCIE_MTX_GRX_P13

M1
M2

PCIE_MTX_GRX_P14

N2

PCIE_MTX_GRX_N14

N1

PCIE_MTX_GRX_P15

P1
P2

AC1
AC2

PCIE_ITX_PRX_P1

AB4

PCIE_ITX_PRX_N1

AB3

PCIE_ITX_PRX_P2

AA2

PCIE_ITX_PRX_N2

AA1

PCIE_ITX_PRX_P3

Y1

PCIE_ITX_PRX_N3

Y2
Y4
Y3
V1
V2

SB_TX0P_C

AD7

SB_TX0N_C

AE7

SB_TX1P_C

AE6

SB_TX1N_C

AD6

SB_TX2P_C

AB6

SB_TX2N_C

AC6

SB_TX3P_C

AD5

SB_TX3N_C

AE5
AC8

AB8

C

C451 0.1U_0402_16V7K VGA@

C450 0.1U_0402_16V7K VGA@

1 2

C466 0.1U_0402_16V7K VGA@

1 2

C452 0.1U_0402_16V7K VGA@

1 2

C468 0.1U_0402_16V7K VGA@

1 2

C454 0.1U_0402_16V7KVGA@

1 2

C470 0.1U_0402_16V7KVGA@

1 2

C456 0.1U_0402_16V7KVGA@

1 2

C472 0.1U_0402_16V7KVGA@

1 2

C458 0.1U_0402_16V7KVGA@

1 2

C474 0.1U_0402_16V7KVGA@

1 2

C460 0.1U_0402_16V7KVGA@

1 2

C476 0.1U_0402_16V7KVGA@

1 2

C462 0.1U_0402_16V7KVGA@

1 2

C478 0.1U_0402_16V7KVGA@

1 2

C464 0.1U_0402_16V7KVGA@

1 2

C480 0.1U_0402_16V7KVGA@

1 2

C31 0.1U_0402_16V7K

1 2

C30 0.1U_0402_16V7K

1 2

C21 0.1U_0402_16V7K

1 2

C20 0.1U_0402_16V7K

1 2

C23 0.1U_0402_16V7K

1 2

C22 0.1U_0402_16V7K

1 2

C271 0.1U_0402_16V7K

1 2

C268 0.1U_0402_16V7K

1 2

C290 0.1U_0402_16V7K

1 2

C295 0.1U_0402_16V7K

1 2

C263 0.1U_0402_16V7K

1 2

C265 0.1U_0402_16V7K

1 2

C262 0.1U_0402_16V7K

1 2

C260 0.1U_0402_16V7K

1 2

R33 1.27K_0402_1%
R31 2K_0402_1%

1 2
1 2

0718 Place within 1"
layout 1:2

2008/11/03 2009/11/03

Compal Secret Data

C467 0.1U_0402_16V7K VGA@
C453 0.1U_0402_16V7K VGA@
C469 0.1U_0402_16V7K VGA@
C455 0.1U_0402_16V7KVGA@
C471 0.1U_0402_16V7KVGA@
C457 0.1U_0402_16V7KVGA@
C473 0.1U_0402_16V7KVGA@
C459 0.1U_0402_16V7KVGA@
C475 0.1U_0402_16V7KVGA@
C461 0.1U_0402_16V7KVGA@
C477 0.1U_0402_16V7KVGA@
C463 0.1U_0402_16V7KVGA@
C479 0.1U_0402_16V7KVGA@
C465 0.1U_0402_16V7KVGA@
C481 0.1U_0402_16V7KVGA@

+1.1VS

H_CLKOP0<4>
H_CLKON0<4>
H_CLKOP1<4>
H_CLKON1<4>

H_CTLOP0<4>
H_CTLON0<4>
H_CTLOP1<4>
H_CTLON1<4>

Deciphered Date

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

R75

1 2

301_0402_1%

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7

H_CADOP8
H_CADON8
H_CADOP9
H_CADON9

H_CADOP10

H_CADON10

H_CADOP11

H_CADON11

H_CADOP12

H_CADON12

H_CADOP13

H_CADON13

H_CADOP14

H_CADON14

H_CADOP15

H_CADON15
H_CLKOP0

H_CLKON0
H_CLKOP1
H_CLKON1

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1

PCIE_ITX_C_PRX_P1 <28>
PCIE_ITX_C_PRX_N1 <28>
PCIE_ITX_C_PRX_P2 <28>
PCIE_ITX_C_PRX_N2 <28>
PCIE_ITX_C_PRX_P3 <26>
PCIE_ITX_C_PRX_N3 <26>

SB_TX0P <19>
SB_TX0N <19>
SB_TX1P <19>
SB_TX1N <19>
SB_TX2P <19>
SB_TX2N <19>
SB_TX3P <19>
SB_TX3N <19>

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

AC24
AC25
AB25
AB24
AA24
AA25

Y22

Y23
W21
W20

V21

V20

U20

U21

U19

U18

T22

T23

AB23
AA22

M22
M23

R21

R20

C23

A24

D

PCIE_MTX_C_GRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P0PCIE_MTX_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1PCIE_MTX_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3PCIE_MTX_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5PCIE_MTX_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6PCIE_MTX_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7PCIE_MTX_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8PCIE_MTX_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10PCIE_MTX_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13PCIE_MTX_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15PCIE_MTX_GRX_N15

TV Tuner
WLAN
GLAN

U25A

HT_RXCAD0P

PART 1 OF 6

HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_RXCALP
HT_RXCALN

RS780M_FCBGA528

PCIE_MTX_C_GRX_P[0..15] <14>
PCIE_MTX_C_GRX_N[0..15] <14>

H_CADIP0

H_CADIN0

H_CADIP1

H_CADIN1

H_CADIP2

H_CADIN2

H_CADIP3

H_CADIN3

H_CADIP4

H_CADIN4

H_CADIP5

H_CADIN5

H_CADIP6

H_CADIN6

H_CADIP7

H_CADIN7

H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11

H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

E

H_CADOP[0..15]
H_CADON[0..15]

H_CADIP[0..15] <4>
H_CADIN[0..15] <4>

R76

1 2

301_0402_1%

10 46Tuesday, Fe b r u a r y 03, 2009

H_CLKIP0 <4>
H_CLKIN0 <4>
H_CLKIP1 <4>
H_CLKIN1 <4>

H_CTLIP0 <4>
H_CTLIN0 <4>
H_CTLIP1 <4>
H_CTLIN1 <4>

of

H_CADOP[0..15]<4>
H_CADON[0..15]<4>

H_CADIP[0..15]
H_CADIN[0..15]

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P

HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N

HYPER TRANSPORT CPU I/F

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

Title

Size Document Number Rev

Custom

Date: Sheet

D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22

F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18

H24
H25
L21
L20

M24
M25
P19
R18

B24

HT_TXCALP

B25

HT_TXCALN

0718 Place within 1"
layout 1:2

Compal Electronics, Inc.

RS780-HT/PCIE

KBYF0 LA-5051P

0.3

A

B

C

D

E

140

For RS780M A13

1 2

R64 133_0402_1%

1 2

+NB_HTPVDD+1.8VS

+1.1VS

GMCH_LCD_CLK
GMCH_LCD_DATA

GMCH_DDC_CLK
GMCH_DDC_DATA

1 2

R511 4.7K_0402_5%

1 2

R512 4.7K_0402_5%

+1.8VS

G

2

S

Q29

@

R332

1 2

0_0402_5%

LDT_STOP#<6,19>

R63 150_0402_1%

1 2

R71 150_0402_1%

+1.1VS

13

D

FDV301N_NL_SOT23-3

1 1

L10

1 2

MBK2012221YZF 0805

2.2U_0603_6.3V4Z

+1.8VS

1 2

MBK2012221YZF 0805

2.2U_0603_6.3V4Z

2 2

+1.8VS

1 2

MBK2012221YZF 0805

2.2U_0603_6.3V4Z

+3VS

1 2

R325 4.7K_0402_5%

1 2

+5VS

+3VS

1 2

R846 0_0402_5% @

NB_PWRGD<20>

R329 4.7K_0402_5%

R318 4.7K_0402_5%@
R323 4.7K_0402_5%@

1 2

R847 0_0402_5%

1 2
1 2

3 3

4 4

L17

L6

C84

+VDDA18HTPLL

C118

C69

A

1

2

1

2

+VDDA18PCIEPLL

1

2

GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B

+1.8VS

1 2

2.2U_0603_6.3V4Z

1 2

MBK2012221YZF 0805

2.2U_0603_6.3V4Z

1 2

R40

4.7K_0402_5%

L41

FBM-L11-201209-300LMA30T_0805

+NB_PLLVDD

1

C433

2

1 2

R34

4.7K_0402_5%

Strap pin

POWER_SEL<41>

GMCH_CRT_CLK
GMCH_CRT_DATA

+1.8VS +3VS+1.8VS

R333
300_0402_5%

1 2

NB_PWRGD_R

S

Q28

1 2

+1.8VS

G

2

D

@

R570

0_0402_5%

13

+3VS

@

1 2

FDV301N_NL_SOT23-3

+3VS

+1.8VS

FBM-L11-201209-300LMA30T_0805

L12

C99

GMCH_CRT_HSYNC<13,18>
GMCH_CRT_VSYNC<13,18>

PLT_RST#<13,19,26,28,30>

+3VS

12

R530

@

2.2K_0402_5%

R324

4.7K_0402_5%

NB_LDTSTOP#

B

L7

1 2

FBM-L11-201209-300LMA30T_0805

22U_0805_6.3V6M

L14

1 2

C106

2.2U_0603_6.3V4Z

+AVDDQ

1

2

GMCH_CRT_R<18>
GMCH_CRT_G<18>
GMCH_CRT_B<18>

GMCH_CRT_CLK<18>
GMCH_CRT_DATA<18>

R59 715_0402_1%

CLK_NBHT<15>
CLK_NBHT#<15>

NB_OSC_14.318M<15>

CLK_NBGFX<15>
CLK_NBGFX#<15>

CLK_SBLINK_BCLK<15>
CLK_SBLINK_BCLK#<15>

GMCH_LCD_CLK<16>

GMCH_LCD_DATA<16>

GMCH_DDC_DATA<17>

GMCH_DDC_CLK<17>

POWER_SEL

1 2

+NB_PLLVDD

+NB_HTPVDD

+VDDA18HTPLL

+VDDA18PCIEPLL

R319

1 2

0_0402_5%

R41 10K_0402_5%

AUX_CAL<13>

Strap pin

R540 1k for RS880M

CPU_LDT_REQ#<6>

ALLOW_LDTSTOP<19>

+AVDD1

1

C65

2

+AVDD2

1

2

GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B

GMCH_CRT_HSYNC
GMCH_CRT_VSYNC
GMCH_CRT_CLK
GMCH_CRT_DATA

DAC_RSET

+NB_PLLVDD
+NB_HTPVDD

NB_RESET#PLT_RST#
NB_PWRGD_R
NB_LDTSTOP#

NB_ALLOW_LDTSTOP

CLK_NBHT
CLK_NBHT#

NB_OSC_14.318M

CLK_NBGFX
CLK_NBGFX#

CLK_SBLINK_BCLK
CLK_SBLINK_BCLK#

GMCH_LCD_CLK
GMCH_LCD_DATA
GMCH_DDC_DATA
GMCH_DDC_CLK

12

AUX_CAL

AVDD=100mA

1

C75

22U_0805_6.3V6M

2

U25C

F12

AVDD1(NC)

E12

AVDD2(NC)

F14

AVDDDI(NC)

G15

AVSSDI(NC)

H15

AVDDQ(NC)

H14

AVSSQ(NC)

E17

C_Pr(DFT_GPIO5)

F17

Y(DFT_GPIO2)

F15

COMP_Pb(DFT_GPIO4)

G18

RED(DFT_GPIO0)

G17

REDb(NC)

E18

GREEN(DFT_GPIO1)

F18

GREENb(NC)

E19

BLUE(DFT_GPIO3)

F19

BLUEb(NC)

A11

DAC_HSYNC(PWM_GPIO4)

B11

DAC_VSYNC(PWM_GPIO6)

F8

DAC_SCL(PCE_RCALRN)

E8

DAC_SDA(PCE_TCALRN)

G14

DAC_RSET(PWM_GPIO1)

A12

PLLVDD(NC)

D14

PLLVDD18(NC)

B12

PLLVSS(NC)

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESETb

A10

POWERGOOD

C10

LDTSTOPb

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN(OSCIN)

F11

REFCLK_N(PWM_GPIO3)

T2

GFX_REFCLKP

T1

GFX_REFCLKN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP(SB_REFCLKP)

V3

GPPSB_REFCLKN(SB_REFCLKN)

B9

I2C_CLK

A9

I2C_DATA

B8

DDC_DATA0/AUX0N(NC)

A8

DDC_CLK0/AUX0P(NC)

B7

DDC_CLK1/AUX1P(NC)

A7

DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

AUX_CAL(NC)

RS780M_FCBGA528

R540

0_0402_5%

1 2

R414

300_0402_5%

1 2

Q56

1 2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

PART 3 OF 6

TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)

TXOUT_U3P(PCIE_RESET_GPIO5)

CRT/TVOUT

TXCLK_UP(PCIE_RESET_GPIO4)

TXCLK_UN(PCIE_RESET_GPIO1)

LVTM

PM

CLOCKs PLL PWR

MIS.

+1.8VS

R338

@

300_0402_5%

@

G

1 2

2

S

@

R571

0_0402_5%

13

D

1 2

FDV301N_NL_SOT23-3

2008/11/03 2009/11/03

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)

TXOUT_L2N(DBG_GPIO0)

TXOUT_L3P(NC)

TXOUT_L3N(DBG_GPIO2)

TXOUT_U0P(NC)
TXOUT_U0N(NC)

TXOUT_U2P(NC)
TXOUT_U2N(NC)

TXOUT_U3N(NC)

TXCLK_LP(DBG_GPIO1)

TXCLK_LN(DBG_GPIO3)

VDDLTP18(NC)
VSSLTP18(NC)

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

LVDS_DIGON(PCE_TCALRP)

LVDS_BLON(PCE_RCALRP)

LVDS_ENA_BL(PWM_GPIO2)

TMDS_HPD(NC)

SUS_STAT#(PWM_GPIO5)

R534

4.7K_0402_5%

NB_ALLOW_LDTSTOP

HPD(NC)

THERMALDIODE_P
THERMALDIODE_N

TESTMODE

Compal Secret Data

Deciphered Date

A22
B22
A21
B21
B20
A20
A19
B19

B18
A18
A17
B17
D20
D21
D18
D19

B16
A16
D16
D17

A13
B13

A15
B15
A14
B14

C14
D15
C16
C18
C20
E20
C22

E9
F7
G12

1.27K_0402_1%

UMA@

D9
D10

D12
AE8

AD8
D13

GMCH_TXOUT0+
GMCH_TXOUT0­GMCH_TXOUT1+
GMCH_TXOUT1­GMCH_TXOUT2+
GMCH_TXOUT2-

GMCH_TZOUT0+
GMCH_TZOUT0­GMCH_TZOUT1+
GMCH_TZOUT1­GMCH_TZOUT2+
GMCH_TZOUT2-

GMCH_TXCLK+
GMCH_TXCLK­GMCH_TZCLK+
GMCH_TZCLK-

+VDDLTP18

+VDDLT18

R328

1 2

R26 10K_0402_5%@

1 2

R316 0_0402_5%

1 2

1 2

R359

1.8K_0402_5%

D

R313

1.27K_0402_1%

UMA@

1 2

SUS_STAT#
SUS_STAT_R#
NB_THERMAL_DA
NB_THERMAL_DC

GMCH_TXOUT0+ <16>
GMCH_TXOUT0- <16>
GMCH_TXOUT1+ <16>
GMCH_TXOUT1- <16>
GMCH_TXOUT2+ <16>
GMCH_TXOUT2- <16>

GMCH_TZOUT0+ <16>
GMCH_TZOUT0- <16>
GMCH_TZOUT1+ <16>
GMCH_TZOUT1- <16>
GMCH_TZOUT2+ <16>
GMCH_TZOUT2- <16>

GMCH_TXCLK+ <16>
GMCH_TXCLK- <16>
GMCH_TZCLK+ <16>
GMCH_TZCLK- <16>

1 2

R347 0_0402_5%@

R350 0_0402_5%@

UMA_HPD

+VDDLTP18

+VDDLT18

0.1U_0402_16V4Z

R330 0_0402_5%

UMA@

1 2
1 2

1 2

UMA_HPD <17>

SUS_STAT# <20>
SUS_STAT_R# <13>
NB_THERMAL_DA <21>
NB_THERMAL_DC <21>

Title

Size Document Number Rev

Custom
Date: Sheet

Compal Electronics, Inc.

RS780 VEDIO/CLK GEN

1

2

1

C442

2

GMCH_ENVDD
ENBKL

R317 0_0402_5%UMA@

KBYF0 LA-5051P

L42

1 2

MBC1608121YZF_0603
C439

2.2U_0603_6.3V4Z

L46

1 2

MBC1608121YZF_0603

1

C443

4.7U_0805_10V4Z

2

UMA_PNL_PWM <16>

Strap pin
NB temp to SB

E

+1.8VS

+1.8VS

GMCH_ENVDD <16>
ENBKL <14,30>
BKOFF# <16,30>

of

11 46Tuesday, Feb ru ar y 03, 2009

0.3

A

1 1

2 2

+1.8VS

3 3

4 4

+1.1VS

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

+1.2V_HT

FBMA-L11-201209-221LMA30T_0805

L21

FBMA-L11-201209-221LMA30T_0805

1

C72
22U_0805_6.3V6M

2

2A

L25

12

C33

L9

22U_0805_6.3V6M

L16

12

22U_0805_6.3V6M

330U_D2E_2.5VM

1

+

2

12

C88

0.1U_0402_16V4Z

12

1

C109

2

22U_0805_6.3V6M

0.1U_0402_16V4Z

2A

1

C131

C150

2

0.1U_0402_16V4Z

2A

1

C130

2

22U_0805_6.3V6M

2A

0.1U_0402_16V4Z

1

1

C92

2

2

22U_0805_6.3V6M

1

C116

C117

2

0.1U_0402_16V4Z

1

1

C127

2

2

0.1U_0402_16V4Z

1

C134

C123

2

0.1U_0402_16V4Z

1

C87

C91

2

0.1U_0402_16V4Z

+1.8VS

C432

1U_0402_6.3V4Z

0.1U_0402_16V4Z

1

1

C121

2

2

0.1U_0402_16V4Z

1

C139

C147

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C136

2

2

0.1U_0402_16V4Z

1

1

C93

2

2

1

2

C114

0.1U_0402_16V4Z

+VDDHTRX

1

2

C135

0.1U_0402_16V4Z

C89

0.1U_0402_16V4Z

+VDDHT

0.68A

1

2

0.68A

+VDDHTTX

1

2

+VDDA18PCIE

0.6A

1

2

0.64A

B

K16
M16

P16
R16
T16

H18
G19
F20
E21
D22
B23
A23

AE25
AD24
AC23
AB22
AA21

Y20

W19

V18
U17
T17
R17
P17

M17

P10
K10

M10

T10
R10

AA9
AB9
AD9
AE9
U10

AE11
AD11

1

C431
1U_0402_6.3V4Z

2

@

U25E

J17

VDDHT_1
VDDHT_2

L16

VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

J10

VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4

L10

VDDA18PCIE_5

W9

VDDA18PCIE_6

H9

VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9

Y9

VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15

F9

VDD18_1

G9

VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)

RS780M_FCBGA528

PART 5/6

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8

VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12

POWER

VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

VDD33_1(NC)
VDD33_2(NC)

C

shape add

VDDA_12=2.5A

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

AE10
AA11
Y11
AD10
AB10
AC10

H11
H12

+VDDA11PCIE

1.1A

7.6A

C1010.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C95

1 2

L5 0_0805_5%

C35
C34

C74 1U_0402_6.3V4Z
C85 1U_0402_6.3V4Z
C81 1U_0402_6.3V4Z
C86 1U_0402_6.3V4Z

C73 0.1U_0402_16V4Z
C82 0.1U_0402_16V4Z

+1.1VS

C940.1U_0402_16V4Z

1

1

1

1

C1120.1U_0402_16V4Z

C1040.1U_0402_16V4Z

C1070.1U_0402_16V4Z

2

2

2

2

1

1

C96

2

2

22U_0805_6.3V6M
22U_0805_6.3V6M

1 2
1 2
1 2
1 2

1 2
1 2

1 2

L3 0_0805_5%

1 2

L4 0_0805_5%

VDD_CORE=5A

C970.1U_0402_16V4Z

1

1

1

1

C1030.1U_0402_16V4Z

C1020.1U_0402_16V4Z

C1100.1U_0402_16V4Z

2

2

2

2

+3VS+1.8VS

0.1U_0402_16V4Z

D

U25F

A25

VSSAHT1

D23

VSSAHT2

E22

VSSAHT3

G22

VSSAHT4

G24

VSSAHT5

G25

VSSAHT6

H19

VSSAHT7

J22

VSSAHT8

L17

VSSAHT9

L22

VSSAHT10

L24

VSSAHT11

+1.1VS

+NB_CORE

C32 330U_D2E_2.5VM

330U_D2E_2.5VM

1

1

C3822U_0805_6.3V6M

C3622U_0805_6.3V6M

C29

1

1

2

+

+

2

2

2

L25

VSSAHT12

M20

VSSAHT13

N22

VSSAHT14

P20

VSSAHT15

R19

VSSAHT16

R22

VSSAHT17

R24

VSSAHT18

R25

VSSAHT19

H20

VSSAHT20

U22

VSSAHT21

V19

VSSAHT22

W22

VSSAHT23

W24

VSSAHT24

W25

VSSAHT25

Y21

VSSAHT26

AD25

VSSAHT27

L12

VSS11

M14

VSS12

N13

VSS13

P12

VSS14

P15

VSS15

R11

VSS16

R14

VSS17

T12

VSS18

U14

VSS19

U11

VSS20

U15

VSS21

V12

VSS22

W11

VSS23

W15

VSS24

AC12

VSS25

AA14

VSS26

Y18

VSS27

AB11

VSS28

AB15

VSS29

AB17

VSS30

AB19

VSS31

AE20

VSS32

AB21

VSS33

K11

VSS34

RS780M_FCBGA528

U25D

AB12

MEM_A0(NC)

AE16

MEM_A1(NC)

V11

MEM_A2(NC)

AE15

MEM_A3(NC)

AA12

MEM_A4(NC)

AB16

MEM_A5(NC)

AB14

MEM_A6(NC)

AD14

MEM_A7(NC)

AD13

MEM_A8(NC)

AD15

MEM_A9(NC)

AC16

MEM_A10(NC)

AE13

MEM_A11(NC)

AC14

MEM_A12(NC)

Y14

MEM_A13(NC)

AD16

MEM_BA0(NC)

AE17

MEM_BA1(NC)

AD17

MEM_BA2(NC)

W12

MEM_RASb(NC)

Y12

MEM_CASb(NC)

AD18

MEM_WEb(NC)

AB13

MEM_CSb(NC)

AB18

MEM_CKE(NC)

V14

MEM_ODT(NC)

V15

MEM_CKP(NC)

W14

MEM_CKN(NC)

AE12

MEM_COMPP(NC)

AD12

MEM_COMPN(NC)

RS780M_FCBGA528

VSSAPCIE1

PART 6/6

VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8

VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30

GROUND

VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)

MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)

MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)

MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)

MEM_DQ13/DVO_D9(NC)

MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)

MEM_DM1/DVO_D8(NC)

SBD_MEM/DVO_I/F

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

VSS10

MEM_DQ4(NC)

MEM_DQ12(NC)

MEM_DQS1P(NC)
MEM_DQS1N(NC)

MEM_DM0(NC)

IOPLLVDD18(NC)

IOPLLVDD(NC)

IOPLLVSS(NC)

MEM_VREF(NC)

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

E

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

Y17
W18
AD20
AE21

W17
AE19

AE23
AE24

AD23
AE18

+1.8VS

+1.1VS

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/11/03 2009/11/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

RS780 PWR/GND

KBYF0 LA-5051P

12 46Tuesday, Fe b r u a r y 03, 2009

E

0.3

of

A

B

C

D

E

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ ENABLEb

GMCH_CRT_VSYNC<11,18>

1 1

12

R46 3K_0402_5%

12

R45 3K_0402_5%@

+3VS

Enables the Test Debug Bus using GPIO. (VSYNC)
1 : Disable (RS780)
0 : Enable (Rs780)

DFT_GPIO1: LOAD_EEPROM_STRAPS

AUX_CAL<11>

RS780 DFT_GPIO1

2 2

1 2

R320 150_0402_1%@

D17
CH751H-40_SC76@

2 1

PLT_RST# <11,19,26,28,30>SUS_STAT_R#<11>

Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

RS780 use HSYNC to enable SIDE PORT

RS780 use HSYNC to enable SIDE PORT

GMCH_CRT_HSYNC<11,18>

12

R340 3K_0402_5%

@

12

R339 3K_0402_5%

+3VS

RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)

0. Enable (RS780)
1 : Disable(RS780)

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/11/03 2009/11/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

RS780 STRAPS

KBYF0 LA-5051P

13 46Tuesday, Fe b r u a r y 03, 2009

E

0.3

of

5

R245

+5VS

R305
0_0402_5%

@

VGA_DISABLE#

ENVDD

VGA_HDMI_CEC
I2CC_SDA

I2CC_SCL

5

PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]

+3VS

EC_ACIN <30>

JMXM2A

1

PWR_SRC

3

PWR_SRC

5

PWR_SRC

7

PWR_SRC

9

PWR_SRC

11

PWR_SRC

13

PWR_SRC

15

PWR_SRC

17

PWR_SRC

19

PWR_SRC

21

GND

23

GND

25

GND

27

GND

29

GND

31

GND

33

GND

35

GND

37

GND

39

GND

41

5V

43

5V

45

5V

47

5V

49

5V

51

GND

53

GND

55

GND

57

GND

59

PEX_STD_SW#

61

VGA_DISABLE#

63

PNL_PWR_EN

65

PNL_BL_EN

67

PNL_BL_PWM

69

HDMI_CEC

71

DVI_HPD

73

LVDS_DDC_DAT

75

LVDS_DDC_CLK

77

GND

79

OEM

81

OEM

83

OEM

85

OEM

87

GND

89

PEX_RX15#

91

PEX_RX15

93

GND

95

PEX_RX14#

97

PEX_RX14

99

GND

101

PEX_RX13#

103

PEX_RX13

105

GND

107

PEX_RX12#

109

PEX_RX12

111

GND

113

PEX_RX11#

115

PEX_RX11

117

GND

119

PEX_RX10#

121

PEX_RX10

123

GND

125

PEX_RX9#

127

PEX_RX9

129

GND

131

PEX_RX8#

133

PEX_RX8

135

GND

137

PEX_RX7#

139

PEX_RX7

141

GND

143

PEX_RX6#

145

PEX_RX6

147

GND

149

PEX_RX5#

151

PEX_RX5

153

GND

155

PEX_RX4#

157

PEX_RX4

159

GND

161

PEX_RX3#

163

PEX_RX3

165

GND

JAE_MM70-314-310B1-1

160mil(4A)

E1 E2

E3 E4

C910

VGA@

680P_0603_50V7K

PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC

PRSNT_R#

PWR_GOOD

PWR_EN

PWR_LEVEL

TH_OVERT#

TH_ALERT#

TH_PWM

SMB_DAT
SMB_CLK

PEX_TX15#

PEX_TX15

PEX_TX14#

PEX_TX14

PEX_TX13#

PEX_TX13

PEX_TX12#

PEX_TX12

PEX_TX11#

PEX_TX11

PEX_TX10#

PEX_TX10
PEX_TX9#

PEX_TX9

PEX_TX8#

PEX_TX8

PEX_TX7#

PEX_TX7

PEX_TX6#

PEX_TX6

PEX_TX5#

PEX_TX5

PEX_TX4#

PEX_TX4

PEX_TX3#

PEX_TX3

PCIE_MTX_C_GRX_N[0..15]<10>
PCIE_MTX_C_GRX_P[0..15]<10>
PCIE_GTX_C_MRX_N[0..15]<10>
PCIE_GTX_C_MRX_P[0..15]<10>

VGA@

12

D D

AC_BATT#

D27
CH751H-40PT_SOD323-2

C C

VGA_PNL_PWM<16>

I2CC_SDA<16>
I2CC_SCL<16>

LVDS DDC Module have 4.7K
Pull-UP

B B

A A

1K_0402_5%

2 1

VGA@

12

R292

0_0402_5%

@

100mil(2.5A, 5VIA)

1 2

ENVDD<16>
ENBKL<11,30>

PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P0

PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1

PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P2

PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P3

PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P4

PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P5

PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P6

PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P7

PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P8

PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P9

PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P10

PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P11

PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P12

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

WAKE#

RSVD
RSVD
RSVD
RSVD

GPIO0
GPIO1
GPIO2

GND
OEM
OEM
OEM
OEM
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

1

2

4

+MXM_B+

VGA@

1 2

FBMA-L11-201209-221LMA30T_0805

VGA@

1 2

FBMA-L11-201209-221LMA30T_0805

1

C911

VGA@

68P_0402_50V8J

2

+MXM_B++MXM_B+

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

VGA_PRSNT_R

42

VGA_WAKE#

44

VGA_PWRGD

46

VGA_ON

48
50
52
54
56

AC_BATT#

58

TH_OVERT#

60

R291

62

0_0402_5% VGA@

64
66
68
70

D_EC_SMB_DA1

72

D_EC_SMB_CK1

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164

4

PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P0

PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P1

PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P2

PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3

PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P4

PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P5

PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6

PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P7

PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P8

PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P9

PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P10

PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P11

PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12

L75

L74

160mil(4A)

2

C909

1

0.1U_0603_25V7K

0.1U_0402_16V4Z

VGA_PRSNT_R <21>
VGA_PWRGD <30>

VGA_ON <32>

B+

VGA@

C912

@

+5VS

1

2

VGA_PWRGD/TH_OVERT# Connect to EC

1 2

TH_OVERT# <30>

+3VS

SYSTEM

EC_SMB_DA1<6,30,38>

EC_SMB_CK1<6,30,38>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

R23 4.3K_0402_5%VGA@

I2CC_SDA<16>
I2CC_SCL<16>

TH_OVERT#
VGA_PWRGD
VGA_HDMI_CEC
VGA_DISABLE#
VGA_WAKE#

+3VS

1 3

D

Q69
2N7002_SOT23

VGA@

CLK_PCIE_VGA#<15>
CLK_PCIE_VGA<15>

2

G

S

Q70
2N7002_SOT23

VGA@

HDMI_TX2-_VGA<17>
HDMI_TX2+_VGA<17>

HDMI_TX1-_VGA<17>
HDMI_TX1+_VGA<17>

HDMI_TX0-_VGA<17>
HDMI_TX0+_VGA<17>

HDMI_CLK-_VGA<17>
HDMI_CLK+_VGA<17>

VGA_HDMI_SDATA<17>
VGA_HDMI_SCLK<17>

VGA_PRSNT_L<21>

R114 10K_0402_5%VGA@

1 2

R96 10K_0402_5%VGA@

1 2

R128 10K_0402_5%@

1 2

R97 10K_0402_5%@

1 2

R142 10K_0402_5%@

1 2

VGA_TZCLK-<16>
VGA_TZCLK+<16>

VGA_TZOUT2-<16>
VGA_TZOUT2+<16>

VGA_TZOUT1-<16>
VGA_TZOUT1+<16>

VGA_TZOUT0-<16>
VGA_TZOUT0+<16>

4.7K_0402_5%

2

1 3

D

G

4.7K_0402_5%

2008/11/03 2009/11/03

3

1 2

R22 4.3K_0402_5% VGA@

1 2

Increase the rise time
Ps. Module have 4.7K Pull-UP

+3VS

(Reserved)
(Reserved)
(Reserved)

PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P13

PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P14

PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P15

CLK_PCIE_VGA#
CLK_PCIE_VGA

VGA_TZCLK­VGA_TZCLK+

VGA_TZOUT2­VGA_TZOUT2+

VGA_TZOUT1­VGA_TZOUT1+

VGA_TZOUT0­VGA_TZOUT0+

+3VS

12

R322

@

D_EC_SMB_DA1

+3VS

12

R336

@

S

D_EC_SMB_CK1

HDMI_TX2-_VGA
HDMI_TX2+_VGA

HDMI_TX1-_VGA
HDMI_TX1+_VGA

HDMI_TX0-_VGA
HDMI_TX0+_VGA

HDMI_CLK-_VGA
HDMI_CLK+_VGA

VGA_HDMI_SDATA
VGA_HDMI_SCLK
VGA_PRSNT_L

(Pull-UP 10K at PCH)

Compal Secret Data

Deciphered Date

2

+3VS

167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229
231
233
235
237
239
241
243
245
247
249
251
253
255
257
259
261
263
265
267
269
271
273
275
277
279
281
283
285
287
289
291
293
295
297
299
301
303
305
307
309
311
313
314

315

JAE_MM70-314-310B1-1

2

JMXM2B

GND
PEX_RX2#
PEX_RX2
GND
PEX_RX1#
PEX_RX1
GND
PEX_RX0#
PEX_RX0
GND
PEX_REFCLK#
PEX_REFCLK
GND
RSVD
RSVD
RSVD
RSVD
RSVD
LVDS_UCLK#
LVDS_UCLK
GND
LVDS_UTX3#
LVDS_UTX3
GND
LVDS_UTX2#
LVDS_UTX2
GND
LVDS_UTX1#
LVDS_UTX1
GND
LVDS_UTX0#
LVDS_UTX0
GND
DP_C_L0#
DP_C_L0
GND
DP_C_L1#
DP_C_L1
GND
DP_C_L2#
DP_C_L2
GND
DP_C_L3#
DP_C_L3
GND
DP_C_AUX#
DP_C_AUX
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
GND
DP_A_L0#
DP_A_L0
GND
DP_A_L1#
DP_A_L1
GND
DP_A_L2#
DP_A_L2
GND
DP_A_L3#
DP_A_L3
GND
DP_A_AUX#
DP_A_AUX
PRSNT_L#

GND

C399

VGA@

10U_0805_6.3V6M

+3VS

1

1

2

VGA_RST# <19>
VGA_DDC_DATA <18>
VGA_DDC_CLK <18>
VGA_CRT_VSYNC <18>
VGA_CRT_HSYNC <18>

VGA_CRT_R <18>
VGA_CRT_G <18>
VGA_CRT_B <18>

VGA_TXCLK- <16>
VGA_TXCLK+ <16>

VGA_TXOUT2- <16>
VGA_TXOUT2+ <16>

VGA_TXOUT1- <16>
VGA_TXOUT1+ <16>

VGA_TXOUT0- <16>
VGA_TXOUT0+ <16>

VGA_HPD <17>

14 46Tuesday, February 03, 2009

1

+3VS +5VS

1

C418

VGA@

4.7U_0805_10V4Z

2

166

GND

168

PEX_TX2#

170

PEX_TX2

172

GND

174

PEX_TX1#

176

PEX_TX1

178

GND

180

PEX_TX0#

182

PEX_TX0

184

GND

PEX_CLK_REQ#

VGA_DDC_DAT

VGA_DDC_CLK

VGA_VSYNC
VGA_HSYNC

VGA_GREEN

LVDS_LCLK#

LVDS_LCLK

LVDS_LTX3#

LVDS_LTX3

LVDS_LTX2#

LVDS_LTX2

LVDS_LTX1#

LVDS_LTX1

LVDS_LTX0#

LVDS_LTX0

DP_D_AUX#

DP_B_AUX#

186
188

PEX_RST#

190
192
194
196
198

GND

200

VGA_RED

202
204

VGA_BLUE

206

GND

208
210
212

GND

214
216
218

GND

220
222
224

GND

226
228
230

GND

232
234
236

GND

238

DP_D_L0#

240

DP_D_L0

242

GND

244

DP_D_L1#

246

DP_D_L1

248

GND

250

DP_D_L2#

252

DP_D_L2

254

GND

256

DP_D_L3#

258

DP_D_L3

260

GND

262
264

DP_D_AUX

266

DP_C_HPD

268

DP_D_HPD

270

RSVD

272

RSVD

274

RSVD

276

GND

278

DP_B_L0#

280

DP_B_L0

282

GND

284

DP_B_L1#

286

DP_B_L1

288

GND

290

DP_B_L2#

292

DP_B_L2

294

GND

296

DP_B_L3#

298

DP_B_L3

300

GND

302
304

DP_B_AUX

306

DP_B_HPD

308

DP_A_HPD

310

3V3

312

3V3

316

GND

Title

Size Document Number Rev

B

KBYF0 LA-5051P

Date: Sheet of

PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P13

PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P14

PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P15

VGA_RST#
VGA_DDC_DATA
VGA_DDC_CLK
VGA_CRT_VSYNC
VGA_CRT_HSYNC

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

VGA_TXCLK­VGA_TXCLK+

VGA_TXOUT2­VGA_TXOUT2+

VGA_TXOUT1­VGA_TXOUT1+

VGA_TXOUT0­VGA_TXOUT0+

VGA_HPD

40mil(1A)

Compal Electronics, Inc.

MXM Connector

1

C183

VGA@

0.1U_0402_16V4Z

2

0.3

5

+1.2V_HT

FBMA-L11-201209-601LMT 0805

D D

C368

22P_0402_50V8J

C C

REQ0# FOR SRC1

REQ2# FOR SRC2

REQ3# FOR SRC3

External 14MHz CLK for SB710

B B

+3VS_CLK

R234

8.2K_0402_5% @

1 2

R235

8.2K_0402_5%

A A

1 2

+VDDCLK_IO

R192

1 2

1

2

1

C313

2

22U_0805_10V4Z

CLK_XTAL_OUT
CLK_XTAL_IN

Y4

12

14.31818MHZ_20P_6X1430004201

1

C360
22P_0402_50V8J

2

NB_OSC_14.318M<11>
CLK_14M_SIO<30>
SB_14M_OSC<19>

R237

@

8.2K_0402_5%

1 2

SEL_SATA

SEL_HT66

R238

8.2K_0402_5%

1 2

0.1U_0402_16V4Z

1

C316

2

MINI1_CLKREQ#<28>
MINI2_CLKREQ#<28>

CLK_SD_48M<25>
CLK_48M_USB<20>

0.1U_0402_16V4Z

1

C361

2

0.1U_0402_16V4Z

+3VS_CLK

FBMA-L11-201209-601LMT 0805

+3VS_CLK

+3VS_CLK

1 2

R231 100_0402_5%

CLK_14M_SIO
SB_14M_OSC SEL_HT66

NB_OSC_14.318M

R522 33_0402_5%
R251 33_0402_5%

CLK_48M_USB CLK_48M_USB_R

1

C365

2

0.1U_0402_16V4Z

R190

1 2

22U_0805_10V4Z

C343 0.1U_0402_16V4Z

+3VS_CLK

1 2

1 2

R201 8.2K_0402_5%

R205 8.2K_0402_5%

@

R244 33_0402_5%
R243 33_0402_5%

1

2

12
12

0.1U_0402_16V4Z

C346

+VDDCLK_IO

R232 200_0402_1%

SEL_SATA

4

0.1U_0402_16V4Z

1

1

C323

C322

2

2

+CLK_VDDA

1

1

C311

C321

0.1U_0402_16V4Z

2

2

12

R503

1 2

FBMA-L11-160808-601LMT 0603

MINI1_CLKREQ#
MINI2_CLKREQ#

SEL_27

1 2

CLK_SD_48M_RCLK_SD_48M

12
12

CLK_XTAL_IN
CLK_XTAL_OUT

+3VS

FBMA-L11-201209-601LMT 0805

U20

49
48

62
66

12
18
28
37
53

17
29
38
44
54
61
69

24
51
50
43
42

63
64
65

71
70

67
68

11
19
27
36
47
52
58
72
73

ICS 9LPRS488

VDDA
GNDA

VDDREF
GNDREF

VDDSRC_IO
VDDSRC_IO
VDDATIG_IO
VDDSB_SRC_IO
VDDCPU_IO

3

VDDDOT
VDDSRC
VDDATIG
VDDSB_SRC
VDDSATA
VDDCPU
VDDHTT
VDD48

CLKREQ0 #
CLKREQ1#
CLKREQ2#
CLKREQ3#
CLKREQ4#

REF2/SEL_27
REF1/SEL_SATA
REF0/SEL_HTT66

48MHz_0
48MHz_1

X1
X2

6

GNDDOT
GNDSRC
GNDSRC
GNDATIG
GNDSB_SRC
GNDSATA
GNDCPU
GNDHTT
GND48
GNDPAD

ICS9LPRS488AKLFT_MLF72_10x10

+3VS_CLK

R230

1 2

SMBCLK
SMBDAT

SB_SRC_SLOW#

CPUKG0T_LPRS

CPUKG0C_LPRS

HTT0T_LPRS / 66 M
HTT0C_LPRS / 66 M

SB_SRC0T_LPRS

SB_SRC0C_LPRS

SB_SRC1T_LPRS

SB_SRC1C_LPRS

ATIG0T_LPRS
ATIG0C_LPRS

ATIG1T_LPRS
ATIG1C_LPRS

ATIG2T_LPRS
ATIG2C_LPRS

SRC0T_LPRS

SRC0C_LPRS

SRC1T_LPRS

SRC1C_LPRS

SRC2T_LPRS

SRC2C_LPRS

SRC3T_LPRS

SRC3C_LPRS

SRC4T_LPRS

SRC4C_LPRS

SRC5T_LPRS

SRC5C_LPRS

SRC6T/SATAT_LPRS

SRC6C/SATAC_LPRS

SRC7T_LPRS/27MHz_SS

SRC7C_LPRS/27MHz_NS

1

C348
22U_0805_10V4Z

2

1
2

41

56
55

60
59

40
39

35
34

33
32

31
30

26
25

23
22

21
20

16
15

14
13

10
9

8
7

46
45

5
4

57

PD#

3

0.1U_0402_16V4Z

1

C324

2

0.1U_0402_16V4Z

ICH_SMBCLK0
ICH_SMBDATA0

SRC_SLOW

CLK_CPU
CLK_CPU#

CLK_HTT
CLK_HTT#

CLK_ATIG0
CLK_ATIG0#

CLK_ATIG1
CLK_ATIG1#

CLK_SRC0
CLK_SRC0#

CLK_SRC2
CLK_SRC2#

CLK_SRC3
CLK_SRC3#

CLK_SB_SRC0#

CLK_SB_SRC1#

R220 8.2K_0402_5%

1

C669

@

2

1U_0603_10V6K

R215 0_0402_5%
R206 0_0402_5%

12

1

2

1 2
1 2

1 2

R225 0_0402_5%

1 2

R222 0_0402_5%

1 2

R223 0_0402_5%

1 2

R226 0_0402_5%

1 2

R227 0_0402_5%

1 2

R229 0_0402_5%VGA@

1 2

R239 0_0402_5%

1 2

R240 0_0402_5%

1 2

R256 0_0402_5%

1 2

R255 0_0402_5%

1 2

R263 0_0402_5%

1 2

R262 0_0402_5%

1 2

R199 0_0402_5%

1 2

R200 0_0402_5%

1 2

R213 0_0402_5%

1 2

R218 0_0402_5%

1

C344

VGA@

C364

2

0.1U_0402_16V4Z

ICH_SMBCLK0 <8,9,20,28>
ICH_SMBDATA0 <8,9,20,28>

+3VS_CLK

0.1U_0402_16V4Z

1

C363

2

CLK_CPU_BCLK

12

R214
261_0402_1%@

CLK_CPU_BCLK#

CLK_NBHT
CLK_NBHT#

CLK_NBGFX
CLK_NBGFX#

CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_PCIE_LAN
CLK_PCIE_LAN#

CLK_PCIE_MINI1
CLK_PCIE_MINI1#

CLK_PCIE_MINI2
CLK_PCIE_MINI2#

CLK_SBLINK_BCLKCLK_SB_SRC0
CLK_SBLINK_BCLK#

CLK_SBSRC_BCLKCLK_SB_SRC1
CLK_SBSRC_BCLK#

2

1

C339

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C319

2

0.1U_0402_16V4Z

SRC 0

SRC 1

SRC 2

SRC 3

CLK_CPU_BCLK <6>

1

C326

2

LAN

NEW CARD

MINI2

MINI1

0.1U_0402_16V4Z

1

2

CPU

CLK_CPU_BCLK# <6>

CLK_NBHT <11>
CLK_NBHT# <11>

CLK_NBGFX <11>
CLK_NBGFX# <11>

CLK_PCIE_VGA <14>
CLK_PCIE_VGA# <14>

CLK_PCIE_LAN <26>
CLK_PCIE_LAN# <26>

CLK_PCIE_MINI1 <28>
CLK_PCIE_MINI1# <28>

CLK_PCIE_MINI2 <28>
CLK_PCIE_MINI2# <28>

CLK_SBLINK_BCLK <11>
CLK_SBLINK_BCLK# <11>

CLK_SBSRC_BCLK <19>
CLK_SBSRC_BCLK# <19>

NB CLOCK INPUT TABLE

NB CLOCKS
HT_REFCLKP
HT_REFCLKN
REFCLK_P
REFCLK_N
GFX_REFCLK
GPP_REFCLK
GPPSB_REFCLK 100M DIFF 100M DIFF

RS740 RX780 RS780

66M SE(SIN GLE END)

NC

14M SE (3.3V) 1 4 M S E (1.8V) 14M S E (1.1V)
NC NC vref

100M DIFF
NC
100M DIFF

NB GFX

VGA chip(Dis)

GLAN

MiniCard_1

MiniCard_2

NB A LINK

SB RCLK

100M DIFF
100M DIFF

100M DIFF
100M DIFF

C325

1

C362

2

0.1U_0402_16V4Z

100M DIFF
100M DIFF

100M DIFF(IN/OUT)*

NC

1

1

C350
1U_0402_6.3V4Z

2

1U CLOSE PIN 69

+3VS_CLK

12

SRC_SLOW

12

@

R197

8.2K_0402_5%

R210

8.2K_0402_5%

SEL_HTT66

SEL_SATA

* default

configure as single-ended 66MHz output

1

configure as dif fe r en tial 100MHz output

*0

100M SATA SRC6 output

1*
0

SPREAD 100M SATA SRC6 output

5

NB_OSC_14.318M

configure as 27M and 27M_SS output

1

configure as SRC_7 output

*0

4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/11/03 2009/11/03

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Clock generator

KBYF0 LA-5051P

15 46Tuesday, Fe b r u a r y 03, 2009

1

of

0.3

5

4

3

2

1

TXOUT0+

+LCDVDD

12

R5
300_0603_5%

D D

2N7002DW-T/R7_SOT363-6

R612

1 2

@

R6

1 2

R4

1 2

0_0402_5%

D2
RB751V_SOD323

21

GMCH_ENVDD<11>

ENVDD<14>

C C

BKOFF#<11,30>

VGA_PNL_PWM<14>
UMA_PNL_PWM<11>

GMCH_ENVDD
ENVDD

Q2A

0_0402_5%UMA@
0_0402_5%VGA@

100K_0402_5%

R610

1 2

R611

1 2

61

R7

0_0402_5%@
0_0402_5%@

LCD POWER CIRCUIT

+3VALW

12

R9
100K_0402_5%

2

12

VGA@

+3VS

12

R8

@

4.7K_0402_5%

DISPOFF#BKOFF#

5

INVT_PWM
INVT_PWM

R3 1K_0402_5%

3

4

2N7002DW-T/R7_SOT363-6
Q2B

12

1

C3

0.047U_0402_16V7K

2

+3VS

G

2

1 3

1

4.7U_0805_10V4Z

2

DAC_BRIG

C11 220P_0402_50V7K

INVT_PWM

C9 220P_0402_50V7K

DISPOFF#

C8 220P_0402_50V7K

W=60mils

S

AO3413_SOT23-3
Q1

D

C5

1 2
1 2
1 2

1

2

+LCDVDD

1

2

C2

4.7U_0805_10V4Z

W=60mils

C6

0.1U_0402_16V4Z

TXOUT0­TXOUT1+

TXOUT1­TXOUT2+

TXOUT2­TXCLK+

TXCLK­TZOUT0+

TZOUT0­TZOUT1+

TZOUT1­TZOUT2+

TZOUT2­TZCLK+

TZCLK-

I2CC_SDA

TXOUT0­TXOUT0+

TXOUT1­TXOUT1+

TXOUT2­TXOUT2+

TXCLK­TXCLK+

TZOUT0­TZOUT0+

TZOUT1­TZOUT1+

TZOUT2­TZOUT2+

TZCLK­TZCLK+

1 4
2 3

RP31 0_0404_4P2R_5%VGA@

1 4
2 3

RP30 0_0404_4P2R_5%VGA@

1 4
2 3

RP29 0_0404_4P2R_5%VGA@

1 4
2 3

RP28 0_0404_4P2R_5%VGA@

2 3
1 4

RP27 0_0404_4P2R_5%VGA@

2 3
1 4

RP26 0_0404_4P2R_5%VGA@

2 3
1 4

RP25 0_0404_4P2R_5%VGA@

2 3
1 4

RP24 0_0404_4P2R_5%VGA@

1 4
2 3

RP13 0_0404_4P2R_5%UMA@

1 4
2 3

RP1 0_0404_4P2R_5%UMA@

1 4
2 3

RP2 0_0404_4P2R_5%UMA@

1 4
2 3

RP3 0_0404_4P2R_5%UMA@

1 4
2 3

RP4 0_0404_4P2R_5%UMA@

2 3
1 4

RP5 0_0404_4P2R_5%UMA@

2 3
1 4

RP6 0_0404_4P2R_5%UMA@

2 3
1 4

RP7 0_0404_4P2R_5%UMA@

2 3
1 4

RP8 0_0404_4P2R_5%UMA@

VGA_TXOUT0+
VGA_TXOUT0-

VGA_TXOUT1+
VGA_TXOUT1-

VGA_TXOUT2+
VGA_TXOUT2-

VGA_TXCLK+
VGA_TXCLK-

VGA_TZOUT0+
VGA_TZOUT0-

VGA_TZOUT1+
VGA_TZOUT1-

VGA_TZOUT2+
VGA_TZOUT2-

VGA_TZCLK+
VGA_TZCLK-

GMCH_LCD_CLKI2CC_SCL
GMCH_LCD_DATA

GMCH_TXOUT0­GMCH_TXOUT0+

GMCH_TXOUT1­GMCH_TXOUT1+

GMCH_TXOUT2­GMCH_TXOUT2+

GMCH_TXCLK­GMCH_TXCLK+

GMCH_TZOUT0­GMCH_TZOUT0+

GMCH_TZOUT1­GMCH_TZOUT1+

GMCH_TZOUT2­GMCH_TZOUT2+

GMCH_TZCLK­GMCH_TZCLK+

VGA_TXOUT0+ <14>
VGA_TXOUT0- <14>

VGA_TXOUT1+ <14>
VGA_TXOUT1- <14>

VGA_TXOUT2+ <14>
VGA_TXOUT2- <14>

VGA_TXCLK+ <14>
VGA_TXCLK- <14>

VGA_TZOUT0+ <14>
VGA_TZOUT0- <14>

VGA_TZOUT1+ <14>
VGA_TZOUT1- <14>

VGA_TZOUT2+ <14>
VGA_TZOUT2- <14>

VGA_TZCLK+ <14>
VGA_TZCLK- <14>

GMCH_LCD_CLK <11>
GMCH_LCD_DATA <11>

GMCH_TXOUT0- <11>
GMCH_TXOUT0+ <11>

GMCH_TXOUT1- <11>
GMCH_TXOUT1+ <11>

GMCH_TXOUT2- <11>
GMCH_TXOUT2+ <11>

GMCH_TXCLK- <11>
GMCH_TXCLK+ <11>

GMCH_TZOUT0- <11>
GMCH_TZOUT0+ <11>

GMCH_TZOUT1- <11>
GMCH_TZOUT1+ <11>

GMCH_TZOUT2- <11>
GMCH_TZOUT2+ <11>

GMCH_TZCLK- <11>
GMCH_TZCLK+ <11>

LCD/PANEL BD. Conn.

JLVDS

42

+INVPWR_B+

+3VS

USB20_CMOS_P3

2

USB20_CMOS_N3

3

12

12

I2CC_SCL

I2CC_SDA
TZOUT0-

TZOUT0+
TZOUT1+

TZOUT1­TZOUT2+

TZOUT2­TZCLK-

TZCLK+

USB20_CMOS_N3
USB20_CMOS_P3

B+

I2CC_SCL<14>
I2CC_SDA<14>

B B

R1 0_0402_5%

USB20_N3<20>
USB20_P3<20>

USB20_N3
USB20_P3

USB20_P3

USB20_N3

+INVPWR_B+

W=40mils

1

1

A A

C12

680P_0402_50V7K

2

2

@

1 2

@

1 2

R2 0_0402_5%

L22

1

1

2

4

WCM2012F2S-900T04_0805

<>

L1

KC FBM-L11-201209-221LMAT_0805

L2

KC FBM-L11-201209-221LMAT_0805
C13
68P_0402_50V8J

3

4

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10

8
6
4
2

ACES_87242-4001-09

CONN@

GND
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

GMD

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11

9
7
5
3
1

41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3

R574 0_0603_5%

1

R575 0_0603_5%@

1

C10 0.1U_0402_16V4Z

2

+LCDVDD

1

C4
10U_0805_10V4Z

2

DAC_BRIG
INVT_PWM
DISPOFF#

TXOUT0­TXOUT0+

TXOUT1­TXOUT1+

TXOUT2+
TXOUT2-

TXCLK­TXCLK+

1 2
1 2

+LCDVDD

W=60mils

1

C7

0.1U_0402_16V4Z

2

DAC_BRIG <30>
INVT_PWM <30>

+3VS
+3VALW

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/11/03 2009/11/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

2

Date: Sheet

Compal Electronics, Inc.

LVDS & DVI Connector

KBYF0 LA-5051P

0.3

of

16 46Tuesday, Fe b r u a r y 03, 2009

1

5

D D

VGA_HDMI_SCLK<14>

GMCH_DDC_CLK<11>

VGA_HDMI_SDATA<14>

GMCH_DDC_DATA<11>

+HDMI_5V_OUT

2

C913

0.1U_0402_16V4Z

C C

B B

A A

1

5

A2Y

3

HDMI_CLK+_VGA<14>
HDMI_CLK-_VGA<14>
HDMI_TX0+_VGA<14>
HDMI_TX0-_VGA<14>
HDMI_TX1+_VGA<14>
HDMI_TX1-_VGA<14>
HDMI_TX2+_VGA<14>
HDMI_TX2-_VGA<14>

HDMI_CLK+_UMA<10>
HDMI_CLK-_UMA<10>
HDMI_TX0+_UMA<10>
HDMI_TX0-_UMA<10>
HDMI_TX1+_UMA<10>
HDMI_TX1-_UMA<10>
HDMI_TX2+_UMA<10>
HDMI_TX2-_UMA<10>

R845 2.2K_0402_5%

1

P

R851 0_0402_5%VGA@

4

OE#

G

U39
SN74AHCT1G125GW_SOT353-5

1 2

R853 0_0402_5%UMA@

1 2

C712 0.1U_0402_16V7KVGA@
C713 0.1U_0402_16V7KVGA@
C714 0.1U_0402_16V7KVGA@
C715 0.1U_0402_16V7KVGA@
C716 0.1U_0402_16V7KVGA@
C717 0.1U_0402_16V7KVGA@
C718 0.1U_0402_16V7KVGA@
C719 0.1U_0402_16V7KVGA@

12

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2

R858 0_0402_5%UMA@

1 2

R859 0_0402_5%UMA@

1 2

R860 0_0402_5%UMA@

1 2

R861 0_0402_5%UMA@

1 2

R862 0_0402_5%UMA@

1 2

R863 0_0402_5%UMA@

1 2

R864 0_0402_5%UMA@

1 2

R865 0_0402_5%UMA@

+3VS

VGA_HPD <14>
UMA_HPD <11>

4

VGA_HDMI_SCLK

GMCH_DDC_CLK
VGA_HDMI_SDATA

GMCH_DDC_DATA

HDMI_C_CLK+
HDMI_C_CLK­HDMI_C_TX0+
HDMI_C_TX0­HDMI_C_TX1+
HDMI_C_TX1­HDMI_C_TX2+
HDMI_C_TX2-

HDMI_C_CLK+
HDMI_C_CLK­HDMI_C_TX0+
HDMI_C_TX0­HDMI_C_TX1+
HDMI_C_TX1­HDMI_C_TX2+
HDMI_C_TX2-

R850

100K_0402_5%

+5VS

1 2

R878 0_0402_5%VGA@

1 2

R879 0_0402_5%UMA@

1 2

R880 0_0402_5%VGA@

1 2

R881 0_0402_5%UMA@

HDMI_HPD

2

C914

0.1U_0402_16V4Z

1

1 2

+3VS

1 2

R857 0_0402_5%

1 2

R856 0_0402_5% @

4.7K_0402_5%

R580

UMA@

+5VS

3

DDC to HDMI CONN

+3VS

12

12

R579

4.7K_0402_5%

UMA@

VGA_HDMI_SCLK_R HDMI_SCLK

VGA_HDMI_SDATA_R

D6

2 1

RB491D_SC59-3

F1

1.1A_6VDC_FUSE

HDMI_C_CLK+ HDMI_R_CK+

HDMI_C_TX0+ HDMI_R_D0+

HDMI_C_TX1+ HDMI_R_D1+

HDMI_C_TX2+ HDMI_R_D2+

6.8K_0402_5%

G

2

S

G

2

BSH111 1N_SOT23-3

Q50

13

D

S

BSH111 1N_SOT23-3

Q49

+HDMI_5V_OUT

W=40mils

21

C177

0.1U_0402_16V4Z

reserve HDMI I2C ESD diode

+HDMI_5V_OUT

12

12

R84

13

D

R87

6.8K_0402_5%

HDMI_SDATA

Place closed to JHDMI1

1

2

1 2

R382 0_0402_5%

L50

1

1

2

4

WCM-2012-900T_0805@

R383 0_0402_5%

R384 0_0402_5%

1

4

WCM-2012-900T_0805@

R385 0_0402_5%

R386 0_0402_5%

1

4

WCM-2012-900T_0805@

R387 0_0402_5%

R388 0_0402_5%

1

4

WCM-2012-900T_0805@

R390 0_0402_5%

4

1 2

1 2

L51

1

4

1 2

1 2

L52

1

4

1 2

1 2

L53

1

4

1 2

3

2

3

2

3

2

3

+HDMI_5V_OUT

VGA_HDMI_SCLK_R
VGA_HDMI_SDATA_R

2

3

2

3

2

3

2

3

2

HDMI_R_CK-HDMI_C_CLK-

HDMI_R_D0-HDMI_C_TX0-

HDMI_R_D1-HDMI_C_TX1-

HDMI_R_D2-HDMI_C_TX2-

HDMI_HPD

HDMI_SDATA
HDMI_SCLK

HDMI_R_CK­HDMI_R_CK+

HDMI_R_D0­HDMI_R_D0+

HDMI_R_D1­HDMI_R_D1+

HDMI_R_D2­HDMI_R_D2+

1 2

R854 0_0402_5% @

1 2

R855 0_0402_5% @

19
18
17
16
15
14
13
12
11
10

HDMI_SCLK
HDMI_SDATA

HDMI_R_CK+
HDMI_R_CK-

HDMI_R_D0+
HDMI_R_D0-

HDMI_R_D1+

HDMI_R_D1-

HDMI_R_D2+

HDMI_R_D2-

715-Ω for RS880M

R866

499_0402_1%

VGA@

9
8
7
6
5
4
3
2
1

JHDMI1

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CK­CK_shield
CK+
D0­D0_shield
D0+
D1­D1_shield
D1+
D2­D2_shield
D2+

SUYIN_100042MR019SX53ZL

CONN@

R866 750_0402_1%UMA@
R867 750_0402_1%UMA@

R869 750_0402_1%UMA@
R871 750_0402_1%UMA@

R872 750_0402_1%UMA@
R874 750_0402_1%UMA@

R876 750_0402_1%UMA@
R877 750_0402_1%UMA@

R872

499_0402_1%

VGA@

GND
GND
GND
GND

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

R867

499_0402_1%

VGA@

R874

499_0402_1%

VGA@

20
21
22
23

+5VS

+5VS

+5VS

+5VS

R869

499_0402_1%

VGA@

R876

499_0402_1%

VGA@

1

Q46A
2N7002DW-T/R7_SOT363-6

6 1

2

Q46B
2N7002DW-T/R7_SOT363-6

3

5

Q47A
2N7002DW-T/R7_SOT363-6

6 1

2

Q47B
2N7002DW-T/R7_SOT363-6

3

5

R871

499_0402_1%

VGA@

R877

499_0402_1%

VGA@

4

4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/11/03 2009/11/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

DVI/HDMI Connector

KBYF0 LA-5051P

0.3

of

17 46Tuesday, Fe b r u a r y 03, 2009

1

A

B

C

D

E

CRT Connector

1 1

CRT_R

CRT_G

CRT_B

R74

150_0402_1%

2 2

GMCH_CRT_VSYNC<11,13>

GMCH_CRT_HSYNC<11,13>

GMCH_CRT_R<11>

3 3

GMCH_CRT_G<11>

GMCH_CRT_B<11>

VGA_CRT_VSYNC<14>

VGA_CRT_HSYNC<14>

VGA_CRT_R<14>

VGA_CRT_G<14>

VGA_CRT_B<14>

GMCH_CRT_VSYNC

GMCH_CRT_HSYNC

GMCH_CRT_R

GMCH_CRT_G

GMCH_CRT_B

VGA_CRT_ VSYNC

VGA_CRT_HSYNC

VGA_CRT_R

VGA_CRT_G

VGA_CRT_B

R381 0_0402_5%

UMA@

R378

UMA@

R371 0_0402_5%

UMA@

R372 0_0402_5%

UMA@

R373 0_0402_5%

UMA@

R380 0_0402_5%

VGA@

R379 0_0402_5%

VGA@

R375 10_0402_5%

VGA@

1 2

R374 10_0402_5%

VGA@

1 2

R376 10_0402_5%

VGA@

1 2

12

12

12

0_0402_5%

12

12

12

12

12

12

R70

150_0402_1%

12

R54

150_0402_1%

CRT_VSYNC

CRT_HSYNC

CRT_R

CRT_G

CRT_B

CRT_VSYNC

CRT_HSYNC

CRT_R

CRT_G

CRT_B

1

1

C120

C140

2

2

5P_0402_50V8C

1 2

C67 0.1U_0402_16V4Z

CRT_HSYNC

C100

5P_0402_50V8C

1 2

L23 FCM2012C-800_0805

1 2

L18 FCM2012C-800_0805

1 2

L13 FCM2012C-800_0805

1

2

5P_0402_50V8C

+CRT_VCC

1

5

U3

P

4

OE#

A2Y

G

SN74AHCT1G125DCKR_SC70-5

3

1 2

C66 0.1U_0402_16V4Z

CRT_VSYNC D_CRT_VSYNC

6.8K_0402_5%

DSUB_12

DSUB_15

R369

33_0402_5%

R368

33_0402_5%

change to 4 7pf for ATI M66/M7x

12

12

Place closed to chipset

4 4

CRT_R_1

CRT_G_1

CRT_B_1

1

C145

C129

2

6P_0402_50V8D

+CRT_VCC

5

P

A2Y

G

SN74AHCT1G125DCKR_SC70-5

3

+CRT_VCC

12

R367

6.8K_0402_5%

1 2

L24 0_0805_5%

1 2

L20 0_0805_5%

1 2

L15 0_0805_5%

1

1

C108

2

2

6P_0402_50V8D

6P_0402_50V8D

12

R13 10K_0402_5%

D_CRT_HSYNC

1

U4

4

OE#

Place closed to chipset

+3VS

12

R366

2

G

BSH111 1N_SOT23-3

public board write w/o PH

VGA@

1 3

D

S

Q52

1 3

D

BSH111 1N_SOT23-3

1 2

R17 0_0402_5%

1 2

R18 0_0402_5%

2

Q53

UMA@

UMA@

G

S

VGA@

1

C133

@

2

GMCH_CRT_DATA

GMCH_CRT_CLK

4.7K_0402_5%

1

C115

@

2

5P_0402_50V8C

5P_0402_50V8C

1 2

L11 FCM1608C-121T_0603

1 2

L8 FCM1608C-121T_0603

+3VS

12

R36

VGA@

CRT_R_2

CRT_G_2

CRT_B_2

1

C105

@

2

5P_0402_50V8C

CRT_HSYNC_2

C98

@

100P_0402_50V8J

check with MXM board

12

R326

4.7K_0402_5%

VGA@

GMCH_CRT_DATA <11>

GMCH_CRT_CLK <11>

CRT_VSYNC_2

1

2

1 2

R35 0_0402_5%VGA@

1 2

R27 0_0402_5%VGA@

+5VS

C90

W=40mils

D18

2 1

RB491D_SC59-3

1

C83

2

100P_0402_50V8J

1

@

2

100P_0402_50V8J

F2

1.1A_6VDC_FUSE

0.1U_0402_16V4Z

1

C125

C76

2

100P_0402_50V8J

W=40mils

21

1

C430

2

DSUB_12

DSUB_15

1

2

100P_0402_50V8J

VGA_DDC_DATA <14>

VGA_DDC_CLK <14>

+CRT_VCC+R_CRT_VCC

JCRT1

6

11

1
7

12

2
8

13

3
9

14

16

G

4

17

G

10
15

5

SUYIN_070546FR015S233ZR

CONN@

CRT_DET# <20>

R30
100K_0402_5%

1 2

+CRT_VCC

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/11/03 2009/11/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

CRT Connector

KBYF0 LA-5051P

0.3

of

18 46Tuesday, Fe b r u a r y 03, 2009

E

A

1 2

R154 8.2K_0402_5%@

A_RST#

B

C

D

E

U10A

N2

A_RST#

V23

PCIE_TX0P

V22

PCIE_TX0N

V24

PCIE_TX1P

V25

PCIE_TX1N

U25

PCIE_TX2P

U24

PCIE_TX2N

T23

PCIE_TX3P

T22

PCIE_TX3N

U22

PCIE_RX0P

U21

PCIE_RX0N

U19

PCIE_RX1P

V19

PCIE_RX1N

R20

PCIE_RX2P

R21

PCIE_RX2N

R18

PCIE_RX3P

R17

PCIE_RX3N

T25

PCIE_CALRP

T24

PCIE_CALRN

P24

PCIE_PVDD

P25

PCIE_PVSS

N25

PCIE_RCLKP/NB_LNK_CLKP

N24

PCIE_RCLKN/NB_LNK_CLKN

K23

NB_DISP_CLKP

K22

NB_DISP_CLKN

M24

NB_HT_CLKP

M25

NB_HT_CLKN

P17

CPU_HT_CLKP

M18

CPU_HT_CLKN

M23

SLT_GFX_CLKP

M22

SLT_GFX_CLKN

J19

GPP_CLK0P

J18

GPP_CLK0N

L20

GPP_CLK1P

L19

GPP_CLK1N

M19

GPP_CLK2P

M20

GPP_CLK2N

N22

GPP_CLK3P

P22

GPP_CLK3N

L18

25M_48M_66M_OSC

J21

25M_X1

J20

25M_X2

A3

X1

B3

X2

F23

ALLOW_LDTSTP

F24

PROCHOT#

F22

LDT_PG

G25

LDT_STP#

G24

LDT_RST#

12
12

+SB_PCIEVDD

1

C524

1U_0402_6.3V4Z

2

CLK_SBSRC_BCLK
CLK_SBSRC_BCLK#

A_RST#
SB_RX0P_C

SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C

SB_RX0P

C275 0.1U_0402_16V7K

1 2

C278 0.1U_0402_16V7K

1 2

C287 0.1U_0402_16V7K

1 2

C279 0.1U_0402_16V7K

1 2

C272 0.1U_0402_16V7K

1 2

C274 0.1U_0402_16V7K

1 2

C266 0.1U_0402_16V7K

1 2

C267 0.1U_0402_16V7K

1 2

R149 562_0402_1%
R143 2.05K_0402_1%

L59

1

C523

10U_0805_10V4Z

CLK_SBSRC_BCLK<15>
CLK_SBSRC_BCLK#<15>

2

Close to SB

PLT_RST#

VGA_RST#

SB_RX0P<10>
SB_RX0N<10>
SB_RX1P<10>
SB_RX1N<10>
SB_RX2P<10>
SB_RX2N<10>
SB_RX3P<10>
SB_RX3N<10>

SB_TX0P<10>
SB_TX0N<10>
SB_TX1P<10>
SB_TX1N<10>
SB_TX2P<10>
SB_TX2N<10>
SB_TX3P<10>
SB_TX3N<10>

+1.2V_HT

PLT_RST# <11,13,26,28,30>

VGA_RST# <14>

SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

+PCIE_VDDR

1 2

MBC1608121YZF_0603

1 1

+3VALW

C294

12

5

0.1U_0402_16V4Z

A_RST#

2 2

C298

0.1U_0402_16V4Z

A_RST#

U12

2

P

B

4

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

12

R179 33_0402_5%

@

+3VALW

12

5

U13

2

P

B

4

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

12

R185 33_0402_5%@

External 14MHz CLK for SB710

3 3

R83 20M_0402_5%@

1 2

C192

1 2

12P_0402_50V8J

R85

20M_0603_5%

C212

1 2

12P_0402_50V8J

Close to SB

SB_32KHI

3
2

SB_32KHO

X2

4

OUT

NC

1

IN

NC

32.768KHZ_12.5P_MC-306

12

Change Capacitors to correct RTC timeing

SB_14M_OSC<15>

ALLOW_LDTSTOP<11>

H_PROCHOT#<6>

H_PWRGD<6>
LDT_STOP#<6,11>
LDT_RST#<6>

SB_14M_OSC

SB_32KHI

SB_32KHO

ALLOW_LDTSTOP
H_PROCHOT#
H_PWRGD
LDT_STOP#
LDT_RST#

218S7EALA11FG_BGA528_SB700

4 4

Security Classification

A

B

SB700

Part 1 of 5

PCICLK5/GPIO41

PCI CLKS

PCI EXPRESS INTERFACE

PCI INTERFACE

REQ3#/GPIO70
REQ4#/GPIO71

GNT3#/GPIO72
GNT4#/GPIO73

INTE#/GPIO33
INTF#/GPIO34

INTG#/GPIO35

CLOCK GENERATOR

INTH#/GPIO36

LPC

LDRQ1#/GNT5#/GPIO68

RTC XTAL

BMREQ#/REQ5#/GPIO65

INTRUDER_ALERT#

CPU

RTC

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/11/03 2009/11/03

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4

PCIRST#

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8

AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CBE0#
CBE1#
CBE2#
CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR

STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#

GNT0#
GNT1#
GNT2#

CLKRUN#

LOCK#

LPCCLK0
LPCCLK1

LAD0
LAD1
LAD2
LAD3

LFRAME#

LDRQ0#

SERIRQ

RTCCLK

VBAT

P4
P3

PCI_CLK2

P1

PCI_CLK3

P2

PCI_CLK4

T4

PCI_CLK5

T3

N1

U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3

PCI_AD23

Y2

PCI_AD24

AA2

PCI_AD25

AB4

PCI_AD26

AA1

PCI_AD27

AB3

PCI_AD28

AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6

1 2

R180 0_0402_5%

V5
AD3

AC4
AE2
AE3

G22
E22

LPC_AD0

H24

LPC_AD1

H23

LPC_AD2

J25

LPC_AD3

J24

LPC_FRAME#

H25
H22

LPC_DRQ1#

AB8
AD7

SERIRQ

V15

RTC_CLK

C3
C2

R127 1M_0402_5%

B2

+RTCVCC_R

C289

1

2

0.1U_0402_16V4Z

Compal Secret Data

PCI_CLK2 <23>
PCI_CLK3 <23>
PCI_CLK4 <23>
PCI_CLK5 <23>

PCI_AD23 <23>
PCI_AD24 <23>
PCI_AD25 <23>
PCI_AD26 <23>
PCI_AD27 <23>
PCI_AD28 <23>

T12PAD @
T13PAD @

@

T11PAD

@

T18PAD

R120 22_0402_5%

@

1 2

C293

1

2

1 2

LPC_AD0 <30>
LPC_AD1 <30>
LPC_AD2 <30>
LPC_AD3 <30>

LPC_FRAME# <30>

LPC_DRQ1# <30>
SERIRQ <30>

R184 510_0402_5%

for Clear CMOS

1U_0402_6.3V4Z

PM_CLKRUN# <30>

W=20mils

Deciphered Date

H_PWRGD H_PWRGD_L

CLK_PCI_EC
LPCCLK1

EC & Debug

RTC_CLK <23>

+RTCVCC

1 2

D

STRAP PIN

+RTCVCC

@

1 2

+1.8VS +3VS

G

2

13

D

S

Q35

CLK_PCI_EC <23,30>
LPCCLK1 <23,30>

R178 1K_0402_5%

J1
0_0603_5%

12

C297

Title

Size Document Number Rev

Custom

Date: Sheet

R394

4.7K_0402_5%

1 2

FDV301N_NL_SOT23-3

H_PWRGD_L <44>

STRAP PIN

+RTCBATT

D10

3

1

2

0.1U_0402_16V4Z

1

2

BAS40-04_SOT23-3

Compal Electronics, Inc.

SB700-PCIE/PCI/ACPI/LPC/RTC

KBYF0 LA-5051P

E

+CHGRTC

19 46Tuesday, Fe b r u a r y 03, 2009

0.3

of

A

SKU-ID R509 R510

B

C

D

E

UMA
DIS

1 1

R417

1 2

10K_0402_5%

+3VS

+3VALW

2 2

3 3

4 4

1 2

R137 10K_0402_5%

SB700 has internal PD

1 2

R133 2.2K_0402_5%@

1 2

R132 2.2K_0402_5%@

1 2

R131 2.2K_0402_5%@

1 2

R124 2.2K_0402_5%

+3VS

R413 2.2K_0402_5%

1 2

R410 2.2K_0402_5%

1 2

+3VALW

R136 2.2K_0402_5%

1 2

R135 2.2K_0402_5%

1 2

R134 10K_0402_5%

1 2

R536 100K_0402_5%@

1 2

HDA_BITCLK_AUDIO<33>
HDA_BITCLK_MDC<32>
HDA_SDOUT_MDC< 32>
HDA_SDOUT_AUDIO<33>

HDA_SDIN0<33>
HDA_SDIN1<32>

STRAP PIN

POP

@

EC_RSMRST#

HDA_SYNC_MDC<32>
HDA_SYNC_AUDIO<33>

HDA_RST_AUDIO#<33>
HDA_RST_MDC#<32>

A

POP

NB_PWRGD

SUS_STAT#

SB_TEST2
SB_TEST1

SB_TEST0

ICH_SMBCLK0
ICH_SMBDATA0

ICH_SMBCLK1
ICH_SMBDATA1
SB_PCIE_WAKE#

EC_LID_OUT#

R146 33_0402_5%
R152 33_0402_5%
R153 33_0402_5%
R147 33_0402_5%

HDARST#<23>

1 2

R513 10K_0402_5%@

1 2

R514 10K_0402_5%@

1 2

R515 10K_0402_5%@

demo circuit LID use RI#

R509 2.2K_0402_5%VGA@

+3VS

1 2
1 2
1 2
1 2

R144 33_0402_5%
R150 33_0402_5%

R145 33_0402_5%
R151 33_0402_5%

1 2

R510 2.2K_0402_5%

1 2

HDA_BITCLK CPU_SIC_SB
HDA_SDOUT

1 2
1 2

1 2
1 2

SB Power Domain :S5

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2

CRT_DET#<18>

EC_SWI#<30>

PM_SLP_S3#<30>
PM_SLP_S5#<30>
PBTN_OUT#<30>
SB_PWRGD<6,32>
SUS_STAT#<11>

EC_GA20<30>
EC_KBRST#<30>

EC_SCI#<30>
EC_SMI#<30>

SB_PCIE_WAKE#<26,28>
H_THERMTRIP#<6>

NB_PWRGD<11>

EC_RSMRST#<30>

UMA@

SB_SPKR<33>

ICH_SMBCLK0<8,9,15,28>
ICH_SMBDATA0<8,9,15,28>
ICH_SMBCLK1<26>
ICH_SMBDATA1<26>

USB_OC#6<29>

EC_LID_OUT#<30>

USB_OC#2<24,29>
USB_OC#1<29>

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2

+3VS

R130 2.2K_0402_5%

High: CRT Plugged

2N7002_SOT23

B

EC_SWI#

PM_SLP_S3#
PM_SLP_S5#
PBTN_OUT#
SB_PWRGD
SUS_STAT#
SB_TEST2
SB_TEST1
SB_TEST0
EC_GA20
EC_KBRST#
EC_SCI#
EC_SMI#

SB_PCIE_WAKE#
H_THERMTRIP#

NB_PWRGD
EC_RSMRST#

SB_SPKR
ICH_SMBDATA0

ICH_SMBCLK1
ICH_SMBDATA1

USB_OC#6
EC_LID_OUT#
USB_OC#2

USB_OC#1

HDA_SYNC

HDARST#

@

1 2

2

G

Q36

CRT_DET

SKU_ID

+3VALW

1 2
13

D

S

T14PAD

@

R406
100K_0402_5%

CRT_DET

U10D

E1

PCI_PME#/GEVENT4#

E2

RI#/EXTEVNT0#

H7

SLP_S2/GPM9#

F5

SLP_S3#

G1

SLP_S5#

H2

PWR_BTN#

H1

PWR_GOOD

K3

SUS_STAT#

H5

TEST2

H4

TEST1

H3

TEST0

Y15

GA20IN/GEVENT0#

W15

KBRST#/GEVENT1#

K4

LPC_PME#/GEVENT3#

K24

LPC_SMI#/EXTEVNT1#

F1

S3_STATE/GEVENT5#

J2

SYS_RESET#/GPM7#

H6

WAKE#/GEVENT8#

F2

BLINK/GPM6#

J6

SMBALERT#/THRMTRIP#/GEVENT2#

W14

NB_PWRGD

D3

RSMRST#

AE18

SATA_IS0#/GPIO10

AD18

CLK_REQ3#/SATA_IS1#/GPIO6

AA19

SMARTVOLT1/SATA_IS2#/GPIO4

W17

CLK_REQ0#/SATA_IS3#/GPIO0

V17

CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39

W20

CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40

W21

SPKR/GPIO2

AA18

SCL0/GPOC0#

W18

SDA0/GPOC1#

K1

SCL1/GPOC2#

K2

SDA1/GPOC3#

AA20

DDC1_SCL/GPIO9

Y18

DDC1_SDA/GPIO8

C1

LLB#/GPIO66

Y19

SMARTVOLT2/SHUTDOWN#/GPIO5

G5

DDR3_RST#/GEVENT7#

B9

USB_OC6#/IR_TX1/GEVENT6#

B8

USB_OC5#/IR_TX0/GPM5#

A8

USB_OC4#/IR_RX0/GPM4#

A9

USB_OC3#/IR_RX1/GPM3#

E5

USB_OC2#/GPM2#

F8

USB_OC1#/GPM1#

E4

USB_OC0#/GPM0#

M1

AZ_BITCLK

M2

AZ_SDOUT

J7

AZ_SDIN0/GPIO42

J8

AZ_SDIN1/GPIO43

L8

AZ_SDIN2/GPIO44

M3

AZ_SDIN3/GPIO46

L6

AZ_SYNC

M4

AZ_RST#

L5

AZ_DOCK_RST#/GPM8#

H19

IMC_GPIO0

H20

IMC_GPIO1

H21

SPI_CS2#/IMC_GPIO2

F25

IDE_RST#/F_RST#/IMC_GPO3

D22

IMC_GPIO4

E24

IMC_GPIO5

E25

IMC_GPIO6

D23

IMC_GPIO7

218S7EALA11FG_BGA528_SB700

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SB700

USB OC

HD AUDIO

INTEGRATED uC

C

Part 4 of 5

USB_HSD9P

USB_HSD9N

USB_HSD8P

USB_HSD8N

USB_HSD7P

USB_HSD7N

USB_HSD6P

USB_HSD6N

USB_HSD5P

USB_HSD5N

USB_HSD4P

USB_HSD4N

USB_HSD3P

USB_HSD3N

USB_HSD2P

USB_HSD2N

USB_HSD1P

USB_HSD1N

USB_HSD0P

USB_HSD0N

IMC_GPIO8
IMC_GPIO9

IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25

IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41

C8

USB_RCOMP

G8

E6
E7

USB20_P12

F7

USB20_N12

E8
H11

J10
E11

F11
A11

B11

USB20_P8

C10

USB20_N8

D10
G11

H12

USB20_P6

E12

USB20_N6

E14

USB20_P5

C12

USB20_N5ICH_SMBCLK0

D12

USB20_P4

B12

USB20_N4

A12

USB20_P3

G12

USB20_N3

G14

USB20_P2

H14

USB20_N2

H15

USB20_P1

A13

USB20_N1

B13

USB20_P0

B14

USB20_N0

A14
A18

B18
F21
D21
F19
E20

CPU_SID_SB

E21
E19

GPIO16

D19

GPIO17

E18
G20

G21
D25
D24
C25
C24
B25
C23

B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18

Compal Secret Data

Deciphered Date

USBCLK/14M_25M_48M_OSC

ACPI / WAKE UP EVENTS

USB_RCOMP

USB_FSD13P

USB MISC

USB_FSD13N
USB_FSD12P

USB_FSD12N

USB 1.1

USB_HSD11P
USB_HSD11N

USB_HSD10P
USB_HSD10N

USB 2.0

GPIO

IMC_PWM0/IMC_GPIO10

SCL2/IMC_GPIO11
SDA2/IMC_GPIO12

SCL3_LV/IMC_GPIO13

SDA3_LV/IMC_GPIO14

IMC_PWM1/IMC_GPIO15

IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17

INTEGRATED uC

2008/11/03 2009/11/03

1 2

CLK_48M_USB

1 2

R40511.8K_0402_1%

R10933_0402_5%@

CLK_48M_USB <15>

USB20_P12 <29>
USB20_N12 <29>

USB20_P8 <28>
USB20_N8 <28>

USB20_P6 <29>
USB20_N6 <29>

USB20_P5 <28>
USB20_N5 <28>

USB20_P4 <25>
USB20_N4 <25>

USB20_P3 <16>
USB20_N3 <16>

R50 0_0402_5% @

1 2

R51 0_0402_5%JV70@

1 2

R52 0_0402_5% JV70@

1 2

R53 0_0402_5% @

1 2

USB20_P1 <29>
USB20_N1 <29>

USB20_P0 <29>
USB20_N0 <29>

CPU_SIC_SB <6>
CPU_SID_SB <6>

GPIO16 <23>
GPIO17 <23>

D

C232

22P_0402_50V8J@

1 2

STRAP PIN
STRAP PIN

USB-12 Bluetooth

USB-8 MiniCard(WLAN)

USB-6 HS-USB

USB-5 MiniCard(TV)

USB-4 Card Reader

USB-3 USB Ca mera

USB-2 USB (eSATA) for SJM70

Ext.USB/B for SJV70

USB-1 Ext.USB/B

USB-0 Ext.USB/B

USB20_P2_2
USB20_P2_1
USB20_N2_1
USB20_N2_2

Title

Size Document Number Rev

Custom

Date: Sheet

USB20_P2_2 <29>
USB20_P2_1 <24>
USB20_N2_1 <24>
USB20_N2_2 <29>

Compal Electronics, Inc.

SB700 USB/HD audio

KBYF0 LA-5051P

20 46Tuesday, Fe b r u a r y 03, 2009

E

of

0.3

A

B

C

D

E

Port Number

EC_THERM#

1 2
1 2

+SB_AVDD

1

2

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

pop after bring up

1 2

R110 0_0402_5%

1 2

R111 0_0402_5%

BLM18PG121SN1D_0603

1

C488

2.2U_0603_6.3V4Z

2

1 1

SATA_STX_DRX_P0<24>

HDD

SATA_STX_R_DRX_P1<24>

S- HDD

ODD

2 2

3 3

SATA_STX_R_DRX_N1<24>

SATA_STX_R_DRX_P2<24>
SATA_STX_R_DRX_N2<24>

C28410P_0402_50V8J

12

12

C28310P_0402_50V8J

12

Y325MHZ_20P

+1.2V_HT

+3VS

12

R176

10M_0402_5%

BLM18PG121SN1D_0603

SATA_STX_DRX_N0<24>

SATA_DTX_C_SRX_N0<24>
SATA_DTX_C_SRX_P0<24>

SATA_STX_R_DRX_N1

SATA_DTX_C_SRX_N1<24>
SATA_DTX_C_SRX_P1<24>

SATA_STX_R_DRX_P2 SATA_STX_DRX_P2
SATA_STX_R_DRX_N2

SATA_DTX_C_SRX_N2<24>
SATA_DTX_C_SRX_P2<24>

SATA_X1

SATA_X2

+3VS

SATA_LED#<31>

L61

12

C562

2.2U_0603_6.3V4Z

L34

1U_0402_6.3V4Z

12

BLM18PG121SN1D_0603

1 2

R182 4.99_0402_1%

1 2

R181 4.99_0402_1%

R342 4.99_0402_1%

1 2
1 2

R183 4.99_0402_1%

R411 10K_0402_5%

1 2

SATA_LED#

2

2

C560
1U_0402_6.3V4Z

1

1

2

C296

1

SATA_STX_DRX_P0
SATA_STX_DRX_N0

SATA_DTX_C_SRX_N0
SATA_DTX_C_SRX_P0

SATA_STX_DRX_P1SATA_STX_R_DRX_P1
SATA_STX_DRX_N1

SATA_DTX_C_SRX_N1
SATA_DTX_C_SRX_P1

SATA_STX_DRX_N2
SATA_DTX_C_SRX_N2

SATA_DTX_C_SRX_P2

R412 1K_0402_1%

1

C546

2

C545

1

2

+XTLVDD_SATA

12

SATA_CAL

SATA_X1
SATA_X2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

U10B

AD9

SATA_TX0P

AE9

SATA_TX0N

AB10

SATA_RX0N

AC10

SATA_RX0P

AE10

SATA_TX1P

AD10

SATA_TX1N

AD11

SATA_RX1N

AE11

SATA_RX1P

AB12

SATA_TX2P

AC12

SATA_TX2N

AE12

SATA_RX2N

AD12

SATA_RX2P

AD13

SATA_TX3P

AE13

SATA_TX3N

AB14

SATA_RX3N

AC14

SATA_RX3P

AE14

SATA_TX4P

AD14

SATA_TX4N

AD15

SATA_RX4N

AE15

SATA_RX4P

AB16

SATA_TX5P

AC16

SATA_TX5N

AE16

SATA_RX5N

AD16

SATA_RX5P

V12

SATA_CAL

Y12

SATA_X1

AA12

SATA_X2

W11

SATA_ACT#/GPIO67

AA11

PLLVDD_SATA

W12

XTLVDD_SATA

218S7EALA11FG_BGA528_SB700

SB700

Part 2 of 5

SATA PWR SERIAL ATA

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23

ATA 66/100/133

IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

SPI_DI/GPIO12

SPI_DO/GPIO11

SPI_CLK/GPIO47

SPI_HOLD#/GPIO31

SPI_CS1#/GPIO32

LAN_RST#/GPIO13

SPI ROM

ROM_RST#/GPIO14

FANOUT0/GPIO3

FANOUT1/GPIO48
FANOUT2/GPIO49

FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52

TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63

TEMPIN3/TALERT#/GPIO64

HW MONITOR

IDE_IORDY

IDE_IRQ

IDE_A0
IDE_A1
IDE_A2

IDE_DACK#

IDE_DRQ
IDE_IOR#

IDE_IOW#

IDE_CS1#
IDE_CS3#

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

AVDD
AVSS

AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24

AD24
AD23
AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23

SB_SI_SPI_SO

G6

SB_SO_SPI_SI

D2

SB_SPICLK

D1

SB_HOLD#

F4

SB_SPICS# SB_SPICLK

F3
U15

J1
M8

M5
M7

P5
P8
R8

NB_THERMAL_DC_R

C6

NB_THERMAL_DA_R NB_THERMAL_DA

B6
A6
A5
B5

A4

R260 0_0402_5%@

B4

R261 0_0402_5%@

C4
D4
D5
D6
A7
B7

F6
G7

C492

0.1U_0402_16V4Z

Pri/SEC,Mas/Slave assignment SATA drive controlled by

Primary master

Secondary master

Primary slave

Secondary slave

Primary (Secondary) master

Primary (Secondary) slave

+3VALW

D30 RB751V_SOD323

+3VALW

1K_0402_5%

SB_SPICS#

@

1 2

R545 0_0402_5%

If use, Un-pop R545

NB_THERMAL_DC+PLLVDD_SATA

VGA_PRSNT_R <14>
VGA_PRSNT_L <14>

+3VALW

@
@

EC_THERM# <30>

VGA_PRSNT_R
VGA_PRSNT_L

L55

SB_HOLD#

12

@

2 1

R549

@

0_0603_5%

R546

@

1 2

@

12

R547

@

1 2

10K_0402_5%

1

2

SATA controler

SATA controler

SATA controler

SATA controler

PATA controler

PATA controler

C667 0.1U_0402_16V4Z @

1 2

R548

@

10K_0402_5%

1 2

U23

1

CE#

3

WP#

7

HOLD#

4

VSS

MX25L8005M2C-15G_SOP8

@

C229
10P_0402_50V8J

R104 100K_0402_5%

NB_THERMAL_DC <11>

NB_THERMAL_DA <11>

2 1

D7 RB751V_SOD323

1 2

NC7SZ08P5X_NL_SC70-5

+SB_SPI_VCC

8

VDD

6

SCK

5

SI

2

SO

U44

4

@

SB_SO_SPI_SI
SB_SI_SPI_SO

ACIN

+3VALWS

5

P

Y

G

3

VGA_PRSNT_R
VGA_PRSNT_L

+3VS

C670

1 2

0.1U_0402_16V4Z

2

B

1

A

1 2

R295 10K_0402_5%

1 2

R296 10K_0402_5%

ACIN <30,36,37,40>

@

ACIN

+3VS

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/11/03 2009/11/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet of

Compal Electronics, Inc.

SB700 SATA/IDE/SPI

KBYF0 LA-5051P

21 46Tuesday, Fe b r u a r y 03, 2009

E

0.3

A

+3VS

C561 10U_0603_6.3V6M
C563 10U_0603_6.3V6M

1 1

+3VS

+1.2V_HT

2 2

+1.2V_HT

+3VALW

3 3

C529 1U_0402_6.3V4Z

1 2

C536 1U_0402_6.3V4Z

1 2

C556 1U_0402_6.3V4Z

1 2

C513 1U_0402_6.3V4Z

1 2

C542 1U_0402_6.3V4Z

1 2

C550 1U_0402_6.3V4Z

1 2

C538 0.1U_0402_16V4Z

1 2

C508 0.1U_0402_16V4Z

1 2

@

C557 10U_0603_6.3V6M

@

C558 10U_0603_6.3V6M

C544 0.1U_0402_16V4Z@

1 2

C548 0.1U_0402_16V4Z@

1 2

C551 0.1U_0402_16V4Z

1 2

@

L32

1 2
1 2
1 2

1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2

12

L60

12

L29

12

FBMA-L11-201209-221LMA30T_0805

C254 10U_0603_6.3V6M
C276 10U_0603_6.3V6M

C525 1U_0402_6.3V4Z
C522 1U_0402_6.3V4Z
C527 1U_0402_6.3V4Z

C251 0.1U_0402_16V4Z
C250 0.1U_0402_16V4Z

FBMA-L11-201209-221LMA30T_0805

C568 10U_0603_6.3V6M
C565 10U_0603_6.3V6M

C547 1U_0402_6.3V4Z
C549 1U_0402_6.3V4Z
C552 0.1U_0402_16V4Z
C559 0.1U_0402_16V4Z

FBMA-L11-201209-221LMA30T_0805

C228 10U_0603_6.3V6M
C236 10U_0603_6.3V6M
C491 1U_0402_6.3V4Z
C497 1U_0402_6.3V4Z
C493 0.1U_0402_16V4Z
C489 0.1U_0402_16V4Z
C499 0.1U_0402_16V4Z

+1.2V_SATA

+AVDD_USB

+PCIE_VDDR

B

U10C

L9

VDDQ_1

M9

VDDQ_2

T15

VDDQ_3

U9

VDDQ_4

U16

VDDQ_5

U17

VDDQ_6

V8

VDDQ_7

W7

VDDQ_8

Y6

VDDQ_9

AA4

VDDQ_10

AB5

VDDQ_11

AB21

VDDQ_12

Y20

VDD33_18_1

AA21

VDD33_18_2

AA22

VDD33_18_3

AE25

VDD33_18_4

P18

PCIE_VDDR_1

P19

PCIE_VDDR_2

P20

PCIE_VDDR_3

P21

PCIE_VDDR_4

R22

PCIE_VDDR_5

R24

PCIE_VDDR_6

R25

PCIE_VDDR_7

AA14

AVDD_SATA_1

AB18

AVDD_SATA_4

AA15

AVDD_SATA_2

AA17

AVDD_SATA_3

AC18

AVDD_SATA_5

AD17

AVDD_SATA_6

AE17

AVDD_SATA_7

A16

AVDDTX_0

B16

AVDDTX_1

C16

AVDDTX_2

D16

AVDDTX_3

D17

AVDDTX_4

E17

AVDDTX_5

F15

AVDDRX_0

F17

AVDDRX_1

F18

AVDDRX_2

G15

AVDDRX_3

G17

AVDDRX_4

G18

AVDDRX_5

218S7EALA11FG_BGA528_SB700

SB700

Part 3 of 5

PCI/GPIO I/O

IDE/FLSH I/O

POWER

A-LINK I/O

3.3V_S5 I/OCORE S5

SATA I/O

USB_PHY_1.2V_1
USB_PHY_1.2V_2

PLL CLKGEN I/O

USB I/O

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8

CORE S0

VDD_9

CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7

S5_1.2V_1
S5_1.2V_2

V5_VREF
AVDDCK_3.3V
AVDDCK_1.2V

AVDDC

L15
M12
M14
N13
P12
P14
R11
R15
T16

L21
L22
L24
L25

A17
A24
B17
J4
J5
L1
L2

G2
G4

A10
B10

AE7
J16
K17
E9

C

+SB_VDD

1 2

R399

1 2

R391

FBMA-L11-201209-221LMA30T_0805

+1.2V_CKVDD

+S5_3V

R138 FBMA-L11-201209-221LMA30T_0805

+S5_1.2V

L28 FBMA-L11-160808-221LMT 0603

+1.2_USB

R578 1K_0402_5%

+V5_VREF
+AVDDCK_3.3V
+AVDDCK_1.2V
+AVDDC

L31

C505 1U_0402_6.3V4Z

C249 1U_0402_6.3V4Z
C502 0.1U_0402_16V4Z
C507 0.1U_0402_16V4Z

C248 10U_0603_6.3V6M

1 2

+1.2VALW

C227 10U_0603_6.3V6M
C242 10U_0603_6.3V6M

12

C231 1U_0402_6.3V4Z

12

C240 1U_0402_6.3V4Z

12

C277

0.1U_0402_16V4Z

L54

FBMA-L11-160808-221LMT 0603

FBMA-L11-201209-221LMA30T_0805@

C49010U_0603_6.3V6M
C40110U_0603_6.3V6M

C5121U_0402_6.3V4Z

12

C5041U_0402_6.3V4Z

12

C5211U_0402_6.3V4Z

12

C5261U_0402_6.3V4Z

12

C5190.1U_0402_16V4Z

12

C5110.1U_0402_16V4Z

12

FBMA-L11-160808-221LMT 0603

1 2
1 2

12
12

+3VALW

C25210U_0603_6.3V6M
C24310U_0603_6.3V6M

C2411U_0402_6.3V4Z

12

C5031U_0402_6.3V4Z

12

C2530.1U_0402_16V4Z

12

C5060.1U_0402_16V4Z

12

C2470.1U_0402_16V4Z

12

2

2

C291

1U_0603_10V4Z

1

1

C4872.2U_0603_6.3V4Z

12

C4960.1U_0402_16V4Z

12

FOR SB700 ALL issue
A12 Will cha n ge to +1.2V_HT

+1.2VALW
+1.2V_HT

+1.2V_HT

L56 FBMA-L11-160808-221LMT 0603

R1721K_0402_5%

12
21

D9 RB751V_SOD323

+3VALW

C4951U_0402_6.3V4Z

12

C4941U_0402_6.3V4Z

12

+5VS
+3VS

D

+1.2VALW

U10E

SB700

T10

AVSS_SATA_1

U10

AVSS_SATA_2

U11

AVSS_SATA_3

U12

AVSS_SATA_4

V11

AVSS_SATA_5

V14

AVSS_SATA_6

W9

AVSS_SATA_7

Y9

AVSS_SATA_8

Y11

AVSS_SATA_9

Y14

AVSS_SATA_10

Y17

AVSS_SATA_11

AA9

AVSS_SATA_12

AB9

AVSS_SATA_13

AB11

AVSS_SATA_14

AB13

AVSS_SATA_15

AB15

AVSS_SATA_16

AB17

AVSS_SATA_17

AC8

AVSS_SATA_18

AD8

AVSS_SATA_19

AE8

AVSS_SATA_20

A15

AVSS_USB_1

B15

AVSS_USB_2

C14

AVSS_USB_3

D8

AVSS_USB_4

D9

AVSS_USB_5

D11

AVSS_USB_6

D13

AVSS_USB_7

D14

AVSS_USB_8

D15

AVSS_USB_9

E15

AVSS_USB_10

F12

AVSS_USB_11

F14

AVSS_USB_12

G9

AVSS_USB_13

H9

AVSS_USB_14

H17

AVSS_USB_15

J9

AVSS_USB_16

J11

AVSS_USB_17

J12

AVSS_USB_18

J14

AVSS_USB_19

J15

AVSS_USB_20

K10

AVSS_USB_21

K12

AVSS_USB_22

K14

AVSS_USB_23

K15

AVSS_USB_24

H18

PCIE_CK_VSS_1

J17

PCIE_CK_VSS_2

J22

PCIE_CK_VSS_3

K25

PCIE_CK_VSS_4

M16

PCIE_CK_VSS_5

M17

PCIE_CK_VSS_6

M21

PCIE_CK_VSS_7

P16

PCIE_CK_VSS_8

F9

AVSSC

Part 5 of 5

218S7EALA11FG_BGA528_SB700

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42

GROUND

VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50

PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21

AVSSCK

A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24

P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25

L17

E

+AVDDCK_1.2V

+AVDDCK_3.3V

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

L57

FBMA-L11-160808-221LMT 0603

L30

FBMA-L11-160808-221LMT 0603

2008/11/03 2009/11/03

+1.2V_HT

C5012.2U_0603_6.3V4Z

12

C5100.1U_0402_16V4Z

12

+3VS

C2462.2U_0603_6.3V4Z

12

C5000.1U_0402_16V4Z

12

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SB700 power/GND

KBYF0 LA-5051P

22 46Tuesday, Fe b r u a r y 03, 2009

E

of

0.3

A

B

C

D

E

REQUIRED STRAPS

PCI_CLK2

CLK_PCI_PCM CLK_PCI_DBG

PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5
CLK_PCI_EC
LPCCLK1
RTC_CLK
HDARST#
GPIO17
GPIO16

BOOTFAIL

TIMER

ENABLED

BOOTFAIL
TIMER
DISABLED

DEFAULT

R155

@

R156

PULL

1 1

PCI_CLK2<19>
PCI_CLK3<19>
PCI_CLK4<19>
PCI_CLK5<19>

CLK_PCI_EC<19,30>

LPCCLK1<19,30>
RTC_CLK<19>

2 2

HDARST#<20>

HIGH

PULL
LOW

GPIO17<20>
GPIO16<20>

PCI_CLK3

USE
DEBUG
STRAPS

IGNORE
DEBUG
STRAPS

DEFAULT

+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW

12

10K_0402_5%

10K_0402_5%

R158

@

12

R157

12

10K_0402_5%

12

10K_0402_5%

PCI_CLK4 PCI_CLK5

RESERVED

R161

@

R162

@

RESERVED

12

10K_0402_5%

12

10K_0402_5%

NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

LPC_CLK0

R159

10K_0402_5%

@

R160

10K_0402_5%

@

12

12

CLK_PCI_EC

ENABLE PCI
MEM BOOT

DISABLE PCI
MEM BOOT

DEFAULT

12

R121

10K_0402_5%

@

12

R122

10K_0402_5%

CLKGEN
ENABLED

CLKGE N

DISABLED

DEFAULT

R116

10K_0402_5%

@

R117

10K_0402_5%

RTC_CLKLPC_CLK1

INTERNAL
RTC

DEFAULT

EXT. RTC

(PD on X1,
apply
32KHz to
RTC_CLK)

12

R125

@

12

R126

@

12

10K_0402_5%

12

2.2K_0402_5%

AZ_RST_CD#

EC

ENABLED

EC

DISABLED

DEFAULT

12

R139

10K_0402_5%

@

12

R140

10K_0402_5%

GP17

GP16

Internal pull up

H,H = Reserved
H,L = SPI ROM

L,H = LPC ROM (Default L,NC)

L,L = FWH ROM

12

12

@

R102

2.2K_0402_5%

R99

2.2K_0402_5%

R103

2.2K_0402_5%

12

12

@

R100

2.2K_0402_5%

DEBUG STRAPS

SB700 HAS 15K IN T E RN AL PU FOR PCI_AD[28:23]

12

2.2K_0402_5%

PCI_AD27 PCI_AD26

12

2.2K_0402_5%

USE ACPI
BCLK

DEFAULT

BYPASS
ACPI
BCLK

R165

@

USE PCI
PLL

DEFAULT

BYPASS
PCI PLL

R168

@

PCI_AD28

PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23

USE
LONG
RESET

DEFAULT

USE
SHORT

RESET

R167

@

PULL

3 3

PCI_AD28<19>
PCI_AD27<19>
PCI_AD26<19>
PCI_AD25<19>
PCI_AD24<19>
PCI_AD23<19>

4 4

HIGH

PULL
LOW

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

2.2K_0402_5%

C

PCI_AD25 PCI_AD24

12

2.2K_0402_5%

USE DEFAULT
PCIE STRAPS

DEFAULT

USE EEPROM
PCIE STRAPS

R166

@

USE IDE
PLL

DEFAULT

BYPASS IDE
PLL

R169

@

2008/11/03 2009/11/03

12

2.2K_0402_5%

PCI_AD23

RESERVED

12

R164

2.2K_0402_5%

@

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

SB700 STRAPS

KBYF0 LA-5051P

23 46Tuesday, Fe b r u a r y 03, 2009

E

0.3

of

A

B

C

D

E

F

G

H

+5VS

1

2

0.1U_0402_16V4Z

12

0.1U_0402_16V4Z

1

C424

@

2

1000P_0402_50V7K

1

2

C482

10U_0805_10V4Z

1 1

Pleace near HD CONN (JSATA1)

+3VS

R348 0_0805_5%

Pleace near HD CONN

C483

1

2

@

1

2

0.1U_0402_16V4Z

+3VS_HDD1

C419

1U_0603_10V4Z

0.1U_0402_16V4Z

1

C420

2

1

C423

@

2

1U_0402_6.3V4Z

1

C421

1000P_0402_50V7K

1

C395

C396

2

2

SUYIN_127043FR022G226ZL_NR

JSATA1

GND

A+

A-

GND

B-

B+

GND

V33
V33

V33
GND
GND
GND

V5
V5
V5

GND

Reserved

GND

V12

V12

V12

<BOM Structure>

1
2
3
4
5
6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

Second-HDD

+5VS

C573

10U_0805_10V4Z

1

2

0.1U_0402_16V4Z

2 2

Pleace near HD CONN (JSATA3)

+3VS

R349 0_0805_5%

12

0.1U_0402_16V4Z

1

C570

@

2

1000P_0402_50V7K

Pleace near HD CONN

3 3

+5VALW

C340

4.7U_0805_10V4Z

SYSON#<29,36,43>

USB20_P2_1<20>

4 4

USB20_N2_1<20>

USB20_P2_1

USB20_N2_1

A

1

2

1

2

C576

1

2

@

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

+3VS_HDD2

C485

1U_0603_10V4Z

1

C567

C486

2

1000P_0402_50V7K

1

C569

@

2

80mil

U30

1

GND

2

IN

3

IN

4

EN#

TPS2061DRG4_SO8

@

1 2

R389 0_0402_5%

L37

1

1

4

4

WCM2012F2S-900T04_0805

<>

1 2

R377 0_0402_5%@

1U_0402_6.3V4Z

1

1

C574

C575

2

2

+USB_VCCA

8

OUT

7

OUT

6

OUT

5

FLG

2

3

B

JSATA3

GND

A+

A-

GND

B-

B+

GND

VCC3.3
VCC3.3
VCC3.3

GND
GND

GND
VCC5
VCC5
VCC5

GND

RESERVED

GND

VCC12
VCC12
VCC12

G1

CONN@

G2

+3VALW

12

R242
100K_0402_5%
R228

10K_0402_5%

OCTEK_SAT-22SB1G_RV

2

3

1
2
3
4
5
6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

23
24

1 2

USB20_P2_R
USB20_N2_R

HDD

SATA_STX_RC_DRX_P0
SATA_STX_RC_DRX_N0

SATA_DTX_SRX_N0
SATA_DTX_SRX_P0

+3VS_HDD1

+5VS

SATA_STX_RC_DRX_P1
SATA_STX_RC_DRX_N1

SATA_DTX_SRX_N1
SATA_DTX_SRX_P1

+3VS_HDD2

+5VS

1

C333

0.1U_0402_16V4Z

2

C

C336 0.01U_0402_16V7K
C332 0.01U_0402_16V7K

C345 0.01U_0402_16V7K
C347 0.01U_0402_16V7K

C379 0.01U_0402_16V7K
C384 0.01U_0402_16V7K

C378 0.01U_0402_16V7K
C369 0.01U_0402_16V7K

USB_OC#2 <20,29>

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

PJDLC05_SOT23~D

SATA_STX_DRX_P0
SATA_STX_DRX_N0

SATA_DTX_C_SRX_N0
SATA_DTX_C_SRX_P0

Adjust HDD1 CHA I/O EQ

Adjust HDD1 CHB I/O EQ

SATA_STX_R_DRX_P1
SATA_STX_R_DRX_N1

SATA_DTX_C_SRX_N1
SATA_DTX_C_SRX_P1

+USB_VCCA

W=60mils

1

+

C806

150U_Y_6.3VM

2

USB20_N2_R

USB20_P2_R

D39

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

1

C808

2

0.1U_0402_16V4Z

2

3

1

1000P_0402_50V7K

SATA_STX_DRX_P0 <21>
SATA_STX_DRX_N0 <21>

SATA_DTX_C_SRX_N0 <21>
SATA_DTX_C_SRX_P0 <21>

R680 470K_0402_5%@
R679 470K_0402_5%@
R677 470K_0402_5%@
R676 470K_0402_5%@

1
2
3
4
5
6
7

8
9
10
11
12
13

JUSB4

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

SUYIN_020173MR004S512ZL

Deciphered Date

SATA_PTX_RPI_DRX_P0
SATA_PTX_RPI_DRX_N0

SATA_DTX_RPO_PRX_P0

12
12
12
12

ODD

SATA_STX_RC_DRX_P2
SATA_STX_RC_DRX_N2

SATA_DTX_SRX_N2
SATA_DTX_SRX_P2

+5VS

F

C622 0.01U_0402_16V7K@

1 2

C620 0.01U_0402_16V7K@

1 2

C618 0.01U_0402_16V7K@

1 2

C617 0.01U_0402_16V7K@

1 2

SATA_STX_R_DRX_P1 <21>
SATA_STX_R_DRX_N1 <21>

SATA_DTX_C_SRX_N1 <21>
SATA_DTX_C_SRX_P1 <21>

JSATA2

GND

A+

A-

GND

B-

B+

GND

DP
+5V
+5V

15
14

1

C807

2

2008/11/03 2009/11/03

E

GND

GND

GND

GND

OCTEK_0709015-SD001_RVCONN@

USB20_N2_R
USB20_P2_R

Compal Secret Data

MD

U2

2

VDD1

6

VDD2

3

AI+

4

AI-

7

BO+

8

BO-

1

A_EQ

20

A_EM

10

B_EQ

11

B_EM

PI2EQX3231BLZHE_TQFN20_3P5X4P5

@

R404 0_0402_5%@

1 2

R403 0_0402_5%@

1 2

R402 0_0402_5%@

1 2

R401 0_0402_5%@

1 2

VDD3
VDD4

GND1
GND2
GND3
GND4

AO+
AO-

9
15
19

CE

18
17

14

BI+

13

BI-

5
16
12
21

HDD1 Redriver Chip Enable

C302 0.01U_0402_16V7K

1 2

C301 0.01U_0402_16V7K

1 2

C300 0.01U_0402_16V7K

1 2

C299 0.01U_0402_16V7K

1 2

Size Document Number Rev

Date: Sheet

+1.5VS+1.5VS

SATA1_CE

SATA_PTX_RPO_DRX_P0
SATA_PTX_RPO_DRX_N0

SATA_DTX_RPI_PRX_N0SATA_DTX_RPO_PRX_N0
SATA_DTX_RPI_PRX_P0

SATA_PTX_RPO_DRX_P0
SATA_PTX_RPO_DRX_N0

SATA_DTX_RPI_PRX_N0
SATA_DTX_RPI_PRX_P0

SATA1_CE

SATA_STX_R_DRX_P2
SATA_STX_R_DRX_N2

SATA_DTX_C_SRX_N2
SATA_DTX_C_SRX_P2

+5VS

+1.5VS

1 2

R425 470_0402_5%@

R426
10K_0402_5%

@

Placea caps. near ODD CONN.

0.1U_0402_16V4Z

C591

Title

B

1U_0603_10V4Z

1

1

1

2

C580

C614

2

2

Compal Electronics, Inc.

HDD & ODD Connector

KBYF0 LA-5051P

G

C610

@

1U_0402_6.3V4Z

2

1 2

@

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

C612

@

1

1

C611

Adjust HDD1 PCH TX Swing

SATA_STX_R_DRX_P2 <21>
SATA_STX_R_DRX_N2 <21>

SATA_DTX_C_SRX_N2 <21>
SATA_DTX_C_SRX_P2 <21>

10U_0805_10V4Z

1

C386
10U_0805_10V4Z

2

of

24 46Tuesday, Fe b r u a r y 03, 2009

H

+1.5VS

1

2

0.3

5

4

3

2

1

+REG18_PLL

12

C592 0.1U_0402_16V4Z

D D

+3VS

@

1 2

Vender suggesttion

C C

@

47P_0402_50V8J

1

2

1

C596

2

+3VS

+3VALW

R395
100K_0402_5%

Internal 200K Pull UP

1 2

R393 0_0402_5%

C595
1U_0402_6.3V4Z

MODE_SEL

12

R396
0_0402_5%

@

1 2

R843 0_0603_5%

RST#

R844 0_0603_5%

1 2

+XDPWR_SDPWR_MSPWR

1

C593

4.7U_0603_6.3V6K

2

@

USB20_N4<20>
USB20_P4<20>
5IN1_LED#<31>

+XDPWR_SDPWR_MSPWR

C594

1

0.1U_0402_16V4Z

RST#

2

MODE_SEL
XTLO
XTLI

USB20_N4
USB20_P4

R363 6.19K_0402_1%

CARD_AGND

1
3
7

9
11
33

8
44
45
47
48

4

5
14

12

2
12

32

6
46

R396 NC for RTS5158E
R396 stuff for RTS5159

CLK_SD_48M<15>

12

R397

@

33_0402_5%

B B

@

1

C598
22P_0402_50V8J

2

1 2

R398 0_0402_5%

@

1 2

C597 6P_0402_50V8D

12MHZ_16PF_6X12000012

@

1 2

C600 6P_0402_50V8D

XTLI

12

Y2

@

XTLO

EMI

+XDPWR_SDPWR_MSPWR

40~60 mil

R42

A A

100K_0402_5%

1 2

R400 0_0603_5%

1

C599

0.1U_0402_16V4Z

2

1 2

+CARDPWR

R392
0_0603_5%

1 2

SDDAT5_XDD0_MSD6
SDCLK_XDD1_MSCLK
SDDAT7_XDD2_MSD2
SDDAT1_XDD3_MSD1
XDD4_SDDAT1
XDD5_MSBS
SDDAT0_XDD6_MSD0
SDDAT6_XDD7_MSD3

SDDAT3_XDWE#
SDDAT4_XDWP#_MSD7
XDALE
XDCD
XD_RDY
SDDAT2_XDRE#
XDCE#
XDCLE

R362 0_0402_5%

U14

AV_PLL
NC
NC
CARD_3V3
D3V3
D3V3

3V3_IN
RST#
MODE_SEL
XTLO
XTLI

DM
DP
GPIO0

RREF
DGND

DGND
AGND

AGND

RTS5158E-GR_LQFP48_7X7

+CARDPWR

12

SD_DAT2/XD_RE#_SP16

SD_DAT3/XD_WE#_SP15

SD_DAT4/XD_WP#/MS_D7_SP13

SD_DAT5/XD_D0/MS_D6_SP12
SD_CLK/XD_D1/MS_CLK_SP11
SD_DAT6/XD_D7/MS_D3_SP10

SD_DAT7/XD_D2/MS_D2_SP8
SD_DAT0/XD_D6/MS_D0_SP7
SD_DAT1/XD_D3/MS_D1_SP6

XD_D4/SD_DAT1_SP4

JP56

3

XD-VCC

32

XD-D0

10

9
8
7
6
5
4

34
33
35
40
39
38
37
36

11
31

41
42

TAITW_R015-A10-LM_NR

XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

7IN1 GND
7IN1 GND

7IN1 GND
7IN1 GND

7 IN 1 CONN

VREG

MS_D4

XD_CLE_SP19
XD_CE#_SP18
XD_ALE_SP17

XD_RDY_SP14

MS_INS#_SP9

XD_D5_SP5

SD_CD#_SP3

SD_WP_SP2

XD_CD#_SP1

EEDI

XTAL_CTR

MS_D5

EEDO
EECS
EESK

SD_CMD

+REG18

NC

SD-CD-SW

SD-WP-SW

MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

10
22
30

43
42
41
40
39
38
37
35
34
31
29
28
27
26
25
23
21
20
19
18

13
24

15
16
17
36

SD-VCC

MS-VCC

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7

SD-CMD

MS-SCLK

MS-INS

MS-BS

XTAL_CTR

21
28

20
14
12
30
29
27
23
18
16
25
1

2

26
17
15
19
24
22
13

1 2

C341 1U_0402_6.3V4Z

XDCLE
XDCE#

XDALE
SDDAT2_XDRE#
SDDAT3_XDWE#

XD_RDY
SDDAT4_XDWP#_MSD7
SDDAT5_XDD0_MSD6
SDCLK_XDD1_MSCLK_L
SDDAT6_XDD7_MSD3
MS_INS#
SDDAT7_XDD2_MSD2
SDDAT0_XDD6_MSD0
SDDAT1_XDD3_MSD1

XDD5_MSBS

XDD4_SDDAT1

SDCD
SDWP
XDCD

12

R284 0_0603_5%

SD_CMD

+CARDPWR

SDCLK_XDD1_MSCLK
SDDAT0_XDD6_MSD0

XDD4_SDDAT1
SDDAT2_XDRE#
SDDAT3_XDWE#

SDDAT4_XDWP#_MSD7

SDDAT5_XDD0_MSD6
SDDAT6_XDD7_MSD3
SDDAT7_XDD2_MSD2

SDCLK_XDD1_MSCLK
SDDAT0_XDD6_MSD0
SDDAT1_XDD3_MSD1
SDDAT7_XDD2_MSD2
SDDAT6_XDD7_MSD3

XDD5_MSBS

R354 0_0402_5%

SD_CMD

SDCD

SDWP

MS_INS#

+3VS

12

SDCLK_XDD1_MSCLK

1

C604
22P_0402_50V8J@

2

+CARDPWR

C603

10U_0805_10V4Z

1

1

0.1U_0402_16V4Z

2

2

1

C342

C484

2

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/03 2009/11/03

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Ele ct ronics, Inc.

Card Reader JMB385

KBYF0 LA-5051P

0.3

25 46Tuesday, February 03, 2009

1

A

+3VALW +3V_LAN

+3V_LAN

1 1

2 2

3 3

4 4

1

C149

4.7U_0805_10V4Z

2

PCIE_PTX_C_IRX_N3<10>
PCIE_PTX_C_IRX_P3<10>

1

2

ICH_SMBDATA1<20>

1 2

R77 0_1206_5%

1 2

R60 4.7K_0402_5%

60mil

1

C417

2

0.1U_0402_16V4Z

PLT_RST#<11,13,19,28,30>

SB_PCIE_WAKE#<20,28>

EC_PME#<30>

LAN_XTALI

Y1

1 2

25MHZ_20P

C138
27P_0402_50V8J

LAN_PME#

+3V_LAN

1

1

0.1U_0402_16V4Z

2

LAN_XTALO

27P_0402_50V8J

C428

C422

2

0.1U_0402_16V4Z

CLK_PCIE_LAN#<15>
CLK_PCIE_LAN<15>

1 2

R37 10K_0402_5%

R21 1K_0402_5%

+3VS

R20 1K_0402_5%

+3V_LAN

ENERGY_DET<30>

PCIE_ITX_C_PRX_N3<10>
PCIE_ITX_C_PRX_P3<10>

C142
C143

PLT_RST# LAN_RESET#

12

1

C137

2

2N7002DW-T/R7_SOT363-6
R15 0_0402_5% @

A

1 2

0.1U_0402_16V7K

1 2

0.1U_0402_16V7K

R47 0_0402_5%

1 2

R56 0_0402_5%@

1 2

R61 0_0402_5%

1 2

XTALO

R73
200_0402_1%

+3V_LAN

5

3

4

Q4B

@

1 2

ICH_SMBCLK1<20>

+3V_LAN

12

0.1U_0402_16V4Z

CLK_PCIE_LAN#
CLK_PCIE_LAN

1 2
1 2

ENERGY_DET
+LAN_GPHYPLLVDD
PCIE_ITX_C_PRX_N3
PCIE_ITX_C_PRX_P3
PCIE_PTX_IRX_N3
PCIE_PTX_IRX_P3

LAN_SMBCLK
LAN_SMBDATA

1 2

R67 0_0402_5%

+LAN_PCIEVDD

R14

4.7K_0402_5%

LAN_SMBDATA

+3V_LAN

1

C678

2

LAN_PME#

LAN_PME#

SPROM_WP

LAN_XTALI
XTALO

2N7002DW-T/R7_SOT363-6
R19 0_0402_5%

U5

28

PCIE_REFCLK_N

29

PCIE_REFCLK_P

11

CLKREQ

3

LOW PWR

53

VMAIN_PRSNT

54

VAUX_PRSNT

59

ENERGY_DET

35

GPHY_PLLVDD

32

PCIE_RXD_N

31

PCIE_RXD_P

25

PCIE_TXD_N

26

PCIE_TXD_P

10

PERST

12

WAKE

58

SMB_CLK

57

SMB_DATA

4

GPIO_0(SERIAL_DO)

7

GPIO_1(SERIAL_DI)

8

GPIO_2

9

UART_MODE

21

XTALI

22

XTALO

16

REG_GND/S_IDDQ
PCIE_GND/VDD24E- PAD

BCM5764MKML_QFN68

5784

+3V_LAN

2

6 1

Q4A

@

@

1 2

TRD1_N/AVDD
TRD2_N/AVDD

REGCTL25/12_IO

PCIE_VDD/PLL

+3V_LAN

12

LAN_SMBCLK

B

TRD0_N

TRD0_P
TRD1_P/T1_N
TRD2_P/T2_N

TRD3_N

TRD3_P

LINKLED

SPD100LED
SPD1000LED
TRAFFICLED

SCLK(EECLK)

SO(EEDATA)

REGCTL12

RDAC

XTALVDD

VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

VDDP

VDDP/DC

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

BIASVDD

PCIE_PLLVDD

PCIE_VDD

AVDD/DC

AVDD/AVDDL

AVDD/DC

AVDDL
AVDDL/T1_P
AVDDL/T2_P

AVDDL

R16

4.7K_0402_5%

B

SI

CS

LAN_MIDI0-

41

LAN_MIDI0+

40

+LAN_AVDD

42

LAN_MIDI1-

43

+LAN_AVDD

48

LAN_MIDI2-

47

LAN_MIDI3-

49

LAN_MIDI3+

50

2
1
67
66

SPROM_CLK

65

SPROM_DIN

63

SPROM_DOUT

64

SPROM_CS

62

LAN_REGCTL12

14
18
37

23
6
15
19
56
61

17
68

5
13
20
34
55
60

36
30
27
33

38
45
52

39
44
46

+LAN_AVDDL

51
69

C

R309 1_1206_1%

+3V_LAN

LAN_LINK#

12

R24
0_0402_5%

R25
0_0402_5%

LAN_RDAC

R66 1.24K_0402_1%

+LAN_XTALVDD

+3V_LAN

+LAN_BIASVDD
+LAN_PCIEPLLVDD

+LAN_PCIEVDD

+LAN_AVDDL

+LAN_AVDDL
LAN_MIDI1+
LAN_MIDI2+

LAN_ACTIVITY#

12

R29 4.7K_0402_5%

1 2

1 2

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

R12 1_1206_1%

1 2

LAN_REGCTL12

Q3
MMJT9435T1G_SOT223

LAN_MIDI0- <27>
LAN_MIDI0+ <27>

LAN_MIDI1- <27>
LAN_MIDI2- <27>

LAN_MIDI3- <27>
LAN_MIDI3+ <27>

1 2

C444

+1.2V_VDDCIO

+1.2V_VDDCIO

BLM18AG601SN1D_0603

+1.2V_LAN

1

2

LAN_MIDI1+ <27>
LAN_MIDI2+ <27>

2008/11/03 2009/11/03

1

C68

10U_0805_10V4Z

LAN_LINK# <27>

LAN_ACTIVITY# <27>

+1.2V_VDDCIO

L48

1

C437

0.1U_0402_16V4Z

2

+3V_LAN_R

1

C27

0.1U_0402_16V4Z

2

4.7U_0805_10V4Z

2 3

4

1

1

2

0.1U_0402_16V4Z

+3V_LAN

C412

2

4.7U_0805_10V4Z

+1.2V_VDDCIO

1

C415

2

0.1U_0402_16V4Z

L43

1 2

BLM18AG601SN1D_0603

Compal Secret Data

Deciphered Date

C

1

C28

2

1

0.1U_0402_16V4Z

2

1

C39

2

R308 0_0402_5%@

C71

0.1U_0402_16V4Z

12

+3V_LAN

1

1

2

C37

C132

0.1U_0402_16V4Z

2

SPROM_DIN

U24

1

A0

VCC

2

A1

WP

3

A2

SCL

4

GND

SDA

AT24C64AN-10SU-2.7_SO8

D

+1.2V_LAN

1

1

1

C448

C409

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

+3V_LAN

R299

4.7K_0402_5%

1 2

8
7
6
5

20mil

+LAN_PCIEPLLVDD

0.1U_0402_16V4Z

20mil

+LAN_PCIEVDD

0.1U_0402_16V4Z

20mil

+LAN_AVDD

0.1U_0402_16V4Z

20mil

+LAN_AVDDL

0.1U_0402_16V4Z

20mil

+LAN_GPHYPLLVDD

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

+3V_LAN

+3V_LAN

1

C410

0.1U_0402_16V4Z

2

SPROM_WP
SPROM_CLK
SPROM_DOUT

C440

C434

C427

C426

C126

Title

Size Document Number Rev

Custom

Date: Sheet

R311

4.7K_0402_5%

BLM18AG601SN1D_0603

1

1

C445

2

2

4.7U_0805_10V4Z

BLM18AG601SN1D_0603

1

1

C441

2

2

4.7U_0805_10V4Z

1

1

C70

2

2

0.1U_0402_16V4Z

BLM18AG601SN1D_0603

1

1

C416

2

2

4.7U_0805_10V4Z

1

C122

2

4.7U_0805_10V4Z

BLM18AG601SN1D_0603

1

2

Compal Electronics, Inc.

KBYF0 LA-5051P

1

C438

C111

0.1U_0402_16V4Z

2

2

R312

4.7K_0402_5%

1 2

L47

1 2

L45

1 2

1 2

BLM18AG601SN1D_0603

L38

1 2

L19

1 2

1 2

L39

BCM5764M_5787M

D

+1.2V_LAN

+1.2V_LAN

+1.2V_LAN

+1.2V_LAN

+3V_LAN+3V_LAN

R321

4.7K_0402_5%

1 2

+3V_LAN

26 46Tu esday, February 03, 2009

0.3

of

5

4

3

2

1

1

C403

0.1U_0402_16V4Z

2

T1

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+

6

TD2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

350uH_GSL5009LF-1

1

C406

2

MCT1

MX1+

MX1-

MCT2

MX2+

MX2-

MCT3

MX3+

MX3-

MCT4

MX4+

MX4-

24
23
22
21
20
19
18
17
16
15
14
13

R300

75_0402_1%

12

R303

75_0402_1%

12

R302
75_0402_1%

12

12

RJ45_MIDI0+
RJ45_MIDI0-

RJ45_MIDI1+
RJ45_MIDI1-

RJ45_MIDI2+
RJ45_MIDI2-

RJ45_MIDI3+
RJ45_MIDI3-

R304
75_0402_1%

RJ45_GND

12

R504
0_0603_5%

@

40mil

LAN_LINK#<26>

LAN_ACTIVITY#<26>

+3V_LAN

+3V_LAN

1 2

C397
220P_0402_50V7K

LAN_ACTIVITY#

R298 1K_0402_5%

LAN_LINK#

R307

RJ45_GND LANGND

12

RJ45_MIDI3-

RJ45_MIDI3+

RJ45_MIDI1-

RJ45_MIDI2­RJ45_MIDI2+
RJ45_MIDI1+

RJ45_MIDI0­RJ45_MIDI0+

12

1K_0402_5%

C25
1000P_1206_2KV7K

JRJ45

12

Yellow LED-

11

Yellow LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

Green LED-

9

Green LED+

SUYIN_100073FR012G101ZL

conn@

1 2

C408
220P_0402_50V7K

1 2

C24

0.1U_0402_16V4Z

4.7U_0805_10V4Z

1

2

Guide Pin

14

SHLD2

13

SHLD1

R505
0_0603_5%

40mil

1

12

C26

2

D D

LAN_MIDI0+<26>
LAN_MIDI0-<26>

LAN_MIDI1+<26>
LAN_MIDI1-<26>

LAN_MIDI2+<26>
LAN_MIDI2-<26>

LAN_MIDI3+<26>
LAN_MIDI3-<26>

C C

LAN_MIDI0+
LAN_MIDI0-

LAN_MIDI1+
LAN_MIDI1-

LAN_MIDI2+
LAN_MIDI2-

LAN_MIDI3+
LAN_MIDI3-

0.1U_0402_16V4Z

1

C400

0.1U_0402_16V4Z

2

1

C402

2

0.1U_0402_16V4Z

Place close to TCT pin

B B

LAN_ACTIVITY#

LAN_LINK#

1 2

C398
68P_0402_50V8J

@

1 2

C405
68P_0402_50V8J

@

For EMI

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/03 2009/11/03

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

KBYF0 LA-5051P

2

Date: Sheet of

Compal Ele ct ronics, Inc.

LAN Magnetic & RJ45/RJ11

27 46Tuesday, February 03, 2009

1

0.3

A

B

C

D

E

For Wireless LAN

+3VS+3VS +1.5VS

1

C615

0.1U_0402_16V4Z

2

WL_OFF#
PLT_RST#

R279 0_0603_5%

1 2

R278 0_0603_5%

1 2

12

+3VALW

@

MINI1_LED#

(9~16mA)

R550
100K_0402_5%

@

ICH_SMBCLK0
ICH_SMBDATA0

USB20_N8
USB20_P8

+3VS
+1.5VS

WL_OFF# <30>
PLT_RST# <11,13,19,26,30>

+3VS
+3VALW

ICH_SMBCLK0 <8,9,15,20>

ICH_SMBDATA0 <8,9,15,20>
USB20_N8 <20>

USB20_P8 <20>

MINI1_LED# <30>

WLAN_BT_DATA<29>

WLAN_BT_CLK<29>

MINI2_CLKREQ#<15>

CLK_PCIE_MINI2#<15>
CLK_PCIE_MINI2<15>

PCIE_PTX_C_IRX_N1<10>
PCIE_PTX_C_IRX_P1<10>

PCIE_ITX_C_PRX_N1<10>
PCIE_ITX_C_PRX_P1<10>

+3VS

1

C387

@

4.7U_0805_10V4Z

2

SB_PCIE_WAKE#

+3VS

For TV-Tuner/HW MPEG

+1.5VS

1

C380

@

0.1U_0402_16V4Z

2

R498 0_0402_5%@

1 2

WLAN_BT_DATA
WLAN_BT_CLK
MINI2_CLKREQ#

CLK_PCIE_MINI2#
CLK_PCIE_MINI2

PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P1

PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P1

E51TXD_P80DATA_R
E51RXD_P80CLK

1

C383

@

4.7U_0805_10V4Z

2

JMINI2

1

1

3

3

5

5

7

7

9

9
111112
131314
151516

171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152

G153G254G355G3

1

C385

0.1U_0402_16V4Z

2

2

2

4

4

6

6

8

8

10

10

12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

FOX_AS0B226-S99N-7F

56

CONN@

1

C389

@

0.1U_0402_16V4Z

2

+3VS
+1.5VS

PLT_RST#

R344 0_0603_5%@

1 2

R345 0_0603_5%

1 2

ICH_SMBCLK0
ICH_SMBDATA0

USB20_N5
USB20_P5

+3VS

H=9.2 mm

@

USB20_N5 <20>
USB20_P5 <20>

+3VS
+3VALW

+3VS

0_0402_5%

1 2

1

C613

0.1U_0402_16V4Z

2

R282 0_0402_5%@

WLAN_BT_DATA
WLAN_BT_CLK
MINI1_CLKREQ#

CLK_PCIE_MINI1#
CLK_PCIE_MINI1

PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2

PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P2

E51TXD_P80DATA_R

E51RXD_P80CLK

1 2

1

C390

4.7U_0805_10V4Z

2

1

C381

0.1U_0402_16V4Z

2

JMINI1

1

1

3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

GND1

GND2

FOX_AS0B226-S52N-7F~N

CONN@

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

1

C382

0.1U_0402_16V4Z

2

1

C609

4.7U_0805_10V4Z

PCIE_PTX_C_IRX_N2<10>
PCIE_PTX_C_IRX_P2<10>

PCIE_ITX_C_PRX_N2<10>
PCIE_ITX_C_PRX_P2<10>

WLAN_BT_DATA<29>

WLAN_BT_CLK<29>

MINI1_CLKREQ#<15>

CLK_PCIE_MINI1#<15>
CLK_PCIE_MINI1<15>

E51RXD_P80CLK<30>

2

SB_PCIE_WAKE#

R469

1 1

SB_PCIE_WAKE#<20,26>

E51TXD_P80DATA<30>

2 2

H=5.2 mm

Power

+3VS

+3V

+1.5VS

Mini Card Power Rating

Primary Power (mA)

Peak Normal

1000

330

500

750

250

375

Auxiliary Power (mA)

Normal

250 (wake enable)

5 (Not wake enable)

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/11/03 2009/11/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

MINI CARD (WLAN & TV-Tuner)

KBYF0 LA-5051P

E

0.3

of

28 46Tuesday, Fe b r u a r y 03, 2009

A

B

C

D

E

Bluetooth Conn.

+3VALW +3VS

1

S

AO3413_SOT23-3
Q16

D

W=40mils

C335

0.1U_0402_16V4Z

1 2

B

C334
1U_0603_10V4Z

2

2

G

0.1U_0402_16V4Z

USB20_N6_1
USB20_P6_1

+BT_VCC

12

R452
300_0603_5%

13

D

Q42
2N7002_SOT23

S

1
2
3
4

5
6

USB_OC#6

1

C566

2

HS USB PORT

JUSB3

VCC
D­D+
GND

GND1
GND2

SUYIN_020173MR004S512ZL

USB20_P12<20>
USB20_N12<20>

WLAN_BT_DATA<28>

WLAN_BT_CLK<28>

USB_OC#6 <20>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 1

BT_ON#<30>

2 2

+5VALW

1

C555

4.7U_0805_10V4Z

2

SYSON#<24,36,43>

3 3

USB20_P6<20>

USB20_N6<20>

4 4

USB20_P6

USB20_N6

A

BT_ON#

U29

1

GND

2

IN

3

IN

4

EN#

TPS2061DRG4_SO8

R407 0_0402_5%@

1

4

R408 0_0402_5%@

C320

0.1U_0402_16V4Z

1 2

R202 10K_0402_5%

L58

WCM2012F2S-900T04_0805

<>

80mil

OUT
OUT
OUT
FLG

+USB_VCCB

+

1 2

1

4

1 2

PJDLC05_SOT23~D

C330

0.1U_0402_16V4Z

+USB_VCCB

8
7
6
5

+USB_VCCB

1

C539
150U_D2_6.3VM

2

2

2

3

3

USB20_N6_1
USB20_P6_1

D21

G

2

1 3

1

C327

4.7U_0805_10V4Z

2

+3VALW

12

R421
100K_0402_5%

R422 10K_0402_5%

W=80mils

1

C498
470P_0402_50V7K

2

USB20_P6_1

USB20_N6_1

2

3

1

USB20_P12
USB20_N12

WLAN_BT_DATA
WLAN_BT_CLK

+3VALW

+3VALW

12

1

2

C

+BT_VCC

JP10

1

9

1

GND

2

2

3

3

4

4

5

5

6

6

7

7

8

10

8

GND

ACES_87213-0800G

CONN@

2 PORT

SYSON#
USB20_N0

USB20_P0
USB20_N1

USB20_P1
USB_OC#1

12

R516
100K_0402_5%

USB_OC#1

1

C607

0.1U_0402_16V4Z

2

SYSON#<24,36,43>

USB20_N0<20>
USB20_P0<20>

USB20_N1<20>
USB20_P1<20>

USB_OC#1<20>

1 PORT FOR JV70

R520
100K_0402_5%

@

USB_OC#2

C608

0.1U_0402_16V4Z

@

2008/11/03 2009/11/03

SYSON#<24,36,43>

USB20_N2_2<20>
USB20_P2_2<20>

USB_OC#2<20,24>

Compal Secret Data

Deciphered Date

SYSON#
USB20_N2_2

USB20_P2_2
USB_OC#2

D

+5VALW

+5VALW

JP54

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

G1

14

G2

E&T_3703-E12N-03R

right

JP55

1

1

GND

2

2

3

3

4

4

5

5

6

6

7

7

8

8

GND

E-T_3703-E08N-03R

Right Up

9

10

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

NEW CARD & US B Connector

KBYF0 LA-5051P

E

of

29 46Tuesday, Fe b r u a r y 03, 2009

0.3

5

+3VALW

@

1 2

R204 10K_0402_5%

1 2

R211 10K_0402_5%

D D

RCIRRX<32>

22P_0402_50V8J@

C C

+5VS

B B

ESB_EC_CK2<31>
ESB_EC_DA2<31>

ESB_EC_CK2<31>
ESB_EC_DA2<31>

EC_I2C_INT2<31>
EC_I2C_INT1<31>

1 2

R221 4.7K_0402_5%

1 2

R224 4.7K_0402_5%

+3VALW

1 2

R207 4.7K_0402_5%

1 2

R208 4.7K_0402_5%

+3VS

1 2

R217 2.2K_0402_5%

1 2

R216 2.2K_0402_5%

1 2

R561 4.7K_0402_5%

1 2

R562 4.7K_0402_5%

1 2

R473 8.2K_0402_5% @

LPC debug port

JP28

1
2
3
4
5
6
7
8
9

10

A A

11
12
13
14
15
16
17
18
19
20

ACES_85201-20051

@

EC_PME#

LID_SW#

R198

10K_0402_5%

D11

RB751V_SOD323

C331

R219 33_0402_5%@

12

CLK_PCI_EC<19,23>

+3VALW

R188 47K_0402_5%

C306 0.1U_0402_16V4Z

TP_CLK
TP_DATA

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

ESB_CLK
ESB_DATA

PM_CLKRUN#

+5VS +3VS

CLK_14M_SIO
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ1#
PLT_RST#

R521 0_0402_5%

1 2

R523 0_0402_5%

1 2

SERIRQ

5

+3VALW

21

12

1 2

EC_RCIRRX

12

CLK_PCI_EC

12

CY@

CY@

+3VALW

2

1

CLK_14M_SIO <15>

LPC_DRQ1# <19>

0.1U_0402_16V4Z
C315

1

1

C307

2

2

0.1U_0402_16V4Z

Pin 74--ENE RST(R) or CY INT(R)
Pin16--ENE RST(L) or CY INT(L)

PM_CLKRUN#<19>

EC_SMB_CK2

12

R474 0_0402_5%

EC_SMB_DA2

12

R475 0_0402_5%

ENE@

ESB_CLK

12

R477 0_0402_5%

ESB_DATA

ENE@

12

R478 0_0402_5%

R479 0_0402_5%

EC_I2C_INT2_R

12

EC_I2C_INT1_R

12

R480 0_0402_5%

1 2

R286 47K_0402_5%

1 2

R287 47K_0402_5%

EC_SMB_CK1<6,14,38>
EC_SMB_DA1<6,14,38>
EC_SMB_CK2<6>
EC_SMB_DA2<6>

PM_SLP_S3#<20>
PM_SLP_S5#<20>

TH_OVERT#<14>

ENERGY_DET<26>

C353

15P_0402_50V8J

ENE@

FAN_SPEED1<35>

BT_ON#<29>

ON/OFF<32>

PWR_SUSP_LED<31>

NUM_LED#<31>

EC_GA20<20>

EC_KBRST#<20>

SERIRQ<19>

LPC_FRAME#<19>

LPC_AD3<19>
LPC_AD2<19>
LPC_AD1<19>
LPC_AD0<19>

PLT_RST#<11,13,19,26,28>

EC_SCI#<20>

KSO1
KSO2

EC_SMI#<20>

LPCCLK1 <19,23>

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C337

2

EC_SCI#
PM_CLKRUN#

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#

EC_I2C_INT2_R

ESB_CLK
ESB_DATA
TH_OVERT#
ENERGY_DET
FAN_SPEED1
BT_ON#
E51TXD_P80DATA
E51RXD_P80CLK
ON/OFF
PWR_SUSP_LED
NUM_LED#

4

1

C351

2

EC_GA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

PLT_RST#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

EC_CRY1
EC_CRY2

4

2

C356

1000P_0402_50V7K

1

U16

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

LID_SW#/GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT#/GPIO0C

19

EC_PME#/GPIO0D

25

EC_THERM#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LED#/GPIO19

36

NUMLED#/GPIO1A

122

XCLK1

123

XCLK0

3

+3VALW

L35

1 2

FBM-L11-160808-800LMT_0603

2

C357
1000P_0402_50V7K

1

9

22

VCC

LPC & MISC

PS2 Interface

Int. K/B
Matrix

SM Bus

11

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+EC_VCCA

33

96

111

VCC

VCC

VCC

PWM Output

AD Input

DA Output

1

2

ECAGND

67

125

VCC

VCC

AVCC

INVT_PWM/PWM1/GPIO0F

BEEP#/PWM2/GPIO10

ACOFF/FANPWM2/GPIO13

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SPI Device Interface

SPI Flash ROM

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

CAPS_LED#/GPIO53

GPIO

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

VR_ON/XCLK32K/GPIO57

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

ICH_PWROK/GPXO06

GPO

GPIO

PM_SLP_S4#/GPXID1

GPI

GND

GND

GND

AGND

GND

GND

24

35

KB926QFB1_LQFP128_14X14

69

94

20mil

113

ECAGND

FBM-L11-160808-800LMT_0603

KSI[0..7]

C312

0.1U_0402_16V4Z

INVT_PWM_R

21

BEEP#

23

SPIDI/RD#

SPICS#

GPXO10
GPXO11

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

26
27

63
64
65
66
75
76

68
70
71
72

83
84
85
86
87
88

97
98
99
109

119
120
126
128

73
74
89
90
91
92
93
95
121
127

100
101
102
103
104
105
106
107
108

110
112
114
115
116
117
118

124

L36

12

ACOFF

BATT_TEMP
BATT_OVP
ADP_I
AD_BID0
VGA_PWRGD
AD_PID0

DAC_BRIG
EN_DFAN1
IREF
CALIBRATE#

EC_MUTE

BT_LED#
TP_CLK
TP_DATA

3S/4S#
65W/90W#
EC_VLDT_EN

LID_SW#

EC_SI_SPI_SO
EC_SO_SPI_SI
EC_SPICLK
EC_SPICS#/FSEL#

EC_RCIRRX

EC_I2C_INT1_R
FSTCHG
BATT_GRN_LED#
CAPS_LED#
BATT_AMB_LED#
PWR_LED
SYSON
VR_ON
ACIN

EC_RSMRST#
EC_LID_OUT#
EC_ON
EC_SWI#
EC_PWROK
BKOFF#_R
WL_OFF#

MINI1_LED#

VGATE
ENBKL
EAPD
EC_THERM#
SUSP#
PBTN_OUT#
EC_PME#

Compal Secret Data

FANPWM1/GPIO12

AD3/GPIO3B
AD4/GPIO42

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDO/WR#

SPICLK/GPIO58

CIR_RX/GPIO40

SYSON/GPIO56

AC_IN/GPIO59

EC_ON/GPXO05

EC_SWI#/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

ENBKL/GPXID2

2008/11/03 2009/11/03

3

1 2

1

C354

4.7U_0805_10V4Z

2

Deciphered Date

KSO[0..17]

R614

0_0402_5%

BEEP# <33>
FAN_PW M <35>

ACOFF <40>

C305 0.01U_0402_16V7K

BATT_OVP <40>

ADP_I <40>

VGA_PWRGD <14>

DAC_BRIG <16>
EN_DFAN1 <35>
IREF <40>
CALIBRATE# <40>

EC_MUTE <34>

MEDIA_LED#_IN <31>
EC_ACIN <14>

BT_LED# <31>
TP_CLK <31>
TP_DATA <31>

3S/4S# <40>

65W/90W# <40>

EC_VLDT_EN <32>

LID_SW# <32>

EC_SI_SPI_SO <31>

EC_SO_SPI_SI <31>
EC_SPICLK <31>
EC_SPICS#/FSEL# <31>

FSTCHG <40>

BATT_GRN_LED# <31>

CAPS_LED# <31>

BATT_AMB_LED# <31>

PWR_LED <31>

SYSON <36,42>

VR_ON <44>

ACIN <21,36,37,40>

EC_RSMRST# <20>

EC_LID_OUT# <20>

EC_ON <32>
EC_SW I# <20>
EC_PW ROK <32>

WL_OFF# <28>

MEDIA_LED#_OUT <31>

MINI1_LED# <28>

VGATE <44>
ENBKL <11,14>

EAPD <33>
EC_THERM# <21>
SUSP# <32,36,43>
PBTN_OUT# <20>
EC_PME# <26>

12

2

ECAGND

VGATE(A32)

2

For EC Tools

+3VALW

JP11

KSI[0..7] <31>

KSO[0..17] <31>

INVT_PWM <16>

BATT_TEMP <38>

Analog Board ID definition,
Please see page 3.

+3VALW

Ra

Rb

No EC change, so Keep the board ID = 0.3

15P_0402_50V8J

Title

Size Document Number Rev

Date: Sheet of

1

1

2

2

3

3

4

4

ACES_85205-0400

@

PLT_RST#

R258 100K_0402_5%

3S/4S#

VR_ON

R551 100K_0402_5%

BKOFF#_R

1 2

R288 10K_0402_5%

R524 0_0402_5%

65W/90W#

R246 100K_0402_5%

BT_ON#

R552 100K_0402_5%

R189
100K_0402_5%

1 2

AD_BID0

R187
18K_0402_5%

1 2

EC_SPICLK
EC_SPICS#/FSEL#

1

2

0.1U_0402_16V4Z

EC_CRY1 EC_CRY2

2

C358

1

X1

32.768KHZ_12.5P_MC-306

BATT_TEMP
BATT_OVP
ACIN

ON/OFF

Compal Electronics, Inc.

B

KBYF0 LA-5051P

E51RXD_P80CLK
E51TXD_P80DATA

@

1 2

@

1 2

R241 4.7K_0402_5%

1 2

Ra

C308

Rb

4

1

IN

2

C40 100P_0402_50V8J@

12

C41 100P_0402_50V8J @

12

C304 100P_0402_50V8J

12

C303 100P_0402_50V8J

12

C355 100P_0402_50V8J

12

C46 100P_0402_50V8J

12

EC ENE KB926

1

Place on RAM door

E51RXD_P80CLK <28>
E51TXD_P80DATA <28>

12

+3VALW

12

12

+3VALW

@

R203
100K_0402_5%

1 2

AD_PID0

0.1U_0402_16V4Z

2

C359
15P_0402_50V8J

1

30 46Tuesday, February 03, 2009

1

2

OUT

NC3NC

R209
100K_0402_5%

1 2

1

BKOFF# <11,16>

C317

0.3

EC_SPICS#/FSEL#<30>

+3VALW

R233 4.7K_0402_5%
R271 4.7K_0402_5%

INT_KBD Conn.

+5VALW

R446 453_0402_1%

+5VALW

R447 240_0402_5%

+5VALW

R448 453_0402_1%

+5VALW

R449 240_0402_5%

1 2

+3VALW

R273 0_0603_5%

1 2
1 2

(Left)

(Right)

1 2

1 2

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

For EMI

CP1

KSI3
KSI2

2

KSI1

3

KSI0

4 5

100P_1206_8P4C_50V8

CP2

KSO0
KSO1

2

KSO2

3

KSO3

4 5

100P_1206_8P4C_50V8

CP5

KSO8
KSO9

2

KSO10

3

KSO11

4 5

100P_1206_8P4C_50V8

CP6

KSO12
KSO13

2

KSO14

3

KSO15

4 5

100P_1206_8P4C_50V8

HT-297UD/ C B _ B L U E/ A M B _0603

HT-297UD/ C B _ B L U E/ A M B _0603

EC_SPICS#/FSEL#

81
7
6

81
7
6

81
7
6

81
7
6

A

4 3

B

2 1

LED1

A

4 3

B

2 1

LED2

SPI_WP#
SPI_HOLD#

JKB1

26

KSO0

25

KSO1

24

KSO2

23

KSO3

22

KSO4

21

KSO5

20

KSO6

19

KSO7

18

KSO8

17

KSO9

16

KSO10

15

KSO11

14

KSO12

13

KSO13

12

KSO14

11

KSO15

10

KSO16

9

KSO17

8

KSI0

7

KSI1

6

KSI2

5

KSI3

4

KSI4

3

KSI5

2

KSI6

1

KSI7

ACES_88747-2601

KSO16
KSO17

PWR_SUSP_LED#

BATT_AMB_LED#

BATT_GRN_LED#

C374 0.1U_0402_16V4Z

1 2

+SPI_VCC

U18

1

CE#

3
7
4

MX25L8005M2C-15G_SOP8

KSI[0..7]
KSO[0..17]

G2
G1

KSO4
KSO5
KSO6
KSO7

KSI6
KSI7
KSI5
KSI4

PWR_LED#

VDD

WP#

SCK
HOLD#
VSS

100P_1206_8P4C_50V8

C56 100P_0402_50V8J
C57 100P_0402_50V8J

SI

SO

28
27

CP3

2
3
4 5

CP4

2
3
4 5

100P_1206_8P4C_50V8

1 2
1 2

BATT_AMB_LED# <30>

BATT_GRN_LED# <30>

8

R269 0_0402_5%

6

1 2

R268 0_0402_5%

5

1 2

R236 0_0402_5%

2

1 2

KSI[0..7] <30>

KSO[0..17] <30>

81
7
6

81
7
6

JM70

+5VALW

+5VALW

EC_SPICS#/FSEL#
SPI_WP#
SPI_HOLD#

EC_SPICLK <30>
EC_SO_SPI_SI <30>

EC_SI_SPI_SO <30>

U19

1

CE#

3

WP#

7

HOLD#

4

VSS

MX25L1005AMC-12G_SOP8

@

Reserved for BIOS simulator.
Footprint SO8

To Media/B Conn.

CAP Sansor right

ESB_EC_CK2<30>
ESB_EC_DA2<30>

EC_I2C_INT1<30>

ESB_EC_CK2
ESB_EC_DA2

@

R563300_0402_5%

1 2

R582300_0402_5%

1 2

@

C905

33P_0402_50V8K

@

CAP Sansor lift for JM70

ESB_EC_CK2<30>
ESB_EC_DA2<30>

EC_I2C_INT2<30>

ESB_EC_CK2
ESB_EC_DA2

@

C45

100P_0402_50V8J

1

2

R587300_0402_5%

1 2

R588300_0402_5%

1 2

33P_0402_50V8K

CAP Sansor up for JV70

PWR_LED# PWR_SUSP_LED#

61

HT-297UD/ C B _ B L U E/ A M B _0603

1 2

R450 453_0402_1%

R451 240_0402_5%

R264

100K_0402_5%

A

4 3

B

2 1

LED3

JM70@

2

1 2

PWR_SUSP_LED#

Color Need ConfirmColor Need Confirm

PWR_LED#

PWR_SUSP_LED<30>PWR_LED<30>

Q20A

2N7002DW-T/R7_SOT363-6

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C907

VDD
SCK

To TP/B Conn.

+SPI_VCC

8

EC_SPICLK

6

EC_SO_SPI_SI

5

SI

EC_SI_SPI_SO

2

SO

+3VS+5VS

JP2

6

8

6

8

5

7

5

7

4

4

3

3

2

2

1

1

ACES_85201-0605
C906
33P_0402_50V8K

@

+3VS+5VS

C908
33P_0402_50V8K

R247

100K_0402_5%

1 2

CONN@

JP6

6
5
4
3
2
1

ACES_85201-0605

3

5

4

6
5
4
3
2
1

CONN@

2N7002DW-T/R7_SOT363-6

8

8

7

7

Q20B

JM70

1.HDD

3.CAP LED

4.NUM_LED

2008/11/03 2009/11/03

Compal Secret Data

Deciphered Date

100P_0402_50V8J

JV70

1.HDD

2.BT_LED2.BT_LED

4.NUM_LED

3.CAP LED

@

C42

JP13

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

G13

12

12

G14

Left Right

SW4
EVQPLHA15_4P

3
4

5

Left Right

SW1
EVQPLHA15_4P

3
4

5

JM70JM70

BTN_L

1

2

JV70

13
14

ACES_87151-1207G

TO POWER BTN/B for JV70

JP45

G1
G2

ACES_88266-02001

Need Check

To LED/B Conn.

MEDIA_LED#_IN<30>

JM70@

6

JV70@

6

1
2

1
2

3
4

+5VS

@

1

C208

0.1U_0402_16V4Z

2

TP_DATA <30>
TP_CLK <30>

BTN_R

100P_0402_50V8J

BTN_L

1
2

100P_0402_50V8J

1
2

ACES_85201-0605

MEDIA_LED#_IN

1

1

@

@

C259

C258
100P_0402_50V8J

2

2

PSOT24C-LF-T7_SOT23-3

SW5

JM70@

BTN_R

@

C43

BTN_RBTN_L

JP12

7

7

8

8

CONN@

Title

Size Document Number Rev

Custom

Date: Sheet

EVQPLHA15_4P

1
2
3
4
5
6

1

2

1
2
3
4
5
6

4

3
4

3
4

1

C915

0.1U_0402_16V4Z

2

+3VS

Y

1
2

5

6

SW2

JV70@

EVQPLHA15_4P

1
2

5

6

ON/OFFBTN# <32>

+3VS

MEDIA_LED#_OUT

5

U38

SATA_LED#

2

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5

3

Compal Electronics, Inc.

BIOS, I/O Port & K/B Connector

KBYF0 LA-5051P

TP_DATA
TP_CLK

MEDIA_LED#_OUT <30>
BT_LED# <30>
CAPS_LED# <30>
NUM_LED# <30>

3

D8

1

SATA_LED# <21>
5IN1_LED# <25>

of

31 46Tuesday, Feb ru ar y 03, 2009

2

0.3

A

ON/OFF switch

Power Button

B

C

D

E

HDA MDC Conn.

TOP Side

1 1

1 2

R11 10K_0603_5%@

1 2

R301 10K_0603_5%@

Bottom Side

EC_ON<30>

13

D

2

G

Q19

S

D14

RB751V_SOD323

R257

SUSP#

D16

ON/OFFBTN#

10K_0402_5%

180K_0402_5%

C349

1U_0805_25V4Z

10K_0402_1%

21

0.1U_0402_16V4Z

330K_0402_5%VGA@

21

RB751V_SOD323

VGA@

0.22U_0603_16V7K

VGA@

EC_ON

R249

R272

C377

C373

R196

+3VS

+3VS

12

2

1

12

2

1

2

1

ON/OFFBTN#<31> HDA_SDIN1<20>

JM70

ON/OFFBTN#

2 2

PJDLC05_SOT23~D

3 3

4 4

3
4

ON/OFFBTN#

D22

SUSP<36>

SUSP#<30,36,43>

JM70@

SW3
SMT1-05-A_4P

5

6

3

@

1

2N7002_SOT23

A

1
2

2

SUSP#

+3VALW

R194
100K_0402_5%

1 2

D12

2

1

DAN202UT106_SC70-3

1 2

2

G

3

13

D

S

2N7002_SOT23

51ON#

2

C329
1000P_0402_50V7K

1

Q15

Power ON Circuit

U21A
SN74LVC14APWLE_TSSOP14

14

P

1

O2I

G

7

+3VALW +3VALW

U21C

14

SN74LVC14APWLE_TSSOP14

P

5

O6I

G

7

+3VALW

C352

0.1U_0402_16V4Z

1 2

U21E

14

SN74LVC14APWLE_TSSOP14

P

11

O10I

G

7

B

JMDC1

1

GND1

HDA_SDOUT_MDC<20>
ON/OFF <30>
51ON# <37> HDA_BITCLK_MDC <20>

12

D13
RLZ20A_LL34

HDA_SYNC_MDC<20>

HDA_RST_MDC#<20>

EMI Notice

1 2

R281 33_0402_5%

HDA_SDIN1_MDC

HDA_SNC_MDC ,HDA_SDOUT_MDC DONT Cross Mode

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

Connector for MDC Rev1.5

IAC_BITCLK

GND13GND14GND15GND16GND17GND

18

RES0
RES1

3.3V
GND3
GND4

ACES_88018-124G

CONN@

2

R283 0_0402_5%

4
6
8
10
12

20mil

1 2

12

R280
0_0402_5%

1

C393
22P_0402_50V8J

2

JM70

CIR

IR1

Vs3OUT

1

GND

TSOP36236TR_4P

JM70@

GND

4
2

RCIRRX

1

C644
1000P_0402_50V7K

2

JM70@

+3VALW+3VALW

U21B
SN74LVC14APWLE_TSSOP14

14

P

3

O4I

G

7

EC_PWROK<30>

1 2

R254 0_0402_5%@

For South Bridge

1 2

R253 0_0402_5%

+3VALW

12

R501

100_0805_5%

JM70@

1

C645

4.7U_0805_10V4Z

SB_PWRGD <6,20>

JM70@

2

Lid Switch

U21D

14

SN74LVC14APWLE_TSSOP14

P

9

O8I

G

7

+3VALW

U21F

14

SN74LVC14APWLE_TSSOP14

P

13

O12I

G

7

For +VCCP/+1.05VS

EC_VLDT_EN<30>

EC_VLDT_EN

1 2

R250 0_0402_5%

SUSP#

R252 0_0402_5%@

R267

@

1 2

0_0402_5%

R266

1 2

0_0402_5%

VGA_ON <14>

1 2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

VLDT_EN <36,41,42>

2008/11/03 2009/11/03

(Hall Effect Switch)

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

JV70 JM 7 0

+3VALW

VDD

GND

12

R285
47K_0402_5%

LID_R

3

D31

1

C601
10P_0402_50V8J

2

Title

Size Document Number Rev

B

Date: Sheet

2

C602

1

U28

A3212ELHLT-T_SOT23W-3

JV70@

D

2

OUTPUT

1

21

CH751H-40PT_SOD323-2

Compal Electronics, Inc.

Power OK, R eset and RTC Circuit, TP
KBYF0 LA-5051P

+3VALW

For EMI

RCIRRX <30>

U31

LID_SW# <30>

E

+3VALW

1

C394
1U_0603_10V4Z

2

+3VALW

2

VDD

3

OUTPUT

GND

A3212ELHLT-T_SOT23W-3

1

JM70@

32 46Tuesday, Fe b r u a r y 03, 2009

LID_R

0.3

of

A

1 1

EC Beep

BEEP#<30>

PCI Beep

SB_SPKR<20>

C920

1U_0402_6.3V4Z

C923

1U_0402_6.3V4Z

1 2

1 2

R885

1 2

560_0402_5%

R887

1 2

560_0402_5%

B

2

+VDDA

B

12

R882
10K_0402_5%

12

R884
10K_0402_5%

1

C

Q73

E

2SC2411K_SOT23

3

1 2

C916 1U_0402_6.3V4Z

C922

MONO_IN

1 2

1U_0402_6.3V4Z

1 2

R886 2.4K_0402_1%

C

D

E

F

G

H

Codec Regulator

@

1 2

+5VS +5VAMP

L70

1 2

KC FBM-L11-201209-221LMAT_0805

L69

1 2

KC FBM-L11-201209-221LMAT_0805

4.7U_0805_10V4Z
C917

C918

0.1U_0402_16V4Z

R883 0_0805_5%

60mil 40mil

U58

1

IN

OUT

2

GND

3

SHDN

BYP

G9191-475T1U_SOT23-5

5

4

(output = 300 mA)

+VDDA

C921

12

0.22U_0402_6.3V6K

+VDDA

4.75v

C919

4.7U_0805_10V4Z

HD Audio Codec

12

D67

2 1

L77

1 2

10U_0805_10V4Z

R889

1 2

1K_0402_1%

LINE_L

MIC1_L<34>
MIC1_R<34>

1 2

1 2

B

RB751V_SOD323

1

C927

2

INT_MIC_RINT_MIC

R890

12

1K_0603_1%JM70@

R891

12

1K_0603_1%JM70@

MIC1_L

C937 4.7U_0805_6.3V6K

MIC1_R

C938 4.7U_0805_6.3V6K

12

R894 20K_0402_1%
R895 5.11K_0402_1%

EAPD<30>
SPDIF<34>

0.1U_0402_16V4Z

1

C928

2

0.1U_0402_16V4Z

1 2

C932 4.7U_0805_6.3V6K

1 2

C933 4.7U_0805_6.3V6K

1 2

C934 4.7U_0805_6.3V6KJM70@

1 2

C935 4.7U_0805_6.3V6KJM70@

+MIC2_VREFO

1 2
1 2

HDA_RST_AUDIO#<20>
HDA_SYNC_AUDIO<20>

HDA_SDOUT_AUDIO<20>

SENSE A
SENSE B

1 2

R896 0_0402_5%

1 2

R897 0_0402_5%

1

C929

2

MIC2_C_L
MIC2_C_R

MIC1_C_L
MIC1_C_R

MONO_IN

DMIC_DATA

DGND

C

40mil

+AVDD_AC97

U59

AVDD125AVDD2

14

LINE2_L

15

LINE2_R

16

MIC2_L

17

MIC2_R

23

LINE1_L

24

LINE1_R

18

LINE1_VREFO

20

LINE2_VREFO

19

MIC2_VREFO

21

MIC1_L

22

MIC1_R

12

PCBEEP_IN

11

RESET#

10

SYNC

5

SDATA_OUT

2

GPIO0/DMIC_DATA1/2

3

GPIO1/DMIC_DATA3/4

13

SENSE A

34

SENSE B

47

EAPD

48

SPDIFO1

4

DVSS1

7

DVSS2

38

ALC272-GR_LQFP48_7X7

R888

10K_0402_5%

+VDDA

FBM-L11-160808-800LMT_0603

2 2

LINE_L<34>

LINE_R<34>

3 3

LINEIN_PLUG#<34>

MIC_PLUG#<34>
HP_PLUG#<34>

R602 10K_0402_1%

Sense Pin Impedance Codec Signals

39.2K

SENSE A

20K

10K

4 4

5.1K

39.2K

SENSE B

20K

10K

5.1K

A

PORT-A (PIN 39, 41)

PORT-B (PIN 21, 22)

PORT-C (PIN 23, 24)

PORT-D (PIN 35, 36)

PORT-E (PIN 14, 15)

PORT-F (PIN 16, 17)

PORT-G (PIN 43, 44)

PORT-H (PIN 45, 46)

0.1U_0402_16V4Z

10mil

1

C924

2

10U_0805_10V4Z

1

C925

2

0.1U_0402_16V4Z

+3VS_DVDD

1

C926

2

10mil

1

1

C931

C930

0.1U_0402_16V4Z

1

9

DVDD

DVDD_IO

35

LOUT1_L

36

LOUT_R

39

LOUT2_L

41

LOUT2_R

45

SPDIFO2

BITCLK

SDATA_IN

MONO_OUT

CBP

CPVEE

HPOUT_R

CBN

VREF

JDREF

HPOUT_L

AVSS1
AVSS2

46
43

NC

44

6

8
37
29
31
28
32
30
27
40
33
26

42

DMIC_CLK1/2

DMIC_CLK3/4

MIC1_VREFO

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

10U_0805_10V4Z

2

2

AMP_LEFT
AMP_RIGHT

DEL SPDIF_HDMI

DMIC_CLKLINE_R

R892 0_0402_5%

1 2

HDA_SDIN0_AUDIO
WOOFER_MONO

10mil

HP_R

HP_L

AGND

1 2

2.2U_0603_6.3V4Z

CODEC_VREF

20K_0402_1%

1 2

R893 33_0402_5%

C939

+MIC1_VREFO_L

HP_R <34>

HP_L <34>

R898

C936

10P_0402_50V8J

1 2

2

1

10mil

C941

12

0.1U_0402_16V4Z

2008/11/03 2009/11/03

E

L76

MBK1608121YZF_0603

1 2

AMP_LEFT <34>
AMP_RIGHT <34>

+3VS

For EMI

HDA_BITCLK_AUDIO <20>

HDA_SDIN0 <20>
WOOFER_MONO <34>

C940

2.2U_0603_6.3V4Z

C939 C940 must close
codec

1

1

C942
10U_0805_10V4Z

2

2

1 2

R899 0_0805_5%

1 2

R901 0_0805_5%

1 2

R903 0_0805_5%

GND GNDA

Compal Secret Data

Deciphered Date

+MIC2_VREFO

Analog MIC for JV70

For EMI

DMIC_CLK_R

R470 FBM-11-160808-700T_0603AMIC@

DMIC_DATA_R

R471 FBM-11-160808-700T_0603AMIC@

Digital MIC for JM70

0_0603_5%

DMIC_CLK

R482
R481

1 2

R900 0_0805_5%

1 2

R902 0_0805_5%

1 2

R904 0_0805_5%

DMIC@
DMIC@

0_0603_5%

SM05T1G_SOT23-3

DMIC_CLK_R
DMIC_DATA_RDMIC_DATA

D68

@

15mil

INT_MIC

DMIC Conn.

2

3

1

+3VS

1

2

2

1

C676
220P_0402_50V8J

@

12

R472

2.2K_0402_5%

AMIC@

1

C605

AMIC@

220P_0402_50V7K

2

JP41

1

1

2

2

3

3

4

4

ACES_88266-04001

CONN@

C675
220P_0402_50V8J

@

5

G1

6

G2

GND GNDA

Title

Size Document Number Rev

B

F

Date: Sheet

Compal Electronics, Inc.

HD Audio Codec ALC268

KBYF0 LA-5051P

G

0.3

of

33 46Tuesday, Fe b r u a r y 03, 2009

H

A

B

C

D

E

Int. Speaker Conn.

+5VAMP

1 1

AMP_C_LEFT

JM70

R518

JM70@

7

RIN+

17

RIN-

9

LIN+

5

LIN-

19

SHUTDOWN

GND5

20

21

Gain = 5.1dB(BTL Mode)

R519 1.8K_0402_5%JM70@

C656 0.01U_0603_50V7KJM70@

+5VAMP

WOOFER_IN­WOOFER_IN+

1 2

C945

0.47U_0603_16V4Z

AMP_C_RIGHT

1 2

AMP_RIGHT<33>

2 2

AMP_LEFT<33>

1 2

R907 0_0402_5%

C946

0.47U_0603_16V4Z

C947

0.47U_0603_16V4Z

1 2

C948

R910 0_0402_5%

0.47U_0603_16V4Z

EC_MUTE<30>

1 2

1 2

EC_MUTE

Check with EC

3 3

+5VAMP

1

C671
10U_0805_10V4Z

2

JM70@

2

C652

0.1U_0603_25V7K

1

JM70@

Fc(high)= 482Hz

1K_0402_1%

WOOFER_MONO<33>

4 4

WOOFER_MONO

0.33U_0603_16V4Z

A

JM70@

1 2

C654

R517

1 2

JM70@

C651

0.068U_0603_16V7K

1 2

4.7K_0402_1%

1

JM70@

2

2

C606

2.2U_0603_6.3V4Z

1

JM70@

JONS

C943

10U_0805_10V4Z

15

6

16

VDD

PVDD1

PVDD2

GAIN0
GAIN1

ROUT+

ROUT-

LOUT+

LOUT-

NC

BYPASS

GND41GND311GND213GND1

TPA6017A2PWP_TSSOP20

Fc(low)= 2KHz

1 2

1 2

U43

6

VDD

SHUTDOWN#

4
3
2

Vo+

IN-

Vo-

IN+

GND

BYPASS

APA3011XA-TRL_MSOP8

JM70@

B

1

2

U60

GAIN0

2

GAIN1

3

SPKR+

18

SPKR-

14

SPKL+

4

SPKL-

8

12
10

1
5
8
7

1

C944

0.1U_0402_16V4Z

2

R905

100K_0402_5%

1 2

1 2

R908

100K_0402_5%

Keep 10 mil width

2

C950

0.47U_0603_16V4Z

1

EC_MUTE

WOOFER+
WOOFER-

30mil

JONS

+5VAMP

R906
100K_0402_5%

@

1 2

+5VSPDIF

R909
100K_0402_5%

1 2

@

HP_R

HP_R<33>
HP_L<33>

LINE_R<33>
LINE_L<33>

R467

100K_0402_5%

1 2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+5VAMP

EC_MUTE <30>

1
2

3
4

ACES_88266-02001

CONN@

C

JP17

1
2

G1
G2

MIC1_R<33>
MIC1_L<33>

2008/11/03 2009/11/03

1 2

R633 56.2_0603_1%

HP_L HPOUT_L_1

1 2

R634 56.2_0603_1%

LINE_R
LINE_L

MIC2_R_1
MIC2_L_1

3

@

SM05_SOT23

D69

1 2

R911 1K_0603_1%

1 2

R912 1K_0603_1%

Compal Secret Data

20mil

SPKL+

R619 0_0603_5%

SPKL­SPKR+
SPKR-

S

1 2

G

2

D

Q39

1 3

AO3413_SOT23-3

HPOUT_R_1 HPOUT_R_2

1 2

L62 FBM-11-160808-700T_0603

1 2

L63 FBM-11-160808-700T_0603

SPDIF<33>

Left

2

RB751V-40TE17_SOD323-2

1

MIC1_R_L

1 2

MIC1_L_L

1 2

1 2

R618 0_0603_5%

1 2

R617 0_0603_5%

1 2

R616 0_0603_5%

1 2

R625
100K_0402_5%

SPDIF_PLUG#

20mil

C759

330P_0402_50V7K

HPOUT_L_2

+MIC1_VREFO_L +MIC1_VREFO_L

D28

R645

2.2K_0402_5%

L65 FBM-11-160808-700T_0603
L66 FBM-11-160808-700T_0603

C770

220P_0402_50V7K

Deciphered Date

D

+5VAMP+5VAMP

1 2
13

D

2

G

Q40

S

2

330P_0402_50V7K

1

SPDIF

C762

100P_0402_50V8J

LINEIN_PLUG#<33>

1 2

L64 FBM-11-160808-700T_0603JM70@

1 2

L44 FBM-11-160808-700T_0603JM70@

220P_0402_50V7K

1 2
12

1

220P_0402_50V7K

2

3

1

@

HP_PLUG#

1
2
3
4

2

ACES_88266-04001

CONN@

JP3

1
2
3
4

5

G1

6

G2

HP_PLUG# <33>

SM05_SOT23

D70

R626
100K_0402_5%

2N7002_SOT23

SPK_L+
SPK_L­SPK_R+
SPK_R-

2

3

SM05_SOT23

D71

1

@

13

D

2

G

Q38

S

2N7002_SOT23

LINE Out/Headphone Out

2007/12/07

2

C760

1

3

SM05_SOT23

D65

@

1

2

1

C763

2

JM70@

R647

2.2K_0402_5%

C771

C949

1 2

0.1U_0402_16V4Z

2

SPDIF_PLUG#

1

+5VSPDIF

JM70

LINEIN_PLUG#

LINE_R_R
LINE_L_R

1

220P_0402_50V7K

2

JM70@

D29

RB751V-40TE17_SOD323-2

1 2
12

MIC_PLUG#<33>

MIC2_R_1
MIC2_L_1

1

2

Title

Size Document Number Rev

B

KBYF0 LA-5051P

Date: Sheet

S/PDIF Out JACK

@

2

D60

D61

C764

SM05_SOT23

D66

Compal Electronics, Inc.

Amplifier & Audio Jack

1

3

PJDLC05_SOT23~D

JHP1

1

1

2

2

3

3

4

4

5

5

8

8

DRIVE

9

IC

9

10

10

SINGA_2SJ-A373-H01

CONN@

LINE-IN JACK

2

1

3

2

3

1

@

D72

2
3

MIC_PLUG#

5
4
3

6
2
1

5
4
3

6
2
1

E

6

GND

7

GND

PJDLC05_SOT23~D@

JLINE1

SINGA_2SJ-S351-015

JM70@

MIC JACK

PJDLC05_SOT23~D@

1

JMIC1

SINGA_2SJ-S351-015

of

34 46Tuesday, Fe b r u a r y 03, 2009

0.3

H1

H_3P0

H5

H3

H2

H_3P0

@

1

@

1

H_3P0

H4

H_3P0

@

@

1

1

H_3P0

H6

H_3P0

@

1

H7

H_3P0

@

1

@

1

H8

H_3P0

H9

H_3P0

@

@

1

1

30>

EN_DFAN1

EN_DFAN1

+VCC_FAN1

R815

1 2

330_0402_5%

+5VS

EN_FAN1_R

12

C769

0.047U_0402_16V7K

FAN_SPEED1<30>

C435 10U_0805_10V4Z

1 2

U26

1

VEN

2
3
4

GND

VIN

GND
GND

VO

GND

VSET

G990P11U_SOP8

FAN1 Conn

8
7
6
5

+3VS

12

R310
10K_0402_5%

1

C411
1000P_0402_50V7K

2

FAN_PWM<30>

R355 close to JP32

40mil

+VCC_FAN1

R346 0_0603_5%

1 2

0_0603_5%

R355

@

+5VS

1 2

12

D19
1SS355_SOD323-2

D20

1 2

BAS16_SOT23-3
C429

10U_0805_10V4Z

1 2

C425

1000P_0402_50V7K

1 2

Change to SC1BAS16000

JP32

1
2
3

ACES_85205-03001

CONN@

H10

H_3P0

H17

H_3P2

H40

H_3P2

H19

H_4P2

H12

H11

H_3P0

H_3P0

@

1

1

1

1

@

1

H18

H_3P2

@

@

1

H41

H_3P2

@

@

1

H20

H21

H_4P2

H_4P2

@

@

1

1

H23

H_3P2

H35

H_3P2

@

1

@

1

1

@

@

H22

H_4P2

H_3P0

1

H29

1

H26

H_3P2

H38

H_3P2

@

H42

H_3P0

@

@

1

H25

H32

H_3P2

H_3P2

@

1

1

@

1

H39

H_3P2

@

@

1

H27

H_3P2

@

1

@

1

H28

H31

H_4P1X4P6N

H_4P1N

@

@

1

1

FD1

@

1

FIDUCIAL_C40M80

FD5

FIDUCIAL_C40M80

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/03 2009/11/03

@

1

FIDUCIAL_C40M80

FIDUCIAL_C40M80

Compal Secret Data

H43
H_10P0N

FD2

@

1

FD6

@

1

Deciphered Date

@

1

FD3

1

FIDUCIAL_C40M80

FD4

@

FIDUCIAL_C40M80

@

1

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

FAN & Screw Hole

KBYF0 LA-5051P

0.3

of

35 46Tuesday, Feb ru ar y 03, 2009

A

B

C

D

E

+5VALW TO +5VS

+5VALW

U15

8

S

D

7

S

D

6

S

D

5

1

1

C310

C309

1 1

10U_0805_10V4Z

+VSB

2

10U_0805_10V4Z

R212
200K_0402_5%

SUSP

2N7002_SOT23

ACIN<21,30,37,40>

2

12

2

Q14

G

Q43
2N7002_SOT23

@

ACIN

D

AO4468_SO8

5VS_GATE

13

D

S

2

G

G

R541

@

1 2

1M_0402_5%

13

D

S

+3VALW TO +3VS

+3VALW

2 2

1

C376

C375
10U_0805_10V4Z

2

10U_0805_10V4Z

1

C286

C285

10U_0805_10V4Z

2

10U_0805_10V4Z

3 3

+VSB

R424
510K_0402_5%

SUSP

Q45
2N7002_SOT23

U22

8

S

D

7

S

D

6

S

D

5

1

2

+1.8V to +1.8VS

+1.8V

1

2

12

2

G

Q51
2N7002_SOT23

ACIN

8
7
6
5

1.8VS_GATE

13

D

S

G

D

AO4468_SO8

U11

S

D

S

D

S

D

G

D

SI4856ADY_SO8

AO4430

1 2

1M_0402_5%

13

D

2

G

S

R542

1
2
3
4

1
2
3
4

1
2
3
4

+5VS

C318
10U_0805_10V4Z

1

C328

0.1U_0603_25V7K

2

+3VS

C391
10U_0805_10V4Z

+1.8VS

C269
10U_0805_10V4Z

1

C564

0.1U_0603_25V7K

2

1

2

1

2

1

2

1

C314

2

1U_0603_10V4Z

1

C388

2

1U_0603_10V4Z

1

C270

2

1U_0603_10V4Z

D

S

D

S

D

S

R193

470_0603_5%

1 2
13

2

G

Q13

2N7002_SOT23

R277

470_0603_5%

1 2
13

2

G

Q25

2N7002_SOT23

R163
470_0603_5%

1 2
13

2

G

Q37
2N7002_SOT23

SUSP

SUSP5VS_GATE

SUSP

+VSB

C14

10U_0805_10V4Z

R306
150K_0402_5%

VLDT_EN#

2N7002_SOT23

+1.2VALW

1

2

12

2

G

Q27

ACIN

Q58
2N7002_SOT23

8
7
6
5

13

D

S

U1

S

D

S

D

S

D

G

D

SI4856ADY_SO8

AO4430

1.2V_GATE

R543

1 2

1M_0402_5%

13

D

2

G

S

+1.2V_HT

1
2
3

C16

4

10U_0805_10V4Z

1

C407

0.1U_0603_25V7K

2

1

2

1

C15

2

1U_0603_10V4Z

SUSP<32>

100K_0402_5%

10K_0402_5%

R186

10K_0402_5%

SYSON#

SYSON

R171

SUSP

R275

VLDT_EN#

SYSON#<24,29,43>

SYSON<30,42>

SUSP#<30,32,43>

R10

470_0603_5%

1 2
13

D

VLDT_EN#

2

G

Q26

S

2N7002_SOT23

VLDT_EN<32,41,42>

+5VALW

R177
100K_0402_5%

1 2

13

D

Q11

2

2N7002_SOT23

G

S

12

+5VALW

R276
100K_0402_5%

1 2

13

D

Q24

2

2N7002_SOT23

G

S

12

+5VALW

R191
100K_0402_5%

1 2

13

D

Q12

2

2N7002_SOT23

G

S

12

+1.5VS +2.5VS +1.8V+0.9V

R270
470_0603_5%

4 4

1 2
13

D

SUSP SUSP SYSON# SYSON#

2

G

Q22

S

2N7002_SOT23

R423
470_0603_5%

1 2
13

D

2

G

Q44

S

2N7002_SOT23

A

+1.1VS

D

S

R544
470_0603_5%

1 2
13

2

G

Q57
2N7002_SOT23

VLDT_EN#

D

S

R170
470_0603_5%

1 2
13

2

G

Q10
2N7002_SOT23

B

D

S

R173
470_0603_5%

1 2
13

2

G

Q9
2N7002_SOT23

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/11/03 2009/11/03

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

DC Interface

KBYF0 LA-5051P

of

36 46Tuesday, Fe b r u a r y 03, 2009

E

0.3

A

B

C

D

1 1

PL1

SINGA_2DC-G756I200

1

2

G
G

3

PJP1

2 2

DC_IN_S1

12

PC1
1000P_0402_50V7K

SMB3025500YA_2P

1 2

12

PC2

100P_0402_50V8J

12

1000P_0402_50V7K

RTC Battery

PBJ1

-+

MAXEL_ML1220T10@

12

+RTCBATT

PC3

+RTCBATT

12

PC4

100P_0402_50V8J

VIN

10K_0402_5%

ACIN <21,30,36,40>

1 2

PR4

0_0402_5%

PR2

@

12

PR710K_0402_5%

12

12

PD3
RLZ4.3B_LL34

PR197

10K_0402_1%

1 2

Min. Typ Max.
H-->L 16.976V 17.525V 17.728V
L-->H 17.430V 17.901V 18.384V

PR1

1M_0402_1%

1 2

1

0

PU1A

LM358DT_SO8

Vin Dectector

PC5

0.1U_0603_25V7K

1 2

PR8

10K_0402_5%

12

VINVIN

12

12

PR3

84.5K_0402_1%

12

PR6

20K_0402_1%

RTCVREF

PC6
1000P_0402_50V7K

VS

8

P

G

4

PR5
22K_0402_5%

1 2

3

+

2

-

SP093MX0000

VIN

+3VALWP +3VALW

(8.61A,400mils ,Via NO.= 20)

PD4
RLS4148_LL34-2

3 3

560_0603_5%

+CHGRTC

4 4

PR15

1 2

51ON#<32>

BATT+

CHGRTCP

PR16

560_0603_5%

1 2

RLS4148_LL34-2

PD5

PR11

200_0603_5%

1 2

100K_0402_1%

1 2

PR13

22K_0402_1%

RTCVREF

3.3V

12

12

12

PR12

PU2 G920AT24U_SOT89-3

3

OUT

PC9
10U_0805_10V4Z

TP0610K-T1-E3_SOT23-3

N1

12

PC7

0.22U_0603_25V7K

IN

GND

1

2

PQ1

N2

2

12

PR14
200_0603_5%

12

PC10

1U_0805_25V4Z

PR9

68_1206_5%

13

1 2

12

12

PR10
68_1206_5%

12

PC8

0.1U_0603_25V7K

VS

+5VALWP

+VSBP +VSB

(120mA,40mils ,Via NO.= 2)

+1.2VALWP +1.2VALW

(3.94A,160mils ,Via NO.=8)

+NB_COREP +NB_CORE

(8.8A,360mils ,Via NO.=18)

PJ2

2

112

JUMP_43X118@

PJ4

2

112

JUMP_43X118@

PJ6

2

112

JUMP_43X39 @

+5VALW

+1.8VP +1.8V

(12.06A,480mils ,Via NO.=24)

(1.9A,80mils ,Via NO.=4)

PJ8

2

112

JUMP_43X118@

(1.0A,40mils ,Via NO.=2)

PJ10

2

112

JUMP_43X118@

(1.0A,40mils ,Via NO.=2)

PJ3

2

112

JUMP_43X118@

PJ5

2

112

JUMP_43X79@

(2A,80mils ,Via NO.= 4)(8.61A,400mils ,Via NO.= 20)

PJ7

2

112

JUMP_43X118@

PJ9

2

112

JUMP_43X118@

PJ11

2

112

JUMP_43X118@

+0.9V+0.9VP

+1.1VS+1.1VSP

+2.5VS+2.5VSP

1 2

+1.5VS+1.5VSP

PC172

0.1U_0402_25V6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

2009/11/032008/11/03

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DCIN & DETECTOR

KBKC0_KBYF0

D

37

0.3

46Tuesday, February 03, 2009

of

A

B

C

D

PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C

PH1

PC14

0.22U_0603_16V7K

12

VL

12

0.1U_0603_25V7K

12

PR22

PR19

8.87K_0402_1%

1 2

10.7K_0402_1%

PC11

TM_REF1

12

PC15

1000P_0402_50V7K

SUYIN_200275MR007G161ZL

1 1

PJP2

1
2
3

EC_SMCA

4

EC_SMDA

5
6
7
8
9

PR20

100_0402_1%

PR21
100_0402_1%

1 2

1 2

12

PR26
1K_0402_1%

PR24

6.49K_0402_1%

12

VMB

SMB3025500YA_2P

12

PC12
1000P_0402_50V7K

PL2

1 2

+3VALWP

BATT+

12

PC13

0.01U_0402_25V7K

100K_0603_1%_TH11-4H104FT

12

12

PR25
100K_0402_1%

VL

47K_0402_1%

1 2

8

PU3A

3

P

+

2

-

G

LM393DG_SO8

4

PR23

100K_0402_1%

PR18

O

12

VL

PR17
47K_0402_1%

1 2

PD6

2

1

RLS4148_LL34-2

VL

12

13

PQ2
DTC115EUA_SC70-3

MAINPWON <6,39>

2 2

TP0610K-T1-E3_SOT23-3

B+

3 3

VL

PR33

100K_0402_1%

POK<39,41>

1 2

1 2

PR34
0_0402_5%

12

2

G

PC19

0.1U_0402_16V7K

@

22K_0402_1%

13

D

S

12

PR31

1 2

PQ4
SSM3K7002F_SC59-3

PR29

12

PC16

100K_0402_1%

@

0.22U_0603_25V7K

PQ3

2

BATT_TEMP <30>

EC_SMB_CK1 <6,14,30>

EC_SMB_DA1 <6,14,30>

13

12

PC17

0.1U_0603_25V7K

@

+VSBP

PH2 near main Battery CONN :

BAT. thermal protection at 92 degree C
Recovery at 56 degree C

VL

12

PH2

100K_0603_1%_TH11-4H104FT

0.22U_0603_16V7K

@

PR30

@

12K_0402_1%

1 2

12

12

PC18

@

PR32
12K_0402_1%

TM_REF1

@

PR28

@

100K_0402_1%

1 2

VL

8

5

+

6

-

4

PU3B

P

7

O

G

LM393DG_SO8

VL

1 2

PR27

@

100K_0402_1%

PD7

@

RLS4148_LL34-2

12

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

2009/11/032008/11/03

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

BATTERY CONN / OTP

KBKC0_KBYF0

D

38 46T u e s day, February 03, 2009

0.3

of

5

4

3

2

1

ISL6237_B+

12

12

PC24

PC23

4.7U_1206_25V6K

4.7U_1206_25V6K

10UH_MSCDRI-104A-100M-E_4.6A_20%

12

4.7_1206_5%

12

680P_0603_50V7K

PL3

12

PC25

2200P_0402_50V7K

12

PR41

61.9K_0402_1%

1 2

PR43

1 2

10K_0402_1%

+5VALWP

1

+

PC35
330U_6.3V_M

2

12

12

1 2

MAINPW O N<6,38>

ISL6237_B+

3 6

241

3 6

241

PR46

100K_0402_1%

PR47

2

PQ38

578

PQ5

AO4466_SO8

578

PQ7
AO4712_SO8

1 2

200K_0402_5%

PR54

0_0402_5%

1 2

VL

1 2

12

1 3

PC31

0.1U_0603_25V7K

1 2

PC37

0.22U_0603_25V7K

PR52

806K_0603_1%

12

PR35

0_0805_5%

1 2

0.1U_0603_25V7K

DH3

PR38

BST3A

12

2.2_0603_5%

LX3

FB3

VL

2VREF_ISL6237

1 2

PC36 0.22U_0603_10V7K

PR50

@

0_0402_5%

1 2

PR55

@

47K_0402_5%

1 2

12

PC38

PC39

0.047U_0402_16V7K

0.047U_0402_16V7K

@

DL3

PC26

33
26
24

25

23

30

32

20

14

27

PR51

1 2

2VREF_ISL6237

1 2

PU4

TP
UGATE2
BOOT2

PHASE2

LGATE2

OUT2

REFIN2

1

REF

8

LDOREFIN

NC

4

EN_LDO

EN1

EN2

0_0402_5%

PC163

1U_0603_6.3V6M

6

5

12

VIN

NC

1 2

PC27

3

VCC

TON

2

12

PR53
0_0402_5%

2VREF_ISL6237

VL

12

PC28

1U_0603_10V6K

7

19

LDO

PVCC

15

UGATE1

17

BOOT1

16

PHASE1

18

LGATE1

22

PGND

10

OUT1

11

FB1

9

BYP

29

SKIP

28

POK2

13

POK1

12

ILIM1

31

ILIM2

GND

ISL6237IRZ-T_QFN32_5X5

21

4.7U_0805_6.3V6K

DH5

BST5A

LX5

DL5

FB5

ILM1

ILIM2

578

PQ6

AO4466_SO8

3 6

241

PC29

1U_0603_10V6K

1 2

PR39

2.2_0603_5%

0.1U_0603_25V7K

PC32

PR44 0_0402_5%@

PR45 0_0402_5%

1 2

12

AO4712_SO8

1 2

12

PR48

330K_0402_1%

PR49

330K_0402_1%

578

PQ8

PR37

3 6

241

PC34

VL

POK <38,41>

12

12

+5VALWP Ipeak=8.444A ; Imax=5.91A
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(5E-06 * 330K)/10=165mV
Ilimit=165mV/18m ~ 165mV/15m
=9.167A ~ 11A
Iocp=Ilimit+Delta I/2
=9.7285A ~ 11.5615A
Delta I=1.123A (Freq=400KHz)

B+

PL15

FBMA-L11-322513-151LMA50T_1210

12

+

1 2

PC171

0.1U_0402_25V6

PR40

0_0402_5%

1 2

PR42

10K_0402_1%

1 2

@

1SS355_SOD323-2

12

12

12

PC21

PC20

4.7U_1206_25V6K

PL4

10UH_MSCDRI-104A-100M-E_4.6A_20%

1 2

VS

PD12

4.7U_1206_25V6K

PD8

RLZ5.1B_LL34

1 2

12

PC22

2200P_0402_50V7K

PR36

4.7_1206_5%

PC33

680P_0603_50V7K

TP0610K-T1-E3_SOT23-3

D D

+3VALWP

1

PC30

330U_6.3V_M

C C

B B

+3.3VALWP Ipeak=8.444A ; Imax=5.91A

A A

Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)

2

Vlimit=(5E-06 * 330K)/10=165mV
Ilimit=165mV/18m ~ 165mV/15m
=9.167A ~ 11A
Iocp=Ilimit+Delta I/2
=9.721A ~ 11.554A
Delta I=1.108A (Freq=300KHz)

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/03 2009/11/03

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

2

Date: Sheet of

+5V/+3V

KBKC0_KBYF0

Tuesday, February 03, 2009

1

0.3

39 46

A

PQ9

VIN

12

PR58

1 1

3.3_1210_5%

PR182

3.3_1210_5%

12

12

PC50

2.2U_0805_25V6K

Icharge=(Vsrset/Vvdac)*(0.1/PR36)
90W adapter
Iadapter=(Vacset/Vvdac)*(0.1/PR48)=4.04A

8
7

5

PR60
340K_0402_1%

1 2

ACDET

PR64

54.9K_0402_1%

1 2

AO4407A_SO8

4

1
2
36

1 2

PQ10

AO4407A_SO8

1
2
3 6

4

12

PC44

PR59

100K_0402_1%

0.01U_0402_25V7K

PD13

@

1 2

RLZ24B_LL34

65W adapter
Iadapter=(Vacset/Vvdac)*(0.1/PR48)=2.90A
Input OVP : 22.3V
Input UVP : 17.26V
Fsw : 300KHz

2 2

24751_VREF

PR69
47K_0402_1%

1 2

13

D

S

G

GND

CELLS

VREF

1 2

PR70 0_0402_5%@

CELLS

2

PQ15
SSM3K7002F_SC59-3

3 Cell
4 Cell

3S/4S# <30>

Cells selector

3 3

LI-3S :13.5V----BATT-OVP=1.5V
LI-4S :18V----BATT-OVP=1.998V
BATT-OVP=0.111*BATT+

PR63

64.9K_0402_1%

24751_VREF

4 4

65W/90W#<30>

1 2

PR183

100K_0402_1%

PQ37

SSM3K7002F_SC59-3

2

G

ACSET

12

12

PR66
100K_0402_1%

13

D

S

PR67
340K_0402_1%

1 2

PR68

54.9K_0402_1%

1 2

100K_0402_1%

PQ14_GATE

PC62

0.1U_0603_25V7K

ACGOOD#

PC168

ACOFF

1 2

0.1U_0402_16V7K

BATT_OVP<30>

Charger ADJ Calibrate#

PR71

1 2

2

12

1 3

ACSET

RTCVREF

24751_VREF 24751_VREF

12

PR194

100K_0402_1%

13

D

2

G

S

12

PQ40

PR195

340K_0402_1%

SSM3K7002F_SC59-3

PR79

10K_0402_1%

1 2

PQ14
SI2301BDS-T1-E3_SOT23-3

1 2

PR72

100K_0402_1%

PR196

200K_0402_1%

4.0V L

CP setting

A

4.1V

4.2V

L

H

B

0.015_2512_1%

8
7

1

5

2

0.1U_0402_16V7K

1 2

12

PC47

0.1U_0603_25V7K

24751_VREF

PC61

1U_0603_10V6K

12

13

D

2

G

S

PU1B

7

LM358DT_SO8

PR80 PR85

@0

887K 221K

887K 221K

B

PR56

4
3

PC46

12

ACN
ACP

ACDRV

ACSET

1 2

PC57

0.47U_0603_16V7K

OVPSET

24751_VREF

12

VADJ

/BATDRV

PQ14_GATE

PQ39
SSM3K7002F_SC59-3

8

P

+

0

-

G

4

C

PC173

12

PJ13

2

112

JUMP_43X118@

1 2

PC51

0.1U_0603_25V7K

ACOFF <30>

ICHG setting

12

PR74
100K_0402_1%

CHG_B+

578

3 6

241

578

3 6

241

PR73

17.4K_0402_1%

12

PC64

0.01U_0402_25V7K

@

PC174

0.1U_0402_25V6

1 2

PC42

4.7U_1206_25V6K

PQ11
AO4466_SO8

10UH_PCMB104T-100MS_6A_20%

PQ13
AO4466_SO8

12

CHGEN#

PU5

1

CHGEN

PC49

0.1U_0603_25V7K

@

2

ACN

3

ACP

4

ACDRV

5

ACDET

6

ACSET

7

ACOP

8

OVPSET

9

AGND

10

VREF

11

VDAC

12

VADJ

13

ACGOOD

14

BATDRV

BQ24751ARHDR_QFN28_5X5

PVCC

BTST

HIDRV

PH

REGN

LODRV

PGND

LEARN

CELLS

SRP
SRN

BAT

TP

SRSET

IADAPT

PVCC

28

BTST

27

DH_CHG

26

LX_CHG

25

REGN

24

12

PC55
1U_0603_10V6K

DL_CHG

23

22

21

CELLS

20

SE_CHG+

19

SE_CHG-

18
17

12

29

SRSET

16

PR76
10_0603_5%

1 2

15

PC65

100P_0402_50V8J

B+

0.1U_0402_25V6

PC48

0.1U_0603_25V7K

1 2

PR61

2.2_0603_5%

1 2

PD10

12

RLS4148_LL34-2

PC63

0.1U_0603_25V7K

12

VMB

PC66

0.01U_0402_25V7K

12

PR77

340K_0402_1%

12

PR78

499K_0402_1%

12

PR81

105K_0402_1%

12

PC67

VS

12

5
6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Calibrate#<30>

0.01U_0402_25V7K

ADP_I <30>

REGN

PR84

100K_0402_1%

Compal Secret Data

@

0_0402_5%

1 2

12

2

G

Deciphered Date

C

PR188

S

D

13

G

PQ17

2

SI2301BDS-T1-E3_SOT23-3

13

D

PQ19
RHU002N06_SOT323-3

S

PR82

1 2

0_0402_5%

12

1 2

PC43

1 2
12

PR65

4.7_1206_5%

12

PC56

680P_0603_50V8J

IREF <30>

2009/11/032008/11/03

1 2

4.7U_1206_25V6K

PL5

12

24751_VREF

12

PR189

4.3K_0402_5%

@

PC40

0.01U_0402_25V7K

PC45

/BATDRV

2200P_0402_25V7K

1
2

12

PC169

10U_1206_25V6M

0.1U_0402_16V7K

PC59

0.1U_0603_25V7K

CC=0.2~4.26A
Iref=0.77448*Icharge
Iref=0.155~3.3V

12

PR80

887K_0402_1%

VADJ

12

PR85

221K_0402_1%

PR62

0.02_2512_1%

PC58

1 2

1 2

4
3

FSTC HG<30>

Title

Size Document Number Rev

Date: Sheet

D

12

PR57
100K_0402_1%

36

241

PQ12
AO4407A_SO8

578

BATT+

12

12

PC53

PC52

10U_1206_25V6M

10U_1206_25V6M

12

PC60

0.1U_0603_25V7K

@

24751_VREF

@

PR75

100K_0402_1%

ACGOOD#

2

G

24751_VREF

2

G

1 2

13

D

PQ16
SSM3K7002F_SC59-3

@

S

PR83
100K_0402_1%

1 2

13

D

PQ18
SSM3K7002F_SC59-3

S

Compal Electronics, Inc.

CHARGER

KBKC0_KBYF0

D

40 46T u e s day, February 03, 2009

ACIN <21,30,36,37>

CHGEN#

0.3

of

A

B

C

D

POWER_SEL

HIGH 1.0V

1.1VLOW

1 1

PR91

@

0_0402_5%

POWER_SEL<11>

2 2

+1.1V

+NB_COREP

PC83

330U_D2E_2.5VM

3 3

VLDT_EN<32,36,42>

1 2

PC73

@

0.01U_0402_25V7K

PR99

1 2

7.87K_0402_1%

PC80

0.022U_0402_16V7K

1 2

PL7

1 2

1.2UH_1164AY-1R2N=P3_9.8A_30%

1

+

2

47K_0402_1%

4.7_1206_5%

680P_0603_50V8J

PR111

12

12

PQ21

@

SSM3K7002F_SC59-3

12

2

G

PC76

1000P_0402_25V8J

12

PQ22

AO4466_SO8

PR104

7.87K_0402_1%

1 2

12

PR106

12

PC85

NB_COREP_EN

PC90

0.1U_0402_10V7K

1 2

PR98

90.9K_0402_1%

PR87

@

10K_0402_1%

13

D

S

PR96

3.3K_0402_5%

12

578

3 6

241

8

D6D5D7D

G

S

S

S

3

2

1

+5VALW

12

@

0_0402_5%

1 2

@

0.1U_0402_16V7K

ISL6228_B+

12

PC78

PQ24
FDS6670AS_NL_SO8

4

0.1U_0402_16V7K

PR90

PC72

4.7U_1206_25V6K

PC86

1 2

12

PC79

12

LG_NB_COREP

FB1_NB_COREP

@

12K_0402_1%

1 2
13

D

2

G

S

12

PR97

102K_0402_1%

FB1_NB_COREP

4.7U_1206_25V6K

NB_COREP_EN

LX_NB_COREP

UG_NB_COREP

BST_NB_COREP

12

PR108

2.2_0603_5%

PR86

PQ20

@

SSM3K7002F_SC59-3

ISL6228_B+ ISL6228_B+

1000P_0402_50V7K

8

FB1

9

VO1

10

OCSET1

11

EN1

12

PHASE1

13

UGATE1

14

BOOT1

PC91

1U_0402_6.3V6K

PC68

PR88

12

12

12

5

4

VIN1

VCC1

PU6

1U_0402_6.3V6K

+5VALW +5VALW

PC74

7

PGOOD1

PVCC115LGATE116PGND117PGND218LGATE219PVCC220BOOT2

1 2

2.2_0603_1%

PC70

0.1U_0603_25V7K

PR92

12

10_0603_1%

12

PR94
22K_0402_1%

1 2

6

FSET1

ISL6228HRTZ-T_QFN28_4X4

PC69

12

1U_0402_6.3V6K

PR89

1 2

2.2_0603_1%

12

1000P_0402_50V7K

2

3

VIN2

VCC2

1 2

0.1U_0603_25V7K

PC75

+5VALW+5VALW

PC92
1U_0402_6.3V6K

PC71

PR93

10_0603_1%

12

1

GND_T

FSET2

PGOOD2

FB2

VO2

OCSET2

EN2

PHASE2

UGATE2

21

BST_1.2V

12

PR95

18.2K_0402_1%

1 2

29

28

27

26

25

24

23

22

PR112

1 2

2.2_0603_5%

FB2_1.2V

1.2V_EN

UG_1.2V

B+ ISL6228_B+

1

12

+

PC164

220U_25V_M

8
7
6
5

LX_1.2V

PC89

1 2

0.1U_0402_16V7K

AO4932_SO8

G2
S2/D1
S2/D1
S2/D1

LG_1.2V

2

PQ23

D2
D2
G1
S1

1
2
3
4

PC170

0.1U_0402_25V6

66.5K_0402_1%

ISL6228_B+

PL14

HCB4532KF-800T90_1812

1 2

PR100

12

PC81

12

12

1 2

12

PC84

4.7U_1206_25V6K

PR110

4.7_1206_5%

PC88

680P_0603_50V8J

PR101

3.3K_0402_5%

4.7U_1206_25V6K

1 2

1.8UH_1164AY-1R8N=P3_9.5A_30%

1000P_0402_25V8J

12

PR102

1 2

71.5K_0402_1%
PR103

1 2

8.06K_0402_1%

PC82

0.022U_0402_16V7K

1 2

PR107

8.06K_0402_1%

PL8

1 2

PC77

1 2

330U_6.3V_M

PC87

1.2VP Ipeak=3.94A ; Imax=2.758A

+1.2VALWP

1

+

2

DCR=10m ohm (max)

1.1VP Ipeak=8.9A ; Imax=6.23A
DCR=6m ohm (max)
Rocset=(Iocp*DCR)/10E-06=7.68K ohm

POK<38,39>

Iocp=9.846A(1.3*DCR)

4 4

Csen=L/(Rocset*DCR)=0.022uF

PR114
0_0402_5%

12

1.2V_EN

12

@

PC93

0.01U_0402_25V7K

Rocset=(Iocp*DCR)/10E-06=6.65K ohm
Iocp=5.542A(1.2*DCR)
Csen=L/(Rocset*DCR)=0.027uF

Freq=366KHz
Rfset=1/(1.5E-10 * Freq)=18.2K

Freq=303KHz
Rfset=1/(1.5E-10 * Freq)=22K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

2009/11/032008/11/03

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

NB_COREP / 1.2VSB

KBKC0_KBYF0

D

41 46T u e s day, February 03, 2009

0.3

of

5

4

3

2

1

PC95

4.7U_1206_25V6K

+1.1VSP

PJ14

2

JUMP_43X118@

112

1

+

PC98
330U_6.3V_M

2

B+

+1.8VP

51117_B+

D D

PR115

200K_0402_5%

1 2

PR116

0_0402_5%

1 2

SYSON<30,36>

C C

VFB=0.75V
Vo=VFB*(1+PR120/PR121)=1.8V
Ton=19E-12*Ron*(((2/3)*Vo+100mV)/Vin)+50ns=3.1E-07
Freq=305KHz

Cesr=15m ohm

B B

Ipeak=12.6A Imax=8.82A
Delta I=((19-1.8)*(1.8/19))/(L*Freq)=5.332A
Vtrip=Rtrip*10uA=0.24V
Iocp-min=Vtrip/Rdsonmax*1.4+2.666=17.573A
Iocp-max=Vtrip/Rdsontyp*1.2+2.666=26.908A
Iocp=17.573~26.908A

+5VALW

PR187

47K_0402_5%

PR118
0_0603_1%

1 2

1U_0603_10V6K

12

PC101

12

PC97

0.1U_0402_16V7K

@

12

PC99

@

47P_0402_50V8J

1 2

PR120

14K_0402_1%

1 2

12

PR121
10K_0402_1%

VLDT_EN<32,36,41>

PU7

2

TON

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

VLDT_EN

BST_1.8V

15

14

1

TP

EN_PSV

GND7PGND

TPS51117RGYR_QFN14_3.5x3.5

8

PR122

@

0_0402_5%

1 2

PC106

@

1U_0603_10V6K

VBST

DRVH

V5DRV

DRVL

TRIP

13
12

LL

11
10
9

1U_0402_6.3V6K

12

12

@

PR186
47K_0402_5%

DH_1.8V
LX_1.8V

DL_1.8V

@

PC102

1 2

@

PU8

7

POK

8

EN

0_0603_1%

12

PR117

BST_1.8V-1

12

+5VALW

6

VIN

VOUT

VCNTL

VOUT

FB

VIN

GND

APL5912-KAC-TRL_SO8

1

PR119

17.4K_0402_1%

5
4
3
2
9

PC96

1 2

0.1U_0603_25V7K

+5VALW

FDS6670AS_NL_SO8

12

PC100

4.7U_0805_10V6K

+1.2VALW

1

1

2

2

12

1.3K_0402_1%

PQ27

4

PJ15
JUMP_43X79

@

@

PC103

4.7U_0805_6.3V6K

PR123

@

@

PR124

3K_0402_1%

578

G

12

12

3 6

D6D5D7D

S

3

241

8

S

S

2

1

PQ26
AO4466_SO8

12

12

PC94

4.7U_1206_25V6K

PL9

1.2UH_1164AY-1R2N=P3_9.8A_30%

1 2

12

PR190

4.7_1206_5%

12

PC160
680P_0603_50V8J

@

PC104

12

@

PC105

22U_0805_6.3V6M

12

0.01U_0402_25V7K

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

2009/11/032008/11/03

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

1.8VSP/+1.1VSP

KBKC0_KBYF0

42 46T u e s day, February 03, 2009

1

0.3

of

5

4

3

2

+3VS

1

+5VALW

12

6

VIN

VOUT

VCNTL

VOUT

VIN

GND

APL5915KAI-TRL_SO8

1

+1.8V

1

1

2

2

1 2

13

D

2

G

S

PC107
1U_0402_6.3V6K

5
4
3
2

FB

9

PJ17
JUMP_43X79@

PR128

1K_0402_1%

PR129

1K_0402_1%

PQ28
SSM3K7002F_SC59-3

@

D D

PU9

7

PR125

10K_0402_1%

+3VS

C C

+1.8V

+5VALW

12

PC112
1U_0402_6.3V6K

B B

PR130

10K_0402_1%

30,32,36>

SUSP#

1 2

PC121

0.1U_0402_16V7K

12

@

12

PR184
47K_0402_5%

PU11

7

8

POK

EN

6

5

VIN

4

VOUT

VCNTL

3

VOUT

2

FB

9

VIN

GND

APL5915KAI-TRL_SO8

1

1

PJ18

1

JUMP_43X79@

2

2

12

PC115

4.7U_0805_6.3V6K

PR132

1.54K_0402_1%

12

12

PR133

1.74K_0402_1%

12

PC117

0.01U_0402_25V7K

12

+1.5VSP

PC119

22U_0805_6.3V6M

1 2

PC111

0.1U_0402_16V7K

SYSON#<24,29,36>

12

@

12

PR185
47K_0402_5%

@

PR131

0_0402_5%

1 2

0.1U_0402_16V7K@

POK

8

EN

PC113

4.7U_0805_6.3V6K

12

PC118

12

12

1

PJ16

1

JUMP_43X79@

2

2

12

PC108

4.7U_0805_6.3V6K

PR126

2.15K_0402_1%

12

PC116

0.1U_0402_16V7K

12

12

PR127
1K_0402_1%

PU10

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TRL_SO8

+0.9VP

12

PC120
10U_0805_6.3V6M

12

PC109

0.01U_0402_25V7K

NC
NC
NC
TP

PC110

22U_0805_6.3V6M

+2.5VSP

+3VALW

12

PC114
1U_0402_6.3V6K

12

6
5
7
8
9

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

5

4

3

Compal Secret Data

Deciphered Date

2009/11/032008/11/03

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

0.9VP//1.5VSP/2.5VSP

KBKC0_KBYF0

43 46T u e s day, February 03, 2009

1

0.3

of

5

PR135

2_0603_5%

1 2

CPU_B+

12

12

+1.8V

VW0

12

PC146

1000P_0402_50V7K

PR178

6.81K_0402_1%

12

+5VS

0.1U_0603_25V7K

PR144
105K_0402_1%@

PR149
105K_0402_1%@

0_0402_5%

+CPU_CORE_0

0.1U_0603_25V7K

1 2

PR139

2_0603_5%

PR160

PR164

0_0402_5%

0_0402_5%

+CPU_CORE_1

D D

+5VS +3VS

12

PR143
0_0402_5%

12

12

PR147

105K_0402_1%

C C

VGATE<30>

H_PWRGD_L<19>

CPU_SVD<6>

CPU_SVC<6>

VR_ON<30>

PR157

12

34.8K_0402_1%

B B

DIFF_0

PC144

PR174

4700P_0402_25V7K

255_0402_1%

12

A A

PR176

1K_0402_5%

FB_0

12

12

PR177

54.9K_0402_1%

5

PR146
10K_0402_1%@

PR153 0_0402_5%

1 2
1 2

PR192 0_0402_5% @

PR152 0_0402_5%

PR156 0_0402_5%

PR158

12

82.5K_0402_1%

12

PC145

180P_0402_50V8J

PC150

12

1200P_0402_50V7K

12

12

CPU_VDD0_FB_H<6>

CPU_VDD0_FB_L<6>
CPU_VDD1_FB_L<6>

CPU_VDD1_FB_H<6>

COMP0

12

PC128

PC132

PU12

1

OFS/VFIXEN

2

PGOOD

3

PWROK

4

SVD

5

SVC

6

ENABLE

7

RBIAS

8

OCSET

9

VDIFF0

10

FB0

11

COMP0

12

VW0

ISP0
ISN0

VSEN0

12

PR161

10_0402_5%

RTN0

12

PR165

0_0402_5%

PR198

@

100K_0402_5%

PR171

12

255_0402_1%

4

12

12

48

47

VIN

VCC

ISL6265IRZ-T_QFN48_6X6~D

ISN0

ISP0

14

13

12

RTN1

12

12

VSEN1

PR172

10_0402_5%

DIFF_1

PR175

PC147

4700P_0402_25V7K

12

PR179

1K_0402_5%

4

PR134

44.2K_0402_1%

46

45

FB_NB

COMP_NB

VSEN0

RTN0

15

16

PR166

1 2

10_0402_5%

12

12

12

PC122

33P_0402_50V8K

12

12

1200P_0402_50V7K

PC127

1000P_0402_50V7K

PR137

22K_0402_1%

PR141

0_0402_5%

42

43

44

RTN_NB

FSET_NB

VSEN_NB

VDIFF1

RTN1

VSEN1

19

17

18

PR167

1 2

10_0402_5%

PR180

54.9K_0402_1%

12

PC123

12

12

PR140

10_0402_5%

1 2

12

PR142

11.3K_0402_1%

39

40

41

PGND_NB

LGATE_NB

OCSET_NB

VW1

COMP121ISP1

FB1

22

20

12

PC148

180P_0402_50V8J

PC151

12

1200P_0402_50V7K

3

CPU_B+

578

PQ30

3 5

578

3 6

3 5

578

3 6

PC124

12

12

241

241

241

241

UGATE_NB

PHASE_NB

PR136

2.2_0603_5%

BOOT_NB

1 2

1 2

PC129

PR145

0.22U_0603_10V7K

12

CPU_VDDNB_FB_L <6>

UGATE0

PHASE0

BOOT0

1 2

0.22U_0603_10V7K

+5VS

12

PC138
1U_0603_16V6K

UGATE1

PHASE1

BOOT1

1 2

PR150

2.2_0603_5%

PR163

2.2_0603_5%

0.22U_0603_10V7K

2008/11/03 2009/11/03

12

38

37

PHASE_NB

23

24

ISP1

ISN1

VW1

COMP1FB_1

12

+CPU_CORE_NB

BOOT_NB

UGATE_NB

BOOT0
UGATE0
PHASE0

PGND0

LGATE0

PVCC

LGATE1

PGND1
PHASE1
UGATE1

BOOT1

ISN1

LGATE_NB

CPU_VDDNB_FB_H <6>

PHASE_NB

LGATE_NB
PHASE_NB
UGATE_NB

PR148
10_0402_5%

1 2

36
35
34
33
32
31
30
29
28
27
26
25

TP

49

12

PC149

1000P_0402_50V7K

PR181

6.81K_0402_1%

12

0_0402_5%

BOOT_NB
BOOT0
UGATE0
PHASE0

LGATE0

LGATE1

PHASE1
UGATE1
BOOT1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

PQ29
AO4466_SO8

3 6

241

578

AO4712_SO8

3 6

241

1 2

PC135

PQ32

AO4456_SO8

LGATE0

1 2

PC141

PQ35

AO4456_SO8

LGATE1

Compal Secret Data

Deciphered Date

2

12

12

PC155

PC152

10U_1206_25V6M

0.01U_0402_25V7K

PL11

3.3UH_SIQB74B-3R3PF_5.9A_20%

1 2

PR138

4.7_1206_5%

PC131
680P_0603_50V7K

PQ31

SI7686DP-T1-E3_SO8

578

3 6

241

PQ34

SI7686DP-T1-E3_SO8

578

3 6

241

2

HCB4532KF-800T90_1812

1 2

12

2200P_0402_50V7K

12

PC133

10U_1206_25V6M

PQ33
AO4456_SO8

12

PC139

10U_1206_25V6M

PQ36
AO4456_SO8

PL10

PC125

220U_25V_M

+CPU_CORE_NB

1

+

PC130
220U_D2_4VM

2

CPU_B+

12

12

PC153

PC134

10U_1206_25V6M

CPU_B+

PC140

10U_1206_25V6M

PC156

0.01U_0402_25V7K

2200P_0402_50V7K

12

PR154

4.7_1206_5%

12

PC136
680P_0603_50V7K

10K_0603_5%_TSM1A103J4302RE

12

12

PC157

PC154

0.01U_0402_25V7K

2200P_0402_50V7K

0.36UH_PCMC104T-R36MN1R17_30A_20%

12

PR169

4.7_1206_5%

12

PC142
680P_0603_50V7K

10K_0603_5%_TSM1A103J4302RE

Title

Size Document Number Rev

Custom

Date: Sheet

1

1

+

2

B+

+VDDNB
Design Current: 2.1A
Max current: 3A
OCP_min:5A

12

1
2

PR151

16.2K_0402_1%

1 2

4.02K_0402_1%

0.1U_0402_16V7K
PH3

@

ISP0

PL12

PR155

1 2

PC137

12

10_0402_5%

12

PR159

4
3

12

@

ISN0

0.36UH_PCMC104T-R36MN1R17_30A_20%

+CPU_CORE_0
Design Current: 12.6A
Max current: 18A
OCP_min:24A

12

PL13

1
2

PR168

16.2K_0402_1%

1 2

4.02K_0402_1%

0.1U_0402_16V7K
PH4

@

ISP1

+CPU_CORE_1

PR170

1 2

PC143

12

10_0402_5%

12

PR173

4
3

12

@

ISN1

Design Current: 12.6A
Max current: 18A
OCP_min:24A

Compal Electronics, Inc.

+CPU_CORE

KBKC0_KBYF0

Tuesday, February 03, 2009

1

+CPU_CORE_0

+CPU_CORE_1

of

44 46

0.3

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

for PWR

Reason for change Rev. P G # Modify List Date Ph aseFixed IssueItem

D D

EMI request. EMI request.

1

EMI request. EMI request. 40

2

EMI request. EMI request.

0.1 to DVT

0.1

0.1

3
4

EMI request. EMI request.

5

Link CIS error. Link CIS error. 40

cost down cost down

6

C C

7

8

9

schematic update. schematic update. 0.1 44

10

layout space too small. layout space too small. 0.1 41 08, 12/24 to DVT

cost downcost down

cost downcost down

0.1

0.1

0.1

0.1

Change PR38,PR39,PR108,PR112,PR136,PR150,PR163 from

40 08, 12/24

SD013000080 to SD013220B80.

Add PC170,PC171,PC172,PC173,PC174 SE00000G880
S CER CAP 0.1U 25V K X5R 0402

Add PL15 SM010016410 S SUPPRE_ KC FBMA-L11-322513-

39

151LMA50T

Add PL14 SM010018210 S SUPPRE_ TAI-TECH HCB4532KF

41

-800T90 1812
Change PQ9, PQ10, PQ12 from SB944070000

S TR AO4407 1P SO8 W/D to SB00000DL00
S TR AO4407A 1P SO8

Change PC30 from SGA19331360 S POLY C 330U 6.3V M

40

D3L ESR25M TPE H2.8 to SF000001G00
S_A-P_CAP 330U 6.3V M 6.3X5.7 LESR14M ME

Change PC35 from SGA20151320 S POLY C 150U 6.3V M
D2E TPE ESR18 H1.8 to SF000001G00

400.1
S_A-P_CAP 330U 6.3V M 6.3X5.7 LESR14M ME

Change PC87, PC98 from SGA19331D00 S POLY C 330U 2.5V M

41,

D2 TPE LESR15M H1.8 to SF000001G00 S_A-P_CAP 330U

42

6.3V M 6.3X5.7 LESR14M ME

Delete PR198 SD028100380 S RES 1/16W 100K +-5% 0402

Change PQ23 from SB00000CG00 S TR AO4466
1N SO8 to SB00000BG00 S TR AO4932 2N SO8

Delete PQ25 SB00000AJ00 S TR AO4712 1N SO8

to DVT08, 12/24

to DVT08, 12/24

to DVT08, 12/24

to DVT08, 12/24

to DVT08, 12/24

to DVT08, 12/24

to DVT08, 12/24

to DVT08, 12/24

11

B B

12

13

14

15

16

17

18

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/03 2009/11/03

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Do c ument Number Rev

Custom

Tuesday, F ebruary 03, 2009

2

Date: Sheet

PIR List

KBKC0_KBYF0

45 46

1

0.3

of

5

4

3

2

1

NO DATE PAGE MODIFICATION LIST PURPOSE

-----------------------------------------------------------------------------------------------------------------------------------------------

12/17 p.12 L3,L4 change from bead to 0 Ohm
12/17 P.17 Add R858~R865 for VGA HDMI
12/17 P.18 R374,R375,R376 change from 0 ohm to 10 ohm
12/17 P.20 R50 ,R53 change from JV70@ to @

D D

12/17 P.20 R51 ,R52 change from JM70@ to JV70@
12/17 P.24 JP18 change from ESATA to USB port
12/17 P.25 R396 change from 10K to 0 Ohm
12/17 P.31 C905~C907 change from 0.1u to 33P
12/17 P.31 U19 change from mount to @ ; U18 change from @ to mount
12/17 P.32 D22 change from mount to @
12/18 P.24 SATA re-driver IC reserved
12/22 P.8 Add c124,c128,c151,c155,c55,c119,c113,c197 0.1uF EMI request
12/22 P.30 Add c40 c41 100P EMI request
12/22 P.30 Add c42,c43,c45 EMI request
12/22 P.37~p.45 upgrade PWR schematic
12/22 P.30 Add C65 22uF for CRT flicker

C C

12/23 P.21 Delete R174,R175
01/16 P.16 Add r611,r612 connect to INVT_PWM
01/16
01/16

P.11 Add r347 connect to BKOFF#
P.30 add r288 BKOFF# 4.7k pull low

Vari-Bright reserved
Vari-Bright reserved

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/03 2009/11/03

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

HW PIR

KBYF0 LA-5051P

46 46Tuesday, February 03, 2009

1

0.3

of