COMPAL LA-4961P Schematics

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile AMD S1G3 CPU with ATI
RS880M(NB) & SB710(SB) core logic

3 3

2009-08-27

REV:1.0

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/03/23 2010/03/23

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

LA-4961P

1 54Thursday , August 27, 2009

E

1.0

A

Compal Confidential

B

C

D

E

TAG UMA

Accelerometer
ST LIS302DL TR

1 1

Page 3 0

LVDS Panel
Interface

CRT

Display Port

Page 1 7

Page 1 6

Page 1 8

daughter board

2 2

Express Card 54

PCIE X1 + USB X1

Page 3 1

10/100/1 000 LAN

88 E 8 072

Page 25

3 3

RJ45 CONN

Page 26

Ri co R5U230

Controller

1394 port

Page 3 1 Page 3 1 Page 3 1

Smart Card

Mini Card UWB
PCIE X 1

daughter board

Thermal Se nsor
ADM1032

Fan c onn

Page 27

PCI-E BUS

WLAN Card

USB + PCIE X1

Page 27

Page 4

Page 4

Caspian

AMD S1G3 CPU

638-PIN uFCPGA 638

Hyper Transport Link

16X16

ATI RS880M

Page 10, 11, 12, 13, 14

A- Li nk Expre ss II

4X P CI-E

ATI SB710

Page 19, 20, 21 ,22, 23

LPC BUS

Page 4, 5, 6, 7

DDR2 800MHz 1.8V

Dual Channel

DDR2 4 00MHz

USB2.0

Azalia

SATA0

SATA1

DDR2- SO-DIMM X2

BANK 0 , 1, 2, 3

Page 8, 9

Side-Port DDR2 SDRAM
512Mbits (32Mbx16)-64MB

WWAN USB X 1

Page 27

USB x2(Docking)

FingerPrinter VFM451
USBx1

USB conn x 2(For I/O)
BT Conn USB x 1

USB ConnX2
sub BD
USB x1(Camara)

MD C V1.5

Audio CKT

92HD75

SATA ODD Connector

2.5" SAT A HDD Connector

Page 33

Page 30

Page 30

Page 3 1

Page 17

Page 28

Page 24

Page 24

72QFN

Clock Generator

IC S9L PRS4 76E

Page 15

Page 13

daughter board

daughter board

RJ11

Page 28

TPA6041A

AMP & Audio Jack

daughter board

P38

Docking CONN.

(1) PCI Express x1 channels
(2) PS/2 Interf aces
(2) USB 2.channels
(2) SATA Channels
(2) Display Port Channels

TPM1.2

SLB9635TT

Page 29 page 34

SMSC KBC 1098

SMSC Super I/O

ITE IT8305

Page 35

Power OK CKT.

page 36

Power On/Off CKT.

4 4

page 28

DC/DC Interface CKT.

Page 3 3

A

LED CKT.

Page 3 1

RTC CKT.

Page 3 1

TrackPoint CONN.

Page 28

Touch Pad CONN.

B

Page 3 1

Int.KBD

Page 28

SP I ROM
2 M B

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

COM1 LPT
( Docking ) ( Docking )

Page 33 Page 33

Page 29

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

(1) Serial P ort
(1) Parallel Port
(1) Line In
(1) Line Out
(1) RJ45 (10/100/1000)
(1) V GA
(1) 2 LAN indicator LED's
(1) Power Button
(1) I2C interface

Compal Electronics, Inc.

Block Diagram

LA-4961P

2 54Thursday , August 27 , 2009

E

1.0

A

B

C

D

E

Voltage Rails

1 1

O MEANS ON X MEANS OFF

Symbol Note :

: means Digital Ground

+5VS

State

power
plane

+B

VL

+3VL

+5VALW

+3VALW

+1.8V

+3VS

+1.5VS

+0.9V

+CPU_CORE_0

+2.5VS

+1.8VS

+NB_VDDC

+VDDA11PCIE

: means Analog Ground

Lay out Note s

: Q ues ti on Are a Mark. (Wa it ch eck )

"*" as default BOM setting
@ : means just reserve , no build
45@ : Install when 45 level Assy.

2 2

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O

O

O

O

O

X

O

O

O

O

X

O

X X

X

X X X

OO

OO

X

X

CONN@:means ME part

3 3

4 4

A

B

SMBUS Control Table

THERMAL

SOURCE INVERTER BATT EEPROM

SMB_CK_CLK0

SMB_CK_DAT0

SMB_CK_CLK1

SMB_CK_DAT1

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SB710

SB710

2007/08/02 2008/08/02

C

X X X X X X
X X X X X X X X X X

Compal Secret Data

SERIAL

Deciphered Date

SENSOR

CPU &

ADM103 2

D

SODIMM CLK CHIP

V

MINI CARD LCD

Slot 2I / II

X

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-4961P

E

HDMI

G-Sensor

VV

3 54Thursday , August 27 , 2009

1.0

A

1 1

H_C ADIP[0..15 ]<10>

2 2

H_CLKIP0<10>
H_CLK IN0<10>
H_CLKIP1<10>

3 3

H_CLK IN1<10>

H_CTLIP0<10>

H_CTLIP1<10> H_CTLOP1 <10>
H_CTLIN1<10>

H_ CADIP[0..1 5]

H_C ADIN[0 ..15]

VLDT= 500mA

H_CAD IP0
H_C ADIN0
H_CAD IP1
H_C ADIN1
H_CAD IP2
H_C ADIN2
H_CAD IP3
H_C ADIN3
H_CAD IP4
H_C ADIN4
H_CAD IP5
H_C ADIN5
H_CAD IP6
H_C ADIN6
H_CAD IP7
H_C ADIN7
H_CAD IP8
H_C ADIN8
H_CAD IP9
H_C ADIN9
H_CAD IP10
H_CAD IN10
H_CAD IP11
H_CAD IN11
H_CAD IP12
H_CAD IN12
H_CAD IP13
H_CAD IN13
H_CAD IP14
H_CAD IN14
H_CAD IP15
H_CAD IN15

+1.2V_HT

JCPU1A

D1

VLDT_A0

D2

VLDT_A1

D3

VLDT_A2

D4

VLDT_A3

E3

L0_CADIN_H0

E2

L0_CADIN_L0

E1

L0_CADIN_H1

F1

L0_CADIN_L1

G3

L0_CADIN_H2

G2

L0_CADIN_L2

G1

L0_CADIN_H3

H1

L0_CADIN_L3

J1

L0_CADIN_H4

K1

L0_CADIN_L4

L3

L0_CADIN_H5

L2

L0_CADIN_L5

L1

L0_CADIN_H6

M1

L0_CADIN_L6

N3

L0_CADIN_H7

N2

L0_CADIN_L7

E5

L0_CADIN_H8

F5

L0_CADIN_L8

F3

L0_CADIN_H9

F4

L0_CADIN_L9

G5

L0_CADIN_H10

H5

L0_CADIN_L10

H3

L0_CADIN_H11

H4

L0_CADIN_L11

K3

L0_CADIN_H12

K4

L0_CADIN_L12

L5

L0_CADIN_H13

M5

L0_CADIN_L13

M3

L0_CADIN_H14

M4

L0_CADIN_L14

N5

L0_CADIN_H15

P5

L0_CADIN_L15

J3

L0_CLKIN_H0

J2

L0_CLKIN_L0

J5

L0_CLKIN_H1

K5

L0_CLKIN_L1

N1

L0_CTLIN_H0

P1

L0_CTLIN_L0

P3

L0_CTLIN_H1

P4

L0_CTLIN_L1

FOX_P Z6382A-284S-41F_GRIFFIN

CONN@

Athlon 64 S1
Processor Socket

9/2 0 SP0 70 00D M0 0/SP 07000 EQ00

HT LINK

B

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

L0_CADOUT_H0

L0_CADOUT_L0

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H15

L0_CADOUT_L15

L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

AE2
AE3
AE4
AE5

AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3

Y1
W1
Y4
Y3

R2
R3
T5
R5

H_CAD OP[0..15]

H_ CADON[0..1 5]

+1.2V_HT

1 2

C7 10U_0805_10V4Z

H_CAD OP0
H_CAD ON0
H_CAD OP1
H_CAD ON1
H_CAD OP2
H_CAD ON2
H_CAD OP3
H_CAD ON3
H_CAD OP4
H_CAD ON4
H_CAD OP5
H_CAD ON5
H_CAD OP6
H_CAD ON6
H_CAD OP7
H_CAD ON7
H_CAD OP8
H_CAD ON8
H_CAD OP9
H_CAD ON9
H_CAD OP10
H_CAD ON10
H_CAD OP11
H_CAD ON11
H_CAD OP12
H_CAD ON12
H_CAD OP13
H_CAD ON13
H_CAD OP14
H_CAD ON14
H_CAD OP15
H_CAD ON15

H_PROCH OT#<6,46>

C

H_CAD OP[0..15] <10>

H_C ADON[0..15 ] <10>H_C ADIN[0..1 5]<10>

chang e 4.7 U to 1 0U fo r AMD S1G3 requ est. HP 12/8

H_CLKOP0 <10>
H_CLKON0 <10>
H_CLKOP1 <10>
H_CLKON1 <10>

H_CTLOP0 <10>
H_CTLON0 <10>H_CTLIN0<10>

H_CTLON1 <10>

12

30K_0402_5%

R556

Q108

CBE

123

PMBT3904_SOT23

for F an sh ake i ss ue wh en in 7 0 de gree . Co mpal 3/23

+5VS+1.8V

12

+1.2V_HT

1

2

+3VS

1

C8

2

CPU_THER MTRIP#_R<6>

0.1U_0402_16V4Z

NB_THERMAL_DA<11>
NB_THERMAL_DC<11>

PWM Fan Control
circuit

10K_0402_5%
R557

FAN_PWM<33>

R1 3K_0402_5%

250 mi l

C1
10U_0805_10V4Z

C9

1 2

HP 3/ 30

12

D

VLDT CAP.

1

C2
10U_0805_10V4Z

2

Thermal Sensor EMC1402

NB_THERMAL_DA

NB_THERMAL_DC

2200P_0402_50V7K

CPU_THER MTRIP#_R

NB_THERMAL_DA
NB_THERMAL_DC

FAN_PWM_R

1

2

1

C3

0.22U_0603_16V4 Z

2

Near CPU Socket

U1

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

chang e fro m ADM1 032 t o EMC 1402 12/1

addre ss: 4 C

+3VS

5

U2

P

INB

4

O

G

TC7SH00FU_SSOP5

R534 2.2K_0402_5%

INA

3

for R F, HP 12/10

1

2

SMDATA

12

C4

0.22U_0603_16V4 Z

8

SMCLK

7

6

ALERT#

5

GND

+5VS

12

0_0603_5%
R471

C10

1 2

0.1U_0402_10V6K@

1

C5
180P_0402_50V8J

2

FAN_PWM_R

E

1

2

SMB_CK_CLK0 <6,8,9,1 5,21,30>

SMB_CK_DAT0 < 6,8,9,15,21,30>

conn@

JP1

1

1

2

2

G1

3

3

G2

ACES_85204-03001

C6
180P_0402_50V8J

4
5

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

AMD CPU S1G2 HT I/F

LA-4961P

4 54Thursday , August 27 , 2009

E

1.0

A

B

C

D

E

Processor DDR2 Memory Interface

1 1

+1.8V

9/2 3 HP

R2

1K_0402_1%

1 2

+MCH_REF

C12

R3

1K_0402_1%

1 2

2 2

JCPU1B

D10

VTT1

Pla ce th em cl os e t o CP U wi thin 1"

R4 39.2_0402_1%

1 2

DDR_A_BS #0<8>
DDR_A_BS #1<8>
DDR_A_BS #2<8>

DDR_A _RAS#<8>
DDR_A _CAS#<8>
DDR_A_W E#<8>

1 2

R5 39.2_0402_1%

+1.8V

DDR_A _ODT0<8>
DDR_A _ODT1<8>

DDR_CS0_D IMMA#<8>
DDR_CS1_D IMMA#<8> DDR_CS0_D IMMB# <9>

DDR_CKE 0_DIMMA<8>
DDR_CKE 1_DIMMA<8>

DDR_A _CLK0<8>

DDR_A _CLK#0<8>

3 3

4 4

DDR_A _CLK1<8>

DDR_A _CLK#1<8>

DDR_A _MA[15..0]<8> DDR_B _MA[15..0] <9>

MEMZP
MEMZN

DDR_A _ODT0
DDR_A _ODT1

DDR_C S0_DIMMA#
DDR_C S1_DIMMA# DDR_C S0_DIMMB#

DDR_CKE 0_DIMMA
DDR_CKE 1_DIMMA

DDR_A _CLK0
DDR_A _CLK#0
DDR_A _CLK1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_BS #0
DDR_A_BS #1
DDR_A_BS #2

DDR_A _RAS#
DDR_A _CAS#
DDR_A_W E#

AD10

AF10

AE10

AA16

MEM:CMD /CTRL/CLK

C10

VTT2

B10

VTT3
VTT4

MEMZP
MEMZN

H16

RSVD_M1

T19

MA0_ODT0

V22

MA0_ODT1

U21

MA1_ODT0

V19

MA1_ODT1

T20

MA0_CS_L0

U19

MA0_CS_L1

U20

MA1_CS_L0

V20

MA1_CS_L1

J22

MA_CKE0

J20

MA_CKE1

N19

MA_CLK_H5

N20

MA_CLK_L5

E16

MA_CLK_H1

F16

MA_CLK_L1

Y16

MA_CLK_H7
MA_CLK_L7

P19

MA_CLK_H4

P20

MA_CLK_L4

N21

MA_ADD0

M20

MA_ADD1

N22

MA_ADD2

M19

MA_ADD3

M22

MA_ADD4

L20

MA_ADD5

M24

MA_ADD6

L21

MA_ADD7

L19

MA_ADD8

K22

MA_ADD9

R21

MA_ADD10

L22

MA_ADD11

K20

MA_ADD12

V24

MA_ADD13

K24

MA_ADD14

K19

MA_ADD15

R20

MA_BANK0

R23

MA_BANK1

J21

MA_BANK2

R19

MA_RAS_L

T22

MA_CAS_L

T24

MA_WE_L

FOX_P Z6382A-284S-41F_GRIFFIN

Athlo n 64 S1
Proce ssor
Socke t

CONN@

VTT5
VTT6
VTT7
VTT8
VTT9

VTT_SENSE

MEMVREF

RSVD_M2

MB0_ODT0
MB0_ODT1
MB1_ODT0

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0

MB_CKE0
MB_CKE1

MB_CLK_H5

MB_CLK_L5

MB_CLK_H1

MB_CLK_L1

MB_CLK_H7

MB_CLK_L7

MB_CLK_H4

MB_CLK_L4

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8

MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

MB_BANK0
MB_BANK1
MB_BANK2

MB_RAS_L
MB_CAS_L

MB_WE_L

W10
AC10
AB10
AA10
A10

Y10

W17

B18

W26
W23
Y26

V26
W25
U22

J25
H26

P22
R22
A17
A18
AF18
AF17
R26
R25

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24

R24
U26
J26

U25
U24
U23

+0.9V+0.9V

+MCH_REF

DDR_B _ODT0
DDR_B _ODT1

DDR_C S1_DIMMB#

DDR_CKE 0_DIMMB
DDR_CKE 1_DIMMB

DDR_B _CLK0
DDR_B _CLK#0
DDR_B _CLK1
DDR_B _CLK#1DDR_A _CLK#1

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_B_BS #0
DDR_B_BS #1
DDR_B_BS #2

DDR_B _RAS#
DDR_B _CAS#
DDR_B_W E#

0.1U_0402_16V4Z

DDR_B _ODT0 <9>
DDR_B _ODT1 <9>

DDR_CS1_D IMMB# <9>

DDR_CKE 0_DIMMB <9>
DDR_CKE 1_DIMMB <9>

DDR_B _CLK0 <9>
DDR_B _CLK#0 <9>
DDR_B _CLK1 <9>
DDR_B _CLK#1 <9>

DDR_B_BS #0 <9>
DDR_B_BS #1 <9>
DDR_B_BS #2 <9>

DDR_B _RAS# <9>
DDR_B _CAS# <9>
DDR_B_W E# <9>

1

C13

2

1000P_0402_25V8J

DDR _B_D[63.. 0]<9>

1

2

DDR_B _DM[7..0]<9> DDR_A _DM[7..0] <8>

DDR_B _DQS0<9>
DDR_B _DQS#0<9>
DDR_B _DQS1<9>
DDR_B _DQS#1<9>
DDR_B _DQS2<9>
DDR_B _DQS#2<9>
DDR_B _DQS3<9>
DDR_B _DQS#3<9>
DDR_B _DQS4<9>
DDR_B _DQS#4<9>
DDR_B _DQS5<9>
DDR_B _DQS#5<9>
DDR_B _DQS6<9>
DDR_B _DQS#6<9>
DDR_B _DQS7<9>
DDR_B _DQS#7<9>

DDR_B _D0
DDR_B _D1
DDR_B _D2
DDR_B _D3
DDR_B _D4
DDR_B _D5
DDR_B _D6
DDR_B _D7
DDR_B _D8
DDR_B _D9
DDR_B _D10
DDR_B _D11
DDR_B _D12
DDR_B _D13
DDR_B _D14
DDR_B _D15
DDR_B _D16
DDR_B _D17
DDR_B _D18
DDR_B _D19
DDR_B _D20
DDR_B _D21
DDR_B _D22
DDR_B _D23
DDR_B _D24
DDR_B _D25
DDR_B _D26
DDR_B _D27
DDR_B _D28
DDR_B _D29
DDR_B _D30
DDR_B _D31
DDR_B _D32
DDR_B _D33
DDR_B _D34
DDR_B _D35
DDR_B _D36
DDR_B _D37
DDR_B _D38
DDR_B _D39
DDR_B _D40
DDR_B _D41
DDR_B _D42
DDR_B _D43
DDR_B _D44
DDR_B _D45
DDR_B _D46
DDR_B _D47
DDR_B _D48
DDR_B _D49
DDR_B _D50
DDR_B _D51
DDR_B _D52
DDR_B _D53
DDR_B _D54
DDR_B _D55
DDR_B _D56
DDR_B _D57
DDR_B _D58
DDR_B _D59
DDR_B _D60
DDR_B _D61
DDR_B _D62
DDR_B _D63

DDR_B_DM 0
DDR_B_DM 1
DDR_B_DM 2
DDR_B_DM 3
DDR_B_DM 4
DDR_B_DM 5
DDR_B_DM 6
DDR_B_DM 7

DDR_B _DQS0
DDR_B _DQS#0
DDR_B _DQS1
DDR_B _DQS#1
DDR_B _DQS2
DDR_B _DQS#2
DDR_B _DQS3
DDR_B _DQS#3
DDR_B _DQS4
DDR_B _DQS#4
DDR_B _DQS5
DDR_B _DQS#5
DDR_B _DQS6
DDR_B _DQS#6
DDR_B _DQS7
DDR_B _DQS#7

JCPU 1C

C11

MB_DATA0

A11

MB_DATA1

A14

MB_DATA2

B14

MB_DATA3

G11

MB_DATA4

E11

MB_DATA5

D12

MB_DATA6

A13

MB_DATA7

A15

MB_DATA8

A16

MB_DATA9

A19

MB_DATA10

A20

MB_DATA11

C14

MB_DATA12

D14

MB_DATA13

C18

MB_DATA14

D18

MB_DATA15

D20

MB_DATA16

A21

MB_DATA17

D24

MB_DATA18

C25

MB_DATA19

B20

MB_DATA20

C20

MB_DATA21

B24

MB_DATA22

C24

MB_DATA23

E23

MB_DATA24

E24

MB_DATA25

G25

MB_DATA26

G26

MB_DATA27

C26

MB_DATA28

D26

MB_DATA29

G23

MB_DATA30

G24

MB_DATA31

AA24

MB_DATA32

AA23

MB_DATA33

AD24

MB_DATA34

AE24

MB_DATA35

AA26

MB_DATA36

AA25

MB_DATA37

AD26

MB_DATA38

AE25

MB_DATA39

AC22

MB_DATA40

AD22

MB_DATA41

AE20

MB_DATA42

AF20

MB_DATA43

AF24

MB_DATA44

AF23

MB_DATA45

AC20

MB_DATA46

AD20

MB_DATA47

AD18

MB_DATA48

AE18

MB_DATA49

AC14

MB_DATA50

AD14

MB_DATA51

AF19

MB_DATA52

AC18

MB_DATA53

AF16

MB_DATA54

AF15

MB_DATA55

AF13

MB_DATA56

AC12

MB_DATA57

AB11

MB_DATA58

Y11

MB_DATA59

AE14

MB_DATA60

AF14

MB_DATA61

AF11

MB_DATA62

AD11

MB_DATA63

A12

MB_DM0

B16

MB_DM1

A22

MB_DM2

E25

MB_DM3

AB26

MB_DM4

AE22

MB_DM5

AC16

MB_DM6

AD12

MB_DM7

C12

MB_DQS_H0

B12

MB_DQS_L0

D16

MB_DQS_H1

C16

MB_DQS_L1

A24

MB_DQS_H2

A23

MB_DQS_L2

F26

MB_DQS_H3

E26

MB_DQS_L3

AC25

MB_DQS_H4

AC26

MB_DQS_L4

AF21

MB_DQS_H5

AF22

MB_DQS_L5

AE16

MB_DQS_H6

AD16

MB_DQS_L6

AF12

MB_DQS_H7

AE12

MB_DQS_L7

FOX_P Z6382A-284S-41F_GRIFFIN

Athlon 64 S1
Processor Socket

CONN@

MEM:DATA

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8

MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

MA_DQS_H0

MA_DQS_L0

MA_DQS_H1

MA_DQS_L1

MA_DQS_H2

MA_DQS_L2

MA_DQS_H3

MA_DQS_L3

MA_DQS_H4

MA_DQS_L4

MA_DQS_H5

MA_DQS_L5

MA_DQS_H6

MA_DQS_L6

MA_DQS_H7

MA_DQS_L7

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12

E12
C15
E19
F24
AC24
Y19
AB16
Y13

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13

DDR_A _D0
DDR_A _D1
DDR_A _D2
DDR_A _D3
DDR_A _D4
DDR_A _D5
DDR_A _D6
DDR_A _D7
DDR_A _D8
DDR_A _D9
DDR_A _D10
DDR_A _D11
DDR_A _D12
DDR_A _D13
DDR_A _D14
DDR_A _D15
DDR_A _D16
DDR_A _D17
DDR_A _D18
DDR_A _D19
DDR_A _D20
DDR_A _D21
DDR_A _D22
DDR_A _D23
DDR_A _D24
DDR_A _D25
DDR_A _D26
DDR_A _D27
DDR_A _D28
DDR_A _D29
DDR_A _D30
DDR_A _D31
DDR_A _D32
DDR_A _D33
DDR_A _D34
DDR_A _D35
DDR_A _D36
DDR_A _D37
DDR_A _D38
DDR_A _D39
DDR_A _D40
DDR_A _D41
DDR_A _D42
DDR_A _D43
DDR_A _D44
DDR_A _D45
DDR_A _D46
DDR_A _D47
DDR_A _D48
DDR_A _D49
DDR_A _D50
DDR_A _D51
DDR_A _D52
DDR_A _D53
DDR_A _D54
DDR_A _D55
DDR_A _D56
DDR_A _D57
DDR_A _D58
DDR_A _D59
DDR_A _D60
DDR_A _D61
DDR_A _D62
DDR_A _D63

DDR_A_DM 0
DDR_A_DM 1
DDR_A_DM 2
DDR_A_DM 3
DDR_A_DM 4
DDR_A_DM 5
DDR_A_DM 6
DDR_A_DM 7

DDR_A _DQS0
DDR_A _DQS#0
DDR_A _DQS1
DDR_A _DQS#1
DDR_A _DQS2
DDR_A _DQS#2
DDR_A _DQS3
DDR_A _DQS#3
DDR_A _DQS4
DDR_A _DQS#4
DDR_A _DQS5
DDR_A _DQS#5
DDR_A _DQS6
DDR_A _DQS#6
DDR_A _DQS7
DDR_A _DQS#7

DDR_ A_D[63..0 ] <8>

DDR_A _DQS0 <8>
DDR_A _DQS#0 <8>
DDR_A _DQS1 <8>
DDR_A _DQS#1 <8>
DDR_A _DQS2 <8>
DDR_A _DQS#2 <8>
DDR_A _DQS3 <8>
DDR_A _DQS#3 <8>
DDR_A _DQS4 <8>
DDR_A _DQS#4 <8>
DDR_A _DQS5 <8>
DDR_A _DQS#5 <8>
DDR_A _DQS6 <8>
DDR_A _DQS#6 <8>
DDR_A _DQS7 <8>
DDR_A _DQS#7 <8>

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

AMD CPU S1G2 DDRII I/F

LA-4961P

5 54Thursday , August 27 , 2009

E

1.0

A

+2.5VS

C14

@

100U_D2_10VM

1 1

CLK_CP U_BCLK<15>

Plac e cl ose to C PU wihtin 1.5"

C18

0718 Silego -- 216 ohm

CLK_CP U_BCLK#<15>

12

R1210K_0402_5%

Q11

CBE

THERM_SC#<21>

+1.8VS

2 2

LDT_RST#<19>

+1.8VS

H_PW RGD_CPU<19>

PMBT3904_SOT23

R19
300_0402_5%

1 2

LDT_RST#

R25
300_0402_5%

1 2

H_PW RGD_CPU

123

+CPU_C ORE_0

R141K_0402_5%

ALERT

R18 10_0402_ 5%

1 2
1 2

R20 10_0402_ 5%

+1.8V

12

10/ 29 HP

CPU_V DD0_FB_L

Close to CPU

C19 3900P_0402_50V7K

9/2 3 H P

3 3

+1.8VS

HP 4/ 6

R35
560_0402_5%

1 2

LDT_STOP#<11,19>

+1.8VS

R42
1K_0402_5%

1 2

4 4

CPU_LDT_R EQ#

LDT_STOP#

SMB_CK_CLK0<4,8,9 ,15,21,30>

SMB_CK_DAT0<4,8,9,15,21,30>

CPU_LD T_REQ# <11,19>

B

L1

1 2

FBM_L11_201209_300L_0805

1

+

2

3900P_0402_50V7K

1 2

12

R9
169_0402_1%

1 2

+1.8V

+5VS

2

Q4A
DMN66D0LDW-7_SOT363-6

+5VS

2

Q5A
DMN66D0LDW-7_SOT363-6

+2.5VDDA

+1.2V_HT

11/ 6 H P

61

CPU_SMDATA

61

1

C154.7U_0805_10V4Z

2

10/ 29 HP

CPU_SMCLK

VDDA= 300mA

3300P_0402_50V7K

1

1

C17

C16

0.22U_0603_16V4 Z

2

2

CPU_C LKIN_SC_P
CPU_C LKIN_SC_N

LDT_RST#
H_PW RGD_CPU
LDT_STOP#

CPU_S IC
CPU_S ID

R13 44.2_0402_1%
R15 44.2_0402_1%

R509

R510 300_0402_5%

ALERT

1 2
1 2

CPU_V DD0_FB_H<45>
CPU_V DD0_FB_L<45>

AMD r eco mm end NC 10/15

CPU _DBRD Y
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_T DI

R489 300_0402_5%

1 2

CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1CPU_V DD0_FB_H

510_0402_5%

CPU_T EST25_H_BYPASSCLK_H

1 2

CPU_TEST25_L_BYPASSCLK_L

1 2

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_T EST22_SCANSHIFTEN

T17 PAD
T18 PAD

CPU_T EST12_SCANSHIFTENB
CPU_T EST27_SINGLECHAIN

5

3

4

Q4B
DMN66D0LDW-7_SOT363-6

5

3

4

Q5B
DMN66D0LDW-7_SOT363-6

C21 220P_0402_25V8J

F10

AF4
AF5

AE6

AB6

G10
AA9
AC9
AD9
AF9

AD7

H10

AB8
AF7
AE7
AE8
AC8
AF8

AA6

R34

1.5K_0402_5%

CPU_S IC

CPU_S ID

4.7K_0402_5%

CPU_HTREF0
CPU_HTREF1

CPU_V DD0_FB_H
CPU_V DD0_FB_L

1

C20 220P_0402_25V8J

2

1

2

C

JCPU 1D

F8

VDDA1

F9

VDDA2

A9

CLKIN_H

A8

CLKIN_L

B7

RESET_L

A7

PWROK
LDTSTOP_L

C6

LDTREQ_L

SIC
SID
ALERT_L

R6

HT_REF0

P6

HT_REF1

F6

VDD0_FB_H

E6

VDD0_FB_L

Y6

VDD1_FB_H
VDD1_FB_L

DBRDY
TMS
TCK
TRST_L
TDI

TEST23

TEST18

G9

TEST19

E9

TEST25_H

E8

TEST25_L

TEST21
TEST20
TEST24
TEST22
TEST12
TEST27

C2

TEST9
TEST6

A3

RSVD1

A5

RSVD2

B3

RSVD3

B5

RSVD4

C1

RSVD5

FOX_P Z6382A-284S-41F_GRIFFIN

CONN@

R43

+3VS

12

12

THERMTRIP_L

PROCHOT_L

MEMHOT_L

THERMDC
THERMDA

VDDIO_FB_H

VDDIO_FB_L

VDDNB_FB_H

VDDNB_FB_L

TEST28_H

TEST29_H

1

C705

0.1U_0402_25V6

2

KEY1
KEY2

SVC
SVD

DBREQ_L

TDO

TEST28_L

TEST17
TEST16
TEST15
TEST14

TEST7

TEST10

TEST8

TEST29_L

RSVD10

RSVD9
RSVD8
RSVD7
RSVD6

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

D

Q10

CBE

123

HDT_RST#

R572

1K_0402_1%

11/ 6 H P

U3

4

Y

R7

1 2

+1.8V

M11
W18

CPU_SVC

A6

CPU_SVD

A4

AF6
AC7
AA8

W7
W8

W9
Y9

H6
G6

CPU_D BREQ#

E10

CPU_TDO

AE9

CPU_T EST28_H_PLLCHRZ_P

J7

CPU_T EST28_L_PLLCHRZ_N

H8

CPU_TEST17_BP3

D7

CPU_TEST16_BP2 CPU_S ID

E7

CPU_TEST15_BP1

F7

CPU_TEST14_BP0

C7

C3
K8

C4

CPU_TEST29_H_FBCLKOUT_P

C9

CPU_TEST29_L_FBCLKOUT_N

C8

H18
H19
AA7
D5
C5

CPU_SVC <45>
CPU_SVD <45>

CPU_THER MTRIP#_R
H_PROCH OT#

VDD_N B_FB_H <45>
VDD_N B_FB_L <45>

10/ 29 HP

10/ 29 HP

@

R508 590_0402_1%

1 2

11/ 6 H P

11/ 6 HP

+1.8V

R39220_0402_5%@

R38220_0402_5%@

R40300_0402_5%

R41220_0402_5%@

12

12

12

12

220_0402_5%@ R3 7

220_0402_5%@ R3 6

12

12

H_PROCH OT# <4,46>

PAD

HDT Connector

680_0402_5%

CPU_THER MTRIP#_R

CPU_THER MTRIP#_R <4>

rou te as d iff eren tial
as sh ort a s po ssib le
tes t poi nt un der the pac kage

T9PAD
T10PAD

T11PAD
T12PAD
T1PAD
T2PAD

+1.2V_HT

T15PAD

T16

JP2

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

2423
26

SAMTEC_ASP-68200-07

PMBT3904_SOT23

HP 3/ 30

HP 3/ 30

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_T EST22_SCANSHIFTEN

CPU_TEST15_BP1

CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

E

HP, 6 /12

12

H_THERMTRIP# <21>

H_PROCH OT#

chang e fro m +1.8 VS to +1.8V
for l ekage issue HP 12/18

CPU_SVC
CPU_SVD

VDD_N B_FB_H
VDD_N B_FB_L

LDT_RST#

1 2

R8 300_0402_5%

R10 1K_0402_5%

1 2
1 2

R11 1K_0402_5%

10/ 29 HP

R16 10_0402_5%

1 2
1 2

R17 10_0402_5%

Close to CPU

R490 390_0402_5%

CPU_S IC

1 2
1 2

R491 390_0402_5%

10/ 29 HP

R24 300_0402_5%

1 2

R26 300_0402_5%
R27 300_0402_5%
R28 300_0402_5%@

R30 300_0402_5%@

R32 300_0402_5%@
R33 300_0402_5%@

+3VS

5

LDT_RST#

2

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5

3

12
12
12

12

12
12

SB_PW RGD <21,33,45>

+1.8V

+1.8V

+CPU_ CORE_NB

+1.8V

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

AMD CPU S1G2 CTRL

LA-4961P

6 54Thursday , August 27 , 2009

E

1.0

A

VDD(+CPU_CORE) decoupling.

+CPU_C ORE_0

1

+

1 1

C22
330U_X_2VM_R6M

2

1

+

C23
330U_X_2VM_R6M

2

Near CPU Socket

+CPU_C ORE_0

1

C26
22U_0805_6.3V6M

2

+CPU_C ORE_0

1

C34

0.22U_0603_16V4 Z

2

2 2

1

C27
22U_0805_6.3V6M

2

1

C35

0.01U_0402_25V4 Z

2

1

C28
22U_0805_6.3V6M

2

1

2

C36
180P_0402_50V8J

1

C29
22U_0805_6.3V6M

2

Under CPU Socket

VDDIO decoupling.

+1.8V

1

C43
22U_0805_6.3V6M

2

3 3

+1.8V

1

C50

0.22U_0603_16V4 Z

2

+1.8V +1.8V

1

C62

0.01U_0402_25V4 Z

2

4 4

+1.8V

1

C77

4.7U_0805_10V4Z

2

1

C44
22U_0805_6.3V6M

2

1

C45

0.22U_0603_16V4 Z

2

1

C46

0.22U_0603_16V4 Z

2

Under CPU Socket

Between CPU Socket and DIMM

1

C51

0.22U_0603_16V4 Z

2

1

C63

0.01U_0402_25V4 Z

2

1

2

A

C78

4.7U_0805_10V4Z

1

C52

0.22U_0603_16V4 Z

2

180 PF Qt 'y fo ll ow the dis tanc e be twee n
CPU s ock et an d DIMM 0. < 2.5i nch>

1

C64
180P_0402_50V8J

2

1

C79

4.7U_0805_10V4Z

2

1

C53

0.22U_0603_16V4 Z

2

1

2

1

2

C65
180P_0402_50V8J

C80

4.7U_0805_10V4Z

1

180P_0402_50V8J

2

B

+CPU_C ORE_0

1

+

2

+CPU_C ORE_0

1

C30
22U_0805_6.3V6M

2

1

C47

C48

180P_0402_50V8J

2

1

C66
180P_0402_50V8J

2

1

C: Ch ang e to N BO C AP

+

C76
220U_Y_4VM

@

2

B

C24
330U_X_2VM_R6M

1

C31
22U_0805_6.3V6M

2

+CPU_C ORE_0

1

C37

0.22U_0603_16V4 Z

2

1

C67
180P_0402_50V8J

2

1

+

C25
330U_X_2VM_R6M

2

1

C32
22U_0805_6.3V6M

2

1

C38

0.01U_0402_25V4 Z

2

1

C33
22U_0805_6.3V6M

2

1

C39
180P_0402_50V8J

2

C

L

+0. 8V ~+1 .1V , 3A
(+- 25 mV_ dc , + -125 mV_ac )

2A , (+- 100 mV_d c,
+- 15 0mV_ ac)

18A /72 0mil /36v ias

+CPU_ CORE_NB

+1.8V

JCPU1E

G4
H2

J9
J11
J13
J15

K6
K10
K12
K14

L4

L7

L9
L11
L13
L15

M2
M6
M8

M10

N7
N9

N11

K16

M16

P16
T16
V16

H25

J17
K18
K21
K23
K25
L17

M18
M21
M23
M25
N17

FOX_P Z6382A-284S-41F_GRIFFIN

Athlon 64 S1
Processor Socket

CONN@

VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12

D

VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8

VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26

VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13

+CPU_CORE_NB decoupling.

+CPU_ CORE_NB

1

C40
22U_0805_6.3V6M

2

VTT decoupling.

+0.9V

1

C54

4.7U_0805_10V4Z

2

+0.9V

1

C68

4.7U_0805_10V4Z

2

Secur ity Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Near CPU Socket Right side.

Near CPU Socket Left side.

Issued Date

1

C55

4.7U_0805_10V4Z

2

1

C69

4.7U_0805_10V4Z

2

C

1

C41
22U_0805_6.3V6M

2

2007/08/02 2008/08/02

1

2

1

C56

0.22U_0603_16V4 Z

2

1

C70

0.22U_0603_16V4 Z

2

C42
22U_0805_6.3V6M

+0.9V

Near Power Supply

1

C: Ch ang e to N BO C AP

+

C49
220U_Y_4VM

2

1

C57

0.22U_0603_16V4 Z

2

1

C71

0.22U_0603_16V4 Z

2

Compal Secret Data

Deciphered Date

1

C58
1000P_0402_25V8J

2

1

C72
1000P_0402_25V8J

2

D

L

10/6 HP

P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2

Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18

1

C59
1000P_0402_25V8J

2

1

C73
1000P_0402_25V8J

2

18A /72 0mil /36v ias

+CPU_C ORE_0+CPU_C ORE_0

+1.8V

1

C60
180P_0402_50V8J

2

1

C74
180P_0402_50V8J

2

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet

E

JCPU 1F

AA4

VSS1

AA11

VSS2

AA13

VSS3

AA15

VSS4

AA17

VSS5

AA19

VSS6

AB2

VSS7

AB7

VSS8

AB9

VSS9

AB23

VSS10

AB25

VSS11

AC11

VSS12

AC13

VSS13

AC15

VSS14

AC17

VSS15

AC19

VSS16

AC21

VSS17

AD6

VSS18

AD8

VSS19

AD25

VSS20

AE11

VSS21

AE13

VSS22

AE15

VSS23

AE17

VSS24

AE19

VSS25

AE21

VSS26

AE23

VSS27

B4

VSS28

B6

VSS29

B8

VSS30

B9

VSS31

B11

VSS32

B13

VSS33

B15

VSS34

B17

VSS35

B19

VSS36

B21

VSS37

B23

VSS38

B25

VSS39

D6

VSS40

D8

VSS41

D9

VSS42

D11

VSS43

D13

VSS44

D15

VSS45

D17

VSS46

D19

VSS47

D21

VSS48

D23

VSS49

D25

VSS50

E4

VSS51

F2

VSS52

F11

VSS53

F13

VSS54

F15

VSS55

F17

VSS56

F19

VSS57

F21

VSS58

F23

VSS59

F25

VSS60

H7

VSS61

H9

VSS62

H21

VSS63

H23

VSS64

J4

VSS65

FOX_P Z6382A-284S-41F_GRIFFIN

Athlon 64 S1
Processor Socket

CONN@

1

C61
180P_0402_50V8J

2

1

C75
180P_0402_50V8J

2

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

Compal Electronics, Inc.

AMD CPU S1G2 PWR & GND

LA-4961P

E

of

7 54Thursday , August 27 , 2009

1.0

A

B

C

D

E

+V_DD R_MCH_REF

JDIMMA

1

VREF

3

DDR_A _D0
DDR_A _D1

1 1

2 2

DDR_CKE 0_DIMMA<5>

DDR_A_BS #2<5>

DDR_A_BS #0<5>
DDR_A_W E#<5>

DDR_A _CAS#<5>
DDR_C S1_DIMMA#<5>

DDR_A _ODT1<5>

3 3

SMB_CK_DAT0<4,6,9,15,21,30>
SMB_CK_CLK0<4,6,9 ,15,21,30>

4 4

A

+3VS

DDR_A _DQS#0
DDR_A _DQS0

DDR_A _D2
DDR_A _D3

DDR_A _D8
DDR_A _D9

DDR_A _DQS#1
DDR_A _DQS1

DDR_A _D10
DDR_A _D11

DDR_A _D16 DDR_A _D20
DDR_A _D17

DDR_A _DQS#2
DDR_A _DQS2

DDR_A _D18
DDR_A _D19

DDR_A _D24
DDR_A _D25

DDR_A_DM 3

DDR_A _D26
DDR_A _D27

DDR_CKE 0_DIMMA

DDR_A_BS #2

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1 DDR_A_MA0

DDR_A_MA10
DDR_A_BS #0
DDR_A_W E#

DDR_A _CAS# DDR_A _ODT0
DDR_C S1_DIMMA#

DDR_A _ODT1

DDR_A _D32
DDR_A _D33

DDR_A _DQS#4
DDR_A _DQS4

DDR_A _D34
DDR_A _D35

DDR_A _D40
DDR_A _D41

DDR_A_DM 5

DDR_A _D42
DDR_A _D43

DDR_A _D48
DDR_A _D49

DDR_A _DQS#6
DDR_A _DQS6

DDR_A _D50
DDR_A _D51

DDR_A _D56
DDR_A _D57

DDR_A_DM 7

DDR_A _D58
DDR_A _D59

1

C97

0.1U_0402_16V4Z

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

TYCO_292527-4

CONN@

9/2 0 SP0 70 00B Z0 0/SP 07000 EU00
DDR 2 SOC KE T H 9.2 (REV)

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

NC
DM2
VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

A7
A6

VDD

A4
A2

A0
VDD
BA1

RAS#

S0#

VDD

ODT0

NC/A13

VDD

NC

VSS

DQ36
DQ37

VSS
DM4
VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS
CK1

CK1#

VSS
DM6
VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS
SAO
SA1

GND

B

+1.8V+1.8V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202

DDR_A _D4
DDR_A _D5

DDR_A_DM 0

DDR_A _D6
DDR_A _D7

DDR_A _D12
DDR_A _D13

DDR_A_DM 1

DDR_A _D14
DDR_A _D15

DDR_A _D21

DDR_A_DM 2

DDR_A _D22
DDR_A _D23

DDR_A _D28
DDR_A _D29

DDR_A _DQS#3
DDR_A _DQS3

DDR_A _D30
DDR_A _D31

DDR_CKE 1_DIMMA

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2

DDR_A_BS #1
DDR_A _RAS#
DDR_C S0_DIMMA#

DDR_A_MA13

DDR_A _D36
DDR_A _D37

DDR_A_DM 4

DDR_A _D38
DDR_A _D39

DDR_A _D44
DDR_A _D45

DDR_A _DQS#5
DDR_A _DQS5

DDR_A _D46
DDR_A _D47

DDR_A _D52
DDR_A _D53

DDR_A_DM 6

DDR_A _D54
DDR_A _D55

DDR_A _D60
DDR_A _D61

DDR_A _DQS#7
DDR_A _DQS7

DDR_A _D62
DDR_A _D63

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR _A_D[0..6 3]

DDR_A _DM[0..7]

DDR _A_DQS[0. .7]

DDR_A _MA[0..15]

DDR_A _DQS#[0.. 7]

DDR_A _CLK0 <5>
DDR_A _CLK#0 <5>

+V_DD R_MCH_REF

1

C90

2

1000P_0402_25V8J

0.1U_0402_16V4Z

DDR_CKE 1_DIMMA <5>

DDR_A_BS #1 <5>
DDR_A _RAS# <5>
DDR_CS0_D IMMA# <5>

DDR_A_ODT0 <5>

DDR_A _CLK1 <5>
DDR_A _CLK#1 <5>

C

D

DDR_A_MA6
DDR_A_MA7
DDR_A_MA11
DDR_A_MA14

DDR_CKE 0_DIMMA
DDR_CKE 1_DIMMA
DDR_A_MA15
DDR_A_BS #2

DDR_A_BS #1
DDR_A_MA0
DDR_A_MA2
DDR_A_MA4

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS #0

DDR_A_W E#
DDR_A _CAS#
DDR_C S1_DIMMA#
DDR_A _ODT1

DDR_A_MA13
DDR_A _ODT0
DDR_C S0_DIMMA#
DDR_A _RAS#

DDR _A_D[0..6 3] <5>

DDR_A _DM[0..7] <5>

DDR_ A_DQS[0.. 7] <5>

DDR_A _MA[0..15] <5>

DDR_A _DQS#[0.. 7] <5>

+1.8V

R44

@

1K_0402_1%

1 2

1

C91

@

2

2007/08/02 2008/08/02

+V_DD R_MCH_REF <9,44>

R45
1K_0402_1%

1 2

Compal Secret Data

Deciphered Date

47_0804_8P4R_5%

R478 47_0402_5%
R479 47_0402_5%
R480 47_0402_5%
R481 47_0402_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

Size Doc ument Number Re v

Cus tom

Date: Sheet of

+0.9V

RP1

18
27
36
45

12
12
12
12

RP3

18
27
36
45

RP4

18
27
36
45

RP5

18
27
36
45

RP6

18
27
36
45

RP7

18
27
36
45

Cross between +1.8V and +0.9V power plan

C720

@

0.1U_0402_16V4Z

Title

Compal Electronics, Inc.

1 2

C81 0.1U_0402_16V4Z

1 2

C82 0.1U_0402_16V4Z

1 2

C83 0.1U_0402_16V4Z

1 2

C84 0.1U_0402_16V4Z

1 2

C85 0.1U_0402_16V4Z

1 2

C86 0.1U_0402_16V4Z

1 2

C87 0.1U_0402_16V4Z

1 2

C88 0.1U_0402_16V4Z

1 2

C89 0.1U_0402_16V4Z

1 2

C92 0.1U_0402_16V4Z

1 2

C93 0.1U_0402_16V4Z

1 2

C94 0.1U_0402_16V4Z

1 2

C95 0.1U_0402_16V4Z

1 2

C96 0.1U_0402_16V4Z

+1.8V

2

2

C721

@

1

0.1U_0402_16V4Z

1

Compa l EMI 6/11

DDRII SO-DIMM 1

LA-4961P

E

8 54Thursday , August 27 , 2009

+1.8V

1.0

A

B

C

D

E

JDIMMB

+V_DD R_MCH_REF<8,44>

1

C100

1 1

2 2

3 3

4 4

1000P_0402_25V8J

DDR_CKE 0_DIMMB<5>

DDR_B_BS #2<5>

DDR_B_BS #0<5>
DDR_B_W E#<5>

DDR_B _CAS#<5>
DDR_C S1_DIMMB#<5>

DDR_B _ODT1<5>

SMB_CK_DAT0<4,6,8,15,21,30>
SMB_CK_CLK0<4,6,8 ,15,21,30>

2

DDR_B _D0
DDR_B _D1

DDR_B _DQS#0
DDR_B _DQS0

DDR_B _D2
DDR_B _D3

DDR_B _D8
DDR_B _D13

DDR_B _DQS#1
DDR_B _DQS1

DDR_B _D10
DDR_B _D11

DDR_B _D21
DDR_B _D17

DDR_B _DQS#2
DDR_B _DQS2

DDR_B _D18 DDR_B _D22
DDR_B _D19

DDR_B _D24
DDR_B _D25

DDR_B_DM 3

DDR_B _D26
DDR_B _D27

DDR_CKE 0_DIMMB

DDR_B_BS #2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS #0
DDR_B_W E#

DDR_B _CAS# DDR_B _ODT0
DDR_C S1_DIMMB#

DDR_B _ODT1

DDR_B _D32
DDR_B _D33

DDR_B _DQS#4
DDR_B _DQS4

DDR_B _D34
DDR_B _D35

DDR_B _D40
DDR_B _D41

DDR_B_DM 5

DDR_B _D42
DDR_B _D43 DDR_B _D47

DDR_B _D48
DDR_B _D49 DDR_B _D53

DDR_B _DQS#6
DDR_B _DQS6

DDR_B _D50
DDR_B _D51 DDR_B _D55

DDR_B _D56
DDR_B _D57

DDR_B_DM 7

DDR_B _D58
DDR_B _D59

+3VS

0.1U_0402_16V4Z

C113

1

2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

TYCO_292527-4

CONN@

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1
RAS#

S0#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

GND

NC

A7
A6

A4
A2
A0

NC

9/2 0 SP0 70 00E T0 0/SP 07000 GN00

+1.8V+1.8V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202

DDR_B _D4
DDR_B _D5

DDR_B_DM 0

DDR_B _D6
DDR_B _D7

DDR_B _D12
DDR_B _D9

DDR_B_DM 1

DDR_B _D14
DDR_B _D15

DDR_B _D20
DDR_B _D16

DDR_B_DM 2

DDR_B _D23

DDR_B _D28
DDR_B _D29

DDR_B _DQS#3
DDR_B _DQS3

DDR_B _D30
DDR_B _D31

DDR_CKE 1_DIMMB

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6DDR_B_MA8

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS #1
DDR_B _RAS#
DDR_C S0_DIMMB#

DDR_B_MA13

DDR_B _D36
DDR_B _D37

DDR_B_DM 4

DDR_B _D38
DDR_B _D39

DDR_B _D44
DDR_B _D45

DDR_B _DQS#5
DDR_B _DQS5

DDR_B _D46

DDR_B _D52

DDR_B_DM 6

DDR_B _D54

DDR_B _D60
DDR_B _D61

DDR_B _DQS#7
DDR_B _DQS7

DDR_B _D62
DDR_B _D63

+3VS

DDR _B_D[0..6 3]

DDR_B _DM[0..7]

DDR _B_DQS[0. .7]

DDR_B _MA[0..15]

DDR_B _DQS#[0.. 7]

DDR_B _CLK0 <5>
DDR_B _CLK#0 <5>

DDR_CKE 1_DIMMB <5>

DDR_B_BS #1 <5>
DDR_B _RAS# <5>
DDR_C S0_DIMMB# <5>

DDR_B _ODT0 <5>

DDR_B _CLK1 <5>
DDR_B _CLK#1 <5>

DDR_ B_D[0..63 ] <5>

DDR_B _DM[0..7] <5>

DDR_B _DQS[0..7 ] <5>

DDR_B _MA[0..15] <5>

DDR_B _DQS#[0.. 7] <5>

DDR_B_MA6
DDR_B_MA2
DDR_B_MA0
DDR_C S0_DIMMB#

DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA4

DDR_CKE 1_DIMMB
DDR_B_MA15
DDR_CKE 0_DIMMB
DDR_B_BS #2

chang e 8P4 R to 0 402 f or im prove layo ut pl aceme nt. C ompal 12/5

DDR_B_MA8
DDR_B_MA5
DDR_B_MA12
DDR_B_MA9

DDR_B_MA10
DDR_B_BS #0
DDR_B_MA1
DDR_B_MA3

DDR_B _ODT1
DDR_C S1_DIMMB#
DDR_B _CAS#
DDR_B_W E#

DDR_B_BS #1
DDR_B _RAS#
DDR_B _ODT0
DDR_B_MA13

47_0804_8P4R_5%

47_0804_8P4R_5%

R524 47_0402_5%
R525 47_0402_5%
R526 47_0402_5%
R527 47_0402_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

+0.9V

RP8

RP9

RP11

RP12

RP13

RP14

18
27
36
45

18
27
36
45

12
12
12
12

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

12

C98 0.1U_0402_16V4Z

1 2

C99 0.1U_0402_16V4Z

12

C101 0.1U _0402_16V4Z

1 2

C102 0.1U _0402_16V4Z

12

C103 0.1U _0402_16V4Z

1 2

C104 0.1U _0402_16V4Z

12

C105 0.1U _0402_16V4Z

1 2

C106 0.1U _0402_16V4Z

12

C107 0.1U _0402_16V4Z

1 2

C108 0.1U _0402_16V4Z

12

C109 0.1U _0402_16V4Z

1 2

C110 0.1U _0402_16V4Z

12

C111 0.1U _0402_16V4Z

1 2

C112 0.1U _0402_16V4Z

Cross between +1.8V and +0.9V power plan

+1.8V

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

DDRII SO-DIMM 2

LA-4961P

9 54Th urs day, Au gust 27, 2009

E

1.0

A

U4B

D4

GFX_RX0P

C4

GFX_RX0N

A3

GFX_RX1P

B3

GFX_RX1N

C2

GFX_RX2P

C1

GFX_RX2N

E5

GFX_RX3P

F5

GFX_RX3N

G5

GFX_RX4P

G6

AE3
AD4
AE2
AD3
AD1
AD2

AA8

AA7

AA5
AA6

H5
H6

M8

M7

M5
R8

R6
R5

W6
U5
U6
U8
U7

W5

J6
J5
J7
J8
L5
L6

L8
P7

P5

P8

P4
P3
T4
T3

V5

Y8

Y7

Y5

GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

1 1

PCIE_PRX_DTX_P0<25>
PCIE_PRX_DTX_N0<25>
PCIE_PRX_DTX_P1<31>
PCIE_PRX_DTX_N1<31>

PCIE_PRX_DTX_P3<31>
PCIE_PRX_DTX_N3<31>

2 2

PCIE_PRX_DTX_P4<27>
PCIE_PRX_DTX_N4<27>

SB_RX0P<19>
SB_RX0N<19>
SB_RX1P<19>
SB_RX1N<19>
SB_RX2P<19>
SB_RX2N<19>
SB_RX3P<19>
SB_RX3N<19>

PAR T 2 O F 6

PCIE I/F GFX

PC IE I/ F GP P

PCI E I/F SB

PCE_CALRP(PCE_BCALR P)
PCE_CALRN(PCE_BCALR N)

RS880MN_FCBGA528

RS780 M Displa y Port Suppo rt (muxed on GFX)

DP0

DP1

3 3

9/2 0 SA0 00 01Z G0 0( A11 ) S I C 216 -067 4001 -00/ RS78 0M F CBGA5 28P 0FH

GFX_TX0,TX1,TX2 and TX3

AUX0 and HPD0

GFX_TX4,TX5,TX6 and TX7

AUX1 and HPD1

B

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P

GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

GPP_TX0P

GPP_TX0N

GPP_TX1P

GPP_TX1N

GPP_TX2P

GPP_TX2N

GPP_TX3P

GPP_TX3N

GPP_TX4P

GPP_TX4N

GPP_TX5P

GPP_TX5N

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

PCIE_PTX_DRX_P0

AC1

PCIE_PTX_DRX_N0

AC2

PCIE_PTX_DRX_P1

AB4

PCIE_PTX_DRX_N1

AB3
AA2
AA1

PCIE_PTX_DRX_P3

Y1

PCIE_PTX_DRX_N3

Y2

PCIE_PTX_DRX_P4

Y4

PCIE_PTX_DRX_N4

Y3
V1
V2

SB_TX0P_C

AD7

SB_TX0N_C

AE7

SB_TX1P_C

AE6

SB_TX1N_C

AD6

SB_TX2P_C

AB6

SB_TX2N_C

AC6

SB_TX3P_C

AD5

SB_TX3N_C

AE5

AC8
AB8

DPA_TXP0 <18>
DPA_TXN0 <18>
DPA_TXP1 <18>
DPA_TXN1 <18>
DPA_TXP2 <18>
DPA_TXN2 <18>
DPA_TXP3 <18>
DPA_TXN3 <18>
DPB_TXP0 <32>
DPB_TXN0 <32>
DPB_TXP1 <32>
DPB_TXN1 <32>
DPB_TXP2 <32>
DPB_TXN2 <32>
DPB_TXP3 <32>
DPB_TXN3 <32>
DPC_TXP0 <32>
DPC_TXN0 <32>
DPC_TXP1 <32>
DPC_TXN1 <32>
DPC_TXP2 <32>
DPC_TXN2 <32>
DPC_TXP3 <32>
DPC_TXN3 <32>

rem ov e U WB , 1 0/21 HPrem ov e U WB , 1 0/21 HP

C124 0.1U_0402_16V7K
C125 0.1U_0402_16V7K
C126 0.1U_0402_16V7K
C127 0.1U_0402_16V7K
C128 0.1U_0402_16V7K
C129 0.1U_0402_16V7K
C130 0.1U_0402_16V7K
C131 0.1U_0402_16V7K

R46 1.27K_0402_1%

1 2

R47 2K_0402_1%

1 2

C114 0.1U_0402_16V7K

1 2

C115 0.1U_0402_16V7K

1 2

C116 0.1U_0402_16V7K

1 2

C117 0.1U_0402_16V7K

1 2

C118 0.1U_0402_16V7K

1 2

C119 0.1U_0402_16V7K

1 2

C120 0.1U_0402_16V7K

1 2

C121 0.1U_0402_16V7K

1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

C

Display Port

PCIE_PTX_C_DRX_P0 <25>
PCIE_PTX_C_DRX_N0 <25>
PCIE_PTX_C_DRX_P1 <31>
PCIE_PTX_C_DRX_N1 <31>

PCIE_PTX_C_DRX_P3 <31>
PCIE_PTX_C_DRX_N3 <31>
PCIE_PTX_C_DRX_P4 <27>
PCIE_PTX_C_DRX_N4 <27>

SB_TX0P <19>
SB_TX0N <19>
SB_TX1P <19>
SB_TX1N <19>
SB_TX2P <19>
SB_TX2N <19>
SB_TX3P <19>
SB_TX3N <19>

+1.1VS

NIC

Media Card

EXP

WLAN

H_CLKOP0<4>
H_CLKON0<4>
H_CLKOP1<4>
H_CLKON1<4>

H_CTLOP0<4>
H_CTLON0<4>

H_CTLON1<4>

Place within 1"
layout 1:2 (W/S=5mil/10mil)

H_CAD OP[0..15]<4>

H_C ADON[0..15 ]<4> H_C ADIN[0. .15] <4>

H_CAD OP0
H_CAD ON0
H_CAD OP1
H_CAD ON1
H_CAD OP2
H_CAD ON2
H_CAD OP3
H_CAD ON3
H_CAD OP4
H_CAD ON4
H_CAD OP5
H_CAD ON5
H_CAD OP6
H_CAD ON6
H_CAD OP7
H_CAD ON7

H_CAD OP8
H_CAD ON8
H_CAD OP9

H_CAD ON9
H_CAD OP10
H_CAD ON10
H_CAD OP11
H_CAD ON11
H_CAD OP12
H_CAD ON12
H_CAD OP13
H_CAD ON13
H_CAD OP14
H_CAD ON14
H_CAD OP15
H_CAD ON15

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1

R48 301_0402_1%

1 2

D

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

AC24
AC25
AB25
AB24
AA24
AA25

Y22

Y23
W21
W20

V21

V20

U20

U21

U19

U18

T22

T23

AB23
AA22

M22
M23

R21

R20

C23

A24

H_ CADON[0..1 5]

U4A

HT_RXCAD0P

PAR T 1 O F 6

HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_RXCALP
HT_RXCALN

RS880MN_FCBGA528

H_ CADIP[0..1 5]H _CADOP[0. .15]

H_C ADIN[0 ..15]

HYPER TRANSPORT CPU I/F

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P

HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

HT_TXCLK0P

HT_TXCLK0N

HT_TXCLK1P

HT_TXCLK1N

HT_TXCTL0P

HT_TXCTL0N

HT_TXCTL1P

HT_TXCTL1N

HT_TXCALP
HT_TXCALN

E

H_C ADIP[0..15 ] <4>

H_CAD IP0

D24

H_C ADIN0

D25

H_CAD IP1

E24

H_C ADIN1

E25

H_CAD IP2

F24

H_C ADIN2

F25

H_CAD IP3

F23

H_C ADIN3

F22

H_CAD IP4

H23

H_C ADIN4

H22

H_CAD IP5

J25

H_C ADIN5

J24

H_CAD IP6

K24

H_C ADIN6

K25

H_CAD IP7

K23

H_C ADIN7

K22

H_CAD IP8

F21

H_C ADIN8

G21

H_CAD IP9

G20

H_C ADIN9

H21

H_CAD IP10

J20

H_CAD IN10

J21

H_CAD IP11

J18

H_CAD IN11

K17

H_CAD IP12

L19

H_CAD IN12

J19

H_CAD IP13

M19

H_CAD IN13

L18

H_CAD IP14

M21

H_CAD IN14

P21

H_CAD IP15

P18

H_CAD IN15

M18

H24
H25
L21
L20

H_CTLIP0

M24

H_CTLIN0

M25

H_CTLIP1

P19

H_CTLIN1

R18

B24
B25

Place within 1"
layout 1:2 (W/S=5mil/10mil)

H_CLK IP0 <4>
H_CLK IN0 <4>
H_CLK IP1 <4>
H_CLK IN1 <4>

H_CTLIP0 <4>

H_CTL IN0 <4>

H_CTLIP1 <4>H_CTLOP1<4>

H_CTL IN1 <4>

R49 301_0402_1%

1 2

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

RS880-HT/PCIE

LA-4961P

10 54Thu rsd ay, Aug ust 27, 2009

E

1.0

A

1 1

R50

LDT_STOP#<6,19>

CPU_LDT_R EQ#<6,19>

2 2

3 3

1 2

0_0402_5%

R51

1 2

0_0402_5%

+1.8VS

FBMA-L11-160808-221LMT_0603

NB_LDTSTOP#

NB_ALLOW_LDTSTOP

+1.1VS

FBMA-L11-160808-221LMT_0603

+1.8VS

FBMA-L11-160808-221LMT_0603

+1.8VS

FBMA-L11-160808-221LMT_0603

1 2

2.2U_0 603_6.3V4Z

+1.8VS

1 2

L9

L8

1

C140

2

1 2

R56

4.7K_0402_5%

DYN_P WR_EN<43>

1 2

L6

1 2

C136

2.2U_0 603_6.3V4Z

1

C139

2.2U_0 603_6.3V4Z

2

1 2

R57

2.2K_0402_5%

B

+1.8VS

1 2

FBMA-L11-160808-221LMT_0603

L5

1

C135

2.2U_0 603_6.3V4Z

1

2

2

PLT_RST#<19,25 ,27,29,31,34>

NB_PW RGD<21>

+1.8VS

NB_OSC_14.318M<15>

CLK_S BLINK_BCLK<15>
CLK_SB LINK_BCLK#<15>

DDC2_ CLK<17>

DDC2_DAT A<17>
HDMIDAT_UMA<18,32>
HDMICLK_UMA<18,32>
DOCK_AUX+<32>
DOCK_AUX-<32>

R63 5.1K_0402_1%

12

2K_0402_5%

+3VS

+1.8VS

L4

+AVDDQ

C134

2.2U_0 603_6.3V4Z

CRT _HSYNC<14,16>

CRT_ VSYNC<14,16>
CRT_D DC_CLK<16,32>
CRT_D DC_DATA<16,32>

+NB_PLLVDD
+NB_HTPVDD

+VDDA18HTPLL

+VDDA 18PCIEPLL

1 2

R54 300_0402_5%

CLK_NBHT<15>
CLK_NBHT#<15>

NBGFX_CLK<15>
NBGFX_CLK#<15>

12

R65

L2

1 2

BLM18PG121SN1D_0603

L3

0_0603_5%

1

2

D_RED<16>

D_GREEN<16>

D_BLUE<16>

R52 715_0402_1%

R53 0_0402_5%

1 2

+AVDD1

+AVDD2

1

C133

2.2U_0 603_6.3V4Z

2

D_RED

D_GREEN

D_BLUE

1 2

NB_RESET#
NB_PW RGD
NB_LDTSTOP#

NB_ALLOW_LDTSTOP

AUX_CAL<14>

Strap pin

CR T_HSYNC
CRT_V SYNC

AVDD= 150mA

1

C132

2.2U_0 603_6.3V4Z

2

F12
E12
F14

G15

H15
H14

E17
F17
F15

G18
G17

E18
F18
E19
F19

A11
B11

F8
E8

G14

A12
D14
B12

H17

D7
E7

D8
A10
C10
C12

C25
C24

E11
F11

T2

T1

U1

U2

V4

V3

B9

A9

B8

A8

B7

A7

B10

G11

C8

C

U4C

AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)

C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)

RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)

DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SCL(PCE_RCALRN)
DAC_SDA(PCE_TCALRN)

DAC_RSET(PWM_GPIO1)

PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)

VDDA18HTPLL

VDDA18PCIEPLL1
VDDA18PCIEPLL2

SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP

HT_REFCLKP
HT_REFCLKN

REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)

GFX_REFCLKP
GFX_REFCLKN

GPP_REFCLKP
GPP_REFCLKN

GPPSB_REFCLKP(SB_REFCLK P)
GPPSB_REFCLKN(SB_REFCLK N)

I2C_CLK
I2C_DATA
DDC_DATA0/AUX0N(NC)
DDC_CLK0/AUX0P(NC)
DDC_CLK1/AUX1P(NC)
DDC_DATA1/AUX1N(NC)

STRP_DATA

RSVD

AUX_CAL(NC)

PAR T 3 OF 6

RS880MN_FCBGA528

TXOUT_L0P(NC)

TXOUT_L0N(NC)

TXOUT_L1P(NC)

TXOUT_L1N(NC)

TXOUT_L2P(NC)

TXOUT_L2N(DBG_GPIO0)

TXOUT_L3P(NC)

TXOUT_L3N(DBG_GPIO2)

TXOUT_U0P(NC)

TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)

TXOUT_U3P(PCIE_RESET_GPIO5)

CRT/TVOUT

TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

LVTM

PM

TXOUT_U0N(NC)

TXOUT_U2P(NC)
TXOUT_U2N(NC)

TXOUT_U3N(NC)

TXCLK_LP(DBG_GPIO1)

TXCLK_LN(DBG_GPIO3)

VDDLTP18(NC)
VSSLTP18(NC)

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

LVDS_DIGON(PCE_TCALRP)

LVDS_BLON(PCE_RCALRP)

LVDS_ENA_BL(PWM _GPIO2)

CLOCKs PLL PWR

MIS.

TMDS_HPD(NC)

SUS_STAT#(PWM_GPIO5)

THERMALDIODE_P

THERMALDIODE_N

TESTMODE

HPD(NC)

D

LVDS

A22
B22
A21
B21
B20
A20
A19
B19

B18
A18
A17
B17
D20
D21
D18
D19

B16
A16
D16
D17

A13
B13

A15
B15
A14
B14

C14
D15
C16
C18
C20
E20
C22

E9
F7
G12

D9
D10

D12

AE8
AD8

D13

LVDS_A0+ < 17>
LVDS_A0- <17>
LVDS_A1+ < 17>
LVDS_A1- <17>
LVDS_A2+ < 17>
LVDS_A2- <17>

LVDS_B0+ < 17>
LVDS_B0- <17>
LVDS_B1+ < 17>
LVDS_B1- <17>
LVDS_B2+ < 17>
LVDS_B2- <17>

LVDS_ACLK+ <17>
LVDS_ACLK- <17>
LVDS_BCLK+ <17>
LVDS_BCLK- <17>

+VDDLTP18

+VDDLT18

C141

0.1U_0402_16V4Z

ENAVDD

NB_PWM

ENABLT

R60 100K_0402_5%

1 2

1 2

R61 0_0402_5%

NB_THERMAL_DA
NB_THERMAL_DC

1 2

R64

1.8K_0402_5%

1

C137

2.2U_0 603_6.3V4Z

2

1

1

C142

4.7U_0805_10V4Z

2

2

L

ENAVDD <17>

ENABLT <17>

HPD <18>

SUS_STAT# <21>

NB_THERMAL_DA <4>
NB_THERMAL_DC <4>

1

C138

0.1U_0402_16V4Z

2

L10

1 2

FBMA-L11-160808-221LMT_0603

0.0 8A /10mil/1 vias

ENAVDD
ENABLT

HP 2/ 6

HP re quest 12/02

DPC_H PD <32>

E

L7

1 2

FBMA-L11-160808-221LMT_0603

+1.8VS

ins ta ll 10/ 25 H P

R55

1 2

0_0402_5%

R58 10K_0402_5%

1 2

R59 10K_0402_5%

1 2

+1.8VS

INV_PWM <17>

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

RS880 VEDIO/CLK GEN

LA-4961P

11 54Thursday, August 27, 2009

E

1.0

A

B

C

D

E

1 1

0.6 A/ 50mi l/4v ias

2A

C153

4.7U_0805_10V4Z

2A

1

C178

2

4.7U_0805_10V4Z

L

2A

0.1U_0402_16V4Z
C144

1

C143

2

0.4 5A /40mil/3 vias

L

0.1U_0402_16V4Z

1

1

C154

2

2

0.1U_0402_16V4Z

0.5 A/ 50mi l/4v ias

L

2A

1

C162

C161

2

0.1U_0402_16V4Z

0.2 5A /30mil/2 vias

L

1

C180

C179

2

0.1U_0402_16V4Z

+1.8VS

C189

1U_04 02_6.3V4Z

1

C145

2

0.1U_0402_16V4Z

1

C155

2

1

C163

2

0.1U_0402_16V4Z

1

C181

2

0.1U_0402_16V4Z

+1.8VS

1

2

0.1U_0402_16V4Z
C146

1

1

2

2

0.1U_0402_16V4Z
C156

1

2

1

1

C164

2

2

0.1U_0402_16V4Z

1

1

C182

2

2

0.1U_0402_16V4Z

+VDDHT

1

C147

0.1U_0402_16V4Z

2

+VDDHTRX

1

C157

0.1U_0402_16V4Z

2

+VDDHTTX

1

C165

2

0.1U_0402_16V4Z

+VDDA 18PCIE

1

C183

2

0.1U_0402_16V4Z

10/ 07 HP

+1.8V_VDD_SP

J17
K16
L16

M16

P16
R16
T16

H18

G19

F20
E21
D22
B23
A23

AE25
AD24
AC23
AB22
AA21

Y20

W19

V18
U17
T17
R17
P17

M17

J10
P10
K10

M10

L10

W9

H9
T10
R10

Y9
AA9
AB9
AD9
AE9

U10

F9

G9
AE11
AD11

1

C190
1U_0402_6.3V4Z

2

U4E

VDDHT_1

PAR T 5 /6

VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15

VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)

RS880MN_F CBGA528

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8

VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12

POWER

VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

VDD33_1(NC)
VDD33_2(NC)

L

VDDA_ 12=2.5A

+VDDA 11PCIE

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

AE10
AA11
Y11
AD10
AB10

+1.8V_VDD_MEM

AC10

H11
H12

0.7 A/ 60mi l/4v ias

L

1

C1670.1U_0402_16V4Z

2

0.1 5A /30mil/2 vias

L

+3VS

L12

1 2

FBMA-L11-201209-221LMA30T_0805

C148

C149

C150 1U_04 02_6.3V4Z

1 2

C151 1U_04 02_6.3V4Z

1 2

C152 1U_04 02_6.3V4Z

1 2

C158 1U_04 02_6.3V4Z

1 2

C159 0.1U_04 02_16V4Z
C160 0.1U_04 02_16V4Z

7A/ 28 0mil/16vias

1

C1680.1U_0402_16V4Z

2

1

1

1

C1690.1U_0402_16V4Z

2

1

1

C1720.1U_0402_16V4Z

C1700.1U_0402_16V4Z

C1730.1U_0402_16V4Z

C1710.1U_0402_16V4Z

2

2

2

2

+1.8VS

C184 4.7U_0805_10V4Z
C185 0.1U_0402_16V4Z
C186 0.1U_0402_16V4Z
C187 0.1U_0402_16V4Z
C188 0.1U_0402_16V4Z

1 2

1 2

10U_0805_10V4Z

10U_0805_10V4Z

12
12

VDD_C ORE=5A

330U_D2E_2.5VM _R15

1

1

1

C17610U_0805_10V4Z

C1750.1U_0402_16V4Z

C1740.1U_0402_16V4Z

2

2

2

12
12
12
12
12

C1910.1U_0402_16V4Z

C1920.1U_0402_16V4Z

+1.1VS

+NB_VD DC

1

C166

1

C17710U_0805_10V4Z

+

2

2

10/ 09 HP

+1.1VS

4.7U_0805_10V4Z

10/ 09 HP

4.7U_0805_10V4Z

L14

2 2

3 3

+1.2V_HT

+1.8VS

1 2

FBMA-L11-201209-221LMA30T_0805

L15

1 2

FBMA-L11-201209-221LMA30T_0805

4.7U_0805_10V4Z

U4F

A25

VSSAHT1

D23

VSSAHT2

E22

VSSAHT3

G22

VSSAHT4

G24

VSSAHT5

G25

VSSAHT6

H19

VSSAHT7

J22

VSSAHT8

L17

VSSAHT9

L22

VSSAHT10

L24

VSSAHT11

L25

VSSAHT12

M20

VSSAHT13

N22

VSSAHT14

P20

VSSAHT15

R19

VSSAHT16

R22

VSSAHT17

R24

VSSAHT18

R25

VSSAHT19

H20

VSSAHT20

U22

VSSAHT21

V19

VSSAHT22

W22

VSSAHT23

W24

VSSAHT24

W25

VSSAHT25

Y21

VSSAHT26

AD25

VSSAHT27

L12

VSS11

M14

VSS12

N13

VSS13

P12

VSS14

P15

VSS15

R11

VSS16

R14

VSS17

T12

VSS18

U14

VSS19

U11

VSS20

U15

VSS21

V12

VSS22

W11

VSS23

W15

VSS24

AC12

VSS25

AA14

VSS26

Y18

VSS27

AB11

VSS28

AB15

VSS29

AB17

VSS30

AB19

VSS31

AE20

VSS32

AB21

VSS33

K11

VSS34

RS880MN_F CBGA528

PAR T 6 /6

GROUND

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8

VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

VSS10

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

RS880 PWR/GND

LA-4961P

12 54Thursday, August 27, 2009

E

1.0

A

B

C

D

E

U5

MEM_BA0
MEM_BA1

MEM_A12
MEM_A11

1 1

12

R68

@

100_0402_1%

2 2

MEM_A10
MEM_A9
MEM_A8
MEM_A7
MEM_A6
MEM_A5
MEM_A4
MEM_A3
MEM_A2 MEM_A12
MEM_A1
MEM_A0

MEM_CLKN
MEM_CLKP

MEM_CKE

MEM_CS#

MEM_WE#

MEM_RAS#

MEM_CAS#

MEM_DM0
MEM_DM1

MEM_ODT

MEM_DQS_P0
MEM_DQS_N0

MEM_DQS_P1
MEM_DQS_N1

+MEM_VREF

MEM_BA2

@

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

K4N51 163QG-HC25 FBGA84 ~D

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSS1
VSS2
VSS3
VSS4
VSS5

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

MEM_DQ15
MEM_DQ11
MEM_DQ13 MEM_A1
MEM_DQ12 MEM_A2
MEM_DQ8
MEM_DQ10
MEM_DQ9
MEM_DQ14
MEM_DQ3
MEM_DQ7
MEM_DQ1
MEM_DQ6
MEM_DQ5
MEM_DQ0
MEM_DQ4
MEM_DQ2

+1.8V_MEM_VDDQ

12

R69 40.2_0402_1%

12

R70 40.2_0402_1%

+VDDL

+1.8V_MEM_VDDQ

L44

1 2

FBMA-L11-160808-221LMT_0603

1

C196

1U_0603_10V6K

2

Layout Note: 50 mil for VSSDL

10/2 2 HP

+1.8V_MEM_VDDQ

MEM_A0

MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11

MEM_BA0
MEM_BA1
MEM_BA2

MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_ODT

MEM_CLKP
MEM_CLKN

MEM_COMP_P

MEM_COMP_N

U4D

AB12

MEM_A0(NC)

AE16

MEM_A1(NC)

V11

MEM_A2(NC)

AE15

MEM_A3(NC)

AA12

MEM_A4(NC)

AB16

MEM_A5(NC)

AB14

MEM_A6(NC)

AD14

MEM_A7(NC)

AD13

MEM_A8(NC)

AD15

MEM_A9(NC)

AC16

MEM_A10(NC)

AE13

MEM_A11(NC)

AC14

MEM_A12(NC)

Y14

MEM_A13(NC)

AD16

MEM_BA0(NC)

AE17

MEM_BA1(NC)

AD17

MEM_BA2(NC)

W12

MEM_RASb(NC)

Y12

MEM_CASb(NC)

AD18

MEM_WEb(NC)

AB13

MEM_CSb(NC)

AB18

MEM_CKE(NC)

V14

MEM_ODT(NC)

V15

MEM_CKP(NC)

W14

MEM_CKN(NC)

AE12

MEM_COMPP(NC)

AD12

MEM_COMPN(NC)

RS880MN_FCBGA528

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)

MEM_DQ2/DVO_DE(NC)

MEM_DQ3/DVO_D0(NC)

MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)

MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)

MEM_DQ12(NC)

MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)

MEM_DQS1P(NC)

MEM_DQS1N(NC)

MEM_DM0(NC)

MEM_DM1/DVO_D8(NC)

SBD_MEM/DVO_I/F

IOPLLVDD18(NC)

IOPLLVDD(NC)

MEM_VREF(NC)

IOPLLVSS(NC)

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

Y17
W18
AD20
AE21

W17
AE19

AE23
AE24

AD23

AE18

MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15

MEM_DQS_P0
MEM_DQS_N0
MEM_DQS_P1
MEM_DQS_N1

MEM_DM0
MEM_DM1

+NB_I OPLLVDD

+MEM_VREF1

MEM_COMP_P and MEM_COMP_N trace
width >=10mils and 10mils spacing from
other Signals in X,Y,Z directions

15mA

L17

1 2

FBMA-L11-160808-221LMT_0603

1

C193

2.2U_0 603_6.3V4Z

2

+1.8V_ IOPLLVDD

1

2

AMD rec ommends 200 Ohm @ 100Mhz

+1.1VS

C195

0.1U_0402_16V4Z

+1.8VS

L16

1 2

FBMA-L11-160808-221LMT_0603

1

C194

2.2U_0 603_6.3V4Z

2

3 3

1

C197

2

R71

1 2

1K_0402_1%

0.1U_0402_16V4Z

+MEM_VREF

1

C204

2

R73

0.1U_0402_16V4Z

1 2

1K_0402_1%

4 4

A

Side Port d isabl e,VREF need
connect to +1.8VS for DDR2

+1.8V_MEM_VDDQ+1.8V_MEM_VDDQ

1

C198

2

R72

1 2

1K_0402_1%

0.1U_0402_16V4Z

+MEM_VREF1

1

C205

2

R74

0.1U_0402_16V4Z

1 2

1K_0402_1%

B

+1.8V_MEM_VDDQ

2

C199

1

2

C200

1

1U_0402_6.3V4Z

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C201

2

1U_0402_6.3V4Z

1

1

C203

C202

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

2007/08/02 2008/08/02

C

10/ 07 HP

220 ohm @ 100MHz,2A

22U_0805_6.3V6M

Compal Secret Data

Deciphered Date

+1.8VS

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

RS880 Side-Port DDR2 SDRAM

LA-4961P

13 54Thursday, August 27, 2009

E

1.0

A

B

C

D

E

1 1

2 2

RS78 0 DF T_G PIO5 mux at CRT_VS YNC pull low to 3K

CRT_V SYNC<11,16>

AUX_CAL<11>

1 2

R77 150_0402_1%

12

R75 1K_0402_5%

12

R76 1K_0402_5%@

+3VS

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

Enables the Test Debug Bus using GPIO.
1 : Disable (RS780) Enable (RX780)
0 : Enable (RS780) Disable (RX780)
PIN: RX780:NB_TV_C; RS740: RS740_DFT_GPIO5; RS780: VSYNC#

3 3

DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb

RX780: Enables the Test Debug Bus using PCIE bus
1 : Disable ( Can still be enabled using nbcfg register access )

RS78 0 us e H SYNC to enable SIDE PORT (internal pull hig h)

CRT _HSYNC<11,16>

4 4

A

B

12

R78 3K_0402_5%

12

R79 3K_0402_5%@

+3VS

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

0 : Enable

RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)

1. Disable (RS740/RS780)
0 : Enable (RS740/RS780)

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

D

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

RS880 STRAPS

LA-4961P

14 54Thursday, August 27, 2009

E

1.0

A

B

C

D

E

L45

NB_OSC_14.318M

1 2

R93 90.9_0402_1%

12

CLK_P CIE_WLAN_REQ#

12

100M D IFF
100M D IFF

100M D IFF(IN/OU T)*

+VDDC LK_IO

1

2

EXP

WLAN

CRD_R EQ#

0.1U_0402_16V4Z

1

C214

2

SMB_CK_CLK0<4,6,8, 9,21,30>
SMB_CK_DAT0<4,6,8,9,21 ,30>

CLK_P CIE_MCARD#<27>

CLK_P CIE_MCARD<27>

1

C215

2

0.1U_0402_16V4Z

CLK_PCIE_EXP#<31>

CLK_PCIE_EXP<31>

NB_OSC_14.318M <11>

0.1U_0402_16V4Z

C216

1

2

C217

0.1U_0402_16V4Z

22P_0402_50V8J

C218

2

1

C225

2

0.1U_0402_16V4Z

1

Rou tin g t he tr ace at l eas t 10mil

+3VS_CLK

+VDDC LK_IO

B

+3VS

1

C219

2

CLK_XTAL_OUT

CLK_XTAL_IN

Y1

12

14.31818MHZ_20P_6X1430004201

1

C226

22P_0402_50V8J

2

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

+3VS_CLK

+VDDC LK_IO

17
18

1 2

FBMA-L11-201209-221LMA30T_0805

10/ 6 H P

71

72

73

U6

GND

VSS_48

SCL
SDA
VDD_DOT
SRC_7#/27M
SRC_7/27M_SS
VSS_DOT
SRC_5#
SRC_5
SRC_4#
SRC_4
VSS_SRC
VDD_SRC_IO
SRC_3#
SRC_3
SRC_2#
SRC_2
VDD_SRC
VDD_SRC_IO

VSS_SRC19SRC_1#20SRC_121SRC_0#22SRC_023CLKREQ_0#24ATIGCLK_2#25ATIGCLK_226VSS_ATIG27VDD_ATIG_IO28VDD_ATIG29ATIGCLK_1#30ATIGCLK_131ATIGCLK_0#32VSS_SB_SRC36SB_SRC_135SB_SRC_1#34ATIGCLK_0

Secur ity Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.2V_HT

FBMA-L11-201209-601LMT_0805~D

10/2 2 HP

1 1

2 2

3 3

NB_OSC_14.318M_R

+3VS_CLK

4 4

NB CLOCK INPUT TABLE

NB CL OCKS

HT_REFCLKP

HT_REF CLKN

REFCLK_P

REFCL K_N

GFX_REFCLK 100M D IFF

1 2

22U_0805_6.3V6M

1 2

R91 158_0402_1%

R94 10K_0402_5%

R95 10K_0402_5%

RX780 RS780

100M D IFF
100M D IFF

14M SE (1.8V) 14M SE (1.1V)
NC vr ef

A

L43

CLK_48M_USB_R

+3VS_CLK

CLK_XTAL_IN

CLK_XTAL_OUT

66

67

68

69

VDD_48

XTAL_IN

48MHz_17048MHz_0

XTAL_OUT

Issued Date

+3VS_CLK

R492

R84 33_0402_5%

1 2

27M_SEL

NB_OSC_14 .318M_R

SEL_SATA

64

63

65

VSS_REF

REF_2/SEL_27

REF_1/SEL_SATA

REF_0/SEL_HTT66

+VDDC LK_IO

C

1

C206
22U_0805_6.3V6M

2

+3VS_CLK

10K_0402_5%

C667

@

+3VS_CLK

+3VS_CLK

62

61

60

59

58

57

VSS_HTT

VDD_HTT

VDD_REF

HTT_0/66M_0

HTT_0#/66M_1

33

+3VS_CLK

chang e CLK _PCIE_ CARD/ # fro m Pin 25,26 to P in22, 23 HP 12/8

CRD_R EQ#

1

C207

0.1U_0402_16V4Z

2

1

C220

0.1U_0402_16V4Z

2

R82 22_0402_5%

CLK_SB_14M <19>

12

12

12P_0402_50V8J

1 2

R86 4.7K_0402_5%

CLK_C PU_BCLK_R

CLK_C PU_BCLK#_R

56

55

PD#

CPU_K8_0

CPU_K8_0#

VDD_CPU

VDD_CPU_I/O

VSS_CPU
CLKREQ_1#
CLKREQ_2#

VDD_A
VSS_A

VSS_SATA

SRC_6/SATA

SRC_6#/SATA#

VDD_SATA
CLKREQ_3#
CLKREQ_4#

SB_SRC_SLOW#

SB_SRC_0

SB_SRC_0#

VDD_SB_SRC

VDD_SB_SRC_IO

ICS9L PRS476EKLFT_QFN72_10x10

CLK_SB LINK_BCLK <11>
CLK_SB LINK_BCLK# <11>
NBGFX_CLK <11>
NBGFX_CLK# <11>

CRD_R EQ# <21,31>
CLK_P CIE_CARD <31>
CLK_P CIE_CARD# <31>
CLK_P CIE_LAN <25>
CLK_P CIE_LAN# <25>

2007/08/02 2008/08/02

R85 33_0402_5%
R523 33_0402_5%

+3VS_CLK

1 2

R87 0_0402_5%

1 2

R89 0_0402_5%

54
53
52
51
50
49
48
47
46
45
44
43

10/ 29 HP

42
41
40
39
38
37

NB GF X

Compal Secret Data

Deciphered Date

1

C208

0.1U_0402_16V4Z

2

1

C221

0.1U_0402_16V4Z

2

C2244.7P_0402_50V8C

1 2

1 2

1 2

1 2
1 2

+3VS_CLK
+VDDC LK_IO

CLK_P CIE_LAN_REQ#_R
CLK_P CIE_WLAN_REQ#

+3VS_CLK

CPPE_ NC#_R

1 2

R90 10K_0402_5%

+3VS_CLK
+VDDC LK_IO

1 2

R49310K_0402_5%

C66812P_0402_50V8J @

1 2

SB LIN K

Media Card

NIC

1

C209

0.1U_0402_16V4Z

2

1

C222

0.1U_0402_16V4Z

2

R88
261_0402_1%@

CLK_P CIE_WLAN_REQ# <27>

+3VS_CLK

+3VS_CLK

CLK_SBSRC _BCLK <19>
CLK_SBSRC _BCLK# <19>

CLK_P CIE_LAN_REQ#_R

D

1

C210

0.1U_0402_16V4Z

2

1

C223

0.1U_0402_16V4Z

2

CLK_48M_USB <21>

CLK_14M_KBC <33>
CLK_14M_SIO <34>
CLK_NBHT <11>
CLK_NBHT# <11>

CLK_CP U_BCLK <6>

1

C211

0.1U_0402_16V4Z

2

add C LK_14 M_SIO for s uper IO. C ompal 12/4

NB

CP U

CLK_CP U_BCLK# <6>

For I CS ne ed to p ull high .
For S LG i s NC

SB SRC

+3VS

R92

8.2K_0402_5%

1 2

DMN66D0LDW-7_SOT363-6

CPPE_NC#<20,21,31>

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

1

C212

0.1U_0402_16V4Z

2

LP_EN# <21,25>

5

3

4

Q6B

+3VS

R96

8.2K_0402_5%

12

2

6 1

DMN66D0LDW-7_SOT363-6
Q6A

Compal Electronics, Inc.

Clock generator

LA-4961P

E

1

C213

1U_0402_6.3V4Z

2

CPPE_ NC#_R

15 54Thu rsday, August 27, 2009

1.0

A

B

C

D

E

D_ RED
D_ GRE EN
D_ BLUE

R9 8 1 50_04 02_1%

R9 7 1 50_04 02_1%

R9 9 1 50_04 02_1%

12

12

1 1

12

D_ RED<11 >

D_ GREE N<11>

D_ BLUE<11>

D_ RED

D_ GRE EN

D_ BLUE

Pl ace cloce to NB

L

L19
CS0 805-6 8NJ-S _0805

1 2

L21
CS0 805-6 8NJ-S _0805

1 2

L23
CS0 805-6 8NJ-S _0805

1 2

10/ 29 H P

2 2

+5VS

C2 34

0.1U _0402 _16V4Z

1 2

+5VS

C2 35

0.1U _0402 _16V4Z

1 2

cha nge t o L CL f iltt er 10 /23 H P

L20
CS0 805-6 8NJ-S _0805

1 2

L22
CS0 805-6 8NJ-S _0805

1 2

L24
CS0 805-6 8NJ-S _0805

27P _0402_5 0V8J

C2 31

1

1

2

2

1 2

27P _0402_5 0V8J

27P _0402_5 0V8J

C2 33

C2 32

1

2

VGA _RED< 32>

VGA _GRN<32>

VGA _BLU< 32>

RE D_R <32>

GR EEN _R <32>

BL UE_R <32>

R4 63 140_04 02_1%

12

12

21

D4
CH 491D _SC59

2 1

C2 27

0.1U _0402 _16V4Z

1

2

RE D

D_ DDC DATA

GR EEN

B LUE

D_ DDC CLK

SUY IN_07 0912H R015S 239Z R_15P

10/ 23 H P

F1

1.1A _6VD C_FU SE

@

C6 88

10P _0402_50 V8J

10P _0402_50 V8J

1

1

2

2

R4 73 0_08 05_5%

1 2

R4 75 0_08 05_5%

1 2

R4 77 0_08 05_5%

1 2

R4 72

1 2

0_08 05_5%

R4 74

1 2

0_08 05_5%

R4 76

1 2

0_08 05_5%

R4 61 140_04 02_1%

R4 62 140_04 02_1%

12

@

@

C6 87

C6 86

10P _0402_50 V8J

1

2

W=40mi ls

JC RT1

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

+C RTVD D+R CRT_ VCC+5VS

16
17

CO NN@

Pl ace clo ce to JC RT1

1

5

M74 VHC1G T125 DF2G SC 70

CR T_H SYN C<1 1,14>

CR T_V SYN C< 11,14>

3 3

P

A2Y

G

3

U7

4

OE#

HS Y NC

1

5

U8

P

V SY NC

4

OE#

A2Y

G

M74 VHC1G T125 DF2G S C70

3

Pl ace cloce to NB

L

R1 00 0_04 02_5%

1 2

R1 05 0_04 02_5%

1 2

5P_ 0402_50 V8C

C2 36

1

2

D_ HS YN C

D_ VSY NC

1

C2 37

5P_ 0402_50 V8C

2

D_ HS YNC <32>

D_ VSY NC <3 2>

D_ DDCD ATA<1 1,32>

D_ DDC CLK<11,32>

+C RTVD D

D5

4

GR EEN

01/16 ESD

D_ VSY NC

bec aus e RS8 80 co nfi rmed +5V torel ence on I2 C DDC ,
lev el- sh ift er is not requi red. (DB2 11/2 8)

VIN

3

IO2

CM1 293A-0 2SR_SOT14 3-4@

+C RTVD D

D6

4

3

CM1 293A-0 2SR_SOT14 3-4

@

+C RTVD D

4

3

CM1 293A-0 2SR_SOT14 3-4@

4.7K _0402 _5%

12

VIN

IO2

R1 03

D7

+5VS

RE D

2

IO1

1

GND

B LUE

2

IO1

1

GND

D_ HS YN C

2

IO1

VIN

1

GND

IO2

R1 04

4.7K _0402 _5%

12

CR T_DDC _DAT A <11 ,32>

CR T_D DC_CL K <11 ,32>

layout note: D_HSYNC
& D_VS YNC sh ould be
routed to do cking
connec tor th en to VGA
connec tor

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/09/15 2009/09/15

Compal Secret Data

Deciphered Date

D

Pl ace cloce to NB

L

Title

Size D ocum ent N umber Re v

Da te: She et of

Compal Electronics, Inc.

CRT Connector

LA -49 61P

E

16 54Thur sday , Au gust 27, 2 009

1. 0

5

4

3

2

1

LCD/PANEL BD. CONN.

+5VS

D1 0

4

D D

IN VPWR _B+

+L CDV DD

+5V _WEBCAM

USB 20_P 4_R

4

1

L49

C6 55

1 2

4

1

1 2

680P _0402_50V 7K

1

2

US B20_ N4_R

3

3

2

2

compal EMI , 6/13

1 2

1 2

C6 56

LVD S_ACLK -<1 1>

LVD S_ACLK +<11>

LVD S_A0-<11>
LVD S_A0+<11>
LVD S_A1-<11>
LVD S_A1+<11>
LVD S_A2-<11>
LVD S_A2+<11>

C C

USB 20_P4<21>
USB 20_N4<21>

B B

R4 37 0_04 02_5%@

WCM 2012F 2S-900T 04_0805

R4 38 0_04 02_5%@

+3VS

47P _0402_5 0V8J@

12

JLV DS1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

ACE S_87 216-4016_40 P

CO NN@

Compal ME request 12/03

USB 20_P 4_R
US B20_ N4_R

DD C2_ CLK

R4 524.7K _0402 _5%

DD C2_DA TA

R4 534.7K _0402 _5%

47P _0402_5 0V8J@

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

1 2

R4 39 0_08 05_5%

680P _0402_50V 7K

C6 58

C6 57

1

12

2

DA C_B RIG
CAM ERA_ OFF#
INV _PWMDI SP_O FF#

DD C2_DA TA
DD C2_ CLK

+3VS

680P _0402_50V 7K

INV _PWM <11>

DD C2_DA TA <1 1>
DD C2_ CLK <1 1>

LVD S_B2+ < 11>
LVD S_B2- <11>
LVD S_B1+ < 11>
LVD S_B1- <11>
LVD S_B0+ < 11>
LVD S_B0- <11>

LVD S_BCLK + <11>

LVD S_BCLK - <11>

DA C_B RIG

+3VS

R5 07

1.8K _0402 _1%

R5 06

1K_ 0402_1%

For CC FL p anel

+3VS+LC DV DD IN VPWR _B+ B+

12

C6 54

US B20_ N4_R

12

12

VIN

3

IO2

CM1 293A-0 2SR_SOT14 3-4

USB 20_P 4_R

2

IO1

1

GND

ESD 2/18

INV _PWM

1

680P _0402_5 0V7K
C6 53

2

LCD POWER CIRCUIT

EN AVD D<11>

CAM ERA_ OFF<20>

DMN 66D0L DW-7 _SOT363- 6

R1 19

100K _0402_1 %

Q7A

4/1 1 HP

+3VS

12

12

R1 16
100_ 0402_1%

61

R1 18 4 7K_04 02_5%

2

2

IN

12

DI SP_O FF#

+5VS +5V _WEBCAM

1U_0 603_1 0V4Z

C2 42

1

2

R4 47
100K _0402_1 %

5

1 2

0.1U _0402 _16V4Z

1

OUT

Q28
DTC 124EK AT146_SC 59-3

GND

3

4/1 1 HP

4.7K _0402_5 %
R1 12

12

HP, 4/17

CAM ERA_ OFF#

3

DMN 66D0L DW-7 _SOT363- 6

Q7B

4

+L CDV DD+L CDV DD +3VS

D

1 3

1

1

C2 50

C2 51

4.7U _0805 _10V4Z

2

2

solved pane l flashing issue HP 2/6

R5 40

1 2

2 1

CH75 1H-4 0PT_S OD323-2

G

2

ENA BLT

2K_ 0402_5%

D4 2

LI D_SW #

47P _0402_50 V8J

0.01 U_040 2_16V7K

@

C2 43

1

12

C6 72

2

Q26

S

AP2 301GN 1P_SOT23

R1 17 1M_ 0402_5%

1 2

C2 49 0.1U _0402 _16V4Z

1 2

12

C2 44

1

2

R1 08

100K _0402_1 %

4.7U _0805 _10V4Z

0.1U _0402 _16V4Z

C2 45

1

2

1

C2 52

4.7U _0805 _10V4Z

2

ENA BLT <11>

LI D_SW # <21, 28,33>

HP, 4/8

+5VS

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/09/15

Compal Secret Data

Deciphered Date

2

Title

Size D ocum ent N umber Re v

Da te: She et of

Compal Electronics, Inc.

LCD CONN & Q-Switch & GPIO Ext.

LA -49 61P

1

17 54Thur sday , Au gust 27, 2 009

1. 0

A

B

C

D

E

10/ 17 HP

C502

12

1 1

HDMIDAT_UMA<11,32>

HDMICLK_UMA<11,32>

2 2

HP 12 /02

3 3

100K_0402_5%

4 4

R125

1 2

HP 2/ 6

Q9B

4

DMN66D0LDW-7_SOT363-6

5

HDMI_ HPD

3

HPD <11>

DOCK _ID <20,32>

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

HP 12 /02

DMN66D0LDW-7_SOT363-6

@

C719

1U_0603_10V6K

Q98A

2

4

5

DMN66D0LDW-7_SOT363-6

12

1 2

61

DMN66D0LDW-7_SOT363-6

Q98B

DMN66D0LDW-7_SOT363-6

3

61

Q9A

DOCK _ID

add l evel sfit f or di splay port. HP 1 2/15

HP, 6 11

2

R569
470K_0402_5%

3

4

2

Q113A

DPB_HPD

61

R568

470K_0402_5%

1 2

Q113B
DMN66D0LDW-7_SOT363-6

DOCK _ID

5

R487

Q20A

6 1

6 1

Q21A

1 2

R535

200K_0402_5%

B+

12

5.1M_0402_5%

+3VS

1 2

0.1U_0402_16V4Z

DMN66D0LDW-7_SOT363-6

2

2

DMN66D0LDW-7_SOT363-6

0.1U_0402_16V4Z

DPB_H PD <32>

R488

1M_0402_5%

C503

B+

Q20B

4

5

5

4

Q21B

12

NB_CA D

compa l 2/19

+3VS

R409

100K_0402_5%

1 2

3

3

DP AUX-

DP AUX+

R410
100K_0402_5%

1 2

DMN66D0LDW-7_SOT363-6

B+ +3VS

1 2

61

Q22A

R411
100K_0402_5%

2

R412
100K_0402_5%

1 2

Q22B

3

DMN66D0LDW-7_SOT363-6

NB_CA D

5

4

10/ 25 HP

+3VS

21

D46

@

SDM10U45-7_SOD523-2

21

F2

NANOS MDC050F 0 .5A 13.2V POLY-FUSE

DPA_TXN3<10>

DPA_TXP3<10>

DPA_TXN2<10>

DPA_TXP2<10>

DPA_TXN1<10>

DPA_TXP1<10>

DPA_TXN0<10>

DPA_TXP0<10>

@

R485

1 2

HDMI_ HPD
DP AUX-

DP AUX+

1 2

+DPA_VCC

0_1206_5%

R484

1

2

Display port Connector

0_1206_5%

+DPA_3V

1

C693

C694

10U_0805_10V4Z

R_DPA_TXN3

R_DPA_TXP3
R_DPA_TXN2

R_DPA_TXP2
R_DPA_TXN1

R_DPA_TXP1
R_DPA_TXN0

R_DPA_TXP0

12

200K_0402_5%
R486

JDP1

20

DP_PWR

19

RTN

18

HP_DET

17

AUX_CH-

16

GND

15

AUX_CH+

14

GND

13

CA_DET

12

LAN3-

11

LAN3_shield

10

LAN3+

9

LAN2-

8

LAN2_shield

7

LAN2+

6

LAN1-

5

LAN1_shield

4

LAN1+

3

LAN0-

2

LAN0_shield

1

LAN0+

MOLEX_105020-0001_20P

2

0.01U_0402_16V7K

C6950 .1U_0402_16V4Z

12

C6960 .1U_0402_16V4Z

12

C6970 .1U_0402_16V4Z

12

C6980 .1U_0402_16V4Z

12

C6990 .1U_0402_16V4Z

12

C7000 .1U_0402_16V4Z

12

C7010 .1U_0402_16V4Z

12

C7020 .1U_0402_16V4Z

12

GND
GND
GND
GND

21
22
23
24

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

Display port

LA-4961P

18 54Thursday, August 27, 2009

E

1.0

A

+3VALW

C263

12

0.1U_0402_16V4Z@

NB_RST#_R

1 1

2 2

3 3

+3VS

H_PW RGD_CPU<6>

4 4

5

2

P

B

Y

1

A

G

3

12

R149 33_0402_5%

R152 20M_0402_5%@

1 2

C281

1 2

18P_0402_50V8J

R154

20M_0402_5%

C282

1 2

18P_0402_50V8J

Close to SB

R165 10K_0402_5%

U9

PLT_RST#

4

NC7SZ08P5X_NL_SC70-5@

12

12

PLT_RST# <11 ,25,27,29,31,34>

Y2

4

OSC

1

OSC

32.768KHZ_12.5PF_Q13MC 14610050_10PPM

PROCHOT#

R167

1 2

0_0402_5%

+1.2V_HT

3

NC

2

NC

Check AMD need pul l l ow or not

SB_RX0P<10>
SB_RX0N<10>
SB_RX1P<10>
SB_RX1N<10>
SB_RX2P<10>
SB_RX2N<10>
SB_RX3P<10>
SB_RX3N<10>

SB_TX0P<10>
SB_TX0N<10>
SB_TX1P<10>
SB_TX1N<10>
SB_TX2P<10>
SB_TX2N<10>
SB_TX3P<10>
SB_TX3N<10>

+PCIE _VDDR

L29

1 2

FBMA-L11-201209-221LMA30T_0805

SB_32KHI

CLK_SB_14M<15>

SB_32KHO

1 2

R142 8.2K_0402_5%@

C264 0.1U_0402_16V7K

1 2

C265 0.1U_0402_16V7K

1 2

C266 0.1U_0402_16V7K

1 2

C267 0.1U_0402_16V7K

1 2

C268 0.1U_0402_16V7K

1 2

C269 0.1U_0402_16V7K

1 2

C270 0.1U_0402_16V7K

1 2

C272 0.1U_0402_16V7K

1 2

C279

10U_0805_10V4Z

Close to SB

CLK_SB SRC_BCLK<15>
CLK_SBSRC _BCLK#<15>

CPU_LDT_R EQ#<6,11>

LDT_STOP#<6,11>

B

NB_RST#_R

R150 562_0402_1%
R151 2.05K_0402_1%

1

1

2

2

R451 0_0402_5%

R155 1K_0402_5%

LDT_RST#<6>

NB_RST#_R

SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C

12
12

+SB_PC IEVDD

C280

1U_0402_6.3V4Z

CPU_LDT_R EQ#
PROCHOT#
H_PW RGD_SBH_PW RGD_SB

12

12

SB_32KHI

SB_32KHO

U10A

N2

A_RST#

V23

PCIE_TX0P

V22

PCIE_TX0N

V24

PCIE_TX1P

V25

PCIE_TX1N

U25

PCIE_TX2P

U24

PCIE_TX2N

T23

PCIE_TX3P

T22

PCIE_TX3N

U22

PCIE_RX0P

U21

PCIE_RX0N

U19

PCIE_RX1P

V19

PCIE_RX1N

R20

PCIE_RX2P

R21

PCIE_RX2N

R18

PCIE_RX3P

R17

PCIE_RX3N

T25

PCIE_CALRP

T24

PCIE_CALRN

P24

PCIE_PVDD

P25

PCIE_PVSS

N25

PCIE_RCLKP/NB_LNK_CLKP

N24

PCIE_RCLKN/NB_LNK_CLKN

K23

NB_DISP_CLKP

K22

NB_DISP_CLKN

M24

NB_HT_CLKP

M25

NB_HT_CLKN

P17

CPU_HT_CLKP

M18

CPU_HT_CLKN

M23

SLT_GFX_CLKP

M22

SLT_GFX_CLKN

J19

GPP_CLK0P

J18

GPP_CLK0N

L20

GPP_CLK1P

L19

GPP_CLK1N

M19

GPP_CLK2P

M20

GPP_CLK2N

N22

GPP_CLK3P

P22

GPP_CLK3N

L18

25M_48M_66M_OSC

J21

14M_X1

J20

14M_X2

A3

X1

B3

X2

ALLOW_LDTSTP
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#

RT C X TAL

F23
F24

F22
G25
G24

218S7EALA11FG_BGA528_SB700

C

SB710

Part 1 of 5

PC I EX PR ES S INTE RFA CE

C PU

PCICLK5/GPIO41

PC I CL KS

PC I IN TE RF ACE

REQ3#/GPIO70
REQ4#/GPIO71

GNT3#/GPIO72
GNT4#/GPIO73

INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36

CL OCK GEN ERAT OR

L PC

LDRQ1#/GNT5#/GPIO68

BMREQ#/REQ5#/GPIO65

INTRUDER_ALERT#

RTC

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4

PCIRST#

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8

AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CBE0#
CBE1#
CBE2#
CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR

STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#

GNT0#
GNT1#
GNT2#

CLKRUN#

LOCK#

LPCCLK0
LPCCLK1

LAD0
LAD1
LAD2
LAD3

LFRAME#

LDRQ0#

SERIRQ

RTCCLK

VBAT

CLK_PCI_TPM_R

P4

CLK_P CI_SIO_R

P3

PCI_C LK2_R

P1

CLK_P CI_KBC_R

P2

CLK_P CI_DB_R

T4

PCI_C LK5_R

T3

N1

U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3

PCI_AD23

Y2

PCI_AD24

AA2

PCI_AD25

AB4

PCI_AD26

AA1

PCI_AD27

AB3

PCI_AD28

AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5

R153 33_0402_5%

AD6
V5

AD3
AC4
AE2

PCI_P IRQH#

AE3

CLK_P CI_EC_R

G22

LPCCLK1

E22
H24
H23
J25
J24
H25
H22
AB8

BMREQ#

AD7
V15

C3

R166

C2

1 2

1M_0402_5%

B2

0.1U_0402_16V4Z

R143 22_0402_5%

1 2

R144 22_0402_5%

1 2

R145 22_0402_5%

1 2

R146 22_0402_5%

1 2

R147 22_0402_5%

1 2

R148 22_0402_5%

1 2

1 2

R156 0_0402_5%

R158 33_0402_5%

1 2

+RTCVCC

2

C679

1

D

PCI_RST# <27,29>

PCI_AD23 <22>
PCI_AD24 <22>
PCI_AD25 <22>
PCI_AD26 <22>
PCI_AD27 <22>
PCI_AD28 <22>

PCI_S ERR# <29,33>

PM_CLKRUN# <29,33,34>

12

CLK_P CI_EC

LPCCLK1 <22>
LPC_LAD0 <27,29,33,34>
LPC_LAD1 <27,29,33,34>
LPC_LAD2 <27,29,33,34>
LPC_LAD3 <27,29,33,34>
LPC_LFRAME# <27,29,33,34>
LPC_LD RQ#0 <34>

SIRQ <29,33,34>

RTC_CLK <22>

STRAP PIN

W=2 0mi ls

C681

1

1U_0603_10V4Z

2

Pla ce ne ar IBEX -M

CLK_PCI_TPM
CLK_P CI_SIO
PCI_CLK2
CLK_P CI_KBC
CLK_P CI_DB
PCI_CLK5

ACCEL_INT# <30>

CLK_P CI_EC <22>

STRAP PIN
EC & Debug

for b atter y life cycl e iss ue ,H P 2/11

CLK_PCI_TPM <29>
CLK_P CI_SIO <34>
PCI_CLK2 <22>
CLK_P CI_KBC <22,33>
CLK_P CI_DB <22,29>
PCI_CLK5 <22>

CLK_PCI_TPM
CLK_P CI_SIO
PCI_CLK2
CLK_P CI_KBC
CLK_P CI_DB
PCI_CLK5
CLK_P CI_EC

LPCCLK1

C271 22P_0402_50V8J
C273 22P_0402_50V8J
C274 22P_0402_50V8J
C275 22P_0402_50V8J
C276 22P_0402_50V8J
C277 22P_0402_50V8J
C278 12P_0402_50V8J

R495 33_0402_5%

1 2

for 8 0 p or t d ebu g ca rd 1 0/31

D43

1

DAN202 U_SC70

1 2
1 2
1 2
1 2
1 2
1 2
1 2

LPC_LAD0

LPC_LAD1

LPC_LAD2

LPC_LAD3

LPC_LD RQ#0

BMREQ#

LPCCLK1

2

3

W=2 0mi ls

1 2

1 2

1 2

1 2

1 2

1 2

C676 12P_0402_50V8J

1 2

@

BATT1.1+VRE G3_51125+RTCVCC

R456

1 2

1K_0402_5%

E

CLK_P CI_DEBUG <27>

R15710K_0402_5% @

R15910K_0402_5% @

R16010K_0402_5% @

R16110K_0402_5% @

R16310K_0402_5% @

R16410K_0402_5%

CONN@

JBATT1
E-T_3801-E02N-01R_2P

W=2 0mi ls

+3VS

1

2

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

SB710-PCIE/PCI/ACPI/LPC/RTC

LA-4961P

19 54Thursday, August 27, 2009

E

1.0

A

B

C

D

E

C28310P_0402_50V8J

12

12

Y3

25MHz_20pF_6X25000017

1 1

SATA_STX_C_DRX_P0<24>

HDD

ODD

Dock

Dock

2 2

3 3

SATA_STX_C_DRX_N0<24>

SATA_SRX_C_DTX_N0<24>
SATA_SRX_C_DTX_P0<24>

SATA_STX_C_DRX_P1<24>

SATA_STX_C_DRX_N1<24>

SATA_SRX_C_DTX_N1<24>
SATA_SRX_C_DTX_P1<24>

SATA_STX_DRX_P2<32>

SATA_STX_DRX_N2<32>

SATA_SRX_DTX_N2<32>
SATA_SRX_DTX_P2<32>

SATA_STX_DRX_P3<32>

SATA_STX_DRX_N3<32>

SATA_SRX_DTX_N3<32>
SATA_SRX_DTX_P3<32>

+1.2V_HT

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

1 2

+3VS

C28410P_0402_50V8J

12

C285 0.01U_0402_25V7K

1 2

C286 0.01U_0402_25V7K

1 2

SATA_SRX_C_DTX_N0
SATA_SRX_C_DTX_P0

C287 0.01U_0402_25V7K

1 2

C288 0.01U_0402_25V7K

1 2

SATA_SRX_C_DTX_N1
SATA_SRX_C_DTX_P1

SATA_STX_DRX_P2
SATA_STX_DRX_N2

SATA_SRX_DTX_N2
SATA_SRX_DTX_P2

SATA_STX_DRX_P3
SATA_STX_DRX_N3

SATA_SRX_DTX_N3
SATA_SRX_DTX_P3

+3VS

L30

C293

1U_0402_6.3V4Z

L31

1 2

1U_0402_6.3V4Z

SATA_X1

12

R169

10M_0402_5%

SATA_X2

HP 5/ 29

HP 5/ 29

R171 1K_0402_1%

R172 10K_ 0402_5%

1 2

SATA_LED#<31,32>

+PLLVDD_SATA

2

1

1U_0402_6.3V4Z

C295

10U_0603_6.3V6M

2

2

C294

C677

1

1

chang e to 0603 f or la yout place ment

+XTLVDD_SATA

2

1

SATA_STX_DRX_P0
SATA_STX_DRX_N0

SATA_STX_DRX_P1
SATA_STX_DRX_N1

SATA_CAL

12

SATA_X1

SATA_X2

U10B

AD9

SATA_TX0P

AE9

SATA_TX0N

AB10

SATA_RX0N

AC10

SATA_RX0P

AE10

SATA_TX1P

AD10

SATA_TX1N

AD11

SATA_RX1N

AE11

SATA_RX1P

AB12

SATA_TX2P

AC12

SATA_TX2N

AE12

SATA_RX2N

AD12

SATA_RX2P

AD13

SATA_TX3P

AE13

SATA_TX3N

AB14

SATA_RX3N

AC14

SATA_RX3P

AE14

SATA_TX4P

AD14

SATA_TX4N

AD15

SATA_RX4N

AE15

SATA_RX4P

AB16

SATA_TX5P

AC16

SATA_TX5N

AE16

SATA_RX5N

AD16

SATA_RX5P

V12

SATA_CAL

Y12

SATA_X1

AA12

SATA_X2

W11

SATA_ACT#/GPIO67

AA11

PLLVDD_SATA

W12

XTLVDD_SATA

218S7EALA11FG_BGA528_SB700

SB710

Part 2 of 5

SAT A P WR SER IAL ATA

HW M ONITO R

IDE_IORDY

IDE_IRQ

IDE_A0
IDE_A1
IDE_A2

IDE_DACK#

IDE_DRQ

IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23
IDE_D9/GPIO24

AT A 66 /10 0/133

IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

SPI_DI/GPIO12

SPI_DO/GPIO11

SPI_CLK/GPIO47

SPI_HOLD#/GPIO31

SPI_CS1#/GPIO32

LAN_RST#/GPIO13

ROM_RST#/GPIO14

SP I ROM

FANOUT0/GPIO3
FANOUT1/GPIO48
FANOUT2/GPIO49

FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52

TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63

TEMPIN3/TALERT#/GPIO64

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

AVDD

AVSS

AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24

AD24
AD23

rem ov e U WB , 1 0/21 HP

AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23

G6
D2
D1
F4
F3

U15
J1

M8
M5

R170 150K_0402_5%

M7

P5
P8

GPIO52

R8

C6
B6
A6
A5
B5

R178 10K_0402_5%

GPIO53

A4
B4
C4
D4
D5
D6
A7
B7

F6

G7

0.1U_0402_16V4Z

+SB_AVDD

C296

CPPE_NC#
CRD_R EQ#_R

1

2

KBC_SPI_SO <33>
KBC_S PI_SI <33>
KBC_S PI_CLK <33>

KBC_SPI_CS0# <33>

NPCI_RS T# <33,34>
HDD_H ALTLED <31>

WXMIT_OFF# <27>

1 2

CAME RA_OFF <17>

R177 150_0402_1%

1 2

12

HP 4/ 9

+3VALW

1

C297

2.2U_0 603_6.3V4Z

2

CPPE_NC# <15,21,31>
CRD_R EQ#_R <21>

ADP_PRES <25,31 ,33,36,39,46>

HP 2/ 5

2N7002_SOT23-3

HP, 6 /10

HP, 6 /10

+3VS

R175
100K_0402_5%

R573 0_0402_5%@

1 2

1 2

13

D

Q112

2

G

S

GPIO53 GPIO52

12

@

R549
10K_0402_5%

12

@

10K_0402_5%

R551

HP 5/ 29

+3VS

DOCK _ID <18,32>

HP, 6 /10

12

R550

@

10K_0402_5%

12

@

R176
10K_0402_5%

<>

VRA M ID, C ompa l 2/ 17

VRA M I D G PIO 52 GP IO 53

Hyn ix 64M B 0

4 4

Sam su ng 1 28MB

Hyn ix 128 MB

Sam su ng 1 28MB (2n d sour ce)

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

(ma in sou rce)

(2n d sour ce)

(2n d sour ce)

0

1

1 1

Compal Electronics, Inc.

SB710 SATA/IDE/SPI

LA-4961P

20 54Thursday, August 27, 2009

E

0

1

0

1.0

A

chang e +3V ALW to +3VL Comp al 2/3

6.81K_0402_5%

R179

C298

4.7U_0603_6.3V6M

HDA_SDOUT_ MDC<28>
HDA_S DOUT_CODEC<31>

WOL_EN<25>
HDA_S YNC_MDC<28>
HDA _SYNC_COD EC<31>

HDA_R ST#_CODEC<31>
HDA_RST#_MDC<28>

HDARST#<22>

HDA_B IT_CLK_CODEC

HDA_B ITCLK_MDC

HDA_S DOUT_MDC

HDA_S DOUT_CODEC

+3VL

12

2

GATEA20<33>

KB_RST#<33>

2N7002_SOT23-3

LID_SW#<17,28,33>

R192 33_0402_5%
R193 33_0402_5%

+3VALW

5

U11

3

HP, 7 /3

STRAP PIN

HP 4/ 7

1 1

HDA_B IT_CLK_CODEC<31>
HDA_B ITCLK_MDC<28>

1 2

1 2

1 2

1 2

1 2

HDA_S DIN0<31>
HDA_S DIN1<28>

ON/OFF BTN#<25,28,32>

+3VS

1 2

R181 4.7K_0402_5%

+3VS

R182 2.2K_0402_5%

1 2

R183 2.2K_0402_5%

1 2

R184 10K_0402_5%

+3VALW

R187 2.2K_0402_5%

R189 2.2K_0402_5%

2 2

R190 100K_0402_5%
R454 10K_0402_5%
R455 10K_0402_5%
R563 10K_0402_5%

3 3

1 2

1 2

1 2

12

12
12
12

SUS_STAT#

SMB_CK_CLK0

SMB_CK_DAT0

SATA_ISO#

10/ 21 HP

SMB_CK_CLK1

SMB_CK_DAT1

XMIT_OFF#
HDA_S DIN0
HDA_S DIN1
SLP_S5#

HP, 4 /13

C299 82P_0402_50V8J

C300 82P_0402_50V8J

C301 82P_0402_50V8J

C302 82P_0402_50V8J

B

P

O4I

1

NC

G

SN74L VC1G17DBVR SOT23-5

CH751H-40PT_S OD323-2

D12

13

D

Q29

2

G

S

+3VS

+3VS

2

G

Q110

1 3

D

2N7002_SOT23-3

+3VALW

THERM_SC#<6>

1 2

1 2

R194 33_0402_5%
R195 33_0402_5%

R196 33_0402_5%
R197 33_0402_5%

R198 33_0402_5%
R199 33_0402_5%

Q104

CRD_R EQ#<15,31>

HP 2/ 6

LAN_PCIE_W AKE#<25,27,31>

SLP_S3#<31,33,36,39>
SLP_S5#<36,42>

SB_PW RGD<6,33,45>
SUS_STAT#<11>

21

LANLINK_STATUS#<25,26,32>

RUNS CI_EC#<33>

PREP#<32>

H_THERMTRIP#<6>

NB_PW RGD<11>

PM_RSMRST#<33,42>

R185 10K_0402_5%

S

HDAB ITCLK

1 2
1 2

1 2
1 2

1 2
1 2

D

S

12

LP_EN#<15,25>

R188 10K_0402_5%

HDA_SPKR<31>
SMB_CK_CLK0<4,6,8, 9,15,30>
SMB_CK_DAT0<4,6,8,9,15 ,30>

XMIT_OFF#<27>

WLAN _OFF<27>

BT_OFF<30>

LOM_PWR#<26>

R191 10K_0402_5%

CPPE_NC#<15,20,31>

HDA_SDOUT

HDA_S DIN0
HDA_S DIN1

WOL_EN

CRD_R EQ#_R

13

+3VS

2

G

2N7002_SOT23-3

SUS_STAT#

H_THERMTRIP#
NB_PW RGD

PM_RSMRST#

SATA_ISO#

12

SMB_CK_CLK0
SMB_CK_DAT0
SMB_CK_CLK1
SMB_CK_DAT1

12

CRD_R EQ#_R

HDA _SYNC

HDARST#

CRD_R EQ#_R <20>

C

U10D

E1

PCI_PME#/GEVENT4#

E2

RI#/EXTEVNT0#

H7

SLP_S2/GPM9#

F5

SLP_S3#

G1

SLP_S5#

H2

PWR_BTN#

H1

PWR_GOOD

K3

SUS_STAT#

H5

TEST2

H4

TEST1

H3

TEST0

Y15

GA20IN/GEVENT0#

W15

KBRST#/GEVENT1#

K4

LPC_PME#/GEVENT3#

K24

LPC_SMI#/EXTEVNT1#

F1

S3_STATE/GEVENT5#

J2

SYS_RESET#/GPM7#

H6

WAKE#/GEVENT8#

F2

BLINK/GPM6#

J6

SMBALERT#/THRMTRIP#/GEVEN T2#

W14

NB_PWRGD

D3

RSMRST#

AE18

SATA_IS0#/GPIO10

AD18

CLK_REQ3#/SATA_IS1#/GPIO6

AA19

SMARTVOLT1/SATA_IS2#/GPIO4

W17

CLK_REQ0#/SATA_IS3#/GPIO0

V17

CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39

W20

CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40

W21

SPKR/GPIO2

AA18

SCL0/GPOC0#

W18

SDA0/GPOC1#

K1

SCL1/GPOC2#

K2

SDA1/GPOC3#

AA20

DDC1_SCL/GPIO9

Y18

DDC1_SDA/GPIO8

C1

LLB#/GPIO66

Y19

SMARTVOLT2/SHUTDOWN #/GPIO5

G5

DDR3_RST#/GEVENT7#

B9

USB_OC6#/IR_TX1/GEVENT6#

B8

USB_OC5#/IR_TX0/GPM5#

A8

USB_OC4#/IR_RX0/GPM4#

A9

USB_OC3#/IR_RX1/GPM3#

E5

USB_OC2#/GPM2#

F8

USB_OC1#/GPM1#

E4

USB_OC0#/GPM0#

M1

AZ_BITCLK

M2

AZ_SDOUT

J7

AZ_SDIN0/GPIO42

J8

AZ_SDIN1/GPIO43

L8

AZ_SDIN2/GPIO44

M3

AZ_SDIN3/GPIO46

L6

AZ_SYNC

M4

AZ_RST#

L5

AZ_DOCK_RST#/GPM8#

H19

IMC_GPIO0

H20

IMC_GPIO1

H21

SPI_CS2#/IMC_GPIO2

F25

IDE_RST#/F_RST#/IMC_GPO3

D22

IMC_GPIO4

E24

IMC_GPIO5

E25

IMC_GPIO6

D23

IMC_GPIO7

218S7EALA11FG_BGA528_SB700

D

SB710

AC PI / W AKE UP EV ENT S

US B O C

HD AUD IO

Part 4 of 5

USBCLK/14M_25M_48M_OSC

IN TE GR ATED u C

USB_RCOMP

USB_FSD13P
USB_FSD13N

US B MI SC

USB_FSD12P
USB_FSD12N

USB_HSD11P

US B 1. 1

USB_HSD11N

USB_HSD10P
USB_HSD10N

USB_HSD9P
USB_HSD9N

USB_HSD8P
USB_HSD8N

USB_HSD7P
USB_HSD7N

USB_HSD6P
USB_HSD6N

USB_HSD5P
USB_HSD5N

USB_HSD4P

US B 2. 0

USB_HSD4N

USB_HSD3P
USB_HSD3N

GP IO

USB_HSD2P
USB_HSD2N

USB_HSD1P
USB_HSD1N

USB_HSD0P
USB_HSD0N

IMC_GPIO8
IMC_GPIO9

IMC_PWM0/IMC_GPIO10

SCL2/IMC_GPIO11
SDA2/IMC_GPIO12

SCL3_LV/IMC_GPIO13

SDA3_LV/IMC_GPIO14

IMC_PWM1/IMC_GPIO15

IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17

IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25

IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41

C8

USB_RCOMP

G8

USB20_P13

E6

USB20_N13

E7

F7
E8

USB20_P11

H11

USB20_N11

J10

E11

delet e USB 20_P10 /N10 for r emove NIC8 075. HP 12/5

F11

A11
B11

USB20_P8

C10

USB20_N8

D10

USB20_P7

G11

USB20_N7

H12

USB20_P6

E12

USB20_N6

E14

USB20_P5

C12

USB20_N5

D12

USB20_P4

B12

USB20_N4

A12

USB20_P3

G12

USB20_N3

G14

USB20_P2

H14

USB20_N2

H15

USB20_P1

A13

USB20_N1

B13

USB20_P0

B14

USB20_N0

A14

A18
B18
F21
D21
F19
E20
E21
E19
D19
E18

G20
G21
D25
D24
C25
C24
B25
C23

B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18

1 2

R18011.8K_0402_1%

USB20_P13 <29>
USB20_N13 <29>

USB20_P11 <30>
USB20_N11 <30>

USB20_P8 <32>
USB20_N8 <32>

USB20_P7 <27>
USB20_N7 <27>

USB20_P6 <32>
USB20_N6 <32>

USB20_P5 <30>
USB20_N5 <30>

USB20_P4 <17>
USB20_N4 <17>

USB20_P3 <30>
USB20_N3 <30>

USB20_P2 <31>
USB20_N2 <31>

USB20_P1 <31>
USB20_N1 <31>

USB20_P0 <30>
USB20_N0 <30>

GPIO16 <22>
GPIO17 <22>

CLK_48M_USB <15>

USB-13 FPR

USB-11 Bluetooth

USB-8 Dock

USB-7 MiniCard(WWAN)

USB-6 Dock

USB-5 left side

USB-4 U SB Camera

USB-3 left side

USB-2 d aughter board

USB-1 Express card

USB-0 L eft side (S/W Debug Port)

STRAP PIN
STRAP PIN

E

IN TE GR ATED u C

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

SB710 USB/AC97

LA-4961P

21 54Thursday, August 27, 2009

E

1.0

A

B

C

D

E

REQUIRED STRAPS

PCI_CLK3

PULL

1 1

2 2

HIGH

PULL
LOW

PCI_C LK2<19>

CLK_P CI_KBC<19,33>

CLK_P CI_DB<19,29>

PCI_CLK5<19>

CLK_P CI_EC<19>

LPCCLK1<19>
RTC_CLK<19>

HDARST#<21>

GPIO17<21>
GPIO16<21>

BOOTFAIL
TIMER
ENABLED

BOOTFAIL
TIMER
DISABLED

DEF AULT

+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW

R200

2.2K_0402_5%

R210

@

2.2K_0402_5%

USE
DEBUG
STR APS

IGNORE
DEBUG
STR APS

DEF AULT

12

R201

@

12

R211

12

10K_0402_5%

12

2.2K_0402_5%

PCI_CLK4 PCI_CLK5

RESERVED

R202

@

R212

@

RESERVED

12

10K_0402_5%

12

10K_0402_5%

NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

AZ_RST_CD#

ENABLE PCI
MEM BOOT

DISABLE PCI
MEM BOOT

DEF AULT

12

R203

10K_0402_5%

@

R213

10K_0402_5%

@

R204

@

12

R214

CLKGEN
ENABLED

CLKGEN
DISABLED

DEF AULT

12

10K_0402_5%

2.2K_0402_5%

R205

10K_0402_5%

@

12

R215

2.2K_0402_5%

RTC_CLKLPC_CLK1

INTERNA L
RT C

DEF AULT

EXT . RTC

(PD on X1,
apply
32KHz to
RTC_CLK)

12

R206

@

12

R216

@

LPC_CLK0

EC

ENABLED

GP17

GP16PCI_CLK2

In tern al pull up

H,H = Reserved

H,L = SPI ROM

EC

DISABLED

DEF AULT

12

R207

10K_0402_5%

12

2.2K_0402_5%

10K_0402_5%

@

R217

2.2K_0402_5%

12

12

L,H = LPC ROM (Default)

L,L = FWH ROM

12

12

R208

2.2K_0402_5%

R218

@

2.2K_0402_5%

@

2.2K_0402_5%

12

12

R219

2.2K_0402_5%

R209

DEBUG STRAPS

SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

12

2.2K_0402_5%

PCI_AD27 PCI_AD26

USE PCI
PL L

DEF AULT

BYP ASS
PC I PLL

R221

@

USE ACPI
BCLK

DEF AULT

BYP ASS
AC PI
BCLK

12

R222

2.2K_0402_5%

@

PCI_AD28

3 3

PCI_AD28<19>
PCI_AD27<19>
PCI_AD26<19>
PCI_AD25<19>
PCI_AD24<19>
PCI_AD23<19>

4 4

PULL
HIGH

PULL
LOW

USE
LONG
RESET

DEF AULT

USE
SHORT
RESET

R220

@

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

2.2K_0402_5%

C

PCI_AD25 PCI_AD24

USE IDE
PL L

DEF AULT

BYPASS IDE
PL L

R223

@

USE DEFAULT
PCI E ST RAPS

DEF AULT

USE EEPROM
PCI E ST RAPS

12

R224

2.2K_0402_5%

@

2007/08/02 2008/08/02

PCI_AD23

RESERVED

12

R225

2.2K_0402_5%

@

Compal Secret Data

Deciphered Date

12

2.2K_0402_5%

D

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

SB710 STRAPS

LA-4961P

22 54Thursday, August 27, 2009

E

1.0

A

B

C

D

E

0.6 A/ 50mi l/4v ias

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

V5_VREF

AVDDC

L

L15
M12
M14
N13
P12
P14
R11
R15
T16

0.3 A/ 30mi l/2v ias

L

L21
L22
L24
L25

0.1 A/ 30m il/ 2via s ?

L

A17
A24
B17
J4
J5
L1
L2

G2
G4

A10
B10

+V5_VREF

AE7

+AVDD CK_3.3V

J16

+AVDD CK_1.2V

K17

+AVDDC

E9

+1.2V_SB_CORE

1 2

+

12
12
12
12
12
12

10/ 07 HP

10/ 07 HP

+1.2V_CKVD D

C322 1U_0402_6.3V4 Z@

1 2

C327 10U_0805_10V4Z@

1 2

remov e C32 0, C32 4, C3 26 fo r lay out 1 0/22 HP

10/ 07 HP

+S5_3V

+S5_1.2V

+1.2_USB

0.1U_0402_16V4Z

1 2

C33222U_0805_6.3V6M

C3351U_0 402_6.3V4Z

12

C3371U_0 402_6.3V4Z

12

C3381U_0 402_6.3V4Z

12

C3390.1 U_0402_16V4Z

12

C3400.1 U_0402_16V4Z

12

C3410.1 U_0402_16V4Z

12

1 2

C353

+1.2VALW

+

12
12

2

2

1U_0603_10V4Z

1

1

1 2

C34922U_A_4VM
C3500.1U_04 02_16V4Z
C3511U_0 402_6.3V4Z

C354

L38

10/ 07 HP

FBMA-L11-201209-221LMA30T_0805

C30422U_A_4V M
C3061U_0402_6.3V4Z
C3081U_0402_6.3V4Z
C3101U_0402_6.3V4Z
C3121U_0402_6.3V4Z
C3140.1U_0402_16V4Z
C3160.1U_0402_16V4Z

+3VALW

12

12

+1.2V_HT

+3VALW

C3612.2U_ 0603_6.3V4Z

C3620.1U_0402_16V4Z

+1.2V_HT

10/ 07 HP

R2301K_0402_5%

12

D13

21

CH751H-40PT_S OD323-2

+5VS

+3VS

+1.2VALW

C3441U_0402_6.3V4Z

12

C3460. 1U_0402_16V4Z

12

0.4 5A /40 mil /3vias ?

+3VS

1 1

L

+1.2V_HT

2 2

+1.2V_HT

L

+3VALW

L

<1. 25 A/5 0mil/4v ias?

3 3

C303 22U_0805_6.3V6M
C305 1U_0402_6.3V4Z

1 2

C307 1U_0402_6.3V4Z

1 2

C309 1U_0402_6.3V4Z

1 2

C311 1U_0402_6.3V4Z

1 2

C313 1U_0402_6.3V4Z

1 2

C315 1U_0402_6.3V4Z

1 2

C317 0.1U_0402_16V4Z

1 2

C318 0.1U_0402_16V4Z

1 2

C323 1U_0 402_6.3V4Z@

1 2

remov e C31 9, C32 1, C3 25 fo r lay out 1 0/22 HP

0.8 A/ 50mi l/4v ias

1 2

FBMA-L11-201209-221LMA30T_0805

C678 10U_0805_10V6K

C328 4.7U_0805_10V4Z
C329 1U_0402_6.3V4 Z
C330 1U_0402_6.3V4 Z
C331 1U_0402_6.3V4 Z
C333 1U_0402_6.3V4 Z
C334 0.1U_0402_16V4Z
C336 0.1U_0402_16V4Z

1 2

FBMA-L11-201209-221LMA30T_0805

<1. 25 A/5 0mil/4vias

C342 22U_0805_6.3V6M
C343 1U_0805_16V7K
C345 1U_0805_16V7K
C347 0.1U_0402_16V4Z
C348 0.1U_0402_16V4Z

1 2

FBMA-L11-201209-221LMA30T_0805

C352 10U_0805_10V4Z
C355 10U_0805_10V4Z
C356 1U_0402_6.3V4Z
C357 1U_0402_6.3V4Z
C358 0.1U_0402_16V4Z
C359 0.1U_0402_16V4Z
C360 0.1U_0402_16V4Z

12

L33

1 2
1 2
1 2
1 2
1 2
1 2

L34

1 2
1 2
1 2
1 2

L37

1 2
1 2
1 2
1 2
1 2
1 2
1 2

L

R5390_0402_5%

12

HP 2/ 5

+3VS

+PCIE _VDDR

12

12

12

+1.2V_SATA

+AVDD_USB

U10C

L9

VDDQ_1

M9

VDDQ_2

T15

VDDQ_3

U9

VDDQ_4

U16

VDDQ_5

U17

VDDQ_6

V8

VDDQ_7

W7

VDDQ_8

Y6

VDDQ_9

AA4

VDDQ_10

AB5

VDDQ_11

AB21

VDDQ_12

Y20

VDD33_18_1

AA21

VDD33_18_2

AA22

VDD33_18_3

AE25

VDD33_18_4

P18

PCIE_VDDR_1

P19

PCIE_VDDR_2

P20

PCIE_VDDR_3

P21

PCIE_VDDR_4

R22

PCIE_VDDR_5

R24

PCIE_VDDR_6

R25

PCIE_VDDR_7

AA14

AVDD_SATA_1

AB18

AVDD_SATA_4

AA15

AVDD_SATA_2

AA17

AVDD_SATA_3

AC18

AVDD_SATA_5

AD17

AVDD_SATA_6

AE17

AVDD_SATA_7

A16

AVDDTX_0

B16

AVDDTX_1

C16

AVDDTX_2

D16

AVDDTX_3

D17

AVDDTX_4

E17

AVDDTX_5

F15

AVDDRX_0

F17

AVDDRX_1

F18

AVDDRX_2

G15

AVDDRX_3

G17

AVDDRX_4

G18

AVDDRX_5

218S7EALA11FG_BGA528_SB700

SB710

Part 3 of 5

PCI/ GPIO I/ O

ID E/ FLS H I/O

POWER

A-L INK I/O

3.3 V_S5 I /OCO RE S5

SATA I/O

USB_PHY_1.2V_1
USB_PHY_1.2V_2

PL L CL KG EN I /O

US B I/O

CO RE S0

CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7

S5_1.2V_1
S5_1.2V_2

AVDDCK_3.3V

AVDDCK_1.2V

U10E

SB710

T10

AVSS_SATA_1

U10

AVSS_SATA_2

U11

AVSS_SATA_3

U12

AVSS_SATA_4

V11

AVSS_SATA_5

V14

AVSS_SATA_6

W9

AVSS_SATA_7

Y9

AVSS_SATA_8

Y11

AVSS_SATA_9

Y14

AVSS_SATA_10

Y17

AVSS_SATA_11

AA9

AVSS_SATA_12

AB9

AVSS_SATA_13

AB11

AVSS_SATA_14

AB13

AVSS_SATA_15

AB15

AVSS_SATA_16

AB17

AVSS_SATA_17

AC8

AVSS_SATA_18

AD8

AVSS_SATA_19

AE8

AVSS_SATA_20

A15

AVSS_USB_1

B15

AVSS_USB_2

C14

AVSS_USB_3

D8

AVSS_USB_4

D9

AVSS_USB_5

D11

AVSS_USB_6

D13

AVSS_USB_7

D14

AVSS_USB_8

D15

AVSS_USB_9

E15

AVSS_USB_10

F12

AVSS_USB_11

F14

AVSS_USB_12

G9

AVSS_USB_13

H9

AVSS_USB_14

H17

AVSS_USB_15

J9

AVSS_USB_16

J11

AVSS_USB_17

J12

AVSS_USB_18

J14

AVSS_USB_19

J15

AVSS_USB_20

K10

AVSS_USB_21

K12

AVSS_USB_22

K14

AVSS_USB_23

K15

AVSS_USB_24

H18

PCIE_CK_VSS_1

J17

PCIE_CK_VSS_2

J22

PCIE_CK_VSS_3

K25

PCIE_CK_VSS_4

M16

PCIE_CK_VSS_5

M17

PCIE_CK_VSS_6

M21

PCIE_CK_VSS_7

P16

PCIE_CK_VSS_8

F9

AVSSC

Part 5 of 5

218S7EALA11FG_BGA528_SB700

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43

GROUND

VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50

PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21

AVSSCK

A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24

P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25

L17

L39

1 2

L40

1 2

+1.2V_HT

C3632.2U_0 603_6.3V4Z

12

C3640.1U_0402_16V4Z

12

+3VS

C3652.2U_0 603_6.3V4Z

12

C3660.1 U_0402_16V4Z

12

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

SB710 PWR/GND

LA-4961P

23 54Thursday, August 27, 2009

E

1.0

+AVDD CK_1.2V

+AVDD CK_3.3V

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

2007/08/02 2008/08/02

C

A

B

C

D

E

HDD Connector

+5VS

1

1 1

C367

10U_0805_10V4Z

1

2

0.1U_0402_16V4Z

C368

2

1

C369

2

0.1U_0402_16V4Z

1

C370

2

0.1U_0402_16V4Z

SUYIN_1 27043FR022G528_2 2P_NR-T

CONN@

JHD D1

GND

GND

GND

GND
GND
GND

GND

Reserved

GND

1
2

A+

3

A-

4

B-

B+

V33
V33
V33

V5
V5
V5

V12
V12
V12

6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

SATA_SRX_DTX_P0

Near CONN side.

+5VS

SATA_SRX_DTX_N0

5

C371 0.01U_04 02_16V7K

12

C372 0.01U_04 02_16V7K

12

SATA_STX_C_DRX_P0
SATA_STX_C_DRX_N0

SATA_SRX_C_DTX_N0
SATA_SRX_C_DTX_P0

SATA_STX_C_DRX_P0 <20>
SATA_STX_C_DRX_N0 <20>

SATA_SRX_C_DTX_N0 <20>
SATA_SRX_C_DTX_P0 <20>

CD-ROM Connector

CONN@

2 2

+5VS

Pl acea cap s. near O DD C ONN .

1U_0603_10V4Z

0.1U_0402_16V4Z

C379

1

C380

2

10U_0805_10V4Z

1

2

1

1

C381

2

C382
10U_0805_10V4Z

2

JODD 1

GND

A+

A-

GND

B-

B+

GND

DP

V5
V5

MD
GND
GND

SANTA_202001-1_13P-T

1
2
3
4
5
6

7
8
9
10
11
12
13

SATA_SRX_DTX_P1

R232

1 2

0_0402_5%

+5VS

C377 0.01U_04 02_16V7K

12

C378 0.01U_04 02_16V7K

12

Near CONN side.

SATA_STX_C_DRX_P1
SATA_STX_C_DRX_N1

SATA_SRX_C_DTX_N1SATA_SRX_DTX_N1
SATA_SRX_C_DTX_P1

SATA_STX_C_DRX_P1 <20>
SATA_STX_C_DRX_N1 <20>

SATA_SRX_C_DTX_N1 <20>
SATA_SRX_C_DTX_P1 <20>

3 3

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

HDD/CDROM

LA-4961P

24 54Thursday, August 27, 2009

E

1.0

5

5/9 H P

R233 100K_0402_5%

ADP_PRES< 20,31,33,36,39,46>

WOL_EN<21>

D D

ON/OFF BTN#<21,28,32>

SLP_S5<30,31,32,36>

DMN66D0LDW-7_SOT363-6

Q2B

3

5

4

LAN_PCIE_W AKE#

1 2

DMN66D0LDW-7_SOT363-6

13

D

Q31

2

G

SSM3K7002FU_SC70-3

S

LP_EN#<15,21>

LAN_PCIE_W AKE# <21,27,31>

DMN66D0LDW-7_SOT363-6

wor ka rou nd a ou t- of- bo x S 4 W OL i ssue wit h SB 7001 0/08 HP

PCIE_PRX_DTX_P0<10>

DMN66D0LDW-7_SOT363-6

LAN_PCIE_W AKE#

+3V_LAN

C C

for D C mod e can' t boo t iss ue1/1 5 HP

B B

25MHZ_20P_1BG25000CK1A

A A

1
2
3
4

CAT24 C08WI-GT3 SO 8P

6 1

0.1U_0402_16V4Z

U13

A0
A1
NC
GND

Q2A

2

DMN66D0LDW-7_SOT363-6

C40727P_0402_50V8J

12

Y4

C40927P_0402_50V8J

12

C411

12

8

VCC

7

WP

6

SCL

5

SDA

5

PCIE_PTX_C_DRX_P0<10>
PCIE_PTX_C_DRX_N0<10>

+3VS

LP_EN#

1 2

4.7K_0402_5%

LAN_EE_CLK
LAN_EE_DATA

PCIE_PRX_DTX_N0<10>

CLK_P CIE_LAN#<15>

Q19A

CLK_P CIE_LAN<15>

R250

2

PLT_RST#<11,19 ,27,29,31,34>

LAN_MDI0P<26>
LAN_M DI0N<26>
LAN_MDI1P<26>
LAN_M DI1N<26>
LAN_MDI2P<26>
LAN_M DI2N<26>
LAN_MDI3P<26>
LAN_M DI3N<26>

+3V_LAN

12

12

R249
100K_0402_5%

61

LAN_X1
LAN_X2

+3V_LAN

HP 5/ 29

12

R251

4.7K_0402_5%

1 2

R236 10K_0402_5%

LAN_DIS#

+3V_LAN
+3VS

4

2

Q1A

6 1

HP 3/ 25

LP_EN

5/9 HP

Q34A

PCIE_RXP0_LAN

C4000.1U_0402_16V4Z

12

PCIE_RXN0_LA N

C4010.1U_0402_16V4Z

12

PLT_RST#_R

LAN_EE_CLK
LAN_EE_DATA

remov e 807 5@ por tion

LAN_X1
LAN_X2

remov e 807 5@, HP 12/5

1 2

R239 10K_0402_5%

CTRL18
CTRL12

1 2

4.99K_0402_1%

R246

4

+3VALW

+5VALW

SI2301BDS_SOT23

R234
10K_0402_5%

R235

1 2

47K_0402_5%

61

2

remov e 807 5@, HP 12/5

0.022U_0402_16V7K

U12

42

CLKREQn

49

TX_P

50

TX_N

54

RX_P

53

RX_N

6

WAKEn

55

REFCLKP

56

REFCLKN

5

PERSTn

17

MDIP0

18

MDIN0

20

MDIP1

21

MDIN1

26

MDIP2

27

MDIN2

30

MDIP3

31

MDIN3

38

VPD_CLK

41

VPD_DATA

34

SPI_DO

35

SPI_DI

37

SPI_CLK

36

SPI_CS

15

XTALI

14

XTALO

10

LOM_DISABLEn(USB_DM-)

9

SWITCH_VAUX(USB_D P+)

11

SWITCH_VCC(LOM_DISABL En)

12

VAUX_AVLBL

47

VMAIN_AVLBL

4

CTRL18

3

CTRL12

16

RSET

S

Q30

G

2

12

R554

15K_0402_5%

HP, 4 /13

EEPROM

MEMORY

CLOCK

12

PCI-E

Media

FLASH

Analog

D

13

Q34B

1

C712

2

+3V_LAN

PLT_RST#_R

3

5

4

3

DMN66D0LDW-7_SOT363-6

+3V_LAN

0.1U_0402_16V4Z

1

C383

2

0.1U_0402_16V4Z

1

C384

2

0.1U_0402_16V4Z

1

C385

2

0.1U_0402_16V4Z

1

C386

2

1

C387

0.1U_0402_16V4Z

2

2

pow er -do wn NI C in ste ad of low- powe r mo de H P, 3 /23

+3V_LAN

LED_ACTn

TESTMODE

AVDDH

AVDD

AVDD

VDDO_TTL
VDDO_TTL
VDDO_TTL
VDDO_TTL

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

EAPD

SMALERTn

SMCLK

Reserved
Reserved
Reserved
SMDATA

59
60
62
63

46

R545 0_0402_5%

1 2

8

19
22

NC

23

NC

28

R546 0_0402_5%

1 2

1
40
45
61

R547 0_0402_5%

1 2

2
7
13
33
39
44
48
58
65

R548 0_0402_5%

1 2

51

NC

52

NC

remov e 807 5@, HP 12/5

32
57

R242 10K_0402_5%

64

24
25
29
43

remov e 807 5@, HP 12/5

LED

LED_LINK10/100n

LED_LINK1000n

LED_DUPLEXn

TEST

POWER

&

GROUND

(PD18LDO)NC

No Connect

88E80 72 & 88E8075_QFN64

R544 0_0402_5%

1 2

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

HP 2/ 14

LAN_ACT#

HP 2/ 14

V1.8_LAN

HP 2/ 14

HP 2/ 14

12

2008/09/15 2009/09/15

LAN_ACT# <26,32>

+3V_LAN

+3V_LAN

V1.2_LAN

HP 2/ 14

+3V_LAN

10/08 HP

Compal Secret Data

Deciphered Date

G

2

13

D

S

2N7002_SOT23-3

Q107

0.1U_0603_25V7K

2

0.1U_0402_16V4Z

LANLINK_STATUS# <21,26,32>

1

C685

@

2

1

C389

2

V1.2_LAN

2SB1188T100R_SC62-3

V1.8_LAN

V1.2_LAN

0.1U_0402_16V4Z

1

C396

2

0.1U_0402_16V4Z

V1.2_LAN

0.1U_0402_16V4Z

1

C402

2

0.1U_0402_16V4Z

V1.8_LAN

1

2

0.1U_0402_16V4Z

C388

+1.2VALW to V1.2_LAN

V1.2_LAN+1.2VALW

1

Q79

8

D

7

D

6

D

5

D

SI4800 BDY_SO8

1

C570

4.7U_0805_10V4Z

2

C571

1

S

2

S
S
G

Title

Size Doc ument Number Re v

Date: Sheet of

2

3
4

1U_0402_6.3V4Z

3

4

for c an't power on in AC m ode 5 /9 HP

Compal Electronics, Inc.

Giga LAN 88E8072

1

1

C397

C398

2

2

0.1U_0402_16V4Z

1

1

C404

C403

2

2

0.1U_0402_16V4Z

+3V_LAN

C4064.7U_0805_1 0V4Z

R237 4.7K_0402_5%@

12

Q32

@

C40810U_0805_10V4Z

12

C41210U_0805_10V4Z

12

1

2SB1188T100R_SC62-3

2 3

+3V_LAN

C4104.7U_0805_1 0V4Z

R245 4.7K_0402_5%

12

Q33

1

2 3

remov e 807 5@, HP 12/5

4.7U_0805_10V4Z

1

C568

@

2

1 2

R499 750K _0402_5%

LP_EN

5

DMN66D0LDW-7_SOT363-6
Q19B

1

5/9 HP

12

12

1

2

1

1

2

1

2

@

C399

0.1U_0402_16V4Z

C405

0.1U_0402_16V4Z

CTRL12

CTRL18

C569

0.1U_0603_25V7K

B+

25 54Thurs day, August 27 , 2009

1.0

5

D D

4

3

2

1

V_3 P3_LA N_LED

R4 69

10K _0402_5%

12

C C

LAN _MDI0P<25>
LA N_MD I0N<25>

LAN _MDI1P<25>
LA N_MD I1N<25>

LAN _MDI2P<25>
LA N_MD I2N<25>

LAN _MDI3P<25>
LA N_MD I3N<25>

V1. 8_LAN

1 2

B B

A A

1 2

C4 30

0.1U _0402 _16V7K

1 2

C4 33

0.1U _0402 _16V7K

1 2

C4 35

0.1U _0402 _16V7K

1 2

C4 37

0.1U _0402 _16V7K

R2 56
0_08 05_5%

TRM_ CT

TRM_ CT

TRM_ CT

TRM_ CT

LAN _MDI0 P
LA N_MD I0N

LAN _MDI1 P
LA N_MD I1N

LAN _MDI2 P
LA N_MD I2N

LAN _MDI3 P
LA N_MD I3N

LA N_MD I0N

LAN _MDI0 P

LA N_MD I1N

LAN _MDI1 P

LA N_MD I2N

LAN _MDI2 P

LA N_MD I3N

LAN _MDI3 P

T3

12

TD4-

11

TD4+

10

TCT4

9

TD3-

8

TD3+

7

TCT3

6

TD2-

5

TD21+

4

TCT2

3

TD1-

2

TD1+

1

TCT1

NS8 92402 1G

Pin Sw ap. 10 /05

Swap P & N. 10/09

1:1

1:1

1:1

1:1

MX4-

MX4+

MCT4

MX3-

MX3+

MCT3

MX2-

MX2+

MCT2

MX1-

MX1+

MCT1

LAN _ACT#<25,32>

MDO 0-

13

MDO 0+

14

MCT0

15

MDO 1-

16

MDO 1+

17

MCT1

18

MDO 2-

19

MDO 2+

20

MCT2

21

MDO 3-

22

MDO 3+

23

MCT3

24

MDO 0- <32>

MDO 0+ <32>

C4 31 0.01 U_040 2_50V7K

1 2

MDO 1- <32>

MDO 1+ <32>

C4 34 0.01 U_040 2_50V7K

1 2

MDO 2- <32>

MDO 2+ <32>

C4 36 0.01 U_040 2_50V7K

1 2

MDO 3- <32>

MDO 3+ <32>

C4 38 0.01 U_040 2_50V7K

1 2

R2 57
75_0 402_1%

1 2

R2 59
75_0 402_1%

1 2

R2 60
75_0 402_1%

1 2

R2 62
75_0 402_1%

1 2

LAN LINK_ STATUS#< 21,25, 32>

C4 39 100 0P_1808 _3KV7K

1 2

LAN _ACT#

1 2

V_3 P3_LA N_LED

LAN LINK _STATUS #

1 2

@

PAC DN042 Y3R_ SOT23- 3

1

D4 7

11/ 04 ESD requ est

V_3 P3_LA N_LED

R2 53 300_ 0603_5%

1 2

C4 28680P _0402_50V 7K@

R2 55

10K _0402_5%

12

V_3 P3_LA N_LED

R2 58 3 00_06 03_5%

1 2

C4 32680P _0402_50V 7K@

LAN _ACT#

2

LAN LINK _STATUS #

3

MDO 3-

MDO 3+

MDO 1-

MDO 2-

MDO 2+

MDO 1+

MDO 0-

MDO 0+

JR J45

13

Yellow LED+

14

Yellow LED-

8

PR4-

DETECT PIN1

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

DETCET PIN2

1

PR1+

11

Green LED+

12

Green LED-

FOX _JM36 11A-P1123 -7H_14P

HP, 4/8

20 mil

SHLD1

SHLD1

+3V _LAN V_3 P3_LA N_LED

+3V ALW

R2 52
10K _0402_5%

1 2

16

9

10

connec tion the pin10 to GND. 12/31

15

20 mil

R2 61

1 2

0_04 02_5%

1 2

R2 5449 9_0402_ 1%

1 2

LOM _PWR# <21>

C4 29680P _0402_50V 7K@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/09/15

Compal Secret Data

Deciphered Date

2

Title

Size D ocum ent N umber R ev

Da te: She et of

Compal Electronics, Inc.

Magnetic & RJ45

LA -49 61P

1

26 54Thur sday , Au gust 27, 20 09

1. 0

A

1 1

Mini Card Slot3--WWAN

JP10

LAN_PCIE_W AKE#<21,25,31>

1 2

R513 0_0402 _5% @

HP re ser ve 12/0 2

T4 P AD
T5 P AD

2 2

+3V_WWAN

T6 P AD

CONN@

1

1

3

3

5

5

7

7

9

9
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152

GND153GND2

FOXCON N AS0B226-S40N-7F 52P

+3V_WWAN

2

2

4

4

6

6
8

10

UIM_PWR

8

UIM_DATA

10

UIM_CLK

12

UIM_RST

14

UIM_VPP

16
18

M_WXMIT_OFF#

20

PLT_RST#

22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

B

SIO_GPIO23 <34>

HP 3/ 31

USB20_N7 <21>
USB20_P7 <21>

WW_LED# <31>

Mini Card Slot 1---WLAN

1
3
5
7
9

CLK_P CIE_MCARD#<15>
CLK_P CIE_MCARD<15>

CLK_P CI_DEBUG<19>

PCIE_PRX_DTX_N4<10>
PCIE_PRX_DTX_P4<10>

PCIE_PTX_C_DRX_N4<10>
PCIE_PTX_C_DRX_P4<10>

PCI_RST# _R

+3V_WLAN

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

FOXCON N AS0B226-S40N-7F 52P

CONN@

JP9

C669

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

GND1

1

2

C

D

E

Rese rve for port8 0 card use for FCS i n factory side.

DEG_FRAME#
DEBU G_AD3
DEBU G_AD2
DEBU G_AD1
DEBU G_AD0

PCI_RST# _R

2

2

4

4

6

6

DEG_FRAME#

8

8

DEBU G_AD3

10

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND2

47P_0402_50V8J

0.01U_0402_16V7K

C441

1

2

DEBU G_AD2

12

DEBU G_AD1

14

DEBU G_AD0

16
18

XMIT_OFF#

20

PLT_RST#_WLAN

22
24
26
28
30
32
34
36

remov e due to AM D pla tform no s uppor t WiM AX 12/02

38
40
42

WL_LED#_R

44
46
48
50
52

54

CLK_P CIE_WLAN_REQ#<15>

0.1U_0402_16V4Z

4.7U_0805_10V4Z

C442

C443

1

1

2

2

R263 0_0402_5%
R264 0_0402_5%
R265 0_0402_5%
R266 0_0402_5%
R267 0_0402_5%

R268 0_0402_5%

XMIT_OFF# <21>

WLAN _OFF<21>

C670

47P_0402_50V8J

0.01U_0402_16V7K
C445

C444

1

1

1

2

0.1U_0402_16V4Z

2

2

1 2
1 2
1 2
1 2
1 2

1 2

+1.5VS+3V_WLAN

4.7U_0805_10V4Z

C446

1

2

+3V_WLAN

+1.5VS

WL_LED#_R

1 2

R561 0_0402_5%

LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0

HP 3/ 25

C440 0.022U_0402_25V7K

Q16A

61

DMN66D0LDW-7_SOT363-6

2

12

R276
10K_0402_5%

LPC_LFRAME# <19,29,33,34>

LPC_L AD[0..3] <19,29,33,34>
PCI_RST# <19,29>

1 2

HP 3/ 25

5

R272

100K_0402_5%

WL_LED# <31>

3

Q16B
DMN66D0LDW-7_SOT363-6

4

4

DMN66D0LDW-7_SOT363-6

PLT_RST#<11,19 ,25,29,31,34>

Q17A

PLT_RST#_WLAN

61

DMN66D0LDW-7_SOT363-6

2

1 2

5

Q17B

2 1

R277 47K_0402_5%

1 2

R278 47K_0402_5%

1 2

3

12

R269
10K_0402_5%

CH751H-40PT_S OD323-2
D14

R273

12

10K_0402_5%

HP 3/ 25

SI2305DS-T1-E3_SOT23-3

+5VS

2

Q43

+5VS

+3VS

31

+3V_WLAN

pow er do wn WW AM cir cuit . HP 5/2 9

3 3

WXMIT_OFF#<20>

HP, 6 /11

4 4

MC1_DISABLE<33>

A

+3VS

1 2

+3VS

WWAN@

R570
10K_0402_5%

1 2

R532

WWAN@

R529
10K_0402_5%

WWAN@

1 2

2N7002_SOT23-3

220K_0402_1%

R530

0_0402_5%

WWAN@

WWAN@

Q101

+3V_WWAN

R571
470_0805_5%

WWAN@

1 2

13

2

G

D

Q114
2N7002_SOT23-3

S

WWAN@

+3V_WWAN

12

B+

WWAN@

R531
330K_0402_5%

1 2

13

D

2

G

S

MC1_DISABLE

+3VS

WWAN@

Q100
SI7326DN-T1-GE3_PAK1212-8

3 5

241

B

WWAN@

C671

1

2

+3V_WWAN

C453

C451

47P_0402_50V8J

1

2

WWAN@

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

39P_0402_50V8J@

39P_0402_50V8J@

C452

39P_0402_50V8J@

1

1

2

2

UIM_VPP
UIM_DATAM_WXMIT_OFF#

+3V_WWAN

0.1U_0402_16V4Z

0.01U_0402_16V7K

C447

1

2

WWAN@

4.7U_0805_10V4Z

C448

C449

1

1

2

2

WWAN@

R288

47K_0402_5%

@

2008/03/13 2009/05/11

C

JP12

4
5
6
7

12

UIM_PWR

Compal Secret Data

Deciphered Date

GND
VPP
I/O
DET

U16

1

2

S DIO(B R) NUP4301MR6T1 TSOP-6@

TAITW_PMPAT6-06GLBS7N14N0CONN@

CH1

CH4

Vn

CH23CH3

6

5

Vp

4

1

VCC

2

RST

3

CLK

C462

8

GND

9

GND

WWAN@

D

1

2

UIM_PWR
UIM_RST
UIM_CLK

18P_0402_50V8J

WWAN@

+3V_WWAN

+3V_WWAN

D17

DAN217T146_SC59-3@

4.7U_0805_10V4Z
C464

C463

1

1

2

2

WWAN@

3

1

2

0.1U_0402_16V4Z

Title

WLAN&WWAN Mini-Card

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

LA-4961P

E

27 54Thurs day, August 27 , 2009

1.0

CAP_CLK<33>
CAP_DAT<33>
CAP_INT<33>

HDA_S DOUT_MDC<21>

HDA_S YNC_MDC<21>

HDA_S DIN1<21>

HDA_RST#_MDC<21>

delet e MOD EM_DIS ABLE# 1/22 HP

Cap SWITCH BOARD. INT_KBD CONN.

1
3
5
7

9
11
13
15
17
19
21
23

ACES 85203-12021 12P P1.0

CONN@

+3VS

R293 0_0402_5%

1 2

1 2

C468

10P_0402_25V8K@

for i mprov e batt ery l ife
HP 2/ 11

JP13

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

R289 5.1K_0402 _5%

R290 5.1K_0402 _5%

12

12

R291

10K_0402_5%

12

R448 0_0402_5%

1 2

R449 0_0402_5%

1 2

R450 0_0402_5%

1 2

10/09 EMI

1 2

R292 33_0402_5%

1 2

R537 4.7K_0402_5%

CAP_RST_EC<33>
WL/BT_LED#<31>

2

1

2

2

C673

C674

1

1

@

@

10P_0402_50V8J

10P_0402_50V8J

STB_LED#<31,32>
ON/OF F#<21,25,32>

C675

@

10P_0402_50V8J

MDC 1.5 Conn.

JP15

ACES_88020-12101_12PCONN@

1

HDA_S DOUT_MDC

HDA_S YNC_MDC
HDA_S DIN1_MDC

1

3

3

5

5

7

7

9

9

11

11

GND13GND14GND15GND16GND17GND

LID_SW#

2

2

4

4

6

6

8

8

10

10

12

12

18

2
4
6
8
10
12
14
16
18
20
22
24

+3VS+3VS +VREG3_51125+VREG3_51125+VREG3_51125

CAP_RST_EC
WL/BT_LED#

CAP_CLK
CAP_DAT
CAP_INT

STB_LED#
ON/ OFF#ON/OFF#
LID_SW#

HDA_B ITCLK_MDC <21>

+VREG3_51125

HP, 7 /3

12

R574
47K_0402_5%

C465

1000P_0402_50V7K

1

2

LID_SW# <17,21,33>

+3VS

C466

0.1U_0402_16V4Z

C467

1

1

2

2

D34

1

DAP202U_SOT323-3
D36

1

DAP202U_SOT323-3
D38

1

DAP202U_SOT323-3
D40

1

DAP202U_SOT323-3

2

2

4

4

6

6

8

8

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

63
64

KSO[0.. 13]

KSI [0..7]

KSO11
KSO0
KSO2
KSO5
KSI_D_14
KSI_D_8
KSI_D_12
KSI_D_10
KSI_D_0
KSI_D_4
KSI_D_2
KSI_D_1
KSI_D_3
KSO3
KSO8
KSO4
KSO7
KSO6
KSO10
KSO1
KSI_D_5
KSI_D_6
KSI7
KSI_D_13
KSI_D_11
KSI_D_9
KSO9
KSO12
KSO13

2

3

2

3

2

3

2

3

KSI_D_3

KSI_D_11

KSI_D_4

KSI_D_12

KSI_D_5

KSI_D_13

KSI_D_6

KSI_D_14

KSO[0.. 13]<33>

KSI [0..7]<33>

D35

KSI_D_0

1

DAP202U_SOT323-3
D37

1

DAP202U_SOT323-3
D39

1

DAP202U_SOT323-3

KSO11
KSO0
KSO2
KSO5
KSI_D_14
KSI_D_8
KSI_D_12
KSI_D_10
KSI_D_0
KSI_D_4
KSI_D_2
KSI_D_1
KSI_D_3
KSO3
KSO8
KSO4
KSO7
KSO6
KSO10
KSO1
KSI_D_5
KSI_D_6
KSI7
KSI_D_13
KSI_D_11
KSI_D_9
KSO9
KSO12
KSO13

2

3

2

3

2

3

KSI_D_8

KSI_D_1

KSI_D_9

KSI_D_2

KSI_D_10

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

61
62

KSI0

KSI1

KSI2

4.7U_0805_10V4Z

@

KSI3

KSI4

KSI5

KSI6

JP14

1

1

3

3

5

5

7

7

9

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

GND1

GND3

GND2

GND4

HIROSE FH12HP- 30S-1SV 55 30PCONN@

@

KSI_D_3
KSO3

2

KSO8

3

KSO4

4 5

100P_1206_8P4C_50V8K

@

KSI_D_0
KSI_D_4

2

KSI_D_2

3

KSI_D_1

4 5

100P_1206_8P4C_50V8K

@

KSI_D_14
KSI_D_8

2

KSI_D_12

3

KSI_D_10

4 5

100P_1206_8P4C_50V8K

@

KSO11
KSO0

2

KSO2

3

KSO5

4 5

100P_1206_8P4C_50V8K

@

KSI_D_11
KSI_D_9

2

KSO9

3

KSO12

4 5

100P_1206_8P4C_50V8K

@

KSI_D_5
KSI_D_6

2

KSI7

3

KSI_D_13

4 5

100P_1206_8P4C_50V8K

@

KSO7
KSO6

2

KSO10

3

KSO1

4 5

100P_1206_8P4C_50V8K

@

KSO13

C703

100P_0402_50V8J

CP2

CP4

CP6

CP7

CP1

CP3

CP5

1 2

81
7
6

81
7
6

81
7
6

81
7
6

81
7
6

81
7
6

81
7
6

Power button

ON/ OFF#

+3VL

100K_0402_5%

R294

12

1

C473

0.1U_0402_10V6K

2

R295 0_0402_5%

1 2

HP re quest 11/28

ON/OFF BTN# <21,25,32>

ON/OFF BTN_KBC# <33>

TrackPoint CONN.

JP33

1

+5VS

SP_CLK<33>

ACES_87153-08011_8P

2

1

2
4
6

8
10
12

4
6
8
10
12

Compa l, 4/ 1

SP_DATA

SP_DATA <33>

2008/03/13 2009/05/11

3

3

5

5

7

7

9

9

11

11

CONN@

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+5VS

1

C651

0.1U_0402_16V4Z

2

Compal Secret Data

Deciphered Date

cor re ct KB co nn ec tor Mat rix. com pal 12/2 4

Title

Size Doc ument Number Re v

Date: Sheet

Compal Electronics, Inc.

MDC/KBD/ON_OFF/LID

LA-4961P

1.0

of

28 54Thursday, August 27, 2009

A

B

C

D

+3VS

+3V ALW

E

Finger printer TPM1.2 on board

+3V ALW

Q4 9 AP 2301 GN 1P_SOT 23

S

D

13

C4 78 0.1U_0 402_1 6V4Z

C4 79 10U_08 05_10V 4Z

USB 20_N1 3<21>

G

2

1

2

USB 20_P13<21>

1

2

+5V ALW

USB 20_N 13

US B20_ N1_P WR

D2 7

2

4

IO1

VIN

1

3

GND

IO2

CM1 293A-0 2SR_SOT14 3-4

ESD 2/18

HP, 4/8

PCI _RST#<19,27>

+5V ALW

2

G

R2 96
10K _0402_5%

1 2

R2 97
220K _0402_1%

1 2

13

D

Q5 0

2N70 02_SOT2 3-3

S

1 1

2 2

JP2 0

1
3
5
7

CO NN@

ACE S_85 203-04021

USB 20_P13 PLT_ RST#

US B20_ N1_P WR

2

1

2

USB 20_N 13

4

3

4

USB 20_P13

6

5

6

8

7

8

R2 98 10K _0402_5%

4.7K _0402 _5%@

0_04 02_5%

1 2

+3VS

12

R3 03

12

R3 04

CLK _PCI_TP M<19>

1 2

1 2

C4 80

@

10P _0402_50V 8K

PM _CLK RUN#< 19,33 ,34>

1 2

C4 81 22 P_040 2_50V8J

32.7 68KH Z 1TJ S125 DJ4A420P

1 2

C4 82 22 P_040 2_50V8J

2

3

Y5

NC

NC

R3 00 10_04 02_5%

IN

OUT

@

1

4

C4 74

1

2

LPC _LAD0
LPC _LAD1
LPC _LAD2
LPC _LAD3
LPC _LFR AME#

SI RQ

TPM_XTALO

TPM_XTALI

12

C4 75

0.1U _0402 _16V4Z

1

2

26
23
20
17
22
16
28
27
21

15

7

14

13

TPM_XTALI

R3 05
10M _0402_5%

TPM_XTALO

C4 76

0.1U _0402 _16V4Z

0.1U _0402 _16V4Z

1

2

U1 8

LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
LPCPD#
SERIRQ
LCLK

SL B 96 35

SL B 96 35 T T 1.2

SL B 96 35SLB 9 63 5

CLKRUN#

PP

XTALO

XTALI/32K IN

5

10

19

24

VDD

VDD

VDD

GPIO2

T T 1.2

T T 1.2 T T 1.2

TEST1

TESTB1/BADD

GND

GND

GND

GND

SLB 9635 T T 1.2_TSS OP28

4

11

18

25

C4 77

0.1U _0402 _16V4Z

1

2

VSB

6

GPIO

2

Base I/O Address
0 = 02Eh
1 = 04Eh*

8
9

3

NC

12

NC

1

NC

TPM_G PIO
TPM_G PIO2

R3 01

0_04 02_5%

1 2

T7PAD
T8PAD

R2 99

4.7K _0402 _5%

1 2

R3 02

4.7K _0402_5 %

+3VS+3VS

12

@

Add SIRQ and connect to

Issued Date

pin5.

8051 _REC OVER#

51125_PWR

+3VL

12

R3 06

100K _0402_5 %

CL K_PCI _DB<1 9,22>

LPC _LFRA ME#<1 9,27, 33,34>

SI RQ<19 ,33,34>

PLT_R ST#<11 ,19, 25,27 ,31,34>

PC I_SE RR#<1 9,33>

LPC _LAD0<19, 27,33 ,34>
LPC _LAD1<19, 27,33 ,34>
LPC _LAD2<19, 27,33 ,34>
LPC _LAD3<19, 27,33 ,34>

8051TX<33>

8051RX<33>
8051 _REC OVER#<33>
DEB UG_K BCRST< 41>

HP 2/11

KBC _SPI _CS1 #_R<3 3>

2008/09/15 2009/09/15

C4 83

1 2

SPI _CS0 #SPI _CS0 #_JP

+3VL

1

2

20mils

SPI _WP#

SPI _HOL D#_1

SPI _CS0 #

SPI _WP#

U1 9

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

WIE SO_G 6179-100 000_8P

SPI _CS0 #

VSS

1 2

R3 10 0_ 0402_5%@

+3VL

4

2

Q

R5 60
100K _0402_5 %

1 2

2MB SPI ROM

SST25VF016B-50_SO8

SPI _SO _RSPI _SI

1 2

R3 08 15_0 402_5%

HP 3/25

&U 1

@

SPI _SO <33 >

HP BIO S request (DB2 12/02)

BIOS ROM

0.1U _0402 _16V4Z

3 3

4 4

connec t to KBC pin108. HP 2/3

+3VL

SPI _CS0#<33>

SPI _CLK<33>

SPI _SI<33>

20mils

SPI _CLK

SPI _HOL D#_0 SPI _HOL D#_1

SPI _CLK _JP SPI _CLK

SPI _SI_ JP SP I_SI

SPI _SO _R S PI_S O_JP

SPI _WP#<33>

1 2

R3 07 3.3K _0402 _5%

20mils

+3VL

R3 11 0_04 02_5%

R3 12 0_04 02_5%

R3 13 0_04 02_5%

R3 14 0_04 02_5%

R5 11 0_04 02_5%

R3 09 1 0K_04 02_5%

1 2

1 2

1 2

1 2

1 2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

LPC Debug Port

SI RQ

8051 _REC OVER#

SPI _CLK _JP
SPI _CS0 #_JP
SPI _SI_ JP
SPI _SO_J P
SPI _HOL D#_0

Compal Secret Data

Deciphered Date

D

JP2 1

1

Ground

2

LPC_PCI_CLK

3

Ground

4

LPC_FRAME#

5

+V3S

6

LPC_RESET#

7

+V3S

8

LPC_AD0

9

LPC_AD1

10

LPC_AD2

11

LPC_AD3

12

VCC_3VA

13

PWR_LED#

14

CAPS_LED#

15

NUM_LED#

16

VCC1_PWRGD

17

SPI_CLK

18

SPI_CS#

19

SPI_SI

20

SPI_SO

21

SPI_HOLD#

22

Reserved

23

Reserved

24

Reserved

ACE S_87 216-2404_24P

CO NN@

Title

Size D ocum ent N umber R ev

Da te: She et

Compal Electronics, Inc.

TCG/BIOS ROM/PS2/SW LPC DEBUG

LA -49 61P

E

o f

29 54Thur sday , Au gust 27, 20 09

1. 0

5

4

US B_VC CA+5V ALW

3

2

1

+5V ALW

4.7U _0805 _10V4Z

SLP _S5

4.7U _0805 _10V4Z

4.7U _0805 _10V4Z

SLP _S5

SLP _S5

C4 84

@

+5V ALW

C4 90

+5V ALW

C6 89

D D

C C

B B

A A

SLP_S 5<25 ,31,3 2,36>

U2 0

1

GND

2

IN

3

IN

4

1

2

EN#

TPS 2068I DGNG4-R _MSOP8

(2A,10 0mils ,Via N O.=4)

US B_VC CA USB _VCC B

R4 70
0_08 05_5%

1 2

U2 1

@

1

GND

2

IN

3

IN

4

1

2

1

2

EN#

TPS 2068I DGNG4-R _MSOP8

(2A,10 0mils ,Via N O.=4)

U3 0

1

GND

2

IN

3

IN

4

EN#

TPS 2068I DGNG4-R _MSOP8

(2A,10 0mils ,Via N O.=4)

8

OUT

7

OUT

6

OUT

5

OC#

8

OUT

7

OUT

6

OUT

5

OC#

8

OUT

7

OUT

6

OUT

5

OC#

R3 15
10K _0402_5%

1 2

@

1 2

@

1 2

W=100m ils

150U _D_6. 3VM

1

+

C4 85

2

R3 18

10K _0402_5%

W=100m ils

1

+

C4 91

2

R4 82
10K _0402_5%

W=100m ils

1

+

C6 90

2

JU SB1

1

1

2

D2 9

I/O1

REF1

I/O23I/O3

PJU SB208_ SOT23-6@

USB 20_P0<21>

1

2

2

3

3

4

4

5

GND

6

GND

7

GND

8

GND

SUY IN_02 0167M R004 S511Z R_4PC ONN @

R5 00 0_04 02_5%@

1 2

L46

1

USB 20_N3<21>

USB 20_P3<21>

JU SB2

1

1

2

2

3

3

4

4

5

GND

6

GND

7

GND

8

GND

SUY IN_02 0167M R004 S511Z R_4PC ONN @

USB 20_N5<21>

USB 20_P5<21>

US B20_ N5_RUSB 20_P 5_R

6

I/O4

5

REF2

JU SB3

1

1

2

2

3

3

4

4

5

GND

6

GND

7

GND

8

GND

SUY IN_02 0167M R004 S511Z R_4PC ONN @

USB 20_N0<21>

US B_VC CA

USB 20_P 3_RUS B20_ N3_R

4

02/18 ESD

R5 04 0_04 02_5%@

1 2

L48

1

1

4

4

WCM 2012F 2S-900 T04_0805

1 2

R5 05 0_04 02_5%@

1

4

4

WCM 2012F 2S-900T 04_0805

1 2

R5 01 0_04 02_5%@

R5 02 0_0 402_5%@

L47

1

4

WCM 2012F 2S-900 T04_0805

R5 03 0_0 402_5%@

2

2

USB 20_P 0_R
US B20_ N0_R

3

3

1 2

1

4

1 2

2

2

US B20_ N3_R
USB 20_P 3_R

3

3

2

2

US B20_ N5_R
USB 20_P 5_R

3

3

+3VS

+3VS

JP2 3

ACE S_87 212-05G0_5P

CO NN@

BT_ OFF<21>

ACC EL_IN T#< 19>

SMB _CK_DA T0<4,6,8 ,9,1 5,21>
SMB _CK_ CLK0<4,6, 8,9, 15,21>

R3 21 10K _0402_5%

US B20_ N3_R

US B20_ N0_RUSB 20_P 0_R

02/18 ESD

USB 20_P 3_R

US B_V CCC

US B20_ N5_R
USB 20_P 5_R

US B20_ N0_R
USB 20_P 0_R

1000 P_0402_ 50V7K

0.1U _0402 _16V4Z

1

1

C4 87

C4 86

2

2

US B_VC CB+5VA LW

swap J USB3 & JUS B2 US B sign al for USB debug port (USB port 0) HP 2/10

1000 P_0402_ 50V7K

0.1U _0402 _16V4Z

150U _D_6. 3VM

1

1

@

@

C4 93

2

2

C4 92

US B_V CCC+5VA LW

150U _D_6. 3VM

1000 P_0402_ 50V7K

0.1U _0402 _16V4Z

1

1

C6 92

C6 91

2

2

D2 8

1

2

I/O1

REF1

I/O23I/O3

PJU SB208_ SOT23-6@

REF2

6

I/O4

5

4

BT Connector

1
2

USB 20_P 11_R

R3 16 0 _0402_ 5%

3
4
5

USB 20_N1 1_R

12

1 2

R3 17 0 _0402_ 5%

1 2

R3 19
10K _0402_5%

R3 20

1 2

220K _0402_1 %

Q51

S

G

AP2 301GN 1P_SOT23

2

ACCELEROMETER

U2 2

LIS302DL

1

VDD_IO

6

VDD

8

INT 1
INT 29GND

12

SDO

13

SDA / SDI / SDO

14

12

Mus t be place d i n the cent er of the s yst em.

L

Change U12 p art de script ion from
LIS302 DLTR L GA to HP302D LTR8 as HP
change list. 12/03

SCL / SPC

7

CS

HP3 02DLT R8_LGA14_3 X5

GND
GND
GND

RSVD
RSVD

2
4
5
10

3
11

+3VAUX _BT

D

13

+3VS

+3VAUX _BT+3VS

C4 88 0.1 U_040 2_16V4Z

1

2

0.1U _0402 _16V4Z

C4 94

1

2

USB 20_P11 <21>
USB 20_N1 1 <21>
BT_L ED <31>

C4 89 10U _0805 _10V4Z

1

2

+3VS

10U_ 0805_6. 3V6M

C4 95

1

2

HP 2/12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/09/15

Compal Secret Data

Deciphered Date

2

Title

Size D ocum ent N umber R ev

Da te: She et of

Compal Electronics, Inc.

USB & BT Connector & Acclerometer

LA -49 61P

1

30 54Thur sday , Au gust 27, 20 09

1. 0

5

4

3

2

1

Audio/Express Card/TP/LEDs Connector

DOCK_ LINE_IN_L<32>
DOCK_ LINE_IN_R<32>

LINE_ IN_SENSE<32> LINE_OUT_SENSE <32>

HDA_B IT_CLK_CODEC<21>

D D

C C

B B

HDA_S DOUT_CODEC<21>

HDA_R ST#_CODEC<21>

HDA _SYNC_COD EC<21>

LAN_PCIE_W AKE#<21,25,27>

AMBER_BATLED#<33>

AQUAWHITE_BATLED#<33>

HDD_H ALTLED<20>

HDA_S DIN0<21>

+VREG3_51125

HP 2/ 17

SLP_S3#<21,33,36,39>

PLT_RST#<11,19 ,25,27,29,34>

CPPE_NC#<15,20,21>

SATA_LED#<20,32>

STB_LED#<28,32>

WL/BT_LED#<28>

DTA114YKAT146_SOT23-3

WW_LED#<27>

DTA114YKAT146_SOT23-3

DOCK_ LINE_IN_L
DOCK_ LINE_IN_R
LINE_ IN_SENSE LIN E_OUT_SENSE

HDA_B IT_CLK_CODEC
HDA_S DOUT_CODEC
HDA_R ST#_CODEC
HD A_SYNC_CO DEC
HDA_S DIN0

+3VALW

+5VS
+3VS

+1.5VS

SLP_S3#
LAN_PCIE_W AKE#
PLT_RST#
CPPE_NC#
AMBER_BATLED#
AQUAWHITE_BATLED#
SATA_LED#
HDD_H ALTLED#
STB_LED#
WL/BT_LED#

+3VS

47K

Q52

10K

2

1 3

13

2

10K

47K

Q53

+3V_WWAN

10 /2 1 mo ve 13 94 A t o c ard r eade r US B bo ard

A A

JP34

1

1

3
5
7
9

13
15
17
19
21
23
25
27
29
31
33
35

39
41
43
45
47
49

BT_LED<30>WL_LED#<27>

2

3

4

5

6

7

8

9

10

111112

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

30

29

32

31

34

33

36

35
373738
39

40

41

42

43

44

45

46

47

48

49

50

515152

E-T_1001K-F50E-08E_50P-T

CONN@

BT_LED

WL_LED

remov e UWB LED# 10/31

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

52

DLINE_OUT_L
DLINE _OUT_R

A_SD#
EAPD
HDA_SPKR

CLK_PCIE_EXP#
CLK_PCIE_EXP

PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_P3

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3

USB20_N1
USB20_P1

TP_CLK
TP_DATA

+3VS

12

61

2

5

R322
47K_0402_5%

WL/BT_LED#

Q8A
DMN66D0LDW-7_SOT363-6

3

Q8B
DMN66D0LDW-7_SOT363-6

4

BT_LED

WL_LED

DLINE _OUT_L <32>
DLINE _OUT_R <32>

A_SD# <33>

EAPD <33>

HDA_SPKR <21>

CLK_PCIE_EXP# <15>
CLK_PCIE_EXP <15>

PCIE_PTX_C_DRX_N3 <10>
PCIE_PTX_C_DRX_P3 <10>

PCIE_PRX_DTX_N3 <10>

PCIE_PRX_DTX_P3 <10>

USB20_N1 <21>
USB20_P1 <2 1>

TP_CLK <33>
TP_DATA <33>

corre ct th e net name 1/15 Compal

R323 100K_0402_5%

1 2

R324 100K_0402_5%

1 2

Card Reader 7 in 1 + 1 Port USB Connector

+VREG3_51125 +3VALW +5VS +3VS +1.5VS

HP 2/ 17

0.1U_0402_16V4Z

C680

1 2

1

1

1

1

C646

C647

2

1U_0402_6.3V6K

P-TWO_196087-18021-3_18P-T

chang e boa rd to board cont or to wire to b oard conne ctor. Compa l 12/12

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

JP29

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

19

17

19

20

18

20

CONN@

powe r-dow n of 1 394/c ardre ader chip when no ca rd/13 94 ins erted HP 3/24

CRD_RST#

DMN66D0LDW-7_SOT363-6

CRD_R EQ#<15,21>

C648

1U_0402_6.3V6K

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

1

C649

C650

2

2

1U_0402_6.3V6K

cha ng e 0 .1 U t o 1 U , HP 3 /23

+5VALW

USB20_N2
USB20_P2
SLP_S5

CRD_RST#

CRD_L OCAL

CLK_P CIE_CARD
CLK_P CIE_CARD#

PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1

PCIE_PRX_DTX_P1
PCIE_PRX_DTX_N1

1 2

R541 10K_0402_5%

61

Q18A

CRD_L OCAL

SIO_GPIO43<34>

R542 15K_0402_5%

2

1 2

1

C711

2

0.022U_0402_16V7K

2N7002_SOT23-3

12

R566

@

0_0402_5%

Q23

USB20_N2 <21>
USB20_P2 <21>

SLP_S5 < 25,30,32,36>

+3VS_CD

HP 6/ 8

CLK_P CIE_CARD <15>

CLK_P CIE_CARD# <15>

PCIE_PTX_C_DRX_P1 <10>
PCIE_PTX_C_DRX_N1 <10>

PCIE_PRX_DTX_P1 <10>
PCIE_PRX_DTX_N1 <10>

PLT_RST#

HP 6/ 8HP , 6/13

+3VS_CD

13

D

2

G

S

R567

1 2

680K_0402_5%

R565
15K_0402_5%

1 2

HP 4/ 7

14vs15 _FF_DETECT<33>

DMN66D0LDW-7_SOT363-6

1
@

C718

2

0.1U_0402_16V4Z

2

C717
1U_0402_6.3V4Z

1

+3VS

5

Serial Port CONN

+5VS

+5VS

2

Q18B

HP 6/ 8

3

4

S

Q106

R559

47K_0402_5%

1 2

61

DCD#1
DSR#1
RXD1
RTS#1
TXD1
CTS#1
RI#1
DTR#1
SER_SHD

5

G

2

Q109A
DMN66D0LDW-7_SOT363-6

DCD#1<32,34>
DSR#1<32,34>
RXD1<32,34>
RTS#1<32,34>
TXD1<32,34>
CTS#1<32,34>

RI#1<32,34>

DTR#1<32,34>

SER_S HD<32>

CRD_L OCAL

SI2301BDS_SOT23

R55847K_0402_5%

1 2

3

Q109BDMN66D0 LDW-7_SOT363-6

4

D

13

4.7U_0805_25V6-K

JP35

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

14

10

14

11

13

11

13

12

12

E-T_3800K-F12N-03R_12P

CONN@

ADP_PRES <20,25 ,33,36,39,46>

+3VS_CD

1

C684

2

HP 2/ 3

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/01 2010/09/01

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

CR&LEDS&PW&Audio&Exp Conn

LA-4961P

31 54Th urs day, Au gust 27, 2009

1

1.0

(1) PC I Express x1 channels
(2) PS / 2 Interfaces
(2) US B 2.channels
(2) SA TA Channels
(2) Di splay Port Channels
(1) Se rial Port
(1) Pa rallel Port
(1) Line In
(1) Line Out
(1) RJ 45 (10/100/1000)
(1 ) VGA
(1) 2 LAN indicator LED's
(1) Po wer Button
(1) I2 C interface

1/15 HP

DPB_TX P0<10>
DPB_T XN0< 10>

DPB_TX P1<10>
DPB_T XN1< 10>

DPB_TX P2<10>
DPB_T XN2< 10>

DPB_TX P3<10>
DPB_T XN3< 10>

HDM ICLK _UMA< 11,18>
HDM IDAT _UMA<1 1,18>

VA

C5 06 0.1U _0603 _50V4Z

C5 07 0.1U _0603 _50V4Z

1

1

2

2

VA

MDO 3+

MDO 3+<26>
MDO 3-<26>

MDO 2+<26>
MDO 2-<26>

HP 2/3

MDO 3-

MDO 2+

MDO 2-

DET ECT

+5VS

1/15 HP

DPB_TX P0

DPB _TXN0

DPB_TX P1

DPB _TXN1

DPB_TX P2

DPB _TXN2

DPB_TX P3

DPB _TXN3

thi s c ir cui t w il l be on d ock s taton , HP 12/0 2

DOCK CONN. 184PIN

VIN VA

L41

HCB 2012K F-121 T50_0805

1 2

JD OCKA

190

P1

G1

188
187
186
185
184
183
182

181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144

FOX _QL00 94L-D26601 -8H

1

188

2

187

3

186

4

185

5

184

6

183

7

182

8

181

9

180

10

179

11

178

12

177

13

176

14

175

15

174

16

173

17

172

18

171

19

170

20

169

21

168

22

167

23

166

24

165

25

164

26

163

27

162

28

161

29

160

30

159

31

158

32

157

33

156

34

155

35

154

36

153

37

152

38

151

39

150

40

149

41

148

42

147

43

146

44

145

45

144

189

1

MDO 1+

2

MDO 1-

3
4

MDO 0+

5

MDO 0-

6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

DPC_ TXP0

31

DPC _TXN0

32
33

DPC_ TXP1

34

DPC _TXN1

35
36

DPC_ TXP2

37

DPC _TXN2

38
39

DPC_ TXP3

40

DPC _TXN3

41
42

DOC K_AUX+

43

DOC K_AUX-

44
45

R4 40

1 2

10K _0402_5%

2

G

ADP _SIG NAL
HDM ICLK _UMA
HDM IDAT _UMA

LPTSTB#
LPT AFD#
LPT ERR#
LPT ACK#
LPT BUSY
LPTPE
LPTS LCT
LP D7
LP D6
LP D5
LP D4
LP D3
LP D2
LP D1
LP D0
LPT SLCTI N#
LPT INIT#
STB _LED# _R

PRE P#

U2 4

1

2

TS5 A3157_S C70-6

+5V ALW

NO

GND

NC3COM

SATA_ SRX_DTX_P2
SATA_ SRX_DTX_ N2

SATA_ SRX_DTX_P3
SATA_ SRX_DTX_ N3

HP 2/18

IN

VCC

DOCKING CONNECT

+5VS

C5 09

C5 08

10U_ 0805_ 10V4Z

1

1

2

2

1/15 HP

MDO 1+ <26>
MDO 1- <26>

MDO 0+ <26>
MDO 0- <26>

LAN LINK_ STATUS# <21, 25,26>

+5VS

HP 2/4HP 2/4

HP 2/18HP 2/18 HP 2/18

LAN _ACT# <25,26>

USB 20_N6 <21>

USB 20_P6 <21>

DPC_T XP0 <10>
DPC _TXN0 < 10>

DPC_T XP1 <10>
DPC _TXN1 < 10>

DPC_T XP2 <10>
DPC _TXN2 < 10>

DPC_T XP3 <10>
DPC _TXN3 < 10>

DOC K_AUX+ <11>
DOC K_AUX- <11>

C5 11

C5 10

0.1U _0402 _16V4Z

0.1U _0402 _16V4Z

0.1U _0402 _16V4Z

1

1

2

2

+5VS

SE R_SH D<31>

SE R_S HD

HP 10/3 1

+5V ALW

1 2

3

4

10/ 17 H P

D

Q8 2

S

DP B_HP D<18>

LPTSTB#<34>
LPT AFD#<34>
LPT ERR#<34>
LPTA CK#<34>
LPT BUSY<34>

LPTPE<34 >

LPTS LCT<34>

LP D7<34>
LP D6<34>

SATA_ SRX_DTX_P2<20 >
SATA_ SRX_DTX_N2<20>

SATA_ SRX_DTX_P3<20 >
SATA_ SRX_DTX_ N3<20 >

LPT SLCTIN#<34>

LPT INIT#<34>

SAT A_LED#<20,31>

USB 20_N8<21>
USB 20_P8<21>

VGA _RED< 16>

LP D5<34>
LP D4<34>
LP D3<34>
LP D2<34>
LP D1<34>
LP D0<34>

PRE P#<21>

STB _LED# < 28,31>

DO CK _RED

R4 98

4.7K _0402 _5%

1 2

Q3A

61

DMN 66D0L DW-7 _SOT363- 6

PRE P# DO CK _ID

2

SATA_ STX_DRX_P2<20 >
SATA_ STX_DRX_ N2<20 >

SATA_ STX_DRX_P3<20 >
SATA_ STX_DRX_ N3<20 >

R5 38
10K _0402_5%

STB _LED# _R

Q3B

5

DMN 66D0L DW-7 _SOT363- 6

HP 2/4

2N70 02_SOT2 3-3

13

ADP _SIG NAL

6

5

4

SLP_S 5 <25 ,30,3 1,36>

HP 12/03

143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

192
194
196
198
200

DO CK _ID

+5VS

0.1U _0402 _16V4Z

RE D_R <16>

JD OCK B

143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

99

99

98

98

97

97

96

96

95

95

G2
G4
G6
G8
G10

FOX _QL00 94L-D266 01-8H

C5 20

12

change +5VS to + 5VALW for RJ45 LED issue Compal 2/9

HP 2/3

DO CK _GRN

DO CK _ID

VA_ ON#

DP C_H PD <11 >

ON /OFF BTN# <21,2 5,28>

D_ DDC DATA <11,16>

D_ DDC CLK <11,16>

D_ VSY NC < 16>
D_ HS YNC <16>

GND

GND

GND

DC D#1 <31,34 >
RI #1 <3 1,34>

DT R#1 <3 1,34>
CTS# 1 <31 ,34>
RTS# 1 <31 ,34>

DS R#1 < 31,34>

LINE _OUT _SENSE <31>

U2 6

1

NO

2

GND

NC3COM

TS5 A3157_S C70-6

TXD1 < 31,34>

RXD1 <31, 34>

KBD _DATA <33>
KBD _CLK <33>
PS2 _DATA < 33>
PS2 _CLK < 33>
LINE _IN_ SENS E <31>

DO CK_L INE_ IN_L <3 1>
DO CK_ LINE _IN_R <31>

DLIN E_OU T_L < 31>
DL INE_O UT_R <31>

6

IN

5

VCC

4

DO CK_ ID<18,20 >

HP 12/03

46

46

47

47

48

48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94

G1
G3
G5
G7
G9

49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94

191
193
195
197
199

ON /OFF BTN#
VA_ ON#
DOC K_AUX+
DOC K_AUX-

DD C-DA TA
DD C_C LK

DO CK _RED

DO CK _GRN
DO CK_ BLU

D CD# 1

RI #1
DT R#1
CTS #1
RTS #1
DS R#1
TXD1

RXD 1

1/15 HP

KBD _DATA

KBD _CLK
PS 2_DATA
PS2 _CLK

LINE _OUT _SENS E

DL INE _IN_L
DL INE _IN_ R

DLIN E_OU T_L
DL INE_ OUT_ R

DET ECT

VG A_GR N< 16>

R3 40

1 2

10K _0402_5%

12

R3 39

1K_ 0402_5%

1/15 HP1/15 HP

DO CK _ID

+5VS

+5V ALW

1

C5 05

0.1U _0402 _16V4Z

2

C5 22

12

0.1U _0402 _16V4Z

GR EEN _R <16>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/09/15 2009/09/15

Compal Secret Data

Deciphered Date

U2 5

VGA _BLU< 16>

Title

Size D ocum ent N umber Re v

Cu stom

Da te: She et

1

NO

2

DO CK_ BLU

GND

NC3COM

TS5 A3157_SC 70-6

Compal Electronics, Inc.

DOCK CONN

LA -4 961 P

DO CK _ID

6

IN

+5VS

5

VCC

4

0.1U _0402 _16V4Z

BL UE_R <16>

32 54Thur sday , Au gust 27, 2 009

C5 21

12

1. 0

o f

+3VL

RP 15

KSI 3

1 8

KSI 2

2 7

KSI 1

3 6

KSI 0

4 5

10K _0804 _8P4R_5%

RP 16

KSI 7

1 8

KSI 6

2 7

KSI 5

3 6

KSI 4

4 5

10K _0804 _8P4R_5%

+5VS

TP _CLK

1 2

R3 61 10K_ 0402_5%

TP_DAT A

1 2

R3 65 10K_ 0402_5%

RP 17

SP_ CLK

1 8

SP _DATA

2 7

PS2 _CLK

3 6

PS 2_DATA

4 5

10K _0804 _8P4R_5%

from Power

4IN1

33P _0402_50 V8J

Y6

C5 32

1

2

33P _0402_50 V8J

C5 33

OUT

1

NC3NC

2

OC P_I N_AD C< 46>

2

32.7 68KH Z 1TJ S125 DJ4A420P

33pF o nly fo r 1070 /1091

+R TCVC C

C5 34

1U_0 603_1 0V4Z

C5 35

0.1U _0402 _16V4Z

1

1

2

2

HP 12/5

PMC<39>

add on e mor e 0.1 U for SMSC design guideline 12/10

SPI _SI<29>

KBC _SPI _SI<20>

SPI _CS0#<29>

KBC _SPI _CS0#< 20>

SPI _SO<29>

KBC _SPI _SO<20>

KSO [0.. 13]<28>

KS I[0. .7]< 28>

TP_C LK<31 >
TP_DAT A<31>
SP_ CLK<28>
SP_ DATA<28>
PS2 _CLK<32>

PS2 _DATA<32>

PM _CLK RUN#< 19,29 ,34>
SI RQ<19 ,29,34>
CLK _PCI_ KBC< 19,22>
RU NSC I_E C#<21>

LPC _LAD3<19 ,27,29 ,34>
LPC _LAD2<19 ,27,29 ,34>
LPC _LAD1<19 ,27,29 ,34>
LPC _LAD0<19 ,27,29 ,34>

LPC _LFRA ME#<1 9,27, 29,34>
NPC I_RST #<2 0,34>

+R TCVC C

BAT_A LARM<40>
KBC _SPI _CLK<20 >
SPI _CLK< 29>

KBC _SPI _CS1 #_R<2 9>

MC1 _DISA BLE<27>

1 2
1 2

C7 15

2200 P_0402_ 50V7K

0.1U _0402 _16V4Z
C7 10

1

@

2

KS O0
KS O1
KS O2
KS O3
KS O4
KS O5
KS O6
KS O7
KS O8
KS O9
KS O10
KS O11
KS O12
KS O13

KSI 0
KSI 1
KSI 2
KSI 3
KSI 4
KSI 5
KSI 6
KSI 7

TP _CLK

TP_DAT A
SP_ CLK
SP _DATA

PS2 _CLK

PS 2_DATA

CLK _PCI_ KBC

RU NSC I_E C#

CR Y1
CR Y2

R3 86300_ 0402_5%
R3 87300_ 0402_5%

2

2

C7 16
2200 P_0402_ 50V7K

1

1

add fi lteri ng ci rcuit for AD input. HP 5/29

0.1U _0402 _16V4Z

0.1U _0402 _16V4Z

C5 23

C5 24

1

2

128
127

97
96
95
94

21
20
19
18
17
16
13
12
10

9
8
7
6
5

29
28
27
26
25
24
23
22

35
36
61
62
66
67

55
57
54
76

51
50
48
46

52
53

70
71

68

1
2

3
30
31
32
33
34
43
44

1

1

2

2

U2 7

FLDATAOUT
HSTDATAOUT/GPIO45
FLCS0#
HSTCS0#/GPIO44
FLDATAIN
HSTDATAIN/GPIO43

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12/GPIO00/KBRST
KSO13/GPIO18

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

IMCLK
IMDAT
KCLK
KDAT
EMCLK
EMDAT

CLKRUN#
SER_IRQ
PCI_CLK
EC_SCI#

LAD[3]
LAD[2]
LAD[1]
LAD[0]

LFRAME#
LRESET#

XTAL1
XTAL2

VCC0

Alarm [CKT#2]/GPIO36
HSTCLK/GPIO41
FLCLK
GPIO39
HSTCS1#/GPIO42
FLCS1#
GPIO38
GPIO37
ADC1/GPIO46
ADC_TO_PWM_IN

KBC 1098- NU_TQF P128_14X14

+3VL

0.1U _0402 _16V4Z

0.1U _0402 _16V4Z

4.7U _0805 _10V4Z

C5 25

C5 26

C5 27

1

1

2

2

Key boa rd/ Mou se Int erf ace

Pow er Mgm t/S IRQ

LPC
Bus

AGND

VSS11VSS37VSS47VSS56VSS

72

1

2

14

106

119

49

VCC1

VCC139VCC158VCC184VCC1

VCC1

VCC2

ADP_PRES[CKT#2]/GPIO27/WK_SE05

Gen era l P urp ose I/ O I nte rface

SMSC_1098-NU_TQFP-128P

Access Bus I nterface

32KHZ_OUT/GPIO22/WK_SE01

Mis cel lan eous

AVSS

VSS82VSS

45

104

117

12

R5 64
0_04 02_5%

1 2

0.1U _0402 _16V4Z
R3 58 0_ 0402_5%

C5 28

GPIO28
GPIO29
GPIO30
GPIO31
GPIO32

OUT0/(SCI)

OUT1/IRQ8#

CFETA/OUT7/nSMI

OUT8/KBRST

OUT9/PWM2

OUT10/PWM0

PWM_CHRGCTL

GPIO01
GPIO02

GPIO03
GPIO04/KSO14
GPIO05/KSO15

GPIO07/PWM3

GPIO08/RXD

GPIO09/TXD

GPIO11/AB2A_DATA

GPIO12/AB2A_CLK

GPIO13/AB2B_DATA

GPIO14/AB2B_CLK
GPIO15/FAN_TACH1
GPIO16/FAN_TACH2

GPIO17/A20M

GPIO20/PS2CLK
GPIO21/PS2DAT

GPIO24/KSO16

AB1A_DATA

AB1A_CLK

AB1B_DATA

AB1B_CLK

GPIO25

GPIO26/KSO17

NC_CLOCKI

RESET_OUT#/GPIO06

PWRGD

VCC1_RST#

ADC_TO_PWM_OUT/GPIO19

TEST PIN

CFETB/GPIO10

BAT_LED#

PWR_LED#/8051TX

FDD_LED#/8051RX

AC[CKT#2]/GPIO23

ADC2/GPIO40

Q/GPIO33

GPIO34
GPIO35

AVCC

+3VS

C5 29 0.1U _0402 _25V6

1 2

C5 30 4.7U _0805 _6.3V6K

15

CAP

93
98
99
100
126

124
125

123
122
121
120
118

107
79
80
81
83

85
86
87

88
89
90
91
92
101
102

103
105
4
74

111
112

109
110

73

108
59
75
60
78
77
38

69

116
113
115
114

41
42
65
64
63
40

1 2

R3 59 0_04 02_5%

1 2

KB C_P WR_O N
AQU AWHI TE_BA TLED#

KB RST#

THM _TRAVEL#

14v s15_F F_DE TECT

PM_ RSMRST#

R3 62300 _0402_5%

1 2

R3 64 10K _0402_5%

1 2

AB 2A_DATA

R3 66 0_04 02_5%

AB2 A_CLK

ADP _DET#

AB 1A_DATA
AB1 A_CLK

AB 1B_DATA
AB1 B_CLK

R3 75 0_0 402_5%

1 2

32K _CLK
S B_PW RGD
SY S_ PWRG D

TEST

R3 85 0 _0402_ 5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

R3 68 0_04 02_5%

1 2

R3 69 0_04 02_5%

1 2

R3 71 0_04 02_5%

1 2

change "BAT CON" to ADP_DET# HP 12/12

R3 73 10K _0402_5%

1 2

R3 74 0_0 402_5%

1 2

1 2

R3 77 0_04 02_5%

1 2

R3 78 0_04 02_5%

R3 82 10K _0402_5%

1 2

1 2

R3 84 0_04 02_5%

+3VL

HP 2/3

SPI _WP# <29>

8051TX
8051RX

1 2

2008/09/15 2009/09/15

+3VL

A _SD

AB1 A_DATA < 38>
AB1 A_CLK <38>

AB1 B_DATA < 38>
AB1 B_CLK <38>

R3 76 10_0402 _5%@

1 2

Compal Secret Data

EAP D <31>
PC I_SE RR# < 19,29>

KB C_P WR_O N <41>
AQU AWHI TE_BA TLED# < 31>

FET _A <40>
KB_ RST# <2 1>
FAN _PWM <4>
BAT _PWM_OUT <39>
CH GCT RL <39>

THM_ TRAVEL# <38>
ON/ OFFB TN_K BC# <2 8>
14v s15_F F_DE TECT <31>
SLP _S3# <2 1,31, 36,39>
8051 _REC OVER# <29>

PM_ RSMRST# <21,42>

ADP _DET# <46>

CAP _DAT <28>
CA P_CLK <28>
CEL LS <39>

THM _MAIN# <38>
GATE A20 <21>

KB D_CLK <32>
KBD _DATA <32>

ADP _PRE S <20 ,25,3 1,36, 39,46>

CAP _INT <28>

CLK _14M_K BC <15>
AD P_EN <39>
SB _PW RGD < 6,21,45>
SY S_ PWRG D <44, 45>
VC C1_ PWRG D <39 ,41>
OC P <46>

FET _B <40>
AMB ER_BAT LED# <3 1>
8051TX < 29>
8051RX <29>

AC_ ADP_ PRES <39>
AD P_I D_AD C <46>
LA TCH <40 >
LI D_SW # <17, 21,28>
CAP _RST _EC <2 8>

Deciphered Date

8/25

A _SD

R5 75 0_04 02_5%

1 2

2N70 02_SOT2 3-3

HP BIO S request (DB2 11/28)

C5 31 10P _0402_2 5V8K@

1 2

13

D

@

S

A_S D# <31>

Q11 5

2

G

SIO _GPIO 41 <34>

HP 4/7

14v s15_F F_DE TECT

KB _RST#

VC C1_ PWR GD

KBD _CLK

KBD _DATA

AD P_I D_AD C

add fi lteri ng ci rcuit for AD input. HP 5/29

Title

Size D ocum ent N umber Re v

Da te: She et of

Compal Electronics, Inc.

LA -49 61P

1 2

R5 62 100K_0 402_5%

1 2

R3 60 10K_04 02_5%

FET _A

FET _B

LAT CH

S B_PW RGD

PM_ RSMRST#

KB C_P WR_O N

SLP _S3#

HP, 4/14

RP 18

4.7K _080 4_8P4R_5 %

AB1 A_CLK
AB 1A_DATA
AB1 B_CLK
AB 1B_DATA

8051TX

8051RX

1 2

R3 80 100K _0402_5 %

1 2

R3 81 100K _0402_5 %

1 2

R3 83 10K _0402_5%

1 2

R4 65 100K _0402_5 %

1 2

R4 66 100K _0402_5 %

C7 14

1 2

2200 P_0402_50 V7K

KBC1091/1098

+3VL

1 2

R4 43 10K _0402_5%

R4 44 10K _0402_5%

R4 45 10K _0402_5%

R3 67 4.7K _0402 _5%

R3 70 10K _0402_5%

R3 72 10K _0402_5%

1 2

1 2

1 2

1 2

1 2

1 2

R4 64 47K_04 02_5%

+3VL

1 8
2 7
3 6
4 5

+3VL

33 54Th ur sd ay , Aug ust 2 7, 2009

1. 0

5

8/25

D D

NPC I_RST #<2 0,33>

+3VS

PLT_R ST#<1 1,19, 25,27 ,29,31>

RP 24

SIO _GPI O46

18

SIO _GPI O45

27

SIO _GPI O44

36

SIO _GPI O43

45

10K _0804 _8P4R_5%

+3VS

RP 25

R5 19

1 2

R5 20

1 2

R5 21

1 2

R5 22

1 2

S IO_IR Q

18

SIO _GPI O12

27

SIO _GPI O10

36
45

10K _0804 _8P4R_5%

SIO _GPI O23

10K _0402_5%

SIO _GPI O41

10K _0402_5%

SIO _GPI O42

10K _0402_5%

SIO _GPI O11

10K _0402_5%

C C

B B

A A

13

D

Q11 6

@

2

G

2N70 02_SOT2 3-3

S

R3 89 2.2K _0402_5 %

+3VS

4

LPC _LFRA ME#<1 9,27, 29,33>

LP C_LD RQ#0<19>

12

1 2

+3VS

R5 17 1 0K_04 02_5%

1 2

R5 18 10K _0402_5%

CLK _PCI_ SIO

12

R3 94

10_0 402_5%@

1

C5 39
18P _0402_5 0V8J

@

2

3

LPC _LAD0<19, 27,29 ,33>

LPC _LAD1<19 ,27,29 ,33>

LPC _LAD2<19, 27,29 ,33>

LPC _LAD3<19 ,27,29 ,33>

PM _CLK RUN#< 19,29 ,33>

CLK _PCI_ SIO<19>

SI RQ<19 ,29,33>

CLK _14M_SI O<15 >

SIO _GPIO4 1<33>

SIO _GPIO4 3<31>

SIO _GPIO 23<27>

LPC _LAD0
LPC _LAD1
LPC _LAD2
LPC _LAD3

LPC _LFR AME#
LP C_LD RQ#0

SIO _PD#

P M_CLK RUN#
CLK _PCI_ SIO
SI RQ
SIO _PME#

CLK _14M_S IO

SIO _GPI O41
SIO _GPI O42
SIO _GPI O43
SIO _GPI O44
SIO _GPI O45
SIO _GPI O46

SIO _GPI O10
SIO _GPI O11
SIO _GPI O12
S IO_IR Q

SIO _GPI O23

U2 8

9

LAD0

11

LAD1

12

LAD2

13

LAD3

14

LFRAME#

15

LDRQ#

16

PCI_RESET#

17

LPCPD#

18

CLKRUN#

19

PCI_CLK

20

SER_IRQ

6

IO_PME#

8

CLK14

CLO CK

21

GPIO41

22

GPIO42

24

GPIO43

25

GPIO44

26

GPIO45

27

GPIO46

28
29
30
31
32
33
34

57

GPIO

GPIO47
GPIO10
GPIO11/SYSOPT
GPIO12/IO_SMI#
GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO23

POWER

EPAD

LPC 47N21 7N-A BZJ _QFN5 6

Base I/O Address

0 = 02Eh
1 = 04Eh*

RXD1

TXD1
DSR1#
RTS1#
CTS1#
DTR1#

RI1#

DCD1#

SERIAL I/FPARALLEL I/F

LPC I/F

INIT#

SLCTIN#

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

SLCT

BUSY

ACK#

ERROR#

ALF#

STROBE#

VTR
VCC
VCC
VCC
VCC

PE

55
56
1
2
3
4
5

35
36
37
39
40
41
42
43
44
45
47
48
49
50
51
52
53

7
10
23
38
46

TXD1
DS R#1
RTS #1
CTS #1
DT R#1
RI #1
D CD# 1

LPT INIT#
LPT SLCTI N#
LP D0
LP D1
LP D2
LP D3
LP D4
LP D5
LP D6
LP D7
LPTS LCT
LPTPE
LPT BUSY
LPT ACK#
LPT ERR#
LPT AFD#
LPTSTB#

0.1U _0402 _16V4Z

0.1U _0402 _16V4Z

RXD 1

54

1

C7 06

2

RXD1 <31, 32>

R5 16 1K_ 0402_5%

1 2

TXD1 < 31,32>
DS R#1 < 31,32>
RTS# 1 <31 ,32>
CTS# 1 <31 ,32>
DTR #1 <31 ,32>
RI #1 <3 1,32>
DC D#1 < 31,32>

LPT INIT# < 32>
LPT SLCTIN# <32>
LP D0 <32>
LP D1 <32>
LP D2 <32>
LP D3 <32>
LP D4 <32>
LP D5 <32>
LP D6 <32>
LP D7 <32>
LPTSLC T <32>
LPTPE <32>
LPT BUSY <32>
LPTA CK# <32 >
LPT ERR# < 32>
LPT AFD# < 32>
LPTSTB# <32>

1

1

C7 08

C7 07

2

2

0.1U _0402 _16V4Z

+3VS

1

C7 09

4.7U _0805 _10V4Z

2

D CD# 1

RI #1
CTS #1
DS R#1

2

RP 19

1 8
2 7
3 6
4 5

4.7K _120 6_8P4R_ 5%

Parallel Port

+3VS

TO IT8 305

CH75 1H-4 0PT_S OD323-2

LPT ERR#

LPTPE
LPT BUSY
LPT ACK#
LPTS LCT

LP D3
LP D2
LP D1
LP D0

LP D7
LP D6
LP D5
LP D4

LPT SLCTI N#
LPT AFD#
LPT INIT#
LPTSTB#

+5V S_PRN

R3 96

1 2

4.7K _0402_5 %

RP 20

1 8
2 7
3 6
4 5

2.2K _8P4 R_0.05
RP 21

1 8
2 7
3 6
4 5

2.2K _8P4 R_0.05
RP 22

1 8
2 7
3 6
4 5

2.2K _8P4 R_0.05
RP 23

1 8
2 7
3 6
4 5

2.2K _8P4 R_0.05

1

+5VS

21

D3 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/09/15

Compal Secret Data

Deciphered Date

2

Title

Size D ocum ent N umber R ev

Cu sto m

Da te: She et of

Compal Electronics, Inc.

Super I/O LPC47N217

LA -49 61P

1

34 54Th ur sd ay , A ug ust 2 7, 2009

1. 0

+1.8VS

+5VS

1 2

R399 31.6K_0402_1%

1 2

R400 88.7K_0603_1%

R407

16.9K_0402_1%

HP 4/ 6

12

HP 4/ 6

2VREF_51125

4700P_0402_16V7K

12

C542

1 2

R401 10K_0402_5%

1 2

R402 100K_0402_1%

1 2

R404 100K_0402_1%

2VREF_393

1 2

1M_0402_5%

VL

3

+

2

-

1

C541
1000P_0402_50V7K

2

SLP_S3<36>

R397

8

U29A

P

1

O

G

LM393DG_SO8

4

DMN66D0LDW-7_SOT363-6

SLP_S3

+3VS

12

R398
680_0402_5%

1 2

SHORT PADS

J1

Q15B

3

5

4

MINI CARD STANDOFF

H30
HOLEA

1

H31
HOLEA

1

H32
HOLEA

1

PWR _GD <36,43,44,45>

H33
HOLEA

1

MDC STANDOFF

H14
HOLEA

1

H1

H2

HOLEA

HOLEA

1

1

H11

H10

HOLEA

HOLEA

1

1

H3
HOLEA

1

H19
HOLEA

1

H4
HOLEA

1

H20
HOLEA

1

H5
HOLEA

1

H21
HOLEA

1

H15
HOLEA

1

H6
HOLEA

1

H16
HOLEA

1

H7
HOLEA

H17
HOLEA

H18
HOLEA

1

1

H34
HOLEA

1

1

FM3

FM2

FM1

1

1

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

FM4

1

1

H26
HOLEA

1

H28

H27

HOLEA

HOLEA

1

1

CPU screw hole

H29
HOLEA

1

14@

ZZZ 1

PCB-MB

ZZZ 2

15.6@

ZZZ 1

64@

PCB-MB

PCB-MB

ZZZ 2

128@

PCB-MB

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

POK CKT

LA-4961P

35 54Thurs day, August 27 , 2009

1.0

A

B

C

D

E

+5VALW TO +5VS

+5VALW

1 1

1

C554

0.1U_0603_25V7K

2

Q59

8

D

7

D

6

D

5

D

SI4800 BDY_SO8

1

C555

4.7U_0805_10V4Z

2

+1.8V TO +1.8VS

+1.8V

2 2

C562

0.1U_0603_25V7K

8
7

5

1

1

C563

2

2

4.7U_0805_10V4Z

0.01U_0402_25V7K

Q61

IRF811 3PBF_SO8

4

1

C567

2

1.8VS_ENABLE

12

C548

1

S

2

S

3

S

4

G

+1.8VS

1
2
36

1U_0402_6.3V4Z

R419

750K_0402_5%

+5VS

4.7U_0805_10V4Z

1

2

1U_0402_6.3V4Z

RU NON

10U_0805_10V4Z

1

C556

2

13

D

S

1

C549

2

2

C557

1

R418

1 2

330K_0402_5%

SLP_S3

2

G

Q64
2N7002_SOT23-3

1

C550

0.1U_0603_25V7K

2

10/2 2 HP

1

C558

0.1U_0603_25V7K

2

B+

D45

1SS355_SOD323-2

0.1U_0603_25V7K

+3VS+1.8VS

12

0.1U_0603_25V7K

C564

Discharge circuit

SLP_S3

Q14B

5

SLP_S3

+1.8VS

R422
470_0805_5%

1 2

3

DMN66D0LDW-7_SOT363-6

4

+1.5VS

R536

@

470_0805_5%

1 2

13

D

@

Q103

2

G

2N7002_SOT23-3

S

for + 1.5VS disch arge

+5VS

3 3

SLP_S3

4 4

DMN66D0LDW-7_SOT363-6

2

G

SLP_S3

R421
470_0805_5%

1 2

13

D

Q66

2N7002_SOT23-3

S

2

Q15A

+3VS

A

DMN66D0LDW-7_SOT363-6

R429
470_0805_5%

1 2

61

VLDT_EN#

Q14A

2

+1.2V_HT

1 2

61

B

R423
470_0805_5%

+3VALW TO +3VS

+3VALW +3VS

Q58

8

D

7

D

6

D

5

D

SI4800 BDY_SO8

1

2

4.7U_0805_10V4Z

1

2

C552

C551

+1.2VALW TO +1.2V_HT

+1.2VALW +1.2V_HT

Q62

IRF811 3PBF_SO8

8
7

5

1

1

C565

2

2

4.7U_0805_10V4Z

0.01U_0402_16V7K

ADP_PRES< 20,25,31,33,39,46>

DMN66D0LDW-7_SOT363-6

SLP_S5<25,30,31,32>

SLP_S5#<21,42>

2N7002_SOT23-3

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C545

1

S

2

S

3

S

4

G

1

2

0.047U_0402_16V4Z

1
2
36

4

12

R494
470_0402_5%

1

C566

2

Q12A

100K_0402_5%

1

2

1U_04 02_6.3V4Z

C553

HP, 4 /19

C559

1U_0402_6.3V4Z

12

61

2

12

R442

13

D

Q85

2

G

S

C

4.7U_0805_10V4Z

C546

RU NON

4.7U_0805_10V4Z

1

2

R417
820K_0402_5%

HP 5/ 29

2007/08/02 2008/08/02

C560

1

2

D

S

1

2

3

4

1

C547

0.1U_0603_25V7K

2

R415

12

47K_0402_5%

13

Q60

SLP_S3

2

G

2N7002_SOT23-3

1

C561

0.1U_0603_25V7K

2

R416

12

330K_0402_5%

Q12B

DMN66D0LDW-7_SOT363-6

VLDT_EN#

5

SLP_S3<35>

DMN66D0LDW-7_SOT363-6

Compal Secret Data

B+

B+

100K_0402_5%

SLP_S3SLP_S5

Q13A

Deciphered Date

R427

2

VL+3VALW

12

61

VL

12

R428

100K_0402_5%

VLDT_EN#

Q13B

DMN66D0LDW-7_SOT363-6

PWR _GD<35,43,44,45>SLP_S3#<21, 31,33,39>

D

PWR _GD

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

3

5

4

Compal Electronics, Inc.

DC/DC Circuits

LA-4961P

36 54Thursday, August 27, 2009

E

1.0

5

D D

4

3

2

1

LM33 1
Ther mal
Prot ector

AC
Adap ter
in

C C

Page 38

VIN

EN0

SWIT CHADP_ EN#

B+

EN0

TPS5 1125
DC/D C
(3V/ 5V)

51125_PWR

Page 40

2VR EF _511 25

+3VA LWP 3A

+5VA LWP 4.5A

Page 43

B+

B+

BQ24 740
Char ger

Page 39

B+

Page 40

BATS ELB_A

BATS ELB_A#

Batt ery A
6 Ce ll

Batt ery B
8 Ce ll

Batt ery
Sele ctor
Circ uit

B B

VCC VR _ON

ISL6 265
(+CP U_CO RE0/
+CPU _COR E_NB)

TPS5 1117
(1.2 V)

RPGO OD

EN_P SV

TPS5 1117
(1.8 V)

SLP_ S5#

EN_P SV

TPS5 1117
(1.0 ~1.1 V)

PWR_ GD

EN_P SV

Page 42

Page 42

Page 43

PWR _GD+5V ALW

+CPU _CORE0
( 35 A)

+CPU _COR E_NB
( 4A )

Page 45

+1.2 VALW P 8A

+1.8 VP 8A

+NB_ VDDC P 7A

+1.2 VALW

+1.2 VALW

+1.8 VP

PWR_ GD

+1.2 V_HT

PWR_ GD

+3VS

+3VS

TPS5 1100
LDO
(+0. 9V)

Page 44

G299 2
LDO
(+1. 5V)

Page 44

RT90 24
LDO
(+1. 1V)

Page 44

G291 6
LDO
(+2. 5V)

Page 44

+0.9 VP 2A

+1.5 VSP 2A

+1.1 VSP 3A

+2.5 VSP 0.2A

SWIT CH

SWIT CH

BATT

A A

5

SWIT CH

4

Batt ery
Conn ector
A

BATT _A

Batt ery

Page 38 Page 38

Conn ector
B

BATT _B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/09/15 2009/09/15

3

Compal Secret Data

Deciphered Date

Title

Size Do cumen t Numb er R ev

Cu stom

2

Da te: Sheet o f

Compal Electronics, Inc.

POWER BLOCK DIAGRAM

LA-4961P

1

37 54Th ursda y, Augus t 27, 20 09

5

4

3

2

1

PJP1

4

V-

5

V-

6

GND_1

D D

C C

THM _MAIN#<33>

OC P_ADJ<4 6>

B B

PC N1

SUYIN_ 20163 S-06G1 -K

A A

THM_TRA VEL#

7

GND_2

8

GND_3

9

GND_4

FOX _JPD11 31-DB371-7F

PJP2

1

1

2

2

3

3

4

4

5

5

PR2 1M_0402 _1%

6

6

7

7

8

8

SUYIN_ 20004 6MR008 G102ZR

PR4

100K_04 02_5%

BATT+

SMD
SMC

GND

PR9

B/I
TS

PQ30

1

2
3
4
5

6

1K_0402 _5%

+3VL

12

1

2

3

SSM 3K7002FU _SC70-3

210K_04 02_1%

3

ID

1

V+

2

V+

12

12

MMBT3906_SOT23 -3

13

D

2

G

S

220K_04 02_5%

PR9 2

294K_04 02_1%

1 2

PR1 1

1 2

2

BAV 99WT1G_SC7 0-3

PD 26

5

VIN

12

12

1000P _0402_50V7K

PL2

SMB 3025500YA_2 P

1 2

AB1A_DA TA <33>

AB1 A_CLK <33>

+3VL

PR1
@15K_04 02_5%

BATT_A

12

PC6

0.01 U_0402_5 0V4Z

PH1 under CPU botten side :

PQ29

PR9 1

VL+3VL

3

C

1

12

A DPIN

2

3

PD1

1

@PJSOT2 4C_SOT23

69.8 K_0402_1%

1 2

12

PR8 9

100K_04 02_1%

E

B

2

12

PR90

150K_04 02_1%

PR8 8

12

PC 1

12

PR 3

PC 7

1K_04 02_5%

PD1 5

1

BAV99W T1G_SC70-3

2

3

12

PC2
1000P_0 402_50V7K

100 P_0402_50V8J

12

PR 5

100 P_0402_50V8J

VL

PL1

SMB 3025500YA_2 P

1 2

100P_04 02_50V8J

12

12

PC 8

100_0 402_5%

100 P_0402_50V8J

PD1 6

1

BAV99W T1G_SC70-3

2

3

PC3

12

PR 6

100_0 402_5%

PD1 7

1

BAV99W T1G_SC70-3

2

3

12

PC 4

VMB_A

12

PC5
1000P_0 402_50V7K

12

PC9
100P_04 02_50V8J

CPU thermal protection at 90 +-3 degree C
(Need to be checked)

VMB_B

SMB 3025500YA_2 P

PR7

1K_0402 _5%

1 2

12

12

PC 28

PR 14

PC 27

100_0 402_5%

100 P_0402_50V8J

3

1

PD 18

PJS OT24CW_SO T323

100 P_0402_50V8J

1

2

3

PD 20

12

12

PR 15

BAV 99WT1G_SC7 0-3

12

PC2 9
100P_04 02_50V8J

100_0 402_5%

AB1B_DA TA <33>

AB1 B_CLK <33>

1

2

3

2

3

+3VL

PD1 9

1

BAV 99WT1G_SC7 0-3

PD 25

PJSOT24 CW_SOT323

4

1 2

12

PC1 1
1000P_0 402_50V7K

BATT_B

PL3

12

PC1 0

0.01 U_0402_5 0V4Z

1.0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Clos e to CPU

PC1 2

@0.0 22U_0603_2 5V7K

2008/09/15 2009/09/15

3

2RE F_51125

12

12

12

PR16

@51 .1K_0402_1%

2RE F_51125

Compal Secret Data

PH1
@10 0K_0603_1%_ TSM1A104F436 1RZ

PR12

@150K_0 603_1%

1 2

1 2

PR1 3

@75K_04 02_1%

PR17

@150K_0 402_1%

Deciphered Date

12

@470K_0 402_1%

1 2

PU1

1

IN+

VCC+

2

GND

3

IN-

@LM V331IDC KRG4_SC 70-5

12

PC1 3

@1000P_ 0402_50V7K

2

OUT

PR8

VL

PR10
@100K_0 402_5%

VL

5

4

Title

Size Do cumen t Numb er R ev

Cu stom

Da te: Sheet o f

1 2

13

D

PQ1

2

G

@SS M3K7002 FU_SC70-3

S

Compal Electronics, Inc.

DC-IN/ BATTERY CONN

LA-4961P

1

38 54Th ursda y, Augus t 27, 20 09

EN0 <41>

ADP_SIGNAL

5

VI N

PQ101
AO4433L _SO8

1
2
3 6

1 2

PC1 01

D D

0.1U _0603_25V7 K

1 2

PR1 01

200K_04 02_5%

1 2

PR1 36

100K_04 02_1%

PR1 19
200K_04 02_1%

PR123

41.2 K_0402_1%

P2

12

PR1 41

76. 8K_0402_1%

PR1 31
10K _0603_0.1%

2VR EF_51125

P2BATT

PR1 27

C C

P2

12

12

B B

VI N

12

12

A A

8
7

5

4

12

PR1 11
150K_04 02_5%

61

PQ105A
DMN 66D0LD W-7 2 N SOT363-6

2

34

PQ105B
DMN 66D0LD W-7 2 N SOT363-6

5

PR1 35

100K_04 02_1%

1 2

PR1 37

24K_060 3_1%

1 2

PR1 18

1 2

255K_04 02_1%

8

5

P

+

6

-

G

PU1 03B
LM393DG _SO8

4

2VR EF_51125

@76 .8K_0402_1%

3

+

2

-

PQ102
AO4433L _SO8

8
7

5

4

12

13

D

S

VCC1_PWRGD <3 3,41>

VL

ADP _EN <33>

3

2

12

PR1 40

7

O

1 2

604K_04 02_1%

VL

8

P

O

G

PU1 03A
LM393DG _SO8

4

23. 7K_0402_1%

+

-

PR1 25

1

8

P

G

4

PR1 38

1 2

100K_04 02_5%

PR139

1 2

1M_0402 _5%

1

O

PU1 0A
LM393DG _SO8

+3VL

12

PR1 20

4.7K_ 0402_5%

12

PC1 24

0.1U _0402_10V7 K

PR105
15K_040 2_5%

P4

1
2
36

1 2

PR1 03

47K_040 2_5%

2

G

PQ104
SSM 3K7002FU _SC70-3

12

BAT_PW M_OUT<33>

422K_04 02_1%

1U_ 0603_6.3V6M

PC1 25

0.1U _0402_25V6

1 2

AC Detector
High 13.277
Low 10.708

ADP_PRES <20,25,31,33,36,46>

+3VL

PR1 42
22K_040 2_5%

1 2

AC_ADP_PRES < 33>

+3VL

PR1 14

PC116

4

PR1 04

1 2

56K_040 2_1%

SLP_S3#<21,31,33,36>

12

1 2

PC1 11
1U_ 0603_6.3V6M

12

PR1 13
453K_04 02_1%

12

PR1 15
1M_0402 _1%

22.6 K_0402_5%

IADAPT<46>

CH GCTRL

12

PC1 07

0.01 U_0402_16V 7K

PR1 09

0_0402_ 5%

1 2

BQ2 4740VREF

+3VL

VA DJ

PR1 16

100P_04 02_50V8J

PR1 30

1K_0402 _5%

1 2

0.04 7U_0402_16 V7K

Note: X7R type

12

8

IADSLP

9

AGND

10

VREF

11

VDAC

12

VADJ

13

EXTPWR

14

ISYNSET

12

IADAP T

PC1 19

PD1 03

1SS 355_SOD323-2

PC1 23

PC1 28

0.1U _0402_25V6

ACD ET

+3VL

6

7

LPREF

ACSET

IADAPT

SRSET

15

16

12

12

PR1 24
147K_04 02_1%

12

12

3

PR1 02

0.01 _2512_1%

1

2

PC1 05

1U_ 0603_6.3V6M

1 2

12

PC1 08

0.1 U_0603_50V 7K

3

4

5

ACP

LPMD

ACDET

PU1 01
BQ2 4740RH DR_QFN28_ 5X5

SRN

19

18

12

PC1 22
1U_ 0603_6.3V6M

12

12

13

2

G

SRP

PR1 22

210K_04 02_1%

PR1 33
100K_04 02_5%

PR1 34
220K_04 02_5%

CH GEN#

D

PQ109

S

BSS138_ SOT23-3

BAT

17

BATT

PR1 26
470K_04 02_5%

1 2

B+

HCB 2012KF-121 T50_0805

4

3

12

PC106
@0.1 U_0603_25V 7K

CH GEN#

1

2

ACN

CHGEN

PVCC

BTST

HIDRV

REGN

LODRV

PGND

DPMDET

CELLS

21

20

12

2

PL101

1 2

29

TP

28

27

26

25

PH

24

23

22

SRSET <4 6>

CH GCTRL <33>

+3VL+3VL

E

3

B

PQ108
MMBT3906_SOT23 -3

C

1

1 2

47K_040 2_5%

1U_ 0805_25V6K

1 2

BST _CHG

DH _CHG

LX_CHG

RE GN

DL _CHG

PC1 18

12

1U_ 0603_10V6K

PR1 29

12

PC1 02

4.7 U_0805_25V6 M

PC1 09

1 2

PR1 21

0_0402_ 5%

1 2

PR1 28

0_0402_ 5%

ACD ETACD ET

12

PR1 32
300K_04 02_5%

12

PC1 03

PR1 10
10_0805 _5%

1 2

PC1 10

0.1U _0402_10V7 K

12

PD1 02
LL4 148 LL-34

1 2

0.1U _0603_50V7 K

12

PC1 04

4.7 U_0805_25V6 M

1 2

PR1 17
100K_04 02_5%

PC1 20

2

4.7 U_0805_25V6 M

CHG _B+

578

CEL LS <3 3>

12

IADAP T

P4P2

CHG _B+

PQ106
AON 7408L_ DFN8-5

10U _LF919 AS-100M-P3_4.5A_ 20%

3 5

241

PQ107
AO4468L _SO8

3 6

241

12

PC1 21
@0.1 U_0603_25V 7K

PR1 43

11K_040 2_5%

1 2

PC1 27

1U_ 0603_10V6K

PQ103
P1403EV G_SO8

1
2
3 6

4

PR106
0_0402_ 5%

1 2

PL102

1 2

12

12

PR1 44

49.9 K_0402_1%

8
7

5

P2

12

12

PC1 13

PC1 12

PC1 17

4.7 U_0805_25V6 M

4.7 U_0805_25V6 M

0.1U _0402_10V7 K

PU1 04

1

+IN

2

V-

3

-IN

V+

OUT

LMV321AS5X_G_SOT23-5

1 2

PR1 45

39.2 K_0402_1%

1

PR1 12

0.01 _1206_1%

1 2

1 2

5

4

BATT

12

12

12

PC1 15

PC1 14

4.7 U_0805_25V6 M

4.7 U_0805_25V6 M

VL

PMC < 33>

Charge Detector
High 17.614
Low 17.201

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/09/15 2009/09/15

3

Compal Secret Data

Deciphered Date

2

Title

Size Do cumen t Numb er R ev

Da te: Sheet o f

Compal Electronics, Inc.

Charger

LA-4961P

39 54Th ursda y, Augus t 27, 20 09

1

1.0

PC1 26

@4. 7U_0805_25V6 M

5

4

3

2

1

1 2

PR18

5

6

VL

8

P

+

-

G

4

1M_0402_5%

12

PC30

0.1U_0603_50V4Z

7

O

PU10B
LM393DG_SO8

+3VL

12

PR20
100K_0402_5%

BAT_ALARM < 33>

LATCH<33>

BATT_A

BATT_B

PD2
CH715FPT_SC 70

2

3

S

G

2

1

0.1U_0603_50V4Z

D

PQ3
BSS84LT1G_SOT23-3

BATT_IN

13

PD22

1SS355_SOD323-2

12

PC15

2VREF_51125

BATT

12

D D

12

12

PR19

93.1K_0603_1%

PR21
20K_0402_1%

PR94

8.06K_0402_1%

12

PR93

10K_0402_5%

13

D

2

G

PQ31

S

SSM3K7002FU_SC70-3

CFET_B

1 2

12

PD8
RLZ27V

2 1

PR34

0_0402_5%

51125_PWRVin

BATT

C C

12

PR28
470K_0402_5%

1

2

PQ8
PMBT2222A_SOT23-3

1 2

PD5
1SS355_SOD323-2

2

1 2

PD9
1SS355_SOD323-2

3

1

PQ17

3

12

2

G

2

G

PR30

10K_0402_5%

13

2

G

13

D

PQ11
SSM3K7002FU_SC70-3

S

BATT

12

12

PR42

10K_0402_5%

13

2

G

13

D

PQ22

S

SSM3K7002FU_SC70-3

D

PQ10
SSM3K7002FU_SC70-3

S

PR36
470K_0402_5%

D

PQ19

S

SSM3K7002FU_SC70-3

CFET_A<46>

CFET_A

FET_A<33>

B B

FET_B<33>

A A

PR32

10K_0402_5%

1 2

BATT_IN

1 2

PR44

10K_0402_5%

BATT_IN

CFET_B

PR29
470K_0402_5%

1 2

3 6
2
1

PQ12
P1403EVG_SO8

PQ15

AO4433L_SO8

1
2
3 6

PR39

470K_0402_5%

1 2

PMBT2222A_SOT23-3

PD6
SX34H_SMA

4

4

PD7
SX34H_SMA

BATT_IN

21

BATT_A_P

5

7
8

8
7

5

21

BATT_IN

2

G

2

G

5

7
8

PQ13
P1403EVG_SO8

PQ14

AO4433L_SO8

8
7

5

BATT_B_P

2

G

2

G

13

D

PQ7

S

SSM3K7002FU_SC70-3

13

D

PQ9

S

SSM3K7002FU_SC70-3

4

36
2
1

1
2
36

4

13

D

PQ20

S

SSM3K7002FU_SC70-3

13

D

PQ21

S

SSM3K7002FU_SC70-3

12

PR31

4.7K_0402_5%

12

PR33
470K_0402_5%

12

PR35
470K_0402_5%

12

PR41

4.7K_0402_5%

BATT_A

BATT_B

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/09/15 2009/09/15

3

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

Battery selector

LA-4961P

40 54Thursday, August 27, 2009

1

5

4

3

2

1

2VREF_51125

12

PC3 02

1U_ 0603_6.3V6M

D D

51125_P WR

12

PD3 06

3900P _0402_50V7K

12

PR3 11

PC3 12

PR3 19

1 2

@0_040 2_5%

PQ307

1SS 355_SOD323-2

12

PC3 03

4.7 U_0805_25V 6-K

12

12

2

G

100K_04 02_5%

1 2

13

D

G

S

PQ301
AON 7408L_ DFN8-5

3 5

241

5

4

PQ304
AON 7406L_ DFN8-5

123

ENT RIP2

13

D

PQ306
SSM 3K7002FU _SC70-3

S

PR3 16

PR3 17

330K_04 02_5%

2

PD3 03

1SS 355_SOD323-2

PD3 05

1SS 355_SOD323-2

UG1 _3V

12

12

12

10U _0805_6.3V6M

PR3 09

0_0402_ 5%

1 2

VL

B+

PL301

HCB 2012KF-121 T50_0805

1 2

12

C C

4.7U H_PCM C063T- 4R7MN_5.5A_2 0%

B++

12

0.1 U_0603_50V 7K

PC3 17

PC3 01

PL302

+3VALWP

1

PC3 10

150 U_B2_6.3VM

B B

2

VL

12

B+

12

PR3 29
100K_04 02_5%

A A

12

PC3 22

0.1U _0402_25V6

12

PR330

60.4 K_0402_5%

13

D

2

G

S

PQ308
SSM 3K7002FU _SC70-3

+

1000P_0 603_50V7K

D

S

PR3 18
100K_04 02_5%

PR3 28

1 2

0_0402_ 5%

4.7_ 1206_5%

ENT RIP1

PQ305
SSM 3K7002FU _SC70-3

13

2

G

SSM 3K7002FU _SC70-3

+3VALWP

+3VLP

12

PC3 07

1 2

PC3 08

0.1U _0402_10V 7K

B++

KBC_PWR_ON <33>

PR3 31

1 2

100K_04 02_5%

DEBUG_KBCRST <29 >

VCC1_PWRGD <3 3,39>

PR3 07

1 2

0_0402_ 5%

PR3 13

@1M_040 2_1%

1 2

+5VALW P

+3VALW P

620K_04 02_5%

EN0 <38>

Enable +5VALWP when DC mo de for S5 pow er consumptio n

5

4

PR3 01

13.7 K_0402_1%

1 2

PR3 03

20K_040 2_1%

1 2

PR3 05

95.3 K_0402_1%

1 2

BST_3V

UG_ 3V

LX_3V

LG_3V

PR3 15

PJP301

1 2

PA D-OPE N 4x4m
PJP303

1 2

PA D-OPE N 4x4m

2 1

PA D-OPE N 2x2m

2 1

PA D-OPE N 2x2m

2 1

PA D-OPE N 2x2m

25

P PAD

7

VO2

8

VREG3

9

VBST2

10

DRVH2

11

LL2

12

DRVL2

12

2VREF_51125

0.1U _0603_25V7 K

PJP302

PJP305

PJP304

ENT RIP2

5

6

VFB2

ENTRIP2

SKIPSEL

EN0

14

13

51125_P WR

PC3 14

+VREG3_51125+3VLP

+3VL+3VEXTLP

VL+5VLP

4

TONSEL

GND

15

+5VALW

+3VALW

3

VREF

VIN

16

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/09/15 2009/09/15

3

PR3 02

30.9 K_0402_1%

1 2

PR3 04

20K_040 2_1%

1 2

PR3 06

90.9 K_0402_1%

ENT RIP1

1 2

1

2

VFB1

ENTRIP1

24

VO1

23

PGOOD

22

VBST1

21

DRVH1

20

LL1

19

DRVL1

VREG5

VCLK

PU3 01

17

18

TPS 51125RGER_ QFN24_4X4

+5VLP

12

PC3 15
22U _0805_6.3V6M

BST_5V

UG_ 5V

LX_5V

LG_5V

PR3 08

0_0402_ 5%

1 2

+3VL

12

PR3 14
100K_04 02_5%

+5VALWP

(4.5A, 180mil s ,Via NO.= 9)

(3A,12 0mils ,Via NO.= 6)

PR3 20

255K_04 02_1%

12

PC3 21

1U_ 0603_10V6K

Compal Secret Data

Deciphered Date

PC3 09

0.1U _0402_10V7 K

1 2

RPG OOD <42>

P2

12

12

PR3 21

11. 5K_0402_1%

PR3 10

0_0402_ 5%

1 2

AO4712L _SO8

PC3 19

1U_ 0603_10V6K

DEB UG_KBC RST

PU3 02

1

+IN

2

V-

3

-IN

LMV321AS5X_G_SOT23-5

2

OUT

PQ303

12

V+

B++

12

PC3 04

PL303

12

12

PC3 05

3900P _0402_50V7K

4.7 U_0805_25V 6-K

+5VALWP

1

+

PC3 11
150 U_B2_6.3VM

2

3 5

578

3 6

241

241

12

0.1 U_0603_50V 7K

PC3 18

PQ302
AON 7408L_ DFN8-5

4.7U H_PCM C063T- 4R7MN_5.5A_2 0%

1 2

12

PR3 12

4.7_ 1206_5%

12

PC3 13
1000P_0 603_50V7K

+5VLP

PU3 03

1

VIN

12

2

PR3 25

3

220K_ 0402_5%

12

+5VLP

PR3 26

470K_04 02_5%

5

PR3 27

1 2

4

680K_04 02_5%

Title

Size Do cumen t Numb er R ev

Cu stom

Da te: Sheet o f

VOUT

GND

EN

FB

APL5317

PR3 24

16.5 K_0402_1%

12

PD3 04
1SS 355_SOD323-2

Compal Electronics, Inc.

3.3VALWP/5VALWP

5

4

12

LA-4961P

12

PR3 22

64.9 K_0402_1%

12

PR3 23

20K_040 2_1%

1

PC3 06

4.7 U_0805_25V 6-K

+3VEXTLP

12

PC3 20

10U _0805_6.3V6M

41 54Th ursda y, Augus t 27, 20 09

1.0

5

4

3

2

1

PR4 01

D D

RPG OOD<41>

0_0402_ 5%

12

PC4 01

12

@1000P_ 0402_50V7K

12

PR4 02

2.2_ 0402_5%

BST_1.2V

1 2

1

PR4 03
255K_04 02_1%

1 2

1 2

PR4 05 0_040 2_5%

PR4 08

1 2

6.49 K_0402_1%

1 2

PC4 10

@10P_04 02_50V8J

PR410

10K _0603_0.1%

12

PC4 06

+1.2VALW P

+1.2VALW P

12

+5VALW

+5VALW

C C

1 2

PR4 06

316_040 2_1%

1U_ 0603_10V6K

PU4 01

2

TON

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

PR4 31

0_0402_ 5%

1 2

14TP15

VBST

EN_PSV

DRVH

TRIP

V5DRV

DRVL

GND7PGND

TPS 51117R GYR_QFN 14_3.5 x3.5

8

PM_RSMR ST# <21,33>

13

12

LL

11

10

9

UG_ 1.2V

LX_1.2V

PR4 07

1 2

+5VALW

LG_ 1.2V

PC4 05

0.1U _0402_10V7 K

1 2

12.1 K_0402_1%

12

PC4 07

4.7U _0805_10V6 K

PR4 04

0_0402_ 5%

1 2

UG1 _1.2V

5

D8D7D6D

PQ401

S1S2S3G

AO4466L _SO8

4

578

PQ402

3 6

241

FDS 6690AS_G_ SO8

PC4 37

1.2V_B+

12

12

PC4 02

PC4 03

0.1 U_0402_25V 6

0.1 U_0603_50V 7K

2.2U H_PCM C063T-2R2 MN_8A_20%

12

PR4 09

4.7_ 1206_5%

12

PC4 11
1000P_0 603_50V7K

4.7 U_0805_25V6 M

PL402

1 2

+1.2VALW P

PL401

HCB 1608KF-121 T30_0603

1 2

12

PC4 04

4.7 U_0805_25V6 M

12

PR4 34

@1K_040 2_5%

@4.7 U_0805_ 6.3V6K

PJP401

1 2

PA D-OPE N 3x3m

B+

PC4 08

+1.2VALWP

12

+1.2VALW

1

+

PC4 09

2

220 U_D2_4 VY_R25M

(8A,32 0mils ,Via NO.= 16)

PR4 11

SLP_S5#<21,3 6>

0_0402_ 5%

12

PC4 12

12

@1000P_ 0402_50V7K

12

UG_ 1.8V

LX_1.8V

PR4 17

1 2

+5VALW

LG_ 1.8V

PC4 17

0.1U _0402_10V7 K

1 2

11.5 K_0402_1%

12

PC4 19

4.7U _0805_10V6 K

PR4 15

0_0402_ 5%

1 2

UG1 _1.8V

5

D8D7D6D

PQ403

S1S2S3G

AO4466L _SO8

4

578

PQ404

3 6

241

FDS 6690AS_G_ SO8

PC4 13

PR4 12

2.2_ 0402_5%

BST_1.8V

1 2

2

3

4

5

6

PU4 02

TON

VOUT

V5FILT

VFB

PGOOD

1

B B

PC4 18

+1.8VP

+1.8VP

12

@10P_04 02_50V8J

+5VALW

1 2

PR4 16

316_040 2_1%

1U_ 0603_10V6K

PR4 13
255K_04 02_1%

1 2

1 2

PR4 14 0_0402_5%

PR4 18

1 2

14.3 K_0402_1%

1 2

PC4 20

10K _0603_0.1%

PR420

12

14TP15

VBST

EN_PSV

DRVH

TRIP

V5DRV

DRVL

GND7PGND

TPS 51117R GYR_QFN 14_3.5 x3.5

8

13

12

LL

11

10

9

1.8V_B+

12

12

PC4 14

PC4 15

0.1 U_0402_25V 6

0.1 U_0603_50V 7K

2.2U H_PCM C063T-2R2 MN_8A_20%

12

PR4 19

4.7_ 1206_5%

12

PC4 23
1000P_0 603_50V7K

4.7 U_0805_25V6 M

PL404

1 2

@4.7 U_0805 _6.3V6K

PL403

HCB 1608KF-121 T30_0603

1 2

12

PC4 16

4.7 U_0805_25V6 M

12

PC421

+1.8VP

1

+

2

B+

PC4 22
220 U_D2_4 VY_R25M

PJP402

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/09/15 2009/09/15

3

Compal Secret Data

Deciphered Date

+1.8VP

1 2

PA D-OPE N 4x4m

2

+1.8V

(8A,32 0mils ,Via NO.= 16)

Title

Size Do cumen t Numb er R ev

Da te: Sheet o f

Compal Electronics, Inc.

1.2VALWP/1.8VP

LA-4961P

42 54Th ursda y, Augus t 27, 20 09

1

1.0

5

4

3

2

1

VDD C_B+

12

12

PC4 26

PC4 25

0.1 U_0603_50V 7K

2.2U H_PCM C063T-2R2 MN_8A_20%

12

PR4 29

4.7_ 1206_5%

12

PC4 35
1000P_0 603_50V7K

PJP403

1 2

PA D-OPE N 4x4m

0.1 U_0402_25V 6

12

PC4 27

4.7 U_0805_25V6 M

PL406

1 2

4.7U _0805_ 6.3V6K

12

+NB _VDDC P

1 2

PR4 21
150K_04 02_5%

+NB _VDDC P

PC4 24

12

0.01 U_0402_16V 7K

PR4 23
255K_04 02_1%

1 2

PR4 25 0_040 2_5%

PR4 28

10K_040 2_1%

1 2

PR430

23.7 K_0402_1%

1 2

191K_04 02_1%

1 2

12

PR4 33

2

3

4

5

6

PU4 03

TON

VOUT

V5FILT

VFB

PGOOD

1

EN_PSV

GND7PGND

TPS 51117R GYR_QFN 14_3.5 x3.5

8

PR4 32

16.2 K_0402_1%

1 2

12

PC4 36
1500P_0 402_50V7K

BST _VDDC

14TP15

VBST

DRVH

LL

TRIP

V5DRV

DRVL

PC4 32

1 2

4700P_0 402_16V7K

PR4 22

2.2_ 0402_5%

UG _VDD C

LX_ VDDC

PR4 27

1 2

+5VALW

LG _VDDC

0.1U _0402_10V7 K

1 2

13

12

11

10

9

DYN_PWR_EN < 11>

PC4 29

1 2

12.4 K_0402_1%

12

DYN_PWR_EN

0

1

0_0402_ 5%

1 2

PC4 31

4.7U _0805_10V6 K

NB_VDDC

1.1

1.0

PR4 24

UG 1_VDD C

5

4

578

3 6

241

+NB _VDDC P

D8D7D6D

PQ405

S1S2S3G

AO4466L _SO8

PQ406
AO4712L _SO8

PWR_GD<3 5,36, 44,45>

D D

+5VALW

C C

B B

1 2

PR4 26

316_040 2_1%

PC4 30

1U_ 0603_10V6K

PL405

HCB 1608KF-121 T30_0603

1 2

12

PC4 28

4.7 U_0805_25V6 M

+NB_VDDCP

1

12

+

PC4 33

(7A,28 0mils ,Via NO.= 14)

+N B_VDDC

2

B+

PC4 34
220 U_D2_4 VY_R25M

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/09/15 2009/09/15

3

Compal Secret Data

Deciphered Date

Title

Size Do cumen t Numb er R ev

2

Da te: Sheet o f

Compal Electronics, Inc.

NB_VDDC

LA-4961P

43 54Th ursda y, Augus t 27, 20 09

1

1.0

5

4

3

2

1

+5VALW

+1.8V

12

PC6 08

D D

C C

+1.2VALW

12

1U_ 0603_6.3V6M

12

PC6 03

10U _0805_6.3V6 M

@10 U_0805_1 0V4Z

+0.9VP

+0.9VP

PC6 04

12

PC6 09
10U _0805_6.3V6M

PJP601

1 2

PA D-OPE N 3x3m

PU6 01

1

VDDQSNS

2

VLDOIN

3

VTT

4

PGND

5

VTTSNS

11

VTTREF

TP

TPS 51100DGQR_MSO P10

+0.9V

GND

10

VIN

9

S5

8

7

S3

6

(2A,80 mils , Via NO.= 4)

+5VALW

PC6 15

12

1U_ 0603_10V6K

PR6 12

0_0402_ 5%

PW R_GD

1 2

@0.1 U_0402_16V 7K

B B

12

PC6 18

PR6 14

10K_040 2_1%

PC6 22
1000P_0 402_50V7K

12

PU6 03

1

EN

2

GND

FB3PGOOD

RT9024GE_SOT23-6

PR6 18

1 2

2.2_ 0402_5%

1 2

12

PR6 09

3.92 K_0402_1%

VCC

DRI

+1.1VSP

6

5

4

12

PC6 19
1000P_0 402_50V7K

12

PR6 17
@0_040 2_5%

3 5

12

PR607

16K_040 2_5%

12

C

2

B

E

PQ604

3 1

MMBT3904W H_SOT323-3

1 2

PR6 10

0_0402_ 5%

241

12

12

PC6 23

2.2U _0603_ 6.3V6K

+1.2V_HT

12

10U _0805_6.3V6 M

PQ603
SI723 0DN-T 1-GE3_PAK1212-8

PC6 20
10U _0805_6.3V6M

+5VALW

PC6 02
1U_ 0603_10V6K

+1.2VALW

PR6 16

1K_0402 _5%

1 2

+1.8V

+V _DDR_M CH_RE F <8,9 >

12

PC6 13

PC6 14

10U _0805_6.3V6 M

+1.1VSP

12

PC6 21
10U _0805_6.3V6M

PWR_GD<35,36,43,45>

PR6 05

0_0402_ 5%

1 2

@0.1 U_0402_16V 7K

PC6 10

12

+5VALW

2

+1.8VP

12

PC6 05

12

PR606

10K_040 2_5%

61

PQ602A
DMN 66D0LD W-7 2 N SOT363-6

10U _0805_6.3V6 M

5

12

34

+1.5VSP

12

PR6 03

200_040 2_1%

PC6 06

@10 U_0805_1 0V4Z

12

PR6 08
1K_0402 _1%

PQ602 B

DMN 66D0LD W-7 2 N SOT363-6

PJP602

1 2

PA D-OPE N 3x3m

12

PC6 11

2

3

4

12

0.1 U_0402_10V 7K

PU6 02

VIN1VCNTL

GND

VREF

VOUT

G29 92F1U_SO8

+1.5VSP

PC6 12
10U _0805_6.3V6M

+1.5VS

+3VS +2.5VSP

PU6 04
G916T1U F_SOT23-5

1 2

10K_040 2_5%

12

PC6 16
10U _0805_6.3V6M

+2.5VSP

PR6 11

1

IN

SHDN#3SET

PJP604

2 1

PA D-OPE N 2x2m

GND

5

OUT

2

12

PR6 13

4

1K_0402 _1%

12

PR6 15
1K_0402 _1%

+2.5VS

6

5

NC

7

NC

8

NC

9

TP

+5VALW

12

PC6 07
1U_ 0603_10V6K

(2A,80 mils , Via NO.= 4)

12

PC6 17
10U _0805_6.3V6M

(200mA ,10mil s ,Via NO.= 1)

SYS_PWRGD <33,45>

PJP603

+1.1VSP

A A

5

1 2

PA D-OPE N 3x3m

(3A,12 0mils ,Via NO.= 6)

+1.1VS

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/09/15 2009/09/15

3

Compal Secret Data

Deciphered Date

2

Title

Size Do cumen t Numb er R ev

Da te: Sheet o f

Compal Electronics, Inc.

0.9V/1.5VS/1.1VS/2.5VS

LA-4961P

44 54Th ur sd ay, Aug ust 27 , 2 009

1

1.0

5

+CPU_CORE_NB

VDD_N B_FB_H<6>

VDD_N B_FB_L<6>

D D

PR204

22K_0402_1%

1 2

1 2

PC205

1000P_0402_50V7K

C C

SYS_PW RGD<33,44>

SB_PWRGD<6,21,33>

CPU_SVD<6>

CPU_SVC<6>

PWR _GD<35,36,43,44>

PR225

1 2

B B

255_0402_1%

PR229

1 2

54.9K_0402_1%

1 2

1K_0402_1%

PC239
180P_0402_50V8J

PC235

1 2

4700P_0402_25V7K

PR227

PC237

1 2

1200P_0402_50V7K

1 2

+3VS

12

PR213

10K_0402_1%

PR221 0_0402_5%

PR222 0_0402_5%

PR223

1 2

21.5K_0402_1%

CPU_V DD0_FB_H<6>

CPU_B+

+5VS

1 2

1 2

1 2

6.81K_0402_1%

1 2

PC240
1000P_0402_50V7K

PR232

+5VALW

PR207

2_0402_5%

1 2

0.1U_0603_25V7K

1 2

PR210

0_0402_5%

1 2

PR211

@0_0402_5%

1 2

PR212

@10K_0402_5%

PR224

1 2

95.3K_0402_1%

1 2

PR234
0_0402_5%

PR205

2_0402_5%

1 2

0.1U_0402_16V7K

12

PC210

1

2

3

SVD

4

SVC

5

6

7

8

9

10

11

12

PC244
1000P_0402_50V7K

PC206

PU201

OFS/VFIXEN

PGOOD

PWROK

SVD

SVC

ENABLE

RBIAS

OCSET

VDIFF0

FB0

COMP0

VW0

12

12

33P_0402_50V8J

47

48

VIN

VCC

ISN0

ISP0

14

13

ISP 0

+CPU_C ORE_0

4

12

12

PR202

PR203

0_0402_5%

12

12

PC209

PC208

1200P_0402_50V7K

12

PC223

1000P_0402_50V7K

PR208

1 2

44.2K_0402_1%

VSEN_NB

RTN_NB

42

43

44

45

46

FB_NB

ISL6265AIRZ-T_QFN48_ 6X6

VSEN0

15

VSEN0

12

@1000P_0402_50V7K

RTN_NB

FSET_NB

VSEN_NB

COMP_NB

VDIFF1

RTN1

RTN0

VSEN1

19

17

16

18

RTN0

RTN1

PC245

4.7UH _PCMC063T-4R7MN_5.5A_20%

1

12

+

PC202
220U_B_2.5VM_R35M

2

PC201

10U_0805_6.3V6M

0_0402_5%

PR206

15K_0402_1%

LGATE_NB

39

40

PGND_NB

COMP121ISP1

22

PHASE_NB

38

LGATE_NB

PHASE_NB

VW1

23

0.1U_0402_16V7K

UGATE_NB

37

BOOT_NB

UGATE_NB

UGATE0

PHASE0

PHASE1

UGATE1

ISN1

24

12

41

OCSET_NB

FB1

20

PL201

12

PC207

PR209

1_0603_5%

36

35

BOOT0

34

33

32

PGND0

31

LGATE0

30

PVCC

29

LGATE1

28

PGND1

27

26

25

BOOT1

TP

49

+CPU_C ORE_0

ISP 1

12

BOOT_NB1

12

BOOT_NB

UGATE0

PHASE0

LGATE0

LGATE1

PHASE1

UGATE1

BOOT1

BOOT0

PR228

2.2_0603_5%

3

2.2_0603_5%

1 2

1
2
3

PQ201

4

AON74 06L_DFN8-5

LGATE_NB

+5VALW

0.22U_0603_10V7K

PR214

1 2

1 2

0_0603_5%

PR215

PR226

1 2

0_0603_5%

1 2

PC236

0.22U_0603_10V7K

12

PC221

2.2U_0603_6.3V6K

PC224

1 2

1
2

5

3 5

PR201

0_0402_5%

PHASE_NB

12

PR217

4.7_1206_5%

12

PC227
1000P_0603_50V7K

AO4474L_SO8

UGATE0_1

UGATE1_1

4

1 2

UGATE_NB

PQ204

PQ202
AON74 08L_DFN8-5

578

3 6

241

4

123 5

PQ205
TPCA80 28-H_SOP-ADVANCE8-5

578

PQ207
AO4474L_SO8

3 6

241

4

123 5

PQ206
TPCA80 28-H_SOP-ADVANCE8-5

12

2

PC242

PC212

PR216

4.7_1206_5%

PC228

PR230

12

0.1U_0603_50V7K

12

PC213

4.7U_0805_25V6-K

12

12

PC225

12

PC229

4.7U_0805_25V6-K

12

4.7_1206_5%

12

PC238
1000P_0603_50V7K

PC203

4.7U_0805_25V6-K

1000P_0603_50V7K

4.7U_0805_25V6-K

12

PC204

4.7U_0805_25V6-K

3900P_0402_50V7K

CPU_B+

12

12

12

12

PC214

4.7U_0805_25V6-K

PC230

4.7U_0805_25V6-K

PC222

PC215

4.7U_0805_25V6-K

0.36UH_PC MC104T-R36MN1R17_30A_20%

12

PR218

16.5K_0402_1%

ISP 0

12

12

PC231

PC232

4.7U_0805_25V6-K

0.36UH_PC MC104T-R36MN1R17_30A_20%

12

PR231

16.5K_0402_1%

ISP 1

CPU_B+

HCB2012KF-121T50_0805

HCB2012KF-121T50_0805

12

12

PC216

0.1U_0603_50V7K

3900P_0402_50V7K

PL203

PR219

4.02k_0603_1%

1 2

1 2

PC226

0.1U_0603_25V7K

12

12

PC233

0.1U_0603_50V7K

3900P_0402_50V7K

PL204

PR233

4.02k_0603_1%

1 2

1 2

PC241

0.1U_0603_25V7K

1

PL202

12

PL205

12

12

CPU_B+

12

B+

PC220

@47U_25V_M

1

+

2

+CPU_C ORE_0

+CPU_C ORE_0

CPU_V DD0_FB_L<6>

A A

+1.8V

5

1 2

PR237
0_0402_5%

1 2

PR240
1K_0402_5%

12

PC247

@1000P_0402_50V7K

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/09/15

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

CPU_CORE

LA-4961P

45 54Thursday, August 27, 2009

1

1.0

5

BQ2 4740VREF

12

PR5 0
165K_04 02_1%

IADAP T<39 >

D D

CFE T_A<40>

ADP _PRES

2

G

ADP _SIGNA L

1 2

100_040 2_5%

C C

1 2

PR5 1

10K_040 2_1%

1 2

PR9 5

150K_04 02_5%

BSS138_ SOT23-3

13

D

PQ34

S

SSM 3K7002FU _SC70-3

PR5 8

2

PQ33

1 3

D

12

PR6 2

8.06 K_0402_1%

G

S

G

2

13

D

S

PQ32

BSS138_ SOT23-3

OC P_ADJ <38>

NDS 0610_G_SOT 23-3

VI N

12

PR7 5
68K_040 2_1%

1

2

3

12

100K_04 02_1%

PQ24

12

PR7 2

E

3

+3VL

B

2

C

PQ35

1

MMBT3906_SOT23 -3

B B

12

PR6 1

8.66 K_0402_1%

12

PR67

45.3 K_0402_1%

33K_040 2_1%

12

PR79

4.7K_ 0402_1%

2VR EF_51125

12

PR6 9
130K_04 02_1%

12

PR8 2
10K_040 2_1%

1 2

10K_040 2_5%

4

PC2 1

0.22 U_0603_10V 7K

1 2

PU1 2

+IN

V-

-IN

OUT

LMV321AS5X_G_SOT23-5

PR4 9

PD2 1

1SS 355_SOD323-2

D

S

13

G

2

PD2 3

1SS 355_SOD323-2

1 2

1M_0402 _5%

PR8 4

8

5

+

6

-

PR8 5

4

5

V+

4

12

12

LM393DG _SO8

P

7

O

G

PU1 4B

+5VS

12

PC 31

0.0 1U_0402_16 V7K

12

PR5 2
2K_0402 _5%

PD1 1
1SS 355_SOD323-2

1 2

12

1

PR 59

2

3.9 K_0402_5%

+3VL

PC 23

12

3900P _0402_50V7K

PR6 4
100_040 2_5%

OC P_A_IN

AD P_ID_ ADC <33>

12

PR7 0
47K_040 2_1%

1 2

PR6 0

100K_04 02_5%

12

PD2 4

RLZ 4.7B_LL34

ADP _DET# <33>

3

C

PQ26

2

B

MMBT3904W H_SOT323-3

E

3 1

OC P_IN_ ADC <33>

SRSET <3 9>

PR7 1

100K_04 02_5%

OCP< 33>

100K_04 02_5%

+3VL

12

12

PR7 3
100K_04 02_5%

PR6 6

2

PR6 3

@0_040 2_5%

1 2

12

PR6 5

27.4 K_0402_1%

12

12

PC3 2

0.01 U_0402_16 V7K

3

2

2

G

PR6 8

200K_04 02_5%

1 2

VL

8

LM393DG _SO8

P

+

O

-

G

PU1 4A

4

1 2

PR5 7
0_0402_ 5%

13

D

S

PQ25
SSM 3K7002FU _SC70-3

12

PC2 6
10U _0805_10V6K

1

1

H_P ROCHOT # <4 ,6>

+3VL

12

PR7 4
10K_040 2_5%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/09/15 2009/09/15

3

Compal Secret Data

Deciphered Date

Title

Size Do cumen t Numb er R ev

Cu stom

2

Da te: Sheet o f

Compal Electronics, Inc.

ADP_OCP

LA-4961P

46 54Th ursda y, Augus t 27, 20 09

1

5

Versi on chan ge list (P.I.R. List) Power section Page 1 of 1

4

3

2

1

Item Reaso n for c hange PG# Modify Lis tDate P hase

2008 /12/ 11 DB1-- >DB2

1

2

2009 /01/ 16 DB2-- >SI1 Im pro ve D DR t erm inat ion pow er rail efficiency 44 Change DD R te rmi nati on s olu tion from G2992 to TPS51100

3

2009 /01/ 22 DB2-- >SI1 Mo dif y th e ch arg er funtion 39 M odi fy t he w atc h-dog c ircuit

4

2009 /02/ 03 DB2-- >SI1 Mo dif y th e Vi n/C harge detector 39 F ine tun e th e t rigger point

5

D D

2009 /02/ 03 DB2-- >SI1 Mo dif y th e wa tch -dog s equence 39 Ch ang e PR 133 .1 a nd P Q108.3 to +3VL

6

2009 /02/ 03 DB2-- >SI1 Fi ne tune Pow er monit or settin g 39 Ch ang e PR 143 fro m 100 to 11K

7

2009 /02/ 10 DB2-- >SI1 Ad dit iona l +3 VL for KBC ADC accur acy 41 Add ext erna l +3V L LDO

8

2009 /02/ 18 DB2-- >SI1 44 Add +V _DD R_MC H_REF n etAdd +V_D DR_ MCH_R EF net

9

2009 /02/ 19 DB2-- >SI1 39

10

2009 /02/ 19 DB2-- >SI1 Ad jus t NB _VDD C b etwe en 0 .95V and 1.1V

11

2009 /02/ 20 DB2-- >SI1 Fo r E MI r equest 41453V/5 V

12

2009 /04/ 07 SI1-- >SI2 Fo r H P's reques t,

14

2009 /04/ 09 SI1-- >SI2 To im prov e th e p ower eff ici ency when S5 under DC mode,

15

C C

2009 /04/ 14 SI1-- >SI2 En abl e +5 VALW P w hen DC m ode 4 1 A dd P R318 as 100 K w hich is the pul l high of PQ305.3 to VL

16

2009 /04/ 16 SI1-- >SI2 Fo r E MI r equest 41 C han ge P D18 and PD1 9 fr om BAV99 to PJSOT24CW

17

2009 /04/ 24 SI1-- >SI2 Fi ne tune NB_ VDD C po wer o n sequence 4 3 C hang e P R421 fro m 10K to 150K

18

2009 /04/ 24 SI1-- >SI2 Tr ave l ba tter y c an n ot b e dete cted issue 38 Ch ange PR9 fr om 1 00K to 21 0K

19

2009 /04/ 24 SI1-- >SI2 Fo r R F re quest 4243Add PC41 3,P C425 and PC437 as 0.1u

20

2009 /05/ 25 SI2-- >PV For S5 powe r c onsump tion,

21

2009 /05/ 25 SI2-- >PV

22

2009 /05/ 29 SI2-- >PV23For HP r equest 42 Add a ser ial res isto r ( 0ohm ins tal l) bet ween pin 6 of PU401

2009 /05/ 29 Chan ge P R62 to 8 .06K_1%

24

2009 /05/ 30 SI2-- >PV

25

2009 /06/ 05 SI2-- >PV26Enab le + 5VA LW a t S5 wh en batte ry mode 41 Un inst all PR319

B B

2009 /06/ 06 SI2-- >PV For EMI req ues t (h ad been imp lemented a t SI2) 4243Chan ge P R40 2,PR 412 from 0 to 2.2

27

2009 /06/ 06 SI2-- >PV Fin e tu ne p owe r se que nce for N B_VDDC

28

2009 /06/ 06 SI2-- >PV 38 C han ge P R9 f rom 100K t o 210KEnsu re t he T HM_ MAIN # le vel l ower enou gh

29

2009 /06/ 09 SI2-- >PV 44 C han ge P Q604 fr om 2 N700 2 to MMBT3 904

30

2009 /06/ 09 SI2-- >PV Add PQ20 , P Q25 and PQ26 a s BAV99For ESD reque st 3 8

31

2009 /06/ 26 SI2-- >PV

32

2009 /06/ 26

33

2009 /06/ 26 SI2-- >PV

34

2009 /07/ 04 SI2-- >PV

35

A A

2009 /07/ 07 PV--> PV-R Re ser ve a dum my load to pre vent the leakage issue in the

36

2009 /07/ 07

37

2009 /07/ 07 Chan ge P C30 2 fr om 0 .22u to 1 uPV-- >PV-R T I re que st t o p reve nt LDO is sue 41

38

2009 /07/ 15 PV--> PV-R TI re ques t to pr event LDO issu e

39

5

BATC ON c irc uit is r emo ved due to SMS c 1098 des ign. 40 Delet e P D10, PR4 5 and PU 9

Modi fy c irc uit for Debug bo ard 4 0 Cha nge PR3 4 f rom 100 ohm to 0 o hm2009 /01/ 16 DB2-- >SI1

Chan ge P R14 5 fr om 3 3K to 39 .2K

For EMI reque st Add PC12 5 a nd P C128 as 0.1u

(ins tead of 1.0 V and 1.1V).

add a di ode whi ch c onn ects th e B++ and 51125_PWR

Re-c onne ct the EN s ign al ( ENT RIP1 /2) to 2 singal N-MOSFET

rese rve add itio nal cir cuit to ena ble +5VALWP at battery mode

For AirL ine ada pter de tection i ssue 39 Un-in stal l PR127

Fine tun e O CP set ting 46 C han ge P R49 to 100K

(had bee n i mpel emen ted at S I2)

when mai n b atte ry b e i nser ted (ha d be en impel emented at SI2)

For HP r equest

(MEM O)

SI2- ->PV

For HP's requ est 44 C han ge P R616 fr om 10K to 1K

(MEM O)

Fine tun e V sens e fe edb ack to prev net feedbac k saturat ion issue 4 5 Cha nge PR2 18 and PR23 1 f rom 3.6 5K to 16. 5K

(MEM O)

Fine tun e e nabl e si gna l le vel to make sure the switc h

(MEM O)

can work no rmally

futu re. Tha t is sue has hap pen ed on PUM A platfor m

PV-- >PV-R A dd a pu ll d own res isto r t o pr even t the floating o f PQ307 Ad d PR 331 as 1K41

(Cap acit anc e on VRE G5 shou ld be 33u at le ast)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

43 C han ge P R430 to 23. 7K_0 402 _1% and PR433 to 191K_0402 _1%

PR31 1/PC 312 :4.7 ohm/ 10 00pF
PC31 7/PC 301 :0.1 uF/ 390 0pF
PR31 2/PC 313 :4.7 ohm/ 10 00pF
PC31 8/PC 304 :0.1 uF/ 390 0pF
CPU CORE
PR21 7/PC 227 :4.7 ohm/ 10 00pF
PC24 2/PC 203 :0.1 uF/ 390 0pF
PR21 6/PC 225 :4.7 ohm/ 10 00pF
PC21 6/PC 222 :0.1 uF/ 390 0pF
PR23 0/PC 238 :4.7 ohm/ 10 00pF
PC23 3/PC 232 :0.1 uF/ 390 0pF

41 A dd PD30 6 as 1SS355

41 C han ge P Q305 fr om 2 N700 2KD W-2N _SOT 363 to SSM3K7002 FU_SC70

Add PQ30 6 a s SS M3K7 002FU_SC 70-3

Conn ect PQ3 05.3 to DEBUG_KB CRST

Dele te P D20

Chan ge P C42 4 fr om 1 000P t o 0.01u

Add PR40 9,P R419 and PR 429 as 4. 7 ohm
Add PC41 1,P C423 and PC 435 as 10 00pF

41 A dd PR31 9 as 0

PQ30 8 a s SS M3K7220FU
PR32 9 a s 100K
PR33 0 as 15K
PC32 2 a s 0.01u
Ress erve PR328

Add PR14 1 a s 78 .6K bet ween Vin and PU103.3
Chan ge n et name AC_ AND _CHG to AC_ADP _PRES

and sign al PM_RS MRST#.

46Beca use tab le o f AC ad apte rs has been e xpanded.SI2- ->PV

P R61 to 8 .66K_1%
P R67 to 4 5.3K_1%

Add PR32 8 as 0

Add PR40 9,P R419 as 4.7
PC41 1,P C423 as 1000p
PC41 3,P C437 as 0 .1u_0603
PC40 2,P C414 as 0 .1u_0402
Chan ge P R42 2 fr om 0 to 2.2
Add PR42 9 as 4.7
PC43 5 a s 1000p
PC42 5 a s 0.1 u_0603
PC42 6 a s 0.1 u_0402

43 C han ge P R421 fr om 10 K to 150K

P C42 4 fr om 1 000p t o 0.01u

Add PR61 6 as 10K

Chan ge P R33 0 fr om 15 K to 20KFor HP's requ est 41

P R22 3 fr om 1 00K to 2 1.5K
P R22 4 fr om 1 7.4K t o 95.3K
P R20 6 fr om 14 K to 15K
Add PR21 9 a nd P R233 as 4.02K

41 C han ge P R330 fr om 2 0K to 60. 4K

P C32 2 fr om 0 .01u to 0.1u

42 R ese rve PR43 4 as 1K

Chan ge P C31 5 fr om 10 u to 22u

41

P C26 fro m 1u to 10u

Compal Secret Data

2008/09/15 2009/09/15

3

Deciphered Date

Compal Electronics, Inc.

Title

Changed-L ist History

Size Docume nt Numb er Rev

LA- 496 1P

2

Date: She et of

47 54Th ursda y, Augu st 27 , 200 9

1

1.0

5

Version Change List

Version Change List ( P. I. R. List ) for HW Circuit

Version Change ListVersion Change List

Item

Item Issue D

Pa ge#

ItemItem

D D

C C

B B

A A

ge#

PaPa

ge#ge#

33

33

333 3

1111

29

29 LPC

292 9

2222

29

29 VGA

292 9

3333

30,

30, 3 1

31 USB

30,3 0,

4444
5555
6666

7777
8888
9999

10

10

1010
11

11

1111
12

12

1212
13

13

1313
14

14

1414
15

15

1515
16

16

1616
17

17

1717
18

18

1818
19

19

1919

20

20

2020
21

21

2121
22

22

2222
23

23

2323
24

24

2424

26

26

2626
27

27 26

2727
28

2828
29

29

2929
30

30

303 0
31

31

313 1
32

32

323 2

3131

4444 The

29

29 LPC

292 9

27

27 USB (WLAN conn)

272 7
27

27 WWWWWAN

272 7
32

32 VGA

323 2
11

11 N B

111 1
32

32 DO

323 2
18

18 DP

181 8
17

17 LCD

171 7
32

32 DO

323 2
25

25 NNNNIC

252 5
32

32 DO

323 2
34

34 Super IO

343 4
15

15 CL

151 5
9999 DDR

30

30 USB

303 0
25

25 NNNNIC

252 5
25

25 NNNNIC

252 5
27

27 WWAM

272 7
15

15 CL

151 5

4444 CCCCPU

26

2626

4444 FFFF A N
33

33 KKKKBC

333 3
31

31 KKKKBC

313 1
18

18 Display

181 8
6666 Lea

TTTTitle

itle

itleitle

KBC 1

KBC 1 098

KBC 1KBC 1

LPC Debug port

Debug port

LPCLPC

Debug port Debug port

VGA

VGAVGA

USB

USBUSB
The rmal senseor

rmal senseor

TheThe

rmal senseorrmal senseor

LPC Debug port

Debug port

LPCLPC

Debug port Debug port

USB (WLAN conn)

USB (WLAN conn) USB (WLAN conn)

WAN

WANWAN

VGA

VGAVGA
NB

NBNB
DO CK

CK

DODO

CKCK

DP

DPD P
LCD

LCDLCD
DO CK

CK

DODO

CKCK

IC

ICIC

DO CK

CK

DODO

CKCK

Super IO

Super IOSuper IO
CL K gen

K gen

CLCL

K genK gen

DDR II

II

DDRDDR

IIII

USB

USBUSB

IC

ICIC
IC

ICIC

WWAM

WWAMWWAM
CL K gen

K gen

CLCL

K genK gen

PU

PUPU

WWAM

WWAM

WWAMWWAM

AN

ANAN

BC

BCBC
BC

BCBC

Display Port

Display Display

Lea kage

kage

LeaLea

kagekage

098

098098

Port

PortPort

( P. I. R. List ) for HW Circuit

( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit

Req

Req uest

uest

ReqReq

Date

DateDate

11

11 /28

/28

1111

/28/28

11

11 /28

/28 HP BI

1111

/28/28

11

11 /28

/28 HHHHP

1111

/28/28

12

12 /1

/1 CCCCompal

1212

/1/1

12

12 /1

/1 CCCCompal

1212

/1/1

12

12 /2

/2 HP BI

1212

/2/2

12

12 /2

/2 HP

1212

/2/2

12

12 /2

/2 HP

1212

/2/2

12

12 /2

/2 HP

1212

/2/2

12

12 /2

/2 HP

1212

/2/2

12

12 /2

/2 HP

1212

/2/2

12

12 /2

/2 HP

1212

/2/2

12

12 /3

/3 CCCCompal

1212

/3/3

12

12 /3

/3 HP

1212

/3/3

12

12 /3

/3 HP

1212

/3/3

12

12 /3

/3 HP

1212

/3/3

12

12 /4

/4 CCCCompal

1212

/4/4

12

12 /4

/4 CCCCompal

1212

/4/4

12

12 /5

/5 CCCCompal

1212

/5/5

12

12 /5

/5 HP

1212

/5/5

12

12 /5

/5

1212

/5/5

12

12 /5

/5 HP

1212

/5/5

12

12 /5

/5 HP

1212

/5/5

12

12 /8

/8 HP

1212

/8/8

12

12 /8

/8 HP

1212

/8/8

12

12 /9

/9 HP

1212

/9/9

12 /10

/1028

1212

/10/10

12

12 /10

/10 CCCCompal

1212

/10/10

12

12 /12

/12 HP

1212

/12/12

12

12 /15

/15 HP

1212

/15/15

12

12 /18

/18 HP

1212

/18/18

uestuest

Own

Own er

er

OwnOwn

erer

HP BI

HP BIOS

HP BIHP BI

HP BIOS

HP BIHP BI

P

P P

ompal

ompalompal
ompal

ompalompal

HP BIOS

HP BIHP BI

HP

HPHP
HP

HPHP
HP

HPHP
HP

HPHP
HP

HPHP
HP

HPHP

ompal

ompalompal

HP

HPHP
HP

HPHP
HP

HPHP

ompal

ompalompal
ompal

ompalompal
ompal

ompalompal

HP

HPHP

HP

HP

HPHP
HP

HPHP
HP

HPHP
HP

HPHP

HP

HPHP
HP

HPHP
HP

HP12

HPHP

ompal

ompalompal

HP

HPHP
HP

HPHP
HP

HPHP

4

Issue Description

Issue DIssue D

HP BIOS team design chan

HP BIOS team design change

HP BIOS team design chanHP BIOS team design chan

OS

OSOS

LPC

LPC debug card can't work

LPCLPC

OS

OSOS

De

De sign change for RS880M VGA I2C DDC

DeDe
all

all USB board can't work

all all
System c

System can't power on

System cSystem c

LPC

LPC debug card can't work

LPCLPC

OS

OSOS

AMD platfor

AMD platform is not support WiMAX

AMD platforAM D platfor
HP

HP Comm team design change

HPHP
VGA ca

VGA ca n't work issue

VGA caVGA ca
HP d

HP d esign change

HP dHP d
HP d

HP d esign change

HP dHP d
HP d

HP d esign change

HP dHP d
Compa

Compa l ME design change

CompaCompa
HP d

HP d esign change

HP dHP d
V1 .2_

V1 .2_ LAN leakage issue

V1 .2_V1.2_

all the FETs c

all the FETs c icuit will be located inside docking station

all the FETs call the FETs c

Compal

Compal design change

CompalCompal
Compal

Compal design change

CompalCompal
la yout

la yout placement issue

la yout layout

re-

re- define the USB debug port (USB port 0)

re-re­V1 .2_LAN l

V1 .2_LAN leakage issue & improve layout

V1 .2_LAN lV1.2_LAN l
HP recom

HP recommand that 8075 is not needed

HP recomHP recom
HP d

HP d esign change

HP dHP d
Adding clk requ

Adding clk requ est signal for media/1394 daughter

Adding clk requAdding clk requ
board for

board for power saving benefit

board forboard for
AMD

AMD S1G3 request for +1.2V_HT power rail

AMD AMD
HP d

HP d esign change

HP dHP d
HP design change for RF

HPHP
de

de sign change to meet SMSC guideline

de de

HP d

HP d esign change

HP dHP d

add leve

add leve l shit control for DP

add leveadd leve
lllleakage fro +1.8VS

eakage fro +1.8VS cccchange power rail from +1.8VS to +1.8V

eakage fro +1.8VSeakage fro +1.8VS

escriptionDate

escriptionescription

ge remove AD

gege

debug card can't work ch ange JP21

debug card can't work debug card can't work

sign change for RS880M VGA I2C DDC del

sign change for RS880M VGA I2C DDCsign change for RS880M VGA I2C DDC

USB board can't work change

USB board can't work USB board can't work

an't power on thermal sens

an't power onan't power on

debug card can't work ch an

debug card can't work debug card can't work

m is not support WiMAX remove USB20

m is not support WiMAXm is not support WiMAX

Comm team design change reserve R5

Comm team design change Comm team design change

n't work issue ch ange

n't work issuen't work issue

esign change change R61 fro

esign changeesign change
esign change re

esign changeesign change
esign change remo

esign changeesign change

l ME design change ch an

l ME design changel ME design change

esign change re move SER_SHD

esign changeesign change

LAN leakage issue ch

LAN leakage issueLAN leakage issue

icuit will be located inside docking station All the

icuit will be located inside docking stationicuit will be located inside docking station

design change Change Sup

design change design change
design change add CLK_14M_SIO for Super IO & delete CLK_48M_SIO

design change design change

placement issue cgange rsisto

placement issueplacement issue

define the USB debug port (USB port 0)

define the USB debug port (USB port 0)define the USB debug port (USB port 0)

eakage issue & improve layout Swap p

eakage issue & improve layouteakage issue & improve layout

mand that 8075 is not needed remove R246,R240

mand that 8075 is not neededmand that 8075 is not needed

esign change add W

esign changeesign change

est signal for media/1394 daughter

est signal for media/1394 daughter est signal for media/1394 daughter

power saving benefit

power saving benefit power saving benefit

S1G3 request for +1.2V_HT power rail C1

S1G3 request for +1.2V_HT power railS1G3 request for +1.2V_HT power rail

esign change change

esign changeesign change

design change for RF

design change for RF design change for RF

sign change to meet SMSC guideline add C7

sign change to meet SMSC guidelinesign change to meet SMSC guideline

esign change ch ange BA

esign changeesign change

l shit control for DP add Q1

l shit control for DPl shit control for DP

3

So

So lution Description

lution Description

SoSo

lution Descriptionlution Description

remove ADP_DET# signal connection from pin 80 of KBC

remove ADremove AD
to

to pin 87 (GPIO9)

pin 87 (GPIO9)

to to

pin 87 (GPIO9) pin 87 (GPIO9)

ch ange JP21 .16 conection from DEBUG_KBCRST to "51125_PWR"

ch ange JP21change JP21

de l ete R101, R102, Q18,Q19

ete R101, R102, Q18,Q19 0.2

de ldel

ete R101, R102, Q18,Q19ete R101, R102, Q18,Q19

ch ange USB PWR switch enable signal from SLP_S5# to SLP_S5

ch ange change
thermal sens or change from ADM1032 to EMC1402

thermal sensthermal se ns
ch an ge JP21.12 conection from "B+" to "51125_PWR" & change

ge JP21.12 conection from "B+" to "51125_PWR" & change

ch anch an

ge JP21.12 conection from "B+" to "51125_PWR" & change ge JP21.12 conection from "B+" to "51125_PWR" & change

JP21.16 conection from "DEBUG_KBCRST" to "VCC1_PWRG

JP21.16 conection from "DEBUG_KBCRST" to "VCC1_PWRGD"

JP21.16 conection from "DEBUG_KBCRST" to "VCC1_PWRGJP21.16 conection from "DEBUG_KBCRST" to "VCC1_PWRG
remove USB20 _N9\P9 from WLAN connector (JP9)

remove USB20remove USB20
reserve R513 for LAN_PCIE_WAKE# of JP10 pin1

reserve R5reserve R5

ch ange DOCK_ID signal pullup power rail to +5VS

ch ange change

ch ange R61 fro m 10Kohm to 0 ohm

ch ange R61 frochange R61 fro
re move Q23, Q5, Q6, R457~R460,R483,C682,C683

move Q23, Q5, Q6, R457~R460,R483,C682,C683 0.2

rere

move Q23, Q5, Q6, R457~R460,R483,C682,C683move Q23, Q5, Q6, R457~R460,R483,C682,C683

remo ve C253, R467. add R514, Q98

ve C253, R467. add R514, Q98 0.2

remoremo

ve C253, R467. add R514, Q98ve C253, R467. add R514, Q98

ch an ge the LCD connector type

ch anch an
remove SER_SHD signal & pin76 pullup 10k ohm to +5VS

remove SER_SHDremove SER_SHD
ch ange power rail friom +1.2V_HT to +1.2VALW

ange power rail friom +1.2V_HT to +1.2VALW 0. 2

chch

ange power rail friom +1.2V_HT to +1.2VALWange power rail friom +1.2V_HT to +1.2VALW

All the CEC and CAD pins (143,46,142 and 47) will left as NC

All theAll the
Change Sup er IO IT8305E to LPC47N217

Change SupChange Sup

add CLK_14M_SIO for Super IO & delete CLK_48M_SIO 0. 2

add CLK_14M_SIO for Super IO & delete CLK_48M_SIOadd CLK_14M_SIO for Super IO & delete CLK_48M_SIO

cgange rsi sto r size from 8P4R to 0402

cgange rsi stocgange rsisto
Swap JUSB1

Swap JUSB1 & JUSB2's USB signal

Swap JUSB1 Swap JUSB1

Swap power rail +1.2V_HT & V1.2_LAN

Swap pSwap p

remove R246,R240 ,R241,R247,R244,R238,C421,U14 & USB signal

remove R246,R240remove R246,R240

add W WAM wakeup circuit

add Wadd W

cccchange CLK_PCIE_CARD#/CLK_PCIE_CARD from pin25,26

hange CLK_PCIE_CARD#/CLK_PCIE_CARD from pin25,26

hange CLK_PCIE_CARD#/CLK_PCIE_CARD from pin25,26hange CLK_PCIE_CARD#/CLK_PCIE_CARD from pin25,26

to pin 22

to pin 22,23 & rename pin24 to CRD_REQ# & connect to JP29 pin20

to pin 22 to pin 22

C1 ,C2,C7 change from 4.7U to 10U

,C2,C7 change from 4.7U to 10U 0.2

C1C1

,C2,C7 change from 4.7U to 10U ,C2,C7 change from 4.7U to 10U

ch ange R279 pin1 power rail from +3VALW to +3VS

ch angechange
add R5

add R5 34

add R5add R5
add C7 10

add C7add C7
ch ange BATCON to ADP_DET# and connection Pin87 & pin92

ch ange BAch ange BA
add Q1 02, R535

add Q1add Q1

hange power rail from +1.8VS to +1.8V 0.2

hange power rail from +1.8VS to +1.8Vhange power rail from +1.8VS to +1.8V

P_DET# signal connection from pin 80 of KBC

P_DET# signal connection from pin 80 of KBCP_DET# signal connection from pin 80 of KBC

.16 conection from DEBUG_KBCRST to "51125_PWR" 0.2

.16 conection from DEBUG_KBCRST to "51125_PWR".16 conection from DEBUG_KBCRST to "51125_PWR"

USB PWR switch enable signal from SLP_S5# to SLP_S5 0. 2

USB PWR switch enable signal from SLP_S5# to SLP_S5USB PWR switch enable signal from SLP_S5# to SLP_S5

or change from ADM1032 to EMC1402 0.2

or change from ADM1032 to EMC1402 or change from ADM1032 to EMC1402

13 for LAN_PCIE_WAKE# of JP10 pin1 0.2

13 for LAN_PCIE_WAKE# of JP10 pin113 for LAN_PCIE_WAKE# of JP10 pin1

DOCK_ID signal pullup power rail to +5VS 0 .2

DOCK_ID signal pullup power rail to +5VSDOCK_ID signal pullup power rail to +5VS

ge the LCD connector type 0.2

ge the LCD connector typege the LCD connector type

CEC and CAD pins (143,46,142 and 47) will left as NC 0.2

CEC and CAD pins (143,46,142 and 47) will left as NC CEC and CAD pins (143,46,142 and 47) will left as NC

er IO IT8305E to LPC47N217 0.2

er IO IT8305E to LPC47N217er IO IT8305E to LPC47N217

ower rail +1.2V_HT & V1.2_LAN

ower rail +1.2V_HT & V1.2_LANower rail +1.2V_HT & V1.2_LAN

WAM wakeup circuit 0.2

WAM wakeup circuitWAM wakeup circuit

,23 & rename pin24 to CRD_REQ# & connect to JP29 pin20

,23 & rename pin24 to CRD_REQ# & connect to JP29 pin20,23 & rename pin24 to CRD_REQ# & connect to JP29 pin20

R279 pin1 power rail from +3VALW to +3VS 0.2

R279 pin1 power rail from +3VALW to +3VS R279 pin1 power rail from +3VALW to +3VS

34 0.2

3434

10 0.2

1010

TCON to ADP_DET# and connection Pin87 & pin92 0.2

TCON to ADP_DET# and connection Pin87 & pin92TCON to ADP_DET# and connection Pin87 & pin92

02, R535 0.2

02, R53502, R535

2

_N9\P9 from WLAN connector (JP9) 0.2

_N9\P9 from WLAN connector (JP9)_N9\P9 from WLAN connector (JP9)

m 10Kohm to 0 ohm 0.2

m 10Kohm to 0 ohmm 10Kohm to 0 ohm

signal & pin76 pullup 10k ohm to +5VS 0.2

signal & pin76 pullup 10k ohm to +5VS signal & pin76 pullup 10k ohm to +5VS

r size from 8P4R to 0402 0.2

r size from 8P4R to 0402r size from 8P4R to 0402

& JUSB2's USB signal 0.2

& JUSB2's USB signal & JUSB2's USB signal

,R241,R247,R244,R238,C421,U14 & USB signal

,R241,R247,R244,R238,C421,U14 & USB signal,R241,R247,R244,R238,C421,U14 & USB signal

1

Rev.

Rev.Pa

Rev.Rev.

0.2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.2

D"

D"D"

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.2

0.20 .2

0.2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

0.2HP

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

0.2

0.20 .2

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/02 2009/09/15

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

HW Changed-List History-1

LA-4961P

1

48 54Thurs day, August 27 , 2009

1.0

5

Version Change List

Version Change List ( P. I. R. List ) for HW Circuit

Version Change ListVersion Change List

Item

Item Issue D

Pa ge#

ItemItem

D D

C C

B B

A A

ge#

PaPa

ge#ge#

28

28

282 8

1111

26

26 LLLL A N

262 6

2222

32

32 Do

323 2

3333

32

32 Do

323 2

4444

32

32 Do

323 2

5555

32

32 Do

323 2

6666

32

32 Do

323 2

7777

25

25 NNNNIC

252 5

8888

31

31 WLAN_LED

313 1

9999

28

28 MMMMDC

282 8

10

10

101 0

21

21 PWR on CKT

212 1

11

11

111 1

29,

29, 3 3

33 KKKKBC

29,2 9,

12

12

121 2
13

13

131 3
14

14

141 4
15

15

151 5
16

16

161 6
17

17

171 7

18

18

181 8

19

19

191 9

20

20

202 0

21

21

212 1
22

22

222 2

23

23

232 3
24

24

242 4
26

26

262 6

3333

32

32 Do

323 2
32

32 Do

323 2
31

31 card rea

313 1
32

32 Do

323 2
32

32 Do

323 2

23

23 SB

20

232 3

202 0

17

17 LCD Pane

171 7
17

17 card rea

171 7

11

11 18

18 DP

111 1

181 8

32

32 Do

323 2

30

30 USB

303 0
19

19 RRRRTC

191 9
19

19 SB

191 9

TTTTitle

itle

itleitle

KB

KB connector

connector

KBKB

connector connector

AN

ANAN

Docking

ck ing

DoDo

ck ingcking

Docking

ck ing

DoDo

ck ingcking

Docking

ck ing

DoDo

ck ingcking

Docking

ck ing

DoDo

ck ingcking

Docking

ck ing

DoDo

ck ingcking

IC

ICIC

WLAN_LED

WLAN_LEDWLAN_LED

DC

DCDC

PWR on CKT

PWR on CKTPWR on CKT

BC

BCBC

Docking

ck ing

DoDo

ck ingcking

Docking

ck ing

DoDo

ck ingcking

card reader

card reacard rea
Docking

DoDo
Docking

DoDo

SB710

SBSB

LCD Pane l

LCD PaneLCD Pane
card reader

card reacard rea

DP

DPD P
Docking

DoDo

USB

USBUSB

ck ing

ck ingcking
ck ing

ck ingcking

71 0

71 0710

ck ing

ck ingcking

TC

TCTC

SB710

71 0

SBSB

71 0710

5

der

derder

der

der der

l

l l

( P. I. R. List ) for HW Circuit

( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit

Req

Req uest

uest

ReqReq

Date

DateDate

12

12 /24

/24

1212

/24/24

12

12 /31

/31 CCCCompal

1212

/31/31

1/

1/ 15

15 HP

1/1/

1515

1/

1/ 15

15 HP

1/1/

1515

1/

1/ 15

15 HP

1/1/

1515

1/

1/ 15

15 HP

1/1/

1515

1/

1/ 15

15 HP

1/1/

1515

1/

1/ 15

15 HP

1/1/

1515

1/

1/ 15

15 CCCCompal

1/1/

1515

1/

1/ 22

22 HP

1/1/

2222

2/3

2/3 CCCCompal

2/32/3
2/3

2/3 HP

2/32/3
2/3

2/3 HP

2/32/3
2/3

2/3 HP

2/32/3
2/3

2/3 HP

2/32/3
2/4

2/4 HP

2/42/4
2/4

2/4 HP

2/42/4

2/5

2/5 HP

2/52/5

2/6

2/6 HP

2/62/6
2/6

2/6 HP

2/62/6

2/6

2/6 HP

2/62/6
2/9

2/9 CCCCompal

2/92/9

2/

2/ 10

10 HP

2/2/

1010

2/

2/ 11

11 HP

2/2/

1111

2/

2/ 12

12 HP

2/2/

1212

uestuest

Own

Own er

er

OwnOwn

erer

CCCCompal

ompal

ompalompal

ompal LAN cable can't

ompalompal

HP Docking connector pin ou

HPHP
HP Docking connector pin ou

HPHP
HP Docking connector pin ou

HPHP

HP Docking connector pin ou

HPHP

HP can't programing serial po

HPHP

HP can't boot in DC mode

HPHP

ompal WLAN_LED iss

ompalompal

HP Modem disable GPIO is no needed

HPHP

ompal system auto power on after un-

ompalompal

HP for SPI lock feature & only apply to AMD p

HPHP
HP Display

HPHP
HP Display

HPHP
HP to beefup with enough decoupling

HPHP
HP ddddocking station design change

HPHP
HP docking station power LED abnor

HPHP

HP for

HPHP

HP LLLLCD Panel flashing issue

HPHP
HP for power-down of 1394/cardread

HPHP

HP design cha

HPHP

ompal RJ45 green LED doesn't light with cable w

ompalompal

HP correct the USB debug port 0

HPHP
HP for

HPHP
HP port 9,10,11 are un-used and BIO

HPHP

4

Issue Description

Issue DIssue D

Key Board matrix e

Key Board matrix error

Key Board matrix eKey Board matrix e
LAN cable can't dectect

LAN cable can'tLAN cable can't
Docking connector pin out error

Docking connector pin ouDocking connector pin ou
Docking connector pin out error

Docking connector pin ouDocking connector pin ou
Docking connector pin out error

Docking connector pin ouDocking connector pin ou

Docking connector pin out error

Docking connector pin ouDocking connector pin ou

can't programing serial port by BIOS

can't programing serial pocan't programing serial po

can't boot in DC mode aaaadd Q2 to isolated when DC mode

can't boot in DC modecan't boot in DC mode
WLAN_LED issue

WLAN_LED issWLAN_LED iss
Modem disable GPIO is no needed delete U17 RR173, connect HAD_RST#_MDC to pin 11

Modem disable GPIO is no neededModem disable GPIO is no needed

system auto power on after un-plug AC

system auto power on after un-system auto power on after un-

for SPI lock feature & only apply to AMD platform

for SPI lock feature & only apply to AMD pfor SPI lock feature & only apply to AMD p
Display port working not right

DisplayDisplay
Display port working not right

DisplayDisplay

to beefup with enough decoupling cap on MB

to beefup with enough decouplingto beefup with enough decoupling

ocking station design change chan

ocking station design changeocking station design change

docking station power LED abnormal

docking station power LED abnordocking station power LED abnor

for improve battery life

forfor

CD Panel flashing issue rrrremove R106, D41 & add R540

CD Panel flashing issueCD Panel flashing issue

for power-down of 1394/cardreader chip

for power-down of 1394/cardreadfor power-down of 1394/cardread
when no card/1394

when no card/1394 inserted

when no card/1394 when no card/1394
design change

design chadesign cha

RJ45 green LED doesn't light with cable while

RJ45 green LED doesn't light with cable wRJ45 green LED doesn't light with cable w
system po

system po wer off with AC in

system po system po
correct the USB debug port 0 location

correct the USB debug port 0correct the USB debug port 0
for RTC battery life issue

forfor

port 9,10,11 are un-used and BIOS can disable the

port 9,10,11 are un-used and BIOport 9,10,11 are un-used and BIO
one OHCI

one OHCI controller

one OHCI one OHCI

4

escriptionDate

escriptionescription

rror Correct the right Key Board Matrix

rrorrror

dectect con

dectect dectect

t error delete p

t errort error
t error Swap

t errort error
t error

t errort error

t error let pin77

t errort error

rt by BIOS SER_SHD signal (after Q96) connect to pin 10 of JP35

rt by BIOSrt by BIOS

ue correct the net name to WL/BT_LED#

ue ue

port working not right Swap pin 146 and pin 145 con

port working not right port working not right
port working not right swap pin 52 and pin 51 connec

port working not right port working not right

improve battery life remove IDE PATA controller and flash contro

improve battery life improve battery life

inserted

insertedinserted

nge chang

ngenge

wer off with AC in

wer off with AC inwer off with AC in

RTC battery life issue cha

RTC battery life issue RTC battery life issue

controller

controller controller

3

So

So lution Description

lution Description

SoSo

lution Descriptionlution Description

Correct the right Key Board Matrix

Correct the right Key Board MatrixCorrect the right Key Board Matrix
con nection JRJ45 pin10 to GND

nection JRJ45 pin10 to GND

concon

nection JRJ45 pin10 to GNDnection JRJ45 pin10 to GND

delete pin 180 (PLT_RST#) & let it NC

delete pdelete p
Swap pin assignment of pin2,3 & pin183,184

SwapSwap
Add con

Add connection for pin 51 to signal DOCK_AUX-

Add conAdd con
pin 52 to signal

pin 52 to signal DOCK_AUX+, pin 138 (HDMICLK_UMA)

pin 52 to signalpin 52 to signal
,pin 137 ( H

,pin 137 ( HDMIDAT_UMA)

,pin 137 ( H,pin 137 ( H

let pin77 & pin 78 NC pin because of the dock side is GND

let pin77let pin77

SER_SHD signal (after Q96) connect to pin 10 of JP35

SER_SHD signal (after Q96) connect to pin 10 of JP35SER_SHD signal (after Q96) connect to pin 10 of JP35
&

& let pin76 NC

& &

dd Q2 to isolated when DC mode

dd Q2 to isolated when DC modedd Q2 to isolated when DC mode

correct the net name to WL/BT_LED#

correct the net name to WL/BT_LED#correct the net name to WL/BT_LED#
delete U17 RR173, connect HAD_RST#_MDC to pin 11

delete U17 RR173, connect HAD_RST#_MDC to pin 11delete U17 RR173, connect HAD_RST#_MDC to pin 11
of MDC v

of MDC v ia a serial resistor (4.7K)

of MDC v of MDC v

plug AC change R179 power rail from +3VALW to +3

plug ACplug AC

latform change R375 to 0ohm & connect to U19 pi

latformlatform

cap on MB chan

cap on MB cap on MB

mal aaaadd Q3 for invert STB_LED# signal behavior

malmal

er chip

er chip er chip

hile

hilehile

location swap JUSB2 & JUSB3 si

location location

S can disable the

S can disable theS can disable the

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/02 2009/09/15

change R179 power rail from +3VALW to +3VL

change R179 power rail from +3VALW to +3change R179 power rail from +3VALW to +3

Swap pin 146 and pin 145 con nection

Swap pin 146 and pin 145 con Swap pin 146 and pin 145 con
swap pin 52 and pin 51 connection

swap pin 52 and pin 51 connec swap pin 52 and pin 51 connec
chan ge C684 from 0.1U to 4.7U

chanchan

chan ge pin11, pin178, oin179 from NC to +5VS

chanchan

dd Q3 for invert STB_LED# signal behavior

dd Q3 for invert STB_LED# signal behaviordd Q3 for invert STB_LED# signal behavior

remove IDE PATA controller and flash controller power rail

remove IDE PATA controller and flash controremove IDE PATA controller and flash contro
++++3VS) & connect pin 1 of R170 to pin M5 of SB710

3VS) & connect pin 1 of R170 to pin M5 of SB710

3VS) & connect pin 1 of R170 to pin M5 of SB7103VS) & connect pin 1 of R170 to pin M5 of SB710

emove R106, D41 & add R540

emove R106, D41 & add R540emove R106, D41 & add R540

aaaadd Q104~Q107, R541~R543

dd Q104~Q107, R541~R543

dd Q104~Q107, R541~R543dd Q104~Q107, R541~R543

change R60 & R125 from 20k to 100K ohm

changchang
change the R340 power rail from +5VS to +5

change the R340 power rail from +5VS to +5VALW

change the R340 power rail from +5VS to +5change the R340 power rail from +5VS to +5

swap JUSB2 & JUSB3 signal

swap JUSB2 & JUSB3 siswap JUSB2 & JUSB3 si
cha nge D43 pin2 power rail from +3VL to +VREG3_51125

chacha
cha

cha nge the USB port from port 11 to port 12

chacha

in 180 (PLT_RST#) & let it NC

in 180 (PLT_RST#) & let it NCin 180 (PLT_RST#) & let it NC

pin assignment of pin2,3 & pin183,184

pin assignment of pin2,3 & pin183,184 pin assignment of pin2,3 & pin183,184

nection for pin 51 to signal DOCK_AUX-

nection for pin 51 to signal DOCK_AUX- nection for pin 51 to signal DOCK_AUX-

& pin 78 NC pin because of the dock side is GND

& pin 78 NC pin because of the dock side is GND & pin 78 NC pin because of the dock side is GND

let pin76 NC

let pin76 NClet pin76 NC

ia a serial resistor (4.7K)

ia a serial resistor (4.7K)ia a serial resistor (4.7K)

change R375 to 0ohm & connect to U19 pin3

change R375 to 0ohm & connect to U19 pichange R375 to 0ohm & connect to U19 pi

ge C684 from 0.1U to 4.7U

ge C684 from 0.1U to 4.7Uge C684 from 0.1U to 4.7U

ge pin11, pin178, oin179 from NC to +5VS

ge pin11, pin178, oin179 from NC to +5VSge pin11, pin178, oin179 from NC to +5VS

e R60 & R125 from 20k to 100K ohm

e R60 & R125 from 20k to 100K ohme R60 & R125 from 20k to 100K ohm

nge D43 pin2 power rail from +3VL to +VREG3_51125

nge D43 pin2 power rail from +3VL to +VREG3_51125nge D43 pin2 power rail from +3VL to +VREG3_51125
nge the USB port from port 11 to port 12

nge the USB port from port 11 to port 12nge the USB port from port 11 to port 12

Compal Secret Data

Deciphered Date

2

DOCK_AUX+, pin 138 (HDMICLK_UMA)

DOCK_AUX+, pin 138 (HDMICLK_UMA) DOCK_AUX+, pin 138 (HDMICLK_UMA)

DMIDAT_UMA)

DMIDAT_UMA)DMIDAT_UMA)

nection

nectionnection

tion

tiontion

gnal

gnalgnal

Title

Size Doc ument Number Re v

2

Date: Sheet of

1

VL

VLVL

n3

n3n3

ller power rail

ller power rail ller power rail

VALW

VALWVALW

Compal Electronics, Inc.

HW Changed-List History-1

LA-4961P

1

Rev.

Rev.Pa

Rev.Rev.

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.320

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

49 54Thurs day, August 27 , 2009

1.0

5

Version Change List

Version Change List ( P. I. R. List ) for HW Circuit

Version Change ListVersion Change List

Item

Item Issue D

Pa ge#

ItemItem

D D

C C

ge#

PaPa

ge#ge#

25

25

27

27

252 5

272 7

28

28 31

31 Au

282 8

313 1

29

29 20

20 VRAM

292 9

202 0

30

30 32

32 Do

303 0

323 2

31

31 32

32 Do

313 1

323 2

32

32 32

32 Do

323 2

323 2

TTTTitle

itle

itleitle

NNNNIC

IC

ICIC

Au dio Express

dio Express

AuAu

dio Express dio Express

VRAM ID

VRAM VRAM
Docking

DoDo
Docking

DoDo
Docking

DoDo

ck ing

ck ingcking
ck ing

ck ingcking
ck ing

ck ingcking

ID

IDID

( P. I. R. List ) for HW Circuit

( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit

Req

Req uest

uest

ReqReq

Date

DateDate

2/

2/ 14

14

2/2/

1414

2/

2/ 17

17 HP

2/2/

1717

2/

2/ 17

17 CCCCompal

2/2/

1717

2/

2/ 18

18 HP

2/2/

1818

2/

2/ 18

18 HP

2/2/

1818

2/

2/ 19

19 CCCCompal

2/2/

1919

uestuest

Own

Own er

er

OwnOwn

erer

HP

HP

HPHP
HP to i

HPHP

ompal add VRAM ID for side poert memory 2nd source

ompalompal

HP DP's 1

HPHP
HP SATA's

HPHP

ompal due

ompalompal

4

Issue Description

Issue DIssue D

design change for 8059 (co-l

design change for 8059 (co-lay)

design change for 8059 (co-ldesign change for 8059 (co-l
to improve battery life

to ito i

add VRAM ID for side poert memory 2nd source ad

add VRAM ID for side poert memory 2nd sourceadd VRAM ID for side poert memory 2nd source
DP's 16 AC coupling remove to docking station

DP's 1DP's 1
SATA's 4 AC coupling remove to docking station

SATA'sSATA's
due to DP current is 500mA

duedue

escriptionDate

escriptionescription

ay) aaaadd R544~R548

ay)ay)

mprove battery life change both pin 21 of JP34 and pin 1 of C646 connection

mprove battery lifemprove battery life

6 AC coupling remove to docking station deletet C659~C666, C512~C519

6 AC coupling remove to docking station6 AC coupling remove to docking station

4 AC coupling remove to docking station deletet R342~R3

4 AC coupling remove to docking station 4 AC coupling remove to docking station

to DP current is 500mA change

to DP current is 500mA to DP current is 500mA

3

So

So lution Description

lution Description

SoSo

lution Descriptionlution Description

dd R544~R548

dd R544~R548dd R544~R548

change both pin 21 of JP34 and pin 1 of C646 connection

change both pin 21 of JP34 and pin 1 of C646 connection change both pin 21 of JP34 and pin 1 of C646 connection
to +VREG3

to +VREG3 _51125 (from +3VL

to +VREG3to +VREG3
ad d R549, R550,R551,R176

d R549, R550,R551,R176

adad

d R549, R550,R551,R176d R549, R550,R551,R176

deletet C659~C666, C512~C519

deletet C659~C666, C512~C519deletet C659~C666, C512~C519

deletet R342~R345

deletet R342~R3deletet R342~R3
change F2 from 3A to 0.5A

changechange

F2 from 3A to 0.5A

F2 from 3A to 0.5A F2 from 3A to 0.5A

2

_51125 (from +3VL

_51125 (from +3VL_51125 (from +3VL

45

4545

1

Rev.

Rev.Pa

Rev.Rev.

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

0.3

0.3

0.30 .3

B B

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/02 2009/09/15

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

HW Changed-List History-1

LA-4961P

1

50 54Thurs day, August 27 , 2009

1.0

5

Version Change List

Version Change List ( P. I. R. List ) for HW Circuit

Version Change ListVersion Change List

Item

Item Issue D

Pa ge#

ItemItem

D D

C C

B B

ge#

PaPa

ge#ge#

25

25

NNNNIC

252 5
2222 4444 FFFFan
3333 31

31 card rea

313 1
4444 29

29 SSSSPI

292 9
5555 27 ,

27, WLAN,

27,2 7,

6666 27

27 WL

272 7

7777 27

27 SB

272 7

8888 4,

4, 6666 CCCCPU

4,4,

9999 27

27 WWWWWAN

272 7

10

10 28

28 Point s

101 0

282 8

11

11 33

33 KKKKBC

111 1

333 3

12

12 35

35 PWR OK

121 2

353 5

13

13 6666 CCCCPU

131 3

14

14 28

28 LLLLID SWITCH

141 4

282 8

15

15 21

21 power but

151 5

212 1

16

16 31 ,

31, 3 3

161 6

31,3 1,

IC

ICIC

an

anan

card reader

card reacard rea

PI

PIPI

WLAN,

25 NNNNIC

WLAN,WLAN,

252 5

WLAN

WLWL

SB710

SBSB

PU

PUPU

WAN

WANWAN

Point stick

Point sPoint s

BC

BCBC

PWR OK

PWR OKPWR OK

PU

PUPU

ID SWITCH

ID SWITCHID SWITCH

power button

power butpower but

33 KKKKBC

BC

333 3

BCBC

TTTTitle

itle

itleitle

AN

ANAN

71 0

71 0710

der

derder

tick

ticktick

IC

ICIC

ton

tonton

( P. I. R. List ) for HW Circuit

( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit

Req

Req uest

uest

ReqReq

Date

DateDate

3/

3/ 23

23

3/3/

2323

3/

3/ 23

23 CCCCompal

3/3/

2323

3/

3/ 24

24 HP

3/3/

2424

3/

3/ 25

25 HP

3/3/

2525

3/

3/ 25

25 HP

3/3/

2525

3/

3/ 25

25 HP

3/3/

2525

3/

3/ 25

25 HP

3/3/

2525

3/

3/ 30

30 HP

3/3/

3030

3/

3/ 31

31 HP

3/3/

3131

4/1

4/1 CCCCompal

4/14/1
4/6

4/6 HP

4/64/6

4/6

4/6 HP

4/64/6

4/6

4/6 HP

4/64/6

4/6

4/6 HP

4/64/6

4/7

4/7 HP

4/74/7
4/7

4/7 HP

4/74/7

uestuest

Own

Own er

er

OwnOwn

erer

HP

HP

HPHP

ompal Fan shake when temperatur

ompalompal

HP 1394 detection circuit design chan

HPHP
HP SMsC recommand to add 100k ohm fro select pin

HPHP
HP power MOSFET can not be fully shutoff w

HPHP

HP delete CLK_PCI

HPHP

HP HHHHP design change for GPIO56

HPHP
HP HP design change for CPU Therm

HPHP

HP HP

HPHP

ompal Poin

ompalompal

HP BOM ch

HPHP

HP BOM ch

HPHP

HP BOM ch

HPHP

HP LID_

HPHP

HP Pr

HPHP
HP design change for detect 14" & 15.6"

HPHP

4

Issue Description

Issue DIssue D

power-down NIC instead of low-power

power-down NIC instead of low-power mode

power-down NIC instead of low-powerpower-down NIC instead of low-power

Fan shake when temperatur e in 70 degree

Fan shake when temperaturFan shake when temperatur

1394 detection circuit design change

1394 detection circuit design chan1394 detection circuit design chan
SMsC recommand to add 100k ohm fro select pin aaaadd R560

SMsC recommand to add 100k ohm fro select pinSMsC recommand to add 100k ohm fro select pin

power MOSFET can not be fully shutoff with

power MOSFET can not be fully shutoff wpower MOSFET can not be fully shutoff w
+3V/+5

+3V/+5V level

+3V/+5+3V/+5

HP design chan

HP design chan ge

HP design chanHP design chan

HP design change for CPU Thermal

HP design change for CPU ThermHP design change for CPU Therm

HP design change for WWAN dection pin

HP HP
Point Stick pin out error

PoinPoin
BOM change

BOM chBOM ch

BOM change

BOM chBOM ch

BOM change

BOM chBOM ch

LID_SW# is triggering very intermittently and

LID_LID_
cause lockup in POST

cause lockup in POST B173

cause lockup in POST cause lockup in POST
Pr ess twice power to power on in DC mode

PrPr
design change for detect 14" & 15.6" panel

design change for detect 14" & 15.6" design change for detect 14" & 15.6"

escriptionDate

escriptionescription

e in 70 degree add

e in 70 degreee in 70 degree

V level

V levelV level

ge

gege

P design change for GPIO56 cccconnection CRD_REQ#_R to GPIO56

P design change for GPIO56P design change for GPIO56

design change for WWAN dection pin ccccontion JP10 pin26 to Super IO GPIO23

design change for WWAN dection pindesign change for WWAN dection pin

t Stick pin out error Swap

t Stick pin out errort Stick pin out error

ange chang

angeange

ange c

angeange

ange

angeange

SW# is triggering very intermittently and

SW# is triggering very intermittently andSW# is triggering very intermittently and

B173

B173 B173

ess twice power to power on in DC mode cccchange R179 to 4.7K

ess twice power to power on in DC modeess twice power to power on in DC mode

3

So

So lution Description

lution Description

SoSo

lution Descriptionlution Description

mode aaaadd Q34, R554, C712, R555, Q107 & delete R186, R239

mode mode

ge delete R533, R552,R543 & add R559, R558, Q1

gege

ith

ith ith

al change Q10 pin2 power rail from +1.8VS to +1.2V_

alal

panel add GPIO03 (14vs

panel panel

dd Q34, R554, C712, R555, Q107 & delete R186, R239

dd Q34, R554, C712, R555, Q107 & delete R186, R239dd Q34, R554, C712, R555, Q107 & delete R186, R239

add Q108, C556 & C557

Q108, C556 & C557

addadd

Q108, C556 & C557 Q108, C556 & C557

delete R533, R552,R543 & add R559, R558, Q108

delete R533, R552,R543 & add R559, R558, Q1delete R533, R552,R543 & add R559, R558, Q1

dd R560

dd R560dd R560

change R277 power rail from +3VS to +5V

change R277 power rail from +3VS to +5VS & change R277

change R277 power rail from +3VS to +5Vchange R277 power rail from +3VS to +5V
from 680

from 680 to 47k & R272 from 220K to 100K, R234 change

from 680 from 680
power rail to +5VALW & change to 10K

power rail to +5VALW & change to 10K

power rail to +5VALW & change to 10Kpower rail to +5VALW & change to 10K

delete CLK_PCIE_WLAN_REQ# from JP9 pin 7

delete CLK_PCIdelete CLK_PCI
& connect CLK_P

& connect CLK_PCIE_WLAN_REQ# to WLAN_OFF

& connect CLK_P& connect CLK_P

onnection CRD_REQ#_R to GPIO56

onnection CRD_REQ#_R to GPIO56onnection CRD_REQ#_R to GPIO56

change Q10 pin2 power rail from +1.8VS to +1.2V_HT

change Q10 pin2 power rail from +1.8VS to +1.2V_change Q10 pin2 power rail from +1.8VS to +1.2V_
& connection thermal sensor pin4 (thermal#) to CPU dir

& connection thermal sensor pin4 (thermal#) to CPU dirtertly.

& connection thermal sensor pin4 (thermal#) to CPU dir& connection thermal sensor pin4 (thermal#) to CPU dir

ontion JP10 pin26 to Super IO GPIO23

ontion JP10 pin26 to Super IO GPIO23ontion JP10 pin26 to Super IO GPIO23

Swap from pin1 to pin8

SwapSwap

change pull down resistor on FET_A R443 from 1.2K to

changchang
10K; Change pulldown resistor on SB_PWRGD R367

10K; Change pulldown resistor on SB_PWRGD R367 from

10K; Change pulldown resistor on SB_PWRGD R367 10K; Change pulldown resistor on SB_PWRGD R367

1.2K to

1.2K to 4.7K

1.2K to 1.2K to
c hange PWR_GD resistor values - change R399 to 31.6K_1%,

hange PWR_GD resistor values - change R399 to 31.6K_1%,

c c

hange PWR_GD resistor values - change R399 to 31.6K_1%,hange PWR_GD resistor values - change R399 to 31.6K_1%,

change R400 to 88.7K_1%, cha

change R400 to 88.7K_1%, change

change R400 to 88.7K_1%, cha change R400 to 88.7K_1%, cha
R407 t

R407 to 16.9K_1%, change R401 to 10K_5%

R407 t R407 t

change R35 value to 560 ohm (instead of 300 ohm)

change R35 value to 560 ohm (instead of 300 ohm)

change R35 value to 560 ohm (instead of 300 ohm)change R35 value to 560 ohm (instead of 300 ohm)

ad

ad d Q110 & C713

d Q110 & C713

adad

d Q110 & C713d Q110 & C713

hange R179 to 4.7K

hange R179 to 4.7Khange R179 to 4.7K

add GPIO03 (14vs 15_FF_DETECT) on KBC

add GPIO03 (14vsadd GPIO03 (14vs

to 47k & R272 from 220K to 100K, R234 change

to 47k & R272 from 220K to 100K, R234 changeto 47k & R272 from 220K to 100K, R234 change

from pin1 to pin8

from pin1 to pin8 from pin1 to pin8

e pull down resistor on FET_A R443 from 1.2K to

e pull down resistor on FET_A R443 from 1.2K toe pull down resistor on FET_A R443 from 1.2K to

4.7K

4.7K 4.7K

o 16.9K_1%, change R401 to 10K_5%

o 16.9K_1%, change R401 to 10K_5%o 16.9K_1%, change R401 to 10K_5%

2

E_WLAN_REQ# from JP9 pin 7

E_WLAN_REQ# from JP9 pin 7 E_WLAN_REQ# from JP9 pin 7

CIE_WLAN_REQ# to WLAN_OFF

CIE_WLAN_REQ# to WLAN_OFFCIE_WLAN_REQ# to WLAN_OFF

15_FF_DETECT) on KBC

15_FF_DETECT) on KBC15_FF_DETECT) on KBC

nge

ngenge

1

08

0808

S & change R277

S & change R277S & change R277

HT

HT HT

tertly.

tertly.tertly.

from

fromfrom

Rev.

Rev.Pa

Rev.Rev.

0.4

0.41111

0.40 .4

0.4

0.4

0.40 .4

0.4

0.4

0.40 .4

0.4

0.4

0.40 .4

0.4

0.425

0.40 .4

0.4

0.4

0.40 .4

0.4

0.4

0.40 .4

0.4

0.4

0.40 .4

0.4

0.4

0.40 .4

0.4

0.4

0.40 .4

0.4

0.4

0.40 .4

0.4

0.4

0.40 .4

0.4

0.4

0.40 .4

0.4

0.4

0.40 .4

0.4

0.4

0.40 .4

0.4

0.4

0.40 .4

17

17 26

26 NNNNIC

171 7

262 6

18

18 17 ,

17, 2 9

181 8

17,1 7,

19

19

26

191 9

262 6

A A

20

20

20

20

202 0

202 0

21

21

17

17

212 1

171 7

29 LC

LC D & FP

292 9

LCLC
NNNNIC
SB

SB710

SBSB
WebC

WebCan

WebCWebC

IC

ICIC

D & FP

D & FPD & FP

IC

ICIC

71 0

71 0710

an

anan

5

4/8

4/8 HP

4/84/8

4/8

4/8 HP

4/84/8
4/9

4/9

4/94/9
4/9

4/9

4/94/9
4/

4/ 11

4/4/

HP HHHHP design change for LED, NIC is locate on the

HPHP

HP to make sure can turn off the

HPHP
HP

HP HP desig

HPHP
HP

HP HP d

HPHP

11

HP

HP in order to support ne

1111

HPHP

P design change for LED, NIC is locate on the

P design change for LED, NIC is locate on theP design change for LED, NIC is locate on the

r

r ear, not side of system. So, after docking, even

ear, not side of system. So, after docking, even

r r

ear, not side of system. So, after docking, even ear, not side of system. So, after docking, even

NIC

NIC leds on NB side is blinking, users will not see it,

leds on NB side is blinking, users will not see it,

NICNIC

leds on NB side is blinking, users will not see it, leds on NB side is blinking, users will not see it,

to make sure can turn off the power MOS

to make sure can turn off theto make sure can turn off the
HP desig n change to simplified circuit

HP desigHP desig

HP design CPPE_NC# connection

HP dHP d
in order to support new Webcan

in order to support nein order to support ne

4

n change to simplified circuit delete Q1B, R

n change to simplified circuitn change to simplified circuit

esign CPPE_NC# connection CPPE_N

esign CPPE_NC# connectionesign CPPE_NC# connection

w Webcan

w Webcan w Webcan

power MOS change the G gate of MOS to +5VS & +5VA

power MOS power MOS

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/02 2009/09/15

delete Q37 &

delete Q37 & Q38

delete Q37 & delete Q37 &

change the G gate of MOS to +5VS & +5VALW

change the G gate of MOS to +5VS & +5VAchange the G gate of MOS to +5VS & +5VA

delete Q1B, R553

delete Q1B, Rdelete Q1B, R

CPPE_NC# connect to U10.C4 (GPIO55)

CPPE_N CPPE_N

delete Q24, C248, R113 & R446, R174.then c

delete Q24, C248, R113 & R446, R174.then connect

delete Q24, C248, R113 & R446, R174.then cdelete Q24, C248, R113 & R446, R174.then c
CARMERA_O

CARMERA_OFF to MOS G gate.

CARMERA_OCARMERA_O

Compal Secret Data

Deciphered Date

Q38

Q38Q38

553

553553

C# connect to U10.C4 (GPIO55)

C# connect to U10.C4 (GPIO55)C# connect to U10.C4 (GPIO55)

FF to MOS G gate.

FF to MOS G gate.FF to MOS G gate.

Title

Size Doc ument Number Re v

2

Date: Sheet of

LW

LWLW

onnect

onnect onnect

Compal Electronics, Inc.

HW Changed-List History-1

LA-4961P

0.4

0.4

0.40 .4

0.4

0.4

0.40 .4

0.4

0.426

0.40 .4

0.4

0.4

0.40 .4

0.4

0.4

0.40 .4

1

51 54Thurs day, August 27 , 2009

1.0

5

Version Change List

Version Change List ( P. I. R. List ) for HW Circuit

Version Change ListVersion Change List

Item

Item Issue D

Pa ge#

ItemItem

D D

C C

ge#

PaPa

ge#ge#

21

21

22

22

212 1

222 2

23

23 20

20 NNNNIC

232 3

202 0

24

24 33

33 KKKKBC

242 4

333 3

25

25 32

32

252 5

323 2

26

26 36

36

262 6

363 6

TTTTitle

itle

itleitle

SB

SB710

71 0

SBSB

71 0710

IC

ICIC
BC

BCBC

do

docking

ck ing

dodo

ck ingcking

DC

DC -DC

-DC

DCDC

-DC-DC

( P. I. R. List ) for HW Circuit

( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit

Req

Req uest

uest

ReqReq

Date

DateDate

4/

4/ 13

13

4/4/

1313

4/

4/ 13

13 HP

4/4/

1313

4/

4/ 14

14 HP

4/4/

1414

4/

4/ 17

17 HP

4/4/

1717

4/

4/ 19

19 HP

4/4/

1919

uestuest

Own

Own er

er

OwnOwn

erer

HP

HP

HPHP

HP BOM cha

HPHP
HP add pull-down resistor to signal "SLP_S5

HPHP

HP design chang

HPHP
HP to fine turn power

HPHP

4

Issue Description

Issue DIssue D

add a 10K pull-down resistor to signal "SLP_S5

add a 10K pull-down resistor to signal "SLP_S5#"

add a 10K pull-down resistor to signal "SLP_S5add a 10K pull-down resistor to signal "SLP_S5

BOM change

BOM chaBOM cha

add pull-down resistor to signal "SLP_S5#"

add pull-down resistor to signal "SLP_S5add pull-down resistor to signal "SLP_S5

design change

design changdesign chang
to fine turn power on sequence

to fine turn power to fine turn power

escriptionDate

escriptionescription

nge cha

nge nge

e connec

e e

on sequence chang

on sequenceon sequence

3

#" change R464 connection from +3VLto

#"#"

2

So

So lution Description

lution Description

SoSo

lution Descriptionlution Description

#" aaaadd R563

dd R563

#"#"

dd R563dd R563

cha nge C712 to 0.022uF (from 0.1uF)

nge C712 to 0.022uF (from 0.1uF)

chacha

nge C712 to 0.022uF (from 0.1uF)nge C712 to 0.022uF (from 0.1uF)

change R464 connection from +3VLto GND

change R464 connection from +3VLto change R464 connection from +3VLto

connect pin 2 of Q3A to signal PREP#, dock pin 111

connecconnec

change C553 from 0.01U to 0.047U

changchang

t pin 2 of Q3A to signal PREP#, dock pin 111

t pin 2 of Q3A to signal PREP#, dock pin 111t pin 2 of Q3A to signal PREP#, dock pin 111

e C553 from 0.01U to 0.047U

e C553 from 0.01U to 0.047Ue C553 from 0.01U to 0.047U

GND

GNDGND

1

Rev.

Rev.Pa

Rev.Rev.

0.4

0.4

0.40 .4

0.4

0.4

0.40 .4

0.4

0.4

0.40 .4

0.4

0.4

0.40 .4

0.4

0.4

0.40 .4

B B

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/02 2009/09/15

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

HW Changed-List History-1

LA-4961P

1

52 54Thurs day, August 27 , 2009

0.7

5

Version Change List

Version Change List ( P. I. R. List ) for HW Circuit

Version Change ListVersion Change List

Item

Item Issue D

Pa ge#

ItemItem

D D

C C

B B

ge#

PaPa

ge#ge#

25

25

1111

252 5

2222 27

27 WWWWWAN

272 7

3333 25

25 NNNNIC

252 5
4444 33

33 KKKKBC

333 3
5555 20

20 SB

202 0

6666 36

36 DC

363 6

7777 20

20 SB

202 0

8888 31

31 card rea

313 1
9999 13

13 sideport

131 3

10

10 31

31 card rea

101 0

313 1

11

11 25

25 NNNNIC

111 1

252 5

12

12 31

31 card rea

121 2

313 1

13

13 18

18 DP

131 3

181 8

TTTTitle

itle

itleitle

NNNNIC

IC

ICIC

WAN

WANWAN

IC

ICIC
BC

BCBC

SB710

71 0

SBSB

71 0710

DC -DC

-DC

DCDC

-DC-DC

SB710

71 0

SBSB

71 0710

card reader

card reacard rea
sideport memory

sideport side port

card reader

card reacard rea

card reader

card reacard rea

DP

DPD P

IC

ICIC

der

derder

memory

memorymemory

der

derder

der

derder

( P. I. R. List ) for HW Circuit

( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit

Req

Req uest

uest

ReqReq

Date

DateDate

5/9

5/9

5/95/9

5/

5/ 29

29 HP

5/5/

2929

5/

5/ 29

29 HP

5/5/

2929

5/

5/ 29

29 HP

5/5/

2929

5/

5/ 29

29 HP

5/5/

2929

5/

5/ 29

29 HP

5/5/

2929

5/

5/ 29

29 HP

5/5/

2929

6/4

6/4 HP

6/46/4
6/5

6/5 AAAAMD

6/56/5

6/8

6/8 HP

6/86/8
6/8

6/8 CCCCompal

6/86/8

6/9

6/9 HP

6/96/9

6/

6/ 11

11 AAAAMD

6/6/

1111

uestuest

Own

Own er

er

OwnOwn

erer

HP

HP

HPHP

HP Ch

HPHP

HP to support

HPHP
HP add fi

HPHP
HP delete the SATA decoupling cap, Be

HPHP

HP DC mode can't power on i

HPHP

HP for

HPHP

HP reserve 0 ohm for CRD)REQ#

HPHP

MD AMD SCL suggection:Connected a 100

MDMD

HP so

HPHP

ompal combine Q111 & Q97 as dual FET Q19

ompalompal

HP the power down feature for BIOS (The id

HPHP

MD AMD require a blank time on HPD signa

MDMD

4

Issue Description

Issue DIssue D

can't power on in AC mode due to PWR_GD

can't power on in AC mode due to PWR_GD be

can't power on in AC mode due to PWR_GD can't power on in AC mode due to PWR_GD
dr

dr ive to low

dr dr

Ch ange WWAN circuit to follow what HP comm

ChCh
team, & power down WWAN

team, & power down WWAN card

team, & power down WWAN team, & power down WWAN

to support LAN/WLAN switch

to support to support
add filtering circuit for AD input

add fiadd fi
delete the SATA decoupling cap, Because the caps

delete the SATA decoupling cap, Bedelete the SATA decoupling cap, Be
are located in docking station side a

are located in docking station side already

are located in docking station side a are located in docking station side a

DC mode can't power on issue

DC mode can't power on iDC mode can't power on i

for AMD vidoe driver reques

for for

reserve 0 ohm for CRD)REQ# aaaadd R565

reserve 0 ohm for CRD)REQ#reserve 0 ohm for CRD)REQ#
AMD SCL suggection:Connected a 100 -? 1%

AMD SCL suggection:Connected a 100AMD SCL suggection:Connected a 100
resist

resistor between MEM_CKP and MEM_CKN

resist resist
(not installed by def

(not installed by default).

(not installed by def (not installed by def

so me 1394 not detected

me 1394 not detected ad

soso

me 1394 not detectedme 1394 not detected

in order to improve the placeme

in order to improve the placement

in order to improve the placemein order to improve the placeme

the power down feature for BIOS (The idea is

the power down feature for BIOS (The idthe power down feature for BIOS (The id
to have BIOS SIO GPIO control, if that GPIO is

to have BIOS SIO GPIO control, if that GPIO is

to have BIOS SIO GPIO control, if that GPIO is to have BIOS SIO GPIO control, if that GPIO is
high, th

high, th e circuit is enabled. If the GPIO is GPI or

high, thhigh, th
low, the power-down circuit then disa

low, the power-down circuit then disabled.)

low, the power-down circuit then disa low, the power-down circuit then disa

AMD require a blank time on HPD signal when

AMD require a blank time on HPD signaAMD require a blank time on HPD signa
docking station and NB both have DP. The change

docking station and NB both have DP. The change

docking station and NB both have DP. The change docking station and NB both have DP. The change
basically will block DPB HPD for a 10

basically will block DPB HPD for a 10 0ms becuase

basically will block DPB HPD for a 10basically will block DPB HPD for a 10
p

p ass through

ass through

p p

ass throughass through

escriptionDate

escriptionescription

ive to low

ive to lowive to low

ange WWAN circuit to follow what HP comm

ange WWAN circuit to follow what HP commange WWAN circuit to follow what HP comm

LAN/WLAN switch add FE

LAN/WLAN switchLAN/WLAN switch

ltering circuit for AD input add

ltering circuit for AD inputltering circuit for AD input

ssue conn

ssuessue

AMD vidoe driver reques

AMD vidoe driver requesAMD vidoe driver reques

or between MEM_CKP and MEM_CKN

or between MEM_CKP and MEM_CKNor between MEM_CKP and MEM_CKN

ault).

ault).ault).

e circuit is enabled. If the GPIO is GPI or

e circuit is enabled. If the GPIO is GPI ore circuit is enabled. If the GPIO is GPI or

3

card

cardcard

cause the caps

cause the capscause the caps

lready

lreadylready

nt

ntnt

be

bebe

-? 1%

-? 1%-? 1%

ea is

ea is ea is

bled.)

bled.)bled.)

l when

l when l when

0ms becuase

0ms becuase0ms becuase

So

So lution Description

lution Description

SoSo

lution Descriptionlution Description

delete R555, R512. change R499 pin2 from runon

delete R555, R512. change R499 pin2 from runon to B+.

delete R555, R512. change R499 pin2 from runon delete R555, R512. change R499 pin2 from runon
ch

ch ange Q79 power source from V1.2_LAN to +1.2VALW

ange Q79 power source from V1.2_LAN to +1.2VALW

chch

ange Q79 power source from V1.2_LAN to +1.2VALWange Q79 power source from V1.2_LAN to +1.2VALW

delete R279, R528, Q99 & change Q100 pi

delete R279, R528, Q99 & change Q100 pin5 power

delete R279, R528, Q99 & change Q100 pidelete R279, R528, Q99 & change Q100 pi
rai

rail from +3VALW to +3VS

l from +3VALW to +3VS

rai rai

l from +3VALW to +3VSl from +3VALW to +3VS

add FET Q111

add FEadd FE
add C714, C715, C716,R564

C714, C715, C716,R564

add add

C714, C715, C716,R564C714, C715, C716,R564

delete C289~C2

delete C289~C292

delete C289~C2delete C289~C2

connect R442.1 pin to +3VALW (instead of VL)

ect R442.1 pin to +3VALW (instead of VL)

conn conn

ect R442.1 pin to +3VALW (instead of VL)ect R442.1 pin to +3VALW (instead of VL)

conn

connect R175.2 to signal DOCK_ID (instead of GND)

ect R175.2 to signal DOCK_ID (instead of GND)

connconn

ect R175.2 to signal DOCK_ID (instead of GND)ect R175.2 to signal DOCK_ID (instead of GND)

,

, and make R175 to 100K

and make R175 to 100K

, ,

and make R175 to 100Kand make R175 to 100K

dd R565

dd R565dd R565

un-install

un-install R68

un-installun-install

ad d Q23, R566

d Q23, R566

adad

d Q23, R566d Q23, R566

combine Q111 & Q97 as dual FET Q19

combine Q111 & Q97 as dual FET Q19 combine Q111 & Q97 as dual FET Q19

add

add R565, R567, C717,C718

R565, R567, C717,C718

add add

R565, R567, C717,C718R565, R567, C717,C718

delete R124, R514 add Q113,R568,R569,C7

delete R124, R514 add Q113,R568,R569,C7 19

delete R124, R514 add Q113,R568,R569,C7delete R124, R514 add Q113,R568,R569,C7

T Q111

T Q111T Q111

R68

R68 R68

92

9292

2

n5 power

n5 powern5 power

19

1919

1

to B+.

to B+. to B+.

Rev.

Rev.Pa

Rev.Rev.

0.5

0.5

0.50 .5

0.5

0.5

0.50 .5

0.5

0.5

0.50 .5

0.5

0.5

0.50 .5

0.5

0.5

0.50 .5

0.5

0.5

0.50 .5

0.5

0.5

0.50 .5

0.5

0.5

0.50 .5

0.5

0.5

0.50 .5

0.5

0.5

0.50 .5

0.5

0.5

0.50 .5

0.5

0.5

0.50 .5

0.5

0.5

0.50 .5

14

14 27

27 WWWWWAN

141 4

272 7

15

15 8888 DDDDDR

151 5

16

16 6666 CCCCPU

161 6

17

17 17

17 web

171 7

171 7

A A

18 31

31 WWWWWAN

181 8

313 1

WAN

WANWAN

DR

DRDR

PU

PUPU

web cam

cam

webweb

camcam

WAN

WANWAN

5

6/

6/ 11

11 CCCCompal

6/6/

1111

6/

6/ 11

11 CCCCompal

6/6/

1111

6/

6/ 12

12 HP

6/6/
6/

6/ 13

6/6/
6/

6/ 13

6/6/

HP HP request add 1k resistor between Q10.2 and LDT_R

1212

HPHP

13 CCCCompal

1313
13 HP

HP WWAN LED abnormal when po

1313

HPHP

ompal

ompalompal

ompal EEEEMI request 0.1UF cap for +1.8V

ompalompal

ompal EMI request add com-choke for

ompalompal

MC1_DISABL is open drain seeting need pull high,

MC1_DISABL is open drain seeting need pull high,

MC1_DISABL is open drain seeting need pull high, MC1_DISABL is open drain seeting need pull high,
and +3V_WWAN need discharge circu

and +3V_WWAN need discharge circuit

and +3V_WWAN need discharge circuand +3V_WWAN need discharge circu

MI request 0.1UF cap for +1.8V add

MI request 0.1UF cap for +1.8VMI request 0.1UF cap for +1.8V

HP request add 1k resistor between Q10.2 and LDT_R ST#.

HP request add 1k resistor between Q10.2 and LDT_RHP request add 1k resistor between Q10.2 and LDT_R

EMI request add com-choke for webcam

EMI request add com-choke forEMI request add com-choke for
WWAN LED abnormal when power down

WWAN LED abnormal when poWWAN LED abnormal when po

4

webcam add

webcam webcam

wer down chajnge Q53 pin2 power rail from +3VS to +3V_WW

wer downwer down

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.5

0.5

ad

ad dR570, R571, Q114

dR570, R571, Q114

adad

dR570, R571, Q114dR570, R571, Q114

it

itit

add C720, C721

C720, C721

addadd

C720, C721 C720, C721

ST#. aaaadd R572

ST#.ST#.

add L49

L49

addadd

L49 L49

chajnge Q53 pin2 power rail from +3VS to +3V_WWAN

chajnge Q53 pin2 power rail from +3VS to +3V_WWchajnge Q53 pin2 power rail from +3VS to +3V_WW

2007/08/02 2009/09/15

3

Compal Secret Data

Deciphered Date

dd R572

dd R572dd R572

2

AN

ANAN

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

HW Changed-List History-1

LA-4961P

1

0.50 .5

0.5

0.5

0.50 .5

0.5

0.5

0.50 .5

0.5

0.5

0.50 .5

0.5

0.51 8

0.50 .5

53 54Thurs day, August 27 , 2009

0.7

5

Version Change List

Version Change List ( P. I. R. List ) for HW Circuit

Version Change ListVersion Change List

Item

Item Issue D

Pa ge#

ItemItem

D D

C C

ge#

PaPa

ge#ge#

30

30

1111

303 0
2222 21, 28

21 , 28 SM

21 , 2821, 28

1111 31

31 card rea

313 1

2222

33 1.0

333 3

TTTTitle

itle

itleitle

USB

USB

USBUSB
SM SC CBB

SC CBB

SMSM

SC CBBSC CBB

card reader

card reacard rea

Aud

Audio

io33

AudAud

ioio

der

der der

( P. I. R. List ) for HW Circuit

( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit

Req

Req uest

uest

ReqReq

Date

DateDate

6/

6/ 20

20

6/6/

2020

7/4

7/4 HP

7/47/4

8/

8/ 13

13 HP

8/8/

1313

8/ 24

24

8/8/

2424

uestuest

Own

Own er

er

OwnOwn

erer

CCCCompal

ompal

ompalompal

HP for SM

HPHP

HP

HPHP

HP

HP8/

HPHP

4

Issue Description

Issue DIssue D

change C485, C491,C690 footprint for 2nd sou

change C485, C491,C690 footprint for 2nd sou rce

change C485, C491,C690 footprint for 2nd souchange C485, C491,C690 footprint for 2nd sou
for SMsC CBB utilized the Lid#.

for SMfor SM

card reader can't detect & r

card reader can't detect & reduce power consumption

card reader can't detect & rcard reader can't detect & r

there is the po-po sound when warm boot

there is the po-po sound when warm bothere is the po-po sound when warm bo

escriptionDate

escriptionescription

sC CBB utilized the Lid#. move Q110 close to SB710 and pull high LID

sC CBB utilized the Lid#.sC CBB utilized the Lid#.

educe power consumption

educe power consumptioneduce power consumption

3

rce

rcerce

ot

otot

2

So

So lution Description

lution Description

SoSo

lution Descriptionlution Description

change foo

change footprint from C_D to C_D2E

change foochange foo

move Q110 close to SB710 and pull high LID_SW#

move Q110 close to SB710 and pull high LIDmove Q110 close to SB710 and pull high LID

remove C718 and change R558 to 47K o

remove C718 and change R558 to 47K ohm

remove C718 and change R558 to 47K oremove C718 and change R558 to 47K o

ad

ad d Q115, R575,Q116

d Q115, R575,Q116there is the po-po sound when warm bo

adad

d Q115, R575,Q116d Q115, R575,Q116

tprint from C_D to C_D2E

tprint from C_D to C_D2Etprint from C_D to C_D2E

hm

hmhm

_SW#

_SW#_SW#

1

Rev.

Rev.Pa

Rev.Rev.

0.6

0.6

0.60 .6

0.6

0.6

0.60 .6

1.0

1.0

1.01 .0

1.0

1.01 .0

B B

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/02 2009/09/15

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

HW Changed-List History-1

LA-4961P

1

54 54Th urs day, Au gust 27, 2009

0.7