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LA-4901P
Schematics
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COMPAL LA-4901P Schematics

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1
A A
2
3
4
5
Compal Confidential
Schematics Document
B B
Intel CLARKSFIELD/ARRANDALE with IBEX PEAK-M core logic
Cartier DIS
C C
LA-4901P
2009-12-01
REV:1.0
D D
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
Cover Sheet
LA -490 1 P
5
1 54Tu e s da y, De ce mbe r 15 , 20 09
1. 0
1
Compal Confidential
File Name : LA-4901P
Thermal Sensor EMC2113
A A
Page 4
Fan Control
Page 4
DP to Docking
2
Page 36
3
Cartier DIS
Mobile
4
5
Accelerometer
LIS302DLTR
Page 34
XDP Conn.
LCD conn
CRT
Page 19
Page 18
CRT to Docking
Page 36
DP conn
Page 18
N10 M-GLM
Page 20,21,22,23
VRAM DDR3-512MB
Page 24,25
PEG X 16
Auburndale / Clarksfield
Socke t-rPGA989
37.5mm*37.5mm
Page 4,5,6,7,8
DMI X4
Dual Channel
SATA4
DDR3-SO-DIMM X 2DDR3 1066/1333MHz 1.5V
BANK 0, 1, 2, 3
E-SATA and USB comb o conn x 1(For I/O)
Page 32
Page 9,10
Clock Generator ICS9LPRS397
Page 4
CK505
Page 11
B B
Express Card 54
PCIE X1 + USB X1
Audio Board
WWAN Card
PCIE X1
Page 28
USB2.0
USB2.0
Intel Ibex Peak M
Azalia
1071pins
SATA0
SATA1
10/100/1000 LAN
Intel Hansville GbE
PHY
Page 26
WLAN Card
WLAN + PCIE X1
Page 28
PCI-E BUS
Richo R5C835
Controller
Page 30
PCI BUS
25mm*27mm
Page 12,13,14,15,16,17
USB x2(Docking) FingerPrinter VFM451
USBx1
USB conn x 3(For I/O) BT Conn USB x 1
USB x1(Camara)
MDC V1.5
Audio CKT
IDT 92HD75
RJ45 CONN
C C
Page 27
1394 port
Smart Card
Modular
SD/MMC Slot
Audio Board
SATA ODD Connector
Modular
Page 32
Page 19
Page 31
Audio Board
Page 12
Page 34
Page 33
daughter board
RJ11
TPA6047A
AMP & Audio Jack
Cable
Audio Board
2.5" SATA HDD Connector
RTC CKT.
Page 12
Power OK CKT.
Page 37
LED
Audio Board
TPM1.2 SLB9635TT
Page 33 page 35
LPC BUS
SMSC KBC 1098
SMSC Super I/O
LPC47N217
Page 36
Page 12
COM 1 LPT
Power On/Off CKT.
D D
Page 31
DC/DC Interface CKT.
Page 38
1
Touch Pad CONN.
TrackPoint CONN.
SPI ROM
8M B
2
Page 31
Page 33
Int.KBD
Page 31Page 31
( Docking ) ( Docking )
Page 34 Page 34
Security Classification
Issued Date
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Page 34
Docking CONN.
(2) PS/ 2 Interfaces (2) USB 2.channels (2) SATA Channels (2) Display Port Channels (1) Se rial Port (1) Pa rallel Port (1) Line In (1) Line Out (1) RJ45 (10/100/1000) (1 ) VGA (1) 2 LAN indicator LED's (1) Power Button (1) I2C interface
Compal Electronics, Inc.
Block Diagram
LA -490 1 P
5
2 54Tu e s da y, De ce mbe r 15 , 20 09
1. 0
1
Voltage Rails
State
S0
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery don't exist
A A
( O MEANS ON X MEANS OFF )
+RTCVCC
power plane
O O O O O O
+B +3VL +0.75V
O O O O O
X
+5VALW +3VALW
O O O O
X X X X
+3VM +1.05VM
O O O O
X X
+1.5V
O
X X X
+5VS +3VS +1.5VS +VGA_CORE +VCCP +CPU_CORE +1.05VS +1.8VS
OO OO
X
X
Symbol Note :
: means Digital Ground
: means Analog Ground
Install below 45 level BOM structure
45@ : means just put it in the BOM of 45 level.
Install below 43 level BOM structure
@ : means just reserve , no build CONN@ : means ME part. VRAM@ : means VRAM strip pin part.
SMBUS Control Table
SOURCE
SMB_EC_CK1 SMB_EC_DA1
SMBCLK SMBDATA
SML0CLK SML0DATA
SML1CLK SML1DATA
SMSC1098
Calpella
Calpella
Calpella
BATT
V
X X X
THERMAL
SODIMM CLK CHIP
XDP G-SENSOR
X
X X
V V
X
X
X X
MINI CARD
V V
X X X
DOCK
X
X
V
X
X X
SENSOR
NIC
X X X
V
X
X X X
V
V
X
X
Security Classification
Issued Date
1
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
Notes List
LA -490 1 P
3 54Tu e s da y, De ce mbe r 15 , 20 09
1. 0
Layout rule 10mil width tr：ace length < 0.5", spacing 20mil
A A
H_ P ECI15
to power; PU to VCCP at power side also
H_ P R OC H OT#46
H_ T HER MTR IP#15 ,20
H_ C P UR ST#
H_ P M_ S Y NC14
H_ C P UP W RGD
H _ C PU P WRG D15
PM _ DR A M_ P WR GD14
from power
VT TP W R GOOD37
B B
BU F _P L T_R ST#15
200 9/0 2/2 4 HP DB-2
VD D PW R G O OD _R
200 9/0 4/1 0 HP DB-3
1
CO M P3
R220 _0402_1%
1 2 1 2 1 2 1 2
T2
R1 6
1 2
0_ 0402_5%
R1 7
1 2
0_ 0402_5%
R1 9
1 2
0_ 0402_5%
R2 0
1 2
0_ 0402_5%
R2 1
1 2
0_ 0402_5%
R2 2
1 2
0_ 0402_5%
R2 4
1 2
0_ 0402_5%
R2 6
1 2
0_ 0402_5%
R3 0
1 2
0_ 0402_5%
R3 1
1 2
1.5K_ 04 02 _1 %
75 0_0402_1%
R1 4 1.5K_ 04 02 _1 %
1 2
R1 5 75 0_0402_1%
1 2
CO M P2
R520 _0402_1%
CO M P1
R749 .9_0402_1% R949 .9_0402_1%
CO M P0
TP _ S KTO CC#
H_ C A TE R R#
H_ P EC I_ISO
H_ P R OC H O T#_D
H_ T HER M TRIP# _R
H_ C P UR S T# _R
H_ P M_ S Y N C_ R
VC C PW R G O OD _1
VC C PW R G O OD _0
VD D PW R G O OD _R
H_ P W RG D _ XDP_RH_ P W RG D _ XDP
PL T _R ST# _R
12
R3 3
JC P U1B
AT23
COMP3
AT24
COMP2
G16
COMP1
AT26
COMP0
AH24
SKTOCC#
AK14
CATERR#
AT15
PECI
AN26
PROCHOT#
AK15
THERMTRIP#
AP26
RESET_OBS#
AL15
PM_SYNC
AN14
VCCPWRGOOD_1
AN27
VCCPWRGOOD_0
AK13
SM_DRAMPWROK
AM15
VTTPWRGOOD
AM26
TAPPWRGOOD
AL14
RSTIN#
IC , AUB _ CFD_rPGA ,R1P0
+1 .5 V
12
R1 22 6 0_ 0402_5%
200 9/0 7/0 2 HP SI-1b
MISC THERMAL
PWR MANAGEMENT
@
VC C P_ 1 . 5 VS PWR GD 37
JTA G M APPING
CLOCKS
DDR3
MISC
JTAG & BPM
2
C O N N @
BCLK
BCLK#
BCLK_ITP
BCLK_ITP#
PEG_CLK
PEG_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
SM_DRAMRST#
SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]
PM_EXT_TS#[0] PM_EXT_TS#[1]
PRDY# PREQ#
TRST#
TDI_M
TDO_M
DBR#
BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]
TCK TMS
TDO
A16 B16
AR30 AT30
E16 D16
A18 A17
F6 AL1
AM1 AN1
AN15 AP15
AT28 AP27
AN28 AP28 AT27
AT29
TDI
AR27 AR29 AP29
AN25
AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23
CL K _ BC LK CL K _ BCL K#
CL K _ C PU_XD P CL K _ C PU_XD P#
CL K_EXP C LK_EX P#
R1 1 0_ 0402_5%
1 2
R1 3 0_ 0402_5%
1 2
SM _ R CO MP0 SM _ R CO MP1 SM _ R CO MP2
PM_ EXTTS# 0 PM_ EXTTS# 1
XD P _PR D Y# XD P _PREQ#
XD P _TC K X DP_ TMS XD P _TR ST#
XD P _TD I XD P _TD O XD P _TD I_ M XD P _TD O_ M
XD P _D BRE SET#
X DP_ BPM#0 X DP_ BPM#1 X DP_ BPM#2 X DP_ BPM#3 X DP_ BPM#4 X DP_ BPM#5 X DP_ BPM#6 X DP_ BPM#7
T3
R1 8 0_ 0402_5%
1 2
C 1
0. 1U _0 40 2_ 16 V4Z
3
R1 10 K_0 40 2_ 5%
PM_ EXTTS# 0
CL K _ CP U_BC LK 15 CL K _ CP U_BC LK# 15
CL K_ EXP 13 CL K_ EXP # 13
from DDR
PM_ EXTTS# 1_ R 9,10
R1 21 9 10 0K_ 04 02 _5 %
X DP_ BPM#0
R1 01 6 0_0402_5%
1 2
R1 01 7 0_0402_5%@
CF G 125 CF G 135 CF G 145 CF G 155
@
X DP_ BPM#1 X DP_ BPM#2 X DP_ BPM#3
+V C CP
1
PM _ PW R BTN# _R12 ,14
2
1 2
R1 01 8 0_0402_5%
1 2
R1 01 9 0_0402_5%@
1 2
R1 02 0 0_0402_5%
1 2
R1 02 1 0_0402_5%@
1 2
R1 02 2 0_0402_5%
1 2
R1 02 3 0_0402_5%@
1 2
H_ C P UP W RGD
H_ P W RG D _ XDP
PM_ EXTTS# 1
SS M3 K7002F_ SC5 9- 3 Q8 7
S
G
2
12
1
@
2
CF G 175 CF G 165
R2 5 1K_ 04 02 _5 %
1 2
1 2
R2 7 0_0 40 2_ 5%
200 8/1 2/1 2 HP
1 2
R3 10 K_0 40 2_ 5%
1 2
+1 .5 V
12
R1 21 8 1K_ 04 02 _5 %
D
13
200 9/0 7/0 2 HP SI-1b
C9 97 47 0P_ 04 02 _5 0V 8J
200 9/0 7/2 1 HP SI-2
XD P _PREQ# XD P _PR D Y#
XD P _BPM#0_R XD P _BPM#1_R
XD P _BPM#2_R XD P _BPM#3_R
X DP_ BPM#4 X DP_ BPM#5
X DP_ BPM#6 X DP_ BPM#7
H_ C P UP W RGD _R PM _ PW R B TN#_R
T11 0 T11 1
XD P _TC K
DR A MR ST # 9,1 0
PC H _ DD R _ RST 5 ,1 5
CPU XDP Connector
JP 1
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
39
PWRGOOD/HOOK0
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
SAMTE_BSH -0 30 -0 1- L- D-A C O N N@
4
PM _ PW R B TN#_R
OBSFN_C0 OBSFN_C1
OBSDATA_C0 OBSDATA_C1
OBSDATA_C2 OBSDATA_C3
OBSFN_D0 OBSFN_D1
OBSDATA_D0 OBSDATA_D1
OBSDATA_D2 OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND1
GND3
GND5
GND7
GND9
GND11
GND13
GND15
TRST#
GND17
R9 09 1K_ 04 02 _5 %@
TD0
TDI
TMS
1 2
200 8/1 0/0 9 HP
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
C F G8 5 C F G9 5
C F G0 5 C F G1 5
C F G2 5 C F G3 5
CF G 10 5 CF G 11 5
C F G4 5 C F G5 5
C F G6 5 C F G7 5
CL K _ C PU_XD P CL K _ C PU_XD P#
XD P _RST#_R XD P _D BRE SET#_R
XD P _TD O XD P _TR ST# XD P _TD I X DP_ TMS
XD P _RST#_R
+V C CP
XD P _TD O
200 9/0 2/2 5 HP DB-2
200 8/1 2/1 2 HP DB-1
+V C CP
1K_ 04 02 _5 %
R2 8
1 2 1 2
R2 9 0_ 0402_5%
1 2
R3 2 0_ 0402_5%
H_ C P UR ST# XD P _D BRE SET#
@
5
200 9/0 2/0 6 HP DB-2
R1 0 51 _0402_5%
1 2
Thi s s hal l pla ce near XDP
200 9/0 4/1 3 Com pal DB-3
+3 VS
12
R2 3 1K_ 04 02 _5 %
XD P _DB RES ET# 12,1 4
PL T_RST# 12,15,2 0, 26 ,2 8, 31 ,33
+V C CP+V C CP
H_ C A TE R R# H_ P R OC H O T#_D H_ C P UR S T# _R
DDR 3 C omp en sat ion Signals
SM _ R CO MP0 SM _ R CO MP1 SM _ R CO MP2
Lay out No te :Pl ease these res ist ors n ear Processor
Pro ces sor P ullups
R3 9 49. 9_ 04 02 _1 %
1 2
R4 2 68_ 04 02 _5 %
1 2
R4 5 68_ 04 02 _5 %@
1 2
R5 2 10 0_0402_1%
1 2
R5 3 24 .9_0402_1%
1 2
R5 4 13 0_0402_1%
1 2
+V C CP
REMOTE Thermal sensor
RE M OT E2+
C 4
22 00P_0 40 2_ 50 V7K
RE M OTE 2-
1
2
1
200 9/0 2/0 6 HP DB-2
Clo se to XDP
XD P _TR ST#
R5 5 51 _0402_5%
1 2
C
Q1
2
B
MMB T3904WH _S OT3 23 -3
E
3 1
Layout Note: place near the hottest spot area for
NB & top SODIMM.
+3 VS
12
R3 5
68 _0402_5%
1
200 9/0 2/0 6 HP DB-2
C 3
0. 1U _0 40 2_ 16 V4Z
H_ T HER MTR IP#15 ,20
200 9/0 2/2 0 HP DB-2 200 9/0 4/1 0 HP DB-3
2
3
1 2
R1 14 1
2
H_ T HER MTRI P#
Security Classification
Issued Date
C C
D D
Thermal Sensor EMC2113-2 with CPU PWM FAN
VG A _ TH E RMD C21
VG A _ TH ER MDA21
1 2
C 2 22 00P_0 40 2_ 50 V7K
200 9/0 1/2 1 HP
10 K_0 40 2_ 5%
TH E RM _S CI#15
R4 8 10 K_0 40 2_ 5%@
1 2
+3 VS
R5 1 0_ 0402_5%
1 2
200 8/1 1/1 7 HP
VG A _ TH E RM DC VG A _ TH E RMD A +3 V S_TH ER FA N _P W M- R AD D R_ SEL
2008/09/15 2009/12/31
U5 4 EMC 21 13 -2 -A X_Q FN 16 _4X4
1
DN
2
DP
3
0.4mA
VDD
4
PWM_IN
5
ADDR_SEL
6
ALERT#
7
SYS_SHDN#
8
SMDATA
Add 0 ohm a nd 0.1u
Compal Secret Data
Deciphered Date
4
GND
17
DP2/DN3 DN2/DP3
TRIP_SET
SHDN_SEL
GND
PWM
TACH
SMCLK
RE M OT E2+
16
RE M OTE 2-
15
R3 8 4.53K_0 40 2_ 1%
14
1 2
200 9/0 2/0 6 HP DB-2
R4 1 10 K_0 40 2_ 5%
13
1 2
12
FA N _P W M _O UT
11
T A C H
10 9
SM B_CL K_ S3 9 ,10,11,13 ,32SM B_D ATA _S39,10,11 ,1 3, 32
R7 94 0_0402_5%
FA N _P W M- R
C8 30
0. 1U _0 40 2_ 16 V4Z
200 9/0 7/2 3 Com pal th ermal team
@
1 2
R4 4 10 K_0 40 2_ 5%
R1 06 1 0_0402_5%
1 2
R4 7 10 K_0 40 2_ 5%
Ins tall
Don 't Ins tall
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
1 2
1
@
2
1 2
Add in th is ma p at 11/24
R10 60
R79 4,R 1061
+3 VS
+3 VS
10/16 HP Add
+5 VS
12
200 9/0 2/0 6 HP DB-2
R1 06 0 10 K_0 40 2_ 5%
EMC 2113EMC 210 3 ( de fault)
R79 4,R 1061
JP 2
C O N N@
1
0.3A
1
2
2
3
3
4
4
5
G5
6
G6
ACE S_85205 -040 01
200 9/0 1/2 0 Com pal HW
R10 60
Compal Electronics, Inc.
ARD/CFD(1/5)-Thermal/XDP
LA -490 1 P
5
FA N _P W M 35
4 54Tu e s da y, De ce mbe r 15 , 20 09
1. 0
1
JC P U1A
DM I _C RX_ PTX _N 014 DM I _C RX_ PTX _N 114 DM I _C RX_ PTX _N 214 DM I _C RX_ PTX _N 314
DM I_ CR X_PTX_ P014 DM I_ CR X_PTX_ P114 DM I_ CR X_PTX_ P214
A A
DM I_ CR X_PTX_ P314 DM I _C TX_ PRX _N 014
DM I _C TX_ PRX _N 114 DM I _C TX_ PRX _N 214 DM I _C TX_ PRX _N 314
DM I_ CTX_P RX_ P014 DM I_ CTX_P RX_ P114 DM I_ CTX_P RX_ P214 DM I_ CTX_P RX_ P314
R5 8 1K_ 04 02 _5 %
B B
C C
1 2
R5 9 1K_ 04 02 _5 %
1 2
R6 2 1K_ 04 02 _5 %
1 2
R6 3 1K_ 04 02 _5 %
1 2
R6 4 1K_ 04 02 _5 %
1 2
A24
DMI_RX#[0]
C23
DMI_RX#[1]
B22
DMI_RX#[2]
A21
DMI_RX#[3]
B24
DMI_RX[0]
D23
DMI_RX[1]
B23
DMI_RX[2]
A22
DMI_RX[3]
D24
DMI_TX#[0]
G24
DMI_TX#[1]
F23
DMI_TX#[2]
H23
DMI_TX#[3]
D25
DMI_TX[0]
F24
DMI_TX[1]
E23
DMI_TX[2]
G23
DMI_TX[3]
E22
FDI_TX#[0]
D21
FDI_TX#[1]
D19
FDI_TX#[2]
D18
FDI_TX#[3]
G21
FDI_TX#[4]
E19
FDI_TX#[5]
F21
FDI_TX#[6]
G18
FDI_TX#[7]
D22
FDI_TX[0]
C21
FDI_TX[1]
D20
FDI_TX[2]
C18
FDI_TX[3]
G22
FDI_TX[4]
E20
FDI_TX[5]
F20
FDI_TX[6]
G19
FDI_TX[7]
F17
FDI_FSYNC[0]
E17
FDI_FSYNC[1]
C17
FDI_INT
F18
FDI_LSYNC[0]
D17
FDI_LSYNC[1]
IC , AUB _ CFD _r PG A,R1P 0
DMI Intel(R) FDI
PCI EXPRESS -- GRAPHICS
C O N N @
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS PEG_RX#[0]
PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]
PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]
PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]
PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]
PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]
PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]
B26 A26 B27 A25
K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31
J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30
L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26
L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25
CFG Straps for PROCESSOR
C F G 0
R6 7 3.01K_0 40 2_ 1%@
1 2
PCI -Ex pre ss Co nfi gur ati on Select
1: Sin gle PEG 0: Bif urc at ion enabled
CFG0
Not ap pli ca ble fo r C lar ksf ie ld Processor
R6 9 3.01K_0 40 2_ 1%
C F G 3
C F G 4
D D
1 2
CFG 3-P CI Ex pre ss Sta tic Lane Reversal
1: Nor mal O peration 0: Lan e N um ber s Reversed
CFG3
15 -> 0, 14 -> 1, .....
R7 0 3.01K_0 40 2_ 1%@
1 2
CFG 4-D isp la y P ort Presence
1: Dis abl ed ; N o P hys ica l Display Port att ach ed to Em bed ded Di splay Port
CFG4
0: Ena ble d; An ex ter nal Display Port dev ice is c onn ect ed to the Embedded Dis pla y Port
2
EX P _I CO MPI
EX P _R BI AS PC I E_ CR X_GTX _N0
PC I E_ CR X_GTX _N1 PC I E_ CR X_GTX _N2 PC I E_ CR X_GTX _N3 PC I E_ CR X_GTX _N4 PC I E_ CR X_GTX _N5 PC I E_ CR X_GTX _N6 PC I E_ CR X_GTX _N7 PC I E_ CR X_GTX _N8 PC I E_ CR X_GTX _N9 PC I E_ CR X_GTX _N10 PC I E_ CR X_GTX _N11 PC I E_ CR X_GTX _N12 PC I E_ CR X_GTX _N13 PC I E_ CR X_GTX _N14 PC I E_ CR X_GTX _N15
PC I E_ CRX _G TX_ P0 PC I E_ CRX _G TX_ P1 PC I E_ CRX _G TX_ P2 PC I E_ CRX _G TX_ P3 PC I E_ CRX _G TX_ P4 PC I E_ CRX _G TX_ P5 PC I E_ CRX _G TX_ P6 PC I E_ CRX _G TX_ P7 PC I E_ CRX _G TX_ P8 PC I E_ CRX _G TX_ P9 PC I E_ CRX _G TX_ P1 0 PC I E_ CRX _G TX_ P1 1 PC I E_ CRX _G TX_ P1 2 PC I E_ CRX _G TX_ P1 3 PC I E_ CRX _G TX_ P1 4 PC I E_ CRX _G TX_ P1 5
PC I E _C TX_ GR X_C_N 0 PC I E _C TX_ GR X_C_N 1 PC I E _C TX_ GR X_C_N 2 PC I E _C TX_ GR X_C_N 3 PC I E _C TX_ GR X_C_N 4 PC I E _C TX_ GR X_C_N 5 PC I E _C TX_ GR X_C_N 6 PC I E _C TX_ GR X_C_N 7 PC I E _C TX_ GR X_C_N 8 PC I E _C TX_ GR X_C_N 9 PC I E_ CT X_G RX _C_N1 0 PC I E_ CT X_G RX _C_N1 1 PC I E_ CT X_G RX _C_N1 2 PC I E_ CT X_G RX _C_N1 3 PC I E_ CT X_G RX _C_N1 4 PC I E_ CT X_G RX _C_N1 5
PC I E_ CT X_G RX _C_P0 PC I E_ CT X_G RX _C_P1 PC I E_ CT X_G RX _C_P2 PC I E_ CT X_G RX _C_P3 PC I E_ CT X_G RX _C_P4 PC I E_ CT X_G RX _C_P5 PC I E_ CT X_G RX _C_P6 PC I E_ CT X_G RX _C_P7 PC I E_ CT X_G RX _C_P8 PC I E_ CT X_G RX _C_P9 PC I E_ CT X_G RX _C_P1 0 PC I E_ CT X_G RX _C_P1 1 PC I E_ CT X_G RX _C_P1 2 PC I E_ CT X_G RX _C_P1 3 PC I E_ CT X_G RX _C_P1 4 PC I E_ CT X_G RX _C_P1 5
R5 6 49 .9 _0 40 2_ 1%
1 2
R5 7 75 0_ 04 02 _1%
1 2
Layout rule tra：ce length < 0.5"
PC I E_ CRX _G TX_ N[ 0..15 ] 20
PC I E_ CRX _G TX_ P[0.. 15 ] 20
C 5 0.1U_ 04 02 _1 0V 7K
1 2
C 6 0.1U_ 04 02 _1 0V 7K
1 2
C 7 0.1U_ 04 02 _1 0V 7K
1 2
C 8 0.1U_ 04 02 _1 0V 7K
1 2
C 9 0.1U_ 04 02 _1 0V 7K
1 2
C1 0 0.1U_ 04 02 _1 0V 7K
1 2
C1 1 0.1U_ 04 02 _1 0V 7K
1 2
C1 2 0.1U_ 04 02 _1 0V 7K
1 2
C1 3 0.1U_ 04 02 _1 0V 7K
1 2
C1 4 0.1U_ 04 02 _1 0V 7K
1 2
C1 5 0.1U_ 04 02 _1 0V 7K
1 2
C1 6 0.1U_ 04 02 _1 0V 7K
1 2
C1 7 0.1U_ 04 02 _1 0V 7K
1 2
C1 8 0.1U_ 04 02 _1 0V 7K
1 2
C1 9 0.1U_ 04 02 _1 0V 7K
1 2
C2 0 0.1U_ 04 02 _1 0V 7K
1 2
C2 1 0.1U_ 04 02 _1 0V 7K
1 2
C2 2 0.1U_ 04 02 _1 0V 7K
1 2
C2 3 0.1U_ 04 02 _1 0V 7K
1 2
C2 4 0.1U_ 04 02 _1 0V 7K
1 2
C2 5 0.1U_ 04 02 _1 0V 7K
1 2
C2 6 0.1U_ 04 02 _1 0V 7K
1 2
C2 7 0.1U_ 04 02 _1 0V 7K
1 2
C2 8 0.1U_ 04 02 _1 0V 7K
1 2
C2 9 0.1U_ 04 02 _1 0V 7K
1 2
C3 0 0.1U_ 04 02 _1 0V 7K
1 2
C3 1 0.1U_ 04 02 _1 0V 7K
1 2
C3 2 0.1U_ 04 02 _1 0V 7K
1 2
C3 3 0.1U_ 04 02 _1 0V 7K
1 2
C3 4 0.1U_ 04 02 _1 0V 7K
1 2
C3 5 0.1U_ 04 02 _1 0V 7K
1 2
C3 6 0.1U_ 04 02 _1 0V 7K
1 2
C F G 7
R6 8 3.01K_0 40 2_ 1%@
1 2
Onl y t emp or ary fo r e arl y C FD sa mples (rPGA/BGA)
PC I E_ CT X_G RX _N0 PC I E_ CT X_G RX _N1 PC I E_ CT X_G RX _N2 PC I E_ CT X_G RX _N3 PC I E_ CT X_G RX _N4 PC I E_ CT X_G RX _N5 PC I E_ CT X_G RX _N6 PC I E_ CT X_G RX _N7 PC I E_ CT X_G RX _N8 PC I E_ CT X_G RX _N9 PC I E_ CT X_G RX _N10 PC I E_ CT X_G RX _N11 PC I E_ CT X_G RX _N12 PC I E_ CT X_G RX _N13 PC I E_ CT X_G RX _N14 PC I E_ CT X_G RX _N15
PC I E_ CTX_GRX_ P0 PC I E_ CTX_GRX_ P1 PC I E_ CTX_GRX_ P2 PC I E_ CTX_GRX_ P3 PC I E_ CTX_GRX_ P4 PC I E_ CTX_GRX_ P5 PC I E_ CTX_GRX_ P6 PC I E_ CTX_GRX_ P7 PC I E_ CTX_GRX_ P8 PC I E_ CTX_GRX_ P9 PC I E_ CTX_GRX_ P1 0 PC I E_ CTX_GRX_ P1 1 PC I E_ CTX_GRX_ P1 2 PC I E_ CTX_GRX_ P1 3 PC I E_ CTX_GRX_ P1 4 PC I E_ CTX_GRX_ P1 5
3
+V _ DDR _ C PU _R EF0
+V _ DDR _ C PU _R EF1
200 9/0 7/2 1 HP SI-2
PC H _ DD R _ RST4,15
PC I E_ CTX_GRX_ N[ 0..15 ] 20
PC IE _C TX_ GR X_P [0 ..15] 20
Q88 AP2302GN_SO T23
D
S
1 3
G
2
D
S
1 3
AP 23 02 GN _S OT2 3 Q8 9
G
2
10 0K_ 04 02 _5%
10 0K_ 04 02 _5%
C F G04 C F G14 C F G24 C F G34 C F G44 C F G54 C F G64 C F G74 C F G84 C F G94 CF G 1 04 CF G 1 14 CF G 1 24 CF G 1 34 CF G 1 44 CF G 1 54 CF G 1 64 CF G 1 74
R6 5 0_ 0402_5%@
1 2
R6 6 0_ 0402_5%@
1 2
R1 22 0
R1 22 2
4
C F G 0 C F G 1 C F G 2 C F G 3 C F G 4 C F G 5 C F G 6 C F G 7 C F G 8 C F G 9 CF G 1 0 CF G 1 1 CF G 1 2 CF G 1 3 CF G 1 4 CF G 1 5 CF G 1 6 CF G 1 7 CF G 1 8
JC P U1E
AP25
RSVD1
AL25
RSVD2
AL24
RSVD3
AL22
RSVD4
AJ33
RSVD5
AG9
RSVD6
M27
RSVD7
L28
RSVD8
J17
SA_DIMM_VREF
H17
SB_DIMM_VREF
G25
RSVD11
G17
RSVD12
E31
RSVD13
E30
RSVD14
AM30
CFG[0]
AM28
CFG[1]
AP31
CFG[2]
AL32
CFG[3]
AL30
CFG[4]
AM31
CFG[5]
AN29
CFG[6]
AM32
CFG[7]
AK32
CFG[8]
AK31
CFG[9]
AK28
CFG[10]
AJ28
CFG[11]
AN30
CFG[12]
AN32
CFG[13]
AJ32
CFG[14]
AJ29
CFG[15]
AJ30
CFG[16]
AK30
CFG[17]
H16
RSVD_TP_86
B19
RSVD15
A19
RSVD16
A20
RSVD17
B20
RSVD18
U9
RSVD19
T9
RSVD20
AC9
RSVD21
AB9
RSVD22
C1
RSVD_NCTF_23
A3
RSVD_NCTF_24
J29
RSVD26
J28
RSVD27
A34
RSVD_NCTF_28
A33
RSVD_NCTF_29
C35
RSVD_NCTF_30
B35
RSVD_NCTF_31
IC , AUB _ CFD_rPGA ,R1P0
RESERVED
12
@
12
@
T22
C O N N@
RSVD32 RSVD33
RSVD34 RSVD35
RSVD36
RSVD_NCTF_37
RSVD38 RSVD39
RSVD_NCTF_40 RSVD_NCTF_41
RSVD_NCTF_42 RSVD_NCTF_43
RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52
RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57
RSVD58
RSVD_TP_59 RSVD_TP_60
RSVD62
RSVD63
RSVD64
RSVD65
RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75
RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85
AJ13 AJ12
AH25 AK26
AL26 AR2
AJ26 AJ27
AP1 AT2
AT3 AR1
AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32
E15 F15 A2
KEY
D15 C15
R6 0 0_ 0402_5%@
1 2
AJ15
R6 1 0_ 0402_5%@
AH15
1 2
AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3
V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9
AP34
VSS
5
200 9/0 2/1 9 HP DB-2
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
ARD/CFD(2/5)-DMI/PEG/FDI
LA- 4901P
5
5 54Tu e s da y, De ce mbe r 15 , 20 09
1. 0
1
2
3
4
5
AR10 AT10
J C PU1 D
B5
SB_DQ[0]
A5
SB_DQ[1]
C3
SB_DQ[2]
B3
SB_DQ[3]
E4
SB_DQ[4]
A6
SB_DQ[5]
A4
SB_DQ[6]
C4
SB_DQ[7]
D1
SB_DQ[8]
D2
SB_DQ[9]
F2
SB_DQ[10]
F1
SB_DQ[11]
C2
SB_DQ[12]
F5
SB_DQ[13]
F3
SB_DQ[14]
G4
SB_DQ[15]
H6
SB_DQ[16]
G2
SB_DQ[17]
J6
SB_DQ[18]
J3
SB_DQ[19]
G1
SB_DQ[20]
G5
SB_DQ[21]
J2
SB_DQ[22]
J1
SB_DQ[23]
J5
SB_DQ[24]
K2
SB_DQ[25]
L3
SB_DQ[26]
M1
SB_DQ[27]
K5
SB_DQ[28]
K4
SB_DQ[29]
M4
SB_DQ[30]
N5
SB_DQ[31]
AF3
SB_DQ[32]
AG1
SB_DQ[33]
AJ3
SB_DQ[34]
AK1
SB_DQ[35]
AG4
SB_DQ[36]
AG3
SB_DQ[37]
AJ4
SB_DQ[38]
AH4
SB_DQ[39]
AK3
SB_DQ[40]
AK4
SB_DQ[41]
AM6
SB_DQ[42]
AN2
SB_DQ[43]
AK5
SB_DQ[44]
AK2
SB_DQ[45]
AM4
SB_DQ[46]
AM3
SB_DQ[47]
AP3
SB_DQ[48]
AN5
SB_DQ[49]
AT4
SB_DQ[50]
AN6
SB_DQ[51]
AN4
SB_DQ[52]
AN3
SB_DQ[53]
AT5
SB_DQ[54]
AT6
SB_DQ[55]
AN7
SB_DQ[56]
AP6
SB_DQ[57]
AP8
SB_DQ[58]
AT9
SB_DQ[59]
AT7
SB_DQ[60]
AP9
SB_DQ[61] SB_DQ[62] SB_DQ[63]
AB1
SB_BS[0]
W5
SB_BS[1]
R7
SB_BS[2]
AC5
SB_CAS#
Y7
SB_RAS#
AC6
SB_WE#
DDR SYSTEM MEMORY - B
J C PU1 C
A A
DD R _ A_ D [0..6 3]9
B B
C C
DD R _ A_ BS09 DD R _ A_ BS19 DD R _ A_ BS29
DD R _ A_ C AS#9 DD R _ A_ R AS#9 DD R _ A_ W E#9
DD R _ A _D 0 DD R _ A _D 1 DD R _ A _D 2 DD R _ A _D 3 DD R _ A _D 4 DD R _ A _D 5 DD R _ A _D 6 DD R _ A _D 7 DD R _ A _D 8 DD R _ A _D 9 DD R _ A _D 10 DD R _ A _D 11 DD R _ A _D 12 DD R _ A _D 13 DD R _ A _D 14 DD R _ A _D 15 DD R _ A _D 16 DD R _ A _D 17 DD R _ A _D 18 DD R _ A _D 19 DD R _ A _D 20 DD R _ A _D 21 DD R _ A _D 22 DD R _ A _D 23 DD R _ A _D 24 DD R _ A _D 25 DD R _ A _D 26 DD R _ A _D 27 DD R _ A _D 28 DD R _ A _D 29 DD R _ A _D 30 DD R _ A _D 31 DD R _ A _D 32 DD R _ A _D 33 DD R _ A _D 34 DD R _ A _D 35 DD R _ A _D 36 DD R _ A _D 37 DD R _ A _D 38 DD R _ A _D 39 DD R _ A _D 40 DD R _ A _D 41 DD R _ A _D 42 DD R _ A _D 43 DD R _ A _D 44 DD R _ A _D 45 DD R _ A _D 46 DD R _ A _D 47 DD R _ A _D 48 DD R _ A _D 49 DD R _ A _D 50 DD R _ A _D 51 DD R _ A _D 52 DD R _ A _D 53 DD R _ A _D 54 DD R _ A _D 55 DD R _ A _D 56 DD R _ A _D 57 DD R _ A _D 58 DD R _ A _D 59 DD R _ A _D 60 DD R _ A _D 61 DD R _ A _D 62 DD R _ A _D 63
AJ10 AL10
AK12
AK11
AM10 AR11
AL11
AT11 AP12 AM12 AN12 AM13
AT14
AT12
AL13 AR14 AP14
A10
SA_DQ[0]
C10
SA_DQ[1]
C7
SA_DQ[2]
A7
SA_DQ[3]
B10
SA_DQ[4]
D10
SA_DQ[5]
E10
SA_DQ[6]
A8
SA_DQ[7]
D8
SA_DQ[8]
F10
SA_DQ[9]
E6
SA_DQ[10]
F7
SA_DQ[11]
E9
SA_DQ[12]
B7
SA_DQ[13]
E7
SA_DQ[14]
C6
SA_DQ[15]
H10
SA_DQ[16]
G8
SA_DQ[17]
K7
SA_DQ[18]
J8
SA_DQ[19]
G7
SA_DQ[20]
G10
SA_DQ[21]
J7
SA_DQ[22]
J10
SA_DQ[23]
L7
SA_DQ[24]
M6
SA_DQ[25]
M8
SA_DQ[26]
L9
SA_DQ[27]
L6
SA_DQ[28]
K8
SA_DQ[29]
N8
SA_DQ[30]
P9
SA_DQ[31]
AH5
SA_DQ[32]
AF5
SA_DQ[33]
AK6
SA_DQ[34]
AK7
SA_DQ[35]
AF6
SA_DQ[36]
AG5
SA_DQ[37]
AJ7
SA_DQ[38]
AJ6
SA_DQ[39] SA_DQ[40]
AJ9
SA_DQ[41] SA_DQ[42] SA_DQ[43]
AK8
SA_DQ[44]
AL7
SA_DQ[45] SA_DQ[46]
AL8
SA_DQ[47]
AN8
SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51]
AM9
SA_DQ[52]
AN9
SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]
AC3
SA_BS[0]
AB2
SA_BS[1]
U7
SA_BS[2]
AE1
SA_CAS#
AB3
SA_RAS#
AE9
SA_WE#
C O N N@
AA6
SA_CK[0]
AA7
SA_CK#[0]
P7
SA_CKE[0]
Y6
SA_CK[1]
Y5
SA_CK#[1]
P6
SA_CKE[1]
AE2
SA_CS#[0]
AE8
SA_CS#[1]
AD8
SA_ODT[0]
AF9
SA_ODT[1]
DD R _ A _D M0
B9
SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]
SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]
SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]
DDR SYSTEM MEMORY A
SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]
SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]
D7 H7 M7 AG6 AM7 AN10 AN13
C9 F8 J9 N9 AH7 AK9 AP11 AT13
C8 F9 H9 M9 AH8 AK10 AN11 AR13
Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9
DD R _ A _D M1 DD R _ A _D M2 DD R _ A _D M3 DD R _ A _D M4 DD R _ A _D M5 DD R _ A _D M6 DD R _ A _D M7
DD R _ A_ DQS#0 DD R _ A_ DQS#1 DD R _ A_ DQS#2 DD R _ A_ DQS#3 DD R _ A_ DQS#4 DD R _ A_ DQS#5 DD R _ A_ DQS#6 DD R _ A_ DQS#7
DD R _ A_ DQS0 DD R _ A_ DQS1 DD R _ A_ DQS2 DD R _ A_ DQS3 DD R _ A_ DQS4 DD R _ A_ DQS5 DD R _ A_ DQS6 DD R _ A_ DQS7
DD R _ A _MA 0 DD R _ A _MA 1 DD R _ A _MA 2 DD R _ A _MA 3 DD R _ A _MA 4 DD R _ A _MA 5 DD R _ A _MA 6 DD R _ A _MA 7 DD R _ A _MA 8 DD R _ A _MA 9 DD R _ A_ MA1 0 DD R _ A_ MA1 1 DD R _ A_ MA1 2 DD R _ A_ MA1 3 DD R _ A_ MA1 4 DD R _ A_ MA1 5
M_ C L K_ DD R0 9 M_ C L K_ DD R#0 9 DD R _ CK E 0 _DIMMA 9
M_ C L K_ DD R1 9 M_ C L K_ DD R#1 9 DD R _ CK E 1 _DIMMA 9
DD R _ CS 0 _D IMMA# 9 DD R _ CS 1 _D IMMA# 9
M_ ODT0 9 M_ ODT1 9
DD R _ A_ D M[0 .. 7] 9
DD R _ A_ D QS# [0 .. 7] 9
DD R _ A_ D QS [0 ..7] 9
DD R _ A_ MA[ 0. .1 5] 9
DD R _ B_ D [0..6 3]10
DD R _ B_ BS010 DD R _ B_ BS110 DD R _ B_ BS210
DD R _ B_ C AS #10 DD R _ B_ R AS #10 DD R _ B_ W E#10
DD R _ B _D 0 DD R _ B _D 1 DD R _ B _D 2 DD R _ B _D 3 DD R _ B _D 4 DD R _ B _D 5 DD R _ B _D 6 DD R _ B _D 7 DD R _ B _D 8 DD R _ B _D 9 DD R _ B _D 10 DD R _ B _D 11 DD R _ B _D 12 DD R _ B _D 13 DD R _ B _D 14 DD R _ B _D 15 DD R _ B _D 16 DD R _ B _D 17 DD R _ B _D 18 DD R _ B _D 19 DD R _ B _D 20 DD R _ B _D 21 DD R _ B _D 22 DD R _ B _D 23 DD R _ B _D 24 DD R _ B _D 25 DD R _ B _D 26 DD R _ B _D 27 DD R _ B _D 28 DD R _ B _D 29 DD R _ B _D 30 DD R _ B _D 31 DD R _ B _D 32 DD R _ B _D 33 DD R _ B _D 34 DD R _ B _D 35 DD R _ B _D 36 DD R _ B _D 37 DD R _ B _D 38 DD R _ B _D 39 DD R _ B _D 40 DD R _ B _D 41 DD R _ B _D 42 DD R _ B _D 43 DD R _ B _D 44 DD R _ B _D 45 DD R _ B _D 46 DD R _ B _D 47 DD R _ B _D 48 DD R _ B _D 49 DD R _ B _D 50 DD R _ B _D 51 DD R _ B _D 52 DD R _ B _D 53 DD R _ B _D 54 DD R _ B _D 55 DD R _ B _D 56 DD R _ B _D 57 DD R _ B _D 58 DD R _ B _D 59 DD R _ B _D 60 DD R _ B _D 61 DD R _ B _D 62 DD R _ B _D 63
C O N N@
SB_CK[0] SB_CK#[0] SB_CKE[0]
SB_CK[1] SB_CK#[1] SB_CKE[1]
SB_CS#[0] SB_CS#[1]
SB_ODT[0] SB_ODT[1]
SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]
SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]
SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]
W8 W9 M3
V7 V6 M2
AB8 AD6
AC7 AD1
D4 E1 H3 K1 AH1 AL2 AR4 AT8
D5 F4 J4 L4 AH2 AL4 AR5 AR8
C5 E3 H4 M5 AG2 AL5 AP5 AR7
U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1
DD R _ B _D M0 DD R _ B _D M1 DD R _ B _D M2 DD R _ B _D M3 DD R _ B _D M4 DD R _ B _D M5 DD R _ B _D M6 DD R _ B _D M7
DD R _ B_ DQS#0 DD R _ B_ DQS#1 DD R _ B_ DQS#2 DD R _ B_ DQS#3 DD R _ B_ DQS#4 DD R _ B_ DQS#5 DD R _ B_ DQS#6 DD R _ B_ DQS#7
DD R _ B_ DQS0 DD R _ B_ DQS1 DD R _ B_ DQS2 DD R _ B_ DQS3 DD R _ B_ DQS4 DD R _ B_ DQS5 DD R _ B_ DQS6 DD R _ B_ DQS7
DD R _ B _MA 0 DD R _ B _MA 1 DD R _ B _MA 2 DD R _ B _MA 3 DD R _ B _MA 4 DD R _ B _MA 5 DD R _ B _MA 6 DD R _ B _MA 7 DD R _ B _MA 8 DD R _ B _MA 9 DD R _ B_ MA1 0 DD R _ B_ MA1 1 DD R _ B_ MA1 2 DD R _ B_ MA1 3 DD R _ B_ MA1 4 DD R _ B_ MA1 5
M_ C L K_ DD R2 10 M_ C L K_ DD R#2 10 DD R _ CK E 2 _DIMMB 10
M_ C L K_ DD R3 10 M_ C L K_ DD R#3 10 DD R _ CK E 3 _DIMMB 10
DD R _ CS 2 _D IMMB# 10 DD R _ CS 3 _D IMMB# 10
M_ ODT2 10 M_ ODT3 10
DD R _ B_ D M[0 .. 7] 10
DD R _ B_ D QS# [0 .. 7] 10
DD R _ B_ D QS [0 ..7] 10
DD R _ B_ MA[ 0. .1 5] 10
IC , AUB _ CFD _r PG A,R1P 0
IC , AUB _ CFD _r PG A,R1P 0
D D
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
ARD/CFD(3/5)-DDR3
LA -490 1 P
5
6 54Tu e s da y, De ce mbe r 15 , 20 09
1. 0
1
+C P U_C ORE
J C PU1 F
C O N N @
45W
52A
AG35
A A
B B
C C
D D
VCC1
AG34
VCC2
AG33
VCC3
AG32
VCC4
AG31
VCC5
AG30
VCC6
AG29
VCC7
AG28
VCC8
AG27
VCC9
AG26
VCC10
AF35
VCC11
AF34
VCC12
AF33
VCC13
AF32
VCC14
AF31
VCC15
AF30
VCC16
AF29
VCC17
AF28
VCC18
AF27
VCC19
AF26
VCC20
AD35
VCC21
AD34
VCC22
AD33
VCC23
AD32
VCC24
AD31
VCC25
AD30
VCC26
AD29
VCC27
AD28
VCC28
AD27
VCC29
AD26
VCC30
AC35
VCC31
AC34
VCC32
AC33
VCC33
AC32
VCC34
AC31
VCC35
AC30
VCC36
AC29
VCC37
AC28
VCC38
AC27
VCC39
AC26
VCC40
AA35
VCC41
AA34
VCC42
AA33
VCC43
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
IC , AUB _ CFD _r PG A,R1P 0
CPU CORE SUPPLY
POWER
1.1V RAIL POWER
CPU VIDS
SENSE LINES
18A
VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8
VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32
VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44
PSI#
VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]
PROC_DPRSLPVR
VTT_SELECT
ISENSE
VCC_SENSE VSS_SENSE
VTT_SENSE
VSS_SENSE_VTT
AH14 AH12 AH11 AH10
1 J14 J13 H14
2
H12 G14 G13 G12 G11 F14 F13
1 F12 F11 E14
2
E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11
AF10 AE10 AC10 AB10
1 Y10 W10 U10
2
T10 J12 J11 J16 J15
AN33
H_ V I D0
AK35
H_ V I D1
AK33
H_ V I D2
AK34
H_ V I D3
AL35
H_ V I D4
AL33
H_ V I D5
AM33
H_ V I D6
AM35
PM _ DP R S LP VR_ R
AM34
G15
H_VTTVID1 = Low, 1.1V H_VTTVID1 = High, 1.05V
AN35
R7 5 0_ 0402_5%
1 2
AJ34 AJ35
1 2
R7 6 0_ 0402_5%
B15 A15
Close to CPU
VC C SE N SE VS S SE N SE
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C3 8
C3 7
1
2
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C4 5
C4 6
1
2
+V C CP
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C5 7
C5 6
1
2
1 2
R7 4 0_ 0402_5%
1 2
R7 7 10 0_0402_1%
1 2
R7 8 10 0_0402_1%
+V C CP
1
2
1
2
PS I# 46 H_ V I D[0 .. 6] 46
H_ V TTV ID1 43
IM V P_ IMO N 46
VT T_ SENSE 43 VS S _S ENSE_ VTT 43
22 U_0805_6.3V 6M
C4 0
22 U_0805_6.3V 6M
C4 8
VC C SE N SE VS S SE N SE
2
+C P U_C ORE
PR O C _D P R SL PVR 46
VC C SE N SE 46 VS S SE N SE 46
+V C CP
C4 1
@
CPU
3
+C P U_C ORE
47 P_0 40 2_ 50 V8J
1
2
47 P_0 40 2_ 50 V8J
47 P_0 40 2_ 50 V8J
C4 2
1
@
2
47 P_0 40 2_ 50 V8J
C4 3
C4 4
1
1
@
@
2
2
47 P_0 40 2_ 50 V8J
47 P_0 40 2_ 50 V8J
C6 0
C5 9
1
1
@
@
2
2
C6 1
1
@
2
47 P_0 40 2_ 50 V8J
C6 2
1
@
2
200 9/0 7/2 2 HP SI-2
47 P_0 40 2_ 50 V8J
+V C CP
10 U_0805_6.3V 6M
22 U_0805_6.3V 6M
C6 8
1
2
+V C CP
1
2
C6 9
1
2
22 U_0805_6.3V 6M
22 U_0805_6.3V 6M
C7 4
C7 5
1
2
JC P U1G
AT21
VAXG1
AT19
VAXG2
AT18
VAXG3
AT16
VAXG4
AR21
VAXG5
AR19
VAXG6
AR18
VAXG7
AR16
VAXG8
AP21
VAXG9
AP19
VAXG10
AP18
VAXG11
AP16
VAXG12
AN21
VAXG13
AN19
VAXG14
AN18
VAXG15
AN16
VAXG16
AM21
VAXG17
AM19
VAXG18
AM18
VAXG19
AM16
VAXG20
AL21
VAXG21
AL19
VAXG22
AL18
VAXG23
AL16
VAXG24
AK21
VAXG25
AK19
VAXG26
AK18
VAXG27
AK16
VAXG28
AJ21
VAXG29
AJ19
VAXG30
AJ18
VAXG31
AJ16
VAXG32
AH21
VAXG33
AH19
VAXG34
AH18
VAXG35
AH16
VAXG36
J24
VTT1_45
J23
VTT1_46
H25
VTT1_47
K26
VTT1_48
J27
VTT1_49
J26
VTT1_50
J25
VTT1_51
H27
VTT1_52
G28
VTT1_53
G27
VTT1_54
G26
VTT1_55
F26
VTT1_56
E26
VTT1_57
E25
VTT1_58
IC , AUB _ CFD_rPGA ,R1P0
4
C O N N @
GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]
GFX_VR_EN
GFX_IMON
AR22 AT22
AM22 AP22 AN22 AP23 AM23 AP24 AN24
AR25 AT25
R7 1 1K_ 04 02 _5 %
AM24
15A
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
GRAPHICS
GFX_DPRSLPVR
GRAPHICS VIDs
AJ1
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8
6A
FDI PEG & DMI
POWER
1.1A
VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18
DDR3 - 1.5V RAILS
VTT0_59 VTT0_60 VTT0_61 VTT0_62
VTT1_63 VTT1_64 VTT1_65
1.1V1.8V
VTT1_66 VTT1_67 VTT1_68
VCCPLL1 VCCPLL2 VCCPLL3
1U _0 60 3_ 10 V4 Z
AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1
P10 N10 L10 K10
J22 J20 J18 H21 H20 H19
L26 L27 M26
C5 0
1
2
33 0 U _D 2_ 2V Y_R 7M
C6 3
1
+
2
1U _0 60 3_ 10 V4 Z
C7 8
1
1
2
2
5
12
+1 . 5 V_ C PU_ VD DQ
200 9/0 7/0 2 HP SI-2
1U _0 60 3_ 10 V4 Z
1U _0 60 3_ 10 V4 Z
1
2
10 U_0805_6.3V 6M
1
2
1U _0 60 3_ 10 V4 Z
C7 9
1
2
1U _0 60 3_ 10 V4 Z
1U _0 60 3_ 10 V4 Z
C5 1
C5 2
1
2
10 U_0805_6.3V 6M
C6 5
C6 4
1
2
+V C CP
22 U_0805_6.3V 6M
C7 0
1
2
2. 2 U_ 06 03 _6 .3V4Z C8 0
1
2
C5 4
C5 3
1
1
2
2
22 U_0805_6.3V 6M
C7 1
1
2
+V C CP
10 U_0805_6.3V 6M
C7 7
1
2
+1 .8 VS
4. 7U _0 60 3_ 6. 3V6K
10 U_0805_6.3V 6M
C8 2
C8 1
1
2
+1.5V to +1.5V_CPU_VDDQ Transfer
SIS 40 6DN-T1- GE3_PAK1212-8-5
Q9 1
5
C9 94
0.1U_ 04 02 _1 0V 6K R1 22 4
1
1 2
0_ 0402_5%
2
R U NO N
4
+1 . 5 V_ C PU_ VD DQ+1 .5 V
1 2 3
R U N O N 38
200 9/0 7/0 2 HP SI-1b200 9/0 7/2 1 HP SI-2
C9 91 0.1U_ 04 02 _1 0V 6K
1 2
C9 92 0.1U_ 04 02 _1 0V 6K
C9 95
0.1U_ 04 02 _1 0V 6K
1
2
Sti ch CAP b etw een 1. 5V and 1 .5V-CPU_VDDQ
1 2
C9 93 0.1U_ 04 02 _1 0V 6K
1 2
C9 96 0.1U_ 04 02 _1 0V 6K
1 2
+1 . 5 V_ C PU_ VD DQ+1 .5 V
SL P_S338
+1 . 5 V_ C PU_ VD DQ
S LP_ S3
2
G
12
R1 22 3 51 0_0402_5%
13
D
Q92 SS M3 K7002F_ SC5 9- 3
S
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
ARD/CFD(4/5)-PWR
LA -490 1 P
5
7 54Tu e s da y, De ce mbe r 15 , 20 09
1. 0
1
J C PU1 H
AT20
VSS1
AT17
VSS2
AR31
VSS3
AR28
VSS4
AR26
VSS5
AR24
VSS6
AR23
VSS7
AR20
VSS8
AR17
A A
B B
C C
VSS9
AR15
VSS10
AR12
VSS11
AR9
VSS12
AR6
VSS13
AR3
VSS14
AP20
VSS15
AP17
VSS16
AP13
VSS17
AP10
VSS18
AP7
VSS19
AP4
VSS20
AP2
VSS21
AN34
VSS22
AN31
VSS23
AN23
VSS24
AN20
VSS25
AN17
VSS26
AM29
VSS27
AM27
VSS28
AM25
VSS29
AM20
VSS30
AM17
VSS31
AM14
VSS32
AM11
VSS33
AM8
VSS34
AM5
VSS35
AM2
VSS36
AL34
VSS37
AL31
VSS38
AL23
VSS39
AL20
VSS40
AL17
VSS41
AL12
VSS42
AL9
VSS43
AL6
VSS44
AL3
VSS45
AK29
VSS46
AK27
VSS47
AK25
VSS48
AK20
VSS49
AK17
VSS50
AJ31
VSS51
AJ23
VSS52
AJ20
VSS53
AJ17
VSS54
AJ14
VSS55
AJ11
VSS56
AJ8
VSS57
AJ5
VSS58
AJ2
VSS59
AH35
VSS60
AH34
VSS61
AH33
VSS62
AH32
VSS63
AH31
VSS64
AH30
VSS65
AH29
VSS66
AH28
VSS67
AH27
VSS68
AH26
VSS69
AH20
VSS70
AH17
VSS71
AH13
VSS72
AH9
VSS73
AH6
VSS74
AH3
VSS75
AG10
VSS76
AF8
VSS77
AF4
VSS78
AF2
VSS79
AE35
VSS80
IC , AUB _ CFD _r PG A,R1P 0
VSS
C O N N@
VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160
AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30
2
JC P U1I
K27
VSS161
K9
VSS162
K6
VSS163
K3
VSS164
J32
VSS165
J30
VSS166
J21
VSS167
J19
VSS168
H35
VSS169
H32
VSS170
H28
VSS171
H26
VSS172
H24
VSS173
H22
VSS174
H18
VSS175
H15
VSS176
H13
VSS177
H11
VSS178
H8
VSS179
H5
VSS180
H2
VSS181
G34
VSS182
G31
VSS183
G20
VSS184
G9
VSS185
G6
VSS186
G3
VSS187
F30
VSS188
F27
VSS189
F25
VSS190
F22
VSS191
F19
VSS192
F16
VSS193
E35
VSS194
E32
VSS195
E29
VSS196
E24
VSS197
E21
VSS198
E18
VSS199
E13
VSS200
E11
VSS201
E8
VSS202
E5
VSS203
E2
VSS204
D33
VSS205
D30
VSS206
D26
VSS207
D9
VSS208
D6
VSS209
D3
VSS210
C34
VSS211
C32
VSS212
C29
VSS213
C28
VSS214
C24
VSS215
C22
VSS216
C20
VSS217
C19
VSS218
C16
VSS219
B31
VSS220
B25
VSS221
B21
VSS222
B18
VSS223
B17
VSS224
B13
VSS225
B11
VSS226
B8
VSS227
B6
VSS228
B4
VSS229
A29
VSS230
A27
VSS231
A23
VSS232
A9
VSS233
IC , AUB _ CFD _r PG A,R1P 0
VSS
C O N N@
3
+C P U_C ORE
@
CPU CORE
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C8 3
1
2
1
2
1
2
C8 4
1
2
22 U_0805_6.3V 6M
22 U_0805_6.3V 6M
C9 7 4
C9 7 1
1
2
22 U_0805_6.3V 6M
22 U_0805_6.3V 6M
C1 11
C9 6
1
@
@
2
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C8 6
C8 5
1
1
2
2
between Inductor and socket
22 U_0805_6.3V 6M
22 U_0805_6.3V 6M
C8 8
1
2
1
2
C9 3
1
2
22 U_0805_6.3V 6M
22 U_0805_6.3V 6M
C9 75
C9 7
1
@
2
10 U_0805_6.3V 6M
1
2
22 U_0805_6.3V 6M
1
2
22 U_0805_6.3V 6M
1
@
2
Inside cavity
10 U_0805_6.3V 6M
C8 7
C8 9
1
2
10 U_0805_6.3V 6M
C1 0 0
C9 7 0
1
2
22 U_0805_6.3V 6M
C9 69
C9 76
1
@
2
@
4
10 U_0805_6.3V 6M
C9 0
1
2
10 U_0805_6.3V 6M
C1 0 2
1
2
22 U_0805_6.3V 6M
C1 04
1
@
2
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C9 1
1
2
10 U_0805_6.3V 6M
C9 5
1
2
22 U_0805_6.3V 6M
C9 73
1
2
10 U_0805_6.3V 6M
C9 2
1
2
1
2
1
2
C9 4
1
2
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C9 8
C9 9
1
2
22 U_0805_6.3V 6M
22 U_0805_6.3V 6M
C1 13
C1 12
1
2
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C1 17
C1 14
1
1
2
2
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C1 0 1
1
2
1
2
C1 2 0
1
2
22 U_0805_6.3V 6M
22 U_0805_6.3V 6M
C1 15
C1 16
1
2
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C1 19
C1 18
1
1
2
2
10 U_0805_6.3V 6M
C1 0 3
1
2
33 0 U_D2 _2 .5 VM_ R6 M
22 U_0805_6.3V 6M
C1 05
C9 77
1
1
+
2
2
5
33 0 U_D2 _2 .5 VM_ R6 M
33 0 U_D2 _2 .5 VM_ R6 M
33 0 U_D2 _2 .5 VM_ R6 M
C1 07
C1 09
1
1
+
+
2
2
47 0 U_D2 _2 VM_R4 .5 M
C1 08
1
+
2
C1 06
1
+
@
2
Under cavity
10 0K_ 04 02 _5 %
10 0K_ 04 02 _5 %
10 0K_ 04 02 _5 %
10 0K_ 04 02 _5 %
VS S _N C TF7_ R
+3 VS
12
R7 9
61
Q2 A 2N 7 002DWH _SOT3 63 -6
2
+3 VS
12
R8 0
5
+3 VS
12
R8 1
2
+3 VS
12
R8 2
5
CR A CK_ B GA
34
Q2 B 2N 7 002DWH _SOT3 63 -6
CR A CK_ B GA
61
Q5 A 2N 7 002DWH _SOT3 63 -6
CR A CK_ B GA
34
Q5 B 2N 7 002DWH _SOT3 63 -6
CR A CK_ BG A 17 ,3 5
VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7
NCTF
AT1 AR34 B34 B2 B1 A35
VS S _N C TF2_ R VS S _N C TF3_ R VS S _N C TF4_ R VS S _N C TF5_ R VS S _N C TF6_ R VS S _N C TF7_ R
T23 T24 T25
VS S _N C TF2_ R
VS S _N C TF1_ R
VS S _N C TF6_ R
VS S _N C TF1_ R
AT35
BGA Ball Cracking Prevention and Detection
D D
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
ARD/CFD(5/5)-GND/Bypass
LA -490 1 P
5
8 54Tu e s da y, De ce mbe r 15 , 20 09
1. 0
1
+V R EF _ DQ_DIM MA
2.2U_ 06 03 _6 .3 V6 K
0. 1U _0 40 2_ 16 V4Z C1 2 1
1
1
2
A A
B B
C C
2
DD R _ CK E 0 _DIMMA6
DD R _ A_ BS26
M_ C L K_ DD R06 M_ C L K_ DD R#06
DD R _ A_ BS06 DD R _ A_ W E#6
DD R _ A_ C AS#6
DD R _ CS 1 _D IMMA#6
200 9/0 2/1 6 HP DB-2
+3 VS
1
2
D D
+V R EF _ D Q_ DI MMA DD R _ A _D 0
C1 2 2
DD R _ A _D 1 DD R _ A _D M0 DD R _ A _D 2
DD R _ A _D 3 DD R _ A _D 8
DD R _ A _D 9 DD R _ A_ DQS#1
DD R _ A_ DQS1 DD R _ A _D 10
DD R _ A _D 11 DD R _ A _D 16
DD R _ A _D 17 DD R _ A_ DQS#2
DD R _ A_ DQS2 DD R _ A _D 18
DD R _ A _D 19 DD R _ A _D 24
DD R _ A _D 25 DD R _ A _D M3 DD R _ A _D 26
DD R _ A _D 27
DD R _ CK E 0 _DIMMA
DD R _ A _BS2 DD R _ A_ MA1 2
DD R _ A _MA 9 DD R _A_MA8
DD R _ A _MA 5 DD R _ A _MA 3
DD R _ A _MA 1 M_ C L K _DDR0
M_ C L K _DDR# 0 DD R _ A_ MA1 0
DD R _ A _BS0 DD R _ A_ WE#
DD R _ A_ CAS # M_ O DT0 DD R _ A_ MA1 3
DD R _ CS 1 _ DI MMA#
DD R _ A _D 32 DD R _ A _D 33
DD R _ A_ DQS#4 DD R _ A_ DQS4
DD R _ A _D 34 DD R _ A _D 35
DD R _ A _D 40 DD R _ A _D 41
DD R _ A _D M5 DD R _ A _D 42
DD R _ A _D 43 DD R _ A _D 48
DD R _ A _D 49 DD R _ A_ DQS#6
DD R _ A_ DQS6 DD R _ A _D 50
DD R _ A _D 51 DD R _ A _D 56
DD R _ A _D 57 DD R _ A _D M7 DD R _ A _D 58
DD R _ A _D 59
R8 7 10 K_0 40 2_ 5%
1 2
2.2U_ 04 02 _6 .3 V6 M
0. 1U _0 40 2_ 16 V4Z
C1 43
C1 44
1
2
+1. 5V + 1. 5V
3A @ 1
3A @ 1. 5V
.5V
3A @ 13A @ 1
.5V.5V
DDR3 SO-DIMM A
JD I MA 1
C O N N @
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1 VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9 VSS925VSS10
27
DQS#1 DQS129RESET# VSS1131VSS12
33
DQ10
35
DQ11 VSS1337VSS14
39
DQ16
41
DQ17 VSS1543VSS16
45
DQS#2 DQS247VSS17 VSS1849DQ22
51
DQ18 DQ1953VSS19 VSS2055DQ28
57
DQ24 DQ2559VSS21 VSS2261DQS#3
63
DM3 VSS2365VSS24
67
DQ26
69
DQ27 VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3 A12/BC#83A11
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1 VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
10 K_0 40 2_ 5%
R8 8
12
VTT1
205
G1
FO X _AS0 A626-U2 RN -7 F
VSS3 DQS0
VSS6
VSS8 DQ12 DQ13
DM1
DQ14 DQ15
DQ20 DQ21
DM2
DQ23
DQ29
DQS3 DQ30
DQ31
CKE1 VDD2
VDD4
VDD6
VDD8
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30
DM4
VSS31
DQ38 DQ39
VSS33
DQ44 DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46 DQ47
VSS40
DQ52 DQ53
VSS42
DM6
VSS43
DQ54 DQ55
VSS45
DQ60 DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62 DQ63
VSS52
EVENT#
SDA
VTT2
DQ4 DQ5
DQ6 DQ7
A15 A14
A7 A6
A4 A2
A0
CK1
BA1
S0#
NC2
SCL
G2
TOP SLOT
Reserved
1
2
2
DD R _ A _D 4
4
DD R _ A _D 5
6 8
DD R _ A_ DQS#0
10
DD R _ A_ DQS0
12 14
DD R _ A _D 6
16
DD R _ A _D 7
18 20
DD R _ A _D 12
22
DD R _ A _D 13
24 26
DD R _ A _D M1
28
DR A MR S T#
30 32
DD R _ A _D 14
34
DD R _ A _D 15
36 38
DD R _ A _D 20
40
DD R _ A _D 21
42 44
DD R _ A _D M2
46 48
DD R _ A _D 22
50
DD R _ A _D 23
52 54
DD R _ A _D 28
56
DD R _ A _D 29
58 60
DD R _ A_ DQS#3
62
DD R _ A_ DQS3
64 66
DD R _ A _D 30
68
DD R _ A _D 31
70 72
DD R _ CK E 1 _DIMMA
74 76
DD R _ A_ MA1 5
78
DD R _ A_ MA1 4
80 82
DDR_A_MA11
84
DD R _ A _MA 7
86 88
DD R _A_MA6
90
DD R _ A _MA 4
92 94
DD R _ A _MA 2
96
DD R _ A _MA 0
98 100
M_ C L K _DDR1
102
M_ C L K _DDR# 1
104 106
DD R _ A _BS1
108
DD R _ A_ RAS #
110 112
DD R _ CS 0 _ DI MMA#
114 116 118
M_ O DT1
120 122 124
+V R EF _ CA
126 128
DD R _ A _D 36
130
DD R _ A _D 37
132 134
DD R _ A _D M4
136 138
DD R _ A _D 38
140
DD R _ A _D 39
142 144
DD R _ A _D 44
146
DD R _ A _D 45
148 150
DD R _ A_ DQS#5
152
DD R _ A_ DQS5
154 156
DD R _ A _D 46
158
DD R _ A _D 47
160 162
DD R _ A _D 52
164
DD R _ A _D 53
166 168
DD R _ A _D M6
170 172
DD R _ A _D 54
174
DD R _ A _D 55
176 178
DD R _ A _D 60
180
DD R _ A _D 61
182 184
DD R _ A_ DQS#7
186
DD R _ A_ DQS7
188 190
DD R _ A _D 62
192
DD R _ A _D 63
194 196
P M_E XTTS#1 _R
198
SM B _D ATA _S3
200
SM B _C LK_S3
202 204
206
+0. 75 V
0. 6 5A
0. 6 5A @0 .75 V
@0. 75V
0. 6 5A0. 6 5A
@0. 75V@0. 75V
SM B _D ATA _S3 SM B _C LK_S3
+0 .7 5VS
For ME/iAMT debug
2
DR A MR ST # 4, 10
DD R _ CK E 1 _DIMMA 6
M_ C L K_ DD R1 6 M_ C L K_ DD R#1 6
DD R _ A_ BS1 6 DD R _ A_ R AS# 6
DD R _ CS 0 _D IMMA# 6 M_ ODT0 6
M_ ODT1 6
0. 1U _0 40 2_ 16 V4Z C1 41
1
2
PM_EX TTS# 1_ R 4, 10 SM B_D ATA _S3 4,1 0,11,13,32 SM B_CL K_ S3 4 ,10,11,13 ,32
JP 20
3
3
G2
2
2
G1
1
1
ACE S_85204 -030 01
C O N N@
1
+V R EF _CA
2.2U_ 06 03 _6 .3 V6 K C1 42
3
R8 3 1K_ 04 02 _1 %
R8 4 1K_ 04 02 _1 %
+1 .5 V
12
+V _ DDR _ C PU _ REFA
12
+V R EF _ DQ_DIM MA +V _ DDR _ C PU _ REFA
DD R _ A_ D[ 0. .63]6 DD R _ A_ D M[0 .. 7]6 DD R _ A_ D QS[ 0. .7 ]6 DD R _ A_ D QS# [0 .. 7]6 DD R _ A_ MA[ 0. .1 5]6
+1. 5V
12
R1 18 2 1K_ 04 02 _1 %
12
R1 18 3 1K_ 04 02 _1 %
200 9/0 4/1 0 HP DB-3
4
R9 91 0_0402_5%
1 2
200 9/0 4/1 0 HP DB-3
R8 6 0_ 0402_5%
1 2
200 9/0 4/1 0 HP DB-3
5
+V _ DDR _ C PU _R EF0
2
Layout Note: Pl ace near JDIMMA
+1. 5V
10 U_0603_6.3V 6M
10 U_0603_6.3V 6M
C1 2 6
1
2
5 4
Security Classification
Issued Date
3
10 U_0603_6.3V 6M
C1 2 7
1
2
10 U_0603_6.3V 6M
C1 2 8
1
2
C1 2 9
1
2
2008/09/15 2009/12/31
10 U_0603_6.3V 6M
10 U_0603_6.3V 6M
C1 3 0
1
1
2
2
Compal Secret Data
0. 1U _0 40 2_ 16 V4Z
C1 3 1
C1 3 2
1
@
2
Deciphered Date
4
@
0. 1U _0 40 2_ 16 V4Z
0. 1U _0 40 2_ 16 V4Z C1 3 3
1
@
2
0. 1U _0 40 2_ 16 V4Z
C1 3 4
C1 3 5
1
2
1
1
+
@
@
2
2
Layout Note: Place near JDIMMA.203 & JDIMMA.204
+0 .7 5VS
C1 40
C1 37
1U_0402_6.3 V6 K
C1 36
1U_0402_6.3 V6 K
C1 23
33 0 U _ D2 _2 VY_ R7 M
1
2
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
C1 38
1U_0402_6.3 V6 K
1
1
2
2
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
LA -490 1 P
10 U_0603_6.3V 6M
C1 39
1U_0402_6.3 V6 K
1
1
2
2
5
C1 24
10 U_0603_6.3V 6M
C1 25
10 U_0603_6.3V 6M
1
1
2
2
200 9/0 4/2 4 HP SI-1
9 54Tu e s da y, De ce mbe r 15 , 20 09
1. 0
1
+V R EF _ DQ_DIM MB
0. 1U _0 40 2_ 16 V4Z
2.2U_ 06 03 _6 .3 V6 K
1
1
C1 45
2
+3 VS
2
DD R _ CK E 2 _DIMMB6
DD R _ B_ BS26
M_ C L K_ DD R26 M_ C L K_ DD R#26
DD R _ B_ BS06 DD R _ B_ W E#6
DD R _ B_ C AS#6
DD R _ CS 3 _D IMMB#6
2.2U_ 04 02 _6 .3 V6 M
1
A A
B B
C C
200 9/0 2/1 6 HP DB-2
2
D D
+V R EF _ D Q_ DI MMB DD R _ B _D 0
DD R _ B _D 1
C1 46
DD R _ B _D M0 DD R _ B _D 2
DD R _ B _D 3 DD R _ B _D 8
DD R _ B _D 9 DD R _ B_ DQS#1
DD R _ B_ DQS1 DD R _ B _D 10
DD R _ B _D 11 DD R _ B _D 16
DD R _ B _D 17 DD R _ B_ DQS#2
DD R _ B_ DQS2 DD R _ B _D 18
DD R _ B _D 19 DD R _ B _D 24
DD R _ B _D 25 DD R _ B _D M3 DD R _ B _D 26
DD R _ B _D 27
DD R _ CK E 2 _DIMMB
DD R _ B _BS2 DD R _ B_ MA1 2
DD R _ B _MA 9 DDR_B_MA8
DD R _ B _MA 5 DD R _ B _MA 3
DD R _ B _MA 1 M_ C L K _DDR2
M_ C L K _DDR# 2 DD R _ B_ MA1 0
DD R _ B _BS0 DD R _ B_ WE#
DD R _ B_ CAS # M_ O DT2 DD R _ B_ MA1 3
DD R _ CS 3 _ DI MMB#
DD R _ B _D 32 DD R _ B _D 33
DD R _ B_ DQS#4 DD R _ B_ DQS4
DD R _ B _D 34 DD R _ B _D 35
DD R _ B _D 40 DD R _ B _D 41
DD R _ B _D M5 DD R _ B _D 42
DD R _ B _D 43 DD R _ B _D 48
DD R _ B _D 49 DD R _ B_ DQS#6
DD R _ B_ DQS6 DD R _ B _D 50
DD R _ B _D 51 DD R _ B _D 56
DD R _ B _D 57 DD R _ B _D M7 DD R _ B _D 58
DD R _ B _D 59
R9 1
1 2
10 K_0 40 2_ 5%
0. 1U _0 40 2_ 16 V4Z C1 66
C1 65
1
1 2
R9 2 10K_0402_5%
2
DDR3 SO-DIMM B
+1. 5V + 1. 5V
REVERSE
3A @ 1
3A @ 1. 5V
.5V
3A @ 13A @ 1
.5V.5V
C O N N @
JD I MB 1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1 VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9 VSS925VSS10
27
DQS#1 DQS129RESET# VSS1131VSS12
33
DQ10
35
DQ11 VSS1337VSS14
39
DQ16
41
DQ17 VSS1543VSS16
45
DQS#2 DQS247VSS17 VSS1849DQ22
51
DQ18 DQ1953VSS19 VSS2055DQ28
57
DQ24 DQ2559VSS21 VSS2261DQS#3
63
DM3 VSS2365VSS24
67
DQ26
69
DQ27 VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3 A12/BC#83A11
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1 VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
+0. 75 V
VSS3 DQS0
VSS6
VSS8 DQ12 DQ13
DM1
DQ14 DQ15
DQ20 DQ21
DM2
DQ23
DQ29
DQS3 DQ30
DQ31
CKE1 VDD2
VDD4
VDD6
VDD8
CK1
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30
DM4
VSS31
DQ38 DQ39
VSS33
DQ44 DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46 DQ47
VSS40
DQ52 DQ53
VSS42
DM6
VSS43
DQ54 DQ55
VSS45
DQ60 DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62 DQ63
VSS52
EVENT#
SDA SCL
VTT2
2
DD R _ B_ D QS# [0 .. 7]6 DD R _ B_ D[ 0. .63]6
2
DD R _ B _D 4
4
DQ4 DQ5
DQ6 DQ7
A15 A14
A7 A6
A4 A2
A0
BA1
S0#
G2
6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
206
DD R _ B _D 5 DD R _ B_ DQS#0
DD R _ B_ DQS0 DD R _ B _D 6
DD R _ B _D 7 DD R _ B _D 12
DD R _ B _D 13 DD R _ B _D M1
DR A MR S T# DD R _ B _D 14
DD R _ B _D 15 DD R _ B _D 20
DD R _ B _D 21 DD R _ B _D M2 DD R _ B _D 22
DD R _ B _D 23 DD R _ B _D 28
DD R _ B _D 29 DD R _ B_ DQS#3
DD R _ B_ DQS3 DD R _ B _D 30
DD R _ B _D 31
DD R _ CK E 3 _DIMMB DD R _ B_ MA1 5
DD R _ B_ MA1 4 DDR _B_MA11
DD R _ B _MA 7 DDR_B_MA6
DD R _ B _MA 4 DD R _ B _MA 2
DD R _ B _MA 0 M_ C L K _DDR3
M_ C L K _DDR# 3 DD R _ B _BS1
DD R _ B_ RAS # DD R _ CS 2 _ DI MMB#
M_ O DT3
+V R EF _ CB DD R _ B _D 36
DD R _ B _D 37 DD R _ B _D M4 DD R _ B _D 38
DD R _ B _D 39 DD R _ B _D 44
DD R _ B _D 45 DD R _ B_ DQS#5
DD R _ B_ DQS5 DD R _ B _D 46
DD R _ B _D 47 DD R _ B _D 52
DD R _ B _D 53 DD R _ B _D M6 DD R _ B _D 54
DD R _ B _D 55 DD R _ B _D 60
DD R _ B _D 61 DD R _ B_ DQS#7
DD R _ B_ DQS7 DD R _ B _D 62
DD R _ B _D 63 P M_E XTTS#1 _R
SM B _D ATA _S3 SM B _C LK_S3
0. 6 5A
0. 6 5A @0 .75 V
@0. 75V
0. 6 5A0. 6 5A
@0. 75V@0. 75V
DR A MR ST # 4,9
DD R _ CK E 3 _DIMMB 6
M_ C L K_ DD R3 6 M_ C L K_ DD R#3 6
DD R _ B_ BS1 6 DD R _ B_ R AS# 6
DD R _ CS 2 _D IMMB# 6 M_ ODT2 6
M_ ODT3 6
0. 1U _0 40 2_ 16 V4Z C1 59
1
2
PM_EX TTS# 1_ R 4, 9 SM B_D ATA _S3 4,9 ,11,13,32 SM B_CL K_ S3 4 ,9,11,1 3, 32 +0 .7 5VS
DD R _ B_ D M[0 .. 7]6 DD R _ B_ D QS[ 0. .7 ]6 DD R _ B_ MA[ 0. .1 5]6
+V R EF _CB
2.2U_ 06 03 _6 .3 V6 K C1 60
1
2
3
R1 18 7 1K_ 04 02 _1 %
R1 18 8 1K_ 04 02 _1 %
Layout Note: Pl ace near JDIMMB
200 9/0 4/2 4 HP SI-1
+1. 5V
12
12
200 9/0 4/2 4 SI-1
10 U_0603_6.3V 6M
1
2
4
10 U_0603_6.3V 6M
1
2
+V _ DDR _ C PU _ REFB
200 8/1 1/0 7 HP
10 U_0603_6.3V 6M
C1 53
1
2
C1 54
1
@
2
200 9/0 4/1 0 HP DB-3
0. 1U _0 40 2_ 16 V4Z C1 55
1
@
2
+V _ DDR _ C PU _R EF1
0. 1U _0 40 2_ 16 V4Z C1 56
1
@
2
0. 1U _0 40 2_ 16 V4Z C1 57
200 9/0 4/2 4 HP SI-1
0. 1U _0 40 2_ 16 V4Z C1 58
1
@
2
200 9/0 4/1 0 HP DB-3
33 0 U _D 2_ 2V Y_R 7M
C9 61
1
+
@
2
R1 18 4 1K_ 04 02 _1 %
R1 18 5 1K_ 04 02 _1 %
Layout Note: Place near JDIMMB.203 & JDIMMB.204
+V R EF _ DQ_DIM MB
R8 9 0_ 0402_5%
1 2
200 9/0 4/1 0 HP DB-3
R9 0 0_ 0402_5%
1 2
+1 .5 V +0. 75 VS
10 U_0603_6.3V 6M
10 U_0603_6.3V 6M
10 U_0603_6.3V 6M
C1 49
C1 50
1
1
2
2
C1 52
C1 51
1
2
5
+1 .5 V
12
+V _ DDR _ C PU _ REFB
12
1U_0402_6.3 V6 K
C1 6 1
1
1
2
2
1U_0402_6.3 V6 K
1U_0402_6.3 V6 K
1U_0402_6.3 V6 K
C1 6 2
C1 6 4
C1 6 3
1
1
2
2
BOT SLOT
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Da t e: She et o f
Compal Electronics, Inc.
DDRIII-SODIMM SLOT2
LA -490 1 P
5
10 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
A A
CL K _ BU F_ DO T9613 CL K _ BU F_DOT 96 #13
27 M_CL K20 27 M _S SC20
CL K _ BU F _CK SS CD13 CL K _ BU F _CK SS CD#13
CL K _ DMI13 CL K _ DMI #13
B B
CL K _ B UF_ DO T96 CL K _ B UF_ DO T96#
27 M_CLK 27 M_SSC
CL K _ BU F _CK S SCD CL K _ BU F _C KSS CD#
CL K _ DM I CL K _ DMI #
R9 3 0_ 0402_5%
1 2
R9 5 0_ 0402_5%
1 2
R9 6 0_ 0402_5%
1 2
R9 7 22 _0402_1%
1 2
200 9/0 2/2 7 Nvi dia DB -2 NV care
R9 9 0_ 0402_5%
1 2
R1 00 0_0402_5%
1 2
R1 01 0_0402_5%
1 2
R1 03 0_0402_5%
1 2
2
L_ C L K _B UF_ DO T96 L_ C L K_BU F_DOT 96 #
L _2 7M_CL K L_ 27 M_SSC
L_ C L K_B U F _C KSS CD L_ C L K_B U F _C KSS CD#
L_ C L K_ DMI L_ C L K_ DMI #
CP U _ STOP#
250mA 80mA
U2
1
VDD_DOT
2
VSS_DOT
3
DOT_96
4
DOT_96#
5
VDD_27
6
27MHZ
7
27MHZ_SS
8
VSS_27
9
VSS_SATA
10
SRC_1/SATA
11
SRC_1#/SATA#
12
VSS_SRC
13
SRC_2
14
SRC_2#
15
VDD_SRC_IO
16
CPU_STOP#
RTM890N- 63 2_ QF N32_5X5
3
96MHz
REF_0/CPU_SEL
CKPWRGD/PD#
100MHz 133MHz
100MHz
TGND
33
SDA
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_CPU_IO
VDD_SRC
4
+3 VS_ +1 .5 VS
200 9/0 6/3 0 HP SI-2
+3 VS_C K505 +1 .0 5VS_C K505+3 VS_C K505 +1 .0 5VS_C K505
32
SCL
31 30 29 28 27 26 25
24 23 22 21 20 19 18 17
SM B _C LK_S3 SM B _D ATA _S3 RE F _0 / C PU_S EL
CL K_XTAL _I N C LK_XTAL_ OU T
CK _ PWR G D
R_ C L K_ B U F_B CL K R_ C L K_ B U F_B CL K#
R9 433 _0402_1%
1 2
1
2
R1 02 0 _0 40 2_ 5%
1 2
R1 04 0_0 40 2_ 5%
1 2
CL K _ 14M_ PCH
C8 3 1
@
10 P_0 40 2_ 50 V8 C
CL K _ BU F _BCL K CL K _ BU F_B CLK#
SM B_CL K_ S3 4, 9, 10 ,13,32 SM B_DA TA_ S3 4, 9, 10 ,1 3,32 CL K _ 14 M_P CH 13
CL K _ BU F_ BC LK 13 CL K _ BU F_ BC LK# 13
5
47 P_0 40 2_ 50 V8J
C1 77
1
2
200 9/0 6/3 0 HP SI-2 200 9/0 9/1 4 HP SI-2b
R1 21 4 0_0603_5%@
1 2
R1 21 5 0_0603_5%
1 2
2008/09/15 2009/12/31
+3 VS +1. 5V S
Compal Secret Data
Deciphered Date
4
CK _ PWR G D
33 P_0 40 2_ 50 V8J
Tit le
Size Do c u me nt N umb er R e v
Da t e: She et o f
R9 8 10 K_0 40 2_ 5%
1 2
13
D
2
G
S
Q8 SS M3K7 00 2FU_SC7 0- 3
14 .31818MHZ_ 20 P_ 1BX14 31 8B E1A
C1 67
Close to U2
Y1
2
1
12
2
C1 6 8
33 P_0 40 2_ 50 V8J
1
C LK_XTAL_ OU T
Compal Electronics, Inc.
CLOCK GENERATOR
LA -490 1 P
CL K _ EN# 46
CL K_XTAL _I N
5
+3 VS_C K505
1. 0
11 54T u esd ay , Dec ember 15, 2 00 9
+3 VS_ +1 .5 VS
+1 .05VS_ CK5 05+1 .0 5VS
C C
1 2
R1 2 8 0_0603_5%
10 U_0603_6.3V 6M
1
2
D D
(Default)
0 133MHz
1
100MHz 100MHz
1
Close to U2 Close to U2
0. 1U _0 40 2_ 16 V4Z
C1 78
1
2
CPU_1PIN 30 CPU_0
133MHz
10 U_ 08 05 _1 0V 4Z
0. 1U _0 40 2_ 16 V4Z
C1 80
C1 79
1
1
2
2
47 P_0 40 2_ 50 V8J
0. 1U _0 40 2_ 16 V4Z C1 82
C1 81
1
1
2
2
200 9/0 2/0 6 HP DB-2
+1 .0 5VS
R1 4 2 10 K_0 40 2_ 5%@
R1 4 4 10 K_0 40 2_ 5%
C1 83
1 2
1 2
CP U _ STOP#
C1 8 4 1 0P _0 40 2_ 50 V8C
R1 27 1 0K_0402_5%
1 2
@
1 2
EMI Capacitor
RE F _0 / C PU_S EL
+3 VS_ CK 50 5
RE F _0 / C PU_S EL
2
+3 VS
+3 VS_C K505
1 2
R1 0 9 0_0603_5%
0. 1U _0 40 2_ 16 V4Z
10 U_0603_6.3V 6M
C1 71
1
1
2
2
0. 1U _0 40 2_ 16 V4Z
0. 1U _0 40 2_ 16 V4Z
C1 72
C1 73
1
1
2
2
3
0. 1U _0 40 2_ 16 V4Z
0. 1U _0 40 2_ 16 V4Z
C1 74
C1 76
C1 75
1
1
2
2
Security Classification
Issued Date
1
2
3
4
5
PC H _ RT CX1
32 . 76 8KHZ_ 12 .5PF_ Q1 3MC 14 61 00 02
for SM SC EC
not ice KB C state
PC H _ RT CX2
1
C1 91 18 P_0 40 2_ 50 V8J
2
KB C _SPI_ SI_R
HD A _ BI T _CLK_ MDC31 HD A _ BI T _CLK _C ODEC31 HD A _ SY N C_ M DC31 HD A _ SY N C_ C O D EC31 HD A _ SP KR31
HD A _ RS T# _MDC31 HD A _ RS T #_ CO DE C31
HD A _ SD IN 031 HD A _ SD IN 131
HD A _ SD O U T_M DC31 HD A _ SD O U T_ CO DE C31
+R T CV CC
1U _0 60 3_ 10 V4 Z
1 2
R1 64 20 K_0402_1%
1 2
R1 65 20 K_0402_1%
1U _0 60 3_ 10 V4 Z
+3 V AL W
KB C _SP I_ CL K_R35 KB C _SPI_C S0 #_ R35 KB C _SPI_C S1 #_ R35
KB C _SPI_S I_ R35 KB C _SPI _SO35
1
12
C1 92
200 9/0 2/2 0 HP DB-2
CL R P1
SH O R T P ADS
2
1
C1 95
200 9/0 4/2 4 HP SI-1
2
R1 67 33_0402_5%
1 2
R1 68 33_0402_5%
1 2
R1 69 33_0402_5%
1 2
R1 70 33_0402_5%
1 2
R1 72 33_0402_5%
1 2
R1 73 33_0402_5%
1 2
R1 76 33_0402_5%
1 2
R1 77 33_0402_5%
1 2
R1 14 4 1K_ 04 02 _5 %
1 2 1 2
R1 22 5 10K_0 40 2_ 5%
R1 02 6 15_0402_5%
1 2
R1 81 0_0402_5%
1 2
R1 85 0_0402_5%
1 2
R1 02 7 15_0402_5%
1 2
1 2
R1 5 9 10M_0 40 2_ 5%
18 P_0 40 2_ 50 V8J
1
1
C1 9 0
A A
2
200 9/0 4/1 3 DB- 3 C omp al WLAN nosie
C1 93 22P_0 40 2_ 50 V8J C1 94 22P_0 40 2_ 50 V8J C2 00 22P_0 40 2_ 50 V8J C2 01 22P_0 40 2_ 50 V8J
B B
iTPM ENABLE/DISABLE
+3 VS
Ena ble =Stuff Dis abl e=N o Stuff
C C
OSC4OSC
NC3NC
Y3
2
@
HD A _ BI T _CLK _MD C
1 2
@
HD A _ BI T _CLK_ CO DEC
1 2
HD A _ SD O U T_ MDC
@
1 2
HD A _ SD O U T_ C OD EC
@
1 2
1 2
R1 8 6 1 K_ 04 02 _5 %@
GPIO33 iAMT Enable /Disable
+R T CV CC
200 9/0 2/0 6 HP DB-2
+3 VS
1 2
R1 6 1 1 0K _0 40 2_ 5%
1 2
R1 6 3 1 K_ 04 02 _5 %@
LOW =De fault HIG H=N o R eboot
FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3
FWH4 / LFRAME#
LDRQ1# / GPIO23
RTCIHDA
LPC
SATA0RXN SATA0RXP
HDD
SATA0TXN SATA0TXP
SATA1RXN SATA1RXP
ODD
SATA1TXN SATA1TXP
SATA2RXN SATA2RXP
DOCKING
SATA2TXN SATA2TXP
SATA3RXN SATA3RXP SATA3TXN SATA3TXP
SATA4RXN SATA4RXP
E-SATA
SATA4TXN
SATA
SATA4TXP SATA5RXN
SATA5RXP
DOCKING
SATA5TXN SATA5TXP
SATAICOMPO
SATAICOMPI
SATALED#
SATA0GP / GPIO21 SATA1GP / GPIO19
SPI JTAG
LDRQ0#
SERIRQ
D33 B33 C32 A32
C34 A34
F34 AB9
AK7 AK6 AK11 AK9
AH6 AH5 AH9 AH8
AF11 AF9 AF7 AF6
AH3 AH1 AF3 AF1
AD9 AD8 AD6 AD5
AD3 AD1 AB3 AB1
AF16 AF15
T3
Y9 V1
SI R Q
HD A _ SP K R
NA N D_D ET# SI R Q
SA TA_P RX_ DTX_N 0 S ATA_PR X_DTX_P0 SA TA_P TX_ DRX_N 0 S ATA_PTX_D RX_P0
SA TA_P RX_ DTX_N 1 S ATA_PR X_DTX_P1 SA TA_P TX_ DRX_N 1 S ATA_PTX_D RX_P1
SA TA_P RX_ DTX_N 2 S ATA_PR X_DTX_P2 SA TA_P TX_ DRX_N 2 S ATA_PTX_D RX_P2
SA TA_P RX_ DTX_N 4 S ATA_PR X_DTX_P4 SA TA_P TX_ DRX_N 4 S ATA_PTX_D RX_P4
SA TA_P RX_ DTX_N 5 S ATA_PR X_DTX_P5 SA TA_P TX_ DRX_N 5 S ATA_PTX_D RX_P5
SA TA_D ET# 0 HD D _ HA L TLED _R
200 9/0 2/1 8 HP DB-2
200 9/0 2/0 6 HP DB-2
1 2
R1 80 37. 4_ 04 02 _1 %
1 2
R1 82 10K_0402_1%
R1 09 6 0_0402_5%
1 2
LP C _L AD0 28, 33 ,3 5,36 LP C _L AD1 28, 33 ,3 5,36 LP C _L AD2 28, 33 ,3 5,36 LP C _L AD3 28, 33 ,3 5,36
LP C _ LFRAME# 28 ,3 3, 35 ,36 LP C _L DR Q# 0 36
200 9/0 5/0 2 HP SI-1
SI R Q 30 ,3 3,35,36
SA TA_PR X_DTX_N0 29 SATA_ PRX _D TX_ P0 29 SA TA_PTX_D RX_N0 29 SATA_ PTX_DR X_ P0 29
SA TA_PR X_DTX_N1 29 SATA_ PRX _D TX_ P1 29 SA TA_PTX_D RX_N1 29 SATA_ PTX_DR X_ P1 29
SA TA_PR X_DTX_N4 29 SATA_ PRX _D TX_ P4 29 SA TA_PTX_D RX_N4 29 SATA_ PTX_DR X_ P4 29
+1 .0 5VS
+3 VS
SA TA_LED# 3 1, 34
200 9/0 8/3 0 HP PV
200 9/0 5/1 2 HP SI-1
SA TA_D ET# 0
HD D _ HA L TL ED 31
PC H _ RT C RS T#
U4 A
B13
RTCX1
D13
RTCX2
C14
RTCRST#
D17
SRTCRST#
A16
INTRUDER#
A14
INTVRMEN
A30
HDA_BCLK
D29
HDA_SYNC
P1
SPKR
C30
HDA_RST#
G30
HDA_SDIN0
F30
HDA_SDIN1
E32
HDA_SDIN2
F32
HDA_SDIN3
B29
HDA_SDO
H32
HDA_DOCK_EN# / GPIO33
J30
HDA_DOCK_RST# / GPIO13
M3
JTAG_TCK
K3
JTAG_TMS
K1
JTAG_TDI
J2
JTAG_TDO
J4
JTAG_RST#
BA2
SPI_CLK
AV3
SPI_CS0#
AY3
SPI_CS1#
AY1
SPI_MOSI
AV1
SPI_MISO
IB E XP EAK -M_ FCBGA 10 71
SM _ IN T R UD ER# PC H _ IN T V RME N
1 2
R1 60 1M_ 04 02 _5 %
1 2
R1 62 33 0K_ 04 02 _5 %
Hig h = In te rna l V R E nab led(Default)
T12 7
PC H _ RT CX1 PC H _ RT CX2
PC H _ RT C RS T# PC H _ SR T CR ST# SM _ IN T R UD ER# PC H _ IN T V RME N
HD A _ B IT_ CL K H D A _ SY N C HD A _ SP K R HD A _ R ST#
HD A _ SD I N0 HD A _ SD I N1
HD A _ SD O UT
G PIO33AQ U AWH I T E_BATL ED
PC H _ JT A G_ TCK PC H _ J TAG _TMS PC H _ J TAG _TDI PC H _ J TAG _TDO PC H _ J TAG _R ST#
PC H _ SP I _C LK PC H _ S PI_ CS 0# PC H _ S PI_ CS 1#
PC H _ S PI_ SI HD D _ HA L TLED
C2 15
1U _0 60 3_ 10 V4 Z
+3 VS
1 2
R1 15 9 10 K_ 04 02 _5%
200 9/0 2/1 1 HP DB-2
SA TA_P RX_ DTX_N 0 S ATA_PR X_DTX_P0 SA TA_P RX_ DTX_N 1 S ATA_PR X_DTX_P1
SA TA_P RX_ DTX_N 2 S ATA_PR X_DTX_P2 SA TA_P RX_ DTX_N 5 S ATA_PR X_DTX_P5
SA TA_PR X_DTX_N2 34 SATA_ PRX _D TX_ P2 34 SA TA_PTX_D RX_N2 34 SATA_ PTX_DR X_ P2 34
SA TA_P RX_ DTX_N 4 S ATA_PR X_DTX_P4
SA TA_PR X_DTX_N5 34 SATA_ PRX _D TX_ P5 34 SA TA_PTX_D RX_N5 34 SATA_ PTX_DR X_ P5 34
+3 VS
12
R1 83 10 K_0 40 2_ 5%
W=20mils
1
2
12
R1 84 10 K_0 40 2_ 5%
RTC Conn.
D 1
1
DA N 2 02 U_SC7 0
Place near IBEX-M
NA N D_D ET#
T13 0 T13 1 T13 2 T13 3
T13 4 T13 5 T13 6 T13 7
33 0K_ 04 02 _5%
T14 0
200 8/1 2/1 2 HP
T14 1
AQ U AWH I TE _BATLED#31 ,35
@
200 9/0 2/0 6 HP DB-2
2
R1 9 8
3
1 2
W=20mils
1K_ 04 02 _5 %
12
R6 8 1
@
BATT1.1+VREG 3_ 51 12 5+R T CV CC
+3 VS
12
13
D
2
G
S
JB AT1
W=20mils
R7 90
@
10 K_0 40 2_ 5%
AQ U AWH I T E_BATL ED
200 9/0 2/0 6 HP DB-2
Q6 3 2N7002H_S OT2 3- 3
C O N N@
1
2
ACE S_85205 -020 0
Hi Disable Lo Enable Default
XD P _FN0
R7 9833_0402_5% @
US B _OC# 015
+3 VALW +3 V AL W+ 3 VA LW +3 VA LW
12
R1 88 20 0_0402_5%
PC H _ J TAG _TMS PCH _ J TAG_TDO PC H _ J TAG _R ST#PC H _ J TAG _TDI
12
R1 94 10 0_0402_1%
D D
PCH Pin
PCH _JT AG_TDO
PCH _JT AG_TMS
PCH _JT AG_TDI
PCH _JT AG_TCK
PCH _JT AG_ RST#
12
R1 89 20 0_0402_5%
12
R1 95 10 0_0402_1%
Ref Des PCH JTA G Pre -Pr oduction PCH JT AG Pr oduction
ES1
ES2
No Ins tall
R189 R195 R No In stall No In stall
R
R194 R R190 R196 R R199 R191 R197 R 51o hmNo Ins tall No I ns tall
100 ohm
No Ins tall
200 ohm
200 ohm 100 ohm
100 ohm
No Ins tall No I ns tall 5 1ohm
200 ohm No Ins tall
200 ohm 100 ohm
100 ohm
No Ins tall No I ns tall
51o hm
51o hm
20K ohm
20K ohm 10K ohm
10K ohm
1
12
R1 9 0 20 0_0402_5%
12
R1 9 6 10 0_0402_1%
MP No Ins tall200ohm No Ins tall 51o hm No Ins tallR188 No Ins tall
No Ins tall 51o hm 51o hm No Ins tall No Ins tall
12
R1 91 20 K_0 40 2_ 5%
12
R1 97 10 K_0 40 2_ 5%
PC H _ J TAG _TDO PC H _ J TAG _TMS PC H _ J TAG _TDI PC H _ J TAG _R ST# PC H _ JT A G_ TCK
@
200 9/0 3/0 8 HP SI-1
@
R1 10 5 51_0402_5%@ R1 10 6 51_0402_5%@ R1 10 7 51_0402_5%@ R1 10 8 51_0402_5%@ R1 99 51 _0402_5%
+1 .0 5VS
1 2 1 2 1 2 1 2 1 2
2
US B _OC# 115 US B _OC# 215
US B _OC# 315
US B _OC# 415 US B _OC# 515
US B _OC# 615 US B _OC# 715
PW R _ GD3 5, 37 PM _ PW R BTN# _R4 ,14
PW R _ GD
1
C9 9 8
@
0.1U_ 04 02 _2 5V 4K
2
200 9/0 9/1 5 Com pal ESD PV
PC H _ JT A G_ TCK
3
1 2 1 2
1 2 1 2
200 8/1 2/1 2 HP
1 2 1 2
1 2 1 2
R8 14
1 2
200 9/0 2/0 6 HP DB-2
1 2
R8 19 0_0402_5%
Security Classification
Issued Date
XD P _FN1
R8 0033_0402_5% @
XD P _FN2
R8 0233_0402_5% @ R8 0433_0402_5% @
XD P _FN3
R1 09 533 _0 40 2_ 5% @
XD P _FN5
R8 0833_0402_5% @ R8 1033_0402_5% @
XD P _FN6 XD P _FN7
R8 1233_0402_5% @
PW R _ GD
XD P _PW R BTN #_ R
0_ 0402_5%
T128 T129
PC H _ JT A G_ TCK_R
PCH XDP Conn.
JP 15
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
39
PWRGOOD/HOOK0
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
SAMTE_BSH -0 30 -0 1- L- D-A C O N N@
2008/09/15 2009/12/31
Compal Secret Data
OBSDATA_C0 OBSDATA_C1
OBSDATA_C2 OBSDATA_C3
OBSDATA_D0 OBSDATA_D1
OBSDATA_D2 OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
Deciphered Date
GND1 OBSFN_C0 OBSFN_C1
GND3
GND5
GND7 OBSFN_D0 OBSFN_D1
GND9
GND11
GND13
DBR#/HOOK7
GND15
TRST#
GND17
4
2
XD P _FN1 7
4
XD P _FN1 6
6 8
XD P _FN8
10
XD P _FN9
12 14
XD P _FN1 0
16
XD P _FN1 1
18 20 22 24 26
XD P _FN1 2
28
XD P _FN1 3
30 32
XD P _FN1 4
34
XD P _FN1 5
36 38 40 42 44 46 48 50
PC H _ JT A G_ TDO #_ R
52
TD0
TDI
TMS
54 56 58 60
PC H _ JT A G_ RST#_R PC H _ JT A G_ TDI _R PC H _ J TAG _TMS_R
R7 96 33_0402_5%@
1 2
R7 97 33_0402_5%@
1 2
R7 99 33_0402_5%@
1 2
R8 01 33_0402_5%@
1 2
R8 03 33_0402_5%@
1 2
R8 05 33_0402_5%@
1 2
R8 07 33_0402_5%@
1 2
R8 09 33_0402_5%@
1 2
R8 11 33_0402_5%@
1 2
R8 13 33_0402_5%@
1 2
R8 15 1K_ 04 02 _5 %
1 2
R8 16 0 _0 40 2_ 5%
1 2
R8 17 0 _0 40 2_ 5%@
1 2
R8 18 0 _0 40 2_ 5%
1 2
R8 20 0 _0 40 2_ 5%
1 2
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
SA TA_D ET# 0 HD D _ HA L TLED _R
PC H _ J TAG _TDO PC H _ J TAG _R ST# PC H _ J TAG _TDI PC H _ J TAG _TMS
Compal Electronics, Inc.
IBEX-M(1/6)-HDA/JTAG/SATA
PC H _ XDP _G PIO 28 15 PC H _ XDP _G PIO 0 15
PC H _ XDP _G PIO 20 13 PC H _ XDP _G PIO 18 13
200 9/0 2/1 6 HP DB-2
PC H _ XDP _G PIO 36 15 PC H _ XDP _G PIO 37 1 5,19
PC H _ XDP _G PIO 16 15 PC H _ XDP _G PIO 49 15
+3 VS+3 VS
PL T_RST# 4,15,20 ,2 6, 28 ,3 1,33 XD P _DBR ESE T# 4,14
LA -490 1 P
5
GPI O_28 GPI O_0
GPI O_36 GPI O_37
GPI O_16 GPI O_49
12 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
2
3
4
5
SM B _C LK_S3 SM B _D ATA _S3
A A
U 4 B
BG30
PERN1
BJ30
PERP1
BF29
PETN1
BH29
PC I E_ PRX _DTX_ N231
EXP
WLAN
B B
NIC
EXP
C C
WLAN
D D
PC I E_ PRX _DTX_ P231 PC I E_ PTX_C _D RX_ N231 PC I E_ PTX_C_ DR X_P231
PC I E_ PRX _DTX_ N428 PC I E_ PRX _DTX_ P428 PC I E_ PTX_C _D RX_ N428 PC I E_ PTX_C_ DR X_P428
PC I E_ PRX _DTX_ N626 PC I E_ PRX _DTX_ P626 PC I E_ PTX_C _D RX_ N626 PC I E_ PTX_C_ DR X_P626
PC H _ XDP _G PIO 1812
CL K _ PC IE_L AN _REQ1 #26
+3 VS
CL K _P CIE_E XP#31 CL K _ PCI E_ EXP3 1
PC H _ XDP _G PIO 2012
CL K RE Q_EXP#31
CL K _ PC I E_MC ARD #28 CL K _ PC I E_MC ARD28
CL K R EQ _ WL AN #28
C2 16 0.1U_0 40 2_ 10 V7 K
1 2
C2 17 0.1U_0 40 2_ 10 V7 K
1 2
C2 18 0.1U_0 40 2_ 10 V7 K
1 2
C2 19 0.1U_0 40 2_ 10 V7 K
1 2
C2 22 0.1U_0 40 2_ 10 V7 K
1 2
C2 23 0.1U_0 40 2_ 10 V7 K
1 2
+3 V AL W
R2 12 1 0K_0402_5%
+3 VS
+3 V AL W
+3 V AL W
+3 V AL W
+3 V AL W
R8 2 1 10 K_0 40 2_ 5%
1 2
R2 13
1 2 1 2
R2 14
R2 0 4 10 K_0 40 2_ 5% R1 00 9 0_0402_5% R2 0 6 10 K_0 40 2_ 5%
R2 16
1 2 1 2
R2 17
R3 5 4 10 K_0 40 2_ 5%
R3 5 3 10 K_0 40 2_ 5%
R1 13 8 10K_0 40 2_ 5%
200 9/0 2/0 6 HP DB-2
200 9/0 2/0 6 HP DB-2
1 2
0_ 0402_5% 0_ 0402_5%
1 2 1 2 1 2
0_ 0402_5% 0_ 0402_5%
1 2
1 2
1 2
PC I E_ PR X_DTX_N2 PC I E_ PRX _DTX_ P2 PC I E_ PTX_D RX_N2 PC I E_ PTX_DR X_ P2
PC I E_ PR X_DTX_N4 PC I E_ PRX _DTX_ P4 PC I E_ PTX_D RX_N4 PC I E_ PTX_DR X_ P4
PC I E_ PR X_DTX_N6 PC I E_ PRX _DTX_ P6 PC I E_ PTX_D RX_N6 PC I E_ PTX_DR X_ P6
200 9/0 5/0 2 HP SI-1
R1 19 8 0_0402_5%
1 2
CL K _ PC IE_EX P#_R CL K _ PC IE_EX P_R
200 8/1 2/1 2 HP
CL K _ PC I E_ MCA RD#_R CL K _ PC I E_ MCA RD_R
PETP1
AW30
PERN2
BA30
PERP2
BC30
PETN2
BD30
PETP2
AU30
PERN3
AT30
PERP3
AU32
PETN3
AV32
PETP3
BA32
PERN4
BB32
PERP4
BD32
PETN4
BE32
PETP4
BF33
PERN5
BH33
PERP5
BG32
PETN5
BJ32
PETP5
BA34
PERN6
AW34
PERP6
BC34
PETN6
BD34
PETP6
AT34
PERN7
AU34
PERP7
AU36
PETN7
AV36
PETP7
BG34
PERN8
BJ34
PERP8
BG36
PETN8
BJ36
PETP8
AK48
CLKOUT_PCIE0N
AK47
CLKOUT_PCIE0P
P9
PCIECLKRQ0# / GPIO73
AM43
CLKOUT_PCIE1N
AM45
CLKOUT_PCIE1P
U4
PCIECLKRQ1# / GPIO18
AM47
CLKOUT_PCIE2N
AM48
CLKOUT_PCIE2P
N4
PCIECLKRQ2# / GPIO20
AH42
CLKOUT_PCIE3N
AH41
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
AM51
CLKOUT_PCIE4N
AM53
CLKOUT_PCIE4P
M9
PCIECLKRQ4# / GPIO26
AJ50
CLKOUT_PCIE5N
AJ52
CLKOUT_PCIE5P
H6
PCIECLKRQ5# / GPIO44
AK53
CLKOUT_PEG_B_N
AK51
CLKOUT_PEG_B_P
P13
PEG_B_CLKRQ# / GPIO56
IB E XP EA K-M_FCBG A1071
PCI-E*
120/133MHz
100MHz
100MHz
100MHz
100MHz
SMBALERT# / GPIO11
SMBCLK
SMBDATA
SML0ALERT# / GPIO60
SML0CLK
SML0DATA
SML1ALERT# / GPIO74
SMBus
SML1CLK / GPIO58
SML1DATA / GPIO75
CL_CLK1
Link
Controller
100MHz
100MHz
PEG
CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P
100MHz
133MHz
96MHz
From CLK BUFFER
CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P
CL_DATA1
CL_RST1#
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N CLKOUT_PEG_A_P
CLKOUT_DMI_N CLKOUT_DMI_P
CLKIN_DMI_N CLKIN_DMI_P
CLKIN_BCLK_N CLKIN_BCLK_P
CLKIN_DOT_96N CLKIN_DOT_96P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
Clock Flex
L_ L ID_ SW #
B9
SM B CL K
H14
SM BD ATA
C8
SM L 0ALER T#
J14
SM L 0C LK
C6
SM L 0DATA
G8
SM L 1ALER T#
M14
SM L 1C LK
E10
SM L 1DATA
G12
T13 T11 T9
PE G _ C LKREQ #
H1
AD43 AD45
AN4 AN2
CL K _ DP#
AT1
CL K _ DP
AT3
AW24 BA24
AP3 AP1
F18 E18
AH13 AH12
P41
J42
XTAL25_IN
AH51
XTAL25_OUT
AH53 AF38
R2 18 90.9_0402_1%
1 2
T45
P43
T42
N50
CL K_14M_SIO_ P
R2 22 22_0402_5%
1 2
200 9/0 5/1 9 HP SI-1
For SMSC SIO 14MHz CLK out
200 9/0 7/0 3 SI-1b 200 9/0 8/3 0 HP PV
SM L0 CL K 26 SM L0 DATA 26
CL _ CL K 28 CL _ DA TA 28 CL _ RST # 28
CL K _P EG_VG A# 20 CL K _ PEG _V GA 20
CL K_ EXP # 4 CL K_ EXP 4
T27 T28
CL K _D MI# 11 CL K _D MI 11
CL K _ BU F_ BC LK# 11 CL K _ BU F_ BC LK 11
CL K _ BU F_DOT 96 # 11 CL K _ BU F_DOT 96 11
CL K _ BU F _CK SSC D# 11 CL K _ BU F _CK SSC D 11
CL K _ 14 M_P CH 11
CL K _ PC I_ FB 15
T93
T94
DDR
Intel LAN
CBB
+1 .0 5VS
1
C8 33 10 P_0 40 2_ 50 V8C
2
PE G _ C LKREQ #
09/ 02/ 22 HP DB-2
CL K_14M_ SIO 36
@
R2 00 10K_0 40 2_ 5%
1 2
R2 02 10K_0 40 2_ 5%
1 2
R2 09 10K_0 40 2_ 5%
1 2
Q6 A
2N 7 002DWH _SOT3 63 -6
SM B CL K
6 1
2
Q6 B
2N 7 002DWH _SOT3 63 -6
SM BD ATA
+3 VS
61
3 4
R1 14 6 0_0402_5%@
1 2
R1 14 7 0_0402_5%@
1 2
SM L 1_CL K_ R
5
SM L 1C LK
SM BDATA
Q7 A
2N 7 002DWH _SOT3 63 -6
SM B CL K SM BD ATA
2
Q7 B
2N 7 002DWH _SOT3 63 -6
SM L 1DATA
+3 VALW +3 VS
5
XTAL25_IN XTAL25_OUT
SM L 1_DA TA_ R
34
Thi s c irc ui t w ill ad d/d ele te i n I NTE L E S2 sample to test.
@
1 2
R2 15 1M_ 04 02 _5%
Y4
1 2
@
25 M HZ_20P_ 1B G2 50 00 CK1 A
18 P_0 40 2_ 50 V8J
C2 26
1
@
2
SM B CL K
+3 VS +3 V AL W
SM BD ATA SM L 0C LK SM L 0DATA
SM L 1ALER T# SM L 0ALER T# L_ L ID_ SW # SM L 1C LK SM L 1DATA
SM B _C LK_S3
SM B _D ATA _S3
R9 13 0 _0 40 2_ 5%
1 2
Q7 6A
2N 7 002DWH _SOT3 63 -6
6 1
R2 01 2 .2 K_0402_5% R2 03 2 .2 K_0402_5% R2 05 2 .2 K_0402_5% R2 07 2 .2 K_0402_5%
200 9/0 2/2 0 HP DB-2
R2 11 1 0K_0402_5% R9 58 1 0K_0402_5% R9 59 1 0K_0402_5% R1 09 2 4.7 K_0402_5% R1 09 3 4.7 K_0402_5%
200 9/0 2/2 0 HP DB-2
SM L 1C LK SM L 1DATA
1 2 1 2 1 2 1 2
1 2 1 2
200 9/0 8/3 0 HP PV
1 2 1 2 1 2
SM B_CL K_ S3 4, 9, 10 ,11,32SM BCLK
SM B_DA TA_ S3 4 ,9 ,10,11,32
CA P _CLK 31,3 5
SM L1 _C LK 20
200 9/0 1/2 0 int el WoW
2
Q7 6B
2N 7 002DWH _SOT3 63 -6
3 4
SM L 1_ DAT A 20
5
R9 14 0 _0 40 2_ 5%
1 2
18 P_0 40 2_ 50 V8J
C2 2 7
1
200 9/0 4/1 0 HP DB-3
2
the P/ N i s cha ged to SD028000080
CA P _DAT 3 1,35
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
IBEX-M(2/6)-PCI-E/SMBUS/CLK
LA -490 1 P
5
13 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
2
3
4
5
DM I_ CTX_P RX_ N05 DM I_ CTX_P RX_ N15 DM I_ CTX_P RX_ N25 DM I_ CTX_P RX_ N35
DM I_ CTX_P RX_ P05 DM I_ CTX_P RX_ P15 DM I_ CTX_P RX_ P25
A A
B B
DM I_ CTX_P RX_ P35
DM I_ CR X_PTX_ N05 DM I_ CR X_PTX_ N15 DM I_ CR X_PTX_ N25 DM I_ CR X_PTX_ N35
DM I_ CR X_PTX_ P05 DM I_ CR X_PTX_ P15 DM I_ CR X_PTX_ P25 DM I_ CR X_PTX_ P35
+1 .0 5VS
1 2
R2 27 49 .9_0402_1%
XD P _DB RES ET#4, 12
VG AT E35 ,4 6
M_ P WR O K37
PM _ DR A M_ P WR GD4 RP G O OD42
PM _ RS MRS T#35
+3 V AL W
SU S _PW R _ACK35 PM _ PW R BTN# _R4 ,12
ON / O FF B TN#31
AC _ PRE SE NT20,3 5
DM I _C TX_ PRX _N 0 DM I _C TX_ PRX _N 1 DM I _C TX_ PRX _N 2 DM I _C TX_ PRX _N 3
DM I _C TX_ PRX _P0 DM I _C TX_ PRX _P1 DM I _C TX_ PRX _P2 DM I _C TX_ PRX _P3
DM I _C RX_ PTX _N 0 DM I _C RX_ PTX _N 1 DM I _C RX_ PTX _N 2 DM I _C RX_ PTX _N 3
DM I _C RX_ PTX _P0 DM I _C RX_ PTX _P1 DM I _C RX_ PTX _P2 DM I _C RX_ PTX _P3
DM I _IR C OMP
SY S _R ST#
1 2
R2 28 0_04 02 _5 %
R2 32 0 _0 40 2_ 5% R2 33 1 0K_0402_5%
R1 06 3 10K_0402_5%
R2 34 0_ 0402_5%
200 8/1 2/0 6 fol low UMA
VG A TE
1 2
R2 3 0 0_0402_5%
1 2
R2 3 1 0_0402_5%
PM _ DR A M_ P W RG D
1 2 1 2
1 2
1 2
LO W _ BAT#_ R
I BEX _R#
AU X PW R OK
U 4 C
BC24
DMI0RXN
BJ22
DMI1RXN
AW20
DMI2RXN
BJ20
DMI3RXN
BD24
DMI0RXP
BG22
DMI1RXP
BA20
DMI2RXP
BG20
DMI3RXP
BE22
DMI0TXN
BF21
DMI1TXN
BD20
DMI2TXN
BE18
DMI3TXN
BD22
DMI0TXP
BH21
DMI1TXP
BC20
DMI2TXP
BD18
DMI3TXP
BH25
DMI_ZCOMP
BF25
DMI_IRCOMP
T6
SYS_RESET#
M6
SYS_PWROK
B17
PWROK
K5
MEPWROK
A10
LAN_RST#
D9
DRAMPWROK
C16
RSMRST#
M1
SUS_PWR_ACK / GPIO30
P5
PWRBTN#
P7
ACPRESENT / GPIO31
A6
BATLOW# / GPIO72
F14
RI#
IB E XP EA K-M_FCBG A1071
DMI
FDI
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
System Power Management
FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7
FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7
FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1
WAKE#
SLP_S4#
SLP_S3#
SLP_M#
TP23
PMSYNCH
SLP_LAN#
BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12
BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12
R1 16 5 1K_0402_5%
BJ14
1 2
R1 16 6 1K_0402_5%
1 2
BF13
R1 16 7 1K_0402_5%
1 2
BH13
R1 16 8 1K_0402_5%
1 2
BJ12
R1 16 9 1K_0402_5%
1 2
BG14
PC I E_ W A KE#
J12
PM _ CL K R UN#
Y1
SU S _STAT #
P8
SU S _ CL K
F3
E4
H7
P12
K8
N2
BJ10
PM _ SL P_ LAN#
F6
PC I E_ W AK E# 2 8,31
PM _ CL K RU N# 3 0, 33 ,3 5,36
T142
200 9/0 8/3 0 HP PV
T30
SL P_ S5 # 34
SL P_ S4 # 38,45
SL P_ S3 # 31,35 ,3 7, 38 ,4 0,42,43,4 4,48
PM _S LP_M# 35 ,3 7, 38
H_ P M_ S Y NC 4
PM _ SLP_L AN# 35 ,38,45
1K_ 04 02 _0 .5 %
12
R2 35
U 4 D
T48
L_BKLTEN
T47
L_VDD_EN
Y48
L_BKLTCTL
AB48
L_DDC_CLK
Y45
L_DDC_DATA
AB46
L_CTRL_CLK
V48
L_CTRL_DATA
AP39
LVD_IBG
AP41
LVD_VBG
AT43
LVD_VREFH
AT42
LVD_VREFL
AV53
LVDSA_CLK#
AV51
LVDSA_CLK
BB47
LVDSA_DATA#0
BA52
LVDSA_DATA#1
AY48
LVDSA_DATA#2
AV47
LVDSA_DATA#3
BB48
LVDSA_DATA0
BA50
LVDSA_DATA1
AY49
LVDSA_DATA2
AV48
LVDSA_DATA3
AP48
LVDSB_CLK#
AP47
LVDSB_CLK
AY53
LVDSB_DATA#0
AT49
LVDSB_DATA#1
AU52
LVDSB_DATA#2
AT53
LVDSB_DATA#3
AY51
LVDSB_DATA0
AT48
LVDSB_DATA1
AU50
LVDSB_DATA2
AT51
LVDSB_DATA3
AA52
CRT_BLUE
AB53
CRT_GREEN
AD53
CRT_RED
V51
CRT_DDC_CLK
V53
CRT_DDC_DATA
Y53
CRT_HSYNC
Y51
CRT_VSYNC
AD48
DAC_IREF
AB51
CRT_IRTN
IB E XP EAK -M_ FCBGA 10 71
SDVO_INTN SDVO_INTP
DDPB_AUXN DDPB_AUXP
DDPB_HPD
DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P
DDPC_AUXN DDPC_AUXP
DDPC_HPD
DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P
DDPD_AUXN DDPD_AUXP
DDPD_HPD
DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P
BJ46 BG46
BJ48 BG48
BF45 BH45
T51 T53
BG44 BJ44 AU38
BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38
Y49 AB49
BE44 BD44 AV40
BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36
U50 U52
BC46 BD46 AT38
BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36
SDVO_TVCLKINN SDVO_TVCLKINP
SDVO_STALLN SDVO_STALLP
SDVO_CTRLCLK
SDVO_CTRLDATA
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
CRT
VG A TE
C C
S LP_ S3 # P M_S LP_M# AU X PW R OK SU S _PW R _ AC K PM _ R SMR ST# M_ P WR OK
D D
T12 0 T12 1 T12 2 T12 3 T12 4 T12 5 T12 6
1
PM _ CL K R UN#
SY S _R ST# LO W _ BAT#_ R PM _ SL P_ LAN# I BEX _R# PC I E_ W A KE#
R2 3 7 10 K_0 40 2_ 5%
1 2
R2 3 9 10 K_0 40 2_ 5%@
1 2
R2 4 0 10 K_0 40 2_ 5%
1 2
R2 4 1 10 K_0 40 2_ 5%
1 2
R2 4 2 10 K_0 40 2_ 5%
1 2
200 9/0 9/1 5 HP SI-2b
R2 4 3 10 K_0 40 2_ 5%
1 2
R9 1 8 10 K_0 40 2_ 5%@
1 2
200 9/0 5/1 6 HP SI-1
+3 VS
+3 V AL W
200 9/0 1/2 2 HP DB-2
VG A TE
S LP_ S3 # S LP_ S4 # S LP_ S5 #AC_ P R E SEN T
2
R2 29 1 0K_0402_5%
1 2
R9 15 1 0K_0402_5%@
1 2
R9 16 1 0K_0402_5%@
1 2
R9 17 1 0K_0402_5%@
1 2
Security Classification
Issued Date
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
IBEX-M(3/6)-DMI/GPIO/LVDS
LA- 4901P
5
14 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
PC I _ AD [0 ..3 1]30
A A
PC I _ CBE 0#30 PC I _ CBE 1#30 PC I _ CBE 2#30 PC I _ CBE 3#30
PC I _ REQ 2#30
B B
C C
PC I _ STO P# PC I _ TR D Y# PC I _ D EVS EL# PC I _ FR A ME#
PC I _ LOCK # PC I _ RE Q0 # PC I _ P IRQB# OD D _ DET#
PC I _ P IRQA# PC I _ P IRQD# PC I _ RE Q3 # PC I _ P ERR #
D D
200 9/0 7/0 2 HP SI-1b
PC I _ RE Q2 # PC I _ RE Q1 # AC C E L_ IN T# PC I _ S ERR #
PC I _ P IRQE# PC I _ PI RQ G# PC I _ P IRQC# PC I _ IR D Y#
MO D EM _DIS ABL E# PC I _G NT2 #30
PC I _ PI RQ E#30 OD D _ DET#29
PC I _ PIR QG #30 AC C EL _I NT#32
PC I _R ST#28 ,3 0 PC I _ SE RR#30,33,35
PC I _ PE RR#30
PC I _ IR D Y#30 PC I _ PAR30 PC I _ DE VSE L#30 PC I _ FR AME#30
PC I _S TOP #30 PC I _ TR DY #30
PL T_RST#4,12,20 ,2 6, 28 ,3 1,33
200 9/0 3/2 3 Com pal DB-3
RP 59
1 8 2 7 3 6 4 5
8. 2K _0 80 4_ 8P4R_ 5% R P 6
1 8 2 7 3 6 4 5
8. 2K _0 80 4_ 8P4R_ 5% R P 8
1 8 2 7 3 6 4 5
8. 2K _0 80 4_ 8P4R_ 5%
R P 7
1 8 2 7 3 6 4 5
8. 2K _0 80 4_ 8P4R_ 5% R P 9
1 8 2 7 3 6 4 5
8. 2K _0 80 4_ 8P4R_ 5%
+3 VS
1
PC I _ AD 0 PC I _ AD 1 PC I _ AD 2 PC I _ AD 3 PC I _ AD 4 PC I _ AD 5 PC I _ AD 6 PC I _ AD 7 PC I _ AD 8 PC I _ AD 9 PC I _ AD 10 PC I _ AD 11 PC I _ AD 12 PC I _ AD 13 PC I _ AD 14 PC I _ AD 15 PC I _ AD 16 PC I _ AD 17 PC I _ AD 18 PC I _ AD 19 PC I _ AD 20 PC I _ AD 21 PC I _ AD 22 PC I _ AD 23 PC I _ AD 24 PC I _ AD 25 PC I _ AD 26 PC I _ AD 27 PC I _ AD 28 PC I _ AD 29 PC I _ AD 30 PC I _ AD 31
PC I _ P IRQA# PC I _ P IRQB# PC I _ P IRQC# PC I _ P IRQD#
PC I _ RE Q0 # PC I _ RE Q1 # PC I _ RE Q2 # PC I _ RE Q3 #
PC I _ GNT0#
MO D EM _ DI SAB LE#
PC I _ GNT2# PC I _ GNT3#
PC I _ P IRQE# OD D _ DET# PC I _ PI RQ G# AC C E L_ IN T#
PC I _ RS T# PC I _ S ERR #
PC I _ P ERR #
PC I _ IR D Y# PC I _ P AR PC I _ D EVS EL# PC I _ FR A ME#
PC I _ LOCK # PC I _ STO P#
PC I _ TR D Y#
CL K _ PC I _ KBC _R CL K _ PC I_FB_R CL K _ P CI_TP M_R CL K _ PCI _1 39 4_ R CL K _ P CI_DB _P
U4 E
H40
AD0
N34
AD1
C44
AD2
A38
AD3
C36
AD4
J34
AD5
A40
AD6
D45
AD7
E36
AD8
H48
AD9
E40
AD10
C40
AD11
M48
AD12
M45
AD13
F53
AD14
M40
AD15
M43
AD16
J36
AD17
K48
AD18
F40
AD19
C42
AD20
K46
AD21
M51
AD22
J52
AD23
K51
AD24
L34
AD25
F42
AD26
J40
AD27
G46
AD28
F44
AD29
M47
AD30
H36
AD31
J50
C/BE0#
G42
C/BE1#
H47
C/BE2#
G34
C/BE3#
G38
PIRQA#
H51
PIRQB#
B37
PIRQC#
A44
PIRQD#
F51
REQ0#
A46
REQ1# / GPIO50
B45
REQ2# / GPIO52
M53
REQ3# / GPIO54
F48
GNT0#
K45
GNT1# / GPIO51
F36
GNT2# / GPIO53
H53
GNT3# / GPIO55
B41
PIRQE# / GPIO2
K53
PIRQF# / GPIO3
A36
PIRQG# / GPIO4
A48
PIRQH# / GPIO5
K6
PCIRST#
E44
SERR#
E50
PERR#
A42
IRDY#
H44
PAR
F46
DEVSEL#
C46
FRAME#
D49
PLOCK#
D41
STOP#
C48
TRDY#
M7
PME#
D5
PLTRST#
N52
CLKOUT_PCI0
P53
CLKOUT_PCI1
P46
CLKOUT_PCI2
P51
CLKOUT_PCI3
P48
CLKOUT_PCI4
IB E XP EAK -M_ FCBGA 10 71
CL K _ PCI _S IO36 CL K _ PC I_ KBC35 CL K _ PC I _D EBU G28 CL K _ PC I_ DB33
CL K _ PC I_ FB13 CL K _ PCI _T PM33
CL K_PC I_ 13 9430
TH E RM _ SCI#
PC I _ GNT3#
R1 02 8 8.2K_ 04 02 _5%
1 2
R2 87 1K_ 04 02 _5 %@
1 2
A16 sw ap ov eri de Str ap/Top-Block Swa p O ver ri de jumper
Low =A1 6 swap ove rri de/ To p-Block
PCI _GN T3#
Swa p O ver ri de enabled Hig h=D efault
PCI
NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11
NVRAM
NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15
NV_WR#0_RE# NV_WR#1_RE#
NV_WE#_CK0 NV_WE#_CK1
USB
OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43
OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14
+3 VS
2
AY9
NV_CE#0
BD1
NV_CE#1
AP15
NV_CE#2
BD8
NV_CE#3
AV9
NV_DQS0
BG8
NV_DQS1
AP7 AP6
200 9/0 8/3 0 HP PV
AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6
NV _ ALE
BD3
NV_ALE NV_CLE
NV_RCOMP
NV_RB#
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N
USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P
USBRBIAS#
USBRBIAS
C9 5 1 2 2P _0 40 2_ 50 V8J
@
NV _ C LE
AY6
1 2
AU2
R2 51 32.4 _0 40 2_ 1%
AV7 AY8
AY5 AV11
BF5
US B 20_N0
H18
US B 20 _P0
J18
US B 20_N1
A18
US B 20 _P1
C18
US B 20_N2
N20
US B 20 _P2
P20
US B 20_N3
J20
US B 20 _P3
L20
US B 20_N4
F20
US B 20 _P4
G20 A20 C20 M22 N22 B21 D21
US B 20_N8
H22
US B 20 _P8
J22
US B 20_N9
E22
US B 20 _P9
F22
US B 20_N10
A22
US B 20 _P10
C22
US B 20_N11
G24
US B 20 _P11
H24
US B 20_N12
L24
US B 20 _P12
M24
US B 20_N13
A24
US B 20 _P13
C24
US B RB I AS
B25 D25
Within 500 mils
US B _ OC #0
N16
US B _ OC #1
J16
US B _ OC #2
F16
US B _ OC #3
L16
US B _ OC #4
E14
US B _ OC #5
G16
US B _ OC #6
F12
US B _ OC #7
T15
200 9/0 7/2 3 Add Ca p. SI- 2 Compal RF 200 9/1 1/0 2 Del Ca p. MV Compal RF
C9 5 3 2 2P _0 40 2_ 50 V8J
C9 5 4 2 2P _0 40 2_ 50 V8J
C9 5 2 2 2P _0 40 2_ 50 V8J
1
1
1
1
@
@
@
2
2
2
2
BU F _P L T_R ST#4
2
@
1 2
R2 52 22 .6_0402_1%
C9 5 6 2 2P _0 40 2_ 50 V8J
C9 5 5 2 2P _0 40 2_ 50 V8J
1
1
@
@
@
2
2
200 9/0 2/1 9 HP DB-2
200 9/0 8/3 0 HP PV
US B 20 _N0 32 US B2 0_ P0 32 US B 20 _N1 32 US B2 0_ P1 32 US B 20 _N2 32 US B2 0_ P2 32 US B 20 _N3 32 US B2 0_ P3 32 US B 20 _N4 31 US B2 0_ P4 31
US B 20 _N8 32 US B2 0_ P8 32 US B 20 _N9 28 US B2 0_ P9 28 US B2 0_ N1 0 33 US B2 0_ P1 0 33 US B2 0_ N1 1 34 US B2 0_ P1 1 34 US B2 0_ N1 2 19 US B2 0_ P1 2 19 US B2 0_ N1 3 34 US B2 0_ P1 3 34
US B _OC# 0 12 US B _OC# 1 12 US B _OC# 2 12 US B _OC# 3 12 US B _OC# 4 12 US B _OC# 5 12 US B _OC# 6 12 US B _OC# 7 12
C9 4 9 2 2P _0 40 2_ 50 V8J
1
2
1 2
R2 74 0_04 02 _5%
4
O
+3 VS
200 9/0 1/2 0 HP
CONN CONN CONN CONN EXPRESS
Bluetooth WWAN Fingerprint DOCK USB Camera DOCK
200 9/0 1/2 1 Int el WoW
R9 19 2 2_ 04 02 _5%
1 2
R9 20 2 2_ 04 02 _5%
1 2
R9 21 2 2_ 04 02 _5%
1 2
R9 22 2 2_ 04 02 _5%
1 2
R9 23 2 2_ 04 02 _5%
1 2
R9 24 2 2_ 04 02 _5%
1 2
R9 25 2 2_ 04 02 _5%
1 2
+3 VS
5
P
IN1 IN2
G
U 5
3
SN 7 4 AH C 1 G0 8D CKR _SC70-5
PL T _R ST#
1 2
@
3
R2 44 10K_0 40 2_ 5%
1 2
PC H _ XDP _G PIO 012 OC P#47
RU N SCI _ EC #35 TH E RM _S CI#4 PC H _ DD R _ RST4,5
200 9/0 7/0 2 HP SI-1b
LA N _D IS#26,27
PC H _ XDP _G PIO 1612 AL S_ EN #19 WW A N_D E T#28
200 9/0 4/1 0 HP DB-3
WW A N_T R AN S MI T_OFF#28 ,3 3 PC H _ XDP _G PIO 2812 ST P_PC I# SA TA_ CLKRE Q# PC H _ XDP _G PIO 3612 PC H _ XDP _G PIO 3712 ,19 DO C K _I D034 DO C K _I D134 CL K _ PC IE_L AN _REQ#26
200 8/1 2/1 2 HP
PC H _ XDP _G PIO 4912 WL A N _T R AN SMIT_ OF F#28
PC H _ NC TF 617 PC H _ NC TF 717
PC H _ NC TF 1917
PC H _ NC TF 2617
CL K _ PC I _ KBC _R
CL K _ P CI_DB _P CL K _ PC I_FB_R CL K _ P CI_TP M_R
CL K _ PCI _1 39 4_ R
US B _ OC #7 US B _ OC #6 US B _ OC #5
US B _ OC #1 US B _ OC #2 US B _ OC #3 PC H _ XD P_GPI O3 6
PC I _ GNT0# MO D EM _ DI SAB LE#
R1 22 7 0_0402_5% R1 13 9 0_0402_5% R1 09 7 0_0402_5%
R1 00 4 0_0402_5% R1 00 5 0_0402_5% R1 00 6 0_0402_5% R1 00 7 0_0402_5%
Security Classification
Issued Date
3
PC H _ XD P_GPI O0
RU N SCI _ EC# TH E RM _ SCI#
200 9/0 4/1 0 HP DB-3
G PIO15 PC H _ XD P_GPI O1 6 AL S _ EN# WW A N_D E T# G PIO24 WW A N_T R AN S M IT_ OF F#
ST P _P CI# SA TA_ C LK REQ # PC H _ XD P_GPI O3 6 PC H _ XD P_GPI O3 7 DO C K _ ID 0 DO C K _ ID 1
G PIO46 G PIO48 PC H _ XD P_GPI O4 9 WL A N _T R AN SMI T_O FF#
200 9/0 7/2 1 HP SI-2
1 2 1 2 1 2
1 2 1 2 1 2 1 2
R2 54 1 K_0402_5%@
1 2
R2 59 1 K_0402_5%@
1 2
U 4 F
Y3
BMBUSY# / GPIO0
C38
TACH1 / GPIO1
D37
TACH2 / GPIO6
J32
TACH3 / GPIO7
F10
GPIO8
K9
LAN_PHY_PWR_CTRL / GPIO12
T7
GPIO15
AA2
SATA4GP / GPIO16
F38
TACH0 / GPIO17
Y7
SCLOCK / GPIO22
H10
MEM_LED / GPIO24
AB12
GPIO27
V13
GPIO28
M11
STP_PCI# / GPIO34
V6
SATACLKREQ# / GPIO35
AB7
SATA2GP / GPIO36
AB13
SATA3GP / GPIO37
V3
SLOAD / GPIO38
P3
SDATAOUT0 / GPIO39
H3
PCIECLKRQ6# / GPIO45
F1
PCIECLKRQ7# / GPIO46
AB6
SDATAOUT1 / GPIO48
AA4
SATA5GP / GPIO49
F8
GPIO57
A4
VSS_NCTF_1
A49
VSS_NCTF_2
A5
VSS_NCTF_3
A50
VSS_NCTF_4
A52
VSS_NCTF_5
A53
VSS_NCTF_6
B2
VSS_NCTF_7
B4
VSS_NCTF_8
B52
VSS_NCTF_9
B53
VSS_NCTF_10
BE1
VSS_NCTF_11
BE53
VSS_NCTF_12
BF1
VSS_NCTF_13
BF53
VSS_NCTF_14
BH1
VSS_NCTF_15
BH2
VSS_NCTF_16
BH52
VSS_NCTF_17
BH53
VSS_NCTF_18
BJ1
VSS_NCTF_19
BJ2
VSS_NCTF_20
BJ4
VSS_NCTF_21
BJ49
VSS_NCTF_22
BJ5
VSS_NCTF_23
BJ50
VSS_NCTF_24
BJ52
VSS_NCTF_25
BJ53
VSS_NCTF_26
D1
VSS_NCTF_27
D2
VSS_NCTF_28
D53
VSS_NCTF_29
E1
VSS_NCTF_30
E53
VSS_NCTF_31
IB E XP EAK -M_ FCBGA 10 71
200 9/0 1/2 2 HP
CP P E# 31 LE D _ LIN K_LAN #_ R 26, 27 IS O _ PRE P# 34
BT _ OFF 32 WE B CA M _OF F F PR_ O FF 33 NP C I_R ST# 3 5, 36
PCI _GN T0#
0 0 1 1 1
2008/09/15 2009/12/31
Compal Secret Data
4
CLKOUT_PCIE6N CLKOUT_PCIE6P
CLKOUT_PCIE7N
MISC
CLKOUT_PCIE7P
CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLKOUT_BCLK0_P / CLKOUT_PCIE8P
GPIO
CPU
NCTF
RSVD
Dan bur y T ec hno log y Enable NV_ ALE H igh =E nda bled
Low =Di sab le (@)
NV _ ALE
R2 70 1K_ 04 02 _5 %@
DMI Te rmi na tio n Voltage NV_ CLE S et to Vs s w hen LOW
Set to Vc c whe n HIGH
NV _ C LE
R2 83 1K_ 04 02 _5 %@
Boo t B IOS Strap
MOD EM_ DIS ABLE# B oot BI OS Location
Deciphered Date
LPC*
0 1
Res erv ed( NAND) PCI
0
SPI
4
A20GATE
PROCPWRGD
THRMTRIP#
INIT3_3V#
1 2
1 2
AH45 AH46
AF48 AF47
U2
AM3 AM1 BG10
PECI
T1
RCIN#
BE10 BD10
BA22
TP1
AW22
TP2
BB22
TP3
AY45
TP4
AY46
TP5
AV43
TP6
AV45
TP7
AF13
TP8
M18
TP9
N18
TP10
AJ24
TP11
AK41
TP12
AK42
TP13
M32
TP14
N32
TP15
M30
TP16
N30
TP17
H12
TP18
AA23
TP19
AB45
NC_1
AB38
NC_2
AB42
NC_3
AB41
NC_4
T39
NC_5
P6 C10
TP24
+V _ NVR A M_V CCQ
+3 VS
200 9/0 7/2 2 HP SI-2
5
R2 23
CL K _ PC IE_ LA N#_R CL K _ PC IE_ LA N_R
PC H _ PE C I_R KB _ RST#
H_ T HERMTR IP#_L
T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 T48 T49 T50 T51 T52 T53 T54 T55 T56
T57 T58
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
0_ 0402_5%
1 2
0_ 0402_5%
1 2
R2 25
R2 4710 K_0 40 2_ 5%
1 2
1 2
1 2
R2 495 4.9_0402_1%
R2 50
56 _0402_5%
LA N _ DI S#
NP C I_ RST #
SA TA_ C LK REQ #
PC H _ XD P_GPI O4 9
WW A N_D E T#
AL S _ EN#
RU N SCI _ EC#
PC H _ XD P_GPI O1 6
DO C K _ ID 0
DO C K _ ID 1
G PIO48
ST P _P CI#
KB _ RST#
200 9/0 1/2 0 For BIOS
US B _ OC #2
WL A N _T R AN SMI T_O FF#
WW A N_T R AN S M IT_ OF F#
G PIO24
G PIO15
200 9/0 2/0 6 HP DB-2
IS O _ PR EP#
CL K _ PC I E_LAN_ REQ#
US B _ OC #0
CP P E#
US B _ OC #4
PC H _ XD P_GPI O2 8
200 8/1 2/1 2 HP
G PIO46
LE D _ L IN K_LAN #_ R
200 9/0 2/0 6 HP DB-2
CL K _ PC IE_LAN# 26 CL K _ PC IE_LAN 26
+3 VS
GA TEA 20 35
CL K _ CP U_BC LK# 4 CL K _ CP U_BC LK 4
R2 480_ 0402_5%
H_ P ECI 4 KB _R ST# 35 H_ C P UP W RGD 4 H_ T HER MTRIP# 4 ,2 0
12
+V C CP
200 9/0 4/1 0 HP DB-3
R2 86 10K_0 40 2_ 5%
1 2
R2 55 10K_0 40 2_ 5%
1 2
R2 60 10K_0 40 2_ 5%
1 2
R2 64 10K_0 40 2_ 5%
1 2
R2 66 100K_ 04 02 _5%
1 2
R2 68 10K_0 40 2_ 5%
1 2
R2 71 10K_0 40 2_ 5%
1 2
200 9/0 6/0 9 HP SI-2
R2 76 10K_0 40 2_ 5%
1 2
R2 78 10K_0 40 2_ 5%
1 2
R2 80 10K_0 40 2_ 5%
1 2
R2 82 10K_0 40 2_ 5%
1 2
R2 85 10K_0 40 2_ 5%
1 2
R6 94 10K_0 40 2_ 5%
1 2
200 9/0 5/0 2 HP SI-1
R1 19 3 10K_0 40 2_ 5%
1 2
R2 57 10K_0 40 2_ 5%
1 2
R2 62 10K_0 40 2_ 5%
1 2
R2 65 10K_0 40 2_ 5%
1 2
R2 67 1K_ 04 02 _5 %
1 2
R2 69 10K_0 40 2_ 5%
1 2
R2 72 10K_0 40 2_ 5%
1 2
R2 75 10K_0 40 2_ 5%
1 2
R2 79 10K_0 40 2_ 5%
1 2
R2 81 10K_0 40 2_ 5%
1 2
200 9/0 4/1 0 HP DB-3
R1 09 9 10K_0 40 2_ 5%
1 2
R4 98 10K_0 40 2_ 5%
1 2
R1 14 2 10K_0 40 2_ 5%
1 2
Compal Electronics, Inc.
IBEX-M(4/6)-PCI/USB/RSVD
LA -490 1 P
5
15 54T u esd ay , Dec ember 15, 2 00 9
LAN
+3 VM_L AN
+3 VS
+3 V AL W
1. 0
1
2
3
4
5
+1. 05 VS
1U _0 60 3_ 10 V4 Z
C2 31
C2 30
1
1
2
2
+1 .0 5VS
T11 4
200 9/0 1/2 2 HP DB-2
+1. 05 VS
1U_0402_6.3 V6 K
C2 4 7
C2 4 8
1
1
2
2
1U_0402_6.3 V6 K
1U_0402_6.3 V6 K
C2 51
C2 52
1
2
1 2
1 2
T11 7
1 2
1U_0402_6.3 V6 K
1 2
1U_0402_6.3 V6 K
C2 53
1
2
+3 VS
C8 8 10.1 U_ 04 02 _1 6V4 Z @
L5
C2 68
@
L6
C2 74
@
1
2
R6 74 0_0402_5%
+1 .0 5VS
10 UH_ LB 20 12 T10 0M R_ 20 %_0 80 5
10 UH_ LB 20 12 T10 0M R_ 20 %_0 80 5
+1 .0 5VM
1U_0402_6.3 V6 K
1
C2 35
2
A A
B B
C C
T59
200 9/0 2/0 5 HP DB-2
1 2
C2 59
1 2
C2 60
1 2
C2 64
1 2
C2 66
+R T CV CC
200 8/1 2/0 6 fol low UMA
0. 1U _0 40 2_ 16 V4Z
0. 1U _0 40 2_ 16 V4Z
0. 1U _0 40 2_ 16 V4Z
0. 1U _0 40 2_ 16 V4Z
C9 11
T11 2 T11 3
200 9/0 1/2 2 HP DB-2
1 2
C2 37 0 .1U_ 04 02 _1 6V 4Z
+1 .0 5VM
22 U_0805_6.3V 6M
22 U_0805_6.3V 6M
C2 44
C2 43
1
1
2
2
C2 46
+V C C RTCEXT
1 2
0. 1U _0 40 2_ 16 V4Z
+1 .8 VS
+V 1 .0 5S _VC CA_A_ DP L
+V 1 .0 5S _VC CA_B_ DP L
+1 .0 5VS
1U_0402_6.3 V6 K
1U_0402_6.3 V6 K
C2 55
C2 56
C2 57
1
1
2
2
+V 1 .1A _ I NT_ VCCSU S
+3 VALW
0. 2 A
0. 2 A@ 3.3 V
0. 2 A0. 2 A
+3 VS
0. 4 A
0. 4 A@ 3.3 V
0. 4 A0. 4 A
+V C CP
0. 1 A
0. 1 A@ 1.1 V
0. 1 A0. 1 A
4.7U_ 06 03 _6 .3 V6 K C2 71
C2 70
1
1
2
2
2m A @
2m A @3 .3V
2m A @2m A @
1U_0402_6.3 V6 K
0. 1U _0 40 2_ 16 V4Z
C2 77
C2 76
1
1
2
2
C2 40
C2 45
1
2
+V C C SST
@3. 3V
@3. 3V@3. 3V
@3. 3V
@3. 3V@3. 3V
@1. 1V
@1. 1V@1. 1V
0. 1U _0 40 2_ 16 V4Z
3.3 V
3.3 V3.3 V
1
2
1U_0402_6.3 V6 K
1
2
1U_0402_6.3 V6 K
1
2
1U_0402_6.3 V6 K
0. 1U _0 40 2_ 16 V4Z
C2 72
1
2
0. 1U _0 40 2_ 16 V4Z
U 4 J
AP51
VCCACLK[1]
AP53
VCCACLK[2]
AF23
VCCLAN[1]
AF24
VCCLAN[2]
Y20
DCPSUSBYP
AD38
VCCME[1]
AD39
VCCME[2]
AD41
VCCME[3]
AF43
VCCME[4]
AF41
VCCME[5]
AF42
VCCME[6]
V39
VCCME[7]
V41
VCCME[8]
V42
VCCME[9]
Y39
VCCME[10]
Y41
VCCME[11]
Y42
VCCME[12]
V9
DCPRTC
AU24
VCCVRM[3]
BB51
VCCADPLLA[1]
BB53
VCCADPLLA[2]
BD51
VCCADPLLB[1]
BD53
VCCADPLLB[2]
AH23
VCCIO[21]
AJ35
VCCIO[22]
AH35
VCCIO[23]
AF34
VCCIO[2]
AH34
VCCIO[3]
AF32
VCCIO[4]
V12
DCPSST
Y22
DCPSUS
P18
VCCSUS3_3[29]
U19
VCCSUS3_3[30]
U20
VCCSUS3_3[31]
U22
VCCSUS3_3[32]
V15
VCC3_3[5]
V16
VCC3_3[6]
Y16
VCC3_3[7]
AT18
V_CPU_IO[1]
AU18
V_CPU_IO[2]
A12
VCCRTC
IB E XP EA K-M_FCBG A1071
0.035A
0.072A
0.073A
>1mA
0.052A
0.344A
1.998A
3.208A
2mA
POWER
USB
Clock and Miscellaneous
PCI/GPIO/LPC
0.032A
SATA
CPU
RTC PCI/GPIO/LPC
0.163A
>1mA
>1mA
0.357A
6mA
HDA
VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8]
VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8]
VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCSUS3_3[21] VCCSUS3_3[22] VCCSUS3_3[23] VCCSUS3_3[24] VCCSUS3_3[25] VCCSUS3_3[26] VCCSUS3_3[27]
VCCSUS3_3[28]
VCCIO[56]
V5REF_SUS
V5REF
VCC3_3[8]
VCC3_3[9] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13]
VCC3_3[14]
VCCSATAPLL[1] VCCSATAPLL[2]
VCCIO[9]
VCCVRM[4]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCME[13] VCCME[14] VCCME[15] VCCME[16]
VCCSUSHDA
V24 V26 Y24 Y26
V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26
U23 V23 F24
K49
J38 L38 M36 N36 P36 U35
AD13
AK3 AK1
AH22
AT20
AH19 AD20 AF22 AD19
AF20 AF19 AH20
AB19 AB20 AB22 AD22
AA34 Y34 Y35 AA35
L30
+1 .0 5VS
1
C2 36 1U_0402_6.3 V6 K
2
+3 V AL W
0. 1U _0 40 2_ 16 V4Z
C2 38
1
2
+1 .0 5VS
IC H _ V5 R E F_ SUS
IC H _ V5 R E F_ R UN
+3 VS
1
C2 50
0. 1U _0 40 2_ 16 V4Z
2
+3 VS
1 2
C2 58 0.1U _0 40 2_ 16 V4 Z
T115 T116
200 9/0 1/2 2 HP DB-2
+1 .8 VS
+P C H _V CC1_1 _2 0 +P C H _V CC1_1 _2 1 +P C H _V CC1_1 _2 2 +P C H _V CC1_1 _2 3
+V C CSU SHD A
1
C2 7 5 1U _0 40 2_ 6. 3V6K
2
0. 1U _0 40 2_ 16 V4Z
C2 39
1
2
1U _0 40 2_ 6. 3V6K
C2 65
1
2
R2 95 0_04 02 _5 %
1 2
R2 96 0_04 02 _5 %
1 2
R2 97 0_04 02 _5 %
1 2
R2 98 0_04 02 _5 %
1 2
R3 0 1 0_ 0402_5%
1 2
+1 .8 VS
200 9/0 1/2 2 HP DB-2
+1. 05 VS
+1 .0 5VS
+1 .0 5VM
+3 VALW
U4 G
AB24
VCCCORE[1]
AB26
10 U_0805_6.3V 6M
VCCCORE[2]
AB28
VCCCORE[3]
AD26
VCCCORE[4]
AD28
VCCCORE[5]
AF26
VCCCORE[6]
AF28
VCCCORE[7]
AF30
VCCCORE[8]
AF31
VCCCORE[9]
AH26
VCCCORE[10]
AH28
VCCCORE[11]
AH30
VCCCORE[12]
AH31
VCCCORE[13]
AJ30
VCCCORE[14]
AJ31
VCCCORE[15]
AK24
VCCIO[24]
BJ24
VCCAPLLEXP
AN20
VCCIO[25]
AN22
VCCIO[26]
AN23
VCCIO[27]
AN24
VCCIO[28]
AN26
VCCIO[29]
AN28
VCCIO[30]
BJ26
VCCIO[31]
BJ28
VCCIO[32]
AT26
VCCIO[33]
AT28
VCCIO[34]
AU26
VCCIO[35]
AU28
1U_0402_6.3 V6 K
VCCIO[36]
AV26
VCCIO[37]
AV28
VCCIO[38]
AW26
VCCIO[39]
AW28
VCCIO[40]
BA26
VCCIO[41]
BA28
VCCIO[42]
BB26
VCCIO[43]
BB28
VCCIO[44]
BC26
VCCIO[45]
BC28
10 U_0805_6.3V 6M
VCCIO[46]
BD26
VCCIO[47]
BD28
VCCIO[48]
BE26
VCCIO[49]
BE28
VCCIO[50]
BG26
VCCIO[51]
BG28
VCCIO[52]
BH27
VCCIO[53]
AN30
VCCIO[54]
AN31
VCCIO[55]
AN35
VCC3_3[1]
AT22
VCCVRM[1]
BJ18
VCCFDIPLL
AM23
VCCIO[1]
IB E XP EAK -M_ FCBGA 10 71
+V 1 .0 5S _VC CA_A_ DP L
1
1
+
C2 67 22 0U _B 2_ 2.5VM _R15
2
2
+V 1 .0 5S _VC CA_B_ DP L
1
1
+
C2 73 22 0U _B 2_ 2.5VM _R15
2
2
@
@
POWER
1.524A
VCC CORE
0.042A
PCI E*
0.035A 6mA
200 9/0 4/2 4 HP SI-1
0.069A
CRTLVDS
0.030A
0.059A
HVCMOS
0.061A
DMI
0.156A
NAND / SPI
0.085A
FDI
VCCADAC[1]
VCCADAC[2] VSSA_DAC[1] VSSA_DAC[2]
VCCALVDS
VSSA_LVDS
VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4]
VCC3_3[2] VCC3_3[3] VCC3_3[4]
VCCVRM[2]
VCCDMI[1] VCCDMI[2]
VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] VCCPNAND[4] VCCPNAND[5] VCCPNAND[6] VCCPNAND[7] VCCPNAND[8] VCCPNAND[9]
VCCME3_3[1] VCCME3_3[2] VCCME3_3[3] VCCME3_3[4]
+V 1 .05 S_ VCCA_ A_DPL
+V 1 .05 S_ VCCA_ B_DPL
AE50 AE52 AF53 AF51
AH38 AH39
AP43 AP45 AT46 AT45
AB34 AB35 AD35
AT24
AT16 AU16
AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15
AM8 AM9 AP11 AP9
10 0_0402_5%
200 9/0 2/0 3 HP DB-2
+3 V S_V C CDAC
0.01U_0 60 3_ 16 V7K
10 U_0805_6.3V 6M
C2 32
C2 33
1
1
@
+3 VS
+1 .8VS
+V C CP
+V _ NVR A M_V CCQ
R2 99
@
@
2
2
200 9/0 4/1 3 Com pal DB-3
1 2
C2 42 0 .1U_ 04 02 _1 6V 4Z
1 2
C2 49 1 U_0603_10V4Z
R5 08 0 _0 60 3_ 5%
0. 1U _0 40 2_ 16 V4Z
C2 54
1
2
+3 VM
0. 1U _0 40 2_ 16 V4Z
C2 61
1
2
12
21
D 2
CH 7 51 H-40PT_SOD 32 3- 2
1
C2 78 1U_0402_6.3 V6 K
2
1 2
0. 1U _0 40 2_ 16 V4Z MU R AT A_ BLM18 AG 60 1SN 1D _0 60 3
C2 34
1
2
1 2
200 9/0 8/3 0 HP PV
200 9/0 1/2 2 HP DB-2
IC H _ V5 R E F_ SUS
L40
+3 VS
+1 .8 VS
+5 VS + 3V S+3V AL W+ 5 VALW
12
R3 00
10 0_0402_5%
200 9/0 2/0 3 HP DB-2
21
D 3 CH 7 51 H-40PT_SOD 32 3- 2
IC H _ V5 R E F_ R UN
20 mils20 mils
1
C2 7 9 1U _0 40 2_ 6. 3V6K
2
D D
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
IBEX-M(5/6)-PWR
LA -490 1 P
5
16 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
2
3
4
5
U4 I
AY7
VSS[159]
B11
VSS[160]
B15
VSS[161]
B19
VSS[162]
B23
VSS[163]
B31
VSS[164]
B35
VSS[165]
B39
VSS[166]
B43
VSS[167]
B47
VSS[168]
B7
A A
B B
C C
VSS[169]
BG12
VSS[170]
BB12
VSS[171]
BB16
VSS[172]
BB20
VSS[173]
BB24
VSS[174]
BB30
VSS[175]
BB34
VSS[176]
BB38
VSS[177]
BB42
VSS[178]
BB49
VSS[179]
BB5
VSS[180]
BC10
VSS[181]
BC14
VSS[182]
BC18
VSS[183]
BC2
VSS[184]
BC22
VSS[185]
BC32
VSS[186]
BC36
VSS[187]
BC40
VSS[188]
BC44
VSS[189]
BC52
VSS[190]
BH9
VSS[191]
BD48
VSS[192]
BD49
VSS[193]
BD5
VSS[194]
BE12
VSS[195]
BE16
VSS[196]
BE20
VSS[197]
BE24
VSS[198]
BE30
VSS[199]
BE34
VSS[200]
BE38
VSS[201]
BE42
VSS[202]
BE46
VSS[203]
BE48
VSS[204]
BE50
VSS[205]
BE6
VSS[206]
BE8
VSS[207]
BF3
VSS[208]
BF49
VSS[209]
BF51
VSS[210]
BG18
VSS[211]
BG24
VSS[212]
BG4
VSS[213]
BG50
VSS[214]
BH11
VSS[215]
BH15
VSS[216]
BH19
VSS[217]
BH23
VSS[218]
BH31
VSS[219]
BH35
VSS[220]
BH39
VSS[221]
BH43
VSS[222]
BH47
VSS[223]
BH7
VSS[224]
C12
VSS[225]
C50
VSS[226]
D51
VSS[227]
E12
VSS[228]
E16
VSS[229]
E20
VSS[230]
E24
VSS[231]
E30
VSS[232]
E34
VSS[233]
E38
VSS[234]
E42
VSS[235]
E46
VSS[236]
E48
VSS[237]
E6
VSS[238]
E8
VSS[239]
F49
VSS[240]
F5
VSS[241]
G10
VSS[242]
G14
VSS[243]
G18
VSS[244]
G2
VSS[245]
G22
VSS[246]
G32
VSS[247]
G36
VSS[248]
G40
VSS[249]
G44
VSS[250]
G52
VSS[251]
AF39
VSS[252]
H16
VSS[253]
H20
VSS[254]
H30
VSS[255]
H34
VSS[256]
H38
VSS[257]
H42
VSS[258]
IB E XP EAK -M_ FCBGA 10 71
VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[326] VSS[327] VSS[328] VSS[329] VSS[330] VSS[331] VSS[332] VSS[333] VSS[334] VSS[335] VSS[336] VSS[337] VSS[338] VSS[339] VSS[340] VSS[341] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] VSS[353] VSS[354] VSS[355] VSS[356] VSS[366]
H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14
U 4 H
AB16
VSS[0]
AA19
VSS[1]
AA20
VSS[2]
AA22
VSS[3]
AM19
VSS[4]
AA24
VSS[5]
AA26
VSS[6]
AA28
VSS[7]
AA30
VSS[8]
AA31
VSS[9]
AA32
VSS[10]
AB11
VSS[11]
AB15
VSS[12]
AB23
VSS[13]
AB30
VSS[14]
AB31
VSS[15]
AB32
VSS[16]
AB39
VSS[17]
AB43
VSS[18]
AB47
VSS[19]
AB5
VSS[20]
AB8
VSS[21]
AC2
VSS[22]
AC52
VSS[23]
AD11
VSS[24]
AD12
VSS[25]
AD16
VSS[26]
AD23
VSS[27]
AD30
VSS[28]
AD31
VSS[29]
AD32
VSS[30]
AD34
VSS[31]
AU22
VSS[32]
AD42
VSS[33]
AD46
VSS[34]
AD49
VSS[35]
AD7
VSS[36]
AE2
VSS[37]
AE4
VSS[38]
AF12
VSS[39]
Y13
VSS[40]
AH49
VSS[41]
AU4
VSS[42]
AF35
VSS[43]
AP13
VSS[44]
AN34
VSS[45]
AF45
VSS[46]
AF46
VSS[47]
AF49
VSS[48]
AF5
VSS[49]
AF8
VSS[50]
AG2
VSS[51]
AG52
VSS[52]
AH11
VSS[53]
AH15
VSS[54]
AH16
VSS[55]
AH24
VSS[56]
AH32
VSS[57]
AV18
VSS[58]
AH43
VSS[59]
AH47
VSS[60]
AH7
VSS[61]
AJ19
VSS[62]
AJ2
VSS[63]
AJ20
VSS[64]
AJ22
VSS[65]
AJ23
VSS[66]
AJ26
VSS[67]
AJ28
VSS[68]
AJ32
VSS[69]
AJ34
VSS[70]
AT5
VSS[71]
AJ4
VSS[72]
AK12
VSS[73]
AM41
VSS[74]
AN19
VSS[75]
AK26
VSS[76]
AK22
VSS[77]
AK23
VSS[78]
AK28
VSS[79]
IB E XP EAK -M_ FCBGA 10 71
VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]
VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]
AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26 AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47
+3 VS
12
R3 02
10 0K_ 04 02 _5%
PC H _ NC T F615
+3 VS
R3 03
10 0K_ 04 02 _5%
PC H _ NC T F715
+3 VS
R3 04
10 0K_ 04 02 _5%
PC H _ NC T F1915
+3 VS
R3 05
10 0K_ 04 02 _5%
PC H _ NC T F2615
12
12
2
12
5
61
Q9 A 2N 7 002DWH _SOT3 63 -6
2
34
Q9 B 2N 7 002DWH _SOT3 63 -6
5
61
Q1 0A 2N 7 002DWH _SOT3 63 -6
34
Q1 0B 2N 7 002DWH _SOT3 63 -6
CR A CK_ B GA
CR A CK_ B GA
CR A CK_ B GA
CR A CK_ BG A 8, 35
BGA Ball Cracking Prevention and Detection
D D
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
IBEX-M(6/6)-GND
LA- 4901P
5
17 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
CRT Connector
DA C _ RE D20
DA C _ GR N20
DA C _ BL U20
GPU
A A
L
Place cloce to GPU
B B
DA C _ RE D
DA C _ GR N
DA C _ B LU
74 A HCT 1G 12 5G W_SOT 353- 5
C R T_ H S YN C20
CR T _VS YNC20
10 P_0 40 2_ 50 V8J
C2 84
1
@
2
10 P_0 40 2_ 50 V8J
1
@
2
L7 CS0 80 5- 68 NJ -S_0805
1 2
L9 CS0 80 5- 68 NJ -S_0805
1 2
L1 1 CS0 80 5- 68 NJ -S_0805
1 2
10 P_0 40 2_ 50 V8J
C2 85
C2 86
1
@
2
+5 VS + 5V S
C2 90
0. 1U _0 40 2_ 16 V4Z
5
P
A2Y
G
3
1 2
1
U 6
OE#
1
2
4
5
A2Y
3
DA C _ RE D _ R
DA C _ GR N _ R
DA C _ BL U_R
27 P_0 40 2_ 50 V8J
C2 91
0. 1U _0 40 2_ 16 V4Z
P
G
27 P_0 40 2_ 50 V8J
27 P_0 40 2_ 50 V8J
C2 87
C2 88
1
1
2
2
1 2
H S Y N C
1
U7
V S Y N C
4
OE#
74 A HCT 1G 12 5G W_SOT 353- 5
Place cloce to VGA
L
L8 CS0 80 5- 68 NJ -S_0805
1 2
L1 0 CS0 80 5- 68 NJ -S_0805
1 2
L1 2 CS0 80 5- 68 NJ -S_0805
1 2
C2 89
R3 16 0 _0 40 2_ 5%
R3 17 0 _0 40 2_ 5%
2
VG A _ RED34
VG A _ GRN34
VG A _BLU34
SW >> Port
200 8/1 2/0 6 Nvidia
1 2
1 2
C2 92
5P_ 04 02 _5 0V 8C
R E D_ R 34
GR E EN_ R 34
BL U E_R 34
C9 42
1
2
1
2
GPU >> SW
L48 FC M1 60 8C F-1 21 T0 3_ 2P
L49 FC M1 60 8C F-1 21 T0 3_ 2P
L50 FC M1 60 8C F-1 21 T0 3_ 2P
10 P_0 40 2_ 50 V8J
10 P_0 40 2_ 50 V8J
10 P_0 40 2_ 50 V8J
C9 43
C9 44
1
1
2
2
D _ HS Y NC
D _ V SYN C
1
C2 93 5P_ 04 02 _5 0V 8C
2
layout note: D_HSYNC & D_VSYNC should be routed to docking connector then to VGA connector
1 2
1 2
1 2
200 9/0 2/1 8 Com pal DB-2 EMI
D _ H S Y NC 34
D _ V SYN C 34
3
200 9/0 9/1 0 HP PV
GN D _ C RT
R3 14 75 _0 40 2_ 1%
12
0_ 0402_5%
2
NC
CH 4 91 DPT_SO T2 3- 3
3
0. 1U _0 40 2_ 16 V4Z
12
R1 24 4
D 4
F1
GN D _ C RT
D_ D D CC L K34
21
R3 13 75 _0 40 2_ 1%
R3 12 75 _0 40 2_ 1%
12
12
1. 1 A_ 8V _SMD1 81 2P110 TF( HF )
10 P_0 40 2_ 50 V8 J
C2 81
1
2
10 P_0 40 2_ 50 V8 J
10 P_0 40 2_ 50 V8 J
C2 83
C2 82
1
1
2
2
1
4
1
C2 80
2
VG A _ R ED_ R D_ D D CD A TA
VG A _ G RN _R
VG A _ BL UE_R
D_ D D CC L K
+C R TV D D+R C RT_ VC C+5 VS
W=40mils
JP 4
C O N N @
6
11
1 7
12
2 8
13
3 9
14
4 10 15
5
SU Y IN _ 0 7 09 12 FR0 15 S2 29 ZR
+C R TV DD +3 VS
R3 18
4.7K_ 04 02 _5 %
12
L
VG A _ BL UE_R VG A _ G RN _R VG A _ R ED_ R D _ HS Y NC D _ V SYN C
16
G
17
G
R3 19
4.7K_ 04 02 _5 %
12
200 9/0 2/2 4 Nvi dia DB-2
2
Q4 A
6 1
2N 7 0 02 KD WH_ SO T363- 6
Q4 B
2N 7 0 02 KD WH_ SO T363- 6
Place cloce to VGA
3 4
5
1
D 6
@
2
3
R3 21
R3 20
4.7K_ 04 02 _5 %
12
200 9/0 2/1 8 Com pal DB-2 EMI
DA N217GT1 46 _S C59-3
1
D 7
@
2
3
DA N217GT1 46 _S C59-3
1
D 5
@
2
3
4.7K_ 04 02 _5 %
12
DA N217GT1 46 _S C59-3
DA N217GT1 46 _S C59-3
1
D8
@
2
3
CR T _DD C _ DAT A 20D_ D D CD A TA34
DA N217GT1 46 _S C59-3
1
D 9
@
2
3
+C R TV D D
5
CR T _DD C _ CLK 20
R1 11 4 0_0402_5%
Display Port Connector
R1 11 2 0_0 40 2_ 5%
1 2
L42
@
MB _D PA_ TXN 222
MB _D PA_ TXP 222
C C
MB _D PA_ TXP 122
MB _D PA_ TXN 122
MB _D PA_ TXP 322
MB _D PA_ TXN 322
D D
MB _D PA_ TXN 022
MB _D PA_ TXP 022
1
1
4
4
WCM -2 01 2- 90 0T_ 4P
1 2
R1 11 5 0_0 40 2_ 5%
R1 11 8 0_0 40 2_ 5%
1 2
L45
@
1
1
4
4
WCM -2 01 2- 90 0T_ 4P
1 2
R1 12 0 0_0 40 2_ 5%
R1 11 3 0_0 40 2_ 5%
1 2
L43
@
1
1
4
4
WCM -2 01 2- 90 0T_ 4P
1 2
R1 11 6 0_0 40 2_ 5%
R1 11 9 0_0 40 2_ 5%
1 2
L46
@
1
1
4
4
WCM -2 01 2- 90 0T_ 4P
1 2
R1 12 1 0_0 40 2_ 5%
1
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
MB _ DPA _TXN2 _L
MB_D PA_ TXP 2_ L
200 8/1 2/1 7 EMI DB
MB_D PA_ TXP 1_ L
MB _ DPA _TXN1 _L
MB_D PA_ TXP 3_ L
MB _ DPA _TXN3 _L
MB _ DPA _TXN0 _L
MB_D PA_ TXP 0_ L
MB _ DP A_AUX L#
MB _ DP A_AUX L
MB _ DPA _AUX22
MB _ DPA _AUX#22
1 2
L44
@
1
1
4
4
WCM -2 01 2- 90 0T_ 4P
1 2
R1 11 7 0_0402_5%
6 1
2N 7 002KDW H_SOT 36 3- 6
2N 7 002KDW H_SOT 36 3- 6
6 1
MB _ DP _ HPD22
2
MB _ DP A_AUX #_ L
2
2
MB _ DP A_AUX _L
3
3
C3 500.1U_ 04 02 _1 0V 7K
1 2
200 8/1 2/1 2 Nvi dia re quest to P22
Q6 5A
2
2
Q6 6A
4
4
1 2
Q6 5B
2N 7 002KDW H_SOT 36 3- 6
5
5
2N 7 0 02 KD WH_ SO T363- 6
Q6 6B
C3 490.1U_ 04 02 _1 0V 7K
1 2
0_ 0402_5%
12
R1 09 1 10 0K_ 04 02 _5 %
3
3
R1 08 8
200 9/0 6/3 0 SI-2
MB _ DP A_AUX L
DD C 1 _EN
MB _ DP A_AUX L#
DP A _HP D
C9 57
0. 1U _0 40 2_ 16 V4Z
200 9/0 4/0 9 HP DB-3
MB _ DP A_AUX #_ L MB _ DP A_AUX _L
CA _ D ET22
+5 VS +5 VS
12
200 8/1 2/0 6 Nvidia
R9 84 10 K_0 40 2_ 5%
R9 85
61
1
2N 7 002KDW H_SOT 36 3- 6
2
Q6 7A
Security Classification
Issued Date
3
10 K_0 40 2_ 5%
1 2
2
3
Q6 7B 2N 7 002KDW H_SOT 36 3- 6
CA _ D ET
5
200 9/0 2/2 6 Nvi dia DB-2
4
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
MB _ DPA _TXN3 _L MB_D PA_ TXP 3_ L
MB _ DPA _TXN2 _L MB_D PA_ TXP 2_ L
MB _ DPA _TXN1 _L MB_D PA_ TXP 1_ L
MB _ DPA _TXN0 _L MB_D PA_ TXP 0_ L
D6 5
@
F2
SD M10 U4 5- 7_ SO D523-2
NA N O SM D C0 5 0 F 0 .5 A 1 3. 2V PO LY -FU SE
+3 VS
12
21
R9 56 0_ 1206_5%
+3 VS_D P
C8 4 1
1
2 1
2
C3 51 0.1U_ 04 02 _1 0V 7K
1 2
C3 52 0.1U_ 04 02 _1 0V 7K
1 2
C3 53 0.1U_ 04 02 _1 0V 7K
1 2
C3 54 0.1U_ 04 02 _1 0V 7K
1 2
C3 55 0.1U_ 04 02 _1 0V 7K
1 2
C3 56 0.1U_ 04 02 _1 0V 7K
1 2
C8 50 0.1U_ 04 02 _1 0V 7K
1 2
C8 51 0.1U_ 04 02 _1 0V 7K
1 2
+D PA _3 V
C8 4 2
10 U_ 08 05 _1 0V 4Z
0. 1U _0 40 2_ 16 V4Z
1
2
+3 V S_ DP
+3 V S_DP
DP A _HP D
200 9/0 2/1 2 Nvi dia DB-2
CA _ D ET DP A _TXN3_C
DP A _TX P3_C DP A _TXN2_C
DP A _TX P2_C DP A _TXN1_C
DP A _TX P1_C DP A _TXN0_C
DP A _TX P0_C
CA _ D ET
MB _ DP A_AUX #_ L
MB _ DP A_AUX _L
Tit le
Size Do c u me nt N umb er R e v
Da t e: She et o f
Compal Electronics, Inc.
CRT & DP Connector
LA -490 1 P
JD P 1
C O N N@
20
DP_PWR
19
RTN
18
HP_DET
17
AUX_CH-
16
GND
15
AUX_CH+
14
GND
13 12 11 10
9 8 7 6 5 4 3 2 1
200 8/1 2/1 9 Nvidia
R1 06 5 1M_ 04 02 _5 %
1 2
200 9/0 2/1 2 Nvi dia DB-2
R9 73 100K_ 04 02 _5%
1 2
R9 74 100K_ 04 02 _5%@
1 2
R9 60 100K_ 04 02 _5%@
1 2
R9 61 100K_ 04 02 _5%
1 2
5
GND
CA_DET
GND
LANE3-
GND
LANE3_shield
GND
LANE3+ LANE2­LANE2_shield LANE2+ LANE1­LANE1_shield LANE1+ LANE0­LANE0_shield LANE0+
MOL EX_10 50 20 -0001
18 54T u esd ay , Dec ember 15, 2 00 9
24 23 22 21
+3 VS
+3 VS
1. 0
1
2
3
4
5
LCD/PANEL BD. CONN.
+L C D VD D+3 VS
47 P_0 40 2_ 50 V8J
68 0P_ 04 02 _5 0V7K
C2 97
68 0P_ 04 02 _5 0V 7K
A A
@
2
1
12
C2 96
C2 98
1
2
R1 24 8
@
22 0K_ 04 02 _5 %
R1 24 9
@
10 0K_ 04 02 _5 %
R1 25 2 0_0805_5% SI2 30 3C DS-T1 -E3_SOT 23 -3
0.22U_0 60 3_ 25 V7 K
12
1
@
2
12
1 2
@
D
S
13
Q96
C1 00 0
G
2
200 9/0 9/1 6 HP SI-2b
IN V PW R _B +B+
1U_0805_25V6K
47 P_0 40 2_ 50 V8J
1
@
2
C1 00 2
C1 00 1
1
2
Key_Board_Light power Control
+5 VKBL +5 VS + 5 VS
SI2 30 1C DS-T1 -G E3_SO T23- 3
1 3
200 9/0 1/2 2 HP DB-2
Q7 1
S
D
G
2
12
R1 13 4
10 K_0 40 2_ 5%
2
1 3
D
Q72 2N7002H_S OT2 3- 3
LI D _ SW#
G
S
DI S P_ O FF#
200 9/0 3/0 8 DB-3
200 8/1 2/0 6 Nvi dia DB-1
200 9/0 3/0 8 HP SI-1
CH 7 51 H-40PT_SOD 32 3- 2
200 9/0 6/3 0 HP SI-1b 200 9/0 8/3 0 HP PV
200 9/0 3/0 8 DB-3
1 2
R1 17 1 2K_ 04 02 _5 %
2 1
EN A BL T
D1 4
LI D _ SW#
12
200 8/1 2/0 6 Nvi dia DB-1
R3 3 3
10 K_0 40 2_ 1%
EN A BLT 20
LI D _S W# 3 1, 35
200 9/0 1/2 0 Nvi dia DB -2 DP add Cap.
B B
C C
D D
DP D_ TXP021 DP D _TXN021
IN V _ PW M20 AL S _E N#15
+5 VKB L
200 8/1 2/1 2 for ke ybo ard light
+3 VS
+L C D VD D
PC H _ XDP _G PIO 3712 ,1 5
1 2 1 2
1 2
200 9/0 6/0 2 SI-2
R9 11 0 _0 80 5_ 5%
1 2
DP D _ TXP0_C
C9 160.1U_ 04 02 _1 0V 7K C9 170.1U_ 04 02 _1 0V 7K
DP D _ TXN0_ C
DI S P_ O FF# US B 2 0_ N1 2_ R
C3 08680P_ 04 02 _5 0V 7K
WE B CA M _ON
+L C D VD D _R
R3 41 0 _0 40 2_ 5%
1 2
200 9/0 4/2 4 SI-1
JE D P1
C O N N @
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
0.6A
25
27
27
29
29
31
G1
ACE S_50238 -030 71 -002
200 9/0 2/0 2 DB- 2 c han ge EDP CONN. 200 9/0 9/1 5 SI- 2b cha nge EDP CONN.
0.6A
2 4 6
8 10 12 14 16 18 20 22 24 26 28 30
G2
10 0K_ 04 02 _5%
12
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
WE B CA M _ON
R3 34
200 9/0 1/2 0 Nvi dia DB -2 DP add Cap.
DP D _ A UX_ C
C9 1 4 0.1U_0 40 2_ 10 V7 K
1 2
C9 1 5 0.1U_0 40 2_ 10 V7 K
DP D _ AU X#_C US B 20_P12 _R
1 2
200 9/0 4/2 4 SI-1
DP D _ DP _ H PD 20
+5 VS
200 9/0 6/0 2 SI-2
IN V PW R _B +
200 9/0 6/3 0 Com pal SI-2
DP D _ AU X#_C DP D _ A UX_ C
DP D _ AUX 21 DP D _A UX# 21
R1 05 0 100 K_0402_5%
1 2
R1 04 9 100 K_0402_5%
1 2
47 P_0 40 2_ 50 V8J
C3 02
1
@
2
0. 1U _0 40 2_ 16 V4Z
0.01U_0 40 2_ 16 V7 K C3 04
C3 03
1
1
2
2
+5 VS
R3 39 0 _0 40 2_ 5%
1 2
L36
@
+3 VS
1
1
4
4
WCM -2 01 2- 90 0T_ 4P
R3 40 0 _0 40 2_ 5%
1 2
2
3
2
2
3
3
US B 20_P12 _RUS B 2 0_ N1 2_ R
D1 3
@
PJ D LC 05 H_SOT 23 -3
US B2 0_ P1 2 15
US B 20 _N12 15
200 9/0 4/2 4 SI-1
1
4. 7U _0 80 5_ 10 V4Z
C3 05
1
2
LCD POWER CIRCUIT
E N AV D D20
SS M3 K7002F_ SC5 9- 3
10 K_0 40 2_ 1%
200 8/1 2/0 6 Nvidia
R3 45
Q1 5
C3 10
1
2
SI2 30 1C DS-T1 -G E3_SO T23-3
1 3
D
G
2
R3 43 1 M_0402_5%
C3 09 0 .1 U_ 04 02 _1 6V4Z
1
C3 11
4. 7U _0 80 5_ 10 V4Z
2
S
1 2
1 2
12
R3 4 2 10 0_0402_1%
13
D
Q1 1
12
2
G
S
2
IN
R3 4 4 47 K_0 40 2_ 5%
1 2
0. 1U _0 40 2_ 16 V4Z
1
OUT
GND
Q1 6 DT C 124EKAGZT146 _S C5 9- 3
3
+3 VS+L C D VD D+L CD V DD
1
C3 12
4. 7U _0 80 5_ 10 V4Z
2
@
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Da t e: She et o f
Compal Electronics, Inc.
LCD & eDP CONN.
LA -490 1 P
5
19 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
200 8/1 1/2 1 Swa p P CIE for Layout
PC IE _C TX_ GR X_P 155 PC I E_ CTX_GRX_ N1 55 PC IE _C TX_ GR X_P 145 PC I E_ CTX_GRX_ N1 45 PC IE _C TX_ GR X_P 135 PC I E_ CTX_GRX_ N1 35 PC IE _C TX_ GR X_P 125 PC I E_ CTX_GRX_ N1 25 PC IE _C TX_ GR X_P 115
A A
B B
C C
D D
PC I E_ CTX_GRX_ N1 15 PC IE _C TX_ GR X_P 105 PC I E_ CTX_GRX_ N1 05 PC IE _C TX_ GR X_P 95 PC I E_ CTX_GRX_ N95 PC IE _C TX_ GR X_P 85 PC I E_ CTX_GRX_ N85 PC IE _C TX_ GR X_P 75 PC I E_ CTX_GRX_ N75 PC IE _C TX_ GR X_P 65 PC I E_ CTX_GRX_ N65 PC IE _C TX_ GR X_P 55 PC I E_ CTX_GRX_ N55 PC IE _C TX_ GR X_P 45 PC I E_ CTX_GRX_ N45 PC IE _C TX_ GR X_P 35 PC I E_ CTX_GRX_ N35 PC IE _C TX_ GR X_P 25 PC I E_ CTX_GRX_ N25 PC IE _C TX_ GR X_P 15 PC I E_ CTX_GRX_ N15 PC IE _C TX_ GR X_P 05 PC I E_ CTX_GRX_ N05
PC IE _C RX_ GT X_P 155 PC I E_ CRX _G TX_ N1 55 PC IE _C RX_ GT X_P 145 PC I E_ CRX _G TX_ N1 45 PC IE _C RX_ GT X_P 135 PC I E_ CRX _G TX_ N1 35 PC IE _C RX_ GT X_P 125 PC I E_ CRX _G TX_ N1 25 PC IE _C RX_ GT X_P 115 PC I E_ CRX _G TX_ N1 15 PC IE _C RX_ GT X_P 105 PC I E_ CRX _G TX_ N1 05 PC IE _C RX_ GT X_P 95 PC I E_ CRX _G TX_ N95 PC IE _C RX_ GT X_P 85 PC I E_ CRX _G TX_ N85 PC IE _C RX_ GT X_P 75 PC I E_ CRX _G TX_ N75 PC IE _C RX_ GT X_P 65 PC I E_ CRX _G TX_ N65 PC IE _C RX_ GT X_P 55 PC I E_ CRX _G TX_ N55 PC IE _C RX_ GT X_P 45 PC I E_ CRX _G TX_ N45 PC IE _C RX_ GT X_P 35 PC I E_ CRX _G TX_ N35 PC IE _C RX_ GT X_P 25 PC I E_ CRX _G TX_ N25 PC IE _C RX_ GT X_P 15 PC I E_ CRX _G TX_ N15 PC IE _C RX_ GT X_P 05 PC I E_ CRX _G TX_ N05
CL K _ PEG _V GA13 CL K _ PEG _V GA#13
PL T_RST#4,12,15 ,2 6, 28 ,3 1,33
C3 44 0.1U_0 40 2_ 10 V7 K
1 2
C3 45 0.1U_0 40 2_ 10 V7 K
1 2
C3 42 0.1U_0 40 2_ 10 V7 K
1 2
C3 43 0.1U_0 40 2_ 10 V7 K
1 2
C3 40 0.1U_0 40 2_ 10 V7 K
1 2
C3 41 0.1U_0 40 2_ 10 V7 K
1 2
C3 38 0.1U_0 40 2_ 10 V7 K
1 2
C3 39 0.1U_0 40 2_ 10 V7 K
1 2
C3 36 0.1U_0 40 2_ 10 V7 K
1 2
C3 37 0.1U_0 40 2_ 10 V7 K
1 2
C3 34 0.1U_0 40 2_ 10 V7 K
1 2
C3 35 0.1U_0 40 2_ 10 V7 K
1 2
C3 32 0.1U_0 40 2_ 10 V7 K
1 2
C3 33 0.1U_0 40 2_ 10 V7 K
1 2
C3 30 0.1U_0 40 2_ 10 V7 K
1 2
C3 31 0.1U_0 40 2_ 10 V7 K
1 2
C3 28 0.1U_0 40 2_ 10 V7 K
1 2
C3 29 0.1U_0 40 2_ 10 V7 K
1 2
C3 26 0.1U_0 40 2_ 10 V7 K
1 2
C3 27 0.1U_0 40 2_ 10 V7 K
1 2
C3 24 0.1U_0 40 2_ 10 V7 K
1 2
C3 25 0.1U_0 40 2_ 10 V7 K
1 2
C3 22 0.1U_0 40 2_ 10 V7 K
1 2
C3 23 0.1U_0 40 2_ 10 V7 K
1 2
C3 20 0.1U_0 40 2_ 10 V7 K
1 2
C3 21 0.1U_0 40 2_ 10 V7 K
1 2
C3 18 0.1U_0 40 2_ 10 V7 K
1 2
C3 19 0.1U_0 40 2_ 10 V7 K
1 2
C3 16 0.1U_0 40 2_ 10 V7 K
1 2
C3 17 0.1U_0 40 2_ 10 V7 K
1 2
C3 14 0.1U_0 40 2_ 10 V7 K
1 2
C3 15 0.1U_0 40 2_ 10 V7 K
1 2
R3 6 5 20 0_0402_1%@
R3 6 6 2.49K_0 40 2_ 1% R3 6 7 0_ 0402_5%
+3 VS
R1 2 4 10 K_0 40 2_ 5%
1 2
1 2 1 2 1 2
PCIE_CRX_ GTX_G_P15 PCIE_CRX_ GTX_G_N15 PC I E_ CRX _G TX_ G_ P1 4 PC I E_ CRX _G TX_ G_ N1 4 PC I E_ CRX _G TX_ G_ P1 3 PC I E_ CRX _G TX_ G_ N1 3 PC I E_ CRX _G TX_ G_ P1 2 PC I E_ CRX _G TX_ G_ N1 2 PC I E_ CRX _G TX_ G_ P1 1 PC I E_ CRX _G TX_ G_ N1 1 PC I E_ CRX _G TX_ G_ P1 0 PC I E_ CRX _G TX_ G_ N1 0 PC I E_ CRX _G TX_ G_ P9 PC I E_ CR X_GTX _G _N9 PCIE_CRX_ GTX_G_P8 PCIE_CRX_ GTX_G_N8 PCIE_CRX_ GTX_G_P7 PCIE_CRX_ GTX_G_N7 PCIE_CRX_ GTX_G_P6 PCIE_CRX_ GTX_G_N6 PCIE_CRX_ GTX_G_P5 PCIE_CRX_ GTX_G_N5 PCIE_CRX_ GTX_G_P4 PCIE_CRX_ GTX_G_N4 PCIE_CRX_ GTX_G_P3 PCIE_CRX_ GTX_G_N3 PCIE_CRX_ GTX_G_P2 PCIE_CRX_ GTX_G_N2 PCIE_CRX_ GTX_G_P1 PCIE_CRX_ GTX_G_N1 PCIE_CRX_ GTX_G_P0 PCIE_CRX_ GTX_G_N0
P EX_ RST#
U8 A
AE12 AF12 AG12 AG13 AF13 AE13 AE15 AF15 AG15 AG16 AF16 AE16 AE18 AF18 AG18 AG19 AF19 AE19 AE21 AF21 AG21 AG22 AF22 AE22 AE24 AF24 AG24 AF25 AG25 AG26 AF27 AE27
AD10 AD11 AD12 AC12 AB11 AB12 AD13 AD14 AD15 AC15 AB14 AB15 AC16 AD16 AD17 AD18 AC18 AB18 AB19 AB20 AD19 AD20 AD21 AC21 AB21 AB22 AC22 AD22 AD23 AD24 AE25 AE26
AB10 AC10
AF10 AE10
AG10
AD9 AE9
N10M- GL M-S-A 3_ BGA 53 3
27 M_ CLK11
2
Pa r t 1 o f 5
PEX_RX0 PEX_RX0_N PEX_RX1 PEX_RX1_N PEX_RX2 PEX_RX2_N PEX_RX3 PEX_RX3_N PEX_RX4 PEX_RX4_N PEX_RX5 PEX_RX5_N PEX_RX6 PEX_RX6_N PEX_RX7 PEX_RX7_N PEX_RX8 PEX_RX8_N PEX_RX9 PEX_RX9_N PEX_RX10 PEX_RX10_N PEX_RX11 PEX_RX11_N PEX_RX12 PEX_RX12_N PEX_RX13 PEX_RX13_N PEX_RX14 PEX_RX14_N PEX_RX15 PEX_RX15_N
PEX_TX0 PEX_TX0_N PEX_TX1 PEX_TX1_N PEX_TX2 PEX_TX2_N PEX_TX3 PEX_TX3_N PEX_TX4 PEX_TX4_N PEX_TX5 PEX_TX5_N PEX_TX6 PEX_TX6_N PEX_TX7 PEX_TX7_N PEX_TX8 PEX_TX8_N PEX_TX9 PEX_TX9_N PEX_TX10 PEX_TX10_N PEX_TX11 PEX_TX11_N PEX_TX12 PEX_TX12_N PEX_TX13 PEX_TX13_N PEX_TX14 PEX_TX14_N PEX_TX15 PEX_TX15_N
PEX_REFCLK PEX_REFCLK_N
PEX_TSTCLK_OUT PEX_TSTCLK_OUT_N
PEX_TERMP PEX_RST_N PEX_CLKREQ_N
X TAL OUT
27 MHZ_1 6P F_X 7T0 27 00 0B G1 H- V
1
C8 24 20 P_0 40 2_ 50V8
2
N1
GPIO0
G1
GPIO1
C1
GPIO2
M2
GPIO3
M3
GPIO4
K3
GPIO5
K2
GPIO6
J2
GPIO7
C2
GPIO8
M1
GPIO9
D2
GPIO10
D1
GPIO11
GPIO
DACA_HSYNC DACA_VSYNC
DACA_GREEN
DACB_HSYNC DACB_VSYNC
DACB_GREEN
PCI EXPRESS
JTAG_TRST_N
TEST
I2C DACADACB
XTAL_OUTBUFF
CLK
R3 7 3 0_ 0402_5%
1 2
Y8
@
4
GND
1
IN
@
GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19
DACA_RED
DACA_BLUE
DACA_VREF DACA_RSET
DACB_RED
DACB_BLUE
DACB_VREF DACB_RSET
JTAG_TCK
JTAG_TDI JTAG_TDO JTAG_TMS
TESTMODE
I2CA_SCL I2CA_SDA
I2CB_SCL I2CB_SDA
I2CC_SCL I2CC_SDA
I2CH_SCL I2CH_SDA
I2CS_SCL I2CS_SDA
XTAL_SSIN
XTAL_OUT
XTAL_IN
OUT
GND
J3 J1 K1 F3 G3 G2 F1 F2
AD2 AD1
AE2 AD3 AE3
AF1 AE1
U6 U4
T5 R4 T4
R6 V6
AF3 AG4 AE4 AF4 AG3
AD25
R1 T3
R2 R3
A2 B1
A3 A4
T1 T2
D11 E9 E10 D10
3 2
3
IN V _ P WM ENAVDD EN A BL T GP U _ VI D0 GP U _ VI D1 GP U _ VI D2 TH E RM # TH E R M#_ VG A THM_ALERT
NV _ G PIO 11 AC_DET_R
NV _ G PIO 14
DA C _ RE D DA C _ B LU DA C _ GR N
DA CA_VR EF DA C A_ R S EF
JT A G_ TC K JT A G_ TD I JT A G_ TD O JT A G_ TMS JT A G_ TR ST
I2 C B _SCL I2 C B _SDA
EDID_C LK EDID_D ATA
HD CP_SCL HD CP _SDA
I2 C S _SCL I2 C S _SDA
27 M_SSC
X TAL OUT X TAL IN
C3 13 0. 1U _0 40 2_ 16 V4Z R3 52 1 24 _0 40 2_ 1%
R3 6 8 10 K_0 40 2_ 5%
1 2
R3 6 9 10 K_0 40 2_ 5%@
1 2
R3 7 0 10 K_0 40 2_ 5%@
1 2
200 8/1 2/0 5 Nvidia
X TAL IN
X TAL IN
1
C8 25
@
20 P_0 40 2_ 50V8
2
1 2 1 2
1 2
1 2
1 2
T60 T61 T62 T63 T64
1 2 1 2
R3 460_ 04 02 _5% R3 470_ 04 02 _5% @
R3 480_ 04 02 _5% @
R1 08 50_0402_5% R1 08 60_0402_5%
SML1_C LK SML1_D ATA
TH E R M#_ VG A
HP D - C 22 IN V _ PW M 19 E N AV D D 19 EN A BLT 19 GP U _ VID 0 48 GP U _ VID 1 48 GP U _ VID 2 48
TH E RM _A LERT
AC _ PRE SE NT 14,35
DP E _HP D 34
DP D _ DP _ H PD 19 C R T_ H S YN C 18
CR T _VS YNC 18 DA C _ RE D 18
DA C _ BL U 18 DA C _ GR N 18
200 9/0 1/2 0 DB- 1 C RT iss ue for Compal
CR T _DD C _C LK 18 CR T _DD C _ DAT A 18
HD C P_S CL 21 HD C P_S D A 21
SM L1 _C LK 13 SM L1 _D ATA 13
27 M_SS C 11
+3 VS +3 VS
12
R1 15 7 10 K_0 40 2_ 5%
2N 7 002DWH _SOT3 63 -6
Docking
e-DP
200 8/1 2/0 5 Nvi dia fo r t hermal debug
5
Q7 8B
CRT
HDCP EXT/THERMAL
12
R1 15 8 10 K_0 40 2_ 5%
34
61
2
4
GP U_VID0
GP U _ VI D2 IN V _ P WM
Close to GPU
DA C _ RE D DA C _ GR N DA C _ B LU
TH E RM # TH M _A LERT
I2 C S _SCL I2 C S _SDA
ED I D_ CL K ED I D_ DAT A
HD C P_S C L HD C P_S D A
I2 C B _SCL I2 C B _SDA
Q7 8A 2N 7 002DWH _SOT3 63 -6
200 9/0 2/1 8 HP DB-2
200 9/0 9/1 6 Com pal SI-2R
R1 06 7 10K_0402_5%
1 2
R1 06 8 10K_0402_5%
1 2
R1 08 7 10K_0402_5%
1 2
200 8/1 2/1 9 Nvidia
R3 49 1 50 _0 40 2_ 1%@
1 2
R3 50 1 50 _0 40 2_ 1%@
1 2
R3 51 1 50 _0 40 2_ 1%@
1 2
R1 05 4 2.2 K_0402_5%@
1 2
R1 05 5 2.2 K_0402_5%
1 2
200 9/0 2/1 8 HP DB-2
R3 55 1 0K_0402_5%
1 2
R3 56 1 0K_0402_5%
1 2
R7 88 2 .2 K_0402_5%
1 2
R7 89 2 .2 K_0402_5%
1 2
R3 61 2 .2 K_0402_5%
1 2
R3 64 2 .2 K_0402_5%
1 2
R1 06 9 2.2 K_0402_5%
1 2
R1 07 0 2.2 K_0402_5%
1 2
H_ T HER MTR IP# 4, 15
+3 VS
NV _ G PIO 11 NV _ G PIO 14GP U _ VI D1
JT A G_ TR ST
+3 VS
200 8/1 2/1 2 Nvidia
R1 05 2 10K_0402_5%
1 2
R1 05 3 10K_0402_5%
1 2
R1 10 2 10K_0402_5%
1 2
R1 15 0 10K_0402_5%@
1 2
200 9/0 2/1 2 Nvi dia DB-2
GPIO I/O ACTIVE USAGE
GPIO0
IN
N/A
GPIO1
IN
N/A
GPIO2
OUT
H
GPIO3
OUT
H
GPIO4
OUT
H
GPIO5
OUT
N/A
GPIO6
OUT
N/A
GPIO7
OUT
N/A
GPIO8
IN
L
GPIO9
OUT
L
GPIO10
OUT
N/A
GPIO11
OUT
L
GPIO12
IN
N/A
GPIO13
OUT
L
GPIO14
OUT
H
GPIO15
GPIO16
GPIO17
OUT
N/A
N/A
N/A
GPIO18 N/A
5
HPD-C (used for IFPC)
2nd DVI Hot-plug
Panel Back-Light PWM
Panel Pow er Enable
Panel Back-Light Enable
NVVDD VID0
NVVDD VID1
NVVDD VID2
OVERT
Thermal Alert
MEM_VREF
SLI SYNCO
AC Detect
MEM_VID
PS Control
HPD-E (used for IFPE)IN
FAN PWM Control
GPIO19 N/A HPD-D (used for IFPD)IN
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
PEG Interface
LA-4901P
5
20 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
2
3
4
5
LVDS Interface
U 8 C
AC4
IFPA_TXC
AD4
200 9/0 1/2 0 Nvi dia DB-2
A A
DP A _AUX22 DP A _AUX#22 DP A_ TXP 022 DP A_ TXN 022 DP A_ TXP 122
Quick SW
eDP
B B
DOCKING
DP A_ TXN 122 DP A_ TXP 222 DP A_ TXN 222 DP A_ TXP 322 DP A_ TXN 322
DP D _ AUX19 DP D _ AUX #19 DP D_ TXP019 DP D _TXN019
200 9/0 1/2 0 Nvi dia DB-2
DP E _AUX34 DP E _AUX#34 DP E_ TXP 034 DP E_ TXN 034 DP E_ TXP 134 DP E_ TXN 134 DP E_ TXP 234 DP E_ TXN 234 DP E_ TXP 334 DP E_ TXN 334
DP A _AUX DP A _AUX#
DP D _ AU X DP D _ AU X#
DP E _AUX DP E _AUX#
IFPA_TXC_N
V5
IFPA_TXD0
V4
IFPA_TXD0_N
AA5
IFPA_TXD1
AA4
IFPA_TXD1_N
W4
IFPA_TXD2
Y4
IFPA_TXD2_N
AB4
IFPA_TXD3
AB5
IFPA_TXD3_N
AB3
IFPB_TXC
AB2
IFPB_TXC_N
W1
IFPB_TXD4
V1
IFPB_TXD4_N
W3
IFPB_TXD5
W2
IFPB_TXD5_N
AA2
IFPB_TXD6
AA3
IFPB_TXD6_N
AB1
IFPB_TXD7
AA1
IFPB_TXD7_N
G4
IFPC_AUX_I2CW_SCL
G5
IFPC_AUX_I2CW_SDA_N
P4
IFPC_L0
N4
IFPC_L0_N
M5
IFPC_L1
M4
IFPC_L1_N
L4
IFPC_L2
K4
IFPC_L2_N
H4
IFPC_L3
J4
IFPC_L3_N
D3
IFPD_AUX_I2CX_SCL
D4
IFPD_AUX_I2CX_SDA_N
F5
IFPD_L0
F4
IFPD_L0_N
E4
IFPD_L1
D5
IFPD_L1_N
C3
IFPD_L2
C4
IFPD_L2_N
B3
IFPD_L3
B4
IFPD_L3_N
F7
IFPE_AUX_I2CY_SCL
G6
IFPE_AUX_I2CY_SDA_N
D6
IFPE_L0
C6
IFPE_L0_N
A6
IFPE_L1
A7
IFPE_L1_N
B6
IFPE_L2
B7
IFPE_L2_N
E6
IFPE_L3
E7
IFPE_L3_N
N10M- GL M-S-A 3_ BGA 53 3
Pa r t 3 o f 5
C15
NC
D15
NC
J5
NC
NCRFU
T6
RFU_1
W6
RFU_2
Y6
RFU_3
AA6
RFU_4
N3
RFU_5
ST R AP 0
C7
STRAP0 STRAP1 STRAP2
BUFRST_N
LVDS / TMDS
THERMDN THERMDP
GENERAL STRAPSERIAL
SPDIF
ROM_CS_N ROM_SCLK
ROM_SI
ROM_SO
IFPAB_RSET
IFPC_RSET IFPD_RSET
IFPE_RSET
CEC
B9 A9
N5
D8 D9
N2 F9
B10 C9 A10 C10
AB6 R5 M6 F8
ST R AP 1 ST R AP 2
VG A_THER MDC VG A_THER MDA
RO M _ CS # RO M _ SC LK RO M _ SI RO M _ SO
IFPAB_ RSET IFPC_RSE T IF P D_ R S ET IF P E_ RSE T
200 9/0 2/2 6 Nvi dia DB-2
R3 85 10K_0 40 2_ 5%
1 2
R3 86 1K_ 04 02 _1 %@
1 2
R3 87 1K_ 04 02 _1 %
1 2
R7 91 1K_ 04 02 _1 %
1 2
R9 75 1K_ 04 02 _1 %
1 2
VG A _ TH E RMD C 4 VG A _ TH ER MDA 4
+3 VS
R9 76 1 00 K_0402_5%
DP A _AUX DP A _AUX# DP D _ AU X DP D _ AU X#
C C
D D
1
DP E _AUX DP E _AUX#
1 2
R9 77 1 00 K_0402_5%
1 2
R1 05 6 100 K_0402_5%
1 2
R1 05 7 100 K_0402_5%
1 2
R1 10 3 100 K_0402_5%
1 2
R1 10 4 100 K_0402_5%
1 2
V-BIOS ROM
RO M _ SI RO M _ SO RO M _ SC LK RO M _ CS #
U3 4
5 2 6 1
SST25 VF5 12 -2 0- 4C -S AE_ SO8
2
SI SO SCK CE#
VDD
HOLD#
WP# VSS
GLM:SA000030V20 : S IC N10M-GLM-S-QS(GT218-920) BGA 533P
Hynix : SD034150280 S RES 1/16W 15K +-1% 0402 Samsung: SD034200280 S RES 1/16W 20K +-1% 0402
HDCP ROM Straps
+3 VS
@
8 7 3 4
1
C8 82
0.1U_ 04 02 _1 0V 7K
2
@
U1 1
1
A0
VCC
2
A1
3 4
3
WP
SCL
A2
SDA
GND
AT 2 4C1 6 BN- SH BY- B
Security Classification
Issued Date
+3 VS
1
C3 58
@
0. 1U _0 40 2_ 16 V4Z
8 7 6 5
2
HD CP_SCL HD CP _SDA
HD C P_S C L
R4 06 10 K_0 40 2_ 5%
HD C P_S CL 20 HD C P_S D A 20
12
@
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
@
MULTI LEVEL STRAPS
@
@
@
VR A M@
N S @
4
ST R AP 0 ST R AP 1 ST R AP 2 RO M _ SI RO M _ SO RO M _ SC LK
R3 89
1 2
5.1K_ 04 02 _1% R3 91
1 2
34 .8K_0 40 2_ 1%
R3 93
1 2
5.1K_ 04 02 _1% R3 95
1 2
20 K_0 40 2_ 1%
R3 98
1 2
10 K_0 40 2_ 1%
R4 02
1 2
15 K_0 40 2_ 1%
FB HW S trap for DD R3: (RAM_CFG @ROM_SI)
- Hynix 64 Mx16: 0000 (R395 p ull-down 15K)
- Sams ung 64Mx16: 0001 (R395 p ull-down 20K)
+3 VS
St uff R394 -- > N10M-GLM, N10M-NS
R3 90
1 2
45 .3K_0 40 2_ 1%
R3 92
1 2
34 .8K_0 40 2_ 1%
R3 94
1 2
24 .9K_0 40 2_ 1%
R3 96
@
1 2
5.1K_ 04 02 _1 % R3 99
@
1 2
10 K_0 40 2_ 1%
R4 03
GL M@
1 2
15 K_0 40 2_ 1%
Tit le
N10M(2)_ LVDS&DP&HDCP
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Stuff R 402 --> N10M-NS Stuff R 403 --> N10M-GLM
R402/R40 3:
- 15K: VB IOS com bine d in SBIOS
- 35K: u se VBIOS rom chip
Compal Electronics, Inc.
LA -490 1 P
5
21 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
A A
MD A [63.. 0]24,2 5
MD A [63.. 0]24,2 5 CM D A[ 30 .. 0] 2 4,25
B B
C C
+V D D_MEM
R4 0 7
@
1K_ 04 02 _1 %
R4 1 0
D D
@
1K_ 04 02 _1 %
MD A [6 3. .0 ]
U8 B
MD A 0
D22
MD A 1
E24
MD A 2
E22
MD A 3
D24
MD A 4
D26
MD A 5
D27
MD A 6
C27
MD A 7
B27
MD A 8
A21
MD A 9
B21
MD A 10
C21
MD A 11
C19
MD A 12
C18
MD A 13
D18
MD A 14
B18
MD A 15
C16
MD A 16
E21
MD A 17
F21
MD A 18
D20
MD A 19
F20
MD A 20
D17
MD A 21
F18
MD A 22
D16
MD A 23
E16
MD A 24
A22
MD A 25
C24
MD A 26
D21
MD A 27
B22
MD A 28
C22
MD A 29
A25
MD A 30
B25
MD A 31
A26
MD A 32
U24
MD A 33
V24
MD A 34
V23
MD A 35
R24
MD A 36
T23
MD A 37
R23
MD A 38
P24
MD A 39
P22
MD A 40
AC24
MD A 41
AB23
MD A 42
AB24
MD A 43
W24
MD A 44
AA22
MD A 45
W23
MD A 46
W22
MD A 47
V22
MD A 48
AA25
MD A 49
W27
MD A 50
W26
MD A 51
W25
MD A 52
AB25
MD A 53
AB26
MD A 54
AD26
MD A 55
AD27
MD A 56
V25
MD A 57
R25
MD A 58
V26
MD A 59
V27
MD A 60
R26
MD A 61
T25
MD A 62
N25
MD A 63
N26
12
Rt
FB _ VR E F
12
1
C3 61
Rb
0. 1U _0 40 2_ 16 V4Z@
2
Pa r t 2 o f 5
FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31
MEMORY INTERFACE
FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63
N10M- GL M-S-A 3_ BGA 53 3
FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7
FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7
CM D A2 8 CM D A3 0 CM D A7 CM D A1 8
F26
FBA_CMD0
J24
FBA_CMD1
F25
FBA_CMD2
M23
FBA_CMD3
N27
FBA_CMD4
M27
FBA_CMD5
K26
FBA_CMD6
J25
FBA_CMD7
J27
FBA_CMD8
G23
FBA_CMD9
G26
FBA_CMD10
J23
FBA_CMD11
M25
FBA_CMD12
K27
FBA_CMD13
G25
FBA_CMD14
L24
FBA_CMD15
K23
FBA_CMD16
K24
FBA_CMD17
G22
FBA_CMD18
K25
FBA_CMD19
H22
FBA_CMD20
M26
FBA_CMD21
H24
FBA_CMD22
F27
FBA_CMD23
J26
FBA_CMD24
G24
FBA_CMD25
G27
FBA_CMD26
M24
FBA_CMD27
K22
FBA_CMD28
J22
FBA_CMD29
L22
FBA_CMD30
C26
FBA_DQM0
B19
FBA_DQM1
D19
FBA_DQM2
D23
FBA_DQM3
T24
FBA_DQM4
AA23
FBA_DQM5
AB27
FBA_DQM6
T26
FBA_DQM7
D25 A18 E18 B24 R22 Y24 AA27 R27
C25 A19 E19 A24 T22 AA24 AA26 T27
A16
FB_VREF
F24
FBA_CLK0
FBA_CLK0_N
FBA_CLK1_N
F23 N24
FBA_CLK1
N23 M22
FBA_DEBUG
200 9/0 2/1 3 Nvi dia DB-2
R1 15 4 10K_0402_5%
1 2
R1 15 5 10K_0402_5%
1 2
R1 07 7 10K_0402_5%
1 2
R4 09 1 0K_0402_5%
1 2
200 9/0 2/0 6 Nvi dia DB-2
CM D A0 CM D A1 CM D A2 CM D A3 CM D A4 CM D A5 CM D A6 CM D A7 CM D A8 CM D A9 CM D A1 0 CM D A1 1 CM D A1 2 CM D A1 3 CM D A1 4 CM D A1 5 CM D A1 6 CM D A1 7 CM D A1 8 CM D A1 9 CM D A2 0 CM D A2 1 CM D A2 2 CM D A2 3 CM D A2 4 CM D A2 5 CM D A2 6 CM D A2 7 CM D A2 8 CM D A2 9 CM D A3 0
DQ M A0 DQ M A1 DQ M A2 DQ M A3 DQ M A4 DQ M A5 DQ M A6 DQ M A7
DQ S A#0 DQ S A#1 DQ S A#2 DQ S A#3 DQ S A#4 DQ S A#5 DQ S A#6 DQ S A#7
DQ S A0 DQ S A1 DQ S A2 DQ S A3 DQ S A4 DQ S A5 DQ S A6 DQ S A7
FB _ VR E F
R1 07 2 10K_0 40 2_ 5%
W=15mils
1 2
2
DQ M A[3.. 0] 24
DQ M A[7.. 4] 25
DQ S A# [3 ..0 ] 24
DQ S A# [7 ..4 ] 25
DQ S A[3. .0 ] 24
DQ S A[7. .4 ] 25
CL KA0 24 CL KA0# 24
CL KA1 25 CL KA1# 25
+V D D_MEM
3
C8 7 1
0.01U_0 40 2_ 16 V7 K
C8 7 3
0. 1U _0 40 2_ 16 V4Z
0.01U_0 40 2_ 16 V7 K
1
2
200 9/0 1/2 0 DB- 2 a dd DP Cap.
C8 7 4
1
2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
GPU
C8 7 2
1
1
2
2
DP A_ TXP 02 1 DP A _TX N021
DP A_ TXP 12 1 DP A _TX N121
DP A_ TXP 22 1 DP A _TX N221
DP A_ TXP 32 1 DP A _TX N321
H P D- C20
+3 VS
DP A _AUX21 DP A _AUX#21
HP D - G PU
R1 20 5 100 K_0402_5%@
HP D - C
1 2
R1 20 6 100 K_0402_5%
1 2
200 9/0 6/1 0 SI- 2 T i request
4
+5 VS
C8 7 6
1U _0 40 2_ 6. 3V6K
C8 7 5
1U _0 40 2_ 6. 3V6K
0. 1U _0 40 2_ 16 V4Z
1
1
2
2
C9 240. 1U _0 40 2_ 10 V7K
DP A _TX P0C DP A _TXN0C
C9 250. 1U _0 40 2_ 10 V7K
DP A _TX P1C
C9 260. 1U _0 40 2_ 10 V7K
DP A _TXN1C
C9 270. 1U _0 40 2_ 10 V7K
DP A _TX P2C
C9 280. 1U _0 40 2_ 10 V7K C9 290. 1U _0 40 2_ 10 V7K
DP A _TXN2C DP A _TX P3C
C9 300. 1U _0 40 2_ 10 V7K C9 310. 1U _0 40 2_ 10 V7K
DP A _TXN3C
200 8/1 2/1 2 Nvidia
HP D - G PU
T13 9
HP D - C
R1 01 010 0K_ 04 02 _5 %
1 2
DP A _LP
200 9/0 2/0 6 Nvi dia (d el ter ma tion rsistor)
U6 1
2
VDD
8
VDD
14
VDD
17
VDD
23
VDD
34
VDD
48
VDD
54
VDD
3
ML_IN 0(p)
4
ML_IN 0(n)
6
ML_IN 1(p)
7
ML_IN 1(n)
9
ML_IN 2(p)
10
ML_IN 2(n)
12
ML_IN 3(p)
13
ML_IN 3(n)
39
CAD
37
HPD
30
LP#
29
Priority
36
AUX (p)
35
AUX (n)
5
GND
11
GND
20
GND
27
GND
31
GND
42
GND
44
GND
51
GND
57
Thermol pad(GND)
SN 7 5 DP 12 8A RTQ R_ QFN 56 _8 X8
DP A _LP
ML_A 0(p)
ML_A 0(n)
65mA
R1 10 9 10K_0402_5%
1 2
R1 11 0 10K_0402_5%@
1 2
ML_A 1(p)
ML_A 1(n)
ML_A 2(p)
ML_A 2(n)
ML_A 3(p)
ML_A 3(n)
ML_B 0(p)
ML_B 0(n)
ML_B 1(p)
ML_B 1(n)
ML_B 2(p)
ML_B 2(n)
ML_B 3(p)
ML_B 3(n)
AUX_A (p) AUX_A (n)
AUX_B (p) AUX_B (n)
CAD_A HPD_A
CAD_B HPD_B
DP(vadj)
VDD*1
56 55
53 52
50 49
47 46
25 24
22 21
19 18
16 15
45 43
28 26
41 40
33 32
R1 01 1 6.49K_0 40 2_ 1%
1
1 2
38
+3 VS
5
MB _D PA_ TXP 0 18 MB _D PA_ TXN 0 18
MB _D PA_ TXP 1 18 MB _D PA_ TXN 1 18
MB _D PA_ TXP 2 18 MB _D PA_ TXN 2 18
MB _D PA_ TXP 3 18 MB _D PA_ TXN 3 18
DP B_TXP0 34 DP B_ TXN 0 34
DP B_TXP1 34 DP B_ TXN 1 34
DP B_TXP2 34 DP B_ TXN 2 34
DP B_TXP3 34 DP B_ TXN 3 34
MB _ DPA _AUX 18 MB _ DPA _AUX# 18
DP B _AUX 34 DP B _AUX# 34
CA _ D ET 18 MB _ DP _ HPD 18
CA D _ B 34 DP B _HP D 34
+3 VS
M/B DP
Docking
Close to U8
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
N10M(3)_VGA RAM Interface
LA -490 1 P
5
22 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
VGA Pow er sequence: +.3VS->+NVVDD->+VDD_MEM
4.7U_ 06 03 _6 .3 V6 K
C4 05
1
2
A A
200 9/0 2/2 7 Nvi dia DB -2 NV care
0. 1U _0 40 2_ 16 V4Z
0.047U_ 04 02 _1 6V 7K
C4 08
C3 81
1
1
2
2
0.047U_ 04 02 _1 6V 7K
C3 62
1
2
0.01U_0 40 2_ 16 V7K
0.047U_ 04 02 _1 6V 7K C3 64
C3 63
1
1
2
2
0.022U_ 04 02 _1 6V 7K
C3 84
1
2
+3 VS
R7 9 2 0_ 0603_5%
B B
1 2
4.7U_ 06 03 _6 .3 V6 K
C4 21
1
2
200 9/0 2/2 7 Nvi dia DB -2 NV care
C C
200 9/0 3/3 0 Nvi dia DB-3
+3 VS
L1 9
1 2
PB Y1 60 80 8T-301Y-N _0 60 3
4.7U_ 06 03 _6 .3 V6 K
C4 42
1
2
+3 VS
D D
L22
1 2
BL M18PG 18 1S N1D_0 60 3
220mA
4.7U_ 06 03 _6 .3 V6 K
C4 43
1
2
120mA
1U _0 40 2_ 6. 3V4Z
4.7U_ 06 03 _6 .3 V6 K C4 54
C8 84
1
1
2
2
1
C4 22
1
2
IF PC_ PLLVD D
1U_0402_6.3 V6 K
C4 44
1
2
47 00P_0 40 2_ 25 V7K
C4 55
1
2
120mA
1U _0 40 2_ 6. 3V4Z
0.1U_ 04 02 _1 0V 6K C9 59
C4 23
1
2
200 9/0 3/3 0 Nvi dia DB-3
0.1U_ 04 02 _1 0V 6K
C4 45
1
2
DA C A_ V D D
0.1U_ 04 02 _1 0V 6K
C4 56
1
2
0.1U_ 04 02 _1 0V 6K
0.1U_ 04 02 _1 0V 6K
C9 60
1
1
2
2
+3 VS
C8 5 3
1
2
+3 VS
C8 93
1
2
15.69A
0.01U_0 40 2_ 16 V7K
0.01U_0 40 2_ 16 V7K
C3 65
1
2
C3 85
1
2
1 2 1 2
1 2
1 2
PB Y1 60 80 8T-301Y-N _0 60 3
1U_0603_10V6K
1 2
PB Y1 60 80 8T-301Y-N _0 60 3
1U_0603_10V6K
C3 67
C3 66
1
1
2
2
0.022U_ 04 02 _1 6V 7K
0.022U_ 04 02 _1 6V 7K C3 87
C3 86
1
1
2
2
10 U_0805_6.3V 6M
C4 06
C4 04
1
1
2
2
R1 17 510 K_ 04 02 _5 % R1 17 610 K_ 04 02 _5 %
R1 17 710 K_ 04 02 _5 %
L37
L41
0.01U_0 40 2_ 16 V7K
0.022U_ 04 02 _1 6V 7K
1U _0 40 2_ 6. 3V4Z
C8 5 4
1
2
C8 94
1
2
0.01U_0 40 2_ 16 V7K C3 69
C3 68
1
2
0.022U_ 04 02 _1 6V 7K
C3 88
C3 89
1
2
1U _0 40 2_ 6. 3V4Z
C4 07
1
2
VD D 3 3
PE X _S VDD_3 V3
IFP A_IOVDD IF P B_ I O VDD IFP C _IOVD D IF P DE _ I O VDD
IFP AB_PLLVDD IF PC_ PLLVD D IF P D_ P L LVDD IF P E_ P L LVD D
220mA
4.7U_ 06 03 _6 .3 V6 K
1U_0402_6.3 V6 K
C8 5 5
1
2
220mA
4.7U_ 06 03 _6 .3 V6 K
1U_0402_6.3 V6 K
C8 95
1
2
2
+N V VD D
0.01U_0 40 2_ 16 V7K
1
2
0.022U_ 04 02 _1 6V 7K
1
2
C8 5 6
C8 96
2
J10 J12 J13
L9
M9 M11 M17
N9 N11 N12 N13 N14 N15 N16 N17 N19 P11 P12 P13 P14 P15 P16 P17
R9 R11 R12 R13 R14 R15 R16 R17
T9 T11 T17
U9 U19
W9 W10 W12 W13 W18 W19
A12 B12 C12 D12 E12 F12
AG9
V3 V2
H6
AD5
P6 N6
D7
IF PD_ PLLVD D
0.1U_ 04 02 _1 0V 6K
1
2
IFP E_PLLVDD
0.1U_ 04 02 _1 0V 6K
1
2
J9
J6
U 8 D
Pa r t 4 o f 5
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDD33 VDD33 VDD33 VDD33 VDD33 VDD33
POWER
2A
45mA 45mA
PEX_SVDD_3V3
IFPA_IOVDD IFPB_IOVDD IFPC_IOVDD IFPDE_IOVDD
IFPAB_PLLVDD IFPC_PLLVDD
120mA
FB_CAL_PD_VDDQ IFPD_PLLVDD IFPE_PLLVDD
N10M- GL M-S-A 3_ BGA 53 3
+1 .0 5VS
PB Y1 60 80 8T-221Y-N _2 P
C4 46
1
2
Lay out No te :Please col se to Ball.
2.63A
PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ
PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD
PEX_PLLVDD
VID_PLLVDD
SP_PLLVDD
60mA
FB_PLLAVDD FB_PLLAVDD FB_DLLAVDD
VDD_SENSE VDD_SENSE
1 2
4.7U_ 06 03 _6 .3 V6 K
A13
FBVDDQ
B13
FBVDDQ
C13
FBVDDQ
D13
FBVDDQ
D14
FBVDDQ
E13
FBVDDQ
F13
FBVDDQ
F14
FBVDDQ
F15
FBVDDQ
F16
FBVDDQ
F17
FBVDDQ
F19
FBVDDQ
F22
FBVDDQ
H23
FBVDDQ
H26
FBVDDQ
J15
FBVDDQ
J16
FBVDDQ
J18
FBVDDQ
J19
FBVDDQ
L19
FBVDDQ
L23
FBVDDQ
L26
FBVDDQ
M19
FBVDDQ
N22
FBVDDQ
U22
FBVDDQ
Y22
FBVDDQ
AG6 AF6 AE6 AD6 AC13 AC7 AB17 AB16 AB13 AB9 AB8 AB7
AG7 AF7 AE7 AD8 AD7 AC9
AF9 K6 L6 K5
PLLVDD
R19 AC19 T19
AG2
DACA_VDD
W5
DACB_VDD
B15 W15 E15
200 9/0 3/3 0 Nvi dia DB-3
L20
C4 47
1
2
200 9/0 2/2 7 Nvi dia DB -2 NV care
3
+V D D_MEM
0.01U_0 40 2_ 16 V7 K
0.01U_0 40 2_ 16 V7 K
0.01U_0 40 2_ 16 V7 K C3 72
C3 71
C3 70
1
2
C4 0 9
1
2
Lay out No te :Please col se to Ball.
PE X _ PL LDVDD
SP _ P LL VDD
200 8/1 2/2 0 Nvi dia re que st to sp lit e t he power plan for SSC
FB _ PL L A VDD
DA C A_ V D D DA C B_ V D D
300mA
0.1U_ 04 02 _1 0V 6K
1U_0603_10V6K
C4 48
1
2
1
1
2
2
200 9/0 2/2 7 Nvi dia DB -2 NV care
0.1U_ 04 02 _1 0V 6K
0.1U_ 04 02 _1 0V 6K
1U_0402_6.3 V6 K
C4 1 0
C4 1 1
1
1
2
2
C4 15
1
2
GP U _ P LL VDD
R4 15 1 0K_0402_5%
1 2
R4 18 4 0. 2_ 04 02 _1%
1 2
200 9/0 2/2 7 Nvi dia DB -2 NV care
R3 71 0 _0 40 2_ 5%
1 2
IFP C _IOVD D
0.1U_ 04 02 _1 0V 6K
C4 49
1
Lay out No te :Please col se to BGA.
2
3
0.047U_ 04 02 _1 6V 7K
0.047U_ 04 02 _1 6V 7K C8 27
C8 26
C3 73
1
2
C4 1 2
1
2
0.1U_ 04 02 _1 0V 6K
Security Classification
1
1
2
2
+1 .0 5VS
4.7U_ 06 03 _6 .3 V6 K
1U_0402_6.3 V6 K
C4 1 3
C4 1 4
1
1
2
2
C4 16
0.1U_ 04 02 _1 0V 6K
C4 17
1U_0402_6.3 V6 K
1
1
2
2
+N V VD D _ S ENSE
+1 .0 5VS
200 9/0 2/2 7 Nvi dia DB -2 NV care 200 9/0 2/2 7 Nvi dia DB -2 NV care
Lay out No te :Please col se to Ball.
Issued Date
0.047U_ 04 02 _1 6V 7K
1U _0 40 2_ 6. 3V4Z
C8 28
1
2
22 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C4 0 2
1
2
600 mA
C4 18
1U_0402_6.3 V6 K
C4 19
1
1
2
2
+V D D_MEM
L38
1 2
PB Y 16 0808T-2 21 Y- N_2P
4.7U_ 06 03 _6 .3 V6 K
C8 5 7
1
2
SP _ P LL VDD
4
U 8 E
B2
GND
B5
GND
B8
GND
4.7U_ 06 03 _6 .3 V6 K
C3 80
1
2
+1 .0 5VS
C4 03
22 U_0805_6.3V 6M
C4 20
10 U_0805_6.3V 6M
4.7U_ 06 03 _6 .3 V6 K
1
1
2
2
1 2 1 2
+N V VD D _ SE NSE 48
285mA
1U_0603_10V6K
C8 5 8
C8 5 9
1
2
4.7U_ 06 03 _6 .3 V6 K
C9 58
C9 41
1
2
2008/09/15 2009/12/31
to Power
IFP D E_IO VDD
0.1U_ 04 02 _1 0V 6K
0.1U_ 04 02 _1 0V 6K C8 6 0
1
1
2
1
2
Lay out No te :Please col se to BGA.
2
L47
1 2
10 0 N H_ CL H1 60 8T- R1 0J -S_5%
1U_0402_6.3 V6 K
200 9/0 2/2 3 Nvi dia DB-2
Compal Secret Data
Deciphered Date
B11
GND
B14
GND
B17
GND
B20
GND
B23
GND
B26
GND
E2
GND
E5
GND
E8
GND
E11
GND
E17
GND
E20
GND
E23
GND
E26
GND
H2
GND
H5
GND
J11
GND
J14
GND
J17
GND
K9
GND
K19
GND
L2
GND
L5
GND
L11
GND
L12
GND
L13
GND
L14
GND
L15
GND
L16
GND
L17
GND
M12
GND
M13
GND
M14
GND
M15
GND
M16
GND
P2
GND
P5
GND
P9
GND
P19
GND
P23
GND
P26
GND
T12
GND
T13
W16
E14
N10M- GL M-S-A 3_ BGA 53 3
+1 .0 5VS
GND
GND_SENSE GND_SENSE
R4 1 30_04 02 _5% R4 1 40_04 02 _5%
4
Pa r t 5 o f 5
MULTI_STRAP_REF1_GND MULTI_STRAP_REF0_GND
Lay out No te :Please col se to Ball.
Lay out No te :Please col se to Ball.
PEX_P LLDVDD
Lay out No te :Please col se to Ball.
5
U2
GND
U5
GND
U11
GND
U12
GND
U13
GND
U14
GND
U15
GND
U16
GND
U17
GND
U23
GND
U26
GND
V9
GND
V19
GND
W11
GND
W14
GND
W17
GND
Y2
GND
Y5
GND
Y23
GND
Y26
GND
GND
FB_CAL_PU_GND
FB_CAL_TERM_GND
PE X _S VDD_3 V3
FB _ PL L A VDD
GP U _ P LL VDD
C4 2 4
AC2
GND
AC5
GND
AC6
GND
AC8
GND
AC11
GND
AC14
GND
AC17
GND
AC20
GND
AC23
GND
AC26
GND
AF2
GND
AF5
GND
AF8
GND
AF11
GND
AF14
GND
AF17
GND
AF20
GND
AF23
GND
AF26
GND
T16
GND
T15
GND
T14
GND
F6
GND
Lay out No te :Please col se to Ball.
0.01U_0 40 2_ 25 V7 K C4 2 5
1
2
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
200 9/0 2/1 3 Nvi dia DB-2
R1 05 8 40. 2_ 04 02 _1 %
A15
1 2
R1 05 9 60. 4_ 04 02 _1 %
B16
1 2
R3 83 4 0. 2K_0402_1%
F11
1 2
R3 84 4 0. 2K_0402_1%
F10
1 2
120mA
0.1U_ 04 02 _1 0V 6K C4 5 8
C4 5 7
1
1
2
2
1U _0 40 2_ 6. 3V4Z
Lay out No te :Please col se to BGA.
R6 31 0 _0 40 2_ 5%
C8 5 2
200mA
47 00P_0 40 2_ 25 V7K
1U _0 40 2_ 6. 3V4Z
C4 38
C4 39
1
1
2
2
105mA
4.7U_ 06 03 _6 .3 V6 K
0. 1U _0 40 2_ 16 V4Z
C4 50
C4 51
1
1
2
2
120mA
0. 1U _0 40 2_ 16 V4Z
1U _0 40 2_ 6. 3V4Z
C4 2 6
1
1
2
2
1U _0 40 2_ 6. 3V4Z
4.7U_ 06 03 _6 .3 V6 K C4 41
C4 40
1
1
2
2
1U _0 40 2_ 6. 3V4Z
0. 1U _0 40 2_ 16 V4Z
C4 52
C4 53
1
1
2
2
4.7U_ 06 03 _6 .3 V6 K
1U _0 40 2_ 6. 3V4Z
C4 2 7
C4 2 8
1
1
2
2
Compal Electronics, Inc.
N10M(4)_Power/GND
LA -490 1 P
5
1 2
4.7U_ 06 03 _6 .3 V6 K
1
2
L18
1 2
BL M18PG 18 1S N1D_0 60 3
Lay out No te :Please col se to BGA.
1 2
10 0 NH_C LH 16 08 T-R10 J- S_ 5%
Lay out No te :Please col se to BGA.
L15
1 2
0. 1 U H_ MLF 16 08 DR10KT_10%_1 60 8
Lay out No te :Please col se to BGA.
+3 VS
+1. 05 VS
+1. 05 VS
L2 1
+1. 05 VS
1U _0 40 2_ 6. 3V4Z
C8 2 9
1
2
23 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
2
3
4
5
VRAM DDR3 chips (512MB)
64Mx16 DDR3 800MHz*4==>512MB Low 32 bit FB
A A
B B
C C
D D
DQ S A[ 7..0]22, 25 DQ S A# [7 ..0 ]22,25 DQ M A[7.. 0]22 ,2 5 MD A[ 63 ..0]22 ,25 CM D A[ 30 .. 0]2 2, 25
DQ S A [7 .. 0]
DQ S A#[7 .. 0] DQ M A[ 7. .0 ] MD A [6 3. .0 ] CM D A [3 0..0]
CM D A1 522,25
1K_ 04 02 _1 %
1K_ 04 02 _1 %
+V D D_MEM
R4 2 6
R4 2 8
+V D D_MEM
12
12
C4 72
1
2
10 K_0 40 2_ 5%
12
R4 2 1
ME M_ V R EF0
1
C4 6 1
0.01U_0 40 2_ 16 V7 K
2
1U _0 40 2_ 6. 3V6K
C4 73
1
2
Hynix : H5TQ1G63BFR-12C-->SA000032400 Samsung : K4W1G1646E-HC12-->SA000035700
U1 3
ME M_ V R EF0
CM D A1 9 CM D A2 5 CM D A2 2 CM D A2 4 CM D A0 CM D A2 CM D A2 1 CM D A1 6 CM D A2 3 CM D A2 0 CM D A1 7 CM D A9 CM D A1 4 CM D A2 6
CM D A1 2 CM D A3 CM D A2 7
CL KA0 CL KA0 # CM D A1 8
CM D A3 0 CM D A2 9 CM D A1 CM D A1 0 CM D A1 1
DQ S A1 DQ S A2
DQ M A1 DQ M A2
DQ S A#1 DQ S A#2
CM D A1 5
ZQ 0
24 3_0402_1%
12
R4 2 2
M9
VREFCA
H2
VREFDQ
N4
A0
P8
A1
P4
A2
N3
A3
P9
A4
P3
A5
R9
A6
R3
A7
T9
A8
R4
A9
L8
A10/AP
R8
A11
N8
A12
T4
A13
T8
A14
M8
A15/BA3
M3
BA0
N9
BA1
M4
BA2
J8
CK
K8
CK
K10
CKE/CKE0
K2
ODT/ODT0
L3
CS
J4
RAS
K4
CAS
L4
WE
310mA
F4
DQSL
C8
DQSU
E8
DML
D4
DMU
G4
DQSL
B8
DQSU
T3
RESET
L9
ZQ/ZQ0
J2
NC/ODT1
L2
NC/CS1
J10
NC/CE1
L10
NCZQ1
A1
NC
A11
NC
T1
NC
T11
NC
10 0- BALL SD R AM DDR3
K4 B 1 G1 64 6D -H CF8 _F BGA10 0
VR A M@
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VDD VDD VDD VDD VDD VDD VDD VDD VDD
MD A 8
E4
MD A 9
F8
MD A 10
F3
MD A 11
F9
MD A 12
H4
MD A 13
H9
MD A 14
G3
MD A 15
H8
MD A 16
D8
MD A 21
C4
MD A 19
C9
MD A 20
C3
MD A 18
A8
MD A 22
A3
MD A 17
B9
MD A 23
A4
+V D D_MEM
B3 D10 G8 K3 K9 N2 N10 R2 R10
+V D D_MEM
A2 A9 C2 C10 D3 E10 F2 H3 H10
A10
VSS
B4
VSS
E2
VSS
G9
VSS
J3
VSS
J9
VSS
M2
VSS
M10
VSS
P2
VSS
P10
VSS
T2
VSS
T10
VSS
B2 B10 D2 D9 E3 E9 F10 G2 G10
CL K A022
CL KA0#22
DDR3 BGA MEMORY
1U _0 40 2_ 6. 3V6K
1U _0 40 2_ 6. 3V6K
1U _0 40 2_ 6. 3V6K
C4 74
C4 75
1
1
2
2
0.1U_ 04 02 _1 6V 7K
0.1U_ 04 02 _1 6V 7K C4 77
C4 76
1
1
2
2
0.1U_ 04 02 _1 6V 7K
0.1U_ 04 02 _1 6V 7K C4 80
C4 79
C4 78
1
2
1
1
2
2
U1 4
ME M_ V R EF1
M9 H2
CM D A1 9
N4
CM D A2 5
P8
CM D A2 2
P4
CM D A2 4
N3
CM D A0
P9
CM D A2
P3
CM D A2 1
200 8/1 2/0 8 swa p d ata bu s for layout 200 8/1 2/0 8 swa p d ata bu s for layout
+V D D_MEM
R4 24
1K_ 04 02 _1 %
R4 27
1K_ 04 02 _1 %
12
12
ME M_ V R EF1
1
C4 60
0.01U_0 40 2_ 16 V7 K
2
+V D D_MEM
C4 62
1
2
12 1_0402_1%
1 2
12 1_0402_1%
200 9/0 2/2 7 Nvi dia DB -2 NV care
0.1U_ 04 02 _1 6V 7K
0.1U_ 04 02 _1 6V 7K C4 81
1
2
CL KA0
12
R4 25
C4 590 .0 1U _0 40 2_ 16 V7K
12
R4 29
CL KA0 #
R9
CM D A1 6
R3
CM D A2 3
T9
CM D A2 0
R4
CM D A1 7
L8
CM D A9
R8
CM D A1 4
N8
CM D A2 6
T4 T8
M8
CM D A1 2
M3
CM D A3
N9
CM D A2 7
M4
CL KA0
J8
CL KA0 #
K8
CM D A1 8
K10
CM D A3 0
K2
CM D A2 9
L3
CM D A1
J4
CM D A1 0
K4
CM D A1 1
L4
DQ S A0
F4
DQ S A3
C8
DQ M A0
E8
DQ M A3
D4
DQ S A#0
G4
DQ S A#3
B8
CM D A1 5
T3
ZQ 1
L9
24 3_0402_1%
12
J2
R4 2 3
L2
J10
L10
A1
A11
T1
T11
DDR3 BGA MEMORY
1U_0402_6.3 V6 K
1U_0402_6.3 V6 K
1U_0402_6.3 V6 K
C4 64
C4 63
1
1
2
2
VR A M@
310mA
10 0- BALL SD R AM DDR3
1U_0402_6.3 V6 K
C4 65
1
2
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
0.1U_ 04 02 _1 6V 7K
C4 66
1
2
VREFCA VREFDQ
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3
BA0 BA1 BA2
CK CK CKE/CKE0
ODT/ODT0 CS RAS CAS WE
DQSL DQSU
DML DMU
DQSL DQSU
RESET ZQ/ZQ0
NC/ODT1 NC/CS1 NC/CE1 NCZQ1
NC NC NC NC
K4 B 1 G1 6 46 D- HCF8_ FBG A1 00
VDD VDD VDD VDD VDD VDD VDD VDD VDD
MD A 0
E4
MD A 1
F8
MD A 2
F3
MD A 3
F9
MD A 4
H4
MD A 5
H9
MD A 6
G3
MD A 7
H8
MD A 24
D8
MD A 29
C4
MD A 26
C9
MD A 30
C3
MD A 28
A8
MD A 25
A3
MD A 27
B9
MD A 31
A4
+V D D_MEM
B3 D10 G8 K3 K9 N2 N10 R2 R10
+V D D_MEM
A2 A9 C2 C10 D3 E10 F2 H3 H10
A10
VSS
B4
VSS
E2
VSS
G9
VSS
J3
VSS
J9
VSS
M2
VSS
M10
VSS
P2
VSS
P10
VSS
T2
VSS
T10
VSS
B2 B10 D2 D9 E3 E9 F10 G2 G10
0.1U_ 04 02 _1 6V 7K
C4 67
1
2
0.1U_ 04 02 _1 6V 7K
0.1U_ 04 02 _1 6V 7K
0.1U_ 04 02 _1 6V 7K C4 69
C4 68
1
1
2
2
0.1U_ 04 02 _1 6V 7K
C4 70
C4 71
1
1
2
2
Address
CMD0 CMD1 CMD2 CMD3 CMD4 CMD5 CMD6 CMD7
CMD9 CMD10 CMD11 CMD12 CMD13 CMD14 CMD15 CMD16 CMD17 CMD18 CMD19 CMD20 CMD21 CMD22 CMD23 CMD24 CMD25 CMD26 CMD27 CMD28 CMD29 CMD30
DATA Bus
0..31
32..63 A4 RAS# A5 BA1
A11 CAS# WE# BA0
A12 RST RST A7 A10 CKE A0 A9 A6 A2 A8 A3 A1 A13 BA2
CS# ODT
LOW HIGH
RAS#
BA1 A2 A4 A3 CKE CS#CMD8 A11 CAS# WE# BA0 A5 A12
A7 A10
A0 A9 A6
A8
A1 A13 BA2 ODT
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Da t e: She et o f
Compal Electronics, Inc.
VRAM DDR3
LA-4901P
Tu e s da y, De ce mbe r 15 , 20 09
5
54
24
0.1
1
VRAM DDR3 chips (512MB)
64Mx16 DDR3 800MHz*4==>512MB High 32 bit FB
ME M_ V R EF2
CM D A1 9
A A
CM D A722
CM D A2 822
B B
C C
+V D D_MEM
R4 35
1K_ 04 02 _1 %
R4 38
1K_ 04 02 _1 %
12
12
ME M_ V R EF2
1
C4 83
0.01U_0 40 2_ 16 V7K
2
CM D A2 5 CM D A4 CM D A6 CM D A5 CM D A1 3 CM D A2 1 CM D A1 6 CM D A2 3 CM D A2 0 CM D A1 7 CM D A9 CM D A1 4 CM D A2 6
CM D A1 2 CM D A3 CM D A2 7
CL KA1 CL KA1 # CM D A7
CM D A2 8 CM D A8 CM D A1 CM D A1 0 CM D A1 1
DQ S A4 DQ S A7
DQ M A4 DQ M A7
DQ S A#4 DQ S A#7
CM D A1 5
12
R4 32
ZQ 2
24 3_0402_1%
2
DQ S A[ 7..0]22, 24 DQ S A# [7 ..0 ]22,24
DQ M A[7.. 0]22 ,2 4
U1 5
M9
H2 N4
P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8
M8
M3
N9
M4
J8
K8
K10
K2 L3
J4 K4 L4
F4
C8
E8
D4
G4
B8
T3 L9
J2 L2
J10 L10
A1
A11
T1
T11
VR A M@
VREFCA VREFDQ
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3
BA0 BA1 BA2
CK CK CKE/CKE0
ODT/ODT0 CS RAS CAS WE
DQSL DQSU
DML DMU
DQSL DQSU
RESET ZQ/ZQ0
NC/ODT1 NC/CS1 NC/CE1 NCZQ1
NC NC NC NC
K4 B 1 G1 64 6D -H CF8 _F BGA10 0
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ
310mA 310mA
VDDQ VDDQ VDDQ VDDQ
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
10 0- BALL SD R AM DDR3
MD A 32
E4
MD A 33 MD A 41
F8
MD A 34
F3
MD A 35
F9
MD A 36
H4
MD A 37
H9
MD A 38
G3
MD A 39
H8
200 8/1 2/0 8 swa p d ata bu s for layout
MD A 60 MD A 54
D8
MD A 61
C4
MD A 62
C9
MD A 56
C3
MD A 57
A8
MD A 59
A3
MD A 63
B9
MD A 58
A4
+V D D_MEM
B3 D10 G8 K3 K9 N2 N10 R2 R10
+V D D_MEM
A2 A9 C2 C10 D3 E10 F2 H3 H10
A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10
B2 B10 D2 D9 E3 E9 F10 G2 G10
CL K A122
CL K A1 #22
MD A [63.. 0]22 ,24 CM D A[ 30 .. 0]2 2, 24
3
DQ S A [7 .. 0]
DQ S A#[7 .. 0] DQ M A[ 7. .0 ] MD A [6 3. .0 ] CM D A [3 0..0]
CL KA1
12
R4 34
12 1_0402_1%
1 2
C4 820 .0 1U _0 40 2_ 16 V7K
12
R4 37
12 1_0402_1%
200 9/0 2/2 7 Nvi dia DB -2 NV care
CL KA1 #
ME M_ V R EF3
CM D A1 9 CM D A2 5 CM D A4 CM D A6 CM D A5 CM D A1 3 CM D A2 1 CM D A1 6 CM D A2 3 CM D A2 0 CM D A1 7 CM D A9 CM D A1 4 CM D A2 6
CM D A1 2 CM D A3 CM D A2 7
CL KA1 CL KA1 #
CM D A722
CM D A2822
CM D A7
CM D A2 8 CM D A8 CM D A1 CM D A1 0 CM D A1 1
DQ S A5 DQ S A6
DQ M A5 DQ M A6
DQ S A#5 DQ S A#6
CM D A1 5
R4 33
M9
H2 N4
P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8
M8
M3
N9
M4
J8
K8
K10
K2 L3
J4 K4 L4
F4
C8
E8
D4
G4
B8
T3
ZQ 3
L9
J2
24 3_0402_1%
12
L2
J10
L10
A1
A11
T1
T11
4
U1 6
VR A M@
10 0- BALL SD R AM DDR3
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSSQ VSSQ
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VREFCA VREFDQ
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3
BA0 BA1 BA2
CK CK CKE/CKE0
ODT/ODT0 CS RAS CAS WE
DQSL DQSU
DML DMU
DQSL DQSU
RESET ZQ/ZQ0
NC/ODT1 NC/CS1 NC/CE1 NCZQ1
NC NC NC NC
K4 B 1 G1 64 6D -H CF8 _F BGA10 0
5
MD A 45
E4 F8
MD A 43
F3
MD A 42
F9
MD A 44
H4
MD A 40
H9
MD A 46
G3
MD A 47
H8
D8 C4 C9 C3 A8 A3 B9 A4
B3 D10 G8 K3 K9 N2 N10 R2 R10
A2 A9 C2 C10 D3 E10 F2 H3 H10
A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10
B2 B10 D2 D9 E3 E9 F10 G2 G10
200 8/1 2/0 8 swa p d ata bu s for layout
MD A 48 MD A 53 MD A 50 MD A 52 MD A 51 MD A 55 MD A 49
+V D D_MEM
+V D D_MEM
+V D D_MEM
R4 36
1K_ 04 02 _1 %
R4 39
1K_ 04 02 _1 %
12
12
ME M_ V R EF3
1
C4 84
0.01U_0 40 2_ 16 V7 K
2
+V D D_MEM +V D D_MEM
1U_0402_6.3 V6 K
C4 8 5
1
2
D D
1
DDR3 BGA MEMORY DDR3 BGA MEMORY
1U_0402_6.3 V6 K
C4 8 6
1
2
1U_0402_6.3 V6 K
1U_0402_6.3 V6 K
C4 8 7
1
2
0.1U_ 04 02 _1 6V 7K
C4 8 8
C4 8 9
1
1
2
2
0.1U_ 04 02 _1 6V 7K
0.1U_ 04 02 _1 6V 7K C4 9 1
C4 9 0
1
1
2
2
2
0.1U_ 04 02 _1 6V 7K
0.1U_ 04 02 _1 6V 7K
C4 9 2
1
2
0.1U_ 04 02 _1 6V 7K
C4 9 3
C4 9 4
1
1
2
2
Security Classification
Issued Date
3
1U_0402_6.3 V6 K
1U_0402_6.3 V6 K
C4 9 6
C4 9 5
1
1
2
2
2008/09/15 2009/12/31
1U_0402_6.3 V6 K
1U_0402_6.3 V6 K
C4 9 8
C4 9 7
1
1
2
2
Compal Secret Data
0.1U_ 04 02 _1 6V 7K
C4 9 9
1
2
Deciphered Date
0.1U_ 04 02 _1 6V 7K
C5 0 0
1
2
4
0.1U_ 04 02 _1 6V 7K
0.1U_ 04 02 _1 6V 7K C5 0 2
C5 0 1
1
1
2
2
0.1U_ 04 02 _1 6V 7K
0.1U_ 04 02 _1 6V 7K C5 0 4
C5 0 3
1
1
2
2
Tit le
Size Do c u me nt N umb er R e v
Da t e: She et o f
Compal Electronics, Inc.
VRAM DDR3
Cartier DIS
Tu e s da y, De ce mbe r 15 , 20 09
5
0.1
542 5
1
2
3
4
5
1 2
0. 1U _0 40 2_ 16 V4Z
1
2
VCT
R4 42 0_ 0603_5%
+3 VM_L AN
C5 13
13 14
17 18
20 21
23 24
6 1
2 5
4 15
19 29
47 46 37
43 11 40
22 16 8
7 49
From Power
+1 .0 5VM_L AN
10 U_ 08 05 _1 0V 4Z
C5 14
1
2
+3 . 3 VM_ LA N_OUT +3 . 3 VM _L AN_ OU T_R
+1 .0VM_LAN 4
+1 .0VM_LAN 3 +1 .0VM_LAN 2
+1 .0VM_LAN 1
LA N _ CTR L_ 18
R4 53 3 .0 1K_0402_1%
1 2
R4 54 3 .0 1K_0402_1%
1 2
1 2
R4 5 6 0_0603_5%
1 2
R4 5 7 0_0603_5%
1 2
R4 5 9 0_0603_5%
1 2
R4 6 1 0_0603_5%
1 2
R4 6 2 0_0603_5%
T13 8
LA N _ MDI 0P 27 LA N _ MD I0 N 27
LA N _ MDI 1P 27 LA N _ MD I1 N 27
LA N _ MDI 2P 27 LA N _ MD I2 N 27
LA N _ MDI 3P 27 LA N _ MD I3 N 27
TR M_CT 27
+3 VM_L AN
1
C5 24 1U _0 60 3_ 10 V4 Z
2
+1 .0VM _L AN+3 VM_L AN
200 9/0 1/2 2 HP
+1 .0VM _L AN
10 U_0805_6.3V 6M
0. 1U _0 40 2_ 16 V4Z C5 1 0
+3 VM
C5 0 9
1
2
R9 32 0_ 0603_5%
1 2
PCIE
SMBUS
JTAG LED
328mA
1
2
MDI_PLUS0
MDI_MINUS0
MDI_PLUS1
MDI_MINUS1
MDI
MDI_PLUS2
MDI_MINUS2
MDI_PLUS3
MDI_MINUS3
RSVD_VCC3P3_1 RSVD_VCC3P3_2
VDD3P3_IN
VDD3P3_OUT
92mA
VDD3P3_15 VDD3P3_19 VDD3P3_29
VDD1P0_47 VDD1P0_46 VDD1P0_37
VDD1P0_43 VDD1P0_11 VDD1P0_40
VDD1P0_22 VDD1P0_16
VDD1P0_8
CTRL_1P0
VSS_EPAD
A A
200 9/0 2/1 9 HP DB-2
From Power
200 9/0 5/0 2 HP SI-1
R1 19 9 0_0402_5%
B B
C C
CL K _ PC IE_L AN _REQ1 #13
CL K _ PC I E_ LAN_R EQ #15 PL T_ RST#4, 12 ,1 5, 20 ,2 8,31,33
CL K _ PC IE_L AN15 CL K _ PC IE_L AN #15
PC I E_ PRX _DTX_ P613 PC I E_ PR X_DTX_N613
PC I E_ PTX_C _D RX_ P613 PC I E_ P TX_ C_DRX _N 613
SM L 0C LK13 SM L 0D ATA13
LA N _ DIS#1 5, 27
LE D _ LIN K_LAN #_ R15 ,2 7 LE D _ LINK _L AN#27 LA N _ ACT #27 ,3 4
200 8/1 1/1 7 HP
1 2
200 9/0 1/2 2 HP
R9 30 0_0402_5%@
1 2
R4 50 0_0402_5%
1 2
C5 16 0.1U_0 40 2_ 10 V7 K
1 2
C5 18 0.1U_0 40 2_ 10 V7 K
1 2
R4 51 0_0402_5%
1 2
R4 52 0_0402_5%
1 2
R4 55 0_0402_5%
1 2
R1 13 5 0_0402_5%@
1 2
R4 58 10K_0 40 2_ 5%@
1 2
R4 60 10K_0 40 2_ 5%@
1 2
R4 63 1 K_0402_5% R4 64 3 .0 1K_0402_1%
CL K _ PC I E_LAN_ REQ#_R PL T _RST#_LAN
PC I E_ PR X_DTX_P6 _C PC I E _P RX_ DTX_N 6_ C
LA N _ SM _CLK LA N _ SM _DAT
LA N _ PH Y P C_ R
200 9/0 2/0 6 HP DB-2
LE D _ LINK _L AN# LA N _ ACT #
LA N _ JTA G_ TMS LA N _ JT AG_TC K
XTAL1_C XTAL2
1 2 1 2
U1 8
48
CLK_REQ_N
36
PE_RST_N
44
PE_CLKP
45
PE_CLKN
38
PETp
39
PETn
41
PERp
42
PERn
28
SMB_CLK
31
SMB_DATA
3
LAN_DISABLE_N
26
LED0
27
LED1
25
LED2
32
T65 T66
JTAG_TDI
34
JTAG_TDO
33
JTAG_TMS
35
JTAG_TCK
9
XTAL_OUT
10
XTAL_IN
30
TEST_EN
12
RBIAS
WG 8 2 57 7L M_QFN 48 P
200 9/0 2/0 6 HP DB-2
XTAL1
C9 34 10P_ 04 02 _5 0V 8C
1 2
Y5
25 M H Z_ 18 PF_ X5H025000DI 1H -H
1 2
1
C5 29
D D
1
33 P_0 40 2_ 50 V8J
2
200 9/0 9/1 1 HP PV
1
C5 30 33 P_0 40 2_ 50 V8J
2
XTAL1_C
XTAL2
Security Classification
Issued Date
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Da t e: She et o f
Compal Electronics, Inc.
Intel 82566 Nineveh
LA- 4901P
5
26 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
A A
R1 13 7 0_0402_5%
LE D _ LINK _L AN# _R15,2 6 LE D _ LIN K_ LA N_ DOCK#34
B B
1 2
D
1 3
G
2
200 9/0 1/2 2 HP DB-2
S
LE D _ LINK _L AN#
Q7 3 2N7002H_S OT2 3- 3
2
LA N _ DIS# 15 ,26
3
LA N _A CT#26 ,3 4
LA N _ ACT #
1 2
LE D _ LINK _L AN#26
LE D _ LINK _L AN#
200 9/0 1/2 2 HP DB-2
1 2
4
+3 VM_L AN
R9 26
10 K_0 40 2_ 5%
12
R4 67 3 00 _0 60 3_ 5%
1 2
C5 3568 0P_ 04 02 _5 0V 7K@
+3 VM_L AN
R4 68
10 K_0 40 2_ 5%
12
R4 70 30 0_0603_5%
1 2
C5 3868 0P_ 04 02 _5 0V 7K@
RJ-45 CONN.
+3 V M_LAN _L ED
+3 V M_LAN _L ED
3
MDO3 ­MD O 3+ MDO1 ­MDO2 ­MD O 2+ MD O 1+ MDO0 ­MD O 0+
2
D5 7
@
PJ D LC 05 H_SOT 23 -3
200 9/0 2/1 8 Com pal DB-2 EMI
1
JP 6
13
Yellow LED+
14
Yellow LED-
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
11
Green LED+
12
Green LED-
FOX _JM36 11 3- P1 12 3- 7F
C O N N@
5
16
SHLD1
DETECT PIN1
DETCET PIN2
9
10 15
SHLD1
200 9/0 2/2 4 Com pal DB-2
+3 VM_L AN + 3 V M_L AN_LED
12
R4 7 3
+3 VM_L AN
12
R1 02 5
@
0_ 0402_5%
LA N _ MDI 0N26
LA N _ MDI 0P26
C C
D D
TR M_CT26
200 9/0 4/1 0 HP DB-3
1
1 2
R1 08 3 0_0402_5%@
LA N _ MDI 1N26
LA N _ MDI 1P26
LA N _ MDI 2N26
LA N _ MDI 2P26
LA N _ MDI 3N26
LA N _ MDI 3P26
1 2
C5 3 6 1U_0402_6.3 V6 K
200 9/0 1/2 2 HP
LA N _ MD I0 N
LA N _ MD I0 P TR M_ CT_ R LA N _ MD I1 N
LA N _ MD I1 P TR M_ CT_ R LA N _ MD I2 N MDO2 -
LA N _ MD I2 P TR M_ CT_ R LA N _ MD I3 N
LA N _ MD I3 P TR M_ CT_ R
0. 1U _0 40 2_ 16 V4Z
0. 1U _0 40 2_ 16 V4Z
C9 62
C9 63
1
1
2
2
pla ce 1 c ap aci tor at ea ch pi n (1,4,7,10)
200 9/0 4/2 4 HP SI-1
1
2
0. 1U _0 40 2_ 16 V4Z C9 64
2
T1
12
TD4-
11
TD4+
10
TCT4
9
TD3-
8
TD3+
7
TCT3
6
TD2-
5
TD21+
4
TCT2
3
TD1-
2
TD1+
1
TCT1
35 0u H_ NS892402P
TR M_ CT_ R
0. 1U _0 40 2_ 16 V4Z C9 65
1
2
MDO0 -
13
MX4-
MD O 0+
1:1
1:1
1:1
1:1
MX4+ MCT4
MX3-
MX3+ MCT3
MX2-
MX2+ MCT2
MX1-
MX1+ MCT1
14
MC T0
15
MDO1 -
16
MD O 1+
17
MC T1
18 19
MD O 2+
20
MC T2
21
MDO3 -
22
MD O 3+
23
MC T3
24
MD O0 - 34
MD O0 + 34
MD O1 - 34
MD O1 + 34
MD O2 - 34
MD O2 + 34
MD O3 - 34
MD O3 + 34
Security Classification
Issued Date
3
Change design. 10/12
R4 69
C5 37 0.01U_ 04 02 _5 0V 7K
1 2
C5 40 0.01U_ 04 02 _5 0V 7K
1 2
C5 42 0.01U_ 04 02 _5 0V 7K
1 2
C5 44 0.01U_ 04 02 _5 0V 7K
1 2
2008/09/15 2009/12/31
75 _0402_1%
1 2
R4 71
75 _0402_1%
1 2
R4 72
75 _0402_1%
1 2
R4 74
75 _0402_1%
1 2
Compal Secret Data
Deciphered Date
4
C5 45 10 00P_1 80 8_ 3K V7K
1 2
10 0K_ 04 02 _5 %
DO C K _I D34
Tit le
Size Do c u me nt N umb er R e v
Da t e: She et o f
Q17
SI2 30 1C DS-T1 -G E3_SO T23- 3
S
G
2
13
D
2
G
S
D
13
Q23 2N7002H_S OT2 3- 3
20 mil20 mil
Compal Electronics, Inc.
Magnetic & RJ45
LA- 4901P
5
27 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
2
3
4
5
Reserve for port80 card use for FCS in factory side. 10/17
WLAN (Halt mini Card)
0.01U_0 40 2_ 16 V7 K
C5 49
1
2
G
2
+1 .5 VS
4. 7U _0 80 5_ 10 V4Z
0. 1U _0 40 2_ 16 V4Z C5 51
C5 50
1
1
2
2
S
D
1 3
5W
WL A N _T R AN SMIT_ OF F# 15
+3 V _W LAN
PC I E_ W AK E#14 ,3 1
CL K R EQ _ WLAN#13 CL K _ PC I E_MC ARD #13
CL K _ PC I E_MC ARD13
CL K _ PC I _D EBU G15
PC I E_ PRX _DTX_ N413 PC IE _PRX_ DTX _P 413
PC I E_ PTX_C _D RX_ N413 PC I E_ PTX_C_ DR X_P413
CL _ CL K13 CL _ DA TA13 CL _ RST #13
R4 89 0_0402_5%
CL _ D ATA
R4 90 0_0402_5%
CL _ R ST#
R4 91 0_0402_5%
+3 V _W LAN
0.01U_0 40 2_ 16 V7 K
0. 1U _0 40 2_ 16 V4Z
C5 46
1
A A
2
4. 7U _0 80 5_ 10 V4Z
C5 47
C5 48
1
1
2
2
Close to JP7
+3 VALW
10 K_0 40 2_ 5%
12
R4 87
200 9/0 5/0 2 HP SI-1
MC 2 _ DI SAB LE35
XM I T_ D_ OFF#
Add to prevent leakage issue.
B B
0.1U_ 04 02 _1 0V 6K
@
1 2
R4 88 220K_0402_1%
2 1
D1 5 CH 7 51 H-40PT_SOD 32 3- 2
1
200 8/1 2/1 2 HP
C9 10
@
2
SI2 30 5A DS- T1 -G E3_ SO T23-3
Q2 4
DE G _ FR A ME# DE B UG _AD3 DE B UG _AD2 DE B UG _AD1 DE B UG _AD0
PC I _ RS T#_ R
200 9/0 4/1 0 HP DB-3
R4 85 0_0402_5%
1 2
R4 86 0_0402_5%
1 2
1 2 1 2 1 2
R4 7 7 0_ 0402_5%
1 2
R4 7 8 0_ 0402_5%
1 2
R4 7 9 0_ 0402_5%
1 2
R4 8 0 0_ 0402_5%
1 2
R4 8 1 0_ 0402_5%
1 2
R4 8 2 0_ 0402_5%
1 2
PC I E_ W A KE#
CL K _ PC I E _M CAR D# CL K _ PC I E _M CAR D
PC I _ RS T#_ R CL K _ PC I _ DEB UG
PC I E_ C_ RXN 4 PC I E _C _R XP4
+3 V _W LAN
CL _ C L K_RCL _ C LK CL _ D AT A_R CL _ R ST# _R
T6 7TP C1 2
JP 7
C O N N@
1
1
3
3
5
5
7
7 9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 515152
GND153GND2
MOL EX_67 91 0- 5700
LP C _ LAD3 LP C _ LAD2 LP C _ LAD1 LP C _ LAD0
2 4 6 8
LP C _ LFRAME# 12 ,3 3, 35 ,36
LP C _L AD[0..3 ] 12 ,3 3, 35 ,36 PC I _R ST# 1 5, 30
+3 V _ WLAN
2 4 6
DE G _ FR A ME#
8
DE B UG _AD3
10
DE B UG _AD2
12
DE B UG _AD1
14
DE B UG _AD0
16 18
XM I T_ D_ OFF#
20 22 24 26 28 30 32 34 36
200 8/1 2/1 2 HP
38 40 42
WL _ L ED #
44 46 48 50 52
PL T_ RST# 4,12,15 ,2 0, 26 ,3 1,33
WL _ LED# 33
2A
0.5A
+1 .5 VS
54
WWAN (Full mini Card)
+3 V _ WW AN
JP 9
C O N N@
2.5A
1 3 5
200 8/1 2/1 2 HP
T68
C C
+3 V _ WW AN
D D
1
WW A N_T R AN S MI T_OFF#1 5,33
T69
T70
7
FO X CO N N AS0B2 26 -S 40 N-7F 52 P
D1 7
CH 7 51 H-40PT_SOD 32 3- 2
1 3 5 7 9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 515152
GND153GND2
M_ W X MIT _O FF#
21
2
2
4
4
6
6
8
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
54
2
200 8/1 2/1 2 HP
UI M _PW R UI M _ DA TA UI M _ CL K UI M _ RS T UI M _ VPP
M_ W X MIT _O FF#
WW A N_D E T#
WW _ L E D#
200 9/0 4/1 0 HP DB-3
WW A N_D E T# 15
US B 20 _N9 15 US B2 0_ P9 15
WW _ L ED # 33
MC 1 _ DI SAB LE35
R5 02
@
10 K_0 40 2_ 5%
12
+3 V AL W
3
200 9/0 4/2 4 HP SI-1
R1 18 6
1 2
22 0K_ 04 02 _1%
C9 5 0
0.1U_ 04 02 _1 0V 6K
200 9/0 5/1 3 HP SI-1
C5 66
1
2
Close to JP9
200 9/0 3/0 8 HP DB-3
1
@
2
Security Classification
Issued Date
+3 V _ WW AN
39 P_0 40 2_ 50 V8J
C5 68
39 P_0 40 2_ 50 V8J
C5 67
39 P_0 40 2_ 50 V8J
1
1
2
2
+3 VALW
S
Q8 4
G
SI2 30 5A DS- T1 -G E3_ SO T23-3
2
D
1 3
+3 V _ WW AN
7W
2.5A
2008/09/15 2009/12/31
@
1 2
R1 17 2 0_ 08 05 _5%
Compal Secret Data
Deciphered Date
+3 V _ WW AN
C5 64
0. 1U _0 40 2_ 16 V4Z
C5 63
0.01U_0 40 2_ 16 V7K
C5 65
4. 7U _0 80 5_ 10 V4Z
1
1
2
+3 VS
1
2
2
U2 0
@
1
6
CH1
CH4
2
5
Vn
Vp
4
CH23CH3
S D IO( BR ) NUP 43 01 MR6 T1 TSOP- 6
JP 10
C O N N@
4
12
5 6 7
UI M _PW R
GND VPP I/O DET
TA I TW _PM PAT6-06GLBS7 N14N0
Tit le
Size Do c u me nt N umb er R e v
Da t e: She et o f
UI M _ VPP UI M _ DA TA
R5 04
@
47 K_0 40 2_ 5%
4
1
VCC
2
RST
3
CLK
C5 69
8
GND
9
GND
Compal Electronics, Inc.
WLAN&WWAN
LA -490 1 P
@
18 P_0 40 2_ 50 V8J
1
2
+3 V _ WW AN
DA N217GT1 46 _S C59-3
UI M _PW R UI M _ RS T UI M _ CL K
4. 7U _0 80 5_ 10 V4Z
C5 70
1
2
5
+3 V _ WW AN
3
1
2
D1 6
@
0. 1U _0 40 2_ 16 V4Z
C5 71
1
2
28 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
2
3
4
5
SATA ODD CONN.SATA HDD CONN.
Place caps. near
A A
J H DD1
23
PTH
24
PTH
25
NPTH
26
NPTH
SA NTA_1 92 60 1- 1_ NR
1.1A
C O N N @
GND
GND
GND
3.3V
3.3V
3.3V GND GND GND
GND
RSVD
GND
V12 V12 V12
1
SA TA_P TX_ C_ DRX _P0
2
A+
A­B-
B+
V5 V5 V5
3 4 5 6 7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
SA T A_ PTX_C_DR X_ N0 SA T A_ PRX _C _DTX_ N0
SA TA_P RX_ C_ DTX _P0
+5 VS
1
2
+5 VS
10 U_ 08 05 _1 0V 4Z
C9 12
HDD CONN.
Near CONN side.
10 U_ 08 05 _1 0V 4Z
0. 1U _0 40 2_ 16 V4Z
C1 96
C1 97
1
1
1
2
2
2
1 2 1 2
1 2 1 2
0. 1U _0 40 2_ 16 V4Z C1 98
0. 1U _0 40 2_ 16 V4Z
1
2
S ATA_PTX_D RX_P0
C1 8 60.0 1U _0 40 2_ 16 V7 K C1 8 70.0 1U _0 40 2_ 16 V7 K
SA TA_P TX_ DRX_N 0
C1 8 80.0 1U _0 40 2_ 16 V7 K
SA TA_P RX_ DTX_N 0 S ATA_PR X_DTX_P0
C1 8 90.0 1U _0 40 2_ 16 V7 K
C1 99
SATA_ PTX_DR X_ P0 12 SA TA_PTX_D RX_N0 12
SA TA_PR X_DTX_N0 12 SATA_ PRX _D TX_ P0 12
JO D D 1
17
NPTH
16
NPTH
15
PTH
14
PTH
TY C O_ 1735491-3_NR
C O N N@
GND
TX+
TX-
GND
RX+ RX-
GND
DP
1.6A
MD GND GND
1
SA TA_P TX_ C_ DRX _P1
2
SA T A_ PTX_C_DR X_ N1
3 4
SA T A_ PRX _C _DTX_ N1 SA TA_P RX_ DTX_N 1
5 6 7
R1 79 0 _0 40 2_ 5%@
8 9
V5
10
V5
11 12 13
1 2
+5 VS
Placea caps. near HDD CONN.
B B
NAND FLASH
E-SATA Redriver
200 9/0 5/1 2 HP SI-1 200 9/0 6/3 0 HP SI-2
PI3 EQX 495 1S T_P END an d 1.5V power rai l o pti on 6/30
200 9/0 9/1 0 HP PV
+3 VS +1 .5 VS+3 VS_1 .5 VS
R1 21 6 0_0603_5%@
+3 VS_1 .5 VS
1 2
Place caps. near ODD CONN.
C2 0 20.0 1U _0 40 2_ 16 V7 K
1 2
C2 0 30.0 1U _0 40 2_ 16 V7 K
1 2
C2 0 40.0 1U _0 40 2_ 16 V7 K
1 2
C2 0 60.0 1U _0 40 2_ 16 V7 K
1 2
1
C2 10
@
0. 1U _0 40 2_ 16 V4Z
2
TI & P eri co m selectCha nge TI t o P ericom
S ATA_PTX_D RX_P1 SA TA_P TX_ DRX_N 1
S ATA_PR X_DTX_P1SA TA_P RX_ C_ DTX _P1
OD D _ DET# 15
+5 VS
1
2
Placea caps. near ODD CONN.
R1 21 7 0_0 60 3_ 5%
1 2
SATA_ PTX_DR X_ P1 12 SA TA_PTX_D RX_N1 12
SA TA_PR X_DTX_N1 12 SATA_ PRX _D TX_ P1 12
Near CONN side.
0. 1U _0 40 2_ 16 V4Z
10 U_ 08 05 _1 0V 4Z
1U _0 60 3_ 10 V4 Z
C2 11
C2 13
C2 12
1
1
2
2
10 U_ 08 05 _1 0V 4Z
C2 14
1
2
C C
200 9/0 8/3 0 HP PV
D D
200 9/0 2/2 6 HP DB-2
1
200 9/0 4/2 4 SI-1200 9/0 4/2 4 SI-1
SA TA_P TX_ DRX_P 4_ R
C9 800. 01 U_ 04 02 _1 6V7K
SATA_ PTX_DR X_ P412 SA TA_PTX_D RX_N412 SA TA_PR X_C_D TX_ P432 SA TA_P RX_ C_ DTX _N 432
+3 VS_1 .5 VS
1
2
2
SA TA_P RX_ C_ DTX _P4 SA T A_ PRX _C _DTX_ N4
+3 VS_1 .5 VS
Place caps. near U66
C9 88
1U _0 60 3_ 10 V4 Z
C9 89
0. 1U _0 40 2_ 16 V4Z
C9 90
0.01U_0 40 2_ 16 V7 K
1
1
2
2
1 2 1 2 1 2 1 2
R1 20 3 4.7K_ 04 02 _5%
R1 20 1 4.7K_ 04 02 _5% R1 20 2 4.7K_ 04 02 _5% R1 25 0 4.7K_ 04 02 _5%@ R1 25 1 4.7K_ 04 02 _5%@
3
SA T A_ PTX_DRX_ N4 _R SAT A _PTX_C_D RX _N4_R SA T A_ PTX_C_DR X_ N4
C9 810. 01 U_ 04 02 _1 6V7K
SA T A_ PRX _C _DTX_ P4_ R
C9 860. 01 U_ 04 02 _1 6V7K C9 870. 01 U_ 04 02 _1 6V7K
1 2
1 2 1 2 1 2 1 2
Security Classification
Issued Date
U6 6
1
AI+
2
AI-
11
BI+
12
BI-
7
EN
17
MODE
8
B_EM / B_EQ
9
A_EM / B_EM
2008/09/15 2009/12/31
6
10
20
16
AO+
VDD18
VDD18
VDD18
VDD18
3
50mA
GND / A_EN#
13
GND / B_EN#
GND / A_EM
GND / A_EQ18HEATGND
19
21
AO-
BO+
BO-
PI 2EQX4 95 1S LZD EX_ TQ FN2 0_ 4X 4
Compal Secret Data
Deciphered Date
4
SA T A_ PTX_C_DR X_ P4_ R SA TA_P TX_ C_ DRX _P4
15 14
SA TA_P RX_ DTX_P 4_ R
5
SA T A_ PRX _D TX_ N4 _RSA TA_PR X_C_DTX_ N4 _R
4
C984, C985 near JP29
C9 84 0.01U_ 04 02 _1 6V 7K
1 2
C9 85 0.01U_ 04 02 _1 6V 7K
1 2
C9 82 0.01U_ 04 02 _1 6V 7K
1 2
C9 83 0.01U_ 04 02 _1 6V 7K
1 2
C982, C983 near U4
Tit le
Size Do c u me nt N umb er R e v
Da t e: She et o f
Compal Electronics, Inc.
NAND/HDD/ODD/E-SATA Redriver
LA- 4901P
5
SA TA_P TX_ C_ DRX _P4 32 SA TA_P TX_ C_ DRX _N 4 32 SA TA_PR X_DTX_P4 12 SA TA_PR X_DTX_N4 12
1. 0
29 54T u esd ay , Dec ember 15, 2 00 9
1
PC I _ AD[ 0. .3 1]15
+3 VS
R5 14
10 0K_ 04 02 _1%
12
A A
CB S _ GR ST#
1
C6 08 1U_0603_10V6K
2
200 8/1 2/1 2 HP
B B
PC I _ AD 22 CB S _I DSE L
Layout Note: Add GND shield.
CL K_PC I_ 13 9415
PM _ CL K RU N#14,3 3, 35 ,36
C C
+S C _PW R
200 9/0 5/1 6 HP SI-1
CL K_PCI _1 39 4
12
R5 15
@
10 _0402_5%
1
C6 09
@
4.7P_ 04 02 _5 0V 8C
2
PC I _ CBE 3#15 PC I _ CBE 2#15 PC I _ CBE 1#15 PC I _ CBE 0#15
PC I _ PAR15 PC I _ FR AME#15 PC I _ TR DY #15 PC I _ IR D Y#15 PC I _S TOP #15
R5 16
1 2
10 0_0402_5%
SC _ C LK SC_ C L K_ R
200 9/0 3/0 8 SI- 1 A dd R for RF
+S C _PW R
D6 9 1N 4 1 48 WS FL_ SO D323-2
D7 0 1N 4 1 48 WS FL_ SO D323-2
D7 1 1N 4 1 48 WS FL_ SO D323-2
R5 36 1 5K_0402_5% R9 62 1 5K_0402_5% R9 63 1 5K_0402_5%
PC I _ DE VSE L#15 PC I _ PE RR#15
PC I _ SE RR#15,33,35
PC I _R EQ2#15 PC I _G NT2 #15
200 8/1 2/1 2 HP
PC I _R ST#15 ,2 8
R5 20 10K_0 40 2_ 5%@
1 2
R5 21 0_0402_5%
1 2
R5 22 10K_0 40 2_ 5%
1 2
+3 VS
R1 17 3 47_0402_5%
1 2
1 2
R5 27 1 0K_0402_5%
PC I _ PIR QE #15 PC I _ PIR QG #15
R5 30 10K_0 40 2_ 5%
+3 VS
R5 31 100K_ 04 02 _5%
1 2
1 2
1 2
1 2 1 2 1 2
1 2 1 2
200 9/0 3/0 8 HP DB-3
SC _ D ATA SC _ R ST SC _ C LK
PC I _ AD 31 PC I _ AD 30 PC I _ AD 29 PC I _ AD 28 PC I _ AD 27 PC I _ AD 26 PC I _ AD 25 PC I _ AD 24 PC I _ AD 23 PC I _ AD 22 PC I _ AD 21 PC I _ AD 20 PC I _ AD 19 PC I _ AD 18 PC I _ AD 17 PC I _ AD 16 PC I _ AD 15 PC I _ AD 14 PC I _ AD 13 PC I _ AD 12 PC I _ AD 11 PC I _ AD 10 PC I _ AD 9 PC I _ AD 8 PC I _ AD 7 PC I _ AD 6 PC I _ AD 5 PC I _ AD 4 PC I _ AD 3 PC I _ AD 2 PC I _ AD 1 PC I _ AD 0
PC I _ CB E#3 PC I _ CB E#2 PC I _ CB E#1 PC I _ CB E#0
PC I _ P AR PC I _ FR A ME# PC I _ TR D Y# PC I _ IR D Y# PC I _ STO P# PC I _ D EVS EL#
PC I _ P ERR # PC I _ S ERR #
PC I _ RE Q2 # PC I _ GNT2#
CL K_PCI _1 39 4 CB S _ GR ST#
PM E# SC _ R ST SC _ D ATA
SC _ C D# SC S EN S E
U2 1
121
AD31
122
AD30
123
AD29
124
AD28
125 126 127
1 4 5 7
9 10 12 13 14 27 28 29 30 31 32 34 36 39 40 41 42 43 44 45 46
2 15 26 37
25 16 18 17 21 19
3 22 24
120 119
117 116
82
114
78
89 88 87 86 85
112 113
77 81
98
101 105 109
C6 19 12P_ 04 02 _5 0V 8J
1 2
C6 22 12P_ 04 02 _5 0V 8J
1 2
C6 23 12P_ 04 02 _5 0V 8J
1 2
R5C835
AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
C/BE3# C/BE2# C/BE1# C/BE0#
PAR FRAME# TRDY# IRDY# STOP# DEVSEL# IDSEL PERR# SERR#
REQ# GNT#
PCICLK PCIRST# GBRST# CLKRUN# PME#
SCRST SCCLK SCIO SCCD# SCSENSE
INTA# INTB#
HWSPND# TEST
AGND AGND AGND AGND
R5C83 5- TQ FP1 28 P_TQFP12 8_ 14 X1 4
SMART Card Connector
JP 38
C O N N@
20
191920
D D
171718 151516 131314 111112 9910 778 556 334 112
E-T _6 90 0- Q1 0N-00R
+S C _PW R
18
SC _ R ST
16 14
SC _ C LK
12
SC _ D ATA
10 8 6
SC _ C D#
4 2
GND GND GND
Layout Note: Add GND shield
1
+S C _PW R
1
2
C8 40
0. 1U _0 40 2_ 16 V4Z
2
VCC_PCI3V
2.5mA
VCC_PCI3V VCC_PCI3V VCC_PCI3V
49mA
VCC_RIN
VCC_ROUT VCC_ROUT VCC_ROUT VCC_ROUT VCC_ROUT
0.2mA
VCC_3V
10mA
VCC_MD3V
AVCC_PHY3V
25.6mA
AVCC_PHY3V AVCC_PHY3V
2mA
VCC_SC
TPBIAS0
TPAP0 TPAN0
TPBP0 TPBN0
MDIO00 MDIO01 MDIO02 MDIO03 MDIO04 MDIO05 MDIO06 MDIO07 MDIO08 MDIO09 MDIO10 MDIO11 MDIO12 MDIO13 MDIO14 MDIO15 MDIO16 MDIO17 MDIO18 MDIO19
SCVCC5EN# SCVCC3EN#
XI
XO
REXT VREF
UDIO0/SRIRQ#
UDIO1 UDIO2 UDIO3 UDIO4 UDIO5
GND GND GND GND GND GND GND GND GND GND
Layout Note: Add GND shield for 1394.
2
0.01U_0 40 2_ 16 V7 K
6 23 38 118
92 11
33 59 91 111
79 54
+3 V _ PH Y
97 104 108
90
IE E E1394_TPBI AS0
110
IE E E1394_TPAP 0
107
IE E E1 39 4_ TPA N0
106
IE E E1394_TPBP 0
103
IE E E1 39 4_ TPB N0
102
SD _ C AR D _ DET #
70
MD I O0 1
69
XD _ CE #
63
SD _ W P
68
SD P WR 0 _ MS P WR _XD PWR
67
XD W P#
66
3I N 1 _L ED#
65 64
SD _ MM C _ CMD
62
SD C L K_ M MC CL K_R
60
SD D AT A 0_MSDATA0
58
SD D AT A 1_MSDATA1
57
SD D AT A 2_MSDATA2
56
SD D AT A 3_MSDATA3
55
MM C _D 4
53
MM C _D 5
52
MM C _D 6
51
MM C _D 7
50
XD C LE
49
X DAL E
48
SC V CC 5 E N#
83
SC V CC 3 E N#
84
R 5C 83 2XI
95
R 5C 83 2XO
96 100
99
SI R Q
76
TP _ UD IO 1
75
TP _ UD IO 2
74
UD I O 3
73
UD I O 4
72
UD I O 5
71 8
20
Layout Note:
35
Please them close to U21.
47 61 80 93 94 115 128
IE E E1 39 4_ TPB N0 IE E E1394_TPBP 0 IE E E1 39 4_ TPA N0 IE E E1394_TPAP 0
C5 91
1
2
IE E E1394_TPBI AS0
0.01U_0 40 2_ 16 V7 K
0.01U_0 40 2_ 16 V7 K
C5 92
1
2
1
2
56 .2_0402_1%
12
56 .2_0402_1%
12
1
@
2
0.01U_0 40 2_ 16 V7 K
C5 93
C5 94
1
1
2
2
+3 VS
0.01U_0 40 2_ 16 V7 K
10 U_ 08 05 _1 0V 4Z
1
1
2
2
C6 06
C6 07
IE EE 13 94 _TP AP0 31 IE E E1394_TPAN 0 31
IE EE 13 94 _TP BP0 31 IE E E1394_TPBN 0 31
SD _ C AR D _D ET# 31
T81 T82
S D _WP 31
SD P WR 0 _ MS P WR_ XDPWR 31
T83 T84
SD _ MM C _C MD 31
SD D AT A 0_ MSD ATA0 31
SD D AT A 1_ MSD ATA1 31
SD D AT A 2_ MSD ATA2 31
SD D AT A 3_ MSD ATA3 31
MM C_D4 31
MM C_D5 31
MM C_D6 31
MM C_D7 31
T85 T86
SI R Q 12 ,3 3,35,36
T87 T88
200 9/0 2/2 4 Com pal DB -2 for layout
27 0P_ 04 02 _5 0V 7K
R5 34
5.1K_ 04 02 _1 %
C6 24
12
R5 3 8
56 .2_0402_1%
R5 3 7
12
R5 45
56 .2_0402_1%
R5 44
12
0.01U_0 40 2_ 16 V7 K
0. 33 U_ 06 03 _1 6V4Z
C6 31
C6 32
1
2
3
+3 VS
10 U_0805_10V4 Z
C5 95
1
2
0.01U_0 40 2_ 16 V7K
0.01U_0 40 2_ 16 V7K
0.47U_0 60 3_ 16 V4 Z
1
1
1
2
2
2
C6 03
C6 02
C6 04
GND
GND GND
R1 04 8 33_ 04 02 _5%
1 2
Layout Note: Add GND shield for SDCLK_MMCCLK, SDPWR0_MSPWR_XDPWR.
Security Classification
3
0. 1U _0 40 2_ 16 V4Z
0.01U_0 40 2_ 16 V7 K
1
2
GND
0.47U_0 60 3_ 16 V4 Z
C6 05
GND
1
1
1
2
2
2
C5 99
C5 98
C5 97
1
2
C6 10
Layout Note: Add GND shield for
1394.and Same length as TPA+/-,TPB+/-
GND
Layout Note: Shield GND for CBS_CCLK_INTERNAL and CBS_CCLK
0.01U_0 40 2_ 16 V7K
1
2
Issued Date
4
Layout Note: Place close to R5C835 and Shield GND for SDCLK_MSCLK
C5 96
+3 VS
10 U_ 08 05 _1 0V 4Z
0.01U_0 40 2_ 16 V7 K
1
2
C6 00
+S C _PW R
0.01U_0 40 2_ 16 V7K
10 U_0805_10V4 Z
1
2
C6 11
SD C L K_ MM CCL K 31
C6 15
10 K_0 40 2_ 1%
12
R5 26
1 2
16 P_0 40 2_ 50 V8J
C6 01
1 2
16 P_0 40 2_ 50 V8J
+3 VS
Layout Note: Place these cap close to U21
SC V CC 3 E N#
+3 VS
SC V CC 5 E N#
2008/03/13 2009/05/11
Layout Note: Place close to R5C835 and Shield GND for SD_CLK
R 5C 83 2XI
12
X1 24 .576MHz_16P_ 3X G- 24 57 6-43E1
R 5C 83 2XO
200 9/0 4/0 7 DB- 3 Compal
L23 MB K20 1 26 01 YZF_2P
1 2
1
C9 45
0.1U_ 04 02 _1 0V 6K
1 2
R1 16 4
10 0K_ 04 02 _5%
2
2
G
Compal Secret Data
Deciphered Date
4
200 8/1 2/0 6 fol low UMA
+5 VS
12
R1 16 1 10 K_0 40 2_ 5%
R1 16 3 0_0 40 2_ 5%
13
D
Q8 3
S
SS M3 K7002F_ SC5 9- 3
SD,MMC,MS,XD muti-function pin define
MDIO PIN Name MDIO00
SD Card PIN Name
SDCD# MDIO01 MDIO02 MDIO03 MDIO04 MDIO05 MDIO06
SDWP#
SDPWR0
SDPWR1
SDLED# MDIO07 MDIO08
+3 V _ PHY
0.01U_0 40 2_ 16 V7K
10 U_0805_6.3V 6M
1
1
2
2
C6 1 3
C6 1 2
MDIO10
10 00P_0 40 2_ 25 V8J
MDIO11 MDIO12
1
MDIO13 MDIO14
2
C6 1 4
MDIO15
SDCCMD
SDCCLKMDIO09
SDCDAT0
SDCDAT1
SDCDAT2
SDCDAT3
MDIO16 MDIO17 MDIO18 MDIO19
SD,MMC for Cartier DIS and UMA
Function set pin define
UDIO3 UDIO5UDIO4 Function
Pull-down Disable MS,xD Card,serial ROMPull-down P ull-up
AP 23 01 GN -H F_SOT23-3
Q79
3 1
1 2
Pull-downPull-upPull-up Enable serial EEPROM
Pull-upPull-upPull-up Ensable MS,xD Card,disable serial ROM
UD I O 5 UD I O 3 UD I O 4
2
R5 17 100K_ 04 02 _5%
1 2
R5 18 10K_0 40 2_ 5%@
1 2
R5 19 10K_0 40 2_ 5%@
1 2
R5 23 100K_ 04 02 _5%@
1 2
R5 24 10K_0 40 2_ 5%
1 2
R5 25 10K_0 40 2_ 5%
1 2
200 9/0 2/2 4 Com pal DB-2 200 9/0 4/1 6 Com pal DB -3 follow KAQ 00
+S C _PW R
0.1U_ 04 02 _1 0V 6K
C9 46
1
2
1
C9 48
@
0.1U_ 04 02 _1 0V 6K
2
+5 VS
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
AP 23 01 GN -H F_SOT23-3
Q81
Compal Electronics, Inc.
1394+2 in 1 Card
LA -490 1 P
5
MMC Card PIN Name MMCCD#
MMCPWR
MMCLED#
MMCCMD MMCCLK MMCDAT0 MMCDAT1 MMCDAT2 MMCDAT3 MMCDAT4 MMCDAT5 MMCDAT6 MMCDAT7
+3 VS
31
2
SC V CC 3 E N#
5
MS Card PIN Name
MSCD#
MSPWR
MSLED# MSEXTCK MSBS MSCCLK MSCDAT0 MSCDAT1 MSCDAT2 MSCDAT3
AP 23 09 GN -H F_SOT23-3
Q82
3 1
R1 16 2
2
10 0K_ 04 02 _5%
12
30 54T u esd ay , Dec ember 15, 2 00 9
XD Card PIN Name XDCD0#
XDCD1# XDCE# XDR/B# XDPWR XDWP# XDLED#
XDWE# XDRE# XDCDAT0 XDCDAT1 XDCDAT2 XDCDAT3 XDCDAT4 XDCDAT5 XDCDAT6 XDCDAT7 XDCLE XDALE
0.1U_ 04 02 _1 0V 6K
C9 47
1
2
+3 VS
1. 0
1
2
3
4
5
AUDIO BOARD CONNECTOR (MALE)
US B 20 _N415 US B2 0_ P415 CP P E#15
200 9/0 7/2 1 HP SI-2
A A
SD P WR 0 _ MS P WR_ XDPWR30
B B
+5 VALW
PC I E_ W AKE #14 ,2 8 CL K RE Q_EXP#13 CL K _P CIE_E XP#13 CL K _P CIE_E XP1 3 PC I E_ PRX _DTX_ N213 PC IE _PRX_ DTX _P 213 PC I E_ PTX_C _D RX_ N213 PC I E_ PTX_C_ DR X_P213 SL P_S3#14 ,3 5, 37 ,38,40,42 ,4 3, 44,4 8 PL T_RST#4,12,15 ,2 0, 26 ,2 8,33
+1 .5 VS A_ SD #35 SD D AT A 0_ MSD ATA030 SD D AT A 1_ MSD ATA130 SD D AT A 2_ MSD ATA230 SD D AT A 3_ MSD ATA330 MM C_D430 MM C_D530 MM C_D630 MM C_D730
SD C L K_ MM CCL K30 SD _ MM C _C MD30 SD _ W P30
SD _ C AR D _D ET#30
+5 VS
US B 20_N4 US B 20 _P4
PC I E_ W A KE# CL K R EQ_ EXP# CL K _ PCI E_ EXP # CL K _ PC IE_EX P PC I E_ PR X_DTX_N2 PC I E_ PRX _DTX_ P2 PC I E _P TX_ C_DRX _N 2 PC I E_ PTX_C _D RX_ P2 S LP_ S3 # PL T _R ST#
Power Button
S W 1
@
1BT 00 2- 01 21 L_4P
3
1 2
4
5
6
C C
R6 09 4 7_ 04 02 _5 %
ON / O F F#
1 2
ON / O FF # 34
C7 12 1U _0 60 3_ 10 V4 Z
JP 5
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
GND
E&T_1000-F68 E-04R
C O N N @
+3V L
12
R6 0 7 10 0K_ 04 02 _5 %
1
200 9/0 7/2 1 HP SI-2
2
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
HD D _ HA L TLED
42
42
SA T A_ LED#
44
44
AM BER _ BAT LED#
46
46
AQ U AWH I T E_BATL ED #
48
48
WL / B T_L ED#
50
50
ST B_LED#
52
52
54
54
56
56
58
58
60
60
62
62
64
64
66
66
68
68
70
GND
D3 1
@
21
CH 7 51 H-40PT_SOD 32 3- 2
+3 VS
LI N E _IN _SE NSE 34 DO C K _H PS# 34 DO C K _L IN E_ IN_ L 34 DO C K _L I NE_I N_ R 34 DL I NE _O UT_ L 34 DL I N E_ OU T_R 34
HD A _ BI T _CLK _C ODEC 12 HD A _ SD O U T_ CO DE C 12 HD A _ SD IN 0 12 HD A _ SY N C_ C O D EC 12 HD A _ RS T #_ CO DE C 12 HD A _ SP KR 12
+3 VALW
MU TE_ LED_ CNTL 35
+3V L
ON / O FF B TN _K BC# 35
R6 10 100K_ 04 02 _5%@
R1 22 8 0_0402_5%
200 9/0 1/2 1 COM PAL EMI
HD D _ HA L TL ED 12 SA TA_L ED# 12, 34 AM BER _B ATL ED# 35 AQ U AWH I TE _BATLED# 12,35 WL / B T_L ED# 33 ST B_LED# 34
IE E E1394_TPBN 0 30 IE EE 13 94 _TP BP0 30
IE E E1394_TPAN 0 30 IE EE 13 94 _TP AP0 30
R1 17 9 0_0 40 2_ 5%
1 2
1 2
1 2
200 9/0 5/0 2 HP SI-1200 9/0 5/0 2 HP SI-1
+3 V AL W
ON / O FF B TN# 14
PW R BT N _O UT# 34,35
MDC 1.5 Conn.
JP 21
C O N N@
ACE S_88020 -121 01 _1 2P
1
HD A _ SD O U T_ MDC12 HD A _ SY N C_ M D C12
HD A _ SD I N112 HD A _ RS T #_ MDC12
1 2
R6 05 33_ 04 02 _5 %
HD A _ SD O U T_ MDC HD A _ SY N C_ M D C
HD A _ SD I N 1_ MDC
1
3
3
5
5
7
7
9
9
11
11
GND13GND14GND15GND16GND17GND
+3 VS
2
2
4
4
6
6
8
8
10
10
12
12
R6 06 0 _0 40 2_ 5%
1 2 1 2
C7 06
10 P_0 40 2_ 25 V8K@
HD A _ BI T _CLK_ MDC 12
INT_KBD CONN.
JP 36
K SO1 1 KS O 0 KS O 2 KS O 5 KS I _D _1 4 KS I _D _8 KS I _D _1 2 KS I _D _1 0 KS I _D _0 KS I _D _4 KS I _D _2 KS I _D _1 KS I _D _3 KS O 3 KS O 8 KS O 4 KS O 7 KS O 6 K SO1 0 KS O 1 KS I _D _5 KS I _D _6 KS I 7 KS I _D _1 3 KS I _D _1 1 KS I _D _9 KS O 9 K SO1 2 K SO1 3
C O N N @
1 3 5 7
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
61 62
HI R O SE FH1 2H P- 30 S-1SV 55 30P
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
GND1 GND2
GND3 GND4
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
63 64
KS I 0
KS I 1
KS I 2
K SO1 1 KS O 0 KS O 2 KS O 5 KS I _D _1 4 KS I _D _8 KS I _D _1 2 KS I _D _1 0 KS I _D _0 KS I _D _4 KS I _D _2 KS I _D _1 KS I _D _3 KS O 3 KS O 8 KS O 4 KS O 7 KS O 6 K SO1 0 KS O 1 KS I _D _5 KS I _D _6 KS I 7 KS I _D _1 3 KS I _D _1 1 KS I _D _9 KS O 9 K SO1 2 K SO1 3
D2 4
1
DA P202U_S OT3 23 -3 D2 6
1
DA P202U_S OT3 23 -3 D2 8
1
DA P202U_S OT3 23 -3
CAP SWITCH BOARD.
12
CA P _CLK1 3, 35 CA P _DAT13,3 5 CA P _INT35
R6 04
10 K_0 40 2_ 5%
12
CP 2
4 5 3 2
CP 3
4 5 3 2
CP 5
2 3 4 5
KS I 3
KS I 4
KS I 5
KS I 6
12
C8 36
KS O [0 ..13] KS I [0 ..7 ]
@
6 7 81
@
6 7 81
@
81 7 6
D2 3
1
DA P202U_S OT3 23 -3 D2 5
1
DA P202U_S OT3 23 -3 D2 7
1
DA P202U_S OT3 23 -3 D2 9
1
DA P202U_S OT3 23 -3
+3 VS+3V L +V REG 3_ 51 12 5
KS O [0 ..13]35 KS I [0 ..7 ]35
KS I _D _1 4 KS I _D _8 KS I _D _1 2 KS I _D _1 0
10 0P_ 12 06 _8 P4 C_ 50 V8K
K SO1 1 KS O 0 KS O 2 KS O 5
10 0P_ 12 06 _8 P4 C_ 50 V8K
KS O 8 KS O 3 KS I _D _9 KS I _D _3
10 0P_ 12 06 _8 P4 C_ 50 V8K
KS I _D _0
2
KS I _D _8
3
KS I _D _1
2
KS I _D _9
3
KS I _D _2 K S I_ D_ 5
2
KS I _D _1 0 KS I _D _1 3
3
10 00P_0 40 2_ 50 V7K
R6 03 5. 1K_ 04 02 _5 %12R6 02 5. 1K_ 04 02 _5 %
CA P _RS T_E C35 WL / BT_LED#33
ST B_ LED#34 LI D _S W#19 ,3 5
CP 1
KS O 9
2
KS I 7
3
KS I _D _6
4 5
10 0P_ 12 06 _8 P4 C_ 50 V8K
CP 4
KS I _D _1 1 KS O 1
2
K SO1 0
3
KS O 6
4 5
10 0P_ 12 06 _8 P4 C_ 50 V8K
CP 6
KS I _D _1 KS I _D _2
2
KS I _D _0
3
KS I _D _4
4 5
10 0P_ 12 06 _8 P4 C_ 50 V8K
CP 7
KS I _D _5 KS O 7
2
KS I _D _1 3
3
KS O 4
4 5
10 0P_ 12 06 _8 P4 C_ 50 V8K
KS I _D _3
2
KS I _D _1 1
3
KS I _D _4
2
KS I _D _1 2
3
2 3
KS I _D _6
2
KS I _D _1 4
3
+3V L
200 9/0 6/3 0 HP SI-2
1 2
R1 78 100 K_0402_5%
200 9/0 8/3 0 HP PV
C8 37 0 .1 U_ 06 03 _5 0V4Z
1 2
200 9/0 1/2 1 COM PAL EMI
JP 37
1
2
1
2
3
4
3
4
5
6
5
6
7
8
7
8
9
10
9
10
11
12
11
12
13
14
13
14
15
16
15
16
17
18
17
18
19
20
19
ON / O F F# LI D _ SW#
20
22
21
22
24
23
24
ACE S 8 52 03 -1 20 21 1 2P P1 .0
C O N N@
21 23
@
81 7 6
@
81 7 6
@
81 7 6
@
81 7 6
LI D _ SW#
+V REG 3_ 51 12 5
CA P _R ST_ EC WL / B T_L ED#
CA P _ CL K CA P _ DA T CA P _ IN T
ST B_LED# ON / O F F# LI D _ SW#
+3 VS
18
D D
200 9/0 1/2 1 HP
1
+3 VS
C7 03
10 00P_0 40 2_ 50 V7K
C7 04
0. 1U _0 40 2_ 16 V4Z
C7 05
1
2
4. 7U _0 80 5_ 10 V4Z
1
1
@
2
2
2
Security Classification
Issued Date
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Da t e: She et o f
Compal Electronics, Inc.
MDC/KBD/ON_OFF/CAP
LA -490 1 P
5
31 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
USB CONN.
+5 V AL W US B _VC CA+5V AL W
12
R6 13
U2 9
1
A A
SL P_ S438
B B
C C
S LP_ S4
1
C7 1 3
4. 7U _0 80 5_ 10 V4Z
S LP_ S4
4. 7U _0 80 5_ 10 V4Z
2
+5 V AL W US B _VC CB+ 5 VA LW
1
C7 1 9
2
GND
2
IN
3
IN
4
EN#
G5 4 7 F2P 81 U_MSO P8
(2A,100mils ,Via NO.=4)
1 2
PA D -SH O RT 2x 2m
U3 0
1 2 3 4
G5 4 7 F2P 81 U_MSO P8
(2A,100mils ,Via NO.=4)
GND IN IN EN#
8
OUT
7
OUT
6
OUT
5
OC#
J4
US B _VC CBUS B_V C CA
US B 20 _P015
US B 20_N015
@
8
OUT
7
OUT
6
OUT
5
OC#
200 9/0 7/2 1 Com pal SI-2 EMI
10 K_0 40 2_ 5%
W=100mils
1
C7 14
+
@
2
R1 23 0 0_0402_5%
1
4
R1 23 1 0_0402_5%
R6 16 10 K_0 40 2_ 5%
1 2
W=100mils
C7 20
+
US B 20 _P115
US B 20 _N115
2
15 0 U_ B2_6.3V M_R35 M
10 00P_0 40 2_ 50 V7K
0. 1U _0 40 2_ 16 V4Z C7 1 6
C7 1 5
1
1
2
2
1 2
L52
@
1
4
WCM -2 01 2- 90 0T_ 4P
2
2
3
3
1 2
15 0 U_ B2_6.3V M_R35 M
0. 1U _0 40 2_ 16 V4Z C7 22
C7 21
1
2
R1 23 3 0_0 40 2_ 5%
1
4
R1 23 5 0_0 40 2_ 5%
1
2
1 2
L54
@
1
4
WCM -2 01 2- 90 0T_ 4P
1 2
1
2
2
3
US B 20_P0_ R
US B 2 0_ N0 _R
200 9/0 7/2 1 Com pal SI-2 EMI
10 00P_0 40 2_ 50 V7K
US B 20_P1_ R
2
US B 2 0_ N1 _R
3
US B 2 0_ N0 _R US B 20_P0_ R
C O N N@
US B 2 0_ N1 _R US B 20_P1_ R
200 9/0 8/1 4 Com pal DFB PV
JP 27
1
1
2
2
3
3
4
4
5
GND
6
GND
7
GND
8
GND
SU Y IN 0 20 13 3MR00 4S 53 6ZL 4 P
US B 20_P0_ RUSB 2 0 _N0_R
2
3
D3 3
@
PJ D L C05H_ SO T23-3
200 9/0 2/1 8 Com pal DB-2 EMI
1
200 9/0 8/1 4 Com pal DFB PV
JP 28
1
1
2
2
3
3
4
4
5
GND
6
GND
7
GND
8
GND
SU Y IN 0201 33 MR 00 4S5 36 ZL 4PC O N N @
US B 20_P1_ RUS B 2 0_ N1 _R
2
3
D3 4
@
PJ D LC 05 H_SOT 23 -3
200 9/0 2/1 8 Com pal DB-2 EMI
1
3
+3 VS
0. 1U _0 40 2_ 16 V4Z
C7 23
1
2
+3 VS_A CL_IO
+3 VS
S LP_ S4
C8 77
4. 7U _0 80 5_ 10 V4Z
US B2 0_ P315
US B 20 _N315
C7 24
+3 VS
ODM part# HP302DLTR8-MBD
10 U_0603_6.3V 6M
1
2
AC C EL _ IN T#15
SM B_DA TA_ S34,9 ,1 0, 11 ,13 SM B_CL K_ S34 ,9 ,10,11,13
R6 1 9 10 K_0 40 2_ 5%
Must be placed in the center of the system.
L
+5 V AL W US B _VC C D+5 V AL W
1
2
+3 VS +3 V S_ ACL _I O
1 2
1
0.4mA
6 8
12 13
12
14
7
U6 2
1
GND
2
IN
3
IN
4
EN#
G5 4 7 F2P 81 U_MSO P8
(2A,100mils ,Via NO.=4)
R1 23 2 0_0402_5%
1 2
L53
@
1
1
4
4
WCM -2 01 2- 90 0T_ 4P
1 2
R1 23 4 0_0402_5%
R6 17 0_ 0603_5%
U3 1
LIS302DL
VDD_IO
GND
VDD
GND GND
INT 1 INT 29GND
SDO SDA / SDI / SDO SCL / SPC
RSVD
CS
RSVD
HP 30 2DLTR 8_ LG A14_3X5
8
OUT
7
OUT
6
OUT
5
OC#
US B 20_P3_ R
2
2
US B 2 0_ N3 _R
3
3
200 9/0 7/2 1 Com pal SI-2 EMI
4
5
BT ConnectorACCELEROMETER
JP 26
70mA
1 2
US B 20_P8_ R
R6 11 0_ 0402_5%
3
US B 2 0_ N8 _R
4 5
ACE S_87212 -05G 0_ 5P
C O N N@
2 4 5 10
3
+3 VS
11
12
R1 01 2 10 K_0 40 2_ 5%
W=100mils
C8 78
BT _ OFF15
15 0 U_ B2_6.3V M_R35 M
1
+
2
10 00P_0 40 2_ 50 V7K
0. 1U _0 40 2_ 16 V4Z C8 80
C8 79
1
1
2
2
1 2
R6 12 0_ 0402_5%
1 2
12
R6 14 10 K_0 40 2_ 5%
R6 1 5
1 2
22 0K_ 04 02 _1%
US B 20_P3_ RU SB2 0 _N 3_ R
2
3
D6 8 PJ D LC 05 H_SOT 23 -3
Q3 3 SI23 01CDS -T1-GE3 _S OT2 3- 3
S
G
2
SS M3K7 00 2FU_SC7 0- 3
200 9/0 9/0 3 Com pal PV
US B 2 0_ N3 _R US B 20_P3_ R
@
200 9/0 2/1 8 Com pal DB-2 EMI
1
+3 VAU X_ BT
D
13
12
R1 24 5
47 0_0402_5%
13
D
Q9 3
2
G
S
200 9/0 8/1 4 Com pal DFB PV
JP 39
1
1
2
2
3
3
4
4
5
GND
6
GND
7
GND
8
GND
SU Y IN 0 20 13 3MR00 4S 53 6ZL 4 PC O N N @
US B 20 _P8 15 US B 20 _N8 15 BT _L ED 33
+3 VAU X_ BT+3 V AL W
C7 17 0. 1U _0 40 2_ 16 V4Z
1
1
2
2
C7 18 10 U_ 08 05 _1 0V 4Z
USB and E-SATA Combo CONN.
R1 23 6 0_0 40 2_ 5%
1 2
L55
@
D D
US B2 0_ P215
US B 20 _N215
1
1
1
4
4
WCM -2 01 2- 90 0T_ 4P
1 2
R1 23 7 0_0 40 2_ 5%
2
2
3
3
US B 20_P2_ R
US B 2 0_ N2 _R
200 9/0 7/2 1 Com pal SI-2 EMI
+5 VALW U S B_ V C CC+ 5 VALW
U3 2
1
GND
2
IN
3
S LP_ S4
C7 25
4. 7U _0 80 5_ 10 V4Z
1
2
IN
4
EN#
G5 4 7 F2P 81 U_MSO P8
(2A,100mils ,Via NO.=4)
US B 20_P2_ RU S B2 0_N2_R
2
3
D3 6
@
PJ D LC 05 H_SOT 23 -3
200 09/ 02/ 18 Co mpa l DB-2 EMI
1
2
12
R6 18 10 K_0 40 2_ 5%
8
OUT
7
OUT
6
OUT
5
OC#
W=100mils
1
+
C7 26
2
15 0 U_ B2_6.3V M_R35 M
0. 1U _0 40 2_ 16 V4Z
10 00P_0 40 2_ 50 V7K
C7 27
C7 28
1
1
2
2
Security Classification
Issued Date
3
SA TA_PTX_C _D RX_ P429 SA TA_P TX_ C_ DRX _N 429
SA TA_P RX_ C_ DTX _N 429 SA TA_PR X_C_D TX_ P429
2008/09/15 2009/12/31
US B 2 0_ N2 _R US B 20_P2_ R
SA TA_P TX_ C_ DRX _P4 SA T A_ PTX_C_DR X_ N4
SA T A_ PRX _C _DTX_ N4 SA TA_P RX_ C_ DTX _P4
Compal Secret Data
Deciphered Date
4
200 9/0 5/1 2 HP SI-1
JP 29
USB
1
VBUS
2
D-
3
D+
4
GND
5
GND
6
A+
ESA TA
7
A-
8
GND
9
B-
10
B+
11
GND
12
GND
13
GND
Boss
14
GND
Boss
15
GND
TA I WI _ EU0 16 -1 17 CR L- TW
C O N N@
16 17
Tit le
Size Do c u me nt N umb er R e v
Da t e: She et o f
Compal Electronics, Inc.
USB/BT/E-SATA Conn/Acclerometer
LA -490 1 P
5
32 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
2
3
4
5
LPC Debug Port
80 5 1 _ RECOV ER#
A A
CL K _ PC I_ DB15
LP C _ LFRAME#1 2, 28 ,3 5, 36 SI R Q12 ,3 0, 35 ,3 6 PL T_ RST#4,12,15 ,2 0, 26 ,2 8, 31 PC I _ SE RR #15 ,30,35 LP C _L AD012 ,2 8,35,36 LP C _L AD112 ,2 8,35,36 LP C _L AD212 ,2 8,35,36 LP C _L AD312 ,2 8,35,36
80 51TX35 80 51RX35 80 5 1 _R EC OVE R#35 DE B UG _ K BC RS T42
SP I _C S1#35
R6 3 2 10 0K_ 04 02 _5%
1 2
B+ _ DEBU G
SI R Q
80 5 1 _ RECOV ER# SP I _ CL K_ JP
SP I _ CS 0# _JP SP I _SI_ JP SP I _SO_ JP SP I _HOL D# _0
+3V L
JP 13
1
Ground
2
LPC_PCI_CLK
3
Ground
4
LPC_FRAME#
5
+V3S
6
LPC_RESET#
7
+V3S
8
LPC_AD0
9
LPC_AD1
10
LPC_AD2
11
LPC_AD3
12
VCC_3VA
13
PWR_LED#
14
CAPS_LED#
15
NUM_LED#
16
VCC1_PWRGD
17
SPI_CLK
18
SPI_CS#
19
SPI_SI
20
SPI_SO
21
SPI_HOLD#
22
Reserved
23
Reserved
24
Reserved
ACE S_87216 -240 4_ 24 P
C O N N@
Finger Printer
B B
F PR_ O FF15
+3 VALW
12
R6 23 10 K_0 40 2_ 5%
R6 28 22 0K_ 04 02 _1%
1 2
Q3 4 SI2 30 1C DS-T1 -G E3 _SO T2 3- 3
S
D
13
C7 36 1 0U_0805_10V4 Z
G
2
C7 35 0 .1U_ 04 02 _1 6V 4Z
1
1
2
2
US B 20 _N1015 US B2 0_ P1 015
200 9/0 6/3 0 HP SI-2
+5 VALW
US B 20_N10
19mA
US B 20_ N1_PW R
D3 7
2
4
IO1
VIN
1
3
GND
IO2
CM1 29 3A-02SR _S OT1 43 -4
FPR : Validity
200 9/0 6/0 2 Com pal SI -2 for DFB
JP 30
2
112
4
334
5
665
7
887
ACE S_85203 -040 21
C O N N @
US B 20 _P10
200 8/1 2/1 7 Com pal ME
TrackPoint CONN. T/P CONN.
JP 24
1
+5 VS
SP _ CL K35
1
2
3
3
4
5
5
6
7
7
8
9
9
10
11
11
12
ACE S_87153 -080 11
C O N N @
2 4 6 8 10 12
WLAN/WWAN/BT LED
WL _ LED#28
WW A N_T R AN S MI T_OFF#15 ,2 8
WW _ L ED #28
BT _L ED32
SP _ DATA 35
WL _ L ED #
WW _ L E D#
1
C7 09
0. 1U _0 40 2_ 16 V4Z
2
200 9/0 4/2 4 HP SI-1
1 2
2N 7 002DWH _SOT3 63 -6
1 2
BT _ LED
WL _ L ED
200 9/0 8/3 0 HP SI-2b
R9 54 1 00 K_0402_5%
R9 55 1 00 K_0402_5%@
R1 19 1 0_0402_5%
R1 19 2 0_0402_5%
Q6 0B
5
1 2
1 2
+5 VS+5 VS +5 VS
TP _D ATA35 TP _C LK35
+3 VS
12
34
61
2
200 9/0 6/0 2 Com pal SI -2 for DFB
JP 25
887 665
4
334
2
2
112
3
ACE S_85203 -040 21
C O N N@
D3 2
@
PJ D LC 05 H_SOT 23 -3
200 9/0 2/1 8 Com pal DB-2 EMI
1
R9 5 3 47 K_0 40 2_ 5%
WL / B T_L ED#
Q6 0A 2N 7 002DWH _SOT3 63 -6
7 5
WL / B T_L ED# 31
1
C7 10
0. 1U _0 40 2_ 16 V4Z
2
+3 VS
TPM1.2 on board
C7 3 0
0. 1U _0 40 2_ 16 V4Z
C7 3 2
C7 3 1
BIOS ROM(16MB)
8MB SPI ROM
C C
0. 1U _0 40 2_ 16 V4Z
20mils
R6 33 3 .3 K_0402_5%
+3V L SP I _C S0#35 SP I _C LK3 5 SP I _SI35
SP I _CLK
12
R1 11 1
@
10 _0402_5%
1
C9 13
@
10 P_0 40 2_ 50 V8J
2
D D
200 8/1 2/1 8 Com pal EMI
SP I _HOL D# _0 SP I _HOL D# _1 SP I _ CL K_ JP SP I _CLK SP I _SI_ JP SP I _SI
1 2
R6 37 0_ 04 02 _5 %
1 2
R6 38 15 _0 40 2_ 5%
1 2
R6 39 15 _0 40 2_ 5%
1 2
R6 40 0_ 04 02 _5 %
1 2
R6 41 22 _0 40 2_ 5%
SP I _CLK SP I _ CL K_ ROM SP I _SI
SP I _CS0 #SP I_ CS0 #_ JP SP I _SOSP I _SO_ JP
1
1 2
R1 24 6 15_ 04 02 _5%
1 2
R1 24 7 15_ 04 02 _5%
1 2
R1246, R1247 near U52
200 9/0 9/1 7 HP SI-2b
+3 VL
200 9/0 4/1 0 HP DB-3
+3 VL
200 9/0 9/1 7 HP SI-2b
C7 38
1
2
20m ils
+3 VL
8 Pin SPI ROM SCKET
20mils
25mA
SP I _ WP # SP I _HOL D# _1 SP I _CS0 #
SP I _ SI _ROM
64 M MX2 5L 64 05 DZN I- 12 G WSO N 8P
200 9/0 6/0 2 Com pal SI -2 for UMA
SP I _CS0 #
@
1 2
R1 18 0 10 0K _0 40 2_ 5%
1 2
R6 3 5 3 .3 K_ 04 02 _5 %
SP I _ WP #
SPI ROM
U5 2
C O N N @
8
VCC
3
W
7
HOLD
1
S
6
C
5
D
4
VSS
SP I _SO_ R
2
Q
&U 1
45 @
W25Q64BVSSIG SOP 8P
1 2
R6 34 2 2_ 04 02 _5 %
200 9/0 2/2 0 HP DB-2
SP I _SO 35
Security Classification
1 2
R6 36 0_04 02 _5%@
2
3
1 2
C7 29 22P_0402_50V8J
2 3
32 . 76 8KHZ_ 12 .5PF_ QTF M28 -3 27 68 K1
1 2
C7 34 22P_0402_50V8J
200 8/1 2/1 2 HP
+3 VS
12
R6 27
@
4.7K_ 04 02 _5 %
12
R6 2 9
@
0_ 0402_5%
200 9/0 6/3 0 SI-2
Issued Date
Y6
1
IN
NC
4
OUT
NC
+3 VS
2008/09/15 2009/12/31
TPM_ XTA LI
12
R6 20 10 M_0 40 2_ 5%
TPM_ XTA LO
LP C _L AD012 ,2 8,35,36 LP C _L AD112 ,2 8,35,36 LP C _L AD212 ,2 8,35,36 LP C _L AD312 ,2 8,35,36 LP C _ LFRAME#1 2, 28 ,3 5, 36 PL T_RST#4,12,15 ,2 0, 26 ,2 8,31
200 9/0 8/3 0 HP PV
SI R Q12 ,3 0, 35 ,36 CL K _ PCI _T PM15
1 2
PM _ CL K RU N#14 ,3 0,35,36
1 2
200 9/0 8/3 0 HP PV
Compal Secret Data
C7 3710 P_ 04 02 _5 0V8K @
R1 23 84. 7K _0 40 2_ 5%
LP C P D# _TPM
Deciphered Date
LP C _ LAD0 LP C _ LAD1 LP C _ LAD2 LP C _ LAD3 LP C _ L FRAME# PL T _R ST# LP C P D# _TPM
SI R Q
@
1 2
R6 24 10_ 04 02 _5 %
TPM_ XTA LO TPM_ XTA LI
4
0. 1U _0 40 2_ 16 V4Z
1
1
2
2
U3 3
26
LAD0
23
LAD1
20
LAD2
17
LAD3
22
LFRAME#
16
LRESET#
28
LPCPD#
27
SERIRQ
21
LCLK
15
CLKRUN#
7
PP
14
XTALO
13
XTALI/32K IN
+3 V AL W
0. 1U _0 40 2_ 16 V4Z
1
2
10
19
24
VDD
VDD
VDD
5mA 25mA
SL B 9 635 TT
SL B 9 635 TT 1.2
SL B 9 635 TTS LB 96 35 TT
1. 2
1. 2 1. 2
TESTB1/BADD
GND
GND
GND
GND
4
11
18
25
C7 3 3
0. 1U _0 40 2_ 16 V4Z
1
2
5
VSB
R6 2 2
4.7K_ 04 02 _5 %
@
+3 VS
12
33 54T u esd ay , Dec ember 15, 2 00 9
TP M_ GP IO
6
GPIO
TP M_ GP IO 2
2
GPIO2
Base I/O Address 0 = 02Eh 1 = 04Eh*
8
TEST1
NC NC NC
SLB 9 63 5 TT 1.2 _T SSO P28
Size Do c u me nt N umb er R e v
Da t e: She et o f
1 2
9
3 12 1
Tit le
FPR/BIOS/LPC DEBUG/LED/TPM/TP
LA- 4901P
T89 T90
R6 2 5
0_ 0402_5%
1 2
R6 26
4.7K_ 04 02 _5 %
Compal Electronics, Inc.
5
1. 0
1
VA
C7 40 0 .1 U_ 06 03 _5 0V4Z
(1) PC I E xp res s x 1 channels (2) PS /2 In te rfaces (2) US B 2 .c han nels (2) SA TA Ch ann els (2) Di spl ay Po rt Channels (1) Se ria l Port (1) Pa ral le l Port (1) Li n e In (1) Li ne Out (1) RJ 45 (1 0/1 00/1000) (1) VGA
A A
(1) 2 LAN i ndi cat or LED's (1) Po wer B utton (1) I2 C i nt erface
MD O3 +27 MD O3 -27
MD O2 +27 MD O2 -27
B B
DP B_ TXP 02 2 DP B _TX N022
DP B_ TXP 12 2
Quick SW GPU
DP B _TX N122 DP B_ TXP 22 2
DP B _TX N222 DP B_ TXP 32 2
DP B _TX N322
DP B _AUX22 DP B _AUX#22
C7 41 0 .1 U_ 06 03 _5 0V4Z
1
1
2
2
V A
DE T E CT
+5 VS
DP B _AUX DP B _AUX#
200 8/1 2/1 1 nVidia 200 8/1 2/1 1 nVidia
DOCK CONN. 184PIN
VIN VA
HCB 20 12 KF- 12 1T50_0805
1 2
5A
HCB 20 12 KF- 12 1T50_0805
1 2
12A
JP 32A
190
P1
188
188
187
187
186
186
185
185
184
184
183
183
182
182
181
181
180
180
179
179
178
178
177
177
176
176
175
175
174
174
173
173
172
172
171
171
170
170
169
169
168
168
167
167
166
166
165
165
164
164
163
163
162
162
161
161
160
160
159
159
158
158
157
157
156
156
155
155
154
154
153
153
152
152
151
151
150
150
149
149
148
148
147
147
146
146
145
145
144
144
FOX _Q L0 09 4L -D26601-8H
2
DOCKING CONNECT
+5 VS
L34
L51
189
G1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
200 9/0 2/0 6 HP DB-2 200 9/0 2/0 6 HP DB-2
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
DP E _AUX
43
DP E _AUX#
44 45
+5 VS
200 9/0 1/2 2 HP DB-2 200 9/0 1/2 2 HP DB-2
C7 43
C7 42
0. 1U _0 40 2_ 16 V4Z
10 U_0805_10V4 Z
1
1
2
2
MD O1 + 27 MD O1 - 27
MD O0 + 27 MD O0 - 27
LE D _ LIN K_ LA N_ DOCK# 27 LA N _A CT# 2 6, 27
200 9/0 1/2 2 HP DB-2
US B 20 _N11 15 US B2 0_ P1 1 15
DP E_ TXP 0 21 DP E_ TXN 0 21
DP E_ TXP 1 21 DP E_ TXN 1 21
DP E_ TXP 2 21 DP E_ TXN 2 21
DP E_ TXP 3 21 DP E_ TXN 3 21
DP E _AUX 21 DP E _AUX# 21
C7 44
1
2
3
DO C K _ ID
C7 45
0. 1U _0 40 2_ 16 V4Z
0. 1U _0 40 2_ 16 V4Z
1
2
200 8/1 2/0 6 fol low UMA
200 9/0 2/0 6 HP DB-2
200 9/0 2/0 6 HP DB-2
CA D _ B22 DP _ C EC DP B _HP D22 SL P_S5#14
AD P _SI GNAL DP B _CT RL CL K DP B _CT RL DATA
DP B _AUX DP B _AUX# DP E _AUX#
LP TSTB#36 LP T AF D#36 LP T ERR #36 LP T ACK #36 LP T BU SY36 LP TP E36 LP TS LCT36 LP D736 LP D636 LP D536 LP D436 LP D336 LP D236 LP D136 LP D036 LP T SLCTIN#36 LP TI NI T#36
SA TA_L ED#1 2, 31 DO C K _I D27 IS O _ PRE P#15
SATA_ PTX_DR X_ P512 SA TA_PTX_D RX_N512
SATA_ PRX _D TX_ P512 SA TA_PR X_DTX_N512
US B 20 _N1315 US B2 0_ P1 315
SATA_ PTX_DR X_ P212 SA TA_PTX_D RX_N212
SATA_ PRX _D TX_ P212 SA TA_PR X_DTX_N212
DP _ C EC DP B _HP D
R6 46 1 K_0402_5%
AD P _SIGN AL
R1 20 7 0_0402_5%
1 2
R1 20 9 0_0402_5%
1 2
L PTS TB# LP T A FD# LP T ER R# LP T AC K# LP T BU S Y LP T PE LP T SLCT LP D 7 LP D 6 LP D 5 LP D 4 LP D 3 LP D 2 LP D 1 LP D 0 LP T SL CTIN# LP T INIT# ST B _L ED#_R
DO C K _ ID IS O _ PR EP#
4
200 9/0 2/0 6 Fol low Dior
R6 45 1 0K_0402_5%
1 2
ON / O FF # _ DO CK
R1 24 1 0_0402_5% R1 24 2 0_0402_5%@
1 2
+3 V AL W
1 2 1 2
JP 32B
143
143
142
142
141
141
140
140
139
139
138
138
137
137
136
136
135
135
134
134
133
133
132
132
131
131
130
130
129
129
128
128
127
127
126
126
125
125
124
124
123
123
122
122
121
121
120
120
119
119
118
118
117
117
116
116
115
115
114
114
113
113
112
112
111
111
110
110
109
109
108
108
107
107
106
106
105
105
104
104
103
103
102
102
101
101
100
100
99
99
98
98
97
97
96
96
95
95
192
G2
194
G4
196
G6
198
G8
200
G10
FOX _Q L0 09 4L -D26601-8H
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94
G1 G3 G5 G7 G9
ON / O F F# PW R BT N _ OUT#
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94
191 193 195 197 199
200 9/0 9/0 3 Compal
D C A D2 DP _ C E C2 DP E _HP D ON / O FF # _ DO CK VA _ O N#
1 2 1 2
D_ D D CD A TA D_ D D CC L K
R_ D O CK_ R ED R_ D O CK_ G RN
R_ D O CK_BL U DC D # 1
RI # 1 DT R #1 CT S #1 RT S #1 DS R # 1 TXD1 RX D 1 SE R _SH D
KB D _D ATA KB D _ CL K PS 2 _ DATA PS 2 _ CLK
DO C K _ HPS#
DL I N E_ OU T_L DL I N E _O UT_ R
DE T E CT
VA _ O N#
1K_ 04 02 _5 %
ON / O FF # 31 PW R BT N _O UT# 31,35
DP _ C EC 2 DP E _HP D 20
200 9/0 9/0 3 Compal
DP C _ CT R LC LK DP C _ CT R LD ATA
DP E _AUX
R1 20 80_ 04 02 _5 % R1 21 00_ 04 02 _5 %
D_ D D CD A TA 18 D_ D D CC L K 18 D _ V SYN C 18 D _ H S YN C 18
R9 47 0_0402_5%
1 2
R9 48 0_0402_5%
1 2
R9 49 0_0402_5%
1 2
DC D # 1 36 RI # 1 36 DT R #1 36 CT S# 1 36 RT S# 1 36 DS R #1 36 TXD1 36 RX D1 36 SE R _SH D 36 DO C K _I D0 15 DO C K _I D1 15
200 9/0 1/2 0 fol low Dior DIS
KB D _DA TA 35 KB D _CLK 35 PS 2 _D ATA 35 PS 2 _C LK 35 LI N E _IN _SENSE 31 DO C K _H PS# 31
DO C K _L I NE_ IN _L 31 DO C K _L I NE_I N_ R 31
DL I N E_OUT _L 31 DL I N E_ O UT_ R 31
5
R6 44
12
200 8/1 2/0 6 fol low UMA
200 9/0 6/3 0 SI-2200 9/0 6/3 0 SI-2
1
C7 39
0. 1U _0 40 2_ 16 V4Z
2
DO C K _R ED DO C K _G RN
DO C K _ BL U
Issued Date
+3 VS
+5 VALW
12
R1 14 5
13
2
G
0. 1U _0 40 2_ 16 V4Z
GR E EN_ R 18
4
10 K_0 40 2_ 5%
ST B _L ED#_R
D
Q75 2N7002H_S OT2 3- 3
S
C7 70
12
VG A _BLU18
200 9/0 2/0 6 Fol low Dior
ST B_LED#31
U3 6
VG A _ GRN18
DO C K _G RN
1
NO
2
GND
NC3COM
TS5 A3157_SC7 0- 6
2008/09/15 2009/12/31
ST B_LED#
DO C K _ ID
6
IN
5
VCC
4
Compal Secret Data
Deciphered Date
DO C K _R ED DO C K _G RN DO C K _ BL U
DO C K _R ED DO C K _G RN DO C K _ BL U
DP B _HP D DP E _HP D
1
2
DO C K _ BL U
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
R9 50 1 50 _0 40 2_ 1%
1 2
R9 51 1 50 _0 40 2_ 1%
1 2
R9 52 1 50 _0 40 2_ 1%
1 2
ADD by HP 2 008 /10/17
C7 66 0. 1U _0 40 2_ 16 V4Z@
1 2
C7 67 0. 1U _0 40 2_ 16 V4Z@
1 2
C7 68 0. 1U _0 40 2_ 16 V4Z@
1 2
R1 21 1 100 K_0402_5%
1 2
R1 21 2 100 K_0402_5%
1 2
200 9/0 6/3 0 SI-2
U3 7
NO
GND
NC3COM
TS5 A3157_SC7 0- 6
VCC
DO C K _ ID
6
IN
5
4
Compal Electronics, Inc.
DOCK CONN
LA -490 1 P
5
+3 VS+3 VS+3 VS
C7 7 1
0. 1U _0 40 2_ 16 V4Z
BL U E_R 18
34 54T u esd ay , Dec ember 15, 2 00 9
12
1. 0
0. 1U _0 40 2_ 16 V4Z
RE D _ R 18
NO<-->COM
OFF
ON
200 8/1 2/1 8 nVidia
R6 51 1 00 K_0402_5%@
1 2
R6 52 1 00 K_0402_5%@
1 2
R6 53 1 00 K_0402_5%@
1 2
R6 54 1 00 K_0402_5%@
1 2
C7 69
12
3
Security Classification
C C
2009/09/03 reserve for auto power on/off when dock
C6 94
@
0.1U_ 04 02 _1 0V 6K
IS O _ PR EP#
D D
DM N 66 D0LDW-7 _S OT3 63 -6
@
10 K_0 40 2_ 5%
1
2
@
Q9 4A
R1 24 0
2
+3 V AL W
12
61
ON / O F F#
3
@
Q9 4B DM N 66D0 LD W- 7_ SOT36 3- 6
5
4
ON / O FF # _ DO CK
200 9/0 9/0 3 Compal
U3 5
VG A _ RE D18
DO C K _R ED
1
NO
2
GND
VCC
NC3COM
TS5 A3157_SC7 0- 6
IN
IN
L
H
1
2
DO C K _ ID
6
5
4
NC<-->COM
ON
OFF
DP E _AUX# DP E _AUX DP B _AUX# DP B _AUX
1
+3 VL
200 9/0 2/2 0 Com pal DB -2 layout
RP 16
KS I 1
18
KS I 0
27
KS I 3
36
KS I 2
45
10 K_ 08 04 _8 P4R_5%
RP 18
KS I 7
1 8
KS I 6
2 7
KS I 5
3 6
A A
+5 VS
B B
C C
22 P_0 40 2_ 50 V8J
Y7
C7 81
1
2
2
KS I 4
4 5
10 K_ 08 04 _8 P4R_5%
RP 26
TP _ CL K
1 8
TP _ DA TA
2 7
KB D _ CL K
3 6
KB D _D ATA
4 5
10 K_ 08 04 _8 P4R_5%
RP 19
SP _ CLK
1 8
SP _ DATA
2 7
PS 2 _ CLK
3 6
PS 2 _ DATA
4 5
10 K_ 08 04 _8 P4R_5%
CL K _ PC I_KBC
12
R9 66 10 _0402_5%@
1
C8 49
4.7P_ 04 02 _5 0V 8C@
2
4IN1
22 P_0 40 2_ 50 V8J
C7 82
OUT
1
NC3NC
2
32 . 76 8KHZ_ 12 .5PF_ QTF M28 -3 27 68 K1
+R T CV CC
200 9/0 2/0 6 HP DB-2
SP I_ SI33 KB C _SPI_S I_ R12 SP I _C S0#33 KB C _SPI_C S0 #_ R12 SP I_ SO33 KB C _SPI _SO12
KS I 0
T143
KS I 1
T144
200 9/0 2/0 6 HP DB-2
BA T_A LARM41 KB C _SP I_ CL K_R12 SP I _C LK33 MC 2 _ DI SAB LE28 KB C _SP I_ CS1#_R12 SP I _C S1#33 MC 1 _ DI SAB LE28
PM _ SLP_L AN#1 4, 38 ,4 5 P MC40 OC P _ A_IN47
1 2
R1 03 2 0_0402_5%
1 2
R1 03 3 22_0402_5%
KS O[ 0. .1 3]31
KS I[ 0. .7 ]31
TP _C LK33 TP _D ATA33 SP _ CL K33 SP _ DATA33 PS 2_ CL K34 PS 2 _D ATA34
PM _ CL K RU N#14 ,3 0,33,36 SI R Q12 ,3 0, 33 ,36 CL K _ PC I_KB C15 RU N SCI _ EC #15
LP C _L AD312 ,2 8,33,36 LP C _L AD212 ,2 8,33,36 LP C _L AD112 ,2 8,33,36 LP C _L AD012 ,2 8,33,36
LP C _ LFRAME#1 2, 28 ,3 3, 36 NP C I_R ST#15, 36
+V C C0
1 2
R1 03 9 0_0402_5%
1 2
R1 19 5 300_0402_5%
1 2
R1 19 6 300_0402_5%
SP I _ CS 0# _EC
KB C _SPI_ SO _R
KS O 0 KS O 1 KS O 2 KS O 3 KS O 4 KS O 5 KS O 6 KS O 7 KS O 8 KS O 9 K SO1 0 K SO1 1 K SO1 2 K SO1 3
KS I 0 KS I 1 KS I 2 KS I 3 KS I 4 KS I 5 KS I 6 KS I 7
TP _ CL K TP _ DA TA SP _ CLK SP _ DATA PS 2 _ CLK PS 2 _ DATA
CL K _ PC I_KBC RU N SCI _ EC#
C R Y1 C R Y2
SP I _ CS 1# _EC
128 127
97 96 95 94
21 20 19 18 17 16 13 12 10
9 8 7 6 5
29 28 27 26 25 24 23 22
35 36 61 62 66 67
55 57 54 76
51 50 48 46
52 53
70 71
68
1 2
3 30 31 32 33 34 43 44
12
R7 2 2 0_ 0402_5%
C7 84
1U _0 60 3_ 10 V4 Z
12
R7 29
@
D D
0_ 0402_5%
C7 85
1
2
+V C C0
0. 1U _0 40 2_ 16 V4Z
1
2
2
0. 1U _0 40 2_ 16 V4Z
0. 1U _0 40 2_ 16 V4Z
C7 73
C7 74
1
1
2
2
U3 9
FLDATAOUT HSTDATAOUT/GPIO45 FLCS0# HSTCS0#/GPIO44 FLDATAIN HSTDATAIN/GPIO43
KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12/GPIO00/KBRST KSO13/GPIO18
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7
IMCLK IMDAT KCLK KDAT EMCLK EMDAT
CLKRUN# SER_IRQ PCI_CLK EC_SCI#
LAD[3] LAD[2] LAD[1] LAD[0]
LFRAME# LRESET#
XTAL1 XTAL2
VCC0 Alarm [CKT#2]/GPIO36
HSTCLK/GPIO41 FLCLK GPIO39 HSTCS1#/GPIO42 FLCS1# GPIO38 GPIO37 ADC1/GPIO46 ADC_TO_PWM_IN
200 9/0 5/0 2 HP SI-1
C9 66 2200P_ 04 02 _5 0V7K C9 68 2200P_ 04 02 _5 0V7K
+3V L
0. 1U _0 40 2_ 16 V4Z
0. 1U _0 40 2_ 16 V4Z C7 75
1
2
4. 7U _0 80 5_ 10 V4Z
C7 76
C7 77
1
1
2
2
100mA 2mA
Keyboard/Mouse Interface
Power Mgmt/SIRQ
LPC Bus
AGND
72
1 2 1 2
+3 V S_ EC
14
106
119
49
VCC1
VCC139VCC158VCC184VCC1
VCC1
VCC2
General Purpose I/O Interface
SMSC_1098-NU_TQFP-128P
Access Bus Interface
VSS11VSS37VSS47VSS56VSS
AVSS
VSS82VSS
45
104
117
AV S S
12
R1 19 7 0_ 0402_5%
3
1 2
R6 7 1 0_0402_5%
0. 1U _0 40 2_ 16 V4Z C7 78
1
2
CAP
GPIO28 GPIO29 GPIO30 GPIO31 GPIO32
OUT0/(SCI)
OUT1/IRQ8#
CFETA/OUT7/nSMI
OUT8/KBRST
OUT9/PWM2
OUT10/PWM0
PWM_CHRGCTL
GPIO01 GPIO02
GPIO03 GPIO04/KSO14 GPIO05/KSO15
GPIO07/PWM3
GPIO08/RXD
GPIO09/TXD
GPIO11/AB2A_DATA
GPIO12/AB2A_CLK
GPIO13/AB2B_DATA
GPIO14/AB2B_CLK GPIO15/FAN_TACH1 GPIO16/FAN_TACH2
GPIO17/A20M
GPIO20/PS2CLK GPIO21/PS2DAT
ADP_PRES[CKT#2]/GPIO27/WK_SE05
GPIO24/KSO16
AB1A_DATA
AB1A_CLK
AB1B_DATA
AB1B_CLK
GPIO25
GPIO26/KSO17
32KHZ_OUT/GPIO22/WK_SE01
NC_CLOCKI
RESET_OUT#/GPIO06
PWRGD
VCC1_RST#
ADC_TO_PWM_OUT/GPIO19
TEST PIN
CFETB/GPIO10
BAT_LED#
PWR_LED#/8051TX
Miscellaneous
FDD_LED#/8051RX
AC[CKT#2]/GPIO23
ADC2/GPIO40
Q/GPIO33
GPIO34 GPIO35
AVCC
KB C1 09 8- NU _VTQFP 12 8_ 14 X14
C9 67 2200P_ 04 02 _5 0V7K
1 2
+3 VS
15 93
98 99 100 126
124 125
123 122 121 120 118
107 79 80 81 83
85 86 87
88 89 90 91 92 101 102
103 105 4 74
111 112
109 110
73 108
59 75 60 78 77 38
69
116 113 115 114
41 42 65 64 63 40
200 8/0 4/1 4 EC
KB C _PW R _ON AQ U AWH I T E_BATL ED #
KB R ST # FA N _P W M
TH M _T RAV EL#
PM _ R SMR ST# CR A CK_ B GA GP I O9
AB 2 A_ DA TA AB 2 A_ CL K
PW R BT N _ OUT#
200 9/0 7/2 2 HP SI-2
AB 1 A_ DA TA AB 1 A_ CL K
AB 1 B_ DA TA AB 1 B_ CL K
EA # 32 K_CLK
PG D _ IN PW R _ GD
TEST
System Board ID Detect
KS I 3 KS I 2 KS I 1 KS I 0
C7 79 4.7U_0 80 5_ 10 V4 Z
1 2
R6 77 0_0402_5%
1 2
R1 03 4 0_0402_5%@
1 2
R1 03 5 0_0402_5%
1 2
D4 0 CH 7 51 H-40PT_SOD 32 3- 2
R6 82 0_0402_5% R6 83 0_0402_5% R6 84 0_0402_5% R6 85 0_0402_5% R1 10 1 0_0402_5%
R6 87 0_0402_5% R6 88 1K_ 04 02 _5 %@
R6 91 0_0402_5% R6 92 220_0402_5%
R1 03 6 0_0402_5% R6 98 1K_ 04 02 _5 %
R1 03 7 0_0402_5%
R7 02 100K_ 04 02 _5%
R1 19 4 300_0402_5%
R7 06 0_0402_5%
T11 8
200 9/0 1/2 2 HP DB-2
T11 9
200 9/0 2/0 6 HP DB-2
1 2 1 2 1 2 1 2 1 2
200 9/0 1/2 2 HP DB-2
1 2 1 2
1 2 1 2
1 2 1 2
1 2
1 2
1 2
1 2
21
200 9/0 1/2 2 HP DB-2
R6 69 0_0402_5%@ R6 70 0_0402_5%@
R6 72 0_0402_5%@ R6 73 0_0402_5%@
AD P _ DE T#
+3V L
200 9/0 2/1 6 HP DB-2
200 8/1 2/1 2 HP
200 8/0 4/1 4 EC
4
1 2 1 2
1 2 1 2
200 9/0 2/0 6 HP DB-2 200 9/0 8/3 0 HP PV
2N 7 00 2D WH_ SO T36 3- 6
PM _S LP_M# 14 ,3 7, 38 SU S _PW R _ACK 14 AC _ PRE SE NT 14 ,2 0 MU TE_ LED_ CNTL 31 PC I _ SE RR # 15,30 ,3 3
KB C _PW R _O N 42 AQ U AWH I TE _BATLED# 12,31 BA TSEL B_A# FE T_ A 41 KB _ RST# 15 FA N _P W M 4 BA T_P WM _O UT 40 CH G C TR L 40
TH M_T RAV EL# 39 ON / O FF B TN _K BC# 31
SL P_S3# 14,31,3 7, 38 ,4 0, 42 ,43,44,48 80 5 1 _ RECOV ER# 33
PM _ RS MRS T# 14 CR A CK_ BG A 8, 17
CA P _DAT 1 3,31 CA P _CLK 1 3, 31 CE L LS 40 A_ S D# 31 AD P _DET# 47 TH M_M AIN # 39 GA TE A20 15
KB D _CLK 34 KB D _DA TA 34 PW R BT N _O UT# 31,34 AD P _PR ES 38 ,4 0, 47
AB 1 A_ DA TA 39 AB 1 A_ CLK 39
AB 1 B_ DA TA 39 AB 1 B_ CLK 39
CA P _INT 31
AD P _EN 47 PG D _ IN PM _ PW R OK 46 P W R_ G D 12, 37 VC C 1 _P W R GD 4 2,47 O C P 47
FE T_ B 41 AM BER _B ATL ED# 31 80 51TX 33 80 51RX 33
+3V L
AC _ ADP _ PRES 40 AD P _A_ ID 47 LA T CH 41 LI D _ SW# 19, 31 CA P _RS T_ EC 31
+3V L
Q1 2A
2N 7 00 2D WH_ SO T36 3- 6
6 1
@
2
3 4
Q1 2B
@
5
@
47 K_0 40 2_ 5%
200 9/0 5/0 2 HP SI-1
to Power
200 8/1 2/1 2 HP
to Power
to Power
to Power
200 9/0 5/0 2 HP SI-1
to Power
to Power
to Power
to Power
200 8/1 2/1 2 HP
to Power
200 8/1 2/1 2 HP
200 9/0 2/1 6 HP DB-2
12
R9 90
to Power
Q8 5B
@
2N 7 002DWH _SOT3 63 -6
PG D _ IN
R1 20 4 1K_ 04 02 _5 %
200 9/0 5/1 6 HP SI-1
+3 VL
12
R1 20 0
@
10 K_0 40 2_ 5%
34
AQ U AWH I T E_BATL ED #
5
BUILD PHASE R669R670R672R673
X --> means installed
KB R ST # VC C 1 _P W R GD
CR A CK_ B GA
PG D _ IN PM _ R SMR ST# KB C _PW R _ON LA T CH FE T _A FE T _B GP I O9
200 9/0 5/1 6 HP SI-1
1 2
5
61
@
AD P _ EN
2
Q8 5A 2N 7 002DWH _SOT3 63 -6
Q12B Q 12A
FCS/MV
DB1 DB2
X X
X DBx X X SI1 SI2 SIx PV
X X X X
X PVx
200 9/0 5/0 2 HP SI-1 200 9/0 2/0 6 HP DB-2
R1 14 3 10K_0 40 2_ 5%@
1 2
R9 65 10K_0 40 2_ 5%
1 2
R6 97 100K_ 04 02 _5%
1 2
200 9/0 2/1 6 HP DB-2
R7 11 10K_0 40 2_ 5%@
1 2
200 9/0 5/0 2 HP SI-1
R7 12 100K_ 04 02 _5%
1 2
R7 01 10K_0 40 2_ 5%
1 2
R9 68 10K_0 40 2_ 5%
1 2
R9 69 10K_0 40 2_ 5%
1 2
R9 70 10K_0 40 2_ 5%
1 2
R1 14 0 10K_0 40 2_ 5%
1 2
200 9/0 2/0 6 HP DB-2
AB 1 A_ DA TA AB 1 A_ CL K AB 1 B_ CL K AB 1 B_ DA TA
RP 20
1 8 2 7 3 6 4 5
4. 7K _0 80 4_ 8P4R_ 5%
VG AT E 14 ,4 6
X
X
+3V L
+3V L
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Da t e: She et o f
Compal Electronics, Inc.
KBC1098
LA- 4901P
5
35 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
2
3
4
5
D4 3
R7 3 2
1 2
4.7K_ 04 02 _5 %
RP 22
1 8 2 7 3 6 4 5
RP 23
1 8 2 7 3 6 4 5
RP 24
1 8 2 7 3 6 4 5
RP 25
1 8 2 7 3 6 4 5
SI O _G PI O46 SI O _G PI O45 SI O _G PI O44 SI O _G PI O43
SI O _ IRQ SI O _G PI O12
SI O _G PI O10
+5 VS
21
DC D # 1
R1 07 9 4.7K_ 04 02 _5 %
1 2
R1 08 0 4.7K_ 04 02 _5 %
RI # 1
1 2
CT S #1
R1 08 1 4.7K_ 04 02 _5 %
1 2
R1 08 2 4.7K_ 04 02 _5 %
DS R # 1
1 2
RX D 1
R7 3 6 1K_ 04 02 _5 %
1 2
+3 VS
U6 5
RX D 1
RX D134 TXD134 DS R #134 RT S# 134 CT S# 134 DT R #134 RI # 134 DC D # 134
LP TI NI T#34 LP T SLCTIN#34 LP D034 LP D134 LP D234 LP D334 LP D434 LP D534 LP D634 LP D734 LP TS LCT34 LP TP E34 LP T BU SY34 LP T ACK #34 LP T ERR #34 LP T AF D#34 LP TSTB#34
200 9/0 6/3 0 SI-2
+3 VS
C7 90 0 .1U_ 04 02 _1 6V 4Z
+3 VS
C7 87 0 .1U_ 04 02 _1 6V 4Z
C7 86 0 .1U_ 04 02 _1 6V 4Z
1
1
1
2
2
2
TXD1 DS R # 1 RT S #1 CT S #1 DT R #1 RI # 1
DC D # 1
LP T INIT# LP T SL CTIN# LP D 0 LP D 1 LP D 2LP D2 LP D 3 LP D 4LP D4 LP D 5 LP D 6LP D6 LP D 7 LP T SLCT LP T PE LP T BU S Y LP T AC K# LP T ER R# LP T A FD# L PTS TB#
C7 89 4 .7U_ 08 05 _1 0V 4Z
1
2
54
RXD1
55
TXD1
56
DSR1#
1
RTS1#
2
CTS1#
3
DTR1#
4
RI1#
5
35 36 37 39 40 41 42 43 44 45 47 48 49 50 51 52 53
7 10 23 38 46
SERIAL I/FPARALLEL I/F
DCD1#
INIT# SLCTIN# PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 SLCT PE BUSY ACK# ERROR# ALF# STROBE#
VTR VCC VCC VCC VCC
LP C 4 7N2 17 N- ABZ J_QFN 56 _8 X8
CLOCK
GPIO11/SYSOPT
POWER
LFRAME#
LDRQ#
PCI_RESET#
LPCPD#
LPC I/F
CLKRUN#
PCI_CLK SER_IRQ IO_PME#
CLK14
GPIO41 GPIO42 GPIO43 GPIO44 GPIO45
GPIO
GPIO46 GPIO47 GPIO10
GPIO12/IO_SMI#
GPIO13/IRQIN1 GPIO14/IRQIN2
GPIO23
EPAD
LAD0 LAD1 LAD2 LAD3
9 11 12 13
14 15
16 17
18 19 20 6
8
21 22 24 25 26 27 28 29 30 31 32 33 34
57
LP C _ AD0 LP C _ AD1 LP C _ AD2 LP C _ AD3
LP C _ F RAM E# LP C _ DR Q# 0
NP C I_ RST # LP C P D# _S IO
PM _ CL K R UN# CL K _ PC I_ SIO
SI R Q
SI O _P ME#
R7 35 10 K_0 40 2_ 5%
CL K_14M_SIO
SI O _G PI O41 SI O _G PI O42 SI O _G PI O43 SI O _G PI O44 SI O _G PI O45 SI O _G PI O46
SI O _G PI O10 SY S O PT SI O _G PI O12 SI O _ IRQ
SI O _G PI O23
200 9/0 8/3 0 HP PV
1 2
R1 18 9 0_0 40 2_ 5%
12
R1 19 0 10 K_0 40 2_ 5%
@
1 2
200 9/0 4/2 4 SI-1
LP C _L AD0 12 ,2 8,33,35 LP C _L AD1 12 ,2 8,33,35 LP C _L AD2 12 ,2 8,33,35 LP C _L AD3 12 ,2 8,33,35
LP C _ LFRAME# 1 2,28,33,35 LP C _ LD RQ#0 12
NP C I_R ST# 1 5,35
PM _ CL K RU N# 1 4, 30 ,3 3,35 CL K _ PC I_ SIO 15 SI R Q 12 ,3 0,33,35
+3 VS
CL K_14M_ SIO 13
SE R _SH DSE R _SH D _G PIO 47
SE R _SH D 34
200 8/1 2/1 2 HP
LP C P D# _S IO
R1 23 9 4.7 K_0402_5%
1 2
200 9/0 8/3 0 HP PV
+3 VS
Parallel Port
TO LPC47N217N
CH 7 51 H-40PT_SOD 32 3- 2
A A
B B
+5 V S_PR N
LP T ER R#
LP T AC K# LP T BU S Y LP T PE LP T SLCT
LP D 3 LP D 2 LP D 1 LP D 0
LP D 7 LP D 6 LP D 5 LP D 4
LP T INIT# L PTS TB# LP T A FD# LP T SL CTIN#
RP 57
RP 58
4.7K_ 08 04 _8 P4 R_5%
4.7K_ 08 04 _8 P4 R_5%
4.7K_ 08 04 _8 P4 R_5%
4.7K_ 08 04 _8 P4 R_5%
18 27 36 45
10 K_ 08 04 _8 P4R_5%
18 27 36 45
10 K_ 08 04 _8 P4R_5%
+3 VS
R1 13 0 10K_0 40 2_ 5%
1 2
R1 13 1 10K_0 40 2_ 5%
C C
D D
1 2
R1 13 2 10K_0 40 2_ 5%
1 2
R1 17 4 10K_0 40 2_ 5%
1 2
Base I/O Address
0 = 02Eh 1 = 04Eh
CL K_14M_SIOC LK_ P CI_SI O
12
R7 4 2 10 _0402_5%
1
C7 9 1 18 P_0 40 2_ 50 V8 J
2
12
R7 4 3
@
10 _0402_5%
1
C7 9 2
@
10 P_0 40 2_ 25 V8K
2
1
SI O _G PI O23 SI O _G PI O41 SI O _G PI O42 SY S O PT
200 9/0 3/2 3 Com pal DB-3
@
@
Security Classification
Issued Date
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/09 2009/09/09
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Da t e: She et o f
Compal Electronics, Inc.
SUPER I/O LPC47N217N-ABZJ
LA -490 1 P
5
36 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
1 2
1 2
1 2
CH 7 51 H-40PT_SOD 32 3- 2
CH 7 51 H-40PT_SOD 32 3- 2
1 2
1 2
1 2
56 .2K_0 40 2_ 1%
200 8/1 2/1 2 HP
D4 4
D4 5
12
R7 6 3
21
21
R7 49 10 K_0 40 2_ 5%
2V R EF_ 51 12 5
R7 5 2 49 .9K_0 40 2_ 1%
1
C7 94 33 00P_0 40 2_ 25 V7K
2
R7 5 9 10 K_0 40 2_ 5%
1
C7 95 33 00P_0 40 2_ 25 V7K
2
+5 VS
R7 4 7 3.3K_ 04 02 _5 %
R7 4 8 76 .8K_0 40 2_ 1%
R7 5 1 11 .5K_0 40 2_ 1%
1 2
R7 5 3 3.3K_ 04 02 _5 %
1 2
R7 5 4 3.3K_ 04 02 _5 %
200 9/0 2/2 5 HP DB-2
R7 5 8 3.3K_ 04 02 _5 %
R7 6 1 49 .9K_0 40 2_ 1%
R7 6 2 16 .2K_0 40 2_ 1%
200 8/1 2/1 2 HP
1. 5V _POK45
A A
B B
+0 .7 5VS
M_ P WR OK14
SL P_S3#14 ,3 1, 35 ,38,40,42 ,4 3, 44,4 8
NV V DD _ PO K48
+3 VS
+1 .0 5VS
2
1 2
2V R EF_3 93
1 2
R7 50 34.8 K_0402_ 1%
1 2
1 2
R7 44 1M_ 04 02 _5 %
1 2
3 2
1
C7 93 10 00P_0 40 2_ 50 V7K
2
1 2
1M_ 04 02 _5 %
2V R EF_3 93
5 6
+5 V AL W
+
-
R7 56
+
-
8
P
G
4
+5 V AL W
1
O
U4 1 A LM 393DR_ SO 8
8
P
7
O
G
U4 1 B LM 393DR_ SO 8
4
+3 VS
J2
1 2
SH O R T PA DS
VC C P_ P OK43
MC 7 4 VH C1 G08DFT2G_S C7 0- 5
3
12
R7 4 6 10 K_0 40 2_ 5%
+3 VALW
1
IN1
2
IN2
U4 2
200 9/0 9/1 5 Com pal ESD PV
5
VCC
OUT
GND
3
@
0.1U_ 04 02 _2 5V 4K
200 8/1 2/1 2 HP
4
C9 99
1
2
12
R7 5 5
4.99K_0 40 2_ 1%
12
R7 6 0
2.49K_0 40 2_ 1%
VC C P_ E N 43
PW R _ GD 1 2,35
VT TP W R GOOD 4
S LP_ S3 #
4
+3 V AL W
5
1
IN1
2
IN2
3
200 9/0 7/0 2 HP SI-1b
VCC
4
OUT
U6 7
GND
MC 7 4 VH C1 G08DFT2G_S C7 0- 5
5
VC C P_ 1 . 5 VS PWR GD 4
R1 04 0 3.3K_ 04 02 _1 %
1. 8 VS_ PO K44
+1 .5 VS
C C
D D
1
1 2
R1 04 2 10.7K_0 40 2_ 1%
1 2
200 9/0 2/2 5 HP DB-2 200 9/0 7/2 1 HP SI-2
R1 04 4 16 5K_ 04 02 _1 %
200 8/1 2/1 2 HP
1. 0 5VM_ LAN _P OK45
PM _S LP_M#1 4,35,38
+3 VM +1. 05 VM
200 9/0 2/0 6 HP DB-2
R1 04 3 10K_0 40 2_ 5%
12
1
C8 97 33 00P_0 40 2_ 25 V7K
2
2V R EF_ 51 12 5
R9 4 1 3.3K_ 04 02 _5 %
2V R EF_ 51 12 5
R9 3 7 3.3K_ 04 02 _5 % R9 3 9 46 .4K_0 40 2_ 1% R9 4 0 14 .7K_0 40 2_ 1%
1 2
1 2
R9 8 6 41 .2K_0 40 2_ 1%
2V R E F_ 39 3_ R
200 9/0 7/2 1 HP SI-2
1 2
71 .5K_0 40 2_ 1%
1 2 1 2 1 2
D6 6
1 2
1N 4 1 48 WS FL_ SO D323-2
R9 42
86 .6K_0 40 2_ 1%
2
R1 04 1
1 2
1M_ 04 02 _5 %
+5 V AL W
8
3
P
+
2
-
G
U 3 A
LM 3 93 DR _SO8
R9 87
4
12
1
C8 63 10 00P_0 40 2_ 25 V8J
2
R9 38 10K_0 40 2_ 5%
1 2
2 1
CH 7 51 H-40PT_SOD 32 3- 2
12
12
C8 3 9 33 00P_0 40 2_ 50 V7K
1
O
+3 VALW
R9 35 1M_ 04 02 _5 %
1 2
+5 V AL W
8
U3 B
5
P
+
7
2V R E F_ 39 3_ R
D6 7
R9 89 1 M_0402_5%
C8 64 0.068U_0 40 2_ 10 V6K
O
6
-
G
LM 393DR_ SO 8
4
1 2
1 2
200 9/0 7/0 9 HP SI-1b
3
12
R9 36
3.3K_ 04 02 _5%
12
R9 88 1K_ 04 02 _5 %
Security Classification
Issued Date
M_ P WR O K 14
2008/09/15 2009/12/31
MDC STANDOFF Mini PCIE STANDOFF
H1 3 HO L EA
1
H8
H 9
HO L EA
HO L EA
1
H1 7 HO L EA
1
FM 1
1
1
Compal Secret Data
Deciphered Date
4
1
H1 8 HO L EA
1
FM 2
H1 5 HO L EA
1
H1 1
H1 0
HO L EA
HO L EA
1
H1 9 HO L EA
1
F M3
1
1
1
H2 0 HO L EA
1
FM 4
H 1 HO L EA
H2 5 HO L EA
1
H2 1
H2 2
HO L EA
1
H2 3
HO L EA
HO L EA
1
1
H 2
H 3
HO L EA
HO L EA
1
1
Tit le
Size Do c u me nt N umb er R e v
Da t e: She et
1
H2 4 HO L EA
H4 HO L EA
1
LA- 4901P
1
H 5 HO L EA
1
SATA STANDOFF
H7 HO L EA
1
H2 6 HO L EA
1
ZZ Z1
PCB-MB
Compal Electronics, Inc.
POK CKT
5
37 54T u esd ay , Dec ember 15, 2 00 9
1. 0
o f
A
B
C
D
E
+1.05VM to +1.05VS Transfer
4
R1 17 8
1 2 3
+1 .0 5VS+1 .05VM_LAN
6A
200 9/0 5/0 7 HP SI-1
C8 04
10 U_ 08 05 _1 0V 4Z
1
2
C9 78
33 0 U_ B2_2VM_R15 M
1
+
2
Q57 AO4 43 0L _S O8
8 7 6
10 U_ 08 05 _1 0V 4Z
C8 02
5
0. 1U _0 40 2_ 16 V4Z
1
2
R U NO N
200 9/0 4/1 3 Com pal DB-3
1 2
0_ 0402_5%
C8 01
1 1
1
2
+3VALW to +3VM Transfer
@
PM _ SLP_L AN#1 4, 35 ,45
+3 V AL W +3 VM
C8 0 0
0. 1U _0 40 2_ 16 V4Z
12
2
G
R7 7 3 47 K_0 40 2_ 5%
1 2
4.7K_ 04 02 _5 %
13
D
Q4 3 2N7002H_S OT2 3- 3
S
R7 7 4
1
2
Q4 0
SI2 30 1C DS-T1 -G E3_SO T23- 3
S
D
13
G
2
LA N _ EN#
1.5A
0. 1U _0 40 2_ 16 V4Z
C7 9 8
1
1
C7 9 9 10 U_ 08 05 _1 0V 4Z
2
2
Discharge circuit-2 for V-M
+1 .0 5VM
12
R7 7 1 47 0_0402_5%
61
Q4 1A
2N 7 00 2D WH_ SO T36 3- 6
200 8/1 2/1 2 fol low UMA
2
LA N _ EN#P M _SLP _M
+3 VM
12
34
5
R7 72 47 0_0402_5%
Q4 1B 2N 7 002DWH _SOT3 63 -6
200 9/0 4/1 3 Com pal DB-3
+3VALW to +3VS Transfer
+5 VS+5 V ALW
C8 09
4.5A
0. 1U _0 40 2_ 16 V4Z
1
2
R U N O N 7
1 2 3
+3 VS+3 V ALW
6.5A
0. 1U _0 40 2_ 16 V4Z
C8 06
1
2
12
R7 78 47 0_0402_5%
1
C8 08
0.01U_0 40 2_ 16 V7 K
2
1
C8 10 10 U_ 08 05 _1 0V 4Z
2
10 U_0603_6.3V 6M
C8 07
1
2
10/17 HP correct it
+1.05VM_LAN to +1.05VM Transfer
U5 5
SI7 32 6D N- T1- GE 3_ PAK 12 12 -8-5
5
C8 13
0. 1U _0 40 2_ 16 V4Z
C8 12
10 U_ 08 05 _1 0V 4Z
1
1
2
2
R9 43
1 2
B+
33 0K_ 04 02 _5%
AD P _PRES
5
+1. 05 VM+ 1 .0 5V M_L AN
1 2 3
4
Q5 8A 2N 7 002DWH _SOT3 63 -6
6 1
2
12
R1 04 7 82 0K_ 04 02 _5%
34
Q5 8B 2N 7 002DWH _SOT3 63 -6
2.5A
C8 15
10 U_0805_10V4 Z
1
2
PM _ SLP_M
C9 79
33 0U _B 2_ 2VM_R 15 M
1
+
2
@
200 9/0 5/0 7 HP SI-1
+1.5V to +1.5VS Transfer
Q62 AO4 43 0L _S O8
8 7 6
10 U_0805_10V6 K
C8 44
0.1U_ 04 02 _1 0V 6K
1
2
R1 01 3
10 0K_ 04 02 _5 %
5
12
R U NO N
2
G
4
12
R9 57 10 0K_ 04 02 _5%
13
D
S
Q47
SS M3K7 00 2FU_SC7 0- 3
C8 43
1
2
PM _S LP_M#1 4,35,37
+1.5V to +VDD_MEM Transfer
C9 36
1
2
S LP_ S3S LP_ S4PM_SL P_ M
0.1U_ 04 02 _1 0V 6K
2
G
12
Q7 7 AO4 43 0L _S O8
8 7 6 5
+3 VL+3 VL+3V L
12
R7 80 10 0K_ 04 02 _5%
13
D
S
Q49
SS M3K 70 02 FU_ SC70-3
+1 .5 VS+1. 5V
12
C9 35
12
34
5
SL P_S37
SL P_S3#14 ,3 1, 35 ,37,40,42 ,4 3, 44,4 8SL P_S4#14 ,4 5
10 0K_ 04 02 _5%
10 U_0805_10V6 K
1
2
R1 15 6 82 0K_ 04 02 _5 %
Q9 5B 2N 7 002DWH _SOT3 63 -6
R1 01 5
1
1.5A
2 3
C8 46
10 U_0805_10V6 K
C8 45
0.1U_ 04 02 _1 0V 6K
1
1
2
2
12
R7 79 10 0K_ 04 02 _5 %
SL P_ S432
R1 01 4
10 0K_ 04 02 _5%
2
G
12
13
D
S
Q4 8
SS M3K7 00 2FU_SC7 0- 3
R1 24 3 33 0K_ 04 02 _5 %
S LP_ S3
2N 7 00 2D WH_ SO T36 3- 6
2
Q9 5A
AD P _PRES
61
1 2 3
4
12
200 9/0 2/1 8 Com pal DB-2 200 9/0 9/0 8 Com pal PV
R1 17 0 10 K_0 40 2_ 5%
1
C9 3 9
0. 22 U_ 04 02 _1 0V4Z
2
+V D D_MEM+1 .5 VB+
3A
C9 37
0.1U_ 04 02 _1 0V 6K
C9 38
10 U_0805_10V6 K
1
1
2
2
B +
R7 76 33 0K_ 04 02 _5%
SH O R T P ADS
2 2
S LP_ S3
2
Q4 5A
2N 7 00 2D WH_ SO T36 3- 6
AD P _PR ES3 5, 40 ,47
SI7 32 6D N- T1- GE 3_ PAK 12 12 -8 -5
12
1
5
C8 05 10 U_0603_6.3V 6M
2
12
J 3
61
5
U4 5
4
R U NO N
12
R7 77 82 0K_ 04 02 _5%
34
Q4 5B 2N 7 002DWH _SOT3 63 -6
+5VALW to +5VS Transfer
U4 6
SI7 32 6D N- T1- GE 3_ PAK 12 12 -8 -5
5
1
C8 11 10 U_ 08 05 _1 0V 4Z
3 3
2
4
R U NO N
1 2 3
Discharge circuit-1
+1 .0 5VS
12
R7 81 47 0_0402_5%
13
D
2
G
A
Q5 0 2N7002H_S OT2 3- 3
S
S LP_ S3
4 4
S LP_ S3
2
G
+3 VS
12
R7 82 22 0_0402_5%
13
D
Q5 1 2N7002H_S OT2 3- 3
S
S LP_ S3
B
+1 .5VS
12
61
2
R7 83 47 0_0402_5%
Q5 2A 2N 7 002DWH _SOT3 63 -6
S LP_ S4
12
34
5
R7 86 47 0_0402_5%
Q5 2B 2N 7 002DWH _SOT3 63 -6
S LP_ S3S LP_ S3
2
G
Compal Secret Data
+1 .8VS+1. 5V
12
R7 85 47 0_0402_5%
13
D
Q5 4
SS M3K7 00 2FU_SC7 0- 3
S
Deciphered Date
D
+5 VS
12
R7 84 47 0_0402_5%
13
D
Q5 3
2
G
2N 70 02 H_ SOT23 -3
S
Security Classification
Issued Date
C
2008/09/15 2009/12/31
S LP_ S3
+0 .7 5VS
12
13
D
2
G
S
R7 8 7 10 _0402_5%
200 9/0 6/3 0 SI-2
Q56
SS M3K 70 02 FU_ SC70-3
Tit le
Size Do c u me nt N umb er R e v
Da t e: She et o f
Compal Electronics, Inc.
DC/DC Circuits
LA- 4901P
E
38 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
2
3
4
ADP_SIGNAL
PJP1
3
GND1
4
GND2
6
A A
PJP2
@SUYIN_200046GR008G102ZR_8P-T
B B
THM_MAIN#35
OCP_ADJ47
C C
PCN1
SUYIN_20163S-06G1-K
THM_TRAVEL#35
D D
GND_1
7
GND_2
8
GND_3
9
GND_4
FOX_JPD113E-LB103-7F
@
1
1
2
2
3
3
4
4
5
5 6 7 8
SSM3K7002FU_SC70-3
210K_0402_1%
PR2 1M_0402_1%
6 7 8
PR4
100K_0402_5%
PQ30
1
BATT+
2
SMD
3
SMC
4
B/I
5
TS
6
GND
+3VL
PR9
BAV99WT1G_SC70-3
SINGAL
PWR1
PWR2
12
MMBT3906_SOT23-3
13
D
G
S
294K_0402_1%
1 2
PR11
1K_0402_5%
1 2
PD18
5
1
2
12
PQ29
2
PR91
220K_0402_5%
PR92
1 2
PC27
1
2
3
1
VL+3VL
3
C
1 12
12
100P_0402_50V8J
ADPIN
2
3
PD1
1
@PJSOT24C_SOT23
69.8K_0402_1%
1 2
12
PR89
100K_0402_1%
E
B
2
12
PR90
150K_0402_1%
2
3
PD2
1
PJSOT24C_SOT23
PR88
VIN
12
12
1000P_0402_50V7K
PL2
SMB3025500YA_2P
1 2
AB1A_DATA 35
AB1A_CLK 35
+3VL
PR1 @15K_0402_5%
BATT_A
12
PC6
0.01U_0402_50V4Z
PH1 under CPU botten side :
12
PC1
100P_0402_50V8J
12
PC7
PR3
1K_0402_5%
100P_0402_50V8J
PD15 BAV99WT1G_SC70-3
1
2
3
SMB3025500YA_2P
12
PC2 1000P_0402_50V7K
12
12
PR5
100_0402_5%
PD16
1
BAV99WT1G_SC70-3
VL
2
PL1
1 2
100P_0402_50V8J
12
PC8
100P_0402_50V8J
3
PC3
12
PR6
100_0402_5%
PD17
1
BAV99WT1G_SC70-3
2
3
12
PC4
VMB_A
12
PC5 1000P_0402_50V7K
12
PC9 100P_0402_50V8J
CPU thermal protection at 90 +-3 degree C (Need to be checked)
VMB_B
SMB3025500YA_2P
PR7
1K_0402_5%
1 2
12
2
PD3
1
3
PR14
100_0402_5%
PD19
1
BAV99WT1G_SC70-3
PJSOT24C_SOT23
2
3
PC28
100P_0402_50V8J
12
12
PR15
100_0402_5%
1
PD20 BAV99WT1G_SC70-3
2
3
1 2
12
PC11 1000P_0402_50V7K
12
PC29 100P_0402_50V8J
AB1B_DATA 35 AB1B_CLK 35
+3VL
2
BATT_B
PL3
12
PC10
0.01U_0402_50V4Z
0.1
Security Classification
Close to CPU
PC12
0.1U_0603_25V7K
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2VREF_51125
12
PH1 100K_0603_1%_T SM1A104F4361RZ
PR12
53.6K_0603_1%
1 2
2VREF_51125
Deciphered Date
3
1 2
PR13
75K_0402_1%
150K_0402_1%
PR17
12
5 6
12
PC13
1000P_0402_50V7K
12
2008/09/15 2009/09/15
12
PR16
19.1K_0402_1%
Compal Secret Data
PR8
470K_0402_1%
1 2
8
P
+
O
-
G
PU15B
4
LM393DG_SO8
VL
PR10 100K_0402_5%
7
1 2
13
D
PQ1
2
G
SSM3K7002FU_SC70-3
S
Title
Size Document Number R ev
Cu stom
Date: Sheet o f
Compal Electronics, Inc.
DC-IN/ BATTERY CONN
LA-4902P
4
EN0 42
39 54Tuesday, December 15, 2009
A
VI N
PQ101 AO4407L_SO8
1 2 3 6
1 1
2 2
0.1U_0603_25V7K
1 2
200K_0402_5%
ADP_EN#
1 2
100K_0402_1%
P2
1 2
PC101
PR101
P2BATT
PR136
12
PR119 200K_0402_1%
12
PR123
41.2K_0402_1%
3 3
4
12
PR111 150K_0402_5%
PR135
100K_0402_1%
1 2
PR137
24.3K_0603_1%
1 2
1 2
255K_0402_1%
5
+
6
-
2VREF_51125
8 7
5
PR118
8
P
G
PU103B LMV393DR2G_SO8
4
PQ102 AO4407A_SO8
8 7
5
4
12
PR105 15K_0402_5%
13
D
S
VL
PR138
1 2
100K_0402_5%
PR139
1 2
1M_0402_5%
8
3
P
+
1
O
2
-
G
PU10A LMV393DR2G_SO8
4
12
PR140
23.7K_0402_1%
BAT_PWM_OUT35
+3VL
12
PR120
22K_0402_5%
7
O
P4
1 2 36
1 2
PR103
47K_0402_5%
2
G
PQ104 SSM3K7002FU_SC70-3
422K_0402_1%
1U_0603_6.3V6M
AC Detector High 11.85 Low 10.55
ADP_PRES 35,38,47
1 2
PR114
PC116
+3VL
56K_0402_1%
PR104
1 2
SLP_S3#14,31,35,37,38,42,43,44,48
12
1 2
PC111 1U_0603_6.3V6M
12
PR113 453K_0402_1%
12
PR115 1M_0402_1%
43.2K_0402_1%
IADAPT47
Charge Detector
1 2
PR125
604K_0402_1%
3
+
2
-
VL
12
PC124
0.1U_0402_10V7K
8
P
1
O
G
PU103A LMV393DR2G_SO8
4
VIN
12
PR128
76.8K_0402_1%
P2
12
PR127 @76.8K_0402_1%
12
PR131
4 4
10K_0603_0.1%
High 17.588 Low 17.292
AC_ADP_PRES
+3VL
PR151 22K_0402_5%
1 2
B
12
PC107
0.01U_0402_16V7K
PR109
0_0402_5%
1 2
BQ24740VREF
+3VL
8
9
10
11
12
13
14
12
PR116
IADAPT
PC119
100P_0402_50V8J
1K_0402_5%
CHGCT RL
1 2
AC_ADP_PRES 35
ACDET
+3VL
6
7
LPREF
ACSET
IADSLP
AGND
VREF
PU101 BQ24740RHDR_QFN28_5X5
VDAC
VADJ
EXTPWR
ISYNSET
IADAPT
SRSET
15
16
12
12
PR124 147K_0402_1%
PR130
PD103 1SS355_SOD323-2
0.047U_0402_16V7K
Note: X7R type
5
17
BATT
PC123
PC108
ACDET
BAT
12
PR102
0.01_2512_1%
1 2
ACP
PC105
1U_0603_6.3V6M
1 2
12
0.1U_0603_50V7K
3
4
ACP
LPMD
SRP
SRN
19
18
12
PC122 1U_0603_6.3V6M
12
4 3
ACN
12
PC106 @0.1U_0603_25V7K
2
ACN
CELLS
20
12
PR122
210K_0402_1%
+3VL
2
G
12
PR134
470K_0402_5%
B+
PL103
1.2UH_1127AS-1R2N_2.4A_30%
1 2
PL101
@HCB2012KF-121T50_0805
1 2
CH GEN#
1
29
TP
CHGEN
28
PVCC
BTST
HIDRV
PH
REGN
LODRV
PGND
27
26
25
24
23
22
PC109 1U_0805_25V6K
BST_CHG
DH_CHG
LX_CHG
RE GNVADJ
DL _CHG
DPMDET
21
SRSET 47
CHGCTRL 35
12
PR126
100K_0402_5%
12
PR133 220K_0402_5%
CH GEN#
13
D
S
B
2
PQ109 BSS138_SOT23-3
C
12
PC102
4.7U_0805_25V6M
1 2
1 2
PR121
0_0402_5%
1 2
PR145
0_0402_5%
PD102
LLS4148_LL34-2
PC118
12
1U_0603_10V6K
+3VL
E
3
PQ108
MMBT3906_SOT23-3
C
1
1 2
PR129
47K_0402_5%
12
12
PC103
4.7U_0805_25V6M
PR110 10_0805_5%
1 2
PC110
0.1U_0402_10V7K
1 2
12
AO4468L_SO8
PR117 100K_0402_5%
1 2
PC120
0.1U_0603_50V7K
ACDETACDET
12
PR132 300K_0402_5%
PC104
4.7U_0805_25V6M
PQ107
CELLS 35
12
CHG_B+
1
+
PC132 47U_25V_M
2
CHG_B+
5
D8D7D6D
PQ106
S1S2S3G
AO4466_SO8
4
578
3 6
241
12
PC121 @0.1U_0603_25V7K
IADAPT
P4P2
PQ103
AO4407A_SO8
1 2 3 6
4
PR106 0_0402_5%
1 2
PL102
10U_LF919AS-100M-P3_4.5A_20%
1 2
PR141
4.7_1206_5%
1 2 12
PC126
680P_0603_50V8J
PR142
11K_0402_5%
1 2
1U_0603_10V6K
PC127
12
PR144
49.9K_0402_1%
D
8 7
5
P2
0.01_1206_1%
1 2
12
12
PC112
PC113
4.7U_0805_25V6M
4.7U_0805_25V6M
PC117
0.1U_0402_10V7K
1
+IN
OUTPUT
1 2
PR143
39.2K_0402_1%
V+
2
V-
3
-IN
PU104
LMV321M5X-NOPB _SO T23 -5
12
PR112
1 2
5
4
+5VALW
BATT
12
PC128 4.7U_0805_25V6M
PMC 35
12
12
PC114 4.7U_0805_25V6M
PC115 4.7U_0805_25V6M
2VREF_51125
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
2008/09/15 2009/09/15
Compal Secret Data
Deciphered Date
C
Title
Size Document Number R ev
Date: Sheet o f
Compal Electronics, Inc.
Charger
LA-4902P
D
40 54Tuesday, December 15, 2009
0.1
A
1 2
PR1100
5
+
6
-
1M_0402_5%
VL
8
P
O
G
PU10B LMV 393DR2G_SO8
4
12
PC1100
0.1U_0603 _50V4Z
7
+3VL
12
PR1104 100 K_0402_5%
BAT_ALARM 35
2VREF_51 125
BATT
12
1 1
12
PR1105
93.1K_ 0603_1%
PR1109 20K _0402_1%
12
PR1103
10K _0402_5%
B
BATT_B
BATT_A
C
Vin
PD1102
1SS35 5_SOD323-2
PD1100 RB715F _S OT323-3
2 3
B+_DEBUG
D
12
PR1101
0_0 402_5%
1 2
PD1103
GLZ27D_LL 34-2
B++ 51125_PWR
12
PD1101
1SS35 5_SOD323-2
12
PR1106
100 _0805_5%
1
1 2
12
PC1102
0.1U_0603 _50V4Z
12
PR1110
8.06K_ 0402_1%
13
D
CFET_B
2
G
PQ1100
S
SSM3K7002FU_SC70-3
CFET_B
PQ1102
LA TCH35
S
G
2
PR1112
0_0 402_5%
D
1 2
13
BSS84 LT1G_SOT23-3
BATT_IN
BATT
2 2
12
PR1114 470 K_0402_5%
1
2
CFET_A47
PR1119
10K _0402_5%
1 2
BATT_IN
10K _0402_5%
CFET_A
34
PQ1106B 2N7002 KDW -2N_SOT363-6
5
12
PR1117
61
2
PQ1106A
2N7002 KDW -2N_SOT363-6
1 2
PD1106 1SS35 5_SOD323-2
PQ1105 PMB T2222A_SOT23-3
3
BATT
3 3
4 4
FET_A 35
FET_B 35
1 2
PR1127
10K _0402_5%
CFET_B
BATT_IN
CFET_B
2
10K _0402_5%
61
12
PR1122 470 K_0402_5%
12
PR1126
5
PQ1112A 2N7002 KDW -2N_SOT363-6
1 2
PD1109 1SS35 5_SOD323-2
34
PQ1112B 2N7002 KDW -2N_SOT363-6
1
2
3
PQ1111
PR1115 470 K_0402_5%
1 2
3 6 2 1
PQ1107 AO4407A_SO8
PQ1109
AO4407A_SO8
1 2 3 6
470 K_0402_5%
1 2
PR1124
PMB T2222A_SOT23-3
PD1107 SX34-40_SMA
21
4
4
21
PD1108 SX34-40_SMA
BATT_IN
BATT_A_P
5 7
8
8 7
5
BATT_IN
5
2
5 7
8
PQ1108 AO4407A_SO8
PQ1110
AO4407A_SO8
8 7
5
BATT_B_P
5
2
34
PQ1113B 2N7002 KDW -2N_SOT363-6
PQ1113A
61
2N7002 KDW -2N_SOT363-6
4
36 2 1
1 2 36
4
34
PQ1114B 2N7002 KDW -2N_SOT363-6
61
PQ1114A 2N7002 KDW -2N_SOT363-6
12
PR1118
4.7K_0 402_5%
12
PR1120 470 K_0402_5%
12
PR1121 470 K_0402_5%
12
PR1125
4.7K_0 402_5%
BATT_A
BATT_B
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
2008/09/15 2009/09/15
Compal Secret Data
Deciphered Date
C
Title
Size Do cument Number Rev
Cu stom
Da te: Sheet o f
Compal Electronics, Inc.
Battery selector
LA-49 02P
D
41 54Tue sday, Decemb er 15, 2009
A
B
C
D
E
2VREF_51125
12
PC302
1U_0603_16V7
1 1
PR301
13.7K_0402_1%
+3VALWP
B+
PL301
HCB2012KF-121T50_0805
1 2
1
+
PC316 @100U_25V_M
2
1000P_0402_50V7K
2 2
PC301
+3VALWP
150U_B_6.3VM_R45M
3 3
2N7002KDW-2N_SOT363-6
4 4
PC310
ENTRIP1
61
PQ305A
SSM3K7002FU_SC70-3
B++
12
12
12
PC303
0.1U_0402_25V6
PC317
4.7UH_SIQB74B-4R7PF_4A_20%
1
+
PL302
12
PR311
4.7_1206_5%
4.7U_0805_25V6-K
2
1000P_0603_50V8J
2
PQ307
PC312
5
100K_0402_5%
1 2
13
D
2
G
S
241
12
12
123
ENTRIP2
34
PQ305B 2N7002KDW-2N_SOT363-6
PR316
PR317
330K_0402_5%
12
12
PD305 1SS355_SOD323-2
12
PD301 1SS355_SOD323-2
SIS412DN
PQ301
UG1_3V
3 5
5
PQ304
4
AON7406L_DFN8-5
VL
PR318 100K_0402_5%
1 2
12
PC307
2.2U_0805_10V6K
PR309
0_0402_5%
1 2
1 2
PC308
0.1U_0402_10V7K
SLP_S3#14,31,35,37,38,40,43,44,48
+5VALWP
+3VALWP
KBC_PWR_ON 35
DEBUG_KBCRST 33
VCC1_PWRGD 35,47
+3VLP
PR307
1 2
2.2_0402_5%
PD302
@1SS355_SOD323-2
PJP301
1 2
PAD-OPEN 4x4m PJP303
1 2
PAD-OPEN 4x4m
1 2
PR303
20K_0402_1%
1 2
PR305
107K_0402_1%
1 2
BST_3V UG_3V UG_5V LX_3V
LG_3V
ENTRIP2
3
4
5
6
25
P PAD
VFB2
VREF
TONSEL
ENTRIP2
7
VO2
8
VREG3
9
VBST2
10
DRVH2
11
LL2
12
DRVL2
GND
VIN
SKIPSEL
EN0
15
16
14
13
12
PR315
@620K_0402_5%
12
2VREF_51125
0.1U_0603_25V7K
+5VALW
+3VALW
PJP302
2 1
PAD-OPEN 2x2m
PJP304
2 1
PAD-OPEN 2x2m
PJP305
2 1
PAD-OPEN 2x2m
12
PC314
PC315
22U_0805_6.3V6M
(4.5A,180mils ,Via NO.= 9)
(3A,120mils ,Via NO.= 6)
+VREG3_51125+3VLP
VL+5VLP
+3VL+3VEXTLP
PR302
30.9K_0402_1%
1 2
PR304
20K_0402_1%
1 2
PR306
95.3K +-1% 0402
ENTRIP1
1 2
1
2
VFB1
ENTRIP1
24
VO1
23
PGOOD
22
VBST1
21
DRVH1
20
LL1
19
DRVL1
VREG5
VCLK
PU301
17
18
TPS51125RGER_QFN24_4X4
+5VLP
1 2
12
PR319
@0_0402_5%
1U_0603_10V6K
BST_5V
LX_5V
LG_5V
PC321
PR308
2.2_0402_5%
1 2
+3VL
12
51125_PWR B++
PR320
255K_0402_1%
12
+5VALWP
12
PC318
PC309
0.1U_0402_10V7K
1 2
S TR AON7702L 1N DFN
PR314 @100K_0402_5%
P2
12
12
PR321
11.5K_0402_1%
12
12
PC304
PC305
0.1U_0402_25V6 1000P_0402_50V7K
PR310
0_0402_5%
1 2
RPGOOD 14
PC319
10U_0805_10V6K
DEBUG_KBCRST
PU302
1
+IN
2
V-
3
-IN
LMV321AS5X_SOT 23- 5
B++
12
PC306
PQ302
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4
PQ303
SIS412DN
3 5
241
5
123
PL303
4.7UH_PCMC063T -4R7MN_5.5A_20%
1 2
12
PR312
4.7_1206_5%
12
PC313 1000P_0603_50V8J
1
+
PC311
2
150U_B_6.3VM_R45M
+5VALWP
+3VEXTLP
OUT
V+
12
+5VLP
PR325
5
4
+5VLP
220K_0402_5%
1
12
2
3
12
PR326
470K_0402_5%
PR327
1 2
680K_0402_5%
PU303
VIN
GND
EN
VOUT
APL5317
16.5K_0402_1%
FB
12
PD304 1SS355_SOD323-2
5
4
PR324
12
12
PR322
64.9K_0402_1%
12
PR323
20K_0402_1%
12
PC320
2.2U_0603_6.3V6K
EN0 39
A
B
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008/09/15 2009/09/15
C
Compal Secret Data
Deciphered Date
Title
Size Document Number R ev
Cu stom
D
Date: Sheet o f
Compal Electronics, Inc.
3.3VALWP/5VALWP
LA-4902P
42 54Tuesday, December 15, 2009
E
0.1
A
B
C
D
1 1
2 2
B+
PL401
HCB2012KF-121T50_0805
1 2
12
PC416
0.1U_0402_25V6
SLP_S3#14,31,35,37,38,40,42,44,48
VCCP_EN37
VCCP_B+
12
PC401
1000P_0402_50V7K
+6269_VCC
2.2U_0603_6.3V6K
12
PC402
4.7U_0805_25V6-K
PC407
1 2
@0_0402_5%
1 2
0_0402_5%
12
PC403
12
PR406
PR428
4.7U_0805_25V6-K
12
PC404
4.7U_0805_25V6-K
PR405
0_0402_5%
1 2
12
PC411 @0.1U_0402_25V4K
22P_0402_50V8J
PR427
10K_0402_5%
VCCP_POK37
1
2
3
4
12
PC414
+3VS
12
PR401
@10K_0402_5%
17
PU401
VIN
VCC
FCCM
EN
12
PR409
19.1K_0402_1%
12
+VCCP
12
LX_VCCP
16
15UG14
GND
PHASE
PGOOD
COMP5FB6FSET
FB_VCCP
PR410
49.9K_0402_1%
DH_VCCP
7
12
1 2
PR402
2.2_0603_5%
+5VALW
BST_VCCP
PR403
0_0402_5%
13
BOOT
12
PVCC
DL _VCCP
11
LG
10
PGND
SE_VCCP
9
ISEN
VO
ISL6269ACRZ-T _QFN16
8
+VCCP
12
PC413
0.01U_0402_16V7K
12
PR404
2.2_0603_5%
1 2
1 2
1 2
PR417
0_0603_5%
1 2
PC405
0.22U_0603_16V7K
+6269_VCC
PC406
2.2U_0603_6.3V6K
1 2
PR407
7.87K_0402_1%
578
PQ401
DH _VCCP1
S TR T PC8037-H 1N SO8
3 6
241
PQ402
3 5
241
AON6718L
PL402
0.33UH_PCMC063T-R33MN_20A_20%
1 2
12
PR408
4.7_1206_5%
PC412
1 2
1000P_0603_50V7K
+VCCP
1
+
PC408
2
330U_X_2VM_R6M
1
1
PC409
+
+
PC410
2
2
330U_X_2VM_R6M
330U_X_2VM_R6M
(18A,720mils ,Via NO.= 36)
3 3
H_VTTVID17
H_VTTVID1= Low, 1.1V H_VTTVID1= High, 1.05V
4 4
A
1 2
PR416
35.7K_0402_1%
PC415
6800P_0603_50V7K
1 2
12
PR412
1.96K_0402_1%
PR411
1.58K_0402_1%
B
+VCCP
1 2
PR413 10_0402_5%
1 2
PR414 0_0402_5%
PC125 @0.1U_0402_10V7K
1 2
1 2
PR415 0_0402_5%
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VTT_SENSE 7
VSS_SENSE_VTT 7
2008/09/15 2009/09/15
Compal Secret Data
Deciphered Date
C
Title
Size Document Number R ev
Date: Sheet o f
Compal Electronics, Inc.
1.05V_VCCP
LA-4902P
D
43 54Tuesday, December 15, 2009
0.1
A
B
C
D
+1.5V
12
12
PC601
10U_0805_10V4Z
12
PR601
1K_0402_1%
PC602
12
PR603 1K_0402_1%
+0.75VS
PR605
0_0402_5%
1 2
12
PC607 @0.1U_0402_16V7K
1.8VS_POK 37
12
(2A,80mils ,Via NO.= 4)
1 1
+5VALW
PQ601A
2
1 2
10 9 8 7 6 11
10U_0805_6.3V6M
61
PJP601
PAD-OPEN 3x3m
PR604
47K_0402_1%
1 2
SLP_S3#14,31,35,37,38,40,42,43,48
PD601
1 2
1SS355_SOD323-2
12
316K_0402_1% PR607
1 2
PC608
10U_0805_10V6K
PC606
1 2
1 2
PR609
0_0402_5%
0.47U_0402_6.3V6K
2 2
PR608
402K_0402_1%
12
PC610
1 2
10U_0805_10V6K
12
0.1U_0402_16V7K
PC609
+1.8VSP
PL601
+5VALW
3 3
HCB1608KF-121T30_0603
1 2
12
PC611
0.1U_0402_25V6
12
PR602 10K_0402_5%
2N7002KDW-2N_SOT363-6
34
PQ601B 2N7002KDW-2N_SOT363-6
5
+0.75VSP
PU602
1
EN/SYNC
FB
2
GND
3 4 5
GND
SW
SW IN BS
MP2121DQ-LF-Z_QFN10_3X3
IN
POK
TP
0.1U_0402_10V7K
PC604
12
PU601
VIN1VCNTL
2 3 4
G2992F1U_SO8
GND VREF VOUT
NC NC NC
TP
+0.75VSP
12
PC605 10U_0805_6.3V6M
SLP_S3# 14,31,35,37,38,40,42,43,48
1.2UH_1127AS-1R2N_2.4A_30%
1 2
12
PR606
4.7_1206_5%
PD602
12
@B340A_SMA2
PC612 680P_0603_50V7K
PL602
6 5 7 8 9
12
PC603 1U_0603_10V6K
12
PC613
+5VALW
+1.8VSP
12
PC614
<BOM Structure>
<BOM Structure>
22U_0805_6.3V6M
22U_0805_6.3V6M
PJP602
+1.8VSP
4 4
A
1 2
PAD-OPEN 3x3m
(1.5A,60mils ,Via NO.= 3)
+1.8VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
2008/09/15 2009/09/15
Compal Secret Data
Deciphered Date
C
Title
Size Document Number R ev
Date: Sheet o f
Compal Electronics, Inc.
0.75VSP/PCIE/1.8VSP
LA-4902P
D
44 54Tuesday, December 15, 2009
0.1
A
B
C
D
PR516
PM_SLP_LAN#14,35,38
1 1
+5VALW
+5VALW
2 2
1 2
PR518
316_0402_1%
PC520
1U_0603_10V6K
SLP_S4#14,38
3 3
+5VALW
+5VALW
1 2
PR522
316_0402_1%
PC522
1U_0603_10V6K
0_0402_5%
+1.05VMP_LAN
+1.05VMP_LAN
12
PR521
0_0402_5%
+1.5VP
+1.5VP
12
12
PC519
12
@1000P_0402_50V7K
1 2
PR519 0_0402_5%
PR503
1 2
4.12K_0402_1%
1 2
PC526
@10P_0402_50V8J
10K_0402_1%
12
PC524
12
@1000P_0402_50V7K
1 2
PR520 0_0402_5%
PR501
1 2
10.2K_0603_0.1%
10K_0603_0.1%
PR514 255K_0402_1%
1 2
PR504
PR523 255K_0402_1%
1 2
PR502
UG_1.05V LX_1.05V
PR517
1 2
+5VALW LG_1.05V
UG_1.5V LX_1.5V
PR515
1 2
+5VALW LG_1.5V
PC511
0.1U_0402_10V7K
1 2
15.4K_0402_1%
PC510
0.1U_0402_10V7K
1 2
7.87K_0402_1%
12
PC521
4.7U_0805_10V6K
12
PC523
4.7U_0805_10V6K
PR509
0_0402_5%
1 2
PR508
0_0402_5%
1 2
UG1_1.05V
UG1_1.5V
PQ502
SIS412DN
PQ501
SIS412DN
3 5
241
786
5
PQ504
4
S TR AO4712L 1N SO8
123
+1.05VMP_LAN
3 5
241
786
5
4
PR511
2.2_0402_5%
BST_1.05V
1 2
1
PU501
2
TON
3
VOUT
4
V5FILT
5
VFB
6
PGOOD
12
1
PU502
2
TON
3
VOUT
4
V5FILT
5
VFB
6
PGOOD
12
14TP15
VBST
EN_PSV
DRVH
LL
TRIP
V5DRV
DRVL
GND7PGND
TPS51117RGYR_QFN14_3.5x3.5
8
1.05VM_LAN_POK 37
BST_1.5V
14TP15
VBST
EN_PSV
DRVH
LL
TRIP
V5DRV
DRVL
GND7PGND
TPS51117RGYR_QFN14_3.5x3.5
8
13 12 11 10 9
PR510
2.2_0402_5%
1 2
13 12 11 10 9
123
12
12
1.05VS_B+
12
12
PC504
PC505
0.1U_0402_25V6
1000P_0402_50V7K
2.2UH_PCMC063T -2R2MN_8A_20%
1 2
12
PR513
4.7_1206_5%
12
PC517 1000P_0603_50V8J
PJP501
1 2
PAD-OPEN 4x4m
1.5V_B+
12
12
PC502
PC501
0.1U_0402_25V6
1000P_0402_50V7K
2.2UH_PCMC063T -2R2MN_8A_20%
1 2
12
PR512
4.7_1206_5%
12
PC516 1000P_0603_50V8J
PC506
4.7U_0805_25V6M
PL503
4.7U_0805_6.3V6K
PC508
4.7U_0805_25V6M
PL502
4.7U_0805_6.3V6K
PL501
HCB1608KF-121T30_0603
1 2
12
PC507
4.7U_0805_25V6M
12
PC514
+1.05VM_LAN
PL504
HCB1608KF-121T30_0603
1 2
12
PC509
4.7U_0805_25V6M
12
PC513
B+
+1.05VMP_LAN
1
+
PC515
2
330U_B2_2.5VM_R15M
(8A,320mils ,Via NO.= 16)
B+
+1.5VP
1
+
PC512
2
330U_2.5V_B2_R15M
PQ503
1.5V_POK 37
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
2008/09/15 2009/09/15
Compal Secret Data
STS14N3LLH5 1N SO8
Deciphered Date
C
+1.5VP
PJP502
1 2
PAD-OPEN 4x4m
Title
Size Document Number R ev
Date: Sheet o f
Compal Electronics, Inc.
(8A,320mils ,Via NO.= 16)
+1.5V
1.5VP/1.05VMP
LA-4902P
D
45 54Tuesday, December 15, 2009
0.1
8
H H
H_ VID0
H_ VID07
H_ VID1
H_ VID17
H_ VID2
H_ VID27
H_ VID3
H_ VID37
H_ VID4
H_ VID47
H_ VID5
H_ VID57
H_ VID6
H_ VID67
PRO C_ DPR SLP VR7
VGATE14,35
H_PR OC HOT#4
12
PR234
@24 9K_0402_1%
PC227
15 0P_ 0402_50V8J
PM_ PWR OK35
CLK _EN#11
+VC CP
PSI#7
12
PR235
8.0 6K_0402_1%
1 2
33 P_04 02_50V8J
1 2
PRO C_ DPR SLP VR
PR219 0_0402_ 5%
1 2
1 2
PSI#
1 2
PR223 14 7K_04 02_1%
+VC CP
1 2
0_0402_ 5%
12
PC222
10 00P_ 0402_50 V7K
PC2 25
1 2
PR241
32 4K_040 2_1%
G G
F F
E E
D D
12
PR225
1 2
PR236
562_040 2_1%
1 2
2.3 7K_0402_1%
IS EN3 IS EN2 IS EN1
1 2
+3V ALW
47K_0402 _5%
PR221 @1 K_04 02_5%
PR283 1K _0402 _5%
1 2
PR224
68_0402 _5%
1 2
PC221
@22 P_ 0402 _50V8J
39 0P_040 2_50V7K
1 2
PC2 24
PR238
12
PC235
C C
VC CS ENSE7
B B
VSSSENSE7
1 2
PR2 51 0_0402_5%
PR2 63 0_0402_5%
1 2
33 0P_0 402_50V7 K
10 00P_04 02_50V7K
PR2 09 0_0402_5%
PR2 15
1 2
12
0.2 2U _0402_10V6K PC236
PC244
PC247
7
CLK _EN#
37
38
39
40
CLK_EN#
ISEN111VSEN12RTN13ISUM-14ISUM+15VDD
PC248
33 0P_0 402_50V7 K
VR_ON
DPRSLPVR
12
35
VID031VID132VID233VID334VID536VID6
VID4
BOOT2 UGATE2 PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1
VIN
IMON18BOOT119UGATE1
ISL6 28 83 HRZ- T_QF N40_5X5
17
16
20
12
12
PC228
1U_ 0603_10V6K
82.5_0402_1%
PR250
PC2 45
0.0 1U _0402_25V7K
PR260 768_040 2_1%
1 2
PU20 1
1
PGOOD
2
PSI#
3
RBIAS
4
VR_TT#
5
NTC
6
VW
7
COMP
8
FB
9
ISEN3
10
ISEN2
41
AGND
12
0.2 2U _0402_10V6K
0.2 2U _0402_10V6K
PC237
12
12
12
H_ VID0 H_ VID1 H_ VID2 H_ VID3 H_ VID4 H_ VID5 H_ VID6 PRO C_ DPR SLP VR
PC211 1U_ 0603_10V6K
30 29 28 27 26 25 24 23 22 21
12
PR2 42 0_0402_5%
1 2
PR2 44 1_0402_5%
1 2
PC229
0.2 2U _0603_25V7K
12
PC2 41
0.0 22 U_0402_25V7K
6
1 2
PR228
@0_0402_5%
1 2
PC2 23 1U_ 0603_10V6K
CPU_B +
+5V ALW
6.8 1K_0402_1%
12
0.3 3U _0603_10V7K
PC2 42
+5V ALW
PR2 46
12
PC2 43
PR2 66 @1 K_04 02_5%
12
PR2 67 @1 K_04 02_5%
12
PR2 68 1K_04 02_5%
12
PR2 69 1K_04 02_5%
12
PR2 70 @1 K_04 02_5%
12
PR2 71 1K_04 02_5%
12
PR2 72 @1 K_04 02_5%
12
PR2 73 1K_04 02_5%
12
PR239 0_04 02_5%
1 2
PR2 40 @402K_ 0402_1%
1 2
12
12
PC230
0.0 68 U_0603_16V7K
VSSSENSE
VSUM+
12
PR252
2.6 1K_0402_1%
0.0 47 U_0402_16V7K
12
12
PH20 1 10 KB_ 0603_ 5%_ERTJ1VR103J
PR262
11 K_0402 _1%
VSUM-
+VC CP
BOO ST _CPU2 UGAT E_ CPU2 P HASE_CP U2
LGATE _CPU2
+5V ALW
12
PC218
1U_ 0603_10V6K
IMVP_IMO N 7
+1. 05VS
5
H_ VID0 H_ VID1 H_ VID2 H_ VID3 H_ VID4 H_ VID5 H_ VID6 PRO C_ DPR SLP VR
PU20 2
5
BOOT
VCC
6
FCCM
UGATE
2
PWM
PHASE
3
LGATE
GND
ISL6 20 8C RZ-T _QFN8
BOO ST_ CPU1
PR208
2.2 _0603_5%
BOO ST _CPU3
1
UGAT E_ CPU3
8
P HASE_CP U3
7
LGATE _CPU3
4
UGAT E_ CPU1
P HASE_CP U1
LGATE _CPU1
PR280 1K_0402_5%
12
PR281 1K_0402_5%
12
PR282 @1K_0 402_5%
12
PR275 @1K_0 402_5%
12
PR276 1K_0402_5%
12
PR277 @1K_0 402_5%
12
PR278 1K_0402_5%
12
PR279 @1K_0 402_5%
12
12
PR226
2.2 _0603_5%
1 2
PR2 48
2.2 _0603_5%
PC209
0.2 2U_ 0603_10V7K
1 2
0.2 2U_ 0603_10V7K
1 2
12
4
PR2 49
0_0603_ 5%
PC2 19
PR2 64
0_0603_ 5%
1 2
PR274 0_0603_ 5%
PC240
0.2 2U_ 0603_10V7K
1 2
12
UGAT E1 _C PU1
12
UGAT E1 _C PU2
UGAT E1 _C PU3
578
3 6
241
3 5
241
578
3 6
241
3 5
241
578
3 6
241
PQ205 S T R TPC 80 37 -H 1N SO8
3 5
241
3
CPU_ B+
12
PC201
0.1 U_0 402_25V6
PQ201 S T R TPC 80 37 -H 1N SO8
PQ202 TPCA8036
PC2 12
0.1 U_0 402_25V6
PQ203
S T R TPC 80 37 -H 1N SO8
PQ204 TPCA8036
12
PC2 31
0.1 U_0 402_25V6
PQ206 TPCA8036
2
PL201
SMB3 02 5500YA_2P
12
12
12
PC202
22 00P_ 0402_50 V7K
12
12
PC203
PC207
4.7 U_ 0805_25V6-K
PR211
PC208
4.7 U_ 0805_25V6-K
4.7 U_ 0805_25V6-K
12
PR213
4.7_120 6_5%
3.6 5K_0603_1%
12
12
PC204
PC220
4.7 U_ 0805_25V6-K
0.3 6UH_PC MC1 04 T- R36MN1R17_ 30A_20%
LF2 V 2N
12
12
PR214
10 K_0402 _1%
10 00P_ 0402_50 V7K
PL202
1 2
PC249
4 3
12
PC2 10
10 00P_06 03_50V7K
12
12
PC2 13
22 00P_04 02_50V7K
12
PR2 29
12
PC2 26
10 00P_06 03_50V7K
12
12
PC2 32
22 00P_04 02_50V7K
12
PR2 53
12
PC246
10 00P_06 03_50V7K
12
12
PC2 51
PC2 14
10 00P_04 02_50V7K
4.7 U_0 805_25V6 -K
4.7 _1206_5%
PC2 52
PC2 33
10 00P_04 02_50V7K
4.7 U_0 805_25V6 -K
4.7 _1206_5%
IS EN2 VSUM+
CPU_B +
12
12
12
PC2 17
PC2 16
PC2 15
4.7 U_0 805_25V6 -K
12
PR2 31
3.6 5K_0603_1%
12
PC2 34
4.7 U_0 805_25V6 -K
12
PR255
3.6 5K_0603_1%
4.7 U_0 805_25V6 -K
4.7 U_0 805_25V6 -K
PL203
0.3 6UH_PC MC1 04 T- R36MN1R17_ 30A_20%
1
LF3 V 3N
2
12
PR2 32
10 K_0402 _1%
IS EN3 VSUM+
CPU_B +
12
12
12
PC2 39
PC2 38
4.7 U_0 805_25V6 -K
4.7 U_0 805_25V6 -K
PL204
0.3 6UH_PC MC1 04 T- R36MN1R17_ 30A_20%
1
LF1 V 1 N
2
12
PR256
10K_0402 _1%
<BO M S tructure >
IS EN1
VSUM+
1
B+
1
12
+
PC206
@10 0U_ 25V_M
2
@10 00P_0603_50V7K
+CP U_C ORE
12
PR216 1_0402_ 5%
VSUM-
4 3
VSUM-
4 3
VSUM-
12
PR233 1_0402_ 5%
12
PR2 57 1_0402_ 5%
+CP U_C ORE
+CP U_C ORE
12
A A
8
7
PC2 50
0.1 U_ 0402_16V7K
6
5
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CO NFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
2008/09/15 2009/09/15
Compal Secret Data
Deciphered Date
3
Compal Electronics, Inc.
Title
Size Do cum en t Nu mber R e v
Dat e: Sheet of
2
CPU_CORE
LA -4891
46 54Tuesda y, De ce mber 15, 2009
1
0.1
5
BQ24740VREF
12
PR1000 165K_0402_1%
IADAPT40
D D
CFET _A41
ADP_PRES
40
2
G
ADP_SIGNAL
1 2
100_0402_5%
C C
VI N
1 2
PR1013
10K_0402_1%
1 2
PR1014
150K_0402_5%
BSS138_SOT23-3
13
D
PQ1002
S
SSM3K7002FU_SC70-3
PR1022
PQ1000
1 3
D
G
S
G
2
13
D
S
PQ1001
BSS138_SOT23-3
OCP_ADJ 39
NDS0610_NL_SOT23-3
2
1
2
3
12
LMV321M5X-NOPB _SO T23 -5
PR1018 100K_0402_1%
S
PQ1003
12
PR1030 68K_0402_5%
12
PR1040 33K_0402_5%
12
PR1042
8.06K_0402_1%
12
+3VL
E
3
B
2
C
PQ1006
1
MMBT3906_SOT23-3
1
O
PU15A LM393DG_SO8
ADP_ A_ID
+3VL
12
PR1064 22K_0402_5%
ADP_A_ID 35
ADP_DET# 35
PD1004
12
PR1046
8.66K_0402_1%
12
12
3 2
ADP_ A_ID
PR1059
45.3K_0402_1%
1 2
PR1062
1M_0402_5%
VL
8
P
+
-
G
4
PR1045
B B
4.7K_0402_5%
1SS355_SOD323-2
2VREF_51125
12
PR1063 130K_0402_1%
A A
12
PR1065 10K_0402_1%
1 2
PR1066
10K_0402_5%
5
4
PC1000
0.22U_0603_10V7K
1 2
+IN
V-
OUTPUT
-IN
PU1000
1SS355_SOD323-2
D
13
G
2
4
V+
PD1000
5
4
12
+5VS
12
PC1001
0.01U_0402_16V7K
12
PR1017 2K_0402_5%
PD1001 1SS355_SOD323-2
1 2
12
1
PR1025
2
3.9K_0402_5%
3
OCP35
12
PC1003
3900P_0402_50V7K
2N7002KDW-2N_SOT363-6
1 2
PR1028
100K_0402_5%
OCP_A_IN
1 2
PR1032
100_0402_5%
2N7002KDW-2N_SOT363-6
PQ1007B
PQ1007A
2
B
12
GLZ4.7B_LL34-2
34
61
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
SRSET 40
C
PQ1005
MMBT 3904W_SOT323-3
E
3 1
OCP_A_IN 35
PD1003
ADP_EN# 40
5
VCC1_PWRGD 35,42
2
3
ADP_EN 35
2008/09/15 2009/09/15
Compal Secret Data
Deciphered Date
PR1023
27.4_0402_1%
1 2
PR1021
100K_0402_1%
12
PC1002
1 2
@0_0402_1%
1 2
200K_0402_1%
0.01U_0402_16V7K
PR1024 100K_0402_1%
1 2
2
PR1015
PR1016
PU1
1
IN+
VCC+
2
GND
OUT
3
IN-
LMV331IDCKRG4_SC70-5
1 2
PR1026
100K_0402_1%
2
1
+3VS
PR1019 10K_0402_5%
1 2
1 2
PR1020 0_0402_5%
13
D
2
G
S
PQ1004 SSM3K7002FU_SC70-3
+3VS
PR1027 10K_0402_1%
+5VS
1 2
5 4
+3VS
Title
Size Document Number R ev
Cu stom Date: Sheet o f
Compal Electronics, Inc.
ADP_OCP
LA-4902P
47 54Tuesday, December 15, 2009
1
OCP# 15
5
4
3
2
1
GPU_VID0 GPU_VID1 +NVVDD
0 1
PQ701 TPC8037_SO8
241
786
PQ702
AO4714_SO8
123
+VGA_COREP
1 1 1
2
PR701
D D
C C
B B
A A
SLP_S3#
PQ711
13
D
SSM3K7002FU_SC70-3
2
G
S
PR702
316_0402_1%
PC702
1U_0603_10V6K
4.42K_0402_1%
PC727
0.022U_0402_16V7K
1 2
5
200K_0402_5%
1 2
0.22U_0402_10V6K
+5VALW
+5VALW
12
12
PR734
2N7002KDW-2N_SOT363-6
PR735
5.1K_0402_1%
12
PC701
12
12
+VGA_COREP
PR739
15K_0402_1%
PQ710A
PR736 @10K_0402_5%
1 2
PR709
90.9K_0402_1%
12
12
61
2
NVVDD_POK37
12
PR740
17.8K_0402_1%
34
PQ710B
5
2N7002KDW-2N_SOT363-6
1 2
0.022U_0402_16V7K
PR705 255K_0402_1%
1 2
@10P_0402_50V8J
PC713
12
PR708
12
1K_0402_1%
PC717
0.022U_0402_16V7K
1 2
PC726
4
PU701
2
TON
3
VOUT
4
V5FILT
5
VFB
6
PGOOD
+VGA_COREP1
PR737
15K_0402_1%
2.61K_0402_1% PR732
1
EN_PSV
GND7PGND
12
1 2
12
1 2
578
BST_VGA
1 2
14TP15
VBST
13
DRVH
12
LL
11
TRIP
10
V5DRV
9
DRVL
8
S IC RT8209BGQW WQFN 14P PWM
1 2
PR717
10_0402_5%
1 2
PR718 0_0402_5%
PR704
0_0402_5%
+VGA_COREP
+NVVDD_SENSE
1 2
PC706
0.1U_0402_10V7K
LX_VGA
+5VALW
DL _VGA
1 2
PR707 0_0402_5%
1 2
12
12.4K_0402_1%
PC707
4.7U_0805_10V6K
+NVVDD_SENSE 23
PR706
DH _VGA_1D H_VGA
3 6
5
4
GPU_VID0 20
PR738 @10K_0402_5%
GPU_VID1 20
PR733 @10K_0402_5%
GPU_VID2 20
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008/09/15 2009/09/15
3
Compal Secret Data
Deciphered Date
0 0 1
@0.1U_0402_25V6
PC708
12
0.68UH_PCMC063T-R68MN_15.5A_20%
12
PR720
4.7_1206_5%
12
PC716 1000P_0603_50V7K
PJP701
1 2
PAD-OPEN 4x4m
PJP702
1 2
PAD-OPEN 4x4m
GPU_VID2
0 0 0 1
VGA_B+
4.7U_0805_25V6-K
12
1 2
4.7U_0805_25V6-K
PC703
PC704
12
12
PL702
+
+N VVDD
Title
Size Document Number R ev
Cu stom
LA-4902P
Date: Sheet o f
0.75V
0.8V
0.85V 1V
PL701
HCB1608KF-121T30_0603
1 2
2200P_0402_50V7K
PC710
12
PC718
@1000P_0603_50V7K
330U_D2E_2.5VM_R9M
1
PC709
2
330U_D2E_2.5VM_R9M
1
PC711
+
2
(10A,400mils ,Via NO.= 20)
Compal Electronics, Inc.
VCCGFX
1
B+
12
PC719
@1000P_0603_50V7K
+VGA_COREP
48 54Tuesday, December 15, 2009
5
4
3
2
Version change list (P.I.R. List) Power section Page 1 of 1
1
Item Reason for change PG# Modify List
Date
Phase
1
D D
2
3 4
5
6
7
C C
B B
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFIDENTIAL AND TR AD E SECRET INFOR MATION. THIS SHEET MAY N OT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEP ART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET N OR THE INFOR MATION IT CONTAINS
5
4
MAY BE USED BY OR DISC LOSED TO ANY THI RD PARTY W ITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELEC TRONICS, INC .
3
Compal Secret Data
2008/09/15 2009/09/15
Deciphered Date
2
Compal Electronics, Inc.
Title
Changed-List History
Size D oc u m en t Num be r Re v
Da te: She et of
LA- 49 02P
49 54Tu e sd ay , De cem ber 15, 200 9
1
0.1
A
B
C
Version Change List ( P. I. R. List ) for HW Circuit DB-1>> DB-2
D
E
Item Date
01
1
1 1
2 3 4 5 6 7 8 9 10 11 12 13
2 2
14 15 16 17 18 19 20 21 22 23 24
3 3
25 26 27 28 29 30 31 32 33 34 35 36
4 4
37 38
2222009/02/06
009/02/06 HP
009/02/06009/02/06
01
2222009/02/06
009/02/06
009/02/06009/02/06
01
2222009/02/06
009/02/06 HP
009/02/06009/02/06
01
2222009/02/24
009/02/24
009/02/24009/02/24
01
2222009/02/25
009/02/25 Debug port design guide changed XDP debug ports to CFG4 - pin 28, CFG5 - pin 30, CFG10 - pin 22, and CFG11 pin
009/02/25009/02/25
02
2222009/02/19
009/02/19 HP
009/02/19009/02/19
12
009/02/25 In
009/02/25009/02/25
2222009/02/06
009/02/0612HP
009/02/06009/02/06
12
2222009/02/06
009/02/06 Del C205, C207, C208, C209 for docking.
009/02/06009/02/06
12
2222009/02/06
009/02/06 Change D1pin 2 form +3VL to +VREG3_511
009/02/06009/02/06
12
2222009/02/06
009/02/06 DDDDel JP15 pin 51, 53 trace (SMB_DATA_S3, SMB_CLK_S3) and add test point.
009/02/06009/02/06
12
2222009/02/11
009/02/11
009/02/11009/02/11
12
2222009/02/11
009/02/11
009/02/11009/02/11
12
009/02/18
009/02/18009/02/18
13
2222009/02/06
009/02/06 Install R354
009/02/06009/02/06
13
009/02/06
009/02/06009/02/06
13
2222009/02/20
009/02/20
009/02/20009/02/20
13
2222009/02/20
009/02/20
009/02/20009/02/20
13
2222009/02/22
009/02/22 HP
009/02/22009/02/22
2222009/02/22
009/02/2213HP
009/02/22009/02/22
14
2222009/01/22
009/01/22
009/01/22009/01/22
14
009/02/19
009/02/19009/02/19
14
009/02/06
009/02/06009/02/06
14
009/02/06
009/02/06009/02/06
14
009/02/25
009/02/25009/02/25
16
2222009/01/22
009/01/22 HP
009/01/22009/01/22
16
009/01/22
009/01/22009/01/22
16
2222009/01/22
009/01/22 Del C847 and add test poi
009/01/22009/01/22
16
2222009/01/22
009/01/22 Del L4, C269 and add test poi
009/01/22009/01/22
16
009/01/22
009/01/22009/01/22
16
2222009/02/03
009/02/03 Change R299, R300 form 10 ohm to 100ohm.
009/02/03009/02/03
16
2222009/02/03
009/02/03
009/02/03009/02/03
16
2222009/02/05
009/02/05
009/02/05009/02/05
18
2222009/02/18
009/02/18 Compal
009/02/18009/02/18
18
2222009/02/24
009/02/24 Change R321, R320, R319, R318 form 2.2K ohm to 4.7K ohm.
009/02/24009/02/24
2222009/02/18
009/02/1818Compal
009/02/18009/02/18
18
009/02/12
009/02/12009/02/12
19
2222009/01/22
009/01/22 HP
009/01/22009/01/22
Owner
Compal
Compal2222009/02/25
CompalCompal
Compal2222009/02/25
CompalCompal
Compal
CompalCompal
Nvidia
Nvidia
NvidiaNvidia
Compal Res
CompalCompal
Nvidia2222009/02/12
NvidiaNvidia
A
HP Del R4, R6, R8 for XDP.
HPHP
HP
HP
HPHP
HP Del R34, R36, R46, R49, R37 for XD
HPHP
HP
HP
HPHP
HP
HPHP
HP No install R60, R
HPHP
HP Change R1026, R181, R185, R1027 from 15 ohm to 0 oh
HPHP
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HPHP
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HP
HPHP
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HP
HPHP
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HPHP
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HP
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HP
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HPHP
HP Del L1, C228, C229 and add test po
HPHP
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HP
HPHP
HP
HP
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HP Ad
HPHP
Solution Description
Del R4, R6, R8 for XDP.
Del R4, R6, R8 for XDP.Del R4, R6, R8 for XDP.
Del
Del R40 for Thermal sensor.
R40 for Thermal sensor.
Del Del
R40 for Thermal sensor.R40 for Thermal sensor.
Del R34, R36, R46, R49, R37 for XDP.
Del R34, R36, R46, R49, R37 for XDDel R34, R36, R46, R49, R37 for XD
Change R31 24.9K ohm to 1.5K ohm and R33 12.4K ohm to 750 ohm for intel
Change R31 24.9K ohm to 1.5K ohm and R33 12.4K ohm to 750 ohm for intel WOW.
Change R31 24.9K ohm to 1.5K ohm and R33 12.4K ohm to 750 ohm for intel Change R31 24.9K ohm to 1.5K ohm and R33 12.4K ohm to 750 ohm for intel
Debug port design guide changed XDP debug ports to CFG4 - pin 28, CFG5 - pin 30, CFG10 - pin 22, and CFG11 pin 24.
Debug port design guide changed XDP debug ports to CFG4 - pin 28, CFG5 - pin 30, CFG10 - pin 22, and CFG11 pinDebug port design guide changed XDP debug ports to CFG4 - pin 28, CFG5 - pin 30, CFG10 - pin 22, and CFG11 pin
No install R60, R61.
No install R60, RNo install R60, R
In stall C193, C194 for WLAN nosie
stall C193, C194 for WLAN nosie
InIn
stall C193, C194 for WLAN nosiestall C193, C194 for WLAN nosie
Change R1026, R181, R185, R1027 from 15 ohm to 0 ohm.
Change R1026, R181, R185, R1027 from 15 ohm to 0 ohChange R1026, R181, R185, R1027 from 15 ohm to 0 oh
Del C205, C207, C208, C209 for docking.HP
Del C205, C207, C208, C209 for docking.Del C205, C207, C208, C209 for docking.
Change D1pin 2 form +3VL to +VREG3_51125
Change D1pin 2 form +3VL to +VREG3_511Change D1pin 2 form +3VL to +VREG3_511
el JP15 pin 51, 53 trace (SMB_DATA_S3, SMB_CLK_S3) and add test point.
el JP15 pin 51, 53 trace (SMB_DATA_S3, SMB_CLK_S3) and add test point.el JP15 pin 51, 53 trace (SMB_DATA_S3, SMB_CLK_S3) and add test point.
Add R1144 1K o
Add R1144 1K ohm
Add R1144 1K oAdd R1144 1K o
AAAAdd Test point for SATA bus.
dd Test point for SATA bus.
dd Test point for SATA bus.dd Test point for SATA bus.
Add NAND Flash dect pin (BRAID_DET)
Add NAND Flash dect pin (BRAID_DET)2222009/02/18
Add NAND Flash dect pin (BRAID_DET)Add NAND Flash dect pin (BRAID_DET)
Install R354
Install R354Install R354
Add R1138 10K ohm
Add R1138 10K ohm2222009/02/06
Add R1138 10K ohmAdd R1138 10K ohm
Cha
Change R1092, R1093 power sourece form +3VS to +3VS.
nge R1092, R1093 power sourece form +3VS to +3VS.
ChaCh a
nge R1092, R1093 power sourece form +3VS to +3VS.nge R1092, R1093 power sourece form +3VS to +3VS.
Del R208, R2
Del R208, R210
Del R208, R2Del R208, R2
Add Q76A and Q76B for C
Add Q76A and Q76B for C BB
Add Q76A and Q76B for CAdd Q76A and Q76B for C
Rese
Reserve R1146 and R1147 for external VGA thermal
rve R1146 and R1147 for external VGA thermal
ReseRe se
rve R1146 and R1147 for external VGA thermalrve R1146 and R1147 for external VGA thermal
Del R238, because double pull down.
Del R238, because double pull down.
Del R238, because double pull down. Del R238, because double pull down.
Del R288
Del R2882222009/02/19
Del R288Del R288
SSSStuff R296
tuff R2962222009/02/06
tuff R296tuff R296
Add R1142 10K ohm
Add R1142 10K ohm2222009/02/06
Add R1142 10K ohmAdd R1142 10K ohm
Add C949 for RF
Add C949 for RFCompal
Add C949 for RFAdd C949 for RF
Del L1, C228, C229 and add test point.
Del L1, C228, C229 and add test poDel L1, C228, C229 and add test po
Del L2, C241 and add test poi
Del L2, C241 and add test poi nt.
Del L2, C241 and add test poiDel L2, C241 and add test poi
Del C847 and add test point.
Del C847 and add test poiDel C847 and add test poi
Del L4, C269 and add test poi nt.
Del L4, C269 and add test poiDel L4, C269 and add test poi
Del L3, C263, C262 and add test poi
Del L3, C263, C262 and add test point.
Del L3, C263, C262 and add test poiDel L3, C263, C262 and add test poi
Change R299, R300 form 10 ohm to 100ohm.
Change R299, R300 form 10 ohm to 100ohm.Change R299, R300 form 10 ohm to 100ohm.
CCCChange C278 form 0.1uF to 1uF.
hange C278 form 0.1uF to 1uF.
hange C278 form 0.1uF to 1uF.hange C278 form 0.1uF to 1uF.
Change C243, C244 form 10uF to 22uF.
Change C243, C244 form 10uF to 22uF.
Change C243, C244 form 10uF to 22uF.Change C243, C244 form 10uF to 22uF.
AAAAdd L48, L49, L50, C944, C943, C942 for EMI
dd L48, L49, L50, C944, C943, C942 for EMI
dd L48, L49, L50, C944, C943, C942 for EMIdd L48, L49, L50, C944, C943, C942 for EMI
Change R321, R320, R319, R318 form 2.2K ohm to 4.7K ohm.
Change R321, R320, R319, R318 form 2.2K ohm to 4.7K ohm.Change R321, R320, R319, R318 form 2.2K ohm to 4.7K ohm.
Reserve D5, D6, D7, D8, D9 for ESD
erve D5, D6, D7, D8, D9 for ESD
ResRe s
erve D5, D6, D7, D8, D9 for ESDerve D5, D6, D7, D8, D9 for ESD
Del R1066
Del R1066Nvidia
Del R1066Del R1066
Ad d Q71, Q72, R1134 for Keyboard light
d Q71, Q72, R1134 for Keyboard light
AdAd
d Q71, Q72, R1134 for Keyboard lightd Q71, Q72, R1134 for Keyboard light
10
1010
61.
61.61.
hm
hmhm
nt.
nt.nt.
BB
BBBB
B
nt.2222009/01/22
nt.nt.
nt.
nt.nt.
P.
P.P.
int.
int.int.
nt.2222009/01/22
nt.nt.
25
2525
m.
m.m.
WOW.
WOW.WOW.
24.HP
24. 24.
Security Classification
Issued Date
THIS SHE ET OF ENG INEE RING DRA WIN G IS THE P ROP RIETA RY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRAD E SEC RET INFO RMATI ON. THIS S HEE T MA Y NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEP ARTM ENT EXCE PT A S AUTHO RIZED BY C OMP AL ELE CTRON ICS, IN C. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY B E USE D B Y O R D ISCLO SE D TO AN Y TH IRD PAR TY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
D
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
Hardware revision (0.1 to 0.2)
LA -490 1 P
E
Rev.Page#
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
1. 0
50 54T u esd ay , Dec ember 15, 2 00 9
Reque st
A
B
C
Version Change List ( P. I. R. List ) for HW Circuit DB-1>> DB-2
D
E
Item Date
19
39
1 1
40 41 42 43 44 45 46 47 48 49 50 51
2 2
52 53 54 55 56 57 58 59 60 61 62
3 3
63 64 65 66 67 68 69 70 71 72
2222009/02/06
009/02/06 Nvidia
009/02/06009/02/06
19
2222009/02/06
009/02/06
009/02/06009/02/06
20
2222009/02/12
009/02/12
009/02/12009/02/12
20
2222009/02/24
009/02/24
009/02/24009/02/24
20
2222009/02/25
009/02/25
009/02/25009/02/25
21
2222009/01/20
009/01/20 HP
009/01/20009/01/20
21
2222009/02/26
009/02/26 De
009/02/26009/02/26
22
2222009/01/20
009/01/20
009/01/20009/01/20
22
2222009/02/06
009/02/06 Del
009/02/06009/02/06
22
2222009/02/06
009/02/06 Del
009/02/06009/02/06
23
2222009/02/23
009/02/23 Add L47, C941 for SP_PLLVDD
009/02/23009/02/23
26
2222009/02/19
009/02/19 Del C505, C509, C507, C508, C905, Q18, R440, R1062, R
009/02/19009/02/19
26
2222009/02/06
009/02/06
009/02/06009/02/06
27
2222009/02/18
009/02/18
009/02/18009/02/18
28
2222009/02/06
009/02/06
009/02/06009/02/06
29
009/02/26
009/02/26009/02/26
30
009/02/24
009/02/24009/02/24
30
2222009/02/24
009/02/24
009/02/24009/02/24
31
2222009/02/22
009/02/22
009/02/22009/02/22
2222009/02/18
009/02/1832HP
009/02/18009/02/18
33
2222009/02/18
009/02/18
009/02/18009/02/18
34
009/02/06
009/02/06009/02/06
34
009/01/22
009/01/22009/01/22
34
009/02/06
009/02/06009/02/06
34
2222009/02/06
009/02/06 HP
009/02/06009/02/06
35
2222009/02/06
009/02/06 Re
009/02/06009/02/06
35
2222009/02/06
009/02/06
009/02/06009/02/06
35
2222009/02/16
009/02/16 Change R692 from 10K ohm to 220 o
009/02/16009/02/16
35
2222009/01/22
009/01/22 Del L4, C269 and add test poi
009/01/22009/01/22
36
2222009/02/18
009/02/18 Compal
009/02/18009/02/18
37
2222009/02/25
009/02/25
009/02/25009/02/25
37
2222009/02/06
009/02/06
009/02/06009/02/06
37
2222009/02/25
009/02/25
009/02/25009/02/25
38
2222009/02/18
009/02/18
009/02/18009/02/18
Owner
Nvidia AAAAdd C914, C915, C916, C917 for eDP.
NvidiaNvidia
HP
HP
HPHP
Nvidia
Nvidia Re
NvidiaNvidia
HP
HP
HPHP
HP
HPHP
HP
HPHP
Nvidia
Nvidia
NvidiaNvidia
Nvidia
Nvidia AAAAdd C924 ~ C931 for DP function
NvidiaNvidia
Nvidia
Nvidia
NvidiaNvidia
Nvidia
Nvidia
NvidiaNvidia
Nvidia
Nvidia
NvidiaNvidia
HP
HPHP
HP
HP
HPHP
HP
HP
HPHP
HP
HP
HPHP
HP
HP
HPHP
Compal
Compal
CompalCompal
Compal
Compal Add Q79 ~ Q83, R1163, R1162, R1164, C945, C946, C947, C9
CompalCompal
Compal
Compal
CompalCompal
HP
HPHP
Compal
Compal Res
CompalCompal
HP
HP
HPHP
HP
HP
HPHP
HP
HP
HPHP
HP
HPHP
HP
HP
HPHP
HP
HP
HPHP
HP
HP
HPHP
HP
HP
HPHP
Compal cha
CompalCompal
HP
HP
HPHP
HP
HP
HPHP
HP
HP
HPHP
Compal
CompalCompal
Solution Description
dd C914, C915, C916, C917 for eDP.
dd C914, C915, C916, C917 for eDP.dd C914, C915, C916, C917 for eDP.
Change R341 pin 1 power plan form +5VS to +3VALW.
Change R341 pin 1 power plan form +5VS to +3VALW.
Change R341 pin 1 power plan form +5VS to +3VALW.Change R341 pin 1 power plan form +5VS to +3VALW.
Re serve R1150
serve R1150
ReR e
serve R1150serve R1150
Change R355, R356 from 2K ohm to 10K oh
Change R355, R356 from 2K ohm to 10K oh m.
Change R355, R356 from 2K ohm to 10K ohChange R355, R356 from 2K ohm to 10K oh
Ad
Ad d Q78, R1158, R1157 for thermal trip.
d Q78, R1158, R1157 for thermal trip.HP
AdAd
d Q78, R1158, R1157 for thermal trip.d Q78, R1158, R1157 for thermal trip.
Del LVDS function
Del LVDS function
Del LVDS functionDel LVDS function
De l C346, because no SPDIF.
l C346, because no SPDIF.
DeDe
l C346, because no SPDIF.l C346, because no SPDIF.
dd C924 ~ C931 for DP function
dd C924 ~ C931 for DP functiondd C924 ~ C931 for DP function
Del RP28, 31, 34, 40, 49, 52, 55, 29, 43, 35, 39, 44, 48, 53, 56, 30, 33, 36, 38, 45, 46, 42 for VRAM
RP28, 31, 34, 40, 49, 52, 55, 29, 43, 35, 39, 44, 48, 53, 56, 30, 33, 36, 38, 45, 46, 42 for VRAM
Del Del
RP28, 31, 34, 40, 49, 52, 55, 29, 43, 35, 39, 44, 48, 53, 56, 30, 33, 36, 38, 45, 46, 42 for VRAMRP28, 31, 34, 40, 49, 52, 55, 29, 43, 35, 39, 44, 48, 53, 56, 30, 33, 36, 38, 45, 46, 42 for VRAM
Del C904, 899, 900, 901, 902, 903 for VRAM
C904, 899, 900, 901, 902, 903 for VRAM
DelDel
C904, 899, 900, 901, 902, 903 for VRAM C904, 899, 900, 901, 902, 903 for VRAM
Add L47, C941 for SP_PLLVDD
Add L47, C941 for SP_PLLVDDAdd L47, C941 for SP_PLLVDD
Del C505, C509, C507, C508, C905, Q18, R440, R1062, R441
Del C505, C509, C507, C508, C905, Q18, R440, R1062, RDel C505, C509, C507, C508, C905, Q18, R440, R1062, R
Add C934
Add C934
Add C934Add C934
Rese
ReserveD57 for ESD
rveD57 for ESD
ReseRe se
rveD57 for ESDrveD57 for ESD
RRRRecover Q25, R503, R483
ecover Q25, R503, R483
ecover Q25, R503, R483ecover Q25, R503, R483
AAAAdd R1159 for NAND Flash detect
dd R1159 for NAND Flash detect2222009/02/26
dd R1159 for NAND Flash detectdd R1159 for NAND Flash detect
Del R529, R528, R535, C618, U
Del R529, R528, R535, C618, U 22
Del R529, R528, R535, C618, UDel R529, R528, R535, C618, U
Add Q79 ~ Q83, R1163, R1162, R1164, C945, C946, C947, C948
Add Q79 ~ Q83, R1163, R1162, R1164, C945, C946, C947, C9Add Q79 ~ Q83, R1163, R1162, R1164, C945, C946, C947, C9
Del D30, U28, C711, R608
Del D30, U28, C711, R608
Del D30, U28, C711, R608Del D30, U28, C711, R608
Rese
Reserve D33, D34, D36, D68 for ESD
rve D33, D34, D36, D68 for ESD
ReseRe se
rve D33, D34, D36, D68 for ESDrve D33, D34, D36, D68 for ESD
Reserve D32 for ESD
erve D32 for ESD
ResRe s
erve D32 for ESDerve D32 for ESD
Add JP32 of pin 179, 178, 11, 10 to +5VS
Add JP32 of pin 179, 178, 11, 10 to +5VS2222009/02/06
Add JP32 of pin 179, 178, 11, 10 to +5VSAdd JP32 of pin 179, 178, 11, 10 to +5VS
Del C746 ~ C7
Del C746 ~ C7 61
Del C746 ~ C7Del C746 ~ C7
AAAAdd Q75, R1145.
dd Q75, R1145.2222009/02/06
dd Q75, R1145.dd Q75, R1145.
Del R647~ R650
Del R647~ R650
Del R647~ R650Del R647~ R650
Re serve R711
serve R711
ReR e
serve R711serve R711
Add R1140
Add R1140
Add R1140Add R1140
Change R692 from 10K ohm to 220 ohm
Change R692 from 10K ohm to 220 oChange R692 from 10K ohm to 220 o
Del L4, C269 and add test poi nt.
Del L4, C269 and add test poiDel L4, C269 and add test poi
change Super IO from ITE to SMSC
nge Super IO from ITE to SMSC
chacha
nge Super IO from ITE to SMSCnge Super IO from ITE to SMSC
Del R758
Del R758
Del R758Del R758
CCCChange R941 pin from PM_SLP_LAN# to PM_SLP_M#
hange R941 pin from PM_SLP_LAN# to PM_SLP_M#
hange R941 pin from PM_SLP_LAN# to PM_SLP_M#hange R941 pin from PM_SLP_LAN# to PM_SLP_M#
ch
ch ange R1044 from 49.9K ohm to 78.7K ohm.
ange R1044 from 49.9K ohm to 78.7K ohm.
chch
ange R1044 from 49.9K ohm to 78.7K ohm.ange R1044 from 49.9K ohm to 78.7K ohm.
Add Q77, R1170, C939, R1156, C935 ~ C9
Add Q77, R1170, C939, R1156, C935 ~ C938
Add Q77, R1170, C939, R1156, C935 ~ C9Add Q77, R1170, C939, R1156, C935 ~ C9
612222009/01/22
6161
nt.
nt.nt.
222222009/02/24
2222
hm
hmhm
38Compal
3838
m.
m.m.
441HP
441441
48
4848
73 74
4 4
75 76
Security Classification
Issued Date
THIS SHE ET OF ENG INEE RING DRA WIN G IS THE P ROP RIETA RY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRAD E SEC RET INFO RMATI ON. THIS S HEE T MA Y NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEP ARTM ENT EXCE PT A S AUTHO RIZED BY C OMP AL ELE CTRON ICS, IN C. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY B E USE D B Y O R D ISCLO SE D TO AN Y TH IRD PAR TY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
D
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
Hardware revision (0.1 to 0.2)
LA -490 1 P
E
Rev.Page#
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
1. 0
51 54T u esd ay , Dec ember 15, 2 00 9
Reque st
A
B
C
Version Change List ( P. I. R. List ) for HW Circuit DB-2>> DB-3
D
E
Item Date
15
01
1 1
02 03 04 05 06 07 08 09 10 11 12 13
2 2
14 15 16 17 18 19 20 21 22 23 24
3 3
25 26 27 28 29 30 31
2222009/03/23
009/03/23 Add RP59
009/03/23009/03/23
15
009/03/23
009/03/23009/03/23
30
2222009/03/08
009/03/08
009/03/08009/03/08
36
2222009/03/23
009/03/23 Compal
009/03/23009/03/23
36
2222009/03/23
009/03/23 Change R1059 from 40.2 ohm to 60.4 ohm
009/03/23009/03/23
36
2222009/03/23
009/03/23
009/03/23009/03/23
36
2222009/04/09
009/04/09 Install R706 for SMSC C
009/04/09009/04/09
23
009/04/09
009/04/09009/04/09
23
009/04/09
009/04/09009/04/09
23
2222009/04/09
009/04/09
009/04/09009/04/09
18
2222009/04/09
009/04/09 Ad
009/04/09009/04/09
01
2222009/04/13
009/04/13 Compal
009/04/13009/04/13
38
2222009/04/13
009/04/13 Compal
009/04/13009/04/13
35
2222009/04/13
009/04/13 Compal
009/04/13009/04/13
31
2222009/04/13
009/04/13 Compal
009/04/13009/04/13
16
2222009/04/13
009/04/13 Compal
009/04/13009/04/13
15
009/04/13 Change C956 ~ C951 from 47P to 22P for
009/04/13009/04/13
04
009/04/10 Install R51
009/04/10009/04/10
27
2222009/04/10
009/04/10 HP
009/04/10009/04/10
33
2222009/04/10
009/04/10 HP
009/04/10009/04/10
15
009/04/10
009/04/10009/04/10
04
009/04/10
009/04/10009/04/10
20
009/04/10 HP
009/04/10009/04/10
15
2222009/04/10
009/04/10 HP
009/04/10009/04/10
19
2222009/04/10
009/04/10 HP
009/04/10009/04/10
19
2222009/04/10
009/04/10 HP
009/04/10009/04/10
09
2222009/04/10
009/04/10 HP
009/04/10009/04/10
10
2222009/04/10
009/04/10 HP
009/04/10009/04/10
38
009/04/13 Compal
009/04/13009/04/13
13
2222009/04/10
009/04/10 HP
009/04/10009/04/10
35
2222009/04/14
009/04/14 Install R1035, R1036, R1037; no install R1
009/04/14009/04/14
Owner
Compal
Compal
CompalCompal
Compal
Compal
CompalCompal
Compal
Compal
CompalCompal
Compal
CompalCompal
Nvidia
Nvidia
NvidiaNvidia
Nvidia
NvidiaNvidia
Compal
Compal
CompalCompal
Nvidia
Nvidia
NvidiaNvidia
Nvidia
Nvidia
NvidiaNvidia
Nvidia
Nvidia
NvidiaNvidia
HP
HP
HPHP
Compal DDDDel R12 for follow UMA
CompalCompal
Compal De
CompalCompal
Compal
CompalCompal
Compal Ad
CompalCompal
Compal DDDDel R290, R291 for follow UMA
CompalCompal
Compal
Compal2222009/04/13
CompalCompal
HP
HP2222009/04/10
HPHP
HP
HPHP
HP Re
HPHP
HP2222009/04/10
HPHP
HP2222009/04/10
HPHP
HP
HPHP
HP Re
HPHP
HP Re
HPHP
HP Del R484
HPHP
HP DDDDel M2
HPHP
HP DDDDel M2
HPHP
Compal
CompalCompal
HP
HPHP
Compal
CompalCompal
Solution Description
Add RP59
Add RP59Add RP59
Re
Re serve C956 ~ C951 for RF
serve C956 ~ C951 for RF2222009/03/23
ReR e
serve C956 ~ C951 for RFserve C956 ~ C951 for RF
Add R1173 for RF
Add R1173 for RF
Add R1173 for RFAdd R1173 for RF
Add R1174 10K ohm
Add R1174 10K ohm
Add R1174 10K ohmAdd R1174 10K ohm
Change R1059 from 40.2 ohm to 60.4 ohm
Change R1059 from 40.2 ohm to 60.4 ohmChange R1059 from 40.2 ohm to 60.4 ohm
Change R418 from 60.4 ohm to 40.2 ohm
Change R418 from 60.4 ohm to 40.2 ohmNvidia
Change R418 from 60.4 ohm to 40.2 ohmChange R418 from 60.4 ohm to 40.2 ohm
Install R706 for SMSC CBB
Install R706 for SMSC CInstall R706 for SMSC C
Del L16, C429 ~ C432 for no use LVDS function
Del L16, C429 ~ C432 for no use LVDS function2222009/04/09
Del L16, C429 ~ C432 for no use LVDS functionDel L16, C429 ~ C432 for no use LVDS function
Del L17, C433 ~ C435, C436, C437, C883 for no use LVDS functi
Del L17, C433 ~ C435, C436, C437, C883 for no use LVDS functi on
Del L17, C433 ~ C435, C436, C437, C883 for no use LVDS functiDel L17, C433 ~ C435, C436, C437, C883 for no use LVDS functi
AAAAdd R1175 ~ R1177 for no use LVDS function
dd R1175 ~ R1177 for no use LVDS function
dd R1175 ~ R1177 for no use LVDS functiondd R1175 ~ R1177 for no use LVDS function
Ad d C957 for DP issue
d C957 for DP issue
AdAd
d C957 for DP issued C957 for DP issue
el R12 for follow UMA
el R12 for follow UMAel R12 for follow UMA
De l Q70, R1094 for follow UMA
l Q70, R1094 for follow UMA
DeDe
l Q70, R1094 for follow UMAl Q70, R1094 for follow UMA
Re
Re serve R1140
serve R1140
ReR e
serve R1140serve R1140
Ad d R1179 for follow UMA
d R1179 for follow UMA
AdAd
d R1179 for follow UMAd R1179 for follow UMA
el R290, R291 for follow UMA
el R290, R291 for follow UMAel R290, R291 for follow UMA
Change C956 ~ C951 from 47P to 22P for RF
Change C956 ~ C951 from 47P to 22P for Change C956 ~ C951 from 47P to 22P for
Install R51
Install R51Install R51
No install R10
No install R1083
No install R10No install R10
Re serve R1180
serve R1180
ReR e
serve R1180serve R1180
LAN_DIS# should pull up to +3VM_LAN instead of 3VALW
LAN_DIS# should pull up to +3VM_LAN instead of 3VALWHP
LAN_DIS# should pull up to +3VM_LAN instead of 3VALWLAN_DIS# should pull up to +3VM_LAN instead of 3VALW
Change R14/R15 to 1.1K1%/3K1% per DG1.
Change R14/R15 to 1.1K1%/3K1% per DG1.52
Change R14/R15 to 1.1K1%/3K1% per DG1.Change R14/R15 to 1.1K1%/3K1% per DG1.
Install R1085 and R1086 for SM communication to G
Install R1085 and R1086 for SM communication to GPU
Install R1085 and R1086 for SM communication to GInstall R1085 and R1086 for SM communication to G
Re serve R1181
serve R1181
ReR e
serve R1181serve R1181
Re serve R331
serve R331
ReR e
serve R331serve R331
Del R484
Del R484Del R484
el M2
el M2el M2
el M2
el M2el M2
Add R1178
Add R11782222009/04/13
Add R1178Add R1178
XTAL_IN (ohm to GND if not used)For discrete:NO INSTALL: R215, Y4, C226, INSTALL 0ohm resistor in C227
XTAL_IN (ohm to GND if not used)For discrete:NO INSTALL: R215, Y4, C226, INSTALL 0ohm resistor in C227
XTAL_IN (ohm to GND if not used)For discrete:NO INSTALL: R215, Y4, C226, INSTALL 0ohm resistor in C227XTAL_IN (ohm to GND if not used)For discrete:NO INSTALL: R215, Y4, C226, INSTALL 0ohm resistor in C227
Install R1035, R1036, R1037; no install R1 034.
Install R1035, R1036, R1037; no install R1Install R1035, R1036, R1037; no install R1
83
8383
BB
BBBB
RF
RFRF
034.Compal
034.034.
52HP
5252
PU2222009/04/10
PUPU
on2222009/04/09
onon
Rev.Page#
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
Reque st
4 4
Security Classification
Issued Date
THIS SHE ET OF ENG INEE RING DRA WIN G IS THE P ROP RIETA RY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRAD E SEC RET INFO RMATI ON. THIS S HEE T MA Y NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEP ARTM ENT EXCE PT A S AUTHO RIZED BY C OMP AL ELE CTRON ICS, IN C. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY B E USE D B Y O R D ISCLO SE D TO AN Y TH IRD PAR TY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
D
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
Hardware revision (0.2 to 0.3)
LA -490 1 P
E
52 54T u esd ay , Dec ember 15, 2 00 9
1. 0
A
B
C
Version Change List ( P. I. R. List ) for HW Circuit DB-3>> SI-1
D
E
Item Date
16
01
1 1
02 03 04 05 06 07 08 09 10 11 12 13
2 2
2222009/04/24
009/04/24 Del R294
009/04/24009/04/24
13
2222009/04/24
009/04/24 HP
009/04/24009/04/24
14
2222009/04/24
009/04/24
009/04/24009/04/24
14
2222009/04/24
009/04/24
009/04/24009/04/24
14
2222009/04/24
009/04/24 AAAAdd R1188, R1187 for intel spec
009/04/24009/04/24
27
009/04/24
009/04/24009/04/24
36
2222009/04/24
009/04/24 Add R1190, R1189
009/04/24009/04/24
29
2222009/04/24
009/04/24 DDDDel C574~C577 and C579~C582.
009/04/24009/04/24
33
009/04/24
009/04/24009/04/24
26
009/05/02
009/05/02009/05/02
04
2222009/05/02
009/05/02 HP
009/05/02009/05/02
35
2222009/05/02
009/05/02 HP
009/05/02009/05/02
38
2222009/05/02
009/05/02 HP
009/05/02009/05/02
Owner
HP
HP
HPHP
HP
HPHP
HP
HP
HPHP
HP
HP
HPHP
HP
HP
HPHP
HP
HP
HPHP
HP
HP
HPHP
HP
HP
HPHP
HP
HP
HPHP
HP
HP
HPHP
HP Install R1060
HPHP
HP Add R1197, C967, C966, C968, R1195, R11
HPHP
HP Add C978, C979
HPHP
Solution Description
Del R294
Del R294Del R294
Del CL
Del CLRP2
RP2
Del CLDel CL
RP2RP2
Del C147, C148 locat
Del C147, C148 location
Del C147, C148 locatDel C147, C148 locat
Add C961
Add C961
Add C961Add C961
dd R1188, R1187 for intel spec
dd R1188, R1187 for intel specdd R1188, R1187 for intel spec
Add C962 ~ C965
Add C962 ~ C9652222009/04/24
Add C962 ~ C965Add C962 ~ C965
Add R1190, R1189
Add R1190, R1189Add R1190, R1189
el C574~C577 and C579~C582.
el C574~C577 and C579~C582.el C574~C577 and C579~C582.
Add R1191, R1192
Add R1191, R11922222009/04/24
Add R1191, R1192Add R1191, R1192
Add R1198, R1199
Add R1198, R11992222009/05/02
Add R1198, R1199Add R1198, R1199
Install R1060
Install R1060Install R1060
Add R1197, C967, C966, C968, R1195, R11 96
Add R1197, C967, C966, C968, R1195, R11Add R1197, C967, C966, C968, R1195, R11
Add C978, C979
Add C978, C979Add C978, C979
ion
ionion
96
9696
Rev.Page#
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
Version Change List ( P. I. R. List ) for HW Circuit SI-1>> SI-1b
Reque st
Item Date
01 02 03 04 05 06
3 3
2222009/07/21
009/07/2104HP
009/07/21009/07/21
04
009/07/02
009/07/02009/07/02
05
2222009/07/21
009/07/21 HP
009/07/21009/07/21
07
2222009/07/02
009/07/02 HP
009/07/02009/07/02
19
009/06/30 AAAAdd R1213, D72 for Lid SW issue
009/06/30009/06/30
37
2222009/07/09
009/07/09 HP
009/07/09009/07/09
Reque st
Owner
HP Add
HPHP
HP
HP2222009/07/02
HPHP
HP
HPHP
HP AAAAdd Q91, R1224, C994, C995, C991, C992, C993, C996, Q92, R1223 for CPU S3 power savings issue
HPHP
HP
HP2222009/06/30
HPHP
HP Ch
HPHP
Solution Description
Add C997, R1219, Q87, R1218 for CPU S3 power savings issue
C997, R1219, Q87, R1218 for CPU S3 power savings issue
AddAdd
C997, R1219, Q87, R1218 for CPU S3 power savings issue C997, R1219, Q87, R1218 for CPU S3 power savings issue
Add
Add R1226 for CPU S3 power savings issue
R1226 for CPU S3 power savings issue
AddAdd
R1226 for CPU S3 power savings issue R1226 for CPU S3 power savings issue
Add Q8
Add Q88, Q89 and reserve R1220, R1222 for CPU S3 power savings issue
Add Q8Ad d Q 8
Ch ange C864 from 0.047uF to 0.068uF.
ChCh
8, Q89 and reserve R1220, R1222 for CPU S3 power savings issue
8, Q89 and reserve R1220, R1222 for CPU S3 power savings issue8, Q89 and reserve R1220, R1222 for CPU S3 power savings issue
dd Q91, R1224, C994, C995, C991, C992, C993, C996, Q92, R1223 for CPU S3 power savings issue
dd Q91, R1224, C994, C995, C991, C992, C993, C996, Q92, R1223 for CPU S3 power savings issuedd Q91, R1224, C994, C995, C991, C992, C993, C996, Q92, R1223 for CPU S3 power savings issue
dd R1213, D72 for Lid SW issue
dd R1213, D72 for Lid SW issuedd R1213, D72 for Lid SW issue
ange C864 from 0.047uF to 0.068uF.
ange C864 from 0.047uF to 0.068uF.ange C864 from 0.047uF to 0.068uF.
Rev.Page#
0.5
0.5
0.5
0.5
0.5
0.5
0.5
4 4
Security Classification
Issued Date
THIS SHE ET OF ENG INEE RING DRA WIN G IS THE P ROP RIETA RY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRAD E SEC RET INFO RMATI ON. THIS S HEE T MA Y NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEP ARTM ENT EXCE PT A S AUTHO RIZED BY C OMP AL ELE CTRON ICS, IN C. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY B E USE D B Y O R D ISCLO SE D TO AN Y TH IRD PAR TY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
D
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
Hardware revision (0.3 to 0.5)
LA -490 1 P
E
53 54T u esd ay , Dec ember 15, 2 00 9
1. 0
A
B
C
Version Change List ( P. I. R. List ) for HW Circuit SI-1b>> SI-2
D
E
Item Date
07
01
1 1
02 03 04 05
2222009/07/22
009/07/22
009/07/22009/07/22
11
009/06/30
009/06/30009/06/30
15
2222009/07/23
009/07/23
009/07/23009/07/23
12
2222009/09/03
009/09/03 Compal
009/09/03009/09/03
32
2222009/09/03
009/09/03 Compal
009/09/03009/09/03
Owner
HP
HP Change C72 ~ C75 from 10uF to 20
HPHP
Compal
Compal
CompalCompal
Compal
Compal
CompalCompal
Compal CCCChange JBAT1 Connector.
CompalCompal
Compal Re
CompalCompal
Solution Description
Change C72 ~ C75 from 10uF to 20 uF
Change C72 ~ C75 from 10uF to 20Change C72 ~ C75 from 10uF to 20
Res
Reserve R1215 for CLK gen change
erve R1215 for CLK gen change2222009/06/30
ResRe s
erve R1215 for CLK gen changeerve R1215 for CLK gen change
Add C949 ~ C951 for Compal RF te
Add C949 ~ C951 for Compal RF te am.
Add C949 ~ C951 for Compal RF teAdd C949 ~ C951 for Compal RF te
hange JBAT1 Connector.
hange JBAT1 Connector.hange JBAT1 Connector.
Re serve Q
serve Q
ReR e
serve Qserve Q
uF
uFuF
am.
am.am.
06 07 08 09 10 11 12 13
2 2
Rev.Page#
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
14 15 16 17 18 19 20 21 22 23 24
Reque st
3 3
25 26 27 28 29 30 31
4 4
Security Classification
Issued Date
THIS SHE ET OF ENG INEE RING DRA WIN G IS THE P ROP RIETA RY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRAD E SEC RET INFO RMATI ON. THIS S HEE T MA Y NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEP ARTM ENT EXCE PT A S AUTHO RIZED BY C OMP AL ELE CTRON ICS, IN C. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY B E USE D B Y O R D ISCLO SE D TO AN Y TH IRD PAR TY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
D
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
Hardware revision (0.5 to 0.6)
LA -490 1 P
E
54 54T u esd ay , Dec ember 15, 2 00 9
1. 0
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