How it Works
COMPAL
Loading...
LA-4901P
Schematics
54 pgs1.44 Mb0

COMPAL LA-4901P Schematics

1
A A
2
3
4
5
Compal Confidential
Schematics Document
B B
Intel CLARKSFIELD/ARRANDALE with IBEX PEAK-M core logic
Cartier DIS
C C
LA-4901P
2009-12-01
REV:1.0
D D
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
Cover Sheet
LA -490 1 P
5
1 54Tu e s da y, De ce mbe r 15 , 20 09
1. 0
1
Compal Confidential
File Name : LA-4901P
Thermal Sensor EMC2113
A A
Page 4
Fan Control
Page 4
DP to Docking
2
Page 36
3
Cartier DIS
Mobile
4
5
Accelerometer
LIS302DLTR
Page 34
XDP Conn.
LCD conn
CRT
Page 19
Page 18
CRT to Docking
Page 36
DP conn
Page 18
N10 M-GLM
Page 20,21,22,23
VRAM DDR3-512MB
Page 24,25
PEG X 16
Auburndale / Clarksfield
Socke t-rPGA989
37.5mm*37.5mm
Page 4,5,6,7,8
DMI X4
Dual Channel
SATA4
DDR3-SO-DIMM X 2DDR3 1066/1333MHz 1.5V
BANK 0, 1, 2, 3
E-SATA and USB comb o conn x 1(For I/O)
Page 32
Page 9,10
Clock Generator ICS9LPRS397
Page 4
CK505
Page 11
B B
Express Card 54
PCIE X1 + USB X1
Audio Board
WWAN Card
PCIE X1
Page 28
USB2.0
USB2.0
Intel Ibex Peak M
Azalia
1071pins
SATA0
SATA1
10/100/1000 LAN
Intel Hansville GbE
PHY
Page 26
WLAN Card
WLAN + PCIE X1
Page 28
PCI-E BUS
Richo R5C835
Controller
Page 30
PCI BUS
25mm*27mm
Page 12,13,14,15,16,17
USB x2(Docking) FingerPrinter VFM451
USBx1
USB conn x 3(For I/O) BT Conn USB x 1
USB x1(Camara)
MDC V1.5
Audio CKT
IDT 92HD75
RJ45 CONN
C C
Page 27
1394 port
Smart Card
Modular
SD/MMC Slot
Audio Board
SATA ODD Connector
Modular
Page 32
Page 19
Page 31
Audio Board
Page 12
Page 34
Page 33
daughter board
RJ11
TPA6047A
AMP & Audio Jack
Cable
Audio Board
2.5" SATA HDD Connector
RTC CKT.
Page 12
Power OK CKT.
Page 37
LED
Audio Board
TPM1.2 SLB9635TT
Page 33 page 35
LPC BUS
SMSC KBC 1098
SMSC Super I/O
LPC47N217
Page 36
Page 12
COM 1 LPT
Power On/Off CKT.
D D
Page 31
DC/DC Interface CKT.
Page 38
1
Touch Pad CONN.
TrackPoint CONN.
SPI ROM
8M B
2
Page 31
Page 33
Int.KBD
Page 31Page 31
( Docking ) ( Docking )
Page 34 Page 34
Security Classification
Issued Date
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Page 34
Docking CONN.
(2) PS/ 2 Interfaces (2) USB 2.channels (2) SATA Channels (2) Display Port Channels (1) Se rial Port (1) Pa rallel Port (1) Line In (1) Line Out (1) RJ45 (10/100/1000) (1 ) VGA (1) 2 LAN indicator LED's (1) Power Button (1) I2C interface
Compal Electronics, Inc.
Block Diagram
LA -490 1 P
5
2 54Tu e s da y, De ce mbe r 15 , 20 09
1. 0
1
Voltage Rails
State
S0
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery don't exist
A A
( O MEANS ON X MEANS OFF )
+RTCVCC
power plane
O O O O O O
+B +3VL +0.75V
O O O O O
X
+5VALW +3VALW
O O O O
X X X X
+3VM +1.05VM
O O O O
X X
+1.5V
O
X X X
+5VS +3VS +1.5VS +VGA_CORE +VCCP +CPU_CORE +1.05VS +1.8VS
OO OO
X
X
Symbol Note :
: means Digital Ground
: means Analog Ground
Install below 45 level BOM structure
45@ : means just put it in the BOM of 45 level.
Install below 43 level BOM structure
@ : means just reserve , no build CONN@ : means ME part. VRAM@ : means VRAM strip pin part.
SMBUS Control Table
SOURCE
SMB_EC_CK1 SMB_EC_DA1
SMBCLK SMBDATA
SML0CLK SML0DATA
SML1CLK SML1DATA
SMSC1098
Calpella
Calpella
Calpella
BATT
V
X X X
THERMAL
SODIMM CLK CHIP
XDP G-SENSOR
X
X X
V V
X
X
X X
MINI CARD
V V
X X X
DOCK
X
X
V
X
X X
SENSOR
NIC
X X X
V
X
X X X
V
V
X
X
Security Classification
Issued Date
1
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
Notes List
LA -490 1 P
3 54Tu e s da y, De ce mbe r 15 , 20 09
1. 0
Layout rule 10mil width tr：ace length < 0.5", spacing 20mil
A A
H_ P ECI15
to power; PU to VCCP at power side also
H_ P R OC H OT#46
H_ T HER MTR IP#15 ,20
H_ C P UR ST#
H_ P M_ S Y NC14
H_ C P UP W RGD
H _ C PU P WRG D15
PM _ DR A M_ P WR GD14
from power
VT TP W R GOOD37
B B
BU F _P L T_R ST#15
200 9/0 2/2 4 HP DB-2
VD D PW R G O OD _R
200 9/0 4/1 0 HP DB-3
1
CO M P3
R220 _0402_1%
1 2 1 2 1 2 1 2
T2
R1 6
1 2
0_ 0402_5%
R1 7
1 2
0_ 0402_5%
R1 9
1 2
0_ 0402_5%
R2 0
1 2
0_ 0402_5%
R2 1
1 2
0_ 0402_5%
R2 2
1 2
0_ 0402_5%
R2 4
1 2
0_ 0402_5%
R2 6
1 2
0_ 0402_5%
R3 0
1 2
0_ 0402_5%
R3 1
1 2
1.5K_ 04 02 _1 %
75 0_0402_1%
R1 4 1.5K_ 04 02 _1 %
1 2
R1 5 75 0_0402_1%
1 2
CO M P2
R520 _0402_1%
CO M P1
R749 .9_0402_1% R949 .9_0402_1%
CO M P0
TP _ S KTO CC#
H_ C A TE R R#
H_ P EC I_ISO
H_ P R OC H O T#_D
H_ T HER M TRIP# _R
H_ C P UR S T# _R
H_ P M_ S Y N C_ R
VC C PW R G O OD _1
VC C PW R G O OD _0
VD D PW R G O OD _R
H_ P W RG D _ XDP_RH_ P W RG D _ XDP
PL T _R ST# _R
12
R3 3
JC P U1B
AT23
COMP3
AT24
COMP2
G16
COMP1
AT26
COMP0
AH24
SKTOCC#
AK14
CATERR#
AT15
PECI
AN26
PROCHOT#
AK15
THERMTRIP#
AP26
RESET_OBS#
AL15
PM_SYNC
AN14
VCCPWRGOOD_1
AN27
VCCPWRGOOD_0
AK13
SM_DRAMPWROK
AM15
VTTPWRGOOD
AM26
TAPPWRGOOD
AL14
RSTIN#
IC , AUB _ CFD_rPGA ,R1P0
+1 .5 V
12
R1 22 6 0_ 0402_5%
200 9/0 7/0 2 HP SI-1b
MISC THERMAL
PWR MANAGEMENT
@
VC C P_ 1 . 5 VS PWR GD 37
JTA G M APPING
CLOCKS
DDR3
MISC
JTAG & BPM
2
C O N N @
BCLK
BCLK#
BCLK_ITP
BCLK_ITP#
PEG_CLK
PEG_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
SM_DRAMRST#
SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]
PM_EXT_TS#[0] PM_EXT_TS#[1]
PRDY# PREQ#
TRST#
TDI_M
TDO_M
DBR#
BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]
TCK TMS
TDO
A16 B16
AR30 AT30
E16 D16
A18 A17
F6 AL1
AM1 AN1
AN15 AP15
AT28 AP27
AN28 AP28 AT27
AT29
TDI
AR27 AR29 AP29
AN25
AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23
CL K _ BC LK CL K _ BCL K#
CL K _ C PU_XD P CL K _ C PU_XD P#
CL K_EXP C LK_EX P#
R1 1 0_ 0402_5%
1 2
R1 3 0_ 0402_5%
1 2
SM _ R CO MP0 SM _ R CO MP1 SM _ R CO MP2
PM_ EXTTS# 0 PM_ EXTTS# 1
XD P _PR D Y# XD P _PREQ#
XD P _TC K X DP_ TMS XD P _TR ST#
XD P _TD I XD P _TD O XD P _TD I_ M XD P _TD O_ M
XD P _D BRE SET#
X DP_ BPM#0 X DP_ BPM#1 X DP_ BPM#2 X DP_ BPM#3 X DP_ BPM#4 X DP_ BPM#5 X DP_ BPM#6 X DP_ BPM#7
T3
R1 8 0_ 0402_5%
1 2
C 1
0. 1U _0 40 2_ 16 V4Z
3
R1 10 K_0 40 2_ 5%
PM_ EXTTS# 0
CL K _ CP U_BC LK 15 CL K _ CP U_BC LK# 15
CL K_ EXP 13 CL K_ EXP # 13
from DDR
PM_ EXTTS# 1_ R 9,10
R1 21 9 10 0K_ 04 02 _5 %
X DP_ BPM#0
R1 01 6 0_0402_5%
1 2
R1 01 7 0_0402_5%@
CF G 125 CF G 135 CF G 145 CF G 155
@
X DP_ BPM#1 X DP_ BPM#2 X DP_ BPM#3
+V C CP
1
PM _ PW R BTN# _R12 ,14
2
1 2
R1 01 8 0_0402_5%
1 2
R1 01 9 0_0402_5%@
1 2
R1 02 0 0_0402_5%
1 2
R1 02 1 0_0402_5%@
1 2
R1 02 2 0_0402_5%
1 2
R1 02 3 0_0402_5%@
1 2
H_ C P UP W RGD
H_ P W RG D _ XDP
PM_ EXTTS# 1
SS M3 K7002F_ SC5 9- 3 Q8 7
S
G
2
12
1
@
2
CF G 175 CF G 165
R2 5 1K_ 04 02 _5 %
1 2
1 2
R2 7 0_0 40 2_ 5%
200 8/1 2/1 2 HP
1 2
R3 10 K_0 40 2_ 5%
1 2
+1 .5 V
12
R1 21 8 1K_ 04 02 _5 %
D
13
200 9/0 7/0 2 HP SI-1b
C9 97 47 0P_ 04 02 _5 0V 8J
200 9/0 7/2 1 HP SI-2
XD P _PREQ# XD P _PR D Y#
XD P _BPM#0_R XD P _BPM#1_R
XD P _BPM#2_R XD P _BPM#3_R
X DP_ BPM#4 X DP_ BPM#5
X DP_ BPM#6 X DP_ BPM#7
H_ C P UP W RGD _R PM _ PW R B TN#_R
T11 0 T11 1
XD P _TC K
DR A MR ST # 9,1 0
PC H _ DD R _ RST 5 ,1 5
CPU XDP Connector
JP 1
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
39
PWRGOOD/HOOK0
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
SAMTE_BSH -0 30 -0 1- L- D-A C O N N@
4
PM _ PW R B TN#_R
OBSFN_C0 OBSFN_C1
OBSDATA_C0 OBSDATA_C1
OBSDATA_C2 OBSDATA_C3
OBSFN_D0 OBSFN_D1
OBSDATA_D0 OBSDATA_D1
OBSDATA_D2 OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND1
GND3
GND5
GND7
GND9
GND11
GND13
GND15
TRST#
GND17
R9 09 1K_ 04 02 _5 %@
TD0
TDI
TMS
1 2
200 8/1 0/0 9 HP
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
C F G8 5 C F G9 5
C F G0 5 C F G1 5
C F G2 5 C F G3 5
CF G 10 5 CF G 11 5
C F G4 5 C F G5 5
C F G6 5 C F G7 5
CL K _ C PU_XD P CL K _ C PU_XD P#
XD P _RST#_R XD P _D BRE SET#_R
XD P _TD O XD P _TR ST# XD P _TD I X DP_ TMS
XD P _RST#_R
+V C CP
XD P _TD O
200 9/0 2/2 5 HP DB-2
200 8/1 2/1 2 HP DB-1
+V C CP
1K_ 04 02 _5 %
R2 8
1 2 1 2
R2 9 0_ 0402_5%
1 2
R3 2 0_ 0402_5%
H_ C P UR ST# XD P _D BRE SET#
@
5
200 9/0 2/0 6 HP DB-2
R1 0 51 _0402_5%
1 2
Thi s s hal l pla ce near XDP
200 9/0 4/1 3 Com pal DB-3
+3 VS
12
R2 3 1K_ 04 02 _5 %
XD P _DB RES ET# 12,1 4
PL T_RST# 12,15,2 0, 26 ,2 8, 31 ,33
+V C CP+V C CP
H_ C A TE R R# H_ P R OC H O T#_D H_ C P UR S T# _R
DDR 3 C omp en sat ion Signals
SM _ R CO MP0 SM _ R CO MP1 SM _ R CO MP2
Lay out No te :Pl ease these res ist ors n ear Processor
Pro ces sor P ullups
R3 9 49. 9_ 04 02 _1 %
1 2
R4 2 68_ 04 02 _5 %
1 2
R4 5 68_ 04 02 _5 %@
1 2
R5 2 10 0_0402_1%
1 2
R5 3 24 .9_0402_1%
1 2
R5 4 13 0_0402_1%
1 2
+V C CP
REMOTE Thermal sensor
RE M OT E2+
C 4
22 00P_0 40 2_ 50 V7K
RE M OTE 2-
1
2
1
200 9/0 2/0 6 HP DB-2
Clo se to XDP
XD P _TR ST#
R5 5 51 _0402_5%
1 2
C
Q1
2
B
MMB T3904WH _S OT3 23 -3
E
3 1
Layout Note: place near the hottest spot area for
NB & top SODIMM.
+3 VS
12
R3 5
68 _0402_5%
1
200 9/0 2/0 6 HP DB-2
C 3
0. 1U _0 40 2_ 16 V4Z
H_ T HER MTR IP#15 ,20
200 9/0 2/2 0 HP DB-2 200 9/0 4/1 0 HP DB-3
2
3
1 2
R1 14 1
2
H_ T HER MTRI P#
Security Classification
Issued Date
C C
D D
Thermal Sensor EMC2113-2 with CPU PWM FAN
VG A _ TH E RMD C21
VG A _ TH ER MDA21
1 2
C 2 22 00P_0 40 2_ 50 V7K
200 9/0 1/2 1 HP
10 K_0 40 2_ 5%
TH E RM _S CI#15
R4 8 10 K_0 40 2_ 5%@
1 2
+3 VS
R5 1 0_ 0402_5%
1 2
200 8/1 1/1 7 HP
VG A _ TH E RM DC VG A _ TH E RMD A +3 V S_TH ER FA N _P W M- R AD D R_ SEL
2008/09/15 2009/12/31
U5 4 EMC 21 13 -2 -A X_Q FN 16 _4X4
1
DN
2
DP
3
0.4mA
VDD
4
PWM_IN
5
ADDR_SEL
6
ALERT#
7
SYS_SHDN#
8
SMDATA
Add 0 ohm a nd 0.1u
Compal Secret Data
Deciphered Date
4
GND
17
DP2/DN3 DN2/DP3
TRIP_SET
SHDN_SEL
GND
PWM
TACH
SMCLK
RE M OT E2+
16
RE M OTE 2-
15
R3 8 4.53K_0 40 2_ 1%
14
1 2
200 9/0 2/0 6 HP DB-2
R4 1 10 K_0 40 2_ 5%
13
1 2
12
FA N _P W M _O UT
11
T A C H
10 9
SM B_CL K_ S3 9 ,10,11,13 ,32SM B_D ATA _S39,10,11 ,1 3, 32
R7 94 0_0402_5%
FA N _P W M- R
C8 30
0. 1U _0 40 2_ 16 V4Z
200 9/0 7/2 3 Com pal th ermal team
@
1 2
R4 4 10 K_0 40 2_ 5%
R1 06 1 0_0402_5%
1 2
R4 7 10 K_0 40 2_ 5%
Ins tall
Don 't Ins tall
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
1 2
1
@
2
1 2
Add in th is ma p at 11/24
R10 60
R79 4,R 1061
+3 VS
+3 VS
10/16 HP Add
+5 VS
12
200 9/0 2/0 6 HP DB-2
R1 06 0 10 K_0 40 2_ 5%
EMC 2113EMC 210 3 ( de fault)
R79 4,R 1061
JP 2
C O N N@
1
0.3A
1
2
2
3
3
4
4
5
G5
6
G6
ACE S_85205 -040 01
200 9/0 1/2 0 Com pal HW
R10 60
Compal Electronics, Inc.
ARD/CFD(1/5)-Thermal/XDP
LA -490 1 P
5
FA N _P W M 35
4 54Tu e s da y, De ce mbe r 15 , 20 09
1. 0
1
JC P U1A
DM I _C RX_ PTX _N 014 DM I _C RX_ PTX _N 114 DM I _C RX_ PTX _N 214 DM I _C RX_ PTX _N 314
DM I_ CR X_PTX_ P014 DM I_ CR X_PTX_ P114 DM I_ CR X_PTX_ P214
A A
DM I_ CR X_PTX_ P314 DM I _C TX_ PRX _N 014
DM I _C TX_ PRX _N 114 DM I _C TX_ PRX _N 214 DM I _C TX_ PRX _N 314
DM I_ CTX_P RX_ P014 DM I_ CTX_P RX_ P114 DM I_ CTX_P RX_ P214 DM I_ CTX_P RX_ P314
R5 8 1K_ 04 02 _5 %
B B
C C
1 2
R5 9 1K_ 04 02 _5 %
1 2
R6 2 1K_ 04 02 _5 %
1 2
R6 3 1K_ 04 02 _5 %
1 2
R6 4 1K_ 04 02 _5 %
1 2
A24
DMI_RX#[0]
C23
DMI_RX#[1]
B22
DMI_RX#[2]
A21
DMI_RX#[3]
B24
DMI_RX[0]
D23
DMI_RX[1]
B23
DMI_RX[2]
A22
DMI_RX[3]
D24
DMI_TX#[0]
G24
DMI_TX#[1]
F23
DMI_TX#[2]
H23
DMI_TX#[3]
D25
DMI_TX[0]
F24
DMI_TX[1]
E23
DMI_TX[2]
G23
DMI_TX[3]
E22
FDI_TX#[0]
D21
FDI_TX#[1]
D19
FDI_TX#[2]
D18
FDI_TX#[3]
G21
FDI_TX#[4]
E19
FDI_TX#[5]
F21
FDI_TX#[6]
G18
FDI_TX#[7]
D22
FDI_TX[0]
C21
FDI_TX[1]
D20
FDI_TX[2]
C18
FDI_TX[3]
G22
FDI_TX[4]
E20
FDI_TX[5]
F20
FDI_TX[6]
G19
FDI_TX[7]
F17
FDI_FSYNC[0]
E17
FDI_FSYNC[1]
C17
FDI_INT
F18
FDI_LSYNC[0]
D17
FDI_LSYNC[1]
IC , AUB _ CFD _r PG A,R1P 0
DMI Intel(R) FDI
PCI EXPRESS -- GRAPHICS
C O N N @
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS PEG_RX#[0]
PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]
PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]
PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]
PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]
PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]
PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]
B26 A26 B27 A25
K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31
J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30
L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26
L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25
CFG Straps for PROCESSOR
C F G 0
R6 7 3.01K_0 40 2_ 1%@
1 2
PCI -Ex pre ss Co nfi gur ati on Select
1: Sin gle PEG 0: Bif urc at ion enabled
CFG0
Not ap pli ca ble fo r C lar ksf ie ld Processor
R6 9 3.01K_0 40 2_ 1%
C F G 3
C F G 4
D D
1 2
CFG 3-P CI Ex pre ss Sta tic Lane Reversal
1: Nor mal O peration 0: Lan e N um ber s Reversed
CFG3
15 -> 0, 14 -> 1, .....
R7 0 3.01K_0 40 2_ 1%@
1 2
CFG 4-D isp la y P ort Presence
1: Dis abl ed ; N o P hys ica l Display Port att ach ed to Em bed ded Di splay Port
CFG4
0: Ena ble d; An ex ter nal Display Port dev ice is c onn ect ed to the Embedded Dis pla y Port
2
EX P _I CO MPI
EX P _R BI AS PC I E_ CR X_GTX _N0
PC I E_ CR X_GTX _N1 PC I E_ CR X_GTX _N2 PC I E_ CR X_GTX _N3 PC I E_ CR X_GTX _N4 PC I E_ CR X_GTX _N5 PC I E_ CR X_GTX _N6 PC I E_ CR X_GTX _N7 PC I E_ CR X_GTX _N8 PC I E_ CR X_GTX _N9 PC I E_ CR X_GTX _N10 PC I E_ CR X_GTX _N11 PC I E_ CR X_GTX _N12 PC I E_ CR X_GTX _N13 PC I E_ CR X_GTX _N14 PC I E_ CR X_GTX _N15
PC I E_ CRX _G TX_ P0 PC I E_ CRX _G TX_ P1 PC I E_ CRX _G TX_ P2 PC I E_ CRX _G TX_ P3 PC I E_ CRX _G TX_ P4 PC I E_ CRX _G TX_ P5 PC I E_ CRX _G TX_ P6 PC I E_ CRX _G TX_ P7 PC I E_ CRX _G TX_ P8 PC I E_ CRX _G TX_ P9 PC I E_ CRX _G TX_ P1 0 PC I E_ CRX _G TX_ P1 1 PC I E_ CRX _G TX_ P1 2 PC I E_ CRX _G TX_ P1 3 PC I E_ CRX _G TX_ P1 4 PC I E_ CRX _G TX_ P1 5
PC I E _C TX_ GR X_C_N 0 PC I E _C TX_ GR X_C_N 1 PC I E _C TX_ GR X_C_N 2 PC I E _C TX_ GR X_C_N 3 PC I E _C TX_ GR X_C_N 4 PC I E _C TX_ GR X_C_N 5 PC I E _C TX_ GR X_C_N 6 PC I E _C TX_ GR X_C_N 7 PC I E _C TX_ GR X_C_N 8 PC I E _C TX_ GR X_C_N 9 PC I E_ CT X_G RX _C_N1 0 PC I E_ CT X_G RX _C_N1 1 PC I E_ CT X_G RX _C_N1 2 PC I E_ CT X_G RX _C_N1 3 PC I E_ CT X_G RX _C_N1 4 PC I E_ CT X_G RX _C_N1 5
PC I E_ CT X_G RX _C_P0 PC I E_ CT X_G RX _C_P1 PC I E_ CT X_G RX _C_P2 PC I E_ CT X_G RX _C_P3 PC I E_ CT X_G RX _C_P4 PC I E_ CT X_G RX _C_P5 PC I E_ CT X_G RX _C_P6 PC I E_ CT X_G RX _C_P7 PC I E_ CT X_G RX _C_P8 PC I E_ CT X_G RX _C_P9 PC I E_ CT X_G RX _C_P1 0 PC I E_ CT X_G RX _C_P1 1 PC I E_ CT X_G RX _C_P1 2 PC I E_ CT X_G RX _C_P1 3 PC I E_ CT X_G RX _C_P1 4 PC I E_ CT X_G RX _C_P1 5
R5 6 49 .9 _0 40 2_ 1%
1 2
R5 7 75 0_ 04 02 _1%
1 2
Layout rule tra：ce length < 0.5"
PC I E_ CRX _G TX_ N[ 0..15 ] 20
PC I E_ CRX _G TX_ P[0.. 15 ] 20
C 5 0.1U_ 04 02 _1 0V 7K
1 2
C 6 0.1U_ 04 02 _1 0V 7K
1 2
C 7 0.1U_ 04 02 _1 0V 7K
1 2
C 8 0.1U_ 04 02 _1 0V 7K
1 2
C 9 0.1U_ 04 02 _1 0V 7K
1 2
C1 0 0.1U_ 04 02 _1 0V 7K
1 2
C1 1 0.1U_ 04 02 _1 0V 7K
1 2
C1 2 0.1U_ 04 02 _1 0V 7K
1 2
C1 3 0.1U_ 04 02 _1 0V 7K
1 2
C1 4 0.1U_ 04 02 _1 0V 7K
1 2
C1 5 0.1U_ 04 02 _1 0V 7K
1 2
C1 6 0.1U_ 04 02 _1 0V 7K
1 2
C1 7 0.1U_ 04 02 _1 0V 7K
1 2
C1 8 0.1U_ 04 02 _1 0V 7K
1 2
C1 9 0.1U_ 04 02 _1 0V 7K
1 2
C2 0 0.1U_ 04 02 _1 0V 7K
1 2
C2 1 0.1U_ 04 02 _1 0V 7K
1 2
C2 2 0.1U_ 04 02 _1 0V 7K
1 2
C2 3 0.1U_ 04 02 _1 0V 7K
1 2
C2 4 0.1U_ 04 02 _1 0V 7K
1 2
C2 5 0.1U_ 04 02 _1 0V 7K
1 2
C2 6 0.1U_ 04 02 _1 0V 7K
1 2
C2 7 0.1U_ 04 02 _1 0V 7K
1 2
C2 8 0.1U_ 04 02 _1 0V 7K
1 2
C2 9 0.1U_ 04 02 _1 0V 7K
1 2
C3 0 0.1U_ 04 02 _1 0V 7K
1 2
C3 1 0.1U_ 04 02 _1 0V 7K
1 2
C3 2 0.1U_ 04 02 _1 0V 7K
1 2
C3 3 0.1U_ 04 02 _1 0V 7K
1 2
C3 4 0.1U_ 04 02 _1 0V 7K
1 2
C3 5 0.1U_ 04 02 _1 0V 7K
1 2
C3 6 0.1U_ 04 02 _1 0V 7K
1 2
C F G 7
R6 8 3.01K_0 40 2_ 1%@
1 2
Onl y t emp or ary fo r e arl y C FD sa mples (rPGA/BGA)
PC I E_ CT X_G RX _N0 PC I E_ CT X_G RX _N1 PC I E_ CT X_G RX _N2 PC I E_ CT X_G RX _N3 PC I E_ CT X_G RX _N4 PC I E_ CT X_G RX _N5 PC I E_ CT X_G RX _N6 PC I E_ CT X_G RX _N7 PC I E_ CT X_G RX _N8 PC I E_ CT X_G RX _N9 PC I E_ CT X_G RX _N10 PC I E_ CT X_G RX _N11 PC I E_ CT X_G RX _N12 PC I E_ CT X_G RX _N13 PC I E_ CT X_G RX _N14 PC I E_ CT X_G RX _N15
PC I E_ CTX_GRX_ P0 PC I E_ CTX_GRX_ P1 PC I E_ CTX_GRX_ P2 PC I E_ CTX_GRX_ P3 PC I E_ CTX_GRX_ P4 PC I E_ CTX_GRX_ P5 PC I E_ CTX_GRX_ P6 PC I E_ CTX_GRX_ P7 PC I E_ CTX_GRX_ P8 PC I E_ CTX_GRX_ P9 PC I E_ CTX_GRX_ P1 0 PC I E_ CTX_GRX_ P1 1 PC I E_ CTX_GRX_ P1 2 PC I E_ CTX_GRX_ P1 3 PC I E_ CTX_GRX_ P1 4 PC I E_ CTX_GRX_ P1 5
3
+V _ DDR _ C PU _R EF0
+V _ DDR _ C PU _R EF1
200 9/0 7/2 1 HP SI-2
PC H _ DD R _ RST4,15
PC I E_ CTX_GRX_ N[ 0..15 ] 20
PC IE _C TX_ GR X_P [0 ..15] 20
Q88 AP2302GN_SO T23
D
S
1 3
G
2
D
S
1 3
AP 23 02 GN _S OT2 3 Q8 9
G
2
10 0K_ 04 02 _5%
10 0K_ 04 02 _5%
C F G04 C F G14 C F G24 C F G34 C F G44 C F G54 C F G64 C F G74 C F G84 C F G94 CF G 1 04 CF G 1 14 CF G 1 24 CF G 1 34 CF G 1 44 CF G 1 54 CF G 1 64 CF G 1 74
R6 5 0_ 0402_5%@
1 2
R6 6 0_ 0402_5%@
1 2
R1 22 0
R1 22 2
4
C F G 0 C F G 1 C F G 2 C F G 3 C F G 4 C F G 5 C F G 6 C F G 7 C F G 8 C F G 9 CF G 1 0 CF G 1 1 CF G 1 2 CF G 1 3 CF G 1 4 CF G 1 5 CF G 1 6 CF G 1 7 CF G 1 8
JC P U1E
AP25
RSVD1
AL25
RSVD2
AL24
RSVD3
AL22
RSVD4
AJ33
RSVD5
AG9
RSVD6
M27
RSVD7
L28
RSVD8
J17
SA_DIMM_VREF
H17
SB_DIMM_VREF
G25
RSVD11
G17
RSVD12
E31
RSVD13
E30
RSVD14
AM30
CFG[0]
AM28
CFG[1]
AP31
CFG[2]
AL32
CFG[3]
AL30
CFG[4]
AM31
CFG[5]
AN29
CFG[6]
AM32
CFG[7]
AK32
CFG[8]
AK31
CFG[9]
AK28
CFG[10]
AJ28
CFG[11]
AN30
CFG[12]
AN32
CFG[13]
AJ32
CFG[14]
AJ29
CFG[15]
AJ30
CFG[16]
AK30
CFG[17]
H16
RSVD_TP_86
B19
RSVD15
A19
RSVD16
A20
RSVD17
B20
RSVD18
U9
RSVD19
T9
RSVD20
AC9
RSVD21
AB9
RSVD22
C1
RSVD_NCTF_23
A3
RSVD_NCTF_24
J29
RSVD26
J28
RSVD27
A34
RSVD_NCTF_28
A33
RSVD_NCTF_29
C35
RSVD_NCTF_30
B35
RSVD_NCTF_31
IC , AUB _ CFD_rPGA ,R1P0
RESERVED
12
@
12
@
T22
C O N N@
RSVD32 RSVD33
RSVD34 RSVD35
RSVD36
RSVD_NCTF_37
RSVD38 RSVD39
RSVD_NCTF_40 RSVD_NCTF_41
RSVD_NCTF_42 RSVD_NCTF_43
RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52
RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57
RSVD58
RSVD_TP_59 RSVD_TP_60
RSVD62
RSVD63
RSVD64
RSVD65
RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75
RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85
AJ13 AJ12
AH25 AK26
AL26 AR2
AJ26 AJ27
AP1 AT2
AT3 AR1
AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32
E15 F15 A2
KEY
D15 C15
R6 0 0_ 0402_5%@
1 2
AJ15
R6 1 0_ 0402_5%@
AH15
1 2
AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3
V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9
AP34
VSS
5
200 9/0 2/1 9 HP DB-2
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
ARD/CFD(2/5)-DMI/PEG/FDI
LA- 4901P
5
5 54Tu e s da y, De ce mbe r 15 , 20 09
1. 0
1
2
3
4
5
AR10 AT10
J C PU1 D
B5
SB_DQ[0]
A5
SB_DQ[1]
C3
SB_DQ[2]
B3
SB_DQ[3]
E4
SB_DQ[4]
A6
SB_DQ[5]
A4
SB_DQ[6]
C4
SB_DQ[7]
D1
SB_DQ[8]
D2
SB_DQ[9]
F2
SB_DQ[10]
F1
SB_DQ[11]
C2
SB_DQ[12]
F5
SB_DQ[13]
F3
SB_DQ[14]
G4
SB_DQ[15]
H6
SB_DQ[16]
G2
SB_DQ[17]
J6
SB_DQ[18]
J3
SB_DQ[19]
G1
SB_DQ[20]
G5
SB_DQ[21]
J2
SB_DQ[22]
J1
SB_DQ[23]
J5
SB_DQ[24]
K2
SB_DQ[25]
L3
SB_DQ[26]
M1
SB_DQ[27]
K5
SB_DQ[28]
K4
SB_DQ[29]
M4
SB_DQ[30]
N5
SB_DQ[31]
AF3
SB_DQ[32]
AG1
SB_DQ[33]
AJ3
SB_DQ[34]
AK1
SB_DQ[35]
AG4
SB_DQ[36]
AG3
SB_DQ[37]
AJ4
SB_DQ[38]
AH4
SB_DQ[39]
AK3
SB_DQ[40]
AK4
SB_DQ[41]
AM6
SB_DQ[42]
AN2
SB_DQ[43]
AK5
SB_DQ[44]
AK2
SB_DQ[45]
AM4
SB_DQ[46]
AM3
SB_DQ[47]
AP3
SB_DQ[48]
AN5
SB_DQ[49]
AT4
SB_DQ[50]
AN6
SB_DQ[51]
AN4
SB_DQ[52]
AN3
SB_DQ[53]
AT5
SB_DQ[54]
AT6
SB_DQ[55]
AN7
SB_DQ[56]
AP6
SB_DQ[57]
AP8
SB_DQ[58]
AT9
SB_DQ[59]
AT7
SB_DQ[60]
AP9
SB_DQ[61] SB_DQ[62] SB_DQ[63]
AB1
SB_BS[0]
W5
SB_BS[1]
R7
SB_BS[2]
AC5
SB_CAS#
Y7
SB_RAS#
AC6
SB_WE#
DDR SYSTEM MEMORY - B
J C PU1 C
A A
DD R _ A_ D [0..6 3]9
B B
C C
DD R _ A_ BS09 DD R _ A_ BS19 DD R _ A_ BS29
DD R _ A_ C AS#9 DD R _ A_ R AS#9 DD R _ A_ W E#9
DD R _ A _D 0 DD R _ A _D 1 DD R _ A _D 2 DD R _ A _D 3 DD R _ A _D 4 DD R _ A _D 5 DD R _ A _D 6 DD R _ A _D 7 DD R _ A _D 8 DD R _ A _D 9 DD R _ A _D 10 DD R _ A _D 11 DD R _ A _D 12 DD R _ A _D 13 DD R _ A _D 14 DD R _ A _D 15 DD R _ A _D 16 DD R _ A _D 17 DD R _ A _D 18 DD R _ A _D 19 DD R _ A _D 20 DD R _ A _D 21 DD R _ A _D 22 DD R _ A _D 23 DD R _ A _D 24 DD R _ A _D 25 DD R _ A _D 26 DD R _ A _D 27 DD R _ A _D 28 DD R _ A _D 29 DD R _ A _D 30 DD R _ A _D 31 DD R _ A _D 32 DD R _ A _D 33 DD R _ A _D 34 DD R _ A _D 35 DD R _ A _D 36 DD R _ A _D 37 DD R _ A _D 38 DD R _ A _D 39 DD R _ A _D 40 DD R _ A _D 41 DD R _ A _D 42 DD R _ A _D 43 DD R _ A _D 44 DD R _ A _D 45 DD R _ A _D 46 DD R _ A _D 47 DD R _ A _D 48 DD R _ A _D 49 DD R _ A _D 50 DD R _ A _D 51 DD R _ A _D 52 DD R _ A _D 53 DD R _ A _D 54 DD R _ A _D 55 DD R _ A _D 56 DD R _ A _D 57 DD R _ A _D 58 DD R _ A _D 59 DD R _ A _D 60 DD R _ A _D 61 DD R _ A _D 62 DD R _ A _D 63
AJ10 AL10
AK12
AK11
AM10 AR11
AL11
AT11 AP12 AM12 AN12 AM13
AT14
AT12
AL13 AR14 AP14
A10
SA_DQ[0]
C10
SA_DQ[1]
C7
SA_DQ[2]
A7
SA_DQ[3]
B10
SA_DQ[4]
D10
SA_DQ[5]
E10
SA_DQ[6]
A8
SA_DQ[7]
D8
SA_DQ[8]
F10
SA_DQ[9]
E6
SA_DQ[10]
F7
SA_DQ[11]
E9
SA_DQ[12]
B7
SA_DQ[13]
E7
SA_DQ[14]
C6
SA_DQ[15]
H10
SA_DQ[16]
G8
SA_DQ[17]
K7
SA_DQ[18]
J8
SA_DQ[19]
G7
SA_DQ[20]
G10
SA_DQ[21]
J7
SA_DQ[22]
J10
SA_DQ[23]
L7
SA_DQ[24]
M6
SA_DQ[25]
M8
SA_DQ[26]
L9
SA_DQ[27]
L6
SA_DQ[28]
K8
SA_DQ[29]
N8
SA_DQ[30]
P9
SA_DQ[31]
AH5
SA_DQ[32]
AF5
SA_DQ[33]
AK6
SA_DQ[34]
AK7
SA_DQ[35]
AF6
SA_DQ[36]
AG5
SA_DQ[37]
AJ7
SA_DQ[38]
AJ6
SA_DQ[39] SA_DQ[40]
AJ9
SA_DQ[41] SA_DQ[42] SA_DQ[43]
AK8
SA_DQ[44]
AL7
SA_DQ[45] SA_DQ[46]
AL8
SA_DQ[47]
AN8
SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51]
AM9
SA_DQ[52]
AN9
SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]
AC3
SA_BS[0]
AB2
SA_BS[1]
U7
SA_BS[2]
AE1
SA_CAS#
AB3
SA_RAS#
AE9
SA_WE#
C O N N@
AA6
SA_CK[0]
AA7
SA_CK#[0]
P7
SA_CKE[0]
Y6
SA_CK[1]
Y5
SA_CK#[1]
P6
SA_CKE[1]
AE2
SA_CS#[0]
AE8
SA_CS#[1]
AD8
SA_ODT[0]
AF9
SA_ODT[1]
DD R _ A _D M0
B9
SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]
SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]
SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]
DDR SYSTEM MEMORY A
SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]
SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]
D7 H7 M7 AG6 AM7 AN10 AN13
C9 F8 J9 N9 AH7 AK9 AP11 AT13
C8 F9 H9 M9 AH8 AK10 AN11 AR13
Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9
DD R _ A _D M1 DD R _ A _D M2 DD R _ A _D M3 DD R _ A _D M4 DD R _ A _D M5 DD R _ A _D M6 DD R _ A _D M7
DD R _ A_ DQS#0 DD R _ A_ DQS#1 DD R _ A_ DQS#2 DD R _ A_ DQS#3 DD R _ A_ DQS#4 DD R _ A_ DQS#5 DD R _ A_ DQS#6 DD R _ A_ DQS#7
DD R _ A_ DQS0 DD R _ A_ DQS1 DD R _ A_ DQS2 DD R _ A_ DQS3 DD R _ A_ DQS4 DD R _ A_ DQS5 DD R _ A_ DQS6 DD R _ A_ DQS7
DD R _ A _MA 0 DD R _ A _MA 1 DD R _ A _MA 2 DD R _ A _MA 3 DD R _ A _MA 4 DD R _ A _MA 5 DD R _ A _MA 6 DD R _ A _MA 7 DD R _ A _MA 8 DD R _ A _MA 9 DD R _ A_ MA1 0 DD R _ A_ MA1 1 DD R _ A_ MA1 2 DD R _ A_ MA1 3 DD R _ A_ MA1 4 DD R _ A_ MA1 5
M_ C L K_ DD R0 9 M_ C L K_ DD R#0 9 DD R _ CK E 0 _DIMMA 9
M_ C L K_ DD R1 9 M_ C L K_ DD R#1 9 DD R _ CK E 1 _DIMMA 9
DD R _ CS 0 _D IMMA# 9 DD R _ CS 1 _D IMMA# 9
M_ ODT0 9 M_ ODT1 9
DD R _ A_ D M[0 .. 7] 9
DD R _ A_ D QS# [0 .. 7] 9
DD R _ A_ D QS [0 ..7] 9
DD R _ A_ MA[ 0. .1 5] 9
DD R _ B_ D [0..6 3]10
DD R _ B_ BS010 DD R _ B_ BS110 DD R _ B_ BS210
DD R _ B_ C AS #10 DD R _ B_ R AS #10 DD R _ B_ W E#10
DD R _ B _D 0 DD R _ B _D 1 DD R _ B _D 2 DD R _ B _D 3 DD R _ B _D 4 DD R _ B _D 5 DD R _ B _D 6 DD R _ B _D 7 DD R _ B _D 8 DD R _ B _D 9 DD R _ B _D 10 DD R _ B _D 11 DD R _ B _D 12 DD R _ B _D 13 DD R _ B _D 14 DD R _ B _D 15 DD R _ B _D 16 DD R _ B _D 17 DD R _ B _D 18 DD R _ B _D 19 DD R _ B _D 20 DD R _ B _D 21 DD R _ B _D 22 DD R _ B _D 23 DD R _ B _D 24 DD R _ B _D 25 DD R _ B _D 26 DD R _ B _D 27 DD R _ B _D 28 DD R _ B _D 29 DD R _ B _D 30 DD R _ B _D 31 DD R _ B _D 32 DD R _ B _D 33 DD R _ B _D 34 DD R _ B _D 35 DD R _ B _D 36 DD R _ B _D 37 DD R _ B _D 38 DD R _ B _D 39 DD R _ B _D 40 DD R _ B _D 41 DD R _ B _D 42 DD R _ B _D 43 DD R _ B _D 44 DD R _ B _D 45 DD R _ B _D 46 DD R _ B _D 47 DD R _ B _D 48 DD R _ B _D 49 DD R _ B _D 50 DD R _ B _D 51 DD R _ B _D 52 DD R _ B _D 53 DD R _ B _D 54 DD R _ B _D 55 DD R _ B _D 56 DD R _ B _D 57 DD R _ B _D 58 DD R _ B _D 59 DD R _ B _D 60 DD R _ B _D 61 DD R _ B _D 62 DD R _ B _D 63
C O N N@
SB_CK[0] SB_CK#[0] SB_CKE[0]
SB_CK[1] SB_CK#[1] SB_CKE[1]
SB_CS#[0] SB_CS#[1]
SB_ODT[0] SB_ODT[1]
SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]
SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]
SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]
W8 W9 M3
V7 V6 M2
AB8 AD6
AC7 AD1
D4 E1 H3 K1 AH1 AL2 AR4 AT8
D5 F4 J4 L4 AH2 AL4 AR5 AR8
C5 E3 H4 M5 AG2 AL5 AP5 AR7
U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1
DD R _ B _D M0 DD R _ B _D M1 DD R _ B _D M2 DD R _ B _D M3 DD R _ B _D M4 DD R _ B _D M5 DD R _ B _D M6 DD R _ B _D M7
DD R _ B_ DQS#0 DD R _ B_ DQS#1 DD R _ B_ DQS#2 DD R _ B_ DQS#3 DD R _ B_ DQS#4 DD R _ B_ DQS#5 DD R _ B_ DQS#6 DD R _ B_ DQS#7
DD R _ B_ DQS0 DD R _ B_ DQS1 DD R _ B_ DQS2 DD R _ B_ DQS3 DD R _ B_ DQS4 DD R _ B_ DQS5 DD R _ B_ DQS6 DD R _ B_ DQS7
DD R _ B _MA 0 DD R _ B _MA 1 DD R _ B _MA 2 DD R _ B _MA 3 DD R _ B _MA 4 DD R _ B _MA 5 DD R _ B _MA 6 DD R _ B _MA 7 DD R _ B _MA 8 DD R _ B _MA 9 DD R _ B_ MA1 0 DD R _ B_ MA1 1 DD R _ B_ MA1 2 DD R _ B_ MA1 3 DD R _ B_ MA1 4 DD R _ B_ MA1 5
M_ C L K_ DD R2 10 M_ C L K_ DD R#2 10 DD R _ CK E 2 _DIMMB 10
M_ C L K_ DD R3 10 M_ C L K_ DD R#3 10 DD R _ CK E 3 _DIMMB 10
DD R _ CS 2 _D IMMB# 10 DD R _ CS 3 _D IMMB# 10
M_ ODT2 10 M_ ODT3 10
DD R _ B_ D M[0 .. 7] 10
DD R _ B_ D QS# [0 .. 7] 10
DD R _ B_ D QS [0 ..7] 10
DD R _ B_ MA[ 0. .1 5] 10
IC , AUB _ CFD _r PG A,R1P 0
IC , AUB _ CFD _r PG A,R1P 0
D D
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
ARD/CFD(3/5)-DDR3
LA -490 1 P
5
6 54Tu e s da y, De ce mbe r 15 , 20 09
1. 0
1
+C P U_C ORE
J C PU1 F
C O N N @
45W
52A
AG35
A A
B B
C C
D D
VCC1
AG34
VCC2
AG33
VCC3
AG32
VCC4
AG31
VCC5
AG30
VCC6
AG29
VCC7
AG28
VCC8
AG27
VCC9
AG26
VCC10
AF35
VCC11
AF34
VCC12
AF33
VCC13
AF32
VCC14
AF31
VCC15
AF30
VCC16
AF29
VCC17
AF28
VCC18
AF27
VCC19
AF26
VCC20
AD35
VCC21
AD34
VCC22
AD33
VCC23
AD32
VCC24
AD31
VCC25
AD30
VCC26
AD29
VCC27
AD28
VCC28
AD27
VCC29
AD26
VCC30
AC35
VCC31
AC34
VCC32
AC33
VCC33
AC32
VCC34
AC31
VCC35
AC30
VCC36
AC29
VCC37
AC28
VCC38
AC27
VCC39
AC26
VCC40
AA35
VCC41
AA34
VCC42
AA33
VCC43
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
IC , AUB _ CFD _r PG A,R1P 0
CPU CORE SUPPLY
POWER
1.1V RAIL POWER
CPU VIDS
SENSE LINES
18A
VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8
VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32
VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44
PSI#
VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]
PROC_DPRSLPVR
VTT_SELECT
ISENSE
VCC_SENSE VSS_SENSE
VTT_SENSE
VSS_SENSE_VTT
AH14 AH12 AH11 AH10
1 J14 J13 H14
2
H12 G14 G13 G12 G11 F14 F13
1 F12 F11 E14
2
E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11
AF10 AE10 AC10 AB10
1 Y10 W10 U10
2
T10 J12 J11 J16 J15
AN33
H_ V I D0
AK35
H_ V I D1
AK33
H_ V I D2
AK34
H_ V I D3
AL35
H_ V I D4
AL33
H_ V I D5
AM33
H_ V I D6
AM35
PM _ DP R S LP VR_ R
AM34
G15
H_VTTVID1 = Low, 1.1V H_VTTVID1 = High, 1.05V
AN35
R7 5 0_ 0402_5%
1 2
AJ34 AJ35
1 2
R7 6 0_ 0402_5%
B15 A15
Close to CPU
VC C SE N SE VS S SE N SE
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C3 8
C3 7
1
2
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C4 5
C4 6
1
2
+V C CP
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C5 7
C5 6
1
2
1 2
R7 4 0_ 0402_5%
1 2
R7 7 10 0_0402_1%
1 2
R7 8 10 0_0402_1%
+V C CP
1
2
1
2
PS I# 46 H_ V I D[0 .. 6] 46
H_ V TTV ID1 43
IM V P_ IMO N 46
VT T_ SENSE 43 VS S _S ENSE_ VTT 43
22 U_0805_6.3V 6M
C4 0
22 U_0805_6.3V 6M
C4 8
VC C SE N SE VS S SE N SE
2
+C P U_C ORE
PR O C _D P R SL PVR 46
VC C SE N SE 46 VS S SE N SE 46
+V C CP
C4 1
@
CPU
3
+C P U_C ORE
47 P_0 40 2_ 50 V8J
1
2
47 P_0 40 2_ 50 V8J
47 P_0 40 2_ 50 V8J
C4 2
1
@
2
47 P_0 40 2_ 50 V8J
C4 3
C4 4
1
1
@
@
2
2
47 P_0 40 2_ 50 V8J
47 P_0 40 2_ 50 V8J
C6 0
C5 9
1
1
@
@
2
2
C6 1
1
@
2
47 P_0 40 2_ 50 V8J
C6 2
1
@
2
200 9/0 7/2 2 HP SI-2
47 P_0 40 2_ 50 V8J
+V C CP
10 U_0805_6.3V 6M
22 U_0805_6.3V 6M
C6 8
1
2
+V C CP
1
2
C6 9
1
2
22 U_0805_6.3V 6M
22 U_0805_6.3V 6M
C7 4
C7 5
1
2
JC P U1G
AT21
VAXG1
AT19
VAXG2
AT18
VAXG3
AT16
VAXG4
AR21
VAXG5
AR19
VAXG6
AR18
VAXG7
AR16
VAXG8
AP21
VAXG9
AP19
VAXG10
AP18
VAXG11
AP16
VAXG12
AN21
VAXG13
AN19
VAXG14
AN18
VAXG15
AN16
VAXG16
AM21
VAXG17
AM19
VAXG18
AM18
VAXG19
AM16
VAXG20
AL21
VAXG21
AL19
VAXG22
AL18
VAXG23
AL16
VAXG24
AK21
VAXG25
AK19
VAXG26
AK18
VAXG27
AK16
VAXG28
AJ21
VAXG29
AJ19
VAXG30
AJ18
VAXG31
AJ16
VAXG32
AH21
VAXG33
AH19
VAXG34
AH18
VAXG35
AH16
VAXG36
J24
VTT1_45
J23
VTT1_46
H25
VTT1_47
K26
VTT1_48
J27
VTT1_49
J26
VTT1_50
J25
VTT1_51
H27
VTT1_52
G28
VTT1_53
G27
VTT1_54
G26
VTT1_55
F26
VTT1_56
E26
VTT1_57
E25
VTT1_58
IC , AUB _ CFD_rPGA ,R1P0
4
C O N N @
GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]
GFX_VR_EN
GFX_IMON
AR22 AT22
AM22 AP22 AN22 AP23 AM23 AP24 AN24
AR25 AT25
R7 1 1K_ 04 02 _5 %
AM24
15A
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
GRAPHICS
GFX_DPRSLPVR
GRAPHICS VIDs
AJ1
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8
6A
FDI PEG & DMI
POWER
1.1A
VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18
DDR3 - 1.5V RAILS
VTT0_59 VTT0_60 VTT0_61 VTT0_62
VTT1_63 VTT1_64 VTT1_65
1.1V1.8V
VTT1_66 VTT1_67 VTT1_68
VCCPLL1 VCCPLL2 VCCPLL3
1U _0 60 3_ 10 V4 Z
AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1
P10 N10 L10 K10
J22 J20 J18 H21 H20 H19
L26 L27 M26
C5 0
1
2
33 0 U _D 2_ 2V Y_R 7M
C6 3
1
+
2
1U _0 60 3_ 10 V4 Z
C7 8
1
1
2
2
5
12
+1 . 5 V_ C PU_ VD DQ
200 9/0 7/0 2 HP SI-2
1U _0 60 3_ 10 V4 Z
1U _0 60 3_ 10 V4 Z
1
2
10 U_0805_6.3V 6M
1
2
1U _0 60 3_ 10 V4 Z
C7 9
1
2
1U _0 60 3_ 10 V4 Z
1U _0 60 3_ 10 V4 Z
C5 1
C5 2
1
2
10 U_0805_6.3V 6M
C6 5
C6 4
1
2
+V C CP
22 U_0805_6.3V 6M
C7 0
1
2
2. 2 U_ 06 03 _6 .3V4Z C8 0
1
2
C5 4
C5 3
1
1
2
2
22 U_0805_6.3V 6M
C7 1
1
2
+V C CP
10 U_0805_6.3V 6M
C7 7
1
2
+1 .8 VS
4. 7U _0 60 3_ 6. 3V6K
10 U_0805_6.3V 6M
C8 2
C8 1
1
2
+1.5V to +1.5V_CPU_VDDQ Transfer
SIS 40 6DN-T1- GE3_PAK1212-8-5
Q9 1
5
C9 94
0.1U_ 04 02 _1 0V 6K R1 22 4
1
1 2
0_ 0402_5%
2
R U NO N
4
+1 . 5 V_ C PU_ VD DQ+1 .5 V
1 2 3
R U N O N 38
200 9/0 7/0 2 HP SI-1b200 9/0 7/2 1 HP SI-2
C9 91 0.1U_ 04 02 _1 0V 6K
1 2
C9 92 0.1U_ 04 02 _1 0V 6K
C9 95
0.1U_ 04 02 _1 0V 6K
1
2
Sti ch CAP b etw een 1. 5V and 1 .5V-CPU_VDDQ
1 2
C9 93 0.1U_ 04 02 _1 0V 6K
1 2
C9 96 0.1U_ 04 02 _1 0V 6K
1 2
+1 . 5 V_ C PU_ VD DQ+1 .5 V
SL P_S338
+1 . 5 V_ C PU_ VD DQ
S LP_ S3
2
G
12
R1 22 3 51 0_0402_5%
13
D
Q92 SS M3 K7002F_ SC5 9- 3
S
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
ARD/CFD(4/5)-PWR
LA -490 1 P
5
7 54Tu e s da y, De ce mbe r 15 , 20 09
1. 0
1
J C PU1 H
AT20
VSS1
AT17
VSS2
AR31
VSS3
AR28
VSS4
AR26
VSS5
AR24
VSS6
AR23
VSS7
AR20
VSS8
AR17
A A
B B
C C
VSS9
AR15
VSS10
AR12
VSS11
AR9
VSS12
AR6
VSS13
AR3
VSS14
AP20
VSS15
AP17
VSS16
AP13
VSS17
AP10
VSS18
AP7
VSS19
AP4
VSS20
AP2
VSS21
AN34
VSS22
AN31
VSS23
AN23
VSS24
AN20
VSS25
AN17
VSS26
AM29
VSS27
AM27
VSS28
AM25
VSS29
AM20
VSS30
AM17
VSS31
AM14
VSS32
AM11
VSS33
AM8
VSS34
AM5
VSS35
AM2
VSS36
AL34
VSS37
AL31
VSS38
AL23
VSS39
AL20
VSS40
AL17
VSS41
AL12
VSS42
AL9
VSS43
AL6
VSS44
AL3
VSS45
AK29
VSS46
AK27
VSS47
AK25
VSS48
AK20
VSS49
AK17
VSS50
AJ31
VSS51
AJ23
VSS52
AJ20
VSS53
AJ17
VSS54
AJ14
VSS55
AJ11
VSS56
AJ8
VSS57
AJ5
VSS58
AJ2
VSS59
AH35
VSS60
AH34
VSS61
AH33
VSS62
AH32
VSS63
AH31
VSS64
AH30
VSS65
AH29
VSS66
AH28
VSS67
AH27
VSS68
AH26
VSS69
AH20
VSS70
AH17
VSS71
AH13
VSS72
AH9
VSS73
AH6
VSS74
AH3
VSS75
AG10
VSS76
AF8
VSS77
AF4
VSS78
AF2
VSS79
AE35
VSS80
IC , AUB _ CFD _r PG A,R1P 0
VSS
C O N N@
VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160
AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30
2
JC P U1I
K27
VSS161
K9
VSS162
K6
VSS163
K3
VSS164
J32
VSS165
J30
VSS166
J21
VSS167
J19
VSS168
H35
VSS169
H32
VSS170
H28
VSS171
H26
VSS172
H24
VSS173
H22
VSS174
H18
VSS175
H15
VSS176
H13
VSS177
H11
VSS178
H8
VSS179
H5
VSS180
H2
VSS181
G34
VSS182
G31
VSS183
G20
VSS184
G9
VSS185
G6
VSS186
G3
VSS187
F30
VSS188
F27
VSS189
F25
VSS190
F22
VSS191
F19
VSS192
F16
VSS193
E35
VSS194
E32
VSS195
E29
VSS196
E24
VSS197
E21
VSS198
E18
VSS199
E13
VSS200
E11
VSS201
E8
VSS202
E5
VSS203
E2
VSS204
D33
VSS205
D30
VSS206
D26
VSS207
D9
VSS208
D6
VSS209
D3
VSS210
C34
VSS211
C32
VSS212
C29
VSS213
C28
VSS214
C24
VSS215
C22
VSS216
C20
VSS217
C19
VSS218
C16
VSS219
B31
VSS220
B25
VSS221
B21
VSS222
B18
VSS223
B17
VSS224
B13
VSS225
B11
VSS226
B8
VSS227
B6
VSS228
B4
VSS229
A29
VSS230
A27
VSS231
A23
VSS232
A9
VSS233
IC , AUB _ CFD _r PG A,R1P 0
VSS
C O N N@
3
+C P U_C ORE
@
CPU CORE
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C8 3
1
2
1
2
1
2
C8 4
1
2
22 U_0805_6.3V 6M
22 U_0805_6.3V 6M
C9 7 4
C9 7 1
1
2
22 U_0805_6.3V 6M
22 U_0805_6.3V 6M
C1 11
C9 6
1
@
@
2
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C8 6
C8 5
1
1
2
2
between Inductor and socket
22 U_0805_6.3V 6M
22 U_0805_6.3V 6M
C8 8
1
2
1
2
C9 3
1
2
22 U_0805_6.3V 6M
22 U_0805_6.3V 6M
C9 75
C9 7
1
@
2
10 U_0805_6.3V 6M
1
2
22 U_0805_6.3V 6M
1
2
22 U_0805_6.3V 6M
1
@
2
Inside cavity
10 U_0805_6.3V 6M
C8 7
C8 9
1
2
10 U_0805_6.3V 6M
C1 0 0
C9 7 0
1
2
22 U_0805_6.3V 6M
C9 69
C9 76
1
@
2
@
4
10 U_0805_6.3V 6M
C9 0
1
2
10 U_0805_6.3V 6M
C1 0 2
1
2
22 U_0805_6.3V 6M
C1 04
1
@
2
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C9 1
1
2
10 U_0805_6.3V 6M
C9 5
1
2
22 U_0805_6.3V 6M
C9 73
1
2
10 U_0805_6.3V 6M
C9 2
1
2
1
2
1
2
C9 4
1
2
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C9 8
C9 9
1
2
22 U_0805_6.3V 6M
22 U_0805_6.3V 6M
C1 13
C1 12
1
2
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C1 17
C1 14
1
1
2
2
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C1 0 1
1
2
1
2
C1 2 0
1
2
22 U_0805_6.3V 6M
22 U_0805_6.3V 6M
C1 15
C1 16
1
2
10 U_0805_6.3V 6M
10 U_0805_6.3V 6M
C1 19
C1 18
1
1
2
2
10 U_0805_6.3V 6M
C1 0 3
1
2
33 0 U_D2 _2 .5 VM_ R6 M
22 U_0805_6.3V 6M
C1 05
C9 77
1
1
+
2
2
5
33 0 U_D2 _2 .5 VM_ R6 M
33 0 U_D2 _2 .5 VM_ R6 M
33 0 U_D2 _2 .5 VM_ R6 M
C1 07
C1 09
1
1
+
+
2
2
47 0 U_D2 _2 VM_R4 .5 M
C1 08
1
+
2
C1 06
1
+
@
2
Under cavity
10 0K_ 04 02 _5 %
10 0K_ 04 02 _5 %
10 0K_ 04 02 _5 %
10 0K_ 04 02 _5 %
VS S _N C TF7_ R
+3 VS
12
R7 9
61
Q2 A 2N 7 002DWH _SOT3 63 -6
2
+3 VS
12
R8 0
5
+3 VS
12
R8 1
2
+3 VS
12
R8 2
5
CR A CK_ B GA
34
Q2 B 2N 7 002DWH _SOT3 63 -6
CR A CK_ B GA
61
Q5 A 2N 7 002DWH _SOT3 63 -6
CR A CK_ B GA
34
Q5 B 2N 7 002DWH _SOT3 63 -6
CR A CK_ BG A 17 ,3 5
VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7
NCTF
AT1 AR34 B34 B2 B1 A35
VS S _N C TF2_ R VS S _N C TF3_ R VS S _N C TF4_ R VS S _N C TF5_ R VS S _N C TF6_ R VS S _N C TF7_ R
T23 T24 T25
VS S _N C TF2_ R
VS S _N C TF1_ R
VS S _N C TF6_ R
VS S _N C TF1_ R
AT35
BGA Ball Cracking Prevention and Detection
D D
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
ARD/CFD(5/5)-GND/Bypass
LA -490 1 P
5
8 54Tu e s da y, De ce mbe r 15 , 20 09
1. 0
1
+V R EF _ DQ_DIM MA
2.2U_ 06 03 _6 .3 V6 K
0. 1U _0 40 2_ 16 V4Z C1 2 1
1
1
2
A A
B B
C C
2
DD R _ CK E 0 _DIMMA6
DD R _ A_ BS26
M_ C L K_ DD R06 M_ C L K_ DD R#06
DD R _ A_ BS06 DD R _ A_ W E#6
DD R _ A_ C AS#6
DD R _ CS 1 _D IMMA#6
200 9/0 2/1 6 HP DB-2
+3 VS
1
2
D D
+V R EF _ D Q_ DI MMA DD R _ A _D 0
C1 2 2
DD R _ A _D 1 DD R _ A _D M0 DD R _ A _D 2
DD R _ A _D 3 DD R _ A _D 8
DD R _ A _D 9 DD R _ A_ DQS#1
DD R _ A_ DQS1 DD R _ A _D 10
DD R _ A _D 11 DD R _ A _D 16
DD R _ A _D 17 DD R _ A_ DQS#2
DD R _ A_ DQS2 DD R _ A _D 18
DD R _ A _D 19 DD R _ A _D 24
DD R _ A _D 25 DD R _ A _D M3 DD R _ A _D 26
DD R _ A _D 27
DD R _ CK E 0 _DIMMA
DD R _ A _BS2 DD R _ A_ MA1 2
DD R _ A _MA 9 DD R _A_MA8
DD R _ A _MA 5 DD R _ A _MA 3
DD R _ A _MA 1 M_ C L K _DDR0
M_ C L K _DDR# 0 DD R _ A_ MA1 0
DD R _ A _BS0 DD R _ A_ WE#
DD R _ A_ CAS # M_ O DT0 DD R _ A_ MA1 3
DD R _ CS 1 _ DI MMA#
DD R _ A _D 32 DD R _ A _D 33
DD R _ A_ DQS#4 DD R _ A_ DQS4
DD R _ A _D 34 DD R _ A _D 35
DD R _ A _D 40 DD R _ A _D 41
DD R _ A _D M5 DD R _ A _D 42
DD R _ A _D 43 DD R _ A _D 48
DD R _ A _D 49 DD R _ A_ DQS#6
DD R _ A_ DQS6 DD R _ A _D 50
DD R _ A _D 51 DD R _ A _D 56
DD R _ A _D 57 DD R _ A _D M7 DD R _ A _D 58
DD R _ A _D 59
R8 7 10 K_0 40 2_ 5%
1 2
2.2U_ 04 02 _6 .3 V6 M
0. 1U _0 40 2_ 16 V4Z
C1 43
C1 44
1
2
+1. 5V + 1. 5V
3A @ 1
3A @ 1. 5V
.5V
3A @ 13A @ 1
.5V.5V
DDR3 SO-DIMM A
JD I MA 1
C O N N @
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1 VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9 VSS925VSS10
27
DQS#1 DQS129RESET# VSS1131VSS12
33
DQ10
35
DQ11 VSS1337VSS14
39
DQ16
41
DQ17 VSS1543VSS16
45
DQS#2 DQS247VSS17 VSS1849DQ22
51
DQ18 DQ1953VSS19 VSS2055DQ28
57
DQ24 DQ2559VSS21 VSS2261DQS#3
63
DM3 VSS2365VSS24
67
DQ26
69
DQ27 VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3 A12/BC#83A11
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1 VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
10 K_0 40 2_ 5%
R8 8
12
VTT1
205
G1
FO X _AS0 A626-U2 RN -7 F
VSS3 DQS0
VSS6
VSS8 DQ12 DQ13
DM1
DQ14 DQ15
DQ20 DQ21
DM2
DQ23
DQ29
DQS3 DQ30
DQ31
CKE1 VDD2
VDD4
VDD6
VDD8
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30
DM4
VSS31
DQ38 DQ39
VSS33
DQ44 DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46 DQ47
VSS40
DQ52 DQ53
VSS42
DM6
VSS43
DQ54 DQ55
VSS45
DQ60 DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62 DQ63
VSS52
EVENT#
SDA
VTT2
DQ4 DQ5
DQ6 DQ7
A15 A14
A7 A6
A4 A2
A0
CK1
BA1
S0#
NC2
SCL
G2
TOP SLOT
Reserved
1
2
2
DD R _ A _D 4
4
DD R _ A _D 5
6 8
DD R _ A_ DQS#0
10
DD R _ A_ DQS0
12 14
DD R _ A _D 6
16
DD R _ A _D 7
18 20
DD R _ A _D 12
22
DD R _ A _D 13
24 26
DD R _ A _D M1
28
DR A MR S T#
30 32
DD R _ A _D 14
34
DD R _ A _D 15
36 38
DD R _ A _D 20
40
DD R _ A _D 21
42 44
DD R _ A _D M2
46 48
DD R _ A _D 22
50
DD R _ A _D 23
52 54
DD R _ A _D 28
56
DD R _ A _D 29
58 60
DD R _ A_ DQS#3
62
DD R _ A_ DQS3
64 66
DD R _ A _D 30
68
DD R _ A _D 31
70 72
DD R _ CK E 1 _DIMMA
74 76
DD R _ A_ MA1 5
78
DD R _ A_ MA1 4
80 82
DDR_A_MA11
84
DD R _ A _MA 7
86 88
DD R _A_MA6
90
DD R _ A _MA 4
92 94
DD R _ A _MA 2
96
DD R _ A _MA 0
98 100
M_ C L K _DDR1
102
M_ C L K _DDR# 1
104 106
DD R _ A _BS1
108
DD R _ A_ RAS #
110 112
DD R _ CS 0 _ DI MMA#
114 116 118
M_ O DT1
120 122 124
+V R EF _ CA
126 128
DD R _ A _D 36
130
DD R _ A _D 37
132 134
DD R _ A _D M4
136 138
DD R _ A _D 38
140
DD R _ A _D 39
142 144
DD R _ A _D 44
146
DD R _ A _D 45
148 150
DD R _ A_ DQS#5
152
DD R _ A_ DQS5
154 156
DD R _ A _D 46
158
DD R _ A _D 47
160 162
DD R _ A _D 52
164
DD R _ A _D 53
166 168
DD R _ A _D M6
170 172
DD R _ A _D 54
174
DD R _ A _D 55
176 178
DD R _ A _D 60
180
DD R _ A _D 61
182 184
DD R _ A_ DQS#7
186
DD R _ A_ DQS7
188 190
DD R _ A _D 62
192
DD R _ A _D 63
194 196
P M_E XTTS#1 _R
198
SM B _D ATA _S3
200
SM B _C LK_S3
202 204
206
+0. 75 V
0. 6 5A
0. 6 5A @0 .75 V
@0. 75V
0. 6 5A0. 6 5A
@0. 75V@0. 75V
SM B _D ATA _S3 SM B _C LK_S3
+0 .7 5VS
For ME/iAMT debug
2
DR A MR ST # 4, 10
DD R _ CK E 1 _DIMMA 6
M_ C L K_ DD R1 6 M_ C L K_ DD R#1 6
DD R _ A_ BS1 6 DD R _ A_ R AS# 6
DD R _ CS 0 _D IMMA# 6 M_ ODT0 6
M_ ODT1 6
0. 1U _0 40 2_ 16 V4Z C1 41
1
2
PM_EX TTS# 1_ R 4, 10 SM B_D ATA _S3 4,1 0,11,13,32 SM B_CL K_ S3 4 ,10,11,13 ,32
JP 20
3
3
G2
2
2
G1
1
1
ACE S_85204 -030 01
C O N N@
1
+V R EF _CA
2.2U_ 06 03 _6 .3 V6 K C1 42
3
R8 3 1K_ 04 02 _1 %
R8 4 1K_ 04 02 _1 %
+1 .5 V
12
+V _ DDR _ C PU _ REFA
12
+V R EF _ DQ_DIM MA +V _ DDR _ C PU _ REFA
DD R _ A_ D[ 0. .63]6 DD R _ A_ D M[0 .. 7]6 DD R _ A_ D QS[ 0. .7 ]6 DD R _ A_ D QS# [0 .. 7]6 DD R _ A_ MA[ 0. .1 5]6
+1. 5V
12
R1 18 2 1K_ 04 02 _1 %
12
R1 18 3 1K_ 04 02 _1 %
200 9/0 4/1 0 HP DB-3
4
R9 91 0_0402_5%
1 2
200 9/0 4/1 0 HP DB-3
R8 6 0_ 0402_5%
1 2
200 9/0 4/1 0 HP DB-3
5
+V _ DDR _ C PU _R EF0
2
Layout Note: Pl ace near JDIMMA
+1. 5V
10 U_0603_6.3V 6M
10 U_0603_6.3V 6M
C1 2 6
1
2
5 4
Security Classification
Issued Date
3
10 U_0603_6.3V 6M
C1 2 7
1
2
10 U_0603_6.3V 6M
C1 2 8
1
2
C1 2 9
1
2
2008/09/15 2009/12/31
10 U_0603_6.3V 6M
10 U_0603_6.3V 6M
C1 3 0
1
1
2
2
Compal Secret Data
0. 1U _0 40 2_ 16 V4Z
C1 3 1
C1 3 2
1
@
2
Deciphered Date
4
@
0. 1U _0 40 2_ 16 V4Z
0. 1U _0 40 2_ 16 V4Z C1 3 3
1
@
2
0. 1U _0 40 2_ 16 V4Z
C1 3 4
C1 3 5
1
2
1
1
+
@
@
2
2
Layout Note: Place near JDIMMA.203 & JDIMMA.204
+0 .7 5VS
C1 40
C1 37
1U_0402_6.3 V6 K
C1 36
1U_0402_6.3 V6 K
C1 23
33 0 U _ D2 _2 VY_ R7 M
1
2
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
C1 38
1U_0402_6.3 V6 K
1
1
2
2
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
LA -490 1 P
10 U_0603_6.3V 6M
C1 39
1U_0402_6.3 V6 K
1
1
2
2
5
C1 24
10 U_0603_6.3V 6M
C1 25
10 U_0603_6.3V 6M
1
1
2
2
200 9/0 4/2 4 HP SI-1
9 54Tu e s da y, De ce mbe r 15 , 20 09
1. 0
1
+V R EF _ DQ_DIM MB
0. 1U _0 40 2_ 16 V4Z
2.2U_ 06 03 _6 .3 V6 K
1
1
C1 45
2
+3 VS
2
DD R _ CK E 2 _DIMMB6
DD R _ B_ BS26
M_ C L K_ DD R26 M_ C L K_ DD R#26
DD R _ B_ BS06 DD R _ B_ W E#6
DD R _ B_ C AS#6
DD R _ CS 3 _D IMMB#6
2.2U_ 04 02 _6 .3 V6 M
1
A A
B B
C C
200 9/0 2/1 6 HP DB-2
2
D D
+V R EF _ D Q_ DI MMB DD R _ B _D 0
DD R _ B _D 1
C1 46
DD R _ B _D M0 DD R _ B _D 2
DD R _ B _D 3 DD R _ B _D 8
DD R _ B _D 9 DD R _ B_ DQS#1
DD R _ B_ DQS1 DD R _ B _D 10
DD R _ B _D 11 DD R _ B _D 16
DD R _ B _D 17 DD R _ B_ DQS#2
DD R _ B_ DQS2 DD R _ B _D 18
DD R _ B _D 19 DD R _ B _D 24
DD R _ B _D 25 DD R _ B _D M3 DD R _ B _D 26
DD R _ B _D 27
DD R _ CK E 2 _DIMMB
DD R _ B _BS2 DD R _ B_ MA1 2
DD R _ B _MA 9 DDR_B_MA8
DD R _ B _MA 5 DD R _ B _MA 3
DD R _ B _MA 1 M_ C L K _DDR2
M_ C L K _DDR# 2 DD R _ B_ MA1 0
DD R _ B _BS0 DD R _ B_ WE#
DD R _ B_ CAS # M_ O DT2 DD R _ B_ MA1 3
DD R _ CS 3 _ DI MMB#
DD R _ B _D 32 DD R _ B _D 33
DD R _ B_ DQS#4 DD R _ B_ DQS4
DD R _ B _D 34 DD R _ B _D 35
DD R _ B _D 40 DD R _ B _D 41
DD R _ B _D M5 DD R _ B _D 42
DD R _ B _D 43 DD R _ B _D 48
DD R _ B _D 49 DD R _ B_ DQS#6
DD R _ B_ DQS6 DD R _ B _D 50
DD R _ B _D 51 DD R _ B _D 56
DD R _ B _D 57 DD R _ B _D M7 DD R _ B _D 58
DD R _ B _D 59
R9 1
1 2
10 K_0 40 2_ 5%
0. 1U _0 40 2_ 16 V4Z C1 66
C1 65
1
1 2
R9 2 10K_0402_5%
2
DDR3 SO-DIMM B
+1. 5V + 1. 5V
REVERSE
3A @ 1
3A @ 1. 5V
.5V
3A @ 13A @ 1
.5V.5V
C O N N @
JD I MB 1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1 VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9 VSS925VSS10
27
DQS#1 DQS129RESET# VSS1131VSS12
33
DQ10
35
DQ11 VSS1337VSS14
39
DQ16
41
DQ17 VSS1543VSS16
45
DQS#2 DQS247VSS17 VSS1849DQ22
51
DQ18 DQ1953VSS19 VSS2055DQ28
57
DQ24 DQ2559VSS21 VSS2261DQS#3
63
DM3 VSS2365VSS24
67
DQ26
69
DQ27 VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3 A12/BC#83A11
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1 VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
+0. 75 V
VSS3 DQS0
VSS6
VSS8 DQ12 DQ13
DM1
DQ14 DQ15
DQ20 DQ21
DM2
DQ23
DQ29
DQS3 DQ30
DQ31
CKE1 VDD2
VDD4
VDD6
VDD8
CK1
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30
DM4
VSS31
DQ38 DQ39
VSS33
DQ44 DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46 DQ47
VSS40
DQ52 DQ53
VSS42
DM6
VSS43
DQ54 DQ55
VSS45
DQ60 DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62 DQ63
VSS52
EVENT#
SDA SCL
VTT2
2
DD R _ B_ D QS# [0 .. 7]6 DD R _ B_ D[ 0. .63]6
2
DD R _ B _D 4
4
DQ4 DQ5
DQ6 DQ7
A15 A14
A7 A6
A4 A2
A0
BA1
S0#
G2
6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
206
DD R _ B _D 5 DD R _ B_ DQS#0
DD R _ B_ DQS0 DD R _ B _D 6
DD R _ B _D 7 DD R _ B _D 12
DD R _ B _D 13 DD R _ B _D M1
DR A MR S T# DD R _ B _D 14
DD R _ B _D 15 DD R _ B _D 20
DD R _ B _D 21 DD R _ B _D M2 DD R _ B _D 22
DD R _ B _D 23 DD R _ B _D 28
DD R _ B _D 29 DD R _ B_ DQS#3
DD R _ B_ DQS3 DD R _ B _D 30
DD R _ B _D 31
DD R _ CK E 3 _DIMMB DD R _ B_ MA1 5
DD R _ B_ MA1 4 DDR _B_MA11
DD R _ B _MA 7 DDR_B_MA6
DD R _ B _MA 4 DD R _ B _MA 2
DD R _ B _MA 0 M_ C L K _DDR3
M_ C L K _DDR# 3 DD R _ B _BS1
DD R _ B_ RAS # DD R _ CS 2 _ DI MMB#
M_ O DT3
+V R EF _ CB DD R _ B _D 36
DD R _ B _D 37 DD R _ B _D M4 DD R _ B _D 38
DD R _ B _D 39 DD R _ B _D 44
DD R _ B _D 45 DD R _ B_ DQS#5
DD R _ B_ DQS5 DD R _ B _D 46
DD R _ B _D 47 DD R _ B _D 52
DD R _ B _D 53 DD R _ B _D M6 DD R _ B _D 54
DD R _ B _D 55 DD R _ B _D 60
DD R _ B _D 61 DD R _ B_ DQS#7
DD R _ B_ DQS7 DD R _ B _D 62
DD R _ B _D 63 P M_E XTTS#1 _R
SM B _D ATA _S3 SM B _C LK_S3
0. 6 5A
0. 6 5A @0 .75 V
@0. 75V
0. 6 5A0. 6 5A
@0. 75V@0. 75V
DR A MR ST # 4,9
DD R _ CK E 3 _DIMMB 6
M_ C L K_ DD R3 6 M_ C L K_ DD R#3 6
DD R _ B_ BS1 6 DD R _ B_ R AS# 6
DD R _ CS 2 _D IMMB# 6 M_ ODT2 6
M_ ODT3 6
0. 1U _0 40 2_ 16 V4Z C1 59
1
2
PM_EX TTS# 1_ R 4, 9 SM B_D ATA _S3 4,9 ,11,13,32 SM B_CL K_ S3 4 ,9,11,1 3, 32 +0 .7 5VS
DD R _ B_ D M[0 .. 7]6 DD R _ B_ D QS[ 0. .7 ]6 DD R _ B_ MA[ 0. .1 5]6
+V R EF _CB
2.2U_ 06 03 _6 .3 V6 K C1 60
1
2
3
R1 18 7 1K_ 04 02 _1 %
R1 18 8 1K_ 04 02 _1 %
Layout Note: Pl ace near JDIMMB
200 9/0 4/2 4 HP SI-1
+1. 5V
12
12
200 9/0 4/2 4 SI-1
10 U_0603_6.3V 6M
1
2
4
10 U_0603_6.3V 6M
1
2
+V _ DDR _ C PU _ REFB
200 8/1 1/0 7 HP
10 U_0603_6.3V 6M
C1 53
1
2
C1 54
1
@
2
200 9/0 4/1 0 HP DB-3
0. 1U _0 40 2_ 16 V4Z C1 55
1
@
2
+V _ DDR _ C PU _R EF1
0. 1U _0 40 2_ 16 V4Z C1 56
1
@
2
0. 1U _0 40 2_ 16 V4Z C1 57
200 9/0 4/2 4 HP SI-1
0. 1U _0 40 2_ 16 V4Z C1 58
1
@
2
200 9/0 4/1 0 HP DB-3
33 0 U _D 2_ 2V Y_R 7M
C9 61
1
+
@
2
R1 18 4 1K_ 04 02 _1 %
R1 18 5 1K_ 04 02 _1 %
Layout Note: Place near JDIMMB.203 & JDIMMB.204
+V R EF _ DQ_DIM MB
R8 9 0_ 0402_5%
1 2
200 9/0 4/1 0 HP DB-3
R9 0 0_ 0402_5%
1 2
+1 .5 V +0. 75 VS
10 U_0603_6.3V 6M
10 U_0603_6.3V 6M
10 U_0603_6.3V 6M
C1 49
C1 50
1
1
2
2
C1 52
C1 51
1
2
5
+1 .5 V
12
+V _ DDR _ C PU _ REFB
12
1U_0402_6.3 V6 K
C1 6 1
1
1
2
2
1U_0402_6.3 V6 K
1U_0402_6.3 V6 K
1U_0402_6.3 V6 K
C1 6 2
C1 6 4
C1 6 3
1
1
2
2
BOT SLOT
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Da t e: She et o f
Compal Electronics, Inc.
DDRIII-SODIMM SLOT2
LA -490 1 P
5
10 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
A A
CL K _ BU F_ DO T9613 CL K _ BU F_DOT 96 #13
27 M_CL K20 27 M _S SC20
CL K _ BU F _CK SS CD13 CL K _ BU F _CK SS CD#13
CL K _ DMI13 CL K _ DMI #13
B B
CL K _ B UF_ DO T96 CL K _ B UF_ DO T96#
27 M_CLK 27 M_SSC
CL K _ BU F _CK S SCD CL K _ BU F _C KSS CD#
CL K _ DM I CL K _ DMI #
R9 3 0_ 0402_5%
1 2
R9 5 0_ 0402_5%
1 2
R9 6 0_ 0402_5%
1 2
R9 7 22 _0402_1%
1 2
200 9/0 2/2 7 Nvi dia DB -2 NV care
R9 9 0_ 0402_5%
1 2
R1 00 0_0402_5%
1 2
R1 01 0_0402_5%
1 2
R1 03 0_0402_5%
1 2
2
L_ C L K _B UF_ DO T96 L_ C L K_BU F_DOT 96 #
L _2 7M_CL K L_ 27 M_SSC
L_ C L K_B U F _C KSS CD L_ C L K_B U F _C KSS CD#
L_ C L K_ DMI L_ C L K_ DMI #
CP U _ STOP#
250mA 80mA
U2
1
VDD_DOT
2
VSS_DOT
3
DOT_96
4
DOT_96#
5
VDD_27
6
27MHZ
7
27MHZ_SS
8
VSS_27
9
VSS_SATA
10
SRC_1/SATA
11
SRC_1#/SATA#
12
VSS_SRC
13
SRC_2
14
SRC_2#
15
VDD_SRC_IO
16
CPU_STOP#
RTM890N- 63 2_ QF N32_5X5
3
96MHz
REF_0/CPU_SEL
CKPWRGD/PD#
100MHz 133MHz
100MHz
TGND
33
SDA
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_CPU_IO
VDD_SRC
4
+3 VS_ +1 .5 VS
200 9/0 6/3 0 HP SI-2
+3 VS_C K505 +1 .0 5VS_C K505+3 VS_C K505 +1 .0 5VS_C K505
32
SCL
31 30 29 28 27 26 25
24 23 22 21 20 19 18 17
SM B _C LK_S3 SM B _D ATA _S3 RE F _0 / C PU_S EL
CL K_XTAL _I N C LK_XTAL_ OU T
CK _ PWR G D
R_ C L K_ B U F_B CL K R_ C L K_ B U F_B CL K#
R9 433 _0402_1%
1 2
1
2
R1 02 0 _0 40 2_ 5%
1 2
R1 04 0_0 40 2_ 5%
1 2
CL K _ 14M_ PCH
C8 3 1
@
10 P_0 40 2_ 50 V8 C
CL K _ BU F _BCL K CL K _ BU F_B CLK#
SM B_CL K_ S3 4, 9, 10 ,13,32 SM B_DA TA_ S3 4, 9, 10 ,1 3,32 CL K _ 14 M_P CH 13
CL K _ BU F_ BC LK 13 CL K _ BU F_ BC LK# 13
5
47 P_0 40 2_ 50 V8J
C1 77
1
2
200 9/0 6/3 0 HP SI-2 200 9/0 9/1 4 HP SI-2b
R1 21 4 0_0603_5%@
1 2
R1 21 5 0_0603_5%
1 2
2008/09/15 2009/12/31
+3 VS +1. 5V S
Compal Secret Data
Deciphered Date
4
CK _ PWR G D
33 P_0 40 2_ 50 V8J
Tit le
Size Do c u me nt N umb er R e v
Da t e: She et o f
R9 8 10 K_0 40 2_ 5%
1 2
13
D
2
G
S
Q8 SS M3K7 00 2FU_SC7 0- 3
14 .31818MHZ_ 20 P_ 1BX14 31 8B E1A
C1 67
Close to U2
Y1
2
1
12
2
C1 6 8
33 P_0 40 2_ 50 V8J
1
C LK_XTAL_ OU T
Compal Electronics, Inc.
CLOCK GENERATOR
LA -490 1 P
CL K _ EN# 46
CL K_XTAL _I N
5
+3 VS_C K505
1. 0
11 54T u esd ay , Dec ember 15, 2 00 9
+3 VS_ +1 .5 VS
+1 .05VS_ CK5 05+1 .0 5VS
C C
1 2
R1 2 8 0_0603_5%
10 U_0603_6.3V 6M
1
2
D D
(Default)
0 133MHz
1
100MHz 100MHz
1
Close to U2 Close to U2
0. 1U _0 40 2_ 16 V4Z
C1 78
1
2
CPU_1PIN 30 CPU_0
133MHz
10 U_ 08 05 _1 0V 4Z
0. 1U _0 40 2_ 16 V4Z
C1 80
C1 79
1
1
2
2
47 P_0 40 2_ 50 V8J
0. 1U _0 40 2_ 16 V4Z C1 82
C1 81
1
1
2
2
200 9/0 2/0 6 HP DB-2
+1 .0 5VS
R1 4 2 10 K_0 40 2_ 5%@
R1 4 4 10 K_0 40 2_ 5%
C1 83
1 2
1 2
CP U _ STOP#
C1 8 4 1 0P _0 40 2_ 50 V8C
R1 27 1 0K_0402_5%
1 2
@
1 2
EMI Capacitor
RE F _0 / C PU_S EL
+3 VS_ CK 50 5
RE F _0 / C PU_S EL
2
+3 VS
+3 VS_C K505
1 2
R1 0 9 0_0603_5%
0. 1U _0 40 2_ 16 V4Z
10 U_0603_6.3V 6M
C1 71
1
1
2
2
0. 1U _0 40 2_ 16 V4Z
0. 1U _0 40 2_ 16 V4Z
C1 72
C1 73
1
1
2
2
3
0. 1U _0 40 2_ 16 V4Z
0. 1U _0 40 2_ 16 V4Z
C1 74
C1 76
C1 75
1
1
2
2
Security Classification
Issued Date
1
2
3
4
5
PC H _ RT CX1
32 . 76 8KHZ_ 12 .5PF_ Q1 3MC 14 61 00 02
for SM SC EC
not ice KB C state
PC H _ RT CX2
1
C1 91 18 P_0 40 2_ 50 V8J
2
KB C _SPI_ SI_R
HD A _ BI T _CLK_ MDC31 HD A _ BI T _CLK _C ODEC31 HD A _ SY N C_ M DC31 HD A _ SY N C_ C O D EC31 HD A _ SP KR31
HD A _ RS T# _MDC31 HD A _ RS T #_ CO DE C31
HD A _ SD IN 031 HD A _ SD IN 131
HD A _ SD O U T_M DC31 HD A _ SD O U T_ CO DE C31
+R T CV CC
1U _0 60 3_ 10 V4 Z
1 2
R1 64 20 K_0402_1%
1 2
R1 65 20 K_0402_1%
1U _0 60 3_ 10 V4 Z
+3 V AL W
KB C _SP I_ CL K_R35 KB C _SPI_C S0 #_ R35 KB C _SPI_C S1 #_ R35
KB C _SPI_S I_ R35 KB C _SPI _SO35
1
12
C1 92
200 9/0 2/2 0 HP DB-2
CL R P1
SH O R T P ADS
2
1
C1 95
200 9/0 4/2 4 HP SI-1
2
R1 67 33_0402_5%
1 2
R1 68 33_0402_5%
1 2
R1 69 33_0402_5%
1 2
R1 70 33_0402_5%
1 2
R1 72 33_0402_5%
1 2
R1 73 33_0402_5%
1 2
R1 76 33_0402_5%
1 2
R1 77 33_0402_5%
1 2
R1 14 4 1K_ 04 02 _5 %
1 2 1 2
R1 22 5 10K_0 40 2_ 5%
R1 02 6 15_0402_5%
1 2
R1 81 0_0402_5%
1 2
R1 85 0_0402_5%
1 2
R1 02 7 15_0402_5%
1 2
1 2
R1 5 9 10M_0 40 2_ 5%
18 P_0 40 2_ 50 V8J
1
1
C1 9 0
A A
2
200 9/0 4/1 3 DB- 3 C omp al WLAN nosie
C1 93 22P_0 40 2_ 50 V8J C1 94 22P_0 40 2_ 50 V8J C2 00 22P_0 40 2_ 50 V8J C2 01 22P_0 40 2_ 50 V8J
B B
iTPM ENABLE/DISABLE
+3 VS
Ena ble =Stuff Dis abl e=N o Stuff
C C
OSC4OSC
NC3NC
Y3
2
@
HD A _ BI T _CLK _MD C
1 2
@
HD A _ BI T _CLK_ CO DEC
1 2
HD A _ SD O U T_ MDC
@
1 2
HD A _ SD O U T_ C OD EC
@
1 2
1 2
R1 8 6 1 K_ 04 02 _5 %@
GPIO33 iAMT Enable /Disable
+R T CV CC
200 9/0 2/0 6 HP DB-2
+3 VS
1 2
R1 6 1 1 0K _0 40 2_ 5%
1 2
R1 6 3 1 K_ 04 02 _5 %@
LOW =De fault HIG H=N o R eboot
FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3
FWH4 / LFRAME#
LDRQ1# / GPIO23
RTCIHDA
LPC
SATA0RXN SATA0RXP
HDD
SATA0TXN SATA0TXP
SATA1RXN SATA1RXP
ODD
SATA1TXN SATA1TXP
SATA2RXN SATA2RXP
DOCKING
SATA2TXN SATA2TXP
SATA3RXN SATA3RXP SATA3TXN SATA3TXP
SATA4RXN SATA4RXP
E-SATA
SATA4TXN
SATA
SATA4TXP SATA5RXN
SATA5RXP
DOCKING
SATA5TXN SATA5TXP
SATAICOMPO
SATAICOMPI
SATALED#
SATA0GP / GPIO21 SATA1GP / GPIO19
SPI JTAG
LDRQ0#
SERIRQ
D33 B33 C32 A32
C34 A34
F34 AB9
AK7 AK6 AK11 AK9
AH6 AH5 AH9 AH8
AF11 AF9 AF7 AF6
AH3 AH1 AF3 AF1
AD9 AD8 AD6 AD5
AD3 AD1 AB3 AB1
AF16 AF15
T3
Y9 V1
SI R Q
HD A _ SP K R
NA N D_D ET# SI R Q
SA TA_P RX_ DTX_N 0 S ATA_PR X_DTX_P0 SA TA_P TX_ DRX_N 0 S ATA_PTX_D RX_P0
SA TA_P RX_ DTX_N 1 S ATA_PR X_DTX_P1 SA TA_P TX_ DRX_N 1 S ATA_PTX_D RX_P1
SA TA_P RX_ DTX_N 2 S ATA_PR X_DTX_P2 SA TA_P TX_ DRX_N 2 S ATA_PTX_D RX_P2
SA TA_P RX_ DTX_N 4 S ATA_PR X_DTX_P4 SA TA_P TX_ DRX_N 4 S ATA_PTX_D RX_P4
SA TA_P RX_ DTX_N 5 S ATA_PR X_DTX_P5 SA TA_P TX_ DRX_N 5 S ATA_PTX_D RX_P5
SA TA_D ET# 0 HD D _ HA L TLED _R
200 9/0 2/1 8 HP DB-2
200 9/0 2/0 6 HP DB-2
1 2
R1 80 37. 4_ 04 02 _1 %
1 2
R1 82 10K_0402_1%
R1 09 6 0_0402_5%
1 2
LP C _L AD0 28, 33 ,3 5,36 LP C _L AD1 28, 33 ,3 5,36 LP C _L AD2 28, 33 ,3 5,36 LP C _L AD3 28, 33 ,3 5,36
LP C _ LFRAME# 28 ,3 3, 35 ,36 LP C _L DR Q# 0 36
200 9/0 5/0 2 HP SI-1
SI R Q 30 ,3 3,35,36
SA TA_PR X_DTX_N0 29 SATA_ PRX _D TX_ P0 29 SA TA_PTX_D RX_N0 29 SATA_ PTX_DR X_ P0 29
SA TA_PR X_DTX_N1 29 SATA_ PRX _D TX_ P1 29 SA TA_PTX_D RX_N1 29 SATA_ PTX_DR X_ P1 29
SA TA_PR X_DTX_N4 29 SATA_ PRX _D TX_ P4 29 SA TA_PTX_D RX_N4 29 SATA_ PTX_DR X_ P4 29
+1 .0 5VS
+3 VS
SA TA_LED# 3 1, 34
200 9/0 8/3 0 HP PV
200 9/0 5/1 2 HP SI-1
SA TA_D ET# 0
HD D _ HA L TL ED 31
PC H _ RT C RS T#
U4 A
B13
RTCX1
D13
RTCX2
C14
RTCRST#
D17
SRTCRST#
A16
INTRUDER#
A14
INTVRMEN
A30
HDA_BCLK
D29
HDA_SYNC
P1
SPKR
C30
HDA_RST#
G30
HDA_SDIN0
F30
HDA_SDIN1
E32
HDA_SDIN2
F32
HDA_SDIN3
B29
HDA_SDO
H32
HDA_DOCK_EN# / GPIO33
J30
HDA_DOCK_RST# / GPIO13
M3
JTAG_TCK
K3
JTAG_TMS
K1
JTAG_TDI
J2
JTAG_TDO
J4
JTAG_RST#
BA2
SPI_CLK
AV3
SPI_CS0#
AY3
SPI_CS1#
AY1
SPI_MOSI
AV1
SPI_MISO
IB E XP EAK -M_ FCBGA 10 71
SM _ IN T R UD ER# PC H _ IN T V RME N
1 2
R1 60 1M_ 04 02 _5 %
1 2
R1 62 33 0K_ 04 02 _5 %
Hig h = In te rna l V R E nab led(Default)
T12 7
PC H _ RT CX1 PC H _ RT CX2
PC H _ RT C RS T# PC H _ SR T CR ST# SM _ IN T R UD ER# PC H _ IN T V RME N
HD A _ B IT_ CL K H D A _ SY N C HD A _ SP K R HD A _ R ST#
HD A _ SD I N0 HD A _ SD I N1
HD A _ SD O UT
G PIO33AQ U AWH I T E_BATL ED
PC H _ JT A G_ TCK PC H _ J TAG _TMS PC H _ J TAG _TDI PC H _ J TAG _TDO PC H _ J TAG _R ST#
PC H _ SP I _C LK PC H _ S PI_ CS 0# PC H _ S PI_ CS 1#
PC H _ S PI_ SI HD D _ HA L TLED
C2 15
1U _0 60 3_ 10 V4 Z
+3 VS
1 2
R1 15 9 10 K_ 04 02 _5%
200 9/0 2/1 1 HP DB-2
SA TA_P RX_ DTX_N 0 S ATA_PR X_DTX_P0 SA TA_P RX_ DTX_N 1 S ATA_PR X_DTX_P1
SA TA_P RX_ DTX_N 2 S ATA_PR X_DTX_P2 SA TA_P RX_ DTX_N 5 S ATA_PR X_DTX_P5
SA TA_PR X_DTX_N2 34 SATA_ PRX _D TX_ P2 34 SA TA_PTX_D RX_N2 34 SATA_ PTX_DR X_ P2 34
SA TA_P RX_ DTX_N 4 S ATA_PR X_DTX_P4
SA TA_PR X_DTX_N5 34 SATA_ PRX _D TX_ P5 34 SA TA_PTX_D RX_N5 34 SATA_ PTX_DR X_ P5 34
+3 VS
12
R1 83 10 K_0 40 2_ 5%
W=20mils
1
2
12
R1 84 10 K_0 40 2_ 5%
RTC Conn.
D 1
1
DA N 2 02 U_SC7 0
Place near IBEX-M
NA N D_D ET#
T13 0 T13 1 T13 2 T13 3
T13 4 T13 5 T13 6 T13 7
33 0K_ 04 02 _5%
T14 0
200 8/1 2/1 2 HP
T14 1
AQ U AWH I TE _BATLED#31 ,35
@
200 9/0 2/0 6 HP DB-2
2
R1 9 8
3
1 2
W=20mils
1K_ 04 02 _5 %
12
R6 8 1
@
BATT1.1+VREG 3_ 51 12 5+R T CV CC
+3 VS
12
13
D
2
G
S
JB AT1
W=20mils
R7 90
@
10 K_0 40 2_ 5%
AQ U AWH I T E_BATL ED
200 9/0 2/0 6 HP DB-2
Q6 3 2N7002H_S OT2 3- 3
C O N N@
1
2
ACE S_85205 -020 0
Hi Disable Lo Enable Default
XD P _FN0
R7 9833_0402_5% @
US B _OC# 015
+3 VALW +3 V AL W+ 3 VA LW +3 VA LW
12
R1 88 20 0_0402_5%
PC H _ J TAG _TMS PCH _ J TAG_TDO PC H _ J TAG _R ST#PC H _ J TAG _TDI
12
R1 94 10 0_0402_1%
D D
PCH Pin
PCH _JT AG_TDO
PCH _JT AG_TMS
PCH _JT AG_TDI
PCH _JT AG_TCK
PCH _JT AG_ RST#
12
R1 89 20 0_0402_5%
12
R1 95 10 0_0402_1%
Ref Des PCH JTA G Pre -Pr oduction PCH JT AG Pr oduction
ES1
ES2
No Ins tall
R189 R195 R No In stall No In stall
R
R194 R R190 R196 R R199 R191 R197 R 51o hmNo Ins tall No I ns tall
100 ohm
No Ins tall
200 ohm
200 ohm 100 ohm
100 ohm
No Ins tall No I ns tall 5 1ohm
200 ohm No Ins tall
200 ohm 100 ohm
100 ohm
No Ins tall No I ns tall
51o hm
51o hm
20K ohm
20K ohm 10K ohm
10K ohm
1
12
R1 9 0 20 0_0402_5%
12
R1 9 6 10 0_0402_1%
MP No Ins tall200ohm No Ins tall 51o hm No Ins tallR188 No Ins tall
No Ins tall 51o hm 51o hm No Ins tall No Ins tall
12
R1 91 20 K_0 40 2_ 5%
12
R1 97 10 K_0 40 2_ 5%
PC H _ J TAG _TDO PC H _ J TAG _TMS PC H _ J TAG _TDI PC H _ J TAG _R ST# PC H _ JT A G_ TCK
@
200 9/0 3/0 8 HP SI-1
@
R1 10 5 51_0402_5%@ R1 10 6 51_0402_5%@ R1 10 7 51_0402_5%@ R1 10 8 51_0402_5%@ R1 99 51 _0402_5%
+1 .0 5VS
1 2 1 2 1 2 1 2 1 2
2
US B _OC# 115 US B _OC# 215
US B _OC# 315
US B _OC# 415 US B _OC# 515
US B _OC# 615 US B _OC# 715
PW R _ GD3 5, 37 PM _ PW R BTN# _R4 ,14
PW R _ GD
1
C9 9 8
@
0.1U_ 04 02 _2 5V 4K
2
200 9/0 9/1 5 Com pal ESD PV
PC H _ JT A G_ TCK
3
1 2 1 2
1 2 1 2
200 8/1 2/1 2 HP
1 2 1 2
1 2 1 2
R8 14
1 2
200 9/0 2/0 6 HP DB-2
1 2
R8 19 0_0402_5%
Security Classification
Issued Date
XD P _FN1
R8 0033_0402_5% @
XD P _FN2
R8 0233_0402_5% @ R8 0433_0402_5% @
XD P _FN3
R1 09 533 _0 40 2_ 5% @
XD P _FN5
R8 0833_0402_5% @ R8 1033_0402_5% @
XD P _FN6 XD P _FN7
R8 1233_0402_5% @
PW R _ GD
XD P _PW R BTN #_ R
0_ 0402_5%
T128 T129
PC H _ JT A G_ TCK_R
PCH XDP Conn.
JP 15
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
39
PWRGOOD/HOOK0
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
SAMTE_BSH -0 30 -0 1- L- D-A C O N N@
2008/09/15 2009/12/31
Compal Secret Data
OBSDATA_C0 OBSDATA_C1
OBSDATA_C2 OBSDATA_C3
OBSDATA_D0 OBSDATA_D1
OBSDATA_D2 OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
Deciphered Date
GND1 OBSFN_C0 OBSFN_C1
GND3
GND5
GND7 OBSFN_D0 OBSFN_D1
GND9
GND11
GND13
DBR#/HOOK7
GND15
TRST#
GND17
4
2
XD P _FN1 7
4
XD P _FN1 6
6 8
XD P _FN8
10
XD P _FN9
12 14
XD P _FN1 0
16
XD P _FN1 1
18 20 22 24 26
XD P _FN1 2
28
XD P _FN1 3
30 32
XD P _FN1 4
34
XD P _FN1 5
36 38 40 42 44 46 48 50
PC H _ JT A G_ TDO #_ R
52
TD0
TDI
TMS
54 56 58 60
PC H _ JT A G_ RST#_R PC H _ JT A G_ TDI _R PC H _ J TAG _TMS_R
R7 96 33_0402_5%@
1 2
R7 97 33_0402_5%@
1 2
R7 99 33_0402_5%@
1 2
R8 01 33_0402_5%@
1 2
R8 03 33_0402_5%@
1 2
R8 05 33_0402_5%@
1 2
R8 07 33_0402_5%@
1 2
R8 09 33_0402_5%@
1 2
R8 11 33_0402_5%@
1 2
R8 13 33_0402_5%@
1 2
R8 15 1K_ 04 02 _5 %
1 2
R8 16 0 _0 40 2_ 5%
1 2
R8 17 0 _0 40 2_ 5%@
1 2
R8 18 0 _0 40 2_ 5%
1 2
R8 20 0 _0 40 2_ 5%
1 2
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
SA TA_D ET# 0 HD D _ HA L TLED _R
PC H _ J TAG _TDO PC H _ J TAG _R ST# PC H _ J TAG _TDI PC H _ J TAG _TMS
Compal Electronics, Inc.
IBEX-M(1/6)-HDA/JTAG/SATA
PC H _ XDP _G PIO 28 15 PC H _ XDP _G PIO 0 15
PC H _ XDP _G PIO 20 13 PC H _ XDP _G PIO 18 13
200 9/0 2/1 6 HP DB-2
PC H _ XDP _G PIO 36 15 PC H _ XDP _G PIO 37 1 5,19
PC H _ XDP _G PIO 16 15 PC H _ XDP _G PIO 49 15
+3 VS+3 VS
PL T_RST# 4,15,20 ,2 6, 28 ,3 1,33 XD P _DBR ESE T# 4,14
LA -490 1 P
5
GPI O_28 GPI O_0
GPI O_36 GPI O_37
GPI O_16 GPI O_49
12 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
2
3
4
5
SM B _C LK_S3 SM B _D ATA _S3
A A
U 4 B
BG30
PERN1
BJ30
PERP1
BF29
PETN1
BH29
PC I E_ PRX _DTX_ N231
EXP
WLAN
B B
NIC
EXP
C C
WLAN
D D
PC I E_ PRX _DTX_ P231 PC I E_ PTX_C _D RX_ N231 PC I E_ PTX_C_ DR X_P231
PC I E_ PRX _DTX_ N428 PC I E_ PRX _DTX_ P428 PC I E_ PTX_C _D RX_ N428 PC I E_ PTX_C_ DR X_P428
PC I E_ PRX _DTX_ N626 PC I E_ PRX _DTX_ P626 PC I E_ PTX_C _D RX_ N626 PC I E_ PTX_C_ DR X_P626
PC H _ XDP _G PIO 1812
CL K _ PC IE_L AN _REQ1 #26
+3 VS
CL K _P CIE_E XP#31 CL K _ PCI E_ EXP3 1
PC H _ XDP _G PIO 2012
CL K RE Q_EXP#31
CL K _ PC I E_MC ARD #28 CL K _ PC I E_MC ARD28
CL K R EQ _ WL AN #28
C2 16 0.1U_0 40 2_ 10 V7 K
1 2
C2 17 0.1U_0 40 2_ 10 V7 K
1 2
C2 18 0.1U_0 40 2_ 10 V7 K
1 2
C2 19 0.1U_0 40 2_ 10 V7 K
1 2
C2 22 0.1U_0 40 2_ 10 V7 K
1 2
C2 23 0.1U_0 40 2_ 10 V7 K
1 2
+3 V AL W
R2 12 1 0K_0402_5%
+3 VS
+3 V AL W
+3 V AL W
+3 V AL W
+3 V AL W
R8 2 1 10 K_0 40 2_ 5%
1 2
R2 13
1 2 1 2
R2 14
R2 0 4 10 K_0 40 2_ 5% R1 00 9 0_0402_5% R2 0 6 10 K_0 40 2_ 5%
R2 16
1 2 1 2
R2 17
R3 5 4 10 K_0 40 2_ 5%
R3 5 3 10 K_0 40 2_ 5%
R1 13 8 10K_0 40 2_ 5%
200 9/0 2/0 6 HP DB-2
200 9/0 2/0 6 HP DB-2
1 2
0_ 0402_5% 0_ 0402_5%
1 2 1 2 1 2
0_ 0402_5% 0_ 0402_5%
1 2
1 2
1 2
PC I E_ PR X_DTX_N2 PC I E_ PRX _DTX_ P2 PC I E_ PTX_D RX_N2 PC I E_ PTX_DR X_ P2
PC I E_ PR X_DTX_N4 PC I E_ PRX _DTX_ P4 PC I E_ PTX_D RX_N4 PC I E_ PTX_DR X_ P4
PC I E_ PR X_DTX_N6 PC I E_ PRX _DTX_ P6 PC I E_ PTX_D RX_N6 PC I E_ PTX_DR X_ P6
200 9/0 5/0 2 HP SI-1
R1 19 8 0_0402_5%
1 2
CL K _ PC IE_EX P#_R CL K _ PC IE_EX P_R
200 8/1 2/1 2 HP
CL K _ PC I E_ MCA RD#_R CL K _ PC I E_ MCA RD_R
PETP1
AW30
PERN2
BA30
PERP2
BC30
PETN2
BD30
PETP2
AU30
PERN3
AT30
PERP3
AU32
PETN3
AV32
PETP3
BA32
PERN4
BB32
PERP4
BD32
PETN4
BE32
PETP4
BF33
PERN5
BH33
PERP5
BG32
PETN5
BJ32
PETP5
BA34
PERN6
AW34
PERP6
BC34
PETN6
BD34
PETP6
AT34
PERN7
AU34
PERP7
AU36
PETN7
AV36
PETP7
BG34
PERN8
BJ34
PERP8
BG36
PETN8
BJ36
PETP8
AK48
CLKOUT_PCIE0N
AK47
CLKOUT_PCIE0P
P9
PCIECLKRQ0# / GPIO73
AM43
CLKOUT_PCIE1N
AM45
CLKOUT_PCIE1P
U4
PCIECLKRQ1# / GPIO18
AM47
CLKOUT_PCIE2N
AM48
CLKOUT_PCIE2P
N4
PCIECLKRQ2# / GPIO20
AH42
CLKOUT_PCIE3N
AH41
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
AM51
CLKOUT_PCIE4N
AM53
CLKOUT_PCIE4P
M9
PCIECLKRQ4# / GPIO26
AJ50
CLKOUT_PCIE5N
AJ52
CLKOUT_PCIE5P
H6
PCIECLKRQ5# / GPIO44
AK53
CLKOUT_PEG_B_N
AK51
CLKOUT_PEG_B_P
P13
PEG_B_CLKRQ# / GPIO56
IB E XP EA K-M_FCBG A1071
PCI-E*
120/133MHz
100MHz
100MHz
100MHz
100MHz
SMBALERT# / GPIO11
SMBCLK
SMBDATA
SML0ALERT# / GPIO60
SML0CLK
SML0DATA
SML1ALERT# / GPIO74
SMBus
SML1CLK / GPIO58
SML1DATA / GPIO75
CL_CLK1
Link
Controller
100MHz
100MHz
PEG
CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P
100MHz
133MHz
96MHz
From CLK BUFFER
CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P
CL_DATA1
CL_RST1#
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N CLKOUT_PEG_A_P
CLKOUT_DMI_N CLKOUT_DMI_P
CLKIN_DMI_N CLKIN_DMI_P
CLKIN_BCLK_N CLKIN_BCLK_P
CLKIN_DOT_96N CLKIN_DOT_96P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
Clock Flex
L_ L ID_ SW #
B9
SM B CL K
H14
SM BD ATA
C8
SM L 0ALER T#
J14
SM L 0C LK
C6
SM L 0DATA
G8
SM L 1ALER T#
M14
SM L 1C LK
E10
SM L 1DATA
G12
T13 T11 T9
PE G _ C LKREQ #
H1
AD43 AD45
AN4 AN2
CL K _ DP#
AT1
CL K _ DP
AT3
AW24 BA24
AP3 AP1
F18 E18
AH13 AH12
P41
J42
XTAL25_IN
AH51
XTAL25_OUT
AH53 AF38
R2 18 90.9_0402_1%
1 2
T45
P43
T42
N50
CL K_14M_SIO_ P
R2 22 22_0402_5%
1 2
200 9/0 5/1 9 HP SI-1
For SMSC SIO 14MHz CLK out
200 9/0 7/0 3 SI-1b 200 9/0 8/3 0 HP PV
SM L0 CL K 26 SM L0 DATA 26
CL _ CL K 28 CL _ DA TA 28 CL _ RST # 28
CL K _P EG_VG A# 20 CL K _ PEG _V GA 20
CL K_ EXP # 4 CL K_ EXP 4
T27 T28
CL K _D MI# 11 CL K _D MI 11
CL K _ BU F_ BC LK# 11 CL K _ BU F_ BC LK 11
CL K _ BU F_DOT 96 # 11 CL K _ BU F_DOT 96 11
CL K _ BU F _CK SSC D# 11 CL K _ BU F _CK SSC D 11
CL K _ 14 M_P CH 11
CL K _ PC I_ FB 15
T93
T94
DDR
Intel LAN
CBB
+1 .0 5VS
1
C8 33 10 P_0 40 2_ 50 V8C
2
PE G _ C LKREQ #
09/ 02/ 22 HP DB-2
CL K_14M_ SIO 36
@
R2 00 10K_0 40 2_ 5%
1 2
R2 02 10K_0 40 2_ 5%
1 2
R2 09 10K_0 40 2_ 5%
1 2
Q6 A
2N 7 002DWH _SOT3 63 -6
SM B CL K
6 1
2
Q6 B
2N 7 002DWH _SOT3 63 -6
SM BD ATA
+3 VS
61
3 4
R1 14 6 0_0402_5%@
1 2
R1 14 7 0_0402_5%@
1 2
SM L 1_CL K_ R
5
SM L 1C LK
SM BDATA
Q7 A
2N 7 002DWH _SOT3 63 -6
SM B CL K SM BD ATA
2
Q7 B
2N 7 002DWH _SOT3 63 -6
SM L 1DATA
+3 VALW +3 VS
5
XTAL25_IN XTAL25_OUT
SM L 1_DA TA_ R
34
Thi s c irc ui t w ill ad d/d ele te i n I NTE L E S2 sample to test.
@
1 2
R2 15 1M_ 04 02 _5%
Y4
1 2
@
25 M HZ_20P_ 1B G2 50 00 CK1 A
18 P_0 40 2_ 50 V8J
C2 26
1
@
2
SM B CL K
+3 VS +3 V AL W
SM BD ATA SM L 0C LK SM L 0DATA
SM L 1ALER T# SM L 0ALER T# L_ L ID_ SW # SM L 1C LK SM L 1DATA
SM B _C LK_S3
SM B _D ATA _S3
R9 13 0 _0 40 2_ 5%
1 2
Q7 6A
2N 7 002DWH _SOT3 63 -6
6 1
R2 01 2 .2 K_0402_5% R2 03 2 .2 K_0402_5% R2 05 2 .2 K_0402_5% R2 07 2 .2 K_0402_5%
200 9/0 2/2 0 HP DB-2
R2 11 1 0K_0402_5% R9 58 1 0K_0402_5% R9 59 1 0K_0402_5% R1 09 2 4.7 K_0402_5% R1 09 3 4.7 K_0402_5%
200 9/0 2/2 0 HP DB-2
SM L 1C LK SM L 1DATA
1 2 1 2 1 2 1 2
1 2 1 2
200 9/0 8/3 0 HP PV
1 2 1 2 1 2
SM B_CL K_ S3 4, 9, 10 ,11,32SM BCLK
SM B_DA TA_ S3 4 ,9 ,10,11,32
CA P _CLK 31,3 5
SM L1 _C LK 20
200 9/0 1/2 0 int el WoW
2
Q7 6B
2N 7 002DWH _SOT3 63 -6
3 4
SM L 1_ DAT A 20
5
R9 14 0 _0 40 2_ 5%
1 2
18 P_0 40 2_ 50 V8J
C2 2 7
1
200 9/0 4/1 0 HP DB-3
2
the P/ N i s cha ged to SD028000080
CA P _DAT 3 1,35
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
IBEX-M(2/6)-PCI-E/SMBUS/CLK
LA -490 1 P
5
13 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
2
3
4
5
DM I_ CTX_P RX_ N05 DM I_ CTX_P RX_ N15 DM I_ CTX_P RX_ N25 DM I_ CTX_P RX_ N35
DM I_ CTX_P RX_ P05 DM I_ CTX_P RX_ P15 DM I_ CTX_P RX_ P25
A A
B B
DM I_ CTX_P RX_ P35
DM I_ CR X_PTX_ N05 DM I_ CR X_PTX_ N15 DM I_ CR X_PTX_ N25 DM I_ CR X_PTX_ N35
DM I_ CR X_PTX_ P05 DM I_ CR X_PTX_ P15 DM I_ CR X_PTX_ P25 DM I_ CR X_PTX_ P35
+1 .0 5VS
1 2
R2 27 49 .9_0402_1%
XD P _DB RES ET#4, 12
VG AT E35 ,4 6
M_ P WR O K37
PM _ DR A M_ P WR GD4 RP G O OD42
PM _ RS MRS T#35
+3 V AL W
SU S _PW R _ACK35 PM _ PW R BTN# _R4 ,12
ON / O FF B TN#31
AC _ PRE SE NT20,3 5
DM I _C TX_ PRX _N 0 DM I _C TX_ PRX _N 1 DM I _C TX_ PRX _N 2 DM I _C TX_ PRX _N 3
DM I _C TX_ PRX _P0 DM I _C TX_ PRX _P1 DM I _C TX_ PRX _P2 DM I _C TX_ PRX _P3
DM I _C RX_ PTX _N 0 DM I _C RX_ PTX _N 1 DM I _C RX_ PTX _N 2 DM I _C RX_ PTX _N 3
DM I _C RX_ PTX _P0 DM I _C RX_ PTX _P1 DM I _C RX_ PTX _P2 DM I _C RX_ PTX _P3
DM I _IR C OMP
SY S _R ST#
1 2
R2 28 0_04 02 _5 %
R2 32 0 _0 40 2_ 5% R2 33 1 0K_0402_5%
R1 06 3 10K_0402_5%
R2 34 0_ 0402_5%
200 8/1 2/0 6 fol low UMA
VG A TE
1 2
R2 3 0 0_0402_5%
1 2
R2 3 1 0_0402_5%
PM _ DR A M_ P W RG D
1 2 1 2
1 2
1 2
LO W _ BAT#_ R
I BEX _R#
AU X PW R OK
U 4 C
BC24
DMI0RXN
BJ22
DMI1RXN
AW20
DMI2RXN
BJ20
DMI3RXN
BD24
DMI0RXP
BG22
DMI1RXP
BA20
DMI2RXP
BG20
DMI3RXP
BE22
DMI0TXN
BF21
DMI1TXN
BD20
DMI2TXN
BE18
DMI3TXN
BD22
DMI0TXP
BH21
DMI1TXP
BC20
DMI2TXP
BD18
DMI3TXP
BH25
DMI_ZCOMP
BF25
DMI_IRCOMP
T6
SYS_RESET#
M6
SYS_PWROK
B17
PWROK
K5
MEPWROK
A10
LAN_RST#
D9
DRAMPWROK
C16
RSMRST#
M1
SUS_PWR_ACK / GPIO30
P5
PWRBTN#
P7
ACPRESENT / GPIO31
A6
BATLOW# / GPIO72
F14
RI#
IB E XP EA K-M_FCBG A1071
DMI
FDI
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
System Power Management
FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7
FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7
FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1
WAKE#
SLP_S4#
SLP_S3#
SLP_M#
TP23
PMSYNCH
SLP_LAN#
BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12
BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12
R1 16 5 1K_0402_5%
BJ14
1 2
R1 16 6 1K_0402_5%
1 2
BF13
R1 16 7 1K_0402_5%
1 2
BH13
R1 16 8 1K_0402_5%
1 2
BJ12
R1 16 9 1K_0402_5%
1 2
BG14
PC I E_ W A KE#
J12
PM _ CL K R UN#
Y1
SU S _STAT #
P8
SU S _ CL K
F3
E4
H7
P12
K8
N2
BJ10
PM _ SL P_ LAN#
F6
PC I E_ W AK E# 2 8,31
PM _ CL K RU N# 3 0, 33 ,3 5,36
T142
200 9/0 8/3 0 HP PV
T30
SL P_ S5 # 34
SL P_ S4 # 38,45
SL P_ S3 # 31,35 ,3 7, 38 ,4 0,42,43,4 4,48
PM _S LP_M# 35 ,3 7, 38
H_ P M_ S Y NC 4
PM _ SLP_L AN# 35 ,38,45
1K_ 04 02 _0 .5 %
12
R2 35
U 4 D
T48
L_BKLTEN
T47
L_VDD_EN
Y48
L_BKLTCTL
AB48
L_DDC_CLK
Y45
L_DDC_DATA
AB46
L_CTRL_CLK
V48
L_CTRL_DATA
AP39
LVD_IBG
AP41
LVD_VBG
AT43
LVD_VREFH
AT42
LVD_VREFL
AV53
LVDSA_CLK#
AV51
LVDSA_CLK
BB47
LVDSA_DATA#0
BA52
LVDSA_DATA#1
AY48
LVDSA_DATA#2
AV47
LVDSA_DATA#3
BB48
LVDSA_DATA0
BA50
LVDSA_DATA1
AY49
LVDSA_DATA2
AV48
LVDSA_DATA3
AP48
LVDSB_CLK#
AP47
LVDSB_CLK
AY53
LVDSB_DATA#0
AT49
LVDSB_DATA#1
AU52
LVDSB_DATA#2
AT53
LVDSB_DATA#3
AY51
LVDSB_DATA0
AT48
LVDSB_DATA1
AU50
LVDSB_DATA2
AT51
LVDSB_DATA3
AA52
CRT_BLUE
AB53
CRT_GREEN
AD53
CRT_RED
V51
CRT_DDC_CLK
V53
CRT_DDC_DATA
Y53
CRT_HSYNC
Y51
CRT_VSYNC
AD48
DAC_IREF
AB51
CRT_IRTN
IB E XP EAK -M_ FCBGA 10 71
SDVO_INTN SDVO_INTP
DDPB_AUXN DDPB_AUXP
DDPB_HPD
DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P
DDPC_AUXN DDPC_AUXP
DDPC_HPD
DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P
DDPD_AUXN DDPD_AUXP
DDPD_HPD
DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P
BJ46 BG46
BJ48 BG48
BF45 BH45
T51 T53
BG44 BJ44 AU38
BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38
Y49 AB49
BE44 BD44 AV40
BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36
U50 U52
BC46 BD46 AT38
BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36
SDVO_TVCLKINN SDVO_TVCLKINP
SDVO_STALLN SDVO_STALLP
SDVO_CTRLCLK
SDVO_CTRLDATA
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
CRT
VG A TE
C C
S LP_ S3 # P M_S LP_M# AU X PW R OK SU S _PW R _ AC K PM _ R SMR ST# M_ P WR OK
D D
T12 0 T12 1 T12 2 T12 3 T12 4 T12 5 T12 6
1
PM _ CL K R UN#
SY S _R ST# LO W _ BAT#_ R PM _ SL P_ LAN# I BEX _R# PC I E_ W A KE#
R2 3 7 10 K_0 40 2_ 5%
1 2
R2 3 9 10 K_0 40 2_ 5%@
1 2
R2 4 0 10 K_0 40 2_ 5%
1 2
R2 4 1 10 K_0 40 2_ 5%
1 2
R2 4 2 10 K_0 40 2_ 5%
1 2
200 9/0 9/1 5 HP SI-2b
R2 4 3 10 K_0 40 2_ 5%
1 2
R9 1 8 10 K_0 40 2_ 5%@
1 2
200 9/0 5/1 6 HP SI-1
+3 VS
+3 V AL W
200 9/0 1/2 2 HP DB-2
VG A TE
S LP_ S3 # S LP_ S4 # S LP_ S5 #AC_ P R E SEN T
2
R2 29 1 0K_0402_5%
1 2
R9 15 1 0K_0402_5%@
1 2
R9 16 1 0K_0402_5%@
1 2
R9 17 1 0K_0402_5%@
1 2
Security Classification
Issued Date
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
IBEX-M(3/6)-DMI/GPIO/LVDS
LA- 4901P
5
14 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
PC I _ AD [0 ..3 1]30
A A
PC I _ CBE 0#30 PC I _ CBE 1#30 PC I _ CBE 2#30 PC I _ CBE 3#30
PC I _ REQ 2#30
B B
C C
PC I _ STO P# PC I _ TR D Y# PC I _ D EVS EL# PC I _ FR A ME#
PC I _ LOCK # PC I _ RE Q0 # PC I _ P IRQB# OD D _ DET#
PC I _ P IRQA# PC I _ P IRQD# PC I _ RE Q3 # PC I _ P ERR #
D D
200 9/0 7/0 2 HP SI-1b
PC I _ RE Q2 # PC I _ RE Q1 # AC C E L_ IN T# PC I _ S ERR #
PC I _ P IRQE# PC I _ PI RQ G# PC I _ P IRQC# PC I _ IR D Y#
MO D EM _DIS ABL E# PC I _G NT2 #30
PC I _ PI RQ E#30 OD D _ DET#29
PC I _ PIR QG #30 AC C EL _I NT#32
PC I _R ST#28 ,3 0 PC I _ SE RR#30,33,35
PC I _ PE RR#30
PC I _ IR D Y#30 PC I _ PAR30 PC I _ DE VSE L#30 PC I _ FR AME#30
PC I _S TOP #30 PC I _ TR DY #30
PL T_RST#4,12,20 ,2 6, 28 ,3 1,33
200 9/0 3/2 3 Com pal DB-3
RP 59
1 8 2 7 3 6 4 5
8. 2K _0 80 4_ 8P4R_ 5% R P 6
1 8 2 7 3 6 4 5
8. 2K _0 80 4_ 8P4R_ 5% R P 8
1 8 2 7 3 6 4 5
8. 2K _0 80 4_ 8P4R_ 5%
R P 7
1 8 2 7 3 6 4 5
8. 2K _0 80 4_ 8P4R_ 5% R P 9
1 8 2 7 3 6 4 5
8. 2K _0 80 4_ 8P4R_ 5%
+3 VS
1
PC I _ AD 0 PC I _ AD 1 PC I _ AD 2 PC I _ AD 3 PC I _ AD 4 PC I _ AD 5 PC I _ AD 6 PC I _ AD 7 PC I _ AD 8 PC I _ AD 9 PC I _ AD 10 PC I _ AD 11 PC I _ AD 12 PC I _ AD 13 PC I _ AD 14 PC I _ AD 15 PC I _ AD 16 PC I _ AD 17 PC I _ AD 18 PC I _ AD 19 PC I _ AD 20 PC I _ AD 21 PC I _ AD 22 PC I _ AD 23 PC I _ AD 24 PC I _ AD 25 PC I _ AD 26 PC I _ AD 27 PC I _ AD 28 PC I _ AD 29 PC I _ AD 30 PC I _ AD 31
PC I _ P IRQA# PC I _ P IRQB# PC I _ P IRQC# PC I _ P IRQD#
PC I _ RE Q0 # PC I _ RE Q1 # PC I _ RE Q2 # PC I _ RE Q3 #
PC I _ GNT0#
MO D EM _ DI SAB LE#
PC I _ GNT2# PC I _ GNT3#
PC I _ P IRQE# OD D _ DET# PC I _ PI RQ G# AC C E L_ IN T#
PC I _ RS T# PC I _ S ERR #
PC I _ P ERR #
PC I _ IR D Y# PC I _ P AR PC I _ D EVS EL# PC I _ FR A ME#
PC I _ LOCK # PC I _ STO P#
PC I _ TR D Y#
CL K _ PC I _ KBC _R CL K _ PC I_FB_R CL K _ P CI_TP M_R CL K _ PCI _1 39 4_ R CL K _ P CI_DB _P
U4 E
H40
AD0
N34
AD1
C44
AD2
A38
AD3
C36
AD4
J34
AD5
A40
AD6
D45
AD7
E36
AD8
H48
AD9
E40
AD10
C40
AD11
M48
AD12
M45
AD13
F53
AD14
M40
AD15
M43
AD16
J36
AD17
K48
AD18
F40
AD19
C42
AD20
K46
AD21
M51
AD22
J52
AD23
K51
AD24
L34
AD25
F42
AD26
J40
AD27
G46
AD28
F44
AD29
M47
AD30
H36
AD31
J50
C/BE0#
G42
C/BE1#
H47
C/BE2#
G34
C/BE3#
G38
PIRQA#
H51
PIRQB#
B37
PIRQC#
A44
PIRQD#
F51
REQ0#
A46
REQ1# / GPIO50
B45
REQ2# / GPIO52
M53
REQ3# / GPIO54
F48
GNT0#
K45
GNT1# / GPIO51
F36
GNT2# / GPIO53
H53
GNT3# / GPIO55
B41
PIRQE# / GPIO2
K53
PIRQF# / GPIO3
A36
PIRQG# / GPIO4
A48
PIRQH# / GPIO5
K6
PCIRST#
E44
SERR#
E50
PERR#
A42
IRDY#
H44
PAR
F46
DEVSEL#
C46
FRAME#
D49
PLOCK#
D41
STOP#
C48
TRDY#
M7
PME#
D5
PLTRST#
N52
CLKOUT_PCI0
P53
CLKOUT_PCI1
P46
CLKOUT_PCI2
P51
CLKOUT_PCI3
P48
CLKOUT_PCI4
IB E XP EAK -M_ FCBGA 10 71
CL K _ PCI _S IO36 CL K _ PC I_ KBC35 CL K _ PC I _D EBU G28 CL K _ PC I_ DB33
CL K _ PC I_ FB13 CL K _ PCI _T PM33
CL K_PC I_ 13 9430
TH E RM _ SCI#
PC I _ GNT3#
R1 02 8 8.2K_ 04 02 _5%
1 2
R2 87 1K_ 04 02 _5 %@
1 2
A16 sw ap ov eri de Str ap/Top-Block Swa p O ver ri de jumper
Low =A1 6 swap ove rri de/ To p-Block
PCI _GN T3#
Swa p O ver ri de enabled Hig h=D efault
PCI
NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11
NVRAM
NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15
NV_WR#0_RE# NV_WR#1_RE#
NV_WE#_CK0 NV_WE#_CK1
USB
OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43
OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14
+3 VS
2
AY9
NV_CE#0
BD1
NV_CE#1
AP15
NV_CE#2
BD8
NV_CE#3
AV9
NV_DQS0
BG8
NV_DQS1
AP7 AP6
200 9/0 8/3 0 HP PV
AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6
NV _ ALE
BD3
NV_ALE NV_CLE
NV_RCOMP
NV_RB#
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N
USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P
USBRBIAS#
USBRBIAS
C9 5 1 2 2P _0 40 2_ 50 V8J
@
NV _ C LE
AY6
1 2
AU2
R2 51 32.4 _0 40 2_ 1%
AV7 AY8
AY5 AV11
BF5
US B 20_N0
H18
US B 20 _P0
J18
US B 20_N1
A18
US B 20 _P1
C18
US B 20_N2
N20
US B 20 _P2
P20
US B 20_N3
J20
US B 20 _P3
L20
US B 20_N4
F20
US B 20 _P4
G20 A20 C20 M22 N22 B21 D21
US B 20_N8
H22
US B 20 _P8
J22
US B 20_N9
E22
US B 20 _P9
F22
US B 20_N10
A22
US B 20 _P10
C22
US B 20_N11
G24
US B 20 _P11
H24
US B 20_N12
L24
US B 20 _P12
M24
US B 20_N13
A24
US B 20 _P13
C24
US B RB I AS
B25 D25
Within 500 mils
US B _ OC #0
N16
US B _ OC #1
J16
US B _ OC #2
F16
US B _ OC #3
L16
US B _ OC #4
E14
US B _ OC #5
G16
US B _ OC #6
F12
US B _ OC #7
T15
200 9/0 7/2 3 Add Ca p. SI- 2 Compal RF 200 9/1 1/0 2 Del Ca p. MV Compal RF
C9 5 3 2 2P _0 40 2_ 50 V8J
C9 5 4 2 2P _0 40 2_ 50 V8J
C9 5 2 2 2P _0 40 2_ 50 V8J
1
1
1
1
@
@
@
2
2
2
2
BU F _P L T_R ST#4
2
@
1 2
R2 52 22 .6_0402_1%
C9 5 6 2 2P _0 40 2_ 50 V8J
C9 5 5 2 2P _0 40 2_ 50 V8J
1
1
@
@
@
2
2
200 9/0 2/1 9 HP DB-2
200 9/0 8/3 0 HP PV
US B 20 _N0 32 US B2 0_ P0 32 US B 20 _N1 32 US B2 0_ P1 32 US B 20 _N2 32 US B2 0_ P2 32 US B 20 _N3 32 US B2 0_ P3 32 US B 20 _N4 31 US B2 0_ P4 31
US B 20 _N8 32 US B2 0_ P8 32 US B 20 _N9 28 US B2 0_ P9 28 US B2 0_ N1 0 33 US B2 0_ P1 0 33 US B2 0_ N1 1 34 US B2 0_ P1 1 34 US B2 0_ N1 2 19 US B2 0_ P1 2 19 US B2 0_ N1 3 34 US B2 0_ P1 3 34
US B _OC# 0 12 US B _OC# 1 12 US B _OC# 2 12 US B _OC# 3 12 US B _OC# 4 12 US B _OC# 5 12 US B _OC# 6 12 US B _OC# 7 12
C9 4 9 2 2P _0 40 2_ 50 V8J
1
2
1 2
R2 74 0_04 02 _5%
4
O
+3 VS
200 9/0 1/2 0 HP
CONN CONN CONN CONN EXPRESS
Bluetooth WWAN Fingerprint DOCK USB Camera DOCK
200 9/0 1/2 1 Int el WoW
R9 19 2 2_ 04 02 _5%
1 2
R9 20 2 2_ 04 02 _5%
1 2
R9 21 2 2_ 04 02 _5%
1 2
R9 22 2 2_ 04 02 _5%
1 2
R9 23 2 2_ 04 02 _5%
1 2
R9 24 2 2_ 04 02 _5%
1 2
R9 25 2 2_ 04 02 _5%
1 2
+3 VS
5
P
IN1 IN2
G
U 5
3
SN 7 4 AH C 1 G0 8D CKR _SC70-5
PL T _R ST#
1 2
@
3
R2 44 10K_0 40 2_ 5%
1 2
PC H _ XDP _G PIO 012 OC P#47
RU N SCI _ EC #35 TH E RM _S CI#4 PC H _ DD R _ RST4,5
200 9/0 7/0 2 HP SI-1b
LA N _D IS#26,27
PC H _ XDP _G PIO 1612 AL S_ EN #19 WW A N_D E T#28
200 9/0 4/1 0 HP DB-3
WW A N_T R AN S MI T_OFF#28 ,3 3 PC H _ XDP _G PIO 2812 ST P_PC I# SA TA_ CLKRE Q# PC H _ XDP _G PIO 3612 PC H _ XDP _G PIO 3712 ,19 DO C K _I D034 DO C K _I D134 CL K _ PC IE_L AN _REQ#26
200 8/1 2/1 2 HP
PC H _ XDP _G PIO 4912 WL A N _T R AN SMIT_ OF F#28
PC H _ NC TF 617 PC H _ NC TF 717
PC H _ NC TF 1917
PC H _ NC TF 2617
CL K _ PC I _ KBC _R
CL K _ P CI_DB _P CL K _ PC I_FB_R CL K _ P CI_TP M_R
CL K _ PCI _1 39 4_ R
US B _ OC #7 US B _ OC #6 US B _ OC #5
US B _ OC #1 US B _ OC #2 US B _ OC #3 PC H _ XD P_GPI O3 6
PC I _ GNT0# MO D EM _ DI SAB LE#
R1 22 7 0_0402_5% R1 13 9 0_0402_5% R1 09 7 0_0402_5%
R1 00 4 0_0402_5% R1 00 5 0_0402_5% R1 00 6 0_0402_5% R1 00 7 0_0402_5%
Security Classification
Issued Date
3
PC H _ XD P_GPI O0
RU N SCI _ EC# TH E RM _ SCI#
200 9/0 4/1 0 HP DB-3
G PIO15 PC H _ XD P_GPI O1 6 AL S _ EN# WW A N_D E T# G PIO24 WW A N_T R AN S M IT_ OF F#
ST P _P CI# SA TA_ C LK REQ # PC H _ XD P_GPI O3 6 PC H _ XD P_GPI O3 7 DO C K _ ID 0 DO C K _ ID 1
G PIO46 G PIO48 PC H _ XD P_GPI O4 9 WL A N _T R AN SMI T_O FF#
200 9/0 7/2 1 HP SI-2
1 2 1 2 1 2
1 2 1 2 1 2 1 2
R2 54 1 K_0402_5%@
1 2
R2 59 1 K_0402_5%@
1 2
U 4 F
Y3
BMBUSY# / GPIO0
C38
TACH1 / GPIO1
D37
TACH2 / GPIO6
J32
TACH3 / GPIO7
F10
GPIO8
K9
LAN_PHY_PWR_CTRL / GPIO12
T7
GPIO15
AA2
SATA4GP / GPIO16
F38
TACH0 / GPIO17
Y7
SCLOCK / GPIO22
H10
MEM_LED / GPIO24
AB12
GPIO27
V13
GPIO28
M11
STP_PCI# / GPIO34
V6
SATACLKREQ# / GPIO35
AB7
SATA2GP / GPIO36
AB13
SATA3GP / GPIO37
V3
SLOAD / GPIO38
P3
SDATAOUT0 / GPIO39
H3
PCIECLKRQ6# / GPIO45
F1
PCIECLKRQ7# / GPIO46
AB6
SDATAOUT1 / GPIO48
AA4
SATA5GP / GPIO49
F8
GPIO57
A4
VSS_NCTF_1
A49
VSS_NCTF_2
A5
VSS_NCTF_3
A50
VSS_NCTF_4
A52
VSS_NCTF_5
A53
VSS_NCTF_6
B2
VSS_NCTF_7
B4
VSS_NCTF_8
B52
VSS_NCTF_9
B53
VSS_NCTF_10
BE1
VSS_NCTF_11
BE53
VSS_NCTF_12
BF1
VSS_NCTF_13
BF53
VSS_NCTF_14
BH1
VSS_NCTF_15
BH2
VSS_NCTF_16
BH52
VSS_NCTF_17
BH53
VSS_NCTF_18
BJ1
VSS_NCTF_19
BJ2
VSS_NCTF_20
BJ4
VSS_NCTF_21
BJ49
VSS_NCTF_22
BJ5
VSS_NCTF_23
BJ50
VSS_NCTF_24
BJ52
VSS_NCTF_25
BJ53
VSS_NCTF_26
D1
VSS_NCTF_27
D2
VSS_NCTF_28
D53
VSS_NCTF_29
E1
VSS_NCTF_30
E53
VSS_NCTF_31
IB E XP EAK -M_ FCBGA 10 71
200 9/0 1/2 2 HP
CP P E# 31 LE D _ LIN K_LAN #_ R 26, 27 IS O _ PRE P# 34
BT _ OFF 32 WE B CA M _OF F F PR_ O FF 33 NP C I_R ST# 3 5, 36
PCI _GN T0#
0 0 1 1 1
2008/09/15 2009/12/31
Compal Secret Data
4
CLKOUT_PCIE6N CLKOUT_PCIE6P
CLKOUT_PCIE7N
MISC
CLKOUT_PCIE7P
CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLKOUT_BCLK0_P / CLKOUT_PCIE8P
GPIO
CPU
NCTF
RSVD
Dan bur y T ec hno log y Enable NV_ ALE H igh =E nda bled
Low =Di sab le (@)
NV _ ALE
R2 70 1K_ 04 02 _5 %@
DMI Te rmi na tio n Voltage NV_ CLE S et to Vs s w hen LOW
Set to Vc c whe n HIGH
NV _ C LE
R2 83 1K_ 04 02 _5 %@
Boo t B IOS Strap
MOD EM_ DIS ABLE# B oot BI OS Location
Deciphered Date
LPC*
0 1
Res erv ed( NAND) PCI
0
SPI
4
A20GATE
PROCPWRGD
THRMTRIP#
INIT3_3V#
1 2
1 2
AH45 AH46
AF48 AF47
U2
AM3 AM1 BG10
PECI
T1
RCIN#
BE10 BD10
BA22
TP1
AW22
TP2
BB22
TP3
AY45
TP4
AY46
TP5
AV43
TP6
AV45
TP7
AF13
TP8
M18
TP9
N18
TP10
AJ24
TP11
AK41
TP12
AK42
TP13
M32
TP14
N32
TP15
M30
TP16
N30
TP17
H12
TP18
AA23
TP19
AB45
NC_1
AB38
NC_2
AB42
NC_3
AB41
NC_4
T39
NC_5
P6 C10
TP24
+V _ NVR A M_V CCQ
+3 VS
200 9/0 7/2 2 HP SI-2
5
R2 23
CL K _ PC IE_ LA N#_R CL K _ PC IE_ LA N_R
PC H _ PE C I_R KB _ RST#
H_ T HERMTR IP#_L
T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 T48 T49 T50 T51 T52 T53 T54 T55 T56
T57 T58
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
0_ 0402_5%
1 2
0_ 0402_5%
1 2
R2 25
R2 4710 K_0 40 2_ 5%
1 2
1 2
1 2
R2 495 4.9_0402_1%
R2 50
56 _0402_5%
LA N _ DI S#
NP C I_ RST #
SA TA_ C LK REQ #
PC H _ XD P_GPI O4 9
WW A N_D E T#
AL S _ EN#
RU N SCI _ EC#
PC H _ XD P_GPI O1 6
DO C K _ ID 0
DO C K _ ID 1
G PIO48
ST P _P CI#
KB _ RST#
200 9/0 1/2 0 For BIOS
US B _ OC #2
WL A N _T R AN SMI T_O FF#
WW A N_T R AN S M IT_ OF F#
G PIO24
G PIO15
200 9/0 2/0 6 HP DB-2
IS O _ PR EP#
CL K _ PC I E_LAN_ REQ#
US B _ OC #0
CP P E#
US B _ OC #4
PC H _ XD P_GPI O2 8
200 8/1 2/1 2 HP
G PIO46
LE D _ L IN K_LAN #_ R
200 9/0 2/0 6 HP DB-2
CL K _ PC IE_LAN# 26 CL K _ PC IE_LAN 26
+3 VS
GA TEA 20 35
CL K _ CP U_BC LK# 4 CL K _ CP U_BC LK 4
R2 480_ 0402_5%
H_ P ECI 4 KB _R ST# 35 H_ C P UP W RGD 4 H_ T HER MTRIP# 4 ,2 0
12
+V C CP
200 9/0 4/1 0 HP DB-3
R2 86 10K_0 40 2_ 5%
1 2
R2 55 10K_0 40 2_ 5%
1 2
R2 60 10K_0 40 2_ 5%
1 2
R2 64 10K_0 40 2_ 5%
1 2
R2 66 100K_ 04 02 _5%
1 2
R2 68 10K_0 40 2_ 5%
1 2
R2 71 10K_0 40 2_ 5%
1 2
200 9/0 6/0 9 HP SI-2
R2 76 10K_0 40 2_ 5%
1 2
R2 78 10K_0 40 2_ 5%
1 2
R2 80 10K_0 40 2_ 5%
1 2
R2 82 10K_0 40 2_ 5%
1 2
R2 85 10K_0 40 2_ 5%
1 2
R6 94 10K_0 40 2_ 5%
1 2
200 9/0 5/0 2 HP SI-1
R1 19 3 10K_0 40 2_ 5%
1 2
R2 57 10K_0 40 2_ 5%
1 2
R2 62 10K_0 40 2_ 5%
1 2
R2 65 10K_0 40 2_ 5%
1 2
R2 67 1K_ 04 02 _5 %
1 2
R2 69 10K_0 40 2_ 5%
1 2
R2 72 10K_0 40 2_ 5%
1 2
R2 75 10K_0 40 2_ 5%
1 2
R2 79 10K_0 40 2_ 5%
1 2
R2 81 10K_0 40 2_ 5%
1 2
200 9/0 4/1 0 HP DB-3
R1 09 9 10K_0 40 2_ 5%
1 2
R4 98 10K_0 40 2_ 5%
1 2
R1 14 2 10K_0 40 2_ 5%
1 2
Compal Electronics, Inc.
IBEX-M(4/6)-PCI/USB/RSVD
LA -490 1 P
5
15 54T u esd ay , Dec ember 15, 2 00 9
LAN
+3 VM_L AN
+3 VS
+3 V AL W
1. 0
1
2
3
4
5
+1. 05 VS
1U _0 60 3_ 10 V4 Z
C2 31
C2 30
1
1
2
2
+1 .0 5VS
T11 4
200 9/0 1/2 2 HP DB-2
+1. 05 VS
1U_0402_6.3 V6 K
C2 4 7
C2 4 8
1
1
2
2
1U_0402_6.3 V6 K
1U_0402_6.3 V6 K
C2 51
C2 52
1
2
1 2
1 2
T11 7
1 2
1U_0402_6.3 V6 K
1 2
1U_0402_6.3 V6 K
C2 53
1
2
+3 VS
C8 8 10.1 U_ 04 02 _1 6V4 Z @
L5
C2 68
@
L6
C2 74
@
1
2
R6 74 0_0402_5%
+1 .0 5VS
10 UH_ LB 20 12 T10 0M R_ 20 %_0 80 5
10 UH_ LB 20 12 T10 0M R_ 20 %_0 80 5
+1 .0 5VM
1U_0402_6.3 V6 K
1
C2 35
2
A A
B B
C C
T59
200 9/0 2/0 5 HP DB-2
1 2
C2 59
1 2
C2 60
1 2
C2 64
1 2
C2 66
+R T CV CC
200 8/1 2/0 6 fol low UMA
0. 1U _0 40 2_ 16 V4Z
0. 1U _0 40 2_ 16 V4Z
0. 1U _0 40 2_ 16 V4Z
0. 1U _0 40 2_ 16 V4Z
C9 11
T11 2 T11 3
200 9/0 1/2 2 HP DB-2
1 2
C2 37 0 .1U_ 04 02 _1 6V 4Z
+1 .0 5VM
22 U_0805_6.3V 6M
22 U_0805_6.3V 6M
C2 44
C2 43
1
1
2
2
C2 46
+V C C RTCEXT
1 2
0. 1U _0 40 2_ 16 V4Z
+1 .8 VS
+V 1 .0 5S _VC CA_A_ DP L
+V 1 .0 5S _VC CA_B_ DP L
+1 .0 5VS
1U_0402_6.3 V6 K
1U_0402_6.3 V6 K
C2 55
C2 56
C2 57
1
1
2
2
+V 1 .1A _ I NT_ VCCSU S
+3 VALW
0. 2 A
0. 2 A@ 3.3 V
0. 2 A0. 2 A
+3 VS
0. 4 A
0. 4 A@ 3.3 V
0. 4 A0. 4 A
+V C CP
0. 1 A
0. 1 A@ 1.1 V
0. 1 A0. 1 A
4.7U_ 06 03 _6 .3 V6 K C2 71
C2 70
1
1
2
2
2m A @
2m A @3 .3V
2m A @2m A @
1U_0402_6.3 V6 K
0. 1U _0 40 2_ 16 V4Z
C2 77
C2 76
1
1
2
2
C2 40
C2 45
1
2
+V C C SST
@3. 3V
@3. 3V@3. 3V
@3. 3V
@3. 3V@3. 3V
@1. 1V
@1. 1V@1. 1V
0. 1U _0 40 2_ 16 V4Z
3.3 V
3.3 V3.3 V
1
2
1U_0402_6.3 V6 K
1
2
1U_0402_6.3 V6 K
1
2
1U_0402_6.3 V6 K
0. 1U _0 40 2_ 16 V4Z
C2 72
1
2
0. 1U _0 40 2_ 16 V4Z
U 4 J
AP51
VCCACLK[1]
AP53
VCCACLK[2]
AF23
VCCLAN[1]
AF24
VCCLAN[2]
Y20
DCPSUSBYP
AD38
VCCME[1]
AD39
VCCME[2]
AD41
VCCME[3]
AF43
VCCME[4]
AF41
VCCME[5]
AF42
VCCME[6]
V39
VCCME[7]
V41
VCCME[8]
V42
VCCME[9]
Y39
VCCME[10]
Y41
VCCME[11]
Y42
VCCME[12]
V9
DCPRTC
AU24
VCCVRM[3]
BB51
VCCADPLLA[1]
BB53
VCCADPLLA[2]
BD51
VCCADPLLB[1]
BD53
VCCADPLLB[2]
AH23
VCCIO[21]
AJ35
VCCIO[22]
AH35
VCCIO[23]
AF34
VCCIO[2]
AH34
VCCIO[3]
AF32
VCCIO[4]
V12
DCPSST
Y22
DCPSUS
P18
VCCSUS3_3[29]
U19
VCCSUS3_3[30]
U20
VCCSUS3_3[31]
U22
VCCSUS3_3[32]
V15
VCC3_3[5]
V16
VCC3_3[6]
Y16
VCC3_3[7]
AT18
V_CPU_IO[1]
AU18
V_CPU_IO[2]
A12
VCCRTC
IB E XP EA K-M_FCBG A1071
0.035A
0.072A
0.073A
>1mA
0.052A
0.344A
1.998A
3.208A
2mA
POWER
USB
Clock and Miscellaneous
PCI/GPIO/LPC
0.032A
SATA
CPU
RTC PCI/GPIO/LPC
0.163A
>1mA
>1mA
0.357A
6mA
HDA
VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8]
VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8]
VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCSUS3_3[21] VCCSUS3_3[22] VCCSUS3_3[23] VCCSUS3_3[24] VCCSUS3_3[25] VCCSUS3_3[26] VCCSUS3_3[27]
VCCSUS3_3[28]
VCCIO[56]
V5REF_SUS
V5REF
VCC3_3[8]
VCC3_3[9] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13]
VCC3_3[14]
VCCSATAPLL[1] VCCSATAPLL[2]
VCCIO[9]
VCCVRM[4]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCME[13] VCCME[14] VCCME[15] VCCME[16]
VCCSUSHDA
V24 V26 Y24 Y26
V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26
U23 V23 F24
K49
J38 L38 M36 N36 P36 U35
AD13
AK3 AK1
AH22
AT20
AH19 AD20 AF22 AD19
AF20 AF19 AH20
AB19 AB20 AB22 AD22
AA34 Y34 Y35 AA35
L30
+1 .0 5VS
1
C2 36 1U_0402_6.3 V6 K
2
+3 V AL W
0. 1U _0 40 2_ 16 V4Z
C2 38
1
2
+1 .0 5VS
IC H _ V5 R E F_ SUS
IC H _ V5 R E F_ R UN
+3 VS
1
C2 50
0. 1U _0 40 2_ 16 V4Z
2
+3 VS
1 2
C2 58 0.1U _0 40 2_ 16 V4 Z
T115 T116
200 9/0 1/2 2 HP DB-2
+1 .8 VS
+P C H _V CC1_1 _2 0 +P C H _V CC1_1 _2 1 +P C H _V CC1_1 _2 2 +P C H _V CC1_1 _2 3
+V C CSU SHD A
1
C2 7 5 1U _0 40 2_ 6. 3V6K
2
0. 1U _0 40 2_ 16 V4Z
C2 39
1
2
1U _0 40 2_ 6. 3V6K
C2 65
1
2
R2 95 0_04 02 _5 %
1 2
R2 96 0_04 02 _5 %
1 2
R2 97 0_04 02 _5 %
1 2
R2 98 0_04 02 _5 %
1 2
R3 0 1 0_ 0402_5%
1 2
+1 .8 VS
200 9/0 1/2 2 HP DB-2
+1. 05 VS
+1 .0 5VS
+1 .0 5VM
+3 VALW
U4 G
AB24
VCCCORE[1]
AB26
10 U_0805_6.3V 6M
VCCCORE[2]
AB28
VCCCORE[3]
AD26
VCCCORE[4]
AD28
VCCCORE[5]
AF26
VCCCORE[6]
AF28
VCCCORE[7]
AF30
VCCCORE[8]
AF31
VCCCORE[9]
AH26
VCCCORE[10]
AH28
VCCCORE[11]
AH30
VCCCORE[12]
AH31
VCCCORE[13]
AJ30
VCCCORE[14]
AJ31
VCCCORE[15]
AK24
VCCIO[24]
BJ24
VCCAPLLEXP
AN20
VCCIO[25]
AN22
VCCIO[26]
AN23
VCCIO[27]
AN24
VCCIO[28]
AN26
VCCIO[29]
AN28
VCCIO[30]
BJ26
VCCIO[31]
BJ28
VCCIO[32]
AT26
VCCIO[33]
AT28
VCCIO[34]
AU26
VCCIO[35]
AU28
1U_0402_6.3 V6 K
VCCIO[36]
AV26
VCCIO[37]
AV28
VCCIO[38]
AW26
VCCIO[39]
AW28
VCCIO[40]
BA26
VCCIO[41]
BA28
VCCIO[42]
BB26
VCCIO[43]
BB28
VCCIO[44]
BC26
VCCIO[45]
BC28
10 U_0805_6.3V 6M
VCCIO[46]
BD26
VCCIO[47]
BD28
VCCIO[48]
BE26
VCCIO[49]
BE28
VCCIO[50]
BG26
VCCIO[51]
BG28
VCCIO[52]
BH27
VCCIO[53]
AN30
VCCIO[54]
AN31
VCCIO[55]
AN35
VCC3_3[1]
AT22
VCCVRM[1]
BJ18
VCCFDIPLL
AM23
VCCIO[1]
IB E XP EAK -M_ FCBGA 10 71
+V 1 .0 5S _VC CA_A_ DP L
1
1
+
C2 67 22 0U _B 2_ 2.5VM _R15
2
2
+V 1 .0 5S _VC CA_B_ DP L
1
1
+
C2 73 22 0U _B 2_ 2.5VM _R15
2
2
@
@
POWER
1.524A
VCC CORE
0.042A
PCI E*
0.035A 6mA
200 9/0 4/2 4 HP SI-1
0.069A
CRTLVDS
0.030A
0.059A
HVCMOS
0.061A
DMI
0.156A
NAND / SPI
0.085A
FDI
VCCADAC[1]
VCCADAC[2] VSSA_DAC[1] VSSA_DAC[2]
VCCALVDS
VSSA_LVDS
VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4]
VCC3_3[2] VCC3_3[3] VCC3_3[4]
VCCVRM[2]
VCCDMI[1] VCCDMI[2]
VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] VCCPNAND[4] VCCPNAND[5] VCCPNAND[6] VCCPNAND[7] VCCPNAND[8] VCCPNAND[9]
VCCME3_3[1] VCCME3_3[2] VCCME3_3[3] VCCME3_3[4]
+V 1 .05 S_ VCCA_ A_DPL
+V 1 .05 S_ VCCA_ B_DPL
AE50 AE52 AF53 AF51
AH38 AH39
AP43 AP45 AT46 AT45
AB34 AB35 AD35
AT24
AT16 AU16
AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15
AM8 AM9 AP11 AP9
10 0_0402_5%
200 9/0 2/0 3 HP DB-2
+3 V S_V C CDAC
0.01U_0 60 3_ 16 V7K
10 U_0805_6.3V 6M
C2 32
C2 33
1
1
@
+3 VS
+1 .8VS
+V C CP
+V _ NVR A M_V CCQ
R2 99
@
@
2
2
200 9/0 4/1 3 Com pal DB-3
1 2
C2 42 0 .1U_ 04 02 _1 6V 4Z
1 2
C2 49 1 U_0603_10V4Z
R5 08 0 _0 60 3_ 5%
0. 1U _0 40 2_ 16 V4Z
C2 54
1
2
+3 VM
0. 1U _0 40 2_ 16 V4Z
C2 61
1
2
12
21
D 2
CH 7 51 H-40PT_SOD 32 3- 2
1
C2 78 1U_0402_6.3 V6 K
2
1 2
0. 1U _0 40 2_ 16 V4Z MU R AT A_ BLM18 AG 60 1SN 1D _0 60 3
C2 34
1
2
1 2
200 9/0 8/3 0 HP PV
200 9/0 1/2 2 HP DB-2
IC H _ V5 R E F_ SUS
L40
+3 VS
+1 .8 VS
+5 VS + 3V S+3V AL W+ 5 VALW
12
R3 00
10 0_0402_5%
200 9/0 2/0 3 HP DB-2
21
D 3 CH 7 51 H-40PT_SOD 32 3- 2
IC H _ V5 R E F_ R UN
20 mils20 mils
1
C2 7 9 1U _0 40 2_ 6. 3V6K
2
D D
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
IBEX-M(5/6)-PWR
LA -490 1 P
5
16 54T u esd ay , Dec ember 15, 2 00 9
1. 0
1
2
3
4
5
U4 I
AY7
VSS[159]
B11
VSS[160]
B15
VSS[161]
B19
VSS[162]
B23
VSS[163]
B31
VSS[164]
B35
VSS[165]
B39
VSS[166]
B43
VSS[167]
B47
VSS[168]
B7
A A
B B
C C
VSS[169]
BG12
VSS[170]
BB12
VSS[171]
BB16
VSS[172]
BB20
VSS[173]
BB24
VSS[174]
BB30
VSS[175]
BB34
VSS[176]
BB38
VSS[177]
BB42
VSS[178]
BB49
VSS[179]
BB5
VSS[180]
BC10
VSS[181]
BC14
VSS[182]
BC18
VSS[183]
BC2
VSS[184]
BC22
VSS[185]
BC32
VSS[186]
BC36
VSS[187]
BC40
VSS[188]
BC44
VSS[189]
BC52
VSS[190]
BH9
VSS[191]
BD48
VSS[192]
BD49
VSS[193]
BD5
VSS[194]
BE12
VSS[195]
BE16
VSS[196]
BE20
VSS[197]
BE24
VSS[198]
BE30
VSS[199]
BE34
VSS[200]
BE38
VSS[201]
BE42
VSS[202]
BE46
VSS[203]
BE48
VSS[204]
BE50
VSS[205]
BE6
VSS[206]
BE8
VSS[207]
BF3
VSS[208]
BF49
VSS[209]
BF51
VSS[210]
BG18
VSS[211]
BG24
VSS[212]
BG4
VSS[213]
BG50
VSS[214]
BH11
VSS[215]
BH15
VSS[216]
BH19
VSS[217]
BH23
VSS[218]
BH31
VSS[219]
BH35
VSS[220]
BH39
VSS[221]
BH43
VSS[222]
BH47
VSS[223]
BH7
VSS[224]
C12
VSS[225]
C50
VSS[226]
D51
VSS[227]
E12
VSS[228]
E16
VSS[229]
E20
VSS[230]
E24
VSS[231]
E30
VSS[232]
E34
VSS[233]
E38
VSS[234]
E42
VSS[235]
E46
VSS[236]
E48
VSS[237]
E6
VSS[238]
E8
VSS[239]
F49
VSS[240]
F5
VSS[241]
G10
VSS[242]
G14
VSS[243]
G18
VSS[244]
G2
VSS[245]
G22
VSS[246]
G32
VSS[247]
G36
VSS[248]
G40
VSS[249]
G44
VSS[250]
G52
VSS[251]
AF39
VSS[252]
H16
VSS[253]
H20
VSS[254]
H30
VSS[255]
H34
VSS[256]
H38
VSS[257]
H42
VSS[258]
IB E XP EAK -M_ FCBGA 10 71
VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[326] VSS[327] VSS[328] VSS[329] VSS[330] VSS[331] VSS[332] VSS[333] VSS[334] VSS[335] VSS[336] VSS[337] VSS[338] VSS[339] VSS[340] VSS[341] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] VSS[353] VSS[354] VSS[355] VSS[356] VSS[366]
H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14
U 4 H
AB16
VSS[0]
AA19
VSS[1]
AA20
VSS[2]
AA22
VSS[3]
AM19
VSS[4]
AA24
VSS[5]
AA26
VSS[6]
AA28
VSS[7]
AA30
VSS[8]
AA31
VSS[9]
AA32
VSS[10]
AB11
VSS[11]
AB15
VSS[12]
AB23
VSS[13]
AB30
VSS[14]
AB31
VSS[15]
AB32
VSS[16]
AB39
VSS[17]
AB43
VSS[18]
AB47
VSS[19]
AB5
VSS[20]
AB8
VSS[21]
AC2
VSS[22]
AC52
VSS[23]
AD11
VSS[24]
AD12
VSS[25]
AD16
VSS[26]
AD23
VSS[27]
AD30
VSS[28]
AD31
VSS[29]
AD32
VSS[30]
AD34
VSS[31]
AU22
VSS[32]
AD42
VSS[33]
AD46
VSS[34]
AD49
VSS[35]
AD7
VSS[36]
AE2
VSS[37]
AE4
VSS[38]
AF12
VSS[39]
Y13
VSS[40]
AH49
VSS[41]
AU4
VSS[42]
AF35
VSS[43]
AP13
VSS[44]
AN34
VSS[45]
AF45
VSS[46]
AF46
VSS[47]
AF49
VSS[48]
AF5
VSS[49]
AF8
VSS[50]
AG2
VSS[51]
AG52
VSS[52]
AH11
VSS[53]
AH15
VSS[54]
AH16
VSS[55]
AH24
VSS[56]
AH32
VSS[57]
AV18
VSS[58]
AH43
VSS[59]
AH47
VSS[60]
AH7
VSS[61]
AJ19
VSS[62]
AJ2
VSS[63]
AJ20
VSS[64]
AJ22
VSS[65]
AJ23
VSS[66]
AJ26
VSS[67]
AJ28
VSS[68]
AJ32
VSS[69]
AJ34
VSS[70]
AT5
VSS[71]
AJ4
VSS[72]
AK12
VSS[73]
AM41
VSS[74]
AN19
VSS[75]
AK26
VSS[76]
AK22
VSS[77]
AK23
VSS[78]
AK28
VSS[79]
IB E XP EAK -M_ FCBGA 10 71
VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]
VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]
AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26 AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47
+3 VS
12
R3 02
10 0K_ 04 02 _5%
PC H _ NC T F615
+3 VS
R3 03
10 0K_ 04 02 _5%
PC H _ NC T F715
+3 VS
R3 04
10 0K_ 04 02 _5%
PC H _ NC T F1915
+3 VS
R3 05
10 0K_ 04 02 _5%
PC H _ NC T F2615
12
12
2
12
5
61
Q9 A 2N 7 002DWH _SOT3 63 -6
2
34
Q9 B 2N 7 002DWH _SOT3 63 -6
5
61
Q1 0A 2N 7 002DWH _SOT3 63 -6
34
Q1 0B 2N 7 002DWH _SOT3 63 -6
CR A CK_ B GA
CR A CK_ B GA
CR A CK_ B GA
CR A CK_ BG A 8, 35
BGA Ball Cracking Prevention and Detection
D D
Security Classification
Issued Date
1
2
MAY BE USED BY OR DIS CLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
4
Tit le
Size Do c u me nt N umb er R e v
Cu s t om
Da t e: She et o f
Compal Electronics, Inc.
IBEX-M(6/6)-GND
LA- 4901P
5
17 54T u esd ay , Dec ember 15, 2 00 9
1. 0
Loading...
+ 37 hidden pages
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use