COMPAL LA-4892P Schematics

A

1 1

B

C

D

E

Compal Confidential

Schematics Document

2 2

AUBURNDALE with Intel
IBEX PEAK-M core logic

Dior UMA

3 3

2009-05-16

REV:0.3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/10/31 2009/11/06

Compal Secret Data

Deciphered Date

Title

Size Doc umen t Nu mber R ev

Cu sto m

D

Dat e: Shee t o f

Compal Electronics, Inc.

Cover Sheet

LA -4 8 92 P

E

1 45Fri day, May 15, 2 009

0.3

A

Compal Confidential

File Name : Dior UMA

Fan Control

Page 4

1 1

2 2

Ex press Card 54

Sub-board

Page 29

10 /100/1000 LAN

Marvell

88 E 8059/ 8 8E807 2

RJ45 CONN

3 3

RTC CKT.

Page 28

Page 22

Page 24

LED

Page 28

LCD co nn

C R T

CRT to Docking

DP con n

DP to Do cking

WWAN Card

WLAN Card

Page 24

Page 21

Page 20

Page 28

Page 19

Page 28

Page 24

PCI-E BUS

1394/Card Reader

Sub-board

13 94 port

B

SD/MM C /
MS/ XD Slo t

C

Dior UMA

Mobile

CPU Dual Core

Socket-rPGA989

37.5mm *37.5mm

FD I DM I X4

Intel Ibex Peak M

10 7 1p ins

25mm*27mm

Page 1 3,14,1 5,16,17,18

Page 29

Br a id woo d

NA ND card

LP C BUS

Page 4 ,5,6,7,8

ONFI I nterface

Page 19

USB2.0

Azalia

SATA0

SATA1

Dual Channel

D

XDP Conn.

Page 4

DDR3-SO-DIMM X 2DD R 3 10 66/ 133 3MH z 1 .5V

BAN K 0, 1, 2, 3

USB x2(Docking)

USB x 2(Sub/B)

Page 9 ,10,11

Page 28

Page 26

FingerPrinter VFM451
US B x 1

Page 27

USB conn x 2(For I/O)
BT Conn USB x 1

USB x 1(Camara)

MD C V1.5

Audio CKT

Sub-board

SATA ODD Connector

Page 29

Page 21

Page 25

92HD75

Page 29

Page 19

2. 5" SATA HDD Connector

Page 19

E

Acc elerometer

LI S 302DLT R

Page 26

CK5 05

Clock Generator
xS L G8SP58 5

Page 12

daughter board

RJ 1 1

Page 25

TPA6047A

AMP & Audio Jack

Page. 28

(2) PS/2 Interfaces
(2) USB 2.channels
(2) SATA Channels
(2) Display Port Channels
(1) Serial Port
(1) Parallel Port

Docking CONN.

Page 29

(1 ) Line In

Power OK CKT.

Page 31

4 4

Po wer On/Off CKT.

Page 24

DC/DC Interface CKT.

Page 32

A

TPM1.2

SLB9635TT

Page 27 page 30

Touch Pad CONN.

TrackPoint CONN.

SP I ROM
4M B

B

SMSC KBC
1098

Page 29

Page 25

Page 27

Int.KBD

Page 25

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Super I/O
LPC47N217

C O M 1 L P T
( Docking ) ( Docking )

Page 28 Page 28

2008/10/31 2009/11/06

Page 31

Compal Secret Data

Deciphered Date

D

Title

Size Doc umen t Nu mber R ev

Cu sto m

Dat e: Shee t o f

(1 ) Line Out
(1) RJ45 (10/100/1000)
( 1) VGA
(1) 2 LAN indicator LED's
(1) Power Button
(1) I2C interface

Compal Electronics, Inc.

Block Diagram

LA -4 892 P

E

2 45Fri day, May 15, 2 009

0.3

A

Voltage Rails

power
plane

State

( O ME ANS ON X M EANS O FF )

+RTCVCC

+B

+3VL +0.75V

+5VALW

+3VALW

+1.5V

+5VS

+3VS

+1.5VS

+VCCP

+CPU_C ORE

+1.05 VS

+1.8VS

Symbol Note :

: means Digital Ground

: means Analog Ground

Install below 43 level BOM structure for ver. 0.2

S0

S1

S3

S5 S4/ AC

S5 S4/ Batte ry only

S5 S4/ AC & B attery
don't exist

1 1

O

O

O

O

O

O

O

O

O

O

O

X

O

O

O

O

X

O

X X

X

X X X

OO

OO

X

X

8072@ : Install for 8072 NIC controller

Install below 45 level BOM structure for ver. 0.2

45@ : means just put it in the BOM of 45 level.

Reserve below BOM structure for ver. 0.2

@ : means just reserve , no build

CONN@ : means ME part.

8059@ : Install for 8059 NIC controller

SMBUS Contro l Table

SOURCE

SMB_EC _CK1
SMB_EC _DA1

SMBCLK
SMBDATA

SML0CLK
SML0DA TA

SML1CLK
SML1DA TA

SMSC10 98

Calpel la

Calpel la

Calpel la

BATT

V

X
X
X

THERMAL

SODIMM CLK CH IP

XDP G-SENS OR

X

X X

V V

X

X

X X

MINI C ARD

X

V V V

X

X

X X

DOCK

X

V

X
X

SENSOR

NIC

X X

X
X
X

X

V

X

V

X
X

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/31 2009/11/06

A

Compal Secret Data

Deciphered Date

Title

Size Do cumen t Nu mber R ev

Cu sto m

Dat e: Shee t o f

Compal Electronics, Inc.

Notes List

LA -4 892 P

3 45Fri day, May 15, 2009

0.3

H_CPUR ST#

1 2

1.5K_0402_1%

09/01/22 HP

5

T1PAD

R14

1 2

0_0402_5%

R15

1 2

0_0402_5%

R19

1 2

0_0402_5%

1 2

R20

1 2

R21

0_0402_5%

R23

1 2

0_0402_5%

R25

1 2

0_0402_5%

R29

1 2

0_0402_5%

R30

1 2

R220_0402_1%

1 2

R920_0402_1%

1 2

R349.9_0402_1%

1 2

R549.9_0402_1%

1 2

TP_SKTOCC#

H_CAT ERR#

H_PE CI_ISO

H_PROCHO T#_D

H_THERMT RIP#_R

R18

0_0402_5%

H_PM_ SYNC_R

0_0402_5%

VCCPWR GOOD_1

VCCPWR GOOD_0

VDDPW RGOOD_R

H_PWR GD_XDP_RH_PWR GD_XDP

PLT_RST#_R

12

R32
750_0402_1%

COMP3

COMP2

COMP1

COMP0

H_CPUR ST#_R

JCPU 1B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_ 1

AN27

VCCPWRGOOD_ 0

AK13

SM_DRAMPWR OK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC,A UB_CFD_rP GA,R1P0

MISC THERMAL

PWR MANAGEMENT

Layo ut rule：10mil w idth tra ce
leng th < 0. 5", s pacing 2 0mil

D D

H_PE CI16

H_PROCHO T#42

H_THERMT RIP#16

H_PM_ SYNC15

H_C PUPWRGD

H_CPU PWRGD16

C C

PM_DRAM_PW RGD15

VTTPWRGOOD32

BUF_PLT_RST#16

4

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSC LK

DPLL_REF_SSC LK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PM_EXT_TS#[0]
PM_EXT_TS#[1]

DDR3

MISC

JTAG & BPM

BCLK

BCLK#

PRDY#

PREQ#

TRST#

TDI_M

TDO_M

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

3

PM_EXTTS#0

A16
B16

CLK_CPU_XD P

AR30

CLK_CPU_XD P#

AT30

E16
D16

A18
A17

F6

SM_RCOMP0

AL1

SM_RCOMP1

AM1

SM_RCOMP2

AN1

PM_EXTTS#0

AN15

PM_EXTTS#1

AP15

XDP_ PRDY#

AT28

XDP_PREQ#

AP27

XDP_TCK

AN28

TCK

XDP_TMS

AP28

TMS

XDP_TRST#

AT27

XDP_TDI

AT29

TDI

XDP_TDO

AR27

TDO

XDP_TDI_M

AR29

XDP_TDO_M

AP29

XDP_DBRESET#

AN25

XDP_BPM#0

AJ22

XDP_BPM#1

AK22

XDP_BPM#2

AK24

XDP_BPM#3

AJ24

XDP_BPM#4

AJ25

XDP_BPM#5

AH22

XDP_BPM#6

AK23

XDP_BPM#7

AH23

CLK_CPU _BCLK 16
CLK_CPU _BCLK# 16

CLK_EXP 14
CLK_EXP# 14

T91 P AD

1 2

R17 0_0402_5%

12/03 HP

0.1U_0402 _10V6K

11/10 HP

DRAMRST# 9,10

PM_EXTTS#1_R 9,10

XDP_BPM#0

CFG125

XDP_BPM#1

CFG135

XDP_BPM#2

CFG145

XDP_BPM#3

CFG155

11/14 HP

+VCCP

1

C1

2

@

PM_PWRBT N#_R15

PM_EXTTS#1

VDDPW RGOOD_R

09/04/07 Intel

from DDR

R870 0_0402_5%

1 2

R871 0_0402_5%@

1 2

R872 0_0402_5%

1 2

R873 0_0402_5%@

1 2

R874 0_0402_5%

1 2

R875 0_0402_5%@

1 2

R876 0_0402_5%

1 2

R877 0_0402_5%@

1 2

H_C PUPWRGD

H_PWR GD_XDP

R26 0_0402_5%

12/05 HP

R1 10K_0402_5%

R7 10K_0402_5%

R12 1.1K_0402_1%

R13 3K_0402_1%

XDP_PREQ#
XDP_ PRDY#

CFG175
CFG165

XDP_BPM#4
XDP_BPM#5

XDP_BPM#6
XDP_BPM#7

R24
1K_0402_5%

H_CP UPWRGD _R

1 2

PM_PWRBT N#_R

1 2

T127PAD
T128PAD

XDP_TCK

1 2

1 2

1 2

1 2

XDP_BPM#0_R
XDP_BPM#1_R

XDP_BPM#2_R
XDP_BPM#3_R

2

+VCCP

XDP_TDO

+1.5V

This s hall place near XDP

XDP Connector

JP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH- 030-01-L-D-A CONN @

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

1 2

R6 51_0402_5%

2

GND1

4

OBSFN_C0

6

OBSFN_C1

8

GND3

10
12
14

GND5

16
18
20

GND7

22

OBSFN_D0

24

OBSFN_D1

26

GND9

28
30
32

GND11

34
36
38

GND13

40
42
44
46
48
50

GND15

52

TD0

54

TRST#

56

TDI

58

TMS

60

GND17

+VCCP

2009/0 3/31 HP

CLK_CPU_XD P
CLK_CPU_XD P#

XDP_RST#_R
XDP_DBRESET#

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS

XDP_RST#_R

12/05 HP

CFG8 5
CFG9 5

CFG0 5
CFG1 5

CFG2 5
CFG3 5

CFG10 5
CFG11 5

CFG4 5
CFG5 5

CFG6 5
CFG7 5

+VCCP

1 2

R27 1K_0402_5%

PLT_RST#

@

1 2

R31 0_0402_5%

H_CPUR ST#

1

+3VS

R22
1K_0402_5%

1 2

PLT_RST# 13,16,22,24, 27,29

XDP_DBRESET# 13,15

09/05/14 HP

SCLK

SDATA

ALERT#

FAN_PW M30

8

7

6

5

B B

H_PROCHO T#

09/05/14 HP

A A

+3VS

THERMAL_D+

THERMAL_D-

+VCCP

B

2

E

3 1

Q98
MMBT3904W_SOT323-3

+3VS

2

C945

0.1U_0402 _10V6K

R917 2.2K_0402_5%

THERM_INT

12

1

+3VS

R965 10K_0402_5%

C

U48

1

VDD

2

D+

3

D-

THERM#4GND

ADM1032ARMZ R EEL_MSOP8

1 2

PWM Fan Control circuit

U47

1
2

74AHC1G00GW _SOT353-5

SMB_CLK_S3 9,10,12,1 4,26

SMB_DATA_S3 9,10,12,14, 26

THERM_SCI# 16

B
A
GND3Y

5

Vcc

R42 22_0402_5%

4

2200P_0402_50V7K

THERMAL_D+

C946

THERMAL_D-

12

2

1

+5VS+5VS

1

C2

0.1U_0402 _10V6K

@

2

C

Q86

2

B

MMBT3904W_SOT323-3

E

3 1

Layo ut No te:

Plac e n ear t he hotte st
spot area

conn@

JP2

1

1

2

2

3

3

ACES_85204- 03001

G1
G2

Put the sensor colse to CPU

5

4

11/12

09/02/05 HP

4
5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/10/31 2009/11/06

Proces sor Pullups JTAG MAPPING

H_CAT ERR#

H_PROCHO T#_D

H_CPUR ST#_R

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

1 2

R34 49.9_0402_1%

1 2

R36 68_0402_5%

1 2

R37 68_0402_5%@

DDR3 C ompen sation Signals

1 2

R44 100_0402_1%

1 2

R45 24.9_0402_1%

1 2

R46 130_0402_1%

Layout Note :Please these
resist ors n ear Processor

Compal Secret Data

Deciphered Date

2

+VCCP

Close to XDP

XDP_TRST#

1 2

R47 51_0402_5%

Title

Auburndale(1/5)-Thermal/XDP

Size Document Num ber R ev

Cust om

LA -4 892 P

Date: Sheet

11/12 remov e the maping option

Compal Electronics, Inc.

1

4 45Satu rday, May 16, 2009

0.3

of

5

JCPU 1A

DMI_CRX_PTX_N015
DMI_CRX_PTX_N115
DMI_CRX_PTX_N215
DMI_CRX_PTX_N315

DMI_CRX_PTX_P015
DMI_CRX_PTX_P115

D D

DMI_CRX_PTX_P215
DMI_CRX_PTX_P315

DMI_CTX_PRX_N015
DMI_CTX_PRX_N115
DMI_CTX_PRX_N215
DMI_CTX_PRX_N315

DMI_CTX_PRX_P015
DMI_CTX_PRX_P115
DMI_CTX_PRX_P215
DMI_CTX_PRX_P315

FDI_CTX_ PRX_N015
FDI_CTX_ PRX_N115
FDI_CTX_ PRX_N215
FDI_CTX_ PRX_N315
FDI_CTX_ PRX_N415
FDI_CTX_ PRX_N515
FDI_CTX_ PRX_N615
FDI_CTX_ PRX_N715

FDI_CTX_PRX_P015
FDI_CTX_PRX_P115
FDI_CTX_PRX_P215
FDI_CTX_PRX_P315
FDI_CTX_PRX_P415
FDI_CTX_PRX_P515

C C

FDI_CTX_PRX_P615
FDI_CTX_PRX_P715

FDI_ FSYNC 015
FDI_ FSYNC 115

FDI_IN T15

FDI_ LSYNC015
FDI_ LSYNC115

FDI_CTX_ PRX_N0
FDI_CTX_ PRX_N1
FDI_CTX_ PRX_N2
FDI_CTX_ PRX_N3
FDI_CTX_ PRX_N4
FDI_CTX_ PRX_N5
FDI_CTX_ PRX_N6
FDI_CTX_ PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FD I_FSY NC0
FD I_FSY NC1

FDI_ INT

FDI_ LSYNC 0
FDI_ LSYNC 1

A24
C23
B22
A21

B24
D23
B23
A22

D24
G24
F23
H23

D25
F24
E23
G23

E22
D21
D19
D18
G21
E19
F21
G18

D22
C21
D20
C18
G22
E20
F20
G19

F17
E17

C17

F18
D17

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]

FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]

FDI_FSYNC[0]
FDI_FSYNC[1]

FDI_INT

FDI_LSYNC[0]
FDI_LSYNC[1]

PEG_RCOMPO

DMI Intel(R) FDI

PCI EXPRESS -- GRAPHICS

B B

IC,A UB_CFD_rP GA,R1P0

PEG_ICOMPI

PEG_ICOMPO

PEG_RBIAS

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

B26
A26
B27
A25

K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

EXP_ICOMPI

EXP_RBIAS

4

R49 49.9_0402_1%

1 2

R50 750_0402_1%

1 2

Layo ut rule tra ce
leng th < 0.5"

11/06 HP

3

2

1

：

CFG04
CFG14
CFG24
CFG34
CFG44
CFG54
CFG64
CFG74
CFG84
CFG94
CFG104
CFG114
CFG124
CFG134
CFG144
CFG154
CFG164
CFG174

T20 P AD

R58

0_0402_5%@

1 2
1 2

0_0402_5%@

R59

CFG 0
CFG 1
CFG 2
CFG 3
CFG 4
CFG 5
CFG 6
CFG 7
CFG 8
CFG 9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18

AP25

AL25
AL24
AL22
AJ33

AM30
AM28
AP31

AL32

AL30
AM31
AN29
AM32
AK32
AK31
AK28

AJ28
AN30
AN32

AJ32

AJ29

AJ30
AK30

AG9
M27
L28

J17
H17
G25
G17
E31
E30

H16

B19
A19

A20
B20

U9
T9

AC9
AB9

C1
A3

J29

J28

A34
A33

C35
B35

JCPU 1E

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
SA_DIMM_VREF
SB_DIMM_VREF
RSVD11
RSVD12
RSVD13
RSVD14

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86

RSVD15
RSVD16

RSVD17
RSVD18

RSVD19
RSVD20

RSVD21
RSVD22

RSVD_NCTF_2 3
RSVD_NCTF_2 4

RSVD26
RSVD27

RSVD_NCTF_2 8
RSVD_NCTF_2 9

RSVD_NCTF_3 0
RSVD_NCTF_3 1

RSVD_NCTF_3 7

RSVD_NCTF_4 0
RSVD_NCTF_4 1

RSVD_NCTF_4 2
RSVD_NCTF_4 3

RSVD_NCTF_5 4
RSVD_NCTF_5 5
RSVD_NCTF_5 6
RSVD_NCTF_5 7

RESERVED

RSVD32
RSVD33

RSVD34
RSVD35

RSVD36

RSVD38
RSVD39

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53

RSVD58

RSVD_TP_59
RSVD_TP_60

RSVD62
RSVD63
RSVD64
RSVD65

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

AJ13
AJ12

AH25
AK26

AL26
AR2

AJ26
AJ27

AP1
AT2

AT3
AR1

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32

E15
F15
A2

KEY

D15
C15

R53 0_0402_5%@

AJ15

R54 0_0402_5%@

AH15

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

AP34

VSS

1 2
1 2

09/02/13 HP

Deciphered Date

2

IC,A UB_CFD_rP GA,R1P0

Compal Electronics, Inc.

Title

Auburndale(2/5)-DMI/PEG/FDI

Size Document Num ber R ev

Cust om

LA -4 892 P

Date: Sheet of

1

5 45Satu rday, May 16, 2009

0.3

CFG Straps for PROCESSOR

CFG 0

1 2

R60 3.01K_0402_1%@

PCI-Ex press Configuration Select

1: Sin gle PEG
0: Bif urcat ion enabled

CFG0

Not ap plica ble fo r Clarksfield Processor

CFG 3

1 2

R62 3.01K_0402_1%@

CFG3-P CI Ex press Static Lane Reversal

1: Nor mal Operation
0: Lan e Num bers Reversed

CFG3

15 -> 0, 14 ->1, .....

A A

CFG 4

5

R63

1 2

3.01K_0402_1%@

CFG4-D ispla y Port Presence

1: Dis abled ; No P hysical Display Port
attach ed to Embedded Display Port

CFG4

0: Ena bled; An ex ternal Display Port
device is c onnect ed to the Embedded
Displa y Port

4

CFG 7

1 2

R61 3.01K_0402_1%@

Only t empor ary fo r earl y CFD samples (rPGA/BGA)
No nee ded by MoW41.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/10/31 2009/11/06

Compal Secret Data

5

4

3

2

1

AR10
AT10

JCPU 1D

W8

SB_CK[0]

W9

SB_CK#[0]

B5

SB_DQ[0]

A5

SB_DQ[1]

C3

SB_DQ[2]

B3

SB_DQ[3]

E4

SB_DQ[4]

A6

SB_DQ[5]

A4

SB_DQ[6]

C4

SB_DQ[7]

D1

SB_DQ[8]

D2

SB_DQ[9]

F2

SB_DQ[10]

F1

SB_DQ[11]

C2

SB_DQ[12]

F5

SB_DQ[13]

F3

SB_DQ[14]

G4

SB_DQ[15]

H6

SB_DQ[16]

G2

SB_DQ[17]

J6

SB_DQ[18]

J3

SB_DQ[19]

G1

SB_DQ[20]

G5

SB_DQ[21]

J2

SB_DQ[22]

J1

SB_DQ[23]

J5

SB_DQ[24]

K2

SB_DQ[25]

L3

SB_DQ[26]

M1

SB_DQ[27]

K5

SB_DQ[28]

K4

SB_DQ[29]

M4

SB_DQ[30]

N5

SB_DQ[31]

AF3

SB_DQ[32]

AG1

SB_DQ[33]

AJ3

SB_DQ[34]

AK1

SB_DQ[35]

AG4

SB_DQ[36]

AG3

SB_DQ[37]

AJ4

SB_DQ[38]

AH4

SB_DQ[39]

AK3

SB_DQ[40]

AK4

SB_DQ[41]

AM6

SB_DQ[42]

AN2

SB_DQ[43]

AK5

SB_DQ[44]

AK2

SB_DQ[45]

AM4

SB_DQ[46]

AM3

SB_DQ[47]

AP3

SB_DQ[48]

AN5

SB_DQ[49]

AT4

SB_DQ[50]

AN6

SB_DQ[51]

AN4

SB_DQ[52]

AN3

SB_DQ[53]

AT5

SB_DQ[54]

AT6

SB_DQ[55]

AN7

SB_DQ[56]

AP6

SB_DQ[57]

AP8

SB_DQ[58]

AT9

SB_DQ[59]

AT7

SB_DQ[60]

AP9

SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

AB1

SB_BS[0]

W5

SB_BS[1]

R7

SB_BS[2]

AC5

SB_CAS#

Y7

SB_RAS#

AC6

SB_WE#

DDR SYSTEM MEMORY - B

SB_CKE[0]

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

M3

V7
V6
M2

AB8
AD6

AC7
AD1

D4
E1
H3
K1
AH1
AL2
AR4
AT8

D5
F4
J4
L4
AH2
AL4
AR5
AR8

C5
E3
H4
M5
AG2
AL5
AP5
AR7

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

DDR _B_DM0
DDR _B_DM1
DDR _B_DM2
DDR _B_DM3
DDR _B_DM4
DDR _B_DM5
DDR _B_DM6
DDR _B_DM7

DDR_ B_DQS#0
DDR_ B_DQS#1
DDR_ B_DQS#2
DDR_ B_DQS#3
DDR_ B_DQS#4
DDR_ B_DQS#5
DDR_ B_DQS#6
DDR_ B_DQS#7

DDR _B_DQS0
DDR _B_DQS1
DDR _B_DQS2
DDR _B_DQS3
DDR _B_DQS4
DDR _B_DQS5
DDR _B_DQS6
DDR _B_DQS7

DDR_ B_MA0
DDR_ B_MA1
DDR_ B_MA2
DDR_ B_MA3
DDR_ B_MA4
DDR_ B_MA5
DDR_ B_MA6
DDR_ B_MA7
DDR_ B_MA8
DDR_ B_MA9
DDR_B_ MA10
DDR_B_ MA11
DDR_B_ MA12
DDR_B_ MA13
DDR_B_ MA14
DDR_B_ MA15

M_CLK_DD R2 10
M_CLK_DDR# 2 10
DDR_ CKE2_DIMMB 10

M_CLK_DD R3 10
M_CLK_DDR# 3 10
DDR_ CKE3_DIMMB 10

DDR_ CS2_DIMMB# 10
DDR_ CS3_DIMMB# 10

M_ODT2 10
M_ODT3 10

DDR_ B_DM[0..7] 10

DDR_ B_DQS#[0. .7] 10

DDR_ B_DQS[0.. 7] 10

DDR_ B_MA[0..15] 10

JCPU 1C

D D

DDR_ A_D[0..6 3]9

C C

B B

DDR_A_ BS09
DDR_A_ BS19
DDR_A_ BS29

DDR_ A_CAS#9
DDR_ A_RAS#9
DDR_A_W E#9

DDR_ A_D0
DDR_ A_D1
DDR_ A_D2
DDR_ A_D3
DDR_ A_D4
DDR_ A_D5
DDR_ A_D6
DDR_ A_D7
DDR_ A_D8
DDR_ A_D9
DDR _A_D10
DDR _A_D11
DDR _A_D12
DDR _A_D13
DDR _A_D14
DDR _A_D15
DDR _A_D16
DDR _A_D17
DDR _A_D18
DDR _A_D19
DDR _A_D20
DDR _A_D21
DDR _A_D22
DDR _A_D23
DDR _A_D24
DDR _A_D25
DDR _A_D26
DDR _A_D27
DDR _A_D28
DDR _A_D29
DDR _A_D30
DDR _A_D31
DDR _A_D32
DDR _A_D33
DDR _A_D34
DDR _A_D35
DDR _A_D36
DDR _A_D37
DDR _A_D38
DDR _A_D39
DDR _A_D40
DDR _A_D41
DDR _A_D42
DDR _A_D43
DDR _A_D44
DDR _A_D45
DDR _A_D46
DDR _A_D47
DDR _A_D48
DDR _A_D49
DDR _A_D50
DDR _A_D51
DDR _A_D52
DDR _A_D53
DDR _A_D54
DDR _A_D55
DDR _A_D56
DDR _A_D57
DDR _A_D58
DDR _A_D59
DDR _A_D60
DDR _A_D61
DDR _A_D62
DDR _A_D63

AJ10

AL10
AK12

AK11

AM10
AR11

AL11

AT11
AP12
AM12
AN12
AM13

AT14

AT12

AL13
AR14
AP14

A10

SA_DQ[0]

C10

SA_DQ[1]

C7

SA_DQ[2]

A7

SA_DQ[3]

B10

SA_DQ[4]

D10

SA_DQ[5]

E10

SA_DQ[6]

A8

SA_DQ[7]

D8

SA_DQ[8]

F10

SA_DQ[9]

E6

SA_DQ[10]

F7

SA_DQ[11]

E9

SA_DQ[12]

B7

SA_DQ[13]

E7

SA_DQ[14]

C6

SA_DQ[15]

H10

SA_DQ[16]

G8

SA_DQ[17]

K7

SA_DQ[18]

J8

SA_DQ[19]

G7

SA_DQ[20]

G10

SA_DQ[21]

J7

SA_DQ[22]

J10

SA_DQ[23]

L7

SA_DQ[24]

M6

SA_DQ[25]

M8

SA_DQ[26]

L9

SA_DQ[27]

L6

SA_DQ[28]

K8

SA_DQ[29]

N8

SA_DQ[30]

P9

SA_DQ[31]

AH5

SA_DQ[32]

AF5

SA_DQ[33]

AK6

SA_DQ[34]

AK7

SA_DQ[35]

AF6

SA_DQ[36]

AG5

SA_DQ[37]

AJ7

SA_DQ[38]

AJ6

SA_DQ[39]
SA_DQ[40]

AJ9

SA_DQ[41]
SA_DQ[42]
SA_DQ[43]

AK8

SA_DQ[44]

AL7

SA_DQ[45]
SA_DQ[46]

AL8

SA_DQ[47]

AN8

SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]

AM9

SA_DQ[52]

AN9

SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

AC3

SA_BS[0]

AB2

SA_BS[1]

U7

SA_BS[2]

AE1

SA_CAS#

AB3

SA_RAS#

AE9

SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DM[0]

SA_DM[1]

SA_DM[2]

SA_DM[3]

SA_DM[4]

SA_DM[5]

SA_DM[6]

SA_DM[7]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]

SA_MA[1]

SA_MA[2]

SA_MA[3]

SA_MA[4]

SA_MA[5]

SA_MA[6]

SA_MA[7]

SA_MA[8]

SA_MA[9]

SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AA6
AA7
P7

Y6
Y5
P6

AE2
AE8

AD8
AF9

B9
D7
H7
M7
AG6
AM7
AN10
AN13

C9
F8
J9
N9
AH7
AK9
AP11
AT13

C8
F9
H9
M9
AH8
AK10
AN11
AR13

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

DDR _A_DM0
DDR _A_DM1
DDR _A_DM2
DDR _A_DM3
DDR _A_DM4
DDR _A_DM5
DDR _A_DM6
DDR _A_DM7

DDR_ A_DQS#0
DDR_ A_DQS#1
DDR_ A_DQS#2
DDR_ A_DQS#3
DDR_ A_DQS#4
DDR_ A_DQS#5
DDR_ A_DQS#6
DDR_ A_DQS#7

DDR _A_DQS0
DDR _A_DQS1
DDR _A_DQS2
DDR _A_DQS3
DDR _A_DQS4
DDR _A_DQS5
DDR _A_DQS6
DDR _A_DQS7

DDR_ A_MA0
DDR_ A_MA1
DDR_ A_MA2
DDR_ A_MA3
DDR_ A_MA4
DDR_ A_MA5
DDR_ A_MA6
DDR_ A_MA7
DDR_ A_MA8
DDR_ A_MA9
DDR_A_ MA10
DDR_A_ MA11
DDR_A_ MA12
DDR_A_ MA13
DDR_A_ MA14
DDR_A_ MA15

M_CLK_DD R0 9
M_CLK_DDR# 0 9
DDR_ CKE0_DIMMA 9

M_CLK_DD R1 9
M_CLK_DDR# 1 9
DDR_ CKE1_DIMMA 9

DDR_ CS0_DIMMA# 9
DDR_ CS1_DIMMA# 9

M_ODT0 9
M_ODT1 9

DDR_ A_DM[0..7] 9

DDR_ A_DQS#[0. .7] 9

DDR_ A_DQS[0.. 7] 9

DDR_ A_MA[0..15] 9

DDR_ B_D[0..6 3]10

DDR_B_ BS010
DDR_B_ BS110
DDR_B_ BS210

DDR_ B_CAS#10
DDR_ B_RAS#10
DDR_B_W E#10

DDR_ B_D0
DDR_ B_D1
DDR_ B_D2
DDR_ B_D3
DDR_ B_D4
DDR_ B_D5
DDR_ B_D6
DDR_ B_D7
DDR_ B_D8
DDR_ B_D9
DDR _B_D10
DDR _B_D11
DDR _B_D12
DDR _B_D13
DDR _B_D14
DDR _B_D15
DDR _B_D16
DDR _B_D17
DDR _B_D18
DDR _B_D19
DDR _B_D20
DDR _B_D21
DDR _B_D22
DDR _B_D23
DDR _B_D24
DDR _B_D25
DDR _B_D26
DDR _B_D27
DDR _B_D28
DDR _B_D29
DDR _B_D30
DDR _B_D31
DDR _B_D32
DDR _B_D33
DDR _B_D34
DDR _B_D35
DDR _B_D36
DDR _B_D37
DDR _B_D38
DDR _B_D39
DDR _B_D40
DDR _B_D41
DDR _B_D42
DDR _B_D43
DDR _B_D44
DDR _B_D45
DDR _B_D46
DDR _B_D47
DDR _B_D48
DDR _B_D49
DDR _B_D50
DDR _B_D51
DDR _B_D52
DDR _B_D53
DDR _B_D54
DDR _B_D55
DDR _B_D56
DDR _B_D57
DDR _B_D58
DDR _B_D59
DDR _B_D60
DDR _B_D61
DDR _B_D62
DDR _B_D63

IC,A UB_CFD_rP GA,R1P0

IC,A UB_CFD_rP GA,R1P0

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/10/31 2009/11/06

Compal Secret Data

Deciphered Date

2

Title

Size Document Num ber R ev

Cust om

Date: Sheet o f

Compal Electronics, Inc.

Auburndale(3/5)-DDR3

LA -4 892 P

1

6 45Satu rday, May 16, 2009

0.3

5

+CPU_C ORE

JCPU 1F

D D

C C

B B

A A

48A 1

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

IC,A UB_CFD_rP GA,R1P0

CPU CO RE SUPPLY

POWER

CPU VIDS

SENSE LINES

5

1.1V R AIL POWER

PROC_DPRSLP VR

VTT_SELECT

VCC_SENSE
VSS_SENSE

VTT_SENSE

VSS_SENSE_VTT

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8

VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32

VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

ISENSE

+VCCP

AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

+VCCP

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

AN33

PSI#

H_VI D0

AK35

H_VI D1

AK33

H_VI D2

AK34

H_VI D3

AL35

H_VI D4

AL33

H_VI D5

AM33

H_VI D6

AM35

PM_DPRSL PVR_R

AM34

G15

AN35

VCC _SENSE

AJ34

VSS_SENSE

AJ35

B15
A15

VCC SENSE

VSSSENSE

PSI# 42

H_VID [0..6] 42

1 2

R67 0_0402_5%

H_VTTVID1 38

H_VTTVID1 = Low, 1.1V

H_VTTVID1 = High, 1.05V

IMVP_IMON 42

0_0402_5%

R68

1 2
1 2

R69 0_0402_5%

VTT_SENSE 38
VSS_SENSE_VTT 38

Clo se to CPU

1 2

R70 100_0402_1%

1 2

R71 100_0402_1%

+VCCP

+VCCP

22U_0805_6.3V6M

C958

1

2

10U_0805_10V4K

C65

1

2

VCC SENSE
VSSSENSE

4

+VCCP

09/05/11 HP

22U_0805_6.3V6M

C957

1

1

2

2

10U_0805_10V4K

C66

1

1

2

2

PROC _DPRSLPVR 42

+CPU_C ORE

4

22U_0805_6.3V6M

22U_0805_6.3V6M

C42

1

2

10U_0805_10V4K

10U_0805_10V4K

C45

1

2

VCCSEN SE 42
VSSSENSE 42

3

330U 2V M X LESR6M SX H1.9

330U 2V M X LESR6M SX H1.9

1

C968

+

2

09/04/16 Compal

22U_0805_6.3V6M

22U_0805_6.3V6M

C40

1

2

10U_0805_10V4K

C46

1

2

22U_0805_6.3V6M

C39

C68

C959

1

1

10U_0805_10V4K

C38

2

10U_0805_10V4K

C67

1

1

2

2

Inside cavity

10U_0805_10V4K

C60

Under cavity

2

C41

1

2

CPU

47P_0402_50V8J@

+GFX_CORE

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C969

1

+

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

C925

C924

C880

1

1

1

2

2

2

09/03/31 HP

47P_0402_50V8J@

12

C935

47P_0402_50V8J@

C936

12

12

C938

C937

12

47P_0402_50V8J@

C881

JCPU1 G

AT21

VAXG1

AT19

VAXG2

AT18

VAXG3

+VCCP

+VCCP

AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16

AL21
AL19
AL18

AL16
AK21
AK19
AK18
AK16

AJ21

AJ19

AJ18

AJ16
AH21
AH19
AH18
AH16

47P_0402_50V8J@

J24
J23

H25

K26

J27
J26

J25
H27
G28
G27
G26
F26
E26
E25

IC,A UB_CFD_rP GA,R1P0

5A18A

VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36

VTT1_45
VTT1_46
VTT1_47

VTT1_48
VTT1_49
VTT1_50
VTT1_51
VTT1_52
VTT1_53
VTT1_54
VTT1_55
VTT1_56
VTT1_57
VTT1_58

+VCCP +CPU_C ORE+GFX_CORE +1.5V

FDI PEG & DMI

47P_0402_50V8J@

12

12

C743

C744

47P_0402_50V8J@

2

AR22

VAXG_SENSE

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

GFX_VR_EN

GFX_IMON

AT22

AM22
AP22
AN22
AP23
AM23
AP24
AN24

AR25
AT25
AM24

VSSAXG_SENSE

SENSE

LINES

GRAPH ICS

GFX_DPRSLPVR

GR APH ICS VID s

AJ1

VDDQ1

AF1

VDDQ2

AE7

VDDQ3

AE4

VDDQ4

AC1

VDDQ5

AB7

VDDQ6

AB4

VDDQ7

Y1

VDDQ8

W7

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

VTT0_59
VTT0_60
VTT0_61
VTT0_62

VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68

VCCPLL1
VCCPLL2
VCCPLL3

47P_0402_50V8J@

W4
U1
T7
T4
P1
N7
N4
L1
H1

P10
N10
L10
K10

J22
J20
J18
H21
H20
H19

L26
L27
M26

3A

POWER

DDR3 - 1.5V RAILS

1.1V1.8V

0.6A

47P_0402_50V8J@

12

12

C742

C741

+VCCP

+VCCP

12

47P_0402_50V8J@

C745

1

2

VCC_AXG_SENSE 44
VSS_AXG_SENSE 44

GFXVR_VID_0 44
GFXVR_VID_1 44
GFXVR_VID_2 44
GFXVR_VID_3 44
GFXVR_VID_4 44
GFXVR_VID_5 44
GFXVR_VID_6 44

GFXVR_EN 44
GFXVR_DPR SLPVR 44
GFXVR_IMON 44

1U_0603_1 0V4Z

C47

1

2

1U_0603_1 0V4Z

1U_0603_1 0V4Z

C71

1

2

12

C746

47P_0402_50V8J@

1U_0603_1 0V4Z

C48

1

2

C72

1

2

47P_0402_50V8J@

12

C747

C50

C49

1

1

2

2

+1.8VS

22U_0805_6.3V6M

2.2U_0603 _6.3V4Z

4.7U_0603 _6.3V6K

C74

C73

1

1

2

2

12

C748

+1.5V

1U_0603_1 0V4Z

1U_0603_1 0V4Z

GFXVR_EN

1U_0603_1 0V4Z

1

2

C75

47P_0402_50V8J@

C51

1

1 2

R844 4.7K_0402_5%

09/04/13 Intel

22U_0805_6.3V6M

22U_0805_6.3V6M

C955

C956

1

1

2

2

09/03/31 HP

47P_0402_50V8J@

12

12

C931

47P_0402_50V8J@

C932

47P_0402_50V8J@

12

12

C933

C934

11/25 HP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/10/31 2009/11/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Num ber R ev

Cust om

Date: Sheet of

Auburndale(4/5)-PWR

LA -4 892 P

1

7 45Satu rday, May 16, 2009

0.3

5

JCPU 1H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

D D

C C

B B

AR17
AR15
AR12

AP20
AP17
AP13
AP10

AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11

AL34
AL31
AL23
AL20
AL17
AL12

AK29
AK27
AK25
AK20
AK17

AJ31
AJ23
AJ20
AJ17
AJ14
AJ11

AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13

AG10

AE35

VSS8
VSS9
VSS10
VSS11

AR9

VSS12

AR6

VSS13

AR3

VSS14
VSS15
VSS16
VSS17
VSS18

AP7

VSS19

AP4

VSS20

AP2

VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33

AM8

VSS34

AM5

VSS35

AM2

VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42

AL9

VSS43

AL6

VSS44

AL3

VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56

AJ8

VSS57

AJ5

VSS58

AJ2

VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72

AH9

VSS73

AH6

VSS74

AH3

VSS75
VSS76

AF8

VSS77

AF4

VSS78

AF2

VSS79
VSS80

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

4

JCPU 1I

K27

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

VSS

NCTF

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

AT35
AT1
AR34
B34
B2
B1
A35

VSS_NCTF 1_R
VSS_NCTF 2_R
VSS_NCTF 3_R
VSS_NCTF 4_R
VSS_NCTF 5_R
VSS_NCTF 6_R
VSS_NCTF 7_R

3

+CPU_C ORE

1

2

1

2

1

2

1

2

T54
T55
T78
T79
T80
T56
T57

09/01/15 HP

2

CPU CORE

22U_0805_6.3V6M

22U_0805_6.3V6M

C76

22U_0805_6.3V6M

C90

22U_0805_6.3V6M

C98

22U_0805_6.3V6M

C975

22U_0805_6.3V6M

C77

C78

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C92

C91

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C99

C100

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C976

C977

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C80

C79

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C93

C94

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C983

C101

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C978

C979

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C81

1

2

22U_0805_6.3V6M

C95

1

2

22U_0805_6.3V6M

C103

1

2

22U_0805_6.3V6M

C980

1

2

C82

1

2

22U_0805_6.3V6M

C96

1

2

22U_0805_6.3V6M

C110

1

2

22U_0805_6.3V6M

C981

1

2

22U_0805_6.3V6M

C83

1

2

Under cavity

22U_0805_6.3V6M

C111

1

2

22U_0805_6.3V6M

C982

1

2

09/05/14 HP

22U_0805_6.3V6M

C84

1

between Inductor and socket

2

22U_0805_6.3V6M

C112

1

2

22U_0805_6.3V6M

C88

1

2

+CPU_C ORE

330U 2V M X LESR6M SX H1.9

C108

1

+

@

2

22U_0805_6.3V6M

C984

1

2

22U_0805_6.3V6M

C102

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C89

C985

1

1

2

2

10U_0805_10V4K

22U_0805_6.3V6M

C988

C113

1

1

2

2

330U 2V M X LESR6M SX H1.9

330U 2V M X LESR6M SX H1.9

C109

C107

1

1

+

+

@

2

2

Inside cavity

1

330U 2V M X LESR6M SX H1.9

C105

1

+

2

330U 2V M X LESR6M SX H1.9

330U 2V M X LESR6M SX H1.9

C106

C104

1

1

+

+

2

2

Bulk caps

09/01/15 HP

IC,A UB_CFD_rP GA,R1P0

A A

5

IC,A UB_CFD_rP GA,R1P0

4

BGA Ball Cracking Prevention and Detection

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/10/31 2009/11/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Auburndale(5/5)-GND/Bypass

Size Document Num ber R ev

Cust om

LA -4 892 P

Date: Sheet of

1

8 45Fri day, M ay 15, 2009

0.3

5

09/04/23 HP

+V_D DR_REF_DIMMA_DQ

2.2U_0603 _6.3V4Z

0.1U_0402 _10V6K
C115

C114

1

1

2

D D

C C

B B

A A

2

DDR_ CKE0_DIMMA6

DDR_A_ BS26

M_CLK_DD R06
M_CLK_DDR# 06

DDR_A_ BS06

DDR_A_W E#6
DDR_ A_CAS#6

DDR_ CS1_DIMMA#6

1 2

10K_0402_5%

0.1U_0402 _10V6K

+3VS

2.2U_0603 _6.3V4Z
C136

C135

1

1

2

2

+1.5V +1.5V

3 A

3 A @1 . 5 V

@ 1. 5V

3 A3 A

@ 1. 5V@ 1. 5V

DDR3 SO-DIMM A

JDIMA1 CONN @

VREF_DQ1VSS1

3

R80

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9
VSS925VSS10
DQS#127DM1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16
DQS#245DM2
DQS247VSS17
VSS1849DQ22

51

DQ18
DQ1953VSS19
VSS2055DQ28

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3
A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

DDR_ A_D0
DDR_ A_D1

DDR _A_DM0

DDR_ A_D2
DDR_ A_D3

DDR_ A_D8
DDR_ A_D9

DDR_ A_DQS#1
DDR _A_DQS1

DDR _A_D10
DDR _A_D11

DDR _A_D16
DDR _A_D17

DDR_ A_DQS#2
DDR _A_DQS2

DDR _A_D18
DDR _A_D19

DDR _A_D24
DDR _A_D25

DDR _A_DM3

DDR _A_D26
DDR _A_D27

DDR_ CKE0_DIMMA

DDR_ A_BS2

DDR_A_ MA12
DDR_ A_MA9

DDR _A_MA8
DDR_ A_MA5

DDR_ A_MA3
DDR_ A_MA1

M_CLK_D DR0
M_CLK_D DR#0

DDR_A_ MA10
DDR_ A_BS0

DDR_A_ WE#
DDR _A_CAS# M_ODT0

DDR_A_ MA13
DDR_ CS1_DIMMA#

DDR _A_D32
DDR _A_D33

DDR_ A_DQS#4
DDR _A_DQS4

DDR _A_D34
DDR _A_D35

DDR _A_D40
DDR _A_D41

DDR _A_DM5

DDR _A_D42
DDR _A_D43

DDR _A_D48
DDR _A_D49

DDR_ A_DQS#6
DDR _A_DQS6

DDR _A_D50
DDR _A_D51

DDR _A_D56
DDR _A_D57

DDR _A_DM7

DDR _A_D58
DDR _A_D59

R79

10K_0402_5%

12

VSS3

DQS0

VSS6

VSS8
DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ23

DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44

DQ45
VSS35
DQS#5

DQS5

VSS38

DQ46

DQ47
VSS40

DQ52

DQ53
VSS42

VSS43

DQ54

DQ55
VSS45

DQ60

DQ61
VSS47
DQS#7

DQS7

VSS50

DQ62

DQ63
VSS52

EVENT#

VTT2

DQ4
DQ5

DQ6
DQ7

A15
A14

A7

A6
A4

A2
A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA

SCL

G2

TOP SLOT

5

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

4

DDR_ A_D4
DDR_ A_D5

DDR_ A_DQS#0
DDR _A_DQS0

DDR_ A_D6
DDR_ A_D7

DDR _A_D12
DDR _A_D13

DDR _A_DM1
DRAMRST#

DDR _A_D14
DDR _A_D15

DDR _A_D20
DDR _A_D21

DDR _A_DM2

DDR _A_D22
DDR _A_D23

DDR _A_D28
DDR _A_D29

DDR_ A_DQS#3
DDR _A_DQS3

DDR _A_D30
DDR _A_D31

DDR_ CKE1_DIMMA

DDR_A_ MA15
DDR_A_ MA14

DDR_ A_MA11
DDR_ A_MA7

DDR _A_MA6
DDR_ A_MA4

DDR_ A_MA2
DDR_ A_MA0

M_CLK_D DR1
M_CLK_D DR#1

DDR_ A_BS1
DDR _A_RAS#

DDR_ CS0_DIMMA#

M_ODT1

DDR _A_D36
DDR _A_D37

DDR _A_DM4

DDR _A_D38
DDR _A_D39

DDR _A_D44
DDR _A_D45

DDR_ A_DQS#5
DDR _A_DQS5

DDR _A_D46
DDR _A_D47

DDR _A_D52
DDR _A_D53

DDR _A_DM6

DDR _A_D54
DDR _A_D55

DDR _A_D60
DDR _A_D61

DDR_ A_DQS#7
DDR _A_DQS7

DDR _A_D62
DDR _A_D63

PM_EXTTS#1_R
SMB_DATA_S3
SMB_CLK_S3

+0.75VS

0000 .6 5 A @ 0. 75 V

. 65 A@ 0 . 7 5V

. 65 A@ 0 . 7 5V. 65 A@ 0 . 7 5V

4

DRAMRST# 4,10

DDR_ CKE1_DIMMA 6

M_CLK_DD R1 6
M_CLK_DDR# 1 6

DDR_A_ BS1 6
DDR_ A_RAS# 6

DDR_ CS0_DIMMA# 6
M_ODT0 6

M_ODT1 6

0.1U_0402 _10V6K
C129

1

2

PM_EXTTS#1_R 4,10

SMB_DATA_S3 4,10,12,14, 26
SMB_CLK_S3 4,10,12,1 4,26

DDR_ A_D[0..6 3]6

DDR_ A_DM[0..7]6

DDR_ A_DQS[0.. 7]6

DDR_ A_DQS#[0. .7]6

DDR_ A_MA[0..15]6

09/04/23 HP

+V_D DR_REF_DIMMA_CA

2.2U_0603 _6.3V4Z
C130

1

2

3

La yout Note :
Pl ac e n ear D IM M

+1.5V

10U_0603_6.3V6M

C118

C119

1

1

2

2

La yout Note :
Pl ac e n ear D IM M

+0.75VS

C131

1U_0603_1 0V4Z

C132

1U_0603_1 0V4Z

1

1

2

2

+0.75VS

C159

10U_0603_6.3V6M

C962

10U_0603_6.3V6M

1

1

2

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/10/31 2009/11/06

Compal Secret Data

10U_0603_6.3V6M

C120

1

2

C133

1U_0603_1 0V4Z

1

2

C963

10U_0603_6.3V6M

1

2

Deciphered Date

2

10U_0603_6.3V6M

C121

1

2

09/03/31 HP

C134

1U_0603_1 0V4Z

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

C122

1

2

330U 2V M X LESR6M SX H1.9

10U_0603_6.3V6M

C123

C128

1

1

+

2

2

La yout Note :
Sha red be twe en th e t wo
SO- DIM Ms.
Pl ac e t wo ca paci tors c lose
to t he VR and one
be tw ee n t he tw o SODI MMs

1

Title

Size Document Num ber R ev

Cust om

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

LA -4 892 P

1

of

9 45Satu rday, May 16, 2009

0.3

5

09/04/23 HP

D D

C C

B B

A A

+V_D DR_REF_DIMMB_DQ

2.2U_0603 _6.3V4Z

1

C137

2

DDR_ CKE2_DIMMB6

DDR_B_ BS26

M_CLK_DD R26
M_CLK_DDR# 26

DDR_B_ BS06

DDR_B_W E#6
DDR_ B_CAS#6

DDR_ CS3_DIMMB#6

+3VS

1

2

0.1U_0402 _10V6K

2.2U_0603 _6.3V4Z

DDR_ B_D0
DDR_ B_D1

1

C138

DDR _B_DM0

2

DDR_ B_D2
DDR_ B_D3

DDR_ B_D8
DDR_ B_D9

DDR_ B_DQS#1
DDR _B_DQS1

DDR _B_D10
DDR _B_D11

DDR _B_D16
DDR _B_D17

DDR_ B_DQS#2
DDR _B_DQS2

DDR _B_D18
DDR _B_D19

DDR _B_D24
DDR _B_D25

DDR _B_DM3

DDR _B_D26
DDR _B_D27

DDR_ CKE2_DIMMB

DDR_ B_BS2

DDR_B_ MA12
DDR_ B_MA9

DDR _B_MA8
DDR_ B_MA5

DDR_ B_MA3
DDR_ B_MA1

M_CLK_D DR2
M_CLK_D DR#2

DDR_B_ MA10
DDR_ B_BS0

DDR_B_ WE#
DDR _B_CAS# M_ODT2

DDR_B_ MA13
DDR_ CS3_DIMMB#

DDR _B_D32
DDR _B_D33

DDR_ B_DQS#4
DDR _B_DQS4

DDR _B_D34
DDR _B_D35

DDR _B_D40
DDR _B_D41

DDR _B_DM5

DDR _B_D42
DDR _B_D43

DDR _B_D48
DDR _B_D49

DDR_ B_DQS#6
DDR _B_DQS6

DDR _B_D50
DDR _B_D51

DDR _B_D56
DDR _B_D57

DDR _B_DM7

DDR _B_D58
DDR _B_D59

1 2

10K_0402_5%

0.1U_0402 _10V6K

C157

C158

1

2

+1.5V +1.5V

3 A

3 A @1 . 5 V

@ 1. 5V

3 A3 A

@ 1. 5V@ 1. 5V

CONN @

JDIMB1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9
VSS925VSS10

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17
VSS1849DQ22

51

DQ18
DQ1953VSS19
VSS2055DQ28

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3
A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

R82

1 2

R83 10K_0402_5%

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

VSS3

DQS0

VSS6

VSS8
DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ23

DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

2
4

DQ4

6

DQ5

8
10
12
14
16

DQ6

18

DQ7

20
22
24
26
28

DM1

30
32
34
36
38
40
42
44
46

DM2

48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78

A15

80

A14

82
84
86

A7

88
90

A6

92

A4

94
96

A2

98

A0

100
102

CK1

104
106
108

BA1

110
112
114

S0#

116
118
120
122

NC2

124
126
128
130
132
134
136

DM4

138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170

DM6

172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

SDA

202

SCL

204

206

G2

BOT SLOT

5

4

DDR_ B_D4
DDR_ B_D5

DDR_ B_DQS#0
DDR _B_DQS0

DDR_ B_D6
DDR_ B_D7

DDR _B_D12
DDR _B_D13

DDR _B_DM1
DRAMRST#

DDR _B_D14
DDR _B_D15

DDR _B_D20
DDR _B_D21

DDR _B_DM2

DDR _B_D22
DDR _B_D23

DDR _B_D28
DDR _B_D29

DDR_ B_DQS#3
DDR _B_DQS3

DDR _B_D30
DDR _B_D31

DDR_ CKE3_DIMMB

DDR_B_ MA15
DDR_B_ MA14

DDR_ B_MA11
DDR_ B_MA7

DDR _B_MA6
DDR_ B_MA4

DDR_ B_MA2
DDR_ B_MA0

M_CLK_D DR3
M_CLK_D DR#3

DDR_ B_BS1
DDR _B_RAS#

DDR_ CS2_DIMMB#

M_ODT3

+VREF_ CA

DDR _B_D36
DDR _B_D37

DDR _B_DM4

DDR _B_D38
DDR _B_D39

DDR _B_D44
DDR _B_D45

DDR_ B_DQS#5
DDR _B_DQS5

DDR _B_D46
DDR _B_D47

DDR _B_D52
DDR _B_D53

DDR _B_DM6

DDR _B_D54
DDR _B_D55

DDR _B_D60
DDR _B_D61

DDR_ B_DQS#7
DDR _B_DQS7

DDR _B_D62
DDR _B_D63

PM_EXTTS#1_R
SMB_DATA_S3
SMB_CLK_S3

4

0000 .6 5 A @ 0. 75 V

. 65 A@ 0 . 7 5V

. 65 A@ 0 . 7 5V. 65 A@ 0 . 7 5V

DRAMRST# 4,9

DDR_ CKE3_DIMMB 6

M_CLK_DD R3 6
M_CLK_DDR# 3 6

DDR_B_ BS1 6
DDR_ B_RAS# 6

DDR_ CS2_DIMMB# 6
M_ODT2 6

M_ODT3 6

0.1U_0402 _10V6K

C151

1

1

2

2

PM_EXTTS#1_R 4,9

SMB_DATA_S3 4,9,12,14,2 6
SMB_CLK_S3 4,9,12,14 ,26

+0.75VS

DDR_ B_DQS#[0. .7]6

DDR_ B_D[0..6 3]6

DDR_ B_DM[0..7]6

DDR_ B_DQS[0.. 7]6

DDR_ B_MA[0..15]6

09/04/23 HP

+V_D DR_REF_DIMMB_CA

2.2U_0603 _6.3V4Z

C152

3

La yout Note :
Pl ac e n ear D IM M

La yout Note :
Pl ac e n ear D IM M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

09/03/31 HP

+1.5V

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

C141

1

2

+0.75VS

1U_0603_1 0V4Z

C153

1

1

2

2

2008/10/31 2009/11/06

C143

C142

1

1

2

2

1U_0603_1 0V4Z

1U_0603_1 0V4Z

1U_0603_1 0V4Z

C154

C156

C155

1

1

2

2

Compal Secret Data

2

10U_0603_6.3V6M

C145

C144

1

1

2

2

Deciphered Date

2

10U_0603_6.3V6M

10U_0603_6.3V6M

C146

1

2

09/04/29 HP

330U_D2_2VM_R6M

C964

1

+

2

1

Compal Electronics, Inc.

Title

Size Document Num ber R ev

Date: Sheet

DDRIII-SODIMM SLOT2

LA -4 892 P

1

10 45S aturd ay, May 16, 2009

of

0.3

5

4

3

2

1

09/04/ 03 Auburndale/Arrandale only supports M1 change Vref to +V_DDR_CPU_REF

+1.5V

12

R76

+V_D DR_REF_DIMMA_CA

D D

1K_0402_1%

12

R77

1K_0402_1%

+1.5V

12

12

R952

1K_0402_1%

R953

1K_0402_1%

+V_D DR_REF_DIMMA_DQ

09/04/23 HP

+1.5V

12

R948

1K_0402_1%

+V_D DR_REF_DIMMB_CA

+1.5V

12

R954

1K_0402_1%

+V_D DR_REF_DIMMB_DQ

12

R949

C C

1K_0402_1%

12

R955

1K_0402_1%

11/20 Auburndale does not require to support M2 for VrefDQ, HP

11/20 HP

09/03/31 Auburndale/Arrandale only supports M1,HP

B B

11/20 HP

09/03/31 Auburndale/Arrandale only supports M1,HP

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/11/06

Compal Secret Data

Deciphered Date

2

Title

Size Document Num ber R ev

Cust om

Date: Sheet

Compal Electronics, Inc.

DDRIII SO-DIMM VREFDQ (M1/M2/M3)

LA -4 892 P

1

of

11 45F rida y, May 15, 2009

0.3

5

D D

4

3

2

1

VDD_REF

XTAL_IN

XTAL_OUT

VSS_REF

VDD_CPU

CPU_0

CPU_0#

VSS_CPU

CPU_1

CPU_1#

VDD_SRC

+3VS_CK505 +1.05VS_CK505+3VS_CK505 +1.05VS_CK505

32

SCL

31

SDA

30
29
28
27
26
25

24
23
22
21
20
19
18
17

SMB_CLK_S3
SMB_DATA_S3
REF _0/CPU_SEL

CLK_XTAL_IN
CLK_XTAL_OUT

CK_PW RGD

R_C LK_BUF_BCLK CLK_B UF_BCLK
R_CL K_BUF_BCLK# CLK_BUF_BC LK#

R94 0_0402_5%

1 2
1 2

R96 0_0402_5%

CLK_14M_ PCH

R90

12

33_0402_1%

CK_PW RGD

2N7002DW T/R7_SOT-363-6

R152

Q96A

SMB_CLK_S3 4,9,10,14 ,26
SMB_DATA_S3 4,9,10,14,2 6

CLK_14M_PC H 14

CLK_BUF _BCLK 14
CLK_BUF_ BCLK# 14

1 2

10K_0402_5%

61

2

+3VS_CK505

CLK_EN# 42

C182

33P_0402_50V8J

14.31818MHZ_20P_1BX14318BE1A

CLK_XTAL_OUT

CLK_XTAL_IN

Y1

12

2

2

1

C183

33P_0402_50V8J

1

U2

1

+3VS_CK505

VDD_DOT

2

VSS_DOT

3

DOT_96

4

DOT_96#

5

VDD_27

6

27MHZ

7

27MHZ_SS

8

VSS_27

9

VSS_SATA

10

SRC_1/SATA

11

SRC_1#/SATA#

12

VSS_SRC

13

SRC_2

14

SRC_2#

15

VDD_SRC_IO

16

CPU_STOP#

SLG8SP585VT R_QFN32_5X5

REF_0/CPU_SEL

CKPWRGD/PD #

VDD_CPU_IO

TGND

33

R85 0_0402_5%

R87 0_0402_5%

R91 0_0402_5%

R92 0_0402_5%
R93 0_0402_5%
R95

0.1U_0402 _10V6K

47P_0402_50V8J

C179

C180

1

1

2

2

0.1U_0402 _10V6K

47P_0402_50V8J

C169

C168

1

1

2

2

1 2
1 2

1 2
1 2

1 2
1 2

C181

0.1U_0402 _10V6K
C170

1

2

0_0402_5%

CPU_STOP#

C221

C174

L_CLK_BUF _DOT96
L_CLK_BUF _DOT96#

L_CL K_BUF_CKSSCD
L_C LK_BUF_CKSSCD#

L_CLK _DMI
L_CLK _DMI#

CPU_STOP#

R99 10K_0402_5%

1 2

CLK_14M_ PCH

12

10P_0402_50V8J@

REF _0/CPU_SEL

12

10P_0402_50V8J@

C177

0.1U_0402 _10V6K

1

2

Close to U2

0.1U_0402 _10V6K
C178

1

2

11/06 HP

Close to U2

0.1U_0402 _10V6K

C166

1

2

CLK_BUF_D OT96
CLK_BUF_D OT96#

CLK_ BUF_CKSSCD
CLK_ BUF_CKSSCD#

CLK _DMI
CLK _DMI#

0.1U_0402 _10V6K

1

2

C167

CLK_BUF_D OT9614

CLK_BUF_D OT96#14

CLK_ BUF_CKSSCD14

+1.05VS_CK505+1.05VS

+3VS_CK505

CLK_ BUF_CKSSCD#14

CLK_D MI14

CLK_DMI#14

10U_0805_10V4K

10U_0805_10V4K

C176

1

1

2

2

0.1U_0402 _10V6K

10U_0805_10V4K

C165

C164

1

1

2

2

C C

1 2

R970_0603_5%

B B

+3VS

1 2

R840_0603_5%

EMI Capacitor

11/06 HP

A A

(Def ault )

1

CPU_ 1CPU_ 0PIN 30

133MHz

133MHz0

100MHz100MHz

5

+VCCP

1 2

R100 10K_0402_5%@

1 2

R101 10K_0402_5%

REF _0/CPU_SEL

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/10/31 2009/11/06

Compal Secret Data

Deciphered Date

2

Title

Size Document Num ber R ev

Date: Sheet o f

Compal Electronics, Inc.

CLOCK GENERATOR

LA -4 892 P

1

12 45S aturd ay, May 16, 2009

0.3

5

PCH_RTCX1

1 2

R134 10M_0402_5%

18P_0402_50V8J

1

1

C188

D D

C752 47P_0402 _50V8J

C753 39P_0402 _50V8J

C754 47P_0402 _50V8J

C755 47P_0402 _50V8J

C C

B B

PCH_JTAG_TMS
PCH_JT AG_TDO
PCH_JT AG_TDI
PCH_JT AG_RST#

A A

OSC4OSC

2

NC3NC

Y2

2

HDA_BIT _CLK_MDC

1 2

HDA_B IT_CLK_CODEC

1 2

HDA_SDO UT_MDC

1 2

HDA_S DOUT_CODE C

1 2

09/02/19 EMI

+3VALW +3VALW +3VALW

R355

PCH Pin

PCH_JT AG_TDO

PCH_JT AG_TMS

PCH_JT AG_TDI

PCH_JT AG_TCK
PCH_JT AG_RST#

PCH_RTCX2

32.768KH Z_12.5PF_Q 13MC14610002

1

C189
18P_0402_50V8J

2

12

200_0402_5%

12

R354
100_0402_1%

PRE-PR ODUCTION
ES1 ES2

R358

No Install

R535

No Install
200ohm

R355

100ohm 10 0ohm

R354

200ohm

R536

100ohm 10 0ohm

R537

51ohm 51ohm 51ohm

R156

20Kohm

R643

10Kohm NA

R353

5

HDA_BIT_ CLK_MDC25

HDA_BIT _CLK_CODEC29

HDA_ SYNC_ CODEC29

HDA_SDOU T_CODEC29

12

R358

12

+RTCVC C

HDA_ SYNC_MDC25

HDA_RST# _MDC25

HDA_RST #_CODEC29

HDA_SDOU T_MDC25

AMT_OVERR IDE30

200_0402_5%

R535
100_0402_1%

200ohm
100ohm
200ohm

200ohm

+RTCVC C

C190

1U_0603_1 0V4Z

1 2

R139 20K_0402_1%

1 2

R140 20K_0402_1%

C193

1U_0603_1 0V4Z

HDA_S PKR29

HDA_ SDIN029

HDA_ SDIN125

LID_SW #21,25, 30

+3VALW

1 2

R147 10K_0402_5%

for SMSC EC

notice KBC state

R356

PRODUCTION

No Install
No Install
No Install
No Install
No Install
No Install

NA NA

R135

1 2

R137

1 2

1

12

CLRP1

SHORT PADS

2

1

2

09/05/05

R141 33 _0402_5%

1 2

R142 33 _0402_5%

1 2

R143 33 _0402_5%

1 2

R144 33 _0402_5%

1 2

R145 33 _0402_5%

1 2

R146 33 _0402_5%

1 2

R148 33 _0402_5%

1 2

R149 33 _0402_5%

1 2

LID_SW #

KBC_SP I_CLK_R30

KBC_SPI_C S0#_R30

PCH_ SPI_CS1#_R30

KBC_ SPI_SI_R30

KBC_SPI_SO30

12

200_0402_5%

12

R537
100_0402_1%

QSRefDes

NA

1M_0402_5%

330K_0402_5%

High = Inte rnal V R Enabled(Default)

T151
PAD

4

SM_INT RUDER#

PCH _INTVRMEN

PCH_RTCX1
PCH_RTCX2

PCH_RTC RST#

PCH_SRTC RST#

SM_INT RUDER#

PCH _INTVRMEN

HDA_BIT _CLK

HD A_SYN C

HDA _SPKR

HDA_RST#

HDA_ SDIN0

HDA_ SDIN1

HDA_SDOUT

PCH_JT AG_TCK

PCH_JTAG_TMS

PCH_JT AG_TDI

PCH_JT AG_TDO

PCH_JT AG_RST#

1 2

R157 15_0402_5%

1 2

R165 15_0402_5%

PM_PWROK30,42

PLT_RST#4,16,22,2 4,27,29

XDP_DBRESET#4 ,15

1 2

R156 51_0402_5%

4

U4A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST # / GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IBEXPEAK-M_FCBGA1071

R163 1K_0402_5%

3

+3VS

D33
B33
C32
A32

C34

A34
F34

AB9

AK7
AK6
AK11
AK9

AH6
AH5
AH9
AH8

AF11
AF9
AF7
AF6

AH3
AH1
AF3
AF1

AD9
AD8
AD6
AD5

AD3
AD1
AB3
AB1

AF16

AF15

T3

Y9

V1

SIRQ

HDA _SPKR

NAND_D ET#

SIRQ

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2

SATA_PRX_DTX_N5
SATA_PRX_DTX_P5
SATA_PTX_DRX_N5
SATA_PTX_DRX_P5

SATAICOMP

1 2

R158 10K_0402_5%

GPIO21

HDD_HA LTLED

1 2

R136 10K_0402_5%

1 2

R138 1K_0402_5%@

LOW=Default HIGH=N o Reboot

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

LP C

RT CIH DA

SA TA

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

SPI JTAG

09/05/05 HP

+3VS +BATT1.1+VREG3_51125+ RTCVCC

R162

1 2

1K_0402_5%

1 2

PCH_JT AG_TDO

PCH_JT AG_TDI
PCH_JTAG_TMS

PCH_JT AG_TCK

JP3

CONN @

E-T_670 1K-Q24N-00R_24P-T

24

TCK0

GND

23

GND

GND

22

TCK1

21

TMS

20

TDI

19

TRST#

18

TDO

17

GND

16

HOOK7

15

HOOK6

14

VCCOBS_AB

13

HOOK5

12

HOOK4

11

HOOK2

10

HOOK0

9

GND

8

OBSDATA_A3

7

OBSDATA_A2

6

GND

5

OBSDATA_A1

4

OBSDATA_A0

3

GND

2

OBSFN_A1

1

OBSFN_A0

26
25

3

2

LPC_LAD0 27,30, 31
LPC_LAD1 27,30, 31
LPC_LAD2 27,30, 31
LPC_LAD3 27,30, 31

LPC_LFRAME# 27,30 ,31

LPC_LDRQ# 0 31

R155

1 2

37.4_0402_1%

NAND_DET # 19

SIRQ 2 7,30,31

SATA_PRX_DTX_N0 19
SATA_PRX_DTX_P0 19
SATA_PTX_DRX_N0 19
SATA_PTX_DRX_P0 19

SATA_PRX_DTX_N1 19
SATA_PRX_DTX_P1 19
SATA_PTX_DRX_N1 19
SATA_PTX_DRX_P1 19

+1.05VS

+3VS

SATA_LED# 28,29

09/03/31 HP

HDD_HALT LED 29

PAD

PAD

T130

T131

PAD

PAD
T132

T133

09/01/15 HP

09/03/31 HP

NB HDD

NB ODD

09/01/15 HP

11/11 HP

NAND_D ET#

GPIO21

SATA_PRX_DTX_N2 28
SATA_PRX_DTX_P2 28
SATA_PTX_DRX_N2 28
SATA_PTX_DRX_P2 28

SATA_PRX_DTX_N5 28
SATA_PRX_DTX_P5 28
SATA_PTX_DRX_N5 28
SATA_PTX_DRX_P5 28

+3VS

09/04/23 HP

R160
10K_0402_5%

1 2

1 2

R966 10K_0402_5%

Dock Up grade Bay

09/04/23 HP

eSATA i n doc king

+3VS

09/02/09 Power team

D38

2

W=20 mils

C208

1

1U_0603_1 0V4Z

2

Pla ce ne ar I BEX-M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

BAV70W_SOT323-3

2008/10/31 2009/11/06

+BATT_D

3

Compal Secret Data

1 2

W=20 mils

Deciphered Date

2

R748

1K_0402_5%

W=20 mils

CONN @

JBATT1
E-T_380 1-E02N-01R_2P

1

2

1

Title

Size Document Num ber R ev

Cust om

Date: Sheet

Compal Electronics, Inc.

IBEX-M(1/6)-HDA/JTAG/SATA

LA -4 892 P

1

of

13 45S aturd ay, May 16, 2009

0.3

5

D D

PCIE_PRX_DTX_N229

EXP

Med ia C ard

WLAN

C C

NIC

PCIE_PRX_DTX_P229
PCIE_PTX_C _DRX_N229
PCIE_PTX_C_DRX_P229

PCIE_PRX_DTX_N329
PCIE_PRX_DTX_P329
PCIE_PTX_C _DRX_N329
PCIE_PTX_C_DRX_P329

PCIE_PRX_DTX_N424
PCIE_PRX_DTX_P424
PCIE_PTX_C _DRX_N424
PCIE_PTX_C_DRX_P424

PCIE_PRX_DTX_N622
PCIE_PRX_DTX_P622
PCIE_PTX_C _DRX_N622
PCIE_PTX_C_DRX_P622

C210 0.1U_0402 _10V6K

1 2

C211 0.1U_0402 _10V6K

1 2

C209 0.1U_0402 _10V6K

1 2

C212 0.1U_0402 _10V6K

1 2

C213 0.1U_0402 _10V6K

1 2

C214 0.1U_0402 _10V6K

1 2

C217 0.1U_0402 _10V6K

1 2

C218 0.1U_0402 _10V6K

1 2

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

PCIE_PRX_DTX_N6
PCIE_PRX_DTX_P6
PCIE_PTX_DRX_N6
PCIE_PTX_DRX_P6

11/07 HP

+3VALW

1 2

R676 10K_0402_5%

+3VS

1 2

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

CLK_ PCIE_MCARD _PCH#_R

0_0402_5%

CLK_ PCIE_MCARD _PCH_R

0_0402_5%

+3VALW

+3VALW

R640 10K_0402_5%

CLK_PCIE_ EXP_PCH#_R
CLK_PCIE_ EXP_PCH_R

CLK_ PCIE_C ARD_PCH#_R
CLK_ PCIE_C ARD_PCH_R

1 2

R770 10K_0402_5%

1 2

R825 10K_0402_5%

R180

1 2
1 2

R181

R183

1 2
1 2

R184

R185

1 2
1 2

R186

+3VS

5

CLKR EQ_CARD#

3

2N7002DW T/R7_SOT-363-6
Q96B

CLK_ PCIE_CARD_ PCH#29
CLK_ PCIE_CARD_ PCH29

CLK_ PCIE_MCARD_PC H#24
CLK_ PCIE_MCARD_PC H24

09/02/19 HP

CLK_PCIE_EXP_ PCH#29
CLK_PCIE_EXP_ PCH29

CLKREQ_EXP#29

CLKRE Q_CARD#29

CLKREQ_W LAN#24

4

5

B B

EXP

Med ia C ard

WLAN

A A

CLKR EQ_CARD#_R16

T123P AD
T124P AD
T125P AD
T126P AD

4

U4B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_ B_N

AK51

CLKOUT_PEG_ B_P

P13

PEG_B_CLKRQ# / GPIO56

IBEXPEAK-M_FCBGA1071

4

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1ALERT# / GPIO74

SMBus

PCI-E *

Link

Con troll er

PEG_A_CLKRQ# / GPIO47

PEG

CLKOUT_DP_ N / CLKOUT_BCLK1_N
CLKOUT_DP_ P / CLKOUT_BCLK1_P

From C LK BUFFER

CLKIN_SATA_N / CKSSCD _N
CLKIN_SATA_P / CKSSCD _P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

Clock Flex

SMB_CLK_S3
SMB_DATA_S3

09/02/05 HP

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_ A_N
CLKOUT_PEG_ A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_BCLK_N
CLKIN_BCLK_P

CLKIN_DOT_96 N
CLKIN_DOT_96 P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

3

CONN @

JSMBUS

1

G14GND

2

5

CLK

G2

3

DATA

MOLEX_53261-0319

Set it as GPI11

SMBALERT#

B9

SMBCLK

H14

SMBDATA

C8

SML0ALERT#

J14

SML0CLK

C6

SML0DATA

G8

SML1ALERT#

M14

SML1CLK

E10

SML1DATA

G12

T13

T11

T9

PEG_CLKREQ#

H1

AD43
AD45

AN4
AN2

CLK_DP#

AT1

CLK_D P

AT3

AW24
BA24

AP3
AP1

F18
E18

AH13
AH12

P41

J42

XTAL25_IN

AH51

XTAL25_OUT

AH53

R187 90.9 _0402_1%

AF38

T45

T140 PAD

P43

T141 PAD

CLK_14M_SIO_P CLK_14M_SIO

T42

N50

T142 PAD

CLK_14M_SIO

3

T51 PAD

CLK_EXP# 4
CLK_EXP 4

T52 PAD
T53 PAD

CLK_DMI# 12
CLK_D MI 12

CLK_BUF_ BCLK# 12
CLK_BUF _BCLK 12

CLK_BUF_D OT96# 12
CLK_BUF_D OT96 12

CLK_ BUF_CKSSCD# 12
CLK_ BUF_CKSSCD 12

CLK_14M_PCH 12

CLK_P CI_FB 16

1 2

12

R118 22_0402_5%

@

1 2

C923 10P_0402 _50V8J

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

SMB_CLK_S3

SMB_DATA_S3

1 2

R169 10K_0402_5%

1 2

R171 10K_0402_5%

09/01/15 HP

SMBCLK

R351 0_ 0402_5%@

1 2

PEG_CLKREQ#

SMBALERT# SML1ALERT# S ML1ALERT#

1 2

R177 10K_0402_5%

R350

1 2

09/01/17 HP

SMBDATA

R352 0_ 0402_5%@

SML1CLK

SML1DATA

11/10 HP

1 2

R906 0_ 0402_5%

1 2

R907 0_ 0402_5%

1 2

XTAL25_IN

XTAL25_OUT

+3VALW

SMBCLK

SMBDATA

+3VS

09/02/14 HP

09/04/07 Intel

+1.05VS

CLK_14M_SIO 31

09/01/06 Intel

2008/10/31 2009/11/06

Compal Secret Data

Deciphered Date

2

+3VS

0_0402_5%@

Q8A

2N7002DW T/R7_SOT-363-6

2N7002DW T/R7_SOT-363-6

61

2

Q8B

3

4

5

09/01/15 HP

Q7A

2N7002DW T/R7_SOT-363-6

6 1

2N7002DW T/R7_SOT-363-6

3

R182 1M_0402_5%@

25MHZ_20P_1 BG25000CK1A

18P_0402_50V8J

C223

1

@

2

Not e: r emov e 25M Hz c rysta l

or E S2 s ilico n.

f

2

Q7B

4

5

1 2

Y3

1 2

SMB_CLK_S3

SMB_DATA_S3

@

18P_0402_50V8J

1

2

1

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

SMBALERT#

SML0ALERT#

1 2

R167 2.2K_0402_5%

1 2

R168 2.2K_0402_5%

1 2

R170 2.2K_0402_5%

1 2

R172 2.2K_0402_5%

1 2

R174 4.7K_0402_5%

1 2

R176 4.7K_0402_5%

1 2

R207 10K_0402_5%

1 2

R272 10K_0402_5%

1 2

R771 10K_0402_5%

R357

1 2

0_0402_5%

R360

1 2

0_0402_5%

SMB_CLK_S3 4,9,10,12 ,26

SMB_DATA_S3 4,9,10,12,2 6

+3VALW

12/19 HP

CAP_CLK 25,30

CAP_DAT 25,30

09/04/08 HP

XTAL25_IN

C224

@

Title

Size Document Num ber R ev

Cust om

Date: Sheet o f

Compal Electronics, Inc.

IBEX-M(2/6)-PCI-E/SMBUS/CLK

LA -4 892 P

12

R944 0_0402_5%

1

14 45S aturd ay, May 16, 2009

0.3