Compal LA-4853P NAWF2, Aspire 5332, Aspire 5732, Aspire 5732G, Aspire 5732Z Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

NAWF2 M/B Schematics Document

Intel Penryn Processor with Cantiga + DDRIII + ICH9M+M92-S2 XT

3 3

2009-09-17

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/07/01 2010/07/01

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB A4853

401817

153Monday, September 28, 2009

E

A

of

A

B

C

D

E

Compal Confidential

Model Name : NAWF2 File Name : LA-4853P P/N : DA60000FI00

1 1

P/N : DA60000FI10

VRAM 512MB / 256MB 64M16 x 4 / 32M16 x 4

page 21

Fan Control

page 4

DDR2 500MHz

LCD Conn.

page 23

LVDS

PCI-Express 16xATI M92-S2 XT

page 17,18,19,20,21,22

CRT Conn.

page 24

2 2

MINI Card x1

WLAN

page 33

LAN ATHEROS AR8132

page 31

PCI-Express

port 0

HDD

RJ45

page 32

Conn.

Intel Penryn Processor

uPGA-478 Package

(Socket P)

H_A#(3..35) H_D#(0..63)

667/800/1066MHz

page 4,5,6

FSB

Intel Cantiga

uFCBGA-1329

page 7,8,9,10,11,12,13

DMI

C-Link

Intel ICH9-M

S-ATA

port 1

ODD Conn.

page 29page 29

BGA-676

page 25,26,27,28

Thermal Sensor

EMC 1402

page 4

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 800/1066

USB conn x2

USB port 0, 6

3.3V 48MHz

3.3V 24.576MHz/48Mhz

USB

Clock Generator

ICS9LPRS387

page 16

204pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

CMOS Camera

HD Audio

page 14,15

Card Reader Realtek RTS5159

page 36page 34 page 23

HDA Codec

ALC272

page 38

Phone Jack x2

page 39

Audio AMP

page 39

LPC BUS

3 3

RTC CKT.

page 26

Power On/Off CKT.

page 37

DC/DC Interface CKT.

page 40

LS-4851P

POWER/B Conn.

page 36

Touch Pad

ENE KB926 D3

page 36

BIOS

page 36

page 35

Int.KBD

page 36

Power Circuit DC/DC

4 4

page 41,42,43,44 45,46,47,48,49

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/07/01 2010/07/01

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB A4853

401817

A

of

253Monday, September 28, 2009

E

A

Voltage Rails

Power Plane Description

VIN

1 1

2 2

B+ +CPU_CORE +0.75VS 0.75V switched power rail for DDR terminator +1.05VS 1.05V switched power rail +1.1VS 1.1V switched power rail ON OFF OFF +1.5V 1.5V power rail for DDR ON ON OFF +1.5VS +1.8V +1.8VS 1.8V switched power rail ON OFF OFF +2.5VS +3VALW +3V +3V_LAN +3VS +5VALW +5VS +VSB VSB always on power rail ON ON* +RTCVCC RTC power +VGA_CORE Core voltage for GPU ON OFF OFF

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU

1.5V switched power rail

1.8V power rail for GMCH LVDS

2.5V switched power rail

3.3V always on power rail

3.3V power rail for SB

3.3V power rail for LAN

3.3V switched power rail 5V always on power rail 5V switched power rail

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

B

S1 S3 S5

N/A N/A N/A

ON OFF ON OFF OFF ON OFF OFF

ON OFF OFF ON OFF

ON ON ON ON ON ON ON ON

ON ON

N/AN/AN/A OFF

ON

OFF

ON ON*

OFF ON OFF

OFF

ON*

ON

OFFON

OFF

ONON

C

STATE

SIGNAL

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SLP_S1# SLP_S3#

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

HIGH

LOWLOWLOW

D

HIGHHIGHHIGH

HIGH

ON

OFF

ON ON

ON

OFF

ON

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

AD_BID

00 V

V typ

AD_BID

0 V 0 V

V

AD_BID

8.2K +/- 5% 0.216 V 0.250 V 0.289 V

0.436 V 0.503 V 0.538 V18K +/- 5%

0.712 V 0.819 V 0.875 V33K +/- 5%

max

BOARD ID Table BTO Option Table

Board ID

0 1 2

PCB Revision

0.1(PVT2)

1.0(Pre-MP)

BTO Item BOM Structure GM45

GM@

8132 8132@

E

LOW

OFF

3 4 5 6 7

PCIE table

EC SM Bus1 address

3 3

Device

Smart Battery EEPROM(24C16/02)

Address Address

1010 000X b

ICH9M SM Bus address

Device

Clock Generator (ICS9LPRS387, SLG8SP556V)

DDR DIMM0 DDR DIMM2

Address

1101 001Xb

1001 000Xb 1001 010Xb

EC SM Bus2 address

Device

EMC 1402-1 GMT G781-1

1001 100X b0001 011X b 1001 101X b

USB table

UHCI1

EHCI1

EHCI2

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port8 Port9 Port10 Port11

MB USB Conn.

CMOS Camera Card Reader

MB USB Conn.

Wireless Card

PCIE port1 PCIE port2 PCIE port3 PCIE port4 PCIE port5 PCIE port6

SATA table

SATA port0 SATA port1 SATA port2 SATA port3

Wireless Card PCIE LAN

HDD ODD

SATA port4

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/07/01 2010/07/01

Compal Secret Data

Deciphered Date

D

SATA port5

Title

Size Document Number Rev

Date: Sheet

B

Compal Electronics, Inc.

SCHEMATIC,MB A4853

401817

A

of

353Monday, September 28, 2009

E

5

4

3

2

1

H_A#[3..35]<7>

H_REQ#[0..4]<7>

H_RS#[0..2]<7>

D D

C C

B B

BSEL2 BSEL1 BSEL0 BCLK

000266 010200

A A

H_A#[3..35] H_REQ#[0..4] H_RS#[0..2]

JCPU1A

AA4 AB2 AA3

D22

J4 L5 L4

K5

M3

N2

J1 N3 P5 P2

L2 P4 P1 R1

M1

K3 H2 K2

J3

L1 Y2

U5 R3

W6

U4 Y5 U1 R4 T5 T3

W2 W5

Y4 U2 V4

W3

V1 A6

A5 C4

D5 C6 B4 A3

M4

N5 T2 V3 B2 D2

D3 F6

16601

JCPU1A

A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#

REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#

A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]

Penryn

Penryn CONN@

CONN@

ADDR GROUP_0

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

ADDR GROUP_1

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDI TDO TMS

TRST#

DBR#

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA THERMDC

ICH

THERMTRIP#

H CLK

BCLK[0] BCLK[1]

RESERVED

H_PROCHOT#

H1 E2 G5

H5 F21 E1

F1

H_IERR#

D20 B3

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2

XDP_BPM#5

AC1

XDP_TCK

AC5

XDP_TDI

AA6 AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_DBRESET#

C20

H_PROCHOT#

D21

H_THERMDA

A24

H_THERMDC

B25 C7

A22 A21

Layout Note: H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil

+1.05VS

12

R12

R12 56_0402_5%

56_0402_5% @

@

B

2

E

3 1

C

Q2

Q2 MMBT3904_SOT23-3

MMBT3904_SOT23-3 @

@

4

H_ADS# <7> H_BNR# <7> H_BPRI# <7>

H_DEFER# <7> H_DRDY# <7> H_DBSY# <7>

H_BR0# <7>

H_INIT# <26> H_LOCK# <7> H_RESET# <7>

H_TRDY# <7> H_HIT# <7>

H_HITM# <7>

XDP_DBRESET# <27>

H_THERMTRIP# <8,26>

CLK_CPU_BCLK <16> CLK_CPU_BCLK# <16>

OCP# <27>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

EN_DFAN1<35>

EN_DFAN1 VSET

2009/01/21 2010/01/21

3

1 2

R51 330_0402_5%R51 330_0402_5%

20080430 Add soft-start for +5VS drop issue

H_THERMDA

2200P_0402_50V7K

H_THERMDC

Compal Secret Data

+VCC_FAN1

1

C158

2

Deciphered Date

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15

H_ADSTB#0<7>

H_ADSTB#1<7>

H_A20M#<26>

H_FERR#<26>

H_IGNNE#<26>

H_STPCLK#<26>

H_INTR<26>

H_NMI<26>

H_SMI#<26>

H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

1

5

+5VS

1

C106

0.01U_0402_16V7K

2

XDP_TDI

XDP_TMS XDP_BPM#5

H_PROCHOT# H_IERR#

XDP_TRST#

XDP_TCK

+3VS

C114 10U_0805_10V4ZC114 10U_0805_10V4Z

1 2

U5

1

VEN

2

VIN

3

VO

4

VSET

G993P1UF_SOP8

FAN_SPEED1<35>

R43 54.9_0402_1%R43 54.9_0402_1%

1 2

R42 54.9_0402_1%R42 54.9_0402_1%

1 2

R16 54.9_0402_1%

1 2

@

R70 56_0402_5%R70 56_0402_5% R54 56_0402_5%R54 56_0402_5%

R41 54.9_0402_1%R41 54.9_0402_1% R17 54.9_0402_1%R17 54.9_0402_1%

1 2

C159

0.1U_0402_16V4Z

1 2

U9

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

Address 1001 100X b

2

FAN1 Conn

8

GND

7

GND

6

GND

5

GND

+3VS

12

R55

R55 10K_0402_5%

10K_0402_5%

1

C115

C115 1000P_0402_50V7K

1000P_0402_50V7K

2

12 12

12

SMCLK

SMDATA

ALERT#

GND

+5VS

12

D6

D6 1SS355_SOD323-2

1SS355_SOD323-2

D7

1 2

BAS16_SOT23-3

BAS16_SOT23-3 C122

C122

10U_0805_10V4Z

1 2

C121

1000P_0402_50V7K

1 2

40mil

+VCC_FAN1

+1.05VS

JP12

1 2 3

ACES_85205-03001

ACES_85205-03001 CONN@

CONN@

left NC if no ITP 39Ohm

8 7 6 5

Title

Size Document Number Rev

B

Date: Sheet

1 2

R109

R109 10K_0402_5%

10K_0402_5%

401817

EC_SMB_CK2 <22,35> EC_SMB_DA2 <22,35>

+3VS

Compal Electronics, Inc.

SCHEMATIC,MB A4853

453Monday, September 28, 2009

1

of

A

5

4

3

2

1

H_D#[0..63]

JCPU1B

G22 G25

G24

H22

H23 H26

H25

N22

R23 M24 M23

R24

N25 M26

N24

AD26

C23 D25 C24

AF26

AF1

C21

E22 F24 E26

F23 E25

E23 K24

J24 J23

F26 K22

J26

K25 P26

L23 L22 P25

P23 P22 T24

L25 T25

L26

A26 B22

B23

C3

JCPU1B

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2]

Penryn

Penryn CONN@

CONN@

DATA GRP 0

MISC

DATA GRP 1

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]#

DATA GRP 2DATA GRP 3

D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]#

DSTBN[2]#

DSTBP[2]#

DINV[2]#

D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]#

DSTBN[3]#

DSTBP[3]#

DINV[3]# COMP[0]

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

H_D#0

PAD

PAD PAD

PAD

H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

GTL_REF0

@

@ @

@

TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

D D

H_DSTBN#0<7> H_DSTBN#2 <7> H_DSTBP#0<7> H_DSTBP#2 <7>

H_DINV#0<7>

C C

Trace Close CPU < 0.5'

Width=4 mil , Spacing: 15mil (55Ohm)

B B

R386

R386 1K_0402_1%

1K_0402_1%

R387

R387 2K_0402_1%

2K_0402_1%

+1.05VS

1 2

H_DSTBN#1<7> H_DSTBN#3 <7> H_DSTBP#1<7> H_DSTBP#3 <7>

H_DINV#1<7>

R406 1K_0402_5%@R406 1K_0402_5%@ R405 1K_0402_5%@R405 1K_0402_5%@

C438 0.1U_0402_16V4Z@C438 0.1U_0402_16V4Z@

1 2

12 12

T2

T2 T26

T26 T27

T27

CPU_BSEL0<16> CPU_BSEL1<16> CPU_BSEL2<16>

H_D#32

Y22

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

V23

H_D#37

T22

H_D#38

U25

H_D#39

U23

H_D#40

Y25

H_D#41

W22

H_D#42

Y23

H_D#43

W24

H_D#44

W25

H_D#45

AA23

H_D#46

AA24

H_D#47

AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0 COMP1 COMP2 COMP3

H_PWRGOOD H_CPUSLP#

R393 27.4_0402_1%

R393 27.4_0402_1% R394 54.9_0402_1%

R394 54.9_0402_1% R15 27.4_0402_1%

R15 27.4_0402_1% R14 54.9_0402_1%

R14 54.9_0402_1%

H_DINV#2 <7>

H_DINV#3 <7>

1 2 1 2 1 2 1 2

H_DPRSTP# <8,26,47> H_DPSLP# <26> H_DPWR# <7> H_PWRGOOD <26> H_CPUSLP# <7> PSI# <47>

TRACE CLOSELY CPU < 0.5'

COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms)

H_D#[0..63] <7>

+CPU_CORE

A10 A12 A13 A15 A17 A18 A20

B10 B12 B14 B15 B17 B18 B20

C10 C12 C13 C15 C17 C18

D10 D12 D14 D15 D17 D18

E10 E12 E13 E15 E17 E18 E20

F10 F12 F14 F15 F17 F18 F20 AA7

AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20

AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18

A7 A9

B7 B9

C9

D9

E7 E9

F7 F9

JCPU1C

VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]

Penryn

Penryn CONN@

CONN@

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

.

+CPU_CORE

VCCSENSE

VSSSENSE

C156

CPU_VID0 <47> CPU_VID1 <47> CPU_VID2 <47> CPU_VID3 <47> CPU_VID4 <47> CPU_VID5 <47> CPU_VID6 <47>

R376 100_0402_1%

R375 100_0402_1%

0.01U_0402_16V7K

1 2

C156

+1.05VS

1

2

20mils

1

C157

2

10U_0805_10V4Z

+CPU_CORE

VCCSENSE <47>

VSSSENSE <47>

+1.5VS

A A

Security Classification

2009/07/01 2010/07/01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/01 2010/07/01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

401817

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB A4853

553Monday, September 28, 2009

of

1

of

A

5

4

3

2

1

+CPU_CORE +CPU_CORE

JCPU1D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

D D

C C

B B

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Penryn

Penryn CONN@

CONN@

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

.

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

1

+

C98

C98 330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

2

+CPU_CORE

1

C465

2

10U_0805_6.3V6M

+CPU_CORE

1

C108

2

10U_0805_6.3V6M

+CPU_CORE

1

C112

2

10U_0805_6.3V6M

+CPU_CORE

1

C455

2

10U_0805_6.3V6M

+CPU-CORE Decoupling SPCAP,Polymer

MLCC 0805 X5R

+1.05VS

1

+

C13

330U_D2E_2.5VM_R9

2

2 x 330uF(6mOhm/2) 2 x 330uF(6mOhm/2)

1

+

C113

330U_D2E_2.5VM_R9

2

1

+

C107

330U_D2E_2.5VM_R9

2

South Side Secondary North Side Secondary

10U_0805_6.3V6M

1

C466

2

10U_0805_6.3V6M

1

C451

2

10U_0805_6.3V6M

1

C95

2

10U_0805_6.3V6M

1

2

C111

10U_0805_6.3V6M

1

C90

330U_D2E_2.5VM_R9

2

1

C94

2

(Place these capacitors on South side,Secondary Layer)

10U_0805_6.3V6M

1

C103

2

10U_0805_6.3V6M

1

2

C102

10U_0805_6.3V6M

1

C92

2

1

C91

2

10U_0805_6.3V6M

1

C457

2

(Place these capacitors on North side,Secondary Layer)

10U_0805_6.3V6M

1

C105

2

10U_0805_6.3V6M

1

2

C104

10U_0805_6.3V6M

1

C97

2

10U_0805_6.3V6M

1

2

C440

10U_0805_6.3V6M

1

C444

2

(Place these capacitors on South side,Primary Layer)

10U_0805_6.3V6M

1

C450

2

10U_0805_6.3V6M

1

C442

2

10U_0805_6.3V6M

1

C441

2

10U_0805_6.3V6M

1

2

C469

10U_0805_6.3V6M

1

C443

2

(Place these capacitors on North side,Primary Layer)

C,uF ESR, mohm ESL,nH 4X330uF 6m ohm/4 1.8nH/6

32X22uF 3m ohm/32 0.6nH/32 32X10uF 3m ohm/32 0.6nH/32

1

C119

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

C120

2

1

C118

2

0.1U_0402_16V4Z

1

C78

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

2

C77

0.1U_0402_16V4Z

1

C79

2

+

1

2

10U_0805_6.3V6M@

1

2

10U_0805_6.3V6M@

1

2

10U_0805_6.3V6M@

1

2

10U_0805_6.3V6M@

C93

C456

C110

C468

1

C458

10U_0805_6.3V6M@

2

1

C96

10U_0805_6.3V6M@

2

1

C109

10U_0805_6.3V6M@

2

1

C467

10U_0805_6.3V6M@

2

A A

Security Classification

2009/07/01 2010/07/01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/01 2010/07/01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB A4853

401817

A

653Monday, September 28, 2009

of

1

of

5

4

3

2

1

U23A

H_D#[0..63]<5>

D D

+1.05VS

12

R126

R126 221_0402_1%

221_0402_1%

H_SWING

width=10mil

C C

1 2

12

B B

width:spacing=10mil:20mil (<0.5")

R125

R125 100_0402_1%

100_0402_1%

H_RCOMP

R395

24.9_0402_1%

+1.05VS

1

C206

0.1U_0402_16V4Z

2

width=10mil

R139

R139 1K_0402_1%

1K_0402_1%

1 2 12

R134

R134 2K_0402_1%

2K_0402_1%

1

C216

C216 @

@

0.1U_0402_16V4Z

2

H_RESET#<4>

H_CPUSLP#<5>

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING H_RCOMP

H_RESET# H_CPUSLP#

H_AVREF

U23A

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3

G2

H_D#_4

H6

H_D#_5

H2

H_D#_6

F6

H_D#_7

D4

H_D#_8

H3

H_D#_9

M9

H_D#_10

M11

H_D#_11

J1

H_D#_12

J2

H_D#_13

N12

H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17

R2

H_D#_18

N9

H_D#_19

L6

H_D#_20

M5

H_D#_21

J3

H_D#_22

N2

H_D#_23

R1

H_D#_24

N5

H_D#_25

N6

H_D#_26

P13

H_D#_27

N8

H_D#_28

L7

H_D#_29

N10

H_D#_30

M3

H_D#_31

Y3

H_D#_32

AD14

H_D#_33

Y6

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

Y7

H_D#_38

W2

H_D#_39

AA8

H_D#_40

Y9

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

C5

H_SWING

E3

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GM@

GM@

H_ADSTB#_0 H_ADSTB#_1

H_BREQ#

H_DEFER#

HOST

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HITM# H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_HIT#

A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20

H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

J8 L3 Y13 Y1

L10 M7 AA5 AE6

L9 M8 AA6 AE5

B15 K13 F13 B13 B14

B6 F12 C8

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

H_A#[3..35] <4>

H_ADS# <4> H_ADSTB#0 <4> H_ADSTB#1 <4> H_BNR# <4> H_BPRI# <4> H_BR0# <4> H_DEFER# <4> H_DBSY# <4> CLK_MCH_BCLK <16> CLK_MCH_BCLK# <16> H_DPWR# <5> H_DRDY# <4> H_HIT# <4> H_HITM# <4> H_LOCK# <4> H_TRDY# <4>

H_DINV#0 <5> H_DINV#1 <5> H_DINV#2 <5> H_DINV#3 <5>

H_DSTBN#0 <5> H_DSTBN#1 <5> H_DSTBN#2 <5> H_DSTBN#3 <5>

H_DSTBP#0 <5> H_DSTBP#1 <5> H_DSTBP#2 <5> H_DSTBP#3 <5>

H_REQ#[0..4] <4>

H_RS#[0..2] <4>

within 100mil to Ball A9,B9

A A

Security Classification

2009/07/01 2010/07/01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/01 2010/07/01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB A4853

401817

A

753Monday, September 28, 2009

of

1

of

5

D D

All RSVD balls on GMCH should be left No Connect.

C C

MCH_CLKSEL0<16> MCH_CLKSEL1<16> MCH_CLKSEL2<16>

PM_EXTTS#0

VGATE<16,27,47>

+1.05VS

12

1 2

R177 10K_0402_5% R177 10K_0402_5%

1 2

R202 10K_0402_5% R202 10K_0402_5%

1 2

R189 10K_0402_5% R189 10K_0402_5%

H_DPRSTP#<5,26,47> PM_EXTTS#0<14> PM_EXTTS#1<15>

H_THERMTRIP#<4,26> PM_DPRSLPVR<27,47>

R398

54.9_0402_1%

54.9_0402_1% R397

R397

1 2

330_0402_5%

PM_SYNC#<27>

PLT_RST#<17,25,31,35>

5

PM_EXTTS#1 MCH_CLKREQ#

VGATE

ICH_PWROK

+3VS

2

B

E

1 2

R224 0_0402_5%@R224 0_0402_5%@

1 2

R223 0_0402_5% R223 0_0402_5%

R141 0_0402_5% R141 0_0402_5%

1 2

R135 0_0402_5% R135 0_0402_5%

1 2

R133 100_0402_5% R133 100_0402_5%

1 2

R143 0_0402_5% R143 0_0402_5%

1 2

R140 0_0402_5% R140 0_0402_5%

1 2

12

R403

R403 1K_0402_5%

1K_0402_5%

2

B

C

Q34

Q34 MMBT3904_SOT23-3

MMBT3904_SOT23-3

3 1

GMCH_PWROK

+3VS

12

R404

R404 1K_0402_5%

1K_0402_5%

C

Q33

Q33 MMBT3904_SOT23-3

MMBT3904_SOT23-3

E

3 1

+3VS

ICH_PWROK<27>

B B

A A

MCH_TSATN#

MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2

MCH_CFG_5 MCH_CFG_6 MCH_CFG_7

MCH_CFG_9 MCH_CFG_10

MCH_CFG_12 MCH_CFG_13

MCH_CFG_16

MCH_CFG_19 MCH_CFG_20

PM_SYNC#_R PM_DPRSTP#_R PM_EXTTS#0 PM_EXTTS#1 GMCH_PWROK MCH_RSTIN# THERMTRIP#_R DPRSLPVR_R

MCH_TSATN_EC# <35>

4

U23B

M36

RSVD1

N36

RSVD2

R33

RSVD3

T33

RSVD4

AH9

RSVD5

AH10

RSVD6

AH12

RSVD7

AH13

RSVD8

K12

RSVD9

AL34

RSVD10

AK34

RSVD11

AN35

RSVD12

AM35

RSVD13

T24

RSVD14

B31

RSVD15

B2

RSVD16

M1

RSVD17

AY21

RSVD20

BG23

RSVD22

BF23

RSVD23

BH18

RSVD24

BF18

RSVD25

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC_1

BF48

NC_2

BD48

NC_3

BC48

NC_4

BH47

NC_5

BG47

NC_6

BE47

NC_7

BH46

NC_8

BF46

NC_9

BG45

NC_10

BH44

NC_11

BH43

NC_12

BH6

NC_13

BH5

NC_14

BG4

NC_15

BH3

NC_16

BF3

NC_17

BH2

NC_18

BG2

NC_19

BE2

NC_20

BG1

NC_21

BF1

NC_22

BD1

NC_23

BC1

NC_24

F1

NC_25

A47

NC_26

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GM@

GM@

4

RSVD CFG PM NC

DDR CLK/ CONTROL/ COMPENSATIONHDA

CLKDMIGRAPHICS VIDMEMISC

3

AP24

SA_CK_0

AT21

SA_CK_1

AV24

SB_CK_0

AU20

SB_CK_1

AR24

SA_CK#_0

AR21

SA_CK#_1

AU24

SB_CK#_0

AV20

SB_CK#_1

BC28

SA_CKE_0

AY28

SA_CKE_1

AY36

SB_CKE_0

BB36

SB_CKE_1

BA17

SA_CS#_0

AY16

SA_CS#_1

AV16

SB_CS#_0

AR13

SB_CS#_1

BD17

SA_ODT_0

AY17

SA_ODT_1

BF15

SB_ODT_O

AY13

SB_ODT_1

BG22

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

GFX_VR_EN

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

BH21 BF28

BH28 AV42

SM_VREF

AR36

SM_PWROK

BF17

SM_REXT

BC36

B38 A38 E41 F41

F43

PEG_CLK

E43

PEG_CLK#

AE41

DMI_RXN_0

AE37

DMI_RXN_1

AE47

DMI_RXN_2

AH39

DMI_RXN_3

AE40

DMI_RXP_0

AE38

DMI_RXP_1

AE48

DMI_RXP_2

AH40

DMI_RXP_3

AE35

DMI_TXN_0

AE43

DMI_TXN_1

AE46

DMI_TXN_2

AH42

DMI_TXN_3

AD35

DMI_TXP_0

AE44

DMI_TXP_1

AF46

DMI_TXP_2

AH43

DMI_TXP_3

B33

GFX_VID_0

B32

GFX_VID_1

G33

GFX_VID_2

F33

GFX_VID_3

E33

GFX_VID_4

C34

AH37

CL_CLK

AH36

CL_DATA

AN36

CL_PWROK

AJ35

CL_RST#

AH34

CL_VREF

N28 M28 G36 E36 K36

CLKREQ#

H36

ICH_SYNC#

B12

TSATN#

B28

HDA_BCLK

B30

HDA_RST#

B29

HDA_SDI

C29

HDA_SDO

A28

HDA_SYNC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR3

SMRCOMP SMRCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

SM_PWROK SM_REXT SM_DRAMRST#

CLK_DREF_96M CLK_DREF_96M# CLK_DREF_SSC CLK_DREF_SSC#

CLK_MCH_3GPLL CLK_MCH_3GPLL#

DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3

DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3

DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3

DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3

ICH_PWROK CL_VREF

MCH_CLKREQ#

MCH_TSATN#

3

DDRA_CLK0 <14> DDRA_CLK1 <14> DDRB_CLK0 <15> DDRB_CLK1 <15>

DDRA_CLK0# <14> DDRA_CLK1# <14> DDRB_CLK0# <15> DDRB_CLK1# <15>

DDRA_CKE0 <14> DDRA_CKE1 <14> DDRB_CKE0 <15> DDRB_CKE1 <15>

DDRA_SCS0# <14> DDRA_SCS1# <14> DDRB_SCS0# <15> DDRB_SCS1# <15>

DDRA_ODT0 <14> DDRA_ODT1 <14> DDRB_ODT0 <15> DDRB_ODT1 <15>

R368 80.6_0402_1% R368 80.6_0402_1%

1 2

R367 80.6_0402_1% R367 80.6_0402_1%

1 2

SM_VREF

SM_PWROK <37>

R366 499_0402_1%

1 2

SM_DRAMRST# <14,15>

CLK_DREF_96M <16> CLK_DREF_96M# <16> CLK_DREF_SSC <16> CLK_DREF_SSC# <16>

CLK_MCH_3GPLL <16> CLK_MCH_3GPLL# <16>

DMI_ITX_MRX_N0 <27> DMI_ITX_MRX_N1 <27> DMI_ITX_MRX_N2 <27> DMI_ITX_MRX_N3 <27>

DMI_ITX_MRX_P0 <27> DMI_ITX_MRX_P1 <27> DMI_ITX_MRX_P2 <27> DMI_ITX_MRX_P3 <27>

DMI_MTX_IRX_N0 <27> DMI_MTX_IRX_N1 <27> DMI_MTX_IRX_N2 <27> DMI_MTX_IRX_N3 <27>

DMI_MTX_IRX_P0 <27> DMI_MTX_IRX_P1 <27> DMI_MTX_IRX_P2 <27> DMI_MTX_IRX_P3 <27>

CL_CLK0 <27> CL_DATA0 <27>

CL_RST#0 <27>

MCH_CLKREQ# <16> MCH_ICH_SYNC# <27>

Compal Secret Data

2009/07/01 2010/07/01

Compal Secret Data

SM_DRAMRST# would be needed for DDR3 only

For Cantiga

+1.5V +1.5V

20mil

C278

0.1U_0402_16V4Z

C264

0.1U_0402_16V4Z

Deciphered Date

80 Ohm

1 2

1

2

1 2

+1.05VS

R183

1K_0402_1%

1 2

R182

1

2

R182

511_0402_1%

1 2

2

+1.5V

R363

R363 1K_0402_1%

1K_0402_1%

R369

3.01K_0402_1%

R362

R362 1K_0402_1%

1K_0402_1%

R220

1K_0402_1%

1 2 R221 0_0402_5%

0_0402_5%

R222

1K_0402_1%

@R221

@

+DIMM_VREF

Strap Pin Table

CFG[2:0]

CFG5 CFG6 CFG9 CFG10

CFG[13:12]

CFG16 CFG19

CFG20

(PCIE/SDVO select)

SDVO_CTRLDATA L_DDC_DATA DDPC_CTRLDATA

2

1

12

SM_RCOMP_VOH

CLK_DREF_96M CLK_DREF_96M#

CLK_DREF_SSC CLK_DREF_SSC#

1

C423

0.01U_0402_16V7K

2

SM_RCOMP_VOL

1

C422

0.01U_0402_16V7K

2

R564 0_0402_5%R564 0_0402_5%

1 2

R565 0_0402_5%R565 0_0402_5%

1 2

R566 0_0402_5%R566 0_0402_5%

1 2

R567 0_0402_5%R567 0_0402_5%

1 2

12

1

C419

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K 2

1

C418

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K 2

as close as possible to the related balls

011 = FSB667 010 = FSB800 000 = FSB1067

0 = DMI x 2 1 = DMI x 4

0 = iTPM Host Interface is enabled

1 = iTPM Host Interface is Disabled 0 = Lane Reversal Enable

1 = Normal Operation (Default)

0 = PCIe Loopback Enable 1 = Disable

00 = Reserved 01 = XOR Mode Enabled 10 = All Z Mode Enabled 11 = Normal Operation

0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled

0 = Normal Operation 1 = DMI Lane Reversal Enable

0 = Only PCIE or SDVO is operational. 1 = PCIE/SDVO are operating simu.

0 = No SDVO Card Present 1 = SDVO Card Present

0 = LFP Disable 1 = LFP Card Present; PCIE disable

0 = Digital DisplayPort Disable 1 = Digital DisplayPort Device Present

MCH_CFG_5 MCH_CFG_6 MCH_CFG_7 MCH_CFG_9 MCH_CFG_10 MCH_CFG_12 MCH_CFG_13 MCH_CFG_16

MCH_CFG_19 MCH_CFG_20

Title

Size Document Number Rev

Custom

401817

Date: Sheet

*

(Default)

*

(Default)

*

(Default)

*

* *

*

(Default)

R175 2.21K_0402_1%@R175 2.21K_0402_1%@ R142 4.02K_0402_1%@R142 4.02K_0402_1%@ R162 2.21K_0402_1%@R162 2.21K_0402_1%@ R158 2.21K_0402_1%@R158 2.21K_0402_1%@ R161 2.21K_0402_1%@R161 2.21K_0402_1%@ R154 2.21K_0402_1%@R154 2.21K_0402_1%@ R153 2.21K_0402_1%@R153 2.21K_0402_1%@ R155 2.21K_0402_1%@R155 2.21K_0402_1%@

R159 4.02K_0402_1%@R159 4.02K_0402_1%@ R163 4.02K_0402_1%@R163 4.02K_0402_1%@

Compal Electronics, Inc.

SCHEMATIC,MB A4853

12 12 12 12 12 12 12 12

12 12

1

(Default)

* * *

For HM51

(Default)

*

(Default) (Default) (Default)

+3VS

of

853Monday, September 28, 2009

A

5

4

3

2

1

DDR_A_D[0..63]<14>

D D

C C

B B

DDR_A_DM[0..7]<14>

DDR_A_MA[0..14]<14>

DDR_A_DQS#[0..7]<14> DDR_B_DQS#[0..7]<15>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AJ38

AJ41 AN38 AM38

AJ36

AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36

AW36

BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12

BB9 BA9

AU10

AV9

BA11

BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6

AT5 AN10 AM11

AM5

AN12 AM13

AJ11 AJ12

AJ9 AJ8

DDR_A_D[0..63] DDR_A_DM[0..7] DDR_A_MA[0..14] DDR_A_DQS#[0..7] DDR_B_DQS#[0..7]

U23D

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

SA_RAS# SA_CAS#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7

SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

DDR SYSTEM MEMORY A

SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

CANTIGA ES_FCBGA1329GM@

SA_BS_0 SA_BS_1 SA_BS_2

SA_WE#

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9

DDR_B_D[0..63]<15>

DDR_B_MA[0..14]<15>

BD21 BG18 AT25

BB20 BD20 AY20

AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7

AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

DDR_B_DM[0..7]<15>

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_B_DQ[0..63] DDR_B_DM[0..7] DDR_B_MA[0..14]

DDR_A_BS0 <14> DDR_A_BS1 <14> DDR_A_BS2 <14>

DDR_A_RAS# <14> DDR_A_CAS# <14> DDR_A_WE# <14>

DDR_A_DQS0 <14> DDR_A_DQS1 <14> DDR_A_DQS2 <14> DDR_A_DQS3 <14> DDR_A_DQS4 <14> DDR_A_DQS5 <14> DDR_A_DQS6 <14> DDR_A_DQS7 <14>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AK47 AH46 AP47 AP46 AJ46 AJ48

AM48

AP48 AU47 AU46

BA48

AY48

AT47 AR47

BA47 BC47 BC46 BC44 BG43

BF43

BE45 BC41

BF40

BF41 BG38

BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11

BG8

BH12

BF11

BF8 BG7 BC5 BC6

AY3

AY1

BF6

BF5 BA1 BD3 AV2 AU3 AR3 AN2

AY2 AV1 AP3 AR1

AL1

AL2

AJ1 AH1 AM2 AM3 AH3

AJ3

U23E

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

BC16

SB_BS_0

BB17

SB_BS_1

BB33

SB_BS_2

AU17

SB_RAS#

BG16

SB_CAS#

BF14

SB_WE#

DDR_B_DM0

AM47

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7

SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2

DDR SYSTEM MEMORY B

SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

CANTIGA ES_FCBGA1329GM@

AY47 BD40 BF35 BG11 BA3 AP1 AK2

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6

AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14

DDR_B_BS0 <15> DDR_B_BS1 <15> DDR_B_BS2 <15>

DDR_B_RAS# <15> DDR_B_CAS# <15> DDR_B_WE# <15>

DDR_B_DQS0 <15> DDR_B_DQS1 <15> DDR_B_DQS2 <15> DDR_B_DQS3 <15> DDR_B_DQS4 <15> DDR_B_DQS5 <15> DDR_B_DQS6 <15> DDR_B_DQS7 <15>

A A

Security Classification

2009/07/01 2010/07/01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/01 2010/07/01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB A4853

401817

A

953Monday, September 28, 2009

of

1

of

5

D D

C C

R157

R156

0_0402_5%

1 2

Change to 0Ohm for DIS

R173

12

0_0402_5%

R172

12

0_0402_5%

R171

12

0_0402_5%

B B

0_0402_5%

R160

0_0402_5%

1 2

4

LBKLT_EN

GMCH_TV_COMPS GMCH_TV_LUMA GMCH_TV_CRMA

TV_DCONSEL_0 TV_DCONSEL_1

CRT_IREF

R174

0_0402_5%

1 2

G32 M32 M33 K33

M29 C44

B43 E37 E38

C41 C40 B37 A37

H47 E46 G40 A40

H48 D45

B40 A41

H38 G37

B42 G38

K37

H25 K25

H24

C31 E32

E28 G28

G29 H32

E29

U23C

L32

J33

F40

J37

F37

F25

J28

J32 J29

L29

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN

LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL

LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3

LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3

LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3

LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3

TVA_DAC TVB_DAC TVC_DAC

TV_RTN

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE CRT_GREEN CRT_RED CRT_IRTN CRT_DDC_CLK

CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF

CRT_VSYNC

3

PEG_COMP

PEG_COMPI

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9

LVDS TV VGA

PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8

PCI-EXPRESS GRAPHICS

PEG_TX#_9

PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

CANTIGA ES_FCBGA1329GM@

T37 T36

PCIE_GTX_C_MRX_N0

H44

PCIE_GTX_C_MRX_N1

J46

PCIE_GTX_C_MRX_N2

L44

PCIE_GTX_C_MRX_N3

L40

PCIE_GTX_C_MRX_N4

N41

PCIE_GTX_C_MRX_N5

P48

PCIE_GTX_C_MRX_N6

N44

PCIE_GTX_C_MRX_N7

T43

PCIE_GTX_C_MRX_N8

U43

PCIE_GTX_C_MRX_N9

Y43

PCIE_GTX_C_MRX_N10

Y48

PCIE_GTX_C_MRX_N11

Y36

PCIE_GTX_C_MRX_N12

AA43

PCIE_GTX_C_MRX_N13

AD37

PCIE_GTX_C_MRX_N14

AC47

PCIE_GTX_C_MRX_N15

AD39

PCIE_GTX_C_MRX_P0

H43

PCIE_GTX_C_MRX_P1

J44

PCIE_GTX_C_MRX_P2

L43

PCIE_GTX_C_MRX_P3

L41

PCIE_GTX_C_MRX_P4

N40

PCIE_GTX_C_MRX_P5

P47

PCIE_GTX_C_MRX_P6

N43

PCIE_GTX_C_MRX_P7

T42

PCIE_GTX_C_MRX_P8

U42

PCIE_GTX_C_MRX_P9

Y42

PCIE_GTX_C_MRX_P10

W47

PCIE_GTX_C_MRX_P11

Y37

PCIE_GTX_C_MRX_P12

AA42

PCIE_GTX_C_MRX_P13

AD36

PCIE_GTX_C_MRX_P14

AC48

PCIE_GTX_C_MRX_P15

AD40

PCIE_MTX_GRX_N0

J41

PCIE_MTX_GRX_N1

M46

PCIE_MTX_GRX_N2

M47

PCIE_MTX_GRX_N3

M40

PCIE_MTX_GRX_N4

M42

PCIE_MTX_GRX_N5

R48

PCIE_MTX_GRX_N6

N38

PCIE_MTX_GRX_N7

T40

PCIE_MTX_GRX_N8

U37

PCIE_MTX_GRX_N9

U40

PCIE_MTX_GRX_N10

Y40

PCIE_MTX_GRX_N11

AA46

PCIE_MTX_GRX_N12

AA37

PCIE_MTX_GRX_N13

AA40

PCIE_MTX_GRX_N14

AD43

PCIE_MTX_GRX_N15

AC46

PCIE_MTX_GRX_P0

J42

PCIE_MTX_GRX_P1

L46

PCIE_MTX_GRX_P2

M48

PCIE_MTX_GRX_P3

M39

PCIE_MTX_GRX_P4

M43

PCIE_MTX_GRX_P5

R47

PCIE_MTX_GRX_P6

N37

PCIE_MTX_GRX_P7

T39

PCIE_MTX_GRX_P8

U36

PCIE_MTX_GRX_P9

U39

PCIE_MTX_GRX_P10

Y39

PCIE_MTX_GRX_P11

Y46

PCIE_MTX_GRX_P12

AA36

PCIE_MTX_GRX_P13

AA39

PCIE_MTX_GRX_P14

AD42

PCIE_MTX_GRX_P15

AD46

10mils

2

1 2

R184 49.9_0402_1% R184 49.9_0402_1%

PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_C_GRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15] PCIE_GTX_C_MRX_P[0..15]

C810 0.1U_0402_16V7KC810 0.1U_0402_16V7K

1 2

C812 0.1U_0402_16V7KC812 0.1U_0402_16V7K

1 2

C814 0.1U_0402_16V7KC814 0.1U_0402_16V7K

1 2

C816 0.1U_0402_16V7KC816 0.1U_0402_16V7K

1 2

C818 0.1U_0402_16V7KC818 0.1U_0402_16V7K

1 2

C820 0.1U_0402_16V7KC820 0.1U_0402_16V7K

1 2

C822 0.1U_0402_16V7KC822 0.1U_0402_16V7K

1 2

C824 0.1U_0402_16V7KC824 0.1U_0402_16V7K

1 2

C826 0.1U_0402_16V7KC826 0.1U_0402_16V7K

1 2

C828 0.1U_0402_16V7KC828 0.1U_0402_16V7K

1 2

C830 0.1U_0402_16V7KC830 0.1U_0402_16V7K

1 2

C832 0.1U_0402_16V7KC832 0.1U_0402_16V7K

1 2

C834 0.1U_0402_16V7KC834 0.1U_0402_16V7K

1 2

C836 0.1U_0402_16V7KC836 0.1U_0402_16V7K

1 2

C838 0.1U_0402_16V7KC838 0.1U_0402_16V7K

1 2

C840 0.1U_0402_16V7KC840 0.1U_0402_16V7K

1 2

+1.05VS

PCIE_MTX_C_GRX_N[0..15] <17> PCIE_MTX_C_GRX_P[0..15] <17>

C809 0.1U_0402_16V7KC809 0.1U_0402_16V7K

1 2

C811 0.1U_0402_16V7KC811 0.1U_0402_16V7K

1 2

C813 0.1U_0402_16V7KC813 0.1U_0402_16V7K

1 2

C815 0.1U_0402_16V7KC815 0.1U_0402_16V7K

1 2

C817 0.1U_0402_16V7KC817 0.1U_0402_16V7K

1 2

C819 0.1U_0402_16V7KC819 0.1U_0402_16V7K

1 2

C821 0.1U_0402_16V7KC821 0.1U_0402_16V7K

1 2

C823 0.1U_0402_16V7KC823 0.1U_0402_16V7K

1 2

C825 0.1U_0402_16V7KC825 0.1U_0402_16V7K

1 2

C827 0.1U_0402_16V7KC827 0.1U_0402_16V7K

1 2

C829 0.1U_0402_16V7KC829 0.1U_0402_16V7K

1 2

C831 0.1U_0402_16V7KC831 0.1U_0402_16V7K

1 2

C833 0.1U_0402_16V7KC833 0.1U_0402_16V7K

1 2

C835 0.1U_0402_16V7KC835 0.1U_0402_16V7K

1 2

C837 0.1U_0402_16V7KC837 0.1U_0402_16V7K

1 2

C839 0.1U_0402_16V7KC839 0.1U_0402_16V7K

1 2

1

PCIE_GTX_C_MRX_N[0..15] <17> PCIE_GTX_C_MRX_P[0..15] <17>

PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_N15

PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15

Change to 0Ohm for DIS

A A

R186 0_0402_5%

1 2

@

R176 0_0402_5%

1 2

@

R179 100K_0402_5%

1 2

5

TV_DCONSEL_0 TV_DCONSEL_1 LBKLT_EN

Security Classification

2009/07/01 2010/07/01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/01 2010/07/01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB A4853

401817

1

A

10 53Monday, September 28, 2009

of

5

U23F

DDR3

D D

+1.5V

Reference PILLAR_ROCK CRB Rev1.0

Pins BA36, BB24, BD16, BB21, AW16, AW13, AT13 could be left NC for DDR2 board.

C C

B B

T17

T17 T18

T18

A A

PAD

PAD PAD

PAD

VCC_SM_BA36 VCC_SM_BB24 VCC_SM_BD16

VCC_SM_AW16 VCC_SM_AT13

@

@ @

@

+VGFX_CORE

VCC_AXG_SENSE VSS_AXG_SENSE

5

U23F

2600mA

AP33

VCC_SM_1

AN33

VCC_SM_2

BH32

VCC_SM_3

BG32

VCC_SM_4

BF32

VCC_SM_5

BD32

VCC_SM_6

BC32

VCC_SM_7

BB32

VCC_SM_8

BA32

VCC_SM_9

AY32

VCC_SM_10

AW32

VCC_SM_11

AV32

VCC_SM_12

AU32

VCC_SM_13

AT32

VCC_SM_14

AR32

VCC_SM_15

AP32

VCC_SM_16

AN32

VCC_SM_17

BH31

VCC_SM_18

BG31

VCC_SM_19

BF31

VCC_SM_20

BG30

VCC_SM_21

BH29

VCC_SM_22

BG29

VCC_SM_23

BF29

VCC_SM_24

BD29

VCC_SM_25

BC29

VCC_SM_26

BB29

VCC_SM_27

BA29

VCC_SM_28

AY29

VCC_SM_29

AW29

VCC_SM_30

AV29

VCC_SM_31

AU29

VCC_SM_32

AT29

VCC_SM_33

AR29

VCC_SM_34

AP29

VCC_SM_35

BA36

VCC_SM_36/NC

BB24

VCC_SM_37/NC

BD16

VCC_SM_38/NC

BB21

VCC_SM_39/NC

AW16

VCC_SM_40/NC

AW13

VCC_SM_41/NC

AT13

VCC_SM_42/NC

Y26

VCC_AXG_1

AE25

VCC_AXG_2

AB25

VCC_AXG_3

AA25

VCC_AXG_4

AE24

VCC_AXG_5

AC24

VCC_AXG_6

AA24

VCC_AXG_7

Y24

VCC_AXG_8

AE23

VCC_AXG_9

AC23

VCC_AXG_10

AB23

VCC_AXG_11

AA23

VCC_AXG_12

AJ21

VCC_AXG_13

AG21

VCC_AXG_14

AE21

VCC_AXG_15

AC21

VCC_AXG_16

AA21

VCC_AXG_17

Y21

VCC_AXG_18

AH20

VCC_AXG_19

AF20

VCC_AXG_20

AE20

VCC_AXG_21

AC20

VCC_AXG_22

AB20

VCC_AXG_23

AA20

VCC_AXG_24

T17

VCC_AXG_25

T16

VCC_AXG_26

AM15

VCC_AXG_27

AL15

VCC_AXG_28

AE15

VCC_AXG_29

AJ15

VCC_AXG_30

AH15

VCC_AXG_31

AG15

VCC_AXG_32

AF15

VCC_AXG_33

AB15

VCC_AXG_34

AA15

VCC_AXG_35

Y15

VCC_AXG_36

V15

VCC_AXG_37

U15

VCC_AXG_38

AN14

VCC_AXG_39

AM14

VCC_AXG_40

U14

VCC_AXG_41

T14

VCC_AXG_42

AJ14

VCC_AXG_SENSE

AH14

VSS_AXG_SENSE

CANTIGA ES_FCBGA1329

GM@

VCC_AXG_NTCF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC SM

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43

VCC GFX NCTF

VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52

POWER

VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60

VCC GFX

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

AV44 BA37 AM40 AV21 AY5 AM10 BB13

4

+VGFX_CORE

4

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

C213

0.1U_0402_16V7K

1

2

DDR3

Reference PILLAR_ROCK CRB Rev1.0

VCC_SM_BA36 VCC_SM_BB24 VCC_SM_BD16 VCC_SM_AW16 VCC_SM_AT13

1

C205

C230

C215

2

0.1U_0402_16V7K

C230

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K 2

0.22U_0402_6.3V6K

3

2

Place close to the GMCH

VCC: 1930.4mA (GMCH), 1210.34mA (MCH)

+1.05VS

1

+

C485

@+C485

@

220U_D2_4VM_R15

2

(270UF*1, 22UF*1, 0.22UF*2, 0.1UF*1)

1

C255

C265

C266

0.1U_0402_16V4Z

0.22U_0402_6.3V6K

2

10U_0805_10V4Z

0.1U_0402_16V4Z

0.22U_0402_6.3V6K

1

C256

2

+1.05VS

Cavity Capacitors

+VGFX_CORE

R568

R568 0_0402_5%

0_0402_5%

+1.5V

C269

330U_D2E_2.5VM_R9

VCC_AXG: 6326.84mA (330UF*2, 22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2)

C244

C243

0.47U_0603_16V4Z

0.47U_0603_16V4Z @

@

1

+

C482

@

C482

@

330U_D2E_2.5VM_R9

2

1U_0402_6.3V4Z

@

C234

1

10U_0805_10V4Z

2

@

Cavity Capacitors

Place close to the GMCH

VCC_SM: 2600mA (330UF*1, 22UF*2, 0.1UF*1)

1

+

2

C252

2

10U_0805_10V4Z

C251

2

1

C263

2

0.1U_0402_16V4Z

C235

1

0.1U_0402_16V4Z

2

@

10U_0805_10V4Z

C236

C242

1

@

2

0.1U_0402_16V4Z

For HM51

1

@

2

Place on the edge

1

C229

C228

@

2

0.1U_0402_16V7K

1

C270

2

1U_0402_6.3V4Z

3

C228 @

@

0.1U_0402_16V7K

1

2

C214

C214 @

@

0.1U_0402_16V7K

0.1U_0402_16V7K 2

1

C272

0.47U_0603_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

1

C271

C271 @

@

0.1U_0402_16V7K

0.1U_0402_16V7K 2

Compal Secret Data

Deciphered Date

1

C240

C240 @

@

2

0.1U_0402_16V7K

1

C279

C279 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

2009/07/01 2010/07/01

2

U23G

AG34

VCC_1

AC34

VCC_2

AB34

VCC_3

AA34

VCC_4

Y34

VCC_5

V34

VCC_6

U34

VCC_7

AM33

VCC_8

AK33

VCC_9

AJ33

VCC_10

AG33

VCC_11

AF33

VCC_12

AE33

VCC_13

AC33

VCC_14

AA33

VCC_15

Y33

VCC_16

W33

VCC_17

V33

VCC_18

U33

VCC_19

AH28

VCC_20

AF28

VCC_21

AC28

VCC_22

AA28

VCC_23

AJ26

VCC_24

AG26

VCC_25

AE26

VCC_26

AC26

VCC_27

AH25

VCC_28

AG25

VCC_29

AF25

VCC_30

AG24

VCC_31

AJ23

VCC_32

AH23

VCC_33

AF23

VCC_34

T32

VCC_35

CANTIGA ES_FCBGA1329

GM@

1

VCC CORE

POWER

+1.05VS

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28

VCC NCTF

VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB A4853

401817

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

1

of

11 53Monday, September 28, 2009

A

5

4

3

2

1

L18

+1.05VS

VCCA_HPLL: 24mA

Please check Power source if want support IAMT

D D

(4.7UF*1, 0.1UF*1)

VCCA_MPLL: 139.2mA (22UF*1, 0.1UF*1)

1 2

MBK1608121YZF_0603

120Ohm@100MHz

L6

1 2

MBK1608121YZF_0603

VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1)

1 2

+3VS

L21

L21 MBK1608221YZF_0603

MBK1608221YZF_0603

@

1

+

C483

@+C483

@

220U_D2_4VM_R15

2

For HM51

C C

VCCA_DAC_BG: 2.6833333mA (0.1UF*1, 0.01UF*1)

1 2

+3VS

L20

L20 MBK1608221YZF_0603

MBK1608221YZF_0603

@

For HM51

VCCA_TV_DAC: 40mA (0.1UF*1,

B B

0.01UF*1 for each DAC)

L19

+3VS

MBK1608221YZF_0603

180Ohm@100MHz

+1.05VS_HPLL

C433

4.7U_0805_10V4Z

+1.05VS_MPLL

R108

0.5_0603_1%

C151

C151 22U_0805_6.3V6M

22U_0805_6.3V6M

1

C475

C475 @

@

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

0.01U_0402_16V7K

Close to Ball A26, B27

1

C461

C473

@

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

0.01U_0402_16V7K

Close to Ball A25

1 2

@

C472

C472 @

@

0.1U_0402_16V4Z

1

C434

2

0.1U_0402_16V4Z

12

C189

0.1U_0402_16V4Z

1

2

+3VS_CRTDAC

1

C462

C462 @

@

2

Please check Power source if want support IAMT

1

C474

C474 @

@

10U_0805_6.3V6M

2

1

C460

C460 @

@

2

0.01U_0402_16V7K

1

2

Please check Power source if want support IAMT

1

2

12

R571

R571 0_0402_5%

0_0402_5%

+1.05VS

+3VS_DACBG

12

1

R573

R573 0_0402_5%

0_0402_5%

2

+3VS_TVDAC

12

1

R574

R574 0_0402_5%

0_0402_5%

2

FOR EMI 20080226

+1.05VS

FOR EMI 20080226

For HM51

R262

R262 0_0402_5%@

0_0402_5%@

1 2

+3VS

R261

R261 0_0402_5%

0_0402_5%

1 2

+1.5VS

Please check Power source if want support IAMT

+1.05VS

C304

10U_0805_6.3V6M

1

+

C478

C478 @

@ 220U_D2_4VM_R15

220U_D2_4VM_R15

2

+1.05VS

L22

1 2

MBK1608121YZF_0603

@

VCCA_DPLLA VCCA_DPLLB: 64.8mA (220UF*1, 0.1UF*1)

L12

1 2

MBK1608121YZF_0603

@

12

1 2 R152

R152 0_0805_5%

0_0805_5%

Please check Power source if want support IAMT

For HM51

VCCD_TVDAC: 58.696mA (0.1UF*1, 0.01UF*1)

1 2

+1.5VS

L7

MBK1608221YZF_0603

A A

+1.5VS

1 2

R144

R144 100_0603_1%

100_0603_1%

180Ohm@100MHz

5

1

C246

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

0.022U_0402_16V7K

VCCD_QDAC: 48.363mA (0.1UF*1, 0.01UF*1)

1

C247

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

0.01U_0402_16V7K

C245

C257

1

2

1

2

+1.5VS_TVDAC

Also power for internal Thermal Sensor

+1.5VS_QDAC

12

R165

R165 0_0402_5%

0_0402_5% @

@

Please check Power source if want support IAMT

4

+1.05VS_DPLLA

@

C479

C479 220U_D2_4VM_R15

220U_D2_4VM_R15

+1.05VS_DPLLB

@

C305

C305 10U_0805_10V4Z

10U_0805_10V4Z

+1.8V_TX_LVDS

+VCCA_PEG_BG

1

C289

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

No CIS Symbol

L10

1 2

MBK1608221YZF_0603

1 2

R201

R201 1_0402_1%

1_0402_1%

+1.05VS_A_SM

+1.05VS_A_SM_CK

1 2

R170

R170 0_0603_5%

0_0603_5%

2.2U_0603_6.3V6K

NO_STUFF

+1.05VS_HPLL

+1.8V

For HM51

1

C464

+

@

2

0.1U_0402_16V4Z

1

C290

C290 @

@

2

0.1U_0402_16V4Z

C291

C291 @

@ 1000P_0402_50V7K

1000P_0402_50V7K

VCCA_SM: (22UF*2, 4.7UF*1, 1UF*1)

C233

22U_0805_6.3V6M

1

C241

C241 @

@

2

0_0402_5%

12

1

R569

2

0_0402_5%

12

1

R570

2

0_0402_5%

1

VCCA_LVDS: 13.2mA (1000PF*1)

2

VCCA_PEG_BG: 0.414mA (0.1UF*1)

+1.05VS_PEGPLL

1

2

C254

22U_0805_6.3V6M

VCCA_PEG_PLL: 50mA

1

C288

(0.1UF*1)

0.1U_0402_16V4Z

2

1

C231

4.7U_0805_10V4Z

4.7U_0805_10V4Z 2

VCCA_SM_CK: 24mA (22UF*1, 2.2UF*1, 0.1UF*1)

1

C253

0.1U_0402_16V4Z

2

+3VS_TVDAC

VCCD_HDA: 50mA (0.1UF*1)

12

R402

VCCD_HPLL: 157.2mA (0.1UF*1)

+1.05VS_PEGPLL

VCCD_PEG_PLL: 50mA (0.1UF*1)

1 2

R192

R192 0_0603_5%

0_0603_5%

@

C274

C274 @

@

10U_0805_6.3V6M

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS_CRTDAC

+3VS_DACBG

+1.05VS_DPLLA +1.05VS_DPLLB

+1.05VS_HPLL +1.05VS_MPLL

1

C232

2

1U_0402_6.3V4Z

1

2

+1.5VS_HDA

+1.5VS_TVDAC

+1.5VS_QDAC

+1.8V_LVDS

1

@ C273

@

2

1U_0402_6.3V4Z

VCCD_LVDS: 60.311111mA (1UF*1)

Issued Date

AD48

AA48

AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16

AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25

AL25

AM24

AL24

AM23

AL23

AA47

1

C273

2

3

U23H

852mA

73mA

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

2.69mA

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

64.8mA

F47

VCCA_DPLLA

L48

VCCA_DPLLB

24mA

AD1

VCCA_HPLL

139.2mA

AE1

VCCA_MPLL

13.2mA

J48

VCCA_LVDS

J47

VSSA_LVDS

0.414mA

VCCA_PEG_BG

50mA

VCCA_PEG_PLL

480mA

VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_6 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9

24mA

VCCA_SM_CK_1 VCCA_SM_CK_2 VCCA_SM_CK_3 VCCA_SM_CK_4 VCCA_SM_CK_5 VCCA_SM_CK_NCTF_1 VCCA_SM_CK_NCTF_2 VCCA_SM_CK_NCTF_3 VCCA_SM_CK_NCTF_4 VCCA_SM_CK_NCTF_5 VCCA_SM_CK_NCTF_6 VCCA_SM_CK_NCTF_7 VCCA_SM_CK_NCTF_8

87.79mA

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

50mA

A32

VCC_HDA

58.696mA

M25

VCCD_TVDAC

48.363mA

L28

VCCD_QDAC

157.2mA

AF1

VCCD_HPLL

50mA

VCCD_PEG_PLL

60.31mA

M38

VCCD_LVDS_1

L37

VCCD_LVDS_2

CANTIGA ES_FCBGA1329

GM@

12

R575

R575 0_0402_5%

0_0402_5%

2009/07/01 2010/07/01

CRTPLLA LVDSA PEG

VTT

POWER

A SM

AXF

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

A CK

HV

TV

HDA

DMI PEG

VTTLF

LVDS D TV/CRT

Compal Secret Data

Deciphered Date

118.8mA

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

105.3mA

VCC_HV_1 VCC_HV_2 VCC_HV_3

1782mA

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5

456mA

VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4

VTTLF1 VTTLF2 VTTLF3

U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1

B22 B21 A21

BF21 BH20 BG20 BF20

K47

VCC_HV: 105.3mA

C35 B35 A35

V48 U48 V47 U47 U46

AH48 AF48 AH47 AG47

VCC_DMI: 456mA (0.1UF*1)

VTTLF_CAP1

A8

VTTLF_CAP2

L1

VTTLF_CAP3

AB2

VTT: 852mA

+1.05VS

(270UF*1, 4.7UF*2, 2.2UF*1, 0.47UF*1)

1

+

C481

C481 220U_D2_4VM_R15

220U_D2_4VM_R15

2

4.7U_0805_10V4Z

+1.05VS_AXF

1

C471

C471 @

@

10U_0805_6.3V6M

2

+1.5V_SM_CK

+1.8V_TX_LVDS: 118.8mA (22UF*1, 1000PF*1)

12

R572

0_0402_5%

+3VS

1

C267

0.1U_0402_16V4Z

2

+1.05VS_PEG: 1782mA (220UF*1, 22UF*1, 4.7UF*1)

+1.05VS_DMI

1

C190

C445

0.47U_0603_16V4Z

0.47U_0603_16V4Z 2

0.47U_0603_16V4Z

2

1

C470

0.47U_0603_16V4Z

2

D15

2 1

+1.05VS +3VS

CH751H-40PT_SOD323-2

1

C154

C155

4.7U_0805_10V4Z

2

2.2U_0603_6.3V6K

VCC_AXF: 321.35mA (10UF*1, 1UF*1)

C459

1U_0402_6.3V4Z

1

2

10U_0805_10V4Z

1 2

R399

R399 0_0603_5%

0_0603_5%

1

2

VCC_SM_CK: 119.85mA (10UF*1, 0.1UF*1)

C424

0.1U_0402_16V4Z

+1.8V_TX_LVDS

1

C293

C292

@

1000P_0402_50V7K

1

2

1

C287

0.1U_0402_16V4Z

2

Date: Sheet

2

10U_0805_10V4Z

+1.05VS_PEG

1

+

C312

C311

220U_D2_4VM_R15

2

1 2

R225

R225 0_0805_5%

0_0805_5%

R263

1 2

10_0603_5%

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

401817

1

2

1 2

R361

R361 1_0402_1%

1_0402_1%

SCHEMATIC,MB A4853

C152

C153

0.47U_0603_16V4Z

2

Please check Power source if want support IAMT

+1.05VS

1uH 30%

1 2

L17

L17 MBK1608121YZF_0603

MBK1608121YZF_0603

0.1uH 20%

1 2

R226

@R226

@

0_0603_5%

1 2

C250

C250 10U_0805_6.3V6M

10U_0805_6.3V6M

For HM51

1 2

R264

R264 0_0805_5%

0_0805_5%

+1.05VS

DDR3

+1.5V

Please check Power source if want support IAMT

+1.05VS

12 53Monday, September 28, 2009

1

+1.8V

A

of

5

U23I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

VSS_8

AD47

VSS_9

AB47

VSS_10

Y47

VSS_11

T47

BD46 BA46 AY46 AV46 AR46

AM46

BF44 AH44 AD44 AA44

BC43 AV43 AU43

AM43

BG42 AY42 AT42 AN42

AJ42

AE42

BD41 AU41

AM41

AH41 AD41 AA41

BG40 BB40 AV40 AN40

AT39

AM39

AJ39

AE39

BH38 BC38 BA38 AU38 AH38 AD38 AA38

BF37 BB37

AW37

AT37 AN37

AJ37

BG36 BD36 AK15 AU36

VSS_12

N47

VSS_13

L47

VSS_14

G47

VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21

V46

VSS_22

R46

VSS_23

P46

VSS_24

H46

VSS_25

F46

VSS_26 VSS_27 VSS_28 VSS_29 VSS_30

Y44

VSS_31

U44

VSS_32

T44

VSS_33

M44

VSS_34

F44

VSS_35 VSS_36 VSS_37 VSS_38 VSS_39

J43

VSS_40

C43

VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47

N42

VSS_48

L42

VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55

Y41

VSS_56

U41

VSS_57

T41

VSS_58

M41

VSS_59

G41

VSS_60

B41

VSS_61 VSS_62 VSS_63 VSS_64 VSS_65

H40

VSS_66

E40

VSS_67 VSS_68 VSS_69 VSS_70 VSS_71

N39

VSS_72

L39

VSS_73

B39

VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81

Y38

VSS_82

U38

VSS_83

T38

VSS_84

J38

VSS_85

F38

VSS_86

C38

VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93

H37

VSS_94

C37

VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

GM@

VSS

CANTIGA ES_FCBGA1329

D D

C C

B B

A A

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6

4

U23J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

VSS_230

M17

VSS_231

H17

VSS_232

C17 BA16 AU16

AN16

BG15 AC15

W15

BG14 AA14

BG13 BC13 BA13

AN13

AJ13

AE13

BF12 AV12 AT12

AM12

AA12

BD11 BB11 AY11 AN11 AH11

BG10 AV10 AT10

AJ10 AE10 AA10

N16 G16

C14

N13 G13

N11 G11 C11

M10 BF9 BC9 AN9 AM9 AD9

BH8 BB8 AV8 AT8

VSS_233 VSS_235 VSS_237

VSS_238 VSS_239

K16

VSS_240 VSS_241

E16

VSS_242 VSS_243 VSS_244 VSS_245

A15

VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252

VSS_255 VSS_256 VSS_257 VSS_258

L13

VSS_259 VSS_260

E13

VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266

J12

VSS_267

A12

VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273

Y11

VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290

G9

VSS_291

B9

VSS_292 VSS_293 VSS_294 VSS_295 VSS_296

GM@

VSS

VSS NCTF

CANTIGA ES_FCBGA1329

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5

VSS SCB

NC

3

VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325

VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350

VSS_351 VSS_352 VSS_353 VSS_354

NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

U24 U28 U25 U29

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

BH48 BH1 A48 C1 A3

E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48

2

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/07/01 2010/07/01

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB A4853

401817

A

of

13 53Monday, September 28, 2009

1

5

+DIMM_VREF

DDR_A_D0 DDR_A_D1

DDR_A_DM0 DDR_A_D2

C907

DDR_A_D3 DDR_A_D8

DDR_A_D9 DDR_A_DQS#1

DDR_A_DQS1 DDR_A_D10

DDR_A_D11 DDR_A_D16

DDR_A_D17 DDR_A_DQS#2

DDR_A_DQS2 DDR_A_D18

DDR_A_D19 DDR_A_D24

DDR_A_D25 DDR_A_DM3 DDR_A_D26

DDR_A_D27

DDRA_CKE0

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3

DDR_A_MA1 DDRA_CLK0

DDRA_CLK0# DDR_A_MA10

DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# DDR_A_MA13

DDRA_SCS1#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5 DDR_A_D42

DDR_A_D43 DDR_A_D48

DDR_A_D49 DDR_A_DQS#6

DDR_A_DQS6 DDR_A_D50

DDR_A_D51 DDR_A_D56

DDR_A_D57 DDR_A_DM7 DDR_A_D58

DDR_A_D59

R601

1 2

10K_0402_5%

1

C908

2

2.2U_0603_6.3V4Z

0.1U_0402_16V4Z

D D

C C

B B

A A

DDRA_CKE0<8>

DDR_A_BS2<9>

DDRA_CLK0<8> DDRA_CLK0#<8>

DDR_A_BS0<9>

DDR_A_WE#<9>

DDR_A_CAS#<9> DDRA_ODT0 <8>

DDRA_SCS1#<8>

+3VS

+1.5V +1.5V

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

R602

10K_0402_5%

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

12

VTT1

205

G1

CONN@

VREF_CA

+0.75VS

DQS#0

VSS10

VSS17

VSS19

VSS21

VDD10

VDD12

VDD14

VDD16

VDD18

VSS28

VSS30 VSS31

VSS33

VSS35

DQS#5

VSS38

VSS40

VSS42 VSS43

VSS45

VSS47

DQS#7

VSS50

VSS52

EVENT#

DQ4 DQ5

VSS3

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

DM1

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3 DQ30

DQ31

CKE1

VDD2

VDD4

VDD6

VDD8

CK1

CK1#

RAS#

ODT0 ODT1

NC2

DQ36 DQ37

DM4

DQ38 DQ39

DQ44 DQ45

DQS5 DQ46

DQ47 DQ52

DQ53

DM6

DQ54 DQ55

DQ60 DQ61

DQS7 DQ62

DQ63

SDA SCL

VTT2

A15 A14

A11

A7 A6

A4 A2

A0

BA1

S0#

G2

DIMM0 REV H:5.2mm (BOT)

5

4

2

DDR_A_D4

4

DDR_A_D5

6 8

DDR_A_DQS#0

10

DDR_A_DQS0

12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26

DDR_A_DM1

28

SM_DRAMRST#

30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44

DDR_A_DM2

46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60

DDR_A_DQS#3

62

DDR_A_DQS3

64 66

DDR_A_D30

68

DDR_A_D31

70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDRA_CKE1

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2

DDR_A_MA0 DDRA_CLK1

DDRA_CLK1# DDR_A_BS1

DDR_A_RAS# DDRA_SCS0#

DDRA_ODT0 DDRA_ODT1

DDR_VREF_CA_DIMMA DDR_A_D36

DDR_A_D37 DDR_A_DM4 DDR_A_D38

DDR_A_D39 DDR_A_D44

DDR_A_D45 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D46

DDR_A_D47 DDR_A_D52

DDR_A_D53 DDR_A_DM6 DDR_A_D54

DDR_A_D55 DDR_A_D60

DDR_A_D61 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63 PM_EXTTS#0

D_CK_SDATA D_CK_SCLK

4

+0.75VS

SM_DRAMRST# <8,15>

DDRA_CKE1 <8>

DDRA_CLK1 <8> DDRA_CLK1# <8>

DDR_A_BS1 <9> DDR_A_RAS# <9>

DDRA_SCS0# <8>

DDRA_ODT1 <8>

1 2

R600 0_0402_5%R600 0_0402_5%

PM_EXTTS#0 <8>

D_CK_SDATA <15,16> D_CK_SCLK <15,16>

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z 1

C905

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+DIMM_VREF

1

C906

2

3

Layout Note: Place near JDIMM2

+1.5V

10U_0603_6.3V6M

1

C889

C890

2

Layout Note: Place near JDIMM2.203 & JDIMM2.204

+0.75VS

C9001U_0603_10V4Z C9001U_0603_10V4Z

Compal Secret Data

2009/07/01 2010/07/01

3

Compal Secret Data

Deciphered Date

2

DDR_A_DQS#[0..7]<9>

DDR_A_D[0..63]<9>

DDR_A_DM[0..7]<9> DDR_A_DQS[0..7]<9> DDR_A_MA[0..14]<9>

+DIMM_VREF<8,15>

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

0.1U_0402_16V4Z

10U_0603_6.3V6M

1

C892

C893

C891

2

1

C9011U_0603_10V4Z C9011U_0603_10V4Z

C893

2

1

C9031U_0603_10V4Z C9031U_0603_10V4Z

C9021U_0603_10V4Z C9021U_0603_10V4Z

2

10U_0603_6.3V6M

1

C894

2

10U_0805_6.3V6M

1

2

C904

0.1U_0402_16V4Z

C895

1

2

Title

Size Document Number Rev

B

401817

Date: Sheet

+DIMM_VREF

C887

0.1U_0402_16V4Z

C896

1

2

Compal Electronics, Inc.

1

+1.5V

12

R598

C888

1

2

C898

1

2

R598

12

R599

R599 1K_0402_1%

1K_0402_1%

1

+

C899

C899 330U_D2E_2.5VM_R7

330U_D2E_2.5VM_R7

2

1

+DIMM_VREF

14 53Monday, September 28, 2009

of

1K_0402_1%

2.2U_0805_16V4Z

1

2

0.1U_0402_16V4Z

C897

SCHEMATIC,MB A4853

A

+1.5V +1.5V

+DIMM_VREF

JDIMM1

+DIMM_VREF<8,14>

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1 1

2 2

3 3

4 4

+3VS

1

C909

2

DDR_B_BS2<9>

DDRB_CLK0<8> DDRB_CLK0#<8>

DDR_B_BS0<9>

DDR_B_WE#<9>

DDR_B_CAS#<9>

DDRB_SCS1#<8>

C929

C910

DDR_B_D0 DDR_B_D1

DDR_B_DM0 DDR_B_D2

DDR_B_D3 DDR_B_D8

DDR_B_D9 DDR_B_DQS#1

DDR_B_DQS1 DDR_B_D10

DDR_B_D11 DDR_B_D16

DDR_B_D17 DDR_B_DQS#2

DDR_B_DQS2

DDR_B_D19 DDR_B_D24

DDR_B_D25 DDR_B_DM3 DDR_B_D26

DDR_B_D27

DDRB_CKE0

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3

DDR_B_MA1 DDRB_CLK0

DDRB_CLK0# DDR_B_MA10

DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDR_B_MA13

DDRB_SCS1#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49 DDR_B_DQS#6

DDR_B_DQS6 DDR_B_D50

DDR_B_D51 DDR_B_D56

DDR_B_D57 DDR_B_DM7 DDR_B_D58

DDR_B_D59

R604

1 2

10K_0402_5%

1 2

1

R605

10K_0402_5%

C930

2

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z

JDIMM1

3 5 7

9 11 13 15 17 19 21 23 25 27

31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

63 65 67 69 71

73 75 77 79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

CONN@

DIMM1 REV H:9.2mm (BOT)

A

B

VREF_DQ1VSS1 VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS23 DQ26 DQ27 VSS25

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

G1

+0.75VS

VSS3

DQS#0

DQS0 VSS6

VSS8 DQ12 DQ13

VSS10

DM1

VSS12

DQ14 DQ15

VSS14

DQ20 DQ21

VSS16

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

VSS24

DQ30 DQ31

VSS26

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

VTT2

B

DQ4 DQ5

DQ6 DQ7

A15 A14

A11

CK1

BA1

S0#

SCL

C

2

DDR_B_D4

4

DDR_B_D5

6 8

DDR_B_DQS#0

10

DDR_B_DQS0

12 14

DDR_B_D6

16

DDR_B_D7

18 20

DDR_B_D12

22

DDR_B_D13

24 26

DDR_B_DM1

28

SM_DRAMRST#

30 32

DDR_B_D14

34

DDR_B_D15

36 38

DDR_B_D20

40

DDR_B_D21

42 44

DDR_B_DM2

46 48

DDR_B_D22

50

DDR_B_D23DDR_B_D18

52 54

DDR_B_D28

56

DDR_B_D29

58 60

DDR_B_DQS#3

62

DDR_B_DQS3

64 66

DDR_B_D30

68

DDR_B_D31

70 72

DDRB_CKE1

74 76 78

DDR_B_MA14

80 82

DDR_B_MA11

84

DDR_B_MA7

86

A7

88

DDR_B_MA6

90

A6 A4

A2 A0

G2

92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_B_MA4 DDR_B_MA2

DDR_B_MA0 DDRB_CLK1

DDRB_CLK1# DDR_B_BS1

DDR_B_RAS# DDRB_SCS0#

DDRB_ODT0 DDRB_ODT1

DDR_VREF_CA_DIMMB

DDR_B_D36 DDR_B_D37

DDR_B_DM4 DDR_B_D38

DDR_B_D39 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D47 DDR_B_D52

DDR_B_D53 DDR_B_DM6 DDR_B_D54

DDR_B_D55 DDR_B_D60

DDR_B_D61 DDR_B_DQS#7

DDR_B_DQS7 DDR_B_D62

DDR_B_D63 PM_EXTTS#1

D_CK_SDATA D_CK_SCLK

+0.75VS

SM_DRAMRST# <8,14>

DDRB_CKE1 <8>DDRB_CKE0<8>

DDRB_CLK1 <8> DDRB_CLK1# <8>

DDR_B_BS1 <9> DDR_B_RAS# <9>

DDRB_SCS0# <8> DDRB_ODT0 <8>

DDRB_ODT1 <8>

R603

0_0402_5%

1 2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z 1

2

PM_EXTTS#1 <8>

D_CK_SDATA <14,16> D_CK_SCLK <14,16>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C927

+DIMM_VREF

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1

C928

2

2009/07/01 2010/07/01

C

Layout Note: Place near JDIMM1

+1.5V

10U_0603_6.3V6M

10U_0805_6.3V6M

10U_0603_6.3V6M

1

C911

2

Layout Note: Place near JDIMM1.203 & JDIMM1.204

+0.75VS

1U_0603_10V4Z

2

1

Compal Secret Data

1

C912

2

1U_0603_10V4Z

2

C922

1

Deciphered Date

C913

C923

1

2

1U_0603_10V4Z

2

C924

1

D

DDR_B_DQS#[0..7]<9>

DDR_B_D[0..63]<9>

DDR_B_DM[0..7]<9>

DDR_B_DQS[0..7]<9>

DDR_B_MA[0..14]<9>

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

0.1U_0402_16V4Z

10U_0603_6.3V6M

1

C914

C915

2

1U_0603_10V4Z

1

2

C926

C925

2

1

D

10U_0603_6.3V6M

1

C916

2

10U_0805_6.3V6M

C918

C917

1

2

Title

Size Document Number Rev

B

Date: Sheet

0.1U_0402_16V4Z

10U_0603_6.3V6M

0.1U_0402_16V4Z

C919

C920

1

2

Compal Electronics, Inc.

401817

E

1

+

C921

@+C921

@

330U_D2E_2.5VM_R7

2

SCHEMATIC,MB A4853

of

15 53Monday, September 28, 2009

E

A

FSLC FSLB FSLA CPU

CLKSEL2 CLKSEL1 CLKSEL0

MHz

0 0 0 266 100 33.3

0

10

1 1

01

CLK_REQ#

200 100 33.3

1

Table : ICS9LPRS387

Control

CR#_10(WLAN) PCIEX10 PCIEX0 CR#_6(MCH) CR#_4(NEW CARD) CR#_9(MINI CARDII)

SRC7(VGA_CLK): Discrete VGA[Enable]

+3VS

1 2

R306 10K_0402_5%R306 10K_0402_5%

CLK_PCI2=1, Trusted Mode Enable(No overclocking allowed)

1 2

R593 10K_0402_5%R593 10K_0402_5%

1 2

R312 10K_0402_5%@R312 10K_0402_5%@

1 2

2 2

R310 10K_0402_5%R310 10K_0402_5%

CLK_PCI5=0, Pin63,64 is SRC_CLK CLK_PCI5=1, Pin63,64 is ITP_CLK

1 2

R308 10K_0402_5%@R308 10K_0402_5%@

CLK_PCI4=0, Pin28, 29 is SRC_CLK Pin24, 25 is DOT96_CLK

1 2

R292 10K_0402_5%@R292 10K_0402_5%@

C345 10P_0402_50V8J@C345 10P_0402_50V8J@

1 2

C346 10P_0402_50V8J@C346 10P_0402_50V8J@

1 2

PCIEX6 PCIEX4 PCIEX9

CLK_PCI2

CLK_PCI4

mount to Enable ITP_CLK

CLK_PCI5

CLK_PCI4

CK_PWRGD

For EMI 10/9

+1.05VS

R327

56_0402_5%@

R326

3 3

4 4

CLKSEL0

CLKSEL1

CLKSEL2

R326

2.2K_0402_5%

1 2

R328

R328 1K_0402_5%@

1K_0402_5%@

1 2

R379

R379 0_0402_5%@

0_0402_5%@

R388

R388 10K_0402_5%

10K_0402_5%

1 2

R390

R390 0_0402_5%@

0_0402_5%@

A

+1.05VS

1 2

R314

R314 0_0402_5%

0_0402_5%

R384

1K_0402_5%@

1K_0402_5%@ R383

R383 1K_0402_5%

1K_0402_5%

1 2

R380

R380 0_0402_5%

0_0402_5%

R389

1K_0402_5%@

1K_0402_5%@ R392

R392 1K_0402_5%

1K_0402_5%

1 2

R391

R391 0_0402_5%

0_0402_5%

R313

R313 1K_0402_5%

1K_0402_5%

1 2

B

SRC

PCI

MHz

33.3100166

Free-Run

PCIEX1

CLK_PCI4=1, Pin28, 29 is 27MHz Pin24, 25 is SRC_CLK

CLK_PCI_LPC CLK_PCI_ICH

MCH_CLKSEL0 <8>

CPU_BSEL0 <5>

MCH_CLKSEL1 <8>

CPU_BSEL1 <5>

MCH_CLKSEL2 <8>

CPU_BSEL2 <5>

B

CLK_PCI_LPC<35>

CLK_PCI_ICH<25>

CLK_ICH_48M<27> CLK_SD_48M<30>

+1.05VS

CLK_ICH_14M<27>

ICH_SMBDATA<27,33>

ICH_SMBCLK<27,33>

C

L15

FBMA-L11-201209-221LMA30T_0805

1

C347

C347 10U_0805_10V4Z

10U_0805_10V4Z

2

+3VS

R301

R301 10K_0402_5%

10K_0402_5% @

@

1 2

CK505_PWRGD

13

D

2

G

Q28

S

2N7002_SOT23

2N7002_SOT23 @

@

CLK_PCI_LPC CLK_PCI3

CLK_PCI_ICH CLK_PCI5

CK_PWRGD<27>

VGATE<8,27,47>

C354

1 2

27P_0402_50V8J

C353

27P_0402_50V8J

1 2

CLK_ICH_48M CLK_SD_48M

C

+CLK_VDDSRC

12

1

C358

C358 10U_0805_10V4Z

10U_0805_10V4Z

2

CLK_ENABLE# <47>

H_STP_CPU#<27>

H_STP_PCI#<27>

R307 33_0402_5%R307 33_0402_5%

R309 33_0402_5%R309 33_0402_5%

12

Y2

14.31818MHz_20P_FSX8L14.318181M20FDB

R325 22_0402_5%R325 22_0402_5% R311 22_0402_5%R311 22_0402_5%

R304 33_0402_5%R304 33_0402_5%

+3VS

R305

4.7K_0402_5%

2

G

1 2

+3VS

2

S

Q22

Q22 2N7002_SOT23

2N7002_SOT23

R293

4.7K_0402_5%

G

1 2

S

Q23

Q23 2N7002_SOT23

2N7002_SOT23

D_CK_SDATA

D_CK_SCLK

1 3

D

1 3

D

C371

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

+CLK_VDDSRC

12

R3030_0402_5% R3030_0402_5%

12

R3020_0402_5% @ R3020_0402_5% @

12

12 12

12

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

1

C387

2

0.1U_0402_16V4Z

+CLK_VDD

H_STP_CPU# H_STP_PCI#

CLK_PCI2

CLK_PCI4

CK505_PWRGD

CLK_XTALIN CLK_XTALOUT

CLKSEL0 CLKSEL1 CLKSEL2CLK_ICH_14M

D

E

L16

1

C370

0.1U_0402_16V4Z

2

U16

6 19 72 12 27 55

52 38 62 31 66 23

53 54

13 14 15 16 17

1

5

4

11

20

2

7

8

69

3 18 22 30 26 34 59 42

73

ICS9LPRS387BKLFT_MLF72_10x10

2009/07/01 2010/07/01

1

C380

C381

0.1U_0402_16V4Z

2

VDDREF VDD48 VDDCPU VDDPCI VDDPLL3 VDDSRC

VDDSRC_IO VDDSRC_IO VDDSRC_IO VDDPLL3_IO VDDCPU_IO VDD96_IO

CPU_STOP# PCI_STOP#

PCI1 PCI2/TME PCI3 PCI4/27_SELECT PCI_F5/ITP_EN

CK_PWRGD/PD#

X1 X2

NC

USB_48MHz/FSLA FSLB/TEST_MODE FSLC/TEST_SEL/REF0 REF1

GNDCPU GNDREF GNDPCI GND48 GND GND GNDSRC GNDSRC GNDSRC

GND_THERMAL_PAD

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

ICS9LPRS387, PN:SA000020H10 SLG8SP556V, PN:SA000020K00

E

+3VS

1

C386

2

Compal Secret Data

Deciphered Date

L16

FBMA-L11-201209-221LMA30T_0805

1

C390

C390 10U_0805_10V4Z

10U_0805_10V4Z

2

SRCT0_LPR/DOTT_96_LPR

SRCC0_LPR/DOTC_96_LPR

27MHz_NonSS/SRCT1_LPR/SE1

27MHz_SS/SRCC1_LPR/SE2

SRCT2_LPR/SATAT_LPR

SRCC2_LPR/SATAC_LPR

CPUT2_ITP_LPR/SRCT8_LPR

CPUC2_ITP_LPR/SRCC8_LPR

SDATA

SCLK

CPUT0_LPR_F

CPUC0_LPR_F

CPUT1_LPR_F

CPUC1_LPR_F

SRCT3_LPR SRCC3_LPR

SRCT4_LPR SRCC4_LPR

SRCT6_LPR SRCC6_LPR

SRCT7_LPR SRCC7_LPR

SRCT9_LPR SRCC9_LPR

SRCT10_LPR SRCC10_LPR

SRCT11_LPR SRCC11_LPR

CR#3 CR#4 CR#6 CR7#

CR#9 CR10# CR#11

CR#A

F

12

9 10

71 70

68 67

24 25

28 29

32 33

35 36

39 40

57 56

61 60

64 63

44 45

50 51

48 47

37 41 58 65 43 49 46 21

G

+CLK_VDD

1

C384

0.1U_0402_16V4Z

2

10U_0805_10V4Z

D_CK_SDATA D_CK_SCLK

CLK_CPU_BCLK CLK_CPU_BCLK#

CLK_MCH_BCLK CLK_MCH_BCLK#

CLK_DREF_96M CLK_DREF_96M#

CLK_PCIE_SATA CLK_PCIE_SATA#

CLK_PCIE_ICH CLK_PCIE_ICH#

1

C356

C357

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

VGA: disable this pair by BIOS

R576

R576 R577

R577

Remove New Card CLK For HM51

CLK_MCH_3GPLL CLK_MCH_3GPLL#

CLK_PCIE_VGA CLK_PCIE_VGA#

CLK_PCIE_MINI2 CLK_PCIE_MINI2#

CLK_PCIE_LAN CLK_PCIE_LAN#

(Pull High to +3VS at GMCH side)

R583 0_0402_5%@R583 0_0402_5%@

1 2 1 2

R336 10K_0402_5%R336 10K_0402_5%

1 2

R364 10K_0402_5%R364 10K_0402_5%

(Pull High to +3VS at ICH side)

Title

Size Document Number Rev

Custom

401817

Date: Sheet

G

H

Clock Generator

1

C355

C352

0.1U_0402_16V4Z

2

D_CK_SDATA <14,15>

D_CK_SCLK <14,15>

CLK_CPU_BCLK <4> CLK_CPU_BCLK# <4>

CLK_MCH_BCLK <7> CLK_MCH_BCLK# <7>

CLK_DREF_96M <8> CLK_DREF_96M# <8>

CLK_PCIE_SATA <26> CLK_PCIE_SATA# <26>

CLK_PCIE_ICH <27> CLK_PCIE_ICH# <27>

CLK_MCH_3GPLL <8> CLK_MCH_3GPLL# <8>

CLK_PCIE_VGA <17> CLK_PCIE_VGA# <17>

CLK_PCIE_MINI2 <33> CLK_PCIE_MINI2# <33>

CLK_PCIE_LAN <31> CLK_PCIE_LAN# <31>

Compal Electronics, Inc.

SCHEMATIC,MB A4853

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

CLK_DREF_SSC

12

0_0402_5%@

CLK_DREF_SSC#

12

0_0402_5%@

MCH_CLKREQ# <8> CLKREQB <18>

+3VS

MINI2_CLKREQ# <33>

+3VS

LAN_CLKREQ# <31> SATA_CLKREQ# <27>

C372

2

0.1U_0402_16V4Z

For M92

1

C385

2

27M_NSSC <18> CLK_DREF_SSC <8> 27M_SSC <18> CLK_DREF_SSC# <8>

For M92

16 53Monday, September 28, 2009

H

A

of

5

4

3

2

1

PCIE_GTX_C_MRX_P[0..15]<10> PCIE_GTX_C_MRX_N[0..15]<10> PCIE_MTX_C_GRX_P[0..15]<10> PCIE_MTX_C_GRX_N[0..15]<10>

D D

U30A

PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_N0

PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_N1

PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_N2

PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_N3

PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_N4

PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_N5

C C

B B

CLK_PCIE_VGA<16> CLK_PCIE_VGA#<16>

R578

PLT_RST#<8,25,31,35>

PLTRST_VGA#<25>

12

0_0402_5%

ESD

PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_N6

PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_N7

PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N8

PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_N9

PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_N10

PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11

PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_N12

PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N13

PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_N14

PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N15

CLK_PCIE_VGA CLK_PCIE_VGA#

For Future ASIC Pin N10 need pull down

10K_0402_5%@

R468

12

C627 10P_0402_50V8J@C627 10P_0402_50V8J@

AF30

PCIE_RX0P

AE31

PCIE_RX0N

AE29

PCIE_RX1P

AD28

PCIE_RX1N

AD30

PCIE_RX2P

AC31

PCIE_RX2N

AC29

PCIE_RX3P

AB28

PCIE_RX3N

AB30

PCIE_RX4P

AA31

PCIE_RX4N

AA29

PCIE_RX5P

Y28

PCIE_RX5N

Y30

PCIE_RX6P

W31

PCIE_RX6N

W29

PCIE_RX7P

V28

PCIE_RX7N

V30

PCIE_RX8P

U31

PCIE_RX8N

U29

PCIE_RX9P

T28

PCIE_RX9N

T30

PCIE_RX10P

R31

PCIE_RX10N

R29

PCIE_RX11P

P28

PCIE_RX11N

P30

PCIE_RX12P

N31

PCIE_RX12N

N29

PCIE_RX13P

M28

PCIE_RX13N

M30

PCIE_RX14P

L31

PCIE_RX14N

L29

PCIE_RX15P

K30

PCIE_RX15N

CLOCK

AK30

PCIE_REFCLKP

AK32

PCIE_REFCLKN

L9

NC#1

N9

NC#2

N10

12

NC_PWRGOOD

AL27

PERSTB

216-0728018 A12 M92-S2 XT FCBGA 0FA

PCIE_GTX_C_MRX_P[0..15] PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_P[0..15] PCIE_MTX_C_GRX_N[0..15]

AH30

PCIE_TX0P

AG31

PCIE_TX0N

AG29

PCIE_TX1P

AF28

PCIE_TX1N

AF27

PCIE_TX2P

AF26

PCIE_TX2N

AD27

PCIE_TX3P

AD26

PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P PCIE_TX10N

PCIE_TX11P PCIE_TX11N

PCIE_TX12P PCIE_TX12N

PCIE_TX13P PCIE_TX13N

PCIE_TX14P PCIE_TX14N

PCIE_TX15P PCIE_TX15N

AC25 AB25

Y23 Y24

AB27 AB26

PEG_NRX_C_GTX_P7 PCIE_GTX_C_MRX_P7

Y27 Y26

W24 W23

V27 U26

U24 U23

T26 T27

T24 T23

P27

PEG_NRX_C_GTX_N13 PCIE_GTX_C_MRX_N13

P26

PEG_NRX_C_GTX_P14 PCIE_GTX_C_MRX_P14

P24 P23

PEG_NRX_C_GTX_P15 PCIE_GTX_C_MRX_P15

M27

PEG_NRX_C_GTX_N15 PCIE_GTX_C_MRX_N15

N26

R467 1.27K_0402_1%R467 1.27K_0402_1%

Y22

1 2

R469 2K_0402_1%R469 2K_0402_1%

AA22

1 2

PCI EXPRESS INTERFACE

CALIBRATION

PCIE_CALRP PCIE_CALRN

C595 0.1U_0402_16V7KC595 0.1U_0402_16V7K

1 2

C596 0.1U_0402_16V7KC596 0.1U_0402_16V7K

1 2

C597 0.1U_0402_16V7KC597 0.1U_0402_16V7K

1 2

C598 0.1U_0402_16V7KC598 0.1U_0402_16V7K

1 2

C599 0.1U_0402_16V7KC599 0.1U_0402_16V7K

1 2

C600 0.1U_0402_16V7KC600 0.1U_0402_16V7K

1 2

C601 0.1U_0402_16V7KC601 0.1U_0402_16V7K

1 2

C602 0.1U_0402_16V7KC602 0.1U_0402_16V7K

1 2

C603 0.1U_0402_16V7KC603 0.1U_0402_16V7K

1 2

C604 0.1U_0402_16V7KC604 0.1U_0402_16V7K

1 2

C605 0.1U_0402_16V7KC605 0.1U_0402_16V7K

1 2

C606 0.1U_0402_16V7KC606 0.1U_0402_16V7K

1 2

C607 0.1U_0402_16V7KC607 0.1U_0402_16V7K

1 2

C608 0.1U_0402_16V7KC608 0.1U_0402_16V7K

1 2

C609 0.1U_0402_16V7KC609 0.1U_0402_16V7K

1 2

C610 0.1U_0402_16V7KC610 0.1U_0402_16V7K

1 2

C611 0.1U_0402_16V7KC611 0.1U_0402_16V7K

1 2

C612 0.1U_0402_16V7KC612 0.1U_0402_16V7K

1 2

C613 0.1U_0402_16V7KC613 0.1U_0402_16V7K

1 2

C614 0.1U_0402_16V7KC614 0.1U_0402_16V7K

1 2

C615 0.1U_0402_16V7KC615 0.1U_0402_16V7K

1 2

C616 0.1U_0402_16V7KC616 0.1U_0402_16V7K

1 2

C617 0.1U_0402_16V7KC617 0.1U_0402_16V7K

1 2

C618 0.1U_0402_16V7KC618 0.1U_0402_16V7K

1 2

C619 0.1U_0402_16V7KC619 0.1U_0402_16V7K

1 2

C620 0.1U_0402_16V7KC620 0.1U_0402_16V7K

1 2

C621 0.1U_0402_16V7KC621 0.1U_0402_16V7K

1 2

C622 0.1U_0402_16V7KC622 0.1U_0402_16V7K

1 2

C623 0.1U_0402_16V7KC623 0.1U_0402_16V7K

1 2

C624 0.1U_0402_16V7KC624 0.1U_0402_16V7K

1 2

C625 0.1U_0402_16V7KC625 0.1U_0402_16V7K

1 2

C626 0.1U_0402_16V7KC626 0.1U_0402_16V7K

1 2

+1.1VS

PCIE_GTX_C_MRX_P0PEG_NRX_C_GTX_P0 PCIE_GTX_C_MRX_N0PEG_NRX_C_GTX_N0

PCIE_GTX_C_MRX_P1PEG_NRX_C_GTX_P1 PCIE_GTX_C_MRX_N1PEG_NRX_C_GTX_N1

PCIE_GTX_C_MRX_P2PEG_NRX_C_GTX_P2 PCIE_GTX_C_MRX_N2PEG_NRX_C_GTX_N2

PCIE_GTX_C_MRX_P3PEG_NRX_C_GTX_P3 PCIE_GTX_C_MRX_N3PEG_NRX_C_GTX_N3

PCIE_GTX_C_MRX_P4PEG_NRX_C_GTX_P4 PCIE_GTX_C_MRX_N4PEG_NRX_C_GTX_N4

PCIE_GTX_C_MRX_P5PEG_NRX_C_GTX_P5 PCIE_GTX_C_MRX_N5PEG_NRX_C_GTX_N5

PCIE_GTX_C_MRX_P6PEG_NRX_C_GTX_P6 PCIE_GTX_C_MRX_N6PEG_NRX_C_GTX_N6

PCIE_GTX_C_MRX_N7PEG_NRX_C_GTX_N7

PCIE_GTX_C_MRX_P8PEG_NRX_C_GTX_P8 PCIE_GTX_C_MRX_N8PEG_NRX_C_GTX_N8

PCIE_GTX_C_MRX_P9PEG_NRX_C_GTX_P9 PCIE_GTX_C_MRX_N9PEG_NRX_C_GTX_N9

PCIE_GTX_C_MRX_P10PEG_NRX_C_GTX_P10 PCIE_GTX_C_MRX_N10PEG_NRX_C_GTX_N10

PCIE_GTX_C_MRX_P11PEG_NRX_C_GTX_P11 PCIE_GTX_C_MRX_N11PEG_NRX_C_GTX_N11

PCIE_GTX_C_MRX_P12PEG_NRX_C_GTX_P12 PCIE_GTX_C_MRX_N12PEG_NRX_C_GTX_N12

PCIE_GTX_C_MRX_P13PEG_NRX_C_GTX_P13

PCIE_GTX_C_MRX_N14PEG_NRX_C_GTX_N14

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/07/01 2010/07/01

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB A4853

401817

1

A

of

17 53Monday, September 28, 2009

of

17 53Monday, September 28, 2009

of

17 53Monday, September 28, 2009