Compal LA-4743P Schematics Rev0.1

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Auburndale rPGA989 with

3 3

4 4

A

Intel PCH(Ibex Peak-M) core logic

2009-04-13

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

Cu st om

D

Da te: Sheet o f

Compal Electronics, Inc.

Cover Sheet

Ca lpella DI S LA4743P

1 49Monday, April 13, 2009

E

0.1

A

B

C

D

E

Compal confidential

1 1

Nvidia
NB10M-GE

VRAM DDR3
128/512MB

page 28,29

2 2

Dis

HDMI Conn.

PCI-E BUS*4

Fan conn

page 24,25,26,27

Dis Dis(UMA)

Page 6

LCD Conn.

page 21

MUX

CRT

page 20

MUX

Dis(UMA)Dis

Level Shifter

page 23

page 23

Calpella Consumer 13.3" UMA +Switchable

32QFN

USB2.0 X12

P19

DDR3 SO-DIMM X2

BANK 0, 1, 2, 3

USB Card Reader

USB conn x3

BT Conn

USB Camera

Finger print

PCIE-Express 16X

UMA

UMA

UMA

Mobile Arrandale

2C CPU + GMCH

Socket-rPGA989

Page 6,7,8,9,10

DMI X4

Intel PCH

Ibex Peak-M
FCBGA 951

Page 11,12,13,14,15,16

CK505

Clock Generator
SLG8SP585VTR

DDR3 1066/1333 MHz 1.5V

Dual Channel

Azalia
SATA Master-1

SATA Slave

P17, 18

P33

P36

P36

P21

P36

Audio CKT

JMC261 (LAN
+Card reader)

3 3

Mini-Card

WLAN

P31

RJ45/11 CONN

P31

Mini-Card

WWAN

P32P32 P32

New Card

LPC BUS

SPI

SPI ROM 16M

P34

MX25L1605AM2C-15G

SATA HDD Connector

Codec_IDT92HD81

P34 P35

Audio Jack

P30

ENE

KB926

P38

SATA ODD Connector

P30

C

P37

Int.KBD

P38

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

D

USB Board Conn
USB conn x2

Capsense switch Conn

Title

Size Do cument Number Re v

Cu st om

Da te: Sheet o f

Compal Electronics, Inc.

Block Diagram

Ca lpella DI S LA4743P

E

2 49Monday, April 13, 2009

P33

P36

0.1

RTC CKT.

P21

LED

P36

ACCELEROMETER
ST

4 4

P27

Touch Pad CONN.

P39

SPI ROM
SST25VF080

K/B backlight Conn

P36

Security Classification

DC/DC Interface CKT.

A

P38

B

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

Symbol Note :

Voltage Rails

power
plane

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

1 1

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK
SML1DATA

KB926

KB926

PCH

PCH

PCH

O MEANS ON X MEANS OFF

+B

O
O
O
O
O

+5VALW

+3VALW

O
O
O
O

X
XX

XDP BATT

X V
X

V

X

Thermal
Sensor

X
X
X
X

X

X

X

+1.8V

O
O
O

X
X
X

SODIMM CLK CHIP

X
X

X

X

V V V

X

X

+5VS
+3VS
+1.5VS
+0.9V
+VCCP
+CPU_CORE
+2.5VS
+1.8VS

O
O

X
X
X
X

WLAN
WWAN

NB10M

NB10M-GE

Thermal
Sensor

X
X

X
X X
X

X

X

X

X
X

X

+3VALW +3VALW+3VS+3VS+3VS +3VS+5VL +5VL

45@ : means need be mounted when 45 level assy or rework stage.
BATT @ : means need be mounted when 45 level assy or rework stage.
CONN@ : means ME part

SG@ : means stuff when Switchable graphic

UMA@ : means stuff when UMA skus

VRAM@ : X76 level

8111DL@ : Only for Giga LAN
DEBUG@ : For debug
Cypress@ : Only For Cypress Capacitor sensor board

ENE@ : Only For ENE Capacitor sensor board

M3@ : Only For Intel DDR3 VREF

PA@ : Only For PA

PR@ : Only For PR

Cap sensor
board

V

X

X

X

X XXX X X X X X X

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build

NEW

G sensor

CARD

X X
X

X

V V

X

X

PCH I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

45172932L01：Switchable graphic
45172932L02：UMA only

USB assignment:

USB-0 Right side
USB-1 Right side
USB-2 Left side(with ESATA)
USB-3 X
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Finger Printer
USB-8 MiniCard(WWAN/TV)
USB-9 Express card
USB-10 X
USB-11 X

PCIe assignment:

PCIe-1 WWAN
PCIe-2 WLAN
PCIe-3 LAN
PCIe-4 New card
PCIe-5 X
PCIe-6 X

SATA assignment:

SATA0 HDD
SATA1 ODD
SATA2 X
SATA3 X
SATA4 ESATA
SATA5 X

HEX

A0

D2

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0

NB10M-GE SMBUS Control Table

D_EDID_DATA
D_EDID_CLK
D_CRT_DDC_DATA
D_CRT_DDC_DATA
HDMIDAT_VGA
HDMICLK_VGA

SOURCE LVDS CRT

NB10M

NB10M

NB10M

V

X
X

HDMI

X X

V

X

X

V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Re v

Cu stom

Da te: Sheet

Compal Electronics, Inc.

Notes List

Ca lpella DI S LA4743P

o f

3 49Monday, April 13, 2009

0.1

5

4

3

2

60mA

+3VAUX_BT

1

50mA

1A

D D

VIN

AC

C C

B+

7A

+V_BATTERY Dock con

0.3A

INVPWR_B+

2A

B++

LVDS CON

1.7A

+3VALW

+1.5VS

+5VALW

35mA

169mA

300mA

MDC 1.5

ICH9

LAN

3.39A5.89A

+3VS

RT5158

??mA

???A

1.3A0.58A

Mini card

New card

+5VS

35mA

10mA

25mA

20mA

10mA

1A

811mA

1.5A

250mA

1A

1A

+VDDA
IDT 9271B7

+5VAMP

Finger printer

+3VS_DVDD
ALC268

+3VALW_EC

SPI ROM

New card

PCH

+LCDVDD

LVDS CON

+3VS_CK505

Mini card (WLAN)

Mini card (TV tu/WWAN/Robeson)

1.8A

B B

3.7 X 3=11.1V

DC BATT

B+++

A A

CPU_B+ +VCC_CORE

5

11.05A1.9A

4.7A

+1.5V

1.05V_B+

+1.05VS PCH

10mA2A

4

38A/1.05V

3A

8 A

50mA

+VCCP

2.59A

CPU

CPU

DDR3 800Mhz 4G x2

+0.75V

162mA

??A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PCH

CPU

2007/08/28 2006/03/10

700mA

50mA

Compal Secret Data

Deciphered Date

ODD

SATA

PC Camera(4.75V)

2

Compal Electronics, Inc.

Title

Size Doc ume nt Number Re v

C

Calpella DIS LA4743P

Dat e: Sheet of

Power delevry

1

4 49Mon day , A pril 13, 200 9

0.1

A

1 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Re v

Cu stom

Da te: Sheet

Compal Electronics, Inc.

Notes List

Ca lpella DI S LA4743P

o f

5 49Monday, April 13, 2009

0.1

Layout rule 10m：il
width trace length <

0.5", spacing 20mil

D D

H_ P EC I<14 >

H_ P RO CH OT#<46 >

H_ THE RMT RIP#<14 >

H_ C PU R ST#

H_ P M_ SY NC<13 >

H_ C PU PW RGD

H_ C PU PW RGD<14>

PM _D R AM _P WRGD<13>

C C

From power

VT TP WR GO OD<44 >

BU F_ PL T_R ST#<14 >

5

R1 2 0_ 040 2_1%

1 2

R3 2 0_ 040 2_1%

1 2

R5 4 9.9_0 402_1%

1 2

R7 4 9.9_0 402_1%

1 2

TP _S KTOCC #

T1P AD

H_ C AT ER R#

R1 0

R1 5

R1 9

R2 0

R2 1

R2 3

R2 4

R2 5

R2 6

1.5K_040 2_1%

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

75 0_0 402_1%

H_ P EC I_ ISO

0_ 040 2_5%

H_ P RO C HOT #

H_ THE RM TRIP#_R

0_ 040 2_5%

H_ C PU RS T# _R

0_ 040 2_5%

H_ P M_ SY N C_R

0_ 040 2_5%

SY S_ A GE NT _PWRO K

0_ 040 2_5%

VC CPW RG O OD _0

0_ 040 2_5%

VD DPW RG O OD _R

0_ 040 2_5%

H_ P WR GD _ XDP_RH_ P WR GD _ XDP

0_ 040 2_5%

PL T_ RST #_R

12

R2 8

CO M P3
CO M P2
CO M P1
CO M P0

JC PU1 B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC , AU B_ CFD_ rPG A,R 1P0

C O NN @

MISC THERMAL

PWR MANAGEMENT

CLOCKS

DDR3

MISC

JTAG & BPM

4

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PM_EXT_TS#[0]
PM_EXT_TS#[1]

PRDY#
PREQ#

TRST#

TDI_M

TDO_M

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

TCK
TMS

TDO

3

CL K _C P U_B CLK

A16

CL K _C P U_B CLK #

B16

CL K _C PU _XD P

AR30

CL K _C PU _XD P#

AT30

CL K _EXP

E16

C LK_ EXP#

D16
A18

A17

F6
AL1

AM1
AN1

AN15
AP15

AT28
AP27

AN28
AP28
AT27

AT29

TDI

AR27
AR29
AP29

AN25

AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23

eDP

SM _R C OMP0
SM _R C OMP1
SM _R C OMP2

PM_ EXTTS#0
PM_ EXTTS#1

XD P_ P RDY#
XD P _PR EQ#

XD P_ TCK
X DP_TMS
XD P_ TRS T#

XD P _TD I_R
XD P _TD O_R
XD P_ TDI _M
XD P_ TDO _M

XD P_ D BR ESET#

X DP_BPM# 0
X DP_BPM# 1
X DP_BPM# 2
X DP_BPM# 3
X DP_BPM# 4
X DP_BPM# 5
X DP_BPM# 6
X DP_BPM# 7

R1 4 0_ 040 2_5%

DR AMR ST# <17 ,18 >

T63 P AD

1 2

PM_ EXTTS#0
PM_ EXTTS#1

CL K _C PU _BC LK <14 >
CL K _C PU _BC LK# <1 4>

CL K_E XP <12 >
CL K_E XP# <12 >

R2 7 10 K_0 402 _5%
R2 9 10 K_0 402 _5%

1 2
1 2

OK

PM_EXT TS#1 _R <17 ,18>

from DDR

+V CCP

H_ C PU PW RGD

PM _P W RB TN# _R<13>

H_ P WR GD _ XDP

+V CCP

1

C 1

@

0. 1U_04 02_16 V4Z

2

R1 3
1K_ 04 02_ 5%

1 2

R1 6 0_ 040 2_5%

1 2

XD P _PR EQ#
XD P_ P RDY#

X DP_BPM# 0
X DP_BPM# 1

X DP_BPM# 2
X DP_BPM# 3

X DP_BPM# 4
X DP_BPM# 5

X DP_BPM# 6
X DP_BPM# 7

H_ C PU PW RGD _R
PM _P W RB TN#_R

2

XDP Connector

JP 1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_B SH- 030 -01-L -D-A C O NN@

XD P _RS T#_ R

R2 2 0_040 2_5%@

1 2

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

GND17

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

TD0

54
56

TDI

58

TMS

60

CL K _C PU _XD P
CL K _C PU _XD P#

XD P _RS T#_ R
XD P_ D BR ESET#_R

XD P_ TDO
XD P_ TRS T#
XD P_ TDI
X DP_TMSXD P_ TCK

XD P_ D BR ESET#

PL T_RST# <1 4,3 1,3 2>

1

XD P_ TDI

R2 5 1_ 040 2_1%@

1 2

R4 5 1_ 040 2_1%@

X DP_TMS
XD P _PR EQ#
XD P_ TDO

This shall place near CPU

XD P_ TCK

1 2

R6 5 1_ 040 2_1%@

1 2

R8 5 1_ 040 2_1%

1 2

R9 5 1_ 040 2_1%@

1 2

+V CCP

R1 7
1K_ 04 02_ 5%

1 2

1 2

R1 8

0_ 040 2_5%

R6 03 1K_04 02_5%

1 2

H_ C PU R ST#

XD P_ D BRESET# <13>

+V CCP

+3 VS

JTAG MAPPING

+1 .5V

Fan Voltage Control circuit

SI-1 Change to voltage control circuit

+5 VS

+3 VS

1 2

1

2

U3 2

9

Thermal Pad

8

GND

7

GND

6

GND

5

GND

G9 9 6R D1U_TD FN8 _3X 3

FA N_ S ET<37 >

VEN

VSET

1
2

VIN

3

VO

4

R6 78

10 K_0 402 _5 %

FA N_ S PE ED< 37>

FA N_ S PE ED

C7 75

10 00P _04 02 _50 V7K

1

C 2

2. 2U_06 03_6. 3V4 Z

2

1

C7 74

2. 2U_06 03_6. 3V4 Z

2

+5 VS_ FAN

+5 VS

D1

3

Vcc

2

Line to be protected

1

GND

DLPT05 -7-F_SOT2 3-3

FA N_ S PE ED

1

C 3

0. 1U_04 02_16 V4Z

2

1
2
3

C O NN @

JF AN 1

1

4

2

G1

5

3

G2

ACE S_8 520 4- 030 01

XD P_ TDI _M

XD P _TD O_R

XD P_ TRS T#

R3 0 0_ 040 2_5%

1 2

R3 2 0_ 040 2_5%@

1 2

R3 4
0_ 040 2_5%

1 2

R3 7 0_ 040 2_5%@

1 2

R3 8 0_ 040 2_5%

1 2

R3 9 51 _04 02_1%

1 2

XD P_ TDI

XD P_ TDOXD P_ TDO _M

VD DPW RG O OD _R

R3 1 4.75K_04 02_1%
R3 3 12 K_0 402 _1%

CRB 0.9 R38 change to 1K

1 2
1 2

XD P _TD I_R

Processor Pullups

H_ C AT ER R#
H_ C PU RS T# _R

B B

H_ P RO C HOT #

R3 5 49.9_ 0402_ 1%

1 2

R3 6 68_04 02_5%@

1 2

R1 1 68_04 02_5%

+V CCP

12

DDR3 Compensation Signals

SM _R C OMP0

R4 0 100_0 402_1%

SM _R C OMP1
SM _R C OMP2

Layout Note:Please these
resistors near Processor

A A

1 2

R4 1 24.9_ 0402_ 1%

1 2

R4 2 130_0 402_1%

1 2

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Tit le

Size Do c um en t N umb er R e v

Cu s to m

Da te : She et o f

Compal Electronics, Inc.

Auburndale(1/5)-Thermal/XDP

Ca lp ella DIS L A4743P

1

6 49Mon day, Apr il 13, 20 09

0. 1

5

JC PU1A

DMI_CRX_PTX_N0<13>
DMI_CRX_PTX_N1<13>
DMI_CRX_PTX_N2<13>
DMI_CRX_PTX_N3<13>

DMI_CRX_PTX_P0<13>
DMI_CRX_PTX_P1<13>

D D

DMI_CRX_PTX_P2<13>
DMI_CRX_PTX_P3<13>

DMI_CTX_PRX_N0<13>
DMI_CTX_PRX_N1<13>
DMI_CTX_PRX_N2<13>
DMI_CTX_PRX_N3<13>

DMI_CTX_PRX_P0<13>
DMI_CTX_PRX_P1<13>
DMI_CTX_PRX_P2<13>
DMI_CTX_PRX_P3<13>

FDI_ CTX_PRX_N0<13>
FDI_ CTX_PRX_N1<13>
FDI_ CTX_PRX_N2<13>
FDI_ CTX_PRX_N3<13>
FDI_ CTX_PRX_N4<13>
FDI_ CTX_PRX_N5<13>
FDI_ CTX_PRX_N6<13>
FDI_ CTX_PRX_N7<13>

FDI_ CTX_PRX_P0<13>
FDI_ CTX_PRX_P1<13>
FDI_ CTX_PRX_P2<13>
FDI_ CTX_PRX_P3<13>
FDI_ CTX_PRX_P4<13>
FDI_ CTX_PRX_P5<13>

C C

FDI_ CTX_PRX_P6<13>
FDI_ CTX_PRX_P7<13>

FD I_ FS YNC0<13>
FD I_ FS YNC1<13>

FD I_INT<13>
FD I_ LS YNC0<13>

FD I_ LS YNC1<13>

B B

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,A UB_CFD_rPGA,R1P0

C ONN@

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS
PEG_RX#[0]

PEG_RX#[1]

PCI EXPRESS -- GRAPHICS

PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

DMI Intel(R) FDI

4

EXP_ICOMPI

B26
A26
B27

EXP_RBIAS

A25

PCIE _CRX _GT X_N0

K35

PCIE _CRX _GT X_N1

J34

PCIE _CRX _GT X_N2

J33

PCIE _CRX _GT X_N3

G35

PCIE _CRX _GT X_N4

G32

PCIE _CRX _GT X_N5

F34

PCIE _CRX _GT X_N6

F31

PCIE _CRX _GT X_N7

D35

PCIE _CRX _GT X_N8

E33

PCIE _CRX _GT X_N9

C33

PCIE _CRX _GT X_N10

D32

PCIE _CRX _GT X_N11

B32

PCIE _CRX _GT X_N12

C31

PCIE _CRX _GT X_N13

B28

PCIE _CRX _GT X_N14

B30

PCIE _CRX _GT X_N15

A31

PCIE _CRX _GTX_P0

J35

PCIE _CRX _GTX_P1

H34

PCIE _CRX _GTX_P2

H33

PCIE _CRX _GTX_P3

F35

PCIE _CRX _GTX_P4

G33

PCIE _CRX _GTX_P5

E34

PCIE _CRX _GTX_P6

F32

PCIE _CRX _GTX_P7

D34

PCIE _CRX _GTX_P8

F33

PCIE _CRX _GTX_P9

B33

PCIE _CRX _GTX_P10

D31

PCIE _CRX _GTX_P11

A32

PCIE _CRX _GTX_P12

C30

PCIE _CRX _GTX_P13

A28

PCIE _CRX _GTX_P14

B29

PCIE _CRX _GTX_P15

A30

PCIE _CTX_GRX_C_N0

L33

PCIE _CTX_GRX_C_N1

M35

PCIE _CTX_GRX_C_N2

M33

PCIE _CTX_GRX_C_N3

M30

PCIE _CTX_GRX_C_N4

L31

PCIE _CTX_GRX_C_N5

K32

PCIE _CTX_GRX_C_N6

M29

PCIE _CTX_GRX_C_N7

J31

PCIE _CTX_GRX_C_N8

K29

PCIE _CTX_GRX_C_N9

H30

PCIE _CTX_GRX_C_N10

H29

PCIE _CTX_GRX_C_N11

F29

PCIE _CTX_GRX_C_N12

E28

PCIE _CTX_GRX_C_N13

D29

PCIE _CTX_GRX_C_N14

D27

PCIE _CTX_GRX_C_N15

C26

PCIE _CTX_GRX_C_P0

L34

PCIE _CTX_GRX_C_P1

M34

PCIE _CTX_GRX_C_P2

M32

PCIE _CTX_GRX_C_P3

L30

PCIE _CTX_GRX_C_P4

M31

PCIE _CTX_GRX_C_P5

K31

PCIE _CTX_GRX_C_P6

M28

PCIE _CTX_GRX_C_P7

H31

PCIE _CTX_GRX_C_P8

K28

PCIE _CTX_GRX_C_P9

G30

PCIE _CTX_GRX_C_P10

G29

PCIE _CTX_GRX_C_P11

F28

PCIE _CTX_GRX_C_P12

E27

PCIE _CTX_GRX_C_P13

D28

PCIE _CTX_GRX_C_P14

C27

PCIE _CTX_GRX_C_P15

C25

R44 49.9_0402_1%

1 2

R45 750 _04 02_1%

1 2

PCIE _CRX _GT X_N[0..15] <24>

PCIE _CRX _GT X_P [0..15] <24>

C4 0.1U_040 2_16V4ZSG@

1 2

C5 0.1U_040 2_16V4ZSG@

1 2

C6 0.1U_040 2_16V4ZSG@

1 2

C7 0.1U_040 2_16V4ZSG@

1 2

C8 0.1U_040 2_16V4ZSG@

1 2

C9 0.1U_040 2_16V4ZSG@

1 2

C10 0.1U_04 02_16V4ZSG@

1 2

C11 0.1U_04 02_16V4ZSG@

1 2

C12 0.1U_04 02_16V4ZSG@

1 2

C13 0.1U_04 02_16V4ZSG@

1 2

C14 0.1U_04 02_16V4ZSG@

1 2

C15 0.1U_04 02_16V4ZSG@

1 2

C16 0.1U_04 02_16V4ZSG@

1 2

C17 0.1U_04 02_16V4ZSG@

1 2

C18 0.1U_04 02_16V4ZSG@

1 2

C19 0.1U_04 02_16V4ZSG@

1 2

C20 0.1U_04 02_16V4ZSG@

1 2

C21 0.1U_04 02_16V4ZSG@

1 2

C22 0.1U_04 02_16V4ZSG@

1 2

C23 0.1U_04 02_16V4ZSG@

1 2

C24 0.1U_04 02_16V4ZSG@

1 2

C25 0.1U_04 02_16V4ZSG@

1 2

C26 0.1U_04 02_16V4ZSG@

1 2

C27 0.1U_04 02_16V4ZSG@

1 2

C28 0.1U_04 02_16V4ZSG@

1 2

C29 0.1U_04 02_16V4ZSG@

1 2

C30 0.1U_04 02_16V4ZSG@

1 2

C31 0.1U_04 02_16V4ZSG@

1 2

C32 0.1U_04 02_16V4ZSG@

1 2

C33 0.1U_04 02_16V4ZSG@

1 2

C34 0.1U_04 02_16V4ZSG@

1 2

C35 0.1U_04 02_16V4ZSG@

1 2

3

Layout rule trace
length < 0.5"

PCIE _CTX_GRX_N0
PCIE _CTX_GRX_N1
PCIE _CTX_GRX_N2
PCIE _CTX_GRX_N3
PCIE _CTX_GRX_N4
PCIE _CTX_GRX_N5
PCIE _CTX_GRX_N6
PCIE _CTX_GRX_N7
PCIE _CTX_GRX_N8

PCIE _CTX_GRX_N9
PCIE _CTX_GRX_N10
PCIE _CTX_GRX_N11
PCIE _CTX_GRX_N12
PCIE _CTX_GRX_N13
PCIE _CTX_GRX_N14
PCIE _CTX_GRX_N15

PCIE _CTX_GRX_P0

PCIE _CTX_GRX_P1

PCIE _CTX_GRX_P2

PCIE _CTX_GRX_P3

PCIE _CTX_GRX_P4

PCIE _CTX_GRX_P5

PCIE _CTX_GRX_P6

PCIE _CTX_GRX_P7

PCIE _CTX_GRX_P8

PCIE _CTX_GRX_P9
PCIE _CTX_GRX_P10
PCIE _CTX_GRX_P11
PCIE _CTX_GRX_P12
PCIE _CTX_GRX_P13
PCIE _CTX_GRX_P14
PCIE _CTX_GRX_P15

：

+V _DDR_CPU_REF1

PCIE _CTX_GRX_N[0..15] <24>

PCIE _CTX_GRX_P [0..15] <24>

R50 0_0 402_5%@
R51 0_0 402_5%@

1 2
1 2

2

+V _DDR_CPU_REF0

CF G0
CF G1
CF G2
CF G3
CF G4
CF G5
CF G6
CF G7
CF G8
CF G9
CF G10
CF G11
CF G12
CF G13
CF G14
CF G15
CF G16
CF G17
CF G18

AP25
AL25
AL24
AL22
AJ33

AG9
M27

G25
G17

AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30

AC9

L28
J17
H17

E31
E30

H16

B19
A19

A20
B20

U9

T9

AB9

C1
A3

J29
J28

A34
A33

C35
B35

JC PU1E

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
SA_DIMM_VREF
SB_DIMM_VREF
RSVD11
RSVD12
RSVD13
RSVD14

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86

RSVD15
RSVD16

RSVD17
RSVD18

RSVD19
RSVD20

RSVD21
RSVD22

RSVD_NCTF_23
RSVD_NCTF_24

RSVD26
RSVD27

RSVD_NCTF_28
RSVD_NCTF_29

RSVD_NCTF_30
RSVD_NCTF_31

RESERVED

RSVD32
RSVD33

RSVD34
RSVD35

RSVD36

RSVD_NCTF_37

RSVD38
RSVD39

RSVD_NCTF_40
RSVD_NCTF_41

RSVD_NCTF_42
RSVD_NCTF_43

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52

RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57

RSVD58

RSVD_TP_59
RSVD_TP_60

KEY
RSVD62
RSVD63
RSVD64
RSVD65

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

VSS

AJ13
AJ12

AH25
AK26

AL26
AR2

AJ26
AJ27

AP1
AT2

AT3
AR1

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32

E15
F15
A2
D15
C15
AJ15
AH15

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

AP34

1

R48 0_0 402_5%@

1 2

R49 0_0 402_5%@

1 2

IC,A UB_CFD_rPGA,R1P0

C ONN@

CFG Straps for PROCESSOR

CF G0

R52 3.01K_0402_1%@

1 2

PCI-Express Configuration Select

1: Single PEG

CFG0

A A

No t ap pl ic able for Clarksfield Processor

CF G3

0: B if urcation enabled

R54 3.01K_0402_1%

1 2

CF G3 -P CI Express Static Lane Reversal

1: N ormal Operation

CFG3

0: L an e Numbers Reversed

15 - > 0, 14 ->1, .....

5

*

CF G4

R53 3.01K_0402_1%@

1 2

CF G4 -D isplay Port Presence

1: D is abled; No Physical
D isplay Port

at ta ch ed to Embedded Display Port
0: E na bled; An external

CFG4

D isplay Port
de vi ce is connected to the

Em be dded Display Port

CF G7

R55 3.01K_0402_1%@

Only temporary for early
CFD samples (rPGA/BGA)

Only for pre ES1 sample

1 2

4

**

CFG7

WW33 GPD 3.01K on CFG7 for PCIE Jitter
WW41 don't staff

：

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

Cu st om

2

Da te: Sheet o f

Compal Electronics, Inc.

Auburndale(2/5)-DMI/PEG/FDI

Ca lpella DI S LA4743P

CRB 0.9 change to GND

7 49Monday, April 13, 2009

1

0.1

5

4

3

2

1

AR10
AT10

AF3
AG1
AJ3
AK1
AG4
AG3
AJ4
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9

AB1

AC5
AC6

W5

B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
J6
J3
G1
G5
J2
J1
J5
K2
L3
M1
K5
K4
M4
N5

R7

Y7

JC PU 1D

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

W8

SB_CK[0]

W9

SB_CK#[0]

M3

SB_CKE[0]

V7

SB_CK[1]

V6

SB_CK#[1]

M2

SB_CKE[1]

AB8

SB_CS#[0]

AD6

SB_CS#[1]

AC7

SB_ODT[0]

AD1

SB_ODT[1]

DDR_B_DM0

D4

SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

E1
H3
K1
AH1
AL2
AR4
AT8

D5
F4
J4
L4
AH2
AL4
AR5
AR8

C5
E3
H4
M5
AG2
AL5
AP5
AR7

DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR SYSTEM MEMORY - B

DDR_B_ MA0

U5

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

DDR_B_ MA1
DDR_B_ MA2
DDR_B_ MA3
DDR_B_ MA4
DDR_B_ MA5
DDR_B_ MA6
DDR_B_ MA7
DDR_B_ MA8
DDR_B_ MA9
DDR_B_MA 10
DDR_B_MA 11
DDR_B_MA 12
DDR_B_MA 13
DDR_B_MA 14
DDR_B_MA 15

M_ CLK_DDR2 <18>
M_ CLK _DDR# 2 <18>
DDR_CKE2_DIMMB <18>

M_ CLK_DDR3 <18>
M_ CLK _DDR# 3 <18>
DDR_CKE3_DIMMB <18>

DDR_CS2_DIMMB# <18>
DDR_CS3_DIMMB# <18>

M_ODT2 <18>
M_ODT3 <18>

DDR_B_DM[0..7] <18>

DDR_B_DQS#[0..7 ] <18>

DDR_B_ DQS[0..7] <18>

DDR_B _MA[0..1 5] <18>

JC PU 1C

D D

DDR_A_D[0..63]<17>

C C

B B

DDR_A_BS0<17>
DDR_A_BS1<17>
DDR_A_BS2<17>

DDR_A_ CAS #<17>
DDR_A_ RAS #<17>
DDR_A _WE #<17>

DDR_ A_D0
DDR_ A_D1
DDR_ A_D2
DDR_ A_D3
DDR_ A_D4
DDR_ A_D5
DDR_ A_D6
DDR_ A_D7
DDR_ A_D8
DDR_ A_D9
DDR_A_D1 0
DDR_A_D1 1
DDR_A_D1 2
DDR_A_D1 3
DDR_A_D1 4
DDR_A_D1 5
DDR_A_D1 6
DDR_A_D1 7
DDR_A_D1 8
DDR_A_D1 9
DDR_A_D2 0
DDR_A_D2 1
DDR_A_D2 2
DDR_A_D2 3
DDR_A_D2 4
DDR_A_D2 5
DDR_A_D2 6
DDR_A_D2 7
DDR_A_D2 8
DDR_A_D2 9
DDR_A_D3 0
DDR_A_D3 1
DDR_A_D3 2
DDR_A_D3 3
DDR_A_D3 4
DDR_A_D3 5
DDR_A_D3 6
DDR_A_D3 7
DDR_A_D3 8
DDR_A_D3 9
DDR_A_D4 0
DDR_A_D4 1
DDR_A_D4 2
DDR_A_D4 3
DDR_A_D4 4
DDR_A_D4 5
DDR_A_D4 6
DDR_A_D4 7
DDR_A_D4 8
DDR_A_D4 9
DDR_A_D5 0
DDR_A_D5 1
DDR_A_D5 2
DDR_A_D5 3
DDR_A_D5 4
DDR_A_D5 5
DDR_A_D5 6
DDR_A_D5 7
DDR_A_D5 8
DDR_A_D5 9
DDR_A_D6 0
DDR_A_D6 1
DDR_A_D6 2
DDR_A_D6 3

AJ10
AL10

AK12

AK11

AM10

AR11
AL11

AT11
AP12

AM12

AN12

AM13

AT14
AT12
AL13
AR14
AP14

C10

D10

G10

AH5
AF5
AK6
AK7
AF6
AG5

AK8

AN8

AM9
AN9

AC3
AB2

AE1
AB3
AE9

A10

SA_DQ[0]
SA_DQ[1]

C7

SA_DQ[2]

A7

SA_DQ[3]

B10

SA_DQ[4]
SA_DQ[5]

E10

SA_DQ[6]

A8

SA_DQ[7]

D8

SA_DQ[8]

F10

SA_DQ[9]

E6

SA_DQ[10]

F7

SA_DQ[11]

E9

SA_DQ[12]

B7

SA_DQ[13]

E7

SA_DQ[14]

C6

SA_DQ[15]

H10

SA_DQ[16]

G8

SA_DQ[17]

K7

SA_DQ[18]

J8

SA_DQ[19]

G7

SA_DQ[20]
SA_DQ[21]

J7

SA_DQ[22]

J10

SA_DQ[23]

L7

SA_DQ[24]

M6

SA_DQ[25]

M8

SA_DQ[26]

L9

SA_DQ[27]

L6

SA_DQ[28]

K8

SA_DQ[29]

N8

SA_DQ[30]

P9

SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]

AJ7

SA_DQ[38]

AJ6

SA_DQ[39]
SA_DQ[40]

AJ9

SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]

AL7

SA_DQ[45]
SA_DQ[46]

AL8

SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]

U7

SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0]

SA_CK#[0]

SA_CKE[0]

SA_CK[1]

SA_CK#[1]

SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AA6
AA7
P7

Y6
Y5
P6

AE2
AE8

AD8
AF9

B9
D7
H7
M7
AG6
AM7
AN10
AN13

C9
F8
J9
N9
AH7
AK9
AP11
AT13

C8
F9
H9
M9
AH8
AK10
AN11
AR13

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_ MA0
DDR_A_ MA1
DDR_A_ MA2
DDR_A_ MA3
DDR_A_ MA4
DDR_A_ MA5
DDR_A_ MA6
DDR_A_ MA7
DDR_A_ MA8
DDR_A_ MA9
DDR_A_MA 10
DDR_A_MA 11
DDR_A_MA 12
DDR_A_MA 13
DDR_A_MA 14
DDR_A_MA 15

M_ CLK _DDR0 <17>
M_CLK_ DDR#0 <17>
DDR_CKE0_DIMMA <17>

M_ CLK _DDR1 <17>
M_CLK_ DDR#1 <17>
DDR_CKE1_DIMMA <17>

DDR_CS0_DIMMA# <17>
DDR_CS1_DIMMA# <17>

M_ODT0 <17>
M_ODT1 <17>

DDR_A_DM[0..7] <17>

DDR_A_DQS#[0..7] <17>

DDR_A_DQS[0 ..7] <17>

DDR_A_ MA[0..15] <17>

DDR_B_D[0..63]<18>

DDR_B_BS0<18>
DDR_B_BS1<18>
DDR_B_BS2<18>

DDR_B_ CAS #<18>
DDR_B_ RAS #<18>
DDR_B _WE #<18>

DDR_ B_D0
DDR_ B_D1
DDR_ B_D2
DDR_ B_D3
DDR_ B_D4
DDR_ B_D5
DDR_ B_D6
DDR_ B_D7
DDR_ B_D8
DDR_ B_D9
DDR_B_D1 0
DDR_B_D1 1
DDR_B_D1 2
DDR_B_D1 3
DDR_B_D1 4
DDR_B_D1 5
DDR_B_D1 6
DDR_B_D1 7
DDR_B_D1 8
DDR_B_D1 9
DDR_B_D2 0
DDR_B_D2 1
DDR_B_D2 2
DDR_B_D2 3
DDR_B_D2 4
DDR_B_D2 5
DDR_B_D2 6
DDR_B_D2 7
DDR_B_D2 8
DDR_B_D2 9
DDR_B_D3 0
DDR_B_D3 1
DDR_B_D3 2
DDR_B_D3 3
DDR_B_D3 4
DDR_B_D3 5
DDR_B_D3 6
DDR_B_D3 7
DDR_B_D3 8
DDR_B_D3 9
DDR_B_D4 0
DDR_B_D4 1
DDR_B_D4 2
DDR_B_D4 3
DDR_B_D4 4
DDR_B_D4 5
DDR_B_D4 6
DDR_B_D4 7
DDR_B_D4 8
DDR_B_D4 9
DDR_B_D5 0
DDR_B_D5 1
DDR_B_D5 2
DDR_B_D5 3
DDR_B_D5 4
DDR_B_D5 5
DDR_B_D5 6
DDR_B_D5 7
DDR_B_D5 8
DDR_B_D5 9
DDR_B_D6 0
DDR_B_D6 1
DDR_B_D6 2
DDR_B_D6 3

IC,A UB_CFD_rPGA,R1P0

C ONN@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

IC,A UB_CFD_rPGA,R1P0

C ONN@

Deciphered Date

Title

Size Do cument Number Re v

Cu st om

2

Da te: Sheet o f

Compal Electronics, Inc.

Cantiga(2/6)-DDR3 A/B CH

Ca lpella DI S LA4743P

1

8 49Monday, April 13, 2009

0.1

5

+V CC _CORE

JC PU1F

D D

C C

B B

A A

48A 15A18A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

IC,A UB_CFD_rPGA,R1P0

C ONN@

CPU CORE SUPPLY

5

POWER

CPU VIDS

SENSE LINES

1.1V RAIL POWER

PROC_DPRSLPVR

VSS_SENSE_VTT

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8

VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32

VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

PSI#

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VTT_SELECT

ISENSE

VCC_SENSE

VSS_SENSE

VTT_SENSE

AH14
AH12
AH11
AH10

1
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

AN33

AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

G15

C40

2

10U_0805_6 .3V6M

1

C48

2

10U_0805_6 .3V6M

1

C67

2

+VTT_43
+VTT_44

H_ VID0
H_ VID1
H_ VID2
H_ VID3
H_ VID4
H_ VID5
H_ VID6
PM_ DPRS LPV R_R

H_VTTVID1 = Low, 1.1V(Clarksfield)
H_VTTVID1 = High, 1.05V(Auburndale)

AN35

VC CSENSE_R

AJ34

VSSSE NSE_R

AJ35

B15

VSS_SENSE_VTT

A15

Near Processor

V CCSE NSE
VSSSE NSE

R61 100 _0402_1%
R62 100 _0402_1%

4

1

C41

2

10U_0805_6 .3V6M

1

C49

2

@

10U_0805_6 .3V6M

1

2

22U_0805_6.3V6M

+VTT_44
+VTT_43

to power

R58 0_0 402_5%

to power

R5 9 0_0 402_5%

1 2

R6 0 0_0 402_5%

1 2

R203 0_0 402_5%

1 2
1 2

1

1

C42

2

2

10U_0805_6 .3V6M

1

1

C50

2

2

@

10U_0805_6 .3V6M

+V CCP

C68

22U_0805_6.3V6M

R56 0_0 603_5%

1 2

R57 0_0 603_5%

1 2

H_PSI# <46>
H_ VI D[0..6] <46>

to power

1 2

VTT_SELECT <44>

IMVP_IMON <46>

1 2

+V CC_ CORE

4

C43

C51

10U_0805_6 .3V6M

10U_0805_6 .3V6M

+V CCP

1

2

1

2

C52

10U_0805_6 .3V6M

C61

22U_0805_6 .3V6M

V CCSE NSE
VSSSE NSE

+V CCP

1

C62

2

22U_0805_6 .3V6M

+VCCP

H_ DPRS LPVR <46>

to power

VTT_SENSE <44>

3

+VGA_CORE

22U_0805_6.3V6M

22U_0805_6.3V6M

C988

C987

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C993

C991

1

1

@

@

2

330 U_D2_2V Y_R7M

C995

1

1

+

+

1

2

2

2

C63

22U_0805_6 .3V6M

+V CCP

1

2

@

2

330 U_D2_2V Y_R7M

C996

+V CCP

1

C74

C73

2

22U_0805_6 .3V6M

22U_0805_6 .3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

C989

1

1

2

2

22U_0805_6.3V6M

C994

1

2

1

1

C6 9

2

2

22U_0805_6.3V6M

1

1

C75

2

2

22U_0805_6 .3V6M

CPU

VCCSENSE <46>
VSSSENSE <46>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

AT21
AT19
AT18

C990

AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18

AN16
AM21
AM19
AM18
AM16

AL21

AL19

AL18

AL16
AK21
AK19
AK18
AK16

AJ21

AJ19

AJ18

AJ16
AH21
AH19
AH18
AH16

J24
J23
H25

C7 0

22U_0805_6.3V6M

K26
J27
J26
J25

C76

H27
G28
G27
G26

22U_0805_6 .3V6M

F26

E26

E25

Compal Secret Data

JC PU1G

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36

VTT1_45
VTT1_46
VTT1_47

VTT1_48
VTT1_49
VTT1_50
VTT1_51
VTT1_52
VTT1_53
VTT1_54
VTT1_55
VTT1_56
VTT1_57
VTT1_58

IC,A UB_CFD_rPGA,R1P0

C ONN@

GRAPHICS

FDI PEG & DMI

Deciphered Date

POWER

2

VCC_ AXG_SENSE

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

GFX_VR_EN

GFX_IMON

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

VTT0_59
VTT0_60
VTT0_61
VTT0_62

VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68

VCCPLL1
VCCPLL2
VCCPLL3

AR22

VSS_AXG_SENSE

AT22

GFX VR_VID_0

AM22

GFX VR_VID_1

AP22

GFX VR_VID_2

AN22

GFX VR_VID_3

AP23

GFX VR_VID_4

AM23

GFX VR_VID_5

AP24

GFX VR_VID_6

AN24

GFX VR_EN

AR25

GFX VR_DPRSLPV R

AT25

GFX VR_IMON

AM24

R128

@

AJ1
AF1
AE7

1
AE4
AC1
AB7

2
AB4

Y1
W7
W4
U1
T7
T4

1
P1

+

N7
N4
L1

2
H1

P10
N10
L10
K10

1

2
J22

J20
J18
H21
H20
H19

1

2

L26
L27
M26

1

C79

2

1U_0603_10V4Z

Title

Size Do cument Number Re v

Cu st om

Ca lpella DI S LA4743P

Da te: Sheet o f

12

1K_0402_5%

1

1

C57

C56

2

2

1U_0603_10V4Z

1U_0603_10V4Z

1

1

C65

C64

2

2

22U_0805_6 .3V6M

330 U_D2_2V Y_R7M

+V CCP

1

C72

C71

2

10U_0805_6 .3V6M

10U_0805_6 .3V6M

+V CCP

1

C78

C77

2

22U_0805_6 .3V6M

22U_0805_6 .3V6M

1

1

C81

C80

2

2

1U_0603_10V4Z

2.2U_0603_6.3V4Z

Compal Electronics, Inc.

Auburndale(4/5)-PWR

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

GFX_DPRSLPVR

GRAPHICS VIDs

3A

DDR3 - 1.5V RAILS

1.1V1.8V

0.6A

2

1

VCC_ AXG_SENSE <43>
VSS_AXG_SENSE <43>

GFX VR_VID_0 <43>
GFX VR_VID_1 <43>
GFX VR_VID_2 <43>
GFX VR_VID_3 <43>
GFX VR_VID_4 <43>
GFX VR_VID_5 <43>
GFX VR_VID_6 <43>

GFX VR_EN <43>
GFX VR_DPRSLPVR <43>
GFX VR_IMON <43>

1

1

C59

C58

1U_0603_10V4Z

C66

22U_0805_6 .3V6M

1

2

C60

2

2

1U_0603_10V4Z

1

C82

C83

2

22U_0805_6.3V6M

4.7U_0603_6.3V6K

1

+1.5V

1U_0603_10V4Z

+1.8 VS

0.1

9 49Monday, April 13, 2009

5

4

3

2

1

JC PU 1H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

D D

C C

B B

AR17
AR15
AR12

AP20
AP17
AP13
AP10

AN34
AN31
AN23
AN20

AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11

AL34

AL31

AL23

AL20

AL17

AL12

AK29

AK27

AK25

AK20

AK17

AJ31

AJ23

AJ20

AJ17

AJ14

AJ11

AH35

AH34

AH33

AH32

AH31

AH30

AH29

AH28

AH27

AH26

AH20

AH17

AH13

AG10

AE35

AR9
AR6
AR3

AP7
AP4
AP2

AM8
AM5
AM2

AL9
AL6
AL3

AJ8
AJ5
AJ2

AH9
AH6
AH3

AF8
AF4
AF2

VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

JC PU1I

K27

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

VSS

NCTF

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

AT35
AT1
AR34
B34
B2
B1
A35

+V CC _CORE

@

VSS_NCTF1_R
VSS_NCTF2_R

VSS_NCTF3_R
VSS_NCTF4_R
VSS_NCTF5_R

VSS_NCTF6_R
VSS_NCTF7_R

1

1

C84

2

1

2

1

1

C982

2

2

47P _04 02_50V8J

C85

2

10U_0805_6 .3V6M

10U_0805_6 .3V6M

1

C97

C96

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C114

C115

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C86

2

10U_0805_6 .3V6M

1

C98

2

10U_0805_6.3V6M

1

C116

2

10U_0805_6.3V6M

CPU CORE

1

1

C87

2

1

2

1

2

C88

2

10U_0805_6 .3V6M

10U_0805_6 .3V6M

1

C100

C99

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C117

C118

2

10U_0805_6.3V6M

22U_0805_6.3V6M

1

1

1

C89

2

1

2

1

2

C90

2

10U_0805_6 .3V6M

10U_0805_6 .3V6M

1

C101

C102

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C119

C120

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C91

2

1

2

1

2

C92

2

10U_0805_6 .3V6M

10U_0805_6 .3V6M

1

C104

C103

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

+

C121

C108

2

22U_0805_6.3V6M

470 U_D2_2V M_R4.5M

1

1

C93

2

10U_0805_6 .3V6M

1

C105

2

10U_0805_6.3V6M

1

+

C109

2

470 U_D2_2V M_R4.5M

1

C94

2

10U_0805_6 .3V6M

1

C106

2

10U_0805_6.3V6M

1

+

C110

2

470 U_D2_2V M_R4.5M

Inside cavity

C95

2

10U_0805_6 .3V6M

1

between

C107

Inductor and

2

10U_0805_6.3V6M

socket

1

+

C111

2

470 U_D2_2V M_R4.5M

470uF 4.5mohm

IC,A UB_CFD_rPGA,R1P0

C ONN@

A A

5

4

IC,A UB_CFD_rPGA,R1P0

C ONN@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Title

Size Do cument Number Re v

Cu st om

Da te: Sheet o f

Compal Electronics, Inc.

Auburndale(5/5)-GND/Bypass

Ca lpella DI S LA4743P

10 49Monday, April 13, 2009

1

0.1

5

IC H _RTCX 1

R6 3 10M_0402 _5%

1 2

1

1

D D

2

C C

+3 VS

R6 56 10 K_0 402 _5 %

R6 57 10 K_0 402 _5 %

B B

C1 22

18 P_0 402 _5 0V8J

1 2

1 2

OSC4OSC

NC3NC

2

IC H _RTCX 2

1

C1 23

2

Y1

18 P_0 402 _5 0V8J

32 .7 68 KHZ_ 12 .5P F_Q 13MC14 61000 2

SP I_ S B_C S#

SP I _SO _R

+R TC VCC

R6 5 1M_ 0402_ 5%

R6 6 33 0K_ 040 2_ 5%

+R TC VCC

R6 9 20 K_0 402 _1 %

1 2

R7 0 20 K_0 402 _1 %

1 2

HD A_B IT CL K_M DC<33 >
HD A_B IT CL K_ COD EC<33 >
HD A_S YN C_ M DC<33 >
HD A_S YN C_ C OD EC<33 >

HD A_R ST #_ MDC<3 3>
HD A_R ST #_ CO DEC<33 ,3 7>

HD A_S DI N0<33 >
HD A_S DI N1<33 >

HD A_S DO U T_M DC<33 >
HD A_S DO U T_ COD EC<33 >

SP I_ C LK _PC H<3 6>
SP I_ SB _CS #<36>

SP I_ SI<36>

SP I_ SO _R<36 >

1 2

1 2

1

C1 24

1U _0603 _10V4 Z

1U _0603 _10V4 Z

2

1

C1 25

2

R7 2 33 _04 02_5%

1 2

R7 3 33 _04 02_5%

1 2

R7 4 33 _04 02_5%

1 2

R7 5 33 _04 02_5%

1 2

1 2

R7 7 33 _04 02_5%

1 2

R7 8 33 _04 02_5%

R8 1 33 _04 02_5%

1 2

R8 2 33 _04 02_5%

1 2

R6 70 10 0K_ 0402_ 5%@

1 2

SP I_ C L K_P CH
SP I_ S B_C S#

SP I_ SI
SP I _SO _R

SM _I N TR UD ER#

PC H_I NT V RMEN

INTVRMEN
H I n：tegrated VRM enable
L I n：tegrated VRM disable

12

CL R P1

SH O RT P ADS

12

CL R P2

SH O RT P ADS

SB _SPKR<33 >

R6 54 1 5_0 402_5%

1 2

R6 55 1 5_0 402_5%

1 2

4

IC H _RTCX 1
IC H _RTCX 2

IC H _R T CRST#
IC H _S RT CR ST#
SM _I N TR UD ER#
PC H_I NT V RMEN

HD A_B IT_CL K
H D A_ SYN C
SB _SP KR
HD A_R ST#

HD A_S D IN0
HD A_S D IN1

HD A_S D OUT

HD A_D OC K _EN#

T16P AD

PC H_J TAG_ TCK
PC H_J TAG_TMS
PC H_J TAG_TDI
PC H_J TAG_TDO
PC H_J TAG_R ST#

*

U1 A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST# / GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IB EX PEAK- M_FC BGA 1071

+3 VS

R6 4 10 K_0 402 _5 %

1 2

R6 7 1K_ 04 02_ 5%@

1 2

LOW=Default
HIGH=No Reboot

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

RTCIHDA

LPC

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA

SATA4TXP
SATA5RXN

SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

SATA0GP / GPIO21
SATA1GP / GPIO19

SPI JTAG

3

SI RQ

SB _SP KR

*

D33
B33
C32
A32

C34

LD R Q0 #

A34

LD R Q1 #

F34

SI RQ

AB9

AK7
AK6

SA TA_TXN 0_C

AK11

S ATA_ TXP0 _C

AK9

AH6
AH5

SA TA_TXN 4_C

AH9

S ATA_ TXP4 _C

AH8
AF11

AF9
AF7
AF6

AH3
AH1
AF3
AF1

AD9
AD8

SA TA_TXN 2_C

AD6

S ATA_ TXP2 _C

AD5
AD3

AD1
AB3
AB1

AF16

R8 9 37 .4_ 0402_ 1%

1 2

AF15

R9 1 10 K_0 402 _1 %

1 2

T3

G PIO 21

Y9

HD D HA L T_L ED#

V1

LP C _AD0 <31,36 ,37>
LP C _AD1 <31,36 ,37>
LP C _AD2 <31,36 ,37>
LP C _AD3 <31,36 ,37>

LP C _F RAME# <31 ,36 ,37>

T13 PA D
T14 PA D

SI RQ <37 >

C1 26 0. 01 U_0 402_5 0V7 K

1 2

C1 27 0. 01 U_0 402_5 0V7 K

1 2

C1 30 0. 01 U_0 402_5 0V7 K

1 2

C1 31 0. 01 U_0 402_5 0V7 K

1 2

C1 28 0. 01 U_0 402_5 0V7 K

1 2

C1 29 0. 01 U_0 402_5 0V7 K

1 2

+1 .05VS

+3 VS

SA TA_LE D# <38 >

HD D HA LT _L ED# <38>

SA T A_RXN0_C
SA T A_RXP0_C
S ATA_ TXN0

SATA_TX P0

SA T A_RXN4_C
SA T A_RXP4_C
S ATA_ TXN4

SATA_TX P4

SA T A_RXN2_C
SA T A_RXP2_C
S ATA_ TXN2

SATA_TX P2

2

SA TA_RXN0_ C <30>
SA TA_ RXP0_C <3 0>

SATA_T XN0 <30 >
SATA_T XP0 <30 >

SA TA_RXN4_ C <30>
SA TA_ RXP4_C <3 0>

SATA_T XN4 <30 >
SATA_T XP4 <30 >

SA TA_RXN2_ C <35>
SA TA_ RXP2_C <3 5>

SATA_T XN2 <35 >
SATA_T XP2 <35 >

12

R8 6

@

20 0_0 402_5%

12

R6 84

@

10 0_0 402_1%

HDD

ODD

E SATA

1

+3 VALW+ 3V AL W +3 VALW +3 VALW

12

R8 4

@

20 0_0 402_5%

PC H_J TAG_TMS PC H_J TAG_R ST#PC H_J TAG_TDO PC H_J TAG_TDI

12

R6 83

@

10 0_0 402_1%

R8 5
20 K_0 402 _5 %

1 2

R6 85
10 K_0 402 _1 %

1 2

@

1 2
12

@

R8 7
20 K_0 402 _5 %

R8 8

10 K_0 402 _5 %

HDA_SDO

HDA_SYNC

This signal has a weak internal pull down.

H=>On Die PLL is supplied by 1.5V
L=>On Die PLL is supplied by 1.8V

*

HDA_DOCK_EN#

ME debug mode , this signal has a weak internal PU

H=>security measures defined in the Flash

*

Descriptor will be in effect (default)

L=>Flash Descriptor Security will be overridden

A A

5

SPI_MOSI

This signal has a weak internal pull down.

Disable iTPM=No Stuff

*

Enable iTPM=Stuff

iTPM ENABLE/DISABLE

+3 VS

R6 8 1K_ 04 02_ 5%@

1 2

SP I_ SI

4

This signal has a weak internal pull down.
This signal can't PU

Disable iTPM=No Stuff

*

Enable iTPM=Stuff

W=20milsW=20mils

1

C1 32

2. 2U_06 03_6. 3V4 Z

2

Place near IBEX-M

+3 VS

G PIO 21

HD D HA L T_L ED#

R9 2 10 K_0 402 _5 %
R9 3 10 K_0 402 _5 %

12
12

Security Classification

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

D 3

1

DA N20 2U _SC70

Issued Date

2

R9 4 1K _0402 _5%

3

1 2

BATT1

@

BATT1. 1+3 VL+R TC VCC

CR2032 RTC BATTERY

JB ATT1

1

W=20mils

2008/03/13 2009/05/11

1

2

2

3

GND

4

GND

ACE S_8 520 5- 020 01

C O NN @

Compal Secret Data

Deciphered Date

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TCK

PCH_JTAG_RST#

2

1 2

R9 0 51_04 02_5%

RefDesP CH Pi n

R86
R684
R84
R683

R685
R90
R87
R88

PC H_J TAG_ TCK

PCH JTAG Enable PCH JTAG Disable
ES1 ES1E S2 ES2

200ohm

No Install

No Install

200ohm

100ohm
200ohm

No Install

100ohm 100ohm
200ohm

200ohm
100ohm 100ohm
51oh m 51ohm 51ohm
20Kohm 20Kohm
10Kohm 10Kohm

Tit le

Size Do c um en t N umb er R e v

Cu s to m

Da te : She et of

Compal Electronics, Inc.

IBEX-M(1/6)-HDA/JTAG/SATA

Ca lp ella DIS L A4743P

No Install
No Install
No Install

20Kohm
10Kohm

No Install

1

No Install
No Install
No Install
No Install
No InstallR85
No Install

51oh m
No Install
No InstallNo Install

11 49Monda y, Apr il 13, 2009

0. 1

5

D D

PC IE_R XN1<31>

WWAN

WLAN

LAN

New Card

C C

OK

OK

OK

B B

OK

A A

+3 VALW

+3 VS

+3 VS

+3 VALW

WWAN

WLAN

LAN

EXP

PC IE_RXP1<31>
PC IE_TXN 1<31>
PC IE_ TXP1<31>

PC IE_R XN2<31>
PC IE_RXP2<31>
PC IE_TXN 2<31>
PC IE_ TXP2<31>

PC IE_R XN3<32>
PC IE_RXP3<32>
PC IE_TXN 3<32>
PC IE_ TXP3<32>

PC IE_R XN4<31>
PC IE_RXP4<31>
PC IE_TXN 4<31>
PC IE_ TXP4<31>

R4 05 10 K_0 402 _5 %

1 2

R4 11 10 K_0 402 _5 %

1 2

R6 77 10 K_0 402 _5 %

1 2

R4 15 10 K_0 402 _5 %

1 2

CL K _P CI E_WWAN#<31>
CL K _P CI E_WWAN<31 >

CL K RE Q_ W WAN#< 31>

CL K _P CI E_ WLA N#< 31>
CL K _P CI E_ WLA N<3 1>

CL K RE Q_ WL AN#<31 >

CL K _P CIE _LAN#<32 >
CL K _P CIE _LAN<32 >

CL K RE Q_LAN#< 32>

CL K _PCIE_EXP#<31 >
CL K _PCIE_ EXP< 31>

CL K REQ_EXP#<31>

C1 33 0 .1U _04 02 _16 V4Z
C1 34 0 .1U _04 02 _16 V4Z

C1 35 0 .1U _04 02 _16 V4Z
C1 36 0 .1U _04 02 _16 V4Z

C1 37 0 .1U _04 02 _16 V4Z
C1 38 0 .1U _04 02 _16 V4Z

C1 39 0 .1U _04 02 _16 V4Z
C1 40 0 .1U _04 02 _16 V4Z

CL K RE Q_ W WAN#_R

CL K RE Q_ W LAN #

CL K RE Q_ LAN #

CL K RE Q_EXP# _R

R1 07 0_ 0402_ 5%
R1 08 0_ 0402_ 5%

R8 0 10 0_0 402_5%

R1 09 0_ 0402_ 5%
R1 10 0_ 0402_ 5%

R1 11 0_ 0402_ 5%
R1 12 0_ 0402_ 5%

R1 14 0_ 0402_ 5%
R1 15 0_ 0402_ 5%

R8 3 10 0_0 402_5%

R7 56 10 K_0 402_5 %

+3 VALW

R7 57 10 K_0 402_5 %

+3 VALW

R6 06 10 K_0 402_5 %

+3 VALW

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

1 2

1 2

1 2

PC IE_ RXN 1
PC I E_R XP1
PC I E_C _TX N1
PC IE_C_TXP 1

PC IE_ RXN 2
PC I E_R XP2
PC I E_C _TX N2
PC IE_C_TXP 2

PC IE_ RXN 3
PC I E_R XP3
GL A N_ C_TXN
GL A N_C _TXP

PC IE_ RXN 4
PC I E_R XP4
PC I E_C _TX N4
PC IE_C_TXP 4

CL K _P CI E_W WA N#_ R
CL K _P CI E_W WA N_R

CL K RE Q_ W WAN#_R

CL K _P CI E _WLAN#_R
CL K _P CI E _WLAN_R

CL K _P C IE_ LAN #_R
CL K _P C IE_ LAN _R

CL K _PCIE _EX P#_ R
CL K _PCIE _EX P_R

CL K RE Q_EXP# _R

PC IEC L KREQ 4#

PC IEC L KREQ 5#

PE G_B _CL KRQ #

4

U1 B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

T57P AD
T58P AD

T59P AD
T60P AD

T61P AD
T62P AD

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IB EX PEAK-M _FCBGA1 07 1

PCI-E*

SMBALERT# / GPIO11

SMBCLK

SMBDATA

SML0ALERT# / GPIO60

SML0CLK

SML0DATA

SML1ALERT# / GPIO74

SMBus

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

Link

Controller

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

Clock Flex

CL_DATA1

CL_RST1#

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_BCLK_N
CLKIN_BCLK_P

CLKIN_DOT_96N
CLKIN_DOT_96P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

3

EC _ LID_ OUT#
SM B CLK
SM BD AT A
SM L0 CLK
SM L 0DA TA
SM L0 ALERT#
SM L1 ALERT#
SM L1 CLK
SM L 1DA TA

EC _ LID_ OUT#

B9

SM B CLK

H14

SM BD AT A

C8

SM L0 ALERT#

J14

SM L0 CLK

C6

SM L 0DA TA

G8

SM L1 ALERT#

M14

SM L1 CLK

E10

SM L 1DA TA

G12

T13
T11
T9

PE G_C LK REQ #

H1

L_ C L K_P CIE_VGA#

AD43

L_ C L K_P CIE_VGA

AD45
AN4

AN2

CL K _D P#

AT1

CL K _DP

AT3

AW24
BA24

AP3
AP1

F18
E18

AH13
AH12

P41

J42

XTAL25 _IN

AH51

XTAL25 _OU T

AH53

R1 16 9 0.9 _0402 _1%

AF38

T45

P43

T42

N50

R9 5 10 K_0 402 _5%

1 2

R9 6 2.2K_040 2_5%

1 2

R9 7 2.2K_040 2_5%

1 2

R9 8 2.2K_040 2_5%

1 2

R9 9 2.2K_040 2_5%

1 2

R1 00 1 0K_ 040 2_ 5%

1 2

R1 01 1 0K_ 040 2_ 5%

1 2

R1 03 2 .2K_04 02_5%

1 2

R1 04 2 .2K_04 02_5%

1 2

EC _ LI D_O UT# <37>

SM BC LK <31>
SM BD ATA <31>

R2 15
R2 31

1 2

0_0402_5%
0_0402_5%

DTS , read from EC

R1 02 1 0K_ 040 2_ 5%

1 2

R6 04 0 _04 02_5%

1 2

R6 05 0 _04 02_5%

1 2

CL K_E XP# <6 >
CL K_E XP <6>

T71 PA D
T72 PA D

CL K _DMI# <19>
CL K _DMI <19>

CL K _B UF _BCLK# <19>
CL K _B UF _BCLK <19>

CL K _B UF_ DOT 96# <1 9>
CL K _B UF_ DOT 96 <19 >

CL K _B UF _CKS SCD# <19>
CL K _B UF _CKS SCD <1 9>

CL K _1 4M_ PCH <19 >

CL K _P CI_ FB <14>

+3 VALW

WLAN WWAN New 、

、 、

、、

For Intel LAN only

SM B_ EC_CK2 <37>
SM B_ EC_DA2 <37>

PE G_CLKREQ# <1 4>

OK

OK

OK

OK

OK

OK

OK

+1 .05VS

、 card

、、

CL K _PCIE_ VGA# <24 >

CL K _P CIE _VG A <24>

PCH

2

+3 VS

5

Q1 B

3

2N 7002D W-7 -F_ SOT 363 -6

2N 7002D W-7 -F_ SOT 363 -6

4

+3 VS

5

Q4 B

3

2N 7002D W-7 -F_ SOT 363 -6

4

OK

+3 VS

2

Q1 A

6 1

2N 7002D W-7 -F_ SOT 363 -6

+3 VS

2.2K_040 2_5%

2

Q4 A

6 1

XTAL25 _IN

XTAL25 _OU T

+3 VS

R1 05

2.2K_040 2_5%

R1 13 1 M_0402 _5%

R1 06

2.2K_040 2_5%

+3 VS

R6 81

R6 82

2.2K_040 2_5%

SM B_ E C_DA2_RSMB_ EC_DA2

SM B_ E C_CK2_RSMB_ EC_CK2

1 2

Y2

1 2

25 M HZ_20P_1B G25 00 0CK1A

1

C1 41

2

18 P_0 402 _5 0V8J

1

SM B _DATA_S 3SM BD AT A

SM B _CL K_S 3SM B CLK

SM B_ DATA_S3 <1 7,1 8,19, 30>

XDP SODIMM、

、 、

、、

SM B_ CLK _S3 <1 7,1 8,1 9, 30>

SM B_ EC_DA2_R <24>

Nvidisa thermall sensor

SM B_ EC_CK2_R <24>

1

C1 42

2

18 P_0 402 _5 0V8J

、Clock gen、、、、G sensor

、、

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Tit le

Size Do c um en t N umb er R e v

Cu s to m

Da te : She et of

Compal Electronics, Inc.

IBEX-M(2/6)-PCI-E/SMBUS/CLK

Ca lp ella DIS L A4743P

1

12 49Monda y, Apr il 13, 2009

0. 1

5

U 1 C

DM I_ CTX_ PRX _N0<7>
DM I_ CTX_ PRX _N1<7>
DM I_ CTX_ PRX _N2<7>
DM I_ CTX_ PRX _N3<7>

DM I_ CTX_ PRX _P0<7>
DM I_ CTX_ PRX _P1<7>
DM I_ CTX_ PRX _P2<7>

D D

Checklist0.8 MEPWROK
can be connect to
PWROK if iAMT disable

XD P_ DB RESET#<6>

PM _P W ROK<37>

M_ PW RO K< 37>

C C

PM _D R AM _P WRG D<6>

R_ E C_ RS MRST#<4 2>

EC _ RS MRST#<3 7>

PM _P W RBT N#_ R<6>

B B

DM I_ CTX_ PRX _P3<7>

DM I_ CRX_PTX _N0<7>
DM I_ CRX_PTX _N1<7>
DM I_ CRX_PTX _N2<7>
DM I_ CRX_PTX _N3<7>

DM I_ CRX_PTX _P0<7>
DM I_ CRX_PTX _P1<7>
DM I_ CRX_PTX _P2<7>
DM I_ CRX_PTX _P3<7>

+1 .05VS

R1 18 49 .9_ 04 02_ 1%

1 2

4mil width and place
within 500mil of the PCH

：

R1 19 0 _04 02_5%

R3 65 0_ 0402_ 5%

VG ATE<19 ,46 >

R1 20 10 K_0 402 _5 %@

R1 24 1 0K_ 040 2_ 5%

PW RBTN_OUT#<37>

PM _P W ROK PM _ RS MRST#

CH 75 1H-40 PT_SOD323 -2

SY S_ R ST#
PM _C L KRUN#

LO W _B AT#
PM _R I#
IC H _P CI E _WAKE#
EC _ AC IN

1 2

R3 73 0_ 0402_ 5%@

1 2

12

R1 21 0 _04 02_5%
R3 79 0 _04 02_5%@

R1 23

1 2

12

+3 VALW

EC _ AC IN<37>

D3 7

2 1

R1 33 10 K_0 402 _5%@
R1 29 8.2K_040 2_5%

R1 34 8.2K_040 2_5%
R1 36 10 K_0 402 _5%
R1 37 1K_ 04 02_ 5%
R1 38 8.2K_040 2_5%

DM I_ CTX _PR X_N 0
DM I_ CTX _PR X_N 1
DM I_ CTX _PR X_N 2
DM I_ CTX _PR X_N 3

DM I_ CTX _PR X_P0
DM I_ CTX _PR X_P1
DM I_ CTX _PR X_P2
DM I_ CTX _PR X_P3

DM I_ CRX_PT X_N 0
DM I_ CRX_PT X_N 1
DM I_ CRX_PT X_N 2
DM I_ CRX_PT X_N 3

DM I_ CRX_PT X_P0
DM I_ CRX_PT X_P1
DM I_ CRX_PT X_P2
DM I_ CRX_PT X_P3

DM I_ I R COMP

1 2

1 2
1 2

R1 22 10 K_0 402 _5 %

1 2

PM _D R AM _P WR GD

10 0_0 402_5%

R1 51 1 0K_ 040 2_ 5%

1 2

R1 25 0 _04 02_5%

1 2

1 2
1 2

1 2
1 2
1 2

12

SY S_ R ST#

PM _R S MRST#

EC _ AC IN

LO W _B AT#

PM _R I#

+3 VS

+3 VALW

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IB EX PEAK- M_FC BGA 1071

Check PM_SLP_LAN#

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

System Power Management

SLP_LAN# / GPIO29

SUSCLK / GPIO62

SLP_S5# / GPIO63

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

4

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

BJ14
BF13
BH13
BJ12
BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

FD I_ C TX_ PRX_ N0
FD I_ C TX_ PRX_ N1
FD I_ C TX_ PRX_ N2
FD I_ C TX_ PRX_ N3
FD I_ C TX_ PRX_ N4
FD I_ C TX_ PRX_ N5
FD I_ C TX_ PRX_ N6
FD I_ C TX_ PRX_ N7

FD I _CT X_PRX_P0
FD I _CT X_PRX_P1
FD I _CT X_PRX_P2
FD I _CT X_PRX_P3
FD I _CT X_PRX_P4
FD I _CT X_PRX_P5
FD I _CT X_PRX_P6
FD I _CT X_PRX_P7

IC H _P CI E _WAKE#

PM _C L KRUN#

PM _ SUS_STA T#

SU S_ C LK

Can b e left NC when IAMT is
not s upport on the platfrom

If no t using integrated
LAN,s ignal may be left as NC.

FD I_ CT X_PRX_N0 <7>
FD I_ CT X_PRX_N1 <7>
FD I_ CT X_PRX_N2 <7>
FD I_ CT X_PRX_N3 <7>
FD I_ CT X_PRX_N4 <7>
FD I_ CT X_PRX_N5 <7>
FD I_ CT X_PRX_N6 <7>
FD I_ CT X_PRX_N7 <7>

FD I_ CTX _PR X_P0 <7>
FD I_ CTX _PR X_P1 <7>
FD I_ CTX _PR X_P2 <7>
FD I_ CTX _PR X_P3 <7>
FD I_ CTX _PR X_P4 <7>
FD I_ CTX _PR X_P5 <7>
FD I_ CTX _PR X_P6 <7>
FD I_ CTX _PR X_P7 <7>

FD I_ I NT <7>
F DI _ FS YN C0 <7>
F DI _ FS YN C1 <7>
FD I_ L SY NC 0 <7>
FD I_ L SY NC 1 <7>

IC H _P CI E_WAKE# <31 ,32 >

T17

T18

SL P_ S5# <37>

SL P_ S4# <37>

SL P_ S3# <37>

H_ P M_ SY NC <6>

3

R7 70

IG P U_ BKL T_E N

1 2

10 0K_ 040 2_ 5%

IG P U_ BKL T_E N<22>

I_ E NA VD D<21>

DP ST _ PWM<22>

+3 VS

Close PCH and mini space 20mil

I_ C RT _D DC _CL K<20 >
I_ C RT _D D C_D ATA< 20>

I_ C RT _H SYNC< 22>
I_ C RT _V SY NC<22 >

CRB0.9 change to 0 ohm

EDID_ CLK and EDID_DATA single
end a nd keep 30 mil with other
LVDS signal avoid noise

IG P U_ BKL T_E N
I_ E NA VDD

DP ST _ PWM

I_ E DI D_CLK<22 >
I_ E DI D_ DAT A<22>

I_ L VD S_ACLK-< 22>
I_ L VD S_ACLK+<22>

I_ LV DS_ A0-<22>
I_ LV DS_ A1-<22>
I_ LV DS_ A2-<22>

I_ L VDS _A0 +<22>
I_ L VDS _A1 +<22>
I_ L VDS _A2 +<22>

I_ B LUE<22>
I_ G RE EN<22>
I_ R ED<22 >

1 2

R7 71 1 0K_04 02_5%

1 2

R7 72 1 0K_04 02_5%

R7 73 2. 37 K_0 402 _1 %

1 2

T69P AD

I_ B LU E
I_ G R EEN
I_ R ED

0_ 040 2_5%

H SY NC

R7 74

1 2
1 2

V S YNC

R7 75 0 _0 402 _5%

12

R1 26

CRB0.9 change to 1K_0402_0.5%

I_ B LU E
I_ G R EEN
I_ R ED

Pla ce t he 3 re sis tors cl ose to IBEX

1 2

R7 76 15 0_0 402_1%

1 2

R7 77 15 0_0 402_1%

1 2

R7 78 15 0_0 402_1%

T48

T47

Y48

AB48

Y45

AB46

V48

AP39
AP41

AT43
AT42

AV53
AV51

BB47
BA52
AY48
AV47

BB48
BA50
AY49
AV48

AP48
AP47

AY53
AT49
AU52
AT53

AY51
AT48
AU50
AT51

AA52
AB53

AD53

V51
V53

Y53
Y51

AD48

AB51

1K_ 04 02_ 0.5%

U 1 D

L_BKLTEN
L_VDD_EN

L_BKLTCTL
L_DDC_CLK

L_DDC_DATA
L_CTRL_CLK

L_CTRL_DATA
LVD_IBG

LVD_VBG
LVD_VREFH

LVD_VREFL

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

IB EX PEAK-M _FCBGA1 07 1

LVDS

CRT

2

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

SDVO_INTN
SDVO_INTP

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BJ46
BG46

BJ48
BG48

BF45
BH45

T51
T53

BG44
BJ44
AU38

BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38

Y49
AB49

BE44
BD44
AV40

BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

U50
U52

BC46
BD46
AT38

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

HD MI D _C T RLC LK
HD MI D _C T RLD ATA

TM DS _ B_H PD#

1

HD MI D _C TR LCL K <23>
HD MI D _C TR LDA TA <23>

TM DS _B_HPD# <23 >
TM DS D_ DAT A0# <23>

TM DS D_ DAT A0 <23>
TM DS D_ DAT A1# <23>
TM DS D_ DAT A1 <23>
TM DS D_ DAT A2# <23>
TM DS D_ DAT A2 <23>
TM DS D_CLK# <23>
TM DS D_ CLK <23>

SDVO

Display Port B

Display Port C Display Port D

A A

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Tit le

Size Do c um en t N umb er R e v

Cu s to m

Da te : She et

Compal Electronics, Inc.

IBEX-M(3/6)-DMI/GPIO/LVDS

Ca lp ella DIS L A4743P

1

13 49Monda y, Apr il 13, 2009

o f

0. 1

5

PC I_D EV SEL#
PC I_S ER R#
PC I_R EQ0 #
PC I_P IR QB#

PC I_R EQ1 #
PC I_F RAME#
PC I_T RDY#
PC I_P IR QH#

D D

PC I_R EQ3 #
PC I_P I RQF#
PC I_P ER R#
PC I_L OC K#

PC I_P IR QA#
PC I_P IR QD#
PC I_P IRQ G#
PC I_P IR QC#

PC I_P IR QE#
PC I _ST OP#
PC I_I RD Y#

DG P U_ SE LEC T#

C C

R P3

1 8
2 7
3 6
4 5

8. 2K_ 08 04_ 8P4R_ 5%
R P4

1 8
2 7
3 6
4 5

8. 2K_ 08 04_ 8P4R_ 5%
R P5

1 8
2 7
3 6
4 5

8. 2K_ 08 04_ 8P4R_ 5%

R P6

1 8
2 7
3 6
4 5

8. 2K_ 08 04_ 8P4R_ 5%
R P7

1 8
2 7
3 6
4 5

8. 2K_ 08 04_ 8P4R_ 5%

AC CEL _IN T<3 0>

GNT2

Defau lt-Internal pull up
Low=C onfigures DMI for ESI

compa tible operation(for
servers only.Not for
mobile/desktops)

B B

CL K _D EB UG_ POR T_0<3 6>
CL K _D EB UG_ POR T_1<3 1>

A A

PC I _G NT3#

R1 83 1K_04 02_5%@

A16 swap overide Strap/Top-Block
Swap Override jumper

PCI_GNT3#

+3 VS

+3 VS

DG P U_ SE LEC T#<22 >

PC I_S ER R#<37>

PC I_RST#< 36, 37>

0_ 040 2_5%

DG P U_ PW M_ SEL ECT#

R1 50

12

T70 P A D

AC CEL _I NT

*

PC I_PME #<3 7>
PL T_R ST#<6, 31,32>

R_ C LK _ PCI _FB
R_ C LK _ PCI _EC
R_ C LK _DE BUG _PO RT_ 0
R_ C LK _DE BUG _PO RT_ 1

CL K _P CI_ FB<12>
CL K _P CI_ EC<37>

1 2

Low=A16 swap
override/Top-Block
Swap Override enabled
High=Default

5

R1 58 22 _0402 _5%
R1 60 22 _0402 _5%
R1 61 22 _0402 _5%
R1 62 22 _0402 _5%

*

PC I_P IR QA#
PC I_P IR QB#
PC I_P IR QC#
PC I_P IR QD#

PC I_R EQ0 #
PC I_R EQ1 #

DG P U_ SE LEC T#

PC I_R EQ3 #
PC I _G NT0#

PC I _G NT1#
PC I _G NT3#
PC I_P IR QE#

PC I_P I RQF#
PC I_P IRQ G#
PC I_P IR QH#

PC I_S ER R#
PC I_P ER R#

PC I_I RD Y#
PC I_D EV SEL#

PC I_F RAME#
PC I_L OC K#
PC I _ST OP#

PC I_T RDY#

PL T_ RST #

1 2
1 2
1 2
1 2

US B_ O C#0
WX MI T_ OFF #
US B_ O C#1
US B_ O C#2

US B_ O C#6
US B_ O C#5
US B_ O C#4
US B_ O C#7

U 1 E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1# / GPIO50

B45

REQ2# / GPIO52

M53

REQ3# / GPIO54

F48

GNT0#

K45

GNT1# / GPIO51

F36

GNT2# / GPIO53

H53

GNT3# / GPIO55

B41

PIRQE# / GPIO2

K53

PIRQF# / GPIO3

A36

PIRQG# / GPIO4

A48

PIRQH# / GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IB EX PEAK-M _FCBGA1 07 1

R_ C LK _DE BUG _PO RT_ 0
R_ C LK _DE BUG _PO RT_ 1

RP 8

4 5
3 6
2 7
1 8

10 K_1 206 _8 P4R _5%

RP 9

4 5
3 6
2 7
1 8

10 K_1 206 _8 P4R _5%

PCI

R_ C LK _ PCI _FB
R_ C LK _ PCI _EC

+3 VALW

BU F_ PL T_R ST#<6>

4

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

NV_DQS0
NV_DQS1

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11

NVRAM

NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

NV_ALE
NV_CLE

NV_RCOMP

NV_RB#

NV_WR#0_RE#
NV_WR#1_RE#

NV_WE#_CK0
NV_WE#_CK1

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USB

USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

PC I _G NT0#
PC I _G NT1#

Boot BIOS Strap

0
0
1

R1 79 0 _04 02_5%

12

@

10 0K_ 040 2_ 5%

4

R1 85

AY9
BD1
AP15
BD8

AV9
BG8

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

BD3
AY6

AU2
AV7
AY8

AY5
AV11

BF5

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

B25
D25

N16
J16
F16
L16
E14
G16
F12
T15

R1 63 1 K_0 402 _5 %@
R1 64 1 K_0 402 _5 %@

PCI_GNT1#PCI_GNT0#

1 2

U2

@

4

O

GPIO 8

This signal has a weak internal
pull up ,can't Pull low

GPIO15

L I nt：el ME Crypto Transport
Layer Security(TLS) chiper suite
with no confidentiality

H I nt：el ME Crypto Transport
Layer Security(TLS) chiper suite
with confidentiality

*

it ha ve weak internal PU 20K

Check list Rev0.8 section1.23.2 If not
implemented, the Braidwood interface
signals can be left as No Connect (NC).

NV _ ALE
NV _ CL E

GPIO27

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

H O n-D：ie voltage regulator enable

*

US B 20_N0
US B2 0_ P0
US B 20_N1
US B2 0_ P1
US B 20_N2
US B2 0_ P2

US B 20_N4
US B2 0_ P4
US B 20_N5
US B2 0_ P5
US B 20_N6
US B2 0_ P6
US B 20_N7
US B2 0_ P7
US B 20_N8
US B2 0_ P8
US B 20_N9
US B2 0_ P9

US BR B IA S

US B_ O C#0

US B_ O C#1

US B_ O C#2
WX MI T_ OFF #
US B_ O C#4
US B_ O C#5
US B_ O C#6
US B_ O C#7

1 2
1 2

0
1
0
11

+3 VS

5

P

IN1
IN22G

SN 7 4A HC 1 G08 DCKR_SC70 -5

3

L O n-Di：e PLL Voltage Regulator disable

US B2 0_ N0 <35>
US B20_P 0 <35>
US B2 0_ N1 <35>
US B20_P 1 <35>
US B2 0_ N2 <35>
US B20_P 2 <35>

US B2 0_ N4 <21>
US B20_P 4 <21>
US B2 0_ N5 <31>
US B20_P 5 <31>
US B2 0_ N6 <35>
US B20_P 6 <35>
US B2 0_ N7 <35>
US B20_P 7 <35>
US B2 0_ N8 <31>
US B20_P 8 <31>
US B2 0_ N9 <31>
US B20_P 9 <31>

R1 55 22 .6_ 04 02_ 1%

Within 500
mils

1 2

R1 56 0_ 0402_ 5%

Boot BIOS
Location

LPC

12

Reserved(NAND)
PCI
SPI

*

PL T_ RST #

1

MB
MB
MB USB/ESATA
DOCK
USB Camera
WLAN
BT
Finger print
WWAN
New Card

Intel Anti-Theft Techonlogy

NV_ALE

NV _ ALE

NV _ CL E

3

R1 40 1 K_0 402 _1 %

1 2

+3 VS

DG P U_ HO LD _RST#<24>

R1 45 1 0K_ 040 2_ 5%

1 2

+3 VS

PC H_T EMP_ ALE RT#

BT _O FF <35>

WX MI T_OFF# <31>

High=Endabled
Low=Disable(floating)

R1 74 1 K_0 402 _5 %@

1 2

DMI Termination Voltage

Set to Vcc when HIGH

NV_CLE

Set to Vss when LOW

Weak internal
PU,Do not pull low

R1 84 1 K_0 402 _5 %@

1 2

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DG P U_ ED ID SEL#<2 0>
DG P U_ HP D_ INT#<2 3>

EC _ SCI #<3 7>
EC _ SMI#<3 7>

CR _ WA KE #<32>

XM IT _OFF<31 >

Internal VccVRM Option

DG P U_ PW R _EN<23 ,3 9,4 5,4 7>

*

+1 .8VS

+3 VS

U 1 F

PC H_G PIO 0
DG P U_ ED I DSEL #
DG P U_ HP D _IN T#
EC _ SC I#
EC _ SMI #
PC H_G PIO 12
PC H_G PIO 15
DG P U_ HO L D_RST#
DG P U_ PW R OK
CR _ WA K E#
XM I T_O FF

PC H_G PIO 28
H_ S TP _PCI#
G PIO 35
DG P U_ PW R _EN
VG A_P RSN T_L #
G PIO 38
G PIO 39
PC IEC L KREQ 6#
PC IEC L KREQ 7#
G PIO 48
PC H_T EMP _AL ERT#
G PIO 57

NV_ALE

Enabl e Intel Anti-Theft
Techn ology 8.2K PU to +3VS

Disab le Intel Anti-Theft
Techn ology floating(internal PD)

NV_CLE

DMI t ermination voltage.
weak internal PU, don't PD

2008/03/13 2009/05/11

Y3

BMBUSY# / GPIO0

C38

TACH1 / GPIO1

D37

TACH2 / GPIO6

J32

TACH3 / GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CTRL / GPIO12

T7

GPIO15

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

Y7

SCLOCK / GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI# / GPIO34

V6

SATACLKREQ# / GPIO35

AB7

SATA2GP / GPIO36

AB13

SATA3GP / GPIO37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PCIECLKRQ6# / GPIO45

F1

PCIECLKRQ7# / GPIO46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IB EX PEAK-M _FCBGA1 07 1

：

：

PE G_CLKREQ#<12>

Compal Secret Data

2

GPIO

NCTF

Deciphered Date

2

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P

CLKOUT_PCIE7P

PROCPWRGD

CPU

RSVD

+3 VS_NV

2

Q2 9A
2N 7002D W-7 -F_ SOT 363 -6

Q2 9B

61

5

AH45

T19 PA D

AH46

T20 PA D

AF48

T21 PA D

AF47

T22 PA D

GA TE A20

U2

A20GATE

AM3
AM1

PC H_P EC I_ R

BG10

PECI

KB _ RST#

T1

RCIN#

BE10

H_ THE RMT RIP#_L

BD10

THRMTRIP#

BA22

TP1

AW22

TP2

BB22

TP3

AY45

TP4

AY46

TP5

AV43

TP6

AV45

TP7

AF13

TP8

M18

TP9

N18

TP10

AJ24

TP11

AK41

TP12

AK42

TP13

M32

TP14

N32

TP15

M30

TP16

N30

TP17

H12

TP18

AA23

TP19

AB45

NC_1

AB38

NC_2

AB42

NC_3

AB41

NC_4

T39

NC_5

P6

INIT3_3V#

C10

TP24

DG P U_ PW R OK

3

4

2N 70 02 DW- 7-F_SO T36 3-6

Tit le

Size Do c um en t N umb er R e v

Cu s to m

Ca lp ella DIS L A4743P

Da te : She et of

GA TEA 20 <37 >

CL K _C PU _BC LK# <6>
CL K _C PU _BC LK <6>

R1 44 0_040 2_5%

KB _RST# <37>
H_ C PU PW RGD <6>

1 2

R1 46

EC _ SC I#
DG P U_ ED I DSEL #
KB _ RST#
DG P U_ PW R _EN
DG P U_ HP D _IN T#
VG A_P RSN T_L #
DG P U_ HO L D_RST#
G PIO 38
GA TE A20
PC H_T EMP _AL ERT#
G PIO 39
G PIO 48
CR _ WA K E#
DG P U_ PW R OK

INIT3_3V

This signal has weak internal
PU, can't pull low

T48 PA D

EC _ SMI #
PC H_G PIO 15
PC H_G PIO 12
PC IEC L KREQ 6#
PC IEC L KREQ 7#
PC H_G PIO 28
G PIO 57
G PIO 35
VG A_P RSN T_L #

Compal Electronics, Inc.

IBEX-M(4/6)-PCI/USB/RSVD

1

1 2

54 .9_ 0402_ 1%

12

R1 47
56 _04 02_5%

R1 66 1 0K_ 040 2_ 5%

1 2

R1 67 1 0K_ 040 2_ 5%

1 2

R1 71 1 0K_ 040 2_ 5%

1 2

R1 72 1 0K_ 040 2_ 5%

1 2

R1 73 1 0K_ 040 2_ 5%

1 2

R1 75 1 0K_ 040 2_ 5%

1 2

R1 76 1 0K_ 040 2_ 5%

1 2

R1 78 1 0K_ 040 2_ 5%

1 2

R1 80 1 0K_ 040 2_ 5%

1 2

R1 81 1 0K_ 040 2_ 5%

1 2

R1 69 1 0K_ 040 2_ 5%

1 2

R1 70 1 0K_ 040 2_ 5%

1 2

R1 68 1 0K_ 040 2_ 5%

1 2

R8 74 1 0K_ 040 2_ 5%

1 2

R1 57 10 K_0 402_5 %

1 2

R1 59 1K_04 02_5%

1 2

R8 11 10 K_0 402_5 %

1 2

R8 12 10 K_0 402_5 %

1 2

R8 13 10 K_0 402_5 %

1 2

R8 14 10 K_0 402_5 %

1 2

R1 82 10 K_0 402_5 %

1 2

R1 65 10 K_0 402_5 %
R9 11 10 K_0 402_5 %

1 2

1

OK

H_ P ECI <6>

H_ THE RMT RIP# <6>

+V CCP

+3 VS

+3 VALW

12

0. 1

14 49Monda y, Apr il 13, 2009

5

4

3

2

1

1

2

1 2

1

1

C1 62

2

2

10 U_0 805_6 .3V 6M

1 2

0. 1U_04 02_16 V4Z

+1 .8VS

+1 .05VS

1

C1 73

2

1U_04 02_6. 3V6 K

+V 1.1 A_ I NT_VCCS US

+3 VALW

+3 VS

0.

0. 1A @1.1 V

0.0.

1

1

C1 88

2

2

4. 7U_06 03_6. 3V6 K

2m

2m A@ 3.3V

2m2m

1

2

+V CCP _V CC A_C LK

1

C1 43

@

@

2

10 U_0 805_6 .3V 6M

C1 52

0. 1U_04 02_16 V4Z

+1. 05 VS

1

C1 53

2

1

C1 63

2

10 U_0 805_6 .3V 6M

+V CCR TCEX T

1

C1 74

C1 75

2

1U_04 02_6. 3V6 K

+V CCS ST

0.

0. 2A @3.3 V

2A@ 3.3V

0.0.

2A@ 3.3V2A@ 3.3V

0.

0. 4A @3.3 V

4A@ 3.3V

0.0.

4A@ 3.3V4A@ 3.3V

1A@ 1.1V

1A@ 1.1V1A@ 1.1V

1

C1 89

2

0. 1U_04 02_16 V4Z

A@3 .3V

A@3 .3VA@3 .3V

1

C1 97

C1 96

2

0. 1U_04 02_16 V4Z

AP51

C1 44

AP53

1U_04 02_6. 3V6 K

AF23
AF24

Y20

AD38
AD39
AD41
AF43
AF41

1U_04 02_6. 3V6 K

AF42

V39
V41
V42
Y39

C1 61

Y41

1U_04 02_6. 3V6 K

Y42

V9

AU24

BB51
BB53

BD51
BD53

AH23

AJ35

AH35
AF34
AH34

1U_04 02_6. 3V6 K

AF32

V12

Y22

P18
U19
U20
U22

V15
V16
Y16

AT18

AU18

C1 90

A12

0. 1U_04 02_16 V4Z

0. 1U_04 02_16 V4Z

U 1 J

VCCACLK[1]
VCCACLK[2]

VCCLAN[1]
VCCLAN[2]

DCPSUSBYP

VCCME[1]
VCCME[2]
VCCME[3]
VCCME[4]
VCCME[5]
VCCME[6]
VCCME[7]
VCCME[8]
VCCME[9]
VCCME[10]
VCCME[11]
VCCME[12]

DCPRTC

VCCVRM[3]

VCCADPLLA[1]
VCCADPLLA[2]

VCCADPLLB[1]
VCCADPLLB[2]

VCCIO[21]
VCCIO[22]
VCCIO[23]

VCCIO[2]
VCCIO[3]
VCCIO[4]
DCPSST

DCPSUS

VCCSUS3_3[29]
VCCSUS3_3[30]
VCCSUS3_3[31]
VCCSUS3_3[32]

VCC3_3[5]
VCC3_3[6]
VCC3_3[7]

V_CPU_IO[1]

V_CPU_IO[2]

VCCRTC

IB EX PEAK-M _FCBGA1 07 1

POWER

0.052A

0.344A

1.998A

0.035A

0.072A

0.073A

3.208A

2mA

+1 .05VS

+1 .05VS

V24

VCCIO[5]

V26

VCCIO[6]
VCCIO[7]
VCCIO[8]

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]

VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]

USB

VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]

0.163A

VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]

VCCSUS3_3[28]

VCCIO[56]

>1mA

V5REF_SUS

>1mA

V5REF

VCC3_3[8]

0.357A

PCI/GPIO/LPC

0.032A

SATA

6mA

HDA

VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]

VCCSATAPLL[1]
VCCSATAPLL[2]

VCCIO[9]

VCCVRM[4]

VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]

VCCIO[14]
VCCIO[15]
VCCIO[16]

VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]

VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]

VCCSUSHDA

4

Clock and Miscellaneous

CPU

RTC PCI/GPIO/LPC

1
Y24
Y26

2

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

U23
V23

IC H _V 5R E F_S US

F24

IC H _V 5R E F_ RU N

K49

+3 VS

J38
L38
M36
N36
P36

+3 VS

U35

AD13

+1 . 05V S_V CCAPLL

AK3
AK1

AH22

AT20

+1 .8VS

AH19
AD20
AF22
AD19

AF20
AF19
AH20

AB19
AB20
AB22
AD22

+P CH_ VCC 1_1 _2 0

AA34

+P CH_ VCC 1_1 _2 1

Y34

+P CH_ VCC 1_1 _2 2

Y35

+P CH_ VCC 1_1 _2 3

AA35

+3 . 3A _1. 5A_ VCC PAZS US

L30

C1 50

1U _0402 _6.3V6K

+3 VALW

1

1

C1 58

C1 57

2

2

0. 1U_04 02_16 V4Z

0. 1U_04 02_16 V4Z

+1 .05VS

1

C1 71

2

0. 1U_04 02_16 V4Z

C1 76 0. 1U_ 0402_ 16V4Z

1 2

0.

0. 1A @1.1 V

1A@ 1.1V

0.0.

1A@ 1.1V1A@ 1.1V

10 UH_ LB2 012 T10 0MR _20%_ 080 5

1

1

C1 80

C1 81

2

@

@

2

1U_04 02_6. 3V6 K

10 U_0 805_6 .3V 6M

1

C1 84

2

1U_04 02_6. 3V6 K

R1 94 0_ 0402_ 5%

1 2

R1 95 0_ 0402_ 5%

1 2

R1 98 0_ 0402_ 5%

1 2

R2 00 0_ 0402_ 5%

1 2

+3 VALW

1

C1 93

2

1U_04 02_6. 3V6 K

L4

@

1 2

+1 .05VS

+1 .05VS

+1 .05VS

R1 88

@

1 2

10 UH_ LB2 012 T10 0MR _20%_ 080 5

0_ 060 3_5%

C6 82 0 .1U _04 02 _16 V4Z

+1 .05VS+1. 05VS_VCCA PLL _L

R1 89

@

1 2

0_ 060 3_5%

+1 .05VS_ L+1.0 5VS +V 1.05S_ VCCA_A_ DPL _L

R1 91

1 2

0_ 060 3_5%

1 2

0_ 060 3_5%

R2 01

1 2

0_ 060 3_5%

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1 2

+3 VS

1 2

+1 .8VS

+1 .05VS

R1 92

+V 1.0 5S_VCC A_B _DP L_L

1

1

C1 45

2

2

1U_04 02_6. 3V6 K

+1 .05VS_ APL L

L3

@

1

2

+1 .05VS

1

1

C1 64

2

2

1U_04 02_6. 3V6 K

1

1

2

10 UH_ LB2 012 T10 0MR _20%_ 080 5

10 UH_ LB2 012 T10 0MR _20%_ 080 5

1

C1 69

C1 68

2

2

1U _0402 _6.3V6K

1U _0402 _6.3V6K

+1 . 05 V S_V CCFDIPL L

L6

1 2

L7

1 2

U1 G

AB24

VCCCORE[1]

AB26

VCCCORE[2]

AB28

VCCCORE[3]

AD26

VCCCORE[4]

AD28

VCCCORE[5]

AF26

C1 46

VCCCORE[6]

AF28

VCCCORE[7]

AF30

VCCCORE[8]

10 U_0 603_6 .3V 6M

AF31

VCCCORE[9]

AH26

VCCCORE[10]

AH28

VCCCORE[11]

AH30

VCCCORE[12]

AH31

VCCCORE[13]

AJ30

VCCCORE[14]

AJ31

VCCCORE[15]

AK24

VCCIO[24]

BJ24

VCCAPLLEXP

AN20

VCCIO[25]

AN22

VCCIO[26]

AN23

C1 59

VCCIO[27]

@

AN24

VCCIO[28]

AN26

VCCIO[29]

10 U_0 805_6 .3V 6M

AN28

VCCIO[30]

BJ26

VCCIO[31]

BJ28

VCCIO[32]

AT26

VCCIO[33]

AT28

VCCIO[34]

AU26

VCCIO[35]

AU28

VCCIO[36]

AV26

VCCIO[37]

AV28

VCCIO[38]

AW26

VCCIO[39]

AW28

VCCIO[40]

BA26

C1 65

VCCIO[41]

BA28

VCCIO[42]

BB26

1U_04 02_6. 3V6 K

VCCIO[43]

BB28

VCCIO[44]

BC26

VCCIO[45]

BC28

VCCIO[46]

BD26

VCCIO[47]

BD28

VCCIO[48]

BE26

VCCIO[49]

BE28

VCCIO[50]

BG26

VCCIO[51]

BG28

C1 70

VCCIO[52]

BH27

VCCIO[53]

10 U_0 603_6 .3V 6M

AN30

VCCIO[54]

AN31

VCCIO[55]

AN35

VCC3_3[1]

AT22

VCCVRM[1]

BJ18

VCCFDIPLL

AM23

VCCIO[1]

IB EX PEAK-M _FCBGA1 07 1

+V 1.0 5S_VC CA_ A_D PL

2

1

+V 1.0 5S_VC CA_ B_D PL

1

2

2008/03/13 2009/05/11

POWER

1.524A

0.042A

0.035A
6mA

1

+

C1 86

C1 87

2

1U_04 02_6. 3V6 K

22 0U_D2_4 VM_ R15

1

+

C1 92

C1 91

2

1U _0402 _6.3V6K

22 0U_B_2. 5VM_ R1 5M

Compal Secret Data

Deciphered Date

AE50

VCCADAC[1]
VCCADAC[2]

VCCALVDS

VSSA_LVDS

VCC3_3[2]
VCC3_3[3]
VCC3_3[4]

AE52
AF53
AF51

AH38
AH39

AP43
AP45
AT46
AT45

AB34
AB35
AD35

0.069A

VSSA_DAC[1]

CRTLVDS

VSSA_DAC[2]

0.030A

VCC CORE

VCCTX_LVDS[1]

0.059A

VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]

HVCMOS

AT24

VCCVRM[2]

AT16

VCCDMI[1]

0.061A

DMI

VCCPNAND[1]

PCI E*

VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]

0.156A

VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]

VCCME3_3[1]

NAND / SPI

VCCME3_3[2]

0.085A

VCCME3_3[3]

12

2

VCCME3_3[4]

R1 93

@

0_ 060 3_5%

FDI

VCCDMI[2]

AU16

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

AM8
AM9
AP11
AP9

1

2

C9 98

1

2

+1 .8 VS

+V CCP

+1 .05VS

R1 96

10 0_0 402_5%

1

C1 48

C1 47

2

10 U_0 805_6 .3V 6M

0.01U _04 02 _25 V7K

0.01U _06 03 _16 V7K

0.01U _06 03 _16 V7K
C1 000

C9 99

1

1

2

2

1

C1 67

2

1U _0402 _6.3V6K

1

C1 72

2

0. 1U_04 02_16 V4Z

+3 VS

1

C1 78

2

0. 1U_04 02_16 V4Z

R1 90

@

1 2

0_ 060 3_5%

21

12

D 4
CH 75 1H-40 PT_SOD323 -2

1

C1 94
1U_04 02_6. 3V4 K_X 5R

2

Tit le

Size Do c um en t N umb er R e v

Cu s to m

Da te : She et of

L4 5

MU RA TA_ BLM18A G601SN1D _06 03

1

C1 49

2

0. 1U_04 02_16 V4Z

+3 VS

R7 79 0 _06 03_5%

1 2

10 U_0 805_6 .3V 6M

+3 VS

1

C1 60

2

0. 1U_04 02_16 V4Z

R6 71 0_040 2_5%

1 2

R6 72 0_040 2_5%@

1 2

+1 . 05 VS_VC CFD IPL L_L

10 UH_ LB2 012 T10 0MR _20%_ 080 5

IC H _V 5R E F_S US

Compal Electronics, Inc.

IBEX-M(5/6)-PWR

Ca lp ella DIS L A4743P

12

L5

@

1 2

R1 97

10 0_0 402_5%

1

+3 VS

+1 .8VS

+1 .8VS

+3 VS

+1 . 05 V S_V CCFDIPL L

+5 VS +3 VS+3 VALW+5 VALW

12

1

C1 83

@

2

10 U_0 805_6 .3V 6M

21

D 5

CH 75 1H-40 PT_SOD323 -2

IC H _V 5R E F_ RU N

20 mils20 mils

1

C1 95
1U_04 02_6. 3V4 K_X 5R

2

15 49Monda y, Apr il 13, 2009

0. 1

+1 .05VS + VC C P_ VC CA_ CLK _L

R1 86

@

1 2

0_ 060 3_5%

10 UH_ LB2 012 T10 0MR _20%_ 080 5

D D

C C

B B

A A

DG1.1 no M3
support and not
Intel LAN, VCCLAN
Source=>GND

+R TC VCC

L1

@

1 2

C1 66

+V 1.0 5S_VC CA_ A_D PL
+V 1.0 5S_VC CA_ B_D PL

1

2

1 2

0. 1U_04 02_16 V4Z

C1 77

1 2

0. 1U_04 02_16 V4Z

C1 79

1 2

0. 1U_04 02_16 V4Z

C1 82

1 2

0. 1U_04 02_16 V4Z

C1 85

+V CCP

5

5

4

3

2

1

U1 I

AY7

VSS[159]

B11

VSS[160]

B15

VSS[161]

B19

VSS[162]

B23

VSS[163]

B31

VSS[164]

B35

VSS[165]

B39

VSS[166]

B43

VSS[167]

B47

D D

C C

B B

BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49

BC10
BC14
BC18

BC22
BC32
BC36
BC40
BC44
BC52

BD48
BD49

BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50

BF49
BF51
BG18
BG24

BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47

AF39

VSS[168]

B7

VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]

BB5

VSS[180]
VSS[181]
VSS[182]
VSS[183]

BC2

VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]

BH9

VSS[191]
VSS[192]
VSS[193]

BD5

VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]

BE6

VSS[206]

BE8

VSS[207]

BF3

VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]

BG4

VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]

BH7

VSS[224]

C12

VSS[225]

C50

VSS[226]

D51

VSS[227]

E12

VSS[228]

E16

VSS[229]

E20

VSS[230]

E24

VSS[231]

E30

VSS[232]

E34

VSS[233]

E38

VSS[234]

E42

VSS[235]

E46

VSS[236]

E48

VSS[237]

E6

VSS[238]

E8

VSS[239]

F49

VSS[240]

F5

VSS[241]

G10

VSS[242]

G14

VSS[243]

G18

VSS[244]

G2

VSS[245]

G22

VSS[246]

G32

VSS[247]

G36

VSS[248]

G40

VSS[249]

G44

VSS[250]

G52

VSS[251]
VSS[252]

H16

VSS[253]

H20

VSS[254]

H30

VSS[255]

H34

VSS[256]

H38

VSS[257]

H42

VSS[258]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]

H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14

U 1 H

AB16

VSS[0]

AA19

VSS[1]

AA20

VSS[2]

AA22

VSS[3]

AM19

VSS[4]

AA24

VSS[5]

AA26

VSS[6]

AA28

VSS[7]

AA30

VSS[8]

AA31

VSS[9]

AA32

VSS[10]

AB11

VSS[11]

AB15

VSS[12]

AB23

VSS[13]

AB30

VSS[14]

AB31

VSS[15]

AB32

VSS[16]

AB39

VSS[17]

AB43

VSS[18]

AB47

VSS[19]

AB5

VSS[20]

AB8

VSS[21]

AC2

VSS[22]

AC52

VSS[23]

AD11

VSS[24]

AD12

VSS[25]

AD16

VSS[26]

AD23

VSS[27]

AD30

VSS[28]

AD31

VSS[29]

AD32

VSS[30]

AD34

VSS[31]

AU22

VSS[32]

AD42

VSS[33]

AD46

VSS[34]

AD49

VSS[35]

AD7

VSS[36]

AE2

VSS[37]

AE4

VSS[38]

AF12

VSS[39]

Y13

VSS[40]

AH49

VSS[41]

AU4

VSS[42]

AF35

VSS[43]

AP13

VSS[44]

AN34

VSS[45]

AF45

VSS[46]

AF46

VSS[47]

AF49

VSS[48]

AF5

VSS[49]

AF8

VSS[50]

AG2

VSS[51]

AG52

VSS[52]

AH11

VSS[53]

AH15

VSS[54]

AH16

VSS[55]

AH24

VSS[56]

AH32

VSS[57]

AV18

VSS[58]

AH43

VSS[59]

AH47

VSS[60]

AH7

VSS[61]

AJ19

VSS[62]

AJ2

VSS[63]

AJ20

VSS[64]

AJ22

VSS[65]

AJ23

VSS[66]

AJ26

VSS[67]

AJ28

VSS[68]

AJ32

VSS[69]

AJ34

VSS[70]

AT5

VSS[71]

AJ4

VSS[72]

AK12

VSS[73]

AM41

VSS[74]

AN19

VSS[75]

AK26

VSS[76]

AK22

VSS[77]

AK23

VSS[78]

AK28

VSS[79]

IB EX PEAK-M _FCBGA1 07 1

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47

A A

5

IB EX PEAK-M _FCBGA1 07 1

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Tit le

Size Do c um en t N umb er R e v

Cu s to m

Da te : She et of

Compal Electronics, Inc.

IBEX-M(6/6)-GND

Ca lp ella DIS L A4743P

1

16 49Monda y, Apr il 13, 2009

0. 1

5

+V REF_D Q_DIMM A

0.1U_ 040 2_ 10V 6K

2. 2U_06 03_6. 3V4 Z

C1 057

1

D D

C C

B B

A A

2

C1 058

1

2

DD R _C KE 0 _DI MMA<8>

DD R _A _BS 2<8>

M_ CLK _DD R0<8>
M_ CLK _DD R#0<8>

DD R _A _BS 0<8>
DD R _A _W E#<8>

DD R _A _C AS#<8>

DD R _C S1 _D IMMA#<8>

+3 VS

1

2

5

DD R _A _D 0
DD R _A _D 1

DD R _A _D M0
DD R _A _D 2

DD R _A _D 3
DD R _A _D 8

DD R _A _D 9
DD R _A _ DQS #1

DD R _A _ DQS 1
DD R _A _D 10

DD R _A _D 11
DD R _A _D 16

DD R _A _D 17
DD R _A _ DQS #2

DD R _A _ DQS 2
DD R _A _D 18

DD R _A _D 19
DD R _A _D 24

DD R _A _D 25
DD R _A _D M3
DD R _A _D 26

DD R _A _D 27

DD R _C KE 0 _D IMMA

DD R _A _B S2
DD R _A_MA 12

DD R _A _M A9
DD R_A_MA8

DD R _A _M A5
DD R _A _M A3

DD R _A _M A1
M_ CLK _D DR0

M_ CLK _D DR# 0
DD R _A_MA 10

DD R _A _B S0
DD R _A _ WE#

DD R _A _ CAS # M_ O DT0
DD R _A_MA 13

DD R _C S1 _ DIM MA#

DD R _A _D 32
DD R _A _D 33

DD R _A _ DQS #4
DD R _A _ DQS 4

DD R _A _D 34
DD R _A _D 35

DD R _A _D 40
DD R _A _D 41

DD R _A _D M5
DD R _A _D 42

DD R _A _D 43
DD R _A _D 48

DD R _A _D 49
DD R _A _ DQS #6

DD R _A _ DQS 6
DD R _A _D 50

DD R _A _D 51
DD R _A _D 56

DD R _A _D 57
DD R _A _D M7
DD R _A _D 58

DD R _A _D 59

1 2

10 K_0 402 _5 %

1

C2 20

C2 19

2

0. 1U_04 02_16 V4Z

2.2U_ 040 2_ 6.3 V6M

+1. 5V +1. 5V

3A @1

3A @1 .5 V

.5V

3A @13A @1

.5V.5V

JD I MM1 C O NN @

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9
VSS925VSS10

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17
VSS1849DQ22

51

DQ18
DQ1953VSS19
VSS2055DQ28

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3
A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

R2 07

12

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

R2 08

10 K_0 402 _5 %

VREF_CA

+ 0.7 5VS

VSS3

DQS0

VSS6

VSS8
DQ12
DQ13

DM1

DQ14
DQ15

DQ20
DQ21

DM2

DQ23

DQ29

DQS3

DQ30
DQ31

CKE1

VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

VTT2

DQ4
DQ5

DQ6
DQ7

A15
A14

A7
A6

A4
A2

A0

CK1

BA1

S0#

NC2

SCL

G2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

4

DD R _A _D 4
DD R _A _D 5

DD R _A _ DQS #0
DD R _A _ DQS 0

DD R _A _D 6
DD R _A _D 7

DD R _A _D 12
DD R _A _D 13

DD R _A _D M1
DR AMR ST#

DD R _A _D 14
DD R _A _D 15

DD R _A _D 20
DD R _A _D 21

DD R _A _D M2
DD R _A _D 22

DD R _A _D 23
DD R _A _D 28

DD R _A _D 29
DD R _A _ DQS #3

DD R _A _ DQS 3
DD R _A _D 30

DD R _A _D 31

DD R _C KE 1 _D IMMA
DD R _A_MA 15

DD R _A_MA 14
DDR_A_MA11

DD R _A _M A7
DD R_A_MA6

DD R _A _M A4
DD R _A _M A2

DD R _A _M A0
M_ CLK _D DR1

M_ CLK _D DR# 1
DD R _A _B S1

DD R _A _ RAS #
DD R _C S0 _ DIM MA#

M_ O DT1

V_ D DR _M CH_ RE F

DD R _A _D 36
DD R _A _D 37

DD R _A _D M4
DD R _A _D 38

DD R _A _D 39
DD R _A _D 44

DD R _A _D 45
DD R _A _ DQS #5

DD R _A _ DQS 5
DD R _A _D 46

DD R _A _D 47
DD R _A _D 52

DD R _A _D 53
DD R _A _D M6
DD R _A _D 54

DD R _A _D 55
DD R _A _D 60

DD R _A _D 61
DD R _A _ DQS #7

DD R _A _ DQS 7
DD R _A _D 62

DD R _A _D 63
P M_EX TTS# 1_R

SM B _DATA_S 3
SM B _CL K_S 3

0. 65 A

0. 65 A @0.7 5V

0. 65 A0. 65 A

4

+0 .75VS

@0. 75V

@0. 75V@0. 75V

DR AMR ST# <6,18>

DD R _C KE 1 _DI MMA <8>

M_ CLK _DD R1 <8>
M_ CLK _DD R#1 <8>

DD R _A _BS 1 <8>
DD R _A _R AS# <8>

DD R _C S0 _D IMMA# <8>
M_ OD T0 <8>

M_ OD T1 <8>

PM_ EXTTS#1_R <6, 18>

SM B_ DATA_S 3 <12, 18, 19 ,30>
SM B_ CLK _S3 <12, 18, 19,30>

+V REF_CA +V_ D DR _ CP U_ REF

1

1

C2 13

C2 14

2

2

0. 1U_04 02_16 V4Z

2.2U_ 040 2_ 6.3 V6M

DD R _A _D[0. .63 ]<8>
DD R _A _D M[0 ..7 ]<8>
DD R _A _D QS[ 0..7]<8>
DD R _A _D QS# [0..7 ]<8>
DD R _A _MA [0. .15 ]<8>

1 2

R8 77 0 _0 402 _5%

3

Layout Note:
Pl ace near JP4

1

2

+1. 5V

1

1

C2 03

C2 01

10 U_0 603_6 .3V 6M

C2 04

2

2

10 U_0 603_6 .3V 6M

10 U_0 603_6 .3V 6M

Layout Note:
Place near JP4.203 & JP4.204

1

C2 05

2

10 U_0 603_6 .3V 6M

+0 .75VS

1

1

C2 06

2

2

10 U_0 603_6 .3V 6M

1

1

C2 16

C2 15

2

2

1U _0402 _6.3V6K

+V REF_D Q_DIMM A

1

C2 08

C2 07

2

10 U_0 603_6 .3V 6M

1

1

C2 17

2

2

1U _0402 _6.3V6K

1U _0402 _6.3V6K

2

1 2

R8 84 0_ 0402_ 5%

1 2

R8 98 0_ 0402_ 5%

1

C2 09

2

0. 1U_04 02_16 V4Z

10 U_0 603_6 .3V 6M

1

C2 02

C2 18

2

1U _0402 _6.3V6K

10 U_0 805_6 .3V 6M

1

2

DDR3 SO-DIMM A

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

C2 10

M3 @

1

V_ D DR _C P U_ RE F+V REF_D Q_ DIMMA

+V _DD R_ C PU _REF

+V _DD R_ C PU_REF 0

R2 05

1K_ 04 02_ 1%

+1. 5V

12

+V _DD R_ C PU _REF

12

R2 06
1K_ 04 02_ 1%

1

C2 11

2

0. 1U_04 02_16 V4Z

1

1

+

C2 00
33 0 U_ D2_2VY_R7M

C2 12

2

2

0. 1U_04 02_16 V4Z

0. 1U_04 02_16 V4Z

REVERSE

Tit le

Size Do c um en t N umb er R e v

Cu s to m

Da te : She et of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

Ca lp ella DIS L A4743P

1

17 49Monda y, Apr il 13, 2009

0. 1

5

+1 .5V +1 .5V

3A @1

3A @1 .5 V

.5V

3A @13A @1

+V REF_D Q_DIMM B

1

2

D D

C C

B B

A A

V_ D DR _M CH_ RE F

1

C2 21

2

C1 059

2.2U_ 040 2_ 6.3 V6M

0.1U_ 040 2_ 10V 6K

DD R _C KE 2 _DI MMB<8>

DD R _B _BS 2<8>

M_ CLK _DD R2<8>
M_ CLK _DD R#2<8>

DD R _B _BS 0<8>
DD R _B _W E#<8>

DD R _B _C AS#<8>

DD R _C S3 _D IMMB#<8>

+3 VS

1

C2 41

2

DD R _B _D 0
DD R _B _D 1

DD R _B _D M0
DD R _B _D 2

DD R _B _D 3
DD R _B _D 8

DD R _B _D 9
DD R _B _ DQS #1

DD R _B _ DQS 1
DD R _B _D 10

DD R _B _D 11
DD R _B _D 16

DD R _B _D 17
DD R _B _ DQS #2

DD R _B _ DQS 2
DD R _B _D 18

DD R _B _D 19
DD R _B _D 24

DD R _B _D 25
DD R _B _D M3
DD R _B _D 26

DD R _B _D 27

DD R _C KE 2 _D IMMB

DD R _B _B S2
DD R _B_MA 12

DD R _B _M A9
DDR_B_MA8

DD R _B _M A5
DD R _B _M A3

DD R _B _M A1
M_ CLK _D DR2

M_ CLK _D DR# 2
DD R _B_MA 10

DD R _B _B S0
DD R _B _ WE#

DD R _B _ CAS # M_O DT2
DD R _B_MA 13

DD R _C S3 _ DIM MB#

DD R _B _D 32
DD R _B _D 33

DD R _B _ DQS #4
DD R _B _ DQS 4

DD R _B _D 34
DD R _B _D 35

DD R _B _D 40
DD R _B _D 41

DD R _B _D M5
DD R _B _D 42

DD R _B _D 43
DD R _B _D 48

DD R _B _D 49
DD R _B _ DQS #6

DD R _B _ DQS 6
DD R _B _D 50

DD R _B _D 51
DD R _B _D 56

DD R _B _D 57
DD R _B _D M7
DD R _B _D 58

DD R _B _D 59

R2 10

1 2

10 K_0 402 _5%

R2 11

1 2

1

10 K_0 402 _5 %

C2 42

2

0. 1U_04 02_16 V4Z

2.2U_ 040 2_ 6.3 V6M

5

.5V.5V

JD I MM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9
VSS925VSS10

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17
VSS1849DQ22

51

DQ18
DQ1953VSS19
VSS2055DQ28

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3
A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

C O NN @

+ 0.7 5VS

VSS3
DQS0

VSS6

VSS8
DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ23

DQ29

DQS3
DQ30

DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30
VSS31

DQ38
DQ39

VSS33

DQ44

DQ45
VSS35
DQS#5

DQS5
VSS38

DQ46

DQ47
VSS40

DQ52

DQ53
VSS42

VSS43

DQ54

DQ55
VSS45

DQ60

DQ61
VSS47
DQS#7

DQS7
VSS50

DQ62

DQ63
VSS52

EVENT#

VTT2

DQ4
DQ5

DQ6
DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA
SCL

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78

A15

80

A14

82
84
86

A7

88
90

A6

92

A4

94
96

A2

98

A0

100
102
104
106
108
110
112
114

S0#

116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

G2

4

DD R _B _D 4
DD R _B _D 5

DD R _B _ DQS #0
DD R _B _ DQS 0

DD R _B _D 6
DD R _B _D 7

DD R _B _D 12
DD R _B _D 13

DD R _B _D M1
DR AMR ST#

DD R _B _D 14
DD R _B _D 15

DD R _B _D 20
DD R _B _D 21

DD R _B _D M2
DD R _B _D 22

DD R _B _D 23
DD R _B _D 28

DD R _B _D 29
DD R _B _ DQS #3

DD R _B _ DQS 3
DD R _B _D 30

DD R _B _D 31

DD R _C KE 3 _D IMMB
DD R _B_MA 15

DD R _B_MA 14
DDR _B_MA11

DD R _B _M A7
DDR_B_MA6

DD R _B _M A4
DD R _B _M A2

DD R _B _M A0
M_ CLK _D DR3

M_ CLK _D DR# 3
DD R _B _B S1

DD R _B _ RAS #
DD R _C S2 _ DIM MB#

M_ O DT3

V_ D DR _M CH_ RE F
DD R _B _D 36

DD R _B _D 37
DD R _B _D M4
DD R _B _D 38

DD R _B _D 39
DD R _B _D 44

DD R _B _D 45
DD R _B _ DQS #5

DD R _B _ DQS 5
DD R _B _D 46

DD R _B _D 47
DD R _B _D 52

DD R _B _D 53
DD R _B _D M6
DD R _B _D 54

DD R _B _D 55
DD R _B _D 60

DD R _B _D 61
DD R _B _ DQS #7

DD R _B _ DQS 7
DD R _B _D 62

DD R _B _D 63
P M_EX TTS# 1_R

SM B _DATA_S 3
SM B _CL K_S 3

4

0. 65 A

0. 65 A @0.7 5V

@0. 75V

0. 65 A0. 65 A

@0. 75V@0. 75V

DR AMR ST# <6, 17>

DD R _C KE 3 _DI MMB <8>

M_ CLK _DD R3 <8>
M_ CLK _DD R#3 <8>

DD R _B _BS 1 <8>
DD R _B _R AS# <8>

DD R _C S2 _D IMMB# <8>
M_ ODT2 <8>

M_ ODT3 <8>

PM_EXT TS#1 _R <6, 17>

SM B_ DATA_S3 <1 2,1 7,19, 30>
SM B_ CLK _S3 <1 2,1 7,1 9, 30>

+0 .75VS

3

DD R _B _D QS# [0..7 ]<8>
DD R _B _D [0..6 3]<8>
DD R _B _D M[0 ..7 ]<8>
DD R _B _D QS [0. .7]<8>
DD R _B _MA [0. .15 ]<8>

Layout Note:
Pl ace near JP5

1

1

C2 23

2

2

@

@

10 U_0 603_6 .3V 6M

+V REF_CA

1

1

C2 35

C1 060

2

2

0. 1U_04 02_16 V4Z

2. 2U_06 03_6. 3V4 Z

Layout Note:
Place near JP5.203 & JP5.204

+0. 75 VS

R8 85

1 2

0_ 040 2_5%

1 2

R8 99 0_ 0402_ 5%M 3@

+1. 5V

1

1

1

C2 27

C2 26

C2 25

C2 24

2

10 U_0 603_6 .3V 6M

1

1

C2 37

2

2

1U _0402 _6.3V6K

2

2

10 U_0 603_6 .3V 6M

10 U_0 603_6 .3V 6M

1

1

C2 38

C2 40

C2 39

2

2

1U _0402 _6.3V6K

1U _0402 _6.3V6K

1U _0402 _6.3V6K

2

+V _DD R_ C PU_REF+V RE F_ D Q_DIMMB

+V _DD R_ C PU_REF 1

1

1

C2 28

C2 29

2

2

10 U_0 603_6 .3V 6M

10 U_0 603_6 .3V 6M

1

1

C2 30

2

10 U_0 603_6 .3V 6M

10 U_0 603_6 .3V 6M

1

C2 31

C2 32

2

2

0. 1U_04 02_16 V4Z

0. 1U_04 02_16 V4Z

1

1

C2 34

C2 33

2

2

0. 1U_04 02_16 V4Z

0. 1U_04 02_16 V4Z

1

DDR3 SO-DIMM B
REVERSE

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Tit le

Size Do c um en t N umb er R e v

Da te : She et o f

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

Ca lp ella DIS L A4743P

1

18 49Monda y, Apr il 13, 2009

0. 1

5

4

3

2

1

+1.0 5VS _CK505

80mA

+3V S_CK505

250mA

D

OT96

OK

CLK_BUF_DOT 96<12>
CLK_BUF_DOT 96#<12>

DMI

27M_CLK<24>

27M_SSC<24>

CL K_DMI<12>

CLK_DMI#<12>

CL K_ BUF_CKSSCD<12>

CL K_BUF_ CKSSCD#<12>

27M

OK

OK

D D

OK

CKSSCD

CLK_BUF_DOT 96
CLK_BUF_DOT 96#

27M_CLK L_27M_CLK
27M_SSC L_2 7M_SSC

CL K_ DMI
CL K_DMI#

CL K _BUF_CK SSCD
CL K_ BUF_CKSSCD#

R213 33_ 0402_5%
R214 33_ 0402_5%

R216 33_ 0402_5%@
R217 33_ 0402_5%@

R221 33_ 0402_5%
R223 33_ 0402_5%

R219 33_ 0402_5%
R220 33_ 0402_5%

1 2
1 2

1 2
1 2

12
12

12
12

L_CLK_BUF_ DOT96 CLK_14M_PCH
L_CLK_BUF_ DOT96#

L_CLK _DMI
L_CLK_DMI#

L_CLK _BUF_CK SSCD
L_CLK _BUF_CK SSCD#

CPU_ STOP#

U3

1

VDD_DOT

2

VSS_DOT

3

DOT_96

4

96MHz

DOT_96#

5

VDD_27

6

27MHZ

7

27MHZ_SS

8

VSS_27

9

VSS_SATA

10

SRC_1/SATA

11
12
13
14
15
16

SLG8SP 585 VTR_QFN32_5X5

SRC_1#/SATA#
VSS_SRC
SRC_2

100MHz

SRC_2#
VDD_SRC_IO
CPU_STOP#

100MHz

REF_0/CPU_SEL

CKPWRGD/PD#

133MHz

VDD_CPU_IO

TGND

33

Number of Clock Outputs

Output

133MHz
SRC(100MHz_SS)
SRC/SATA(100MHz)
REF(14.318MHz)
DOT_CLK(96MHz) 1

C C

27MHz

27MHz_SS

PIN 30 CPU_1CPU_0

0(default)

1

CPU_SEL During CK_PEWGD Latch Pin1

+3VS

@

R244 10K _04 02_5%

1 2

R247 10K _04 02_5%

1 2

Number

2

SLG8SP585： pin8 is GND (for DELL、HP)
SLG8SP587： pin8 is 48MHz (For ABO or 030)

1
1
1

2

C259

1
1

133MHz

100MHz

133MHz

100MHz

RE F_0/CPU_SE L

18P _04 02_50V8J

CPU_ STOP#

1

CLK_XT AL_OUT
CLK_XT AL_IN

Y 3

1 2

14.318MHZ_16PF_7A14300083

2

C260
18P _04 02_50V8J

Vendor suggests 22pF

1

R234 10K _0402_5%

1 2

+3V S_CK505

CLK_EN#

CLK_EN#<46>

2

SCL
SDA

VDD_REF

XTAL_IN

XTAL_OUT

VSS_REF

VDD_CPU

CPU_0

CPU_0#

VSS_CPU

CPU_1

CPU_1#

VDD_SRC

+3V S_CK505

12

13

D

G

S

+1.0 5VS _CK505

+3V S_CK505

32
31
30
29
28
27
26
25

24
23
22
21
20
19
18
17

R607
10K _04 02_5%

CK PWR GD

Q30

2N7002_SOT23-3

SMB_CLK_S3
SMB_DATA_S3
RE F_0/CPU_SE L

CLK_XTAL_IN
CLK_XTAL_OUT

R_ CK P WRGD

L_CLK_BUF_ BCLK
L_CLK_BUF_ BCLK#

SMB _CLK_S3 <12,17,18,30>

SMB _DATA_S3 <12,17,1 8,30>

R222 33_ 0402_5%

R226 0_ 0402_5%@
R237 0_ 0402_5%

R224 33 _0402_5%
R225 33 _0402_5%

+V CCP

+3VS

1 2
1 2

1 2
1 2

+3V S_CK505

R212

1 2

0_0 805_5%

R218

1 2

0_0 805_5%

12

1

2

+1.0 5VS _CK505

1

2

CK PWR GD

1

C246

C245

2

10U_0805_10V4Z

Place close to U51

1

C253

C252

2

10U_0805_10V4Z

CLK_14M_PCH

VGATE <1 3,46>

CLK_BUF_BCLK <12>
CLK_BUF_BCLK# <12>

1

C247

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C254

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C808 1 0P_ 040 2_50V8J@

1 2

CLK_14M_PCH <12>

BCLK

1

1

C248

2

2

0.1U_0402_16V4Z

C249

OK

1

4M

OK

1

C250

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Routing the trace at least 10mil

B B

A A

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2007/08/28 2006/03/10

3

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

Da te: Sheet

2

Compal Electronics, Inc.

Clock Generator CK505

Ca lpella DI S LA4743P

19 49Monday, April 13, 2009

1

0.1

o f

A

1 1

CRT Connector

+5VS +5VS

C267

0.1U_0402_16V4Z

1 2

1

5

U5
SN74AHCT1G1 25GW_SOT353-5

2 2

CRT_ HSYNC<22>

CRT_VSY NC<22>

CRT_ HS YNC

CRT_ VS YNC

P

A2Y

G

3

4

OE#

B

C268

0.1U_0402_16V4Z

1 2

R815 10K _04 02_5%

HS YNC_G_A

1

5

P

A2Y

G

3

VS Y NC_G_A D_ VS Y NC

4

OE#

U6
SN74AHCT1G1 25GW_SOT353-5

12

R269 0_0 603_5%

1 2

R274 0_0 603_5%

1 2

R ED

GR EEN

BLUE

D_ HS YNC

1

C269

@

5P_040 2_50V8C

2

C

D9

2 1

RB491D_ SC59-3

1

C270

@

5P_040 2_50V8C

2

F1

1.1A_6VDC_FUS E

4.7K_0402_5%

D_ DD CDATA

D_ DDCCL K

21

W=40mils

0.1U_0402_16V4Z

JC RT1

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUY IN_070546FR015S26 3ZR

C ONN@

+CRTV DD +CRTV DD

12

R270

R271

4.7K_0402_5%

+CRT VDD+RCRT_VCC+5VS

1

2

C266

16
17

12

6 1

2N7002DW-7-F_S OT363-6

D

2

Q2A

2N7002DW-7-F_S OT363-6

3

5

Q2B

BLUE
GR EEN
R ED

D6

DGPU_EDIDSEL#

R272

4.7K_0402_5%

4

1

2

+3VS

12

+3V S_NV

3

DAN2 17T 146 _SC59-3

12

R273

4.7K_0402_5%

D7

1

2

3

DGPU_EDIDSEL#

I_ CRT_DDC_DATA

I_ CRT_DDC_CLK

D8

DAN2 17T 146 _SC59-3

10K _04 02_5%

E

Place close to
JCRT1

1

2

3

DAN2 17T 146 _SC59-3

+3VS

UMA @

R901

+3VS

1 2

I_ CRT _DDC_ DATA <13>

I_ CRT_DDC_CLK <13>

DGPU_EDIDSEL EDIDSE L

3 3

CRT Termination/EMI Filter

M_RED<22>

M_GREEN<22>

M_B LUE<22>

4 4

A

12

12

R275

150 _0402_1%

C_ RE D

C_ GRN

12

R276

150 _0402_1%

1

1

C271

C272

@

R277

150 _0402_1%

@

2

2

22P _04 02_50V8J

L8 HLC0 603CSCCR11JT_0603

1 2

L9 HLC0 603CSCCR11JT_0603

1 2

L10 HLC060 3CSCCR11 JT_0603

1 2

1

C273

@

2

22P _04 02_50V8J

22P _04 02_50V8J

B

1

1

C274

2

2

10P _04 02_50V8J

R ED

GR EEN

BLUEC_ BL U

1

C276

C275

2

10P _04 02_50V8J

10P _04 02_50V8J

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/07/26

R900 0_0 402_5%

1 2

SG@

D_ DD CDATA

D_ DDCCL K

DGPU_EDIDS EL#<14>

Compal Secret Data

Deciphered Date

2

6 1

SG@

Q11A

2N7002DW-7-F_S OT363-6

ED IDS EL

DGPU_EDIDSEL#

D

4.7K_0402_5%

5

3

Q11B

+3VS

SG@

R902
10K _0402_5%

1 2

DGPU_EDIDSEL

3

SG@

Q12B
2N7002DW-7-F_S OT363-6

4

4

SG@

2N7002DW-7-F_S OT363-6

5

12

12

SG@

R878

Title

Size Do cument Number Re v

Da te: Sheet o f

SG@

R879

4.7K_0402_5%

D_ CRT_DDC_DATA <24>

EDIDSEL <22>

D_ CRT_DDC_CL K <24>

Q12A

2

2N7002DW-7-F_S OT363-6

6 1

Compal Electronics, Inc.

CRT Connector

Ca lpella DI S LA4743P

20 49Monday, April 13, 2009

E

0.1

5

INVPWR_B ++L CD VDD+3VS

D D

1

12

C277

2

680 P_0 402_50V7K

USB 20_P4<14>
USB 20_N4<14>

C C

12

C278

680 P_0 402_50V7K

USB 20_P4

C279

680 P_0 402_50V7K

USB 20_N4

LVDS CONN & USB Camera + Dig Mic

JLVDS1

+3VS

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

GND41GND

ACE S_8 8242-4001

C ONN@

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

4

LVDS_A2­LVDS_A2+
LVDS_A1­LVDS_A1+
LVDS_A0­LVDS_A0+
LVDS_A CLK­LVDS_A CLK+

DM IC_DAT
DMIC_CLK
+3V _LOGO
LVDS_INV_P WM
BKOFF#

LV DS _EDID_CL K
LVDS_E DID_DATA

R284

2.2K_0402_5%

LV DS _EDID_CL K
LVDS_E DID_DATA

R281

1 2

100 _08 05_5%

+USB_CA M

EMI request.

+3VS

1 2

1

C286
680 P_0 402_50V7K

2

R285

2.2K_0402_5%

1 2

LVDS_A2- <22>
LVDS_A2+ <22>
LVDS_A1- <22>
LVDS_A1+ <22>
LVDS_A0- <22>
LVDS_A0+ <22>
LVDS_A CLK- <22>
LVDS_A CLK+ <22>

DMIC_DA T <33>

DMIC_CLK <33>

+5VS

LVDS_INV_P WM <22>

BKOFF# <37>

LV DS_EDID_CLK <22>
LVDS_E DID_DATA <22>

Must close JLVDS1pin 24、、、、26

DMIC_CLK
DM IC_DAT

1

C287

@

220 P_0 402_25V8J

2

3

0.1U_0402_16V4Z

02/13 Reserve

BKOFF#

1

C288

@

220 P_0 402_25V8J

2

C281

1

2

@

10K _0402_5%

1 2

1

C282

0.1U_0402_16V4Z

2

R282

02/20 Change to 0805 size

12

R278

470 _08 05_5%

61

2

2N7002DW-7-F_S OT363-6
Q3A

Limited Current < 1A

I_ ENAVDD<13>

I_ E NAVDD

10K _0402_5%

D_ ENAVDD<24>

@

L11 0_0 805_5%

L12
FBMA-L11-2 012 09-221LMA30T_0805

2

12

R283

2.2K_0402_5%

1 2

1 2

R279

1M_0402_5%

5

SG@

R880

1

C280

4.7U_0805_10V4Z

12

SG@

Q33
2N7002_SOT23-3

+L CDVDD

Q13

SI2301BDS-T1-E3_SOT23-3

1 3

1

2

D

C284

0.047U_0402_16V7K

01/03 Change to 0.047u to meet T1 timing

+5V ALW+ LC DVDD+L CDVDD

12

R280

100 K_0 402_5%

3

Q3B

4

2N7002DW-7-F_S OT363-6

13

D

2

G

S

1 2

INVPWR_B+B+

+3VS

S

G

2

1

C283

4.7U_0805_10V4Z

2

0308_Reserve L10 and install L11.

B B

USB Camera

+5VS

R288

0_0 402_5%

1

C290

10U_0805_6.3V6M

A A

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

+USB_CAM is +3.9VS, R286:215K; R287:100Kohm

Compal Secret Data

Deciphered Date

2

2

1 2

U7

1

IN

2

GND

3

SHDN

G916-39 0T1 UF_SOT23-5

BYP

OUT

5

4

+USB_CAM=1.25(1+R1091/R1093)

Title

Size Do cument Number Re v

Da te: Sheet o f

Compal Electronics, Inc.

LCD CONN.

Ca lpella DI S LA4743P

12

R286
215 K_0603_1%

12

R287
100 K_0402_1%

1

+USB_CA M

1

2

1

C981

C289

@

2

47P _04 02_50V8J

10U_0805_6 .3V6M

21 49Monday, April 13, 2009

0.1

5

4

3

2

1

LVDS Switch

U3 5

D_ L VDS_A0 +<25>

D_ L VDS_A0 -<25>

D_ L VDS_A1 +<25>

D_ L VDS_A1 -<25>

D_ L VDS_A2 +<25>
D_ L VDS_A2 -<25>
D_ L VD S_ACLK+< 25>

D D

D_ L VD S_ACLK-<25>

I_ L VDS _A0 +<1 3>

I_ LV DS_ A0-<13>

I_ L VDS _A1 +<1 3>

I_ LV DS_ A1-<13>

I_ L VDS _A2 +<1 3>

I_ LV DS_ A2-<13>

I_ L VD S_ACLK+<13>

I_ L VDS _ACLK-< 13>

C C

D_ L VD S_A0+
D_ L VD S_A0­D_ L VD S_A1+
D_ L VD S_A1­D_ L VD S_A2+
D_ L VD S_A2­D_ L VD S_ ACL K+
D_ L VDS_ACLK-

I_ L VDS _A0 +
I_ L VDS _A0 ­I_ L VDS _A1 +
I_ L VDS _A1 ­I_ L VDS _A2 +
I_ L VDS _A2 ­I_ L VDS_ACLK+
I_ L VD S_ACLK-

48

0B1

47

1B1

43

2B1

42

3B1

37

4B1

36

5B1

32

6B1

31

7B1

22

8B1

23

9B1

46

0B2

45

1B2

41

2B2

40

3B2

35

4B2

34

5B2

30

6B2

29

7B2

25

8B2

26

9B2

52

NC

5

NC

54

NC

51

NC

57

Thermal_GND

TS 3D V 52 0E RHUR_Q FN5 6_1 1X5 ~D

S G@

VCC
VCC
VCC
VCC
VCC
VCC
VCC

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

SEL

CRT Switch

+3 VS

B B

0. 1U_04 02_16 V4Z

SG @

1

C1 011

2

0. 1U_04 02_16 V4Z

0. 1U_04 02_16 V4Z

1

C1 012

2

SG @

1

C1 013

2

SG @

4
10
18
27
38
50
56

2
3
7
8
11
12
14
15
19
20

17
1

6
9
13
16
21
24
28
33
39
44
49
53
55

0. 1U_04 02_16 V4Z

LV D S_A0+
LV D S_A0­LV D S_A1+
LV D S_A1­LV D S_A2+
LV D S_A2­LV D S_ ACL K+
LV D S_ACLK-

SG @

1

C1 014

2

+3 VS

R7 90

1 2

0_ 040 2_5%

SG @

1

2

C1 004

0. 1U_04 02_16 V4Z

SG @

DG P U_ SE LEC T#

C1 005

4. 7U_08 05_10 V4Z

SG @
LV DS_A0 + <21>
LV DS_A0 - < 21>
LV DS_A1 + <21>
LV DS_A1 - < 21>
LV DS_A2 + <21>
LV DS_A2 - < 21>
LV D S_ACLK+ <21>
LV D S_ACLK- <21>

DG P U_ SEL ECT# <14>

DP ST _ PWM< 13>

D_ I NV _P WM< 24>

I_ E DI D_DATA<13>

I_ E DI D_CLK< 13>

2N 7002D W-7 -F_ SOT 363 -6

LVDS I2C switch

ED IDS EL

2

D_ E DI D_ DATA<24> LV D S_ ED ID _DATA <21>

R9 19 0_ 040 2_5%

1 2

SG @

2N 7002D W-7 -F_ SOT 363 -6

Q3 4A

61

LV D S_ ED ID_D ATA

5

LV D S_ ED ID_C LK

3

D_ E DI D_ CLK<24>

R9 20 0_ 040 2_5%

1 2

SG @

R8 91

4.7K_040 2_5%

61

SG @

Q3 6A

2

5

4

Q3 4B

SG @

2N 7002D W-7 -F_ SOT 363 -6

+3 VS

S G@

R8 89

4.7K_040 2_5%

1 2

1 2

61

S G@

Q3 7A
2N 70 02 DW- 7-F_SO T36 3-6

2

3

SG @

4

Q3 6B
2N 7002D W-7 -F_ SOT 363 -6

LVDS PWM switch

R8 90 0_ 0402_ 5%@

DP ST _ PWM LV D S_ I NV_ PWM

12

U MA @

R8 92 0 _04 02_5%

ED IDSE L <20>

LV D S_ ED ID_ CLK <2 1>

IN V_P WM <37 >

LV D S_ IN V_P WM <21 >

12

Backlight Enable

SG @

R8 83

4.7K_040 2_5%

61

SG @

2N 70 02 DW- 7-F_SO T36 3-6

IG P U_ BKLT_EN<1 3>

DG P U_ BKL _EN<24 >

Q3 5A

SG @

R8 86

10 K_0 402 _5 %

2

5

1 2

UMA ONLY (LVDS)

I_ L VDS _A0 ­I_ L VDS _A0 +

I_ L VDS _A1 ­I_ L VDS _A1 +

I_ L VDS _A2 + LV D S_A2+
I_ L VDS _A2 -

I_ L VD S_ACLK­I_ L VDS_ACLK+

+3 VS

1 2

1 2

3

5

3

4

S G@

Q3 5B

4

2N 70 02 DW- 7-F_SO T36 3-6

R7 99 0 _04 02 _5%

RP 36

RP 37

RP 38

RP 39

SG @

R8 82

4.7K_040 2_5%

EN B KL

SG @

Q3 7B
2N 7002D W-7 -F_ SOT 363 -6

UM A@

1 2

14
23

14
23

23
14

14
23

LV D S_A0-

LV D S_A0+

0_ 040 4_4P2 R_5 %U MA @

LV D S_A1-

LV D S_A1+

0_ 040 4_4P2 R_5 %U MA @

LV D S_A2-

0_ 040 4_4P2 R_5 %U MA @

LV D S_ACLK-

LV D S_ ACL K+

0_ 040 4_4P2 R_5 %U MA @

EN BK L <3 7>

EN B KLIG P U_ BKL T_E N

U4 3

+3 VS

D _ RE D<24 >
D_ G RE EN<24>
D_ B LU E<24 >
D_ C RT _H SYN C< 24>
D_ C RT _V SY NC<24 >

I_ R ED<13 >
I_ G RE EN<13>
I_ B LUE< 13>
I_ C RT _H SYNC< 13>
I_ C RT _V SY NC<13 >

A A

5

1

VDD

4

VDD

9

VDD

19

VDD

24

A0

22

B0

18

C0

17

D0

14

E0

23

A1

21

B1

16

C1

15

D1

13

E1

PI 3V5 12QE_QSO P24

SG @

GND
GND
GND
GND

DG P U_ SE LEC T#

12

SEL

M_ RED

2

YA

M_ G RE EN

5

YB

M_ B LUE

6

YC

C R T_ HSY NC

8

YD

CR T_ V SY NC

11

YE

3
7
10
20

M_ RED <20>
M_ G REE N <20>
M_ BL UE <20>

C RT_ HS YN C < 20>
CR T_ V SY NC <20>

4

UMA ONLY (CRT)

I_ R ED
I_ G R EEN
I_ B LU E
I_ C RT _H SYN C
I_ C RT _V S YNC

R8 93 0 _04 02_5%U MA@
R8 94 0 _04 02_5%U MA@
R8 95 0 _04 02_5%U MA@
R8 96 0 _04 02_5%U MA@
R8 97 0 _04 02_5%U MA@

12
12
12
12
12

M_ RED
M_ G RE EN
M_ B LUE
C R T_ HSY NC

CR T_ V SY NC

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/09/29 2007/09/29

Compal Secret Data

Deciphered Date

2

Tit le

Size Do c um en t N umb er R e v

Cu s to m

Da te : She et o f

Compal Electronics, Inc.

LVDS Switch

Ca lp ella DIS L A4743P

1

22 49Monda y, Apr il 13, 2009

0. 1

5

Par ade

ST

R8 33

R837

R836

R840

R838

R842

D D

R849

R850

X X X

0 ohm

4.7K ohmX

4.7K ohm

X

X

3.9K ohm499 ohm

0 ohmXX X

C1052

R853

0 ohm 0 ohm X

R855

X X 4.7K ohm

R857

X X 4.7K ohm

R858

0 ohm 0 ohm

X XX4.7K ohm

R851

0 ohm 0 ohm

R854

0 ohm 0 ohm

R843

X XX4.7K ohm

R844

0 ohm 4.7K ohm

R839

R834

X X X

0 ohm

R841

R835

X X

C667 0.1uF 1uF

C C

B B

A A

R862

R867

V

V

HDMI_C_CLK-<25>

HDMI_C_CLK+<25>

HDMI_ C_TX0-<25>

HDMI_ C_TX0+<25>

HDMI_ C_TX1-<25>

HDMI_ C_TX1+<25>

HDMI_ C_TX2-<25>

HDMI_ C_TX2+<25>

Par ade
8171

8101T

0 ohm 4.7K ohm

X

X 4.7K ohm

X

4.7K ohm

X X

499 ohm

X 2.2uF

X

X

X X

4.7K ohm
1uF

X

X

X

X

SG@

C375 0.1U_0402_16V4Z

SG@

C376 0.1U_0402_16V4Z

SG@

C377 0.1U_0402_16V4Z

SG@

C378 0.1U_0402_16V4Z

SG@

C379 0.1U_0402_16V4Z

SG@

C380 0.1U_0402_16V4Z

SG@

C382 0.1U_0402_16V4Z

SG@

C381 0.1U_0402_16V4Z

5

R571

@

2.2K_0402_5%

HDMIDAT_VGA<25>

HDMICLK _VGA<25>

EQUALIZATION SETTING:
[PC1,PC0]=00,8dB
[PC1,PC0]=01,4dB (Recommanded)
[PC1,PC0]=10,12dB
[PC1,PC0]=11,0dB

R859 0_0 402_5%@

12

12

12

12

12

12

12

12

+3V S_NV

HDMICLK-

HDMICLK+

R866

@

R868 0_0 402_5%@

HDMI_ TX_0-

HDMI_ TX_0+

R869

@

R870 0_0 402_5%@

HDMI_ TX_1-

HDMI_ TX_1+

R871

@

R872 0_0 402_5%@

HDMI_ TX_2-

HDMI_ TX_2+

R873

@

HDMICLK­HDMICLK+
HDMI_ TX_0­HDMI_ TX_0+
HDMI_ TX_1- HDMI_DE TECT
HDMI_ TX_1+
HDMI_ TX_2­HDMI_ TX_2+

12

SG@

SG@

R734

R733

499 _04 02_1%

499 _04 02_1%

13

D

SG@

2

2N7002_SOT23-3

G

S

L28

1

1

4

4

L29

1

1

4

4

L30

1

1

4

4

L31

1

1

4

4

12

499 _04 02_1%

Q31

+3V S_NV

12

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

12

SG@

R735

499 _0402_1%

R572

@

2.2K_0402_5%

1 2

4

R576 0_0 402_5%@

2

2

WCM-2012-90 0T_0805

3

3

0_0 402_5%

2

2

WCM-2012-90 0T_0805

3

3

0_0 402_5%

2

2

WCM-2012-90 0T_0805

3

3

0_0 402_5%

2

2

WCM-2012-90 0T_0805

3

3

0_0 402_5%

12

SG@

SG@

R736

R737

499 _04 02_1%

4

SG@

5

Q5B
2N7002DW-7-F_S OT363-6

3

1 2

HDMID_ CTRL DATA<13>
HDMID_CT RLCL K<13>

HDMI_R_CL K-

HDMI_R_CL K+

HDMI_ R_TX0-

HDMI_ R_TX0+

HDMI_ R_TX1-

HDMI_ R_TX1+

HDMI_ R_TX2-

HDMI_ R_TX2+

12

SG@

R738

499 _0402_1%

4

2.2K_0402_5%

12

SG@

R739

499 _04 02_1%

+3V S_NV

SG@

Q5A

2

2N7002DW-7-F_S OT363-6

61

R575 0_0 402_5%@

1 2

+3V S_LS

1 2

12

12

UMA @

12

UMA @

R848

R847

2.2K_0402_5%

UMA@

R850 0_0 402_5%

1 2

1 2

C1052

@

2.2U_0603_6.3V4Z

12

SG@

R740

499 _0402_1%

+3V S_LS

R838

@

4.7K_0402_5%
R842

@

0_0 402_5%

HDMI_DE T<24>

3

+3V S_LS +3VS_LS

TMDSD_DATA2#<13>
TMDSD_DATA2<13>

TMDSD_CLK#<13>

HD MIDA T

HDMICLK

R836

@

12

4.7K_0402_5%

UMA @

R840

1 2

4.7K_0402_5%

UMA @

R853 0_0 402_5%

+3V S_LS

+3V S_LS

10K _0402_5%

1 2

R855 4.7K_0402_5%@

1 2

R857 4.7K_0402_5%@

1 2
UMA @

R858 0_0 402_5%

1 2

4

12

SG@

R924

DGPU_ HPD_ INT#<14>

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

TMDSD_CLK<13>

+3VS_LS

R833

+3VS_LS

UMA @

R849 4.3K_0402_1%

+3VS

Y

@

4.7K_0402_5%

UMA @

12

R837

1 2

0_0 402_5%

+3V S_LS

12

TMDS_B_HPD

HDMICLK+
HDMICLK-

5

HDMI_DE TECT

2

P

B

DGPU _PWR_E N

1

A

G

U51

3

NC7S Z08 P5X _NL_SC70-5

SG@

2N7002DW-7-F_S OT363-6

0.5P_0402_50V8B

HDMI_ TX_2+ TMDS_B_HPD
HDMI_ TX_2-

3

2007/08/28 2006/03/10

3

12

C1053

@

5

Q19B

SG@

UMA @

48

45

47

U47

1

GND

2

VCC3V

3

FUNCTION1

4

FUCNTION2

5

GND

6

ANALOG1(REXT)

7

HPD_SOURCE

8

SDA_SOURCE

9

SCL_SOURCE

10

ANALOG2

11

VCC3V

12

GND

49

thm_pad

R860

@

1 2

68_ 0402_5%

C1055

@

0.5P_0402_50V8B

46

IN_D4-

VCC3V

IN_D4+

IN_D3+

PC0
PC1

OUT_D4+13OUT_D4-14VCC3V15OUT_D3+16OUT_D3-17GND18OUT_D2+19OUT_D2-20VCC3V21OUT_D1+22OUT_D1-23GND

R863

@

1 2

68_ 040 2_5%

HDMI Connector

DGPU _PW R_EN <14,39,45 ,47>

D35

SKS10-04AT_TSMA

4

Compal Secret Data

2 1

Deciphered Date

42

44

43

GND

IN_D3-

R579

1 2

10K _04 02_1%

12

R580
100 K_0 402_1%

IN_D2+

2

41

IN_D2-

+3V S_LS+3VS_LS

2

40

VCC3V

1 2

68_ 0402_5%

UMA@

R832

1 2

TMDSD_DATA1 <13>
TMDSD_DATA1# <13>

TMDSD_DATA0 <13>
TMDSD_DATA0# <13>

39

38

37

GND

IN_D1-

IN_D1+

R864

@

0.5P_0402_50V8B

L32 FBML10160808121LMT_0603

1 2

330 P_0 402_50V7K

36

GND

35

FUNCTION4

34

FUNCTION3

33

VCC3V

32

DDC_EN

31

GND

30

HPD_SINK

29

SDA_SINK

28

SCL_SINK

27

GND

26

VCC3V

25

OE*

S IC STHDLS 101TQT R QFN 48P HDMI SHIFTER

24

R861

@

1 2

68_ 0402_5%

HDMI_ TX_1-

C1056

@

HDMI_ TX_1+

HD MIDA T
HDMICLK

1

C668

2

0_0 603_5%

R834 4.7K_0402_5%@
R835 4.7K_0402_5%@

UMA @

R839 0_0 402_5%

UMA @

R841 0_0 402_5%

R843 0_0 402_5%U MA@
R844 0_0 402_5%@
R845 4.7K_0402_5%UMA@
R846 0_0 402_5%@

HDMI_DE TECT
HD MIDA T
HDMICLK

R851 4.7K_ 0402_5%@
R854 0_0 402_5%

+3V S_LS

UMA@

R856 0_0 402_5%

UMA @

HDMI_ TX_0-

C1054

@

HDMI_ TX_0+

0.5P_0402_50V8B

TMDS_B_HPD#<13>

RB411DT 146 _SOT23-3

R578

R577

1.5K_0402_5% 1 2

HDMI_R_CL K­HDMI_R_CL K+
HDMI_ R_TX0­HDMI_ R_TX0+
HDMI_ R_TX1­HDMI_ R_TX1+
HDMI_ R_TX2­HDMI_ R_TX2+

Title

HDMI LS & Conn.

Size Do cument Number Re v

Cu st om

Ca lpella DI S LA4743P

Da te: Sheet o f

1

1 2

D34

1.5K_0402_5% 1 2

2

UMA @

1

C1048

12
12

12
12
12

12
12
12

12

21

@

+5V S_HDMI

0.01U_0402_16V7K

C665

@

1

1

UMA @

UMA @

2

2

C1050

C1049

12

2N7002DW-7-F_S OT363-6

1

2

C666

22N_0402_16V7K

18
16
15
19

12
10

9
7
6
4
3
1

0.1U_0402_10V6K

0.1U_0402_10V6K

+3V S_LS
+3V S_LS

+3V S_LS
+3V S_LS

+3VS_LS

HDMI_DE TECT

Q19A

SG@

+3V S_LS

12

UMA @

R862
20K _04 02_5%

UMA @

R865

12

0_0 402_5%

UMA @

R867

7.5K_0402_1%

+5VS_HDMI+5VS

22N_0402_16V7K

1

1

C667

2

2

0.1U_0402_16V4Z

JH DMI1

+5V
SDA
SCL
HP_DET

CK­CK+
D0­D0+
D1­D1+
D2­D2+

DDC/CEC_GND

SUY IN_100042MR019S153ZL

C ONN@

C1051

+3V S_LS

2

CEC

Reserved

GND
GND
GND
GND
GND
GND
GND
GND

1

UMA @

2

12

61

12

Compal Electronics, Inc.

23 49Monday, April 13, 2009

1

+3V S_LS+3VS

10U_0805_6 .3V6M

R852
10K _0402_5%

UMA@

13
14

2
5
8
11
20
21
22
23
17

0.1

1

U8 A

P EX_RST#

AE12

AF12
AG12
AG13

AF13

AE13

AE15

AF15
AG15
AG16

AF16

AE16

AE18

AF18
AG18
AG19

AF19

AE19

AE21

AF21
AG21
AG22

AF22

AE22

AE24

AF24
AG24

AF25
AG25
AG26

AF27

AE27
AD10

AD11
AD12
AC12

AB11

AB12
AD13
AD14
AD15
AC15

AB14

AB15
AC16
AD16
AD17
AD18
AC18

AB18

AB19

AB20
AD19
AD20
AD21
AC21

AB21

AB22
AC22
AD22
AD23
AD24

AE25

AE26

AB10
AC10

AF10

AE10
AG10

AD9
AE9

N10M-GLM- S-A1_ BGA533

SG @

PC IE_CTX _GR X_P 15<7>
PC IE_CTX _GR X_N 15<7>
PC IE_CTX _GR X_P 14<7>
PC IE_CTX _GR X_N 14<7>
PC IE_CTX _GR X_P 13<7>
PC IE_CTX _GR X_N 13<7>
PC IE_CTX _GR X_P 12<7>
PC IE_CTX _GR X_N 12<7>
PC IE_CTX _GR X_P 11<7>
PC IE_CTX _GR X_N 11<7>

A A

PC IE_CTX _GR X_P 10<7>
PC IE_CTX _GR X_N 10<7>
PC IE_CTX _GR X_P 9<7>
PC IE_CTX_G RX_ N9<7>
PC IE_CTX _GR X_P 8<7>
PC IE_CTX_G RX_ N8<7>
PC IE_CTX _GR X_P 7<7>
PC IE_CTX_G RX_ N7<7>
PC IE_CTX _GR X_P 6<7>
PC IE_CTX_G RX_ N6<7>
PC IE_CTX _GR X_P 5<7>
PC IE_CTX_G RX_ N5<7>
PC IE_CTX _GR X_P 4<7>
PC IE_CTX_G RX_ N4<7>
PC IE_CTX _GR X_P 3<7>
PC IE_CTX_G RX_ N3<7>
PC IE_CTX _GR X_P 2<7>
PC IE_CTX_G RX_ N2<7>
PC IE_CTX _GR X_P 1<7>
PC IE_CTX_G RX_ N1<7>
PC IE_CTX _GR X_P 0<7>
PC IE_CTX_G RX_ N0<7>

PC IE_CRX_G TX_P 15<7>
PC IE_CRX_G TX_N 15<7>
PC IE_CRX_G TX_P 14<7>
PC IE_CRX_G TX_N 14<7>
PC IE_CRX_G TX_P 13<7>
PC IE_CRX_G TX_N 13<7>
PC IE_CRX_G TX_P 12<7>
PC IE_CRX_G TX_N 12<7>
PC IE_CRX_G TX_P 11<7>
PC IE_CRX_G TX_N 11<7>
PC IE_CRX_G TX_P 10<7>
PC IE_CRX_G TX_N 10<7>

B B

PC IE_CRX_G TX_P 9<7>
PC IE_CRX_GTX_ N9<7>
PC IE_CRX_G TX_P 8<7>
PC IE_CRX_GTX_ N8<7>
PC IE_CRX_G TX_P 7<7>
PC IE_CRX_GTX_ N7<7>
PC IE_CRX_G TX_P 6<7>
PC IE_CRX_GTX_ N6<7>
PC IE_CRX_G TX_P 5<7>
PC IE_CRX_GTX_ N5<7>
PC IE_CRX_G TX_P 4<7>
PC IE_CRX_GTX_ N4<7>
PC IE_CRX_G TX_P 3<7>
PC IE_CRX_GTX_ N3<7>
PC IE_CRX_G TX_P 2<7>
PC IE_CRX_GTX_ N2<7>
PC IE_CRX_G TX_P 1<7>
PC IE_CRX_GTX_ N1<7>
PC IE_CRX_G TX_P 0<7>
PC IE_CRX_GTX_ N0<7>

CL K _P CIE _VG A< 12>
CL K _P CIE _VG A#<1 2>

DG P U_ HO LD_RST#<14>

C C

D D

+3 VS_NV

C7 76 0 .1U _04 02 _16 V4ZSG @
C7 77 0 .1U _04 02 _16 V4ZSG @
C7 78 0 .1U _04 02 _16 V4ZSG @
C7 79 0 .1U _04 02 _16 V4ZSG @
C7 80 0 .1U _04 02 _16 V4ZSG @
C7 81 0 .1U _04 02 _16 V4ZSG @
C7 82 0 .1U _04 02 _16 V4ZSG @
C7 83 0 .1U _04 02 _16 V4ZSG @
C7 84 0 .1U _04 02 _16 V4ZSG @
C7 85 0 .1U _04 02 _16 V4ZSG @
C7 86 0 .1U _04 02 _16 V4ZSG @
C7 87 0 .1U _04 02 _16 V4ZSG @
C7 88 0 .1U _04 02 _16 V4ZSG @
C7 89 0 .1U _04 02 _16 V4ZSG @
C7 90 0 .1U _04 02 _16 V4ZSG @
C7 91 0 .1U _04 02 _16 V4ZSG @
C7 92 0 .1U _04 02 _16 V4ZSG @
C7 93 0 .1U _04 02 _16 V4ZSG @
C7 94 0 .1U _04 02 _16 V4ZSG @
C7 95 0 .1U _04 02 _16 V4ZSG @
C7 96 0 .1U _04 02 _16 V4ZSG @
C7 97 0 .1U _04 02 _16 V4ZSG @
C7 98 0 .1U _04 02 _16 V4ZSG @
C7 99 0 .1U _04 02 _16 V4ZSG @
C8 00 0 .1U _04 02 _16 V4ZSG @
C8 01 0 .1U _04 02 _16 V4ZSG @
C8 02 0 .1U _04 02 _16 V4ZSG @
C8 03 0 .1U _04 02 _16 V4ZSG @
C8 04 0 .1U _04 02 _16 V4ZSG @
C8 05 0 .1U _04 02 _16 V4ZSG @
C8 06 0 .1U _04 02 _16 V4ZSG @
C8 07 0 .1U _04 02 _16 V4ZSG @

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

R6 89 2 00_ 0402_ 1%@

1 2

R6 91 2 .49 K_0 402_1 %SG @

1 2

R6 93 0 _04 02_5%SG@

1 2

R6 94 1 0K_ 040 2_ 5%SG @

1 2

PCIE_CRX_GTX_G_P15
PCIE_CRX_GTX_G_N15
PC IE_CRX_GTX_ G_P14
PC IE_CRX_GTX_ G_N14
PC IE_CRX_GTX_ G_P13
PC IE_CRX_GTX_ G_N13
PC IE_CRX_GTX_ G_P12
PC IE_CRX_GTX_ G_N12
PC IE_CRX_GTX_ G_P11
PC IE_CRX_GTX_ G_N11
PC IE_CRX_GTX_ G_P10
PC IE_CRX_GTX_ G_N10
PC IE_CRX_GTX_ G_P9
PC I E_C RX_ GTX _G_ N9
PCIE_CRX_GTX_G_P8
PCIE_CRX_GTX_G_N8
PCIE_CRX_GTX_G_P7
PCIE_CRX_GTX_G_N7
PCIE_CRX_GTX_G_P6
PCIE_CRX_GTX_G_N6
PCIE_CRX_GTX_G_P5
PCIE_CRX_GTX_G_N5
PCIE_CRX_GTX_G_P4
PCIE_CRX_GTX_G_N4
PCIE_CRX_GTX_G_P3
PCIE_CRX_GTX_G_N3
PCIE_CRX_GTX_G_P2
PCIE_CRX_GTX_G_N2
PCIE_CRX_GTX_G_P1
PCIE_CRX_GTX_G_N1
PCIE_CRX_GTX_G_P0
PCIE_CRX_GTX_G_N0

CLK_PC IE_VGA
CLK_PC IE_VGA#

2

Pa rt 1 of 5

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

PEX_REFCLK
PEX_REFCLK_N

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

PEX_TERMP
PEX_RST_N
PEX_CLKREQ_N

PCI EXPRESS

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11

GPIO

GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19

DACA_HSYNC
DACA_VSYNC

DACA_RED

DACA_BLUE

DACA_GREEN

DACA_VREF
DACA_RSET

DACB_HSYNC
DACB_VSYNC

DACB_RED

DACB_BLUE

DACB_GREEN

DACB_VREF
DACB_RSET

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

JTAG_TRST_N

TEST

TESTMODE

I2CA_SCL
I2CA_SDA

I2CB_SCL
I2CB_SDA

I2CC_SCL

I2CC_SDA

I2C DACADACB

I2CH_SCL
I2CH_SDA

I2CS_SCL
I2CS_SDA

XTAL_SSIN

XTAL_OUTBUFF

XTAL_OUT

XTAL_IN

CLK

20 P_0 402 _5 0V8

N1
G1
C1
M2
M3
K3
K2
J2
C2
M1
D2
D1
J3
J1
K1
F3
G3
G2
F1
F2

AD2
AD1

AE2
AD3
AE3

AF1
AE1

U6
U4

T5
R4
T4

R6
V6

AF3
AG4
AE4
AF4
AG3

AD25

R1
T3

R2
R3

A2
B1

A3
A4

T1
T2

D11
E9
E10
D10

SG @

C8 10

X TALI N

THERMAL ALERT
SINN_GPIO9

D _ RED
D_ B LUE
D_ G RE EN

DA CA_VREF
DA CA_ RS EF

JT A G_T CK
JT A G_T DI
JT A G_T DO
JT AG _TMS
JT A G_T RST

R9 03 10 K_0 402_5 %@
R6 88 10 K_0 402_5 %SG @

I2 C B_ SCL
I2 C B_ SDA

D_EDID_CLK
D_EDID_DATA

HD CP_SCL
HD CP_SDA

VG A _SM _CL K

27 M _SSC

X TALO UT
X TALI N

27 MHZ_18 PF_ X3S027 000FI1 H-X

1

2

C3 58 0 .1U _04 02 _16 V4ZSG @
R2 94 1 24_ 0402_ 1%S G@

1 2
1 2

SG @

1 3
2 4

HD MI _ DET <23 >
D_ I NV _P WM <22>
D_ E NA VD D < 21>
DG P U_ BK L_E N < 22>
GP U _VID0 <47>
GP U _VID1 <47>
GP U _VID2

D_ C RT _H SYN C < 22>
D_ C RT _V SY N C <2 2>

D _ RE D <22>
D_ B LU E <22>

D_ G RE EN <22 >

1 2
1 2

T64 TPC 12
T65 TPC 12
T66 TPC 12
T67 TPC 12

R6 90 10 K_0 402_5 %@

R6 92 10 K_0 402_5 %@

R6 95 0_ 0402_ 5%@

Y7

R3 27 0 _04 02_5%SG@
R3 28 0 _04 02_5%SG@

1 2
1 2

1 2

3

1 2
1 2

D_ C RT _D D C_C LK <20>
D_ C RT _D D C_D ATA <20>

D_ E DI D_ CLK <22>
D_ E DI D_ DATA <22>

D_ E DI D _CL K

R3 250_04 02 _5% @
R3 260_04 02 _5% @

X TALO UT

1

SG @

C8 11
20 P_0 402 _5 0V8

2

D_ E DI D _DA TAVG A_S M_D A

12

12

TH ER M# _VGA
TH ER M _SC I#

CRT

LVDS

HD C P_ SC L <25>

HD C P_ SD A < 25>

27 M _SSC <19>

27 M_ CLK <19>

TH ER M_ SCI #<37>

HDCP

VG A _SM _CL K
VG A_S M_D A

R3 15 0 _04 02_5%SG@
R3 16 0 _04 02_5%SG@

TH ER M _SC I#

TH ER M# _VGA

Close to GPU

D _ RED
D_ G RE EN
D_ B LUE

I2 C B_ SCL
I2 C B_ SDA

HD C P_ S CL
HD C P_ SD A

GP U _VID0
GP U _VID1

D_ E DI D _CL K
D_ E DI D _DA TA

12
12

4

1 2

R2 97 15 0_040 2_1 %S G@
R2 96 15 0_040 2_1 %S G@
R2 95 15 0_040 2_1 %S G@

R3 19 2. 2K_ 0402_ 5%SG @
R3 20 2. 2K_ 0402_ 5%SG @

R6 86 2. 2K_ 0402_ 5%SG @
R6 87 2. 2K_ 0402_ 5%SG @

R5 95 10 K_0 402_5 %@
R1 87 10 K_0 402_5 %@

R8 08 2. 2K_ 0402_ 5%SG @
R8 09 2. 2K_ 0402_ 5%SG @

12

1 2
1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

SM B_ EC_CK2_ R < 12>

SM B_ EC_DA2_R <12>

+3 VS_NV

SG @

R6 961 0K_ 040 2_ 5%

SG @

R3 141 0K_ 040 2_ 5%

+3 VS_NV

GPIO I/O ACTIVE USAGE

GPIO0

IN

N/A

GPIO1

IN

N/A

GPIO2

OUT

H

GPIO3

OUT

H

GPIO4

OUT

H

GPIO5

OUT

N/A

GPIO6

OUT

N/A

GPIO7

OUT

N/A

GPIO8

IN

L

GPIO9

OUT

L

GPIO10

OUT

N/A

GPIO11

OUT

L

GPIO12

IN

N/A

GPIO13

OUT

L

GPIO14

OUT

H

GPIO15

GPIO16

GPIO17

OUT

N/A

N/A

N/A

GPIO18 N/A

5

HPD-C (used for IFPC)

2nd DVI Hot-plug

Panel Back-Light PWM

Panel Power Enable

Panel Back-Light Enable

NVVDD VID0

NVVDD VID1

NVVDD VID2

OVERT

Thermal Alert

MEM_VREF

SLI SYNCO

AC Detect

MEM_VID

PS Control

HPD-E (used for IFPE)IN

FAN PWM Control

GPIO19 N/A HPD-D (used for IFPD)IN

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/12/31

Compal Secret Data

Deciphered Date

4

Tit le

Size Do c um en t N umb er R e v

Cu s to m

Da te : She et

Compal Electronics, Inc.

PEG Interface

Calpella DIS LA4743P

5

24 49Monda y, Apr il 13, 2009

o f

0. 1

1

2

3

4

5

LVDS Interface

U 8 C

D_ L VD S_ACLK+<22>
D_ L VD S_ACLK-<22>
D_ L VDS_A0 +<2 2>
D_ L VDS_A0 -<22>
D_ L VDS_A1 +<2 2>
D_ L VDS_A1 -<22>
D_ L VDS_A2 +<2 2>

A A

B B

D_ L VDS_A2 -<22>

HD MI C LK_ VGA<23>
HD MI D AT_VGA<2 3>

HD MI_C_ TX2+<23>
HD MI_C_ TX2-<2 3>
HD MI_C_ TX1+<23>
HD MI_C_ TX1-<2 3>
HD MI_C_ TX0+<23>
HD MI_C_ TX0-<2 3>
HD MI _ C_C LK+<23>
HD MI _ C_C LK-< 23>

HD MI _C_TX2 +

HD MI _C_TX2 -

HD MI _C_TX1 +

HD MI _C_TX1 -

HD MI _C_TX0 +

HD MI _C_TX0 -

HD MI _ C_ CLK +

HD MI _ C_ CLK -

AC4

IFPA_TXC

AD4

IFPA_TXC_N

V5

IFPA_TXD0

V4

IFPA_TXD0_N

AA5

IFPA_TXD1

AA4

IFPA_TXD1_N

W4

IFPA_TXD2

Y4

IFPA_TXD2_N

AB4

IFPA_TXD3

AB5

IFPA_TXD3_N

AB3

IFPB_TXC

AB2

IFPB_TXC_N

W1

IFPB_TXD4

V1

IFPB_TXD4_N

W3

IFPB_TXD5

W2

IFPB_TXD5_N

AA2

IFPB_TXD6

AA3

IFPB_TXD6_N

AB1

IFPB_TXD7

AA1

IFPB_TXD7_N

G4

IFPC_AUX_I2CW_SCL

G5

IFPC_AUX_I2CW_SDA_N

P4

IFPC_L0

N4

IFPC_L0_N

M5

IFPC_L1

M4

IFPC_L1_N

L4

IFPC_L2

K4

IFPC_L2_N

H4

IFPC_L3

J4

IFPC_L3_N

D3

IFPD_AUX_I2CX_SCL

D4

IFPD_AUX_I2CX_SDA_N

F5

IFPD_L0

F4

IFPD_L0_N

E4

IFPD_L1

D5

IFPD_L1_N

C3

IFPD_L2

C4

IFPD_L2_N

B3

IFPD_L3

B4

IFPD_L3_N

F7

IFPE_AUX_I2CY_SCL

G6

IFPE_AUX_I2CY_SDA_N

D6

IFPE_L0

C6

IFPE_L0_N

A6

IFPE_L1

A7

IFPE_L1_N

B6

IFPE_L2

B7

IFPE_L2_N

E6

IFPE_L3

E7

IFPE_L3_N

N10M-GLM- S-A1_ BGA533

S G@

Pa rt 3 of 5

C15

NC

D15

NC

J5

NC

NCRFU

T6

RFU_1

W6

RFU_2

Y6

RFU_3

AA6

RFU_4

N3

RFU_5

ST R AP0

C7

STRAP0
STRAP1
STRAP2

BUFRST_N

LVDS / TMDS

THERMDN
THERMDP

GENERAL STRAPSERIAL

SPDIF

ROM_CS_N
ROM_SCLK

ROM_SI

ROM_SO

IFPAB_RSET

IFPC_RSET
IFPD_RSET
IFPE_RSET

CEC

B9
A9

N5

D8
D9

N2
F9

B10
C9
A10
C10

AB6
R5
M6
F8

ST R AP1
ST R AP2

VG A_THERMDC
VG A_THERMDA

SP DI F_I N

RO M_C S#
RO M_S CLK
RO M _SI
RO M _SO

IFPAB_ RSET
IFPC_RSET
IF PD _ RSET
IF PE _ RSE T

S G@

R6 69 3 6K_ 040 2_ 1%

1 2

SG @

R3 01 1 0K_ 040 2_ 5%

1 2

R2 90 1 K_0 402 _1 %@

1 2

SG @

R3 02 1 K_0 402 _1 %

1 2

SG @

R6 97 1 K_0 402 _1 %

1 2

SG @

R6 98 1 K_0 402 _1 %

1 2

SPDIF

+3 VS_NV

Straps

C C

D D

1

2

HDCP ROM

U1 0

1

A0

VCC

2

A1

WP

3

SCL

A2

4

SDA

GND

AT 24 C 16 BN- SHB Y-B

SG @

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

8
7
6
5

+3 VS_NV

1

SG @

C3 88

0. 1U_04 02_16 V4Z

2

HD CP_SCL
HD CP_SDA

HD C P_ S CL

R3 13
10 K_0 402 _5 %

HD C P_ SC L <24 >

HD C P_ SD A <24>

12

@

2008/09/15 2009/12/31

Compal Secret Data

Deciphered Date

MULTI LEVEL STRAPS

4

@

SG @

SG @

SG @

SG @

@

ST R AP0
ST R AP1
ST R AP2
RO M _SI
RO M _SO
RO M_S CLK

R3 29

1 2

4.99K_04 02_1%
R3 39

1 2

35 K_0 402 _1 %

R3 42

1 2

24 .9K_04 02_1%

R3 44

1 2

15 K_0 402 _1 %

R3 46

1 2

4.99K_04 02_1%
R3 48

1 2

4.99K_04 02_1%

S G@

R3 30

1 2

45 .3K_04 02_1%

R3 40

@

1 2

4.99K_04 02_1%
R3 43

@

1 2

4.99K_04 02_1%
R3 45

@

1 2

4.99K_04 02_1%
R3 47

@

1 2

4.99K_04 02_1%
R3 49

SG @

1 2

4.99K_04 02_1%

Tit le

N10M(2)_ LVDS&DP&HDCP

Size Do c um en t N umb er R e v

Cu s to m

Da te : She et

FB HW Strap for DD R3: (RAM_CF G @RO M_SI)

- Hynix 64Mx16: 000 0 (R 344 p ull-down 15K)

- Samsung 64Mx1 6: 0001 (R344 pu ll-down 20K)

+3 VS_NV

Compal Electronics, Inc.

Ca lp ella DIS L A4743P

5

25 49Monda y, Apr il 13, 2009

0. 1

o f

1

2

3

4

5

CM DA 7

32~63 CKE 0~31 CKE0~31 ODT32~63 ODT

R7 49

@

10 0_0 402_5%

1 2

12

S G@

R7 47
10 K_0 402 _5 %

R7 45

CM D A18

@

10 0_0 402_5%

1 2

12

SG @

R7 51
10 K_0 402 _5 %

A A

U8 B

MD A[1 5..0]<2 8>

MD A[3 1..16 ]<2 8>

B B

MD A[4 7..32 ]<2 9>

MD A[6 3..48 ]<2 9>

C C

MD A0
MD A1
MD A2
MD A3
MD A4
MD A5
MD A6
MD A7
MD A8
MD A9
MD A1 0
MD A1 1
MD A1 2
MD A1 3
MD A1 4
MD A1 5
MD A1 6
MD A1 7
MD A1 8
MD A1 9
MD A2 0
MD A2 1
MD A2 2
MD A2 3
MD A2 4
MD A2 5
MD A2 6
MD A2 7
MD A2 8
MD A2 9
MD A3 0
MD A3 1
MD A3 2
MD A3 3
MD A3 4
MD A3 5
MD A3 6
MD A3 7
MD A3 8
MD A3 9
MD A4 0
MD A4 1
MD A4 2
MD A4 3
MD A4 4
MD A4 5
MD A4 6
MD A4 7
MD A4 8
MD A4 9
MD A5 0
MD A5 1
MD A5 2
MD A5 3
MD A5 4
MD A5 5
MD A5 6
MD A5 7
MD A5 8
MD A5 9
MD A6 0
MD A6 1
MD A6 2
MD A6 3

+V DD_MEM

AC24
AB23
AB24

W24

AA22

W23
W22

AA25

W27
W26

W25
AB25
AB26
AD26
AD27

D22
E24
E22
D24
D26
D27
C27
B27
A21
B21
C21
C19
C18
D18
B18
C16
E21

F21

D20

F20

D17

F18
D16
E16
A22
C24
D21
B22
C22
A25
B25
A26
U24
V24
V23
R24

T23
R23
P24
P22

V22

V25
R25
V26
V27
R26

T25
N25
N26

Pa rt 2 of 5

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31

MEMORY INTERFACE

FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

N10M-GLM- S-A1_ BGA533

SG @

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28

FBA_CMD29
FBA_CMD30

FBA_DQM0

FBA_DQM1

FBA_DQM2

FBA_DQM3

FBA_DQM4

FBA_DQM5

FBA_DQM6

FBA_DQM7

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FB_VREF

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FBA_DEBUG

CM DA 0

F26

CM DA 1

J24

CM DA 2

F25

CM DA 3

M23

CM DA 4

N27

CM DA 5

M27

CM DA 6

K26

CM DA 7

J25

CM DA 8

J27

CM DA 9

G23

CM D A10

G26

CM D A11

J23

CM D A12

M25

CM D A13

K27

CM D A14

G25

CM D A15

L24

CM D A16

K23

CM D A17

K24

CM D A18

G22

CM D A19

K25

CM D A20

H22

CM D A21

M26

CM D A22

H24

CM D A23

F27

CM D A24

J26

CM D A25

G24

CM D A26

G27

CM D A27

M24

CM D A28

K22

CM D A29

J22

CM D A30

L22

DQ M A0

C26

DQ M A1

B19

DQ M A2

D19

DQ M A3

D23

DQ M A4

T24

DQ M A5

AA23

DQ M A6

AB27

DQ M A7

T26

DQ S A#0

D25

DQ S A#1

A18

DQ S A#2

E18

DQ S A#3

B24

DQ S A#4

R22

DQ S A#5

Y24

DQ S A#6

AA27

DQ S A#7

R27

DQ S A0

C25

DQ S A1

A19

DQ S A2

E19

DQ S A3

A24

DQ S A4

T22

DQ S A5

AA24

DQ S A6

AA26

DQ S A7

T27

FB _V R EF

A16
F24

F23
N24

N23

OD T

M22

SG @

OD T

R1 2 10 K_0 402 _5%

W=15mils

1 2

CM DA [3 0.. 0] <2 8,2 9>

DQ MA[3 ..0 ] <28>

DQ MA[7 ..4 ] <29>

DQ S A#[3. .0] <28>

DQ S A#[7. .4] <29>

DQ S A[3 ..0] <28>

DQ S A[7 ..4] <29>

CL KA0 <28>
CL KA0# <28 >

CL KA1 <29>
CL KA1# <29 >

+V DD_MEM

+V DD_MEM +VD D _MEM + VD D_ MEM +V DD _MEM

R7 46

CM D A28

@

10 0_0 402_5%

1 2

12

SG @

R7 48
10 K_0 402 _5 %

CM D A30

@

10 0_0 402_5%

1 2

12

SG @

R7 52
10 K_0 402 _5 %

R7 50

12

R6 99

@

Rt

1K_ 04 02_ 1%

R7 01

@

1K_ 04 02_ 1%

D D

12

C8 13

Rb

Close to U8

@

FB _V R EF

0. 1U_04 02_16 V4Z

1

2

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/12/31

Compal Secret Data

Deciphered Date

4

Tit le

Size Do c um en t N umb er R e v

Cu s to m

Da te : She et

Compal Electronics, Inc.

N10M(3)_VGA RAM Interface

Ca lp ella DIS L A4743P

5

26 49Monda y, Apr il 13, 2009

o f

0. 1

1

VGA Power sequence: +.3VS->+NVVDD->+VDD_MEM

0. 1U_04 02_16 V4Z

0. 1U_04 02_16 V4Z

C8 14

1

2

A A

0.022u X 9

0.01u X 3

0.1u X 8

4.7u X 1
1u(0402) X 1
1u(0603) X 1
10u(0805) X 3

B B

SG @

0.022 U_0 40 2_1 6V7 K

C8 31

1

2

SG @

+3 VS_NV

SG @

R7 03 0_ 0603_ 5%

1 2

1U _0603 _10V4 Z

C8 58

1

0. 1U_04 02_16 V4Z

C8 15

C8 16

1

1

2

2

SG @

SG @

0.022 U_0 40 2_1 6V7 K

0.022 U_0 40 2_1 6V7 K

C8 32

C8 33

1

1

2

2

SG @

SG @

2

SG @

11.44A

0. 1U_04 02_16 V4Z

C8 17

1

2

SG @

0.022 U_0 40 2_1 6V7 K

C8 34

1

2

SG @

10 U_0 805_6 .3V 6M

C8 47

1

2

SG @

VD D 33

1U _0402 _6.3V4Z

C8 59

1

2

SG @

0. 1U_04 02_16 V4Z

0. 1U_04 02_16 V4Z
C8 19

C8 18

1

1

2

2

SG @

S G@

0.022 U_0 40 2_1 6V7 K

0.022 U_0 40 2_1 6V7 K
C8 36

C8 35

1

1

2

2

SG @

S G@

4.7U_ 060 3_ 6.3 V6K

1U _0402 _6.3V4Z

C8 48

C8 49

1

1

2

2

S G@

SG @

150mA

0. 1U_04 02_16 V4Z

0. 1U_04 02_16 V4Z
C8 61

C8 60

1

1

2

2

SG @

S G@

150mA

SG @

R7 1 10 K_0 402 _5%

1 2

SG @

R7 6 10 K_0 402 _5%

1 2

SG @

R7 9 10 K_0 402 _5%

1 2

+P CIE

C C

SG @

SG @

D D

SG @

L34

1 2

BL M18PG 181 SN1 D_060 3

4.7U_ 060 3_ 6.3 V6K

C8 68

1

2

+3 VS_NV

S G@

L3 8

1 2

BL M18PG 181 SN1 D_060 3

4.7U_ 060 3_ 6.3 V6K

C8 83

1

2

+3 VS_NV

SG @

L41

1 2

BL M18 PG1 81SN1D_0 603

C8 69

C8 84

C9 58

1

2

SG @

1

2

SG @

1

2

SG @

85mA

4.7U_ 060 3_ 6.3 V6K

70mA

4.7U_ 060 3_ 6.3 V6K

120mA

4.7U_ 060 3_ 6.3 V6K

IFP AB_PLLVDD

47 00P _04 02 _25 V7K

1U_06 03_10 V6K

@

C8 71

C8 70

1

1

2

2

S G@

IF PC_P LLVDD

1U_06 03_10 V6K

0.1U_ 040 2_ 10V 6K

C8 85

C8 86

1

1

2

2

S G@

SG @

1U _0402 _6.3V4Z

47 00P _04 02 _25 V7K

C8 99

C9 00

1

1

2

2

S G@

SG @

1

0.1U_ 040 2_ 10V 6K

@

C9 52

1

2

0.1U_ 040 2_ 10V 6K

C9 61

1

2

SG @

DA CA_ VD D

0.1U_ 040 2_ 10V 6K

C9 01

1

2

SG @

0.1U_ 040 2_ 10V 6K

@

C9 59

1

2

0.1U_ 040 2_ 10V 6K

C9 62

1

2

SG @

0.1U_ 040 2_ 10V 6K

C8 87

1

1

C8 88
47 0P_ 040 2_ 50V 8J

2

2

SG @

SG @

150mA

+1 .8 VS_ NV

BL M18PG 181 SN1 D_060 3

+P CIE +P CIE

SG @

2

+N VVD D

0. 1U_04 02_16 V4Z

0. 1U_04 02_16 V4Z

C8 20

C8 21

1

1

2

2

SG @

SG @

0.022 U_0 40 2_1 6V7 K

0.022 U_0 40 2_1 6V7 K
C8 38

C8 37

1

1

2

2

SG @

SG @

1U _0402 _6.3V4Z

C8 50

1

2

SG @

PE X _SVDD_ 3V3

IFP A_IO VDD
IF PB _ IOVDD
IFP C_IOVDD
IF PD E_I O VDD

IFP AB_PLLVDD
IF PC_P LLVDD
IF PD _ PL LVDD
IF PE _ PL LVD D

SG @

L44

1 2

SG @

L42

1 2

BL M18 PG1 81SN1D_0 603

4.7U_ 060 3_ 6.3 V6K

C9 02

1

2

2

U 8 D

J9

VDD

J10

VDD

J12

VDD

J13

VDD

L9

VDD

M9

VDD

M11

VDD

M17

VDD

N9

VDD

N11

VDD

N12

VDD

N13

VDD

N14

VDD

N15

VDD

N16

VDD

N17

VDD

N19

VDD

P11

VDD

P12

VDD

P13

VDD

P14

VDD

P15

VDD

P16

VDD

P17

VDD

R9

VDD

R11

VDD

R12

VDD

R13

VDD

R14

VDD

R15

VDD

R16

VDD

R17

VDD

T9

VDD

T11

VDD

T17

VDD

U9

VDD

U19

VDD

W9

VDD

W10

VDD

W12

VDD

W13

VDD

W18

VDD

W19

VDD

A12

VDD33

B12

VDD33

C12

VDD33

D12

VDD33

E12

VDD33

F12

VDD33

AG9

PEX_SVDD_3V3

V3

IFPA_IOVDD

V2

IFPB_IOVDD

J6

IFPC_IOVDD

H6

IFPDE_IOVDD

AD5

IFPAB_PLLVDD

P6

IFPC_PLLVDD

N6

IFPD_PLLVDD

D7

IFPE_PLLVDD

N10M-GLM- S-A1_ BGA533

SG @

100mA

1U_06 03_10 V6K

C8 76

1

2

SG @

100mA

150mA

4.7U_ 060 3_ 6.3 V6K

C9 03

C9 04

1

2

SG @

C8 77

1

2

SG @

1

2

SG @

3

Pa rt 4 of 5

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

3.4A

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

POWER

PEX_IOVDDQ
PEX_IOVDDQ

1.8A

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD

PEX_PLLVDD

VID_PLLVDD

SP_PLLVDD

PLLVDD
FB_PLLAVDD
FB_PLLAVDD

FB_DLLAVDD

DACA_VDD

120mA

DACB_VDD

FB_CAL_PD_VDDQ

VDD_SENSE
VDD_SENSE

0.1U_ 040 2_ 10V 6K

0.1U_ 040 2_ 10V 6K

1U_06 03_10 V6K

4.7U_ 060 3_ 6.3 V6K

C8 78

C8 91

1

1

2

2

SG @

SG @

IFP C_IOVDD PEX_P LLDVDD

0.1U_ 040 2_ 10V 6K

0.1U_ 040 2_ 10V 6K
C9 63

C9 05

1

1

2

2

SG @

SG @

A13
B13
C13
D13
D14
E13
F13
F14
F15
F16
F17
F19
F22
H23
H26
J15
J16
J18
J19
L19
L23
L26
M19
N22
U22
Y22

AG6
AF6
AE6
AD6
AC13
AC7
AB17
AB16
AB13
AB9
AB8
AB7

AG7
AF7
AE7
AD8
AD7
AC9

AF9
K6
L6
K5
R19
AC19
T19

AG2
W5

B15
W15
E15

IF PB _ IOVDD

IFP A_IO VDD

+V DD_MEM

0.047 U_0 40 2_1 6V7 K

C8 22

S G@

0. 1U_04 02_16 V4Z

C8 39

1

2

S G@

Lay out Not e:Please
col se t o Ball.

PE X_ P LLD VDD
GP U _P LL VDD

SP _PL LVD D

FB _P L L AVDD

DA CA_ VD D
DA CB_ VD D

0.047 U_0 40 2_1 6V7 K

0.047 U_0 40 2_1 6V7 K

C8 23

0.01U _04 02 _16 V7K

C8 24

C8 26

1

2

SG @

SG @

C8 40

1

2

SG @

0. 1U_04 02_16 V4Z

R7 09 1 0K_ 040 2_ 5%SG @

R7 10 4 0.2 _0402 _1%S G@
R7 44 0 _04 02_5%SG@
R7 11 0 _04 02_5%SG@

1U _0603 _10V4 Z

C8 41

1

2

SG @

C8 52

1

2

S G@

1 2

1 2
1 2
1 2

SG @

1U _0603 _10V4 Z

C8 42

1

2

SG @

0. 1U_04 02_16 V4Z
C8 53

1

2

SG @

0.01U _04 02 _16 V7K

1

2

SG @

C8 28

+P CIE

C8 44

1U _0603 _10V4 Z

1

2

S G@

1

2

S G@

C8 29

1

2

SG @

10 U_0 805_6 .3V 6M

600 mA

1U _0603 _10V4 Z

C8 55

1

2

SG @

+V DD_MEM

+N VVD D_ SE NSE

4.7U_ 060 3_ 6.3 V6K

+P CIE

10 U_0 805_6 .3V 6M

4.7U_ 060 3_ 6.3 V6K
C8 57

C8 56

1

1

2

2

S G@

SG @

to Power

SP _PL LVD D

C1 061

4.7U_ 060 3_ 6.3 V6K

C9 60

0.01U _04 02 _16 V7K

C8 27

1

2

SG @

4.7U_ 060 3_ 6.3 V6K

C8 43

1

2

SG @

0. 1U_04 02_16 V4Z
C8 54

1

2

SG @

Layout Note:Please
colse to Ball.

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/12/31

Compal Secret Data

Deciphered Date

4

S G@

R7 040_ 040 2_5%

1 2

S G@

R7 060_ 040 2_5%

1 2

S G@

L4 6

1 2

BL M18 PG1 81SN1D_0 603

1U _0402 _6.3V4Z

1

2

SG @

4

U 8 E

B2

GND

B5

GND

B8

GND

B11

GND

B14

GND

B17

GND

B20

GND

B23

GND

B26

GND

E2

GND

E5

GND

E8

GND

E11

GND

E17

GND

E20

GND

E23

GND

E26

GND

H2

GND

H5

GND

J11

GND

J14

GND

J17

GND

K9

GND

K19

GND

L2

GND

L5

GND

L11

GND

L12

GND

L13

GND

L14

GND

L15

GND

L16

GND

L17

GND

M12

GND

M13

GND

M14

GND

M15

GND

M16

GND

P2

GND

P5

GND

P9

GND

P19

GND

P23

GND

P26

GND

T12

GND

T13

GND

W16

GND_SENSE

E14

GND_SENSE

N10M-GLM- S-A1_ BGA533

SG @

+P CIE

C8 94

1

2

S G@

Pa rt 5 of 5

GND

FB_CAL_PU_GND

FB_CAL_TERM_GND
MULTI_STRAP_REF1_GND
MULTI_STRAP_REF0_GND

GP U _P LL VDD

0. 1U_04 02_16 V4Z

1U _0402 _6.3V4Z

C8 95

1

2

SG @

5

U2

GND

U5

GND

U11

GND

U12

GND

U13

GND

U14

GND

U15

GND

U16

GND

U17

GND

U23

GND

U26

GND

V9

GND

V19

GND

W11

GND

W14

GND

W17

GND

Y2

GND

Y5

GND

Y23

GND

Y26

GND

AC2

GND

AC5

GND

AC6

GND

AC8

GND

AC11

GND

AC14

GND

AC17

GND

AC20

GND

AC23

GND

AC26

GND

AF2

GND

AF5

GND

AF8

GND

AF11

GND

AF14

GND

AF17

GND

AF20

GND

AF23

GND

AF26

GND

T16

GND

T15

GND

T14

GND

F6

GND

PE X _SVDD_ 3V3

FB _P L L AVDD

135mA

C8 79

4.7U_ 060 3_ 6.3 V6M

C8 96

1

2

SG @

Tit le

Size Do c um en t N umb er R e v

Cu s to m

Da te : She et

R7 42 4 0.2 _0402 _1%S G@

A15
B16
F11
F10

SG @

1 2

R7 43 6 0.4 _0402 _1%S G@

1 2

R7 05 4 0.2 K_0 402_1%S G @

1 2

R7 07 4 0.2 K_0 402_1%S G @

1 2

SG @

R7 08 0 _04 02_5%

1 2

0. 1U_04 02_16 V4Z

C8 62

1

2

10mA

1U _0402 _6.3V4Z

4.7U_ 060 3_ 6.3 V6K
C8 67

C8 66

1

1

2

2

SG @

SG @

0. 1U_04 02_16 V4Z

1

2

S G@

C8 97

1

2

SG @

4.7U_ 060 3_ 6.3 V6K

1U _0402 _6.3V4Z

C8 80

1

2

SG @

110mA

1U _0402 _6.3V4Z

C8 93

1

2

S G@

0. 1U_04 02_16 V4Z

C8 81

C8 82

1

1

2

2

SG @

SG @

1 2

1U _0402 _6.3V4Z

C9 64

1

10 N H_M LG1 60 8B1 0NJ T_5 %

1U _0402 _6.3V4Z

2

SG @

Compal Electronics, Inc.

N10M(4)_Power/GND

Ca lp ella DIS L A4743P

5

+3 VS_NV

SG @

L33

1 2

BL M18 PG1 81SN1D_0 603

Lay out Not e:Please
col se t o BGA.

S G@

L3 7

1 2

BL M18 PG1 81SN1D_0 603

SG @

L40

Layout Note:Please
colse to BGA.

o f

27 49Monda y, Apr il 13, 2009

+P CIE

+P CIE

1U _0402 _6.3V4Z

C8 98

1

2

SG @

0. 1

1

2

3

4

5

VRAM DDR3 chips (512MB)

64Mx16 DDR3 700MHz*4==>512MB
Low 32 bit FB

12

R7 14

SG @

ME M_ V REF0

S G@

1

C9 08

0.01U _04 02 _16 V7K

2

10 K_0 402 _5 %

SG @

ME M_ V REF0

CM D A19
CM D A25
CM D A22
CM D A24
CM DA 0
CM DA 2
CM D A21
CM D A16
CM D A23
CM D A20
CM D A17
CM DA 9
CM D A14
CM D A26

CM D A12
CM DA 3
CM D A27

CL K A0
CL K A0#
CM D A18

CM D A30
CM D A29
CM DA 1
CM D A10
CM D A11

DQ S A2
DQ S A1

DQ M A2
DQ M A1

DQ S A#2
DQ S A#1

CM D A15

ZQ 0

24 3_0 402_1%

12

R7 15

A A

B B

C C

DQ S A[7 ..0 ]<2 6,29>
DQ S A#[ 7.. 0]<2 6,2 9>
DQ MA[7..0 ]<26,29>
MD A[6 3..0]<26, 29>
CM DA [3 0.. 0]< 26, 29>

DQ S A[ 7.. 0]

DQ S A#[7. .0]
DQ M A[7 ..0 ]
MD A [63 ..0 ]
CM DA [ 30. .0]

CM DA 15<26 ,29>

1K_ 04 02_ 1%

1K_ 04 02_ 1%

+V DD_MEM

SG @

R7 19

SG @

R7 21

12

12

Hynix : H5TQ1G63BFR-12C-->SA000032400
Samsung : K4W1G1646E-HC12-->SA000035700

U1 1

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

K4 B1G 16 46D -HCF8_ FBG A10 0

VR AM @

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ

310mA 310mA

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

10 0-B ALL
SD RAM D DR3

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

MD A2 1

E4

MD A1 8

F8

MD A2 3

F3

MD A1 6

F9

MD A2 0

H4

MD A1 9

H9

MD A2 2

G3

MD A1 7

H8

MD A8

D8

MD A1 4

C4

MD A1 0

C9

MD A1 2

C3

MD A1 1

A8

MD A1 3

A3

MD A9

B9

MD A1 5

A4

+V DD_MEM

B3
D10
G8
K3
K9
N2
N10
R2
R10

+V DD_MEM

A2
A9
C2
C10
D3
E10
F2
H3
H10

A10

VSS

B4

VSS

E2

VSS

G9

VSS

J3

VSS

J9

VSS

M2

VSS

M10

VSS

P2

VSS

P10

VSS

T2

VSS

T10

VSS

B2
B10
D2
D9
E3
E9
F10
G2
G10

+V DD_MEM

CL K A0<26 >

1 2

SG @

CL KA0#<26>

CL K A0

12

SG @

R7 18
12 1_0 402_1%

C9 060.0 1U_ 04 02_ 16 V7K

12

SG @

R7 22
12 1_0 402_1%

CL K A0#

SG @

R7 17

1K_ 04 02_ 1%

SG @

R7 20

1K_ 04 02_ 1%

12

12

ME M_ V REF1

SG @

1

C9 07

0.01U _04 02 _16 V7K

2

ME M_ V REF1

CM D A19
CM D A25
CM D A22
CM D A24
CM DA 0
CM DA 2
CM D A21
CM D A16
CM D A23
CM D A20
CM D A17
CM DA 9
CM D A14
CM D A26

CM D A12
CM DA 3
CM D A27

CL K A0
CL K A0#
CM D A18

CM D A30
CM D A29
CM DA 1
CM D A10
CM D A11

DQ S A0
DQ S A3

DQ M A0
DQ M A3

DQ S A#0
DQ S A#3

CM D A15

R7 16

S G@

ZQ 1

24 3_0 402_1%

12

U1 2

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

10 0-B ALL

SD RAM D DR3

K4 B1G 1646 D-H CF8 _FBGA1 00

VR AM @

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

Address

CMD0
CMD1

MD A5

E4

MD A1

F8

MD A6

F3

MD A2

F9

MD A4

H4

MD A0

H9

MD A7

G3

MD A3

H8

MD A2 6

D8

MD A3 0

C4

MD A2 8

C9

MD A2 9

C3

MD A2 7

A8

MD A2 5

A3

MD A2 4

B9

MD A3 1

A4

+V DD_MEM

B3
D10
G8
K3
K9
N2
N10
R2
R10

+V DD_MEM

A2
A9
C2
C10
D3
E10
F2
H3
H10

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

B2
B10
D2
D9
E3
E9
F10
G2
G10

CMD2
CMD3
CMD4
CMD5
CMD6
CMD7

CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
CMD15
CMD16
CMD17
CMD18
CMD19
CMD20
CMD21
CMD22
CMD23
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29
CMD30

DATA Bus

32..63

0..31
A4
RAS#
A5
BA1

A11
CAS#
WE#
BA0

A12
RST RST
A7
A10
CKE
A0
A9
A6
A2
A8
A3
A1
A13
BA2

CS#

LOW HIGH

RAS#

BA1
A2
A4
A3
CKE
CS#CMD8
A11
CAS#
WE#
BA0
A5
A12

A7
A10

A0
A9
A6

A8

A1
A13
BA2
ODT

+V DD_MEM

1U_04 02_6. 3V6 K

C9 19

1

D D

1

2

SG @

DDR3 BGA MEMORY

1U_04 02_6. 3V6 K

1U_04 02_6. 3V6 K

1U_04 02_6. 3V6 K

C9 21

C9 20

1

1

2

2

SG @

S G@

0.1U_ 040 2_ 16V 7K

C9 22

C9 23

1

1

2

2

SG @

SG @

0.1U_ 040 2_ 16V 7K

0.1U_ 040 2_ 16V 7K
C9 25

C9 24

1

1

2

2

S G@

SG @

0.1U_ 040 2_ 16V 7K

0.1U_ 040 2_ 16V 7K

C9 26

1

2

SG @

2

0.1U_ 040 2_ 16V 7K

C9 27

C9 28

1

1

2

2

SG @

SG @

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+V DD_MEM

C9 09

1

2

S G@

DDR3 BGA MEMORY

1U_04 02_6. 3V6 K

1U_04 02_6. 3V6 K

C9 10

1

2

SG @

2008/09/15 2009/12/31

1U_04 02_6. 3V6 K

C9 11

1

2

SG @

1U_04 02_6. 3V6 K

C9 12

1

2

SG @

Compal Secret Data

0.1U_ 040 2_ 16V 7K
C9 14

C9 13

1

2

SG @

Deciphered Date

1

2

S G@

0.1U_ 040 2_ 16V 7K

0.1U_ 040 2_ 16V 7K

0.1U_ 040 2_ 16V 7K

C9 15

C9 16

1

1

2

2

SG @

SG @

4

0.1U_ 040 2_ 16V 7K

0.1U_ 040 2_ 16V 7K
C9 18

C9 17

1

1

2

2

SG @

SG @

Tit le

Size Do c um en t N umb er R e v

Da te : She et

Compal Electronics, Inc.

VRAM DDR3

LA-4901P

Mon day, Apr il 13, 20 09

5

0.1

o f

49

28

1

VRAM DDR3 chips (512MB)

64Mx16 DDR3 700MHz*4==>512MB
High 32 bit FB

ME M_ V REF2

CM D A19

R7 25

24 3_0 402_1%

SG @

CM D A25
CM DA 4
CM DA 6
CM DA 5
CM D A13
CM D A21
CM D A16
CM D A23
CM D A20
CM D A17
CM DA 9
CM D A14
CM D A26

CM D A12
CM DA 3
CM D A27

CL K A1
CL K A1#
CM DA 7

CM D A28
CM DA 8
CM DA 1
CM D A10
CM D A11

DQ S A4
DQ S A7

DQ M A4
DQ M A7

DQ S A#4
DQ S A#7

CM D A15
ZQ 2

12

A A

CM DA 7<26>

CM DA 28<26>

B B

C C

+V DD_MEM

S G@

R7 29

1K_ 04 02_ 1%

S G@

R7 32

1K_ 04 02_ 1%

12

12

ME M_ V REF2

SG @

1

C9 31

0.01U _04 02 _16 V7K

2

2

DQ S A[7 ..0 ]<2 6,28>
DQ S A#[ 7.. 0]<2 6,2 8>

DQ MA[7..0 ]<26,28>

U1 3

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

K4 B1G 16 46D -HCF8_ FBG A10 0

VR AM @

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ

310mA 310mA

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

10 0-B ALL
SD RAM D DR3

MD A3 9

E4

MD A3 6

F8

MD A3 7

F3

MD A3 4

F9

MD A3 8

H4

MD A3 3

H9

MD A3 5

G3

MD A3 2

H8

MD A6 1

D8

MD A6 0

C4

MD A5 9

C9

MD A6 2

C3

MD A5 8

A8

MD A6 3

A3

MD A5 7

B9

MD A5 6

A4

+V DD_MEM

B3
D10
G8
K3
K9
N2
N10
R2
R10

+V DD_MEM

A2
A9
C2
C10
D3
E10
F2
H3
H10

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

B2
B10
D2
D9
E3
E9
F10
G2
G10

CL K A1<26 >

CL K A1#<2 6>

MD A[ 63..0 ]< 26, 28>
CM DA [3 0.. 0]< 26, 28>

S G@

C9 29 0. 01U _0402 _16V7 K

1 2

3

12

12

DQ S A[ 7.. 0]

DQ S A#[7. .0]
DQ M A[7 ..0 ]
MD A [63 ..0 ]
CM DA [ 30. .0]

CL K A1

SG @

R7 27
12 1_0 402_1%

SG @

R7 31
12 1_0 402_1%

CL K A1#

ME M_ V REF3

R7 26

24 3_0 402_1%

CM D A19
CM D A25
CM DA 4
CM DA 6
CM DA 5
CM D A13
CM D A21
CM D A16
CM D A23
CM D A20
CM D A17
CM DA 9
CM D A14
CM D A26

CM D A12
CM DA 3
CM D A27

CL K A1
CL K A1#
CM DA 7

CM D A28
CM DA 8
CM DA 1
CM D A10
CM D A11

DQ S A5
DQ S A6

DQ M A5
DQ M A6

DQ S A#5
DQ S A#6

CM D A15

ZQ 3

12

S G@

4

U1 4

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

10 0-B ALL

SD RAM D DR3

K4 B1G 16 46D -HCF8_ FBG A10 0

VR AM @

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

5

MD A4 1

E4

MD A4 6

F8

MD A4 0

F3

MD A4 5

F9

MD A4 2

H4

MD A4 7

H9

MD A4 4

G3

MD A4 3

H8

MD A4 8

D8

MD A5 3

C4

MD A5 0

C9

MD A5 2

C3

MD A5 1

A8

MD A5 4

A3

MD A4 9

B9

MD A5 5

A4

+V DD_MEM

B3
D10
G8
K3
K9
N2
N10
R2
R10

+V DD_MEM

A2
A9
C2
C10
D3
E10
F2
H3
H10

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

B2
B10
D2
D9
E3
E9
F10
G2
G10

+V DD_MEM

12

SG @

R7 28

1K_ 04 02_ 1%

ME M_ V REF3

12

SG @

R7 30

1K_ 04 02_ 1%

SG @

1

C9 30

0.01U _04 02 _16 V7K

2

+V DD_MEM +V DD_MEM

1U_04 02_6. 3V6 K

C9 32

1

2

SG @

D D

1

DDR3 BGA MEMORY DDR3 BGA MEMORY

C9 33

1

2

S G@

1

2

SG @

1

2

SG @

1U_04 02_6. 3V6 K

1U_04 02_6. 3V6 K

1U_04 02_6. 3V6 K

C9 35

C9 34

0.1U_ 040 2_ 16V 7K

0.1U_ 040 2_ 16V 7K

C9 36

1

2

SG @

0.1U_ 040 2_ 16V 7K

C9 37

C9 38

1

1

2

2

SG @

S G@

2

0.1U_ 040 2_ 16V 7K

0.1U_ 040 2_ 16V 7K

C9 39

1

2

SG @

0.1U_ 040 2_ 16V 7K

C9 40

C9 41

1

1

2

2

SG @

SG @

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1U_04 02_6. 3V6 K

C9 42

1

2

SG @

2008/09/15 2009/12/31

1U_04 02_6. 3V6 K

1U_04 02_6. 3V6 K

C9 44

C9 43

1

1

2

2

S G@

SG @

0.1U_ 040 2_ 16V 7K

1U_04 02_6. 3V6 K

C9 46

C9 45

1

1

2

2

SG @

SG @

Compal Secret Data

Deciphered Date

0.1U_ 040 2_ 16V 7K

0.1U_ 040 2_ 16V 7K
C9 48

C9 47

1

1

2

2

SG @

SG @

4

0.1U_ 040 2_ 16V 7K

0.1U_ 040 2_ 16V 7K

C9 49

1

2

S G@

0.1U_ 040 2_ 16V 7K

C9 50

C9 51

1

1

2

2

SG @

SG @

Tit le

Size Do c um en t N umb er R e v

Da te : She et

Compal Electronics, Inc.

VRAM DDR3

Cartier DIS

Mon day, Apr il 13, 20 09

5

0.1

o f

4929

5

D D

4

3

2

1

HDD Connector

JHDD

C C

24

GND

23

GND

OCTE K_SAT-22EH1G_RV

C ONN@

CD-ROM Connector

GND

GND

GND

GND
GND
GND

GND

Reserved

GND

1
2

A+

3

A-

4

SATA_RXN0

5

B-

6

B+

7

8

V33

9

V33

10

V33

11
12
13
14

V5

15

V5

16

V5

17
18
19
20

V12

21

V12

22

V12

C466 0 .01U_0402_16V7K

SATA_RXP0 SA TA_ RXP0_C

12

C467 0 .01U_0402_16V7K

12

Near CONN side.

+3VS

+5VS

SATA_TXP0
SATA_TXN0

SATA_RXN0_C

SATA_TXP0 <11>

SATA_TXN0 <11>

SATA_RXN0_C <11>

SATA_RXP0_C <11>

Pleace near HDD CONN (JP3)

+5VS

1

C462

2

10U_0805_10V4Z

1

1

C463

2

2

0.1U_0402_16V4Z

ACCELEROMETER (ST)

D10

2 1

CH75 1H-4 0PT _SOD323-2

1

C465

C464

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

VDDIO absolute man
rating is VDD+0.1

+3V S_A CL_IO

+3V S_ACL

+3V S_ACL+3VS +3V S_A CL_IO

1 2

U15

1

R366
0_0 402_5%

1 2

2
3
4
5
6

Vdd_IO
GND
Reserved
GND
GND
Vdd

R364

0_0 603_5%

SMB _CLK_S3

14

SCL / SPC

SDA / SDI / SDO

SDO

Reserved

GND
INT 2
INT 1

13
12
11
10
9
8

SMB _DATA_S3

R367

1 2

1

2

0_0 402_5%

+3V S_ACL

1

C468

C469

2

0.1U_0402_16V4Z

10U_0805_6.3V6M

SMB _CLK_S3 <12,17,18,19>

0011101b

SMB _DATA_S3 <12,1 7,18,19>

ACCEL_ INT <14>

JODD

B B

SUY IN_127382FR013GX09ZR

C ONN@

GND

GND

GND

GND
GND

13
12

A+

11

A-

10

B-

B+

DP

V5
V5

MD

SATA_RXP4

8
7

6
5
4
3
2
1

SATA_RXN4

9

C473 0.01 U_0402_16V7K

12

C474 0.01 U_0402_16V7K

12

Near CONN side.

+5VS

SATA_TXP4
SATA_TXN4

SATA_RXN4_C
SATA_RXP4_C

SATA_TXP4 <11>

SATA_TXN4 <11>

SATA_RXN4_C <11>
SATA_RXP4_C <11>

Placea caps. near ODD CONN.

+5VS

1

1

C475

2

0.1U_0402_16V4Z

1

C476

C477

2

2

1U_0603_10V4Z

R368

Must be placed in the center of the system.

02/12 Change SM bus to VS

1

C478

2

10U_0805_10V4Z

10U_0805_10V4Z

ZZ Z1

12

10K _0402_5%

CS

LIS302DLTR_LGA 14_3x5

7

PCB-MB

A A

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

Cu st om

2

Da te: Sheet o f

Compal Electronics, Inc.

HDD & CDROM

Ca lpella DI S LA4743P

1

30 49Monday, April 13, 2009

0.1

A

B

C

D

E

+3V ALW +3VS_WWAN

0.01U_0402_16V7K

1

C515

1 1

2 2

2

0.1U_0402_16V4Z

+3V ALW

WW AN_POWER_OFF<37>

SIM card Connector

UIM_ PWR
UIM_DATA
UI M_CLK
UIM_RS T
UIM_VPP

1

C516

2

0.1U_0402_16V4Z

R409

@

1 2

0_0 603_5%

S

G

2

JS IM

6

6

G2

5

5

G1

4

4

3

3

2

2

1

1

ACE S_8 7212-06G0

C ONN@

4.7U_0805_10V4Z

1

C517

2

+3VS_WWAN

D

13

Q16

@

SI2301BDS_SOT23

8
7

1

C518

2

R410

1 2

0_1 206_5%

UIM_ PWR

+3VS

1 2

47K _04 02_5%

1

C519
18P _04 02_50V8J

2

+3V ALW +1.5 VS_WLAN

1

1

C509

2

2

0.1U_0402_16V4Z

R406

@

UIM_DATA

UI M_CLK

@

WL_ LED# WW _ LED#_R

XMIT_OFF# M_WXMIT_OFF#

UIM_ PWR_R
UIM_DA TA_ R
UI M_CLK_R
UIM_RS T_R
UIM_VPP _R

UIM_ PWR_R
UIM_DA TA_ R
UI M_CLK_R
UIM_RS T_R
UIM_VPP _R

R760 0_0 402_5%
R761 0_0 402_5%
R762 0_0 402_5%
R763 0_0 402_5%
R764 0_0 402_5%

R765 0_0 402_5%
R766 0_0 402_5%
R767 0_0 402_5%
R768 0_0 402_5%
R769 0_0 402_5%

R388

12

0_0 805_5%

1

1

C512

2

0.01U_0402_16V7K

1

2

C513

0.1U_0402_16V4Z

+3V S_WLAN

C510

0.1U_0402_16V4Z

C514

2

4.7U_0805_10V4Z

R389

0_0 805_5%

1

C511

2

4.7U_0805_10V4Z

For PR

1 2

R758 0_0402_5%P R@

1 2

R759 0_0402_5%P R@

1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2

LPC_FRA ME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

UIM_ PWR
UIM_DATA
UI M_CLK
UIM_RS T
UIM_VPP

Mini Card Solt--WLAN/WWAN

IC H_P CIE_ WAK E#

+1.5 VS

PCIE_RXN2<12>
PCIE _RX P2<12>

12

+3VS

PR @
PR @
PR @
PR @
PR @

PA@
PA@
PA@
PA@
PA@

CH_DATA<35>

CH_CLK<35>

CL KRE Q_WL AN#<12>

CLK_PCIE_WLAN#<12>
CLK_PCIE_WLAN<12>

CLK_DEBUG_PORT_1<14>

R399 0_0 402_5%

1 2

R401 0_0 402_5%

1 2

PCIE _TXN2<12>

PCIE _TXP2<12>

CL KR EQ_ WWAN#<12>

CL K_PCIE_WWA N#<12>
CL K_ PCIE _WW AN<12>

PCIE _RX N1<12>
PCIE _RXP1<12>

PCIE _TXN1<12>

PCIE_TXP1<12>

+3V S_WWAN

CH_DAT A
CH_CLK

CL K_ PCIE _MCARD2#
CL K_ PCIE _MCARD2

PLT_RST#

PCIE _TXN2
PCIE _TXP2

+3V S_WLAN

IC H_P CIE_ WAK E#
CH_DAT A
CH_CLK

0_0 402_5%

1 2
1 2

P CIE_ C_RX N1
PCIE _C_RXP1

PCIE _TXN1
PCIE _TXP1

R403 0 _0603_5%

1 2
1 2

R404 0 _0603_5%

R395
R397 0_0402_5%

P CIE_ C_RX N2
PCIE _C_RXP2

JM INIA

A1

WAKE#

A3

COEX1

A5

COEX2

A7

CLKREQ#

A9

GND

A11

REFCLK-

A13

REFCLK+

A15

GND

A17

Reserved

A19

Reserved

A21

GND

A23

PERn0

A25

PERp0

A27

GND

A29

GND

A31

PETn0

A33

PETp0

A35

GND

A37

GND

A39

+3.3Vaux

A41

+3.3Vaux

A43

GND

A45

Reserved

A47

Reserved

A49

Reserved

A51

Reserved

A53

GND

QUASA_CA04 16-092N21

C ONN@

JM INIB

B1

WAKE#

B3

COEX1

B5

COEX1

B7

CLKREQ#

GND

B11

REFCLK-

B13

REFCLK+

GND

B17

Reserved

B19

Reserved

GND

B23

PERn0

B25

PERp0

GND
GND

B31

PETn0

B33

PETp0

GND

B37

GND

B39

+3.3Vaux

B41

+3.3Vaux

B43

GND

B45

Reserved

B47

Reserved

B49

Reserved

B51

Reserved

QUASA_CA04 16-092N21

C ONN@

+3.3Vaux

GND

+1.5V

UIM_PWR

UIM_DATA

UIM_CLK

UIM_RESET

UIM_VPP

GND

W_DISABLE#

PERST#

+3.3Vaux

GND

+1.5V

SMB_CLK

SMB_DATA

GND

USB_D-

USB_D+

GND

LED_WWAN#

LED_WLAN#

LED_WPAN#

+1.5V

GND

+3.3Vaux

+3.3Vaux

+1.5V

UIM_PWR

UIM_DATA

UIM_CLK

UIM_RESET

UIM_VPP

W_DISABLE#

PERST#

+3.3Vaux

+1.5V

SMB_CLK

SMB_DATA

USB_D-

USB_D+

LED_WWAN#

LED_WLAN#

LED_WPAN#

+1.5V

+3.3Vaux

GND

GND

GND

GND

GND

GND

GND

C977 47P_0402_50V8J@

A2
A6

A8
A10
A12
A14
A16

A20
A22
A24

A28
A30
A32

A36
A38

A42
A44
A46
A48

A52
A54

B2
B4
B6
B8
B10
B12
B14
B16
B18
B20
B22
B24
B26
B28
B30
B32
B34
B36
B38
B40
B42
B44
B46
B48
B50
B52

1 2

+1.5 VS_WLAN

XMIT_OFF#

D13

PLT_RST#

R400 0_0 805_5%@
R402 0_0 805_5%

SMB CLK

SMB DATA

2

C978

@

47P _04 02_50V8J

1

C979 4 7P_ 040 2_50V8J@

+1.5 VS_WLAN

M_WXMIT _OFF#

PLT_RST#

SMB CLK

SMB DATA

+1.5 VS_WLAN

1

2

2 1

1 2
1 2

USB 20_N5 <14>
USB 20_P5 <14>

WL_LED# <38>
+1.5 VS_WLAN
+3V S_WLAN

1 2

UIM_ PWR_R

UIM_DA TA_ R

UI M_CLK_R

UIM_RS T_R

UIM_VPP _R

D12

1 2
1 2

USB 20_N8 <14>
USB 20_P8 <14>

WW _ LED#_R

2 1

+1.5 VS_WLAN

R396 0_0 805_5%@
R398 0_0 805_5%

+3V S_WWAN

C980
47P _04 02_50V8J

@

+3V S_WLAN

LPC_FRA ME# <11,36 ,37>
LP C_AD3 <11,36,37>
LP C_AD2 <11,36,37>
LP C_AD1 <11,36,37>
LP C_AD0 <11,36,37>

CH75 1H-4 0_S C76

+3V ALW
+3V S_WLAN
+1.5 VS_WLAN

+3V S_WWAN

CH75 1H-4 0_S C76

+3V ALW
+3VS_WWAN

WW _LED# <38>

XMIT_OFF <14>

WXMIT_OFF# <14>

3 3

C520

1 2

C523 0 .1U_ 0402_16V4Z

1 2

C524 0 .1U_ 0402_16V4Z

+3V ALW

PLT_RST#<6,14,32>

SY S ON<37,38,3 9,48>
SUS P#<37,39,41,44,45>

+3V ALW

4 4

internal pull high to 3.3Vaux-in
EC need setting at Hi-Z & output Low

A

1 2

PLT_RST#
SY S ON
SUS P#

R414 10 0K_ 0402_5%@

1 2

EXP_CPPE#

New Card

0.1U_0402_16V4Z

+3VS

Express Card Power Switch

+1.5VS

U19

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin
AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

R5538D001-TR-F_QFN20_4X4~D

B

1.5Vout

1.5Vout

3.3Vout

3.3Vout

PERST#

GND

OC#

USB 20_N9<14>
USB 20_P9<14>

11
13

3
5

15
19
8
16

NC

7

PERST#

+1.5 VS_PEC

+3V S_PEC

+3V _PEC

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ICH_PCIE_W AKE#<13,32>

2007/08/28 2006/07/26

C

SMB CLK<12>

SMB DATA<12>

R413 0_0 402_5%

1 2

CLKREQ_EXP#<12>

CLK_PCIE_EXP#<12>
CLK_PCIE_EXP<12>

PCIE _RX N4<12>

PCIE _RX P4<12>
PCIE _TXN4<12>

PCIE _TXP4<12>

Compal Secret Data

Deciphered Date

+1.5 VS_PEC

+3V _PEC

+3V S_PEC

330 P_0 402_50V7K

EXP_CPPE#

SMB CLK
SMB DATA

PCIE _PME#_R
PERST#

EXP_CPPE#

C527

@

D

1

2

JEXP

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

SANTA_ 130 801-5_RT

C ONN@

Title

Size Do cument Number Re v

Da te: Sheet o f

Near to Express Card slot.

+3V S_PEC

1

C521

0.1U_0402_16V4Z

C525

0.1U_0402_16V4Z

C528

0.1U_0402_16V4Z

+1.5 VS_PEC

+3V _PEC

1

2

2

1

1

2

2

1

1

2

2

Compal Electronics, Inc.

WLAN, WWAN, New Card

Ca lpella DI S LA4743P

31 49Monday, April 13, 2009

E

C522

4.7U_0805_10V4Z

C526

4.7U_0805_10V4Z

C529

4.7U_0805_10V4Z

0.1

5

+ DVD D

D D

4. 7 UH _10 08 HC- 472EJFS-A _5% _10 08

L2

1 2

Close to Pin8.

+V DD33

CR _ WA KE #<1 4>

C C

27 P_0 402 _5 0V8J

B B

A A

1

1

C1 035

2

2

C1 034

10 U_0 805_6 .3V 6M

0. 1U_04 02_16 V4Z

D4 1 CH 75 1H-40 PT_SOD323 -2

LAN _X1

1

C1 043

1

2

2

+V CC_4IN1 +V CC_4IN1

MD IO 0
MD IO 1
MD IO 2
MD IO 3
MD IO 8

MD IO 9
MD IO 10
MD IO 11

MD IO 4

MD IO 6
MD IO 14

XD _ CD

MD IO 13
MD IO 12

MD I O5_R

MD IO 7

+D VDD1 2

2

1

1

2

C1 020

C1 019

C1 018

0. 1U_04 02_16 V4Z

0. 1U_04 02_16 V4Z

10 U_0 805_6 .3V 6M

CL K _P CIE _LAN#<12 >

CL K _P CIE _LAN<12>

PC IE_TXP 3<12 >

PC IE_TXN 3<12>

IC H _P CI E_WAKE#<13 ,31>

+V CC_4IN1

C4 81 0.1 U_040 2_16V 7K
C4 79 0.1 U_040 2_16V 7K

PL T_RST#<6, 14,31 >

CL K RE Q_LAN#<1 2>

PC IE_RXN3<1 2>
PC IE_RXP3<1 2>

21

2

1

C1 040

1

C1 044
27 P_0 402 _5 0V8J

2

0. 1U_04 02_16 V4Z

LAN _X2

3

IN

OUT

Y 4

NC

NC

4

25 MH Z_1 6PF_ X3S02500 0FG 1H- HX

Card Reader Connector

JR EAD 1

3

XD-VCC

32

XD-D0

10

9
8
7
6
5
4

34
33
35
40
39
38
37
36

11
31

41
42

5

7 IN 1 CONN

XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

7IN1 GND
7IN1 GND

7IN1 GND
7IN1 GND

TAITW _R 0 15 -B 1 0- LM

CONN@

2

2

1

1

C1 021

0. 1U_04 02_16 V4Z

12
12

SD-CD-SW

SD-WP-SW

MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

2

2

1

1

C1 023

C1 022

0. 1U_04 02_16 V4Z

0. 1U_04 02_16 V4Z

R8 19 1 2K_ 040 2_ 1%

SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7

MS-SCLK

12

+V DD33

LAN _X1
LAN _X2

+ DVD D

+D VDD1 2

+V DD33

PC IE_PT X_I RX_ N3
P CIE_PTX _IR X_P 3

+D VDD1 2

M P D
CL K RE Q_ LAN #

CR _ CD 0N

+D VDD1 2

+V DD33 +VD D33

CR _ L ED#

MD IO 14
MD IO 13

21

SD-VCC

28

MS-VCC
SD_CLK

SD-CMD

MS-INS

MS-BS

20
14
12
30
29
27
23
18
16
25
1

2

26
17
15
19
24
22
13

MD I O5_R
MD IO 0
MD IO 1
MD IO 2
MD IO 3
MD IO 8
MD IO 9
MD IO 10
MD IO 11
MD IO 4

CR _ CD 0N

MD IO 6

MD I O5_R
MD IO 0
MD IO 1
MD IO 2
MD IO 3

CR _ CD 1N

MD IO 4

4

+3 V_ LAN

U4 6

1

REXT

2

VDDX33

3

XIN

4

XOUT

5

GND

6

LX

7

FB12

8

VDDREG

9

CLKN

10

CLKP

11

AVDDH

12

RXP

13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

JMC261

RXN
GND

(LQFP 64)

TXN
TXP
AVDDX
RSTN
WAKEN
MPD
CREQN
SMB_SCL/LED2
CR_CD1N
CR_CD0N
VCC3O
VDD
VDDIO
TESTN
SMB_SDA/CR_LEDN
MDIO14
MDIO13
GND

JM C261- LGBZ0A _LQ FP6 4_7X7

JMC251 SA000039X：00
JMC261 SA000037N：00

1

C1 062

2

10 U_0 805_6 .3V 6M

4

R8 17

1 2

0_ 080 5_5%

+V DD33

2

2

1

1

C1 028

C1 029

0. 1U_04 02_16 V4Z

0. 1U_04 02_16 V4Z

LA N _MD I3­LA N _MD I3+

LA N _MD I2­LA N _MD I2+

LA N _MD I1­LA N _MD I1+

LA N _MD I0­LA N _MD I0+

LA N _L INK #
LA N _ACT#
MD IO 0
MD IO 1
MD IO 2

MD IO 3
MD IO 4

R3 33 2 2_0 402_5%

MD IO 5
MD IO 6

MD IO 7
MD IO 8

MD IO 9
MD IO 10
MD IO 11
MD IO 12

C1 030

+D VDD1 2

+D VDD1 2

+D VDD1 2

C1 025

1

2

10 U_0 805_6 .3V 6M

AVDD33

VIN_2
VIP_2

AVDD12

VIN_1
VIP_1

LED1

LED0
MDIO0
MDIO1
MDIO2
VDDIO
MDIO3
MDIO4
MDIO5

MDIO6
MDIO7
VDDIO

MDIO8

MDIO9

MDIO10
MDIO11
MDIO12

GND

GND
VDD

GND

2

2

1

1

C1 026

C1 027

0. 1U_04 02_16 V4Z

0. 1U_04 02_16 V4Z

64

NC

63

NC

62

NC

61

NC

60

NC

59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

D3E support

PL T_ RST # M P D

R9 26 0 _04 02_5%

1 2

@

R3 82 0 _04 02_5%

LA N _P OW E R_ OFF< 37>

1 2

2

1

0. 1U_04 02_16 V4Z

+V DD33

+V DD33

1 2

2

1

C1 086

0. 1U_04 02_16 V4Z

3

2

LA N _ACT#

LA N _L INK #

10/100 and Giga Transformer Co lay

MD I O5_RC R_ CD1 N

C1 042 0 .1U_ 040 2_ 16V 4Z

1 2

1.For Giga LAN (RTL8111DL):
Mail source: LANKom: LG-2446S-1 (P/N: SP050005L00)
2nd Source: MHPC: NS892406 (P/N: SP050005900)

2.For 10/100M (RTL 8103EL):
Main Source: MHPC NS892404 (P/N: SP050003P00)

@

R9 25 0_ 0402_ 5%@
R9 27 0_ 0402_ 5%@

+3 VALW

R8 24

12
12

C4 85

@

1 2

10 0K_ 040 2_ 5%

0. 1U_04 02_16 V4Z

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

R8 23 0_ 0805_ 5%@

1 2

S

2

1

+V DD33
+3 VS

D

13

G

2

Q1 5

SI2 301BDS-T1 -E3 _SOT23-3

40 mils

2007/08/28 2006/10/06

+3 V_ LAN

LA N _MD I0+
LA N _MD I0-

LA N _MD I1+
LA N _MD I1-

LA N _MD I2+
LA N _MD I2-

LA N _MD I3+
LA N _MD I3-

4.7K_040 2_5%

Compal Secret Data

10
11
12

+V DD33

R8 25

CR _ CD 1N
CR _ CD 0N

Deciphered Date

2

1
2
3

4
5

7
8
9

12

C4 80

0. 1U_04 02_16 V4Z

C4 82

0. 1U_04 02_16 V4Z

U1 7

SU PE R WO RL D_ SWG 15 040 1

TCT1

MCT1

TD1+

MX1+

TD1-

MX1-

TCT2

MCT2

TD2+

MX2+

TD2-6MX2­TCT3

MCT3

TD3+

MX3+

TD3-

MX3-

TCT4

MCT4

TD4+

MX4+

TD4-

MX4-

12

R8 26

4.7K_040 2_5%

D3 9

2
3

DA N20 2U_ SC7 0

24
23
22

21
20
19

18
17
16

15
14
13

1

R3 69
30 0_0 402_5%

1

2

2

1

C1 041 1 00 0P_ 0402_ 50V7K

12

C1 039 1 00 0P_ 0402_ 50V7K

12

C1 085 1 00 0P_ 0402_ 50V7K

12

C1 083 1 00 0P_ 0402_ 50V7K

12

XD _ CD

1

2

LA N LED_ACT#

12

RJ 4 5_ MID I3­RJ 4 5_ MID I3+
RJ 4 5_ MID I1­RJ 4 5_ MID I2­RJ 4 5_ MID I2+
RJ 4 5_ MID I1+
RJ 4 5_ MID I0­RJ 4 5_ MID I0+

LA N LE D_ LINK#

12

R3 71
30 0_0 402_5%

RJ 4 5_ MID I0+
RJ 4 5_ MID I0-

RJ 4 5_ MID I1+
RJ 4 5_ MID I1-

RJ 4 5_ MID I2+
RJ 4 5_ MID I2-

RJ 4 5_ MID I3+
RJ 4 5_ MID I3-

R8 28 1 .2K_04 02_5%

+5 VS

C1 047
27 0P_ 040 2_ 25V7

Tit le

USB CardReader&CONN

Size Do c um en t N umb er R e v

Cu s to m

Da te : She et o f

1

LAN Conn.

JR J 45

+3 V_ LAN

+3 V_ LAN

13

Yellow LED+

14

Yellow LED-

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

11

Green LED+

12

Green LED-

FOX _JM361 13-P1 122 -7F

C O NN @

1

C4 83

0. 1U_04 02_16 V4Z

2

R8 22 75_04 02_1%

1 2

R8 21 75_04 02_1%

1 2

R9 23 75_04 02_1%

1 2

81 11 DL@

R9 22 75_04 02_1%

1 2

81 11 DL@

10 00P _12 06 _2K V7K

1 2

+V CC_4IN1

R8 29 1 0K_ 040 2_ 5%

1 2

R8 30 1 0K_ 040 2_ 5%

1 2

R8 31 1 K_0 402 _5 %

1 2

DETECT PIN1

DETCET PIN2

1

C4 84

4. 7U_08 05_10 V4Z

2

C1 045

D4 0

2 1

HT -11 0TW _WHITE

White

Compal Electronics, Inc.

Ca lp ella DIS L A4743P

1

SHLD1

SHLD1

16
9

10
15

LA N GN D

RJ 4 5_ G ND

1

2

CR _ L ED#

MD IO 4
MD IO 6
MD IO 13

0. 1

32 49Monda y, Apr il 13, 2009

A

B

C

D

E

R430

12

0_0 402_5%

R432

4.7K_0402_5%

MIC_EXT_R
MIC_EXT_L

+A VDD_CODEC

HP_DET# <34>
EXTMIC_DET# <34>

C1070 0.1U_ 0402_16V4Z

1 2

EC_BEEP <37>

2N7002_SOT23-3

12

C545

12

1U_0603_10V4Z

R433

4.7K_0402_5%

+A VDD_ CODEC

D

Q38

S

1 2

R909

10K _0402_5%

1 2

13

2

G

SB_SPKR

+V RE FOUT _INT MIC

SB_SPKR <11>

1 2
1 2
1 2

1 2

HP_OUTL <34>
HP _OUTR <34>

MIC_EXT_L <34>
MIC_EXT_R <34>

SPKL+ <34>
SPKL- <34>

SPKR- <34>
SPKR+ <34>

MI C_IN_L <34>
MI C_ IN_R <34>

+VREFOUT_EXTMIC

HP Jack
Ext MIC

Internal SPKR

Int MIC

12

12

+3VS

R437

BLM18B D601SN1D_0603

C551

HDA_BITCLK_CODEC<11>
HDA_ SDIN0<11>

HDA_ SDOUT_CODEC<11>
HDA_ SYNC_CODEC<11>
HDA_RST# _CODEC<11,37>

+3V S_HDA

1

2

0.1U_0402_16V4Z
33P _04 02_50V8K

DMIC_CLK<21>

DMIC_DAT<21>

C554

@

EA P D_CODEC<37>

+3VS

R907 0_0 603_5%

1 2

1 1

2 2

+3VS_DVDD

12

1

1

C553

C976

2

2

0.1U_0402_16V4Z
1U_0402_6.3V6K

C1065 10U_0805_10V4Z

12

R441

@

12

EC_MUTE#<37>

12

47_ 040 2_5%

+3VS

HDA_BIT CLK_CODE C

R444

HDA_ SDIN0_CODEC

1 2

33_ 0402_5%

HDA_ S DOUT_CODE C
HDA_ SYNC_CODEC
HDA_RST #_CODEC

R679 33_ 0402_5%

1 2

R446 0_0 603_5%

1 2

R910 0_0 402_5%@

1 2

R908 10K _04 02_5%

1 2

EC_MUTE#

4.7U_0603_6.3V6M

C1069

2

1

U22

1

DVDD_CORE

9

DVDD

3

DVDD_IO

6

HDA_BITCLK

8

HDA_SDI

5

HDA_SDO

10

HDA_SYNC

11

HDA_RST#

2

DMIC_CLK/GPIO1

4

DMIC0/GPIO2

46

DMIC1/GPIO0/SPDIF_OUT_1

48

SPDIF_OUT_0

47

EAPD

35

CAP-

36

CAP+

7

DVSS

33

AVSS

30

AVSS

26

AVSS

42

PVSS

49

DAP

92HD81B 1X5 NLGX B1X 8_QFN48_7X7~D

HP0_PORT_A_L
HP0_PORT_A_R

VREFOUT_A_or_F

HP1_PORT_B_L
HP1_PORT_B_R

VREFOUT_C

SPKR_PORT_D_L+

SPKR_PORT_D_L­SPKR_PORT_D_R-

SPKR_PORT_D_R+

MONO_OUT

+A VDD_ CODEC +5VS

R904 0_0 805_5%

1

1

C1064

C1063

2

2

27

AVDD
AVDD

PVDD
PVDD

SENSE_A
SENSE_B

PORT_C_L
PORT_C_R

PORT_E_L
PORT_E_R

PORT_F_L

PORT_F_R

PC_BEEP

CAP2

VREFFILT

VREG

38
39

45
13

R442 100 K_0 402_5%

14

C555 100 0P_ 0402_50V7K@

28
29

+V RE FOUT _INT MIC

23

HP_OUTL

31

HP _OUTR

32

MIC_EXTL

19

MIC_EXTR

20
24

SPKL+

40

SPKL-

41

SPKR-

43

SPKR+

44
15

16

MI C_ INL

17

MI C_ INR MIC_IN_R

18

MO NO_INR MON O_IN

12
25

22
21
34

V-

37

2

1

C1072

C1071

4.7U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V4Z

SENSEA

12

1 2

C557 2.2U_0603_6.3V4Z

1 2

C558 2.2U_0603_6.3V4Z

1 2

+VREFOUT_EXTMIC

C559 2.2U_0603_6.3V4Z

1 2

C560 2.2U_0603_6.3V4Z

1 2

C561 0.1U_0402_16V4Z

12

1

2

10U_0805_10V4Z

2

C563

1 2

C564

1

1U_0603_10V6K

10U_0805_10V4Z

1

2

12

1

C1066

2

0.1U_0402_16V4Z

+A VDD_CODEC

C1067

1U_0402_6.3V6K

MIC_EXT_L
MIC_EXT_R

C562

0.1U_0402_16V4Z

1

C1068

2

R438 2.5K_0402_1%
R439 39.2K_0402_1%

10U_0805_10V4Z

R440 20K _04 02_1%
C556 100 0P_ 0402_50V7K

MI C_IN_L

R447 47K _04 02_5%

R448 47K _04 02_5%@

2

R449

1

10K _04 02_5%

1 2

R431

1K_0402_5%

4.7K_0402_5%

MI C_ IN_R
MI C_IN_L

12

R434

12

C546

12

1U_0603_10V4Z

R435

4.7K_0402_5%

1 2

3 3

C983 1 000 P_0 402_50V7K@

MDC 1.5 Conn.

HDA_ SDOUT_MDC<11>

H9
HOLE A

1

HDA_ SYNC_MDC<11>

HDA_ SDIN1<11>

HDA_RS T#_MDC<11>

H10
HOLE A

1

R452 33 _0402_5%

1 2

HDA_ SDOUT_MDC
HDA_ SYNC_MDC

HDA_ S DIN1_MDC

JP8

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

Connector for MDC Rev1.5

C ONN@

IAC_BITCLK

GND13GND14GND15GND16GND17GND

RES0
RES1

3.3V
GND3
GND4

ACE S_8 8018-124G

18

R450 0_0 603_5%

1 2

2
4
6
8
10
12

R453

@

10_ 0402_5%

+3VS

HDA _BITCLK _MDC <11>

C568

@

12

10P _04 02_25V8K

+3VS

1 2

+3VS

1

1

C566

C565

2

2

0.1U_0402_16V4Z

100 0P_ 0402_50V7K

1 2

C984 1 000 P_0 402_50V7K@

1 2

C985 1 000 P_0 402_50V7K@

1 2

C986 1 000 P_0 402_50V7K@

1 2

R754 0_0 603_5%

1 2

R132 0_0 603_5%@

1 2

R135 0_0 603_5%@

1 2

R139 0_0 603_5%@

1 2

GNDA <34>

GNDAGND

MDC Standoff

4 4

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

Cu st om

D

Da te: Sheet o f

Codec_IDT9271B7

Calpella DIS LA4743P

E

33 49Monday, April 13, 2009

0.1

A

B

C

D

E

SPEAKER

JSP K1

1

1

2

2

3

3

4

4

5

GND1

6

GND2

E&T_3806-F04N-02R

C ONN@

1

C572

2

330 P_0 402_50V7K

D16
PSOT24 C_SOT23-3

SPK_R­SPK_R+
SPK_L­SPK_L+

SPKR-

R454 0_ 0603_5%

SPKR-<33>
SPKR+<33>
SPKL-<33>

1 1

SPKL+<33>

1 2

SPKR+

R455 0_ 0603_5%

1 2

SPKL-

R456 0_ 0603_5%

1 2

SPKL+

R457 0_ 0603_5%

1 2

1

1

2

2

3

1

2

D15
PSOT24 C_SOT23-3

C569

330 P_0 402_50V7K

1

C571

C570

2

330 P_0 402_50V7K

330 P_0 402_50V7K

2

3

1

MI C_IN_L<33>

MI C_ IN_R<33>

PSOT24 C_SOT23-3

R469

0_0 402_5%

1

D17

2

12

3

INTMIC IN

C ONN@

JP10

1

1

2

2

3

GND

4

GND

ACE S_8 8231-02001

Audio connector

JA UD IO

1

MIC_EXT_R<33>

2 2

Add JSPK2 for PA

SPK_L­SPK_L+

C ONN@

JSP K2

1

1

2

2

3

GND

4

GND

ACE S_8 8231-02001

MIC_EXT_L<33>

HP_OUTL<33>
HP _OUTR<33>

EXTMIC_DET#<33>

HP_DET#<33>

MIC_EXT_R
MIC_EXT_L

HP_OUTL
HP _OUTR

EXTMIC_DET#
HP_DET#

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND1

12

GND2

ACE S_8 7213-1000G

C ONN@

Consumer IR

3 3

CIR_IN<37>

4.7U_0805_10V4Z

4 4

A

B

+5VL

12

R476
100 _0805_5%

CIR_IN

C597

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

I R1

1

Vout

2

VCC

3

GND

4

GND

IRM-V536/TR1_3P

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

D

Title

Size Do cument Number Re v

Cu st om

Da te: Sheet o f

AMP & Audio Jack

Calpella DIS LA4743P

E

34 49Monday, April 13, 2009

0.1

5

4

3

2

1

Right side USB Power Switch Right side ESATA/USB combination Connector

+5V ALW

U2 4

1

GND

2

D D

C599

USB _EN#

1

2

4.7U_0805_10V4Z

IN

3

IN

4

EN#

TPS2061IDGNR_MSOP8

OUT
OUT
OUT
OC#

8

W=100mils

7
6
5

1

+

C598

2

150 U_B_6.3 VM_R40M

R481 10K _04 02_5%

1

C600

2

0.1U_0402_16V4Z

1 2

+USB_ VCCC

1

C601

2

100 0P_ 0402_50V7K

+5V ALW

+USB _VCCC

R479 0_0 402_5%

USB 20_N2<14>
USB 20_P2<14>

SATA_TXP2<11>
SATA_TXN2<11>

SATA_RXN2_C<11>
SATA_RXP2_C<11>

1 2

R480 0_0 402_5%

1 2

C602 0.01 U_0402_16V7K

12

C603 0.01 U_0402_16V7K

12

US B20_N2_R
USB 20_P2_R

SATA_TXP2
SATA_TXN2

SATA_RXN2
SATA_RXP2

JESATA

1

VBUS

2

D-

3

D+

4

GND

5

GND

6

A+

7

A-

8

GND

9

B-

10

B+

11

GND

12

GND

13

GND

14

GND

15

GND

TYCO_17595 76-1

C ONN@

USB

ESATA

D20

+5V ALW

Finger printer

C C

B B

+3VS

R483
0_0 603_5%

1 2

+3V S_FP

1

C604

0.1U_0402_16V4Z

2

+5V ALW

USB 20_N7<14>
USB 20_P7<14>

US B20_N7_R

R484 0_0 402_5%

1 2

R485 0_0 402_5%

1 2

D22

4
3

2

IO1

VIN

1

GND

IO2

PRTR5V0U2X_SOT143-4

USB 20_P7_R

USB cable connector for Left side

JUSB

+5V ALW

USB_EN#<37>

USB 20_N0<14>
USB 20_P0<14>

USB 20_N1<14>
USB 20_P1<14>

USB _EN#

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND1

12

GND2

ACE S_8 7213-1000G

C ONN@

US B20_N7_R
USB 20_P7_R

C ONN@

JF PR

1

1

2

2

3

3

4

4

5

GND

6

GND

P-T WO_161011-04021

BT Connector

JBT

9

GND

10

GND

ACE S_8 7213-0800G

C ONN@

R491

1 2

+3VS

0_0 603_5%

BT_OFF<14>

4
3

1
2

USB 20_P6_R

3

US B20_N6_R

4
5
6
7
8

1

C605

2

1 2

VIN
IO2

PRTR5V0U2X_SOT143-4

R489 1K_0402_5%@
R490 1K_0402_5%@

1U_0603_10V4Z

USB 20_N2

1
2
3
4
5
6
7
8

R494 10K _0402_5%

USB 20_P2

2

IO1

1

GND

R487 0_0 402_5%
R488 0_0 402_5%

1 2
1 2

Q20 SI2301BDS_SOT23

S

G

12

R493
100 K_0402_5%

2

C609 0 .1U_ 0402_16V4Z

+5V ALW

SATA_TXN2

Need change to New version

US B20_N6_R

0.1U_0402_16V4Z

1

C606

2

+3V AUX_BT

D2 3

4
3

PRTR5V0U2X_SOT143-4

+3V AUX_BT

1

C607

2

4.7U_0805_10V4Z

12
12

+5V ALW

D

13

0.01U_0402_16V7K

1 2

4
3

USB 20_P6 <14>
USB 20_N6 <14>
BT_LED <38>
CH_DATA <31>

CH_CLK <31>

2

IO1

VIN

1

GND

IO2

10 /0 8 ESD request

1

C608

2

D21

VIN
IO2

PRTR5V0U2X_SOT143-4

GND

SATA_TXP2

2

IO1

1

10 /0 8 ESD request

USB 20_P6_R

A A

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

2

Da te: Sheet o f

Compal Electronics, Inc.

USB, BT, eSATA

Ca lpella DI S LA4743P

35 49Monday, April 13, 2009

1

0.1

5

4

3

2

1

D D

0.1U_0402_16V4Z

FSEL#<37>
SPI_CLK<37>

C C

R495 1 0_0 402_5%
R496 1 0_0 402_5%
R497 1 0_0 402_5%

SPI ROM on PCH => 4M (ME code + System BIOS)

+3VS

1 2

1 2

SPI_SI<11>

SPI_WP#

3.3K_0402_5%

S PI_HOLD#

3.3K_0402_5%

SPI_SB _CS#
S PI_CLK_ PCH

SPI_SI

R661

1 2

15_ 0402_5%

R658

R659

SPI_SB _CS#<11>

SP I_CL K_P CH<11>

B B

SPI ROM => 1M (EC code)

+3VL

20mils

1

C610

2

+3VS

1 2

SPI_FS EL#
S PI_CLK_ R

：：：：

：：：：

：：：：

：：：：

0.1U_0402_16V4Z

R660

@

1K_0402_5%

1 2
1 2
1 2

SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH
WIESO_G6179-100000_8P

SA00000XT00 S IC FL 8M
SA00001AW00 S IC FL 16M MX25L
SA000021A00 S IC FL 32M
SA000031Q00 S IC

U25

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

WIESON G6179 8P SPI

VSS

4

SPI_SOSP I_FWR#

2

Q

MX25L8005M2C-15G SOP 8P (MXIC)

1605AM2C-15G SOP 8P SPI (MXIC)

MX25L3205DM2I-12G SOP 8P (MXIC)

FL 32M AT25DF321-SU SOIC 8P (ATMEL)

+3VS

1

C773

2

U31

8

SPI_WP#
S PI_HOLD#

VCC

3

W

7

HOLD

1

S

6

C

5

D

WIESON G6179 8P SPI

1 2

R498 0 _04 02_5%

4

VSS

2

Q

&U25

MX25L8005M2C-15G SOP 8P

45@

FR D#

S PI_CLK_ R

FR D# <37>FW R#<37>

R233

1 2

10_ 0402_5%

0919 EMI request

&U31

32M AT25DF321-SU SOIC 8P

45@

R662

1 2

15_ 0402_5%

SPI_SO_RSP I_SO_L

C391

1 2

6P_040 2_50V8D

SPI_SO_R <11>

LPC Debug Port

CLK_DEBUG_PORT_0<14>

LPC_FRA ME#<11,31,37>

PCI_RST#<14 ,37>

LP C_AD0<11,3 1,37>
LP C_AD1<11,3 1,37>
LP C_AD2<11,3 1,37>
LP C_AD3<11,3 1,37>

ON/OFFBTNLE D#

VC C1 P WRGD

Connect pin3 & 23
together and pin 24
to GND in 6/29.

+3V ALW

R504

1 2

ON/OFFB TN_LED#<37,38>

VC C1 _PWRGD<37>

SPI_CLK_JP18
SPI_CS#_JP18
SPI_SI_JP18
SPI_SO_JP18
SPI_HOLD#_0

SPI_CLK

FSEL#

FW R#

HOLD#

3.3K_0402_5%

FR D#

ON /OFFBT N_LE D#

VC C1 _ PWRGD

Change from +3VL to +3VS. 6/9
Removed +3VS. 6/13

B+

JP1 5

1

Ground

2

LPC_PCI_CLK

3

Ground

4

LPC_FRAME#

5

+V3S

6

LPC_RESET#

7

+V3S

8

LPC_AD0

9

LPC_AD1

10

LPC_AD2

11

LPC_AD3

12

VCC_3VA

13

PWR_LED#

14

CAPS_LED#

15

NUM_LED#

16

VCC1_PWRGD

17

SPI_CLK

18

SPI_CS#

19

SPI_SI

20

SPI_SO

21

SPI_HOLD#

22

Reserved

23

Reserved

24

Reserved

ACE S_8 7216-2404_24P

C ONN@

1 2

R501 0_0402_5%

DE BUG@

1 2

R502 0_0402_5%

DE BUG@

1 2

R503 0_0402_5%

DE BUG@

1 2

R505 0_0402_5%

DE BUG@

1 2

R506 0_0402_5%

DE BUG@

1 2

R507 0_0402_5%

DE BUG@

1 2

R508 0_0402_5%

DE BUG@

SPI_CLK_JP18

SPI_CS#_JP18

SPI_SI_JP18

SPI_HOLD#_0

SPI_SO_JP18

ON/OFFBTNLE D#

VC C1 P WRGD

11/07 Add 0 Ohm for debug port

A A

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

2

Da te: Sheet o f

Compal Electronics, Inc.

BIOS ROM

Ca lpella DI S LA4743P

1

36 49Monday, April 13, 2009

0.1

+3V L_EC

0.1U_0402_16V4Z

1

1

C613

C614

2

R512 4.7K_0402_5%
R513 4.7K_0402_5%
R514 4.7K_0402_5%
R515 4.7K_0402_5%

+3VL

R517 47K_0402_5%

SUS P#

12

R522

8.2K_0402_5%

SY S ON

R521

8.2K_0402_5%

1 2

2

0.1U_0402_16V4Z

SMB _EC_DA1
SMB _EC_CK1
SMB _EC_DA2
SMB _EC_CK2

11/15 Delete PCI_PME#

PCI_ PME#<14>

EC_PME# PCI_RST#

1

C645

0.1U_0402_16V4Z

2

@

03/13 PV2 Add EMI solution

EC DEBUG port

UTX

R542

@

LA N_POWE R_OF F<32>

0.1U_0402_16V4Z

1

1

2

100 0P_ 0402_50V7K

1 2

C630 0.1 U_0402_16V4Z

R533

1

C646

0.1U_0402_16V4Z

2

C615

1 2
1 2
1 2
1 2

CLK_PCI_EC<14>

12

1 2

R543

1 2

0_0 402_5%

C616

2

@

PCI_ RST#

12

R523
100 K_0 402_5%

0_0 402_5%

12

0_0 805_5%

100 0P_ 0402_50V7K

1

C617

2

+3VL +3 VALW

C623

15P _04 02_50V8J

LA N _POWER_ OFF_R

1 2

1 2

12

J4
JOPEN

+3VL

12

R526
10K _0402_5%

LI D_SW#

+3VL

R531

@

10K _0402_5%

1 2

EC_PME#

EC_PME#

+3VL

ON/OFFBT N#<38>

32.768KHZ_ 12.5PF_Q13 MC14610002

ESB_CLK<38>

ESB_DAT<38>

R516

@

33_ 0402_5%

HDA_RST# _CODEC<11,33>

+3VS

12

R525
10K _0402_5%

TP_BTN#

01/03 Change to +3VS

+3V ALW

12

R532
10K _04 02_5%

EC _A CIN<13>

FAN_SP EED<6>

WW AN_POWE R_OF F<31>

1 2

R538 4 .7K_0402_5%

C647
15P _04 02_50V8J

1 2

3

NC

2

NC

1 2

C649
15P _04 02_50V8J

+3VL +3VL

12

R544

4.7K_0402_5%

GAT EA20<14>
KB_RST#<14>

SI RQ<11>

LPC_FRA ME#<11,31,36>

LP C_AD3<11,3 1,36>
LP C_AD2<11,3 1,36>
LP C_AD1<11,3 1,36>
LP C_AD0<11,3 1,36>

PCI_RST#<14 ,36>

EC _SCI#<14>

SMB _EC_CK1<38 ,40>
SMB _EC_DA1<38 ,40>
SMB _EC_CK2<12>
SMB _EC_DA2<12>

SLP_S3#<13>
SLP_S5#<13>
EC_SMI#<14>
LID_SW#<38>

EC _ ACIN

FAN_SP EED
UTX

LA N _POWER_ OFF_R

DIM_LE D<39>

Y6

OSC
OSC

4.7K_0402_5%

1 2

12

4
1

R545

R546 0_0 402_5%

1 2

R547 0_0 402_5%

1 2

GAT EA20
KB_RST#
SI RQ
LPC_FRA ME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CL K_ PCI_ EC

PCI_ RST#
ECRS T#

1 2

R518

0_0 402_5%

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

SMB _EC_CK1
SMB _EC_DA1
SMB _EC_CK2
SMB _EC_DA2

SLP_S3#
SLP_S5#
EC_SMI#
LI D_SW#
ESB_CL K_R
ESB_DA T_R
EC_PME#

WW AN_ POWER_OFF

ON/OFFBTN#

DI M_L ED

C RY 2

@

R539
20M_0402_5%

C RY 1

+3VL +3V L_EC

R511

1 2

0_0 805_5%

U27

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

LID_SW#/GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT#/GPIO0C

19

EC_PME#/GPIO0D

25

EC_THERM#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LED#/GPIO19

36

NUMLED#/GPIO1A

122

XCLK1

123

XCLK0

+E C_A VCC

1

C652

@

10P _04 02_50V8J

2

ESB_CL K_R
ESB_DA T_R

LPC & MISC

9

PS2 Interface

Int. K/B
Matrix

SM Bus

+3V L_EC

12

L26
0_0 603_5%

1 2

C650 0.1U_0 402_16V4Z

Security Classification

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+EC_AVCC

33

96

111

125

VCC

VCC

VCC

VCC

VCC

PWM Output

67

INVT_PWM/PWM1/GPIO0F

ACOFF/FANPWM2/GPIO13

22

VCC

AD Input

DA Output

TP_DATA/PSDAT3/GPIO4F

SPI Device Interface

SPI Flash ROM

BATT_CHGI_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO54

GPO

GPIO

GPI

GND

GND

GND

GND

GND

11

24

35

69

94

113

EC AGND

Issued Date

AVCC

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B
AD4/GPIO42

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

CAPS_LED#/GPIO53

SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10
GPXO11

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

AGND

KB926QFB0 _LQFP128_14X14

L27

1 2

0_0 603_5%

2007/08/28 2006/07/26

21
23
26
27

63
64
65
66
75
76

68
70
71
72

83
84
85
86
87
88

97
98
99
109

119
120
126
128

73
74
89
90
91
92
93
95
121
127

100

R535

101
102
103
104
105
106
107
108

110
112
114
115
116
117
118

124

1

2

For C
Revision

C651 1 00P _0402_50V8J

INV_P WM
EC_BEEP

AC OFF

BATT_TEMP
BATT_OVP
A DP_I
AD P_ID
TP_BTN#

FAB_SET
V CTRL

IREF

AC_SET

EC_MUTE#
USB _EN#
I2 C_INT

TP_CLK
TP_DATA

R524 0_0 402_5%

R527 33_ 0402_5%

1 2

R528 33_ 0402_5%

1 2

R529 33_ 0402_5%

1 2

R530 10K _04 02_5%

CIR_IN
VC C1 _ PWRGD
FS TCHG
STD_ADP
CAP S_L ED#
BAT_LED#
ON /OFFBT N_LE D#
SY S ON
VR _ON
AC _ IN

EC_RSMRST#

1 2

EC _ON
WL_ BLUE_LED#
P M_PWROK_R
BKOFF#
M_PWROK
TP_LED#

SLP_S4#
ENB KL
EA P D_CODEC
THERM_SCI#
SUS P#
PWRBTN_ OUT#
NM I_DBG#

C648

4.7U_0603_6.3V6K

AC _ IN AC IN

1 2

1 2

R534 1 0K_ 0402_5%

0_0 402_5%

SLP_S4# <13>

NM I_DBG# PC I_SERR#

Compal Secret Data

Deciphered Date

INV_P WM <22>
EC_BEEP <33>

AC OFF <41>

BATT_TEMP <40>
BATT_OVP <40>
ADP_I <41>
AD P_ID <40>
TP_BTN# <38>

FAN_SET <6>

VCTRL <41>
IREF <41>
AC_SET <41>

EC_MUTE# <33>

USB_EN# <35>
I2 C_INT <38>

1 2

C IR_IN <34>

VC C1 _P WRGD <36>

FS TCHG <41>

STD_ADP <41>

CAP S_L ED# <38>

BAT_LED# <38>

ON/OFF BTN_LED# <36,38>
SY S ON <31,38,39,48>

VR _ON <46>

EC_RSMRST# <13>

EC _LID_OUT # <12>

EC _ON <42>

WL_ BLUE_LED# <38>
BK OFF # <21>

M_PWROK <13>
TP_LED# <38>

THERM_SCI# <24>
SUS P# <31,39,41,44,45>

PWRBTN_ OUT# <13>

+3VL

12

R540

+3VL

12

0.01U_0402_16V7K

C624

1 2

12

ENB KL <22>
EA P D_CODEC <33>

10K _0402_5%

D2 5

21

CH75 1H-4 0PT _SOD323-2

R541
150 K_0402_5%

D26

2 1

CH75 1H-4 0PT _SOD323-2

FSEL#

EC AGND

R519 10K _0402_5%

1 2

R520 10K _0402_5%

1 2

TP_CLK <38>
TP_DATA <38>

AC_LED# <40>

11/09 don't stuff when use C0

FR D#
FW R#
SPI_CLK

FR D# <36>
FW R# <36>
SPI_CLK <36>
FSEL# <36>

+5VL

R536

1 2

100 _0402_5%

PV PWROK sequence issue

AD P_ID

2 1

CH75 1H-4 0PT _SOD323-2

PC I_S ERR# <14>

AC IN <41>

BATT_OVP

C612

12

100 P_0 402_50V8J

For EMI

KSO15

C618 1 00P _04 02_50V8J@

1 2

C619 1 00P _04 02_50V8J@

1 2

C620 1 00P _04 02_50V8J@

1 2

C621 1 00P _04 02_50V8J@

1 2

C622 1 00P _04 02_50V8J@

1 2

C625 1 00P _04 02_50V8J@

1 2

C626 1 00P _04 02_50V8J@

1 2

C627 1 00P _04 02_50V8J@

1 2

C628 1 00P _04 02_50V8J@

1 2

C629 1 00P _04 02_50V8J@

1 2

C631 1 00P _04 02_50V8J@

1 2

C632 1 00P _04 02_50V8J@

1 2

C633 1 00P _04 02_50V8J@

1 2

C634 1 00P _04 02_50V8J@

1 2

C635 1 00P _04 02_50V8J@

1 2

C636 1 00P _04 02_50V8J@

1 2

C637 1 00P _04 02_50V8J@

1 2

C638 1 00P _04 02_50V8J@

1 2

C639 1 00P _04 02_50V8J@

1 2

C640 1 00P _04 02_50V8J@

1 2

C641 1 00P _04 02_50V8J@

1 2

C642 1 00P _04 02_50V8J@

1 2

C643 1 00P _04 02_50V8J@

1 2

C644 1 00P _04 02_50V8J@

1 2

ENB KL

R741 10K_0402_5%

13" INT_KBD

12

+5V_TP

PM_ PWROK <13>

KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

CONN.( TYPE "D"
KB)

JKB1

KSO15

1

1

KSO10

2

+3VL

D24

Title

Size Do cument Number Re v

Da te: Sheet

Compal Electronics, Inc.

EC KB926/KB Conn.

Ca lpella DI S LA4743P

2

KSO11

3

3

KSO14

4

4

KSO13

5

5

KSO12

6

6

KSO3

7

7

KSO6

8

8

KSO8

9

9

KSO7

10

10

KSO4

11

11

KSO2

12

12

13

13

KSO1

14

14

KSO5

15

15

16

16

17

17

KSO0

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

G1

26

G2

ACE S_8 5202-24051

C ONN@

KSI0

KSI3
KSI2

KSI5
KSI4

KSO9

KSI6
KSI7
KSI1

o f

37 49Monday, April 13, 2009

0.1

A

1 1

B

C

D

E

System LED Conn

JL ED

1

1

GND

2

2

3

3

4

4

5

5

6

6

7

7

8

8

GND

ACE S_8 7213-0800G

C ONN@

9

10

White

AMBER

+5V ALW

+5VS

+3VS

BAT_LED#<37>

SATA_LED#<11>

HDDHALT_LED#<11>

ON /OFFBT N_LE D#

Capacitor Sensor Conn

2 2

Cyp ress@

R597 0_0 402_5%

SMB _EC_CK1<37,40>
SMB _EC_DA1<37,40>

ON/OFF BTN_LED#<3 6,37>

ESB_CLK<37>
ESB_DAT<37>

I2 C_INT<37>

+5V ALW

LI D_SW#<37>

ON/OFF BTN#<37>

3 3

ON /OFFBT N_LE D#

R561 FBMA-11-10 0505-801T 0402ENE@

1 2

R562 FBMA-11-10 0505-801T 0402ENE@

1 2

1 2

R598 0_0 402_5%

1 2

Cyp ress@

R596 1.8K_0402_5%

1 2

R563 1K_0402_5%

1 2

Caps-Lock Conn

JCAP

1
2
3

4
GND
GND

P-T WO_161011-04021

CONN@

+5VS

+3VL

12

R557
0_0 805_5%

1

1

@

C772

15P _04 02_50V8J

C661

2

2

4.7U_0603_6.3V6K

1
2
3
4
5
6

+5VS

JC SB

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

P-T WO_1610 21-10021

C ONN@

CAP S_L ED# <37>

ESB_DAT

ESB_CLK

Keyboard backlight Conn

Power Button

for debug only

SW2

1
2

5

6

SMT 1-05_4P

@

12

@

12

C662

15P _04 02_50V8J

C660

15P _04 02_50V8J

R570

@

33_ 0402_5%

R564

@

33_ 0402_5%

T/P Board (Inculde T/P_ON/OFF)

ON/OFFBTN#

3
4

12

12

SY SON<31,37,3 9,48>

+5V ALW +5V_TP

R558 0_0 603_5%

12

R560

@

10K _0402_5%

13

SY S ON

D

2

G

S

Mini card LED

JTP SW

P-T WO_1610 11-04021

C ONN@

1 2

S

D

13

Q23

G

SI2301BDS-T1-E3_SOT23-3

2

Q24

@

2N7002_SOT23-3

1

1

TP_LED#

2

2

TP_BTN#

3

3

4

4

5

GND

6

GND

T/P Board Conn

@

JTP

1
2
3

4
GND
GND

P-T WO_1610 11-04021

C ONN@

+5VS

1
2
3
4
5
6

TP_LED# <37>
TP_BTN# <37>

+5V_TP

TP_CLK
TP_DATA

100 P_0 402_50V8J

+3VS

12

R565
10K _04 02_5%

TP_DATA
TP_CLK

1

C654

0.1U_0402_16V4Z

2

C658

@

1

1

2

2

2

3

D32
PSOT24 C_SOT23-3

1

TP_CLK <37>
TP_DATA <37>

C659

@

100 P_0 402_50V8J

R566

+5V S_LED

4 4

A

B

1 2

0_0 805_5%

JKBL

1

1

2

2

3

3

4

4

5

GND

6

GND

P-T WO_1610 11-04021

C ONN@

WL_LED#<31>
WW _LED#<31>

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

D

BT_LED<35>

D33

2
3

PSOT24 C_SOT23-3

2N7002_SOT23-3

R567

100 K_0 402_5%

1

Q25

13

D

2

G

12

S

WL_LED

Title

Size Do cument Number Re v

Da te: Sheet o f

WL_ BLUE_LED# <37>

Compal Electronics, Inc.

KBD, ON/OFF, SW, CIR

Ca lpella DI S LA4743P

38 49Monday, April 13, 2009

E

0.1

5

4

3

2

1

+5VALW to +5VS Transfer +3VALW to +3VS Transfer

+5V ALW +3V ALW

B+

D D

12

R583

C675

330 K_0 402_5%

SUS P

2

2N7002DW-7-F_S OT363-6

Q10A

SI7326DN-T1 -E3_PAK1212-8

1

2

10U_0805_10V4Z

RU NON

61

U2 8

4

12

1

2

+5VS +3VS

1
2
35

1

1

C671

C672

2

0.1U_0402_16V4Z
10U_0805_10V4Z

01/03 Sparate+5VS
and +3VS power
timing

R585

470 _0402_5%

C677
470 0P_ 0402_25V7K

2

B+

12

R581

330 K_0 402_5%

SUS P

5

2N7002DW-7-F_S OT363-6

Q10B

SI7326DN-T1 -E3_PAK1212-8

U2 9

1

C669
10U_0805_10V4Z

2

RUNO N_3VS

3

4

1
2
35

4

12

R584
470 _0402_5%

1

C676

0.01U_0402_16V7K

2

1

1

2

C674

C673

2

10U_0805_10V4Z

0.1U_0402_16V4Z

+1.5V to +1.5VS Transfer

SI7326DN-T1 -E3_PAK1212-8

U30

1

C681

2

RU NON

10U_0805_10V4Z

4

12

1

2

1
2
35

R650
1K_0402_5%

C770

0.1U_0402_25V4K

+1.5VS+1.5V

1

2

1

C679

C680

2

0.1U_0402_16V4Z

10U_0805_10V4Z

+3VALW to +3VS_NV Transfer +1.8VS to +1.8VS_NV Transfer +1.5V to +1.5VS_NV Transfer

SI7326DN-T1 -E3_PAK1212-8

U48

SG@

C C

12

SG@

R912

330 K_0 402_5%

DGPU _PW R_EN<14,23,45,47>

SG@

2N7002DW-7-F_S OT363-6

1

2

DGPU _PWR_E N#

3

5

Q14B

4

SG@

C1073
10U_0805_10V4Z

4

12

1

2

+3V S_NVB+ +3VALW +1.8 VS_NV

1
2
35

SG@

SG@

R915
470 _0402_5%

DGPU _PWR_E N

SG@

C1077

0.01U_0402_16V7K

400 mA 100 mA 4.64A

Q14A

SG@

2

12

R913

470 _04 02_5%

61

2N7002DW-7-F_S OT363-6

SG@

1

2

C1075

0.1U_0402_16V4Z

SG@

+1.8 VS

B+

12

1

SG@

R918

2

330 K_0 402_5%

NV VDD_PG#

NV VDD_PG<47>

SG@

2N7002DW-7-F_S OT363-6

C1076

10U_0805_10V4Z

5

Q17B

SI7326DN-T1 -E3_PAK1212-8

U49

SG@

3

4

1
2
35

4

12

SG@

R916
1K_0402_5%

SG@

1

C1078

0.1U_0402_25V4K

2

1

SG@

2

NV VDD_PG

SI7326DN-T1 -E3_PAK1212-8

U50

SG@

12

C1074

SG@

R594

0.1U_0402_16V4Z

SG@

Q17A

470 _04 02_5%

61

2

2N7002DW-7-F_S OT363-6

2N7002DW-7-F_S OT363-6

SG@

SG@

Q18B

1

2

C1081

10U_0805_10V4Z

NV VDD_PG#

3

5

4

+VDD_MEM+1.5V

1
2
35

1

SG@

4

2

C1079

NV VDD_PG

0.1U_0402_16V4Z

SG@

Q18A

SG@

2

12

R917

470 _04 02_5%

61

2N7002DW-7-F_S OT363-6

Discharge circuit DIM LED

+1.5VS

12

R590

470 _0402_5%

61

Q8A

SUS PSUSP SUS PSUS P SY S ON#S USP

2

2N7002DW-7-F_S OT363-6

H15

H14

H13
HOLE A

1

HOL EA

1

HOLE A

1

4

470 _0402_5%

Q9B

12

R587
100 K_0 402_5%

3

Q6B

5

4

H11
HOLE A

1

R589

5

1

+3VS

12

3

4

H12
HOL EA

1

2N7002DW-7-F_S OT363-6

+5VS

12

B B

SY SON#<45> SUSP <45>

A A

H1
HOLE A

1

SY SON<31,37,3 8,48> SUS P# <31,37,41,44,45>

H2

H3
HOLE A

1

H4
HOLE A

1

5

HOL EA

1

470 _0402_5%

R586

100 K_0 402_5%

Q6A

2

H6

H5

HOLE A

HOL EA

1

Q9A

+3VL

1

2

R588

12

61

61

2N7002DW-7-F_S OT363-6

H7
HOL EA

1

2N7002DW-7-F_S OT363-6

+3VL

2N7002DW-7-F_S OT363-6

H8
HOLE A

+VCCP +0.7 5VS

12

R591

470 _0402_5%

3

Q8B

5

4

2N7002DW-7-F_S OT363-6

H17
HOL EA

1

H18
HOLE A

1

H16
HOLE A

1

R592

470 _04 02_5%

Q7A

2

1

1

+1.5V

12

61

2N7002DW-7-F_S OT363-6

FM2

FM1

1

FM4

FM3

1

12

R593

470 _04 02_5%

3

Q7B

5

4

2N7002DW-7-F_S OT363-6

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

DIM_LE D<37>

Deciphered Date

DI M_L ED

2

+5VS +5VS_LED

SI2301BDS-T1-E3_SOT23-3

S

12

R582

10K _0402_5%

DIM_LE D#

13

D

Q27

2

2N7002_SOT23-3

G

S

Q26

D

13

G

2

Title

Size Do cument Number Re v

Da te: Sheet o f

1

C670

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

DC/DC Interface

Ca lpella DI S LA4743P

39 49Monday, April 13, 2009

1

0.1

A

B

C

D

+3VALW

PQ3
TP0610K-T1-E3_SOT23-3

1 2

1 1

100K_0402_5%

2

1 3

PR8
2K_0402_5%

1 2

ADP_SIGNAL

J DC

6

GND

5

GND

4

4

3

3

2

2

1

1

ACES_87302-0441

2 2

ADPINAD PIN

1 2

PR3
10K_0402_5%

2

3

PD1

@PJSOT24C_SOT23-3

1

PR9

12

+3VL

PC2

100P_0402_50V8J

connect to KBC pin97

AC_LED# <37>

12

PR2
10K_0402_5%

12

PD4

RLZ3.6B_LL34

PL1

HCB2012KF-121T50_0805

1 2

PL2

HCB2012KF-121T50_0805

1 2

12

PC3
1000P_0402_50V7K

12

12

PC4

100P_0402_50V8J

PC12
@1000P_0402_50V7K

VIN

12

PC5

1000P_0402_50V7K

ADP_ID <37>

BATT

12

+5VALW

PR1

340K_0402_1%

12

PR4

499K_0402_1%

12

PC6

0.01U_0402_25V7K

12

PR6

105K_0402_1%

12

PC1

0.01U_0402_25V7K

3
2

PU1A

LM358ADT_SO8

8

P

+

1

0

-

G

PR5

10K_0402_5%

12

BATT_OVP <37>

4

JBATT

1

BATT+

2

SMD

3

SMC

4

B/I

GND

5

TS

6

PR16

6.49K_0402_1%

1 2

12

PR17
1K_0402_5%

7

GND

8

GND

SUYIN_200275MR006G113ZL

3 3

4 4

EC_SMD
EC_SMC

PD3

3

1

2

PJSOT24C_SOT23-3

BAT_ID <41>

+3VL

12

PR13

100_0402_5%

PD2

3
2

PJSOT24C_SOT23-3

12

PR14
100_0402_5%

BATT_TEMP <37>

1

VMB

SMB_EC_DA1

SMB_EC_CK1

PL3

HCB2012KF-121T50_0805

1 2

PL4

HCB2012KF-121T50_0805

1 2

12

PC8
1000P_0402_50V7K

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

BATT

PC9

0.01U_0402_50V4Z

SMB_EC_DA1 <37,38>

SMB_EC_CK1 <37,38>

0.22U_0603_10V7K

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C

+5VS

CPU

12

PH1

10K_TH11-3H103FT_0603_1%

PR10

200K_0402_1%

1 2

+5VALW

12

12

PC10

2.49K_0402_1%

2007/05/29 2008/05/29

1 2

PR11

150K_0402_1%

PR12

150K_0402_1%

Compal Secret Data

Deciphered Date

C

12

PR15

PR7

604K_0402_1%

1 2

5

+

6

-

12

PC11
1000P_0402_50V7K

8

P

7

0

G

PU1B

4

LM358ADT_SO8

EN0 <42>

13

D

2

G

Title

Size Document Number R ev

Date: Sheet o f

Compal Electronics, Inc.

DC Connector/CPU_OTP

PQ1
SSM3K7002FU_SC70-3

S

Calpella DIS LA4743P

D

40 49Monday, April 13, 2009

0.1

A

V IN

1 1

PC1 01

47 P_0402_5 0V8J

PR107
47K_0402 _1%

1 2

PQ107

13

SSM3 K70 02FU_SC70-3

2 2

D

2

G

S

PA C IN

ACO FF#

PR101

47 K_0402_5 %

1 2

12

2

13

2

PQ105
DT C11 5EUA_SC70 -3

PR1 11

3K_0402_ 1%

1 2

PD1 01

1 2

1SS 355_SOD323-2

PQ101
AO4 433_SO8

8
7

5

PQ104

DT A144EUA_SC70-3

1 3

PQ109

13

D

SSM3 K70 02 FU_SC70-3

2

G

S

VCT RL<37>

1
2
36

4

PC106

1 2

1U_ 0603 _10V6K

P2

12

0.1 U_0603_16V7K

PR114
@0_0402 _5%

PC117

1
2
3 6

12

PR106

20 0K_0402_ 5%

12

PR1 09
15 0K_0402_ 5%

14 3K_0402_ 1%

12

PR113

PQ103

AO4 409_SO8

4

12

12

8
7

5

AC_ SET<37>

PR115
100K_040 2_1%

@0. 01U_0402_16V7K

SUSP #<31, 37,39 ,44,45>

1 2

1U_ 0603 _6.3V6M

PC1 12

ADP_I<37>

Charge Detector

V IN

PD104
1SS 355_SOD323-2

PR123

1 2

1M_0402_5%

1 2

3 3

V IN

12

PR131
13 3K_0402_ 1%

12

PR135
10 K_0603_0.1%

4 4

1.2 4VREF

3
2

VIN _1

12

8

+

-

4

PR1 25
47_1206 _5%

12

P

1

O

G

PU10 2A
LM3 93DG_SO8

PC125

0.1 U_0603_25V7K

+3VL

12

PR129

10 K_0402_1 %

STD_ADP <37>

+3VL

PR1 28

2

G

12

10 K_0402_5 %

CH GEN#

13

D

S

FST CHG<37>

PQ112
SSM3 K70 02 FU_SC70-3

FST CHG#

1 2

PR137
20K_0402 _1%

PC1 20

+3VL

PR1 32

10 0K_0402_ 5%

2

G

ACD ET

12

100K_040 2_1%

PR104
0_0402_ 5%

1 2

PC1 07

PR110
0_0402_ 5%

1 2

BQ2 4740VREF

PR1 16

39K_0402 _5%

1 2

12

0.2 2U_0603_10V7 K

12

13

D

PQ113
SSM3 K70 02 FU_SC70-3

S

PR138

B

12

+3VL

12

PR118

10K_0402 _5%

0.1 U_0 402_10V7K

ACS ET

ACS ET

12

PR1 40
10 0K_0402_ 5%

8

IADSLP

9

AGND

10

VREF

11

VDAC

12

VADJ

13

EXTPWR

14

ISYNSET

PC1 21

PC123

ACD ET

6

7

LPREF

ACSET

IADAPT

SRSET

15

16

IAD APT

12

10 0P_0402_50V8J

12

P4

PR102

1
2

0.0 12_251 2_1%

1 2

PC102

1U_ 0603 _6.3V6M

12

PC1 08

A CP

0.1 U_0603_25V7K

3

4

5

ACP

LPMD

ACDET

PU10 1
BQ2 4740R HDR_ QFN28_5X5

SRP

BAT

SRN

19

17

18

BATT

133K_040 2_1%

12

PR121
200K_040 2_1%

B+

4
3

1 2

A CN

CH GEN#

1

2

ACN

CHGEN

PVCC

BTST

HIDRV

REGN

LODRV

PGND

DPMDET

CELLS

21

20

SSM3 K70 02 FU_SC70-3

PR1 20

12

PL101
HCB2 012KF-121T50_0805

12

29

TP

PC110
1U_ 0805 _25V6K

28

1 2

0_0402_ 5%

BST _CHG

27

1 2

0_0402_ 5%

DH _ CHG D H_ CHG1

1 2

26

LX_CHG

25

PH

RE GNVADJ

24

D L_C HG

23

22

12

PC119
1U_ 0603 _10V6K

13

D

PQ111

S

IRE F <37>

12

PC1 03

4.7 U_0805_25V6-K

PR1 08
10_1206 _5%

1 2

PR1 42

PR1 39

PD1 02

12

1SS 355_SOD323-2

PR117

100K_040 2_5%

1 2

2

G

12

PC1 05

PC1 04

4.7 U_0805_25V6-K

PC111

1 2

0.1 U_0402_10V7K

PQ110

AO4 468_SO8

BQ2 4740VREF

12

47 K_0402_5 %
PR119

PC124

0.1 U_0603_25V7K

C

PQ102
AO4 407_SO8

1
2

0.0 15_120 6_1%

1 2

PC114

4.7 U_0805_25V6- K

0.1 U_0 402_10V7K

3 6

PR112

1 2

PC118

CHG_B+

4.7 U_0805_25V6-K

CHG_B+

PQ108
AON7 40 8L_ DFN8-5

PL102

3 5

241

10 U_LF 919AS-100 M-P3_4.5A_20%

1 2

12

578

PR1 41

@4. 7_1206_ 5%

12

12

PC113

4.7 U_0805_25V6- K

3 6

241

PC135
@47 0P_ 0603_50V8J

1 2

BAT _ID <40>

8
7

5

4

ACO FF#

BATT

12

12

PC115

4.7 U_0805_25V6- K

D

BATT

PR103

47 K_0402_5 %

1 2

12

PR1 05
10 K_0402_5 %

13

PQ106
DT C11 5EUA_SC70 -3

12

PC122

PC116

4.7 U_0805_25V6- K

4.7 U_0805_25V6- K

V IN

2

ACO FF <37>

12

PR122
68 1K_0402_ 1%

1 2

PR127

10 K_0402_1 %

PR1 24
1K_ 0402_5%

1 2

12

PR134
10K_0402 _5%

ACIN <37>

PA C IN

1.2 4VREF

PC1 26

0.0 47 U_0402_16 V7K

PR1 26

100K_040 2_1%

12

V IN

12

PR130

2.1 5K_0402_1%

1 2

12

PR133
10 K_0603_0 .1%

PC127

22 P_0402_50V8J

V IN

12

8

PU10 2B

5

P

+

7

O

6

-

G

LM3 93DG_SO8

4

PR1 36

60 .4K_0402_1%

1 2

4

12

REF

5

ANODE

LMV 431ACM5X_SOT23-5

PD103

RLZ 4.3 B_LL34

PU10 4

CATHODE

V IN_1

NC
NC

12

3
2
1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/05/29 2008/05/29

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Doc ume nt Number R ev

Dat e: Sheet

Charger

Calpella DIS LA4743P

D

of

41 49M ond ay, Ap ril 13, 2009

0.1

A

B

C

D

E

2VREF_51125

1 1

12

PC313

0.1U_0402_25V6

+3VALWP

B++

12

PC301

100 0P_ 0402_50V7K

SSM3K7 002 FU_SC70-3

12

PC303

4.7U_0805_25V6-K

4.7UH_SIQB74B-4R7PF_4A_20%

1

PC309

+

2

150 U_B_6.3 VM_R45M

PQ305

PL302

+3VLP

PQ301
AON7408 L_DFN8-5

10U_0805_6.3V6M

UG1_ 3V

3 5

241

PR309

0_0 402_5%

12

12

PR315

4.7_1206_5%

12

E NTRIP1

13

D

2

G

S

123

PC314

680 P_0 603_50V8J

2

G

PQ307

13

D

SSM3K7 002 FU_SC70-3

2

G

S

5

1 2

1 2

PQ303

4

AON7406 L_DFN8-5

E NTRIP2

13

D

PQ306
SSM3K7 002 FU_SC70-3

S

PR313
100 K_0 402_5%

12

PR314
100 K_0 402_5%

PC306

VL

12

1 2

1 2

0_0 402_5%

PC307

0.1U_0402_10V7K

LX_3V

B++

EN0<40>

EC_ON <37>

PR307

LG_3V

1M_0402_1%

1 2

191 K_0 402_1%

PR312

B+

2 2

3 3

PL301

HCB2 012 KF-121T50_0805

1 2

13.7K_0402_1%

20K _0402_1%

105 K_0 402_1%

BST_3V

UG_3V

PR311

+5V ALWP

+3V ALWP

0.22U_0603_10V7K

PR301

1 2

PR303

1 2

PR305

1 2

25

7
8

9
10
11
12

12

2VREF_51125

PC302

E NTRIP2

6

P PAD

ENTRIP2

VO2
VREG3
VBST2
DRVH2
LL2
DRVL2

EN0

13

PJP 302

1 2

PA D-OPEN 4x4m
PJP 303

1 2

PA D-OPEN 4x4m

12

PR302

30.9K_0402_1%

1 2

PR304
20K _0402_1%

1 2

PR306
115 K_0402_1%

E NTRIP1

1 2

3

1

2

5

4

VFB1

VFB2

VREF

TONSEL

ENTRIP1

24

VO1

23

PGOOD

VBST1

DRVH1

DRVL1

VREG5

GND

VIN

SKIPSEL

14

VCLK

PU301

17

15

16

18

TPS51125RGER_QFN24_4X4

BST_5V

22

UG_5V

21

LX_5V

20

LL1

LG_5V

19

VL

12

PC311
10U_0805_10V6K

12

B++

PC312

0.1U_0603_25V7K

(4.5A,180mils ,Via NO.= 9)

+5V ALW

(3A,120mils ,Via NO.= 6)

+3V ALW

1 2

PR308

0_0 402_5%

1 2

PR317

0_0 402_5%

B++

12

PC304

PC316

0.1U_0402_25V6

PC308

0.1U_0402_10V7K

1 2

R_EC_RSMRST # <13>

12

100 0P_ 0402_50V7K

1 2

12

PC305

PR310
0_0 402_5%

10U_1206_25V6M

PQ304

STL8NH3 LL

4

3 5

5

+3VLP

VL

241

PQ302
AON7408 L_DFN8-5

PR316

4.7_1206_5%

123

2 1

PA D-OP EN 2 x2m

2 1

PA D-OP EN 2 x2m

PL303

4.7UH_PCMC06 3T-4R7MN_5.5A_20%

1 2

12

1

+

PC310

+3VL

+5VL

150 U_B_6.3 VM_R45M

2

12

PC315

680 P_0 603_50V8J

PJP 301

PJP 304

+5VALWP

4 4

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

Cu st om

D

Da te: Sheet o f

Compal Electronics, Inc.

3.3VALWP/5VALWP

Ca lpella DI S LA4743P

42 49Monday, April 13, 2009

E

0.1

5

CPU_B+

4

3

2

1

12

D D

PR404

10_0402_5%

1 2

VSS_AXG_SENSE<9>

VCC_AXG_SENSE<9>

+VGA_CORE

C C

B B

PR406

10_0402_5%

1 2

150P_0402_50V8J

PC421

1 2

PC411
1000P_0402_50V7K

1 2

PC412
330P_0402_50V7K

PR413

8.66K_0402_1%

12

12

PR416

17.8K_0402_1%

825K_0402_1%

1 2

12

12

PR414

1 2

PC417

100P_0402_50V8J
PC422

22P_0402_50V8J

1 2

GFXVR_PWRGD
GFXVR_CLKEN#

PC413
330P_0402_50V7K

12

PC401

PC402

1000P_0402_50V7K

PC418

1000P_0402_50V7K

12

12

PR417

8.06K_0402_1%

10U_1206_25V6

12

12

PC406

10U_1206_25V6

PC403

0.1U_0402_25V6

+5VALW

PR401

1_0603_5%

12

12

PC407
1U_0603_6.3V6M

29

AGND

7

VSEN

6

FB

5

COMP

4

PR409

47K_0402_1%

+VGA_CORE

12

PR419

12

PR420

@10K_0402_1%

@1.91K_0402_1%

VW

3

12

RBIAS

2

PGOOD

1

CLK_EN#

PR402

0_0603_5%

ISUM+

ISUM-

9

10

8

28

11

12

RTN

PU401
ISL62881HRZ-T _QFN28_4X4

VIN

VDD

ISUM

ISUM+

VID5

VID626VR_ON27DPRSLPVR

25

24

1 2
12

13

IMON

VID323VID4

PC408

0.22U_0603_25V7K

BST_GFX

14

BOOT

UGATE
PHASE

VSSP

LGATE

VCCP

VID0
VID1

VID2

22

12

PR403

22.6K_0402_1%

1 2

PR405

2.2_0603_5%

15

LX_GFX

16
17

DL_GFX

18
19
20
21

12

PC409

0.22U_0402_6.3V6K

1 2

PC410

0.22U_0603_16V7K

PR407

0_0603_5%

1 2

PR410

1 2

0_0603_5%

12

PC419

2.2U_0603_6.3V6K

GFXVR_IMON <9>

VSS_AXG_SENSE

DH_GFX1D H_GFX

+5VALW

TPCA8028_PSO8

PR4210_0402_5%

12

PR4220_0402_5%

12

PR4250_0402_5%

12

PR4260_0402_5%

12

PR4270_0402_5%

12

PR4280_0402_5%

12

PR4300_0402_5%

12

PR4310_0402_5%

12

PR4320_0402_5%

12

578

PQ401
AO4474_SO8

3 6

241

3 5

241

PQ402

GFXVR_VID_0 <9>
GFXVR_VID_1 <9>
GFXVR_VID_2 <9>
GFXVR_VID_3 <9>
GFXVR_VID_4 <9>
GFXVR_VID_5 <9>
GFXVR_VID_6 <9>
GFXVR_EN <9>
GFXVR_DPRSLPVR <9>

12

PR408

4.7_1206_5%

PC420

1 2

680P_0603_50V7K

ISUM+
ISUM-

PL402

4
3

12

PR411

3.65K_0805_1%

1 2

PR415

2.61K_0402_1%

1 2

11K_0402_1%

PC423

0.1U_0402_16V7K

PC424

0.033U_0402_16V7K

PR429

82.5_0402_1%

1 2

1
2

0.56UH_MMD-10CZ-R56M-M1_19A_20%

PH401

1 2

10KB_0603_5%_ERTJ1VR103J

PR418

1 2

1 2

PR423

3.01K_0402_1%

1 2

PC425

0.01U_0402_16V7K

12

PR412
0_0402_5%

1 2

PR424
100_0402_1%

1 2

PC426
180P_0402_50V8J

1 2

+VGA_CORE

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/31 2009/10/31

3

Compal Secret Data

Deciphered Date

Title

Size Document Number R ev

Cu stom

2

Date: Sheet o f

Compal Electronics, Inc.

VCCGFX

Calpella DIS LA4743P

1

43 49Monday, April 13, 2009

5

4

3

2

1

PR517
0_0402_5%

PR518
10_0402_5%

VTTPWRGOOD<6>

PC506

0_0402_5%

VTT_SELECT<9>

12

12

12

PR513

26.7K_0402_1%

0.022U_0402_25V7K@

PR506
0_0402_5%

12

PR5080_0402_5%

12

12

PR520

174K_0402_1%

PR501

1 2

PR502

10.5K_0402_1%

1 2

PR505

0_0402_5%

1 2

12

PC524

BST_1.1VTT

12

UG_1.1VTT

LX_1.1VTT LX_1.05V

LG_1.1VTT

25

10
11
12

7
8
9

PU501

P PAD

PGOOD2
EN2
VBST2
DR VH2
LL2
DR VL2

6

VO2

PGND2

13

PR510

14.7K_0402_1%

1 2

2

5

3

4

GND

VFB1

VFB2

TONSEL

TRIP1

V5FILT

V5IN

TRIP2

17

15

16

14

PR511

12.1K_0402_1%

1 2

1 2

PR514

3.3_0402_5%

12

1U_0603_10V6K
PC513
@0.1U_0402_16V7K

PC514

12

12

PC515

4.7U_0805_10V6K

PR503

75K_0402_1%

1 2

1

VO1

24

PGOOD1

23

EN1

BST_1.05V

22

VBST1

21

DR VH1

20

LL1

LG_1.05V

19

DR VL1

PGND1

TPS51124RGER_QFN24_4x4

18

+5VALW

PR504

29.4K_0402_1%

1 2

12

PC512
@0.1U_0402_16V7K

PR507

0_0402_5%

PR509

0_0402_5%

0_0402_5%

1 2

12

PR512

+1.05VSP

12

PQ501
AON7408L_DFN8-5

PC507

0.1U_0402_10V7K

1 2

UG1_1.05V

SUSP#

B+++

3 5

241

PQ503
FDMC8296_POWER33-8-5

3 5

241

PL502

HCB2012KF-121T50_0805

12

12

PC503

10U_1206_25V6

B+

12

12

PC521

0.1U_0402_25V6

PC505

1000P_0402_50V7K

PL501

2.2UH_PCMC063T-2R2MN_8A_20%

1 2

12

PR516

4.7_1206_5%

12

PC519

680P_0603_50V7K

1

+

PC508

2

+1.05VSP

220U_B2_2.5VM_R25M

D D

VTT_SENSE<9>

B+++

12

12

PC511

PC501

C C

10U_1206_25V6

4.7U_0805_25V6-K

12

12

0.1U_0402_25V6

PC502

1000P_0402_50V7K

PC520

+1.1VTT

1

2

680P_0603_50V7K

330U_X_2VM_R6M

PL503

4.7_1206_5%

PC518

12

PR515

0.47UH_FDV0630-R47M-P3_18A_20%

+

PC523

B B

+VCCP

1

+

PC517

2

1

+

PC522

2

330U_X_2VM_R6M

330U_X_2VM_R6M

VTT_SENSE

+1.1VTT

578

PQ502
AO4474_SO8

0.1U_0402_10V7K

3 6

241

UG1_1.1VTT UG_1.05V

12

PQ504
TPCA8028_PSO8

12

3 5

241

SUSP#<31,37,39,41,45>

PJP501

+1.05VSP

A A

+1.1VTT

1 2

PAD-OPEN 4x4m

PJP502

1 2

PAD-OPEN 4x4m
PJP503

1 2

PAD-OPEN 4x4m

5

+1.05VS

(6A,240mils ,Via NO.= 12)

+VCCP

(14A,240mils ,Via NO.= 28)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/05/29 2008/05/29

3

Compal Secret Data

Deciphered Date

Title

Size Document Number R ev

2

Date: Sheet o f

Compal Electronics, Inc.

1.1VTTP/1.1VSP

Calpella DIS LA4743P

44 49Monday, April 13, 2009

1

0.1

5

D D

C C

PJ P60 1

+0 .75VSP

+1 . 1V_ PCI E

B B

+1 .8 VSP

1 2

PA D- O PE N 3 x3m

PJ P60 3

1 2

PA D- O PE N 3 x3m

PJ P60 2

1 2

PA D- O PE N 3 x3m

(2A,80mils ,Via NO.= 4)

+0 .75VS

(2A,80mils ,Via NO.= 4)

+P CIE

(1.5A,60mils ,Via NO.= 3)

+1 .8VS

4

+1. 5V

12

12

PC 60 1

10 U_080 5_10V 4Z

SYSON#<39>

SUSP<39>

1 2

PR 60 2

@0 _0 402 _5%

SS M3 K70 02FU_S C70 -3

1 2

PR 60 4

0_ 040 2_5%

SUSP#<31,37,39,41,44>

PQ 601

2

12

PC 60 6
@0 .1U_0 402 _1 6V7 K

SU S P#

0.01U _04 02 _16 V7K

PC 60 2

G

1 2

PR 60 9

0_ 040 2_5%

PC 61 7

@1 0U _0 805 _10V4 Z

13

D

S

12

PR 60 1
1K_ 04 02_ 1%

12

PR 60 3
1K_ 04 02_ 1%

PU 60 2

7

POK

8

EN

12

APL59 15KAI- TRL _SO 8

3

PU 60 1

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2 9 92 F1U_SO8

6
5

NC

7

NC

8

NC

9

TP

12

PC 60 3
1U_06 03_16 V6K

+5VALW

2

1

+0.75VSP

12

12

PC 60 5
10 U_0 805_6 .3V 6M

0.1U_ 040 2_ 16V 7K

PC 604

+5 VALW

12

PC 60 9
1U_06 03_6. 3V6 M

6

PU 603

7

POK

DGPU_PWR_EN<14,23,39,47>

+5 VALW

PC 61 8

12

1U_06 03_6. 3V6 M

6

5

VIN

4

VOUT

VCNTL

3

VOUT

2

FB

9

GND

TP

1

PR 61 1

15 K_0 402 _1 %

12

12

PC 61 4
15 0P_ 040 2_ 50V 8J

+3 VS

12

+1.8VSP

12

PC 616
22 U_0 805_6 .3V 6M

PC 615
10 U_0 805_1 0V6K

@0 .01U_ 040 2_ 16V 7K

1 2

PR 60 6

0_ 040 2_5%

PC 61 1

8

EN

12

AP L5 913 -KAC-T RL_ SO8

5

VIN

9

VIN

VCNTL

3

VOUT

4

VOUT

2

FB

GND

1

PR 60 7

15 K_0 402 _1%

12

12

PR 60 8

39 .2K_04 02_1%

12

12

PC 613
@47P_040 2_50V 8J

+1 .5VS

12

PC 61 0
10 U_0 805_1 0V6 K

+1.1V_PCIE

PC 61 2
22 U_0 805_6 .3V 6M

12

PR 61 0

12 K_0 402 _1%

A A

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/11/23 2007/11/23

Compal Secret Data

Deciphered Date

2

Tit le

Size Do c um en t N umb er R e v

Da te : She et o f

Compal Electronics, Inc.

0.75VP/1.8VSP/1.1V_PCIE

Ca lp ella DIS L A4743P

1

45 49Monda y, Apr il 13, 2009

0. 1

8

H H

H_ VID0<9>
H_ VID1<9>
H_ VID2<9>
H_ VID3<9>
H_ VID4<9>
H_ VID5<9>
H_ VID6<9>

G G

H_DPRSL PVR<9>

+3VS

VGATE<13,19>

F F

E E

12

@

PR234

24 9K_0402_ 1%

D D

PC227

15 0P_0402_50V8J

C C

VC CSE NSE

B B

VSSSENSE<9 >

A A

VR _ON<37>

CLK _EN#<19>

PR2 19
0_0402_ 5%

H_PR OCHO T#<6>

12

PR235

8.0 6K_04 02_1%

1 2

10 P_0402_5 0V8K

1 2

PR209 0 _0402_5%

1 2

H_P SI#<9>

1 2

PR223 1 47 K_0402_1%

+VC CP

12

PC222

10 00P_0402_50V7K

PC2 25

1 2

PR2 41
41 2K_0402_ 1%

1 2

PR252 0_040 2_5%

PR2 63 0 _0402_5%

1 2

8

1 2

+VC CP

PR212

1.9 1K_0402_1%

1 2

12

PR217

1.9 1K_04 02_1%

+V CCP

68_0402_5%

1 2

PR225 0_0402_5 %

PR236
562_0402_1%

1 2

PR2 38

2.4 3K_04 02_1%

IS EN2
IS EN1

PR2 81

1K_0402_ 1%

PR290

1K_ 0402_1%@

PR221 1 K_0 402_5%@

1 2

PR222 0_040 2_5%

1 2

PR2 82

1K_ 0402_1%

PR224

1 2

PC221

22 P_0402_50V8J

39 0P_0402_ 50V7K

1 2

PC2 24

33 0P_0402_50V7K

10 00P_0402_50V7K

12

PR2 10 499_0402_1%

1 2

12

12

12

0.2 2U_0402_1 0V4Z

PC232

PC245

PC2 47

7

1
2
3
4
5
6
7
8
9

10
41

12

PC233

12

12

7

PR201 0 _0402_5%

1 2

PR202 0 _0402_5%

1 2

PR203 0 _0402_5%

1 2

PR204 0 _0402_5%

1 2

PR205 0 _0402_5%

1 2

PR206 0 _0402_5%

1 2

PR207 0 _0402_5%

1 2

CLK _EN#

39

40

PU20 1

CLK_EN#
PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2

AGND

ISEN111VSEN12RTN13ISUM-14ISUM+15VDD

0.2 2U_0402_1 0V4Z

PC248

12

33 0P_0402_ 50V7K

12 00P_0402_50V7K

6

+VC CP

@

1 2

1 2

1K_0402_ 1%

PR278

PR277

@

1 2

1 2

1K_0402_ 1%

PR2 89

PR2 75

PC212
1U_ 0603 _10V6K

1 2

12

PC223

1U_ 0603 _10V6K

@

1 2

1K_0402_ 1%

1K_0402_ 1%

PR279

1 2

1K_0402_ 1%

1K_0402_ 1%

PR2 88

+5V ALW

1 2

0_0402_ 5%

PR228

CPU_B +

+5V ALW

8.2 5K_0402_1%

1 2

1K_0402_ 1%

PR280

@

1 2

1K_0402_ 1%

PR2 87

PR239 0_040 2_5%

PR2 46

1 2

1K_0402_ 1%

PR283

@

1 2

1K_0402_ 1%

PR2 86

1 2

12

1 2

1K_0402_ 1%

PR284

@

1 2

1K_0402_ 1%

PR2 85

12

PC230

0.2 2U_0603_25V7 K

VSSSENSE

VSUM+

IMVP_IMON <9>

@

1 2

1K_0402_ 1%

PR276

1 2

1K_0402_ 1%

PR2 74

37

35

38

VID031VID132VID233VID334VID536VID6

VID4

VR_ON

DPRSLPVR

16

BOOT2

UGATE2

PHASE2

VSSP2

LGATE2

VCCP

PWM3

LGATE1

VSSP1

PHASE1

ISL6 28 83HR Z-T_QF N40_5X5

VIN

IMON18BOOT119UGATE1

17

20

1 2

1 2

12

12

PC228

PC229

1U_ 0603 _10V6K

30
29
28
27
26
25
24
23
22
21

PR2 42 0 _0402_5%

PR2 44 1 _0402_5%

0.2 2U_0603_25V7 K

12

12

PC2 49

12

1 2

82.5_0402_1%

PR250

PC2 44

0.0 1U_0402_25V7 K

PR260

1.1 K_0402_1%

1 2

100_040 2_1%

1 2

PR2 65

12

PC241

@27 00P_0 402_50V7K

PC2 42

PR261

0_0402_ 5%

0.2 2U_0603_10V7 K

PR251

2.6 1K_0402_1%

0.0 47 U_0603_16 V7K

PC2 43

12

12

12

PR262

11 K_0402_1 %

PH20 2
10 KB_0 603_5 %_ERTJ1VR103J

VSUM-

12

PC2 50

0.1 U_0402_16V7K

6

BOO ST_ CPU2
UGAT E_CPU2
P HASE_ CPU2

LGATE_ CPU2

5

PR208

0_0603_ 5%

12

BOO ST_ CPU1

UGAT E_CPU1

PR2 48
0_0603_ 5%

P HASE_ CPU1

LGATE_ CPU1

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PC210

0.2 2U_ 0603_10V7 K

1 2

PR243

0_0603_ 5%

12

Issued Date

4

PR213

0_0603_ 5%

12

PC240

0.2 2U_ 0603_10V7 K

1 2

4

3

CPU_B +

12

12

12

PC205

10 U_1206_25V6

10 00P_0402_50V7K

578

3 6

241

PQ202
AO4 474_SO8

PC203

PC204

0.1 U_0402_25V6

12

PQ203

12

PR2 11

4.7 _1206_ 5%

4

TPC A80 28-H_S OP-ADVANCE8-5

123 5

578

PQ205
AO4 474_SO8

3 6

241

4

12

PC2 34

0.1 U_0402_25V6

PQ206

TPC A80 28-H_S OP-ADVANCE8-5

123 5

2007/05/29 2008/05/29

Compal Secret Data

Deciphered Date

3

12

PC2 11

68 0P_0603_ 50V7K

12

PC2 35

10 00P_0402 _50V7K

12

PR253

4.7 _1206_ 5%

12

PC246

68 0P_0603_ 50V7K

2

PL202

HCB2 012KF-121T50_0805

12

PL205

HCB2 012KF-121T50_0805

12

12

PC206

10 U_1206_25V6

0.3 6UH_ PCMC 104 T- R36MN1R17_30A_20%
PL201

1

4

LF2

3

12

12

PR2 15

10K_0402 _5%

3.6 5K_0603_1%

PR2 14

IS EN2

VSUM+

CPU_ B+

12

12

PC2 37

10 U_1206_25V6

PC2 36

10 U_1206_25V6

LF1

12

12

PR256

PR255

10K_0402 _5%

3.6 5K_0603_1%

IS EN1

VSUM+

Iccmax= 35A
I_TDC=TDB
OCP=TDBA, Intel spec=TDBA

Title

Size Doc ume nt Number Re v

Dat e: Sheet of

2

2

0.3 6UH_ PCMC 104 T- R36MN1R17_30A_20%

PL204

4
3

Compal Electronics, Inc.

+CPU_CORE

Calpella DIS LA4743P

1

B+

1

1

+

+

PC202

PC209

10 0U_25V_M

10 0U_25V_M

2

2

+VC C_C ORE

V 2N

12

PR216
1_0402_ 5%

VSUM-

1
2

VSUM-

+VC C_C ORE

V 1N

12

PR2 57
1_0402_ 5%

46 49M ond ay, April 13, 2009

1

0.1

A

1 1

PR701

0_0402_5%

DGPU_PWR_EN<14,23,39,45>

2 2

+N VVDDP

3 3

4 4

PR703

0_0402_5%

1U_0603_10V6K

PR702

316_0402_1%

12

PC702

1 2

@1000P_0402_50V7K

+5VALW

+5VALW

12

12

12

PC701

+VGA_COREP1

0_0402_5%

+N VVDD_SENSE

PR714

12

+NVVDD_SENSE

5.11K_0402_1%

12

PR713
10_0402_5%

+NVVDDP

1 2

PR708

1 2

PC713

@1000P_0402_50V7K

PR711

75K_0402_1%

PR705
255K_0402_1%

1 2

12

12

PR712

76.8K_0402_1%

PR721

0_0402_5%

12

34

2
3
4
5
6

NVVDD_PG <39>

B

1

PU701

TON

EN_PSV

VOUT
V5FILT
VFB
PGOOD

GND7PGND

8

PR718

1 2

38.3K_0402_1%

PQ713B
2N7002KDW-2N_SOT363-6

5

1 2

12

PC714

0.022U_0402_16V7K

BST_VGA

14TP15

VBST

DRVH

LL

TRIP

V5DRV

DRVL

TPS51117RGYR_QFN14_3.5x3.5

PQ713A
2N7002KDW-2N_SOT363-6

6 1

1 2

PR704

0_0402_5%

13
12
11
10
9

1 2

PC706

0.1U_0402_10V7K

DH _VGA
LX_VGA

+5VALW

DL _VGA

2

1 2

12

10K_0402_1%

PC715

0.022U_0402_16V7K

PR715

10K_0402_1%

12

PR716
10K_0402_5%

12

PC707

4.7U_0805_10V6K

PR717

GPU_VID0 <24>

1 2

PR707
0_0402_5%

1 2

PR706

7.15K_0402_1%

12

PR719
10K_0402_5%

C

DH _VGA_1

GPU_VID1 <24>

VGA_B+

3 5

241

PQ701
AON7408L_DFN8-5

@0.1U_0402_25V6

12

4.7U_0805_25V6-K

PC708

PC703

12

0.82UH_PCMC063T-R82MN_13A_20%

PL702

1 2

12

786

5

PQ702

4

AO4714_SO8

123

PR720

4.7_1206_5%

12

PC716
680P_0603_50V7K

GPU_VID1 GPU_VID0 +NVVDD

1
0
0

0
1
0

0.9V

0.85V

0.8V

D

PL701

HCB1608KF-121T30_0603

1 2

4.7U_0805_25V6-K

12

1000P_0402_50V7K

PC704

PC710

12

B+

12

PC705
2200P_0402_50V7K

+NVVDDP

22U_0805_6.3V6M

470U_D2_2VM_R4.5M

1

PC709

+

2

22U_0805_6.3V6M

PC712

PC711

12

12

+N VVDDP

PJP701

1 2

PAD-OPEN 4x4m
PJP702

1 2

PAD-OPEN 4x4m

A

(11A,489mils ,Via NO.= 22)

+N VVDD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2007/05/29 200810/11

Compal Secret Data

Deciphered Date

C

Title

Size Document Number R ev

Date: Sheet o f

Compal Electronics, Inc.

VGA_CORE

Calpella DIS LA4743P

D

47 49Monday, April 13, 2009

0.1

A

1 1

B

C

D

PR901

0_0402_5%

1000P_0402_50V7K@

1 2

PC901

+1.5VP

12

PR906

0_0402_5%

+5VALW

PR903

316_0402_1%

12

+5VALW

12

12

PC907
1U_0603_10V6K

PR904
255K_0402_1%

1 2

2
3
4
5
6

PU901

TON
VOUT
V5FILT
VFB
PGOOD

DH_1.5V_1
LX_1.5V

+5VALW
DL_1.5V

PC905

1 2

0.1U_0402_10V7K

12

1 2

PR905 0_0402_5%

1 2

PR90713.7K_0402_1%

PC908

4.7U_0805_10V6K

DH _1.5V

PQ901
AON7408L_DFN8-5

3 5

241

PQ902
FDMC8296_POWER33-8-5

BST_1.5V

1 2

PR902

0_0402_5%

1

14TP15

VBST

13

EN_PSV

DRVH

TRIP

V5DRV

DRVL

12

LL

11
10
9

SYSON

2 2

GND7PGND

8

3 5

241

+1.5VP

PR908

1 2

10.2K_0603_0.1%

TPS51117RGYR_QFN14_3.5x3.5

1.5V_B+

0.1U_0402_25V6
10U_1206_25V6

PC906

12

PC903

12

12

2.2UH_PCMC063T-2R2MN_8A_20%

1 2

PR909

4.7_1206_5%

1 2

PC913

680P_0603_50V8J

1 2

1000P_0402_50V7K

PC904

PL901

12

3 3

PR911

10K_0603_0.1%

+1.5VP

PJP901

1 2

PAD-OPEN 4x4m

+1.5V

(6A,240mils ,Via NO.= 12)

PL902

HCB1608KF-121T30_0603

1 2

B+

+1.5VP

1

+

PC909

1 2

OCP=9.8913(min)
MOSTemperature Factor=1.3 (100C)

PC910

2

4.7U_0805_6.3V6K
330U_B2_2.5VM_R15M

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2007/05/29 2008/05/29

Compal Secret Data

Deciphered Date

C

Title

Size Document Number R ev

Date: Sheet o f

Compal Electronics, Inc.

1.5VP

Calpella DIS LA4743P

D

48 49Monday, April 13, 2009

0.1

A

B

C

Version Change List ( P. I. R. List ) for Power Circuit

D

E

Page#

1 1

2 2

Title

Date

Request
Owner

Solution Description

Rev.Issue DescriptionItem

3 3

4 4

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

Cu st om

D

Da te: Sheet o f

Compal Electronics, Inc.

Power Changed-List History-1

Ca lpella DI S LA4743P

49 49Monday, April 13, 2009

E

0.1