Compal LA-4743P Schematics Rev0.1

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Auburndale rPGA989 with

3 3

4 4

A

Intel PCH(Ibex Peak-M) core logic

2009-04-13

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

Cu st om

D

Da te: Sheet o f

Compal Electronics, Inc.

Cover Sheet

Ca lpella DI S LA4743P

1 49Monday, April 13, 2009

E

0.1

A

B

C

D

E

Compal confidential

1 1

Nvidia
NB10M-GE

VRAM DDR3
128/512MB

page 28,29

2 2

Dis

HDMI Conn.

PCI-E BUS*4

Fan conn

page 24,25,26,27

Dis Dis(UMA)

Page 6

LCD Conn.

page 21

MUX

CRT

page 20

MUX

Dis(UMA)Dis

Level Shifter

page 23

page 23

Calpella Consumer 13.3" UMA +Switchable

32QFN

USB2.0 X12

P19

DDR3 SO-DIMM X2

BANK 0, 1, 2, 3

USB Card Reader

USB conn x3

BT Conn

USB Camera

Finger print

PCIE-Express 16X

UMA

UMA

UMA

Mobile Arrandale

2C CPU + GMCH

Socket-rPGA989

Page 6,7,8,9,10

DMI X4

Intel PCH

Ibex Peak-M
FCBGA 951

Page 11,12,13,14,15,16

CK505

Clock Generator
SLG8SP585VTR

DDR3 1066/1333 MHz 1.5V

Dual Channel

Azalia
SATA Master-1

SATA Slave

P17, 18

P33

P36

P36

P21

P36

Audio CKT

JMC261 (LAN
+Card reader)

3 3

Mini-Card

WLAN

P31

RJ45/11 CONN

P31

Mini-Card

WWAN

P32P32 P32

New Card

LPC BUS

SPI

SPI ROM 16M

P34

MX25L1605AM2C-15G

SATA HDD Connector

Codec_IDT92HD81

P34 P35

Audio Jack

P30

ENE

KB926

P38

SATA ODD Connector

P30

C

P37

Int.KBD

P38

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

D

USB Board Conn
USB conn x2

Capsense switch Conn

Title

Size Do cument Number Re v

Cu st om

Da te: Sheet o f

Compal Electronics, Inc.

Block Diagram

Ca lpella DI S LA4743P

E

2 49Monday, April 13, 2009

P33

P36

0.1

RTC CKT.

P21

LED

P36

ACCELEROMETER
ST

4 4

P27

Touch Pad CONN.

P39

SPI ROM
SST25VF080

K/B backlight Conn

P36

Security Classification

DC/DC Interface CKT.

A

P38

B

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

Symbol Note :

Voltage Rails

power
plane

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

1 1

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK
SML1DATA

KB926

KB926

PCH

PCH

PCH

O MEANS ON X MEANS OFF

+B

O
O
O
O
O

+5VALW

+3VALW

O
O
O
O

X
XX

XDP BATT

X V
X

V

X

Thermal
Sensor

X
X
X
X

X

X

X

+1.8V

O
O
O

X
X
X

SODIMM CLK CHIP

X
X

X

X

V V V

X

X

+5VS
+3VS
+1.5VS
+0.9V
+VCCP
+CPU_CORE
+2.5VS
+1.8VS

O
O

X
X
X
X

WLAN
WWAN

NB10M

NB10M-GE

Thermal
Sensor

X
X

X
X X
X

X

X

X

X
X

X

+3VALW +3VALW+3VS+3VS+3VS +3VS+5VL +5VL

45@ : means need be mounted when 45 level assy or rework stage.
BATT @ : means need be mounted when 45 level assy or rework stage.
CONN@ : means ME part

SG@ : means stuff when Switchable graphic

UMA@ : means stuff when UMA skus

VRAM@ : X76 level

8111DL@ : Only for Giga LAN
DEBUG@ : For debug
Cypress@ : Only For Cypress Capacitor sensor board

ENE@ : Only For ENE Capacitor sensor board

M3@ : Only For Intel DDR3 VREF

PA@ : Only For PA

PR@ : Only For PR

Cap sensor
board

V

X

X

X

X XXX X X X X X X

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build

NEW

G sensor

CARD

X X
X

X

V V

X

X

PCH I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

45172932L01：Switchable graphic
45172932L02：UMA only

USB assignment:

USB-0 Right side
USB-1 Right side
USB-2 Left side(with ESATA)
USB-3 X
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Finger Printer
USB-8 MiniCard(WWAN/TV)
USB-9 Express card
USB-10 X
USB-11 X

PCIe assignment:

PCIe-1 WWAN
PCIe-2 WLAN
PCIe-3 LAN
PCIe-4 New card
PCIe-5 X
PCIe-6 X

SATA assignment:

SATA0 HDD
SATA1 ODD
SATA2 X
SATA3 X
SATA4 ESATA
SATA5 X

HEX

A0

D2

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0

NB10M-GE SMBUS Control Table

D_EDID_DATA
D_EDID_CLK
D_CRT_DDC_DATA
D_CRT_DDC_DATA
HDMIDAT_VGA
HDMICLK_VGA

SOURCE LVDS CRT

NB10M

NB10M

NB10M

V

X
X

HDMI

X X

V

X

X

V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Re v

Cu stom

Da te: Sheet

Compal Electronics, Inc.

Notes List

Ca lpella DI S LA4743P

o f

3 49Monday, April 13, 2009

0.1

5

4

3

2

60mA

+3VAUX_BT

1

50mA

1A

D D

VIN

AC

C C

B+

7A

+V_BATTERY Dock con

0.3A

INVPWR_B+

2A

B++

LVDS CON

1.7A

+3VALW

+1.5VS

+5VALW

35mA

169mA

300mA

MDC 1.5

ICH9

LAN

3.39A5.89A

+3VS

RT5158

??mA

???A

1.3A0.58A

Mini card

New card

+5VS

35mA

10mA

25mA

20mA

10mA

1A

811mA

1.5A

250mA

1A

1A

+VDDA
IDT 9271B7

+5VAMP

Finger printer

+3VS_DVDD
ALC268

+3VALW_EC

SPI ROM

New card

PCH

+LCDVDD

LVDS CON

+3VS_CK505

Mini card (WLAN)

Mini card (TV tu/WWAN/Robeson)

1.8A

B B

3.7 X 3=11.1V

DC BATT

B+++

A A

CPU_B+ +VCC_CORE

5

11.05A1.9A

4.7A

+1.5V

1.05V_B+

+1.05VS PCH

10mA2A

4

38A/1.05V

3A

8 A

50mA

+VCCP

2.59A

CPU

CPU

DDR3 800Mhz 4G x2

+0.75V

162mA

??A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PCH

CPU

2007/08/28 2006/03/10

700mA

50mA

Compal Secret Data

Deciphered Date

ODD

SATA

PC Camera(4.75V)

2

Compal Electronics, Inc.

Title

Size Doc ume nt Number Re v

C

Calpella DIS LA4743P

Dat e: Sheet of

Power delevry

1

4 49Mon day , A pril 13, 200 9

0.1

A

1 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Re v

Cu stom

Da te: Sheet

Compal Electronics, Inc.

Notes List

Ca lpella DI S LA4743P

o f

5 49Monday, April 13, 2009

0.1

Layout rule 10m：il
width trace length <

0.5", spacing 20mil

D D

H_ P EC I<14 >

H_ P RO CH OT#<46 >

H_ THE RMT RIP#<14 >

H_ C PU R ST#

H_ P M_ SY NC<13 >

H_ C PU PW RGD

H_ C PU PW RGD<14>

PM _D R AM _P WRGD<13>

C C

From power

VT TP WR GO OD<44 >

BU F_ PL T_R ST#<14 >

5

R1 2 0_ 040 2_1%

1 2

R3 2 0_ 040 2_1%

1 2

R5 4 9.9_0 402_1%

1 2

R7 4 9.9_0 402_1%

1 2

TP _S KTOCC #

T1P AD

H_ C AT ER R#

R1 0

R1 5

R1 9

R2 0

R2 1

R2 3

R2 4

R2 5

R2 6

1.5K_040 2_1%

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

75 0_0 402_1%

H_ P EC I_ ISO

0_ 040 2_5%

H_ P RO C HOT #

H_ THE RM TRIP#_R

0_ 040 2_5%

H_ C PU RS T# _R

0_ 040 2_5%

H_ P M_ SY N C_R

0_ 040 2_5%

SY S_ A GE NT _PWRO K

0_ 040 2_5%

VC CPW RG O OD _0

0_ 040 2_5%

VD DPW RG O OD _R

0_ 040 2_5%

H_ P WR GD _ XDP_RH_ P WR GD _ XDP

0_ 040 2_5%

PL T_ RST #_R

12

R2 8

CO M P3
CO M P2
CO M P1
CO M P0

JC PU1 B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC , AU B_ CFD_ rPG A,R 1P0

C O NN @

MISC THERMAL

PWR MANAGEMENT

CLOCKS

DDR3

MISC

JTAG & BPM

4

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PM_EXT_TS#[0]
PM_EXT_TS#[1]

PRDY#
PREQ#

TRST#

TDI_M

TDO_M

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

TCK
TMS

TDO

3

CL K _C P U_B CLK

A16

CL K _C P U_B CLK #

B16

CL K _C PU _XD P

AR30

CL K _C PU _XD P#

AT30

CL K _EXP

E16

C LK_ EXP#

D16
A18

A17

F6
AL1

AM1
AN1

AN15
AP15

AT28
AP27

AN28
AP28
AT27

AT29

TDI

AR27
AR29
AP29

AN25

AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23

eDP

SM _R C OMP0
SM _R C OMP1
SM _R C OMP2

PM_ EXTTS#0
PM_ EXTTS#1

XD P_ P RDY#
XD P _PR EQ#

XD P_ TCK
X DP_TMS
XD P_ TRS T#

XD P _TD I_R
XD P _TD O_R
XD P_ TDI _M
XD P_ TDO _M

XD P_ D BR ESET#

X DP_BPM# 0
X DP_BPM# 1
X DP_BPM# 2
X DP_BPM# 3
X DP_BPM# 4
X DP_BPM# 5
X DP_BPM# 6
X DP_BPM# 7

R1 4 0_ 040 2_5%

DR AMR ST# <17 ,18 >

T63 P AD

1 2

PM_ EXTTS#0
PM_ EXTTS#1

CL K _C PU _BC LK <14 >
CL K _C PU _BC LK# <1 4>

CL K_E XP <12 >
CL K_E XP# <12 >

R2 7 10 K_0 402 _5%
R2 9 10 K_0 402 _5%

1 2
1 2

OK

PM_EXT TS#1 _R <17 ,18>

from DDR

+V CCP

H_ C PU PW RGD

PM _P W RB TN# _R<13>

H_ P WR GD _ XDP

+V CCP

1

C 1

@

0. 1U_04 02_16 V4Z

2

R1 3
1K_ 04 02_ 5%

1 2

R1 6 0_ 040 2_5%

1 2

XD P _PR EQ#
XD P_ P RDY#

X DP_BPM# 0
X DP_BPM# 1

X DP_BPM# 2
X DP_BPM# 3

X DP_BPM# 4
X DP_BPM# 5

X DP_BPM# 6
X DP_BPM# 7

H_ C PU PW RGD _R
PM _P W RB TN#_R

2

XDP Connector

JP 1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_B SH- 030 -01-L -D-A C O NN@

XD P _RS T#_ R

R2 2 0_040 2_5%@

1 2

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

GND17

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

TD0

54
56

TDI

58

TMS

60

CL K _C PU _XD P
CL K _C PU _XD P#

XD P _RS T#_ R
XD P_ D BR ESET#_R

XD P_ TDO
XD P_ TRS T#
XD P_ TDI
X DP_TMSXD P_ TCK

XD P_ D BR ESET#

PL T_RST# <1 4,3 1,3 2>

1

XD P_ TDI

R2 5 1_ 040 2_1%@

1 2

R4 5 1_ 040 2_1%@

X DP_TMS
XD P _PR EQ#
XD P_ TDO

This shall place near CPU

XD P_ TCK

1 2

R6 5 1_ 040 2_1%@

1 2

R8 5 1_ 040 2_1%

1 2

R9 5 1_ 040 2_1%@

1 2

+V CCP

R1 7
1K_ 04 02_ 5%

1 2

1 2

R1 8

0_ 040 2_5%

R6 03 1K_04 02_5%

1 2

H_ C PU R ST#

XD P_ D BRESET# <13>

+V CCP

+3 VS

JTAG MAPPING

+1 .5V

Fan Voltage Control circuit

SI-1 Change to voltage control circuit

+5 VS

+3 VS

1 2

1

2

U3 2

9

Thermal Pad

8

GND

7

GND

6

GND

5

GND

G9 9 6R D1U_TD FN8 _3X 3

FA N_ S ET<37 >

VEN

VSET

1
2

VIN

3

VO

4

R6 78

10 K_0 402 _5 %

FA N_ S PE ED< 37>

FA N_ S PE ED

C7 75

10 00P _04 02 _50 V7K

1

C 2

2. 2U_06 03_6. 3V4 Z

2

1

C7 74

2. 2U_06 03_6. 3V4 Z

2

+5 VS_ FAN

+5 VS

D1

3

Vcc

2

Line to be protected

1

GND

DLPT05 -7-F_SOT2 3-3

FA N_ S PE ED

1

C 3

0. 1U_04 02_16 V4Z

2

1
2
3

C O NN @

JF AN 1

1

4

2

G1

5

3

G2

ACE S_8 520 4- 030 01

XD P_ TDI _M

XD P _TD O_R

XD P_ TRS T#

R3 0 0_ 040 2_5%

1 2

R3 2 0_ 040 2_5%@

1 2

R3 4
0_ 040 2_5%

1 2

R3 7 0_ 040 2_5%@

1 2

R3 8 0_ 040 2_5%

1 2

R3 9 51 _04 02_1%

1 2

XD P_ TDI

XD P_ TDOXD P_ TDO _M

VD DPW RG O OD _R

R3 1 4.75K_04 02_1%
R3 3 12 K_0 402 _1%

CRB 0.9 R38 change to 1K

1 2
1 2

XD P _TD I_R

Processor Pullups

H_ C AT ER R#
H_ C PU RS T# _R

B B

H_ P RO C HOT #

R3 5 49.9_ 0402_ 1%

1 2

R3 6 68_04 02_5%@

1 2

R1 1 68_04 02_5%

+V CCP

12

DDR3 Compensation Signals

SM _R C OMP0

R4 0 100_0 402_1%

SM _R C OMP1
SM _R C OMP2

Layout Note:Please these
resistors near Processor

A A

1 2

R4 1 24.9_ 0402_ 1%

1 2

R4 2 130_0 402_1%

1 2

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Tit le

Size Do c um en t N umb er R e v

Cu s to m

Da te : She et o f

Compal Electronics, Inc.

Auburndale(1/5)-Thermal/XDP

Ca lp ella DIS L A4743P

1

6 49Mon day, Apr il 13, 20 09

0. 1

5

JC PU1A

DMI_CRX_PTX_N0<13>
DMI_CRX_PTX_N1<13>
DMI_CRX_PTX_N2<13>
DMI_CRX_PTX_N3<13>

DMI_CRX_PTX_P0<13>
DMI_CRX_PTX_P1<13>

D D

DMI_CRX_PTX_P2<13>
DMI_CRX_PTX_P3<13>

DMI_CTX_PRX_N0<13>
DMI_CTX_PRX_N1<13>
DMI_CTX_PRX_N2<13>
DMI_CTX_PRX_N3<13>

DMI_CTX_PRX_P0<13>
DMI_CTX_PRX_P1<13>
DMI_CTX_PRX_P2<13>
DMI_CTX_PRX_P3<13>

FDI_ CTX_PRX_N0<13>
FDI_ CTX_PRX_N1<13>
FDI_ CTX_PRX_N2<13>
FDI_ CTX_PRX_N3<13>
FDI_ CTX_PRX_N4<13>
FDI_ CTX_PRX_N5<13>
FDI_ CTX_PRX_N6<13>
FDI_ CTX_PRX_N7<13>

FDI_ CTX_PRX_P0<13>
FDI_ CTX_PRX_P1<13>
FDI_ CTX_PRX_P2<13>
FDI_ CTX_PRX_P3<13>
FDI_ CTX_PRX_P4<13>
FDI_ CTX_PRX_P5<13>

C C

FDI_ CTX_PRX_P6<13>
FDI_ CTX_PRX_P7<13>

FD I_ FS YNC0<13>
FD I_ FS YNC1<13>

FD I_INT<13>
FD I_ LS YNC0<13>

FD I_ LS YNC1<13>

B B

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,A UB_CFD_rPGA,R1P0

C ONN@

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS
PEG_RX#[0]

PEG_RX#[1]

PCI EXPRESS -- GRAPHICS

PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

DMI Intel(R) FDI

4

EXP_ICOMPI

B26
A26
B27

EXP_RBIAS

A25

PCIE _CRX _GT X_N0

K35

PCIE _CRX _GT X_N1

J34

PCIE _CRX _GT X_N2

J33

PCIE _CRX _GT X_N3

G35

PCIE _CRX _GT X_N4

G32

PCIE _CRX _GT X_N5

F34

PCIE _CRX _GT X_N6

F31

PCIE _CRX _GT X_N7

D35

PCIE _CRX _GT X_N8

E33

PCIE _CRX _GT X_N9

C33

PCIE _CRX _GT X_N10

D32

PCIE _CRX _GT X_N11

B32

PCIE _CRX _GT X_N12

C31

PCIE _CRX _GT X_N13

B28

PCIE _CRX _GT X_N14

B30

PCIE _CRX _GT X_N15

A31

PCIE _CRX _GTX_P0

J35

PCIE _CRX _GTX_P1

H34

PCIE _CRX _GTX_P2

H33

PCIE _CRX _GTX_P3

F35

PCIE _CRX _GTX_P4

G33

PCIE _CRX _GTX_P5

E34

PCIE _CRX _GTX_P6

F32

PCIE _CRX _GTX_P7

D34

PCIE _CRX _GTX_P8

F33

PCIE _CRX _GTX_P9

B33

PCIE _CRX _GTX_P10

D31

PCIE _CRX _GTX_P11

A32

PCIE _CRX _GTX_P12

C30

PCIE _CRX _GTX_P13

A28

PCIE _CRX _GTX_P14

B29

PCIE _CRX _GTX_P15

A30

PCIE _CTX_GRX_C_N0

L33

PCIE _CTX_GRX_C_N1

M35

PCIE _CTX_GRX_C_N2

M33

PCIE _CTX_GRX_C_N3

M30

PCIE _CTX_GRX_C_N4

L31

PCIE _CTX_GRX_C_N5

K32

PCIE _CTX_GRX_C_N6

M29

PCIE _CTX_GRX_C_N7

J31

PCIE _CTX_GRX_C_N8

K29

PCIE _CTX_GRX_C_N9

H30

PCIE _CTX_GRX_C_N10

H29

PCIE _CTX_GRX_C_N11

F29

PCIE _CTX_GRX_C_N12

E28

PCIE _CTX_GRX_C_N13

D29

PCIE _CTX_GRX_C_N14

D27

PCIE _CTX_GRX_C_N15

C26

PCIE _CTX_GRX_C_P0

L34

PCIE _CTX_GRX_C_P1

M34

PCIE _CTX_GRX_C_P2

M32

PCIE _CTX_GRX_C_P3

L30

PCIE _CTX_GRX_C_P4

M31

PCIE _CTX_GRX_C_P5

K31

PCIE _CTX_GRX_C_P6

M28

PCIE _CTX_GRX_C_P7

H31

PCIE _CTX_GRX_C_P8

K28

PCIE _CTX_GRX_C_P9

G30

PCIE _CTX_GRX_C_P10

G29

PCIE _CTX_GRX_C_P11

F28

PCIE _CTX_GRX_C_P12

E27

PCIE _CTX_GRX_C_P13

D28

PCIE _CTX_GRX_C_P14

C27

PCIE _CTX_GRX_C_P15

C25

R44 49.9_0402_1%

1 2

R45 750 _04 02_1%

1 2

PCIE _CRX _GT X_N[0..15] <24>

PCIE _CRX _GT X_P [0..15] <24>

C4 0.1U_040 2_16V4ZSG@

1 2

C5 0.1U_040 2_16V4ZSG@

1 2

C6 0.1U_040 2_16V4ZSG@

1 2

C7 0.1U_040 2_16V4ZSG@

1 2

C8 0.1U_040 2_16V4ZSG@

1 2

C9 0.1U_040 2_16V4ZSG@

1 2

C10 0.1U_04 02_16V4ZSG@

1 2

C11 0.1U_04 02_16V4ZSG@

1 2

C12 0.1U_04 02_16V4ZSG@

1 2

C13 0.1U_04 02_16V4ZSG@

1 2

C14 0.1U_04 02_16V4ZSG@

1 2

C15 0.1U_04 02_16V4ZSG@

1 2

C16 0.1U_04 02_16V4ZSG@

1 2

C17 0.1U_04 02_16V4ZSG@

1 2

C18 0.1U_04 02_16V4ZSG@

1 2

C19 0.1U_04 02_16V4ZSG@

1 2

C20 0.1U_04 02_16V4ZSG@

1 2

C21 0.1U_04 02_16V4ZSG@

1 2

C22 0.1U_04 02_16V4ZSG@

1 2

C23 0.1U_04 02_16V4ZSG@

1 2

C24 0.1U_04 02_16V4ZSG@

1 2

C25 0.1U_04 02_16V4ZSG@

1 2

C26 0.1U_04 02_16V4ZSG@

1 2

C27 0.1U_04 02_16V4ZSG@

1 2

C28 0.1U_04 02_16V4ZSG@

1 2

C29 0.1U_04 02_16V4ZSG@

1 2

C30 0.1U_04 02_16V4ZSG@

1 2

C31 0.1U_04 02_16V4ZSG@

1 2

C32 0.1U_04 02_16V4ZSG@

1 2

C33 0.1U_04 02_16V4ZSG@

1 2

C34 0.1U_04 02_16V4ZSG@

1 2

C35 0.1U_04 02_16V4ZSG@

1 2

3

Layout rule trace
length < 0.5"

PCIE _CTX_GRX_N0
PCIE _CTX_GRX_N1
PCIE _CTX_GRX_N2
PCIE _CTX_GRX_N3
PCIE _CTX_GRX_N4
PCIE _CTX_GRX_N5
PCIE _CTX_GRX_N6
PCIE _CTX_GRX_N7
PCIE _CTX_GRX_N8

PCIE _CTX_GRX_N9
PCIE _CTX_GRX_N10
PCIE _CTX_GRX_N11
PCIE _CTX_GRX_N12
PCIE _CTX_GRX_N13
PCIE _CTX_GRX_N14
PCIE _CTX_GRX_N15

PCIE _CTX_GRX_P0

PCIE _CTX_GRX_P1

PCIE _CTX_GRX_P2

PCIE _CTX_GRX_P3

PCIE _CTX_GRX_P4

PCIE _CTX_GRX_P5

PCIE _CTX_GRX_P6

PCIE _CTX_GRX_P7

PCIE _CTX_GRX_P8

PCIE _CTX_GRX_P9
PCIE _CTX_GRX_P10
PCIE _CTX_GRX_P11
PCIE _CTX_GRX_P12
PCIE _CTX_GRX_P13
PCIE _CTX_GRX_P14
PCIE _CTX_GRX_P15

：

+V _DDR_CPU_REF1

PCIE _CTX_GRX_N[0..15] <24>

PCIE _CTX_GRX_P [0..15] <24>

R50 0_0 402_5%@
R51 0_0 402_5%@

1 2
1 2

2

+V _DDR_CPU_REF0

CF G0
CF G1
CF G2
CF G3
CF G4
CF G5
CF G6
CF G7
CF G8
CF G9
CF G10
CF G11
CF G12
CF G13
CF G14
CF G15
CF G16
CF G17
CF G18

AP25
AL25
AL24
AL22
AJ33

AG9
M27

G25
G17

AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30

AC9

L28
J17
H17

E31
E30

H16

B19
A19

A20
B20

U9

T9

AB9

C1
A3

J29
J28

A34
A33

C35
B35

JC PU1E

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
SA_DIMM_VREF
SB_DIMM_VREF
RSVD11
RSVD12
RSVD13
RSVD14

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86

RSVD15
RSVD16

RSVD17
RSVD18

RSVD19
RSVD20

RSVD21
RSVD22

RSVD_NCTF_23
RSVD_NCTF_24

RSVD26
RSVD27

RSVD_NCTF_28
RSVD_NCTF_29

RSVD_NCTF_30
RSVD_NCTF_31

RESERVED

RSVD32
RSVD33

RSVD34
RSVD35

RSVD36

RSVD_NCTF_37

RSVD38
RSVD39

RSVD_NCTF_40
RSVD_NCTF_41

RSVD_NCTF_42
RSVD_NCTF_43

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52

RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57

RSVD58

RSVD_TP_59
RSVD_TP_60

KEY
RSVD62
RSVD63
RSVD64
RSVD65

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

VSS

AJ13
AJ12

AH25
AK26

AL26
AR2

AJ26
AJ27

AP1
AT2

AT3
AR1

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32

E15
F15
A2
D15
C15
AJ15
AH15

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

AP34

1

R48 0_0 402_5%@

1 2

R49 0_0 402_5%@

1 2

IC,A UB_CFD_rPGA,R1P0

C ONN@

CFG Straps for PROCESSOR

CF G0

R52 3.01K_0402_1%@

1 2

PCI-Express Configuration Select

1: Single PEG

CFG0

A A

No t ap pl ic able for Clarksfield Processor

CF G3

0: B if urcation enabled

R54 3.01K_0402_1%

1 2

CF G3 -P CI Express Static Lane Reversal

1: N ormal Operation

CFG3

0: L an e Numbers Reversed

15 - > 0, 14 ->1, .....

5

*

CF G4

R53 3.01K_0402_1%@

1 2

CF G4 -D isplay Port Presence

1: D is abled; No Physical
D isplay Port

at ta ch ed to Embedded Display Port
0: E na bled; An external

CFG4

D isplay Port
de vi ce is connected to the

Em be dded Display Port

CF G7

R55 3.01K_0402_1%@

Only temporary for early
CFD samples (rPGA/BGA)

Only for pre ES1 sample

1 2

4

**

CFG7

WW33 GPD 3.01K on CFG7 for PCIE Jitter
WW41 don't staff

：

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

Cu st om

2

Da te: Sheet o f

Compal Electronics, Inc.

Auburndale(2/5)-DMI/PEG/FDI

Ca lpella DI S LA4743P

CRB 0.9 change to GND

7 49Monday, April 13, 2009

1

0.1

5

4

3

2

1

AR10
AT10

AF3
AG1
AJ3
AK1
AG4
AG3
AJ4
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9

AB1

AC5
AC6

W5

B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
J6
J3
G1
G5
J2
J1
J5
K2
L3
M1
K5
K4
M4
N5

R7

Y7

JC PU 1D

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

W8

SB_CK[0]

W9

SB_CK#[0]

M3

SB_CKE[0]

V7

SB_CK[1]

V6

SB_CK#[1]

M2

SB_CKE[1]

AB8

SB_CS#[0]

AD6

SB_CS#[1]

AC7

SB_ODT[0]

AD1

SB_ODT[1]

DDR_B_DM0

D4

SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

E1
H3
K1
AH1
AL2
AR4
AT8

D5
F4
J4
L4
AH2
AL4
AR5
AR8

C5
E3
H4
M5
AG2
AL5
AP5
AR7

DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR SYSTEM MEMORY - B

DDR_B_ MA0

U5

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

DDR_B_ MA1
DDR_B_ MA2
DDR_B_ MA3
DDR_B_ MA4
DDR_B_ MA5
DDR_B_ MA6
DDR_B_ MA7
DDR_B_ MA8
DDR_B_ MA9
DDR_B_MA 10
DDR_B_MA 11
DDR_B_MA 12
DDR_B_MA 13
DDR_B_MA 14
DDR_B_MA 15

M_ CLK_DDR2 <18>
M_ CLK _DDR# 2 <18>
DDR_CKE2_DIMMB <18>

M_ CLK_DDR3 <18>
M_ CLK _DDR# 3 <18>
DDR_CKE3_DIMMB <18>

DDR_CS2_DIMMB# <18>
DDR_CS3_DIMMB# <18>

M_ODT2 <18>
M_ODT3 <18>

DDR_B_DM[0..7] <18>

DDR_B_DQS#[0..7 ] <18>

DDR_B_ DQS[0..7] <18>

DDR_B _MA[0..1 5] <18>

JC PU 1C

D D

DDR_A_D[0..63]<17>

C C

B B

DDR_A_BS0<17>
DDR_A_BS1<17>
DDR_A_BS2<17>

DDR_A_ CAS #<17>
DDR_A_ RAS #<17>
DDR_A _WE #<17>

DDR_ A_D0
DDR_ A_D1
DDR_ A_D2
DDR_ A_D3
DDR_ A_D4
DDR_ A_D5
DDR_ A_D6
DDR_ A_D7
DDR_ A_D8
DDR_ A_D9
DDR_A_D1 0
DDR_A_D1 1
DDR_A_D1 2
DDR_A_D1 3
DDR_A_D1 4
DDR_A_D1 5
DDR_A_D1 6
DDR_A_D1 7
DDR_A_D1 8
DDR_A_D1 9
DDR_A_D2 0
DDR_A_D2 1
DDR_A_D2 2
DDR_A_D2 3
DDR_A_D2 4
DDR_A_D2 5
DDR_A_D2 6
DDR_A_D2 7
DDR_A_D2 8
DDR_A_D2 9
DDR_A_D3 0
DDR_A_D3 1
DDR_A_D3 2
DDR_A_D3 3
DDR_A_D3 4
DDR_A_D3 5
DDR_A_D3 6
DDR_A_D3 7
DDR_A_D3 8
DDR_A_D3 9
DDR_A_D4 0
DDR_A_D4 1
DDR_A_D4 2
DDR_A_D4 3
DDR_A_D4 4
DDR_A_D4 5
DDR_A_D4 6
DDR_A_D4 7
DDR_A_D4 8
DDR_A_D4 9
DDR_A_D5 0
DDR_A_D5 1
DDR_A_D5 2
DDR_A_D5 3
DDR_A_D5 4
DDR_A_D5 5
DDR_A_D5 6
DDR_A_D5 7
DDR_A_D5 8
DDR_A_D5 9
DDR_A_D6 0
DDR_A_D6 1
DDR_A_D6 2
DDR_A_D6 3

AJ10
AL10

AK12

AK11

AM10

AR11
AL11

AT11
AP12

AM12

AN12

AM13

AT14
AT12
AL13
AR14
AP14

C10

D10

G10

AH5
AF5
AK6
AK7
AF6
AG5

AK8

AN8

AM9
AN9

AC3
AB2

AE1
AB3
AE9

A10

SA_DQ[0]
SA_DQ[1]

C7

SA_DQ[2]

A7

SA_DQ[3]

B10

SA_DQ[4]
SA_DQ[5]

E10

SA_DQ[6]

A8

SA_DQ[7]

D8

SA_DQ[8]

F10

SA_DQ[9]

E6

SA_DQ[10]

F7

SA_DQ[11]

E9

SA_DQ[12]

B7

SA_DQ[13]

E7

SA_DQ[14]

C6

SA_DQ[15]

H10

SA_DQ[16]

G8

SA_DQ[17]

K7

SA_DQ[18]

J8

SA_DQ[19]

G7

SA_DQ[20]
SA_DQ[21]

J7

SA_DQ[22]

J10

SA_DQ[23]

L7

SA_DQ[24]

M6

SA_DQ[25]

M8

SA_DQ[26]

L9

SA_DQ[27]

L6

SA_DQ[28]

K8

SA_DQ[29]

N8

SA_DQ[30]

P9

SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]

AJ7

SA_DQ[38]

AJ6

SA_DQ[39]
SA_DQ[40]

AJ9

SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]

AL7

SA_DQ[45]
SA_DQ[46]

AL8

SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]

U7

SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0]

SA_CK#[0]

SA_CKE[0]

SA_CK[1]

SA_CK#[1]

SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AA6
AA7
P7

Y6
Y5
P6

AE2
AE8

AD8
AF9

B9
D7
H7
M7
AG6
AM7
AN10
AN13

C9
F8
J9
N9
AH7
AK9
AP11
AT13

C8
F9
H9
M9
AH8
AK10
AN11
AR13

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_ MA0
DDR_A_ MA1
DDR_A_ MA2
DDR_A_ MA3
DDR_A_ MA4
DDR_A_ MA5
DDR_A_ MA6
DDR_A_ MA7
DDR_A_ MA8
DDR_A_ MA9
DDR_A_MA 10
DDR_A_MA 11
DDR_A_MA 12
DDR_A_MA 13
DDR_A_MA 14
DDR_A_MA 15

M_ CLK _DDR0 <17>
M_CLK_ DDR#0 <17>
DDR_CKE0_DIMMA <17>

M_ CLK _DDR1 <17>
M_CLK_ DDR#1 <17>
DDR_CKE1_DIMMA <17>

DDR_CS0_DIMMA# <17>
DDR_CS1_DIMMA# <17>

M_ODT0 <17>
M_ODT1 <17>

DDR_A_DM[0..7] <17>

DDR_A_DQS#[0..7] <17>

DDR_A_DQS[0 ..7] <17>

DDR_A_ MA[0..15] <17>

DDR_B_D[0..63]<18>

DDR_B_BS0<18>
DDR_B_BS1<18>
DDR_B_BS2<18>

DDR_B_ CAS #<18>
DDR_B_ RAS #<18>
DDR_B _WE #<18>

DDR_ B_D0
DDR_ B_D1
DDR_ B_D2
DDR_ B_D3
DDR_ B_D4
DDR_ B_D5
DDR_ B_D6
DDR_ B_D7
DDR_ B_D8
DDR_ B_D9
DDR_B_D1 0
DDR_B_D1 1
DDR_B_D1 2
DDR_B_D1 3
DDR_B_D1 4
DDR_B_D1 5
DDR_B_D1 6
DDR_B_D1 7
DDR_B_D1 8
DDR_B_D1 9
DDR_B_D2 0
DDR_B_D2 1
DDR_B_D2 2
DDR_B_D2 3
DDR_B_D2 4
DDR_B_D2 5
DDR_B_D2 6
DDR_B_D2 7
DDR_B_D2 8
DDR_B_D2 9
DDR_B_D3 0
DDR_B_D3 1
DDR_B_D3 2
DDR_B_D3 3
DDR_B_D3 4
DDR_B_D3 5
DDR_B_D3 6
DDR_B_D3 7
DDR_B_D3 8
DDR_B_D3 9
DDR_B_D4 0
DDR_B_D4 1
DDR_B_D4 2
DDR_B_D4 3
DDR_B_D4 4
DDR_B_D4 5
DDR_B_D4 6
DDR_B_D4 7
DDR_B_D4 8
DDR_B_D4 9
DDR_B_D5 0
DDR_B_D5 1
DDR_B_D5 2
DDR_B_D5 3
DDR_B_D5 4
DDR_B_D5 5
DDR_B_D5 6
DDR_B_D5 7
DDR_B_D5 8
DDR_B_D5 9
DDR_B_D6 0
DDR_B_D6 1
DDR_B_D6 2
DDR_B_D6 3

IC,A UB_CFD_rPGA,R1P0

C ONN@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

IC,A UB_CFD_rPGA,R1P0

C ONN@

Deciphered Date

Title

Size Do cument Number Re v

Cu st om

2

Da te: Sheet o f

Compal Electronics, Inc.

Cantiga(2/6)-DDR3 A/B CH

Ca lpella DI S LA4743P

1

8 49Monday, April 13, 2009

0.1

5

+V CC _CORE

JC PU1F

D D

C C

B B

A A

48A 15A18A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

IC,A UB_CFD_rPGA,R1P0

C ONN@

CPU CORE SUPPLY

5

POWER

CPU VIDS

SENSE LINES

1.1V RAIL POWER

PROC_DPRSLPVR

VSS_SENSE_VTT

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8

VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32

VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

PSI#

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VTT_SELECT

ISENSE

VCC_SENSE

VSS_SENSE

VTT_SENSE

AH14
AH12
AH11
AH10

1
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

AN33

AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

G15

C40

2

10U_0805_6 .3V6M

1

C48

2

10U_0805_6 .3V6M

1

C67

2

+VTT_43
+VTT_44

H_ VID0
H_ VID1
H_ VID2
H_ VID3
H_ VID4
H_ VID5
H_ VID6
PM_ DPRS LPV R_R

H_VTTVID1 = Low, 1.1V(Clarksfield)
H_VTTVID1 = High, 1.05V(Auburndale)

AN35

VC CSENSE_R

AJ34

VSSSE NSE_R

AJ35

B15

VSS_SENSE_VTT

A15

Near Processor

V CCSE NSE
VSSSE NSE

R61 100 _0402_1%
R62 100 _0402_1%

4

1

C41

2

10U_0805_6 .3V6M

1

C49

2

@

10U_0805_6 .3V6M

1

2

22U_0805_6.3V6M

+VTT_44
+VTT_43

to power

R58 0_0 402_5%

to power

R5 9 0_0 402_5%

1 2

R6 0 0_0 402_5%

1 2

R203 0_0 402_5%

1 2
1 2

1

1

C42

2

2

10U_0805_6 .3V6M

1

1

C50

2

2

@

10U_0805_6 .3V6M

+V CCP

C68

22U_0805_6.3V6M

R56 0_0 603_5%

1 2

R57 0_0 603_5%

1 2

H_PSI# <46>
H_ VI D[0..6] <46>

to power

1 2

VTT_SELECT <44>

IMVP_IMON <46>

1 2

+V CC_ CORE

4

C43

C51

10U_0805_6 .3V6M

10U_0805_6 .3V6M

+V CCP

1

2

1

2

C52

10U_0805_6 .3V6M

C61

22U_0805_6 .3V6M

V CCSE NSE
VSSSE NSE

+V CCP

1

C62

2

22U_0805_6 .3V6M

+VCCP

H_ DPRS LPVR <46>

to power

VTT_SENSE <44>

3

+VGA_CORE

22U_0805_6.3V6M

22U_0805_6.3V6M

C988

C987

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C993

C991

1

1

@

@

2

330 U_D2_2V Y_R7M

C995

1

1

+

+

1

2

2

2

C63

22U_0805_6 .3V6M

+V CCP

1

2

@

2

330 U_D2_2V Y_R7M

C996

+V CCP

1

C74

C73

2

22U_0805_6 .3V6M

22U_0805_6 .3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

C989

1

1

2

2

22U_0805_6.3V6M

C994

1

2

1

1

C6 9

2

2

22U_0805_6.3V6M

1

1

C75

2

2

22U_0805_6 .3V6M

CPU

VCCSENSE <46>
VSSSENSE <46>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

AT21
AT19
AT18

C990

AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18

AN16
AM21
AM19
AM18
AM16

AL21

AL19

AL18

AL16
AK21
AK19
AK18
AK16

AJ21

AJ19

AJ18

AJ16
AH21
AH19
AH18
AH16

J24
J23
H25

C7 0

22U_0805_6.3V6M

K26
J27
J26
J25

C76

H27
G28
G27
G26

22U_0805_6 .3V6M

F26

E26

E25

Compal Secret Data

JC PU1G

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36

VTT1_45
VTT1_46
VTT1_47

VTT1_48
VTT1_49
VTT1_50
VTT1_51
VTT1_52
VTT1_53
VTT1_54
VTT1_55
VTT1_56
VTT1_57
VTT1_58

IC,A UB_CFD_rPGA,R1P0

C ONN@

GRAPHICS

FDI PEG & DMI

Deciphered Date

POWER

2

VCC_ AXG_SENSE

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

GFX_VR_EN

GFX_IMON

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

VTT0_59
VTT0_60
VTT0_61
VTT0_62

VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68

VCCPLL1
VCCPLL2
VCCPLL3

AR22

VSS_AXG_SENSE

AT22

GFX VR_VID_0

AM22

GFX VR_VID_1

AP22

GFX VR_VID_2

AN22

GFX VR_VID_3

AP23

GFX VR_VID_4

AM23

GFX VR_VID_5

AP24

GFX VR_VID_6

AN24

GFX VR_EN

AR25

GFX VR_DPRSLPV R

AT25

GFX VR_IMON

AM24

R128

@

AJ1
AF1
AE7

1
AE4
AC1
AB7

2
AB4

Y1
W7
W4
U1
T7
T4

1
P1

+

N7
N4
L1

2
H1

P10
N10
L10
K10

1

2
J22

J20
J18
H21
H20
H19

1

2

L26
L27
M26

1

C79

2

1U_0603_10V4Z

Title

Size Do cument Number Re v

Cu st om

Ca lpella DI S LA4743P

Da te: Sheet o f

12

1K_0402_5%

1

1

C57

C56

2

2

1U_0603_10V4Z

1U_0603_10V4Z

1

1

C65

C64

2

2

22U_0805_6 .3V6M

330 U_D2_2V Y_R7M

+V CCP

1

C72

C71

2

10U_0805_6 .3V6M

10U_0805_6 .3V6M

+V CCP

1

C78

C77

2

22U_0805_6 .3V6M

22U_0805_6 .3V6M

1

1

C81

C80

2

2

1U_0603_10V4Z

2.2U_0603_6.3V4Z

Compal Electronics, Inc.

Auburndale(4/5)-PWR

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

GFX_DPRSLPVR

GRAPHICS VIDs

3A

DDR3 - 1.5V RAILS

1.1V1.8V

0.6A

2

1

VCC_ AXG_SENSE <43>
VSS_AXG_SENSE <43>

GFX VR_VID_0 <43>
GFX VR_VID_1 <43>
GFX VR_VID_2 <43>
GFX VR_VID_3 <43>
GFX VR_VID_4 <43>
GFX VR_VID_5 <43>
GFX VR_VID_6 <43>

GFX VR_EN <43>
GFX VR_DPRSLPVR <43>
GFX VR_IMON <43>

1

1

C59

C58

1U_0603_10V4Z

C66

22U_0805_6 .3V6M

1

2

C60

2

2

1U_0603_10V4Z

1

C82

C83

2

22U_0805_6.3V6M

4.7U_0603_6.3V6K

1

+1.5V

1U_0603_10V4Z

+1.8 VS

0.1

9 49Monday, April 13, 2009

5

4

3

2

1

JC PU 1H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

D D

C C

B B

AR17
AR15
AR12

AP20
AP17
AP13
AP10

AN34
AN31
AN23
AN20

AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11

AL34

AL31

AL23

AL20

AL17

AL12

AK29

AK27

AK25

AK20

AK17

AJ31

AJ23

AJ20

AJ17

AJ14

AJ11

AH35

AH34

AH33

AH32

AH31

AH30

AH29

AH28

AH27

AH26

AH20

AH17

AH13

AG10

AE35

AR9
AR6
AR3

AP7
AP4
AP2

AM8
AM5
AM2

AL9
AL6
AL3

AJ8
AJ5
AJ2

AH9
AH6
AH3

AF8
AF4
AF2

VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

JC PU1I

K27

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

VSS

NCTF

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

AT35
AT1
AR34
B34
B2
B1
A35

+V CC _CORE

@

VSS_NCTF1_R
VSS_NCTF2_R

VSS_NCTF3_R
VSS_NCTF4_R
VSS_NCTF5_R

VSS_NCTF6_R
VSS_NCTF7_R

1

1

C84

2

1

2

1

1

C982

2

2

47P _04 02_50V8J

C85

2

10U_0805_6 .3V6M

10U_0805_6 .3V6M

1

C97

C96

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C114

C115

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C86

2

10U_0805_6 .3V6M

1

C98

2

10U_0805_6.3V6M

1

C116

2

10U_0805_6.3V6M

CPU CORE

1

1

C87

2

1

2

1

2

C88

2

10U_0805_6 .3V6M

10U_0805_6 .3V6M

1

C100

C99

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C117

C118

2

10U_0805_6.3V6M

22U_0805_6.3V6M

1

1

1

C89

2

1

2

1

2

C90

2

10U_0805_6 .3V6M

10U_0805_6 .3V6M

1

C101

C102

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C119

C120

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C91

2

1

2

1

2

C92

2

10U_0805_6 .3V6M

10U_0805_6 .3V6M

1

C104

C103

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

+

C121

C108

2

22U_0805_6.3V6M

470 U_D2_2V M_R4.5M

1

1

C93

2

10U_0805_6 .3V6M

1

C105

2

10U_0805_6.3V6M

1

+

C109

2

470 U_D2_2V M_R4.5M

1

C94

2

10U_0805_6 .3V6M

1

C106

2

10U_0805_6.3V6M

1

+

C110

2

470 U_D2_2V M_R4.5M

Inside cavity

C95

2

10U_0805_6 .3V6M

1

between

C107

Inductor and

2

10U_0805_6.3V6M

socket

1

+

C111

2

470 U_D2_2V M_R4.5M

470uF 4.5mohm

IC,A UB_CFD_rPGA,R1P0

C ONN@

A A

5

4

IC,A UB_CFD_rPGA,R1P0

C ONN@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Title

Size Do cument Number Re v

Cu st om

Da te: Sheet o f

Compal Electronics, Inc.

Auburndale(5/5)-GND/Bypass

Ca lpella DI S LA4743P

10 49Monday, April 13, 2009

1

0.1

5

IC H _RTCX 1

R6 3 10M_0402 _5%

1 2

1

1

D D

2

C C

+3 VS

R6 56 10 K_0 402 _5 %

R6 57 10 K_0 402 _5 %

B B

C1 22

18 P_0 402 _5 0V8J

1 2

1 2

OSC4OSC

NC3NC

2

IC H _RTCX 2

1

C1 23

2

Y1

18 P_0 402 _5 0V8J

32 .7 68 KHZ_ 12 .5P F_Q 13MC14 61000 2

SP I_ S B_C S#

SP I _SO _R

+R TC VCC

R6 5 1M_ 0402_ 5%

R6 6 33 0K_ 040 2_ 5%

+R TC VCC

R6 9 20 K_0 402 _1 %

1 2

R7 0 20 K_0 402 _1 %

1 2

HD A_B IT CL K_M DC<33 >
HD A_B IT CL K_ COD EC<33 >
HD A_S YN C_ M DC<33 >
HD A_S YN C_ C OD EC<33 >

HD A_R ST #_ MDC<3 3>
HD A_R ST #_ CO DEC<33 ,3 7>

HD A_S DI N0<33 >
HD A_S DI N1<33 >

HD A_S DO U T_M DC<33 >
HD A_S DO U T_ COD EC<33 >

SP I_ C LK _PC H<3 6>
SP I_ SB _CS #<36>

SP I_ SI<36>

SP I_ SO _R<36 >

1 2

1 2

1

C1 24

1U _0603 _10V4 Z

1U _0603 _10V4 Z

2

1

C1 25

2

R7 2 33 _04 02_5%

1 2

R7 3 33 _04 02_5%

1 2

R7 4 33 _04 02_5%

1 2

R7 5 33 _04 02_5%

1 2

1 2

R7 7 33 _04 02_5%

1 2

R7 8 33 _04 02_5%

R8 1 33 _04 02_5%

1 2

R8 2 33 _04 02_5%

1 2

R6 70 10 0K_ 0402_ 5%@

1 2

SP I_ C L K_P CH
SP I_ S B_C S#

SP I_ SI
SP I _SO _R

SM _I N TR UD ER#

PC H_I NT V RMEN

INTVRMEN
H I n：tegrated VRM enable
L I n：tegrated VRM disable

12

CL R P1

SH O RT P ADS

12

CL R P2

SH O RT P ADS

SB _SPKR<33 >

R6 54 1 5_0 402_5%

1 2

R6 55 1 5_0 402_5%

1 2

4

IC H _RTCX 1
IC H _RTCX 2

IC H _R T CRST#
IC H _S RT CR ST#
SM _I N TR UD ER#
PC H_I NT V RMEN

HD A_B IT_CL K
H D A_ SYN C
SB _SP KR
HD A_R ST#

HD A_S D IN0
HD A_S D IN1

HD A_S D OUT

HD A_D OC K _EN#

T16P AD

PC H_J TAG_ TCK
PC H_J TAG_TMS
PC H_J TAG_TDI
PC H_J TAG_TDO
PC H_J TAG_R ST#

*

U1 A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST# / GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IB EX PEAK- M_FC BGA 1071

+3 VS

R6 4 10 K_0 402 _5 %

1 2

R6 7 1K_ 04 02_ 5%@

1 2

LOW=Default
HIGH=No Reboot

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

RTCIHDA

LPC

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA

SATA4TXP
SATA5RXN

SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

SATA0GP / GPIO21
SATA1GP / GPIO19

SPI JTAG

3

SI RQ

SB _SP KR

*

D33
B33
C32
A32

C34

LD R Q0 #

A34

LD R Q1 #

F34

SI RQ

AB9

AK7
AK6

SA TA_TXN 0_C

AK11

S ATA_ TXP0 _C

AK9

AH6
AH5

SA TA_TXN 4_C

AH9

S ATA_ TXP4 _C

AH8
AF11

AF9
AF7
AF6

AH3
AH1
AF3
AF1

AD9
AD8

SA TA_TXN 2_C

AD6

S ATA_ TXP2 _C

AD5
AD3

AD1
AB3
AB1

AF16

R8 9 37 .4_ 0402_ 1%

1 2

AF15

R9 1 10 K_0 402 _1 %

1 2

T3

G PIO 21

Y9

HD D HA L T_L ED#

V1

LP C _AD0 <31,36 ,37>
LP C _AD1 <31,36 ,37>
LP C _AD2 <31,36 ,37>
LP C _AD3 <31,36 ,37>

LP C _F RAME# <31 ,36 ,37>

T13 PA D
T14 PA D

SI RQ <37 >

C1 26 0. 01 U_0 402_5 0V7 K

1 2

C1 27 0. 01 U_0 402_5 0V7 K

1 2

C1 30 0. 01 U_0 402_5 0V7 K

1 2

C1 31 0. 01 U_0 402_5 0V7 K

1 2

C1 28 0. 01 U_0 402_5 0V7 K

1 2

C1 29 0. 01 U_0 402_5 0V7 K

1 2

+1 .05VS

+3 VS

SA TA_LE D# <38 >

HD D HA LT _L ED# <38>

SA T A_RXN0_C
SA T A_RXP0_C
S ATA_ TXN0

SATA_TX P0

SA T A_RXN4_C
SA T A_RXP4_C
S ATA_ TXN4

SATA_TX P4

SA T A_RXN2_C
SA T A_RXP2_C
S ATA_ TXN2

SATA_TX P2

2

SA TA_RXN0_ C <30>
SA TA_ RXP0_C <3 0>

SATA_T XN0 <30 >
SATA_T XP0 <30 >

SA TA_RXN4_ C <30>
SA TA_ RXP4_C <3 0>

SATA_T XN4 <30 >
SATA_T XP4 <30 >

SA TA_RXN2_ C <35>
SA TA_ RXP2_C <3 5>

SATA_T XN2 <35 >
SATA_T XP2 <35 >

12

R8 6

@

20 0_0 402_5%

12

R6 84

@

10 0_0 402_1%

HDD

ODD

E SATA

1

+3 VALW+ 3V AL W +3 VALW +3 VALW

12

R8 4

@

20 0_0 402_5%

PC H_J TAG_TMS PC H_J TAG_R ST#PC H_J TAG_TDO PC H_J TAG_TDI

12

R6 83

@

10 0_0 402_1%

R8 5
20 K_0 402 _5 %

1 2

R6 85
10 K_0 402 _1 %

1 2

@

1 2
12

@

R8 7
20 K_0 402 _5 %

R8 8

10 K_0 402 _5 %

HDA_SDO

HDA_SYNC

This signal has a weak internal pull down.

H=>On Die PLL is supplied by 1.5V
L=>On Die PLL is supplied by 1.8V

*

HDA_DOCK_EN#

ME debug mode , this signal has a weak internal PU

H=>security measures defined in the Flash

*

Descriptor will be in effect (default)

L=>Flash Descriptor Security will be overridden

A A

5

SPI_MOSI

This signal has a weak internal pull down.

Disable iTPM=No Stuff

*

Enable iTPM=Stuff

iTPM ENABLE/DISABLE

+3 VS

R6 8 1K_ 04 02_ 5%@

1 2

SP I_ SI

4

This signal has a weak internal pull down.
This signal can't PU

Disable iTPM=No Stuff

*

Enable iTPM=Stuff

W=20milsW=20mils

1

C1 32

2. 2U_06 03_6. 3V4 Z

2

Place near IBEX-M

+3 VS

G PIO 21

HD D HA L T_L ED#

R9 2 10 K_0 402 _5 %
R9 3 10 K_0 402 _5 %

12
12

Security Classification

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

D 3

1

DA N20 2U _SC70

Issued Date

2

R9 4 1K _0402 _5%

3

1 2

BATT1

@

BATT1. 1+3 VL+R TC VCC

CR2032 RTC BATTERY

JB ATT1

1

W=20mils

2008/03/13 2009/05/11

1

2

2

3

GND

4

GND

ACE S_8 520 5- 020 01

C O NN @

Compal Secret Data

Deciphered Date

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TCK

PCH_JTAG_RST#

2

1 2

R9 0 51_04 02_5%

RefDesP CH Pi n

R86
R684
R84
R683

R685
R90
R87
R88

PC H_J TAG_ TCK

PCH JTAG Enable PCH JTAG Disable
ES1 ES1E S2 ES2

200ohm

No Install

No Install

200ohm

100ohm
200ohm

No Install

100ohm 100ohm
200ohm

200ohm
100ohm 100ohm
51oh m 51ohm 51ohm
20Kohm 20Kohm
10Kohm 10Kohm

Tit le

Size Do c um en t N umb er R e v

Cu s to m

Da te : She et of

Compal Electronics, Inc.

IBEX-M(1/6)-HDA/JTAG/SATA

Ca lp ella DIS L A4743P

No Install
No Install
No Install

20Kohm
10Kohm

No Install

1

No Install
No Install
No Install
No Install
No InstallR85
No Install

51oh m
No Install
No InstallNo Install

11 49Monda y, Apr il 13, 2009

0. 1

5

D D

PC IE_R XN1<31>

WWAN

WLAN

LAN

New Card

C C

OK

OK

OK

B B

OK

A A

+3 VALW

+3 VS

+3 VS

+3 VALW

WWAN

WLAN

LAN

EXP

PC IE_RXP1<31>
PC IE_TXN 1<31>
PC IE_ TXP1<31>

PC IE_R XN2<31>
PC IE_RXP2<31>
PC IE_TXN 2<31>
PC IE_ TXP2<31>

PC IE_R XN3<32>
PC IE_RXP3<32>
PC IE_TXN 3<32>
PC IE_ TXP3<32>

PC IE_R XN4<31>
PC IE_RXP4<31>
PC IE_TXN 4<31>
PC IE_ TXP4<31>

R4 05 10 K_0 402 _5 %

1 2

R4 11 10 K_0 402 _5 %

1 2

R6 77 10 K_0 402 _5 %

1 2

R4 15 10 K_0 402 _5 %

1 2

CL K _P CI E_WWAN#<31>
CL K _P CI E_WWAN<31 >

CL K RE Q_ W WAN#< 31>

CL K _P CI E_ WLA N#< 31>
CL K _P CI E_ WLA N<3 1>

CL K RE Q_ WL AN#<31 >

CL K _P CIE _LAN#<32 >
CL K _P CIE _LAN<32 >

CL K RE Q_LAN#< 32>

CL K _PCIE_EXP#<31 >
CL K _PCIE_ EXP< 31>

CL K REQ_EXP#<31>

C1 33 0 .1U _04 02 _16 V4Z
C1 34 0 .1U _04 02 _16 V4Z

C1 35 0 .1U _04 02 _16 V4Z
C1 36 0 .1U _04 02 _16 V4Z

C1 37 0 .1U _04 02 _16 V4Z
C1 38 0 .1U _04 02 _16 V4Z

C1 39 0 .1U _04 02 _16 V4Z
C1 40 0 .1U _04 02 _16 V4Z

CL K RE Q_ W WAN#_R

CL K RE Q_ W LAN #

CL K RE Q_ LAN #

CL K RE Q_EXP# _R

R1 07 0_ 0402_ 5%
R1 08 0_ 0402_ 5%

R8 0 10 0_0 402_5%

R1 09 0_ 0402_ 5%
R1 10 0_ 0402_ 5%

R1 11 0_ 0402_ 5%
R1 12 0_ 0402_ 5%

R1 14 0_ 0402_ 5%
R1 15 0_ 0402_ 5%

R8 3 10 0_0 402_5%

R7 56 10 K_0 402_5 %

+3 VALW

R7 57 10 K_0 402_5 %

+3 VALW

R6 06 10 K_0 402_5 %

+3 VALW

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

1 2

1 2

1 2

PC IE_ RXN 1
PC I E_R XP1
PC I E_C _TX N1
PC IE_C_TXP 1

PC IE_ RXN 2
PC I E_R XP2
PC I E_C _TX N2
PC IE_C_TXP 2

PC IE_ RXN 3
PC I E_R XP3
GL A N_ C_TXN
GL A N_C _TXP

PC IE_ RXN 4
PC I E_R XP4
PC I E_C _TX N4
PC IE_C_TXP 4

CL K _P CI E_W WA N#_ R
CL K _P CI E_W WA N_R

CL K RE Q_ W WAN#_R

CL K _P CI E _WLAN#_R
CL K _P CI E _WLAN_R

CL K _P C IE_ LAN #_R
CL K _P C IE_ LAN _R

CL K _PCIE _EX P#_ R
CL K _PCIE _EX P_R

CL K RE Q_EXP# _R

PC IEC L KREQ 4#

PC IEC L KREQ 5#

PE G_B _CL KRQ #

4

U1 B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

T57P AD
T58P AD

T59P AD
T60P AD

T61P AD
T62P AD

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IB EX PEAK-M _FCBGA1 07 1

PCI-E*

SMBALERT# / GPIO11

SMBCLK

SMBDATA

SML0ALERT# / GPIO60

SML0CLK

SML0DATA

SML1ALERT# / GPIO74

SMBus

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

Link

Controller

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

Clock Flex

CL_DATA1

CL_RST1#

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_BCLK_N
CLKIN_BCLK_P

CLKIN_DOT_96N
CLKIN_DOT_96P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

3

EC _ LID_ OUT#
SM B CLK
SM BD AT A
SM L0 CLK
SM L 0DA TA
SM L0 ALERT#
SM L1 ALERT#
SM L1 CLK
SM L 1DA TA

EC _ LID_ OUT#

B9

SM B CLK

H14

SM BD AT A

C8

SM L0 ALERT#

J14

SM L0 CLK

C6

SM L 0DA TA

G8

SM L1 ALERT#

M14

SM L1 CLK

E10

SM L 1DA TA

G12

T13
T11
T9

PE G_C LK REQ #

H1

L_ C L K_P CIE_VGA#

AD43

L_ C L K_P CIE_VGA

AD45
AN4

AN2

CL K _D P#

AT1

CL K _DP

AT3

AW24
BA24

AP3
AP1

F18
E18

AH13
AH12

P41

J42

XTAL25 _IN

AH51

XTAL25 _OU T

AH53

R1 16 9 0.9 _0402 _1%

AF38

T45

P43

T42

N50

R9 5 10 K_0 402 _5%

1 2

R9 6 2.2K_040 2_5%

1 2

R9 7 2.2K_040 2_5%

1 2

R9 8 2.2K_040 2_5%

1 2

R9 9 2.2K_040 2_5%

1 2

R1 00 1 0K_ 040 2_ 5%

1 2

R1 01 1 0K_ 040 2_ 5%

1 2

R1 03 2 .2K_04 02_5%

1 2

R1 04 2 .2K_04 02_5%

1 2

EC _ LI D_O UT# <37>

SM BC LK <31>
SM BD ATA <31>

R2 15
R2 31

1 2

0_0402_5%
0_0402_5%

DTS , read from EC

R1 02 1 0K_ 040 2_ 5%

1 2

R6 04 0 _04 02_5%

1 2

R6 05 0 _04 02_5%

1 2

CL K_E XP# <6 >
CL K_E XP <6>

T71 PA D
T72 PA D

CL K _DMI# <19>
CL K _DMI <19>

CL K _B UF _BCLK# <19>
CL K _B UF _BCLK <19>

CL K _B UF_ DOT 96# <1 9>
CL K _B UF_ DOT 96 <19 >

CL K _B UF _CKS SCD# <19>
CL K _B UF _CKS SCD <1 9>

CL K _1 4M_ PCH <19 >

CL K _P CI_ FB <14>

+3 VALW

WLAN WWAN New 、

、 、

、、

For Intel LAN only

SM B_ EC_CK2 <37>
SM B_ EC_DA2 <37>

PE G_CLKREQ# <1 4>

OK

OK

OK

OK

OK

OK

OK

+1 .05VS

、 card

、、

CL K _PCIE_ VGA# <24 >

CL K _P CIE _VG A <24>

PCH

2

+3 VS

5

Q1 B

3

2N 7002D W-7 -F_ SOT 363 -6

2N 7002D W-7 -F_ SOT 363 -6

4

+3 VS

5

Q4 B

3

2N 7002D W-7 -F_ SOT 363 -6

4

OK

+3 VS

2

Q1 A

6 1

2N 7002D W-7 -F_ SOT 363 -6

+3 VS

2.2K_040 2_5%

2

Q4 A

6 1

XTAL25 _IN

XTAL25 _OU T

+3 VS

R1 05

2.2K_040 2_5%

R1 13 1 M_0402 _5%

R1 06

2.2K_040 2_5%

+3 VS

R6 81

R6 82

2.2K_040 2_5%

SM B_ E C_DA2_RSMB_ EC_DA2

SM B_ E C_CK2_RSMB_ EC_CK2

1 2

Y2

1 2

25 M HZ_20P_1B G25 00 0CK1A

1

C1 41

2

18 P_0 402 _5 0V8J

1

SM B _DATA_S 3SM BD AT A

SM B _CL K_S 3SM B CLK

SM B_ DATA_S3 <1 7,1 8,19, 30>

XDP SODIMM、

、 、

、、

SM B_ CLK _S3 <1 7,1 8,1 9, 30>

SM B_ EC_DA2_R <24>

Nvidisa thermall sensor

SM B_ EC_CK2_R <24>

1

C1 42

2

18 P_0 402 _5 0V8J

、Clock gen、、、、G sensor

、、

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Tit le

Size Do c um en t N umb er R e v

Cu s to m

Da te : She et of

Compal Electronics, Inc.

IBEX-M(2/6)-PCI-E/SMBUS/CLK

Ca lp ella DIS L A4743P

1

12 49Monda y, Apr il 13, 2009

0. 1

5

U 1 C

DM I_ CTX_ PRX _N0<7>
DM I_ CTX_ PRX _N1<7>
DM I_ CTX_ PRX _N2<7>
DM I_ CTX_ PRX _N3<7>

DM I_ CTX_ PRX _P0<7>
DM I_ CTX_ PRX _P1<7>
DM I_ CTX_ PRX _P2<7>

D D

Checklist0.8 MEPWROK
can be connect to
PWROK if iAMT disable

XD P_ DB RESET#<6>

PM _P W ROK<37>

M_ PW RO K< 37>

C C

PM _D R AM _P WRG D<6>

R_ E C_ RS MRST#<4 2>

EC _ RS MRST#<3 7>

PM _P W RBT N#_ R<6>

B B

DM I_ CTX_ PRX _P3<7>

DM I_ CRX_PTX _N0<7>
DM I_ CRX_PTX _N1<7>
DM I_ CRX_PTX _N2<7>
DM I_ CRX_PTX _N3<7>

DM I_ CRX_PTX _P0<7>
DM I_ CRX_PTX _P1<7>
DM I_ CRX_PTX _P2<7>
DM I_ CRX_PTX _P3<7>

+1 .05VS

R1 18 49 .9_ 04 02_ 1%

1 2

4mil width and place
within 500mil of the PCH

：

R1 19 0 _04 02_5%

R3 65 0_ 0402_ 5%

VG ATE<19 ,46 >

R1 20 10 K_0 402 _5 %@

R1 24 1 0K_ 040 2_ 5%

PW RBTN_OUT#<37>

PM _P W ROK PM _ RS MRST#

CH 75 1H-40 PT_SOD323 -2

SY S_ R ST#
PM _C L KRUN#

LO W _B AT#
PM _R I#
IC H _P CI E _WAKE#
EC _ AC IN

1 2

R3 73 0_ 0402_ 5%@

1 2

12

R1 21 0 _04 02_5%
R3 79 0 _04 02_5%@

R1 23

1 2

12

+3 VALW

EC _ AC IN<37>

D3 7

2 1

R1 33 10 K_0 402 _5%@
R1 29 8.2K_040 2_5%

R1 34 8.2K_040 2_5%
R1 36 10 K_0 402 _5%
R1 37 1K_ 04 02_ 5%
R1 38 8.2K_040 2_5%

DM I_ CTX _PR X_N 0
DM I_ CTX _PR X_N 1
DM I_ CTX _PR X_N 2
DM I_ CTX _PR X_N 3

DM I_ CTX _PR X_P0
DM I_ CTX _PR X_P1
DM I_ CTX _PR X_P2
DM I_ CTX _PR X_P3

DM I_ CRX_PT X_N 0
DM I_ CRX_PT X_N 1
DM I_ CRX_PT X_N 2
DM I_ CRX_PT X_N 3

DM I_ CRX_PT X_P0
DM I_ CRX_PT X_P1
DM I_ CRX_PT X_P2
DM I_ CRX_PT X_P3

DM I_ I R COMP

1 2

1 2
1 2

R1 22 10 K_0 402 _5 %

1 2

PM _D R AM _P WR GD

10 0_0 402_5%

R1 51 1 0K_ 040 2_ 5%

1 2

R1 25 0 _04 02_5%

1 2

1 2
1 2

1 2
1 2
1 2

12

SY S_ R ST#

PM _R S MRST#

EC _ AC IN

LO W _B AT#

PM _R I#

+3 VS

+3 VALW

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IB EX PEAK- M_FC BGA 1071

Check PM_SLP_LAN#

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

System Power Management

SLP_LAN# / GPIO29

SUSCLK / GPIO62

SLP_S5# / GPIO63

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

4

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

BJ14
BF13
BH13
BJ12
BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

FD I_ C TX_ PRX_ N0
FD I_ C TX_ PRX_ N1
FD I_ C TX_ PRX_ N2
FD I_ C TX_ PRX_ N3
FD I_ C TX_ PRX_ N4
FD I_ C TX_ PRX_ N5
FD I_ C TX_ PRX_ N6
FD I_ C TX_ PRX_ N7

FD I _CT X_PRX_P0
FD I _CT X_PRX_P1
FD I _CT X_PRX_P2
FD I _CT X_PRX_P3
FD I _CT X_PRX_P4
FD I _CT X_PRX_P5
FD I _CT X_PRX_P6
FD I _CT X_PRX_P7

IC H _P CI E _WAKE#

PM _C L KRUN#

PM _ SUS_STA T#

SU S_ C LK

Can b e left NC when IAMT is
not s upport on the platfrom

If no t using integrated
LAN,s ignal may be left as NC.

FD I_ CT X_PRX_N0 <7>
FD I_ CT X_PRX_N1 <7>
FD I_ CT X_PRX_N2 <7>
FD I_ CT X_PRX_N3 <7>
FD I_ CT X_PRX_N4 <7>
FD I_ CT X_PRX_N5 <7>
FD I_ CT X_PRX_N6 <7>
FD I_ CT X_PRX_N7 <7>

FD I_ CTX _PR X_P0 <7>
FD I_ CTX _PR X_P1 <7>
FD I_ CTX _PR X_P2 <7>
FD I_ CTX _PR X_P3 <7>
FD I_ CTX _PR X_P4 <7>
FD I_ CTX _PR X_P5 <7>
FD I_ CTX _PR X_P6 <7>
FD I_ CTX _PR X_P7 <7>

FD I_ I NT <7>
F DI _ FS YN C0 <7>
F DI _ FS YN C1 <7>
FD I_ L SY NC 0 <7>
FD I_ L SY NC 1 <7>

IC H _P CI E_WAKE# <31 ,32 >

T17

T18

SL P_ S5# <37>

SL P_ S4# <37>

SL P_ S3# <37>

H_ P M_ SY NC <6>

3

R7 70

IG P U_ BKL T_E N

1 2

10 0K_ 040 2_ 5%

IG P U_ BKL T_E N<22>

I_ E NA VD D<21>

DP ST _ PWM<22>

+3 VS

Close PCH and mini space 20mil

I_ C RT _D DC _CL K<20 >
I_ C RT _D D C_D ATA< 20>

I_ C RT _H SYNC< 22>
I_ C RT _V SY NC<22 >

CRB0.9 change to 0 ohm

EDID_ CLK and EDID_DATA single
end a nd keep 30 mil with other
LVDS signal avoid noise

IG P U_ BKL T_E N
I_ E NA VDD

DP ST _ PWM

I_ E DI D_CLK<22 >
I_ E DI D_ DAT A<22>

I_ L VD S_ACLK-< 22>
I_ L VD S_ACLK+<22>

I_ LV DS_ A0-<22>
I_ LV DS_ A1-<22>
I_ LV DS_ A2-<22>

I_ L VDS _A0 +<22>
I_ L VDS _A1 +<22>
I_ L VDS _A2 +<22>

I_ B LUE<22>
I_ G RE EN<22>
I_ R ED<22 >

1 2

R7 71 1 0K_04 02_5%

1 2

R7 72 1 0K_04 02_5%

R7 73 2. 37 K_0 402 _1 %

1 2

T69P AD

I_ B LU E
I_ G R EEN
I_ R ED

0_ 040 2_5%

H SY NC

R7 74

1 2
1 2

V S YNC

R7 75 0 _0 402 _5%

12

R1 26

CRB0.9 change to 1K_0402_0.5%

I_ B LU E
I_ G R EEN
I_ R ED

Pla ce t he 3 re sis tors cl ose to IBEX

1 2

R7 76 15 0_0 402_1%

1 2

R7 77 15 0_0 402_1%

1 2

R7 78 15 0_0 402_1%

T48

T47

Y48

AB48

Y45

AB46

V48

AP39
AP41

AT43
AT42

AV53
AV51

BB47
BA52
AY48
AV47

BB48
BA50
AY49
AV48

AP48
AP47

AY53
AT49
AU52
AT53

AY51
AT48
AU50
AT51

AA52
AB53

AD53

V51
V53

Y53
Y51

AD48

AB51

1K_ 04 02_ 0.5%

U 1 D

L_BKLTEN
L_VDD_EN

L_BKLTCTL
L_DDC_CLK

L_DDC_DATA
L_CTRL_CLK

L_CTRL_DATA
LVD_IBG

LVD_VBG
LVD_VREFH

LVD_VREFL

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

IB EX PEAK-M _FCBGA1 07 1

LVDS

CRT

2

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

SDVO_INTN
SDVO_INTP

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BJ46
BG46

BJ48
BG48

BF45
BH45

T51
T53

BG44
BJ44
AU38

BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38

Y49
AB49

BE44
BD44
AV40

BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

U50
U52

BC46
BD46
AT38

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

HD MI D _C T RLC LK
HD MI D _C T RLD ATA

TM DS _ B_H PD#

1

HD MI D _C TR LCL K <23>
HD MI D _C TR LDA TA <23>

TM DS _B_HPD# <23 >
TM DS D_ DAT A0# <23>

TM DS D_ DAT A0 <23>
TM DS D_ DAT A1# <23>
TM DS D_ DAT A1 <23>
TM DS D_ DAT A2# <23>
TM DS D_ DAT A2 <23>
TM DS D_CLK# <23>
TM DS D_ CLK <23>

SDVO

Display Port B

Display Port C Display Port D

A A

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Tit le

Size Do c um en t N umb er R e v

Cu s to m

Da te : She et

Compal Electronics, Inc.

IBEX-M(3/6)-DMI/GPIO/LVDS

Ca lp ella DIS L A4743P

1

13 49Monda y, Apr il 13, 2009

o f

0. 1

5

PC I_D EV SEL#
PC I_S ER R#
PC I_R EQ0 #
PC I_P IR QB#

PC I_R EQ1 #
PC I_F RAME#
PC I_T RDY#
PC I_P IR QH#

D D

PC I_R EQ3 #
PC I_P I RQF#
PC I_P ER R#
PC I_L OC K#

PC I_P IR QA#
PC I_P IR QD#
PC I_P IRQ G#
PC I_P IR QC#

PC I_P IR QE#
PC I _ST OP#
PC I_I RD Y#

DG P U_ SE LEC T#

C C

R P3

1 8
2 7
3 6
4 5

8. 2K_ 08 04_ 8P4R_ 5%
R P4

1 8
2 7
3 6
4 5

8. 2K_ 08 04_ 8P4R_ 5%
R P5

1 8
2 7
3 6
4 5

8. 2K_ 08 04_ 8P4R_ 5%

R P6

1 8
2 7
3 6
4 5

8. 2K_ 08 04_ 8P4R_ 5%
R P7

1 8
2 7
3 6
4 5

8. 2K_ 08 04_ 8P4R_ 5%

AC CEL _IN T<3 0>

GNT2

Defau lt-Internal pull up
Low=C onfigures DMI for ESI

compa tible operation(for
servers only.Not for
mobile/desktops)

B B

CL K _D EB UG_ POR T_0<3 6>
CL K _D EB UG_ POR T_1<3 1>

A A

PC I _G NT3#

R1 83 1K_04 02_5%@

A16 swap overide Strap/Top-Block
Swap Override jumper

PCI_GNT3#

+3 VS

+3 VS

DG P U_ SE LEC T#<22 >

PC I_S ER R#<37>

PC I_RST#< 36, 37>

0_ 040 2_5%

DG P U_ PW M_ SEL ECT#

R1 50

12

T70 P A D

AC CEL _I NT

*

PC I_PME #<3 7>
PL T_R ST#<6, 31,32>

R_ C LK _ PCI _FB
R_ C LK _ PCI _EC
R_ C LK _DE BUG _PO RT_ 0
R_ C LK _DE BUG _PO RT_ 1

CL K _P CI_ FB<12>
CL K _P CI_ EC<37>

1 2

Low=A16 swap
override/Top-Block
Swap Override enabled
High=Default

5

R1 58 22 _0402 _5%
R1 60 22 _0402 _5%
R1 61 22 _0402 _5%
R1 62 22 _0402 _5%

*

PC I_P IR QA#
PC I_P IR QB#
PC I_P IR QC#
PC I_P IR QD#

PC I_R EQ0 #
PC I_R EQ1 #

DG P U_ SE LEC T#

PC I_R EQ3 #
PC I _G NT0#

PC I _G NT1#
PC I _G NT3#
PC I_P IR QE#

PC I_P I RQF#
PC I_P IRQ G#
PC I_P IR QH#

PC I_S ER R#
PC I_P ER R#

PC I_I RD Y#
PC I_D EV SEL#

PC I_F RAME#
PC I_L OC K#
PC I _ST OP#

PC I_T RDY#

PL T_ RST #

1 2
1 2
1 2
1 2

US B_ O C#0
WX MI T_ OFF #
US B_ O C#1
US B_ O C#2

US B_ O C#6
US B_ O C#5
US B_ O C#4
US B_ O C#7

U 1 E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1# / GPIO50

B45

REQ2# / GPIO52

M53

REQ3# / GPIO54

F48

GNT0#

K45

GNT1# / GPIO51

F36

GNT2# / GPIO53

H53

GNT3# / GPIO55

B41

PIRQE# / GPIO2

K53

PIRQF# / GPIO3

A36

PIRQG# / GPIO4

A48

PIRQH# / GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IB EX PEAK-M _FCBGA1 07 1

R_ C LK _DE BUG _PO RT_ 0
R_ C LK _DE BUG _PO RT_ 1

RP 8

4 5
3 6
2 7
1 8

10 K_1 206 _8 P4R _5%

RP 9

4 5
3 6
2 7
1 8

10 K_1 206 _8 P4R _5%

PCI

R_ C LK _ PCI _FB
R_ C LK _ PCI _EC

+3 VALW

BU F_ PL T_R ST#<6>

4

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

NV_DQS0
NV_DQS1

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11

NVRAM

NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

NV_ALE
NV_CLE

NV_RCOMP

NV_RB#

NV_WR#0_RE#
NV_WR#1_RE#

NV_WE#_CK0
NV_WE#_CK1

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USB

USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

PC I _G NT0#
PC I _G NT1#

Boot BIOS Strap

0
0
1

R1 79 0 _04 02_5%

12

@

10 0K_ 040 2_ 5%

4

R1 85

AY9
BD1
AP15
BD8

AV9
BG8

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

BD3
AY6

AU2
AV7
AY8

AY5
AV11

BF5

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

B25
D25

N16
J16
F16
L16
E14
G16
F12
T15

R1 63 1 K_0 402 _5 %@
R1 64 1 K_0 402 _5 %@

PCI_GNT1#PCI_GNT0#

1 2

U2

@

4

O

GPIO 8

This signal has a weak internal
pull up ,can't Pull low

GPIO15

L I nt：el ME Crypto Transport
Layer Security(TLS) chiper suite
with no confidentiality

H I nt：el ME Crypto Transport
Layer Security(TLS) chiper suite
with confidentiality

*

it ha ve weak internal PU 20K

Check list Rev0.8 section1.23.2 If not
implemented, the Braidwood interface
signals can be left as No Connect (NC).

NV _ ALE
NV _ CL E

GPIO27

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

H O n-D：ie voltage regulator enable

*

US B 20_N0
US B2 0_ P0
US B 20_N1
US B2 0_ P1
US B 20_N2
US B2 0_ P2

US B 20_N4
US B2 0_ P4
US B 20_N5
US B2 0_ P5
US B 20_N6
US B2 0_ P6
US B 20_N7
US B2 0_ P7
US B 20_N8
US B2 0_ P8
US B 20_N9
US B2 0_ P9

US BR B IA S

US B_ O C#0

US B_ O C#1

US B_ O C#2
WX MI T_ OFF #
US B_ O C#4
US B_ O C#5
US B_ O C#6
US B_ O C#7

1 2
1 2

0
1
0
11

+3 VS

5

P

IN1
IN22G

SN 7 4A HC 1 G08 DCKR_SC70 -5

3

L O n-Di：e PLL Voltage Regulator disable

US B2 0_ N0 <35>
US B20_P 0 <35>
US B2 0_ N1 <35>
US B20_P 1 <35>
US B2 0_ N2 <35>
US B20_P 2 <35>

US B2 0_ N4 <21>
US B20_P 4 <21>
US B2 0_ N5 <31>
US B20_P 5 <31>
US B2 0_ N6 <35>
US B20_P 6 <35>
US B2 0_ N7 <35>
US B20_P 7 <35>
US B2 0_ N8 <31>
US B20_P 8 <31>
US B2 0_ N9 <31>
US B20_P 9 <31>

R1 55 22 .6_ 04 02_ 1%

Within 500
mils

1 2

R1 56 0_ 0402_ 5%

Boot BIOS
Location

LPC

12

Reserved(NAND)
PCI
SPI

*

PL T_ RST #

1

MB
MB
MB USB/ESATA
DOCK
USB Camera
WLAN
BT
Finger print
WWAN
New Card

Intel Anti-Theft Techonlogy

NV_ALE

NV _ ALE

NV _ CL E

3

R1 40 1 K_0 402 _1 %

1 2

+3 VS

DG P U_ HO LD _RST#<24>

R1 45 1 0K_ 040 2_ 5%

1 2

+3 VS

PC H_T EMP_ ALE RT#

BT _O FF <35>

WX MI T_OFF# <31>

High=Endabled
Low=Disable(floating)

R1 74 1 K_0 402 _5 %@

1 2

DMI Termination Voltage

Set to Vcc when HIGH

NV_CLE

Set to Vss when LOW

Weak internal
PU,Do not pull low

R1 84 1 K_0 402 _5 %@

1 2

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DG P U_ ED ID SEL#<2 0>
DG P U_ HP D_ INT#<2 3>

EC _ SCI #<3 7>
EC _ SMI#<3 7>

CR _ WA KE #<32>

XM IT _OFF<31 >

Internal VccVRM Option

DG P U_ PW R _EN<23 ,3 9,4 5,4 7>

*

+1 .8VS

+3 VS

U 1 F

PC H_G PIO 0
DG P U_ ED I DSEL #
DG P U_ HP D _IN T#
EC _ SC I#
EC _ SMI #
PC H_G PIO 12
PC H_G PIO 15
DG P U_ HO L D_RST#
DG P U_ PW R OK
CR _ WA K E#
XM I T_O FF

PC H_G PIO 28
H_ S TP _PCI#
G PIO 35
DG P U_ PW R _EN
VG A_P RSN T_L #
G PIO 38
G PIO 39
PC IEC L KREQ 6#
PC IEC L KREQ 7#
G PIO 48
PC H_T EMP _AL ERT#
G PIO 57

NV_ALE

Enabl e Intel Anti-Theft
Techn ology 8.2K PU to +3VS

Disab le Intel Anti-Theft
Techn ology floating(internal PD)

NV_CLE

DMI t ermination voltage.
weak internal PU, don't PD

2008/03/13 2009/05/11

Y3

BMBUSY# / GPIO0

C38

TACH1 / GPIO1

D37

TACH2 / GPIO6

J32

TACH3 / GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CTRL / GPIO12

T7

GPIO15

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

Y7

SCLOCK / GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI# / GPIO34

V6

SATACLKREQ# / GPIO35

AB7

SATA2GP / GPIO36

AB13

SATA3GP / GPIO37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PCIECLKRQ6# / GPIO45

F1

PCIECLKRQ7# / GPIO46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IB EX PEAK-M _FCBGA1 07 1

：

：

PE G_CLKREQ#<12>

Compal Secret Data

2

GPIO

NCTF

Deciphered Date

2

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P

CLKOUT_PCIE7P

PROCPWRGD

CPU

RSVD

+3 VS_NV

2

Q2 9A
2N 7002D W-7 -F_ SOT 363 -6

Q2 9B

61

5

AH45

T19 PA D

AH46

T20 PA D

AF48

T21 PA D

AF47

T22 PA D

GA TE A20

U2

A20GATE

AM3
AM1

PC H_P EC I_ R

BG10

PECI

KB _ RST#

T1

RCIN#

BE10

H_ THE RMT RIP#_L

BD10

THRMTRIP#

BA22

TP1

AW22

TP2

BB22

TP3

AY45

TP4

AY46

TP5

AV43

TP6

AV45

TP7

AF13

TP8

M18

TP9

N18

TP10

AJ24

TP11

AK41

TP12

AK42

TP13

M32

TP14

N32

TP15

M30

TP16

N30

TP17

H12

TP18

AA23

TP19

AB45

NC_1

AB38

NC_2

AB42

NC_3

AB41

NC_4

T39

NC_5

P6

INIT3_3V#

C10

TP24

DG P U_ PW R OK

3

4

2N 70 02 DW- 7-F_SO T36 3-6

Tit le

Size Do c um en t N umb er R e v

Cu s to m

Ca lp ella DIS L A4743P

Da te : She et of

GA TEA 20 <37 >

CL K _C PU _BC LK# <6>
CL K _C PU _BC LK <6>

R1 44 0_040 2_5%

KB _RST# <37>
H_ C PU PW RGD <6>

1 2

R1 46

EC _ SC I#
DG P U_ ED I DSEL #
KB _ RST#
DG P U_ PW R _EN
DG P U_ HP D _IN T#
VG A_P RSN T_L #
DG P U_ HO L D_RST#
G PIO 38
GA TE A20
PC H_T EMP _AL ERT#
G PIO 39
G PIO 48
CR _ WA K E#
DG P U_ PW R OK

INIT3_3V

This signal has weak internal
PU, can't pull low

T48 PA D

EC _ SMI #
PC H_G PIO 15
PC H_G PIO 12
PC IEC L KREQ 6#
PC IEC L KREQ 7#
PC H_G PIO 28
G PIO 57
G PIO 35
VG A_P RSN T_L #

Compal Electronics, Inc.

IBEX-M(4/6)-PCI/USB/RSVD

1

1 2

54 .9_ 0402_ 1%

12

R1 47
56 _04 02_5%

R1 66 1 0K_ 040 2_ 5%

1 2

R1 67 1 0K_ 040 2_ 5%

1 2

R1 71 1 0K_ 040 2_ 5%

1 2

R1 72 1 0K_ 040 2_ 5%

1 2

R1 73 1 0K_ 040 2_ 5%

1 2

R1 75 1 0K_ 040 2_ 5%

1 2

R1 76 1 0K_ 040 2_ 5%

1 2

R1 78 1 0K_ 040 2_ 5%

1 2

R1 80 1 0K_ 040 2_ 5%

1 2

R1 81 1 0K_ 040 2_ 5%

1 2

R1 69 1 0K_ 040 2_ 5%

1 2

R1 70 1 0K_ 040 2_ 5%

1 2

R1 68 1 0K_ 040 2_ 5%

1 2

R8 74 1 0K_ 040 2_ 5%

1 2

R1 57 10 K_0 402_5 %

1 2

R1 59 1K_04 02_5%

1 2

R8 11 10 K_0 402_5 %

1 2

R8 12 10 K_0 402_5 %

1 2

R8 13 10 K_0 402_5 %

1 2

R8 14 10 K_0 402_5 %

1 2

R1 82 10 K_0 402_5 %

1 2

R1 65 10 K_0 402_5 %
R9 11 10 K_0 402_5 %

1 2

1

OK

H_ P ECI <6>

H_ THE RMT RIP# <6>

+V CCP

+3 VS

+3 VALW

12

0. 1

14 49Monda y, Apr il 13, 2009

5

4

3

2

1

1

2

1 2

1

1

C1 62

2

2

10 U_0 805_6 .3V 6M

1 2

0. 1U_04 02_16 V4Z

+1 .8VS

+1 .05VS

1

C1 73

2

1U_04 02_6. 3V6 K

+V 1.1 A_ I NT_VCCS US

+3 VALW

+3 VS

0.

0. 1A @1.1 V

0.0.

1

1

C1 88

2

2

4. 7U_06 03_6. 3V6 K

2m

2m A@ 3.3V

2m2m

1

2

+V CCP _V CC A_C LK

1

C1 43

@

@

2

10 U_0 805_6 .3V 6M

C1 52

0. 1U_04 02_16 V4Z

+1. 05 VS

1

C1 53

2

1

C1 63

2

10 U_0 805_6 .3V 6M

+V CCR TCEX T

1

C1 74

C1 75

2

1U_04 02_6. 3V6 K

+V CCS ST

0.

0. 2A @3.3 V

2A@ 3.3V

0.0.

2A@ 3.3V2A@ 3.3V

0.

0. 4A @3.3 V

4A@ 3.3V

0.0.

4A@ 3.3V4A@ 3.3V

1A@ 1.1V

1A@ 1.1V1A@ 1.1V

1

C1 89

2

0. 1U_04 02_16 V4Z

A@3 .3V

A@3 .3VA@3 .3V

1

C1 97

C1 96

2

0. 1U_04 02_16 V4Z

AP51

C1 44

AP53

1U_04 02_6. 3V6 K

AF23
AF24

Y20

AD38
AD39
AD41
AF43
AF41

1U_04 02_6. 3V6 K

AF42

V39
V41
V42
Y39

C1 61

Y41

1U_04 02_6. 3V6 K

Y42

V9

AU24

BB51
BB53

BD51
BD53

AH23

AJ35

AH35
AF34
AH34

1U_04 02_6. 3V6 K

AF32

V12

Y22

P18
U19
U20
U22

V15
V16
Y16

AT18

AU18

C1 90

A12

0. 1U_04 02_16 V4Z

0. 1U_04 02_16 V4Z

U 1 J

VCCACLK[1]
VCCACLK[2]

VCCLAN[1]
VCCLAN[2]

DCPSUSBYP

VCCME[1]
VCCME[2]
VCCME[3]
VCCME[4]
VCCME[5]
VCCME[6]
VCCME[7]
VCCME[8]
VCCME[9]
VCCME[10]
VCCME[11]
VCCME[12]

DCPRTC

VCCVRM[3]

VCCADPLLA[1]
VCCADPLLA[2]

VCCADPLLB[1]
VCCADPLLB[2]

VCCIO[21]
VCCIO[22]
VCCIO[23]

VCCIO[2]
VCCIO[3]
VCCIO[4]
DCPSST

DCPSUS

VCCSUS3_3[29]
VCCSUS3_3[30]
VCCSUS3_3[31]
VCCSUS3_3[32]

VCC3_3[5]
VCC3_3[6]
VCC3_3[7]

V_CPU_IO[1]

V_CPU_IO[2]

VCCRTC

IB EX PEAK-M _FCBGA1 07 1

POWER

0.052A

0.344A

1.998A

0.035A

0.072A

0.073A

3.208A

2mA

+1 .05VS

+1 .05VS

V24

VCCIO[5]

V26

VCCIO[6]
VCCIO[7]
VCCIO[8]

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]

VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]

USB

VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]

0.163A

VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]

VCCSUS3_3[28]

VCCIO[56]

>1mA

V5REF_SUS

>1mA

V5REF

VCC3_3[8]

0.357A

PCI/GPIO/LPC

0.032A

SATA

6mA

HDA

VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]

VCCSATAPLL[1]
VCCSATAPLL[2]

VCCIO[9]

VCCVRM[4]

VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]

VCCIO[14]
VCCIO[15]
VCCIO[16]

VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]

VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]

VCCSUSHDA

4

Clock and Miscellaneous

CPU

RTC PCI/GPIO/LPC

1
Y24
Y26

2

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

U23
V23

IC H _V 5R E F_S US

F24

IC H _V 5R E F_ RU N

K49

+3 VS

J38
L38
M36
N36
P36

+3 VS

U35

AD13

+1 . 05V S_V CCAPLL

AK3
AK1

AH22

AT20

+1 .8VS

AH19
AD20
AF22
AD19

AF20
AF19
AH20

AB19
AB20
AB22
AD22

+P CH_ VCC 1_1 _2 0

AA34

+P CH_ VCC 1_1 _2 1

Y34

+P CH_ VCC 1_1 _2 2

Y35

+P CH_ VCC 1_1 _2 3

AA35

+3 . 3A _1. 5A_ VCC PAZS US

L30

C1 50

1U _0402 _6.3V6K

+3 VALW

1

1

C1 58

C1 57

2

2

0. 1U_04 02_16 V4Z

0. 1U_04 02_16 V4Z

+1 .05VS

1

C1 71

2

0. 1U_04 02_16 V4Z

C1 76 0. 1U_ 0402_ 16V4Z

1 2

0.

0. 1A @1.1 V

1A@ 1.1V

0.0.

1A@ 1.1V1A@ 1.1V

10 UH_ LB2 012 T10 0MR _20%_ 080 5

1

1

C1 80

C1 81

2

@

@

2

1U_04 02_6. 3V6 K

10 U_0 805_6 .3V 6M

1

C1 84

2

1U_04 02_6. 3V6 K

R1 94 0_ 0402_ 5%

1 2

R1 95 0_ 0402_ 5%

1 2

R1 98 0_ 0402_ 5%

1 2

R2 00 0_ 0402_ 5%

1 2

+3 VALW

1

C1 93

2

1U_04 02_6. 3V6 K

L4

@

1 2

+1 .05VS

+1 .05VS

+1 .05VS

R1 88

@

1 2

10 UH_ LB2 012 T10 0MR _20%_ 080 5

0_ 060 3_5%

C6 82 0 .1U _04 02 _16 V4Z

+1 .05VS+1. 05VS_VCCA PLL _L

R1 89

@

1 2

0_ 060 3_5%

+1 .05VS_ L+1.0 5VS +V 1.05S_ VCCA_A_ DPL _L

R1 91

1 2

0_ 060 3_5%

1 2

0_ 060 3_5%

R2 01

1 2

0_ 060 3_5%

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED BY COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE US ED B Y OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1 2

+3 VS

1 2

+1 .8VS

+1 .05VS

R1 92

+V 1.0 5S_VCC A_B _DP L_L

1

1

C1 45

2

2

1U_04 02_6. 3V6 K

+1 .05VS_ APL L

L3

@

1

2

+1 .05VS

1

1

C1 64

2

2

1U_04 02_6. 3V6 K

1

1

2

10 UH_ LB2 012 T10 0MR _20%_ 080 5

10 UH_ LB2 012 T10 0MR _20%_ 080 5

1

C1 69

C1 68

2

2

1U _0402 _6.3V6K

1U _0402 _6.3V6K

+1 . 05 V S_V CCFDIPL L

L6

1 2

L7

1 2

U1 G

AB24

VCCCORE[1]

AB26

VCCCORE[2]

AB28

VCCCORE[3]

AD26

VCCCORE[4]

AD28

VCCCORE[5]

AF26

C1 46

VCCCORE[6]

AF28

VCCCORE[7]

AF30

VCCCORE[8]

10 U_0 603_6 .3V 6M

AF31

VCCCORE[9]

AH26

VCCCORE[10]

AH28

VCCCORE[11]

AH30

VCCCORE[12]

AH31

VCCCORE[13]

AJ30

VCCCORE[14]

AJ31

VCCCORE[15]

AK24

VCCIO[24]

BJ24

VCCAPLLEXP

AN20

VCCIO[25]

AN22

VCCIO[26]

AN23

C1 59

VCCIO[27]

@

AN24

VCCIO[28]

AN26

VCCIO[29]

10 U_0 805_6 .3V 6M

AN28

VCCIO[30]

BJ26

VCCIO[31]

BJ28

VCCIO[32]

AT26

VCCIO[33]

AT28

VCCIO[34]

AU26

VCCIO[35]

AU28

VCCIO[36]

AV26

VCCIO[37]

AV28

VCCIO[38]

AW26

VCCIO[39]

AW28

VCCIO[40]

BA26

C1 65

VCCIO[41]

BA28

VCCIO[42]

BB26

1U_04 02_6. 3V6 K

VCCIO[43]

BB28

VCCIO[44]

BC26

VCCIO[45]

BC28

VCCIO[46]

BD26

VCCIO[47]

BD28

VCCIO[48]

BE26

VCCIO[49]

BE28

VCCIO[50]

BG26

VCCIO[51]

BG28

C1 70

VCCIO[52]

BH27

VCCIO[53]

10 U_0 603_6 .3V 6M

AN30

VCCIO[54]

AN31

VCCIO[55]

AN35

VCC3_3[1]

AT22

VCCVRM[1]

BJ18

VCCFDIPLL

AM23

VCCIO[1]

IB EX PEAK-M _FCBGA1 07 1

+V 1.0 5S_VC CA_ A_D PL

2

1

+V 1.0 5S_VC CA_ B_D PL

1

2

2008/03/13 2009/05/11

POWER

1.524A

0.042A

0.035A
6mA

1

+

C1 86

C1 87

2

1U_04 02_6. 3V6 K

22 0U_D2_4 VM_ R15

1

+

C1 92

C1 91

2

1U _0402 _6.3V6K

22 0U_B_2. 5VM_ R1 5M

Compal Secret Data

Deciphered Date

AE50

VCCADAC[1]
VCCADAC[2]

VCCALVDS

VSSA_LVDS

VCC3_3[2]
VCC3_3[3]
VCC3_3[4]

AE52
AF53
AF51

AH38
AH39

AP43
AP45
AT46
AT45

AB34
AB35
AD35

0.069A

VSSA_DAC[1]

CRTLVDS

VSSA_DAC[2]

0.030A

VCC CORE

VCCTX_LVDS[1]

0.059A

VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]

HVCMOS

AT24

VCCVRM[2]

AT16

VCCDMI[1]

0.061A

DMI

VCCPNAND[1]

PCI E*

VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]

0.156A

VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]

VCCME3_3[1]

NAND / SPI

VCCME3_3[2]

0.085A

VCCME3_3[3]

12

2

VCCME3_3[4]

R1 93

@

0_ 060 3_5%

FDI

VCCDMI[2]

AU16

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

AM8
AM9
AP11
AP9

1

2

C9 98

1

2

+1 .8 VS

+V CCP

+1 .05VS

R1 96

10 0_0 402_5%

1

C1 48

C1 47

2

10 U_0 805_6 .3V 6M

0.01U _04 02 _25 V7K

0.01U _06 03 _16 V7K

0.01U _06 03 _16 V7K
C1 000

C9 99

1

1

2

2

1

C1 67

2

1U _0402 _6.3V6K

1

C1 72

2

0. 1U_04 02_16 V4Z

+3 VS

1

C1 78

2

0. 1U_04 02_16 V4Z

R1 90

@

1 2

0_ 060 3_5%

21

12

D 4
CH 75 1H-40 PT_SOD323 -2

1

C1 94
1U_04 02_6. 3V4 K_X 5R

2

Tit le

Size Do c um en t N umb er R e v

Cu s to m

Da te : She et of

L4 5

MU RA TA_ BLM18A G601SN1D _06 03

1

C1 49

2

0. 1U_04 02_16 V4Z

+3 VS

R7 79 0 _06 03_5%

1 2

10 U_0 805_6 .3V 6M

+3 VS

1

C1 60

2

0. 1U_04 02_16 V4Z

R6 71 0_040 2_5%

1 2

R6 72 0_040 2_5%@

1 2

+1 . 05 VS_VC CFD IPL L_L

10 UH_ LB2 012 T10 0MR _20%_ 080 5

IC H _V 5R E F_S US

Compal Electronics, Inc.

IBEX-M(5/6)-PWR

Ca lp ella DIS L A4743P

12

L5

@

1 2

R1 97

10 0_0 402_5%

1

+3 VS

+1 .8VS

+1 .8VS

+3 VS

+1 . 05 V S_V CCFDIPL L

+5 VS +3 VS+3 VALW+5 VALW

12

1

C1 83

@

2

10 U_0 805_6 .3V 6M

21

D 5

CH 75 1H-40 PT_SOD323 -2

IC H _V 5R E F_ RU N

20 mils20 mils

1

C1 95
1U_04 02_6. 3V4 K_X 5R

2

15 49Monda y, Apr il 13, 2009

0. 1

+1 .05VS + VC C P_ VC CA_ CLK _L

R1 86

@

1 2

0_ 060 3_5%

10 UH_ LB2 012 T10 0MR _20%_ 080 5

D D

C C

B B

A A

DG1.1 no M3
support and not
Intel LAN, VCCLAN
Source=>GND

+R TC VCC

L1

@

1 2

C1 66

+V 1.0 5S_VC CA_ A_D PL
+V 1.0 5S_VC CA_ B_D PL

1

2

1 2

0. 1U_04 02_16 V4Z

C1 77

1 2

0. 1U_04 02_16 V4Z

C1 79

1 2

0. 1U_04 02_16 V4Z

C1 82

1 2

0. 1U_04 02_16 V4Z

C1 85

+V CCP

5