Compal LA-4743P Schematics

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Arrandale rPGA989 with

3 3

4 4

A

Intel PCH(Ibex Peak-M) core logic

2009-09-10

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

Calpella DIS LA4743P

1 52Friday, September 11, 2009

E

0.4

A

B

C

D

E

Compal confidential

1 1

ATI M93

VRAM DDR3

128/512MB

page 29

Fan conn

page 24,25 ,26,27,28

Dis Dis(UMA)

Page 6

LCD Conn.

page 21

MUX

PCIE-Express 16X

Calpella Consumer 13.3" UMA +Switchable

32QFN

P19

DDR3 SO-DIMM X2

BANK 0, 1, 2, 3

UMA

Mobile Arrandale

2C CPU + GMCH

Socket-rPGA989

Page 6,7,8,9,10

CK505

Clock Generator
SLG8SP585VTR

DDR3 1066/1333 MHz 1.5V

Dual Channel

P17, 18

USB Card reader
RTS 5138

CRT

page 20

MUX

2 2

Dis

HDMI Conn.

page 23

Level Shifter

UMA

Dis(UMA)Dis

UMA

page 23

FDI

Intel PCH

Ibex Peak-M

PCI-E BUS*4

Realtek 8401
(10/100 LAN +Card
reader)

UMA only

3 3

P33

(Giga LAN)

DIS only

P32

Mini-Card

WLAN

Mini-CardRealtek 8111DL

WWAN

P31P31 P31

New Card

FCBGA 951

Page 11,12,13,14,15,16

RJ45/11 CONN

P31

ENE

DMI X4

LPC BUS

USB2.0 X12

Azalia

SATA Master-1

SATA Slave

SPI

SPI ROM 16M

P34

MX25L1605AM2C-15G

4M Bytes

KB926

Version D2

P38

DIS only

USB conn x3

BT Conn

USB Camera

Finger print

Touch Screen

Audio CKT

Codec_IDT92HD80

SATA HDD Connector

SATA ODD Connector

P33

P36

P36

P21

P36

P21

P34 P35

Audio Jack

P30

P30

RTC CKT.

P11

LED

P39

ACCELEROMETER
ST

4 4

P30

Touch Pad CONN.

P39

SPI ROM
SST25VF080

256K bits

K/B backlight Conn

P36

Security Classification

DC/DC Interface CKT.

A

P40

B

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

Int.KBD

P38

USB Board Conn

P37

USB conn x2

Capsense switch Conn

2006/02/13 2006/03/10

C

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

Calpella DIS LA4743P

E

2 52Friday, September 11, 2009

P36

P36

0.4

A

Symbol Note :

Voltage Rails

power
plane

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

1 1

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK
SML1DATA

KB926

KB926

PCH

PCH

PCH

NB10M-GE SMBUS Control Table

D_EDID_DATA
D_EDID_CLK
D_CRT_DDC_DATA
D_CRT_DDC_DATA
HDMIDAT_VGA
HDMICLK_VGA

O MEANS ON X MEANS OFF

+B

O

O

O

O

O

XDP BATT

X V
X

V

X

SOURCE LVDS CRT

M93

M93

M93

X X

V

X

V

X

X

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build

+5VALW

+3VALW

+1.8V

+5VS
+3VS
+1.5VS
+0.9V
+VCCP
+CPU_CORE
+2.5VS
+1.8VS

45@ : means need be mounted when 45 level assy or rework stage.
BATT @ : means need be mounted when 45 level assy or rework stage.
CONN@ : means ME part

SG@ : means stuff when Switchable graphic

UMA@ : means stuff when UMA skus

X76@ : X76 level

PA@ : Only For PA

O

O

O

O

X

XX

Thermal
Sensor

X
X
X
X

X

X

X

HDMI

X

V

O

O

O

X

X

X

SODIMM CLK CHIP

X
X

X

X

V V V

X

X

O

O

X

X

PR@ : Only For PR

8111@ : Only DIS Giga LAN use
5138@ : Only DIS card reader use

8401@ : Only UMA (LAN + Card reader) use
Park@ : Only for Park use

X

X

WLAN
WWAN

+3VALW +3VALW+3VS+3VS+3VS +3VS+5VL +5VL

M93

NB10M-GE

Thermal
Sensor

X
X

X
X X
X

X

X
X

Cap sensor
board

X

X

X
X
X

X

X

X XXX X X X X X X

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

NEW
CARD

X X
X

V V

X

A

G sensor

PCH I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0
DDR SO-DIMM 1

X

X

2007/08/28 2006/03/10

Compal Secret Data

CLOCK GENERATOR (EXT.)

NBW10 SKUs

43172932L01：PA Switchable graphic

3172932L02：PA UMA

4
43172932L03：PR Switchable graphic
43172932L04：PR UMA

PCB part number

CB：DA80000EW00

P
PA：DAZ09A00800
PR：DAZ09A00900

PCH version

A1 QV73 SA00002KV10
B0 QLLT SA00002KV30
B1 QMGS SA00002KV60
B3 QMNT SA00003N730

Deciphered Date

PA@

ZZZ1

PCB-MB

USB assignment:

USB-0 Right side
USB-1 Right side
USB-2 Left side(with ESATA)
USB-3 Touch Screen
USB-4 Camera
USB-5 WLAN

USB-6 X
USB-7 X

USB-8 MiniCard(WWAN/TV)
USB-9 New card
USB-10 USB Card reader
USB-11 Finger Print
USB-12 Bluetooth
USB-13 X

PCIe assignment:

PCIe-1 WWAN
PCIe-2 WLAN
PCIe-3 LAN
PCIe-4 New card
PCIe-5 RTL8401 Combo
PCIe-6 X

PCIe-7 X
PCIe-8 X

SATA assignment:

SATA0 HDD
SATA1 ODD

SATA2 X
SATA3 X

SATA4 ESATA
SATA5 X

HEX

A0

D2
1DG sensor 0 0 0 1 1 1 0 1

PA@/SG@/8111@/8401@
PA@/UMA@/8401@
PR@/SG@/8111@/8401@
PR@/UMA@/8401@

PR@

ZZZ2

PCB-MB

Title

Size Document Number Rev

Custom

Date: Sheet of

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0

Compal Electronics, Inc.

Notes List

Calpella DIS LA4743P

3 52Friday, September 11, 2009

0.4

5

4

3

2

60mA

+3VAUX_BT

1

50mA

1A

D D

VIN

AC

C C

B+

7A

+V_BATTERY Dock con

0.3A

INVPWR_B+

2A

B++

LVDS CON

1.7A

+3VALW

+1.5VS

+5VALW

35mA

169mA

300mA

MDC 1.5

ICH9

LAN

3.39A5.89A

+3VS

RT5158

??mA

???A

1.3A0.58A

Mini card

New card

+5VS

35mA

10mA

25mA

20mA

10mA

1A

811mA

1.5A

250mA

1A

1A

+VDDA
IDT 9271B7

+5VAMP

Finger printer

+3VS_DVDD
ALC268

+3VALW_EC

SPI ROM

New card

PCH

+LCDVDD

LVDS CON

+3VS_CK505

Mini card (WLAN)

Mini card (TV tu/WWAN/Robeson)

1.8A

B B

3.7 X 3=11.1V

BATT

DC

B+++

A A

CPU_B+ +VCC_CORE

5

11.05A1.9A

4.7A

+1.5V

1.05V_B+

+1.05VS PCH

10mA2A

4

38A/1.05V

3A

8 A

50mA

+VCCP

2.59A

CPU

CPU

DDR3 800Mhz 4G x2

+0.75V

162mA

??A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

PCH

CPU

2007/08/28 2006/03/10

700mA

50mA

Compal Secret Data

Deciphered Date

ODD

SATA

PC Camera(4.75V)

2

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Calpella DIS LA4743P

Date: Sheet of

Power delevry

1

4 52Friday, September 11, 2009

0.4

A

1 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Notes List

Calpella DIS LA4743P

5 52Friday, September 11, 2009

0.4

Layout rule：10mil
width trace length <

0.5", spacing 20mil

D D

H_PECI<14>

H_PROCHOT#<47>

H_THERMTRIP#<14,26>

H_CPURST#

H_PM_SYNC<13>

H_CPUPWRGD

H_CPUPWRGD<14>

PM_DRAM_PWRGD<13>

C C

BUF_PLT_RST#<14>

Design guide

1.11update,PLTR ST series
resittor 1.5K, PL
resistor 750 oh m

Processor Pullups

H_CATERR#

H_CPURST#_R

B B

H_PROCHOT#

DDR3 Compensation Signals

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

Layout Note:Please these
resistors near Processor

A A

5

R1 20_0402_1%

1 2

R3 20_0402_1%

1 2

R5 49.9_0402_1%

1 2

R7 49.9_0402_1%

1 2

TP_SKTOCC#

T1PAD

H_CATERR#

R1063

H_PECI_ISO

0_0402_5%

H_PROCHOT#

H_THERMTRIP#

H_CPURST#_R

0_0402_5%

H_PM_SYNC_R

0_0402_5%

SYS_AGENT_PWROK

0_0402_5%

VCCPWRGOOD_0

0_0402_5%

VDDPWRGOOD_R

VTTPWRGOOD_R

H_PWRGD_XDP_RH_PWRGD_XDP

0_0402_5%

PLT_RST#_R

12

R28

12

R10

1 2

R19

1 2

R20

1 2

R21

1 2

R23

1 2

1 2

0_0402_5%

R25

1 2

R26

1 2

1.5K_0402_1%

750_0402_1%

R35 49.9_0402_1%

1 2

R36 68_0402_5%@

1 2

R11 68_0402_5%

R40 100_0402_1%

1 2

R41 24.9_0402_1%

1 2

R42 130_0402_1%

1 2

COMP3

COMP2

COMP1

COMP0

+VCCP

JCPU1B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC,AUB_CFD_rPGA,R1P0

CONN@

JTAG MAPPING

XDP_TDI_R

XDP_TDI_M

XDP_TDO_R

XDP_TRST#

MISC THERMAL

PWR MANAGEMENT

R30 0_0402_5%

1 2

R32 0_0402_5%@

1 2

R34
0_0402_5%

1 2

R37 0_0402_5%@

1 2

R38 0_0402_5%

1 2

R39 51_0402_1%

1 2

4

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PM_EXT_TS#[0]
PM_EXT_TS#[1]

DDR3

MISC

JTAG & BPM

PRDY#

PREQ#

TRST#

TDO_M

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

XDP_TDI

XDP_TDOXDP_TDO_M

TCK
TMS

TDO

TDI_M

DBR#

TDI

CLK_CPU_BCLK

A16

CLK_CPU_BCLK#

B16

CLK_CPU_XDP

AR30

CLK_CPU_XDP#

AT30

CLK_EXP

E16

CLK_EXP#

D16

A18
A17

F6

AL1
AM1
AN1

AN15
AP15

AT28
AP27

AN28
AP28
AT27

AT29
AR27
AR29
AP29

AN25

AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23

eDP

SM_DRAMRST#

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

PM_EXTTS#0
PM_EXTTS#1

XDP_PRDY#
XDP_PREQ#

XDP_TCK
XDP_TMS
XDP_TRST#

XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M

XDP_DBRESET#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

SM_DRAMRST#

R1065

100K_0402_5%

SI：Reserve Reset I C for DRAM RESE T
PV：Add Intel S3 re duce circuit

T63 PAD

R14 0_0402_5%

1 2

PM_EXTTS#0

PM_EXTTS#1

R1073

@

0_0402_5%

1 2

Q87

2N7002_SOT23-3

S

G

2

12

1

2

CLK_CPU_BCLK <14>
CLK_CPU_BCLK# <14>

CLK_EXP <12>
CLK_EXP# <12>

R27 10K_0402_5%

R29 10K_0402_5%

+1.5V

D

13

C1298

470P_0402_50V7K

3

OK

PM_EXTTS#1_R <17,18>

1 2

1 2

12

R1064

1K_0402_1%

DRAMRST# <17,18>

PCH_DDR_RST <14>

from DDR

+VCCP

XDP_PREQ#
XDP_PRDY#

XDP_BPM#0
XDP_BPM#1

XDP_BPM#2

+VCCP

XDP_BPM#3

1

R1084

2

XDP_BPM#4
XDP_BPM#5

XDP_BPM#6
XDP_BPM#7

H_CPUPWRGD_R
PM_PWRBTN#_R

2

1

VTTPWRGOOD_R

12

C1

@

0.1U_0402_16V4Z

R13

H_CPUPWRGD

PM_PWRBTN#_R<13>

H_PWRGD_XDP

VTTPWRGOOD<45>

PV

：

Change solutio n for S3 leakag e issue.

1K_0402_5%

1 2

VTTPWRGOOD

1 2

2K_0402_1%

Fan Voltage Control circuit

+3VS

R678

10K_0402_5%

1 2

FAN_SPEED<38>

FAN_SPEED

C775

1000P_0402_50V7K

1

2

2

XDP_RST#_R

+3VALW

5

U54

P

B

4

Y

A

G

NC7SZ08P5X_NL_SC70-5

3

R1085

1.5K_0402_1%

U32

9

Thermal Pad

8

GND

7

GND

6

GND

5

GND

G996RD1U_TDFN8_3X3

FAN_SET<38>

XDP Connector

JP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

R22 0_0402_5%@

1 2

1.5VSCPU_DRAM_PWRGD

+5VS

1

VEN

2

VIN

3

VO

4

VSET

XDP_TDI

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

GND17

CONN@

1.5VSCPU_DRAM_PWRGD <46>

R1072

12

1.5K_0402_1%

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

TD0

54
56

TDI

58

TMS

60

PLT_RST# <14,24,31,32,33>

VDDPWRGOOD_R

12

R117
750_0402_1%

XDP_TMS

XDP_PREQ#

XDP_TDO

This shall place near CPU

XDP_TCK

+VCCP

CLK_CPU_XDP
CLK_CPU_XDP#

XDP_RST#_R
XDP_DBRESET#_R

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMSXDP_TCK

XDP_DBRESET#

R31 1.1K_0402_1%@

R33 3K_0402_1%@

SI-1 Change to voltage control circuit

1

C2

2.2U_0603_6.3V4Z

2

1

C774

2.2U_0603_6.3V4Z

2

+5VS_FAN

+5VS

3
2
1

FAN_SPEED

D1

Vcc
Line to be protected
GND

DLPT05-7-F_SOT23-3

1

R2 51_0402_1%@

1 2

R4 51_0402_1%@

1 2

R6 51_0402_1%@

1 2

R8 51_0402_1%

1 2

R9 51_0402_1%@

1 2

R17
1K_0402_5%

1 2

1 2

R18
0_0402_5%

R603 1K_0402_5%

1 2

PV： Change to
+1.5VS_CPU, fol low
checklist

1 2

1 2

1

C3

0.1U_0402_16V4Z

2

CONN@

JFAN1

1
2
3

ACES_85204-03001

H_CPURST#

XDP_DBRESET# <13>

+1.5VS_CPU

1

4

2

G1

5

3

G2

+VCCP

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Auburndale(1/5)-Thermal/XDP

Calpella DIS LA4743P

1

6 52Friday, September 11, 2009

0.4

5

JCPU1A

DMI_CRX_PTX_N0<13>
DMI_CRX_PTX_N1<13>
DMI_CRX_PTX_N2<13>
DMI_CRX_PTX_N3<13>

DMI_CRX_PTX_P0<13>
DMI_CRX_PTX_P1<13>

D D

DMI_CRX_PTX_P2<13>
DMI_CRX_PTX_P3<13>

DMI_CTX_PRX_N0<13>
DMI_CTX_PRX_N1<13>
DMI_CTX_PRX_N2<13>
DMI_CTX_PRX_N3<13>

DMI_CTX_PRX_P0<13>
DMI_CTX_PRX_P1<13>
DMI_CTX_PRX_P2<13>
DMI_CTX_PRX_P3<13>

FDI_CTX_PRX_N0<13>
FDI_CTX_PRX_N1<13>
FDI_CTX_PRX_N2<13>
FDI_CTX_PRX_N3<13>
FDI_CTX_PRX_N4<13>
FDI_CTX_PRX_N5<13>
FDI_CTX_PRX_N6<13>
FDI_CTX_PRX_N7<13>

FDI_CTX_PRX_P0<13>
FDI_CTX_PRX_P1<13>
FDI_CTX_PRX_P2<13>
FDI_CTX_PRX_P3<13>
FDI_CTX_PRX_P4<13>
FDI_CTX_PRX_P5<13>

C C

FDI_CTX_PRX_P6<13>
FDI_CTX_PRX_P7<13>

FDI_FSYNC0<13>
FDI_FSYNC1<13>

FDI_INT<13>

FDI_LSYNC0<13>
FDI_LSYNC1<13>

B B

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD_rPGA,R1P0

CONN@

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]

DMI Intel(R) FDI

PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

4

EXP_ICOMPI

B26
A26
B27

EXP_RBIAS

A25

PCIE_CRX_GTX_N0

K35

PCIE_CRX_GTX_N1

J34

PCIE_CRX_GTX_N2

J33

PCIE_CRX_GTX_N3

G35

PCIE_CRX_GTX_N4

G32

PCIE_CRX_GTX_N5

F34

PCIE_CRX_GTX_N6

F31

PCIE_CRX_GTX_N7

D35

PCIE_CRX_GTX_N8

E33

PCIE_CRX_GTX_N9

C33

PCIE_CRX_GTX_N10

D32

PCIE_CRX_GTX_N11

B32

PCIE_CRX_GTX_N12

C31

PCIE_CRX_GTX_N13

B28

PCIE_CRX_GTX_N14

B30

PCIE_CRX_GTX_N15

A31

PCIE_CRX_GTX_P0

J35

PCIE_CRX_GTX_P1

H34

PCIE_CRX_GTX_P2

H33

PCIE_CRX_GTX_P3

F35

PCIE_CRX_GTX_P4

G33

PCIE_CRX_GTX_P5

E34

PCIE_CRX_GTX_P6

F32

PCIE_CRX_GTX_P7

D34

PCIE_CRX_GTX_P8

F33

PCIE_CRX_GTX_P9

B33

PCIE_CRX_GTX_P10

D31

PCIE_CRX_GTX_P11

A32

PCIE_CRX_GTX_P12

C30

PCIE_CRX_GTX_P13

A28

PCIE_CRX_GTX_P14

B29

PCIE_CRX_GTX_P15

A30

PCIE_CTX_GRX_C_N0

L33

PCIE_CTX_GRX_C_N1

M35

PCIE_CTX_GRX_C_N2

M33

PCIE_CTX_GRX_C_N3

M30

PCIE_CTX_GRX_C_N4

L31

PCIE_CTX_GRX_C_N5

K32

PCIE_CTX_GRX_C_N6

M29

PCIE_CTX_GRX_C_N7

J31

PCIE_CTX_GRX_C_N8

K29

PCIE_CTX_GRX_C_N9

H30

PCIE_CTX_GRX_C_N10

H29

PCIE_CTX_GRX_C_N11

F29

PCIE_CTX_GRX_C_N12

E28

PCIE_CTX_GRX_C_N13

D29

PCIE_CTX_GRX_C_N14

D27

PCIE_CTX_GRX_C_N15

C26

PCIE_CTX_GRX_C_P0

L34

PCIE_CTX_GRX_C_P1

M34

PCIE_CTX_GRX_C_P2

M32

PCIE_CTX_GRX_C_P3

L30

PCIE_CTX_GRX_C_P4

M31

PCIE_CTX_GRX_C_P5

K31

PCIE_CTX_GRX_C_P6

M28

PCIE_CTX_GRX_C_P7

H31

PCIE_CTX_GRX_C_P8

K28

PCIE_CTX_GRX_C_P9

G30

PCIE_CTX_GRX_C_P10

G29

PCIE_CTX_GRX_C_P11

F28

PCIE_CTX_GRX_C_P12

E27

PCIE_CTX_GRX_C_P13

D28

PCIE_CTX_GRX_C_P14

C27

PCIE_CTX_GRX_C_P15

C25

R44 49.9_0402 _1%

1 2

R45 750_ 0402_1%

1 2

PCIE_CRX_GTX_N[0..15] <24>

PCIE_CRX_GTX_P[0..15] <24>

C4 0.1U_0402_16V4ZSG@

1 2

C5 0.1U_0402_16V4ZSG@

1 2

C6 0.1U_0402_16V4ZSG@

1 2

C7 0.1U_0402_16V4ZSG@

1 2

C8 0.1U_0402_16V4ZSG@

1 2

C9 0.1U_0402_16V4ZSG@

1 2

C10 0.1U_0402_16V 4ZSG@

1 2

C11 0.1U_0402_16V 4ZSG@

1 2

C12 0.1U_0402_16V 4ZSG@

1 2

C13 0.1U_0402_16V 4ZSG@

1 2

C14 0.1U_0402_16V 4ZSG@

1 2

C15 0.1U_0402_16V 4ZSG@

1 2

C16 0.1U_0402_16V 4ZSG@

1 2

C17 0.1U_0402_16V 4ZSG@

1 2

C18 0.1U_0402_16V 4ZSG@

1 2

C19 0.1U_0402_16V 4ZSG@

1 2

C20 0.1U_0402_16V 4ZSG@

1 2

C21 0.1U_0402_16V 4ZSG@

1 2

C22 0.1U_0402_16V 4ZSG@

1 2

C23 0.1U_0402_16V 4ZSG@

1 2

C24 0.1U_0402_16V 4ZSG@

1 2

C25 0.1U_0402_16V 4ZSG@

1 2

C26 0.1U_0402_16V 4ZSG@

1 2

C27 0.1U_0402_16V 4ZSG@

1 2

C28 0.1U_0402_16V 4ZSG@

1 2

C29 0.1U_0402_16V 4ZSG@

1 2

C30 0.1U_0402_16V 4ZSG@

1 2

C31 0.1U_0402_16V 4ZSG@

1 2

C32 0.1U_0402_16V 4ZSG@

1 2

C33 0.1U_0402_16V 4ZSG@

1 2

C34 0.1U_0402_16V 4ZSG@

1 2

C35 0.1U_0402_16V 4ZSG@

1 2

3

Layout rule：trace
length < 0.5"

PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N8

PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N15

PCIE_CTX_GRX_P0

PCIE_CTX_GRX_P1

PCIE_CTX_GRX_P2

PCIE_CTX_GRX_P3

PCIE_CTX_GRX_P4

PCIE_CTX_GRX_P5

PCIE_CTX_GRX_P6

PCIE_CTX_GRX_P7

PCIE_CTX_GRX_P8

PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P15

+V_DDR_CPU_REF1

PCIE_CTX_GRX_N[0..15] <24>

PCIE_CTX_GRX_P[0..15] <24>

R50 0_04 02_5%@
R51 0_04 02_5%@

1 2
1 2

2

+V_DDR_CPU_REF0

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18

AP25
AL25
AL24
AL22

AJ33

AM30
AM28

AP31
AL32
AL30

AM31

AN29

AM32

AK32
AK31
AK28

AJ28
AN30
AN32

AJ32

AJ29

AJ30
AK30

AG9
M27

H17
G25
G17

AC9

L28

J17

E31
E30

H16

B19
A19

A20
B20

U9

T9

AB9

C1

A3

J29
J28

A34
A33

C35
B35

JCPU1E

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
SA_DIMM_VREF
SB_DIMM_VREF
RSVD11
RSVD12
RSVD13
RSVD14

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86

RSVD15
RSVD16

RSVD17
RSVD18

RSVD19
RSVD20

RSVD21
RSVD22

RSVD_NCTF_23
RSVD_NCTF_24

RSVD26
RSVD27

RSVD_NCTF_28
RSVD_NCTF_29

RSVD_NCTF_30
RSVD_NCTF_31

RSVD_NCTF_37

RSVD_NCTF_40
RSVD_NCTF_41

RSVD_NCTF_42
RSVD_NCTF_43

RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57

RSVD_TP_59
RSVD_TP_60

RESERVED

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

RSVD32
RSVD33

RSVD34
RSVD35

RSVD36

RSVD38
RSVD39

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53

RSVD58

KEY
RSVD62
RSVD63
RSVD64
RSVD65

VSS

AJ13
AJ12

AH25
AK26

AL26
AR2

AJ26
AJ27

AP1
AT2

AT3
AR1

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32

E15
F15
A2
D15
C15
AJ15
AH15

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

AP34

1

R48 0_04 02_5%@

1 2

R49 0_04 02_5%@

1 2

IC,AUB_CFD_rPGA,R1P0

CONN@

CFG Straps for PROCESSOR

CFG0

R52 3.01K_0402_1%@

1 2

PCI-Express Configuration Select

1: Single PEG

CFG0

A A

Not applicable for Clarksfield Processor

CFG3

0: Bifurcation enabled

R54 3.01K_0 402_1%

1 2

CFG3-PCI Expres s Static Lane R eversal

1: Normal Opera tion

CFG3

0: Lane Numbers Reversed

15 -> 0, 14 ->1 , .....

5

*

CFG4

R53 3.01K_0402_1%@

1 2

CFG4-Display Po rt Presence

1: Disabled; No Physical
Display Port

attached to Emb edded Display P ort
0: Enabled; An external

CFG4

Display Port

device is conne cted to the
Embedded Displa y Port

CFG7

R55 3.01K_0 402_1%@

Only temporary for early
CFD samples (rPGA/BGA)

Only for pre ES1 sample

1 2

4

**

CFG7

WW33：PD 3.01K on CFG7 for PCIE Jitter
WW41：don't staff

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

Auburndale(2/5)-DMI/PEG/FDI

Calpella DIS LA4743P

CRB 0.9 change to GND

7 52Friday, September 11, 2009

1

0.4

5

4

3

2

1

AG1

AG4
AG3

AH4

AM6
AN2

AM4
AM3

AN5

AN6
AN4
AN3

AN7

AR10
AT10

AC5

AC6

JCPU1D

W8

SB_CK[0]

W9

SB_CK#[0]

B5

SB_DQ[0]

A5

SB_DQ[1]

C3

SB_DQ[2]

B3

SB_DQ[3]

E4

SB_DQ[4]

A6

SB_DQ[5]

A4

SB_DQ[6]

C4

SB_DQ[7]

D1

SB_DQ[8]

D2

SB_DQ[9]

F2

SB_DQ[10]

F1

SB_DQ[11]

C2

SB_DQ[12]

F5

SB_DQ[13]

F3

SB_DQ[14]

G4

SB_DQ[15]

H6

SB_DQ[16]

G2

SB_DQ[17]

J6

SB_DQ[18]

J3

SB_DQ[19]

G1

SB_DQ[20]

G5

SB_DQ[21]

J2

SB_DQ[22]

J1

SB_DQ[23]

J5

SB_DQ[24]

K2

SB_DQ[25]

L3

SB_DQ[26]

M1

SB_DQ[27]

K5

SB_DQ[28]

K4

SB_DQ[29]

M4

SB_DQ[30]

N5

SB_DQ[31]

AF3

SB_DQ[32]
SB_DQ[33]

AJ3

SB_DQ[34]

AK1

SB_DQ[35]
SB_DQ[36]
SB_DQ[37]

AJ4

SB_DQ[38]
SB_DQ[39]

AK3

SB_DQ[40]

AK4

SB_DQ[41]
SB_DQ[42]
SB_DQ[43]

AK5

SB_DQ[44]

AK2

SB_DQ[45]
SB_DQ[46]
SB_DQ[47]

AP3

SB_DQ[48]
SB_DQ[49]

AT4

SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]

AT5

SB_DQ[54]

AT6

SB_DQ[55]
SB_DQ[56]

AP6

SB_DQ[57]

AP8

SB_DQ[58]

AT9

SB_DQ[59]

AT7

SB_DQ[60]

AP9

SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

AB1

SB_BS[0]

W5

SB_BS[1]

R7

SB_BS[2]

SB_CAS#

Y7

SB_RAS#
SB_WE#

DDR SYSTEM MEMORY - B

SB_CKE[0]

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DM[0]

SB_DM[1]

SB_DM[2]

SB_DM[3]

SB_DM[4]

SB_DM[5]

SB_DM[6]

SB_DM[7]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

M3

V7
V6
M2

AB8
AD6

AC7
AD1

D4
E1
H3
K1
AH1
AL2
AR4
AT8

D5
F4
J4
L4
AH2
AL4
AR5
AR8

C5
E3
H4
M5
AG2
AL5
AP5
AR7

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

M_CLK_DDR2 <18>
M_CLK_DDR#2 <18>
DDR_CKE2_DIMMB <18>

M_CLK_DDR3 <18>
M_CLK_DDR#3 <18>
DDR_CKE3_DIMMB <18>

DDR_CS2_DIMMB# <18>
DDR_CS3_DIMMB# <18>

M_ODT2 <18>
M_ODT3 <18>

DDR_B_DM[0..7] <18>

DDR_B_DQS#[0..7] <18>

DDR_B_DQS[0..7] <18>

DDR_B_MA[0..15] <18>

JCPU1C

D D

DDR_A_D[0..63]<17>

C C

B B

DDR_A_BS0<17>
DDR_A_BS1<17>
DDR_A_BS2<17>

DDR_A_CAS#<1 7>
DDR_A_RAS#<1 7>
DDR_A_WE#<17>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

C10

D10

H10

G10

AH5
AF5
AK6
AK7
AF6
AG5

AJ10

AL10

AK12

AK8

AK11

AN8
AM10
AR11

AL11

AM9

AN9

AT11

AP12
AM12
AN12
AM13

AT14

AT12

AL13
AR14

AP14

AC3
AB2

AE1
AB3
AE9

A10

B10

E10

F10

AJ7
AJ6

AJ9

AL7

AL8

C7
A7

A8
D8

E6
F7
E9
B7
E7
C6

G8

K7

G7

J10

M6
M8

K8
N8
P9

U7

J8

J7

L7

L9
L6

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AA6
AA7
P7

Y6
Y5
P6

AE2
AE8

AD8
AF9

B9
D7
H7
M7
AG6
AM7
AN10
AN13

C9
F8
J9
N9
AH7
AK9
AP11
AT13

C8
F9
H9
M9
AH8
AK10
AN11
AR13

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

M_CLK_DDR0 <17>
M_CLK_DDR#0 <17>
DDR_CKE0_DIMMA <17>

M_CLK_DDR1 <17>
M_CLK_DDR#1 <17>
DDR_CKE1_DIMMA <17>

DDR_CS0_DIMMA# <17>
DDR_CS1_DIMMA# <17>

M_ODT0 <17>
M_ODT1 <17>

DDR_A_DM[0..7] <17>

DDR_A_DQS#[0..7] <17>

DDR_A_DQS[0..7] <17>

DDR_A_MA[0..15] <17>

DDR_B_D[0..63]<18>

DDR_B_BS0<18>
DDR_B_BS1<18>
DDR_B_BS2<18>

DDR_B_CAS#<1 8>
DDR_B_RAS#<1 8>
DDR_B_WE#<18>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

IC,AUB_CFD_rPGA,R1P0

CONN@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

IC,AUB_CFD_rPGA,R1P0

CONN@

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(2/6)-DDR3 A/B CH

Calpella DIS LA4743P

1

8 52Friday, September 11, 2009

0.4

5

+VCC_CORE

JCPU1F

D D

C C

B B

A A

48A 15A18A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

IC,AUB_CFD_rPGA,R1P0

CONN@

CPU CORE SUPPLY

5

1.1V RAIL POWER

POWER

PROC_DPRSLPVR

CPU VIDS

VTT_SELECT

VCC_SENSE
VSS_SENSE

VTT_SENSE

VSS_SENSE_VTT

SENSE LINES

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8

VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32

VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

PSI#

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

ISENSE

AH14
AH12
AH11
AH10

1
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

AN33

AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

G15

C40

2

10U_0805_6.3V6M

1

C48

2

10U_0805_6.3V6M

1

C67

2

+VTT_43
+VTT_44

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
PM_DPRSLPVR_R

H_VTTVID1 = Low, 1.1V(Clarksfield)

H_VTTVID1 = High, 1.05V(Arrandale)

AN35

VCCSENSE_R

AJ34

VSSSENSE_R

AJ35

B15

VSS_SENSE_VTT

A15

Near Processor

VCCSENSE

VSSSENSE

R61 100_ 0402_1%

R62 100_ 0402_1%

4

1

1

C41

2

10U_0805_6.3V6M

1

C49

2

@

10U_0805_6.3V6M

1

2

22U_0805_6.3V6M

+VTT_44

+VTT_43

to power

R58 0_0402_5%

to power

R59 0_0402_5%

1 2

R60 0_0402_5%

1 2

R203 0_0402_ 5%

1 2

1 2

1

C42

2

2

10U_0805_6.3V6M

1

1

C50

2

2

@

10U_0805_6.3V6M

+VCCP

C68

22U_0805_6.3V6M

R56 0_06 03_5%

1 2

R57 0_06 03_5%

1 2

H_PSI# <47>

H_VID[0..6] <47>

to power

1 2

VTT_SELECT <45>

IMVP_IMON <47>

1 2

+VCC_CORE

4

C43

C51

3

+GFX_CORE

22U_0805_6.3V6M

22U_0805_6.3V6M

C988

+VCCP

10U_0805_6.3V6M

1

C52

2

10U_0805_6.3V6M

1

2

+VCCP

10U_0805_6.3V6M

1

1

C63

C62

C61

22U_0805_6.3V6M

2

+VCCP

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C987

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C993

C991

1

1

@

@

2

330U_D2_2VY_R7M

C995

1

1

+

+

2

2

+VCCP

1

2

@

2

330U_D2_2VY_R7M

C996

+VCCP

1

C73

C74

2

22U_0805_6.3V6M

22U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

C990

C989

1

1

2

2

22U_0805_6.3V6M

C994

1

2

1

1

C69

2

2

22U_0805_6.3V6M

1

1

C75

2

2

22U_0805_6.3V6M

CPU

H_DPRSLPVR <47>

to power

J7

1 2

VCCSENSE
VSSSENSE

VCCSENSE <47>
VSSSENSE <47>

VTT_SENSE <45>

+1.5V +1.5VS_CPU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

PAD-OPEN 4x4m

C1299 0.1U_0402_10 V6K

1 2

C1301 0.1U_0402_10 V6K

1 2

C1304 0.1U_0402_10 V6K

1 2

C1305 0.1U_0402_10 V6K

1 2

2008/03/13 2009/05/11

JCPU1G

AT21

VAXG1

AT19

VAXG2

AT18

VAXG3

AT16

VAXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

C70

22U_0805_6.3V6M

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25
H27
G28
G27
G26

22U_0805_6.3V6M

F26
E26
E25

+1.5VS_CPU+1.5V

VTT1_51
VTT1_52
VTT1_53
VTT1_54
VTT1_55
VTT1_56
VTT1_57
VTT1_58

IC,AUB_CFD_rPGA,R1P0

CONN@

C76

Compal Secret Data

B+

12

SUSP<40,46>

Deciphered Date

2

VCC_AXG_SENSE

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

GFX_IMON

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

VTT0_59
VTT0_60
VTT0_61
VTT0_62

VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68

VCCPLL1
VCCPLL2
VCCPLL3

U53

2N7002DW-7-F_SOT363-6

AR22

VSS_AXG_SENSE

AT22

GFXVR_VID_0

AM22

GFXVR_VID_1

AP22

GFXVR_VID_2

AN22

GFXVR_VID_3

AP23

GFXVR_VID_4

AM23

GFXVR_VID_5

AP24

GFXVR_VID_6

AN24

R43 4.7K_04 02_5%

GFXVR_EN

AR25

GFXVR_DPRSLPVR

AT25

GFXVR_IMON

AM24

R128 1K_04 02_5%@

AJ1
AF1
AE7

1
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

P10
N10
L10
K10

J22
J20
J18
H21
H20
H19

L26
L27
M26

4

12

1

2

C56

2

1

+

C64

2

1

C71

2

1

C77

2

1

1

C79

2

2

1U_0603_10V4Z

1
2
35

1

2

R1069

1K_0402_5%

C1306

0.1U_0402_25V4K

Title

Size Document Number Rev

Custom

Calpella DIS LA4743P

Date: Sheet of

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

GRAPHICS

GFX_VR_EN

GFX_DPRSLPVR

GRAPHICS VIDs

3A

FDI PEG & DMI

POWER

DDR3 - 1.5V RAILS

1.1V1.8V

0.6A

+1.5V to +1.5VS_CPU Transfer

+1.5V +1.5VS_CPU

R1068

330K_0402_5%

RUNON_1.5VS_CPU

SUSP

2

SI7326DN-T1-E3_PAK1212-8

1

C1300

2

10U_0805_10V4Z

61

Q88A

2

1

VCC_AXG_SENSE <44>
VSS_AXG_SENSE <44>

GFXVR_VID_0 <44>
GFXVR_VID_1 <44>
GFXVR_VID_2 <44>
GFXVR_VID_3 <44>
GFXVR_VID_4 <44>
GFXVR_VID_5 <44>

1 2

1U_0603_10V4Z

330U_D2_2VY_R7M

10U_0805_6.3V6M

22U_0805_6.3V6M

GFXVR_VID_6 <44>

GFXVR_EN <44>
GFXVR_DPRSLPVR < 44>

1

C57

2

1

C65

2

1

C72

2

1

C78

2

1

C80

2

1U_0603_10V4Z

C1302

0.1U_0402_16V4Z

GFXVR_IMON <44>

12

1

1

C58

2

2

1U_0603_10V4Z

1U_0603_10V4Z

1

C66

2

22U_0805_6.3V6M

22U_0805_6.3V6M

+VCCP

10U_0805_6.3V6M

+VCCP

22U_0805_6.3V6M

1

C81

C82

2

22U_0805_6.3V6M

2.2U_0603_6.3V4Z

1

C1303

2

10U_0805_10V4Z

PV：change discharge
resistor to 220 follow
checkist

1

C60

C59

2

1U_0603_10V4Z

1U_0603_10V4Z

C83

SUSP

4.7U_0603_6.3V6K

R1067

220_0402_5%

+1.8VS

Q88B

5

1

2

Compal Electronics, Inc.

Auburndale(4/5)-PWR

1

+1.5VS_CPU

+1.5VS_CPU

12

3

4

2N7002DW-7-F_SOT363-6

0.4

9 52Friday, September 11, 2009

5

4

3

2

1

JCPU1H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

D D

C C

B B

AR17
AR15
AR12

AR9
AR6

AR3
AP20
AP17
AP13
AP10

AP7

AP4

AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11

AM8

AM5

AM2

AL34
AL31
AL23
AL20
AL17
AL12

AK29
AK27
AK25
AK20
AK17

AJ31
AJ23
AJ20
AJ17
AJ14
AJ11

AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13

AH9

AH6

AH3
AG10

AF8

AF4

AF2
AE35

VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42

AL9

VSS43

AL6

VSS44

AL3

VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56

AJ8

VSS57

AJ5

VSS58

AJ2

VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

JCPU1I

K27

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

VSS

NCTF

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

AT35
AT1
AR34
B34
B2
B1
A35

+VCC_CORE

1

C982

@

2

VSS_NCTF1_R
VSS_NCTF2_R

VSS_NCTF3_R
VSS_NCTF4_R
VSS_NCTF5_R

VSS_NCTF6_R
VSS_NCTF7_R

CPU CORE

1

1

2

1

2

1

2

47P_0402_50V8J

C86

C84

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C115

C114

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C95

C103

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

2

1

2

1

2

C96

C91

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C117

C116

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C105

C106

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

2

1

2

1

2

C98

C97

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C87

C85

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C118

C119

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

2

1

2

1

2

C100

C99

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C88

C89

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C120

C121

2

10U_0805_6.3V6M

10U_0805_6.3V6M

SI：Change CPU core decopuling capacitor for power Transient

1

1

2

1

2

1

+

2

C102

C101

2

22U_0805_6.3V6M

1

C90

C92

2

10U_0805_6.3V6M

1

+

C108

C109

2

470U_D2_2VM_R4.5M

470uF 4.5mohm

1

1

C107

2

22U_0805_6.3V6M

1

C94

2

10U_0805_6.3V6M

1

+

C111

2

470U_D2_2VM_R4.5M

Inside cavity

between
Inductor and
socket

1

1

+

+

C1287

2

C1288

2

@

@

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

C104

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C93

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

+

C110

2

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

IC,AUB_CFD_rPGA,R1P0

CONN@

A A

5

IC,AUB_CFD_rPGA,R1P0

CONN@

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

Custom

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Auburndale(5/5)-GND/Bypass

Calpella DIS LA4743P

10 52Friday, September 11, 2009

1

0.4

5

ICH_RTCX1

R63 10M_0402_5%

1 2

1

1

D D

2

C C

+3VS

R656 10K_0402_5%

R657 10K_0402_5%

B B

C122

18P_0402_50V8J

C53 22P_0402_50V8J@

C54 22P_0402_50V8J@

1 2

1 2

2

OSC4OSC

NC3NC

1 2

1 2

ICH_RTCX2

1

C123

2

Y1

18P_0402_50V8J

32.768KHZ_12.5PF_Q13MC14610002

SPI_SB_CS#

SPI_SO_R

+RTCVCC

R65 1M_0402_5%

R66 330K_0402_5%

+RTCVCC

R69 20K_0402_1%

1 2

R70 20K_0402_1%

1 2

HDA_BITCLK_CODEC<34>

HDA_SYNC_CODEC<34>

HDA_RST#_CODEC<34,38>

HDA_SDIN0<34>

HDA_BITCLK_CODEC

HDA_SDOUT_CODEC

HDA_SDOUT_CODEC<34>

GPIO33 can not pull down
(manufacturing environments)

SPI_CLK_PCH<37>

SPI_SB_CS#<37>

SPI_SI<37>

SPI_SO_R<37>

1 2

1 2

1

C124

1U_0603_10V4Z

1U_0603_10V4Z

2

1

C125

2

R73 33_0402_5%

1 2

R75 33_0402_5%

1 2

1 2

R78 33_0402_5%

R82 33_0402_5%

1 2

SPI_CLK_PCH

SPI_SB_CS#

SPI_SI

SPI_SO_R

SM_INTRUDER#

PCH_INTVRMEN

INTVRMEN
H：Integrated VRM enable
L：Integrated VRM disable

12

CLRP1

SHORT PADS

12

CLRP2

SHORT PADS

SB_SPKR<34>

R654 15_0402_5%

1 2

R655 15_0402_5%

1 2

ICH_RTCX1
ICH_RTCX2

ICH_RTCRST#

ICH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

SB_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDOUT

ME_EN#

T16PAD

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_RST#

4

*

U1A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST# / GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IBEXPEAK-M_FCBGA1071

+3VS

R64 10K_0402_5%

1 2

R67 1K_0402_5%@

1 2

LOW=Default
HIGH=No Reboot

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

FWH4 / LFRAME#

LDRQ1# / GPIO23

LPC

RTCIHDA

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

SPI JTAG

LDRQ0#

SERIRQ

SIRQ

SB_SPKR

*

D33
B33
C32
A32

C34

LDRQ0#

A34

LDRQ1#

F34

SIRQ

AB9

AK7
AK6

SATA_TXN0_C

AK11

SATA_TXP0_C

AK9

AH6
AH5

SATA_TXN4_C

AH9

SATA_TXP4_C

AH8

AF11
AF9
AF7
AF6

SATA2、SATA3 don't

AH3

support on HM55

AH1
AF3
AF1

AD9
AD8

SATA_TXN2_C

AD6

SATA_TXP2_C

AD5

AD3
AD1
AB3
AB1

AF16

R89 37.4_0402_1%

AF15

1 2

R91 10K_0402_1%

1 2

T3

GPIO21

Y9

GPIO19

V1

3

LPC_AD0 <31,38>
LPC_AD1 <31,38>
LPC_AD2 <31,38>
LPC_AD3 <31,38>

LPC_FRAME# <31,38>

T13 PAD
T14 PAD

SIRQ <38>

C126 0.01U_0402_50V7K

1 2

C127 0.01U_0402_50V7K

1 2

C130 0.01U_0402_50V7K

1 2

C131 0.01U_0402_50V7K

1 2

C128 0.01U_0402_50V7K

1 2

C129 0.01U_0402_50V7K

1 2

SATA_LED# <39>

+3VS

+1.05VS

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0
SATA_TXP0

SATA_RXN4_C
SATA_RXP4_C
SATA_TXN4
SATA_TXP4

SATA_RXN2_C
SATA_RXP2_C
SATA_TXN2
SATA_TXP2

SATA_RXN0_C <30>
SATA_RXP0_C <30>

SATA_TXN0 <30>
SATA_TXP0 <30>

SATA_RXN4_C <30>
SATA_RXP4_C <30>

SATA_TXN4 <30>
SATA_TXP4 <30>

SATA_RXN2_C <36>
SATA_RXP2_C <36>

SATA_TXN2 <36>
SATA_TXP2 <36>

2

12

R86

@

200_0402_5%

12

R684

@

100_0402_1%

HDD

ODD

E SATA

1

+3VALW+3VALW +3VALW +3VALW

12

R84

@

200_0402_5%

PCH_JTAG_TMS PCH_JTAG_RST#PCH_JTAG_TDO PCH_JTAG_TDI

12

R683

@

100_0402_1%

R85
20K_0402_5%

1 2

R685
10K_0402_1%

1 2

@

1 2

12

@

R87
20K_0402_5%

R88
10K_0402_5%

HDA_SDO

HDA_SYNC

This signal has a weak internal pull down.

H=>On Die PLL is supplied by 1.5V
L=>On Die PLL is supplied by 1.8V

*

+3VS

12

R670

100K_0402_5%

ME_EN<38>

A A

R1086

100K_0402_5%

ME_EN#

13

D

Q89

2

G

12

2N7002_SOT23

S

PV：Add ME_EN

5

HDA_DOCK_EN#

ME debug mode , this signal has a weak internal PU

H=>security measures defined in the Flash

*

Descriptor will be in effect (default)

L=>Flash Descriptor Security will be overridden

SPI_MOSI

This signal has a weak internal pull down.

Disable iTPM=No Stuff

*

Enable iTPM=Stuff

iTPM ENABLE/DISABLE

+3VS

R68 1K_0402_5%@

1 2

SPI_SI

SI：Reserve GPIO19、21 PD for LPM e nable power sav ing

4

This signal has a weak internal pull down.
This signal can't PU

Disable iTPM=No Stuff

*

Enable iTPM=Stuff

W=20milsW=20mils

1

C132

2.2U_0603_6.3V4Z

2

Place near IBEX-M

GPIO21

GPIO19

GPIO21

GPIO19

R92 10K_0402_5%

R93 10K_0402_5%

R230 10K_0402_5%@

R232 10K_0402_5%@

12

12

1 2

1 2

+3VS

3

BATT1

@

BATT1.1+3VL+RTCVCC

D3

2

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DAN202U_SC70

R94 1K_0402_5%

1 2

3

W=20mils

2008/03/13 2009/05/11

CR2032 RTC BATTERY

JBATT1

1

1

2

2

3

GND

4

GND

ACES_85205-02001

CONN@

Compal Secret Data

Deciphered Date

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TCK

PCH_JTAG_RST#

2

1 2

R90 51_0402_5%

RefDesPCH Pin

R86

R684

R84

R683

R685

R90

R87

R88

PCH_JTAG_TCK

PCH JTAG Enable PCH JTAG Disable

ES1 ES1ES2 ES2

200ohm

No Install

No Install

200ohm

100ohm

200ohm

No Install

100ohm 100ohm

200ohm

200ohm

100ohm 100ohm

51ohm 51ohm 51ohm

20Kohm 20Kohm

10Kohm 10Kohm

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(1/6)-HDA/JTAG/SATA

Calpella DIS LA4743P

No Install

No Install

No Install

20Kohm

10Kohm

No Install

1

No Install

No Install

No Install

No Install

No InstallR85

No Install

51ohm

No Install

No InstallNo Install

11 52Friday, September 11, 2009

0.4

5

D D

PCIE_RXN1<31>

1 2

1 2

1 2

1 2

1 2

CLK_PCIE_WWAN#<31>
CLK_PCIE_WWAN<31>

CLKREQ_WWAN#<31>

CLK_PCIE_WLAN#<31>
CLK_PCIE_WLAN<31>

CLKREQ_WLAN#<31>

CLK_PCIE_LAN#<32>
CLK_PCIE_LAN<32>

CLKREQ_LAN#<32>

CLK_PCIE_EXP#<31>
CLK_PCIE_EXP<31>

CLKREQ_EXP#<31>

CLK_PCIE_COMBO#<33>
CLK_PCIE_COMBO<33>

CLKREQ_COMBO#<33>

PCIE_RXP1<31>
PCIE_TXN1<31>
PCIE_TXP1<31>

PCIE_RXN2<31>
PCIE_RXP2<31>
PCIE_TXN2<31>
PCIE_TXP2<31>

PCIE_RXN3<32>
PCIE_RXP3<32>
PCIE_TXN3<32>
PCIE_TXP3<32>

PCIE_RXN4<31>
PCIE_RXP4<31>
PCIE_TXN4<31>
PCIE_TXP4<31>

PCIE_RXN5<33>
PCIE_RXP5<33>
PCIE_TXN5<33>
PCIE_TXP5<33>

CLKREQ_WWAN#_R

CLKREQ_WLAN#

CLKREQ_LAN#

CLKREQ_EXP#_R

PCIECLKREQ4#

WWAN

WLAN

LAN

New Card

RTL 8401

C C

R405 10K_0402_5%

+3VALW

R411 10K_0402_5%

+3VS

R677 10K_0402_5%

+3VS

R415 10K_0402_5%

+3VALW

R503 10K_0402_5%

+3VALW

OK

WWAN

OK

WLAN

OK

LAN

B B

OK

New Card

Combo

A A

C133 0.1U_0402_16V4Z@
C134 0.1U_0402_16V4Z@

C135 0.1U_0402_16V4Z
C136 0.1U_0402_16V4Z

C137 0.1U_0402_16V4Z8111@
C138 0.1U_0402_16V4Z8111@

C139 0.1U_0402_16V4Z
C140 0.1U_0402_16V4Z

C1277 0.1U_0402_16V4Z8401@
C1278 0.1U_0402_16V4Z8401@

R107 0_0402_5%@
R108 0_0402_5%@

R80 100_0402_5%@

R109 0_0402_5%
R110 0_0402_5%

R111 0_0402_5%
R112 0_0402_5%

R114 0_0402_5%
R115 0_0402_5%

R83 100_0402_5%

R501 0_0402_5%
R502 0_0402_5%

R756 100_0402_5%

R757 10K_0402_5%

+3VALW

R606 10K_0402_5%

+3VALW

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

PCIE7、PCIE8 don't
support on HM55

1 2
1 2

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

1 2
1 2

1 2

1 2

1 2

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

PCIE_RXN3
PCIE_RXP3
GLAN_C_TXN
GLAN_C_TXP

PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4

PCIE_RXN5
PCIE_RXP5
PCIE_C_TXN5
PCIE_C_TXP5

CLK_PCIE_WWAN#_R
CLK_PCIE_WWAN_R

CLKREQ_WWAN#_R

CLK_PCIE_WLAN#_R
CLK_PCIE_WLAN_R

CLK_PCIE_LAN#_R
CLK_PCIE_LAN_R

CLK_PCIE_EXP#_R
CLK_PCIE_EXP_R

CLKREQ_EXP#_R

CLK_PCIE_COMBO#_R
CLK_PCIE_COMBO_R

PCIECLKREQ4#

PCIECLKREQ5#

PEG_B_CLKRQ#

4

U1B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

T59PAD
T60PAD

T61PAD
T62PAD

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IBEXPEAK-M_FCBGA1071

PCI-E*

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML0DATA

SML1ALERT# / GPIO74

SMBus

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

Controller

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

Clock Flex

CL_DATA1

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_BCLK_N
CLKIN_BCLK_P

CLKIN_DOT_96N
CLKIN_DOT_96P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

SMBCLK

SMBDATA

SML0CLK

CL_CLK1

CL_RST1#

3

EC_LID_OUT#

R95 10K_0402_5%

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML0ALERT#

SML1ALERT#

SML1CLK

SML1DATA

EC_LID_OUT#

B9

SMBCLK

H14

SMBDATA

C8

SML0ALERT#

J14

SML0CLK

C6

SML0DATA

G8

SML1ALERT#

M14

SML1CLK

E10

SML1DATA

G12

T13

T11

T9

SI：CLKREQ PD

PEG_CLKREQ#

H1

L_CLK_PCIE_VGA#

AD43

L_CLK_PCIE_VGA

AD45

AN4
AN2

CLK_DP#

AT1

CLK_DP

AT3

AW24
BA24

AP3
AP1

F18
E18

AH13
AH12

P41

J42

XTAL25_IN

AH51

XTAL25_OUT

AH53

R116 90.9_0402_1%

AF38

T45

P43

T42

R1021 22_0402_5%

1 2

N50

SI：Change 48M form CLKOUTFLEX2 to 3

1 2

R96 2.2K_0402_5%

1 2

R97 2.2K_0402_5%

1 2

R98 2.2K_0402_5%

1 2

R99 2.2K_0402_5%

1 2

R100 10K_0402_5%

1 2

R101 10K_0402_5%

1 2

R103 2.2K_0402_5%

1 2

R104 2.2K_0402_5%

1 2

EC_LID_OUT# <38>

SMBCLK <31>

SMBDATA <31>

R215

R231

1 2

0_0402_5%

0_0402_5%

DTS , read from EC

R102 10K_0402_5%

1 2

R604 0_0402_5%

1 2

R605 0_0402_5%

1 2

CLK_EXP# <6>
CLK_EXP <6>

T71 PAD
T72 PAD

CLK_DMI# <19>
CLK_DMI <19>

CLK_BUF_BCLK# <19>
CLK_BUF_BCLK <19>

CLK_BUF_DOT96# <19>
CLK_BUF_DOT96 <19>

CLK_BUF_CKSSCD# <19>
CLK_BUF_CKSSCD <19>

CLK_14M_PCH <19>

CLK_PCI_FB <14>

CLK_48M_CR <33>

+3VALW

WLAN、WWAN、New card

For Intel LAN only

SMB_EC_CK2 <38>

SMB_EC_DA2 <38>

CLK_PCIE_VGA# <24>

CLK_PCIE_VGA <24>

OK

OK

OK

OK

OK

OK

OK

+1.05VS

PCH

2

+3VS

5

Q1B

3

2N7002DW-7-F_SOT363-6

SMB_EC_DA2

SMB_EC_CK2

2N7002DW-7-F_SOT363-6

OK

PV：Delete 25M crys tal and change C142 to 0 ohm

+3VS

2

Q1A

6 1

2N7002DW-7-F_SOT363-6

4

+3VS_VGA +3VS_VGA

SG@

Q4A

6 1

SG@

5

Q4B

2N7002DW-7-F_SOT363-6

3

4

XTAL25_IN

XTAL25_OUT

+3VS

R105

2.2K_0402_5%

2

THERM_DAT_GPU

THERM_CLK_GPU

R113 1M_0402_5%UMA@

1 2

25MHZ_20P_1BG25000CK1A

1

C141

2

UMA@

Y2

1 2

UMA@

18P_0402_50V8J

1

R106

2.2K_0402_5%

SMB_DATA_S3SMBDATA

SMB_CLK_S3SMBCLK

SMB_DATA_S3 <17,18,19,30>

XDP、SODIMM、Clock gen、G sensor

SMB_CLK_S3 <17,18,19,30>

THERM_DAT_GPU <26>

THERM_CLK_GPU <26>

SG@

R1081
0_0402_5%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(2/6)-PCI-E/SMBUS/CLK

Calpella DIS LA4743P

1

12 52Friday, September 11, 2009

0.4

5

<43>

DMI_CTX_PRX_N0<7>
DMI_CTX_PRX_N1<7>
DMI_CTX_PRX_N2<7>
DMI_CTX_PRX_N3<7>

DMI_CTX_PRX_P0<7>
DMI_CTX_PRX_P1<7>
DMI_CTX_PRX_P2<7>

D D

Checklist0.8：MEPWROK
can be connect to
PWROK if iAMT disable

XDP_DBRESET#<6>

PM_PWROK<38>

M_PWROK<38>

C C

PM_DRAM_PWRGD<6>

R_EC_RSMRST#

EC_RSMRST#<38>

PM_PWRBTN#_R<6>

PV：Add SUS_PWR_DN_ ACK
high during col d reset

B B

DMI_CTX_PRX_P3<7>

DMI_CRX_PTX_N0<7>
DMI_CRX_PTX_N1<7>
DMI_CRX_PTX_N2<7>
DMI_CRX_PTX_N3<7>

DMI_CRX_PTX_P0<7>
DMI_CRX_PTX_P1<7>
DMI_CRX_PTX_P2<7>
DMI_CRX_PTX_P3<7>

+1.05VS

R118 49.9_0402_1%

1 2

4mil width and place
within 500mil of the PCH

R119 0_0402_5%

R365 0_0402_5%

VGATE<19,47>

R120 10K_0402_5%

PWRBTN_OUT#<38>

PM_PWROK PM_RSMRST#

CH751H-40PT_SOD323-2

SYS_RST#

PM_CLKRUN#

LOW_BAT#

PM_RI#

ICH_PCIE_WAKE#

EC_ACIN

SUS_PWR_ACK

1 2

R373 0_0402_5%@

1 2

12

R121 0_0402_5%
R379 0_0402_5%@

R123 100_0402_5%

1 2

R124 10K_0402_5%

SUS_PWR_ACK<38>

EC_ACIN<26,38>

D37

2 1

R133 10K_0402_5%@

R129 8.2K_0402_5%

R134 8.2K_0402_5%

R136 10K_0402_5%

R137 1K_0402_5%

R138 8.2K_0402_5%

R151 10K_0402_5%

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_IRCOMP

1 2

1 2
1 2

R122 10K_0402_5%

1 2

PM_DRAM_PWRGD

12

R125 0_0402_5%

1 2

1 2

1 2

1 2

1 2

1 2

SYS_RST#

PM_RSMRST#

SUS_PWR_ACK

EC_ACIN

LOW_BAT#

PM_RI#

+3VALW

12

12

U1C

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IBEXPEAK-M_FCBGA1071

+3VS

Check PM_SLP_LAN#

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

4

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

BJ14

BF13

BH13

BJ12

BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

ICH_PCIE_WAKE#

PM_CLKRUN#

PM_SUS_STAT#

SUS_CLK

Can be left NC when IAMT is
not support on the platfrom

If not using integrated
LAN,signal may be left as NC.

FDI_CTX_PRX_N0 <7>
FDI_CTX_PRX_N1 <7>
FDI_CTX_PRX_N2 <7>
FDI_CTX_PRX_N3 <7>
FDI_CTX_PRX_N4 <7>
FDI_CTX_PRX_N5 <7>
FDI_CTX_PRX_N6 <7>
FDI_CTX_PRX_N7 <7>

FDI_CTX_PRX_P0 <7>
FDI_CTX_PRX_P1 <7>
FDI_CTX_PRX_P2 <7>
FDI_CTX_PRX_P3 <7>
FDI_CTX_PRX_P4 <7>
FDI_CTX_PRX_P5 <7>
FDI_CTX_PRX_P6 <7>
FDI_CTX_PRX_P7 <7>

FDI_INT <7>

FDI_FSYNC0 <7>

FDI_FSYNC1 <7>

FDI_LSYNC0 <7>

FDI_LSYNC1 <7>

ICH_PCIE_WAKE# <31,32,33>

T17

T18

SLP_S5# <38>

SLP_S4# <38>

SLP_S3# <38>

H_PM_SYNC <6>

3

R770

IGPU_BKLT_EN

1 2

100K_0402_5%

IGPU_BKLT_EN<22>

Close PCH and mini space 20mil

I_CRT_HSYNC<22>
I_CRT_VSYNC<22>

CRB0.9 change to 0 ohm

EDID_CLK and EDID_DATA single
end and keep 30 mil with other
LVDS signal avoid noise

IGPU_BKLT_EN
I_ENAVDD

DPST_PWM

1 2

R771 10K_0402_5%

1 2

R772 10K_0402_5%

R773 2.37K_0402_1%

1 2

T69PAD

I_BLUE
I_GREEN
I_RED

R774

1 2
1 2

R775 0_0402_5%

DPST_PWM<22>

+3VS

I_ENAVDD<21>

I_EDID_CLK<22>
I_EDID_DATA<22>

I_LVDS_ACLK-<22>
I_LVDS_ACLK+<22>

I_LVDS_A0-<22>
I_LVDS_A1-<22>
I_LVDS_A2-<22>

I_LVDS_A0+<22>
I_LVDS_A1+<22>
I_LVDS_A2+<22>

I_BLUE<22>
I_GREEN<22>
I_RED<22>

I_CRT_DDC_CLK<20>
I_CRT_DDC_DATA<20>

CRB0.9 change to 1K_0402_0.5%

I_BLUE

I_GREEN

I_RED

Place the 3 resistors close to IBEX

1 2

R776 150_0402_1%

1 2

R777 150_0402_1%

1 2

R778 150_0402_1%

0_0402_5%

HSYNC
VSYNC

12

R126

1K_0402_0.5%

U1D

T48

L_BKLTEN

T47

L_VDD_EN

Y48

L_BKLTCTL

AB48

L_DDC_CLK

Y45

L_DDC_DATA

AB46

L_CTRL_CLK

V48

L_CTRL_DATA

AP39

LVD_IBG

AP41

LVD_VBG

AT43

LVD_VREFH

AT42

LVD_VREFL

AV53

LVDSA_CLK#

AV51

LVDSA_CLK

BB47

LVDSA_DATA#0

BA52

LVDSA_DATA#1

AY48

LVDSA_DATA#2

AV47

LVDSA_DATA#3

BB48

LVDSA_DATA0

BA50

LVDSA_DATA1

AY49

LVDSA_DATA2

AV48

LVDSA_DATA3

AP48

LVDSB_CLK#

AP47

LVDSB_CLK

AY53

LVDSB_DATA#0

AT49

LVDSB_DATA#1

AU52

LVDSB_DATA#2

AT53

LVDSB_DATA#3

AY51

LVDSB_DATA0

AT48

LVDSB_DATA1

AU50

LVDSB_DATA2

AT51

LVDSB_DATA3

AA52

CRT_BLUE

AB53

CRT_GREEN

AD53

CRT_RED

V51

CRT_DDC_CLK

V53

CRT_DDC_DATA

Y53

CRT_HSYNC

Y51

CRT_VSYNC

AD48

DAC_IREF

AB51

CRT_IRTN

IBEXPEAK-M_FCBGA1071

2

SDVO_INTN
SDVO_INTP

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BJ46
BG46

BJ48
BG48

BF45
BH45

T51
T53

BG44
BJ44
AU38

BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38

Y49
AB49

BE44
BD44
AV40

BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

U50
U52

BC46
BD46
AT38

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN

SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

1

HDMID_CTRLCLK
HDMID_CTRLDATA

TMDS_B_HPD#

PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3

HDMID_CTRLCLK <23>
HDMID_CTRLDATA <23>

TMDS_B_HPD# <23>

C1290 0.1U_0402_16V7KUMA@

12

C1291 0.1U_0402_16V7KUMA@

12

C1292 0.1U_0402_16V7KUMA@

12

C1293 0.1U_0402_16V7KUMA@

12

C1294 0.1U_0402_16V7KUMA@

12

C1295 0.1U_0402_16V7KUMA@

12

C1296 0.1U_0402_16V7KUMA@

12

C1297 0.1U_0402_16V7KUMA@

12

SI：HDMI data 0 and data 2 reverse

SDVO

Display Port B

Display Port C

TMDSD_DATA2# <23>
TMDSD_DATA2 <23>
TMDSD_DATA1# <23>
TMDSD_DATA1 <23>
TMDSD_DATA0# <23>
TMDSD_DATA0 <23>
TMDSD_CLK# <23>
TMDSD_CLK <23>

Display Port D

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(3/6)-DMI/GPIO/LVDS

Calpella DIS LA4743P

1

13 52Friday, September 11, 2009

0.4

5

PCI_DEVSEL#
PCI_SERR#
PCI_REQ0#
PCI_PIRQB#

PCI_REQ1#
PCI_FRAME#
PCI_TRDY#
PCI_PIRQH#

D D

PCI_REQ3#
PCI_PIRQF#
PCI_PERR#
PCI_LOCK#

PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQG#
PCI_PIRQC#

PCI_PIRQE#
PCI_STOP#
PCI_IRDY#

DGPU_SELECT#

C C

RP3

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP4

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP5

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP6

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP7

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

ACCEL_INT<30>

GNT2

Default-Internal pull up

Low=Configures DMI for ESI
compatible operation(for
servers only.Not for
mobile/desktops)

B B

CLK_DEBUG_PORT_1<31>

A A

PCI_GNT3#

R183 1K_0402_5%@

A16 swap overide Strap/Top-Block
Swap Override jumper

PCI_GNT3#

+3VS

+3VS

DGPU_SELECT#<22>

PCI_SERR#<38>

PCI_RST#<38>

DGPU_PWM_SELECT#

R150

0_0402_5%

T70 PAD

ACCEL_INT

*

PCI_PME#<38>

PLT_RST#<6,24,31,32,33>

R_CLK_PCI_FB
R_CLK_PCI_EC

R_CLK_DEBUG_PORT_1

CLK_PCI_FB<12>
CLK_PCI_EC<38>

1 2

Low=A16 swap
override/Top-Block
Swap Override enabled
High=Default

5

R158 22_0402_5%
R160 22_0402_5%

R162 22_0402_5%

*

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCI_REQ0#
PCI_REQ1#

DGPU_SELECT#

PCI_REQ3#

PCI_GNT0#
PCI_GNT1#

PCI_GNT3#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

12

PCI_SERR#
PCI_PERR#

PCI_IRDY#

PCI_DEVSEL#
PCI_FRAME#

PCI_LOCK#

PCI_STOP#
PCI_TRDY#

PLT_RST#

1 2
1 2

1 2

USB_OC#0
WXMIT_OFF#
USB_OC#1
USB_OC#2

USB_OC#6
USB_OC#5
USB_OC#4
EXP_CPPE#

U1E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1# / GPIO50

B45

REQ2# / GPIO52

M53

REQ3# / GPIO54

F48

GNT0#

K45

GNT1# / GPIO51

F36

GNT2# / GPIO53

H53

GNT3# / GPIO55

B41

PIRQE# / GPIO2

K53

PIRQF# / GPIO3

A36

PIRQG# / GPIO4

A48

PIRQH# / GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IBEXPEAK-M_FCBGA1071

R_CLK_DEBUG_PORT_1

RP8

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

RP9

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

R_CLK_PCI_FB
R_CLK_PCI_EC

+3VALW

BUF_PLT_RST#<6>

PCI

4

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

NV_DQS0
NV_DQS1

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11

NVRAM

NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

NV_ALE
NV_CLE

NV_RCOMP

NV_RB#

NV_WR#0_RE#
NV_WR#1_RE#

NV_WE#_CK0
NV_WE#_CK1

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USB

USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

PCI_GNT0#

PCI_GNT1#

Boot BIOS Strap

0

0

1

R179 0_0402_5%

12

@

100K_0402_5%

4

R185

R163 1K_0402_5%@

R164 1K_0402_5%@

P

1 2

@

4

O

GPIO8

AY9

This signal has a weak internal

BD1

pull up ,can't Pull low

AP15
BD8

GPIO15

AV9

L：Intel ME Crypto Transport

BG8

Layer Security(TLS) chiper sui te

AP7

with no confidentiality

AP6

H：Intel ME Crypto Transport

AT6
AT9

Layer Security(TLS) chiper sui te

BB1

with confidentiality

AV6
BB3

it have weak internal PU 20K

BA4
BE4
BB6
BD6

Check list Rev0.8 section1.23.2 If not

BB7

implemented, the Braidwood interface

BC8

signals can be left as No Connect (NC).

BJ8
BJ6
BG6

NV_ALE

BD3

NV_CLE

AY6

AU2

AV7

GPIO27

AY8
AY5

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

AV11
BF5

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

B25

D25

N16
J16
F16
L16
E14
G16
F12
T15

CI_GNT1#PCI_GNT0#

U2

H：On-Die voltage regulator enabl e

*

L：On-Die PLL Voltage Regulator d isable

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5

USB6 and USB7 don't
support on HM55

USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N12
USB20_P12

PV：Change BT and F inger print to Port 11 and Por t 12

USBRBIAS

R155 22.6_0402_1%

Boot BIOS
Location

LPC

Reserved(NAND)

PCI

SPI

*

PLT_RST#

1

2

1 2

Within 500
mils

USB_OC#0

USB_OC#1

USB_OC#2
WXMIT_OFF#
USB_OC#4
USB_OC#5
USB_OC#6
EXP_CPPE#

1 2

1 2

0

1

0

11

+3VS

5

P

IN1

IN2

G

SN74AHC1G08DCKR_SC70-5

3

USB20_N0 <36>
USB20_P0 <36>
USB20_N1 <36>
USB20_P1 <36>
USB20_N2 <36>
USB20_P2 <36>
USB20_N3 <21>
USB20_P3 <21>
USB20_N4 <21>
USB20_P4 <21>
USB20_N5 <31>
USB20_P5 <31>

USB20_N8 <31>
USB20_P8 <31>
USB20_N9 <31>
USB20_P9 <31>
USB20_N10 <33>
USB20_P10 <33>
USB20_N11 <36>
USB20_P11 <36>
USB20_N12 <36>
USB20_P12 <36>

BT_OFF <36>

WXMIT_OFF# <31>

EXP_CPPE# <31>

SI：G sensor LED
change to GPIO3 9

3

PCH_GPIO0

DGPU_EDIDSEL#

DGPU_HPD_INT#

EC_SCI#

EC_SCI#<38>

EC_SMI#

EC_SMI#<38>

PCH_GPIO12

PCH_GPIO15

DGPU_HOLD_RST#

DGPU_PWROK

GPIO22

XMIT_OFF

Internal VccVRM Option

PCH_GPIO28

H_STP_PCI#

GPIO35

DGPU_PWR_EN

VGA_PRSNT_L#

WWAN_DETECT#

HDDHALT_LED#

PCIECLKREQ6#

R1078

PCIECLKREQ7#

1 2

0_0402_5%

GPIO48

PCH_TEMP_ALERT#

GPIO57

*

+3VS

MB

MB

MB USB/ESATA

Touch Screen

USB Camera

WLAN

R140 1K_0402_1%

1 2

+3VS

DGPU_EDIDSEL#<20,22>

DGPU_HPD_INT#<23>

DGPU_HOLD_RST#<24>

DGPU_PWROK<48>

XMIT_OFF<31>

R145 10K_0402_5%

1 2

DGPU_PWR_EN<23,40,46,48>

SI：Add WWAN detect

WWAN_DETECT#<31>

HDDHALT_LED#<39>

PCH_DDR_RST<6>

PCH_TEMP_ALERT#<38>

EHCI 1

PV：Add PCH_DDR_RST (GPIO46)
SI：Reserved PCH te mp alert#

WWAN

New Card

USB Card reader

Finger print

EHCI2

BT

PV：Add 0 ohm betwe en power switch and PCH

Intel Anti-Theft Techonlogy

High=Endabled

NV_ALE

Low=Disable(flo ating)

NV_ALE

R174 1K_0402_5%@

1 2

DMI Termination Voltage

Set to Vcc when HIGH

NV_CLE

Set to Vss when LOW

Weak internal
PU,Do not pull low

NV_CLE

R184 1K_0402_5%@

1 2

3

*

N

V_ALE

+1.8VS

Enable Intel Anti-Theft
Technology：8.2K PU to +3VS

Disable Intel Anti-Theft
Technology：floating(internal PD)

NV_CLE

DMI termination voltage.
weak internal PU, don't PD

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U1F

Y3

BMBUSY# / GPIO0

C38

TACH1 / GPIO1

D37

TACH2 / GPIO6

J32

TACH3 / GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CTRL / GPIO12

T7

GPIO15

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

Y7

SCLOCK / GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI# / GPIO34

V6

SATACLKREQ# / GPIO35

AB7

SATA2GP / GPIO36

AB13

SATA3GP / GPIO37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PCIECLKRQ6# / GPIO45

F1

PCIECLKRQ7# / GPIO46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IBEXPEAK-M_FCBGA1071

2008/03/13 2009/05/11

Compal Secret Data

2

GPIO

NCTF

Deciphered Date

2

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

CPU

RSVD

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N
CLKOUT_PCIE7P

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

TP10

TP11

TP12

TP13

TP14

TP15

TP16

TP17

TP18

TP19

NC_1

NC_2

NC_3

NC_4

NC_5

INIT3_3V#

TP24

1

AH45

T19 PAD

AH46

T20 PAD

AF48

T21 PAD

AF47

T22 PAD

GATEA20

U2

AM3

AM1

PCH_PECI_R

BG10

KB_RST#

T1

BE10

H_THERMTRIP#_L

BD10

BA22

TP1

AW22

TP2

BB22

TP3

AY45

TP4

AY46

TP5

AV43

TP6

AV45

TP7

AF13

TP8

M18

TP9

N18

AJ24

AK41

AK42

M32

N32

M30

N30

H12

AA23

AB45

AB38

AB42

AB41

T39

P6

C10

Title

Size Document Number Rev

Custom

Calpella DIS LA4743P

Date: Sheet of

GATEA20 <38>

CLK_CPU_BCLK# <6>

CLK_CPU_BCLK <6>

R144 0_0402_5%

1 2

KB_RST# <38>

H_CPUPWRGD <6>

1 2

R146

EC_SCI#

DGPU_EDIDSEL#

KB_RST#

DGPU_PWR_EN

DGPU_HPD_INT#

VGA_PRSNT_L#

DGPU_HOLD_RST#

WWAN_DETECT#

GATEA20

PCH_TEMP_ALERT#

HDDHALT_LED#

GPIO48

GPIO22

DGPU_PWROK

DGPU_PWROK

OK

54.9_0402_1%

12

R147
56_0402_5%

+VCCP

R166 10K_0402_5%

1 2

R167 10K_0402_5%

1 2

R171 10K_0402_5%

1 2

R172 10K_0402_5%

1 2

R173 10K_0402_5%

1 2
UMA@

R175 10K_0402_5%

1 2

R176 10K_0402_5%

1 2

R178 10K_0402_5%

1 2

R180 10K_0402_5%

1 2

R181 10K_0402_5%

1 2

R169 10K_0402_5%

1 2

R170 10K_0402_5%

1 2

R168 10K_0402_5%

1 2

R874 10K_0402_5%

1 2

R1062 10K_0402_5%@

1 2

INIT3_3V

This signal has weak internal
PU, can't pull low

T48 PAD

EC_SMI#

PCH_GPIO15

PCH_GPIO12

PCIECLKREQ6#

PCIECLKREQ7#

PCH_GPIO28

GPIO57

GPIO35

VGA_PRSNT_L#

GPIO57

PCH_GPIO28

R157 10K_0402_5%

1 2

R159 1K_0402_5%

1 2

R811 10K_0402_5%

1 2

R812 10K_0402_5%

1 2

R813 10K_0402_5%

1 2

R814 10K_0402_5%

1 2

R182 10K_0402_5%

1 2

R165 10K_0402_5%

R911 10K_0402_5%

SG@

R187 10K_0402_5%@

High: M93, Low: M93-LP

R816 10K_0402_5%@

High: Park, Low: Park-LP

1 2

1 2

1 2

12

Compal Electronics, Inc.

IBEX-M(4/6)-PCI/USB/RSVD

1

14 52Friday, September 11, 2009

H_PECI <6>

H_THERMTRIP# <6,26>

+3VS

+3VALW

0.4

5

4

3

2

1

1 2

1

C162

2

10U_0805_6.3V6M

1 2

+1.8VS

+1.05VS

1

C173

2

1U_0402_6.3V6K

+V1.1A_INT_VCCSUS

1

C188

2

4.7U_0603_6.3V6K

1

2

+VCCP_VCCA_CLK

1

1

C143

@

2

2

10U_0805_6.3V6M

C152

0.1U_0402_16V4Z

+1.05VS

1

2

1

1

C163

2

2

10U_0805_6.3V6M

+VCCRTCEXT

0.1U_0402_16V4Z

1

C174

2

1U_0402_6.3V6K

+VCCSST

+3VALW

0.2A@3.3V

0.2A@3.3V

0.2A@3.3V0.2A@3.3V

+3VS

0.4A@3.3V

0.4A@3.3V

0.4A@3.3V0.4A@3.3V

0.1A@1.1V

0.1A@1.1V

0.1A@1.1V0.1A@1.1V

1

1

C189

2

2

0.1U_0402_16V4Z

2mA@3.3V

2mA@3.3V

2mA@3.3V2mA@3.3V

1

C196

2

0.1U_0402_16V4Z

C144

@

1U_0402_6.3V6K

C153

1U_0402_6.3V6K

C161

1U_0402_6.3V6K

C175

1U_0402_6.3V6K

C190

0.1U_0402_16V4Z

C197

0.1U_0402_16V4Z

U1J

AP51

VCCACLK[1]

AP53

VCCACLK[2]

AF23

VCCLAN[1]

AF24

VCCLAN[2]

Y20

DCPSUSBYP

AD38

VCCME[1]

AD39

VCCME[2]

AD41

VCCME[3]

AF43

VCCME[4]

AF41

VCCME[5]

AF42

VCCME[6]

V39

VCCME[7]

V41

VCCME[8]

V42

VCCME[9]

Y39

VCCME[10]

Y41

VCCME[11]

Y42

VCCME[12]

V9

DCPRTC

AU24

VCCVRM[3]

0.072A

BB51

VCCADPLLA[1]

BB53

VCCADPLLA[2]

BD51

VCCADPLLB[1]

BD53

VCCADPLLB[2]

AH23

VCCIO[21]

AJ35

VCCIO[22]

AH35

VCCIO[23]

AF34

VCCIO[2]

AH34

VCCIO[3]

AF32

VCCIO[4]

V12

DCPSST

Y22

DCPSUS

P18

VCCSUS3_3[29]

U19

VCCSUS3_3[30]

U20

VCCSUS3_3[31]

U22

VCCSUS3_3[32]

V15

VCC3_3[5]

V16

VCC3_3[6]

Y16

VCC3_3[7]

AT18

V_CPU_IO[1]

AU18

V_CPU_IO[2]

A12

VCCRTC

IBEXPEAK-M_FCBGA1071

POWER

0.052A

0.344A

USB

0.163A

1.998A

>1mA

0.035A

0.073A

3.208A

2mA

>1mA

Clock and Miscellaneous

0.357A

PCI/GPIO/LPC

VCCSATAPLL[1]

0.032A

VCCSATAPLL[2]

SATA

CPU

6mA

RTC PCI/GPIO/LPC

HDA

VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]

VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]

VCCSUS3_3[28]

VCCIO[56]

V5REF_SUS

V5REF

VCC3_3[8]

VCC3_3[9]

VCC3_3[10]

VCC3_3[11]

VCC3_3[12]

VCC3_3[13]

VCC3_3[14]

VCCIO[9]

VCCVRM[4]

VCCIO[10]

VCCIO[11]

VCCIO[12]

VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]

VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]

VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]

VCCSUSHDA

V24
V26
Y24
Y26

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

U23

V23

F24

K49

J38

L38

M36

N36

P36

U35

AD13

AK3
AK1

AH22

AT20

AH19

AD20

AF22

AD19
AF20
AF19
AH20

AB19
AB20
AB22
AD22

AA34
Y34
Y35
AA35

L30

4

+1.05VS

1

C150

2

1U_0402_6.3V6K

1

2

+1.05VS

ICH_V5REF_SUS

ICH_V5REF_RUN

+3VS

1

C171

2

0.1U_0402_16V4Z

+3VS

C176 0.1U_0402_16V4Z

1 2

+1.05VS_VCCAPLL

+1.8VS

1

C184

2

1U_0402_6.3V6K

+PCH_VCC1_1_20
+PCH_VCC1_1_21
+PCH_VCC1_1_22
+PCH_VCC1_1_23

+3.3A_1.5A_VCCPAZSUS

+3VALW

1

C158

C157

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1A@1.1V

0.1A@1.1V

0.1A@1.1V0.1A@1.1V

10UH_LB2012T100MR_20%_0805

1

1

C180

C181

2

@

@

2

1U_0402_6.3V6K

10U_0805_6.3V6M

R194 0_0402_5%

1 2

R195 0_0402_5%

1 2

R198 0_0402_5%

1 2

R200 0_0402_5%

1 2

+3VALW

1

C193

2

1U_0402_6.3V6K

L4

@

1 2

+1.05VS

+1.05VS

+1.05VS

R188

@

1 2

10UH_LB2012T100MR_20%_0805

0_0603_5%

+1.05VS+1.05VS_VCCAPLL_L

R189

@

1 2

0_0603_5%

+1.05VS_L+1.05VS +V1.05S_VCCA_A_DPL_L

R191

1 2

0_0603_5%

0_0603_5%

1 2

0_0603_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.05VS

1

C145

2

1U_0402_6.3V6K

+1.05VS_APLL

L3

@

1 2

+1.05VS

1

C164

2

1U_0402_6.3V6K

1

1

C169

C168

2

2

1U_0402_6.3V6K

+3VS

C682 0.1U_0402_16V4Z

1 2
+1.8VS

+1.05VS_VCCFDIPLL

+1.05VS

R192

1 2

+V1.05S_VCCA_B_DPL_L

R201

1 2

10UH_LB2012T100MR_20%_0805

1 2

10UH_LB2012T100MR_20%_0805

U1G

AB24

VCCCORE[1]

AB26

VCCCORE[2]

AB28

1

2

1

2

1

2

1

2

1U_0402_6.3V6K

L6

L7

C146

10U_0603_6.3V6M

C159

@

10U_0805_6.3V6M

C165

1U_0402_6.3V6K

C170

10U_0603_6.3V6M

VCCCORE[3]

AD26

VCCCORE[4]

AD28

VCCCORE[5]

AF26

VCCCORE[6]

AF28

VCCCORE[7]

AF30

VCCCORE[8]

AF31

VCCCORE[9]

AH26

VCCCORE[10]

AH28

VCCCORE[11]

AH30

VCCCORE[12]

AH31

VCCCORE[13]

AJ30

VCCCORE[14]

AJ31

VCCCORE[15]

AK24

VCCIO[24]

BJ24

VCCAPLLEXP

AN20

VCCIO[25]

AN22

VCCIO[26]

AN23

VCCIO[27]

AN24

VCCIO[28]

AN26

VCCIO[29]

AN28

VCCIO[30]

BJ26

VCCIO[31]

BJ28

VCCIO[32]

AT26

VCCIO[33]

AT28

VCCIO[34]

AU26

VCCIO[35]

AU28

VCCIO[36]

AV26

VCCIO[37]

AV28

VCCIO[38]

AW26

VCCIO[39]

AW28

VCCIO[40]

BA26

VCCIO[41]

BA28

VCCIO[42]

BB26

VCCIO[43]

BB28

VCCIO[44]

BC26

VCCIO[45]

BC28

VCCIO[46]

BD26

VCCIO[47]

BD28

VCCIO[48]

BE26

VCCIO[49]

BE28

VCCIO[50]

BG26

VCCIO[51]

BG28

VCCIO[52]

BH27

VCCIO[53]

AN30

VCCIO[54]

AN31

VCCIO[55]

AN35

VCC3_3[1]

AT22

VCCVRM[1]

BJ18

VCCFDIPLL

AM23

VCCIO[1]

IBEXPEAK-M_FCBGA1071

+V1.05S_VCCA_A_DPL

2

1

+V1.05S_VCCA_B_DPL

1

2

2008/03/13 2009/05/11

POWER

1.524A

0.042A

0.035A

6mA

1

+

C186

C187

2

1U_0402_6.3V6K

220U_D2_4VM_R15

1

+

C191

C192

2

1U_0402_6.3V6K

220U_B_2.5VM_R15M

Compal Secret Data

Deciphered Date

0.069A

CRTLVDS

0.030A

VCC CORE

0.059A

HVCMOS

0.061A

DMI

PCI E*

0.156A

NAND / SPI

0.085A

FDI

12

0_0603_5%

2

VCCADAC[1]

VCCADAC[2]

VSSA_DAC[1]

VSSA_DAC[2]

VSSA_LVDS

VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]

VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]

VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]

R193

@

VCCALVDS

VCC3_3[2]

VCC3_3[3]

VCC3_3[4]

VCCVRM[2]

VCCDMI[1]

VCCDMI[2]

AE50

AE52

AF53

AF51

AH38

AH39

AP43
AP45
AT46
AT45

AB34

AB35

AD35

AT24

AT16

AU16

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

AM8
AM9
AP11
AP9

C998

1

2

+1.8VS

+VCCP

+1.05VS

R196

100_0402_5%

12

L5

@

1 2

R197

100_0402_5%

+3VS

+5VS +3VS+3VALW+5VALW

12

1

L45

1

C147

2

0.01U_0402_25V7K

0.01U_0603_16V7K

C999

1

2

1

C167

2

1U_0402_6.3V6K

1

2

+3VS

1

2

12

MURATA_BLM18AG601SN1D_0603

1

1

C149

C148

2

2

0.1U_0402_16V4Z

10U_0805_6.3V6M

+3VS

R779 0_0603_5%

0.01U_0603_16V7K

C172

C178

1 2

10U_0805_6.3V6M

C1000

1

2

+3VS

1

C160

2

0.1U_0402_16V4Z

R671 0_0402_5%

1 2

R672 0_0402_5%@

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.05VS_VCCFDIPLL_L

R190

@

1 2

0_0603_5%

10UH_LB2012T100MR_20%_0805

21

D4

CH751H-40PT_SOD323-2

ICH_V5REF_SUS

1

C194
1U_0402_6.3V4K_X5R

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

IBEX-M(5/6)-PWR

Calpella DIS LA4743P

+1.8VS

+1.8VS

+3VS

+1.05VS_VCCFDIPLL

1

@

2

21

D5

CH751H-40PT_SOD323-2

ICH_V5REF_RUN

1

C195
1U_0402_6.3V4K_X5R

2

15 52Friday, September 11, 2009

C183

10U_0805_6.3V6M

20 mils20 mils

0.4

of

+1.05VS +VCCP_VCCA_CLK_L

R186

@

1 2

0_0603_5%

10UH_LB2012T100MR_20%_0805

D D

C C

B B

A A

DG1.1 no M3
support and not
Intel LAN, VCCLAN
Source=>GND

+RTCVCC

L1

@

1 2

C166

+V1.05S_VCCA_A_DPL

+V1.05S_VCCA_B_DPL

1

2

1 2

0.1U_0402_16V4Z

C177

1 2

0.1U_0402_16V4Z

C179

1 2

0.1U_0402_16V4Z

C182

1 2

0.1U_0402_16V4Z

C185

+VCCP

5

5

4

3

2

1

U1I

AY7

VSS[159]

B11

VSS[160]

B15

VSS[161]

B19

VSS[162]

B23

VSS[163]

B31

VSS[164]

B35

VSS[165]

B39

VSS[166]

B43

VSS[167]

B47

D D

C C

B B

BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49

BC10
BC14
BC18

BC22
BC32
BC36
BC40
BC44
BC52

BD48
BD49

BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50

BF49

BF51
BG18
BG24

BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47

AF39

VSS[168]

B7

VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]

BB5

VSS[180]
VSS[181]
VSS[182]
VSS[183]

BC2

VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]

BH9

VSS[191]
VSS[192]
VSS[193]

BD5

VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]

BE6

VSS[206]

BE8

VSS[207]

BF3

VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]

BG4

VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]

BH7

VSS[224]

C12

VSS[225]

C50

VSS[226]

D51

VSS[227]

E12

VSS[228]

E16

VSS[229]

E20

VSS[230]

E24

VSS[231]

E30

VSS[232]

E34

VSS[233]

E38

VSS[234]

E42

VSS[235]

E46

VSS[236]

E48

VSS[237]

E6

VSS[238]

E8

VSS[239]

F49

VSS[240]

F5

VSS[241]

G10

VSS[242]

G14

VSS[243]

G18

VSS[244]

G2

VSS[245]

G22

VSS[246]

G32

VSS[247]

G36

VSS[248]

G40

VSS[249]

G44

VSS[250]

G52

VSS[251]
VSS[252]

H16

VSS[253]

H20

VSS[254]

H30

VSS[255]

H34

VSS[256]

H38

VSS[257]

H42

VSS[258]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]

H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14

U1H

AB16

VSS[0]

AA19

VSS[1]

AA20

VSS[2]

AA22

VSS[3]

AM19

VSS[4]

AA24

VSS[5]

AA26

VSS[6]

AA28

VSS[7]

AA30

VSS[8]

AA31

VSS[9]

AA32

VSS[10]

AB11

VSS[11]

AB15

VSS[12]

AB23

VSS[13]

AB30

VSS[14]

AB31

VSS[15]

AB32

VSS[16]

AB39

VSS[17]

AB43

VSS[18]

AB47

VSS[19]

AB5

VSS[20]

AB8

VSS[21]

AC2

VSS[22]

AC52

VSS[23]

AD11

VSS[24]

AD12

VSS[25]

AD16

VSS[26]

AD23

VSS[27]

AD30

VSS[28]

AD31

VSS[29]

AD32

VSS[30]

AD34

VSS[31]

AU22

VSS[32]

AD42

VSS[33]

AD46

VSS[34]

AD49

VSS[35]

AD7

VSS[36]

AE2

VSS[37]

AE4

VSS[38]

AF12

VSS[39]

Y13

VSS[40]

AH49

VSS[41]

AU4

VSS[42]

AF35

VSS[43]

AP13

VSS[44]

AN34

VSS[45]

AF45

VSS[46]

AF46

VSS[47]

AF49

VSS[48]

AF5

VSS[49]

AF8

VSS[50]

AG2

VSS[51]

AG52

VSS[52]

AH11

VSS[53]

AH15

VSS[54]

AH16

VSS[55]

AH24

VSS[56]

AH32

VSS[57]

AV18

VSS[58]

AH43

VSS[59]

AH47

VSS[60]

AH7

VSS[61]

AJ19

VSS[62]

AJ2

VSS[63]

AJ20

VSS[64]

AJ22

VSS[65]

AJ23

VSS[66]

AJ26

VSS[67]

AJ28

VSS[68]

AJ32

VSS[69]

AJ34

VSS[70]

AT5

VSS[71]

AJ4

VSS[72]

AK12

VSS[73]

AM41

VSS[74]

AN19

VSS[75]

AK26

VSS[76]

AK22

VSS[77]

AK23

VSS[78]

AK28

VSS[79]

IBEXPEAK-M_FCBGA1071

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47

A A

5

IBEXPEAK-M_FCBGA1071

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(6/6)-GND

Calpella DIS LA4743P

1

16 52Friday, September 11, 2009

0.4