COMPAL LA-4631P Schematics

A

1 1

B

C

D

E

2 2

Compal Confidential

Schematic Document

MCP79-MX

2009 / 02 / 19

3 3

Rev:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-4631P

E

142Thursday, Fe br ua ry 19, 2009

1.0

of

A

B

C

D

E

Compal confidential

Braxton 14"

Project Code : KCM00
File Name : LA-4631P

PCB

1 1

ZZZ1

X76

ZZZ2

Fan Driver

RT9027BPS

Thermal Sensor

EMC1402-1-ACZL-TR

P.4

P.4

Intel Penryn

uFCPGA-478 CPU

H_A#(3..35)
H_D#(0..63)

FSB

667/800/1066MHz 1.05V

P.4,5,6

Memory

14" LED Panel
HD 1366 x 768
HD+ 1600 x 900

2 2

HDMI Conn.

P.21

1:2 Switch

P.20

TI

Display Port

SN75DP122A

P.21

P.21

LVDS

HDMI / TMDS

nVIDIA
MCP79-MX

FCBGA 1437

PCI-E x1

PCIE1 PCIE2

Express Card

( 34mm )

3 3

P.23

RealTek
RTL8111DL

RJ45 Conn.

P.22

P.22

Mini Card-1
WLAN (Half)

P.24

PCIE3PCIE0

JMicron
JMB380

IEEE1394

P.26

B to B

P.29

P.7~16

LPC

Power On/Off CKT.

P.29

DC/DC Int erface CKT.

P.30

4 4

Power Circuit DC/DC

P.32~40

A

RTC CKT.

P.14,15,32,33

Power OK CKT.

Touch Pad Conn

B

P.29

KBC

ENE KB926

P.28

Int.KB

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BIOS(System/EC)

P.29

C

2009/02/19 2009/12/31

Dual Channel

DDR3 800/1066 MHz +1.5V

Channel B

SATA

USB2.0

HDA

P.28

SATA_A0

SATA_A1

B to B

USB2

USB1

B to B

USB0

USB3

USB7

USB6

USB5

USB4

Compal Secret Data

Deciphered Date

Channel A

DDR3 / 1GB on board
( 128Mx8) x8pcs

DDR3-SO-DIMM x1

BANK 0, 1, 2, 3

SATA HDD Conn

USB/E-SATA Conn

On Right Side

USB Conn

On Right Side

USB Conn

On Left Side

Express Card

( 34mm )

Mini Card-1 (WLAN)

( Half )

Mini Card-2 (WWAN)

( Full )

Blue Tooth

Camera

Audio Codec
IDT 92HD83

D

P.17,18

P.19

P.20

P.29

P.29

P.27

P.23

P.24

P.24

P.27

P.27

P.25

Title

Size Document Number Rev

Custom

Date: Sheet

SIM Card

Digital Microphone

Tweeter (0.5W x2)

Speaker (1W x2)

Audio Jack x3

B to B

Compal Electronics, Inc.

Block Diagram

LA-4631P

P.24

P.27

P.25, 29

P.25

P.29

1.0

of

242Thursday, F e b r u a ry 19, 2009

E

A

Voltage Rails

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

1 1

O MEANS ON X MEANS OFF

power
plane

+5VS
+3VS
+1.8VS

+B

O
O
O
O
O

X

+5VALW
+3VALW
+1.1VALW

O
O
O
O

X
XX X

+1.5V

O

XX
X

+1.1VS
+VCCP
+1.0VS
+0.75VS
+CPU_CORE
+1.5VS

OO
OO

X

X

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7

SMBUS Control Table

100K +/- 5%Ra

Rb V min

00 V
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

NC

SOURCE

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
DEBUG@ : means jus t r e s e r v e for debug.

AD_BID

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

INVERTER BATT EEPROM

Vtyp

AD_BID

0.503 V

0.819 V

1.185 V 1.264 V

2.200 V

3.300 V

SERIAL SENSOR

THERMAL
(CPU)

0 V 0 V

SODIMM EXP CARD

V

AD_BID

0.538 V

0.875 V

2.341 V

3.300 V

max

MINI CARD1

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

MINI CARD2

PCB Revision

0.1

0.2

0.3

0.4

0.5

1.0

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

MEM_SMBCLK
MEM_SMBDATA MCP79

MCP_SMB_CLK
MCP_SMB_DATA

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

KB926

KB926

X
X

X

MCP79

A

XX

2009/02/19 2009/12/31

Compal Secret Data

X

V

XX
X

X
XX

MINI CARD 1 R E S E R VE D +3VALW TO PULL HIGH

Deciphered Date

XX

V

X

X

V

X

XXX
XX

X

X

X
X

VVV

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-4631P

342Thursday, F eb r u ary 19, 2009

1.0

of

5

4

3

2

1

D D

H_A#[3..16]7

H_ADSTB#07

C C

B B

A A

H_REQ#07
H_REQ#17
H_REQ#27
H_REQ#37
H_REQ#47
H_A#[17..35]7

H_ADSTB#17
H_A20M#7

H_FERR#7
H_IGNNE#7

H_STPCLK#7
H_INTR7
H_NMI7
H_SMI#7

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

JCPU1A

J4

ADDR GROUP_0

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

ADDR GROUP_1

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4
AB2
AA3

V1
A6

A5

C4
D5

C6

B4
A3

M4
N5

T2
V3
B2

D2

D22

D3

F6

THERMAL

A[33]#
A[34]#
A[35]#
ADSTB[1]#

ICH

A20M#
FERR#

THERMTRIP#

IGNNE#
STPCLK#

LINT0
LINT1
SMI#

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

RESERVED

TYCO_2-1871873-3_Merom~D

CONN@

ADS#
BNR#

BPRI#

DEFER#

DRDY#

DBSY#

BR0#
BR1#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

DBR#

XDP/ITP SIGNALS

PROCHOT#

THERMDA
THERMDC

H CLK

BCLK[0]
BCLK[1]

H_ADS#

H1

H_BNR#

E2

H_BPRI#

G5

H_DEFER#

H5

H_DRDY#

F21

H_DBSY#

E1

H_BR0#

F1

H_BR1#

AA7

H_IERR#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_TRDY#

G2

H_HIT#

G6

H_HITM#

E4

XDP_BPM#0

AD4

XDP_BPM#1

AD3

XDP_BPM#2

AD1

XDP_BPM#3

AC4

XDP_BPM#4

AC2

XDP_PREQ#

AC1

XDP_TCK

AC5

XDP_TDI

AA6

TDI

XDP_TDO

AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_DBRESET#

C20

H_PROCHOT#

D21

H_THERMDA_R

A24

H_THERMDC_R

B25

H_THERMTRIP#

C7

CLK_CPU_BCLK

A22

CLK_CPU_BCLK#

A21

H_ADS# 7
H_BNR# 7
H_BPRI# 7

H_DEFER# 7
H_DRDY# 7
H_DBSY# 7

H_BR0# 7
H_BR1# 7

H_INIT# 7
H_LOCK# 7

H_RESET# 7
H_RS#0 7
H_RS#1 7
H_RS#2 7
H_TRDY# 7

H_HIT# 7
H_HITM# 7

T1
T2
T3
T4
T5
T6

T7

H_PROCHOT# 7

R7 100_0402_5%

1 2

R8 100_0402_5%

1 2

H_THERMTRIP# 7

CLK_CPU_BCLK 7
CLK_CPU_BCLK# 7

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

H_THERMDA
H_THERMDC

Fan Control circuit

FAN_SPEED128

0.01U_0402_16V7K

Thermal Sensor

1 2

C2 2200P_0402_50V7K

1 2

+3VS

10K_0402_5%

+3VS

R10

10K_0402_5%

C6

+3VS

1

C1

2

0.1U_0402_16V4Z

H_THERMDA
H_THERMDC
L_THERM#

R9

12

2

1

XDP Reserve

Place close to CPU within 500mil

H_IERR#
H_THERMTRIP#
XDP_PREQ#
XDP_TDI
XDP_TDO
XDP_TMS
H_PROCHOT#
H_BR0#
H_FERR#
H_INTR
H_NMI
H_RESET#
H_BR1#
XDP_TCK
XDP_TRST#

C3

10U_1206_16V4Z~N

1 2

C5

1000P_0402_50V7K~N

EN_DFAN128

U2

1

VDD

2

D+

3

D­THERM#4GND

EMC1402-1-ACZL-TR MSOP 8P

SMBus Address:100_1100

R513 49.9_0402_1%
R514 49.9_0402_1%
R515 49.9_0402_1%
R516 49.9_0402_1%
R517 49.9_0402_1%
R518 49.9_0402_1%
R519 68_0402_5%
R520 62_0402_5%@

1 2

R521 62_0402_5%

1 2

R522 150_0402_1%@

1 2

R523 150_0402_1%@

1 2

R524 200_0402_1%@

1 2

R1275 62_0402_5%

1 2

R525 49.9_0402_1%
R526 649_0402_1%

+5VS

12

EN_DFAN1

40mil

FAN1_POWER

8

SCLK

7

SDATA

6

ALERT#

5

12
12
12
12
12
12
12

12
12

1
2
3
4

1
2
3

4
5

EC_SMB_CK2
EC_SMB_DA2

C4

1 2

10U_1206_16V4Z~N
U3

VEN

GND

VIN

GND
GND

VO

GND

VSET

RT9027BPS SO 8P
JFAN1

1
2
3

GND
GND

MOLEX_53780-0370~D

CONN@

EC_SMB_CK2 28

EC_SMB_DA2 28

+VCCP

8
7
6
5

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Penryn(1/3)-A GTL+/ITP-XDP

LA-4631P

1

1.0

of

442Tuesday, Fe b r u a r y 24, 2009

5

4

3

2

1

H_D#[0..15]7

D D

H_DSTBN#07
H_DSTBP#07
H_DINV#07
H_D#[16..31]7

C C

R13 1K_0402_5%@
R14 1K_0402_5%@

C308 0.1U_0402_16V4Z@

H_DSTBN#17
H_DSTBP#17
H_DINV#17

1 2
1 2

1 2

CPU_BSEL07
CPU_BSEL17
CPU_BSEL27

T8

T10
T11
T12

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

V_CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

JCPU1B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

C3

TEST7

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

TYCO_2-1871873-3_Merom~D

CONN@

MISC

DATA GRP 0

DATA GRP 1

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#

DATA GRP 2DATA GRP 3

D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

layout note: Rout H_DPRSTP# from ICH9 to IMVP6 then to GMCH & CPU
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

CPU_BSEL CPU_BSEL2 CPU_BSEL1

B B

166

200

01

0

1

266000

CPU_BSEL0

1

0

H_PWRGOOD
H_CPUSLP#
H_DPRSTP#

H_DPRSTP#

0.01U 16V K X7R 0402

R527 150_0402_1%@

1 2

R528 51_0402_1%@

1 2

R529 220_0402_1%@

1 2

C649

@

H_D#[32..47] 7

H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7
H_D#[48..63] 7

H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7

H_DPRSTP# 7,38
H_DPSLP# 7

H_DPWR# 7

H_PWRGOOD 7
H_CPUSLP# 7

H_PSI# 38

To IMVP

R15

12

54.9_0402_1%

R16

12

27.4_0402_1%

R17

12

54.9_0402_1%

R18

12

27.4_0402_1%

49.9 25.5 29.9 25.5

Resistor placed within

+VCCP

1

2

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4

+CPU_CORE +CPU_CORE

47A

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AC10
AB10
AB12
AB14
AB15
AB17
AB18

A7

A9
A10
A12
A13
A15
A17
A18
A20

B7

B9
B10
B12
B14
B15
B17
B18
B20

C9
C10
C12
C13
C15
C17
C18

D9
D10
D12
D14
D15
D17
D18

E7

E9
E10
E12
E13
E15
E17
E18
E20

F7

F9
F10
F12
F14
F15
F17
F18
F20

AA9

AB9

JCPU1C

VCC[001]

VCC[068]

VCC[002]

VCC[069]

VCC[003]

VCC[070]

VCC[004]

VCC[071]

VCC[005]

VCC[072]

VCC[006]

VCC[073]

VCC[007]

VCC[074]

VCC[008]

VCC[075]

VCC[009]

VCC[076]

VCC[010]

VCC[077]

VCC[011]

VCC[078]

VCC[012]

VCC[079]

VCC[013]

VCC[080]

VCC[014]

VCC[081]

VCC[015]

VCC[082]

VCC[016]

VCC[083]

VCC[017]

VCC[084]

VCC[018]

VCC[085]

VCC[019]

VCC[086]

VCC[020]

VCC[087]

VCC[021]

VCC[088]

VCC[022]

VCC[089]

VCC[023]

VCC[090]

VCC[024]

VCC[091]

VCC[025]

VCC[092]

VCC[026]

VCC[093]

VCC[027]

VCC[094]

VCC[028]

VCC[095]

VCC[029]

VCC[096]

VCC[030]

VCC[097]

VCC[031]

VCC[098]

VCC[032]

VCC[099]

VCC[033]

VCC[100]
VCC[034]
VCC[035]

VCCP[01]

VCC[036]

VCCP[02]

VCC[037]

VCCP[03]

VCC[038]

VCCP[04]

VCC[039]

VCCP[05]

VCC[040]

VCCP[06]

VCC[041]

VCCP[07]

VCC[042]

VCCP[08]

VCC[043]

VCCP[09]

VCC[044]

VCCP[10]

VCC[045]

VCCP[11]

VCC[046]

VCCP[12]

VCC[047]

VCCP[13]

VCC[048]

VCCP[14]

VCC[049]

VCCP[15]

VCC[050]

VCCP[16]

VCC[052]

VCCA[01]

VCC[053]

VCCA[02]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

TYCO_2-1871873-3_Merom~D

CONN@

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

For 8 layer condition

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

+1.5VS_VCCA

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VSSSENSE

AE7

.

4.5A

10mil

CPU_VID0 38
CPU_VID1 38
CPU_VID2 38
CPU_VID3 38
CPU_VID4 38
CPU_VID5 38
CPU_VID6 38

VCCSENSE 38

VSSSENSE 38

Layout Note:
Route VCCSENSE and VSSSENSE traces at

27.4 Ohms with 50 mil spacing.

+VCCP

1

+

C7

330U 2.5V Y D2 LESR15M CX H1.9

2

1

1

C8

C9

2

2

10U_0805_6.3V6M

0.01U_0402_16V7K

Near pin B26

0_0805_5%

1 2

Length match within 25 mils.
The trace width/space/other is
20/7/25.

R1283

+1.5VS

+VCCP

12

R19
1K_0402_1%

V_CPU_GTLREF

A A

Dual Core CPU

12

R20
2K_0402_1%

For 6 layer

Z=27.4 ohm
VCCSENSE, VSSSENSE/ 14mils (MS),
16mils (SL) width, 7mils space, 25mils
space to other signals Mismatch =25mils.

+CPU_CORE

R21 100_0402_1%

1 2

R23 100_0402_1%

1 2

Close to CPU pin
within 500mils.

VCCSENSE

VSSSENSE

Close to CPU pin AD26
within 500mils.

5

4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Penryn(2/3)-AGTL+/ITP-XDP

LA-4631P

1

of

542Tuesday, Fe b r u a r y 24, 2009

1.0

5

Near CPU CORE regulator

D D

C C

B B

JCPU1D

A4
A8

A11
A14
A16
A19
A23
AF2

B6
B8

B11
B13
B16
B19
B21
B24

C5

C8
C11
C14
C16
C19

C2
C22
C25

D1

D4

D8
D11
D13
D16
D19
D23
D26

E3
E6

E8
E11
E14
E16
E19
E21
E24

F5

F8
F11
F13
F16
F19

F2
F22
F25

G4

G1
G23
G26

H3

H6
H21
H24

J2

J5
J22
J25

K1

K4
K23
K26

L3

L6
L21
L24

M2

M5
M22
M25

N1

N4
N23
N26

VSS[082]

VSS[001]
VSS[002]

VSS[083]

VSS[003]

VSS[084]

VSS[004]

VSS[085]

VSS[005]

VSS[086]

VSS[006]

VSS[087]

VSS[007]

VSS[088]

VSS[008]

VSS[089]

VSS[009]

VSS[090]

VSS[010]

VSS[091]

VSS[011]

VSS[092]

VSS[012]

VSS[093]

VSS[013]

VSS[094]

VSS[014]

VSS[095]

VSS[015]

VSS[096]

VSS[016]

VSS[097]

VSS[017]

VSS[098]

VSS[018]

VSS[099]

VSS[019]

VSS[100]

VSS[020]

VSS[101]

VSS[021]

VSS[102]

VSS[022]

VSS[103]

VSS[023]

VSS[104]

VSS[024]

VSS[105]

VSS[025]

VSS[106]

VSS[026]

VSS[107]

VSS[027]

VSS[108]

VSS[028]

VSS[109]

VSS[029]

VSS[110]

VSS[030]

VSS[111]

VSS[031]

VSS[112]

VSS[032]

VSS[113]

VSS[033]

VSS[114]

VSS[034]

VSS[115]

VSS[035]

VSS[116]

VSS[036]

VSS[117]

VSS[037]

VSS[118]

VSS[038]

VSS[119]

VSS[039]

VSS[120]

VSS[040]

VSS[121]

VSS[041]

VSS[122]

VSS[042]

VSS[123]

VSS[043]

VSS[124]

VSS[044]

VSS[125]

VSS[045]

VSS[126]

VSS[046]

VSS[127]

VSS[047]

VSS[128]

VSS[048]

VSS[129]

VSS[049]

VSS[130]

VSS[050]

VSS[131]

VSS[051]

VSS[132]

VSS[052]

VSS[133]

VSS[053]

VSS[134]

VSS[054]

VSS[135]

VSS[055]

VSS[136]

VSS[056]

VSS[137]

VSS[057]

VSS[138]

VSS[058]

VSS[139]

VSS[059]

VSS[140]

VSS[060]

VSS[141]

VSS[061]

VSS[142]

VSS[062]

VSS[143]

VSS[063]

VSS[144]

VSS[064]

VSS[145]

VSS[065]

VSS[146]

VSS[066]

VSS[147]
VSS[148]

VSS[067]
VSS[068]

VSS[149]

VSS[069]

VSS[150]

VSS[070]

VSS[151]

VSS[071]

VSS[152]

VSS[072]

VSS[153]

VSS[073]

VSS[154]

VSS[074]

VSS[155]

VSS[075]

VSS[156]

VSS[076]

VSS[157]

VSS[077]

VSS[158]

VSS[078]

VSS[159]

VSS[079]

VSS[160]

VSS[080]

VSS[161]

VSS[081]P3VSS[162]

VSS[163]

TYCO_2-1871873-3_Merom~D

CONN@

ESR <= 1.5m ohm
Capacitor > 1980uF

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

4

+CPU_CORE

12

C11
10U_0805_4V

+CPU_CORE

12

C492
10U_0805_4V

+CPU_CORE

12

C27
10U_0805_4V

+CPU_CORE

12

C581
10U_0805_4V

+VCCP

1

C15

0.1U_0402_10V6K

2

+CPU_CORE +CPU_CORE +CPU_CORE+CPU_CORE

1

+

C456
330U_D2E_2.5VM_R9

2

12

C22
10U_0805_4V

12

C582
10U_0805_4V

1

C16

0.1U_0402_10V6K

2

1

+

C458
330U_D2E_2.5VM_R9

2

12

C12
10U_0805_4V

12

C493
10U_0805_4V

12

C26
10U_0805_4V

12

C584
10U_0805_4V

1

C17

0.1U_0402_10V6K

2

1

+

2

12

C13
10U_0805_4V

12

C577
10U_0805_4V

12

C28
10U_0805_4V

12

C583
10U_0805_4V

1

2

C576
330U_D2E_2.5VM_R9

3

C18

0.1U_0402_10V6K

1

+

C522
330U_D2E_2.5VM_R9

2

12

C14
10U_0805_4V

12

C578
10U_0805_4V

12

C591
10U_0805_4V

12

C586
10U_0805_4V

1

C19

0.1U_0402_10V6K

2

12

C457
10U_0805_4V

12

C579
10U_0805_4V

12

C587
10U_0805_4V

12

C585
10U_0805_4V

12

12

12

C588
10U_0805_4V

1

C20

0.1U_0402_10V6K

2

C484
10U_0805_4V

C580
10U_0805_4V

2

12

C485
10U_0805_4V

12

C589
10U_0805_4V

12

C488
10U_0805_4V

12

C590
10U_0805_4V

12

C489
10U_0805_4V

12

C592
10U_0805_4V

Place these caps inside the
socket cavity on Bottom side.

(North side Secondary)

12

C490
10U_0805_4V

16pcs on TOP side

16pcs on bottom side

1

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Penryn(3/3)-AGTL+/ITP-XDP

LA-4631P

1

1.0

of

642Thursday, F e b r u a ry 19, 2009

5

4

3

2

1

D D

C C

CPU_BSEL2

CPU_BSEL25
CPU_BSEL15
CPU_BSEL05

R560

@

12

1K_0402_5%

+VCCP

R24

@

12

1K_0402_5%

12

R26

R25

@

@

1K_0402_5%

12

1K_0402_5%

H_DSTBP#05
H_DSTBN#05
H_DINV#05

H_DSTBP#15
H_DSTBN#15
H_DINV#15

H_DSTBP#25
H_DSTBN#25
H_DINV#25

H_DSTBP#35
H_DSTBN#35
H_DINV#35

H_A#[3..35]4

H_ADSTB#04
H_ADSTB#14

H_REQ#[0..4]4

MRB(REV.E) 1.1VS

+VCCP

B B

A A

12

2.2U_0402_6.3VM

L1
MBK1608221YZF 0603

+V_PLL_CPU

C23

C24

4.7U_0603_6.3V6K

+VCCP

2

C277

1

2

1

2.2U_0402_6.3VM

H_ADS#4
H_BNR#4
H_BR0#4

H_BR1#4
H_DBSY#4
H_DRDY#4
H_HIT#4
H_HITM#4
H_LOCK#4
H_TRDY#4

H_PROCHOT#4
H_THERMTRIP#4

H_FERR#4

H_RS#04
H_RS#14
H_RS#24

20 mA

+V_PLL_CPU

+1.05VS_PLL

1.1VS

R29 49.9_0402_1%
R30 49.9_0402_1%

R31 49.9_0402_1%
R32 49.9_0402_1%

1 2
1 2

12
12

H_PROCHOT#
H_THERMTRIP#

BCLK_VML_COMP_VCC
BCLK_VML_COMP_GND

H_DSTBP#0
H_DSTBN#0
H_DINV#0

H_DSTBP#1
H_DSTBN#1
H_DINV#1

H_DSTBP#2
H_DSTBN#2
H_DINV#2

H_DSTBP#3
H_DSTBN#3
H_DINV#3

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADSTB#0
H_ADSTB#1

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADS#
H_BNR#
H_BR0#
H_BR1#
H_DBSY#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

T13

R1281 0_0402_5%

1 2

R1280 0_0402_5%

1 2

H_FERR#
CPU_BSEL2

CPU_BSEL1
CPU_BSEL0

H_RS#0
H_RS#1
H_RS#2

29 mA

CPU_COMP_VCC
CPU_COMP_GND

PAD

Close to AM39 Ball

5

4

U4A

T40

CPU_DSTBP0#

U40

CPU_DSTBN0#

V41

CPU_DBI0#

W39

CPU_DSTBP1#

W37

CPU_DSTBN1#

V35

CPU_DBI1#

N37

CPU_DSTBP2#

L36

CPU_DSTBN2#

N35

CPU_DBI2#

M39

CPU_DSTBP3#

M41

CPU_DSTBN3#

J41

CPU_DBI3#

AC34

CPU_A3#

AE38

CPU_A4#

AE34

CPU_A5#

AC37

CPU_A6#

AE37

CPU_A7#

AE35

CPU_A8#

AB35

CPU_A9#

AF35

CPU_A10#

AG35

CPU_A11#

AG39

CPU_A12#

AE33

CPU_A13#

AG37

CPU_A14#

AG38

CPU_A15#

AG34

CPU_A16#

AN38

CPU_A17#

AL39

CPU_A18#

AG33

CPU_A19#

AL33

CPU_A20#

AJ33

CPU_A21#

AN36

CPU_A22#

AJ35

CPU_A23#

AJ37

CPU_A24#

AJ36

CPU_A25#

AJ38

CPU_A26#

AL37

CPU_A27#

AL34

CPU_A28#

AN37

CPU_A29#

AJ34

CPU_A30#

AL38

CPU_A31#

AL35

CPU_A32#

AN34

CPU_A33#

AR39

CPU_A34#

AN35

CPU_A35#

AE36

CPU_ADSTB0#

AK35

CPU_ADSTB1#

AC38

CPU_REQ0#

AA33

CPU_REQ1#

AC39

CPU_REQ2#

AC33

CPU_REQ3#

AC35

CPU_REQ4#

AD42

CPU_ADS#

AD43

CPU_BNR#

AE40

CPU_BR0#

AL32

CPU_BR1#

AD39

CPU_DBSY#

AD41

CPU_DRDY#

AB42

CPU_HIT#

AD40

CPU_HITM#

AC43

CPU_LOCK#

AE41

CPU_TRDY#

E41

CPU_PECI

AJ41

CPU_PROCHOT#

AG43

CPU_THERMTRIP#

AH40

CPU_FERR#

F42

CPU_BSEL2

D42

CPU_BSEL1

F41

CPU_BSEL0

AC41

CPU_RS0#

AB41

CPU_RS1#

AC42

CPU_RS2#

AH28

+V_PLL_CPU

U28

+V_PLL_DP

AM39

BCLK_VML_COMP_VDD

AM40

BCLK_VML_COMP_GND

AM43

CPU_COMP_VCC

AM42

CPU_COMP_GND

MCP79MX-B2 PBGA 1437P

FSB

CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#

CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#

CPU_BPRI#

CPU_DEFER#

BCLK_OUT_CPU_P
BCLK_OUT_CPU_N

BCLK_OUT_ITP_P
BCLK_OUT_ITP_N

BCLK_OUT_NB_P
BCLK_OUT_NB_N

BCLK_IN_N
BCLK_IN_P

CPU_A20M#

CPU_IGNNE#

CPU_INIT#
CPU_INTR

CPU_NMI
CPU_SMI#

CPU_PWRGD
CPU_RESET#

CPU_SLP#

CPU_DPSLP#

CPU_DPWR#
CPU_STPCLK#
CPU_DPRSTP#

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

H_D#1

W42

H_D#2

Y40

H_D#3

W41

H_D#4

Y39

H_D#5

V42

H_D#6

Y41

H_D#7

Y42

H_D#8

P42

H_D#9

U41

H_D#10

R42

H_D#11

T39

H_D#12

T42

H_D#13

T41

H_D#14

R41

H_D#15

T43

H_D#16

W35

H_D#17

AA37

H_D#18

W33

H_D#19

W34

H_D#20

AA36

H_D#21

AA34

H_D#22

AA38

H_D#23

AA35

H_D#24

U38

H_D#25

U36

H_D#26

U35

H_D#27

U33

H_D#28

U34

H_D#29

W38

H_D#30

R33

H_D#31

U37

H_D#32

N34

H_D#33

N33

H_D#34

R34

H_D#35

R35

H_D#36

P35

H_D#37

R39

H_D#38

R37

H_D#39

R38

H_D#40

L37

H_D#41

L39

H_D#42

L38

H_D#43

N36

H_D#44

N38

H_D#45

J39

H_D#46

J38

H_D#47

J37

H_D#48

L42

H_D#49

M42

H_D#50

P41

H_D#51

N41

H_D#52

N40

H_D#53

M40

H_D#54

H40

H_D#55

K42

H_D#56

H41

H_D#57

L41

H_D#58

H43

H_D#59

H42

H_D#60

K41

H_D#61

J40

H_D#62

H39

H_D#63

M43

H_BPRI#

AA41

H_DEFER#

AA40
G42

G41
AL43

AL42

BCLK_FEEDBACK_P

AL41

BCLK_FEEDBACK_N

AK42
AK41

AJ40

H_A20M#

AF41

H_IGNNE#

AH39

H_INIT#

AH42

H_INTR

AF42

H_NMI

AG41

H_SMI#

AH41

H_PWRGOOD

AH43

H_RESET#

H38

H_CPUSLP#

AM33

H_DPSLP#

AN33

H_DPWR#

AM32

H_STPCLK#

AG42

H_DPRSTP#

AN32

2009/02/19 2009/12/31

H_D#0

Y43

H_D#[0..63]

H_BPRI# 4
H_DEFER# 4

T21

PAD

T24

PAD

H_A20M# 4
H_IGNNE# 4
H_INIT# 4
H_INTR 4
H_NMI 4
H_SMI# 4

H_PWRGOOD 5

H_RESET# 4
H_CPUSLP# 5

H_DPSLP# 5
H_DPWR# 5
H_STPCLK# 4

H_DPRSTP# 5,38

Compal Secret Data

Deciphered Date

To +CPU_CORE

H_D#[0..63] 5

2

@

@

1

C21
15P_0402_50V8J

2

1

C25
15P_0402_50V8J

2

CLK_CPU_BCLK
CLK_CPU_BCLK#

Title

Size Document Number Rev

Date: Sheet

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

Compal Electronics, Inc.

MCP79(1/10)-FRONT SIDE BUS

LA-4631P

1

of

742Tuesday, Fe b r u a r y 24, 2009

1.0

5

4

3

2

1

DDR_A_DQS#[0..7]

D D

DDR_A_D[0..63]17,18

C C

B B

DDR_A_DM[0..7]17,18

DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0

DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0 DDR_B_DM0

U4B

AL8

MDQ0_63

AL9

MDQ0_62

AP9

MDQ0_61

AN9

MDQ0_60

AL6

MDQ0_59

AL7

MDQ0_58

AN6

MDQ0_57

AN7

MDQ0_56

AR6

MDQ0_55

AR7

MDQ0_54

AV6

MDQ0_53

AW5

MDQ0_52

AN10

MDQ0_51

AR5

MDQ0_50

AU6

MDQ0_49

AV5

MDQ0_48

AU7

MDQ0_47

AU8

MDQ0_46

AW9

MDQ0_45

AP11

MDQ0_44

AW6

MDQ0_43

AY5

MDQ0_42

AU9

MDQ0_41

AV9

MDQ0_40

AU11

MDQ0_39

AV11

MDQ0_38

AV13

MDQ0_37

AW13

MDQ0_36

AR11

MDQ0_35

AT11

MDQ0_34

AR14

MDQ0_33

AU13

MDQ0_32

AR26

MDQ0_31

AU25

MDQ0_30

AT27

MDQ0_29

AU27

MDQ0_28

AP25

MDQ0_27

AR25

MDQ0_26

AP27

MDQ0_25

AR27

MDQ0_24

AP29

MDQ0_23

AR29

MDQ0_22

AP31

MDQ0_21

AR31

MDQ0_20

AV27

MDQ0_19

AN29

MDQ0_18

AV29

MDQ0_17

AN31

MDQ0_16

AU31

MDQ0_15

AR33

MDQ0_14

AV37

MDQ0_13

AW37

MDQ0_12

AT31

MDQ0_11

AV31

MDQ0_10

AT37

MDQ0_9

AU37

MDQ0_8

AW39

MDQ0_7

AV39

MDQ0_6

AR37

MDQ0_5

AR38

MDQ0_4

AV38

MDQ0_3

AW38

MDQ0_2

AR35

MDQ0_1

AP35

MDQ0_0

AN5

MDQM0_7

AU5

MDQM0_6

AR10

MDQM0_5

AN13

MDQM0_4

AN27

MDQM0_3

AW29

MDQM0_2

AV35

MDQM0_1

AR34

MDQM0_0

MCP79MX-B2 PBGA 1437P

MEMORY

PARTITION 0

MEMORY CONTROL 0A

MDQS0_7_P

MDQS0_7_N

MDQS0_6_P

MDQS0_6_N

MDQS0_5_P

MDQS0_5_N

MDQS0_4_P

MDQS0_4_N

MDQS0_3_P

MDQS0_3_N

MDQS0_2_P

MDQS0_2_N

MDQS0_1_P

MDQS0_1_N

MDQS0_0_P

MDQS0_0_N

MRAS0#
MCAS0#

MWE0#

MBA0_2
MBA0_1
MBA0_0

MA0_14
MA0_13
MA0_12
MA0_11
MA0_10

MA0_9
MA0_8
MA0_7
MA0_6
MA0_5
MA0_4
MA0_3
MA0_2
MA0_1
MA0_0

MCLK0A_2_P
MCLK0A_2_N

MCLK0A_1_P
MCLK0A_1_N

MCLK0A_0_P
MCLK0A_0_N

MCS0A_1#
MCS0A_0#

MODT0A_1
MODT0A_0

MCKE0A_1
MCKE0A_0

DDR_A_DQS[0..7]

AL10
AL11
AR8
AR9
AW7
AW8
AP13
AR13
AV25
AW25
AU30
AU29
AT35
AU35
AU39
AT39

AV17
AP17
AR17

AP23
AP19
AW17

AR23
AU15
AN23
AW21
AN19
AV21
AR22
AU21
AP21
AR21
AN21
AV19
AU19
AT19
AR19

AW33
AV33

M_CLK_DDR1

BA24

M_CLK_DDR#1

AY24

M_CLK_DDR0

BB20

M_CLK_DDR#0

BC20

DDR_CS1_DIMMA#

AT15

DDR_CS0_DIMMA#

AR18

M_ODT1

AP15

M_ODT0

AV15

DDR_CKE1_DIMMA

AU23

DDR_CKE0_DIMMA

AT23

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

DDR_A_BS2
DDR_A_BS1
DDR_A_BS0

DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

DDR_A_DQS#[0..7] 17,18

DDR_A_DQS[0..7] 17,18

12

R40

75_0402_1%

DDR_A_RAS# 17,18
DDR_A_CAS# 17,18
DDR_A_WE# 17,18
DDR_A_BS[0..2] 17,18

DDR_A_MA[0..14] 17,18

T30

T31

M_CLK_DDR0 17,18
M_CLK_DDR#0 17,18

T34

DDR_CS0_DIMMA# 17,18

T35

M_ODT0 17,18

T36

DDR_CKE0_DIMMA 17,18

U4C

DDR_B_D[0..63]19

DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1

DDR_B_DM[0..7]19

DDR_B_D0

DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1

AT4

MDQ1_63

AT3

MDQ1_62

AV2

MDQ1_61

AV3

MDQ1_60

AR4

MDQ1_59

AR3

MDQ1_58

AU2

MDQ1_57

AU3

MDQ1_56

AY4

MDQ1_55

AY3

MDQ1_54

BB3

MDQ1_53

BC3

MDQ1_52

AW4

MDQ1_51

AW3

MDQ1_50

BA3

MDQ1_49

BB2

MDQ1_48

BB5

MDQ1_47

BA5

MDQ1_46

BA8

MDQ1_45

BC8

MDQ1_44

BB4

MDQ1_43

BC4

MDQ1_42

BA7

MDQ1_41

AY8

MDQ1_40

BA9

MDQ1_39

BB10

MDQ1_38

BB12

MDQ1_37

AW12

MDQ1_36

BB8

MDQ1_35

BB9

MDQ1_34

AY12

MDQ1_33

BA12

MDQ1_32

BC32

MDQ1_31

AW32

MDQ1_30

BA35

MDQ1_29

AY36

MDQ1_28

BA32

MDQ1_27

BB32

MDQ1_26

BA34

MDQ1_25

AY35

MDQ1_24

BC36

MDQ1_23

AW36

MDQ1_22

BA39

MDQ1_21

AY40

MDQ1_20

BA36

MDQ1_19

BB36

MDQ1_18

BA38

MDQ1_17

AY39

MDQ1_16

BB40

MDQ1_15

AW40

MDQ1_14

AV42

MDQ1_13

AV41

MDQ1_12

BA40

MDQ1_11

BC40

MDQ1_10

AW42

MDQ1_9

AW41

MDQ1_8

AT40

MDQ1_7

AT41

MDQ1_6

AP41

MDQ1_5

AN40

MDQ1_4

AU40

MDQ1_3

AU41

MDQ1_2

AR41

MDQ1_1

AP42

MDQ1_0

AT5

MDQM1_7

BA2

MDQM1_6

AY7

MDQM1_5

BA11

MDQM1_4

BB34

MDQM1_3

BB38

MDQM1_2

AY43

MDQM1_1

AR42

MDQM1_0

MCP79MX-B2 PBGA 1437P

MEMORY
PARTITION 1

MEMORY CONTROL 1A

MDQS1_7_P

MDQS1_7_N

MDQS1_6_P

MDQS1_6_N

MDQS1_5_P

MDQS1_5_N

MDQS1_4_P

MDQS1_4_N

MDQS1_3_P

MDQS1_3_N

MDQS1_2_P

MDQS1_2_N

MDQS1_1_P

MDQS1_1_N

MDQS1_0_P

MDQS1_0_N

MRAS1#
MCAS1#

MWE1#

MBA1_2
MBA1_1
MBA1_0

MA1_14
MA1_13
MA1_12
MA1_11
MA1_10

MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0

MCLK1A_2_P
MCLK1A_2_N

MCLK1A_1_P
MCLK1A_1_N

MCLK1A_0_P
MCLK1A_0_N

MCS1A_1#
MCS1A_0#

MODT1A_1
MODT1A_0

MCKE1A_1
MCKE1A_0

DDR_B_DQS#[0..7]

DDR_B_DQS[0..7]

AT2
AT1
AY2
AY1
BB6
BA6
BA10
AY11
BB33
BA33
BB37
BA37
BA43
AY42
AT42
AT43

AW16
BA15
BA16

BB29
BB18
BB17

BA29
BA14
AW28
BC28
BA17
BB28
AY28
BA28
AY27
BA27
BA26
BB26
BA25
BB25
BA18

BA42
BB42

BB22
BA22

BA19
AY19

BB14
BB16

BB13
AY15

AY31
BB30

DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_B_BS2
DDR_B_BS1
DDR_B_BS0

DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0

M_CLK_DDR3
M_CLK_DDR#3

M_CLK_DDR2
M_CLK_DDR#2

DDR_CS3_DIMMB#
DDR_CS2_DIMMB#

M_ODT3_DIMMB
M_ODT2_DIMMB

DDR_CKE3_DIMMB
DDR_CKE2_DIMMB

DDR_B_DQS#[0..7] 19

DDR_B_DQS[0..7] 19

DDR_B_RAS# 19
DDR_B_CAS# 19
DDR_B_WE# 19
DDR_B_BS[0..2] 19

DDR_B_MA[0..14] 19

M_CLK_DDR3 19
M_CLK_DDR#3 19

M_CLK_DDR2 19
M_CLK_DDR#2 19

DDR_CS3_DIMMB# 19
DDR_CS2_DIMMB# 19

M_ODT3_DIMMB 19
M_ODT2_DIMMB 19

DDR_CKE3_DIMMB 19
DDR_CKE2_DIMMB 19

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

MCP79(2/10)-MEM PARTS 0 & 1

LA-4631P

1

of

842Tuesday, Fe b r u a r y 24, 2009

1.0

5

4

3

2

1

D D

2

1

8mil

MEM_COMP_VDD

MEM_COMP_GND

8mil

C C

+1.5V

B B

R34 40.2_0402_1%

12

R33 40.2_0402_1%

1 2

C348

2.2U_0402_6.3VM

U4D

AU33

MCLK0B_2_P

AU34

MCLK0B_2_N

BB24

MCLK0B_1_P

BC24

MCLK0B_1_N

BA21

MCLK0B_0_P

BB21

MCLK0B_0_N

AU17

MCS0B_0#

AR15

MCS0B_1#

AN17

MODT0B_0

AN15

MODT0B_1

AV23

MCKE0B_0

AN25

MCKE0B_1

AN41

MEM_COMP_VDD

AM41

MEM_COMP_GND

AA22

GND1

AP12

GND2

G30

GND3

P10

GND4

T10

GND5

T6

GND6

V10

GND7

V34

GND8

W5

GND9

AA39

GND10

AB22

GND11

AB7

GND12

AD22

GND13

AE20

GND14

AF24

GND15

AG24

GND16

AH35

GND17

AK7

GND18

AM28

GND19

AT25

GND20

AP30

GND21

AR36

GND22

AU10

GND23

F28

GND24

BC21

GND25

AY9

GND26

BC9

GND27

D34

GND28

F24

GND29

G32

GND30

H31

GND31

K7

GND32

M38

GND33

M5

GND34

M6

GND35

M7

GND36

M9

GND37

N39

GND38

N8

GND39

P33

GND40

P34

GND41

P37

GND42

P4

GND43

P40

GND44

P7

GND45

R36

GND46

R40

GND47

R43

GND48

R5

GND49

T18

GND50

T20

GND51

AK11

GND52

T24

GND53

T26

GND54

MCP79MX-B2 PBGA 1437P

MEMORY CONTROL 1B

MEMORY CONTROL 0B

+V_DLL_DLCELL_AVDD

MCLK1B_2_P
MCLK1B_2_N

MCLK1B_1_P
MCLK1B_1_N

MCLK1B_0_P
MCLK1B_0_N

MCS1B_0#
MCS1B_1#

MODT1B_0
MODT1B_1

MCKE1B_0
MCKE1B_1

+V_PLL_MCLK

+V_PLL_FSB

MRESET0#

+VDD_MEM1
+VDD_MEM2
+VDD_MEM3
+VDD_MEM4
+VDD_MEM5
+VDD_MEM6
+VDD_MEM7
+VDD_MEM8

+VDD_MEM9
+VDD_MEM10
+VDD_MEM11
+VDD_MEM12
+VDD_MEM13
+VDD_MEM14
+VDD_MEM15
+VDD_MEM16
+VDD_MEM17
+VDD_MEM18
+VDD_MEM19
+VDD_MEM20
+VDD_MEM21
+VDD_MEM22
+VDD_MEM23
+VDD_MEM24
+VDD_MEM25
+VDD_MEM26
+VDD_MEM27
+VDD_MEM28
+VDD_MEM29
+VDD_MEM30
+VDD_MEM31
+VDD_MEM32
+VDD_MEM33
+VDD_MEM34
+VDD_MEM35
+VDD_MEM36
+VDD_MEM37
+VDD_MEM38
+VDD_MEM39
+VDD_MEM40
+VDD_MEM41
+VDD_MEM42
+VDD_MEM43
+VDD_MEM44
+VDD_MEM45

GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64

BA41
BB41

AY23
BA23

BA20
AY20

BC16
BA13

AY16
BC13

BA30
BA31

AH27
AG27
AG28

AY32

AM17
AM19
AM21
AM23
AM25
AM27
AM29
AN16
BC29
AN20
AN24
AT17
AP16
AN22
AP20
AP24
AV16
AR16
AR20
AR24
AW15
AP22
AP18
AU16
AN18
AU24
AT21
AY29
AV24
AU20
AU22
AW27
BC17
AV20
AY17
AY18
AM15
AU18
AY25
AY26
AW19
AW24
BC25
AL30
AM31

T33
T34
T35
T37
T38
T7
T9
U18
U20
U22

+1.5V

R537

1 2

0_0402_5%

+1.5V

C29

+1.5V

197 mA

4.77 A

1

2

10U_0805_10V4Z

2

C35

1

1.05V
This voltage powers the PLLs of DDR2 interfaces.

+V_PLL_CPU

DDR_RST#MRESET0#

C30

4.7U_0603_6.3V6K

2

C36

1

0.1U_0402_16V7K

0.1U_0402_16V7K

C31

4.7U_0603_6.3V6K

2

C37

1

0.1U_0402_16V7K

DDR_RST# 17,18,19

2

2

C33

C32

1

1

0.1U_0402_16V7K

2

2

C38

C39

1

1

0.1U_0402_16V7K

2

C34

1

0.1U_0402_16V7K

0.1U_0402_16V7K

2

2

2

C40

1

0.1U_0402_16V7K

0.1U_0402_16V7K

C349

C41

1

1

0.1U_0402_16V7K

0.1U_0402_16V7K

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

MCP79(3/10)-MEM CNTL 0B&1B

LA-4631P

1

942Tuesday, Fe b r u a r y 24, 2009

1.0

of

5

D D

C C

Express Card

LAN
WLAN

EXP_CLKREQ#23
PEB_PRSNT#23

LAN_CLKREQ#22

WLAN_CLKREQ#24

IEEE1394

Express Card

LAN
WLAN

B B

IEEE1394

+VCCP

1.1VS

+VCCP

1.1VS

PCIE_WAKE#22,23,24,28
PCIE_RX0_P23

PCIE_RX0_N23
PCIE_RX1_P22

PCIE_RX1_N22
PCIE_RX2_P24

PCIE_RX2_N24
PCIE_RX3_P26

PCIE_RX3_N26

R52 0_0402_5%

1 2

2

C54

2.2U_0402_6.3VM

1

430 mA

2

2

C55

C56

0.1U_0402_16V7K

0.1U_0402_16V7K

1

1

2.2U

L3 10NH_LQG15HS10NJ02D_5%_0402~D

1 2

C66

1

2

EXP_CLKREQ#
PEB_PRSNT#

PEC_PRSNT#

WLAN_CLKREQ#

PED_PRSNT#

PEE_PRSNT#

PCIE_WAKE#
PCIE_RX0_P

PCIE_RX0_N
PCIE_RX1_P

PCIE_RX1_N
PCIE_RX2_P

PCIE_RX2_N
PCIE_RX3_P

PCIE_RX3_N

+DVDD_PEX

1

C57

1U_0402_6.3V4Z

2

+V_PLL_PEX

C67

2

2.2U_0402_6.3VM

1

4

U4E

F7

PE0_RX0_P

E7

PE0_RX0_N

D7

PE0_RX1_P

C7

PE0_RX1_N

E6

PE0_RX2_P

F6

PE0_RX2_N

E5

PE0_RX3_P

F5

PE0_RX3_N

E4

PE0_RX4_P

E3

PE0_RX4_N

C3

PE0_RX5_P

D3

PE0_RX5_N

G5

PE0_RX6_P

H5

PE0_RX6_N

J7

PE0_RX7_P

J6

PE0_RX7_N

J5

PE0_RX8_P

J4

PE0_RX8_N

L11

PE0_RX9_P

L10

PE0_RX9_N

L9

PE0_RX10_P

L8

PE0_RX10_N

L7

PE0_RX11_P

L6

PE0_RX11_N

N11

PE0_RX12_P

N10

PE0_RX12_N

N9

PE0_RX13_P

P9

PE0_RX13_N

N7

PE0_RX14_P

N6

PE0_RX14_N

N5

PE0_RX15_P

N4

PE0_RX15_N

C9

PE0_PRSNT_16#

D5

PEB_CLKREQ/GPIO_49#

D9

PEB_PRSNT#

E8

PEC_CLKREQ/GPIO_50#

C10

PEC_PRSNT#

M15

PED_CLKREQ/GPIO_51#

B10

PED_PRSNT#

L16

PEE_CLKREQ/GPIO_16#

L18

PEE_PRSNT/GPIO_46#

M16

PEF_CLKREQ/GPIO_17#

M18

PEF_PRSNT/GPIO_47#

M17

PEG_CLKREQ/GPIO_18#

M19

PEG_PRSNT/GPIO_48#

F17

PE_WAKE#

K9

PE1_RX0_P

J9

PE1_RX0_N

H9

PE1_RX1_P

G9

PE1_RX1_N

F9

PE1_RX2_P

E9

PE1_RX2_N

H7

PE1_RX3_P

G7

PE1_RX3_N

T17

+DVDD0_PEX1

W19

+DVDD0_PEX2

U17

+DVDD0_PEX3

V19

C58

1U_0402_6.3V4Z

161 mA

PE_COMP

12

R53

2.37K_0402_1%

@

+DVDD0_PEX4

W16

+DVDD0_PEX5

W17

+DVDD0_PEX6

W18

+DVDD0_PEX7

U16

+DVDD0_PEX8

T19

+DVDD1_PEX1

U19

+DVDD1_PEX2

T16

+V_PLL_PEX

A11

PEX_CLK_COMP

MCP79MX-B2 PBGA 1437P

PCIE

3

PE0_TX0_P
PE0_TX0_N
PE0_TX1_P
PE0_TX1_N
PE0_TX2_P
PE0_TX2_N
PE0_TX3_P
PE0_TX3_N
PE0_TX4_P
PE0_TX4_N
PE0_TX5_P
PE0_TX5_N
PE0_TX6_P
PE0_TX6_N
PE0_TX7_P
PE0_TX7_N
PE0_TX8_P
PE0_TX8_N
PE0_TX9_P

PE0_TX9_N
PE0_TX10_P
PE0_TX10_N
PE0_TX11_P
PE0_TX11_N
PE0_TX12_P
PE0_TX12_N
PE0_TX13_P
PE0_TX13_N
PE0_TX14_P
PE0_TX14_N
PE0_TX15_P
PE0_TX15_N

PE0_REFCLK_P
PE0_REFCLK_N

PE1_REFCLK_P
PE1_REFCLK_N

PE2_REFCLK_P
PE2_REFCLK_N

PE3_REFCLK_P
PE3_REFCLK_N

PE4_REFCLK_P
PE4_REFCLK_N

PE5_REFCLK_P
PE5_REFCLK_N

PE6_REFCLK_P
PE6_REFCLK_N

PEX_RST0#

PE1_TX0_P

PE1_TX0_N

PE1_TX1_P

PE1_TX1_N

PE1_TX2_P

PE1_TX2_N

PE1_TX3_P

PE1_TX3_N

+AVDD0_PEX1
+AVDD0_PEX2
+AVDD0_PEX3
+AVDD0_PEX4
+AVDD0_PEX5
+AVDD0_PEX6
+AVDD0_PEX7
+AVDD0_PEX8

+AVDD0_PEX9
+AVDD0_PEX10
+AVDD0_PEX11
+AVDD0_PEX12
+AVDD0_PEX13

+AVDD1_PEX1

+AVDD1_PEX2

+AVDD1_PEX3

C5
D4
C4
B4
A4
A3
B3
B2
C1
D1
D2
E1
E2
F2
F3
F4
G3
H4
H3
H2
H1
J1
J2
J3
K2
K3
L4
L3
M4
M3
M2
M1

E11
D11

G11
F11

J11
J10

G13
F13

J13
H13

L14
K14

N14
M14

K11
D8

C8
B8

A8
A7

B7
B6

C6

Y12
AA12
AB12
M12
P12
R12
N12
T12
U12
AC12
AD12
V12
W12

M13
N13
P13

MCP79_PCIE_RST#
PCIE_TX0_P

PCIE_TX0_N
PCIE_TX1_P

PCIE_TX1_N
PCIE_TX2_P

PCIE_TX2_N
PCIE_TX3_P

PCIE_TX3_N

CLK_PCIE_EXPR
CLK_PCIE_EXPR#

CLK_PCIE_LANLAN_CLKREQ#
CLK_PCIE_LAN#

CLK_PCIE_WLAN
CLK_PCIE_WLAN#

CLK_PCIE_1394
CLK_PCIE_1394#

2

C59

0.1U_0402_16V7K

1

PCIE_TX0_P 23
PCIE_TX0_N 23

PCIE_TX1_P 22
PCIE_TX1_N 22

PCIE_TX2_P 24
PCIE_TX2_N 24

PCIE_TX3_P 26
PCIE_TX3_N 26

+AVDD_PEX

2

C60

0.1U_0402_16V7K

1

1

C61

1U_0402_6.3V4Z

2

2

CLK_PCIE_EXPR 23

CLK_PCIE_EXPR# 23

CLK_PCIE_LAN 22
CLK_PCIE_LAN# 22

CLK_PCIE_WLAN 24
CLK_PCIE_WLAN# 24

CLK_PCIE_1394 26
CLK_PCIE_1394# 26

Express Card
LAN
WLAN
IEEE1394

1.2A

1

C62

1U_0402_6.3V4Z

2

1

MCP79_PCIE_RST#

R35

1 2

0_0402_5%

2

C43

0.1U_0402_16V7K

@

1

PCIE_RST# 22,23,24,26

Express Card
LAN
WLAN
IEEE1394

L11

1 2

2

C63

2.2U_0402_6.3VM

1

BLM21PG221SN1D_0805~D

1

C64

10U_0805_10V4Z

2

+VCCP

1.1VS

A A

5

4.7U_0603_6.3V6K

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

MCP79(4/10)-PCI EXPRESS

LA-4631P

1

of

10 42Tuesday, Fe b r u a r y 24, 2009

1.0

5

4

3

2

1

R1301
0_0603_1%

1 2

1

C70

2

0.1U_0402_16V4Z

1 2

1 2

R71 22_0402_5% @

1 2

R83 1K_0402_1%@

1 2

C91 0.1U_0402_16V4Z@

1 2

+3VALW

@

R1302
0_0603_1%

1 2

264 mA

4.7U_0603_6.3V6K

LCD_DDC_CLK 20

LCD_DDC_DATA 20

LVDSAC+ 20
LVDSAC- 20

LVDSA0+ 20
LVDSA0- 20
LVDSA1+ 20
LVDSA1- 20
LVDSA2+ 20
LVDSA2- 20

LVDSBC+ 20
LVDSBC- 20

LVDSB0+ 20
LVDSB0- 20
LVDSB1+ 20
LVDSB1- 20
LVDSB2+ 20
LVDSB2- 20

SCL_DP_MCP 21
SDA_DP_MCP 21

SCL_HDMI_MCP 21
SDA_HDMI_MCP 21

2.2U

+1.05VALW_MAC_R

1

C71

C72

2

0.1U_0402_16V4Z

SLP_RMGT#14

SLP_MCP79_MAC#28

+1.05VALW_MAC

12

R1306
0_0603_1%

R57 0_0603_1%

1 2

4.7U_0603_6.3V6K

PHY_25MHZ 22

PHY_25MHZ

@

1

C309

2

0.1U_0402_16V4Z

Signal : TXD0_R
Strap: Networking select
Strapped Value : 0: MII 1: RGMII
Description : Selects an MII interface or an RGMII interface for MAC.

@

1 2

R1308
0_0402_5%

@

R1311

0_0402_5%

1.1VALW

+1.05VALW

+3.3VALW_MAC_REF

R163

LCD_DDC_CLK
LCD_DDC_DATA

+1.05VS_PLL

C176

R1307
20K_0402_1%

12

+3VS +3VS

12

R186

2.7K_0402_5%

C175

4.7U_0603_6.3V6K

+3VALW

12

@

1

C656

0.01U_0402_25V7K

2

12

2.7K_0402_5%

L13

1 2

10NH_LQG15HS10NJ02D _5%_0402~D

1

2

2.2U_0402_6.3VM

+1.05VALW

20 mil

AO3416_SOT23

13

D

Q67

2

G

S

+1.05VALW_MAC

20 mil

2

G

12

R63
10K_0402_5%

1.1VS

+VCCP

1.1VALW_MAC

1.1VALW_MAC

+1.05VALW_MAC

1

C657

0.1U_0402_16V4Z

2

+3VALW +3VALW

12

R1309
10K_0402_5%

R1310

13

D

Q69
2N7002_SOT23

S

0_0402_5%

1 2

@

C658

G

2

0.01U_0402_25V7K

1

2

20 mil

Q68

S

AO3413_SOT23

D

1 3

+3.3VALW_MAC

20 mil

+3.3VALW_MAC

MCP79_AUX-

MCP79_AUX+

R54

@

R55

2.2U_0402_6.3VM

22K_0402_5%

+1.8VS

+3VS

+VCCP

12

R1263

10K_0402_5%

12

R1264

1 2

1 2

C83 10U_0805_10V4Z@

16 mA

1

C88

2

10K_0402_5%

@

1K_0402_5%

C76

4.7U_0603_6.3V6K

1 2

1.1VS

2.2U_0402_6.3VM

12

R1265

9 mA

+3.3VALW_MAC

TI_PRIORITY21

MCP_DP_CBL_DET21

MCP79_LCD_PWM20

MCP79_ENBKL28
MCP79_ENVDD20,28

MCP79_DP3+21
MCP79_DP3-21

MCP79_DP2+21
MCP79_DP2-21
MCP79_DP1+21
MCP79_DP1-21
MCP79_DP0+21
MCP79_DP0-21

MCP79_AUX+21
MCP79_AUX-21

HDMI_HPD21
MCP_DP_HPD21

1

C89

2

2.2U_0402_6.3VM

12

R1266

10K_0402_5%

R69

+1.05VS_PLL

R80 0_0603_1%

1 2

2.2U

R81

1 2

95 mA

12

R1267

10K_0402_5%

10K_0402_5%

1 2

49.9_0402_1%
R70 49.9_0402_1%

+1.05VS_PLL

R79 0_0402_5%

0_0603_1%

0.1U_0402_16V4Z

12

12

R1269

R1268

10K_0402_5%

RXD0
RXD1
RXD2
RXD3
RXCLK
RXCTL

1 2

R61

RGMII_INT

+V_DUAL_MACPLL

+MII_COMP_VDD

1 2

66 mA

TI_PRIORITY
MCP_DP_CBL_DET

MCP79_LCD_PWM
MCP79_ENBKL
MCP79_ENVDD

MCP79_DP3+
MCP79_DP3-

MCP79_DP2+
MCP79_DP2­MCP79_DP1+
MCP79_DP1­MCP79_DP0+
MCP79_DP0-

MCP79_AUX+
MCP79_AUX-

1 2

190 mA

1 2

C842.2U_0402_6.3VM

12

C850.1U_0402_16V4Z

+3VS_PLL_HDMI

C864.7U_0603_6.3V6K

12
12

R821K_0402_1%

1 2

12

C90

@

10K_0402_5%

47K_0402_5%

MII_COMP_GND

+1.8VS_IFP

C870.1U_0402_16V4Z
C4480.1U_0402_16V4Z

HDMI_RSET

HDMI_VPROBE

U4F

C23

RGMII_RXD0

B23

RGMII_RXD1

E24

RGMII_RXD2

A24

RGMII_RXD3

A23

RGMII_RXC/MII_RXCLK

C22

RGMII_RXCTL/MII_RXDV

F23

MII_RXER/GPIO_36

B26

MII_COL/GPIO_20/MSMB_DATA

B22

MII_CRS/GPIO_21/MSMB_CLK

J22

RGMII_INTR/GPIO_35

T23

+V_DUAL_MACPLL

C27

MII_COMP_VDD

B27

MII_COMP_GND

C39

RGB_DAC_RSET

B38

RGB_DAC_VREF

E36

TV_DAC_RSET

A35

TV_DAC_VREF

T28

+V_VPLL

U27

+V_PLL_CORE

C38

XTALIN_TV

D38

XTALOUT_TV

E16

GPIO_6/FERR/IGPU_GPIO_6#

B15

GPIO_7/NFERR/IGPU_GPIO_7#

G39

LCD_BKL_CTL/GPIO_57

E37

LCD_BKL_ON/GPIO_59

F40

LCD_PANEL_PWR/GPIO_58

D35

HDMI_TXC_P/ML0_LANE3_P

E35

HDMI_TXC_N/ML0_LANE3_N

G35

HDMI_TXD0_P/ML0_LANE2_P

F35

HDMI_TXD0_N/ML0_LANE2_N

F33

HDMI_TXD1_P/ML0_LANE1_P

G33

HDMI_TXD1_N/ML0_LANE1_N

J33

HDMI_TXD2_P/ML0_LANE0_P

H33

HDMI_TXD2_N/ML0_LANE0_N

D43

DP_AUX_CH0_P

C43

DP_AUX_CH0_N

C31

HPLUG_DET2/GPIO_22

F31

HPLUG_DET3

M27

+VDD_IFPA

M26

+VDD_IFPB

M28

+V_PLL_IFPAB

M29

+V_PLL_HDMI

T25

+VDD_HDMI

J31

HDMI_RSET

J30

HDMI_VPROBE

MCP79MX-B2 PBGA 1437P

LAN

DACS

FLAT

PANEL

+3.3V_DUAL_RMGT1
+3.3V_DUAL_RMGT2

+V_DUAL_RMGT1
+V_DUAL_RMGT2

MII_VREF

RGMII_TXD0
RGMII_TXD1
RGMII_TXD2
RGMII_TXD3

RGMII_TXC/MII_TXCLK

RGMII_TXCTL/MII_TXEN

RGMII_MDC

RGMII_MDIO

RGMII_PWRDWN/GPIO_37

BUF_25MHZ

MII_RESET#

+V_RGB_DAC

+V_TV_DAC

DDC_CLK0

DDC_DATA0

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_BLUE
RGB_DAC_HSYNC
RGB_DAC_VSYNC

TV_DAC_RED

TV_DAC_GREEN

TV_DAC_BLUE
TV_DAC_HSYNC/GPIO_44
TV_DAC_VSYNC/GPIO_45

IFPA_TXC_P
IFPA_TXC_N

IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N

IFPB_TXC_P
IFPB_TXC_N

IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N

DDC_CLK2/GPIO_23

DDC_DATA2/GPIO_24

DDC_CLK3

DDC_DATA3
IFPAB_RSET

IFPAB_VPROBE

264 mA

J24
K24

U23
V23

E28
B24

C24
C25
D25
D24
C26

D21
C21

G23
E23

J23
J32

K32
B31

A31
B39

A39
B40
A40
A41

A36
B36
C36
D36
C37

B35
C35

B32
A32
D32
C32
D33
C33
B34
C34

L31
K31

J29
H29
L29
K29
L30
K30
N30
M30

C30
B30

D31
E31

E32
G31

+3.3VALW_MAC_R

TXCLK_R

PHY_25MHZ_R

LCD_DDC_CLK
LCD_DDC_DATA

LVDSAC+
LVDSAC-

LVDSA0+
LVDSA0­LVDSA1+
LVDSA1­LVDSA2+
LVDSA2-

LVDSBC+
LVDSBC-

LVDSB0+
LVDSB0­LVDSB1+
LVDSB1­LVDSB2+
LVDSB2-

SCL_DP_MCP
SDA_DP_MCP

SCL_HDMI_MCP
SDA_HDMI_MCP

IFPAB_RSET
IFPAB_VPROBE

C69

R67 10K_0402_5%

R1262 10K_0402_5%

1K_0402_5%

D D

C C

B B

A A

1.1VALW_MAC

+1.05VALW_MAC

12

L4

BLM18AG121SN1D_0603

1

C75

2

MCP79_ENVDD

12

R1279

RGMII_INT
RXCTL
RXCLK
RXD3
RXD2
RXD1
RXD0

Security Classification

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY COMPAL ELECTRONIC S, INC. NEITH ER THIS SHEE T NOR THE IN FORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CO NSENT OF CO MPAL ELECTR ONICS, INC.

3

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

MCP79(5/10)-LAN,RGB,TV,LVD

Size Document Number Rev

2

Date: Sheet

LA-4631P

1

11 42Tuesday, Febru ar y 24, 2009

1.0

of

5

4

3

+3VS

2

1

GPIO

R191

R192

R193

X76L02@

1 2

8.2K_0402_5%

D D

R94 8.2K_0402_5%

+3VS

C C

+3VS

B B

1 2

R95 8.2K_0402_5%

1 2

R92 8.2K_0402_5%

1 2

R98 8.2K_0402_5%

1 2

R97 8.2K_0402_5%

1 2

R99 8.2K_0402_5%

1 2

R124 8.2K_0402_5%

1 2

R138 8.2K_0402_5%

1 2

R140 8.2K_0402_5%

1 2

R147 8.2K_0402_5%

1 2

SERIRQ28

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
HB_PWR_EN
PCI_REQ#4

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_TRDY#

SERIRQ

U4G

T2

PCI_REQ0#

V9

PCI_REQ1/FANRPM2#

T3

PCI_REQ2#/GPIO_40/RS232_DSR#

U9

PCI_REQ3#/GPIO_38/RS232_CTS#

T4

PCI_REQ4#/GPIO_52/RS232_SIN#

AC3

PCI_AD0

AE10

PCI_AD1

AC4

PCI_AD2

AE11

PCI_AD3

AB3

PCI_AD4

AC6

PCI_AD5

AB2

PCI_AD6

AC7

PCI_AD7

AC8

PCI_AD8

AA2

PCI_AD9

AC9

PCI_AD10

AC10

PCI_AD11

AC11

PCI_AD12

AA1

PCI_AD13

AA5

PCI_AD14

Y5

PCI_AD15

W3

PCI_AD16

W6

PCI_AD17

W4

PCI_AD18

W7

PCI_AD19

V3

PCI_AD20

W8

PCI_AD21

V2

PCI_AD22

W9

PCI_AD23

U3

PCI_AD24

W11

PCI_AD25

U2

PCI_AD26

U5

PCI_AD27

U1

PCI_AD28

U6

PCI_AD29

T5

PCI_AD30

U7

PCI_AD31

P2

PCI_INTW#

N3

PCI_INTX#

N2

PCI_INTY#

N1

PCI_INTZ#

Y3

PCI_TRDY#

AD11

PCI_CLKRUN/GPIO_42#

AE2

LPC_DRQ1/GPIO_19#

AE1

LPC_DRQ0#

AE6

LPC_SERIRQ

U24

GND65

U26

GND66

U39

GND67

U4

GND68

U8

GND69

V16

GND70

V17

GND71

V18

GND72

V20

GND73

V22

GND74

V24

GND75

V26

GND76

V27

GND77

V28

GND78

V33

GND79

V37

GND80

V4

GND81

V40

GND82

V7

GND83

W20

GND84

W22

GND85

W24

GND86

W36

GND87

W40

GND88

W43

GND89

Y16

GND90

Y17

GND91

Y18

GND92

Y19

GND93

Y20

GND94

Y22

GND95

Y24

GND96

Y25

GND97

MCP79MX-B2 PBGA 1437P

PCI

GND

PCI_GNT2#/GPIO_41/RS232_DTR#

PCI_GNT3#/GPIO_39/RS232_RTS#

PCI_GNT4#/GPIO_53/RS232_SOUT#

PCI_PERR#/GPIO_43/RS232_DCD#

LPC_PWRDWN#/GPIO_54/EXT_NMI#

LPC

PCI_GNT0#

PCI_GNT1/FANCTL2#

PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#

PCI_DEVSEL#

PCI_FRAME#

PCI_IRDY#

PCI_PAR

PCI_SERR#
PCI_STOP#

PCI_PME/GPIO_30#

PCI_RESET0#
PCI_RESET1#

PCI_CLK0
PCI_CLK1
PCI_CLK2

PCI_CLKIN

LPC_FRAME#

LPC_RESET0#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_CLK0

GND98

GND99
GND100
GND101
GND102
GND103
GND104
GND105
GND106
GND107
GND108
GND109
GND110
GND111
GND112
GND113
GND114
GND115
GND116
GND117
GND118
GND119
GND120
GND121
GND122
GND123
GND124
GND125
GND126
GND127
GND128
GND129
GND130

R3
U10
R4
U11
P3

AA3
AA6
AA11
W10

PCI_DEVSEL#

AA9

PCI_FRAME#

Y4

PCI_IRDY#

AA10
Y1

PCI_PERR#

AB9

PCI_SERR#

AA7

PCI_STOP#

Y2
T1

R10
R11

R6

R96 0_0402_5%

R7

PCI_CLK2

R8

PCI_CLKIN

R9

R_LPC_FRAME#

AD4
AE12

AE5

R_LPC_AD0

AD3

R_LPC_AD1

AD2

R_LPC_AD2

AD1

R_LPC_AD3

AD5

LPC_CLK0_R

AE9

Y26
Y27
AB18
H34
AB20
AB21
AB23
AB24
AB25
AB26
AB27
AB28
AB34
AB37
AB4
AB40
AC22
AC36
AC40
AB33
AC5
AD16
AD17
AD18
AD19
AD20
AD24
AD25
AD26
AD27
AD28
AD33
AD34

R194

X76L01@

1 2

1 2

R104

@

1

C96
10P_0402_50V8J

2

8.2K_0402_5%

1 2

@

X76L01@

1 2

1 2

8.2K_0402_5%

8.2K_0402_5%

R196

R195

X76L02@

1 2

1 2

8.2K_0402_5%

8.2K_0402_5%

X76L01@X76L02@

R1488.2K_0402_5%

1 2

R1508.2K_0402_5%

1 2

R1588.2K_0402_5%

1 2

R1888.2K_0402_5%

1 2

R1898.2K_0402_5%

1 2

R1908.2K_0402_5%

1 2

PCI_PME# HAS INTERNAL PULLUP

T9

1

C95

@

2

10P_0402_50V8J

1 2

33_0402_5%

R105 22_0402_5%

1 2

R107 22_0402_5%

1 2

R108 22_0402_5%

1 2

R109 22_0402_5%

1 2

22_0402_5%

LPC_CLK0

R110

1 2

+3VS

R100

1 2

22_0402_5%

R101

22_0402_5%

PLT_RST# 24,28

Hynix 1G

Samsung 1G

LPC_FRAME#

LPC_AD0 24,28
LPC_AD1 24,28
LPC_AD2 24,28
LPC_AD3 24,28

LPC_CLK0 24,28

39

1
(R192)

0
(R195)

HDA_SDATA_OUT (MSB)
LPC_FRAME# (LSB)

00: Boot ROM l o cated on LPC bus
01: Boot ROM l o cated on PCI bus
10: Boot ROM l o cated on SPI bus
(SPI_CS0)
11: Boot ROM l o cated on SPI bus
(SPI_CS1)

12

R106
10K_0402_5%

41

0
(R194)

1
(R191)

LPC_FRAME# 24,28

53

0
(R196)

0
(R196)

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

MCP79(6/10)-PCI & LPC

LA-4631P

1

12 42Tuesday, Fe b r u a r y 24, 2009

1.0

of

5

4

3

2

1

D D

SATA HDD

ESATA

C C

SATA_A0_TXP20
SATA_A0_TXN20

SATA_A0_RXN20
SATA_A0_RXP20

SATA_A1_TXP29
SATA_A1_TXN29

SATA_A1_RXN29
SATA_A1_RXP29

SATA_A0_TXP
SATA_A0_TXN

SATA_A0_RXN
SATA_A0_RXP

SATA_A1_TXP
SATA_A1_TXN

SATA_A1_RXN
SATA_A1_RXP

1.1VS

+VCCP

12

L8
10NH_LQG1 5 HS10NJ02D_5%_0402~D

81 mA

C100

1.1VS

+VCCP

R115

4.7U_0603_6.3V6K

0_0603_1%

1.1VS

53 mA

+VCCP

L9

BLM18AG121SN1D_0603

1 2

136 mA

C108

+AVDD_SATA

1

2

B B

A A

2

C101

1

10U_0805_10V4Z

2.2U

+V_PLL_SATA

2.2U_0402_6.3VM

2

C109

1

2.2U_0402_6.3VM

+DVDD_SATA

2

1

C110

0.1U_0402_16V7K

2

C111

1

2

1

0.1U_0402_16V7K

2

C106

1

C452

0.1U_0402_16V7K

2

1

2.2U_0402_6.3VM

SATA_TERMP

12

R117

2.49K_0402_1%

C107

0.1U_0402_16V7K

U4H

AJ7

SATA_A0_TX_P

AJ6

SATA_A0_TX_N

AJ5

SATA_A0_RX_N

AJ4

SATA_A0_RX_P

AJ11

SATA_A1_TX_P

AJ10

SATA_A1_TX_N

AJ9

SATA_A1_RX_N

AK9

SATA_A1_RX_P

AK2

SATA_B0_TX_P

AJ3

SATA_B0_TX_N

AJ2

SATA_B0_RX_N

AJ1

SATA_B0_RX_P

AM4

SATA_B1_TX_P

AL3

SATA_B1_TX_N

AL4

SATA_B1_RX_N

AK3

SATA_B1_RX_P

AN1

SATA_C0_TX_P

AM1

SATA_C0_TX_N

AM2

SATA_C0_RX_N

AM3

SATA_C0_RX_P

AP3

SATA_C1_TX_P

AP2

SATA_C1_TX_N

AN3

SATA_C1_RX_N

AN2

SATA_C1_RX_P

E12

SATA_LED#

AE16

+V_PLL_SATA

AF19

+DVDD0_SATA1

AG16

+DVDD0_SATA2

AG17

+DVDD0_SATA3

AG19

+DVDD0_SATA4

AH17

+DVDD1_SATA1

AH19

+DVDD1_SATA2

AJ12

+AVDD0_SATA1

AN11

+AVDD0_SATA2

AK12

+AVDD0_SATA3

AK13

+AVDD0_SATA4

AL12

+AVDD0_SATA5

AM11

+AVDD0_SATA6

AM12

+AVDD0_SATA7

AN12

+AVDD0_SATA8

AL13

+AVDD0_SATA9

AN14

+AVDD1_SATA1

AL14

+AVDD1_SATA2

AM13

+AVDD1_SATA3

AM14

+AVDD1_SATA4

AE3

SATA_TERMP

MCP79MX-B 2 P B G A 1437P

USBSATA

USB_OC2/GPIO_27/MGPIO#
USB_OC3/GPIO_28/MGPIO#

USB0_P

USB0_N

USB1_P

USB1_N

USB2_P

USB2_N

USB3_P

USB3_N

USB4_P

USB4_N

USB5_P

USB5_N

USB6_P

USB6_N

USB7_P

USB7_N

USB8_P

USB8_N

USB9_P

USB9_N

USB10_P
USB10_N

USB11_P
USB11_N

USB_OC0/GPIO_25#
USB_OC1/GPIO_26#

+V_PLL_USB

+3.3V_DUAL_USB1
+3.3V_DUAL_USB2
+3.3V_DUAL_USB3
+3.3V_DUAL_USB4

USB_RBIAS_GND

GND131
GND132
GND133
GND134
GND135
GND136
GND137
GND138
GND139
GND140
GND141
GND142
GND143
GND144
GND145
GND146
GND147
GND148
GND149
GND150
GND151
GND152
GND153
GND154
GND155
GND156
GND157
GND158
GND159
GND160

C29
D29

C28
D28

A28
B28

F29
G29

K27
L27

J26
J27

F27
G27

D27
E27

K25
L25

H25
J25

F25
G25

K23
L23

L21
K21
J21
H21

L28

G26
H27
J28
K28

A27
AD35

AD37
AD38
AE22
AE24
AE39
AE4
AD6
AF16
AF17
AF18
AF20
AF22
AF26
AF27
AF28
AF33
AF34
AF37
AF40
AG18
AG20
AG22
AG26
AG36
AG40
AH18
AH20
AH22
AH24

USB20_P0
USB20_N0

USB20_P1
USB20_N1

USB20_P2
USB20_N2

USB20_P3
USB20_N3

USB20_P4
USB20_N4

USB20_P5
USB20_N5

USB20_P6
USB20_N6

USB20_P7
USB20_N7

USB20_P8
USB20_N8

USB_OC#0
USB_OC#1
USB_OC#2
PM_EXTTS#0_1

+V_PLL_USB

200 mA

+3.3V_DUAL_U SB

USB_RBIAS

R116
806_0402_1%

1 2

USB20_P0 27
USB20_N0 27

USB20_P1 29
USB20_N1 29

USB20_P2 29
USB20_N2 29

USB20_P3 23
USB20_N3 23

USB20_P4 27
USB20_N4 27

USB20_P5 27
USB20_N5 27

USB20_P6 24
USB20_N6 24

USB20_P7 24
USB20_N7 24

T26
T27

+3VALW

R113

0_0603_1%

2

C104

1

USB0
USB1
USB2
Express Card
Camera
BlueTooth
WWAN
WLAN

USB_OC#0 27
USB_OC#1 29
USB_OC#2 29
PM_EXTTS#0_1 19

C105

4.7U_0603_6.3V6K

2.2U_0402_6.3VM

18 mA

2

C97

1

2.2U_0402_6.3VM

2

1

C98

0.1U_0402_16V7K

+3VS

L7
BLM18AG121SN1D_0603

1 2

C99

4.7U_0603_6.3V6K

USB_OC#0
USB_OC#2
USB_OC#1

R78 10K_0402_5%

1 2

R103 10K_0402_5%

1 2

R111 10K_0402_5%

1 2

+5VALW

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH OUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

MCP79(7/10)-SATA & USB

LA-4631P

1

of

13 42Tuesday, F ebruary 24, 2009

1.0

5

@

R118

U8

10K_0402_5%

HDA_BITCLK

D D

1

@

C112

0.1U_0402_16V4Z

2

@

CLKIN

ACZ_SDIN025

NC
NC
SS

EMI_HD_IN_ D

1
2
8
3

7

VDD

6

CLKOUT

5

SSON

4

GND

ASM3P623S00BF-08TR_TSSOP8

1.1VS

+VCCP

12

L10
10NH_LQG15HS10NJ02D _5%_0402~D

+V_PLL_NV

1

1

C82

2

PLACE 0.1UF N EA R AE18 and AE17 BALL

C C

EC_SCI#28
EC_SMI#28

LID_SW#28

DPRSLPVR38

PWRBTN#28

+RTCVCC

Close to RAM door

B B

X1

1 2

1

25MHZ 12PF 30PPM
C128
10P_0402_50V8J

2

A A

R152

1 2

49.9K_0402_1%

NO SHORT PAD

1U_0402_6.3V4Z

JCMOS1

1 2

C126

1 2

10P_0402_50V8J

+RTCVCC

@

@

1

C129

2

XTALOUT

32.768KHZ 1TJS125BJ4A421P

C123

C81

2

0.1U_0402_10V6K

0.1U_0402_10V6K

EC_KBRST#28

1 2

R141 49.9K_0402_1%

R151 10K_0402_5%@

+3VALW

RTC_RST#

EC_RSMRST#28
MCP_PWRGD28

C127

1 2

15P_0402_50V8J

X2

2

IN

NC

3

OUT

NC

XTAOUT_RTC

12

12P_0402_50V8J
C130

C454

220P_0402_50V7K

R197

@

12

0_0402_5%

ACZ_SDIN0

+3VALW

92 mA

2

C124

C125

1

2.2U_0402_6.3VM

4.7U_0603_6.3V6K

EC_GA2028

R159 10K_0402_5%
R160 10K_0402_5%

1 2

R534 0_0402_5%~D

1
4

@

EC_KBRST#

R149 0_0402_5%

PWRBTN#

12

VGATE28,38

T25

PAD

T16

PAD

T28

PAD

12
12

XTALIN
XTALOUT_R

XTALIN_RTC

R549

0_0402_5%~D

1 2

EC_GA20 EC_KBRST#

1

2

220P_0402_50V7K

EMI_HD_IN

12

12
12

12

2

1

2.2U_0402_6.3VM

EC_GA20

INTRUDER#

1 2

XTAOUT_RTC_R

@

C453

4

+3VS+3VS

R119

10K_0402_5%@

@

R122

10K_0402_5%

U4I

G15

HDA_SDATA_IN0

C11510P_0402_50V8J @

J14

HDA_SDATA_IN1/GPIO_2/PS2_KB_CLK

C11610P_0402_50V8J @

J15

HDA_SDATA_IN2/GPIO_3/PS2_KB_DATA

C11710P_0402_50V8J @

R130

49.9_0402_1%

A15

HDA_PULLDN_COMP

+1.05VS_PLL

AE18

+V_PLL_NV_H

T27

+V_PLL_XREF_XS

AE17

+V_PLL_SP_SPREF

L24

GPIO_1/PWRDN_OK/SPI_CS1

L26

GPIO_12/SUS_STAT/ACCLMTR_EXT_TRIG#

K13

A20GATE

L13

KBRDRSTIN#

C19

SIO_PME#

C18

EXT_SMI/GPIO_32#

B20

INTRUDER#

M25

LID#

M24

LLB#

M22

CPU_DPRSLPVR

C16

PWRBTN#

D16

RSTBTN#

C20

RTC_RST#

D20

PWRGD_SB

E20

PS_PWRGD

C17

CPU_VLD

E19

JTAG_TDI

F19

JTAG_TDO

J19

JTAG_TMS

J18

JTAG_TRST#

G19

JTAG_TCK

A16

XTALIN

B16

XTALOUT

A19

XTALIN_RTC

B19

XTALOUT_RTC

MCP79MX-B2 PBGA 1437P

A20GATE,KBRDRSTIN*, RI* & EXTSMI*

1

2

HAVE INTERNAL PULLUPS

HDA

MISC

3

+V_DUAL_HDA1
+V_DUAL_HDA2

HDA_SDATA_OUT

HDA_BITCLK

HDA_RESET#

HDA_DOCK_EN/GPIO_4/PS2_MS_CLK#

HDA_DOCK_RST/GPIO_5/PS2_MS_DATA#

HDA_SYNC

SLP_S3#

SLP_RMGT#

SLP_S5#

THERM_DIODE_P
THERM_DIODE_N

MCP_VID0/GPIO_13
MCP_VID1/GPIO_14
MCP_VID2/GPIO_15

SPKR

SMB_CLK0

SMB_DATA0

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT/GPIO_64#

FANRPM0/GPIO_60

FANCTL0/GPIO_61

FANRPM1/GPIO_63

FANCTL1/GPIO_62

CPUVDD_EN

SPI_CS0/GPIO_10
SPI_CLK/GPIO_11

SPI_DI/GPIO_8

SPI_DO/GPIO_9

SUS_CLK/GPIO_34

BUF_SIO_CLK

TEST_MODE_EN

PKG_TEST

SPKR
0 = User Mode Boot Init table
1 = Safe Mode Boot Init table
Suggest use user mode.

J16
K16

F15

E15

K15
L15

K17
L17

G17
J17
H17

B11
C11

L20
M20
M21

C13

L19
K19
G21
F21
M23

B12
A12
D12
C12

D17

C14
D13
C15
B14

B18

AE7

K22
L22

EMI_HD_IN

MCP_SPKR

EC_LID_OUT#

SUS_CLK_R

2

C455

1

HDA_SDOUT

R127

0_0402_5%

HDA_RESET#
HDA_SYNC

MCP_CORE_VID0 36
MCP_CORE_VID1 36
MCP_CORE_VID2 36

HD Audio Codec

MCP_SMB_CLK
MCP_SMB_DATA

R153

10K_0402_5% @

R156

0_0402_5%

R_ACIN

2 1

12

R164
1K_0402_1%

+3VALW

20 mA

2

C113

C114

1

0.1U_0402_16V7K

0.1U_0402_16V7K

HDA_BITCLK

C118

1

12

R128

12

2

10K_0402_5%

10P_0402_50V8J

+3VALW +3VALW

R142

MCP_SPKR 25

+3VALW

VR_ON

12

ENABLE +1.05V POWER

R296
0_0402_5%

EC_LID_OUT# 28

D4SDMK0340L-7-F

12

1 2

VR_ON 28,38

ACIN 28,32,33

T32 PAD

T33 PAD

2

4.7U_0603_6.3V6K

C119

1

2

10P_0402_50V8J

@

C120

12

@

R143

1 2

2.2K_0402_5%

1 2

R125 22_0402_5%

1 2

R126 22_0402_5%

R131

1 2

22_0402_5%

1

2

10P_0402_50V8J

R134

22K_0402_5%

+3VS

R144

1 2

2.2K_0402_5%

2.2K_0402_5%

12

R154
332K_0402_1%

12

R161

@

EC

R165

@

MCP_SMB_CLK
MCP_SMB_DATA

R166

@

For Audio code use

ACZ_SDOUT
ACZ_BITCLK

+3VALW

12

R129

10K_0402_5%

R132

1 2

R133

22K_0402_5%

12

12

12

R135

22K_0402_5%

1 2

2.2K_0402_5%

+3VALW

10K_0402_5%

10K_0402_5%

22_0402_5%

1

@

C121
10P_0402_50V8J

2

@

12

R146

+3VALW+3VALW

12

R155

@

12

R162

1 2

8
7
6
5

AT24C16AN-10SI-2.7_SO8@

12

R136

22K_0402_5%

2.7K_0402_5%

MEM_SMBCLK
MEM_SMBDATA
SMB_ALERT#

10K_0402_5%

10K_0402_5%

C131

@

0.1U_0402_16V4Z

U9

VCC
WP
SCL
SDA

12

@

R145

10K_0402_5%

ACZ_SDOUT 25
ACZ_BITCLK 25

1

A0

2

A1

3

A2

4

GND

1

ACZ_RST# 25
ACZ_SYNC 25

PM_SLP_S3# 28
SLP_RMGT# 11
PM_SLP_S5# 28

MCP_SPKR

2

3

1

HDCP 2-WIRE ROM

MCP_SMB_CLK 24
MCP_SMB_DATA 24
MEM_SMBCLK 18,19
MEM_SMBDATA 18,19

@

D3
PJDLC05_SOT23

+3VS

12

R137
10K_0402_5%

@

12

R139
10K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY COMPAL ELECTRONIC S, INC. NEITH ER THIS SHEE T NOR THE IN FORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CO NSENT OF CO MPAL ELECTR ONICS, INC.

3

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

2

Date: Sheet

MCP79(8/10)-HDA & MISC

LA-4631P

1

of

14 42Tuesday, Febru ar y 24, 2009

1.0

5

0.75V ~ 1.05 V

+1.0VS

1

1

C132

C133

2

2

D D

C C

B B

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

1

C137

C136

2

2

C152

1

2

C159

1

0.1U_0402_16V7K

C138

10U_0805_10V4Z

4.7U_0603_6.3V6K

2

C153

1

0.1U_0402_16V7K

0.1U_0402_16V7K

2

2

C160

C161

1

1

0.1U_0402_16V7K

1

C134

2

0.1U_0402_16V7K

1

+

C135

2

330U_D2E_2.5VM_R9

0.22U_0402_6.3V6K

1

1

C140

C139

2

2

4.7U_0603_6.3V6K

2

2

C154

1

1

0.1U_0402_16V7K

2

C162

1

0.1U_0402_16V7K

C155

1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

C156

1

0.1U_0402_16V7K

0.1U_0402_16V7K

2

2

C164

C163

1

1

0.1U_0402_16V7K

0.1U_0402_16V7K

RTC Battery

+COINCELL

RTCVREF

A A

12

3

2

D17

1

BAT54CW_SOT323~D

R536
1K_0402_5%~D

+RTCVCC

1

C541
1U_0603_10V4Z~D

2

+RTCVCC

C249

4

11.6 A 1.25A

2

1

C142

C141

1

2

1U_0402_6.3V4Z

C157

0.1U_0402_16V7K

2

C158

1

0.1U_0402_16V7K

0.1U_0402_16V7K

2

C165

1

0.1U_0402_16V7K

3 mA

C177

C248

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

2

1

AA25
AC23

U25
AH12
AG10

AG5

Y21

Y23
AA16
AA26
AA27
AA28
AC16
AC17
AC18
AC19
AC20
AC21
AA17
AC24
AC25
AC26
AC27
AC28
AD21
AD23

W27

V25
AA18
AE19
AE21
AE23
AE25
AE26
AE27
AE28

AF10
AF11

AA19

AF2

AF21
AF23
AF25

AF3

AF4

AF7
AH23

AF9
AA20
AG11
AG12
AG21
AG23
AG25

AG3
AG4

AA21

AG6
AG7
AG8
AG9

AH1
AH10
AH11

W26

AH2
AA23

W28
AH25
AH21

AH3
AH4
AH5
AH6
AH7
AH9

AA24

W21

W23

W25

AF12

A20

2

1

0.1U_0402_16V7K

U4J

+VDD_CORE1
+VDD_CORE2
+VDD_CORE3
+VDD_CORE4
+VDD_CORE5
+VDD_CORE6
+VDD_CORE7
+VDD_CORE8
+VDD_CORE9
+VDD_CORE10
+VDD_CORE11
+VDD_CORE12
+VDD_CORE13
+VDD_CORE14
+VDD_CORE15
+VDD_CORE16
+VDD_CORE17
+VDD_CORE18
+VDD_CORE19
+VDD_CORE20
+VDD_CORE21
+VDD_CORE22
+VDD_CORE23
+VDD_CORE24
+VDD_CORE25
+VDD_CORE26
+VDD_CORE27
+VDD_CORE28
+VDD_CORE29
+VDD_CORE30
+VDD_CORE31
+VDD_CORE32
+VDD_CORE33
+VDD_CORE34
+VDD_CORE35
+VDD_CORE36
+VDD_CORE37
+VDD_CORE38
+VDD_CORE39
+VDD_CORE40
+VDD_CORE41
+VDD_CORE42
+VDD_CORE43
+VDD_CORE44
+VDD_CORE45
+VDD_CORE46
+VDD_CORE47
+VDD_CORE48
+VDD_CORE49
+VDD_CORE50
+VDD_CORE51
+VDD_CORE52
+VDD_CORE53
+VDD_CORE54
+VDD_CORE55
+VDD_CORE56
+VDD_CORE57
+VDD_CORE58
+VDD_CORE59
+VDD_CORE60
+VDD_CORE61
+VDD_CORE62
+VDD_CORE63
+VDD_CORE64
+VDD_CORE65
+VDD_CORE66
+VDD_CORE67
+VDD_CORE68
+VDD_CORE69
+VDD_CORE70
+VDD_CORE71
+VDD_CORE72
+VDD_CORE73
+VDD_CORE74
+VDD_CORE75
+VDD_CORE76
+VDD_CORE77
+VDD_CORE78
+VDD_CORE79
+VDD_CORE80
+VDD_CORE81

+VBAT

MCP79MX-B2 PBGA 1437P

POWER

3

+VTT_CPU1
+VTT_CPU2
+VTT_CPU3
+VTT_CPU4
+VTT_CPU5
+VTT_CPU6
+VTT_CPU7
+VTT_CPU8

+VTT_CPU9
+VTT_CPU10
+VTT_CPU11
+VTT_CPU12
+VTT_CPU13
+VTT_CPU14
+VTT_CPU15
+VTT_CPU16
+VTT_CPU17
+VTT_CPU18

+VTT_CPU20
+VTT_CPU21
+VTT_CPU22
+VTT_CPU23
+VTT_CPU24
+VTT_CPU25
+VTT_CPU26
+VTT_CPU27
+VTT_CPU28
+VTT_CPU29
+VTT_CPU30
+VTT_CPU31
+VTT_CPU32
+VTT_CPU33
+VTT_CPU34
+VTT_CPU35
+VTT_CPU36
+VTT_CPU37
+VTT_CPU38
+VTT_CPU39
+VTT_CPU40
+VTT_CPU41
+VTT_CPU42
+VTT_CPU43
+VTT_CPU44
+VTT_CPU45
+VTT_CPU46
+VTT_CPU47
+VTT_CPU48
+VTT_CPU49
+VTT_CPU50
+VTT_CPU51
+VTT_CPU52
+VTT_CPU53

+VTT_CPUCLK

+3.3V_1
+3.3V_2
+3.3V_3
+3.3V_4
+3.3V_5
+3.3V_6
+3.3V_7
+3.3V_8

+VDD_AUXC1
+VDD_AUXC2
+VDD_AUXC3

+3.3V_DUAL1
+3.3V_DUAL2
+3.3V_DUAL3
+3.3V_DUAL4

R32
AC32
E40
J36
N32
T32
U32
V32
W32
P31
AF32
AE32
AH32
AJ32
AK31
AK32
AD32
AL31

B41
B42
C40
C41
C42
D39
D40
D41
E38
E39
F37
F38
F39
G36
G37
G38
H35
H37
J34
J35
K33
K34
K35
L32
L33
L34
M31
M32
M33
N31
P32
Y32
AA32
AB32

AG32

AD10
AE8
AB10
AD9
Y10
AB11
AA8
Y9

T21
U21
V21

G18
H19
J20
K20

2

C143

1

0.1U_0402_16V7K

2

C166

1

0.1U_0402_16V7K

+VDD_AUXC

C171

0.1U_0402_16V7K

+3.3V_DUAL

C173

4.7U_0603_6.3V6K

2

C144

1

0.1U_0402_16V7K

+3.3V_MCP79

2

C167

1

0.1U_0402_16V7K

2

1

2

C145

1

0.1U_0402_16V7K

2

C168

1

139 mA

2

C172

0.1U_0402_16V7K

1

33 mA

2

C174

0.1U_0402_16V7K

1

368 mA

0.1U_0402_16V7K

2

1

2

C146

0.1U_0402_16V7K

2

C169

1

0.1U_0402_16V7K

1 2

1 2

80mil

2

C147

1

+3VS

R168
0_0402_5%

R170
0_0402_5%

0.1U_0402_16V7K

R167
0_0603_1%

C170

+1.05VALW

4.7U_0603_6.3V6K

+3VALW

1

C148

2

1U_0402_6.3V4Z

1.1VALW

1

C149

C150

2

1U_0402_6.3V4Z

4.7U_0603_6.3V6K

1

+VCCP

1

C151

2

10U_0805_10V4Z

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

MCP79(9/10)-POWER&RTC Batt

LA-4631P

1

of

15 42Thursday, Fe br ua ry 19, 2009

1.0

5

4

3

2

1

D D

C C

B B

A A

U4K

AH26

GND161

AH33

GND162

AH34

GND163

AH37

GND164

AH38

GND165

AJ39

GND166

AJ8

GND167

AK10

GND168

AK33

GND169

AK34

GND170

AK37

GND171

AK4

GND172

AK40

GND173

AL36

GND174

AL40

GND175

AL5

GND176

AM10

GND177

AM16

GND178

AM18

GND179

AM20

GND180

AM22

GND181

AM24

GND182

AM26

GND183

AM30

GND184

AM34

GND185

AM35

GND186

AM37

GND187

AM38

GND188

AM5

GND189

AM6

GND190

AM7

GND191

AM9

GND192

AP26

GND193

AN28

GND194

AN30

GND195

AN39

GND196

AN4

GND197

Y7

GND198

AP10

GND199

AU26

GND200

AP14

GND201

AU14

GND202

AP28

GND203

AP32

GND204

AP34

GND205

AP36

GND206

AP37

GND207

AP4

GND208

AP40

GND209

AP7

GND210

AW23

GND211

AR28

GND212

AR32

GND213

AR40

GND214

AT10

GND215

AR12

GND216

AT13

GND217

AT29

GND218

AT33

GND219

AT6

GND220

AT7

GND221

AT9

GND222

AY21

GND223

AY22

GND224

L12

GND225

AU12

GND226

AU28

GND227

AP33

GND228

AU32

GND229

AR30

GND230

AU36

GND231

AU38

GND232

AU4

GND233

G28

GND234

F20

GND235

AV28

GND236

AV32

GND237

AV36

GND238

AV4

GND239

AV7

GND240

AW11

GND241

G20

GND242

AR43

GND243

AW43

GND244

AY10

GND245

AV12

GND246

AY30

GND247

AY33

GND248

AY34

GND249

AY37

GND250

AY38

GND251

AY41

GND252

MCP79MX-B2 PBGA 1437P

GND

GND253
GND254
GND255
GND256
GND257
GND258
GND259
GND260
GND261
GND262
GND263
GND264
GND265
GND266
GND267
GND268
GND269
GND270
GND271
GND272
GND273
GND274
GND275
GND276
GND277
GND278
GND279
GND280
GND281
GND282
GND283
GND284
GND285
GND286
GND287
GND288
GND289
GND290
GND291
GND292
GND293
GND294
GND295
GND296
GND297
GND298
GND299
GND300
GND301
GND302
GND303
GND304
GND305
GND306
GND307
GND308
GND309
GND310
GND311
GND312
GND313
GND314
GND315
GND316
GND317
GND318
GND319
GND320
GND321
GND322
GND323
GND324
GND325
GND326
GND327
GND328
GND329
GND330
GND331
GND332
GND333
GND334
GND335
GND336
GND337
GND338
GND339
GND340
GND341
GND342
GND343

AV40
BA1
BA4
AW31
AY6
L35
BC33
BC37
BC41
AY14
BC5
C2
D10
D14
D15
D18
D19
D22
D23
D26
D30
D37
D6
E13
E17
E21
E25
E29
E33
F12
F16
F32
F8
G10
G12
G14
G16
BC12
G22
G24
AW20
G34
G4
G43
G6
G8
H11
H15
AW35
H23
AN8
G40
J12
J8
K10
K12
K18
K26
K37
K4
K40
K8
AU1
L40
L43
L5
M10
M34
M35
M37
Y28
Y33
Y34
Y35
Y37
Y38
AB17
AB16
AN26
AD7
M11
AA4
AB19
AY13
P11
Y6
T11
V11
Y11
AH16
T22

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

MCP79(10/10)-GND

LA-4631P

1

16 42Thursday, Fe br ua ry 19, 2009

1.0

of

5

4

3

2

1

VDDQ
VDDQ
VDDQ
VDDQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

ODT
CK#

CKE

CS#
RAS#
CAS#

WE#

RESET#

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

CK

BA0
BA1
BA2

+1.5V

B10
C2
E3
E10

A3
A10
D8
G3
G9
K2
K10
M2
M10

M_ODT0

G2

M_CLK_DDR0

F8

M_CLK_DDR#0

G8

DDR_CKE0_DIMMA

G10
J3

DDR_A_BS1

K9

DDR_A_BS2

J4
H3

DDR_A_RAS#

F4

DDR_A_CAS#DDR_A_MA7

G4

DDR_A_WE#

H4

DDR_RST#

N3
B3

B9
C10
D2
D10
A2
A9
B2
F3
F9
D9
J2
J10
L2
L10
N2
N10

DDR_A_DQS28
DDR_A_DQS#28

DDR_A_D[16..23]8

DDR_A_DM28

+V_DDR_MCH_REF+V_DDR_MCH_REF +V_DDR_MCH_REF +V_DDR_MCH_REF

330U_D2_2.5VY_R15M

1

C180

C178

+

2

DDR_A_D21
DDR_A_D18
DDR_A_D17
DDR_A_D19
DDR_A_D22
DDR_A_D16 DDR_A_D33
DDR_A_D20 DDR_A_D53
DDR_A_D23

1 2

R172 240_0402_5%~D

DDR_A_MA0
DDR_A_MA2

DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7

DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

10U_0603_6.3V6M~D

C181

1

1

2

2

U10

DDR_A_D1
DDR_A_D7
DDR_A_D0
DDR_A_D6
DDR_A_D4
DDR_A_D3
DDR_A_D5
DDR_A_D2

M_ODT08,18
M_CLK_DDR08,18
M_CLK_DDR#08,18

DDR_A_BS08,18
DDR_A_BS18,18
DDR_A_BS28,18

DDR_A_RAS#8,18
DDR_A_CAS#8,18
DDR_A_WE#8,18
DDR_RST#9,18,19

C4

DQS

D4

DQS#

B4

DQ0

C8

DQ1

C3

DQ2

C9

DQ3

E4

DQ4

E9

DQ5

D3

DQ6

E8

DQ7

A8

NU/TDQS#

B8

DM/TDQS

H9

ZQ

E2

VREFDQ

J9

VREFCA

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC#

N4

A13

J8

NC

F10

NC

H2

NC

F2

NC

H10

NC

A1

NC

N8

NC

A11

NC

A4

NC

N1

NC

N11

NC

H5TQ1G83A F P-G7C FBGA 78P

X76@

M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_CS0_DIMMA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_RST#

DDR_A_DQS08
DDR_A_DQS#08

DDR_A_D[0..7]8

D D

DDR_A_DM08

1 2

R171 240_0402_5%~D

DDR_A_MA0
DDR_A_MA1 DDR_A_BS0
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5 DDR_CS0_DIMMA#
DDR_A_MA6

DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

C C

DDR_A_MA14 DDR_A_MA14 DDR_A_MA14DDR_A_MA14

DDR_A_MA[0..14]8,18

DDR_CKE0_DIMMA8,18

B B

DDR_CS0_DIMMA#8,18

10U_0603_6.3V6M~D

U11

C4

DQS

D4

DQS#

B4

DQ0

C8

DQ1

C3

DQ2

C9

DQ3

E4

DQ4

E9

DQ5

D3

DQ6

E8

DQ7

A8

NU/TDQS#

B8

DM/TDQS

H9

ZQ

E2

VREFDQ

J9

VREFCA

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC#

N4

A13

J8

NC

F10

NC

H2

NC

F2

NC

H10

NC

A1

NC

N8

NC

A11

NC

A4

NC

N1

NC

N11

NC

H5TQ1G83A F P-G7C FBGA 78P

X76@

10U_0603_6.3V6M~D

C184

C182

1

1

2

2

10U_0603_6.3V6M~D

+1.5V +1.5V +1.5V

+1.5V+1.5V

+1.5V

VDDQ
VDDQ
VDDQ
VDDQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

ODT

CKE
BA0

BA1
BA2

CS#
RAS#
CAS#

WE#

RESET#

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

C185

C247

B10
C2
E3
E10

A3
A10
D8
G3
G9
K2
K10
M2
M10

G2
F8

CK

G8

CK#

G10
J3

K9
J4

H3
F4
G4
H4
N3

B3
B9
C10
D2
D10
A2
A9
B2
F3
F9
D9
J2
J10
L2
L10
N2
N10

1U_0402_6.3V6K~D

C186

2

1

1U_0402_6.3V6K~D

C253

2

1

DDR_A_D[32..39]8

M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_CS0_DIMMA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_RST#

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

C187

2

2

1

1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

C599

2

2

1

1

DDR_A_DQS48
DDR_A_DQS#48

C188

C251

DDR_A_DM48

1U_0402_6.3V6K~D

2

1

1U_0402_6.3V6K~D

2

1

DDR_A_D39
DDR_A_D34
DDR_A_D32
DDR_A_D35
DDR_A_D36

DDR_A_D37
DDR_A_D38

1 2

R173 240_0402_5%~D

DDR_A_MA0
DDR_A_MA1DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

C189

C190

C191

2

2

1

1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

C256

C255

C250

2

2

1

1

C4
D4

B4
C8
C3
C9

E4

E9
D3

E8

A8

B8
H9

E2

J9

K4

L8

L4

K3

L9

L3
M9
M3
N9
M4
H8
M8

K8
N4

J8

F10

H2

F2

H10

A1
N8

A11

A4
N1

N11

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

C192

2

2

1

1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

C254

2

2

1

1

U12

DQS
DQS#

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

NU/TDQS#
DM/TDQS
ZQ

VREFDQ
VREFCA

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

H5TQ1G83A F P-G7C FBGA 78P

X76@

+V_DDR_MCH_REF

C195

1

2

VDDQ
VDDQ
VDDQ
VDDQ

RAS#
CAS#

WE#

RESET#

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

C197

C196

1

1

2

2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

ODT

CKE

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

CK

CK#

BA0
BA1
BA2

CS#

0.1U_0402_16V4Z~D

B10
C2
E3
E10

A3
A10
D8
G3
G9
K2
K10
M2
M10

G2
F8
G8
G10

J3
K9
J4

H3
F4
G4
H4
N3

B3
B9
C10
D2
D10
A2
A9
B2
F3
F9
D9
J2
J10
L2
L10
N2
N10

C198

1

2

DDR_A_DQS68
DDR_A_DQS#68

DDR_A_D[48..55]8

M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_CS0_DIMMA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_RST#

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C199

C200

1

2

DDR_A_DM68

0.1U_0402_16V4Z~D
C201

1

1

2

2

DDR_A_D54
DDR_A_D51
DDR_A_D49
DDR_A_D50
DDR_A_D52
DDR_A_D48

DDR_A_D55

1 2

R174 240_0402_5%~D

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C202

0.1U_0402_16V4Z~D
C204

C203

1

1

2

2

U13

C4

DQS

D4

DQS#

B4

DQ0

C8

DQ1

C3

DQ2

C9

DQ3

E4

DQ4

E9

DQ5

D3

DQ6

E8

DQ7

A8

NU/TDQS#

B8

DM/TDQS

H9

ZQ

E2

VREFDQ

J9

VREFCA

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC#

N4

A13

J8

NC

F10

NC

H2

NC

F2

NC

H10

NC

A1

NC

N8

NC

A11

NC

A4

NC

N1

NC

N11

NC

H5TQ1G83A F P-G7C FBGA 78P

X76@

0.1U_0402_16V4Z~D

1

2

VDDQ
VDDQ
VDDQ
VDDQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

ODT
CK#

CKE

CS#
RAS#
CAS#

WE#

RESET#

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

CK

BA0
BA1
BA2

B10
C2
E3
E10

A3
A10
D8
G3
G9
K2
K10
M2
M10

M_ODT0

G2

M_CLK_DDR0

F8

M_CLK_DDR#0

G8

DDR_CKE0_DIMMA

G10

DDR_A_BS0

J3

DDR_A_BS1

K9

DDR_A_BS2

J4

DDR_CS0_DIMMA#

H3

DDR_A_RAS#

F4

DDR_A_CAS#

G4

DDR_A_WE#

H4

DDR_RST#

N3
B3

B9
C10
D2
D10
A2
A9
B2
F3
F9
D9
J2
J10
L2
L10
N2
N10

Place close to MEM Place the end of the DDR3

M_CLK_DDR0

3.3P_0402_50V8C~D

C193

1

A A

M_CLK_DDR#0

2

5

12

R175
30_0402_1%~D

M_CLK_DDR0_TERM

12

R176
30_0402_1%~D

+0.75VS

C252

C194

0.1U_0402_10V7K~D

1

2

0.1U_0402_10V7K~D

1

2

4

Second

MAIN

Vendor
Samsung
Hynix

Package
(9*11)
(8*11.5)

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

Samsung DDR3(1066): SA00002L60L (K4B1G0846D-HCF8 FBGA 82P )
Hynix DDR3 (1066): SA00002PO0L (H5TQ1G83AFP-G7C FBGA 78P)

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

DDRIII-Memory Down (Top)

LA-4631P

1

17 42Tuesday, Feb ru ar y 24, 2009

1.0

of

5

4

3

2

1

U14

DDR_A_D10
DDR_A_D13
DDR_A_D11
DDR_A_D8
DDR_A_D9
DDR_A_D14
DDR_A_D12
DDR_A_D15

1K_0402_5%~D@

AT24C02BN-SH-T_SO8~D

C4

DQS

D4

DQS#

B4

DQ0

C8

DQ1

C3

DQ2

C9

DQ3

E4

DQ4

E9

DQ5

D3

DQ6

E8

DQ7

A8

NU/TDQS#

B8

DM/TDQS

H9

ZQ

E2

VREFDQ

J9

VREFCA

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC#

N4

A13

J8

NC

F10

NC

H2

NC

F2

NC

H10

NC

A1

NC

N8

NC

A11

NC

A4

NC

N1

NC

N11

NC

H5TQ1G83A F P-G7C FBGA 78P

X76@

M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA
DDR_A_BS0

@

U18

1

A0

2

A1

3

A2

4

GND

VCC
SCL

SDA

8
7

WP

6
5

+3VS

DDR_A_DQS18
DDR_A_DQS#18

DDR_A_D[8..15]8

D D

DDR_A_DM18

1 2

R177 240_0402_5%~D

DDR_A_MA0
DDR_A_MA1 DDR_A_BS0
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5 DDR_CS0_DIMMA#
DDR_A_MA6

DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

C C

DDR_A_MA14 DDR_A_MA14 DDR_A_MA14 DDR_A_MA14

DDR_A_MA[0..14]8,17

M_ODT08,17
M_CLK_DDR08,17
M_CLK_DDR#08,17

DDR_CKE0_DIMMA8,17

B B

A A

DDR_A_BS08,17

R181

1K_0402_5%~D@

12

12

R182

+1.5V

B10

VDDQ

C2

VDDQ

E3

VDDQ

E10

VDDQ

A3

VDD

A10

VDD

D8

VDD

G3

VDD

G9

VDD

K2

VDD

K10

VDD

M2

VDD

M10

VDD

G2

ODT

F8

CK

G8

CK#

G10

CKE

J3

BA0

K9

BA1

J4

BA2

H3

CS#

F4

RAS#

G4

CAS#

H4

WE#

N3

RESET#

B3

VSSQ

B9

VSSQ

C10

VSSQ

D2

VSSQ

D10

VSSQ

A2

VSS

A9

VSS

B2

VSS

F3

VSS

F9

VSS

D9

VSS

J2

VSS

J10

VSS

L2

VSS

L10

VSS

N2

VSS

N10

VSS

DDR_A_BS18,17
DDR_A_BS28,17

DDR_CS0_DIMMA#8,17

DDR_A_RAS#8,17
DDR_A_CAS#8,17
DDR_A_WE#8,17
DDR_RST#9,17,19

C221

1 2

@

0.1U_0402_16V4Z~D

MEM_SMBCLK
MEM_SMBDATA

DDR_A_DQS38
DDR_A_DQS#38

DDR_A_D[24..31]8

M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA

DDR_A_BS1
DDR_A_BS2

DDR_A_RAS#
DDR_A_CAS#DDR_A_MA7
DDR_A_WE#
DDR_RST#

MEM_SMBCLK 14,19

MEM_SMBDATA 14,19

DDR_A_D27
DDR_A_D30
DDR_A_D26
DDR_A_D25
DDR_A_D31
DDR_A_D28
DDR_A_D24
DDR_A_D29

DDR_A_DM38

1 2

R178 240_0402_5%~D

+V_DDR_MCH_REF+V_DDR_MCH_REF +V_DDR_MCH_REF +V_DDR_MCH_REF

DDR_A_MA0
DDR_A_MA2

DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7

DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_BS1
DDR_A_BS2
DDR_CS0_DIMMA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_RST#

+0.75VS

C647

C4
D4

B4
C8
C3
C9

E4

E9
D3

E8

A8

B8
H9

E2

J9

K4

L8

L4

K3

L9

L3
M9
M3
N9
M4
H8
M8

K8
N4

J8

F10

H2

F2

H10

A1
N8

A11

A4
N1

N11

+V_DDR_MCH_REF

2.2U_0603_6.3V6K~D

C205

1

2

0.1U 50V K X7R 0603

0.1U 50V K X7R 0603
C648

1

1

2

2

U15

DQS
DQS#

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

NU/TDQS#
DM/TDQS
ZQ

VREFDQ
VREFCA

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

H5TQ1G83A F P-G7C FBGA 78P

X76@

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D

C207

C206

C603

C208

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C604

C605

1

1

2

2

+1.5V +1.5V +1.5V

VDDQ
VDDQ
VDDQ
VDDQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

ODT

CK#
CKE

BA0
BA1
BA2

CS#
RAS#
CAS#

WE#

RESET#

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

1

2

B10
C2
E3
E10

A3
A10
D8
G3
G9
K2
K10
M2
M10

G2
F8

CK

G8
G10

J3
K9
J4

H3
F4
G4
H4
N3

B3
B9
C10
D2
D10
A2
A9
B2
F3
F9
D9
J2
J10
L2
L10
N2
N10

C209

1

2

C606

1

2

M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_CS0_DIMMA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_RST#

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C211

C210

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C607

C608

1

2

DDR_A_DQS58
DDR_A_DQS#58

DDR_A_D[40..47]8

DDR_A_DM58

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C212

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C651

1

1

2

2

DDR_A_D42
DDR_A_D41
DDR_A_D43
DDR_A_D47
DDR_A_D46
DDR_A_D40
DDR_A_D44
DDR_A_D45

1 2

R179 240_0402_5%~D

DDR_A_MA0
DDR_A_MA1DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

0.1U_0402_16V4Z~D
C214

C213

1

1

2

2

0.1U_0402_16V4Z~D

@

C653

C652

1

1

2

2

U16

C4
D4

B4
C8
C3
C9

E4

E9
D3

E8

A8

B8
H9

E2

J9

K4

L8

L4

K3

L9

L3
M9
M3
N9
M4
H8
M8

K8
N4

J8

F10

H2

F2

H10

A1
N8

A11

A4
N1

N11

H5TQ1G83A F P-G7C FBGA 78P

X76@

0.1U_0402_16V4Z~D

DDR3 Terminations

DDR_CS0_DIMMA#

DDR_A_WE#

DDR_A_MA12

DDR_A_BS1

DDR_A_MA10

DDR_A_BS2

DDR_A_BS0

DDR_A_MA0

0.1U_0402_16V4Z~D

DDR_A_MA4

DDR_A_MA1

DQS
DQS#

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

NU/TDQS#
DM/TDQS
ZQ

VREFDQ
VREFCA

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

36_0404_4P2R_5%~D

36_0404_4P2R_5%~D

36_0404_4P2R_5%~D

36_0404_4P2R_5%~D

36_0404_4P2R_5%~D

36_0404_4P2R_5%~D

RESET#

+0.75VS

RP5

1 4
2 3

RP7

1 4
2 3

RP9

1 4
2 3

RP11

1 4
2 3

RP13

1 4
2 3

RP15

1 4
2 3

VDDQ
VDDQ
VDDQ
VDDQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

ODT

CKE

RAS#
CAS#

WE#

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

CK#

BA0
BA1
BA2

CS#

B10
C2
E3
E10

A3
A10
D8
G3
G9
K2
K10
M2
M10

G2
F8

CK

G8
G10

J3
K9
J4

H3
F4
G4
H4
N3

B3
B9
C10
D2
D10
A2
A9
B2
F3
F9
D9
J2
J10
L2
L10
N2
N10

DDR_A_DQS78
DDR_A_DQS#78

DDR_A_D[56..63]8

M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_CS0_DIMMA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_RST#

RP6

1 4
2 3

36_0404_4P2R_5%~D

RP8

1 4
2 3

36_0404_4P2R_5%~D

RP10

1 4
2 3

36_0404_4P2R_5%~D

RP12

1 4
2 3

36_0404_4P2R_5%~D

RP14

1 4
2 3

36_0404_4P2R_5%~D

RP16

1 4
2 3

36_0404_4P2R_5%~D

DDR_A_DM78

R180 240_0402_5%~D

DDR_A_RAS#DDR_A_CAS#
M_ODT0DDR_CKE0_DIMMA

DDR_A_MA2
DDR_A_MA3

DDR_A_MA6
DDR_A_MA8

DDR_A_MA5
DDR_A_MA9

DDR_A_MA11
DDR_A_MA14

DDR_A_MA7
DDR_A_MA13

1 2

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_D58
DDR_A_D61
DDR_A_D59
DDR_A_D60
DDR_A_D63
DDR_A_D57
DDR_A_D62
DDR_A_D56

U17

C4

DQS

D4

DQS#

B4

DQ0

C8

DQ1

C3

DQ2

C9

DQ3

E4

DQ4

E9

DQ5

D3

DQ6

E8

DQ7

A8

NU/TDQS#

B8

DM/TDQS

H9

ZQ

E2

VREFDQ

J9

VREFCA

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC#

N4

A13

J8

NC

F10

NC

H2

NC

F2

NC

H10

NC

A1

NC

N8

NC

A11

NC

A4

NC

N1

NC

N11

NC

H5TQ1G83A F P-G7C FBGA 78P

X76@

+0.75VS

1U_0402_6.3V6K~D

C215

2

1

1U_0402_6.3V6K~D

2

1

Place decaps close end termination resistors, one decap for 4 resistors

C216

B10

VDDQ

C2

VDDQ

E3

VDDQ

E10

VDDQ

A3

VDD

A10

VDD

D8

VDD

G3

VDD

G9

VDD

K2

VDD

K10

VDD

M2

VDD

M10

VDD

M_ODT0

G2

ODT

M_CLK_DDR0

F8

CK

M_CLK_DDR#0

G8

CK#

DDR_CKE0_DIMMA

G10

CKE

DDR_A_BS0

J3

BA0

DDR_A_BS1

K9

BA1

DDR_A_BS2

J4

BA2

DDR_CS0_DIMMA#

H3

CS#

DDR_A_RAS#

F4

RAS#

DDR_A_CAS#

G4

CAS#

DDR_A_WE#

H4

WE#

DDR_RST#

N3

RESET#

B3

VSSQ

B9

VSSQ

C10

VSSQ

D2

VSSQ

D10

VSSQ

A2

VSS

A9

VSS

B2

VSS

F3

VSS

F9

VSS

D9

VSS

J2

VSS

J10

VSS

L2

VSS

L10

VSS

N2

VSS

N10

VSS

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

2

C218

C217

1

1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

2

C220

C219

1

1

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRIII-Memory Down (Bottom)

LA-4631P

1

18 42Tuesday, Feb ru ar y 24, 2009

1.0

of

5

4

3

2

1

+1.5V+1.5V +V_DDR_MCH_REF

JDIMM1

1

VREF_DQ

3

DDR_B_D0
DDR_B_D1

DDR_B_DM0

D D

C C

B B

A A

DDR_CKE2_DIMMB8

DDR_B_BS28

M_CLK_DDR28
M_CLK_DDR#28

DDR_B_BS08
DDR_B_WE#8

DDR_B_CAS#8

DDR_CS3_DIMMB#8

+3VS

0.1U_0402_16V4Z~D
C242

C241

1

2

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D18

DDR_B_D19
DDR_B_D24

DDR_B_D25
DDR_B_DM3
DDR_B_D26

DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3

DDR_B_MA1

M_CLK_DDR#2
DDR_B_MA10 DDR_B_BS1

DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_B_MA13

DDR_CS3_DIMMB#

T18

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49
DDR_B_DQS#6

DDR_B_DQS6
DDR_B_D50

DDR_B_D51

+3VS

DDR_B_D56
DDR_B_D57

12

DDR_B_DM7
DDR_B_D58

R184

DDR_B_D59

10K_0402_5%~D

2.2U_0603_6.3V6K~D

1

2

+0.75VS

10K_0402_5%~D

12

R185

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

GND2

FOX_AS0A626-U4SN-7F~D

VSS
DQ4
DQ5
VSS

DQS0#

DQS0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

RESET#

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

CKE1

VDD

VDD

VDD

VDD

VDD

CK1

CK1#

VDD

BA1

RAS#

VDD
ODT0

VDD
ODT1

VDD

VREF_CA

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

EVENT#

SDA

SCL

VTT

BOSS1
BOSS2

A15
A14

A11

A7
A6

A4
A2

A0

S0#

NC

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

+V_DDR_MCH_REF

DDR_B_D4
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR_B_DM1

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA0
M_CLK_DDR3M_CLK_DDR2

M_CLK_DDR#3

DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2_DIMMB
M_ODT3_DIMMB

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63
PM_EXTTS#_R

MEM_SMBDATA
MEM_SMBCLK

+0.75VS

DDR3 SO-DIMM/Standard Type

5

4

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

C222

C223

1

1

2

2

DDR_RST#

2

0.1U_0402_16V4Z~D

B

1

C347

2

0.1U_0402_16V4Z~D

C235

1

2

PM_EXTTS#0_1 13

C236

+5VALW

1 2

C

E

3 1

1

2

R510

4.7K_0402_5%

Q38

MMBT3904_SOT23

+V_DDR_MCH_REF

2.2U_0603_6.3V6K~D

+1.5V

15.4K_0402_1%

12

R511

15.4K_0402_1%

12
@

R512

T17

0_0402_5%~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DDR_CKE3_DIMMB 8

M_CLK_DDR3 8
M_CLK_DDR#3 8

DDR_B_BS1 8
DDR_B_RAS# 8

DDR_CS2_DIMMB# 8
M_ODT2_DIMMB 8

M_ODT3_DIMMB 8

R187

1 2

0_0402_5%~D

R169

R183

1 2

MEM_SMBDATA 14,18

MEM_SMBCLK 14,18

3

+V_DDR_MCH_REF+V_DDR_MCH_REF_R

+3VALW

12

2.7K_0402_5%

+1.5V

R509
1K_0402_5%

1 2

DDR_RST# 9,17,18

Place close to SO-DIMM

+1.5V

13

D

Q5

2

2N7002_SOT23

G

S

Place close to JDIMM pin 203 and 204

2

+0.75VS

C237

@

C224

C231

10U_0603_6.3V6M~D

330U_D2_2.5VY_R15M

1

C225

1

+

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C232

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

C239

C238

2

2

1

1

+1.5V

12

12

DDR_B_D[0..63]8

DDR_B_DQS[0..7]8

DDR_B_DQS#[0..7]8

DDR_B_DM[0..7]8

DDR_B_MA[0..14]8

1U_0402_6.3V6K~D

C227

C226

1

2

0.1U_0402_16V4Z~D
C234

C233

1

2

1U_0402_6.3V6K~D

C240

2

1

R27
1K_0402_1%

+V_DDR_MCH_REF

R28
1K_0402_1%

1U_0402_6.3V6K~D

C228

1

2

0.1U_0402_16V4Z~D

1

2

1U_0402_6.3V6K~D

2

1

+V_DDR_MCH_REF

1U_0402_6.3V6K~D

C229

1

2

2.2U_0402_6.3VM

2.2U_0402_6.3VM

C230

1

1

2

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRIII SO-DIMM SLOT

LA-4631P

19 42Tuesday, Feb ru ar y 24, 2009

1

of

1.0

A

B

C

D

E

LCD

JLVDS1

51

G11

50
48
46

R556 47K_0402_5%

1 1

0.1U_0402_16V7K~N

MCP79_ENVDD11,28

LCD_VCC_TEST_EN28

MCP79_ENVDD

CH751H-40PT_SOD323-2

LCD_VCC_TEST_EN

+3VS

W=60mils W=60mils

1

C273

2

D6

@

2 1

R211

12

0_0402_5%

5

AOZ1320CI-04_SOT23-6

12

R210
10K_0402_1%

U21

IN6OUT
EN3NC

GND

GND

1
4
2

Change from 10K to 100k - 0102.

2 2

+LCDVDD

1

2

C274

1

C275

4.7U_0805_6.3V6K~N

0.1U_0402_16V7K~N

2

LCD_DDC_DATA11

LCD_TST

1

C600
100P_0402_50V

2

+3VALW

LCD_DET#28

LCD_DDC_DATA

1 2

LCD_DET#

R289

1 2

0_0402_5%

INVT_PWM28

D29

1

INVT_PWM DISPOFF#

2

Place D29 close to JLVDS1

CM1213-02SR_SOT143-4

INVT_PWM

VN

CH1

LCD_TST28

LVDSA0+11
LVDSA1-11

LVDSA2+11
LVDSAC-11

LVDSB0+11
LVDSB1-11

LVDSB2+11
LVDSBC-11

4

VP

3

CH2

BKOFF#28

MCP79_LCD_PWM11

+LCDVDD +3VS

EDID_DATA_LCD
LVDSA0+

LVDSA2+
LVDSAC-

LVDSB0+
LVDSB1-

LVDSB2+
LVDSBC-

INVPWR_B+

+3VALW

BKOFF#

MCP79_LCD_PWM

44
42

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10

8
6
4
2

I-PEX_20439-040E-02

D7

SDMK0340L-7-F SOD-323

@

10_0402_5%

49

G9

G10

47

G7

G8

45

G5

G6

43

G3

G4
G2

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

+LCDVDD

41

G1

39

39

37

37
35
33
31
29
27
25
23
21
19
17
15
13
11

EDID_CLK_LCDLCD_TST

35

LVDSA0-

33
31

LVDSA1+LVDSA1-

29

LVDSA2-

27
25

LVDSAC+

23

LVDSB0-

21
19

LVDSB1+

17

LVDSB2-

15
13

LVDSBC+

11
9

9

DISPOFF#

7

7

5

5

INVPWR_B+

3

3

1

1

LVDSA0- 11
LVDSA1+ 11

LVDSA2- 11
LVDSAC+ 11

LVDSB0- 11
LVDSB1+ 11

LVDSB2- 11
LVDSBC+ 11

need swap DISPOFF# to pin 36 on Pannel side.

1 2

L12

FBMA-L11-201209-121LMA50T

W=60mils

LCD_DDC_CLK

R2840_0402_5%

12

B+

LCD_DDC_CLK 11

X01 change JLVDS connect signal (for layout)

+3VS

12

R212

4.7K_0402_5%

DISPOFF#

21

INVT_PWM

R215

12

1

C276
100P_0402_50V

2

SATA HDD

SATA_A0_TXP13

SATA_A0_TXN13
SATA_A0_RXN13
SATA_A0_RXP13

3 3

4 4

A

C569 0.01U_0402_25V7K~N

12

C518 0.01U_0402_25V7K~N

12

C568 0.01U_0402_25V7K~N

12

C570 0.01U_0402_25V7K~N

12

SATA_A0_TXP_C
SATA_A0_TXN_C

SATA_A0_RXN_C
SATA_A0_RXP_C

B

+3VS

+5VS

JSATA1

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

VCC3.3

9

VCC3.3

10

VCC3.3

11

GND

12

GND

13

GND

14

VCC5

15

VCC5

16

VCC5

17

GND

18

RESERVED

19

GND

20

VCC12

21

VCC12

22

VCC12

SUYIN_127043FB022G345ZR_NR

CONN@

GND
GND

23
24

Close to JSATA1.

+5VS

1

+

C394
150U_B2_6.3VM_R45M

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH OUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2009/02/19 2009/12/31

1

C390
10U_0805_10V4Z~N

2

Compal Secret Data

Deciphered Date

D

1

C392

0.1U_0402_16V7K~N

2

1

C391

0.1U_0402_16V7K~N

2

1

C393
1000P_0402_50V7K~N

2

Title

Size Document Number Re v

Custom

Date: Sheet

Compal Electroni cs, Inc.

LCD/SATA HDD

LA-4631P

E

20 42Tuesday, F ebruary 24, 2009

1.0

of

5

D D

Close to JHDMI connector

R406 0_0402_5%@

1 2

L23

1

VGA_DVI_TXD1+

C C

VGA_DVI_TXD2-

VGA_DVI_TXD2+

1

4

4

SUPERWORLD OCE2012120YZF

R416

@

1 2

0_0402_5%

R418 0_0402_5%@

1 2

L25

1

1

4

4

SUPERWORLD OCE2012120YZF

R425 0_0402_5%@

1 2

DVI_TXD1-VGA_DVI_TXD1-

2

2

DVI_TXD1+

3

3

DVI_TXD2-

2

2

DVI_TXD2+

3

3

4

R411 0_0402_5%@

1 2

L24

VGA_DVI_TXC-

VGA_DVI_TXC+

VGA_DVI_TXD0-

VGA_DVI_TXD0+

1

1

2

4

3

4

SUPERWORLD OCE2012120YZF

R417 0_0402_5%@

1 2

R423 0_0402_5%@

1 2

L26

1

1

2

4

3

4

SUPERWORLD OCE2012120YZF

R426 0_0402_5%@

1 2

3

2 1

+5VS

D19 BAT1000-7-F SOT23-3

@

R1282

0_0402_5%

HDMI_HPD11

12

SCL_HDMI_MCP11
SDA_HDMI_MCP11

+5VS

DVI_TXC-

2

DVI_TXC+

3

DVI_TXD0-

2

DVI_TXD0+

3

2

2 1

F1

1A_6VDC_MINISMDC110

+3VS

12

R399

2.2K_0402_5%

HDMI_HPD

SCL_HDMI_MCP
SDA_HDMI_MCP

1

C449

0.1U_0402_16V7K

2

HDMI_DET_C28

SN74AHCT1G125GW_SOT353-5

R404

1 2

0_0402_5%

R405

1 2

0_0402_5%

4

DVI_SCLK
DVI_SDATA

4.7K_0402_5%

+5VS_HDMI

U36

DVI_SCLK

DVI_SDATA

5

1

P

OE#

A2Y

G

3

R412

0.1U_0402_16V7K
C450

12

100K_0402_5%

HDMI_DET_C

+5VS_HDMI

+3VS +3VS

12

12

R413

4.7K_0402_5%

HDMI_SDA
HDMI_SCL

DVI_TXC­DVI_TXC+

DVI_TXD0­DVI_TXD0+

DVI_TXD1­DVI_TXD1+

DVI_TXD2­DVI_TXD2+

G

S

+5VS_HDMI

2

13

D

S

Q13

2N7002_SOT23

1

HDMI Connector

12

1

C451

2

Q12

13

D

2N7002_SOT23

0.1U_0402_16V7K

2

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

FOX_QJ5119L-NVBT-7F

CONN@

R414

4.7K_0402_5%

GND
GND
GND
GND

+5VS_HDMI

12

R396

G

20
21
22
23

12

R415

4.7K_0402_5%

HDMI_SCL

HDMI_SDA

DisplayPort/TMDS 1:2 Switch/Translator DisplayPort Connector

MCP79_DP0+ SW_DP0+

MCP79_DP0+11
MCP79_DP0-11

MCP79_DP1+11
MCP79_DP1-11

MCP79_DP2+11
MCP79_DP2-11

MCP79_DP3+11
MCP79_DP3-11

MCP79_AUX+11
MCP79_AUX-11

SCL_DP_MCP11
SDA_DP_MCP11

B B

SCL_HDMI_MCP11
SDA_HDMI_MCP11

TI_PRIORITY11
MCP_DP_CBL_DET11

DP_CBL_DET MCP_DP_CBL_DET

MCP79_DP0­MCP79_DP1+

MCP79_DP1­MCP79_DP2+

MCP79_DP2­MCP79_DP3+

MCP79_DP3­MCP79_AUX+ DP+

MCP79_AUX­SCL_DP_MCP

SDA_DP_MCP
SCL_HDMI_MCP

SDA_HDMI_MCP

+3VS

1 2

R431 0_0402_5%

MCP_DP_HPDDP_HPD

R451

12

0_0402_5%

R456

@

12

0_0402_5%

12

C460 0.1U_0402_16V7K

12

C462 0.1U_0402_16V7K

12

C464 0.1U_0402_16V7K

12

C466 0.1U_0402_16V7K

12

C470 0.1U_0402_16V7K

12

C472 0.1U_0402_16V7K

12

C474 0.1U_0402_16V7K

12

C475 0.1U_0402_16V7K

R488 0_0402_5%@

1 2

R487 0_0402_5%@

1 2

R490 0_0402_5%@

1 2

R489 0_0402_5%@

1 2

R407 0_0402_5%@

1 2

R408 0_0402_5%@

1 2

R428 4.7K_0402_5%

1 2

R429 4.7K_0402_5%@

1 2

R430 100K_0402_5%

1 2

MCP_DP_CBL_DET_TI

@

1 2

R475 0_0402_5%

DP_CBL_DET

HDMI_HPD
DP_HPD

+3VS

R436

1 2

1 2

@

R486
0_0402_5%

@

MCP79_AUX+11

DP_AUXP
DP_AUXN

MCP79_AUX-11

+3VS

Q45AO3413_SOT23

A A

CBL_DET

100K_0402_5%

SCL_DP_MCP11
SDA_DP_MCP11

S

G

2

D

1 2

1 3

12

R460

R457

100K_0402_5%

1 2

R458 0_0402_5%

1 2

R459 0_0402_5%

1 2

5

SW_DP0­SW_DP1+

SW_DP1­SW_DP2+

SW_DP2­SW_DP3+

SW_DP3-

DP-

4.7K_0402_5%

R445

0_0402_5%

U38

3

ML_IN 0(P)

4

ML_IN 0(N)

6

ML_IN 1(P)

7

ML_IN 1(N)

9

ML_IN 2(P)

10

ML_IN 2(N)

12

ML_IN 3(P)

13

ML_IN 3(N)

45

AUX_SINK (P)

43

AUX_SINK (N)

36

AUX(P)_I2C(SCL)

35

AUX(N)_I2C(SDA)

29

I2C_SCL

28

I2C_SDA

30

LP

33

PRIORITY

41

CAD_SINK

39

CAD

32

TMDS_HPD_SINK

40

DP_HPD_SINK

5

GND

11

GND

20

GND

27

GND

31

GND

42

GND

44

GND

51

GND

57

EXPOSED PAD

SN75DP122A_QFN56_8X8

R452

@

5.1M_0402_5%

MCP79_AUX+

BSS138W-7-F_SOT323-3

MCP79_AUX-

TMDS_SINK_CLK(P)
TMDS_SINK_CLK(N)

TMDS_SINK 0(P)
TMDS_SINK 0(N)

TMDS_SINK 1(P)
TMDS_SINK 1(N)

TMDS_SINK 2(P)
TMDS_SINK 2(N)

DP_SINK 0(P)
DP_SINK 0(N)

DP_SINK 1(P)
DP_SINK 1(N)

DP_SINK 2(P)
DP_SINK 2(N)

DP_SINK 3(P)
DP_SINK 3(N)

+3VS

C491 0.1U_0402_16V4Z

5

P

A2Y

12

G

U41

3

BSS138W-7-F_SOT323-3

VDD*1

DPVADJ

VSADJ

1

74LVC1G14GW_SOT353-5

NC

VCC
VCC
VCC

VDD
VDD
VDD
VDD
VDD

HPD

12

4

G

2

S

R479

@

0_0402_5%

14
17
23

2
8
34
48
54

38

R427 0_0402_5%

16
15

19
18

22
21

25
24

56
55

53
52

50
49

47
46

37

1
26

R440

CBL_DETDP_CBL_DET

G

2

S

R477

@

0_0402_5%

13

D

Q17

12

+3VS+5VS

1 2

VGA_DVI_TXC+
VGA_DVI_TXC-

VGA_DVI_TXD0+
VGA_DVI_TXD0-

VGA_DVI_TXD1+
VGA_DVI_TXD1-

VGA_DVI_TXD2+
VGA_DVI_TXD2-

DP_TX0+
DP_TX0-

DP_TX1+
DP_TX1-

DP_TX2+
DP_TX2-

DP_TX3+
DP_TX3-

R438

1 2

4.7K_0402_1%

R449

0_0402_5%

SCL_DP

13

D

Q16

12

SDA_DP

12

C459 0.1U_0402_16V4Z

12

C461 0.1U_0402_16V4Z

12

C463 0.1U_0402_16V4Z

12

C465 0.1U_0402_16V4Z

12

C467 0.1U_0402_16V4Z

12

C469 0.1U_0402_16V4Z

12

C471 0.1U_0402_16V4Z

12

C473 0.1U_0402_16V4Z

MCP_DP_HPD

R435

12

0_0402_5%@

6.49K_0402_1%

R447 4.7K_0402_5%@

1 2

MCP_DP_CBL_DET

R453

100K_0402_5%

1 2

1 2

12

C4950.1U _0402_16V4Z

C4960.1U _0402_16V4Z

1 2

12

12

4

R439

@

100K_0402_5%

DP_AUXP

DP_AUXN

MCP_DP_HPD 11

+3VS

MCP_DP_CBL_DET 11

F3

MF-NSMF150-2 1.5A 6V

1 2

AZ1045-04QU_MSOP10

@

MF-NSMF150-2 1.5A 6V

1 2

6

NC

NC7NC

VDD3Line 11Line 3

2

Close to JDP connector

Issued Date

1 2

1 2

1 2

1 2

L29

1 2

C4760.1 U_0402_16V7K

C4780.1 U_0402_16V7K

C4800.1 U_0402_16V7K

C4820.1 U_0402_16V7K

+3VS

12

12

R433

R120

100K_0402_5%

DP_AUXP
DP_AUXN

DP_HPD

DP_CBL_DET

100K_0402_5%

DP_CBL_DET28

DP_HPD28

@

100K_0402_5%

R121

100K_0402_5%

12

R441

@

12

12

R443

100K_0402_5%

DP_TX0+
DP_TX0-

DP_TX1+ DP_TXD1+
DP_TX1-

DP_TX2+
DP_TX2-

DP_TX3+
DP_TX3-

R434

1 2

1K_0402_5%

R437

1 2

1K_0402_5%

C486

1

12

R444

2

100K_0402_5%

100P_0402_50V8J

Security Classification

THIS SHEET OF E NGINE ERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
AND TRADE SEC RET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMP AL ELECTRONICS, IN C. NEITHER THIS SH EET NOR THE INFO RMATION IT CONTAIN S

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

+3V_DP

6

9

NC

NC7NC

Line 2

VDD3Line 11Line 3

2

4

DP_TXD0+
DP_TXD0-

1 2

C4770.1 U_0402_16V7K

DP_TXD1-

1 2

C4790.1 U_0402_16V7K

DP_TXD2+
DP_TXD2-

1 2

C4810.1 U_0402_16V7K

DP_TXC+
DP_TXC-

1 2

C4830.1 U_0402_16V7K

BLM18AG121SN1D_0603

1 2

L28

BLM18AG121SN1D_0603

1

C487

180P_0402_50V8J

2

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

2

U39

@

8

10

NC

GND

Line 4

5

MCK3225201YZF 1210

F2

10

9

NC

Line 2

4

L27

1 2

2

C468

U40

@

8

1

+3VS_DP

0.1U_0402_16V7K

GND

Line 4

5

AZ1045-04QU_MSOP10

Compal Electronics, Inc.

Title

HDMI/Display Port Conn.

Size Document Number Rev

Custom

LA-4631P

Date: Sheet

PIN 14
PULLED UP (26K)
INSIDE DONGLE

12

R454
2M_0402_5%

1

10
11
12
13
14
15
16
17
18
19
20

21
22
23
24

JDP1

1

LANE0_P

2
3

LANE0_N

4
5

GND

6
7

LANE2_P

8
9

LANE2_N

GND

CONFIG1

AUXCH_P

AUXCH_N

RETURN

GROUND

FOX_3V102P1-RB2BT-8F_20P

GND

LANE1_P

LANE1_N

GND

LANE3_P

LANE3_N

CONFIG2

GND

HPD

DP_PWR

21 42Tuesday, February 24, 2009

1.0

of

5

W=60mils

+3V_LAN

1.5A

+3V_LAN

1

C615

2

D D

0.1U_0402_10V7K~N

1

C616

2

0.1U_0402_10V7K~N

1

C617

2

0.1U_0402_10V7K~N

+LAN_VDD

1 2

0_0603_5%

These caps close to U64: Pin 44, 45

PCIE_RX1_C_P

12

0.1U_0402_16V7K

PCIE_RX1_C_N

12

0.1U_0402_16V7K

12

0.1U_0402_16V7K

PCIE_TX1_C_NPCIE_TX1_N

12

0.1U_0402_16V7K

PCIE_RST#

1 2

R1255 2.49K_0402_1%

PCIE_WAKE#
ISOLATEB

LAN_CABDT28

LAN_XTAL1

LAN_XTAL2 LAN_XTAL2_R

X5

12

25MHZ_20P

1

C299
27P_0402_50V8J

2

1
2
3

4
5

7
8
9

10
11
12

LAN_XTAL1
LAN_XTAL2_R

LAN_CABDT

1 2

R5500_0402_5%~D

T19

TCT1

MCT1

TD1+

MX1+

TD1-

MX1-

TCT2

MCT2

TD2+

MX2+

TD2-6MX2­TCT3

MCT3

TD3+

MX3+

TD3-

MX3-

TCT4

MCT4

TD4+

MX4+

TD4-

MX4-

LFE9249-R LAN

24
23
22

21
20
19

18
17
16

15
14
13

PCIE_WAKE#10,23,24,28

R1257
15K_0402_5%

1 2

R1250

R234

0_0402_5%

C298

C626
C627
C628
C631

0_0402_5%

1 2

1

2

LAN_MIDI3­LAN_MIDI3+

LAN_MIDI2­LAN_MIDI2+

LAN_MIDI1­LAN_MIDI1+

LAN_MIDI0­LAN_MIDI0+

PCIE_RX1_P10
PCIE_RX1_N10

C C

B B

A A

PCIE_TX1_P10

PCIE_TX1_N10

1 2

+3VS

1K_0402_5%

LAN_LOPWEN28

PHY_25MHZ11

PCIE_TX1_P PCIE_TX1_C_P

CLK_PCIE_LAN10

CLK_PCIE_LAN#10

LAN_CLKREQ#10

PCIE_RST#10,23,24,26

R1256

1 2

LAN_LOPWEN ISOLATEB

@

R230 0_0402_5%@

1 2

27P_0402_50V8J

C304 0.01U_0402_16V7K

1 2

C305 0.01U_0402_16V7K

1 2

C306 0.01U_0402_16V7K

1 2

C307 0.01U_0402_16V7K

1 2

5

4

R1238

1

C6180.1U_0402_10V7K~N

2

U22

20

HSOP

21

HSON

15

HSIP

16

HSIN

17

REFCLK_P

18

REFCLK_M

25

CLKREQB

27

PERSTB

46

RSET

26

LANWAKEB

28

ISOLATEB

41

CKTAL1

42

CKTAL2

23

NC

24

NC

7

GND

14

GND

31

GND

47

GND

22

EGND

RTL8111DL-GR_LQFP48

RJ45_MDI3­RJ45_MDI3+

RJ45_MDI2­RJ45_MDI2+

RJ45_MDI1­RJ45_MDI1+

RJ45_MDI0­RJ45_MDI0+

4

+LAN_VDD12

1

1

C6190.1U_0402_10V7K~N

2

1

C6200.1U_0402_10V7K~N

C6210.1U_0402_10V7K~N

2

2

1

1

C6230.1U_0402_10V7K~N

C6220.1U_0402_10V7K~N

2

2

These caps close to U64: Pin 4,10,13, 30, 36,39

LAN_LED3

33

RTL8111DL

R236

1 2

75_0402_1%

R239

1 2

75_0402_1%

R254

1 2

75_0402_1%

R256

1 2

75_0402_1%

LED3/EEDO

LED2/EEDI/AUX

LED1/EESK

MDI P2
MDI N2
MDI P3
MDI N3

SROUT12

EVDD12
DVDD12
DVDD12
DVDD12
AVDD12

AVDD12

VDDSR
VDDSR

VDD33
VDD33

AVDD33
AVDD33

CT

1000P_1206_2KV7K

EECS

LED0

MDIP0
MDIN0
MDIP1
MDIN1

FB12

ENSR

LAN_LED2

34

LAN_LED1

35
32

38
2

3
5
6
8
9
11
12

4

+LAN_SROUT12

48

+LAN_EVDD12

19
30
36
13
10

39
44

45
29

37
1

40
43

C310

LAN_LED0

LAN_MIDI0+
LAN_MIDI0­LAN_MIDI1+
LAN_MIDI1­LAN_MIDI2+
LAN_MIDI2­LAN_MIDI3+
LAN_MIDI3-

+LAN_AVDD33

12

+LAN_VDD12

+3V_LAN_R

+3V_LAN_R

Security Classification

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

C624

1

2

22U_1206_6.3V6M

1

C625

2

These caps close to U64: Pin 44,45

( Should be place within 200 mils )

L111

+3V_LAN

W=60mils

C632

+LAN_VDD

1

1

C633

2

2

R1254 3.6K_0402_5%

1 2

1 2

4.7UH_1098AS-4R7M_1.3A

W=60mils

+LAN_VDD12

1

2

C643

C644

0.1U_0402_10V7K

These caps close to U64: Pin 1, 29,37,40

0.1U_0402_10V7K~N

R1276

1 2

0_0603_5%

1

2

10U_0603_6.3V

1 2

0_0603_5%

1 2

C636 0.1U_0402_16V7K~N

1 2

C637 0.1U_0402_16V7K~N

1 2

C638 0.1U_0402_16V7K~N

1 2

C639 0.1U_0402_16V7K~N

Issued Date

3

22U_1206_6.3V6M

+3V_LAN

R1258

LAN_LED2

SDMK0340L-7-F

LAN_LED3

SDMK0340L-7-F

LAN_LED1

SDMK0340L-7-F

LAN_LED3

SDMK0340L-7-F

2009/02/19 2009/12/31

+3V_LAN_R

0.1U_0402_10V7K~N

LAN_MIDI2-

LAN_MIDI2+

These caps close to U64: Pin 4

+LAN_VDD

0.1U_0402_10V7K

CM1293A-04SO SOT23-6

1

CH1

2

Vn

3

CH2

D27

@

CH4

CH3

4

5

Vp

6

These components close to U64: Pin 48

( Should be place within 200 mils )

W=30mils

R1259

0_0603_5%

1 2

C634 1U_0402_6.3V4Z

1 2

C635 1U_0402_6.3V4Z

12

These caps close to U64: Pin 19

+3V_LAN

+3V_LAN

D21

LED2_LED3

21

D22

21

D23

LED1_LED3

21

D24

21

+3V_LAN

Compal Secret Data

Deciphered Date

2

C629

2

1

2

@

0.01U_0402_16V7K

+LAN_VDD

LAN_LED0

LED2_LED3
LED1_LED3

2

C630

1

+3VALW

W=30mils

1 2

220_0402_5%

1 2

R1272 0_0402_5%

1 2

220_0402_5%

1 2

220_0402_5%

1 2

R1274 0_0402_5%

1

LAN_MIDI0-

LAN_MIDI0+

LED0_AD0_R

R5

RJ45_MDI3­RJ45_MDI3+
RJ45_MDI1­RJ45_MDI2­RJ45_MDI2+
RJ45_MDI1+
RJ45_MDI0­RJ45_MDI0+

LED2_RXDLY_R

R22

LED1_AD1_R

R12

Title

Size Document Number Rev

Custom

Date: Sheet

CM1293A-04SO SOT23-6

LAN_MIDI1-

LAN_MIDI1+

LAN_MIDI3-

LAN_MIDI3+

1

2

3

D25

@

CM1293A-04SO SOT23-6

1

2

3

@

CM1293A-04SO SOT23-6

1

2

3

@

LED1_LED3
LED2_LED3
LAN_LED0

JLAN1

13

Yellow LED-

12

Yellow LED+

8

TX3-

7

TX3+

6

TX1-

5

TX2-

4

TX2+

3

TX1+

2

TX0-

1

TX0+

11

Orange LED-

9

Green LED-

10

Green-Orange LED+

CH1

Vn

CH2

CH1

Vn

CH2

D26

CH1

Vn

CH2

D28

C640

100P_0402_25V8K

TYCO_2041633-1

C641

CH4

Vp

CH3

CH4

Vp

CH3

CH4

Vp

CH3

100P_0402_25V8K

Compal Electronics, Inc.

Gigabit LAN_RTL8111DL

LA-4631P

1

4

5

6

C642

+3VALW

4

5

6

4

5

6

GND
GND
GND
GND
GND
GND

+3VALW

+3VALW

100P_0402_25V8K

14
15
16
17
18
19

1.0

of

22 42Tuesday, Fe b r u a r y 24, 2009

5

D D

4

3

2

1

Express CardExpress Card Power Switch

JEXP1

1

+1.5VS_CARD

C C

+3VALW

0.1U_0402_16V7K~N
C530

C529

PCIE_RST#10 ,22,24,26

SYSON28,30,35
SUSP#28,30,36,37

R498 100K_0402_5%@

+3VALW

B B

R499 100K_0402_5%@

1 2
1 2

1

1

2

2

0.1U_0402_16V7K~N
C531

PCIE_RST#

PEB_PRSNT#
CPUSB#

+1.5VS+3VS

0.1U_0402_16V7K~N

1

2

U28

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin
AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

TPS2231MRGPR-1 QFN 20P

1.5Vout

1.5Vout

3.3Vout

3.3Vout

PERST#

OC#

NC

GND

(1A) (1.5A)

0.1U_0402_16V7K~N
C524

C523

11
13

3
5

15
19

PERST#

8
16
7

1

1

2

2

+3VS_CARD

0.1U_0402_16V7K~N

10U_0805_4VAM~D

C525

1

2

C532

C526

0.1U_0402_16V7K~N

1

2

10U_0805_4VAM~D

C527

1

1

2

2

+3VS_CARD_AUX

(0.5A)

0.1U_0402_16V7K~N

C533

1

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

C528

1

2

USB20_N313
USB20_P313

SMB_CLK24

SMB_DATA24

PCIE_WAKE#10,22,24,28

EXP_CLKREQ#10

PEB_PRSNT#10

CLK_PCIE_EXPR#10

CLK_PCIE_EXPR10

PCIE_RX0_N10
PCIE_RX0_P10

PCIE_TX0_N10
PCIE_TX0_P10

USB20_N3
USB20_P3

SMB_CLK
SMB_DATA

PEB_PRSNT#
CLK_PCIE_EXPR#
CLK_PCIE_EXPR

PCIE_TX0_N
PCIE_TX0_P

R347 0_0402_5%
R348 0_0402_5%

R493 0_0402_5%
R494 0_0402_5%

R495 0_0402_5%

R496 0_0402_5%
R497 0_0402_5%

R501 0_0402_5%
R505 0_0402_5%

C47 0.1U_0402_16V7K
C46 0.1U_0402_16V7K

1 2

+3VS_CARD_AUX

1 2
1 2

1 2
1 2

12
12

12
12

+1.5VS_CARD

+3VS_CARD

12
12

USB20_N3_R
USB20_P3_R
CPUSB#

SMB_CLK_R
SMB_DATA_R

PERST#

EXP_CLKREQ#_REXP_CLKREQ#
CPPE#

PCIE_RX0_C_N
PCIE_RX0_C_P

PCIE_TX0_C_N
PCIE_TX0_C_P

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

29

GND

GND

GND30GND

FOX_1CX422AU1-BT_26P_RT-T

CONN@

31
32

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/02/19 2009/12/31

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

Express Card

LA-4631P

1.0

23 42Tuesday, February 24, 2009

1

A

WLAN

1 1

PCIE_WAKE#10,22,23,28

WLAN_ACT27

BT_PRI27

WLAN_CLKREQ#10

CLK_PCIE_WLAN#10
CLK_PCIE_WLAN10

PLT_RST#12,28

LPC_CLK012,28

PCIE_RX2_N10
PCIE_RX2_P10

PCIE_TX2_N10

PCIE_TX2_P10

2 2

PCIE_WAKE#

WLAN_CLKREQ# WLAN_CLKREQ#_R
CLK_PCIE_WLAN#

CLK_PCIE_WLAN LPC_AD1

LPC_CLK0

PCIE_TX2_N
PCIE_TX2_P

R260 0_0402_5%

1 2

R261 0_0402_5%

1 2

R262 0_0402_5%

1 2

R268 0_0402_5%

1 2

R282 0_0402_5%

1 2

R102 0_0402_5%

1 2

R112 0_0402_5%

1 2

C51 0.1U_0402_16V7K

12

C50 0.1U_0402_16V7K

12

+3V_WLAN

WLAN_ACT_RWLAN_ACT
BT_PRI_RBT_PRI

PLT_RST#_RPLT_RST#
LPC_CLK0_R

PCIE_RX2_C_N
PCIE_RX2_C_P

PCIE_TX2_C_N
PCIE_TX2_C_P

B

JMINI1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

TYCO_1775861-1~D

CONN@

GND2

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

+1.5VS +3V_WLAN

2

2

4

4

6

6

8

8

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R

PCIE_RST_R#
SMB_CLK_WLAN

SMB_DATA_WLAN

USB20_N7_R
USB20_P7_R

@

C337 47 P 5 0 V J NPO 0402

1

1

2

2

R263 0_0402_5%

1 2

R264 0_0402_5%

1 2

R265 0_0402_5%

1 2

R266 0_0402_5%

1 2

R267 0_0402_5%

1 2

R37 0_0402_5%

1 2

R270 0_0402_5%

1 2

R299 0_0402_5%

1 2

R281 0_0402_5%

1 2

R1288 0_0402_5%@

1 2

R1289 0_0402_5%@

1 2

R273 0_0402_5%

1 2

R278 0_0402_5%

1 2

@

C336 47 P 5 0 V J NPO 0402

C

W=60mils

+3VALW

1

C521

1U_0603_10V6K

B+_BIAS

2

G

LPC_AD3
LPC_AD2

LPC_AD0

WL_RADIO_OFF#

SMB_CLK
SMB_DATA
MCP_SMB_CLK
MCP_SMB_DATA

USB20_N7
USB20_P7

PCIE_RST_R#

EN_WLAN#28

@

R374
470K_0402_5%

@

1 2
13

D

Q44
SSM3K7002FU_SC70-3

S

@

2

C45

0.1U_0402_16V7K

@

1

2

EN_WLAN

LPC_FRAME# 12,28

LPC_AD[0..3] 12,28
WL_RADIO_OFF# 28
PCIE_RST# 10,22,23,26

+3VALW

USB20_N7 13
USB20_P7 13

Q43

D

6
2

1

SI3456BDV-T1-E3 1N TSOP6

G

3

1 2

S

45

@

R368

1.5M_0402_5%

@

MCP_SMB_CLK14

D

+3VS

0.01U 16V K X7R 0402

MCP_SMB_DATA

+5VS

+3V_WLAN

R308

1 2

0_0805_5%

1

C322

2

+1.5VS

C320

SSM3K7002FU_SC70-3

MCP_SMB_CLK

D

1 3

12

Q57

2

SSM3K7002FU_SC70-3

R1296

2.2K_0402_5%

0.01U 16V K X7R 0402

C323

1

2

S

G

1

2

Q56

D

1 3

2

1

2

G

SMB_DATA

0.1U 16V K X7R 0402

4.7U 10V Z Y5V 0805

1

C324

2

C321

0.01U 16V K X7R 0402

2.2K_0402_5%

S

SMB_CLK

C535

R1294

1

+

2

+3VS

E

330U_D2E_6.3VM_R25~D@

12

12

R1295

2.2K_0402_5%

SMB_CLK 23

SMB_DATA 23MCP_SMB_DATA14

WWAN

JMINI2

1

1

3

3 3

+3VS

+3VS

0.01U 16V K X7R 0402

C332

0.1U 16V K X7R 0402

1

1

C333

2

2

A

1

4 4

C331

2

330U_D2E_6.3VM_R25~D@

C574

330U_D2E_6.3VM_R25~D@

1

+

2

0.01U 16V K X7R 0402

4.7U 10V Z Y5V 0805

1

C575

+

2

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

TYCO_1775861-1~D

CONN@

+1.5VS

1

C334

2

B

+1.5VS +3VS

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

GND2

1

C335

0.01U 16V K X7R 0402

2

UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

SMB_CLK_WWAN
SMB_DATA_WWAN

USB20_N6_R
USB20_P6_R

@

@

C350 47 P 5 0 V J NPO 0402

1

1

2

2

+UIM_PWR

WAN_RADIO_OFF#

R275 0_0402_5%

1 2

R276 0_0402_5%

1 2

R277 0_0402_5%

1 2

R279 0_0402_5%

1 2

R280 0_0402_5%

1 2

C351 47 P 5 0 V J NPO 0402

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

PCIE_RST#

+3VALW

SMB_CLK
SMB_DATA

USB20_N6
USB20_P6

2009/02/19 2009/12/31

WAN_RADIO_OFF# 28
PCIE_RST# 10,22,23,26

UIM_DET28

USB20_N6 13
USB20_P6 13

Compal Secret Data

Deciphered Date

UIM_DATA
UIM_DET

C571

100P_0402_25V8K

D

U23

1

CH1

CH4

2

Vn
CH23CH3

S DIO(BR) NUP4301MR6T1 TSOP-6

JSIM1

2

GND

4

VPP

6

I/O

7

DET

8

DET

SUYIN_254070FB008H505ZL

C571 & C573 as close as JSIM1

Title

Mini Card_WLAN/WWAN

Size Document Number Rev

Custom

LA-4631P

Date: Sheet

6
5

Vp

VCC

GND
GND

4

RST
CLK

1
3
5

9
10

+UIM_PWR +3VS

UIM_RSTUIM_VPP
UIM_CLK

C573

C329

100P_0402_25V8K

Compal Electronics, Inc.

E

4.7U 6.3V K X5R 0805

1

2

24 42Tuesday, Fe b r u a r y 24, 2009

D9

@

1

DAN217_SC59-3

1

C330

0.1U 16V K X7R 0402

2

of

3
2

1.0

A

ACZ_BITCLK

R287
0_0402_5%

1 2
1

C572

1 1

2

10P_0402_50V8J

R287 & C572 Close U25 pin6

DMIC_CLK27

DMIC_DATA27

100P_0402_50V

2 2

HP1_JD29
HP2_JD29
MIC_JD29

EC_MUTE#28

ACZ_BITCLK14

ACZ_SDIN014

ACZ_SDOUT14

@

ACZ_SYNC14

ACZ_RST#14

C593

C602

HP1_JD
HP2_JD
MIC_JD

1 2
1

2

1

2

ACZ_SDOUT

R306
0_0402_5%

10P_0402_50V8J

1 2
1 2
1 2
1 2
1 2
1 2

1
@

2

R298 20K_0402_1%

R300 39. 2 K _0402_1%
R301 20K_0402_1%
R303 10K_0402_1%

EC_MUTE#

1 2

C594
100P_0402_50V

EC_MUTE#

1 2

C352 2.2U_0603_6.3V4Z

1 2

12
1 2
1 2

R286 0_0402_5%
R288 33_0402_5%
R290 0_0402_5%
R291 0_0402_5%
R293 0_0402_5%
R294 33_0402_5%
R295 0_0402_5%

EAPD shut down Extenal and Intenal AMP

C338

R297

1

2

B

C339

0.1U_0402_10V6K

EAPD

12

0_0402_5%

SENSE B

SENSE A

+DVDD_AUDIO

1

2

1U_0603_10V6K

10
11

46
48
47
35
36

14

13
49
42

26
30
33

R271

1 2

0_0603_5%

1

C340

2

U25

6
8
5

2
4

7

92HD83C1X5NLGXYBX8 QFN 48P CODEC

C341

0.1U_0402_10V6K

9

3

DVDD

DVDD_IO

HDA_BITCLK
HDA_SDI
HDA_SDO
HDA_SYNC
HDA_RST#
DMIC_CLK/GPIO1
DMIC0/GPIO2
DMIC1/GPIO0/SPDIF_OUT_1
SPDIF_OUT_0
EAPD
CAP­CAP+

SENSE_B

SENSE_A
GPAD

DVSS
PVSS
AVSS
AVSS
AVSS

+3VS

1

2

10U_0603_6.3V

1

DVDD_CORE

HP0_PORT_A_L

HP0_PORT_A_R

VREFOUT_A_or_F

HP1_PORT_B_L

HP1_PORT_B_R

SPKR_PORT_D_L+

SPKR_PORT_D_L-

SPKR_PORT_D_R-

SPKR_PORT_D_R+

27

38

AVDD

AVDD

PORT_C_L
PORT_C_R

VREFOUT_C

PORT_E_L

PORT_E_R

PORT_F_L

PORT_F_R

PC_BEEP

MONO_OUT

CAP2

VREFFILT

VREG

4.7U_0603_6.3V

39

C

45

PVDD

V-

PVDD

28
29
23

31
32

19
20
24

40
41

43
44

15
16

17
18

12
25
22
21
34
37

C342

C353

1

2

+AVDD_AUDIO

1

C343

2

0.1U_0402_10V6K

1U_0603_10V6K

HP1_LEFT_R
HP1_RIGHT_R

HP2_LEFT_R
HP2_RIGHT_R

MIC_LEFT
MIC_RIGHT

SPKER_L1
SPKER_L2

SPKER_R1
SPKER_R2

PC_BEEP

MONO_IN

1

C354

2

1

1

C345

C344

2

2

10U_0603_6.3V

R1290 56_0402_5%

1 2

1 2

R1291 56_0402_5%
R1292 56_0402_5%

1 2

1 2

R1293 56_0402_5%

MIC_LEFT 29
MIC_RIGHT 29

+MIC1_VREFO

1

1

C355

2

2

2.2U_0603_6.3V4Z

+AVDD_AUDIO

1

C346

2

0.1U_0402_10V6K

1U_0603_10V6K

HP1_LEFT
HP1_RIGHT

HP2_LEFT
HP2_RIGHT

1

C356

2

10U_0603_6.3V

D

R229

1 2

0_0805_5%

1U_0603_10V6K

+5VS

HP1_LEFT 29
HP1_RIGHT 29

HP2_LEFT 29
HP2_RIGHT 29

E

HP1_LEFT
HP1_RIGHT

SSM3K131TU_SOT323-3

SSM3K131TU_SOT323-3

2N7002_SOT23

2N7002_SOT23

Q51

Q53

HP1_LEFT
HP1_RIGHT

13

D

S

S

D

1 3

D

@

Q59

S

@

Q63

F

2

G

A B

G

2

HP_MUTE

13

A

S

D

1 3

HP_MUTE

2

G

G

2

2

G

G

2

2

G

G

2

Co-lay schematic

13

D

Q52
SSM3K131TU_SOT323-3

S

S

Q54

D

SSM3K131TU_SOT323-3

1 3

13

D

@

Q60
2N7002_SOT23

S

B

@

S

Q64
2N7002_SOT23

D

1 3

G

HP2_LEFT
HP2_RIGHT

SSM3K131TU_SOT323-3

SSM3K131TU_SOT323-3

HP2_LEFT
HP2_RIGHT

2N7002_SOT23

2N7002_SOT23

13

D

Q47

2

G

S

C D

S

Q49

G

2

D

1 3

HP_MUTE

13

D

@

Q61

S

C D

@

S

Q65

D

1 3

HP_MUTE

H

13

D

Q48

2

SSM3K131TU_SOT323-3

G

S

S

Q50

G

2

D

SSM3K131TU_SOT323-3

1 3

13

D

@

Q62

2

G

G

2

2

2N7002_SOT23

G

S

@

S

Q66

G

2N7002_SOT23

2

D

1 3

C358 1U_0603_10V6K

R315

2.2K_0402_5%

1 2

12

EC_MUTE#

EC Beep

MCP Beep

3 3

SPKER_L1

SPKER_L2

SPKER_R1

SPKER_R2

4 4

BEEP#28

MCP_SPKR14

C243

10U_0603_6.3V6M~D

C244

10U_0603_6.3V6M~D

C245

10U_0603_6.3V6M~D

C246

10U_0603_6.3V6M~D

R307 20K_0402_1%

R310 20K_0402_1%

TWSPK_L1

TWSPK_L2

TWSPK_R1

TWSPK_R2

1 2

1 2

TWSPK_R1 29

TWSPK_R2 29

R393 0_0402_5%

12

R394 0_0402_5%

12

+5VALW

R1287
10K_0402_1%

1 2

HP_MUTE

13

D

Q55

2

SSM3K7002FU_SC70-3

G

S

Reserved for TEST

R320 0_0805_5%

1 2

GND AGND

A

B

C

PC_BEEP

MONO_IN

SPKER_L1
SPKER_L2
SPKER_R1
SPKER_R2

2

3

1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

PACDN042_SOT23-3~D

2009/02/19 2009/12/31

E

2

3

D5

D10

@

@

1

PACDN042_SOT23-3~D

Compal Secret Data

+AVDD_AUDIO +AVDD_AUDIO

12

R272

2.49K_0402_1%

SENSE A SEN SE B

12

C313
1000P_0402_50V7K~D

PLACE CLOSE TO CODEC PIN 13
If SENSE_A total length is greater

than 6 inches, change C313 to 0.1uF.

JSPK1

1

1

2

2

3

3

C596

100P_0402_50V

1

2

100P_0402_50V

1

C597

@

2

100P_0402_50V

1

C595

@

@

2

@

1

C598

2

4

100P_0402_50V

4

5

GND

6

GND

MOLEX_53780-0470

CONN@

Deciphered Date

F

+DVDD_AUDIO

12

R389

2.49K_0402_1%

12

C314
1000P_0402_50V7K~D

12

R304
10K_0402_5%

EAPD

PLACE CLOSE TO CODEC PIN 13
If SENSE_B total length is greater

than 6 inches, change C314 to 0.1uF.
If ports E and F are unused,

simply pull-up SENSE_B to
AVDD with a 100K-ohm resistor.

TWSPK_L1
TWSPK_L2

2

3

D11
ROW PESD5V0U2BT 3P C/C SOT23 ESD

1

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Codec IDT 92HD83

LA-4631P

G

JTWL2

1

1

2

2

3

GND

4

GND

MOLEX_53780-0270~D

CONN@

25 42Tuesday, Fe b r u a r y 24, 2009

H

1.0

of

5

D D

4

+1.8VS_CR

W=30 mil

3

2

These caps close to U26 pin5. These caps close to U26 pin10.

1

C368

2

1000P_0402_50V7K

1

C367

2

0.1U_0402_16V4Z

1

C366

2

10U_0805_10V4Z

1

C369

2

0.1U_0402_16V4Z

1

C386
10U_0805_10V4Z

@

2

1

+3VS

1

C388
10U_0805_10V4Z

@

2

1

C389
10U_0805_10V4Z

@

2

+3VS

W>40 mil

+1.8VS_CR

1

C382

220P_0402_50V7K

2

0.33U_0603_10V7K

Close to U26.

W=10 mil

12

R344

4.99K_0402_1%

1

C383

2

W=10 mil

IEEETP

TPBIAS

12

R345
56_0402_5%

12

R539
56_0402_5%

12

R538
56_0402_5%

IEEE_TPB1N
IEEE_TPB1P
IEEE_TPA1N
IEEE_TPA1P

12

R540
56_0402_5%

IEEE_TPB1N 29
IEEE_TPB1P 29
IEEE_TPA1N 29
IEEE_TPA1P 29

CLK_PCIE_1394#10
CLK_PCIE_139410

PCIE_TX3_N10
PCIE_TX3_P10

C C

B B

PCIE_RX3_N10
PCIE_RX3_P10

PCIE_RST#10,22,23,24

CLK_PCIE_1394#
CLK_PCIE_1394

W=12 mil

PCIE_RST#

C375 0.1U _0402_16V7K

1 2

C376 0.1U _0402_16V7K

1 2

C395 0.1U _0402_16V7K

1 2

C396 0.1U _0402_16V7K

1 2

R337 8.2K_0402_5%

1 2

@

1 2

C387 10U_0805_10V4Z

1 2

C379 0.1 U_0402_16V4Z

R338 0_0402_5%

1 2

+3VS

+3VS

R342 4.7K_0402_5%

1 2

R343 4.7K_0402_5%

1 2

PCIE_TX3_C_N
PCIE_TX3_C_P

PCIE_RX3_C_N
PCIE_RX3_C_P

APREXT

JMB_XIN
JMB_XOUT

XRSTN

T22
T23 R327 200K_0402_5%

U26

3

APCLKN

4

APCLKP

9

APRXN

8

APRXP

11

APTXN

12

APTXP

7

APREXT

38

TXIN

39

TXOUT

JMB380

30

TAV33

1

XRSTN

2

XTEST

13

SEEDAT

14

SEECLK

15

CR1_CD1N

16

CR1_CD0N

17

CR1_PCTLN

21

CR1_LEDN

49

GPAD

JMB380-QGAZ0B_QFN48_7X7

APVDD

APV18

DV33
DV33
DV33
DV18
DV18

MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8

MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14

TPA1P

TPBIAS_1

TREXT

APGND

TCPS
TPB1N
TPB1P
TPA1N

5
10

19
20
44
18
37

48
47
46
45
43
42
41

MDIO7

40
29
28
27
26

MDIO12

25
23

MDIO14

22

IEEE_TPA1P

34

TPBIAS

35

TREXT

36
6

TCPS

24

IEEE_TPB1N

31

IEEE_TPB1P

32

IEEE_TPA1N

33

1

C373

C374

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R325 10K_0402_5%

R329 200K_0402_5%

R340 12K_0402_1%

R341 10K_0402_5%

1

C377

2

1 2

1 2
1 2

1 2

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

1

C378

2

Close to U2 6 pin38, pin39. (L<500mil).

C370

22P_0402_50V8J

24.576MHz_16P_3XG-24576-43E1

C372

22P_0402_50V8J

12

X4

12

W=7 mil

JMB_XIN

12

12

R336
1M_0402_5%

R551

1 2

0_0402_5%~D

W=7 mil

JMB_XOUT

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH OUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

2

Compal Electroni cs, Inc.

Title

IEEE1394_JMB380

Size Document Number Re v

Custom

LA-4631P

Date: Sheet

1

26 42Tuesday, F ebruary 24, 2009

of

1.0

C445

0.1U_0402_16V4Z

+USB_AS+5VALW

W=80mils W=80mils Close to USB Connector.

1

USB_EN#28,29

2

USB_EN#

U32

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062ADR_SO8~D

USB_OC#013

OC1#
OUT1
OUT2
OC2#

8
7
6
5

USB_EN#

12

R388
100K_0402_5%

@

R385

2

G

1

+

C443

12

2

30K_0402_5%

13

D

Q8
SSM3K7002FU_SC70-3

S

150U_B2_6.3VM_R45M

C444

0.1U_0402_16V4Z

Bluetooth

USB20_N013

USB20_P013

USB20_N0

USB20_P0

L19 WCM2012F2S-900T04_0805

1

1

4

4

2

2

3

USB_N0
USB_P0

3

+USB_AS

W=80mils

JUSBP1

1

VBUS

2

D-

3

D+

4

GND

5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_020173MR004S52GZL

change JUSBP1 connect signal (for layout)

USB20_P413
USB20_N413

+3VS

DMIC_CLK25

DMIC_DATA25

L21, L22 AS CLOSE JCA1 AS POSSIBLE

USB20_P4
USB20_N4

DMIC_CLK
DMIC_DATA

USB_DETECT#29

L30 WCM2012F2S-900T04_0805

1

1

2

4

L21 MBK1608221YZF 0603
R74 0_0603_1%

AS CLOSE AS JCA1

100P_0402_50V

10K_0402_1%

USB_DETECT#

3

4

12

1 2

1

1

C446

2

2

100P_0402_50V

RTCVREF RTCVREF RTCVREFRTCVREF

12

R1303

100K_0402_1%~D

2.2U_10V_K X7R_0603

Camera Conn

2

3

USB_P4
USB_N4

C447

R1304

C654

12

12

JCA1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

GND

9

GND

MOLEX_48227-0701

D33
SDMK0340L-7-F

2 1

TC7SZ14FU_SSOP5~D

2
4

USB20_P5_R

6

USB20_N5_R

8
10
12
14

16

+3VS

R398 0_0402_5%
R400 0_0402_5%

USB20_P5_R

USB20_N5_R

12
12

C357

@

BT_PRI 24

USB20_P5 13
USB20_N5 13

47P 50V J NPO 0402

47P 50V J NPO 0402

1

1

C359

@

2

2

JBT1

112
334
556
778
9910
111112
131314

GND15GND

HRS_CL537-0918-4-86

CONN@

51ON# 29,32

USB_DET#_DELAY 28

13

D

Q58
2N7002_SOT23

S

51ON#

BT_DET

BT_OFF#
BT_RADIO_OFF#

BT_DET28

WLAN_ACT24

BT_OFF#28

BT_RADIO_OFF#28

CLOSE TO U48

C655

@

1

0.1U_0402_16V4Z

2

5

1

P

NC
A

G

3

100K_0402_5%

2 1

SDMK0340L-7-F

4

Y

D31

R1305

2

G

12

USB_DET#_DELAY

2

U48

USB_N0

USB_P0

2

3

D20
ROW PESD5V0U2BT 3P C/C SOT23 ESD

1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

USB/BlueTooth/FP/Felcia

LA-4631P

of

27 42Tuesday, Fe b r u a r y 24, 2009

1.0

+3VALW

C404

1000P_0402_50V7K~N

C403

1000P_0402_50V7K~N

C399

0.1U_0402_16V4Z~N

1

2

EC_GA2014
EC_KBRST#14
SERIRQ12
LPC_FRAME#12,24

LPC_CLK0 ECAGND

12

R356
10_0402_5%@

1

C407

@

15P_0402_50V8J

2

USB_EN#
USB_EN2#

Low Enable

EC_SMB_DA2
EC_SMB_CK2

BT_RADIO_OFF#
WAN_RADIO_OFF#
WL_RADIO_OFF#

EC_MUTE#
EN_KBL#
LID_SW_D#
KSO1
KSO2
EC_SMB_DA1
EC_SMB_CK1
EC_GA20
EC_KBRST#
PCIE_WAKE#
BT_DET

MOLEX_53780-0370~D

+3VALW

R500 4.7K_0402_5%
R502 4.7K_0402_5%

R362 4.7K_0402_5%
R363 4.7K_0402_5%

R366 4.7K_0402_5%
R402 4.7K_0402_5%
R403 4.7K_0402_5%

TP_DATA
TP_CLK

R380 10K_0402_5%@

1 2

R392 10K_0402_5%

1 2

R397 10K_0402_5%

1 2

R375 47K_0402_5%

1 2

R401 47K_0402_5%

1 2

R359 4.7K_0402_5%
R360 4.7K_0402_5%
R1252 10K_0402_5%@

1 2

R1253 10K_0402_5%@

1 2

R1277 10K_0402_5%@

1 2

R1284 10K_0402_5%

1 2

JHS1

1
2
3

GND
GND

0.1U_0402_16V4Z

12
12

12
12

12
12
12

1 2
1 2

12
12

1
2
3

4
5

R357

1 2

47K_0402_5%

R376

4.7K_0402_5%

R377

4.7K_0402_5%

+3VALW

LID_SW_D#

C408

+3VALW

+5VS

+3VALW

DP_CBL_DET21

2

1

+3VS

For ENE Debug

EC_SCI#14

R553 0_0603_1%@

LPC_AD312,24
LPC_AD212,24
LPC_AD112,24
LPC_AD012,24

LPC_CLK012,24
PLT_RST#12,24

DP_CBL_DET

KSI[0..7]29

KSO[0..16]29

DIAG_LOOP329

EC_SMB_CK139
EC_SMB_DA139
EC_SMB_CK24
EC_SMB_DA24

PM_SLP_S3#14
PM_SLP_S5#14
EC_SMI#14

LCD_TST20

BT_RADIO_OFF#27

UIM_DET24

PS_ID32
KB_BL_PWM#29
FAN_SPEED14

WL_RADIO_OFF#24

DP_HPD21

ON_OFF29
PWR_BTN_LED#29
EN_KBL#29

FAN_SPEED1

1

@

C650

0.1U_0402_16V4Z

2

R1270 0_0603_1%

@

KSI5KSI4

1 2

R1271 0_0603_1%

1 2

@

1 2

KSI7KSI6

E51_TXD

XCLKO

C400

0.1U_0402_16V4Z~N

KSI[0..7]
KSO[0..16]

DIAG_LOOP3

C401

0.1U_0402_16V4Z~N

1

2

EC_GA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

LPC_CLK0
PLT_RST#

EC_RST#

2 1
1 2

R554 0_0402_5%

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

PM_SLP_S3#

PM_SLP_S5#

EC_SMI#

LCD_TST

BT_RADIO_OFF#

UIM_DET

KB_BL_PWM#

FAN_SPEED1

WL_RADIO_OFF#

E51_TXD

ON_OFF

PWR_BTN_LED#

EN_KBL#

XCLKI

1 2

R552

0_0402_5%~D

22P_0402_50V8J

1

2

C402

0.1U_0402_16V4Z~N

1

2

U29

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

D1SDMK0340L-7-F

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

KSI0

55

KSI0/GPIO30

KSI1

56

KSI1/GPIO31

KSI2

57

KSI2/GPIO32

KSI3

58

KSI3/GPIO33

KSI4

59

KSI4/GPIO34

KSI5

60

KSI5/GPIO35

KSI6

61

KSI6/GPIO36

KSI7

62

KSI7/GPIO37

KSO0

39

KSO0/GPIO20

KSO1

40

KSO1/GPIO21

KSO2

41

KSO2/GPIO22

KSO3

42

KSO3/GPIO23

KSO4

43

KSO4/GPIO24

KSO5

44

KSO5/GPIO25

KSO6

45

KSO6/GPIO26

KSO7

46

KSO7/GPIO27

KSO8

47

KSO8/GPIO28

KSO9

48

KSO9/GPIO29

KSO10

49

KSO10/GPIO2A

KSO11

50

KSO11/GPIO2B

KSO12

51

KSO12/GPIO2C

KSO13

52

KSO13/GPIO2D

KSO14

53

KSO14/GPIO2E

KSO15

54

KSO15/GPIO2F

KSO16

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

LID_SW#/GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT#/GPIO0C

PS_ID

19

EC_PME#/GPIO0D

25

EC_THERM#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

R5550_0402_5%

31

12

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LED#/GPIO19

36

NUMLED#/GPIO1A

122

XCLK1

123

XCLK0

KB926QFD3 LQFP 128P

XCLKO

1

C413

2

32.768KHZ_12.5P_1TJS125BJ2A251

1

2

LPC & MISC

R381

1 2

20M_0603_5%@

4

1

IN

OUT

NC3NC

2

1

2

Int. K/B
Matrix

SM Bus

XCLKI

X3

+EC_AVCC

9

22

33

96

111

125

VCC

VCC

VCC

VCC

VCC

VCC

INVT_PWM/PWM1/GPIO0F

ACOFF/FANPWM2/GPIO13

PWM Output

AD Input

DA Output

PS2 Interface

TP_DATA/PSDAT3/GPIO4F

SPI Device Interface

SPI Flash ROM

BATT_CHGI_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO54

GPO

GPIO

GPI

GND

GND

GND

GND

GND

11

24

35

94

113

1

C414
22P_0402_50V8J

2

1000P_0402_50V7K~N

67

AVCC

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B

AD4/GPIO42

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDO/WR#

SPICLK/GPIO58

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

CAPS_LED#/GPIO53
SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

AGND

69

ECAGND

ECAGND

SPIDI/RD#

SPICS#

GPXO10
GPXO11

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

1

C397

2

21
23
26
27

63
64
65
66
75
76

68
70
71
72

83
84
85
86
87
88

R361 0_0402_5%

97
98
99
109

119
120
126
128

73
74
89
90
91
92
93
95
121
127

100
101
102
103
104
105
106
107
108

110
112
114
115
116
117
118

124

BEEP#
SLP_MCP79_MAC#
ACOFF

BATT_OVP
ADP_I
AD_BID

R1260 0_0402_5%~D@

R1261 0_0402_5%~D@

EN_DFAN1
IREF
CHGVADJ_R

EC_MUTE#
USB_EN#
USBSW_EN2#
USB_EN2#
TP_CLK
TP_DATA

STB_LAN#
BT_OFF#
LID_SW_D#

FRD#SPI_SO
FWR#SPI_SI
SPI_CLK
FSEL#SPICS#

USB_DET#_DELAY
USBSW_EN#
FSTCHG
BATT_CHG_LED#
CAPSLED#
BATT_LOW_LED#
EN_WLAN#
SYSON
VR_ON
ACIN

EC_RSMRST#
EC_LID_OUT#
EC_ON

R1251 0_0402_5%

MCP_PWRGD_EC
BKOFF#
WAN_RADIO_OFF#
LCD_VCC_TEST_EN
PSID_DISABLE#

VGATE
EC_ENBKL
MCP79_ENVDD
BT_DET
SUSP#

BKLT_KB_DET#
+V18R

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

L17

12

MURATA BLM1 8 A G601SN1D 0603

2

C398

0.1U_0402_16V4Z~N

1

R559 0_0402_5%~D

1 2

C406 0.01U_0402_16V7K

1 2

BATT_TEMP

1 2

1 2

12

D2

@

SDMK0340L-7-F

1 2

PWRBTN#

C411 4.7U_0603_6.3V6K

12

C412 0.1U_0402_16V4Z

2009/02/19 2009/12/31

12

L18MURATA BLM18AG601SN1D 0603

INVT_PWM 20
BEEP# 25
SLP_MCP79_MAC# 11
ACOFF 33

BATT_TEMP 39
BATT_OVP 39
ADP_I 33

LCD_DET# 20

EN_DFAN1 4
IREF 33

1 2

R358 0_0402_5%

EC_MUTE# 25
USB_EN# 27,29

USBSW_EN2# 29
USB_EN2# 29

TP_CLK 29
TP_DATA 29

HDMI_DET_C

21

USB_DET#_DELAY 27
USBSW_EN# 29
FSTCHG 33

BATT_CHG_LED# 29

CAPSLED#
BATT_LOW_LED# 29
EN_WLAN# 24

SYSON 23,30,35

VR_ON 14,38

ACIN 14,32,33

EC_RSMRST# 14

EC_LID_OUT# 14

EC_ON 29

BKOFF# 20

WAN_RADIO_OFF# 24

LCD_VCC_TEST_EN 20

PSID_DISABLE# 32

VGATE 14,38

MCP79_ENVDD 11,20

BT_DET 27

SUSP# 23,30,36,37

PWRBTN# 14

BKLT_KB_DET# 29

Compal Secret Data

STB_LAN# 30

+3VALW+EC_AVCC

LAN_CABDT 22

LAN_LOPWEN 22

CHGVADJ 33

HDMI_DET_C 21

BT_OFF# 27

LID_SW# 14

PCIE_WAKE# 10,22,23,24

Deciphered Date

+3VALW

C410

1 2

0.1U_0402_16V4Z~N

R367 15_0402_5%

FRD#SPI_SO SPI_SO

1 2

@

D13 RB751V_SOD323

1 2

MCP79_ENBKL11

21

R378 0_0402_5%

MCP_PWRGD

1 2

R379 10K_0402_5%

@

Board ID

M/B rev:0.1; 0 .2 ; 0.3; 0.4; 0.5; 1.0
Voltage:0.0; 0 . 4 ; 0.8; 1.2; 1.65; 2.2

R365

12

SPI_CS#FSEL#SPICS#

12

R36915_0402_5%

0_0402_5%

10K_0402_5%

R213

BKOFF#
LCD_TST
EC_RSMRST#
MCP_PWRGD

U30

1

CS#

2

SO

3

WP#

4

GND

MX25L1605DM2I-12G SOP 8P ROM

MCP_PWRGD 14

+3VS

EC_ENBKL

12

12

R214
10K_0402_5%

12

R198

22K_0402_5%

0.5A per each pin

Title

BIOS & EC I/O Port

Size Document Number Rev

Custom

LA-4631P

Date: Sheet

+3VALW

Page 3 Note List

R350

100K_0402_5%

Ra

1 2

200K_0402_5%

1

12

R352

Rb

SPI Flash (16Mb*1)

20mils

8

VCC

7

HOLD#

SCLK

Close to U29 Close to U30

12

22K_0402_5%

R1285

SI

SPI_CLK

R364

1 2

6
5

1

2

100K_0402_5%

SPI_CLK_R
SPI_SI

12

R1286

R370

1 2

15_0402_5%

R372

1 2

15_0402_5%

SPI_CLK_R

@

C645
22P_0402_50V8J

1K_0402_1%

2

C409

@

1 2

0.1U_0402_16V4Z~N

1

2

Compal Electronics, Inc.

28 42Tuesday, Feb ru ar y 24, 2009

AD_BID

C405

0.1U_0402_16V4Z

SPI_CLK_R

SPI_CLK
FWR#SPI_SI

@

C646
22P_0402_50V8J

of

1.0

A

+3VALW

Power Button

R382

1 2

D14

100K_0402_5%

1 1

EC_ON28

2 2

EN_KBL#28

PWR_ON-OFF_BTN#

ROW BAV70W-7-F 3P C/C SOT-323

EC_ON

R384
0_0402_5%

12

R383
10K_0402_5%

1U_0603_10V6K

B+_BIAS

2

G

KB_BL_PWM#28

1 2

C415

R371

470K_0402_5%

1 2
13

D

Q39
SSM3K7002FU_SC70-3

S

2

1

2

G

+5VS

1

2

EN_KBL

51ON#

3

12

13

D

Q7

SSM3K7002FU_SC70-3

S

Q41

SI3456BDV-T1-E3 1N TSOP6 W/D

D

6

S

2
1

G

3

13

D

2

G

S

20mil

3 3

ON_OFF 28
51ON# 27,32

C435
1U_0805_25V4Z~D

@

F4

0.75A_24V_1812L075-24DR

45

20mil

R373 1.5M_0402_5%@

Q40
MMBF170-7-F NPN SOT-23

1 2

12

KB_BL_PWM

20mil

R305

0_0805_5%

12

@

D15
RLZ20A_LL34

12

BKLT_KB_DET

B

+5VS_KBL

BKLT_KB_DET

12

R395
100K_0402_5%

+5VS_KBL

JKB2

1

1

2

2

3

3
44GND

TYCO_2041084-4

CONN@

20mil

GND

C

INT_KB_Conn.1

KSI[0..7]
KSO[0..16]

DIAG_LOOP3

KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10

USB_DETECT#27
BATT_CHG_LED#28
BATT_LOW_LED#28
PWR_BTN_LED#28

USBSW_EN2#28

DIAG_LOOP328

KSI[0..7]28

KSO[0..16]28

+3VS

12

R157
10K_0402_5%

BKLT_KB_DET#

13

D

Q42

2

MMBF170-7-F NPN SOT-23

G

S

5
6

BKLT_KB_DET# 28

B to B Conn.

IEEE 1394 Port

JKB1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

TYCO_3-2041084-0

USB20_N113
USB20_P113

USB20_N213
USB20_P213

SATA_A1_TXP13

SATA_A1_TXN13

SATA_A1_RXN13
SATA_A1_RXP13

IEEE_TPB1N26
IEEE_TPB1P26

IEEE_TPA1N26
IEEE_TPA1P26

USB_OC#113
USB_OC#213

USB_EN#27,28
USBSW_EN#28
USB_EN2#28

GND
GND

D

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5

31
32

USB20_N1
USB20_P1

USB20_N2
USB20_P2

SATA_A1_TXP
SATA_A1_TXN

SATA_A1_RXN
SATA_A1_RXP

IEEE_TPB1N
IEEE_TPB1P

IEEE_TPA1N
IEEE_TPA1P

USB_OC#1
USB_OC#2
USB_EN#
USBSW_EN#
USB_EN2#
USB_DETECT#
BATT_CHG_LED#
BATT_LOW_LED#
PWR_BTN_LED#
PWR_ON-OFF_BTN#
USBSW_EN2#

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

DIAG_LOOP3

For EMI

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

61
62

KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16

C542 100P_0402_25V8K
C543 100P_0402_25V8K
C544 100P_0402_25V8K
C545 100P_0402_25V8K
C546 100P_0402_25V8K
C547 100P_0402_25V8K
C548 100P_0402_25V8K
C549 100P_0402_25V8K
C550 100P_0402_25V8K
C551 100P_0402_25V8K
C552 100P_0402_25V8K
C553 100P_0402_25V8K C567 100P_0402_25V8K
C554 100P_0402_25V8K
C555 100P_0402_25V8K

JBTB1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

GND
GND

E-T_1001-F60E-03R

CONN@

E

C556 100P_0402_25V8K
C557 100P_0402_25V8K
C558 100P_0402_25V8K
C559 100P_0402_25V8K
C560 100P_0402_25V8K
C561 100P_0402_25V8K
C562 100P_0402_25V8K
C563 100P_0402_25V8K
C564 100P_0402_25V8K
C565 100P_0402_25V8K
C566 100P_0402_25V8K

+5VALW

+3VALW
+MIC1_VREFO

MIC_JD
MIC_RIGHT
MIC_LEFT

HP2_JD
HP2_RIGHT
HP2_LEFT

HP1_JD
HP1_RIGHT
HP1_LEFT

TWSPK_R1
TWSPK_R2

MIC_JD 25
MIC_RIGHT 25
MIC_LEFT 25

HP2_JD 25
HP2_RIGHT 25
HP2_LEFT 25

HP1_JD 25
HP1_RIGHT 25
HP1_LEFT 25

TWSPK_R1 25
TWSPK_R2 25

Tweeter C hannel R output

Touch PAD/B Conn.

CONN@

+5VS

TP_DATA28
TP_CLK28

1

C440

0.01U_0402_16V7K

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

2

D

TP_DATA
TP_CLK

1

1

C442100P_0402_25V8K

C441100P_0402_25V8K

2

2

Custom

Date: Sheet

TYCO_2041084-4

6

44GND

3

5

3

GND

2

2

1

1

JTP1

2

3

D16
PESD5V0U2BT 3P C/C SOT23 ESD

1

Title

Size Document Number Rev

Compal Electronics, Inc.

PWR_OK/BTN/TP

LA-4631P

E

of

29 42Tuesday, Fe b r u a r y 24, 2009

1.0

A

B

C

D

E

+5VALW to +5VS Transfer+3VALW to +3VS Transfer

C506

1

S

2

S

3

S

4

G

+3VS+3VALW

10U_0805_10V4Z~N

1

1

C498

2

2

0.1U_0402_16V4Z~N

C499

U43

8

S

D

7

S

D

6

1

C500

2

10U_0805_10V4Z~N

RUNON 5VS_GATE

S

D

5

G

D

AO4478L 1N SO8

1 2

R464
47K_0402_5%

1

2

B+_BIAS

12

R461

330K_0402_5%

1 1

SUSP

2

G

1

2

RUNON 3VS_GATE

13

D

Q18

SSM3K7002FU_SC70-3

S

U42

8

D

7

D

6

D

5

D

C497

AO4478L 1N SO8

10U_0805_10V4Z~N

1 2

R463
100K_0402_5%

1

0.01U_0402_25V7K~N

2

+5VS+5VALW

1
2
3
4

C507

0.01U_0402_25V7K~N

1

2

0.1U_0402_16V4Z~N

C502

1

C503
10U_0805_10V4Z~N

2

SUSP

+1.05VALW to +VCCP Transfer

1
2
3
4

0.1U_0402_16V4Z~N

+VCCP+1.05VALW

10U_0805_10V4Z~N

1

C504

2

B+_BIAS

2

G

1

R462

C501

1 2

2

10U_0805_10V4Z~N

47K_0402_5%

1.05VS ON 1.05VS_GATE

1 2

R465
100K_0402_5%

13

D

Q19

SSM3K7002FU_SC70-3

S

U44

8

S

D

7

S

D

6

S

D

5

G

D

AO4430L 1N SO8

1

C508

0.01U_0402_25V7K~N

2

1

C505

2

+3VALW TO +3V_LAN

+3VALW

U45

8

S

D

7

S

D

6

S

D

12

1

C513

2

10U_0805_10V4Z

2

G

5

D

AO4478L 1N SO8

13

D

Q23

S

G

0_0402_5%~D

1 2

12

R472

1

C512

B+_BIAS

STB_LAN#28

2

10U_0805_10V4Z

R470
47K_0402_5%

2N7002_SOT23

2 2

1
2
3
4

R503

332K_0402_1%

+3V_LAN

1

C510

C511

2

1U_0603_10V4Z

10U_0805_10V4Z

1

C516

0.1U_0603_25V7K

2

+1.5V to +1.5VS Transfer

B+_BIAS

1

2

Q21

R467
470_0805_5%

1 2
13

D

S

STB_LAN#

2

G

2N7002_SOT23

SUSP

12

13

D

2

G

S

+1.5V +1.5VS

U46

8

R469

D

7

D

6

D

5

D

AO4478L 1N SO8

R466
100K_0402_5%~D

1 2

0_0402_5%~D

Q22

SSM3K7002FU_SC70-3

1

S

2

S

3

S

4

G

1

C515
470P_0402_50V7K~D

2

20K_0402_5%~D

10U_0805_10V4Z~D

12

R468

C514

1

2

+3VALW to +3V_DP Transfer

B+_BIAS

12

@

R557

330K_0402_5%

RUN_DP 3DP_GATE

13

SUSP

D

2

G

S

@

Q46

SSM3K7002FU_SC70-3

1

@

C609

2

10U_0805_10V4Z~N

1 2

R558

@

100K_0402_5%

+3VS

R1278

0_0805_5%

1 2

U47

8

D

7

D

6

D

5

D

AO4478L 1N SO8 @

1

C612

@

0.01U_0402_25V7K~N

2

1

S

2

S

3

S

4

G

0.1U_0402_16V4Z~N

+3V_DP+3VALW

10U_0805_10V4Z~N

@

1

C610

2

@

1

C611

2

+CPU_CORE

3 3

SYSON23,28,35

4 4

SUSP

SUSP#23,28,36,37

1 2

C509 0.1U_0402_16V4Z~N

+3VALW

12

R471

100K_0402_5%

SYSON#

13

1 2

SUSP

SUSP#

2

G

R473
10K_0402_5%

2

G

R478
10K_0402_5%

1 2

D

S

SYSON

A

+VCCP

Q24
SSM3K7002FU_SC70-3

+5VALW

12

R474
100K_0402_5%

13

D

Q25
SSM3K7002FU_SC70-3

S

SUSP

+VCCP

2

G

C

12

R485
470_0402_5%

13

D

Q27

S

SSM3K7002FU_SC70-3

+0.75VS

12

R480
470_0402_5%

13

SUSP

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

D

2

G

S

Q30
SSM3K7002FU_SC70-3

D

Discharge Circuit

+1.5V

12

R531
470_0402_5%

13

2

G

2

G

D

S

+3V_WLAN

12

13

D

S

Q35
SSM3K7002FU_SC70-3

R484
470_0402_5%

Q34
SSM3K7002FU_SC70-3

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SYSON#

SUSP

B

SUSP

SUSP

+1.5VS

12

13

D

2

G

S

+5VS

12

13

D

2

G

S

R483
470_0402_5%

SUSP

Q33
SSM3K7002FU_SC70-3

R481

470_0402_5%

Q31
SSM3K7002FU_SC70-3

Title

DC/DC Circuits

Size Document Number Rev

Custom

LA-4631P

Date: Sheet

+1.8VS

12

R476
470_0402_5%

13

D

2

G

Q28

S

SSM3K7002FU_SC70-3

+3VS

12

R482

470_0402_5%

13

SUSP

D

2

G

S

Q32
SSM3K7002FU_SC70-3

Compal Electronics, Inc.

E

1.0

of

30 42Tuesday, Fe b r u a r y 24, 2009

5

D D

FD3

FD2

H_2P2

FD1
FIDUCAL

@

H1
HOLEA@

FIDUCAL

@

@

1

1

1

FIDUCAL

1

FD4
FIDUCAL

@

1

4

3

2

1

H5

H2

H_2P8

C C

HOLEA@

1

H4
HOLEA@

1

H6

HOLEA@

HOLEA@

1

H7

H8

HOLEA@

HOLEA@

1

1

1

H11

H10
HOLEA@

1

H12

HOLEA@

HOLEA@

1

H13
HOLEA@

1

1

11pcs

H19

H_3P0

H_3P2

B B

HOLEA@

H21
HOLEA@

H14
HOLEA@

H_4P2

H20
HOLEA@

1

1

1

1

H22
HOLEA@

1

H15
HOLEA@

H17
HOLEA@

1

H16
HOLEA@

1

H18
HOLEA@

1

1

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Screws

LA-4631P

1

31 42Thursday, Fe br ua ry 19, 2009

1.0

of

5

4

3

2

1

PC1

2200P_0402_50V7K~D

ADPIN

PL1

PJPDC1

1

1

2

2

3

3

4

4

5

D D

C C

5

6

6

7

GND

8

GND

ACES_88299-0600

@

BATT+

51ON#27,29

PD3

12

RLS4148_LL34-2

CHGRTCP

PR11

100K_0402_5%~D

PR12

22K_0402_5%~D

1 2

12

12

PC3

PC2

100P_0402_50V8J~D

PL2

BLM18BD102SN1D_0603~D

PJP1
JUMP_43X118@

2

112

12

12

PC11

0.22U_1206_25V7K

51ON#_Gate

12

PQ1

S TR BSS84 1P SOT-23 W/D

13

32.8

2

DOCK_PSIDPSID

VIN

PD2

RLS4148_LL34-2

1 2
12

PR10

33_1206_5%~D

12

PC12

0.1U_0603_25V7K~D

12

1000P_0402_50V7K~D

VS

FBMJ4516HS720NT_1806~D

12

PC5

PC4

100P_0402_50V8J~D

1 2

1000P_0402_50V7K~D

12

PC6

100P_0402_50V8J~D

VIN

VIN

12

32.3

@

5
6

PR8

19.6K_0402_1%~D

+

-

@

12

8

@

P

G

LM393DR_SO8

4

12

PC7

1000P_0402_50V7K~D

PC9

@

12

0.1U_0402_16V7K~D

@

PR4

82.5K_0402_1%~D
PR6

22K_0402_1%~D@

1 2

12

@

PC10
1000P_0402_50V7K~D

PU1B

7

O

1 2

VinDe_INN41
VinDe_Ref

Vin Detector
Max. typ. Min.

L-->H 18.234 17.841 17.449
H-->L 17.597 17.210 16.813

56K_0402_5%~D@

1 2

PR2
1M_0402_1%~N@

1 2

VS

8

@

PU1A

3

P

+

2

-

G

LM393DR_SO8

4

PR9

@

10K_0402_5%~D

12

PR1

O

PC8

@

12

1

0.01U_0402_25V7K~D

VinDe_Out

RLZ4.3B_LL34

RTCVREF

3.3V

PD1

VIN

12

12

@

@

PR5
10K_0402_5%~D

PR3

@

1K_0402_5%~D

1 2

12

@

PR7
10K_0402_5%~D

ACIN 14,28,33

12

+1.8VSP

PR13
200_0805_5%

12

PC14
1U_0805_25V4Z~D

+3VALW+5VALW

2

PR17

PD4

3

DA204U_SOT323~D

1

+5VALW

12

PR16

PR19

@

10K_0402_1%~D

PR21

1 2

10K_0402_1%~D@

Title

DCIN / Precharge

Size Document Number Rev

Date: Sheet

1 2

2.2K_0402_5%~D

+5VALW

PD6

DA204U_SOT323~D

KCM00

PS_ID 28

2

3

1

PSID_DISABLE# 28

1.0Custom

of

1

32 10Tuesday, Fe b r u a r y 24, 2009

PR15

@

1 2

0_0402_5%~D

33_0402_5%~D

S

1 2

SSM3K7002FU_SC70-3

G

2

C

PQ3
MMST3904-7-F_SOT323~D

3 1

2

DOCK_PSID

PJP5
JUMP_43X118@

2

112

PJP2
JUMP_43X118@

112

PJP7
JUMP_43X118@

112

PJP9
JUMP_43X118@

112

PJP11
JUMP_43X118@

112

PJP13
JUMP_43X118@

112

4

+1.05VALW

2

2

+1.0VS

2

2

+0.75VS

Security Classification

2

+1.8VS

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

1

PR18

3

@

PD5
SM24_SOT23

2006/10/1 2007/5/01

1 2

100K_0402_1%~D

PR20

1 2

15K_0402_1%~D

Compal Secret Data

Deciphered Date

PQ2

D

1 3

2

B

E

RTCVREF

PU3

3

PJP3
JUMP_43X118@

112

PJP4
JUMP_43X118@

112

PJP6
JUMP_43X118@

112

PJP8
JUMP_43X118@

112

PJP10
JUMP_43X118@

112

PJP12
JUMP_43X118@

112

PJP14
JUMP_43X118@

112

5

OUT

#SHDN

4

5/3+

GND

2

2

2

2

2

2

2

2

B B

A A

12

PC13

4.7U_0805_6.3V6K~D

+5VALWP

+3VALWP

+1.5VP

MAX1615_IN

1

IN

MAX1615_#SHDN

5

MAX1615EUK+_SOT23-5~D

+5VALW

+3VALW

+1.5V

1 2

PR14 0_0402_5%~D

+1.05VALWP

+1.0VSP

+0.75VSP

A

B

C

D

E

PQ4

VIN

12

1 1

PR24

3.3_1210_5%~D

12

PR25

3.3_1210_5%~D

PC27

2.2U_0805_25V6K

1 2

1 2

90W adapter
Icharge=(Vsrset/Vvdac)*(0.1/PR222)=3.3A

2 2

Iadapter=(Vacset/Vvdac)*(0.1/PR217)=3.34A
Input OVP : 22.3V

FDS4435BZ_SO8

8

D

7

D

6

D

5

D

PC15

0.01U_0603_50V7K~D

PR28
340K_0402_1%~D

1 2

ACDET

PR32

54.9K_0402_1%

1 2

PR34
340K_0402_1%~D

1 2

OVPSET

1

S

2

S

3

S

4

G

PC21

1 2

CP setting

Input UVP : 16.98V

ACGOOD#

PR35

54.9K_0402_1%

1 2

SI2301BDS-T1-E3_SOT23-3

PR36

100K_0402_1%~D

1 2

PC40

0.1U_0603_25V7K~D

GATE

2

12

ACSET

Fsw : 300KHz

VREF

PR37
47K_0402_1%~D

1 2

13

D

S

CELLS

CELLS

2

G

PQ10
2N7002 1N SOT-23

GND
VREF

3 Cell
4 Cell

3cell/4cell# 39

Cells selector

3 3

+COINCELL

PR46

1 2

B+

100_0805_5%~D

+5VALW

PR49

1 2

12

1 2

S DIO 1SS355

220K_0402_5%

470K_0402_5%~D

PQ16

2

G

A

PD8

PR51

4 4

1 2

32.8

220K_0402_5%

12

PR53

PC45

0.1U_0603_25V7K~D

PJP16

1

1

2

2

3

3

4

GND

5

GND

MOLEX_53780-0370~D

@

PQ12

S TR BSS84 1P SOT-23 W/D

13

32.8

PC43

2

13

D

SSM3K7002FU_SC70-3

S

CHGVADJ28

B+_BIAS

1 2

0.1U_0805_25V7M~N

PQ5

FDS4435BZ_SO8

1
2
3
4

12

PR26

100K_0402_1%~D

0.01U_0402_25V7K~D

ACDRV

124K_0402_1%

1 2

VREF

0.01U_0402_25V7K~D

@

PQ9

1 3

S
S
S
G

PR31

PC31

D
D
D
D

1U_0603_10V6K~D

0.015_2512_1%

8
7
6

1

5

2

0.1U_0402_16V7K~D

1 2

12

PC25

0.1U_0603_25V7K~D

12

12

PC38

PR22

PC16

ACP

ACSET

PR33
100K_0402_1%~D

1 2

0.47U_0603_16V7K~N

VREF

12

/BATDRV

REGN

12

PR43

PR44

210K_0402_1%~D

1 2

0_0402_5%~D@

VADJ

12

PR45
499K_0402_1%~D

CHGVADJ Battery Voltage/per cell

0V 3V

3.3V 4.2V

B

4
3

PU4

VADJ

ACN

12

ACOP

PC34

CHGEN#

1

CHGEN

PC26

0.1U_0603_25V7K~D

2

ACN

3

ACP

4

ACDRV

5

ACDET

6

ACSET

7

ACOP

8

OVPSET

9

AGND

10

VREF

11

VDAC

12

VADJ

13

ACGOOD

14

BATDRV

BQ24751ARHDR_QFN28_5X5

28

PVCC

27

BTST

26

HIDRV

25

PH

24

REGN

23

LODRV

22

PGND

21

LEARN

20

CELLS

19

SRP

18

SRN

17

BAT

29

TP

16

SRSET

15

IADAPT

ADP_I28

ACOFF

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

B+

PL13

SUPPRE_TDK MPZ1608S300AT 0603

1 2

PC17

0.1U_0805_25V7K

PVCC

1 2

PR27

2.2_0603_5%~D

BTST

1 2

DH_CHG

LX_CHG

PD7

12

RLS4148_LL34-2

REGN

12

PC32
1U_0603_10V6K~D

DL_CHG

ACOFF 28

CELLS

SRP
SRN

12

PC39

0.1U_0603_25V7K~D

PQ6

FDS6690AS_NL_SO8

1 2

PC28

0.1U_0603_25V7K~D
PQ8

FDS6690AS_NL_SO8

CHG_B+

578

578

1 2

3 6

241

10UH_SIL1045RA-100PF_4.5A_30%

1 2

12

PR30

4.7_1206_5%~D

12

PC33

3 6

241

PC224.7U_1206_25V6K~D

12

PL3

680P_0603_50V8J~D

ICHG setting

PR38

12

12

IADAPT

1 2

PR42

10_0603_5%~D

PC42

100P_0402_50V8J~D

100K_0402_1%~D

1 2

PC44

0.1U_0402_16V7K~D

2006/10/1 2007/5/01

PR39
100K_0402_1%~D

12

VREF

12

PR50

12

PR52
340K_0402_1%~D

Compal Secret Data

2

G

60.4K_0402_1%~D

12

@

IREF Current

0V 0A

3.3V 3A

VREF

12

PR47
200K_0402_1%~D

13

D

PQ15
2N7002 1N SOT-23

S

Deciphered Date

PC41

0.01U_0402_25V7K~D

GATE

13

D

PQ13

2

2N7002 1N SOT-23

G

S

D

PC181000P_0402_50V7K~D

1 2

IREF 28

PC201000P_0402_50V7K~D

PC194.7U_1206_25V6K~D

12

PC29

1 2

10U_1206_25V6M~D

12

PC36

0.1U_0603_25V7K~D

12

PR23

PC24

PC234.7U_1206_25V6K~D

1 2

/BATDRV

PR29

0.02_2512_1%

1
2

PC35

0.1U_0402_16V7K~D

1 2

PR40

100K_0402_1%~D

ACGOOD#

FSTCHG28

Title

Size Document Number Rev

B

Date: Sheet

100K_0402_1%~D

1 2

0.01U_0402_25V7K~D

4
3

12

RTCVREF

12

3

4

G

5

PC37

0.1U_0603_25V7K~D

@

VREF

100K_0402_1%~D

1 2

13

D

2

G

S

VREF

PR48
100K_0402_1%~D

1 2

13

D

2

G

S

S1S2S

D8D7D6D

12

PR41

PQ11
2N7002 1N SOT-23

CHGEN#

PQ14
2N7002 1N SOT-23

Compal Electronics, Inc.

Charger

KCM00

E

PQ7
FDS4435BZ_SO8

12

PC30

10U_1206_25V6M~D

BATT+

@

PC171

10U_1206_25V6M~D

ACIN 14,28,32

of

33 10Tuesday, Fe b r u a r y 24, 2009

1.0

B+

5

PJP17
JUMP_43X118@

2

112

4

ISL6237_B+

PR54

0_0805_5%

1 2

3

2

1

ISL6237_B+

FDS8884_SO8

PR67

267K_0402_1%~D

12

PR68

12

309K_0402_1%

PQ18

PQ19

578

3 6

241

578

3 6

241

VL

POK

12

12

PC50

PC49

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

PL4

3.3UH +-20% FDVE1040-3R3M 11.3A

12

PR56

4.7_1206_5%~D

12

PC60

680P_0603_50V8J~D

5VALWP

Imax=7.5A

Iocp=9.8A

Fsw=400kHz

12

PC51

2200P_0402_50V7K~D

12

PR60

PR62

1 2

61.9K_0402_1%~D

1 2

9.76K_0402_1%~D

+5VALWP

12

@

PC169

1

+

10U_1206_25V6M~D

PC61
330U_D3L_6.3VM_R25M

2

1 2

1U_0603_10V6K~D

7

3

LDO

PVCC

VCC

UGATE1

BOOT1

PHASE1

LGATE1

PGND

OUT1

FB1

BYP

SKIP

POK2

POK1

ILIM1

ILIM2

GND

ISL6237IRZ-T_QFN32_5X5

21

PR74

@

0_0402_5%~D

VL

12

PC59

19
15
17

16

18

22

10

11

9

29

28

13

12

31

PC54

1U_0603_10V6K~D

4.7U_0805_6.3V6K~D

1 2

DH5DH3

2.2_0603_5%~D

0.1U_0603_25V7K~D

LX5

DL5

FB5

6237_SKIP

PR64 0_0402_5%~D

1 2

ILM1

ILIM2

FDS6690AS_NL_SO8

PR58

12

PC57

1 2

PR63 0_0402_5%~D@

12

Rds(on) = 15m ohm(max) ; Rds(on) = 12m ohm(typical)

12

12

PC48

2200P_0402_50V7K~D

12

PR55

4.7_1206_5%~D

12

PC58

680P_0603_50V8J~D

3 6

241

3 6

241

578

PQ17
FDS8884_SO8

578

PQ20

FDS6690AS_NL_SO8

1 2

0.1U_0603_25V7K~D

PR57

12

2.2_0603_5%~D

PC56

0.1U_0603_25V7K~D

2VREF_ISL6237

1 2

PC62 0.22U_0603_10V7K~D

PC52

1 2

PU5

33

BST3A BST5A

26
24

LX3

25

DL3

23

FB3

30

32

VL

1

8

6

VIN

TP
UGATE2
BOOT2

PHASE2

LGATE2

OUT2

REFIN2

REF

LDOREFIN

PC53

12

PC46

D D

+3VALWP

12

@

PC168

C C

1

+

PC55
330U_D3L_6.3VM_R25M

2

10U_1206_25V6M~D

3.3UH +-20% FDVE1040-3R3M 11.3A

PR59

0_0402_5%~D

1 2

PR61

1 2

@

10K_0402_1%~D

PC47

4.7U_0805_25V6K~D

PL5

1 2

4.7U_0805_25V6K~D

Rds(on) = 15m ohm(max) ; Rds(on) = 12m ohm(typical)

6237_EN2

1 2

12

20

14

27

PR70

1 2

2VREF_ISL6237

NC

4

EN_LDO

EN1

EN2

0_0402_5%~D

PC64

1U_0603_10V6K~D

5

12

NC

6237_NC

TON

2

6237_TON

12

2VREF_ISL6237

3.3VALWP

Imax=8.5A

VS

Iocp=11A

B B

A A

Fsw=300kHz

PD9

RLZ5.1B_LL34

1 2

1 3

MAINPW O N39

2

PD10

1 2

S DIO 1SS355

PR65

100K_0402_1%~D

1 2

PR66

1 2

200K_0402_5%~D

PR72

0_0402_5%~D

PQ21

S TR BSS84 1P SOT-23 W/D

PC63

0.22U_0603_25V7-K

1 2

VL

PR71

1 2

806K_0603_1%

12

PC65

12

PR69

@

0_0402_5%~D

PR73

47K_0402_5%~D@

1 2

0.047U_0603_16V7K~D

@

EN_LDO

6237_EN1

PC66

0.047U_0402_16V7K~N

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2006/10/1 2007/05/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

+3VALWP, +5VALWP

Size Document Number Rev

Date: Sheet

2

KCM00

Tuesday, February 24, 2009

1

of

34 10

1.0Custom

5

D D

PJP18

B+

C C

SYSON23,28,30

B B

JUMP_43X118@

112

PR81
22K_0402_1%~D

1 2

4

2

PC67

@

12

10U_1206_25V6M~D

12

6269_1.5V

12

PC71

2.2U_0603_6.3V6K~D

PC75

0.1U_0402_16V7K~D

12

PC68

10U_1206_25V6M~D

6269_B+

PR79

0_0402_5%~D

1 2

12

PC76

6269_1.5V

PR75

10K_0402_1%~D

PU6

1

VIN

2

VCC

3

FCCM

4

EN

12

PR84

49.9K_0402_1%~D

12

PC78

22P_0402_50V8J~D

2200P_0402_50V7K~D

3

12

17

16

15

GND

PHASE

PGOOD

COMP5FB6FSET

PR85

57.6K_0402_1%~D

PHASE_1.5V

14

UG

7

12

PR76

1 2

2.2_0603_5%~D

BOOT_1.5V

13

BOOT

12

PVCC

11

LG

10

PGND

9

ISEN

VO

8

12

PC77

0.01U_0402_25V7K~D

UG_1.5V

1 2

PC69

+5VALW

0.1U_0603_25V7K~D

12

PR77

0_0603_5%~D

PR78 4.7_0603_5%~D

6269_1.5V

1 2

PC70

1 2

2.2U_0603_6.3V6K~D

LG_1.5V

ISEN_1.5V

1 2

PR82

7.15K_0402_1%~D

ISL6269ACRZ-T_QFN16_4X4

PQ23

SI4430BDY_SO8

2

578

PQ22

SI4172DY-T1-GE3 1N

3 6

241

1.5UH +-20% FDVE1040-H-1R5M=P3 17.1A

578

3 6

PR80

4.7_1206_5%~D

1 2

PC74
680P_0603_50V8J~D

1 2

241

PL6

1 2

SI4430BDY
Rds(on)=4.8mohm~6mohm

1.5VP

Imax=13A

Iocp=16.9A

Fsw=231kHz

1

+

PC72
220U_D2_4VM~D

2

PR83
2K_0402_1%~D

1 2

12

PR86

1.33K_0402_1%~D

+1.5VP

1

+

2

1

+1.5VP

PC73
220U_D2_4VM~D

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

3

2006/10/1 2007/05/30

Compal Secret Data

Deciphered Date

2

Title

Size Docu me n t N u m ber Re v

Date: Sheet

Compal Electronics, Inc.

Tuesday, February 24, 2009

1.5VP

KCM00

1

35 10

1.0

of

5

PGOOD1 PGOOD2 1K

PJP19
JUMP_43X118@

B+

D D

C C

+1.05VALWP

12

12

12

PC170

PC123

10U_1206_25V6M~D

10U_1206_25V6M~D

2

112

PC83

470P_0402_50V8J~D

1UH_FDV0630-1R0M-P3_10.3A_20%

1

+

PC92

2

220U_X_2VM_R7M~D

12

PC84

680P_0402_50K X7R~D

PR97

1 2

12.1K_0402_1%~D

PC91

.01U_0402_16V7K~D

1 2

PR103

12.1K_0402_1%~D

PL7

1 2

12

PC173

2200P_0402_50V7K~D

1000P_0402_50V7K~D

PC87

12

68K_0402_1%~D

ISL6228_B+

12

PC89

1 2

12

PR106

4.7_1206_5%~D

12

ISL6228_B+

681_0402_5%~D
PR95

1 2

PR96

12

12

PC90

4.7U_1206_25V6K~D

PC97

680P_0603_50V8J~D

4.7U_1206_25V6K~D

86.6K_0402_1%~D

578

PQ24
FDS8884_SO8

3 6

241

578

PQ25
FDS6690AS_NL_SO8

3 6

241

0.1U_0402_16V7K~D

DCR 10m ohm(max)

+1.05VALWP

Imax=7A

B B

Iocp=9.1A

Fsw=303kHz

PC98

PR94

4

串 電組

1 2

1.05VALWP_EN

12

0_0603_5%~D

+5VALWP

PR89

1K_0402_1%~D

@

LX_1.05VALWP

UG_1.05VALWP

BST_1.05VALWP

12

PR108

3

PC80

PC79

1U_0402_6.3V6K~D

@

上

+5VALWP +5VALWP

12

1000P_0402_50V7K~D

+5VALWP

1U_0402_6.3V6K~D

LG_1.05VALWP

0.1U_0603_25V7K~D

ISL6228_B+ ISL6228_B+

PC85

7

PGOOD1

8

FB1

9

VO1

10

OCSET1

11

EN1

12

PHASE1

13

UGATE1

14

BOOT1

PVCC115LGATE116PGND117PGND218LGATE219PVCC220BOOT2

PC102

1 2

PR87

2.2_0603_1%~D

PC81

PR90

12

10_0603_1%

12

PR92

22K_0402_1%~D

1 2

6

FSET1

ISL6228HRTZ-T_QFN28_4X4

12

5

VIN1

PU7

12

1U_0402_6.3V6K~D

12

PR88

12

4

1 2

2.2_0603_1%~D

12

PC82

0.1U_0603_25V7K~D

PR91

10_0603_1%

PC86

1000P_0402_50V7K~D

12

1 2

3

2

1

GND_T

VIN2

VCC2

VCC1

+5VALWP

PC103
1U_0402_6.3V6K~D

1 2

FSET2

PGOOD2

FB2

VO2

OCSET2

EN2

PHASE2

UGATE2

21

BST_1.0VSP

12

PR93

18.2K_0402_1%~D

29

28

1K_0402_1%~D

@

27

26

25

24

23

UG_1.0VP

22

PR111

1 2

2.2_0603_5%~D

LG_1.0VSP

PR98

PR105

0_0402_5%~D

1 2

PC93

1 2

0.01U_0402_25V7K~D@

12

+5VALWP

SUSP# 23,28,30,37

LX_1.0VSP

PC100

1 2

0.1U_0402_16V7K~D

578

3 6

578

3 6

PQ26
FDS8884_SO8

241

SI4386DY_SO8

241

FB2_+1.0VSP

ISL6228_B+

PQ27

12

2

1 2

12

PC94

4.7U_1206_25V6K~D

12

PR110

4.7_1206_5%~D

12

PC101

680P_0603_50V8J~D

PR99

86.6K_0402_1%~D

PC95

4.7U_1206_25V6K~D

681_0402_5%~D

1000P_0402_50V7K~D

PR100

PC88

1 2

12

PR101

1 2

68K_0402_1%~D

PR102

1 2

11K_0402_1%~D

.015U_0402_16V7K~D

PC96

1 2

PR107

11K_0402_1%~D

1 2

PL8

1 2

0.75UH 20% FDVE0630-R75M=P3 13.4A

1

PR109

@

0_0402_5%~D

1 2

PR189
0_0402_5%~D

1 2

(0.75V~1.05V)

1

+

PC99

2

220U_X_2VM_R7M~D

12

12

PC167

10U_1206_25V6M~D

+1.0VS

+1.0VSP

@

DCR 6.2m ohm(max)

PC172

1.0VSP

10U_1206_25V6M~D

Imax=9.3A

Iocp=12.1A

Fsw=366kHz

PR112

+3VALWP

A A

5

0_0402_5%~D

1.05VALWP_EN

12

12

PC104

@

0.01U_0402_25V7K~D

4

VID2 VID1 VID0

LLL
LL
LL

H

L

HH
LL

H

L

HH

H

HH
L
HHH

voltage

1.05

0.98

0.90

0.87

0.80

0.79

0.77

0.75

12

PR113

PR116

@

1 2

10K_0402_1%~D

54.9K_0402_1%

13

D

2

G

S

PQ28

SSM3K7002FU_SC70-3

1 2

FB2_+1.0VSP

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

3

PR119

100K_0402_5%~D

1 2

12

PC105

PR122

0.1U_0402_16V7K~D

@

22K_0402_1%~D

2006/10/1 2007/5/01

PQ29

Compal Secret Data

Deciphered Date

12

PR114

PR117

@

1 2

10K_0402_1%~D

200K_0402_1%~D

13

D

2

G

S

SSM3K7002FU_SC70-3

PR123

@

1 2

2

12

22K_0402_1%~D

PR120
100K_0402_5%~D

1 2

PC106

0.1U_0402_16V7K~D

+1.0VSP

+3VALW+3VALW+3VALW

12

PR115

PR118

@

1 2

10K_0402_1%~D

374K_0402_1%

13

D

2

G

S

PQ30

SSM3K7002FU_SC70-3

1 2

Title

Size Docu me n t N u m ber Re v

Date: Sheet

1.05VALWP/+1.0VSP

Tuesday, February 24, 2009

KCM00

PR124

@

22K_0402_1%~D

PR121

100K_0402_5%~D

1 2

12

PC107

0.1U_0402_16V7K~D

1

MCP_CORE_VID014MCP_CORE_VID114MCP_CORE_VID214

of

36 10

1.0

5

4

3

2

1

D D

+3VALW

SUSP#23,28,30,36

C C

PJP21

+1.5VP

+0.75VSP

10U_0805_10V6K~D

112

JUMP_43X118

@

12

PC117

2

12

PC116

10U_0805_10V6K~D

@

PJP20 JUMP_43X118

112

1 2

PR125 0_0402_5%~D

PC110

0.1U_0402_16V7K~D

12

PC114

@

2

4.7U_0805_6.3V6K~D

12

12

PC115

@

+5VALW

12

PC111
10U_1206_25V6M~D

4.7U_0805_6.3V6K~D

PU8 RT9025

VIN3VOUT

2

EN

4

VDD

12

PC112
1U_0402_6.3V6K~D

RT9026_MSOP10

PU9

1

VDDQSNS

2

VLDOIN

3

VTT

5

VTTSNS

PGND

4

GND

NC

GND

9

GND

VTTREF

GND

11

5

NC

PGOOD

GND

GND

8

VIN

S5
S3

6

7

ADJ

1

0.1U_0402_16V7K~D

PC108

@

12

12

PR126

3.01K_0402_1%~D

12

PR127

2.37K_0402_1%~D

+1.8VSP

12

PC109
10U_1206_25V6M~D

+1.8VSP
Imax=0.3A

10

8
6

9
7

PR128

12

0_0402_5%~D

PC119

0.1U_0402_16V7K~D

@

12

SUSP# 23,28,30,36

PC118

1U_0603_10V6K~D

12

PC113

0.1U_0402_16V7K~D

+3VALW

12

+0.75VSP
Imax=1.5A

B B

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/1 2007/05/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

+0.75VSP/ 1.8VSP

Size Document Number Rev

2

Date: Sheet

KCM00

Tuesday, Febr uary 24, 2009

1

37 10

1.0Custom

of

5

@

D D

DPRSLPVR14

H_DPRSTP#5,7

CLK_EN#

+3VS

+3VS

PR142

499_0402_1%~D

VGATE14,28

H_PSI#5

POW_MON

C C

VR_TT#

PR152 4.22K_0402_1%@

1 2

PC1331U_0603_10V6K~D

1 2

PR151 147K_0402_1%~D

1 2

PH1

1 2

100K_0603_1%_TH11-4H104FT@

1 2

PC1360.015U_0402_16V7K@

PR153 11.5K_0402_1%~D

1 2

PC142

1000P_0402_50V7K~D

1 2

PR156 6.81K_0402_1%~D

1 2

12

PR143

1 2

PR150 10K_0402_1%~D

1 2

PC1400.068U_0603_50V7K~N

1 2

1.91K_0402_1%~D

1 2

PC143 1000P_0402_50V7K~D

PR162 97.6K_0402_1%~D

1 2

B B

12

@

PR190

VCCSENSE5

PC148 220P_0402_50V7K~D

PR164

1 2

150K_0402_1%~D

PR166 1K_0402_1%~D

VSSSENSE5

PC145 470P_0402_50V7K~D

1 2

PC149 1000P_0402_50V7K~D

255_0402_1%~D

1 2

1 2

PR167 0_0402_5%~D

12

1 2

12

PR130 499_0402_1%~D

1 2

PR131 0_0402_5%~D

1 2

PR132 0_0402_5%~D

1 2

PR134 0_0402_5%~D

1 2

12

PC131

1U_0603_10V6K~D

1

PGOOD

2

VW

FB2_CPU

PSI#

3

PMON

4

RBIAS

5

VR_TT#

6

NTC

7

SOFT

8

OCSET

9

VW

10

COMP

11

FB

12

FB2

PMON

RBIAS

NTC
SOFT
OCSET

COMP
FB_CPU

12

PR163
1K_0402_1%~D

PC151 0.022U_0603_25V7K

1 2

PC152

0.022U_0603_25V7K

@

1 2

PR168 0_0402_5%~D

PC154 180P_0402_50V8J~D

1 2

1 2

PR171 1K_0402_1%~D

VCC_PRM

A A

PC156

0.22U_0603_16V7K~D

4

PC120

12

5600P_0402_25V7K

CLK_EN#_CPU

DPRSTP#_CPU

3V3_CPU

48

49

46

47

3V3

GND

CLK_EN#

DPRSTP#

VR_ON

12

PR133

0_0402_5%~D

VID6

VR_ON_CPU

DPRSLPVR_CPU

45

44

VR_ON

DPRSLPVR

ISL6262ACRZ-T_QFN48_7X7

CPU_VID6

12

12

PR1350_0402_5%~D

VID5

43

CPU_VID45CPU_VID3

CPU_VID5

12

PR1370_0402_5%~D

PR1360_0402_5%~D

VID4

14,28

12

VID3

VDIFF13VSEN14RTN15DROOP16DFB17VO18VSUM19VIN20GND21VDD22ISEN223ISEN1

DFB

RTN

VDIFF

DROOP

VSEN_CPU

12

PC153

0.022U_0603_25V7K

Vin_CPU

12

VSUM

PC150

0.1U_0603_25V7K~D

12

1 2

PR172 3.57K_0402_1%~D

PC155 0.068U_0603_50V7K~N

PC157 0.22U_0603_10V7K~D

12

1 2

PR170

12

5

5

CPU_VID25CPU_VID15CPU_VID0

12

12

12

PR1380_0402_5%~D

PR1400_0402_5%~D

PR1410_0402_5%~D

PR1390_0402_5%~D

VID0

VID1

VID2

VID037VID138VID239VID340VID441VID542VID6

BOOT1

UGATE1

PHASE1

PGND1

LGATE1

PVCC

LGATE2

PGND2

PHASE2

UGATE2

BOOT2

24

1 2

VDD_CPU

12

PR161 1_0603_5%~D
PC146
1U_0603_10V6K~D

PR165

1 2

10_0603_5%~D

12

PR169

2.61K_0402_1%~D

PH2
10KB_0603_ERTJ1VR103J

11K_0402_1%~D

1 2

3

+5VS

5

5

PR129
1_0603_5%~D

1 2

12

12

PC126

PC125

1U_0603_10V6K~D

0.01U_0402_25V7K~D

PC132

1 2

0.22U_0603_10V7K~D

PQ32

SI4430BDY_SO8

12

PC127

1U_0603_10V6K~D

3 5

241

5

5

D8D7D6D

S1S2S3G

4

4

SI4430BDY_SO8

36
35
34
33
32
31
30

BOOT_CPU1

UGATE_CPU1
PHASE_CPU1

LGATE_CPU1

PVCC_CPU

12

PC124

0.01U_0402_25V7K~D

PR144

1 2

2.2_0603_5%~D

LGATE_CPU2

29

BOOT_CPU2

2.2_0603_5%~D

+5VS

+CPU_B+

PHASE_CPU2

UGATE_CPU2

PR154

1 2

PC141

1 2

0.22U_0603_10V7K~D

PQ35

SI4430BDY_SO8

3 5

241

5

5

D8D7D6D

S1S2S3G

4

4

SI4430BDY_SO8

28
27
26
25

NC

PU10

29.1

ISEN1
ISEN2

2

12

@

PC128

10U_1206_25V6M~D

PQ31
SI7686DP_POWERPAK

12

D8D7D6D

PR145

PQ33

S1S2S3G

12

PC134

PQ34
SI7686DP_POWERPAK

12

D8D7D6D

PQ36

S1S2S3G

12

12

12

PC130

PC129

10U_1206_25V6M~D

10U_1206_25V6M~D

4.7_1206_5%~D

680P_0603_50V8J~D

PR146

12

PC137

10U_1206_25V6M~D

PR155

4.7_1206_5%~D

PC144
680P_0603_50V8J~D

+CPU_B+

12

3.65K_1206_1%

VSUM

12

PR157

VSUM

1

+

2

PR147

@

3.65K_1206_1%

PC121

10K_0402_1%~D

12

PR158

1

12

2200P_0402_50V7K~D

1
2

12

1_0402_5%~D

VCC_PRM

+CPU_B+

1
2

12

VCC_PRM

PL9

1 2

PC174

PC175

2200P_0402_50V7K~D

PR148

PR159
1_0402_5%~D

FBMJ4516HS720NT_1806~D

1

12

+

PC122

2

100U_25V_M~D

100U_25V_M~D

PL10 0.36UH_PCMC104T-R36MN1R17_30A_20%

4
3

12

PR149 0_0402_5%~D@

1 2

PC135

1 2

ISEN1

0.22U_0603_16V7K~D

12

PC138

PC139

10U_1206_25V6M~D

10U_1206_25V6M~D

PL11 0.36UH_PCMC104T-R36MN1R17_30A_20%

4
3

12

PR160 0_0402_5%~D@

1 2

10K_0402_1%~D

PC147

1 2

0.22U_0603_16V7K~D

ISEN2

B+

+CPU_CORE

Fsw=300kHz

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/1/15 2008/1/15

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

+CPU_CORE

KCM00

1.0

38 10Tuesday, February 24, 2009

1

of

5

D D

BATT+

PL12

FBMA-L18-453215-900LMA90T_1812~D

BATT+

1 2

12

12

PC160

0.01U_0402_25V7K~D

PC158

100P_0402_50V8J~D

PJPB1 battery connector

SMART
Battery:

1.BAT+

2.BAT+

C C

3.ID

4.B/I

5.TS

6.SMD

7.SMC

8.GND

9.GND

BATT++

12

PC159
1000P_0402_50V7K~D

200275MR009G10PZR_9P-T

11
10

GND
GND

PJP22

1
2
3
4

@

5
6
7
8
9

BATT++

12

PC161

100P_0402_50V8J~D

9
8
7
6
5
4
3
2
1

3cell/4cell#

+3VALWP

1 2

1 2

PR177

100_0402_5%~D

1 2

PR178

100_0402_5%~D

4

PD11

@

PR173
47K_0402_5%~D

3cell/4cell# 33

+3VALWP

3

DA204U_SOT323~D

BATT_B/I

2

1

BATT_SMD

EC_SMB_DA1 28

EC_SMB_CK1 28

PD12

DA204U_SOT323~D

@

BATT_SMC

PR175

1K_0402_5%~D

3

2

2

PD13

DA204U_SOT323~D

@

3

1

2

3

1

3

PD14

DA204U_SOT323~D

1

@

2

Battery Connect/OTP

1

Place clsoe to EC pin

BATT_TEMP

1 2

PR174

1K_0402_5%~D

12

1 2

PR176

6.49K_0402_1%~D

PC162

0.1U_0402_16V7K~D

1 2

@

+3VALWP

BATT_TEMP 28

CPU

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

BATT+

12

PR179
453K_0402_1%~D

VS

PC164

0.01U_0402_25V7K~D

BATT_IN

12

PR182

499K_0402_1%~D

12

PR187

86.6K_0402_1%~D

PC165

1000P_0402_50V7K~D

B B

PR185

10K_0402_1%~D

1 2

BATT_OVP28

BATT_OUT

7

PU11B

0

8

LM358ADR_SO8

5

P

+

6

-

G

4

12

VL VS

12

CPU

12

PR180

10.7K_0402_1%~D

PR184

61.9K_0402_1%~D

1 2

1 2

VL

12

PH3
100K_0603_1%_TH11-4H104FT

PR186

150K_0402_1%~D

150K_0402_1%~D

PR188

147K_0402_1%~D

1 2

OTP_IN+

OTP_IN-

12

PR181

3
2

12

PC166
1U_0603_10V6K~D

8

P

+

-

G

4

PC163

0.1U_0603_25V7K~D

1 2

OTP_OUT

1

0

PU11A
LM358ADR_SO8

PD15

1 2

S DIO 1SS355

VL

PR183
205K_0402_1%~D

1 2

MAINPWON 34

LI-3S :12.6V----BATT-OVP=1.1V
LI-4S :16.8V----BATT-OVP=1.5V
BATT-OVP=0.111*BATT+

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/1 2007/05/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

BATTERY CONN

Size Document Number Rev

2

Date: Sheet

KCM00

Tuesday, Febr uary 24, 2009

1

39 10

1.0Custom

of

5

4

3

2

1

Version Change List ( P. I. R. List )

Page 1/1

Request

Item Issue DescriptionDate

1

D D

2

3

4

p33 charger 08/10/15 c ompal meet PSL PQ16

5

p32 DCIN / Precharge 08/10/15 compal meet PSL PQ1

6

p33 charger 08/10/15 c ompal meet PSL PQ12

7

p34 +3VALWP/+5VALWP 08/10/15 c ompal meet PSL PQ21

8

p33 charger 08/10/15 c ompal meet PSL PR22 PR29

9

10

p33 charger 08/10/15 c ompal adjust charge current to 3.1A PR38

11

p33 charger 08/10/15 c ompal adjust CP set for ICPP function PR38

12

C C

B B

A A

p34 +3VALWP/+5VALWP 08/10/15 c ompal meet choke component current limit PL4 PL5

13

p32 DCIN / Precharge 08/10/15 compal meet PSL PL1

14

p38 CPU_CORE 08/10/15 compal meet PSL PL9

15

p39 BATTERY CONN 08/10/15 compal meet PSL PL12

16

17

18

p36 +1.05VALWP/1.0VP 08/10/22 compal Add remote sense function PR189

19

p36 +1.05VALWP/1.0VP 08/10/22 compal adjust output voltage pr94

20

p36 +1.05VALWP/1.0VP 08/10/22 compal PL8

21

22

23

ALL every power 08/10/22 c ompal reduce output ripple PC123 PC167 PC168 PC169 PC170

24

ALL every power 08/10/22 c ompal PR30 PR106 PR55 PR56 PR80 PR110 PR105 PR155sunbber for EMI request

25

ALL every power 08/10/22 c ompal PC33 PC58 PC60 PC74 PC97 PC101 PC134 PC144sunbber for EMI request

26

P34 P35 every power 08/10/22 c ompal PR57 PR58 Pr76increase boost resistor value form 0 ohm to 2.2 ohm for EMI request

27

p39 BATTERY CONN 08/12/03 compal adjust OTP set PR183

28

p33 charger compal DFX request PQ10 PQ11 PQ13 PQ14 PQ1508/12/03

29

p36 +1.05VALWP/1.0VP compal adjust +1.0VSP OCP set PR102 PR10708/12/03

30

p36 +1.05VALWP/1.0VP compal adjust +1.0VSP output voltage08/12/03 PR99

31

32

p39 BATTERY CONN 08/12/12 compal adjust OTP set PR183

p33 charger compal08/12/31 reduce AC-IN inrush current PR24 PR2533

p36 +1.05VALWP/1.0VP 08/12/31 compal34 PC173 PC174 PC175WWAN issue

p34 08/12/31 compal34 adjust +5VALWP voltage PR62 change frome 10k to 9.62k+3VALWP/+5VALWP

08/10/15 compal PQ2 p32 DCIN / Precharge meet PSL

08/10/22 compal PQ6 PQ8p33 charger design change

08/10/22p35 +1.5VSP compal reduce L/S MOS Vds PQ22

08/10/22 compal PL6

08/10/22p33 charger compal EMI request PL13

08/12/12 compal PQ22p35 +1.5VSP design change(already trail run in PT phase)

Owner

pu9p37 +0.75VSP/1.8VSP 08/10/15 c ompal source shortage

PQ6 PQ8compal08/10/15chargerp33 design change

PR127 PR124p37 +0.75VSP/1.8VSP 08/10/15 c ompal adjust 1.8V output voltage

design change

design changep35 +1.5VSP

Solution Description Rev.Page# Titl e

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

PW PIR-1

KCM00

1.0

of

40 10Tuesday, Fe b r u a r y 24, 2009

1

A

Braxton Power block

Battery OVP

Page 39

Turn Off

DC IN

CHARGER
CC:0A~3A
CV:16.8V(4cell)
CV:12.6V(3cell)
(BQ24751)

Page 33

Input
Switch

B+

Page 32

Battery

CPU CORE
OCP:54A
OVP:2V
(ISL6262A)

VR_ON

A A

Page 38

CPU OTP

Page 39

Turn Off

+3VALWP: TDC:8 . 5 A O C P :11A OVP:108%~114%
+5VALWP: TDC:7 . 5 A O C P :9.8A OVP:108%~114%
(ISL6237)

+3VALW

+1.5VP: TDC:13A OCP:16.9 A O V P:113%~119%
(ISL6269A)

+1.5VP

+1.05VALWP: T DC :7A OCP:9.1A O V P:113%~119%
+1.0VSP(0.75V~1.05V):TDC:9.3A OCP:12.1A OVP:113%~119%
(ISL6268)

+1.8VSP TDC:0.24A
(RT9025-25PSP)

+0.75VSP TDC:1.5A
(RT9026MSOP)

Page 34

Page 37

Page 35

Page 37

Page 36

Always

SUSP#

+1.5VP:SYSON

SUSP#

SUSP#

SUSP#

Title

<Title>

Size Document Number Rev

<Doc> 1.0

Custom

A

Date: Sheet

of

41 10Tuesday, February 24, 2009

5

4

3

2

1

Version Change List ( P. I. R. List )

Page 1/1

Request

Item Issue DescriptionDate

1

D D

2

3

4

5

6

7

8

9

10

11

12

C C

13

14

15

16

17

18

19

20

21

22

19 P19-DDR3_SO-DIMM SLOT 2008/09/22 change SO-DI M M S A 0 t o p ul l high & SA1 to pull downcan't use SO-DIMM 0.2

20 P20-LCD/SATA HDD 2008/09/25 can't read EDID for Panel change JLVDS1 Pin 37 from +LCDVDD TO +3VS 0.2

21 P21-HDMI/Display Port 2008/10/07 Change DP122 to DP122A change R4 4 0 f ro m 4 . 64 K t o 5. 1 1K and R438 from 5.11K to 6.49K 0. 2

28 P28-EC_KB926/BIOS/Reed SW2008/10/20 Compal Change EC_SMB _D A1 an d E C_ SMB_CK1 from +5VALW to +3VALW 0.2

18 P18-1GB/2GB_DDR3_On Board2008/12/04 nVidia On board Ram unstable Add 0.1uF cap betw een Te rm ination Resistor and +0.75VS 0.4

14 P14-MCP79(8/10)_HDA/MISC 2009/02/03 Dell saving power consumption change +3VALW to +3V S o n MEM_SMBCLK & MEM_SMBDATA

24 P24-Mini Card_WLAN/WWAN 2009/02/04 Dell reserve SMBus from MCP79

Owner

nVidia

Compal

Compal

can't select on board SPD data ADD R191,R19 2 , R 1 9 3 T O S EL ECT ON BOARD MEMORY VENDOR12 P12-MCP79(6/10)_PCI/LPC 2008/10/13 Compal 0.2

Solution Description Rev.Page# Titl e

1.0

1.0

B B

23

24

25

26

27

28

29

30

31

32

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/02/19 2009/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

EE PIR-1

LA-4631P

1.0

of

42 42Thursday, F e b r u a ry 19, 2009

1