COMPAL LA-4631P Schematics
A
1 1
B
C
D
E
2 2
Compal Confidential
Schematic Document
MCP79-MX
2009 / 02 / 19
3 3
Rev:1.0
4 4
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2009/02/19 2009/12/31
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
LA-4631P
E
142Thursday, Fe br ua ry 19, 2009
1.0
of
A
B
C
D
E
Compal confidential
Braxton 14"
Project Code : KCM00
File Name : LA-4631P
PCB
1 1
ZZZ1
X76
ZZZ2
Fan Driver
RT9027BPS
Thermal Sensor
EMC1402-1-ACZL-TR
P.4
P.4
Intel Penryn
uFCPGA-478 CPU
H_A#(3..35)
H_D#(0..63)
FSB
667/800/1066MHz 1.05V
P.4,5,6
Memory
14" LED Panel
HD 1366 x 768
HD+ 1600 x 900
2 2
HDMI Conn.
P.21
1:2 Switch
P.20
TI
Display Port
SN75DP122A
P.21
P.21
LVDS
HDMI / TMDS
nVIDIA
MCP79-MX
FCBGA 1437
PCI-E x1
PCIE1 PCIE2
Express Card
( 34mm )
3 3
P.23
RealTek
RTL8111DL
RJ45 Conn.
P.22
P.22
Mini Card-1
WLAN (Half)
P.24
PCIE3PCIE0
JMicron
JMB380
IEEE1394
P.26
B to B
P.29
P.7~16
LPC
Power On/Off CKT.
P.29
DC/DC Int erface CKT.
P.30
4 4
Power Circuit DC/DC
P.32~40
A
RTC CKT.
P.14,15,32,33
Power OK CKT.
Touch Pad Conn
B
P.29
KBC
ENE KB926
P.28
Int.KB
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BIOS(System/EC)
P.29
C
2009/02/19 2009/12/31
Dual Channel
DDR3 800/1066 MHz +1.5V
Channel B
SATA
USB2.0
HDA
P.28
SATA_A0
SATA_A1
B to B
USB2
USB1
B to B
USB0
USB3
USB7
USB6
USB5
USB4
Compal Secret Data
Deciphered Date
Channel A
DDR3 / 1GB on board
( 128Mx8) x8pcs
DDR3-SO-DIMM x1
BANK 0, 1, 2, 3
SATA HDD Conn
USB/E-SATA Conn
On Right Side
USB Conn
On Right Side
USB Conn
On Left Side
Express Card
( 34mm )
Mini Card-1 (WLAN)
( Half )
Mini Card-2 (WWAN)
( Full )
Blue Tooth
Camera
Audio Codec
IDT 92HD83
D
P.17,18
P.19
P.20
P.29
P.29
P.27
P.23
P.24
P.24
P.27
P.27
P.25
Title
Size Document Number Rev
Custom
Date: Sheet
SIM Card
Digital Microphone
Tweeter (0.5W x2)
Speaker (1W x2)
Audio Jack x3
B to B
Compal Electronics, Inc.
Block Diagram
LA-4631P
P.24
P.27
P.25, 29
P.25
P.29
1.0
of
242Thursday, F e b r u a ry 19, 2009
E
A
Voltage Rails
State
S0
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
1 1
O MEANS ON X MEANS OFF
power
plane
+5VS
+3VS
+1.8VS
+B
O
O
O
O
O
X
+5VALW
+3VALW
+1.1VALW
O
O
O
O
X
XX X
+1.5V
O
XX
X
+1.1VS
+VCCP
+1.0VS
+0.75VS
+CPU_CORE
+1.5VS
OO
OO
X
X
Board ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7
SMBUS Control Table
100K +/- 5%Ra
Rb V min
00 V
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
SOURCE
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build
DEBUG@ : means jus t r e s e r v e for debug.
AD_BID
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
INVERTER BATT EEPROM
Vtyp
AD_BID
0.503 V
0.819 V
1.185 V 1.264 V
2.200 V
3.300 V
SERIAL SENSOR
THERMAL
(CPU)
0 V 0 V
SODIMM EXP CARD
V
AD_BID
0.538 V
0.875 V
2.341 V
3.300 V
max
MINI CARD1
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
MINI CARD2
PCB Revision
0.1
0.2
0.3
0.4
0.5
1.0
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
MEM_SMBCLK
MEM_SMBDATA MCP79
MCP_SMB_CLK
MCP_SMB_DATA
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KB926
KB926
X
X
X
MCP79
A
XX
2009/02/19 2009/12/31
Compal Secret Data
X
V
XX
X
X
XX
MINI CARD 1 R E S E R VE D +3VALW TO PULL HIGH
Deciphered Date
XX
V
X
X
V
X
XXX
XX
X
X
X
X
VVV
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
Notes List
LA-4631P
342Thursday, F eb r u ary 19, 2009
1.0
of
5
4
3
2
1
D D
H_A#[3..16]7
H_ADSTB#07
C C
B B
A A
H_REQ#07
H_REQ#17
H_REQ#27
H_REQ#37
H_REQ#47
H_A#[17..35]7
H_ADSTB#17
H_A20M#7
H_FERR#7
H_IGNNE#7
H_STPCLK#7
H_INTR7
H_NMI7
H_SMI#7
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_A20M#
H_FERR#
H_IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
JCPU1A
J4
ADDR GROUP_0
A[3]#
L5
A[4]#
L4
A[5]#
K5
A[6]#
M3
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L2
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
M1
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L1
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
ADDR GROUP_1
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U1
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W2
A[27]#
W5
A[28]#
Y4
A[29]#
U2
A[30]#
V4
A[31]#
W3
A[32]#
AA4
AB2
AA3
V1
A6
A5
C4
D5
C6
B4
A3
M4
N5
T2
V3
B2
D2
D22
D3
F6
THERMAL
A[33]#
A[34]#
A[35]#
ADSTB[1]#
ICH
A20M#
FERR#
THERMTRIP#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RESERVED
TYCO_2-1871873-3_Merom~D
CONN@
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
BR1#
IERR#
INIT#
LOCK#
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
XDP/ITP SIGNALS
PROCHOT#
THERMDA
THERMDC
H CLK
BCLK[0]
BCLK[1]
H_ADS#
H1
H_BNR#
E2
H_BPRI#
G5
H_DEFER#
H5
H_DRDY#
F21
H_DBSY#
E1
H_BR0#
F1
H_BR1#
AA7
H_IERR#
D20
H_INIT#
B3
H_LOCK#
H4
H_RESET#
C1
H_RS#0
F3
H_RS#1
F4
H_RS#2
G3
H_TRDY#
G2
H_HIT#
G6
H_HITM#
E4
XDP_BPM#0
AD4
XDP_BPM#1
AD3
XDP_BPM#2
AD1
XDP_BPM#3
AC4
XDP_BPM#4
AC2
XDP_PREQ#
AC1
XDP_TCK
AC5
XDP_TDI
AA6
TDI
XDP_TDO
AB3
XDP_TMS
AB5
XDP_TRST#
AB6
XDP_DBRESET#
C20
H_PROCHOT#
D21
H_THERMDA_R
A24
H_THERMDC_R
B25
H_THERMTRIP#
C7
CLK_CPU_BCLK
A22
CLK_CPU_BCLK#
A21
H_ADS# 7
H_BNR# 7
H_BPRI# 7
H_DEFER# 7
H_DRDY# 7
H_DBSY# 7
H_BR0# 7
H_BR1# 7
H_INIT# 7
H_LOCK# 7
H_RESET# 7
H_RS#0 7
H_RS#1 7
H_RS#2 7
H_TRDY# 7
H_HIT# 7
H_HITM# 7
T1
T2
T3
T4
T5
T6
T7
H_PROCHOT# 7
R7 100_0402_5%
1 2
R8 100_0402_5%
1 2
H_THERMTRIP# 7
CLK_CPU_BCLK 7
CLK_CPU_BCLK# 7
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
H_THERMDA
H_THERMDC
Fan Control circuit
FAN_SPEED128
0.01U_0402_16V7K
Thermal Sensor
1 2
C2 2200P_0402_50V7K
1 2
+3VS
10K_0402_5%
+3VS
R10
10K_0402_5%
C6
+3VS
1
C1
2
0.1U_0402_16V4Z
H_THERMDA
H_THERMDC
L_THERM#
R9
12
2
1
XDP Reserve
Place close to CPU within 500mil
H_IERR#
H_THERMTRIP#
XDP_PREQ#
XDP_TDI
XDP_TDO
XDP_TMS
H_PROCHOT#
H_BR0#
H_FERR#
H_INTR
H_NMI
H_RESET#
H_BR1#
XDP_TCK
XDP_TRST#
C3
10U_1206_16V4Z~N
1 2
C5
1000P_0402_50V7K~N
EN_DFAN128
U2
1
VDD
2
D+
3
DTHERM#4GND
EMC1402-1-ACZL-TR MSOP 8P
SMBus Address:100_1100
R513 49.9_0402_1%
R514 49.9_0402_1%
R515 49.9_0402_1%
R516 49.9_0402_1%
R517 49.9_0402_1%
R518 49.9_0402_1%
R519 68_0402_5%
R520 62_0402_5%@
1 2
R521 62_0402_5%
1 2
R522 150_0402_1%@
1 2
R523 150_0402_1%@
1 2
R524 200_0402_1%@
1 2
R1275 62_0402_5%
1 2
R525 49.9_0402_1%
R526 649_0402_1%
+5VS
12
EN_DFAN1
40mil
FAN1_POWER
8
SCLK
7
SDATA
6
ALERT#
5
12
12
12
12
12
12
12
12
12
1
2
3
4
1
2
3
4
5
EC_SMB_CK2
EC_SMB_DA2
C4
1 2
10U_1206_16V4Z~N
U3
VEN
GND
VIN
GND
GND
VO
GND
VSET
RT9027BPS SO 8P
JFAN1
1
2
3
GND
GND
MOLEX_53780-0370~D
CONN@
EC_SMB_CK2 28
EC_SMB_DA2 28
+VCCP
8
7
6
5
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/02/19 2009/12/31
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
Penryn(1/3)-A GTL+/ITP-XDP
LA-4631P
1
1.0
of
442Tuesday, Fe b r u a r y 24, 2009
5
4
3
2
1
H_D#[0..15]7
D D
H_DSTBN#07
H_DSTBP#07
H_DINV#07
H_D#[16..31]7
C C
R13 1K_0402_5%@
R14 1K_0402_5%@
C308 0.1U_0402_16V4Z@
H_DSTBN#17
H_DSTBP#17
H_DINV#17
1 2
1 2
1 2
CPU_BSEL07
CPU_BSEL17
CPU_BSEL27
T8
T10
T11
T12
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
V_CPU_GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
JCPU1B
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
D[7]#
K24
D[8]#
G24
D[9]#
J24
D[10]#
J23
D[11]#
H22
D[12]#
F26
D[13]#
K22
D[14]#
H23
D[15]#
J26
DSTBN[0]#
H26
DSTBP[0]#
H25
DINV[0]#
N22
D[16]#
K25
D[17]#
P26
D[18]#
R23
D[19]#
L23
D[20]#
M24
D[21]#
L22
D[22]#
M23
D[23]#
P25
D[24]#
P23
D[25]#
P22
D[26]#
T24
D[27]#
R24
D[28]#
L25
D[29]#
T25
D[30]#
N25
D[31]#
L26
DSTBN[1]#
M26
DSTBP[1]#
N24
DINV[1]#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
C3
TEST7
B22
BSEL[0]
B23
BSEL[1]
C21
BSEL[2]
TYCO_2-1871873-3_Merom~D
CONN@
MISC
DATA GRP 0
DATA GRP 1
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
DATA GRP 2DATA GRP 3
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
COMP0
COMP1
COMP2
COMP3
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#
layout note: Rout H_DPRSTP# from ICH9 to IMVP6 then to GMCH & CPU
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
CPU_BSEL CPU_BSEL2 CPU_BSEL1
B B
166
200
01
0
1
266000
CPU_BSEL0
1
0
H_PWRGOOD
H_CPUSLP#
H_DPRSTP#
H_DPRSTP#
0.01U 16V K X7R 0402
R527 150_0402_1%@
1 2
R528 51_0402_1%@
1 2
R529 220_0402_1%@
1 2
C649
@
H_D#[32..47] 7
H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7
H_D#[48..63] 7
H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7
H_DPRSTP# 7,38
H_DPSLP# 7
H_DPWR# 7
H_PWRGOOD 7
H_CPUSLP# 7
H_PSI# 38
To IMVP
R15
12
54.9_0402_1%
R16
12
27.4_0402_1%
R17
12
54.9_0402_1%
R18
12
27.4_0402_1%
49.9 25.5 29.9 25.5
Resistor placed within
+VCCP
1
2
0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4
+CPU_CORE +CPU_CORE
47A
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AC10
AB10
AB12
AB14
AB15
AB17
AB18
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA9
AB9
JCPU1C
VCC[001]
VCC[068]
VCC[002]
VCC[069]
VCC[003]
VCC[070]
VCC[004]
VCC[071]
VCC[005]
VCC[072]
VCC[006]
VCC[073]
VCC[007]
VCC[074]
VCC[008]
VCC[075]
VCC[009]
VCC[076]
VCC[010]
VCC[077]
VCC[011]
VCC[078]
VCC[012]
VCC[079]
VCC[013]
VCC[080]
VCC[014]
VCC[081]
VCC[015]
VCC[082]
VCC[016]
VCC[083]
VCC[017]
VCC[084]
VCC[018]
VCC[085]
VCC[019]
VCC[086]
VCC[020]
VCC[087]
VCC[021]
VCC[088]
VCC[022]
VCC[089]
VCC[023]
VCC[090]
VCC[024]
VCC[091]
VCC[025]
VCC[092]
VCC[026]
VCC[093]
VCC[027]
VCC[094]
VCC[028]
VCC[095]
VCC[029]
VCC[096]
VCC[030]
VCC[097]
VCC[031]
VCC[098]
VCC[032]
VCC[099]
VCC[033]
VCC[100]
VCC[034]
VCC[035]
VCCP[01]
VCC[036]
VCCP[02]
VCC[037]
VCCP[03]
VCC[038]
VCCP[04]
VCC[039]
VCCP[05]
VCC[040]
VCCP[06]
VCC[041]
VCCP[07]
VCC[042]
VCCP[08]
VCC[043]
VCCP[09]
VCC[044]
VCCP[10]
VCC[045]
VCCP[11]
VCC[046]
VCCP[12]
VCC[047]
VCCP[13]
VCC[048]
VCCP[14]
VCC[049]
VCCP[15]
VCC[050]
VCCP[16]
VCC[052]
VCCA[01]
VCC[053]
VCCA[02]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
TYCO_2-1871873-3_Merom~D
CONN@
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
For 8 layer condition
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
+1.5VS_VCCA
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
VCCSENSE
AF7
VSSSENSE
AE7
.
4.5A
10mil
CPU_VID0 38
CPU_VID1 38
CPU_VID2 38
CPU_VID3 38
CPU_VID4 38
CPU_VID5 38
CPU_VID6 38
VCCSENSE 38
VSSSENSE 38
Layout Note:
Route VCCSENSE and VSSSENSE traces at
27.4 Ohms with 50 mil spacing.
+VCCP
1
+
C7
330U 2.5V Y D2 LESR15M CX H1.9
2
1
1
C8
C9
2
2
10U_0805_6.3V6M
0.01U_0402_16V7K
Near pin B26
0_0805_5%
1 2
Length match within 25 mils.
The trace width/space/other is
20/7/25.
R1283
+1.5VS
+VCCP
12
R19
1K_0402_1%
V_CPU_GTLREF
A A
Dual Core CPU
12
R20
2K_0402_1%
For 6 layer
Z=27.4 ohm
VCCSENSE, VSSSENSE/ 14mils (MS),
16mils (SL) width, 7mils space, 25mils
space to other signals Mismatch =25mils.
+CPU_CORE
R21 100_0402_1%
1 2
R23 100_0402_1%
1 2
Close to CPU pin
within 500mils.
VCCSENSE
VSSSENSE
Close to CPU pin AD26
within 500mils.
5
4
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/02/19 2009/12/31
Compal Secret Data
Deciphered Date
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
Penryn(2/3)-AGTL+/ITP-XDP
LA-4631P
1
of
542Tuesday, Fe b r u a r y 24, 2009
1.0
5
Near CPU CORE regulator
D D
C C
B B
JCPU1D
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
VSS[082]
VSS[001]
VSS[002]
VSS[083]
VSS[003]
VSS[084]
VSS[004]
VSS[085]
VSS[005]
VSS[086]
VSS[006]
VSS[087]
VSS[007]
VSS[088]
VSS[008]
VSS[089]
VSS[009]
VSS[090]
VSS[010]
VSS[091]
VSS[011]
VSS[092]
VSS[012]
VSS[093]
VSS[013]
VSS[094]
VSS[014]
VSS[095]
VSS[015]
VSS[096]
VSS[016]
VSS[097]
VSS[017]
VSS[098]
VSS[018]
VSS[099]
VSS[019]
VSS[100]
VSS[020]
VSS[101]
VSS[021]
VSS[102]
VSS[022]
VSS[103]
VSS[023]
VSS[104]
VSS[024]
VSS[105]
VSS[025]
VSS[106]
VSS[026]
VSS[107]
VSS[027]
VSS[108]
VSS[028]
VSS[109]
VSS[029]
VSS[110]
VSS[030]
VSS[111]
VSS[031]
VSS[112]
VSS[032]
VSS[113]
VSS[033]
VSS[114]
VSS[034]
VSS[115]
VSS[035]
VSS[116]
VSS[036]
VSS[117]
VSS[037]
VSS[118]
VSS[038]
VSS[119]
VSS[039]
VSS[120]
VSS[040]
VSS[121]
VSS[041]
VSS[122]
VSS[042]
VSS[123]
VSS[043]
VSS[124]
VSS[044]
VSS[125]
VSS[045]
VSS[126]
VSS[046]
VSS[127]
VSS[047]
VSS[128]
VSS[048]
VSS[129]
VSS[049]
VSS[130]
VSS[050]
VSS[131]
VSS[051]
VSS[132]
VSS[052]
VSS[133]
VSS[053]
VSS[134]
VSS[054]
VSS[135]
VSS[055]
VSS[136]
VSS[056]
VSS[137]
VSS[057]
VSS[138]
VSS[058]
VSS[139]
VSS[059]
VSS[140]
VSS[060]
VSS[141]
VSS[061]
VSS[142]
VSS[062]
VSS[143]
VSS[063]
VSS[144]
VSS[064]
VSS[145]
VSS[065]
VSS[146]
VSS[066]
VSS[147]
VSS[148]
VSS[067]
VSS[068]
VSS[149]
VSS[069]
VSS[150]
VSS[070]
VSS[151]
VSS[071]
VSS[152]
VSS[072]
VSS[153]
VSS[073]
VSS[154]
VSS[074]
VSS[155]
VSS[075]
VSS[156]
VSS[076]
VSS[157]
VSS[077]
VSS[158]
VSS[078]
VSS[159]
VSS[079]
VSS[160]
VSS[080]
VSS[161]
VSS[081]P3VSS[162]
VSS[163]
TYCO_2-1871873-3_Merom~D
CONN@
ESR <= 1.5m ohm
Capacitor > 1980uF
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
.
4
+CPU_CORE
12
C11
10U_0805_4V
+CPU_CORE
12
C492
10U_0805_4V
+CPU_CORE
12
C27
10U_0805_4V
+CPU_CORE
12
C581
10U_0805_4V
+VCCP
1
C15
0.1U_0402_10V6K
2
+CPU_CORE +CPU_CORE +CPU_CORE+CPU_CORE
1
+
C456
330U_D2E_2.5VM_R9
2
12
C22
10U_0805_4V
12
C582
10U_0805_4V
1
C16
0.1U_0402_10V6K
2
1
+
C458
330U_D2E_2.5VM_R9
2
12
C12
10U_0805_4V
12
C493
10U_0805_4V
12
C26
10U_0805_4V
12
C584
10U_0805_4V
1
C17
0.1U_0402_10V6K
2
1
+
2
12
C13
10U_0805_4V
12
C577
10U_0805_4V
12
C28
10U_0805_4V
12
C583
10U_0805_4V
1
2
C576
330U_D2E_2.5VM_R9
3
C18
0.1U_0402_10V6K
1
+
C522
330U_D2E_2.5VM_R9
2
12
C14
10U_0805_4V
12
C578
10U_0805_4V
12
C591
10U_0805_4V
12
C586
10U_0805_4V
1
C19
0.1U_0402_10V6K
2
12
C457
10U_0805_4V
12
C579
10U_0805_4V
12
C587
10U_0805_4V
12
C585
10U_0805_4V
12
12
12
C588
10U_0805_4V
1
C20
0.1U_0402_10V6K
2
C484
10U_0805_4V
C580
10U_0805_4V
2
12
C485
10U_0805_4V
12
C589
10U_0805_4V
12
C488
10U_0805_4V
12
C590
10U_0805_4V
12
C489
10U_0805_4V
12
C592
10U_0805_4V
Place these caps inside the
socket cavity on Bottom side.
(North side Secondary)
12
C490
10U_0805_4V
16pcs on TOP side
16pcs on bottom side
1
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/02/19 2009/12/31
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
Penryn(3/3)-AGTL+/ITP-XDP
LA-4631P
1
1.0
of
642Thursday, F e b r u a ry 19, 2009
5
4
3
2
1
D D
C C
CPU_BSEL2
CPU_BSEL25
CPU_BSEL15
CPU_BSEL05
R560
@
12
1K_0402_5%
+VCCP
R24
@
12
1K_0402_5%
12
R26
R25
@
@
1K_0402_5%
12
1K_0402_5%
H_DSTBP#05
H_DSTBN#05
H_DINV#05
H_DSTBP#15
H_DSTBN#15
H_DINV#15
H_DSTBP#25
H_DSTBN#25
H_DINV#25
H_DSTBP#35
H_DSTBN#35
H_DINV#35
H_A#[3..35]4
H_ADSTB#04
H_ADSTB#14
H_REQ#[0..4]4
MRB(REV.E) 1.1VS
+VCCP
B B
A A
12
2.2U_0402_6.3VM
L1
MBK1608221YZF 0603
+V_PLL_CPU
C23
C24
4.7U_0603_6.3V6K
+VCCP
2
C277
1
2
1
2.2U_0402_6.3VM
H_ADS#4
H_BNR#4
H_BR0#4
H_BR1#4
H_DBSY#4
H_DRDY#4
H_HIT#4
H_HITM#4
H_LOCK#4
H_TRDY#4
H_PROCHOT#4
H_THERMTRIP#4
H_FERR#4
H_RS#04
H_RS#14
H_RS#24
20 mA
+V_PLL_CPU
+1.05VS_PLL
1.1VS
R29 49.9_0402_1%
R30 49.9_0402_1%
R31 49.9_0402_1%
R32 49.9_0402_1%
1 2
1 2
12
12
H_PROCHOT#
H_THERMTRIP#
BCLK_VML_COMP_VCC
BCLK_VML_COMP_GND
H_DSTBP#0
H_DSTBN#0
H_DINV#0
H_DSTBP#1
H_DSTBN#1
H_DINV#1
H_DSTBP#2
H_DSTBN#2
H_DINV#2
H_DSTBP#3
H_DSTBN#3
H_DINV#3
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#0
H_ADSTB#1
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADS#
H_BNR#
H_BR0#
H_BR1#
H_DBSY#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
T13
R1281 0_0402_5%
1 2
R1280 0_0402_5%
1 2
H_FERR#
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
H_RS#0
H_RS#1
H_RS#2
29 mA
CPU_COMP_VCC
CPU_COMP_GND
PAD
Close to AM39 Ball
5
4
U4A
T40
CPU_DSTBP0#
U40
CPU_DSTBN0#
V41
CPU_DBI0#
W39
CPU_DSTBP1#
W37
CPU_DSTBN1#
V35
CPU_DBI1#
N37
CPU_DSTBP2#
L36
CPU_DSTBN2#
N35
CPU_DBI2#
M39
CPU_DSTBP3#
M41
CPU_DSTBN3#
J41
CPU_DBI3#
AC34
CPU_A3#
AE38
CPU_A4#
AE34
CPU_A5#
AC37
CPU_A6#
AE37
CPU_A7#
AE35
CPU_A8#
AB35
CPU_A9#
AF35
CPU_A10#
AG35
CPU_A11#
AG39
CPU_A12#
AE33
CPU_A13#
AG37
CPU_A14#
AG38
CPU_A15#
AG34
CPU_A16#
AN38
CPU_A17#
AL39
CPU_A18#
AG33
CPU_A19#
AL33
CPU_A20#
AJ33
CPU_A21#
AN36
CPU_A22#
AJ35
CPU_A23#
AJ37
CPU_A24#
AJ36
CPU_A25#
AJ38
CPU_A26#
AL37
CPU_A27#
AL34
CPU_A28#
AN37
CPU_A29#
AJ34
CPU_A30#
AL38
CPU_A31#
AL35
CPU_A32#
AN34
CPU_A33#
AR39
CPU_A34#
AN35
CPU_A35#
AE36
CPU_ADSTB0#
AK35
CPU_ADSTB1#
AC38
CPU_REQ0#
AA33
CPU_REQ1#
AC39
CPU_REQ2#
AC33
CPU_REQ3#
AC35
CPU_REQ4#
AD42
CPU_ADS#
AD43
CPU_BNR#
AE40
CPU_BR0#
AL32
CPU_BR1#
AD39
CPU_DBSY#
AD41
CPU_DRDY#
AB42
CPU_HIT#
AD40
CPU_HITM#
AC43
CPU_LOCK#
AE41
CPU_TRDY#
E41
CPU_PECI
AJ41
CPU_PROCHOT#
AG43
CPU_THERMTRIP#
AH40
CPU_FERR#
F42
CPU_BSEL2
D42
CPU_BSEL1
F41
CPU_BSEL0
AC41
CPU_RS0#
AB41
CPU_RS1#
AC42
CPU_RS2#
AH28
+V_PLL_CPU
U28
+V_PLL_DP
AM39
BCLK_VML_COMP_VDD
AM40
BCLK_VML_COMP_GND
AM43
CPU_COMP_VCC
AM42
CPU_COMP_GND
MCP79MX-B2 PBGA 1437P
FSB
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#
CPU_BPRI#
CPU_DEFER#
BCLK_OUT_CPU_P
BCLK_OUT_CPU_N
BCLK_OUT_ITP_P
BCLK_OUT_ITP_N
BCLK_OUT_NB_P
BCLK_OUT_NB_N
BCLK_IN_N
BCLK_IN_P
CPU_A20M#
CPU_IGNNE#
CPU_INIT#
CPU_INTR
CPU_NMI
CPU_SMI#
CPU_PWRGD
CPU_RESET#
CPU_SLP#
CPU_DPSLP#
CPU_DPWR#
CPU_STPCLK#
CPU_DPRSTP#
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
H_D#1
W42
H_D#2
Y40
H_D#3
W41
H_D#4
Y39
H_D#5
V42
H_D#6
Y41
H_D#7
Y42
H_D#8
P42
H_D#9
U41
H_D#10
R42
H_D#11
T39
H_D#12
T42
H_D#13
T41
H_D#14
R41
H_D#15
T43
H_D#16
W35
H_D#17
AA37
H_D#18
W33
H_D#19
W34
H_D#20
AA36
H_D#21
AA34
H_D#22
AA38
H_D#23
AA35
H_D#24
U38
H_D#25
U36
H_D#26
U35
H_D#27
U33
H_D#28
U34
H_D#29
W38
H_D#30
R33
H_D#31
U37
H_D#32
N34
H_D#33
N33
H_D#34
R34
H_D#35
R35
H_D#36
P35
H_D#37
R39
H_D#38
R37
H_D#39
R38
H_D#40
L37
H_D#41
L39
H_D#42
L38
H_D#43
N36
H_D#44
N38
H_D#45
J39
H_D#46
J38
H_D#47
J37
H_D#48
L42
H_D#49
M42
H_D#50
P41
H_D#51
N41
H_D#52
N40
H_D#53
M40
H_D#54
H40
H_D#55
K42
H_D#56
H41
H_D#57
L41
H_D#58
H43
H_D#59
H42
H_D#60
K41
H_D#61
J40
H_D#62
H39
H_D#63
M43
H_BPRI#
AA41
H_DEFER#
AA40
G42
G41
AL43
AL42
BCLK_FEEDBACK_P
AL41
BCLK_FEEDBACK_N
AK42
AK41
AJ40
H_A20M#
AF41
H_IGNNE#
AH39
H_INIT#
AH42
H_INTR
AF42
H_NMI
AG41
H_SMI#
AH41
H_PWRGOOD
AH43
H_RESET#
H38
H_CPUSLP#
AM33
H_DPSLP#
AN33
H_DPWR#
AM32
H_STPCLK#
AG42
H_DPRSTP#
AN32
2009/02/19 2009/12/31
H_D#0
Y43
H_D#[0..63]
H_BPRI# 4
H_DEFER# 4
T21
PAD
T24
PAD
H_A20M# 4
H_IGNNE# 4
H_INIT# 4
H_INTR 4
H_NMI 4
H_SMI# 4
H_PWRGOOD 5
H_RESET# 4
H_CPUSLP# 5
H_DPSLP# 5
H_DPWR# 5
H_STPCLK# 4
H_DPRSTP# 5,38
Compal Secret Data
Deciphered Date
To +CPU_CORE
H_D#[0..63] 5
2
@
@
1
C21
15P_0402_50V8J
2
1
C25
15P_0402_50V8J
2
CLK_CPU_BCLK
CLK_CPU_BCLK#
Title
Size Document Number Rev
Date: Sheet
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
Compal Electronics, Inc.
MCP79(1/10)-FRONT SIDE BUS
LA-4631P
1
of
742Tuesday, Fe b r u a r y 24, 2009
1.0
5
4
3
2
1
DDR_A_DQS#[0..7]
D D
DDR_A_D[0..63]17,18
C C
B B
DDR_A_DM[0..7]17,18
DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0
DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0 DDR_B_DM0
U4B
AL8
MDQ0_63
AL9
MDQ0_62
AP9
MDQ0_61
AN9
MDQ0_60
AL6
MDQ0_59
AL7
MDQ0_58
AN6
MDQ0_57
AN7
MDQ0_56
AR6
MDQ0_55
AR7
MDQ0_54
AV6
MDQ0_53
AW5
MDQ0_52
AN10
MDQ0_51
AR5
MDQ0_50
AU6
MDQ0_49
AV5
MDQ0_48
AU7
MDQ0_47
AU8
MDQ0_46
AW9
MDQ0_45
AP11
MDQ0_44
AW6
MDQ0_43
AY5
MDQ0_42
AU9
MDQ0_41
AV9
MDQ0_40
AU11
MDQ0_39
AV11
MDQ0_38
AV13
MDQ0_37
AW13
MDQ0_36
AR11
MDQ0_35
AT11
MDQ0_34
AR14
MDQ0_33
AU13
MDQ0_32
AR26
MDQ0_31
AU25
MDQ0_30
AT27
MDQ0_29
AU27
MDQ0_28
AP25
MDQ0_27
AR25
MDQ0_26
AP27
MDQ0_25
AR27
MDQ0_24
AP29
MDQ0_23
AR29
MDQ0_22
AP31
MDQ0_21
AR31
MDQ0_20
AV27
MDQ0_19
AN29
MDQ0_18
AV29
MDQ0_17
AN31
MDQ0_16
AU31
MDQ0_15
AR33
MDQ0_14
AV37
MDQ0_13
AW37
MDQ0_12
AT31
MDQ0_11
AV31
MDQ0_10
AT37
MDQ0_9
AU37
MDQ0_8
AW39
MDQ0_7
AV39
MDQ0_6
AR37
MDQ0_5
AR38
MDQ0_4
AV38
MDQ0_3
AW38
MDQ0_2
AR35
MDQ0_1
AP35
MDQ0_0
AN5
MDQM0_7
AU5
MDQM0_6
AR10
MDQM0_5
AN13
MDQM0_4
AN27
MDQM0_3
AW29
MDQM0_2
AV35
MDQM0_1
AR34
MDQM0_0
MCP79MX-B2 PBGA 1437P
MEMORY
PARTITION 0
MEMORY CONTROL 0A
MDQS0_7_P
MDQS0_7_N
MDQS0_6_P
MDQS0_6_N
MDQS0_5_P
MDQS0_5_N
MDQS0_4_P
MDQS0_4_N
MDQS0_3_P
MDQS0_3_N
MDQS0_2_P
MDQS0_2_N
MDQS0_1_P
MDQS0_1_N
MDQS0_0_P
MDQS0_0_N
MRAS0#
MCAS0#
MWE0#
MBA0_2
MBA0_1
MBA0_0
MA0_14
MA0_13
MA0_12
MA0_11
MA0_10
MA0_9
MA0_8
MA0_7
MA0_6
MA0_5
MA0_4
MA0_3
MA0_2
MA0_1
MA0_0
MCLK0A_2_P
MCLK0A_2_N
MCLK0A_1_P
MCLK0A_1_N
MCLK0A_0_P
MCLK0A_0_N
MCS0A_1#
MCS0A_0#
MODT0A_1
MODT0A_0
MCKE0A_1
MCKE0A_0
DDR_A_DQS[0..7]
AL10
AL11
AR8
AR9
AW7
AW8
AP13
AR13
AV25
AW25
AU30
AU29
AT35
AU35
AU39
AT39
AV17
AP17
AR17
AP23
AP19
AW17
AR23
AU15
AN23
AW21
AN19
AV21
AR22
AU21
AP21
AR21
AN21
AV19
AU19
AT19
AR19
AW33
AV33
M_CLK_DDR1
BA24
M_CLK_DDR#1
AY24
M_CLK_DDR0
BB20
M_CLK_DDR#0
BC20
DDR_CS1_DIMMA#
AT15
DDR_CS0_DIMMA#
AR18
M_ODT1
AP15
M_ODT0
AV15
DDR_CKE1_DIMMA
AU23
DDR_CKE0_DIMMA
AT23
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_A_BS2
DDR_A_BS1
DDR_A_BS0
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0
DDR_A_DQS#[0..7] 17,18
DDR_A_DQS[0..7] 17,18
12
R40
75_0402_1%
DDR_A_RAS# 17,18
DDR_A_CAS# 17,18
DDR_A_WE# 17,18
DDR_A_BS[0..2] 17,18
DDR_A_MA[0..14] 17,18
T30
T31
M_CLK_DDR0 17,18
M_CLK_DDR#0 17,18
T34
DDR_CS0_DIMMA# 17,18
T35
M_ODT0 17,18
T36
DDR_CKE0_DIMMA 17,18
U4C
DDR_B_D[0..63]19
DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_DM[0..7]19
DDR_B_D0
DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
AT4
MDQ1_63
AT3
MDQ1_62
AV2
MDQ1_61
AV3
MDQ1_60
AR4
MDQ1_59
AR3
MDQ1_58
AU2
MDQ1_57
AU3
MDQ1_56
AY4
MDQ1_55
AY3
MDQ1_54
BB3
MDQ1_53
BC3
MDQ1_52
AW4
MDQ1_51
AW3
MDQ1_50
BA3
MDQ1_49
BB2
MDQ1_48
BB5
MDQ1_47
BA5
MDQ1_46
BA8
MDQ1_45
BC8
MDQ1_44
BB4
MDQ1_43
BC4
MDQ1_42
BA7
MDQ1_41
AY8
MDQ1_40
BA9
MDQ1_39
BB10
MDQ1_38
BB12
MDQ1_37
AW12
MDQ1_36
BB8
MDQ1_35
BB9
MDQ1_34
AY12
MDQ1_33
BA12
MDQ1_32
BC32
MDQ1_31
AW32
MDQ1_30
BA35
MDQ1_29
AY36
MDQ1_28
BA32
MDQ1_27
BB32
MDQ1_26
BA34
MDQ1_25
AY35
MDQ1_24
BC36
MDQ1_23
AW36
MDQ1_22
BA39
MDQ1_21
AY40
MDQ1_20
BA36
MDQ1_19
BB36
MDQ1_18
BA38
MDQ1_17
AY39
MDQ1_16
BB40
MDQ1_15
AW40
MDQ1_14
AV42
MDQ1_13
AV41
MDQ1_12
BA40
MDQ1_11
BC40
MDQ1_10
AW42
MDQ1_9
AW41
MDQ1_8
AT40
MDQ1_7
AT41
MDQ1_6
AP41
MDQ1_5
AN40
MDQ1_4
AU40
MDQ1_3
AU41
MDQ1_2
AR41
MDQ1_1
AP42
MDQ1_0
AT5
MDQM1_7
BA2
MDQM1_6
AY7
MDQM1_5
BA11
MDQM1_4
BB34
MDQM1_3
BB38
MDQM1_2
AY43
MDQM1_1
AR42
MDQM1_0
MCP79MX-B2 PBGA 1437P
MEMORY
PARTITION 1
MEMORY CONTROL 1A
MDQS1_7_P
MDQS1_7_N
MDQS1_6_P
MDQS1_6_N
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P
MDQS1_3_N
MDQS1_2_P
MDQS1_2_N
MDQS1_1_P
MDQS1_1_N
MDQS1_0_P
MDQS1_0_N
MRAS1#
MCAS1#
MWE1#
MBA1_2
MBA1_1
MBA1_0
MA1_14
MA1_13
MA1_12
MA1_11
MA1_10
MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0
MCLK1A_2_P
MCLK1A_2_N
MCLK1A_1_P
MCLK1A_1_N
MCLK1A_0_P
MCLK1A_0_N
MCS1A_1#
MCS1A_0#
MODT1A_1
MODT1A_0
MCKE1A_1
MCKE1A_0
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
AT2
AT1
AY2
AY1
BB6
BA6
BA10
AY11
BB33
BA33
BB37
BA37
BA43
AY42
AT42
AT43
AW16
BA15
BA16
BB29
BB18
BB17
BA29
BA14
AW28
BC28
BA17
BB28
AY28
BA28
AY27
BA27
BA26
BB26
BA25
BB25
BA18
BA42
BB42
BB22
BA22
BA19
AY19
BB14
BB16
BB13
AY15
AY31
BB30
DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
DDR_B_BS2
DDR_B_BS1
DDR_B_BS0
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
M_CLK_DDR2
M_CLK_DDR#2
DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
M_ODT3_DIMMB
M_ODT2_DIMMB
DDR_CKE3_DIMMB
DDR_CKE2_DIMMB
DDR_B_DQS#[0..7] 19
DDR_B_DQS[0..7] 19
DDR_B_RAS# 19
DDR_B_CAS# 19
DDR_B_WE# 19
DDR_B_BS[0..2] 19
DDR_B_MA[0..14] 19
M_CLK_DDR3 19
M_CLK_DDR#3 19
M_CLK_DDR2 19
M_CLK_DDR#2 19
DDR_CS3_DIMMB# 19
DDR_CS2_DIMMB# 19
M_ODT3_DIMMB 19
M_ODT2_DIMMB 19
DDR_CKE3_DIMMB 19
DDR_CKE2_DIMMB 19
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/02/19 2009/12/31
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
MCP79(2/10)-MEM PARTS 0 & 1
LA-4631P
1
of
842Tuesday, Fe b r u a r y 24, 2009
1.0
5
4
3
2
1
D D
2
1
8mil
MEM_COMP_VDD
MEM_COMP_GND
8mil
C C
+1.5V
B B
R34 40.2_0402_1%
12
R33 40.2_0402_1%
1 2
C348
2.2U_0402_6.3VM
U4D
AU33
MCLK0B_2_P
AU34
MCLK0B_2_N
BB24
MCLK0B_1_P
BC24
MCLK0B_1_N
BA21
MCLK0B_0_P
BB21
MCLK0B_0_N
AU17
MCS0B_0#
AR15
MCS0B_1#
AN17
MODT0B_0
AN15
MODT0B_1
AV23
MCKE0B_0
AN25
MCKE0B_1
AN41
MEM_COMP_VDD
AM41
MEM_COMP_GND
AA22
GND1
AP12
GND2
G30
GND3
P10
GND4
T10
GND5
T6
GND6
V10
GND7
V34
GND8
W5
GND9
AA39
GND10
AB22
GND11
AB7
GND12
AD22
GND13
AE20
GND14
AF24
GND15
AG24
GND16
AH35
GND17
AK7
GND18
AM28
GND19
AT25
GND20
AP30
GND21
AR36
GND22
AU10
GND23
F28
GND24
BC21
GND25
AY9
GND26
BC9
GND27
D34
GND28
F24
GND29
G32
GND30
H31
GND31
K7
GND32
M38
GND33
M5
GND34
M6
GND35
M7
GND36
M9
GND37
N39
GND38
N8
GND39
P33
GND40
P34
GND41
P37
GND42
P4
GND43
P40
GND44
P7
GND45
R36
GND46
R40
GND47
R43
GND48
R5
GND49
T18
GND50
T20
GND51
AK11
GND52
T24
GND53
T26
GND54
MCP79MX-B2 PBGA 1437P
MEMORY CONTROL 1B
MEMORY CONTROL 0B
+V_DLL_DLCELL_AVDD
MCLK1B_2_P
MCLK1B_2_N
MCLK1B_1_P
MCLK1B_1_N
MCLK1B_0_P
MCLK1B_0_N
MCS1B_0#
MCS1B_1#
MODT1B_0
MODT1B_1
MCKE1B_0
MCKE1B_1
+V_PLL_MCLK
+V_PLL_FSB
MRESET0#
+VDD_MEM1
+VDD_MEM2
+VDD_MEM3
+VDD_MEM4
+VDD_MEM5
+VDD_MEM6
+VDD_MEM7
+VDD_MEM8
+VDD_MEM9
+VDD_MEM10
+VDD_MEM11
+VDD_MEM12
+VDD_MEM13
+VDD_MEM14
+VDD_MEM15
+VDD_MEM16
+VDD_MEM17
+VDD_MEM18
+VDD_MEM19
+VDD_MEM20
+VDD_MEM21
+VDD_MEM22
+VDD_MEM23
+VDD_MEM24
+VDD_MEM25
+VDD_MEM26
+VDD_MEM27
+VDD_MEM28
+VDD_MEM29
+VDD_MEM30
+VDD_MEM31
+VDD_MEM32
+VDD_MEM33
+VDD_MEM34
+VDD_MEM35
+VDD_MEM36
+VDD_MEM37
+VDD_MEM38
+VDD_MEM39
+VDD_MEM40
+VDD_MEM41
+VDD_MEM42
+VDD_MEM43
+VDD_MEM44
+VDD_MEM45
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
BA41
BB41
AY23
BA23
BA20
AY20
BC16
BA13
AY16
BC13
BA30
BA31
AH27
AG27
AG28
AY32
AM17
AM19
AM21
AM23
AM25
AM27
AM29
AN16
BC29
AN20
AN24
AT17
AP16
AN22
AP20
AP24
AV16
AR16
AR20
AR24
AW15
AP22
AP18
AU16
AN18
AU24
AT21
AY29
AV24
AU20
AU22
AW27
BC17
AV20
AY17
AY18
AM15
AU18
AY25
AY26
AW19
AW24
BC25
AL30
AM31
T33
T34
T35
T37
T38
T7
T9
U18
U20
U22
+1.5V
R537
1 2
0_0402_5%
+1.5V
C29
+1.5V
197 mA
4.77 A
1
2
10U_0805_10V4Z
2
C35
1
1.05V
This voltage powers the PLLs of DDR2 interfaces.
+V_PLL_CPU
DDR_RST#MRESET0#
C30
4.7U_0603_6.3V6K
2
C36
1
0.1U_0402_16V7K
0.1U_0402_16V7K
C31
4.7U_0603_6.3V6K
2
C37
1
0.1U_0402_16V7K
DDR_RST# 17,18,19
2
2
C33
C32
1
1
0.1U_0402_16V7K
2
2
C38
C39
1
1
0.1U_0402_16V7K
2
C34
1
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2
2
C40
1
0.1U_0402_16V7K
0.1U_0402_16V7K
C349
C41
1
1
0.1U_0402_16V7K
0.1U_0402_16V7K
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/02/19 2009/12/31
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
MCP79(3/10)-MEM CNTL 0B&1B
LA-4631P
1
942Tuesday, Fe b r u a r y 24, 2009
1.0
of
5
D D
C C
Express Card
LAN
WLAN
EXP_CLKREQ#23
PEB_PRSNT#23
LAN_CLKREQ#22
WLAN_CLKREQ#24
IEEE1394
Express Card
LAN
WLAN
B B
IEEE1394
+VCCP
1.1VS
+VCCP
1.1VS
PCIE_WAKE#22,23,24,28
PCIE_RX0_P23
PCIE_RX0_N23
PCIE_RX1_P22
PCIE_RX1_N22
PCIE_RX2_P24
PCIE_RX2_N24
PCIE_RX3_P26
PCIE_RX3_N26
R52 0_0402_5%
1 2
2
C54
2.2U_0402_6.3VM
1
430 mA
2
2
C55
C56
0.1U_0402_16V7K
0.1U_0402_16V7K
1
1
2.2U
L3 10NH_LQG15HS10NJ02D_5%_0402~D
1 2
C66
1
2
EXP_CLKREQ#
PEB_PRSNT#
PEC_PRSNT#
WLAN_CLKREQ#
PED_PRSNT#
PEE_PRSNT#
PCIE_WAKE#
PCIE_RX0_P
PCIE_RX0_N
PCIE_RX1_P
PCIE_RX1_N
PCIE_RX2_P
PCIE_RX2_N
PCIE_RX3_P
PCIE_RX3_N
+DVDD_PEX
1
C57
1U_0402_6.3V4Z
2
+V_PLL_PEX
C67
2
2.2U_0402_6.3VM
1
4
U4E
F7
PE0_RX0_P
E7
PE0_RX0_N
D7
PE0_RX1_P
C7
PE0_RX1_N
E6
PE0_RX2_P
F6
PE0_RX2_N
E5
PE0_RX3_P
F5
PE0_RX3_N
E4
PE0_RX4_P
E3
PE0_RX4_N
C3
PE0_RX5_P
D3
PE0_RX5_N
G5
PE0_RX6_P
H5
PE0_RX6_N
J7
PE0_RX7_P
J6
PE0_RX7_N
J5
PE0_RX8_P
J4
PE0_RX8_N
L11
PE0_RX9_P
L10
PE0_RX9_N
L9
PE0_RX10_P
L8
PE0_RX10_N
L7
PE0_RX11_P
L6
PE0_RX11_N
N11
PE0_RX12_P
N10
PE0_RX12_N
N9
PE0_RX13_P
P9
PE0_RX13_N
N7
PE0_RX14_P
N6
PE0_RX14_N
N5
PE0_RX15_P
N4
PE0_RX15_N
C9
PE0_PRSNT_16#
D5
PEB_CLKREQ/GPIO_49#
D9
PEB_PRSNT#
E8
PEC_CLKREQ/GPIO_50#
C10
PEC_PRSNT#
M15
PED_CLKREQ/GPIO_51#
B10
PED_PRSNT#
L16
PEE_CLKREQ/GPIO_16#
L18
PEE_PRSNT/GPIO_46#
M16
PEF_CLKREQ/GPIO_17#
M18
PEF_PRSNT/GPIO_47#
M17
PEG_CLKREQ/GPIO_18#
M19
PEG_PRSNT/GPIO_48#
F17
PE_WAKE#
K9
PE1_RX0_P
J9
PE1_RX0_N
H9
PE1_RX1_P
G9
PE1_RX1_N
F9
PE1_RX2_P
E9
PE1_RX2_N
H7
PE1_RX3_P
G7
PE1_RX3_N
T17
+DVDD0_PEX1
W19
+DVDD0_PEX2
U17
+DVDD0_PEX3
V19
C58
1U_0402_6.3V4Z
161 mA
PE_COMP
12
R53
2.37K_0402_1%
@
+DVDD0_PEX4
W16
+DVDD0_PEX5
W17
+DVDD0_PEX6
W18
+DVDD0_PEX7
U16
+DVDD0_PEX8
T19
+DVDD1_PEX1
U19
+DVDD1_PEX2
T16
+V_PLL_PEX
A11
PEX_CLK_COMP
MCP79MX-B2 PBGA 1437P
PCIE
3
PE0_TX0_P
PE0_TX0_N
PE0_TX1_P
PE0_TX1_N
PE0_TX2_P
PE0_TX2_N
PE0_TX3_P
PE0_TX3_N
PE0_TX4_P
PE0_TX4_N
PE0_TX5_P
PE0_TX5_N
PE0_TX6_P
PE0_TX6_N
PE0_TX7_P
PE0_TX7_N
PE0_TX8_P
PE0_TX8_N
PE0_TX9_P
PE0_TX9_N
PE0_TX10_P
PE0_TX10_N
PE0_TX11_P
PE0_TX11_N
PE0_TX12_P
PE0_TX12_N
PE0_TX13_P
PE0_TX13_N
PE0_TX14_P
PE0_TX14_N
PE0_TX15_P
PE0_TX15_N
PE0_REFCLK_P
PE0_REFCLK_N
PE1_REFCLK_P
PE1_REFCLK_N
PE2_REFCLK_P
PE2_REFCLK_N
PE3_REFCLK_P
PE3_REFCLK_N
PE4_REFCLK_P
PE4_REFCLK_N
PE5_REFCLK_P
PE5_REFCLK_N
PE6_REFCLK_P
PE6_REFCLK_N
PEX_RST0#
PE1_TX0_P
PE1_TX0_N
PE1_TX1_P
PE1_TX1_N
PE1_TX2_P
PE1_TX2_N
PE1_TX3_P
PE1_TX3_N
+AVDD0_PEX1
+AVDD0_PEX2
+AVDD0_PEX3
+AVDD0_PEX4
+AVDD0_PEX5
+AVDD0_PEX6
+AVDD0_PEX7
+AVDD0_PEX8
+AVDD0_PEX9
+AVDD0_PEX10
+AVDD0_PEX11
+AVDD0_PEX12
+AVDD0_PEX13
+AVDD1_PEX1
+AVDD1_PEX2
+AVDD1_PEX3
C5
D4
C4
B4
A4
A3
B3
B2
C1
D1
D2
E1
E2
F2
F3
F4
G3
H4
H3
H2
H1
J1
J2
J3
K2
K3
L4
L3
M4
M3
M2
M1
E11
D11
G11
F11
J11
J10
G13
F13
J13
H13
L14
K14
N14
M14
K11
D8
C8
B8
A8
A7
B7
B6
C6
Y12
AA12
AB12
M12
P12
R12
N12
T12
U12
AC12
AD12
V12
W12
M13
N13
P13
MCP79_PCIE_RST#
PCIE_TX0_P
PCIE_TX0_N
PCIE_TX1_P
PCIE_TX1_N
PCIE_TX2_P
PCIE_TX2_N
PCIE_TX3_P
PCIE_TX3_N
CLK_PCIE_EXPR
CLK_PCIE_EXPR#
CLK_PCIE_LANLAN_CLKREQ#
CLK_PCIE_LAN#
CLK_PCIE_WLAN
CLK_PCIE_WLAN#
CLK_PCIE_1394
CLK_PCIE_1394#
2
C59
0.1U_0402_16V7K
1
PCIE_TX0_P 23
PCIE_TX0_N 23
PCIE_TX1_P 22
PCIE_TX1_N 22
PCIE_TX2_P 24
PCIE_TX2_N 24
PCIE_TX3_P 26
PCIE_TX3_N 26
+AVDD_PEX
2
C60
0.1U_0402_16V7K
1
1
C61
1U_0402_6.3V4Z
2
2
CLK_PCIE_EXPR 23
CLK_PCIE_EXPR# 23
CLK_PCIE_LAN 22
CLK_PCIE_LAN# 22
CLK_PCIE_WLAN 24
CLK_PCIE_WLAN# 24
CLK_PCIE_1394 26
CLK_PCIE_1394# 26
Express Card
LAN
WLAN
IEEE1394
1.2A
1
C62
1U_0402_6.3V4Z
2
1
MCP79_PCIE_RST#
R35
1 2
0_0402_5%
2
C43
0.1U_0402_16V7K
@
1
PCIE_RST# 22,23,24,26
Express Card
LAN
WLAN
IEEE1394
L11
1 2
2
C63
2.2U_0402_6.3VM
1
BLM21PG221SN1D_0805~D
1
C64
10U_0805_10V4Z
2
+VCCP
1.1VS
A A
5
4.7U_0603_6.3V6K
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/02/19 2009/12/31
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
MCP79(4/10)-PCI EXPRESS
LA-4631P
1
of
10 42Tuesday, Fe b r u a r y 24, 2009
1.0
5
4
3
2
1
R1301
0_0603_1%
1 2
1
C70
2
0.1U_0402_16V4Z
1 2
1 2
R71 22_0402_5% @
1 2
R83 1K_0402_1%@
1 2
C91 0.1U_0402_16V4Z@
1 2
+3VALW
@
R1302
0_0603_1%
1 2
264 mA
4.7U_0603_6.3V6K
LCD_DDC_CLK 20
LCD_DDC_DATA 20
LVDSAC+ 20
LVDSAC- 20
LVDSA0+ 20
LVDSA0- 20
LVDSA1+ 20
LVDSA1- 20
LVDSA2+ 20
LVDSA2- 20
LVDSBC+ 20
LVDSBC- 20
LVDSB0+ 20
LVDSB0- 20
LVDSB1+ 20
LVDSB1- 20
LVDSB2+ 20
LVDSB2- 20
SCL_DP_MCP 21
SDA_DP_MCP 21
SCL_HDMI_MCP 21
SDA_HDMI_MCP 21
2.2U
+1.05VALW_MAC_R
1
C71
C72
2
0.1U_0402_16V4Z
SLP_RMGT#14
SLP_MCP79_MAC#28
+1.05VALW_MAC
12
R1306
0_0603_1%
R57 0_0603_1%
1 2
4.7U_0603_6.3V6K
PHY_25MHZ 22
PHY_25MHZ
@
1
C309
2
0.1U_0402_16V4Z
Signal : TXD0_R
Strap: Networking select
Strapped Value : 0: MII 1: RGMII
Description : Selects an MII interface or an RGMII interface for MAC.
@
1 2
R1308
0_0402_5%
@
R1311
0_0402_5%
1.1VALW
+1.05VALW
+3.3VALW_MAC_REF
R163
LCD_DDC_CLK
LCD_DDC_DATA
+1.05VS_PLL
C176
R1307
20K_0402_1%
12
+3VS +3VS
12
R186
2.7K_0402_5%
C175
4.7U_0603_6.3V6K
+3VALW
12
@
1
C656
0.01U_0402_25V7K
2
12
2.7K_0402_5%
L13
1 2
10NH_LQG15HS10NJ02D _5%_0402~D
1
2
2.2U_0402_6.3VM
+1.05VALW
20 mil
AO3416_SOT23
13
D
Q67
2
G
S
+1.05VALW_MAC
20 mil
2
G
12
R63
10K_0402_5%
1.1VS
+VCCP
1.1VALW_MAC
1.1VALW_MAC
+1.05VALW_MAC
1
C657
0.1U_0402_16V4Z
2
+3VALW +3VALW
12
R1309
10K_0402_5%
R1310
13
D
Q69
2N7002_SOT23
S
0_0402_5%
1 2
@
C658
G
2
0.01U_0402_25V7K
1
2
20 mil
Q68
S
AO3413_SOT23
D
1 3
+3.3VALW_MAC
20 mil
+3.3VALW_MAC
MCP79_AUX-
MCP79_AUX+
R54
@
R55
2.2U_0402_6.3VM
22K_0402_5%
+1.8VS
+3VS
+VCCP
12
R1263
10K_0402_5%
12
R1264
1 2
1 2
C83 10U_0805_10V4Z@
16 mA
1
C88
2
10K_0402_5%
@
1K_0402_5%
C76
4.7U_0603_6.3V6K
1 2
1.1VS
2.2U_0402_6.3VM
12
R1265
9 mA
+3.3VALW_MAC
TI_PRIORITY21
MCP_DP_CBL_DET21
MCP79_LCD_PWM20
MCP79_ENBKL28
MCP79_ENVDD20,28
MCP79_DP3+21
MCP79_DP3-21
MCP79_DP2+21
MCP79_DP2-21
MCP79_DP1+21
MCP79_DP1-21
MCP79_DP0+21
MCP79_DP0-21
MCP79_AUX+21
MCP79_AUX-21
HDMI_HPD21
MCP_DP_HPD21
1
C89
2
2.2U_0402_6.3VM
12
R1266
10K_0402_5%
R69
+1.05VS_PLL
R80 0_0603_1%
1 2
2.2U
R81
1 2
95 mA
12
R1267
10K_0402_5%
10K_0402_5%
1 2
49.9_0402_1%
R70 49.9_0402_1%
+1.05VS_PLL
R79 0_0402_5%
0_0603_1%
0.1U_0402_16V4Z
12
12
R1269
R1268
10K_0402_5%
RXD0
RXD1
RXD2
RXD3
RXCLK
RXCTL
1 2
R61
RGMII_INT
+V_DUAL_MACPLL
+MII_COMP_VDD
1 2
66 mA
TI_PRIORITY
MCP_DP_CBL_DET
MCP79_LCD_PWM
MCP79_ENBKL
MCP79_ENVDD
MCP79_DP3+
MCP79_DP3-
MCP79_DP2+
MCP79_DP2MCP79_DP1+
MCP79_DP1MCP79_DP0+
MCP79_DP0-
MCP79_AUX+
MCP79_AUX-
1 2
190 mA
1 2
C842.2U_0402_6.3VM
12
C850.1U_0402_16V4Z
+3VS_PLL_HDMI
C864.7U_0603_6.3V6K
12
12
R821K_0402_1%
1 2
12
C90
@
10K_0402_5%
47K_0402_5%
MII_COMP_GND
+1.8VS_IFP
C870.1U_0402_16V4Z
C4480.1U_0402_16V4Z
HDMI_RSET
HDMI_VPROBE
U4F
C23
RGMII_RXD0
B23
RGMII_RXD1
E24
RGMII_RXD2
A24
RGMII_RXD3
A23
RGMII_RXC/MII_RXCLK
C22
RGMII_RXCTL/MII_RXDV
F23
MII_RXER/GPIO_36
B26
MII_COL/GPIO_20/MSMB_DATA
B22
MII_CRS/GPIO_21/MSMB_CLK
J22
RGMII_INTR/GPIO_35
T23
+V_DUAL_MACPLL
C27
MII_COMP_VDD
B27
MII_COMP_GND
C39
RGB_DAC_RSET
B38
RGB_DAC_VREF
E36
TV_DAC_RSET
A35
TV_DAC_VREF
T28
+V_VPLL
U27
+V_PLL_CORE
C38
XTALIN_TV
D38
XTALOUT_TV
E16
GPIO_6/FERR/IGPU_GPIO_6#
B15
GPIO_7/NFERR/IGPU_GPIO_7#
G39
LCD_BKL_CTL/GPIO_57
E37
LCD_BKL_ON/GPIO_59
F40
LCD_PANEL_PWR/GPIO_58
D35
HDMI_TXC_P/ML0_LANE3_P
E35
HDMI_TXC_N/ML0_LANE3_N
G35
HDMI_TXD0_P/ML0_LANE2_P
F35
HDMI_TXD0_N/ML0_LANE2_N
F33
HDMI_TXD1_P/ML0_LANE1_P
G33
HDMI_TXD1_N/ML0_LANE1_N
J33
HDMI_TXD2_P/ML0_LANE0_P
H33
HDMI_TXD2_N/ML0_LANE0_N
D43
DP_AUX_CH0_P
C43
DP_AUX_CH0_N
C31
HPLUG_DET2/GPIO_22
F31
HPLUG_DET3
M27
+VDD_IFPA
M26
+VDD_IFPB
M28
+V_PLL_IFPAB
M29
+V_PLL_HDMI
T25
+VDD_HDMI
J31
HDMI_RSET
J30
HDMI_VPROBE
MCP79MX-B2 PBGA 1437P
LAN
DACS
FLAT
PANEL
+3.3V_DUAL_RMGT1
+3.3V_DUAL_RMGT2
+V_DUAL_RMGT1
+V_DUAL_RMGT2
MII_VREF
RGMII_TXD0
RGMII_TXD1
RGMII_TXD2
RGMII_TXD3
RGMII_TXC/MII_TXCLK
RGMII_TXCTL/MII_TXEN
RGMII_MDC
RGMII_MDIO
RGMII_PWRDWN/GPIO_37
BUF_25MHZ
MII_RESET#
+V_RGB_DAC
+V_TV_DAC
DDC_CLK0
DDC_DATA0
RGB_DAC_RED
RGB_DAC_GREEN
RGB_DAC_BLUE
RGB_DAC_HSYNC
RGB_DAC_VSYNC
TV_DAC_RED
TV_DAC_GREEN
TV_DAC_BLUE
TV_DAC_HSYNC/GPIO_44
TV_DAC_VSYNC/GPIO_45
IFPA_TXC_P
IFPA_TXC_N
IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N
IFPB_TXC_P
IFPB_TXC_N
IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N
DDC_CLK2/GPIO_23
DDC_DATA2/GPIO_24
DDC_CLK3
DDC_DATA3
IFPAB_RSET
IFPAB_VPROBE
264 mA
J24
K24
U23
V23
E28
B24
C24
C25
D25
D24
C26
D21
C21
G23
E23
J23
J32
K32
B31
A31
B39
A39
B40
A40
A41
A36
B36
C36
D36
C37
B35
C35
B32
A32
D32
C32
D33
C33
B34
C34
L31
K31
J29
H29
L29
K29
L30
K30
N30
M30
C30
B30
D31
E31
E32
G31
+3.3VALW_MAC_R
TXCLK_R
PHY_25MHZ_R
LCD_DDC_CLK
LCD_DDC_DATA
LVDSAC+
LVDSAC-
LVDSA0+
LVDSA0LVDSA1+
LVDSA1LVDSA2+
LVDSA2-
LVDSBC+
LVDSBC-
LVDSB0+
LVDSB0LVDSB1+
LVDSB1LVDSB2+
LVDSB2-
SCL_DP_MCP
SDA_DP_MCP
SCL_HDMI_MCP
SDA_HDMI_MCP
IFPAB_RSET
IFPAB_VPROBE
C69
R67 10K_0402_5%
R1262 10K_0402_5%
1K_0402_5%
D D
C C
B B
A A
1.1VALW_MAC
+1.05VALW_MAC
12
L4
BLM18AG121SN1D_0603
1
C75
2
MCP79_ENVDD
12
R1279
RGMII_INT
RXCTL
RXCLK
RXD3
RXD2
RXD1
RXD0
Security Classification
Issued Date
THIS SHEET OF ENGI NEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY COMPAL ELECTRONIC S, INC. NEITH ER THIS SHEE T NOR THE IN FORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CO NSENT OF CO MPAL ELECTR ONICS, INC.
3
2009/02/19 2009/12/31
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
MCP79(5/10)-LAN,RGB,TV,LVD
Size Document Number Rev
2
Date: Sheet
LA-4631P
1
11 42Tuesday, Febru ar y 24, 2009
1.0
of
5
4
3
+3VS
2
1
GPIO
R191
R192
R193
X76L02@
1 2
8.2K_0402_5%
D D
R94 8.2K_0402_5%
+3VS
C C
+3VS
B B
1 2
R95 8.2K_0402_5%
1 2
R92 8.2K_0402_5%
1 2
R98 8.2K_0402_5%
1 2
R97 8.2K_0402_5%
1 2
R99 8.2K_0402_5%
1 2
R124 8.2K_0402_5%
1 2
R138 8.2K_0402_5%
1 2
R140 8.2K_0402_5%
1 2
R147 8.2K_0402_5%
1 2
SERIRQ28
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
HB_PWR_EN
PCI_REQ#4
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_TRDY#
SERIRQ
U4G
T2
PCI_REQ0#
V9
PCI_REQ1/FANRPM2#
T3
PCI_REQ2#/GPIO_40/RS232_DSR#
U9
PCI_REQ3#/GPIO_38/RS232_CTS#
T4
PCI_REQ4#/GPIO_52/RS232_SIN#
AC3
PCI_AD0
AE10
PCI_AD1
AC4
PCI_AD2
AE11
PCI_AD3
AB3
PCI_AD4
AC6
PCI_AD5
AB2
PCI_AD6
AC7
PCI_AD7
AC8
PCI_AD8
AA2
PCI_AD9
AC9
PCI_AD10
AC10
PCI_AD11
AC11
PCI_AD12
AA1
PCI_AD13
AA5
PCI_AD14
Y5
PCI_AD15
W3
PCI_AD16
W6
PCI_AD17
W4
PCI_AD18
W7
PCI_AD19
V3
PCI_AD20
W8
PCI_AD21
V2
PCI_AD22
W9
PCI_AD23
U3
PCI_AD24
W11
PCI_AD25
U2
PCI_AD26
U5
PCI_AD27
U1
PCI_AD28
U6
PCI_AD29
T5
PCI_AD30
U7
PCI_AD31
P2
PCI_INTW#
N3
PCI_INTX#
N2
PCI_INTY#
N1
PCI_INTZ#
Y3
PCI_TRDY#
AD11
PCI_CLKRUN/GPIO_42#
AE2
LPC_DRQ1/GPIO_19#
AE1
LPC_DRQ0#
AE6
LPC_SERIRQ
U24
GND65
U26
GND66
U39
GND67
U4
GND68
U8
GND69
V16
GND70
V17
GND71
V18
GND72
V20
GND73
V22
GND74
V24
GND75
V26
GND76
V27
GND77
V28
GND78
V33
GND79
V37
GND80
V4
GND81
V40
GND82
V7
GND83
W20
GND84
W22
GND85
W24
GND86
W36
GND87
W40
GND88
W43
GND89
Y16
GND90
Y17
GND91
Y18
GND92
Y19
GND93
Y20
GND94
Y22
GND95
Y24
GND96
Y25
GND97
MCP79MX-B2 PBGA 1437P
PCI
GND
PCI_GNT2#/GPIO_41/RS232_DTR#
PCI_GNT3#/GPIO_39/RS232_RTS#
PCI_GNT4#/GPIO_53/RS232_SOUT#
PCI_PERR#/GPIO_43/RS232_DCD#
LPC_PWRDWN#/GPIO_54/EXT_NMI#
LPC
PCI_GNT0#
PCI_GNT1/FANCTL2#
PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_PAR
PCI_SERR#
PCI_STOP#
PCI_PME/GPIO_30#
PCI_RESET0#
PCI_RESET1#
PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLKIN
LPC_FRAME#
LPC_RESET0#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_CLK0
GND98
GND99
GND100
GND101
GND102
GND103
GND104
GND105
GND106
GND107
GND108
GND109
GND110
GND111
GND112
GND113
GND114
GND115
GND116
GND117
GND118
GND119
GND120
GND121
GND122
GND123
GND124
GND125
GND126
GND127
GND128
GND129
GND130
R3
U10
R4
U11
P3
AA3
AA6
AA11
W10
PCI_DEVSEL#
AA9
PCI_FRAME#
Y4
PCI_IRDY#
AA10
Y1
PCI_PERR#
AB9
PCI_SERR#
AA7
PCI_STOP#
Y2
T1
R10
R11
R6
R96 0_0402_5%
R7
PCI_CLK2
R8
PCI_CLKIN
R9
R_LPC_FRAME#
AD4
AE12
AE5
R_LPC_AD0
AD3
R_LPC_AD1
AD2
R_LPC_AD2
AD1
R_LPC_AD3
AD5
LPC_CLK0_R
AE9
Y26
Y27
AB18
H34
AB20
AB21
AB23
AB24
AB25
AB26
AB27
AB28
AB34
AB37
AB4
AB40
AC22
AC36
AC40
AB33
AC5
AD16
AD17
AD18
AD19
AD20
AD24
AD25
AD26
AD27
AD28
AD33
AD34
R194
X76L01@
1 2
1 2
R104
@
1
C96
10P_0402_50V8J
2
8.2K_0402_5%
1 2
@
X76L01@
1 2
1 2
8.2K_0402_5%
8.2K_0402_5%
R196
R195
X76L02@
1 2
1 2
8.2K_0402_5%
8.2K_0402_5%
X76L01@X76L02@
R1488.2K_0402_5%
1 2
R1508.2K_0402_5%
1 2
R1588.2K_0402_5%
1 2
R1888.2K_0402_5%
1 2
R1898.2K_0402_5%
1 2
R1908.2K_0402_5%
1 2
PCI_PME# HAS INTERNAL PULLUP
T9
1
C95
@
2
10P_0402_50V8J
1 2
33_0402_5%
R105 22_0402_5%
1 2
R107 22_0402_5%
1 2
R108 22_0402_5%
1 2
R109 22_0402_5%
1 2
22_0402_5%
LPC_CLK0
R110
1 2
+3VS
R100
1 2
22_0402_5%
R101
22_0402_5%
PLT_RST# 24,28
Hynix 1G
Samsung 1G
LPC_FRAME#
LPC_AD0 24,28
LPC_AD1 24,28
LPC_AD2 24,28
LPC_AD3 24,28
LPC_CLK0 24,28
39
1
(R192)
0
(R195)
HDA_SDATA_OUT (MSB)
LPC_FRAME# (LSB)
00: Boot ROM l o cated on LPC bus
01: Boot ROM l o cated on PCI bus
10: Boot ROM l o cated on SPI bus
(SPI_CS0)
11: Boot ROM l o cated on SPI bus
(SPI_CS1)
12
R106
10K_0402_5%
41
0
(R194)
1
(R191)
LPC_FRAME# 24,28
53
0
(R196)
0
(R196)
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/02/19 2009/12/31
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
MCP79(6/10)-PCI & LPC
LA-4631P
1
12 42Tuesday, Fe b r u a r y 24, 2009
1.0
of
5
4
3
2
1
D D
SATA HDD
ESATA
C C
SATA_A0_TXP20
SATA_A0_TXN20
SATA_A0_RXN20
SATA_A0_RXP20
SATA_A1_TXP29
SATA_A1_TXN29
SATA_A1_RXN29
SATA_A1_RXP29
SATA_A0_TXP
SATA_A0_TXN
SATA_A0_RXN
SATA_A0_RXP
SATA_A1_TXP
SATA_A1_TXN
SATA_A1_RXN
SATA_A1_RXP
1.1VS
+VCCP
12
L8
10NH_LQG1 5 HS10NJ02D_5%_0402~D
81 mA
C100
1.1VS
+VCCP
R115
4.7U_0603_6.3V6K
0_0603_1%
1.1VS
53 mA
+VCCP
L9
BLM18AG121SN1D_0603
1 2
136 mA
C108
+AVDD_SATA
1
2
B B
A A
2
C101
1
10U_0805_10V4Z
2.2U
+V_PLL_SATA
2.2U_0402_6.3VM
2
C109
1
2.2U_0402_6.3VM
+DVDD_SATA
2
1
C110
0.1U_0402_16V7K
2
C111
1
2
1
0.1U_0402_16V7K
2
C106
1
C452
0.1U_0402_16V7K
2
1
2.2U_0402_6.3VM
SATA_TERMP
12
R117
2.49K_0402_1%
C107
0.1U_0402_16V7K
U4H
AJ7
SATA_A0_TX_P
AJ6
SATA_A0_TX_N
AJ5
SATA_A0_RX_N
AJ4
SATA_A0_RX_P
AJ11
SATA_A1_TX_P
AJ10
SATA_A1_TX_N
AJ9
SATA_A1_RX_N
AK9
SATA_A1_RX_P
AK2
SATA_B0_TX_P
AJ3
SATA_B0_TX_N
AJ2
SATA_B0_RX_N
AJ1
SATA_B0_RX_P
AM4
SATA_B1_TX_P
AL3
SATA_B1_TX_N
AL4
SATA_B1_RX_N
AK3
SATA_B1_RX_P
AN1
SATA_C0_TX_P
AM1
SATA_C0_TX_N
AM2
SATA_C0_RX_N
AM3
SATA_C0_RX_P
AP3
SATA_C1_TX_P
AP2
SATA_C1_TX_N
AN3
SATA_C1_RX_N
AN2
SATA_C1_RX_P
E12
SATA_LED#
AE16
+V_PLL_SATA
AF19
+DVDD0_SATA1
AG16
+DVDD0_SATA2
AG17
+DVDD0_SATA3
AG19
+DVDD0_SATA4
AH17
+DVDD1_SATA1
AH19
+DVDD1_SATA2
AJ12
+AVDD0_SATA1
AN11
+AVDD0_SATA2
AK12
+AVDD0_SATA3
AK13
+AVDD0_SATA4
AL12
+AVDD0_SATA5
AM11
+AVDD0_SATA6
AM12
+AVDD0_SATA7
AN12
+AVDD0_SATA8
AL13
+AVDD0_SATA9
AN14
+AVDD1_SATA1
AL14
+AVDD1_SATA2
AM13
+AVDD1_SATA3
AM14
+AVDD1_SATA4
AE3
SATA_TERMP
MCP79MX-B 2 P B G A 1437P
USBSATA
USB_OC2/GPIO_27/MGPIO#
USB_OC3/GPIO_28/MGPIO#
USB0_P
USB0_N
USB1_P
USB1_N
USB2_P
USB2_N
USB3_P
USB3_N
USB4_P
USB4_N
USB5_P
USB5_N
USB6_P
USB6_N
USB7_P
USB7_N
USB8_P
USB8_N
USB9_P
USB9_N
USB10_P
USB10_N
USB11_P
USB11_N
USB_OC0/GPIO_25#
USB_OC1/GPIO_26#
+V_PLL_USB
+3.3V_DUAL_USB1
+3.3V_DUAL_USB2
+3.3V_DUAL_USB3
+3.3V_DUAL_USB4
USB_RBIAS_GND
GND131
GND132
GND133
GND134
GND135
GND136
GND137
GND138
GND139
GND140
GND141
GND142
GND143
GND144
GND145
GND146
GND147
GND148
GND149
GND150
GND151
GND152
GND153
GND154
GND155
GND156
GND157
GND158
GND159
GND160
C29
D29
C28
D28
A28
B28
F29
G29
K27
L27
J26
J27
F27
G27
D27
E27
K25
L25
H25
J25
F25
G25
K23
L23
L21
K21
J21
H21
L28
G26
H27
J28
K28
A27
AD35
AD37
AD38
AE22
AE24
AE39
AE4
AD6
AF16
AF17
AF18
AF20
AF22
AF26
AF27
AF28
AF33
AF34
AF37
AF40
AG18
AG20
AG22
AG26
AG36
AG40
AH18
AH20
AH22
AH24
USB20_P0
USB20_N0
USB20_P1
USB20_N1
USB20_P2
USB20_N2
USB20_P3
USB20_N3
USB20_P4
USB20_N4
USB20_P5
USB20_N5
USB20_P6
USB20_N6
USB20_P7
USB20_N7
USB20_P8
USB20_N8
USB_OC#0
USB_OC#1
USB_OC#2
PM_EXTTS#0_1
+V_PLL_USB
200 mA
+3.3V_DUAL_U SB
USB_RBIAS
R116
806_0402_1%
1 2
USB20_P0 27
USB20_N0 27
USB20_P1 29
USB20_N1 29
USB20_P2 29
USB20_N2 29
USB20_P3 23
USB20_N3 23
USB20_P4 27
USB20_N4 27
USB20_P5 27
USB20_N5 27
USB20_P6 24
USB20_N6 24
USB20_P7 24
USB20_N7 24
T26
T27
+3VALW
R113
0_0603_1%
2
C104
1
USB0
USB1
USB2
Express Card
Camera
BlueTooth
WWAN
WLAN
USB_OC#0 27
USB_OC#1 29
USB_OC#2 29
PM_EXTTS#0_1 19
C105
4.7U_0603_6.3V6K
2.2U_0402_6.3VM
18 mA
2
C97
1
2.2U_0402_6.3VM
2
1
C98
0.1U_0402_16V7K
+3VS
L7
BLM18AG121SN1D_0603
1 2
C99
4.7U_0603_6.3V6K
USB_OC#0
USB_OC#2
USB_OC#1
R78 10K_0402_5%
1 2
R103 10K_0402_5%
1 2
R111 10K_0402_5%
1 2
+5VALW
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH OUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2009/02/19 2009/12/31
Compal Secret Data
Deciphered Date
2
Title
Size Document Number Re v
Date: Sheet
Compal Electronics, Inc.
MCP79(7/10)-SATA & USB
LA-4631P
1
of
13 42Tuesday, F ebruary 24, 2009
1.0
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