COMPAL LA-4602P Schematics

A

1 1

2 2

B

C

D

E

Blue Moutain KIWB1/B2

Schematics Document

Mobile Penryn uFCPGA with Intel

3 3

Cantiga_GM/PM+ICH9-M core logic

REV:2.0

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/03/16 2010/03/15

2009/03/16 2010/03/15

2009/03/16 2010/03/15

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics,Ltd.

Compal Electronics,Ltd.

Compal Electronics,Ltd.

Title

Title

Title

Cover Sheet

Cover Sheet

Cover Sheet

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

KIWB1/B2_LA4602P

KIWB1/B2_LA4602P

KIWB1/B2_LA4602P

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

1 53Wednesday, March 18, 2009

1 53Wednesday, March 18, 2009

1 53Wednesday, March 18, 2009

E

2.0

2.0

2.0

A

Compal confidential

File Name :

VRAM 64*16

1 1

DDR3*8

page20

PCI-E X16

NVidia N10M-GS1
NVidia N10P-GE1

page16~24

CONN

page26

PS8101T

page26

PCI-EHDMI

CRT cable

page28

2 2

LVDS
Connector

page27

PCI Express
Mini card Slot 1

page31

PCI Express
Mini card Slot 2

page31

6*PCI-E BUS

New Card

PCI Express
Mini card Slot 3

3 3

page31

BCM5906/BCM5784M

SIM Card

page31

10/100/1G LAN

RJ45 CONN

ZZZ1

ZZZ1

15.6W_PCB_LA4601P

15.6W_PCB_LA4601P

LVDS I/F

page31

page33

B

None
PCI BUS

3.3V / 33 MHz

page32

C

Mobile Penryn

uFCPGA-478 CPU

page5,6,7

H_A#(3..35)
H_D#(0..63)

FSB
667/800/1066MHz

Intel Cantiga GMCH

PCBGA 1329

page 8,9,10,11,12,13

DMI

C-Line

Intel ICH9-M

mBGA-676

page27,28,29,30

LPC BUS

EC

ENE KB926D

page38

Int.KBD

Touch Pad

page39

BIOS

POWER BD
Power on X1
LED X1 (G)

:POWER
NOVO X1

Clock Gen.

SLG8SP556VTR
ICS9LPRS387AKLFT

DDR3-800(1.5V)
DDR3-1067(1.5V)

Dual Channel

AZALIA

12*USB2.0

4*SATA serial

page39

page40

D

Slide Bar LED X 10 (B)
USER-DEFINED (W)
DOLBY (W)
LED X 3
WIRELESS LED (G)
BLUETOOTH LED (G)
3G LED (G)
HDD LED (G)

page25

POWER ON (G)
BATTERY CHARG(G/A)
WIRELESS SWITCH (G)
ON/OFF

Double check ME

DDR3-SO-DIMM X2

BANK 0, 1, 2, 3

UP TO 8G

SPK amplifier

page36

WOOFER amplifier

Audio Codec

Realtek ALC272

page36

CMOS Camera
BlueTooth CONN
USB CONN X1
New Card X1
M-PCIE CONN X 3

REPEATER

page35

E

RIGHT BD
VOLUME UP X1
VOLUME DOWN X1
MUTE X1
MUTE LED X1(G)

USB_Board
USB CONN X 2
TV CONN X1

page 14,15

2Channel Speaker

page37

1Channel Speaker

HP X 1+

page37

page36

page41

page41

page41

page31

page31

MIC_Ext X1
2Channel MIC_Int

Realtek 5158E
MS/MS
pro/SD/SD
pro/mmc/XD

ESATA HDD AND USB CONN

page37

page37

page36

page35

HDD/ODD,SCL & T/L LED on MB

4 4

A

CAPS and NUM on KBD

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/03/16 2010/03/

2009/03/16 2010/03/

2009/03/16 2010/03/

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

SATA HDD CONN
SATA ODD CONN

D

page35

page35

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

MB Block Diagram

MB Block Diagram

MB Block Diagram

KIWB1/B2_LA4602P

2 53Wednesday, March 18, 2009

2 53Wednesday, March 18, 2009

2 53Wednesday, March 18, 2009

E

0.1

0.1

0.1

A

B

C

D

E

DDR3 Voltage Rails

+5VS
+3VS

power
plane

1 1

+B

State

S0

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O

O
O
O

X

+5VALW

+3VALW

O

O
O

X
X X X

+1.5V

O

X X
X

@ FUNCTION

100@
TVSW@
AO@
MONO@

3 3

BT@ WITH BLUETOOTH
3G@ WITH 3G
TV@ WITH TV

4 4

(100 LAN)
(TV POWER SW)
(ALWAYS ON SW)
(MONO MIC)
(X76 BOM)

10M@
10P@
PM@
45@X76@
GM@
GM45@
GL40@
GIGA@
NO_TVSW@
NO_AO@
ARRAY@
S512@
Q512@
S256@
Q256@

(N10M 40nm CHIPSET)
(N10P 40nm CHIPSET)
(VGA BOM)
(45 BOM)
(UMA BOM)
(GM45 BOM)
(GL40 BOM)
(GIGA LAN)
(NON TV POWER SW)
(NON ALWAY ON SW)
(ARRAY MIC)

FOR X76 BOM
FOR X76 BOM
FOR X76 BOM
FOR X76 BOM

+1.5VS
+1.1VS
+VCCP
+CPU_CORE
+VGA_CORE
+1.8VS

+0.75V

OO

X

X

SMBUS, SPI and I2C Control Table

SOURCE

HDMI BATTEEPROM

LVDS

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

ICH_SMBCLK
ICH_SMBDAT ICH9

LVDS_SCL
LVDS_SDA

GMCH_CRT_CLK
GMCH_CRT_DAT

HDMICLK_NB
HDMIDAT_NB

VGA_DDCCLK
VGA_DDCDATA

VGA_LVDS_SCL
VGA_LVDS_DAT

VGA_HDMI_SCL
VGA_HDMI_DAT

HDCP_SMB_CK1
HDCP_SMB_DA1

FSEL#SPICS#_SB
FRD#SPI_SO_SB
SPI_CLK_SB
FWR#SPI_SI_SB

FSEL#SPICS#
FRD#SPI_SO
SPI_CLK
FWR#SPI_SI

KB926

X

X

KB926

X

X

X

X

Cantiga

X

V

Cantiga

X X X X X X X X X X X X

Cantiga

VGA

VGA

VGA

VGA

ICH9

KB926

X X X X X X X X X X X X

V

X

X

X

V

X

V

X

X

X

XXX

X

HDCP

SERIAL

CRT

X X
X

X
X X X X
X X X X

NEW

CLK

CARD

GEN

X

X X
X

X
X

X

X

X

V V

X X

Mini

CAP
sensor

X X

CARD1

X
X

Mini
CARD2

X
X

V V

X

X

V

X
X
X

THERMAL
SENSOR
(VGA)

V

X
X

THERMAL
SENSOR
(CPU)

VV

V

X X X X X X X X X X

V

X

X X X X X X X X X X
X

X
X

X

X
X X

X X X X X X X X X

X X X X X X X

V

X X X X X X X

V
V

XXXXXXX

X
X

X

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/03/16 2010/03/15

2009/03/16 2010/03/15

2009/03/16 2010/03/15

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

MB Notes List

MB Notes List

MB Notes List

KIWB1/B2_LA4601P

3 53Wednesday, March 18, 2009

3 53Wednesday, March 18, 2009

3 53Wednesday, March 18, 2009

E

0.1

0.1

0.1

A

B

C

D

E

Performance Mode P0 TDP at Tj = 102 C* (DDR3)VGA and DDR3 Voltage Rails (N10x GPIO)

GPIO I/O ACTIVE Function Description
GPIO0
GPIO1
GPIO2

1 1

GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13

2 2

GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23

3 3

N/A

N/A
IN

-

Hot plug detect for IFP link C
OUT
OUT
OUT
OUT
OUT
OUT
I/O
OUT
OUT
I/O
IN
OUT
OUT
IN
OUT
IN
IN
IN
IN
IN
IN

Panel Back-Light brightness(PWM capable)

H

Panel Power Enable

H

Panel Back-Light On/Off (PWM)

H

GPU VID0

­GPU VID1

­GPU VID2

­Thermal Catastrophic Overtemp

L

Thermal Alert

L

Memory VREF switch
SLI raster sync

L

AC power detect pin

­MEM_VID orPower supply control

-

- Power supply control

-

Hot plug detect for IFP Link E

-

Programmable Fan Control

-

-

-

Hot plug detect for IFP Link D

-

-

Hot plug detect for IFP link F

-

SLI swap ready signal

I/O

GPIO5GPIO6 N10M-GS N10P-GS

(+VGA_CORE)

Products

N10P-GS
128bit
1024MB
DDR3

N10P-GE
128bit
1024MB
DDR3

N10P-LP
128bit
1024MB
DDR3

Performance Mode P0 TDP at Tj = 102 C* (DDR3)

Products

N10M-GE
64bit
512MB
DDR3

N10M-GS
64bit
512MB
DDR3

N10M-LP
64bit
512MB
DDR3

Power Sequence

(+3VS)

(1.1VS)

GPU Mem NVCLK
(4) (1,5) (6)

(W) (W)

21.07

20.97

15.48

GPU Mem NVCLK
(4) (1,5) (6)

(W) (W)

13.36

14.29

8.28

/MCLK NVVDD
(MHz)

6.67

TBD

6.73

TBD

6.44

TBD

/MCLK NVVDD
(MHz)

2.93

TBD

3.10

TBD

2.91

TBD

(V) (A) (W) (A) (W) (A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

TBD

18.25

TBD

19.17

TBD

13.95

(V) (A) (W) (A) (W)

TBD

11.89

TBD

11.53

TBD

6.60

The ramp time for any rail must be more than 40us

VDD33

PEX_VDD

NVVDD

17.34

17.25

11.86

10.70

11.53

5.61

tNVVDD

FBVDD

2.06

2.03

1.90

FBVDD

0.66

0.70

0.62

GPU_VID11GPU_VID011VGA_CORE P-State

0 0.8V
0

0

0.85V

0.9V

12
12
0, 10

IFPAB_IOVDD

(1.8VS)

FBVDDQ

FBVDDQ PCI Express I/O and
(GPU+Mem)
(1.5V)(1.5V)

3.09

4.09

3.05

4.09 6.14

2.85

3.99

FBVDDQ PCI Express I/O and
(GPU+Mem)
(1.5V)(1.5V)

(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

0.99

2.16

1.05

2.28 3.42

0.93

2.20

(1.05V)

6.14

850 75 0.14

5.99

810

(1.05V)

3.24

792 75 0.14

3.3

782

0.89

0.88840

0.85

0.83

0.86817

0.82

PLLVDD

75 0.14

75 0.14

PLLVDD

75 0.14

75 0.14

PEX_VDD can ramp up any time

tNV-IFPAB_IOVDD

tNV-FBVDDQ

I/O and
PLLVDD

63 0.07

63 0.07

63 0.07

I/O and
PLLVDD

63 0.07

63 0.07

63 0.07

Other
(3.3V)(1.05V)(1.8V)

55 0.18

55 0.18

55 0.18

Other
(3.3V)(1.05V)(1.8V)

100 0.33

100 0.33

100 0.33

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/03/16 2010/03/15

2009/03/16 2010/03/15

2009/03/16 2010/03/15

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

VGA Notes List

VGA Notes List

VGA Notes List

KIWB1/B2_LA4602P

4 53Wednesday, March 18, 2009

4 53Wednesday, March 18, 2009

4 53Wednesday, March 18, 2009

E

0.1

0.1

0.1

5

4

3

2

1

XDP Reserve

+VCCP

SMCLK

SMDATA

ALERT#

GND

1 2

U2

U2

VEN
VIN
VO
VSET

G990P11U_SO8

G990P11U_SO8

12

+VCC_FAN1

1

2

XDP_DBRESET#

XDP_TDI
XDP_TMS
XDP_TDO
XDP_TRST#
XDP_TCK

+3VS

12

@ R9

@

8
7
6
5

8

GND

7

GND

6

GND

5

GND

40mil

+VCC_FAN1

R2 1K_0402_5%@R2 1K_0402_5%@

1 2

R4 54.9_0402_1%R4 54.9_0402_1%

1 2

R5 54.9_0402_1%R5 54.9_0402_1%

1 2

R6 54.9_0402_1%@R6 54.9_0402_1%@

1 2

R7 54.9_0402_1%R7 54.9_0402_1%

1 2

R8 54.9_0402_1%R8 54.9_0402_1%

1 2

R9
10K_0402_5%

10K_0402_5%

EC_SMB_CK2
EC_SMB_DA2

+5VS

12

@

@

D1

D1
1SS355TE-17_SOD323-2

1SS355TE-17_SOD323-2
D2 BAS16_SOT23-3@D2 BAS16_SOT23-3@

1 2

C5 1U_0603_10V4ZC5 1U_0603_10V4Z

1 2

C6 0.1U_0402_16V4ZC6 0.1U_0402_16V4Z

1 2

H_IERR#
H_PROCHOT#

D D

H_A#[3..16]<8>

H_ADSTB#0<8>

H_REQ#0<8>
H_REQ#1<8>
H_REQ#2<8>
H_REQ#3<8>
H_REQ#4<8>

H_A#[17..35]<8>

C C

H_ADSTB#1<8>

H_A20M#<28>

H_FERR#<28>

H_IGNNE#<28>
H_STPCLK#<28>

H_INTR<28>

H_NMI<28>
H_SMI#<28>

B B

RSVD pins on the CPU
should be left as NO
CONNECT

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

AA4
AB2
AA3

D22

W6

W2
W5

W3

J4
L5

L4
K5
M3
N2

J1
N3
P5
P2

L2
P4
P1
R1
M1

K3
H2
K2

J3

L1
Y2

U5
R3

U4
Y5
U1
R4
T5
T3

Y4
U2
V4

V1
A6

A5
C4

D5
C6
B4
A3

M4
N5
T2
V3
B2
D2

D3
F6

CONN@

CONN@

JCPU1A

JCPU1A

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

A20M#
FERR#
IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

Penryn

Penryn

ADDR GROUP_0

ADDR GROUP_0

ADDR GROUP_1

ADDR GROUP_1

THERMAL

THERMAL

ICH

ICH

THERMTRIP#

RESERVED

RESERVED

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

DBR#

XDP/ITP SIGNALS

XDP/ITP SIGNALS

PROCHOT#

THERMDA
THERMDC

H CLK

H CLK

BCLK[0]
BCLK[1]

H_ADS#

H1

H_BNR#

E2

H_BPRI#

G5

H_DEFER#

H5

H_DRDY#

F21

H_DBSY#

E1

H_BR0#

F1

H_IERR#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_TRDY#

G2

H_HIT#

G6

H_HITM#

E4

XDP_BPM#0

AD4

XDP_BPM#1

AD3

XDP_BPM#2

AD1

XDP_BPM#3

AC4

XDP_BPM#4

AC2

XDP_BPM#5

AC1

XDP_TCK

AC5

XDP_TDI

AA6

TDI

XDP_TDO

AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_DBRESET#

C20

H_PROCHOT#

D21

H_THERMDA

A24

H_THERMDC

B25

H_THERMTRIP#

C7

CLK_CPU_BCLK

A22

CLK_CPU_BCLK#

A21

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

H_ADS# <8>
H_BNR# <8>

H_BPRI# <8>
H_DEFER# <8>

H_DRDY# <8>
H_DBSY# <8>

H_BR0# <8>

H_INIT# <28>

H_LOCK# <8>

H_RESET# <8>
H_RS#0 <8>
H_RS#1 <8>
H_RS#2 <8>
H_TRDY# <8>

H_HIT# <8>
H_HITM# <8>

XDP_DBRESET# <29>

H_THERMTRIP# <8,28>

CLK_CPU_BCLK <23>
CLK_CPU_BCLK# <23>

+3VS

FAN1 Conn

EN_FAN1<38>

FAN +5VS DROOP

A A

R1 56_0402_5%R1 56_0402_5%

1 2

R3 56_0402_5%R3 56_0402_5%

1 2

USE->68Ω,NOT USE-->56Ω

+3VS

1

C1

C1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

H_THERMDA

1 2

C2 2200P_0402_50V7KC2 2200P_0402_50V7K

1 2

R10 10K_0402_5%R10 10K_0402_5%

H_THERMDC
THERM#

2nd Source: ADT7421ARMZ (SA00001UN00)

+VCC_FAN1

EN_FAN1

+VCC_FAN1

R11 100_0402_5%R11 100_0402_5%

1 2

1

2

FAN_SPEED1<38>

1000P_0402_50V7K

1000P_0402_50V7K

U1

U1

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

EMC1402-1-ACZL-TR_MSOP8

Address:100_1100

+5VS

C3 10U_0805_10V4ZC3 10U_0805_10V4Z

1
2
3
4

C4

C4
2200P_0402_50V7K

2200P_0402_50V7K

R12

R12

10K_0402_5%

10K_0402_5%

+3VS

C7

C7

+3VS

+VCCP

EC_SMB_CK2 <16,38,42>

EC_SMB_DA2 <16,38,42>

JP1

JP1

1

1

2

2

3

3

4

GND

5

GND

E&T_3801-F03N-01RME@

E&T_3801-F03N-01RME@

Security Classification

Security Classification

Security Classification

2008/03/25 2008/04/

2008/03/25 2008/04/

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/25 2008/04/

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics,Ltd.

Compal Electronics,Ltd.

Compal Electronics,Ltd.

Title

Title

Title

Penryn(1/3)

Penryn(1/3)

Penryn(1/3)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

KIWB1/B2_LA4602P

KIWB1/B2_LA4602P

KIWB1/B2_LA4602P

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

5 53Wednesday, March 18, 2009

5 53Wednesday, March 18, 2009

5 53Wednesday, March 18, 2009

1

0.1

0.1

0.1

5

4

3

2

1

+CPU_CORE +CPU_CORE

CONN@

CONN@

JCPU1B

D D

C C

H_D#[0..15]<8>

H_DSTBN#0<8>
H_DSTBP#0<8>

H_DINV#0<8>

H_D#[16..31]<8>

H_DSTBN#1<8>
H_DSTBP#1<8>

H_DINV#1<8>

R16 1K_0402_5%@R16 1K_0402_5%@

1 2

R18 1K_0402_5%@R18 1K_0402_5%@

1 2

CPU_BSEL1<23>
CPU_BSEL2<23>

T1T1
T2T2
T3T3
T4T4
T5T5

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

+CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

Trace Close CPU < 0.5'

B B

Width=4 mil ,
Spacing: 15mil
(55Ohm)

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24

H22
F26
K22
H23

H26
H25

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

AD26

C23
D25
C24

AF26

AF1
A26

B22
B23
C21

J24
J23

J26

C3

JCPU1B

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]

Penryn

Penryn

DATA GRP 0

DATA GRP 0

MISC

MISC

DATA GRP 1

DATA GRP 1

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#

DATA GRP 2DATA GRP 3

DATA GRP 2DATA GRP 3

D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

COMP0
COMP1
COMP2
COMP3

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

R15 27.4_0402_1%R15 27.4_0402_1%

1 2

R17 54.9_0402_1%R17 54.9_0402_1%

1 2

R19 27.4_0402_1%R19 27.4_0402_1%

1 2

R20 54.9_0402_1%R20 54.9_0402_1%

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

1 2

H_D#[32..47] <8>

H_DSTBN#2 <8>
H_DSTBP#2 <8>
H_DINV#2 <8>

H_D#[48..63] <8>

H_DSTBN#3 <8>
H_DSTBP#3 <8>
H_DINV#3 <8>

H_DPRSTP# <8,28,50>
H_DPSLP# <28>
H_DPWR# <8>
H_PWRGOOD <28>CPU_BSEL0<23>
H_CPUSLP# <8>

H_PSI# <50>

TRACE CLOSELY CPU < 0.5'

COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms)
COMP1, COMP3 layout : Width 5mils and Space 25mils (55Ohms)

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

+VCCP

12

R21

R21
1K_0402_1%

1K_0402_1%

Layout note: Z0=55 ohm

0.5" max for GTLREF.

A A

+CPU_GTLREF

12

R24

R24
2K_0402_1%

2K_0402_1%

FSB

BCLK BSEL2 BSEL1 BSEL0
533
667
800

133

166

200

0 0 1

1 00

1067 266 0 0 0

110

Close to CPU pin AD26
within 500mils.

5

4

Security Classification

Security Classification

Security Classification

2007/10/15 2008/10/15

2007/10/15 2008/10/15

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

CONN@

CONN@

JCPU1C

JCPU1C

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AC10
AB10
AB12
AB14
AB15
AB17
AB18

A10
A12
A13
A15
A17
A18
A20

B10
B12
B14
B15
B17
B18
B20

C10
C12
C13
C15
C17
C18

D10
D12
D14
D15
D17
D18

E10
E12
E13
E15
E17
E18
E20

F10
F12
F14
F15
F17
F18
F20
AA7
AA9

AB9

A7

VCC[001]

A9

VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]

B7

VCC[010]

B9

VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]

C9

VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]

D9

VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]

E7

VCC[033]

E9

VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]

F7

VCC[042]

F9

VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]

VCCSENSE
VCC[065]
VCC[066]
VCC[067]

VSSSENSE

Penryn

Penryn

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

R13 0_0402_5%R13 0_0402_5%

G21

R14 0_0402_5%R14 0_0402_5%

V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

.

.

For testing purpose only

VCCSENSE

VSSSENSE

12
12

Length match within 25 mils.
The trace width/space/other is
18/7/25.

Layout Note:
Route VCCSENSE and VSSSENSE traces at

27.4 Ohms with 50 mil spacing.
Place PU and PD within 1 inch of CPU.
Length matched to within 25 mils.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

+VCCP

Near pin B26

20mils

CPU_VID0 <50>
CPU_VID1 <50>
CPU_VID2 <50>
CPU_VID3 <50>
CPU_VID4 <50>
CPU_VID5 <50>
CPU_VID6 <50>

VCCSENSE <50>

VSSSENSE <50>

+CPU_CORE

1

C8

2

R22

R22
100_0402_1%

100_0402_1%

1 2

R23

R23
100_0402_1%

100_0402_1%

1 2

10U_0805_10V4ZC810U_0805_10V4Z

+1.5VS

1

C9

2

0.01U_0402_16V7KC90.01U_0402_16V7K

VCCSENSE

VSSSENSE

Close to CPU pin
within 500mils.

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Penryn (2/3)

Penryn (2/3)

Penryn (2/3)

KIWB3/B4_LA4551P

KIWB3/B4_LA4551P

KIWB3/B4_LA4551P

6 53Wednesday, March 18, 2009

6 53Wednesday, March 18, 2009

6 53Wednesday, March 18, 2009

1

0.1

0.1

0.1

5

CONN@

CONN@

JCPU1D

JCPU1D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

D D

C C

B B

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Penryn

Penryn

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

.

220U_D2_4VM

220U_D2_4VM

4

+CPU_CORE

10~15 vias for +CPU_CORE

needed to update

1

2

+

+

C10

C10
1200U_PFAF250E128MNTTE_2.5VM

1200U_PFAF250E128MNTTE_2.5VM

3 4

10~15 vias for GND

SGA00003F10 1000uF
be placed under the center of CPU

Middle Frequency Decoupling

+VCCP

C28

C28
22P_0402_50V8J

22P_0402_50V8J

@

@

+VCCP

C48

C48

1

+

+

2

1

C46

C46

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C29

C29
22P_0402_50V8J

22P_0402_50V8J

@

@

1

C47

C47

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C30

C30
22P_0402_50V8J

22P_0402_50V8J

@

@

1

C49

C49

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

3

20080826FOR 3G ISSUE (SED)

C31

C31
22P_0402_50V8J

22P_0402_50V8J

@

@

1

C50

C50

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

+CPU_CORE

1

2

+CPU_CORE

1

2

Reserved

C26

C26
22P_0402_50V8J

22P_0402_50V8J

@

@

1

C51

C51

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C832

C832
10U_0805_6.3V6M

10U_0805_6.3V6M

C818

C818
10U_0805_6.3V6M

10U_0805_6.3V6M

1

2

1

@

@

2

C27

C27
22P_0402_50V8J

22P_0402_50V8J

@

@

1

2

2

C834
10U_0805_6.3V6M

10U_0805_6.3V6M

C831

C831
10U_0805_6.3V6M

10U_0805_6.3V6M

Per PWR team request ,
reserve 12 MLCC for +CPU_CORE

C52

C52

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C664

C664
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C817

C817
10U_0805_6.3V6M

10U_0805_6.3V6M

2

Place these inside socket cavity
on L8 (North side Secondary)

1

@

@

C834

1

2

1

@

@

2

C833

C833
10U_0805_6.3V6M

10U_0805_6.3V6M

C830

C830
10U_0805_6.3V6M

10U_0805_6.3V6M

1

@

@

2

1

2

C644

C644
10U_0805_6.3V6M

10U_0805_6.3V6M

C803

C803
10U_0805_6.3V6M

10U_0805_6.3V6M

1

2

1

@

@

2

C647

C647
10U_0805_6.3V6M

10U_0805_6.3V6M

C804

C804
10U_0805_6.3V6M

10U_0805_6.3V6M

1

A A

Security Classification

Security Classification

Security Classification

2007/10/15 2008/10/15

2007/10/15 2008/10/15

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Penryn (3/3)

Penryn (3/3)

Penryn (3/3)

KIW10/11_LA4142P

KIW10/11_LA4142P

KIW10/11_LA4142P

7 53Wednesday, March 18, 2009

7 53Wednesday, March 18, 2009

7 53Wednesday, March 18, 2009

1

0.1

0.1

0.1

5

U3A

AD14

AA13
AA11

AD11
AD10
AD13
AE12

AE14

AE11

F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9

M11

J1
J2

N12

J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6

P13

N8
L7

N10

M3
Y3

Y6
Y10
Y12
Y14

Y7

W2

AA8

Y9
AA9

AE9
AA2
AD8
AA3
AD3
AD7

AF3
AC1
AE3
AC3

AE8

AG2

AD6

C5

E3

C12
E11

A11
B11

12

U3A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

H_RCOMP H_SWNGH_VREF

R51

R51

24.9_0402_1%

24.9_0402_1%

CANTIGA ES_FCBGA1329GM45@

CANTIGA ES_FCBGA1329GM45@

H_D#[0..63]<6>

D D

C C

H_RESET#<5>
H_CPUSLP#<6>

layout note:
Route H_SCOMP and H_SCOMP# with trace width

spacing and impedance (55 ohm) same as FSB data traces

B B

Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20

12

R42

R42
1K_0402_1%

1K_0402_1%

12

R50

R50
2K_0402_1%

2K_0402_1%

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWNG
H_RCOMP

H_RESET#
H_CPUSLP#

H_VREF

1

C59

C59

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

HOST

HOST

+VCCP+VCCP

H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADSTB#_0
H_ADSTB#_1

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HITM#
H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

12

R43

R43
221_0603_1%

221_0603_1%

12

R52

R52
100_0402_1%

100_0402_1%

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9

H_ADS#

H_BNR#

H_HIT#

within 100 mils from NB

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

J8
L3
Y13
Y1

L10
M7
AA5
AE6

L9
M8
AA6
AE5

B15
K13
F13
B13
B14

B6
F12
C8

1

C60

C60

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

Near B3 pin

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

4

H_A#[3..35] <5>

SMRCOMP_VOH

SMRCOMP_VOL

H_ADS# <5>
H_ADSTB#0 <5>
H_ADSTB#1 <5>
H_BNR# <5>
H_BPRI# <5>
H_BR0# <5>
H_DEFER# <5>
H_DBSY# <5>
CLK_MCH_BCLK <23>
CLK_MCH_BCLK# <23>
H_DPWR# <6>
H_DRDY# <5>
H_HIT# <5>
H_HITM# <5>
H_LOCK# <5>
H_TRDY# <5>

H_DINV#0 <6>
H_DINV#1 <6>
H_DINV#2 <6>
H_DINV#3 <6>

H_DSTBN#0 <6>
H_DSTBN#1 <6>
H_DSTBN#2 <6>
H_DSTBN#3 <6>

H_DSTBP#0 <6>
H_DSTBP#1 <6>
H_DSTBP#2 <6>
H_DSTBP#3 <6>

H_REQ#0 <5>
H_REQ#1 <5>
H_REQ#2 <5>
H_REQ#3 <5>
H_REQ#4 <5>

H_RS#0 <5>
H_RS#1 <5>
H_RS#2 <5>

Layout Note:
V_DDR_MCH_REF trace
width and spacing is 20/20.

+DDR_MCH_REF

+3VS

12

R34

R34
10K_0402_5%

10K_0402_5%

ICH_POK<29,38>

VGATE<29,50>

PLT_RST#<16,27,31,32>

R37 0_0402_5%R37 0_0402_5%
R39 0_0402_5%@R39 0_0402_5%@
R40 100_0402_5%R40 100_0402_5%

1

C61

C61

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1 2
1 2
1 2

1

C53

C53

0.01U_0402_25V7K

0.01U_0402_25V7K

2

1

C55

C55

0.01U_0402_25V7K

0.01U_0402_25V7K

2

12

R35

R35
10K_0402_5%

10K_0402_5%

PM_EXTTS#0
PM_EXTTS#1

+1.5V

12

R45

R45
1K_0402_1%

1K_0402_1%

12

R53

R53
1K_0402_1%

1K_0402_1%

1

C54

C54

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2

1

C56

C56

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2

PM_POK_R

PLT_RST#_R

MCH_CLKSEL0<23>
MCH_CLKSEL1<23>
MCH_CLKSEL2<23>

PM_BMBUSY#<29>

H_DPRSTP#<6,28,50>
PM_EXTTS#0<14,15>
PM_EXTTS#1

H_THERMTRIP#<5,28>

DPRSLPVR<29,50>

+1.5V

12

12

12

CFG5

R28

R28
1K_0402_1%

1K_0402_1%

R25

R25

3.01K_0402_1%

3.01K_0402_1%

R26

R26
1K_0402_1%

1K_0402_1%

3

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

CFG5

T28T28
T29T29
T30T30
T31T31
T32T32
T33T33
T34T34
T35T35
T36T36
T37T37
T38T38
T39T39
T40T40
T41T41
T42T42

PM_BMBUSY#

H_DPRSTP#

PM_EXTTS#0

PM_EXTTS#1

PM_POK_R

PLT_RST#_R

H_THERMTRIP#

DPRSLPVR

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1

SA_ODT_0
SA_ODT_1
SB_ODT_O
SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#

CL_VREF

DDPC_CTRLCLK
SDVO_CTRLCLK

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK
HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

2

M_CLK_DDR0

AP24

M_CLK_DDR1

AT21

M_CLK_DDR2

AV24

M_CLK_DDR3

AU20

M_CLK_DDR#0

AR24

M_CLK_DDR#1

AR21

M_CLK_DDR#2

AU24

M_CLK_DDR#3

AV20

DDR_CKE0_DIMMA

BC28

DDR_CKE1_DIMMA

AY28

DDR_CKE2_DIMMB

AY36

DDR_CKE3_DIMMB

BB36

DDR_CS0_DIMMA#

BA17

DDR_CS1_DIMMA#

AY16

DDR_CS2_DIMMB#

AV16

DDR_CS3_DIMMB#

AR13

M_ODT0

BD17

M_ODT1

AY17

M_ODT2

BF15

M_ODT3

AY13

SMRCOMP

BG22

SMRCOMP#

BH21

SMRCOMP_VOH

BF28

SMRCOMP_VOL

BH28

+DDR_MCH_REF

AV42

SM_PWROK

AR36

SM_REXT

BF17

SM_DRAMRST#

BC36

CLK_MCH_DREFCLK

B38

CLK_MCH_DREFCLK#

A38

MCH_SSCDREFCLK

E41

MCH_SSCDREFCLK#

F41

CLK_MCH_3GPLL

F43

CLK_MCH_3GPLL#

E43

DMI_TXN0

AE41

DMI_TXN1

AE37

DMI_TXN2

AE47

DMI_TXN3

AH39

DMI_TXP0

AE40

DMI_TXP1

AE38

DMI_TXP2

AE48

DMI_TXP3

AH40

DMI_RXN0

AE35

DMI_RXN1

AE43

DMI_RXN2

AE46

DMI_RXN3

AH42

DMI_RXP0

AD35

DMI_RXP1

AE44

DMI_RXP2

AF46

DMI_RXP3

AH43

B33

T43 PADT43 PAD

B32

T44 PADT44 PAD

G33

T45 PADT45 PAD

F33

T46 PADT46 PAD

E33

T47 PADT47 PAD

C34

T48T48

For AMT function

CL_CLK0

AH37

CL_DATA0

AH36
AN36

CL_RST#

AJ35

CL_VREF

AH34

N28
M28

HDMICLK_NB

G36

HDMIDAT_NB

E36

MCH_CLKREQ#

K36

MCH_ICH_SYNC#

H36

B12

MCH_HDA_BCLK

B28

MCH_HDA_RST#

B30

MCH_HDA_SDIN0_R

B29

MCH_HDA_SDOUT

C29

MCH_HDA_SYNC

A28

M_CLK_DDR0 <14>
M_CLK_DDR1 <14>
M_CLK_DDR2 <15>
M_CLK_DDR3 <15>

M_CLK_DDR#0 <14>
M_CLK_DDR#1 <14>
M_CLK_DDR#2 <15>
M_CLK_DDR#3 <15>

DDR_CKE0_DIMMA <14>
DDR_CKE1_DIMMA <14>
DDR_CKE2_DIMMB <15>
DDR_CKE3_DIMMB <15>

DDR_CS0_DIMMA# <14>
DDR_CS1_DIMMA# <14>
DDR_CS2_DIMMB# <15>
DDR_CS3_DIMMB# <15>

M_ODT0 <14>
M_ODT1 <14>
M_ODT2 <15>

20mil

M_ODT3 <15>

1 2

R29 80.6_0402_1%R29 80.6_0402_1%

R30 0_0402_5%R30 0_0402_5%

1 2

R31 12K_0402_5%@R31 12K_0402_5%@

1 2

R32 10K_0402_5%@R32 10K_0402_5%@

1 2

R33 499_0402_1%R33 499_0402_1%

SM_DRAMRST# <14,15>

DDR3

CLK_MCH_DREFCLK <23>
CLK_MCH_DREFCLK# <23>
MCH_SSCDREFCLK <23>
MCH_SSCDREFCLK# <23>

CLK_MCH_3GPLL <23>
CLK_MCH_3GPLL# <23>

DMI_TXN0 <29>
DMI_TXN1 <29>
DMI_TXN2 <29>
DMI_TXN3 <29>

DMI_TXP0 <29>
DMI_TXP1 <29>
DMI_TXP2 <29>
DMI_TXP3 <29>

DMI_RXN0 <29>
DMI_RXN1 <29>
DMI_RXN2 <29>
DMI_RXN3 <29>

DMI_RXP0 <29>
DMI_RXP1 <29>
DMI_RXP2 <29>
DMI_RXP3 <29>

1 2

connect to power CPU_CORE

CL_CLK0 <29>
CL_DATA0 <29>

M_PWROK <29>
CL_RST# <29>

T49T49
T50T50

R41 56_0402_5%R41 56_0402_5%

1 2

R44 0_0402_5%GM@R44 0_0402_5%GM@
R46 0_0402_5%GM@R46 0_0402_5%GM@
R47 33_0402_5%GM@R47 33_0402_5%GM@
R48 0_0402_5%GM@R48 0_0402_5%GM@
R49 0_0402_5%GM@R49 0_0402_5%GM@

Notice: Please check HDA power rail to select HDA controller.

1 2
1 2
1 2
1 2
1 2

HDMICLK_NB <24>
HDMIDAT_NB <24>
MCH_CLKREQ# <23>
MCH_ICH_SYNC# <29>
TSATN# <38>

+VCCP

U3B

CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

AH10
AH12
AH13

AL34
AK34
AN35

AM35

AY21

BG23
BF23
BH18
BF18

AT40
AT11

BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43

M36
N36
R33
T33
AH9

K12

T24

B31

B2
M1

T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28

R29

B7
N33
P32

T20
R32

BH6
BH5

BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1

F1
A47

U3B

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

RSVD15
RSVD16
RSVD17

RSVD20

RSVD22
RSVD23
RSVD24
RSVD25

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26

CANTIGA ES_FCBGA1329GM45@

CANTIGA ES_FCBGA1329GM45@

RSVD CFG PM NC

RSVD CFG PM NC

SM_RCOMP_VOH
SM_RCOMP_VOL

DDR CLK/ CONTROL/ COMPENSATIONHDA

DDR CLK/ CONTROL/ COMPENSATIONHDA

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLKDMIGRAPHICS VIDMEMISC

CLKDMIGRAPHICS VIDMEMISC

DDPC_CTRLDATA
SDVO_CTRLDATA

T6T6
T7T7
T8T8
T9T9
T10T10
T11T11
T12T12
T13T13
T14T14
T15T15
T16T16
T17T17
T18T18
T19T19

T20T20
T26T26
T21T21

T22T22

T23T23
T24T24
T25T25
T27T27

1

+1.5V

12

R27

R27

80.6_0402_1%

80.6_0402_1%

For Crestline: 20ohm
For Calero: 80.6ohm
For Cantiga: 80.6ohm

MCH_HDA_BCLK

+VCCP

12

1

C58

C58

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

HDA_BITCLK_CODEC <28,36>
HDA_RST_CODEC# <28,36>
HDA_SDIN0 <28>
HDA_SDOUT_CODEC <28,36>
HDA_SYNC_CODEC <28,36>

1.5V_PGOOD <48>
DDR3_SM_PWROK

1

@

@

C57

C57
10P_0402_50V8J

10P_0402_50V8J

2

R36

R36
1K_0402_1%

1K_0402_1%

R38

R38
499_0402_1%

499_0402_1%

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

3

2007/10/15 2008/10/15

2007/10/15 2008/10/15

2007/10/15 2008/10/15

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cantiga GMCH(1/6)-GTL

Cantiga GMCH(1/6)-GTL

Cantiga GMCH(1/6)-GTL

KIWB3/B4_LA4551P

KIWB3/B4_LA4551P

KIWB3/B4_LA4551P

1

8 53Wednesday, March 18, 2009

8 53Wednesday, March 18, 2009

8 53Wednesday, March 18, 2009

0.1

0.1

0.1

5

D D

4

3

2

1

U3D

DDR_A_D[0..63]<14>

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33 DDR_A_DQS#0
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AJ38
AJ41

AN38

AM38

AJ36

AJ40
AM44
AM42

AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36

AW36

BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12

BB9
BA9

AU10

AV9

BA11

BD9
AY8
BA6
AV5
AV7

AT9
AN8
AU5
AU6

AT5

AN10

AM11

AM5

AJ9

AJ8

AN12

AM13

AJ11
AJ12

U3D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#

SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

CANTIGA ES_FCBGA1329GM45@

CANTIGA ES_FCBGA1329GM45@

BG18
AT25

BB20
BD20
AY20

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7

AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

DDR_A_BS1
DDR_A_BS2

DDR_A_RAS#
DDR_A_CAS#
DDR_A_W E#

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#1

DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11

DDR_A_MA12

DDR_A_MA13

DDR_A_MA14

DDR_A_BS0

BD21

DDR_A_BS[0..2] <14>

DDR_A_RAS# <14>
DDR_A_CAS# <14>
DDR_A_W E# <14>

DDR_A_DM[0..7] <14>

DDR_A_DQS[0..7] <14>

DDR_A_DQS#[0..7] <14>

DDR_A_MA[0..14] <14>

DDR_B_D[0..63]<15>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AK47
AH46
AP47
AP46

AJ46

AJ48
AM48
AP48
AU47
AU46
BA48
AY48

AT47
AR47
BA47
BC47
BC46
BC44
BG43

BF43
BE45
BC41

BF40

BF41
BG38

BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11

BG8

BH12

BF11

BF8
BG7
BC5
BC6
AY3
AY1

BF6

BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1

AL1

AL2

AJ1
AH1
AM2
AM3
AH3

AJ3

U3E

U3E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

DDR_B_BS0

BC16

SB_BS_0
SB_BS_1
SB_BS_2

SB_RAS#
SB_CAS#

SB_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

CANTIGA ES_FCBGA1329GM45@

CANTIGA ES_FCBGA1329GM45@

BB17
BB33

AU17
BG16
BF14

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6

AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

DDR_B_BS1
DDR_B_BS2

DDR_B_RAS#
DDR_B_CAS#
DDR_B_W E#

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

DDR_B_BS[0..2] <15>

DDR_B_RAS# <15>
DDR_B_CAS# <15>
DDR_B_W E# <15>

DDR_B_DM[0..7] <15>

DDR_B_DQS[0..7] <15>

DDR_B_DQS#[0..7] <15>

DDR_B_MA[0..14] <15>

A A

Security Classification

Security Classification

Security Classification

2007/10/15 2008/10/15

2007/10/15 2008/10/15

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga GMCH (2/6)-DDRII

Cantiga GMCH (2/6)-DDRII

Cantiga GMCH (2/6)-DDRII

KIWB3/B4_LA4551P

KIWB3/B4_LA4551P

KIWB3/B4_LA4551P

9 53Wednesday, March 18, 2009

9 53Wednesday, March 18, 2009

9 53Wednesday, March 18, 2009

1

0.1

0.1

0.1

5

+3VS

4

3

PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15] <16>
PCIE_MTX_C_GRX_P[0..15] <16>

PCIE_GTX_C_MRX_N[0..15] <16>
PCIE_GTX_C_MRX_P[0..15] <16>

2

1

Strap Pin Table

1 2

R54 2.2K_0402_5%

R54 2.2K_0402_5%

D D

1 2

R55 2.2K_0402_5%

R55 2.2K_0402_5%

For Cantiga:2.37kohm
For Crestline:2.4kohm
For Calero: 1.5Kohm

Note: All LVDS data
signals/and it's compliments
should be routed
Differentially

C C

B B

GMCH_CRT_HSYNC<26>

GMCH_CRT_VSYNC<26>

change R64,R65 from 33ohm to 30ohm
by checklist2.0 & CRB1.0 05/08/08

A A

LVDS_SCL
LVDS_SDA

GMCH_ENBKL<25>

+3VS

LVDS_SCL<25>
LVDS_SDA<25>
GM_ENVDD<25>

LVDS_ACLK#<25>
LVDS_ACLK<25>
LVDS_BCLK#<25>
LVDS_BCLK<25>

LVDS_A0#<25>
LVDS_A1#<25>
LVDS_A2#<25>

R60 75_0402_5%GM@R60 75_0402_5%GM@
R61 75_0402_5%GM@R61 75_0402_5%GM@
R62 75_0402_5%GM@R62 75_0402_5%GM@

GMCH_ENBKL

R56 10K_0402_5%R56 10K_0402_5%

1 2

R57 10K_0402_5%R57 10K_0402_5%

1 2

LVDS_SCL
LVDS_SDA
GM_ENVDD

1 2

R58 2.37K_0402_1%R58 2.37K_0402_1%

LVDS_A0<25>
LVDS_A1<25>
LVDS_A2<25>

LVDS_B0#<25>
LVDS_B1#<25>
LVDS_B2#<25>

LVDS_B0<25>
LVDS_B1<25>
LVDS_B2<25>

1 2
1 2
1 2

LVDS_ACLK#
LVDS_ACLK
LVDS_BCLK#
LVDS_BCLK

LVDS_A0#
LVDS_A1#
LVDS_A2#

LVDS_A0
LVDS_A1
LVDS_A2

LVDS_B0#
LVDS_B1#
LVDS_B2#

LVDS_B0
LVDS_B1
LVDS_B2

Layout Note: Place 150 Ω termination
resistors close to GMCH

R63 150_0402_1%GM@R63 150_0402_1%GM@

1 2

R64 150_0402_1%GM@R64 150_0402_1%GM@

1 2

R65 150_0402_1%GM@R65 150_0402_1%GM@

1 2

GMCH_CRT_B<26>
GMCH_CRT_G<26>
GMCH_CRT_R<26>

GMCH_CRT_CLK<26>
GMCH_CRT_DATA<26>

R66

R66

R67 30_0402_1%GM@R67 30_0402_1%GM@

5

30_0402_1%GM@

30_0402_1%GM@

GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B

@

@

R68

R68
0_0402_5%

0_0402_5%

GMCH_CRT_CLK
GMCH_CRT_DATA

Place the resistor within 500mils
(1.27mm)of the (G)MCH

U3C

U3C

L32

T51T51

T52T52

T53T53

T54T54

T55T55

TVA_DAC PCIE_MTX_GRX_N2
TVB_DAC
TVC_DAC

GMCH_CRT_B
GMCH_CRT_G
GMCH_CRT_R

20mil

@

@

R69

R69
0_0402_5%

0_0402_5%

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

12

R70

R70

1.02K_0402_1%

1.02K_0402_1%

For Cantiga:1.02kohm
For Crestline:1.3kohm
For Calero: 255ohm

CANTIGA ES_FCBGA1329GM45@

CANTIGA ES_FCBGA1329GM45@

4

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9

LVDS TV VGA

LVDS TV VGA

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PEGCOMP trace width
and spacing is 20/25 mils.

T37

PEGCOMP

T36

PCIE_GTX_C_MRX_N0

H44

PCIE_GTX_C_MRX_N1

J46

PCIE_GTX_C_MRX_N2

L44

PCIE_GTX_C_MRX_N3

L40

PCIE_GTX_C_MRX_N4

N41

PCIE_GTX_C_MRX_N5

P48

PCIE_GTX_C_MRX_N6

N44

PCIE_GTX_C_MRX_N7

T43

PCIE_GTX_C_MRX_N8

U43

PCIE_GTX_C_MRX_N9

Y43

PCIE_GTX_C_MRX_N10

Y48

PCIE_GTX_C_MRX_N11

Y36

PCIE_GTX_C_MRX_N12

AA43

PCIE_GTX_C_MRX_N13

AD37

PCIE_GTX_C_MRX_N14

AC47

PCIE_GTX_C_MRX_N15

AD39

PCIE_GTX_C_MRX_P0

H43

PCIE_GTX_C_MRX_P1

J44

PCIE_GTX_C_MRX_P2

L43

PCIE_GTX_C_MRX_P3

L41

PCIE_GTX_C_MRX_P4

N40

PCIE_GTX_C_MRX_P5

P47

PCIE_GTX_C_MRX_P6

N43

PCIE_GTX_C_MRX_P7

T42

PCIE_GTX_C_MRX_P8

U42

PCIE_GTX_C_MRX_P9

Y42

PCIE_GTX_C_MRX_P10

W47

PCIE_GTX_C_MRX_P11

Y37

PCIE_GTX_C_MRX_P12

AA42

PCIE_GTX_C_MRX_P13

AD36

PCIE_GTX_C_MRX_P14

AC48

PCIE_GTX_C_MRX_P15

AD40

PCIE_MTX_GRX_N0

J41

PCIE_MTX_GRX_N1

M46
M47

PCIE_MTX_GRX_N3

M40

PCIE_MTX_GRX_N4

M42

PCIE_MTX_GRX_N5

R48

PCIE_MTX_GRX_N6

N38

PCIE_MTX_GRX_N7

T40

PCIE_MTX_GRX_N8

U37

PCIE_MTX_GRX_N9

U40

PCIE_MTX_GRX_N10

Y40

PCIE_MTX_GRX_N11

AA46

PCIE_MTX_GRX_N12

AA37

PCIE_MTX_GRX_N13

AA40

PCIE_MTX_GRX_N14

AD43

PCIE_MTX_GRX_N15

AC46

PCIE_MTX_GRX_P0

J42

PCIE_MTX_GRX_P1

L46

PCIE_MTX_GRX_P2

M48

PCIE_MTX_GRX_P3

M39

PCIE_MTX_GRX_P4

M43

PCIE_MTX_GRX_P5

R47

PCIE_MTX_GRX_P6

N37

PCIE_MTX_GRX_P7

T39

PCIE_MTX_GRX_P8

U36

PCIE_MTX_GRX_P9

U39

PCIE_MTX_GRX_P10

Y39

PCIE_MTX_GRX_P11

Y46

PCIE_MTX_GRX_P12

AA36

PCIE_MTX_GRX_P13

AA39

PCIE_MTX_GRX_P14

AD42

PCIE_MTX_GRX_P15

AD46

PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0

PCIE_GTX_C_MRX_P3

CFG[2:0] FSB Freq select

CFG[4:3]
CFG5 (DMI select)

CFG6

CFG7 (Intel Management
Engine Crypto strap)
CFG8

CFG9
(PCIE Graphics Lane Reversal)

R59 49.9_0402_1%R59 49.9_0402_1%

1 2

Please check Power
source if want
support IAMT

+VCC_PEG

CFG10 (PCIE Lookback enable)

CFG11
CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

CLOSE TO MCH

C62 0.1U_0402_10V7KPM@C62 0.1U_0402_10V7KPM@

1 2

C63 0.1U_0402_10V7KPM@C63 0.1U_0402_10V7KPM@

1 2

C64 0.1U_0402_10V7KPM@C64 0.1U_0402_10V7KPM@

1 2

C65 0.1U_0402_10V7KPM@C65 0.1U_0402_10V7KPM@

1 2

C66 0.1U_0402_10V7KPM@C66 0.1U_0402_10V7KPM@

1 2

C67 0.1U_0402_10V7KPM@C67 0.1U_0402_10V7KPM@

1 2

C68 0.1U_0402_10V7KPM@C68 0.1U_0402_10V7KPM@

1 2

C69 0.1U_0402_10V7KPM@C69 0.1U_0402_10V7KPM@

1 2

C70 0.1U_0402_10V7KPM@C70 0.1U_0402_10V7KPM@

1 2

C71 0.1U_0402_10V7KPM@C71 0.1U_0402_10V7KPM@

1 2

C72 0.1U_0402_10V7KPM@C72 0.1U_0402_10V7KPM@

1 2

C73 0.1U_0402_10V7KPM@C73 0.1U_0402_10V7KPM@

1 2

C74 0.1U_0402_10V7KPM@C74 0.1U_0402_10V7KPM@

1 2

C75 0.1U_0402_10V7KPM@C75 0.1U_0402_10V7KPM@

1 2

C76 0.1U_0402_10V7KPM@C76 0.1U_0402_10V7KPM@

1 2

C77 0.1U_0402_10V7KPM@C77 0.1U_0402_10V7KPM@

1 2

C78 0.1U_0402_10V7KPM@C78 0.1U_0402_10V7KPM@

1 2

C79 0.1U_0402_10V7KPM@C79 0.1U_0402_10V7KPM@

1 2

C80 0.1U_0402_10V7KPM@C80 0.1U_0402_10V7KPM@

1 2

C81 0.1U_0402_10V7KPM@C81 0.1U_0402_10V7KPM@

1 2

C82 0.1U_0402_10V7KPM@C82 0.1U_0402_10V7KPM@

1 2

C83 0.1U_0402_10V7KPM@C83 0.1U_0402_10V7KPM@

1 2

C84 0.1U_0402_10V7KPM@C84 0.1U_0402_10V7KPM@

1 2

C85 0.1U_0402_10V7KPM@C85 0.1U_0402_10V7KPM@

1 2

C86 0.1U_0402_10V7KPM@C86 0.1U_0402_10V7KPM@

1 2

C87 0.1U_0402_10V7KPM@C87 0.1U_0402_10V7KPM@

1 2

C88 0.1U_0402_10V7KPM@C88 0.1U_0402_10V7KPM@

1 2

C89 0.1U_0402_10V7KPM@C89 0.1U_0402_10V7KPM@

1 2

C90 0.1U_0402_10V7KPM@C90 0.1U_0402_10V7KPM@

1 2

C91 0.1U_0402_10V7KPM@C91 0.1U_0402_10V7KPM@

1 2

C92 0.1U_0402_10V7KPM@C92 0.1U_0402_10V7KPM@

1 2

C93 0.1U_0402_10V7KPM@C93 0.1U_0402_10V7KPM@

1 2

C94 0.1U_0402_10V7KGM@C94 0.1U_0402_10V7KGM@

1 2

C95 0.1U_0402_10V7KGM@C95 0.1U_0402_10V7KGM@

1 2

C96 0.1U_0402_10V7KGM@C96 0.1U_0402_10V7KGM@

1 2

C97 0.1U_0402_10V7KGM@C97 0.1U_0402_10V7KGM@

1 2

C98 0.1U_0402_10V7KGM@C98 0.1U_0402_10V7KGM@

1 2

C99 0.1U_0402_10V7KGM@C99 0.1U_0402_10V7KGM@

1 2

C100 0.1U_0402_10V7KGM@C100 0.1U_0402_10V7KGM@

1 2

C101 0.1U_0402_10V7KGM@C101 0.1U_0402_10V7KGM@

1 2

R71 0_0402_5%GM@R71 0_0402_5%GM@

1 2

Compal Secret Data

Compal Secret Data

2008/03/25 2008/04/

2008/03/25 2008/04/

2008/03/25 2008/04/

3

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15

TMDS_B_CLK <24>
TMDS_B_CLK# <24>
TMDS_B_DATA0 <24>
TMDS_B_DATA0# <24>
TMDS_B_DATA1 <24>
TMDS_B_DATA1# <24>
TMDS_B_DATA2 <24>
TMDS_B_DATA2# <24>

TMDS_B_HPD# <24>

2

000 = FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved

Reserved
0 = DMI x 2

1 = DMI x 4
0 = The iTPM Host Interface is enable

1 = The iTPM Host Interface is disable
0 =(TLS)chiper suite with no confidentiality

1 =(TLS)chiper suite with confidentiality

*

*

Reserved
0 = Reverse Lane,15->0, 14->1

1 = Normal Operation,Lane Number in order
0 = Enable

1 = Disable
Reserved
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled

ReservedCFG[15:14]
0 = Disabled

1 = Enabled
ReservedCFG[18:17]
0 = Normal Operation

(Lane number in Order)
1 = Reverse Lane

0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO are operating simu.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom
Date: Sheet of

Date: Sheet of

Date: Sheet of

*

(Default)11 = Normal Operation

*

*

*

Compal Electronics,Ltd.

Compal Electronics,Ltd.

Compal Electronics,Ltd.

Cantiga(3/6)-VGA/LVDS/TV

Cantiga(3/6)-VGA/LVDS/TV

Cantiga(3/6)-VGA/LVDS/TV
KIWB3/B4_LA4551P

KIWB3/B4_LA4551P

KIWB3/B4_LA4551P

1

*

*

10 53Wednesday, March 18, 2009

10 53Wednesday, March 18, 2009

10 53Wednesday, March 18, 2009

0.1

0.1

0.1

5

0.1U_0402_16V4Z

0.1U_0402_16V4Z

GM@

GM@

+3VS_DAC_BG

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C110

C110

GM@

GM@

2

GM@

GM@

R85

R85

1 2

0.022U_0402_16V7K

0.022U_0402_16V7K

+3VS_DAC_CRT

1

1

C102

C102

2

2

0.022U_0402_16V7K

0.022U_0402_16V7K

1

C111

C111

2

+VCCP

+3VS_TVDAC

1

C144

C144

2

GM@

GM@

0.022U_0402_16V7K

0.022U_0402_16V7K

C103

C103

GM@

GM@

22U_0805_6.3VA

22U_0805_6.3VA

10U_0805_10V4Z

10U_0805_10V4Z

GM@

GM@

C112

C112

1

2

C110

C110

0_0402_5%

0_0402_5%

PM@

PM@

220U_D2_4VY_R15M

220U_D2_4VY_R15M

1

C145

C145

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

GM@

GM@

1

C838

C838

@

@

2

GM@

GM@

+1.5VS_PEG_BG: 0.414mA
(0.1UF*1)

1

+

+

C132

C132

2

VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1)

VCCA_DAC_BG: 2.68mA (0.1UF*1, 0.01UF*1)

+1.5VS_PEG_BG

R78

R78

12

0_0603_5%

0_0603_5%

C129

C129

C133

C133

1

2

12

1

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

+1.05VS_A_SM_CK

1U_0402_6.3V4Z

1U_0402_6.3V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1

C134

C134

2

C130

C130

+1.5VS

R81

R81

1 2

0_0805_5%

0_0805_5%

10U_0805_10V4Z

10U_0805_10V4Z

R82

R82

0_0603_5%

0_0603_5%

+3VS

R72

R72

1 2

0_0603_5%

0_0603_5%

GM@

GM@

+3VS

D D

C C

B B

R74

R74

1 2

0_0603_5%

0_0603_5%

GM@

GM@

C102

C102

0_0402_5%

0_0402_5%

PM@

PM@ R79

VCCA_SM:720mA
(22UF*2, 4.7UF*1, 1UF*1)

VCCA_SM_CK: 220mA
(22UF*1, 2.2UF*1, 0.1UF*1)

+3VS

0_0603_5%

0_0603_5%

C144

C144

0_0402_5%

0_0402_5%

PM@

PM@

4

+3VS_DAC_CRT

+3VS_DAC_BG

+1.05VS_DPLLA
+1.05VS_DPLLB

+1.05VS_HPLL
+1.05VS_MPLL

+1.8V_TXLVDS

1000P_0402_50V7K

1000P_0402_50V7K

1

C122

C122

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C137

C137

1

2

+3VS_TVDAC: 40mA
(0.1UF*1, 0.01UF*1 for
each DAC)

VCC_HDA: 50mA
(0.1UF*1)

+1.05VS_PEGPLL

+1.05VS_A_SM

1

1U_0603_10V4Z

1U_0603_10V4Z

2

1U_0603_10V4Z

1U_0603_10V4Z

C138

C138

+3VS_TVDAC

1

C120

C120

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

+1.5VS_TVDAC
+1.5VS_QDAC

+1.05VS_HPLL

+1.05VS_PEGPLL

+1.8V_LVDS

+1.5VS

20 mils

1

C131

C131

2

U3H

U3H

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

AD48

VCCA_PEG_BG

AA48

VCCA_PEG_PLL

AR20

VCCA_SM_1

AP20

VCCA_SM_2

AN20

VCCA_SM_3

AR17

VCCA_SM_4

AP17

VCCA_SM_5

AN17

VCCA_SM_6

AT16

VCCA_SM_7

AR16

VCCA_SM_8

AP16

VCCA_SM_9

AP28

VCCA_SM_CK_1

AN28

VCCA_SM_CK_2

AP25

VCCA_SM_CK_3

AN25

VCCA_SM_CK_4

AN24

VCCA_SM_CK_5

AM28

VCCA_SM_CK_NCTF_1

AM26

VCCA_SM_CK_NCTF_2

AM25

VCCA_SM_CK_NCTF_3

AL25

VCCA_SM_CK_NCTF_4

AM24

VCCA_SM_CK_NCTF_5

AL24

VCCA_SM_CK_NCTF_6

AM23

VCCA_SM_CK_NCTF_7

AL23

VCCA_SM_CK_NCTF_8

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS_1

L37

VCCD_LVDS_2

POWER

POWER

A SM

A SM

HDA

HDA

LVDS D TV/CRT

LVDS D TV/CRT

U3

U3

CRTPLLA LVDSA PEG

CRTPLLA LVDSA PEG

TV

TV

VTT

VTT

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

AXF

VCC_SM_CK_1

VCC_SM_CK_2

VCC_SM_CK_3

VCC_SM_CK_4

SM CK

SM CK

VCC_TX_LVDS

A CK

A CK

HV

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4

DMI PEG

DMI PEG

VTTLF

VTTLF

CANTIGA ES_FCBGA1329GM45@

CANTIGA ES_FCBGA1329GM45@

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25

VCC_HV_1
VCC_HV_2
VCC_HV_3

VTTLF1
VTTLF2
VTTLF3

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

B22
B21
A21

BF21
BH20
BG20
BF20

K47

C35
B35
A35

V48
U48
V47
U47
U46

AH48
AF48
AH47
AG47

A8
L1
AB2

3

+VCCP

+1.8V_TXLVDS

+VCC_PEG

+VCC_DMI

VCC_DMI: 456mA
(0.1UF*1)

20mils

1

C150

C150

2

220U_D2_4VM

220U_D2_4VM

1

+

+

C104

C104

2

1

C1130.47U_0402_6.3V6K C1130.47U_0402_6.3V6K

2

+V1.05VS_AXF

+1.5V_SM_CK

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

1

C151

C151

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+VCCP

+3VS

+1.05VS_DPLLA

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C106

C106

1

2

GM@

GM@

+1.05VS_DPLLB

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C115

C115

1

2

GM@

GM@

+1.05VS_HPLL

1

C123

C123

2

+1.05VS_MPLL

1

C135

C135

2

+1.05VS_PEGPLL

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C146

C146

1

2

+VCCP_D

D3

@D3

@

2 1

CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

@

@

C105

C105

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C114

C114

2

+3VS_HV

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C142

C142

2

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

1

C152

C152

2

1 2

10U_0805_10V4Z

10U_0805_10V4Z

MCK3225151YZF 1210

MCK3225151YZF 1210

1

C107

C107

2

GM@

GM@

+1.05VS_DPLLA
+1.05VS_DPLLB: 64.8mA
(470UF*1, 0.1UF*1)

R76

R76

1 2

10U_0805_10V4Z

10U_0805_10V4Z

MCK3225151YZF 1210

MCK3225151YZF 1210

1

GM@

GM@

C116

C116

2

GM@

GM@

R79

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

1

C124

C124

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2

R83

R83

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

1

C139

C139

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2

1 2

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

1

C147

C147

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2

R87

@R87

@

10_0402_5%

10_0402_5%

R73

R73

+VCCP

GM@

GM@

+VCCP

+1.05VS_HPLL: 24mA
(4.7UF*1, 0.1UF*1)

12

+VCCP

1.05VS_MPLL: 139.2mA
(22UF*1, 0.1UF*1)

12

+VCCP

+1.5VS_PEG_PLL: 50mA
(0.1UF*1)

L1

L1

R88

R88

12

0_0402_5%

0_0402_5%

12

+VCCP

C140

C140

0_0402_5%

0_0402_5%

PM@

PM@

+3VS_HV

C126

C126

0_0402_5%

0_0402_5%

PM@

PM@

40 mils

1000P_0402_50V7K

1000P_0402_50V7K

GM@

GM@

0316 add

0316 add

+V1.05VS_AXF

10U_0805_10V4Z

10U_0805_10V4Z

+1.5VS_TVDAC

C126

C126

1

C140

C140

2

+VCC_PEG

1

C143

C143

+

+

2

+VCC_DMI

C153

C153

1

2

C108

C108

1

2

0.022U_0402_16V7K

0.022U_0402_16V7K

1

2

+1.8V_TXLVDS

C141

C141

220U_D2_4VM

220U_D2_4VM

C148

C148

1U_0603_10V4Z

1U_0603_10V4Z

C154

C154

+1.5V_SM_CK

C117

C117

1

C127

C127

2

GM@

GM@

GM@

GM@

10U_0805_10V4Z

10U_0805_10V4Z

1

2

10U_0805_10V4Z

10U_0805_10V4Z

1

2

10U_0805_10V4Z

10U_0805_10V4Z

1

2

1U_0603_10V4Z

1U_0603_10V4Z

1

2

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C128

C128

R84

R84

0_0603_5%

0_0603_5%

GM@

GM@

GM@

GM@

C155

C155

1

VCC_AXF: 321.35mA
(10UF*1, 1UF*1)

1 2

R75

R75

0_0603_5%

0_0603_5%

C109

C109

VCC_SM_CK: 119.85mA
(10UF*1, 0.1UF*1)

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z

10U_0805_10V4Z

C118

C118

1

2

10U_0805_10V4Z

10U_0805_10V4Z

1

VCCD_TVDAC: 58.696mA

2

(0.1UF*1, 0.01UF*1)

GM@

GM@

12

+1.8V_TXLVDS: 118.8mA
(22UF*1, 1000PF*1)

+VCCP

R166

R166

12

0_1206_5%

0_1206_5%

R86

R86

0_0805_5%

0_0805_5%

10U_0805_10V4Z

10U_0805_10V4Z

1

2

+VCCP

R77

R77

1 2

0_0805_5%

0_0805_5%

R80

R80

0_0603_5%

0_0603_5%

GM@

GM@

+1.8V

+VCCP

12

+1.5V

+1.5VS

12

PM

PM

PM@

PM@

U3

U3

1

C156

C156

C157

C157

2

VCCD_QDAC: 48.363mA
(0.1UF*1, 0.01UF*1)

R89

R89

0_0603_5%

0_0603_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1

1

C158

C158

GM@

2

GM@

2

5

+1.8V_LVDS

12

+1.5VS

GM@

GM@

10U_0805_10V4Z

10U_0805_10V4Z

1

C159

C159

2

+1.5VS_QDAC

1U_0402_6.3V4Z

1U_0402_6.3V4Z

A A

GM@

GM@

1.8V_LVDS: 60.311111mA
(1UF*1)

R90

R90

0_0603_5%

0_0603_5%

1U_0603_10V4Z

1U_0603_10V4Z

GM@

GM@

C160

C160

1

2

GM@

GM@

12

C160

C160

0_0603_5%

0_0603_5%

PM@

PM@

4

+1.8V

GL40

GL40

GL40@

GL40@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPE RTY OF COMPAL ELE CTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPE RTY OF COMPAL ELE CTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPE RTY OF COMPAL ELE CTRONICS, INC. A ND CONTAINS CONFIDENTIAL
AND TRAD E SECRET INFOR MATION. THIS SHEET MAY NOT BE TRAN SFERED FR OM THE CUSTO DY OF THE COM PETENT DIVISION OF R &D

AND TRAD E SECRET INFOR MATION. THIS SHEET MAY NOT BE TRAN SFERED FR OM THE CUSTO DY OF THE COM PETENT DIVISION OF R &D

AND TRAD E SECRET INFOR MATION. THIS SHEET MAY NOT BE TRAN SFERED FR OM THE CUSTO DY OF THE COM PETENT DIVISION OF R &D
DEPARTMEN T EXCEPT AS AU THORIZED BY COM PAL ELECTRONICS , INC. NEITHER TH IS SHEET NOR T HE INFORMATION IT C ONTAINS

DEPARTMEN T EXCEPT AS AU THORIZED BY COM PAL ELECTRONICS , INC. NEITHER TH IS SHEET NOR T HE INFORMATION IT C ONTAINS

DEPARTMEN T EXCEPT AS AU THORIZED BY COM PAL ELECTRONICS , INC. NEITHER TH IS SHEET NOR T HE INFORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/10/15 2008/10/15

2007/10/15 2008/10/15

2007/10/15 2008/10/15

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Crestline GMCH (4/6)-VCC

Crestline GMCH (4/6)-VCC

Custom

Custom

Custom

Crestline GMCH (4/6)-VCC

KIWB3/B4_LA4551P

KIWB3/B4_LA4551P

KIWB3/B4_LA4551P

11 53Friday, April 17, 2009

11 53Friday, April 17, 2009

1

11 53Friday, April 17, 2009

0.1

0.1

0.1

5

D D

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

C C

B B

A A

0.22U_0402_10V4Z

C170

C170

1

1

C167

C167

2

1

2

2

+VCCP

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C171

C171

C172

C172

1

2

AG34
AC34
AB34
AA34

AM33

AK33

AJ33
AG33
AF33

AE33
AC33
AA33

W33

AH28
AF28
AC28
AA28

AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24

AJ23
AH23
AF23

U3G

U3G

VCC_1
VCC_2
VCC_3
VCC_4

Y34

VCC_5

V34

VCC_6

U34

VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13
VCC_14
VCC_15

Y33

VCC_16
VCC_17

V33

VCC_18

U33

VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34

T32

VCC_35

VCC CORE

VCC CORE

4

POWER

POWER

+VCCP

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

GM@

GM@

C173

C173

1U_0603_10V4Z

1U_0603_10V4Z

VCC NCTF

VCC NCTF

CANTIGA ES_FCBGA1329GM45@

CANTIGA ES_FCBGA1329GM45@

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8

VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

3

1782mA

+1.5V

220U_D2_4VM_R15

220U_D2_4VM_R15

1

C168

C168

+

+

2

GM@

+VCCP +AXG_CORE

1

2

220U_D2_4VM_R15

220U_D2_4VM_R15

GM@

GM@

C174

C174

@

@

J1

J1

112

JUMP_43X118

JUMP_43X118

10U_0805_10V4Z

10U_0805_10V4Z

1

GM@

GM@

+

+

C175

C175

2

1

2

2

GM@

GM@

1

C176

C176

2

10U_0805_10V4Z

10U_0805_10V4Z

C176

C176

0_0805_5%

0_0805_5%

PM@

PM@

10U_0805_10V4Z

10U_0805_10V4Z

C162

C162

1

2

0.01U_0402_16V7K

0.01U_0402_16V7K

C163

C163

2

1

+AXG_CORE

0.1U_0402_16V4Z

0.1U_0402_16V4Z

GM@

GM@

1

C177

C177

2

2

U3F

U3F

AP33

VCC_SM_1

AN33

VCC_SM_2

BH32

VCC_SM_3

BG32

VCC_SM_4

BF32

VCC_SM_5

BD32

VCC_SM_6

BC32

VCC_SM_7

BB32

VCC_SM_8

BA32

VCC_SM_9

AY32

VCC_SM_10

AW32

VCC_SM_11

AV32

VCC_SM_12

AU32

VCC_SM_13

AT32

VCC_SM_14

AR32

VCC_SM_15

AP32

VCC_SM_16

AN32

VCC_SM_17

BH31

VCC_SM_18

BG31

VCC_SM_19

BF31

VCC_SM_20

BG30

VCC_SM_21

BH29

VCC_SM_22

BG29

VCC_SM_23

BF29

VCC_SM_24

BD29

VCC_SM_25

BC29

VCC_SM_26

BB29

VCC_SM_27

BA29

VCC_SM_28

AY29

VCC_SM_29

AW29

VCC_SM_30

AV29

VCC_SM_31

AU29

VCC_SM_32

AT29

VCC_SM_33

AR29

VCC_SM_34

AP29

VCC_SM_35

BA36

VCC_SM_36/NC

BB24

VCC_SM_37/NC

BD16

VCC_SM_38/NC

BB21

VCC_SM_39/NC

AW16

VCC_SM_40/NC

AW13

VCC_SM_41/NC

AT13

VCC_SM_42/NC

Y26

VCC_AXG_1

AE25

VCC_AXG_2

AB25

VCC_AXG_3

AA25

VCC_AXG_4

AE24

VCC_AXG_5

AC24

VCC_AXG_6

AA24

VCC_AXG_7

Y24

VCC_AXG_8

AE23

VCC_AXG_9

AC23

VCC_AXG_10

AB23

VCC_AXG_11

AA23

VCC_AXG_12

AJ21

VCC_AXG_13

AG21

VCC_AXG_14

AE21

VCC_AXG_15

AC21

VCC_AXG_16

AA21

VCC_AXG_17

Y21

VCC_AXG_18

AH20

VCC_AXG_19

AF20

VCC_AXG_20

AE20

VCC_AXG_21

AC20

VCC_AXG_22

AB20

VCC_AXG_23

AA20

VCC_AXG_24

T17

VCC_AXG_25

T16

VCC_AXG_26

AM15

VCC_AXG_27

AL15

VCC_AXG_28

AE15

VCC_AXG_29

AJ15

VCC_AXG_30

AH15

VCC_AXG_31

AG15

VCC_AXG_32

AF15

VCC_AXG_33

AB15

VCC_AXG_34

AA15

VCC_AXG_35

Y15

VCC_AXG_36

V15

VCC_AXG_37

U15

VCC_AXG_38

AN14

VCC_AXG_39

AM14

VCC_AXG_40

U14

VCC_AXG_41

T14

VCC_AXG_42

AJ14

T56T56
T57T57

AH14

VCC_AXG_SENSE
VSS_AXG_SENSE

VCC_AXG_NTCF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC SM

VCC SM

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43

VCC GFX NCTF

VCC GFX NCTF

VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52

POWER

POWER

VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

VCC GFX

VCC GFX

VCC SM LF

VCC SM LF

CANTIGA ES_FCBGA1329GM45@

CANTIGA ES_FCBGA1329GM45@

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

AV44
BA37
AM40
AV21
AY5
AM10
BB13

+AXG_CORE

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

Check : power

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C164

C164

1

GM@

GM@

2

C180 0.1U_0402_16V4ZC180 0.1U_0402_16V4Z

C179 0.1U_0402_16V4ZC179 0.1U_0402_16V4Z

1

1

2

2

1

C165

C165

1

GM@

GM@

2

0.22U_0402_10V4Z

0.22U_0402_10V4Z

C166

C166

0_0603_5%

0_0603_5%

PM@

PM@

C182 0.22U_0402_10V4ZC182 0.22U_0402_10V4Z

C181 0.22U_0402_10V4ZC181 0.22U_0402_10V4Z

1

1

2

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
C166

C166

1

GM@

GM@

2

C184 1U_0402_6.3V4ZC184 1U_0402_6.3V4Z

C183 0.47U_0402_6.3V6KC183 0.47U_0402_6.3V6K

1

1

1

2

2

2

C185 1U_0402_6.3V4ZC185 1U_0402_6.3V4Z

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

2007/10/15 2008/10/15

2007/10/15 2008/10/15

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Crestline GMCH (5/6)-VCC

Crestline GMCH (5/6)-VCC

Crestline GMCH (5/6)-VCC

KIWB3/B4_LA4551P

KIWB3/B4_LA4551P

KIWB3/B4_LA4551P

12 53Wednesday, March 18, 2009

12 53Wednesday, March 18, 2009

12 53Wednesday, March 18, 2009

1

0.1

0.1

0.1

5

U3I

U3I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

VSS_8

AD47

VSS_9

AB47

VSS_10

Y47

VSS_11

T47

BD46
BA46
AY46
AV46
AR46
AM46

BF44
AH44
AD44
AA44

BC43
AV43
AU43
AM43

BG42
AY42
AT42
AN42

AJ42

AE42

BD41
AU41
AM41
AH41
AD41
AA41

BG40
BB40
AV40
AN40

AT39
AM39

AJ39

AE39

BH38
BC38
BA38
AU38
AH38
AD38
AA38

BF37
BB37

AW37

AT37
AN37

AJ37

BG36
BD36
AK15
AU36

N47
G47

V46
R46
P46
H46

U44
M44

C43

N42

U41
M41

G41
B41

H40
E40

N39
B39

U38

C38

H37
C37

VSS_12
VSS_13

L47

VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25

F46

VSS_26
VSS_27
VSS_28
VSS_29
VSS_30

Y44

VSS_31
VSS_32

T44

VSS_33
VSS_34

F44

VSS_35
VSS_36
VSS_37
VSS_38
VSS_39

J43

VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48

L42

VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55

Y41

VSS_56
VSS_57

T41

VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72

L39

VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81

Y38

VSS_82
VSS_83

T38

VSS_84

J38

VSS_85

F38

VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

VSS

VSS

CANTIGA ES_FCBGA1329GM45@

CANTIGA ES_FCBGA1329GM45@

D D

C C

B B

A A

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

4

U3J

U3J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

VSS_230

M17

VSS_231

H17

VSS_232

C17

VSS_233

BA16

VSS_235

AU16

VSS_237

AN16

VSS_238

N16

VSS_239

K16

VSS_240

G16

VSS_241

E16

VSS_242

BG15

VSS_243

AC15

VSS_244

W15

VSS_245

A15

VSS_246

BG14

VSS_247

AA14

VSS_248

C14

VSS_249

BG13

VSS_250

BC13

VSS_251

BA13

VSS_252

AN13

VSS_255

AJ13

VSS_256

AE13

VSS_257

N13

VSS_258

L13

VSS_259

G13

VSS_260

E13

VSS_261

BF12

VSS_262

AV12

VSS_263

AT12

VSS_264

AM12

VSS_265

AA12

VSS_266

J12

VSS_267

A12

VSS_268

BD11

VSS_269

BB11

VSS_270

AY11

VSS_271

AN11

VSS_272

AH11

VSS_273

Y11

VSS_275

N11

VSS_276

G11

VSS_277

C11

VSS_278

BG10

VSS_279

AV10

VSS_280

AT10

VSS_281

AJ10

VSS_282

AE10

VSS_283

AA10

VSS_284

M10

VSS_285

BF9

VSS_286

BC9

VSS_287

AN9

VSS_288

AM9

VSS_289

AD9

VSS_290

G9

VSS_291

B9

VSS_292

BH8

VSS_293

BB8

VSS_294

AV8

VSS_295

AT8

VSS_296

CANTIGA ES_FCBGA1329GM45@

CANTIGA ES_FCBGA1329GM45@

VSS

VSS

3

VSS NCTF

VSS NCTF

VSS SCB

VSS SCB

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350

VSS_351
VSS_352
VSS_353
VSS_354

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5

NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34

NC

NC

NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

U24
U28
U25
U29

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1
A3

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

2

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

2007/10/15 2008/10/15

2007/10/15 2008/10/15

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga GMCH (6/6)-GND

Cantiga GMCH (6/6)-GND

Cantiga GMCH (6/6)-GND

KIWB3/B4_LA4551P

KIWB3/B4_LA4551P

KIWB3/B4_LA4551P

13 53Wednesday, March 18, 2009

13 53Wednesday, March 18, 2009

13 53Wednesday, March 18, 2009

1

0.1

0.1

0.1

5

DDR_A_DQS#[0..7]<9>

DDR_A_D[0..63]<9>

DDR_A_DM[0..7]<9>
DDR_A_DQS[0..7]<9>
DDR_A_MA[0..14]<9>

D D

+1.5V

Layout Note:

C C

Layout Note:
Place near JP2.203 & JP2.204

B B

A A

Place near JP2

+1.5V

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C188

C188

C187

C187

2

1

2

+0.75V

1U_0603_10V4Z

1U_0603_10V4Z

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

C190

C190

C189

C189

2

2

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

2

2

1

2

C201

C201

C200

C200

1

1

5

C14

C14
22P_0402_50V8J

22P_0402_50V8J

@

@

10U_0805_6.3V6M

10U_0805_6.3V6M

C191

C191

1U_0603_10V4Z

1U_0603_10V4Z

2

C202

C202

1

+V_DDR3_DIMM_REF<15>

FOR 3G ISSUE (SED)

C16

C15

C15
22P_0402_50V8J

22P_0402_50V8J

@

@

Layout Note: Place these 4 Caps near Command
and Control signals of DIMMA

0.1U_0402_16V4Z

10U_0805_6.3V6M

10U_0805_6.3V6M

1

2

C203

C203

0.1U_0402_16V4Z

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C192

C192

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C204

C204

2

C16
22P_0402_50V8J

22P_0402_50V8J

@

@

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C194

C194

C193

C193

1

1

2

2

4

+V_DDR3_DIMM_REF

1

C186

C186

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C195

C195

1

1

2

2

4

+1.5V

12

R91

R91
100_0402_1%

100_0402_1%

12

R92

R92

100_0402_1%

100_0402_1%

20080826

C17

C17
22P_0402_50V8J

22P_0402_50V8J

@

@

1

C196

C196

+

+

2

+V_DDR3_DIMM_REF

C18

C18
22P_0402_50V8J

22P_0402_50V8J

@

@

C197

C197
470U_D2_2.5VM_R15

470U_D2_2.5VM_R15

@

@

3

+V_DDR3_DIMM_REF

DDR_A_D0
DDR_A_D1

DDR_A_DM0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_D9
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11
DDR_A_D16

DDR_A_D17
DDR_A_DQS#2

DDR_A_DQS2
DDR_A_D18

DDR_A_D19
DDR_A_D24

1

2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

C206

C206

3

10K_0402_5%

10K_0402_5%

1

2

DDR_A_D25
DDR_A_DM3
DDR_A_D26

DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3

DDR_A_MA1
M_CLK_DDR0

M_CLK_DDR#0
DDR_A_MA10

DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49
DDR_A_DQS#6

DDR_A_DQS6
DDR_A_D50

DDR_A_D51
DDR_A_D56

DDR_A_D57
DDR_A_DM7
DDR_A_D58

DDR_A_D59

R96

R96

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C19

C19
22P_0402_50V8J

22P_0402_50V8J

@

@

DDR_CKE0_DIMMA<8>

DDR_A_BS2<9>

M_CLK_DDR0<8>
M_CLK_DDR#0<8>

DDR_A_BS0<9>

DDR_A_WE#<9>

DDR_A_CAS#<9> M_ODT0 <8>

DDR_CS1_DIMMA#<8>

+3VS

C205

C205

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.5V +1.5V

JP2

JP2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

12

R97

R97

10K_0402_5%

10K_0402_5%

2007/09/29 2007/09/29

2007/09/29 2007/09/29

2007/09/29 2007/09/29

VTT1

205

G1

FOX _AS0A626-U2RN-7F_RV

FOX _AS0A626-U2RN-7F_RV

Compal Secret Data

Compal Secret Data

Compal Secret Data

DQ4
DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1

VDD2

A15
A14

VDD4

A11

A7

VDD6

A6
A4

VDD8

A2
A0

VDD10

CK1
CK1#

VDD12

BA1
RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

SCL

VTT2

G2

Deciphered Date

Deciphered Date

Deciphered Date

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

2

DDR_A_D4
DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

DDR_A_DM1
SM_DRAMRST#

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2
DDR_A_D22

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_BS1

DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
M_ODT1

DDR_VREF_CA_DIMMA
DDR_A_D36

DDR_A_D37
DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53
DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63
PM_EXTTS#0_1

CLK_SMBDATA
CLK_SMBCLK

+0.75V

+0.75V

2

1

SM_DRAMRST# <8,15>

DDR_CKE1_DIMMA <8>

M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>

DDR_A_BS1 <9>
DDR_A_RAS# <9>

DDR_CS0_DIMMA# <8>

M_ODT1 <8>

R95

R95

1 2

0_0402_5%

0_0402_5%

PM_EXTTS#0 <8,15>

CLK_SMBDATA <15,23>
CLK_SMBCLK <15,23>

2.2U_0805_16V4Z

2.2U_0805_16V4Z

1

C198

C198

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

+V_DDR3_DIMM_REF

C199

C199

DDR3 SO-DIMM A
REVERSE

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

DDRIII-SODIMM SLOT1

DDRIII-SODIMM SLOT1

KIWB1/B2_LA4601P

1

1.0

1.0

14 53Monday, April 27, 2009

14 53Monday, April 27, 2009

14 53Monday, April 27, 2009

1.0

5

DDR_B_DQS#[0..7]<9>

DDR_B_D[0..63]<9>

DDR_B_DM[0..7]<9>

DDR_B_DQS[0..7]<9>

DDR_B_MA[0..14]<9>

D D

C C

B B

A A

Layout Note:
Place near JP3

+1.5V

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C208

C208

C207

C207

2

+1.5V

C22

C22
22P_0402_50V8J

22P_0402_50V8J

@

@

Layout Note:
Place near JP3.203 & JP3.204

+0.75V

1U_0603_10V4Z

1U_0603_10V4Z

2

C218

C218

1

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

C210

C210

C209

C209

2

2

FOR 3G ISSUE (SED)

C23

C23
22P_0402_50V8J

22P_0402_50V8J

@

@

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

2

2

C219

C219

C220

C220

1

1

5

1

2

2

1

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

C221

C221

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C211

C211

2

C24

C24
22P_0402_50V8J

22P_0402_50V8J

@

@

1

C222

C222

2

Layout Note: Place these 4 Caps near Command
and Control signals of DIMMA

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C212

C212

10U_0805_6.3V6M

10U_0805_6.3V6M

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C213

C213

1

2

20080826

C25

C25
22P_0402_50V8J

22P_0402_50V8J

@

@

C214

C214

1

2

C20

C20
22P_0402_50V8J

22P_0402_50V8J

@

@

0.1U_0402_16V4Z

1

2

C215

C215

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

4

C216

C216

1

+

+

C217

C217
470U_D2_2.5VM_R15

470U_D2_2.5VM_R15

@

@

2

C21

C21
22P_0402_50V8J

22P_0402_50V8J

@

@

4

3

+1.5V +1.5V

+V_DDR3_DIMM_REF

JP3

+V_DDR3_DIMM_REF<14>

DDR_B_BS2<9>

M_CLK_DDR2<8>
M_CLK_DDR#2<8>

DDR_B_BS0<9>

DDR_B_WE#<9>

DDR_B_CAS#<9> M_ODT2 <8>

DDR_CS3_DIMMB#<8>

+3VS

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

10K_0402_5%

10K_0402_5%

1

C225

C225

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Issued Date

Issued Date

Issued Date

DDR_B_D0
DDR_B_D1

DDR_B_DM0
DDR_B_D2

DDR_B_D3
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D10

DDR_B_D11
DDR_B_D16

DDR_B_D17
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D18

DDR_B_D19
DDR_B_D24

DDR_B_D25
DDR_B_DM3
DDR_B_D26

DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3

DDR_B_MA1
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_MA10

DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_B_MA13

DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49
DDR_B_DQS#6

DDR_B_DQS6
DDR_B_D50

DDR_B_D51
DDR_B_D56

DDR_B_D57
DDR_B_DM7
DDR_B_D58

DDR_B_D59

R99

R99

1 2

1 2

R100

R100

10K_0402_5%

10K_0402_5%

3

JP3

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-UARN-7F _RV

FOX_AS0A626-UARN-7F _RV

2007/09/29 2007/09/29

2007/09/29 2007/09/29

2007/09/29 2007/09/29

2
4

DQ4

6

DQ5

8

VSS3

10

DQS#0

12

DQS0

14

VSS6

16

DQ6

18

DQ7

20

VSS8

22

DQ12

24

DQ13

26

VSS10

28

DM1

30
32
34

DQ14

36

DQ15

38
40

DQ20

42

DQ21

44
46

DM2

48

VSS17

50

DQ22

52

DQ23

54

VSS19

56

DQ28

58

DQ29

60

VSS21

62
64

DQS3

66
68

DQ30

70

DQ31

72

74

CKE1

76

VDD2

78

A15

80

A14

82

VDD4

84

A11

86

A7

88

VDD6

90

A6

92

A4

94

VDD8

96

A2

98

A0

100

VDD10

102

CK1

104

CK1#

106

VDD12

108

BA1

110

RAS#

112

VDD14

114

S0#

116

ODT0

118

VDD16

120

ODT1

122

NC2

124

VDD18

126

VREF_CA

128

VSS28

130

DQ36

132

DQ37

134

VSS30

136

DM4

138

VSS31

140

DQ38

142

DQ39

144

VSS33

146

DQ44

148

DQ45

150

VSS35

152

DQS#5

154

DQS5

156

VSS38

158

DQ46

160

DQ47

162

VSS40

164

DQ52

166

DQ53

168

VSS42

170

DM6

172

VSS43

174

DQ54

176

DQ55

178

VSS45

180

DQ60

182

DQ61

184

VSS47

186

DQS#7

188

DQS7

190

VSS50

192

DQ62

194

DQ63

196

VSS52

198

EVENT#

200

SDA

202

SCL

204

VTT2

206

G2

+0.75V

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DDR_B_D4
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR_B_DM1
SM_DRAMRST#

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA0
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_BS1

DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
M_ODT3

DDR_VREF_CA_DIMMB

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63
PM_EXTTS#0_1

CLK_SMBDATA
CLK_SMBCLK

+0.75V

2

1

SM_DRAMRST# <8,14>

DDR_CKE3_DIMMB <8>DDR_CKE2_DIMMB<8>

M_CLK_DDR3 <8>
M_CLK_DDR#3 <8>

DDR_B_BS1 <9>
DDR_B_RAS# <9>

DDR_CS2_DIMMB# <8>

M_ODT3 <8>

R98

R98

1 2

0_0402_5%

0_0402_5%

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C223

C223

C224

C224

2

2

+V_DDR3_DIMM_REF

same with intel DDR3 CRB connection

PM_EXTTS#0 <8,14>

CLK_SMBDATA <14,23>
CLK_SMBCLK <14,23>

DDR3 SO-DIMM B
REVERSE

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

DDRIII-SODIMM SLOT2

DDRIII-SODIMM SLOT2

KIWB1/B2_LA4601P

15 53Monday, April 27, 2009

15 53Monday, April 27, 2009

15 53Monday, April 27, 2009

1

1.0

1.0

1.0

5

D D

C C

B B

A A

+VCCP +PLLVDD

L508 MBK1608121YZF_0603

4700P_0402_16V7K

4700P_0402_16V7K

20P_0402_50V8

20P_0402_50V8

R1074

R1074

100K_0402_1%

100K_0402_1%

L508 MBK1608121YZF_0603

1 2
PM@

PM@

PM@

PM@

C1158

C1158

L510

PM@L510

PM@

1 2

MBK1608121YZF_0603

MBK1608121YZF_0603

1

PM@

PM@

C1168

C1168

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

A0

2

A1

3

A2

4

GND

12

AT24C16AN-10SU-2.7_SO8

AT24C16AN-10SU-2.7_SO8

PM@

PM@

PM@

PM@

VGA_DDCCLK<26>

VGA_DDCDATA<26>

VGA_LVDS_SCL<25>

VGA_LVDS_SDA<25>

12P_0402_50V8J

12P_0402_50V8J

5

1U_0603_10V4Z

1U_0603_10V4Z

PM@

PM@

C1164

C1164

4
1

27MHZ_16PF_X7T027000BG1H-V

27MHZ_16PF_X7T027000BG1H-V

VCC

WP
SCL
SDA

PM@

PM@

C1155

C1155

1U_0603_10V4Z

1U_0603_10V4Z

PM@

PM@

1

C1159

C1159

0.1U_0402_16V4Z

0.1U_0402_16V4Z

UNDER GPU

2

GND
IN

PM@

PM@

1

PM@

PM@

C1121

C1121

2

U51

U51

8
7
6
5

1

C247

C247

PM@

PM@

2

12P_0402_50V8J

12P_0402_50V8J

1U_0603_10V4Z

1U_0603_10V4Z

PM@

PM@

C1165

C1165

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Y9

Y9

OUT

GND

R1072

R1072

10K_0402_5%

10K_0402_5%

1

C246

C246

PM@

PM@

12P_0402_50V8J

12P_0402_50V8J

2

3
2

2.2K_0402_5%

2.2K_0402_5%

PM@

PM@

C1156

C1156

1

2

@

@

+SP_PLLVDD+VCCP

1

C245

C245

2

PM@

PM@

C1157

C1157

NEAR GPU

1U_0603_10V4Z

1U_0603_10V4Z

4700P_0402_16V7K

4700P_0402_16V7K

PM@

PM@

C1166

C1166

XTALIN

XTALOUT

1

PM@

PM@

C1167

C1167
20P_0402_50V8

20P_0402_50V8

2

12

PM@

PM@

R1071

R1071

2.2K_0402_5%

2.2K_0402_5%

@

@

R1073

R1073

1

PM@

PM@

2

12P_0402_50V8J

12P_0402_50V8J

C244

C244

PM@

PM@

+3VS

PM@

PM@

R1070

R1070

2.2K_0402_5%

2.2K_0402_5%

HDCP_I2CH_SCL
HDCP_I2CH_SDA

PM@

PM@

PM@

PM@
PM@

PM@

PM@

PM@

2.2K_0402_5%

2.2K_0402_5%

+3VS

PCIE_MTX_C_GRX_N[0..15]<10>
PCIE_MTX_C_GRX_P[0..15]<10>

PCIE_GTX_C_MRX_N[0..15]<10>
PCIE_GTX_C_MRX_P[0..15]<10>

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15

L517MBK1608121YZF_0603

L517MBK1608121YZF_0603

12

L518MBK1608121YZF_0603

L518MBK1608121YZF_0603

12

L519MBK1608121YZF_0603

L519MBK1608121YZF_0603

12

L520MBK1608121YZF_0603

L520MBK1608121YZF_0603

12

R110

R110

PM@

PM@

4

PLT_RST#<8,27,31,32>

PULL UP BY EC SIDE

+3VS

VGA_DDCCLK_C

VGA_DDCDATA_C

VGA_LVDS_SCL_C
VGA_LVDS_SDA_C

R109

R109

2.2K_0402_5%

2.2K_0402_5%

PM@

PM@

4

PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]

C226 0.1U_0402_16V7KPM@C226 0.1U_0402_16V7KPM@

1 2

C227 0.1U_0402_16V7KPM@C227 0.1U_0402_16V7KPM@

1 2

C228 0.1U_0402_16V7KPM@C228 0.1U_0402_16V7KPM@

1 2

C230 0.1U_0402_16V7KPM@C230 0.1U_0402_16V7KPM@

1 2

C231 0.1U_0402_16V7KPM@C231 0.1U_0402_16V7KPM@

1 2

C232 0.1U_0402_16V7KPM@C232 0.1U_0402_16V7KPM@

1 2

C233 0.1U_0402_16V7KPM@C233 0.1U_0402_16V7KPM@

1 2

C234 0.1U_0402_16V7KPM@C234 0.1U_0402_16V7KPM@

1 2

C235 0.1U_0402_16V7KPM@C235 0.1U_0402_16V7KPM@

1 2

C236 0.1U_0402_16V7KPM@C236 0.1U_0402_16V7KPM@

1 2

C237 0.1U_0402_16V7KPM@C237 0.1U_0402_16V7KPM@

1 2

C238 0.1U_0402_16V7KPM@C238 0.1U_0402_16V7KPM@

1 2

C239 0.1U_0402_16V7KPM@C239 0.1U_0402_16V7KPM@

1 2

C240 0.1U_0402_16V7KPM@C240 0.1U_0402_16V7KPM@

1 2

C241 0.1U_0402_16V7KPM@C241 0.1U_0402_16V7KPM@

1 2

C242 0.1U_0402_16V7KPM@C242 0.1U_0402_16V7KPM@

1 2

C243 0.1U_0402_16V7KPM@C243 0.1U_0402_16V7KPM@

1 2

C248 0.1U_0402_16V7KPM@C248 0.1U_0402_16V7KPM@

1 2

C249 0.1U_0402_16V7KPM@C249 0.1U_0402_16V7KPM@

1 2

C250 0.1U_0402_16V7KPM@C250 0.1U_0402_16V7KPM@

1 2

C251 0.1U_0402_16V7KPM@C251 0.1U_0402_16V7KPM@

1 2

C252 0.1U_0402_16V7KPM@C252 0.1U_0402_16V7KPM@

1 2

C253 0.1U_0402_16V7KPM@C253 0.1U_0402_16V7KPM@

1 2

C254 0.1U_0402_16V7KPM@C254 0.1U_0402_16V7KPM@

1 2

PM@

PM@

C255 0.1U_0402_16V7K

C255 0.1U_0402_16V7K

1 2

C256 0.1U_0402_16V7K

C256 0.1U_0402_16V7K

PM@

PM@

1 2

C257 0.1U_0402_16V7KPM@C257 0.1U_0402_16V7KPM@

1 2

C258 0.1U_0402_16V7KPM@C258 0.1U_0402_16V7KPM@

1 2

C259 0.1U_0402_16V7KPM@C259 0.1U_0402_16V7KPM@

1 2

C260 0.1U_0402_16V7KPM@C260 0.1U_0402_16V7KPM@

1 2

C262 0.1U_0402_16V7KPM@C262 0.1U_0402_16V7KPM@

1 2

C263 0.1U_0402_16V7KPM@C263 0.1U_0402_16V7KPM@

1 2

+3VS

PLT_RST#

12

R1085

R1085

10K_0402_5%

10K_0402_5%

@

@

R1092 2.2K_0402_5%PM@R1092 2.2K_0402_5%PM@

PM@

PM@

R1091 2.2K_0402_5%

R1091 2.2K_0402_5%

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

PCIE_GTX_MRX_P0
PCIE_GTX_MRX_N0
PCIE_GTX_MRX_P1
PCIE_GTX_MRX_N1
PCIE_GTX_MRX_P2
PCIE_GTX_MRX_N2
PCIE_GTX_MRX_P3
PCIE_GTX_MRX_N3
PCIE_GTX_MRX_P4
PCIE_GTX_MRX_N4
PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N5
PCIE_GTX_MRX_P6
PCIE_GTX_MRX_N6
PCIE_GTX_MRX_P7
PCIE_GTX_MRX_N7
PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N8
PCIE_GTX_MRX_P9
PCIE_GTX_MRX_N9
PCIE_GTX_MRX_P10
PCIE_GTX_MRX_N10
PCIE_GTX_MRX_P11
PCIE_GTX_MRX_N11
PCIE_GTX_MRX_P12
PCIE_GTX_MRX_N12
PCIE_GTX_MRX_P13
PCIE_GTX_MRX_N13
PCIE_GTX_MRX_P14
PCIE_GTX_MRX_N14
PCIE_GTX_MRX_P15
PCIE_GTX_MRX_N15

CLK_PCIE_VGA<23>
CLK_PCIE_VGA#<23>

10K_0402_5% PM@

10K_0402_5% PM@

+PLLVDD

EC_SMB_CK2<5,38,42>
EC_SMB_DA2<5,38,42>

PULL UP BY VGA SIDE

PULL UP BY RGB SIDE

3

U50A

U50A

AP17

PEX_RX0

AN17

PEX_RX0_N

AN19

PEX_RX1

AP19

PEX_RX1_N

AR19

PEX_RX2

AR20

PEX_RX2_N

AP20

PEX_RX3

AN20

PEX_RX3_N

AN22

PEX_RX4

AP22

PEX_RX4_N

AR22

PEX_RX5

AR23

PEX_RX5_N

AP23

PEX_RX6

AN23

PEX_RX6_N

AN25

PEX_RX7

AP25

PEX_RX7_N

AR25

PEX_RX8

AR26

PEX_RX8_N

AP26

PEX_RX9

AN26

PEX_RX9_N

AN28

PEX_RX10

AP28

PEX_RX10_N

AR28

PEX_RX11

AR29

PEX_RX11_N

AP29

PEX_RX12

AN29

PEX_RX12_N

AN31

PEX_RX13

AP31

PEX_RX13_N

AR31

PEX_RX14

AR32

PEX_RX14_N

AR34

PEX_RX15

AP34

PEX_RX15_N

AL17

PEX_TX0

AM17

PEX_TX0_N

AM18

PEX_TX1

AM19

PEX_TX1_N

AL19

PEX_TX2

AK19

PEX_TX2_N

AL20

PEX_TX3

AM20

PEX_TX3_N

AM21

PEX_TX4

AM22

PEX_TX4_N

AL22

PEX_TX5

AK22

PEX_TX5_N

AL23

PEX_TX6

AM23

PEX_TX6_N

AM24

PEX_TX7

AM25

PEX_TX7_N

AL25

PEX_TX8

AK25

PEX_TX8_N

AL26

PEX_TX9

AM26

PEX_TX9_N

AM27

PEX_TX10

AM28

PEX_TX10_N

AL28

PEX_TX11

AK28

PEX_TX11_N

AK29

PEX_TX12

AL29

PEX_TX12_N

AM29

PEX_TX13

AM30

PEX_TX13_N

AM31

PEX_TX14

AM32

PEX_TX14_N

AN32

PEX_TX15

AP32

PEX_TX15_N

AR16

PEX_REFCLK

AR17

PEX_REFCLK_N

R1079

R1079

12

EC_SMB_CK2
EC_SMB_DA2

AR13

PEX_CLKREQ_N

AJ17

PEX_TSTCLK_OUT

AJ18

PEX_TSTCLK_OUT_N

AM16

PEX_RST_N

AG21

PEX_TERMP

AE9

PLLVDD

AF9

SP_PLLVDD

AD9

VID_PLLVDD

B1

XTAL_IN

B2

XTAL_OUT

D1

XTAL_OUTBUFF

D2

XTAL_SSIN

E2

I2CS_SCL

E1

I2CS_SDA

E3

I2CC_SCL

E4

I2CC_SDA

G3

I2CB_SCL

G2

I2CB_SDA

G1

I2CA_SCL

G4

I2CA_SDA

F6

I2CH_SCL

G6

I2CH_SDA

N10P-GS-A1_BGA969

N10P-GS-A1_BGA969

10M@

10M@

12

1 2

R1082 200_0402_5%@R1082 200_0402_5%@

R1084 2.49K_0402_1%PM@R1084 2.49K_0402_1%PM@

+SP_PLLVDD

XTALIN
XTALOUT VGA_CRT_R

XTAL_OUTBUFF
XTAL_SSIN

VGA_LVDS_SCL_C
VGA_LVDS_SDA_C

VGA_HDMI_SCL_R
VGA_HDMI_SDA_R

VGA_DDCCLK_C
VGA_DDCDATA_C

HDCP_I2CH_SCL
HDCP_I2CH_SDA

60mA

45mA
45mA

Part 1 of 7

Part 1 of 7

PCI EXPRESS

PCI EXPRESS

CLK

CLK

I2C

I2C

GPIO

GPIO

DVO

DVO

MIOA_HSYNC
MIOA_VSYNC

MIOB_HSYNC
MIOB_VSYNC

MIOA_CTL3
MIOA_VREF

MIOB_CTL3

MIOB_VREF

MIOA_CLKIN

MIOA_CLKOUT

MIOB_CLKIN

MIOB_CLKOUT

MIOA_CLKOUT_N
MIOB_CLKOUT_N

MIOACAL_PD_VDDQ

MIOACAL_PU_GND

MIOBCAL_PD_VDDQ

MIOBCAL_PU_GND

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_HSYNC

DACA_VSYNC

DACA_VDD
DACA_VREF
DACA_RSET

DACB_RED

DACB_GREEN

DACs

DACs

DACB_BLUE

DACB_HSYNC

DACB_VSYNC

DACB_VDD
DACB_VREF
DACB_RSET

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23

MIOA_D0
MIOA_D1
MIOA_D2
MIOA_D3
MIOA_D4
MIOA_D5
MIOA_D6
MIOA_D7
MIOA_D8

MIOA_D9
MIOA_D10
MIOA_D11
MIOA_D12
MIOA_D13
MIOA_D14

MIOB_D0

MIOB_D1

MIOB_D2

MIOB_D3

MIOB_D4

MIOB_D5

MIOB_D6

MIOB_D7

MIOB_D8

MIOB_D9
MIOBD_10
MIOB_D11
MIOB_D12
MIOB_D13
MIOB_D14

MIOA_DE

MIOB_DE

K1
K2
K3
H3
H2
H1
H4
H5
H6
J7
K4
K5
H7
J4
J6
L1
L2
L4
M4
L7
L5
K6
L6
M6

N1
P4
P1
P2
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6

Y1
Y2
Y3
AB3
AB2
AB1
AC4
AC1
AC2
AC3
AE3
AE2
U6
W6
Y6

N3
L3

W1
W2

N2
P5
N5

Y5
W3
AF1

N4
R4

AE1
V4

T4
W4

U5
T5

AA7
AA6

AM15
AM14
AL14

AM13
AL13

AJ12
AK12
AK13

AK4
AL4
AJ4

AM1
AM2

AG7
AK6
AH7

R1068 10K_0402_5%PM@R1068 10K_0402_5%PM@

R1069 10K_0402_5%PM@R1069 10K_0402_5%PM@

@

@

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

VGA_HSYNC
VGA_VSYNC

+DACA_VDD
DACA_VREF
DACA_RSET

PM@

PM@

R1093

R1093
124_0402_1%

124_0402_1%

+DACB_VDD
DACB_RSET

2

NV_INVTPWM
VGA_ENVDD
VGA_ENBKL
GPU_VID0
GPU_VID1

1 2

1 2

PAD

PAD

T85

T85

R108110K_0402_5% PM@ R108110K_0402_5% PM@

12

R108310K_0402_5% PM@ R108310K_0402_5% PM@

12

1

PM@

PM@

C1163

C1163

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

R1094 10K_0402_5%PM@R1094 10K_0402_5%PM@
R793 10K_0402_5%

R793 10K_0402_5%

1 2

@

@

HDMI_DETECT_VGA <24>

PAD

PAD

T84

T84

VGA_ENVDD <25>

@

@

VGA_ENBKL <25>

VGA_CRT_R <26>
VGA_CRT_G <26>
VGA_CRT_B <26>

VGA_HSYNC <26>
VGA_VSYNC <26>

470P_0402_50V7K

470P_0402_50V7K

1
PM@

PM@

C1160

C1160

2

4700P_0402_16V7K

4700P_0402_16V7K

12

GPU_VID1 GPU_VID0 VGA_CORE P-State

+DACA_VDD

1 2

L509MBK1608121YZF_0603

L509MBK1608121YZF_0603

1

2

PM@

PM@

PM@

PM@

C1161

C1161

C1162

C1162

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

2

1

External Spread Spectrum

U52

OSC_OUT

1
2
3

ASM3P2872AF-06OR_TSOT-23-6@

ASM3P2872AF-06OR_TSOT-23-6@

U52

REFOUT
XOUT
XIN/CLKIN

MODOUT

6

VSS

OSC_SPREAD

5
4

VDD

+3VS

1

@

@

C1147

C1147

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

If External Spread Spectrum not stuff then stuff resistor

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

3

2008/03/25 2008/04/

2008/03/25 2008/04/

2008/03/25 2008/04/

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1

GPU_VID0 <49>

12

PM@

PM@

R1067

R1067
10K_0402_5%

10K_0402_5%

GPU_VID1 <49>

10K_0402_5%

10K_0402_5%

PM@

PM@

R1066

R1066

12

GPIO5GPIO6 N10M-GS N10P-GS

0 0
0

CRT OUT

R1086 150_0402_1%PM@R1086 150_0402_1%PM@

VGA_CRT_G

R1087 150_0402_1%PM@R1087 150_0402_1%PM@

VGA_CRT_B

R1088 150_0402_1%PM@R1088 150_0402_1%PM@

+3VS

PM@

PM@

OSC_OUT XTAL_OUTBUFF

OSC_SPREAD

Compal Electronics,Ltd.

Compal Electronics,Ltd.

Compal Electronics,Ltd.

Title

Title

Title

N10x-GS PCIE,LVDS,GPIO,CLK

N10x-GS PCIE,LVDS,GPIO,CLK

N10x-GS PCIE,LVDS,GPIO,CLK

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Wednesday, March 18, 2009

Date: Sheet of

Wednesday, March 18, 2009

Date: Sheet of

Wednesday, March 18, 2009

1
11

1 2
1 2
1 2

R1075 22_0402_5%@R1075 22_0402_5%@

1 2

R1179 22_0402_5%@R1179 22_0402_5%@

1 2

NIWBA_LA5371P

0.8V

0.85V

0.9V120, 10

12

12

12

16

16

1

16

PM@

PM@

R1077

R1077
10K_0402_5%

10K_0402_5%

XTAL_SSIN

PM@

PM@

R1178

R1178
10K_0402_5%

10K_0402_5%

0.1

0.1

0.1

53

53

53