COMPAL LA-4602P Schematics

A

1 1

2 2

B

C

D

E

Blue Moutain KIWB1/B2

Schematics Document

Mobile Penryn uFCPGA with Intel

3 3

Cantiga_GM/PM+ICH9-M core logic

REV:2.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/03/16 2010/03/15

C

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

Cover Sheet

Size Document Number Rev

Custom

KIWB1/B2_LA4602P

Date: Sheet of

D

Date: Sheet of

1 53Wednesday, March 18, 2009

E

2.0

A

Compal confidential

File Name :

VRAM 64*16

1 1

DDR3*8

page20

PCI-E X16

NVidia N10M-GS1 NVidia N10P-GE1

page16~24

CONN

page26

PS8101T

page26

PCI-EHDMI

CRT cable

page28

2 2

LVDS Connector

page27

PCI Express Mini card Slot 1

page31

PCI Express Mini card Slot 2

page31

6*PCI-E BUS

New Card

PCI Express Mini card Slot 3

3 3

page31

BCM5906/BCM5784M

SIM Card

page31

10/100/1G LAN

RJ45 CONN

ZZZ1

15.6W_PCB_LA4601P

LVDS I/F

page31

page33

B

None PCI BUS

3.3V / 33 MHz

page32

C

Mobile Penryn

uFCPGA-478 CPU

page5,6,7

H_A#(3..35) H_D#(0..63)

FSB 667/800/1066MHz

Intel Cantiga GMCH

PCBGA 1329

page 8,9,10,11,12,13

DMI

C-Line

Intel ICH9-M

mBGA-676

page27,28,29,30

LPC BUS

EC

ENE KB926D

page38

Int.KBD

Touch Pad

page39

BIOS

POWER BD Power on X1 LED X1 (G)

:POWER NOVO X1

Clock Gen.

SLG8SP556VTR ICS9LPRS387AKLFT

DDR3-800(1.5V) DDR3-1067(1.5V)

Dual Channel

AZALIA

12*USB2.0

4*SATA serial

page39

page40

D

Slide Bar LED X 10 (B) USER-DEFINED (W) DOLBY (W) LED X 3 WIRELESS LED (G) BLUETOOTH LED (G) 3G LED (G) HDD LED (G)

page25

POWER ON (G) BATTERY CHARG(G/A) WIRELESS SWITCH (G) ON/OFF

Double check ME

DDR3-SO-DIMM X2

BANK 0, 1, 2, 3

UP TO 8G

SPK amplifier

page36

WOOFER amplifier

Audio Codec

Realtek ALC272

page36

CMOS Camera BlueTooth CONN USB CONN X1 New Card X1 M-PCIE CONN X 3

REPEATER

page35

E

RIGHT BD VOLUME UP X1 VOLUME DOWN X1 MUTE X1 MUTE LED X1(G)

USB_Board USB CONN X 2 TV CONN X1

page 14,15

2Channel Speaker

page37

1Channel Speaker

HP X 1+

page37

page36

page41

page31

MIC_Ext X1 2Channel MIC_Int

Realtek 5158E MS/MS pro/SD/SD pro/mmc/XD

ESATA HDD AND USB CONN

page37

page36

page35

HDD/ODD,SCL & T/L LED on MB

4 4

A

CAPS and NUM on KBD

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/03/16 2010/03/

Compal Secret Data

Deciphered Date

SATA HDD CONN SATA ODD CONN

D

page35

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

MB Block Diagram

KIWB1/B2_LA4602P

2 53Wednesday, March 18, 2009

E

0.1

A

B

C

D

E

DDR3 Voltage Rails

+5VS +3VS

power plane

1 1

+B

State

S0

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

O

O O O

X

+5VALW

+3VALW

O

O O

X X X X

+1.5V

O

X X X

@ FUNCTION

100@ TVSW@ AO@ MONO@

3 3

BT@ WITH BLUETOOTH 3G@ WITH 3G TV@ WITH TV

4 4

(100 LAN) (TV POWER SW) (ALWAYS ON SW) (MONO MIC) (X76 BOM)

10M@ 10P@ PM@ 45@X76@ GM@ GM45@ GL40@ GIGA@ NO_TVSW@ NO_AO@ ARRAY@ S512@ Q512@ S256@ Q256@

(N10M 40nm CHIPSET) (N10P 40nm CHIPSET) (VGA BOM) (45 BOM) (UMA BOM) (GM45 BOM) (GL40 BOM) (GIGA LAN) (NON TV POWER SW) (NON ALWAY ON SW) (ARRAY MIC)

FOR X76 BOM FOR X76 BOM FOR X76 BOM FOR X76 BOM

+1.5VS +1.1VS +VCCP +CPU_CORE +VGA_CORE +1.8VS

+0.75V

OO

X

SMBUS, SPI and I2C Control Table

SOURCE

HDMI BATTEEPROM

LVDS

EC_SMB_CK1 EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

ICH_SMBCLK ICH_SMBDAT ICH9

LVDS_SCL LVDS_SDA

GMCH_CRT_CLK GMCH_CRT_DAT

HDMICLK_NB HDMIDAT_NB

VGA_DDCCLK VGA_DDCDATA

VGA_LVDS_SCL VGA_LVDS_DAT

VGA_HDMI_SCL VGA_HDMI_DAT

HDCP_SMB_CK1 HDCP_SMB_DA1

FSEL#SPICS#_SB FRD#SPI_SO_SB SPI_CLK_SB FWR#SPI_SI_SB

FSEL#SPICS# FRD#SPI_SO SPI_CLK FWR#SPI_SI

KB926

X

KB926

X

Cantiga

X

V

Cantiga

X X X X X X X X X X X X

Cantiga

VGA

ICH9

KB926

X X X X X X X X X X X X

V

X

V

X

V

X

XXX

X

HDCP

SERIAL

CRT

X X X

X X X X X X X X X

NEW

CLK

CARD

GEN

X

X X X

X X

X

V V

X X

Mini

CAP sensor

X X

CARD1

X X

Mini CARD2

X X

V V

X

V

X X X

THERMAL SENSOR (VGA)

V

X X

THERMAL SENSOR (CPU)

VV

V

X X X X X X X X X X

V

X

X X X X X X X X X X X

X X

X

X X X

X X X X X X X X X

X X X X X X X

V

X X X X X X X

V V

XXXXXXX

X X

X

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/03/16 2010/03/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

MB Notes List

KIWB1/B2_LA4601P

3 53Wednesday, March 18, 2009

E

0.1

A

B

C

D

E

Performance Mode P0 TDP at Tj = 102 C* (DDR3)VGA and DDR3 Voltage Rails (N10x GPIO)

GPIO I/O ACTIVE Function Description GPIO0 GPIO1 GPIO2

1 1

GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13

2 2

GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23

3 3

N/A

N/A IN

-

Hot plug detect for IFP link C OUT OUT OUT OUT OUT OUT I/O OUT OUT I/O IN OUT OUT IN OUT IN IN IN IN IN IN

Panel Back-Light brightness(PWM capable)

H

Panel Power Enable

H

Panel Back-Light On/Off (PWM)

H

GPU VID0

GPU VID1

GPU VID2

Thermal Catastrophic Overtemp

L

Thermal Alert

L

Memory VREF switch SLI raster sync

L

AC power detect pin

MEM_VID orPower supply control

-

- Power supply control

-

Hot plug detect for IFP Link E

-

Programmable Fan Control

-

Hot plug detect for IFP Link D

-

Hot plug detect for IFP link F

-

SLI swap ready signal

I/O

GPIO5GPIO6 N10M-GS N10P-GS

(+VGA_CORE)

Products

N10P-GS 128bit 1024MB DDR3

N10P-GE 128bit 1024MB DDR3

N10P-LP 128bit 1024MB DDR3

Performance Mode P0 TDP at Tj = 102 C* (DDR3)

Products

N10M-GE 64bit 512MB DDR3

N10M-GS 64bit 512MB DDR3

N10M-LP 64bit 512MB DDR3

Power Sequence

(+3VS)

(1.1VS)

GPU Mem NVCLK (4) (1,5) (6)

(W) (W)

21.07

20.97

15.48

GPU Mem NVCLK (4) (1,5) (6)

(W) (W)

13.36

14.29

8.28

/MCLK NVVDD (MHz)

6.67

TBD

6.73

TBD

6.44

TBD

/MCLK NVVDD (MHz)

2.93

TBD

3.10

TBD

2.91

TBD

(V) (A) (W) (A) (W) (A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

TBD

18.25

TBD

19.17

TBD

13.95

(V) (A) (W) (A) (W)

TBD

11.89

TBD

11.53

TBD

6.60

The ramp time for any rail must be more than 40us

VDD33

PEX_VDD

NVVDD

17.34

17.25

11.86

10.70

11.53

5.61

tNVVDD

FBVDD

2.06

2.03

1.90

FBVDD

0.66

0.70

0.62

GPU_VID11GPU_VID011VGA_CORE P-State

0 0.8V 0

0

0.85V

0.9V

12 12 0, 10

IFPAB_IOVDD

(1.8VS)

FBVDDQ

FBVDDQ PCI Express I/O and (GPU+Mem) (1.5V)(1.5V)

3.09

4.09

3.05

4.09 6.14

2.85

3.99

FBVDDQ PCI Express I/O and (GPU+Mem) (1.5V)(1.5V)

(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

0.99

2.16

1.05

2.28 3.42

0.93

2.20

(1.05V)

6.14

850 75 0.14

5.99

810

(1.05V)

3.24

792 75 0.14

3.3

782

0.89

0.88840

0.85

0.83

0.86817

0.82

PLLVDD

75 0.14

PLLVDD

75 0.14

PEX_VDD can ramp up any time

tNV-IFPAB_IOVDD

tNV-FBVDDQ

I/O and PLLVDD

63 0.07

I/O and PLLVDD

63 0.07

Other (3.3V)(1.05V)(1.8V)

55 0.18

Other (3.3V)(1.05V)(1.8V)

100 0.33

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/03/16 2010/03/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

VGA Notes List

KIWB1/B2_LA4602P

4 53Wednesday, March 18, 2009

E

0.1

5

4

3

2

1

XDP Reserve

+VCCP

SMCLK

SMDATA

ALERT#

GND

1 2

U2

VEN VIN VO VSET

G990P11U_SO8

12

+VCC_FAN1

1

2

XDP_DBRESET#

XDP_TDI XDP_TMS XDP_TDO XDP_TRST# XDP_TCK

+3VS

12

@ R9

@

8 7 6 5

8

GND

7

GND

6

GND

5

GND

40mil

+VCC_FAN1

R2 1K_0402_5%@R2 1K_0402_5%@

1 2

R4 54.9_0402_1%R4 54.9_0402_1%

1 2

R5 54.9_0402_1%R5 54.9_0402_1%

1 2

R6 54.9_0402_1%@R6 54.9_0402_1%@

1 2

R7 54.9_0402_1%R7 54.9_0402_1%

1 2

R8 54.9_0402_1%R8 54.9_0402_1%

1 2

R9 10K_0402_5%

10K_0402_5%

EC_SMB_CK2 EC_SMB_DA2

+5VS

12

@

D1

D1 1SS355TE-17_SOD323-2

1SS355TE-17_SOD323-2 D2 BAS16_SOT23-3@D2 BAS16_SOT23-3@

1 2

C5 1U_0603_10V4ZC5 1U_0603_10V4Z

1 2

C6 0.1U_0402_16V4ZC6 0.1U_0402_16V4Z

1 2

H_IERR# H_PROCHOT#

D D

H_A#[3..16]<8>

H_ADSTB#0<8>

H_REQ#0<8> H_REQ#1<8> H_REQ#2<8> H_REQ#3<8> H_REQ#4<8>

H_A#[17..35]<8>

C C

H_ADSTB#1<8>

H_A20M#<28>

H_FERR#<28>

H_IGNNE#<28> H_STPCLK#<28>

H_INTR<28>

H_NMI<28> H_SMI#<28>

B B

RSVD pins on the CPU should be left as NO CONNECT

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1

H_A20M# H_FERR# H_IGNNE#

H_STPCLK# H_INTR H_NMI H_SMI#

AA4 AB2 AA3

D22

W6

W2 W5

W3

J4 L5

L4 K5 M3 N2

J1 N3 P5 P2

L2 P4 P1 R1 M1

K3 H2 K2

J3

L1 Y2

U5 R3

U4 Y5 U1 R4 T5 T3

Y4 U2 V4

V1 A6

A5 C4

D5 C6 B4 A3

M4 N5 T2 V3 B2 D2

D3 F6

CONN@

JCPU1A

A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#

REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#

A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]

Penryn

ADDR GROUP_0

ADDR GROUP_1

THERMAL

ICH

THERMTRIP#

RESERVED

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDO TMS

TRST#

DBR#

XDP/ITP SIGNALS

PROCHOT#

THERMDA THERMDC

H CLK

BCLK[0] BCLK[1]

H_ADS#

H1

H_BNR#

E2

H_BPRI#

G5

H_DEFER#

H5

H_DRDY#

F21

H_DBSY#

E1

H_BR0#

F1

H_IERR#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_TRDY#

G2

H_HIT#

G6

H_HITM#

E4

XDP_BPM#0

AD4

XDP_BPM#1

AD3

XDP_BPM#2

AD1

XDP_BPM#3

AC4

XDP_BPM#4

AC2

XDP_BPM#5

AC1

XDP_TCK

AC5

XDP_TDI

AA6

TDI

XDP_TDO

AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_DBRESET#

C20

H_PROCHOT#

D21

H_THERMDA

A24

H_THERMDC

B25

H_THERMTRIP#

C7

CLK_CPU_BCLK

A22

CLK_CPU_BCLK#

A21

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

H_ADS# <8> H_BNR# <8>

H_BPRI# <8> H_DEFER# <8>

H_DRDY# <8> H_DBSY# <8>

H_BR0# <8>

H_INIT# <28>

H_LOCK# <8>

H_RESET# <8> H_RS#0 <8> H_RS#1 <8> H_RS#2 <8> H_TRDY# <8>

H_HIT# <8> H_HITM# <8>

XDP_DBRESET# <29>

H_THERMTRIP# <8,28>

CLK_CPU_BCLK <23> CLK_CPU_BCLK# <23>

+3VS

FAN1 Conn

EN_FAN1<38>

FAN +5VS DROOP

A A

R1 56_0402_5%R1 56_0402_5%

1 2

R3 56_0402_5%R3 56_0402_5%

1 2

USE->68Ω,NOT USE-->56Ω

+3VS

1

C1

0.1U_0402_16V4Z

2

H_THERMDA

1 2

C2 2200P_0402_50V7KC2 2200P_0402_50V7K

1 2

R10 10K_0402_5%R10 10K_0402_5%

H_THERMDC THERM#

2nd Source: ADT7421ARMZ (SA00001UN00)

+VCC_FAN1

EN_FAN1

+VCC_FAN1

R11 100_0402_5%R11 100_0402_5%

1 2

1

2

FAN_SPEED1<38>

1000P_0402_50V7K

U1

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

Address:100_1100

+5VS

C3 10U_0805_10V4ZC3 10U_0805_10V4Z

1 2 3 4

C4

C4 2200P_0402_50V7K

2200P_0402_50V7K

R12

10K_0402_5%

+3VS

C7

+3VS

+VCCP

EC_SMB_CK2 <16,38,42>

EC_SMB_DA2 <16,38,42>

JP1

1

2

3

4

GND

5

GND

E&T_3801-F03N-01RME@

Security Classification

2008/03/25 2008/04/

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/25 2008/04/

3

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

Penryn(1/3)

Size Document Number Rev

Custom

KIWB1/B2_LA4602P

Date: Sheet of

2

Date: Sheet of

5 53Wednesday, March 18, 2009

1

0.1

5

4

3

2

1

+CPU_CORE +CPU_CORE

CONN@

JCPU1B

D D

C C

H_D#[0..15]<8>

H_DSTBN#0<8> H_DSTBP#0<8>

H_DINV#0<8>

H_D#[16..31]<8>

H_DSTBN#1<8> H_DSTBP#1<8>

H_DINV#1<8>

R16 1K_0402_5%@R16 1K_0402_5%@

1 2

R18 1K_0402_5%@R18 1K_0402_5%@

1 2

CPU_BSEL1<23> CPU_BSEL2<23>

T1T1 T2T2 T3T3 T4T4 T5T5

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1

+CPU_GTLREF

TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7

CPU_BSEL0 CPU_BSEL1 CPU_BSEL2

Trace Close CPU < 0.5'

B B

Width=4 mil , Spacing: 15mil (55Ohm)

E22 F24 E26 G22 F23 G25 E25 E23 K24 G24

H22 F26 K22 H23

H26 H25

N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24

AD26

C23 D25 C24

AF26

AF1 A26

B22 B23 C21

J24 J23

J26

C3

JCPU1B

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2]

Penryn

DATA GRP 0

MISC

DATA GRP 1

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]#

DATA GRP 2DATA GRP 3

D[41]# D[42]# D[43]# D[44]# D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]# COMP[0]

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

COMP0 COMP1 COMP2 COMP3

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3

R15 27.4_0402_1%R15 27.4_0402_1%

1 2

R17 54.9_0402_1%R17 54.9_0402_1%

1 2

R19 27.4_0402_1%R19 27.4_0402_1%

1 2

R20 54.9_0402_1%R20 54.9_0402_1%

H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI#

1 2

H_D#[32..47] <8>

H_DSTBN#2 <8> H_DSTBP#2 <8> H_DINV#2 <8>

H_D#[48..63] <8>

H_DSTBN#3 <8> H_DSTBP#3 <8> H_DINV#3 <8>

H_DPRSTP# <8,28,50> H_DPSLP# <28> H_DPWR# <8> H_PWRGOOD <28>CPU_BSEL0<23> H_CPUSLP# <8>

H_PSI# <50>

TRACE CLOSELY CPU < 0.5'

COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) COMP1, COMP3 layout : Width 5mils and Space 25mils (55Ohms)

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

+VCCP

12

R21

R21 1K_0402_1%

1K_0402_1%

Layout note: Z0=55 ohm

0.5" max for GTLREF.

A A

+CPU_GTLREF

12

R24

R24 2K_0402_1%

2K_0402_1%

FSB

BCLK BSEL2 BSEL1 BSEL0 533 667 800

133

166

200

0 0 1

1 00

1067 266 0 0 0

110

Close to CPU pin AD26 within 500mils.

5

4

Security Classification

2007/10/15 2008/10/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Deciphered Date

CONN@

JCPU1C

AA10 AA12 AA13 AA15 AA17 AA18 AA20

AC10 AB10 AB12 AB14 AB15 AB17 AB18

A10 A12 A13 A15 A17 A18 A20

B10 B12 B14 B15 B17 B18 B20

C10 C12 C13 C15 C17 C18

D10 D12 D14 D15 D17 D18

E10 E12 E13 E15 E17 E18 E20

F10 F12 F14 F15 F17 F18 F20 AA7 AA9

AB9

A7

VCC[001]

A9

VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009]

B7

VCC[010]

B9

VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018]

C9

VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025]

D9

VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032]

E7

VCC[033]

E9

VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041]

F7

VCC[042]

F9

VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064]

VCCSENSE VCC[065] VCC[066] VCC[067]

VSSSENSE

Penryn

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

R13 0_0402_5%R13 0_0402_5%

G21

R14 0_0402_5%R14 0_0402_5%

V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

.

For testing purpose only

VCCSENSE

VSSSENSE

12 12

Length match within 25 mils. The trace width/space/other is 18/7/25.

Layout Note: Route VCCSENSE and VSSSENSE traces at

27.4 Ohms with 50 mil spacing. Place PU and PD within 1 inch of CPU. Length matched to within 25 mils.

Title

Size Document Number Rev

B

Date: Sheet of

2

Date: Sheet of

+VCCP

Near pin B26

20mils

CPU_VID0 <50> CPU_VID1 <50> CPU_VID2 <50> CPU_VID3 <50> CPU_VID4 <50> CPU_VID5 <50> CPU_VID6 <50>

VCCSENSE <50>

VSSSENSE <50>

+CPU_CORE

1

C8

2

R22

R22 100_0402_1%

100_0402_1%

1 2

R23

R23 100_0402_1%

100_0402_1%

1 2

10U_0805_10V4ZC810U_0805_10V4Z

+1.5VS

1

C9

2

0.01U_0402_16V7KC90.01U_0402_16V7K

VCCSENSE

VSSSENSE

Close to CPU pin within 500mils.

Compal Electronics, Inc.

Penryn (2/3)

KIWB3/B4_LA4551P

6 53Wednesday, March 18, 2009

1

0.1

5

CONN@

JCPU1D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

D D

C C

B B

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Penryn

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

.

220U_D2_4VM

4

+CPU_CORE

10~15 vias for +CPU_CORE

needed to update

1

2

+

C10

C10 1200U_PFAF250E128MNTTE_2.5VM

1200U_PFAF250E128MNTTE_2.5VM

3 4

10~15 vias for GND

SGA00003F10 1000uF be placed under the center of CPU

Middle Frequency Decoupling

+VCCP

C28

C28 22P_0402_50V8J

22P_0402_50V8J

@

+VCCP

C48

1

+

2

1

C46

0.1U_0402_16V4Z

2

C29

C29 22P_0402_50V8J

22P_0402_50V8J

@

1

C47

0.1U_0402_16V4Z

2

C30

C30 22P_0402_50V8J

22P_0402_50V8J

@

1

C49

0.1U_0402_16V4Z

2

3

20080826FOR 3G ISSUE (SED)

C31

C31 22P_0402_50V8J

22P_0402_50V8J

@

1

C50

0.1U_0402_16V4Z

2

+CPU_CORE

1

2

+CPU_CORE

1

2

Reserved

C26

C26 22P_0402_50V8J

22P_0402_50V8J

@

1

C51

0.1U_0402_16V4Z

2

C832

C832 10U_0805_6.3V6M

10U_0805_6.3V6M

C818

C818 10U_0805_6.3V6M

10U_0805_6.3V6M

1

2

1

@

2

C27

C27 22P_0402_50V8J

22P_0402_50V8J

@

1

2

C834 10U_0805_6.3V6M

10U_0805_6.3V6M

C831

C831 10U_0805_6.3V6M

10U_0805_6.3V6M

Per PWR team request , reserve 12 MLCC for +CPU_CORE

C52

0.1U_0402_16V4Z

C664

C664 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C817

C817 10U_0805_6.3V6M

10U_0805_6.3V6M

2

Place these inside socket cavity on L8 (North side Secondary)

1

@

C834

1

2

1

@

2

C833

C833 10U_0805_6.3V6M

10U_0805_6.3V6M

C830

C830 10U_0805_6.3V6M

10U_0805_6.3V6M

1

@

2

1

2

C644

C644 10U_0805_6.3V6M

10U_0805_6.3V6M

C803

C803 10U_0805_6.3V6M

10U_0805_6.3V6M

1

2

1

@

2

C647

C647 10U_0805_6.3V6M

10U_0805_6.3V6M

C804

C804 10U_0805_6.3V6M

10U_0805_6.3V6M

1

A A

Security Classification

2007/10/15 2008/10/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Penryn (3/3)

KIW10/11_LA4142P

7 53Wednesday, March 18, 2009

1

0.1

5

U3A

AD14

AA13 AA11

AD11 AD10 AD13 AE12

AE14

AE11

F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9

M11

J1 J2

N12

J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6

P13

N8 L7

N10

M3 Y3

Y6 Y10 Y12 Y14

Y7

W2

AA8

Y9 AA9

AE9 AA2 AD8 AA3 AD3 AD7

AF3 AC1 AE3 AC3

AE8

AG2

AD6

C5

E3

C12 E11

A11 B11

12

U3A

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_SWING H_RCOMP

H_CPURST# H_CPUSLP#

H_AVREF H_DVREF

H_RCOMP H_SWNGH_VREF

R51

24.9_0402_1%

CANTIGA ES_FCBGA1329GM45@

H_D#[0..63]<6>

D D

C C

H_RESET#<5> H_CPUSLP#<6>

layout note: Route H_SCOMP and H_SCOMP# with trace width

spacing and impedance (55 ohm) same as FSB data traces

B B

Layout Note: H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20

12

R42

R42 1K_0402_1%

1K_0402_1%

12

R50

R50 2K_0402_1%

2K_0402_1%

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWNG H_RCOMP

H_RESET# H_CPUSLP#

H_VREF

1

C59

0.1U_0402_16V4Z

2

HOST

+VCCP+VCCP

H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADSTB#_0 H_ADSTB#_1

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HITM# H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

12

R43

R43 221_0603_1%

221_0603_1%

12

R52

R52 100_0402_1%

100_0402_1%

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9

H_ADS#

H_BNR#

H_HIT#

within 100 mils from NB

A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20

H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

J8 L3 Y13 Y1

L10 M7 AA5 AE6

L9 M8 AA6 AE5

B15 K13 F13 B13 B14

B6 F12 C8

1

C60

0.1U_0402_16V4Z

2

Near B3 pin

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

4

H_A#[3..35] <5>

SMRCOMP_VOH

SMRCOMP_VOL

H_ADS# <5> H_ADSTB#0 <5> H_ADSTB#1 <5> H_BNR# <5> H_BPRI# <5> H_BR0# <5> H_DEFER# <5> H_DBSY# <5> CLK_MCH_BCLK <23> CLK_MCH_BCLK# <23> H_DPWR# <6> H_DRDY# <5> H_HIT# <5> H_HITM# <5> H_LOCK# <5> H_TRDY# <5>

H_DINV#0 <6> H_DINV#1 <6> H_DINV#2 <6> H_DINV#3 <6>

H_DSTBN#0 <6> H_DSTBN#1 <6> H_DSTBN#2 <6> H_DSTBN#3 <6>

H_DSTBP#0 <6> H_DSTBP#1 <6> H_DSTBP#2 <6> H_DSTBP#3 <6>

H_REQ#0 <5> H_REQ#1 <5> H_REQ#2 <5> H_REQ#3 <5> H_REQ#4 <5>

H_RS#0 <5> H_RS#1 <5> H_RS#2 <5>

Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.

+DDR_MCH_REF

+3VS

12

R34

R34 10K_0402_5%

10K_0402_5%

ICH_POK<29,38>

VGATE<29,50>

PLT_RST#<16,27,31,32>

R37 0_0402_5%R37 0_0402_5% R39 0_0402_5%@R39 0_0402_5%@ R40 100_0402_5%R40 100_0402_5%

1

C61

0.1U_0402_16V4Z

2

1 2 1 2 1 2

1

C53

0.01U_0402_25V7K

2

1

C55

0.01U_0402_25V7K

2

12

R35

R35 10K_0402_5%

10K_0402_5%

PM_EXTTS#0 PM_EXTTS#1

+1.5V

12

R45

R45 1K_0402_1%

1K_0402_1%

12

R53

R53 1K_0402_1%

1K_0402_1%

1

C54

2.2U_0603_6.3V4Z

2

1

C56

2.2U_0603_6.3V4Z

2

PM_POK_R

PLT_RST#_R

MCH_CLKSEL0<23> MCH_CLKSEL1<23> MCH_CLKSEL2<23>

PM_BMBUSY#<29>

H_DPRSTP#<6,28,50> PM_EXTTS#0<14,15> PM_EXTTS#1

H_THERMTRIP#<5,28>

DPRSLPVR<29,50>

+1.5V

12

CFG5

R28

R28 1K_0402_1%

1K_0402_1%

R25

3.01K_0402_1%

R26

R26 1K_0402_1%

1K_0402_1%

3

MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2

CFG5

T28T28 T29T29 T30T30 T31T31 T32T32 T33T33 T34T34 T35T35 T36T36 T37T37 T38T38 T39T39 T40T40 T41T41 T42T42

PM_BMBUSY#

H_DPRSTP#

PM_EXTTS#0

PM_EXTTS#1

PM_POK_R

PLT_RST#_R

H_THERMTRIP#

DPRSLPVR

SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1

SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1

SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1

SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1

SA_ODT_0 SA_ODT_1 SB_ODT_O SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#

CL_VREF

DDPC_CTRLCLK SDVO_CTRLCLK

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

2

M_CLK_DDR0

AP24

M_CLK_DDR1

AT21

M_CLK_DDR2

AV24

M_CLK_DDR3

AU20

M_CLK_DDR#0

AR24

M_CLK_DDR#1

AR21

M_CLK_DDR#2

AU24

M_CLK_DDR#3

AV20

DDR_CKE0_DIMMA

BC28

DDR_CKE1_DIMMA

AY28

DDR_CKE2_DIMMB

AY36

DDR_CKE3_DIMMB

BB36

DDR_CS0_DIMMA#

BA17

DDR_CS1_DIMMA#

AY16

DDR_CS2_DIMMB#

AV16

DDR_CS3_DIMMB#

AR13

M_ODT0

BD17

M_ODT1

AY17

M_ODT2

BF15

M_ODT3

AY13

SMRCOMP

BG22

SMRCOMP#

BH21

SMRCOMP_VOH

BF28

SMRCOMP_VOL

BH28

+DDR_MCH_REF

AV42

SM_PWROK

AR36

SM_REXT

BF17

SM_DRAMRST#

BC36

CLK_MCH_DREFCLK

B38

CLK_MCH_DREFCLK#

A38

MCH_SSCDREFCLK

E41

MCH_SSCDREFCLK#

F41

CLK_MCH_3GPLL

F43

CLK_MCH_3GPLL#

E43

DMI_TXN0

AE41

DMI_TXN1

AE37

DMI_TXN2

AE47

DMI_TXN3

AH39

DMI_TXP0

AE40

DMI_TXP1

AE38

DMI_TXP2

AE48

DMI_TXP3

AH40

DMI_RXN0

AE35

DMI_RXN1

AE43

DMI_RXN2

AE46

DMI_RXN3

AH42

DMI_RXP0

AD35

DMI_RXP1

AE44

DMI_RXP2

AF46

DMI_RXP3

AH43

B33

T43 PADT43 PAD

B32

T44 PADT44 PAD

G33

T45 PADT45 PAD

F33

T46 PADT46 PAD

E33

T47 PADT47 PAD

C34

T48T48

For AMT function

CL_CLK0

AH37

CL_DATA0

AH36 AN36

CL_RST#

AJ35

CL_VREF

AH34

N28 M28

HDMICLK_NB

G36

HDMIDAT_NB

E36

MCH_CLKREQ#

K36

MCH_ICH_SYNC#

H36

B12

MCH_HDA_BCLK

B28

MCH_HDA_RST#

B30

MCH_HDA_SDIN0_R

B29

MCH_HDA_SDOUT

C29

MCH_HDA_SYNC

A28

M_CLK_DDR0 <14> M_CLK_DDR1 <14> M_CLK_DDR2 <15> M_CLK_DDR3 <15>

M_CLK_DDR#0 <14> M_CLK_DDR#1 <14> M_CLK_DDR#2 <15> M_CLK_DDR#3 <15>

DDR_CKE0_DIMMA <14> DDR_CKE1_DIMMA <14> DDR_CKE2_DIMMB <15> DDR_CKE3_DIMMB <15>

DDR_CS0_DIMMA# <14> DDR_CS1_DIMMA# <14> DDR_CS2_DIMMB# <15> DDR_CS3_DIMMB# <15>

M_ODT0 <14> M_ODT1 <14> M_ODT2 <15>

20mil

M_ODT3 <15>

1 2

R29 80.6_0402_1%R29 80.6_0402_1%

R30 0_0402_5%R30 0_0402_5%

1 2

R31 12K_0402_5%@R31 12K_0402_5%@

1 2

R32 10K_0402_5%@R32 10K_0402_5%@

1 2

R33 499_0402_1%R33 499_0402_1%

SM_DRAMRST# <14,15>

DDR3

CLK_MCH_DREFCLK <23> CLK_MCH_DREFCLK# <23> MCH_SSCDREFCLK <23> MCH_SSCDREFCLK# <23>

CLK_MCH_3GPLL <23> CLK_MCH_3GPLL# <23>

DMI_TXN0 <29> DMI_TXN1 <29> DMI_TXN2 <29> DMI_TXN3 <29>

DMI_TXP0 <29> DMI_TXP1 <29> DMI_TXP2 <29> DMI_TXP3 <29>

DMI_RXN0 <29> DMI_RXN1 <29> DMI_RXN2 <29> DMI_RXN3 <29>

DMI_RXP0 <29> DMI_RXP1 <29> DMI_RXP2 <29> DMI_RXP3 <29>

1 2

connect to power CPU_CORE

CL_CLK0 <29> CL_DATA0 <29>

M_PWROK <29> CL_RST# <29>

T49T49 T50T50

R41 56_0402_5%R41 56_0402_5%

1 2

R44 0_0402_5%GM@R44 0_0402_5%GM@ R46 0_0402_5%GM@R46 0_0402_5%GM@ R47 33_0402_5%GM@R47 33_0402_5%GM@ R48 0_0402_5%GM@R48 0_0402_5%GM@ R49 0_0402_5%GM@R49 0_0402_5%GM@

Notice: Please check HDA power rail to select HDA controller.

1 2 1 2 1 2 1 2 1 2

HDMICLK_NB <24> HDMIDAT_NB <24> MCH_CLKREQ# <23> MCH_ICH_SYNC# <29> TSATN# <38>

+VCCP

U3B

CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20

AH10 AH12 AH13

AL34 AK34 AN35

AM35

AY21

BG23 BF23 BH18 BF18

AT40 AT11

BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43

M36 N36 R33 T33 AH9

K12

T24

B31

B2 M1

T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28

R29

B7 N33 P32

T20 R32

BH6 BH5

BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1

F1 A47

U3B

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14

RSVD15 RSVD16 RSVD17

RSVD20

RSVD22 RSVD23 RSVD24 RSVD25

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20

PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR

NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26

CANTIGA ES_FCBGA1329GM45@

RSVD CFG PM NC

SM_RCOMP_VOH SM_RCOMP_VOL

DDR CLK/ CONTROL/ COMPENSATIONHDA

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLKDMIGRAPHICS VIDMEMISC

DDPC_CTRLDATA SDVO_CTRLDATA

T6T6 T7T7 T8T8 T9T9 T10T10 T11T11 T12T12 T13T13 T14T14 T15T15 T16T16 T17T17 T18T18 T19T19

T20T20 T26T26 T21T21

T22T22

T23T23 T24T24 T25T25 T27T27

1

+1.5V

12

R27

80.6_0402_1%

For Crestline: 20ohm For Calero: 80.6ohm For Cantiga: 80.6ohm

MCH_HDA_BCLK

+VCCP

12

1

C58

0.1U_0402_16V4Z

2

HDA_BITCLK_CODEC <28,36> HDA_RST_CODEC# <28,36> HDA_SDIN0 <28> HDA_SDOUT_CODEC <28,36> HDA_SYNC_CODEC <28,36>

1.5V_PGOOD <48> DDR3_SM_PWROK

1

@

C57

C57 10P_0402_50V8J

10P_0402_50V8J

2

R36

R36 1K_0402_1%

1K_0402_1%

R38

R38 499_0402_1%

499_0402_1%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

3

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

Cantiga GMCH(1/6)-GTL

KIWB3/B4_LA4551P

1

8 53Wednesday, March 18, 2009

0.1

5

D D

4

3

2

1

U3D

DDR_A_D[0..63]<14>

C C

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_DQS#0 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AJ38 AJ41

AN38

AM38

AJ36

AJ40 AM44 AM42

AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36

AW36

BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12

BB9 BA9

AU10

AV9

BA11

BD9 AY8 BA6 AV5 AV7

AT9 AN8 AU5 AU6

AT5

AN10

AM11

AM5

AJ9

AJ8

AN12

AM13

AJ11 AJ12

U3D

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

SA_BS_0 SA_BS_1 SA_BS_2

SA_RAS# SA_CAS#

SA_WE#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7

SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3

DDR SYSTEM MEMORY A

SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

CANTIGA ES_FCBGA1329GM45@

BG18 AT25

BB20 BD20 AY20

AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7

AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

DDR_A_BS1 DDR_A_BS2

DDR_A_RAS# DDR_A_CAS# DDR_A_W E#

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_DQS#1

DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11

DDR_A_MA12

DDR_A_MA13

DDR_A_MA14

DDR_A_BS0

BD21

DDR_A_BS[0..2] <14>

DDR_A_RAS# <14> DDR_A_CAS# <14> DDR_A_W E# <14>

DDR_A_DM[0..7] <14>

DDR_A_DQS[0..7] <14>

DDR_A_DQS#[0..7] <14>

DDR_A_MA[0..14] <14>

DDR_B_D[0..63]<15>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AK47 AH46 AP47 AP46

AJ46

AJ48 AM48 AP48 AU47 AU46 BA48 AY48

AT47 AR47 BA47 BC47 BC46 BC44 BG43

BF43 BE45 BC41

BF40

BF41 BG38

BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11

BG8

BH12

BF11

BF8 BG7 BC5 BC6 AY3 AY1

BF6

BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1

AL1

AL2

AJ1 AH1 AM2 AM3 AH3

AJ3

U3E

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

DDR_B_BS0

BC16

SB_BS_0 SB_BS_1 SB_BS_2

SB_RAS# SB_CAS#

SB_WE#

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7

SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2

DDR SYSTEM MEMORY B

SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

CANTIGA ES_FCBGA1329GM45@

BB17 BB33

AU17 BG16 BF14

AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6

AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

DDR_B_BS1 DDR_B_BS2

DDR_B_RAS# DDR_B_CAS# DDR_B_W E#

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14

DDR_B_BS[0..2] <15>

DDR_B_RAS# <15> DDR_B_CAS# <15> DDR_B_W E# <15>

DDR_B_DM[0..7] <15>

DDR_B_DQS[0..7] <15>

DDR_B_DQS#[0..7] <15>

DDR_B_MA[0..14] <15>

A A

Security Classification

2007/10/15 2008/10/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga GMCH (2/6)-DDRII

KIWB3/B4_LA4551P

9 53Wednesday, March 18, 2009

1

0.1

5

+3VS

4

3

PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_C_GRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15] PCIE_GTX_C_MRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15] <16> PCIE_MTX_C_GRX_P[0..15] <16>

PCIE_GTX_C_MRX_N[0..15] <16> PCIE_GTX_C_MRX_P[0..15] <16>

2

1

Strap Pin Table

1 2

R54 2.2K_0402_5%

D D

1 2

R55 2.2K_0402_5%

For Cantiga:2.37kohm For Crestline:2.4kohm For Calero: 1.5Kohm

Note: All LVDS data signals/and it's compliments should be routed Differentially

C C

B B

GMCH_CRT_HSYNC<26>

GMCH_CRT_VSYNC<26>

change R64,R65 from 33ohm to 30ohm by checklist2.0 & CRB1.0 05/08/08

A A

LVDS_SCL LVDS_SDA

GMCH_ENBKL<25>

+3VS

LVDS_SCL<25> LVDS_SDA<25> GM_ENVDD<25>

LVDS_ACLK#<25> LVDS_ACLK<25> LVDS_BCLK#<25> LVDS_BCLK<25>

LVDS_A0#<25> LVDS_A1#<25> LVDS_A2#<25>

R60 75_0402_5%GM@R60 75_0402_5%GM@ R61 75_0402_5%GM@R61 75_0402_5%GM@ R62 75_0402_5%GM@R62 75_0402_5%GM@

GMCH_ENBKL

R56 10K_0402_5%R56 10K_0402_5%

1 2

R57 10K_0402_5%R57 10K_0402_5%

1 2

LVDS_SCL LVDS_SDA GM_ENVDD

1 2

R58 2.37K_0402_1%R58 2.37K_0402_1%

LVDS_A0<25> LVDS_A1<25> LVDS_A2<25>

LVDS_B0#<25> LVDS_B1#<25> LVDS_B2#<25>

LVDS_B0<25> LVDS_B1<25> LVDS_B2<25>

1 2 1 2 1 2

LVDS_ACLK# LVDS_ACLK LVDS_BCLK# LVDS_BCLK

LVDS_A0# LVDS_A1# LVDS_A2#

LVDS_A0 LVDS_A1 LVDS_A2

LVDS_B0# LVDS_B1# LVDS_B2#

LVDS_B0 LVDS_B1 LVDS_B2

Layout Note: Place 150 Ω termination resistors close to GMCH

R63 150_0402_1%GM@R63 150_0402_1%GM@

1 2

R64 150_0402_1%GM@R64 150_0402_1%GM@

1 2

R65 150_0402_1%GM@R65 150_0402_1%GM@

1 2

GMCH_CRT_B<26> GMCH_CRT_G<26> GMCH_CRT_R<26>

GMCH_CRT_CLK<26> GMCH_CRT_DATA<26>

R66

R67 30_0402_1%GM@R67 30_0402_1%GM@

5

30_0402_1%GM@

GMCH_CRT_R GMCH_CRT_G GMCH_CRT_B

@

R68

R68 0_0402_5%

0_0402_5%

GMCH_CRT_CLK GMCH_CRT_DATA

Place the resistor within 500mils (1.27mm)of the (G)MCH

U3C

L32

T51T51

T52T52

T53T53

T54T54

T55T55

TVA_DAC PCIE_MTX_GRX_N2 TVB_DAC TVC_DAC

GMCH_CRT_B GMCH_CRT_G GMCH_CRT_R

20mil

@

R69

R69 0_0402_5%

0_0402_5%

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

12

R70

1.02K_0402_1%

For Cantiga:1.02kohm For Crestline:1.3kohm For Calero: 255ohm

CANTIGA ES_FCBGA1329GM45@

4

PEG_COMPI

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9

LVDS TV VGA

PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8

PCI-EXPRESS GRAPHICS

PEG_TX#_9

PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PEGCOMP trace width and spacing is 20/25 mils.

T37

PEGCOMP

T36

PCIE_GTX_C_MRX_N0

H44

PCIE_GTX_C_MRX_N1

J46

PCIE_GTX_C_MRX_N2

L44

PCIE_GTX_C_MRX_N3

L40

PCIE_GTX_C_MRX_N4

N41

PCIE_GTX_C_MRX_N5

P48

PCIE_GTX_C_MRX_N6

N44

PCIE_GTX_C_MRX_N7

T43

PCIE_GTX_C_MRX_N8

U43

PCIE_GTX_C_MRX_N9

Y43

PCIE_GTX_C_MRX_N10

Y48

PCIE_GTX_C_MRX_N11

Y36

PCIE_GTX_C_MRX_N12

AA43

PCIE_GTX_C_MRX_N13

AD37

PCIE_GTX_C_MRX_N14

AC47

PCIE_GTX_C_MRX_N15

AD39

PCIE_GTX_C_MRX_P0

H43

PCIE_GTX_C_MRX_P1

J44

PCIE_GTX_C_MRX_P2

L43

PCIE_GTX_C_MRX_P3

L41

PCIE_GTX_C_MRX_P4

N40

PCIE_GTX_C_MRX_P5

P47

PCIE_GTX_C_MRX_P6

N43

PCIE_GTX_C_MRX_P7

T42

PCIE_GTX_C_MRX_P8

U42

PCIE_GTX_C_MRX_P9

Y42

PCIE_GTX_C_MRX_P10

W47

PCIE_GTX_C_MRX_P11

Y37

PCIE_GTX_C_MRX_P12

AA42

PCIE_GTX_C_MRX_P13

AD36

PCIE_GTX_C_MRX_P14

AC48

PCIE_GTX_C_MRX_P15

AD40

PCIE_MTX_GRX_N0

J41

PCIE_MTX_GRX_N1

M46 M47

PCIE_MTX_GRX_N3

M40

PCIE_MTX_GRX_N4

M42

PCIE_MTX_GRX_N5

R48

PCIE_MTX_GRX_N6

N38

PCIE_MTX_GRX_N7

T40

PCIE_MTX_GRX_N8

U37

PCIE_MTX_GRX_N9

U40

PCIE_MTX_GRX_N10

Y40

PCIE_MTX_GRX_N11

AA46

PCIE_MTX_GRX_N12

AA37

PCIE_MTX_GRX_N13

AA40

PCIE_MTX_GRX_N14

AD43

PCIE_MTX_GRX_N15

AC46

PCIE_MTX_GRX_P0

J42

PCIE_MTX_GRX_P1

L46

PCIE_MTX_GRX_P2

M48

PCIE_MTX_GRX_P3

M39

PCIE_MTX_GRX_P4

M43

PCIE_MTX_GRX_P5

R47

PCIE_MTX_GRX_P6

N37

PCIE_MTX_GRX_P7

T39

PCIE_MTX_GRX_P8

U36

PCIE_MTX_GRX_P9

U39

PCIE_MTX_GRX_P10

Y39

PCIE_MTX_GRX_P11

Y46

PCIE_MTX_GRX_P12

AA36

PCIE_MTX_GRX_P13

AA39

PCIE_MTX_GRX_P14

AD42

PCIE_MTX_GRX_P15

AD46

PCIE_MTX_GRX_P3 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_P0 PCIE_MTX_GRX_N0

PCIE_GTX_C_MRX_P3

CFG[2:0] FSB Freq select

CFG[4:3] CFG5 (DMI select)

CFG6

CFG7 (Intel Management Engine Crypto strap) CFG8

CFG9 (PCIE Graphics Lane Reversal)

R59 49.9_0402_1%R59 49.9_0402_1%

1 2

Please check Power source if want support IAMT

+VCC_PEG

CFG10 (PCIE Lookback enable)

CFG11 CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

CLOSE TO MCH

C62 0.1U_0402_10V7KPM@C62 0.1U_0402_10V7KPM@

1 2

C63 0.1U_0402_10V7KPM@C63 0.1U_0402_10V7KPM@

1 2

C64 0.1U_0402_10V7KPM@C64 0.1U_0402_10V7KPM@

1 2

C65 0.1U_0402_10V7KPM@C65 0.1U_0402_10V7KPM@

1 2

C66 0.1U_0402_10V7KPM@C66 0.1U_0402_10V7KPM@

1 2

C67 0.1U_0402_10V7KPM@C67 0.1U_0402_10V7KPM@

1 2

C68 0.1U_0402_10V7KPM@C68 0.1U_0402_10V7KPM@

1 2

C69 0.1U_0402_10V7KPM@C69 0.1U_0402_10V7KPM@

1 2

C70 0.1U_0402_10V7KPM@C70 0.1U_0402_10V7KPM@

1 2

C71 0.1U_0402_10V7KPM@C71 0.1U_0402_10V7KPM@

1 2

C72 0.1U_0402_10V7KPM@C72 0.1U_0402_10V7KPM@

1 2

C73 0.1U_0402_10V7KPM@C73 0.1U_0402_10V7KPM@

1 2

C74 0.1U_0402_10V7KPM@C74 0.1U_0402_10V7KPM@

1 2

C75 0.1U_0402_10V7KPM@C75 0.1U_0402_10V7KPM@

1 2

C76 0.1U_0402_10V7KPM@C76 0.1U_0402_10V7KPM@

1 2

C77 0.1U_0402_10V7KPM@C77 0.1U_0402_10V7KPM@

1 2

C78 0.1U_0402_10V7KPM@C78 0.1U_0402_10V7KPM@

1 2

C79 0.1U_0402_10V7KPM@C79 0.1U_0402_10V7KPM@

1 2

C80 0.1U_0402_10V7KPM@C80 0.1U_0402_10V7KPM@

1 2

C81 0.1U_0402_10V7KPM@C81 0.1U_0402_10V7KPM@

1 2

C82 0.1U_0402_10V7KPM@C82 0.1U_0402_10V7KPM@

1 2

C83 0.1U_0402_10V7KPM@C83 0.1U_0402_10V7KPM@

1 2

C84 0.1U_0402_10V7KPM@C84 0.1U_0402_10V7KPM@

1 2

C85 0.1U_0402_10V7KPM@C85 0.1U_0402_10V7KPM@

1 2

C86 0.1U_0402_10V7KPM@C86 0.1U_0402_10V7KPM@

1 2

C87 0.1U_0402_10V7KPM@C87 0.1U_0402_10V7KPM@

1 2

C88 0.1U_0402_10V7KPM@C88 0.1U_0402_10V7KPM@

1 2

C89 0.1U_0402_10V7KPM@C89 0.1U_0402_10V7KPM@

1 2

C90 0.1U_0402_10V7KPM@C90 0.1U_0402_10V7KPM@

1 2

C91 0.1U_0402_10V7KPM@C91 0.1U_0402_10V7KPM@

1 2

C92 0.1U_0402_10V7KPM@C92 0.1U_0402_10V7KPM@

1 2

C93 0.1U_0402_10V7KPM@C93 0.1U_0402_10V7KPM@

1 2

C94 0.1U_0402_10V7KGM@C94 0.1U_0402_10V7KGM@

1 2

C95 0.1U_0402_10V7KGM@C95 0.1U_0402_10V7KGM@

1 2

C96 0.1U_0402_10V7KGM@C96 0.1U_0402_10V7KGM@

1 2

C97 0.1U_0402_10V7KGM@C97 0.1U_0402_10V7KGM@

1 2

C98 0.1U_0402_10V7KGM@C98 0.1U_0402_10V7KGM@

1 2

C99 0.1U_0402_10V7KGM@C99 0.1U_0402_10V7KGM@

1 2

C100 0.1U_0402_10V7KGM@C100 0.1U_0402_10V7KGM@

1 2

C101 0.1U_0402_10V7KGM@C101 0.1U_0402_10V7KGM@

1 2

R71 0_0402_5%GM@R71 0_0402_5%GM@

1 2

Compal Secret Data

2008/03/25 2008/04/

3

Compal Secret Data

Deciphered Date

PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_N15

PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15

TMDS_B_CLK <24> TMDS_B_CLK# <24> TMDS_B_DATA0 <24> TMDS_B_DATA0# <24> TMDS_B_DATA1 <24> TMDS_B_DATA1# <24> TMDS_B_DATA2 <24> TMDS_B_DATA2# <24>

TMDS_B_HPD# <24>

2

000 = FSB 1066MHz 010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved

Reserved 0 = DMI x 2

1 = DMI x 4 0 = The iTPM Host Interface is enable

1 = The iTPM Host Interface is disable 0 =(TLS)chiper suite with no confidentiality

1 =(TLS)chiper suite with confidentiality

*

Reserved 0 = Reverse Lane,15->0, 14->1

1 = Normal Operation,Lane Number in order 0 = Enable

1 = Disable Reserved 00 = Reserved

01 = XOR Mode Enabled 10 = All Z Mode Enabled

ReservedCFG[15:14] 0 = Disabled

1 = Enabled ReservedCFG[18:17] 0 = Normal Operation

(Lane number in Order) 1 = Reverse Lane

0 = Only PCIE or SDVO is operational. 1 = PCIE/SDVO are operating simu.

Title

Size Document Number Rev

Custom

Custom Date: Sheet of

Date: Sheet of

*

(Default)11 = Normal Operation

*

Compal Electronics,Ltd.

Cantiga(3/6)-VGA/LVDS/TV

Cantiga(3/6)-VGA/LVDS/TV KIWB3/B4_LA4551P

KIWB3/B4_LA4551P

1

*

10 53Wednesday, March 18, 2009

0.1

5

0.1U_0402_16V4Z

GM@

+3VS_DAC_BG

0.1U_0402_16V4Z

1

C110

GM@

2

GM@

R85

1 2

0.022U_0402_16V7K

+3VS_DAC_CRT

1

C102

2

0.022U_0402_16V7K

1

C111

2

+VCCP

+3VS_TVDAC

1

C144

2

GM@

0.022U_0402_16V7K

C103

GM@

22U_0805_6.3VA

10U_0805_10V4Z

GM@

C112

1

2

C110

0_0402_5%

PM@

220U_D2_4VY_R15M

1

C145

0.1U_0402_16V4Z

2

GM@

1

C838

@

2

GM@

+1.5VS_PEG_BG: 0.414mA (0.1UF*1)

1

+

C132

2

VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1)

VCCA_DAC_BG: 2.68mA (0.1UF*1, 0.01UF*1)

+1.5VS_PEG_BG

R78

12

0_0603_5%

C129

C133

1

2

12

1

4.7U_0805_10V4Z

2

+1.05VS_A_SM_CK

1U_0402_6.3V4Z

10U_0805_10V4Z

1

C134

2

C130

+1.5VS

R81

1 2

0_0805_5%

10U_0805_10V4Z

R82

0_0603_5%

+3VS

R72

1 2

0_0603_5%

GM@

+3VS

D D

C C

B B

R74

1 2

0_0603_5%

GM@

C102

0_0402_5%

PM@

PM@ R79

VCCA_SM:720mA (22UF*2, 4.7UF*1, 1UF*1)

VCCA_SM_CK: 220mA (22UF*1, 2.2UF*1, 0.1UF*1)

+3VS

0_0603_5%

C144

0_0402_5%

PM@

4

+3VS_DAC_CRT

+3VS_DAC_BG

+1.05VS_DPLLA +1.05VS_DPLLB

+1.05VS_HPLL +1.05VS_MPLL

+1.8V_TXLVDS

1000P_0402_50V7K

1

C122

0.1U_0402_16V4Z

2

C137

1

2

+3VS_TVDAC: 40mA (0.1UF*1, 0.01UF*1 for each DAC)

VCC_HDA: 50mA (0.1UF*1)

+1.05VS_PEGPLL

+1.05VS_A_SM

1

1U_0603_10V4Z

2

1U_0603_10V4Z

C138

+3VS_TVDAC

1

C120

2

0.1U_0402_16V4Z

1

2

+1.5VS_TVDAC +1.5VS_QDAC

+1.05VS_HPLL

+1.05VS_PEGPLL

+1.8V_LVDS

+1.5VS

20 mils

1

C131

2

U3H

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

AD48

VCCA_PEG_BG

AA48

VCCA_PEG_PLL

AR20

VCCA_SM_1

AP20

VCCA_SM_2

AN20

VCCA_SM_3

AR17

VCCA_SM_4

AP17

VCCA_SM_5

AN17

VCCA_SM_6

AT16

VCCA_SM_7

AR16

VCCA_SM_8

AP16

VCCA_SM_9

AP28

VCCA_SM_CK_1

AN28

VCCA_SM_CK_2

AP25

VCCA_SM_CK_3

AN25

VCCA_SM_CK_4

AN24

VCCA_SM_CK_5

AM28

VCCA_SM_CK_NCTF_1

AM26

VCCA_SM_CK_NCTF_2

AM25

VCCA_SM_CK_NCTF_3

AL25

VCCA_SM_CK_NCTF_4

AM24

VCCA_SM_CK_NCTF_5

AL24

VCCA_SM_CK_NCTF_6

AM23

VCCA_SM_CK_NCTF_7

AL23

VCCA_SM_CK_NCTF_8

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS_1

L37

VCCD_LVDS_2

POWER

A SM

HDA

LVDS D TV/CRT

U3

CRTPLLA LVDSA PEG

TV

VTT

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

AXF

VCC_SM_CK_1

VCC_SM_CK_2

VCC_SM_CK_3

VCC_SM_CK_4

SM CK

VCC_TX_LVDS

A CK

HV

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5

VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4

DMI PEG

VTTLF

CANTIGA ES_FCBGA1329GM45@

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25

VCC_HV_1 VCC_HV_2 VCC_HV_3

VTTLF1 VTTLF2 VTTLF3

U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1

B22 B21 A21

BF21 BH20 BG20 BF20

K47

C35 B35 A35

V48 U48 V47 U47 U46

AH48 AF48 AH47 AG47

A8 L1 AB2

3

+VCCP

+1.8V_TXLVDS

+VCC_PEG

+VCC_DMI

VCC_DMI: 456mA (0.1UF*1)

20mils

1

C150

2

220U_D2_4VM

1

+

C104

2

1

C1130.47U_0402_6.3V6K C1130.47U_0402_6.3V6K

2

+V1.05VS_AXF

+1.5V_SM_CK

0.47U_0402_6.3V6K

1

C151

2

0.1U_0402_16V4Z

+VCCP

+3VS

+1.05VS_DPLLA

0.1U_0402_16V4Z

C106

1

2

GM@

+1.05VS_DPLLB

0.1U_0402_16V4Z

C115

1

2

GM@

+1.05VS_HPLL

1

C123

2

+1.05VS_MPLL

1

C135

2

+1.05VS_PEGPLL

0.1U_0402_16V4Z

0.1U_0402_16V4Z C146

C146

1

2

+VCCP_D

D3

@D3

@

2 1

CH751H-40PT_SOD323-2

4.7U_0805_10V4Z

1

@

C105

2

4.7U_0805_10V4Z

1

C114

2

+3VS_HV

0.1U_0402_16V4Z

1

C142

2

0.47U_0402_6.3V6K

1

C152

2

1 2

10U_0805_10V4Z

MCK3225151YZF 1210

1

C107

2

GM@

+1.05VS_DPLLA +1.05VS_DPLLB: 64.8mA (470UF*1, 0.1UF*1)

R76

1 2

10U_0805_10V4Z

MCK3225151YZF 1210

1

GM@

C116

2

GM@

R79

BLM18PG121SN1D_0603

1

C124

2.2U_0603_6.3V4Z

2

R83

BLM18PG121SN1D_0603

1

C139

2.2U_0603_6.3V4Z

2

1 2

BLM18PG121SN1D_0603

1

C147

2.2U_0603_6.3V4Z

2

R87

@R87

@

10_0402_5%

R73

+VCCP

GM@

+VCCP

+1.05VS_HPLL: 24mA (4.7UF*1, 0.1UF*1)

12

+VCCP

1.05VS_MPLL: 139.2mA (22UF*1, 0.1UF*1)

12

+VCCP

+1.5VS_PEG_PLL: 50mA (0.1UF*1)

L1

R88

12

0_0402_5%

12

+VCCP

C140

0_0402_5%

PM@

+3VS_HV

C126

0_0402_5%

PM@

40 mils

1000P_0402_50V7K

GM@

0316 add

+V1.05VS_AXF

10U_0805_10V4Z

+1.5VS_TVDAC

C126

1

C140

2

+VCC_PEG

1

C143

+

2

+VCC_DMI

C153

1

2

C108

1

2

0.022U_0402_16V7K

1

2

+1.8V_TXLVDS

C141

220U_D2_4VM

C148

1U_0603_10V4Z

C154

+1.5V_SM_CK

C117

1

C127

2

GM@

10U_0805_10V4Z

1

2

10U_0805_10V4Z

1

2

10U_0805_10V4Z

1

2

1U_0603_10V4Z

1

2

1

2

0.1U_0402_16V4Z

C128

R84

0_0603_5%

GM@

C155

1

VCC_AXF: 321.35mA (10UF*1, 1UF*1)

1 2

R75

0_0603_5%

C109

VCC_SM_CK: 119.85mA (10UF*1, 0.1UF*1)

0.1U_0402_16V4Z

10U_0805_10V4Z

C118

1

2

10U_0805_10V4Z

1

VCCD_TVDAC: 58.696mA

2

(0.1UF*1, 0.01UF*1)

GM@

12

+1.8V_TXLVDS: 118.8mA (22UF*1, 1000PF*1)

+VCCP

R166

12

0_1206_5%

R86

0_0805_5%

10U_0805_10V4Z

1

2

+VCCP

R77

1 2

0_0805_5%

R80

0_0603_5%

GM@

+1.8V

+VCCP

12

+1.5V

+1.5VS

12

PM

PM@

U3

1

C156

C157

2

VCCD_QDAC: 48.363mA (0.1UF*1, 0.01UF*1)

R89

0_0603_5%

0.1U_0402_16V4Z

10U_0805_10V4Z

1

C158

GM@

2

GM@

2

5

+1.8V_LVDS

12

+1.5VS

GM@

10U_0805_10V4Z

1

C159

2

+1.5VS_QDAC

1U_0402_6.3V4Z

A A

GM@

1.8V_LVDS: 60.311111mA (1UF*1)

R90

0_0603_5%

1U_0603_10V4Z

GM@

C160

1

2

GM@

12

C160

0_0603_5%

PM@

4

+1.8V

GL40

GL40@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPE RTY OF COMPAL ELE CTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPE RTY OF COMPAL ELE CTRONICS, INC. A ND CONTAINS CONFIDENTIAL AND TRAD E SECRET INFOR MATION. THIS SHEET MAY NOT BE TRAN SFERED FR OM THE CUSTO DY OF THE COM PETENT DIVISION OF R &D

AND TRAD E SECRET INFOR MATION. THIS SHEET MAY NOT BE TRAN SFERED FR OM THE CUSTO DY OF THE COM PETENT DIVISION OF R &D

AND TRAD E SECRET INFOR MATION. THIS SHEET MAY NOT BE TRAN SFERED FR OM THE CUSTO DY OF THE COM PETENT DIVISION OF R &D DEPARTMEN T EXCEPT AS AU THORIZED BY COM PAL ELECTRONICS , INC. NEITHER TH IS SHEET NOR T HE INFORMATION IT C ONTAINS

DEPARTMEN T EXCEPT AS AU THORIZED BY COM PAL ELECTRONICS , INC. NEITHER TH IS SHEET NOR T HE INFORMATION IT C ONTAINS

DEPARTMEN T EXCEPT AS AU THORIZED BY COM PAL ELECTRONICS , INC. NEITHER TH IS SHEET NOR T HE INFORMATION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Crestline GMCH (4/6)-VCC

Custom

Crestline GMCH (4/6)-VCC

KIWB3/B4_LA4551P

11 53Friday, April 17, 2009

1

11 53Friday, April 17, 2009

0.1

5

D D

0.22U_0402_10V4Z

10U_0805_10V4Z

C C

B B

A A

0.22U_0402_10V4Z

C170

1

C167

2

1

2

+VCCP

0.1U_0402_16V4Z

C171

C172

1

2

AG34 AC34 AB34 AA34

AM33

AK33

AJ33 AG33 AF33

AE33 AC33 AA33

W33

AH28 AF28 AC28 AA28

AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24

AJ23 AH23 AF23

U3G

VCC_1 VCC_2 VCC_3 VCC_4

Y34

VCC_5

V34

VCC_6

U34

VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

VCC_13 VCC_14 VCC_15

Y33

VCC_16 VCC_17

V33

VCC_18

U33

VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34

T32

VCC_35

VCC CORE

4

POWER

+VCCP

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

GM@

C173

1U_0603_10V4Z

VCC NCTF

CANTIGA ES_FCBGA1329GM45@

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44

3

1782mA

+1.5V

220U_D2_4VM_R15

1

C168

+

2

GM@

+VCCP +AXG_CORE

1

2

220U_D2_4VM_R15

GM@

C174

@

J1

112

JUMP_43X118

10U_0805_10V4Z

1

GM@

+

C175

2

1

2

GM@

1

C176

2

10U_0805_10V4Z

C176

0_0805_5%

PM@

10U_0805_10V4Z

C162

1

2

0.01U_0402_16V7K

C163

2

1

+AXG_CORE

0.1U_0402_16V4Z

GM@

1

C177

2

U3F

AP33

VCC_SM_1

AN33

VCC_SM_2

BH32

VCC_SM_3

BG32

VCC_SM_4

BF32

VCC_SM_5

BD32

VCC_SM_6

BC32

VCC_SM_7

BB32

VCC_SM_8

BA32

VCC_SM_9

AY32

VCC_SM_10

AW32

VCC_SM_11

AV32

VCC_SM_12

AU32

VCC_SM_13

AT32

VCC_SM_14

AR32

VCC_SM_15

AP32

VCC_SM_16

AN32

VCC_SM_17

BH31

VCC_SM_18

BG31

VCC_SM_19

BF31

VCC_SM_20

BG30

VCC_SM_21

BH29

VCC_SM_22

BG29

VCC_SM_23

BF29

VCC_SM_24

BD29

VCC_SM_25

BC29

VCC_SM_26

BB29

VCC_SM_27

BA29

VCC_SM_28

AY29

VCC_SM_29

AW29

VCC_SM_30

AV29

VCC_SM_31

AU29

VCC_SM_32

AT29

VCC_SM_33

AR29

VCC_SM_34

AP29

VCC_SM_35

BA36

VCC_SM_36/NC

BB24

VCC_SM_37/NC

BD16

VCC_SM_38/NC

BB21

VCC_SM_39/NC

AW16

VCC_SM_40/NC

AW13

VCC_SM_41/NC

AT13

VCC_SM_42/NC

Y26

VCC_AXG_1

AE25

VCC_AXG_2

AB25

VCC_AXG_3

AA25

VCC_AXG_4

AE24

VCC_AXG_5

AC24

VCC_AXG_6

AA24

VCC_AXG_7

Y24

VCC_AXG_8

AE23

VCC_AXG_9

AC23

VCC_AXG_10

AB23

VCC_AXG_11

AA23

VCC_AXG_12

AJ21

VCC_AXG_13

AG21

VCC_AXG_14

AE21

VCC_AXG_15

AC21

VCC_AXG_16

AA21

VCC_AXG_17

Y21

VCC_AXG_18

AH20

VCC_AXG_19

AF20

VCC_AXG_20

AE20

VCC_AXG_21

AC20

VCC_AXG_22

AB20

VCC_AXG_23

AA20

VCC_AXG_24

T17

VCC_AXG_25

T16

VCC_AXG_26

AM15

VCC_AXG_27

AL15

VCC_AXG_28

AE15

VCC_AXG_29

AJ15

VCC_AXG_30

AH15

VCC_AXG_31

AG15

VCC_AXG_32

AF15

VCC_AXG_33

AB15

VCC_AXG_34

AA15

VCC_AXG_35

Y15

VCC_AXG_36

V15

VCC_AXG_37

U15

VCC_AXG_38

AN14

VCC_AXG_39

AM14

VCC_AXG_40

U14

VCC_AXG_41

T14

VCC_AXG_42

AJ14

T56T56 T57T57

AH14

VCC_AXG_SENSE VSS_AXG_SENSE

VCC_AXG_NTCF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC SM

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43

VCC GFX NCTF

VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52

POWER

VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60

VCC GFX

VCC SM LF

CANTIGA ES_FCBGA1329GM45@

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

AV44 BA37 AM40 AV21 AY5 AM10 BB13

+AXG_CORE

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

Check : power

0.1U_0402_16V4Z

0.1U_0402_16V4Z C164

C164

1

GM@

2

C180 0.1U_0402_16V4ZC180 0.1U_0402_16V4Z

C179 0.1U_0402_16V4ZC179 0.1U_0402_16V4Z

1

2

1

C165

1

GM@

2

0.22U_0402_10V4Z

C166

0_0603_5%

PM@

C182 0.22U_0402_10V4ZC182 0.22U_0402_10V4Z

C181 0.22U_0402_10V4ZC181 0.22U_0402_10V4Z

1

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K C166

C166

1

GM@

2

C184 1U_0402_6.3V4ZC184 1U_0402_6.3V4Z

C183 0.47U_0402_6.3V6KC183 0.47U_0402_6.3V6K

1

2

C185 1U_0402_6.3V4ZC185 1U_0402_6.3V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Crestline GMCH (5/6)-VCC

KIWB3/B4_LA4551P

12 53Wednesday, March 18, 2009

1

0.1

5

U3I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

VSS_8

AD47

VSS_9

AB47

VSS_10

Y47

VSS_11

T47

BD46 BA46 AY46 AV46 AR46 AM46

BF44 AH44 AD44 AA44

BC43 AV43 AU43 AM43

BG42 AY42 AT42 AN42

AJ42

AE42

BD41 AU41 AM41 AH41 AD41 AA41

BG40 BB40 AV40 AN40

AT39 AM39

AJ39

AE39

BH38 BC38 BA38 AU38 AH38 AD38 AA38

BF37 BB37

AW37

AT37 AN37

AJ37

BG36 BD36 AK15 AU36

N47 G47

V46 R46 P46 H46

U44 M44

C43

N42

U41 M41

G41 B41

H40 E40

N39 B39

U38

C38

H37 C37

VSS_12 VSS_13

L47

VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25

F46

VSS_26 VSS_27 VSS_28 VSS_29 VSS_30

Y44

VSS_31 VSS_32

T44

VSS_33 VSS_34

F44

VSS_35 VSS_36 VSS_37 VSS_38 VSS_39

J43

VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48

L42

VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55

Y41

VSS_56 VSS_57

T41

VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72

L39

VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81

Y38

VSS_82 VSS_83

T38

VSS_84

J38

VSS_85

F38

VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

VSS

CANTIGA ES_FCBGA1329GM45@

D D

C C

B B

A A

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6

4

U3J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

VSS_230

M17

VSS_231

H17

VSS_232

C17

VSS_233

BA16

VSS_235

AU16

VSS_237

AN16

VSS_238

N16

VSS_239

K16

VSS_240

G16

VSS_241

E16

VSS_242

BG15

VSS_243

AC15

VSS_244

W15

VSS_245

A15

VSS_246

BG14

VSS_247

AA14

VSS_248

C14

VSS_249

BG13

VSS_250

BC13

VSS_251

BA13

VSS_252

AN13

VSS_255

AJ13

VSS_256

AE13

VSS_257

N13

VSS_258

L13

VSS_259

G13

VSS_260

E13

VSS_261

BF12

VSS_262

AV12

VSS_263

AT12

VSS_264

AM12

VSS_265

AA12

VSS_266

J12

VSS_267

A12

VSS_268

BD11

VSS_269

BB11

VSS_270

AY11

VSS_271

AN11

VSS_272

AH11

VSS_273

Y11

VSS_275

N11

VSS_276

G11

VSS_277

C11

VSS_278

BG10

VSS_279

AV10

VSS_280

AT10

VSS_281

AJ10

VSS_282

AE10

VSS_283

AA10

VSS_284

M10

VSS_285

BF9

VSS_286

BC9

VSS_287

AN9

VSS_288

AM9

VSS_289

AD9

VSS_290

G9

VSS_291

B9

VSS_292

BH8

VSS_293

BB8

VSS_294

AV8

VSS_295

AT8

VSS_296

CANTIGA ES_FCBGA1329GM45@

VSS

3

VSS NCTF

VSS SCB

VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325

VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350

VSS_351 VSS_352 VSS_353 VSS_354

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5

NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34

NC

NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

U24 U28 U25 U29

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

BH48 BH1 A48 C1 A3

E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48

2

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga GMCH (6/6)-GND

KIWB3/B4_LA4551P

13 53Wednesday, March 18, 2009

1

0.1

5

DDR_A_DQS#[0..7]<9>

DDR_A_D[0..63]<9>

DDR_A_DM[0..7]<9> DDR_A_DQS[0..7]<9> DDR_A_MA[0..14]<9>

D D

+1.5V

Layout Note:

C C

Layout Note: Place near JP2.203 & JP2.204

B B

A A

Place near JP2

+1.5V

10U_0805_6.3V6M

1

C188

C187

2

1

2

+0.75V

1U_0603_10V4Z

10U_0805_6.3V6M

1

C190

C189

2

1U_0603_10V4Z

2

1

2

C201

C200

1

5

C14

C14 22P_0402_50V8J

22P_0402_50V8J

@

10U_0805_6.3V6M

C191

1U_0603_10V4Z

2

C202

1

+V_DDR3_DIMM_REF<15>

FOR 3G ISSUE (SED)

C16

C15

C15 22P_0402_50V8J

22P_0402_50V8J

@

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

0.1U_0402_16V4Z

10U_0805_6.3V6M

1

2

C203

0.1U_0402_16V4Z

10U_0805_6.3V6M

1

C192

2

10U_0805_6.3V6M

1

C204

2

C16 22P_0402_50V8J

22P_0402_50V8J

@

0.1U_0402_16V4Z

0.1U_0402_16V4Z C194

C194

C193

1

2

4

+V_DDR3_DIMM_REF

1

C186

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z C195

C195

1

2

4

+1.5V

12

R91

R91 100_0402_1%

100_0402_1%

12

R92

100_0402_1%

20080826

C17

C17 22P_0402_50V8J

22P_0402_50V8J

@

1

C196

+

2

+V_DDR3_DIMM_REF

C18

C18 22P_0402_50V8J

22P_0402_50V8J

@

C197

C197 470U_D2_2.5VM_R15

470U_D2_2.5VM_R15

@

3

+V_DDR3_DIMM_REF

DDR_A_D0 DDR_A_D1

DDR_A_DM0 DDR_A_D2

DDR_A_D3 DDR_A_D8

DDR_A_D9 DDR_A_DQS#1

DDR_A_DQS1 DDR_A_D10

DDR_A_D11 DDR_A_D16

DDR_A_D17 DDR_A_DQS#2

DDR_A_DQS2 DDR_A_D18

DDR_A_D19 DDR_A_D24

1

2

2.2U_0603_6.3V4Z

C206

3

10K_0402_5%

1

2

DDR_A_D25 DDR_A_DM3 DDR_A_D26

DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3

DDR_A_MA1 M_CLK_DDR0

M_CLK_DDR#0 DDR_A_MA10

DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5 DDR_A_D42

DDR_A_D43 DDR_A_D48

DDR_A_D49 DDR_A_DQS#6

DDR_A_DQS6 DDR_A_D50

DDR_A_D51 DDR_A_D56

DDR_A_D57 DDR_A_DM7 DDR_A_D58

DDR_A_D59

R96

1 2

0.1U_0402_16V4Z

C19

C19 22P_0402_50V8J

22P_0402_50V8J

@

DDR_CKE0_DIMMA<8>

DDR_A_BS2<9>

M_CLK_DDR0<8> M_CLK_DDR#0<8>

DDR_A_BS0<9>

DDR_A_WE#<9>

DDR_A_CAS#<9> M_ODT0 <8>

DDR_CS1_DIMMA#<8>

+3VS

C205

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.5V +1.5V

JP2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

12

R97

10K_0402_5%

2007/09/29 2007/09/29

VTT1

205

G1

FOX _AS0A626-U2RN-7F_RV

Compal Secret Data

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1

VDD2

A15 A14

VDD4

A11

A7

VDD6

A6 A4

VDD8

A2 A0

VDD10

CK1 CK1#

VDD12

BA1 RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL

VTT2

G2

Deciphered Date

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

2

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR_A_DM1 SM_DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2 DDR_A_D22

DDR_A_D23 DDR_A_D28

DDR_A_D29 DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D30

DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2

DDR_A_MA0 M_CLK_DDR1

M_CLK_DDR#1 DDR_A_BS1

DDR_A_RAS# DDR_CS0_DIMMA#

M_ODT0 M_ODT1

DDR_VREF_CA_DIMMA DDR_A_D36

DDR_A_D37 DDR_A_DM4 DDR_A_D38

DDR_A_D39 DDR_A_D44

DDR_A_D45 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D46

DDR_A_D47 DDR_A_D52

DDR_A_D53 DDR_A_DM6 DDR_A_D54

DDR_A_D55 DDR_A_D60

DDR_A_D61 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63 PM_EXTTS#0_1

CLK_SMBDATA CLK_SMBCLK

+0.75V

2

1

SM_DRAMRST# <8,15>

DDR_CKE1_DIMMA <8>

M_CLK_DDR1 <8> M_CLK_DDR#1 <8>

DDR_A_BS1 <9> DDR_A_RAS# <9>

DDR_CS0_DIMMA# <8>

M_ODT1 <8>

R95

1 2

0_0402_5%

PM_EXTTS#0 <8,15>

CLK_SMBDATA <15,23> CLK_SMBCLK <15,23>

2.2U_0805_16V4Z

1

C198

2

0.1U_0402_16V4Z

1

2

+V_DDR3_DIMM_REF

C199

DDR3 SO-DIMM A REVERSE

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

KIWB1/B2_LA4601P

1

1.0

14 53Monday, April 27, 2009

1.0

5

DDR_B_DQS#[0..7]<9>

DDR_B_D[0..63]<9>

DDR_B_DM[0..7]<9>

DDR_B_DQS[0..7]<9>

DDR_B_MA[0..14]<9>

D D

C C

B B

A A

Layout Note: Place near JP3

+1.5V

10U_0805_6.3V6M

1

C208

C207

2

+1.5V

C22

C22 22P_0402_50V8J

22P_0402_50V8J

@

Layout Note: Place near JP3.203 & JP3.204

+0.75V

1U_0603_10V4Z

2

C218

1

10U_0805_6.3V6M

1

C210

C209

2

FOR 3G ISSUE (SED)

C23

C23 22P_0402_50V8J

22P_0402_50V8J

@

1U_0603_10V4Z

2

C219

C220

1

5

1

2

1

10U_0805_6.3V6M

C221

10U_0805_6.3V6M

1

C211

2

C24

C24 22P_0402_50V8J

22P_0402_50V8J

@

1

C222

2

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

0.1U_0402_16V4Z

C212

10U_0805_6.3V6M

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z C213

C213

1

2

20080826

C25

C25 22P_0402_50V8J

22P_0402_50V8J

@

C214

1

2

C20

C20 22P_0402_50V8J

22P_0402_50V8J

@

0.1U_0402_16V4Z

1

2

C215

0.1U_0402_16V4Z

1

2

4

C216

1

+

C217

C217 470U_D2_2.5VM_R15

470U_D2_2.5VM_R15

@

2

C21

C21 22P_0402_50V8J

22P_0402_50V8J

@

4

3

+1.5V +1.5V

+V_DDR3_DIMM_REF

JP3

+V_DDR3_DIMM_REF<14>

DDR_B_BS2<9>

M_CLK_DDR2<8> M_CLK_DDR#2<8>

DDR_B_BS0<9>

DDR_B_WE#<9>

DDR_B_CAS#<9> M_ODT2 <8>

DDR_CS3_DIMMB#<8>

+3VS

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

10K_0402_5%

1

C225

2

0.1U_0402_16V4Z

Issued Date

DDR_B_D0 DDR_B_D1

DDR_B_DM0 DDR_B_D2

DDR_B_D3 DDR_B_D8

DDR_B_D9 DDR_B_DQS#1

DDR_B_DQS1 DDR_B_D10

DDR_B_D11 DDR_B_D16

DDR_B_D17 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D18

DDR_B_D19 DDR_B_D24

DDR_B_D25 DDR_B_DM3 DDR_B_D26

DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3

DDR_B_MA1 M_CLK_DDR2

M_CLK_DDR#2 DDR_B_MA10

DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDR_B_MA13

DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49 DDR_B_DQS#6

DDR_B_DQS6 DDR_B_D50

DDR_B_D51 DDR_B_D56

DDR_B_D57 DDR_B_DM7 DDR_B_D58

DDR_B_D59

R99

1 2

R100

10K_0402_5%

3

JP3

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-UARN-7F _RV

2007/09/29 2007/09/29

2 4

DQ4

6

DQ5

8

VSS3

10

DQS#0

12

DQS0

14

VSS6

16

DQ6

18

DQ7

20

VSS8

22

DQ12

24

DQ13

26

VSS10

28

DM1

30 32 34

DQ14

36

DQ15

38 40

DQ20

42

DQ21

44 46

DM2

48

VSS17

50

DQ22

52

DQ23

54

VSS19

56

DQ28

58

DQ29

60

VSS21

62 64

DQS3

66 68

DQ30

70

DQ31

72

74

CKE1

76

VDD2

78

A15

80

A14

82

VDD4

84

A11

86

A7

88

VDD6

90

A6

92

A4

94

VDD8

96

A2

98

A0

100

VDD10

102

CK1

104

CK1#

106

VDD12

108

BA1

110

RAS#

112

VDD14

114

S0#

116

ODT0

118

VDD16

120

ODT1

122

NC2

124

VDD18

126

VREF_CA

128

VSS28

130

DQ36

132

DQ37

134

VSS30

136

DM4

138

VSS31

140

DQ38

142

DQ39

144

VSS33

146

DQ44

148

DQ45

150

VSS35

152

DQS#5

154

DQS5

156

VSS38

158

DQ46

160

DQ47

162

VSS40

164

DQ52

166

DQ53

168

VSS42

170

DM6

172

VSS43

174

DQ54

176

DQ55

178

VSS45

180

DQ60

182

DQ61

184

VSS47

186

DQS#7

188

DQS7

190

VSS50

192

DQ62

194

DQ63

196

VSS52

198

EVENT#

200

SDA

202

SCL

204

VTT2

206

G2

+0.75V

Compal Secret Data

Deciphered Date

2

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR_B_DM1 SM_DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2 DDR_B_D22

DDR_B_D23 DDR_B_D28

DDR_B_D29 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D30

DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA14 DDR_B_MA11

DDR_B_MA7 DDR_B_MA6

DDR_B_MA4 DDR_B_MA2

DDR_B_MA0 M_CLK_DDR3

M_CLK_DDR#3 DDR_B_BS1

DDR_B_RAS# DDR_CS2_DIMMB#

M_ODT2 M_ODT3

DDR_VREF_CA_DIMMB

DDR_B_D36 DDR_B_D37

DDR_B_DM4 DDR_B_D38

DDR_B_D39 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D47 DDR_B_D52

DDR_B_D53 DDR_B_DM6 DDR_B_D54

DDR_B_D55 DDR_B_D60

DDR_B_D61 DDR_B_DQS#7

DDR_B_DQS7 DDR_B_D62

DDR_B_D63 PM_EXTTS#0_1

CLK_SMBDATA CLK_SMBCLK

+0.75V

2

1

SM_DRAMRST# <8,14>

DDR_CKE3_DIMMB <8>DDR_CKE2_DIMMB<8>

M_CLK_DDR3 <8> M_CLK_DDR#3 <8>

DDR_B_BS1 <9> DDR_B_RAS# <9>

DDR_CS2_DIMMB# <8>

M_ODT3 <8>

R98

1 2

0_0402_5%

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

C223

C224

2

+V_DDR3_DIMM_REF

same with intel DDR3 CRB connection

PM_EXTTS#0 <8,14>

CLK_SMBDATA <14,23> CLK_SMBCLK <14,23>

DDR3 SO-DIMM B REVERSE

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

KIWB1/B2_LA4601P

15 53Monday, April 27, 2009

1

1.0

5

D D

C C

B B

A A

+VCCP +PLLVDD

L508 MBK1608121YZF_0603

4700P_0402_16V7K

20P_0402_50V8

R1074

100K_0402_1%

L508 MBK1608121YZF_0603

1 2 PM@

PM@

C1158

L510

PM@L510

PM@

1 2

MBK1608121YZF_0603

1

PM@

C1168

2

0.1U_0402_16V4Z

1

A0

2

A1

3

A2

4

GND

12

AT24C16AN-10SU-2.7_SO8

PM@

VGA_DDCCLK<26>

VGA_DDCDATA<26>

VGA_LVDS_SCL<25>

VGA_LVDS_SDA<25>

12P_0402_50V8J

5

1U_0603_10V4Z

PM@

C1164

4 1

27MHZ_16PF_X7T027000BG1H-V

VCC

WP SCL SDA

PM@

C1155

1U_0603_10V4Z

PM@

1

C1159

0.1U_0402_16V4Z

UNDER GPU

2

GND IN

PM@

1

PM@

C1121

2

U51

8 7 6 5

1

C247

PM@

2

12P_0402_50V8J

1U_0603_10V4Z

PM@

C1165

0.1U_0402_16V4Z

Y9

OUT

GND

R1072

10K_0402_5%

1

C246

PM@

12P_0402_50V8J

2

3 2

2.2K_0402_5%

PM@

C1156

1

2

@

+SP_PLLVDD+VCCP

1

C245

2

PM@

C1157

NEAR GPU

1U_0603_10V4Z

4700P_0402_16V7K

PM@

C1166

XTALIN

XTALOUT

1

PM@

C1167

C1167 20P_0402_50V8

20P_0402_50V8

2

12

PM@

R1071

2.2K_0402_5%

@

R1073

1

PM@

2

12P_0402_50V8J

C244

PM@

+3VS

PM@

R1070

2.2K_0402_5%

HDCP_I2CH_SCL HDCP_I2CH_SDA

PM@

PM@ PM@

PM@

2.2K_0402_5%

+3VS

PCIE_MTX_C_GRX_N[0..15]<10> PCIE_MTX_C_GRX_P[0..15]<10>

PCIE_GTX_C_MRX_N[0..15]<10> PCIE_GTX_C_MRX_P[0..15]<10>

PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_P15 PCIE_GTX_C_MRX_N15

L517MBK1608121YZF_0603

12

L518MBK1608121YZF_0603

12

L519MBK1608121YZF_0603

12

L520MBK1608121YZF_0603

12

R110

PM@

4

PLT_RST#<8,27,31,32>

PULL UP BY EC SIDE

+3VS

VGA_DDCCLK_C

VGA_DDCDATA_C

VGA_LVDS_SCL_C VGA_LVDS_SDA_C

R109

2.2K_0402_5%

PM@

4

PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_C_GRX_P[0..15] PCIE_GTX_C_MRX_N[0..15] PCIE_GTX_C_MRX_P[0..15]

C226 0.1U_0402_16V7KPM@C226 0.1U_0402_16V7KPM@

1 2

C227 0.1U_0402_16V7KPM@C227 0.1U_0402_16V7KPM@

1 2

C228 0.1U_0402_16V7KPM@C228 0.1U_0402_16V7KPM@

1 2

C230 0.1U_0402_16V7KPM@C230 0.1U_0402_16V7KPM@

1 2

C231 0.1U_0402_16V7KPM@C231 0.1U_0402_16V7KPM@

1 2

C232 0.1U_0402_16V7KPM@C232 0.1U_0402_16V7KPM@

1 2

C233 0.1U_0402_16V7KPM@C233 0.1U_0402_16V7KPM@

1 2

C234 0.1U_0402_16V7KPM@C234 0.1U_0402_16V7KPM@

1 2

C235 0.1U_0402_16V7KPM@C235 0.1U_0402_16V7KPM@

1 2

C236 0.1U_0402_16V7KPM@C236 0.1U_0402_16V7KPM@

1 2

C237 0.1U_0402_16V7KPM@C237 0.1U_0402_16V7KPM@

1 2

C238 0.1U_0402_16V7KPM@C238 0.1U_0402_16V7KPM@

1 2

C239 0.1U_0402_16V7KPM@C239 0.1U_0402_16V7KPM@

1 2

C240 0.1U_0402_16V7KPM@C240 0.1U_0402_16V7KPM@

1 2

C241 0.1U_0402_16V7KPM@C241 0.1U_0402_16V7KPM@

1 2

C242 0.1U_0402_16V7KPM@C242 0.1U_0402_16V7KPM@

1 2

C243 0.1U_0402_16V7KPM@C243 0.1U_0402_16V7KPM@

1 2

C248 0.1U_0402_16V7KPM@C248 0.1U_0402_16V7KPM@

1 2

C249 0.1U_0402_16V7KPM@C249 0.1U_0402_16V7KPM@

1 2

C250 0.1U_0402_16V7KPM@C250 0.1U_0402_16V7KPM@

1 2

C251 0.1U_0402_16V7KPM@C251 0.1U_0402_16V7KPM@

1 2

C252 0.1U_0402_16V7KPM@C252 0.1U_0402_16V7KPM@

1 2

C253 0.1U_0402_16V7KPM@C253 0.1U_0402_16V7KPM@

1 2

C254 0.1U_0402_16V7KPM@C254 0.1U_0402_16V7KPM@

1 2

PM@

C255 0.1U_0402_16V7K

1 2

C256 0.1U_0402_16V7K

PM@

1 2

C257 0.1U_0402_16V7KPM@C257 0.1U_0402_16V7KPM@

1 2

C258 0.1U_0402_16V7KPM@C258 0.1U_0402_16V7KPM@

1 2

C259 0.1U_0402_16V7KPM@C259 0.1U_0402_16V7KPM@

1 2

C260 0.1U_0402_16V7KPM@C260 0.1U_0402_16V7KPM@

1 2

C262 0.1U_0402_16V7KPM@C262 0.1U_0402_16V7KPM@

1 2

C263 0.1U_0402_16V7KPM@C263 0.1U_0402_16V7KPM@

1 2

+3VS

PLT_RST#

12

R1085

10K_0402_5%

@

R1092 2.2K_0402_5%PM@R1092 2.2K_0402_5%PM@

PM@

R1091 2.2K_0402_5%

PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N15

PCIE_GTX_MRX_P0 PCIE_GTX_MRX_N0 PCIE_GTX_MRX_P1 PCIE_GTX_MRX_N1 PCIE_GTX_MRX_P2 PCIE_GTX_MRX_N2 PCIE_GTX_MRX_P3 PCIE_GTX_MRX_N3 PCIE_GTX_MRX_P4 PCIE_GTX_MRX_N4 PCIE_GTX_MRX_P5 PCIE_GTX_MRX_N5 PCIE_GTX_MRX_P6 PCIE_GTX_MRX_N6 PCIE_GTX_MRX_P7 PCIE_GTX_MRX_N7 PCIE_GTX_MRX_P8 PCIE_GTX_MRX_N8 PCIE_GTX_MRX_P9 PCIE_GTX_MRX_N9 PCIE_GTX_MRX_P10 PCIE_GTX_MRX_N10 PCIE_GTX_MRX_P11 PCIE_GTX_MRX_N11 PCIE_GTX_MRX_P12 PCIE_GTX_MRX_N12 PCIE_GTX_MRX_P13 PCIE_GTX_MRX_N13 PCIE_GTX_MRX_P14 PCIE_GTX_MRX_N14 PCIE_GTX_MRX_P15 PCIE_GTX_MRX_N15

CLK_PCIE_VGA<23> CLK_PCIE_VGA#<23>

10K_0402_5% PM@

+PLLVDD

EC_SMB_CK2<5,38,42> EC_SMB_DA2<5,38,42>

PULL UP BY VGA SIDE

PULL UP BY RGB SIDE

3

U50A

AP17

PEX_RX0

AN17

PEX_RX0_N

AN19

PEX_RX1

AP19

PEX_RX1_N

AR19

PEX_RX2

AR20

PEX_RX2_N

AP20

PEX_RX3

AN20

PEX_RX3_N

AN22

PEX_RX4

AP22

PEX_RX4_N

AR22

PEX_RX5

AR23

PEX_RX5_N

AP23

PEX_RX6

AN23

PEX_RX6_N

AN25

PEX_RX7

AP25

PEX_RX7_N

AR25

PEX_RX8

AR26

PEX_RX8_N

AP26

PEX_RX9

AN26

PEX_RX9_N

AN28

PEX_RX10

AP28

PEX_RX10_N

AR28

PEX_RX11

AR29

PEX_RX11_N

AP29

PEX_RX12

AN29

PEX_RX12_N

AN31

PEX_RX13

AP31

PEX_RX13_N

AR31

PEX_RX14

AR32

PEX_RX14_N

AR34

PEX_RX15

AP34

PEX_RX15_N

AL17

PEX_TX0

AM17

PEX_TX0_N

AM18

PEX_TX1

AM19

PEX_TX1_N

AL19

PEX_TX2

AK19

PEX_TX2_N

AL20

PEX_TX3

AM20

PEX_TX3_N

AM21

PEX_TX4

AM22

PEX_TX4_N

AL22

PEX_TX5

AK22

PEX_TX5_N

AL23

PEX_TX6

AM23

PEX_TX6_N

AM24

PEX_TX7

AM25

PEX_TX7_N

AL25

PEX_TX8

AK25

PEX_TX8_N

AL26

PEX_TX9

AM26

PEX_TX9_N

AM27

PEX_TX10

AM28

PEX_TX10_N

AL28

PEX_TX11

AK28

PEX_TX11_N

AK29

PEX_TX12

AL29

PEX_TX12_N

AM29

PEX_TX13

AM30

PEX_TX13_N

AM31

PEX_TX14

AM32

PEX_TX14_N

AN32

PEX_TX15

AP32

PEX_TX15_N

AR16

PEX_REFCLK

AR17

PEX_REFCLK_N

R1079

12

EC_SMB_CK2 EC_SMB_DA2

AR13

PEX_CLKREQ_N

AJ17

PEX_TSTCLK_OUT

AJ18

PEX_TSTCLK_OUT_N

AM16

PEX_RST_N

AG21

PEX_TERMP

AE9

PLLVDD

AF9

SP_PLLVDD

AD9

VID_PLLVDD

B1

XTAL_IN

B2

XTAL_OUT

D1

XTAL_OUTBUFF

D2

XTAL_SSIN

E2

I2CS_SCL

E1

I2CS_SDA

E3

I2CC_SCL

E4

I2CC_SDA

G3

I2CB_SCL

G2

I2CB_SDA

G1

I2CA_SCL

G4

I2CA_SDA

F6

I2CH_SCL

G6

I2CH_SDA

N10P-GS-A1_BGA969

10M@

12

1 2

R1082 200_0402_5%@R1082 200_0402_5%@

R1084 2.49K_0402_1%PM@R1084 2.49K_0402_1%PM@

+SP_PLLVDD

XTALIN XTALOUT VGA_CRT_R

XTAL_OUTBUFF XTAL_SSIN

VGA_LVDS_SCL_C VGA_LVDS_SDA_C

VGA_HDMI_SCL_R VGA_HDMI_SDA_R

VGA_DDCCLK_C VGA_DDCDATA_C

HDCP_I2CH_SCL HDCP_I2CH_SDA

60mA

45mA 45mA

Part 1 of 7

PCI EXPRESS

CLK

I2C

GPIO

DVO

MIOA_HSYNC MIOA_VSYNC

MIOB_HSYNC MIOB_VSYNC

MIOA_CTL3 MIOA_VREF

MIOB_CTL3

MIOB_VREF

MIOA_CLKIN

MIOA_CLKOUT

MIOB_CLKIN

MIOB_CLKOUT

MIOA_CLKOUT_N MIOB_CLKOUT_N

MIOACAL_PD_VDDQ

MIOACAL_PU_GND

MIOBCAL_PD_VDDQ

MIOBCAL_PU_GND

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_HSYNC

DACA_VSYNC

DACA_VDD DACA_VREF DACA_RSET

DACB_RED

DACB_GREEN

DACs

DACB_BLUE

DACB_HSYNC

DACB_VSYNC

DACB_VDD DACB_VREF DACB_RSET

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23

MIOA_D0 MIOA_D1 MIOA_D2 MIOA_D3 MIOA_D4 MIOA_D5 MIOA_D6 MIOA_D7 MIOA_D8

MIOA_D9 MIOA_D10 MIOA_D11 MIOA_D12 MIOA_D13 MIOA_D14

MIOB_D0

MIOB_D1

MIOB_D2

MIOB_D3

MIOB_D4

MIOB_D5

MIOB_D6

MIOB_D7

MIOB_D8

MIOB_D9 MIOBD_10 MIOB_D11 MIOB_D12 MIOB_D13 MIOB_D14

MIOA_DE

MIOB_DE

K1 K2 K3 H3 H2 H1 H4 H5 H6 J7 K4 K5 H7 J4 J6 L1 L2 L4 M4 L7 L5 K6 L6 M6

N1 P4 P1 P2 P3 T3 T2 T1 U4 U1 U2 U3 R6 T6 N6

Y1 Y2 Y3 AB3 AB2 AB1 AC4 AC1 AC2 AC3 AE3 AE2 U6 W6 Y6

N3 L3

W1 W2

N2 P5 N5

Y5 W3 AF1

N4 R4

AE1 V4

T4 W4

U5 T5

AA7 AA6

AM15 AM14 AL14

AM13 AL13

AJ12 AK12 AK13

AK4 AL4 AJ4

AM1 AM2

AG7 AK6 AH7

R1068 10K_0402_5%PM@R1068 10K_0402_5%PM@

R1069 10K_0402_5%PM@R1069 10K_0402_5%PM@

@

VGA_CRT_R VGA_CRT_G VGA_CRT_B

VGA_HSYNC VGA_VSYNC

+DACA_VDD DACA_VREF DACA_RSET

PM@

R1093

R1093 124_0402_1%

124_0402_1%

+DACB_VDD DACB_RSET

2

NV_INVTPWM VGA_ENVDD VGA_ENBKL GPU_VID0 GPU_VID1

1 2

PAD

T85

R108110K_0402_5% PM@ R108110K_0402_5% PM@

12

R108310K_0402_5% PM@ R108310K_0402_5% PM@

12

1

PM@

C1163

0.1U_0402_16V4Z

2

R1094 10K_0402_5%PM@R1094 10K_0402_5%PM@ R793 10K_0402_5%

R793 10K_0402_5%

1 2

@

HDMI_DETECT_VGA <24>

PAD

T84

VGA_ENVDD <25>

@

VGA_ENBKL <25>

VGA_CRT_R <26> VGA_CRT_G <26> VGA_CRT_B <26>

VGA_HSYNC <26> VGA_VSYNC <26>

470P_0402_50V7K

1 PM@

PM@

C1160

2

4700P_0402_16V7K

12

GPU_VID1 GPU_VID0 VGA_CORE P-State

+DACA_VDD

1 2

L509MBK1608121YZF_0603

1

2

PM@

C1161

C1162

4.7U_0603_6.3V6M

2

1

External Spread Spectrum

U52

OSC_OUT

1 2 3

ASM3P2872AF-06OR_TSOT-23-6@

U52

REFOUT XOUT XIN/CLKIN

MODOUT

6

VSS

OSC_SPREAD

5 4

VDD

+3VS

1

@

C1147

0.1U_0402_16V4Z

2

If External Spread Spectrum not stuff then stuff resistor

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

3

2008/03/25 2008/04/

Compal Secret Data

Deciphered Date

2

1

GPU_VID0 <49>

12

PM@

R1067

R1067 10K_0402_5%

10K_0402_5%

GPU_VID1 <49>

10K_0402_5%

PM@

R1066

12

GPIO5GPIO6 N10M-GS N10P-GS

0 0 0

CRT OUT

R1086 150_0402_1%PM@R1086 150_0402_1%PM@

VGA_CRT_G

R1087 150_0402_1%PM@R1087 150_0402_1%PM@

VGA_CRT_B

R1088 150_0402_1%PM@R1088 150_0402_1%PM@

+3VS

PM@

OSC_OUT XTAL_OUTBUFF

OSC_SPREAD

Compal Electronics,Ltd.

Title

N10x-GS PCIE,LVDS,GPIO,CLK

Size Document Number Rev

C

Date: Sheet of

Wednesday, March 18, 2009

Date: Sheet of

Wednesday, March 18, 2009

Date: Sheet of

Wednesday, March 18, 2009

1 11

1 2 1 2 1 2

R1075 22_0402_5%@R1075 22_0402_5%@

1 2

R1179 22_0402_5%@R1179 22_0402_5%@

1 2

NIWBA_LA5371P

0.8V

0.85V

0.9V120, 10

12

16

1

16

PM@

R1077

R1077 10K_0402_5%

10K_0402_5%

XTAL_SSIN

PM@

R1178

R1178 10K_0402_5%

10K_0402_5%

0.1

53

5

FBA_CMD[0..30]

FBA_D[0..63]

U50B

D D

C C

+1.5VRAM

B B

1K_0402_5%

R1105

R1109

@

UNDER GPU

10MIL

+FB_VREF

1

C1169

0.01U_0402_16V7K

2

@

+FB_PLLVDD

+1.5VRAM

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

+FB_PLLVDD

+FB_VREF

PM@

1 2

R1110 10K_0402_5%

L32

FBA_D0

N33

FBA_D1

L33

FBA_D2

N34

FBA_D3

N35

FBA_D4

P35

FBA_D5

P33

FBA_D6

P34

FBA_D7

K35

FBA_D8

K33

FBA_D9

K34

FBA_D10

H33

FBA_D11

G34

FBA_D12

G33

FBA_D13

E34

FBA_D14

E33

FBA_D15

G31

FBA_D16

F30

FBA_D17

G30

FBA_D18

G32

FBA_D19

K30

FBA_D20

K32

FBA_D21

H30

FBA_D22

K31

FBA_D23

L31

FBA_D24

L30

FBA_D25

M32

FBA_D26

N30

FBA_D27

M30

FBA_D28

P31

FBA_D29

R32

FBA_D30

R30

FBA_D31

AG30

FBA_D32

AG32

FBA_D33

AH31

FBA_D34

AF31

FBA_D35

AF30

FBA_D36

AE30

FBA_D37

AC32

FBA_D38

AD30

FBA_D39

AN33

FBA_D40

AL31

FBA_D41

AM33

FBA_D42

AL33

FBA_D43

AK30

FBA_D44

AK32

FBA_D45

AJ30

FBA_D46

AH30

FBA_D47

AH33

FBA_D48

AH35

FBA_D49

AH34

FBA_D50

AH32

FBA_D51

AJ33

FBA_D52

AL35

FBA_D53

AM34

FBA_D54

AM35

FBA_D55

AF33

FBA_D56

AE32

FBA_D57

AF34

FBA_D58

AE35

FBA_D59

AE34

FBA_D60

AE33

FBA_D61

AB32

FBA_D62

AC35

FBA_D63

AG27

FB_DLLAVDD

AF27

FB_PLLAVDD

J27

FB_VREF

T30

FBA_DEBUG

N10P-GS-A1_BGA969

10M@

FBA_DQM[0..7]

FBA_DQS[0..7]

FBA_DQS#[0..7]

Part 2 of 7

4

MEMORY INTERFACE

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30

FBA_DQM0

FBA_DQM1

FBA_DQM2

FBA_DQM3

FBA_DQM4

FBA_DQM5

FBA_DQM6

FBA_DQM7

A

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FBA_CLK0_N

FBA_CLK1_N

FBA_CLK0

FBA_CLK1

FBA_CMD[0..30] <21>

FBA_DQM[0..7] <21> FBA_DQS[0..7] <21> FBA_DQS#[0..7] <21> FBA_D[0..63] <21>

V32 W31 U31 Y32 AB35 AB34 W35 W33 W30 T34 T35 AB31 Y30 Y34 W32 AA30 AA32 Y33 U32 Y31 U34 Y35 W34 V30 U35 U30 U33 AB30 AB33 T33 W29

P32 H34 J30 P30 AF32 AL32 AL34 AF35

L35 G35 H31 N32 AD32 AJ31 AJ35 AC34

L34 H35 J32 N31 AE31 AJ32 AJ34 AC33

T32 T31

AC31 AC30

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FBA_DQS#0 FBA_DQS#1 FBA_DQS#2 FBA_DQS#3 FBA_DQS#4 FBA_DQS#5 FBA_DQS#6 FBA_DQS#7

FBA_DQS0 FBA_DQS1 FBA_DQS2 FBA_DQS3 FBA_DQS4 FBA_DQS5 FBA_DQS6 FBA_DQS7

FBA_CLK0 FBA_CLK0#

FBA_CLK1 FBA_CLK1#

3

UPDATE 0216 UPDATE 0216

R1095 10K_0402_5%

FBA_CMD7

R1101 10K_0402_5%

FBA_CMD15

R1096 10K_0402_5%

FBA_CMD18

R1098 10K_0402_5%

FBA_CMD28

R1099 10K_0402_5%

FBA_CMD30

FBA_CLK0 <21> FBA_CLK0# <21>

FBA_CLK1 <21> FBA_CLK1# <21>

PM@

1 2

PM@

1 2

PM@

1 2

PM@

1 2

PM@

1 2

+1.5VRAM

R1106 60.4_0402_1%

R1106 60.4_0402_1% R1107 40.2_0402_1%

R1107 40.2_0402_1% R1108 40.2_0402_1%

R1108 40.2_0402_1%

Place Components Close to BGA

FBC_D0 FBC_D1 FBC_D2 FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7 FBC_D8 FBC_D9 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63

PM@

PM@ PM@

PM@

12 12

U50C

B13

FBC_D0

D13

FBC_D1

A13

FBC_D2

A14

FBC_D3

C16

FBC_D4

B16

FBC_D5

A17

FBC_D6

D16

FBC_D7

C13

FBC_D8

B11

FBC_D9

C11

FBC_D10

A11

FBC_D11

C10

FBC_D12

C8

FBC_D13

B8

FBC_D14

A8

FBC_D15

E8

FBC_D16

F8

FBC_D17

F10

FBC_D18

F9

FBC_D19

F12

FBC_D20

D8

FBC_D21

D11

FBC_D22

E11

FBC_D23

D12

FBC_D24

E13

FBC_D25

F13

FBC_D26

F14

FBC_D27

F15

FBC_D28

E16

FBC_D29

F16

FBC_D30

F17

FBC_D31

D29

FBC_D32

F27

FBC_D33

F28

FBC_D34

E28

FBC_D35

D26

FBC_D36

F25

FBC_D37

D24

FBC_D38

E25

FBC_D39

E32

FBC_D40

F32

FBC_D41

D33

FBC_D42

E31

FBC_D43

C33

FBC_D44

F29

FBC_D45

D30

FBC_D46

E29

FBC_D47

B29

FBC_D48

C31

FBC_D49

C29

FBC_D50

B31

FBC_D51

C32

FBC_D52

B32

FBC_D53

B35

FBC_D54

B34

FBC_D55

A29

FBC_D56

B28

FBC_D57

A28

FBC_D58

C28

FBC_D59

C26

FBC_D60

D25

FBC_D61

B25

FBC_D62

A25

FBC_D63

K27

FBCAL_PD_VDDQ

L27

FBCAL_PU_GND

M27

FBCAL_TERM_GND

N10P-GS-A1_BGA969

10M@

FBC_CMD[0..30]

FBC_DQM[0..7] FBC_DQS[0..7]

FBC_DQS#[0..7]

FBC_D[0..63]

Part 3 of 7

2

MEMORY INTERFACE C

FBC_DQS_RN0 FBC_DQS_RN1 FBC_DQS_RN2 FBC_DQS_RN3 FBC_DQS_RN4 FBC_DQS_RN5 FBC_DQS_RN6 FBC_DQS_RN7

FBC_DQS_WP0 FBC_DQS_WP1 FBC_DQS_WP2 FBC_DQS_WP3 FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6 FBC_DQS_WP7

FBC_CMD[0..30] <22>

FBC_DQM[0..7] <22>

FBC_DQS[0..7] <22> FBC_DQS#[0..7] <22> FBC_D[0..63] <22>

FBC_CMD0 FBC_CMD1 FBC_CMD2 FBC_CMD3 FBC_CMD4 FBC_CMD5 FBC_CMD6 FBC_CMD7 FBC_CMD8

FBC_CMD9 FBC_CMD10 FBC_CMD11 FBC_CMD12 FBC_CMD13 FBC_CMD14 FBC_CMD15 FBC_CMD16 FBC_CMD17 FBC_CMD18 FBC_CMD19 FBC_CMD20 FBC_CMD21 FBC_CMD22 FBC_CMD23 FBC_CMD24 FBC_CMD25 FBC_CMD26 FBC_CMD27 FBC_CMD28 FBC_CMD29 FBC_CMD30

FBC_DQM0

FBC_DQM1

FBC_DQM2

FBC_DQM3

FBC_DQM4

FBC_DQM5

FBC_DQM6

FBC_DQM7

FBC_CLK0

FBC_CLK0_N

FBC_CLK1

FBC_CLK1_N

FBC_DEBUG

FBC_CMD0

C17

FBC_CMD1

B19

FBC_CMD2

D18

FBC_CMD3

F21

FBC_CMD4

A23

FBC_CMD5

D21

FBC_CMD6

B23

FBC_CMD7

E20

FBC_CMD8

G21

FBC_CMD9

F20

FBC_CMD10

F19

FBC_CMD11

F23

FBC_CMD12

A22

FBC_CMD13

C22

FBC_CMD14

B17

FBC_CMD15

F24

FBC_CMD16

C25

FBC_CMD17

E22

FBC_CMD18

C20

FBC_CMD19

B22

FBC_CMD20

A19

FBC_CMD21

D22

FBC_CMD22

D20

FBC_CMD23

E19

FBC_CMD24

D19

FBC_CMD25

F18

FBC_CMD26

C19

FBC_CMD27

F22

FBC_CMD28

C23

FBC_CMD29

B20

FBC_CMD30

A20

FBC_DQM0

A16

FBC_DQM1

D10

FBC_DQM2

F11

FBC_DQM3

D15

FBC_DQM4

D27

FBC_DQM5

D34

FBC_DQM6

A34

FBC_DQM7

D28

FBC_DQS#0

B14

FBC_DQS#1

B10

FBC_DQS#2

D9

FBC_DQS#3

E14

FBC_DQS#4

F26

FBC_DQS#5

D31

FBC_DQS#6

A31

FBC_DQS#7

A26

FBC_DQS0

C14

FBC_DQS1

A10

FBC_DQS2

E10

FBC_DQS3

D14

FBC_DQS4

E26

FBC_DQS5

D32

FBC_DQS6

A32

FBC_DQS7

B26

FBC_CLK0

E17

FBC_CLK0#

D17

FBC_CLK1

D23

FBC_CLK1#

E23

PM@

G19

R1111 10K_0402_5%

R1100 10K_0402_5%

FBC_CMD7

R1102 10K_0402_5%

FBC_CMD15

R1097 10K_0402_5%

FBC_CMD18

R1103 10K_0402_5%

FBC_CMD28

R1104 10K_0402_5%

FBC_CMD30

FBC_CLK0 <22> FBC_CLK0# <22>

FBC_CLK1 <22>

12

FBC_CLK1# <22>

+1.5VRAM

1

1 2

PM@

Memory/PKG

+VCCP +FB_PLLVDD

A A

L511 MBK1608121YZF_0603PM@L511 MBK1608121YZF_0603PM@

1 2

4.7U 6.3V K X5R 0603

5

1

PM@

C1172

1 PM@C1172

PM@

1U_0603_10V4Z

2

C1170

PM@

2

NEAR GPU UNDER GPU

C1171

0.1U_0402_16V4Z

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR3 GDDR3

Must be used 1% resister for driver calibration

2007/10/15 2008/10/15

3

FBVDDQ

FBCAL_PU_GND FBCAL_PD_VDDQ FBCAL_TERM_GND

+1.5VS

+1.8VS

Compal Secret Data

Deciphered Date

40.2 ohm

60.4 ohm

60.4 ohm 40.2 ohm

2

40.2 ohm

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

N10x-GS Memory

NIWBA_LA5371P

1

17 53Wednesday, March 18, 2009

0.1

5

VGA_LVDS_ACLK<25> VGA_LVDS_ACLK#<25> VGA_LVDS_A0<25> VGA_LVDS_A0#<25>

PM@

+3VS

VGA_LVDS_A1<25> VGA_LVDS_A1#<25> VGA_LVDS_A2<25> VGA_LVDS_A2#<25>

VGA_LVDS_BCLK<25> VGA_LVDS_BCLK#<25> VGA_LVDS_B0<25> VGA_LVDS_B0#<25> VGA_LVDS_B1<25> VGA_LVDS_B1#<25> VGA_LVDS_B2<25> VGA_LVDS_B2#<25>

VGA_HDMI_TX2+<24>

VGA_HDMI_TX2-<24>

VGA_HDMI_TX1+<24>

VGA_HDMI_TX1-<24>

VGA_HDMI_TX0+<24>

VGA_HDMI_TX0-<24>

VGA_HDMI_CLK+<24>

VGA_HDMI_CLK-<24>

2

Q63A

4

Q63B

5

D D

C C

VGA_HDMI_SCL<24>

B B

VGA_HDMI_SDA<24>

6 1

2N7002DW-T/R7_SOT363-6

3

5V PULL UP IN CONNECTER SIDE

R1120 10K_0402_5%

PM@

+3VS

HDMI_CEC<24>

1 2

R722 0_0402_5%@R722 0_0402_5%@

12

HDMI_CEC_R

4

12

R1113

4.7K_0402_5%

PM@

12

R1118

4.7K_0402_5%

PM@

PAD

T89

STRAP0<20> STRAP1<20> STRAP2<20>

VGA_LVDS_ACLK VGA_LVDS_ACLK# VGA_LVDS_A0 VGA_LVDS_A0# VGA_LVDS_A1 VGA_LVDS_A1# VGA_LVDS_A2 VGA_LVDS_A2#

VGA_LVDS_BCLK VGA_LVDS_BCLK# VGA_LVDS_B0 VGA_LVDS_B0# VGA_LVDS_B1 VGA_LVDS_B1# VGA_LVDS_B2 VGA_LVDS_B2#

VGA_HDMI_TX2+ VGA_HDMI_TX2VGA_HDMI_TX1+ VGA_HDMI_TX1VGA_HDMI_TX0+ VGA_HDMI_TX0VGA_HDMI_CLK+ VGA_HDMI_CLK-

IFPC_AUX IFPC_AUX_N

STRAP0 STRAP1 STRAP2

U50D

AM11

IFPA_TXC

AM12

IFPA_TXC_N

AM8

IFPA_TXD0

AL8

IFPA_TXD0_N

AM10

IFPA_TXD1

AM9

IFPA_TXD1_N

AK10

IFPA_TXD2

AL10

IFPA_TXD2_N

AK11

IFPA_TXD3

AL11

IFPA_TXD3_N

AP13

IFPB_TXC

AN13

IFPB_TXC_N

AN8

IFPB_TXD4

AP8

IFPB_TXD4_N

AP10

IFPB_TXD5

AN10

IFPB_TXD5_N

AR11

IFPB_TXD6

AR10

IFPB_TXD6_N

AN11

IFPB_TXD7

AP11

IFPB_TXD7_N

AM7

IFPC_L0

AM6

IFPC_L0_N

AL5

IFPC_L1

AM5

IFPC_L1_N

AM3

IFPC_L2

AM4

IFPC_L2_N

AP1

IFPC_L3

AR2

IFPC_L3_N

AR8

IFPD_L0

AR7

IFPD_L0_N

AP7

IFPD_L1

AN7

IFPD_L1_N

AN5

IFPD_L2

AP5

IFPD_L2_N

AR5

IFPD_L3

AR4

IFPD_L3_N

AH6

IFPE_L0

AH5

IFPE_L0_N

AH4

IFPE_L1

AG4

IFPE_L1_N

AF4

IFPE_L2

AF5

IFPE_L2_N

AE6

IFPE_L3

AE5

IFPE_L3_N

AL2

IFPF_L0

AL3

IFPF_L0_N

AJ3

IFPF_L1

AJ2

IFPF_L1_N

AJ1

IFPF_L2

AH1

IFPF_L2_N

AH2

IFPF_L3

AH3

IFPF_L3_N

AP2

IFPC_AUX_I2CW_SCL

AN3

IFPC_AUX_I2CW_SDA_N

AP4

IFPD_AUX_I2CX_SCL

AN4

IFPD_AUX_I2CX_SDA_N

AE4

IFPE_AUX_I2CY_SCL

AD4

IFPE_AUX_I2CY_SDA_N

AF3

IFPF_AUX_I2CZ_SCL

AF2

IFPF_AUX_I2CZ_SDA_N

A4

BUFRST_N

AB5

CEC

W5

STRAP0

W7

STRAP1

V7

STRAP2

3

Part 4 of 7

LVDS/TMDS

GENERAL

MULTI_STRAP_REF0_GND MULTI_STRAP_REF1_GND

NC_0 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8

NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26

NC

NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42 NC_43 NC_44 NC_45 NC_46 NC_47 NC_48

VDD_SENSE_0 VDD_SENSE_1 VDD_SENSE_2

GND_SENSE_0 GND_SENSE_1 GND_SENSE_2

TEST

TESTMODE

JTAG_TCK

JTAG_TDI JTAG_TDO JTAG_TMS

JTAG_TRST_N

SERIAL

ROM_CS_N

ROM_SI

ROM_SO

ROM_SCLK

NC/SPDIF

THERMDP THERMDN

A2 A7 B7 C5 C7 D5 D6 D7 E5 E7 F4 G5 G11 G12 G14 G15 G27 G28 G24 G25 H32 J18 J19 J25 J26 L29 M7 M29 P6 P29 R29 U7 V6 Y4 AA4 AB4 AB7 AC5 AD6 AD29 AE29 AF6 AG6 AG20 AG29 AH29 AJ5 AK15 AL7

D35 P7 AD20

AD19 E35 R7

TESTMODE

AP35

JTAG_TCK

AP14 AN14

JTAG_TDO

AN16 AR14

JTAG_TRST_N

AP16

C3 D3 C4 D4

SPDIF_IN

A5 N9

R1119 40.2K_0402_1%

M9

R1121 40.2K_0402_1%

B5

PAD

B4

PAD

PM@

1 2

R1112 0_0402_5%

PM@

1 2

R1114 0_0402_5%

ROM_SI ROM_SO ROM_SCLK

PM@

1 2

PM@

1 2

T90

T90 T91

T91

PAD

1K_0402_5%PM@

1K_0402_5%PM@ R1116

R1116

PAD

PAD PAD

PAD

ROM_SI <20> ROM_SO <20> ROM_SCLK <20>

T88

2

+VGASENSE <49>

+3VS

12

@

R1115

R1115 10K_0402_5%

10K_0402_5%

T86

12

T87

PM@

R1117

R1117 10K_0402_5%

10K_0402_5%

1

N10P-GS-A1_BGA969

10M@

A A

5

4

10M@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

N10P/N10M LVDS,HDMI

Size Document Number Rev

Custom

Date: Sheet of

NIWBA_LA5371P

1

18 53Wednesday, March 18, 2009

0.1

5

+VGA_CORE

PM@

C1181

C1181 4700P_0402_16V7K

4700P_0402_16V7K

PM@

C1184

0.01U_0402_16V7K

PM@

L512MBK1608121YZF_0603

0.01U_0402_16V7K

C1185

C1185 .022U_0402_16V7

.022U_0402_16V7

PM@

C1190

0.22U_0603_10V7K

1

PM@

C1193

2

1U_0603_10V4Z

D D

+VCCP

C C

1 2

4.7U 6.3V K X5R 0603

PM@

C1194

PM@

C1176

0.01U_0402_16V7K

C1186

C1186 .022U_0402_16V7

.022U_0402_16V7

PM@

C1191

0.22U_0603_10V7K

0.1U_0402_16V4Z

C1195

PM@

C1174

C1174 .015U_0402_16V7K

.015U_0402_16V7K

PM@

C1177

0.01U_0402_16V7K

C1187

C1187 .022U_0402_16V7

.022U_0402_16V7

1

PM@

C1192

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

C1196

PM@

4

PM@

C1182

C1182 .015U_0402_16V7K

.015U_0402_16V7K

PM@

C1178

0.01U_0402_16V7K

C1188

C1188 .022U_0402_16V7

.022U_0402_16V7

UNDER GPU

1

4700P_0402_25V7K

2

PM@

C1197

PM@

C1175

C1175 .022U_0402_16V7

.022U_0402_16V7

PM@

C1179

0.01U_0402_16V7K

PM@

C1189

0.1U_0402_10V7K

220mA

+IFPAB_PLLVDD

1

2

PM@

C1183

C1183 .022U_0402_16V7

.022U_0402_16V7

PM@

C1180

0.01U_0402_16V7K

AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB25 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AD12 AD14 AD16 AD18 AD22 AD24

3

U50G

VDD_0

Part 7 of 7

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5

22.28A

VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28

L11

VDD_29

L12

VDD_30

L13

VDD_31

L14

VDD_32

L15

VDD_33

L16

VDD_34

L17

VDD_35

L18

VDD_36

L19

VDD_37

L20

VDD_38

L21

VDD_39

L22

VDD_40

L23

VDD_41

L24

VDD_42

L25

VDD_43

M12

VDD_44

M14

VDD_45

M16

VDD_46

M18

VDD_47

M20

VDD_48

M22

VDD_49

M24

VDD_50

P11

VDD_51

P13

VDD_52

P15

VDD_53

P17

VDD_54

P19

VDD_55

POWER

VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71 VDD_72 VDD_73 VDD_74 VDD_75 VDD_76 VDD_77 VDD_78 VDD_79 VDD_80 VDD_81 VDD_82 VDD_83 VDD_84 VDD_85 VDD_86 VDD_87 VDD_88 VDD_89 VDD_90 VDD_91 VDD_92 VDD_93 VDD_94 VDD_95 VDD_96 VDD_97 VDD_98

VDD_99 VDD_100 VDD_101 VDD_102 VDD_103 VDD_104 VDD_105 VDD_106 VDD_107 VDD_108 VDD_109 VDD_110

P21 P23 P25 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 T12 T14 T16 T18 T20 T22 T24 V11 V13 V15 V17 V19 V21 V23 V25 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 Y12 Y14 Y16 Y18 Y20 Y22 Y24

+VGA_CORE

1

PM@

C1198

0.1U_0402_16V4Z

2

1

PM@

C1199

0.1U_0402_16V4Z

2

1

PM@

C1200

0.1U_0402_16V4Z

2

UNDER GPU (0-150 Mil)

1

PM@

C1201

0.1U_0402_16V4Z

2

PM@

C1202

C1202 1U_0402_6.3V6K

1U_0402_6.3V6K

1

PM@

C1203

C1203 1U_0402_6.3V6K

1U_0402_6.3V6K

+VCCP

220mA

+3VS

L513

PM@ L513

PM@ 1 2

MBK1608121YZF_0603

4.7U 6.3V K X5R 0603

PM@

C1210

1

1U_0603_10V4Z

2

PM@

C1213

1U_0603_10V4Z

PM@

C1214

PM@

C1211

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

PM@

C1215

1

0.1U_0402_16V4Z

2

PM@

C1216

+IFPD_PLLVDD

+IFPC_PLLVDD

1

220mA

2

+1.5VRAM

150mA

C1229

PM@

C1219

PM@

+IFPA_IOVDD +IFPB_IOVDD

1

150mA

2

285mA

+IFPC_IOVDD +IFPD_IOVDD

1

285mA

2

1 2

R1122 1K_0402_5%@R1122 1K_0402_5%@

PM@

12

R1123 1K_0402_5%

10K_0402_5%

12

@

10K_0402_5%

PM@ R1124

PM@

12

10K_0402_5%

PM@ R1125

PM@

12

PM@ R1126

PM@

12

10K_0402_5%

R1180

R1124

R1125 R1126

+IFPAB_PLLVDD +IFPAB_RSET

+IFPA_IOVDD +IFPB_IOVDD

+IFPC_PLLVDD

+IFPC_RSET

+IFPC_IOVDD

+IFPD_PLLVDD +IFPD_RSET

+IFPD_IOVDD

+IFPEF_PLLVDD

+IFPE_IOVDD +IFPF_IOVDD

PM@

+1.8VS

MBK1608121YZF_0603

B B

A A

+VCCP

+1.5VRAM

MBK1608121YZF_0603

UNDER GPU

PM@

C1237

0.01U_0402_16V7K

1

PM@

C1241

0.1U_0402_16V4Z

2

1 2

L514

4.7U 6.3V K X5R 0603

PM@

1 2

L516

4.7U 6.3V K X5R 0603

PM@

C1238

0.01U_0402_16V7K

1

PM@

C1242

0.1U_0402_16V4Z

2

5

PM@

C1212

1

PM@

C1226

2

PM@

C1239

0.01U_0402_16V7K

1

PM@

C1243

0.1U_0402_16V4Z

2

1

1U_0603_10V4Z

2

1U_0603_10V4Z

PM@

C1217

PM@

C1227

PM@

C1240

0.01U_0402_16V7K

0.1U_0402_16V4Z

C1218

C1228

PM@

1

4700P_0402_25V7K

2

1

0.1U_0402_16V4Z

2

4

N10P-GS-A1_BGA969

N10P-GS-A1_BGA969 U50E

U50E

J23

FBVDDQ_0

J24

FBVDDQ_1

J29

FBVDDQ_2

AA27

FBVDDQ_3

AA29

FBVDDQ_4

AA31

FBVDDQ_5

AB27

FBVDDQ_6

AB29

FBVDDQ_7

AC27

FBVDDQ_8

AD27

FBVDDQ_9

AE27

FBVDDQ_10

AJ28

FBVDDQ_11

B18

FBVDDQ_12

E21

FBVDDQ_13

G17

FBVDDQ_14

G18

FBVDDQ_15

G22

FBVDDQ_16

G8

FBVDDQ_17

G9

FBVDDQ_18

H29

FBVDDQ_19

J14

FBVDDQ_20

J15

FBVDDQ_21

J16

FBVDDQ_22

J17

FBVDDQ_23

J20

FBVDDQ_24

J21

FBVDDQ_25

J22

FBVDDQ_26

N27

FBVDDQ_27

P27

FBVDDQ_28

R27

FBVDDQ_29

T27

FBVDDQ_30

U27

FBVDDQ_31

U29

FBVDDQ_32

V27

FBVDDQ_33

V29

FBVDDQ_34

V34

FBVDDQ_35

W27

FBVDDQ_36

Y27

FBVDDQ_37

AK9

IFPAB_PLLVDD

AJ11

IFPAB_RSET

AG9

IFPA_IOVDD

AG10

IFPB_IOVDD

AJ9

IFPC_PLLVDD

AK7

IFPC_RSET

AJ8

IFPC_IOVDD

AC6

IFPD_PLLVDD

AB6

IFPD_RSET

AK8

IFPD_IOVDD

AJ6

IFPEF_PLLVDD

AL1

IFPEF_RSET

AE7

IFPE_IOVDD

AD7

IFPF_IOVDD

Part 5 of 7

N10P-GS-A1_BGA969

3

10M@

2A

PEX_IOVDDQ_0 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8

PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14 PEX_IOVDDQ_15 PEX_IOVDDQ_16 PEX_IOVDDQ_17 PEX_IOVDDQ_18 PEX_IOVDDQ_19 PEX_IOVDDQ_20 PEX_IOVDDQ_21 PEX_IOVDDQ_22 PEX_IOVDDQ_23 PEX_IOVDDQ_24

POWER

PEX_SVDD_3V3_0 PEX_SVDD_3V3_1

AG11 AG12 AG13 AG15 AG16 AG17 AG18 AG22 AG23 AG24 AG25 AG26 AJ14 AJ15 AJ19 AJ21 AJ22 AJ24 AJ25 AJ27 AK18 AK20 AK23 AK26 AL16

AK16

PEX_IOVDD_0

AK17

PEX_IOVDD_1

AK21

PEX_IOVDD_2

AK24

PEX_IOVDD_3

AK27

PEX_IOVDD_4

150mA

AG14

PEX_PLLVDD

VDD33_0 VDD33_1 VDD33_2 VDD33_3 VDD33_4

MIOA_VDDQ_0 MIOA_VDDQ_1 MIOA_VDDQ_2 MIOA_VDDQ_3

MIOB_VDDQ_0 MIOB_VDDQ_1 MIOB_VDDQ_2 MIOB_VDDQ_3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

10M@

AG19 F7

J10 J11 J12 J13 J9

P9 R9 T9 U9

AA9 AB9 W9 Y9

120mA

PM@

C1244

0.1U_0402_10V7K

1

PM@

C1204

C1204 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

PM@

C1220

0.1U_0402_16V4Z

2

PM@

C1233

0.1U_0402_10V7K

+3VS

PM@

C1245

0.1U_0402_10V7K

2007/10/15 2008/10/15

1

PM@

C1205

C1205 10U_0603_6.3V6M

10U_0603_6.3V6M

2

PM@

C1221

C1221 1U_0402_6.3V6K

1U_0402_6.3V6K

UNDER GPU

PM@

C1234

0.1U_0402_10V7K

Compal Secret Data

Deciphered Date

PM@

C1230

0.01U_0402_16V7K

UNDER GPU

PM@

C1235

C1235 1U_0603_10V4Z

1U_0603_10V4Z

NEAR GPUUNDER GPU

2

1

PM@

C1206

C1206 10U_0603_6.3V6M

10U_0603_6.3V6M

2

PM@

C1222

C1222 1U_0603_10V4Z

1U_0603_10V4Z

1

2

NEAR GPU (0-750 Mil)

PM@

C1223

C1223 1U_0603_10V4Z

1U_0603_10V4Z

PM@

C1231

0.1U_0402_10V7K

NEAR GPU

+3VS

PM@

C1236

C1236 1U_0603_10V4Z

1U_0603_10V4Z

PM@

C1207

C1207 10U_0603_6.3V6M

10U_0603_6.3V6M

1

PM@

C1208

C1208 10U_0603_6.3V6M

10U_0603_6.3V6M

2

PM@

C1224

C1224 1U_0603_10V4Z

1U_0603_10V4Z

1

PM@

C1209

C1209 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

PM@

C1225

4.7U 6.3V K X5R 0603

2

PM@

L515

NEAR GPU

+3VS

PM@

C1232

C1232 1U_0603_10V4Z

1U_0603_10V4Z

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

N10x-GS POWER

NIWBA_LA5371P

1

12

MBK1608121YZF_0603

19 53Wednesday, April 22, 2009

+VCCP

0.1

5

U50F

Part 6 of 7

B3

GND_0

B6

GND_1

B9

GND_2

B12

GND_3

B15

GND_4

B21

GND_5

B24

GND_6

B27

GND_7

B30

GND_8

B33

GND_9

D D

C C

B B

A A

C34

E12 E15 E18 E24 E27 E30

M11 M13 M15 M17 M19 M21 M23 M25 M31 M34 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 P12 P14 P16 P18 P20 P22 P24

R31 R34

U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25

V12 V14 V16

C2

GND_10 GND_11

E6

GND_12

E9

GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19

F2

GND_20

F31

GND_21

F34

GND_22

F5

GND_23

J2

GND_24

J5

GND_25

J31

GND_26

J34

GND_27

K9

GND_28

L9

GND_29

M2

GND_30

M5

GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63

R2

GND_64

R5

GND_65 GND_66 GND_67

T11

GND_68

T13

GND_69

T15

GND_70

T17

GND_71

T19

GND_72

T21

GND_73

T23

GND_74

T25

GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90

V2

GND_91

V5

GND_92

V9

GND_93 GND_94 GND_95 GND_96

Part 6 of 7

GND

GND_97 GND_98

GND_99 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192

V18 V20 V22 V24 V31 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25 AA2 AA5 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA34 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AC9 AD2 AD5 AD11 AD13 AD15 AD17 AD21 AD23 AD25 AD31 AD34 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AG2 AG5 AG31 AG34 AK2 AK5 AK14 AK31 AK34 AL6 AL9 AL12 AL15 AL18 AL21 AL24 AL27 AL30 AN2 AN34 AP3 AP6 AP9 AP12 AP15 AP18 AP21 AP24 AP27 AP30 AP33

4

STRAP2<18> STRAP1<18> STRAP0<18> ROM_SCLK<18>

ROM_SI<18>

ROM_SO<18>

X2

S1024@

X76_S1024

X3

H1024@

X76_H1024

X4

S512@

X76_S512

X5

H512@

X76_H512

U50

N10P-GS

10P@

GB1 Family GPU Strap Qptions

STRAP2 STRAP1 STRAP0 ROM_SCLK ROM_SI ROM_SO

N10P-GS

(0xA74)

3

+3VS

12

PM@

R1127

R1127 10K_0402_1%

10K_0402_1%

12

@

R1133

R1133 10K_0402_1%

10K_0402_1%

(0xA34)

N10M-GS

2

12

@

R1128

R1128 10K_0402_1%

10K_0402_1%

12

PM@

R1134

R1134 10K_0402_1%

10K_0402_1%

Samsung

Hynix PD 15K

Samsung PD 20K

Hynix PD 15K

12

PM@

R1129

45.3K_0402_1%

12

@

R1135

R1135 10K_0402_1%

10K_0402_1%

12

@

R1130

R1130 15K_0402_1%

15K_0402_1%

12

PM@

R1136

R1136 15K_0402_1%

15K_0402_1%

ROM_SO

64Mx16 PD 15K

64Mx16

PD 10K

ROM_SO

64Mx16

PD 10K

12

@

R1131

R1131 2K_0402_5%

2K_0402_5%

12

X76@

R1137

R1137 20K_0402_1%

20K_0402_1%

ROM_SCLK STRAP2GPU ROM_SI

PD 15K

ROM_SCLK STRAP2GPU ROM_SI

PD 15K

12

@

R1132

4.99K_0402_1%

12

PM@

R1138

R1138 10K_0402_1%

10K_0402_1%

PD 20K

GPU DEVIDRAM_CFGGPU DEVID

PU 10K

PD 10K

1

STRAP0STRAP1FB Memory

PU 45K

STRAP0STRAP1FB Memory

PU 45K

N10P-GS-A1_BGA969

10M@

5

Security Classification

2008/03/25 2008/04/

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/25 2008/04/

3

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

N10x-GS GND & STRAP

Size Document Number Rev

Custom

Custom Date: Sheet of

Wednesday, March 18, 2009

Date: Sheet of

Wednesday, March 18, 2009

Date: Sheet of

2

Wednesday, March 18, 2009

NIWBA_LA5371P

1

20

0.1

53

5

N10x 40nm DDR3 MAPPING NVIDIA COCUMENT FOR DA-3978-001

PM@

R1139

R1139 243_0402_1%

243_0402_1%

1 2

12

PM@

R1144

R1144 243_0402_1%

243_0402_1%

FBA_CMD[0..30] FBA_DQM[0..7] FBA_DQS[0..7] FBA_DQS#[0..7] FBA_D[0..63]

FBA_CLK0#<17> FBA_CLK1#<17>

PM@

R1140

R1140 240_0402_1%

240_0402_1%

FBA_CMD[0..30]<17>

FBA_DQM[0..7]<17>

FBA_DQS[0..7]<17>

FBA_DQS#[0..7]<17>

D D

C C

FBA_D[0..63]<17>

FBA_CLK0

FBA_CLK0#

FBA_CLK1

FBA_CLK1#

VREFD_Q1 FBA_CMD19

FBA_CMD25 FBA_CMD22 FBA_CMD24 FBA_CMD0 FBA_CMD2 FBA_CMD21 FBA_CMD16 FBA_CMD23 FBA_CMD20 FBA_CMD17 FBA_CMD9 FBA_CMD14 FBA_CMD26

FBA_CMD12 FBA_CMD3 FBA_CMD27

FBA_CMD18

FBA_CMD30 FBA_CMD29 FBA_CMD1 FBA_CMD10 FBA_CMD11

FBA_DQS0 FBA_DQS1

FBA_DQM0 FBA_DQM1

FBA_DQS#0 FBA_DQS#1

FBA_CMD15

12

M9 H2

N4 P8 P4 N3 P9 P3 R9 R3 T9 R4

L8 R8 N8 T4 T8 M8

M3 N9 M4

J8 K8

K10

K2

L3

J4 K4

L4

F4 C8

E8 D4

G4 B8

T3

L9

J2

L2

J10 L10

A1

A11

T1

T11

4

U54

DQL0

VREFCA

DQL1

VREFDQ

DQL2 DQL3

A0

DQL4

A1 A2

DQL5

A3

DQL6

A4

DQL7 A5 A6 A7

DQU0

A8

DQU1

A9

DQU2

A10/AP

DQU3

A11

DQU4

A12

DQU5 DQU6

A13

DQU7

A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

NC NC NC NC

K4B1G1646D-HCF8_FBGA100

@

100-BALL

100-BALL SDRAM DDR3

SDRAM DDR3

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

3

U55

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

100-BALL

100-BALL SDRAM DDR3

SDRAM DDR3

K4B1G1646D-HCF8_FBGA100

@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

+1.5VRAM

PM@

R1142

R1142 240_0402_1%

240_0402_1%

VREFC_A3 VREFD_Q3

FBA_CMD19 FBA_CMD25 FBA_CMD4 FBA_CMD6 FBA_CMD5 FBA_CMD13 FBA_CMD21 FBA_CMD16 FBA_CMD23 FBA_CMD20 FBA_CMD17 FBA_CMD9 FBA_CMD14 FBA_CMD26

FBA_CMD12 FBA_CMD3 FBA_CMD27

FBA_CLK1<17>FBA_CLK0<17>

FBA_CMD7 FBA_CMD28

FBA_CMD8 FBA_CMD1 FBA_CMD10 FBA_CMD11

FBA_DQS4 FBA_DQS5

FBA_DQM4 FBA_DQM5

FBA_DQS#4 FBA_DQS#5

FBA_CMD15

12

FBA_D19

E4

FBA_D22

F8

FBA_D18

F3

FBA_D23

F9

FBA_D17

H4

FBA_D21

H9

FBA_D16

G3

FBA_D20

H8

FBA_D31

D8

FBA_D28

C4

FBA_D29

C9

FBA_D25

C3

FBA_D27

A8

FBA_D24

A3

FBA_D30

B9

FBA_D26

A4

B3

VDD

D10

VDD

G8

VDD

K3

VDD

K9

VDD

N2

VDD

N10

VDD

R2

VDD

R10

VDD

+1.5VRAM

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10

VSS

B4

VSS

E2

VSS

G9

VSS

J3

VSS

J9

VSS

M2

VSS

M10

VSS

P2

VSS

P10

VSS

T2

VSS

T10

VSS

B2 B10 D2 D9 E3 E9 F10 G2 G10

PM@

R1141

R1141 240_0402_1%

240_0402_1%

VREFC_A2 VREFD_Q2

FBA_CMD19 FBA_CMD25 FBA_CMD22 FBA_CMD24 FBA_CMD0 FBA_CMD2 FBA_CMD21 FBA_CMD16 FBA_CMD23 FBA_CMD20 FBA_CMD17 FBA_CMD9 FBA_CMD14 FBA_CMD26

FBA_CMD12 FBA_CMD3 FBA_CMD27

FBA_CLK0 FBA_CLK0# FBA_CMD18

FBA_CMD30 FBA_CMD29 FBA_CMD1 FBA_CMD10 FBA_CMD11

FBA_DQS2 FBA_DQS3

FBA_DQM2 FBA_DQM3

FBA_DQS#2 FBA_DQS#3

FBA_CMD15

12

FBA_D5

E4

FBA_D1

F8

FBA_D7

F3

FBA_D0

F9

FBA_D6

H4

FBA_D2

H9

FBA_D3

G3

FBA_D4

H8

FBA_D13

D8

FBA_D9

C4

FBA_D14

C9

FBA_D11

C3

FBA_D12

A8

FBA_D8

A3

FBA_D15

B9

FBA_D10

A4

+1.5VRAM

B3 D10 G8 K3 K9 N2 N10 R2 R10

+1.5VRAM

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

U56

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

100-BALL

100-BALL SDRAM DDR3

SDRAM DDR3

K4B1G1646D-HCF8_FBGA100

@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

2

U57

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

100-BALL

100-BALL SDRAM DDR3

SDRAM DDR3

K4B1G1646D-HCF8_FBGA100

@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E4 F8 F3 F9 H4 H9 G3 H8

D8 C4 C9 C3 A8 A3 B9 A4

B3

VDD

D10

VDD

G8

VDD

K3

VDD

K9

VDD

N2

VDD

N10

VDD

R2

VDD

R10

VDD

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10

VSS

B4

VSS

E2

VSS

G9

VSS

J3

VSS

J9

VSS

M2

VSS

M10

VSS

P2

VSS

P10

VSS

T2

VSS

T10

VSS

B2 B10 D2 D9 E3 E9 F10 G2 G10

+1.5VRAM

PM@

R1143

R1143 240_0402_1%

240_0402_1%

VREFC_A4VREFC_A1 VREFD_Q4

FBA_CMD19 FBA_CMD25 FBA_CMD4 FBA_CMD6 FBA_CMD5 FBA_CMD13 FBA_CMD21 FBA_CMD16 FBA_CMD23 FBA_CMD20 FBA_CMD17 FBA_CMD9 FBA_CMD14 FBA_CMD26

FBA_CMD12 FBA_CMD3 FBA_CMD27

FBA_CLK1 FBA_CLK1#

FBA_CMD7

FBA_CMD28 FBA_CMD8 FBA_CMD1 FBA_CMD10 FBA_CMD11

FBA_DQS7 FBA_DQS6

FBA_DQM7 FBA_DQM6

FBA_DQS#7 FBA_DQS#6

FBA_CMD15

12

FBA_D32

E4

FBA_D33

F8

FBA_D34

F3

FBA_D35

F9

FBA_D36

H4

FBA_D37

H9

FBA_D38

G3

FBA_D39

H8

FBA_D40

D8

FBA_D45

C4

FBA_D41

C9

FBA_D46

C3

FBA_D43

A8

FBA_D47

A3

FBA_D42

B9

FBA_D44

A4

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

FBA_D60 FBA_D59 FBA_D61 FBA_D63 FBA_D56 FBA_D58 FBA_D57 FBA_D62

FBA_D48 FBA_D52 FBA_D51 FBA_D54 FBA_D49 FBA_D55 FBA_D50 FBA_D53

1

+1.5VRAM

B B

+1.5VRAM

A A

1

PM@

C1246

C1246 10U_0603_6.3V6M

10U_0603_6.3V6M

2

PM@

C1254

1

2

1U_0402_6.3V4Z

PM@

C1265

1

2

1U_0402_6.3V4Z

PM@

C1255

1

2

1U_0402_6.3V4Z

PM@

C1266

1

2

5

1

PM@

C1247

C1247 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

2

1U_0402_6.3V4Z

1

2

1U_0402_6.3V4Z

PM@

C1256

1U_0402_6.3V4Z

PM@

C1267

1

2

PM@

C1257

1

2

PM@

C1268

1

2

PM@

C1248

C1248 10U_0603_6.3V6M

10U_0603_6.3V6M

PM@

C1258

1

2

1U_0402_6.3V4Z

PM@

C1269

1

2

1U_0402_6.3V4Z

1

2

1U_0402_6.3V4Z

PM@

C1259

1

2

1U_0402_6.3V4Z

PM@

C1270

1

2

PM@

C1249

C1249 10U_0603_6.3V6M

10U_0603_6.3V6M

PM@

C1260

1

2

1U_0402_6.3V4Z

PM@

C1271

1

2

1U_0402_6.3V4Z

1

PM@

C1250

C1250 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1U_0402_6.3V4Z

PM@

C1261

1

2

1U_0402_6.3V4Z

PM@

C1272

1

2

4

1

2

1U_0402_6.3V4Z

1

2

1U_0402_6.3V4Z

1

PM@

C1251

C1251 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1U_0402_6.3V4Z

PM@

C1262

1U_0402_6.3V4Z

PM@

C1273

+1.5VRAM

PM@

R1145

1.33K_0402_1%

PM@

C1263

1

2

+1.5VRAM

1

PM@

+

PM@

C1274

1

2

+

C1264

C1264 220U_D2_4VM_R15

220U_D2_4VM_R15

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

3

PM@

R1147

1.33K_0402_1%

2007/10/15 2008/10/15

VREFD_Q3

12

VREFC_A3 VREFC_A4

VREFC_A1 VREFD_Q2

10MIL 10MIL

12

1

PM@

C1252

0.1U_0402_10V6K

2

Compal Secret Data

Deciphered Date

2

1.33K_0402_1%

PM@

R1146

PM@

R1148

+1.5VRAM

VREFD_Q4

12

VREFC_A2VREFD_Q1

12

1

PM@

C1253

0.1U_0402_10V6K

2

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

VRAM DDRA

NIWBA_LA5371P

1

0.1

21 53Wednesday, April 22, 2009

0.1

5

PCI

SRC

CPU

CLKSEL1

0

FSA

CLKSEL0

MHz

266

MHz

1000

MHz

33.30

14.318 96.0 48.0

DOT_96 MHz

USB MHz

FSC FSB REF

CLKSEL2

0 1000 133 33.31 14.318 96.0 48.0

0 1001 200 33.30 14.318 96.0 48.0

D D

0 1001 166 33.31 14.318 96.0 48.0

1 1000 333 33.30 14.318 96.0 48.0

1 1000 100 33.31 14.318 96.0 48.0

1 1001 400 33.30 14.318 96.0 48.0

1 1 1

R184 2.2K_0402_5%R184 2.2K_0402_5%

FSA

CPU_BSEL0<6>

C C

CPU_BSEL1<6>

B B

CPU_BSEL2<6>

12

@

R215

R215 10K_0402_5%

10K_0402_5%

12

R218

A A

10K_0402_5%

R187 0_0402_5%R187 0_0402_5%

R198 0_0402_5%R198 0_0402_5%

R204 10K_0402_5%R204 10K_0402_5%

FSC

R209 0_0402_5%

+3VS+3VS +3VS

12

PM@

R216

R216 10K_0402_5%

10K_0402_5%

12

GM@

R219

R219 10K_0402_5%

10K_0402_5%

1 2

1 2 1 2

12

FSB

12

R217

R217 10K_0402_5%

10K_0402_5%

12

@

R220

R220 10K_0402_5%

10K_0402_5%

Reserved

+VCCP

@

R183

R183 56_0402_5%

56_0402_5%

1 2

R185 1K_0402_5%R185 1K_0402_5%

1 2

12

@

R190

R190 1K_0402_5%

1K_0402_5%

+VCCP

12

@

R194

R194 1K_0402_5%

1K_0402_5% R196 1K_0402_5%R196 1K_0402_5%

1 2

12

@

R199

R199 0_0402_5%

0_0402_5%

+VCCP

12

@

R200

R200 1K_0402_5%

1K_0402_5% R205 1K_0402_5%

R205 1K_0402_5%

1 2

12

@

R212

R212 0_0402_5%

0_0402_5%

14.31818MHZ_16PF_DSX840GA

MCH_CLKSEL0 <8>

MCH_CLKSEL1 <8>

MCH_CLKSEL2 <8>

C455 22P_0402_50V8JC455 22P_0402_50V8J

Y2

C456 22P_0402_50V8JC456 22P_0402_50V8J

Routing the trace at least 10mil

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP# For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96#

Pin28/29 : LCDCLK / LCDCLK# 1 = Pin24/25 : SRC_0 / SRC_0# Pin28/29 : 27M/27M_SS

5

CLK_XTAL_INITP_EN PCI4_SEL PCI2_TME

12

CLK_XTAL_OUT

4

R178 0_0805_5%R178 0_0805_5%

+3VS

+1.5VS

+VCCP

1 2

R181 0_0805_5%@R181 0_0805_5%@

1 2

R182 0_0805_5%R182 0_0805_5%

1 2

CLK_48M_CR CLK_48M_ICH CLK_14M_ICH CLK_14M_SIO

C853 22P_0402_50V8J@C853 22P_0402_50V8J@ C854 22P_0402_50V8J@C854 22P_0402_50V8J@ C855 22P_0402_50V8J@C855 22P_0402_50V8J@ C856 22P_0402_50V8J@C856 22P_0402_50V8J@

FOR 3G ISSUE (SED)

CLK_48M_CR<34>

CLK_48M_ICH<29>

CLK_14M_ICH<29> CLK_14M_SIO<39>

CK_PWRGD<29>

H_STP_CPU#<29>

H_STP_PCI#<29>

CLK_PCI_DB<39>

CLK_PCI_LPC<38> CLK_PCI_ICH<27>

4

+3VSM_CK505

1

C441

C441 10U_0805_10V4Z

10U_0805_10V4Z

2

+VDD_CK505

1

C448

C448 10U_0805_10V4Z

10U_0805_10V4Z

2

SA000020K00 (Silego : SLG8SP556VTR ) SA000020H10 (ICS : ICS9LPRS387BKLFT)

R192

CLK_48M_CR

CLK_48M_ICH

CLK_14M_ICH CLK_14M_SIO

R192

1 2

R193

1 2

R195

1 2

R197 33_0402_5%@R197 33_0402_5%@

1 2

R207 33_0402_5%@R207 33_0402_5%@

1 2

R213 33_0402_5%R213 33_0402_5%

1 2

R214 33_0402_5%

1 2

1

C442

0.1U_0402_16V4Z

2

+VDD_CK505

12_0402_5%

33_0402_5%

CK_PWRGD

PM_STP_CPU# PM_STP_PCI#

CLK_XTAL_IN CLK_XTAL_OUT

3

1

C443

0.1U_0402_16V4Z

2

1

C449

0.1U_0402_16V4Z

2

+3VSM_CK505

U16

55

6 12 72 19 27

66 31 62 52 23 38

FSA

20

FSB

2

FSC

7

8

1 11

53 54

5

4

13

PCI2_TME

14 15

PCI4_SEL

16

ITP_EN

17

18

3 22 26 69 30 34 59 42 73

SLG8SP556VTR_QFN72_10X10

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C450

0.1U_0402_16V4Z

2

VDD_SRC VDD_REF VDD_PCI VDD_CPU VDD_48 VDD_PLL3

VDD_CPU_IO VDD_PLL3_IO VDD_SRC_IO VDD_SRC_IO VDD_IO VDD_SRC_IO

USB_0/FS_A FS_B/TEST_MODE REF_0/FS_C/TEST_ REF_1

CKPWRGD/PD# NC

CPU_STOP# PCI_STOP#

XTAL_IN XTAL_OUT

PCI_1 PCI_2 PCI_3 PCI_4/SEL_LCDCL PCIF_5/ITP_EN

VSS_PCI VSS_REF VSS_48 VSS_IO VSS_CPU VSS_PLL3 VSS_SRC VSS_SRC VSS_SRC VSS

1

C444

0.1U_0402_16V4Z

2

1

C445

0.1U_0402_16V4Z

2

1

C451

0.1U_0402_16V4Z

2

SRC_0#/DOT_96#

LCDCLK#/27M_SS

SRC_8#/CPU_ITP#

USB_1/CLKREQ_A#

2008/03/25 2008/04/

1

C452

0.1U_0402_16V4Z

2

SDA SCL

CPU_0

CPU_0#

CPU_1

CPU_1#

SRC_0/DOT_96

LCDCLK/27M

SRC_2

SRC_2#

SRC_3

SRC_3#

SRC_4

SRC_4#

SRC_6

SRC_6#

SRC_7

SRC_7#

SRC_8/CPU_ITP

SRC_9

SRC_9#

SRC_10

SRC_10#

SRC_11

SRC_11#

CLKREQ_3# CLKREQ_4# CLKREQ_6# CLKREQ_7#

CLKREQ_9# SLKREQ_10# CLKREQ_11#

Compal Secret Data

1

C446

0.1U_0402_16V4Z

2

1

2

9 10

71 70 68 67

24 25

28 29

32 33

35 36

39 40

57 56

61 60

64 63

44 45

50 51

48 47

37 41 58 65 43 49 46 21

Deciphered Date

1

C447

0.1U_0402_16V4Z

2

C453

0.1U_0402_16V4Z

CLK_SMBDATA CLK_SMBCLK

CLK_CPU_BCLK CLK_CPU_BCLK# CLK_MCH_BCLK CLK_MCH_BCLK#

R_CLK_DOT R_CLK_DOT#

CLK_MCH_3GPLL CLK_MCH_3GPLL#

CLK_PCIE_EXP CLK_PCIE_EXP#

CLK_PCIE_WLAN2 CLK_PCIE_WLAN2#

CLK_PCIE_WLAN CLK_PCIE_WLAN#

CLK_PCIE_WLAN1 CLK_PCIE_WLAN1#

CLK_PCIE_LAN CLK_PCIE_LAN#

CLK_PCIE_ICH CLK_PCIE_ICH#

CLK_PCIE_SATA CLK_PCIE_SATA#

EXP_CLKREQ# WLAN_CLKREQ2# WLAN_CLKREQ# WLAN_CLKREQ1# CLKREQ_LAN#

SATA_CLKREQ#_R MCH_CLKREQ#_R

2

1

C454

0.1U_0402_16V4Z

2

R186 0_0402_5%GM@R186 0_0402_5%GM@ R188 0_0402_5%PM@R188 0_0402_5%PM@ R189 0_0402_5%GM@R189 0_0402_5%GM@ R191 0_0402_5%PM@R191 0_0402_5%PM@

2

ICH_SMBDATA<29,31>

1 2 1 2 1 2 1 2

R221 0_0402_5%R221 0_0402_5% R222 0_0402_5%R222 0_0402_5%

ICH_SMBCLK<29,31>

CLK_SMBDATA <14,15> CLK_SMBCLK <14,15>

CLK_CPU_BCLK <5> CLK_CPU_BCLK# <5> CLK_MCH_BCLK <8> CLK_MCH_BCLK# <8>

MCH_SSCDREFCLK <8> MCH_SSCDREFCLK# <8>

CLK_MCH_3GPLL <8> CLK_MCH_3GPLL# <8>

CLK_PCIE_EXP <31> CLK_PCIE_EXP# <31>

CLK_PCIE_WLAN2 <31> CLK_PCIE_WLAN2# <31>

CLK_PCIE_WLAN <31> CLK_PCIE_WLAN# <31>

CLK_PCIE_WLAN1 <31> CLK_PCIE_WLAN1# <31>

CLK_PCIE_LAN <32> CLK_PCIE_LAN# <32>

CLK_PCIE_ICH <29> CLK_PCIE_ICH# <29>

CLK_PCIE_SATA <28> CLK_PCIE_SATA# <28>

EXP_CLKREQ# <31> WLAN_CLKREQ2# <31> WLAN_CLKREQ# <31> WLAN_CLKREQ1# <31> CLKREQ_LAN# <32>

1 2 1 2

1

+3VS

@

R235 0_0402_5%R235 0_0402_5%

1 2

2N7002DW-T/R7_SOT363-6

6 1

@ Q1A

@

+3VS

@ Q1B

@

3

2N7002DW-T/R7_SOT363-6

R234 0_0402_5%R234 0_0402_5%

1 2

CLK_MCH_DREFCLK <8>

CLK_PCIE_VGA <16>

CLK_MCH_DREFCLK# <8>

CLK_PCIE_VGA# <16>

@

R179

2.2K_0402_5%

Q1A

2 5

Q1B

4

@

R180

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

SRC PORT LIST

DEVICEPORT

SRC0 SRC2 SRC3 SRC4 SRC6 SRC7

MCH_DREFCLK MCH_3GPLL PCIE_EXP#

PCIE_WLAN2

PCIE_WLAN

PCIE_WLAN1 SRC8 SRC9 SRC10 SRC11

SATA_CLKREQ#_R EXP_CLKREQ# WLAN_CLKREQ1# MCH_CLKREQ#_R CLKREQ_LAN# WLAN_CLKREQ# WLAN_CLKREQ2#

REQ PORT LIST

PCIE_LAN

PCIE_ICH

PCIE_SATA

R201 10K_0402_5%R201 10K_0402_5%

R202 10K_0402_5%R202 10K_0402_5%

R203 10K_0402_5%R203 10K_0402_5%

R206 10K_0402_5%R206 10K_0402_5%

R208 10K_0402_5%R208 10K_0402_5%

R210 10K_0402_5%R210 10K_0402_5%

R211 10K_0402_5%R211 10K_0402_5%

12 12 12 12 12 12 12

DEVICEPORT

REQ_3# REQ_4# REQ_6# REQ_7# REQ_9#

PCIE_EXP#

PCIE_WLAN2

PCIE_WLAN PCIE_WLAN1

PCIE_LAN REQ_10# REQ_11# REQ_A#

SATA_CLKREQ# <29> MCH_CLKREQ# <8>

Compal Electronics,Ltd.

Title

Clock Generator CK505

Size Document Number Rev

Custom

KIWB3/B4_LA4551P

Date: Sheet of

PCIE_SATA

MCH_3GPLL

1

23 53Wednesday, March 18, 2009

+3VS

0.1

5

4

3

2

1

+3VS

12

@

R223

R223 0_0402_5%

0_0402_5%

D D

C C

+3VS

12

R225

4.7K_0402_5%

GM@

@

R226

R226 0_0402_5%

0_0402_5%

+3VS

TMDS pull down (500ohm) resistors G9x only

HDMI_CLK+_CONN HDMI_CLK-_CONN HDMI_TX0+_CONN HDMI_TX0-_CONN HDMI_TX1+_CONN HDMI_TX1-_CONN HDMI_TX2+_CONN HDMI_TX2-_CONN

B B

A A

NEAR CONNECT

HDMI_CLK+

HDMI_CLK-

HDMI_TX0+

HDMI_TX0-

HDMI_TX1+

HDMI_TX1-

HDMI_TX2+

HDMI_TX2-

HDMI_CLK+ HDMI_CLKHDMI_TX0+ HDMI_TX0HDMI_TX1+ HDMI_TX1HDMI_TX2+ HDMI_TX2-

1 2

R236 499_0402_1%PM@R236 499_0402_1%PM@

1 2

R237 499_0402_1%PM@R237 499_0402_1%PM@

1 2

R238 499_0402_1%PM@R238 499_0402_1%PM@

1 2

R239 499_0402_1%PM@R239 499_0402_1%PM@

1 2

R240 499_0402_1%PM@R240 499_0402_1%PM@

1 2

R241 499_0402_1%PM@R241 499_0402_1%PM@

1 2

R242 499_0402_1%PM@R242 499_0402_1%PM@

1 2

R243 499_0402_1%PM@R243 499_0402_1%PM@

L17

1

4

WCM-2012-900T_4P

WCM-2012-900T_4P L18

L18

1

4

WCM-2012-900T_4P

WCM-2012-900T_4P L20

L20

1

4

WCM-2012-900T_4P

WCM-2012-900T_4P L21

L21

1

4

WCM-2012-900T_4P

R251 0_0402_5%@R251 0_0402_5%@

1 2

R252 0_0402_5%@R252 0_0402_5%@

1 2

R253 0_0402_5%@R253 0_0402_5%@

1 2

R254 0_0402_5%@R254 0_0402_5%@

1 2

R255 0_0402_5%@R255 0_0402_5%@

1 2

R256 0_0402_5%@R256 0_0402_5%@

1 2

R257 0_0402_5%@R257 0_0402_5%@

1 2

R258 0_0402_5%@R258 0_0402_5%@

1 2

5

2

3

2

3

2

3

2

3

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

HDMI_CLK+_CONN HDMI_CLK-_CONN HDMI_TX0+_CONN HDMI_TX0-_CONN HDMI_TX1+_CONN HDMI_TX1-_CONN HDMI_TX2+_CONN HDMI_TX2-_CONN

13

D

PM@

S

Q2

Q2 2N7002W -T/R7_SOT323-3

2N7002W -T/R7_SOT323-3

12

@

R224

R224 0_0402_5%

0_0402_5%

4.7K_0402_5%

R227

1 2

R229

1 2

4.7K_0402_5%

TMDS_B_CLK<10> TMDS_B_CLK#<10>

TMDS_B_DATA0<10> TMDS_B_DATA0#<10>

TMDS_B_DATA1<10> TMDS_B_DATA1#<10>

TMDS_B_DATA2<10> TMDS_B_DATA2#<10>

2

+3VS

G

HDMI_DETECT_VGA<16>

HDMI_CLK+

HDMI_TX0+

HDMI_TX1+

R612

4

HDMICLK_R HDMIDAT_R

HDMI_DETECT

@R227

@ @R229

@

1 2

HDMI_DETECT_VGA

R825

1 2

68_0402_5%

@

R826

1 2

68_0402_5%

@

R827

1 2

68_0402_5%

@

R828

1 2

68_0402_5%

@

R613

4.7K_0402_5%

@

1 2

P/N:SA00002D700 (8101T) P/N:SA00001U900 (CH7318A)

U17

25

OE#

28

SCL_SINK

29

SDA_SINK

30

HPD_SINK

32

DDC_EN

34

CFG0

35

CFG1

internal pull down

48

IN_D4+

47

IN_D4-

45

IN_D3+

44

IN_D3-

42

IN_D2+

41

IN_D2-

39

IN_D1+

38

IN_D1-

PS8101TQFN48G_QFN48_7X7GM@

R249

1 2

1K_0402_1%PM@

HDMI_CLK-

HDMI_TX0-

HDMI_TX1-

HDMI_TX2-HDMI_TX2+

Issued Date

12

PM@

R250

R250 10K_0402_1%

10K_0402_1%

HDMI_DETECT

1 2

L19 FBMA-L10-160808-121LMT_2P

PM@

+5VS

2008/03/25 2008/04/

3

@

D6

D6 RB751V_SOD323

RB751V_SOD323

2 1

C857

1 2

0.5P_0402_50V8@

0.5P_0402_50V8@ C858

C858

1 2

0.5P_0402_50V8@

0.5P_0402_50V8@ C859

C859

1 2

0.5P_0402_50V8@

0.5P_0402_50V8@ C860

C860

1 2

0.5P_0402_50V8@

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

VCC

11

VCC

15

VCC

21

VCC

26

VCC

33

VCC

40

VCC

46

VCC

4

PC1

3

PC0

internal pull down

6

REXT

7

HPD#

8

SDA

9

SCL

10

RT_EN#

13

OUT_D4+

14

OUT_D4-

16

OUT_D3+

17

OUT_D3-

19

OUT_D2+

20

OUT_D2-

22

OUT_D1+

23

OUT_D1-

1

GND

5

GND

12

GND

18

GND

24

GND

27

GND

31

GND

36

GND

37

GND

43

GND

49

PAD

3

1

@

2

D7

D7 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

Compal Secret Data

Deciphered Date

FOR 7318C PIN6 PULL DOWN 1.2Kohm

PIN7 PULL DOWN 7.5Kohm PIN7 PULL UP 20Kohm

+3VS

1

GM@

C457

0.1U_0402_16V4Z

2

R228 4.7K_0402_5%GM@R228 4.7K_0402_5%GM@

1 2

R230 4.7K_0402_5%@R230 4.7K_0402_5%@

1 2

R231 499_0402_1%GM@R231 499_0402_1%GM@

1 2

TMDS_B_HPD#

HDMI_CLK+ HDMI_CLK-

HDMI_TX0+ HDMI_TX0-

HDMI_TX1+ HDMI_TX1-

HDMI_TX2+ HDMI_TX2-

1 2

R247 0_0402_5%GM@R247 0_0402_5%GM@

1 2

R248 0_0402_5%PM@R248 0_0402_5%PM@

PM@

C472

C472 330P_0402_50V7K

330P_0402_50V7K

+5VS

HDMIDAT_R

1

GM@

C458

0.1U_0402_16V4Z

2

TMDS_B_HPD# <10>

+5VS

3

2

1

GM@

C459

0.1U_0402_16V4Z

2

+3VS

VGA_HDMI_CLK-<18> VGA_HDMI_CLK+<18>

VGA_HDMI_TX0-<18> VGA_HDMI_TX0+<18>

VGA_HDMI_TX1-<18> VGA_HDMI_TX1+<18>

VGA_HDMI_TX2-<18> VGA_HDMI_TX2+<18>

VGA_HDMI_SDA<18>

VGA_HDMI_SCL<18>

2

@

1

D5

D5 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

HDMIDAT_R HDMICLK_R

HDMICLK_R

1

@

D8

D8 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

1

GM@

C460

C460 10U_0805_10V4Z

10U_0805_10V4Z

2

+3VS

12

GM@

R232

2.2K_0402_5%

R244

@ R244

@

0_0805_5%

R245

2.2K_0402_5%

1 2

Title

Size Document Number Rev

Custom

Custom Date: Sheet of

Date: Sheet of

12

GM@

R233

2.2K_0402_5%

C461 0.1U_0402_16V7KPM@C461 0.1U_0402_16V7KPM@

1 2

C462 0.1U_0402_16V7KPM@C462 0.1U_0402_16V7KPM@

1 2

C463 0.1U_0402_16V7KPM@C463 0.1U_0402_16V7KPM@

1 2

C464 0.1U_0402_16V7KPM@C464 0.1U_0402_16V7KPM@

1 2

C465 0.1U_0402_16V7KPM@C465 0.1U_0402_16V7KPM@

1 2

C466 0.1U_0402_16V7KPM@C466 0.1U_0402_16V7KPM@

1 2

C467 0.1U_0402_16V7KPM@C467 0.1U_0402_16V7KPM@

1 2

C468 0.1U_0402_16V7KPM@C468 0.1U_0402_16V7KPM@

1 2

L15

1 2

L16 MBK1608121YZF_0603

1 2

PM@

C469

PM@

12P_0402_50V8J

+5VS

R246

2.2K_0402_5%

1 2

HDMI_CLK-_CONN HDMI_CLK+_CONN HDMI_TX0-_CONN HDMI_TX0+_CONN HDMI_TX1-_CONN HDMI_TX1+_CONN HDMI_TX2-_CONN HDMI_TX2+_CONN

Compal Electronics,Ltd.

Level Shiftter_PS8101T

KIWB1/B2_LA4601P

TMDS_B_HPD#

MBK1608121YZF_0603PM@

1

2

21

D4

D4 RB491D_SC59-3

RB491D_SC59-3

+5VS_HDMI

18 16 15 19

12 10

+3VS

12

R615

R615 20K_0402_1%

20K_0402_1%

@

12

R614

7.5K_0402_1%

@

HDMIDAT_NB <8> HDMICLK_NB <8>

HDMI_CLKHDMI_CLK+

HDMI_TX0HDMI_TX0+

HDMI_TX1HDMI_TX1+

HDMI_TX2HDMI_TX2+

HDMIDAT_R HDMICLK_R

1

C470

PM@

2

12P_0402_50V8J

C471

1

0.1U_0402_16V4Z

2

JHDMI

+5V SDA SCL HP_DET

CKCK+

9

D0-

7

D0+

6

D1-

4

D1+

3

D2-

1

D2+

SUYIN_100042MR019S153ZL

1

Reserved

DDC/CEC_GND

24 53Wednesday, March 18, 2009

CEC

GND GND GND GND GND GND GND GND

HDMI_CEC<18>

13 14

2 5 8 11 20 21 22 23 17

0.1

5

LCD POWER CIRCUIT

+LCDVDD

13

D

D D

2N7002_SOT23

GM@

R263 0_0402_5%

GM_ENVDD<10>

VGA_ENVDD<16>

1 2

R265 0_0402_5%

1 2

PM@

D

Q5

S

R264

100K_0402_5%

R790

R790 150_0603_1%

150_0603_1%

2

G

DTC124EK

2

12

@R264

@

+5VALW

IN

12

R791

R791 100K_0402_5%

100K_0402_5%

1 2

1

OUT

Q4

Q4 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

GND

3

UMA LCD/PANEL BD. Conn.

JLVDS1

1

+LCDVDD_CONN +LCDVDD_CONN

+3VS +3VS

C C

INVT_PWM<38> DAC_BRIG<38>

LVDS_SCL<10> LVDS_SDA<10>

(60 MIL)

DISPOFF#

LVDS_SCL LVDS_SDA

3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

GND41GND

ACES_87142-4041

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

42

4

R792 220K_0402_5%R792 220K_0402_5%

1

2

+LEDVDD

LVDS_B2# LVDS_B2 LVDS_BCLK# LVDS_BCLK LVDS_B1#LVDS_B1# LVDS_B1 LVDS_A0# LVDS_A0 LVDS_B0 LVDS_B0# LVDS_A1 LVDS_A1# LVDS_A2# LVDS_A2 LVDS_ACLK# LVDS_ACLK

C11

0.1U_0402_16V4Z

+LEDVDD

+3VS

W=60mils

S

G

2

SI2301BDS-T1-E3_SOT23-3

D

Q6

1 3

LVDS_B2# <10> LVDS_B2 <10> LVDS_BCLK# <10> LVDS_BCLK <10> LVDS_B1# <10> LVDS_B1 <10> LVDS_A0# <10> LVDS_A0 <10> LVDS_B0 <10> LVDS_B0# <10>

LVDS_A1 <10> LVDS_A1# <10> LVDS_A2# <10> LVDS_A2 <10> LVDS_ACLK# <10> LVDS_ACLK <10>

1

C478

4.7U_0805_10V4Z

2

W=60mils

+LCDVDD

FBMA-L11-201209-221LMA30T_0805

L23

1 2

+LCDVDD_CONN

+3VS

680P_0402_50V7K

3

1

C473

4.7U_0805_10V4Z

2

@

C836

2

+3VS

12

R259

4.7K_0402_5%

D9

BKOFF#<38>

GMCH_ENBKL<10> VGA_ENBKL<16>

1

C474

0.1U_0402_16V4Z

2

BKOFF# DISPOFF#

D9

21

CH751H-40PT_SOD323-2

R260 0_0402_5%GM@R260 0_0402_5%GM@ R261 0_0402_5%PM@R261 0_0402_5%PM@

12 12

VGA LCD/PANEL BD. Conn.

+LCDVDD_CONN

1

2

VGA_LVDS_SCL<16> VGA_LVDS_SDA<16>

(60 MIL)

INVT_PWM<38> DAC_BRIG<38>

DISPOFF#

VGA_LVDS_SCL VGA_LVDS_SDA

4.7K_0402_5%

ENBKL

R262

100K_0402_1%

1 2

change from 10K to 100K 5/8 by checklist

JLVDS2

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

39 GND41GND

ACES_87142-4041

ENBKL <38>

+LEDVDD

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

470P_0402_50V7K

+LEDVDD

C837

680P_0402_50V7K

@

VGA_LVDS_B2# VGA_LVDS_B2 VGA_LVDS_BCLK# VGA_LVDS_BCLK VGA_LVDS_B1# VGA_LVDS_B1 VGA_LVDS_A0# VGA_LVDS_A0 VGA_LVDS_B0 VGA_LVDS_B0# VGA_LVDS_A1 VGA_LVDS_A1# VGA_LVDS_A2# VGA_LVDS_A2 VGA_LVDS_ACLK# VGA_LVDS_ACLK

1

@

1

C475

2

470P_0402_50V7K

For EMI

FBMA-L11-201209-221LMA30T_0805

1

C479

4.7U_0805_25V6-K

2

+LCDVDD_CONN +3VS

VGA_LVDS_B2# <18>

VGA_LVDS_B2 <18> VGA_LVDS_BCLK# <18> VGA_LVDS_BCLK <18> VGA_LVDS_B1# <18> VGA_LVDS_B1 <18>

VGA_LVDS_A0# <18>

VGA_LVDS_A0 <18>

VGA_LVDS_B0 <18>

VGA_LVDS_B0# <18>

VGA_LVDS_A1 <18>

VGA_LVDS_A1# <18>

VGA_LVDS_A2# <18>

VGA_LVDS_A2 <18>

VGA_LVDS_ACLK# <18>

VGA_LVDS_ACLK <18>

INVT_PWM

DAC_BRIG

DISPOFF#

@

1

C476

2

470P_0402_50V7K

L22

1 2

@

C477

B+

+LEDVDD

JLVDS4

JLVDS3

1

2 3

B B

A A

+LCDVDD_CONN

+3VS

INVT_PWM<38>

DAC_BRIG<38> LVDS_SCL<10> LVDS_SDA<10>

LVDS_B2#<10>

LVDS_B2<10> LVDS_BCLK#<10>

LVDS_BCLK<10>

LVDS_B1#<10>

LVDS_B1<10> LVDS_A0#<10> VGA_LVDS_A0<18>

LVDS_A0<10>

LVDS_B0<10>

LVDS_B0#<10> LVDS_A1<10>

LVDS_A1#<10> LVDS_A2#<10>

LVDS_A2<10>

LVDS_ACLK#<10> LVDS_ACLK<10>

5

+LEDVDD

(60 MIL)

DISPOFF# DAC_BRIG

DAC_BRIG

LVDS_SCL LVDS_SDA

LVDS_B2# LVDS_B2

LVDS_BCLK# LVDS_BCLK

LVDS_B1# LVDS_B1

LVDS_A0# VGA_LVDS_A0 LVDS_A0

LVDS_B0 LVDS_B0#

LVDS_A1 LVDS_A1#

LVDS_A2# LVDS_A2

LVDS_ACLK# LVDS_ACLK

4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

IPEX_20143-040E-20F

41

2

G1

42

3

G2

43

4

G3

44

5

G4

45

6

G5

46

7

G6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/10/15 2008/10/15

Compal Secret Data

INVT_PWM<38>

DAC_BRIG<38> VGA_LVDS_SCL<16> VGA_LVDS_SDA<16>

VGA_LVDS_B2#<18> VGA_LVDS_B2<18>

VGA_LVDS_BCLK#<18> VGA_LVDS_BCLK<18>

VGA_LVDS_B1#<18> VGA_LVDS_B1<18>

VGA_LVDS_A0#<18>

VGA_LVDS_B0<18> VGA_LVDS_B0#<18>

VGA_LVDS_A1<18> VGA_LVDS_A1#<18>

VGA_LVDS_A2#<18> VGA_LVDS_A2<18>

VGA_LVDS_ACLK#<18> VGA_LVDS_ACLK<18>

Deciphered Date

+LCDVDD_CONN

+LEDVDD

+3VS

400mA

+LEDVDD

(60 MIL)

DISPOFF# VGA_LVDS_SCL

VGA_LVDS_SDA VGA_LVDS_B2#

VGA_LVDS_B2 VGA_LVDS_BCLK#

VGA_LVDS_BCLK VGA_LVDS_B1#

VGA_LVDS_B1 VGA_LVDS_A0#

VGA_LVDS_B0 VGA_LVDS_B0#

VGA_LVDS_A1 VGA_LVDS_A1#

VGA_LVDS_A2# VGA_LVDS_A2

VGA_LVDS_ACLK# VGA_LVDS_ACLK

2

IPEX_20143-040E-20F

JLVDS4

1

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

41

2

G1

42

3

G2

43

4

G3

44

5

G4

45

6

G5

46

7

G6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

LVDS & DVI Connector

KIWB1/B2_LA4601P

25 53Wednesday, March 18, 2009

1

0.1

A

B

C

D

E

CLOSE TO CHIPSET

R266 0_0402_5%PM@R266 0_0402_5%PM@

VGA_CRT_R<16>

GMCH_CRT_R<10>

1 1

VGA_CRT_G<16>

GMCH_CRT_G<10>

VGA_CRT_B<16>

GMCH_CRT_B<10>

2 2

VGA_HSYNC<16> GMCH_CRT_HSYNC<10>

1 2

R267 0_0402_5%GM@ R268 0_0402_5%PM@R268 0_0402_5%PM@

1 2

R269 0_0402_5%GM@R269 0_0402_5%GM@

1 2

R270 0_0402_5%PM@R270 0_0402_5%PM@

1 2

R271 0_0402_5%GM@R271 0_0402_5%GM@

1 2

R276 0_0402_5%PM@R276 0_0402_5%PM@

1 2

Place closed to chipset

R277 0_0402_5%PM@R277 0_0402_5%PM@

VGA_VSYNC<16>

3 3

GMCH_CRT_VSYNC<10>

1 2

CLOSE TO CONN

12

1

C487

0.1U_0402_16V4Z

2

1

C490

0.1U_0402_16V4Z

2

R272

R272 150_0402_1%

150_0402_1%

12

R273

R273 150_0402_1%

150_0402_1%

+CRT_VCC

5

P

A2Y

G

3

CRT_R_1

CRT_G_1

12

R274

R274 150_0402_1%

150_0402_1%

1

4

OE#

U20

U20 SN74AHCT1G125DCKR_SC70-5

SN74AHCT1G125DCKR_SC70-5

CRT_B_1

12

1

2

R275

R275 1K_0402_5%

1K_0402_5%

CRT_HSYNC_1

CRT_VSYNC_1

FCM1608CF-121T03_2P

L24

1 2

FCM1608CF-121T03_2P

L25

1 2

FCM1608CF-121T03_2P

L26

1 2

C481

C481 10P_0402_50V8J

10P_0402_50V8J

+5VS +5VS +5VS

3

2

@

D11

D11 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

+5VS +5VS

1

2

1

FCM1608CF-121T03_2P

L27

1 2

FCM1608CF-121T03_2P

L28

1 2

C483

C483 10P_0402_50V8J

10P_0402_50V8J

3

2

3

2

1

@

D12

D12 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

JVGA_VSJVGA_HS

1

@

D15

D15 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

1

2

1

C484

C484 10P_0402_50V8J

10P_0402_50V8J

2

3

2

@

C488

C488 10P_0402_50V8J

10P_0402_50V8J

1

C485

C485 10P_0402_50V8J

10P_0402_50V8J

2

REDGREENBLUE

1

@

D13

D13 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

JVGA_HS

JVGA_VS

1

C489

@C489

@

10P_0402_50V8J

2

RED

GREEN

BLUE

1

C486

C486 10P_0402_50V8J

10P_0402_50V8J

2

+5VS

CRT Connector

+CRT_VCC

D10

2 1

RB491D_SC59-3

W=40mils

RED GREEN BLUE JVGA_VS JVGA_HS

CRT_DDC_DAT CRT_DDC_CLK

UPDATE FOR PVT

1

C480

0.1U_0402_16V4Z

2

JCRT1

1

2

3

4

5

6

7

8

9

10

11

12

13

GND1

14

GND2

ACES_87213-1200G

ME@

2.2K

+3VS

+CRT_VCC

Issued Date

2.2K

12

R282

2.2K_0402_5%

CRT_DDC_DAT

CRT_DDC_CLK

1

@

C491

C491 100P_0402_50V8J

100P_0402_50V8J

2

C

1

@

C492

C492 68P_0402_50V8K

68P_0402_50V8K

2

Compal Secret Data

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

CRT & TV-OUT Connector

KIWB1/B2_LA4601P

26 53Wednesday, March 18, 2009

E

0.1

12

R278

2.2K_0402_5%

VGA_DDCDATA<16>

GMCH_CRT_DATA<10>

R284 0_0402_5%GM@R284 0_0402_5%GM@

GMCH_CRT_CLK<10>

VGA_DDCCLK<16>

4 4

1 2

R285 0_0402_5%PM@R285 0_0402_5%PM@

1 2

A

12

R279

2.2K_0402_5%

B

+3VS

5

4

2

Q30A

Q30A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

3

Q30B

Q30B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

61

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

+RTCVCC

R314 330K_0402_1%R314 330K_0402_1%

LAN100_SLP

1 2

R316 1M_0402_5%R316 1M_0402_5%

SM_INTRUDER#

1 2

R318 330K_0402_1%R318 330K_0402_1%

D D

C C

1 2

ICH_INTVRMEN

+RTCVCC

HDD

ODD

1 2

2

C495

0.1U_0402_16V4Z

1

R322

100_0603_1%

DRIVE_LED#<42>

SATA_DTX_C_IRX_N0<35> SATA_DTX_C_IRX_P0<35>

SATA_ITX_DRX_N0<35> SATA_ITX_DRX_P0<35>

SATA_DTX_C_IRX_N1<35> SATA_DTX_C_IRX_P1<35>

SATA_ITX_DRX_N1<35> SATA_ITX_DRX_P1<35>

32.768KHZ_12.5P_1TJS125BJ2A251

+RTCBATT

DRIVE_LED#

SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 SATA_ITX_DRX_N0

SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 SATA_ITX_DRX_N1 SATA_ITX_DRX_P1

+RTCVCC

HDA_BITCLK_CODEC<8,36>

HDA_SDOUT_CODEC<8,36>

HDA_SYNC_CODEC<8,36>

HDA_RST_CODEC#<8,36>

HDA_SDIN0<8> HDA_SDIN1 HDA_SDIN2<36>

C494

C496

+3VS

4

1 2

10P_0402_50V8J

Y3

2 3

1 2

R320 20K_0402_5%R320 20K_0402_5%

1

IN

NC

4

OUT

NC

10P_0402_50V8J

CLRP1

2 1

2MM

1 2

C497 1U_0603_10V4ZC497 1U_0603_10V4Z

close to RAM door

+1.5VS

1 2

R326 24.9_0402_1%R326 24.9_0402_1%

1 2

R327 33_0402_5%R327 33_0402_5%

1 2

R329 33_0402_5%R329 33_0402_5%

1 2

R330 33_0402_5%R330 33_0402_5%

1 2

R333 33_0402_5%R333 33_0402_5%

1 2

R335 10K_0402_5%R335 10K_0402_5%

1 2 1 2

SATA_LED#

D16RB751V_SOD323 D16RB751V_SOD323

2 1

C498 0.01U_0402_16V7KC498 0.01U_0402_16V7K C499 0.01U_0402_16V7KC499 0.01U_0402_16V7K

C500 0.01U_0402_16V7KC500 0.01U_0402_16V7K C501 0.01U_0402_16V7KC501 0.01U_0402_16V7K

ICH_RTCX1

12

R317

R317 10M_0402_5%

10M_0402_5%

ICH_RTCX2 ICH_RTCRST#

ICH_SRTCRST# SM_INTRUDER#

ICH_INTVRMEN LAN100_SLP

SATA_ITX_C_DRX_N0 SATA_ITX_C_DRX_P0SATA_ITX_DRX_P0

SATA_ITX_C_DRX_N1 SATA_ITX_C_DRX_P1

GLAN_COMP HDA_BITCLK_R HDA_SYNC_R HDA_RST_R#

HDA_SDOUT_R

U21A

C23

RTCX1

C24

RTCX2

A25

RTCRST#

F20

SRTCRST#

C22

INTRUDER#

B22

INTVRMEN

A22

LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14

LAN_RXD0

G13

LAN_RXD1

D14

LAN_RXD2

D13

LAN_TXD_0

D12

LAN_TXD_1

E13

LAN_TXD_2

B10

GPIO56

B28

GLAN_COMPI

B27

GLAN_COMPO

AF6

HDA_BIT_CLK

AH4

HDA_SYNC

AE7

HDA_RST#

AF4

HDA_SDIN0

AG4

HDA_SDIN1

AH3

HDA_SDIN2

AE5

HDA_SDIN3

AG5

HDA_SDOUT

AG7

HDA_DOCK_EN#/GPIO33

AE8

HDA_DOCK_RST#/GPIO34

AG8

SATALED#

AJ16

SATA0RXN

AH16

SATA0RXP

AF17

SATA0TXN

AG17

SATA0TXP

AH13

SATA1RXN

AJ13

SATA1RXP

AG14

SATA1TXN

AF14

SATA1TXP

ICH9-M ES_FCBGA676

3

LPC_AD0

K5

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME#

RTC

LPCCPU

LAN / GLAN

IHDA

SATA

LDRQ0#

LDRQ1#/GPIO23

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD

IGNNE#

INIT# INTR

RCIN#

SMI#

STPCLK#

THRMTRIP#

TP12

SATA4RXN

SATA4RXP SATA4TXN SATA4TXP

SATA5RXN

SATA5RXP SATA5TXN SATA5TXP

SATA_CLKN SATA_CLKP

SATARBIAS#

SATARBIAS

NMI

LPC_AD1

K4

LPC_AD2

L6

LPC_AD3

K2

LPC_FRAME#

K3

LPC_DRQ0#

J3 J1

N7 AJ27

AJ25 AE23

AJ26 AD22 AF25 AE22

AG25 L3

AF23 AF24

AH27 AG26 AG27

SATA_DTX_C_IRX_N4

AH11

SATA_DTX_C_IRX_P4

AJ11

SATA_ITX_C_DRX_N4

AG12

SATA_ITX_C_DRX_P4

AF12

AH9 AJ9 AE10 AF10

AH18 AJ18 AJ7

SATARBIAS

AH7

GATEA20 H_A20M#

H_DPSLP# H_FERR#_S H_PWRGOOD H_IGNNE# H_INIT#

H_INTR KB_RST#

H_NMI H_SMI#

H_STPCLK# THRMTRIP_ICH#

R336 1K_0402_5%@R336 1K_0402_5%@ R337 1K_0402_5%@R337 1K_0402_5%@

CLK_PCIE_SATA# CLK_PCIE_SATA

2

LPC_AD[0..3] <38,39>

LPC_FRAME# <38,39> LPC_DRQ0# <39>

GATEA20 <38> H_A20M# <5>

R323 0_0402_5%R323 0_0402_5%

1 2 1 2

R338 24.9_0402_1%R338 24.9_0402_1%

12

R325 56_0402_5%R325 56_0402_5%

H_PWRGOOD <6> H_IGNNE# <5> H_INIT# <5>

H_INTR <5>

KB_RST# <38>

H_NMI <5> H_SMI# <5>

H_STPCLK# <5>

R331 54.9_0402_1%R331 54.9_0402_1%

1 2

CLK_PCIE_SATA# <23> CLK_PCIE_SATA <23>

1 2

H_DPRSTP#H_DPRSTP_R#

1 2

+VCCP

12

R328

R328 56_0402_5%

56_0402_5%

SATA_DTX_IRX_N4_CONN

C8260.01U_0402_16V7K C8260.01U_0402_16V7K

12

SATA_DTX_IRX_P4_CONN

C8270.01U_0402_16V7K C8270.01U_0402_16V7K

12

SATA_ITX_DRX_N4_CONN

C8240.01U_0402_16V7K C8240.01U_0402_16V7K

12

SATA_ITX_DRX_P4_CONN

C8250.01U_0402_16V7K C8250.01U_0402_16V7K

12

NEAR U42

10mils width less than 500mils

H_DPRSTP# <6,8,50> H_DPSLP# <6>

H_THERMTRIP#

1

R313

R324

R324 56_0402_5%

56_0402_5%

R313

10K_0402_5%

R315

10K_0402_5%

R319

56_0402_5%

R321

56_0402_5%

GATEA20

KB_RST#

H_DPRSTP#

H_DPSLP#

+VCCP

12

H_THERMTRIP# <5,8>

SATA_DTX_IRX_N4_CONN <35>

SATA_DTX_IRX_P4_CONN <35>

SATA_ITX_DRX_N4_CONN <35>

SATA_ITX_DRX_P4_CONN <35>

+3VS

12

+VCCP

@R319

@

12

@R321

@

12

H_FERR# <5>

B B

HDA_SDOUT_R

A A

5

4

Need check

+3VS

R339

R339 1K_0402_5%

1K_0402_5%

@

1 2

XOR Chain Entrance Strap

HDA_SDOUTICH_TP3 Description 0 0 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/10/15 2008/10/15

RSVD

0

Enter XOR Chain

1

Normal Operation

0

Set PCIE port config bit 1

11

Compal Secret Data

Deciphered Date

2

SATA PORT LIST

DEVICEPORT

HDD

0 1

ODD X

2

X

3

ESATA

4

X5

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

ICH9M(2/4)-LAN,IDELPC,RTC

JITR1_LA-4141P

1

0.1

28 53Wednesday, March 18, 2009

0.1

5

4

3

2

1

+3VS

SERIRQ PCI_CLKRUN# GPIO38 EC_THERM#

D D

OCP#

PM_BMBUSY# GPIO39 GPIO48

+3VALW

LINKALERT# CL_RST# XDP_DBRESET# ICH_RI# ICH_PCIE_WAKE# ICH_LOW_BAT# LID_OUT# WOL_EN

+3VALW

ICH_SMBCLK<23,31>

ICH_SMBDATA<23,31>

+3VS

H_STP_PCI#<23> H_STP_CPU#<23>

EC_LID_OUT#<38>

VGATE<8,50>

+3VS

GPIO7 GPIO13

C C

GPIO17 GPIO18 GPIO20 GPIO22

+3VS

SB_SPKR

GPIO57 DPRSLPVR ICH_RSVD

+3VALW

+3VS

CLK_14M_ICHCLK_48M_ICH

LINKALERT# ME__EC_CLK1 ME__EC_DATA1

ICH_RI#

OCP#

XDP_DBRESET# PM_BMBUSY#

LID_OUT#

H_STP_PCI# R_STP_CPU#

PCI_CLKRUN# ICH_PCIE_WAKE#

SERIRQ EC_THERM#

VRMPWRGD

SST_CTL OCP# GPIO7

EC_SMI# EC_SCI# GPIO13 GPIO17 GPIO18 GPIO20 GPIO22 GPIO27

SATA_CLKREQ# GPIO38 GPIO39 GPIO48 GPIO49 GPIO57

SB_SPKR MCH_ICH_SYNC# ICH_RSVD

XDP_DBRESET#<5> PM_BMBUSY#<8>

ICH_PCIE_WAKE#<31,32>

SERIRQ<38,39>

EC_THERM#<38>

CPUSB#<31,38>

EC_SMI#<38> EC_SCI#<38>

SATA_CLKREQ#<23>

SB_SPKR<36>

MCH_ICH_SYNC#<8>

CLK_14M_ICH CLK_48M_ICH

ICH_SUSCLK SLP_S3#

SLP_S4# SLP_S5#

S4_STATE# ICH_POK

ICH_LOW_BAT# PBTN_OUT#

CK_PWRGD_R CK_PWRGD M_PWROK

CL_VREF0_ICH CL_VREF1_ICH

CL_RST#

GPIO14

WOL_EN

CLK_14M_ICH <23> CLK_48M_ICH <23>

SB_INT_FLASH_SEL <40>

+3VALW

SLP_S3# <38> SLP_S4# <38> SLP_S5# <38>

DPRSLPVR

PBTN_OUT# <38>

CL_CLK0 <8> CL_CLK1

CL_DATA0 <8> CL_DATA1

CL_RST# <8>

+3VALW

EC_RSMRST#REC_RSMRST#R

DPRSLPVR <8,50>

M_PWROK <8> VGATE <8,50>

ACIN

ICH_POK <8,38>

CK_PWRGD <23>

ACIN <38,44,46>

M_PWROK

+3VS

+3VALW

POK <47>

+3VALW

USB_OC#6 USB_OC#1 USB_OC#2 USB_OC#4

USB_OC#5 USB_OC#7 USB_OC#9

B B

USB_OC#0

USB_OC#8 USB_OC#3 USB_OC#10 USB_OC#11

+3VS

VRMPWRGD

CLK_ENABLE#<50>

PCIE_RXN1<31>

PCIE_RXP1<31> PCIE_TXN1<31> PCIE_TXP1<31>

PCIE_RXN3<31>

PCIE_RXP3<31> PCIE_TXN3<31> PCIE_TXP3<31>

PCIE_RXN4<31> PCIE_RXP4<31> PCIE_TXN4<31>

PCIE_TXP4<31>

PCIE_RXN5<31> PCIE_RXP5<31> PCIE_TXN5<31>

PCIE_TXP5<31>

PCIE_IRX_PTX_N6<32> PCIE_IRX_PTX_P6<32> PCIE_ITX_C_PRX_N6<32> PCIE_ITX_C_PRX_P6<32>

SB_SPI_CS#1<27>

USB_OC#0<35>

USB_OC#4<41>

USB_OC#11<41>

A A

PCIE_RXN1

PCIE_RXP1

PCIE_C_TXN1

PCIE_C_TXP1

PCIE_RXN3

PCIE_RXP3

PCIE_C_TXN3

PCIE_C_TXP3

PCIE_RXN4

PCIE_RXP4

PCIE_C_TXN4

PCIE_C_TXP4

PCIE_RXN5

PCIE_RXP5

PCIE_C_TXN5

PCIE_C_TXP5

PCIE_IRX_PTX_N6 PCIE_IRX_PTX_P6 PCIE_ITX_PRX_N6 PCIE_ITX_PRX_P6

SB_SPI_CS#1

USB_OC#0

USB_OC#1

USB_OC#2

USB_OC#3

USB_OC#4

USB_OC#5

USB_OC#6

USB_OC#7

USB_OC#8

USB_OC#9

USB_OC#10

USB_OC#11

USBRBIAS

DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0

DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1

DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2

DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3

CLK_PCIE_ICH# CLK_PCIE_ICH

DMI_IRCOMP

USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N11 USB20_P11

DMI_RXN0 <8> DMI_RXP0 <8> DMI_TXN0 <8> DMI_TXP0 <8>

DMI_RXN1 <8> DMI_RXP1 <8> DMI_TXN1 <8> DMI_TXP1 <8>

DMI_RXN2 <8> DMI_RXP2 <8> DMI_TXN2 <8> DMI_TXP2 <8>

DMI_RXN3 <8> DMI_RXP3 <8> DMI_TXN3 <8> DMI_TXP3 <8>

CLK_PCIE_ICH# <23> CLK_PCIE_ICH <23>

USB20_N0 <35> USB20_P0 <35> USB20_N1 USB20_P1 USB20_N2 <41> USB20_P2 <41> USB20_N3 <31> USB20_P3 <31> USB20_N4 <41> USB20_P4 <41> USB20_N5 USB20_P5 USB20_N6 <41> USB20_P6 <41> USB20_N7 <34> USB20_P7 <34> USB20_N8 <31> USB20_P8 <31> USB20_N9 <31> USB20_P9 <31> USB20_N10 <31> USB20_P10 <31> USB20_N11 <41> USB20_P11 <41>

+1.5VS

EC_RSMRST#<38>

EC_RSMRST#R

+3VALW

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

3

Compal Secret Data

Deciphered Date

2

Title

ICH9M(3/4)-USB,GPIO,PCIE

Size Document Number Rev

C

Date: Sheet of

1

0.1

2008/10/15

+RTCVCC

D D

5

+5VS +3VS

ICH_V5REF_RUN

20 mils

ICH_V5REF_RUN

ICH_V5REF_SUS

4

+VCCP

3

1

C521 0.1U_0402_16V4ZC521 0.1U_0402_16V4Z

C518

0.1U_0402_16V4Z

2

0.01U_0402_16V7K

C519

1

2

1

C522 10U_0805_6.3V6MC522 10U_0805_6.3V6M

2

1

2

+VCCP

+1.5VS

2

1

+3VALW+5VALW

1 2

R409

R409 0_0402_5%

0_0402_5%

PM@

+3VS

ICH_V5REF_SUS

20 mils

1

C530

C530 1U_0603_10V4Z

1U_0603_10V4Z

C C

+1.5VS

B B

2

40 mils

+1.5VS

+3VS

VCCSUS1_5_ICH_1 VCCSUS1_5_ICH_2

+3VALW

+3VS

(SATA)

+VCCP

(DMI)

+3VS

+1.5VS+3VS

+3VALW

+1.5VS

+3VS

A A

+1.5VS

0.1U_0402_16V4Z

close to AC7

+1.5VS

(10UF*1, 2.2UF*1)

5

C551

1

2

C554

VCC_LAN1_05_INT_ICH_1 VCC_LAN1_05_INT_ICH_2 VCCCL1_05_ICH

1

2

10U_0805_10V4Z

+3VS

4

+3VS

KIWB3/B4_LA4551P

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Elm434[(0)-3.11 -0 330115

ICH9M(4/4)-POWER&GND

JITR1_LA-4141P

30 53Wednesday, March 18, 2009

1

0.1

A

Mini-Express Card for 3G Or TV Tuner

Mini-Express Card(Slot 1-TV TUNNER) 4.0mm high

ICH_PCIE_WAKE# BT_ACTIVE WLAN_ACTIVE WLAN_CLKREQ1#

PCIE_RXN3<29> PCIE_RXP3<29>

PCIE_TXN3<29> PCIE_TXP3<29>

EC_TX_P80_DATA EC_RX_P80_CLK

+3VALW

A

WLAN_CLKREQ#

+3VS_TV

TV_POWER_SW<38>

PLT_RST#<8,16,27,32>

CPUSB#<29,38>

+3VALW

+3VS

+5VS

+1.5VS

PLT_RST#

AO_SYSON

AO_SUSP#

CPUSB#

WLAN_CLKREQ#<23>

CLK_PCIE_WLAN#<23>

1 1

2 2

3 3

+1.5VS

+3VS

4 4

+3VALW

CLK_PCIE_WLAN<23>

PCIE_RXN5<29> PCIE_RXP5<29>

PCIE_TXN5<29> PCIE_TXP5<29>

CLK_PCIE_WLAN1#<23>

+3VALW

EC_TX_P80_DATA EC_RX_P80_CLK

CLK_PCIE_WLAN1<23>

+3VS

EC_TX_P80_DATA<38,39> EC_RX_P80_CLK<38,39>

ICH_PCIE_WAKE#<29,32>

BT_ACTIVE<41> WLAN_ACTIVE<41>

WLAN_CLKREQ1#<23>

EC_TX_P80_DATA<38,39> EC_RX_P80_CLK<38,39>

2005/09/27 modified. Base on OPTION GTM351E Datasheet Rev0.1

Vcc 3.3V +/- 8% Peak Icc 2750mA with max supply droop 50mA Average Icc 1000mA

+3VS_TV

+1.5VS_TV

+3VS +1.5VS

TV_RST#

B

USB20_N9 <29> USB20_P9 <29>

+3VS

+1.5VS_CARD1

+3VS_CARD1

+3VALW_CARD1

PERST#

B

+1.5VS_TV+3VS_TV

+1.5VS

+3VS_TV+1.5VS_TV

+3VS

+3VALW

USB20_N8 <29> USB20_P8 <29>

WLAN_LED#

+1.5VS_CARD1

+3VS_CARD1

+3VALW_CARD1

PLT_RST# <8,16,27,32>

3G_OFF# <38> WL_OFF# <38>

PLT_RST# <8,16,27,32> +3VALW +3VS

ICH_SMBCLK <23,29> ICH_SMBDATA <23,29>

WLAN_LED# <42>

AO_NEWCARD<38>

+3VS_TV

C

+3VS

USB20_N3<29> USB20_P3<29>

SUSP<43,48,49> AO_3G#<38>

SUSP AO_3G#

Mini-Exp3(e)8.680405 -62.16 Td[(M)-0.993546(i)3.642[(M(-)-2)106(E)6.18218( )13.0cm BT/R7 3 Tf0 0.99672 -1 -0 572aMPAL ELECTRONICS, INC., IN C.

ICH_PCIE_WAKE# BT_ACTIVE WLAN_ACTIVE WLAN_CLKREQ2#

CLK_PCIE_WLAN2#<23>

CLK_PCIE_WLAN2<23>

PCIE_RXN1<29> PCIE_RXP1<29>

PCIE_TXN1<29> PCIE_TXP1<29>

EC_TX_P80_DATA EC_RX_P80_CLK

+3V_WWAN

+3VALW

AO_SYSON

AO_SUSP#

Compal Secret Data

2007/10/15 2008/10/15

Compal Secret Data

AO_NEWCARD<38>

SYSON<38,43,48,49>

SUSP#<38,43,48,49>

USB20_N10<29> USB20_P10<29>

SUSP<43,48,49>

AO_NEWCARD

C

ICH_PCIE_WAKE#<29,32>

BT_ACTIVE<41> WLAN_ACTIVE<41>

WLAN_CLKREQ2#<23>

EC_TX_P80_DATA<38,39> EC_RX_P80_CLK<38,39>

SYSONSYSON

AO_NEWCARD

SUSP#

+3VS

SUSP

+5VALW

EC_SMB_CK1<38,45>

EC_SMB_DA1<38,45>

Security Classification

Issued Date

IssCCCId(E E E E E E E E E E ELECTRONICSC C 2009

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

USB20_N10_R USB20_P10_R

Deciphered Date

D

USB20_N3_R USB20_P3_R

UIM_VPP UIM_DATA

+UIM_PWR

D

E

+5VALW

+3V_WWAN

+1.5VS

+UIM_PWR UIM_DATA UIM_CLK UIM_RST UIM_VPP

USB20_N3_R USB20_P3_R

ICH_SMBCLK<23,29> ICH_SMBDATA<23,29>

Title

Size Document Number Rev

Date: Sheet of

+3VALW +3V_WWAN

+3VS

+3V_WWAN

3G_OFF# <38> WL_OFF# <38>

PLT_RST# <8,16,27,32>

+3V_WWAN

+3VS

ICH_SMBCLK <23,29> ICH_SMBDATA <23,29>

3G_LED#

+1.5VS_CARD1

ICH_PCIE_WAKE#<29,32>

+3VALW_CARD1

EXP_CLKREQ#<23>

CLK_PCIE_EXP#<23> CLK_PCIE_EXP<23>

3G_LED# <42>

+1.5VS

UIM_DATA +UIM_PWR

+3VS

+UIM_PWR UIM_RST UIM_CLK

USB20_N10_R

USB20_P10_R

CPUSB#<29,38>

+3VS_CARD1

PCIE_RXN4<29> PCIE_RXP4<29>

PCIE_TXN4<29> PCIE_TXP4<29>

CPUSB#

PERST#

CPUSB#

Compal Electronics, Inc.

Mini-Card/3G/FeliCa/BT

JITR1_LA-4141P

E

+3VS

0.1

31 53Wednesday, March 18, 2009

0.1

5

+3VALW

L29

@L29

@

1 2

MBK3216260YZF_2P

1

2

C591

MBK3216260YZF_2P

1 3

1

C585

0.1U_0603_25V7K

2

+LAN_AVDD

EMI 20080826

D

2

S

Q33

G

AO3414_SOT23-3

+5VALW

13

D

D D

+3V_LAN

C C

+1.2V_LAN

B B

Layout Notice : Filter place as close chip as possible.

A A

12

R440

R440 0_0805_5%

0_0805_5%

GIGA@

L30

1 2

MBK1608601YZF_2P

L31

1 2

MBK1608601YZF_2P

L32

1 2

MBK1608601YZF_2P

1 2

MBK1608601YZF_2P

C34

1 2

1000P_0402_50V7K

L34

1 2

MBK1608601YZF_2P

L35

1 2

MBK1608601YZF_2P

+2.5V12_LAN

L33

EN_WOL<38>

EN_WOL

12

R441

R441 0_0805_5%

0_0805_5%

100@

1

C586

0.1U_0402_16V4Z

2

C587

0.1U_0402_16V4Z

1

C589

2

0.047U_0402_16V4Z

1

C592

C592 1U_0603_10V4Z

1U_0603_10V4Z

2

1

C594

4.7U_0805_10V4Z

2

1

C598

4.7U_0805_10V4Z

2

1

C600

C600 1U_0603_10V4Z

1U_0603_10V4Z

2

Notice : 4.7u 6.3V capactor Thickness 1.25mm

5

D

2

G

S

EMI 20080826

1000P_0402_50V7K

+LAN_BIASVDD

+XTALVDD

1

C590

2

0.047U_0402_16V4Z

+AVDDL

1

C593

0.1U_0402_16V4Z

2

+GPHY_PLLVDD

1

C595

0.1U_0402_16V4Z

2

+PCIE_PLLVDD

1

C599

0.1U_0402_16V4Z

2

+PCIE_VDD

1

C601

0.1U_0402_16V4Z

2

Q34

Q34 2N7002_SOT23

2N7002_SOT23

C32

1 2

0.01U_0402_16V7K

4

2

C581

C581 10U_0805_10V4Z

10U_0805_10V4Z

1

2

C582

0.1U_0402_16V4Z

1

C583

0.1U_0402_16V4Z

2

Layout Notice : Place as close chip as possible.

R444 0_0402_5%GIGA@R444 0_0402_5%GIGA@

1 2

R442 0_0402_5%100@R442 0_0402_5%100@

1 2

+AVDDL

+PCIE_PLLVDD

+PCIE_VDD

1 2

R467 1K_0402_5%R467 1K_0402_5%

1 2

R469 0_0402_5%@R469 0_0402_5%@

1 2

R470 4.7K_0402_5%GIGA@R470 4.7K_0402_5%GIGA@

1 2

R472 4.7K_0402_5%GIGA@R472 4.7K_0402_5%GIGA@

1 2

R473 1K_0402_5%

1 2

100@

R474 1.24K_0402_1%

1 2

GIGA@

1

C605

C605 27P_0402_50V8J

27P_0402_50V8J

2

PCIE_IRX_PTX_P6<29> PCIE_IRX_PTX_N6<29> PCIE_ITX_C_PRX_P6<29> PCIE_ITX_C_PRX_N6<29>

+3V_LAN

ICH_PCIE_WAKE#<29,31> LAN_WAKE#<38>

PLT_RST#<8,16,27,31>

4

+2.5V12_LAN

+1.2V_LAN

+GPHY_PLLVDD

C596 0.1U_0402_16V7KC596 0.1U_0402_16V7K C597 0.1U_0402_16V7KC597 0.1U_0402_16V7K

R462 0_0402_5%@R462 0_0402_5%@

CLK_PCIE_LAN<23>

CLK_PCIE_LAN#<23>

PLT_RST#

R468 1K_0402_5%R468 1K_0402_5%

+3VS

CLKREQ_LAN#<23>

R477 200_0402_1%R477 200_0402_1%

1 2

Y4

1 2

1

25MHZ_20PY425MHZ_20P

C604

C604 27P_0402_50V8J

27P_0402_50V8J

2

+3V_LAN

1 2

R450 0_0402_5%GIGA@R450 0_0402_5%GIGA@

1 2

R456 0_0402_5%GIGA@R456 0_0402_5%GIGA@

1 2

R457 0_0402_5%100@R457 0_0402_5%100@

PCIE_IRX_C_PTX_P6 PCIE_IRX_C_PTX_N6

VMAIN_PRSNT

XTALO XTALI

VMAIN_PRSNT

XTALO XTALI

U24

5

VDDC_IO

55

VDDC_IO

13

VDDC

20

VDDC

34

VDDC

60

VDDC

39

AVDDL

45

AVDDL

51

AVDDL

35

GPHY_PLLVDDL

30

PCIE_PLLVDDL

27

PCIE_PLLVDDL

33

PCIE_VDDL

24

PCIE_VDDL

26

PCIE_TXD_P

25

PCIE_TXD_N

31

PCIE_RXD_P

32

PCIE_RXD_N

12

WAKE#

10

PERST#

29

PCIE_REFCLK_P

28

PCIE_REFCLK_N

54

VAUX_PRSNT

53

VMAIN_PRSNT

3

LOW_PWR

58

TEST1

57

TEST2

22

XTALO

21

XTALI

37

RDAC

11

CLK_REQ#

3

+1.2V_LAN

1

C574

4.7U_0805_10V4Z

2

1

C575

0.1U_0402_16V4Z

2

Layout Notice : 1.2V filter. Place as close chip as possible.

+2.5V12_LAN

+3V_LAN

61

15

19

VDDIO6VDDIO56VDDIO

VDDIO

69

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

3

12

R772

R772 0_0402_5%

0_0402_5%

100@

38

68

52

DC

GPIO1_SERIALDI

GPIO0_SERIALDO

GND

2008/03/25 2008/04/

36

BIASVDDH

23

XTALVDDH

48

AVDDH

42

AVDDH

49

TRD3_N

50

TRD3_P

47

TRD2_N

46

TRD2_P

43

TRD1_N

44

TRD1_P

41

TRD0_N

40

TRD0_P

2

LINKLED#

1

SPD100LED#

67

SPD1000LED#

66

TRAFFICLED#

8

GPIO2

9

UART_MODE

7 4

65

SCLK_EECLK

63

SI

64

SO_EEDATA

62

CS#

59

ENERGY_DET

+2.5V12_LAN

17

VDDC_IO

18

REGOUT12_IO

14

REGCTL12

16

SUPER_IDDQ

BCM5784MKMLG B0_QFN68_10X10

+LAN_BIASVDD

+XTALVDD

+LAN_AVDD

LAN_AVDDH AVDDH_LAN_TRD1N

LAN_TX3LAN_TX3+

LAN_TX2LAN_TX2+

LAN_TRD1N_TRD1P LAN_RX1+

LAN_TX0LAN_TX0+

R484 330_0402_5%R484 330_0402_5% R453 0_0402_5%R453 0_0402_5%

R454 0_0402_5%GIGA@R454 0_0402_5%GIGA@ R455 0_0402_5%100@R455 0_0402_5%100@

GPIO2

LAN_WP

LAN_CLK SI LAN_DATA CS#

R466 0_0402_5%@R466 0_0402_5%@

0_0402_5%

Compal Secret Data

LAN_TX3- <33> LAN_TX3+ <33>

LAN_TX2- <33> LAN_TX2+ <33>

LAN_RX1+ <33> LAN_TX0- <33>

LAN_TX0+ <33>

12 1 2 1 2 1 2

R458 4.7K_0402_5%@R458 4.7K_0402_5%@

1 2

R459 0_0402_5%@R459 0_0402_5%@

1 2

R460 0_0402_5%

1 2

GIGA@

R461 0_0402_5%

1 2

GIGA@

R463 4.7K_0402_5%R463 4.7K_0402_5%

1 2 1 2

R464 4.7K_0402_5%R464 4.7K_0402_5%

1 2

R465 4.7K_0402_5%R465 4.7K_0402_5%

1 2

R471 0_0402_5%

1 2

GIGA@

CTL12

MMJT9435T1G_SOT223

12

R475

Deciphered Date

2

+3V_LAN

1

Q36

2 3

1

2

CTL25

1

C602

0.1U_0402_16V4Z

2

4

C603

C603 10U_0805_10V4Z

10U_0805_10V4Z

1

C576

0.1U_0402_16V4Z

2

LAN_WP LAN_CLK LAN_DATA

C35

1 2

1000P_0402_50V7K

ACTIVITY# <33>

+3V_LAN

PCI_CBE#3 <27>

+1.2V_LAN

1

C577

0.1U_0402_16V4Z

2

+3V_LAN

12

R443

4.7K_0402_5%

AVDDH_LAN_TRD1N

LAN_TRD1N_TRD1P

1

C578

0.1U_0402_16V4Z

2

R446 0_0402_5%100@R446 0_0402_5%100@

1 2

R447 0_0402_5%GIGA@R447 0_0402_5%GIGA@

1 2

R448 0_0402_5%100@R448 0_0402_5%100@

1 2

R449 0_0402_5%GIGA@R449 0_0402_5%GIGA@

1 2

1

C579

0.1U_0402_16V4Z

2

C588 0.1U_0402_16V4ZC588 0.1U_0402_16V4Z

1 2

U23

8

VCC

7

WP

6

SCL

5

SDA

AT24C02_SO8

LAN_RX1LAN_AVDDH LAN_RX1+ LAN_RX1-

EMI 20080826

LINKLED# <33>

+3V_LAN

41

Q35

@ Q35

@

MBT35200MT1G_TSOP6

3

256

+2.5V12_LAN

0.1U_0402_16V4Z

Compal Electronics,Ltd.

Title

Broadcom LAN BCM5784M/5906M

Size Document Number Rev

C

Date: Sheet of

10U_0805_10V4Z

1

C839

C840

@

2

KIWB1/B2_LA4601P

1

A0

2

A1

3

NC

4

GND

LAN_RX1- <33>

0.1

32 53Wednesday, March 18, 2009

0.1

5

0513 : CARD_3V3

󲔊󴴸󵙄󵖄

100K change to 4.7u CAP==> 0521 : change C79 form 4.7u to 0.1u, add R47 100K ohm, change C526 form 1u to 4.7u

D D

1 2

3V3_IN RST# MODE SEL XTLO XTLI

1 2

USB20_N7 USB20_P7

C618 0.1U_0402_16V4ZC618 0.1U_0402_16V4Z

1 3 7

9 11 33

8 44 45 47 48

4

5 14

2 12

32

6 46

R498

0_0402_5%

1 2

C619

1 2 1 2

1

2

1

C622

0.1U_0402_16V4Z

2

XDPWR_SDPWR_MSPWR

USB20_N7<29>

USB20_P7<29>

4.7U_0603_6.3V6K

R491 0_0603_5%@R491 0_0603_5%@

+3VS

R492 0_0603_5%R492 0_0603_5%

+3VALW

keep supply 3.3V to 3V3_IN when S3

Vender suggesttion

C C

R495

R495 100K_0402_5%

100K_0402_5%

1 2

RST#

1

C623

C623 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

R497

6.19K_0402_1%

4

R489 0_0402_5%R489 0_0402_5%

U25

AV_PLL NC NC CARD_3V3 D3V3 D3V3

3V3_IN RST# MODE_SEL XTLO XTLI

DM DP GPIO0

RREF DGND

DGND AGND

AGND

RTS5158E-GR_LQFP48_7X7

󵝙󳒢

12

VREG

MS_D4

XD_CLE_SP19 XD_CE#_SP18 XD_ALE_SP17

SD_DAT2/XD_RE#_SP16

SD_DAT3/XD_WE#_SP15

SD_DAT4/XD_WP#/MS_D7_SP13

XD_RDY_SP14

SD_DAT5/XD_D0/MS_D6_SP12 SD_CLK/XD_D1/MS_CLK_SP11 SD_DAT6/XD_D7/MS_D3_SP10

MS_INS#_SP9 SD_DAT7/XD_D2/MS_D2_SP8 SD_DAT0/XD_D6/MS_D0_SP7 SD_DAT1/XD_D3/MS_D1_SP6

XD_D5_SP5

XD_D4/SD_DAT1_SP4

SD_CD#_SP3

SD_WP_SP2

XD_CD#_SP1

XTAL_CTR

MS_D5

EEDO EECS EESK

SD_CMD

C621 1U_0603_16V4ZC621 1U_0603_16V4Z

1 2

10 22 30

NC

43 42 41 40 39 38 37 35 34 31 29 28 27 26 25 23 21 20 19 18

EEDI

XTAL_CTR 3V3_IN

13 24

15 16 17 36

XDCLE XDCE#

XDALE SDDAT2_XDRE# SDDAT3_XDWE#

XD_RDY SDDAT4_XDWP#_MSD7 SDDAT5_XDD0_MSD6 SDCLK_XDD1_MSCLK SDDAT6_XDD7_MSD3

MS_INS# SDDAT7_XDD2_MSD2 SDDAT0_XDD6_MSD0 SDDAT1_XDD3_MSD1

XDD5_MSBS XDD4_SDDAT1

SDCD SDWP XDCD

12

R496

0_0603_5%

SD_CMD

3

R490

100K_0402_5%

R493

0_0402_5%

R494

0_0402_5%

XDPWR_SDPWR_MSPWR

1 2

MS-SCLK

12

SD-CLK

12

1

C620

0.1U_0402_16V4Z

2

JREAD1

SDDAT4_XDWP#_MSD7 SDDAT1_XDD3_MSD1 SDDAT7_XDD2_MSD2

SDDAT6_XDD7_MSD3 SDDAT4_XDWP#_MSD7 SDDAT2_XDRE# SDCD SDWP

SDDAT5_XDD0_MSD6 XDD4_SDDAT1

SDDAT0_XDD6_MSD0 SDDAT0_XDD6_MSD0 SDDAT3_XDWE#

XDCE# SDDAT2_XDRE# SDCLK_XDD1_MSCLK XDCLE XDALE XD_RDY XDCD

JREAD1

33

xD-WP

8

xD-D3

9

xD-D2

24

MS-DATA3

27

SD-DAT4

30

SD-DAT2

1

SD-CD

2

SD-WP

32

xD-D0

6

xD-D5

7

xD-D4

5

xD-D6

34

xD-WE

3

xD-VCC

4

xD-D7

37

xD-CE

38

xD-RE

10

xD-D1

36

xD-CLE

35

xD-ALE

39

xD-R/B

40

xD-CD

TAITW_R015-A10-LM_NR

ME@

23

SD-DAT5

14

SD-DAT0

25

SD-CMD

29

SD-DAT3

12

SD-DAT1

26

MS-SCLK

13

MS-BS

22

MS-INS

28

MS-VCC

15

MS-DATA1

19

MS-DATA2

17

MS-DATA0

20

SD-CLK

18

SD-DAT6

16

SD-DAT7

21

SD-VCC

31

7IN1-GND

11

7IN1-GND

41

GND

42

GND

R663

R663 33_0402_5%

33_0402_5%

@

1 2

C805

C805 22P_0402_50V8J

22P_0402_50V8J

@

MSCLK and SDCLK solution󰻈󳑱, (

󱭐

SD_DAT1

󴽬󲋮󱅹

1

SDDAT5_XDD0_MSD6 SDDAT0_XDD6_MSD0

SD_CMD

SDDAT3_XDWE#

XDD4_SDDAT1

MS-SCLK

XDD5_MSBS

MS_INS#

SDDAT1_XDD3_MSD1XDD5_MSBS SDDAT7_XDD2_MSD2

SD-CLK SDDAT6_XDD7_MSD3SDDAT6_XDD7_MSD3 SDDAT7_XDD2_MSD2

R665

R665 33_0402_5%

33_0402_5%

@

1 2

C807

C807 22P_0402_50V8J

22P_0402_50V8J

@

@R496

󴦻󰷕󵙄󵖄󲕸󵝙󳒢󳲯 󰺏󴨔󵚩󴼚

RTS5158E󳗍pin23

XDPWR_SDPWR_MSPWR

SD-CLKCLK_48M_CR MS-SCLK

R664

R664 33_0402_5%

33_0402_5%

@

1 2

C806

C806 22P_0402_50V8J

22P_0402_50V8J

@

RTS5158E󰾽).

EMI

B B

CLK_48M_CR

47P_0402_50V8J

C625

CLK_48M_CR<23>

MODE SEL

12

1

@C625

@

R500

10K_0402_5%

2

@

0521_C503 and R436 should be open

A A

5

R499 0_0603_5%R499 0_0603_5%

1 2

C624

1 2

6P_0402_50V8D

@

Y5

12MHZ_16P_6X12000012

@

C626

1 2

6P_0402_50V8D

@

4

XTLI

12

XTLO

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

1394+3 in 1 Card

LA-3691P

1

34 53Wednesday, March 18, 2009

1.0

A

B

C

D

E

F

G

H

SATA HDD Conn.

JHDD

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12

GND

22

V12

GND

FOX_LD2122H-S43_NR

ME@

SATA ODD Conn.

JODD

1

SATA_ITX_DRX_P1<28>

SATA_DTX_C_IRX_N1<28>

SATA_DTX_C_IRX_P1<28>

23 24

CONN need change to new CONN

SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 SATA_DTX_IRX_P1

SATA_ITX_DRX_N1<28>

C635 0.01U_0402_16V7KC635 0.01U_0402_16V7K

1 2

C636 0.01U_0402_16V7KC636 0.01U_0402_16V7K

1 2

SATA_ITX_DRX_P1 SATA_ITX_DRX_N1

SATA_DTX_IRX_N1

+5VS

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

DP

9

+5V

10

+5V

11

MD

12

GND

13

GND

OCTEK_SLS-13SB1G_RV

ME@

1

C631

C631 10U_0805_10V4Z

10U_0805_10V4Z

2

SATA_ITX_DRX_P0 SATA_ITX_DRX_N0

SATA_DTX_IRX_N0 SATA_DTX_IRX_P0

+3VS

+5VS

1

@

C632

0.1U_0402_16V4Z

2

SATA_ITX_DRX_P0<28>

SATA_DTX_C_IRX_N0<28>

1 1

SATA_DTX_C_IRX_P0<28>

+5VS +3VS

1

C627

C627 1000P_0402_50V7K

1000P_0402_50V7K

2

2 2

SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0

1

C628

0.1U_0402_16V4Z

2

1

C629

C629 1U_0603_10V4Z

1U_0603_10V4Z

2

SATA_ITX_DRX_N0<28>

C634 0.01U_0402_16V7KC634 0.01U_0402_16V7K

1 2

C633 0.01U_0402_16V7KC633 0.01U_0402_16V7K

1 2

1

C630

C630 10U_0805_10V4Z

10U_0805_10V4Z

2

+USB_VCCB

1

+

C733

150U_D2_6.3VM

2

SATA_ITX_DRX_P4_CONN<28>

3 3

C732 0.1U_0402_16V4ZC732 0.1U_0402_16V4Z

4 4

A

SATA_ITX_DRX_N4_CONN<28>

SATA_DTX_IRX_N4_CONN<28>

SATA_DTX_IRX_P4_CONN<28>

+5VALW

U34

1

GND

2

12

USB_ON<38,41>

USB_ON

IN

3

IN

4

EN

G545A1P1U_SO8

B

W=80mils

1

C734

C734 470P_0402_50V7K

470P_0402_50V7K

2

USB20_N0<29> USB20_P0<29>

SATA_ITX_DRX_P4_CONN SATA_ITX_DRX_N4_CONN

SATA_DTX_IRX_N4_CONN SATA_DTX_IRX_P4_CONN

+USB_VCCB

8

OUT

7

OUT

6

OUT

5

OC#

ESATA and USB Conn.

JESATA

1

VBUS

2

D-

3

D+

4

GND

5

GND

6

A+

7

A-

8

GND

9

B-

10

B+

11

GND

12

GND

13

GND

14

GND

15

GND

TYCO_1759576-1

ME@

1

2

USB20_N0 USB20_P0

C735

1000P_0402_50V7K@

USB_OC#0 <29>

C

ESATA

USB

A+ = RXP A- = RXN

B- = TXN B+ = TXP

Security Classification

D

Compal Secret Data

2007/10/15 2008/10/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

E

Compal Secret Data

Deciphered Date

F

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

HDD & ODD Connector

KIWB1/B2_LA4601P

G

35 53Wednesday, March 18, 2009

H

0.1

5

+5VS

+5VDDA_CODEC

D D

4

HDA_RST_CODEC# HDA_SYNC_CODEC HDA_SDOUT_CODEC

3

2

1

+5VDDA_CODEC+3VS +3VDD_CODEC

BITCLK

GNDA

INT_MIC_L

+MIC1_VREFO_L

INT_MIC_L

INT_MIC_R

MIC_INTL MIC_INTR

MIC_INL MIC_INR

+5VDDA_CODEC

+3VDD_CODEC

+IOVDD_CODEC

C_LINE_OUTL C_LINE_OUTR

LINE_OUTL LINE_OUTR

SPDIF_OUT <37>

C C

GNDA

INT_MIC_R

GNDA

EXT_MIC_L<37>

EXT_MIC_R<37>

HDA_BITCLK_CODEC<8,28> HDA_SDOUT_CODEC<8,28>

HDA_SDIN2<28> HDA_RST_CODEC#<8,28> HDA_SYNC_CODEC<8,28>

GPO_AUD<38>

MIC_JD<37>

PLUG_IN<37>

MIC_EXTL_C MIC_EXTR_C

PC_BEEP

BITCLK

HDA_SDOUT_CODEC

HDA_RST_CODEC# HDA_SYNC_CODEC

SENSEA SENSEB

MONO_OUT

MONO_OUT <37>

+MIC1_VREFO_L +MIC2_VREFO

HP_OUTL <37> HP_OUTR <37>

EAPD<38>

B B

+5VAMP

+3VS

GAIN0 GAIN1

LINE_OUTL

PC_BEEPPC_BEEP1

A A

BEEP#<38>

LINE_OUTR

LIN RIN

AMP_OFF# EC_MUTE#

SPK_L1-

SPK_L1- <37>

SPK_R1-

SPK_R1- <37>

SPK_L2+

SPK_L2+ <37>

SPK_R2+

SPK_R2+ <37>

EC_MUTE# <37,38>

+5VAMP +5VAMP

GAIN1GAIN0

SB_SPKR<29>

5

4

3

2

1

5

4

3

2

1

Audio Jack

EMI 20080826

L49

D D

EXT_MIC_L<36>

EXT_MIC_L

47P_0402_50V8J

C669

SubWoofer Conn.

Speaker Connector

EXT_MIC_R<36>

WOOFER-

WOOFER+

SPK_R1-<36> SPK_R2+<36> SPK_L1-<36> SPK_L2+<36>

C C

SPK_R1SPK_R2+ SPK_L1SPK_L2+

EMI 20080826

L43 FBMA-L11-160808-121LMA30TL43 FBMA-L11-160808-121LMA30T

1 2

L44 FBMA-L11-160808-121LMA30TL44 FBMA-L11-160808-121LMA30T

1 2

L45 FBMA-L11-160808-121LMA30TL45 FBMA-L11-160808-121LMA30T

1 2

L46 FBMA-L11-160808-121LMA30TL46 FBMA-L11-160808-121LMA30T

1 2

L47 FBMA-L11-160808-121LMA30TL47 FBMA-L11-160808-121LMA30T

1 2

L48 FBMA-L11-160808-121LMA30TL48 FBMA-L11-160808-121LMA30T

1 2

20mil

WOWO+ SPK_R1-_CONN SPK_R2+_CONN SPK_L1-_CONN SPK_L2+_CONN

JSPK1

1

2

3

4

5

7

5

G1

6

8

6

G2

ACES_87213-0600G

MIC_JD<36>

EXT_MIC_R

47P_0402_50V8J

MIC_JD

1K_0402_5%

C671

R537

@R537

@

L49

1 2

FBMA-L10-160808-121LMT_2P

1

2

GNDA

L50

1 2

FBMA-L10-160808-121LMT_2P

1

2

GNDA

12

@R538

@

1K_0402_5%

GNDA

R538

EMI 20080826

HP_OUTR<36> HP_OUTL<36>

PLUG_IN<36>

B B

HP_OUTR HP_OUTL

PLUG_IN

+5VS

1

C677

0.1U_0402_16V4Z

2

L51

L51 FBMA-L10-160808-121LMT_2P

FBMA-L10-160808-121LMT_2P L52

L52 FBMA-L10-160808-121LMT_2P

FBMA-L10-160808-121LMT_2P

1

2

GNDA

1

2

GNDA

1 2 1 2

SPDIF_OUT<36>

EXT_MIC_L-2

C670

@C670

@

10P_0402_50V8J

EXT_MIC_R-2

C672

@C672

@

10P_0402_50V8J

220P_0402_50V7K

1

C67310P_0402_50V8J@C67310P_0402_50V8J

@

2

GNDA

1 2

SPDIF_OUT

C676

C674

PR-OUT PL-OUT

12

GNDAGNDA

220P_0402_50V7K

C675

1 2

Audio Jack

MIC IN

JMIC1

1 2

3 4 5

6

G

SINGA_2SJ-0960-C02

ME@

Headphone

JHP1

6 1

4 5 7

3 8

2

SINGA_2SJ1533-000111

33K_0402_5%

1 2

R620

+5VAMP

WIN1

WIN2

4

R620

1500P_0402_50V7K

1 2

C762

W=40mil

U39

6

VDD

SHUTDOWN#

3

IN+

4

IN-

2

BYPASS

APA3011XA-TRL_MSOP8

GND

1 5

Vo+

8

Vo-

7

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

G1442 SubWoofer Amplifier

1nd = APA3011 (SA00001JM00) 2nd = TPA6211 (SA621110010 )

R618

C759

MONO_OUT<36>

A A

MONO_OUT

5

0.018U_0603_50V7J

C759

1 2

8.45K_0402_1%

0.01U_0402_16V7K

1 2

C760

C760 68K_0402_5%

68K_0402_5%

1 2

R619

C761

2.2U_0603_6.3V4Z

2

1

WOOFER+ WOOFER-

+3VALW

ONLY FOR 15.6W

R621

R621 10K_0402_5%

10K_0402_5%

@

1 2

0_0402_5%

2008/03/25 2008/04/

3

EC_MUTE#AMP_OFF#

R622

12

Compal Secret Data

EC_MUTE# <36,38>

Deciphered Date

Compal Electronics,Ltd.

Title

AMP,Audio speaker CONN

Size Document Number Rev

Custom

Custom Date: Sheet of

Date: Sheet of

2

Date: Sheet of

KIWB1/B2_LA4601P

1

37 53Wednesday, March 18, 2009

0.1

L38

+3VALW

L38

FBM-11-160808-601-T_0603

KB_RST#<28>

12

C687 22P_0402_50V8J@C687 22P_0402_50V8J@

C686

0.1U_0402_16V4Z

ECAGND

2

1

KSO1 KSO2

KSO[0..15]<39>

KSI[0..7]<39,42>

0_0402_5%

1 2

+3VALW +EC_AVCC

ENE UPDATE 10/21

+3VALW

R550

R550 10K_0402_5%

10K_0402_5%

1 2

LAN_WAKE#<32>

EC_PME#

PCI_PME#<27>

+3VALW

+5VALW

1 2

R557 100K_0402_1%@R557 100K_0402_1%@

1 2

R558 100K_0402_1%@R558 100K_0402_1%@

1 2

R559 10K_0402_5%@R559 10K_0402_5%@

FRD#SPI_SO

FSEL#SPICS#

KSO17

+3VALW

EC_SMB_CK1

EC_SMB_DA1

R779

GATEA20<28>

SERIRQ<29,39>

LPC_FRAME#<28,39>

LPC_AD3<28,39> LPC_AD2<28,39> LPC_AD1<28,39> LPC_AD0<28,39>

CLK_PCI_LPC<23>

PCI_RST#<27,39>

EC_SCI#<29>

PWR_LED_SC#<42>

KSI3<39,42> KSI4<39>

KSO[0..15] KSI[0..7]

KSO16<42>

KSO17<42>

EC_SMB_CK1<31,45> EC_SMB_DA1<31,45>

EC_SMB_CK2<5,16,42> EC_SMB_DA2<5,16,42>

SLP_S3#<29> SLP_S5#<29>

EC_SMI#<29>

LID_SW#<39> +3VALW +3VALW

EC_TX_P80_DATA<31,39> EC_RX_P80_CLK<31,39>

EC_SMB_CK1

EC_SMB_DA1

1 2

R552 4.7K_0402_5%R552 4.7K_0402_5%

KILL_SW#<39>

FAN_SPEED1<5>

3G_OFF#<31>

ON/OFF#<42>

AO_NEWCARD<31>

NUM_LED#<39>

+3VALW

C680

0.1U_0402_16V4Z

C680

0.1U_0402_16V4Z

1

2

KB_RST#_EC

LPC_AD3 LPC_AD2 LPC_AD1 BATT_TEMP LPC_AD0

EC_RST#

EC_SCI#

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

KSO16 KSO17

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

EC_SMI# LID_SW#

FAN_SPEED1

EC_TX_P80_DATA EC_RX_P80_CLK

AO_NEWCARD

XCLKI XCLKO

C685

1000P_0402_50V7K

C685

1000P_0402_50V7K

1

2

+EC_AVCC

CHARGE_LED0# CHARGE_LED1#

WIRELESS_LED#

ENE ISSUE CHANGE FROM 4.7uF TO 1uF

needed to update to D2 version

ECAGND

20080606

SA00001J570

INVT_PWM BEEP#

ACOFF

BATT_OVP CPUSB# TSATN#_EC

DAC_BRIG EN_FAN1 IREF

USB_ON AO_3G# TP_LOCK# TP_CLK TP_DATA

FRD#SPI_SO FWR#SPI_SI SPI_CLK FSEL#SPICS#

RCIRRX I2C_INT I2C_INT

CAPS_LED#

SYSON

ACIN

EC_LID_OUT#

EC_ON

MUTE_LED

ICH_POK_EC ICH_POK

BKOFF#

EC_THERM#

SUSP#

PBTN_OUT#

1

2

R542 0_0603_5%@R542 0_0603_5%@

1 2

C691

C691 1U_0603_10V4Z

1U_0603_10V4Z

INVT_PWM <25> BEEP# <36> NOVO# <42> ACOFF <46>

BATT_TEMP <45>

BATT_OVP <46> ADP_I <46>

CPUSB# <29,31>

DAC_BRIG <25> EN_FAN1 <5> IREF <46> CHGVADJ <46>

EC_MUTE#

EC_MUTE# <36,37> USB_ON <35,41>

AO_3G# <31>

TP_LOCK# <40>

TP_CLK <39>

TP_DATA <39>

EN_WOL <32> BATT_SEL_EC <46> CMOS_OFF# <41>

FRD#SPI_SO <40>

FWR#SPI_SI <40>

FSEL#SPICS# <40>

RCIRRX <42>

I2C_INT <42>

FSTCHG <46>

CHARGE_LED0# <40>

CAPS_LED# <39>

CHARGE_LED1# <40>

PWR_LED# <40>

SYSON <31,43,48,49> VR_ON <50> ACIN <29,44,46>

EC_RSMRST# <29> EC_LID_OUT# <29> EC_ON <42>

MUTE_LED# <42>

BKOFF# <25> WL_OFF# <31> TV_POWER_SW <31> WIRELESS_LED# <40>

SLP_S4# <29>

ENBKL <25>

EAPD <36>

EC_THERM# <29>

SUSP# <31,43,48,49> PBTN_OUT# <29> BT_OFF# <41>

R546 10K_0402_5%@R546 10K_0402_5%@

SPI_CLK <40>

TSATN# <8> GPO_AUD <36>

1 2

USB_ON

1 2

R555 0_0402_5%

@

SUSP#

+3VALW

KB926 SPI STRAP PIN

+3VS

ICH_POK <8,29>

+3VS

TP_CLK TP_DATA

R545 4.7K_0402_5%R545 4.7K_0402_5%

BATT_OVP BATT_TEMP ACIN

1 2

C688 100P_0402_50V8JC688 100P_0402_50V8J

1 2

C689 100P_0402_50V8JC689 100P_0402_50V8J

+5VS

+3VS

R562

2.2K_0402_5%

1

@

C694

C694 100P_0402_50V8J

100P_0402_50V8J

2

EC_SMB_CK2 EC_SMB_DA2

X1

2

IN

NC

3

OUT

32.768KHZ_12.5P_1TJS125BJ2A251

NC

XCLKO

1 4

XCLKI

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

BIOS & EC I/O Port

JITR1_LA-4141P

38 53Wednesday, March 18, 2009

0.1

5

4

3

2

1

INT_KBD Conn.

KSI[0..7]

D D

C C

KSO[0..15]

KSO2

C697 100P_0402_50V8J@C697 100P_0402_50V8J@

KSO15

C699 100P_0402_50V8J@C699 100P_0402_50V8J@

KSO6

C701 100P_0402_50V8J@C701 100P_0402_50V8J@

KSO8

C703 100P_0402_50V8J@C703 100P_0402_50V8J@

KSO13

C705 100P_0402_50V8J@C705 100P_0402_50V8J@

KSO12

C707 100P_0402_50V8J@C707 100P_0402_50V8J@

KSO11

C709 100P_0402_50V8J@C709 100P_0402_50V8J@

KSO10

C711 100P_0402_50V8J@C711 100P_0402_50V8J@

KSO3

C713 100P_0402_50V8J@C713 100P_0402_50V8J@

KSO4

C715 100P_0402_50V8J@C715 100P_0402_50V8J@

KSI0

C717 100P_0402_50V8J@C717 100P_0402_50V8J@

KSO0

C719 100P_0402_50V8J@C719 100P_0402_50V8J@

CONN PIN define need double check

To TP/B Conn.

TP_CLK<38> TP_DATA<38>

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

KSI[0..7] <38,42> KSO[0..15] <38>

1

@

C724

C724 100P_0402_50V8J

100P_0402_50V8J

2

+5VS

C723

0.1U_0402_16V4Z

1

@

C725

C725 100P_0402_50V8J

100P_0402_50V8J

2

KSO1 KSO7 KSI2 KSO5 KSI3 KSO14 KSI7 KSI6 KSI5 KSI4 KSO9 KSI1

TP_CLK TP_DATA

C698 100P_0402_50V8J@C698 100P_0402_50V8J@

1 2

C700 100P_0402_50V8J@C700 100P_0402_50V8J@

1 2

C702 100P_0402_50V8J@C702 100P_0402_50V8J@

1 2

C704 100P_0402_50V8J@C704 100P_0402_50V8J@

1 2

C706 100P_0402_50V8J@C706 100P_0402_50V8J@

1 2

C708 100P_0402_50V8J@C708 100P_0402_50V8J@

1 2

C710 100P_0402_50V8J@C710 100P_0402_50V8J@

1 2

C712 100P_0402_50V8J@C712 100P_0402_50V8J@

1 2

C714 100P_0402_50V8J@C714 100P_0402_50V8J@

1 2

C716 100P_0402_50V8J@C716 100P_0402_50V8J@

1 2

C718 100P_0402_50V8J@C718 100P_0402_50V8J@

1 2

C720 100P_0402_50V8J@C720 100P_0402_50V8J@

1 2

JP15

4

3

2

1

E&T_6905-E04N-00R

ME@

+5VS

NUM_LED#<38>

CAPS_LED#<38>

12 12

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10

KSO15

R770470_0402_5% R770470_0402_5% R771470_0402_5% R771470_0402_5%

ACES_85201-3005N

JP13

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

G1

32

G2

+3VALW

1 2

R565 0_0402_5%R565 0_0402_5%

Lid Switch

C721

0.1U_0402_16V4Z

+VCC_LID

1

2

EC_TX_P80_DATA<31,38> EC_RX_P80_CLK<31,38>

R566 100K_0402_5%R566 100K_0402_5%

2

A3212ELHLT-T_SOT23W-3

VDD

OUTPUT

GND

1

EC DEBUG PORT

+3VALW

EC_TX_P80_DATA EC_RX_P80_CLK

1 2

3

U30

Kill Switch

JP14

1 2 3 4

ACES_85205-0400

ME@

2

C722

10P_0402_50V8J

1

1 2 3 4

LID_SW# <38>

CONN PIN define need double check

+3VALW

B B

KILL_SW#<38>

KILL_SW#

R632

100K_0402_5%

12

LSSM12-P-V-T-R_3P

3

2

1

SW2

FOR LPC SIO DEBUG PORT

JP16

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

A A

16

17

18

19

20

ACES_85201-2005

ME@

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LPC_DRQ0# PCI_RST#

CLK_PCI_DB SERIRQ

5

+5VS

+3VS

CLK_14M_SIO <23> LPC_AD0 <28,38> LPC_AD1 <28,38> LPC_AD2 <28,38> LPC_AD3 <28,38>

LPC_FRAME# <28,38> LPC_DRQ0# <28> PCI_RST# <27,38>

CLK_PCI_DB <23>

SERIRQ <29,38>

R567 10K_0402_5%

12

@

4

Security Classification

2007/10/15 2008/10/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

B

B Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

KB /SW /LPC Debug Conn.

KIWB1/B2_LA4601P

39 53Wednesday, March 18, 2009

1

0.1

FOR EC 16M SPI ROM

INPUT A B L L H L L H H H

+3VALW

1

C726

0.1U_0402_16V4Z

2

FRD#SPI_SO<38>

FRD#SPI_SO SPI_SO

R568 15_0402_5%R568 15_0402_5%

1 2

INT_SPI_CS#

OUTPUT Y

L

INT_SPI_CS#

H

R573 15_0402_5%R573 15_0402_5%

1 2

MC74VHC1G32DFT2G_SC70-5~D

20mils

U31

1

CS#

2 3 4

VCC

SO

HOLD#

WP#

SCLK

GND

@ U32

@

4

+3VALW

U32

O

SI

5

P

INB INA

G

3

MX25L1605AM2C-12G_SO8

12

R812

R812 10K_0402_5%

10K_0402_5%

8 7 6 5

INT_FLASH_EN#

1 2

R569 15_0402_5%R569 15_0402_5%

SPI_SI FWR#SPI_SI

FSEL#SPICS#

1 2

R570 15_0402_5%R570 15_0402_5%

1 2

R572

@R572

100K_0402_5%

@

1 2

FSEL#SPICS# <38>

SPI_CLKSPI_CLK_R

SPI_CLK <38>

FWR#SPI_SI <38>

SPI_CLK_R

R571

33_0402_5%

C727

22P_0402_50V8J

12

47_0402_5%

R832

C861

68P_0402_50V8J

3G@

1 2 1

3G@C861

3G@

2

EMI 3G

H

R574 0_0402_5%R574 0_0402_5%

H

FSEL#SPICS#

SB_INT_FLASH_SEL<29>

SPI_SO

SC500005B00,If=5mA,Vf=2.7V~3.15V,R=460~390ohm

WHITE

CHARGE_LED0#<38>

CHARGE_LED1#<38>

AMBER

PWR_LED#<38>

CHARGE_LED0#

CHARGE_LED1#

TP_LOCK#<38>

12-21SYGCS530-E1S155TR8_W

BATT_CHG_LED#

R625 470_0402_5%R625 470_0402_5%

R626 470_0402_5%R626 470_0402_5%

BATT_LOW_LED#

WHITE

WIRELESS_LED#<38>

WHITE

12-21SYGCS530-E1S155TR8_W

1 2

+3VALW

JP17

2

112

4

334

SPI_CLK_R

6

556

8

778

E&T_2941-G08N-00E~DME@

LED

LED1

21

1 2

LED4

R577 750_0402_5%R577 750_0402_5%

21

19-213A-T1D-CP2Q2HY-3T_WHITE

LED5

21

INT_FLASH_EN#

SPI_SI

R624 470_0402_5%R624 470_0402_5%

1 2

2

3

LED7 12-22-S2ST3D-C30-2C_WHI-ORGLED7 12-22-S2ST3D-C30-2C_WHI-ORG

1 2

R627 470_0402_5%R627 470_0402_5%

1 2

1

+5VALW

+5VS

+5VALW

1

FD1FD1

H1 HOLEAH1HOLEA

1

H7 HOLEAH7HOLEA

1

H15

H15 HOLEA

HOLEA

1

H22

H22 HOLEA

HOLEA

1

H27

H27 HOLEA

HOLEA

1

FD2FD2

H2 HOLEAH2HOLEA

1

H8 HOLEAH8HOLEA

1

H16

H16 HOLEA

HOLEA

1

H23

H23 HOLEA

HOLEA

1

H28

H28 HOLEA

HOLEA

1

FD3FD3

H3 HOLEAH3HOLEA

1

H9 HOLEAH9HOLEA

1

H17

H17 HOLEA

HOLEA

1

H24

H24 HOLEA

HOLEA

1

FD4FD4

H4 HOLEAH4HOLEA

1

H10

H10 HOLEA

HOLEA

1

H18

H18 HOLEA

HOLEA

1

H25

H25 HOLEA

HOLEA

1

H5 HOLEAH5HOLEA

1

H11

H11 HOLEA

HOLEA

1

H19

H19 HOLEA

HOLEA

1

H26

H26 HOLEA

HOLEA

1

H6 HOLEAH6HOLEA

1

H12

H12 HOLEA

HOLEA

1

H20

H20 HOLEA

HOLEA

1

H21

H21 HOLEA

HOLEA

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

LED/EC SPI ROM

KIWB1/B2_LA4601P

40 53Wednesday, March 18, 2009

0.1

A

B

C

D

E

+5VALW

+USB_VCCA

1 1

USB_ON<35,38>

USB_ON

USB_OC#4 <29> USB_OC#11 <29>

2 2

+USB_VCCA

USB20_P4<29> USB20_N4<29>

USB20_N11<29> USB20_P11<29>

USB20_P4 USB20_N4

USB20_N11 USB20_P11

+5VS

3 3

BT_OFF#<38>

+3VS

+3VS_BT

CMOS1

CMOS_OFF#<38>

4 4

USB20_N2<29> USB20_P2<29>

USB20_N2 USB20_P2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI

A

B

C

BT_LED#<42>

Compal Secret Data

USB20_N6<29>

USB20_P6<29> BT_ACTIVE<31> WLAN_ACTIVE<31>

USB20_N6 USB20_P6 BT_ACTIVE WLAN_ACTIVE BTON_LED

Title

Size Document Number Rev

D

Date: Sheet of

E

+3VALW

R581

R581 100_0603_5%

100_0603_5%

@

1 2

RCIRRX<38>

RCIRRX PWR_LED_SC#

+3VALW

1 2

22P_0402_50V8J

1 2

R583 100_0603_5%R583 100_0603_5%

CIR

R582

33_0402_5%

C739

4.7U_0805_10V4Z

1

2

IR1

1

Vout

2

1

C740

2

VCC

3

GND

4

GND

IRM-V538/TR1_3P

PWR_LED_SC#<38>

NOVO_BTN#

3

+5VALW

12

NOVO_BTN#

ON/OFFBTN#

2

D29

D29 PJSOT24C 3P C/A SOT-23

PJSOT24C 3P C/A SOT-23

1

R780

R780 750_0402_5%

750_0402_5%

JP23

1

2

3

4

5

6

7

GND

8

GND

ACES_85201-06051

ME@

MUTE_LED#<38>

KSO16<38> KSI2<38,39> KSO17<38> KSI3<38,39>

Power Bottom Board Conn. 6 pin

Bottom Board Conn. 6 pin

MUTE_LED# KSO16 KSI2 KSO17 KSI3ON/OFFBTN#

KSI2

2

3

D30

D30 PJDLC05_SOT23-3

PJDLC05_SOT23-3

+5VS

KSI3KSO16

12

R781

R781 750_0402_5%

750_0402_5%

JP25

1 2 3 4 5 6 7 8

ACES_85201-06051

ME@

1 2 3 4 5 6 GND GND

3

2

KSO17

D33

D33 PJDLC05_SOT23-3

PJDLC05_SOT23-3

ON/OFF switch

Power Button

TOP Side

Bottom Side

ON/OFFBTN#

EC_ON<38>

EC_ON

SW1

@SW1

@

1 2

5

6

2 1

J22MM J22MM

2 1

J32MM J32MM

R587

R587 10K_0402_5%

10K_0402_5%

1 2

NOVO#<38> 51_ON#<44>

3 4

SMT1-05_4P

D26

1

DAN202UT106_SC70-3

NOVO#

51_ON#

3 2

Q44

2N7002_SOT23-3

+3VALW

R589

R589 100K_0402_5%

100K_0402_5%

1 2

2

G

+3VALW

R584

R584 100K_0402_5%

100K_0402_5%

1 2

2

1

13

D

S

D28

2 3

DAN202UT106_SC70-3

ON/OFF# 51_ON#

C741

C741 1000P_0402_50V7K

1000P_0402_50V7K

@

NOVO_BTN#

1

ON/OFF# <38>

51_ON# <44>

12

D27

D27 RLZTE1120A LL34

RLZTE1120A LL34

@

1

BTN FUNCTION

MUTE BTN

DOWN

UP

KEY MATRIX

IN

KSO17 KSO17 KSO16

1

OUT

KSI3 KSI2 KSI2

IDEAPAD BOARD 2PIN

ACES_87213-0200

4

G2

3

G1

2

1

JP26

+5VS

R769

1 2

100_0603_5%

Slide Board Conn. 10 pin

JP24

DRIVE_LED#<28>

BT_LED#<41>

WLAN_LED#<31>

3G_LED#<31>

DRIVE_LED# BT_LED# WLAN_LED# 3G_LED#

+5VS

I2C_INT<38>

EC_SMB_DA2<5,16,38> EC_SMB_CK2<5,16,38>

R773470_0402_5% R773470_0402_5%

12

R774470_0402_5% R774470_0402_5%

12

R775470_0402_5% R775470_0402_5%

12

R776470_0402_5% R776470_0402_5%

12

R631 0_0402_5%R631 0_0402_5%

1 2

R586 0_0402_5%

1 2

R585 0_0402_5%

1 2

I2C_INT_R R_SMB_DA2

R_SMB_CK2

JP24

1

2

3

4

5

6

7

8

9

10

11

GND

12

GND

ACES_85201-1005N

Security Classification

2008/03/25 2008/04/

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/25 2008/04/

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

Audio Jack & SW connector

Size Document Number Rev

Custom

Date: Sheet of

KIWB1/B2_LA4601P

42 53Wednesday, March 18, 2009

0.1

A

B

C

D

E

+3VALW TO +3VS+5VALW TO +5VS

+5VALW

U35

8

D

+1.5V

C754

C754 10U_0805_10V4Z

10U_0805_10V4Z

R608

R608 0_0402_5%

0_0402_5%

@

1 2

7

D

6

D

5

D

SI4800BDY-T1-E3_SO8

R598

R598 0_0402_5%

0_0402_5%

1 2

U38

8

D

7

D

6

D

5

D

SI4800BDY-T1-E3_SO8

0.1U_0603_25V7K

1

C742

C742 10U_0805_10V4Z

2

G

2

B+

R593

R593 20K_0402_5%

20K_0402_5%

13

D

S

5VS_GATE

10U_0805_10V4Z

Q49

Q49 2N7002_SOT23

2N7002_SOT23

1 1

SUSP

+1.5V to +1.5VS

2 2

SUSP

2N7002_SOT23

1

2

+5VALW

R606

R606 47K_0402_5%

47K_0402_5%

1 2

Q57

13

D

2

G

S

S S S

G

@

S S S

G

1.5VS_GATE

1

C757

@

2

+5VS

1 2

1 3 4

2

1

C751

0.1U_0603_25V7K

2

+1.5VS

1 2 3 4

1

C758

0.1U_0603_25V7K

2

C743

C743 10U_0805_10V4Z

10U_0805_10V4Z

1

C755

C755 10U_0805_10V4Z

10U_0805_10V4Z

2

1

C744

C744 1U_0603_10V4Z

1U_0603_10V4Z

2

1

C756

C756 1U_0603_10V4Z

1U_0603_10V4Z

2

12

R590

R590 470_0603_5%

470_0603_5%

13

D

S

12

13

D

S

SUSP

2

G

Q46

Q46 2N7002_SOT23

2N7002_SOT23

R601

R601 470_0603_5%

470_0603_5%

SUSP

2

G

Q52

Q52 2N7002_SOT23

2N7002_SOT23

SUSP

2

G

12

R602

R602 470_0603_5%

470_0603_5%

@

13

D

S

B+

Q53

Q53 2N7002_SOT23

2N7002_SOT23

@

1

C745

C745 10U_0805_10V4Z

10U_0805_10V4Z

2

12

R594

R594 47K_0402_5%

47K_0402_5%

13

D

Q50

Q50 2N7002_SOT23

2N7002_SOT23

S

2

G

+3VALW

8 7 6 5

+3VS

U36

1

S

D

2

D

G

D

SI4800BDY-T1-E3_SO8

R599

R599 0_0402_5%

0_0402_5%

@

1 2

+1.5V +VCCP+1.8V +0.75V

12

13

D

S

4

1

C752

0.1U_0603_25V7K

2

R603

R603 470_0603_5%

470_0603_5%

SYSON# SUSP SYSON#SYSON#

2

G

Q54

Q54 2N7002_SOT23

2N7002_SOT23

C746

C746 10U_0805_10V4Z

10U_0805_10V4Z

2

1

S

D

3

S

1

C747

C747 1U_0603_10V4Z

1U_0603_10V4Z

2

12

R604

R604 470_0603_5%

470_0603_5%

13

D

G

Q55

S

2N7002_SOT23

2

12

R591

R591 470_0603_5%

470_0603_5%

13

D

S

SUSP

2

G

Q47

Q47 2N7002_SOT23

2N7002_SOT23

12

13

D

S

R605

R605 470_0603_5%

470_0603_5%

2

G

Q56

Q56 2N7002_SOT23

2N7002_SOT23

+1.8V to +1.8VS

+1.8V +1.8VS

J4

112

JUMP_43X118

2

12

R592

R592 470_0603_5%

470_0603_5%

13

D

S

SUSP

2

G

Q48

Q48 2N7002_SOT23

2N7002_SOT23

3 3

R609

R609 10K_0402_5%

10K_0402_5%

Q58

2

IN

+5VALW

12

1

3

@

R610

R610 100K_0402_5%

100K_0402_5%

OUT

GND

+5VALW

12

R611

R611 100K_0402_5%

SYSON#<48,49>

SYSON<31,38,48,49>

B

SYSON#

DTC124EKAT146_SC59-3

SYSON

100K_0402_5%

Q59

1

OUT

2

IN

GND

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DC Interface

KIWB1/B2_LA4601P

43 53Monday, April 27, 2009

E

0.1

RTCVREF

12

SUSP<31,48,49>

SUSP#<31,38,48,49>

4 4

SUSP

DTC124EKAT146_SC59-3

A

B

C

D

1 1

2 2

DC030006J00

JDCIN

JDCIN 4602-Q04C-09R 4P P2.5@

4602-Q04C-09R 4P P2.5@

1

2

3

4

APDIN APDIN1

21

12

PC112

0.1U_0603_50V7K

PF101

7A_24VDC_429007.W RML

12

SMB3025500YA_2P

12

PC101

1000P_0402_50V7K

PL101

1 2

100P_0402_50V8J

PC102

12

VIN

12

PR103

12

100P_0402_50V8J

PC113

PC103

PC104

1000P_0402_50V7K

0.1U_0603_50V7K

1000P_0402_50V7K

VINDE-1

12

PC106

1000P_0603_50V7K

PR103

82.5K_0402_1%

12

PR107

PR106

PR106 215K_0402_1%

215K_0402_1%

1 2

24.9K_0402_1%

VINDE-3

12

PC107

0.1U_0402_16V7K

VINDE-2

PR109

PR109 10K_0402_5%

10K_0402_5%

3

+

2

-

PR102

PR102 1M_0402_1%

1M_0402_1%

1 2

VS

8

P

O

G

PU102A

PU102A LM393DG_SO8

LM393DG_SO8

4

12

1

RTCVREF

3.3V

VIN

PR105

PR105 10K_0402_1%

10K_0402_1%

1 2

PACIN

12

PD102

RLZ4.3B_LL34

ACIN <29,38,46>

PACIN

Vin Detector

High 18.135 17.566 17.011 Low 14.866 14.355 14.063

PR110

68_1206_5%

13

VIN

PD103

LL4148_LL34-2

1 2

51ON-1

12

PC109

0.1U_0603_25V7K

12

PR111

PR111 68_1206_5%

68_1206_5%

VS

SP093MX0000

PD101

LL4148_LL34-2

PR101

200_0603_5%

1 2

100K_0402_1%

PR113

22K_0402_1%

1 2

12

PR112

PQ101

TP0610K-T1-E3_SOT23-3

51ON-2

12

PC108

1 2

0.22U_0603_25V7K

51ON-3

2

BATT+

3 3

CHGRTCP

51_ON#<42>

RTC Battery

JRTC

- +

MAXEL_ML1220T10@

12

+RTCBATT

PD104

1 2

RB751V-40TE17_SOD323-2

+CHGRTC

PR115

560_0603_5%

1 2

PR116

560_0603_5%

1 2

RTCVREF

3.3V

12

PC110

PC110 10U_0603_6.3V6M

10U_0603_6.3V6M

PU101

CHGRTCINRTCVREF-1

12

PR114

PR114 200_0603_5%

200_0603_5%

12

PC111

PC111 1U_0805_25V4Z

1U_0805_25V4Z

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/05/21 2009/05/21

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DCIN & DETECTOR

44 53Wednesday, March 18, 2009

D

44 53Wednesday, March 18, 2009

0.1

A

PQ301

PQ301 FDS6675BZ_SO8

FDS6675BZ_SO8

1 2

100K_0402_5%

8 7

5

PR306

PR306 340K_0402_1%

340K_0402_1%

1 2

PR310

54.9K_0402_1%

1 2

PR316

1 2

4

VIN

PR301

3.3_1210_5%

1 1

2.2U_0805_25V6K

2 2

CP Point Setting

90W adapter Vacset=3.3*(127K/(75K+127K))=2.075V CP Point=(Vacset/Vvdac)*(0.1/PR302)=4.19A

65W adapter Vacset=3.3*(115K/(150K+115K))=1.432V CP Point=(Vacset/Vvdac)*(0.1/PR302)=2.89A

PR305

3.3_1210_5%

PC311

BK-1 BK-2

1 2

1 2 12

1 2

PC301

0.01U_0402_25V7K

PR309

340K_0402_1%

PR314

54.9K_0402_1%

Input OVP : 22.3V ACIN detect : 17.26V

PQ302

PQ302 FDS6675BZ_SO8

FDS6675BZ_SO8

1

2

36

3 6

4

12

PC306

1 2

0.01U_0402_25V7K

100K_0402_5%

PR304

PR311

75K_0402_1%

24751_VREF ACSET

1 2

PC315

0.01U_0402_25V7K@

CP setting

24751_VREF

PQ306

AO3413_SOT23-3

2

Fsw : 300KHz

1 3

1 2

PC324

0.1U_0603_25V7K

24751_VREF

PR320

100K_0402_5%

3 3

ACOFF 24751_OCP-1

1 2

PC326

0.1U_0402_16V7K

0.1U_0402_16V7K PR323

PR323

340K_0402_1%

24751_VREF

12

PR318

PR318 200K_0402_5%

2

G

200K_0402_5%

24751_OCP-2

13

D

PQ308

PQ308 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

12

24751_OCP-3

2

G

ACSET

13

D

PQ307

PQ307 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

VMB2

VS

12

1

OVP-3

0

8

3

P

+

2

-

G

PU302A

4

LM358DR_SO8

PR330

PR330 10K_0402_5%

10K_0402_5%

12

BATT_OVP<38>

A/D

4 4

A

12

PR327

OVP-1

340K_0402_1%

12

PC329

PR329

0.01U_0402_25V7K

0.01U_0402_25V7K 499K_0402_1%

499K_0402_1%

OVP-2

12

PR331

105K_0402_1%

CHGVADJ<38>

12

PC330

0.01U_0402_25V7K

B

24751_PVCC

PR302

8

0.015_1206_1%

7

B+_IN CHG_B+

PC308

12

0.1U_0603_25V7K

12

PC322

1

5

2

12

PR313

127K_0402_1%

+EC_AVCC

1U_0603_10V6K

210K_0402_1%

1 2

0.1U_0402_16V7K

PR326

PC307

1 2

0.47U_0603_16V7K

24751_OVPSET

PR337

PR337 0_0402_5%@

0_0402_5%@

1 2

PR336

PR336 0_0402_5%

0_0402_5%

24751_ACGOOD#

/BATDRV

REGN

4 3

CHGEN#

12

PC309

24751_ACN

@

24751_ACP

24751_ACDRV#

ACDET

24751_ACOP

PC317

12

VADJ

12

PR324

PR324 0_0402_5%@

0_0402_5%@

12

PR328

PU301

1

CHGEN

0.1U_0603_25V7K

2

ACN

3

ACP

4

ACDRV

5

ACDET

6

ACSET

7

ACOP

8

OVPSET

9

AGND

10

VREF

11

VDAC

12

VADJ

13

ACGOOD

14

BATDRV

BQ24751ARHDR_QFN28_5X5

VADJ

12

PC328

499K_0402_1%

1000P_0402_50V7K

"CHGVADJ" connect to EC DA pin

28

PVCC

27

BTST

26

HIDRV

25

PH

24

REGN

23

LODRV

22

PGND

21

LEARN

20

CELLS

19

SRP

18

SRN

17

BAT

29

TP

16

SRSET

15

IADAPT

100P_0402_50V8J

CHGVADJ Pre Cell

3.3V 4.35V

0V 4V

24751_BTST-1

24751_HIDRV

24751_PH

REGN

12

PC316

PC316 1U_0603_10V6K

1U_0603_10V6K

24751_LODRV

ACOFF

CELLS

24751_SRP 24751_SRN

12

SRSET

IADAPT

1 2

PR321

10_0603_5%

B+

12

PC332

PC332 1000P_0402_50V7K

1000P_0402_50V7K

1 2

PR307

2.2_0402_5%

1 2

24751_BTST

12

PD301

LL4148_LL34-2

PC323

0.1U_0603_25V7K

12

PC327

PJ301

2

112

JUMP_43X118@

PC310

0.1U_0603_25V7K

1 2

PC312

0.1U_0603_25V7K

ACOFF <38>

12

PR334

PR334 0_0402_5%

0_0402_5%

ICHG setting

12

PR322

PR322 180K_0402_1%

180K_0402_1%

ADP_I <38>

LI-3S :13.5V----BATT-OVP=1.5V BATT-OVP=0.1112*BATT+

8

5

P

+

7

0

OVP-4

6

-

G

PU302B

4

LM358DR_SO8

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

C

578

3 6

578

3 6

24751_VREF

PR315

49.9K_0402_1%@

49.9K_0402_1%@ PQ310

PQ310

1 2

SSM3K7002FU_SC70-3@

13

D

BAT_SEL

2

G

S

54.9K_0402_1%

12

@

IREF Current

2.842V 3.3A

Deciphered Date

C

1 2

PQ303

PQ303 AO4466_SO8

AO4466_SO8

241

10U_LF919AS-100M-P3_4.5A_20%

PQ305

PQ305 AO4466_SO8

AO4466_SO8

241

PR332

PR332 0_0402_5%@

0_0402_5%@

12

PR333

PR333 0_0402_5%@

0_0402_5%@

PR319

12

PC325

0.01U_0402_25V7K

1 2

PC303

4.7U_1206_25V6K

PL202

1 2

12

PR312

4.7_1206_5%

24751_SNB

12

PC318

820P_0603_50V7K

2009/05/212008/05/21

1 2

PC304

PC305

4.7U_1206_25V6K

24751_SW-1

12

BATT_SEL_HW <45>

BATT_SEL_EC <38>

IREF <38>

D

12

PR303

PR303 100K_0402_5%

PC302

0.01U_0402_25V7K

/BATDRV

PR308

0.02_1206_1%

1 2

PC331

10U_1206_25V6M

PC319

0.1U_0402_16V7K

1 2

12

PC320

0.1U_0603_25V7K

24751_ACGOOD#

FSTCHG<38>

Title

Size Document Number Rev

Date: Sheet of

100K_0402_5%

1 2

4 3

RTCVREF

12

PR317

100K_0402_5%

Compal Electronics, Inc.

CHARGER

12

PC321

0.1U_0603_25V7K

@

24751_VREF

2

G

24751_VREF

2

G

D

PR335

@

36

578

12

100K_0402_5%

13

D

S

1 2

13

D

S

241

PC313

10U_1206_25V6M

PQ311

PQ311 SSM3K7002FU_SC70-3@

SSM3K7002FU_SC70-3@

PR325

PR325 100K_0402_5%

100K_0402_5%

CHGEN#

PQ309

PQ309 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

PQ304

PQ304 FDS6675BZ_SO8

FDS6675BZ_SO8

BATT+

12

PC314

10U_1206_25V6M

46 53Wednesday, March 18, 2009

ACIN <29,38,44>

0.1

5

4

3

2

1

B+

D D

ISL6237_B+

VL

3/5V_VIN

3/5V_VCC

ISL6237_B+

PC406

2200P_0402_50V7K

12

+5VALWP

+3VALWP

UG3

BST3A-1

3V_SNB

C C

BST3A

SW3

LG3

FB3

VL

2VREF_ISL6237

VS

EN_LDO-1

EN_LDO

3/5V_EN1

3/5V_EN2

HG5 BST5A

SW5

LG5

FB5

5V_SKIP

ILM1

ILIM2

BST5A-1

5V_SNB

VL

POK <29>

B B

MAINPWON <45>

VL

3/5V_NC

3/5V_TON

2VREF_ISL6237

+3VALWP +3VALW

+5VALWP +5VALW

2VREF_ISL6237

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/05/21 2009/05/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

3VALW/5VALW

Size Document Number Rev

Wednesday, March 18, 2009

Date: Sheet of

2

Date: Sheet of

47 53

1

0.1Custom

5

D D

SYSON<31,38,43,49>

+5VALW

C C

SUSP#<31,38,43,49>

+5VS

B B

+1.5V

1

PJ502

1

JUMP_43X79@

2

12

PC519

4.7U_0805_6.3V6K

A A

SUSP<31,43,49>

SYSON#<43,49>

1 2

0.1U_0402_16V7K@

5

PR534

0_0402_5%

PR516

0_0402_5%@

PC522

0.75V_EN

12

13

D

2

G

S

1K_0402_1%

PQ505

PQ505 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

PR515

PR517

PR518

0_0402_5%

1 2

PR521

422_0603_1%

1 2

PC529

1U_0603_10V6K

PR526

100K_0402_1%

1 2

PR529

422_0603_1%

1 2

PC539

1U_0603_10V6K

0.75V_IN

12

0.75V_REF

12

PC521

0.1U_0402_16V7K

12

PC526

0.1U_0402_16V7K

@

12

PC536

0.22U_0402_6.3V6K

12

4

PC530

47P_0402_50V8J@

1 2

PR523

31.6K_0402_1%

1 2

12

PR524

30.1K_0402_1%

PC540

47P_0402_50V8J

@

1 2

PR531

13.7K_0402_1%

1 2

12

PR532

31.6K_0402_1%

PU502

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TRL_SO8

+0.75VP

12

PC523

PC523 10U_0603_6.3V6M

10U_0603_6.3V6M

4

1 2

PR533

PR533 100K_0402_1%

100K_0402_1%

6 5

NC

7

NC

8

NC

9

TP

1.5V_TON

1.5V_EN

1.5V_V5FILT

1.5V_FB

12

@

VCCP_TON

VCCP_EN

VCCP_V5FILT

VCCP_FB

3

578

PR501

240K_0402_1%

1 2

BST_1.5V BST_1.5V-1

1 2

PR519

2.2_0603_5%

1

2

TON

EN_PSV

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

PC543

0.1U_0402_16V7K

2 3 4 5 6

12

GND7PGND

1.5V_PGOOD <8>

240K_0402_1%

1 2

1

TON

EN_PSV

VOUT V5FILT VFB PGOOD

GND7PGND

+3VALW

PC520

PC520 1U_0402_6.3V6K

1U_0402_6.3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2.2_0603_5%

14TP15

TRIP

DRVL

TRIP

DRVL

LL

3

UG_1.5V

13

SW_1.5V

12

1.5V_TRIP

11

PR522

23.7K_0402_1%

10

LG_1.5V

9

PR527

2.2_0603_5%

1 2

UG_VCCP

13

SW_VCCP

12

VCCP_TRIP

11 10

LG_VCCP

9

VBST

DRVH

V5DRV

8

PU501

PU501 TPS51117RGYR_QFN14_3.5x3.5

TPS51117RGYR_QFN14_3.5x3.5

PR525

BST_VCCP BST_VCCP-1

14TP15

VBST

DRVH

V5DRV

8

PU503

PU503 TPS51117RGYR_QFN14_3.5x3.5

TPS51117RGYR_QFN14_3.5x3.5

PC525

0.1U_0603_25V7K

1 2

0.1U_0603_25V7K

1 2

PR530

23.7K_0402_1%

1 2

+5VALW

12

PC535

1 2

+5VS

12

Compal Secret Data

3 6

578

PC531

4.7U_0805_6.3V6K

PC541

4.7U_0805_6.3V6K

3 6

578

3 6

578

3 6

+VCCPP +VCCP

Deciphered Date

2

1.5V_IN

PQ501

PQ501 AO4466_SO8

AO4466_SO8

241

2.2UH_PCMC063T-2R2MN_8A_20%

12

PR520

4.7_1206_5%

1.5V_SNB

12

AO4712_SO8

PQ506

PC532

241

470P_0603_50V7K

VCCP_IN

PQ507

PQ507 AO4466_SO8

AO4466_SO8

241

1.8UH_SIL104R-1R8PF_9.5A_30%

12

PR528

4.7_1206_5%

VCCP_SNB

AO4712_SO8

PQ508

12

PC542

241

680P_0603_50V7K

PJ503

2

JUMP_43X118@

2009/05/212008/05/21

2

12

PC533

680P_0402_50V7K

PL501

1 2

PL502

1 2

112

PJ501

2

112

JUMP_43X79@

12

PC501

10U_1206_25V6M

1

+

PC527

2

220U_6.3VM_R15

PJ506

2

112

JUMP_43X79

@

12

PC534

10U_1206_25V6M

1

+

PC537

2

220U_6.3VM_R15

12

PC544

PC545

330P_0402_50V7K

+1.5VP

12

PC528

10U_0603_6.3V6M

12

PC547

PC546

220P_0402_50V7K

+VCCPP

12

PC538

10U_0603_6.3V6M

+1.5VP +1.5V

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

1.5V/VCCP/0.75V

1

B+

470P_0402_50V7K

B+

12

PC548

680P_0402_50V7K

820P_0603_50V7K

PJ504

2

112

JUMP_43X118@

PJ505

2

112

JUMP_43X79@

1

+0.75V+0.75VP

0.1

48 53Wednesday, March 18, 2009

0.1

5

4

3

2

1

PR617

100K_0402_1%

1 2

SUSP#

SYSON

D D

+1.8V_VCC

C C

B B

GPU_VID1<16>

A A

NB10M-GS1

(Remove PR620)

NB10P-GE1

+VGA_PVCC

+5VS

SUSP#<31,38,43,48>

GVID1-2

GVID1-1

GPU_VID0<16>

10K_0402_5%

GPIO6 GPIO5

GPU_VID1 GPU_VID0 VGA_CORE

GPIO6 GPIO5

GPU_VID1 GPU_VID0 VGA_CORE

12

PR621

0 1

5

0 0

0

GVID0-1

0.92V

0.9V0

1.1V

+VGA_VCC

GVID0-2

1.8V_V5FILT

1.8V_FB

SUSP<31,43,48>

1.8V_TON

1.8V_EN

VGA_FCCM

VGA_EN

2 3 4 5 6

PU601

TON VOUT V5FILT VFB PGOOD

COMP_VGA

BST_1.8V BST_1.8V-1

1

14TP15

VBST

EN_PSV

V5DRV

GND7PGND

TPS51117RGYR_QFN14_3.5x3.5

8

FSET_VGA

VGA_FB

COMP_VGA-1

1.1V_EN

4

DRVH

TRIP

DRVL

LL

13 12 11 10 9

12

PR634

2.37K_0402_1%

UG_1.8V SW_1.8V

1.8V_TRIP

LG_1.8V

12

PC610

4.7U_0805_6.3V6K

UG_VGA BST_VGA BST_VGA-1

1 2

PD601

PD601 1SS355_SOD323-2@

1SS355_SOD323-2@

+VGA_PVCC

ISEN_VGA

+1.8VS

1.1V_REF

+1.8V_VCC

+5VS

SW_VGA

1.1V_IN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1.8V_IN

1.8V_SNB

VGA_IN

0.88UH_PCMB103E-R88MS_20A_20%

1 2

786

5

4

LG_VGA

SUSP<31,43,48>

+1.1VSP +1.8VP

3

VGA_SNB

PQ605

123

SI4634DY-T1-E3_SO8

+5VS

0.1U_0402_16V7K

Compal Secret Data

Deciphered Date

PL602

PC631

B+

12

PC602

330P_0402_50V7K

+1.5VRAMP

12

PC606

10U_0603_6.3V6M

B+

12

PR615

0_0402_5%@PR615

0_0402_5%

@

+3VS

LDO_1.8V_EN

12

+VGASENSE <18>

2009/05/212008/05/21

2

+VGA_COREP +VGA_CORE

+VGA_COREP

+5VALW +1.8V_VCC

+5VS

LDO_1.8V_IN

12

PR623

1K_0402_1%

LDO_1.8V_REF

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

VGA_CORE/1.8V/1.1V

+1.1VS+1.1VSP

+1.5VRAM+1.5VRAMP

+1.8V+1.8VP

+1.8V_VCC

0.1

49 53Wednesday, March 18, 2009

1

0.1

5

4

3

2

1

VR_ON

+3VS

12

PR830

1

DROOP

2

VREF

3

GND

4

CSP1

5

CSN1

6

CSN2

7

CSP2

8

GNDSNS

9

VSNS

10

THERM

<6>

12

PR831

10K_0402_1%

1.91K_0402_1%

@

+3VS +5VS

12

PR865

0_0402_5%

PR865

0_0402_5%

PR834

0_0402_5%@PR834

0_0402_5%

@

12

CPU_VREF

12

PR833 124K_0402_1%PR833 124K_0402_1%

PR836 0_0402_5%PR836 0_0402_5%

PR835 0_0402_5%PR835 0_0402_5%

CPU_VR_ON

CPU_TONSEL

CPU_V5FILT

40

41

GND

V5FILT

VR_TT#11DPRSTP#12PSI#13VID614VID515VID416VID317VID218VID119VID0

CPU_TRIPSEL

CPU_ISLEW

CPU_OSRSEL

35

36

37

38

39

ISLEW

TONSEL

OSRSEL

TRIPSEL

PWRMON

PU801

TPS51620RHAR_QFN40_6X6

VID5

VID6

VID4

PSI#

CPU_DPRSTP#

12

1 2

PR852 0_0402_5%PR852 0_0402_5%

PR855 0_0402_5%PR855 0_0402_5%

PR853 0_0402_5%PR853 0_0402_5%

PR854 0_0402_5%PR854 0_0402_5%

H_PSI#

<6,8,28>

CPU_VID5

CPU_VID6

H_DPRSTP#

CPU_VID4

34

VID3

1 2

PR856 0_0402_5%PR856 0_0402_5%

<6>

PR837 0_0402_5%PR837 0_0402_5%

VR_ON

PR857 0_0402_5%PR857 0_0402_5%

CPU_VID3

D D

VGATE<8,29>

1 2

1 2 1 2

1 2 1 2 1 2 1 2

CPU_GNDSNS

CPU_VSNS

12

PR844

0_0402_5%

PR844

0_0402_5%

VCCSENSE

1 2

PR832

PR832 0_0402_5%@

0_0402_5%@

PC824

1U_0402_6.3V6K

CPU_DROOP CPU_VREF

CPU_CSP1-2

CPU_CSP1-2 CPU_CSN1-1

CPU_CSN1-1 CPU_CSN2-1

CPU_CSN2-1 CPU_CSP2-2

CPU_CSP2-2

CPU_THERM

12

PR845

0_0402_5%

PR845

0_0402_5%

PR849

PR849 20K_0402_1%

20K_0402_1%

12

PR847

PR847 100_0402_1%

100_0402_1%

<6>

+CPU_CORE

CLK_ENABLE#<29>

C C

CPU_VREF

PR839

4.02K_0402_1%

CPU_CSP1

PR861 470_0402_1%PR861 470_0402_1%

CPU_CSN1

PR862 470_0402_1%PR862 470_0402_1%

CPU_CSN2

PR863 470_0402_1%PR863 470_0402_1%

CPU_CSP2

PR864 470_0402_1%PR864 470_0402_1%

B B

12

PC836

100P_0402_50V8J

12 12

PC837

100P_0402_50V8J

12

1 2

PR843

100_0402_1%

PC825 68P_0402_50V8JPC825 68P_0402_50V8J PC826 0.22U_0603_10V7KPC826 0.22U_0603_10V7K

PC828 33P_0402_50V8JPC828 33P_0402_50V8J PC830 33P_0402_50V8JPC830 33P_0402_50V8J PC832 33P_0402_50V8JPC832 33P_0402_50V8J PC833 33P_0402_50V8JPC833 33P_0402_50V8J

12

VSSSENSE

<38>

12

PR866

1.91K_0402_1%

@

<8,29>

DPRSLPVR

PQ801

5

4

SI4634DY-T1-E3_SO8

3 5

241 786

123

3 5

241

786

5

PQ801 SI7686DP-T1-E3_SO8

SI7686DP-T1-E3_SO8

12

PR819

4.7_1206_5%

CPU1_SNB

12

PQ803

PC815

SI4634DY-T1-E3_SO8

680P_0402_50V7K

12

PQ804

PQ804 SI7686DP-T1-E3_SO8

SI7686DP-T1-E3_SO8

PQ806

SI4634DY-T1-E3_SO8

123

1 2

PR838 0_0402_5%PR838 0_0402_5%

786

+5VS

5

4

PQ802

123

SI4634DY-T1-E3_SO8

786

5

PQ805

123

CPU_DPRSLPVR

CPU_CLK_EN#

31

32

33

VBST

V5IN

PGND

PR860 0_0402_5%PR860 0_0402_5%

30 29 28

LL1

27 26 25 24 23

LL2

22 21

<6>

UGATE_CPU1 BOOT_CPU1 PHASE_CPU1 LGATE_CPU1

1 2

PC831 10U_0603_6.3V6M

LGATE_CPU2 PHASE_CPU2 BOOT_CPU2 UGATE_CPU2

<6>

PGOOD DRVH1

CLK_EN#

DPRSLPVR

DRVL1

DRVL2

VBST2 DRVH2

20

VID0

VID1

VID2

1 2

PR858 0_0402_5%PR858 0_0402_5%

PR859 0_0402_5%PR859 0_0402_5%

<6>

CPU_VID2

CPU_VID1

CPU_VID0

PR841

1 2

2.2_0603_5%

PR846

1 2

2.2_0603_5%

+5VS

PD801

PD801 1SS355_SOD323-2

1SS355_SOD323-2

1 2

BOOT_CPU1-1

1 2

PC827

0.22U_0603_10V7K

+5VS

BOOT_CPU2-1

1 2

PC834

0.22U_0603_10V7K

1 2

PD802

PD802 1SS355_SOD323-2

1SS355_SOD323-2

12

PC804

PC808

10U_1206_25V6M

PC817

10U_1206_25V6M

12

CPU2_SNB

12

PR829

4.7_1206_5%

PC823

PC823 680P_0402_50V7K

680P_0402_50V7K

PC809

10U_1206_25V6M

+CPU_B+

PC818

10U_1206_25V6M

+CPU_B+

1

12

2200P_0402_50V7K

PR801

17.8K_0402_1%

PR848

17.8K_0402_1%

+

2

PC805

220U_25V_M

PL802

0.36UH_PCMC104T-R36MN1R17_30A_20%

1

CPU_CSP1-1

2

12

PR840

69.8K_0402_1%

1 2

PR842

28.7K_0402_1%

1 2

PC829

0.033U_0402_16V7K

CPU_CSP1

PL803

0.36UH_PCMC104T-R36MN1R17_30A_20%

1

CPU_CSP2-1

2

12

PR850

69.8K_0402_1%

1 2

PR851

28.7K_0402_1%

1 2

PC835

0.033U_0402_16V7K

CPU_CSP2

CPU_SN-1

1 2

CPU_SN-2

1 2

PL801

HCB4532KF-800T90_1812

1 2

4 3

PH801

100K_0603_1%_TH11-4H104FT

CPU_CSN1

4 3

PH803

100K_0603_1%_TH11-4H104FT

CPU_CSN2

12

PC806

PC806 330P_0402_50V7K

330P_0402_50V7K

+CPU_CORE

B+

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/05/21 2009/05/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

+CPU_CORE

Wednesday, March 18, 2009

0.1

50 53

1

0.1

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 2

for PWR

Reason for change PG# Modify List Date PhaseItem

Change PU301 Pin 11 VDAC source form

D D

1

P46Improve charge output current accuracy.

24751_VRFE to +EC_AVCC.

Change PR801, PR848 from 15.4k_0402_1% to 17.8k_0402_1%

Improve CPU_CORE transient response. P50

2

Adjust loadline. P50 Change PR839 from 5.76k_0402_1% to 4.02k_0402_1% 20080804 DVT

3

Reduce VGA_CORE ripple.

4

Change PC829, PC835 from 0.022u to 0.033u.

Add PC633, PC634 10u_0603_6.3V_V6M.

P49

Add PC619 330u_2.5V_R9M

20080725 DVT

20080804 DVTChange PR840, PR850 from 196k_0402_1% to 69.8k_0402_1%

20080804 DVT

Improve VGA_CORE efficiency at heavy load. P49 Add PD601

5

Adjust 0.75V power sequence. Add PR534.

6

C C

Adjust power sequence.

7

P48

Change PR525 from 0 to 27K. PR526 from 0 to 100k. Add 0.1u_0402 at PC630 0.22u_0402 at PC536.

P49

20080813

20080813 DVT

DVT20080804

DVT

Change PQ603 from SI4686 to SI7686DP.

For customer upgrade VGA to N10X. P49

8

Change PQ604, PQ605 from FDMS670 to SI4634DY. Change PL602 from 1u to .88u.

20080813 DVT

Change PC615 from 220u ESR15 to 330u ESR9.

Reserve OSR to reduce overshoot. P50

9

10

B B

11

12

Improve VGA CORE driver ability for upgrade VGA chip from N9X to N10X.

Reduce power board band.

Change 1.8V sequence the same with 1.8VS. Add PR617, PR631, PR637.P49

13

14

15

16

A A

17

Adjust power sequence.

Reduce power board band. Add PC332 1000P_0402_50V7KP46 Reserve VDAC power connect to

24751_VREF and EC_AVCC

Reduce power board band. P44 Add PC112, PC113 0.1U_0603_50V7K 20081022 PVT

Add PR865 20080813 DVT

P49 Change PU602 VGA CORE solution from TPS51117 to ISL6269A

Change PR403, PR405, PR519, PR527, PR603, PR611, PR841, PR846 to 2.2ohm at BOM. Change PR402, PR404, PR520, PR528, PR604, PR612, PR819, PR829 to 4.7ohm at BOM. Change PC414, PC415 to 330p_0402_50V at BOM.

P47

Change PC542, PC608, PC618, PC815, PC823 680P_0603_50V7K at BOM.

P48

Change PC532 to 470P-0603_50V7K. Add PC546 220P_0402_50V7K.

P49

Add PC405, PC544, PC602, PC617, PC806 330P_0402_50V7K.

P50

Add PC545 470P_0402_50V7K. Add PC533, PC547 680P_0402_50V7K.

20080823 DVT

20080826 DVT

20080902

Change PR617, PR632 to 100k_0402_1%.

P49

Add PC604, PC631 to 0.1u_0402.

20080905

20081013 PVT

P46 PVT20081015Add PR336, PR337 0_0402_5%

DVT

DVTFor solve charger unstable. P46 Add PC331 10u_1206_25V6M

DVT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/09/20 2008/09/20

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PIR (PWR)

<Doc>

0.1

51 53Wednesday, March 18, 2009

1

0.1

5

4

3

2

1

NO DATE PAGE MODIFICATION LIST PURPOSE

-------------------------------------------------------------------------------------------------------------

1 P11 change R166 package from 0805 to 1206 2 3 4 P42 add D29,D30,D33 EMI REQUEST

D D

P29 REMOVE D17

ADD R788P16 (MEM_VREF PULL DOWN)

VOLTAGE DRAP GPIO STATUS REMOVE AC IN CONTROL OF SW

DVT

P365 add R789 FOR MONO P426 CHANGE R781 FROM 300 TO 560

MEET LED SPEC P197 ADD 220uF FOR VGA COREADD C843 P258 G5243 ISSUEchange LCD power circuit P429 modify JP26 pin define P1810 remove R135

MEET IDEAPAD SPEC

CHECK NV SPEC P1611 ADD R793,R795,R796 FOR N10x 40nm P1912 ADD R794 FOR N10x 40nm P713 STUFF C832,C834,C833,C647,C818,C817,C803 POWER REQUEST P1914 ADD C844,C845,C846,C847,C848,C849,C850,C851,C852 NV REQUEST P3515 CHANGE U42 POWER FROM 1.8V TO 1.8VS UPDATE

C C

P4316 ADD J4 1.8V CONNECT TO 1.8VS P1417 CHANGE FROM 0.75V TO 0.75VS DDR3 POWER P1518 CHANGE FROM 0.75V TO 0.75VS DDR3 POWER P4319 CHANGE FROM 0.75V TO 0.75VS DDR3 POWER P3720 HP_OUTR TO SWAP HP_OUTL HP_OUTR TO SWAP HP_OUTL P3621 CHANGE C646,C646 FROM 0.1uF TO 0.01uF AUDIO TEAM TO REQUEST THE HPF OF 600Hz P3722 CHANGE C760 FROM 1nF TO 10nF AUDIO TEAM TO REQUEST THE LPF OF 600Hz

CHANGE R619 FROM 47Kohm TO 68KohmP3723 AUDIO TEAM TO REQUEST THE LPF OF 600Hz DELETE 5VS_GATE , R596,R597,R607P4324 DELETE 5VS_GATE SWAP LED7P4025 SWAP LED7 CHANGE LED POWER FROM 3V TO 5VP40,P4226 USE WHITE LED REMOVE U42P3527 REMOVE ESATA REDRIVER

B B

ADD AO FUNCTIONP31,P3828 ADD AO FUNCTION

CHANGE R560,R561 FROM 4.7K TO 2.2KP3829 I2C BUS ADD R810,R811P3830 I2C BUS POWER CHANGE U37,U38 POWER FROM B+ TO +5VALWP4331 CHANGE MOSFET VDS TO MODIFY ALL LED SYMBOLP4032 MODIFY COLOR TO WHITE MODIFY R627,R624,R577 FROM 300 TO 453OHMP4033 MODIFY COLOR TO WHITE ADD C853,C854,C855,C856P2334 FOR 3G ISSUE (SED)

ADD C14~C31P7,P14,P1535 FOR 3G ISSUE (SED) 36 C32,C33,C34,C35P32 37

DEL R616,R617,R765,R766,R764,R767,P37 EMI

EMI

R534,R536,R539,R540

ADD L43,L44,L45,L46,L47,L48,L49,L50,L51,L52P37 EMI38

A A

REMOVE C843P19 CHANGE TO POWER SIDE39

ADD TV POWER SW FUNCTIONP3140 ADD TV POWER SW FUNCTION

CHANGE R1 FROM 49.9 TO 56 OHM P541 FOLLOW INTEL CHECK LIST 2.0

FOLLOW INTEL CHECK LIST 2.0CHANGE R3 FROM 56 TO 68 OHM P542 FOLLOW INTEL CHECK LIST 2.0CHANGE R45 R53 FROM 10K TO 1K OHM P843 CHANGE TO GPO_AUDREMOVE "DDR3_SM_PWROK"P844

5

4

3

2

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

HW PIR

KIWB1/B2_LA4602P 1.0

52 53Wednesday, March 18, 2009

1

5

NO DATE PAGE MODIFICATION LIST PURPOSE

NO DATE PAGE MODIFICATION LIST PURPOSENO DATE PAGE MODIFICATION LIST PURPOSE

------------------------------------------------------------------------------------------------------------- DVT

------------------------------------------------------------------------------------------------------------- DVT------------------------------------------------------------------------------------------------------------- DVT 45 COST DOWNCHANGE R79 R83 SIZE FROM 0805 TO 0603 P11

4

3

2

1

ADD R813 ,R735,R793,R818,R816,R819,R817P1646 FOR N10x 40nm DELETE L10,C316,C315,C312P1947 FOR N10x 40nm

D D

DELETE L10,C316,C315,C312P1948 FOR N10x 40nm CHANGE C781,C782,C800,C801 FROM 0.01UF TO 0.1 UFP21,P2249 FOR N10x 40nm ADD R824P3150 FOR 3G CARD ADD GPO_AUDP3651 FOR MUTE ISSUE CHANGE R562,R563 FROM 4.7K TO 2.2K OHMP3852 FOR SM BUS ISSUE (PULL UP) ADD C757P4353 FOR POWER SEQUENCE

NO DATE PAGE MODIFICATION LIST PURPOSE

NO DATE PAGE MODIFICATION LIST PURPOSENO DATE PAGE MODIFICATION LIST PURPOSE

------------------------------------------------------------------------------------------------------------- PVT

------------------------------------------------------------------------------------------------------------- PVT------------------------------------------------------------------------------------------------------------- PVT 1 CHANGE R606,R595 FROM 150K TO 47KP43

REMOVE C757P43

2

3 4 5

C C

ADD POLY FUSE(F1)P26 ADD R825,R826,R827,R828,C857,C858,C859,C860P24 CHANGE LED SYSBOLP40 UPDATE FOOTPRINT CHANGE R801 SIZE FROM 0603 TO 0805P31 NON-TV SW6

POWER SEQUENCE POWER SEQUENCE CRT PIN ISSUE EMI SOLUTION OF HDMI

CHANGE R3 FROM 68 TO 56 OHMP5 INTEL CHECK LIST 2.07 8 9 P28 CHANGE C494,C496 FROM 15pF TO 10pF 10 11

P32 P38

ADD R829P36

CHANGE C693,C696 FROM 15pF TO 18pF

CHANGE C605 FROM 27pF TO 33pF

REQUEST OF EMI RTC ADJUSTMENT RTC ADJUSTMENT

RTC ADJUSTMENT CHANGE C728,C733 SYMBOLP35,P4112 UPDATE FOOTPRINT ADD R830,R831P3813 ENE ISSUE ADD R832,C861P4014 3G REQUEST ADD C862,C863P4115 MOSFET SW OF OVERSHOOT

NO DATE PAGE MODIFICATION LIST PURPOSE

NO DATE PAGE MODIFICATION LIST PURPOSENO DATE PAGE MODIFICATION LIST PURPOSE

B B

------------------------------------------------------------------------------------------------------------- PRE MP

------------------------------------------------------------------------------------------------------------- PRE MP------------------------------------------------------------------------------------------------------------- PRE MP ADD R834,R835,R836,R837,R838,R839,Q12A,Q12BP16,P181 FOR N10x 40nm

CONNECT AUX PIN FOR HDMI (AP2,AN3)P16,P182 FOR N10x 40nm R587 PULL DOWNP423 FOR POWER ON/ OFF SWAP CHARGE_LED0# AND CHARGE_LED1#P404 LED ISSUE CHANGE C758 FROM 1U TO 18NP375 AUDIO TEAM REQUEST CHANGE R618 FROM 18KOHM TO 8.45KP376 AUDIO TEAM REQUEST CHANGE R832 FROM 0 TO 47 OHMP407 SED 3G TEAM REQUEST CHANGE C861 FROM 12P TO 68PP408 SED 3G TEAM REQUEST CHANGE C645,C646 FROM .01U TO 3300PP369 AUDIO TEAM REQUEST

P36 CHANGE R587 FROM 4.7K TO 10K ohm10 FOR POWER ON/ OFF P42 CHANGE R769 TYPE FROM 0402 TO 060311

A A

NO DATE PAGE MODIFICATION LIST PURPOSE

NO DATE PAGE MODIFICATION LIST PURPOSENO DATE PAGE MODIFICATION LIST PURPOSE

------------------------------------------------------------------------------------------------------------- Upgrade

------------------------------------------------------------------------------------------------------------- Upgrade------------------------------------------------------------------------------------------------------------- Upgrade

1 P16~P22 Modify nVIDIA N10x(40nm) and VRAM FOR N10x 40nm

5

4

Title

Size Document Number Rev

B

Date: Sheet of

3

2

Date: Sheet of

Compal Electronics, Inc.

HW PIR

KIWB1/B2_LA4602P 1.0

53 53Wednesday, March 18, 2009

1

COMPAL LA-4602P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual