Compal LA-4601P Schematics

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2 2

Blue Moutain KIWB1/B2

Schematics Document

Mobile Penryn uFCPGA with Intel

3 3

Cantiga_GM/PM+ICH9-M core logic

REV:0.1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/25 2008/04/

C

Compal Secret Data

Deciphered Date

Compal Electr onics,Ltd.

Title

Cover Sheet

Size Document Number Rev

Custom

KIWB1/B2_LA4601P

D

Date: Sheet

E

of

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0.1

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A

Compal confidential

File Name :

VRAM 32*32

1 1

GDDR3*4

page20

PCI-E X16

NVidia NB9M
NVidia NB9P

page16~24

CONN

page26

PS8101T

page26

CRT cable

page28

2 2

LVDS
Connector

page27

PCI Express
Mini card Slot 1

page31

6*PCI-E BUS

PCI Express
Mini card Slot 2

page31

PCI Express
Mini card Slot 3

3 3

page31

BCM5906/BCM5784M

SIM Card

page31

10/100/1G LAN

RJ45 CONN

PCI-EHDMI

New Card

ZZZ1

15.6W_PCB_LA4601P

page31

page33

B

LVDS I/F

None
PCI BUS

3.3V / 33 MHz

page32

C

Mobile Penryn

uFCPGA-478 CPU

page5,6,7

H_A#(3..35)
H_D#(0..63)

FSB
667/800/1066MHz

Intel Cantiga GMCH

PCBGA 1329

page 8,9,10,11,12,13

DMI

C-Line

Intel ICH9-M

mBGA-676

page27,28,29,30

LPC BUS

EC

ENE KB926D

page38

Int.KBD

Touch Pad

page39

BIOS

POWER BD
Power on X1
LED X1 (G)

:POWER
NOVO X1

Clock Gen.

SLG8SP556VTR
ICS9LPRS387AKLFT

DDR3-800(1.5V)
DDR3-1067(1.5V)

Dual Channel

AZALIA

12*USB2.0

4*SATA serial

page39

page40

D

Slide Bar LED X 10 (B)
USER-DEFINED (W)
DOLBY (W)
LED X 3
WIRELESS LED (G)
BLUETOOTH LED (G)
3G LED (G)
HDD LED (G)

page25

POWER ON (G)
BATTERY CHARG(G/A)
WIRELESS SWITCH (G)
ON/OFF

Double check ME

DDR3-SO-DIMM X2

BANK 0, 1, 2, 3

UP TO 8G

SPK amplifier

page36

WOOFER amplifier

Audio Codec

Realtek ALC272

page36

CMOS Camera

BlueTooth CONN

USB CONN X1

New Card X1

M-PCIE CONN X 3

REPEATER

page35

E

RIGHT BD
VOLUME UP X1
VOLUME DOWN X1
MUTE X1
MUTE LED X1(G)

USB_Board
USB CONN X 2
TV CONN X1

page 14,15

2Channel Speaker

page37

1Channel Speaker

HP X 1+

page37

page36

page41

page41

page41

page31

MIC_Ext X1
2Channel MIC_Int

Realtek 5158E
MS/MS

page31

pro/SD/SD
pro/mmc/XD

ESATA HDD AND USB CONN

page37

page37

page36

page35

HDD/ODD,SCL & T/L LED on MB

4 4

A

CAPS and NUM on KBD

B

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BYOR DISCLOSEDTO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/03/24 2008/04/

Compal Secret Data

Deciphered Date

SATA HDD CONN

SATA ODD CONN

D

page35

page35

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

MB Block Diagram

KIWB1/B2_LA4601P

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DDR3 Voltage Rails

+5VS
+3VS

power
plane

1 1

+B

State

S0

S1

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O
O
O
O
O

X

+5VALW

+3VALW

O
O
O
O

X
XX X

+1.5V
+1.8V
+0.75V

O

XX
X

+1.5VS
+1.1VS
+VCCP
+CPU_CORE
+VGA_CORE
+1.8VS

OO
OO

X

X

SMBUS, SPI and I2C Control Table

SOURCE

HDMI BATTEEPROM

LVDS

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

ICH_SMBCLK
ICH_SMBDAT ICH9

LVDS_SCL
LVDS_SDA

GMCH_CRT_CLK
GMCH_CRT_DAT

HDMICLK_NB
HDMIDAT_NB

VGA_DDCCLK
VGA_DDCDATA

VGA_LVDS_SCL
VGA_LVDS_DAT

VGA_HDMI_SCL
VGA_HDMI_DAT

HDCP_SMB_CK1
HDCP_SMB_DA1

FSEL#SPICS#_SB
FRD#SPI_SO_SB
SPI_CLK_SB
FWR#SPI_SI_SB

FSEL#SPICS#
FRD#SPI_SO
SPI_CLK
FWR#SPI_SI

KB926

KB926

Cantiga

Cantiga

Cantiga

VGA

VGA

VGA

VGA

ICH9

KB926

X

X
X

X

X

X

X

V

XX X XXX XXXXX X

XXX XXX XXXXX X

V

X

X
X

V

X

V

X

X

X

XXX

X

HDCP

SERIAL

CRT

XX
X

X
XX X X
XX X X

NEW
CARD

V

XXX
X

VV

X

XX

CLK
GEN

X
X

Mini

CAP
sensor

XX

CARD1

X
X

Mini
CARD2

X
X

VV

X

X

V

X
X
X

THERMAL
SENSOR
(VGA)

V
V

X
X

THERMAL
SENSOR
(CPU)

VV

V

X XXX XXXXX X

V

X

X XXX XXXXX X
X

X
X

X

X
XX

XXX XXXXX X

XX XXXXX

V

XX XXXXX

V
V

XXXXXXX

X
X

X

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/03/24 2008/04/

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

MB Notes List

KIWB1/B2_LA4601P

352Thursday, June 26, 2008

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E

VGA and DDR2 Voltage Rails (NB9M-GS)

power

State +1.8V

1 1

S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery

don't exist

GPIO I/O ACTIVE Function Description
GPIO0
GPIO1
GPIO2
GPIO3

2 2

3 3

GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23

plane

S0
S1
S3

N/A

N/A
IN
OUT
OUT
OUT
OUT
OUT
OUT
I/O
OUT
OUT
I/O
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
N/A N/A Available

Available
Hot plug detect for IFP link C

­H

Panel Back-Light brightness(PWM)

H

Panel Power Enable

H

Panel Back-Light On/Off (PWM)
GPU VID0

­GPU VID1

­GPU VID2 or M EM VID

-

L

Thermal Catastrophic Overtemp

L

FAN control and/or Thermal Alert (PWM)
Memory VREF switch
SLI raster sync

L

AC power detect pin

­Power supply control

-

- Power supply control
Hot plug detect for IFP link E

­Dongle DVI Mode control for Primary Displayport

­Dongle HDMI Mode control for Primary Displayport

­Dongle DVI Mode control for Secondary Displayport

­Dongle HDMI Mode control for Secondary Displayport

­Hot plug detect for IFP link D

­Hot plug detect for IFP link E

­SLI swap ready signal

-

O
O
O
O
O

X

O
O
O
O

X

O

XX
X

XX X

+3VS
+VGA_CORE
+1.1VS

OO
OO

X
X

(+VGA_CORE)

VRAM POWER SQUENCE
GDDR3 FOR 4 UNIT = 5.4A

The ramp time for any rail must be more than 40us

(+3VS)

(1.1VS)

VDD33

PEX_VDD

NVVDD

EDP at Tj = 97C*

Power Supply Rail

NVVDD Variable
FB_DLLAVDD 1.1
FB_PLLAVDD
IFPC_IOVDD
IFPD_IOVDD
IFPE_IOVDD
IFPF_IOVDD
PEX_IOVDD/Q
PEX_PLLVDD
PLLVDD
SP_PLLVDD
VID_PLLVDD

TOTAL

FBVDD/Q
IFPA_IOVDD
IFPB_IOVDD
IFPAB_PLLVDD
IFPCD_PLLVDD
IFPEF_PLLVDD

TOTAL

DACA_VDD
DACB_VDD
DACC_VDD
MIOA_VDDQ
MIOB_VDDQ
VDD33

TO T AL 3.3 0.51A

(V)

1.1

1.1

1.1

1.1

1.1

1.1

1.1

1.1

1.1

1.1

1.1

1.8

1.8

1.8

1.8

1.8

1.8

1.8

3.3

3.3

3.3

3.3

3.3

3.3

GDDR3 DDR2

20.65A 16.96A

3.37A

5.76A 5.47A 3.96A

POWER SQUENCE

PEX_VDD can r a mp up any time

tNVVDD>=0

tNV-FB

tFBVDDQ>=0

NB9P-GS

10mA
10mA
80mA
80mA
160mA
160mA
1550mA
90mA
45mA
45mA
45mA

2.3A

2.02A 3.21A 2.25A
95mA
95mA
70mA
25mA
85mA

3.69A

110mA
120mA
110mA
10mA
10mA
150mA

NB9P-GE2

GDDR3 DDR2

18.47A 16.06A

4 4

A

B

(1.8VS)

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FBVDDQ

C

2008/03/24 2008/04/

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

VGA Notes List

KIWB1/B2_LA4601P

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1

USE->56Ω,NOT USE->50Ω

+VCCP

H_IERR#
H_PROCHOT#

D D

H_A#[3..16]<8>

H_ADSTB#0<8>

H_REQ#0<8>
H_REQ#1<8>
H_REQ#2<8>
H_REQ#3<8>
H_REQ#4<8>

H_A#[17..35]<8>

C C

H_ADSTB#1<8>

H_A20M#<28>

H_FERR#<28>

H_IGNNE#<28>
H_STPCLK#<28>

H_INTR<28>

H_NMI<28>
H_SMI#<28>

B B

RSVD pins on the CPU
should be left as NO
CONNECT

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

AA4
AB2
AA3

D22

K5
M3
N2

N3
P5
P2

P4
P1
R1
M1

K3
H2
K2

Y2
U5
R3

W6

U4
Y5
U1
R4
T5

T3
W2
W5

Y4

U2

V4
W3

V1

A6

A5

C4

D5

C6

B4

A3

M4

N5

T2

V3

B2

D2

D3

F6

J4
L5
L4

J1

L2

J3
L1

CONN@

JCPU1A

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

A20M#
FERR#
IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

Penryn

ADDR GROUP_0

ADDR GROUP_1

THERMAL

ICH

THERMTRIP#

RESERVED

ADS#
BNR#
BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

DBR#

XDP/ITP SIGNALS

PROCHOT#

THERMDA
THERMDC

H CLK

BCLK[0]
BCLK[1]

H_ADS#

H1

H_BNR#

E2

H_BPRI#

G5

H_DEFER#

H5

H_DRDY#

F21

H_DBSY#

E1

H_BR0#

F1

H_IERR#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_TRDY#

G2

H_HIT#

G6

H_HITM#

E4

XDP_BPM#0

AD4

XDP_BPM#1

AD3

XDP_BPM#2

AD1

XDP_BPM#3

AC4

XDP_BPM#4

AC2

XDP_BPM#5

AC1

XDP_TCK

AC5

XDP_TDI

AA6

TDI

XDP_TDO

AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_DBRESET#

C20

H_PROCHOT#

D21

H_THERMDA

A24

H_THERMDC

B25

H_THERMTRIP#

C7

CLK_CPU_BCLK

A22

CLK_CPU_BCLK#

A21

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

H_ADS# <8>
H_BNR# <8>

H_BPRI# <8>
H_DEFER# <8>

H_DRDY# <8>
H_DBSY# <8>

H_BR0# <8>

H_INIT# < 28>

H_LOCK# <8>

H_RESET# <8>
H_RS#0 <8>
H_RS#1 <8>
H_RS#2 <8>
H_TRDY# <8>

H_HIT# <8>
H_HITM# <8>

XDP_DBRESET# <29>

H_THERMTRIP# <8,28>

CLK_CPU_BCLK <23>
CLK_CPU_BCLK# <23>

+3VS

FAN1 Conn

EN_FAN1<38>

FAN +5VS DROOP

A A

R1 49.9_0402_1%

1 2

R3 56_0402_5%

1 2

USE->68Ω,NOT USE-->56Ω

+3VS

1

C1

0.1U_0402_16V4Z

2

H_THERMDA

1 2

C2 2200P_0402_50V7K

1 2

R10 10K_0402_5%

H_THERMDC
THERM#

2nd Source: NS95245

+VCC_FAN1

EN_FAN1

+VCC_FAN1

R11 100_0402_5%

1 2

1

2

FAN_SPEED1<38>

1000P_0402_50V7K

U1

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

Address:100_1100

+5VS

C3 10U_0805_10V4Z

1
2
3
4

C4
2200P_0402_50V7K

R12

10K_0402_5%

+3VS

C7

SMCLK

SMDATA

ALERT#

GND

1 2

U2

VEN
VIN
VO
VSET

G990P11U_SO8

12

+VCC_FAN1

1

2

XDP Reserve

XDP_DBRESET#

XDP_TDI
XDP_TMS
XDP_TDO
XDP_TRST#
XDP_TCK

8
7
6
5

GND
GND
GND
GND

R2 1K_0402_5%@

1 2

R4 54.9_0402_1%

1 2

R5 54.9_0402_1%

1 2

R6 54.9_0402_1%@

1 2

R7 54.9_0402_1%

1 2

R8 54.9_0402_1%

1 2

+3VS

12

R9

@

10K_0402_5%

EC_SMB_CK2
EC_SMB_DA2

8
7
6
5

+5VS

40mil

+VCC_FAN1

EC_SMB_CK2 <16,38,42>

EC_SMB_DA2 <16,38,42>

12

@

D1
1SS355TE-17_SOD323-2

D2 BAS16_SOT23-3@

1 2

C5 1U_0603_10V4Z

1 2

C6 0.1U_0402_16V4Z

1 2

JP1

1

1

2

2

3

3

4

GND

5

GND

E&T_3801-F03N-01RME@

+3VS

+VCCP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/25 2008/04/

3

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

Penryn(1/3)

Size D ocument Number Rev

Custom

KIWB3/B4_LA4551P

2

Date: Sheet

552Monday, June 30, 2008

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0.1

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4

3

2

1

+CPU_CORE +CPU_CORE

CONN@

D D

C C

H_D#[0..15]<8>

H_DSTBN#0<8>
H_DSTBP#0<8>

H_DINV#0<8>

H_D#[16..31]<8>

H_DSTBN#1<8>
H_DSTBP#1<8>

H_DINV#1<8>

R16 1K_0402_5%@

1 2

R18 1K_0402_5%@

1 2

CPU_BSEL1<23>
CPU_BSEL2<23>

T1
T2
T3
T4
T5

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

+CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

TEST7
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

Trace Close CPU < 0.5'

B B

Width=4 mil ,
Spacing: 15mil
(55Ohm)

E22
F24
E26

G22

F23

G25

E25
E23
K24

G24

H22
F26
K22
H23

H26
H25

N22
K25
P26
R23
L23

M24

L22

M23

P25
P23
P22
T24

R24

L25
T25

N25

L26
M26
N24

AD26

C23
D25
C24

AF26

AF1

A26

B22

B23
C21

J24
J23

J26

C3

JCPU1B

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]

Penryn

DATA GRP 0

MISC

DATA GRP 1

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#

DATA GRP 2DATA GRP 3

D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

COMP0
COMP1
COMP2
COMP3

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

R15 27.4_0402_1%

1 2

R17 54.9_0402_1%

1 2

R19 27.4_0402_1%

1 2

R20 54.9_0402_1%

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

1 2

H_D#[32..47] <8>

H_DSTBN#2 <8>
H_DSTBP#2 <8>
H_DINV#2 <8>

H_D#[48..63] <8>

H_DSTBN#3 <8>
H_DSTBP#3 <8>
H_DINV#3 <8>

H_DPRSTP# <8,28,50>
H_DPSLP# <28>
H_DPWR# <8>
H_PWRGOOD <28>CPU_BSEL0<23>
H_CPUSLP# <8>

H_PSI# <50>

TRACE CLOSELY CPU < 0.5'

COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms)
COMP1, COMP3 layout : Width 5mils and Space 25mils (55Ohms)

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

+VCCP

12

R21
1K_0402_1%

Layout note: Z0=55 ohm

0.5" max for GTLREF.

A A

+CPU_GTLREF

12

R24
2K_0402_1%

FSB

BCLK BSEL2 BSEL1 BSEL0
533
667
800

133

166

200

001

100

1067 266 0 0 0

110

Close to CPU pin AD26
within 500mils.

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Deciphered Date

CONN@

JCPU1C

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AC10
AB10
AB12
AB14
AB15
AB17
AB18

A10
A12
A13
A15
A17
A18
A20

B10
B12
B14
B15
B17
B18
B20

C10
C12
C13
C15
C17
C18

D10
D12
D14
D15
D17
D18

E10
E12
E13
E15
E17
E18
E20

F10
F12
F14
F15
F17
F18
F20
AA7
AA9

AB9

A7

VCC[001]

A9

VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]

B7

VCC[010]

B9

VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]

C9

VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]

D9

VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]

E7

VCC[033]

E9

VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]

F7

VCC[042]

F9

VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]

VCCSENSE
VCC[065]
VCC[066]
VCC[067]

VSSSENSE

Penryn

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

R13 0_0402_5%

G21

R14 0_0402_5%

V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

.

For testing purpose only

VCCSENSE

VSSSENSE

12
12

Length match within 25 mils.
The trace width/space/other is
18/7/25.

Layout Note:
Route VCCSENSE and VSSSENSE traces at

27.4 Ohms with 50 mil spacing.
Place PU an d P D wit h i n 1 inch of CPU.
Length matched to within 25 mils.

Title

Size D ocument Number Rev

B

2

Date: Sheet

+VCCP

Near pin B26

20mils

CPU_VID0 <50>
CPU_VID1 <50>
CPU_VID2 <50>
CPU_VID3 <50>
CPU_VID4 <50>
CPU_VID5 <50>
CPU_VID6 <50>

VCCSENSE <50>

VSSSENSE <50>

+CPU_CORE

1 2

1 2

1

C9

C8

2

10U_0805_10V4Z

R22
100_0402_1%

R23
100_0402_1%

1

2

0.01U_0402_16V7K

VCCSENSE

VSSSENSE

Close to CPU pin
within 500mils.

Compal Electronics, Inc.

Penryn (2/3)

KIWB3/B4_LA4551P

652Monday, June 30, 2008

1

+1.5VS

0.1

of

CyberForum.ru

5

CONN@

JCPU1D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

D D

C C

B B

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Penryn

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

220U_D2_4VM

4

+CPU_CORE

10~15 vias for +CPU_CORE

needed to update

1

2

+

C10
1200U_PFAF250E128MNTTE_2.5VM

3 4

10~15 vias for GND

SGA00003F10 1000uF
be placed under the center of CPU

Middle Frequency Decoupling

+VCCP

C48

1

+

2

1

C46

0.1U_0402_16V4Z

2

1

C47

0.1U_0402_16V4Z

2

1

C49

0.1U_0402_16V4Z

2

3

1

C50

0.1U_0402_16V4Z

2

+CPU_CORE

1

@

2

+CPU_CORE

1

@

2

Reserved

1

C51

0.1U_0402_16V4Z

2

1

@

C832
10U_0805_6.3V6M

C818
10U_0805_6.3V6M

2

1

@

2

1

2

2

1

@

C834
10U_0805_6.3V6M

C831
10U_0805_6.3V6M

Per PWR team request ,
reserve 12 MLCC for +CPU_CORE

C52

0.1U_0402_16V4Z

C664
10U_0805_6.3V6M

2

1

@

C817
10U_0805_6.3V6M

2

Place these inside socket cavity
on L8 (North side Secondary)

1

@

2

1

@

2

@

C833
10U_0805_6.3V6M

@

C830
10U_0805_6.3V6M

1

C644
10U_0805_6.3V6M

2

1

C803
10U_0805_6.3V6M

2

1

@

2

1

@

2

C647
10U_0805_6.3V6M

C804
10U_0805_6.3V6M

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Deciphered Date

Title

Size D ocument Number Rev

B

2

Date: Sheet

Compal Electronics, Inc.

Penryn (3/3)

KIW10/11_LA4142P

752Thursday, June 26, 2008

1

of

0.1

CyberForum.ru

5

U3A

H_D#0

H_D#[0..63]<6>

D D

C C

H_RESET#<5>
H_CPUSLP#<6>

layout note:
Route H_SCOMP and H_SCOMP# with trace width

spacing and impedance (55 ohm) same as FSB data traces

B B

Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20

12

R42
1K_0402_1%

12

1

C59

R50

0.1U_0402_16V4Z

2K_0402_1%

2

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWNG
H_RCOMP

H_RESET#
H_CPUSLP#

H_VREF

F2

G8

F8

E6
G2
H6
H2

F6
D4
H3
M9

M11

J1
J2

N12

J6
P2
L2

R2
N9

L6

M5

J3

N2
R1
N5
N6

P13

N8

L7

N10

M3

Y3

AD14

Y6

Y10
Y12
Y14

Y7

W2

AA8

Y9

AA13

AA9
AA11
AD11
AD10
AD13
AE12

AE9

AA2

AD8

AA3

AD3

AD7
AE14

AF3

AC1

AE3

AC3
AE11

AE8

AG2

AD6

C5

E3

C12

E11

A11

B11

12

R51

24.9_0402_1%

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

CANTIGA ES_FCBGA1329GM@

H_RCOMP H_SWNGH_VREF

HOST

+VCCP+VCCP

H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADSTB#_0
H_ADSTB#_1

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HITM#
H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

12

R43
221_0603_1%

12

R52
100_0402_1%

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9

H_ADS#

H_BNR#

H_HIT#

within 100 mils from NB

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

J8
L3
Y13
Y1

L10
M7
AA5
AE6

L9
M8
AA6
AE5

B15
K13
F13
B13
B14

B6
F12
C8

1

C60

0.1U_0402_16V4Z

2

Near B3 pin

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

4

H_A#[3..35] <5>

SMRCOMP_VOH

SMRCOMP_VOL

H_ADS# <5>
H_ADSTB#0 <5>
H_ADSTB#1 <5>
H_BNR# <5>
H_BPRI# <5>
H_BR 0# <5>
H_DEFER# <5>
H_DBSY# <5>
CLK_M CH_BCLK <23>
CLK_M CH_BCLK # <23>
H_DPWR# <6>
H_DRDY# <5>
H_HIT# <5>
H_HITM# <5>
H_LOCK# <5>
H_TRDY# <5>

H_DINV#0 <6>
H_DINV#1 <6>
H_DINV#2 <6>
H_DINV#3 <6>

H_DSTBN#0 <6>
H_DSTBN#1 <6>
H_DSTBN#2 <6>
H_DSTBN#3 <6>

H_DSTBP#0 <6>
H_DSTBP#1 <6>
H_DSTBP#2 <6>
H_DSTBP#3 <6>

H_REQ#0 <5>
H_REQ#1 <5>
H_REQ#2 <5>
H_REQ#3 <5>
H_REQ#4 <5>

H_RS#0 <5>
H_RS#1 <5>
H_RS#2 <5>

Layout Note:
V_DDR_MCH_REF trace
width and spacing is 20/20.

+DDR_MCH_REF

+3VS

12

R34
10K_0402_5%

ICH_POK<29,38>

VGATE<29,50>

PLT_RST#<16,27,31,32>

R37 0_0402_5%
R39 0_0402_5%@
R40 100_0402_5%

1

C61

0.1U_0402_16V4Z

2

1 2
1 2
1 2

1

C53

0.01U_0402_25V7K

2

1

C55

0.01U_0402_25V7K

2

12

R35
10K_0402_5%

PM_EXTTS#0
PM_EXTTS#1

+1.5V

12

R45
10K_0402_5%

12

R53
10K_0402_5%

1

C54

2.2U_0603_6.3V4Z

2

1

C56

2.2U_0603_6.3V4Z

2

MCH_CLKSEL0<23>
MCH_CLKSEL1<23>
MCH_CLKSEL2<23>

H_THERMTRIP#<5,28>

PM_POK_R

PLT_RST#_R

+1.5V

CFG5

PM_BMBUSY#<29>

H_DPRSTP#<6,28,50>
PM_EXTTS#0<1 4, 15>
PM_EXTTS#1

DPRSLPVR<29,50>

12

R28
1K_0402_1%

12

R25

3.01K_0402_1%

12

R26
1K_0402_1%

3

T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19

T20
T26
T21

T22

T23
T24
T25
T27

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

CFG5

T28
T29
T30
T31
T32
T33
T34
T35
T36
T37
T38
T39
T40
T41
T42

PM_BMBUSY#

H_DPRSTP#

PM_EXTTS#0

PM_EXTTS#1

PM_POK_R

PLT_RST#_R

H_THERMTRIP#

DPRSLPVR

CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

AH10
AH12
AH13

AL34
AK34
AN35

AM35

AY21

BG23

BF23

BH18

BF18

AT40
AT11

BG48

BF48
BD48
BC48
BH47
BG47
BE47
BH46

BF46
BG45
BH44
BH43

M36
N36
R33
T33
AH9

K12

T24

B31

B2
M1

T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28

R29

B7
N33
P32

T20
R32

BH6
BH5

BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1

A47

U3B

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

RSVD15
RSVD16
RSVD17

RSVD20

RSVD22
RSVD23
RSVD24
RSVD25

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24

F1

NC_25
NC_26

2

M_CLK_DDR0

AP24

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

SA_CS#_0
SA_CS#_1
SB_CS#_0

DDR CLK/ CONTROL/ COMPENSATIONHDA

CLKDMIGRAPHICS VIDMEMISC

SB_CS#_1
SA_ODT_0

SA_ODT_1

SB_ODT_O

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK
HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

RSVD CFG PM NC

CANTIGA ES_FCBGA1329 GM@

M_CLK_DDR1

AT21

M_CLK_DDR2

AV24

M_CLK_DDR3

AU20

M_CLK_DDR#0

AR24

M_CLK_DDR#1

AR21

M_CLK_DDR#2

AU24

M_CLK_DDR#3

AV20

DDR_CKE0_DIMMA

BC28

DDR_CKE1_DIMMA

AY28

DDR_CKE2_DIMMB

AY36

DDR_CKE3_DIMMB

BB36

DDR_CS0_DIMMA#

BA17

DDR_CS1_DIMMA#

AY16

DDR_CS2_DIMMB#

AV16

DDR_CS3_DIMMB#

AR13

M_ODT0

BD17

M_ODT1

AY17

M_ODT2

BF15

M_ODT3

AY13

SMRCOMP

BG22

SMRCOMP#

BH21

SMRCOMP_VOH

BF28

SMRCOMP_VOL

BH28

+DDR_MCH_REF

AV42

SM_PWROK

AR36

SM_REXT

BF17

SM_DRAMRST#

BC36

CLK_MCH_DREFCLK

B38

CLK_MCH_DREFCLK#

A38

MCH_SSCDREFCLK

E41

MCH_SSCDREFCLK#

F41

CLK_MCH_3GPLL

F43

CLK_MCH_3GPLL#

E43

DMI_TXN0

AE41

DMI_TXN1

AE37

DMI_TXN2

AE47

DMI_TXN3

AH39

DMI_TXP0

AE40

DMI_TXP1

AE38

DMI_TXP2

AE48

DMI_TXP3

AH40

DMI_RXN0

AE35

DMI_RXN1

AE43

DMI_RXN2

AE46

DMI_RXN3

AH42

DMI_RXP0

AD35

DMI_RXP1

AE44

DMI_RXP2

AF46

DMI_RXP3

AH43

B33

T43 PAD

B32

T44 PAD

G33

T45 PAD

F33

T46 PAD

E33

T47 PAD

C34

T48

For AMT function

CL_CLK0

AH37

CL_DATA0

AH36
AN36

CL_RST#

AJ35

CL_VREF

AH34

N28
M28

HDMICLK_NB

G36

HDMIDAT_NB

E36

MCH_CLKREQ#

K36

MCH_ICH_SYNC#

H36

B12

MCH_HDA_BCLK

B28

MCH_HDA_RST#

B30

MCH_HDA_SDIN0_R

B29

MCH_HDA_SDOUT

C29

MCH_HDA_SYNC

A28

Notice: Please check HDA power rail to select HDA controller.

M_CLK_DDR0 <14>
M_CLK_DDR1 <14>
M_CLK_DDR2 <15>
M_CLK_DDR3 <15>

M_CLK_DDR#0 <14>
M_CLK_DDR#1 <14>
M_CLK_DDR#2 <15>
M_CLK_DDR#3 <15>

DDR_CKE0_DI MMA <14>
DDR_CKE1_DI MMA <14>
DDR_CKE2_DI MMB <15>
DDR_CKE3_DI MMB <15>

DDR_CS0_DIMMA# <14>
DDR_CS1_DIMMA# <14>
DDR_CS2_DIMMB# <15>
DDR_CS3_DIMMB# <15>

M_ODT0 <14>
M_ODT1 <14>
M_ODT2 <15>

20mil

M_ODT3 <15>

1 2

R29 80.6_0402_1%

R30 0_0402_5%

1 2

R31 12K_0402_5%@

1 2

SM_DRAMRST# <14,15>

DDR3

CLK_MCH_D REFCLK <23>
CLK_MCH_D REFCLK# <23>
MCH_SSCDR EFCLK <23>
MCH_SSCDREFCLK# <23>

CLK_MCH_3GPLL <23>
CLK_MCH_3GPLL# <23>

DMI_TXN0 <29>
DMI_TXN1 <29>
DMI_TXN2 <29>
DMI_TXN3 <29>

DMI_TXP0 <29>
DMI_TXP1 <29>
DMI_TXP2 <29>
DMI_TXP3 <29>

DMI_RXN0 <29>
DMI_RXN1 <29>
DMI_RXN2 <29>
DMI_RXN3 <29>

DMI_RXP0 <29>
DMI_RXP1 <29>
DMI_RXP2 <29>
DMI_RXP3 <29>

connect to power CPU_CORE

CL_CLK0 <29>
CL_DATA 0 <29>

M_PWROK <29>
CL_RST# <29>

T49
T50

R41 56_0402_5%

1 2

R44 0_0402_5%GM@
R46 0_0402_5%GM@
R47 33_0402_5%GM@
R48 0_0402_5%GM@
R49 0_0402_5%GM@

1 2
1 2
1 2
1 2
1 2

HDMI CLK_NB <24>
HDMIDAT_NB <24>
MCH_ CLKREQ# <23>
MCH _ICH _SYN C# <29>
TSATN# <38>

+VCCP

R32 10K_0402_5%@

1 2

R33 499_0402_1%

1 2

1

+1.5V

12

R27

80.6_0402_1%

For Crestline: 20ohm
For Calero: 80.6ohm
For Cantiga: 80.6ohm

1.5V_PGOOD <48>
DDR3_SM_PW ROK <38>

MCH_HDA_BCLK

+VCCP

12

R36
1K_0402_1%

1

C58

0.1U_0402_16V4Z

2

HDA_BIT C LK_C OD EC <18,28,36>
HDA_RST_C OD EC# <18,28,36>
HDA_SDIN 0 <28>
HDA_SDO U T _C ODE C <18,28,36>
HDA_SYNC_CODEC <18,28,36>

R38
499_0402_1%

1

@

C57
10P_0402_50V8J

2

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAI NS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

3

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

2

Title

Size Docu me n t N u m ber Re v

C

Date: Sheet

Compal Electronics, Inc.

Cantiga GMCH(1/6)-GTL

KIWB3/B4_LA4551P

1

852Monday, J une 30, 2008

of

0.1

CyberForum.ru

5

D D

4

3

2

1

DDR_A_BS[0..2] <14>

DDR_A_RAS# <14>
DDR_A_CAS# <14>
DDR_A_WE# <14>

DDR_A_DM[0..7] <14>

DDR_A_DQS[0..7] <14>

DDR_A_DQS#[0..7] <14>

DDR_A_MA[0..14] <14>

DDR_A_D[0..63]<14>

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33 DDR_A_DQS#0
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AJ38

AJ41
AN38
AM38

AJ36

AJ40
AM44
AM42
AN43
AN44
AU40

AT38
AN41
AN39
AU44
AU42

AV39

AY44

BA40
BD43

AV41

AY43

BB41
BC40

AY37
BD38

AV37

AT36

AY38

BB38

AV36

AW36

BD13
AU11
BC11

BA12
AU13

AV13
BD12
BC12

BB9
BA9

AU10

AV9

BA11

BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6

AT5
AN10
AM11

AM5

AN12
AM13

AJ11
AJ12

AJ9
AJ8

U3D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#

SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3

DDR SYSTEM MEMORY A

SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

CANTIGA ES_FCBGA1329 GM@

BG18
AT25

BB20
BD20
AY20

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7

AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

DDR_A_BS1
DDR_A_BS2

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#1

DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11

DDR_A_MA12

DDR_A_MA13

DDR_A_MA14

DDR_A_BS0

BD21

DDR_B_D[0..63]<15>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AK47
AH46
AP47
AP46

AJ46

AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43

BF43
BE45
BC41

BF40

BF41
BG38

BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11

BG8

BH12

BF11

BF8
BG7
BC5
BC6
AY3
AY1

BF6

BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1

AL1

AL2

AJ1
AH1
AM2
AM3
AH3

AJ3

U3E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

DDR_B_BS0

BC16

SB_BS_0
SB_BS_1
SB_BS_2

SB_RAS#
SB_CAS#

SB_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2

DDR SYSTEM MEMORY B

SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

CANTIGA ES_FCBGA1329GM@

BB17
BB33

AU17
BG16
BF14

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6

AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

DDR_B_BS1
DDR_B_BS2

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

DDR_B_BS[0..2] <15>

DDR_B_RAS# <15>
DDR_B_CAS# <15>
DDR_B_WE# <15>

DDR_B_DM[0..7] <15>

DDR_B_DQS[0..7] <15>

DDR_B_DQS#[0..7] <15>

DDR_B_MA[0..14] <15>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Deciphered Date

Title

Size D ocument Number Rev

B

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga GMC H (2/6)-DDRII

KIWB3/B4_LA4551P

952Monday, June 30, 2008

1

0.1

CyberForum.ru

5

+3VS

4

3

PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15] <16>
PCIE_MTX_C_GRX_P[0..15] <16>

PCIE_GTX_C_MRX_N[0..15] <16>
PCIE_GTX_C_MRX_P[0..15] <16>

2

1

Strap Pin Table

1 2

R54 2.2K_0402_5%

D D

1 2

R55 2.2K_0402_5%

For Cantiga:2.37kohm
For Crestline:2.4kohm
For Calero: 1.5Kohm

Note: All LVDS data
signals/and it's compliments
should be routed
Differentially

C C

B B

GMCH_CRT_HSYNC<26>

GMCH_CRT_VSYNC<26>

change R64,R65 from 33ohm to 30ohm
by checklist2.0 & CRB1.0 05/08/08

A A

LVDS_SCL
LVDS_SDA

GMCH_ENBKL<25>

+3VS

LVDS_SCL<25>
LVDS_SDA<25>
GM_ENVDD<25>

LVDS_ACLK#<25>
LVDS_ACLK<25>
LVDS_BCLK#<25>
LVDS_BCLK<25>

LVDS_A0#<25>
LVDS_A1#<25>
LVDS_A2#<25>

R60 75_0402_5%GM@
R61 75_0402_5%GM@
R62 75_0402_5%GM@

GMCH_ENBKL

R56 10K_0402_5%

1 2

R57 10K_0402_5%

1 2

LVDS_SCL
LVDS_SDA
GM_ENVDD

1 2

R58 2.37K_0402_1%

LVDS_A0<25>
LVDS_A1<25>
LVDS_A2<25>

LVDS_B0#<25>
LVDS_B1#<25>
LVDS_B2#<25>

LVDS_B0<25>
LVDS_B1<25>
LVDS_B2<25>

1 2
1 2
1 2

LVDS_ACLK#
LVDS_ACLK
LVDS_BCLK#
LVDS_BCLK

LVDS_A0#
LVDS_A1#
LVDS_A2#

LVDS_A0
LVDS_A1
LVDS_A2

LVDS_B0#
LVDS_B1#
LVDS_B2#

LVDS_B0
LVDS_B1
LVDS_B2

Layout Note: Place 150 Ω termination
resistors close to GMCH

R63 150_0402_1%GM@

1 2

R64 150_0402_1%GM@

1 2

R65 150_0402_1%GM@

1 2

GMCH_CRT_B<26>
GMCH_CRT_G<26>
GMCH_CRT_R<26>

GMCH_CRT_CLK<26>
GMCH_CRT_DATA<26>

R66

R67 30_0402_1%GM@

5

30_0402_1%GM@

@

R68
0_0402_5%

GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B

GMCH_CRT_CLK
GMCH_CRT_DATA

Place the resistor within 500mils
(1.27mm)of the (G)MCH

U3C

L32

T51

T52

T53

T54

T55

TVA_DAC PCIE_MTX_GRX_N2
TVB_DAC
TVC_DAC

GMCH_CRT_B
GMCH_CRT_G
GMCH_CRT_R

20mil

@

R69
0_0402_5%

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

12

R70

1.02K_0402_1%

For Cantiga:1.02kohm
For Crestline:1.3kohm
For Calero: 255ohm

CANTIGA ES_FCBGA1329GM@

LVDS TV VGA

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8

PCI-EXPRESS GRAPHICS

PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PEGCOMP trace width
and spacing is 20/25 mils.

T37

PEGCOMP

T36

PCIE_GTX_C_MRX_N0

H44

PCIE_GTX_C_MRX_N1

J46

PCIE_GTX_C_MRX_N2

L44

PCIE_GTX_C_MRX_N3

L40

PCIE_GTX_C_MRX_N4

N41

PCIE_GTX_C_MRX_N5

P48

PCIE_GTX_C_MRX_N6

N44

PCIE_GTX_C_MRX_N7

T43

PCIE_GTX_C_MRX_N8

U43

PCIE_GTX_C_MRX_N9

Y43

PCIE_GTX_C_MRX_N10

Y48

PCIE_GTX_C_MRX_N11

Y36

PCIE_GTX_C_MRX_N12

AA43

PCIE_GTX_C_MRX_N13

AD37

PCIE_GTX_C_MRX_N14

AC47

PCIE_GTX_C_MRX_N15

AD39

PCIE_GTX_C_MRX_P0

H43

PCIE_GTX_C_MRX_P1

J44

PCIE_GTX_C_MRX_P2

L43

PCIE_GTX_C_MRX_P3

L41

PCIE_GTX_C_MRX_P4

N40

PCIE_GTX_C_MRX_P5

P47

PCIE_GTX_C_MRX_P6

N43

PCIE_GTX_C_MRX_P7

T42

PCIE_GTX_C_MRX_P8

U42

PCIE_GTX_C_MRX_P9

Y42

PCIE_GTX_C_MRX_P10

W47

PCIE_GTX_C_MRX_P11

Y37

PCIE_GTX_C_MRX_P12

AA42

PCIE_GTX_C_MRX_P13

AD36

PCIE_GTX_C_MRX_P14

AC48

PCIE_GTX_C_MRX_P15

AD40

PCIE_MTX_GRX_N0

J41

PCIE_MTX_GRX_N1

M46
M47

PCIE_MTX_GRX_N3

M40

PCIE_MTX_GRX_N4

M42

PCIE_MTX_GRX_N5

R48

PCIE_MTX_GRX_N6

N38

PCIE_MTX_GRX_N7

T40

PCIE_MTX_GRX_N8

U37

PCIE_MTX_GRX_N9

U40

PCIE_MTX_GRX_N10

Y40

PCIE_MTX_GRX_N11

AA46

PCIE_MTX_GRX_N12

AA37

PCIE_MTX_GRX_N13

AA40

PCIE_MTX_GRX_N14

AD43

PCIE_MTX_GRX_N15

AC46

PCIE_MTX_GRX_P0

J42

PCIE_MTX_GRX_P1

L46

PCIE_MTX_GRX_P2

M48

PCIE_MTX_GRX_P3

M39

PCIE_MTX_GRX_P4

M43

PCIE_MTX_GRX_P5

R47

PCIE_MTX_GRX_P6

N37

PCIE_MTX_GRX_P7

T39

PCIE_MTX_GRX_P8

U36

PCIE_MTX_GRX_P9

U39

PCIE_MTX_GRX_P10

Y39

PCIE_MTX_GRX_P11

Y46

PCIE_MTX_GRX_P12

AA36

PCIE_MTX_GRX_P13

AA39

PCIE_MTX_GRX_P14

AD42

PCIE_MTX_GRX_P15

AD46

PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0

PCIE_GTX_C_MRX_P3

CFG[2:0] FSB Freq select

CFG[4:3] Reserved
CFG5 (DMI select)

CFG6

CFG7 (Intel Management
Engine Crypto strap)
CFG8

CFG9
(PCIE Graphics Lane Reversal)

R59 49.9_0402_1%

1 2

Please check Power
source if want
support IAMT

+VCC_PEG

CFG10 (PCIE Lookback enable)

CFG11
CFG[13:12] (XOR/ALLZ)

CFG16 (FSB D y namic ODT)

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

CLOSE TO MCH

C62 0.1U_0402_10V7KPM@

1 2

C63 0.1U_0402_10V7KPM@

1 2

C64 0.1U_0402_10V7KPM@

1 2

C65 0.1U_0402_10V7KPM@

1 2

C66 0.1U_0402_10V7KPM@

1 2

C67 0.1U_0402_10V7KPM@

1 2

C68 0.1U_0402_10V7KPM@

1 2

C69 0.1U_0402_10V7KPM@

1 2

C70 0.1U_0402_10V7KPM@

1 2

C71 0.1U_0402_10V7KPM@

1 2

C72 0.1U_0402_10V7KPM@

1 2

C73 0.1U_0402_10V7KPM@

1 2

C74 0.1U_0402_10V7KPM@

1 2

C75 0.1U_0402_10V7KPM@

1 2

C76 0.1U_0402_10V7KPM@

1 2

C77 0.1U_0402_10V7KPM@

1 2

C78 0.1U_0402_10V7KPM@

1 2

C79 0.1U_0402_10V7KPM@

1 2

C80 0.1U_0402_10V7KPM@

1 2

C81 0.1U_0402_10V7KPM@

1 2

C82 0.1U_0402_10V7KPM@

1 2

C83 0.1U_0402_10V7KPM@

1 2

C84 0.1U_0402_10V7KPM@

1 2

C85 0.1U_0402_10V7KPM@

1 2

C86 0.1U_0402_10V7KPM@

1 2

C87 0.1U_0402_10V7KPM@

1 2

C88 0.1U_0402_10V7KPM@

1 2

C89 0.1U_0402_10V7KPM@

1 2

C90 0.1U_0402_10V7KPM@

1 2

C91 0.1U_0402_10V7KPM@

1 2

C92 0.1U_0402_10V7KPM@

1 2

C93 0.1U_0402_10V7KPM@

1 2

C94 0.1U_0402_10V7KGM@

1 2

C95 0.1U_0402_10V7KGM@

1 2

C96 0.1U_0402_10V7KGM@

1 2

C97 0.1U_0402_10V7KGM@

1 2

C98 0.1U_0402_10V7KGM@

1 2

C99 0.1U_0402_10V7KGM@

1 2

C100 0.1U_0402_10V7KGM@

1 2

C101 0.1U_0402_10V7KGM@

1 2

R71 0_0402_5%GM@

1 2

2008/03/25 2008/04/

3

Compal Secret Data

Deciphered Date

PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15

TMDS_B_CLK <24>
TMDS_B_CLK# <24>
TMDS_B_DATA0 <24>
TMDS_B_DATA0# <24>
TMDS_B_DATA1 <24>
TMDS_B_DATA1# <24>
TMDS_B_DATA2 <24>
TMDS_B_DATA2# <24>

TMDS_B_HPD# <24>

2

000 = FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved

0 = DMI x 2
1 = DMI x 4

0 = The iTPM Host Interface is enable
1 = The iTPM Hos t Interface is disable

0 =(TLS)chipe r s uite with no confidentiality
1 =(TLS)chipe r s uite with confidentiality

*

*

Reserved
0 = Reverse Lane,15->0, 14->1

1 = Normal Opera tion,Lane Number in order
0 = Enable

1 = Disable
Reserved
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled

ReservedCFG[15:14]
0 = Disabled

1 = Enabled
ReservedCFG[18:17]
0 = Normal Operation

(Lane number in Order)
1 = Reverse Lane

0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO are operating simu.

Title

Size D ocument Number Rev

Custom
Date: Sheet

*

(Default)11 = Normal Operation

*

*

*

Compal Electronics,Ltd.

Cantiga(3/6)-VGA/LVDS/TV
KIWB3/B4_LA4551P

1

*

*

10 52Monday, June 30, 2008

of

0.1

CyberForum.ru

5

0.1U_0402_16V4Z

GM@

+3VS_DAC_BG

0.1U_0402_16V4Z

1

C110

GM@

2

GM@

R85

1 2

0.022U_0402_16V7K

+3VS_DAC_CRT

1

1

C102

2

2

0.022U_0402_16V7K

1

C111

2

+VCCP

+3VS_TVDAC

1

C144

2

GM@

0.022U_0402_16V7K

1

C103

GM@

2

22U_0805_6.3VA

10U_0805_10V4Z

GM@

C112

1

GM@

2

C110

0_0402_5%

PM@

220U_D2_4VY_R15M

1

C145

0.1U_0402_16V4Z

2

GM@

C838

@

+1.5VS_PEG_BG: 0.414mA
(0.1UF*1)

1 2

0_0805_5%

1

+

C132

2

R82

0_0603_5%

VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1)

VCCA_DAC_BG: 2.68mA (0.1UF*1, 0.01UF*1)

+1.5VS_PEG_BG

R78

12

0_0603_5%

C129

C133

1

2

12

1

4.7U_0805_10V4Z
C130

2

+1.05VS_A_SM_CK

1U_0402_6.3V4Z

10U_0805_10V4Z

1

C134

2

+1.5VS

R81

10U_0805_10V4Z

+3VS

R72

1 2

0_0603_5%

GM@

+3VS

D D

C C

B B

R74

1 2

0_0603_5%

GM@

C102

0_0402_5%

PM@

VCCA_SM:720mA
(22UF*2, 4.7U F * 1, 1UF*1)

VCCA_SM_CK: 220mA
(22UF*1, 2.2U F * 1, 0.1UF*1)

+3VS

0_0603_5%

C144

0_0402_5%

PM@

4

+3VS_DAC_CRT

+3VS_DAC_BG

+1.05VS_DPLLA
+1.05VS_DPLLB

+1.05VS_HPLL
+1.05VS_MPLL

+1.8V_TXLVDS

1000P_0402_50V7K

1

C122

0.1U_0402_16V4Z

2

C137

1

2

+3VS_TVDAC: 40mA
(0.1UF*1, 0.01UF*1 for
each DAC)

VCC_HDA: 50mA
(0.1UF*1)

+1.05VS_PEGPLL

+1.05VS_A_SM

1

1U_0603_10V4Z

2

1U_0603_10V4Z

C138

+3VS_TVDAC

+1.05VS_PEGPLL

1

C120

2

0.1U_0402_16V4Z

1

2

+1.5VS_TVDAC
+1.5VS_QDAC

+1.05VS_HPLL

+1.8V_LVDS

+1.5VS

20 mils

1

C131

2

U3H

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

AD48

VCCA_PEG_BG

AA48

VCCA_PEG_PLL

AR20

VCCA_SM_1

AP20

VCCA_SM_2

AN20

VCCA_SM_3

AR17

VCCA_SM_4

AP17

VCCA_SM_5

AN17

VCCA_SM_6

AT16

VCCA_SM_7

AR16

VCCA_SM_8

AP16

VCCA_SM_9

AP28

VCCA_SM_CK_1

AN28

VCCA_SM_CK_2

AP25

VCCA_SM_CK_3

AN25

VCCA_SM_CK_4

AN24

VCCA_SM_CK_5

AM28

VCCA_SM_CK_NCTF_1

AM26

VCCA_SM_CK_NCTF_2

AM25

VCCA_SM_CK_NCTF_3

AL25

VCCA_SM_CK_NCTF_4

AM24

VCCA_SM_CK_NCTF_5

AL24

VCCA_SM_CK_NCTF_6

AM23

VCCA_SM_CK_NCTF_7

AL23

VCCA_SM_CK_NCTF_8

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS_1

L37

VCCD_LVDS_2

POWER

A SM

HDA

LVDS D TV/CRT

U3

CRTPLLA LVDSA PEG

TV

VTT

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

VCC_TX_LVDS

A CK

HV

DMI PEG

VTTLF

CANTIGA ES_FCBGA1329GM@

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

VCC_HV_1
VCC_HV_2
VCC_HV_3

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4

VTTLF1
VTTLF2
VTTLF3

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

B22
B21
A21

BF21
BH20
BG20
BF20

K47

C35
B35
A35

V48
U48
V47
U47
U46

AH48
AF48
AH47
AG47

A8
L1
AB2

3

+VCCP

+1.8V_TXLVDS

+VCC_PEG

+VCC_DMI

VCC_DMI: 456mA
(0.1UF*1)

20mils

1

C150

2

220U_D2_4VM

1

+

C104

2

1

C1130.47U_0402_6.3V6K

2

+V1.05VS_AXF

+1.5V_SM_CK

0.47U_0402_6.3V6K

1

C151

2

2

+1.05VS_DPLLA

+1.05VS_HPLL

0.1U_0402_16V4Z

+1.05VS_MPLL

0.1U_0402_16V4Z

+1.05VS_PEGPLL

2 1

0.1U_0402_16V4Z

C106

1

2
GM@

+1.05VS_DPLLB

0.1U_0402_16V4Z

C115

1

2
GM@

1

C123

2

1

C135

2

0.1U_0402_16V4Z
C146

1

2

+VCCP_D

D3

@

CH751H-40PT_SOD323-2

4.7U_0805_10V4Z

1

@

C105

2

4.7U_0805_10V4Z

1

C114

2

+3VS_HV

0.1U_0402_16V4Z

1

C142

2

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

1

C152

2

+VCCP

+3VS

1 2

10U_0805_10V4Z

MCK3225151YZF 1210

1

C107

2

GM@

+1.05VS_DPLLA
+1.05VS_DPLLB: 64.8mA
(470UF*1, 0.1UF*1)

R76

1 2

10U_0805_10V4Z

MCK3225151YZF 1210

1

GM@

C116

2

GM@

R79

MBK2012121YZF_0805

1

C124

2.2U_0603_6.3V4Z

2

R83

MBK2012121YZF_0805

1

C139

2.2U_0603_6.3V4Z

2

BLM18PG121SN1D_0603

1

C147

2.2U_0603_6.3V4Z

2

R87

@

10_0402_5%

R73

+VCCP

GM@

+VCCP

+1.05VS_HPLL: 24mA
(4.7UF*1, 0.1UF*1)

12

+VCCP

1.05VS_MPLL: 139.2mA
(22UF*1, 0.1UF*1)

12

+VCCP

+1.5VS_PEG_PLL: 50mA
(0.1UF*1)

L1

12

+VCCP

R88

12

0_0402_5%

12

C140

0_0402_5%

PM@

+3VS_HV

C126

0_0402_5%

PM@

40 mils

1000P_0402_50V7K

GM@

0316 add

0316 add

+V1.05VS_AXF

10U_0805_10V4Z

+1.5VS_TVDAC

C126

1

C140

2

+VCC_PEG

1

C143

+

2

+VCC_DMI

C153

1

2

C108

1

2

0.022U_0402_16V7K

1

2

+1.8V_TXLVDS

C141

220U_D2_4VM

C148

1U_0603_10V4Z

C154

+1.5V_SM_CK

C117

1

C127

2

GM@

GM@

10U_0805_10V4Z

1

2

10U_0805_10V4Z

1

2

10U_0805_10V4Z

1

2

1U_0603_10V4Z

1

2

1

2

0.1U_0402_16V4Z

C128

R84

0_0603_5%

GM@

GM@

0_0805_5%

C155

1

VCC_AXF: 321.35mA
(10UF*1, 1UF*1)

1 2

R75

0_0603_5%

C109

VCC_SM_CK: 119.85mA
(10UF*1, 0.1UF*1)

0.1U_0402_16V4Z

10U_0805_10V4Z

1

2

10U_0805_10V4Z

1

VCCD_TVDAC: 58.696mA

2

(0.1UF*1, 0.01UF*1)

GM@

12

+1.8V_TXLVDS: 118.8mA
(22UF*1, 1000PF*1)

+VCCP

R166

12

R86

0_0805_5%

10U_0805_10V4Z

1

2

+VCCP

R77

1 2

0_0805_5%

C118

R80

0_0603_5%

GM@

+1.8V

12

+1.5V

+1.5VS

12

+VCCP

PM

PM@

C156

1

C157

2

VCCD_QDAC: 48.363mA
(0.1UF*1, 0.01UF*1)

R89

0_0603_5%

10U_0805_10V4Z

0.1U_0402_16V4Z

1

1

C158

GM@

2

2

+1.8V_LVDS

12

+1.5VS

GM@

10U_0805_10V4Z

1

C159

2

+1.5VS_QDAC

1U_0402_6.3V4Z

A A

GM@

5

1.8V_LVDS: 60.311111mA
(1UF*1)

R90

0_0603_5%

1U_0603_10V4Z

GM@

C160

1

2

GM@

12

C160

0_0603_5%

PM@

4

+1.8V

Security Classification

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY COMPAL EL ECTRONICS, IN C. NEITHER TH IS SHEET NOR TH E INFORMATIO N IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR W RITTEN CONSE NT OF COMPAL EL ECTRONICS, I NC.

3

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Custom

Crestline GMCH (4/6)-VCC

KIWB3/B4_LA4551P

11 52Thursday, June 26, 2008

1

of

0.1

CyberForum.ru

5

4

3

2

1

U3F

1782mA

+1.5V

220U_D2_4VM_R15

C168

GM@

J1

112

JUMP_43X118

1

GM@

1

+

C174

2

2

220U_D2_4VM_R15

1

+

2

@

2

10U_0805_10V4Z

GM@

GM@

1

C176

C175

2

10U_0805_10V4Z

C176

0_0805_5%

PM@

C171

+VCCP

0.1U_0402_16V4Z

C172

1

2

D D

0.22U_0402_10V4Z

10U_0805_10V4Z

C C

B B

0.22U_0402_10V4Z

C170

1

1

C167

2

1

2

2

AG34
AC34
AB34
AA34

AM33

AK33

AJ33
AG33
AF33

AE33
AC33
AA33

W33

AH28
AF28
AC28
AA28

AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24

AJ23
AH23
AF23

U3G

VCC_1
VCC_2
VCC_3
VCC_4

Y34

VCC_5

V34

VCC_6

U34

VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13
VCC_14
VCC_15

Y33

VCC_16
VCC_17

V33

VCC_18

U33

VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34

T32

VCC_35

VCC CORE

POWER

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8

VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28

VCC NCTF

VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

CANTIGA ES_FCBGA1329GM@

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

+VCCP

+VCCP +AXG_CORE

GM@

C173

1U_0603_10V4Z

C162

1

2

1

2

10U_0805_10V4Z

+AXG_CORE

0.1U_0402_16V4Z

GM@

C177

0.01U_0402_16V7K

2

1

1

2

C163

AP33

VCC_SM_1

AN33

VCC_SM_2

BH32

VCC_SM_3

BG32

VCC_SM_4

BF32

VCC_SM_5

BD32

VCC_SM_6

BC32

VCC_SM_7

BB32

VCC_SM_8

BA32

VCC_SM_9

AY32

VCC_SM_10

AW32

VCC_SM_11

AV32

VCC_SM_12

AU32

VCC_SM_13

AT32

VCC_SM_14

AR32

VCC_SM_15

AP32

VCC_SM_16

AN32

VCC_SM_17

BH31

VCC_SM_18

BG31

VCC_SM_19

BF31

VCC_SM_20

BG30

VCC_SM_21

BH29

VCC_SM_22

BG29

VCC_SM_23

BF29

VCC_SM_24

BD29

VCC_SM_25

BC29

VCC_SM_26

BB29

VCC_SM_27

BA29

VCC_SM_28

AY29

VCC_SM_29

AW29

VCC_SM_30

AV29

VCC_SM_31

AU29

VCC_SM_32

AT29

VCC_SM_33

AR29

VCC_SM_34

AP29

VCC_SM_35

BA36

VCC_SM_36/NC

BB24

VCC_SM_37/NC

BD16

VCC_SM_38/NC

BB21

VCC_SM_39/NC

AW16

VCC_SM_40/NC

AW13

VCC_SM_41/NC

AT13

VCC_SM_42/NC

Y26

VCC_AXG_1

AE25

VCC_AXG_2

AB25

VCC_AXG_3

AA25

VCC_AXG_4

AE24

VCC_AXG_5

AC24

VCC_AXG_6

AA24

VCC_AXG_7

Y24

VCC_AXG_8

AE23

VCC_AXG_9

AC23

VCC_AXG_10

AB23

VCC_AXG_11

AA23

VCC_AXG_12

AJ21

VCC_AXG_13

AG21

VCC_AXG_14

AE21

VCC_AXG_15

AC21

VCC_AXG_16

AA21

VCC_AXG_17

Y21

VCC_AXG_18

AH20

VCC_AXG_19

AF20

VCC_AXG_20

AE20

VCC_AXG_21

AC20

VCC_AXG_22

AB20

VCC_AXG_23

AA20

VCC_AXG_24

T17

VCC_AXG_25

T16

VCC_AXG_26

AM15

VCC_AXG_27

AL15

VCC_AXG_28

AE15

VCC_AXG_29

AJ15

VCC_AXG_30

AH15

VCC_AXG_31

AG15

VCC_AXG_32

AF15

VCC_AXG_33

AB15

VCC_AXG_34

AA15

VCC_AXG_35

Y15

VCC_AXG_36

V15

VCC_AXG_37

U15

VCC_AXG_38

AN14

VCC_AXG_39

AM14

VCC_AXG_40

U14

VCC_AXG_41

T14

VCC_AXG_42

AJ14

T56
T57

AH14

VCC_AXG_SENSE
VSS_AXG_SENSE

VCC_AXG_NTCF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC SM

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43

VCC GFX NCTF

VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52

POWER

VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

VCC GFX

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

A A

CANTIGA ES_FCBGA1329GM@

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

AV44
BA37
AM40
AV21
AY5
AM10
BB13

+AXG_CORE

0.1U_0402_16V4Z

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

Check : power

C164

1

GM@

2

0.22U_0402_10V4Z

C166

0_0603_5%

PM@

C181 0.22U_0402_10V4Z

C180 0.1U_0402_16V4Z

C179 0.1U_0402_16V4Z

1

1

1

2

2

2

4.7U_0603_6.3V6K

C165

1

GM@

2

C182 0.22U_0402_10V4Z

1

1

2

2

C166

1

GM@

2

C184 1U_0402_6.3V4Z

C185 1U_0402_6.3V4Z

C183 0.47U_0402_6.3V6K

1

1

2

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Crestline GMCH (5/6)-VCC

KIWB3/B4_LA4551P

12 52Thursd a y, June 26, 2008

1

0.1

of

CyberForum.ru

5

U3I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

VSS_8

AD47

VSS_9

AB47

VSS_10

Y47

VSS_11

T47

BD46
BA46
AY46
AV46
AR46
AM46

BF44
AH44
AD44
AA44

BC43
AV43
AU43
AM43

BG42
AY42
AT42
AN42

AJ42
AE42

BD41
AU41
AM41
AH41
AD41
AA41

BG40
BB40
AV40
AN40

AT39
AM39

AJ39
AE39

BH38
BC38
BA38
AU38
AH38
AD38
AA38

BF37
BB37

AW37

AT37
AN37

AJ37

BG36
BD36
AK15
AU36

VSS_12

N47

VSS_13

L47

VSS_14

G47

VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21

V46

VSS_22

R46

VSS_23

P46

VSS_24

H46

VSS_25

F46

VSS_26
VSS_27
VSS_28
VSS_29
VSS_30

Y44

VSS_31

U44

VSS_32

T44

VSS_33

M44

VSS_34

F44

VSS_35
VSS_36
VSS_37
VSS_38
VSS_39

J43

VSS_40

C43

VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47

N42

VSS_48

L42

VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55

Y41

VSS_56

U41

VSS_57

T41

VSS_58

M41

VSS_59

G41

VSS_60

B41

VSS_61
VSS_62
VSS_63
VSS_64
VSS_65

H40

VSS_66

E40

VSS_67
VSS_68
VSS_69
VSS_70
VSS_71

N39

VSS_72

L39

VSS_73

B39

VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81

Y38

VSS_82

U38

VSS_83

T38

VSS_84

J38

VSS_85

F38

VSS_86

C38

VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93

H37

VSS_94

C37

VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

VSS

CANTIGA ES_FCBGA1329GM@

D D

C C

B B

A A

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

4

U3J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

VSS_230

M17

VSS_231

H17

VSS_232

C17

VSS_233

BA16

VSS_235

AU16

VSS_237

AN16

VSS_238

N16

VSS_239

K16

VSS_240

G16

VSS_241

E16

VSS_242

BG15

VSS_243

AC15

VSS_244

W15

VSS_245

A15

VSS_246

BG14

VSS_247

AA14

VSS_248

C14

VSS_249

BG13

VSS_250

BC13

VSS_251

BA13

VSS_252

AN13

VSS_255

AJ13

VSS_256

AE13

VSS_257

N13

VSS_258

L13

VSS_259

G13

VSS_260

E13

VSS_261

BF12

VSS_262

AV12

VSS_263

AT12

VSS_264

AM12

VSS_265

AA12

VSS_266

J12

VSS_267

A12

VSS_268

BD11

VSS_269

BB11

VSS_270

AY11

VSS_271

AN11

VSS_272

AH11

VSS_273

Y11

VSS_275

N11

VSS_276

G11

VSS_277

C11

VSS_278

BG10

VSS_279

AV10

VSS_280

AT10

VSS_281

AJ10

VSS_282

AE10

VSS_283

AA10

VSS_284

M10

VSS_285

BF9

VSS_286

BC9

VSS_287

AN9

VSS_288

AM9

VSS_289

AD9

VSS_290

G9

VSS_291

B9

VSS_292

BH8

VSS_293

BB8

VSS_294

AV8

VSS_295

AT8

VSS_296

CANTIGA ES_FCBGA1329GM@

VSS

3

VSS NCTF

VSS SCB

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350

VSS_351
VSS_352
VSS_353
VSS_354

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5

NC

NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

U24
U28
U25
U29

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1
A3

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

2

1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cantiga GMCH (6/6)-GND

KIWB3/B4_LA4551P

13 52Thursd a y, June 26, 2008

1

of

0.1

CyberForum.ru

5

DDR_A_DQS#[0..7]<9>

DDR_A_D[0..63]<9>

DDR_A_DM[0..7]<9>
DDR_A_DQS[0..7]<9>
DDR_A_MA[0..14]<9>

D D

Layout Note:

C C

Layout Note:
Place near JP4.203 & JP4.204

B B

A A

Place near JP4

+1.5V

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

C188

2

+0.75V

1U_0603_10V4Z

C189

1U_0603_10V4Z

2

C200

1

5

C187

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

C190

2

2

1U_0603_10V4Z

2

2

C201

C202

1

1

+V_DDR3_DIMM_REF<15>

<BOM Structure>

Layout Note: Place these 4 Caps near Command
and Control signals of DIMMA

0.1U_0402_16V4Z

1

2

<BOM Structure>

C204

C193

0.1U_0402_16V4Z
C194

1

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

C192

C191

2

2

1U_0603_10V4Z

10U_0805_6.3V6M

2

1

C203

1

2

4

+V_DDR3_DIMM_REF

1

C186

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C195

1

1

2

2

4

+1.5V

12

12

C196

R91
100_0402_1%

R92

100_0402_1%

1

+

C197
470U_D2_2.5VM_R15

@

2

+V_DDR3_DIMM_REF

3

+V_DDR3_DIMM_REF

DDR_A_D0
DDR_A_D1

DDR_A_DM0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_D9
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11
DDR_A_D16

DDR_A_D17
DDR_A_DQS#2

DDR_A_DQS2
DDR_A_D18

DDR_A_D19
DDR_A_D24

DDR_A_D25
DDR_A_DM3
DDR_A_D26

DDR_A_D27

1

2

2.2U_0603_6.3V4Z

DDR_CKE0_DIMMA

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3

DDR_A_MA1
M_CLK_DDR0

M_CLK_DDR#0
DDR_A_MA10

DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49
DDR_A_DQS#6

DDR_A_DQS6
DDR_A_D50

DDR_A_D51
DDR_A_D56

DDR_A_D57
DDR_A_DM7
DDR_A_D58

DDR_A_D59

1 2

10K_0402_5%

1

C206

2

R96

0.1U_0402_16V4Z

DDR_CKE0_DIMMA<8>

DDR_A_BS2<9>

M_CLK_DDR0<8>
M_CLK_DDR#0<8>

DDR_A_BS0<9>

DDR_A_WE#<9>

DDR_A_CAS#<9> M_ODT0 <8>

DDR_CS1_DIMMA#<8>

+3VS

C205

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.5V +1.5V

JP2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

12

R97

10K_0402_5%

2007/09/29 2007/09/29

VTT1

205

G1

FOX _AS0A626-U2RN-7F_RV

Compal Secret Data

DQ4
DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1

VDD2

A15
A14

VDD4

A11

A7

VDD6

A6
A4

VDD8

A2
A0

VDD10

CK1
CK1#

VDD12

BA1

RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

SCL
VTT2

G2

Deciphered Date

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

2

DDR_A_D4
DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

DDR_A_DM1
SM_DRAMRST#

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2
DDR_A_D22

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_BS1

DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
M_ODT1

DDR_VREF_CA_DIMMA
DDR_A_D36

DDR_A_D37
DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53
DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63
PM_EXTTS#0_1

CLK_SMBDATA
CLK_SMBCLK

+0.75V

+0.75V

2

SM_DRAMRST# <8,15>

DDR_CKE1_DIMMA <8>

M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>

DDR_A_BS1 <9>
DDR_A_RAS# <9>

DDR_CS0_DIMMA# <8>

M_ODT1 <8>

R95

1 2

0_0402_5%

PM_EXTTS#0 <8,15>

CLK_SMBDATA <15,23>
CLK_SMBCLK <15,23>

DDR3 SO-DIMM A
REVERSE

Title

Size Document Number Rev

Custom

Date: Sheet

1

+V_DDR3_DIMM_REF

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

1

C199

C198

2

2

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

KIWB1/B2_LA4601P

14 52Monday, June 30, 2008

1

1.0

of

CyberForum.ru

5

DDR_B_DQS#[0..7]<9>

DDR_B_D[0..63]<9>

DDR_B_DM[0..7]<9>
DDR_B_DQS[0..7]<9>
DDR_B_MA[0..14]<9>

D D

C C

B B

A A

Layout Note:
Place near JP5

Layout Note: Place these 4 Caps near Command

+1.5V

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

C207

2

Layout Note:
Place near JP5.203 & JP5.204

+0.75V

1U_0603_10V4Z

C209

C208

2

1U_0603_10V4Z

1U_0603_10V4Z

2

2

C218

C219

1

1

10U_0805_6.3V6M

1

2

1U_0603_10V4Z

2

C220

1

5

1

1

C211

C210

2

2

10U_0805_6.3V6M

1

2

C222

C221

2

1

and Control signals of DIMMA

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C212

2

C214

C213

1

1

2

2

0.1U_0402_16V4Z

1

2

4

+V_DDR3_DIMM_REF

+V_DDR3_DIMM_REF<14>

0.1U_0402_16V4Z

C215

C216

1

1

+

C217
470U_D2_2.5VM_R15

2

@

2

DDR_B_BS2<9>

M_CLK_DDR2<8>
M_CLK_DDR#2<8>

DDR_B_BS0<9>

DDR_B_WE#<9>

DDR_B_CAS#<9> M_ODT2 <8>

DDR_CS3_DIMMB#<8>

+3VS

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C225

2

0.1U_0402_16V4Z

3

DDR_B_D0
DDR_B_D1

DDR_B_DM0
DDR_B_D2

DDR_B_D3
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D10

DDR_B_D11
DDR_B_D16

DDR_B_D17
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D18

DDR_B_D19
DDR_B_D24

DDR_B_D25
DDR_B_DM3
DDR_B_D26

DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3

DDR_B_MA1
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_MA10

DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_B_MA13

DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49
DDR_B_DQS#6

DDR_B_DQS6
DDR_B_D50

DDR_B_D51
DDR_B_D56

DDR_B_D57
DDR_B_DM7
DDR_B_D58

DDR_B_D59

R99

1 2

10K_0402_5%

1 2

R100

3

+1.5V +1.5V

JP3

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

10K_0402_5%

VTT1

205

G1

FOX_AS0A626-UARN-7F _RV

2007/09/29 2007/09/29

2
4

DQ4

6

DQ5

8

VSS3

10

DQS#0

12

DQS0

14

VSS6

16

DQ6

18

DQ7

20

VSS8

22

DQ12

24

DQ13

26

VSS10

28

DM1

30
32
34

DQ14

36

DQ15

38
40

DQ20

42

DQ21

44
46

DM2

48

VSS17

50

DQ22

52

DQ23

54

VSS19

56

DQ28

58

DQ29

60

VSS21

62
64

DQS3

66
68

DQ30

70

DQ31

72

74

CKE1

76

VDD2

78

A15

80

A14

82

VDD4

84

A11

86

A7

88

VDD6

90

A6

92

A4

94

VDD8

96

A2

98

A0

100

VDD10

102

CK1

104

CK1#

106

VDD12

108

BA1

110

RAS#

112

VDD14

114

S0#

116

ODT0

118

VDD16

120

ODT1

122

NC2

124

VDD18

126

VREF_CA

128

VSS28

130

DQ36

132

DQ37

134

VSS30

136

DM4

138

VSS31

140

DQ38

142

DQ39

144

VSS33

146

DQ44

148

DQ45

150

VSS35

152

DQS#5

154

DQS5

156

VSS38

158

DQ46

160

DQ47

162

VSS40

164

DQ52

166

DQ53

168

VSS42

170

DM6

172

VSS43

174

DQ54

176

DQ55

178

VSS45

180

DQ60

182

DQ61

184

VSS47

186

DQS#7

188

DQS7

190

VSS50

192

DQ62

194

DQ63

196

VSS52

198

EVENT#

200

SDA

202

SCL

204

VTT2

206

G2

+0.75V

Compal Secret Data

Deciphered Date

DDR_B_D4
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR_B_DM1
SM_DRAMRST#

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31

DDR_CKE3_DIMMB

DDR_VREF_CA_DIMMB

2

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA0
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_BS1

DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
M_ODT3

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63
PM_EXTTS#0_1

CLK_SMBDATA
CLK_SMBCLK

+0.75V

2

1

SM_DRAMRST# <8,14>

DDR_CKE3_DIMMB <8>DDR_CKE2_DIMMB<8>

M_CLK_DDR3 <8>
M_CLK_DDR#3 <8>

DDR_B_BS1 <9>
DDR_B_RAS# <9>

DDR_CS2_DIMMB# <8>

M_ODT3 <8>

R98

0_0402_5%

1 2

0.1U_0402_16V4Z

2.2U_0805_16V4Z

same with intel DDR3 CRB connection

PM_EXTTS#0 <8,14>

CLK_SMBDATA <14,23>
CLK_SMBCLK <14,23>

1

1

C224

C223

2

2

DDR3 SO-DIMM B

+V_DDR3_DIMM_REF

REVERSE

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

KIWB1/B2_LA4601P

1

1.0

of

15 52Monday, June 30, 2008

CyberForum.ru

5

PCIE_MTX_C_GRX_N[0..15]<10>
PCIE_MTX_C_GRX_P[0..15]<10>

PCIE_GTX_C_MRX_N[0..15]<10>
PCIE_GTX_C_MRX_P[0..15]<10>

D D

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2

C C

B B

PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15

PLT_RST#<8,27,31,32>

for GT21x request

PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]

C226 0.1U_0402_16V7KPM@

1 2

C227 0.1U_0402_16V7KPM@

1 2

C228 0.1U_0402_16V7KPM@

1 2

C230 0.1U_0402_16V7KPM@

1 2

C231 0.1U_0402_16V7KPM@

1 2

C232 0.1U_0402_16V7KPM@

1 2

C233 0.1U_0402_16V7KPM@

1 2

C234 0.1U_0402_16V7KPM@

1 2

C235 0.1U_0402_16V7KPM@

1 2

C236 0.1U_0402_16V7KPM@

1 2

C237 0.1U_0402_16V7KPM@

1 2

C238 0.1U_0402_16V7KPM@

1 2

C239 0.1U_0402_16V7KPM@

1 2

C240 0.1U_0402_16V7KPM@

1 2

C241 0.1U_0402_16V7KPM@

1 2

C242 0.1U_0402_16V7KPM@

1 2

C243 0.1U_0402_16V7KPM@

1 2

C248 0.1U_0402_16V7KPM@

1 2

C249 0.1U_0402_16V7KPM@

1 2

C250 0.1U_0402_16V7KPM@

1 2

C251 0.1U_0402_16V7KPM@

1 2

C252 0.1U_0402_16V7KPM@

1 2

C253 0.1U_0402_16V7KPM@

1 2

C254 0.1U_0402_16V7KPM@

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

PLT_RST#

PM@
PM@

CLK_PCIE_VGA< 23>
CLK_PCIE_VGA#<23>

@

R115
10K_0402_5%

1 2

C255 0.1U_0402_16V7K
C256 0.1U_0402_16V7K
C257 0.1U_0402_16V7KPM@
C258 0.1U_0402_16V7KPM@
C259 0.1U_0402_16V7KPM@
C260 0.1U_0402_16V7KPM@
C262 0.1U_0402_16V7KPM@
C263 0.1U_0402_16V7KPM@

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

PCIE_GTX_MRX_P0
PCIE_GTX_MRX_N0
PCIE_GTX_MRX_P1
PCIE_GTX_MRX_N1
PCIE_GTX_MRX_P2
PCIE_GTX_MRX_N2
PCIE_GTX_MRX_P3
PCIE_GTX_MRX_N3
PCIE_GTX_MRX_P4
PCIE_GTX_MRX_N4
PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N5
PCIE_GTX_MRX_P6
PCIE_GTX_MRX_N6
PCIE_GTX_MRX_P7
PCIE_GTX_MRX_N7
PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N8
PCIE_GTX_MRX_P9
PCIE_GTX_MRX_N9
PCIE_GTX_MRX_P10
PCIE_GTX_MRX_N10
PCIE_GTX_MRX_P11
PCIE_GTX_MRX_N11
PCIE_GTX_MRX_P12
PCIE_GTX_MRX_N12
PCIE_GTX_MRX_P13
PCIE_GTX_MRX_N13
PCIE_GTX_MRX_P14
PCIE_GTX_MRX_N14
PCIE_GTX_MRX_P15
PCIE_GTX_MRX_N15

CLK_PCIE_VGA
CLK_PCIE_VGA#

+1.1VS

R116

2.49K_0402_1%

PM@

1 2

External Spread Spectrum

U7

1

REFOUT

2

OSC_OUT

A A

3

ASM3P2872AF-06OR_TSOT-23-6@

XOUT
XIN/CLKIN

VSS

MODOUT

VDD

6
5
4

OSC_SPREAD

+3VS

1

@

C265

0.1U_0402_16V4Z

2

4

U5A

AP17

PEX_RX0

AN17

PEX_RX0_N

AN19

PEX_RX1

AP19

PEX_RX1_N

AR19

PEX_RX2

AR20

PEX_RX2_N

AP20

PEX_RX3

AN20

PEX_RX3_N

AN22

PEX_RX4

AP22

PEX_RX4_N

AR22

PEX_RX5

AR23

PEX_RX5_N

AP23

PEX_RX6

AN23

PEX_RX6_N

AN25

PEX_RX7

AP25

PEX_RX7_N

AR25

PEX_RX8

AR26

PEX_RX8_N

AP26

PEX_RX9

AN26

PEX_RX9_N

AN28

PEX_RX10

AP28

PEX_RX10_N

AR28

PEX_RX11

AR29

PEX_RX11_N

AP29

PEX_RX12

AN29

PEX_RX12_N

AN31

PEX_RX13

AP31

PEX_RX13_N

AR31

PEX_RX14

AR32

PEX_RX14_N

AR34

PEX_RX15

AP34

PEX_RX15_N

AL17

PEX_TX0

AM17

PEX_TX0_N

AM18

PEX_TX1

AM19

PEX_TX1_N

AL19

PEX_TX2

AK19

PEX_TX2_N

AL20

PEX_TX3

AM20

PEX_TX3_N

AM21

PEX_TX4

AM22

PEX_TX4_N

AL22

PEX_TX5

AK22

PEX_TX5_N

AL23

PEX_TX6

AM23

PEX_TX6_N

AM24

PEX_TX7

AM25

PEX_TX7_N

AL25

PEX_TX8

AK25

PEX_TX8_N

AL26

PEX_TX9

AM26

PEX_TX9_N

AM27

PEX_TX10

AM28

PEX_TX10_N

AL28

PEX_TX11

AK28

PEX_TX11_N

AK29

PEX_TX12

AL29

PEX_TX12_N

AM29

PEX_TX13

AM30

PEX_TX13_N

AM31

PEX_TX14

AM32

PEX_TX14_N

AN32

PEX_TX15

AP32

PEX_TX15_N

AR16

PEX_REFCLK

AR17

PEX_REFCLK_N

AR13

PEX_CLKREQ_N

AM16

PEX_RST_N

AG21

PEX_TERMP

1 2

0_0402_5%
R723

XTAL_OUTBUFF
XTAL_SSIN

AG19

N10@

OSC_OUT XTAL_OUTBUFF

OSC_SPREAD

PEX_RFU1

AG20

PEX_RFU2

D1

XTAL_OUTBUFF

D2

XTAL_SSIN

R121 22_0402_5%@

1 2

R123 22_0402_5%@

1 2

Part 1 of 6

SWAP_RDY_A/GPIO22

PCI EXPRESS

PEX_TSTCLK_OUT_N

CLK

NB9P-GS_BGA969~D9M@

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18

DVO / GPIO

GPIO19
GPIO20
GPIO21

STEREO/GPIO23

DACA_HSYNC
DACA_VSYNC

DACA_RED

DACA_BLUE

DACA_GREEN

DACA_RSET
DACA_VREF

DACB_RED

DACB_BLUE

DACB_GREEN

DACB_RSET

DACB_CSYNC

DACB_VREF

DACsI2C

DACC_HSYNC
DACC_VSYNC

DACC_RED

DACC_BLUE

DACC_GREEN

DACC_RSET
DACC_VREF

I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CD_SCL
I2CD_SDA
I2CE_SCL
I2CE_SDA
I2CH_SCL
I2CH_SDA
I2CS_SCL
I2CS_SDA

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

JTAG_TRST_N

TESTMODE

TEST

PEX_TSTCLK_OUT

XTAL_IN

XTAL_OUT

12

R122
10K_0402_5%

PM@

XTAL_SSIN

12

PM@

R124
10K_0402_5%

K1
K2
K3
H3
H2
H1
H4
H5
H6
J7
K4
K5
H7
J4
J6
L1
L2
L4
M4
L7
L5
K6
L6
M6

AM13
AL13
AM15
AL14
AM14
AK13
AK12

AA4
Y4
AB4
AB6
AB5
AC5

AM1
AM2
AK4
AJ4
AL4
AH7
AK6

G1
G4
G3
G2
E3
E4
F4
G5
D5
E5
F6
G6
E2
E1

AP14
AN14
AN16
AR14
AP16
AP35

AJ17
AJ18

B1
B2

3

NV_INVTPWM
VGA_ENVDD
VGA_ENBKL
GPU_VID0
GPU_VID1

MEM_VREF

1 2

R719 10K_0402_5%PM@

1 2

R720 10K_0402_5%PM@

VGA_HSYNC
VGA_VSYNC
VGA_CRT_R
VGA_CRT_B
VGA_CRT_G
DACA_VREF
DACA_RSET

HDMI_CEC_R

0_0402_5% N10@

VGA_DDCCLK_C
VGA_DDCDATA_C
VGA_HDMI_SCL
VGA_HDMI_SDA
VGA_LVDS_SCL_C
VGA_LVDS_SDA_C
I2CD_SCL
I2CD_SDA
I2CE_SCL
I2CE_SDA
HDCP_I2CH_SCL
HDCP_I2CH_SDA
EC_SMB_CK2

EC_SMB_DA2
JTAG_TCK
JTAG_TDO
JTAG_TRST_N

TESTMODE

1 2

R117 200_0402_5%@

XTALIN
XTALOUT

XTALIN
XTALOUT

PAD

PM@

R108
124_0402_1%

N10@

1 2

R722

1 2

1 2

R114

1

C264
20P_0402_50V8

2

PM@

HDMI_DETECT_VGA <24>

PAD

T58

VGA_ENVDD <25>
VGA_ENBKL <25>
GPU_VID0 <49>
GPU_VID1 <49>

MEM_VREF <17,21,22>

T59

VGA_HSYNC <26>
VGA_VSYNC <26>
VGA_CRT_R <26>
VGA_CRT_B <26>
VGA_CRT_G <26>

1

PM@

C229

0.1U_0402_16V4Z

2

R73527K_0402_5%

+3VS

HDMI_CEC <24>

for GT21x request

VGA_HDMI_SCL <24>
VGA_HDMI_SDA <24>

EC_SMB_CK2 <5,38,42>
EC_SMB_DA2 <5,38,42>

PAD

T60

PAD

T61

12

PM@

R118
10K_0402_5%

Y1

3

OUT

2

GND

PM@

27MHZ_16PF_X7T027000BG1H-V

PM@

10K_0402_5%

NB9M-GS

NB9P-GE2

I2CE_SCL
I2CE_SDA
I2CD_SCL
I2CD_SDA

VGA_LVDS_SCL_C
VGA_LVDS_SDA_C

HDCP_I2CH_SCL
HDCP_I2CH_SDA

4

GND

1

IN

2

GPIO6 GPIO5

GPU_VID1 GPU_VID0 VGA_CORE

0
1
1

GPU_VID1 GPU_VID0 VGA_CORE

1

0

R101 2.2K_0402_5%PM@

1 2

R102 2.2K_0402_5%PM@

1 2

R103 2.2K_0402_5%PM@

1 2

R104 2.2K_0402_5%PM@

1 2

VGA_DDCCLK_C
VGA_DDCDATA_C

R109

2.2K_0402_5%

PM@

+3VS

PM@

R113

2.2K_0402_5%

1

C266
20P_0402_50V8

2

PM@

L2 MBK1608121YZF_0603PM@

L3 MBK1608121YZF_0603PM@
L4
L5 MBK1608121YZF_0603PM@

R110

2.2K_0402_5%

PM@

+3VS

PM@

R111

2.2K_0402_5%

@

R119

2.2K_0402_5%

1 2
1 2

1 2
1 2

0
1
0

1

1

+3VS

MBK1608121YZF_0603PM@

C244

PM@

12P_0402_50V8J

12

@

R112
10K_0402_5%

0.9V

1.17V

1.09V

1.00V

0.9V

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

1

C245

PM@

12P_0402_50V8J

2

12P_0402_50V8J

P-State

10,12

0
8

P-State

0

8,10,12

CRT OUT

R105 150_0402_1%PM@

1 2

R106 150_0402_1%PM@

1 2

R107 150_0402_1%PM@

1 2

1

1

C246

C247

PM@

PM@

2

2

1

PM@

C261

0.1U_0402_16V4Z

2

U6

8

VCC

7

WP

6

SCL

5

SDA

AT24C16AN-10SU-2.7_SO8PM@

1

1

12P_0402_50V8J

2

A0
A1
A2

GND

VGA_DDCCLK <26>
VGA_DDCDATA <26>

VGA_LVDS_SCL <25>
VGA_LVDS_SDA <25>

1
2
3
4

12

PM@

R120
100K_0402_1%

If External Spread Spectrum not stuff then stuff resistor

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/25 2008/04/

3

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

NB9P PCIE,LVDS,GPIO,CLK

Size D ocument Number Rev

Custom

2

Date: Sheet

KIWB1/B2_LA4601P

Monday, June 30, 2008

of

16

1

0.1

52

CyberForum.ru

5

D D

C C

B B

A A

FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

MEM_VREF<16,21,22>

MEM_VREF

R30
R32
P31
N30

L31
M32
M30

L30

P33
P34
N35
P35
N34

L33

L32

N33
K31
K30
G30
K32
G32
H30
F30
G31
H33
K35
K33
G34
K34
E33
E34
G33

AG30

AH31

AG32

AF31
AF30
AD30
AC32
AE30
AE32
AF33
AF34
AE35
AE33
AE34
AC35
AB32
AN33
AK32

AL33

AM33

AL31

AK30

AJ30

AH30

AM35

AH33
AH35
AH32
AH34

AM34

AL35
AJ33

2

G

5

U5B

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

NB9P-GS_BGA969~D

9M@

+FB_VREF

13

D

Q3

SSM3K7002FU_SC70-3

S

PM@

Part 2 of 6

MEMORY

PM@

1 2

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30

FBA_DQM0

FBA_DQM1

INTERFACE 1

FBA_DQM2

FBA_DQM3

FBA_DQM4

FBA_DQM5

FBA_DQM6

FBA_DQM7

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FB_VREF

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FBA_DEBUG

10mil

R718931_0402_5%

0.01U_0402_16V7K

C267

PM@

V32
W31
U31
Y32
AB35
AB34
W35
W33
W30
T34
T35
AB31
Y30
Y34
W32
AA30
AA32
Y33
U32
Y31
U34
Y35
W34
V30
U35
U30
U33
AB30
AB33
T33
W29

P30
P32
J30
H34
AF32
AF35
AL32
AL34

N32
L35
H31
G35
AD32
AC34
AJ31
AJ35

N31
L34
J32
H35
AE31
AC33
AJ32
AJ34

J27
T32

T31
AC31
AC30
T30

4

FBAA[0..11]

FBBA[2..5]

FBADQM[0..7]
FBADQS[0..7]

FBADQS#[0..7]

FBAD[0..63]

FBAA4
FBARAS#
FBAA5
FBA_BA1
FBBA2
FBBA4
FBBA3
FBA_CMD7
FBA_CMD8
FBAA11
FBACAS#
FBAWE#
FBA_BA0
FBBA5
FBA_CS1
FBA_RST_R
FBAA7

R635 0_0402_5%PM@

FBAA10
FBA_CMD18
FBAA0
FBAA9
FBAA6
FBAA2
FBAA8
FBAA3
FBAA1

FBA_BA2_CMD27
SNN_FBA_CMD28
FBA_CMD29 FBC_CMD29

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

FBADQS#0
FBADQS#1
FBADQS#2
FBADQS#3
FBADQS#4
FBADQS#5
FBADQS#6
FBADQS#7

FBADQS0
FBADQS1
FBADQS2
FBADQS3
FBADQS4
FBADQS5
FBADQS6
FBADQS7

+FB_VREF

FBACLK0
FBACLK0#
FBACLK1
FBACLK1#
AGP_FBA_DEBUG

+1.8VS

12

R133
549_0402_1%

PM@

12

1

R134

1.3K_0402_1%

PM@

2

FBARAS# <21>
FBA_BA1 <21>

FBACAS# <21>
FBAWE# <21>
FBA_BA0 <21>

FBA_CS1 <21>

1 2

12

R639
10K_0402_5%

PM@

R641

FBAA[0..11] <21>

FBBA[2..5] <21>

FBADQM[0..7] <21>

FBADQS[0..7] <21>
FBADQS#[0..7] <21>
FBAD[0..63] <21>

FBA_RST

0_0402_5%PM@

12

FBACLK0 <21>
FBACLK1 <21>

FBACLK1# <21>

FBA_CMD7

FBA_CMD18

FBA_CMD29

FBA_CMD8

10K_0402_5%

R754

1 2

N10@

FBA_RST <21>

R637
10K_0402_5%

PM@

1 2

FBA_BA2

for GT21x request

+1.8VS

12

R131
10K_0402_5%

PM@

R724

N10@

1 2

R721

N9@

1 2

R728

N10@

1 2

R727

N9@

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

FBA_BA2 <21>

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

3

2

U5C

FBCD0
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63

D11

FBC_D0

E11

FBC_D1

F10

FBC_D2

D8

FBC_D3

F8

FBC_D4

F9

FBC_D5

E8

FBC_D6

F12

FBC_D7

B11

FBC_D8

C13

FBC_D9

A11

FBC_D10

B8

FBC_D11

A8

FBC_D12

C8

FBC_D13

C11

FBC_D14

C10

FBC_D15

D12

FBC_D16

E13

FBC_D17

F17

FBC_D18

F15

FBC_D19

F16

FBC_D20

E16

FBC_D21

F14

FBC_D22

F13

FBC_D23

D13

FBC_D24

A13

FBC_D25

B13

FBC_D26

A14

FBC_D27

C16

FBC_D28

A17

FBC_D29

B16

FBC_D30

D16

FBC_D31

D24

FBC_D32

D26

FBC_D33

E25

FBC_D34

F25

FBC_D35

F27

FBC_D36

E28

FBC_D37

F28

FBC_D38

D29

FBC_D39

A25

FBC_D40

B25

FBC_D41

D25

FBC_D42

C26

FBC_D43

C28

FBC_D44

B28

FBC_D45

A28

FBC_D46

A29

FBC_D47

E29

FBC_D48

F29

FBC_D49

D30

FBC_D50

E31

FBC_D51

C33

FBC_D52

D33

FBC_D53

F32

FBC_D54

E32

FBC_D55

B29

FBC_D56

C29

FBC_D57

B31

FBC_D58

C31

FBC_D59

B32

FBC_D60

C32

FBC_D61

B34

FBC_D62

B35

FBC_D63

NB9P-GS_BGA969~D

9M@

for GT21x REMOVE R721,R725

FBA_CKE_H <21>
FBA_CKE_L <21>

for GT21x REMOVE R727,R729

FBACS0#_L <21>
FBACS0#_H <21>

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

Part 3 of 6

MEMORY

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8

FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30

FBC_DQM0

FBC_DQM1

INTERFACE 2

FBC_DQM2

FBC_DQM3

FBC_DQM4

FBC_DQM5

FBC_DQM6

FBC_DQM7

FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7

FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7

FBC_CLK0

FBC_CLK0_N

FBC_CLK1

FBC_CLK1_N

FBC_DEBUG

FBC_CMD7

FBC_CMD18

FBC_CMD29

FBC_CMD8

2

C17
B19
D18
F21
A23
D21
B23
E20
G21
F20
F19
F23
A22
C22
B17
F24
C25
E22
C20
B22
A19
D22
D20
E19
D19
F18
C19
F22
C23
B20
A20

F11
D10
D15
A16
D27
D28
D34
A34

D9
B10
E14
B14
F26
A26
D31
A31

E10
A10
D14
C14
E26
B26
D32
A32

E17
D17
D23
E23
G19

N10@

1 2

N9@

1 2

N10@

1 2

N9@

1 2

FBC_RST_R

R726

R725

R730

R729

FBCA[0..11]

FBCA[2..5]

FBCDQM[0..7]

FBCDQS[0..7]

FBCDQS#[0..7]

FBCD[0..63]

FBCA4
FBCRAS#
FBCA5
FBC_BA1

FBC_A6
FBC_A0

FBC_A9
FBC_CMD7
FBC_CMD8

FBCA11
FBCCAS#
FBCWE#
FBC_BA0

FBC_A1
FBC_CS1

FBCA7

FBCA10
FBC_CMD18
FBCA0
FBCA9
FBCA6
FBCA2
FBCA8
FBCA3
FBCA1

SNN_FBC_CMD28

FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBCDQM7

FBCDQS#0
FBCDQS#1
FBCDQS#2
FBCDQS#3
FBCDQS#4
FBCDQS#5
FBCDQS#6
FBCDQS#7

FBCDQS0
FBCDQS1
FBCDQS2
FBCDQS3
FBCDQS4
FBCDQS5
FBCDQS6
FBCDQS7

FBCCLK0
FBCCLK0#
FBCCLK1
FBCCLK1#
AGP_FBC_DEBUG

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

Title

Size D ocument Number Rev

Date: Sheet

FBCA[0..11] <22>

FBCDQS#[0..7] <22>
FBCD[0..63] <22>

FBCRAS# <22>
FBC_BA1 <22>

FBC_A6 <22>
FBC_A0 <22>
FBC_A9 <22>

FBCCAS# <22>
FBCWE# <22>
FBC_BA0 <22>
FBC_A1 <22>
FBC_CS1 <22>

1 2

R636 0_0402_5%PM@

12

R640
10K_0402_5%

PM@

FBC_BA2_CMD27

Custom

1

FBCA[2..5] <22>

FBCDQM[0..7] <22>
FBCDQS[0..7] <22>

10K_0402_5%

R786

1 2

N10@

FBC_RST

R638
10K_0402_5%

PM@

1 2

FBC_BA2

R642 0_0402_5%PM@

FBCCLK0 <22>
FBCCLK0# <22>
FBCCLK1 <22>
FBCCLK1# <22>FBACLK0# <21>

12

+1.8VS

12

R132
10K_0402_5%

PM@

FBC_CKE_H <22>
FBC_CKE_L <22>

FBCCS0#_L <22>
FBCCS0#_H <22>

Compal Electronics, Inc.

NB9M-GE Memory

KIWB1/B2_LA4601P

17 52Monday, June 30, 2008

1

FBC_RST <22>

FBC_BA2 <22>

0.1

of

CyberForum.ru

5

4

3

2

1

AM11
AM12

AM8

AL8

AM10

AM9

AK10

AL10

AK11

AL11
AP13
AN13

AN8

AP8
AP10
AN10
AR11
AR10
AN11
AP11

AJ11

AE1

AB3

AB2

AB1

AC4
AC1
AC2
AC3

AE3

AE2

AF1

AB7

AD6

AF6

AG6

AK15

AL7

D35

U5D

D7
A7
C7
B7
D6

N4
R4
T4

P5
N2
N3
L3

N1
P4
P1
P2
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6

N5

V4

W4
W3

Y5
W1
W2

Y1

Y2

Y3

U6
W6

Y6
W5
W7

V7

A2

AJ5

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

IFPAB_RSET
HDA_BCLK

HDA_SYNC
HDA_SDI
HDA_SDO
HDA_RST_N

MIOA_CLKIN
MIOA_CLKOUT
MIOA_CLKOUT_N

MIOA_CTL3
MIOA_DE
MIOA_HSYNC
MIOA_VSYNC

MIOA_D0
MIOA_D1
MIOA_D2
MIOA_D3
MIOA_D4
MIOA_D5
MIOA_D6
MIOA_D7
MIOA_D8
MIOA_D9
MIOA_D10
MIOA_D11
MIOA_D12
MIOA_D13
MIOA_D14

MIOA_VREF
MIOB_CLKIN

MIOB_CLKOUT
MIOB_CLKOUT_N

MIOB_CTL3
MIOB_DE
MIOB_HSYNC
MIOB_VSYNC

MIOB_D0
MIOB_D1
MIOB_D2
MIOB_D3
MIOB_D4
MIOB_D5
MIOB_D6
MIOB_D7
MIOB_D8
MIOB_D9
MIOB_D10
MIOB_D11
MIOB_D12
MIOB_D13
MIOB_D14
MIOB_D15/(STRAP0)
MIOB_D16/(STRAP1)
MIOB_D17/(STRAP2)

MIOB_VREF
NC_0

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NB9P-GS_BGA969~D9M@

Part 4 of 6

LVDS

HDA

MULTIUSE IN PU T OUTPUT

NC

IFPC_AUX

IFPC_AUX_N

IFPC_DPL0_TXD2

IFPC_DPL0_TXD2_N

IFPC_DPL1_TXD1

IFPC_DPL1_TXD1_N

IFPC_DPL2_TXD0

IFPC_DPL2_TXD0_N

IFPC_DPL3_TXC

IFPC_DPL3_TXC_N

IFPD_AUX

IFPD_AUX_N

IFPD_DPL0_TXD2

IFPD_DPL0_TXD2_N

IFPD_DPL1_TXD1

IFPD_DPL1_TXD1_N

IFPD_DPL2_TXD0

IFPD_DPL2_TXD0_N

IFPD_DPL3_TXC

IFPD_DPL3_TXC_N

IFPCD_RSET

IFPE_AUX

IFPE_AUX_N

IFPE_DPL0_TXD2

IFPE_DPL0_TXD2_N

IFPE_DPL1_TXD1

IFPE_DPL1_TXD1_N

MXM/DVI/DP

IFPE_DPL2_TXD0

IFPE_DPL2_TXD0_N

IFPE_DPL3_TXC

IFPE_DPL3_TXC_N

IFPF_AUX

IFPF_AUX_N

IFPF_DPL0_TXD2

IFPF_DPL0_TXD2_N

IFPF_DPL1_TXD1

IFPF_DPL1_TXD1_N

IFPF_DPL2_TXD0

IFPF_DPL2_TXD0_N

IFPF_DPL3_TXC

IFPF_DPL3_TXC_N

IFPEF_RSET

ROM_SCLK

ROM_CS_N

BUFRST_N

PGOOD_OUT

STRAP_REF_MIOB

GENERAL

STRAP_REF_3V3

THERMDN

THERMDP

RUF

ROM_SI

ROM_SO

SPDIF

RFU_0
RFU_1
RFU_2
RFU_3
RFU_4
RFU_5
RFU_6
RFU_7
RFU_8

RFU_9
RFU_10
RFU_11
RFU_12
RFU_13
RFU_14
RFU_15
RFU_16
RFU_17

NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18

AP2
AN3

VGA_HDMI_TX2+

AM7

VGA_HDMI_TX2-

AM6

VGA_HDMI_TX1+

AL5

VGA_HDMI_TX1-

AM5

VGA_HDMI_TX0+

AM3

VGA_HDMI_TX0-

AM4

VGA_HDMI_CLK+

AP1

VGA_HDMI_CLK-

AR2
AP4

AN4
AR8
AR7
AP7
AN7
AN5
AP5
AR5
AR4

IFPCD_RSET

AK7
AE4

AD4
AH6
AH5
AH4
AG4
AF4
AF5
AE6
AE5

AF3
AF2

AL2
AL3
AJ3
AJ2
AJ1
AH1
AH2
AH3

IFPEF_RSET

AL1
D4

D3
C4
C3

A5
A4
C5

R141 40.2K_0402_1%PM@

M9

R142 40.2K_0402_1%PM@

N9
B4

B5
AD29

AE29
AG29
AH29
G11
G12
G14
G15
G24
G25
G27
G28
J25
J26
L29
M29
P29
R29

E35
E7
F7
H32
M7
P6
P7
R7
U7
V6

R136 1K_0402_5%

R139 1K_0402_5%@

ROM_SCLK
ROM_SI
ROM_SO

SPDIF_IN

1 2
1 2

PM@

1 2

1 2

PAD

T64

PAD

T65

PAD

T66

PAD

T67

VGA_HDMI_TX2+ <24>
VGA_HDMI_TX2- <24>
VGA_HDMI_TX1+ <24>
VGA_HDMI_TX1- <24>
VGA_HDMI_TX0+ <24>
VGA_HDMI_TX0- <24>
VGA_HDMI_CLK+ <24>
VGA_HDMI_CLK- <24>

ROM_SCLK <20>
ROM_SI <20>
ROM_SO <20>

1 2

VGA_LVDS_ACLK
VGA_LVDS_ACLK#
VGA_LVDS_A0
VGA_LVDS_A0#
VGA_LVDS_A1
VGA_LVDS_A1#
VGA_LVDS_A2
VGA_LVDS_A2#

VGA_LVDS_BCLK
VGA_LVDS_BCLK#
VGA_LVDS_B0
VGA_LVDS_B0#
VGA_LVDS_B1
VGA_LVDS_B1#
VGA_LVDS_B2
VGA_LVDS_B2#

IFPAB_RSET

HDA_SYNC_CODEC_R

HDA_SDIN1_R
HDA_SDOUT_CODEC_R
HDA_RST_CODEC#_R

VGA_LVDS_ACLK<25>
VGA_LVDS_ACLK#<25>
VGA_LVDS_A0<25>
VGA_LVDS_A0#<25>
VGA_LVDS_A1<25>
VGA_LVDS_A1#<25>
VGA_LVDS_A2<25>

D D

IFPAB_RSET

12

PM@

R135
1K_0402_5%

HDA_BITCLK_CODEC<8,28,36>
HDA_SYNC_CODEC<8,28,36>
HDA_SDIN1<28>
HDA_SDOUT_CODEC<8,28,36>
HDA_RST_CODEC#<8,28,36>

HDA_BITCLK_CODEC HDA_BITCLK_CODEC_R
HDA_SYNC_CODEC

HDA_SDIN1
HDA_SDOUT_CODEC
HDA_RST_CODEC#

VGA_LVDS_A2#<25>

VGA_LVDS_BCLK<25>
VGA_LVDS_BCLK#<25>
VGA_LVDS_B0<25>
VGA_LVDS_B0#<25>
VGA_LVDS_B1<25>
VGA_LVDS_B1#<25>
VGA_LVDS_B2<25>
VGA_LVDS_B2#<25>

R782 0_0402_5%N9@

1 2

R783 0_0402_5%N9@

1 2

R137 10_0402_5%N9@

1 2

R784 0_0402_5%N9@

1 2

R785 0_0402_5%N9@

1 2

R138 10K_0402_5%PM@

for GT21x REMOVE R782,R783,R137,R784,R785

C C

R140 10K_0402_5%PM@

1 2

B B

STRAP0<20>
STRAP1<20>
STRAP2<20>

A A

STRAP0
STRAP1
STRAP2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Deciphered Date

Title

Size D ocument Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

NB9M/9P MIO,HDA,LVDS

KIWB1/B2_LA4601P

18 52Monday, June 30, 2008

1

0.1

of

CyberForum.ru

5

+VGA_CORE

+VGA_CORE

D D

C C

11.57A

1

PM@

C284

0.47U_0402_6.3V6K

2

+VGA_CORE

1

PM@

C293

4.7U 6.3V K X 5R 0603

2

+FB_AVDD0

+FB_AVDD1

1

PM@

C271

0.1U_0402_16V4Z

2

1

PM@

C285

0.47U_0402_6.3V6K

2

NEAR BGA

1

PM@

C294

4.7U 6.3V K X 5R 0603

2

1

PM@

C307

0.01U_0402_16V7K

2

1

PM@

C312

0.01U_0402_16V7K

2

1

PM@

C275

0.1U_0402_16V4Z

2

1

PM@

C286

0.47U_0402_6.3V6K

2

1

PM@

C277

0.1U_0402_16V4Z

2

1

PM@

C308

0.1U_0402_16V4Z

2

1

PM@

C315

0.1U_0402_16V4Z

2

1

2

1

PM@

C287

0.47U_0402_6.3V6K

2

L8 MBK1608121YZF_0603PM@

1

PM@

C309

4.7U_0603_6.3V6M

2

L10 MBK1608121YZF_0603PM@

1

PM@

C316

4.7U_0603_6.3V6M

2

NEAR BALL

PM@

C278

0.1U_0402_16V4Z

1

PM@

C288

0.47U_0402_6.3V6K

2

50mA 10MIL

1 2

50mA 10MIL

1 2

1

PM@

C279

0.1U_0402_16V4Z

2

PLACE CLOSE TO BALLS

PM@

C332

0.1U_0402_16V4Z

PM@

C340

0.1U_0402_16V4Z

+1.8VS

1

PM@

4.7U 6.3V K X5R 0603

2

+1.8VS

1

PM@

1U_0603_10V4Z

2

+1.8VS

1

PM@

1U_0603_10V4Z

2

PLACE NEAR BGA

1

PM@

C320

0.022U_0402_16V7K

2

B B

1

PM@

C321

0.022U_0402_16V7K

2

1

PM@

C322

0.1U_0402_16V4Z

2

PLACE BELOW GPU

1

PM@

C328
4700P_0402_25V7K

2

A A

1

PM@

C329
4700P_0402_25V7K

2

1

PM@

C337
4700P_0402_25V7K

2

1

PM@

C330
4700P_0402_25V7K

2

1

PM@

C338
4700P_0402_25V7K

2

1

PM@

C323

0.1U_0402_16V4Z

2

1

PM@

C324

4.7U 6.3V K X 5R 0603

2

FBAVDDQ=1.72A

1

PM@

C331

0.022U_0402_16V7K

2

1

PM@

C339

0.022U_0402_16V7K

2

1

2

1

2

+VGASENSE<49>

C325

C333

C341

+VGASENSE

4

1

PM@

C280

0.1U_0402_16V4Z

2

1

PM@

C289

0.47U_0402_6.3V6K

2

+1.1VS

+1.1VS

1 2

R150 0_0402_5%PM@

W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25

AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AD12
AD14
AD16
AD18
AD22
AD24

AD20

L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
M12
M14
M16
M18
M20
M22
M24
P11
P13
P15
P17
P19
P21
P23
P25
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T12
T14
T16
T18
T20
T22
T24
V11
V13
V15
V17
V19
V21
V23
V25

Y12
Y14
Y16
Y18
Y20
Y22
Y24

U5E

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDD_72
VDD_73
VDD_74
VDD_75
VDD_76
VDD_77
VDD_78
VDD_79
VDD_80
VDD_81
VDD_82
VDD_83
VDD_84
VDD_85
VDD_86
VDD_87
VDD_88
VDD_89
VDD_90
VDD_91
VDD_92
VDD_93
VDD_94
VDD_95
VDD_96
VDD_97
VDD_98
VDD_99
VDD_100
VDD_101
VDD_102
VDD_103
VDD_104
VDD_105
VDD_106
VDD_107
VDD_108
VDD_109
VDD_110

VDD_SENSE

NB9P-GS_BGA969~D9M@

Part 5 of 6

FBAC_DLLAVDD

FBAC_PLLAVDD

FB_CAL_PD_VDDQ

MIOA_VDDQ_0
MIOA_VDDQ_1
MIOA_VDDQ_2
MIOA_VDDQ_3

MIOA_CAL_PD_VDDQ

MIOB_VDDQ_0
MIOB_VDDQ_1
MIOB_VDDQ_2
MIOB_VDDQ_3

MIOB_CAL_PD_VDDQ

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8

PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDDQ_15
PEX_IOVDDQ_16
PEX_IOVDDQ_17
PEX_IOVDDQ_18
PEX_IOVDDQ_19

POWER

PEX_IOVDDQ_20
PEX_IOVDDQ_21
PEX_IOVDDQ_22
PEX_IOVDDQ_23
PEX_IOVDDQ_24

IFPAB_PLLVDD
IFPCD_PLLVDD
IFPEF_PLLVDD

VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4

DACA_VDD
DACB_VDD

DACC_VDD

FB_DLLAVDD
FB_PLLAVDD

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4

PEX_PLLVDD

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8

FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37

IFPA_IOVDD
IFPB_IOVDD
IFPC_IOVDD
IFPD_IOVDD
IFPE_IOVDD

IFPF_IOVDD

PLLVDD

VID_PLLVDD

SP_PLLVDD

3

1

PM@

J9
J10
J11
J12
J13

+DACA_VDD +DACB_VDD

AJ12

+DACB_VDD

AC6

+DACC_VDD

AG7

+FB_AVDD0

AG27
AF27

+FB_AVDD1

J19
J18

R145 44.2_0402_1%PM@

1 2

K27

R146 10K_0402_5%PM@

1 2

P9
R9
T9
U9
U5
AA9
AB9
W9
Y9
AA7

AK16
AK17
AK21
AK24
AK27

AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24
AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16

+PEX_PLLVDD

AG14
B18

E21
G8
G9
G17
G18
G22
H29
J14
J15
J16
J17
J20
J21
J22
J23
J24
J29
N27
P27
R27
T27
U27
U29
V27
V29
V34
W27
Y27
AA27
AA29
AA31
AB27
AB29
AC27
AD27
AE27
AJ28

AG9
AG10
AJ8
AK8
AE7
AD7
AK9
AJ9
AJ6

AE9
AD9
AF9

+1.8VS

+IFPA_IOVDD
+IFPB_IOVDD
+IFPC_IOVDD
+IFPD_IOVDD
+IFPE_IOVDD
+IFPF_IOVDD
+IFPAB_PLLVDD
+IFPCD_PLLVDD
+IFPEF_PLLVDD

12~16mil

C272

0.1U_0402_16V4Z

2

1

PM@

C281
470P_0402_50V7K

2

1

PM@

C290

0.1U_0402_16V4Z

2

1

PM@

C295

0.1U_0402_16V4Z

2

+PEX_PLLVDD

+IFPAB_PLLVDD

+IFPCD_PLLVDD

+IFPA_IOVDD

+IFPB_IOVDD

+IFPC_IOVDD

+IFPD_IOVDD

1

2

NEAR BALL

1

2

NEAR BALL

+1.8VS

1

2

NEAR BALL

1

PM@

C296

0.1U_0402_16V4Z

2

1

2

1

PM@

C344

0.1U_0402_16V4Z

2

PM@

C273

0.1U_0402_16V4Z

PM@

C282
4700P_0402_16V7K

PM@

C291

0.1U_0402_16V4Z

PM@

C303

0.01U_0402_16V7K

1

2

1

2

2

1

1

2

2

1

1

2

+3VS

+3VS

2

1

1

PM@

C297
1U_0402_6.3V4Z

2

NEAR BALL

PM@

C310
4700P_0402_25V7K

PM@

C313
4700P_0402_25V7K

NEAR BALL

4700P_0402_25V7K
C317

PM@

470P_0402_50V7K

PM@

C326
4700P_0402_25V7K

NEAR BALL

4700P_0402_25V7K

PM@

C334

C342

PM@

4700P_0402_25V7K

1

PM@

C345

0.1U_0402_16V4Z

2

2

PM@

C274

4.7U_0603_6.3V6M

1

NEAR BGA

1 2

L6 MBK1608121YZF_0603PM@

2

PM@

C283

4.7U_0603_6.3V6M

1

NEAR BGA

PM@

C292

4.7U_0603_6.3V6M

NEAR BGA

1

PM@

C304

0.1U_0402_16V4Z

2

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

C318

PM@

PM@

C327
470P_0402_50V7K

2

470P_0402_50V7K
C335

PM@

1

1

PM@

C343
470P_0402_50V7K

2

1

PM@

C346
1U_0402_6.3V6K

2

110mA

110mA

1

PM@

C298

0.47U_0402_6.3V6K

2

1

PM@

C305
1U_0402_6.3V4Z

2

NEAR BGA

1

PM@

C311

2

1

PM@

C314

2

2

C319

PM@

1

2

1

NEAR BGA

1

PM@

C347
1U_0402_6.3V6K

2

2

130mA

1

PM@

C299

0.47U_0402_6.3V6K

2

L9 MBK1608121YZF_0603N9@

L41 MBK1608121YZF_0603N10@

L11 MBK1608121YZF_0603N9@

L42 MBK1608121YZF_0603N10@

L40

L12

4.7U_0603_6.3V6M
C336

PM@

L13

+3VS

To support both 1.1V (for G9X) and 1.05V (for GT21X)

1 2

L7 MBK1608121YZF_0603PM@

1

PM@

C306
10U_0805_10V4Z

2

12MIL

12

12

12MIL

12

12

12

MBK1608121YZF_0603N10@

MBK1608121YZF_0603

12

N9@

12MIL

MBK1608121YZF_0603

12

12MIL

PM@

L14 MBK1608121YZF_0603PM@

1

PM@

C348
1U_0402_6.3V6K

2

1

PM@

C300

4.7U 6.3V K X5R 0603

2

NEAR BGANEAR BALL

200mA

200mA

200mA

12

NEAR BALL

1

+DACC_VDD

+1.1VS

PM@

R144
10K_0402_5%

1 2

+1.1VS

1

PM@

C302
10U_0805_10V4Z

2

PEX_IOVDDQ=1.6A
PEX_IOVDD=500mA

PM@

R143

10K_0402_5%

1 2

1

2

PM@

C301
10U_0805_10V4Z

PEX_PLLVDD=100mA

180mA

IFPAB_PLLVDD: To support both

1.8V(for G9X) and 1.05V(for GT21X)

+1.8VS

+1.1VS

IFPC_PLLVDD To support both

+1.8VS

1.8V(for G9X) and 1.05V(for GT21X)

+1.1VS

+3VS

IFPA/B_IOVDD: To support both

1.8V(for G9X) and 3.3V(for GT21X)

+1.8VS

+1.1VS

+1.1VS

PLLVDD=65mA
SP_PLLVDD=25mA
VID_PLLVDD=50mA

+IFPE_IOVDD
+IFPF_IOVDD

+IFPEF_PLLVDD

R147 10K_0402_5%PM@

1 2

R148 10K_0402_5%PM@

1 2

R149 10K_0402_5%PM@

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH OUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date: Sheet

NB9P-GE Power

KIWB1/B2_LA4601P

1

of

19 52Monday, June 30, 2008

0.1

CyberForum.ru

5

U5F

B3

GND_0

B6

GND_1

B9

GND_2

B12

GND_3

B15

GND_4

B21

GND_5

B24

GND_6

B27

GND_7

B30

GND_8

D D

C C

B B

A A

B33

GND_9

C2

GND_10

C34

GND_11

E6

GND_12

E9

GND_13

E12

GND_14

E15

GND_15

E18

GND_16

E24

GND_17

E27

GND_18

E30

GND_19

F2

GND_20

F5

GND_21

F31

GND_22

F34

GND_23

J2

GND_24

J5

GND_25

J31

GND_26

J34

GND_27

L9

GND_28

M2

GND_29

M5

GND_30

M11

GND_31

M13

GND_32

M15

GND_33

M17

GND_34

M19

GND_35

M21

GND_36

M23

GND_37

M25

GND_38

M31

GND_39

M34

GND_40

N11

GND_41

N12

GND_42

N13

GND_43

N14

GND_44

N15

GND_45

N16

GND_46

N17

GND_47

N18

GND_48

N19

GND_49

N20

GND_50

N21

GND_51

N22

GND_52

N23

GND_53

N24

GND_54

N25

GND_55

P12

GND_56

P14

GND_57

P16

GND_58

P18

GND_59

P20

GND_60

P22

GND_61

P24

GND_62

R2

GND_63

R5

GND_64

R31

GND_65

R34

GND_66

T11

GND_67

T13

GND_68

T15

GND_69

T17

GND_70

T19

GND_71

T21

GND_72

T23

GND_73

T25

GND_74

U11

GND_75

U12

GND_76

U13

GND_77

U14

GND_78

U15

GND_79

U16

GND_80

U17

GND_81

U18

GND_82

U19

GND_83

U20

GND_84

U21

GND_85

U22

GND_86

U23

GND_87

U24

GND_88

U25

GND_89

V2

GND_90

V5

GND_91

V9

GND_92

V12

GND_93

V14

GND_94

V16

GND_95

V18

GND_96

V20

GND_97

V22

GND_98

V24

GND_99

5

Part 6 of 6

GND

RFU_GND_0
RFU_GND_1

GND_SENSE

FB_CAL_PU_GND

FB_CAL_TERM_GND

MIOA_CAL_PU_GND

NB9P-GS_BGA969~D9M@

MIOB_CAL_PU_GND

GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190

V31
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25
AA2
AA5
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA34
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AC9
AD2
AD5
AD11
AD13
AD15
AD17
AD21
AD23
AD25
AD31
AD34
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AG2
AG5
AG31
AG34
AK2
AK5
AK31
AK34
AL6
AL9
AL12
AL15
AL18
AL21
AL24
AL27
AL30
AN2
AN34
AP3
AP6
AP9
AP12
AP15
AP18
AP21
AP24
AP27
AP30
AP33
AK14
K9

R163 0_0402_5%PM@

AD19

R164 33.2_0402_1%PM@

L27

R165 40.2_0402_1%PM@

M27
T5

AA6

Place Components Close to BGA

U5

NB9P-GE2

9P@

1 2
1 2

1 2

4

STRAP2<18>
STRAP1<18>
STRAP0<18>
ROM_SCLK<18>

ROM_SI<18>

ROM_SO<18>

STRAP2
STRAP1
STRAP0
ROM_SCLK
ROM_SI
ROM_SO

3

+3VS

12

X76@

R151
10K_0402_1%

12

X76@

R157
10K_0402_5%

12

@

R152
10K_0402_5%

12

PM@

R158
10K_0402_1%

12

PM@

R153

45.3K_0402_1%~D

12

@

R159
10K_0402_5%

12

@

R154
10K_0402_5%

12

PM@

R160
15K_0402_1%

2

12

X76@

R155
2K_0402_5%

12

X76@

R161
20K_0402_1%

12

PM@

R156

4.99K_0402_1%

12

@

R162
2K_0402_5%

1

GB1 Family GPU Strap Qptions

STRAP0STRAP1

PU 45K

PU 45K

PU 45K

PU 45K

PU 45K

STRAP0STRAP1

PU 45K

PU 45K

PU 45K

PU 45K

PU 45K

1

0.1

of

20

52

NB9M-GS

128bit

NB9P-GE2

128bit

Component

GDDR3 VRAM
(16M*32)

GDDR3 VRAM
(32M*32)

Memory/PKG

GDDR3

FB Memory

Samsung

16Mx32

32Mx32

Hynix

16Mx32

32Mx32

Qimonda

16Mx32

32Mx32

FB Memory

Samsung

16Mx32

32Mx32 PD 10K

Hynix

16Mx32

32Mx32

Qimonda

16Mx32

32Mx32

Manufacturer Compal PN

Hynix
Qimonda
Samsung
Hynix
Qimonda
Samsung

FBCAL_PU_GND FBCAL_PD_VDDQ FBCAL_TERM_GND

33.2ohm 40.2ohm44.2ohm

ROM_SO

PU 5K

PU 5K

PU 5K

PU 5K

PU 5K

ROM_SCLK

PD 15K

PD 15K

PD 15K

PD 15K

PD 20K

PD 45K

PD 15K

PD 35K

PD 10K

STRAP2GPU ROM_SI

PU 10K

PU 10K

PU 10K

PU 10K

PU 10KPD 15K

PD 10K

PD 10K

PD 10K

PD 10K

PD 10K

PU 5K PD 15K PU 10K PD 10K PU 45KPD 30K

ROM_SO

PU 5K

PU 5K

PU 5K

PU 5K

PU 5K

ROM_SCLK

PD 15K

PD 15K

PD 15K

PD 15K

PD 15K

PD 20K

PD 45K

PD 15K

PD 35K

PD 10K

STRAP2GPU ROM_SI

PU 5K

PU 5K

PU 5K

PU 5K

PU 5K

PD 10K

PD 10K

PD 10K

PD 10K

PU 5K PD 15K PD 30K PU 5K PD 10K PU 45K

Compal X76 PN

XX
X
X
X

X
X

X
SA000024N20
SA00002R600

GDDR3 BY N10

To update for NV PUN-03304-001_V06 (2008/5/20)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/25 2008/04/

3

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

NB9P-GE GND & STRAP

Size D ocument Number Rev

Custom
Date: Sheet

2

Monday, June 30, 2008

KIWB1/B2_LA4601P

CyberForum.ru

5

FBAA[0..11]<17>

FBBA[2..5]<17>
FBADQM[0..7]<17>
FBADQS[0..7]<17>

FBADQS#[0..7]<17>

FBAD[0..63]<17>

D D

C C

Place close to Memories so as to
Minimize the stub length

FBAA[0..11]

FBBA[2..5]
FBADQM[0..7]
FBADQS[0..7]
FBADQS#[0..7]

FBAD[0..63]

FBA_BA0<17>
FBA_BA1<17>

FBACLK0<17>

FBACLK0#<17>

FBACLK1<17>

FBACLK1#<17>

FBACLK0

12

PM@

R643
475_0402_1%

FBACLK0#

FBACLK1

12

PM@

R644
475_0402_1%

FBACLK1#

FBA_CS1<17>
FBARAS#<17>

FBACAS#<17>
FBAWE#<17>

FBACS0#_L<17>
FBA_CKE_L<17>

R645

1 2

FBA_RST<17> FBA_RST<17>
FBA_BA2<17>

V4:Scan Enable must be to groud

4

B12

D12

G11

L11

P12

U8

VSSQB1VSSQB4VSSQB9VSSQ

VSSQD1VSSQD4VSSQD9VSSQ

VSSQG2VSSQ

VSSA3VSS

A10

VSSG1VSS

G12

VSSQL2VSSQ

VSSL1VSS

FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBA_BA0
FBA_BA1

FBADQM3
FBADQM1
FBADQM0
FBADQM2

FBADQS3
FBADQS1
FBADQS0
FBADQS2

+VREFA0
+VREFA1

FBA_CS1
FBARAS#

FBACAS#
FBAWE#
FBACS0#_L

FBA_CKE_L
FBACLK0
FBACLK0#

FBADQS#3
FBADQS#1
FBADQS#0
FBADQS#2

K4

A0

H2

A1

K3

A2

M4

A3

K9

A4

H11

A5

K10

A6

L9

A7

K11

A8/AP

M9

A9

K2

A10

L4

A11

G4

BA0

G9

BA1

E3

DM0

E10

DM1

N10

DM2

N3

DM3

D2

WDQS0

D11

WDQS1

P11

WDQS2

P2

WDQS3

H1

VREF

H12

VREF

J2

RFU1

J3

RFU2

H3

RAS#

F4

CAS#

H9

WE#

F9

CS#

H4

CKE

J11

CK

J10

CK#

A4

243_0402_1%PM@

+1.8VS +1.8VS

FBA_RST
FBA_BA2

ZQ

A9

MF

D3

RDQS0

D10

RDQS1

P10

RDQS2

P3

RDQS3

A2

VDD

A11

VDD

F1

VDD

F12

VDD

M1

VDD

M12

VDD

V2

VDD

V11

VDD

V4

SEN

V9

RESET

H10

BA2

J1

VSSA

J12

VSSA

T12

VSSQP1VSSQP4VSSQP9VSSQ

VSSQT1VSSQT4VSSQT9VSSQ

B2

DQ0

B3

DQ1

C2

DQ2

C3

DQ3

E2

DQ4

F3

DQ5

F2

DQ6

G3

DQ7

B11

DQ8

B10

DQ9

C11

DQ10

C10

DQ11

E11

DQ12

F10

DQ13

F11

DQ14

G10

DQ15

M11

DQ16

L10

DQ17

N11

DQ18

M10

DQ19

R11

DQ20

R10

DQ21

T11

DQ22

T10

DQ23

M2

DQ24

L3

DQ25

N2

DQ26

M3

DQ27

R2

DQ28

R3

DQ29

T2

DQ30

T3

DQ31

A1

VDDQ

A12

VDDQ

C1

VDDQ

C4

VDDQ

C9

VDDQ

C12

VDDQ

E1

VDDQ

E4

VDDQ

E9

VDDQ

E12

VDDQ

J4

VDDQ

J9

VDDQ

N1

VDDQ

N4

VDDQ

N9

VDDQ

N12

VDDQ

R1

VDDQ

R4

VDDQ

R9

VDDQ

R12

VDDQ

V1

VDDQ

V12

VDDQ

K1

VDDA

K12

VDDA

VSSV3VSS

K4J52324QE-BC14_FBGA136~D

X76@

L12

V10

FBAD25
FBAD27
FBAD30
FBAD24
FBAD29
FBAD26
FBAD31
FBAD28
FBAD10
FBAD12
FBAD11
FBAD15
FBAD9
FBAD13
FBAD8
FBAD14
FBAD1
FBAD5
FBAD2
FBAD4
FBAD0
FBAD3
FBAD7
FBAD6
FBAD19
FBAD17
FBAD18
FBAD16
FBAD20
FBAD21
FBAD23
FBAD22

+1.8VS

3

2

BGA 84 ADR/CMND MAPPING

DATA Bus

0..31

Address

CMD0
CMD1

3

CMD2

CMD4
CMD5

1 6

CMD6
CMD7

CS1* CS1*
CMD8
CMD9A0A11

0

CMD10
CMD11
CMD12

2

CMD13
CMD14
CMD15
CMD16
CMD17
CMD18

FOR N10

CMD19
CMD20
CMD21
CMD22
CMD23
CMD24
CMD25
CMD26
CMD27
CMD28

RFU1

CMD29
CMD30

32..63
A4
RAS* BA2
A5

BA0CMD3

BA1

A6

A9

CKE

CAS*

CS0*

A11
CS*

CAS*

CKE*

WE*

BA1

BA0

A1
A12

A12
RST/ODT

RST/ODT

A7

A7
A10

A10
CKE

WE#
A0A0
A9

A9

A6

A6
A2
A8

A8

A3

A1

A1

A13

A13

RAS#

BA2
RFU0

RFU0
RFU1

CS0*

RFU2

RFU2

MIRROR

FBA_CS1<17>

FBA_BA2<17>
FBACS0#_H<17>
FBA_CKE_H<17>

R646

1 2

V4:Scan Enable must be to groud

FBBA4
FBBA5
FBAA6
FBAA9
FBAA0
FBAA1
FBBA2
FBAA11
FBAA10
FBBA3
FBAA8
FBAA7
FBA_BA1
FBA_BA0

FBADQM5
FBADQM6
FBADQM7
FBADQM4

FBADQS5
FBADQS6
FBADQS7
FBADQS4

+VREFA2
+VREFA3

FBA_CS1
FBA_BA2

FBACS0#_H
FBA_CKE_H
FBACAS#

FBAWE#
FBACLK1
FBACLK1#

243_0402_1%PM@

FBADQS#5
FBADQS#6
FBADQS#7
FBADQS#4

FBA_RST
FBARAS#

1

B12

D12

G11

L11

P12

U9

VSSQB1VSSQB4VSSQB9VSSQ

VSSQD1VSSQD4VSSQD9VSSQ

VSSQG2VSSQ

VSSA3VSS

A10

VSSG1VSS

G12

VSSQL2VSSQ

VSSL1VSS

K4

A0

H2

A1

K3

A2

M4

A3

K9

A4

H11

A5

K10

A6

L9

A7

K11

A8/AP

M9

A9

K2

A10

L4

A11

G4

BA0

G9

BA1

E3

DM0

E10

DM1

N10

DM2

N3

DM3

D2

WDQS0

D11

WDQS1

P11

WDQS2

P2

WDQS3

H1

VREF

H12

VREF

J2

RFU1

J3

RFU2

H3

RAS#

F4

CAS#

H9

WE#

F9

CS#

H4

CKE

J11

CK

J10

CK#

A4

ZQ

A9

MF

D3

RDQS0

D10

RDQS1

P10

RDQS2

P3

RDQS3

A2

VDD

A11

VDD

F1

VDD

F12

VDD

M1

VDD

M12

VDD

V2

VDD

V11

VDD

V4

SEN

V9

RESET

H10

BA2

J1

VSSA

J12

VSSA

T12

VSSQP1VSSQP4VSSQP9VSSQ

VSSQT1VSSQT4VSSQT9VSSQ

B2

DQ0

B3

DQ1

C2

DQ2

C3

DQ3

E2

DQ4

F3

DQ5

F2

DQ6

G3

DQ7

B11

DQ8

B10

DQ9

C11

DQ10

C10

DQ11

E11

DQ12

F10

DQ13

F11

DQ14

G10

DQ15

M11

DQ16

L10

DQ17

N11

DQ18

M10

DQ19

R11

DQ20

R10

DQ21

T11

DQ22

T10

DQ23

M2

DQ24

L3

DQ25

N2

DQ26

M3

DQ27

R2

DQ28

R3

DQ29

T2

DQ30

T3

DQ31

A1

VDDQ

A12

VDDQ

C1

VDDQ

C4

VDDQ

C9

VDDQ

C12

VDDQ

E1

VDDQ

E4

VDDQ

E9

VDDQ

E12

VDDQ

J4

VDDQ

J9

VDDQ

N1

VDDQ

N4

VDDQ

N9

VDDQ

N12

VDDQ

R1

VDDQ

R4

VDDQ

R9

VDDQ

R12

VDDQ

V1

VDDQ

V12

VDDQ

K1

VDDA

K12

VDDA

VSSV3VSS

K4J52324QE-BC14_FBGA136~D

X76@

L12

V10

FBAD45
FBAD47
FBAD43
FBAD46
FBAD44
FBAD42
FBAD40
FBAD41
FBAD51
FBAD48
FBAD55
FBAD52
FBAD53
FBAD50
FBAD54
FBAD49
FBAD62
FBAD60
FBAD63
FBAD58
FBAD56
FBAD57
FBAD61
FBAD59
FBAD39
FBAD38
FBAD37
FBAD35
FBAD36
FBAD34
FBAD32
FBAD33

+1.8VS

5

7

4

+1.8VS

0.01U_0402_16V7K

1

B B

A A

C765

2

1000P_0402_50V7K

+1.8VS

0.01U_0402_16V7K

1

C773

2

1000P_0402_50V7K

+1.8VS

1

C783

+

220U_D2_4VM_R15

PM@

2

1

C766

2

0.01U_0402_16V7K

1

C774

2

0.01U_0402_16V7K

0.1U_0402_16V4Z

1

C767

2

0.1U_0402_16V4Z

1

C775

2

5

1

C768

2

1U_0402_6.3V4Z

1

C776

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

1

C769

2

0.1U_0402_16V4Z

1

C777

2

1

C770

2

0.1U_0402_16V4Z

1

C778

2

0.1U_0402_16V4Z

1

2

1

2

C771

C779

1

C772

2

0.01U_0402_16V7K

1

C780

0.01U_0402_16V7K

2

+1.8VS +1.8VS

12

R647
549_0402_1%~D

1.27V~0.9V

+VREFA1
+VREFA0

R651

931_0402_5%

PM@

MEM_VREF<16,17,22> MEM_VREF<16,17,22>

4

MEM_VREF MEM_VREF

2

G

10mil

1

C781

0.01U_0402_16V7K

2

PM@

1 2

13

D

Q60

SSM3K7002FU_SC70-3

S

PM@

PM@

12

R649

1.3K_0402_1%

PM@

Security Classification

Issued Date

THIS SHEET OF E NGIN EERIN G DRA WING I S THE P ROPRI ETAR Y PROP ERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECR ET I NFO RMA TION . T HIS SHE ET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUT HORIZ ED B Y COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

12

R648
549_0402_1%~D

1.27V~0.9V

+VREFA3
+VREFA2

R652

931_0402_5%

PM@

2

G

2

10mil

1

C782

0.01U_0402_16V7K

2

PM@

1 2

13

D

Q61

SSM3K7002FU_SC70-3

S

PM@

Title

Size Document Number R ev

Custom

Date: Sheet

PM@

12

R650

1.3K_0402_1%

PM@

Compal Electronics, Inc.

VRAM DDRA

of

1

21 52Monday, June 30, 2008

0.1

CyberForum.ru

5

FBCA[0..11]<17>

FBCA[2..5]<17>
FBCDQM[0..7]<17>
FBCDQS[0..7]<17>

FBCDQS#[0..7]<17>

FBCD[0..63]<17>

D D

C C

Place close to Memories so as to
Minimize the stub length

FBCA[0..11]

FBCA[2..5]
FBCDQM[0..7]
FBCDQS[0..7]
FBCDQS#[0..7]

FBCD[0..63]

FBC_BA0<17>
FBC_BA1<17>

FBCCLK0<17>

FBCCLK0#<17>

FBCCLK1<17>

FBCCLK1#<17>

FBCCLK0

12

PM@

R653
475_0402_1%

FBCCLK0#

FBCCLK1

12

PM@

R654
475_0402_1%

FBCCLK1#

FBC_CS1<17>
FBCRAS#<17>

FBCCAS#<17>
FBCWE#<17>

FBCCS0#_L<17>

FBC_CKE_L<17>

R655

1 2

FBC_RST<17> FBC_RST<17>
FBC_BA2<17>

V4:Scan Enable must be to groud

4

B12

D12

G11

L11

P12

U10

VSSQB1VSSQB4VSSQB9VSSQ

VSSQD1VSSQD4VSSQD9VSSQ

VSSQG2VSSQ

VSSA3VSS

A10

VSSG1VSS

G12

VSSQL2VSSQ

VSSL1VSS

FBCA0
FBCA1
FBCA2
FBCA3
FBCA4
FBCA5
FBCA6
FBCA7
FBCA8
FBCA9
FBCA10
FBCA11
FBC_BA0
FBC_BA1

FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM0

FBCDQS1
FBCDQS2
FBCDQS3
FBCDQS0

+VREFA0
+VREFA1

FBC_CS1
FBCRAS#

FBCCAS#
FBCWE#
FBCCS0#_L

FCB_CKE_L
FBCCLK0
FBCCLK0#

FBCDQS#1
FBCDQS#2
FBCDQS#3
FBCDQS#0

K4

A0

H2

A1

K3

A2

M4

A3

K9

A4

H11

A5

K10

A6

L9

A7

K11

A8/AP

M9

A9

K2

A10

L4

A11

G4

BA0

G9

BA1

E3

DM0

E10

DM1

N10

DM2

N3

DM3

D2

WDQS0

D11

WDQS1

P11

WDQS2

P2

WDQS3

H1

VREF

H12

VREF

J2

RFU1

J3

RFU2

H3

RAS#

F4

CAS#

H9

WE#

F9

CS#

H4

CKE

J11

CK

J10

CK#

A4

243_0402_1%PM@

+1.8VS +1.8VS

FBC_RST
FBC_BA2

ZQ

A9

MF

D3

RDQS0

D10

RDQS1

P10

RDQS2

P3

RDQS3

A2

VDD

A11

VDD

F1

VDD

F12

VDD

M1

VDD

M12

VDD

V2

VDD

V11

VDD

V4

SEN

V9

RESET

H10

BA2

J1

VSSA

J12

VSSA

T12

VSSQP1VSSQP4VSSQP9VSSQ

VSSQT1VSSQT4VSSQT9VSSQ

B2

DQ0

B3

DQ1

C2

DQ2

C3

DQ3

E2

DQ4

F3

DQ5

F2

DQ6

G3

DQ7

B11

DQ8

B10

DQ9

C11

DQ10

C10

DQ11

E11

DQ12

F10

DQ13

F11

DQ14

G10

DQ15

M11

DQ16

L10

DQ17

N11

DQ18

M10

DQ19

R11

DQ20

R10

DQ21

T11

DQ22

T10

DQ23

M2

DQ24

L3

DQ25

N2

DQ26

M3

DQ27

R2

DQ28

R3

DQ29

T2

DQ30

T3

DQ31

A1

VDDQ

A12

VDDQ

C1

VDDQ

C4

VDDQ

C9

VDDQ

C12

VDDQ

E1

VDDQ

E4

VDDQ

E9

VDDQ

E12

VDDQ

J4

VDDQ

J9

VDDQ

N1

VDDQ

N4

VDDQ

N9

VDDQ

N12

VDDQ

R1

VDDQ

R4

VDDQ

R9

VDDQ

R12

VDDQ

V1

VDDQ

V12

VDDQ

K1

VDDA

K12

VDDA

VSSV3VSS

K4J52324QE-BC14_FBGA136~D

X76@

L12

V10

FBCD14
FBCD9
FBCD13
FBCD10
FBCD11
FBCD15
FBCD12
FBCD8
FBCD19
FBCD17
FBCD21
FBCD16
FBCD20
FBCD22
FBCD18
FBCD23
FBCD27
FBCD24
FBCD31
FBCD25
FBCD29
FBCD26
FBCD28
FBCD30
FBCD4
FBCD1
FBCD6
FBCD0
FBCD3
FBCD2
FBCD5
FBCD7

+1.8VS

3

2

BGA 84 ADR/CMND MAPPING

DATA Bus

0..31

Address

CMD0

1

CMD1
CMD2

CMD4

2

CMD5
CMD6
CMD7

CS1* CS1*

CMD8

3

CMD9A0A11
CMD10
CMD11
CMD12

0

CMD13
CMD14
CMD15
CMD16
CMD17
CMD18

FOR N10

CMD19
CMD20
CMD21
CMD22
CMD23
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29

RFU1

CMD30

32..63
A4
RAS* BA2
A5

BA0CMD3

BA1

A6

A9

CKE

CAS*

CS0*

A11

CAS*

CS*

CKE*

WE*

BA1

BA0

A1

A12

A12
RST/ODT

RST/ODT

A7

A7

A10

A10
CKE

WE#

A0A0
A9

A9

A6

A6
A2

A8

A8
A3

A1

A1
A13

A13

RAS#

BA2
RFU0

RFU0
RFU1

CS0*

RFU2

RFU2

MIRROR

FBC_A0<17>
FBC_A1<17>

FBC_A6<17>

FBC_A9<17>

FBC_CS1<17>

FBC_BA2<17>
FBCCS0#_H<17>
FBC_CKE_H<17>

R656

1 2

V4:Scan Enable must be to groud

FBC_A0
FBC_A1
FBCA6
FBCA9
FBCA0
FBCA1
FBC_A6
FBCA11
FBCA10
FBC_A9
FBCA8
FBCA7
FBC_BA1
FBC_BA0

FBCDQM4
FBCDQM6
FBCDQM7
FBCDQM5

FBCDQS4
FBCDQS6
FBCDQS7
FBCDQS5

+VREFA2
+VREFA3

FBC_CS1
FBC_BA2

FBCCS0#_H
FBC_CKE_H
FBCCAS#

FBCWE#
FBCCLK1
FBCCLK1#

243_0402_1%PM@

FBCDQS#4
FBCDQS#6
FBCDQS#7
FBCDQS#5

FBC_RST
FBCRAS#

1

B12

D12

G11

L11

P12

U11

VSSQB1VSSQB4VSSQB9VSSQ

VSSQD1VSSQD4VSSQD9VSSQ

VSSQG2VSSQ

VSSA3VSS

A10

VSSG1VSS

G12

VSSQL2VSSQ

VSSL1VSS

K4

A0

H2

A1

K3

A2

M4

A3

K9

A4

H11

A5

K10

A6

L9

A7

K11

A8/AP

M9

A9

K2

A10

L4

A11

G4

BA0

G9

BA1

E3

DM0

E10

DM1

N10

DM2

N3

DM3

D2

WDQS0

D11

WDQS1

P11

WDQS2

P2

WDQS3

H1

VREF

H12

VREF

J2

RFU1

J3

RFU2

H3

RAS#

F4

CAS#

H9

WE#

F9

CS#

H4

CKE

J11

CK

J10

CK#

A4

ZQ

A9

MF

D3

RDQS0

D10

RDQS1

P10

RDQS2

P3

RDQS3

A2

VDD

A11

VDD

F1

VDD

F12

VDD

M1

VDD

M12

VDD

V2

VDD

V11

VDD

V4

SEN

V9

RESET

H10

BA2

J1

VSSA

J12

VSSA

T12

VSSQP1VSSQP4VSSQP9VSSQ

VSSQT1VSSQT4VSSQT9VSSQ

B2

DQ0

B3

DQ1

C2

DQ2

C3

DQ3

E2

DQ4

F3

DQ5

F2

DQ6

G3

DQ7

B11

DQ8

B10

DQ9

C11

DQ10

C10

DQ11

E11

DQ12

F10

DQ13

F11

DQ14

G10

DQ15

M11

DQ16

L10

DQ17

N11

DQ18

M10

DQ19

R11

DQ20

R10

DQ21

T11

DQ22

T10

DQ23

M2

DQ24

L3

DQ25

N2

DQ26

M3

DQ27

R2

DQ28

R3

DQ29

T2

DQ30

T3

DQ31

A1

VDDQ

A12

VDDQ

C1

VDDQ

C4

VDDQ

C9

VDDQ

C12

VDDQ

E1

VDDQ

E4

VDDQ

E9

VDDQ

E12

VDDQ

J4

VDDQ

J9

VDDQ

N1

VDDQ

N4

VDDQ

N9

VDDQ

N12

VDDQ

R1

VDDQ

R4

VDDQ

R9

VDDQ

R12

VDDQ

V1

VDDQ

V12

VDDQ

K1

VDDA

K12

VDDA

VSSV3VSS

K4J52324QE-BC14_FBGA136~D

X76@

L12

V10

FBCD35
FBCD36
FBCD33
FBCD38
FBCD32
FBCD39
FBCD34
FBCD37
FBCD51
FBCD53
FBCD54
FBCD52
FBCD55
FBCD49
FBCD48
FBCD50
FBCD61
FBCD58
FBCD62
FBCD59
FBCD60
FBCD57
FBCD63
FBCD56
FBCD40
FBCD44
FBCD41
FBCD45
FBCD43
FBCD46
FBCD42
FBCD47

+1.8VS

4

6

7

5

+1.8VS

0.01U_0402_16V7K

1

B B

A A

C784

2

1000P_0402_50V7K

+1.8VS

0.01U_0402_16V7K

1

C792

2

1000P_0402_50V7K

+1.8VS

1

C802

+

220U_D2_4VM_R15

PM@

2

1

C785

2

0.01U_0402_16V7K

1

C793

2

0.01U_0402_16V7K

0.1U_0402_16V4Z

1

C786

2

0.1U_0402_16V4Z

1

C794

2

5

1

C787

2

1U_0402_6.3V4Z

1

C795

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

1

C788

2

0.1U_0402_16V4Z

1

C796

2

1

C789

2

0.1U_0402_16V4Z

1

C797

2

0.1U_0402_16V4Z

1

2

1

2

C790

C798

1

C791

2

0.01U_0402_16V7K

1

C799

0.01U_0402_16V7K

2

+1.8VS +1.8VS

12

R657
549_0402_1%~D

1.27V~0.9V

+VREFA1
+VREFA0

R661

931_0402_5%

PM@

MEM_VREF<16,17,21> MEM_VREF<16,17,21>

4

MEM_VREF MEM_VREF

2

G

10mil

1

C800

0.01U_0402_16V7K

2

PM@

1 2

13

D

Q62

SSM3K7002FU_SC70-3

S

PM@

PM@

12

R659

1.3K_0402_1%

PM@

Security Classification

Issued Date

THIS SHEET OF E NGIN EERIN G DRA WING I S THE P ROPRI ETAR Y PROP ERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECR ET I NFO RMA TION . T HIS SHE ET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUT HORIZ ED B Y COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

12

R658
549_0402_1%~D

1.27V~0.9V

+VREFA3
+VREFA2

R662

931_0402_5%

PM@

2

G

2

10mil

1

C801

0.01U_0402_16V7K

2

PM@

1 2

13

D

Q63

SSM3K7002FU_SC70-3

S

PM@

Title

Size Document Number R ev

Custom

Date: Sheet

PM@

12

R660

1.3K_0402_1%

PM@

Compal Electronics, Inc.

VRAM DDRA

of

1

22 52Monday, June 30, 2008

0.1

CyberForum.ru

5

PCI

SRC

CPU

CLKSEL1

0

FSA

CLKSEL0

MHz

266

MHz

1000

MHz

MHz

33.30

14.318 96.0 48.0

DOT_96
MHz

USB
MHz

FSC FSB REF

CLKSEL2

01000 133 33.31 14.318 96.0 48.0

01001 200 33.30 14.318 96.0 48.0

D D

01001 166 33.31 14.318 96.0 48.0

11000 333 33.30 14.318 96.0 48.0

11000 100 33.31 14.318 96.0 48.0

11001 400 33.30 14.318 96.0 48.0

111

FSA

R184 2.2K_0402_5%

CPU_BSEL0<6>

C C

CPU_BSEL1<6>

B B

CPU_BSEL2<6>

12

@

R215
10K_0402_5%

12

R218

A A

10K_0402_5%

R187 0_0402_5%

R198 0_0402_5%

FSC

R204 10K_0402_5%
R209 0_0402_5%

+3VS+3VS +3VS

12

PM@

R216
10K_0402_5%

12

GM@

R219
10K_0402_5%

1 2

1 2

1 2
1 2

12

12

R217
10K_0402_5%

12

@

R220
10K_0402_5%

FSB

Reserved

+VCCP

@

R183

56_0402_5%

1 2

R185 1K_0402_5%

1 2

12

@

R190

1K_0402_5%

+VCCP

12

@

R194

1K_0402_5%

R196 1K_0402_5%

1 2

12

@

R199

0_0402_5%

+VCCP

12

@

R200

1K_0402_5%

R205 1K_0402_5%

1 2

12

@

R212

0_0402_5%

14.31818MHZ_16PF_DSX840GA

MCH_CLKSEL0 <8>

MCH_CLKSEL1 <8>

MCH_CLKSEL2 <8>

C455 22P_0402_50V8J

Y2

C456 22P_0402_50V8J

Routing the trace at least 10mil

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96#

Pin28/29 : LCDCLK / LCDCLK#
1 = Pin24/25 : SRC_0 / SRC_0#
Pin28/29 : 27M/27M_SS

5

CLK_XTAL_INITP_EN PCI4_SEL PCI2_TME

12

CLK_XTAL_OUT

4

R178 0_0805_5%

+3VS

R181 0_0805_5%@

+1.5VS

R182 0_0805_5%

+VCCP

CLK_48M_CR<34>

CLK_48M_ICH<29>

CLK_14M_ICH<29>
CLK_14M_SIO<39>

CK_PWRGD<29>

H_STP_CPU#<29>

H_STP_PCI#<29>

CLK_PCI_DB<39>

CLK_PCI_LPC<38>
CLK_PCI_ICH<27>

4

1 2

1 2

1 2

+3VSM_CK505

1

C448
10U_0805_10V4Z

2

1

2

1

C441
10U_0805_10V4Z

2

+VDD_CK505

SA000020K00 (Silego : SLG8SP556VTR )
SA000020H00 (ICS : ICS9LPRS387AKLFT)

+VDD_CK505

R192 12_0402_5%

1 2

R193 12_0402_5%

1 2

R195 33_0402_5%

1 2

R197 33_0402_5%@

1 2

R207 33_0402_5%@

1 2

R213 33_0402_5%

1 2

R214 33_0402_5%

1 2

3

1

C452

0.1U_0402_16V4Z

2

CPU_0

CPU_0#

CPU_1

CPU_1#

SRC_0/DOT_96

LCDCLK/27M

SRC_2

SRC_2#

SRC_3

SRC_3#

SRC_4

SRC_4#

SRC_6

SRC_6#

SRC_7

SRC_7#

SRC_8/CPU_ITP

SRC_9

SRC_9#

SRC_10

SRC_10#

SRC_11

SRC_11#

CLKREQ_3#
CLKREQ_4#
CLKREQ_6#
CLKREQ_7#

CLKREQ_9#
SLKREQ_10#
CLKREQ_11#

Compal Secret Data

1

C446

0.1U_0402_16V4Z

2

9

SDA

10

SCL

71
70
68
67

24
25

28
29

32
33

35
36

39
40

57
56

61
60

64
63

44
45

50
51

48
47

37
41
58
65
43
49
46
21

C442

0.1U_0402_16V4Z

1

C449

0.1U_0402_16V4Z

2

+3VSM_CK505

FSA
FSB
FSC

CK_PWRGD

PM_STP_CPU#
PM_STP_PCI#

CLK_XTAL_IN
CLK_XTAL_OUT

PCI2_TME

PCI4_SEL
ITP_EN

1

C443

0.1U_0402_16V4Z

2

U16

55

6
12
72
19
27

66
31
62
52
23
38

20

2

7

8

1
11

53
54

5

4

13
14
15
16
17

18

3
22
26
69
30
34
59
42
73

SLG8SP556VTR_QFN72_10X10

1

C450

0.1U_0402_16V4Z

2

VDD_SRC
VDD_REF
VDD_PCI
VDD_CPU
VDD_48
VDD_PLL3

VDD_CPU_IO
VDD_PLL3_IO
VDD_SRC_IO
VDD_SRC_IO
VDD_IO
VDD_SRC_IO

USB_0/FS_A
FS_B/TEST_MODE
REF_0/FS_C/TEST_
REF_1

CKPWRGD/PD#
NC

CPU_STOP#
PCI_STOP#

XTAL_IN
XTAL_OUT

PCI_1
PCI_2
PCI_3
PCI_4/SEL_LCDCL
PCIF_5/ITP_EN

VSS_PCI
VSS_REF
VSS_48
VSS_IO
VSS_CPU
VSS_PLL3
VSS_SRC
VSS_SRC
VSS_SRC
VSS

1

C444

0.1U_0402_16V4Z

2

Security Cla ssification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

1

C445

0.1U_0402_16V4Z

2

1

C451

0.1U_0402_16V4Z

2

SRC_0#/DOT_96#

LCDCLK#/27M_SS

SRC_8#/CPU_ITP#

USB_1/CLKREQ_A#

2008/03/25 2008/04/

1

C453

0.1U_0402_16V4Z

2

CLK_SMBDATA
CLK_SMBCLK

CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_BCLK
CLK_MCH_BCLK#

R_CLK_DOT
R_CLK_DOT#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_EXP
CLK_PCIE_EXP#

CLK_PCIE_WLAN2
CLK_PCIE_WLAN2#

CLK_PCIE_WLAN
CLK_PCIE_WLAN#

CLK_PCIE_WLAN1
CLK_PCIE_WLAN1#

CLK_PCIE_LAN
CLK_PCIE_LAN#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_PCIE_SATA
CLK_PCIE_SATA#

EXP_CLKREQ#
WLAN_CLKREQ2#
WLAN_CLKREQ#
WLAN_CLKREQ1#
CLKREQ_LAN#

SATA_CLKREQ#_R
MCH_CLKREQ#_R

Deciphered Date

1

2

2

C447

0.1U_0402_16V4Z

1

C454

0.1U_0402_16V4Z

2

CLK_SMBDATA <14,15>
CLK_SMBCLK <14,15>

CLK_CPU_BCLK <5>
CLK_CPU_BCLK# <5>
CLK_MCH_BCLK <8>
CLK_MCH_BCLK# <8>

R186 0_0402_5%GM@

1 2

R188 0_0402_5%PM@

1 2

R189 0_0402_5%GM@

1 2

R191 0_0402_5%PM@

1 2

MCH_SSCDREFCLK <8>
MCH_SSCDREFCLK# <8>

CLK_MCH_3GPLL <8>
CLK_MCH_3GPLL# <8>

CLK_PCIE_EXP <31>
CLK_PCIE_EXP# <31>

CLK_PCIE_WLAN2 <31>
CLK_PCIE_WLAN2# <31>

CLK_PCIE_WLAN <31>
CLK_PCIE_WLAN# <31>

CLK_PCIE_WLAN1 <31>
CLK_PCIE_WLAN1# <31>

CLK_PCIE_LAN <32>
CLK_PCIE_LAN# <32>

CLK_PCIE_ICH <29>
CLK_PCIE_ICH# <29>

CLK_PCIE_SATA <28>
CLK_PCIE_SATA# <28>

EXP_CLKREQ# <31>
WLAN_CLKREQ2# <31>
WLAN_CLKREQ# <31>
WLAN_CLKREQ1# <31>
CLKREQ_LAN# <32>

R221 0_0402_5%

1 2

R222 0_0402_5%

1 2

2

1

+3VS

R235 0_0402_5%

1 2

2N7002DW-T/R7_SOT363-6

ICH_SMBDATA<29,31>

ICH_SMBCLK<29,31>

6 1

@

+3VS

@

3

2N7002DW-T/R7_SOT363-6

R234 0_0402_5%

1 2

CLK_MCH_DREFCLK <8>

CLK_PCIE_VGA <16>

CLK_MCH_DREFCLK# <8>

CLK_PCIE_VGA# <16>

Q1A

2
5

Q1B

4

@

R179

2.2K_0402_5%

@

R180

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

SRC PORT LIST

DEVICEPORT

SRC0
SRC2
SRC3
SRC4
SRC6
SRC7

MCH_DREFCLK
MCH_3GPLL
PCIE_EXP#

PCIE_WLAN2

PCIE_WLAN

PCIE_WLAN1
SRC8
SRC9
SRC10
SRC11

SATA_CLKREQ#_R
EXP_CLKREQ#
WLAN_CLKREQ1#
MCH_CLKREQ#_R
CLKREQ_LAN#
WLAN_CLKREQ#
WLAN_CLKREQ2#

REQ PORT LIST

PCIE_LAN

PCIE_ICH

PCIE_SATA

R201 10K_0402_5%

R202 10K_0402_5%

R203 10K_0402_5%

R206 10K_0402_5%

R208 10K_0402_5%

R210 10K_0402_5%

R211 10K_0402_5%

12
12
12
12
12
12
12

+3VS

DEVICEPORT

REQ_3#
REQ_4#
REQ_6#
REQ_7#
REQ_9#

PCIE_EXP#

PCIE_WLAN2

PCIE_WLAN
PCIE_WLAN1

PCIE_LAN
REQ_10#
REQ_11#
REQ_A#

SATA_CLKREQ# <29>
MCH_CLKREQ# <8>

Compal Electronics,Ltd.

Title

Clock Generator CK505

Size Doc u ment Numbe r Re v

Custom

KIWB3/B4_LA4551P

Date: Sheet

PCIE_SATA

MCH_3GPLL

1

23 52Monday, June 30, 2008

0.1

of

CyberForum.ru

5

4

3

2

1

+3VS

12

@

R223
0_0402_5%

D D

C C

+3VS

12

12

@

R226
0_0402_5%

R225

4.7K_0402_5%

GM@

+3VS

TMDS pull down (500ohm) resistors G9x only

HDMI_CLK+_CONN
HDMI_CLK-_CONN
HDMI_TX0+_CONN
HDMI_TX0-_CONN
HDMI_TX1+_CONN
HDMI_TX1-_CONN
HDMI_TX2+_CONN
HDMI_TX2-_CONN

B B

A A

NEAR CONNECT

HDMI_CLK+

HDMI_CLK-

HDMI_TX0+

HDMI_TX0-

HDMI_TX1+

HDMI_TX1-

HDMI_TX2+

HDMI_TX2-

HDMI_CLK+
HDMI_CLK­HDMI_TX0+
HDMI_TX0­HDMI_TX1+
HDMI_TX1­HDMI_TX2+
HDMI_TX2-

1 2

R236 499_0402_1%PM@

1 2

R237 499_0402_1%PM@

1 2

R238 499_0402_1%PM@

1 2

R239 499_0402_1%PM@

1 2

R240 499_0402_1%PM@

1 2

R241 499_0402_1%PM@

1 2

R242 499_0402_1%PM@

1 2

R243 499_0402_1%PM@

L17

1

1

4

4

@

WCM-2012-900T_4P
L18

1

1

4

4

@

WCM-2012-900T_4P
L20

1

1

4

4

@

WCM-2012-900T_4P
L21

1

1

4

4

WCM-2012-900T_4P@

R251 0_0402_5%

1 2

R252 0_0402_5%

1 2

R253 0_0402_5%

1 2

R254 0_0402_5%

1 2

R255 0_0402_5%

1 2

R256 0_0402_5%

1 2

R257 0_0402_5%

1 2

R258 0_0402_5%

1 2

5

2

2

3

3

2

2

3

3

2

2

3

3

2

2

3

3

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

13

D

PM@

S

Q2
2N7002W-T/R7_SOT323-3

HDMI_CLK+_CONN
HDMI_CLK-_CONN
HDMI_TX0+_CONN
HDMI_TX0-_CONN
HDMI_TX1+_CONN
HDMI_TX1-_CONN
HDMI_TX2+_CONN
HDMI_TX2-_CONN

12

@

R224
0_0402_5%

4.7K_0402_5%

R227

1 2

R229

1 2

4.7K_0402_5%

4.7K_0402_5%

TMDS_B_CLK<10>
TMDS_B_CLK#<10>

TMDS_B_DATA0<10>
TMDS_B_DATA0#<10>

TMDS_B_DATA1<10>
TMDS_B_DATA1#<10>

TMDS_B_DATA2<10>
TMDS_B_DATA2#<10>

2

+3VS

G

R612

@
@

@

HDMICLK_R
HDMIDAT_R

HDMI_DETECT

R613

4.7K_0402_5%

@

1 2

1 2

9/14 Reserve for VGA
used;check pin name

HDMI_DETECT_VGA<16>

4

P/N:SA00002D700 (8101T)
P/N:SA00001U900 (CH7318A)

U17

25

OE#

28

SCL_SINK

29

SDA_SINK

30

HPD_SINK

32

DDC_EN

34

CFG0

35

CFG1

internal pull down

48

IN_D4+

47

IN_D4-

45

IN_D3+

44

IN_D3-

42

IN_D2+

41

IN_D2-

39

IN_D1+

38

IN_D1-

PS8101TQFN48G_QFN48_7X7GM@

9/14 Modify for
UMA used

HDMI_DETECT

R249

1 2

1K_0402_1%PM@

@

D6
RB751V_SOD323

2 1

12

PM@

R250
10K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/25 2008/04/

3

L19

1 2

FBML10160808121LMT_0603PM@

+5VS

2

VCC

11

VCC

15

VCC

21

VCC

26

VCC

33

VCC

40

VCC

46

VCC

4

PC1

3

PC0

internal pull down

6

REXT

7

HPD#

8

SDA

9

SCL

10

RT_EN#

13

OUT_D4+

14

OUT_D4-

16

OUT_D3+

17

OUT_D3-

19

OUT_D2+

20

OUT_D2-

22

OUT_D1+

23

OUT_D1-

1

GND

5

GND

12

GND

18

GND

24

GND

27

GND

31

GND

36

GND

37

GND

43

GND

49

PAD

3

1

@

2

D7
BAT54S-7-F_SOT23-3

Compal Secret Data

Deciphered Date

FOR 7318C PIN6 PULL DOWN 1.2Kohm

PIN7 PULL DOWN 7.5Kohm
PIN7 PULL UP 20Kohm

+3VS

1

GM@

C457

0.1U_0402_16V4Z

2

R228 4.7K_0402_5%GM@

1 2

R230 4.7K_0402_5%@

1 2

R231 499_0402_1%GM@

1 2

TMDS_B_HPD#

HDMI_CLK+
HDMI_CLK-

HDMI_TX0+
HDMI_TX0-

HDMI_TX1+
HDMI_TX1-

HDMI_TX2+
HDMI_TX2-

1 2

R247 0_0402_5%GM@

1 2

R248 0_0402_5%PM@

PM@

C472
330P_0402_50V7K

+5VS

HDMIDAT_R

1

GM@

C458

0.1U_0402_16V4Z

2

TMDS_B_HPD# <10>

+5VS

3

3

2

2

1

GM@

C459

0.1U_0402_16V4Z

2

+3VS

VGA_HDMI_CLK-<18>
VGA_HDMI_CLK+<18>

VGA_HDMI_TX0-<18>
VGA_HDMI_TX0+<18>

VGA_HDMI_TX1-<18>
VGA_HDMI_TX1+<18>

VGA_HDMI_TX2-<18>
VGA_HDMI_TX2+<18>

VGA_HDMI_SDA<16>

VGA_HDMI_SCL<16>

2

@

1

D5
BAT54S-7-F_SOT23-3

HDMIDAT_R
HDMICLK_RHDMI_DETECT_VGA

HDMICLK_R

1

@

D8
BAT54S-7-F_SOT23-3

1

GM@

C460
10U_0805_10V4Z

2

+3VS

12

GM@

R232

2.2K_0402_5%

R244

@

0_0805_5%

R245

2.2K_0402_5%

1 2

Title

Size D ocument Number Rev

Custom
Date: Sheet

12

C461 0.1U_0402_16V7KPM@
C462 0.1U_0402_16V7KPM@

C463 0.1U_0402_16V7KPM@
C464 0.1U_0402_16V7KPM@

C465 0.1U_0402_16V7KPM@
C466 0.1U_0402_16V7KPM@

C467 0.1U_0402_16V7KPM@
C468 0.1U_0402_16V7KPM@

L15 MBK1608121YZF_0603PM@

L16 MBK1608121YZF_0603PM@

HDMI_CLK-_CONN
HDMI_CLK+_CONN
HDMI_TX0-_CONN
HDMI_TX0+_CONN
HDMI_TX1-_CONN
HDMI_TX1+_CONN
HDMI_TX2-_CONN
HDMI_TX2+_CONN

Compal Electronics,Ltd.

Level Shiftter_PS8101T

TMDS_B_HPD#

GM@

R233

2.2K_0402_5%

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

C469

PM@

12P_0402_50V8J

+5VS

21

R246

2.2K_0402_5%

1 2

KIWB1/B2_LA4601P

1

1

C470

PM@

2

2

12P_0402_50V8J

D4
RB491D_SC59-3

+5VS_HDMI

JHDMI

18
16
15
19

12
10

9
7
6
4
3
1

SUYIN_100042MR019S153ZL

1

+3VS

12

R615
20K_0402_1%

@

12

R614

7.5K_0402_1%

@

HDMIDAT_NB <8>
HDMICLK_NB <8>

HDMI_CLK­HDMI_CLK+

HDMI_TX0­HDMI_TX0+

HDMI_TX1­HDMI_TX1+

HDMI_TX2­HDMI_TX2+

HDMIDAT_R
HDMICLK_R

C471

1

0.1U_0402_16V4Z

2

+5V
SDA
SCL
HP_DET

CK­CK+
D0­D0+
D1­D1+
D2­D2+

DDC/CEC_GND

24 52Monday, June 30, 2008

CEC

Reserved

GND
GND
GND
GND
GND
GND
GND
GND

of

HDMI_CEC<16>

13
14

2
5
8
11
20
21
22
23
17

0.1

CyberForum.ru

5

LCD POWER CIRCUIT

+3VS

W=60mils

D D

1

1

C149

0.1U_0402_16V4Z

@

C478

4.7U_0805_10V4Z

2

2

delay 1.1ms

U18

5

4

OUT

IN

GND

IN

G5243T11U_SOT23-5

EN

1

place C361 near U13

2

3

R264

100K_0402_1%

+LCDVDD

W=60mils

1

C473

4.7U_0805_10V4Z

2

1 2

4

1

C474

0.1U_0402_16V4Z

2

12

R2630_0402_5%

GM@

12

R2650_0402_5%

PM@

GM_ENVDD <10>

VGA_ENVDD <16>

3

BKOFF#<38>

GMCH_ENBKL<10>
VGA_ENBKL<16>

BKOFF# D ISPOF F#

D9

CH751H-40PT_SOD323-2

R260 0_0402_5%GM@
R261 0_0402_5%PM@

2

+3VS

12

R259

21

12
12

4.7K_0402_5%

ENBKL

R262

100K_0402_1%

1 2

change from 10K to 100K
5/8 by checklist

ENBKL <38>

470P_0402_50V7K

1

@

1

1

C475

2

2

470P_0402_50V7K

For EMI

INVT_PWM

DAC_BRIG

DISPOFF#

@

@

1

C477

C476

2

470P_0402_50V7K

place C363 &C362 near U12

B+

L22

UMA LCD/PANEL BD. Conn.

JLVDS1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39
GND41GND

ACES_87142-4041

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

LVDS_SCL
LVDS_SDA

LVDS_BCLK#
LVDS_BCLK

LVDS_B2
LVDS_B2#

LVDS_B1
LVDS_B1#LVDS_B1#

LVDS_B0
LVDS_B0#

+3VS +3VS

+LCDVDD_CONN

(60 MIL)

LVDS_SCL <10>
LVDS_SDA <10>

LVDS_BCLK# <10>
LVDS_BCLK <10>

LVDS_B2 <10>
LVDS_B2# <10>

LVDS_B1 <10>
LVDS_B1# <10>

LVDS_B0 <10>
LVDS_B0# <10>

LVDS_ACLK
LVDS_ACLK#

LVDS_A2
LVDS_A2#

LVDS_A1
LVDS_A1#

LVDS_A0
LVDS_A0#

+LEDVDD

DISPOFF#

C C

INVT_PWM<38>
DAC_BRIG<38>

LVDS_ACLK<10>
LVDS_ACLK#<10>

LVDS_A2<10>
LVDS_A2#<10>

LVDS_A1<10>
LVDS_A1#<10>

LVDS_A0<10>
LVDS_A0#<10>

FBMA-L11-201209-221LMA30T_0805

12

C479

4.7U_0805_10V4Z

VGA_LVDS_ACLK<18>
VGA_LVDS_ACLK#<18>

1

1

C837
680P_0402_50V7K

2

2

@

INVT_PWM<38>
DAC_BRIG<38>

VGA_LVDS_A2<18>
VGA_LVDS_A2#<18>

VGA_LVDS_A1<18>
VGA_LVDS_A1#<18>

VGA_LVDS_A0<18>
VGA_LVDS_A0#<18>

VGA LCD/PANEL BD. Conn.

+LEDVDD

DISPOFF#

VGA_LVDS_ACLK
VGA_LVDS_ACLK#

VGA_LVDS_A2
VGA_LVDS_A2#

VGA_LVDS_A1
VGA_LVDS_A1#

VGA_LVDS_A0
VGA_LVDS_A0#

JLVDS2

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39
GND41GND

ACES_87142-4041

2

2

4

4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42

+LCDVDD_CONN

2

C836
680P_0402_50V7K

1

@

L23

(60 MIL)

FBMA-L11-201209-221LMA30T_0805

VGA_LVDS_SDA
VGA_LVDS_SCL

VGA_LVDS_BCLK
VGA_LVDS_BCLK#

VGA_LVDS_B0
VGA_LVDS_B0#

VGA_LVDS_B1
VGA_LVDS_B1#

VGA_LVDS_B2
VGA_LVDS_B2#

12

+LCDVDD

VGA_LVDS_SDA <16>
VGA_LVDS_SCL <16>

VGA_LVDS_BCLK <18>

VGA_LVDS_BCLK# <18>

VGA_LVDS_B0 <18>

VGA_LVDS_B0# <18>

VGA_LVDS_B1 <18>

VGA_LVDS_B1# <18>

VGA_LVDS_B2 <18>

VGA_LVDS_B2# <18>

B B

+LCDVDD

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

2

Date: Sheet

Compal Electronics, Inc.

LVDS & DVI Connector

KIWB1/B2_LA4601P

25 52Monday, June 30, 2008

1

0.1

of

CyberForum.ru

A

B

C

D

E

CRT Connector

CLOSE TO CHIPSET

R266 0_0402_5%PM@

VGA_CRT_R<16>

GMCH_CRT_R<10>

1 1

VGA_CRT_G<16>

GMCH_CRT_G<10>

VGA_CRT_B<16>

GMCH_CRT_B<10>

2 2

VGA_HSYNC<16>
GMCH_CRT_HSYNC<10>

1 2

R267 0_0402_5%GM@

1 2

R268 0_0402_5%PM@

1 2

R269 0_0402_5%GM@

1 2

R270 0_0402_5%PM@

1 2

R271 0_0402_5%GM@

1 2

R276 0_0402_5%PM@

1 2

Place closed to chipset

R277 0_0402_5%PM@

VGA_VSYNC<16>

3 3

GMCH_CRT_VSYNC<10>

1 2

CLOSE TO CONN

12

R272
150_0402_1%

1

C487

0.1U_0402_16V4Z

2

<BOM Structure>

1

C490

0.1U_0402_16V4Z

2

12

R273
150_0402_1%

+CRT_VCC

5

A2Y

3

+CRT_VCC

5

A2Y

3

12

R274
150_0402_1%

1

P

4

OE#

G

U19
SN74AHCT1G125DCKR_SC70-5

1

P

4

OE#

G

U20
SN74AHCT1G125DCKR_SC70-5

CRT_R_1

CRT_G_1

CRT_B_1

12

R275
1K_0402_5%

1

@

C481
10P_0402_50V8J

2

CRT_HSYNC_1

CRT_VSYNC_1

L24 FCM1608C-121T_0603

1 2

L25 FCM1608C-121T_0603

1 2

L26 FCM1608C-121T_0603

1 2

1

@

C482
10P_0402_50V8J

2

+5VS +5VS +5VS

3

2

@

D11
BAT54S-7-F_SOT23-3

+5VS +5VS

3

2

@

D14
BAT54S-7-F_SOT23-3

1

@

C483
10P_0402_50V8J

2

3

1

2

3

1

2

L27 FCM1608C-121T_0603

1 2

L28 FCM1608C-121T_0603

1 2

1

@

D12
BAT54S-7-F_SOT23-3

1

@

D15
BAT54S-7-F_SOT23-3

JVGA_VSJVGA_HS

1

2

@

C488
10P_0402_50V8J

1

C484
10P_0402_50V8J

2

3

2

@

D13
BAT54S-7-F_SOT23-3

1

2

1

C485
10P_0402_50V8J

2

REDGREENBLUE

1

JVGA_HS

JVGA_VS

C489

@

10P_0402_50V8J

RED

GREEN

BLUE

1

C486
10P_0402_50V8J

2

+5VS

2 1

RED
GREEN
BLUE
JVGA_VS
JVGA_HS

CRT_DDC_DAT
CRT_DDC_CLK

D10

RB491D_SC59-3

W=40mils

+CRT_VCC

+CRT_VCC

1
2
3
4
5
6
7
8

9
10
11
12

13
14

1

C480

0.1U_0402_16V4Z

2

JCRT1

1
2
3
4
5
6
7
8
9
10
11
12

GND1
GND2

ACES_87213-1200G

ME@

2.2K

+3VS

+CRT_VCC

12

R280

2.2K_0402_5%

Issued Date

2.2K

12

R282

2.2K_0402_5%

CRT_DDC_DAT

1

@

C491
100P_0402_50V8J

2

2007/10/15 2008/10/15

C

CRT_DDC_CLK

1

@

C492
68P_0402_50V8K

2

Compal Secret Data

Deciphered Date

Title

Size D ocument Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

CRT & TV-OUT Connector

KIWB1/B2_LA4601P

26 52Monday, June 30, 2008

E

0.1

of

12

R278

2.2K_0402_5%

R281 0_0402_5%PM@

VGA_DDCDATA<16>

GMCH_CRT_DATA<10>

GMCH_CRT_CLK<10>

VGA_DDCCLK<16>

4 4

1 2

R283 0_0402_5%GM@

1 2

R284 0_0402_5%GM@

1 2

R285 0_0402_5%PM@

1 2

12

R279

2.2K_0402_5%

+3VS

5

4

2

Q30A
2N7002DW-T/R7_SOT363-6

3

Q30B
2N7002DW-T/R7_SOT363-6

61

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CyberForum.ru

5

4

3

2

1

D D

C C

+3VS

1 2

R286 8.2K_0402_5%

1 2

R287 8.2K_0402_5%

1 2

R288 8.2K_0402_5%

1 2

R289 8.2K_0402_5%

1 2

R290 8.2K_0402_5%

1 2

R291 8.2K_0402_5%

1 2

R292 8.2K_0402_5%

1 2

R293 8.2K_0402_5%

+3VS

1 2

R294 8.2K_0402_5%

1 2

R295 8.2K_0402_5%

1 2

R296 8.2K_0402_5%

1 2

R297 8.2K_0402_5%

1 2

R298 8.2K_0402_5%

1 2

R299 8.2K_0402_5%

1 2

R300 8.2K_0402_5%

1 2

R301 8.2K_0402_5%

1 2

R303 8.2K_0402_5%

1 2

R304 8.2K_0402_5%

1 2

R305 8.2K_0402_5%

1 2

R306 8.2K_0402_5%

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U21B

D11

AD0

C8

AD1

D9

AD2

E12

AD3

E9

AD4

C9

AD5

E10

AD6

B7

AD7

C7

AD8

C5

AD9

G11

AD10

F8

AD11

F11

AD12

E7

AD13

A3

AD14

D2

AD15

F10

AD16

D5

AD17

D10

AD18

B3

AD19

F7

AD20

C3

AD21

F3

AD22

F4

AD23

C1

AD24

G7

AD25

H7

AD26

D1

AD27

G5

AD28

H6

AD29

G1

AD30

H3

AD31

Interrupt I/F

J5

PIRQA#

E1

PIRQB#

J6

PIRQC#

C4

PIRQD#

ICH9-M ES_FCBGA676

PCI

REQ0#
GNT0#

REQ1#/GPIO50

GNT1#/GPIO51

REQ2#/GPIO52

GNT2#/GPIO53

REQ3#/GPIO54

GNT3#/GPIO55

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PCIRST#
DEVSEL#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

PAR

F1
G4
B6
A7
F13
F12
E6
F6

D8
B4
D6
A5

D3
E3
R1
C6
E4
C2
J4
A4
F5
D7

C14
D4
R2

H4
K6
F2
G2

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
PCI_REQ2#
PCI_GNT2#
PCI_REQ3#
PCI_GNT3#

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_IRDY#
PCI_PAR
PCI_RST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PLT_RST#
CLK_PCI_ICH
PCI_PME#

1 2

R302 10K_0402_5%@

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_CBE#3 <32>

CLK_PCI_ICH <23>
PCI_PME# <38>

+3VALW

Place closely pin D4

PCI_GNT0#

12

@

1 2

R310 1K_0402_5%@

B B

PCI_GNT3#

R307
1K_0402_5%

SB_SPI_CS#1<29>

SB_SPI_CS#1

12

@

R308
1K_0402_5%

Pull high?

CLK_PCI_ICH

@

R309
10_0402_5%

1 2
1

@

C493

8.2P_0402_50V

2

Boot BIOS Strap

A16 Swap Override Strap

PCI_GNT#3

A A

Low= A16 swap o v e r ri de Enable
High= Default*

5

PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction

0

11

4

1 SPI
01

PCI
LPC*

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Deciphered Date

2

PCI_RST#

PLT_RST#

12

@

12

Title

Size Document Number Rev

Date: Sheet

PCI_RST# <38,39>

R311
100K_0402_5%

PLT_RST# <8,16,31,32>

R312
100K_0402_5%

Compal Electronics, Inc.

ICH9M(1/4)-PCI

JITR1_LA-4141P

1

0.1

of

27 52Monday, June 30, 2008

CyberForum.ru

5

+RTCVCC

R314 330K_0402_1%

LAN100_SLP

1 2

R316 1M_0402_5%

SM_INTRUDER#

1 2

R318 330K_0402_1%

D D

C C

1 2

ICH_INTVRMEN

+RTCVCC

HDD

ODD

1 2

2

C495

0.1U_0402_16V4Z

1

R322

100_0603_1%

DRIVE_LED#<42>

SATA_DTX_C_IRX_N0<35>
SATA_DTX_C_IRX_P0<35>

SATA_ITX_DRX_N0<35>
SATA_ITX_DRX_P0<35>

SATA_DTX_C_IRX_N1<35>
SATA_DTX_C_IRX_P1<35>

SATA_ITX_DRX_N1<35>
SATA_ITX_DRX_P1<35>

32.768KHZ_12.5P_1TJS125BJ2A251

+RTCBATT

DRIVE_LED#

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0

SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1
SATA_ITX_DRX_N1
SATA_ITX_DRX_P1

+RTCVCC

HDA_BITCLK_CODEC<8,18,36>

HDA_SYNC_CODEC<8,18,36>

HDA_RST_CODEC#<8,18,36>

HDA_SDOUT_CODEC<8,18,36>

HDA_SDIN0<8>
HDA_SDIN1<18>
HDA_SDIN2<36>

+3VS

4

1 2

C494 15P_0402_50V8J

Y3

2
3

1 2

C496 15P_0402_50V8J

1 2

R320 20K_0402_5%

1

IN

NC

4

OUT

NC

CLRP1

2 1

2MM

1 2

C497 1U_0603_10V4Z

close to RAM door

+1.5VS

1 2

R326 24.9_0402_1%

1 2

R327 33_0402_5%

1 2

R329 33_0402_5%

1 2

R330 33_0402_5%

1 2

R333 33_0402_5%

1 2

R335 10K_0402_5%

1 2
1 2

1 2
1 2

SATA_LED#

D16RB751V_SOD323

2 1

C498 0.01U_0402_16V7K
C499 0.01U_0402_16V7K

C500 0.01U_0402_16V7K
C501 0.01U_0402_16V7K

12

R317
10M_0402_5%

SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0SATA_ITX_DRX_P0

SATA_ITX_C_DRX_N1
SATA_ITX_C_DRX_P1

ICH_RTCX1

ICH_RTCX2
ICH_RTCRST#

ICH_SRTCRST#
SM_INTRUDER#

ICH_INTVRMEN
LAN100_SLP

GLAN_COMP
HDA_BITCLK_R
HDA_SYNC_R
HDA_RST_R#

HDA_SDOUT_R

U21A

C23

RTCX1

C24

RTCX2

A25

RTCRST#

F20

SRTCRST#

C22

INTRUDER#

B22

INTVRMEN

A22

LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14

LAN_RXD0

G13

LAN_RXD1

D14

LAN_RXD2

D13

LAN_TXD_0

D12

LAN_TXD_1

E13

LAN_TXD_2

B10

GPIO56

B28

GLAN_COMPI

B27

GLAN_COMPO

AF6

HDA_BIT_CLK

AH4

HDA_SYNC

AE7

HDA_RST#

AF4

HDA_SDIN0

AG4

HDA_SDIN1

AH3

HDA_SDIN2

AE5

HDA_SDIN3

AG5

HDA_SDOUT

AG7

HDA_DOCK_EN#/GPIO33

AE8

HDA_DOCK_RST#/GPIO34

AG8

SATALED#

AJ16

SATA0RXN

AH16

SATA0RXP

AF17

SATA0TXN

AG17

SATA0TXP

AH13

SATA1RXN

AJ13

SATA1RXP

AG14

SATA1TXN

AF14

SATA1TXP

ICH9-M ES_FCBGA676

3

RTC

LAN / GLAN

IHDA

2

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LPCCPU

SATA

LDRQ0#

LDRQ1#/GPIO23

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD

IGNNE#

INIT#
INTR

RCIN#

SMI#

STPCLK#

THRMTRIP#

TP12

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATA_CLKN
SATA_CLKP

SATARBIAS#

SATARBIAS

NMI

LPC_AD1

K4

LPC_AD2

L6

LPC_AD3

K2

LPC_FRAME#

K3

LPC_DRQ0#

J3
J1

N7
AJ27

AJ25
AE23

AJ26
AD22
AF25
AE22

AG25
L3

AF23
AF24

AH27
AG26
AG27

SATA_DTX_C_IRX_N4

AH11

SATA_DTX_C_IRX_P4

AJ11

SATA_ITX_C_DRX_N4

AG12

SATA_ITX_C_DRX_P4

AF12

AH9
AJ9
AE10
AF10

AH18
AJ18
AJ7

SATARBIAS

AH7

GATEA20
H_A20M#

H_DPSLP#
H_FERR#_S
H_PWRGOOD
H_IGNNE#
H_INIT#

H_INTR
KB_RST#

H_NMI
H_SMI#

H_STPCLK#
THRMTRIP_ICH#

R336 1K_0402_5%@

1 2

R337 1K_0402_5%@

1 2

CLK_PCIE_SATA#
CLK_PCIE_SATA

LPC_AD0

K5

LPC_AD[0..3] <38,39>

LPC_FRAME# <38,39>
LPC_DRQ0# <39>

GATEA20 <38>
H_A20M# <5>

R323 0_0402_5%

R338 24.9_0402_1%

12

R325 56_0402_5%

1 2

H_PWRGOOD <6>
H_IGNNE# <5>
H_INIT# <5>

H_INTR <5>

KB_RST# <38>

H_NMI <5>
H_SMI# <5>

H_STPCLK# <5>

R331 54.9_0402_1%

1 2

CLK_PCIE_SATA# <23>
CLK_PCIE_SATA <23>

1 2

H_DPRSTP#H_DPRSTP_R#

C8260.01U_0402_16V7K

12

C8270.01U_0402_16V7K

12

C8240.01U_0402_16V7K

12

C8250.01U_0402_16V7K

12

H_DPRSTP# <6,8,50>
H_DPSLP# <6>

+VCCP

12

R328
56_0402_5%

H_THERMTRIP#

SATA_ITX_DRX_N4_CONN

SATA_ITX_DRX_P4_CONN

SATA_DTX_IRX_N4_CONN

SATA_DTX_IRX_P4_CONN

NEAR U42

10mils width less than 500mils

1

R324
56_0402_5%

R313

10K_0402_5%

R315

10K_0402_5%

R319

56_0402_5%

R321

56_0402_5%

GATEA20

KB_RST#

H_DPRSTP#

H_DPSLP#

+VCCP

12

H_THERMTRIP# <5,8>

SATA_ITX_DRX_N4_CONN <35>

SATA_ITX_DRX_P4_CONN <35>
SATA_DTX_IRX_N4_CONN <35>
SATA_DTX_IRX_P4_CONN <35>

+3VS

12

12

+VCCP

@

12

@

12

H_FERR# <5>

B B

HDA_SDOUT_R

A A

5

4

Need check

+3VS

R339
1K_0402_5%

@

1 2

XOR Chain E ntrance Strap

HDA_SDOUTICH_TP3 Description
0
0
1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

0

RSVD

1

Enter XOR Chain

0

Normal Operation

11

Set PCIE port config bit 1

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

2

SATA PORT LIST

DEVICEPORT

HDD

0

ODD

1

X

2

X

3
4

ESATA

X

5

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

ICH9M(2/4)-LAN,IDELPC,RTC

JITR1_LA-4141P

1

0.1

of

28 52Monday, June 30, 2008

CyberForum.ru

5

4

3

2

1

+3VS

R340 10K_0402_5%

1 2

R341 8.2K_0402_5%

1 2

R342 10K_0402_5%@

1 2

R343 8.2K_0402_5%@

1 2

R348 10K_0402_5%

D D

C C

B B

A A

1 2

R352 8.2K_0402_5%@

1 2

R353 10K_0402_5%@

1 2

R356 10K_0402_5%

1 2

+3VALW

R355 10K_0402_5%

1 2

R361 10K_0402_5%@

1 2

R364 10K_0402_5%

1 2

R366 10K_0402_5%

1 2

R367 1K_0402_5%

1 2

R368 8.2K_0402_5%

1 2
1 2

R372 10K_0402_5%

1 2

+3VS

R376 10K_0402_5%

1 2

R378 10K_0402_5%

1 2

R379 10K_0402_5%@

1 2

R380 10K_0402_5%@

1 2

R382 10K_0402_5%

1 2

R383 10K_0402_5%

1 2

+3VS

R388 10K_0402_5%@

1 2

R389 100K_0402_5%@

1 2

R390 100K_0402_5%@

1 2

R391 1K_0402_5%@

1 2

+3VALW

RP1

45
36
27
18

10K_1206_8P4R_5%

RP2

45
36
27
18

10K_1206_8P4R_5%

RP3

45
36
27
18

10K_1206_8P4R_5%

CLK_ENABLE#<50>

USB_OC#6
USB_OC#1
USB_OC#2
USB_OC#4

USB_OC#5
USB_OC#7
USB_OC#9
USB_OC#0

USB_OC#8
USB_OC#3
USB_OC#10
USB_OC#11

+3VS

1 2
13

D

2

G

S

SERIRQ
PCI_CLKRUN#
GPIO38
EC_THERM#

OCP#

PM_BMBUSY#
GPIO39
GPIO48

LINKALERT#
CL_RST#
XDP_DBRESET#
ICH_RI#
ICH_PCIE_WAKE#
ICH_LOW_BAT#
LID_OUT#
WOL_EN

GPIO7
GPIO13
GPIO17
GPIO18
GPIO20
GPIO22

SB_SPKR

GPIO57
DPRSLPVR
ICH_RSVD

@

R398
330_0402_5%

R399 0_0402_5%@

1 2

@

Q32
RHU002N06_SOT323

+3VALW

H_STP_PCI#<23>
H_STP_CPU#<23>

low-->default
High -->No boot

VRMPWRGD

12

R349
10K_0402_5%

+3VS

@

R354
10K_0402_5%

1 2

3G

WLAN

NEW CARD

TV TUNER

LAN

SPI not used, Left NC

+3VALW

12

SERIRQ<38,39>

OCP#

CPUSB#<31>

EC_SMI#<38>
EC_SCI#<38>

R344

2.2K_0402_5%

R359 0_0402_5%

12

R347
10K_0402_5%

12

@

R357
10K_0402_5%

R362 0_0402_5%

1 2

VGATE<8,50>

R369 0_0402_5%

R384 1K_0402_5%@

ICH_SMBCLK<23,31>

ICH_SMBDATA<23,31>

EC_LID_OUT#<38>

1 2

1 2

XDP_DBRESET#<5>
PM_BMBUSY#<8>

ICH_PCIE_WAKE#<31,32>

EC_THERM#<38>

SATA_CLKREQ#<23>

SB_SPKR<36>

MCH_ICH_SYNC#<8>

AC decoupling c ap r an g e o f 7 5 nF t o 220nF

PCIE_RXN1<31>

PCIE_RXP1<31>
PCIE_TXN1<31>
PCIE_TXP1<31>

PCIE_RXN3<31>

PCIE_RXP3<31>
PCIE_TXN3<31>
PCIE_TXP3<31>

PCIE_RXN4<31>
PCIE_RXP4<31>
PCIE_TXN4<31>
PCIE_TXP4<31>

PCIE_RXN5<31>
PCIE_RXP5<31>
PCIE_TXN5<31>
PCIE_TXP5<31>

PCIE_IRX_PTX_N6<32>
PCIE_IRX_PT X_P6<32>
PCIE_ITX_C_PR X _N6<32>
PCIE_ITX_C_PRX_P6<32>

SB_SPI_CS#1<27>

C507 0.1U_0402_10V7K
C508 0.1U_0402_10V7K

C509 0.1U_0402_10V7K
C510 0.1U_0402_10V7K

C511 0.1U_0402_10V7K
C512 0.1U_0402_10V7K

C513 0.1U_0402_10V7K
C514 0.1U_0402_10V7K

C515 0.1U_0402_10V7K
C516 0.1U_0402_10V7K

USB_OC#0<35>

USB_OC#4<41>

USB_OC#11<41>

R400 22.6_0402_1%

1 2

Within 500 mils

LINKALERT#
ME__EC_CLK1
ME__EC_DATA1

ICH_RI#

XDP_DBRESET#
PM_BMBUSY#

1 2

H_STP_PCI#
R_STP_CPU#

PCI_CLKRUN#
ICH_PCIE_WAKE#

SERIRQ
EC_THERM#

VRMPWRGD

SST_CTL

T69R370 10K_0402_5%

OCP#
GPIO7

EC_SMI#
EC_SCI#
GPIO13
GPIO17
GPIO18
GPIO20
GPIO22
GPIO27

T71

SATA_CLKREQ#
GPIO38
GPIO39
GPIO48
GPIO49
GPIO57

SB_SPKR
MCH_ICH_SYNC#
ICH_RSVD

T72
T73
T74

PCIE_RXN1

PCIE_RXP1

PCIE_C_TXN1

PCIE_C_TXP1

PCIE_RXN3

PCIE_RXP3

PCIE_C_TXN3

PCIE_C_TXP3

PCIE_RXN4

PCIE_RXP4

PCIE_C_TXN4

PCIE_C_TXP4

PCIE_RXN5

PCIE_RXP5

PCIE_C_TXN5

PCIE_C_TXP5

PCIE_IRX_PTX_N6
PCIE_IRX_PT X_P6
PCIE_ITX_PRX_N6
PCIE_ITX_PRX_P6

SB_SPI_CS#1

USB_OC#0

USB_OC#1

USB_OC#2

USB_OC#3

USB_OC#4

USB_OC#5

USB_OC#6

USB_OC#7

USB_OC#8

USB_OC#9

USB_OC#10

USB_OC#11

USBRBIAS

12

R345

2.2K_0402_5%

LID_OUT#

U21C

G16

SMBCLK

A13

SMBDATA

E17

LINKALERT#/GPIO60/CLGPIO4

C17

SMLINK0

B18

SMLINK1

F19

RI#

R4

SUS_STAT#/LPCPD#

G19

SYS_RESET#

M6

PMSYNC#/GPIO0

A17

SMBALERT#/GPIO11

A14

STP_PCI#

E19

STP_CPU#

L4

CLKRUN#

E20

WAKE#

M5

SERIRQ

AJ23

THRM#

D21

VRMPWRGD

A20

TP11

AG19

GPIO1

AH21

GPIO6

AG21

GPIO7

A21

GPIO8

C12

GPIO12

C21

GPIO13

AE18

GPIO17

K1

GPIO18

AF8

GPIO20

AJ22

SCLOCK/GPIO22

A9

GPIO27

D19

GPIO28

L1

SATACLKREQ#/GPIO35

AE19

SLOAD/GPIO38

AG22

SDATAOUT0/GPIO39

AF21

SDATAOUT1/GPIO48

AH24

GPIO49

A8

GPIO57/CLGPIO5

M7

SPKR

AJ24

MCH_SYNC#

B21

TP3

AH20

TP8

AJ20

TP9

AJ21

TP10

ICH9-M ES_FCBGA676

U21D

N29

PERN1

N28

PERP1

P27

PETN1

P26

PETP1

L29

PERN2

L28

PERP2

M27

PETN2

M26

PETP2

J29

PERN3

J28

PERP3

K27

PETN3

K26

PETP3

G29

PERN4

G28

PERP4

H27

PETN4

H26

PETP4

E29

PERN5

E28

PERP5

F27

PETN5

F26

PETP5

C29

PERN6/GLAN_RXN

C28

PERP6/GLAN_RXP

D27

PETN6/GLAN_TXN

D26

PETP6/GLAN_TXP

D23

SPI_CLK

D24

SPI_CS0#

F23

SPI_CS1#GPIO58/CLGPIO6

D25

SPI_MOSI

E23

SPI_MISO

N4

OC0#/GPIO59

N5

OC1#/GPIO40

N6

OC2#/GPIO41

P6

OC3#/GPIO42

M1

OC4#/GPIO43

N2

OC5#/GPIO29

M4

OC6#/GPIO30

M3

OC7#/GPIO31

N3

OC8#/GPIO44

N1

OC9#/GPIO45

P5

OC10#/GPIO46

P3

OC11#/GPIO47

AG2

USBRBIAS

AG1

USBRBIAS#

ICH9-M ES_FCBGA676

SMB

clocks

SYS / GPIOGPIOMISC

Controller Link

DMI0RXN
DMI0RXP
DMI0TXN

DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN

DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN

DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN

DMI3TXP

DMI_CLKN
DMI_CLKP

PCI - Express

DMI_ZCOMP

Direct Media Interface

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N

USB

USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBP10N

USBP10P

USBP11N

USBP11P

SPI

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37

SATA

GPIO

CLK14
CLK48

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

S4_STATE#/GPIO26

PWROK

DPRSLPVR/GPIO16

BATLOW#
PWRBTN#
LAN_RST#

RSMRST#

Power MGT

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

CL_RST0#
CL_RST1#

MEM_LED/GPIO24

GPIO10/SUS_PWR_ACK

GPIO14/AC_PRESENT

WOL_EN/GPIO9

DMI_RXN0

V27

DMI_RXP0

V26

DMI_TXN0

U29

DMI_TXP0

U28

DMI_RXN1

Y27

DMI_RXP1

Y26

DMI_TXN1

W29

DMI_TXP1

W28

DMI_RXN2

AB27

DMI_RXP2

AB26

DMI_TXN2

AA29

DMI_TXP2

AA28

DMI_RXN3

AD27

DMI_RXP3

AD26

DMI_TXN3

AC29

DMI_TXP3

AC28

CLK_PCIE_ICH#

T26

CLK_PCIE_ICH

T25
AF29

AF28

USB20_N0

AC5

USB20_P0

AC4

USB20_N1

AD3

USB20_P1

AD2

USB20_N2

AC1

USB20_P2

AC2

USB20_N3

AA5

USB20_P3

AA4

USB20_N4

AB2

USB20_P4

AB3

USB20_N5

AA1

USB20_P5

AA2

USB20_N6

W5

USB20_P6

W4

USB20_N7

Y3

USB20_P7

Y2

USB20_N8

W1

USB20_P8

W2

USB20_N9

V2

USB20_P9

V3

USB20_N10

U5

USB20_P10

U4

USB20_N11

U1

USB20_P11

U2

+3VS

R346

AH23
AF19
AE21
AD20

H1
AF3

P1
C16

E16
G17

C10
G20
M2
B13
R3
D20
D22
R5
R6
B16
F24

B19
F22

C19
C25

A19
F21

D18
A16

C18
C11
C20

8.2K_0402_5%

1 2

CLK_14M_ICH
CLK_48M_ICH

ICH_SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

S4_STATE#
ICH_POK

R365 499_0402_1%

ICH_LOW_BAT#
PBTN_OUT#

CK_PWRGD_R CK_PWRGD
M_PWROK

CL_VREF0_ICH
CL_VREF1_ICH

CL_RST#

GPIO14

WOL_EN

1 2

R373 0_0402_5%

R374 0_0402_5%

SB_INT _FLASH_SEL <40>

+3VALW

R386

CLK_14M_ICH <23>
CLK_48M_ICH <23>

T68

SLP_S3# <38>
SLP_S4# <38>
SLP_S5# <38>

PBTN_OUT# <38>

1 2

1 2

T70

CL_CLK0 <8>
CL_CLK1

CL_DATA0 <8>
CL_DATA1

CL_RST# <8>

12

10K_0402_5%

change from 100k to 10k ohm 5/8

DMI_RXN0 <8>
DMI_RXP0 <8>
DMI_TXN0 <8>
DMI_TXP0 <8>

DMI_RXN1 <8>
DMI_RXP1 <8>
DMI_TXN1 <8>
DMI_TXP1 <8>

DMI_RXN2 <8>
DMI_RXP2 <8>
DMI_TXN2 <8>
DMI_TXP2 <8>

DMI_RXN3 <8>
DMI_RXP3 <8>
DMI_TXN3 <8>
DMI_TXP3 <8>

CLK_PCIE_ICH# <23>

DMI_IRCOMP

CLK_PCIE_ ICH <23>

R397 24.9_0402_1%

1 2

USB20_N0 <35>
USB20_P0 <35>
USB20_N1
USB20_P1
USB20_N2 <41>
USB20_P2 <41>
USB20_N3 <31>
USB20_P3 <31>
USB20_N4 <41>
USB20_P4 <41>
USB20_N5
USB20_P5
USB20_N6 <41>
USB20_P6 <41>
USB20_N7 <34>
USB20_P7 <34>
USB20_N8 <31>
USB20_P8 <31>
USB20_N9 <31>
USB20_P9 <31>
USB20_N10 <31>
USB20_P10 <31>
USB20_N11 <41>
USB20_P11 <41>

Within 500 mils

LEFT USB

CMOS
3G Card
RIGHT USB

BT
Card Reader
WLAN
TV Tuner
New Card
RIGHT USB

DPRSLPVR

EC_RSMRST#REC_RSMRST#R

D17 RB751V_S OD323

2 1

R387 0_0402_5%@

+1.5VS

+3VALW

12

@

R358
10K_0402_5%

R360 100_0402_5%@

1 2

DPRSLPVR <8,50>

R371 10K_0402_5%

M_PWROK <8>
VGATE <8,50>

ACIN

12

ACIN <38,44>

EC_RSMRST#<38>

PCIE PORT LIST

1
2
3
4
5
6

Place closely pin B2 Place closely pin AC1

12

@

R350
10_0402_5%

1

@

C502
10P_0402_50V8J

2

ICH_POK <8,38>

1 2

10K_0402_5%@

1 2

CK_PWRGD <23>

1

C505

0.1U_0402_16V4Z

2

1

C506

0.1U_0402_16V4Z

2

RSMRST circuit

BAV99DW-7_S O T363

@

R395

2.2K_0402_5%

1 2

1 2

2.2K_0402_5%

DEVICEPORT

3G

WLAN
NEW CARD

TV TUNNER

LAN

R396

D18B

4

5

3

M_PWROK

R363

R375 3.24K_0402_1%

1 2

12

R377
453_0402_1%

R381 3.24K_0402_1%

1 2

12

R385
453_0402_1%

R392

@

0_0402_5%

C

123

E

Q31
MMBT3906_SOT23-3

B

1 2

R394 4.7K_0402_5%

1

D18A
BAV99DW-7_SOT363

6

1 2

EC_RSMRST#R

1 2

2

USB PORT LIST

0
1
2
3
4
5
6
7
8
9
10
11

CLK_14M_ICHCLK_48M_ICH

12

R351
10_0402_5%

@

1

C503
10P_0402_50V8J

@

2

M_PWROK

1

C504

@

1000P_0402_50V7K

2

R393

@

0_0402_5%

DEVICEPORT

LEFT SIDE

CMOS
3G
RIGHT SIDE

BT

CARD READER

WIRELESS

TV TUNNER

NEW CARD

RIGHT SIDE

+3VS

+3VALW

POK <47>

+3VALW

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAI NS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

3

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

ICH9M(3/4)-USB,GPIO,PCIE

Size Docu me n t N u m ber Re v

C

Date: Sheet

JITR1_LA-4141P

1

29 52Monday, J une 30, 2008

of

0.1

CyberForum.ru

5

+RTCVCC

0.1U_0402_16V4Z

D D

C C

+1.5VS

B B

0.1U_0402_16V4Z

A A

+1.5VS

R401

100_0402_5%

R403

100_0402_5%

1 2

+1.5VS

220U_D2_4VM

R407

1 2

CHB1608U301_0603

+1.5VS

C550

0.1U_0402_16V4Z

+3VS

C553

1 2

CHB1608U301_0603

R404

0_0805_5%

1

2

R411

1

1

C520

+5VS +3VS

C517

0.1U_0402_16V4Z

2

2

21

D19
CH751H-40PT_SOD323-2

ICH_V5REF_RUN

1

C523
1U_0603_10V4Z

2

+3VALW+5VALW

21

D20
CH751H-40PT_SOD323-2

ICH_V5REF_SUS

1

C530
1U_0603_10V4Z

2

40 mils

1

+

C533

C532

2

10U_0805_10V4Z

1

C541

2

1U_0603_10V4Z

+1.5VS

1

0.1U_0402_16V4Z

2

close to AC7

+1.5VS

(10UF*1, 2.2UF*1)

4.7U_0805_10V4Z

1

C556

2

5

20 mils

20 mils

10U_0805_10V4Z

1

C534

2

1

C542

2

10U_0805_10V4Z

1

C551

2

CHB1608U301_0603

1 2

R410

C554

20 mils

ICH_V5REF_RUN

ICH_V5REF_SUS

1

1

C535

2

2

2.2U_0603_6.3V4Z

+1.5VS

1

C543

1U_0603_10V4Z

1U_0603_10V4Z

+1.5VS

1U_0603_10V4Z

T77
T78

2.2U_0603_6.3V4Z

1

C555

2

10U_0805_10V4Z

2

+1.5VS

1

C544

2

1

C548

2

VCC_LAN1_05_INT_ICH_1
VCC_LAN1_05_INT_ICH_2 VCCCL1_05_ICH

1

2

+3VS

4

U21F

A23

VCCRTC

A6

V5REF

AE1

V5REF_SUS

AA24

VCC1_5_B[01]

AA25

VCC1_5_B[02]

AB24

VCC1_5_B[03]

AB25

VCC1_5_B[04]

AC24

VCC1_5_B[05]

AC25

VCC1_5_B[06]

AD24

VCC1_5_B[07]

AD25

VCC1_5_B[08]

AE25

VCC1_5_B[09]

AE26

VCC1_5_B[10]

AE27

VCC1_5_B[11]

AE28

VCC1_5_B[12]

AE29

VCC1_5_B[13]

F25

VCC1_5_B[14]

G25

VCC1_5_B[15]

H24

VCC1_5_B[16]

H25

VCC1_5_B[17]

J24

VCC1_5_B[18]

J25

VCC1_5_B[19]

K24

VCC1_5_B[20]

K25

VCC1_5_B[21]

L23

VCC1_5_B[22]

L24

VCC1_5_B[23]

L25

VCC1_5_B[24]

M24

VCC1_5_B[25]

M25

VCC1_5_B[26]

N23

VCC1_5_B[27]

N24

VCC1_5_B[28]

N25

VCC1_5_B[29]

P24

VCC1_5_B[30]

P25

VCC1_5_B[31]

R24

VCC1_5_B[32]

R25

VCC1_5_B[33]

R26

VCC1_5_B[34]

R27

VCC1_5_B[35]

T24

VCC1_5_B[36]

T27

VCC1_5_B[37]

T28

VCC1_5_B[38]

T29

VCC1_5_B[39]

U24

VCC1_5_B[40]

U25

VCC1_5_B[41]

V24

VCC1_5_B[42]

V25

VCC1_5_B[43]

U23

VCC1_5_B[44]

W24

VCC1_5_B[45]

W25

VCC1_5_B[46]

K23

VCC1_5_B[47]

Y24

VCC1_5_B[48]

Y25

VCC1_5_B[49]

AJ19

VCCSATAPLL

AC16

VCC1_5_A[01]

AD15

VCC1_5_A[02]

AD16

VCC1_5_A[03]

AE15

VCC1_5_A[04]

AF15

VCC1_5_A[05]

AG15

VCC1_5_A[06]

AH15

VCC1_5_A[07]

AJ15

VCC1_5_A[08]

AC11

VCC1_5_A[09]

AD11

VCC1_5_A[10]

AE11

VCC1_5_A[11]

AF11

VCC1_5_A[12]

AG10

VCC1_5_A[13]

AG11

VCC1_5_A[14]

AH10

VCC1_5_A[15]

AJ10

VCC1_5_A[16]

AC9

VCC1_5_A[17]

AC18

VCC1_5_A[18]

AC19

VCC1_5_A[19]

AC21

VCC1_5_A[20]

G10

VCC1_5_A[21]

G9

VCC1_5_A[22]

AC12

VCC1_5_A[23]

AC13

VCC1_5_A[24]

AC14

VCC1_5_A[25]

AJ5

VCCUSBPLL

AA7

VCC1_5_A[26]

AB6

VCC1_5_A[27]

AB7

VCC1_5_A[28]

AC6

VCC1_5_A[29]

AC7

VCC1_5_A[30]

A10

VCCLAN1_05[1]

A11

VCCLAN1_05[2]

A12

VCCLAN3_3[1]

B12

VCCLAN3_3[2]

A27

VCCGLANPLL

D28

VCCGLAN1_5[1]

D29

VCCGLAN1_5[2]

E26

VCCGLAN1_5[3]

E27

VCCGLAN1_5[4]

A26

VCCGLAN3_3

ICH9-M ES_FCBGA676

4

VCCA3GP

ARX

ATX

USB CORE

GLAN POWER

CORE

VCCP_CORE

PCI

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]
VCCSUS1_5[2]

VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]

VCCPSUS

VCCSUS3_3[05]

VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]

VCCPUSB

VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]

VCCDMIPLL

VCC_DMI[1]

VCC_DMI[2]

V_CPU_IO[1]
V_CPU_IO[2]

VCC3_3[01]
VCC3_3[02]
VCC3_3[07]

VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]

VCCHDA

VCCSUSHDA

VCCCL1_05

VCCCL1_5

VCCCL3_3[1]
VCCCL3_3[2]

1

C518

2

+3VS

0.1U_0402_16V4Z

1

2

T75
T76

0.1U_0402_16V4Z

+3VALW

+3VS

3

1

C521 0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

0.01U_0402_16V7K

1

C519

C522 10U_0805_6.3V6M

2

C524 10U_0805_10V4Z

C531

1

C536

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

R408
0_0402_5%

GM@

+3VALW

1

1

C546

C547

0.1U_0402_16V4Z

2

2

1

C549

4.7U_0603_6.3V6K

2

T79

1

C552
1U_0603_10V4Z@

2

2007/10/15 2008/10/15

3

R402

1 2

CHB1608U301_0603

1

2

+VCCP

1

2

+3VS

1

C529

0.1U_0402_16V4Z

2

1

C540

2

12

(SATA)

1

C537

0.1U_0402_16V4Z

2

1 2

R409
0_0402_5%

PM@

1

C545

4.7U_0603_6.3V6M

2

Compal Secret Data

+1.5VS

+3VS

(DMI)

1

C525

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z
C539

2

+3VALW

Deciphered Date

+3VS

1

2

+VCCP

A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29
W23

Y23
AB23

AC23
AG29

AJ6
AC10

AD19
AF20
AG24
AC20

B9
F9
G3
G6
J2
J7
K7

AJ4
AJ3

AC8
F17

VCCSUS1_5_ICH_1

AD8

VCCSUS1_5_ICH_2

F18

A18
D16
D17
E22

AF1

T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7

G22
G23

A24
B24

KIWB3/B4_LA4551P

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+VCCP

4.7U_0603_6.3V6M
C526

1

2

C538

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

2

R405

PM@

0_0402_5%

2

C527

1

U21E

AA26

VSS[001]

AA27

VSS[002]

AA3

VSS[003]

AA6

VSS[004]

AB1

VSS[005]

AA23

VSS[006]

AB28

VSS[007]

AB29

VSS[008]

AB4

VSS[009]

AB5

VSS[010]

AC17

VSS[011]

AC26

VSS[012]

AC27

VSS[013]

AC3

VSS[014]

AD1

VSS[015]

AD10

VSS[016]

AD12

VSS[017]

AD13

VSS[018]

AD14

VSS[019]

AD17

VSS[020]

AD18

VSS[021]

AD21

VSS[022]

AD28

VSS[023]

AD29

VSS[024]

AD4

VSS[025]

AD5

VSS[026]

AD6

VSS[027]

AD7

VSS[028]

AD9

VSS[029]

AE12

VSS[030]

AE13

VSS[031]

AE14

VSS[032]

AE16

VSS[033]

AE17

VSS[034]

AE2

VSS[035]

0.1U_0402_16V4Z
C528

1

2

+1.5VS+3VS

R406
0_0402_5%

GM@

1 2

1 2

AE20

VSS[036]

AE24

VSS[037]

AE3

VSS[038]

AE4

VSS[039]

AE6

VSS[040]

AE9

VSS[041]

AF13

VSS[042]

AF16

VSS[043]

AF18

VSS[044]

AF22

VSS[045]

AH26

VSS[046]

AF26

VSS[047]

AF27

VSS[048]

AF5

VSS[049]

AF7

VSS[050]

AF9

VSS[051]

AG13

VSS[052]

AG16

VSS[053]

AG18

VSS[054]

AG20

VSS[055]

AG23

VSS[056]

AG3

VSS[057]

AG6

VSS[058]

AG9

VSS[059]

AH12

VSS[060]

AH14

VSS[061]

AH17

VSS[062]

AH19

VSS[063]

AH2

VSS[064]

AH22

VSS[065]

AH25

VSS[066]

AH28

VSS[067]

AH5

VSS[068]

AH8

VSS[069]

AJ12

VSS[070]

AJ14

VSS[071]

AJ17

VSS[072]

AJ8

VSS[073]

B11

VSS[074]

B14

VSS[075]

B17

VSS[076]

B2

VSS[077]

B20

VSS[078]

B23

VSS[079]

B5

VSS[080]

B8

VSS[081]

C26

VSS[082]

C27

VSS[083]

E11

VSS[084]

E14

VSS[085]

E18

VSS[086]

E2

VSS[087]

E21

VSS[088]

E24

VSS[089]

E5

VSS[090]

E8

VSS[091]

F16

VSS[092]

F28

VSS[093]

F29

VSS[094]

G12

VSS[095]

G14

VSS[096]

G18

VSS[097]

G21

VSS[098]

G24

VSS[099]

G26

VSS[100]

G27

VSS[101]

G8

VSS[102]

H2

VSS[103]

H23

VSS[104]

H28

VSS[105]

H29

VSS[106]

ICH9-M ES_FCBGA676

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

ICH9M(4/4)-P OWER&GND

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

JITR1_LA-4141P

VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]

1

H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

0.1

of

30 52Thursd a y, June 26, 2008

CyberForum.ru

A

Mini-Express Card for 3G Or TV Tuner

Mini-Express Card for WLAN

Mini-Express Card(Slot 1-TV TUNNER) 4.0mm high

ICH_PCIE_WAKE#<29,32>

BT_ACTIVE<41>
WLAN_ACTIVE<41>

WLAN_CLKREQ#<23>

1 1

EC_TX_P80_DATA<38,39>
EC_RX_P80_CLK<38,39>

Vcc 3.3V +/- 8%
Peak Icc 2750mA
with max supply droop 50mA
Average Icc 10 00mA

Mini-Express Card(Slot 2-WIRELESS) 5.6mm high

2 2

ICH_PCIE_WAKE#<29,32>

WLAN_CLKREQ1#<23>

EC_TX_P80_DATA<38,39>
EC_RX_P80_CLK<38,39>

2005/09/27 modified.
Base on OPTION GTM351E Datasheet Rev0.1

Vcc 3.3V +/- 8%
Peak Icc 2750mA

3 3

with max supply droop 50mA
Average Icc 10 00mA

ICH_PCIE_WAKE#
BT_ACTIVE
WLAN_ACTIVE
WLAN_CLKREQ#

CLK_PCIE_WLAN#<23>

CLK_PCIE_WLAN<23>

PCIE_RXN5<29>
PCIE_RXP5<29>

PCIE_TXN5<29>
PCIE_TXP5<29>

EC_TX_P80_DATA
EC_RX_P80_CLK

ICH_PCIE_WAKE#
BT_ACTIVE
WLAN_ACTIVE
WLAN_CLKREQ1#

CLK_PCIE_WLAN 1#<23>

CLK_PCIE_WLAN1<23>

PCIE_RXN3<29>
PCIE_RXP3<29>

PCIE_TXN3<29>
PCIE_TXP3<29>

EC_TX_P80_DATA
EC_RX_P80_CLK

R413 0_0402_5%@

1 2

R412 0_0402_5%@

1 2

+3VS

100_0402_1%

R757

1 2
1 2

R756

100_0402_1%

2005/09/27 modified.
Base on OPTION GTM351E Datasheet Rev0.1

R428 0_0402_5%@

1 2

R429 0_0402_5%@

1 2

+3VS

100_0402_1%

R436

1 2
1 2

R755

100_0402_1%

Express Card Power Switch

+1.5VS

1

C567

0.1U_0402_16V4Z

2

+3VS

1

C570

0.1U_0402_16V4Z

2

+3VALW

1

C573

0.1U_0402_16V4Z

2

4 4

+3VALW

PLT_RST#<8,16, 27,32>

R438 100K_0402_5%@

1 2

+1.5VS

+3VS

+3VALW

PLT_RST#

SYSON<38,43,48,49>
SUSP#<38,43,48,49>

CPUSB#<29>

SYSON
SUSP#

CPUSB#

JP5

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

FOX_AS0B226-S40N-7F

ME@

JP7

1

WAKE#

3

NC

5

NC

7

CLKREQ#

9

GND

11

REFCLK-

13

REFCLK+

15

GND

17

NC

19

NC

21

GND

23

PERn0

25

PERp0

27

GND

29

GND

31

PETn0

33

PETp0

35

GND

37

NC

39

NC

41

NC

43

NC

45

NC

47

NC

49

NC

51

NC

53

GND

TAITW_PFPET0-AFGLBG1ZZ4N0

ME@

U22

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin
AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

R5538_QFN20

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND2

PERST#

+3.3Vaux

+1.5V

SMB_CLK

SMB_DATA

USB_D-

USB_D+

LED_WWAN#

LED_WLAN#
LED_WPAN#

+1.5V
+3.3V

1.5Vout

1.5Vout

3.3Vout

3.3Vout

OC#

PERST#

NC

GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

3.3V
GND

1.5V
NC
NC
NC
NC
NC

GND

NC

GND

GND

GND

GND

GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

+1.5VS_CARD1

11
13

+3VS_CARD1

3
5

+3VALW_CARD1

15
19

PERST#

8
16
7

B

+3VS

+1.5VS

R418 0_0402_5%@

1 2

R415 0_0402_5%

1 2

R416 0_0402_5%@

1 2

R417 0_0402_5%@

1 2

R421 0_0402_5%@

1 2

R423 0_0402_5%@

1 2

+3VS

+1.5VS

R430 0_0402_5%@
R431 0_0402_5%

R432 0_0402_5%@
R433 0_0402_5%@

R434 0_0402_5%@
R435 0_0402_5%@

40mil

60mil

40mil

2Watt

1 2
1 2

1 2
1 2

1 2
1 2

@

+1.5VS_CARD1

1

C565
10U_0805_10V4Z

2

+3VS_CARD1

1

C568
10U_0805_10V4Z

2

+3VALW_CARD1

1

@

C571
10U_0805_10V4Z

2

+1.5VS

1

C559

4.7U_0805_10V4Z

2

WL_OFF#

+3VALW
+3VS

ICH_SMBCLK <23,29>
ICH_SMBDATA <23,29>

USB20_N9 <29>
USB20_P9 <29>

+3VALW

1

C835

0.1U_0402_16V4Z

2

R760300_0402_5%

12

R761300_0402_5%

12

Imax = 0.75A

1

C566

0.1U_0402_16V4Z

2

Imax = 1.35A

1

C569

0.1U_0402_16V4Z

2

Imax = 0.275A

1

C572

0.1U_0402_16V4Z

2

+3VS

1

C557

4.7U_0805_10V4Z

2

3G_OFF# <38>

WL_O FF# <38>

PLT_RST# <8,16,27,32>

3G_OFF# <38>
WL_O FF# <38>

PLT_RST# <8,16,27,32>
+3VALW
+3VS

ICH_SMBCLK <23,29>
ICH_SMBDATA <23,29>

USB20_N8 <29>
USB20_P8 <29>

WLAN_LED#

C

+3VS

1

C562

0.1U_0402_16V4Z

2

1

C558

0.1U_0402_16V4Z

2

+1.5VS

1

C560

0.1U_0402_16V4Z

2

1

C561

0.1U_0402_16V4Z

2

Mini-Express Card(Slot 3-WWAN 3G) 5.6mm high

WLAN_LED# <42>

ICH_PCIE_WAKE#<29,32>

WLAN_CLKREQ2#<23>

EC_TX_P80_DATA<38,39>
EC_RX_P80_CLK<38,39>

Vcc 3.3V +/- 8%
Peak Icc 2750mA
with max supply droop 50mA
Average Icc 10 00mA

UIM_VPP
UIM_DATA

+UIM_PWR

CLK_PCIE_WLAN2#<23>

ICH_PCIE_WAKE#
BT_ACTIVE
WLAN_ACTIVE
WLAN_CLKREQ2#

CLK_PCIE_WLAN2<23>

PCIE_RXN1<29>
PCIE_RXP1<29>

PCIE_TXN1<29>
PCIE_TXP1<29>

EC_TX_P80_DATA
EC_RX_P80_CLK

R437

10K_0402_5%

R414 0_0402_5%@

1 2

R419 0_0402_5%@

1 2

+3VS

100_0402_1%

R758

1 2
1 2

R759

100_0402_1%

D21

@

CM1293-04SO_SOT23-6

1

CH1

2

Vn

3

CH2

JP8

4

GND

5

VPP

6

I/O

7

DET

12

TAITW_PMPAT6-06GLBS7N14N0 ME@

4

CH4

5

Vp

6

CH3

VCC

RST
CLK

GND
GND

New Card 34mm Socket (Left/TOP)

USB20_N10<29>

USB20_P10<29>

ICH_SMBCLK<23,29>

ICH_SMBDATA<23,29>

+1.5VS_CARD1

ICH_PCIE_WAKE#<29,32>

+3VALW_CARD1

+3VS_CARD1

EXP_CLKREQ#<23>

CLK_PCIE_EXP#<23>
CLK_PCIE_EXP<23>

PCIE_RXN4<29>
PCIE_RXP4<29>

PCIE_TXN4<29>
PCIE_TXP4<29>

1
2
3

8
9

CPUSB#

D

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

CPUSB#

PERST#

JP6

WAKE#
NC
NC
CLKREQ#
GND
REFCLK­REFCLK+
GND
NC
NC
GND
PERn0
PERp0
GND
GND
PETn0
PETp0
GND
NC
NC
NC
NC
NC
NC
NC
NC

GND

ME@

2

3.3V

4

GND

6

1.5V

8

NC

10

NC

12

NC

14

NC

16

NC

18

GND

20

NC

22

PERST#

24

+3.3Vaux

26

GND

28

+1.5V

30

SMB_CLK

32

SMB_DATA

34

GND

36

USB_D-

38

USB_D+

40

GND

42

LED_WWAN#

44

LED_WLAN#

46

LED_WPAN#

48

+1.5V

50

GND

52

+3.3V

54

GND

TAITW_PFPET0-AFGLBG1ZZ4N0

+3VS

40mil

+UIM_PWR
UIM_RST
UIM_CLK

1

1

C563

2

2

4.7U_0805_10V4Z

JEXP1

26

GND

25

USB_D-

24

USB_D+

23

CPUSB#

22

RSV

21

RSV

20

SMB_CLK

19

SMB_DATA

18

+1.5V

17

+1.5V

16

WAKE#

15

+3.3VAUX

14

PERST#

13

+3.3V

12

+3.3V

11

CLKREQ#

10

CPPE#

9

REFCLK-

8

REFCLK+

7

GND

6

PERn0

5

PERp0

4

GND

3

PETn0

2

PETp0

1

GND

27

GND1

28

GND2

SANTA_130832- 1_RV

+3VS

+1.5VS

2Watt

+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

R420 0_0402_5%

1 2

R422 0_0402_5%@

1 2

R424 0_0402_5%@

1 2

R425 0_0402_5%@

1 2

R426 0_0402_5%@

1 2

R427 0_0402_5%@

1 2

WIMAX_LED#

+3VS

D22

@

2

1

3

DAN217T146_SC59-3

C564

0.1U_0402_16V4Z

update symbol 6/26

E

+3VALW
+3VS

ICH_SMBCLK <23,29>
ICH_SMBD ATA <23,29>

USB20_N3 <29>
USB20_P3 <29>

WIMAX_LED# <42>

3G_OF F# <38>
WL_OF F# <38>
PLT_RST# <8,16,27,32>

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAI NS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

C

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Mini-Card/3G/FeliCa/BT

Size Docu me n t N u m ber Re v

Date: Sheet

JITR1_LA-4141P

E

of

31 52Monday, J une 30, 2008

0.1

CyberForum.ru

5

+3VALW

L29

1 2

+5VALW

12

R439
33K_0402_5%

13

D D

+3V_LAN

12

FBM-L11-160808-601LMT_0603

C C

FBM-L11-160808-601LMT_0603

+1.2V_LAN

B B

Layout Notice : Filter place as close
chip as possible.

A A

EN_WOL<38>

+2.5V12_LAN

R440
0_0805_5%

GIGA@

L30

1 2

FBM-L11-160808-601LMT_0603

L31

1 2

L32

1 2

L33

1 2

FBM-L11-160808-601LMT_0603

L34

1 2

FBM-L11-160808-601LMT_0603

L35

1 2

FBM-L11-160808-601LMT_0603

L36

1 2

FBM-L11-160808-601LMT_0603

EN_WOL

12

R441
0_0805_5%

100@

1

C586

0.1U_0402_16V4Z

2

2

C587

0.1U_0402_16V4Z

1

1

C589

2

0.047U_0402_16V4Z

1

C592
1U_0603_10V4Z

2

1

C594

4.7U_0805_10V4Z

2

1

C598

4.7U_0805_10V4Z

2

1

C600
1U_0603_10V4Z

2

Notice : 4.7u 6.3V capactor Thickness 1.25mm

5

2

G

+LAN_BIASVDD

+XTALVDD

1

C590

2

0.047U_0402_16V4Z

1

C593

0.1U_0402_16V4Z

2

1

C595

0.1U_0402_16V4Z

2

1

C599

0.1U_0402_16V4Z

2

1

C601

0.1U_0402_16V4Z

2

D

Q34
2N7002_SOT23

S

+AVDDL

+GPHY_PLLVDD

+PCIE_PLLVDD

+PCIE_VDD

FBM-L11-321611-260-LMT_1206@

D

S

1 3

Q33

G

2

AO3414_SOT23-3

1

C585

0.1U_0603_25V7K

2

+LAN_AVDD

1

C591

2

0.01U_0402_16V7K

4

2

C581
10U_0805_10V4Z

1

2

C582

0.1U_0402_16V4Z

1

1

C583

0.1U_0402_16V4Z

2

Layout Notice : Place as close chip as possible.

R444 0_0402_5%GIGA@

+2.5V12_LAN

+1.2V_LAN

+GPHY_PLLVDD

PCIE_IRX_PT X_P6<29>
PCIE_IRX_PTX_N6<29>
PCIE_ITX_C_PRX_P6<29>
PCIE_ITX_C_PRX_N6<29>

ICH_PCIE_WAKE#<29,31>
LAN_WAKE#<38>

PLT_RST#<8,16,27,31>

4

C596 0.1U_0402_16V7K
C597 0.1U_0402_16V7K

R462 0_0402_5%@

CLK_PCIE_LAN<23>

CLK_PCIE_LAN#<23>

PLT_RST#

+3V_LAN

CLKREQ_LAN#<23>

R477 200_0402_1%

1 2

Y4

1 2

1

25MHZ_20P

C604
27P_0402_50V8J

2

1 2

R442 0_0402_5%100@

1 2

+AVDDL

+PCIE_PLLVDD

+PCIE_VDD

1 2

R467 1 K _0402_5%

1 2

R468 1 K _0402_5%

1 2

R469 0_0402_5%@

1 2

R470 47K_0402_5%GIGA@

1 2

R472 47K_0402_5%GIGA@

1 2

R473 1 K _0402_5%

1 2

100@

R474 1.24K_0402_1%

1 2

GIGA@

1

C605

27P_0402_50V8J

2

R450 0_0402_5%GIGA@
R451 0_0402_5%100@

1 2

R456 0_0402_5%GIGA@

1 2

R457 0_0402_5%100@

XTALO
XTALI

+3V_LAN

1

C584
1U_0603_10V4Z

2

1 2

12

PCIE_IRX_C_PTX_P6
PCIE_IRX_C_P TX_N6

XTALO
XTALI

U24

5

VDDC_IO

55

VDDC_IO

13

VDDC

20

VDDC

34

VDDC

60

VDDC

39

AVDDL

45

AVDDL

51

AVDDL

35

GPHY_PLLVDDL

30

PCIE_PLLVDDL

27

PCIE_PLLVDDL

33

PCIE_VDDL

24

PCIE_VDDL

26

PCIE_TXD_P

25

PCIE_TXD_N

31

PCIE_RXD_P

32

PCIE_RXD_N

12

WAKE#

10

PERST#

29

PCIE_REFCLK_P

28

PCIE_REFCLK_N

54

VAUX_PRSNT

53

VMAIN_PRSNT

3

LOW_PWR

58

TEST1

57

TEST2

22

XTALO

21

XTALI

37

RDAC

11

CLK_REQ#

3

+1.2V_LAN

1

C574

4.7U_0805_10V4Z

2

2

1

C575

0.1U_0402_16V4Z

2

Layout Notice : 1.2V filter. Place as close chip as possible.

+2.5V12_LAN

+3V_LAN

61

15

19

VDDIO6VDDIO56VDDIO

VDDIO

VDDIO

69

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

3

12

R772
0_0402_5%

100@

38

68

52

DC

DC

DC

GPIO1_SERIALDI

GPIO0_SERIALDO

GND

36

BIASVDDH

23

XTALVDDH

48

AVDDH

42

AVDDH

49

TRD3_N

50

TRD3_P

47

TRD2_N

46

TRD2_P

43

TRD1_N

44

TRD1_P

41

TRD0_N

40

TRD0_P

2

LINKLED#

1

SPD100LED#

67

SPD1000LED#

66

TRAFFICLED#

8

GPIO2

9

UART_MODE

7
4

65

SCLK_EECLK

63

SI

64

SO_EEDATA

62

CS#

59

ENERGY_DET

+2.5V12_LAN

17

VDDC_IO

18

REGOUT12_IO

14

REGCTL12

16

SUPER_IDDQ

BCM5784MKMLG B0_QFN 68_10X10

2008/03/25 2008/04/

+LAN_BIASVDD

+XTALVDD

+LAN_AVDD

LAN_AVDDH
AVDDH_LAN_TRD1N

LAN_TX3­LAN_TX3+

LAN_TX2­LAN_TX2+

LAN_TRD1N_TRD1P
LAN_RX1+

LAN_TX0­LAN_TX0+

1 2

R452 0_0402_5%

1 2

R453 0_0402_5%100@

1 2

R454 0_0402_5%GIGA@

1 2

R455 0_0402_5%100@

GPIO2

R458 4.7K_0402_5%@

1 2

R459 0_0402_5%@

LAN_WP

LAN_CLK
SI
LAN_DATA
CS#

R466 0_0402_5%@

Compal Secret Data

1 2

R460 0_0402_5%

1 2

R461 0_0402_5%

GIGA@

1 2

GIGA@

R463 4.7K_0402_5%

1 2
1 2

R464 4.7K_0402_5%

1 2

R465 4.7K_0402_5%

1 2

R471 0_0402_5%

1 2

GIGA@

CTL12

MMJT9435T1G_SOT223

12

R475

0_0402_5%

Deciphered Date

2

LAN_TX3- <33>
LAN_TX3+ <33>

LAN_TX2- <33>
LAN_TX2+ <33>

LAN_RX1+ <33>
LAN_TX0- <33>

LAN_TX0+ <33>

+3V_LAN

1

Q36

2 3
1

2

1

2

PCI_ CBE#3 <27>

CTL25

1

C602

0.1U_0402_16V4Z

2

4

C603
10U_0805_10V4Z

C576

0.1U_0402_16V4Z

+3V_LAN

LAN_WP
LAN_CLK

LAN_DATA

AVDDH_LAN_TRD1N

LAN_TRD1N_TRD1P

LINK LED# <33>

ACTIVITY# <33>

+3V_LAN

+1.2V_LAN

1

1

C577

0.1U_0402_16V4Z

2

12

R443

4.7K_0402_5%

1

C578

0.1U_0402_16V4Z

2

12

R445

4.7K_0402_5%

R446 0_0402_5%100@

1 2

R447 0_0402_5%GIGA@

1 2

R448 0_0402_5%100@

1 2

R449 0_0402_5%GIGA@

1 2

+2.5V12_LAN

0.1U_0402_16V4Z

Compal Electronics,Ltd.

Title

Broadcom LAN BCM5784M/5906M

Size Docu me n t N u m ber Re v

C

Date: Sheet

1

C579

0.1U_0402_16V4Z

2

C588 0.1U_0402_16V4Z

1 2

U23

8

VCC

7

WP

6

SCL

5

GND

SDA

AT24C02_SO8

LAN_RX1­LAN_AVDDH
LAN_RX1+
LAN_RX1-

+3V_LAN

41

Q35

MBT35200MT1G_TSOP6

3

256

10U_0805_10V4Z

1

1

C839

C840

2

2

KIWB1/B2_LA4601P

1

1

A0

2

A1

3

NC

4

LAN_RX1- <33>

LAN_RX1- <33>

1

C580

0.1U_0402_16V4Z

2

32 52Monday, June 30, 2008

of

0.1

CyberForum.ru

5

+2.5V12_LAN

C606 0.1U_0402_16V4Z

1 2

C607 0.1U_0402_16V4Z

1 2

C608 0.1U_0402_16V4Z

D D

1 2

C609 0.1U_0402_16V4Z

1 2

C611 0.1U_0402_16V4Z

1 2

12

100@

R478
0_0402_5%

LAN_TX3+<32>

LAN_TX3-<32>

LAN_TX2+<32>

LAN_TX2-<32>

LAN_RX1+<32>

LAN_RX1-<32>

LAN_TX0+<32>

LAN_TX0-<32>

LAN_TX3-

LAN_TX2+

LAN_TX2-

LAN_RX1+

LAN_RX1-

LAN_TX0+

LAN_TX0- MDO0-

Change C468,C470,C473,C474,C475,C476 from 0.01uF to 0.1uF

near LAN controller

LAN_RX1-

R485 49.9_0402_1%100@

LAN_RX1+

R486 49.9_0402_1%100@

C C

LAN_TX0-

LAN_TX0+

R487 49.9_0402_1%100@
R488 49.9_0402_1%100@

12
12

12
12

C613

1 2

C615

1 2

TCT

TCT

TCT

TCT

100@

0.1U_0402_16V4Z

100@

0.1U_0402_16V4Z

4

T80

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+
TD2-6MX2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

BOTH_GST5009-LF

MCT1
MX1+

MX1-

MCT2
MX2+

MCT3
MX3+

MX3-

MCT4
MX4+

MX4-

3

2

1

RJ11+RJ45 CONN

24

MDO3+LAN_TX3+

23

MDO3-

22

MCT1

21

MDO2+

20

MDO2-

19

MCT0

18

MDO1+

17

MDO1-

16

MCT1

15

MDO0+

14
13

R479 75_0402_5%

R480 75_0402_5%

R482 75_0402_5%

R483 75_0402_5%

12

12

12

12

RJ45_PRMCT0

JLAN

12

12

R481 330_0402_5%

MDO0+
MDO0­MDO1+
MDO2+
MDO2­MDO1­MDO3+
MDO3-

12

R484 330_0402_5%

1 2

C614

0.1U_0402_16V4Z

Amber LED-

11

Amber LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

Green LED-

9

Green LED+

FOX_JM36113-P2221-7F

<BOM Structure>

C616

16

SHLD4

15

SHLD3

14

SHLD2

13

SHLD1

2

2

1

C617

0.1U_0402_16V4Z

1

+3V_LAN

0.01U_0402_16V7K

+3V_LAN

C612

0.01U_0402_16V7K

C610

ACTIVITY#<32>

1

2

LINKLED#<32>

1

2

RJ45_PR

1000P_1206_2KV7K

B B

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

LAN CONTROLLER

KIWB1/B2_LA4601P

33 52Monday, June 30, 2008

1

0.1

of

CyberForum.ru

5

0513 : CARD_3V3 10

旁路電阻

0K change to 4.7u CAP==>
0521 : change C79 form 4.7u to 0.1u, add R47 100K ohm,
change C526 form 1u to 4.7u

D D

1 2

3V3_IN
RST#
MODE SEL
XTLO
XTLI

1 2

USB20_N7
USB20_P7

C618 0.1U_04 02_16V4Z

1
3
7

9
11
33

8
44
45
47
48

4

5
14

2
12

32

6
46

0_0402_5%

1 2

C619

1 2
1 2

1

@

2

1

C622

0.1U_0402_16V4Z

2

XDPWR_SDPW R _MSPW R

USB20_N7<29>

USB20_P7<29>

4.7U_0603_6.3V6K

R491 0_0603_5%@

+3VS

R492 0_0603_5%

+3VALW

keep supply 3.3V to 3V3_IN when S3

Vender suggesttion

C C

R495
100K_0402_5%

1 2

1

2

C623
1U_0402_6.3V4Z

RST#

R497

6.19K_0402_1%

4

R489 0_0402_5%

U25

AV_PLL
NC
NC
CARD_3V3
D3V3
D3V3

3V3_IN
RST#
MODE_SEL
XTLO
XTLI

DM
DP
GPIO0

RREF
DGND

DGND
AGND

AGND

RTS5158E-GR_LQFP48_7X7

R498

預留

12

VREG

MS_D4

XD_CLE_SP19
XD_CE#_SP18

XD_ALE_SP17

SD_DAT2/XD_RE#_SP16

SD_DAT3/XD_WE#_SP15

SD_DAT4/XD_WP#/MS_D7_SP13

XD_RDY_SP14

SD_DAT5/XD_D0/MS_D6_SP12

SD_CLK/XD_D1/MS_CLK_SP11

SD_DAT6/XD_D7/MS_D3_SP10

MS_INS#_SP9
SD_DAT7/XD_D2/MS_D2_SP8
SD_DAT0/XD_D6/MS_D0_SP7
SD_DAT1/XD_D3/MS_D1_SP6

XD_D5_SP5

XD_D4/SD_DAT1_SP4

SD_CD#_SP3

SD_WP_SP2

XD_CD#_SP1

XTAL_CTR

MS_D5

EEDO
EECS
EESK

SD_CMD

C621 1 U_0603_16V4Z

1 2

10
22
30

NC

43
42
41
40
39
38
37
35
34
31
29
28
27
26
25
23
21
20
19
18

EEDI

XTAL_CTR 3V3_IN

13
24

15
16
17
36

XDCLE
XDCE#

XDALE
SDDAT2_XDRE#
SDDAT3_XDWE#

XD_RDY
SDDAT4_XDWP#_MSD7
SDDAT5_XDD0_MSD6
SDCLK_XDD1_MSCLK
SDDAT6_XDD7_MSD3

MS_INS#
SDDAT7_XDD2_MSD2
SDDAT0_XDD6_MSD0
SDDAT1_XDD3_MSD1

XDD5_MSBS
XDD4_SDDAT1

SDCD
SDWP
XDCD

12

R496

0_0603_5%

SD_CMD

3

SDDAT4_XDWP#_MSD7
SDDAT1_XDD3_MSD1
SDDAT7_XDD2_MSD2

SDDAT6_XDD7_MSD3
SDDAT4_XDWP#_MSD7
SDDAT2_XDRE#
SDCD
SDWP

SDDAT5_XDD0_MSD6
XDD4_SDDAT1

SDDAT0_XDD6_MSD0 SDDAT0_XDD6_MSD0
SDDAT3_XDWE#

XDCE#
SDDAT2_XDRE#
SDCLK_XDD1_MSCLK
XDCLE
XDALE
XD_RDY
XDCD

R493

0_0402_5%

R494

12

12

0_0402_5%

R490

100K_0402_5%

MS-SCLK

SD-CLK

XDPWR_SDPWR _MSPW R

1

C620

0.1U_0402_16V4Z

2

1 2

2

33

8
9

24
27
30

1
2

32

6
7
5

34

3

4
37
38
10
36
35
39
40

JREAD1

xD-WP
xD-D3
xD-D2

MS-DATA3
SD-DAT4
SD-DAT2
SD-CD
SD-WP

xD-D0
xD-D5
xD-D4
xD-D6
xD-WE
xD-VCC
xD-D7
xD-CE
xD-RE
xD-D1
xD-CLE
xD-ALE
xD-R/B
xD-CD

TAITW_R015-A10-LM_NR

ME@

1

23

SD-DAT5

14

SD-DAT0

25

SD-CMD

29

SD-DAT3

12

SD-DAT1

26

MS-SCLK

13

MS-BS

22

MS-INS

28

MS-VCC

15

MS-DATA1

19

MS-DATA2

17

MS-DATA0

20

SD-CLK

18

SD-DAT6

16

SD-DAT7

21

SD-VCC

31

7IN1-GND

11

7IN1-GND

41

GND

42

GND

R663
33_0402_5%

@

1 2

C805
22P_0402_50V8J

@

MSCLK and SDCLK 
solution , ( 

SD_DAT1 RTS5

將 連接到

SDDAT5_XDD0_MSD6
SDDAT0_XDD6_MSD0

SD_CMD

SDDAT3_XDWE#

XDD4_SDDAT1

MS-SCLK

XDD5_MSBS

MS_INS#

SDDAT1_XDD3_MSD1XDD5_MSBS
SDDAT7_XDD2_MSD2

SD-CLK
SDDAT6_XDD7_MSD3SDDAT6_XDD7_MSD3
SDDAT7_XDD2_MSD2

R665
33_0402_5%

@

1 2

C807
22P_0402_50V8J

@

該二電

使用 但請靠

158E pin23

XDPWR_SDPW R _MSPW R

SD-CLKCLK_48M_CR MS-SCLK

R664
33_0402_5%

@

1 2

C806
22P_0402_50V8J

@

O EMI

　 預留給

TS5158E ).

醪側

的

B B

CLK_48M_CR

C625

47P_0402_50V8J

CLK_48M_CR<23>

MODE SEL

12

1

@

R500

10K_0402_5%

2

@

0521_C503 and R436 should be open

A A

5

R499 0_0603_5%

1 2

C624

1 2

6P_0402_50V8D

@

Y5
12MHZ_16P_6X12000012

@

C626

1 2

6P_0402_50V8D

@

4

XTLI

12

XTLO

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH OUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

1394+3 in 1 Card

LA-3691P

1

of

34 52Monday, June 30, 2008

1.0

CyberForum.ru

A

B

C

D

E

F

G

H

SATA HDD Conn.

JHDD

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12

GND

22

V12

GND

FOX_LD2122H-S43_NR

ME@

SATA ODD Conn.

JODD

1

SATA_ITX_DRX_P1<28>

SATA_DTX_C_IRX_N1<28>

SATA_DTX_C_IRX_P1<28>

23
24

CONN need change to new CONN

SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1 SATA_DTX_IRX_P1

SATA_ITX_DRX_N1<28>

C635 0.01U_0402_16V7K

1 2

C636 0.01U_0402_16V7K

1 2

SATA_ITX_DRX_P1
SATA_ITX_DRX_N1

SATA_DTX_IRX_N1

+5VS

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

DP

9

+5V

10

+5V

11

MD

12

GND

13

GND

OCTEK_SLS-13SB1G_RV

ME@

1

C631
10U_0805_10V4Z

2

SATA_ITX_DRX_P0
SATA_ITX_DRX_N0

SATA_DTX_IRX_N0
SATA_DTX_IRX_P0

+3VS

+5VS

1

@

C632

0.1U_0402_16V4Z

2

SATA_ITX_DRX_P0<28>

SATA_DTX_C_IRX_N0<28>

1 1

SATA_DTX_C_IRX_P0<28>

+5VS +3VS

1

C627
1000P_0402_50V7K

2

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0

1

C628

0.1U_0402_16V4Z

2

1

C629
1U_0603_10V4Z

2

SATA_ITX_DRX_N0<28>

C634 0.01U_0402_16V7K

1 2

C633 0.01U_0402_16V7K

1 2

1

C630
10U_0805_10V4Z

2

2 2

+USB_VCCB

+USB_VCCB

1

+

C733
150U_D2_6.3VM

2

SATA_ITX_DRX_P4_CONN<28>

3 3

C732 0.1U_0402_16V4Z

4 4

A

SATA_ITX_DRX_N4_CONN<28>

SATA_DTX_IRX_N4_CONN<28>

SATA_DTX_IRX_P4_CONN<28>

+5VALW

U34

1

GND

2

IN

12

USB_ON<38,41>

USB_ON

3

IN

4

EN

G545A1P1U_SO8

B

W=80mils

1

C734
470P_0402_50V7K

2

USB20_N0<29>
USB20_P0<29>

SATA_ITX_DRX_P4_CONN
SATA_ITX_DRX_N4_CONN

SATA_DTX_IRX_N4_CONN
SATA_DTX_IRX_P4_CONN

+USB_VCCB

8

OUT

7

OUT

6

OUT

5

OC#

ESATA and USB Conn.

JESATA

1

VBUS

2

D-

3

D+

4

GND

5

GND

6

A+

7

A-

8

GND

9

B-

10

B+

11

GND

12

GND

13

GND

14

GND

15

GND

TYCO_1759576-1

ME@

1

2

C735

1000P_0402_50V7K@

USB20_N0
USB20_P0

USB_OC#0 <29>

C

ESATA

USB

+1.8V

+1.8V

OUTPUT SWING CONTROL OUTPUT DE-EMPHASIS ADJUSTMENT

SEL2_[A:B] SWING

0

1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BYOR DISCLOSEDTO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2007/10/15 2008/10/15

1 2

R747 0_0402_5%@

1 2

R746 0_0402_5%@

1 2

R745 0_0402_5%@

1 2

R744 0_0402_5%@

1 2

R743 0_0402_5%@

1 2

R742 0_0402_5%@

1 2

R741 0_0402_5%@

1 2

R740 0_0402_5%@

1 2

R739 0_0402_5%@

1 2

R738 0_0402_5%@

1 2

R737 0_0402_5%@

1 2

R752 0_0402_5%@

1 2

R753 0_0402_5%@

1.2X

E

SATA_ITX_DRX_P4_CONN

SATA_ITX_DRX_N4_CONN

SATA_DTX_IRX_P4_CONN

SATA_DTX_IRX_N4_CONN

SEL3_[A:B] DE-EMPHASIS

1X

Compal Secret Data

Deciphered Date

U42

2

AI+

3

AI-

7

BO+

8

BO-

34

SEL0_A

13

SEL0_B

33

SEL1_A

14

SEL1_B

32

SEL2_A

15

SEL2_B

31

SEL3_A

16

SEL3_B

30

EN_A

29

EN_B

19

IREF

11

CLKIN+

12

CLKIN-

PI2EQX3201BZFEX_TQFN36_6X5

@

0

1

F

9dB

-3.5dB

+1.8V

1
6
10
23
28
5

SATA_DTX_IRX_P4_A0+

SATA_DTX_IRX_P4_A0-

27
26

SATA_DTX_IRX_P4_B1-

21

SATA_DTX_IRX_P4_B1+

22

17
18

36
35

25
20
9
4
24

37

1

2

R751 0_0402_5%@
R750 0_0402_5%@

R749 0_0402_5%@
R748 0_0402_5%@

1

C663
1000P_0402_50V7K

2

@

VDD
VDD
VDD
VDD
VDD

AVDD

AO+

AO-

BI-

BI+

OUT+

OUT­SD_A

SD_B

GND
GND
GND
GND

AGND

PAD

EQUALIZER SELECTION

SEL3_[A:B] DE-EMPHASIS

0

1

1

Title

Size Document Number Rev

B

Date: Sheet

0.01U_0402_16V7K

1 2
1 2

1 2
1 2

1

C661
1U_0603_10V4Z

2

@

@

C828

1 2

C829

1 2

C822

1 2

C823

1 2

0.01U_0402_16V7K @

C657

0.1U_0402_16V4Z

@

0

1

0

11

Compal Electronics, Inc.

HDD & ODD Connector

KIWB1/B2_LA4601P

G

1

C654
10U_0805_10V4Z

2

@

SATA_ITX_DRX_P4_CONN
SATA_ITX_DRX_N4_CONN

0.01U_0402_16V7K@

0.01U_0402_16V7K@

SATA_DTX_IRX_N4_CONN
SATA_DTX_IRX_P4_CONN

COMPLIANCE CHANNEL

NO EQUALIZATION

[0:2.2.5dB]@1.6GHz

[2.5:4.5dB]@1.6GHz

[4.5:6.5dB]@1.6GHz

35 52Monday, June 30, 2008

H

1

C656
10U_0805_10V4Z

2

@

of

0.1

CyberForum.ru

5

+5VS

R503 MB V2012301Y ZF _0805

10U_0805_10V4Z

D D

12

C640

1

1

2

2

Adjustable Output

U26

1

IN

2

GND

3

SHDN

G9191-475T1U_SOT23-5

C641

0.1U_0402_16V4Z

+5VDDA_CODEC

5

OUT

4

BYP

1

1

C643

C642

2

2

4.7U_0805_10V4Z

0.01U_0402_16V7K

4

HDA_RST_CODEC#
HDA_SYNC_CODEC
HDA_SDOUT_CODEC

1

1

C819

C820

2

2

@

@

22P_0402_50V8J

22P_0402_50V8J

1

1

C808

C821

2

2

@

@

22P_0402_50V8J

22P_0402_50V8J

BITCLK

3

EMI

R502

1 2

MBV2012301YZF_0805

C637

1

2

0.1U_0402_16V4Z

C638

1

2

10U_0805_10V4Z

2

+5VDDA_CODEC+3VS +3VDD_CODEC

1

1

C816

C648

2

2

10U_0805_10V4Z

0.1U_0402_16V4Z

C649

1

1

2

0.1U_0402_16V4Z

Place near Pin25 Place near Pin38Place near Pin1

+MIC2_VREFO

21

D31
RB751V_SOD323

12

R509

4.7K_0402_5%

MIC1

1

GNDA

2

WM-64PCY_2P

45@

C C

MIC4

1
2

WM-64PCY_2P

45@

GNDA

1

C655
47P_0402_50V8J

2

GNDA

1

C660
47P_0402_50V8J

2

ARRAY@

GNDA

ARRAY@

12

R5130_0603_5%

+MIC2_VREFO

21

12

R518

12

R5200_0603_5%

INT_MIC_L

D32
RB751V_SOD323

ARRAY@

4.7K_0402_5%

ARRAY@

INT_MIC_R

R731

1 2

R732

1 2

R733

1 2

Internal MIC / Array MIC

0_0402_5%

0_0402_5%

0_0402_5%

4.7K_0402_5%

EXT_MIC_L<37>

EXT_MIC_R<37>

external MIC

+MIC1_VREFO_L

12

12

R535

R533

4.7K_0402_5%

INT_MIC_L

INT_MIC_R

MIC Sense
R516 place near pin13
Capless HP Sense
R517 place near pin34

1 2
1 2

R7011K _0402_5%
R7021K _0402_5%

ARRAY@

MIC_JD<37>

PLUG_IN<37>

HDA_BITCLK_CODEC<8, 18,28>
HDA_SDOUT_CODEC<8,18,28>

HDA_RST_CODEC#<8,18,28>
HDA_SYNC_CODEC< 8,18,28>

1 2
1 2

MIC_INTL MIC_INTR

2.2U_0603_16V6K

2.2U_0603_16V6K

EAPD<38>

MIC_INTL

R7031K _0402_5%

MIC_INTR

R7041K _0402_5%

HDA_SDIN2<28>

1 2

R734 0_0402_5%MONO@

C651

12

C650

12

C6522.2U_0603_16V6K

12

C6532.2U_0603_16V6K

12

1 2

R705 22_0402_5%

HDA_SDOUT_CODEC

1 2

R706 22_0402_5%

HDA_RST_CODEC#
HDA_SYNC_CODEC

12

R51620K_0402_5%

12

R5175.1K_0402_1%

1 2

R7620_0402_5%

MIC_INL
MIC_INR

MIC_EXTL_C
MIC_EXTR_C

SENSEA
SENSEB

GNDAGND

Pin Assignment

LINE-OUT (Pin35/36)

B B

Capless HP-OUT (Pin32/33)

LINE1 (Pin23/24)

MIC1(Pin21/22)

MONO-OUT(Pin37)

MIC2(Pin16/17)

PC Beep

EC Beep

A A

BEEP#<38>

0.1U_0402_16V4Z@

SB_SPKR<29>

ICH Beep

C666

12

1

1U_0603_10V4Z

C667

2

C668

12

1U_0603_10V4Z

5

Location Function

Internal

External

External

External

Internal

Internal

R524

560_0402_5%

R531

560_0402_5%

R532

2

B

12

1 2

1 2

10K_0402_5%

+3VS

12

R521
10K_0402_1%

C662

12

12

1U_0603_10V4Z

R522
10K_0402_1%

1 2

R523 20K _0402_5%

1

C

Q37
2SC2411KT146_SOT23-3

E

3

D23

@

RB751V_SOD323

2 1

Int Speaker

Headphone out

Line in

Mic in

Internal Subwoofer

Internal Mic

C665 1U _0603_10V4Z

12

R527
20K_0402_5%

@

1 2

+5VAMP

W=40mil

1

1

C811

0.1U_0402_16V4Z

R709 0_0402_5%

LINE_OUTL
LINE_OUTR

PC_BEEPPC_BEEP1

4

R710

2

1 2
1 2

0_0402_5%

2

12

@

C812

4.7U_0805_10V4Z

12

R711

R712

10K_0402_5%

10K_0402_5%

@

GAIN0
GAIN1

LIN
RIN

1

C813

0.1U_0603_25V7K

2

3

U40

16

VDD

6

PVDD

15

PVDD

2

GAIN0

3

GAIN1

5

LIN-

17

RIN-

9

LIN+

7

RIN+

1

C815

0.1U_0603_25V7K

2

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEETMAY NOT BE TRANSFERED FROM TH E CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS, INC. NEITHER THIS SHE ET NOR THE INFORMAT ION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUTPRIOR WRITTENCONSENT OF COMPAL ELECTRONICS, INC.

+5VDDA_CODEC

U41

14
15
16
17
23
24
21
22

PC_BEEP

12

BITCLK

6
5

8
11
10

2

3
13
34
47
43

4

7

ALC272-GR_LQFP48

NC

SHUTDOWN

LOUT­ROUT­LOUT+

ROUT+

GND
GND
GND
GND
GND

BYPASS

TPA6017A2PWPR_TSS O P20

2008/03/25 2008/04/

+3VDD_CODEC

1

38

9

DVDD

AVDD125AVDD2
LINE2-L
LINE2-R
MIC2_L
MIC2_R
LINE1_L
LINE1_R
MIC1_L
MIC1_R

BEEP_IN

BITCLK
SDATA_OUT
SDATA_IN
RESET#
SYNC

GPIO0/DMIC_DATA1/2
GPIO1/DMIC_DATA3/4
SENSE A
SENSE B
EAPD
NC
DVSS

DVSS

12

19

8
14
4
18

1
11
13
20
21

10

DVDD_IO

LOUT1_L
LOUT1_R
LOUT2_L
LOUT2_R
SPDIFO1

SPDIFO2
HPOUT_L
HPOUT_R

MONO_OUT

DMIC_CLK1/2

DMIC_CLK3/4
LINE2_VREFO
LINE1_VREFO

MIC1_VREFO

MIC2_VREFO

CPVREF

VREF

JDREF

CBN
CBP

AVSS1
AVSS2

+3VALW

R707

10K_0402_5%

@

AMP_OFF# EC_MUTE#

1 2

R708

20mil

1

C814

4.7U_0805_10V4Z

2

Compal Secret Data

Deciphered Date

2

Place near Pin9

+IOVDD_CODEC

1

1

C842

C639

2

2

0.1U_0402_16V4Z

C_LINE_OUTL

35

C_LINE_OUTR

36
39
41
48
45
33
32

37

46
44
20
18
28
19
31
27
40
30
29

26
42

SPK_R2+

MONO_OUT

C659 2.2U_0603_10V6K

1 2

0_0402_5%

SPK_L1­SPK_R1­SPK_L2+

1 2

+MIC1_VREFO_L

+MIC2_VREFO

C658 2.2U_0603_10V6K

1 2

SPK_L1- <37>
SPK_R1- <37>
SPK_L2+ <37>
SPK_R2+ <37>

R778 0_0402_5%PM@

R777 0_0402_5%GM@

10U_0805_10V4Z

C645 0.1U_0603_25V7K

1 2

C646 0.1U_0603_25V7K

1 2

R7630_0402_5%

12

R51063.4_0402_1%

12

R51263.4_0402_1%

MONO_OUT <37>

1 2

EC_MUTE# <37,38>

C

Date: Sheet

1 2

1 2

LINE_OUTR

SPDIF_OUT <37>

HP_OUT L <37>
HP_OU TR <37>

12

R519
20K_0402_1%

Compal Electronics,Ltd.

Title

HD Audio Codec_ALC272

Size Docu me n t N u m ber Re v

+3VS

+1.5VS

LINE_OUTL

Internal Speaker

SPDIF

Headphone

add a 64 ohm serial resistor

2

1

C810

C809

1

2

10U_0805_10V4Z

0.1U_0402_16V4Z

Close Pin27

GAIN0 GAIN1

0 0 6dB
0 1 10dB
1 0 15.6dB
1 1 21.6dB

+5VAMP +5VAMP

R713

@

100K_0402_1%

1 2

R715

100K_0402_1%

1 2

KIWB1/B2_LA4601P

1

R714

100K_0402_1%

1 2

GAIN1GAIN0

R716

100K_0402_1%

@

1 2

36 52Monday, June 30, 2008

of

0.1

CyberForum.ru

5

4

3

2

1

Audio Jack

1

C67310P_0402_50V8J

@

2

GNDA

1 2

SPDIF_OUT

C676

EXT_MIC_L-2

C674

PL-OUT
PR-OUT

12

GNDAGNDA

220P_0402_50V7K

C675

1 2

Audio Jack

MIC IN

JMIC1

1
2

3
4
5

6

G

SINGA_2SJ-0960-C02

ME@

Headphone

JHP1

6
1

4
5
7

3
8

2

SINGA_2SJ1533-000111

D D

EXT_MIC_L<36>

EXT_MIC_L

SubWoofer Conn.

Speaker Connector

WOOFER-

SPK_R1-<36>
SPK_R2+<36>
SPK_L1-<36>
SPK_L2+<36>

C C

WOOFER+

R616 0_0603_5%
R617 0_0603_5%
R765 0_0603_5%
R766 0_0603_5%
R764 0_0603_5%
R767 0_0603_5%

12
12
12
12
12
12

20mil

WO­WO+
SPK_R1­SPK_R2+
SPK_L1­SPK_L2+

JSPK1

1

1

2

2

3

3

4

4

5

7

5

G1

6

8

6

G2

ACES_87213-0600G

EXT_MIC_R<36>

MIC_JD<36>

EXT_MIC_R

MIC_JD

1K_0402_5%

1 2

R534 0_0603_5%

1

C669

47P_0402_50V8J

2

GNDA

1 2

R536 0_0603_5%

1

C671

47P_0402_50V8J

2

GNDA

12

R537

@

GNDA

bead?

bead?

12

R538

@

1K_0402_5%

1

C670

@

10P_0402_50V8J

2

GNDA

EXT_MIC_R-2

1

C672

@

10P_0402_50V8J

2

GNDA

220P_0402_50V7K

bead?

HP_OUTL<36>
HP_OUTR<36>

PLUG_IN<36>

B B

HP_OUTL
HP_OUTR

PLUG_IN

+5VS

1

C677

0.1U_0402_16V4Z

2

1 2

R539 0_0603_5%

1 2

R540 0_0603_5%

SPDIF_OUT<36>

220P_0402_50V7K

33K_0402_5%

1 2

+5VAMP

WIN1

WIN2

R620

1500P_0402_50V7K

1 2

C762

W=40mil

U39

6

VDD

SHUTDOWN#

3

IN+

4

IN-

2

APA3011XA-TRL_MSOP8

BYPASS

GND

Vo+

1
5
8

Vo-

7

G1442 SubWoofer Amplifier

1nd = APA3011 (SA00001JM00)
2nd = TPA6211 (SA621110010 )

1U_0603_10V4Z

MONO_OUT<36>

A A

MONO_OUT

1 2

C759

18K_0402_5%

R618

1000P_0402_50V7K

1 2

C760
47K_0402_5%

1 2

R619

C761

2.2U_0603_6.3V4Z

2

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

WOOFER+
WOOFER-

+3VALW

ONLY FOR 15.6W

R621
10K_0402_5%

@

1 2

0_0402_5%

2008/03/25 2008/04/

3

EC_MUTE#AMP_OFF#

R622

12

EC_MUTE# <36,38>

Compal Secret Data

Deciphered Date

C763

0.1U_0402_16V4Z

+5VAMP

1

2

2

bead?

2

C764
10U_0805_10V4Z

1

+5VS

12

R6230_0603_5%

Compal Electronics,Ltd.

Title

AMP,Audio speaker CONN

Size D ocument Number Rev

Custom
Date: Sheet

KIWB1/B2_LA4601P

1

37 52Monday, June 30, 2008

of

0.1

CyberForum.ru

L38

+3VALW +EC_AVCC

+3VALW

LAN_WAKE#<32>

PCI_PME#<27>

+3VALW

+5VALW

+3VS

12

1

2

1 2

FBM-11-160808-601-T_0603

0.1U_0402_16V4Z

1 2

L39 FBM-11-160808-601-T_0603

12

C687 22P_0402_50V8J@

1 2

R543 47K_0402_5%

0.1U_0402_16V4Z

1 2

R551 0_0402_5%

1 2

R554 0_0402_5%@

S

+3VALW

1 2

R557 100K_0402_1%@

1 2

R558 100K_0402_1%@

1 2

R559 10K_0402_5%@

1 2

R560 4.7K_0402_5%

1 2

R561 4.7K_0402_5%

R562

4.7K_0402_5%

@

C694
100P_0402_50V8J

FRD#SPI_SO

FSEL#SPICS#

KSO17

EC_SMB_CK1

EC_SMB_DA1

12

R563

4.7K_0402_5%

EC_SMB_CK2
EC_SMB_DA2

1

@

C695
100P_0402_50V8J

2

2

C683

1

KB_RST#<28>

C686

D

13

@

G

2N7002_SOT23

2

1

C684

1000P_0402_50V7K

2

ECAGND

12

R541 10_0402_5%@

2

1

KSO[0..15]<39>

KSI[0..7]<39,42>

+3VALW

R550
10K_0402_5%

1 2

Q38

32.768KHZ_12.5P_1TJS125BJ2A251

0_0402_5%

1 2

@

2 1

RB751V_SOD323

EC_PME#

X1

2
3

C678

0.1U_0402_16V4Z

1

2

R779

D24

C693 15P_0402_50V8J

NC
NC

C696 15P_0402_50V8J

GATEA20<28>

LPC_FRAME#<28,39>

LPC_AD3<28,39>
LPC_AD2<28,39>
LPC_AD1<28,39>
LPC_AD0<28,39>

CLK_PCI_LPC<23>

PCI_RST#<27,39>

EC_SCI#<29>

PWR_LED_SC#<42>

KSO[0..15]
KSI[0..7]

EC_SMB_CK1<45>
EC_SMB_DA1<45>

EC_SMB_CK2<5,16,42>
EC_SMB_DA2<5,16,42>

SLP_S3#<29>
SLP_S5#<29>

EC_SMI#<29>

LID_SW#<39>

+3VALW

R552 4.7K_0402_5%

+3VALW

R553 4.7K_0402_5%

KILL_SW#<39>

FAN_SPEED1<5>

3G_OFF#<31>
EC_TX_P80_DATA<31,39>
EC_RX_P80_CLK<31,39>

ON/OFF#<42>

NUM_LED#<39>

12

1

IN

4

OUT

12

0.1U_0402_16V4Z

SERIRQ<29,39>

KSI3<39,42>
KSI4<39>

KSO16<42>

KSO17<42>

1 2
1 2

+3VALW

C685

C681

0.1U_0402_16V4Z

1

2

1
2
3
4
5
7
8

10
12

13
37
20
38

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

77
78
79
80

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

122
123

1000P_0402_50V7K

C682

1000P_0402_50V7K

1

1

2

2

U29

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1

LPC & MISC

LAD0
PCICLK

PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24

Int. K/B

KSO5/GPIO25

Matrix

KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

XCLK1
XCLK0

KB926QFA1_LQFP128

SM Bus

C680

0.1U_0402_16V4Z

C679

1

1

2

2

KB_RST#_EC

LPC_AD3
LPC_AD2
LPC_AD1 BATT_TEMP
LPC_AD0

EC_RST#

EC_SCI#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

KSO16
KSO17

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SMI#
LID_SW#

FAN_SPEED1

EC_TX_P80_DATA
EC_RX_P80_CLK

XCLKI
XCLKO

needed to update to D1 version

+EC_AVCC

9

22

33

96

111

125

VCC

VCC

VCC

VCC

VCC

VCC

PWM Output

AD Input

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

GPIO

GPO

GPIO

GPI

GND

GND

GND

GND

GND

11

24

35

94

113

67

AVCC

INVT_PWM/PWM1/GPIO0F

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

ACOFF/FANPWM2/GPIO13

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B

AD4/GPIO42

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

AGND

69

ECAGND

SA00001J550

XCLKO

12

@

R564
20M_0603_5%

XCLKI

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

INVT_PWM

SPICS#

GPXO10
GPXO11

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

21

BEEP#

23
26

ACOFF

27

63

BATT_OVP

64
65
66
75

TSATN#_EC

76

DAC_BRIG

68

EN_FAN1

70

IREF

71
72

83

USB_ON

84

IDEAPAD_LED#

85

TP_LOCK#

86

TP_CLK

87

TP_DATA

88

97
98
99
109

FRD#SPI_SO

119

FWR#SPI_SI

120

SPI_CLK

126

FSEL#SPICS#

128

RCIRRX

73

I2C_INT I2C_INT

74
89

CHARGE_LED0#

90

CAPS_LED#

91

CHARGE_LED1#

92
93

SYSON

95
121

ACIN

127

100

EC_LID_OUT#

101

EC_ON

102

MUTE_LED

103

ICH_POK_EC ICH_POK

104

BKOFF#

105
106
107

WIRELESS_LED#

108

110
112
114

EC_THERM#

115

SUSP#

116

PBTN_OUT#

117
118

124

1

2

R542 0_0603_5%@

1 2

C691
1U_0603_10V4Z

INVT_PWM <25>
BEEP# <36>
NOVO# <42>
ACOFF <46>

BATT_TEMP <45>

BATT_OVP <46>
ADP_I <46>

DAC_BRIG <25>
EN_FAN1 <5>
IREF <46>
CHGVADJ <46>

EC_MUTE#

EC_MUTE# <36,37>
USB_ON <35,41>
IDEAPAD_LED#

TP_LOCK# <40>

TP_CLK <39>

TP_DATA <39>

EN_WOL <32>
BATT_SEL_EC <46>
CMOS_OFF# <41>

FRD#SPI_SO <40>

FWR#SPI_SI <40>

FSEL#SPICS# <40>

RCIRRX <42>

I2C_INT <42>

FSTCHG <46>

CHARGE_LED0# <40>

CAPS_LED# <39>

CHARGE_LED1# <40>

PWR_LED# <40>

SYSON <31,43,48,49>
VR_ON <50>
ACIN <29,44>

EC_RSMRST# <29>
EC_LID_OUT# <29>
EC_ON <42>

MUTE_LED# <42>

BKOFF# <25>
WL_OFF# <31>
DDR3_SM_PWROK <8>
WIRELESS_LED# <40>

SLP_S4# <29>
ENBKL <25>

EAPD <36>

EC_THERM# <29>

SUSP# <31,43,48,49>
PBTN_OUT# <29>
BT_OFF# <41>

R548 4.7K_0402_5%@

1 2

SPI_CLK <40>

R546 10K_0402_5%@

D25 RB751V_SOD323

1 2

R555 0_0402_5%

ENE ISSUE CHANGE FROM 4.7uF TO 1uF
20080606

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

TSATN# <8>

1 2

USB_ON

R547 10K_0402_5%

21

@

SUSP#

1

2

+3VALW

1 2

KB926 SPI STRAP PIN

+3VS

12

R549
10K_0402_5%

ICH_POK <8,29>

1 2

R556 10K_0402_5%

@

C692
1000P_0402_50V7K

+3VS

+5VS

TP_CLK

R544 4.7K_0402_5%

TP_DATA
BATT_OVP
BATT_TEMP
ACIN

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

1 2

R545 4.7K_0402_5%

1 2

1 2

C688 100P_0402_50V8J

1 2

C689 100P_0402_50V8J

1 2

C690 100P_0402_50V8J

BIOS & EC I/O Port

JITR1_LA-4141P

of

38 52Monday, June 30, 2008

0.1

CyberForum.ru

5

4

3

2

1

INT_KBD Conn.

KSI[0..7]

D D

C C

KSO[0..15]

KSO2

C697 100P_0402_50V8J@

KSO15

C699 100P_0402_50V8J@

KSO6

C701 100P_0402_50V8J@

KSO8

C703 100P_0402_50V8J@

KSO13

C705 100P_0402_50V8J@

KSO12

C707 100P_0402_50V8J@

KSO11

C709 100P_0402_50V8J@

KSO10

C711 100P_0402_50V8J@

KSO3

C713 100P_0402_50V8J@

KSO4

C715 100P_0402_50V8J@

KSI0

C717 100P_0402_50V8J@

KSO0

C719 100P_0402_50V8J@

CONN PIN define need double check

To TP/B Conn.

TP_CLK<38>
TP_DATA<38>

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

KSI[0..7] <38,42>
KSO[0..15] <38>

1

@

C724
100P_0402_50V8J

2

+5VS

C723

0.1U_0402_16V4Z

1

@

C725
100P_0402_50V8J

2

KSO1
KSO7
KSI2
KSO5
KSI3
KSO14
KSI7
KSI6
KSI5
KSI4
KSO9
KSI1

TP_CLK
TP_DATA

C698 100P_0402_50V8J@

1 2

C700 100P_0402_50V8J@

1 2

C702 100P_0402_50V8J@

1 2

C704 100P_0402_50V8J@

1 2

C706 100P_0402_50V8J@

1 2

C708 100P_0402_50V8J@

1 2

C710 100P_0402_50V8J@

1 2

C712 100P_0402_50V8J@

1 2

C714 100P_0402_50V8J@

1 2

C716 100P_0402_50V8J@

1 2

C718 100P_0402_50V8J@

1 2

C720 100P_0402_50V8J@

1 2

JP15

1

1

2

2

3

3

4

4

E&T_6905-E04N-00R

ME@

+5VS

NUM_LED#<38>

CAPS_LED#<38>

12
12

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

R770300_0402_5%
R771300_0402_5%

ACES_85201-3005N

JP13

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

G1

32

G2

+3VALW

1 2

R565 0_0402_5%

Lid Switch

C721

0.1U_0402_16V4Z

+VCC_LID

1

2

EC_TX_P80_DATA<31,38>
EC_RX_P80_CLK<31,38>

R566 100K_0402_5%

2

A3212ELHLT-T_SOT23W-3

VDD

OUTPUT

GND

1

EC DEBUG PORT

+3VALW

EC_TX_P80_DATA
EC_RX_P80_CLK

1 2

3

U30

Kill Switch

JP14

1
2
3
4

ACES_85205-0400

ME@

2

C722

10P_0402_50V8J

1

1
2
3
4

LID_SW# <38>

CONN PIN define need double check

+3VALW

B B

KILL_SW#<38>

KILL_SW#

R632

100K_0402_5%

12

SW2

3

3

2

2

1

1

LSSM12-P-V-T-R_3P

FOR LPC SIO DEBUG PORT

JP16

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

A A

16

16

17

17

18

18

19

19

20

20

ACES_85201-2005

ME@

5

+5VS

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ0#
PCI_RST#

CLK_PCI_DB
SERIRQ

+3VS

CLK_14M_SIO <23>
LPC_AD0 <28,38>
LPC_AD1 <28,38>
LPC_AD2 <28,38>
LPC_AD3 <28,38>

LPC_FRAME# <28,38>
LPC_DRQ0# <28>
PCI_RST# <27,38>

CLK_PCI_DB <23>

SERIRQ <29,38>

R567 10K_0402_5%

12

@

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Deciphered Date

2

Title

Size D ocument Number Rev

B
Date: Sheet

Compal Electronics, Inc.

KB /SW /LPC Debug Conn.

KIWB1/B2_LA4601P

39 52Monday, June 30, 2008

1

of

0.1

CyberForum.ru

FOR EC 16M SPI ROM

FRD#SPI_SO<38>

INPUT
AB
LL
HL
LH
HH

FRD#SPI_SO SPI_SO

R568 15_0402_5%

1 2

OUTPUT
Y

L

INT_SPI_CS#

H
H
H

SB_INT_FLASH_SEL<29>

GREEN

GREEN

CHARGE_LED0#<38>

CHARGE_LED1#<38>

Amber

TP_LOCK#<38>

Amber

WIRELESS_LED#<38>

LED
GREEN

+3VALW

1

C726

0.1U_0402_16V4Z

2

INT_SPI_CS#

R573 15_0402_5%

1 2

MC74VHC1G32DFT2G_SC70-5~D

FSEL#SPICS#
SPI_SO

PWR_LED#<38>

CHARGE_LED0#

CHARGE_LED1#

HT-191NB_BLUE_0603

BATT_CHG_LED#

R626 220_0402_5%

BATT_LOW_LED#

HT-191NB_BLUE_0603

20mils

U31

1

CS#

2

SO

3

WP#

4

GND

MX25L1605AM2C-12G_SO8

VCC

HOLD#

SCLK

+3VALW

U32

4

O

1 2

R574 22_0402_5%@

JP17

112
334
556
778

E&T_2941-G08N-00E~DME@

8
7
6
5

SI

5

P

INB
INA

G

3

2
4
6
8

LED

LED1

R625 150_0402_5%

1 2

1 2

LED4

LED5

1 2

HT-110UD_1204

R569 15_0402_5%

SPI_SI FWR#SPI_SI

INT_FLASH_EN#

1

FSEL#SPICS#

2

+3VALW

INT_FLASH_EN#

SPI_CLK_R

SPI_SI

SC521SYG000

21

21

1 2

R570 15_0402_5%

1 2

100K_0402_5%

1 2

1 2

FSEL#SPICS# <38>

LED7

2

3

12-22UYOSYGC-S530-A2-TR8_OR-GR

12

R577300_0402_5%

R627300_0402_5%

R572

+5VS

+3VALW

1

12

R624300_0402_5%

+5VALW

SPI_CLKSPI_CLK_R

+3VALW

SPI_CLK <38>

FWR#SPI_SI <38>

SPI_CLK_R

R571

15_0402_5%

C727

10P_0402_50V8J

1

@

@

12

1

2

FD1

H1
HOLEA

1

H7
HOLEA

1

H15
HOLEA

1

H22
HOLEA

1

H27
HOLEA

1

1

FD2

H2
HOLEA

1

H8
HOLEA

1

H16
HOLEA

1

H23
HOLEA

1

H28
HOLEA

1

1

FD3

H3
HOLEA

1

H9
HOLEA

1

H17
HOLEA

1

H24
HOLEA

1

1

FD4

H4
HOLEA

1

H10
HOLEA

1

H18
HOLEA

1

H25
HOLEA

1

H5
HOLEA

1

H11
HOLEA

1

H19
HOLEA

1

H26
HOLEA

1

H6
HOLEA

1

H12
HOLEA

1

H20
HOLEA

1

H21
HOLEA

1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

LED/EC SPI ROM

KIWB1/B2_LA4601P

of

40 52Monday, June 30, 2008

0.1

CyberForum.ru

A

B

C

D

E

+5VALW

USB Board Conn. 10 pin

+USB_VCCA

U33

1

1 1

2 2

C730 0.1U_0402_16V4Z

12

USB_ON<35,38>

USB_ON

GND

2

IN

3

IN

4

EN

G545A1P1U_SO8

+USB_VCCA

OUT
OUT
OUT
OC#

8
7
6
5

1

C731

2

USB_OC#4 <29>
USB_OC#11 <29>

1000P_0402_50V7K@

+USB_VCCA

1

+

C728
150U_D2_6.3VM

2

W=80mils

1

C729
470P_0402_50V7K

2

JP18

1

USB20_N4<29>
USB20_P4<29>

USB20_N11<29>

USB20_P11<29>

USB20_N4
USB20_P4

USB20_N11
USB20_P11

2
3
4
5
6
7
8

9

1

GND
2
3
4
5
6
7

10

8

GND

ACES_87213-0800G

+5VS

CMOS Camera Conn

3 3

CMOS_OFF#<38>

4 4

+5VS

12

R579
10K_0402_5%

1

2

OUT

IN

GND

3

Q42
DTC124EKAT146_SC59-3

CMOS1

A

S

D

13

G

Q39

2

SI2301BDS-T1-E3_SOT23-3

USB20_N2<29>
USB20_P2<29>

B

USB20_N2
USB20_P2

12

R580
0_0603_5%

1

C738
10U_0805_10V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INF ORMATION. THIS SHEE T MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C736

0.1U_0402_16V4Z

2

1
2
3
4
5
6
7

JP20

1
2
3
4
5
GND1
GND2

ACES_88266-05001

BT_OFF#<38>

BT_LED#<42>

Compal Secret Data

2006/08/18 2007/8/18

C

Deciphered Date

12

R578
10K_0402_1%

1

2

OUT

IN

GND

3

1

OUT

GND

3

BT MODULE CONN

Q40
DTC124EKAT146_SC59-3

Q43
DTC124EKAT146_SC59-3

2

IN

D

BT_ACTIVE<31>
WLAN_ACTIVE<31>

Title

Size Document Number Re v

Custom

Date: Sheet

+3VS

S

G

2

SI2301BDS-T1-E3_SOT23-3

USB20_N6<29>
USB20_P6<29>

+3VS_BT

D

13

Q41

USB20_N6
USB20_P6
BT_ACTIVE
WLAN_ACTIVE
BTON_LED

30mils

1

0.1U_0402_16V4Z
C737

2

Compal Electronics, Inc.

Power OK, Reset and RTC Circuit, TP

KIWB1/B2_LA4601P

E

MOLEX_53780-0870

10

GND2

9

GND1

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

JP21

41 52Monday, June 3 0, 2008

of

0.1

CyberForum.ru

RCIRRX<38>

ON/OFF switch

Power Button

J2 JOPEN@
J3 JOPEN@

Bottom Side

ON/OFFBTN#

EC_ON<38>

EC_ON

+3VALW

1 2

RCIRRX

+3VALW

SW1

1
2

TOP Side

+3VALW

3
4

5

6

12
12

DAN202UT106_SC70-3

12

R587

4.7K_0402_5%

1 2

R588 33K_0402_5%

13

D

2

G

Q45

S

2N7002_SOT23-3

CIR

R581
100_0603_5%

@

R582

1 2

33_0402_5%

C739

22P_0402_50V8J

1 2

R583 100_0603_5%

4.7U_0805_10V4Z

SMT1-05_4P

D26

3

1

2

2

Power Bottom Board Conn. 5 pin

+3VALW

12

R780

300_0402_5%

JP23

1

1

1

2

IR1

1

Vout

2

VCC

3

GND

4

GND

IRM-V538/TR1_3P

ON/OFF#
51_ON#

2

C741
1000P_0402_50V7K

1

Q44
DTC124EKAT146_SC59-3

ON/OFF# <38>

51_ON# <44>

12

D27
RLZTE1120A LL34

IN

1

C740

2

+3VALW

R584
100K_0402_5%

1 2

1

OUT

GND

3

PWR_LED_SC#<38>

NOVO_BTN#
ON/OFFBTN#

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

ACES_85201-06051

ME@

IDEAPAD BOARD 2PIN

MUTE_LED#<38>

KSO16<38>
KSI2<38,39>
KSO17<38>
KSI3<38,39>

BTN FUNCTION

MUTE BTN

DOWN

UP

Bottom Board Conn. 6 pin

+3VS

12

R781

300_0402_5%

JP25

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

ACES_85201-06051

ME@

KEY MATRIX

R769

300_0402_5%

IN

KSO17
KSO17
KSO16

+5VS

12

OUT

KSI3
KSI2
KSI2

JP26

1

1

2

2

3

G1

4

G2

ACES_85204-02001

ME@

Slide Board Conn. 12 pin

+3VALW

R589
100K_0402_5%

NOVO#<38>
51_ON#<44>

NOVO#
51_ON#

1 2

D28

2
3

1

DAN202UT106_SC70-3

NOVO_BTN#

DRIVE_LED#<28>

BT_LED#<41>

WLAN_LED#<31>

WIMAX_LED#<31>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/25 2008/04/

DRIVE_LED#
BT_LED#
WLAN_LED#
WIMAX_LED#

+5VS

Compal Secret Data

Deciphered Date

EC_SMB_DA2<5,16,38>
EC_SMB_CK2<5,16,38>

R773300_0402_5%

12

R774300_0402_5%

12

R775300_0402_5%

12

R776300_0402_5%

12

R631 0_0402_5%

I2C_INT<38>

1 2

R586 0_0402_5%

1 2

R585 0_0402_5%

1 2

I2C_INT_R
R_SMB_DA2

R_SMB_CK2

Compal Electronics,Ltd.

Title

Audio Jack & SW connector

Size D ocument Number Rev

Custom

Date: Sheet

JP24

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_85201-1005N

KIWB1/B2_LA4601P

0.1

of

42 52Monday, June 30, 2008

CyberForum.ru

A

B

C

D

E

+3VALW TO +3VS+5VALW TO +5VS

+5VALW

U35

8

D

+1.5V

C754
10U_0805_10V4Z

R608
0_0402_5%

@

1 2

7

D

6

D

5

D

SI4800BDY-T1-E3_SO8

R598
0_0402_5%

1 2

U38

8

D

7

D

6

D

5

D

SI4800BDY-T1-E3_SO8

0.1U_0603_25V7K

1

C742

2

G

2

B+

R593
20K_0402_5%

13

D

S

10U_0805_10V4Z

Q49
2N7002_SOT23

1 1

SUSP

+1.5V to +1.5VS

2 2

SUSP

2N7002_SOT23

Q57

2

G

B+

R606
150K_0402_5%

13

D

S

1

2

S
S
S
G

@

S
S
S

G

1.5VS_GATE

1

@

C757

2

+5VS

1
2

1
3
4

2

1

C751

0.1U_0603_25V7K

2

+1.5VS

1
2
3
4

1

C758

0.1U_0603_25V7K

2

C743
10U_0805_10V4Z

1

C755
10U_0805_10V4Z

2

R607 100K_0402_5%@

1

C744
1U_0603_10V4Z

2

1

C756
1U_0603_10V4Z

2

12

R590
470_0603_5%

13

D

S

12

13

D

S

5VS_GATE

SUSP

2

G

Q46
2N7002_SOT23

R601
470_0603_5%

SUSP

2

G

Q52
2N7002_SOT23

SUSP

2

G

12

R602
470_0603_5%

13

D

S

B+

Q53
2N7002_SOT23

1

C745
10U_0805_10V4Z

2

12

R594
47K_0402_5%

13

D

Q50
2N7002_SOT23

S

2

G

+3VALW

8
7
6
5

+3VS

U36

1

S

D

2

1

S

D

3

S

D

G

D

SI4800BDY-T1-E3_SO8

R599
0_0402_5%

@

1 2

+1.5V +VCCP+1.8V +0.75V

12

13

D

S

C746

4

10U_0805_10V4Z

2

R596 47K_0402_5%

1 2

1

@

C752

0.1U_0603_25V7K

2

R603
470_0603_5%

SYSON# SUSP SYSON#SYSON#

2

G

Q54
2N7002_SOT23

1

C747
1U_0603_10V4Z

2

12

R604
470_0603_5%

13

D

G

Q55

S

2N7002_SOT23

2

12

R591
470_0603_5%

13

D

S

SUSP

2

G

Q47
2N7002_SOT23

5VS_GATE

12

R605
470_0603_5%

13

D

S

G

Q56
2N7002_SOT23

+1.8V to +1.8VS

SUSP

2

2

G

1

C748
10U_0805_10V4Z

2

B+

R595
100K_0402_5%

13

D

Q51
2N7002_SOT23

S

+1.8V

U37

8

D

7

D

6

D

5

D

SI4800BDY-T1-E3_SO8

R600
0_0402_5%

1 2

@

+1.8VS

1

S

2

S

3

S

4

G

1

C749
10U_0805_10V4Z

2

R597 100K_0402_5%@

1

C753

0.1U_0603_25V7K

2

1

C750
1U_0603_10V4Z

2

12

R592
470_0603_5%

13

D

S

SUSP

2

G

Q48
2N7002_SOT23

5VS_GATE5VS_GATE 1.8VS_GATE

3 3

R609
10K_0402_5%

Q58

2

IN

+5VALW

12

1

3

@

R610
100K_0402_5%

OUT

GND

+5VALW

12

R611

SYSON#<48,49>

SYSON<31,38,48,49>

B

SYSON#

DTC124EKAT146_SC59-3

SYSON

100K_0402_5%

Q59

1

OUT

2

IN

GND

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

DC Interface

KIWB1/B2_LA4601P

43 52Monday, June 30, 2008

E

0.1

of

RTCVREF

12

SUSP<49>

SUSP#<31,38,48,49>

4 4

SUSP

DTC124EKAT146_SC59-3

A

CyberForum.ru

A

B

C

D

1 1

2 2

DC030006J00

JDCIN
4602-Q04C-09R 4P P2.5@

1

1

2

2

3

3

4

4

APDIN

PF101

7A_24VDC_429007.WRML

21

APDIN1

12

PC101

1000P_0402_50V7K

PL101

SMB3025500YA_2P

1 2

12

100P_0402_50V8J

PC102

12

VIN

100P_0402_50V8J

PC103

12

PC104

1000P_0402_50V7K

VINDE-1

12

PC106

0.068U_0603_25V7M

VIN

12

12

PR103

84.5K_0402_1%
PR106

22K_0402_1%

1 2

PR107

20K_0402_1%

PR102
1M_0402_1%

1 2

VINDE-2

VS

12

PC105

1

O

PU102A
LM393DG_SO8

12

RTCVREF

0.01U_0402_25V7K

8

3

P

+

VINDE-3

2

-

12

PC107

0.1U_0402_16V7K

4

PR109
10K_0402_1%

G

3.3V

VIN

12

PR104

12

10K_0805_5%

PD102

RLZ4.3B_LL34

12

PR108

10K_0402_1%

PR105
10K_0402_5%

1 2

PACIN

ACIN <29,38>

PACIN

Vin Detector

High 18.384 17.901 17.430
Low 17.728 17.257 16.976

PR110

68_1206_5%

13

VIN

PD103

LL4148_LL34-2

1 2

51ON-1

12

12

PC109

0.1U_0603_25V7K

12

PR111
68_1206_5%

VS

SP093MX0000

PD101

LL4148_LL34-2

PR101

200_0603_5%

1 2

100K_0402_1%

PR113

22K_0402_1%

1 2

12

PR112

PQ101

TP0610K-T1-E3_SOT23-3

51ON-2

12

PC108

1 2

0.22U_0603_25V7K

51ON-3

2

BATT+

3 3

CHGRTCP

51_ON#<42>

RTC Battery

JRTC

-+

MAXEL_ML1220T10@

12

+RTCBATT

PD104

1 2

RB751V-40TE17_SOD323-2

+CHGRTC

PR115

560_0603_5%

1 2

PR116

560_0603_5%

1 2

RTCVREF

3.3V

12

PC110
10U_0805_10V4Z

PU101

G920AT24U_SOT89-3

3

OUT

GND

1

12

PR114
200_0603_5%

CHGRTCINRTCVREF-1

2

IN

12

PC111
1U_0805_25V4Z

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

A

B

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/05/21 2009/05/21

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DCIN & DETECTOR

D

44 52Monday, June 30, 2008

of

0.1

CyberForum.ru

A

1 1

B

C

D

PH1 under CPU botten side :

CPU thermal protection at 92 degree C

JBATT

VMB2

1

1

2

2

EC_SMCA

3

2 2

3 3

3

EC_SMDA

4

4

5

5

6

6

7

7

8

GND

9

GND

TYCO_1775768-1@

12

PR204

100_0402_1%

12

PR206

100_0402_1%

1 2

PR209
143K_0402_1%

1 2

PR211
10K_0402_1%

PF2
12A_65V_451012MRL

21

VMB

12

PC201
1000P_0402_50V7K

EC_SMB_CK1 <38>

EC_SMB_DA1 <38>

+3VALW

BATT_TEMP <38>

BATT_SEL_HW <46>

PL201

SMB3025500YA_2P

1 2

A/D

BATT+

12

PC202

0.01U_0402_25V7K
100K_0603_1%_TH11-4H104FT

Recovery at 56 degree C

VL

12

PH201

PR205

13.7K_0402_1%

TM-1

12

PC203

0.22U_0603_25V7K

1 2

TM_REF1

12

PR207

15.4K_0402_1%

12

PC204

1000P_0402_50V7K

PR203

47K_0402_1%

TM-2

1 2

5

+

6

-

PR208

12

100K_0402_1%

PR210
100K_0402_1%

8

P

O

G

LM393DG_SO8

4

12

7

PU102B

VL

VL

PR202
47K_0402_1%

1 2

TM-3

MAINPWON <47>

13

D

2

G

S

PQ201

2N7002W-T/R7_SOT323-3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

A

B

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

2009/05/212008/05/21

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

BATTERY CONN / OTP

D

45 52Monday, June 30, 2008

0.1

of

CyberForum.ru

A

PC306

0.01U_0402_25V7K

0.01U_0402_25V7K@

2

1
2
3
4

12

100K_0402_1%

PR304

PR311

75K_0402_1%

1 2

PQ306

PQ302
FDS4435BZ_SO8

S
S
S
G

PC308

PC315

PQ301
FDS4435BZ_SO8

S

D

S

D

S

D

G

D

PR306
340K_0402_1%

PR310

54.9K_0402_1%

PR316

1 2

1
2
3
4

1 2

24751_VREF ACSET

CP setting

SI2301BDS-T1-E3_SOT23-3

1 2

1 2

8
7
6
5

1 2

1 2

100K_0402_1%

VIN

PR301

3.3_1210_5%

1 1

2.2U_0805_25V6K

2 2

CP Point Setting

CP point=Iadapter*85%
90W adapter
Vacset=3.3*(115K/(75K+115K))=1.99V
CP Point=(Vacset/Vvdac)*(0.1/PR302)=4.02A

65W adapter
Vacset=3.3*(115K/(150K+115K))=1.432V
CP Point=(Vacset/Vvdac)*(0.1/PR302)=2.89A

PR305

3.3_1210_5%

PC311

BK-1 BK-2

1 2

PC301

1 2
12

340K_0402_1%

54.9K_0402_1%

1 2

0.01U_0402_25V7K

PR309

PR314

Input OVP : 22.3V
ACIN detect : 17.26V
Fsw : 300KHz

1 3

24751_VREF

PR320

100K_0402_1%

3 3

ACOFF 24751_OCP-1

1 2

PC326

0.1U_0402_16V7K
PR323

340K_0402_1%

24751_VREF

12

PR318

12

12

200K_0402_1%

13

D

2

G

S

2N7002W-T/R7_SOT323-3

24751_OCP-2

PQ308

2

G

ACSET

24751_OCP-3

13

D

S

1 2

PQ307

2N7002W-T/R7_SOT323-3

PC324

0.1U_0603_25V7K

VMB2

CHGVADJ<38>

12

PC330

0.01U_0402_25V7K

7

PC329

0.01U_0402_25V7K

OVP-2

12

PR327

OVP-1

340K_0402_1%

12

PR329

499K_0402_1%

12

PR331

105K_0402_1%

VS

12

1

OVP-3

0

8

3

P

+

2

-

G

PU302A

4

LM358DR_SO8

PR330
10K_0402_1%

BATT_OVP<38>

12

A/D

4 4

A

B

24751_PVCC

8

D

7

D

6

D

5

D

12

0.1U_0603_25V7K

12

1U_0603_10V6K

RTCVREF

PR302

0.015_1206_1%

B+_IN CHG_B+

1
2

0.1U_0402_16V7K

12

PR313

115K_0402_1%

PC322

12

PR317

100K_0402_1%

PR326

210K_0402_1%

1 2

PC307

1 2

24751_ACDRV#

1 2

0.47U_0603_16V7K

24751_OVPSET

24751_VREF

12

24751_ACGOOD#

/BATDRV

REGN

4
3

12

24751_ACN
24751_ACP

ACDET

24751_ACOP

PC317

VADJ

12

12

CHGEN#

PU301

1

CHGEN

PC309

0.1U_0603_25V7K@

2

ACN

3

ACP

4

ACDRV

5

ACDET

6

ACSET

7

ACOP

8

OVPSET

9

AGND

10

VREF

11

VDAC

12

VADJ

13

ACGOOD

14

BATDRV

BQ24751ARHDR_QFN28_5X5

PR324
0_0402_5%@

VADJ

12

PR328

PC328

499K_0402_1%

1000P_0402_50V7K

28

PVCC

27

BTST

26

HIDRV

25

PH

24

REGN

23

LODRV

22

PGND

21

LEARN

20

CELLS

19

SRP

18

SRN

17

BAT

29

TP

16

SRSET

15

IADAPT

100P_0402_50V8J

CHGVADJ Pre Cell

3.3V 4.35V

0V 4V

24751_BTST-1

24751_HIDRV

24751_PH

REGN

12

PC316
1U_0603_10V6K

24751_LODRV

ACOFF

CELLS

24751_SRP
24751_SRN

12

SRSET

IADAPT

1 2

PR321

10_0603_5%

B+

PC310

0.1U_0603_25V7K

1 2

PR307
0_0402_5%

1 2

24751_BTST

12

PD301

LL4148_LL34-2

ACOFF <38>

12

PC323

0.1U_0603_25V7K

12

PC327

C

PJ301

2

112

JUMP_43X118@

1 2

PC312

0.1U_0603_25V7K
PQ305

AO4466_SO8

24751_VREF

PR334
0_0402_5%

ICHG setting

12

PR322
180K_0402_1%

ADP_I <38>

"CHGVADJ" connect to EC DA pin

LI-3S :13.5V----BATT-OVP=1.5V
BATT-OVP=0.1112*BATT+

8

5

P

+

0

OVP-4

6

-

G

PU302B

4

LM358DR_SO8

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

578

3 6

241

578

3 6

241

PR315

49.9K_0402_1%@

1 2
13

D

BAT_SEL

2

PQ310

G

2N7002W-T/R7_SOT323-3@

S

PR333
0_0402_5%@

PR319

54.9K_0402_1%

12

PC325

0.01U_0402_25V7K

@

IREF Current

2.842V 3.3A

1 2

1 2

PC303

4.7U_1206_25V6K

PQ303
AO4466_SO8

PL202

10U_LF919AS-100M-P3_4.5A_20%

1 2

12

PR312

4.7_1206_5%@

24751_SNB

12

PC318

680P_0603_50V8J@

PR332
0_0402_5%@

12

BATT_SEL_HW <45>

12

BATT_SEL_EC <38>

12

IREF <38>

2009/05/212008/05/21

PC304

4.7U_1206_25V6K

1 2

PC305

24751_SW-1

D

12

PR303

PC302

0.01U_0402_25V7K

4.7U_1206_25V6K

/BATDRV

PR308

0.02_1206_1%

1
2

PC319

0.1U_0402_16V7K

1 2

12

PC320

0.1U_0603_25V7K

FSTCHG<38>

Title

Size Document Number Rev

Date: Sheet

100K_0402_1%

1 2

4
3

12

PC321

0.1U_0603_25V7K

@

24751_VREF

1 2

13

D

2

G

S

36

241

578

12

PC313

10U_1206_25V6M

PR325
100K_0402_1%

CHGEN#

PQ309

2N7002W-T/R7_SOT323-3

Compal Electronics, Inc.

CHARGER

D

PQ304
FDS6675BZ_SO8

12

BATT+

PC314

10U_1206_25V6M

of

46 52Monday, June 30, 2008

0.1

CyberForum.ru

5

4

3

2

1

ISL6237_B+

12

12

PC406

PC404

10U_1206_25V6M

2200P_0402_50V7K

PL402

4.7UH_PCMC063T-4R7MN_5.5A_20%

12

PR404

4.7_1206_5%@

5V_SNB

12

PC415

680P_0603_50V8J@

12

PJ402

2

112

JUMP_43X118@

PJ403

2

112

JUMP_43X118@

PR407

61.9K_0402_1%@

1 2

PR409

1 2

0_0402_5%

+5VALWP

1

+

PC413

2

220U_6.3VM_R15

12

0_0402_5%

100K_0402_1%

1 2

PR418

ISL6237_B+

578

3 6

241

578

3 6

241

PR412

PR413

12

PQ401

AO4466_SO8

PQ403
AO4712_SO8

1 2

1 2

200K_0402_5%

BST3A-1

PR403
0_0402_5%

PC411

0.1U_0603_25V7K

1 2

PC417

0.22U_0603_25V7K

VL

PR417

47K_0402_5%

1 2

806K_0603_1%

1 2

12

PC419

PR401

0_0402_5%

1 2

0.1U_0603_25V7K

12

2VREF_ISL6237

1 2

PC416

0.22U_0603_25V7K

PR419

PC420

0.047U_0402_16V7K@

0.047U_0402_16V7K

@

UG3

BST3A

SW3

LG3

FB3

VL

EN_LDO

3/5V_EN1

3/5V_EN2

12

PC407

PR416
0_0402_5%

1 2

2VREF_ISL6237

33
26
24

25

23

30

32

1

8

20

4

14

27

1 2

TP
UGATE2
BOOT2

PHASE2

LGATE2

OUT2

REFIN2

REF

LDOREFIN

NC

EN_LDO

EN1

EN2

PC418

1U_0603_10V6K

VL

578

1 2

PC408

3/5V_VIN

3/5V_VCC

6

3

VIN

VCC

TON

NC

2

5

3/5V_NC

12

3/5V_TON

12

PR420
0_0402_5%

12

1U_0603_10V6K

PC409

7

19

LDO

PVCC

15

UGATE1

17

BOOT1

16

PHASE1

18

LGATE1

22

PGND

10

OUT1

11

FB1

9

BYP

29

SKIP

28

POK2

13

POK1

12

ILIM1

31

ILIM2

GND

PU401

21

ISL6237IRZ-T_QFN32_5X5

4.7U_0805_6.3V6K

PC410

1U_0603_10V6K

1 2

HG5
BST5A

PR405
0_0402_5%

SW5

LG5

FB5

5V_SKIP

ILM1

ILIM2

BST5A-1

12

PC412

0.1U_0603_25V7K

PR410
0_0402_5%@

1 2

PR411
0_0402_5%

PR414
301K_0402_1%

PR415
301K_0402_1%

1 2

12

PQ404

AO4712_SO8

12

12

PQ402
AO4466_SO8

3 6

241

578

3 6

241

VL

POK <29>

+3VALWP +3VALW

+5VALWP +5VALW

2VREF_ISL6237

B+

PJ401
JUMP_43X118@

2

112

D D

4.7UH_PCMC063T-4R7MN_5.5A_20%

1 2

1 2

PR406

0_0402_5%

PR408

10K_0402_1%@

PD402

RLZ5.1B_LL34

1 2

1 2

+3VALWP

1

+

PC421

220U_6.3VM_R15

C C

B B

2

VS

PL401

680P_0603_50V8J@

PC401

4.7_1206_5%@

PC414

12

PC403

10U_1206_25V6M

2200P_0402_50V7K

12

PR402

3V_SNB

12

PD401

RB751V-40TE17_SOD323-2

1 2

EN_LDO-1

PD403

RB751V-40TE17_SOD323-2@

1 2

MAINPWON <45>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

2008/05/21 2009/05/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

3VALW/5VALW

Size Document Number Rev

Monday, June 30, 2008

2

Date: Sheet

47 52

1

0.1Custom

of

CyberForum.ru

5

4

3

2

1

1.5V_IN

578

PR501

2

TON

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

2

TON

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

+3VALW

12

PC520
1U_0603_6.3V6M

240K_0402_5%

1 2

15

1

TP

EN_PSV

GND7PGND

1.5V_PGOOD <8>

PR525

240K_0402_5%

1 2

15

1

TP

EN_PSV

GND7PGND

PR519

0_0603_1%

BST_1.5V BST_1.5V-1

1 2

14

TRIP

DRVL

TRIP

DRVL

LL

LL

UG_1.5V

13

SW_1.5V

12

1.5V_TRIP

1 2

11

23.7K_0402_1%

10

LG_1.5V

9

PR527

0_0603_1%

1 2

UG_VCCP

13

SW_VCCP

12

VCCP_TRIP

1 2

11

23.7K_0402_1%

10

LG_VCCP

9

PR522

PR530

VBST

DRVH

V5DRV

8

PU501
TPS51117RGYR_QFN14_3.5x3.5

BST_VCCP BST_VCCP-1

14

VBST

DRVH

V5DRV

8

PU503
TPS51117RGYR_QFN14_3.5x3.5

PC525

1 2

0.1U_0603_25V7K

+5VALW

PC535

1 2

0.1U_0603_25V7K

+5VS

12

PC531

4.7U_0805_10V6K

12

PC541

4.7U_0805_10V6K

3 6

578

3 6

578

3 6

578

3 6

241

241

241

241

PQ501
AO4466_SO8

AO4712_SO8

PQ506

VCCP_IN

PQ507
AO4466_SO8

AO4712_SO8

PQ508

+VCCPP +VCCP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

PL501

2.2UH_PCMC063T-2R2MN_8A_20%

1 2

12

PR520

4.7_1206_5%@

1.5V_SNB

12

PC532

680P_0603_50V7K@

PL502

1.8UH_SIL104R-1R8PF_9.5A_30%

1 2

12

PR528

4.7_1206_5%@

VCCP_SNB

12

PC542

680P_0603_50V7K@

PJ503

2

112

JUMP_43X118@

2009/05/212008/05/21

2

1 2

PR533

100K_0402_5%

6
5

NC

7

NC

8

NC

9

TP

1.5V_TON

1.5V_EN

1.5V_V5FILT

1.5V_FB

12

@

VCCP_TON

VCCP_EN

VCCP_V5FILT

VCCP_FB

PC543

0.1U_0402_16V7K

D D

SYSON<31,38,43,49>

+5VALW

C C

SUSP#<31,38,43,49>

+5VS

B B

+1.5V

1

PJ502

1

JUMP_43X79@

2

2

12

PC519

4.7U_0805_6.3V6K

A A

PR516

0_0402_5%

0.75V_EN

SYSON#<43,49>

1 2

0.1U_0402_16V7K@

PC522

12

13

D

2

G

S

1K_0402_1%

1K_0402_1%

PQ505
SSM3K7002FU_SC70-3

PR515

PR517

PR518

0_0402_5%

1 2

PR521

422_0603_1%

1 2

PC529

1U_0603_10V6K

PR526

0_0402_5%

1 2

PR529

422_0603_1%

1 2

PC539

1U_0603_10V6K

0.75V_IN

12

0.75V_REF

12

PC521

0.1U_0402_16V7K

12

PC526

0.1U_0402_16V7K

@

12

12

PC536

0.1U_0402_16V7K

@

12

12

PC530

47P_0402_50V8J@

1 2

PR523

31.6K_0402_1%

1 2

12

PR524

30.1K_0402_1%

PC540

47P_0402_50V8J@

1 2

PR531

13.7K_0402_1%

1 2

12

PR532

31.6K_0402_1%

PU502

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TRL_SO8

+0.75VP

12

PC523
10U_0805_6.3V6M

5

4

PJ501

2

112

JUMP_43X79

@

12

PC501

10U_1206_25V6M

1

12

+

PC528

PC527

2

220U_6.3VM_R15

PJ506

2

112

JUMP_43X79@

12

PC534

10U_1206_25V6M

1

12

+

PC537

2

PC538

220U_6.3VM_R15

+1.5VP +1.5V

Title

Size Document Number Rev

Date: Sheet

B+

+1.5VP

10U_0805_6.3V6M

B+

+VCCPP

10U_0805_6.3V6M

PJ504

2

112

JUMP_43X118@

PJ505

2

112

JUMP_43X79@

Compal Electronics, Inc.

1.5V/VCCP/0.75V

48 52Monday, June 30, 2008

1

+0.75V+0.75VP

0.1

of

CyberForum.ru

5

PR602

0_0402_5%

D D

SYSON

31,38,43,48>

+5VALW

C C

B B

GPU_VID1<16>

A A

NB9M-GS

NB9P-GE2

1 2

12

PR605

422_0603_1%

1 2

12

PC607

1U_0603_10V6K

PR610

0_0402_5%

+5VS

1 2

422_0603_1%

1 2

PR630

12

10K_0402_5%

PR613

1U_0603_10V6K

12

SUSP#<31,38,43,48>

PR629

10K_0402_1%

GPU_VID0<16>

PR621

10K_0402_1%

GPIO6 GPIO5

GPU_VID1 GPU_VID0 VGA_CORE

0
1

1

GPIO6 GPIO5

GPU_VID1 GPU_VID0 VGA_CORE

0
1

PC604

0.1U_0402_16V7K@

47P_0402_50V8J@

30.1K_0402_1%

1 2

12

PR608
21K_0402_1%

PC617

GVID1-2

13

D

GVID1-1

2

G

S

12

PC625

0.022U_0402_16V7K

PR624

12

10K_0402_5%

0
0

1

1

PC609

1 2

PR607

12

PC613

0.1U_0402_16V7K@

12

PR620

52.3K_0402_1%

1 2

PQ606
SSM3K7002FU_SC70-3

GVID0-1

12

2

G

12

PC632

0.022U_0402_16V7K

0.9V

1.09V

1.17V

0.9V1

1.0V

1.8V_TON

1.8V_EN

2

1.8V_V5FILT

1.8V_FB

VGA_EN BST_VGA

VGA_V5FILT

VGA_FB

PC619

47P_0402_50V8J@

1 2

PR616

13.3K_0402_1%

1 2
1 2

PR619

66.5K_0402_1%

PR618

127K_0402_1%

1 2

GVID0-2

13

D

PQ607

S

SSM3K7002FU_SC70-3

3
4
5
6

VGA_TON

2

TON

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

SUSP<43> SYSON#<43,48>

5

TON
VOUT
V5FILT
VFB
PGOOD

0_0402_5%

1 2

0.1U_0402_16V7K@

4

PR601

240K_0402_5%

1 2

15

1

TP

EN_PSV

GND7PGND

8

PR609

240K_0402_5%

1 2

14

15

1

TP

EN_PSV

GND7PGND

8

PU602
TPS51117RGYR_QFN14_3.5x3.5

4.7U_0805_6.3V6K

PR625

1.1V_EN

12

PC630

4

PR603

0_0603_1%

BST_1.8V BST_1.8V-1

1 2

14

VBST

V5DRV

PU601
TPS51117RGYR_QFN14_3.5x3.5

VBST

DRVH

TRIP

V5DRV

DRVL

PC621

UG_1.8V

13

DRVH

SW_1.8V

12

LL

1.8V_TRIP

1 2

11

TRIP

DRVL

LL

2

G

PR606

23.7K_0402_1%

10

LG_1.8V

9

BST_VGA-1

1 2

PR611
0_0603_1%

13

12

11

10

9

+1.8V

@

PC614

0.1U_0603_25V7K

UG_VGA
SW_VGA
VGA_TRIP

1 2

PR614
13K_0402_1%

LG_VGA

1

PJ607

1

JUMP_43X79

2

2

1.1V_IN LDO_1.8V_IN

12

PR622

1K_0402_1%

1.1V_REF

13

D

PR627

2.94K_0402_1%

PQ608

S

SSM3K7002FU_SC70-3

1 2

PC603

0.1U_0603_25V7K

+5VALW

12

1 2

+5VS

12

PC620

4.7U_0805_10V6K

12

12

PC626

0.1U_0402_16V7K

3

1.8V_IN

578

PQ601
AO4466_SO8

3 6

241

PL601

2.2UH_PCMC063T-2R2MN_8A_20%

1 2

12

PC610

4.7U_0805_10V6K

12

12

578

3 6

241

578

3 6

241

3 5

241

PU603

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TRL_SO8

+1.1VSP

PC628
10U_0805_6.3V6M

PR604

4.7_1206_5%@

1.8V_SNB

12

PQ602

AO4712_SO8

PC608

680P_0603_50V7K@

VGA_IN

12

PQ603
SI4686DY-T1-E3_SO8

PQ604
FDMS8670S_MLP8

6
5

NC

7

NC

8

NC

9

TP

12

PC611

10U_1206_25V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

PJ601

2

112

JUMP_43X79@

12

PC601

10U_1206_25V6M

1

12

+

PC605

2

220U_6.3VM_R15

PJ605

2

112

JUMP_43X79@

PC612

10U_1206_25V6M

PL602

1UH_PCMB103E-1R0MS_20A_20%

1 2

12

PR612

4.7_1206_5%@

VGA_SNB

12

PC618

680P_0603_50V7K@

+5VS

12

PC622
1U_0603_6.3V6M

1 2

0.1U_0402_16V7K@

0_0402_5%@

4.7U_0805_6.3V6K@

PR626

PC631

Compal Secret Data

Deciphered Date

LDO_1.8V_EN

PC606

B+

12

PR615

12

B+

+1.8VP

10U_0805_6.3V6M

1

+

2

10_0402_5%

PC623

2

G

2

PC615

220U_D2_4VY_R15M

+3VALW

1

2

12

13

D

S

2

1

2

PQ609
SSM3K7002FU_SC70-3@

2009/05/212008/05/21

12

PC616

10U_0805_6.3V6M

PJ608
JUMP_43X79@

1K_0402_1%@

1.54K_0402_1%@

PJ602

+VGA_COREP +VGA_CORE

+VGA_COREP

+VGASENSE <19>

12

PR623

LDO_1.8V_REF

PR628

12

12

PC627

0.1U_0402_16V7K@

Title

Size Document Number Rev

Date: Sheet

2

112

JUMP_43X118

@

PJ603

2

112

JUMP_43X118

@

PJ604

2

112

JUMP_43X79

PJ606

@

2

112

JUMP_43X118

@

PU604

VIN1VCNTL

2
3
4

12

PC629
10U_0805_6.3V6M

@

GND
VREF
VOUT

APL5331KAC-TRL_SO8@

+1.8VP

NC
NC
NC

TP

Compal Electronics, Inc.

VGA_CORE/1.8V/1.1V

1

+1.1VS+1.1VSP

+1.8V+1.8VP

6
5
7
8
9

1

12

@

49 52Monday, June 30, 2008

+5VALW

PC624
1U_0603_6.3V6M

of

0.1

CyberForum.ru

5

+3VS

12

D D

VGATE<8,29>

1 2

1 2
1 2

1 2
1 2
1 2
1 2

CPU_GNDSNS

CPU_VSNS

12

PR844

0_0402_5%

VCCSENSE

1 2

PR832
0_0402_5%@

PC824

1U_0402_6.3V6K

CPU_DROOP
CPU_VREF

CPU_CSP1-2

CPU_CSP1-2
CPU_CSN1-1

CPU_CSN1-1
CPU_CSN2-1

CPU_CSN2-1
CPU_CSP2-2

CPU_CSP2-2

CPU_THERM

12

PR845

0_0402_5%

PR849
20K_0402_5%

12

PR847
100_0402_5%

<6>

+CPU_CORE

CLK_ENABLE#<29>

C C

CPU_VREF

PR839

5.76K_0402_1%

12

PC825 68P_0402_50V8J
PC826 0.22U_0603_10V7K

PC828 33P_0402_50V8K
PC830 33P_0402_50V8K
PC832 33P_0402_50V8K
PC833 33P_0402_50V8K

12

VSSSENSE

CPU_CSP1

PR861 470_0402_1%

CPU_CSN1

PR862 470_0402_1%

CPU_CSN2

PR863 470_0402_1%

CPU_CSP2

PR864 470_0402_1%

B B

12

PC836

100P_0402_50V8J

12
12

PC837

100P_0402_50V8J

12

1 2

1 2

PR843

100_0402_5%

12

PR830

10K_0402_5%@

12

CPU_V5FILT

40

41

GND

V5FILT

1

DROOP

2

VREF

3

GND

4

CSP1

5

CSN1

6

CSN2

7

CSP2

8

GNDSNS

9

VSNS

10

THERM

VR_TT#11DPRSTP#12PSI#13VID614VID515VID416VID317VID218VID119VID0

<6>

4

PR831

10K_0402_5%@

+3VS +5VS

CPU_VREF

12

12

12

12

PR834 0_0402_5%

PR836 0_0402_5%

PR835 0_0402_5%

PR833 124K_0402_1%

CPU_TONSEL

CPU_OSRSEL

CPU_TRIPSEL

CPU_ISLEW

36

39

38

37

ISLEW

TONSEL

OSRSEL

TRIPSEL

PU801

TPS51620RHAR_QFN40_6X6

PSI#

VID5

VID6

CPU_DPRSTP#

12

12

1 2

1 2

PR852 0_0402_5%

PR854 0_0402_5%

PR855 0_0402_5%

PR853 0_0402_5%

H_PSI#

CPU_VID5

CPU_VID6

H_DPRSTP#

VR_ON

12

CPU_VR_ON

34

35

VR_ON

PWRMON

VID3

VID4

1 2

1 2

PR856 0_0402_5%

<6>

<6,8,28>

CPU_VID3

CPU_VID4

1 2

PR837 0_0402_5%

CPU_DPRSLPVR

CPU_CLK_EN#

32

33

CLK_EN#

VID1

VID2

1 2

1 2

PR857 0_0402_5%

PR858 0_0402_5%

<6>

<6>

CPU_VID2

DPRSLPVR

PR838 0_0402_5%

31

PGOOD
DRVH1

DPRSLPVR

VBST

DRVL1

PGND

DRVL2

VBST2

DRVH2

20

VID0

1 2

PR859 0_0402_5%

PR860 0_0402_5%

<6>

CPU_VID1

CPU_VID0

V5IN

<38>

30
29
28

LL1

27
26
25
24
23

LL2

22
21

<6>

<6>

<8,29>

UGATE_CPU1
BOOT_CPU1

PR841

1 2

0_0603_5%

PHASE_CPU1
LGATE_CPU1

1 2

PC831 10U_0603_6.3V6M

LGATE_CPU2
PHASE_CPU2
BOOT_CPU2

PR846

1 2

0_0603_5%

UGATE_CPU2

<6>

<6>

+5VS

PD801
1SS355_SOD323-2

1 2

BOOT_CPU1-1

1 2

PC827

0.22U_0603_10V7K

+5VS

BOOT_CPU2-1

1 2

PC834

0.22U_0603_10V7K

1 2

PD802
1SS355_SOD323-2

3

PC808

PQ801
SI7686DP-T1-E3_SO8

3 5

241

12

786

5

4

PQ802

SI4634DY-T1-E3_SO8

5

4

PQ805

SI4634DY-T1-E3_SO8

123

PQ803

123

SI4634DY-T1-E3_SO8

3 5

241

786

123

PR819

6.8_1206_5%@

CPU1_SNB

12

PC815
470P_0402_50V7K@

12

PC817

PQ804
SI7686DP-T1-E3_SO8

PQ806

SI4634DY-T1-E3_SO8

+5VS

786

5

4

123

786

5

4

12

12

PC804

10U_1206_25V6M

10U_1206_25V6M

12

PC818

10U_1206_25V6M

10U_1206_25V6M

12

PR829

6.8_1206_5%@

CPU2_SNB

12

PC823
470P_0402_50V7K@

2

12

PC809

2200P_0402_50V7K

PR801

15.4K_0402_1%

+CPU_B+

CPU_CSP1

PR848

15.4K_0402_1%

CPU_CSP2

+CPU_B+

0.36UH_PCMC104T-R36MN1R17_30A_20%

CPU_CSP1-1

12

1 2

PR842

28.7K_0402_1%

0.36UH_PCMC104T-R36MN1R17_30A_20%

CPU_CSP2-1

12

1 2

PR851

28.7K_0402_1%

HCB4532KF-800T90_1812

1

+

2

PC805

220U_25V_M

PL802

1
2

PC829

0.022U_0402_16V7K

PL803

1
2

PC835

0.022U_0402_16V7K

PR840
194K_0402_1%

1 2

CPU_SN-1

1 2

1 2

PR850
194K_0402_1%

1 2

CPU_SN-2

1 2

1 2

4
3

4
3

1 2

PH801

100K_0603_1%_TH11-4H104FT

PH803

100K_0603_1%_TH11-4H104FT

1

PL801

B+

+CPU_CORE

CPU_CSN1

CPU_CSN2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

2008/05/21 2009/05/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

2

Date: Sheet

+CPU_CORE

Monday, June 30, 2008

0.1

of

50 52

1

CyberForum.ru

5

4

3

2

Version change list (P.I.R. List) Page 1 of 2

for PWR

Reason for change Rev. PG# Modify List Date PhaseFixed IssueItem

1

D D

1

2

20071031 EVT

20071115 DVT

3

4

5

6

7

8

C C

9

10

11

12

13

14

15

16

B B

17

18

19

20

21

22

23

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2007/09/20 2008/09/20

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

PIR (PWR)

<Doc>

0.1

of

51 52Thursday, June 26, 2008

1

CyberForum.ru

5

4

3

2

1

NO DATE PAGE MODIFICATION LIST PURPOSE

-------------------------------------------------------------------------------------------------------------

D D

C C

B B

A A

Title

Size Document Number Rev

B

5

4

3

2

Date: Sheet

Compal Electronics, Inc.

HW PIR

KIWB3/B4_LA4551P 0.1

of

52 52Thursday, June 26, 2008

1