COMPAL LA-4481P Schematics

http://mycomp.su/x/

A

1 1

2 2

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D

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Compal confidential

Schematics Document

Calypso 13.3"

Mobile AMD S1G2 CPU with ATI RS780M(NB) & SB700(SB) core logic

3 3

2008-09-04

LA-4481P REV:0.4

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-4481P

146Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

Compal Confidential

B

C

Consumer AMD 13.3" UMA - Sally

D

E

1 1

Accelerometer
ST LIS302DLTR

Page 31

Thermal Sensor
ADM1032ARMZ

Page 7

Fan conn

Page 5

AMD S1G2 CPU

638-PIN uFCPGA 638

Page 5, 6, 7, 8

DDR2 800MHz 1.8V

Dual Channel

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

Page 9, 10

72QFN

Clock Generator
SLG8SP626VTR

Page 16

Hyper Transport Link

16X16

Side-Port DDR2 SDRAM

LVDS Panel

Page 17

Page 19

Page 18

A-Link Express II

Interface

2 2

CRT

HDMI

ATI RS780M

Page 10, 11, 12, 13, 14

4X PCI-E

PCI-E BUS*3

ATI SB700

Realtek
8111C(GLAN)

Page 28

3 3

RJ45/11 CONN

Page 26

Page 26

Mini-Card*1

WLAN

Page 27

Express Card

Page 27

Page 20, 21, 22, 23, 24

LPC BUS

DDR2 400MHz

USB2.0 X12

Azalia (HDA I/F)
SATA Master-1
SATA Master-2
SATA Slave
SATA Slave

512Mbits(32Mbx16)-64MB

Page 13

USB conn x2
e-SATA Combo

BT Conn

Mini-Card WLAN

Page 32

Page 32

Page 27

USB WebCam

Page 18

FingerPrinter AES1610
USBx1

page 32

Audio CKT

Codec_IDT9271B7

SATA HDD Connector

Page 29 Page 30

Page 25

CardReader
RTS5158E-GR_LQFP48

Page 28

CardReader Socket

Page 28

AMP & Audio Jack

TPA6017A2

KBC

ENE KB926

Page 34

LED

RTC CKT.

Power OK CKT.

4 4

P35

Page 20

P35

Touch Pad CONN. Int.KBD

Page 35

Consumer IR

Page 30

SPI

Page 34

SPI ROM
SST25VF080B

Page 33

SATA ODD Connector

SATA Multi-Bay Connector

Page 25

Page 25

e-SATA Combo

Page 32

Power On/Off CKT.

P35

Security Classification

DC/DC Interface CKT.

Page 36

A

B

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-4481P

246Monday, September 08, 2008

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0.4

of

http://mycomp.su/x/

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B

C

D

E

Voltage Rails

1 1

State

2 2

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

3 3

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

EC SM Bus1 address

Device

Smart Battery

24C16

4 4

O MEANS ON X MEANS OFF

power
plane

HEX

A0

D2

+B

O
O
O
O
O

X

+5VALW

+3VALW

O
O
O
O

X
XX X

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0

+1.8V

EC SM Bus2 address

HEX

Address Address

16H

1010 000X b

A0H

Device

CPU

ADI1032-2 CPU

HEX

98H
9AH

+5VS
+3VS
+1.5VS
+0.9V
+VCCP
+CPU_CORE

+VGA_CORE
+2.5VS
+1.8VS
+1.2VS
+0.9VGA

OO
OO

O

X
XX
X

1001 100X b0001 011X b
1001 101X b

X

SMBUS Control Table

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
I2C_CLK
I2C_DATA
DDC_CLK0
DDC_DATA0
DDC_CLK1
DDC_DATA1
SCL0
SDA0
SCL1
SDA1
SCL2
SDA2
SCL3
SDA3

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
DEBUG@ : means just reserve for debug.

USB assignment:

USB-0 Right side
USB-1 Right side
USB-2 Left side(with ESATA)
USB-3 Dock
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Finger Printer
USB-8 MiniCard(WWAN/TV)
USB-9 Express card
USB-10 X
USB-11 X

SOURCE

KB926

KB926

RS780M

RS780M

RS780M

SB700

SB700

SB700

SB700

INVERTER BATT EEPROM

X
XXX
XXX X X X X
XXX X X
XXX X X
XXX X X

PCIe assignment:

PCIe-1 TV tuner/WWAN/Robeson
PCIe-2 X
PCIe-3 WLAN
PCIe-4 New Card
PCIe-5 Card reader
PCIe-6 GLAN (Marvell)

SERIAL SENSOR

VV

XXXX
XXXX
XXXX

Layout Notes

L

UMA@ : means for RS780M.
Please see VGA@ as no install. No support RX780M.

11/14 update

: Question Area Mark.(Wait check)

THERMAL

CPU &
ADM1032

SODIMM CLK CHIP

XX

V

XXXX

MINI CARD

Slot 2I / II

XX

LCD

X

V

XXX
XXX X

VV

V

X

XX

X

HDMI

X
X
X

V

XX
XXXX
XXXX
XX

G-Sensor

X
X
X
X
X
X
X

V

X

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-4481P

346Monday, September 08, 2008

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0.4

of

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5

4

3

2

1

SB700

0.3A

INVPWR_B+

D D

VIN

AC

2A

B++

1.7A

LVDS CON

+3VALW

+5VALW

C C

B+

300mA

60mA

10mA

20mA

2mA

1.3A0.58A

35mA

1.3A

3.7A

LAN

+3VAUX_BT

+3VS

SPI ROM+3VL

+3VL_EC

CIR+5VL

+3VL_CAP

+5VS

+VDDA_CODEC
IDT 9271B7

USB Power

CPU

Finger printer PC Camera

50mA

50mA

DDR

5.39A5.89A

700mA

HDD

FAN

SB700

HDMI

1A

??A

79.67mA

1.5A

LEDs

10mA

1.8A

+5VAMP

ODD

+1.35VS

CardReader

LEDs

New card

+2.5VS CPU

Thermal sensor

RS780M

+LCDVDD

G-sensor

+3VS_CLK

SB700

WLAN

Audio codec

LVDS CON

8 A

B B

3.7 X 3=11.1V

B+++

12.11A

+1.8V

3.7A 723.6mA

DDR2 x2

+1.8VS

Side port RAM

+1.5VS

RS780M

New card

WLAN

DC BATT

3.7A

+0.9V

CPU

DDR2 x2

B+++ +1.1VS RS780M

8.84A

CPU

SB700

A A

+1.2VALW

+1.2V_HT RS780M

273mA

+VDDCLK_IO

SB700

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/09/26 2007/09/26

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

LA-4481P

Date: Sheet

Power delivery

1

of

446Monday, September 08, 2008

0.4

http://mycomp.su/x/

A

B

C

D

E

+1.2V_HT

250 mil

1

C1

4.7U_0805_10V4Z

1 1

2

1

C2

4.7U_0805_10V4Z

2

VLDT CAP.

1

C3

0.22U_0603_16V4Z

2

1

2

C4

0.22U_0603_16V4Z

1

C5
180P_0402_50V8J

2

1

C6
180P_0402_50V8J

2

Near CPU Socket

+VLDT_B

AE2
AE3
AE4
AE5

AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3

Y1
W1
Y4
Y3

R2
R3
T5
R5

H_CADOP[0..15]
H_CADON[0..15]

1 2

C7 4.7U_0805_10V4Z

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

H_CADOP[0..15] <11>
H_CADON[0..15] <11>H_CADIN[0..15]<11>

H_CLKOP0 <11>
H_CLKON0 <11>
H_CLKOP1 <11>
H_CLKON1 <11>

H_CTLOP0 <11>
H_CTLON0 <11>H_CTLIN0<11>

H_CTLON1 <11>

PWM Fan Control circuit

CH751H-40PT_SOD323-2

FAN_PWM<34>

+5VS

500mA

1

D1

2 1

6

2

1

D

Q1

G

3

S

SI3456BDV-T1-E3_TSOP6

4 5

C8

4.7U_0805_10V4Z

2

+VCC_FAN

1

C9

0.1U_0402_16V4Z

2

12

D2

@

RLZ5.1B_LL34

JP1

1

1

2

2

3

GND

4

GND

ACES_85205-02001

H_CADIP[0..15]<11>

2 2

H_CLKIP0<11>
H_CLKIN0<11>
H_CLKIP1<11>

3 3

4 4

H_CLKIN1<11>
H_CTLIP0<11>
H_CTLIP1<11> H_CTLOP1 <11>

H_CTLIN1<11>

H_CADIP[0..15]
H_CADIN[0..15]

VLDT=1500mA

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

+1.2V_HT

JCPU1A

D1

VLDT_A0

D2

VLDT_A1

D3

VLDT_A2

D4

VLDT_A3

E3

L0_CADIN_H0

E2

L0_CADIN_L0

E1

L0_CADIN_H1

F1

L0_CADIN_L1

G3

L0_CADIN_H2

G2

L0_CADIN_L2

G1

L0_CADIN_H3

H1

L0_CADIN_L3

J1

L0_CADIN_H4

K1

L0_CADIN_L4

L3

L0_CADIN_H5

L2

L0_CADIN_L5

L1

L0_CADIN_H6

M1

L0_CADIN_L6

N3

L0_CADIN_H7

N2

L0_CADIN_L7

E5

L0_CADIN_H8

F5

L0_CADIN_L8

F3

L0_CADIN_H9

F4

L0_CADIN_L9

G5

L0_CADIN_H10

H5

L0_CADIN_L10

H3

L0_CADIN_H11

H4

L0_CADIN_L11

K3

L0_CADIN_H12

K4

L0_CADIN_L12

L5

L0_CADIN_H13

M5

L0_CADIN_L13

M3

L0_CADIN_H14

M4

L0_CADIN_L14

N5

L0_CADIN_H15

P5

L0_CADIN_L15

J3

L0_CLKIN_H0

J2

L0_CLKIN_L0

J5

L0_CLKIN_H1

K5

L0_CLKIN_L1

N1

L0_CTLIN_H0

P1

L0_CTLIN_L0

P3

L0_CTLIN_H1

P4

L0_CTLIN_L1

TYCO_4-1903401-4_AMD

CONN@

Athlon 64 S1
Processor Socket

HT LINK

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9

L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CLKOUT_H1

L0_CLKOUT_L1
L0_CTLOUT_H0

L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1

If VLDT is connected only on one side, one

4.7uF cap should be added to the island
side.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

AMD CPU S1G2 HT I/F

LA-4481P

546Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

B

C

D

E

0801 add Cap for EMI request

+1.8V

+1.8V

+1.8V

@

1 2

+3VALW

0.1U_0402_16V4Z

C124

@

1 2

@

1 2

+5VALW

0.1U_0402_16V4Z
C123

+5VS

0.1U_0402_16V4Z

Place them close to CPU within 1"

+1.8V

DDR_A_ODT0<9>
DDR_A_ODT1<9>

DDR_CS0_DIMMA#<9>
DDR_CS1_DIMMA#<9> DDR_CS0_DIMMB# <10>

DDR_CKE0_DIMMA<9>
DDR_CKE1_DIMMA<9>

DDR_A_CLK0<9>

DDR_A_CLK#0<9>

DDR_A_CLK1<9>

DDR_A_CLK#1<9>

DDR_A_MA[15..0]<9> DDR_B_MA[15..0] <10>

DDR_A_BS#0<9>
DDR_A_BS#1<9>
DDR_A_BS#2<9>

DDR_A_RAS#<9>
DDR_A_CAS#<9>
DDR_A_WE#<9>

750mA

D10
C10
B10

R3 39.2_0402_1%

1 2
1 2

R4 39.2_0402_1%

T2 PAD

DDR_A_ODT0
DDR_A_ODT1

DDR_CS0_DIMMA#
DDR_CS1_DIMMA# DDR_CS0_DIMMB#

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

AD10
AF10

AE10

AA16

H16
T19

V22
U21
V19

T20
U19
U20
V20

J22
J20

N19
N20
E16
F16
Y16

P19
P20

N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19

R20
R23

J21

R19
T22
T24

1 1

2 2

3 3

4 4

C129

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

DDR_A_CLK0

DDR_A_CLK#0
DDR_A_CLK1

DDR_A_CLK#1

DDR_B_CLK0

DDR_B_CLK#0
DDR_B_CLK1

DDR_B_CLK#1

JCPU1B

VTT1

MEM:CMD/CTRL/CLK

VTT2
VTT3
VTT4

MEMZP
MEMZN

RSVD_M1
MA0_ODT0

MA0_ODT1
MA1_ODT0
MA1_ODT1

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

MA_CKE0
MA_CKE1

MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MA_BANK0
MA_BANK1
MA_BANK2

MA_RAS_L
MA_CAS_L
MA_WE_L

Athlon 64 S1
Processor
Socket

VTT_SENSE

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0

MB_CLK_H5

MB_CLK_L5

MB_CLK_H1

MB_CLK_L1

MB_CLK_H7

MB_CLK_L7

MB_CLK_H4

MB_CLK_L4

TYCO_4-1903401-4_AMD

CONN@

1

2

1

2

1

2

1

2

VTT5
VTT6
VTT7
VTT8
VTT9

MEMVREF

RSVD_M2

MB0_ODT0
MB0_ODT1
MB1_ODT0

MB_CKE0
MB_CKE1

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8

MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

MB_BANK0
MB_BANK1
MB_BANK2

MB_RAS_L
MB_CAS_L

MB_WE_L

C10

1.5P_0402_50V9C

C11

1.5P_0402_50V9C

C12

1.5P_0402_50V9C

C13

1.5P_0402_50V9C

W10
AC10
AB10
AA10
A10

Y10
W17
B18
W26

W23
Y26

V26
W25
U22

J25
H26

P22
R22
A17
A18
AF18
AF17
R26
R25

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24

R24
U26
J26

U25
U24
U23

+0.9V+0.9V

750mA

VTT_SENSE

+MCH_REF

DDR_B_ODT0
DDR_B_ODT1

DDR_CS1_DIMMB#

DDR_CKE0_DIMMB
DDR_CKE1_DIMMB

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1DDR_A_CLK#1

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

+1.8V

R1

1K_0402_1%

R2

1K_0402_1%

T1PAD

T3PAD

DDR_B_ODT0 <10>
DDR_B_ODT1 <10>

DDR_CS1_DIMMB# <10>

DDR_CKE0_DIMMB <10>
DDR_CKE1_DIMMB <10>

DDR_B_CLK0 <10>
DDR_B_CLK#0 <10>
DDR_B_CLK1 <10>
DDR_B_CLK#1 <10>

DDR_B_BS#0 <10>
DDR_B_BS#1 <10>
DDR_B_BS#2 <10>

DDR_B_RAS# <10>
DDR_B_CAS# <10>
DDR_B_WE# <10>

1 2

+MCH_REF

1

C14

2

1 2

0.1U_0402_16V4Z

DDR_B_D[63..0]<10>

1

C15

2

1000P_0402_25V8J

DDR_B_DM[7..0]<10> DDR_A_DM[7..0] <9>

DDR_B_DQS0<10>
DDR_B_DQS#0<10>
DDR_B_DQS1<10>
DDR_B_DQS#1<10>
DDR_B_DQS2<10>
DDR_B_DQS#2<10>
DDR_B_DQS3<10>
DDR_B_DQS#3<10>
DDR_B_DQS4<10>
DDR_B_DQS#4<10>
DDR_B_DQS5<10>
DDR_B_DQS#5<10>
DDR_B_DQS6<10>
DDR_B_DQS#6<10>
DDR_B_DQS7<10>
DDR_B_DQS#7<10>

Processor DDR2 Memory Interface

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7

AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11

AE14
AF14
AF11
AD11

AB26
AE22
AC16
AD12

AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12

C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24

Y11

A12
B16
A22
E25

C12
B12
D16
C16
A24
A23
F26
E26

JCPU1C

Athlon 64 S1
Processor Socket

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

MEM:DATA

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8

MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

MA_DQS_H0

MA_DQS_L0

MA_DQS_H1

MA_DQS_L1

MA_DQS_H2

MA_DQS_L2

MA_DQS_H3

MA_DQS_L3

MA_DQS_H4

MA_DQS_L4

MA_DQS_H5

MA_DQS_L5

MA_DQS_H6

MA_DQS_L6

MA_DQS_H7

MA_DQS_L7

TYCO_4-1903401-4_AMD

CONN@

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12

E12
C15
E19
F24
AC24
Y19
AB16
Y13

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

DDR_A_D[63..0] <9>

DDR_A_DQS0 <9>
DDR_A_DQS#0 <9>
DDR_A_DQS1 <9>
DDR_A_DQS#1 <9>
DDR_A_DQS2 <9>
DDR_A_DQS#2 <9>
DDR_A_DQS3 <9>
DDR_A_DQS#3 <9>
DDR_A_DQS4 <9>
DDR_A_DQS#4 <9>
DDR_A_DQS5 <9>
DDR_A_DQS#5 <9>
DDR_A_DQS6 <9>
DDR_A_DQS#6 <9>
DDR_A_DQS7 <9>
DDR_A_DQS#7 <9>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

AMD CPU S1G2 DDRII I/F

LA-4481P

646Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

A:Need to re-Link "SGN00000200"

1 1

CLK_CPU_BCLK<16>

+2.5VS

C16

100U_D2_10VM@

Place close to CPU wihtin 1.5"

C20

0718 Silego -- 216 ohm

CLK_CPU_BCLK#<16>

C21 3900P_0402_50V7K

0605 change power rail to solve +3vs leakage

+1.8VS

2 2

LDT_RST#<20>

H_PWRGD_CPU<20>

3 3

LDT_STOP#<12,20>

+1.8VS

R47
300_0402_5%

1 2

4 4

CPU_LDT_REQ#

1

C28

0.01U_0402_25V4Z

@

2

R21
300_0402_5%

1 2

LDT_RST#

1

C22

0.01U_0402_25V4Z

@

2

+1.8VS

R26
300_0402_5%

1 2

H_PWRGD_CPU

2

C24

0.1U_0402_16V4Z

1

+1.8VS

R31
300_0402_5%

1 2

LDT_STOP#

1

C25

0.01U_0402_25V4Z

@

2

CPU_LDT_REQ# <12,20>

A

@

+CPU_CORE_0

R20 10_0402_5%

1 2
1 2

R22 10_0402_5%

+CPU_CORE_1

R23 10_0402_5%

1 2
1 2

R24 10_0402_5%

+3VS

2N7002DW-7-F_SOT363-6

CPU_SID

CPU_SIC

0.215mA

C27

1 2

2200P_0402_50V7K

R29

2.2K_0402_5%
R30

2.2K_0402_5%

+3VS

1

2

0.1U_0402_16V4Z

+1.8V

+1.8V

2200p change to
1000p for ADT7421

CPU_VDD0_FB_H
CPU_VDD0_FB_L

Close to CPU

CPU_VDD1_FB_H
CPU_VDD1_FB_L

R27

20K_0402_5%@

Q14B

@

12

12

C26

THERMDA_CPU
THERMDC_CPU

12

5

4

B

L1

1 2

FBM_L11_201209_300L_0805

1

+

2

3900P_0402_50V7K

1 2

12

R12
169_0402_1%

1 2

1 2

C23 0.1U_0402_16V4Z@

R28

12

34.8K_0402_1%~N@

3

2

61

Q14A

2N7002DW-7-F_SOT363-6@

U1

1

VDD
D+

SDATA

ALERT#

D­THERM#4GND

B

SCLK

2
3

ADM1032ARMZ-2REEL_MSOP8

Address:100_1101

+2.5VDDA

VDDA=300mA

3300P_0402_50V7K

1

1

C18

C174.7U_0805_10V4Z

2

2

Address:100_1100

R16 44.2_0402_1%

1 2

R17 44.2_0402_1%

T6 PAD

T11 PAD
T13 PAD

1 2

CPU_VDD0_FB_H<43>
CPU_VDD0_FB_L<43>

CPU_VDD1_FB_H<43>
CPU_VDD1_FB_L<43>

+1.2V_HT

2.09V for Gate

SMB_EC_DA1 <33,34,35,37>

SMB_EC_CK1 <33,34,35,37>

EC is PU to 5VALW

FDV301N, the Vgs is:
min = 0.65V
Typ = 0.85V
Max = 1.5V

8
7
6
5

SMB_EC_CK2 <34>

SMB_EC_DA2 <34>

1

C19

0.22U_0603_16V4Z

2

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

LDT_RST#
H_PWRGD_CPU
LDT_STOP#
CPU_LDT_REQ#

CPU_SIC
CPU_SID

CPU_HTREF0
CPU_HTREF1

CPU_VDD0_FB_H
CPU_VDD0_FB_L

CPU_VDD1_FB_H

CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI

CPU_TEST23_TSTUPD

CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST27_SINGLECHAIN

R25 0_0402_5%

1 2

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

JCPU1D

F8

VDDA1

F9

VDDA2

A9

CLKIN_H

A8

CLKIN_L

B7

RESET_L

A7

PWROK

F10

LDTSTOP_L

C6

LDTREQ_L

AF4

SIC

AF5

SID

AE6

ALERT_L

R6

HT_REF0

P6

HT_REF1

F6

VDD0_FB_H

E6

VDD0_FB_L

Y6

VDD1_FB_H

AB6

VDD1_FB_L

G10

DBRDY

AA9

TMS

AC9

TCK

AD9

TRST_L

AF9

TDI

AD7

TEST23

H10

TEST18

G9

TEST19

E9

TEST25_H

E8

TEST25_L

AB8

TEST21

AF7

TEST20

AE7

TEST24

AE8

TEST22

AC8

TEST12

AF8

TEST27

C2

TEST9

AA6

TEST6

A3

RSVD1

A5

RSVD2

B3

RSVD3

B5

RSVD4

C1

RSVD5

CONN@

TYCO_4-1903401-4_AMD

+1.8V

R37220_0402_5%@

R36220_0402_5%@

12

12

C

D

+1.8V

M11

KEY1

W18

KEY2

CPU_SVC

SVC
SVD

THERMTRIP_L

PROCHOT_L

MEMHOT_L

THERMDC

THERMDA

VDDIO_FB_H
VDDIO_FB_L

VDDNB_FB_H
VDDNB_FB_L

DBREQ_L

TDO

TEST28_H
TEST28_L

TEST17
TEST16
TEST15
TEST14

TEST7

TEST10

TEST8

TEST29_H
TEST29_L

RSVD10

RSVD9
RSVD8
RSVD7
RSVD6

A6

CPU_SVD

A4

AF6
AC7
AA8

THERMDC_CPU

W7

THERMDA_CPU

W8

W9
Y9

VDD_NB_FB_H

H6

VDD_NB_FB_LCPU_VDD1_FB_L

G6

CPU_DBREQ#

E10

CPU_TDO

AE9

CPU_TEST28_H_PLLCHRZ_P

J7

CPU_TEST28_L_PLLCHRZ_N

H8

CPU_TEST17_BP3

D7

CPU_TEST16_BP2

E7

CPU_TEST15_BP1

F7

CPU_TEST14_BP0

C7
C3

K8
C4

CPU_TEST29_H_FBCLKOUT_P

C9

CPU_TEST29_L_FBCLKOUT_N

C8

H18
H19
AA7
D5
C5

CPU_SVC <43>
CPU_SVD <43>

CPU_THERMTRIP#_R
CPU_PROCHOT#_1.8
CPU_MEMHOT#_1.8V

T4PAD
T5PAD

VDD_NB_FB_H <43>
VDD_NB_FB_L <43>

R13

300_0402_5%@

+1.8V sense no support

0605 change value

R39220_0402_5%@12R40300_0402_5%

R38220_0402_5%@

12

2007/08/02 2008/08/02

HDT Connector

12

@

9/20 SP020016900

Compal Secret Data

JP2

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

2423
26

SAMTEC_ASP-68200-07

Deciphered Date

D

1 2

R5 10K_0402_5%

1 2

R6 300_0402_5%

CPU_THERMTRIP#_R

12

+1.8V

T7PAD
T8PAD

testpoint under package

T9PAD
T10PAD
T12PAD
T14PAD

T15PAD
T16PAD

U2

HDT_RST#

4

E

3 1

MMBT3904_NL_SOT23-3

+1.8V

route as differential
as short as possible

+3VS

5

LDT_RST#

2

P

B

Y

1

A

G

NC7SZ08P5X_NL_SC70-5@

3

Custom

E

R7 0_0402_5%@

B

2

Q2

C

R10 10K_0402_5%@

1 2

R11 300_0402_5%

CPU_PROCHOT#_1.8

1 2
1 2

R8 0_0402_5%

1 2

R9 0_0402_5%

12

B

2

MMBT3904_NL_SOT23-3
Q3

E

3 1

C

R246 0_0402_5%@

1 2

CPU_SVC
CPU_SVD

VDD_NB_FB_H
VDD_NB_FB_L

EN0 <37,39>
H_THERMTRIP#_EC <34>
H_THERMTRIP# <21>

@

H_PROCHOT# <20>

R14 1K_0402_5%

1 2
1 2

R15 1K_0402_5%

+CPU_CORE_NB

R18 10_0402_5%

1 2
1 2

R19 10_0402_5%

+1.8V

Close to CPU

+1.8V

CPU_TEST27_SINGLECHAIN

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

SB_PWRGD <21,34,43>

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

AMD CPU S1G2 CTRL

R32 300_0402_5%@

R33 300_0402_5%
R34 300_0402_5%@
R35 300_0402_5%
R41 300_0402_5%@
R42 300_0402_5%@
R43 300_0402_5%@
R44 300_0402_5%@
R45 300_0402_5%@
R46 300_0402_5%@

LA-4481P

E

1 2

1 2

12
12
12
12
12
12
12
12

746Monday, September 08, 2008

of

0.4

http://mycomp.su/x/

A

B

C

D

E

VDD(+CPU_CORE) decoupling.

+CPU_CORE_0

1

+

1 1

C29
330U_X_2VM_R6M

2

1

+

C30
330U_X_2VM_R6M

2

Near CPU Socket

+CPU_CORE_0

1

C35

2

22U_0805_6.3V6M

1

C43
180P_0402_50V8J

2

1

C36
22U_0805_6.3V6M

2

Under CPU Socket

1

C33

2

22U_0805_6.3V6M

+CPU_CORE_0

1

C41

0.22U_0603_16V4Z

2

2 2

1

C34

2

22U_0805_6.3V6M

1

C42

0.01U_0402_25V4Z

2

+CPU_CORE_1

+CPU_CORE_1

1

C37
22U_0805_6.3V6M

2

1

+

C31
330U_X_2VM_R6M

2

+CPU_CORE_1

1

C38
22U_0805_6.3V6M

2

1

C44

0.22U_0603_16V4Z

2

1

+

C32
330U_X_2VM_R6M

2

1

C39
22U_0805_6.3V6M

2

1

C45

0.01U_0402_25V4Z

2

1

C40
22U_0805_6.3V6M

2

1

C46
180P_0402_50V8J

2

2000mA

18000mA 18000mA

3000mA

+CPU_CORE_NB

+1.8V

G4
H2

J9
J11
J13
J15

K6
K10
K12
K14

L4

L7

L9
L11
L13
L15

M2

M6

M8

M10

N7

N9

N11

K16

M16

P16
T16
V16

H25

J17
K18
K21
K23
K25
L17

M18
M21
M23
M25
N17

JCPU1E

VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12

Athlon 64 S1
Processor Socket

VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8

VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26

VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13

TYCO_4-1903401-4_AMD

CONN@

+CPU_CORE_1+CPU_CORE_0

P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2

Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18

+1.8V

+CPU_CORE_NB decoupling.

VDDIO decoupling.

+1.8V

1

C50
22U_0805_6.3V6M

2

3 3

+1.8V

1

C57

0.22U_0603_16V4Z

2

+1.8V +1.8V

1

C69

0.01U_0402_25V4Z

2

4 4

+1.8V

1

2

C84

4.7U_0805_10V4Z

1

C51
22U_0805_6.3V6M

2

1

C52

0.22U_0603_16V4Z

2

1

C53

0.22U_0603_16V4Z

2

Under CPU Socket

Between CPU Socket and DIMM

1

C58

0.22U_0603_16V4Z

2

1

C70

0.01U_0402_25V4Z

2

1

2

A

C85

4.7U_0805_10V4Z

1

C59

0.22U_0603_16V4Z

2

180PF Qt'y follow the distance between
CPU socket and DIMM0. <2.5inch>

1

C71
180P_0402_50V8J

2

1

C86

4.7U_0805_10V4Z

2

1

C60

0.22U_0603_16V4Z

2

1

2

1

2

C72
180P_0402_50V8J

C87

4.7U_0805_10V4Z

1

C54

180P_0402_50V8J

2

1

C73
180P_0402_50V8J

2

1

C: Change to NBO CAP

+

C83
220U_Y_4VM

@

2

B

1

C55
180P_0402_50V8J

2

1

C74
180P_0402_50V8J

2

+CPU_CORE_NB

1

C47
22U_0805_6.3V6M

2

VTT decoupling.

+0.9V

1

C61

4.7U_0805_10V4Z

2

+0.9V

1

C75

4.7U_0805_10V4Z

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Near CPU Socket Right side.

Near CPU Socket Left side.

Issued Date

1

C62

4.7U_0805_10V4Z

2

1

C76

4.7U_0805_10V4Z

2

C

1

C48
22U_0805_6.3V6M

2

2007/08/02 2008/08/02

1

2

1

C63

0.22U_0603_16V4Z

2

1

C77

0.22U_0603_16V4Z

2

C49

@

22U_0805_6.3V6M

+0.9V

Near Power Supply

1

C: Change to NBO CAP

+

C56
220U_Y_4VM

2

1

C64

0.22U_0603_16V4Z

2

1

C78

0.22U_0603_16V4Z

2

Compal Secret Data

Deciphered Date

1

C65
1000P_0402_25V8J

2

1

C79
1000P_0402_25V8J

2

D

1

C66
1000P_0402_25V8J

2

1

C80
1000P_0402_25V8J

2

1

C67
180P_0402_50V8J

2

1

C81
180P_0402_50V8J

2

Title

Size Document Number Rev

Custom

Date: Sheet

JCPU1F

AA11
AA13
AA15
AA17
AA19

AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21

AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23

AA4

AB2
AB7
AB9

AD6
AD8

B4
B6
B8

B9
B11
B13
B15
B17
B19
B21
B23
B25

D6
D8

D9
D11
D13
D15
D17
D19
D21
D23
D25

E4

F2
F11
F13
F15
F17
F19
F21
F23
F25

H7

H9
H21
H23

J4

1

2

1

2

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

Athlon 64 S1

TYCO_4-1903401-4_AMD

Processor Socket

C68
180P_0402_50V8J

C82
180P_0402_50V8J

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

CONN@

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

Compal Electronics, Inc.

AMD CPU S1G2 PWR & GND

LA-4481P

846Monday, September 08, 2008

E

of

0.4

http://mycomp.su/x/

A

B

C

D

E

4.5A 2A

DDR_A_D0
DDR_A_D1

1 1

2 2

DDR_CKE0_DIMMA<6>

DDR_A_BS#2<6>

DDR_A_BS#0<6>
DDR_A_WE#<6>

DDR_A_CAS#<6>
DDR_CS1_DIMMA#<6>

DDR_A_ODT1<6>

3 3

SMB_CK_DAT0<10,16,21,31>
SMB_CK_CLK0<10,16,21,31>

4 4

A

+3VS

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16 DDR_A_D20
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1 DDR_A_MA0

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS# DDR_A_ODT0
DDR_CS1_DIMMA#

DDR_A_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59

1

C104

0.1U_0402_16V4Z

2

JDIMM1

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

TYCO_292527-4

CONN@

+V_DDR_MCH_REF

DQS3#

NC/CKE1

NC/A15
NC/A14

NC/A13

DQS5#

DQS7#

B

DQ12
DQ13

CK0#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3
DQ30

DQ31

RAS#

ODT0

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DQ54
DQ55

DQ60
DQ61

DQS7
DQ62

DQ63

GND

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS
CK0

VSS

VSS

VSS

VSS
DM2

VSS

VSS

VSS

VSS

VSS
VDD

VDD

VDD

VDD
BA1

VDD

VDD
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SAO
SA1

+1.8V+1.8V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202

DDR_A_D4
DDR_A_D5

DDR_A_DM0
DDR_A_D6

DDR_A_D7
DDR_A_D12

DDR_A_D13
DDR_A_DM1

DDR_A_D14
DDR_A_D15

DDR_A_D21

DDR_A_DM2
DDR_A_D22

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53

DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_A_D[0..63]

DDR_A_DM[0..7]

DDR_A_DQS[0..7]

DDR_A_MA[0..15]

DDR_A_DQS#[0..7]

DDR_A_CLK0 <6>
DDR_A_CLK#0 <6>

+V_DDR_MCH_REF

1

C97

2

1000P_0402_25V8J

0.1U_0402_16V4Z

DDR_CKE1_DIMMA <6>

DDR_A_BS#1 <6>
DDR_A_RAS# <6>
DDR_CS0_DIMMA# <6>

DDR_A_ODT0 <6>

DDR_A_CLK1 <6>
DDR_A_CLK#1 <6>

C

DDR_A_D[0..63] <6>
DDR_A_DM[0..7] <6>

DDR_A_DQS[0..7] <6>

DDR_A_MA[0..15] <6>

DDR_A_DQS#[0..7] <6>

+1.8V

R48
1K_0402_1%

1 2

1

C98

2

2007/08/02 2008/08/02

+V_DDR_MCH_REF <10>

R49
1K_0402_1%

1 2

Compal Secret Data

Deciphered Date

D

DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_CKE1_DIMMA
DDR_A_MA15

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1

DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12

DDR_A_BS#0
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3

DDR_A_ODT1
DDR_CS1_DIMMA#
DDR_A_CAS#
DDR_A_WE#

DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_ODT0
DDR_A_MA13

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

Cross between +1.8V and +0.9V power plan

Title

Size Document Number Rev

Custom

Date: Sheet

+0.9V

RP1

18

1 2

C88 0.1U_0402_16V4Z

27

1 2

36

C89 0.1U_0402_16V4Z

45

RP2

18
27
36
45

RP3

18
27
36
45

RP4

18
27
36
45

RP5

18
27
36
45

RP6

18
27
36
45

RP7

18
27
36
45

1 2

C90 0.1U_0402_16V4Z

1 2

C91 0.1U_0402_16V4Z

1 2

C92 0.1U_0402_16V4Z

1 2

C93 0.1U_0402_16V4Z

1 2

C94 0.1U_0402_16V4Z

1 2

C95 0.1U_0402_16V4Z

1 2

C96 0.1U_0402_16V4Z

1 2

C99 0.1U_0402_16V4Z

1 2

C100 0.1U_0402_16V4Z

1 2

C101 0.1U_0402_16V4Z

1 2

C102 0.1U_0402_16V4Z

1 2

C103 0.1U_0402_16V4Z

Compal Electronics, Inc.

DDRII SO-DIMM 0

LA-4481P

E

+1.8V

946Monday, September 08, 2008

0.4

of

http://mycomp.su/x/

A

B

C

D

E

4.5A

JDIMM2

+V_DDR_MCH_REF<9>

1

C107

1 1

1000P_0402_25V8J

2 2

3 3

4 4

2

DDR_CKE0_DIMMB<6>

DDR_B_BS#2<6>

DDR_B_BS#0<6>
DDR_B_WE#<6>

DDR_B_CAS#<6>
DDR_CS1_DIMMB#<6>

DDR_B_ODT1<6>

SMB_CK_DAT0<9,16,21,31>
SMB_CK_CLK0<9,16,21,31>

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D13

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D21
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18 DDR_B_D22
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE0_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS# DDR_B_ODT0
DDR_CS1_DIMMB#

DDR_B_ODT1
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43 DDR_B_D47
DDR_B_D48

DDR_B_D49 DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51 DDR_B_D55

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59

+3VS

0.1U_0402_16V4Z

C120

1

2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

TYCO_292531-4

CONN@

VSS
DQ4
DQ5

VSS
DM0
VSS
DQ6
DQ7
VSS

DQ12
DQ13

VSS
DM1
VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS
DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1

RAS#

S0#
VDD

ODT0

NC/A13

VDD
VSS

DQ36
DQ37

VSS
DM4
VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6
VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS
SAO

SA1

NC

A7
A6

A4
A2
A0

NC

+1.8V+1.8V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D9
DDR_B_DM1

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D16

DDR_B_DM2

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE1_DIMMB
DDR_B_MA15

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6DDR_B_MA8

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#

DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D52

DDR_B_DM6
DDR_B_D54

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

+3VS

DDR_B_D[0..63]

DDR_B_DM[0..7]

DDR_B_DQS[0..7]

DDR_B_MA[0..15]

DDR_B_DQS#[0..7]

DDR_B_CLK0 <6>
DDR_B_CLK#0 <6>

DDR_CKE1_DIMMB <6>

DDR_B_BS#1 <6>
DDR_B_RAS# <6>
DDR_CS0_DIMMB# <6>

DDR_B_ODT0 <6>

DDR_B_CLK1 <6>
DDR_B_CLK#1 <6>

DDR_B_D[0..63] <6>

DDR_B_DM[0..7] <6>

DDR_B_DQS[0..7] <6>

DDR_B_MA[0..15] <6>

DDR_B_DQS#[0..7] <6>

DDR_B_MA6
DDR_B_MA2
DDR_B_MA0
DDR_CS0_DIMMB#

DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA4

DDR_B_BS#2
DDR_CKE0_DIMMB
DDR_B_MA15
DDR_CKE1_DIMMB

DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12

DDR_B_BS#0
DDR_B_MA10
DDR_B_MA1
DDR_B_MA3

DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_B_CAS#
DDR_B_WE#

DDR_B_BS#1
DDR_B_RAS#
DDR_B_ODT0
DDR_B_MA13

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

Cross between +1.8V and +0.9V power plan

RP8

RP9

RP10

RP11

RP12

RP13

RP14

+0.9V

18

C105 0.1U_0402_16V4Z

27
36

1 2

C106 0.1U_0402_16V4Z

45

18

C108 0.1U_0402_16V4Z

27
36

1 2

C109 0.1U_0402_16V4Z

45

18

C110 0.1U_0402_16V4Z

27
36

1 2

C111 0.1U_0402_16V4Z

45

18

C112 0.1U_0402_16V4Z

27

1 2

36

C113 0.1U_0402_16V4Z

45

18

C114 0.1U_0402_16V4Z

27
36

1 2

C115 0.1U_0402_16V4Z

45

18

C116 0.1U_0402_16V4Z

27
36

1 2

C117 0.1U_0402_16V4Z

45

18

C118 0.1U_0402_16V4Z

27
36

1 2

C119 0.1U_0402_16V4Z

45

12

12

12

12

12

12

12

+1.8V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRII SO-DIMM 1

LA-4481P

10 46Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

U3B

D4

GFX_RX0P

C4

GFX_RX0N

A3

GFX_RX1P

B3

GFX_RX1N

C2

GFX_RX2P

C1

GFX_RX2N

E5

GFX_RX3P

F5

GFX_RX3N

G5

GFX_RX4P

G6

AE3
AD4
AE2
AD3
AD1
AD2

W6

AA8
AA7
AA5

AA6

W5

H5
H6

J6
J5
J7
J8
L5
L6

M8

L8
P7

M7

P5
M5
R8

P8
R6
R5

P4

P3

T4

T3

V5
U5

U6
U8
U7

Y8

Y7

Y5

GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

1 1

PCIE_PTX_C_IRX_P0<27>
PCIE_PTX_C_IRX_N0<27>

PCIE_PTX_C_IRX_P2<27>
PCIE_PTX_C_IRX_N2<27>
GLAN_RXP<26>

2 2

GLAN_RXN<26>

SB_RX0P<20>
SB_RX0N<20>
SB_RX1P<20>
SB_RX1N<20>
SB_RX2P<20>
SB_RX2N<20>
SB_RX3P<20>
SB_RX3N<20>

RS780M_FCBGA528

PART 2 OF 6

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F SB

PCE_CALRP(PCE_BCALRP)

PCE_CALRN(PCE_BCALRN)

RS780M Display Port Support (muxed on GFX)

DP0

DP1

3 3

GFX_TX0,TX1,TX2 and TX3
AUX0 and HPD0

GFX_TX4,TX5,TX6 and TX7
AUX1 and HPD1

B

GFX_TX0P

GFX_TX0N

GFX_TX1P

GFX_TX1N

GFX_TX2P

GFX_TX2N

GFX_TX3P

GFX_TX3N

GFX_TX4P

GFX_TX4N

GFX_TX5P

GFX_TX5N

GFX_TX6P

GFX_TX6N

GFX_TX7P

GFX_TX7N

GFX_TX8P

GFX_TX8N

GFX_TX9P

GFX_TX9N

GFX_TX10P

GFX_TX10N

GFX_TX11P

GFX_TX11N

GFX_TX12P

GFX_TX12N

GFX_TX13P

GFX_TX13N

GFX_TX14P

GFX_TX14N

GFX_TX15P

GFX_TX15N

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

PCIE_ITX_PRX_P0

AC1

PCIE_ITX_PRX_N0

AC2
AB4
AB3

PCIE_ITX_PRX_P2

AA2

PCIE_ITX_PRX_N2

AA1

PCIE_ITX_PRX_P3

Y1

PCIE_ITX_PRX_N3

Y2
Y4
Y3
V1
V2

SB_TX0P_C

AD7

SB_TX0N_C

AE7

SB_TX1P_C

AE6

SB_TX1N_C

AD6

SB_TX2P_C

AB6

SB_TX2N_C

AC6

SB_TX3P_C

AD5

SB_TX3N_C

AE5
AC8

AB8

TMDS_B_DATA2 <19>
TMDS_B_DATA2# <19>
TMDS_B_DATA1 <19>
TMDS_B_DATA1# <19>
TMDS_B_DATA0 <19>
TMDS_B_DATA0# <19>
TMDS_B_CLK <19>
TMDS_B_CLK# <19>

C121 0.1U_0402_16V7K
C122 0.1U_0402_16V7K

C125 0.1U_0402_16V7K
C126 0.1U_0402_16V7K
C127 0.1U_0402_16V7K
C128 0.1U_0402_16V7K

C131 0.1U_0402_16V7K
C132 0.1U_0402_16V7K
C133 0.1U_0402_16V7K
C134 0.1U_0402_16V7K
C135 0.1U_0402_16V7K
C136 0.1U_0402_16V7K
C137 0.1U_0402_16V7K
C138 0.1U_0402_16V7K

R50 1.27K_0402_1%

1 2

R51 2K_0402_1%

1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2

1 2

1 2

1 2

1 2

1 2

+1.1VS

C

PCIE_ITX_C_PRX_P0 <27>
PCIE_ITX_C_PRX_N0 <27>

PCIE_ITX_C_PRX_P2 <27>
PCIE_ITX_C_PRX_N2 <27>
GLAN_TXP <26>
GLAN_TXN <26>

SB_TX0P <20>
SB_TX0N <20>
SB_TX1P <20>
SB_TX1N <20>
SB_TX2P <20>
SB_TX2N <20>
SB_TX3P <20>
SB_TX3N <20>

New Card

WLAN
GLAN

H_CADOP[0..15]<5>
H_CADON[0..15]<5> H_CADIN[0..15] <5>

H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

H_CLKOP0<5>
H_CLKON0<5>
H_CLKOP1<5>
H_CLKON1<5>

H_CTLOP0<5>
H_CTLON0<5>

H_CTLON1<5>

0718 Place within 1"
layout 1:2

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1

R52 301_0402_1%

1 2

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7

H_CADOP8
H_CADON8
H_CADOP9
H_CADON9

D

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

AC24
AC25
AB25
AB24
AA24
AA25

Y22

Y23
W21
W20

V21

V20

U20

U21

U19

U18

T22

T23

AB23
AA22

M22
M23

R21

R20

C23

A24

H_CADON[0..15]

U3A

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_RXCALP
HT_RXCALN

RS780M_FCBGA528

H_CADIP[0..15]H_CADOP[0..15]
H_CADIN[0..15]

PART 1 OF 6

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P

HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

HT_TXCLK0P

HT_TXCLK0N

HT_TXCLK1P

HT_TXCLK1N

HYPER TRANSPORT CPU I/F

HT_TXCTL0P

HT_TXCTL0N

HT_TXCTL1P

HT_TXCTL1N

HT_TXCALP
HT_TXCALN

H_CADIP[0..15] <5>

H_CADIP0

D24

H_CADIN0

D25

H_CADIP1

E24

H_CADIN1

E25

H_CADIP2

F24

H_CADIN2

F25

H_CADIP3

F23

H_CADIN3

F22

H_CADIP4

H23

H_CADIN4

H22

H_CADIP5

J25

H_CADIN5

J24

H_CADIP6

K24

H_CADIN6

K25

H_CADIP7

K23

H_CADIN7

K22

H_CADIP8

F21

H_CADIN8

G21

H_CADIP9

G20

H_CADIN9

H21

H_CADIP10

J20

H_CADIN10

J21

H_CADIP11

J18

H_CADIN11

K17

H_CADIP12

L19

H_CADIN12

J19

H_CADIP13

M19

H_CADIN13

L18

H_CADIP14

M21

H_CADIN14

P21

H_CADIP15

P18

H_CADIN15

M18
H24

H25
L21
L20

H_CTLIP0

M24

H_CTLIN0

M25

H_CTLIP1

P19

H_CTLIN1

R18
B24

B25

0718 Place within 1"
layout 1:2

E

H_CLKIP0 <5>
H_CLKIN0 <5>
H_CLKIP1 <5>
H_CLKIN1 <5>

H_CTLIP0 <5>

H_CTLIN0 <5>

H_CTLIP1 <5>H_CTLOP1<5>

H_CTLIN1 <5>

R53 301_0402_1%

1 2

NEED CHECK R68 & R69 WITH AMD

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

RS780-HT/PCIE

LA-4481P

11 46Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

1 1

B

C

D

E

+3VS

1 2

+1.8VS

BLM18PG121SN1D_0603

0605 remove 0 ohm resisters

LDT_STOP#<7,20>

CPU_LDT_REQ#<7,20>

LDT_STOP#

CPU_LDT_REQ#

+1.8VS

1 2

BLM18PG121SN1D_0603

2.2U_0603_6.3V4Z

140OHM

1

C142

2.2U_0603_6.3V4Z

1

2

2

NB_PWRGD<21>

+1.8VS

GREEN

PLT_RST#<15,20,26,27,33,34>

RS780_DFT_GPIO_0<15>

RED

BLUE

NB_OSC_14.318M<16>

CLK_SBLINK_BCLK<16>
CLK_SBLINK_BCLK#<16>

LCD_DDC_CLK<18>
HDMIDAT_UMA<19>

HDMICLK_UMA<19>

LCD_DDC_DAT<18>

+NB_PLLVDD
+NB_HTPVDD

+VDDA18HTPLL
+VDDA18PCIEPLL

NBGFX_CLK<16>
NBGFX_CLK#<16>

1 2

R56 140_0402_1%

1 2

R57 150_0402_1%

1 2

R58 150_0402_1%

2 2

200 Ohm @ 100Mhz

200 Ohm @ 100Mhz 20mA

3 3

200 Ohm @ 100Mhz

200 Ohm @ 100Mhz

+1.8VS

BLM18PG121SN1D_0603

+1.8VS

L9

1 2

BLM18PG121SN1D_0603

2.2U_0603_6.3V4Z

+1.1VS

+1.1VS

+1.8VS

BLM18PG121SN1D_0603

L8

1 2

1

C146

2

1 2

R64

4.7K_0402_5%

L5

1 2

BLM18PG121SN1D_0603

L6

1 2

C143

2.2U_0603_6.3V4Z

1

C145

2.2U_0603_6.3V4Z

2

1 2

R65

4.7K_0402_5%

0605 umount to follow Trinity

L3

0_0603_5%

L4

+AVDDQ

C141

T17 PAD
T18 PAD
T19 PAD

RED<17>
GREEN<17>
BLUE<17>

CRT_HSYNC<15,17>

CRT_VSYNC<15,17>
UMA_CRT_CLK<17>
UMA_CRT_DAT<17>

R60 0_0402_5%

1 2

1 2

R61 300_0402_5%

CLK_NBHT<16>
CLK_NBHT#<16>

+3VS

AUX_CAL<15>

1

4mA

2

R59 715_0402_1%

L2

+AVDD1

+AVDD2

1

C140

2.2U_0603_6.3V4Z

2

RED
GREEN
BLUE

1 2

120mA

NB_RESET#
NB_PWRGD
LDT_STOP#

CPU_LDT_REQ#

Strap pin

R67 10K_0402_5%@

Strap pin

110mA

1

2

20mA

TV_CRMA
TV_LUMA
TV_COMPS

CRT_HSYNC
CRT_VSYNC

20mA
20mA

12

C139

2.2U_0603_6.3V4Z

U3C

F12

AVDD1(NC)

E12

AVDD2(NC)

F14

AVDDDI(NC)

G15

AVSSDI(NC)

H15

AVDDQ(NC)

H14

AVSSQ(NC)

E17

C_Pr(DFT_GPIO5)

F17

Y(DFT_GPIO2)

F15

COMP_Pb(DFT_GPIO4)

G18

RED(DFT_GPIO0)

G17

REDb(NC)

E18

GREEN(DFT_GPIO1)

F18

GREENb(NC)

E19

BLUE(DFT_GPIO3)

F19

BLUEb(NC)

A11

DAC_HSYNC(PWM_GPIO4)

B11

DAC_VSYNC(PWM_GPIO6)

F8

DAC_SCL(PCE_RCALRN)

E8

DAC_SDA(PCE_TCALRN)

G14

DAC_RSET(PWM_GPIO1)

A12

PLLVDD(NC)

D14

PLLVDD18(NC)

B12

PLLVSS(NC)

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESETb

A10

POWERGOOD

C10

LDTSTOPb

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN(OSCIN)

F11

REFCLK_N(PWM_GPIO3)

T2

GFX_REFCLKP

T1

GFX_REFCLKN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP(SB_REFCLKP)

V3

GPPSB_REFCLKN(SB_REFCLKN)

B9

I2C_CLK

A9

I2C_DATA

B8

DDC_DATA0/AUX0N(NC)

A8

DDC_CLK0/AUX0P(NC)

B7

DDC_CLK1/AUX1P(NC)

A7

DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

AUX_CAL(NC)

RS780M_FCBGA528

PART 3 OF 6

TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)

TXOUT_U3P(PCIE_RESET_GPIO5)

CRT/TVOUT

TXCLK_UP(PCIE_RESET_GPIO4)

TXCLK_UN(PCIE_RESET_GPIO1)

LVTM

PM

LVDS_DIGON(PCE_TCALRP)

LVDS_BLON(PCE_RCALRP)

LVDS_ENA_BL(PWM_GPIO2)

CLOCKs PLL PWR

MIS.

TXOUT_L0P(NC)

TXOUT_L0N(NC)

TXOUT_L1P(NC)

TXOUT_L1N(NC)

TXOUT_L2P(NC)

TXOUT_L2N(DBG_GPIO0)

TXOUT_L3P(NC)

TXOUT_L3N(DBG_GPIO2)

TXOUT_U0P(NC)
TXOUT_U0N(NC)

TXOUT_U2P(NC)
TXOUT_U2N(NC)

TXOUT_U3N(NC)

TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)

VDDLTP18(NC)
VSSLTP18(NC)

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

TMDS_HPD(NC)

SUS_STAT#(PWM_GPIO5)

HPD(NC)

THERMALDIODE_P
THERMALDIODE_N

TESTMODE

A22
B22
A21
B21
B20
A20
A19
B19

B18
A18
A17
B17
D20
D21
D18
D19

B16
A16
D16
D17

+VDDLTP18

A13
B13

A15
B15
A14
B14

C14
D15
C16
C18
C20
E20
C22

E9
F7
G12

LVDS_ENA_BL

D9
D10

D12

NB_THERMAL_DA

AE8

NB_THERMAL_DC

AD8

1 2

D13

R68

1.8K_0402_5%

LVDS_A0+ <18>
LVDS_A0- <18>
LVDS_A1+ <18>
LVDS_A1- <18>
LVDS_A2+ <18>
LVDS_A2- <18>

LVDS_ACLK+ <18>
LVDS_ACLK- <18>

+VDDLT18

C147

0.1U_0402_16V4Z

LVDS_DIGON
BLON

1 2

R66 0_0402_5%

2.2U_0603_6.3V4Z

1

C144

2

1

1

2

2

R62 0_0402_5%

1 2

R63

1 2

0_0402_5%

R76 0_0402_5%

1 2

300mA

1

0.1U_0402_16V4Z
C444

2

L10

1 2

BLM18PG121SN1D_0603

C148

4.7U_0805_10V4Z

LCD_BLON

HPD <19>
SUS_STAT_R# <15>

SUS_STAT# <21>

T20PAD
T21PAD

L7

1 2

BLM18PG121SN1D_0603

+1.8VS

+1.8VS

80mA

0901 uninstall D39 without VB
0801 Change Vari-Bright circuit

21

CH751H-40PT_SOD323-2

ENBKL <34>

LVDS_ENA_BL <18>

D39

@

UMA_ENVDD <18>
LVDS_BLON <18>

Strap pin

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

RS780 VEDIO/CLK GEN

LA-4481P

12 46Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

Side-Port DDR2 SDRAM
512Mbits(32Mbx16)-64MB

B

C

D

E

1 1

MEM_BA0
MEM_BA1

MEM_A12
MEM_A11
MEM_A10
MEM_A9
MEM_A8
MEM_A7
MEM_A6
MEM_A5
MEM_A4
MEM_A3
MEM_A2
MEM_A1

12

R69

100_0402_1%

2 2

3 3

MEM_A0

MEM_CLKN
MEM_CLKP

MEM_CKE

MEM_CS#
MEM_WE#
MEM_RAS#
MEM_CAS#
MEM_DM0

MEM_DM1

MEM_ODT

MEM_DQS_P0
MEM_DQS_N0

MEM_DQS_P1
MEM_DQS_N1

+MEM_VREF

MEM_BA2

U4

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25@

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

MEM_DQ15

B9

MEM_DQ11

B1

MEM_DQ13

D9

MEM_DQ12

D1
D3

MEM_DQ10

D7
C2

MEM_DQ14

C8

MEM_DQ3

F9

MEM_DQ7

F1

MEM_DQ1

H9

MEM_DQ6

H1

MEM_DQ5

H3

MEM_DQ0

H7

MEM_DQ4

G2

MEM_DQ2

G8

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

+VDDL

+1.8V_MEM_VDDQ

+1.8V_MEM_VDDQ

L13

1 2

0_0603_5%

1

C152

1U_0603_10V6K

2

Layout Note: 50 mil for VSSDL

R70 40.2_0402_1%
R71 40.2_0402_1%

+1.8V_MEM_VDDQ

12
12

MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10MEM_DQ8
MEM_A11
MEM_A12MEM_DQ9

MEM_BA0
MEM_BA1
MEM_BA2

MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_ODT

MEM_CLKP
MEM_CLKN

MEM_COMP_P
MEM_COMP_N

U3D

AB12

MEM_A0(NC)

AE16

MEM_A1(NC)

V11

MEM_A2(NC)

AE15

MEM_A3(NC)

AA12

MEM_A4(NC)

AB16

MEM_A5(NC)

AB14

MEM_A6(NC)

AD14

MEM_A7(NC)

AD13

MEM_A8(NC)

AD15

MEM_A9(NC)

AC16

MEM_A10(NC)

AE13

MEM_A11(NC)

AC14

MEM_A12(NC)

Y14

MEM_A13(NC)

AD16

MEM_BA0(NC)

AE17

MEM_BA1(NC)

AD17

MEM_BA2(NC)

W12

MEM_RASb(NC)

Y12

MEM_CASb(NC)

AD18

MEM_WEb(NC)

AB13

MEM_CSb(NC)

AB18

MEM_CKE(NC)

V14

MEM_ODT(NC)

V15

MEM_CKP(NC)

W14

MEM_CKN(NC)

AE12

MEM_COMPP(NC)

AD12

MEM_COMPN(NC)

RS780M_FCBGA528

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)

MEM_DQ2/DVO_DE(NC)

MEM_DQ3/DVO_D0(NC)

MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)

MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)

MEM_DQ12(NC)

MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)

MEM_DQS1P(NC)
MEM_DQS1N(NC)

MEM_DM0(NC)

MEM_DM1/DVO_D8(NC)

SBD_MEM/DVO_I/F

IOPLLVDD18(NC)

IOPLLVDD(NC)

IOPLLVSS(NC)

MEM_VREF(NC)

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

Y17
W18
AD20
AE21

W17
AE19

AE23
AE24

AD23
AE18

MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15

MEM_DQS_P0
MEM_DQS_N0
MEM_DQS_P1
MEM_DQS_N1

MEM_DM0
MEM_DM1

+NB_IOPLLVDD

+MEM_VREF1

MEM_COMP_P and MEM_COMP_N trace
width >=10mils and 10mils spacing from
other Signals in X,Y,Z directions

15mA

1 2

BLM18PG121SN1D_0603

1

C149

2.2U_0603_6.3V4Z

2

L12

+1.8V_IOPLLVDD

1

2

AMD recommends 200 Ohm @ 100Mhz

+1.1VS

C151

0.1U_0402_16V4Z

L11

1 2

BLM18PG121SN1D_0603

1

C150

2.2U_0603_6.3V4Z

2

+1.8VS

Side Port disable,VREF need
connect to +1.8VS for DDR2

+1.8V_MEM_VDDQ+1.8V_MEM_VDDQ

1

C153

2

R72

1 2

1K_0402_1%

0.1U_0402_16V4Z

+MEM_VREF

4 4

1

C160

2

R74

0.1U_0402_16V4Z

1 2

1K_0402_1%

A

C154

C161

1

2

R73

1 2

1K_0402_1%

0.1U_0402_16V4Z

+MEM_VREF1

1

2

R75

0.1U_0402_16V4Z

1 2

1K_0402_1%

2

C155

1

B

2

C156

1

1U_0402_6.3V4Z

1

C157

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

C158

1

2

0.1U_0402_16V4Z

+1.8V_MEM_VDDQ

1

C159

2

L14

1 2

0_0805_5%

220 ohm @ 100MHz,2A

22U_0805_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

+1.8VS

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

D

ZZZ2

VRAM_x76

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

RS780 Side-Port DDR2 SDRAM

LA-4481P

13 46Monday, September 08, 2008

E

of

0.4

http://mycomp.su/x/

A

B

C

D

E

1 1

L15 0_0805_5%

+1.2V_HT

1 2

L17 0_0805_5%

1 2

4.7U_0805_10V4Z

1 2

0_0805_5%

1 2

L22

4.7U_0805_10V4Z

4.7U_0805_10V4Z

C172

0_0805_5%

L18

4.7U_0805_10V4Z

4.7U_0805_10V4Z

C197

0.1U_0402_16V4Z

1

C162

2

0.1U_0402_16V4Z

1

C173

2

1

C180

2

0.1U_0402_16V4Z

1

1

C198

2

2

+1.8VS

1U_0402_6.3V4Z

C163

1

2

1

C174

2

0.1U_0402_16V4Z

1

C181

2

0.1U_0402_16V4Z

1

C199

2

0.1U_0402_16V4Z

C208

+1.1VS

2 2

+1.8VS

3 3

0.1U_0402_16V4Z
C165

1

C164

2

0.1U_0402_16V4Z

0.7A

0.1U_0402_16V4Z
C175

1

1

2

2

0.4A

1

C182

C183

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C200

C201

2

0.1U_0402_16V4Z

1

2

0.6A

1

2

1

2

1

C184

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C202

2

+VDDHT

1

C166

0.1U_0402_16V4Z

2

+VDDHTRX

C176

0.1U_0402_16V4Z

+VDDHTTX

1

2

0.7A

1

2

10mA

+1.8VS

25 mA

+VDDA18PCIE

1

2

U3E

J17

VDDHT_1

K16

VDDHT_2

L16

VDDHT_3

M16

VDDHT_4

P16

VDDHT_5

R16

VDDHT_6

T16

VDDHT_7

H18

VDDHTRX_1

G19

VDDHTRX_2

F20

VDDHTRX_3

E21

VDDHTRX_4

D22

VDDHTRX_5

B23

VDDHTRX_6

A23

VDDHTRX_7

AE25

VDDHTTX_1

AD24

VDDHTTX_2

AC23

VDDHTTX_3

AB22

VDDHTTX_4

AA21

VDDHTTX_5

Y20

VDDHTTX_6

W19

VDDHTTX_7

V18

VDDHTTX_8

U17

VDDHTTX_9

T17

VDDHTTX_10

R17

VDDHTTX_11

P17

VDDHTTX_12

M17

VDDHTTX_13

J10

VDDA18PCIE_1

P10

VDDA18PCIE_2

K10

VDDA18PCIE_3

M10

VDDA18PCIE_4

L10

VDDA18PCIE_5

W9

VDDA18PCIE_6

H9

VDDA18PCIE_7

T10

VDDA18PCIE_8

R10

VDDA18PCIE_9

Y9

VDDA18PCIE_10

AA9

VDDA18PCIE_11

AB9

VDDA18PCIE_12

AD9

VDDA18PCIE_13

AE9

VDDA18PCIE_14

U10

VDDA18PCIE_15

F9

VDD18_1

G9

VDD18_2

AE11

VDD18_MEM1(NC)

AD11

VDD18_MEM2(NC)

RS780M_FCBGA528

C209
1U_0402_6.3V4Z

PART 5/6

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8

VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12

POWER

VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

VDD33_1(NC)
VDD33_2(NC)

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

AE10
AA11
Y11
AD10
AB10
AC10

H11
H12

2.5A

+VDDA11PCIE

1

C1860.1U_0402_16V4Z

2

+1.8VS

+3VS

60mA

FBMA-L11-201209-221LMA30T_0805

C167
C168
C169 1U_0402_6.3V4Z
C170 1U_0402_6.3V4Z
C171 1U_0402_6.3V4Z
C177 1U_0402_6.3V4Z

C178 0.1U_0402_16V4Z
C179 0.1U_0402_16V4Z

L16

1 2

1 2
1 2
1 2
1 2

12
12

4.7U_0805_10V4Z
10U_0805_10V4Z

0605 change to jump pad

+1.1VS +NB_VDDC

PAD-OPEN 4x4m

PJP606

1 2

10A

1

1

1

1

1

C1910.1U_0402_16V4Z

2

1 2
1 2

1

C1930.1U_0402_16V4Z

C1920.1U_0402_16V4Z

C1940.1U_0402_16V4Z

2

2

2

C2034.7U_0805_10V4Z

12

C2040.1U_0402_16V4Z

12

C2050.1U_0402_16V4Z

12

C2060.1U_0402_16V4Z

12

C2070.1U_0402_16V4Z

12

C2100.1U_0402_16V4Z
C2110.1U_0402_16V4Z

1

1

C1900.1U_0402_16V4Z

C1890.1U_0402_16V4Z

C1880.1U_0402_16V4Z

C1870.1U_0402_16V4Z

2

2

2

2

70mA

+1.1VS

330U_D2E_2.5VM_R15

1

C185

1

1

C19510U_0805_10V4Z

C19610U_0805_10V4Z

+

2

2

2

U3F

A25

VSSAHT1

D23

VSSAHT2

E22

VSSAHT3

G22

VSSAHT4

G24

VSSAHT5

G25

VSSAHT6

H19

VSSAHT7

J22

VSSAHT8

L17

VSSAHT9

L22

VSSAHT10

L24

VSSAHT11

L25

VSSAHT12

M20

VSSAHT13

N22

VSSAHT14

P20

VSSAHT15

R19

VSSAHT16

R22

VSSAHT17

R24

VSSAHT18

R25

VSSAHT19

H20

VSSAHT20

U22

VSSAHT21

V19

VSSAHT22

W22

VSSAHT23

W24

VSSAHT24

W25

VSSAHT25

Y21

VSSAHT26

AD25

VSSAHT27

L12

VSS11

M14

VSS12

N13

VSS13

P12

VSS14

P15

VSS15

R11

VSS16

R14

VSS17

T12

VSS18

U14

VSS19

U11

VSS20

U15

VSS21

V12

VSS22

W11

VSS23

W15

VSS24

AC12

VSS25

AA14

VSS26

Y18

VSS27

AB11

VSS28

AB15

VSS29

AB17

VSS30

AB19

VSS31

AE20

VSS32

AB21

VSS33

K11

VSS34

RS780M_FCBGA528

PART 6/6

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8

VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30

GROUND

VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

VSS10

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

RS780 PWR/GND

LA-4481P

14 46Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

B

C

D

E

1 1

2 2

RS780 DFT_GPIO5 mux at CRT_VSYNC pull low to 3K

CRT_VSYNC<12,17>

12

R81 1K_0402_5%

12

R82 1K_0402_5%@

+3VS

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

Enables the Test Debug Bus using GPIO.
1 : Disable (RS740) Disable (RX780, RS780)
0 : Enable (Rs740) Enable (RX780, RS780)
PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#

DFT_GPIO1: LOAD_EEPROM_STRAPS

1 2

R83 150_0402_1%@
D3 CH751H-40PT_SOD323-2@

2 1

Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

RS780 DFT_GPIO1

AUX_CAL<12>

SUS_STAT_R#<12> PLT_RST# <12,20,26,27,33,34>

RX780 DFT_GPIO1 mux at GREEN(Ball E18) and change pull low form 150 to 3K.

3 3

DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb

RS780_DFT_GPIO_0<12>

RS780 use HSYNC to enable SIDE PORT (internal pull high)

CRT_HSYNC<12,17>

4 4

A

B

12

R84 1K_0402_5%@

12

R85 3K_0402_5%

12

R248 10K_0402_5%@

RX780: Enables the Test Debug Bus using PCIE bus
1 : Disable ( Can still be enabled using nbcfg register access )
0 : Enable

RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)

1. Disable (RS740/RS780)
0 : Enable (RS740/RS780)

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

RS780 STRAPS

LA-4481P

15 46Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

B

C

D

E

R86

1 2

0_0805_5%

+3VS_CLK

1

C217
10U_0805_10V4Z

2

250mA

1

C218

0.1U_0402_16V4Z

2

1

C231

0.1U_0402_16V4Z

2

1

C219

0.1U_0402_16V4Z

2

1

C232

0.1U_0402_16V4Z

2

1

C220

0.1U_0402_16V4Z

2

1

C233

0.1U_0402_16V4Z

2

1

C221

0.1U_0402_16V4Z

2

1

C234

0.1U_0402_16V4Z

2

1

C222

0.1U_0402_16V4Z

2

1

C223

0.1U_0402_16V4Z

2

1

C224

@

1U_0402_6.3V4Z

2

+3VS

R87

1 2

0_0805_5%

+VDDCLK_IO

1

2

110mA

0.1U_0402_16V4Z

1

C225

2

C226

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C227

2

1

C228

2

0.1U_0402_16V4Z

1

C229

2

0.1U_0402_16V4Z

1

C230

2

+1.2V_HT

10U_0805_10V4Z

1 1

EMI Caps for single end clock.

R249 22_0402_5%

1 2

R88 22_0402_5%

1 2

1 2

CLK_XTAL_OUT

68

VDD_48

XTAL_OUT

CLK_XTAL_IN

66

67

XTAL_IN

SEL_SATA

27M_SEL

NB_OSC_14.318M_R

64

63

65

VSS_REF

REF_2/SEL_27

REF_1/SEL_SATA

REF_0/SEL_HTT66

R89 158_0402_1%

+3VS_CLK

+3VS_CLK

61

60

62

VDD_HTT

VDD_REF

59

58

57

56

PD#

VSS_HTT

HTT_0/66M_0

HTT_0#/66M_1

1 2

R90 90.9_0402_1%

1 2

R92 8.2K_0402_5%

CLK_CPU_BCLK_R
CLK_CPU_BCLK#_R

55

CPU_K8_0

CPU_K8_0#

VDD_CPU

VDD_CPU_I/O

VSS_CPU
CLKREQ_1#
CLKREQ_2#

VDD_A
VSS_A

VSS_SATA

SRC_6/SATA

SRC_6#/SATA#

VDD_SATA
CLKREQ_3#
CLKREQ_4#

SB_SRC_SLOW#

SB_SRC_0

SB_SRC_0#

VDD_SB_SRC

VDD_SB_SRC_IO

CLK_XTAL_OUT
CLK_XTAL_IN

Y1

12

14.31818MHZ_20P_6X1430004201

2 2

22P_0402_50V8J

C238

1

2

Routing the trace at least 10mil

SMB_CK_CLK0<9,10,21,31>
SMB_CK_DAT0<9,10,21,31>

SB LINK SB SRC

MiniCard_2

3 3

CLK_SBLINK_BCLK#<12>

CLK_SBLINK_BCLK<12> CLK_SBSRC_BCLK# <20>

CLK_PCIE_MCARD2#<27>

CLK_PCIE_MCARD2<27>

+3VS_CLK

+VDDCLK_IO

1

C239
22P_0402_50V8J

2

+3VS_CLK

+VDDCLK_IO

U6

1

SCL

2

SDA

3

VDD_DOT

4

SRC_7#/27M

5

SRC_7/27M_SS

6

VSS_DOT

7

SRC_5#

8

SRC_5

9

SRC_4#

10

SRC_4

11

VSS_SRC

12

VDD_SRC_IO

13

SRC_3#

14

SRC_3

15

SRC_2#

16

SRC_2

17

VDD_SRC

18

VDD_SRC_IO

+3VS_CLK

CLK_48M_USB_R

69

70

71

72

73

GND

VSS_48

48MHz_1

48MHz_0

CLK_48M_CR <28>
CLK_48M_USB <21>
NB_OSC_14.318M <12>

CLK_NBHT <12>
CLK_NBHT# <12>

+3VS_CLK

1 2

R93 0_0402_1%

1 2

R95 0_0402_1%

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

+3VS_CLK
+VDDCLK_IO

CLKREQ_NCARD#
CLKREQ_MCARD2#

+3VS_CLK

CLKREQ_MCARD1#
CLKREQ4

1 2

R96 10K_0402_5%

+3VS_CLK
+VDDCLK_IO

NB

R94
261_0402_1%@

1 2

+3VS_CLK

OSC_14M_NB

1.8V 75R/100RRX780

RS780

1.1V 200R/100R

CLK_CPU_BCLK <7>

CPU

CLK_CPU_BCLK# <7>

CLKREQ_NCARD# <27>
CLKREQ_MCARD2# <27>

CLK_SBSRC_BCLK <20>

CLKREQ_MCARD1#

+3VS_CLK

For ICS need to pull high.
For SLG is NC

C622

1 2

1U_0402_6.3V4Z

CLK_48M_USB

NB_OSC_14.318M

1

@

1

5P_0402_50V8C

2

C236

@
2

5P_0402_50V8C

C235

VSS_SRC19SRC_1#20SRC_121SRC_0#22SRC_023CLKREQ_0#24ATIGCLK_2#25ATIGCLK_226VSS_ATIG27VDD_ATIG_IO28VDD_ATIG29ATIGCLK_1#30ATIGCLK_131ATIGCLK_0#32VSS_SB_SRC36SB_SRC_135SB_SRC_1#34ATIGCLK_0

33

+3VS_CLK

R100

@

8.2K_0402_5%

1 2

SEL_SATA

R103

8.2K_0402_5%

4 4

SEL_SATA

* default

1 2

1

configure as SATA output

*

configure as normal SRC(SRC_6) output

0

+3VS_CLK

8.2K_0402_5%

1 2

27M_SEL

R104

27M_SEL

configure as 27M and 27M_SS output

1*
0

configure as SRC_7 output

* default

+3VS_CLK

+VDDCLK_IO

CLKREQ_LAN#

SLG8SP626VTR_QFN72_10x10

NBGFX_CLK <12>
NBGFX_CLK# <12>

CLKREQ_LAN# <26>
CLK_PCIE_LAN <26>
CLK_PCIE_LAN# <26>

CLK_PCIE_NCARD <27>
CLK_PCIE_NCARD# <27>

NB GFX

GLAN

New Card

CLKREQ_NCARD#
CLKREQ_MCARD2#
CLKREQ_MCARD1#
CLKREQ_LAN#
CLKREQ4

NB CLOCK INPUT TABLE

NB CLOCKS
HT_REFCLKP
HT_REFCLKN
REFCLK_P
REFCLK_N
GFX_REFCLK 100M DIFF

R97 8.2K_0402_5%
R98 8.2K_0402_5%
R99 8.2K_0402_5%
R101 8.2K_0402_5%
R102 8.2K_0402_5%@

RX780 RS780

100M DIFF
100M DIFF

14M SE (1.8V) 14M SE (1.1V)
NC vref

1 2
1 2
1 2
1 2
1 2

+3VS_CLK

100M DIFF
100M DIFF

100M DIFF(IN/OUT)*

Use voltage divider resistor R379 & R380 to pull low

NB_OSC_14.318M

configure as single-ended 66MHz output1

*0 configure as differential 100MHz output

* default

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Clock generator

LA-4481P

16 46Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

B

C

D

E

1 1

DAN217_SC59

D5

@

2

L23

1 2

BLM15AG121SN1D_0402

L24

1 2

BLM15AG121SN1D_0402

L25

1 2

BLM15AG121SN1D_0402

1

2

6P_0402_50V8K

R107

150_0402_1%

RED

GREEN

BLUE

12

C241

150_0402_1%

1

1

C242

C243

2

2

6P_0402_50V8K

6P_0402_50V8K

RED<12>

GREEN<12>

BLUE<12>

12

12

R106

2 2

R105

140_0402_1%

DAN217_SC59

1

3

1

C244

C245

2

6P_0402_50V8K

D6

@

GREEN_L

1

2

2

RED_L

BLUE_L

6P_0402_50V8K

1

DAN217_SC59

@

3

1

C246

2

SM01000E100 (S SUPPRE_ KING CORE FBMA-10-100505-800T 0402)

+3VS

12

R108

4.7K_0402_5%

UMA_CRT_DAT<12>

UMA_CRT_CLK<12>

3 3

R109

4.7K_0402_5%

1 2

2N7002DW-7-F_SOT363-6

5

4

2N7002DW-7-F_SOT363-6

2

3

Q7B

6.8K_0402_5%

61

Q7A

470P_0402_50V8J

@

R110

C249

1

2

+CRT_VCC

1

2

R111

6.8K_0402_5%

D_DDCDATA

D_DDCCLK

C250

@

470P_0402_50V8J

CRT_HSYNC<12,15>

CRT_VSYNC<12,15>

CRT CONNECTOR

+R_CRT_VCC

D4

+CRT_VCC

1 2

C247

0.1U_0402_16V4Z

1 2

C248

0.1U_0402_16V4Z

2 1

RB491D_SOT23

+3VS

D_DDCDATA

HSYNC

VSYNC

D_DDCCLK

+CRT_VCC

5

P

A2Y

G

3

5

P

A2Y

G

3

1

OE#

U7
SN74AHCT1G125GW_SOT353-5

1

OE#

U8

SN74AHCT1G125GW_SOT353-5

1

D7

2

3

6P_0402_50V8K

F1

21

1A_6VDC_MINISMDC110

0.1U_0402_16V4Z

JCRT

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5
16

GND

17

GND

SUYIN_070546FR015S265ZR

CONN@

D_HSYNC

4

D_VSYNC

4

+CRT_VCC+5VS

1

C240

2

R112 0_0603_5%

1 2

R113 0_0603_5%

1 2

C251

@

HSYNC

VSYNC

1

1

C252

@

2

2

10P_0402_50V8J

10P_0402_50V8J

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

CRT Connector

LA-4481P

17 46Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

B

C

D

E

LVDS CONN

1.35A

INVPWR_B+ B+

1 1

41
42
43
44
45
46

2 2

ACES_88316-4000

conn@

3 3

JLVDS

40

40

41
42
43
44
45
46

39

39

38

38

37

37

36

36

35

35

34

34

33

33

32

32

31

31

30

30

29

29

28

28

27

27

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

680P_0402_50V7K

C262

@

RS780 VariBright function
R397 & R396 for RS780 VariBright function and EC control option

BKOFF#_R
INV_PWM_LED

+V_LOG

DAC_BRIG
DMIC_DAT
DMIC_CLK

USB20_N5
USB20_P5

LVDS_ACLK+
LVDS_ACLK-

LVDS_A2+
LVDS_A2-

LVDS_A1+
LVDS_A1-

LVDS_A0+
LVDS_A0­LCD_DDC_DAT
LCD_DDC_CLK

12

680P_0402_50V7K

@

L26

1 2

FBMA-L11-201209-221LMA30T_0805

12

C254
680P_0402_50V7K

1 2

R121

1 2

200_0805_5%

12

C261

1

2

DMIC_DAT <29>
DMIC_CLK <29>
+USB_CAM

USB20_N5 <21>
USB20_P5 <21>

LVDS_ACLK+ <12>
LVDS_ACLK- <12>

LVDS_A2+ <12>
LVDS_A2- <12>

LVDS_A1+ <12>
LVDS_A1- <12>

LVDS_A0+ <12>
LVDS_A0- <12>
LCD_DDC_DAT <12>
LCD_DDC_CLK <12>

+LCDVDD

C253
680P_0402_50V7K

+5VS

2A

1

C623
680P_0402_50V7K

2

R396200_0402_5%

1 2

680P_0402_50V7K

C259

@

+3VS

BKOFF# <34>

DAC_BRIG <34>

12

680P_0402_50V7K
C258

INV_PWM_R

INV_PWM_R
BKOFF#_R

0_0402_5%

1 2

R397

BKOFF#

LCD_DDC_CLK

LCD_DDC_DAT

1 2

1 2

1 2

1

C260
680P_0402_50V7K

2

R1164.7K_0402_5%@

R1174.7K_0402_5%

R1194.7K_0402_5%

0801 Change Vari-Bright circuit
0901 Delete D38 for without VB

R395 0_0402_5%@

1 2

R394 0_0402_5%@

1 2

LVDS_BLON <12>
LVDS_ENA_BL <12>

0901 add R410

0619 Solve LED panel flash issue

@

10K_0402_1%

INV_PWM_R

+3VS

R55

R410

0_0402_5%

1 2

12

Q4

@

2N7002_SOT23-3

D

S

INV_PWM_LED

1 3

G

2

BKOFF#_R

12

R54
100K_0402_1%

+3VS

INV_PWM <34>
@

LVDS PWR circuit

+LCDVDD

R114

220_0402_5%

2N7002DW-7-F_SOT363-6

UMA_ENVDD<12>

Q9A

2.2K_0402_5%

Camera PWR circuit

+5VS

PJP604

PAD-OPEN 2x2m

C264

10U_0805_10V4Z

2 1

2

12

1

R124
0_0402_5%

1
2
3

1 2

+5VALW

12

61

R120

RT9193-39GB_SOT23-5

@

0_0402_5%

2

5

1 2

U9

VIN
GND
EN

R125

R115
1M_0402_5%

1 2

3

2N7002DW-7-F_SOT363-6

4

Q9B

VOUT

BP

0.1U_0402_16V4Z

R118

1 2

100K_0402_5%

5

4

C265

CAM_SHDN# <22>

12

12

1

2

2

C255
1000P_0402_50V7K

1

4.7U_0805_10V4Z

+USB_CAM

R122

215K_0402_1%@

2

1

R123

100K_0402_1%@

+3VS

G

2

1 3

C256

C263
10U_0805_10V4Z

+USB_CAM

80mil

S

SI2301BDS-T1-E3_SOT23-3
Q8

D

80mil

+LCDVDD

1

C257

0.1U_0402_16V4Z

2

USB_VCCA is +3.9V, R115:100K;
R114:215Kohm
G916 Vref=1.25V when U54 install
G916-390T1UF

C253 install when U9 is
RT9193-39GB

Close to JLVDS

USB20_N5

D8

4

VIN

3

IO2

PRTR5V0U2X_SOT143-4@

GND

USB20_P5

2

IO1

1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

LCD CONN. / WebCam

LA-4481P

18 46Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

1 1

0.1U_0402_16V4Z

2 2

C266

+HDMI_5V_OUT

2

5

1

P

A2Y

G

3

1

OE#

2.2K_0402_5%

4

U10
SN74AHCT1G125GW_SOT353-5

B

1 2

HDMI_HPD

2

C267

0.1U_0402_16V4Z

1

12

+3VS

R130

HPD <12>

R131

100K_0402_5%

C

12

R126

4.7K_0402_5%

HDMIDAT_UMA<12>

HDMICLK_UMA<12>

R127

4.7K_0402_5%

1 2

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

5

4

3

D

Q10B

E

+HDMI_5V_OUT+3VS

61

Q10A

R128

6.8K_0402_5%

2

R129

6.8K_0402_5%

HDMI_SDATA

HDMI_SCLK

HDMI_CLK+

C269 0.1U_0402_16V7K

TMDS_B_CLK#<11>
TMDS_B_CLK<11>

TMDS_B_DATA0#<11>

TMDS_B_DATA0<11>

TMDS_B_DATA1#<11>

TMDS_B_DATA1<11>

TMDS_B_DATA2#<11>
TMDS_B_DATA2<11>

3 3

4 4

HDMI_CLK­HDMI_CLK+

12

R137

R138

715_0402_1%

+5VS +5VS +5VS +5VS

715_0402_1%

1 2

61

2

Q11A

2N7002DW-7-F_SOT363-6

1 2

C270 0.1U_0402_16V7K

1 2

C271 0.1U_0402_16V7K

1 2

C272 0.1U_0402_16V7K

1 2

C273 0.1U_0402_16V7K

1 2

C274 0.1U_0402_16V7K

1 2

C275 0.1U_0402_16V7K

1 2

C276 0.1U_0402_16V7K

1 2

HDMI_TX0­HDMI_TX0+

R141

715_0402_1%

715_0402_1%

1 2

1 2
3

5

Q11B

4

2N7002DW-7-F_SOT363-6

HDMI_TX1­HDMI_TX1+

715_0402_1%

R142

HDMI_CLK­HDMI_CLK+

HDMI_TX0­HDMI_TX0+

HDMI_TX1­HDMI_TX1+

HDMI_TX2­HDMI_TX2+

HDMI_TX2­HDMI_TX2+

R139

715_0402_1%
R140

715_0402_1%

1 2

1 2

61

2

Q12A

2N7002DW-7-F_SOT363-6

R143

715_0402_1%

R144

1 2

1 2
3

5

Q12B

4

2N7002DW-7-F_SOT363-6

HDMI_CLK-

HDMI_TX0+

HDMI_TX0-

HDMI_TX1+

HDMI_TX1-

HDMI_TX2-

1 2

R132 0_0402_5%@

L27

1

1

4

4

WCM-2012-900T_4P

1 2

R133 0_0402_5%@

1 2

R134 0_0402_5%@

L28

1

1

4

4

WCM-2012-900T_4P

1 2

R135 0_0402_5%@

1 2

R136 0_0402_5%@

L29

1

1

4

4

WCM-2012-900T_4P

1 2

R145 0_0402_5%@

1 2

R146 0_0402_5%@

L30

1

1

4

4

WCM-2012-900T_4P

1 2

R147 0_0402_5%@

2

2

3

3

2

2

3

3

2

2

3

3

2

2

3

3

HDMI_R_CK+

HDMI_R_CK-

HDMI_R_D0+

HDMI_R_D0-

HDMI_R_D1+

HDMI_R_D1-

HDMI_R_D2+HDMI_TX2+

HDMI_R_D2-

+5VS +HDMI_5V_OUT

RB491D_SOT23

D9

2 1

65mA

1

C268

0.1U_0402_16V4Z

2

HDMI Connector

+HDMI_5V_OUT

JHDMI1

18

HDMI_SDATA
HDMI_SCLK
HDMI_HPD

HDMI_R_CK­HDMI_R_CK+
HDMI_R_D0­HDMI_R_D0+
HDMI_R_D1­HDMI_R_D1+
HDMI_R_D2­HDMI_R_D2+

+5V

16

SDA

15

SCL

19

HP_DET

12

CK-

10

CK+

9

D0-

7

D0+

6

D1-

4

D1+

3

D2-

1

D2+

DDC/CEC_GND

SUYIN_100042MR019S153ZLCONN@

CEC

Reserved

GND
GND
GND
GND
GND
GND
GND
GND

13
14

2
5
8
11
20
21
22
23
17

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

HDMI

LA-4481P

19 46Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

B

C

D

E

LPCCLK1

STRAP PIN
EC & Debug

STRAP PIN

+RTCVCC_R

R161
120_0402_5%

1 2

W=20mils

STRAP PIN

R416 33_0402_5%

1 2

ACCEL_INT <31>

CLK_PCI_EC <24,34>

R162
120_0402_5%

1 2

2

J1

2

JUMP_43X39@

1

1

PCICLK2 <24>

PCI_CLK3 <24>
PCI_CLK4 <24>
PCI_CLK5 <24>

STRAP PIN

CLK_PCI_SIO <33>

ZZZ1

PCB-MB

D10

+3VL

2
3

W=20mils

+RTCBATT_R

R163

1 2

1K_0402_5%

+RTCBATT

W=20mils

W=20mils

JBATT1

1
2
3
4

ACES_85205-02001CONN@

9/20 SP020008T00

Compal Electronics, Inc.

SB700-PCIE/PCI/ACPI/LPC/RTC

LA-4481P

20 46Monday, September 08, 2008

E

1
2
GND
GND

+RTCVCC

1

DAN202U_SC70

Title

Size Document Number Rev

Custom

Date: Sheet

0.4

of

Check AMD need pull low or not

R148 8.2K_0402_5%@

C277 0.1U_0402_16V7K

SB_RX0P<11>
SB_RX0N<11>
SB_RX1P<11>
SB_RX1N<11>
SB_RX2P<11>

1 1

+3VALW

C287

12

5

0.1U_0402_16V4Z@

NB_RST#_R

2 2

3 3

18P_0402_50V8J

18P_0402_50V8J

+3VS

R153 33_0402_5%

R154 20M_0402_5%@

1 2

C288

1 2

R155

20M_0603_5%

C289

1 2

Close to SB

R159 10K_0402_5%

U12

2

P

B

PLT_RST#

4

Y

1

A

G

NC7SZ08P5X_NL_SC70-5@

3

12

12

H_PROCHOT#

12

PLT_RST# <12,15,26,27,33,34>

32.768KHZ_12.5PF_9H03200413

4
1

Y2

OSC
OSC

3

NC

2

NC

SB_RX2N<11>
SB_RX3P<11>
SB_RX3N<11>

SB_TX0P<11>
SB_TX0N<11>
SB_TX1P<11>
SB_TX1N<11>
SB_TX2P<11>
SB_TX2N<11>
SB_TX3P<11>
SB_TX3N<11>

+1.2V_HT

SB_32KHI

SB_32KHO

+PCIE_VDDR

1 2

BLM18PG121SN1D_0603

1 2

C278 0.1U_0402_16V7K

1 2

C279 0.1U_0402_16V7K

1 2

C280 0.1U_0402_16V7K

1 2

C281 0.1U_0402_16V7K

1 2

C282 0.1U_0402_16V7K

1 2

C283 0.1U_0402_16V7K

1 2

C284 0.1U_0402_16V7K

1 2

L31

C285

10U_0805_10V4Z

Close to SB

CLK_SBSRC_BCLK<16>
CLK_SBSRC_BCLK#<16>

CPU_LDT_REQ#<7,12>

H_PROCHOT#<7>

LDT_STOP#<7,12>

R151 562_0402_1%
R152 2.05K_0402_1%

1

2

LDT_RST#<7>

12
12

1

C286

1U_0402_6.3V4Z

2

CPU_LDT_REQ#
H_PROCHOT#
H_PWRGD_SB

NB_RST#_R
SB_RX0P_C

SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C

+SB_PCIEVDD

SB_32KHI

SB_32KHO

NB_RST#_R

1 2

9/20 SA00001S510 S IC 218S7EALA11FG SB700 BGA 528P SB 0FH

R160

4 4

H_PWRGD_CPU<7>

H_PWRGD<43>

A

1 2

0_0402_5%

R403

1 2

0_0402_5%

H_PWRGD_SB

B

U11A

N2

A_RST#

V23

PCIE_TX0P

V22

PCIE_TX0N

V24

PCIE_TX1P

V25

PCIE_TX1N

U25

PCIE_TX2P

U24

PCIE_TX2N

T23

PCIE_TX3P

T22

PCIE_TX3N

U22

PCIE_RX0P

U21

PCIE_RX0N

U19

PCIE_RX1P

V19

PCIE_RX1N

R20

PCIE_RX2P

R21

PCIE_RX2N

R18

PCIE_RX3P

R17

PCIE_RX3N

T25

PCIE_CALRP

T24

PCIE_CALRN

P24

PCIE_PVDD

P25

PCIE_PVSS

N25

PCIE_RCLKP/NB_LNK_CLKP

N24

PCIE_RCLKN/NB_LNK_CLKN

K23

NB_DISP_CLKP

K22

NB_DISP_CLKN

M24

NB_HT_CLKP

M25

NB_HT_CLKN

P17

CPU_HT_CLKP

M18

CPU_HT_CLKN

M23

SLT_GFX_CLKP

M22

SLT_GFX_CLKN

J19

GPP_CLK0P

J18

GPP_CLK0N

L20

GPP_CLK1P

L19

GPP_CLK1N

M19

GPP_CLK2P

M20

GPP_CLK2N

N22

GPP_CLK3P

P22

GPP_CLK3N

L18

25M_48M_66M_OSC

J21

25M_X1

J20

25M_X2

A3

X1

B3

X2

RTC XTAL

F23

ALLOW_LDTSTP

F24

PROCHOT#

F22

LDT_PG

G25

LDT_STP#

G24

LDT_RST#

218S7EALA11FG_BGA528_SB700

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SB700

Part 1 of 5

PCICLK5/GPIO41

PCI CLKS

PCI EXPRESS INTERFACE

PCI INTERFACE

REQ3#/GPIO70
REQ4#/GPIO71

GNT3#/GPIO72
GNT4#/GPIO73

CLKRUN#

INTE#/GPIO33
INTF#/GPIO34

INTG#/GPIO35

CLOCK GENERATOR

INTH#/GPIO36

LPC

LFRAME#

LDRQ1#/GNT5#/GPIO68

BMREQ#/REQ5#/GPIO65

INTRUDER_ALERT#

CPU

RTC

2007/08/02 2008/08/02

C

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4

PCIRST#

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8

AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CBE0#
CBE1#
CBE2#
CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR

STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#

GNT0#
GNT1#
GNT2#

LOCK#

LPCCLK0
LPCCLK1

LAD0
LAD1
LAD2
LAD3

LDRQ0#

SERIRQ

RTCCLK

VBAT

P4
P3
P1

CLK_PCI_SIO_R

P2
T4
T3

N1

U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3

PCI_AD23

Y2

PCI_AD24

AA2

PCI_AD25

AB4

PCI_AD26

AA1

PCI_AD27

AB3

PCI_AD28

AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
V5

AD3
AC4
AE2

PCI_PIRQH#

AE3

CLK_PCI_EC_R

G22
E22
H24
H23
J25
J24
H25
H22
AB8
AD7
V15

C3
C2
B2

+SB_VBAT

Compal Secret Data

Deciphered Date

R150 22_0402_5%

1 2

PCI_AD23 <24>
PCI_AD24 <24>
PCI_AD25 <24>
PCI_AD26 <24>
PCI_AD27 <24>
PCI_AD28 <24>

PCI_SERR# <34>

T22PAD

T23PAD
T24PAD

R156 0_0402_5%

R157

T25PAD

C290

0.1U_0402_16V4Z

22_0402_5%

1 2

LPCCLK1 <24>
LPC_AD0 <33,34>
LPC_AD1 <33,34>
LPC_AD2 <33,34>
LPC_AD3 <33,34>
LPC_FRAME# <33,34>

LPC_DRQ# <33>

SIRQ <33,34>

RTC_CLK <24>

+SB_VBAT

1

C291

2

1U_0402_6.3V4Z

12

CLK_PCI_EC

1

2

D

http://mycomp.su/x/

A

B

C

D

E

T26PAD

PCIE_WAKE#
H_THERMTRIP#

NB_PWRGD
EC_RSMRST#

1 2

SMB_CK_CLK0
SMB_CK_DAT0
SMB_CK_CLK1
SMB_CK_DAT1

SB_GPIO5

12

T27PAD

CH751H-40PT_SOD323-2

D33

U11D

E1

PCI_PME#/GEVENT4#

E2

RI#/EXTEVNT0#

H7

SLP_S2/GPM9#

F5

SLP_S3#

G1

SLP_S5#

H2

PWR_BTN#

H1

PWR_GOOD

K3

SUS_STAT#

H5

TEST2

H4

TEST1

H3

TEST0

Y15

GA20IN/GEVENT0#

W15

KBRST#/GEVENT1#

K4

LPC_PME#/GEVENT3#

K24

LPC_SMI#/EXTEVNT1#

F1

S3_STATE/GEVENT5#

J2

SYS_RESET#/GPM7#

H6

WAKE#/GEVENT8#

F2

BLINK/GPM6#

J6

SMBALERT#/THRMTRIP#/GEVENT2#

W14

NB_PWRGD

D3

RSMRST#

AE18

SATA_IS0#/GPIO10

AD18

CLK_REQ3#/SATA_IS1#/GPIO6

AA19

SMARTVOLT1/SATA_IS2#/GPIO4

W17

CLK_REQ0#/SATA_IS3#/GPIO0

V17

CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39

W20

CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40

W21

SPKR/GPIO2

AA18

SCL0/GPOC0#

W18

SDA0/GPOC1#

K1

SCL1/GPOC2#

K2

SDA1/GPOC3#

AA20

DDC1_SCL/GPIO9

Y18

DDC1_SDA/GPIO8

C1

LLB#/GPIO66

Y19

SMARTVOLT2/SHUTDOWN#/GPIO5

G5

DDR3_RST#/GEVENT7#

B9

USB_OC6#/IR_TX1/GEVENT6#

B8

USB_OC5#/IR_TX0/GPM5#

A8

USB_OC4#/IR_RX0/GPM4#

A9

USB_OC3#/IR_RX1/GPM3#

E5

USB_OC2#/GPM2#

F8

USB_OC1#/GPM1#

E4

USB_OC0#/GPM0#

M1

AZ_BITCLK

M2

AZ_SDOUT

J7

AZ_SDIN0/GPIO42

J8

AZ_SDIN1/GPIO43

L8

AZ_SDIN2/GPIO44

M3

AZ_SDIN3/GPIO46

L6

AZ_SYNC

M4

AZ_RST#

L5

AZ_DOCK_RST#/GPM8#

3/5V_OK<39,41>

1 1

2 2

3 3

+3VS

1 2

R167 4.7K_0402_5%

+3VALW

1 2

R168 2.2K_0402_5%@

1 2

R169 2.2K_0402_5%@

1 2

R170 2.2K_0402_5%@

+3VS

R171 2.2K_0402_5%

1 2

R172 2.2K_0402_5%

1 2

+3VALW

R174 2.2K_0402_5%

1 2

R175 2.2K_0402_5%

1 2

LAN_PCIE_WAKE#<26>
MINI_PCIE_WAKE#<27>

SUS_STAT#

SB_TEST2
SB_TEST1
SB_TEST0

SMB_CK_CLK0
SMB_CK_DAT0

SMB_CK_CLK1
SMB_CK_DAT1

12

R177 0_0402_5%

12

R178 0_0402_5%@

HDA_BITCLK_CODEC<29>
HDA_SDOUT_CODEC<29>

HDA_SDIN0<29>

HDA_SYNC_CODEC<29>

HDA_RST#_CODEC<29>

HDARST#<24,34>

0605 remove 0 ohm resisters

+3VALW

R176
10K_0402_5%

1 2

PCIE_WAKE#

R181 33_0402_5%
R182 33_0402_5%

R183 33_0402_5%
R184 33_0402_5%

EC_LID_OUT#<34>

demo circuit LID use RI#

SLP_S3#<34>
SLP_S5#<34>

PWRBTN_OUT#<34>

SB_PWRGD<7,34,43>
SUS_STAT#<12>

GATEA20<34>
KB_RST#<34>
EC_SCI#<34>
EC_SMI#<34>

H_THERMTRIP#<7>

NB_PWRGD<12>

EC_RSMRST#<34>

SB700 has internal PD

+3VS

EXP_CPPE#<27>

LAN_DSM#<26>

1 2
1 2

1 2
1 2

100K_0402_5%

SB_SPKR<29>
SMB_CK_CLK0<9,10,16,31>
SMB_CK_DAT0<9,10,16,31>

SMB_CK_CLK1<27>

SMB_CK_DAT1<27>

R404

1 2

10K_0402_5%

EXP_CPPE#

R247 0_0402_5%

HDABITCLK HDA_BITCLK

HDA_SDOUT
HDA_SDIN0

SUS_STAT#
SB_TEST2
SB_TEST1
SB_TEST0

R173

R179 0_0402_5%

1 2

HDA_SYNC

HDARST#

STRAP PIN

C624 82P_0402_50V8J

1 2

C625 82P_0402_50V8J

1 2

0.1U_0402_16V4Z

4 4

C626

@

HDA_BITCLK_CODEC
HDA_SDOUT_CODEC

+3VS

HDABITCLK

10K_0402_5%

1

2

U30

@

7

VDD

6

CLKOUT

R405

@

5

12

SSON

4

GND

ASM3P623S00BF-08TR_TSSOP8

CLKIN

H19

IMC_GPIO0

H20

IMC_GPIO1

H21

SPI_CS2#/IMC_GPIO2

F25

IDE_RST#/F_RST#/IMC_GPO3

D22

IMC_GPIO4

E24

IMC_GPIO5

E25

IMC_GPIO6

D23

HDA_BITCLK

1
2

NC

8

NC

3

SS

10K_0402_5%

@

10K_0402_5%

1 2

R407

+3VS

R406

@

12

IMC_GPIO7

218S7EALA11FG_BGA528_SB700

EC_RSMRST#

21

SB700

ACPI / WAKE UP EVENTS

USB OC

HD AUDIO

Part 4 of 5

USBCLK/14M_25M_48M_OSC

INTEGRATED uC

USB_RCOMP

USB_FSD13P

USB_FSD13N

USB MISC

USB_FSD12P

USB_FSD12N

USB 1.1

USB_HSD11P
USB_HSD11N

USB_HSD10P
USB_HSD10N

USB_HSD9P

USB_HSD9N

USB_HSD8P

USB_HSD8N

USB_HSD7P

USB_HSD7N

USB_HSD6P

USB_HSD6N

USB_HSD5P

USB_HSD5N

USB_HSD4P

USB 2.0

USB_HSD4N

USB_HSD3P

USB_HSD3N

GPIO

USB_HSD2P

USB_HSD2N

USB_HSD1P

USB_HSD1N

USB_HSD0P

USB_HSD0N

IMC_GPIO8
IMC_GPIO9

IMC_PWM0/IMC_GPIO10

SCL2/IMC_GPIO11

SDA2/IMC_GPIO12
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14

IMC_PWM1/IMC_GPIO15

IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17

IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25

IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41

C8

USB_RCOMP

G8

E6
E7

F7
E8

H11
J10

E11
F11

A11
B11

USB20_P8

C10

USB20_N8

D10

USB20_P7

G11

USB20_N7

H12

USB20_P6

E12

USB20_N6

E14

USB20_P5

C12

USB20_N5

D12

USB20_P4

B12

USB20_N4

A12

USB20_P3

G12

USB20_N3

G14

USB20_P2

H14

USB20_N2

H15

USB20_P1

A13

USB20_N1

B13

USB20_P0

B14

USB20_N0

A14
A18

B18
F21
D21
F19
E20
E21
E19
D19
E18

G20
G21
D25
D24
C25
C24
B25
C23

B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18

1 2

USB20_P8 <27>
USB20_N8 <27>

USB20_P7 <28>
USB20_N7 <28>

USB20_P6 <27>
USB20_N6 <27>

USB20_P5 <18>
USB20_N5 <18>

USB20_P4 <32>
USB20_N4 <32>

USB20_P3 <32>
USB20_N3 <32>

USB20_P2 <32>
USB20_N2 <32>

USB20_P1 <32>
USB20_N1 <32>

USB20_P0 <32>
USB20_N0 <32>

R16611.8K_0402_1%

GPIO16 <24>
GPIO17 <24>

CLK_48M_USB <16>

USB-8 NEW Card
USB-7 CardReader
USB-6 WLAN
USB-5 USB Camera
USB-4 FPR
USB-3 BT
USB-2 Right Side (Upper)
USB-1 Right side (E-SATA Combo)
USB-0 Right side (S/W Debug Port)

STRAP PIN
STRAP PIN

INTEGRATED uC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SB700 USB/AC97

LA-4481P

21 46Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

B

C

D

E

C29210P_0402_50V8J

12

12

Y3

25MHz_20pF_6X25000017

1 1

SATA_TXP0<25>
SATA_TXN0<25>

SATA_TXP1<25>
SATA_TXN1<25>

SATA_TXP2<32>
SATA_TXN2<32>

2 2

+1.2V_HT

BLM18PG121SN1D_0603

+3VS

3 3

C29310P_0402_50V8J

12

C294 0.01U_0402_25V7K

1 2

C295 0.01U_0402_25V7K

1 2

C296 0.01U_0402_25V7K

1 2

C297 0.01U_0402_25V7K

1 2

C298 0.01U_0402_25V7K

1 2

C299 0.01U_0402_25V7K

1 2

+3VS

L32

12

C302

1U_0402_6.3V4Z

L33

12

BLM18PG121SN1D_0603

1U_0402_6.3V4Z

12

R185

10M_0402_5%

R192 10K_0402_5%

1 2

SATA_LED#<35>

2

2

1

1

2

C304

1

SATA_X1

SATA_X2

SATA_RXN0_C<25>
SATA_RXP0_C<25>

SATA_RXN1_C<25>
SATA_RXP1_C<25>

SATA_RXN2_C<32>
SATA_RXP2_C<32>

R191 1K_0402_1%

+PLLVDD_SATA

C303
1U_0402_6.3V4Z

+XTLVDD_SATA

SATA_STX_DRX_P0
SATA_STX_DRX_N0

SATA_STX_DRX_P1
SATA_STX_DRX_N1

SATA_STX_DRX_P2
SATA_STX_DRX_N2

12

77mA

1mA

SATA_CAL

SATA_X1
SATA_X2

U11B

AD9

SATA_TX0P

AE9

SATA_TX0N

AB10

SATA_RX0N

AC10

SATA_RX0P

AE10

SATA_TX1P

AD10

SATA_TX1N

AD11

SATA_RX1N

AE11

SATA_RX1P

AB12

SATA_TX2P

AC12

SATA_TX2N

AE12

SATA_RX2N

AD12

SATA_RX2P

AD13

SATA_TX3P

AE13

SATA_TX3N

AB14

SATA_RX3N

AC14

SATA_RX3P

AE14

SATA_TX4P

AD14

SATA_TX4N

AD15

SATA_RX4N

AE15

SATA_RX4P

AB16

SATA_TX5P

AC16

SATA_TX5N

AE16

SATA_RX5N

AD16

SATA_RX5P

V12

SATA_CAL

Y12

SATA_X1

AA12

SATA_X2

W11

SATA_ACT#/GPIO67

AA11

PLLVDD_SATA

W12

XTLVDD_SATA

218S7EALA11FG_BGA528_SB700

SB700

Part 2 of 5

SATA PWR SERIAL ATA

HW MONITOR

IDE_IORDY

IDE_IRQ

IDE_A0
IDE_A1
IDE_A2

IDE_DACK#

IDE_DRQ

IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23

ATA 66/100/133

IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

SPI_DI/GPIO12

SPI_DO/GPIO11
SPI_CLK/GPIO47

SPI_HOLD#/GPIO31

SPI_CS1#/GPIO32

LAN_RST#/GPIO13

SPI ROM

ROM_RST#/GPIO14

FANOUT0/GPIO3

FANOUT1/GPIO48
FANOUT2/GPIO49

FANIN0/GPIO50

FANIN1/GPIO51

FANIN2/GPIO52

TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63

TEMPIN3/TALERT#/GPIO64

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

AVDD
AVSS

AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24

AD24
AD23
AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23

G6
D2
D1
F4
F3

U15
J1

M8
M5
M7

P5
P8
R8

THERMAL_DC

C6
B6
A6
A5
B5

A4
B4
C4
D4

LFB_ID0

D5

LFB_ID1

D6

LFB_ID2

A7
B7

F6
G7

C305

0.1U_0402_16V4Z

R193 0_0402_5%

1 2

5mA

+SB_AVDD

1

2

BLM18PG121SN1D_0603

1

C306

2.2U_0603_6.3V4Z

2

+3VALW
+3VALW

ISOLATEB <26>

HDD_HALTLED# <35>

WLOFF# <27>
BT_COMBO_EN# <27>

EC_THERM# <34>

BT_OFF <32>
CAM_SHDN# <18>

L34

AC_IN_SB

+3VALW

12

Local Frame Buffer Strapping List
Copy from Becks.

LFB_ID0LFB_ID1LFB_ID2

Hynix

Qimonda

Samsung

000

001

001

LFB_ID0 to LFB_ID2 got internal PU 10K to S5.

LFB_ID2

R186 1K_0402_5%@

R187

@

1 2

10K_0402_5%

1 2

10K_0402_5%@

R189

+3VALW

12

LFB_ID1
LFB_ID0

0605 Change value to solve AC
plugged/unplugged power status
issue.

R408
300K_0402_5%

2 1

D34
CH751H-40PT_SOD323-2

1 2

R188 1K_0402_5%@

1 2

R190 1K_0402_5%@

1 2

AC_IN <34,38>

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

SB700 SATA/IDE/SPI

LA-4481P

22 46Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

B

C

D

E

U11C

L9

VDDQ_1

M9

VDDQ_2

T15

VDDQ_3

U9

VDDQ_4

U16

VDDQ_5

U17

VDDQ_6

V8

VDDQ_7

W7

VDDQ_8

Y6

VDDQ_9

AA4

VDDQ_10

AB5

VDDQ_11

AB21

VDDQ_12

Y20

VDD33_18_1

AA21

VDD33_18_2

AA22

VDD33_18_3

AE25

VDD33_18_4

P18

PCIE_VDDR_1

P19

PCIE_VDDR_2

P20

PCIE_VDDR_3

P21

PCIE_VDDR_4

R22

PCIE_VDDR_5

R24

PCIE_VDDR_6

R25

PCIE_VDDR_7

AA14

AVDD_SATA_1

AB18

AVDD_SATA_4

AA15

AVDD_SATA_2

AA17

AVDD_SATA_3

AC18

AVDD_SATA_5

AD17

AVDD_SATA_6

AE17

AVDD_SATA_7

A16

AVDDTX_0

B16

AVDDTX_1

C16

AVDDTX_2

D16

AVDDTX_3

D17

AVDDTX_4

E17

AVDDTX_5

F15

AVDDRX_0

F17

AVDDRX_1

F18

AVDDRX_2

G15

AVDDRX_3

G17

AVDDRX_4

G18

AVDDRX_5

218S7EALA11FG_BGA528_SB700

SB700

Part 3 of 5

PCI/GPIO I/O

IDE/FLSH I/O

POWER

A-LINK I/O

3.3V_S5 I/OCORE S5

SATA I/O

USB_PHY_1.2V_1
USB_PHY_1.2V_2

PLL CLKGEN I/O

USB I/O

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8

CORE S0

VDD_9

CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7

S5_1.2V_1
S5_1.2V_2

V5_VREF
AVDDCK_3.3V
AVDDCK_1.2V

AVDDC

R196

12

1 2

12

1 2

0.45A/40mil/3vias

0.45A/30mil/3vias

0_0603_5%

1 2

2

1

+PCIE_VDDR

+1.2V_SATA

+AVDD_USB

+3.3V_SB_IDE

C329
1U_0402_6.3V4Z

+3VS

1 1

C307 10U_0805_10V4Z
C309 1U_0402_6.3V4Z

C311 1U_0402_6.3V4Z
C313 1U_0402_6.3V4Z
C315 1U_0402_6.3V4Z
C317 1U_0402_6.3V4Z
C319 1U_0402_6.3V4Z
C321 0.1U_0402_16V4Z
C322 0.1U_0402_16V4Z

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

12

+3VS

0.8A/50mil/4vias

L36 0_0805_5%

+1.2V_HT

2 2

+1.2V_HT

+3VALW

3 3

1 2

C332 10U_0805_10V4Z
C333 1U_0402_6.3V4Z

1 2

C334 1U_0402_6.3V4Z

1 2

C335 1U_0402_6.3V4Z

1 2

C337 1U_0402_6.3V4Z

1 2

C338 0.1U_0402_16V4Z

1 2

C340 0.1U_0402_16V4Z

1 2

1.25A/50mil/4vias

L37 0_0805_5%

C346 10U_0805_10V4Z
C347 10U_0805_10V4Z

1 2

C349 10U_0805_10V4Z

1 2

C351 0.1U_0402_16V4Z

1 2

C352 0.1U_0402_16V4Z

1 2

1.25A/50mil/4vias

L40 0_0805_5%

C356 10U_0805_10V4Z

1 2

C359 10U_0805_10V4Z

1 2

C360 1U_0402_6.3V4Z

1 2

C361 1U_0402_6.3V4Z

1 2

C362 0.1U_0402_16V4Z

1 2

C363 0.1U_0402_16V4Z

1 2

C364 0.1U_0402_16V4Z

1 2

L15
M12
M14
N13
P12
P14
R11
R15
T16

L21
L22
L24
L25

A17
A24
B17
J4
J5
L1
L2

G2
G4

A10
B10

AE7
J16
K17
E9

0.6A/50mil/4vias

+1.2V_SB_CORE

0.3A/30mil/2vias

+1.2V_CKVDD

0.1A/30mil/2vias

+S5_3V

+S5_1.2V

+1.2_USB

+V5_VREF
+AVDDCK_3.3V
+AVDDCK_1.2V
+AVDDC

BLM18PG121SN1D_0603

1

C328

0.1U_0402_16V4Z

2

R197 0_0805_5%

1 2

L39 0_0603_5%

0.1U_0402_16V4Z

1 2

R195 0_0805_5%

L35

1 2

1 2

C357

L41 0_0805_5%

1 2

12

2

1

1 2

C33610U_0805_10V4Z

12
12
12
12
12
12

+1.2VALW

C35310U_0805_10V4Z

12
12

C30810U_0805_10V4Z

C3101U_0402_6.3V4Z

12

C3121U_0402_6.3V4Z

12

C3141U_0402_6.3V4Z

12

C3161U_0402_6.3V4Z

12

C3180.1U_0402_16V4Z

12

C3200.1U_0402_16V4Z

12

+3VALW

C3391U_0402_6.3V4Z
C3411U_0402_6.3V4Z
C3421U_0402_6.3V4Z
C3430.1U_0402_16V4Z
C3440.1U_0402_16V4Z
C3450.1U_0402_16V4Z

C3541U_0402_6.3V4Z
C3551U_0402_6.3V4Z

2

C358

1U_0603_10V4Z

1

12
12

+1.2V_HT

+1.2V_HT

L38 0_0603_5%

D11

CH751H-40PT_SOD323-2

+3VALW

C3652.2U_0603_6.3V4Z
C3660.1U_0402_16V4Z

+1.2VALW

C3481U_0402_6.3V4Z

12

C3500.1U_0402_16V4Z

12

R1981K_0402_5%

12

+5VS

21

+3VS

U11E

SB700

T10

AVSS_SATA_1

U10

AVSS_SATA_2

U11

AVSS_SATA_3

U12

AVSS_SATA_4

V11

AVSS_SATA_5

V14

AVSS_SATA_6

W9

AVSS_SATA_7

Y9

AVSS_SATA_8

Y11

AVSS_SATA_9

Y14

AVSS_SATA_10

Y17

AVSS_SATA_11

AA9

AVSS_SATA_12

AB9

AVSS_SATA_13

AB11

AVSS_SATA_14

AB13

AVSS_SATA_15

AB15

AVSS_SATA_16

AB17

AVSS_SATA_17

AC8

AVSS_SATA_18

AD8

AVSS_SATA_19

AE8

AVSS_SATA_20

A15

AVSS_USB_1

B15

AVSS_USB_2

C14

AVSS_USB_3

D8

AVSS_USB_4

D9

AVSS_USB_5

D11

AVSS_USB_6

D13

AVSS_USB_7

D14

AVSS_USB_8

D15

AVSS_USB_9

E15

AVSS_USB_10

F12

AVSS_USB_11

F14

AVSS_USB_12

G9

AVSS_USB_13

H9

AVSS_USB_14

H17

AVSS_USB_15

J9

AVSS_USB_16

J11

AVSS_USB_17

J12

AVSS_USB_18

J14

AVSS_USB_19

J15

AVSS_USB_20

K10

AVSS_USB_21

K12

AVSS_USB_22

K14

AVSS_USB_23

K15

AVSS_USB_24

H18

PCIE_CK_VSS_1

J17

PCIE_CK_VSS_2

J22

PCIE_CK_VSS_3

K25

PCIE_CK_VSS_4

M16

PCIE_CK_VSS_5

M17

PCIE_CK_VSS_6

M21

PCIE_CK_VSS_7

P16

PCIE_CK_VSS_8

F9

AVSSC

Part 5 of 5

218S7EALA11FG_BGA528_SB700

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42

GROUND

VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50

PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21

AVSSCK

A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24

P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25

L17

+AVDDCK_1.2V

+AVDDCK_3.3V

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

0_0805_5%

L42

1 2

L43 0_0805_5%

1 2

2007/08/02 2008/08/02

+1.2V_HT

C3672.2U_0603_6.3V4Z

12

C3680.1U_0402_16V4Z

12

+3VS

C3692.2U_0603_6.3V4Z

12

C3700.1U_0402_16V4Z

12

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SB700 PWR/GND

LA-4481P

23 46Monday, September 08, 2008

E

of

0.4

http://mycomp.su/x/

A

B

C

D

E

REQUIRED STRAPS

PCI_CLK3

PULL

1 1

2 2

HIGH

PULL
LOW

PCICLK2<20>

PCI_CLK3<20>

PCI_CLK4<20>
PCI_CLK5<20>

CLK_PCI_EC<20,34>

LPCCLK1<20>
RTC_CLK<20>
HDARST#<21,34>

GPIO17<21>
GPIO16<21>

BOOTFAIL
TIMER
ENABLED

BOOTFAIL
TIMER
DISABLED

DEFAULT

+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW

R199

10K_0402_5%

@

R209

10K_0402_5%

USE
DEBUG
STRAPS

IGNORE
DEBUG
STRAPS

DEFAULT

12

R200

@

12

R210

12

10K_0402_5%

12

10K_0402_5%

PCI_CLK4 PCI_CLK5

RESERVED

R201

@

R211

@

RESERVED

12

10K_0402_5%

12

10K_0402_5%

NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

RTC_CLKLPC_CLK1

INTERNAL
RTC

DEFAULT

EXT. RTC

(PD on X1,
apply
32KHz to
RTC_CLK)

12

12

R205

10K_0402_5%

@

R215

2.2K_0402_5%

@

12

12

R202

10K_0402_5%

@

R212

10K_0402_5%

@

12

12

AZ_RST_CD#

ENABLE PCI
MEM BOOT

DISABLE PCI
MEM BOOT

DEFAULT

12

R203

10K_0402_5%

@

12

R213

10K_0402_5%

CLKGEN
ENABLED

CLKGEN
DISABLED

DEFAULT

R204

10K_0402_5%

@

R214

10K_0402_5%

LPC_CLK0

EC
ENABLED

EC
DISABLED

DEFAULT

12

R206

10K_0402_5%

@

12

R216

10K_0402_5%

GP17

GP16PCI_CLK2

Internal pull up

H,H = Reserved

H,L = SPI ROM

L,H = LPC ROM (Default)

L,L = FWH ROM

12

12

R208

R207

10K_0402_5%

2.2K_0402_5%

@

12

12

R217

R218

2.2K_0402_5%

2.2K_0402_5%

@

DEBUG STRAPS

SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

12

2.2K_0402_5%

PCI_AD27 PCI_AD26

USE PCI
PLL

DEFAULT

BYPASS
PCI PLL

R220

@

12

2.2K_0402_5%

USE ACPI
BCLK

DEFAULT

BYPASS
ACPI
BCLK

R221

@

PCI_AD28

3 3

PCI_AD28<20>
PCI_AD27<20>
PCI_AD26<20>
PCI_AD25<20>
PCI_AD24<20>
PCI_AD23<20>

4 4

PULL
HIGH

PULL
LOW

USE
LONG
RESET

DEFAULT

USE
SHORT
RESET

R219

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

2.2K_0402_5%

C

PCI_AD25 PCI_AD24

12

2.2K_0402_5%

USE DEFAULT
PCIE STRAPS

DEFAULT

USE EEPROM
PCIE STRAPS

R223

@

USE IDE
PLL

DEFAULT

BYPASS IDE
PLL

R222

@

2007/08/02 2008/08/02

PCI_AD23

RESERVED

12

R224

2.2K_0402_5%

2.2K_0402_5%

@

Compal Secret Data

Deciphered Date

12

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SB700 STRAPS

LA-4481P

24 46Monday, September 08, 2008

E

of

0.4

http://mycomp.su/x/

A

B

C

D

E

HDD Connector

+5VS

1 1

C371

10U_0805_10V4Z

1

2

0.1U_0402_16V4Z

1.8A

1

1

2

C372

C373

2

0.1U_0402_16V4Z

1

C374

2

0.1U_0402_16V4Z

Pleace near HD CONN

+3VS

C377

@

10U_0805_10V4Z

1

2

0.1U_0402_16V4Z

1

C378

@

2

1

C379

@

2

0.1U_0402_16V4Z

1

C380

2

0.1U_0402_16V4Z

Pleace near HD CONN

JHDD

GND

A+
A-

GND

B­B+

GND

V33
V33

V33
GND
GND
GND

V5
V5
V5

GND

Reserved

GND

GND
GND

V12

V12

V12

24
23

OCTEK_SAT-22EH1G_RV

CONN@

1
2
3
4
5
6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

SATA_TXP0

0.01U_0402_16V7K

SATA_RXN0 SATA_RXN0_C

0.01U_0402_16V7K

Near CONN side.

+3VS

+5VS

SATA_TXN0

C375

12

SATA_RXP0_CSATA_RXP0

C376

12

SATA_TXP0 <22>
SATA_TXN0 <22>

SATA_RXN0_C <22>
SATA_RXP0_C <22>

2 2

10U_0805_10V4Z

+5VS

1

C381

2

0.1U_0402_16V4Z

0605 add 150uF Cap to solve hot-plug

0.1U_0402_16V4Z

1

1

2

C382

0.1U_0402_16V4Z

C383

2

Pleace near HD CONN

+3VS

10U_0805_10V4Z

1

C387

@

2

1

@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C388

1

C384

2

1

C389

@

2

0.1U_0402_16V4Z

1

+

2

1

2

C643
150U_D_6.3VM

C390

Multi-Bay Connector-option

+3VS +5VS

JP3

VCC5
VCC5
VCC5
VCC3
VCC3
VCC3
GND
GND

GND

1

GND

2

TX+

3

TX-

GND

RX-

RX+
GND
GND

GND

TYCO_2023087CONN@

4
5
6
7
8

17

0.01U_0402_16V7K

SATA_RXN1
SATA_RXP1

0.01U_0402_16V7K

16
15
14
13
12
11
10

9

18

SATA_TXP1
SATA_TXN1

SATA_RXN1_C

C385

12

SATA_RXP1_C

C386

12

Near CONN side.

SATA_TXP1 <22>
SATA_TXN1 <22>

SATA_RXN1_C <22>
SATA_RXP1_C <22>

Pleace near HD CONN

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

HDD/CDROM

LA-4481P

25 46Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

1025 add to meet HP request

0_1206_5%

D

G

2

U13

29

HSOP

30

HSON

23

HSIP

24

HSIN

33

CLKREQB

26

REFCLK_P

27

REFCLK_N

20

PERSTB

1

SROUT12

5

FB12

62

ENSR

64

RSET

19

LANWAKEB

36

ISOLATEB

60

CKTAL1

61

CKTAL2

65

EXPOSE_PAD

25

EGND

31

EGND

15

NC

17

NC

18

NC

34

NC

35

NC

39

NC

40

NC

41

NC

42

NC

RTL8111C-GR_QFN64_9X9

24
23
22
21
20
19
18
17
16
15
14
13

+3VALW+3V_LAN

S

Q13
AP2305GN

RJ45_MIDI0­RJ45_MIDI0+

RJ45_MIDI2+
RJ45_MIDI1-

RJ45_MIDI1+
RJ45_MIDI3-

RJ45_MIDI3+

68mA

1 1

LAN_POWER_OFF<34>

@

R226

1 2

1 3

Place Close to Chip

0.1U_0402_16V4Z

1 2
1 2

0.1U_0402_16V4Z

R229

1 2

1
2
3
4
5
6
7
8

9
10
11
12

1

C437

0.01U_0402_16V7K

2

0.01U_0402_16V7K

PCIE_RXP2_LAN
PCIE_RXN2_LAN

GLAN_REQ#

+CTRL_18

0_0603_5%

2.49K_0402_1%

GLAN_WAKE#
ISOLATEB

LAN_X1
LAN_X2

U15

TCT1
TD1+
TD1­TCT2
TD2+
TD2­TCT3
TD3+
TD3­TCT4
TD4+
TD4-

NS692405

MCT1
MX1+

MX1­MCT2
MX2+

MX2­MCT3
MX3+

MX3­MCT4
MX4+

MX4-

C434

+LAN_VDD12

1

C435

2

C411
C412

1 2

R228 0_0402_5%

+3V_LAN

R230

R231

1 2

0_0402_5%

1

C436

2

GLAN_RXP<11>
GLAN_RXN<11>
GLAN_TXP<11>
GLAN_TXN<11>

CLKREQ_LAN#<16>
CLK_PCIE_LAN<16>

CLK_PCIE_LAN#<16>

2 2

+3VS

3 3

4 4

PLT_RST#<12,15,20,27,33,34>

LAN_PCIE_WAKE#<21>
ISOLATEB<22>

12

@

R232
1K_0402_1%

ISOLATEB

R233
15K_0402_5%

LAN_MDI0­LAN_MDI0+

LAN_MDI2- RJ45_MIDI2­LAN_MDI2+

LAN_MDI1­LAN_MDI1+

LAN_MDI3­LAN_MDI3+

1

0.01U_0402_16V7K

0.01U_0402_16V7K

2

Place these components
colsed to LAN chip

A

EEDO

EEDI/AUX

EESK
EECS

LED3
LED2
LED1
LED0

MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3

DVDD12
DVDD12
DVDD12
DVDD12
DVDD12
DVDD12

EVDD12
EVDD12

VDD33
VDD33
VDD33
VDD33

VDDSR

AVDD33
AVDD33

AVDD12
AVDD12
AVDD12
AVDD12

IGPIO

OGPIO

B

45
47
48
44

54
55
56
57

3
4
6
7
9
10
12
13

21
32
38
43
49
52

22
28

16
37
46
53

63
2

59
8

11
14
58

50
51

C426

C427

C429

C430

HP PoE solution

B

3.6K_0402_5%
R227

1 2

LAN_LINK#
LAN_ACTIVITY#

LAN_MDI0+
LAN_MDI0­LAN_MDI1+
LAN_MDI1­LAN_MDI2+
LAN_MDI2­LAN_MDI3+
LAN_MDI3-

+LAN_VDD12

+3V_LAN

+3V_LAN

DSM#

1 2

0.01U_0402_16V7K

1 2

0.01U_0402_16V7K

1 2

0.01U_0402_16V7K

1 2

0.01U_0402_16V7K

+LAN_EVDD12

22U_0805_6.3VAM

+LAN_VDD12

+3V_LAN

C423

C

+3V_LAN

2

2

C397

0.1U_0402_16V4Z

C398

0.1U_0402_16V4Z

1

1

Close to Pin2 & pin59

4.7uHc
hok

e

L45

+CTRL_18

1 2

4.7UH_1008HC-472EJFS-A_5%_1008

Close to Pin1

22U_0805_6.3VAM

Y4

LAN_X2LAN_X1

12

25MHZ_20P

1

C421

27P_0402_50V8J

L47

1

1

C424

0.1U_0402_16V4Z

2

2

1 2

R235 10K_0402_5%@

1 2

R236 0_0402_5%

R237

1 2

75_0402_1%
R238

1 2

75_0402_1%
R239

1 2

75_0402_1%
R241

1 2

75_0402_1%

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0_0603_5%

RJ45_GND

Issued Date

2

+3V_LAN

C

+3VALW

LAN_DSM# <21>

C433

1 2

1000P_1808_3KV7K

2007/08/02 2008/08/02

+LAN_VDD12

2

C409

1

1

C422
27P_0402_50V8J

2

LAN_ACTIVITY#

LAN_LINK#

LAN_LINK#
LAN_ACTIVITY#

2

C410

0.1U_0402_16V4Z

1

1

@

C425

@

C428

2

2

1

3

D36

@

68P_0402_50V8K

68P_0402_50V8K

PSOT24C_SOT23-3

Compal Secret Data

Deciphered Date

R234 300_0402_5%

R240 300_0402_5%

2

1

D

Close to Pin16,37,46,53

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

2

C403

C404

1

1

0.1U_0402_16V4Z

close to pin 5 for EMI

2

1

0.1U_0402_16V4Z

+LAN_VDD12

+3V_LAN

12

RJ45_MIDI3­RJ45_MIDI3+
RJ45_MIDI1­RJ45_MIDI2­RJ45_MIDI2+
RJ45_MIDI1+
RJ45_MIDI0­RJ45_MIDI0+

+3V_LAN

12

1

2

D

0.1U_0402_16V4Z

2

2

C399

1

1

2

C405

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C414

C413

1

0.1U_0402_16V4Z

L46

LAN Conn.

JRJ45

13

Yellow LED+

14

Yellow LED-

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

11

Green LED+

12

Green LED-

FOX_JM36113-P1123-7F

CONN@

C431

0.1U_0402_16V4Z

E

+3V_LAN

2

2

C401

C400

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C406

1

0.1U_0402_16V4Z

2

C415

1

0_0603_5%

0.1U_0402_16V4Z

1U_0402_6.3V6K

1

0.1U_0402_16V4Z

2

C407

1

0.1U_0402_16V4Z

2

C416

1

0.1U_0402_16V4Z

+LAN_EVDD12

2

C419

1

C402

0.1U_0402_16V4Z

+LAN_VDD12

2

C408

1

2

C417

1

2

C420

1

close to pin 28 for EMI

16

SHLD1

DETECT PIN1

DETCET PIN2

Title

Size Document Number Rev

Custom

Date: Sheet

9

10
15

SHLD1

LANGND

1

C432

4.7U_0805_10V4Z

2

Compal Electronics, Inc.

RTL8111C/8102E 10/100/1000 LAN

LA-4481P

26 46Monday, September 08, 2008

E

of

0.4

http://mycomp.su/x/

A

Mini Card Slot 1---WLAN

+3VS +1.5VS+3VS_WLAN +1.5VS_WLAN +3VALW_WLAN

Max 1A Max 0.5A

R242

12

0_0805_5%

C438

0.1U_0402_16V4Z

1 1

2 2

MINI_PCIE_WAKE#<21>

CH_DATA<32>

CH_CLK<32>

CLKREQ_MCARD2#<16>

CLK_PCIE_MCARD2#<16>

CLK_PCIE_MCARD2<16>

PCIE_PTX_C_IRX_N2<11>
PCIE_PTX_C_IRX_P2<11>

PCIE_ITX_C_PRX_N2<11>
PCIE_ITX_C_PRX_P2<11>

+3VS_WLAN

BT_COMBO_EN#<22>

1

1

2

R250 0_0603_5%

2

MINI_PCIE_WAKE#
CH_DATA
CH_CLK

1 2

R252

1 2

0_0402_5%

4.7K_0402_5%

C439

4.7U_0805_10V4Z

CH_CLK

12

R253

R243

1 2

0_0805_5%

C440

0.01U_0402_16V7K

JP4

1

1

3

3

5

5

7

7

9

9
111112
131314
151516

171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152

G153G254G355G3

1

2

0.1U_0402_16V4Z

2

2

4

4

6

6

8

8

10

10

12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

CONN@

56

FOX_AS0B226-S99N-7F

9/20 SP01000HS00/SP01000LX00

1

C441

2

WL_OFF#
PLT_RST#

SMB_CK_CLK1
SMB_CK_DAT1

WL_LED#

B

1

C442

4.7U_0805_10V4Z

2

+3VS_WLAN
+1.5VS_WLAN

CH751H-40PT_SOD323-2

+3VALW_WLAN

Max 0.3A

1

2

2 1

D35

USB20_N6 <21>
USB20_P6 <21>

WL_LED# <35>

R244 0_0805_5%

1 2

C443

R245 0_0805_5%@

0.1U_0402_16V4Z

0804 change power rail

+3VS_WLAN

1 2

WLOFF# <22>

+3VALW

C

D

E

9/20 STANDOFF (H=7.5 mm) ES000000D00

New Card

C453

0.1U_0402_16V4Z

12

C456

0.1U_0402_16V4Z

12

Max 0.275A

3 3

+3VALW

C457

PLT_RST#<12,15,20,26,33,34>

SYSON<34,35,36,40>
SUSP#<29,34,36,38,41>

EXP_CPPE#<21>

0.1U_0402_16V4Z

12

+3VS

PLT_RST#

EXP_CPPE#

Express Card Power Switch

+1.5VS

U16

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin
AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

THERMAL_PAD

18

RCLKEN

R5538D001-TR-F_QFN20_4X4~D

1.5Vout

1.5Vout

3.3Vout

3.3Vout

OC#

PERST#

GND

11
13

3
5

15
19
8
16

NC

7

21

+3V_PEC

PERST#

+1.5VS_PEC

Max 0.65A

+3VS_PEC

Max 1.3A

USE TI TPS2231MRGPR

Near to Express Card slot.

USB20_N8<21>

USB20_P8<21>

SMB_CK_CLK1<21>
SMB_CK_DAT1<21>

CLKREQ_NCARD#<16>

CLK_PCIE_NCARD#<16>

CLK_PCIE_NCARD<16>

4 4

PCIE_PTX_C_IRX_N0<11>
PCIE_PTX_C_IRX_P0<11>

PCIE_ITX_C_PRX_N0<11>
PCIE_ITX_C_PRX_P0<11>

+1.5VS_PEC

+3V_PEC

+3VS_PEC

330P_0402_50V7K

A

EXP_CPPE#

SMB_CK_CLK1
SMB_CK_DAT1

MINI_PCIE_WAKE#

PERST#

CLKREQ_NCARD#

EXP_CPPE#

1

C466

@

2

JEXP

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

29

GND

30

GND

ACES_91740-02644_LB

CONN@

+3VS_PEC

C460

+1.5VS_PEC

C462

+3V_PEC

C464

4.7U_0805_10V4Z

1

C461

2

0.1U_0402_16V4Z

4.7U_0805_10V4Z

1

C463

2

0.1U_0402_16V4Z

4.7U_0805_10V4Z

1

C465

2

0.1U_0402_16V4Z

B

1

2

1

2

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

WLAN/TV tuner/Express Card

LA-4481P

27 46Monday, September 08, 2008

E

of

0.4

http://mycomp.su/x/

+3VS

R417

100K_0402_5%

1 2

1

C630

1U_0402_6.3V6K

D D

2

0804 Change value for brightness

R276

1 2

+3VS

1.2K_0402_5%

5

R418 0_0402_5%

R420
499K_0402_1%~D

@

1 2

White

D16

2 1

HT-110TW_WHITE

0901 Change D16 footprint

RST#

12

4.7U_0603_6.3V6K

R277

0_0402_5%

1 2

1U_0603_16V6K

+3VS

C635

1

2

0.1U_0402_16V4Z

CR_LED#

+VCC_4IN1

1

C628

0.1U_0402_16V4Z

+3VS

C631

1

2

C636

1

2

0.1U_0402_16V4Z

1

C632

2

0.1U_0402_16V4Z

USB20_N7<21>
USB20_P7<21>

2

1

C633

2

RST#
MODE SEL

XTLO
XTLI

USB20_N7
USB20_P7
CR_LED#

0901 Change power rail for Vendor suggestion

MODE SEL

C C

1

2

47P_0402_50V8J

@

C638

R424

10K_0402_5%

1 2

CLK_48M_CR<16>

@

48MHZ_16PF_FSX3M 12.000M16FAQ@

R278

0_0402_5%

1 2

6P_0402_50V8J

C640

Y6

4

XTLI

334

1

221

2

1

XTLO

6.19K_0402_1%
R425

2

C641
6P_0402_50V8J

1

4

0.1U_0402_16V4Z
C629

1 2

U31

1

AV_PLL

3

NC

7

NC

9

CARD_3V3

11

D3V3

33

D3V3

8

3V3_IN

44

RST#

45

MODE_SEL

47

XTLO

48

XTLI

4

DM

5

DP

14

GPIO0

12

2

RREF

12

DGND

32

DGND

6

AGND

46

AGND

RTS5158E-GR_LQFP48_7X7

1 2

R419 0_0402_5%

SD_DAT2/XD_RE#_SP16

SD_DAT3/XD_WE#_SP15

SD_DAT4/XD_WP#/MS_D7_SP13

SD_DAT5/XD_D0/MS_D6_SP12

SD_CLK/XD_D1/MS_CLK_SP11

SD_DAT6/XD_D7/MS_D3_SP10

SD_DAT7/XD_D2/MS_D2_SP8
SD_DAT0/XD_D6/MS_D0_SP7
SD_DAT1/XD_D3/MS_D1_SP6

XD_D4/SD_DAT1_SP4

R422
10_0402_5%@

10P_0402_50V8J

C637

@

VREG

MS_D4

XD_CLE_SP19
XD_CE#_SP18
XD_ALE_SP17

XD_RDY_SP14

MS_INS#_SP9

XD_D5_SP5

SD_CD#_SP3

SD_WP_SP2

XD_CD#_SP1

EEDI

XTAL_CTR

MS_D5

EEDO

EECS
EESK

SD_CMD

MSCLK

NC

12

1

2

10
22
30

XD_CLE

43

XDCE#

42

XD_ALE

41

XD_RE#_SDD2

40

XDWE#_SDD3

39

XDRDY

38

XDWP#_SDD4

37

XDD0_SDD5

35

XDD1

34

XDD7_SDD6_MSD3

31

MSINS#

29

XDD2_SDD7_MSD2

28

XDD6_SDD0_MSD0

27

XDD3_MSD1

26

XDD5_MSBS

25

XDD4_SDD1

23

SDCD#

21

SDWP

20

XDCD#

19
18

13
24

15
16
17
36

10P_0402_50V8J

@

C634

1U_0603_10V4Z

1 2

R423 0_0402_5%

1 2

SDCMD

SDCLK

12

R427
10_0402_5%@

1

C639

2

1 2
1 2

+3VS

3

2

1

Card Reader Connector

MSCLK

R4210_0402_5%

SDCLK

R4280_0402_5%

JREAD

+VCC_4IN1 +VCC_4IN1

XDD0_SDD5
XDD1
XDD2_SDD7_MSD2
XDD3_MSD1
XDD4_SDD1
XDD5_MSBS
XDD6_SDD0_MSD0
XDD7_SDD6_MSD3

XDWE#_SDD3
XDWP#_SDD4
XD_ALE
XDCD#
XDRDY
XD_RE#_SDD2
XDCE#
XD_CLE

3

XD-VCC

32

XD-D0

10

XD-D1

9

XD-D2

8

XD-D3

7

XD-D4

6

XD-D5

5

XD-D6

4

XD-D7

34

XD-WE

33

XD-WP

35

XD-ALE

40

XD-CD

39

XD-R/B

38

XD-RE

37

XD-CE

36

XD-CLE

11

7IN1 GND

31

7IN1 GND

41

7IN1 GND

42

7IN1 GND

TAITW_R015-B10-LM

CONN@

7 IN 1 CONN

SD-VCC

MS-VCC

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7

SD-CMD

SD-CD-SW
SD-WP-SW

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

MS-INS

MS-BS

21
28

SDCLK

20

XDD6_SDD0_MSD0

14

XDD4_SDD1

12

XD_RE#_SDD2

30

XDWE#_SDD3

29

XDWP#_SDD4

27

XDD0_SDD5

23

XDD7_SDD6_MSD3

18

XDD2_SDD7_MSD2

16

SDCMD

25

SDCD#

1

SDWP

2

MSCLK

26

XDD6_SDD0_MSD0

17

XDD3_MSD1

15

XDD2_SDD7_MSD2

19

XDD7_SDD6_MSD3

24

MSINS#

22

XDD5_MSBS

13

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/10/06

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom
Date: Sheet

Compal Electronics, Inc.

USB CardReader&CONN

LA-4481P

1

28 46Monday, September 08, 2008

of

0.4

http://mycomp.su/x/

A

B

C

D

E

CODEC POWER

R279

1 2

+3VS

BLM18BD601SN1D_0603

1 1

+3VDD_CODEC +VDDA_CODEC

0.1U_0402_16V4Z

1

C486

C487

2

1U_0603_10V4Z

+3VS_HDA

R280

1 2

BLM18BD601SN1D_0603

1

2

1

C488

0.1U_0402_16V4Z

2

+VDDA_CODEC_R+3VS

1

C489

2

0.1U_0402_16V4Z

R281

1 2

0_0603_5%

1

C490
1U_0603_10V4Z

2

W=40Mil

1 2

C485 0.1U_0402_16V4Z

SUSP#<27,34,36,38,41>

+5VALW +VDDA_CODEC

U19

1

IN

OUT

2

GND

3

SHDN

BYP

G9191-475T1U_SOT23-5

5

4

1

2

1

C492

0.1U_0402_16V4Z

2

C491

2.2U_0805_16V4Z

(4.75V(4.56~4.94V))

300mA

U20

+3VDD_CODEC

+VDDA_CODEC_R

+3VS_HDA

HDA_BITCLK_CODEC

12

@

R282

47_0402_5%

2 2

33P_0402_50V8K

1

C493

@

2

EC_BEEP<34>
SB_SPKR<21>

HDA_BITCLK_CODEC<21>
HDA_SDOUT_CODEC<21>

HDA_SDIN0<21>

HDA_SYNC_CODEC<21>

HDA_RST#_CODEC<21>

DMIC_CLK<18>

R287 47K_0402_5%@

1 2

R289 47K_0402_5%

1 2

R290 10K_0402_5%

1 2

C497 0.1U_0402_16V4Z

1 2

0730 add R301 fix MIC auto switch

3 3

HDA_BITCLK_CODEC
HDA_SDOUT_CODEC

R283 33_0402_5%

HDA_SYNC_CODEC
HDA_RST#_CODEC

+VDDA_CODEC_R

1 2

R288

1 2

FBMA-L10-160808-301LMT 0603

C495 1U_0603_10V4Z

1 2

0.1U_0402_16V4Z
C496

10K_0402_5%

R301

10U_0805_10V4Z
C500

1 2

VC_REFA

MONO_INR

9

DVDD_CORE*

1

DVDD_CORE

25

AVDD1*

38

AVDD2**

3

DVDD_IO

32

MONO_OUT

6

BITCLK

5

SDO

8

SDI_CODEC

10

SYNC

11

RESET#

46

DMIC_CLK

33

12

12

CAP2

12

PCBEEP

40

NC / OTP

34

SENSE_B / NC

37

NC

18

NC

19

NC

20

NC

27

VREFFILT

26

AVSS1*

42

AVSS2**

7

DVSS**

92HD71B7X5NLGXA1X8_QFN48_7X7

EAPD/ SPDIF OUT 0 or 1 / GPIO 0

VOL_UP/DMIC_0/GPIO 1
VOL_DN/DMIC_1/GPIO 2

GPIO 3

VREFOUT-E / GPIO 4

GPIO 5
GPIO 6

SPDIF OUT1 / GPIO 7

SPDIF OUT0

VREFOUT-B
VREFOUT-C

SENSE_A

PORTA_R
PORTA_L

PORTB_R
PORTB_L

PORTC_R
PORTC_L

PORTD_R
PORTD_L

PORTE_R

PORTE_L

PORTF_R

PORTF_L

EAPD_CODEC

47
2
4
30
31
43
44
45
48

28
29

SENSE

13

HP_OUTR

41

HP_OUTL

39

MIC_EXTR

22

MIC_EXTL

21

24
23

LINE_OUT_R

36

LINE_OUT_L

35

15
14

17
16

EAPD_CODEC <34>
DMIC_DAT <18>

0509 Solve MIC no function

VREFOUT_B <30>

R284 5.1K_0402_1%

1 2

R285 20K_0402_1%

1 2

R286 39.2K_0402_1%

1 2

C494 0.1U_0402_16V4Z

1 2

HP_OUTR <30>
HP_OUTL <30>

1 2

C498 1U_0603_10V6K

1 2

C499 1U_0603_10V6K

LINE_OUT_R <30>
LINE_OUT_L <30>

+VDDA_CODEC_R

HP Jack & Dock

Internal SPKR.

EXTMIC_DET# <30>
JACK_DET# <30>

MIC_EXT_R <30>
MIC_EXT_L <30>

Jack MIC

C501

@

1 2

0.1U_0402_16V4Z

C502

@

1 2

0.1U_0402_16V4Z

C503

SENSE A

Port

4 4

A

B

C

D

39.2K E

20K

10K

5.11K

A

PortResistor

F

G

H

SENSE B

Resistor

39.2K

20K

10K

5.11K

@

1 2

C504

@

1 2

@

1 2

0_0402_5%

@

1 2

0_0805_5%

1 2

0_1206_5%

B

R292

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R291

R293

Use an 80mil to
connection or place
a 1206 resistor under
CODEC with double
vias.

Security Classification

GNDA <30>

GNDAGND

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Audio Codec-IDT9271B7

LA-4481P

29 46Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

R294

0.1U_0402_16V4Z

+5VS

1 1

R297

LINE_OUT_R<29>

LINE_OUT_L<29>

2 2

0_0402_5%

R300

0_0402_5%

12

12

12

0_1206_5%

C512 0.022U_0603_25V7K
C513 47P_0402_50V8J
C514 0.022U_0603_25V7K
C515 47P_0402_50V8J

C516 0.022U_0603_25V7K
C517 47P_0402_50V8J
C518 0.022U_0603_25V7K
C519 47P_0402_50V8J

1

2

0.1U_0402_16V4Z

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

EC_MUTE#<34>

C505

1

C506

2

1

C507

2

EC_MUTE#

10U_0805_10V4Z

U21

7

17

9

5

19

RIN+

RIN-

LIN+

LIN-

SHUTDOWN

+5VAMP

20

B

16

15

6

VDD

PVDD1

PVDD2

GND41GND311GND213GND1

2

GAIN0

3

GAIN1

18

ROUT+

14

ROUT-

4

LOUT+

8

LOUT-

12

NC

10

BYPASS

THERMAL PAD

21

TPA6017A2_TSSOP20

R295

@

100K_0402_5%

SPKR+

R298

SPKR-

100K_0402_5%

SPKL+

SPKL-

Keep 10 mil width

1

C520
1U_0805_25V4Z

2

1UF

10 dB

12

12

+5VS

12

R296

100K_0402_5%

12

R299
100K_0402_5%

C

GAIN0 GAIN1 Av(inv)

0

0

1

1

@

0

1

0

1

6dB

10dB

15.6dB

21.6dB

D

E

SPEAKER

SPKR­SPKR+
SPKL­SPKL+

C508

100P_0402_50V8J

@

PSOT24C_SOT23-3

1

2

D55

1

C509

2

100P_0402_50V8J

2

3

1

1

C510

2

100P_0402_50V8J

3

D56

@

C511

100P_0402_50V8J

2

PSOT24C_SOT23-3

1

JP7

1

1

2

2

3

3

4

4

5

1

GND1

6

GND2

2

E&T_3806-F04N-02RCONN@

0804 Reserve ESD doide

3 3

VREFOUT_B<29>

0605 Remove Transisters.

0605 change Cap size to solve DFB issue.

+

HP_OUTR<29>

HP_OUTL<29>

4 4

A

1 2

C523 150U_B_6.3VM_R40M

+

1 2

C524 150U_B_6.3VM_R40M

B

HP_OUT_R

HP_OUT_L

0509 Solve MIC no function

R429

0_0402_5%

4.7K_0402_5%

JP48

1
2
3
4
5
6
7
8
9

10

13

11

GND

14

12

GND

ACES_85201-1205N

CONN@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C642

12

R430

1
2
3
4
5
6
7
8
9
10
11
12

C

1 2

1U_0603_10V4Z

12

12

R431

4.7K_0402_5%

EXT_MIC_R
EXT_MIC_L

HP_OUT_R
HP_OUT_L

EXTMIC_DET#
JACK_DET#

CIR_IN

+5VL

2007/08/02 2008/08/02

MIC_EXT_R <29>

MIC_EXT_L <29>

EXTMIC_DET# <29>
JACK_DET# <29>

CIR_IN <34>

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

AMP & Audio Jack

LA-4481P

30 46Monday, September 08, 2008

E

of

0.4

http://mycomp.su/x/

A

B

C

D

E

ACCELEROMETER

+3VS_ACL+3VS +3VS_ACL_IO

1

2

R308 0_0603_5%

1 2

1

C528
10U_0805_6.3V6M

2

D19

2 1

CH751H-40PT_SOD323-2

1 1

C527

0.1U_0402_16V4Z

SMB_CK_CLK0

14

VDDIO absolute man

U22

rating is VDD+0.1

Vdd_IO
GND
Reserved
GND
GND
Vdd

12

SCL / SPC

SDA / SDI / SDO

SDO

Reserved

GND
INT 2
INT 1

CS

LIS302DLTR_LGA14_3x5

7

+3VS_ACL_IO

2 2

3 3

+3VS_ACL

R310
0_0402_5%

1 2

1
2
3
4
5
6

R312 10K_0402_5%

Must be placed in the center of the system.

SMB_CK_DAT0

13

R311

12

0_0402_5%

1 2

11
10
9
8

SMB_CK_CLK0 <9,10,16,21>

0011101b

SMB_CK_DAT0 <9,10,16,21>

HDD_HALTLED <35>
ACCEL_INT <20>

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Accelerometer

LA-4481P

31 46Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

B

C

D

E

E-SATA Combo & USB-1

Max 2.5A

1 1

1

C531

4.7U_0805_10V4Z

2

USB_EN#<34>

U23

1

GND

2
3
4

OUT

IN

OUT
OUT

IN

OC#

EN#

TPS2061IDGN_MSOP8~N

8
7
6

1

5

+

C530

2

150U_D_6.3VM

USB-3

2 2

U24

1

GND

2

IN

3

IN

1

C537

4.7U_0805_10V4Z

3 3

2

USB_EN#

USB20_N2<21>

USB20_P2<21>

+5VALW

USB20_N2_R

4

EN#

TPS2061IDGN_MSOP8~N

L56

4

4

1

1

WCM-2012-900T_0805

D24

4

VIN

3

IO2

PRTR5V0U2X_SOT143-4@

GND

8

OUT

7

OUT

6

OUT

5

OC#

3

2

2

IO1

1

3

2

USB20_P2_R

C536

150U_D_6.3VM

+USB_VCCB

USB20_N2_R
USB20_P2_R

+USB_VCCA+5VALW

W=100mils

1

C532

2

0.1U_0402_16V4Z
1000P_0402_50V7K

+USB_VCCB+5VALW

W=100mils

1

1

+

C538

2

2

0.1U_0402_16V4Z

JP11

1

USB+5V

2

USBN1

3

USBP1

SHADIN

GND4SHADIN

SUYIN_020173MR004S592ZL

CONN@

1

C533

2

Max 2.5A

1

C539

2

1000P_0402_50V7K

L55

USB20_N0<21>

USB20_P0<21>

+5VALW

USB20_P0_R

4

4

1

1

WCM-2012-900T_0805

D21

4

IO1

VIN

3

GND

IO2

PRTR5V0U2X_SOT143-4@

BT Connector

6
5

BT_OFF<22>

+USB_VCCA

3

3

USB20_N0_R
USB20_P0_R

2

2

USB20_N0_R

2
1

JP10

CONN@

GND2
GND1

ACES 87213-0800G

1

C540
1U_0603_10V4Z

2

Check BT power consumption < 1A

SUYIN_020173MR004S592ZL
JP9

1

USB+5V

2

USBN1

3

USBP1

SHADIN

GND4SHADIN

CONN@

0509 Solve MIC no function

10
9
8

8

7

7

USB20_P3

6

6

USB20_N3

5

5

4

4

R313 1K_0402_5%@

3

3

2

2

1

1

1 2

10K_0402_5%

R316

R314 1K_0402_5%@

+3VAUX_BT

USB20_N3

12

R315
100K_0402_5%

1 2
1 2

6
5

D23

4

VIN

3

GND

IO2

PRTR5V0U2X_SOT143-4@

Q21 SI2301BDS-T1-E3_SOT23-3

S

D

13

G

2

0.01U_0402_16V7K

1 2

C544 0.1U_0402_16V4Z

2

IO1

1

1

C541

2

+3VAUX_BT

USB20_P3

+3VAUX_BT+3VALW

0.1U_0402_16V4Z

1

C542

2

4.7U_0805_10V4Z

1

2

C543

+USB_VCCA

USB20_N1<21>

SATA_TXP2<22>
SATA_TXN2<22>

SATA_RXN2_C<22>
SATA_RXP2_C<22>

+USB_VCCA

SATA_TXN2

USB20_P3 <21>
USB20_N3 <21>
BT_LED <35>
CH_DATA <27>

CH_CLK <27>

USB20_N1_R

USB20_P1<21>

D20

4

VIN

3

IO2

PRTR5V0U2X_SOT143-4@

L54

4

1

C534 1000P_0402_50V7K
C535 1000P_0402_50V7K

D22

4

IO1

VIN

3

GND

IO2

PRTR5V0U2X_SOT143-4@

USB20_P1_R

2

IO1

1

GND

4

1

WCM-2012-900T_4P

1 2
1 2

SATA_TXP2

2
1

3

2

3

2

ESATA Combo

Max 0.5A

+USB_VCCA

USB20_N1_R
USB20_P1_R

SATA_TXP2
SATA_TXN2

SATA_RXN2
SATA_RXP2

0605 add GND shaping

CONN@

JP8

1

B_VCC

2

B_D-

3

B_D+

4

B_GND

5

GND

6

A+

7

A-

8

GND

9

B-

10

B+

11

GND

TYCO_1759576-1

USB

ESATA

SHIELD
SHIELD
SHIELD
SHIELD

12
13
14
15

Finger printer

R317

1 2

0_0603_5%@

Q20 SI2301BDS-T1-E3_SOT23-3@

S

D

13

G

2

USB_EN#

USB20_N4<21>

4 4

+3VS_FB
USB20_N4

USB20_P4<21>

D25

4
3

PRTR5V0U2X_SOT143-4

2

IO1

VIN

1

GND

IO2

USB20_P4

+3VS_FB

1

C545

0.1U_0402_16V4Z

2

USB20_N4
USB20_P4

R318

1 2

0_0603_5%

JP12

1

1

2

2

3

3

4

4

ACES_85201-04051

CONN@

0730 change conn fix DFB issue.

0804 moute it for ESD.

A

+3VS+3VALW

5

G1

6

G2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

USB, BT, eSATA,FPR

LA-4481P

32 46Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

B

C

D

E

C546

SPI_CS#<34>
SPI_CLK<34>

1

2

+3VL

20mils

SPI_CLK

C548

@

22P_0402_25V8K

CONN@

U25

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

WIESON G6179 8P SPI

VSS

4

2

Q

0605 remove 0 ohm resisters

R325

@

33_0402_5%

1 2
1

2

&U1

45@

SST25VF080B-50-4C-S2AF_SO8

EC_SI_SPI_SO <34>

+3VL

1

0.1U_0402_16V4Z@

1 1

2 2

SMB_EC_CK1<7,34,35,37>
SMB_EC_DA1<7,34,35,37>

C547

2

U26

8
7
6
5

AT24C16AN-10SI-2.7_SO8@

VCC
WP
SCL
SDA

GND

A0
A1
A2

12

R319

@

100K_0402_5%

1
2
3
4

12

R324

@

100K_0402_5%

SPI Flash (8Mb*1)

0.1U_0402_16V4Z

EC_SO_SPI_SI<34>

0605 Remove LPC debug connector

3 3

SIRQ<20,34>

LPC_AD3<20,34>

LPC_AD1<20,34>

LPC_FRAME#<20,34>

4 4

A

LPC Debug Port

+3VALW

SIRQ

LPC_AD3

LPC_AD1

LPC_FRAME#

7

8

9

10

H1

LPC_DRQ#

56

PLT_RST#

4

LPC_AD2

3

LPC_AD0

2

CLK_PCI_SIO

1

DEBUG_PAD@

B

@

1 2
2

1

PLT_RST# <12,15,20,26,27,34>

LPC_AD2 <20,34>

LPC_AD0 <20,34>

CLK_PCI_SIO <20>

R329

22_0402_5%

C550

@

22P_0402_50V8J

LPC_DRQ# <20>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

BIOS ROM/Debug Tool

LA-4481P

33 46Monday, September 08, 2008

E

of

0.4

http://mycomp.su/x/

A

B

C

D

E

+3VL_EC

0.1U_0402_16V4Z

1

1

2

0.1U_0402_16V4Z

1 1

2 2

3 3

4 4

ESB_CLK
ESB_DAT

LAN_POWER_OFF<26>

SMB_EC_DA1
SMB_EC_CK1

SMB_EC_DA2
SMB_EC_CK2

SUSP#

12

R337
100K_0402_5%

C552

C551

2

R331 4.7K_0402_5%
R332 4.7K_0402_5%

R333 4.7K_0402_5%
R334 4.7K_0402_5%

SYSON

12

R338
100K_0402_5%

R346 4.7K_0402_5%

1 2

R347 4.7K_0402_5%

1 2

0509 change value to solve ENE cap-board could not detect

VLDT_EN

R412
10K_0402_5%

1 2

1

C553

2

1000P_0402_50V7K

1 2
1 2

1 2
1 2

CLK_PCI_EC<20,24>

ON/OFF#<35>

LAN_POWER_OFF

0.1U_0402_16V4Z

1

2

+3VL

+3VALW

1 2

0_0402_5%

1

C554

2

C573

1 2

15P_0402_50V8J@

R336

C585 0.1U_0402_16V4Z

12

R339
10K_0402_5%

LID_SW#

+3VL

+3VL

4.7K_0402_5%

R414

1000P_0402_50V7K

C555

+3VL

+3VS

R335

1 2

33_0402_5%@

1 2

47K_0402_5%

12

R348

12

32.768KHZ_12.5PF_9H03200413

E51_RXD

+3VL +3VL_EC

R330

1 2

0_0805_5%

U28

CRY2

12

@

R350
20M_0402_5%

CRY1

GATEA20
KB_RST#
SIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_PCI_EC

PLT_RST#
ECRST#
EC_SCI#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
ESB_CLK
ESB_DAT

E51_TXD
E51_RXD

GATEA20<21>
KB_RST#<21>
SIRQ<20,33>

LPC_FRAME#<20,33>

LPC_AD3<20,33>
LPC_AD2<20,33>
LPC_AD1<20,33>
LPC_AD0<20,33>

PLT_RST#<12,15,20,26,27,33>

EC_SCI#<21>

HDARST#<21,24>

SMB_EC_CK1<7,33,35,37>
SMB_EC_DA1<7,33,35,37>
SMB_EC_CK2<7>
SMB_EC_DA2<7>

SLP_S3#<21>
SLP_S5#<21> EC_LID_OUT# <21>
EC_SMI#<21>
LID_SW#<35>

ESB_CLK<35>
ESB_DAT<35>

H_THERMTRIP#_EC<7>

VLDT_EN<36>

NUM_LED#<35>

C587
15P_0402_50V8J

1 2

Y5

3
2

OSC

NC

OSC

NC

1 2

C589
15P_0402_50V8J

4
1

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LPC & MISC

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

LID_SW#/GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT#/GPIO0C

19

EC_PME#/GPIO0D

25

EC_THERM#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LED#/GPIO19

36

NUMLED#/GPIO1A

122

XCLK1

123

XCLK0

+3VL_EC

+EC_AVCC

Int. K/B
Matrix

SM Bus

12

L57
0_0603_5%

1 2

C590 0.1U_0402_16V4Z

+EC_AVCC

9

22

33

96

111

125

VCC

VCC

VCC

VCC

VCC

VCC

PWM Output

AD Input

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

GPIO

GPO

GPIO

GPI

GND

GND

GND

GND

GND

11

24

35

94

113

67

AVCC

INVT_PWM/PWM1/GPIO0F

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

ACOFF/FANPWM2/GPIO13

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B
AD4/GPIO42

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C

PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10
GPXO11

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

AGND

KB926QFC0_LQFP128_14X14

69

ECAGND

L58

1 2

0_0603_5%

INV_PWM

21

FAN_PWM

23
26

ACOFF

27

BATT_TEMP

63

BATT_OVP

64
65
66

TP_BTN#

75
76

68
70

IREF

71
72

83
84
85
86

TP_CLK

87

TP_DATA

88

AC_LED#

97
98
99
109

119
120
126
128

73
74
89
90
91
92
93
95
121
127

100
101
102
103
104
105
106
107
108

110
112
114
115
116
117
118

124

R409 100K_0402_5%

CIR_IN
FSTCHG

BAT_LED#
ON/OFFBTN_LED#
SYSON
VR_ON
ACIN_D

EC_RSMRST#

WL_BLUE_LED#

SB_PWRGD
BKOFF#

TP_LED#

SUSP#
PWRBTN_OUT#

C588 4.7U_0805_10V4Z

12

1 2

BATT_OVP

INV_PWM <18>
FAN_PWM <5>
EC_BEEP <29>
ACOFF <38>

C574

BATT_TEMP <37>
BATT_OVP <37>
ADP_I <38>
ADP_ID <37>

TP_BTN# <35>

DAC_BRIG <18>
VCTRL <38>
IREF <38>
AC_SET <38>

EC_MUTE# <30>

USB_EN# <32>

I2C_INT <35>
TP_CLK <35>

TP_DATA <35>

AC_LED# <37>

VGATE <43>

EC_SI_SPI_SO <33>
EC_SO_SPI_SI <33>
SPI_CLK <33>
SPI_CS# <33>

CIR_IN <30>
FSTCHG <38>

STD_ADP <38>
CAPS_LED# <35>
BAT_LED# <35>
ON/OFFBTN_LED# <35>

SYSON <27,35,36,40>

EC_RSMRST# <21>

EC_ON <36,39>

WL_BLUE_LED# <35>
SB_PWRGD <7,21,43>
BKOFF# <18>

TP_LED# <35>

VFIX_EN <43>
ENBKL <12>
EAPD_CODEC <29>

EC_THERM# <22>

SUSP# <27,29,36,38,41>

PWRBTN_OUT# <21>

PCI_SERR# <20>

12

C563100P_0402_50V8J

0.01U_0402_16V7K

1 2

CIR_IN

ECAGND

R341 10K_0402_5%

R344 10K_0402_5%

0619 change pin assignment

ACES_85201-04051

KBD CONN

ACES_85201-24051

12

VR_ON <43>

12

5
6

0605 Change pin assignment

GND1
GND2

CONN@

JP15

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

+5VL

KSI1

1

KSI7

2

KSI6

3

KSO9

4

KSI4

5

KSI5

6

KSO0

7

KSI2

8

KSI3

9

KSO5

10

KSO1

11

KSI0

12

KSO2

13

KSO4

14

KSO7

15

KSO8

16

KSO6

17

KSO3

18

KSO12

19

KSO13

20

KSO14

21

KSO11

22

KSO10

23

KSO15

24

25
26

0605 Change value to solve AC
plugged/unplugged power status
issue.

ACIN_D

KB Back Light Conn

R426

@

10_0805_5%~D

JP16

1

1

+BK_PWR

2

2

3

3

G1

4

4

G2

CONN@

For EMI

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

TP_BTN#

TP_CLK

TP_DATA

R345

1 2

D26

2 1

CH751H-40PT_SOD323-2

C586 100P_0402_50V8J

+5VS

12

12

R413

S

0_0805_5%

G

2

D

SI2301BDS-T1-E3_SOT23-3

1 3

30 mils

C556 100P_0402_25V8K@

1 2

C557 100P_0402_25V8K@

1 2

C558 100P_0402_25V8K@

1 2

C559 100P_0402_25V8K@

1 2

C560 100P_0402_25V8K@

1 2

C561 100P_0402_25V8K@

1 2

C562 100P_0402_25V8K@

1 2

C564 100P_0402_25V8K@

1 2

C565 100P_0402_25V8K@

1 2

C566 100P_0402_25V8K@

1 2

C567 100P_0402_25V8K@

1 2

C568 100P_0402_25V8K@

1 2

C569 100P_0402_25V8K@

1 2

C570 100P_0402_25V8K@

1 2

C571 100P_0402_25V8K@

1 2

C572 100P_0402_25V8K@

1 2

C575 100P_0402_25V8K@

1 2

C576 100P_0402_25V8K@

1 2

C577 100P_0402_25V8K@

1 2

C578 100P_0402_25V8K@

1 2

C579 100P_0402_25V8K@

1 2

C580 100P_0402_25V8K@

1 2

C581 100P_0402_25V8K@

1 2

C582 100P_0402_25V8K@

1 2

1 2

1 2

1 2

300K_0402_5%

12

12

R433
10K_0402_5%

Q24

R340

R342

R343

10K_0402_5%

10K_0402_5%

10K_0402_5%

+3VL

AC_IN <22,38>

EC_BEEP

12

0_0402_5%

R353

+3VS

+5V_TP

EC DEBUG port

R415

@

E51_TXD

1 2

0_0603_5%

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

EC KB926/KB conn

LA-4481P

34 46Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

B

C

D

E

TouchPAD ON/OFF

JP18

1

1

TP_LED#

2

2

TP_BTN#

3

5

3

G1

4

6

4

1 1

G2

ACES_85201-04051

CONN@

0.1U_0402_16V4Z

+5VS

1

C595

2

1

0.1U_0402_16V4Z
C606

2

TP_LED# <34>
TP_BTN# <34>

+5VALW +5V_TP

SYSON<27,34,36,40>

R352

10K_0402_5%@

R351 0_0603_5%

1 2

Q19 SI2301BDS-T1-E3_SOT23-3@

S

12

G

2

13

D

Q18

2

G

S

Max 0.5A

D

13

2N7002_SOT23-3@

0804 add Caps for ESD reserve

@

G1
G2

1

C591

2

1

1

2

2

3

3

4

4

100P_0402_50V8J

Max 0.5A

+5V_TP

TP_CLK
TP_DATA

M/B TO TP/B

0.1U_0402_16V4Z
JP20

5

2 2

6

ACES_85201-04051

CONN@

9/20
SP01000KC00/SP01E000900

HDD/G-Sensor LED

+5VS

12

R361

10K_0402_5%

3 3

SATA_LED#<22>

2N7002DW-7-F_SOT363-6

Q23A

61

2

Q23B

5

2N7002DW-7-F_SOT363-6

2N7002_SOT23-3

11/10 update

Battery Charge LED

BAT_LED#<34>

Num LOCK LED

4 4

NUM_LED#<34>

POWER LED

White LED: VF=3V, IF = 10mA, Res = 200 ohm
Amber LED: VF=1.8V, IF = 8mA, Res = 390 ohm

A

PSOT24C_SOT23-3

1

C592

@

2

+5VS

R359

200_0402_5%

3

WHITE

4

Q22

ON/OFFBTN_LED#

TP_DATA
TP_CLK

3

D27

TP_CLK <34>

TP_DATA <34>

1

C593

@

2

100P_0402_50V8J

+3VS

12

12

R360
390_0402_5%

21

43

13

D

S

@

2

1

YELLOW

1 2

0_0402_5%

2

G

WHITE

HT-F196BP5_WHITE

WHITE

HT-F196BP5_WHITE

WHITE

HT-F196BP5_WHITE

0804 Mout it for ESD

D28
HT-297UY5/BP5_YELLOW-WHITE

R363

D29

21

D30

21

D31

21

1 2

200_0402_5%

HDD_HALTLED# <22>

HDD_HALTLED <31>

+5VALW

R367

1 2

200_0402_5%

+5VS

R369

1 2

1.2K_0402_5%

+5VALW

R372

B

0804 Change value to adjust brightness

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Capacitor Sensor Conn

0605 Remove LDO

ENE

Cypress

0616 Reserve ENE Capboard EMI solution

SMB_EC_CK1<7,33,34,37>

ESB_CLK<34>
ESB_DAT<34>

I2C_INT<34>

LID_SW#<34>

SMB_EC_DA1<7,33,34,37>

0616 Reserve ENE Capboard EMI solution

SMB_EC_CK1
ESB_CLK
ESB_DAT

SMB_EC_DA1

ESB_DAT_R

ESB_CLK_R

C600 33P_0402_50V8J@

C598 33P_0402_50V8J

@

300 ohm bead+ 33PF

R355 0_0402_5%
R356 FBMA-11-100505-301T_0402
R357 FBMA-11-100505-301T_0402

R358 0_0402_5%

1 2

12

12

Capa-Lock Conn

1
2
3
4

+3VS

1
2
3
4

2N7002_SOT23-3

+5VS

CAPS_LED# <34>

R398

1 2

47K_0402_5%

13

D

Q43

S

Compal Secret Data

Deciphered Date

2 1

D32
CH751H-40PT_SOD323-2

2

G

12

R402
100K_0402_5%

BT_LED <32>

D

CONN@

JP49

5

G1

6

G2

ACES_85201-04051

WLAN and BT LED inform pin to KBC

WL_BLUE_LED#<34>

2007/08/02 2008/08/02

C

+5VS +3VL_CAP +3VL

21

PJP605
PAD-OPEN 2x2m

1 2
1 2
1 2

15P_0402_50V8J

+3VL_CAP+3VL

15P_0402_50V8J

1

C597

C594

2

0.1U_0402_16V4Z

@

C601

2

1

1

2

12

R354
0_0805_5%

ESB_CLK_R
ESB_DAT_R

1

C599

4.7U_0603_6.3V6K

2

0804 Mout it for ESD

ON/OFF Button Connector

+5VALW

ON/OFF#<34>

ON/OFFBTN_LED#<34>

WL/WW_LED#WL_BLUE_LED#

ON/OFF#
ON/OFFBTN_LED#

R399

12

10K_0402_5%@

1 2

R400 0_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet

CONN@

1

1

2

2

3

3

4

4

ACES_85201-04051

+3VS

Compal Electronics, Inc.

TP,MDC,ON/OFF,S/W,LED,Reed

LA-4481P

JP21

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_85201-1005N

CONN@

JP19

5

G1

6

G2

WL_LED# <27>

E

1

C596
10U_0805_10V4Z

2

@

35 46Monday, September 08, 2008

0.4

of

http://mycomp.su/x/

A

+5VALW TO +5VS

+5VALW

Q39

8

D

7

D

6

D

5

1

2

4.7U_0805_10V4Z

D

SI4800BDY_SO8

C610

1 1

S
S
S
G

C604

1
2
3
4

1U_0402_6.3V4Z

+5VS

4.7U_0805_10V4Z

1

C605

2

RUNON

1

2

+1.8V TO +1.8VS

+1.8V

Q41

IRF8113PBF_SO8

8
7

5

1

C618

2

2 2

4.7U_0805_10V4Z

C621

0.01U_0402_25V7K

Discharge circuit

3 3

SUSP SUSP

2N7002DW-7-F_SOT363-6

+1.8VS

1

4

1.8VS_ENABLE

1

2

470K_0402_5%

+5VS

2

C613

1
2

2

36

1U_0402_6.3V4Z

1 2

330K_0402_5%

3

Q34B

R381

1 2

2N7002DW-7-F_SOT363-6

4

5

0605 Add Resister to protect Q41

JBK00-->750K

R384
470_0805_5%

1 2
61

Q29A

2N7002DW-7-F_SOT363-6

R379

SUSP

2

C614
10U_0805_10V4Z

1

B+

2

+1.8VS

R385
470_0805_5%

1 2
61

Q30A

VLDT_EN#

2N7002DW-7-F_SOT363-6

B

+3VALW TO +3VS

+3VALW +3VS

1

S
S
S
G

1
2
3
4

1

2

0.01U_0402_25V7K

C602

2

1U_0402_6.3V4Z

RUNON

C609

3

4

8
7
6
5

SI4800BDY_SO8

1

C608

2

4.7U_0805_10V4Z

Q38

D
D
D
D

+1.2VALW TO +1.2V_HT

+1.2VALW +1.2V_HT

Q42

IRF8113PBF_SO8

8
7

5

1

C619

2

C620

4.7U_0805_10V4Z

0.01U_0402_25V7K

0605 Add Resister to protect Q42

JBK00-->10M

+1.2V_HT

R386
470_0805_5%

1 2
61

Q31A

2

2N7002DW-7-F_SOT363-6

C615

1
2
36

4
1

2

1 2

SUSP

1

C603 4.7U_0805_10V4Z

2

R376

12

330K_0402_5%

5

Q36B

2N7002DW-7-F_SOT363-6

1U_0402_6.3V4Z

R401

5

B+

SUSP

1

C616 4.7U_0805_10V4Z

2

R378

330K_0402_5%

61

2

2N7002DW-7-F_SOT363-6

Q36A

430K_0402_5%

+1.1VS

R383
470_0805_5%

1 2
3

Q31B

4

1

2

VLDT_EN#

C

12

B+

EC_ON<34,39>

SYSON#<42> SUSP <42>

D

EC_ON#

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2

EC_ON#

2

100K_0402_5%

SYSON#

Q33A

SYSON

+1.2VALW

1 2
61

+5VL

12

61

R388

2

R380
470_0805_5%

Q34A

R382
100K_0402_5%

Q35A

+5VL+5VL

12

61

VLDT_EN#

VLDT_EN<34>

2N7002DW-7-F_SOT363-6

12

R389
100K_0402_5%

SUSP

3

Q33B

5

2N7002DW-7-F_SOT363-6

4

VLDT_EN#

VLDT_EN

SUSP# <27,29,34,38,41>SYSON<27,34,35,40>

5

+5VL

12

R390
100K_0402_5%

3

Q35B

4

E

FM1

+3VS

R387
470_0805_5%

1 2
3

Q29B

SUSP

2N7002DW-7-F_SOT363-6

4 4

5

4

2N7002DW-7-F_SOT363-6

A

+1.5VS

R391
470_0805_5%

1 2
3

Q30B

SUSP SYSON#

5

4

2N7002DW-7-F_SOT363-6

+0.9V

R392
470_0805_5%

1 2
61

Q32A

2

2N7002DW-7-F_SOT363-6

B

SYSON#

+1.8V

R393
470_0805_5%

1 2
3

Q32B

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

H2
HOLEA

1

H7

HOLEA

1

H21
HOLEA

1

D

H3
HOLEA

H8

HOLEA

H15
HOLEA

H4
HOLEA

1

1

1

H17
HOLEA

1

1

H6

H5

HOLEA

HOLEA

1

1

H11

H10

HOLEA

HOLEA

1

1

H16
HOLEA

1

Title

Size Document Number Rev

Custom

Date: Sheet

H25

H18

HOLEA

HOLEA

1

1

Compal Electronics, Inc.

DC/DC Circuits

LA-4481P

H12
HOLEA

1

H14
HOLEA

1

H19
HOLEA

1

H13
HOLEA

1

H9

HOLEA

H20
HOLEA

E

1

HOLEA

1

FM2

1

1

FM4

FM3

1

1

FM5

FM6

1

1

H24

H23

H22

36 46Monday, September 08, 2008

HOLEA

HOLEA

1

1

1

0.4

of

http://mycomp.su/x/

A

BATT1

45@

CR2032 RTC BATTERY

B

C

D

E

1 1

TP0610K-T1-E3_SOT23-3

2 2

+3VALW

PQ3

PJP1

4

4

3

3

2

2

1

1

ACES_87343-047N-2

1 3

PR8
2K_0402_5%

<BOM Structure>
1 2

ADP_SIGNAL

+3VL

12

PR9
100K_0402_5%

2

ADPINADPIN

2

3

PD1

@PJSOT24C_SOT23-3

1

AC_LED# <34>

1 2

PR3
10K_0402_5%

12

100P_0402_50V8J

PC2

12

PR2
10K_0402_5%

12

PC3
1000P_0402_50V7K

12

HCB2012KF-121T50_0805

1 2

HCB2012KF-121T50_0805

1 2

12

PD4

RLZ3.6B TE-11 LL-34

PL1

PL2

PC4

100P_0402_50V8J

PC12
@1000P_0402_50V7K

VIN

12

12

PC5

1000P_0402_50V7K

ADP_ID <34>

PC7

2200P_0402_50V7K

BATT_A

12

+5VALW

PR1

340K_0402_1%

12

PR4

499K_0402_1%

12

12

PC6

0.01U_0402_25V7K

12

PR6

105K_0402_1%

12

PC1

0.01U_0402_25V7K

3
2

PU1A

LM358ADT_SO8

8

P

+

1

0

-

G

4

PR5

10K_0402_5%

12

BATT_OVP <34>

PH1 under CPU botten side :

PL3

VMB

PJP2

7

GND

8

GND

SUYIN_200275MR006G113ZL

3 3

BATT+

SMD
SMC

GND

1
2

3
4

B/I

5

TS

6

6.49K_0402_1%

1 2

12

PR17
1K_0402_5%

PR16

EC_SMD
EC_SMC

12

PR13

100_0402_5%

BAT_ID <38>

+3VL

PD2
PJSOT24C_SOT23-3

3
2

12

PR14
100_0402_5%

BATT_TEMP <34>

1

2

3

PD3

PJSOT24C_SOT23-3

1

SMB_EC_DA1

SMB_EC_CK1

HCB2012KF-121T50_0805

1 2

1 2

PL4
HCB2012KF-121T50_0805

12

PC8
1000P_0402_50V7K

SMB_EC_DA1 <7,33,34,35>

SMB_EC_CK1 <7,33,34,35>

BATT_A

12

PC9

0.01U_0402_50V4Z

PC10

0.22U_0603_10V7K

CPU

12

+5VS

12

PH1
10KB_0603_1%_TH11-3H103FT

+5VALW

12

PR12

2.21K_0402_1%

CPU thermal protection at 95 +-3 degree C

PR7

604K_0402_1%

1 2

PR10

200K_0402_1%

1 2
1 2

PR11

150K_0402_1%

150K_0402_1%

12

PR15

8

5

P

+

6

-

G

4

12

PC11
1000P_0402_50V7K

7

0

PU1B
LM358ADT_SO8

2

G

13

D

PQ2
SSM3K7002FU_SC70-3

S

EN0 <7,39>

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

DC Connector/CPU_OTP

LA-4481P

37 46Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

B

C

D

VIN

PQ101
SI4835BDY-T1-E3 1P SO8

8
7

5

1 1

DTA144EUA_SC70-3

PQ118

2

PR107
47K_0402_1%

1 2

2

G

2

13

D

S

PQ107
SSM3K7002FU_SC70-3

13

PQ105
DTC115EUA_SC70-3

1 3

1
2
36

4

12

12

PC101

47P_0402_50V8J

PR150

200K_0402_5%

12

PR151
150K_0402_5%

PACIN_1 <39>

2 2

ACOFF#

1 2

PD101

1 2

1SS355_SOD323-2

PR111

3K_0402_1%

PACIN

2

G

13

D

PQ109
SSM3K7002FU_SC70-3

S

Charge Detector

VIN

PD104
1SS355_SOD323-2

<BOM Structure>

1 2

3
2

12

8

+

-

4

PR123
1M_0402_5%

1 2

VIN_1

PR125

47_1206_5%

12

P

1

O

G

PU102A
LM393DG_SO8

PC125

0.1U_0603_25V7K

3 3

VIN

12

PR131
133K_0402_1%

12

PR135
10K_0603_0.1%

1.24VREF

4 4

A

PR101

47K_0402_5%

1 2

2

VCTRL<34>

P2

1 3

PQ104

DTA144EUA_SC70-3

PR129

12

PC106

0.47U_0603_16V7K

PR114
@0_0402_5%

1 2

PC117

1U_0603_10V6K

+3VL

12

PR128

10K_0402_1%

2

G

STD_ADP <34>

12

PR106

12

PR109
150K_0402_5%

PR113

143K_0402_1%

12

ADP_I<34>

+3VL

12

10K_0402_5%

CHGEN#

13

D

PQ112
SSM3K7002FU_SC70-3

S

FSTCHG<34>

PQ103

SI4835BDY-T1-E3 1P SO8

1
2
3 6

4

AC_SET<34>

@0.01U_0402_16V7K

200K_0402_5%

SUSP#<27,29,34,36,41>

1 2

PC112

1 2

1U_0603_6.3V6M

12

12

PR115
100K_0402_1%

39K_0402_5%

PC120

0.22U_0603_10V7K

FSTCHG#

1 2

PR137
20K_0402_1%

8
7

5

PR104
0_0402_5%

1 2

PC107

PR110

0_0402_5%

BQ24740VREF

+3VL

PR116

10K_0402_5%

1 2

12

ACSET

12

10

11

12

13

14

12

PR118

0.1U_0402_10V7K

+3VL

PR132

100K_0402_5%

2

G

ACDET

12

B

ACDET

ACSET

12

PR140

100K_0402_5%

7

LPREF

8

IADSLP

9

AGND

VREF

VDAC

VADJ

EXTPWR

ISYNSET

IADAPT

15

IADAPT

12

PC121

100P_0402_50V8J

PC123

PACIN_1

12

13

D

PQ113
SSM3K7002FU_SC70-3

S

PR138

100K_0402_1%

P4

0.012_2512_1%

4
3

1U_0603_6.3V6M

12

0.1U_0603_25V7K

4

5

6

LPMD

ACSET

ACDET

PU101
BQ24740RHDR_QFN28_5X5

BAT

SRSET

SRN

17

16

18

BATT

12

12

5

P

A2Y

G

74LVC1G17GW TSSOP

3

B+

PR102

PC102

1 2

PC108

3

ACP

SRP

19

PR120

133K_0402_1%

PR121
200K_0402_1%

1 2

1
2

12

PC109
@0.1U_0603_25V7K

CHGEN#

1

2

ACN

TP

CHGEN

PVCC

BTST

HIDRV

PH

REGN

LODRV

PGND

DPMDET

CELLS

21

20

SSM3K7002FU_SC70-3

12

HCB2012KF-121T50_0805

PL101

29

28

BST_CHG

27

DH_CHG

26

LX_CHG

25

REGNVADJ

24

DL_CHG

23

22

PQ111

IREF <34>

Add one shoot schmeatic.

1

PR148

10K_0402_5%

PU105

NC

4

1 2

PC132

0.047UF_0402_16V7

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

PC110
1U_0805_25V6K

1 2

0_0402_5%

1 2

PD102

1SS355_SOD323-2

12

PC119

1U_0603_10V6K

13

D

S

12

12

PR149

560K_0402_1%

12

PC103

4.7U_0805_25V6-K

PR108
10_1206_5%

1 2

PR141

12

PR117

100K_0402_5%

1 2

2

G

12

PD105

CHG_B+

12

PC104

4.7U_0805_25V6-K

PC111

0.1U_0402_10V7K

1 2

BQ24740VREF

12

PC124

+3VL+3VL

5

1

P

A2Y

G

74LVC1G17GW TSSOP

3

RLS4148_LL34-2

12

12

4.7U_0805_25V6-K

CHG_B+

12

4

PC128

220P_0402_50V7K

578

3 6

578

3 6

PACIN_2

C

PC129

1500P_0402_50V7K

PQ108
AO4466_SO8

241

PR139
@4.7_1206_5%

1 2
12

PQ110

241

FDS6690AS_SO8

BAT_ID <37>

12

PC122

@0.1U_0603_25V7K

1000P_0402_50V7K

Compal Secret Data

PL102
10U_LF919AS-100M-P3_4.5A_20%

1 2

PC131

@680P_0603_50V7K

PR126

100K_0402_1%

12

PC126

Deciphered Date

PC105

47K_0402_5%
PR119

0.1U_0603_25V7K

PU104

NC

2007/05/29 2008/05/29

1
2
3 6

ACOFF#

PQ106

DTC115EUA_SC70-3

12

12

PC113

4.7U_0805_25V6-K

VIN

12

PR130
10K_0402_1%

1 2

12

PR133
10K_0603_0.1%

22P_0402_50V8J

PQ102

FDS6675BZ 1P SO8

4

PR103

47K_0402_5%

1 2

12

PR105
10K_0402_5%

13

PR112

0.015_1206_1%

1 2

PC114

1 2

4.7U_0805_25V6-K
PC118

0.1U_0402_10V7K

12

PC127

8
7

5

VIN

2

ACOFF<34>

PR122
681K_0402_1%

1 2

5

+

6

-

APL1431LBBC-TR_SOT23-5

BATT

PQ114
FDS6675BZ 1P SO8

8
7

5

SSM3K7002FU_SC70-3

13

PACIN_2

PR144

0_0402_5%

1 2

BATT

12

12

PC115

4.7U_0805_25V6-K

4.7U_0805_25V6-K

STD_ADP

8

PU102B

P

7

O

G

LM393DG_SO8

4

RLZ4.3B_LL34

PR136

60.4K_0402_1%

1 2

4

REF

CATHODE

5

ANODE

Title

Size Document Number Rev

Date: Sheet

D

2

G

S

PQ120

13

D

2

G

S

PQ115

PC130

1 2

SSM3K7002FU_SC70-3

@0.068U_0402_16V7K

+3VL

PC116

PQ119

PD103

PU103

220K_0402_1%

S

G

2

PACIN

VIN

12

PR127
10K_0402_1%

12

VIN_1

3
2

NC

1

NC

PR147

D

13

SSM3K7002FU_SC70-3

PC133

12

1 2

12

47P_0402_50V8J

1 2

PR134
10K_0402_5%

Compal Electronics, Inc.

Charger

LA-4481P

D

4

470K_0402_5%

12

PR146

4.7K_0402_5%

SSM3K7002FU_SC70-3

13

D

S

PQ116

+3VL

5NC1

PU106

P

A2Y

G

74LVC1G14GW_SOT353-5

3

PR124
1K_0402_5%

1.24VREF

1
2
36

PR143

2

G

4

38 46Monday, September 08, 2008

BATT_A

12

12

PR142

13

D

2

G

S

AC_IN <22,34>

PACIN

of

0.4

470K_0402_5%

PQ117SSM3K7002FU_SC70-3

http://mycomp.su/x/

A

B

C

D

E

2VREF_51125

1 1

PC301

2200P_0402_50V7K

+3VALWP

B++

12

SSM3K7002FU_SC70-3

1 2

PR318
604K_0402_1%

0.047U_0603_16V7K

12

PC303

4.7U_0805_25V6-K

4.7UH_SIQB74B-4R7PF_4A_20%

1

PC309

+

2

150U_D_6.3VM

PQ305

SSM3K7002FU_SC70-3

PC318

PL302

12

D

S

PQ308

+3VLP

578

PQ301

AO4466_SO8

3 6

241

12

12

PR315

@4.7_1206_5%

12

ENTRIP1

13

2

G

13

D

2

G

S

PC314

@680P_0603_50V8J

2

G

PQ307

13

D

SSM3K7002FU_SC70-3

2

G

S

3 6

241

1 2

578

PQ303
AO4468_SO8

ENTRIP2

13

D

PQ306
SSM3K7002FU_SC70-3

S

PR313
100K_0402_5%

12

10U_0805_6.3V6M

UG1_3V

PR309

0_0402_5%

1 2

PR314
100K_0402_5%

PC306

VL

12

PR307

1 2

1 2

0_0402_5%

PC307

0.1U_0402_10V7K

LX_3V

LG_3V

B++

EN0<7,37>

EC_ON <34,36>

PR312

1M_0402_1%

1 2

191K_0402_1%

B+

2 2

3 3

PL301

HCB2012KF-121T50_0805

1 2

PACIN_1<38>

13.7K_0402_1%

20K_0402_1%

115K_0402_1%

BST_3V

UG_3V

PR311

+5VALWP

+3VALWP

0.22U_0603_10V7K

PR301

1 2

PR303

1 2

PR305

1 2

25

7
8

9
10
11
12

12

2VREF_51125

PC302

ENTRIP2

6

P PAD

ENTRIP2

VO2
VREG3
VBST2
DRVH2
LL2
DRVL2

EN0

13

PJP302

1 2

PAD-OPEN 4x4m
PJP303

1 2

PAD-OPEN 4x4m

12

PR302

30.9K_0402_1%

1 2

PR304
20K_0402_1%

1 2

PR306
115K_0402_1%

ENTRIP1

1 2

3

4

1

2

5

VFB1

VFB2

VREF

TONSEL

ENTRIP1

24

VO1

23

PGOOD

VBST1

DRVH1

DRVL1

VREG5

GND

VIN

SKIPSEL

14

VCLK

PU301

17

15

16

18

TPS51125RGER_QFN24_4X4

BST_5V

22

UG_5V

21

LX_5V

20

LL1

LG_5V

19

VL

12

PC311
10U_0805_10V6K

12

B++

PC312

0.1U_0603_25V7K

(4.5A,180mils ,Via NO.= 9)

+5VALW

(3A,120mils ,Via NO.= 6)

+3VALW

PR308

2.2_0402_5%

1 2

+3VL

12

B++

PC308

0.1U_0402_10V7K

1 2

PR317
100K_0402_5%

12

12

PC304

2200P_0402_50V7K

PR310
0_0402_5%

1 2

3/5V_OK <21,41>

12

PC305

PC313

4.7U_0805_25V6-K

4.7U_0805_25V6-K

PQ304

FDS6690AS_NL_SO8

578

3 6

578

3 6

+3VLP

VL

241

241

PQ302

AO4466_SO8

PL303

4.7UH_PCMC063T-4R7MN_5.5A_20%

1 2

12

PR316

@4.7_1206_5%

12

PC315

@680P_0603_50V8J

PJP301

2 1

PAD-OPEN 2x2m

PJP304

2 1

PAD-OPEN 2x2m

+3VL

+5VL

1

+

PC310
150U_D_6.3VM

2

+5VALWP

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

3.3VALWP/5VALWP

LA-4481P

39 46Monday, September 08, 2008

E

0.4

of

http://mycomp.su/x/

A

1 1

PR401

0_0402_5%

SYSON<27,34,35,36>

2 2

3 3

1 2

@1000P_0402_50V7K

PC401

+1.8VP

12

PR405

0_0402_5%

PR403

316_0402_1%

12

+5VALW

+5VALW

12

12

PC409
1U_0603_10V6K

+1.8VP

1 2

14.3K_0603_0.1%

1 2

PC413
@10P_0402_50V8J

10K_0603_0.1%

PR408

PR404
255K_0402_1%

1 2

12

PR409

PU401

2
3
4
5
6

TON
VOUT
V5FILT
VFB
PGOOD

B

1

14

15

TP

EN_PSV

GND7PGND

TPS51117RGYR_QFN14_3.5x3.5

8

VBST

DRVH

TRIP

V5DRV

DRVL

1 2

PR402

0_0402_5%

13
12

LL

11
10
9

DH_1.8V
LX_1.8V

+5VALW+5VALW

DL_1.8V

BST1_1.8VBST_1.8V

0.1U_0402_10V7K

PR410

1 2

0_0402_5%

12

PC415

4.7U_0805_10V6K

1 2

PC402

1 2

PR406

10.7K_0402_1%

DH_1.8V_1

578

3 6

241

578

3 6

241

C

PQ401
AO4466_SO8

PR407

PQ402
FDS6690AS_NL_SO8

1.8V_B+

12

PC403

4.7U_0805_25V6-K

2.2UH_PCMC063T-2R2MN_8A_20%

12

@4.7_1206_5%

12

PC412

HCB1608KF-121T30_0603

12

12

PC404

4.7U_0805_25V6-K

2200P_0402_50V7K

PL402

1 2

@680P_0603_50V8J

1 2

PC405

PL401

D

B+

+1.8VP

1

+

PC408

2

220U_D2_4VY_R25M

PJP401

+1.8VP

4 4

1 2

PAD-OPEN 4x4m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

(7A,280mils ,Via NO.= 14)

+1.8V

2007/05/29 2008/05/29

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

1.8VP

LA-4481P

D

40 46Monday, September 08, 2008

of

0.4

http://mycomp.su/x/

A

1 1

B+++

12

12

12

PC502

PC501

PC517

4.7U_0805_25V6-K

4.7U_0805_25V6-K

2200P_0402_50V7K

+1.1VS

+1.1VSP

B+++

B

PR518
0_0402_5%

1 2

1 2

PR517
10_0402_5%

+1.1VSP

PR501

11.5K_0402_1%

1 2

PR502

24.9K_0402_1%

1 2

PR505

0_0402_5%

C

PR503

18.7K_0402_1%

1 2

PR504

11.5K_0402_1%

12

+1.2VALWP

12

D

B+++

HCB2012KF-121T50_0805

PL502

B+

12

E

VCCP_POK

3

4

15

TONSEL

V5FILT

GND

V5IN

16

12

2

17

12

PC515

4.7U_0805_10V6K

1

VO1

VFB1

24

PGOOD1

23

EN1

BST_1.2V

22

VBST1

UG_1.2V

21

DR VH1

20

LL1

LG_1.2V

19

DR VL1

TRIP1

PGND1

TPS51124RGER_QFN24_4x4

18

PR510

10.5K_0402_1%

+5VALW

LX_1.2V

PR512

33K_0402_5%

1 2

12

PC512

0.1U_0402_16V7K

PR507

0_0402_5%

PR509

0_0402_5%

12

12

PC507

0.1U_0402_10V7K

1 2

UG1_1.2V

3/5V_OK <21,39>

PQ502

AO4466_SO8

PQ504

AO4468_SO8

578

3 6

241

3.3UH 30% MSCDRI-7030AB-3R3N 4.1A

578

3 6

241

12

PC504

4.7U_0805_25V6-K

PL503

1 2

PC505

12

2200P_0402_50V7K

PR515

1K_0402_5%

+1.2VALWP

+1.2VALWP

12

PC510

4.7U_0805_6.3V6K

1

+

1 2

2

PC511

220U_B_2.5VM_R35M

2 2

PQ501

AO4466_SO8

+1.1VSP

PL501

+1.1VSP

1

+

2

PC508

220U_D2_4VY_R25M

3 3

2.2UH_PCMC063T-2R2MN_8A_20%

12

PC509

4.7U_0805_6.3V6K

12

578

3 6

241

578

3 6

241

SUSP#<27,29,34,36,38>

@0.022U_0603_25V7K

PC506

0.1U_0402_10V7K

UG1_1.1V

PQ503
FDS6690AS_NL_SO8

0_0402_5%

@0.1U_0402_10V7K

12

PR513

PR506
0_0402_5%

12

PC513

PC503

PR5080_0402_5%

12

BST_1.1V

12

UG_1.1V

12

LX_1.1V

LG_1.1V

12

PC514

1U_0603_10V6K

PU501

25

P PAD

7

PGOOD2

8

EN2

9

VBST2

10

DR VH2

11

LL2

12

DR VL2

PR511

15.4K_0402_1%

1 2

1 2

12

6

5

VO2

VFB2

TRIP2

PGND2

14

13

PR514

3.3_0402_5%

(6A,240mils ,Via NO.=12)

PJP501

+1.1VSP

4 4

A

+1.1VSP

1 2

PAD-OPEN 4x4m
PJP503

1 2

PAD-OPEN 4x4m

+1.1VS

+1.1VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

(4A,160mils ,Via NO.=8)

+1.2VALWP

1 2

D

PJP502

PAD-OPEN 4x4m

+1.2VALW

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

1.1VSP/1.2VALWP

LA-4481P

41 46Monday, September 08, 2008

E

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0.4

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A

1 1

B

C

D

E

+1.8V

PU601

VIN1VCNTL

12

PC601

10U_0805_10V4Z

SYSON#<36>

2 2

SUSP<36>

3 3

1 2

PR602

0_0402_5%

SSM3K7002FU_SC70-3

1 2

PR604

@0_0402_5%

+1.5VSP

PQ601

2

G

12

PC606
@0.1U_0402_16V7K

+0.9VP

12

1K_0402_1%

12

PR603

13

D

1K_0402_1%

S

PJP601

1 2

PAD-OPEN 3x3m

PJP603

1 2

PAD-OPEN 3x3m

PR601

2

GND

3

VREF

4

VOUT

G2992F1U_SO8

12

12

PC605
10U_0805_6.3V6M

0.1U_0402_16V7K

PC604

(2A,80mils ,Via NO.= 4)

+0.9V

(1A,40mils ,Via NO.= 2)

+1.5VS

+0.9VP

6
5

NC

7

NC

8

NC

9

TP

+5VALW

12

PC603
1U_0603_16V6K

10U_0805_10V4Z

SUSP<36>

+3VS

+1.8V

PC613

SSM3K7002FU_SC70-3

1 2

PR608

0_0402_5%

12

PC607

1U_0603_6.3V6M

12

PQ602

13

D

2

G

S

12

PC610
@0.1U_0402_16V7K

(500mA,40mils ,Via NO.= 1)

PU602
APL5508-25DC-TRL_SOT89-3

2

IN

OUT

GND

1

12

PR606
1K_0402_1%

VREF1.5V

12

PR607

5.1K_0402_1%

3

PU603

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2992F1U_SO8

6
5

NC

7

NC

8

NC

9

TP

12

PC612
1U_0603_16V6K

+5VALW

+1.5VSP

12

12

PC614
10U_0805_6.3V6M

0.1U_0402_16V7K

PC611

+2.5VSP

12

12

PR605
@150_1206_5%

PC608

4.7U_0805_6.3V6K

PJP602

+2.5VSP

4 4

A

1 2

PAD-OPEN 3x3m

(500mA,40mils ,Via NO.= 1)

+2.5VS

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

0.9VSP/2.5VSP/1.5VSP

LA-4481P

42 46Monday, September 08, 2008

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A

+CPU_CORE_NB

VDD_NB_FB_H<7>

VDD_NB_FB_L<7>

1 1

PR204

ISL6265_PWROK

13

D

VFIX_EN<34>

2

G

S

Connect to EC pin 110.

2 2

VGATE<34>
H_PWRGD<20>
SB_PWRGD<7,21,34>

CPU_SVD<7>

CPU_SVC<7>

VR_ON<34>

PR225

1 2

3 3

4 4

255_0402_1%

PR230

1 2

54.9K_0402_1%

CPU_VDD0_FB_H<7>

CPU_VDD0_FB_L<7>

CPU_VDD1_FB_L<7>

CPU_VDD1_FB_H<7>

PC223

1 2

4700P_0402_25V7K

PR227

1 2

1K_0402_1%

PC225

1 2

1200P_0402_50V7K

1 2

PC227
180P_0402_50V8J

A

22K_0402_1%

1 2

1000P_0402_50V7K

PQ209
SSM3K7002FU_SC70-3

+5VS

+3VS

12

PR216

10K_0402_1%

PR246 100K_0402_5%
PR234 @100K_0402_5%

PR218

1 2

PR222

1 2

PR223

1 2

34.8K_0402_1%

1 2

PC205

CPU_B+

1 2
1 2

0_0402_5%

0_0402_5%

PR232

1 2

6.81K_0402_1%

1 2

PC228
1000P_0402_50V7K

+5VS

PR208

2_0402_5%

1 2

0.1U_0603_25V7K

1 2

PR212

0_0402_5%

1 2

PR213

@0_0402_5%

1 2

PR215

@10K_0402_5%

ISL6265_PWROK

ISL6265_PWROK

PR224

1 2

82.5K_0402_1%

1 2

PR235
0_0402_5%

1 2

PR237
0_0402_5%

1 2

PR239
0_0402_5%

1 2

PR241
0_0402_5%

0.1U_0402_16V7K

PC216

SVD
SVC

PR205

2_0402_5%

1 2

PC207

12

PU201

1

OFS/VFIXEN

2

PGOOD

3

PWROK

4

SVD

5

SVC

6

ENABLE

7

RBIAS

8

OCSET

9

VDIFF0

10

FB0

11

COMP0

12

VW0

PC241
1000P_0402_50V7K

12

PC242
1000P_0402_50V7K

12

12

48

47

VIN

ISP0

14

13

ISP 0

+CPU_CORE_0

B

12

PR206

0_0402_5%

12

12

PC208

PC209

1200P_0402_50V7K

33P_0402_50V8K

12

PR210

1 2

44.2K_0402_1%

44

45

46

VCC

FB_NB

FSET_NB

COMP_NB

ISL6265IRZ-T_QFN48_6X6

RTN1

VSEN0

RTN0

ISN0

17

15

16

RTN1

VSEN0

RTN0

12

PC244

@1000P_0402_50V7K

12

PC245

@1000P_0402_50V7K

12

@1000P_0402_50V7K

B

PC243

VSEN_NB

43

VSEN_NB

VSEN1

18

VSEN1

PC246

12

@1000P_0402_50V7K

12

PR209

1000P_0402_50V7K

RTN_NB

42

RTN_NB

VDIFF1

19

PC247

12

0_0402_5%

12

PR207

40

41

PGND_NB

OCSET_NB

COMP121ISP1

FB1

20

PL201

4.7UH 30% MSCDRI-7030AB-4R7N 3.3A

1

+

2

PC202

PC201

10U_0805_6.3V6M

220U_B_2.5VM_R35M

0.1U_0402_16V7K

UGATE NB

37

BOOT_NB

PHASE_NB

UGATE_NB

BOOT0

UGATE0

PHASE0

PGND0

LGATE0

LGATE1

PGND1

PHASE1

UGATE1

BOOT1

ISN1

24

+CPU_CORE_1

PC206

PR211

1_0603_5%

PVCC

TP

49

14K_0402_1%

LGATE NB

39

LGATE_NB

VW1

22

PHASE NB

38

23

C

12

PQ201

AO4468_SO8

1
2
3 6

12

BOOT_NB1

12

2.2_0603_5%

1 2

PR228

12

12

PR214

1 2

1 2

0_0603_5%

PR219

PR226

1 2

0_0603_5%

1 2

PC224

0.22U_0603_10V7K

PC232

1200P_0402_50V7K

4700P_0402_25V7K

BOOT_NB

36
35

UGATE0

34

PHASE0

33
32

LGATE0

31
30

LGATE1

29
28

PHASE1

27

UGATE1

26

BOOT1

25

ISP 1

1000P_0402_50V7K

6.81K_0402_1%

BOOT0

2.2_0603_5%

PC230

PR236

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

8
7

5

4

0_0402_5%

12

PC210

2.2U_0603_6.3V6K

PQ204

PQ207

AO4714 1N SO8

PC231

12

PR238

54.9K_0402_1%

12

PR240

1K_0402_1%

PR243

255_0402_1%

12

PHASE NB

UGATE0_1

578

UGATE1_1

578

12

LGATE NB

+5VS

0.22U_0603_10V7K
PC217

1 2

AO4714 1N SO8

180P_0402_50V8J

PC233

2007/08/02 2008/08/02

PQ202

AO4466_SO8

1
2
3 6

4

PR203

1 2

UGATE NB

578

PQ203

AO4474_SO8

3 6

578

3 6

241

3 6

241

12

12

3 6

578

578

Compal Secret Data

Deciphered Date

8
7

5

241

AO4714 1N SO8

241

3 6

241

3 6

241

12

PC239

PC234

220P_0402_50V7K

PR220

PQ205

PQ206
AO4474_SO8

PQ208

AO4714 1N SO8

D

12

PC203

2200P_0402_50V7K

12

PC235

4.7U_0805_25V6-K

4.7U_0805_25V6-K

12

12

@4.7_1206_5%

PC218

12

PC240

220P_0402_50V7K

12

PR229

12

@4.7_1206_5%

PC226
@680P_0603_50V8J

D

12

@680P_0603_50V8J

PC204

12

4.7U_0805_25V6-K

CPU_B+

12

12

PC212

4.7U_0805_25V6-K

0.36UH_PCMC104T-R36MN1R17_30A_20%

0.1U_0603_25V7K

12

PC237

4.7U_0805_25V6-K

0.1U_0603_25V7K

12

PC213

PC214

4.7U_0805_25V6-K

2200P_0402_50V7K

12

PL203

PR221

PR217

4.02k_0603_1%

16.5K_0402_1%

1 2

PC219

PC236

1 2

ISP 0

12

12

PC220

4.7U_0805_25V6-K

4.7U_0805_25V6-K

12

PR231

16.5K_0402_1%

4.02k_0603_1%

1 2

PC229

ISP 1

Title

Size Document Number Rev

Custom

Date: Sheet

E

CPU_B+

PL202

SMB3025500YA_2P

12

12

PC255

PC254

390P_0402_50V7K

1500P_0402_50V7K

12

12

12

PC221

PC222

2200P_0402_50V7K

4.7U_0805_25V6-K

12

PL204

0.36UH_PCMC104T-R36MN1R17_30A_20%

PR233

1 2

12

PC215

1000P_0402_50V7K

12

PC257

PC256

1500P_0402_50V7K

Compal Electronics, Inc.

CPU_CORE

LA-4481P

E

12

PC211

+CPU_CORE_0

CPU_B+

12

390P_0402_50V7K

+CPU_CORE_1

B+

1

1

+

+

PC238

2

2

100U_25V_M

@47U_25V_M

43 46Monday, September 08, 2008

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A

B

Version Change List ( P. I. R. List ) for Power Circuit

C

D

E

Page#

137

1 1

2
3
4
5
6
7

2 2

38
39
40
41
42

38
837
9 38

10 39
11 38

Title

DC Connector
/CPU_OTP

Charger

3.3VALWP/5VALWP

1.8VP

1.1VSP/1.2VALWP

CPU_CORE

Charger

DC Connector
/CPU_OTP

Charger

3.3VALWP/5VALWP

Charger PWR PWR request Add 4 cell one shoot schematic, add net name PACIN_2

Date

2008/05/21

2008/05/21

2008/05/21

2008/05/21

2008/05/21

2008/05/21

2008/06/04

2008/06/12

2008/06/18

2008/07/21

2008/07/28

Owner

PWR

PWR

PWR

PWR

PWR

PWR

PWR HP request Add 4 cell schematic, add net name BATT_A.

PWR

PWR PWR request

PWR request, solve inrush current.

PWR request, modify OCP

For PWR request, prevent leakage
power and modify OCP.

PWR request

Thermal request, prevent PH1
will OTP on TPDL.

PWR requestPWR Add PR311 191K_0402_1%, PR312 1M_0402_1%.

PR8 change the value from 100 to 2K.HW request 0.2

Modify PR102 footprint and PQ101,PQ103 change from AM4835 to SI4835BDY,
PQ103 change from AM4835 to FDS6675BZ, PC106 change from 0.22u to 0.47u,

PR305 change the value from 140K to 95.3K, PR306 change the value
from 133K to 105K, PC318 change the value from 0.022u to 0.047u.

PR406 change the value from 15.4K to 10.7K.PWR request, modify OCP.

Add PR515 1k_0402_5%, PR511 change the value from 18.2K to 15.4K,
PR510 change the value from 17.8K to 10.5K.

Modify PC206 change the footprint from 0603 to 0402,
PR207 change the value from 15.4K to 14K.

PR12 change the value from 2.55K to 2.21K.

Add PC133 220P_0402, PR147 change the value
from 100K_0402_5% to 470K_0402_1%.

Solution Description

Rev.Issue DescriptionItem

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.3

Request

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Power Changed-List History-1

LA-4481P

44 46Monday, September 08, 2008

E

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5

w

Fix Audio MIC no function and follow Ripley schematics

<2008.05.09>

D D

<2008.06.05>

C C

<2008.06.16>
<2008.06.19>

<2008.07.30>

<2008.08.01>
<2008.08.04>

B B

<2008.09.04>

A A

1

Fix ENE cap-board could not detect

2

Fix BT no function and follow Ripley schematics

3

change power rail to solve +3vs leakage

1

Remove 0 ohm resisters at LDT_STOP# & CPU_LDT_REQ#

2

Remove 0 ohm resisters at NB_PWRGD Remove R164 (0 ohm)

3

Change value to solve AC plugged/unplugged power status issue.

4

add 150uF Cap to solve hot-plug for Multi-bay ODD

5

Remove HP switch Transisters and change Cap size to solve DFB issue.

6

Remove LPC debug connector

7

Remove 0 ohm resisters at SPI ROM

8

add GND shaping at E-SATA Add E-SATA GND shaping32

9

Change Keyboard pin assignment to follow Ripley design

10

Change value to solve AC plugged/unplugged power status issue.

11

Add Keyboard backlight control circuit

12

Remove Cap-sensor baord power LDO

13

Add Resister to protect Q42, Q41

14

1

Solve LED panel flash issue when AC IN

1

change KB backlight connector pin assignment

2

Fix external and internal MIC auto switch issue

1

change FPR connector to fix Assy DFB issue.

2

Vari-Bright design change for EC & RS780 common use 18, 12 Add D38, D39, R76 0.3

1

Reserve Caps to protect ESD 35 Add C595, C606 0.3

1

Change R value for LED brightness

2

Fix OTS#0392705 (WLAN Slot Pin 24 is tied to different power than pins 2, 52, 39 and 41)

3

Reserve ESD diode to protect SPK

4

Fix FPR ESD issue

5

Reserve Cap to protect T/P ON/OFF

6

0804 Change value to adjust LED brightness

7

Install Cap to fix ESD issue 35 Install C597

8

Remove Varibright function 12, 18 Uninstall D39, Delete D38

1

2

Follow Vendor suggestion to change CR_LED# Change power rail from+5VS to +3vs28

3

Reserve R for protect LED panel flash control Add R41018

4

5

6

4

3

PAGE Modify ListFixed Issue and change itemItem

Add R429, R430, R431, C642

34 0.2

Remove R410 & R411 & C627

32 change BT pin assignment

LDT_RST# & H_PWRGD_CPU & LDT_STOP# & CPU_LDT_REQ# change

07

power rail to +1.8VS

12

Remove R54 & R55 (0 ohm)

21

22

Change R408 to 300k ohm

25 Add C643 150uF

30

33

33

Change C523 & C524 size and remove Q16, Q17, Q24...

Remove JP14

Remove R320~323 (0 ohm)

2

1

M.B. Ver.

0.230

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

34

34

34

change pin assignment (follow Ripley)

change R345 to 300Kohm

add Q24, R426

remove U29....35

Add R381 & R40136

35 Add C600, C601 and Change R356, R357 size to 300ohm beadAdd and reserve EMI soulution for ENE cap-board

0.2

0.2

0.2

0.2

0.2

0.2

18 Add Q4 and R54 0.2

34 pin1 & 2 (Power), pin3 & 4 (GND) swapped

0.2

29 add R301 and pull up +VDDA_CODEC_R 0.3

32 change pin count from 6 pins to 4 pins 0.3

28 Change R276 value to 1.2Kohm

27 Unmount R245 and install R244

30 Add D55, D56

32 Install D25

35 Add C595, C606

35 Change R369 value to 1.2kohm

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.4

Change D16 footprint28Fix SMT DFX issue

0.4

0.4

0.4

0.4

0.4

pin1 & 2 (Po

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/13 2006/03/10

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

HW PIR(1)

LA-4481P

1

45 46Monday, September 08, 2008

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A

Calypso power sequence

1 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/28 2006/03/10

A

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-4481P

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