COMPAL LA-4471P Schematics

5

D D

4

3

2

1

C C

Compal confidential

KSRAA LA-4471P Schematics Document

Mobile Penryn uFCPGA with
Cantiga + ICH9M core logic

B B

2008-06-12

REV:1.0

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/02/20 2008/10/25

2008/02/20 2008/10/25

2008/02/20 2008/10/25

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

401596

401596

401596

1

147Thursday, June 12, 2008

147Thursday, June 12, 2008

147Thursday, June 12, 2008

B

B

B

of

of

of

5

Compal confidential

Model : KSRAA
File Name : LA-4471P

Montevina Platform

D D

Display port

page 19

HDMI Conn.

page 19

4

3

2

1

KSRAA Sub-board

VGA/B
LS-4471P NB9E-GTX
LS-4302P NB9E-GS

Mobile Penryn

uFCPGA-478 CPU

page 4,5,6

Thermal Sensor
SMSC EMC1402

page 4

Fan Control

page 4

Power/B
1 Button+2LED
LS-4305P

KS/B
KS+CIR+LogoLED

1:2 Switch

SN75DP122

page 19

Small Board

LVDS
Conn

C C

nVIDIA NB9E-GTX
NB9E-GS

with 1G/512MB
GDDR3 VRAM

PCI-E BUS

PCI-E Port 6

Card Reader Controller

JMB380

Port 3

page 27

Mini-Card

TMA

PCI-E Port 5

page 25

Mini-Card

WLAN

PCI-E Port 4
USB Port 7

CRT Conn

VGA/B Conn.

page 17

page 25

page 18

PCI-Express x 16

New Card socket

5GHz

Mini-Card

ROBSON

USB Port 2

page 25

page 26

PCI-E Port 1

Mini-Card

WiMedia UWB

USB Port 6

page 25

USB port 8

USB BUS

H_A#(3..35)
H_D#(0..63)

Intel Cantiga

uFCBGA-1329

page 7,8,9,10,11,12,13

Intel ICH9-M

BGA-676

PCI-E BUS

1394 port

page 27

B B

5in1 Slot

page 27

PCI-E Port 3

1000 LAN -LOM

RTL8111C

page 28

RJ45/11 CONN

page 28

SM BUS

FM Tuner

page 33

ENE KB926

A A

Cap senser
Conn

page 34

Touch Pad
Conn

Int.KBD

page 32page 34

FSB

800/1066MHz

DMI

C-Link

page 20,21,22,23

LPC BUS

3.3V 33 MHz

page 32

SPI BIOS

page 31

CIR

USB
Azalia

SATA

on KS/B

DDR3 1333MHz

Dual Channel

Int. Camera
USB x 1

page 33

USB port 11

3GHz

SATA 0

SATA 1

SATA 2

SATA 3

USB x 3
conn

3.3V 480MHz

3.3V 24.576MHz/48Mhz

USB port 4

Tweeter/HP Amplifier
& Int-Mic

SATA HDD Connector

SATA HDD Connector

SATA ODD Connector

eSATA Re-driver IC
EQS3201

DDR3-SO-DIMM X2

BANK 0, 1, 2, 3

USB2.0

page 26

USB port 0-3

Bluetooth Conn

USB2.0
Finger Printer

MDC V1.5

HD Audio Codec

ALC268+272

page 34

page 31

page 29

page 24

page 24

page 24

page 21

page 14,15

page 33

USB port 5

Tweeter Range
Amplifier

APA2068

page 30

Medium Range
Amplifier

APA2068

page 30

Subwoofer Amplifier

APA3011

page 30

USB/B conn
with eSATA

page 24

USB port 3

Tweeter

Midrange

Subwoofer

Audio Jack

MIC/Line-in

S/DIF Jack

HP//Line-out/S-DIF

on Audio/B

on Audio/B

LS-4306P
FP/B

LS-4307P

LED/B
8 LED+Lid
LS-430BP

Cap Sense/B
9 BOT+LED
LS-430CP

Audio/B
MIC+S/DIF+VR
LS-430DP

TP_LED/B
5 LED for TP COVER
LS-430EP

FM Tuner/B
FM Tuner+wirless con
LS-430EP

RTC BAT.

page 38

Power On/Off CKT.

DC/DC Interface CKT.

Charger

Power Circuit DC/DC

page 35

page 37,38

Page 40

Page 38~45

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/02/20 2008/10/25

2008/02/20 2008/10/25

2008/02/20 2008/10/25

Compal Secret Data

Compal Secret Data

Compal Secret Data

2

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

401596

401596

401596

1

of

247Saturday, May 17, 2008

of

247Saturday, May 17, 2008

of

247Saturday, May 17, 2008

B

B

B

A

Voltage Rails

B

C

D

E

Power Plane

VIN

1 1

B+
+CPU_CORE
+0.75VS
+1.05VS
+1.5VS
+1.5V

+3VALW
+3VL
+3V_SB
+3V_LAN
+3V_WLAN
+3VS
+5VALW
+5VL
+5V_SB

2 2

+5VS
+VSB
+RTCVCC

Description

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU

0.9V switched power rail for DDR terminator

1.05V switched power rail

1.5V switched power rail

1.5V power rail for DDR

3.3V always on power rail

3.3V always on power rail

3.3V power rail for LAN

3.3V power rail for LAN

3.3V power rail for LAN

3.3V switched power rail
5V always on power rail
5V always on power rail
5V power rail for SB
5V switched power rail
VSB always on power rail
RTC power

S1 S3 S5

ON ON ON

OFF

ON ON ON ON

OFF

OFF

ON
ON

OFF
OFF OFF

ON

OFF OFF

ON
ON

ON

ON

ON ON

ONON
ON ON
ON ON
ON ON

OFF

ON
ON

ON ON
ON ON
ON ON

OFF

ON

ON ON

ON
ON

OFF
OFF

OFF

OFF
OFF
OFF

OFF

OFF

ON ON

OFF

OFF

OFF

OFF

OFF

OFF
OFF

OFF

OFF
ON ON
OFF OFF

OFF

OFF

OFF

ON

ONON

G3

SIGNAL

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SLP_S1# SLP_S3#

SLP_S4# SLP_S5#

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

HIGH

LOWLOWLOW

LOW LOW LOW LOW

HIGHHIGHHIGH

HIGH

HIGH

G3 LOWLOWLOWLOW

External PCI Devices

Device

EC SM Bus1 address

Device

EC KB926 C0

+5VL

3 3

+5VL
+5VL

+3VS

Smart Battery+5VL
HDMI-CEC
FUN/B (CAP Sensor)
TMA THM Sen

ADI ADM1032

IDSEL#

REQ#/GNT#

Interrupts

EC SM Bus2 address

PowerPower

Address Address

0001 011X b
0011 010x b

1001 100x b

+3VS

+3VS

+3VS

+3VS

Device

EC KB926 C0
CPU THM Sen .SMSC

EMC1402-1-ACZL-TR
CPU THM Sen .SMSC

EMC1402-2-ACZL-TR
VGA THM Sen. ADI

ADM1032

1001 100x b

1001 101x b

1001 100x b

ICH9M SM Bus address

Device

Power

ICH9M

+3V_SB

Clock Generator

+3VS

(SLG8SP556V)
DDR DIMM0

+3VS

DDR DIMM1

+3VS

Express

+3VS

FM Module

+3VS

Vertial I2C

Address

1101 001Xb

1001 000Xb
1001 010Xb

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/02/20 2009/2/1

2008/02/20 2009/2/1

2008/02/20 2009/2/1

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

401596

401596

401596

347Monday, June 30, 2008

347Monday, June 30, 2008

347Monday, June 30, 2008

E

B

B

B

of

of

of

5

+5VS

FAN1 Conn

12

DC1

DC1
1SS355_SOD323-2

1SS355_SOD323-2

+3VS

12

RC4

RC4
10K_0402_5%

D D

FAN_SPEED1<32>

10K_0402_5%

12

DC2

DC2
BAS16_SOT23-3

BAS16_SOT23-3

Update Footprint

20080305 change to G990

+5VS

+VCC_FAN1

EN_DFAN1<32>

C C

FAN_SPEED2<32>

EN_DFAN1

+3VS

12

RC17

RC17
10K_0402_5%

10K_0402_5%

+5VS

12

DC3

DC3
1SS355_SOD323-2

1SS355_SOD323-2

12

DC4

DC4
BAS16_SOT23-3

BAS16_SOT23-3

Update Footprint

20080305 change to G990

+5VS

+VCC_FAN2

EN_DFAN2<32>

B B

EN_DFAN2

RC32

RC32

1 2

49.9K_0402_1%

49.9K_0402_1%

1U_0402_6.3V4Z

1U_0402_6.3V4Z

CC68

CC68

W=40mils

+VCC_FAN1

CC1 10U_0805_10V4ZCC1 10U_0805_10V4Z

CC2 1000P_0402_50V7KCC2 1000P_0402_50V7K

1

CC3

CC3
1000P_0402_50V7K

1000P_0402_50V7K

2

UC1

UC1
1
2
3
4

1

G990P11U_SO8

G990P11U_SO8

CC4

CC4
10U_0805_10V4Z

10U_0805_10V4Z

2

FAN2 Conn

W=40mils

+VCC_FAN2

CC5 10U_0805_10V4ZCC5 10U_0805_10V4Z

CC6 1000P_0402_50V7KCC6 1000P_0402_50V7K

1

CC7

CC7
1000P_0402_50V7K

1000P_0402_50V7K

2

UC2

UC2
1
2
3
4

1

1

2

CC8

CC8
10U_0805_10V4Z

10U_0805_10V4Z

2

G990P11U_SO8

G990P11U_SO8

VEN
VIN
VO
VSET

VEN
VIN
VO
VSET

1 2

1 2

1 2

1 2

JFAN1

JFAN1

1

1

2

2

3

3

4

GND

5

GND

ACES_85205-03001@

ACES_85205-03001@

8

GND

7

GND

6

GND

5

GND

JFAN2

JFAN2

1

1

2

2

3

3

4

GND

5

GND

ACES_85205-03001@

ACES_85205-03001@

8

GND

7

GND

6

GND

5

GND

Place Caps Close to CPU Socket

CC10 180P_0402_50V8J@CC10 180P_0402_50V8J@

1 2

CC11 180P_0402_50V8J@CC11 180P_0402_50V8J@

1 2

CC12 180P_0402_50V8J@CC12 180P_0402_50V8J@

1 2

CC13 180P_0402_50V8J@CC13 180P_0402_50V8J@

1 2

CC15 180P_0402_50V8J@CC15 180P_0402_50V8J@

1 2

CC16 180P_0402_50V8J@CC16 180P_0402_50V8J@

1 2

CC17 180P_0402_50V8J@CC17 180P_0402_50V8J@

1 2

CC18 180P_0402_50V8J@CC18 180P_0402_50V8J@

1 2

A A

Place Caps Close to South Bridge

H_INIT#
H_A20M#
H_INTR
H_NMI
H_SMI#
H_STPCLK#
H_IGNNE#

H_FERR#

+CPU_GTLREF2

+1.05VS

QC: POP
DC: DEPOP

4

H_ADSTB#0<7>

H_REQ#0<7>
H_REQ#1<7>
H_REQ#2<7>
H_REQ#3<7>
H_REQ#4<7>

H_ADSTB#1<7>

H_A20M#<21>
H_FERR#<21>
H_IGNNE#<21>

H_STPCLK#<21>
H_INTR<21>
H_NMI<21>
H_SMI#<21>

RC34 51_0402_1%RC34 51_0402_1%

1 2

+CPU_GTLREF2

Layout close CPU PIN D22
50 ohm, 0.5 inch (max)

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

H_THERMDA2
H_THERMDC2

3

+1.05VS

Quad Core support circuit

12

RC39

RC39

1K_0402_1%

1K_0402_1%

12

D

D

RC37

RC37

2K_0402_1%

2K_0402_1%

S

S

H_A#[3..35]<7>

JCPU1A

JCPU1A

J4

ADDR GROUP 0 ADDR GROUP 1

ADDR GROUP 0 ADDR GROUP 1

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

Merom Ball-out Rev 1a@

Merom Ball-out Rev 1a@

Thermal Sensor SMSC EMC1402-1 (Main)

+3VS

1

CC9

CC9

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

H_THERMDA

CC14

CC14

H_THERMDC

1 2

2200P_0402_50V7K

2200P_0402_50V7K

13

QC4

QC4

2

G

G

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

H_A#[3..35]

ADS#
BNR#
BPRI#

DEFER#

DRDY#

DBSY#

BR0#
IERR#

INIT#

LOCK#

CONTROL

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#

PREQ#

TCK

TDI
TDO
TMS

TRST#

XDP/ITP SIGNALS

XDP/ITP SIGNALS

DBR#

THERMAL

THERMAL

PROCHOT#

THERMDA
THERMDC

ICH

ICH

THERMTRIP#

H CLK

H CLK

BCLK[0]
BCLK[1]

RESERVED

RESERVED

UC3

UC3

1

VDD

2

D+

3

ALERT/THERM2

D-

4

THERM

SMSC EMC1402

SMSC EMC1402

+3VALW

12

RC40

RC40
100K_0402_5%

100K_0402_5%

C

C

E

E

QC3

QC3

3 1
MMBT3904_SOT23

MMBT3904_SOT23

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
C1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

D21
A24
B25

C7

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

A22
A21

+1.05VS

20080224 ADD

+3VALW

12

RC41

RC41
100K_0402_5%

100K_0402_5%

RC36

RC36

1 2

2

B

B

10K_0402_5%

10K_0402_5%

H_ADS#
H_BNR#
H_BPRI#

H_DEFER#
H_DRDY#
H_DBSY#

H_BR0#
H_IERR#

H_INIT#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_HIT#
H_HITM#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3

XDP_BPM#4
ITP_PREQ
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#

H_PROCHOT#
H_THERMDA
H_THERMDC

H_THERMTRIP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

PROCHOT# PU: 68Ohm near CPU and MVP6.
56Ohm near CPU

1 2

RC44 56_0402_5%@RC44 56_0402_5%@

1 2

RC45 68_0402_5%RC45 68_0402_5%

H_PROCHOT#

8

SCLK

7

SDATA

6
5

GND

SMB_EC_CK2
SMB_EC_DA2

RC33

@RC33

@

1 2

10K_0402_5%

10K_0402_5%

QUAD_DET <6>

H_ADS# <7>
H_BNR# <7>
H_BPRI# <7>

H_DEFER# <7>
H_DRDY# <7>
H_DBSY# <7>

H_BR0# <7>

H_INIT# <21>
H_LOCK# <7>
H_RESET# <7>

H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>
H_TRDY# <7>

H_HIT# <7>
H_HITM# <7>

TBD

H_THERMTRIP# <8,21>

CLK_CPU_BCLK <16>
CLK_CPU_BCLK# <16>

Place close to CPU within 500mil

2

H_IERR#
H_THERMTRIP#
ITP_PREQ
ITP_TDI
ITP_TDO
ITP_TMS

H_BR0#

H_INTR
H_NMI
H_RESET#

200800404 RC14,RC15 change to 51 Ohm

ITP_TCK
ITP_TRST#

RC1

RC1
RC2 56_0402_5%RC2 56_0402_5%
RC3 49.9_0402_1%RC3 49.9_0402_1%
RC5

RC5

@

@

RC6 51_0402_1%

RC6 51_0402_1%

1 2

RC7 39_0402_1%RC7 39_0402_1%

200800414 Del RC8

RC9 62_0402_5%RC9 62_0402_5%

1 2

200800414 Del RC10

RC11 150_0402_1%RC11 150_0402_1%

1 2

RC12 150_0402_1%RC12 150_0402_1%

1 2

RC13 49.9_0402_1%RC13 49.9_0402_1%

@

@

RC14 51_0402_1%

RC14 51_0402_1%
RC15 51_0402_1% @ RC15 51_0402_1% @

20080317 RC1,RC13 change to 49.9 Ohm

+1.05VS

12

CC71 0.1U_0402_16V4ZCC71 0.1U_0402_16V4Z

XDP_DBRESET# <22>

B

B

2

QC5

@

QC5

@

MMBT3904_NL_SOT23-3

MMBT3904_NL_SOT23-3

E

E

3 1

C

C

To EC & VGA conn

EC_SMB_CK2 <17,32>
EC_SMB_DA2 <17,32>

+3VS

Address:1001_100x EMC1402-1
Address:1001_101x EMC1402-2

OCP# <22>

CC70

@CC70

@

1 2

1

+1.05VS

12

RC31

@RC31

@

330_0402_5%

330_0402_5%

B

B

2

E

E

3 1

C

C

QC2

@

QC2

@

MMBT3904_SOT23

MMBT3904_SOT23

+1.05VS

12

RC16

@RC16

@

330_0402_5%

330_0402_5%

B

B

2

E

E

3 1

C

C

QC1

@

QC1

@

MMBT3904_SOT23

MMBT3904_SOT23

To power

To power

12
12
12
12

12

12

12
12

49.9_0402_1%

49.9_0402_1%

150_0402_1%

150_0402_1%

+1.05VS

H_THERMTRIP#

H_THERMTRIP#

XDP Connector

JXDP

JXDP

1

1

3
XDP_BPM#2
XDP_BPM#1

XDP_BPM2#2
XDP_BPM2#1

ITP_DBRESET#
ITP_TRST#
ITP_TMS

QC:
ES1: DePOP ALL
ES2: POP ALL
DC: DEPOP ALL

XDP_BPM2#3

+1.05VS

Thermal Sensor SMSC EMC1402-2 (Second)

+3VS

1

CC69

@CC69

@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

H_THERMDA2
H_THERMDC2

2200P_0402_50V7K

2200P_0402_50V7K

1
2
3
4

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29
GND31GND

GND33GND

P-TWO_196027-30041@

P-TWO_196027-30041@

XDP_BPM2#0

XDP_BPM2#1

XDP_BPM2#2

XDP_BPM2#3

12

RR38 10K_0402_5%RR38 10K_0402_5%

Place close to JITP within 200ps = 1000 mil

UC4

UC4

VDD
D+

ALERT/THERM2

D­THERM

SMSC EMC1402@

SMSC EMC1402@

SCLK

SDATA

8
7
6
5

GND

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32
34

RR34
RR35
RR36
RR37

XDP_PRE#

SMB_EC_CK3
SMB_EC_DA3

RC43

@RC43

@

1 2

10K_0402_5%

10K_0402_5%

XDP_BPM#4ITP_PREQ
XDP_BPM#3

XDP_BPM#0

XDP_BPM2#3
XDP_BPM2#0

H_PWRGOOD_R

ITP_TCK

ITP_TDO
ITP_TDI
XDP_PRE#

51_0402_1%

@RR34

51_0402_1%

@

51_0402_1%

@RR35

51_0402_1%

@

51_0402_1%

@RR36

51_0402_1%

@

51_0402_1%

@RR37

51_0402_1%

@

1 2

RC46 0_0402_5%@RC46 0_0402_5%@

1 2

RC47 0_0402_5%@RC47 0_0402_5%@

RR32

RR32

1 2

1K_0402_5%

1K_0402_5%

1 2

RR33 1K_0402_5%RR33 1K_0402_5%

+1.05VS

To EC & VGA conn

+3VS

ENTRIP2 <39,41>

ENTRIP1 <39,41>

H_PWRGOOD <5,21>
CLK_XDP# <16>CLK_XDP<16>

H_RESET#H_RESET#_R

EC_SMB_CK2 <17,32>
EC_SMB_DA2 <17,32>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/02/20 2008/10/25

2008/02/20 2008/10/25

2008/02/20 2008/10/25

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

401596

401596

401596

1

447Tuesday, May 27, 2008

447Tuesday, May 27, 2008

447Tuesday, May 27, 2008

B

B

B

of

of

of

5

4

3

2

1

H_D#[0..15]<7>

D D

+1.05VS

12

RC18

RC18
1K_0402_1%

1K_0402_1%

+GTL_REF0

12

RC19

RC19
2K_0402_1%

2K_0402_1%

Close to CPU pin AD26
within 500mils.

C C

RC20 1K_0402_5%@RC20 1K_0402_5%@
RC21 1K_0402_5%@RC21 1K_0402_5%@

CC20 0.1U_0402_16V4Z@CC20 0.1U_0402_16V4Z@

CPU_BSEL CPU_BSEL2 CPU_BSEL1

166

B B

200

H_DSTBN#0<7>
H_DSTBP#0<7>
H_DINV#0<7>
H_D#[16..31]<7>

H_DSTBN#1<7>
H_DSTBP#1<7>
H_DINV#1<7> H_DINV#3 <7>

1 2
1 2

1 2

RC22 0_0402_5%@RC22 0_0402_5%@

CPU_BSEL0<8,16>
CPU_BSEL1<8,16>
CPU_BSEL2<8,16>

+GTL_REF0

TEST1
TEST2

TEST4

CPU_BSEL0

01

0

1

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8

H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

1

0

AD26

AF26

JCPU1B

JCPU1B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#
GTLREF

C23

TEST1

D25

TEST2

C24

TEST3
TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a@

Merom Ball-out Rev 1a@

DATA GRP 1

DATA GRP 1

MISC

MISC

DATA GRP 0

DATA GRP 0

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#

DATA GRP 2DATA GRP 3

DATA GRP 2DATA GRP 3

D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#
DPWR#

PWRGOOD

SLP#

PSI#

H_PWRGOOD
H_CPUSLP#
H_BR1_C#

H_D#32

Y22

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

V23

H_D#37

T22

H_D#38

U25

H_D#39

U23

H_D#40

Y25

H_D#41

W22

H_D#42

Y23

H_D#43

W24

H_D#44

W25

H_D#45

AA23

H_D#46

AA24

H_D#47

AB25
Y26
AA26
U22

H_D#48

AE24

H_D#49

AD24

H_D#50

AA21

H_D#51

AB22

H_D#52

AB21

H_D#53

AC26

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AC25

H_D#58

AE21

H_D#59

AD21

H_D#60

AC22

H_D#61

AD23

H_D#62

AF22

H_D#63

AC23
AE25
AF24
AC20

COMP0

R26

COMP1

U26

COMP2

AA1

COMP3

Y1

H_DPRSTP#

E5

H_DPSLP#

B5

H_DPWR#

D24

H_PWRGOOD

D6

H_CPUSLP#

D7

H_PSI#

AE6

RC27 150_0402_1%@RC27 150_0402_1%@

1 2

RC28 51_0402_1%@RC28 51_0402_1%@

1 2

RC35 62_0402_5%@RC35 62_0402_5%@

1 2

266 0 0 0

Need to check

H_CPUSLP#
H_PWRGOOD
H_DPRSTP#
H_DPSLP#

CC72 180P_0402_50V8J@CC72 180P_0402_50V8J@
CC73 180P_0402_50V8J@CC73 180P_0402_50V8J@
CC74 180P_0402_50V8J@CC74 180P_0402_50V8J@
CC75 180P_0402_50V8J@CC75 180P_0402_50V8J@

12
12
12
12

20080317 new add

H_D#[32..47] <7>

H_DSTBN#2 <7>
H_DSTBP#2 <7>
H_DINV#2 <7>
H_D#[48..63] <7>

H_DSTBN#3 <7>
H_DSTBP#3 <7>

To +CPU_CORE

H_DPRSTP# <8,21,44>
H_DPSLP# <21>

H_DPWR# <7>
H_PWRGOOD <4,21>
H_CPUSLP# <7>

H_PSI# <44>

To +CPU_CORE

+1.05VS

Reserve for
debug
close to CPU

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

12

RC24

RC24

27.4_0402_1%

27.4_0402_1%

12

RC25

RC25

54.9_0402_1%

54.9_0402_1%

1 2

RC42 0_0402_5%@RC42 0_0402_5%@

RC26

RC26

27.4_0402_1%

27.4_0402_1%

12

RC23

RC23

54.9_0402_1%

54.9_0402_1%

H_BR1#

+VCC_CORE +VCC_CORE

12

H_BR1_C#

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AC10

AB10
AB12
AB14
AB15
AB17
AB18

A7

A9
A10
A12
A13
A15
A17
A18
A20

B7

B9
B10
B12
B14
B15
B17
B18
B20

C9
C10
C12
C13
C15
C17
C18

D9
D10
D12
D14
D15
D17
D18

E7

E9
E10
E12
E13
E15
E17
E18
E20

F10
F12
F14
F15
F17
F18
F20
AA7
AA9

AB9

JCPU1C

JCPU1C

F7
F9

@

@

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

+VCC_CORE

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

RC29

RC29
100_0402_1%

100_0402_1%

1 2

RC30

RC30
100_0402_1%

100_0402_1%

1 2

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VSSSENSE

AE7

.

.

VCCSENSE

VSSSENSE

CPU_VID0 <44>
CPU_VID1 <44>
CPU_VID2 <44>
CPU_VID3 <44>

To +CPU_CORE

CPU_VID4 <44>
CPU_VID5 <44>
CPU_VID6 <44>

VCCSENSE <44>

To +CPU_CORE

VSSSENSE <44>

To +CPU_CORE

Length match
within 25 mils.

+1.05VS

1

+

2

1

1

CC21

CC21

CC22

CC22

2

2

10U_0805_10V4Z

10U_0805_10V4Z

Near pin C26

CC19

@+CC19

@

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

+1.5VS

0.01U_0402_16V7K

0.01U_0402_16V7K

Near pin B26

The trace

A A

Close to CPU pin
within 500mils.

width/space/other
is 20/7/25.

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/02/20 2008/10/25

2008/02/20 2008/10/25

2008/02/20 2008/10/25

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

401596

401596

401596

1

547Saturday, May 17, 2008

547Saturday, May 17, 2008

547Saturday, May 17, 2008

B

B

B

of

of

of

5

4

+VCC_CORE

Place these capacitors on L8
(North side,Secondary Layer)

1

CC23

CC23
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC24

CC24
10U_0805_6.3V6M

10U_0805_6.3V6M

2

3

1

CC25

CC25
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC26

CC26
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC27

CC27
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC28

CC28
10U_0805_6.3V6M

10U_0805_6.3V6M

2

2

1

CC29

CC29
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC30

CC30
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

RC3851_0402_1% RC3851_0402_1%

+1.05VS

CC61

CC61

+VCC_CORE

1

CC31

CC31
10U_0805_6.3V6M

10U_0805_6.3V6M

2

+VCC_CORE

1

CC39

CC39
10U_0805_6.3V6M

10U_0805_6.3V6M

2

+VCC_CORE

1

CC47

CC47
10U_0805_6.3V6M

10U_0805_6.3V6M

2

South Side Secondary
of CPU Socket

330U_D2_2VY_R7M

330U_D2_2VY_R7M

+1.05VS

1

+

+

2

1

CC62

CC62

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

CC32

CC32
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC40

CC40
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC48

CC48
10U_0805_6.3V6M

10U_0805_6.3V6M

2

+VCC_CORE

1

+

+

CC55

CC55

2

1

CC33

CC33
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC41

CC41
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC49

CC49
10U_0805_6.3V6M

10U_0805_6.3V6M

2

CC56

CC56

330U_D2_2VY_R7M

330U_D2_2VY_R7M

1

CC63

CC63

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

+

+

2

330U_D2_2VY_R7M@

330U_D2_2VY_R7M@

1

2

1

CC34

CC34
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC42

CC42
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC50

CC50
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

+

+

CC57

CC57

2

CC64

CC64

0.1U_0402_16V4Z

0.1U_0402_16V4Z

330U_D2_2VY_R7M

330U_D2_2VY_R7M

1

+

+

CC58

CC58

CC59

CC59
@

@

2

330U_D2_2VY_R7M

330U_D2_2VY_R7M

1

CC65

CC65

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

CC35

CC35
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC43

CC43
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC51

CC51
10U_0805_6.3V6M

10U_0805_6.3V6M

2

330U_D2_2VY_R7M

330U_D2_2VY_R7M

1

+

+

CC60

CC60

2

1

CC36

CC36
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC44

CC44
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC52

CC52
10U_0805_6.3V6M

10U_0805_6.3V6M

2

North Side Secondary
of CPU Socket

1

+

+

2

1

CC66

CC66

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

CC67

CC67

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

CC37

CC37
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC45

CC45
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC53

CC53
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC38

CC38
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC46

CC46
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

CC54

CC54
10U_0805_6.3V6M

10U_0805_6.3V6M

2

ESR <= 1.5m ohm
Capacitor > 1980uF

330uF ESR 7m ohm X 6 PCS

Place these inside socket
cavity on Bottom layer (North
side Secondary)

Mid Frequence Decoupling

D D

JCPU1D

JCPU1D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

C C

QUAD_DET<4>

Pin F8
Dual Core: GND (internal)
Quad Core: Floating (internal)

B B

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

.

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

12

330U_D2_2VY_R7M

330U_D2_2VY_R7M

Pin D8,AA8,AC8 and AE8

A A

Reserved for QC

5

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/02/20 2008/10/25

2008/02/20 2008/10/25

2008/02/20 2008/10/25

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

401596

401596

401596

1

647Tuesday, May 27, 2008

647Tuesday, May 27, 2008

647Tuesday, May 27, 2008

B

B

B

of

of

5

4

3

2

1

U3A

H_D#[0..63]<5>

D D

C C

Layout Note:
H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 10/20

within 100 mils from NB

+1.05VS+1.05VS

B B

12

R25

R25
1K_0402_1%

1K_0402_1%

12

R27

R27
2K_0402_1%

2K_0402_1%

1

C53

C53

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

H_RCOMP +H_SWNG+H_VREF

R28

R28

24.9_0402_1%

24.9_0402_1%12R29

12

R26

R26
221_0402_1%

221_0402_1%

12

R29
100_0402_1%

100_0402_1%

1

C54

C54

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

H_RESET#<4>
H_CPUSLP#<5>

Near B3 pin

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

+H_SWNG
H_RCOMP

+H_VREF

U3A

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3

G2

H_D#_4

H6

H_D#_5

H2

H_D#_6

F6

H_D#_7

D4

H_D#_8

H3

H_D#_9

M9

H_D#_10

M11

H_D#_11

J1

H_D#_12

J2

H_D#_13

N12

H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17

R2

H_D#_18

N9

H_D#_19

L6

H_D#_20

M5

H_D#_21

J3

H_D#_22

N2

H_D#_23

R1

H_D#_24

N5

H_D#_25

N6

H_D#_26

P13

H_D#_27

N8

H_D#_28

L7

H_D#_29

N10

H_D#_30

M3

H_D#_31

Y3

H_D#_32

AD14

H_D#_33

Y6

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

Y7

H_D#_38

W2

H_D#_39

AA8

H_D#_40

Y9

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

C5

H_SWING

E3

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329
NBR3@

NBR3@

H_ADSTB#_0
H_ADSTB#_1

H_BREQ#

H_DEFER#

HOST

HOST

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_LOCK#

H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#
H_BPRI#

H_HIT#

H_HITM#

H_RS#_0
H_RS#_1
H_RS#_2

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

J8
L3
Y13
Y1

L10
M7
AA5
AE6

L9
M8
AA6
AE5

B15
K13
F13
B13
B14

B6
F12
C8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

CLK_MCH_BCLK
CLK_MCH_BCLK#

H_A#[3..35] <4>

H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR# <4>
H_BPRI# <4>
H_BR0# <4>
H_DEFER# <4>
H_DBSY# <4>
CLK_MCH_BCLK <16>
CLK_MCH_BCLK# <16>
H_DPWR# <5>
H_DRDY# <4>
H_HIT# <4>
H_HITM# <4>
H_LOCK# <4>
H_TRDY# <4>

H_DINV#0 <5>
H_DINV#1 <5>
H_DINV#2 <5>
H_DINV#3 <5>

H_DSTBN#0 <5>
H_DSTBN#1 <5>
H_DSTBN#2 <5>
H_DSTBN#3 <5>

H_DSTBP#0 <5>
H_DSTBP#1 <5>
H_DSTBP#2 <5>
H_DSTBP#3 <5>

H_REQ#0 <4>
H_REQ#1 <4>
H_REQ#2 <4>
H_REQ#3 <4>
H_REQ#4 <4>

H_RS#0 <4>
H_RS#1 <4>
H_RS#2 <4>

A A

Security Classification

Security Classification

Security Classification

2008/02/20 2009/2/1

2008/02/20 2009/2/1

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/02/20 2009/2/1

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

401596

401596

401596

B

B

B

of

747Saturday, May 17, 2008

of

747Saturday, May 17, 2008

of

747Saturday, May 17, 2008

1

Strap Pin Table

5

011 = FSB667

CFG[2:0]

CFG5
CFG6

D D

CFG7

CFG9
CFG10

CFG[13:12]

CFG16
CFG19

CFG20

(PCIE/SDVO select)

C C

B B

+3VS

A A

1 2

R67 10K_0402_5%R67 10K_0402_5%

010 = FSB800
000 = FSB1067

0 = DMI x 2
1 = DMI x 4

0 = iTPM Host Interface is enabled

1 = iTPM Host Interface is Disabled
0 = Intel Management Engine Crypto Transport Layer Security

(TLS) cipher suite with no confidentiality
1 = Intel Management Engine Crypto TLS cipher suite with

confidentiality
0 = Lane Reversal Enable

0 = PCIe Loopback Enable
1 = Disable

01 = All Z Mode Enabled
00 = Reserved
10 = XOR Mode Enabled
11 = Normal Operation

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled

0 = Normal Operation
1 = DMI Lane Reversal Enable

0 = Only PCIE or SDVO is operational.

(Default)

*

*

*

(Default)

(Default)

(Default) - can support disble by SW.

*

*

(Default)1 = Normal Operation

(Default)

*

(Default)

*

(Default)

*

(Default)

*

1 = PCIE/SDVO are operating simu.

R44 1K_0402_5%R44 1K_0402_5%
R45 1K_0402_5%R45 1K_0402_5%
R46 1K_0402_5%R46 1K_0402_5%

R47 2.21K_0402_1%@R47 2.21K_0402_1%@
R49 2.21K_0402_1%@R49 2.21K_0402_1%@
R51 2.21K_0402_1%@R51 2.21K_0402_1%@

R53 2.21K_0402_1%@R53 2.21K_0402_1%@
R55 2.21K_0402_1%@R55 2.21K_0402_1%@

R57 2.21K_0402_1%@R57 2.21K_0402_1%@
R59 2.21K_0402_1%@R59 2.21K_0402_1%@

R61 2.21K_0402_1%@R61 2.21K_0402_1%@

R62 4.02K_0402_1%@R62 4.02K_0402_1%@
R64 4.02K_0402_1%@R64 4.02K_0402_1%@

R66 0_0402_5%R66 0_0402_5%

R69 0_0402_5%R69 0_0402_5%
R71 100_0402_5%R71 100_0402_5%

R72 0_0402_5%R72 0_0402_5%
R73 0_0402_5%R73 0_0402_5%

GMCH_PWROK

1 2
1 2
1 2

1 2
1 2

1 2
1 2

1 2

1 2
1 2

1 2

1 2
1 2

1 2
1 2

VGATE<22,32,44>

PM_PWROK<22,32>

PM_EXTTS#0_1_R

Use VGATE for GMCH_PWROK

1 2

R75 0_0402_5%@R75 0_0402_5%@

PM_PWROK

1 2

R76 0_0402_5%R76 0_0402_5%

5

CPU_BSEL0<5,16>
CPU_BSEL1<5,16>
CPU_BSEL2<5,16>

+3VS

PM_SYNC#<22>
H_DPRSTP#<5,21,44>

PM_EXTTS#0_1<14,15>

PLT_RST#<14,15,17,20,25,26,27,28,32>
H_THERMTRIP#<4,21>
PM_DPRSLPVR<22,44>

4

U3B

U3B

M36

RSVD1

N36

RSVD2

R33

RSVD3

T33

RSVD4

AH9

RSVD5

AH10

RSVD6

AH12

RSVD7

AH13

RSVD8

K12

RSVD9

AL34

RSVD10

AK34

RSVD11

AN35

RSVD12

AM35

RSVD13

T24

RSVD14

B31

RSVD15

B2

RSVD16

M1

RSVD17

AY21

RSVD20

BG23

RSVD22

BF23

RSVD23

BH18

RSVD24

BF18

RSVD25

4

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

MCH_CFG_5
MCH_CFG_6
MCH_CFG_7

MCH_CFG_9
MCH_CFG_10

MCH_CFG_12
MCH_CFG_13

MCH_CFG_16

MCH_CFG_19
MCH_CFG_20

PM_SYNC#_R
PM_EXTTS#0

PM_EXTTS#0_1_R
GMCH_PWROK
MCH_RSTIN#
NB_THERMTRIP#
DPRSLPVR

12
12
12

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC_1

BF48

NC_2

BD48

NC_3

BC48

NC_4

BH47

NC_5

BG47

NC_6

BE47

NC_7

BH46

NC_8

BF46

NC_9

BG45

NC_10

BH44

NC_11

BH43

NC_12

BH6

NC_13

BH5

NC_14

BG4

NC_15

BH3

NC_16

BF3

NC_17

BH2

NC_18

BG2

NC_19

BE2

NC_20

BG1

NC_21

BF1

NC_22

BD1

NC_23

BC1

NC_24

F1

NC_25

A47

NC_26

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329
NBR3@

NBR3@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RSVD CFG PM NC

RSVD CFG PM NC

3

DDR CLK/ CONTROL/ COMPENSATIONHDA

DDR CLK/ CONTROL/ COMPENSATIONHDA

CLKDMIGRAPHICS VIDMEMISC

CLKDMIGRAPHICS VIDMEMISC

3

AP24

SA_CK_0

AT21

SA_CK_1

AV24

SB_CK_0

AU20

SB_CK_1

AR24

SA_CK#_0

AR21

SA_CK#_1

AU24

SB_CK#_0

AV20

SB_CK#_1

BC28

SA_CKE_0

AY28

SA_CKE_1

AY36

SB_CKE_0

BB36

SB_CKE_1

BA17

SA_CS#_0

AY16

SA_CS#_1

AV16

SB_CS#_0

AR13

SB_CS#_1

BD17

SA_ODT_0

AY17

SA_ODT_1

BF15

SB_ODT_O

AY13

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK
HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

2008/02/20 2009/2/1

2008/02/20 2009/2/1

2008/02/20 2009/2/1

SMRCOMP

BG22

SMRCOMP#

BH21

+SM_RCOMP_VOH

BF28

+SM_RCOMP_VOL

BH28

+SM_VREF

AV42

DDR3_SM_PWROK_C

AR36

SM_REXT

BF17

SM_DRAMRST#

BC36

B38
A38
E41
F41

CLK_MCH_3GPLL

F43

CLK_MCH_3GPLL#

E43

AE41
AE37
AE47
AH39

AE40
AE38
AE48
AH40

AE35
AE43
AE46
AH42

AD35
AE44
AF46
AH43

B33
B32
G33
F33
E33

C34

AH37
AH36
AN36
AJ35
AH34

N28
M28
G36
E36
K36
H36

B12

B28
B30
B29
C29
A28

+NB_CLVREF

0.1U_0402_16V4Z

0.1U_0402_16V4Z

PM_PWROK

+NB_CLVREF

+NB_CLVREF=0.355V

SDVO_SCLK
SDVO_SDATA
CLKREQ_3GPLL#

MCH_TSATN#

Compal Secret Data

Compal Secret Data

Compal Secret Data

R33 80.6_0402_1%R33 80.6_0402_1%
R34 80.6_0402_1%R34 80.6_0402_1%

20080425 R37@

R37 10K_0402_1%@R37 10K_0402_1%@
R38 499_0402_1%R38 499_0402_1%

SM_DRAMRST# <14,15>

Follow Design Guide

CL_VREF
should be

0.35 V

C60

C60

Deciphered Date

Deciphered Date

Deciphered Date

2

DDRA_CLK0 <14>
DDRA_CLK1 <14>
DDRB_CLK0 <15>
DDRB_CLK1 <15>

DDRA_CLK0# <14>
DDRA_CLK1# <14>
DDRB_CLK0# <15>
DDRB_CLK1# <15>

DDRA_CKE0 <14>
DDRA_CKE1 <14>
DDRB_CKE0 <15>
DDRB_CKE1 <15>

DDRA_SCS0# <14>
DDRA_SCS1# <14>
DDRB_SCS0# <15>
DDRB_SCS1# <15>

DDRA_ODT0 <14>
DDRA_ODT1 <14>
DDRB_ODT0 <15>
DDRB_ODT1 <15>

1 2
1 2

1 2
1 2

CLK_MCH_3GPLL <16>
CLK_MCH_3GPLL# <16>

DMI_ITX_MRX_N0 <20>
DMI_ITX_MRX_N1 <20>
DMI_ITX_MRX_N2 <20>
DMI_ITX_MRX_N3 <20>

DMI_ITX_MRX_P0 <20>
DMI_ITX_MRX_P1 <20>
DMI_ITX_MRX_P2 <20>
DMI_ITX_MRX_P3 <20>

DMI_MTX_IRX_N0 <20>
DMI_MTX_IRX_N1 <20>
DMI_MTX_IRX_N2 <20>
DMI_MTX_IRX_N3 <20>

DMI_MTX_IRX_P0 <20>
DMI_MTX_IRX_P1 <20>
DMI_MTX_IRX_P2 <20>
DMI_MTX_IRX_P3 <20>

+1.05VS

R74

R74

1K_0402_1%

1K_0402_1%

1 2

1

R77

R77

499_0402_1%

499_0402_1%

2

1 2

CL_CLK0 <22>
CL_DATA0 <22>

CL_RST#0 <22>

CLKREQ_3GPLL# <16>

MCH_ICH_SYNC# <22>

2

SM_DRAMRST# would be
needed for DDR3 only

For Cantiga 80 Ohm

20mil

DDR3_SM_PWROK_C

+1.5V

1 2

1 2

+1.5V

1

C59

C59

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

Strap Pin Table

SDVO_CTRLDATA

+1.05VS

R83

R83

54.9_0402_1%

54.9_0402_1%

MCH_TSATN#

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

1

+1.5V

12

R30

R30

1K_0402_1%

1K_0402_1%

+SM_RCOMP_VOH

2

0.01U_0402_25V4Z

0.01U_0402_25V4Z

+SM_RCOMP_VOL

0.01U_0402_25V4Z

0.01U_0402_25V4Z

R35

R35
1K_0402_1%

1K_0402_1%

R39

R39
1K_0402_1%

1K_0402_1%

R1071 0_0402_5%R1071 0_0402_5%

C55

C55

C57

C57

1 2

1

2

1

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
C56

C56

1

3.01K_0402_1%

3.01K_0402_1%

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
C58

C58

1

12

R31

R31

12

R32

R32

1K_0402_1%

1K_0402_1%

DDR3_SM_PWROK <42>

20080425 change to 0 Ohm

0 = No SDVO Card Present
1 = SDVO Card Present

0 = Digital DisplayPort Disable
1 = Digital DisplayPort Device Present

SDVO_SCLK
SDVO_SDATA

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

R79 0_0402_5%R79 0_0402_5%

1 2

R80 0_0402_5%R80 0_0402_5%

1 2

+3VS

12

12

R81

R81

1K_0402_5%

1K_0402_5%

12

Q4

Q4

MMBT3904_NL_SOT23-3

MMBT3904_NL_SOT23-3

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

401596

401596

401596

R82

R82
1K_0402_5%

1K_0402_5%

B

B

2

E

E

3 1

C

C

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

MCH_TSATN_EC# <32>

1

R135

@R135

@

1 2

0_0402_5%

0_0402_5%

1 2

R134

R134
0_0402_5%

0_0402_5%

847Saturday, May 17, 2008

847Saturday, May 17, 2008

847Saturday, May 17, 2008

(Default)

*

(Default)DDPC_CTRLDATA

*

of

of

of

+3VS

B

B

B

5

D D

DDR_A_D[0..63]<14>

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

U3D

U3D

AJ38

SA_DQ_0

AJ41

SA_DQ_1

AN38

SA_DQ_2

AM38

SA_DQ_3

AJ36

SA_DQ_4

AJ40

SA_DQ_5

AM44

SA_DQ_6

AM42

SA_DQ_7

AN43

SA_DQ_8

AN44

SA_DQ_9

AU40

SA_DQ_10

AT38

SA_DQ_11

AN41

SA_DQ_12

AN39

SA_DQ_13

AU44

SA_DQ_14

AU42

SA_DQ_15

AV39

SA_DQ_16

AY44

SA_DQ_17

BA40

SA_DQ_18

BD43

SA_DQ_19

AV41

SA_DQ_20

AY43

SA_DQ_21

BB41

SA_DQ_22

BC40

SA_DQ_23

AY37

SA_DQ_24

BD38

SA_DQ_25

AV37

SA_DQ_26

AT36

SA_DQ_27

AY38

SA_DQ_28

BB38

SA_DQ_29

AV36

SA_DQ_30

AW36

SA_DQ_31

BD13

SA_DQ_32

AU11

SA_DQ_33

BC11

SA_DQ_34

BA12

SA_DQ_35

AU13

SA_DQ_36

AV13

SA_DQ_37

BD12

SA_DQ_38

BC12

SA_DQ_39

BB9

SA_DQ_40

BA9

SA_DQ_41

AU10

SA_DQ_42

AV9

SA_DQ_43

BA11

SA_DQ_44

BD9

SA_DQ_45

AY8

SA_DQ_46

BA6

SA_DQ_47

AV5

SA_DQ_48

AV7

SA_DQ_49

AT9

SA_DQ_50

AN8

SA_DQ_51

AU5

SA_DQ_52

AU6

SA_DQ_53

AT5

SA_DQ_54

AN10

SA_DQ_55

AM11

SA_DQ_56

AM5

SA_DQ_57

AJ9

SA_DQ_58

AJ8

SA_DQ_59

AN12

SA_DQ_60

AM13

SA_DQ_61

AJ11

SA_DQ_62

AJ12

SA_DQ_63

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329
NBR3@

NBR3@

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

4

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#

SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

BD21
BG18
AT25

BB20
BD20
AY20

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7

AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8

DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_BS0 <14>
DDR_A_BS1 <14>
DDR_A_BS2 <14>

DDR_A_RAS# <14>
DDR_A_CAS# <14>
DDR_A_WE# <14>

DDR_A_DM[0..7] <14>

DDR_A_DQS[0..7] <14>

DDR_A_DQS#[0..7] <14>

DDR_A_MA[0..14] <14>

3

DDR_B_D[0..63]<15>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AK47
AH46
AP47
AP46

AJ46

AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11

BG8
BH12
BF11

BF8
BG7
BC5
BC6

AY3

AY1

BF6

BF5

BA1

BD3

AV2
AU3
AR3
AN2

AY2

AV1

AP3
AR1

AL1

AL2

AJ1
AH1
AM2
AM3
AH3

AJ3

2

U3E

U3E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329
NBR3@

NBR3@

1

BC16

SB_BS_0

BB17

SB_BS_1

BB33

SB_BS_2

AU17

SB_RAS#

BG16

SB_CAS#

BF14

SB_WE#

DDR_B_DM0

AM47

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

AY47
BD40
BF35
BG11
BA3
AP1
AK2

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6

AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

DDR_B_BS0 <15>
DDR_B_BS1 <15>
DDR_B_BS2 <15>

DDR_B_RAS# <15>
DDR_B_CAS# <15>
DDR_B_WE# <15>

DDR_B_DM[0..7] <15>

DDR_B_MA[0..14] <15>

DDR_B_DQS[0..7] <15>

DDR_B_DQS#[0..7] <15>

A A

Security Classification

Security Classification

Security Classification

2008/02/20 2009/2/1

2008/02/20 2009/2/1

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/02/20 2009/2/1

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471
401596

401596

401596

1

B

B

B

of

947Wednesday, May 28, 2008

of

947Wednesday, May 28, 2008

of

947Wednesday, May 28, 2008

5

L_DDC_DATA

D D

1 = LFP Card Present; PCIE disable

C C

(Default)0 = LFP Disable

*

Need to connect to GND if not used.

B B

4

U3C

U3C

L32

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329
NBR3@

NBR3@

LVDS TV VGA

LVDS TV VGA

3

10mils

PEG_COMP

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9

T37
T36

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_10

PEG_RX_11

PEG_RX_12

PEG_RX_13

PEG_RX_14

PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_10

PEG_TX_11

PEG_TX_12

PEG_TX_13

PEG_TX_14

PEG_TX_15

1 2

RS1 49.9_0402_1%RS1 49.9_0402_1%

PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_N15

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_P15

PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15

2

+1.05VS

C62 0.1U_0402_16V7KC62 0.1U_0402_16V7K

1 2

C64 0.1U_0402_16V7KC64 0.1U_0402_16V7K

1 2

C66 0.1U_0402_16V7KC66 0.1U_0402_16V7K

1 2

C68 0.1U_0402_16V7KC68 0.1U_0402_16V7K

1 2

C70 0.1U_0402_16V7KC70 0.1U_0402_16V7K

1 2

C72 0.1U_0402_16V7KC72 0.1U_0402_16V7K

1 2

C74 0.1U_0402_16V7KC74 0.1U_0402_16V7K

1 2

C76 0.1U_0402_16V7KC76 0.1U_0402_16V7K

1 2

C78 0.1U_0402_16V7KC78 0.1U_0402_16V7K

1 2

C80 0.1U_0402_16V7KC80 0.1U_0402_16V7K

1 2

C82 0.1U_0402_16V7KC82 0.1U_0402_16V7K

1 2

C84 0.1U_0402_16V7KC84 0.1U_0402_16V7K

1 2

C86 0.1U_0402_16V7KC86 0.1U_0402_16V7K

1 2

C88 0.1U_0402_16V7KC88 0.1U_0402_16V7K

1 2

C90 0.1U_0402_16V7KC90 0.1U_0402_16V7K

1 2

C92 0.1U_0402_16V7KC92 0.1U_0402_16V7K

1 2

C61 0.1U_0402_16V7KC61 0.1U_0402_16V7K
C63 0.1U_0402_16V7KC63 0.1U_0402_16V7K
C65 0.1U_0402_16V7KC65 0.1U_0402_16V7K
C67 0.1U_0402_16V7KC67 0.1U_0402_16V7K
C69 0.1U_0402_16V7KC69 0.1U_0402_16V7K
C71 0.1U_0402_16V7KC71 0.1U_0402_16V7K
C73 0.1U_0402_16V7KC73 0.1U_0402_16V7K
C75 0.1U_0402_16V7KC75 0.1U_0402_16V7K

C77 0.1U_0402_16V7KC77 0.1U_0402_16V7K
C79 0.1U_0402_16V7KC79 0.1U_0402_16V7K
C81 0.1U_0402_16V7KC81 0.1U_0402_16V7K
C83 0.1U_0402_16V7KC83 0.1U_0402_16V7K
C85 0.1U_0402_16V7KC85 0.1U_0402_16V7K
C87 0.1U_0402_16V7KC87 0.1U_0402_16V7K
C89 0.1U_0402_16V7KC89 0.1U_0402_16V7K
C91 0.1U_0402_16V7KC91 0.1U_0402_16V7K

PCIE_GTX_C_MRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1

PCIE_GTX_C_MRX_P[0..15] <17>

PCIE_GTX_C_MRX_N[0..15] <17>

PCIE_MTX_C_GRX_P[0..15] <17>

PCIE_MTX_C_GRX_N[0..15] <17>

PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15

A A

Security Classification

Security Classification

Security Classification

2008/02/20 2009/2/1

2008/02/20 2009/2/1

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/02/20 2009/2/1

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

401596

401596

401596

1

B

B

B

of

10 47Saturday, May 17, 2008

of

10 47Saturday, May 17, 2008

of

10 47Saturday, May 17, 2008

5

+1.5V

DDR PWR

D D

330U_D2_2.5VY_R15M

330U_D2_2.5VY_R15M

10U_0805_10V4Z

10U_0805_10V4Z

1

+

+

C96

C96

2

0317 change value

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z

10U_0805_10V4Z

C94

C94

C93

C93

1

2

C95

C95

1

2

2

1

C96 change to Poly Cap 20080304

C C

Could be NC for DDR2 Board.

1

1

1

0.1U_0402_16V4Z

C230

C230

@

@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C228

C228

@

@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C231

C231

@

@

B B

A A

5

C202

C202

@

@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C134

C134

@

@

2

1

2

T3PAD T3PAD
T4PAD T4PAD

4

U3F

U3F

3000mA

AP33

VCC_SM_1

AN33

VCC_SM_2

BH32

VCC_SM_3

BG32

VCC_SM_4

BF32

VCC_SM_5

BD32

VCC_SM_6

BC32

VCC_SM_7

BB32

VCC_SM_8

BA32

VCC_SM_9

AY32

VCC_SM_10

AW32

VCC_SM_11

AV32

VCC_SM_12

AU32

VCC_SM_13

AT32

VCC_SM_14

AR32

VCC_SM_15

AP32

VCC_SM_16

AN32

VCC_SM_17

BH31

VCC_SM_18

BG31

VCC_SM_19

BF31

VCC_SM_20

BG30

VCC_SM_21

BH29

VCC_SM_22

BG29

VCC_SM_23

BF29

VCC_SM_24

BD29

VCC_SM_25

BC29

VCC_SM_26

BB29

VCC_SM_27

BA29

VCC_SM_28

AY29

VCC_SM_29

AW29

VCC_SM_30

AV29

VCC_SM_31

AU29

VCC_SM_32

AT29

VCC_SM_33

AR29

VCC_SM_34

AP29

VCC_SM_35

BA36

VCC_SM_36/NC

BB24

VCC_SM_37/NC

BD16

VCC_SM_38/NC

BB21

VCC_SM_39/NC

AW16

VCC_SM_40/NC

AW13

VCC_SM_41/NC

AT13

VCC_SM_42/NC

6326.84mA

Y26

VCC_AXG_1

AE25

VCC_AXG_2

AB25

VCC_AXG_3

AA25

VCC_AXG_4

AE24

VCC_AXG_5

AC24

VCC_AXG_6

AA24

VCC_AXG_7

Y24

VCC_AXG_8

AE23

VCC_AXG_9

AC23

VCC_AXG_10

AB23

VCC_AXG_11

AA23

VCC_AXG_12

AJ21

VCC_AXG_13

AG21

VCC_AXG_14

AE21

VCC_AXG_15

AC21

VCC_AXG_16

AA21

VCC_AXG_17

Y21

VCC_AXG_18

AH20

VCC_AXG_19

AF20

VCC_AXG_20

AE20

VCC_AXG_21

AC20

VCC_AXG_22

AB20

VCC_AXG_23

AA20

VCC_AXG_24

T17

VCC_AXG_25

T16

VCC_AXG_26

AM15

VCC_AXG_27

AL15

VCC_AXG_28

AE15

VCC_AXG_29

AJ15

VCC_AXG_30

AH15

VCC_AXG_31

AG15

VCC_AXG_32

AF15

VCC_AXG_33

AB15

VCC_AXG_34

AA15

VCC_AXG_35

Y15

VCC_AXG_36

V15

VCC_AXG_37

U15

VCC_AXG_38

AN14

VCC_AXG_39

AM14

VCC_AXG_40

U14

VCC_AXG_41

T14

VCC_AXG_42

AJ14

VCC_AXG_SENSE

AH14

VSS_AXG_SENSE

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329
NBR3@

NBR3@

4

VCC_AXG_NTCF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC SM

VCC SM

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43

VCC GFX NCTF

VCC GFX NCTF

VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52

POWER

POWER

VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

VCC GFX

VCC GFX

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

VCC SM LF

3

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

VCCSM_LF1

AV44

VCCSM_LF2

BA37

VCCSM_LF3

AM40

VCCSM_LF4

AV21

VCCSM_LF5

AY5

VCCSM_LF6

AM10

VCCSM_LF7

BB13

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C111

C111

Issued Date

Issued Date

Issued Date

1

2

3

+1.05VS

NB Core

220U_D2_4VY_R15M

220U_D2_4VY_R15M

1

+

+

C101

C101

2

220U_D2_4VY_R15M@

220U_D2_4VY_R15M@

Intel: VCC -- 220U*2, ESR 12mOhm

1

+

+

C97

C97

2

10U_0805_10V4Z

10U_0805_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

1

1

C102

C102

2

2

C98

C98

0.22U_0402_10V4Z

0.22U_0402_10V4Z

C97,C101 change to Poly Cap 20080304

1

1

C113

C113

0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

1

0.22U_0402_10V4Z

0.22U_0402_10V4Z

2008/02/20 2009/2/1

2008/02/20 2009/2/1

2008/02/20 2009/2/1

C112

C112

C114

C114

0.22U_0402_10V4Z

0.22U_0402_10V4Z

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2

1

0.47U_0402_10V4Z

0.47U_0402_10V4Z
C115

C115

2

Deciphered Date

Deciphered Date

Deciphered Date

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C99

C99

2

1

C116

C116

1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

2

1

C100

C100

2

1

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C117

C117

2

2

U3G

U3G

AG34

VCC_1

AC34

VCC_2

AB34

VCC_3

AA34

VCC_4

Y34

VCC_5

V34

VCC_6

U34

VCC_7

AM33

VCC_8

AK33

VCC_9

AJ33

VCC_10

AG33

VCC_11

AF33

VCC_12

AE33

VCC_13

AC33

VCC_14

AA33

VCC_15

Y33

VCC_16

W33

VCC_17

V33

VCC_18

U33

VCC_19

AH28

VCC_20

AF28

VCC_21

AC28

VCC_22

AA28

VCC_23

AJ26

VCC_24

AG26

VCC_25

AE26

VCC_26

AC26

VCC_27

AH25

VCC_28

AG25

VCC_29

AF25

VCC_30

AG24

VCC_31

AJ23

VCC_32

AH23

VCC_33

AF23

VCC_34

T32

VCC_35

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329
NBR3@

NBR3@

1

Extnal Graphic: 1210.34mA
integrated Graphic: 1930.4mA

VCC CORE

VCC CORE

POWER

POWER

+1.05VS

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8

VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28

VCC NCTF

VCC NCTF

VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

401596

401596

401596

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

of

of

of

11 47Tuesday, May 27, 2008

11 47Tuesday, May 27, 2008

11 47Tuesday, May 27, 2008

1

B

B

B

5

D D

12

Pin AE1

+1.05VS_MPLL+1.05VS+1.05VS_AHPLL+1.05VS

1

C127

C127

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R108

R107

R107

FBMA-L11-160808-121LMT_0603

FBMA-L11-160808-121LMT_0603

C C

C136

C136

10U_0805_10V4Z

10U_0805_10V4Z

PCIe&DMI

+1.5VS

R110 0_0603_5%R110 0_0603_5%

12

1

C126

C126

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Pin AD1

+1.5VS_PEG_BG

1 2

C141

C141

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Pin AD48

1

2

1

2

R108

FBMA-L11-160808-121LMT_0603

FBMA-L11-160808-121LMT_0603

1 2

C138

C138

R109 0.5_0805_1%R109 0.5_0805_1%

10U_0805_10V4Z

10U_0805_10V4Z

+1.05VS_PEGPLL

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C139

C139

2

PCIe&DMI
Pin AA48

C143 change to Poly Cap 20080304

+1.5VS_TVDAC

1 2

+1.5VS

R1072 0_0603_5%R1072 0_0603_5%

10U_0805_10V4Z

10U_0805_10V4Z

C841

C841

1

2

1

C842

C842

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Pin M25

2

New Add_20080221

B B

+1.5VS

R119

R119
0_0603_5%

0_0603_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.01U_0402_25V4Z

0.01U_0402_25V4Z

12

1

C162

C162

2

+1.5VS_QDAC

1

C163

C163

2

TV

Pin L28

Intel Errata.

+1.05VS +1.05VS_DHPLL

R121

R121

1 2
0_0402_5%

0_0402_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.05VS

A A

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

R123

R123

1_0402_1%

1_0402_1%

L1

L1

12

C170

C170

PCIe&DMI

12

10U_0805_10V4Z

10U_0805_10V4Z

5

2

Pin AF1

1

+1.05VS_PEGPLL

C174

C174

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

C173

C173

2

Pin AA47

4

+1.05VS

R112

R112

1 2

0_0805_5%

0_0805_5%

1

+

+

C143

C143

2

220U_D2_4VY_R15M

220U_D2_4VY_R15M

+1.05VS

R115

R115

1 2

0_0603_5%

0_0603_5%

1

C150

C150

C840

C840
10U_0805_10V4Z

10U_0805_10V4Z

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

4

DDR3

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1

C144

C144

2

10U_0805_10V4Z

10U_0805_10V4Z

DDR3

1

C151

C151

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2

3

U3H

U3H

73mA

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

2.68mA

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

AD48

AA48

AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16

AD1

13.2mA

AE1

J48

414uA

J47

50mA

+1.05VS_AHPLL

+1.05VS_PEGPLL

+1.05VS_A_SM

1

C145

C145

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

Pin AR20

+1.05VS_MPLL

+1.5VS_PEG_BG

DDR3:747.5mA

1

C146

C146

2

DDR3:37.95mA

+1.05VS_A_SM_CK

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

2

C152

C152

2

1

Pin AP28

R1073

R1073

1 2

0_0402_5%

0_0402_5%

+1.5VS_TVDAC
+1.5VS_QDAC

+1.05VS_DHPLL

+1.05VS_PEGPLL

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25

AL25

AM24

AL24

AM23

AL23

B24
A24

A32

M25

L28

AF1

60.31mA

AA47

M38

L37

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329
NBR3@

NBR3@

+1.05VS +3VS

3

24mA

VCCA_DPLLB

139.2mA

VCCA_HPLL
VCCA_MPLL

VCCA_LVDS
VSSA_LVDS

VCCA_PEG_BG

VCCA_PEG_PLL

POWER

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9

POWER

26mA

VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8

VCCA_TV_DAC_1
VCCA_TV_DAC_2

VCC_HDA

VCCD_TVDAC
VCCD_QDAC

VCCD_HPLL
VCCD_PEG_PLL

VCCD_LVDS_1
VCCD_LVDS_2

26mA

TVA 24.15mA
TVB 39.48mA
TVX 24.15mA

50mA

58.67mA

48.363mA

157.2mA

HDA

HDA

50mA

D21

D21

2 1

CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

2008/02/20 2009/2/1

2008/02/20 2009/2/1

2008/02/20 2009/2/1

CRTPLLA LVDSA PEG

CRTPLLA LVDSA PEG

VTT

VTT

VCC_AXF_1
VCC_AXF_2

A SM

A SM

VCC_AXF_3

AXF

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

SM CK

VCC_TX_LVDS

A CK

A CK

HV

HV

105.3mA

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

1732mA

TV

TV

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4

DMI PEG

DMI PEG

VTTLF

VTTLF

LVDS D TV/CRT

LVDS D TV/CRT

R1006

R1006

1 2

10_0603_5%

10_0603_5%

Compal Secret Data

Compal Secret Data

Compal Secret Data

852mA

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25

VCC_HV_1
VCC_HV_2
VCC_HV_3

456mA

VTTLF1
VTTLF2
VTTLF3

Deciphered Date

Deciphered Date

Deciphered Date

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

B22
B21
A21

DDR3:149.5mA

BF21
BH20
BG20
BF20

K47

118.8mA

C35
B35
A35

V48
U48
V47
U47
U46

AH48
AF48
AH47
AG47

+NB_VTTLF1

A8

+NB_VTTLF2

L1

+NB_VTTLF3

AB2

0.47U_0402_10V4Z

0.47U_0402_10V4Z

1

C128

C128

0.47U_0402_10V4Z

0.47U_0402_10V4Z
2

+1.05VS_AXF

+1.5V_SM_CK

+3VS

+1.05VS_PEG_DMI

+1.05VS_PEG_DMI

1

C167

C167

2

2

1

C168

C168

0.47U_0402_10V4Z

0.47U_0402_10V4Z
2

2

2

C123

C123

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

1

0.47U_0402_10V4Z

0.47U_0402_10V4Z
C169

C169

2

1

+1.05VS

AGTL+

1

C129

C129

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

2

Intel: VTT 270U*1 ESR 12mOhm

1

C130

C130

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

2

1

+

+

C131

C131
220U_D2_4VY_R15M

220U_D2_4VY_R15M

2

C131 change to Poly Cap 20080304

+1.05VS_AXF

NB I/O

2

C140

C140
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

+1.05VS

R111

R111

1 2

0_0603_5%

0_0603_5%

1

C142

C142

10U_0805_10V4Z

10U_0805_10V4Z
2

Pin B22

+1.5V_SM_CK

1

C147

C147

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

+3VS

1

C158

C158

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Pin C35

2

DDR2

Pin BF21

R114

R114
1_0402_1%

1_0402_1%

C149

C149

1 2

10U_0805_10V4Z

10U_0805_10V4Z

R113

R113

1 2

0_0805_5%

0_0805_5%

1

C148

C148
10U_0805_10V4Z

10U_0805_10V4Z

2

+1.5V

DVT-R120 change to J8 for power rating issue.

+1.05VS_PEG_DMI

1

C164

C164

2

10U_0805_10V4Z

10U_0805_10V4Z

Pin V48

10U_0805_10V4Z@

10U_0805_10V4Z@

PCIe&DMI

1

C165

C165

2

1

+

+

C166

C166

2

220U_D2_4VY_R15M

220U_D2_4VY_R15M

2

+1.05VS

J8

112

JUMP_43X118@J8JUMP_43X118@

C165 change to Poly Cap 20080304

+1.05VS_PEG_DMI

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

401596

401596

401596

Date: Sheet

Date: Sheet

Date: Sheet

PCIe&DMI

1

C171

C171

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

Pin AH48

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

1

of

of

of

12 47Tuesday, May 27, 2008

12 47Tuesday, May 27, 2008

12 47Tuesday, May 27, 2008

B

B

B

5

U3I

U3I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

VSS_8

AD47

VSS_9

AB47

VSS_10

Y47

VSS_11

T47

BD46
BA46
AY46
AV46
AR46

AM46

BF44
AH44
AD44
AA44

M44

BC43
AV43
AU43

AM43

BG42
AY42
AT42
AN42

AJ42

AE42

BD41
AU41

AM41

AH41
AD41
AA41

M41

BG40
BB40
AV40
AN40

AT39

AM39

AJ39

AE39

BH38
BC38
BA38
AU38
AH38
AD38
AA38

BF37
BB37

AW37

AT37
AN37

AJ37

BG36
BD36
AK15
AU36

VSS_12

N47

VSS_13

L47

VSS_14

G47

VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21

V46

VSS_22

R46

VSS_23

P46

VSS_24

H46

VSS_25

F46

VSS_26
VSS_27
VSS_28
VSS_29
VSS_30

Y44

VSS_31

U44

VSS_32

T44

VSS_33
VSS_34

F44

VSS_35
VSS_36
VSS_37
VSS_38
VSS_39

J43

VSS_40

C43

VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47

N42

VSS_48

L42

VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55

Y41

VSS_56

U41

VSS_57

T41

VSS_58
VSS_59

G41

VSS_60

B41

VSS_61
VSS_62
VSS_63
VSS_64
VSS_65

H40

VSS_66

E40

VSS_67
VSS_68
VSS_69
VSS_70
VSS_71

N39

VSS_72

L39

VSS_73

B39

VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81

Y38

VSS_82

U38

VSS_83

T38

VSS_84

J38

VSS_85

F38

VSS_86

C38

VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93

H37

VSS_94

C37

VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

VSS

VSS

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329
NBR3@

NBR3@

D D

C C

B B

A A

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

4

3

U3J

U3J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

VSS_230

M17

VSS_231

H17

VSS_232

C17

VSS_233

BA16

VSS_235

AU16

VSS_237

AN16

VSS_238

N16

VSS_239

K16

VSS_240

G16

VSS_241

E16

VSS_242

BG15

VSS_243

AC15

VSS_244

W15

VSS_245

A15

VSS_246

BG14

VSS_247

AA14

VSS_248

C14

VSS_249

BG13

VSS_250

BC13

VSS_251

BA13

VSS_252

AN13

VSS_255

AJ13

VSS_256

AE13

VSS_257

N13

VSS_258

L13

VSS_259

G13

VSS_260

E13

VSS_261

BF12

VSS_262

AV12

VSS_263

AT12

VSS_264

AM12

VSS_265

AA12

VSS_266

J12

VSS_267

A12

VSS_268

BD11

VSS_269

BB11

VSS_270

AY11

VSS_271

AN11

VSS_272

AH11

VSS_273

Y11

VSS_275

N11

VSS_276

G11

VSS_277

C11

VSS_278

BG10

VSS_279

AV10

VSS_280

AT10

VSS_281

AJ10

VSS_282

AE10

VSS_283

AA10

VSS_284

M10

VSS_285

BF9

VSS_286

BC9

VSS_287

AN9

VSS_288

AM9

VSS_289

AD9

VSS_290

G9

VSS_291

B9

VSS_292

BH8

VSS_293

BB8

VSS_294

AV8

VSS_295

AT8

VSS_296

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329
NBR3@

NBR3@

VSS

VSS

VSS NCTF

VSS NCTF

VSS SCB

VSS SCB

NC

NC

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350

VSS_351
VSS_352
VSS_353
VSS_354

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5

NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

U24
U28
U25
U29

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1
A3

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

2

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/02/20 2009/2/1

2008/02/20 2009/2/1

2008/02/20 2009/2/1

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

401596

401596

401596

B

B

B

of

of

of

13 47Saturday, May 17, 2008

13 47Saturday, May 17, 2008

13 47Saturday, May 17, 2008

1

5

+V_DDR3_DIMM_REF

D D

+V_DDR3_DIMM_REF<15>

C C

B B

A A

+V_DDR3_DIMM_REF

CD47

CD47

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1K_0402_1%

1K_0402_1%

2.2U_0805_16V4Z

2.2U_0805_16V4Z

1

1

2

2

CD1

CD1

+1.5V

12

12

RD1

RD1

RD2

RD2
1K_0402_1%

1K_0402_1%

+V_DDR3_DIMM_REF

DDRA_CKE0<8>

+1.5V +1.5V

DDR_A_BS2<9>

DDRA_CLK0<8>

DDRA_CLK0#<8>

DDR_A_BS0<9>

DDR_A_WE#<9>

DDR_A_CAS#<9>

DDRA_SCS1#<8>

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CD21

CD21

4

JDDR1

JDDR1

VREF_DQ1VSS1

3

DDR_A_D0
DDR_A_D1

DDR_A_DM0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_D9
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11
DDR_A_D16

DDR_A_D17
DDR_A_DQS#2

DDR_A_DQS2
DDR_A_D18

DDR_A_D19
DDR_A_D24

DDR_A_D25
DDR_A_DM3
DDR_A_D26

DDR_A_D27

DDRA_CKE0

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3

DDR_A_MA1
DDRA_CLK0 DDRA_CLK1

DDRA_CLK0# DDRA_CLK1#
DDR_A_MA10

DDR_A_BS0
DDR_A_WE#

DDR_A_MA13
DDRA_SCS1#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49
DDR_A_DQS#6

DDR_A_DQS6

DDR_A_D51
DDR_A_D56

DDR_A_D57
DDR_A_DM7

DDR_A_D59

RD7

RD7

1 2

10K_0402_5%

10K_0402_5%

1

1

CD22

CD22

2

2

RD9

RD9

10K_0402_5%

10K_0402_5%

1 2

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_C-2013289 @

TYCO_C-2013289 @

VSS3

DQS#0

DQS0
VSS6

VSS8
DQ12
DQ13

VSS10

DQ14
DQ15

DQ20
DQ21

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3
DQ30

DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30
VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42
VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

2

DDR_A_D4

4

DQ4
DQ5

DQ6
DQ7

DM1

DM2

A15
A14

A11

A7
A6

A4
A2

A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA
SCL

G2

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_A_D5
DDR_A_DQS#0

DDR_A_DQS0
DDR_A_D6

DDR_A_D7
DDR_A_D12

DDR_A_D13
DDR_A_DM1

SM_DRAMRST#
DDR_A_D14

DDR_A_D15
DDR_A_D20

DDR_A_D21
DDR_A_DM2
DDR_A_D22

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31

RD19 0_0402_5%@RD19 0_0402_5%@

DDRA_CKE1

1 2

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0

DDR_A_BS1
DDR_A_RAS#

DDRA_SCS0#
DDRA_ODT0DDR_A_CAS#

DDRA_ODT1

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53
DDR_A_DM6
DDR_A_D54

DDR_A_D55DDR_A_D50
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62DDR_A_D58

DDR_A_D63
PM_EXTTS#0_1

PM_SMBDATA
PM_SMBCLK

+0.75VS

3

RD3

RD3

1 2

SM_DRAMRST# <8,15>

DDRA_CKE1 <8>

DDRA_CLK1 <8>
DDRA_CLK1# <8>

DDR_A_BS1 <9>
DDR_A_RAS# <9>

DDRA_SCS0# <8>
DDRA_ODT0 <8>

DDRA_ODT1 <8>

0_0402_5%

0_0402_5%

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

+3VS

12

RD6

@RD6

@

PM_SMBDATA <15,16,22,25,26>

PM_SMBCLK <15,16,22,25,26>

DDR_A_DQS#[0..7]<9>
DDR_A_D[0..63]<9>
DDR_A_DM[0..7]<9>
DDR_A_DQS[0..7]<9>
DDR_A_MA[0..14]<9>

2

CD18

CD18

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2.7K_0402_5%

2.7K_0402_5%

CD19

CD19

+V_DDR3_DIMM_REF

1

2

PM_EXTTS#0_1 <8,15>

2

Layout Note:
Place near JDDR1

+1.5V

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

CD4

CD4

CD3

CD3

2

2

Layout Note:
Place near JDDR1.203 & JDDR1.204

+0.75VS

1U_0603_10V4Z

1U_0603_10V4Z

2

1

1

CD5

CD5

2

1U_0603_10V4Z

1U_0603_10V4Z

2

CD13

CD13

1

1

CD6

CD6

2

1U_0603_10V4Z

1U_0603_10V4Z

2

CD14

CD14

1

LPC Debug Port

JDEBUG

JDEBUG

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

ACES_85201-2005@

ACES_85201-2005@

10U_0805_6.3V6M

10U_0805_6.3V6M

CD7

CD7

1U_0603_10V4Z

1U_0603_10V4Z

2

CD15

CD15

1

@ RD4

@

CLK_14M_SIO
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ0#
PLT_RST#

1 2

RD8 0_0402_5%@RD8 0_0402_5%@

SIRQ

10U_0805_6.3V6M

10U_0805_6.3V6M

1

CD8

CD8

2

1

CD17

CD17

CD16

CD16

2

+5VS

RD4

0_0402_5%

0_0402_5%

1

Layout Note: Place these 4 Caps near Command
and Control signals of DIMMA

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

CD9

CD9

1

2

CD10

CD10

CD11

CD11

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
CD12

CD12

1

2

1

+

+

CD2

CD2

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

2

20080305 new add for EMI

+3VS

CLK_PCI_SIO

RD18

RD18

@

@

22_0402_5%

22_0402_5%

1 2
1

CD46 10P_0402_50V8J@CD46 10P_0402_50V8J@

2

CLK_14M_SIO <16>

LPC_AD0 <15,21,32>
LPC_AD1 <15,21,32>
LPC_AD2 <15,21,32>

LPC_AD3 <15,21,32>
LPC_FRAME# <15,21,32>
LPC_DRQ0# <15,21>

PLT_RST# <8,15,17,20,25,26,27,28,32>

CLK_PCI_SIO <16>

SIRQ <15,22,32>

CLK_14M_SIO

@

@

22_0402_5%

22_0402_5%

RD22

RD22

CD48 10P_0402_50V8J@CD48 10P_0402_50V8J@

close to RAM Door

1 2
1

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/02/20 2009/2/1

2008/02/20 2009/2/1

2008/02/20 2009/2/1

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

401596

401596

401596

1

14 47Friday, May 30, 2008

14 47Friday, May 30, 2008

14 47Friday, May 30, 2008

of

of

of

B

B

B

A

+V_DDR3_DIMM_REF

+V_DDR3_DIMM_REF<14>

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1

2 2

3 3

4 4

1

CD23

CD23

2

DDRB_CKE0<8> DDRB_CKE1 <8>

+1.5V +1.5V

DDR_B_BS2<9>

DDRB_CLK0<8>

DDRB_CLK0#<8>

DDR_B_BS0<9>

DDR_B_WE#<9>

DDR_B_CAS#<9>

DDRB_SCS1#<8>

+3VS

CD44

CD44

A

1

CD24

CD24

2

1

2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

DDR_B_D0
DDR_B_D1

DDR_B_DM0
DDR_B_D2

DDR_B_D3
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D10

DDR_B_D11
DDR_B_D16

DDR_B_D17
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D18

DDR_B_D19
DDR_B_D24

DDR_B_D25
DDR_B_DM3
DDR_B_D26

DDR_B_D27

DDRB_CKE0 DDRB_CKE1

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8 DDR_B_MA6

DDR_B_MA5
DDR_B_MA3

DDR_B_MA1
DDRB_CLK0

DDRB_CLK0#
DDR_B_MA10

DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_B_MA13

DDRB_SCS1#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59

RD16

RD16

1 2

10K_0402_5%

10K_0402_5%

1 2

1

RD21

RD21

10K_0402_5%

10K_0402_5%

CD45

CD45

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

JDDR2

JDDR2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17
VSS1849DQ22

51

DQ18
DQ1953VSS19
VSS2055DQ28

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3
A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_C-2013310 @

TYCO_C-2013310 @

B

VSS3

DQS0

VSS6

VSS8
DQ12
DQ13

VSS10

DQ14
DQ15

DQ20
DQ21

DQ23

DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30
VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42
VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

B

C

DDR_B_DQS#[0..7]<9>
DDR_B_D[0..63]<9>

0_0402_5%

0_0402_5%

2.2U_0805_16V4Z

2.2U_0805_16V4Z

1

CD41

CD41

2

DDR_B_DM[0..7]<9>

DDR_B_DQS[0..7]<9>
DDR_B_MA[0..14]<9>

+V_DDR3_DIMM_REF

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

CD42

CD42

2

Layout Note:
Place near JDDR2

+1.5V

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

CD26

CD26

2

Layout Note:
Place near JDDR2.203 & JDDR2.204

+0.75VS

1U_0603_10V4Z

1U_0603_10V4Z

1

CD27

CD27

2

2

CD36

CD36

1

1

CD28

CD28

2

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

2

CD37

CD37

1

New LPC Debug Pad ---- MB side

RD12

RD12

0_0402_5%@

0_0402_5%@

E51_RXD

SIRQ

LPC_AD3

LPC_AD1

LPC_FRAME#

1 2

1 2

RD14

RD14
0_0402_5%

0_0402_5%

E51_RXD<25,32>

SIRQ<14,22,32>

LPC_AD3<14,21,32>

LPC_AD1<14,21,32>

Under DDR ME Assigment Area
Keep Resistor near Debug Pad and in the same side

Reverse side DIMM ---- Pin 1 keep away DIMM

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/02/20 2009/2/1

2008/02/20 2009/2/1

2008/02/20 2009/2/1

Compal Secret Data

Compal Secret Data

Compal Secret Data

2

DDR_B_D4

4

DQ4
DQ5

DQ6
DQ7

DM1

DM2

A15
A14

A7
A6

A4
A2

A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA
SCL

G2

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_B_D5
DDR_B_DQS#0

DDR_B_DQS0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1

SM_DRAMRST#
DDR_B_D14

DDR_B_D15
DDR_B_D20

DDR_B_D21
DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31

RD20 0_0402_5%@RD20 0_0402_5%@

1 2

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7

DDR_B_MA4
DDR_B_MA2

DDR_B_MA0
DDRB_CLK1

DDRB_CLK1#
DDR_B_BS1

DDR_B_RAS#
DDRB_SCS0#

DDRB_ODT0
DDRB_ODT1

DDR_VREF_CA_DIMMB
DDR_B_D36

DDR_B_D37
DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53DDR_B_D49
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63
PM_EXTTS#0_1

PM_SMBDATA
PM_SMBCLK

+0.75VS

SM_DRAMRST# <8,14>

DDRB_CLK1 <8>
DDRB_CLK1# <8>

DDR_B_BS1 <9>
DDR_B_RAS# <9>

DDRB_SCS0# <8>
DDRB_ODT0 <8>

DDRB_ODT1 <8>
RD10

RD10

1 2

PM_EXTTS#0_1 <8,14>

PM_SMBDATA <14,16,22,25,26>

PM_SMBCLK <14,16,22,25,26>

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

CD29

CD29

2

1U_0603_10V4Z

1U_0603_10V4Z

2

2

CD38

CD38

CD39

CD39

1

1

+3VALW

Deciphered Date

Deciphered Date

Deciphered Date

D

1

CD30

CD30

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

CD40

CD40

2

10

D

Layout Note: Place these 4 Caps near Command
and Control signals of DIMMA

0.1U_0402_16V4Z

10U_0805_6.3V6M

10U_0805_6.3V6M

1

CD31

CD31

2

D_PAD1

D_PAD1

7

8

9

0.1U_0402_16V4Z

10U_0805_6.3V6M

10U_0805_6.3V6M

1

2

DEBUG_PAD@

DEBUG_PAD@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CD32

CD32

56

4

3

2

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CD34

CD34

CD33

CD33

1

2

CD35

CD35

1

1

2

2

RD11

RD11

0_0402_5%@

0_0402_5%@

1 2

1 2

RD13

RD13
0_0402_5%

0_0402_5%

PLT_RST#

LPC_AD2

LPC_AD0

CLK_PCI_DDR

RD15

@RD15

@

1 2

10_0402_5%

10_0402_5%

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

401596

401596

401596

Date: Sheet

Date: Sheet

Date: Sheet

E

1

+

+

CD25

CD25

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

2

E51_TXD

LPC_DRQ0#

@

@

1 2

E51_TXD <25,32>

LPC_DRQ0# <14,21>

PLT_RST# <8,14,17,20,25,26,27,28,32>

LPC_AD2 <14,21,32>

LPC_AD0 <14,21,32>

CLK_PCI_DDR <16>LPC_FRAME#<14,21,32>

CD43

CD43

10P_0402_50V8J

10P_0402_50V8J

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

SCHEMATIC, MB A4471

E

B

B

15 47Saturday, May 17, 2008

15 47Saturday, May 17, 2008

15 47Saturday, May 17, 2008

B

of

of

of